diff --git a/CHANGELOG.md b/CHANGELOG.md index c1402c90b..8f695eb44 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,5 +1,22 @@ # Changelog +## Release 525 Entries + +### [525.53] 2022-11-10 + +#### Changed + +- GSP firmware is now distributed as multiple firmware files: this release has `gsp_tu10x.bin` and `gsp_ad10x.bin` replacing `gsp.bin` from previous releases. + - Each file is named after a GPU architecture and supports GPUs from one or more architectures. This allows GSP firmware to better leverage each architecture's capabilities. + - The .run installer will continue to install firmware to `/lib/firmware/nvidia/` and the `nvidia.ko` kernel module will load the appropriate firmware for each GPU at runtime. + +#### Fixed + +- Add support for IBT (indirect branch tracking) on supported platforms, [#256](https://github.com/NVIDIA/open-gpu-kernel-modules/issues/256) by @rnd-ash +- Return EINVAL when [failing to] allocating memory, [#280](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/280) by @YusufKhan-gamedev +- Fix various typos in nvidia/src/kernel, [#16](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/16) by @alexisgeoffrey +- Added support for rotation in X11, Quadro Sync, Stereo, and YUV 4:2:0 on Turing. + ## Release 520 Entries ### [520.56.06] 2022-10-12 @@ -29,6 +46,8 @@ - Improved compatibility with new Linux kernel releases - Fixed possible excessive GPU power draw on an idle X11 or Wayland desktop when driving high resolutions or refresh rates +### [515.65.07] 2022-10-19 + ### [515.65.01] 2022-08-02 #### Fixed diff --git a/README.md b/README.md index cece7290f..6ddd56377 100644 --- a/README.md +++ b/README.md @@ -1,7 +1,7 @@ # NVIDIA Linux Open GPU Kernel Module Source This is the source release of the NVIDIA Linux open GPU kernel modules, -version 520.56.06. +version 525.53. ## How to Build @@ -15,9 +15,9 @@ as root: make modules_install -j$(nproc) -Note that the kernel modules built here must be used with gsp.bin +Note that the kernel modules built here must be used with GSP firmware and user-space NVIDIA GPU driver components from a corresponding -520.56.06 driver release. This can be achieved by installing +525.53 driver release. This can be achieved by installing the NVIDIA GPU driver from the .run file using the `--no-kernel-modules` option. E.g., @@ -167,7 +167,7 @@ for the target kernel. ## Compatible GPUs The open-gpu-kernel-modules can be used on any Turing or later GPU -(see the table below). However, in the 520.56.06 release, +(see the table below). However, in the 525.53 release, GeForce and Workstation support is still considered alpha-quality. To enable use of the open kernel modules on GeForce and Workstation GPUs, @@ -175,7 +175,7 @@ set the "NVreg_OpenRmEnableUnsupportedGpus" nvidia.ko kernel module parameter to 1. For more details, see the NVIDIA GPU driver end user README here: -https://us.download.nvidia.com/XFree86/Linux-x86_64/520.56.06/README/kernel_open.html +https://us.download.nvidia.com/XFree86/Linux-x86_64/525.53/README/kernel_open.html In the below table, if three IDs are listed, the first is the PCI Device ID, the second is the PCI Subsystem Vendor ID, and the third is the PCI @@ -652,6 +652,17 @@ Subsystem Device ID. | NVIDIA PG506-232 | 20B6 10DE 1492 | | NVIDIA A30 | 20B7 10DE 1532 | | NVIDIA A100-PCIE-40GB | 20F1 10DE 145F | +| NVIDIA A800-SXM4-80GB | 20F3 10DE 179B | +| NVIDIA A800-SXM4-80GB | 20F3 10DE 179C | +| NVIDIA A800-SXM4-80GB | 20F3 10DE 179D | +| NVIDIA A800-SXM4-80GB | 20F3 10DE 179E | +| NVIDIA A800-SXM4-80GB | 20F3 10DE 179F | +| NVIDIA A800-SXM4-80GB | 20F3 10DE 17A0 | +| NVIDIA A800-SXM4-80GB | 20F3 10DE 17A1 | +| NVIDIA A800-SXM4-80GB | 20F3 10DE 17A2 | +| NVIDIA A800 80GB PCIe | 20F5 10DE 1799 | +| NVIDIA A800 80GB PCIe LC | 20F5 10DE 179A | +| NVIDIA A800 40GB PCIe | 20F6 10DE 17A3 | | NVIDIA GeForce GTX 1660 Ti | 2182 | | NVIDIA GeForce GTX 1660 | 2184 | | NVIDIA GeForce GTX 1650 SUPER | 2187 | diff --git a/kernel-open/Kbuild b/kernel-open/Kbuild index a329aaee7..4552c6ad9 100644 --- a/kernel-open/Kbuild +++ b/kernel-open/Kbuild @@ -72,7 +72,7 @@ EXTRA_CFLAGS += -I$(src)/common/inc EXTRA_CFLAGS += -I$(src) EXTRA_CFLAGS += -Wall -MD $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-error -Wno-format-extra-args EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM -EXTRA_CFLAGS += -DNV_VERSION_STRING=\"520.56.06\" +EXTRA_CFLAGS += -DNV_VERSION_STRING=\"525.53\" EXTRA_CFLAGS += -Wno-unused-function @@ -229,6 +229,7 @@ NV_HEADER_PRESENCE_TESTS = \ drm/drm_ioctl.h \ drm/drm_device.h \ drm/drm_mode_config.h \ + drm/drm_modeset_lock.h \ dt-bindings/interconnect/tegra_icc_id.h \ generated/autoconf.h \ generated/compile.h \ @@ -243,6 +244,8 @@ NV_HEADER_PRESENCE_TESTS = \ linux/log2.h \ linux/of.h \ linux/bug.h \ + linux/sched.h \ + linux/sched/mm.h \ linux/sched/signal.h \ linux/sched/task.h \ linux/sched/task_stack.h \ @@ -286,7 +289,10 @@ NV_HEADER_PRESENCE_TESTS = \ linux/ioasid.h \ linux/stdarg.h \ linux/iosys-map.h \ - asm/coco.h + asm/coco.h \ + linux/vfio_pci_core.h \ + soc/tegra/bpmp-abi.h \ + soc/tegra/bpmp.h # Filename to store the define for the header in $(1); this is only consumed by # the rule below that concatenates all of these together. diff --git a/kernel-open/common/inc/cpuopsys.h b/kernel-open/common/inc/cpuopsys.h index 9be69fb36..974304194 100644 --- a/kernel-open/common/inc/cpuopsys.h +++ b/kernel-open/common/inc/cpuopsys.h @@ -242,7 +242,7 @@ #endif /* For verification-only features not intended to be included in normal drivers */ -#if (defined(NV_MODS) || defined(NV_GSP_MODS)) && defined(DEBUG) && !defined(DISABLE_VERIF_FEATURES) +#if defined(ENABLE_VERIF_FEATURES) #define NV_VERIF_FEATURES #endif @@ -276,12 +276,6 @@ #define NV_IS_MODS 0 #endif -#if defined(NV_GSP_MODS) -#define NV_IS_GSP_MODS 1 -#else -#define NV_IS_GSP_MODS 0 -#endif - #if defined(NV_WINDOWS) #define NVOS_IS_WINDOWS 1 #else diff --git a/kernel-open/common/inc/nv-firmware.h b/kernel-open/common/inc/nv-firmware.h new file mode 100644 index 000000000..3ddade5b7 --- /dev/null +++ b/kernel-open/common/inc/nv-firmware.h @@ -0,0 +1,132 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NV_FIRMWARE_H +#define NV_FIRMWARE_H + + + +#include +#include + +typedef enum +{ + NV_FIRMWARE_TYPE_GSP, + NV_FIRMWARE_TYPE_GSP_LOG +} nv_firmware_type_t; + +typedef enum +{ + NV_FIRMWARE_CHIP_FAMILY_NULL = 0, + NV_FIRMWARE_CHIP_FAMILY_TU10X = 1, + NV_FIRMWARE_CHIP_FAMILY_TU11X = 2, + NV_FIRMWARE_CHIP_FAMILY_GA100 = 3, + NV_FIRMWARE_CHIP_FAMILY_GA10X = 4, + NV_FIRMWARE_CHIP_FAMILY_AD10X = 5, + NV_FIRMWARE_CHIP_FAMILY_GH100 = 6, + NV_FIRMWARE_CHIP_FAMILY_END, +} nv_firmware_chip_family_t; + +static inline const char *nv_firmware_chip_family_to_string( + nv_firmware_chip_family_t fw_chip_family +) +{ + switch (fw_chip_family) { + case NV_FIRMWARE_CHIP_FAMILY_GH100: return "gh100"; + case NV_FIRMWARE_CHIP_FAMILY_AD10X: return "ad10x"; + case NV_FIRMWARE_CHIP_FAMILY_GA10X: return "ga10x"; + case NV_FIRMWARE_CHIP_FAMILY_GA100: return "ga100"; + case NV_FIRMWARE_CHIP_FAMILY_TU11X: return "tu11x"; + case NV_FIRMWARE_CHIP_FAMILY_TU10X: return "tu10x"; + + case NV_FIRMWARE_CHIP_FAMILY_END: // fall through + case NV_FIRMWARE_CHIP_FAMILY_NULL: + return NULL; + } + return NULL; +} + +// The includer (presumably nv.c) may optionally define +// NV_FIRMWARE_PATH_FOR_FILENAME(filename) +// to return a string "path" given a gsp_*.bin or gsp_log_*.bin filename. +// +// The function nv_firmware_path will then be available. +#if defined(NV_FIRMWARE_PATH_FOR_FILENAME) +static inline const char *nv_firmware_path( + nv_firmware_type_t fw_type, + nv_firmware_chip_family_t fw_chip_family +) +{ + if (fw_type == NV_FIRMWARE_TYPE_GSP) + { + switch (fw_chip_family) + { + case NV_FIRMWARE_CHIP_FAMILY_AD10X: + return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_ad10x.bin"); + + case NV_FIRMWARE_CHIP_FAMILY_GH100: // fall through + case NV_FIRMWARE_CHIP_FAMILY_GA100: // fall through + case NV_FIRMWARE_CHIP_FAMILY_GA10X: // fall through + case NV_FIRMWARE_CHIP_FAMILY_TU11X: // fall through + case NV_FIRMWARE_CHIP_FAMILY_TU10X: + return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_tu10x.bin"); + + case NV_FIRMWARE_CHIP_FAMILY_END: // fall through + case NV_FIRMWARE_CHIP_FAMILY_NULL: + return ""; + } + } + else if (fw_type == NV_FIRMWARE_TYPE_GSP_LOG) + { + switch (fw_chip_family) + { + case NV_FIRMWARE_CHIP_FAMILY_AD10X: + return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_log_ad10x.bin"); + + case NV_FIRMWARE_CHIP_FAMILY_GH100: // fall through + case NV_FIRMWARE_CHIP_FAMILY_GA100: // fall through + case NV_FIRMWARE_CHIP_FAMILY_GA10X: // fall through + case NV_FIRMWARE_CHIP_FAMILY_TU11X: // fall through + case NV_FIRMWARE_CHIP_FAMILY_TU10X: + return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_log_tu10x.bin"); + + case NV_FIRMWARE_CHIP_FAMILY_END: // fall through + case NV_FIRMWARE_CHIP_FAMILY_NULL: + return ""; + } + } + + return ""; +} +#endif // defined(NV_FIRMWARE_PATH_FOR_FILENAME) + +// The includer (presumably nv.c) may optionally define +// NV_FIRMWARE_DECLARE_GSP_FILENAME(filename) +// which will then be invoked (at the top-level) for each +// gsp_*.bin (but not gsp_log_*.bin) +#if defined(NV_FIRMWARE_DECLARE_GSP_FILENAME) +NV_FIRMWARE_DECLARE_GSP_FILENAME("gsp_ad10x.bin") +NV_FIRMWARE_DECLARE_GSP_FILENAME("gsp_tu10x.bin") +#endif // defined(NV_FIRMWARE_DECLARE_GSP_FILENAME) + +#endif // NV_FIRMWARE_DECLARE_GSP_FILENAME diff --git a/kernel-open/common/inc/nv-hash.h b/kernel-open/common/inc/nv-hash.h index 97dbb5ddc..0405f0a1d 100644 --- a/kernel-open/common/inc/nv-hash.h +++ b/kernel-open/common/inc/nv-hash.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-22 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -91,6 +91,6 @@ static inline void _nv_hash_init(struct hlist_head *ht, unsigned int sz) * @key: the key of the objects to iterate over */ #define nv_hash_for_each_possible(name, obj, member, key) \ - nv_hlist_for_each_entry(obj, &name[NV_HASH_MIN(key, NV_HASH_BITS(name))], member) + hlist_for_each_entry(obj, &name[NV_HASH_MIN(key, NV_HASH_BITS(name))], member) #endif // __NV_HASH_H__ diff --git a/kernel-open/common/inc/nv-hypervisor.h b/kernel-open/common/inc/nv-hypervisor.h index ddc6a9134..6ee37f76c 100644 --- a/kernel-open/common/inc/nv-hypervisor.h +++ b/kernel-open/common/inc/nv-hypervisor.h @@ -27,15 +27,13 @@ #include // Enums for supported hypervisor types. -// New hypervisor type should be added before OS_HYPERVISOR_CUSTOM_FORCED +// New hypervisor type should be added before OS_HYPERVISOR_UNKNOWN typedef enum _HYPERVISOR_TYPE { OS_HYPERVISOR_XEN = 0, OS_HYPERVISOR_VMWARE, OS_HYPERVISOR_HYPERV, OS_HYPERVISOR_KVM, - OS_HYPERVISOR_PARALLELS, - OS_HYPERVISOR_CUSTOM_FORCED, OS_HYPERVISOR_UNKNOWN } HYPERVISOR_TYPE; diff --git a/kernel-open/common/inc/nv-kthread-q.h b/kernel-open/common/inc/nv-kthread-q.h index 82a8a6b8a..991a1d957 100644 --- a/kernel-open/common/inc/nv-kthread-q.h +++ b/kernel-open/common/inc/nv-kthread-q.h @@ -115,11 +115,6 @@ struct nv_kthread_q_item void *function_args; }; -#if defined(NV_KTHREAD_CREATE_ON_NODE_PRESENT) - #define NV_KTHREAD_Q_SUPPORTS_AFFINITY() 1 -#else - #define NV_KTHREAD_Q_SUPPORTS_AFFINITY() 0 -#endif #ifndef NUMA_NO_NODE #define NUMA_NO_NODE (-1) @@ -142,18 +137,12 @@ struct nv_kthread_q_item // // A short prefix of the qname arg will show up in []'s, via the ps(1) utility. // -// The kernel thread stack is preferably allocated on the specified NUMA node if -// NUMA-affinity (NV_KTHREAD_Q_SUPPORTS_AFFINITY() == 1) is supported, but -// fallback to another node is possible because kernel allocators do not +// The kernel thread stack is preferably allocated on the specified NUMA node, +// but fallback to another node is possible because kernel allocators do not // guarantee affinity. Note that NUMA-affinity applies only to // the kthread stack. This API does not do anything about limiting the CPU // affinity of the kthread. That is left to the caller. // -// On kernels, which do not support NUMA-aware kthread stack allocations -// (NV_KTHTREAD_Q_SUPPORTS_AFFINITY() == 0), the API will return -ENOTSUPP -// if the value supplied for 'preferred_node' is anything other than -// NV_KTHREAD_NO_NODE. -// // Reusing a queue: once a queue is initialized, it must be safely shut down // (see "Stopping the queue(s)", below), before it can be reused. So, for // a simple queue use case, the following will work: diff --git a/kernel-open/common/inc/nv-linux.h b/kernel-open/common/inc/nv-linux.h index e3ac4d519..792287b3e 100644 --- a/kernel-open/common/inc/nv-linux.h +++ b/kernel-open/common/inc/nv-linux.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -191,13 +191,6 @@ */ #define NV_CURRENT_EUID() (__kuid_val(current->cred->euid)) -#if !defined(NV_KUID_T_PRESENT) -static inline uid_t __kuid_val(uid_t uid) -{ - return uid; -} -#endif - #if defined(CONFIG_VGA_ARB) #include #endif @@ -234,18 +227,6 @@ static inline uid_t __kuid_val(uid_t uid) #include #endif -#if defined(NV_EFI_ENABLED_PRESENT) && defined(NV_EFI_ENABLED_ARGUMENT_COUNT) -#if (NV_EFI_ENABLED_ARGUMENT_COUNT == 1) -#define NV_EFI_ENABLED() efi_enabled(EFI_BOOT) -#else -#error "NV_EFI_ENABLED_ARGUMENT_COUNT value unrecognized!" -#endif -#elif (defined(NV_EFI_ENABLED_PRESENT) || defined(efi_enabled)) -#define NV_EFI_ENABLED() efi_enabled -#else -#define NV_EFI_ENABLED() 0 -#endif - #if defined(CONFIG_CRAY_XT) #include NV_STATUS nvos_forward_error_to_cray(struct pci_dev *, NvU32, @@ -521,7 +502,7 @@ static inline void *nv_vmalloc(unsigned long size) return ptr; } -static inline void nv_vfree(void *ptr, NvU32 size) +static inline void nv_vfree(void *ptr, NvU64 size) { NV_MEMDBG_REMOVE(ptr, size); vfree(ptr); @@ -592,11 +573,7 @@ static NvBool nv_numa_node_has_memory(int node_id) { if (node_id < 0 || node_id >= MAX_NUMNODES) return NV_FALSE; -#if defined(NV_NODE_STATES_N_MEMORY_PRESENT) return node_state(node_id, N_MEMORY) ? NV_TRUE : NV_FALSE; -#else - return node_state(node_id, N_HIGH_MEMORY) ? NV_TRUE : NV_FALSE; -#endif } #define NV_KMALLOC(ptr, size) \ @@ -606,6 +583,13 @@ static NvBool nv_numa_node_has_memory(int node_id) NV_MEMDBG_ADD(ptr, size); \ } +#define NV_KZALLOC(ptr, size) \ + { \ + (ptr) = kzalloc(size, NV_GFP_KERNEL); \ + if (ptr) \ + NV_MEMDBG_ADD(ptr, size); \ + } + #define NV_KMALLOC_ATOMIC(ptr, size) \ { \ (ptr) = kmalloc(size, NV_GFP_ATOMIC); \ @@ -838,10 +822,8 @@ static inline dma_addr_t nv_phys_to_dma(struct device *dev, NvU64 pa) }) #endif -#if defined(NV_PCI_STOP_AND_REMOVE_BUS_DEVICE_PRESENT) // introduced in 3.4.9 +#if defined(NV_PCI_STOP_AND_REMOVE_BUS_DEVICE_PRESENT) // introduced in 3.18-rc1 for aarch64 #define NV_PCI_STOP_AND_REMOVE_BUS_DEVICE(pci_dev) pci_stop_and_remove_bus_device(pci_dev) -#elif defined(NV_PCI_REMOVE_BUS_DEVICE_PRESENT) // introduced in 2.6 -#define NV_PCI_STOP_AND_REMOVE_BUS_DEVICE(pci_dev) pci_remove_bus_device(pci_dev) #endif #define NV_PRINT_AT(nv_debug_level,at) \ @@ -1139,11 +1121,14 @@ static inline int nv_kmem_cache_alloc_stack(nvidia_stack_t **stack) { nvidia_stack_t *sp = NULL; #if defined(NVCPU_X86_64) - sp = NV_KMEM_CACHE_ALLOC(nvidia_stack_t_cache); - if (sp == NULL) - return -ENOMEM; - sp->size = sizeof(sp->stack); - sp->top = sp->stack + sp->size; + if (rm_is_altstack_in_use()) + { + sp = NV_KMEM_CACHE_ALLOC(nvidia_stack_t_cache); + if (sp == NULL) + return -ENOMEM; + sp->size = sizeof(sp->stack); + sp->top = sp->stack + sp->size; + } #endif *stack = sp; return 0; @@ -1152,7 +1137,7 @@ static inline int nv_kmem_cache_alloc_stack(nvidia_stack_t **stack) static inline void nv_kmem_cache_free_stack(nvidia_stack_t *stack) { #if defined(NVCPU_X86_64) - if (stack != NULL) + if (stack != NULL && rm_is_altstack_in_use()) { NV_KMEM_CACHE_FREE(stack, nvidia_stack_t_cache); } @@ -1386,8 +1371,7 @@ typedef struct nv_dma_map_s { * xen_swiotlb_map_sg_attrs may try to route to the SWIOTLB. We must only use * single-page sg elements on Xen Server. */ -#if defined(NV_SG_ALLOC_TABLE_FROM_PAGES_PRESENT) && \ - !defined(NV_DOM0_KERNEL_PRESENT) +#if !defined(NV_DOM0_KERNEL_PRESENT) #define NV_ALLOC_DMA_SUBMAP_SCATTERLIST(dm, sm, i) \ ((sg_alloc_table_from_pages(&sm->sgt, \ &dm->pages[NV_DMA_SUBMAP_IDX_TO_PAGE_IDX(i)], \ @@ -1667,6 +1651,27 @@ static inline nv_linux_file_private_t *nv_get_nvlfp_from_nvfp(nv_file_private_t #define NV_STATE_PTR(nvl) &(((nv_linux_state_t *)(nvl))->nv_state) +static inline nvidia_stack_t *nv_nvlfp_get_sp(nv_linux_file_private_t *nvlfp, nvidia_entry_point_index_t which) +{ +#if defined(NVCPU_X86_64) + if (rm_is_altstack_in_use()) + { + down(&nvlfp->fops_sp_lock[which]); + return nvlfp->fops_sp[which]; + } +#endif + return NULL; +} + +static inline void nv_nvlfp_put_sp(nv_linux_file_private_t *nvlfp, nvidia_entry_point_index_t which) +{ +#if defined(NVCPU_X86_64) + if (rm_is_altstack_in_use()) + { + up(&nvlfp->fops_sp_lock[which]); + } +#endif +} #define NV_ATOMIC_READ(data) atomic_read(&(data)) #define NV_ATOMIC_SET(data,val) atomic_set(&(data), (val)) @@ -1895,20 +1900,12 @@ static inline NvU32 nv_default_irq_flags(nv_state_t *nv) #define NV_GET_UNUSED_FD_FLAGS(flags) (-1) #endif -#if defined(NV_SET_CLOSE_ON_EXEC_PRESENT) - #define NV_SET_CLOSE_ON_EXEC(fd, fdt) __set_close_on_exec(fd, fdt) -#elif defined(NV_LINUX_TIME_H_PRESENT) && defined(FD_SET) - #define NV_SET_CLOSE_ON_EXEC(fd, fdt) FD_SET(fd, fdt->close_on_exec) -#else - #define NV_SET_CLOSE_ON_EXEC(fd, fdt) __set_bit(fd, fdt->close_on_exec) -#endif - #define MODULE_BASE_NAME "nvidia" #define MODULE_INSTANCE_NUMBER 0 #define MODULE_INSTANCE_STRING "" #define MODULE_NAME MODULE_BASE_NAME MODULE_INSTANCE_STRING -NvS32 nv_request_soc_irq(nv_linux_state_t *, NvU32, nv_soc_irq_type_t, NvU32, NvU32); +NvS32 nv_request_soc_irq(nv_linux_state_t *, NvU32, nv_soc_irq_type_t, NvU32, NvU32, const char*); static inline void nv_mutex_destroy(struct mutex *lock) { diff --git a/kernel-open/common/inc/nv-list-helpers.h b/kernel-open/common/inc/nv-list-helpers.h index a241d358d..15d51d2bc 100644 --- a/kernel-open/common/inc/nv-list-helpers.h +++ b/kernel-open/common/inc/nv-list-helpers.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -73,21 +73,4 @@ } #endif -#if defined(NV_HLIST_FOR_EACH_ENTRY_ARGUMENT_COUNT) -#if NV_HLIST_FOR_EACH_ENTRY_ARGUMENT_COUNT == 3 -#define nv_hlist_for_each_entry(pos, head, member) \ - hlist_for_each_entry(pos, head, member) -#else -#if !defined(hlist_entry_safe) -#define hlist_entry_safe(ptr, type, member) \ - (ptr) ? hlist_entry(ptr, type, member) : NULL -#endif - -#define nv_hlist_for_each_entry(pos, head, member) \ - for (pos = hlist_entry_safe((head)->first, typeof(*(pos)), member); \ - pos; \ - pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member)) -#endif -#endif // NV_HLIST_FOR_EACH_ENTRY_ARGUMENT_COUNT - #endif // __NV_LIST_HELPERS_H__ diff --git a/kernel-open/common/inc/nv-mm.h b/kernel-open/common/inc/nv-mm.h index 21ad97c9a..44b2bdc3c 100644 --- a/kernel-open/common/inc/nv-mm.h +++ b/kernel-open/common/inc/nv-mm.h @@ -29,6 +29,25 @@ typedef int vm_fault_t; #endif +/* pin_user_pages + * Presence of pin_user_pages() also implies the presence of unpin-user_page(). + * Both were added in the v5.6-rc1 + * + * pin_user_pages() was added by commit eddb1c228f7951d399240 + * ("mm/gup: introduce pin_user_pages*() and FOLL_PIN") in v5.6-rc1 (2020-01-30) + * + */ + +#include +#include +#if defined(NV_PIN_USER_PAGES_PRESENT) + #define NV_PIN_USER_PAGES pin_user_pages + #define NV_UNPIN_USER_PAGE unpin_user_page +#else + #define NV_PIN_USER_PAGES NV_GET_USER_PAGES + #define NV_UNPIN_USER_PAGE put_page +#endif // NV_PIN_USER_PAGES_PRESENT + /* get_user_pages * * The 8-argument version of get_user_pages was deprecated by commit @@ -47,51 +66,57 @@ typedef int vm_fault_t; * */ -#if defined(NV_GET_USER_PAGES_HAS_ARGS_WRITE_FORCE) +#if defined(NV_GET_USER_PAGES_HAS_ARGS_FLAGS) #define NV_GET_USER_PAGES get_user_pages -#elif defined(NV_GET_USER_PAGES_HAS_ARGS_TSK_WRITE_FORCE) - #define NV_GET_USER_PAGES(start, nr_pages, write, force, pages, vmas) \ - get_user_pages(current, current->mm, start, nr_pages, write, force, pages, vmas) +#elif defined(NV_GET_USER_PAGES_HAS_ARGS_TSK_FLAGS) + #define NV_GET_USER_PAGES(start, nr_pages, flags, pages, vmas) \ + get_user_pages(current, current->mm, start, nr_pages, flags, pages, vmas) #else - #include - #include - static inline long NV_GET_USER_PAGES(unsigned long start, unsigned long nr_pages, - int write, - int force, + unsigned int flags, struct page **pages, struct vm_area_struct **vmas) { - unsigned int flags = 0; + int write = flags & FOLL_WRITE; + int force = flags & FOLL_FORCE; - if (write) - flags |= FOLL_WRITE; - if (force) - flags |= FOLL_FORCE; - - #if defined(NV_GET_USER_PAGES_HAS_ARGS_TSK_FLAGS) - return get_user_pages(current, current->mm, start, nr_pages, flags, - pages, vmas); + #if defined(NV_GET_USER_PAGES_HAS_ARGS_WRITE_FORCE) + return get_user_pages(start, nr_pages, write, force, pages, vmas); #else - // remaining defination(NV_GET_USER_PAGES_HAS_ARGS_FLAGS) - return get_user_pages(start, nr_pages, flags, pages, vmas); - #endif + // NV_GET_USER_PAGES_HAS_ARGS_TSK_WRITE_FORCE + return get_user_pages(current, current->mm, start, nr_pages, write, + force, pages, vmas); + #endif // NV_GET_USER_PAGES_HAS_ARGS_WRITE_FORCE } -#endif +#endif // NV_GET_USER_PAGES_HAS_ARGS_FLAGS + +/* pin_user_pages_remote + * + * pin_user_pages_remote() was added by commit eddb1c228f7951d399240 + * ("mm/gup: introduce pin_user_pages*() and FOLL_PIN") in v5.6 (2020-01-30) + * + * pin_user_pages_remote() removed 'tsk' parameter by commit + * 64019a2e467a ("mm/gup: remove task_struct pointer for all gup code") + * in v5.9-rc1 (2020-08-11). * + * + */ + +#if defined(NV_PIN_USER_PAGES_REMOTE_PRESENT) + #if defined (NV_PIN_USER_PAGES_REMOTE_HAS_ARGS_TSK) + #define NV_PIN_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, vmas, locked) \ + pin_user_pages_remote(NULL, mm, start, nr_pages, flags, pages, vmas, locked) + #else + #define NV_PIN_USER_PAGES_REMOTE pin_user_pages_remote + #endif // NV_PIN_USER_PAGES_REMOTE_HAS_ARGS_TSK +#else + #define NV_PIN_USER_PAGES_REMOTE NV_GET_USER_PAGES_REMOTE +#endif // NV_PIN_USER_PAGES_REMOTE_PRESENT /* * get_user_pages_remote() was added by commit 1e9877902dc7 * ("mm/gup: Introduce get_user_pages_remote()") in v4.6 (2016-02-12). * - * The very next commit cde70140fed8 ("mm/gup: Overload get_user_pages() - * functions") deprecated the 8-argument version of get_user_pages for the - * non-remote case (calling get_user_pages with current and current->mm). - * - * The guidelines are: call NV_GET_USER_PAGES_REMOTE if you need the 8-argument - * version that uses something other than current and current->mm. Use - * NV_GET_USER_PAGES if you are refering to current and current->mm. - * * Note that get_user_pages_remote() requires the caller to hold a reference on * the task_struct (if non-NULL and if this API has tsk argument) and the mm_struct. * This will always be true when using current and current->mm. If the kernel passes @@ -113,66 +138,55 @@ typedef int vm_fault_t; */ #if defined(NV_GET_USER_PAGES_REMOTE_PRESENT) - #if defined(NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_WRITE_FORCE) - #define NV_GET_USER_PAGES_REMOTE get_user_pages_remote + #if defined(NV_GET_USER_PAGES_REMOTE_HAS_ARGS_FLAGS_LOCKED) + #define NV_GET_USER_PAGES_REMOTE get_user_pages_remote + + #elif defined(NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS_LOCKED) + #define NV_GET_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, vmas, locked) \ + get_user_pages_remote(NULL, mm, start, nr_pages, flags, pages, vmas, locked) + + #elif defined(NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS) + #define NV_GET_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, vmas, locked) \ + get_user_pages_remote(NULL, mm, start, nr_pages, flags, pages, vmas) + #else - static inline long NV_GET_USER_PAGES_REMOTE(struct task_struct *tsk, - struct mm_struct *mm, + // NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_WRITE_FORCE + static inline long NV_GET_USER_PAGES_REMOTE(struct mm_struct *mm, unsigned long start, unsigned long nr_pages, - int write, - int force, + unsigned int flags, struct page **pages, - struct vm_area_struct **vmas) + struct vm_area_struct **vmas, + int *locked) { - unsigned int flags = 0; + int write = flags & FOLL_WRITE; + int force = flags & FOLL_FORCE; - if (write) - flags |= FOLL_WRITE; - if (force) - flags |= FOLL_FORCE; - - #if defined(NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS) - return get_user_pages_remote(tsk, mm, start, nr_pages, flags, + return get_user_pages_remote(NULL, mm, start, nr_pages, write, force, pages, vmas); - #elif defined(NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS_LOCKED) - return get_user_pages_remote(tsk, mm, start, nr_pages, flags, - pages, vmas, NULL); - #else - // remaining defined(NV_GET_USER_PAGES_REMOTE_HAS_ARGS_FLAGS_LOCKED) - return get_user_pages_remote(mm, start, nr_pages, flags, - pages, vmas, NULL); - #endif } - #endif + #endif // NV_GET_USER_PAGES_REMOTE_HAS_ARGS_FLAGS_LOCKED #else #if defined(NV_GET_USER_PAGES_HAS_ARGS_TSK_WRITE_FORCE) - #define NV_GET_USER_PAGES_REMOTE get_user_pages - #else - #include - #include - - static inline long NV_GET_USER_PAGES_REMOTE(struct task_struct *tsk, - struct mm_struct *mm, + static inline long NV_GET_USER_PAGES_REMOTE(struct mm_struct *mm, unsigned long start, unsigned long nr_pages, - int write, - int force, + unsigned int flags, struct page **pages, - struct vm_area_struct **vmas) + struct vm_area_struct **vmas, + int *locked) { - unsigned int flags = 0; + int write = flags & FOLL_WRITE; + int force = flags & FOLL_FORCE; - if (write) - flags |= FOLL_WRITE; - if (force) - flags |= FOLL_FORCE; - - return get_user_pages(tsk, mm, start, nr_pages, flags, pages, vmas); + return get_user_pages(NULL, mm, start, nr_pages, write, force, pages, vmas); } - #endif -#endif + #else + #define NV_GET_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, vmas, locked) \ + get_user_pages(NULL, mm, start, nr_pages, flags, pages, vmas) + #endif // NV_GET_USER_PAGES_HAS_ARGS_TSK_WRITE_FORCE +#endif // NV_GET_USER_PAGES_REMOTE_PRESENT /* * The .virtual_address field was effectively renamed to .address, by these diff --git a/kernel-open/common/inc/nv-pci.h b/kernel-open/common/inc/nv-pci.h index 84c0f5d93..ba33fdb01 100644 --- a/kernel-open/common/inc/nv-pci.h +++ b/kernel-open/common/inc/nv-pci.h @@ -27,17 +27,6 @@ #include #include "nv-linux.h" -#if defined(NV_DEV_IS_PCI_PRESENT) -#define nv_dev_is_pci(dev) dev_is_pci(dev) -#else -/* - * Non-PCI devices are only supported on kernels which expose the - * dev_is_pci() function. For older kernels, we only support PCI - * devices, hence returning true to take all the PCI code paths. - */ -#define nv_dev_is_pci(dev) (true) -#endif - int nv_pci_register_driver(void); void nv_pci_unregister_driver(void); int nv_pci_count_devices(void); diff --git a/kernel-open/common/inc/nv-pgprot.h b/kernel-open/common/inc/nv-pgprot.h index b56d95611..581e97f3a 100644 --- a/kernel-open/common/inc/nv-pgprot.h +++ b/kernel-open/common/inc/nv-pgprot.h @@ -78,13 +78,8 @@ static inline pgprot_t pgprot_modify_writecombine(pgprot_t old_prot) #define NV_PGPROT_UNCACHED_DEVICE(old_prot) pgprot_noncached(old_prot) #if defined(NVCPU_AARCH64) -#if defined(NV_MT_DEVICE_GRE_PRESENT) -#define NV_PROT_WRITE_COMBINED_DEVICE (PROT_DEFAULT | PTE_PXN | PTE_UXN | \ - PTE_ATTRINDX(MT_DEVICE_GRE)) -#else #define NV_PROT_WRITE_COMBINED_DEVICE (PROT_DEFAULT | PTE_PXN | PTE_UXN | \ PTE_ATTRINDX(MT_DEVICE_nGnRE)) -#endif #define NV_PGPROT_WRITE_COMBINED_DEVICE(old_prot) \ __pgprot_modify(old_prot, PTE_ATTRINDX_MASK, NV_PROT_WRITE_COMBINED_DEVICE) #define NV_PGPROT_WRITE_COMBINED(old_prot) NV_PGPROT_UNCACHED(old_prot) diff --git a/kernel-open/common/inc/nv-procfs-utils.h b/kernel-open/common/inc/nv-procfs-utils.h index 5911d2d44..c4035ec4f 100644 --- a/kernel-open/common/inc/nv-procfs-utils.h +++ b/kernel-open/common/inc/nv-procfs-utils.h @@ -74,21 +74,8 @@ typedef struct file_operations nv_proc_ops_t; __entry; \ }) -/* - * proc_mkdir_mode exists in Linux 2.6.9, but isn't exported until Linux 3.0. - * Use the older interface instead unless the newer interface is necessary. - */ -#if defined(NV_PROC_REMOVE_PRESENT) # define NV_PROC_MKDIR_MODE(name, mode, parent) \ proc_mkdir_mode(name, mode, parent) -#else -# define NV_PROC_MKDIR_MODE(name, mode, parent) \ - ({ \ - struct proc_dir_entry *__entry; \ - __entry = create_proc_entry(name, mode, parent); \ - __entry; \ - }) -#endif #define NV_CREATE_PROC_DIR(name,parent) \ ({ \ @@ -104,16 +91,6 @@ typedef struct file_operations nv_proc_ops_t; #define NV_PDE_DATA(inode) PDE_DATA(inode) #endif -#if defined(NV_PROC_REMOVE_PRESENT) -# define NV_REMOVE_PROC_ENTRY(entry) \ - proc_remove(entry); -#else -# define NV_REMOVE_PROC_ENTRY(entry) \ - remove_proc_entry(entry->name, entry->parent); -#endif - -void nv_procfs_unregister_all(struct proc_dir_entry *entry, - struct proc_dir_entry *delimiter); #define NV_DEFINE_SINGLE_PROCFS_FILE_HELPER(name, lock) \ static int nv_procfs_open_##name( \ struct inode *inode, \ diff --git a/kernel-open/common/inc/nv-proto.h b/kernel-open/common/inc/nv-proto.h index b7434ccef..815107d25 100644 --- a/kernel-open/common/inc/nv-proto.h +++ b/kernel-open/common/inc/nv-proto.h @@ -54,8 +54,6 @@ void nv_free_contig_pages (nv_alloc_t *); NV_STATUS nv_alloc_system_pages (nv_state_t *, nv_alloc_t *); void nv_free_system_pages (nv_alloc_t *); -void nv_address_space_init_once (struct address_space *mapping); - int nv_uvm_init (void); void nv_uvm_exit (void); NV_STATUS nv_uvm_suspend (void); diff --git a/kernel-open/common/inc/nv.h b/kernel-open/common/inc/nv.h index 8537ec962..794dc7d27 100644 --- a/kernel-open/common/inc/nv.h +++ b/kernel-open/common/inc/nv.h @@ -40,6 +40,7 @@ #include #include "nv_stdarg.h" #include +#include #include #include @@ -160,8 +161,14 @@ typedef enum _TEGRASOC_WHICH_CLK TEGRASOC_WHICH_CLK_MAUD, TEGRASOC_WHICH_CLK_AZA_2XBIT, TEGRASOC_WHICH_CLK_AZA_BIT, - TEGRA234_CLK_MIPI_CAL, - TEGRA234_CLK_UART_FST_MIPI_CAL, + TEGRASOC_WHICH_CLK_MIPI_CAL, + TEGRASOC_WHICH_CLK_UART_FST_MIPI_CAL, + TEGRASOC_WHICH_CLK_SOR0_DIV, + TEGRASOC_WHICH_CLK_DISP_ROOT, + TEGRASOC_WHICH_CLK_HUB_ROOT, + TEGRASOC_WHICH_CLK_PLLA_DISP, + TEGRASOC_WHICH_CLK_PLLA_DISPHUB, + TEGRASOC_WHICH_CLK_PLLA, TEGRASOC_WHICH_CLK_MAX, // TEGRASOC_WHICH_CLK_MAX is defined for boundary checks only. } TEGRASOC_WHICH_CLK; @@ -304,7 +311,7 @@ typedef struct nv_alloc_mapping_context_s { typedef enum { - NV_SOC_IRQ_DISPLAY_TYPE, + NV_SOC_IRQ_DISPLAY_TYPE = 0x1, NV_SOC_IRQ_DPAUX_TYPE, NV_SOC_IRQ_GPIO_TYPE, NV_SOC_IRQ_HDACODEC_TYPE, @@ -368,6 +375,7 @@ typedef struct nv_state_t nv_aperture_t *mipical_regs; nv_aperture_t *fb, ud; nv_aperture_t *simregs; + nv_aperture_t *emc_regs; NvU32 num_dpaux_instance; NvU32 interrupt_line; @@ -430,9 +438,6 @@ typedef struct nv_state_t /* Variable to force allocation of 32-bit addressable memory */ NvBool force_dma32_alloc; - /* Variable to track if device has entered dynamic power state */ - NvBool dynamic_power_entered; - /* PCI power state should be D0 during system suspend */ NvBool d0_state_in_suspend; @@ -465,6 +470,9 @@ typedef struct nv_state_t /* Check if NVPCF DSM function is implemented under NVPCF or GPU device scope */ NvBool nvpcf_dsm_in_gpu_scope; + /* Bool to check if the device received a shutdown notification */ + NvBool is_shutdown; + } nv_state_t; // These define need to be in sync with defines in system.h @@ -473,6 +481,10 @@ typedef struct nv_state_t #define OS_TYPE_SUNOS 0x3 #define OS_TYPE_VMWARE 0x4 +#define NVFP_TYPE_NONE 0x0 +#define NVFP_TYPE_REFCOUNTED 0x1 +#define NVFP_TYPE_REGISTERED 0x2 + struct nv_file_private_t { NvHandle *handles; @@ -482,6 +494,7 @@ struct nv_file_private_t nv_file_private_t *ctl_nvfp; void *ctl_nvfp_priv; + NvU32 register_or_refcount; }; // Forward define the gpu ops structures @@ -513,8 +526,9 @@ typedef struct UvmGpuChannelResourceBindParams_tag *nvgpuChannelResourceBindPar typedef struct UvmGpuPagingChannelAllocParams_tag nvgpuPagingChannelAllocParams_t; typedef struct UvmGpuPagingChannel_tag *nvgpuPagingChannelHandle_t; typedef struct UvmGpuPagingChannelInfo_tag *nvgpuPagingChannelInfo_t; -typedef NV_STATUS (*nvPmaEvictPagesCallback)(void *, NvU32, NvU64 *, NvU32, NvU64, NvU64); -typedef NV_STATUS (*nvPmaEvictRangeCallback)(void *, NvU64, NvU64); +typedef enum UvmPmaGpuMemoryType_tag nvgpuGpuMemoryType_t; +typedef NV_STATUS (*nvPmaEvictPagesCallback)(void *, NvU32, NvU64 *, NvU32, NvU64, NvU64, nvgpuGpuMemoryType_t); +typedef NV_STATUS (*nvPmaEvictRangeCallback)(void *, NvU64, NvU64, nvgpuGpuMemoryType_t); /* * flags @@ -566,12 +580,6 @@ typedef enum NV_POWER_STATE_RUNNING } nv_power_state_t; -typedef enum -{ - NV_FIRMWARE_GSP, - NV_FIRMWARE_GSP_LOG -} nv_firmware_t; - #define NV_PRIMARY_VGA(nv) ((nv)->primary_vga) #define NV_IS_CTL_DEVICE(nv) ((nv)->flags & NV_FLAG_CONTROL) @@ -587,12 +595,6 @@ typedef enum #define NV_SOC_IS_ISO_IOMMU_PRESENT(nv) \ ((nv)->iso_iommu_present) -/* - * NVIDIA ACPI event ID to be passed into the core NVIDIA driver for - * AC/DC event. - */ -#define NV_SYSTEM_ACPI_BATTERY_POWER_EVENT 0x8002 - /* * GPU add/remove events */ @@ -604,8 +606,6 @@ typedef enum * to core NVIDIA driver for ACPI events. */ #define NV_SYSTEM_ACPI_EVENT_VALUE_DISPLAY_SWITCH_DEFAULT 0 -#define NV_SYSTEM_ACPI_EVENT_VALUE_POWER_EVENT_AC 0 -#define NV_SYSTEM_ACPI_EVENT_VALUE_POWER_EVENT_BATTERY 1 #define NV_SYSTEM_ACPI_EVENT_VALUE_DOCK_EVENT_UNDOCKED 0 #define NV_SYSTEM_ACPI_EVENT_VALUE_DOCK_EVENT_DOCKED 1 @@ -616,14 +616,18 @@ typedef enum #define NV_EVAL_ACPI_METHOD_NVIF 0x01 #define NV_EVAL_ACPI_METHOD_WMMX 0x02 -#define NV_I2C_CMD_READ 1 -#define NV_I2C_CMD_WRITE 2 -#define NV_I2C_CMD_SMBUS_READ 3 -#define NV_I2C_CMD_SMBUS_WRITE 4 -#define NV_I2C_CMD_SMBUS_QUICK_WRITE 5 -#define NV_I2C_CMD_SMBUS_QUICK_READ 6 -#define NV_I2C_CMD_SMBUS_BLOCK_READ 7 -#define NV_I2C_CMD_SMBUS_BLOCK_WRITE 8 +typedef enum { + NV_I2C_CMD_READ = 1, + NV_I2C_CMD_WRITE, + NV_I2C_CMD_SMBUS_READ, + NV_I2C_CMD_SMBUS_WRITE, + NV_I2C_CMD_SMBUS_QUICK_WRITE, + NV_I2C_CMD_SMBUS_QUICK_READ, + NV_I2C_CMD_SMBUS_BLOCK_READ, + NV_I2C_CMD_SMBUS_BLOCK_WRITE, + NV_I2C_CMD_BLOCK_READ, + NV_I2C_CMD_BLOCK_WRITE +} nv_i2c_cmd_t; // Flags needed by OSAllocPagesNode #define NV_ALLOC_PAGES_NODE_NONE 0x0 @@ -636,27 +640,33 @@ typedef enum #define NV_GET_NV_STATE(pGpu) \ (nv_state_t *)((pGpu) ? (pGpu)->pOsGpuInfo : NULL) -#define IS_REG_OFFSET(nv, offset, length) \ - (((offset) >= (nv)->regs->cpu_address) && \ - (((offset) + ((length)-1)) <= \ - (nv)->regs->cpu_address + ((nv)->regs->size-1))) +static inline NvBool IS_REG_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length) +{ + return ((offset >= nv->regs->cpu_address) && + ((offset + (length - 1)) <= (nv->regs->cpu_address + (nv->regs->size - 1)))); +} -#define IS_FB_OFFSET(nv, offset, length) \ - (((nv)->fb) && ((offset) >= (nv)->fb->cpu_address) && \ - (((offset) + ((length)-1)) <= (nv)->fb->cpu_address + ((nv)->fb->size-1))) +static inline NvBool IS_FB_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length) +{ + return ((nv->fb) && (offset >= nv->fb->cpu_address) && + ((offset + (length - 1)) <= (nv->fb->cpu_address + (nv->fb->size - 1)))); +} -#define IS_UD_OFFSET(nv, offset, length) \ - (((nv)->ud.cpu_address != 0) && ((nv)->ud.size != 0) && \ - ((offset) >= (nv)->ud.cpu_address) && \ - (((offset) + ((length)-1)) <= (nv)->ud.cpu_address + ((nv)->ud.size-1))) +static inline NvBool IS_UD_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length) +{ + return ((nv->ud.cpu_address != 0) && (nv->ud.size != 0) && + (offset >= nv->ud.cpu_address) && + ((offset + (length - 1)) <= (nv->ud.cpu_address + (nv->ud.size - 1)))); +} -#define IS_IMEM_OFFSET(nv, offset, length) \ - (((nv)->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address != 0) && \ - ((nv)->bars[NV_GPU_BAR_INDEX_IMEM].size != 0) && \ - ((offset) >= (nv)->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address) && \ - (((offset) + ((length) - 1)) <= \ - (nv)->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + \ - ((nv)->bars[NV_GPU_BAR_INDEX_IMEM].size - 1))) +static inline NvBool IS_IMEM_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length) +{ + return ((nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address != 0) && + (nv->bars[NV_GPU_BAR_INDEX_IMEM].size != 0) && + (offset >= nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address) && + ((offset + (length - 1)) <= (nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + + (nv->bars[NV_GPU_BAR_INDEX_IMEM].size - 1)))); +} #define NV_RM_MAX_MSIX_LINES 8 @@ -787,7 +797,7 @@ NV_STATUS NV_API_CALL nv_pci_trigger_recovery (nv_state_t *); NvBool NV_API_CALL nv_requires_dma_remap (nv_state_t *); NvBool NV_API_CALL nv_is_rm_firmware_active(nv_state_t *); -const void*NV_API_CALL nv_get_firmware(nv_state_t *, nv_firmware_t, const void **, NvU32 *); +const void*NV_API_CALL nv_get_firmware(nv_state_t *, nv_firmware_type_t, nv_firmware_chip_family_t, const void **, NvU32 *); void NV_API_CALL nv_put_firmware(const void *); nv_file_private_t* NV_API_CALL nv_get_file_private(NvS32, NvBool, void **); @@ -828,6 +838,7 @@ NV_STATUS NV_API_CALL nv_acquire_fabric_mgmt_cap (int, int*); int NV_API_CALL nv_cap_drv_init(void); void NV_API_CALL nv_cap_drv_exit(void); NvBool NV_API_CALL nv_is_gpu_accessible(nv_state_t *); +NvBool NV_API_CALL nv_match_gpu_os_info(nv_state_t *, void *); NvU32 NV_API_CALL nv_get_os_type(void); @@ -916,11 +927,11 @@ NvBool NV_API_CALL rm_is_supported_pci_device(NvU8 pci_class, void NV_API_CALL rm_i2c_remove_adapters (nvidia_stack_t *, nv_state_t *); NvBool NV_API_CALL rm_i2c_is_smbus_capable (nvidia_stack_t *, nv_state_t *, void *); -NV_STATUS NV_API_CALL rm_i2c_transfer (nvidia_stack_t *, nv_state_t *, void *, NvU8, NvU8, NvU8, NvU32, NvU8 *); +NV_STATUS NV_API_CALL rm_i2c_transfer (nvidia_stack_t *, nv_state_t *, void *, nv_i2c_cmd_t, NvU8, NvU8, NvU32, NvU8 *); NV_STATUS NV_API_CALL rm_perform_version_check (nvidia_stack_t *, void *, NvU32); -NV_STATUS NV_API_CALL rm_system_event (nvidia_stack_t *, NvU32, NvU32); +void NV_API_CALL rm_power_source_change_event (nvidia_stack_t *, NvU32); void NV_API_CALL rm_disable_gpu_state_persistence (nvidia_stack_t *sp, nv_state_t *); NV_STATUS NV_API_CALL rm_p2p_init_mapping (nvidia_stack_t *, NvU64, NvU64 *, NvU64 *, NvU64 *, NvU64 *, NvU64, NvU64, NvU64, NvU64, void (*)(void *), void *); @@ -944,6 +955,7 @@ void NV_API_CALL rm_kernel_rmapi_op(nvidia_stack_t *sp, void *ops_cmd); NvBool NV_API_CALL rm_get_device_remove_flag(nvidia_stack_t *sp, NvU32 gpu_id); NV_STATUS NV_API_CALL rm_gpu_copy_mmu_faults(nvidia_stack_t *, nv_state_t *, NvU32 *); NV_STATUS NV_API_CALL rm_gpu_copy_mmu_faults_unlocked(nvidia_stack_t *, nv_state_t *, NvU32 *); +NV_STATUS NV_API_CALL rm_gpu_handle_mmu_faults(nvidia_stack_t *, nv_state_t *, NvU32 *); NvBool NV_API_CALL rm_gpu_need_4k_page_isolation(nv_state_t *); NvBool NV_API_CALL rm_is_chipset_io_coherent(nv_stack_t *); NvBool NV_API_CALL rm_init_event_locks(nvidia_stack_t *, nv_state_t *); @@ -969,12 +981,13 @@ const char* NV_API_CALL rm_get_dynamic_power_management_status(nvidia_stack_t *, const char* NV_API_CALL rm_get_gpu_gcx_support(nvidia_stack_t *, nv_state_t *, NvBool); void NV_API_CALL rm_acpi_notify(nvidia_stack_t *, nv_state_t *, NvU32); -NV_STATUS NV_API_CALL rm_get_clientnvpcf_power_limits(nvidia_stack_t *, nv_state_t *, NvU32 *, NvU32 *); + +NvBool NV_API_CALL rm_is_altstack_in_use(void); /* vGPU VFIO specific functions */ NV_STATUS NV_API_CALL nv_vgpu_create_request(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU32, NvU16 *, NvU32, NvBool *); NV_STATUS NV_API_CALL nv_vgpu_delete(nvidia_stack_t *, const NvU8 *, NvU16); -NV_STATUS NV_API_CALL nv_vgpu_get_type_ids(nvidia_stack_t *, nv_state_t *, NvU32 *, NvU32 **, NvBool); +NV_STATUS NV_API_CALL nv_vgpu_get_type_ids(nvidia_stack_t *, nv_state_t *, NvU32 *, NvU32 *, NvBool, NvU8, NvBool); NV_STATUS NV_API_CALL nv_vgpu_get_type_info(nvidia_stack_t *, nv_state_t *, NvU32, char *, int, NvU8); NV_STATUS NV_API_CALL nv_vgpu_get_bar_info(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU64 *, NvU32, void *); NV_STATUS NV_API_CALL nv_vgpu_start(nvidia_stack_t *, const NvU8 *, void *, NvS32 *, NvU8 *, NvU32); @@ -987,6 +1000,10 @@ NV_STATUS NV_API_CALL nv_get_usermap_access_params(nv_state_t*, nv_usermap_acces nv_soc_irq_type_t NV_API_CALL nv_get_current_irq_type(nv_state_t*); void NV_API_CALL nv_flush_coherent_cpu_cache_range(nv_state_t *nv, NvU64 cpu_virtual, NvU64 size); +#if defined(NV_VMWARE) +const void* NV_API_CALL rm_get_firmware(nv_firmware_type_t fw_type, const void **fw_buf, NvU32 *fw_size); +#endif + /* Callbacks should occur roughly every 10ms. */ #define NV_SNAPSHOT_TIMER_HZ 100 void NV_API_CALL nv_start_snapshot_timer(void (*snapshot_callback)(void *context)); @@ -998,6 +1015,16 @@ static inline const NvU8 *nv_get_cached_uuid(nv_state_t *nv) return nv->nv_uuid_cache.valid ? nv->nv_uuid_cache.uuid : NULL; } +/* nano second resolution timer callback structure */ +typedef struct nv_nano_timer nv_nano_timer_t; + +/* nano timer functions */ +void NV_API_CALL nv_create_nano_timer(nv_state_t *, void *pTmrEvent, nv_nano_timer_t **); +void NV_API_CALL nv_start_nano_timer(nv_state_t *nv, nv_nano_timer_t *, NvU64 timens); +NV_STATUS NV_API_CALL rm_run_nano_timer_callback(nvidia_stack_t *, nv_state_t *, void *pTmrEvent); +void NV_API_CALL nv_cancel_nano_timer(nv_state_t *, nv_nano_timer_t *); +void NV_API_CALL nv_destroy_nano_timer(nv_state_t *nv, nv_nano_timer_t *); + #if defined(NVCPU_X86_64) static inline NvU64 nv_rdtsc(void) diff --git a/kernel-open/common/inc/nv_uvm_interface.h b/kernel-open/common/inc/nv_uvm_interface.h index 9587e4236..1c9e68b2c 100644 --- a/kernel-open/common/inc/nv_uvm_interface.h +++ b/kernel-open/common/inc/nv_uvm_interface.h @@ -331,10 +331,14 @@ typedef NV_STATUS (*uvmPmaEvictPagesCallback)(void *callbackData, NvU64 *pPages, NvU32 count, NvU64 physBegin, - NvU64 physEnd); + NvU64 physEnd, + UVM_PMA_GPU_MEMORY_TYPE mem_type); // Mirrors pmaEvictRangeCb_t, see its documentation in pma.h. -typedef NV_STATUS (*uvmPmaEvictRangeCallback)(void *callbackData, NvU64 physBegin, NvU64 physEnd); +typedef NV_STATUS (*uvmPmaEvictRangeCallback)(void *callbackData, + NvU64 physBegin, + NvU64 physEnd, + UVM_PMA_GPU_MEMORY_TYPE mem_type); /******************************************************************************* nvUvmInterfacePmaRegisterEvictionCallbacks diff --git a/kernel-open/common/inc/nv_uvm_types.h b/kernel-open/common/inc/nv_uvm_types.h index dc3a4dc15..cce348a25 100644 --- a/kernel-open/common/inc/nv_uvm_types.h +++ b/kernel-open/common/inc/nv_uvm_types.h @@ -897,6 +897,16 @@ typedef struct UvmGpuAccessCntrConfig_tag NvU32 threshold; } UvmGpuAccessCntrConfig; +// +// When modifying this enum, make sure they are compatible with the mirrored +// MEMORY_PROTECTION enum in phys_mem_allocator.h. +// +typedef enum UvmPmaGpuMemoryType_tag +{ + UVM_PMA_GPU_MEMORY_TYPE_UNPROTECTED = 0, + UVM_PMA_GPU_MEMORY_TYPE_PROTECTED = 1 +} UVM_PMA_GPU_MEMORY_TYPE; + typedef UvmGpuChannelInfo gpuChannelInfo; typedef UvmGpuChannelAllocParams gpuChannelAllocParams; typedef UvmGpuCaps gpuCaps; diff --git a/kernel-open/common/inc/nvgputypes.h b/kernel-open/common/inc/nvgputypes.h index 59ba45b3d..d01841467 100644 --- a/kernel-open/common/inc/nvgputypes.h +++ b/kernel-open/common/inc/nvgputypes.h @@ -150,9 +150,7 @@ typedef struct NvSyncPointFenceRec { |* *| \***************************************************************************/ -#if !defined(XAPIGEN) /* NvOffset is XAPIGEN builtin type, so skip typedef */ typedef NvU64 NvOffset; /* GPU address */ -#endif #define NvOffset_HI32(n) ((NvU32)(((NvU64)(n)) >> 32)) #define NvOffset_LO32(n) ((NvU32)((NvU64)(n))) diff --git a/kernel-open/common/inc/nvkms-api-types.h b/kernel-open/common/inc/nvkms-api-types.h index 0f59c8304..7131b32b8 100644 --- a/kernel-open/common/inc/nvkms-api-types.h +++ b/kernel-open/common/inc/nvkms-api-types.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -29,6 +29,7 @@ #include #define NVKMS_MAX_SUBDEVICES NV_MAX_SUBDEVICES +#define NVKMS_MAX_HEADS_PER_DISP NV_MAX_HEADS #define NVKMS_LEFT 0 #define NVKMS_RIGHT 1 @@ -530,4 +531,78 @@ typedef struct { NvBool noncoherent; } NvKmsDispIOCoherencyModes; +enum NvKmsInputColorSpace { + /* Unknown colorspace; no de-gamma will be applied */ + NVKMS_INPUT_COLORSPACE_NONE = 0, + + /* Linear, Rec.709 [-0.5, 7.5) */ + NVKMS_INPUT_COLORSPACE_SCRGB_LINEAR = 1, + + /* PQ, Rec.2020 unity */ + NVKMS_INPUT_COLORSPACE_BT2100_PQ = 2, +}; + +enum NvKmsOutputTf { + /* + * NVKMS itself won't apply any OETF (clients are still + * free to provide a custom OLUT) + */ + NVKMS_OUTPUT_TF_NONE = 0, + NVKMS_OUTPUT_TF_TRADITIONAL_GAMMA_SDR = 1, + NVKMS_OUTPUT_TF_PQ = 2, +}; + +/*! + * HDR Static Metadata Type1 Descriptor as per CEA-861.3 spec. + * This is expected to match exactly with the spec. + */ +struct NvKmsHDRStaticMetadata { + /*! + * Color primaries of the data. + * These are coded as unsigned 16-bit values in units of 0.00002, + * where 0x0000 represents zero and 0xC350 represents 1.0000. + */ + struct { + NvU16 x, y; + } displayPrimaries[3]; + + /*! + * White point of colorspace data. + * These are coded as unsigned 16-bit values in units of 0.00002, + * where 0x0000 represents zero and 0xC350 represents 1.0000. + */ + struct { + NvU16 x, y; + } whitePoint; + + /** + * Maximum mastering display luminance. + * This value is coded as an unsigned 16-bit value in units of 1 cd/m2, + * where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2. + */ + NvU16 maxDisplayMasteringLuminance; + + /*! + * Minimum mastering display luminance. + * This value is coded as an unsigned 16-bit value in units of + * 0.0001 cd/m2, where 0x0001 represents 0.0001 cd/m2 and 0xFFFF + * represents 6.5535 cd/m2. + */ + NvU16 minDisplayMasteringLuminance; + + /*! + * Maximum content light level. + * This value is coded as an unsigned 16-bit value in units of 1 cd/m2, + * where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2. + */ + NvU16 maxCLL; + + /*! + * Maximum frame-average light level. + * This value is coded as an unsigned 16-bit value in units of 1 cd/m2, + * where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2. + */ + NvU16 maxFALL; +}; + #endif /* NVKMS_API_TYPES_H */ diff --git a/kernel-open/common/inc/nvkms-format.h b/kernel-open/common/inc/nvkms-format.h index d1483f875..88b26b3d4 100644 --- a/kernel-open/common/inc/nvkms-format.h +++ b/kernel-open/common/inc/nvkms-format.h @@ -86,8 +86,9 @@ enum NvKmsSurfaceMemoryFormat { NvKmsSurfaceMemoryFormatY12___V12U12_N420 = 32, NvKmsSurfaceMemoryFormatY8___U8___V8_N444 = 33, NvKmsSurfaceMemoryFormatY8___U8___V8_N420 = 34, + NvKmsSurfaceMemoryFormatRF16GF16BF16XF16 = 35, NvKmsSurfaceMemoryFormatMin = NvKmsSurfaceMemoryFormatI8, - NvKmsSurfaceMemoryFormatMax = NvKmsSurfaceMemoryFormatY8___U8___V8_N420, + NvKmsSurfaceMemoryFormatMax = NvKmsSurfaceMemoryFormatRF16GF16BF16XF16, }; typedef struct NvKmsSurfaceMemoryFormatInfo { diff --git a/kernel-open/common/inc/nvkms-kapi.h b/kernel-open/common/inc/nvkms-kapi.h index a63d8dfdf..0ae71e170 100644 --- a/kernel-open/common/inc/nvkms-kapi.h +++ b/kernel-open/common/inc/nvkms-kapi.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -149,6 +149,7 @@ struct NvKmsKapiDeviceResourcesInfo { } caps; NvU64 supportedSurfaceMemoryFormats[NVKMS_KAPI_LAYER_MAX]; + NvBool supportsHDR[NVKMS_KAPI_LAYER_MAX]; }; #define NVKMS_KAPI_LAYER_MASK(layerType) (1 << (layerType)) @@ -218,6 +219,11 @@ struct NvKmsKapiLayerConfig { struct NvKmsRRParams rrParams; struct NvKmsKapiSyncpt syncptParams; + struct NvKmsHDRStaticMetadata hdrMetadata; + NvBool hdrMetadataSpecified; + + enum NvKmsOutputTf tf; + NvU8 minPresentInterval; NvBool tearing; @@ -226,6 +232,8 @@ struct NvKmsKapiLayerConfig { NvS16 dstX, dstY; NvU16 dstWidth, dstHeight; + + enum NvKmsInputColorSpace inputColorSpace; }; struct NvKmsKapiLayerRequestedConfig { @@ -277,6 +285,8 @@ struct NvKmsKapiHeadModeSetConfig { NvKmsKapiDisplay displays[NVKMS_KAPI_MAX_CLONE_DISPLAYS]; struct NvKmsKapiDisplayMode mode; + + NvBool vrrEnabled; }; struct NvKmsKapiHeadRequestedConfig { @@ -368,6 +378,9 @@ struct NvKmsKapiDynamicDisplayParams { /* [OUT] Connection status */ NvU32 connected; + /* [OUT] VRR status */ + NvBool vrrSupported; + /* [IN/OUT] EDID of connected monitor/ Input to override EDID */ struct { NvU16 bufferSize; @@ -484,6 +497,38 @@ struct NvKmsKapiFunctionsTable { */ void (*releaseOwnership)(struct NvKmsKapiDevice *device); + /*! + * Grant modeset permissions for a display to fd. Only one (dispIndex, head, + * display) is currently supported. + * + * \param [in] fd fd from opening /dev/nvidia-modeset. + * + * \param [in] device A device returned by allocateDevice(). + * + * \param [in] head head of display. + * + * \param [in] display The display to grant. + * + * \return NV_TRUE on success, NV_FALSE on failure. + */ + NvBool (*grantPermissions) + ( + NvS32 fd, + struct NvKmsKapiDevice *device, + NvU32 head, + NvKmsKapiDisplay display + ); + + /*! + * Revoke modeset permissions previously granted. This currently applies for all + * previous grant requests for this device. + * + * \param [in] device A device returned by allocateDevice(). + * + * \return NV_TRUE on success, NV_FALSE on failure. + */ + NvBool (*revokePermissions)(struct NvKmsKapiDevice *device); + /*! * Registers for notification, via * NvKmsKapiAllocateDeviceParams::eventCallback, of the events specified diff --git a/kernel-open/common/inc/nvmisc.h b/kernel-open/common/inc/nvmisc.h index 210e23798..fa33a9ffd 100644 --- a/kernel-open/common/inc/nvmisc.h +++ b/kernel-open/common/inc/nvmisc.h @@ -234,12 +234,14 @@ extern "C" { #define DRF_EXTENT(drf) (drf##_HIGH_FIELD) #define DRF_SHIFT(drf) ((drf##_LOW_FIELD) % 32U) #define DRF_SHIFT_RT(drf) ((drf##_HIGH_FIELD) % 32U) +#define DRF_SIZE(drf) ((drf##_HIGH_FIELD)-(drf##_LOW_FIELD)+1U) #define DRF_MASK(drf) (0xFFFFFFFFU >> (31U - ((drf##_HIGH_FIELD) % 32U) + ((drf##_LOW_FIELD) % 32U))) #else #define DRF_BASE(drf) (NV_FALSE?drf) // much better #define DRF_EXTENT(drf) (NV_TRUE?drf) // much better #define DRF_SHIFT(drf) (((NvU32)DRF_BASE(drf)) % 32U) #define DRF_SHIFT_RT(drf) (((NvU32)DRF_EXTENT(drf)) % 32U) +#define DRF_SIZE(drf) (DRF_EXTENT(drf)-DRF_BASE(drf)+1U) #define DRF_MASK(drf) (0xFFFFFFFFU>>(31U - DRF_SHIFT_RT(drf) + DRF_SHIFT(drf))) #endif #define DRF_DEF(d,r,f,c) (((NvU32)(NV ## d ## r ## f ## c))<>(31-((DRF_ISBIT(1,drf)) % 32)+((DRF_ISBIT(0,drf)) % 32))) #define DRF_DEF(d,r,f,c) ((NV ## d ## r ## f ## c)<>DRF_SHIFT(NV ## d ## r ## f))&DRF_MASK(NV ## d ## r ## f)) #endif @@ -907,6 +909,16 @@ static NV_FORCEINLINE void *NV_NVUPTR_TO_PTR(NvUPtr address) return uAddr.p; } +// Get bit at pos (k) from x +#define NV_BIT_GET(k, x) (((x) >> (k)) & 1) +// Get bit at pos (n) from (hi) if >= 64, otherwise from (lo). This is paired with NV_BIT_SET_128 which sets the bit. +#define NV_BIT_GET_128(n, lo, hi) (((n) < 64) ? NV_BIT_GET((n), (lo)) : NV_BIT_GET((n) - 64, (hi))) +// +// Set the bit at pos (b) for U64 which is < 128. Since the (b) can be >= 64, we need 2 U64 to store this. +// Use (lo) if (b) is less than 64, and (hi) if >= 64. +// +#define NV_BIT_SET_128(b, lo, hi) { nvAssert( (b) < 128 ); if ( (b) < 64 ) (lo) |= NVBIT64(b); else (hi) |= NVBIT64( b & 0x3F ); } + #ifdef __cplusplus } #endif //__cplusplus diff --git a/kernel-open/common/inc/nvstatus.h b/kernel-open/common/inc/nvstatus.h index f90cbf520..4f5284db2 100644 --- a/kernel-open/common/inc/nvstatus.h +++ b/kernel-open/common/inc/nvstatus.h @@ -24,11 +24,6 @@ #ifndef SDK_NVSTATUS_H #define SDK_NVSTATUS_H -/* XAPIGEN - this file is not suitable for (nor needed by) xapigen. */ -/* Rather than #ifdef out every such include in every sdk */ -/* file, punt here. */ -#if !defined(XAPIGEN) /* rest of file */ - #ifdef __cplusplus extern "C" { #endif @@ -125,6 +120,4 @@ const char *nvstatusToString(NV_STATUS nvStatusIn); } #endif -#endif // XAPIGEN - #endif /* SDK_NVSTATUS_H */ diff --git a/kernel-open/common/inc/nvstatuscodes.h b/kernel-open/common/inc/nvstatuscodes.h index 09256bf70..517a8cef8 100644 --- a/kernel-open/common/inc/nvstatuscodes.h +++ b/kernel-open/common/inc/nvstatuscodes.h @@ -24,11 +24,6 @@ #ifndef SDK_NVSTATUSCODES_H #define SDK_NVSTATUSCODES_H -/* XAPIGEN - this file is not suitable for (nor needed by) xapigen. */ -/* Rather than #ifdef out every such include in every sdk */ -/* file, punt here. */ -#if !defined(XAPIGEN) /* rest of file */ - NV_STATUS_CODE(NV_OK, 0x00000000, "Success") NV_STATUS_CODE(NV_ERR_GENERIC, 0x0000FFFF, "Failure: Generic Error") @@ -153,6 +148,7 @@ NV_STATUS_CODE(NV_ERR_NVLINK_CLOCK_ERROR, 0x00000076, "Nvlink Clock NV_STATUS_CODE(NV_ERR_NVLINK_TRAINING_ERROR, 0x00000077, "Nvlink Training Error") NV_STATUS_CODE(NV_ERR_NVLINK_CONFIGURATION_ERROR, 0x00000078, "Nvlink Configuration Error") NV_STATUS_CODE(NV_ERR_RISCV_ERROR, 0x00000079, "Generic RISC-V assert or halt") +NV_STATUS_CODE(NV_ERR_FABRIC_MANAGER_NOT_PRESENT, 0x0000007A, "Fabric Manager is not loaded") // Warnings: NV_STATUS_CODE(NV_WARN_HOT_SWITCH, 0x00010001, "WARNING Hot switch") @@ -164,6 +160,4 @@ NV_STATUS_CODE(NV_WARN_NOTHING_TO_DO, 0x00010006, "WARNING Noth NV_STATUS_CODE(NV_WARN_NULL_OBJECT, 0x00010007, "WARNING NULL object found") NV_STATUS_CODE(NV_WARN_OUT_OF_RANGE, 0x00010008, "WARNING value out of range") -#endif // XAPIGEN - #endif /* SDK_NVSTATUSCODES_H */ diff --git a/kernel-open/common/inc/os-interface.h b/kernel-open/common/inc/os-interface.h index 0aaf20521..9ebeeed83 100644 --- a/kernel-open/common/inc/os-interface.h +++ b/kernel-open/common/inc/os-interface.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -143,6 +143,14 @@ void NV_API_CALL os_free_semaphore (void *); NV_STATUS NV_API_CALL os_acquire_semaphore (void *); NV_STATUS NV_API_CALL os_cond_acquire_semaphore (void *); NV_STATUS NV_API_CALL os_release_semaphore (void *); +void* NV_API_CALL os_alloc_rwlock (void); +void NV_API_CALL os_free_rwlock (void *); +NV_STATUS NV_API_CALL os_acquire_rwlock_read (void *); +NV_STATUS NV_API_CALL os_acquire_rwlock_write (void *); +NV_STATUS NV_API_CALL os_cond_acquire_rwlock_read (void *); +NV_STATUS NV_API_CALL os_cond_acquire_rwlock_write(void *); +void NV_API_CALL os_release_rwlock_read (void *); +void NV_API_CALL os_release_rwlock_write (void *); NvBool NV_API_CALL os_semaphore_may_sleep (void); NV_STATUS NV_API_CALL os_get_version_info (os_version_info*); NvBool NV_API_CALL os_is_isr (void); diff --git a/kernel-open/conftest.sh b/kernel-open/conftest.sh index b756779d7..c04dbe26d 100755 --- a/kernel-open/conftest.sh +++ b/kernel-open/conftest.sh @@ -588,7 +588,9 @@ compile_test() { # is present. # # Added by commit 3c299dc22635 ("PCI: add - # pci_get_domain_bus_and_slot function") in 2.6.33. + # pci_get_domain_bus_and_slot function") in 2.6.33 but aarch64 + # support was added by commit d1e6dc91b532 + # ("arm64: Add architectural support for PCI") in 3.18-rc1 # CODE=" #include @@ -649,7 +651,7 @@ compile_test() { #include void conftest_register_cpu_notifier(void) { register_cpu_notifier(); - }" > conftest$$.c + }" compile_check_conftest "$CODE" "NV_REGISTER_CPU_NOTIFIER_PRESENT" "" "functions" ;; @@ -665,7 +667,7 @@ compile_test() { #include void conftest_cpuhp_setup_state(void) { cpuhp_setup_state(); - }" > conftest$$.c + }" compile_check_conftest "$CODE" "NV_CPUHP_SETUP_STATE_PRESENT" "" "functions" ;; @@ -697,66 +699,6 @@ compile_test() { compile_check_conftest "$CODE" "NV_IOREMAP_WC_PRESENT" "" "functions" ;; - file_operations) - # 'ioctl' field removed by commit b19dd42faf41 - # ("bkl: Remove locked .ioctl file operation") in v2.6.36 - CODE=" - #include - int conftest_file_operations(void) { - return offsetof(struct file_operations, ioctl); - }" - - compile_check_conftest "$CODE" "NV_FILE_OPERATIONS_HAS_IOCTL" "" "types" - ;; - - sg_alloc_table) - # - # sg_alloc_table_from_pages added by commit efc42bc98058 - # ("scatterlist: add sg_alloc_table_from_pages function") in v3.6 - # - CODE=" - #include - void conftest_sg_alloc_table_from_pages(void) { - sg_alloc_table_from_pages(); - }" - - compile_check_conftest "$CODE" "NV_SG_ALLOC_TABLE_FROM_PAGES_PRESENT" "" "functions" - ;; - - efi_enabled) - # - # Added in 2.6.12 as a variable - # - # Determine if the efi_enabled symbol is present (as a variable), - # or if the efi_enabled() function is present and how many - # arguments it takes. - # - # Converted from a variable to a function by commit 83e68189745a - # ("efi: Make 'efi_enabled' a function to query EFI facilities") - # in v3.8 - # - echo "$CONFTEST_PREAMBLE - #if defined(NV_LINUX_EFI_H_PRESENT) - #include - #endif - int conftest_efi_enabled(void) { - return efi_enabled(0); - }" > conftest$$.c - - $CC $CFLAGS -c conftest$$.c > /dev/null 2>&1 - rm -f conftest$$.c - - if [ -f conftest$$.o ]; then - echo "#define NV_EFI_ENABLED_PRESENT" | append_conftest "functions" - echo "#define NV_EFI_ENABLED_ARGUMENT_COUNT 1" | append_conftest "functions" - rm -f conftest$$.o - return - else - echo "#define NV_EFI_ENABLED_PRESENT" | append_conftest "symbols" - return - fi - ;; - dom0_kernel_present) # Add config parameter if running on DOM0. if [ -n "$VGX_BUILD" ]; then @@ -967,6 +909,38 @@ compile_test() { compile_check_conftest "$CODE" "NV_MDEV_GET_TYPE_GROUP_ID_PRESENT" "" "functions" ;; + vfio_device_mig_state) + # + # Determine if vfio_device_mig_state enum is present or not + # + # Added by commit 115dcec65f61d ("vfio: Define device + # migration protocol v2") in v5.18 + # + CODE=" + #include + #include + enum vfio_device_mig_state device_state; + " + + compile_check_conftest "$CODE" "NV_VFIO_DEVICE_MIG_STATE_PRESENT" "" "types" + ;; + + vfio_migration_ops) + # + # Determine if vfio_migration_ops struct is present or not + # + # Added by commit 6e97eba8ad874 ("vfio: Split migration ops + # from main device ops") in v6.0 + # + CODE=" + #include + #include + struct vfio_migration_ops mig_ops; + " + + compile_check_conftest "$CODE" "NV_VFIO_MIGRATION_OPS_PRESENT" "" "types" + ;; + mdev_parent) # # Determine if the struct mdev_parent type is present. @@ -1051,6 +1025,40 @@ compile_test() { compile_check_conftest "$CODE" "NV_MDEV_PARENT_OPS_HAS_OPEN_DEVICE" "" "types" ;; + mdev_parent_ops_has_device_driver) + # + # Determine if 'mdev_parent_ops' structure has 'device_driver' field. + # + # Added by commit 88a21f265ce5 ("vfio/mdev: Allow the mdev_parent_ops + # to specify the device driver to bind) in v5.14 (2021-06-17) + # + CODE=" + #include + #include + int conftest_mdev_parent_ops_has_device_driver(void) { + return offsetof(struct mdev_parent_ops, device_driver); + }" + + compile_check_conftest "$CODE" "NV_MDEV_PARENT_OPS_HAS_DEVICE_DRIVER" "" "types" + ;; + + mdev_driver_has_supported_type_groups) + # + # Determine if 'mdev_driver' structure has 'supported_type_groups' field. + # + # Added by commit 6b42f491e17c ("vfio/mdev: Remove mdev_parent_ops) + # in v5.19 (2022-04-11) + # + CODE=" + #include + #include + int conftest_mdev_driver_has_supported_type_groups(void) { + return offsetof(struct mdev_driver, supported_type_groups); + }" + + compile_check_conftest "$CODE" "NV_MDEV_DRIVER_HAS_SUPPORTED_TYPE_GROUPS" "" "types" + ;; + pci_irq_vector_helpers) # # Determine if pci_alloc_irq_vectors(), pci_free_irq_vectors() @@ -1105,6 +1113,61 @@ compile_test() { compile_check_conftest "$CODE" "NV_VFIO_DEVICE_MIGRATION_HAS_START_PFN" "" "types" ;; + vfio_uninit_group_dev) + # + # Determine if vfio_uninit_group_dev() function is present or not. + # + # Added by commit ae03c3771b8c (vfio: Introduce a vfio_uninit_group_dev() + # API call) in v5.15 + # + CODE=" + #include + void conftest_vfio_uninit_group_dev() { + vfio_uninit_group_dev(); + }" + + compile_check_conftest "$CODE" "NV_VFIO_UNINIT_GROUP_DEV_PRESENT" "" "functions" + ;; + + + vfio_pci_core_available) + # Determine if VFIO_PCI_CORE is available + # + # Added by commit 7fa005caa35e ("vfio/pci: Introduce + # vfio_pci_core.ko") in v5.16 (2021-08-26) + # + + CODE=" + #if defined(NV_LINUX_VFIO_PCI_CORE_H_PRESENT) + #include + #endif + + #if !defined(CONFIG_VFIO_PCI_CORE) && !defined(CONFIG_VFIO_PCI_CORE_MODULE) + #error VFIO_PCI_CORE not enabled + #endif + void conftest_vfio_pci_core_available(void) { + struct vfio_pci_core_device dev; + }" + + compile_check_conftest "$CODE" "NV_VFIO_PCI_CORE_PRESENT" "" "generic" + ;; + + vfio_register_emulated_iommu_dev) + # + # Determine if vfio_register_emulated_iommu_dev() function is present or not. + # + # Added by commit c68ea0d00ad8 (vfio: simplify iommu group allocation + # for mediated devices) in v5.16 + # + CODE=" + #include + void conftest_vfio_register_emulated_iommu_dev() { + vfio_register_emulated_iommu_dev(); + }" + + compile_check_conftest "$CODE" "NV_VFIO_REGISTER_EMULATED_IOMMU_DEV_PRESENT" "" "functions" + ;; + drm_available) # Determine if the DRM subsystem is usable CODE=" @@ -1192,22 +1255,6 @@ compile_test() { compile_check_conftest "$CODE" "NV_GET_NUM_PHYSPAGES_PRESENT" "" "functions" ;; - proc_remove) - # - # Determine if the proc_remove() function is present. - # - # Added by commit a8ca16ea7b0a ("proc: Supply a function to - # remove a proc entry by PDE") in v3.10 - # - CODE=" - #include - void conftest_proc_remove(void) { - proc_remove(); - }" - - compile_check_conftest "$CODE" "NV_PROC_REMOVE_PRESENT" "" "functions" - ;; - backing_dev_info) # # Determine if the 'address_space' structure has @@ -1225,77 +1272,6 @@ compile_test() { compile_check_conftest "$CODE" "NV_ADDRESS_SPACE_HAS_BACKING_DEV_INFO" "" "types" ;; - address_space) - # - # Determine if the 'address_space' structure has - # a 'tree_lock' field of type rwlock_t. - # - # 'tree_lock' was changed to spinlock_t by commit 19fd6231279b - # ("mm: spinlock tree_lock") in v2.6.27 - # - # It was removed altogether by commit b93b016313b3 ("page cache: - # use xa_lock") in v4.17 - # - CODE=" - #include - int conftest_address_space(void) { - struct address_space as; - rwlock_init(&as.tree_lock); - return offsetof(struct address_space, tree_lock); - }" - - compile_check_conftest "$CODE" "NV_ADDRESS_SPACE_HAS_RWLOCK_TREE_LOCK" "" "types" - ;; - - address_space_init_once) - # - # Determine if address_space_init_once is present. - # - # Added by commit 2aa15890f3c1 ("mm: prevent concurrent - # unmap_mapping_range() on the same inode") in v2.6.38 - # - # If not present, it will be defined in uvm-linux.h. - # - CODE=" - #include - void conftest_address_space_init_once(void) { - address_space_init_once(); - }" - - compile_check_conftest "$CODE" "NV_ADDRESS_SPACE_INIT_ONCE_PRESENT" "" "functions" - ;; - - kuid_t) - # - # Determine if the 'kuid_t' type is present. - # - # Added by commit 7a4e7408c5ca ("userns: Add kuid_t and kgid_t - # and associated infrastructure in uidgid.h") in v3.5 - # - CODE=" - #include - kuid_t conftest_kuid_t; - " - - compile_check_conftest "$CODE" "NV_KUID_T_PRESENT" "" "types" - ;; - - pm_vt_switch_required) - # - # Determine if the pm_vt_switch_required() function is present. - # - # Added by commit f43f627d2f17 ("PM: make VT switching to the - # suspend console optional v3") in v3.10 - # - CODE=" - #include - void conftest_pm_vt_switch_required(void) { - pm_vt_switch_required(); - }" - - compile_check_conftest "$CODE" "NV_PM_VT_SWITCH_REQUIRED_PRESENT" "" "functions" - ;; - xen_ioemu_inject_msi) # Determine if the xen_ioemu_inject_msi() function is present. CODE=" @@ -1473,39 +1449,6 @@ compile_test() { compile_check_conftest "$CODE" "NV_NVHOST_DMA_FENCE_UNPACK_PRESENT" "" "functions" ;; - of_get_property) - # - # Determine if the of_get_property function is present. - # - # Support for kernels without CONFIG_OF defined added by commit - # 89272b8c0d42 ("dt: add empty of_get_property for non-dt") in v3.1 - # - # Test if linux/of.h header file inclusion is successful or not and - # define/undefine NV_LINUX_OF_H_USABLE depending upon status of inclusion - # - echo "$CONFTEST_PREAMBLE - #include - " > conftest$$.c - - $CC $CFLAGS -c conftest$$.c > /dev/null 2>&1 - rm -f conftest$$.c - - if [ -f conftest$$.o ]; then - rm -f conftest$$.o - echo "#define NV_LINUX_OF_H_USABLE" | append_conftest "generic" - CODE=" - #include - void conftest_of_get_property() { - of_get_property(); - }" - - compile_check_conftest "$CODE" "NV_OF_GET_PROPERTY_PRESENT" "" "functions" - else - echo "#undef NV_LINUX_OF_H_USABLE" | append_conftest "generic" - echo "#undef NV_OF_GET_PROPERTY_PRESENT" | append_conftest "functions" - fi - ;; - of_find_node_by_phandle) # # Determine if the of_find_node_by_phandle function is present. @@ -1594,50 +1537,28 @@ compile_test() { compile_check_conftest "$CODE" "NV_PNV_PCI_GET_NPU_DEV_PRESENT" "" "functions" ;; - kernel_write) + kernel_write_has_pointer_pos_arg) # - # Determine if the function kernel_write() is present. - # - # First exported by commit 7bb307e894d5 ("export kernel_write(), - # convert open-coded instances") in v3.9 + # Determine the pos argument type, which was changed by + # commit e13ec939e96b1 (fs: fix kernel_write prototype) on + # 9/1/2017. # echo "$CONFTEST_PREAMBLE #include - void conftest_kernel_write(void) { - kernel_write(); + ssize_t kernel_write(struct file *file, const void *buf, + size_t count, loff_t *pos) + { + return 0; }" > conftest$$.c; - $CC $CFLAGS -c conftest$$.c > /dev/null 2>&1 + $CC $CFLAGS -c conftest$$.c > /dev/null 2>&1 rm -f conftest$$.c - if [ -f conftest$$.o ]; then - echo "#undef NV_KERNEL_WRITE_PRESENT" | append_conftest "function" + if [ -f conftest$$.o ]; then + echo "#define NV_KERNEL_WRITE_HAS_POINTER_POS_ARG" | append_conftest "function" rm -f conftest$$.o else - echo "#define NV_KERNEL_WRITE_PRESENT" | append_conftest "function" - - # - # Determine the pos argument type, which was changed by - # commit e13ec939e96b1 (fs: fix kernel_write prototype) on - # 9/1/2017. - # - echo "$CONFTEST_PREAMBLE - #include - ssize_t kernel_write(struct file *file, const void *buf, - size_t count, loff_t *pos) - { - return 0; - }" > conftest$$.c; - - $CC $CFLAGS -c conftest$$.c > /dev/null 2>&1 - rm -f conftest$$.c - - if [ -f conftest$$.o ]; then - echo "#define NV_KERNEL_WRITE_HAS_POINTER_POS_ARG" | append_conftest "function" - rm -f conftest$$.o - else - echo "#undef NV_KERNEL_WRITE_HAS_POINTER_POS_ARG" | append_conftest "function" - fi + echo "#undef NV_KERNEL_WRITE_HAS_POINTER_POS_ARG" | append_conftest "function" fi ;; @@ -2004,6 +1925,7 @@ compile_test() { }" > conftest$$.c $CC $CFLAGS -c conftest$$.c > /dev/null 2>&1 + rm -f conftest$$.c if [ -f conftest$$.o ]; then rm -f conftest$$.o @@ -2013,7 +1935,7 @@ compile_test() { else echo "#undef NV_DRM_UNIVERSAL_PLANE_INIT_HAS_FORMAT_MODIFIERS_ARG" | append_conftest "types" - echo "$CONFTEST_PREAMBLE + CODE=" #if defined(NV_DRM_DRMP_H_PRESENT) #include #endif @@ -2033,35 +1955,10 @@ compile_test() { 0, /* unsigned int format_count */ DRM_PLANE_TYPE_PRIMARY, NULL); /* const char *name */ - }" > conftest$$.c + }" - $CC $CFLAGS -c conftest$$.c > /dev/null 2>&1 - - if [ -f conftest$$.o ]; then - rm -f conftest$$.o - - echo "#define NV_DRM_UNIVERSAL_PLANE_INIT_HAS_NAME_ARG" | append_conftest "types" - else - echo "#undef NV_DRM_UNIVERSAL_PLANE_INIT_HAS_NAME_ARG" | append_conftest "types" - fi + compile_check_conftest "$CODE" "NV_DRM_UNIVERSAL_PLANE_INIT_HAS_NAME_ARG" "" "types" fi - - ;; - - vzalloc) - # - # Determine if the vzalloc function is present - # - # Added by commit e1ca7788dec6 ("mm: add vzalloc() and - # vzalloc_node() helpers") in v2.6.37 (2010-10-26) - # - CODE=" - #include - void conftest_vzalloc() { - vzalloc(); - }" - - compile_check_conftest "$CODE" "NV_VZALLOC_PRESENT" "" "functions" ;; drm_driver_has_set_busid) @@ -2186,29 +2083,14 @@ compile_test() { echo "#error wait_on_bit_lock() conftest failed!" | append_conftest "functions" ;; - bitmap_clear) - # - # Determine if the bitmap_clear function is present - # - # Added by commit c1a2a962a2ad ("bitmap: introduce bitmap_set, - # bitmap_clear, bitmap_find_next_zero_area") in v2.6.33 - # (2009-12-15) - # - CODE=" - #include - void conftest_bitmap_clear() { - bitmap_clear(); - }" - - compile_check_conftest "$CODE" "NV_BITMAP_CLEAR_PRESENT" "" "functions" - ;; - pci_stop_and_remove_bus_device) # # Determine if the pci_stop_and_remove_bus_device() function is present. # # Added by commit 210647af897a ("PCI: Rename pci_remove_bus_device - # to pci_stop_and_remove_bus_device") in v3.4 (2012-02-25) + # to pci_stop_and_remove_bus_device") in v3.4 (2012-02-25) but + # aarch64 support was added by commit d1e6dc91b532 + # ("arm64: Add architectural support for PCI") in v3.18-rc1. # CODE=" #include @@ -2220,23 +2102,6 @@ compile_test() { compile_check_conftest "$CODE" "NV_PCI_STOP_AND_REMOVE_BUS_DEVICE_PRESENT" "" "functions" ;; - pci_remove_bus_device) - # - # Determine if the pci_remove_bus_device() function is present. - # Added before Linux-2.6.12-rc2 2005-04-16 - # Because we support builds on non-PCI platforms, we still need - # to check for this function's presence. - # - CODE=" - #include - #include - void conftest_pci_remove_bus_device() { - pci_remove_bus_device(); - }" - - compile_check_conftest "$CODE" "NV_PCI_REMOVE_BUS_DEVICE_PRESENT" "" "functions" - ;; - drm_helper_mode_fill_fb_struct | drm_helper_mode_fill_fb_struct_has_const_mode_cmd_arg) # # Determine if the drm_helper_mode_fill_fb_struct function takes @@ -2334,23 +2199,6 @@ compile_test() { compile_check_conftest "$CODE" "NV_PCI_DEV_HAS_ATS_ENABLED" "" "types" ;; - mt_device_gre) - # - # Determine if MT_DEVICE_GRE flag is present. - # - # MT_DEVICE_GRE flag is removed by commit 58cc6b72a21274 - # ("arm64: mm: Remove unused support for Device-GRE memory type") in v5.14-rc1 - # (2021-06-01). - # - CODE=" - #include - unsigned int conftest_mt_device_gre(void) { - return MT_DEVICE_GRE; - }" - - compile_check_conftest "$CODE" "NV_MT_DEVICE_GRE_PRESENT" "" "types" - ;; - get_user_pages) # # Conftest for get_user_pages() @@ -2668,20 +2516,146 @@ compile_test() { fi ;; - usleep_range) + pin_user_pages) # - # Determine if the function usleep_range() is present. + # Determine if the function pin_user_pages() is present. + # Presence of pin_user_pages() also implies the presence of + # unpin-user_page(). Both were added in the v5.6-rc1 # - # Added by commit 5e7f5a178bba ("timer: Added usleep_range timer") - # in v2.6.36 (2010-08-04) + # pin_user_pages() was added by commit eddb1c228f7951d399240 + # ("mm/gup: introduce pin_user_pages*() and FOLL_PIN") in + # v5.6-rc1 (2020-01-30) + + # conftest #1: check if pin_user_pages() is available + # return if not available. # CODE=" - #include - void conftest_usleep_range(void) { - usleep_range(); + #include + void conftest_pin_user_pages(void) { + pin_user_pages(); }" - compile_check_conftest "$CODE" "NV_USLEEP_RANGE_PRESENT" "" "functions" + compile_check_conftest "$CODE" "NV_PIN_USER_PAGES_PRESENT" "" "functions" + ;; + + pin_user_pages_remote) + # Determine if the function pin_user_pages_remote() is present + # + # pin_user_pages_remote() was added by commit eddb1c228f7951d399240 + # ("mm/gup: introduce pin_user_pages*() and FOLL_PIN") + # in v5.6 (2020-01-30) + + # pin_user_pages_remote() removed 'tsk' parameter by + # commit 64019a2e467a ("mm/gup: remove task_struct pointer for + # all gup code") in v5.9-rc1 (2020-08-11). + + # + # This function sets the NV_PIN_USER_PAGES_REMOTE_* macros as per + # the below passing conftest's + # + set_pin_user_pages_remote_defines () { + if [ "$1" = "" ]; then + echo "#undef NV_PIN_USER_PAGES_REMOTE_PRESENT" | append_conftest "functions" + else + echo "#define NV_PIN_USER_PAGES_REMOTE_PRESENT" | append_conftest "functions" + fi + + if [ "$1" = "NV_PIN_USER_PAGES_REMOTE_HAS_ARGS_TSK" ]; then + echo "#define NV_PIN_USER_PAGES_REMOTE_HAS_ARGS_TSK" | append_conftest "functions" + else + echo "#undef NV_PIN_USER_PAGES_REMOTE_HAS_ARGS_TSK" | append_conftest "functions" + fi + } + + # conftest #1: check if pin_user_pages_remote() is available + # return if not available. + # Fall through to conftest #2 if it is present + # + echo "$CONFTEST_PREAMBLE + #include + void conftest_pin_user_pages_remote(void) { + pin_user_pages_remote(); + }" > conftest$$.c + + $CC $CFLAGS -c conftest$$.c > /dev/null 2>&1 + rm -f conftest$$.c + + if [ -f conftest$$.o ]; then + set_pin_user_pages_remote_defines "" + rm -f conftest$$.o + return + fi + + # conftest #2: Check if pin_user_pages_remote() has tsk argument + echo "$CONFTEST_PREAMBLE + #include + long pin_user_pages_remote(struct task_struct *tsk, + struct mm_struct *mm, + unsigned long start, + unsigned long nr_pages, + unsigned int gup_flags, + struct page **pages, + struct vm_area_struct **vmas, + int *locked) { + return 0; + }" > conftest$$.c + + $CC $CFLAGS -c conftest$$.c > /dev/null 2>&1 + rm -f conftest$$.c + + if [ -f conftest$$.o ]; then + set_pin_user_pages_remote_defines "NV_PIN_USER_PAGES_REMOTE_HAS_ARGS_TSK" + rm -f conftest$$.o + else + set_pin_user_pages_remote_defines "NV_PIN_USER_PAGES_REMOTE_PRESENT" + fi + ;; + + vfio_pin_pages) + # + # Determine if vfio_pin_pages() kABI accepts "struct vfio_device *" + # argument instead of "struct device *" + # + # Replaced "struct device *" with "struct vfio_device *" by commit + # 8e432bb015b6c ("vfio/mdev: Pass in a struct vfio_device * to + # vfio_pin/unpin_pages()") in v5.19 + # + echo "$CONFTEST_PREAMBLE + #include + #include + int vfio_pin_pages(struct vfio_device *device, + unsigned long *user_pfn, + int npage, + int prot, + unsigned long *phys_pfn) { + return 0; + }" > conftest$$.c + + $CC $CFLAGS -c conftest$$.c > /dev/null 2>&1 + rm -f conftest$$.c + + if [ -f conftest$$.o ]; then + echo "#define NV_VFIO_PIN_PAGES_HAS_VFIO_DEVICE_ARG" | append_conftest "functions" + rm -f conftest$$.o + else + echo "#undef NV_VFIO_PIN_PAGES_HAS_VFIO_DEVICE_ARG" | append_conftest "functions" + fi + ;; + + pci_driver_has_driver_managed_dma) + # + # Determine if "struct pci_driver" has .driver_managed_dma member. + # + # Added by commit 512881eacfa7 ("bus: platform,amba,fsl-mc,PCI: + # Add device DMA ownership management") in v5.19 + # + CODE=" + #include + int conftest_pci_driver_has_driver_managed_dma(void) { + return offsetof(struct pci_driver, driver_managed_dma); + }" + + compile_check_conftest "$CODE" "NV_PCI_DRIVER_HAS_DRIVER_MANAGED_DMA" "" "types" ;; radix_tree_empty) @@ -2751,6 +2725,130 @@ compile_test() { compile_check_conftest "$CODE" "NV_DRM_MASTER_DROP_HAS_FROM_RELEASE_ARG" "" "types" ;; + drm_connector_lookup) + # + # Determine if function drm_connector_lookup() is present. + # + # Added by commit b164d31f50b2 ("drm/modes: add connector reference + # counting. (v2)") in v4.7 (2016-05-04), when it replaced + # drm_connector_find(). + # + # It was originally added in drm_crtc.h, then moved to + # drm_connector.h by commit 522171951761 + # ("drm: Extract drm_connector.[hc]") in v4.9 (2016-08-12) + # + + CODE=" + #if defined(NV_DRM_DRM_CRTC_H_PRESENT) + #include + #endif + #if defined(NV_DRM_DRM_CONNECTOR_H_PRESENT) + #include + #endif + void conftest_drm_connector_lookup(void) { + drm_connector_lookup(); + }" + + compile_check_conftest "$CODE" "NV_DRM_CONNECTOR_LOOKUP_PRESENT" "" "functions" + ;; + + drm_connector_put) + # + # Determine if function drm_connector_put() is present. + # + # Added by commit ad09360750af ("drm: Introduce + # drm_connector_{get,put}()") in v4.12 (2017-02-28), + # when it replaced drm_connector_unreference() that + # was added with NV_DRM_CONNECTOR_LOOKUP_PRESENT. + # + + CODE=" + #if defined(NV_DRM_DRM_CONNECTOR_H_PRESENT) + #include + #endif + void conftest_drm_connector_put(void) { + drm_connector_put(); + }" + + compile_check_conftest "$CODE" "NV_DRM_CONNECTOR_PUT_PRESENT" "" "functions" + ;; + + drm_modeset_lock_all_end) + # + # Determine the number of arguments of the + # DRM_MODESET_LOCK_ALL_END() macro. + # + # DRM_MODESET_LOCK_ALL_END() is added with two arguments by commit + # b7ea04d299c7 (drm: drm: Add DRM_MODESET_LOCK_BEGIN/END helpers) + # in v5.0 (2018-11-29). The definition and prototype is changed to + # also take the third argument drm_device, by commit 77ef38574beb + # (drm/modeset-lock: Take the modeset BKL for legacy drivers) + # in v5.9 (2020-08-17). + # + DRM_MODESET_3_COMPILED=0 + DRM_MODESET_2_COMPILED=0 + DRM_MODESET_INCLUDES=" + #if defined(NV_DRM_DRM_DEVICE_H_PRESENT) + #include + #endif + #if defined(NV_DRM_DRM_DRV_H_PRESENT) + #include + #endif + #if defined(NV_DRM_DRM_MODESET_LOCK_H_PRESENT) + #include + #endif" + + echo "$CONFTEST_PREAMBLE + $DRM_MODESET_INCLUDES + + void conftest_drm_modeset_lock_all_end( + struct drm_device *dev, + struct drm_modeset_acquire_ctx ctx, + int ret) { + DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, 0, ret); + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret); + }" > conftest$$.c + + $CC $CFLAGS -c conftest$$.c > /dev/null 2>&1 + rm -f conftest$$.c + + if [ -f conftest$$.o ]; then + DRM_MODESET_3_COMPILED=1 + rm -f conftest$$.o + fi + + echo "$CONFTEST_PREAMBLE + $DRM_MODESET_INCLUDES + + void conftest_drm_modeset_lock_all_end( + struct drm_device *dev, + struct drm_modeset_acquire_ctx ctx, + int ret) { + DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, 0, ret); + DRM_MODESET_LOCK_ALL_END(ctx, ret); + }" > conftest$$.c + + $CC $CFLAGS -c conftest$$.c > /dev/null 2>&1 + rm -f conftest$$.c + + if [ -f conftest$$.o ]; then + DRM_MODESET_2_COMPILED=1 + rm -f conftest$$.o + fi + + # If the macro is undefined, both code snippets will still compile, + # so we need to check both and make sure only one compiles successfully. + if [ "$DRM_MODESET_3_COMPILED" = "1" ] && + [ "$DRM_MODESET_2_COMPILED" = "0" ]; then + echo "#define NV_DRM_MODESET_LOCK_ALL_END_ARGUMENT_COUNT 3" | append_conftest "functions" + elif [ "$DRM_MODESET_3_COMPILED" = "0" ] && + [ "$DRM_MODESET_2_COMPILED" = "1" ]; then + echo "#define NV_DRM_MODESET_LOCK_ALL_END_ARGUMENT_COUNT 2" | append_conftest "functions" + else + echo "#define NV_DRM_MODESET_LOCK_ALL_END_ARGUMENT_COUNT 0" | append_conftest "functions" + fi + ;; + drm_atomic_state_ref_counting) # # Determine if functions drm_atomic_state_get/put() are @@ -3038,23 +3136,6 @@ compile_test() { fi ;; - kthread_create_on_node) - # - # Determine if kthread_create_on_node is available - # - # kthread_create_on_node was added in by commit 207205a2ba26 - # ("kthread: NUMA aware kthread_create_on_node()") in v2.6.39 - # (2011-03-22). - # - CODE=" - #include - void kthread_create_on_node_conftest(void) { - (void)kthread_create_on_node(); - }" - - compile_check_conftest "$CODE" "NV_KTHREAD_CREATE_ON_NODE_PRESENT" "" "functions" - ;; - cpumask_of_node) # # Determine whether cpumask_of_node is available. @@ -3397,8 +3478,16 @@ compile_test() { # Note that drm_connector.h by introduced by commit 522171951761 # ("drm: Extract drm_connector.[hc]") in v4.9 (2016-08-12) # + # Note: up to 4.9 function was provided by drm_crtc.h by commit + # f453ba046074 in 2.6.29 (2008-12-29) + # CODE=" + #if defined(NV_DRM_DRM_CONNECTOR_H_PRESENT) #include + #endif + #if defined(NV_DRM_DRM_CRTC_H_PRESENT) + #include + #endif void conftest_drm_connector_funcs_have_mode_in_name(void) { drm_mode_connector_attach_encoder(); }" @@ -3406,21 +3495,25 @@ compile_test() { compile_check_conftest "$CODE" "NV_DRM_CONNECTOR_FUNCS_HAVE_MODE_IN_NAME" "" "functions" ;; - - node_states_n_memory) + drm_connector_has_vrr_capable_property) # - # Determine if the N_MEMORY constant exists. + # Determine if drm_connector_attach_vrr_capable_property and + # drm_connector_set_vrr_capable_property is present # - # Added by commit 8219fc48adb3 ("mm: node_states: introduce - # N_MEMORY") in v3.8 (2012-12-12). + # Added by commit ba1b0f6c73d4ea1390f0d5381f715ffa20c75f09 ("drm: + # Add vrr_capable property to the drm connector") in v5.0-rc1 + # (2018-11-28) # CODE=" - #include - int conftest_node_states_n_memory(void) { - return N_MEMORY; + #if defined(NV_DRM_DRM_CONNECTOR_H_PRESENT) + #include + #endif + + void conftest_drm_connector_has_vrr_capable_property(void) { + drm_connector_attach_vrr_capable_property(); }" - compile_check_conftest "$CODE" "NV_NODE_STATES_N_MEMORY_PRESENT" "" "types" + compile_check_conftest "$CODE" "NV_DRM_CONNECTOR_HAS_VRR_CAPABLE_PROPERTY" "" "functions" ;; vm_fault_t) @@ -3615,92 +3708,6 @@ compile_test() { compile_check_conftest "$CODE" "NV_PM_RUNTIME_AVAILABLE" "" "generic" ;; - device_driver_of_match_table) - # - # Determine if the device_driver struct has an of_match_table member. - # - # of_match_table was added by commit 597b9d1e44e9 ("drivercore: - # Add of_match_table to the common device drivers") in v2.6.35 - # (2010-04-13). - # - CODE=" - #include - int conftest_device_driver_of_match_table(void) { - return offsetof(struct device_driver, of_match_table); - }" - - compile_check_conftest "$CODE" "NV_DEVICE_DRIVER_OF_MATCH_TABLE_PRESENT" "" "types" - ;; - - device_of_node) - # - # Determine if the device struct has an of_node member. - # - # of_node member was added by commit d706c1b05027 ("driver-core: - # Add device node pointer to struct device") in v2.6.35 - # (2010-04-13). - # - CODE=" - #include - int conftest_device_of_node(void) { - return offsetof(struct device, of_node); - }" - - compile_check_conftest "$CODE" "NV_DEVICE_OF_NODE_PRESENT" "" "types" - ;; - - dev_is_pci) - # - # Determine if the dev_is_pci() macro is present. - # - # dev_is_pci() macro was added by commit fb8a0d9d1bfd ("pci: Add - # SR-IOV convenience functions and macros") in v2.6.34 - # (2010-02-10). - # - CODE=" - #include - void conftest_dev_is_pci(void) { - if(dev_is_pci()) {} - } - " - - compile_check_conftest "$CODE" "NV_DEV_IS_PCI_PRESENT" "" "functions" - ;; - - of_find_matching_node) - # - # Determine if the of_find_matching_node() function is present. - # - # Test if linux/of.h header file inclusion is successful or not and - # define/undefine NV_LINUX_OF_H_USABLE depending upon status of inclusion. - # - # of_find_matching_node was added by commit 283029d16a88 - # ("[POWERPC] Add of_find_matching_node() helper function") in - # v2.6.25 (2008-01-09). - # - echo "$CONFTEST_PREAMBLE - #include - " > conftest$$.c - - $CC $CFLAGS -c conftest$$.c > /dev/null 2>&1 - rm -f conftest$$.c - - if [ -f conftest$$.o ]; then - rm -f conftest$$.o - echo "#define NV_LINUX_OF_H_USABLE" | append_conftest "generic" - CODE=" - #include - void conftest_of_find_matching_node() { - of_find_matching_node(); - }" - - compile_check_conftest "$CODE" "NV_OF_FIND_MATCHING_NODE_PRESENT" "" "functions" - else - echo "#undef NV_LINUX_OF_H_USABLE" | append_conftest "generic" - echo "#undef NV_OF_FIND_MATCHING_NODE_PRESENT" | append_conftest "functions" - fi - ;; - dma_direct_map_resource) # # Determine whether dma_is_direct() exists. @@ -3857,7 +3864,7 @@ compile_test() { #include #endif - #if defined(NV_DRM_CONNECTOR_H_PRESENT) + #if defined(NV_DRM_DRM_CONNECTOR_H_PRESENT) #include #endif @@ -4009,6 +4016,26 @@ compile_test() { compile_check_conftest "$CODE" "NV_DRM_CRTC_STATE_HAS_PAGEFLIP_FLAGS" "" "types" ;; + drm_crtc_state_has_vrr_enabled) + # + # Determine if 'drm_crtc_state' structure has a + # 'vrr_enabled' field. + # + # Added by commit 1398958cfd8d331342d657d37151791dd7256b40 ("drm: + # Add vrr_enabled property to drm CRTC") in v5.0-rc1 (2018-11-28) + # + CODE=" + #if defined(NV_DRM_DRM_CRTC_H_PRESENT) + #include + #endif + + int conftest_drm_crtc_state_has_vrr_enabled(void) { + return offsetof(struct drm_crtc_state, vrr_enabled); + }" + + compile_check_conftest "$CODE" "NV_DRM_CRTC_STATE_HAS_VRR_ENABLED" "" "types" + ;; + ktime_get_raw_ts64) # # Determine if ktime_get_raw_ts64() is present @@ -4146,36 +4173,6 @@ compile_test() { fi ;; - hlist_for_each_entry) - # - # Determine how many arguments hlist_for_each_entry takes. - # - # Changed by commit b67bfe0d42c ("hlist: drop the node parameter - # from iterators") in v3.9 (2013-02-28) - # - echo "$CONFTEST_PREAMBLE - #include - void conftest_hlist_for_each_entry(void) { - struct hlist_head *head; - struct dummy - { - struct hlist_node hlist; - }; - struct dummy *pos; - hlist_for_each_entry(pos, head, hlist) {} - }" > conftest$$.c - - $CC $CFLAGS -c conftest$$.c > /dev/null 2>&1 - rm -f conftest$$.c - - if [ -f conftest$$.o ]; then - rm -f conftest$$.o - echo "#define NV_HLIST_FOR_EACH_ENTRY_ARGUMENT_COUNT 3" | append_conftest "functions" - else - echo "#define NV_HLIST_FOR_EACH_ENTRY_ARGUMENT_COUNT 4" | append_conftest "functions" - fi - ;; - drm_vma_offset_exact_lookup_locked) # # Determine if the drm_vma_offset_exact_lookup_locked() function @@ -4533,38 +4530,6 @@ compile_test() { compile_check_conftest "$CODE" "NV_DRM_GEM_OBJECT_VMAP_HAS_MAP_ARG" "" "types" ;; - set_close_on_exec) - # - # __set_close_on_exec(() was added by - # commit 1dce27c5aa67 ("Wrap accesses to the fd_sets") - # in v3.4-rc1 (2012-02-19) - # - CODE=" - #include - #include - void conftest_set_close_on_exec(void) { - __set_close_on_exec(); - }" - - compile_check_conftest "$CODE" "NV_SET_CLOSE_ON_EXEC_PRESENT" "" "functions" - ;; - - iterate_fd) - # - # iterate_fd() was added by - # commit c3c073f808b2 ("new helper: iterate_fd()") - # in v3.7-rc1 (2012-09-26) - # - CODE=" - #include - #include - void conftest_iterate_fd(void) { - iterate_fd(); - }" - - compile_check_conftest "$CODE" "NV_ITERATE_FD_PRESENT" "" "functions" - ;; - seq_read_iter) # # Determine if seq_read_iter() is present @@ -4599,23 +4564,6 @@ compile_test() { compile_check_conftest "$CODE" "NV_PCI_CLASS_MULTIMEDIA_HD_AUDIO_PRESENT" "" "generic" ;; - sg_page_iter_page) - # - # Determine if sg_page_iter_page() is present - # - # sg_page_iter_page() was added by commit 2db76d7c3c6db - # ("lib/scatterlist: sg_page_iter: support sg lists w/o backing - # pages") in v3.10-rc1 (2013-05-11). - # - CODE=" - #include - void conftest_sg_page_iter_page(void) { - sg_page_iter_page(); - }" - - compile_check_conftest "$CODE" "NV_SG_PAGE_ITER_PAGE_PRESENT" "" "functions" - ;; - unsafe_follow_pfn) # # Determine if unsafe_follow_pfn() is present. @@ -5294,6 +5242,48 @@ compile_test() { compile_check_conftest "$CODE" "NV_PLATFORM_IRQ_COUNT_PRESENT" "" "functions" ;; + devm_clk_bulk_get_all) + # + # Determine if devm_clk_bulk_get_all() function is present + # + # Added by commit f08c2e286 ("clk: add managed version of clk_bulk_get_all") + # + CODE=" + #if defined(NV_LINUX_CLK_H_PRESENT) + #include + #endif + void conftest_devm_clk_bulk_get_all(void) + { + devm_clk_bulk_get_all(); + } + " + compile_check_conftest "$CODE" "NV_DEVM_CLK_BULK_GET_ALL_PRESENT" "" "functions" + ;; + + mmget_not_zero) + # + # Determine if mmget_not_zero() function is present + # + # mmget_not_zero() function was added by commit + # d2005e3f41d4f9299e2df6a967c8beb5086967a9 ("userfaultfd: don't pin + # the user memory in userfaultfd_file_create()") in v4.7 + # (2016-05-20) in linux/sched.h but then moved to linux/sched/mm.h + # by commit 68e21be2916b359fd8afb536c1911dc014cfd03e + # ("sched/headers: Move task->mm handling methods to + # ") in v4.11 (2017-02-01). + CODE=" + #if defined(NV_LINUX_SCHED_MM_H_PRESENT) + #include + #elif defined(NV_LINUX_SCHED_H_PRESENT) + #include + #endif + void conftest_mmget_not_zero(void) { + mmget_not_zero(); + }" + + compile_check_conftest "$CODE" "NV_MMGET_NOT_ZERO_PRESENT" "" "functions" + ;; + dma_resv_add_fence) # # Determine if the dma_resv_add_fence() function is present. @@ -5377,7 +5367,7 @@ compile_test() { # Determine if 'num_registered_fb' variable is present. # # 'num_registered_fb' was removed by commit 5727dcfd8486 - # ("fbdev: Make registered_fb[] private to fbmem.c) for + # ("fbdev: Make registered_fb[] private to fbmem.c") for # v5.20 linux-next (2022-07-27). # CODE=" @@ -5389,6 +5379,31 @@ compile_test() { compile_check_conftest "$CODE" "NV_NUM_REGISTERED_FB_PRESENT" "" "types" ;; + acpi_video_backlight_use_native) + # + # Determine if acpi_video_backlight_use_native() function is present + # + # acpi_video_backlight_use_native was added by commit 2600bfa3df99 + # (ACPI: video: Add acpi_video_backlight_use_native() helper) for + # v6.0 (2022-08-17). Note: the include directive for + # in this conftest is necessary in order to support kernels between + # commit 0b9f7d93ca61 ("ACPI / i915: ignore firmware requests for + # backlight change") for v3.16 (2014-07-07) and commit 3bd6bce369f5 + # ("ACPI / video: Port to new backlight interface selection API") + # for v4.2 (2015-07-16). Kernels within this range use the 'bool' + # type and the related 'false' value in without first + # including the definitions of that type and value. + # + CODE=" + #include + #include + void conftest_acpi_video_backglight_use_native(void) { + acpi_video_backlight_use_native(0); + }" + + compile_check_conftest "$CODE" "NV_ACPI_VIDEO_BACKLIGHT_USE_NATIVE" "" "functions" + ;; + # When adding a new conftest entry, please use the correct format for # specifying the relevant upstream Linux kernel commit. # diff --git a/kernel-open/nvidia-drm/nvidia-drm-connector.c b/kernel-open/nvidia-drm/nvidia-drm-connector.c index 6fbcd6372..77a6120e4 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-connector.c +++ b/kernel-open/nvidia-drm/nvidia-drm-connector.c @@ -118,6 +118,11 @@ __nv_drm_detect_encoder(struct NvKmsKapiDynamicDisplayParams *pDetectParams, return false; } +#if defined(NV_DRM_CONNECTOR_HAS_VRR_CAPABLE_PROPERTY) + drm_connector_attach_vrr_capable_property(&nv_connector->base); + drm_connector_set_vrr_capable_property(&nv_connector->base, pDetectParams->vrrSupported ? true : false); +#endif + if (pDetectParams->connected) { if (!pDetectParams->overrideEdid && pDetectParams->edid.bufferSize) { diff --git a/kernel-open/nvidia-drm/nvidia-drm-crtc.c b/kernel-open/nvidia-drm/nvidia-drm-crtc.c index 6380fe7b1..51d6324cb 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-crtc.c +++ b/kernel-open/nvidia-drm/nvidia-drm-crtc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -46,6 +46,35 @@ #include #endif +#if defined(NV_DRM_HAS_HDR_OUTPUT_METADATA) +static int +nv_drm_atomic_replace_property_blob_from_id(struct drm_device *dev, + struct drm_property_blob **blob, + uint64_t blob_id, + ssize_t expected_size) +{ + struct drm_property_blob *new_blob = NULL; + + if (blob_id != 0) { + new_blob = drm_property_lookup_blob(dev, blob_id); + if (new_blob == NULL) { + return -EINVAL; + } + + if ((expected_size > 0) && + (new_blob->length != expected_size)) { + drm_property_blob_put(new_blob); + return -EINVAL; + } + } + + drm_property_replace_blob(blob, new_blob); + drm_property_blob_put(new_blob); + + return 0; +} +#endif + static void nv_drm_plane_destroy(struct drm_plane *plane) { struct nv_drm_plane *nv_plane = to_nv_plane(plane); @@ -84,9 +113,6 @@ cursor_plane_req_config_update(struct drm_plane *plane, { struct nv_drm_plane *nv_plane = to_nv_plane(plane); struct NvKmsKapiCursorRequestedConfig old_config = *req_config; - struct nv_drm_device *nv_dev = to_nv_device(plane->dev); - struct nv_drm_plane_state *nv_drm_plane_state = - to_nv_drm_plane_state(plane_state); if (plane_state->fb == NULL) { cursor_req_config_disable(req_config); @@ -186,7 +212,6 @@ plane_req_config_update(struct drm_plane *plane, struct nv_drm_device *nv_dev = to_nv_device(plane->dev); struct nv_drm_plane_state *nv_drm_plane_state = to_nv_drm_plane_state(plane_state); - int ret = 0; if (plane_state->fb == NULL) { plane_req_config_disable(req_config); @@ -309,6 +334,9 @@ plane_req_config_update(struct drm_plane *plane, nv_plane->defaultCompositionMode; #endif + req_config->config.inputColorSpace = + nv_drm_plane_state->input_colorspace; + req_config->config.syncptParams.preSyncptSpecified = false; req_config->config.syncptParams.postSyncptRequested = false; @@ -320,10 +348,10 @@ plane_req_config_update(struct drm_plane *plane, #if defined(NV_LINUX_NVHOST_H_PRESENT) && defined(CONFIG_TEGRA_GRHOST) #if defined(NV_NVHOST_DMA_FENCE_UNPACK_PRESENT) if (plane_state->fence != NULL) { - ret = nvhost_dma_fence_unpack( - plane_state->fence, - &req_config->config.syncptParams.preSyncptId, - &req_config->config.syncptParams.preSyncptValue); + int ret = nvhost_dma_fence_unpack( + plane_state->fence, + &req_config->config.syncptParams.preSyncptId, + &req_config->config.syncptParams.preSyncptValue); if (ret != 0) { return ret; } @@ -339,6 +367,60 @@ plane_req_config_update(struct drm_plane *plane, #endif } +#if defined(NV_DRM_HAS_HDR_OUTPUT_METADATA) + if (nv_drm_plane_state->hdr_output_metadata != NULL) { + struct hdr_output_metadata *hdr_metadata = + nv_drm_plane_state->hdr_output_metadata->data; + struct hdr_metadata_infoframe *info_frame = + &hdr_metadata->hdmi_metadata_type1; + struct nv_drm_device *nv_dev = to_nv_device(plane->dev); + uint32_t i; + + if (hdr_metadata->metadata_type != HDMI_STATIC_METADATA_TYPE1) { + NV_DRM_DEV_LOG_ERR(nv_dev, "Unsupported Metadata Type"); + return -1; + } + + for (i = 0; i < ARRAY_SIZE(info_frame->display_primaries); i ++) { + req_config->config.hdrMetadata.displayPrimaries[i].x = + info_frame->display_primaries[i].x; + req_config->config.hdrMetadata.displayPrimaries[i].y = + info_frame->display_primaries[i].y; + } + + req_config->config.hdrMetadata.whitePoint.x = + info_frame->white_point.x; + req_config->config.hdrMetadata.whitePoint.y = + info_frame->white_point.y; + req_config->config.hdrMetadata.maxDisplayMasteringLuminance = + info_frame->max_display_mastering_luminance; + req_config->config.hdrMetadata.minDisplayMasteringLuminance = + info_frame->min_display_mastering_luminance; + req_config->config.hdrMetadata.maxCLL = + info_frame->max_cll; + req_config->config.hdrMetadata.maxFALL = + info_frame->max_fall; + + req_config->config.hdrMetadataSpecified = true; + + switch (info_frame->eotf) { + case HDMI_EOTF_SMPTE_ST2084: + req_config->config.tf = NVKMS_OUTPUT_TF_PQ; + break; + case HDMI_EOTF_TRADITIONAL_GAMMA_SDR: + req_config->config.tf = + NVKMS_OUTPUT_TF_TRADITIONAL_GAMMA_SDR; + break; + default: + NV_DRM_DEV_LOG_ERR(nv_dev, "Unsupported EOTF"); + return -1; + } + } else { + req_config->config.hdrMetadataSpecified = false; + req_config->config.tf = NVKMS_OUTPUT_TF_NONE; + } +#endif + /* * Unconditionally mark the surface as changed, even if nothing changed, * so that we always get a flip event: a DRM client may flip with @@ -509,9 +591,21 @@ static int nv_drm_plane_atomic_set_property( nv_drm_plane_state->fd_user_ptr = u64_to_user_ptr(val); #endif return 0; - } else { - return -EINVAL; + } else if (property == nv_dev->nv_input_colorspace_property) { + nv_drm_plane_state->input_colorspace = val; + return 0; } +#if defined(NV_DRM_HAS_HDR_OUTPUT_METADATA) + else if (property == nv_dev->nv_hdr_output_metadata_property) { + return nv_drm_atomic_replace_property_blob_from_id( + nv_dev->dev, + &nv_drm_plane_state->hdr_output_metadata, + val, + sizeof(struct hdr_output_metadata)); + } +#endif + + return -EINVAL; } static int nv_drm_plane_atomic_get_property( @@ -521,12 +615,26 @@ static int nv_drm_plane_atomic_get_property( uint64_t *val) { struct nv_drm_device *nv_dev = to_nv_device(plane->dev); + const struct nv_drm_plane_state *nv_drm_plane_state = + to_nv_drm_plane_state_const(state); if (property == nv_dev->nv_out_fence_property) { return 0; - } else { - return -EINVAL; + } else if (property == nv_dev->nv_input_colorspace_property) { + *val = nv_drm_plane_state->input_colorspace; + return 0; } +#if defined(NV_DRM_HAS_HDR_OUTPUT_METADATA) + else if (property == nv_dev->nv_hdr_output_metadata_property) { + const struct nv_drm_plane_state *nv_drm_plane_state = + to_nv_drm_plane_state_const(state); + *val = nv_drm_plane_state->hdr_output_metadata ? + nv_drm_plane_state->hdr_output_metadata->base.id : 0; + return 0; + } +#endif + + return -EINVAL; } static struct drm_plane_state * @@ -544,6 +652,14 @@ nv_drm_plane_atomic_duplicate_state(struct drm_plane *plane) __drm_atomic_helper_plane_duplicate_state(plane, &nv_plane_state->base); nv_plane_state->fd_user_ptr = nv_old_plane_state->fd_user_ptr; + nv_plane_state->input_colorspace = nv_old_plane_state->input_colorspace; + +#if defined(NV_DRM_HAS_HDR_OUTPUT_METADATA) + nv_plane_state->hdr_output_metadata = nv_old_plane_state->hdr_output_metadata; + if (nv_plane_state->hdr_output_metadata) { + drm_property_blob_get(nv_plane_state->hdr_output_metadata); + } +#endif return &nv_plane_state->base; } @@ -557,6 +673,12 @@ static inline void __nv_drm_plane_atomic_destroy_state( #else __drm_atomic_helper_plane_destroy_state(state); #endif + +#if defined(NV_DRM_HAS_HDR_OUTPUT_METADATA) + struct nv_drm_plane_state *nv_drm_plane_state = + to_nv_drm_plane_state(state); + drm_property_blob_put(nv_drm_plane_state->hdr_output_metadata); +#endif } static void nv_drm_plane_atomic_destroy_state( @@ -803,7 +925,8 @@ static const struct drm_crtc_helper_funcs nv_crtc_helper_funcs = { }; static void nv_drm_plane_install_properties( - struct drm_plane *plane) + struct drm_plane *plane, + NvBool supportsHDR) { struct nv_drm_device *nv_dev = to_nv_device(plane->dev); @@ -811,6 +934,19 @@ static void nv_drm_plane_install_properties( drm_object_attach_property( &plane->base, nv_dev->nv_out_fence_property, 0); } + + if (nv_dev->nv_input_colorspace_property) { + drm_object_attach_property( + &plane->base, nv_dev->nv_input_colorspace_property, + NVKMS_INPUT_COLORSPACE_NONE); + } + +#if defined(NV_DRM_HAS_HDR_OUTPUT_METADATA) + if (supportsHDR && nv_dev->nv_hdr_output_metadata_property) { + drm_object_attach_property( + &plane->base, nv_dev->nv_hdr_output_metadata_property, 0); + } +#endif } static void @@ -990,7 +1126,9 @@ nv_drm_plane_create(struct drm_device *dev, drm_plane_helper_add(plane, &nv_plane_helper_funcs); if (plane_type != DRM_PLANE_TYPE_CURSOR) { - nv_drm_plane_install_properties(plane); + nv_drm_plane_install_properties( + plane, + pResInfo->supportsHDR[layer_idx]); } __nv_drm_plane_create_alpha_blending_properties( @@ -1141,11 +1279,13 @@ void nv_drm_enumerate_crtcs_and_planes( } for (layer = 0; layer < pResInfo->numLayers[i]; layer++) { + struct drm_plane *overlay_plane = NULL; + if (layer == NVKMS_KAPI_LAYER_PRIMARY_IDX) { continue; } - struct drm_plane *overlay_plane = + overlay_plane = nv_drm_plane_create(nv_dev->dev, DRM_PLANE_TYPE_OVERLAY, layer, diff --git a/kernel-open/nvidia-drm/nvidia-drm-crtc.h b/kernel-open/nvidia-drm/nvidia-drm-crtc.h index 061b235c7..f5db13022 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-crtc.h +++ b/kernel-open/nvidia-drm/nvidia-drm-crtc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -205,6 +205,10 @@ static inline struct nv_drm_plane *to_nv_plane(struct drm_plane *plane) struct nv_drm_plane_state { struct drm_plane_state base; s32 __user *fd_user_ptr; + enum NvKmsInputColorSpace input_colorspace; +#if defined(NV_DRM_HAS_HDR_OUTPUT_METADATA) + struct drm_property_blob *hdr_output_metadata; +#endif }; static inline struct nv_drm_plane_state *to_nv_drm_plane_state(struct drm_plane_state *state) @@ -212,6 +216,11 @@ static inline struct nv_drm_plane_state *to_nv_drm_plane_state(struct drm_plane_ return container_of(state, struct nv_drm_plane_state, base); } +static inline const struct nv_drm_plane_state *to_nv_drm_plane_state_const(const struct drm_plane_state *state) +{ + return container_of(state, const struct nv_drm_plane_state, base); +} + static inline struct nv_drm_crtc *to_nv_crtc(struct drm_crtc *crtc) { if (crtc == NULL) { diff --git a/kernel-open/nvidia-drm/nvidia-drm-drv.c b/kernel-open/nvidia-drm/nvidia-drm-drv.c index cf2080db3..ac504ecea 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-drv.c +++ b/kernel-open/nvidia-drm/nvidia-drm-drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -86,6 +86,23 @@ static struct nv_drm_device *dev_list = NULL; +static const char* nv_get_input_colorspace_name( + enum NvKmsInputColorSpace colorSpace) +{ + switch (colorSpace) { + case NVKMS_INPUT_COLORSPACE_NONE: + return "None"; + case NVKMS_INPUT_COLORSPACE_SCRGB_LINEAR: + return "IEC 61966-2-2 linear FP"; + case NVKMS_INPUT_COLORSPACE_BT2100_PQ: + return "ITU-R BT.2100-PQ YCbCr"; + default: + /* We shoudn't hit this */ + WARN_ON("Unsupported input colorspace"); + return "None"; + } +}; + #if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE) static void nv_drm_output_poll_changed(struct drm_device *dev) @@ -332,6 +349,15 @@ static void nv_drm_enumerate_encoders_and_connectors */ static int nv_drm_create_properties(struct nv_drm_device *nv_dev) { + struct drm_prop_enum_list enum_list[3] = { }; + int i, len = 0; + + for (i = 0; i < 3; i++) { + enum_list[len].type = i; + enum_list[len].name = nv_get_input_colorspace_name(i); + len++; + } + #if defined(NV_LINUX_NVHOST_H_PRESENT) && defined(CONFIG_TEGRA_GRHOST) if (!nv_dev->supportsSyncpts) { return 0; @@ -345,6 +371,23 @@ static int nv_drm_create_properties(struct nv_drm_device *nv_dev) } #endif + nv_dev->nv_input_colorspace_property = + drm_property_create_enum(nv_dev->dev, 0, "NV_INPUT_COLORSPACE", + enum_list, len); + if (nv_dev->nv_input_colorspace_property == NULL) { + NV_DRM_LOG_ERR("Failed to create NV_INPUT_COLORSPACE property"); + return -ENOMEM; + } + +#if defined(NV_DRM_HAS_HDR_OUTPUT_METADATA) + nv_dev->nv_hdr_output_metadata_property = + drm_property_create(nv_dev->dev, DRM_MODE_PROP_BLOB, + "NV_HDR_STATIC_METADATA", 0); + if (nv_dev->nv_hdr_output_metadata_property == NULL) { + return -ENOMEM; + } +#endif + return 0; } diff --git a/kernel-open/nvidia-drm/nvidia-drm-format.c b/kernel-open/nvidia-drm/nvidia-drm-format.c index c8a295936..0f1bff8da 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-format.c +++ b/kernel-open/nvidia-drm/nvidia-drm-format.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -40,9 +40,16 @@ static const u32 nvkms_to_drm_format[] = { [NvKmsSurfaceMemoryFormatR5G6B5] = DRM_FORMAT_RGB565, [NvKmsSurfaceMemoryFormatA8R8G8B8] = DRM_FORMAT_ARGB8888, [NvKmsSurfaceMemoryFormatX8R8G8B8] = DRM_FORMAT_XRGB8888, + [NvKmsSurfaceMemoryFormatX8B8G8R8] = DRM_FORMAT_XBGR8888, [NvKmsSurfaceMemoryFormatA2B10G10R10] = DRM_FORMAT_ABGR2101010, [NvKmsSurfaceMemoryFormatX2B10G10R10] = DRM_FORMAT_XBGR2101010, [NvKmsSurfaceMemoryFormatA8B8G8R8] = DRM_FORMAT_ABGR8888, +#if defined(DRM_FORMAT_ABGR16161616F) + [NvKmsSurfaceMemoryFormatRF16GF16BF16AF16] = DRM_FORMAT_ABGR16161616F, +#endif +#if defined(DRM_FORMAT_XBGR16161616F) + [NvKmsSurfaceMemoryFormatRF16GF16BF16XF16] = DRM_FORMAT_XBGR16161616F, +#endif [NvKmsSurfaceMemoryFormatY8_U8__Y8_V8_N422] = DRM_FORMAT_YUYV, [NvKmsSurfaceMemoryFormatU8_Y8__V8_Y8_N422] = DRM_FORMAT_UYVY, diff --git a/kernel-open/nvidia-drm/nvidia-drm-gem-user-memory.c b/kernel-open/nvidia-drm/nvidia-drm-gem-user-memory.c index e554adc27..64acb928e 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-gem-user-memory.c +++ b/kernel-open/nvidia-drm/nvidia-drm-gem-user-memory.c @@ -113,7 +113,6 @@ static vm_fault_t __nv_drm_gem_user_memory_handle_vma_fault( page_offset = vmf->pgoff - drm_vma_node_start(&gem->vma_node); BUG_ON(page_offset > nv_user_memory->pages_count); - ret = vm_insert_page(vma, address, nv_user_memory->pages[page_offset]); switch (ret) { case 0: diff --git a/kernel-open/nvidia-drm/nvidia-drm-linux.c b/kernel-open/nvidia-drm/nvidia-drm-linux.c index 069814de2..561afa8d0 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-linux.c +++ b/kernel-open/nvidia-drm/nvidia-drm-linux.c @@ -93,8 +93,6 @@ int nv_drm_lock_user_pages(unsigned long address, { struct mm_struct *mm = current->mm; struct page **user_pages; - const int write = 1; - const int force = 0; int pages_pinned; user_pages = nv_drm_calloc(pages_count, sizeof(*user_pages)); @@ -105,7 +103,7 @@ int nv_drm_lock_user_pages(unsigned long address, nv_mmap_read_lock(mm); - pages_pinned = NV_GET_USER_PAGES(address, pages_count, write, force, + pages_pinned = NV_PIN_USER_PAGES(address, pages_count, FOLL_WRITE, user_pages, NULL); nv_mmap_read_unlock(mm); @@ -123,7 +121,7 @@ failed: int i; for (i = 0; i < pages_pinned; i++) { - put_page(user_pages[i]); + NV_UNPIN_USER_PAGE(user_pages[i]); } } @@ -138,8 +136,7 @@ void nv_drm_unlock_user_pages(unsigned long pages_count, struct page **pages) for (i = 0; i < pages_count; i++) { set_page_dirty_lock(pages[i]); - - put_page(pages[i]); + NV_UNPIN_USER_PAGE(pages[i]); } nv_drm_free(pages); @@ -174,12 +171,7 @@ static void __exit nv_linux_drm_exit(void) module_init(nv_linux_drm_init); module_exit(nv_linux_drm_exit); -#if defined(MODULE_LICENSE) MODULE_LICENSE("Dual MIT/GPL"); -#endif -#if defined(MODULE_INFO) - MODULE_INFO(supported, "external"); -#endif -#if defined(MODULE_VERSION) - MODULE_VERSION(NV_VERSION_STRING); -#endif + +MODULE_INFO(supported, "external"); +MODULE_VERSION(NV_VERSION_STRING); diff --git a/kernel-open/nvidia-drm/nvidia-drm-modeset.c b/kernel-open/nvidia-drm/nvidia-drm-modeset.c index 9132af9ad..d8cdf050b 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-modeset.c +++ b/kernel-open/nvidia-drm/nvidia-drm-modeset.c @@ -93,9 +93,6 @@ static bool __will_generate_flip_event(struct drm_crtc *crtc, to_nv_crtc_state(new_crtc_state); struct drm_plane_state *old_plane_state = NULL; struct drm_plane *plane = NULL; - struct drm_plane *primary_plane = crtc->primary; - bool primary_event = false; - bool overlay_event = false; int i; if (!old_crtc_state->active && !new_crtc_state->active) { @@ -274,6 +271,9 @@ nv_drm_atomic_apply_modeset_config(struct drm_device *dev, nv_new_crtc_state->nv_flip = NULL; } +#if defined(NV_DRM_CRTC_STATE_HAS_VRR_ENABLED) + requested_config->headRequestedConfig[nv_crtc->head].modeSetConfig.vrrEnabled = new_crtc_state->vrr_enabled; +#endif } } diff --git a/kernel-open/nvidia-drm/nvidia-drm-priv.h b/kernel-open/nvidia-drm/nvidia-drm-priv.h index dce6a531f..91b7b4f21 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-priv.h +++ b/kernel-open/nvidia-drm/nvidia-drm-priv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -122,6 +122,11 @@ struct nv_drm_device { NvBool supportsSyncpts; struct drm_property *nv_out_fence_property; + struct drm_property *nv_input_colorspace_property; + +#if defined(NV_DRM_HAS_HDR_OUTPUT_METADATA) + struct drm_property *nv_hdr_output_metadata_property; +#endif struct nv_drm_device *next; }; diff --git a/kernel-open/nvidia-drm/nvidia-drm.Kbuild b/kernel-open/nvidia-drm/nvidia-drm.Kbuild index e1ddf454d..4d012bed3 100644 --- a/kernel-open/nvidia-drm/nvidia-drm.Kbuild +++ b/kernel-open/nvidia-drm/nvidia-drm.Kbuild @@ -59,11 +59,14 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_dev_unref NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_reinit_primary_mode_group NV_CONFTEST_FUNCTION_COMPILE_TESTS += get_user_pages_remote NV_CONFTEST_FUNCTION_COMPILE_TESTS += get_user_pages +NV_CONFTEST_FUNCTION_COMPILE_TESTS += pin_user_pages_remote +NV_CONFTEST_FUNCTION_COMPILE_TESTS += pin_user_pages NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_gem_object_lookup NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_atomic_state_ref_counting NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_driver_has_gem_prime_res_obj NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_atomic_helper_connector_dpms NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_connector_funcs_have_mode_in_name +NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_connector_has_vrr_capable_property NV_CONFTEST_FUNCTION_COMPILE_TESTS += vmf_insert_pfn NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_framebuffer_get NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_gem_object_get @@ -100,6 +103,7 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += vm_fault_t NV_CONFTEST_TYPE_COMPILE_TESTS += drm_gem_object_has_resv NV_CONFTEST_TYPE_COMPILE_TESTS += drm_crtc_state_has_async_flip NV_CONFTEST_TYPE_COMPILE_TESTS += drm_crtc_state_has_pageflip_flags +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_crtc_state_has_vrr_enabled NV_CONFTEST_TYPE_COMPILE_TESTS += drm_format_modifiers_present NV_CONFTEST_TYPE_COMPILE_TESTS += mm_has_mmap_lock NV_CONFTEST_TYPE_COMPILE_TESTS += drm_vma_node_is_allowed_has_tag_arg @@ -115,6 +119,7 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += drm_plane_atomic_check_has_atomic_state_arg NV_CONFTEST_TYPE_COMPILE_TESTS += drm_device_has_pdev NV_CONFTEST_TYPE_COMPILE_TESTS += drm_crtc_state_has_no_vblank NV_CONFTEST_TYPE_COMPILE_TESTS += drm_mode_config_has_allow_fb_modifiers +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_has_hdr_output_metadata NV_CONFTEST_TYPE_COMPILE_TESTS += dma_resv_add_fence NV_CONFTEST_TYPE_COMPILE_TESTS += dma_resv_reserve_fences NV_CONFTEST_TYPE_COMPILE_TESTS += reservation_object_reserve_shared_has_num_fences_arg diff --git a/kernel-open/nvidia-modeset/nv-kthread-q.c b/kernel-open/nvidia-modeset/nv-kthread-q.c index 5a95f4a40..31a54cc05 100644 --- a/kernel-open/nvidia-modeset/nv-kthread-q.c +++ b/kernel-open/nvidia-modeset/nv-kthread-q.c @@ -169,7 +169,6 @@ void nv_kthread_q_stop(nv_kthread_q_t *q) // // This function is never invoked when there is no NUMA preference (preferred // node is NUMA_NO_NODE). -#if NV_KTHREAD_Q_SUPPORTS_AFFINITY() == 1 static struct task_struct *thread_create_on_node(int (*threadfn)(void *data), nv_kthread_q_t *q, int preferred_node, @@ -217,7 +216,6 @@ static struct task_struct *thread_create_on_node(int (*threadfn)(void *data), return thread[i]; } -#endif int nv_kthread_q_init_on_node(nv_kthread_q_t *q, const char *q_name, int preferred_node) { @@ -231,11 +229,7 @@ int nv_kthread_q_init_on_node(nv_kthread_q_t *q, const char *q_name, int preferr q->q_kthread = kthread_create(_main_loop, q, q_name); } else { -#if NV_KTHREAD_Q_SUPPORTS_AFFINITY() == 1 q->q_kthread = thread_create_on_node(_main_loop, q, preferred_node, q_name); -#else - return -ENOTSUPP; -#endif } if (IS_ERR(q->q_kthread)) { diff --git a/kernel-open/nvidia-modeset/nvidia-modeset-linux.c b/kernel-open/nvidia-modeset/nvidia-modeset-linux.c index 53b9b4a27..fe425c115 100644 --- a/kernel-open/nvidia-modeset/nvidia-modeset-linux.c +++ b/kernel-open/nvidia-modeset/nvidia-modeset-linux.c @@ -35,6 +35,8 @@ #include #include +#include + #include "nvstatus.h" #include "nv-register-module.h" @@ -956,6 +958,12 @@ nvkms_register_backlight(NvU32 gpu_id, NvU32 display_id, void *drv_priv, struct nvkms_backlight_device *nvkms_bd = NULL; int i; +#if defined(NV_ACPI_VIDEO_BACKLIGHT_USE_NATIVE) + if (!acpi_video_backlight_use_native()) { + return NULL; + } +#endif + gpu_info = nvkms_alloc(NV_MAX_GPUS * sizeof(*gpu_info), NV_TRUE); if (gpu_info == NULL) { return NULL; @@ -1346,29 +1354,7 @@ static void nvkms_proc_exit(void) return; } -#if defined(NV_PROC_REMOVE_PRESENT) proc_remove(nvkms_proc_dir); -#else - /* - * On kernel versions without proc_remove(), we need to explicitly - * remove each proc file beneath nvkms_proc_dir. - * nvkms_proc_init() only creates files directly under - * nvkms_proc_dir, so those are the only files we need to remove - * here: warn if there is any deeper directory nesting. - */ - { - struct proc_dir_entry *entry = nvkms_proc_dir->subdir; - - while (entry != NULL) { - struct proc_dir_entry *next = entry->next; - WARN_ON(entry->subdir != NULL); - remove_proc_entry(entry->name, entry->parent); - entry = next; - } - } - - remove_proc_entry(nvkms_proc_dir->name, nvkms_proc_dir->parent); -#endif /* NV_PROC_REMOVE_PRESENT */ #endif /* CONFIG_PROC_FS */ } @@ -1630,12 +1616,7 @@ restart: module_init(nvkms_init); module_exit(nvkms_exit); -#if defined(MODULE_LICENSE) MODULE_LICENSE("Dual MIT/GPL"); -#endif -#if defined(MODULE_INFO) - MODULE_INFO(supported, "external"); -#endif -#if defined(MODULE_VERSION) - MODULE_VERSION(NV_VERSION_STRING); -#endif + +MODULE_INFO(supported, "external"); +MODULE_VERSION(NV_VERSION_STRING); diff --git a/kernel-open/nvidia-modeset/nvidia-modeset.Kbuild b/kernel-open/nvidia-modeset/nvidia-modeset.Kbuild index 0475f26cf..ebf3f048b 100644 --- a/kernel-open/nvidia-modeset/nvidia-modeset.Kbuild +++ b/kernel-open/nvidia-modeset/nvidia-modeset.Kbuild @@ -85,15 +85,11 @@ $(obj)/$(NVIDIA_MODESET_INTERFACE): $(addprefix $(obj)/,$(NVIDIA_MODESET_OBJECTS NV_OBJECTS_DEPEND_ON_CONFTEST += $(NVIDIA_MODESET_OBJECTS) -NV_CONFTEST_TYPE_COMPILE_TESTS += file_operations -NV_CONFTEST_TYPE_COMPILE_TESTS += node_states_n_memory NV_CONFTEST_TYPE_COMPILE_TESTS += timespec64 NV_CONFTEST_TYPE_COMPILE_TESTS += proc_ops NV_CONFTEST_FUNCTION_COMPILE_TESTS += pde_data -NV_CONFTEST_FUNCTION_COMPILE_TESTS += proc_remove NV_CONFTEST_FUNCTION_COMPILE_TESTS += timer_setup -NV_CONFTEST_FUNCTION_COMPILE_TESTS += kthread_create_on_node NV_CONFTEST_FUNCTION_COMPILE_TESTS += list_is_first NV_CONFTEST_FUNCTION_COMPILE_TESTS += ktime_get_real_ts64 NV_CONFTEST_FUNCTION_COMPILE_TESTS += ktime_get_raw_ts64 -NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_kthread_create_on_node +NV_CONFTEST_FUNCTION_COMPILE_TESTS += acpi_video_backlight_use_native diff --git a/kernel-open/nvidia-peermem/nvidia-peermem.Kbuild b/kernel-open/nvidia-peermem/nvidia-peermem.Kbuild index 3204180a7..d2bcaf8d0 100644 --- a/kernel-open/nvidia-peermem/nvidia-peermem.Kbuild +++ b/kernel-open/nvidia-peermem/nvidia-peermem.Kbuild @@ -30,8 +30,18 @@ NVIDIA_PEERMEM_CFLAGS += -UDEBUG -U_DEBUG -DNDEBUG -DNV_BUILD_MODULE_INSTANCES=0 # MOFED's Module.symvers is needed for the build # to find the additional ib_* symbols. # +# Also, MOFED doesn't use kbuild ARCH names. +# So adapt OFA_ARCH to match MOFED's conventions. +# +ifeq ($(ARCH), arm64) + OFA_ARCH := aarch64 +else ifeq ($(ARCH), powerpc) + OFA_ARCH := ppc64le +else + OFA_ARCH := $(ARCH) +endif OFA_DIR := /usr/src/ofa_kernel -OFA_CANDIDATES = $(OFA_DIR)/$(ARCH)/$(KERNELRELEASE) $(OFA_DIR)/$(KERNELRELEASE) $(OFA_DIR)/default /var/lib/dkms/mlnx-ofed-kernel +OFA_CANDIDATES = $(OFA_DIR)/$(OFA_ARCH)/$(KERNELRELEASE) $(OFA_DIR)/$(KERNELRELEASE) $(OFA_DIR)/default /var/lib/dkms/mlnx-ofed-kernel MLNX_OFED_KERNEL := $(shell for d in $(OFA_CANDIDATES); do \ if [ -d "$$d" ]; then \ echo "$$d"; \ diff --git a/kernel-open/nvidia-uvm/nv-kthread-q-selftest.c b/kernel-open/nvidia-uvm/nv-kthread-q-selftest.c index bb67754e7..88b70a4e8 100644 --- a/kernel-open/nvidia-uvm/nv-kthread-q-selftest.c +++ b/kernel-open/nvidia-uvm/nv-kthread-q-selftest.c @@ -481,16 +481,6 @@ static int _check_cpu_affinity_test(void) int result, node; nv_kthread_q_t local_q; - // If the API does not support CPU affinity, check whether the correct - // error code is returned. - // Non-affinitized queue allocation has been verified by previous test - // so just ensure that the affinitized version also works. - if (!NV_KTHREAD_Q_SUPPORTS_AFFINITY()) { - result = nv_kthread_q_init_on_node(&local_q, "should_fail", 0); - TEST_CHECK_RET(result == -ENOTSUPP); - return 0; - } - for_each_online_node(node) { unsigned i; const unsigned max_i = 100; diff --git a/kernel-open/nvidia-uvm/nv-kthread-q.c b/kernel-open/nvidia-uvm/nv-kthread-q.c index 5a95f4a40..31a54cc05 100644 --- a/kernel-open/nvidia-uvm/nv-kthread-q.c +++ b/kernel-open/nvidia-uvm/nv-kthread-q.c @@ -169,7 +169,6 @@ void nv_kthread_q_stop(nv_kthread_q_t *q) // // This function is never invoked when there is no NUMA preference (preferred // node is NUMA_NO_NODE). -#if NV_KTHREAD_Q_SUPPORTS_AFFINITY() == 1 static struct task_struct *thread_create_on_node(int (*threadfn)(void *data), nv_kthread_q_t *q, int preferred_node, @@ -217,7 +216,6 @@ static struct task_struct *thread_create_on_node(int (*threadfn)(void *data), return thread[i]; } -#endif int nv_kthread_q_init_on_node(nv_kthread_q_t *q, const char *q_name, int preferred_node) { @@ -231,11 +229,7 @@ int nv_kthread_q_init_on_node(nv_kthread_q_t *q, const char *q_name, int preferr q->q_kthread = kthread_create(_main_loop, q, q_name); } else { -#if NV_KTHREAD_Q_SUPPORTS_AFFINITY() == 1 q->q_kthread = thread_create_on_node(_main_loop, q, preferred_node, q_name); -#else - return -ENOTSUPP; -#endif } if (IS_ERR(q->q_kthread)) { diff --git a/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild b/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild index e1af6db88..cdc636193 100644 --- a/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild +++ b/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild @@ -67,17 +67,11 @@ endif NV_OBJECTS_DEPEND_ON_CONFTEST += $(NVIDIA_UVM_OBJECTS) -NV_CONFTEST_FUNCTION_COMPILE_TESTS += address_space_init_once -NV_CONFTEST_FUNCTION_COMPILE_TESTS += vzalloc NV_CONFTEST_FUNCTION_COMPILE_TESTS += wait_on_bit_lock_argument_count NV_CONFTEST_FUNCTION_COMPILE_TESTS += pde_data -NV_CONFTEST_FUNCTION_COMPILE_TESTS += proc_remove -NV_CONFTEST_FUNCTION_COMPILE_TESTS += bitmap_clear -NV_CONFTEST_FUNCTION_COMPILE_TESTS += usleep_range NV_CONFTEST_FUNCTION_COMPILE_TESTS += radix_tree_empty NV_CONFTEST_FUNCTION_COMPILE_TESTS += radix_tree_replace_slot NV_CONFTEST_FUNCTION_COMPILE_TESTS += pnv_npu2_init_context -NV_CONFTEST_FUNCTION_COMPILE_TESTS += kthread_create_on_node NV_CONFTEST_FUNCTION_COMPILE_TESTS += vmf_insert_pfn NV_CONFTEST_FUNCTION_COMPILE_TESTS += cpumask_of_node NV_CONFTEST_FUNCTION_COMPILE_TESTS += list_is_first @@ -88,17 +82,16 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += set_pages_uc NV_CONFTEST_FUNCTION_COMPILE_TESTS += ktime_get_raw_ts64 NV_CONFTEST_FUNCTION_COMPILE_TESTS += ioasid_get NV_CONFTEST_FUNCTION_COMPILE_TESTS += migrate_vma_setup +NV_CONFTEST_FUNCTION_COMPILE_TESTS += mmget_not_zero -NV_CONFTEST_TYPE_COMPILE_TESTS += file_operations -NV_CONFTEST_TYPE_COMPILE_TESTS += kuid_t -NV_CONFTEST_TYPE_COMPILE_TESTS += address_space NV_CONFTEST_TYPE_COMPILE_TESTS += backing_dev_info NV_CONFTEST_TYPE_COMPILE_TESTS += mm_context_t NV_CONFTEST_TYPE_COMPILE_TESTS += get_user_pages_remote NV_CONFTEST_TYPE_COMPILE_TESTS += get_user_pages +NV_CONFTEST_TYPE_COMPILE_TESTS += pin_user_pages_remote +NV_CONFTEST_TYPE_COMPILE_TESTS += pin_user_pages NV_CONFTEST_TYPE_COMPILE_TESTS += vm_fault_has_address NV_CONFTEST_TYPE_COMPILE_TESTS += vm_ops_fault_removed_vma_arg -NV_CONFTEST_TYPE_COMPILE_TESTS += node_states_n_memory NV_CONFTEST_TYPE_COMPILE_TESTS += kmem_cache_has_kobj_remove_work NV_CONFTEST_TYPE_COMPILE_TESTS += sysfs_slab_unlink NV_CONFTEST_TYPE_COMPILE_TESTS += vm_fault_t diff --git a/kernel-open/nvidia-uvm/uvm.c b/kernel-open/nvidia-uvm/uvm.c index 6985dc56a..f537c7e1b 100644 --- a/kernel-open/nvidia-uvm/uvm.c +++ b/kernel-open/nvidia-uvm/uvm.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2021 NVIDIA Corporation + Copyright (c) 2015-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -41,73 +41,6 @@ static dev_t g_uvm_base_dev; static struct cdev g_uvm_cdev; -// List of fault service contexts for CPU faults -static LIST_HEAD(g_cpu_service_block_context_list); - -static uvm_spinlock_t g_cpu_service_block_context_list_lock; - -NV_STATUS uvm_service_block_context_init(void) -{ - unsigned num_preallocated_contexts = 4; - - uvm_spin_lock_init(&g_cpu_service_block_context_list_lock, UVM_LOCK_ORDER_LEAF); - - // Pre-allocate some fault service contexts for the CPU and add them to the global list - while (num_preallocated_contexts-- > 0) { - uvm_service_block_context_t *service_context = uvm_kvmalloc(sizeof(*service_context)); - if (!service_context) - return NV_ERR_NO_MEMORY; - - list_add(&service_context->cpu_fault.service_context_list, &g_cpu_service_block_context_list); - } - - return NV_OK; -} - -void uvm_service_block_context_exit(void) -{ - uvm_service_block_context_t *service_context, *service_context_tmp; - - // Free fault service contexts for the CPU and add clear the global list - list_for_each_entry_safe(service_context, service_context_tmp, &g_cpu_service_block_context_list, - cpu_fault.service_context_list) { - uvm_kvfree(service_context); - } - INIT_LIST_HEAD(&g_cpu_service_block_context_list); -} - -// Get a fault service context from the global list or allocate a new one if there are no -// available entries -static uvm_service_block_context_t *uvm_service_block_context_cpu_alloc(void) -{ - uvm_service_block_context_t *service_context; - - uvm_spin_lock(&g_cpu_service_block_context_list_lock); - - service_context = list_first_entry_or_null(&g_cpu_service_block_context_list, uvm_service_block_context_t, - cpu_fault.service_context_list); - - if (service_context) - list_del(&service_context->cpu_fault.service_context_list); - - uvm_spin_unlock(&g_cpu_service_block_context_list_lock); - - if (!service_context) - service_context = uvm_kvmalloc(sizeof(*service_context)); - - return service_context; -} - -// Put a fault service context in the global list -static void uvm_service_block_context_cpu_free(uvm_service_block_context_t *service_context) -{ - uvm_spin_lock(&g_cpu_service_block_context_list_lock); - - list_add(&service_context->cpu_fault.service_context_list, &g_cpu_service_block_context_list); - - uvm_spin_unlock(&g_cpu_service_block_context_list_lock); -} - static int uvm_open(struct inode *inode, struct file *filp) { NV_STATUS status = uvm_global_get_status(); @@ -489,139 +422,10 @@ static void uvm_vm_close_managed_entry(struct vm_area_struct *vma) static vm_fault_t uvm_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) { uvm_va_space_t *va_space = uvm_va_space_get(vma->vm_file); - uvm_va_block_t *va_block; - NvU64 fault_addr = nv_page_fault_va(vmf); - bool is_write = vmf->flags & FAULT_FLAG_WRITE; - NV_STATUS status = uvm_global_get_status(); - bool tools_enabled; - bool major_fault = false; - uvm_service_block_context_t *service_context; - uvm_global_processor_mask_t gpus_to_check_for_ecc; - if (status != NV_OK) - goto convert_error; - - // TODO: Bug 2583279: Lock tracking is disabled for the power management - // lock in order to suppress reporting of a lock policy violation. - // The violation consists in acquiring the power management lock multiple - // times, and it is manifested as an error during release. The - // re-acquisition of the power management locks happens upon re-entry in the - // UVM module, and it is benign on itself, but when combined with certain - // power management scenarios, it is indicative of a potential deadlock. - // Tracking will be re-enabled once the power management locking strategy is - // modified to avoid deadlocks. - if (!uvm_down_read_trylock_no_tracking(&g_uvm_global.pm.lock)) { - status = NV_ERR_BUSY_RETRY; - goto convert_error; - } - - service_context = uvm_service_block_context_cpu_alloc(); - if (!service_context) { - status = NV_ERR_NO_MEMORY; - goto unlock; - } - - service_context->cpu_fault.wakeup_time_stamp = 0; - - // The mmap_lock might be held in write mode, but the mode doesn't matter - // for the purpose of lock ordering and we don't rely on it being in write - // anywhere so just record it as read mode in all cases. - uvm_record_lock_mmap_lock_read(vma->vm_mm); - - do { - bool do_sleep = false; - if (status == NV_WARN_MORE_PROCESSING_REQUIRED) { - NvU64 now = NV_GETTIME(); - if (now < service_context->cpu_fault.wakeup_time_stamp) - do_sleep = true; - - if (do_sleep) - uvm_tools_record_throttling_start(va_space, fault_addr, UVM_ID_CPU); - - // Drop the VA space lock while we sleep - uvm_va_space_up_read(va_space); - - // usleep_range is preferred because msleep has a 20ms granularity - // and udelay uses a busy-wait loop. usleep_range uses high-resolution - // timers and, by adding a range, the Linux scheduler may coalesce - // our wakeup with others, thus saving some interrupts. - if (do_sleep) { - unsigned long nap_us = (service_context->cpu_fault.wakeup_time_stamp - now) / 1000; - - usleep_range(nap_us, nap_us + nap_us / 2); - } - } - - uvm_va_space_down_read(va_space); - - if (do_sleep) - uvm_tools_record_throttling_end(va_space, fault_addr, UVM_ID_CPU); - - status = uvm_va_block_find_create_managed(va_space, fault_addr, &va_block); - if (status != NV_OK) { - UVM_ASSERT_MSG(status == NV_ERR_NO_MEMORY, "status: %s\n", nvstatusToString(status)); - break; - } - - // Watch out, current->mm might not be vma->vm_mm - UVM_ASSERT(vma == uvm_va_range_vma(va_block->va_range)); - - // Loop until thrashing goes away. - status = uvm_va_block_cpu_fault(va_block, fault_addr, is_write, service_context); - } while (status == NV_WARN_MORE_PROCESSING_REQUIRED); - - if (status != NV_OK) { - UvmEventFatalReason reason; - - reason = uvm_tools_status_to_fatal_fault_reason(status); - UVM_ASSERT(reason != UvmEventFatalReasonInvalid); - - uvm_tools_record_cpu_fatal_fault(va_space, fault_addr, is_write, reason); - } - - tools_enabled = va_space->tools.enabled; - - if (status == NV_OK) { - uvm_va_space_global_gpus_in_mask(va_space, - &gpus_to_check_for_ecc, - &service_context->cpu_fault.gpus_to_check_for_ecc); - uvm_global_mask_retain(&gpus_to_check_for_ecc); - } - - uvm_va_space_up_read(va_space); - uvm_record_unlock_mmap_lock_read(vma->vm_mm); - - if (status == NV_OK) { - status = uvm_global_mask_check_ecc_error(&gpus_to_check_for_ecc); - uvm_global_mask_release(&gpus_to_check_for_ecc); - } - - if (tools_enabled) - uvm_tools_flush_events(); - - // Major faults involve I/O in order to resolve the fault. - // If any pages were DMA'ed between the GPU and host memory, that makes it a major fault. - // A process can also get statistics for major and minor faults by calling readproc(). - major_fault = service_context->cpu_fault.did_migrate; - uvm_service_block_context_cpu_free(service_context); - -unlock: - // TODO: Bug 2583279: See the comment above the matching lock acquisition - uvm_up_read_no_tracking(&g_uvm_global.pm.lock); - -convert_error: - switch (status) { - case NV_OK: - case NV_ERR_BUSY_RETRY: - return VM_FAULT_NOPAGE | (major_fault ? VM_FAULT_MAJOR : 0); - case NV_ERR_NO_MEMORY: - return VM_FAULT_OOM; - default: - return VM_FAULT_SIGBUS; - } + return uvm_va_space_cpu_fault_managed(va_space, vma, vmf); } - static vm_fault_t uvm_vm_fault_entry(struct vm_area_struct *vma, struct vm_fault *vmf) { UVM_ENTRY_RET(uvm_vm_fault(vma, vmf)); @@ -986,8 +790,6 @@ bool uvm_file_is_nvidia_uvm(struct file *filp) NV_STATUS uvm_test_register_unload_state_buffer(UVM_TEST_REGISTER_UNLOAD_STATE_BUFFER_PARAMS *params, struct file *filp) { long ret; - int write = 1; - int force = 0; struct page *page; NV_STATUS status = NV_OK; @@ -998,7 +800,7 @@ NV_STATUS uvm_test_register_unload_state_buffer(UVM_TEST_REGISTER_UNLOAD_STATE_B // are not used because unload_state_buf may be a managed memory pointer and // therefore a locking assertion from the CPU fault handler could be fired. nv_mmap_read_lock(current->mm); - ret = NV_GET_USER_PAGES(params->unload_state_buf, 1, write, force, &page, NULL); + ret = NV_PIN_USER_PAGES(params->unload_state_buf, 1, FOLL_WRITE, &page, NULL); nv_mmap_read_unlock(current->mm); if (ret < 0) @@ -1008,7 +810,7 @@ NV_STATUS uvm_test_register_unload_state_buffer(UVM_TEST_REGISTER_UNLOAD_STATE_B uvm_mutex_lock(&g_uvm_global.global_lock); if (g_uvm_global.unload_state.ptr) { - put_page(page); + NV_UNPIN_USER_PAGE(page); status = NV_ERR_IN_USE; goto error; } @@ -1027,7 +829,7 @@ static void uvm_test_unload_state_exit(void) { if (g_uvm_global.unload_state.ptr) { kunmap(g_uvm_global.unload_state.page); - put_page(g_uvm_global.unload_state.page); + NV_UNPIN_USER_PAGE(g_uvm_global.unload_state.page); } } diff --git a/kernel-open/nvidia-uvm/uvm_ats_faults.c b/kernel-open/nvidia-uvm/uvm_ats_faults.c index 7b7ee646c..cf1023103 100644 --- a/kernel-open/nvidia-uvm/uvm_ats_faults.c +++ b/kernel-open/nvidia-uvm/uvm_ats_faults.c @@ -25,9 +25,62 @@ #include "uvm_ats_faults.h" #include "uvm_migrate_pageable.h" +// TODO: Bug 2103669: Implement a real prefetching policy and remove or adapt +// these experimental parameters. These are intended to help guide that policy. +static unsigned int uvm_exp_perf_prefetch_ats_order_replayable = 0; +module_param(uvm_exp_perf_prefetch_ats_order_replayable, uint, 0644); +MODULE_PARM_DESC(uvm_exp_perf_prefetch_ats_order_replayable, + "Max order of pages (2^N) to prefetch on replayable ATS faults"); + +static unsigned int uvm_exp_perf_prefetch_ats_order_non_replayable = 0; +module_param(uvm_exp_perf_prefetch_ats_order_non_replayable, uint, 0644); +MODULE_PARM_DESC(uvm_exp_perf_prefetch_ats_order_non_replayable, + "Max order of pages (2^N) to prefetch on non-replayable ATS faults"); + +// Expand the fault region to the naturally-aligned region with order given by +// the module parameters, clamped to the vma containing fault_addr (if any). +// Note that this means the region contains fault_addr but may not begin at +// fault_addr. +static void expand_fault_region(struct mm_struct *mm, + NvU64 fault_addr, + uvm_fault_client_type_t client_type, + unsigned long *start, + unsigned long *size) +{ + struct vm_area_struct *vma; + unsigned int order; + unsigned long outer, aligned_start, aligned_size; + + *start = fault_addr; + *size = PAGE_SIZE; + + if (client_type == UVM_FAULT_CLIENT_TYPE_HUB) + order = uvm_exp_perf_prefetch_ats_order_non_replayable; + else + order = uvm_exp_perf_prefetch_ats_order_replayable; + + if (order == 0) + return; + + vma = find_vma_intersection(mm, fault_addr, fault_addr + 1); + if (!vma) + return; + + UVM_ASSERT(order < BITS_PER_LONG - PAGE_SHIFT); + + aligned_size = (1UL << order) * PAGE_SIZE; + + aligned_start = fault_addr & ~(aligned_size - 1); + + *start = max(vma->vm_start, aligned_start); + outer = min(vma->vm_end, aligned_start + aligned_size); + *size = outer - *start; +} + static NV_STATUS uvm_ats_service_fault(uvm_gpu_va_space_t *gpu_va_space, NvU64 fault_addr, - uvm_fault_access_type_t access_type) + uvm_fault_access_type_t access_type, + uvm_fault_client_type_t client_type) { uvm_va_space_t *va_space = gpu_va_space->va_space; struct mm_struct *mm = va_space->va_space_mm.mm; @@ -66,8 +119,6 @@ static NV_STATUS uvm_ats_service_fault(uvm_gpu_va_space_t *gpu_va_space, { .va_space = va_space, .mm = mm, - .start = fault_addr, - .length = PAGE_SIZE, .dst_id = gpu_va_space->gpu->parent->id, .dst_node_id = -1, .populate_permissions = write ? UVM_POPULATE_PERMISSIONS_WRITE : UVM_POPULATE_PERMISSIONS_ANY, @@ -79,6 +130,8 @@ static NV_STATUS uvm_ats_service_fault(uvm_gpu_va_space_t *gpu_va_space, UVM_ASSERT(uvm_ats_can_service_faults(gpu_va_space, mm)); + expand_fault_region(mm, fault_addr, client_type, &uvm_migrate_args.start, &uvm_migrate_args.length); + // TODO: Bug 2103669: Service more than a single fault at a time // // We are trying to use migrate_vma API in the kernel (if it exists) to @@ -131,7 +184,10 @@ NV_STATUS uvm_ats_service_fault_entry(uvm_gpu_va_space_t *gpu_va_space, } else { // TODO: Bug 2103669: Service more than a single fault at a time - status = uvm_ats_service_fault(gpu_va_space, current_entry->fault_address, service_access_type); + status = uvm_ats_service_fault(gpu_va_space, + current_entry->fault_address, + service_access_type, + current_entry->fault_source.client_type); } // Do not flag prefetch faults as fatal unless something fatal happened @@ -155,7 +211,8 @@ NV_STATUS uvm_ats_service_fault_entry(uvm_gpu_va_space_t *gpu_va_space, uvm_fault_access_type_mask_test(current_entry->access_type_mask, UVM_FAULT_ACCESS_TYPE_READ)) { status = uvm_ats_service_fault(gpu_va_space, current_entry->fault_address, - UVM_FAULT_ACCESS_TYPE_READ); + UVM_FAULT_ACCESS_TYPE_READ, + current_entry->fault_source.client_type); // If read accesses are also invalid, cancel the fault. If a // different error code is returned, exit diff --git a/kernel-open/nvidia-uvm/uvm_channel.c b/kernel-open/nvidia-uvm/uvm_channel.c index 18611cfbd..bcc9aeb2f 100644 --- a/kernel-open/nvidia-uvm/uvm_channel.c +++ b/kernel-open/nvidia-uvm/uvm_channel.c @@ -24,6 +24,7 @@ #include "uvm_channel.h" #include "uvm_api.h" +#include "uvm_common.h" #include "uvm_global.h" #include "uvm_hal.h" #include "uvm_procfs.h" @@ -68,6 +69,38 @@ typedef enum UVM_CHANNEL_UPDATE_MODE_FORCE_ALL } uvm_channel_update_mode_t; +static void channel_pool_lock_init(uvm_channel_pool_t *pool) +{ + if (uvm_channel_pool_is_proxy(pool)) + uvm_mutex_init(&pool->mutex, UVM_LOCK_ORDER_CHANNEL); + else + uvm_spin_lock_init(&pool->spinlock, UVM_LOCK_ORDER_CHANNEL); +} + +void uvm_channel_pool_lock(uvm_channel_pool_t *pool) +{ + if (uvm_channel_pool_is_proxy(pool)) + uvm_mutex_lock(&pool->mutex); + else + uvm_spin_lock(&pool->spinlock); +} + +void uvm_channel_pool_unlock(uvm_channel_pool_t *pool) +{ + if (uvm_channel_pool_is_proxy(pool)) + uvm_mutex_unlock(&pool->mutex); + else + uvm_spin_unlock(&pool->spinlock); +} + +void uvm_channel_pool_assert_locked(uvm_channel_pool_t *pool) +{ + if (uvm_channel_pool_is_proxy(pool)) + uvm_assert_mutex_locked(&pool->mutex); + else + uvm_assert_spinlock_locked(&pool->spinlock); +} + // Update channel progress, completing up to max_to_complete entries static NvU32 uvm_channel_update_progress_with_max(uvm_channel_t *channel, NvU32 max_to_complete, @@ -80,7 +113,7 @@ static NvU32 uvm_channel_update_progress_with_max(uvm_channel_t *channel, NvU64 completed_value = uvm_channel_update_completed_value(channel); - uvm_spin_lock(&channel->pool->lock); + uvm_channel_pool_lock(channel->pool); // Completed value should never exceed the queued value UVM_ASSERT_MSG_RELEASE(completed_value <= channel->tracking_sem.queued_value, @@ -108,7 +141,7 @@ static NvU32 uvm_channel_update_progress_with_max(uvm_channel_t *channel, channel->gpu_get = gpu_get; - uvm_spin_unlock(&channel->pool->lock); + uvm_channel_pool_unlock(channel->pool); if (cpu_put >= gpu_get) pending_gpfifos = cpu_put - gpu_get; @@ -157,7 +190,7 @@ static bool channel_is_available(uvm_channel_t *channel, NvU32 num_gpfifo_entrie { NvU32 pending_entries; - uvm_assert_spinlock_locked(&channel->pool->lock); + uvm_channel_pool_assert_locked(channel->pool); if (channel->cpu_put >= channel->gpu_get) pending_entries = channel->cpu_put - channel->gpu_get; @@ -174,14 +207,14 @@ static bool try_claim_channel(uvm_channel_t *channel, NvU32 num_gpfifo_entries) UVM_ASSERT(num_gpfifo_entries > 0); UVM_ASSERT(num_gpfifo_entries < channel->num_gpfifo_entries); - uvm_spin_lock(&channel->pool->lock); + uvm_channel_pool_lock(channel->pool); if (channel_is_available(channel, num_gpfifo_entries)) { channel->current_gpfifo_count += num_gpfifo_entries; claimed = true; } - uvm_spin_unlock(&channel->pool->lock); + uvm_channel_pool_unlock(channel->pool); return claimed; } @@ -248,7 +281,8 @@ static NV_STATUS channel_reserve_in_pool(uvm_channel_pool_t *pool, uvm_channel_t NV_STATUS uvm_channel_reserve_type(uvm_channel_manager_t *manager, uvm_channel_type_t type, uvm_channel_t **channel_out) { - UVM_ASSERT(type < UVM_CHANNEL_TYPE_COUNT); + UVM_ASSERT(type < UVM_CHANNEL_TYPE_COUNT); + return channel_reserve_in_pool(manager->pool_to_use.default_for_type[type], channel_out); } @@ -289,14 +323,14 @@ static NvU32 channel_get_available_push_info_index(uvm_channel_t *channel) { uvm_push_info_t *push_info; - uvm_spin_lock(&channel->pool->lock); + uvm_channel_pool_lock(channel->pool); push_info = list_first_entry_or_null(&channel->available_push_infos, uvm_push_info_t, available_list_node); UVM_ASSERT(push_info != NULL); UVM_ASSERT(push_info->on_complete == NULL && push_info->on_complete_data == NULL); list_del(&push_info->available_list_node); - uvm_spin_unlock(&channel->pool->lock); + uvm_channel_pool_unlock(channel->pool); return push_info - channel->push_infos; } @@ -355,10 +389,6 @@ static void proxy_channel_submit_work(uvm_push_t *push, NvU32 push_size) UVM_ASSERT(uvm_channel_is_proxy(channel)); - // nvUvmInterfacePagingChannelPushStream should not sleep, because a - // spinlock is currently held. - uvm_assert_spinlock_locked(&channel->pool->lock); - status = nvUvmInterfacePagingChannelPushStream(channel->proxy.handle, (char *) push->begin, push_size); if (status != NV_OK) { @@ -409,7 +439,7 @@ void uvm_channel_end_push(uvm_push_t *push) NvU32 cpu_put; NvU32 new_cpu_put; - uvm_spin_lock(&channel->pool->lock); + uvm_channel_pool_lock(channel->pool); new_tracking_value = ++channel->tracking_sem.queued_value; new_payload = (NvU32)new_tracking_value; @@ -446,7 +476,7 @@ void uvm_channel_end_push(uvm_push_t *push) // may notice the GPU work to be completed and hence all state tracking the // push must be updated before that. Notably uvm_pushbuffer_end_push() has // to be called first. - uvm_spin_unlock(&channel->pool->lock); + uvm_channel_pool_unlock(channel->pool); unlock_push(channel); // This memory barrier is borrowed from CUDA, as it supposedly fixes perf @@ -470,7 +500,7 @@ static void write_ctrl_gpfifo(uvm_channel_t *channel, NvU64 ctrl_fifo_entry_valu NvU32 new_cpu_put; uvm_gpu_t *gpu = channel->pool->manager->gpu; - uvm_spin_lock(&channel->pool->lock); + uvm_channel_pool_lock(channel->pool); cpu_put = channel->cpu_put; new_cpu_put = (cpu_put + 1) % channel->num_gpfifo_entries; @@ -505,7 +535,7 @@ static void write_ctrl_gpfifo(uvm_channel_t *channel, NvU64 ctrl_fifo_entry_valu // The moment the channel is unlocked uvm_channel_update_progress_with_max() // may notice the GPU work to be completed and hence all state tracking the // push must be updated before that. - uvm_spin_unlock(&channel->pool->lock); + uvm_channel_pool_unlock(channel->pool); unlock_push(channel); // This memory barrier is borrowed from CUDA, as it supposedly fixes perf @@ -591,12 +621,12 @@ static uvm_gpfifo_entry_t *uvm_channel_get_first_pending_entry(uvm_channel_t *ch if (pending_count == 0) return NULL; - uvm_spin_lock(&channel->pool->lock); + uvm_channel_pool_lock(channel->pool); if (channel->gpu_get != channel->cpu_put) entry = &channel->gpfifo_entries[channel->gpu_get]; - uvm_spin_unlock(&channel->pool->lock); + uvm_channel_pool_unlock(channel->pool); return entry; } @@ -720,9 +750,9 @@ static void channel_destroy(uvm_channel_pool_t *pool, uvm_channel_t *channel) channel_update_progress_all(channel, UVM_CHANNEL_UPDATE_MODE_FORCE_ALL); } - uvm_procfs_destroy_entry(channel->procfs.pushes); - uvm_procfs_destroy_entry(channel->procfs.info); - uvm_procfs_destroy_entry(channel->procfs.dir); + proc_remove(channel->procfs.pushes); + proc_remove(channel->procfs.info); + proc_remove(channel->procfs.dir); uvm_kvfree(channel->push_acquire_infos); uvm_kvfree(channel->push_infos); @@ -977,7 +1007,7 @@ static NV_STATUS channel_pool_add(uvm_channel_manager_t *channel_manager, pool->engine_index = engine_index; pool->pool_type = pool_type; - uvm_spin_lock_init(&pool->lock, UVM_LOCK_ORDER_CHANNEL); + channel_pool_lock_init(pool); num_channels = channel_pool_type_num_channels(pool_type); @@ -1482,11 +1512,11 @@ void uvm_channel_manager_destroy(uvm_channel_manager_t *channel_manager) if (channel_manager == NULL) return; - uvm_procfs_destroy_entry(channel_manager->procfs.pending_pushes); + proc_remove(channel_manager->procfs.pending_pushes); channel_manager_destroy_pools(channel_manager); - uvm_procfs_destroy_entry(channel_manager->procfs.channels_dir); + proc_remove(channel_manager->procfs.channels_dir); uvm_pushbuffer_destroy(channel_manager->pushbuffer); @@ -1583,7 +1613,7 @@ static void uvm_channel_print_info(uvm_channel_t *channel, struct seq_file *s) uvm_channel_manager_t *manager = channel->pool->manager; UVM_SEQ_OR_DBG_PRINT(s, "Channel %s\n", channel->name); - uvm_spin_lock(&channel->pool->lock); + uvm_channel_pool_lock(channel->pool); UVM_SEQ_OR_DBG_PRINT(s, "completed %llu\n", uvm_channel_update_completed_value(channel)); UVM_SEQ_OR_DBG_PRINT(s, "queued %llu\n", channel->tracking_sem.queued_value); @@ -1595,7 +1625,7 @@ static void uvm_channel_print_info(uvm_channel_t *channel, struct seq_file *s) UVM_SEQ_OR_DBG_PRINT(s, "Semaphore GPU VA 0x%llx\n", uvm_channel_tracking_semaphore_get_gpu_va(channel)); UVM_SEQ_OR_DBG_PRINT(s, "Semaphore CPU VA 0x%llx\n", (NvU64)(uintptr_t)channel->tracking_sem.semaphore.payload); - uvm_spin_unlock(&channel->pool->lock); + uvm_channel_pool_unlock(channel->pool); } static void channel_print_push_acquires(uvm_push_acquire_info_t *push_acquire_info, struct seq_file *seq) @@ -1639,7 +1669,7 @@ static void channel_print_pushes(uvm_channel_t *channel, NvU32 finished_pushes_c NvU64 completed_value = uvm_channel_update_completed_value(channel); - uvm_spin_lock(&channel->pool->lock); + uvm_channel_pool_lock(channel->pool); cpu_put = channel->cpu_put; @@ -1687,7 +1717,7 @@ static void channel_print_pushes(uvm_channel_t *channel, NvU32 finished_pushes_c channel_print_push_acquires(push_acquire_info, seq); } } - uvm_spin_unlock(&channel->pool->lock); + uvm_channel_pool_unlock(channel->pool); } void uvm_channel_print_pending_pushes(uvm_channel_t *channel) diff --git a/kernel-open/nvidia-uvm/uvm_channel.h b/kernel-open/nvidia-uvm/uvm_channel.h index 30bf74d6d..2a0a5926a 100644 --- a/kernel-open/nvidia-uvm/uvm_channel.h +++ b/kernel-open/nvidia-uvm/uvm_channel.h @@ -163,7 +163,11 @@ typedef struct uvm_channel_pool_type_t pool_type; // Lock protecting the state of channels in the pool - uvm_spinlock_t lock; + union { + uvm_spinlock_t spinlock; + uvm_mutex_t mutex; + }; + } uvm_channel_pool_t; struct uvm_channel_struct @@ -309,10 +313,20 @@ struct uvm_channel_manager_struct // Create a channel manager for the GPU NV_STATUS uvm_channel_manager_create(uvm_gpu_t *gpu, uvm_channel_manager_t **manager_out); +void uvm_channel_pool_lock(uvm_channel_pool_t *pool); +void uvm_channel_pool_unlock(uvm_channel_pool_t *pool); +void uvm_channel_pool_assert_locked(uvm_channel_pool_t *pool); + +static bool uvm_channel_pool_is_proxy(uvm_channel_pool_t *pool) +{ + UVM_ASSERT(pool->pool_type < UVM_CHANNEL_POOL_TYPE_MASK); + + return pool->pool_type == UVM_CHANNEL_POOL_TYPE_CE_PROXY; +} + static bool uvm_channel_is_proxy(uvm_channel_t *channel) { - UVM_ASSERT(channel->pool->pool_type < UVM_CHANNEL_POOL_TYPE_MASK); - return channel->pool->pool_type == UVM_CHANNEL_POOL_TYPE_CE_PROXY; + return uvm_channel_pool_is_proxy(channel->pool); } static bool uvm_channel_is_ce(uvm_channel_t *channel) diff --git a/kernel-open/nvidia-uvm/uvm_channel_test.c b/kernel-open/nvidia-uvm/uvm_channel_test.c index c1e481ce9..eaca0acd9 100644 --- a/kernel-open/nvidia-uvm/uvm_channel_test.c +++ b/kernel-open/nvidia-uvm/uvm_channel_test.c @@ -747,14 +747,14 @@ static NvU32 get_available_gpfifo_entries(uvm_channel_t *channel) { NvU32 pending_entries; - uvm_spin_lock(&channel->pool->lock); + uvm_channel_pool_lock(channel->pool); if (channel->cpu_put >= channel->gpu_get) pending_entries = channel->cpu_put - channel->gpu_get; else pending_entries = channel->cpu_put + channel->num_gpfifo_entries - channel->gpu_get; - uvm_spin_unlock(&channel->pool->lock); + uvm_channel_pool_unlock(channel->pool); return channel->num_gpfifo_entries - pending_entries - 1; } diff --git a/kernel-open/nvidia-uvm/uvm_global.h b/kernel-open/nvidia-uvm/uvm_global.h index 8ef734530..8ef84cacf 100644 --- a/kernel-open/nvidia-uvm/uvm_global.h +++ b/kernel-open/nvidia-uvm/uvm_global.h @@ -186,8 +186,7 @@ static void uvm_global_remove_parent_gpu(uvm_parent_gpu_t *parent_gpu) uvm_assert_mutex_locked(&g_uvm_global.global_lock); uvm_assert_spinlock_locked(&g_uvm_global.gpu_table_lock); - UVM_ASSERT(g_uvm_global.parent_gpus[gpu_index]); - UVM_ASSERT(g_uvm_global.parent_gpus[gpu_index] == parent_gpu); + UVM_ASSERT(g_uvm_global.parent_gpus[gpu_index] == NULL || g_uvm_global.parent_gpus[gpu_index] == parent_gpu); g_uvm_global.parent_gpus[gpu_index] = NULL; } diff --git a/kernel-open/nvidia-uvm/uvm_gpu.c b/kernel-open/nvidia-uvm/uvm_gpu.c index 93202b7d4..ecf5d02b8 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu.c +++ b/kernel-open/nvidia-uvm/uvm_gpu.c @@ -694,7 +694,7 @@ static NV_STATUS init_parent_procfs_dir(uvm_parent_gpu_t *parent_gpu) static void deinit_parent_procfs_dir(uvm_parent_gpu_t *parent_gpu) { - uvm_procfs_destroy_entry(parent_gpu->procfs.dir); + proc_remove(parent_gpu->procfs.dir); } static NV_STATUS init_parent_procfs_files(uvm_parent_gpu_t *parent_gpu) @@ -722,8 +722,8 @@ static NV_STATUS init_parent_procfs_files(uvm_parent_gpu_t *parent_gpu) static void deinit_parent_procfs_files(uvm_parent_gpu_t *parent_gpu) { - uvm_procfs_destroy_entry(parent_gpu->procfs.access_counters_file); - uvm_procfs_destroy_entry(parent_gpu->procfs.fault_stats_file); + proc_remove(parent_gpu->procfs.access_counters_file); + proc_remove(parent_gpu->procfs.fault_stats_file); } static NV_STATUS init_procfs_dirs(uvm_gpu_t *gpu) @@ -774,9 +774,9 @@ static NV_STATUS init_procfs_dirs(uvm_gpu_t *gpu) // The kernel waits on readers to finish before returning from those calls static void deinit_procfs_dirs(uvm_gpu_t *gpu) { - uvm_procfs_destroy_entry(gpu->procfs.dir_peers); - uvm_procfs_destroy_entry(gpu->procfs.dir_symlink); - uvm_procfs_destroy_entry(gpu->procfs.dir); + proc_remove(gpu->procfs.dir_peers); + proc_remove(gpu->procfs.dir_symlink); + proc_remove(gpu->procfs.dir); } static NV_STATUS init_procfs_files(uvm_gpu_t *gpu) @@ -790,15 +790,15 @@ static NV_STATUS init_procfs_files(uvm_gpu_t *gpu) static void deinit_procfs_files(uvm_gpu_t *gpu) { - uvm_procfs_destroy_entry(gpu->procfs.info_file); + proc_remove(gpu->procfs.info_file); } static void deinit_procfs_peer_cap_files(uvm_gpu_peer_t *peer_caps) { - uvm_procfs_destroy_entry(peer_caps->procfs.peer_symlink_file[0]); - uvm_procfs_destroy_entry(peer_caps->procfs.peer_symlink_file[1]); - uvm_procfs_destroy_entry(peer_caps->procfs.peer_file[0]); - uvm_procfs_destroy_entry(peer_caps->procfs.peer_file[1]); + proc_remove(peer_caps->procfs.peer_symlink_file[0]); + proc_remove(peer_caps->procfs.peer_symlink_file[1]); + proc_remove(peer_caps->procfs.peer_file[0]); + proc_remove(peer_caps->procfs.peer_file[1]); } static NV_STATUS init_semaphore_pool(uvm_gpu_t *gpu) @@ -3080,41 +3080,41 @@ void uvm_gpu_dma_free_page(uvm_parent_gpu_t *parent_gpu, void *va, NvU64 dma_add atomic64_sub(PAGE_SIZE, &parent_gpu->mapped_cpu_pages_size); } -NV_STATUS uvm_gpu_map_cpu_pages(uvm_gpu_t *gpu, struct page *page, size_t size, NvU64 *dma_address_out) +NV_STATUS uvm_gpu_map_cpu_pages(uvm_parent_gpu_t *parent_gpu, struct page *page, size_t size, NvU64 *dma_address_out) { NvU64 dma_addr; UVM_ASSERT(PAGE_ALIGNED(size)); - dma_addr = dma_map_page(&gpu->parent->pci_dev->dev, page, 0, size, DMA_BIDIRECTIONAL); - if (dma_mapping_error(&gpu->parent->pci_dev->dev, dma_addr)) + dma_addr = dma_map_page(&parent_gpu->pci_dev->dev, page, 0, size, DMA_BIDIRECTIONAL); + if (dma_mapping_error(&parent_gpu->pci_dev->dev, dma_addr)) return NV_ERR_OPERATING_SYSTEM; - if (dma_addr < gpu->parent->dma_addressable_start || - dma_addr + size - 1 > gpu->parent->dma_addressable_limit) { - dma_unmap_page(&gpu->parent->pci_dev->dev, dma_addr, size, DMA_BIDIRECTIONAL); + if (dma_addr < parent_gpu->dma_addressable_start || + dma_addr + size - 1 > parent_gpu->dma_addressable_limit) { + dma_unmap_page(&parent_gpu->pci_dev->dev, dma_addr, size, DMA_BIDIRECTIONAL); UVM_ERR_PRINT_RL("PCI mapped range [0x%llx, 0x%llx) not in the addressable range [0x%llx, 0x%llx), GPU %s\n", dma_addr, dma_addr + (NvU64)size, - gpu->parent->dma_addressable_start, - gpu->parent->dma_addressable_limit + 1, - uvm_gpu_name(gpu)); + parent_gpu->dma_addressable_start, + parent_gpu->dma_addressable_limit + 1, + parent_gpu->name); return NV_ERR_INVALID_ADDRESS; } - atomic64_add(size, &gpu->parent->mapped_cpu_pages_size); - *dma_address_out = dma_addr_to_gpu_addr(gpu->parent, dma_addr); + atomic64_add(size, &parent_gpu->mapped_cpu_pages_size); + *dma_address_out = dma_addr_to_gpu_addr(parent_gpu, dma_addr); return NV_OK; } -void uvm_gpu_unmap_cpu_pages(uvm_gpu_t *gpu, NvU64 dma_address, size_t size) +void uvm_gpu_unmap_cpu_pages(uvm_parent_gpu_t *parent_gpu, NvU64 dma_address, size_t size) { UVM_ASSERT(PAGE_ALIGNED(size)); - dma_address = gpu_addr_to_dma_addr(gpu->parent, dma_address); - dma_unmap_page(&gpu->parent->pci_dev->dev, dma_address, size, DMA_BIDIRECTIONAL); - atomic64_sub(size, &gpu->parent->mapped_cpu_pages_size); + dma_address = gpu_addr_to_dma_addr(parent_gpu, dma_address); + dma_unmap_page(&parent_gpu->pci_dev->dev, dma_address, size, DMA_BIDIRECTIONAL); + atomic64_sub(size, &parent_gpu->mapped_cpu_pages_size); } // This function implements the UvmRegisterGpu API call, as described in uvm.h. diff --git a/kernel-open/nvidia-uvm/uvm_gpu.h b/kernel-open/nvidia-uvm/uvm_gpu.h index 8ec172e0c..2ddcd32eb 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu.h +++ b/kernel-open/nvidia-uvm/uvm_gpu.h @@ -44,6 +44,7 @@ #include "uvm_va_block_types.h" #include "uvm_perf_module.h" #include "uvm_rb_tree.h" +#include "uvm_perf_prefetch.h" #include "nv-kthread-q.h" // Buffer length to store uvm gpu id, RM device name and gpu uuid. @@ -159,6 +160,12 @@ struct uvm_service_block_context_struct // State used by the VA block routines called by the servicing routine uvm_va_block_context_t block_context; + + // Prefetch state hint + uvm_perf_prefetch_hint_t prefetch_hint; + + // Prefetch temporary state. + uvm_perf_prefetch_bitmap_tree_t prefetch_bitmap_tree; }; struct uvm_fault_service_batch_context_struct @@ -374,6 +381,16 @@ struct uvm_access_counter_service_batch_context_struct // determine at fetch time that all the access counter notifications in the // batch report the same instance_ptr bool is_single_instance_ptr; + + // Scratch space, used to generate artificial physically addressed notifications. + // Virtual address notifications are always aligned to 64k. This means up to 16 + // different physical locations could have been accessed to trigger one notification. + // The sub-granularity mask can correspond to any of them. + struct { + uvm_processor_id_t resident_processors[16]; + uvm_gpu_phys_address_t phys_addresses[16]; + uvm_access_counter_buffer_entry_t phys_entry; + } scratch; } virt; struct @@ -1309,19 +1326,19 @@ NV_STATUS uvm_gpu_check_ecc_error_no_rm(uvm_gpu_t *gpu); // // Returns the physical address of the pages that can be used to access them on // the GPU. -NV_STATUS uvm_gpu_map_cpu_pages(uvm_gpu_t *gpu, struct page *page, size_t size, NvU64 *dma_address_out); +NV_STATUS uvm_gpu_map_cpu_pages(uvm_parent_gpu_t *parent_gpu, struct page *page, size_t size, NvU64 *dma_address_out); // Unmap num_pages pages previously mapped with uvm_gpu_map_cpu_pages(). -void uvm_gpu_unmap_cpu_pages(uvm_gpu_t *gpu, NvU64 dma_address, size_t size); +void uvm_gpu_unmap_cpu_pages(uvm_parent_gpu_t *parent_gpu, NvU64 dma_address, size_t size); -static NV_STATUS uvm_gpu_map_cpu_page(uvm_gpu_t *gpu, struct page *page, NvU64 *dma_address_out) +static NV_STATUS uvm_gpu_map_cpu_page(uvm_parent_gpu_t *parent_gpu, struct page *page, NvU64 *dma_address_out) { - return uvm_gpu_map_cpu_pages(gpu, page, PAGE_SIZE, dma_address_out); + return uvm_gpu_map_cpu_pages(parent_gpu, page, PAGE_SIZE, dma_address_out); } -static void uvm_gpu_unmap_cpu_page(uvm_gpu_t *gpu, NvU64 dma_address) +static void uvm_gpu_unmap_cpu_page(uvm_parent_gpu_t *parent_gpu, NvU64 dma_address) { - uvm_gpu_unmap_cpu_pages(gpu, dma_address, PAGE_SIZE); + uvm_gpu_unmap_cpu_pages(parent_gpu, dma_address, PAGE_SIZE); } // Allocate and map a page of system DMA memory on the GPU for physical access diff --git a/kernel-open/nvidia-uvm/uvm_gpu_access_counters.c b/kernel-open/nvidia-uvm/uvm_gpu_access_counters.c index 05d3273be..044c15e0e 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu_access_counters.c +++ b/kernel-open/nvidia-uvm/uvm_gpu_access_counters.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2017-2021 NVIDIA Corporation + Copyright (c) 2017-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -41,6 +41,10 @@ #define UVM_PERF_ACCESS_COUNTER_THRESHOLD_MAX ((1 << 16) - 1) #define UVM_PERF_ACCESS_COUNTER_THRESHOLD_DEFAULT 256 +#define UVM_ACCESS_COUNTER_ACTION_NOTIFY 0x1 +#define UVM_ACCESS_COUNTER_ACTION_CLEAR 0x2 +#define UVM_ACCESS_COUNTER_ON_MANAGED 0x4 + // Each page in a tracked physical range may belong to a different VA Block. We // preallocate an array of reverse map translations. However, access counter // granularity can be set to up to 16G, which would require an array too large @@ -934,25 +938,6 @@ static void preprocess_virt_notifications(uvm_gpu_t *gpu, translate_virt_notifications_instance_ptrs(gpu, batch_context); } -static NV_STATUS service_virt_notifications(uvm_gpu_t *gpu, - uvm_access_counter_service_batch_context_t *batch_context) -{ - // TODO: Bug 1990466: Service virtual notifications. Entries with NULL - // va_space are simply dropped. - if (uvm_enable_builtin_tests) { - NvU32 i; - - preprocess_virt_notifications(gpu, batch_context); - - for (i = 0; i < batch_context->virt.num_notifications; ++i) { - const bool on_managed = false; - uvm_tools_broadcast_access_counter(gpu, batch_context->virt.notifications[i], on_managed); - } - } - - return NV_OK; -} - // GPA notifications provide a physical address and an aperture. Sort // accesses by aperture to try to coalesce operations on the same target // processor. @@ -1046,9 +1031,19 @@ static NV_STATUS service_va_block_locked(uvm_processor_id_t processor, uvm_page_mask_set(&service_context->thrashing_pin_mask, page_index); } + // If the underlying VMA is gone, skip HMM migrations. + if (uvm_va_block_is_hmm(va_block)) { + status = uvm_hmm_find_vma(&service_context->block_context, address); + if (status == NV_ERR_INVALID_ADDRESS) + continue; + + UVM_ASSERT(status == NV_OK); + } + service_context->block_context.policy = uvm_va_policy_get(va_block, address); new_residency = uvm_va_block_select_residency(va_block, + &service_context->block_context, page_index, processor, uvm_fault_access_type_mask_bit(UVM_FAULT_ACCESS_TYPE_PREFETCH), @@ -1158,7 +1153,7 @@ static NV_STATUS service_phys_single_va_block(uvm_gpu_t *gpu, const uvm_access_counter_buffer_entry_t *current_entry, const uvm_reverse_map_t *reverse_mappings, size_t num_reverse_mappings, - bool *clear_counter) + unsigned *out_flags) { size_t index; uvm_va_block_t *va_block = reverse_mappings[0].va_block; @@ -1168,7 +1163,7 @@ static NV_STATUS service_phys_single_va_block(uvm_gpu_t *gpu, const uvm_processor_id_t processor = current_entry->counter_type == UVM_ACCESS_COUNTER_TYPE_MIMC? gpu->id: UVM_ID_CPU; - *clear_counter = false; + *out_flags &= ~UVM_ACCESS_COUNTER_ACTION_CLEAR; UVM_ASSERT(num_reverse_mappings > 0); @@ -1217,7 +1212,7 @@ static NV_STATUS service_phys_single_va_block(uvm_gpu_t *gpu, uvm_mutex_unlock(&va_block->lock); if (status == NV_OK) - *clear_counter = true; + *out_flags |= UVM_ACCESS_COUNTER_ACTION_CLEAR; } done: @@ -1238,25 +1233,26 @@ static NV_STATUS service_phys_va_blocks(uvm_gpu_t *gpu, const uvm_access_counter_buffer_entry_t *current_entry, const uvm_reverse_map_t *reverse_mappings, size_t num_reverse_mappings, - bool *clear_counter) + unsigned *out_flags) { NV_STATUS status = NV_OK; size_t index; - *clear_counter = false; + *out_flags &= ~UVM_ACCESS_COUNTER_ACTION_CLEAR; for (index = 0; index < num_reverse_mappings; ++index) { - bool clear_counter_local = false; + unsigned out_flags_local = 0; status = service_phys_single_va_block(gpu, batch_context, current_entry, reverse_mappings + index, 1, - &clear_counter_local); + &out_flags_local); if (status != NV_OK) break; - *clear_counter = *clear_counter || clear_counter_local; + UVM_ASSERT((out_flags_local & ~UVM_ACCESS_COUNTER_ACTION_CLEAR) == 0); + *out_flags |= out_flags_local; } // In the case of failure, drop the refcounts for the remaining reverse mappings @@ -1267,18 +1263,13 @@ static NV_STATUS service_phys_va_blocks(uvm_gpu_t *gpu, } // Iterate over all regions set in the given sub_granularity mask -#define for_each_sub_granularity_region(region_start, region_end, sub_granularity, config) \ - for ((region_start) = find_first_bit(&(sub_granularity), (config)->sub_granularity_regions_per_translation), \ - (region_end) = find_next_zero_bit(&(sub_granularity), \ - (config)->sub_granularity_regions_per_translation, \ - (region_start) + 1); \ - (region_start) < config->sub_granularity_regions_per_translation; \ - (region_start) = find_next_bit(&(sub_granularity), \ - (config)->sub_granularity_regions_per_translation, \ - (region_end) + 1), \ - (region_end) = find_next_zero_bit(&(sub_granularity), \ - (config)->sub_granularity_regions_per_translation, \ - (region_start) + 1)) +#define for_each_sub_granularity_region(region_start, region_end, sub_granularity, num_regions) \ + for ((region_start) = find_first_bit(&(sub_granularity), (num_regions)), \ + (region_end) = find_next_zero_bit(&(sub_granularity), (num_regions), (region_start) + 1); \ + (region_start) < (num_regions); \ + (region_start) = find_next_bit(&(sub_granularity), (num_regions), (region_end) + 1), \ + (region_end) = find_next_zero_bit(&(sub_granularity), (num_regions), (region_start) + 1)) + static bool are_reverse_mappings_on_single_block(const uvm_reverse_map_t *reverse_mappings, size_t num_reverse_mappings) { @@ -1309,7 +1300,7 @@ static NV_STATUS service_phys_notification_translation(uvm_gpu_t *gpu, NvU64 address, unsigned long sub_granularity, size_t *num_reverse_mappings, - bool *clear_counter) + unsigned *out_flags) { NV_STATUS status; NvU32 region_start, region_end; @@ -1318,7 +1309,7 @@ static NV_STATUS service_phys_notification_translation(uvm_gpu_t *gpu, // Get the reverse_map translations for all the regions set in the // sub_granularity field of the counter. - for_each_sub_granularity_region(region_start, region_end, sub_granularity, config) { + for_each_sub_granularity_region(region_start, region_end, sub_granularity, config->sub_granularity_regions_per_translation) { NvU64 local_address = address + region_start * config->sub_granularity_region_size; NvU32 local_translation_size = (region_end - region_start) * config->sub_granularity_region_size; uvm_reverse_map_t *local_reverse_mappings = batch_context->phys.translations + *num_reverse_mappings; @@ -1350,7 +1341,7 @@ static NV_STATUS service_phys_notification_translation(uvm_gpu_t *gpu, current_entry, batch_context->phys.translations, *num_reverse_mappings, - clear_counter); + out_flags); } else { status = service_phys_va_blocks(gpu, @@ -1358,7 +1349,7 @@ static NV_STATUS service_phys_notification_translation(uvm_gpu_t *gpu, current_entry, batch_context->phys.translations, *num_reverse_mappings, - clear_counter); + out_flags); } return status; @@ -1366,7 +1357,8 @@ static NV_STATUS service_phys_notification_translation(uvm_gpu_t *gpu, static NV_STATUS service_phys_notification(uvm_gpu_t *gpu, uvm_access_counter_service_batch_context_t *batch_context, - const uvm_access_counter_buffer_entry_t *current_entry) + const uvm_access_counter_buffer_entry_t *current_entry, + unsigned *out_flags) { NvU64 address; NvU64 translation_index; @@ -1377,7 +1369,7 @@ static NV_STATUS service_phys_notification(uvm_gpu_t *gpu, size_t total_reverse_mappings = 0; uvm_gpu_t *resident_gpu = NULL; NV_STATUS status = NV_OK; - bool clear_counter = false; + unsigned flags = 0; address = current_entry->address.address; UVM_ASSERT(address % config->translation_size == 0); @@ -1405,7 +1397,7 @@ static NV_STATUS service_phys_notification(uvm_gpu_t *gpu, for (translation_index = 0; translation_index < config->translations_per_counter; ++translation_index) { size_t num_reverse_mappings; - bool clear_counter_local = false; + unsigned out_flags_local = 0; status = service_phys_notification_translation(gpu, resident_gpu, batch_context, @@ -1414,9 +1406,11 @@ static NV_STATUS service_phys_notification(uvm_gpu_t *gpu, address, sub_granularity, &num_reverse_mappings, - &clear_counter_local); + &out_flags_local); total_reverse_mappings += num_reverse_mappings; - clear_counter = clear_counter || clear_counter_local; + + UVM_ASSERT((out_flags_local & ~UVM_ACCESS_COUNTER_ACTION_CLEAR) == 0); + flags |= out_flags_local; if (status != NV_OK) break; @@ -1425,17 +1419,14 @@ static NV_STATUS service_phys_notification(uvm_gpu_t *gpu, sub_granularity = sub_granularity >> config->sub_granularity_regions_per_translation; } - // TODO: Bug 1990466: Here we already have virtual addresses and - // address spaces. Merge virtual and physical notification handling - // Currently we only report events for our tests, not for tools if (uvm_enable_builtin_tests) { - const bool on_managed = total_reverse_mappings != 0; - uvm_tools_broadcast_access_counter(gpu, current_entry, on_managed); + *out_flags |= UVM_ACCESS_COUNTER_ACTION_NOTIFY; + *out_flags |= ((total_reverse_mappings != 0) ? UVM_ACCESS_COUNTER_ON_MANAGED : 0); } - if (status == NV_OK && clear_counter) - status = access_counter_clear_targeted(gpu, current_entry); + if (status == NV_OK && (flags & UVM_ACCESS_COUNTER_ACTION_CLEAR)) + *out_flags |= UVM_ACCESS_COUNTER_ACTION_CLEAR; return status; } @@ -1450,11 +1441,18 @@ static NV_STATUS service_phys_notifications(uvm_gpu_t *gpu, for (i = 0; i < batch_context->phys.num_notifications; ++i) { NV_STATUS status; uvm_access_counter_buffer_entry_t *current_entry = batch_context->phys.notifications[i]; + unsigned flags = 0; if (!UVM_ID_IS_VALID(current_entry->physical_info.resident_id)) continue; - status = service_phys_notification(gpu, batch_context, current_entry); + status = service_phys_notification(gpu, batch_context, current_entry, &flags); + if (flags & UVM_ACCESS_COUNTER_ACTION_NOTIFY) + uvm_tools_broadcast_access_counter(gpu, current_entry, flags & UVM_ACCESS_COUNTER_ON_MANAGED); + + if (status == NV_OK && (flags & UVM_ACCESS_COUNTER_ACTION_CLEAR)) + status = access_counter_clear_targeted(gpu, current_entry); + if (status != NV_OK) return status; } @@ -1462,6 +1460,191 @@ static NV_STATUS service_phys_notifications(uvm_gpu_t *gpu, return NV_OK; } +static int cmp_sort_gpu_phys_addr(const void *_a, const void *_b) +{ + return uvm_gpu_phys_addr_cmp(*(uvm_gpu_phys_address_t*)_a, + *(uvm_gpu_phys_address_t*)_b); +} + +static bool gpu_phys_same_region(uvm_gpu_phys_address_t a, uvm_gpu_phys_address_t b, NvU64 granularity) +{ + if (a.aperture != b.aperture) + return false; + + UVM_ASSERT(is_power_of_2(granularity)); + + return UVM_ALIGN_DOWN(a.address, granularity) == UVM_ALIGN_DOWN(b.address, granularity); +} + +static bool phys_address_in_accessed_sub_region(uvm_gpu_phys_address_t address, + NvU64 region_size, + NvU64 sub_region_size, + NvU32 accessed_mask) +{ + const unsigned accessed_index = (address.address % region_size) / sub_region_size; + + // accessed_mask is only filled for tracking granularities larger than 64K + if (region_size == UVM_PAGE_SIZE_64K) + return true; + + UVM_ASSERT(accessed_index < 32); + return ((1 << accessed_index) & accessed_mask) != 0; +} + +static NV_STATUS service_virt_notification(uvm_gpu_t *gpu, + uvm_access_counter_service_batch_context_t *batch_context, + const uvm_access_counter_buffer_entry_t *current_entry, + unsigned *out_flags) +{ + NV_STATUS status = NV_OK; + NvU64 notification_size; + NvU64 address; + uvm_processor_id_t *resident_processors = batch_context->virt.scratch.resident_processors; + uvm_gpu_phys_address_t *phys_addresses = batch_context->virt.scratch.phys_addresses; + int num_addresses = 0; + int i; + + // Virtual address notifications are always 64K aligned + NvU64 region_start = current_entry->address.address; + NvU64 region_end = current_entry->address.address + UVM_PAGE_SIZE_64K; + + + uvm_access_counter_buffer_info_t *access_counters = &gpu->parent->access_counter_buffer_info; + uvm_access_counter_type_t counter_type = current_entry->counter_type; + + const uvm_gpu_access_counter_type_config_t *config = get_config_for_type(access_counters, counter_type); + + uvm_va_space_t *va_space = current_entry->virtual_info.va_space; + + UVM_ASSERT(counter_type == UVM_ACCESS_COUNTER_TYPE_MIMC); + + // Entries with NULL va_space are simply dropped. + if (!va_space) + return NV_OK; + + status = config_granularity_to_bytes(config->rm.granularity, ¬ification_size); + if (status != NV_OK) + return status; + + // Collect physical locations that could have been touched + // in the reported 64K VA region. The notification mask can + // correspond to any of them. + uvm_va_space_down_read(va_space); + for (address = region_start; address < region_end;) { + uvm_va_block_t *va_block; + + NV_STATUS local_status = uvm_va_block_find(va_space, address, &va_block); + if (local_status == NV_ERR_INVALID_ADDRESS || local_status == NV_ERR_OBJECT_NOT_FOUND) { + address += PAGE_SIZE; + continue; + } + + uvm_mutex_lock(&va_block->lock); + while (address < va_block->end && address < region_end) { + const unsigned page_index = uvm_va_block_cpu_page_index(va_block, address); + + // UVM va_block always maps the closest resident location to processor + const uvm_processor_id_t res_id = uvm_va_block_page_get_closest_resident(va_block, page_index, gpu->id); + + // Add physical location if it's valid and not local vidmem + if (UVM_ID_IS_VALID(res_id) && !uvm_id_equal(res_id, gpu->id)) { + uvm_gpu_phys_address_t phys_address = uvm_va_block_res_phys_page_address(va_block, page_index, res_id, gpu); + if (phys_address_in_accessed_sub_region(phys_address, + notification_size, + config->sub_granularity_region_size, + current_entry->sub_granularity)) { + resident_processors[num_addresses] = res_id; + phys_addresses[num_addresses] = phys_address; + ++num_addresses; + } + else { + UVM_DBG_PRINT_RL("Skipping phys address %llx:%s, because it couldn't have been accessed in mask %x", + phys_address.address, + uvm_aperture_string(phys_address.aperture), + current_entry->sub_granularity); + } + } + + address += PAGE_SIZE; + } + uvm_mutex_unlock(&va_block->lock); + } + uvm_va_space_up_read(va_space); + + // The addresses need to be sorted to aid coalescing. + sort(phys_addresses, + num_addresses, + sizeof(*phys_addresses), + cmp_sort_gpu_phys_addr, + NULL); + + for (i = 0; i < num_addresses; ++i) { + uvm_access_counter_buffer_entry_t *fake_entry = &batch_context->virt.scratch.phys_entry; + + // Skip the current pointer if the physical region was already handled + if (i > 0 && gpu_phys_same_region(phys_addresses[i - 1], phys_addresses[i], notification_size)) { + UVM_ASSERT(uvm_id_equal(resident_processors[i - 1], resident_processors[i])); + continue; + } + UVM_DBG_PRINT_RL("Faking MIMC address[%i/%i]: %llx (granularity mask: %llx) in aperture %s on device %s\n", + i, + num_addresses, + phys_addresses[i].address, + notification_size - 1, + uvm_aperture_string(phys_addresses[i].aperture), + uvm_gpu_name(gpu)); + + // Construct a fake phys addr AC entry + fake_entry->counter_type = current_entry->counter_type; + fake_entry->address.address = UVM_ALIGN_DOWN(phys_addresses[i].address, notification_size); + fake_entry->address.aperture = phys_addresses[i].aperture; + fake_entry->address.is_virtual = false; + fake_entry->physical_info.resident_id = resident_processors[i]; + fake_entry->counter_value = current_entry->counter_value; + fake_entry->sub_granularity = current_entry->sub_granularity; + + status = service_phys_notification(gpu, batch_context, fake_entry, out_flags); + if (status != NV_OK) + break; + } + + return status; +} + +static NV_STATUS service_virt_notifications(uvm_gpu_t *gpu, + uvm_access_counter_service_batch_context_t *batch_context) +{ + NvU32 i; + NV_STATUS status = NV_OK; + preprocess_virt_notifications(gpu, batch_context); + + for (i = 0; i < batch_context->virt.num_notifications; ++i) { + unsigned flags = 0; + uvm_access_counter_buffer_entry_t *current_entry = batch_context->virt.notifications[i]; + + status = service_virt_notification(gpu, batch_context, current_entry, &flags); + + UVM_DBG_PRINT_RL("Processed virt access counter (%d/%d): %sMANAGED (status: %d) clear: %s\n", + i + 1, + batch_context->virt.num_notifications, + (flags & UVM_ACCESS_COUNTER_ON_MANAGED) ? "" : "NOT ", + status, + (flags & UVM_ACCESS_COUNTER_ACTION_CLEAR) ? "YES" : "NO"); + + if (uvm_enable_builtin_tests) + uvm_tools_broadcast_access_counter(gpu, current_entry, flags & UVM_ACCESS_COUNTER_ON_MANAGED); + + if (status == NV_OK && (flags & UVM_ACCESS_COUNTER_ACTION_CLEAR)) + status = access_counter_clear_targeted(gpu, current_entry); + + if (status != NV_OK) + break; + } + + return status; +} + + void uvm_gpu_service_access_counters(uvm_gpu_t *gpu) { NV_STATUS status = NV_OK; diff --git a/kernel-open/nvidia-uvm/uvm_gpu_non_replayable_faults.c b/kernel-open/nvidia-uvm/uvm_gpu_non_replayable_faults.c index 3be8a73b2..6faf3555b 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu_non_replayable_faults.c +++ b/kernel-open/nvidia-uvm/uvm_gpu_non_replayable_faults.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2017-2021 NVIDIA Corporation + Copyright (c) 2017-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -338,7 +338,6 @@ static NV_STATUS service_managed_fault_in_block_locked(uvm_gpu_t *gpu, uvm_processor_id_t new_residency; bool read_duplicate; uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); - uvm_va_range_t *va_range = va_block->va_range; uvm_non_replayable_fault_buffer_info_t *non_replayable_faults = &gpu->parent->fault_buffer_info.non_replayable; UVM_ASSERT(!fault_entry->is_fatal); @@ -365,8 +364,11 @@ static NV_STATUS service_managed_fault_in_block_locked(uvm_gpu_t *gpu, } // Check logical permissions - status = uvm_va_range_check_logical_permissions(va_range, + status = uvm_va_block_check_logical_permissions(va_block, + &service_context->block_context, gpu->id, + uvm_va_block_cpu_page_index(va_block, + fault_entry->fault_address), fault_entry->fault_access_type, uvm_range_group_address_migratable(va_space, fault_entry->fault_address)); @@ -386,6 +388,7 @@ static NV_STATUS service_managed_fault_in_block_locked(uvm_gpu_t *gpu, // Compute new residency and update the masks new_residency = uvm_va_block_select_residency(va_block, + &service_context->block_context, page_index, gpu->id, fault_entry->access_type_mask, @@ -422,7 +425,6 @@ static NV_STATUS service_managed_fault_in_block_locked(uvm_gpu_t *gpu, } static NV_STATUS service_managed_fault_in_block(uvm_gpu_t *gpu, - struct mm_struct *mm, uvm_va_block_t *va_block, uvm_fault_buffer_entry_t *fault_entry) { @@ -432,7 +434,6 @@ static NV_STATUS service_managed_fault_in_block(uvm_gpu_t *gpu, service_context->operation = UVM_SERVICE_OPERATION_NON_REPLAYABLE_FAULTS; service_context->num_retries = 0; - service_context->block_context.mm = mm; uvm_mutex_lock(&va_block->lock); @@ -598,6 +599,7 @@ static NV_STATUS service_fault(uvm_gpu_t *gpu, uvm_fault_buffer_entry_t *fault_e // to remain valid until we release. If no mm is registered, we // can only service managed faults, not ATS/HMM faults. mm = uvm_va_space_mm_retain_lock(va_space); + va_block_context->mm = mm; uvm_va_space_down_read(va_space); @@ -622,12 +624,11 @@ static NV_STATUS service_fault(uvm_gpu_t *gpu, uvm_fault_buffer_entry_t *fault_e if (!fault_entry->is_fatal) { status = uvm_va_block_find_create(fault_entry->va_space, - mm, fault_entry->fault_address, va_block_context, &va_block); if (status == NV_OK) - status = service_managed_fault_in_block(gpu_va_space->gpu, mm, va_block, fault_entry); + status = service_managed_fault_in_block(gpu_va_space->gpu, va_block, fault_entry); else status = service_non_managed_fault(gpu_va_space, mm, fault_entry, status); diff --git a/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.c b/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.c index a9b4c7ae2..aaca5fc1b 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.c +++ b/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2021 NVIDIA Corporation + Copyright (c) 2015-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -1055,13 +1055,17 @@ static NV_STATUS preprocess_fault_batch(uvm_gpu_t *gpu, uvm_fault_service_batch_ // - service_access_type: highest access type that can be serviced. static uvm_fault_access_type_t check_fault_access_permissions(uvm_gpu_t *gpu, uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, uvm_fault_buffer_entry_t *fault_entry, bool allow_migration) { NV_STATUS perm_status; - perm_status = uvm_va_range_check_logical_permissions(va_block->va_range, + perm_status = uvm_va_block_check_logical_permissions(va_block, + va_block_context, gpu->id, + uvm_va_block_cpu_page_index(va_block, + fault_entry->fault_address), fault_entry->fault_access_type, allow_migration); if (perm_status == NV_OK) @@ -1083,8 +1087,11 @@ static uvm_fault_access_type_t check_fault_access_permissions(uvm_gpu_t *gpu, // service them before we can cancel the write/atomic faults. So we // retry with read fault access type. if (uvm_fault_access_type_mask_test(fault_entry->access_type_mask, UVM_FAULT_ACCESS_TYPE_READ)) { - perm_status = uvm_va_range_check_logical_permissions(va_block->va_range, + perm_status = uvm_va_block_check_logical_permissions(va_block, + va_block_context, gpu->id, + uvm_va_block_cpu_page_index(va_block, + fault_entry->fault_address), UVM_FAULT_ACCESS_TYPE_READ, allow_migration); if (perm_status == NV_OK) @@ -1156,14 +1163,16 @@ static NV_STATUS service_batch_managed_faults_in_block_locked(uvm_gpu_t *gpu, UVM_ASSERT(ordered_fault_cache[first_fault_index]->fault_address >= va_block->start); UVM_ASSERT(ordered_fault_cache[first_fault_index]->fault_address <= va_block->end); - end = va_block->end; - if (uvm_va_block_is_hmm(va_block)) + if (uvm_va_block_is_hmm(va_block)) { uvm_hmm_find_policy_end(va_block, &block_context->block_context, ordered_fault_cache[first_fault_index]->fault_address, &end); - else + } + else { block_context->block_context.policy = uvm_va_range_get_policy(va_block->va_range); + end = va_block->end; + } // Scan the sorted array and notify the fault event for all fault entries // in the block @@ -1226,7 +1235,11 @@ static NV_STATUS service_batch_managed_faults_in_block_locked(uvm_gpu_t *gpu, UVM_ASSERT(iter.start <= current_entry->fault_address && iter.end >= current_entry->fault_address); - service_access_type = check_fault_access_permissions(gpu, va_block, current_entry, iter.migratable); + service_access_type = check_fault_access_permissions(gpu, + va_block, + &block_context->block_context, + current_entry, + iter.migratable); // Do not exit early due to logical errors such as access permission // violation. @@ -1269,6 +1282,7 @@ static NV_STATUS service_batch_managed_faults_in_block_locked(uvm_gpu_t *gpu, // Compute new residency and update the masks new_residency = uvm_va_block_select_residency(va_block, + &block_context->block_context, page_index, gpu->id, service_access_type_mask, @@ -1348,7 +1362,6 @@ static NV_STATUS service_batch_managed_faults_in_block_locked(uvm_gpu_t *gpu, // See the comments for function service_fault_batch_block_locked for // implementation details and error codes. static NV_STATUS service_batch_managed_faults_in_block(uvm_gpu_t *gpu, - struct mm_struct *mm, uvm_va_block_t *va_block, NvU32 first_fault_index, uvm_fault_service_batch_context_t *batch_context, @@ -1361,7 +1374,6 @@ static NV_STATUS service_batch_managed_faults_in_block(uvm_gpu_t *gpu, fault_block_context->operation = UVM_SERVICE_OPERATION_REPLAYABLE_FAULTS; fault_block_context->num_retries = 0; - fault_block_context->block_context.mm = mm; uvm_mutex_lock(&va_block->lock); @@ -1531,6 +1543,7 @@ static NV_STATUS service_fault_batch(uvm_gpu_t *gpu, // to remain valid until we release. If no mm is registered, we // can only service managed faults, not ATS/HMM faults. mm = uvm_va_space_mm_retain_lock(va_space); + va_block_context->mm = mm; uvm_va_space_down_read(va_space); @@ -1576,13 +1589,11 @@ static NV_STATUS service_fault_batch(uvm_gpu_t *gpu, // TODO: Bug 2103669: Service more than one ATS fault at a time so we // don't do an unconditional VA range lookup for every ATS fault. status = uvm_va_block_find_create(va_space, - mm, current_entry->fault_address, va_block_context, &va_block); if (status == NV_OK) { status = service_batch_managed_faults_in_block(gpu_va_space->gpu, - mm, va_block, i, batch_context, diff --git a/kernel-open/nvidia-uvm/uvm_gpu_semaphore.c b/kernel-open/nvidia-uvm/uvm_gpu_semaphore.c index 5c4683b48..616d67241 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu_semaphore.c +++ b/kernel-open/nvidia-uvm/uvm_gpu_semaphore.c @@ -118,6 +118,13 @@ static bool is_canary(NvU32 val) return (val & ~UVM_SEMAPHORE_CANARY_MASK) == UVM_SEMAPHORE_CANARY_BASE; } +// Can the GPU access the semaphore, i.e., can Host/Esched address the semaphore +// pool? +static bool gpu_can_access_semaphore_pool(uvm_gpu_t *gpu, uvm_rm_mem_t *rm_mem) +{ + return ((uvm_rm_mem_get_gpu_uvm_va(rm_mem, gpu) + rm_mem->size - 1) < gpu->parent->max_host_va); +} + static NV_STATUS pool_alloc_page(uvm_gpu_semaphore_pool_t *pool) { NV_STATUS status; @@ -142,6 +149,9 @@ static NV_STATUS pool_alloc_page(uvm_gpu_semaphore_pool_t *pool) if (status != NV_OK) goto error; + // Verify the GPU can access the semaphore pool. + UVM_ASSERT(gpu_can_access_semaphore_pool(pool->gpu, pool_page->memory)); + // All semaphores are initially free bitmap_fill(pool_page->free_semaphores, UVM_SEMAPHORE_COUNT_PER_PAGE); diff --git a/kernel-open/nvidia-uvm/uvm_hmm.c b/kernel-open/nvidia-uvm/uvm_hmm.c index 00e8633a0..518424755 100644 --- a/kernel-open/nvidia-uvm/uvm_hmm.c +++ b/kernel-open/nvidia-uvm/uvm_hmm.c @@ -46,6 +46,7 @@ MODULE_PARM_DESC(uvm_disable_hmm, #include "uvm_lock.h" #include "uvm_api.h" #include "uvm_va_policy.h" +#include "uvm_tools.h" bool uvm_hmm_is_enabled_system_wide(void) { @@ -96,6 +97,9 @@ NV_STATUS uvm_hmm_va_space_initialize_test(uvm_va_space_t *va_space) if (!uvm_hmm_is_enabled_system_wide() || !mm) return NV_WARN_NOTHING_TO_DO; + if (va_space->initialization_flags & UVM_INIT_FLAGS_DISABLE_HMM) + return NV_ERR_INVALID_STATE; + uvm_assert_mmap_lock_locked_write(mm); uvm_assert_rwsem_locked_write(&va_space->lock); @@ -179,12 +183,19 @@ static bool hmm_invalidate(uvm_va_block_t *va_block, mmu_interval_set_seq(mni, cur_seq); // Note: unmap_vmas() does MMU_NOTIFY_UNMAP [0, 0xffffffffffffffff] + // Also note that hmm_invalidate() can be called when a new va_block is not + // yet inserted into the va_space->hmm.blocks table while the original + // va_block is being split. The original va_block may have its end address + // updated before the mmu interval notifier is updated so this invalidate + // may be for a range past the va_block end address. start = range->start; end = (range->end == ULONG_MAX) ? range->end : range->end - 1; if (start < va_block->start) start = va_block->start; if (end > va_block->end) end = va_block->end; + if (start > end) + goto unlock; if (range->event == MMU_NOTIFY_UNMAP) uvm_va_policy_clear(va_block, start, end); @@ -266,6 +277,7 @@ static NV_STATUS hmm_va_block_find_create(uvm_va_space_t *va_space, UVM_ASSERT(uvm_va_space_initialized(va_space) == NV_OK); UVM_ASSERT(mm); + UVM_ASSERT(!va_block_context || va_block_context->mm == mm); uvm_assert_mmap_lock_locked(mm); uvm_assert_rwsem_locked(&va_space->lock); UVM_ASSERT(PAGE_ALIGNED(addr)); @@ -294,11 +306,13 @@ static NV_STATUS hmm_va_block_find_create(uvm_va_space_t *va_space, // a maximum interval that doesn't overlap any existing UVM va_ranges. // We know that 'addr' is not within a va_range or // hmm_va_block_find_create() wouldn't be called. - uvm_range_tree_adjust_interval(&va_space->va_range_tree, addr, &start, &end); + status = uvm_range_tree_find_hole_in(&va_space->va_range_tree, addr, &start, &end); + UVM_ASSERT(status == NV_OK); // Search for existing HMM va_blocks in the start/end interval and create // a maximum interval that doesn't overlap any existing HMM va_blocks. - uvm_range_tree_adjust_interval(&va_space->hmm.blocks, addr, &start, &end); + status = uvm_range_tree_find_hole_in(&va_space->hmm.blocks, addr, &start, &end); + UVM_ASSERT(status == NV_OK); // Create a HMM va_block with a NULL va_range pointer. status = uvm_va_block_create(NULL, start, end, &va_block); @@ -321,10 +335,7 @@ static NV_STATUS hmm_va_block_find_create(uvm_va_space_t *va_space, } status = uvm_range_tree_add(&va_space->hmm.blocks, &va_block->hmm.node); - if (status != NV_OK) { - UVM_ASSERT(status != NV_ERR_UVM_ADDRESS_IN_USE); - goto err_unreg; - } + UVM_ASSERT(status == NV_OK); done: uvm_mutex_unlock(&va_space->hmm.blocks_lock); @@ -333,9 +344,6 @@ done: *va_block_ptr = va_block; return NV_OK; -err_unreg: - mmu_interval_notifier_remove(&va_block->hmm.notifier); - err_release: uvm_va_block_release(va_block); @@ -352,10 +360,67 @@ NV_STATUS uvm_hmm_va_block_find_create(uvm_va_space_t *va_space, return hmm_va_block_find_create(va_space, addr, false, va_block_context, va_block_ptr); } +NV_STATUS uvm_hmm_find_vma(uvm_va_block_context_t *va_block_context, NvU64 addr) +{ + struct mm_struct *mm = va_block_context->mm; + struct vm_area_struct *vma; + + if (!mm) + return NV_ERR_INVALID_ADDRESS; + + uvm_assert_mmap_lock_locked(mm); + + vma = find_vma(mm, addr); + if (!uvm_hmm_vma_is_valid(vma, addr, false)) + return NV_ERR_INVALID_ADDRESS; + + va_block_context->hmm.vma = vma; + + return NV_OK; +} + +bool uvm_hmm_va_block_context_vma_is_valid(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_va_block_region_t region) +{ + uvm_assert_mutex_locked(&va_block->lock); + + if (uvm_va_block_is_hmm(va_block)) { + struct vm_area_struct *vma = va_block_context->hmm.vma; + + UVM_ASSERT(vma); + UVM_ASSERT(va_block_context->mm == vma->vm_mm); + uvm_assert_mmap_lock_locked(va_block_context->mm); + UVM_ASSERT(vma->vm_start <= uvm_va_block_region_start(va_block, region)); + UVM_ASSERT(vma->vm_end > uvm_va_block_region_end(va_block, region)); + } + + return true; +} + +NV_STATUS uvm_hmm_test_va_block_inject_split_error(uvm_va_space_t *va_space, NvU64 addr) +{ + uvm_va_block_test_t *block_test; + uvm_va_block_t *va_block; + NV_STATUS status; + + if (!uvm_hmm_is_enabled(va_space)) + return NV_ERR_INVALID_ADDRESS; + + status = hmm_va_block_find_create(va_space, addr, false, NULL, &va_block); + if (status != NV_OK) + return status; + + block_test = uvm_va_block_get_test(va_block); + if (block_test) + block_test->inject_split_error = true; + + return NV_OK; +} + typedef struct { struct mmu_interval_notifier notifier; uvm_va_block_t *existing_block; - uvm_va_block_t *new_block; } hmm_split_invalidate_data_t; static bool hmm_split_invalidate(struct mmu_interval_notifier *mni, @@ -363,14 +428,9 @@ static bool hmm_split_invalidate(struct mmu_interval_notifier *mni, unsigned long cur_seq) { hmm_split_invalidate_data_t *split_data = container_of(mni, hmm_split_invalidate_data_t, notifier); - uvm_va_block_t *existing_block = split_data->existing_block; - uvm_va_block_t *new_block = split_data->new_block; - if (uvm_ranges_overlap(existing_block->start, existing_block->end, range->start, range->end - 1)) - hmm_invalidate(existing_block, range, cur_seq); - - if (uvm_ranges_overlap(new_block->start, new_block->end, range->start, range->end - 1)) - hmm_invalidate(new_block, range, cur_seq); + uvm_tools_test_hmm_split_invalidate(split_data->existing_block->hmm.va_space); + hmm_invalidate(split_data->existing_block, range, cur_seq); return true; } @@ -404,6 +464,7 @@ static NV_STATUS hmm_split_block(uvm_va_block_t *va_block, uvm_va_space_t *va_space = va_block->hmm.va_space; struct mm_struct *mm = va_space->va_space_mm.mm; hmm_split_invalidate_data_t split_data; + NvU64 delay_us; uvm_va_block_t *new_va_block; NV_STATUS status; int ret; @@ -419,22 +480,23 @@ static NV_STATUS hmm_split_block(uvm_va_block_t *va_block, return status; // Initialize the newly created HMM va_block. + new_va_block->hmm.node.start = new_va_block->start; + new_va_block->hmm.node.end = new_va_block->end; new_va_block->hmm.va_space = va_space; uvm_range_tree_init(&new_va_block->hmm.va_policy_tree); - // The MMU interval notifier has to be removed in order to resize it. - // That means there would be a window of time where invalidation callbacks - // could be missed. To handle this case, we register a temporary notifier - // to cover the same address range while resizing the old notifier (it is - // OK to have multiple notifiers for the same range, we may simply try to - // invalidate twice). - split_data.existing_block = va_block; - split_data.new_block = new_va_block; - ret = mmu_interval_notifier_insert(&split_data.notifier, + ret = mmu_interval_notifier_insert(&new_va_block->hmm.notifier, mm, - va_block->start, - new_va_block->end - va_block->start + 1, - &hmm_notifier_split_ops); + new_va_block->start, + uvm_va_block_size(new_va_block), + &uvm_hmm_notifier_ops); + + // Since __mmu_notifier_register() was called when the va_space was + // initially created, we know that mm->notifier_subscriptions is valid + // and mmu_interval_notifier_insert() can't return ENOMEM. + // The only error return is for start + length overflowing but we already + // registered the same address range before so there should be no error. + UVM_ASSERT(!ret); uvm_mutex_lock(&va_block->lock); @@ -444,40 +506,38 @@ static NV_STATUS hmm_split_block(uvm_va_block_t *va_block, uvm_mutex_unlock(&va_block->lock); - // Since __mmu_notifier_register() was called when the va_space was - // initially created, we know that mm->notifier_subscriptions is valid - // and mmu_interval_notifier_insert() can't return ENOMEM. - // The only error return is for start + length overflowing but we already - // registered the same address range before so there should be no error. + // The MMU interval notifier has to be removed in order to resize it. + // That means there would be a window of time when invalidation callbacks + // could be missed. To handle this case, we register a temporary notifier + // to cover the address range while resizing the old notifier (it is + // OK to have multiple notifiers for the same range, we may simply try to + // invalidate twice). + split_data.existing_block = va_block; + ret = mmu_interval_notifier_insert(&split_data.notifier, + mm, + va_block->start, + new_end - va_block->start + 1, + &hmm_notifier_split_ops); UVM_ASSERT(!ret); - mmu_interval_notifier_remove(&va_block->hmm.notifier); + // Delay to allow hmm_sanity test to trigger an mmu_notifier during the + // critical window where the split invalidate callback is active. + delay_us = atomic64_read(&va_space->test.split_invalidate_delay_us); + if (delay_us) + udelay(delay_us); - uvm_range_tree_shrink_node(&va_space->hmm.blocks, &va_block->hmm.node, va_block->start, va_block->end); + mmu_interval_notifier_remove(&va_block->hmm.notifier); // Enable notifications on the old block with the smaller size. ret = mmu_interval_notifier_insert(&va_block->hmm.notifier, mm, va_block->start, - va_block->end - va_block->start + 1, - &uvm_hmm_notifier_ops); - UVM_ASSERT(!ret); - - new_va_block->hmm.node.start = new_va_block->start; - new_va_block->hmm.node.end = new_va_block->end; - - ret = mmu_interval_notifier_insert(&new_va_block->hmm.notifier, - mm, - new_va_block->start, - new_va_block->end - new_va_block->start + 1, + uvm_va_block_size(va_block), &uvm_hmm_notifier_ops); UVM_ASSERT(!ret); mmu_interval_notifier_remove(&split_data.notifier); - status = uvm_range_tree_add(&va_space->hmm.blocks, &new_va_block->hmm.node); - UVM_ASSERT(status == NV_OK); - if (new_block_ptr) *new_block_ptr = new_va_block; @@ -485,7 +545,7 @@ static NV_STATUS hmm_split_block(uvm_va_block_t *va_block, err: uvm_mutex_unlock(&va_block->lock); - mmu_interval_notifier_remove(&split_data.notifier); + mmu_interval_notifier_remove(&new_va_block->hmm.notifier); uvm_va_block_release(new_va_block); return status; } @@ -536,9 +596,9 @@ static NV_STATUS split_block_if_needed(uvm_va_block_t *va_block, // page tables. However, it doesn't destroy the va_block because that would // require calling mmu_interval_notifier_remove() which can't be called from // the invalidate callback due to Linux locking constraints. If a process -// calls mmap()/munmap() for SAM and then creates a UVM managed allocation, +// calls mmap()/munmap() for SAM and then creates a managed allocation, // the same VMA range can be picked and there would be a UVM/HMM va_block -// conflict. Creating a UVM managed allocation (or other va_range) calls this +// conflict. Creating a managed allocation (or other va_range) calls this // function to remove stale HMM va_blocks or split the HMM va_block so there // is no overlap. NV_STATUS uvm_hmm_va_block_reclaim(uvm_va_space_t *va_space, @@ -585,6 +645,18 @@ NV_STATUS uvm_hmm_va_block_reclaim(uvm_va_space_t *va_space, return NV_OK; } +void uvm_hmm_va_block_split_tree(uvm_va_block_t *existing_va_block, uvm_va_block_t *new_block) +{ + uvm_va_space_t *va_space = existing_va_block->hmm.va_space; + + UVM_ASSERT(uvm_va_block_is_hmm(existing_va_block)); + uvm_assert_rwsem_locked_write(&va_space->lock); + + uvm_range_tree_split(&existing_va_block->hmm.va_space->hmm.blocks, + &existing_va_block->hmm.node, + &new_block->hmm.node); +} + NV_STATUS uvm_hmm_split_as_needed(uvm_va_space_t *va_space, NvU64 addr, uvm_va_policy_is_split_needed_t split_needed_cb, @@ -733,7 +805,7 @@ void uvm_hmm_find_policy_end(uvm_va_block_t *va_block, { struct vm_area_struct *vma = va_block_context->hmm.vma; uvm_va_policy_node_t *node; - NvU64 end = *endp; + NvU64 end = va_block->end; uvm_assert_mmap_lock_locked(vma->vm_mm); uvm_assert_mutex_locked(&va_block->lock); @@ -747,8 +819,9 @@ void uvm_hmm_find_policy_end(uvm_va_block_t *va_block, if (end > node->node.end) end = node->node.end; } - else + else { va_block_context->policy = &uvm_va_policy_default; + } *endp = end; } @@ -760,7 +833,7 @@ NV_STATUS uvm_hmm_find_policy_vma_and_outer(uvm_va_block_t *va_block, { struct vm_area_struct *vma; unsigned long addr; - NvU64 end = va_block->end; + NvU64 end; uvm_page_index_t outer; UVM_ASSERT(uvm_va_block_is_hmm(va_block)); @@ -801,9 +874,9 @@ static NV_STATUS hmm_clear_thrashing_policy(uvm_va_block_t *va_block, // before the pinned pages information is destroyed. status = UVM_VA_BLOCK_RETRY_LOCKED(va_block, NULL, - unmap_remote_pinned_pages_from_all_processors(va_block, - block_context, - region)); + uvm_perf_thrashing_unmap_remote_pinned_pages_all(va_block, + block_context, + region)); uvm_perf_thrashing_info_destroy(va_block); @@ -839,5 +912,186 @@ NV_STATUS uvm_hmm_clear_thrashing_policy(uvm_va_space_t *va_space) return status; } +uvm_va_block_region_t uvm_hmm_get_prefetch_region(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + NvU64 address) +{ + struct vm_area_struct *vma = va_block_context->hmm.vma; + uvm_va_policy_t *policy = va_block_context->policy; + NvU64 start, end; + + UVM_ASSERT(uvm_va_block_is_hmm(va_block)); + + // We need to limit the prefetch region to the VMA. + start = max(va_block->start, (NvU64)vma->vm_start); + end = min(va_block->end, (NvU64)vma->vm_end - 1); + + // Also, we need to limit the prefetch region to the policy range. + if (policy == &uvm_va_policy_default) { + NV_STATUS status = uvm_range_tree_find_hole_in(&va_block->hmm.va_policy_tree, + address, + &start, + &end); + // We already know the hole exists and covers the fault region. + UVM_ASSERT(status == NV_OK); + } + else { + uvm_va_policy_node_t *node = uvm_va_policy_node_from_policy(policy); + + start = max(start, node->node.start); + end = min(end, node->node.end); + } + + return uvm_va_block_region_from_start_end(va_block, start, end); +} + +uvm_prot_t uvm_hmm_compute_logical_prot(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + NvU64 addr) +{ + struct vm_area_struct *vma = va_block_context->hmm.vma; + + UVM_ASSERT(uvm_va_block_is_hmm(va_block)); + uvm_assert_mmap_lock_locked(va_block_context->mm); + UVM_ASSERT(vma && addr >= vma->vm_start && addr < vma->vm_end); + + if (!(vma->vm_flags & VM_READ)) + return UVM_PROT_NONE; + else if (!(vma->vm_flags & VM_WRITE)) + return UVM_PROT_READ_ONLY; + else + return UVM_PROT_READ_WRITE_ATOMIC; +} + +NV_STATUS uvm_test_split_invalidate_delay(UVM_TEST_SPLIT_INVALIDATE_DELAY_PARAMS *params, struct file *filp) +{ + uvm_va_space_t *va_space = uvm_va_space_get(filp); + + atomic64_set(&va_space->test.split_invalidate_delay_us, params->delay_us); + + return NV_OK; +} + +NV_STATUS uvm_test_hmm_init(UVM_TEST_HMM_INIT_PARAMS *params, struct file *filp) +{ + uvm_va_space_t *va_space = uvm_va_space_get(filp); + struct mm_struct *mm; + NV_STATUS status; + + mm = uvm_va_space_mm_or_current_retain(va_space); + if (!mm) + return NV_WARN_NOTHING_TO_DO; + + uvm_down_write_mmap_lock(mm); + uvm_va_space_down_write(va_space); + if (va_space->hmm.disable) + status = uvm_hmm_va_space_initialize_test(va_space); + else + status = NV_OK; + uvm_va_space_up_write(va_space); + uvm_up_write_mmap_lock(mm); + uvm_va_space_mm_or_current_release(va_space, mm); + + return status; +} + +NV_STATUS uvm_hmm_va_range_info(uvm_va_space_t *va_space, + struct mm_struct *mm, + UVM_TEST_VA_RANGE_INFO_PARAMS *params) +{ + uvm_range_tree_node_t *tree_node; + uvm_va_policy_node_t *node; + struct vm_area_struct *vma; + uvm_va_block_t *va_block; + + if (!mm || !uvm_hmm_is_enabled(va_space)) + return NV_ERR_INVALID_ADDRESS; + + uvm_assert_mmap_lock_locked(mm); + uvm_assert_rwsem_locked(&va_space->lock); + + params->type = UVM_TEST_VA_RANGE_TYPE_MANAGED; + params->managed.subtype = UVM_TEST_RANGE_SUBTYPE_HMM; + params->va_range_start = 0; + params->va_range_end = ULONG_MAX; + params->read_duplication = UVM_TEST_READ_DUPLICATION_UNSET; + memset(¶ms->preferred_location, 0, sizeof(params->preferred_location)); + params->accessed_by_count = 0; + params->managed.vma_start = 0; + params->managed.vma_end = 0; + params->managed.is_zombie = NV_FALSE; + params->managed.owned_by_calling_process = (mm == current->mm ? NV_TRUE : NV_FALSE); + + vma = find_vma(mm, params->lookup_address); + if (!uvm_hmm_vma_is_valid(vma, params->lookup_address, false)) + return NV_ERR_INVALID_ADDRESS; + + params->va_range_start = vma->vm_start; + params->va_range_end = vma->vm_end - 1; + params->managed.vma_start = vma->vm_start; + params->managed.vma_end = vma->vm_end - 1; + + uvm_mutex_lock(&va_space->hmm.blocks_lock); + tree_node = uvm_range_tree_find(&va_space->hmm.blocks, params->lookup_address); + if (!tree_node) { + UVM_ASSERT(uvm_range_tree_find_hole_in(&va_space->hmm.blocks, params->lookup_address, + ¶ms->va_range_start, ¶ms->va_range_end) == NV_OK); + uvm_mutex_unlock(&va_space->hmm.blocks_lock); + return NV_OK; + } + + uvm_mutex_unlock(&va_space->hmm.blocks_lock); + va_block = hmm_va_block_from_node(tree_node); + uvm_mutex_lock(&va_block->lock); + + params->va_range_start = va_block->start; + params->va_range_end = va_block->end; + + node = uvm_va_policy_node_find(va_block, params->lookup_address); + if (node) { + uvm_processor_id_t processor_id; + + if (params->va_range_start < node->node.start) + params->va_range_start = node->node.start; + if (params->va_range_end > node->node.end) + params->va_range_end = node->node.end; + + params->read_duplication = node->policy.read_duplication; + + if (!UVM_ID_IS_INVALID(node->policy.preferred_location)) + uvm_va_space_processor_uuid(va_space, ¶ms->preferred_location, node->policy.preferred_location); + + for_each_id_in_mask(processor_id, &node->policy.accessed_by) + uvm_va_space_processor_uuid(va_space, ¶ms->accessed_by[params->accessed_by_count++], processor_id); + } + else { + uvm_range_tree_find_hole_in(&va_block->hmm.va_policy_tree, params->lookup_address, + ¶ms->va_range_start, ¶ms->va_range_end); + } + + uvm_mutex_unlock(&va_block->lock); + + return NV_OK; +} + +// TODO: Bug 3660968: Remove this hack as soon as HMM migration is implemented +// for VMAs other than anonymous private memory. +bool uvm_hmm_must_use_sysmem(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context) +{ + struct vm_area_struct *vma = va_block_context->hmm.vma; + + uvm_assert_mutex_locked(&va_block->lock); + + if (!uvm_va_block_is_hmm(va_block)) + return false; + + UVM_ASSERT(vma); + UVM_ASSERT(va_block_context->mm == vma->vm_mm); + uvm_assert_mmap_lock_locked(va_block_context->mm); + + return !vma_is_anonymous(vma); +} + #endif // UVM_IS_CONFIG_HMM() diff --git a/kernel-open/nvidia-uvm/uvm_hmm.h b/kernel-open/nvidia-uvm/uvm_hmm.h index b31de4488..738ebcbe5 100644 --- a/kernel-open/nvidia-uvm/uvm_hmm.h +++ b/kernel-open/nvidia-uvm/uvm_hmm.h @@ -65,6 +65,8 @@ typedef struct // Initialize HMM for the given the va_space for testing. // Bug 1750144: UVM: Add HMM (Heterogeneous Memory Management) support to // the UVM driver. Remove this when enough HMM functionality is implemented. + // Locking: the va_space->va_space_mm.mm mmap_lock must be write locked + // and the va_space lock must be held in write mode. NV_STATUS uvm_hmm_va_space_initialize_test(uvm_va_space_t *va_space); // Destroy any HMM state for the given the va_space. @@ -87,6 +89,10 @@ typedef struct // // Return NV_ERR_INVALID_ADDRESS if there is no VMA associated with the // address 'addr' or the VMA does not have at least PROT_READ permission. + // The caller is also responsible for checking that there is no UVM + // va_range covering the given address before calling this function. + // If va_block_context is not NULL, the VMA is cached in + // va_block_context->hmm.vma. // Locking: This function must be called with mm retained and locked for // at least read and the va_space lock at least for read. NV_STATUS uvm_hmm_va_block_find_create(uvm_va_space_t *va_space, @@ -94,23 +100,53 @@ typedef struct uvm_va_block_context_t *va_block_context, uvm_va_block_t **va_block_ptr); + // Find the VMA for the given address and set va_block_context->hmm.vma. + // Return NV_ERR_INVALID_ADDRESS if va_block_context->mm is NULL or there + // is no VMA associated with the address 'addr' or the VMA does not have at + // least PROT_READ permission. + // Locking: This function must be called with mm retained and locked for + // at least read or mm equal to NULL. + NV_STATUS uvm_hmm_find_vma(uvm_va_block_context_t *va_block_context, NvU64 addr); + + // If va_block is a HMM va_block, check that va_block_context->hmm.vma is + // not NULL and covers the given region. This always returns true and is + // intended to only be used with UVM_ASSERT(). + // Locking: This function must be called with the va_block lock held and if + // va_block is a HMM block, va_block_context->mm must be retained and + // locked for at least read. + bool uvm_hmm_va_block_context_vma_is_valid(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_va_block_region_t region); + + // Find or create a HMM va_block and mark it so the next va_block split + // will fail for testing purposes. + // Locking: This function must be called with mm retained and locked for + // at least read and the va_space lock at least for read. + NV_STATUS uvm_hmm_test_va_block_inject_split_error(uvm_va_space_t *va_space, NvU64 addr); + // Reclaim any HMM va_blocks that overlap the given range. - // Note that 'end' is inclusive. - // A HMM va_block can be reclaimed if it doesn't contain any "valid" VMAs. - // See uvm_hmm_vma_is_valid() for details. + // Note that 'end' is inclusive. If mm is NULL, any HMM va_block in the + // range will be reclaimed which assumes that the mm is being torn down + // and was not retained. // Return values: // NV_ERR_NO_MEMORY: Reclaim required a block split, which failed. // NV_OK: There were no HMM blocks in the range, or all HMM // blocks in the range were successfully reclaimed. // Locking: If mm is not NULL, it must equal va_space_mm.mm, the caller - // must hold a reference on it, and it must be locked for at least read - // mode. Also, the va_space lock must be held in write mode. + // must retain it with uvm_va_space_mm_or_current_retain() or be sure that + // mm->mm_users is not zero, and it must be locked for at least read mode. + // Also, the va_space lock must be held in write mode. // TODO: Bug 3372166: add asynchronous va_block reclaim. NV_STATUS uvm_hmm_va_block_reclaim(uvm_va_space_t *va_space, struct mm_struct *mm, NvU64 start, NvU64 end); + // This is called to update the va_space tree of HMM va_blocks after an + // existing va_block is split. + // Locking: the va_space lock must be held in write mode. + void uvm_hmm_va_block_split_tree(uvm_va_block_t *existing_va_block, uvm_va_block_t *new_block); + // Find a HMM policy range that needs to be split. The callback function // 'split_needed_cb' returns true if the policy range needs to be split. // If a policy range is split, the existing range is truncated to @@ -148,7 +184,7 @@ typedef struct // Note that 'last_address' is inclusive. // Locking: the va_space->va_space_mm.mm mmap_lock must be write locked // and the va_space lock must be held in write mode. - // TODO: Bug 2046423: need to implement read duplication support in Linux. + // TODO: Bug 3660922: need to implement HMM read duplication support. static NV_STATUS uvm_hmm_set_read_duplication(uvm_va_space_t *va_space, uvm_read_duplication_policy_t new_policy, NvU64 base, @@ -159,10 +195,11 @@ typedef struct return NV_OK; } - // Set va_block_context->policy to the policy covering the given address - // 'addr' and update the ending address '*endp' to the minimum of *endp, - // va_block_context->hmm.vma->vm_end - 1, and the ending address of the - // policy range. + // This function assigns va_block_context->policy to the policy covering + // the given address 'addr' and assigns the ending address '*endp' to the + // minimum of va_block->end, va_block_context->hmm.vma->vm_end - 1, and the + // ending address of the policy range. Note that va_block_context->hmm.vma + // is expected to be initialized before calling this function. // Locking: This function must be called with // va_block_context->hmm.vma->vm_mm retained and locked for least read and // the va_block lock held. @@ -171,11 +208,11 @@ typedef struct unsigned long addr, NvU64 *endp); - // Find the VMA for the page index 'page_index', - // set va_block_context->policy to the policy covering the given address, - // and update the ending page range '*outerp' to the minimum of *outerp, - // va_block_context->hmm.vma->vm_end - 1, and the ending address of the - // policy range. + // This function finds the VMA for the page index 'page_index' and assigns + // it to va_block_context->vma, sets va_block_context->policy to the policy + // covering the given address, and sets the ending page range '*outerp' + // to the minimum of *outerp, va_block_context->hmm.vma->vm_end - 1, the + // ending address of the policy range, and va_block->end. // Return NV_ERR_INVALID_ADDRESS if no VMA is found; otherwise, NV_OK. // Locking: This function must be called with // va_block_context->hmm.vma->vm_mm retained and locked for least read and @@ -189,6 +226,48 @@ typedef struct // Locking: va_space lock must be held in write mode. NV_STATUS uvm_hmm_clear_thrashing_policy(uvm_va_space_t *va_space); + // Return the expanded region around 'address' limited to the intersection + // of va_block start/end, vma start/end, and policy start/end. + // va_block_context must not be NULL, va_block_context->hmm.vma must be + // valid (this is usually set by uvm_hmm_va_block_find_create()), and + // va_block_context->policy must be valid. + // Locking: the caller must hold mm->mmap_lock in at least read mode, the + // va_space lock must be held in at least read mode, and the va_block lock + // held. + uvm_va_block_region_t uvm_hmm_get_prefetch_region(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + NvU64 address); + + // Return the logical protection allowed of a HMM va_block for the page at + // the given address. + // va_block_context must not be NULL and va_block_context->hmm.vma must be + // valid (this is usually set by uvm_hmm_va_block_find_create()). + // Locking: the caller must hold va_block_context->mm mmap_lock in at least + // read mode. + uvm_prot_t uvm_hmm_compute_logical_prot(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + NvU64 addr); + + NV_STATUS uvm_test_hmm_init(UVM_TEST_HMM_INIT_PARAMS *params, struct file *filp); + + NV_STATUS uvm_test_split_invalidate_delay(UVM_TEST_SPLIT_INVALIDATE_DELAY_PARAMS *params, + struct file *filp); + + NV_STATUS uvm_hmm_va_range_info(uvm_va_space_t *va_space, + struct mm_struct *mm, + UVM_TEST_VA_RANGE_INFO_PARAMS *params); + + // Return true if GPU fault new residency location should be system memory. + // va_block_context must not be NULL and va_block_context->hmm.vma must be + // valid (this is usually set by uvm_hmm_va_block_find_create()). + // TODO: Bug 3660968: Remove this hack as soon as HMM migration is + // implemented for VMAs other than anonymous memory. + // Locking: the va_block lock must be held. If the va_block is a HMM + // va_block, the va_block_context->mm must be retained and locked for least + // read. + bool uvm_hmm_must_use_sysmem(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context); + #else // UVM_IS_CONFIG_HMM() static bool uvm_hmm_is_enabled(uvm_va_space_t *va_space) @@ -230,6 +309,23 @@ typedef struct return NV_ERR_INVALID_ADDRESS; } + static NV_STATUS uvm_hmm_find_vma(uvm_va_block_context_t *va_block_context, NvU64 addr) + { + return NV_OK; + } + + static bool uvm_hmm_va_block_context_vma_is_valid(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_va_block_region_t region) + { + return true; + } + + static NV_STATUS uvm_hmm_test_va_block_inject_split_error(uvm_va_space_t *va_space, NvU64 addr) + { + return NV_ERR_INVALID_ADDRESS; + } + static NV_STATUS uvm_hmm_va_block_reclaim(uvm_va_space_t *va_space, struct mm_struct *mm, NvU64 start, @@ -238,6 +334,10 @@ typedef struct return NV_OK; } + static void uvm_hmm_va_block_split_tree(uvm_va_block_t *existing_va_block, uvm_va_block_t *new_block) + { + } + static NV_STATUS uvm_hmm_split_as_needed(uvm_va_space_t *va_space, NvU64 addr, uvm_va_policy_is_split_needed_t split_needed_cb, @@ -291,6 +391,44 @@ typedef struct return NV_OK; } + static uvm_va_block_region_t uvm_hmm_get_prefetch_region(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + NvU64 address) + { + return (uvm_va_block_region_t){}; + } + + static uvm_prot_t uvm_hmm_compute_logical_prot(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + NvU64 addr) + { + return UVM_PROT_NONE; + } + + static NV_STATUS uvm_test_hmm_init(UVM_TEST_HMM_INIT_PARAMS *params, struct file *filp) + { + return NV_WARN_NOTHING_TO_DO; + } + + static NV_STATUS uvm_test_split_invalidate_delay(UVM_TEST_SPLIT_INVALIDATE_DELAY_PARAMS *params, + struct file *filp) + { + return NV_ERR_INVALID_STATE; + } + + static NV_STATUS uvm_hmm_va_range_info(uvm_va_space_t *va_space, + struct mm_struct *mm, + UVM_TEST_VA_RANGE_INFO_PARAMS *params) + { + return NV_ERR_INVALID_ADDRESS; + } + + static bool uvm_hmm_must_use_sysmem(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context) + { + return false; + } + #endif // UVM_IS_CONFIG_HMM() #endif // _UVM_HMM_H_ diff --git a/kernel-open/nvidia-uvm/uvm_hmm_sanity_test.c b/kernel-open/nvidia-uvm/uvm_hmm_sanity_test.c index 1548e2d2b..98f060c92 100644 --- a/kernel-open/nvidia-uvm/uvm_hmm_sanity_test.c +++ b/kernel-open/nvidia-uvm/uvm_hmm_sanity_test.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2021 NVIDIA Corporation + Copyright (c) 2021-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -35,7 +35,7 @@ NV_STATUS uvm_test_hmm_sanity(UVM_TEST_HMM_SANITY_PARAMS *params, struct file *f uvm_va_block_t *hmm_block = NULL; NV_STATUS status; - mm = uvm_va_space_mm_retain(va_space); + mm = uvm_va_space_mm_or_current_retain(va_space); if (!mm) return NV_WARN_NOTHING_TO_DO; @@ -61,7 +61,7 @@ NV_STATUS uvm_test_hmm_sanity(UVM_TEST_HMM_SANITY_PARAMS *params, struct file *f status = uvm_hmm_va_block_find_create(va_space, 0UL, NULL, &hmm_block); TEST_CHECK_GOTO(status == NV_ERR_INVALID_ADDRESS, done); - // Try to create an HMM va_block which overlaps a UVM managed block. + // Try to create an HMM va_block which overlaps a managed block. // It should fail. status = uvm_hmm_va_block_find_create(va_space, params->uvm_address, NULL, &hmm_block); TEST_CHECK_GOTO(status == NV_ERR_INVALID_ADDRESS, done); @@ -77,14 +77,14 @@ NV_STATUS uvm_test_hmm_sanity(UVM_TEST_HMM_SANITY_PARAMS *params, struct file *f done: uvm_va_space_up_read(va_space); uvm_up_read_mmap_lock(mm); - uvm_va_space_mm_release(va_space); + uvm_va_space_mm_or_current_release(va_space, mm); return status; out: uvm_va_space_up_write(va_space); uvm_up_write_mmap_lock(mm); - uvm_va_space_mm_release(va_space); + uvm_va_space_mm_or_current_release(va_space, mm); return status; } diff --git a/kernel-open/nvidia-uvm/uvm_linux.c b/kernel-open/nvidia-uvm/uvm_linux.c index 5319ba4ea..f27252640 100644 --- a/kernel-open/nvidia-uvm/uvm_linux.c +++ b/kernel-open/nvidia-uvm/uvm_linux.c @@ -34,31 +34,6 @@ // the (out-of-tree) UVM driver from changes to the upstream Linux kernel. // -#if !defined(NV_ADDRESS_SPACE_INIT_ONCE_PRESENT) -void address_space_init_once(struct address_space *mapping) -{ - memset(mapping, 0, sizeof(*mapping)); - INIT_RADIX_TREE(&mapping->page_tree, GFP_ATOMIC); - -#if defined(NV_ADDRESS_SPACE_HAS_RWLOCK_TREE_LOCK) - // - // The .tree_lock member variable was changed from type rwlock_t, to - // spinlock_t, on 25 July 2008, by mainline commit - // 19fd6231279be3c3bdd02ed99f9b0eb195978064. - // - rwlock_init(&mapping->tree_lock); -#else - spin_lock_init(&mapping->tree_lock); -#endif - - spin_lock_init(&mapping->i_mmap_lock); - INIT_LIST_HEAD(&mapping->private_list); - spin_lock_init(&mapping->private_lock); - INIT_RAW_PRIO_TREE_ROOT(&mapping->i_mmap); - INIT_LIST_HEAD(&mapping->i_mmap_nonlinear); -} -#endif - #if UVM_CGROUP_ACCOUNTING_SUPPORTED() void uvm_memcg_context_start(uvm_memcg_context_t *context, struct mm_struct *mm) { diff --git a/kernel-open/nvidia-uvm/uvm_linux.h b/kernel-open/nvidia-uvm/uvm_linux.h index 675901737..94a5c3ce4 100644 --- a/kernel-open/nvidia-uvm/uvm_linux.h +++ b/kernel-open/nvidia-uvm/uvm_linux.h @@ -88,7 +88,7 @@ #include "nv-kthread-q.h" - #if NV_KTHREAD_Q_SUPPORTS_AFFINITY() == 1 && defined(NV_CPUMASK_OF_NODE_PRESENT) + #if defined(NV_CPUMASK_OF_NODE_PRESENT) #define UVM_THREAD_AFFINITY_SUPPORTED() 1 #else #define UVM_THREAD_AFFINITY_SUPPORTED() 0 @@ -136,8 +136,8 @@ static inline const struct cpumask *uvm_cpumask_of_node(int node) #endif // See bug 1707453 for further details about setting the minimum kernel version. -#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 32) -# error This driver does not support kernels older than 2.6.32! +#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0) +# error This driver does not support kernels older than 3.10! #endif #if !defined(VM_RESERVED) @@ -217,10 +217,6 @@ static inline const struct cpumask *uvm_cpumask_of_node(int node) #define NV_UVM_GFP_FLAGS (GFP_KERNEL) -#if !defined(NV_ADDRESS_SPACE_INIT_ONCE_PRESENT) - void address_space_init_once(struct address_space *mapping); -#endif - // Develop builds define DEBUG but enable optimization #if defined(DEBUG) && !defined(NVIDIA_UVM_DEVELOP) // Wrappers for functions not building correctly without optimizations on, @@ -352,23 +348,6 @@ static inline NvU64 NV_GETTIME(void) (bit) = find_next_zero_bit((addr), (size), (bit) + 1)) #endif -// bitmap_clear was added in 2.6.33 via commit c1a2a962a2ad103846e7950b4591471fabecece7 -#if !defined(NV_BITMAP_CLEAR_PRESENT) - static inline void bitmap_clear(unsigned long *map, unsigned int start, int len) - { - unsigned int index = start; - for_each_set_bit_from(index, map, start + len) - __clear_bit(index, map); - } - - static inline void bitmap_set(unsigned long *map, unsigned int start, int len) - { - unsigned int index = start; - for_each_clear_bit_from(index, map, start + len) - __set_bit(index, map); - } -#endif - // Added in 2.6.24 #ifndef ACCESS_ONCE #define ACCESS_ONCE(x) (*(volatile typeof(x) *)&(x)) @@ -439,17 +418,6 @@ static inline NvU64 NV_GETTIME(void) #define PAGE_ALIGNED(addr) (((addr) & (PAGE_SIZE - 1)) == 0) #endif -// Added in 2.6.37 via commit e1ca7788dec6773b1a2bce51b7141948f2b8bccf -#if !defined(NV_VZALLOC_PRESENT) - static inline void *vzalloc(unsigned long size) - { - void *p = vmalloc(size); - if (p) - memset(p, 0, size); - return p; - } -#endif - // Changed in 3.17 via commit 743162013d40ca612b4cb53d3a200dff2d9ab26e #if (NV_WAIT_ON_BIT_LOCK_ARGUMENT_COUNT == 3) #define UVM_WAIT_ON_BIT_LOCK(word, bit, mode) \ @@ -505,21 +473,6 @@ static bool radix_tree_empty(struct radix_tree_root *tree) #endif #endif -#if !defined(NV_USLEEP_RANGE_PRESENT) -static void __sched usleep_range(unsigned long min, unsigned long max) -{ - unsigned min_msec = min / 1000; - unsigned max_msec = max / 1000; - - if (min_msec != 0) - msleep(min_msec); - else if (max_msec != 0) - msleep(max_msec); - else - msleep(1); -} -#endif - typedef struct { struct mem_cgroup *new_memcg; diff --git a/kernel-open/nvidia-uvm/uvm_lock.h b/kernel-open/nvidia-uvm/uvm_lock.h index fe4f114bc..d6bd70649 100644 --- a/kernel-open/nvidia-uvm/uvm_lock.h +++ b/kernel-open/nvidia-uvm/uvm_lock.h @@ -337,7 +337,9 @@ // // - Channel lock // Order: UVM_LOCK_ORDER_CHANNEL -// Spinlock (uvm_spinlock_t) +// Spinlock (uvm_spinlock_t) or exclusive lock (mutex) +// +// Lock protecting the state of all the channels in a channel pool. // // - Tools global VA space list lock (g_tools_va_space_list_lock) // Order: UVM_LOCK_ORDER_TOOLS_VA_SPACE_LIST diff --git a/kernel-open/nvidia-uvm/uvm_map_external.c b/kernel-open/nvidia-uvm/uvm_map_external.c index 3b2752b2e..e6404e667 100644 --- a/kernel-open/nvidia-uvm/uvm_map_external.c +++ b/kernel-open/nvidia-uvm/uvm_map_external.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2021 NVIDIA Corporation + Copyright (c) 2016-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -605,7 +605,7 @@ static NV_STATUS uvm_create_external_range(uvm_va_space_t *va_space, UVM_CREATE_ return NV_ERR_INVALID_ADDRESS; // The mm needs to be locked in order to remove stale HMM va_blocks. - mm = uvm_va_space_mm_retain_lock(va_space); + mm = uvm_va_space_mm_or_current_retain_lock(va_space); uvm_va_space_down_write(va_space); // Create the new external VA range. @@ -619,7 +619,7 @@ static NV_STATUS uvm_create_external_range(uvm_va_space_t *va_space, UVM_CREATE_ } uvm_va_space_up_write(va_space); - uvm_va_space_mm_release_unlock(va_space, mm); + uvm_va_space_mm_or_current_release_unlock(va_space, mm); return status; } @@ -636,6 +636,11 @@ static NV_STATUS set_ext_gpu_map_location(uvm_ext_gpu_map_t *ext_gpu_map, { uvm_gpu_t *owning_gpu; + if (!mem_info->deviceDescendant && !mem_info->sysmem) { + ext_gpu_map->owning_gpu = NULL; + ext_gpu_map->is_sysmem = false; + return NV_OK; + } // This is a local or peer allocation, so the owning GPU must have been // registered. owning_gpu = uvm_va_space_get_gpu_by_uuid(va_space, &mem_info->uuid); diff --git a/kernel-open/nvidia-uvm/uvm_mem.c b/kernel-open/nvidia-uvm/uvm_mem.c index 455506239..1839b836d 100644 --- a/kernel-open/nvidia-uvm/uvm_mem.c +++ b/kernel-open/nvidia-uvm/uvm_mem.c @@ -523,7 +523,7 @@ static NV_STATUS mem_alloc_sysmem_chunks(uvm_mem_t *mem, struct mm_struct *mm, g // In case of failure, the caller is required to handle cleanup by calling // uvm_mem_free -static NV_STATUS mem_alloc_vidmem_chunks(uvm_mem_t *mem, bool zero) +static NV_STATUS mem_alloc_vidmem_chunks(uvm_mem_t *mem, bool zero, bool is_protected) { NV_STATUS status; @@ -559,7 +559,7 @@ static NV_STATUS mem_alloc_vidmem_chunks(uvm_mem_t *mem, bool zero) return NV_OK; } -static NV_STATUS mem_alloc_chunks(uvm_mem_t *mem, struct mm_struct *mm, bool zero) +static NV_STATUS mem_alloc_chunks(uvm_mem_t *mem, struct mm_struct *mm, bool zero, bool is_protected) { if (uvm_mem_is_sysmem(mem)) { gfp_t gfp_flags; @@ -581,7 +581,7 @@ static NV_STATUS mem_alloc_chunks(uvm_mem_t *mem, struct mm_struct *mm, bool zer return status; } - return mem_alloc_vidmem_chunks(mem, zero); + return mem_alloc_vidmem_chunks(mem, zero, is_protected); } static const char *mem_physical_source(uvm_mem_t *mem) @@ -618,6 +618,7 @@ NV_STATUS uvm_mem_alloc(const uvm_mem_alloc_params_t *params, uvm_mem_t **mem_ou { NV_STATUS status; uvm_mem_t *mem = NULL; + bool is_protected = false; UVM_ASSERT(params->size > 0); @@ -639,7 +640,7 @@ NV_STATUS uvm_mem_alloc(const uvm_mem_alloc_params_t *params, uvm_mem_t **mem_ou mem->physical_allocation_size = UVM_ALIGN_UP(mem->size, mem->chunk_size); mem->chunks_count = mem->physical_allocation_size / mem->chunk_size; - status = mem_alloc_chunks(mem, params->mm, params->zero); + status = mem_alloc_chunks(mem, params->mm, params->zero, is_protected); if (status != NV_OK) goto error; @@ -893,7 +894,7 @@ static void sysmem_unmap_gpu_phys(uvm_mem_t *mem, uvm_gpu_t *gpu) // partial map_gpu_sysmem_iommu() operation. break; } - uvm_gpu_unmap_cpu_pages(gpu, dma_addrs[i], mem->chunk_size); + uvm_gpu_unmap_cpu_pages(gpu->parent, dma_addrs[i], mem->chunk_size); dma_addrs[i] = 0; } @@ -914,7 +915,7 @@ static NV_STATUS sysmem_map_gpu_phys(uvm_mem_t *mem, uvm_gpu_t *gpu) return status; for (i = 0; i < mem->chunks_count; ++i) { - status = uvm_gpu_map_cpu_pages(gpu, + status = uvm_gpu_map_cpu_pages(gpu->parent, mem->sysmem.pages[i], mem->chunk_size, &mem->sysmem.dma_addrs[uvm_global_id_gpu_index(gpu->global_id)][i]); diff --git a/kernel-open/nvidia-uvm/uvm_mem.h b/kernel-open/nvidia-uvm/uvm_mem.h index def67cc6b..361e70f45 100644 --- a/kernel-open/nvidia-uvm/uvm_mem.h +++ b/kernel-open/nvidia-uvm/uvm_mem.h @@ -179,6 +179,8 @@ struct uvm_mem_struct // // There is no equivalent mask for vidmem, because only the backing // GPU can physical access the memory + // + // TODO: Bug 3723779: Share DMA mappings within a single parent GPU uvm_global_processor_mask_t mapped_on_phys; struct page **pages; diff --git a/kernel-open/nvidia-uvm/uvm_migrate.c b/kernel-open/nvidia-uvm/uvm_migrate.c index 6f9d6bddf..0786ed960 100644 --- a/kernel-open/nvidia-uvm/uvm_migrate.c +++ b/kernel-open/nvidia-uvm/uvm_migrate.c @@ -207,6 +207,8 @@ NV_STATUS uvm_va_block_migrate_locked(uvm_va_block_t *va_block, uvm_assert_mutex_locked(&va_block->lock); + va_block_context->policy = uvm_va_range_get_policy(va_block->va_range); + if (uvm_va_policy_is_read_duplicate(va_block_context->policy, va_space)) { status = uvm_va_block_make_resident_read_duplicate(va_block, va_block_retry, @@ -466,6 +468,8 @@ static NV_STATUS uvm_va_range_migrate(uvm_va_range_t *va_range, { NvU64 preunmap_range_start = start; + UVM_ASSERT(va_block_context->policy == uvm_va_range_get_policy(va_range)); + should_do_cpu_preunmap = should_do_cpu_preunmap && va_range_should_do_cpu_preunmap(va_block_context->policy, va_range->va_space); @@ -942,10 +946,8 @@ done: // benchmarks to see if a two-pass approach would be faster (first // pass pushes all GPU work asynchronously, second pass updates CPU // mappings synchronously). - if (mm) { + if (mm) uvm_up_read_mmap_lock_out_of_order(mm); - uvm_va_space_mm_or_current_release(va_space, mm); - } if (tracker_ptr) { // If requested, release semaphore @@ -973,6 +975,7 @@ done: } uvm_va_space_up_read(va_space); + uvm_va_space_mm_or_current_release(va_space, mm); // If the migration is known to be complete, eagerly dispatch the migration // events, instead of processing them on a later event flush. Note that an @@ -1043,13 +1046,12 @@ done: // benchmarks to see if a two-pass approach would be faster (first // pass pushes all GPU work asynchronously, second pass updates CPU // mappings synchronously). - if (mm) { + if (mm) uvm_up_read_mmap_lock_out_of_order(mm); - uvm_va_space_mm_or_current_release(va_space, mm); - } tracker_status = uvm_tracker_wait_deinit(&local_tracker); uvm_va_space_up_read(va_space); + uvm_va_space_mm_or_current_release(va_space, mm); // This API is synchronous, so wait for migrations to finish uvm_tools_flush_events(); diff --git a/kernel-open/nvidia-uvm/uvm_migrate_pageable.c b/kernel-open/nvidia-uvm/uvm_migrate_pageable.c index 446e58eda..49fa35f79 100644 --- a/kernel-open/nvidia-uvm/uvm_migrate_pageable.c +++ b/kernel-open/nvidia-uvm/uvm_migrate_pageable.c @@ -74,7 +74,7 @@ static NV_STATUS migrate_vma_page_copy_address(struct page *page, } else { // Sysmem/Indirect Peer - NV_STATUS status = uvm_gpu_map_cpu_page(copying_gpu, page, &state->dma.addrs[page_index]); + NV_STATUS status = uvm_gpu_map_cpu_page(copying_gpu->parent, page, &state->dma.addrs[page_index]); if (status != NV_OK) return status; @@ -628,7 +628,7 @@ void uvm_migrate_vma_finalize_and_map(struct migrate_vma *args, migrate_vma_stat if (state->dma.num_pages > 0) { for_each_set_bit(i, state->dma.page_mask, state->num_pages) - uvm_gpu_unmap_cpu_page(state->dma.addrs_gpus[i], state->dma.addrs[i]); + uvm_gpu_unmap_cpu_page(state->dma.addrs_gpus[i]->parent, state->dma.addrs[i]); } UVM_ASSERT(!bitmap_intersects(state->populate_pages_mask, state->allocation_failed_mask, state->num_pages)); diff --git a/kernel-open/nvidia-uvm/uvm_migrate_pageable.h b/kernel-open/nvidia-uvm/uvm_migrate_pageable.h index 3efa59fc3..3afedafd8 100644 --- a/kernel-open/nvidia-uvm/uvm_migrate_pageable.h +++ b/kernel-open/nvidia-uvm/uvm_migrate_pageable.h @@ -34,8 +34,8 @@ typedef struct { uvm_va_space_t *va_space; struct mm_struct *mm; - const unsigned long start; - const unsigned long length; + unsigned long start; + unsigned long length; uvm_processor_id_t dst_id; // dst_node_id may be clobbered by uvm_migrate_pageable(). diff --git a/kernel-open/nvidia-uvm/uvm_mmu.c b/kernel-open/nvidia-uvm/uvm_mmu.c index d1bfbf21b..db4785e1b 100644 --- a/kernel-open/nvidia-uvm/uvm_mmu.c +++ b/kernel-open/nvidia-uvm/uvm_mmu.c @@ -132,7 +132,7 @@ static NV_STATUS phys_mem_allocate_sysmem(uvm_page_tree_t *tree, NvLength size, // Check for fake GPUs from the unit test if (tree->gpu->parent->pci_dev) - status = uvm_gpu_map_cpu_pages(tree->gpu, out->handle.page, UVM_PAGE_ALIGN_UP(size), &dma_addr); + status = uvm_gpu_map_cpu_pages(tree->gpu->parent, out->handle.page, UVM_PAGE_ALIGN_UP(size), &dma_addr); else dma_addr = page_to_phys(out->handle.page); @@ -217,7 +217,7 @@ static void phys_mem_deallocate_sysmem(uvm_page_tree_t *tree, uvm_mmu_page_table UVM_ASSERT(ptr->addr.aperture == UVM_APERTURE_SYS); if (tree->gpu->parent->pci_dev) - uvm_gpu_unmap_cpu_pages(tree->gpu, ptr->addr.address, UVM_PAGE_ALIGN_UP(ptr->size)); + uvm_gpu_unmap_cpu_pages(tree->gpu->parent, ptr->addr.address, UVM_PAGE_ALIGN_UP(ptr->size)); __free_pages(ptr->handle.page, get_order(ptr->size)); } diff --git a/kernel-open/nvidia-uvm/uvm_perf_heuristics.c b/kernel-open/nvidia-uvm/uvm_perf_heuristics.c index 392f914ba..f3bf82318 100644 --- a/kernel-open/nvidia-uvm/uvm_perf_heuristics.c +++ b/kernel-open/nvidia-uvm/uvm_perf_heuristics.c @@ -50,7 +50,6 @@ NV_STATUS uvm_perf_heuristics_init() void uvm_perf_heuristics_exit() { uvm_perf_access_counters_exit(); - uvm_perf_prefetch_exit(); uvm_perf_thrashing_exit(); } @@ -73,9 +72,6 @@ NV_STATUS uvm_perf_heuristics_load(uvm_va_space_t *va_space) NV_STATUS status; status = uvm_perf_thrashing_load(va_space); - if (status != NV_OK) - return status; - status = uvm_perf_prefetch_load(va_space); if (status != NV_OK) return status; status = uvm_perf_access_counters_load(va_space); @@ -105,6 +101,5 @@ void uvm_perf_heuristics_unload(uvm_va_space_t *va_space) uvm_assert_rwsem_locked_write(&va_space->lock); uvm_perf_access_counters_unload(va_space); - uvm_perf_prefetch_unload(va_space); uvm_perf_thrashing_unload(va_space); } diff --git a/kernel-open/nvidia-uvm/uvm_perf_module.h b/kernel-open/nvidia-uvm/uvm_perf_module.h index b716ce208..0ec21d842 100644 --- a/kernel-open/nvidia-uvm/uvm_perf_module.h +++ b/kernel-open/nvidia-uvm/uvm_perf_module.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016 NVIDIA Corporation + Copyright (c) 2016-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -45,7 +45,6 @@ // // - UVM_PERF_MODULE_TYPE_THRASHING: detects memory thrashing scenarios and // provides thrashing prevention mechanisms -// - UVM_PERF_MODULE_TYPE_PREFETCH: detects memory prefetching opportunities // - UVM_PERF_MODULE_TYPE_ACCESS_COUNTERS: migrates memory using access counter // notifications typedef enum @@ -54,7 +53,6 @@ typedef enum UVM_PERF_MODULE_TYPE_TEST = UVM_PERF_MODULE_FIRST_TYPE, UVM_PERF_MODULE_TYPE_THRASHING, - UVM_PERF_MODULE_TYPE_PREFETCH, UVM_PERF_MODULE_TYPE_ACCESS_COUNTERS, UVM_PERF_MODULE_TYPE_COUNT, diff --git a/kernel-open/nvidia-uvm/uvm_perf_prefetch.c b/kernel-open/nvidia-uvm/uvm_perf_prefetch.c index 9effafa54..a89acdbc2 100644 --- a/kernel-open/nvidia-uvm/uvm_perf_prefetch.c +++ b/kernel-open/nvidia-uvm/uvm_perf_prefetch.c @@ -30,31 +30,6 @@ #include "uvm_va_range.h" #include "uvm_test.h" -// Global cache to allocate the per-VA block prefetch detection structures -static struct kmem_cache *g_prefetch_info_cache __read_mostly; - -// Per-VA block prefetch detection structure -typedef struct -{ - uvm_page_mask_t prefetch_pages; - - uvm_page_mask_t migrate_pages; - - uvm_va_block_bitmap_tree_t bitmap_tree; - - uvm_processor_id_t last_migration_proc_id; - - uvm_va_block_region_t region; - - size_t big_page_size; - - uvm_va_block_region_t big_pages_region; - - NvU16 pending_prefetch_pages; - - NvU16 fault_migrations_to_last_proc; -} block_prefetch_info_t; - // // Tunables for prefetch detection/prevention (configurable via module parameters) // @@ -88,19 +63,54 @@ static bool g_uvm_perf_prefetch_enable; static unsigned g_uvm_perf_prefetch_threshold; static unsigned g_uvm_perf_prefetch_min_faults; -// Callback declaration for the performance heuristics events -static void prefetch_block_destroy_cb(uvm_perf_event_t event_id, uvm_perf_event_data_t *event_data); +void uvm_perf_prefetch_bitmap_tree_iter_init(const uvm_perf_prefetch_bitmap_tree_t *bitmap_tree, + uvm_page_index_t page_index, + uvm_perf_prefetch_bitmap_tree_iter_t *iter) +{ + UVM_ASSERT(bitmap_tree->level_count > 0); + UVM_ASSERT_MSG(page_index < bitmap_tree->leaf_count, + "%zd vs %zd", + (size_t)page_index, + (size_t)bitmap_tree->leaf_count); -static uvm_va_block_region_t compute_prefetch_region(uvm_page_index_t page_index, block_prefetch_info_t *prefetch_info) + iter->level_idx = bitmap_tree->level_count - 1; + iter->node_idx = page_index; +} + +uvm_va_block_region_t uvm_perf_prefetch_bitmap_tree_iter_get_range(const uvm_perf_prefetch_bitmap_tree_t *bitmap_tree, + const uvm_perf_prefetch_bitmap_tree_iter_t *iter) +{ + NvU16 range_leaves = uvm_perf_tree_iter_leaf_range(bitmap_tree, iter); + NvU16 range_start = uvm_perf_tree_iter_leaf_range_start(bitmap_tree, iter); + uvm_va_block_region_t subregion = uvm_va_block_region(range_start, range_start + range_leaves); + + UVM_ASSERT(iter->level_idx >= 0); + UVM_ASSERT(iter->level_idx < bitmap_tree->level_count); + + return subregion; +} + +NvU16 uvm_perf_prefetch_bitmap_tree_iter_get_count(const uvm_perf_prefetch_bitmap_tree_t *bitmap_tree, + const uvm_perf_prefetch_bitmap_tree_iter_t *iter) +{ + uvm_va_block_region_t subregion = uvm_perf_prefetch_bitmap_tree_iter_get_range(bitmap_tree, iter); + + return uvm_page_mask_region_weight(&bitmap_tree->pages, subregion); +} + +static uvm_va_block_region_t compute_prefetch_region(uvm_page_index_t page_index, + uvm_perf_prefetch_bitmap_tree_t *bitmap_tree, + uvm_va_block_region_t max_prefetch_region) { NvU16 counter; - uvm_va_block_bitmap_tree_iter_t iter; - uvm_va_block_bitmap_tree_t *bitmap_tree = &prefetch_info->bitmap_tree; - uvm_va_block_region_t prefetch_region = uvm_va_block_region(bitmap_tree->leaf_count, - bitmap_tree->leaf_count + 1); + uvm_perf_prefetch_bitmap_tree_iter_t iter; + uvm_va_block_region_t prefetch_region = uvm_va_block_region(0, 0); - uvm_va_block_bitmap_tree_traverse_counters(counter, bitmap_tree, page_index, &iter) { - uvm_va_block_region_t subregion = uvm_va_block_bitmap_tree_iter_get_range(bitmap_tree, &iter); + uvm_perf_prefetch_bitmap_tree_traverse_counters(counter, + bitmap_tree, + page_index - max_prefetch_region.first + bitmap_tree->offset, + &iter) { + uvm_va_block_region_t subregion = uvm_perf_prefetch_bitmap_tree_iter_get_range(bitmap_tree, &iter); NvU16 subregion_pages = uvm_va_block_region_num_pages(subregion); UVM_ASSERT(counter <= subregion_pages); @@ -109,289 +119,287 @@ static uvm_va_block_region_t compute_prefetch_region(uvm_page_index_t page_index } // Clamp prefetch region to actual pages - if (prefetch_region.first < bitmap_tree->leaf_count) { - if (prefetch_region.first < prefetch_info->region.first) - prefetch_region.first = prefetch_info->region.first; + if (prefetch_region.outer) { + prefetch_region.first += max_prefetch_region.first; + if (prefetch_region.first < bitmap_tree->offset) { + prefetch_region.first = bitmap_tree->offset; + } + else { + prefetch_region.first -= bitmap_tree->offset; + if (prefetch_region.first < max_prefetch_region.first) + prefetch_region.first = max_prefetch_region.first; + } - if (prefetch_region.outer > prefetch_info->region.outer) - prefetch_region.outer = prefetch_info->region.outer; + prefetch_region.outer += max_prefetch_region.first; + if (prefetch_region.outer < bitmap_tree->offset) { + prefetch_region.outer = bitmap_tree->offset; + } + else { + prefetch_region.outer -= bitmap_tree->offset; + if (prefetch_region.outer > max_prefetch_region.outer) + prefetch_region.outer = max_prefetch_region.outer; + } } return prefetch_region; } -// Performance heuristics module for prefetch -static uvm_perf_module_t g_module_prefetch; - -static uvm_perf_module_event_callback_desc_t g_callbacks_prefetch[] = { - { UVM_PERF_EVENT_BLOCK_DESTROY, prefetch_block_destroy_cb }, - { UVM_PERF_EVENT_MODULE_UNLOAD, prefetch_block_destroy_cb }, - { UVM_PERF_EVENT_BLOCK_SHRINK, prefetch_block_destroy_cb } -}; - -// Get the prefetch detection struct for the given block -static block_prefetch_info_t *prefetch_info_get(uvm_va_block_t *va_block) -{ - return uvm_perf_module_type_data(va_block->perf_modules_data, UVM_PERF_MODULE_TYPE_PREFETCH); -} - -static void prefetch_info_destroy(uvm_va_block_t *va_block) -{ - block_prefetch_info_t *prefetch_info = prefetch_info_get(va_block); - if (prefetch_info) { - kmem_cache_free(g_prefetch_info_cache, prefetch_info); - uvm_perf_module_type_unset_data(va_block->perf_modules_data, UVM_PERF_MODULE_TYPE_PREFETCH); - } -} - -// Get the prefetch detection struct for the given block or create it if it -// does not exist -static block_prefetch_info_t *prefetch_info_get_create(uvm_va_block_t *va_block) -{ - block_prefetch_info_t *prefetch_info = prefetch_info_get(va_block); - if (!prefetch_info) { - // Create some ghost leaves so we can align the tree to big page boundary. We use the - // largest page size to handle the worst-case scenario - size_t big_page_size = UVM_PAGE_SIZE_128K; - uvm_va_block_region_t big_pages_region = uvm_va_block_big_page_region_all(va_block, big_page_size); - size_t num_leaves = uvm_va_block_num_cpu_pages(va_block); - - // If the va block is not big enough to fit 128KB pages, maybe it still can fit 64KB pages - if (big_pages_region.outer == 0) { - big_page_size = UVM_PAGE_SIZE_64K; - big_pages_region = uvm_va_block_big_page_region_all(va_block, big_page_size); - } - - if (big_pages_region.first > 0) - num_leaves += (big_page_size / PAGE_SIZE - big_pages_region.first); - - UVM_ASSERT(num_leaves <= PAGES_PER_UVM_VA_BLOCK); - - prefetch_info = nv_kmem_cache_zalloc(g_prefetch_info_cache, NV_UVM_GFP_FLAGS); - if (!prefetch_info) - goto fail; - - prefetch_info->last_migration_proc_id = UVM_ID_INVALID; - - uvm_va_block_bitmap_tree_init_from_page_count(&prefetch_info->bitmap_tree, num_leaves); - - uvm_perf_module_type_set_data(va_block->perf_modules_data, prefetch_info, UVM_PERF_MODULE_TYPE_PREFETCH); - } - - return prefetch_info; - -fail: - prefetch_info_destroy(va_block); - - return NULL; -} - -static void grow_fault_granularity_if_no_thrashing(block_prefetch_info_t *prefetch_info, +static void grow_fault_granularity_if_no_thrashing(uvm_perf_prefetch_bitmap_tree_t *bitmap_tree, uvm_va_block_region_t region, + uvm_page_index_t first, const uvm_page_mask_t *faulted_pages, const uvm_page_mask_t *thrashing_pages) { if (!uvm_page_mask_region_empty(faulted_pages, region) && (!thrashing_pages || uvm_page_mask_region_empty(thrashing_pages, region))) { - region.first += prefetch_info->region.first; - region.outer += prefetch_info->region.first; - uvm_page_mask_region_fill(&prefetch_info->bitmap_tree.pages, region); + UVM_ASSERT(region.first >= first); + region.first = region.first - first + bitmap_tree->offset; + region.outer = region.outer - first + bitmap_tree->offset; + UVM_ASSERT(region.outer <= bitmap_tree->leaf_count); + uvm_page_mask_region_fill(&bitmap_tree->pages, region); } } -static void grow_fault_granularity(uvm_va_block_t *va_block, - block_prefetch_info_t *prefetch_info, +static void grow_fault_granularity(uvm_perf_prefetch_bitmap_tree_t *bitmap_tree, + NvU32 big_page_size, + uvm_va_block_region_t big_pages_region, + uvm_va_block_region_t max_prefetch_region, const uvm_page_mask_t *faulted_pages, const uvm_page_mask_t *thrashing_pages) { - size_t num_big_pages; - size_t big_page_index; - uvm_va_block_region_t block_region = uvm_va_block_region_from_block(va_block); + uvm_page_index_t pages_per_big_page = big_page_size / PAGE_SIZE; + uvm_page_index_t page_index; + + // Migrate whole block if no big pages and no page in it is thrashing + if (!big_pages_region.outer) { + grow_fault_granularity_if_no_thrashing(bitmap_tree, + max_prefetch_region, + max_prefetch_region.first, + faulted_pages, + thrashing_pages); + return; + } // Migrate whole "prefix" if no page in it is thrashing - if (prefetch_info->big_pages_region.first > 0) { - uvm_va_block_region_t prefix_region = uvm_va_block_region(0, prefetch_info->big_pages_region.first); + if (big_pages_region.first > max_prefetch_region.first) { + uvm_va_block_region_t prefix_region = uvm_va_block_region(max_prefetch_region.first, big_pages_region.first); - grow_fault_granularity_if_no_thrashing(prefetch_info, prefix_region, faulted_pages, thrashing_pages); + grow_fault_granularity_if_no_thrashing(bitmap_tree, + prefix_region, + max_prefetch_region.first, + faulted_pages, + thrashing_pages); } // Migrate whole big pages if they are not thrashing - num_big_pages = uvm_va_block_num_big_pages(va_block, prefetch_info->big_page_size); - for (big_page_index = 0; big_page_index < num_big_pages; ++big_page_index) { - uvm_va_block_region_t big_region = uvm_va_block_big_page_region(va_block, - big_page_index, - prefetch_info->big_page_size); + for (page_index = big_pages_region.first; + page_index < big_pages_region.outer; + page_index += pages_per_big_page) { + uvm_va_block_region_t big_region = uvm_va_block_region(page_index, + page_index + pages_per_big_page); - grow_fault_granularity_if_no_thrashing(prefetch_info, big_region, faulted_pages, thrashing_pages); + grow_fault_granularity_if_no_thrashing(bitmap_tree, + big_region, + max_prefetch_region.first, + faulted_pages, + thrashing_pages); } // Migrate whole "suffix" if no page in it is thrashing - if (prefetch_info->big_pages_region.outer < block_region.outer) { - uvm_va_block_region_t suffix_region = uvm_va_block_region(prefetch_info->big_pages_region.outer, - block_region.outer); + if (big_pages_region.outer < max_prefetch_region.outer) { + uvm_va_block_region_t suffix_region = uvm_va_block_region(big_pages_region.outer, + max_prefetch_region.outer); - grow_fault_granularity_if_no_thrashing(prefetch_info, suffix_region, faulted_pages, thrashing_pages); + grow_fault_granularity_if_no_thrashing(bitmap_tree, + suffix_region, + max_prefetch_region.first, + faulted_pages, + thrashing_pages); } } -// Within a block we only allow prefetching to a single processor. Therefore, if two processors -// are accessing non-overlapping regions within the same block they won't benefit from -// prefetching. +// Within a block we only allow prefetching to a single processor. Therefore, +// if two processors are accessing non-overlapping regions within the same +// block they won't benefit from prefetching. // -// TODO: Bug 1778034: [uvm] Explore prefetching to different processors within a VA block -void uvm_perf_prefetch_prenotify_fault_migrations(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, - uvm_processor_id_t new_residency, - const uvm_page_mask_t *faulted_pages, - uvm_va_block_region_t region) +// TODO: Bug 1778034: [uvm] Explore prefetching to different processors within +// a VA block. +static NvU32 uvm_perf_prefetch_prenotify_fault_migrations(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t new_residency, + const uvm_page_mask_t *faulted_pages, + uvm_va_block_region_t faulted_region, + uvm_page_mask_t *prefetch_pages, + uvm_perf_prefetch_bitmap_tree_t *bitmap_tree) { uvm_page_index_t page_index; - block_prefetch_info_t *prefetch_info; const uvm_page_mask_t *resident_mask = NULL; const uvm_page_mask_t *thrashing_pages = NULL; uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); uvm_va_policy_t *policy = va_block_context->policy; + uvm_va_block_region_t max_prefetch_region; + NvU32 big_page_size; + uvm_va_block_region_t big_pages_region; - uvm_assert_rwsem_locked(&va_space->lock); - - if (!g_uvm_perf_prefetch_enable) - return; - - prefetch_info = prefetch_info_get_create(va_block); - if (!prefetch_info) - return; - - if (!uvm_id_equal(prefetch_info->last_migration_proc_id, new_residency)) { - prefetch_info->last_migration_proc_id = new_residency; - prefetch_info->fault_migrations_to_last_proc = 0; + if (!uvm_id_equal(va_block->prefetch_info.last_migration_proc_id, new_residency)) { + va_block->prefetch_info.last_migration_proc_id = new_residency; + va_block->prefetch_info.fault_migrations_to_last_proc = 0; } - prefetch_info->pending_prefetch_pages = 0; + // Compute the expanded region that prefetching is allowed from. + if (uvm_va_block_is_hmm(va_block)) { + max_prefetch_region = uvm_hmm_get_prefetch_region(va_block, + va_block_context, + uvm_va_block_region_start(va_block, faulted_region)); + } + else { + max_prefetch_region = uvm_va_block_region_from_block(va_block); + } + + uvm_page_mask_zero(prefetch_pages); if (UVM_ID_IS_CPU(new_residency) || va_block->gpus[uvm_id_gpu_index(new_residency)] != NULL) resident_mask = uvm_va_block_resident_mask_get(va_block, new_residency); // If this is a first-touch fault and the destination processor is the - // preferred location, populate the whole VA block + // preferred location, populate the whole max_prefetch_region. if (uvm_processor_mask_empty(&va_block->resident) && uvm_id_equal(new_residency, policy->preferred_location)) { - uvm_page_mask_region_fill(&prefetch_info->prefetch_pages, uvm_va_block_region_from_block(va_block)); + uvm_page_mask_region_fill(prefetch_pages, max_prefetch_region); goto done; } if (resident_mask) - uvm_page_mask_or(&prefetch_info->bitmap_tree.pages, resident_mask, faulted_pages); + uvm_page_mask_or(&bitmap_tree->pages, resident_mask, faulted_pages); else - uvm_page_mask_copy(&prefetch_info->bitmap_tree.pages, faulted_pages); + uvm_page_mask_copy(&bitmap_tree->pages, faulted_pages); - // Get the big page size for the new residency + // If we are using a subregion of the va_block, align bitmap_tree + uvm_page_mask_shift_right(&bitmap_tree->pages, &bitmap_tree->pages, max_prefetch_region.first); + + // Get the big page size for the new residency. // Assume 64K size if the new residency is the CPU or no GPU va space is // registered in the current process for this GPU. if (UVM_ID_IS_GPU(new_residency) && uvm_processor_mask_test(&va_space->registered_gpu_va_spaces, new_residency)) { uvm_gpu_t *gpu = uvm_va_space_get_gpu(va_space, new_residency); - prefetch_info->big_page_size = uvm_va_block_gpu_big_page_size(va_block, gpu); + + big_page_size = uvm_va_block_gpu_big_page_size(va_block, gpu); } else { - prefetch_info->big_page_size = UVM_PAGE_SIZE_64K; + big_page_size = UVM_PAGE_SIZE_64K; } + big_pages_region = uvm_va_block_big_page_region_subset(va_block, max_prefetch_region, big_page_size); + // Adjust the prefetch tree to big page granularity to make sure that we // get big page-friendly prefetching hints - prefetch_info->big_pages_region = uvm_va_block_big_page_region_all(va_block, prefetch_info->big_page_size); - if (prefetch_info->big_pages_region.first > 0) { - prefetch_info->region.first = prefetch_info->big_page_size / PAGE_SIZE - prefetch_info->big_pages_region.first; + if (big_pages_region.first - max_prefetch_region.first > 0) { + bitmap_tree->offset = big_page_size / PAGE_SIZE - (big_pages_region.first - max_prefetch_region.first); + bitmap_tree->leaf_count = uvm_va_block_region_num_pages(max_prefetch_region) + bitmap_tree->offset; - uvm_page_mask_shift_left(&prefetch_info->bitmap_tree.pages, - &prefetch_info->bitmap_tree.pages, - prefetch_info->region.first); + UVM_ASSERT(bitmap_tree->offset < big_page_size / PAGE_SIZE); + UVM_ASSERT(bitmap_tree->leaf_count <= PAGES_PER_UVM_VA_BLOCK); + + uvm_page_mask_shift_left(&bitmap_tree->pages, &bitmap_tree->pages, bitmap_tree->offset); } else { - prefetch_info->region.first = 0; + bitmap_tree->offset = 0; + bitmap_tree->leaf_count = uvm_va_block_region_num_pages(max_prefetch_region); } - prefetch_info->region.outer = prefetch_info->region.first + uvm_va_block_num_cpu_pages(va_block); + bitmap_tree->level_count = ilog2(roundup_pow_of_two(bitmap_tree->leaf_count)) + 1; thrashing_pages = uvm_perf_thrashing_get_thrashing_pages(va_block); - // Assume big pages by default. Prefetch the rest of 4KB subregions within the big page - // region unless there is thrashing. - grow_fault_granularity(va_block, prefetch_info, faulted_pages, thrashing_pages); + // Assume big pages by default. Prefetch the rest of 4KB subregions within + // the big page region unless there is thrashing. + grow_fault_granularity(bitmap_tree, + big_page_size, + big_pages_region, + max_prefetch_region, + faulted_pages, + thrashing_pages); // Do not compute prefetch regions with faults on pages that are thrashing if (thrashing_pages) - uvm_page_mask_andnot(&prefetch_info->migrate_pages, faulted_pages, thrashing_pages); + uvm_page_mask_andnot(&va_block_context->scratch_page_mask, faulted_pages, thrashing_pages); else - uvm_page_mask_copy(&prefetch_info->migrate_pages, faulted_pages); + uvm_page_mask_copy(&va_block_context->scratch_page_mask, faulted_pages); - // Update the tree using the migration mask to compute the pages to prefetch - uvm_page_mask_zero(&prefetch_info->prefetch_pages); - for_each_va_block_page_in_region_mask(page_index, &prefetch_info->migrate_pages, region) { - uvm_va_block_region_t prefetch_region = compute_prefetch_region(page_index + prefetch_info->region.first, - prefetch_info); - uvm_page_mask_region_fill(&prefetch_info->prefetch_pages, prefetch_region); + // Update the tree using the scratch mask to compute the pages to prefetch + for_each_va_block_page_in_region_mask(page_index, &va_block_context->scratch_page_mask, faulted_region) { + uvm_va_block_region_t region = compute_prefetch_region(page_index, bitmap_tree, max_prefetch_region); + + uvm_page_mask_region_fill(prefetch_pages, region); // Early out if we have already prefetched until the end of the VA block - if (prefetch_region.outer == prefetch_info->region.outer) + if (region.outer == max_prefetch_region.outer) break; } - // Adjust prefetching page mask - if (prefetch_info->region.first > 0) { - uvm_page_mask_shift_right(&prefetch_info->prefetch_pages, - &prefetch_info->prefetch_pages, - prefetch_info->region.first); - } - done: // Do not prefetch pages that are going to be migrated/populated due to a // fault - uvm_page_mask_andnot(&prefetch_info->prefetch_pages, - &prefetch_info->prefetch_pages, - faulted_pages); + uvm_page_mask_andnot(prefetch_pages, prefetch_pages, faulted_pages); // TODO: Bug 1765432: prefetching pages that are already mapped on the CPU // would trigger a remap, which may cause a large overhead. Therefore, // exclude them from the mask. - if (UVM_ID_IS_CPU(new_residency)) { + // For HMM, we don't know what pages are mapped by the CPU unless we try to + // migrate them. Prefetch pages will only be opportunistically migrated. + if (UVM_ID_IS_CPU(new_residency) && !uvm_va_block_is_hmm(va_block)) { uvm_page_mask_and(&va_block_context->scratch_page_mask, resident_mask, &va_block->cpu.pte_bits[UVM_PTE_BITS_CPU_READ]); - uvm_page_mask_andnot(&prefetch_info->prefetch_pages, - &prefetch_info->prefetch_pages, - &va_block_context->scratch_page_mask); + uvm_page_mask_andnot(prefetch_pages, prefetch_pages, &va_block_context->scratch_page_mask); } // Avoid prefetching pages that are thrashing - if (thrashing_pages) { - uvm_page_mask_andnot(&prefetch_info->prefetch_pages, - &prefetch_info->prefetch_pages, - thrashing_pages); - } + if (thrashing_pages) + uvm_page_mask_andnot(prefetch_pages, prefetch_pages, thrashing_pages); - prefetch_info->fault_migrations_to_last_proc += uvm_page_mask_region_weight(faulted_pages, region); - prefetch_info->pending_prefetch_pages = uvm_page_mask_weight(&prefetch_info->prefetch_pages); + va_block->prefetch_info.fault_migrations_to_last_proc += uvm_page_mask_region_weight(faulted_pages, faulted_region); + + return uvm_page_mask_weight(prefetch_pages); } -uvm_perf_prefetch_hint_t uvm_perf_prefetch_get_hint(uvm_va_block_t *va_block, - const uvm_page_mask_t *new_residency_mask) +void uvm_perf_prefetch_get_hint(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t new_residency, + const uvm_page_mask_t *faulted_pages, + uvm_va_block_region_t faulted_region, + uvm_perf_prefetch_bitmap_tree_t *bitmap_tree, + uvm_perf_prefetch_hint_t *out_hint) { - uvm_perf_prefetch_hint_t ret = UVM_PERF_PREFETCH_HINT_NONE(); - block_prefetch_info_t *prefetch_info; + uvm_va_policy_t *policy = va_block_context->policy; uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); + uvm_page_mask_t *prefetch_pages = &out_hint->prefetch_pages_mask; + NvU32 pending_prefetch_pages; + + uvm_assert_rwsem_locked(&va_space->lock); + uvm_assert_mutex_locked(&va_block->lock); + UVM_ASSERT(uvm_va_block_check_policy_is_valid(va_block, policy, faulted_region)); + UVM_ASSERT(uvm_hmm_va_block_context_vma_is_valid(va_block, va_block_context, faulted_region)); + + out_hint->residency = UVM_ID_INVALID; if (!g_uvm_perf_prefetch_enable) - return ret; + return; if (!va_space->test.page_prefetch_enabled) - return ret; + return; - prefetch_info = prefetch_info_get(va_block); - if (!prefetch_info) - return ret; + pending_prefetch_pages = uvm_perf_prefetch_prenotify_fault_migrations(va_block, + va_block_context, + new_residency, + faulted_pages, + faulted_region, + prefetch_pages, + bitmap_tree); - if (prefetch_info->fault_migrations_to_last_proc >= g_uvm_perf_prefetch_min_faults && - prefetch_info->pending_prefetch_pages > 0) { + if (va_block->prefetch_info.fault_migrations_to_last_proc >= g_uvm_perf_prefetch_min_faults && + pending_prefetch_pages > 0) { bool changed = false; uvm_range_group_range_t *rgr; @@ -402,62 +410,19 @@ uvm_perf_prefetch_hint_t uvm_perf_prefetch_get_hint(uvm_va_block_t *va_block, max(rgr->node.start, va_block->start), min(rgr->node.end, va_block->end)); - if (uvm_page_mask_region_empty(new_residency_mask, region) && - !uvm_page_mask_region_empty(&prefetch_info->prefetch_pages, region)) { - uvm_page_mask_region_clear(&prefetch_info->prefetch_pages, region); + if (uvm_page_mask_region_empty(faulted_pages, region) && + !uvm_page_mask_region_empty(prefetch_pages, region)) { + uvm_page_mask_region_clear(prefetch_pages, region); changed = true; } } if (changed) - prefetch_info->pending_prefetch_pages = uvm_page_mask_weight(&prefetch_info->prefetch_pages); + pending_prefetch_pages = uvm_page_mask_weight(prefetch_pages); - if (prefetch_info->pending_prefetch_pages > 0) { - ret.residency = prefetch_info->last_migration_proc_id; - ret.prefetch_pages_mask = &prefetch_info->prefetch_pages; - } + if (pending_prefetch_pages > 0) + out_hint->residency = va_block->prefetch_info.last_migration_proc_id; } - - return ret; -} - -void prefetch_block_destroy_cb(uvm_perf_event_t event_id, uvm_perf_event_data_t *event_data) -{ - uvm_va_block_t *va_block; - - UVM_ASSERT(g_uvm_perf_prefetch_enable); - - UVM_ASSERT(event_id == UVM_PERF_EVENT_BLOCK_DESTROY || - event_id == UVM_PERF_EVENT_MODULE_UNLOAD || - event_id == UVM_PERF_EVENT_BLOCK_SHRINK); - - if (event_id == UVM_PERF_EVENT_BLOCK_DESTROY) - va_block = event_data->block_destroy.block; - else if (event_id == UVM_PERF_EVENT_BLOCK_SHRINK) - va_block = event_data->block_shrink.block; - else - va_block = event_data->module_unload.block; - - if (!va_block) - return; - - prefetch_info_destroy(va_block); -} - -NV_STATUS uvm_perf_prefetch_load(uvm_va_space_t *va_space) -{ - if (!g_uvm_perf_prefetch_enable) - return NV_OK; - - return uvm_perf_module_load(&g_module_prefetch, va_space); -} - -void uvm_perf_prefetch_unload(uvm_va_space_t *va_space) -{ - if (!g_uvm_perf_prefetch_enable) - return; - - uvm_perf_module_unload(&g_module_prefetch, va_space); } NV_STATUS uvm_perf_prefetch_init() @@ -467,13 +432,6 @@ NV_STATUS uvm_perf_prefetch_init() if (!g_uvm_perf_prefetch_enable) return NV_OK; - uvm_perf_module_init("perf_prefetch", UVM_PERF_MODULE_TYPE_PREFETCH, g_callbacks_prefetch, - ARRAY_SIZE(g_callbacks_prefetch), &g_module_prefetch); - - g_prefetch_info_cache = NV_KMEM_CACHE_CREATE("block_prefetch_info_t", block_prefetch_info_t); - if (!g_prefetch_info_cache) - return NV_ERR_NO_MEMORY; - if (uvm_perf_prefetch_threshold <= 100) { g_uvm_perf_prefetch_threshold = uvm_perf_prefetch_threshold; } @@ -498,14 +456,6 @@ NV_STATUS uvm_perf_prefetch_init() return NV_OK; } -void uvm_perf_prefetch_exit() -{ - if (!g_uvm_perf_prefetch_enable) - return; - - kmem_cache_destroy_safe(&g_prefetch_info_cache); -} - NV_STATUS uvm_test_set_page_prefetch_policy(UVM_TEST_SET_PAGE_PREFETCH_POLICY_PARAMS *params, struct file *filp) { uvm_va_space_t *va_space = uvm_va_space_get(filp); diff --git a/kernel-open/nvidia-uvm/uvm_perf_prefetch.h b/kernel-open/nvidia-uvm/uvm_perf_prefetch.h index 3e052c451..aeee1bdfa 100644 --- a/kernel-open/nvidia-uvm/uvm_perf_prefetch.h +++ b/kernel-open/nvidia-uvm/uvm_perf_prefetch.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2019 NVIDIA Corporation + Copyright (c) 2016-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -30,32 +30,66 @@ typedef struct { - const uvm_page_mask_t *prefetch_pages_mask; + uvm_page_mask_t prefetch_pages_mask; uvm_processor_id_t residency; } uvm_perf_prefetch_hint_t; -// Global initialization/cleanup functions +// Encapsulates a counter tree built on top of a page mask bitmap in which each +// leaf represents a page in the block. It contains leaf_count and level_count +// so that it can use some macros for perf trees. +typedef struct +{ + uvm_page_mask_t pages; + + uvm_page_index_t offset; + + NvU16 leaf_count; + + NvU8 level_count; +} uvm_perf_prefetch_bitmap_tree_t; + +// Iterator for the bitmap tree. It contains level_idx and node_idx so that it +// can use some macros for perf trees. +typedef struct +{ + s8 level_idx; + + uvm_page_index_t node_idx; +} uvm_perf_prefetch_bitmap_tree_iter_t; + +// Global initialization function (no clean up needed). NV_STATUS uvm_perf_prefetch_init(void); -void uvm_perf_prefetch_exit(void); -// VA space Initialization/cleanup functions -NV_STATUS uvm_perf_prefetch_load(uvm_va_space_t *va_space); -void uvm_perf_prefetch_unload(uvm_va_space_t *va_space); +// Return a hint with the pages that may be prefetched in the block. +// The faulted_pages mask and faulted_region are the pages being migrated to +// the given residency. +// va_block_context must not be NULL, va_block_context->policy must be valid, +// and if the va_block is a HMM block, va_block_context->hmm.vma must be valid +// which also means the va_block_context->mm is not NULL, retained, and locked +// for at least read. +// Locking: The caller must hold the va_space lock and va_block lock. +void uvm_perf_prefetch_get_hint(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t new_residency, + const uvm_page_mask_t *faulted_pages, + uvm_va_block_region_t faulted_region, + uvm_perf_prefetch_bitmap_tree_t *bitmap_tree, + uvm_perf_prefetch_hint_t *out_hint); -// Obtain a hint with the pages that may be prefetched in the block -uvm_perf_prefetch_hint_t uvm_perf_prefetch_get_hint(uvm_va_block_t *va_block, - const uvm_page_mask_t *new_residency_mask); +void uvm_perf_prefetch_bitmap_tree_iter_init(const uvm_perf_prefetch_bitmap_tree_t *bitmap_tree, + uvm_page_index_t page_index, + uvm_perf_prefetch_bitmap_tree_iter_t *iter); +uvm_va_block_region_t uvm_perf_prefetch_bitmap_tree_iter_get_range(const uvm_perf_prefetch_bitmap_tree_t *bitmap_tree, + const uvm_perf_prefetch_bitmap_tree_iter_t *iter); +NvU16 uvm_perf_prefetch_bitmap_tree_iter_get_count(const uvm_perf_prefetch_bitmap_tree_t *bitmap_tree, + const uvm_perf_prefetch_bitmap_tree_iter_t *iter); -// Notify that the given mask of pages within region is going to migrate to -// the given residency. The caller must hold the va_space lock. -void uvm_perf_prefetch_prenotify_fault_migrations(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, - uvm_processor_id_t new_residency, - const uvm_page_mask_t *migrate_pages, - uvm_va_block_region_t region); - -#define UVM_PERF_PREFETCH_HINT_NONE() \ - (uvm_perf_prefetch_hint_t){ NULL, UVM_ID_INVALID } +#define uvm_perf_prefetch_bitmap_tree_traverse_counters(counter,tree,page,iter) \ + for (uvm_perf_prefetch_bitmap_tree_iter_init((tree), (page), (iter)), \ + (counter) = uvm_perf_prefetch_bitmap_tree_iter_get_count((tree), (iter)); \ + (iter)->level_idx >= 0; \ + (counter) = --(iter)->level_idx < 0? 0: \ + uvm_perf_prefetch_bitmap_tree_iter_get_count((tree), (iter))) #endif diff --git a/kernel-open/nvidia-uvm/uvm_perf_thrashing.c b/kernel-open/nvidia-uvm/uvm_perf_thrashing.c index 7d14c93e2..3a4dd7d91 100644 --- a/kernel-open/nvidia-uvm/uvm_perf_thrashing.c +++ b/kernel-open/nvidia-uvm/uvm_perf_thrashing.c @@ -458,7 +458,7 @@ static void cpu_thrashing_stats_exit(void) { if (g_cpu_thrashing_stats.procfs_file) { UVM_ASSERT(uvm_procfs_is_debug_enabled()); - uvm_procfs_destroy_entry(g_cpu_thrashing_stats.procfs_file); + proc_remove(g_cpu_thrashing_stats.procfs_file); g_cpu_thrashing_stats.procfs_file = NULL; } } @@ -522,7 +522,7 @@ static void gpu_thrashing_stats_destroy(uvm_gpu_t *gpu) uvm_perf_module_type_unset_data(gpu->perf_modules_data, UVM_PERF_MODULE_TYPE_THRASHING); if (gpu_thrashing->procfs_file) - uvm_procfs_destroy_entry(gpu_thrashing->procfs_file); + proc_remove(gpu_thrashing->procfs_file); uvm_kvfree(gpu_thrashing); } @@ -652,7 +652,6 @@ done: static void thrashing_reset_pages_in_region(uvm_va_block_t *va_block, NvU64 address, NvU64 bytes); -// Destroy the thrashing detection struct for the given block void uvm_perf_thrashing_info_destroy(uvm_va_block_t *va_block) { block_thrashing_info_t *block_thrashing = thrashing_info_get(va_block); @@ -1066,11 +1065,11 @@ static void thrashing_reset_pages_in_region(uvm_va_block_t *va_block, NvU64 addr // Unmap remote mappings from the given processors on the pinned pages // described by region and block_thrashing->pinned pages. -static NV_STATUS unmap_remote_pinned_pages_from_processors(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, - block_thrashing_info_t *block_thrashing, - uvm_va_block_region_t region, - const uvm_processor_mask_t *unmap_processors) +static NV_STATUS unmap_remote_pinned_pages(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + block_thrashing_info_t *block_thrashing, + uvm_va_block_region_t region, + const uvm_processor_mask_t *unmap_processors) { NV_STATUS status = NV_OK; NV_STATUS tracker_status; @@ -1116,17 +1115,16 @@ static NV_STATUS unmap_remote_pinned_pages_from_processors(uvm_va_block_t *va_bl return status; } -// Unmap remote mappings from all processors on the pinned pages -// described by region and block_thrashing->pinned pages. -NV_STATUS unmap_remote_pinned_pages_from_all_processors(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, - uvm_va_block_region_t region) +NV_STATUS uvm_perf_thrashing_unmap_remote_pinned_pages_all(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_va_block_region_t region) { block_thrashing_info_t *block_thrashing; uvm_processor_mask_t unmap_processors; - uvm_va_policy_t *policy; + uvm_va_policy_t *policy = va_block_context->policy; uvm_assert_mutex_locked(&va_block->lock); + UVM_ASSERT(uvm_va_block_check_policy_is_valid(va_block, policy, region)); block_thrashing = thrashing_info_get(va_block); if (!block_thrashing || !block_thrashing->pages) @@ -1137,15 +1135,9 @@ NV_STATUS unmap_remote_pinned_pages_from_all_processors(uvm_va_block_t *va_block // Unmap all mapped processors (that are not SetAccessedBy) with // no copy of the page - policy = uvm_va_policy_get(va_block, uvm_va_block_region_start(va_block, region)); - uvm_processor_mask_andnot(&unmap_processors, &va_block->mapped, &policy->accessed_by); - return unmap_remote_pinned_pages_from_processors(va_block, - va_block_context, - block_thrashing, - region, - &unmap_processors); + return unmap_remote_pinned_pages(va_block, va_block_context, block_thrashing, region, &unmap_processors); } // Check that we are not migrating pages away from its pinned location and @@ -1246,7 +1238,7 @@ void thrashing_event_cb(uvm_perf_event_t event_id, uvm_perf_event_data_t *event_ if (!va_space_thrashing->params.enable) return; - // TODO: Bug 2046423: HMM will need to look up the policy when + // TODO: Bug 3660922: HMM will need to look up the policy when // read duplication is supported. read_duplication = uvm_va_block_is_hmm(va_block) ? UVM_READ_DUPLICATION_UNSET : @@ -1796,6 +1788,7 @@ static void thrashing_unpin_pages(struct work_struct *work) struct delayed_work *dwork = to_delayed_work(work); va_space_thrashing_info_t *va_space_thrashing = container_of(dwork, va_space_thrashing_info_t, pinned_pages.dwork); uvm_va_space_t *va_space = va_space_thrashing->va_space; + uvm_va_block_context_t *va_block_context = &va_space_thrashing->pinned_pages.va_block_context; UVM_ASSERT(uvm_va_space_initialized(va_space) == NV_OK); @@ -1857,12 +1850,13 @@ static void thrashing_unpin_pages(struct work_struct *work) UVM_ASSERT(block_thrashing); UVM_ASSERT(uvm_page_mask_test(&block_thrashing->pinned_pages.mask, page_index)); - va_space_thrashing->pinned_pages.va_block_context.policy = + uvm_va_block_context_init(va_block_context, NULL); + va_block_context->policy = uvm_va_policy_get(va_block, uvm_va_block_cpu_page_address(va_block, page_index)); - unmap_remote_pinned_pages_from_all_processors(va_block, - &va_space_thrashing->pinned_pages.va_block_context, - uvm_va_block_region_for_page(page_index)); + uvm_perf_thrashing_unmap_remote_pinned_pages_all(va_block, + va_block_context, + uvm_va_block_region_for_page(page_index)); thrashing_reset_page(va_space_thrashing, va_block, block_thrashing, page_index); } @@ -2105,11 +2099,10 @@ NV_STATUS uvm_test_set_page_thrashing_policy(UVM_TEST_SET_PAGE_THRASHING_POLICY_ // Unmap may split PTEs and require a retry. Needs to be called // before the pinned pages information is destroyed. - status = UVM_VA_BLOCK_RETRY_LOCKED(va_block, - NULL, - unmap_remote_pinned_pages_from_all_processors(va_block, - block_context, - va_block_region)); + status = UVM_VA_BLOCK_RETRY_LOCKED(va_block, NULL, + uvm_perf_thrashing_unmap_remote_pinned_pages_all(va_block, + block_context, + va_block_region)); uvm_perf_thrashing_info_destroy(va_block); diff --git a/kernel-open/nvidia-uvm/uvm_perf_thrashing.h b/kernel-open/nvidia-uvm/uvm_perf_thrashing.h index cba9174b3..eeac8e1a5 100644 --- a/kernel-open/nvidia-uvm/uvm_perf_thrashing.h +++ b/kernel-open/nvidia-uvm/uvm_perf_thrashing.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2019 NVIDIA Corporation + Copyright (c) 2016-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -108,8 +108,11 @@ void uvm_perf_thrashing_info_destroy(uvm_va_block_t *va_block); // Unmap remote mappings from all processors on the pinned pages // described by region and block_thrashing->pinned pages. -NV_STATUS unmap_remote_pinned_pages_from_all_processors(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, - uvm_va_block_region_t region); +// va_block_context must not be NULL and va_block_context->policy must be valid. +// See the comments for uvm_va_block_check_policy_is_valid() in uvm_va_block.h. +// Locking: the va_block lock must be held. +NV_STATUS uvm_perf_thrashing_unmap_remote_pinned_pages_all(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_va_block_region_t region); #endif diff --git a/kernel-open/nvidia-uvm/uvm_perf_utils_test.c b/kernel-open/nvidia-uvm/uvm_perf_utils_test.c index 41ac15e4e..0ca6bd5ae 100644 --- a/kernel-open/nvidia-uvm/uvm_perf_utils_test.c +++ b/kernel-open/nvidia-uvm/uvm_perf_utils_test.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015 NVIDIA Corporation + Copyright (c) 2015-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -23,6 +23,7 @@ #include "uvm_perf_utils.h" #include "uvm_va_block.h" +#include "uvm_perf_prefetch.h" #include "uvm_test.h" static NV_STATUS test_saturating_counter_basic(void) @@ -681,10 +682,12 @@ fail: static NV_STATUS test_bitmap_tree_traversal(void) { int value; - uvm_va_block_bitmap_tree_t tree; - uvm_va_block_bitmap_tree_iter_t iter; + uvm_perf_prefetch_bitmap_tree_t tree; + uvm_perf_prefetch_bitmap_tree_iter_t iter; - uvm_va_block_bitmap_tree_init_from_page_count(&tree, 9); + tree.leaf_count = 9; + tree.level_count = ilog2(roundup_pow_of_two(tree.leaf_count)) + 1; + uvm_page_mask_zero(&tree.pages); TEST_CHECK_RET(tree.level_count == 5); TEST_CHECK_RET(tree.leaf_count == 9); @@ -695,7 +698,7 @@ static NV_STATUS test_bitmap_tree_traversal(void) uvm_page_mask_set(&tree.pages, 7); uvm_page_mask_set(&tree.pages, 8); - uvm_va_block_bitmap_tree_traverse_counters(value, &tree, 6, &iter) { + uvm_perf_prefetch_bitmap_tree_traverse_counters(value, &tree, 6, &iter) { if (iter.level_idx == 4) TEST_CHECK_RET(value == 0); else if (iter.level_idx == 3) diff --git a/kernel-open/nvidia-uvm/uvm_pmm_gpu.c b/kernel-open/nvidia-uvm/uvm_pmm_gpu.c index cca6e52b9..b50297563 100644 --- a/kernel-open/nvidia-uvm/uvm_pmm_gpu.c +++ b/kernel-open/nvidia-uvm/uvm_pmm_gpu.c @@ -591,19 +591,16 @@ error: return status; } -NV_STATUS uvm_pmm_gpu_alloc_kernel(uvm_pmm_gpu_t *pmm, - size_t num_chunks, - uvm_chunk_size_t chunk_size, - uvm_pmm_alloc_flags_t flags, - uvm_gpu_chunk_t **chunks, - uvm_tracker_t *out_tracker) +static NV_STATUS pmm_gpu_alloc_kernel(uvm_pmm_gpu_t *pmm, + size_t num_chunks, + uvm_chunk_size_t chunk_size, + uvm_pmm_gpu_memory_type_t memory_type, + uvm_pmm_alloc_flags_t flags, + uvm_gpu_chunk_t **chunks, + uvm_tracker_t *out_tracker) { - uvm_gpu_t *gpu = uvm_pmm_to_gpu(pmm); - NV_STATUS status; size_t i; - uvm_pmm_gpu_memory_type_t memory_type = UVM_PMM_GPU_MEMORY_TYPE_KERNEL; - - status = uvm_pmm_gpu_alloc(pmm, num_chunks, chunk_size, memory_type, flags, chunks, out_tracker); + NV_STATUS status = uvm_pmm_gpu_alloc(pmm, num_chunks, chunk_size, memory_type, flags, chunks, out_tracker); if (status != NV_OK) return status; @@ -618,6 +615,18 @@ NV_STATUS uvm_pmm_gpu_alloc_kernel(uvm_pmm_gpu_t *pmm, return NV_OK; } +NV_STATUS uvm_pmm_gpu_alloc_kernel(uvm_pmm_gpu_t *pmm, + size_t num_chunks, + uvm_chunk_size_t chunk_size, + uvm_pmm_alloc_flags_t flags, + uvm_gpu_chunk_t **chunks, + uvm_tracker_t *out_tracker) +{ + uvm_pmm_gpu_memory_type_t memory_type = UVM_PMM_GPU_MEMORY_TYPE_KERNEL; + + return pmm_gpu_alloc_kernel(pmm, num_chunks, chunk_size, memory_type, flags, chunks, out_tracker); +} + static void chunk_update_lists_locked(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk) { uvm_gpu_root_chunk_t *root_chunk = root_chunk_from_chunk(pmm, chunk); @@ -1174,7 +1183,7 @@ static void root_chunk_unmap_indirect_peer(uvm_pmm_gpu_t *pmm, uvm_gpu_root_chun if (status != NV_OK) UVM_ASSERT(uvm_global_get_status() != NV_OK); - uvm_gpu_unmap_cpu_pages(other_gpu, indirect_peer->dma_addrs[index], UVM_CHUNK_SIZE_MAX); + uvm_gpu_unmap_cpu_pages(other_gpu->parent, indirect_peer->dma_addrs[index], UVM_CHUNK_SIZE_MAX); uvm_processor_mask_clear(&root_chunk->indirect_peers_mapped, other_gpu->id); new_count = atomic64_dec_return(&indirect_peer->map_count); UVM_ASSERT(new_count >= 0); @@ -1304,7 +1313,7 @@ NV_STATUS uvm_pmm_gpu_indirect_peer_map(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chu root_chunk_lock(pmm, root_chunk); if (!uvm_processor_mask_test(&root_chunk->indirect_peers_mapped, accessing_gpu->id)) { - status = uvm_gpu_map_cpu_pages(accessing_gpu, + status = uvm_gpu_map_cpu_pages(accessing_gpu->parent, uvm_gpu_chunk_to_page(pmm, &root_chunk->chunk), UVM_CHUNK_SIZE_MAX, &indirect_peer->dma_addrs[index]); @@ -2705,7 +2714,8 @@ static NV_STATUS uvm_pmm_gpu_pma_evict_pages(void *void_pmm, NvU64 *pages, NvU32 num_pages_to_evict, NvU64 phys_start, - NvU64 phys_end) + NvU64 phys_end, + UVM_PMA_GPU_MEMORY_TYPE mem_type) { NV_STATUS status; uvm_pmm_gpu_t *pmm = (uvm_pmm_gpu_t *)void_pmm; @@ -2804,14 +2814,15 @@ static NV_STATUS uvm_pmm_gpu_pma_evict_pages_wrapper(void *void_pmm, NvU64 *pages, NvU32 num_pages_to_evict, NvU64 phys_start, - NvU64 phys_end) + NvU64 phys_end, + UVM_PMA_GPU_MEMORY_TYPE mem_type) { NV_STATUS status; // RM invokes the eviction callbacks with its API lock held, but not its GPU // lock. uvm_record_lock_rm_api(); - status = uvm_pmm_gpu_pma_evict_pages(void_pmm, page_size, pages, num_pages_to_evict, phys_start, phys_end); + status = uvm_pmm_gpu_pma_evict_pages(void_pmm, page_size, pages, num_pages_to_evict, phys_start, phys_end, mem_type); uvm_record_unlock_rm_api(); return status; } @@ -2821,19 +2832,24 @@ static NV_STATUS uvm_pmm_gpu_pma_evict_pages_wrapper_entry(void *void_pmm, NvU64 *pages, NvU32 num_pages_to_evict, NvU64 phys_start, - NvU64 phys_end) + NvU64 phys_end, + UVM_PMA_GPU_MEMORY_TYPE mem_type) { UVM_ENTRY_RET(uvm_pmm_gpu_pma_evict_pages_wrapper(void_pmm, page_size, pages, num_pages_to_evict, phys_start, - phys_end)); + phys_end, + mem_type)); } // See the documentation of pmaEvictRangeCb_t in pma.h for details of the // expected semantics. -static NV_STATUS uvm_pmm_gpu_pma_evict_range(void *void_pmm, NvU64 phys_begin, NvU64 phys_end) +static NV_STATUS uvm_pmm_gpu_pma_evict_range(void *void_pmm, + NvU64 phys_begin, + NvU64 phys_end, + UVM_PMA_GPU_MEMORY_TYPE mem_type) { NV_STATUS status; uvm_pmm_gpu_t *pmm = (uvm_pmm_gpu_t *)void_pmm; @@ -2922,21 +2938,27 @@ static NV_STATUS uvm_pmm_gpu_pma_evict_range(void *void_pmm, NvU64 phys_begin, N return NV_OK; } -static NV_STATUS uvm_pmm_gpu_pma_evict_range_wrapper(void *void_pmm, NvU64 phys_begin, NvU64 phys_end) +static NV_STATUS uvm_pmm_gpu_pma_evict_range_wrapper(void *void_pmm, + NvU64 phys_begin, + NvU64 phys_end, + UVM_PMA_GPU_MEMORY_TYPE mem_type) { NV_STATUS status; // RM invokes the eviction callbacks with its API lock held, but not its GPU // lock. uvm_record_lock_rm_api(); - status = uvm_pmm_gpu_pma_evict_range(void_pmm, phys_begin, phys_end); + status = uvm_pmm_gpu_pma_evict_range(void_pmm, phys_begin, phys_end, mem_type); uvm_record_unlock_rm_api(); return status; } -static NV_STATUS uvm_pmm_gpu_pma_evict_range_wrapper_entry(void *void_pmm, NvU64 phys_begin, NvU64 phys_end) +static NV_STATUS uvm_pmm_gpu_pma_evict_range_wrapper_entry(void *void_pmm, + NvU64 phys_begin, + NvU64 phys_end, + UVM_PMA_GPU_MEMORY_TYPE mem_type) { - UVM_ENTRY_RET(uvm_pmm_gpu_pma_evict_range_wrapper(void_pmm, phys_begin, phys_end)); + UVM_ENTRY_RET(uvm_pmm_gpu_pma_evict_range_wrapper(void_pmm, phys_begin, phys_end, mem_type)); } static void deinit_chunk_split_cache(uvm_pmm_gpu_t *pmm) @@ -3420,12 +3442,13 @@ NV_STATUS uvm_test_evict_chunk(UVM_TEST_EVICT_CHUNK_PARAMS *params, struct file params->evicted_physical_address = 0; params->chunk_size_backing_virtual = 0; - mm = uvm_va_space_mm_retain_lock(va_space); + mm = uvm_va_space_mm_or_current_retain_lock(va_space); uvm_va_space_down_read(va_space); gpu = uvm_va_space_get_gpu_by_uuid(va_space, ¶ms->gpu_uuid); if (!gpu || !uvm_gpu_supports_eviction(gpu)) { uvm_va_space_up_read(va_space); + uvm_va_space_mm_or_current_release_unlock(va_space, mm); return NV_ERR_INVALID_DEVICE; } pmm = &gpu->pmm; @@ -3436,13 +3459,24 @@ NV_STATUS uvm_test_evict_chunk(UVM_TEST_EVICT_CHUNK_PARAMS *params, struct file // For virtual mode, look up and retain the block first so that eviction can // be started without the VA space lock held. if (params->eviction_mode == UvmTestEvictModeVirtual) { - status = uvm_va_block_find_create(va_space, mm, params->address, NULL, &block); - if (status != NV_OK) { + uvm_va_block_context_t *block_context; + + block_context = uvm_va_block_context_alloc(mm); + if (!block_context) { + status = NV_ERR_NO_MEMORY; uvm_va_space_up_read(va_space); uvm_va_space_mm_release_unlock(va_space, mm); goto out; } + status = uvm_va_block_find_create(va_space, params->address, block_context, &block); + uvm_va_block_context_free(block_context); + if (status != NV_OK) { + uvm_va_space_up_read(va_space); + uvm_va_space_mm_or_current_release_unlock(va_space, mm); + goto out; + } + // Retain the block before unlocking the VA space lock so that we can // safely access it later. uvm_va_block_retain(block); @@ -3451,7 +3485,7 @@ NV_STATUS uvm_test_evict_chunk(UVM_TEST_EVICT_CHUNK_PARAMS *params, struct file // Unlock the VA space to emulate real eviction better where a VA space lock // may not be held or may be held for a different VA space. uvm_va_space_up_read(va_space); - uvm_va_space_mm_release_unlock(va_space, mm); + uvm_va_space_mm_or_current_release_unlock(va_space, mm); if (params->eviction_mode == UvmTestEvictModeVirtual) { UVM_ASSERT(block); diff --git a/kernel-open/nvidia-uvm/uvm_pmm_sysmem.c b/kernel-open/nvidia-uvm/uvm_pmm_sysmem.c index 97f367146..d8345f95e 100644 --- a/kernel-open/nvidia-uvm/uvm_pmm_sysmem.c +++ b/kernel-open/nvidia-uvm/uvm_pmm_sysmem.c @@ -428,10 +428,10 @@ uvm_chunk_sizes_mask_t uvm_cpu_chunk_get_allocation_sizes(void) return uvm_cpu_chunk_allocation_sizes & UVM_CPU_CHUNK_SIZES; } -static void uvm_cpu_chunk_set_phys_size(uvm_cpu_chunk_t *chunk, uvm_chunk_size_t size) +static void uvm_cpu_chunk_set_size(uvm_cpu_chunk_t *chunk, uvm_chunk_size_t size) { #if !UVM_CPU_CHUNK_SIZE_IS_PAGE_SIZE() - chunk->log2_phys_size = ilog2(size); + chunk->log2_size = ilog2(size); #endif } @@ -440,13 +440,7 @@ uvm_chunk_size_t uvm_cpu_chunk_get_size(uvm_cpu_chunk_t *chunk) #if UVM_CPU_CHUNK_SIZE_IS_PAGE_SIZE() return PAGE_SIZE; #else - uvm_chunk_size_t chunk_size; - - UVM_ASSERT(chunk); - UVM_ASSERT(uvm_cpu_chunk_get_phys_size(chunk)); - chunk_size = uvm_va_block_region_size(chunk->region); - UVM_ASSERT(uvm_cpu_chunk_get_phys_size(chunk) >= chunk_size); - return chunk_size; + return ((uvm_chunk_size_t)1) << chunk->log2_size; #endif } @@ -1036,8 +1030,7 @@ void uvm_cpu_chunk_remove_from_block(uvm_va_block_t *va_block, uvm_cpu_chunk_t * return; }; - uvm_page_mask_region_clear(&va_block->cpu.allocated, - uvm_va_block_region(page_index, page_index + uvm_cpu_chunk_num_pages(chunk))); + uvm_page_mask_region_clear(&va_block->cpu.allocated, chunk->region); if (uvm_page_mask_empty(&va_block->cpu.allocated)) { if (UVM_CPU_STORAGE_GET_TYPE(va_block) != UVM_CPU_CHUNK_STORAGE_CHUNK) @@ -1191,7 +1184,7 @@ NV_STATUS uvm_cpu_chunk_alloc(uvm_va_block_t *va_block, } chunk->page = page; - uvm_cpu_chunk_set_phys_size(chunk, alloc_size); + uvm_cpu_chunk_set_size(chunk, alloc_size); chunk->region = region; nv_kref_init(&chunk->refcount); uvm_spin_lock_init(&chunk->lock, UVM_LOCK_ORDER_LEAF); @@ -1224,13 +1217,15 @@ error: return status; } -NV_STATUS uvm_cpu_chunk_split(uvm_va_block_t *va_block, uvm_cpu_chunk_t *chunk, uvm_chunk_size_t new_size) +NV_STATUS uvm_cpu_chunk_split(uvm_va_block_t *va_block, + uvm_cpu_chunk_t *chunk, + uvm_chunk_size_t new_size, + uvm_page_index_t page_index, + uvm_cpu_chunk_t **new_chunks) { NV_STATUS status = NV_OK; - NV_STATUS insert_status; uvm_cpu_chunk_t *new_chunk; - uvm_page_index_t running_page_index = chunk->region.first; - uvm_page_index_t next_page_index; + uvm_page_index_t running_page_index = page_index; size_t num_new_chunks; size_t num_subchunk_pages; size_t i; @@ -1238,21 +1233,13 @@ NV_STATUS uvm_cpu_chunk_split(uvm_va_block_t *va_block, uvm_cpu_chunk_t *chunk, UVM_ASSERT(chunk); UVM_ASSERT(is_power_of_2(new_size)); UVM_ASSERT(new_size < uvm_cpu_chunk_get_size(chunk)); + UVM_ASSERT(new_chunks); - // We subtract 1 from the computed number of subchunks because we always - // keep the original chunk as the first in the block's list. This is so we - // don't lose the physical chunk. - // All new subchunks will point to the original chunk as their parent. - num_new_chunks = (uvm_cpu_chunk_get_size(chunk) / new_size) - 1; + num_new_chunks = uvm_cpu_chunk_get_size(chunk) / new_size; num_subchunk_pages = new_size / PAGE_SIZE; - running_page_index += num_subchunk_pages; - - // Remove the existing chunk from the block first. We re-insert it after - // the split. - uvm_cpu_chunk_remove_from_block(va_block, chunk, chunk->region.first); for (i = 0; i < num_new_chunks; i++) { - uvm_page_index_t relative_page_index = running_page_index - chunk->region.first; + uvm_page_index_t relative_page_index = running_page_index - page_index; uvm_gpu_id_t id; new_chunk = uvm_kvmalloc_zero(sizeof(*new_chunk)); @@ -1264,10 +1251,10 @@ NV_STATUS uvm_cpu_chunk_split(uvm_va_block_t *va_block, uvm_cpu_chunk_t *chunk, new_chunk->page = chunk->page + relative_page_index; new_chunk->offset = chunk->offset + relative_page_index; new_chunk->region = uvm_va_block_region(running_page_index, running_page_index + num_subchunk_pages); - uvm_cpu_chunk_set_phys_size(new_chunk, new_size); + uvm_cpu_chunk_set_size(new_chunk, new_size); nv_kref_init(&new_chunk->refcount); - // This lock is unused for logical blocks but initialize it for + // This lock is unused for logical chunks but initialize it for // consistency. uvm_spin_lock_init(&new_chunk->lock, UVM_LOCK_ORDER_LEAF); new_chunk->parent = chunk; @@ -1286,109 +1273,64 @@ NV_STATUS uvm_cpu_chunk_split(uvm_va_block_t *va_block, uvm_cpu_chunk_t *chunk, parent_dma_addr + (relative_page_index * PAGE_SIZE)); } - status = uvm_cpu_chunk_insert_in_block(va_block, new_chunk, new_chunk->region.first); - if (status != NV_OK) { - uvm_cpu_chunk_put(new_chunk); - goto error; - } - + new_chunks[i] = new_chunk; running_page_index += num_subchunk_pages; } - chunk->region = uvm_va_block_region(chunk->region.first, chunk->region.first + num_subchunk_pages); + // Drop the original reference count on the parent (from its creation). This + // is done so the parent's reference count goes to 0 when all the children + // are released. + uvm_cpu_chunk_put(chunk); error: - // Re-insert the split chunk. This is done unconditionally in both the - // success and error paths. The difference is that on the success path, - // the chunk's region has been updated. - // This operation should never fail with NV_ERR_NO_MEMORY since all - // state memory should already be allocated. Failing with other errors - // is a programmer error. - insert_status = uvm_cpu_chunk_insert_in_block(va_block, chunk, chunk->region.first); - UVM_ASSERT(insert_status != NV_ERR_INVALID_ARGUMENT && insert_status != NV_ERR_INVALID_STATE); - if (status != NV_OK) { - for_each_cpu_chunk_in_block_region_safe(new_chunk, - running_page_index, - next_page_index, - va_block, - chunk->region) { - uvm_cpu_chunk_remove_from_block(va_block, new_chunk, new_chunk->region.first); + while (i--) uvm_cpu_chunk_put(new_chunk); - } } return status; } -uvm_cpu_chunk_t *uvm_cpu_chunk_merge(uvm_va_block_t *va_block, uvm_cpu_chunk_t *chunk) +NV_STATUS uvm_cpu_chunk_merge(uvm_va_block_t *va_block, + uvm_cpu_chunk_t **chunks, + size_t num_merge_chunks, + uvm_chunk_size_t merge_size, + uvm_cpu_chunk_t **merged_chunk) { uvm_cpu_chunk_t *parent; - uvm_cpu_chunk_t *subchunk; - uvm_chunk_sizes_mask_t merge_sizes = uvm_cpu_chunk_get_allocation_sizes(); - uvm_chunk_size_t merge_chunk_size; - uvm_chunk_size_t parent_phys_size; uvm_chunk_size_t chunk_size; - uvm_va_block_region_t subchunk_region; - uvm_page_index_t page_index; - uvm_page_index_t next_page_index; - NV_STATUS insert_status; + size_t i; - UVM_ASSERT(chunk); - parent = chunk->parent; + UVM_ASSERT(chunks); + UVM_ASSERT(num_merge_chunks > 0); + UVM_ASSERT(merged_chunk); - // If the chunk does not have a parent, a merge cannot be done. + parent = chunks[0]->parent; if (!parent) - return NULL; + return NV_WARN_NOTHING_TO_DO; - chunk_size = uvm_cpu_chunk_get_size(chunk); - parent_phys_size = uvm_cpu_chunk_get_phys_size(parent); + chunk_size = uvm_cpu_chunk_get_size(chunks[0]); - // Remove all sizes above the parent's physical size. - merge_sizes &= parent_phys_size | (parent_phys_size - 1); + UVM_ASSERT(uvm_cpu_chunk_get_size(parent) == merge_size); + UVM_ASSERT(merge_size > chunk_size); - // Remove all sizes including and below the chunk's current size. - merge_sizes &= ~(chunk_size | (chunk_size - 1)); + for (i = 1; i < num_merge_chunks; i++) { + if (chunks[i]->parent != parent || uvm_cpu_chunk_get_size(chunks[i]) != chunk_size) + return NV_ERR_INVALID_ARGUMENT; - // Find the largest size that is fully contained within the VA block. - for_each_chunk_size_rev(merge_chunk_size, merge_sizes) { - NvU64 parent_start = uvm_cpu_chunk_get_virt_addr(va_block, parent); - NvU64 parent_end = parent_start + parent_phys_size - 1; - - if (uvm_va_block_contains_address(va_block, parent_start) && - uvm_va_block_contains_address(va_block, parent_start + merge_chunk_size - 1) && - IS_ALIGNED(parent_start, merge_chunk_size) && - IS_ALIGNED(parent_end + 1, merge_chunk_size)) - break; + UVM_ASSERT(nv_kref_read(&chunks[i]->refcount) == 1); } - if (merge_chunk_size == UVM_CHUNK_SIZE_INVALID) - return NULL; + // Take a reference on the parent chunk so it doesn't get released when all + // of the children are released below. + uvm_cpu_chunk_get(parent); - if (uvm_cpu_chunk_get_size(parent) == merge_chunk_size) - return NULL; + for (i = 0; i < num_merge_chunks; i++) + uvm_cpu_chunk_put(chunks[i]); - UVM_ASSERT(chunk_size == uvm_cpu_chunk_get_size(parent)); - UVM_ASSERT(IS_ALIGNED(merge_chunk_size, chunk_size)); + *merged_chunk = parent; - subchunk_region = uvm_va_block_region(parent->region.first + uvm_cpu_chunk_num_pages(parent), - parent->region.first + (merge_chunk_size / PAGE_SIZE)); - - // Remove the first (parent) subchunk. It will be re-inserted later with an - // updated region. - uvm_cpu_chunk_remove_from_block(va_block, parent, parent->region.first); - - for_each_cpu_chunk_in_block_region_safe(subchunk, page_index, next_page_index, va_block, subchunk_region) { - UVM_ASSERT(subchunk); - uvm_cpu_chunk_remove_from_block(va_block, subchunk, subchunk->region.first); - uvm_cpu_chunk_put(subchunk); - } - - parent->region = uvm_va_block_region(parent->region.first, parent->region.first + (merge_chunk_size / PAGE_SIZE)); - insert_status = uvm_cpu_chunk_insert_in_block(va_block, parent, parent->region.first); - UVM_ASSERT(insert_status != NV_ERR_INVALID_ARGUMENT && insert_status != NV_ERR_INVALID_STATE); - - return parent; + return NV_OK; } static uvm_cpu_chunk_t *get_parent_cpu_chunk(uvm_cpu_chunk_t *chunk) @@ -1414,7 +1356,7 @@ static void check_cpu_dirty_flag(uvm_cpu_chunk_t *chunk, uvm_page_index_t page_i // compound pages. page = chunk->page + page_index; if (PageDirty(page)) { - bitmap_fill(chunk->dirty_bitmap, uvm_cpu_chunk_get_phys_size(chunk) / PAGE_SIZE); + bitmap_fill(chunk->dirty_bitmap, uvm_cpu_chunk_get_size(chunk) / PAGE_SIZE); ClearPageDirty(page); } } @@ -1432,7 +1374,7 @@ static uvm_cpu_chunk_t *get_parent_and_page_index(uvm_cpu_chunk_t *chunk, uvm_pa page_index = chunk->offset + (page_index - chunk->region.first); parent = get_parent_cpu_chunk(chunk); - UVM_ASSERT(page_index < uvm_cpu_chunk_get_phys_size(parent) / PAGE_SIZE); + UVM_ASSERT(page_index < uvm_cpu_chunk_get_size(parent) / PAGE_SIZE); *out_page_index = page_index; return parent; } @@ -1442,7 +1384,7 @@ void uvm_cpu_chunk_mark_dirty(uvm_cpu_chunk_t *chunk, uvm_page_index_t page_inde uvm_cpu_chunk_t *parent; parent = get_parent_and_page_index(chunk, &page_index); - if (uvm_cpu_chunk_get_phys_size(parent) == PAGE_SIZE) { + if (uvm_cpu_chunk_get_size(parent) == PAGE_SIZE) { SetPageDirty(parent->page); return; } @@ -1457,7 +1399,7 @@ void uvm_cpu_chunk_mark_clean(uvm_cpu_chunk_t *chunk, uvm_page_index_t page_inde uvm_cpu_chunk_t *parent; parent = get_parent_and_page_index(chunk, &page_index); - if (uvm_cpu_chunk_get_phys_size(parent) == PAGE_SIZE) { + if (uvm_cpu_chunk_get_size(parent) == PAGE_SIZE) { ClearPageDirty(parent->page); return; } @@ -1474,7 +1416,7 @@ bool uvm_cpu_chunk_is_dirty(uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) bool dirty; parent = get_parent_and_page_index(chunk, &page_index); - if (uvm_cpu_chunk_get_phys_size(parent) == PAGE_SIZE) + if (uvm_cpu_chunk_get_size(parent) == PAGE_SIZE) return PageDirty(parent->page); uvm_spin_lock(&parent->lock); diff --git a/kernel-open/nvidia-uvm/uvm_pmm_sysmem.h b/kernel-open/nvidia-uvm/uvm_pmm_sysmem.h index 053ac96f2..cbb9ccb95 100644 --- a/kernel-open/nvidia-uvm/uvm_pmm_sysmem.h +++ b/kernel-open/nvidia-uvm/uvm_pmm_sysmem.h @@ -181,6 +181,9 @@ size_t uvm_pmm_sysmem_mappings_dma_to_virt(uvm_pmm_sysmem_mappings_t *sysmem_map #if UVM_CPU_CHUNK_SIZES == PAGE_SIZE #define UVM_CPU_CHUNK_SIZE_IS_PAGE_SIZE() 1 typedef struct page uvm_cpu_chunk_t; + +#define UVM_CPU_CHUNK_PAGE_INDEX(chunk, page_index) (page_index) + #else #define UVM_CPU_CHUNK_SIZE_IS_PAGE_SIZE() 0 typedef struct uvm_cpu_chunk_struct uvm_cpu_chunk_t; @@ -224,13 +227,10 @@ struct uvm_cpu_chunk_struct // parent. nv_kref_t refcount; - // Size of the chunk at the time of its creation. - // For chunks, which are the result of a split, this - // value will be the size of the chunk prior to the - // split. - // For chunks resulting from page allocations (physical), + // Size of the chunk. + // For chunks resulting from page allocations (physical chunks), // this value is the size of the physical allocation. - size_t log2_phys_size : order_base_2(UVM_CHUNK_SIZE_MASK_SIZE); + size_t log2_size : order_base_2(UVM_CHUNK_SIZE_MASK_SIZE); struct { // Per-GPU array of DMA mapping addresses for the chunk. @@ -252,6 +252,8 @@ struct uvm_cpu_chunk_struct // for logical chunks this will be NULL; unsigned long *dirty_bitmap; }; + +#define UVM_CPU_CHUNK_PAGE_INDEX(chunk, page_index) (chunk->region.first) #endif // UVM_CPU_CHUNK_SIZES == PAGE_SIZE // Return the set of allowed CPU chunk allocation sizes. @@ -302,22 +304,6 @@ void uvm_cpu_chunk_remove_from_block(uvm_va_block_t *va_block, uvm_cpu_chunk_t * // NULL is returned. uvm_cpu_chunk_t *uvm_cpu_chunk_get_chunk_for_page(uvm_va_block_t *block, uvm_page_index_t page_index); -// Return the physical size of the CPU chunk. -// The physical size of the CPU chunk is the size of the physical CPU -// memory backing the CPU chunk. It is set at CPU chunk allocation time -static uvm_chunk_size_t uvm_cpu_chunk_get_phys_size(uvm_cpu_chunk_t *chunk) -{ -#if UVM_CPU_CHUNK_SIZE_IS_PAGE_SIZE() - return (uvm_chunk_size_t)PAGE_SIZE; -#else - return ((uvm_chunk_size_t)1) << chunk->log2_phys_size; -#endif -} - -// Return the size of the CPU chunk. While the physical size of the CPU -// chunk reflects the size of the physical memory backing the chunk, this -// size is the effective size of the chunk and changes as result of CPU -// chunk splits. uvm_chunk_size_t uvm_cpu_chunk_get_size(uvm_cpu_chunk_t *chunk); // Return the number of base system pages covered by the CPU chunk. @@ -370,35 +356,27 @@ NvU64 uvm_cpu_chunk_get_gpu_mapping_addr(uvm_va_block_t *block, // new_size has to be one of the supported CPU chunk allocation sizes and has to // be smaller than the current size of chunk. // -// On success, NV_OK is returned. All new chunks will have chunk as parent and -// chunk's size will have been updated to new_size. -// -// Note that due to the way CPU chunks are managed and split, the number of -// newly created chunks will be (size_of(chunk) / new_size) - 1. -// -// On failure NV_ERR_NO_MEMORY will be returned. chunk's size will not be -// modified. -NV_STATUS uvm_cpu_chunk_split(uvm_va_block_t *va_block, uvm_cpu_chunk_t *chunk, uvm_chunk_size_t new_size); +// On success, NV_OK is returned. On failure NV_ERR_NO_MEMORY will be returned. +NV_STATUS uvm_cpu_chunk_split(uvm_va_block_t *va_block, + uvm_cpu_chunk_t *chunk, + uvm_chunk_size_t new_size, + uvm_page_index_t page_index, + uvm_cpu_chunk_t **new_chunks); -// Merge chunk's parent to the highest possible CPU chunk size fully contained -// within the parent's owning VA block. +// Merge chunks to merge_size. // -// The size to which chunks are merged is determined by finding the largest -// size from the set of allowed CPU chunk sizes that satisfies both criteria -// below: -// * The VA range of the parent chunk resulting from the merge has to be -// fully contained within the VA block. -// * The start and end VA addresses of the parent based on its physical -// size have to be aligned to the merge size. +// All input chunks must have the same parent and size. If not, +// NV_ERR_INVALID_ARGUMENT is returned. // -// It is possible that a merge cannot be done if chunk does not have a parent -// (it is a physical chunk), chunk's owning VA block is not the same as -// its parent's owning VA block, or there is no chunk size that satisfied both -// the above criteria. +// If a merge cannot be done, NV_WARN_NOTHING_TO_DO is returned. // -// Return a pointer to the merged chunk. If a merge could not be done, return -// NULL. -uvm_cpu_chunk_t *uvm_cpu_chunk_merge(uvm_va_block_t *va_block, uvm_cpu_chunk_t *chunk); +// On success, NV_OK is returned and merged_chunk is set to point to the +// merged chunk. +NV_STATUS uvm_cpu_chunk_merge(uvm_va_block_t *va_block, + uvm_cpu_chunk_t **chunks, + size_t num_merge_chunks, + uvm_chunk_size_t merge_size, + uvm_cpu_chunk_t **merged_chunk); // Mark the CPU sub-page page_index in the CPU chunk as dirty. // page_index has to be a page withing the chunk's region. @@ -414,14 +392,22 @@ bool uvm_cpu_chunk_is_dirty(uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) #else // UVM_CPU_CHUNK_SIZE_IS_PAGE_SIZE() -static NV_STATUS uvm_cpu_chunk_split(uvm_va_block_t *va_block, uvm_cpu_chunk_t *chunk, uvm_chunk_size_t new_size) +static NV_STATUS uvm_cpu_chunk_split(uvm_va_block_t *va_block, + uvm_cpu_chunk_t *chunk, + uvm_chunk_size_t new_size, + uvm_page_index_t page_index, + uvm_cpu_chunk_t **new_chunks) { return NV_OK; } -static uvm_cpu_chunk_t *uvm_cpu_chunk_merge(uvm_va_block_t *va_block, uvm_cpu_chunk_t *chunk) +static NV_STATUS uvm_cpu_chunk_merge(uvm_va_block_t *va_block, + uvm_cpu_chunk_t **chunk, + size_t num_merge_chunks, + uvm_chunk_size_t merge_size, + uvm_cpu_chunk_t **merged_chunk) { - return NULL; + return NV_WARN_NOTHING_TO_DO; } static void uvm_cpu_chunk_mark_dirty(uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) diff --git a/kernel-open/nvidia-uvm/uvm_policy.c b/kernel-open/nvidia-uvm/uvm_policy.c index 933decd9d..772c14615 100644 --- a/kernel-open/nvidia-uvm/uvm_policy.c +++ b/kernel-open/nvidia-uvm/uvm_policy.c @@ -101,7 +101,7 @@ static NV_STATUS split_as_needed(uvm_va_space_t *va_space, UVM_ASSERT(PAGE_ALIGNED(addr)); - // Look for UVM managed allocations first, then look for HMM policies. + // Look for managed allocations first, then look for HMM policies. va_range = uvm_va_range_find(va_space, addr); if (!va_range) return uvm_hmm_split_as_needed(va_space, addr, split_needed_cb, data); @@ -203,6 +203,10 @@ NV_STATUS uvm_va_block_set_preferred_location_locked(uvm_va_block_t *va_block, uvm_va_block_context_t *va_block_context) { uvm_assert_mutex_locked(&va_block->lock); + // TODO: Bug 1750144: remove this restriction when HMM handles setting + // the preferred location semantics instead of just recording the policy. + UVM_ASSERT(!uvm_va_block_is_hmm(va_block)); + UVM_ASSERT(va_block_context->policy == uvm_va_range_get_policy(va_block->va_range)); uvm_va_block_mark_cpu_dirty(va_block); @@ -432,10 +436,9 @@ NV_STATUS uvm_va_block_set_accessed_by(uvm_va_block_t *va_block, uvm_tracker_t local_tracker = UVM_TRACKER_INIT(); UVM_ASSERT(!uvm_va_block_is_hmm(va_block)); + UVM_ASSERT(va_block_context->policy == uvm_va_range_get_policy(va_block->va_range)); - va_block_context->policy = uvm_va_range_get_policy(va_block->va_range); - - // Read duplication takes precedence over SetAccesedBy. Do not add mappings + // Read duplication takes precedence over SetAccessedBy. Do not add mappings // if read duplication is enabled. if (uvm_va_policy_is_read_duplicate(va_block_context->policy, va_space)) return NV_OK; @@ -617,6 +620,10 @@ NV_STATUS uvm_va_block_set_read_duplication(uvm_va_block_t *va_block, NV_STATUS status; uvm_va_block_retry_t va_block_retry; + // TODO: Bug 3660922: need to implement HMM read duplication support. + UVM_ASSERT(!uvm_va_block_is_hmm(va_block)); + UVM_ASSERT(va_block_context->policy == uvm_va_range_get_policy(va_block->va_range)); + status = UVM_VA_BLOCK_LOCK_RETRY(va_block, &va_block_retry, va_block_set_read_duplication_locked(va_block, &va_block_retry, @@ -714,6 +721,9 @@ NV_STATUS uvm_va_block_unset_read_duplication(uvm_va_block_t *va_block, NV_STATUS status = NV_OK; uvm_tracker_t local_tracker = UVM_TRACKER_INIT(); + UVM_ASSERT(!uvm_va_block_is_hmm(va_block)); + UVM_ASSERT(va_block_context->policy == uvm_va_range_get_policy(va_block->va_range)); + // Restore all SetAccessedBy mappings status = UVM_VA_BLOCK_LOCK_RETRY(va_block, &va_block_retry, va_block_unset_read_duplication_locked(va_block, diff --git a/kernel-open/nvidia-uvm/uvm_populate_pageable.c b/kernel-open/nvidia-uvm/uvm_populate_pageable.c index 86511500a..17a54234a 100644 --- a/kernel-open/nvidia-uvm/uvm_populate_pageable.c +++ b/kernel-open/nvidia-uvm/uvm_populate_pageable.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2018-2021 NVIDIA Corporation + Copyright (c) 2018-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -54,7 +54,7 @@ NV_STATUS uvm_populate_pageable_vma(struct vm_area_struct *vma, { unsigned long vma_num_pages; unsigned long outer = start + length; - const bool is_writable = is_write_populate(vma, populate_permissions); + unsigned int gup_flags = is_write_populate(vma, populate_permissions) ? FOLL_WRITE : 0; struct mm_struct *mm = vma->vm_mm; unsigned long vm_flags = vma->vm_flags; bool uvm_managed_vma; @@ -97,7 +97,10 @@ NV_STATUS uvm_populate_pageable_vma(struct vm_area_struct *vma, if (uvm_managed_vma) uvm_record_unlock_mmap_lock_read(mm); - ret = NV_GET_USER_PAGES_REMOTE(NULL, mm, start, vma_num_pages, is_writable, 0, pages, NULL); + if (touch) + ret = NV_PIN_USER_PAGES_REMOTE(mm, start, vma_num_pages, gup_flags, pages, NULL, NULL); + else + ret = NV_GET_USER_PAGES_REMOTE(mm, start, vma_num_pages, gup_flags, pages, NULL, NULL); if (uvm_managed_vma) uvm_record_lock_mmap_lock_read(mm); @@ -114,7 +117,7 @@ NV_STATUS uvm_populate_pageable_vma(struct vm_area_struct *vma, for (i = 0; i < ret; i++) { UVM_ASSERT(pages[i]); - put_page(pages[i]); + NV_UNPIN_USER_PAGE(pages[i]); } } @@ -127,7 +130,7 @@ NV_STATUS uvm_populate_pageable_vma(struct vm_area_struct *vma, for (i = 0; i < vma_num_pages; i++) { uvm_touch_page(pages[i]); - put_page(pages[i]); + NV_UNPIN_USER_PAGE(pages[i]); } } diff --git a/kernel-open/nvidia-uvm/uvm_procfs.c b/kernel-open/nvidia-uvm/uvm_procfs.c index b95866fd6..58c4be040 100644 --- a/kernel-open/nvidia-uvm/uvm_procfs.c +++ b/kernel-open/nvidia-uvm/uvm_procfs.c @@ -68,31 +68,7 @@ NV_STATUS uvm_procfs_init() void uvm_procfs_exit() { - uvm_procfs_destroy_entry(uvm_proc_dir); -} - -// TODO: Bug 1767237: Copied from nv-procfs.c. Refactor it out to -// nv-procfs-common.c. -static void procfs_destroy_entry_with_root(struct proc_dir_entry *entry, struct proc_dir_entry *delimiter) -{ -#if defined(NV_PROC_REMOVE_PRESENT) - proc_remove(entry); -#else - while (entry) { - struct proc_dir_entry *next = entry->next; - if (entry->subdir) - procfs_destroy_entry_with_root(entry->subdir, delimiter); - remove_proc_entry(entry->name, entry->parent); - if (entry == delimiter) - break; - entry = next; - } -#endif -} - -void uvm_procfs_destroy_entry(struct proc_dir_entry *entry) -{ - procfs_destroy_entry_with_root(entry, entry); + proc_remove(uvm_proc_dir); } struct proc_dir_entry *uvm_procfs_get_gpu_base_dir() diff --git a/kernel-open/nvidia-uvm/uvm_procfs.h b/kernel-open/nvidia-uvm/uvm_procfs.h index 0521b62c1..c10c9d034 100644 --- a/kernel-open/nvidia-uvm/uvm_procfs.h +++ b/kernel-open/nvidia-uvm/uvm_procfs.h @@ -53,8 +53,6 @@ static bool uvm_procfs_is_debug_enabled(void) struct proc_dir_entry *uvm_procfs_get_gpu_base_dir(void); struct proc_dir_entry *uvm_procfs_get_cpu_base_dir(void); -void uvm_procfs_destroy_entry(struct proc_dir_entry *entry); - int uvm_procfs_open_callback(void); void uvm_procfs_close_callback(void); diff --git a/kernel-open/nvidia-uvm/uvm_pushbuffer.c b/kernel-open/nvidia-uvm/uvm_pushbuffer.c index c48a3d6aa..94685cfe0 100644 --- a/kernel-open/nvidia-uvm/uvm_pushbuffer.c +++ b/kernel-open/nvidia-uvm/uvm_pushbuffer.c @@ -121,7 +121,7 @@ NV_STATUS uvm_pushbuffer_create(uvm_channel_manager_t *channel_manager, uvm_push goto error; // Verify the GPU can access the pushbuffer. - UVM_ASSERT(uvm_pushbuffer_get_gpu_va_base(pushbuffer) + UVM_PUSHBUFFER_SIZE < gpu->parent->max_host_va); + UVM_ASSERT((uvm_pushbuffer_get_gpu_va_base(pushbuffer) + UVM_PUSHBUFFER_SIZE - 1) < gpu->parent->max_host_va); bitmap_fill(pushbuffer->idle_chunks, UVM_PUSHBUFFER_CHUNKS); bitmap_fill(pushbuffer->available_chunks, UVM_PUSHBUFFER_CHUNKS); @@ -372,7 +372,7 @@ void uvm_pushbuffer_destroy(uvm_pushbuffer_t *pushbuffer) if (pushbuffer == NULL) return; - uvm_procfs_destroy_entry(pushbuffer->procfs.info_file); + proc_remove(pushbuffer->procfs.info_file); uvm_rm_mem_free(pushbuffer->memory); uvm_kvfree(pushbuffer); @@ -448,7 +448,7 @@ void uvm_pushbuffer_end_push(uvm_pushbuffer_t *pushbuffer, uvm_push_t *push, uvm { uvm_pushbuffer_chunk_t *chunk = gpfifo_to_chunk(pushbuffer, gpfifo); - uvm_assert_spinlock_locked(&push->channel->pool->lock); + uvm_channel_pool_assert_locked(push->channel->pool); uvm_spin_lock(&pushbuffer->lock); diff --git a/kernel-open/nvidia-uvm/uvm_range_tree.c b/kernel-open/nvidia-uvm/uvm_range_tree.c index 12f9a90f1..eb68eaa9d 100644 --- a/kernel-open/nvidia-uvm/uvm_range_tree.c +++ b/kernel-open/nvidia-uvm/uvm_range_tree.c @@ -166,30 +166,6 @@ void uvm_range_tree_shrink_node(uvm_range_tree_t *tree, uvm_range_tree_node_t *n node->end = new_end; } -void uvm_range_tree_adjust_interval(uvm_range_tree_t *tree, - NvU64 addr, - NvU64 *startp, - NvU64 *endp) -{ - uvm_range_tree_node_t *node; - NvU64 start = *startp; - NvU64 end = *endp; - - uvm_range_tree_for_each_in(node, tree, start, end) { - if (node->start > addr) { - end = node->start - 1; - break; - } - else if (node->end < addr) - start = node->end + 1; - else - UVM_ASSERT_MSG(0, "Found node at address 0x%llx\n", addr); - } - - *startp = start; - *endp = end; -} - void uvm_range_tree_split(uvm_range_tree_t *tree, uvm_range_tree_node_t *existing, uvm_range_tree_node_t *new) @@ -261,3 +237,55 @@ uvm_range_tree_node_t *uvm_range_tree_iter_first(uvm_range_tree_t *tree, NvU64 s return NULL; } + +NV_STATUS uvm_range_tree_find_hole(uvm_range_tree_t *tree, NvU64 addr, NvU64 *start, NvU64 *end) +{ + uvm_range_tree_node_t *node; + + // Find the first node on or after addr, if any + node = uvm_range_tree_iter_first(tree, addr, ULLONG_MAX); + if (node) { + if (node->start <= addr) + return NV_ERR_UVM_ADDRESS_IN_USE; + + // node->start can't be 0, otherwise it would contain addr + if (end) + *end = node->start - 1; + + node = uvm_range_tree_prev(tree, node); + } + else { + // All nodes in the tree must come before addr, if any exist + node = uvm_range_tree_last(tree); + if (end) + *end = ULLONG_MAX; + } + + if (start) { + if (node) + *start = node->end + 1; + else + *start = 0; + } + + return NV_OK; +} + +NV_STATUS uvm_range_tree_find_hole_in(uvm_range_tree_t *tree, NvU64 addr, NvU64 *start, NvU64 *end) +{ + NvU64 temp_start, temp_end; + NV_STATUS status; + + UVM_ASSERT(start); + UVM_ASSERT(end); + UVM_ASSERT(*start <= addr); + UVM_ASSERT(*end >= addr); + + status = uvm_range_tree_find_hole(tree, addr, &temp_start, &temp_end); + if (status == NV_OK) { + *start = max(temp_start, *start); + *end = min(temp_end, *end); + } + + return status; +} diff --git a/kernel-open/nvidia-uvm/uvm_range_tree.h b/kernel-open/nvidia-uvm/uvm_range_tree.h index fca7bc581..ff6b38571 100644 --- a/kernel-open/nvidia-uvm/uvm_range_tree.h +++ b/kernel-open/nvidia-uvm/uvm_range_tree.h @@ -73,11 +73,6 @@ static void uvm_range_tree_remove(uvm_range_tree_t *tree, uvm_range_tree_node_t // lesser or equal to node->end. void uvm_range_tree_shrink_node(uvm_range_tree_t *tree, uvm_range_tree_node_t *node, NvU64 new_start, NvU64 new_end); -// Adjust start and end to be the largest contiguous interval surrounding addr -// between *startp and *endp and without overlapping an existing tree node. -// This function assumes there is no node that includes addr. -void uvm_range_tree_adjust_interval(uvm_range_tree_t *tree, NvU64 addr, NvU64 *startp, NvU64 *endp); - // Splits an existing node into two pieces, with the new node always after the // existing node. The caller must set new->start before calling this function. // existing should not be modified by the caller. On return, existing will @@ -100,6 +95,16 @@ uvm_range_tree_node_t *uvm_range_tree_merge_next(uvm_range_tree_t *tree, uvm_ran // Returns the node containing addr, if any uvm_range_tree_node_t *uvm_range_tree_find(uvm_range_tree_t *tree, NvU64 addr); +// Find the largest hole containing addr but not containing any nodes. If addr +// is contained by a node, NV_ERR_UVM_ADDRESS_IN_USE is returned. +// +// start and end may be NULL. +NV_STATUS uvm_range_tree_find_hole(uvm_range_tree_t *tree, NvU64 addr, NvU64 *start, NvU64 *end); + +// Like uvm_range_tree_find_hole, but start and end are in/out parameters that +// clamp the range. +NV_STATUS uvm_range_tree_find_hole_in(uvm_range_tree_t *tree, NvU64 addr, NvU64 *start, NvU64 *end); + // Returns the prev/next node in address order, or NULL if none exists static uvm_range_tree_node_t *uvm_range_tree_prev(uvm_range_tree_t *tree, uvm_range_tree_node_t *node) { @@ -118,17 +123,6 @@ static uvm_range_tree_node_t *uvm_range_tree_next(uvm_range_tree_t *tree, uvm_ra // Returns the first node in the range [start, end], if any uvm_range_tree_node_t *uvm_range_tree_iter_first(uvm_range_tree_t *tree, NvU64 start, NvU64 end); -// Return true if the range tree is empty. -static bool uvm_range_tree_empty(uvm_range_tree_t *tree) -{ - return list_empty(&tree->head); -} - -static NvU64 uvm_range_tree_node_size(uvm_range_tree_node_t *node) -{ - return node->end - node->start + 1; -} - // Returns the node following the provided node in address order, if that node's // start <= the provided end. static uvm_range_tree_node_t *uvm_range_tree_iter_next(uvm_range_tree_t *tree, uvm_range_tree_node_t *node, NvU64 end) @@ -139,6 +133,25 @@ static uvm_range_tree_node_t *uvm_range_tree_iter_next(uvm_range_tree_t *tree, u return NULL; } +// Return true if the range tree is empty. +static bool uvm_range_tree_empty(uvm_range_tree_t *tree) +{ + return list_empty(&tree->head); +} + +// Return the last node in the tree, or NULL if none exists +static uvm_range_tree_node_t *uvm_range_tree_last(uvm_range_tree_t *tree) +{ + if (list_empty(&tree->head)) + return NULL; + return list_last_entry(&tree->head, uvm_range_tree_node_t, list); +} + +static NvU64 uvm_range_tree_node_size(uvm_range_tree_node_t *node) +{ + return node->end - node->start + 1; +} + #define uvm_range_tree_for_each(node, tree) list_for_each_entry((node), &(tree)->head, list) #define uvm_range_tree_for_each_safe(node, next, tree) \ diff --git a/kernel-open/nvidia-uvm/uvm_range_tree_test.c b/kernel-open/nvidia-uvm/uvm_range_tree_test.c index e4fa28146..de4f5753b 100644 --- a/kernel-open/nvidia-uvm/uvm_range_tree_test.c +++ b/kernel-open/nvidia-uvm/uvm_range_tree_test.c @@ -303,10 +303,93 @@ error: return status; } +static NV_STATUS rtt_check_between(rtt_state_t *state, uvm_range_tree_node_t *lower, uvm_range_tree_node_t *upper) +{ + bool hole_exists = true; + NvU64 hole_start = 0, hole_end = ULLONG_MAX; + NvU64 test_start, test_end; + + if (lower) { + if (lower->end == ULLONG_MAX) { + UVM_ASSERT(!upper); + hole_exists = false; + } + else { + hole_start = lower->end + 1; + } + } + + if (upper) { + if (upper->start == 0) { + UVM_ASSERT(!lower); + hole_exists = false; + } + else { + hole_end = upper->start - 1; + } + } + + if (hole_start > hole_end) + hole_exists = false; + + if (hole_exists) { + size_t i; + NvU64 hole_mid = hole_start + ((hole_end - hole_start) / 2); + NvU64 inputs[] = {hole_start, hole_mid, hole_end}; + + for (i = 0; i < ARRAY_SIZE(inputs); i++) { + TEST_CHECK_RET(uvm_range_tree_find(&state->tree, inputs[i]) == NULL); + + TEST_NV_CHECK_RET(uvm_range_tree_find_hole(&state->tree, inputs[i], &test_start, &test_end)); + TEST_CHECK_RET(test_start == hole_start); + TEST_CHECK_RET(test_end == hole_end); + + test_start = 0; + test_end = ULLONG_MAX; + TEST_NV_CHECK_RET(uvm_range_tree_find_hole_in(&state->tree, inputs[i], &test_start, &test_end)); + TEST_CHECK_RET(test_start == hole_start); + TEST_CHECK_RET(test_end == hole_end); + + test_start = hole_start; + test_end = inputs[i]; + TEST_NV_CHECK_RET(uvm_range_tree_find_hole_in(&state->tree, inputs[i], &test_start, &test_end)); + TEST_CHECK_RET(test_start == hole_start); + TEST_CHECK_RET(test_end == inputs[i]); + + test_start = inputs[i]; + test_end = hole_end; + TEST_NV_CHECK_RET(uvm_range_tree_find_hole_in(&state->tree, inputs[i], &test_start, &test_end)); + TEST_CHECK_RET(test_start == inputs[i]); + TEST_CHECK_RET(test_end == hole_end); + } + } + else { + test_start = 0; + test_end = ULLONG_MAX; + + if (lower) { + MEM_NV_CHECK_RET(uvm_range_tree_find_hole(&state->tree, lower->end, NULL, NULL), + NV_ERR_UVM_ADDRESS_IN_USE); + MEM_NV_CHECK_RET(uvm_range_tree_find_hole_in(&state->tree, lower->end, &test_start, &test_end), + NV_ERR_UVM_ADDRESS_IN_USE); + } + + if (upper) { + MEM_NV_CHECK_RET(uvm_range_tree_find_hole(&state->tree, upper->start, NULL, NULL), + NV_ERR_UVM_ADDRESS_IN_USE); + MEM_NV_CHECK_RET(uvm_range_tree_find_hole_in(&state->tree, upper->start, &test_start, &test_end), + NV_ERR_UVM_ADDRESS_IN_USE); + } + } + + return NV_OK; +} + static NV_STATUS rtt_check_node(rtt_state_t *state, uvm_range_tree_node_t *node) { uvm_range_tree_node_t *temp, *prev, *next; NvU64 start, mid, end; + NvU64 hole_start = 0, hole_end = ULLONG_MAX; start = node->start; end = node->end; @@ -320,6 +403,18 @@ static NV_STATUS rtt_check_node(rtt_state_t *state, uvm_range_tree_node_t *node) TEST_CHECK_RET(uvm_range_tree_find(&state->tree, start) == node); TEST_CHECK_RET(uvm_range_tree_find(&state->tree, mid) == node); TEST_CHECK_RET(uvm_range_tree_find(&state->tree, end) == node); + + MEM_NV_CHECK_RET(uvm_range_tree_find_hole(&state->tree, start, NULL, NULL), NV_ERR_UVM_ADDRESS_IN_USE); + MEM_NV_CHECK_RET(uvm_range_tree_find_hole(&state->tree, mid, NULL, NULL), NV_ERR_UVM_ADDRESS_IN_USE); + MEM_NV_CHECK_RET(uvm_range_tree_find_hole(&state->tree, end, NULL, NULL), NV_ERR_UVM_ADDRESS_IN_USE); + + MEM_NV_CHECK_RET(uvm_range_tree_find_hole_in(&state->tree, start, &hole_start, &hole_end), + NV_ERR_UVM_ADDRESS_IN_USE); + MEM_NV_CHECK_RET(uvm_range_tree_find_hole_in(&state->tree, mid, &hole_start, &hole_end), + NV_ERR_UVM_ADDRESS_IN_USE); + MEM_NV_CHECK_RET(uvm_range_tree_find_hole_in(&state->tree, end, &hole_start, &hole_end), + NV_ERR_UVM_ADDRESS_IN_USE); + TEST_CHECK_RET(uvm_range_tree_node_size(node) == end - start + 1); if (end < ULLONG_MAX) @@ -327,6 +422,8 @@ static NV_STATUS rtt_check_node(rtt_state_t *state, uvm_range_tree_node_t *node) uvm_range_tree_for_each_in(temp, &state->tree, start, end) TEST_CHECK_RET(temp == node); + uvm_range_tree_for_each_in_safe(temp, next, &state->tree, start, end) + TEST_CHECK_RET(temp == node); prev = uvm_range_tree_prev(&state->tree, node); if (prev) { @@ -341,11 +438,16 @@ static NV_STATUS rtt_check_node(rtt_state_t *state, uvm_range_tree_node_t *node) if (next) { TEST_CHECK_RET(node->end < next->start); TEST_CHECK_RET(uvm_range_tree_prev(&state->tree, next) == node); + TEST_CHECK_RET(uvm_range_tree_last(&state->tree) != node); } else { TEST_CHECK_RET(uvm_range_tree_iter_next(&state->tree, node, ULLONG_MAX) == NULL); + TEST_CHECK_RET(uvm_range_tree_last(&state->tree) == node); } + TEST_NV_CHECK_RET(rtt_check_between(state, prev, node)); + TEST_NV_CHECK_RET(rtt_check_between(state, node, next)); + return NV_OK; } @@ -362,13 +464,17 @@ static NV_STATUS rtt_check_iterator_all(rtt_state_t *state) TEST_CHECK_RET(prev->end < node->start); TEST_CHECK_RET(uvm_range_tree_prev(&state->tree, node) == prev); + TEST_NV_CHECK_RET(rtt_check_between(state, prev, node)); + ++iter_count; prev = node; expected = uvm_range_tree_next(&state->tree, node); } - TEST_CHECK_RET(expected == NULL); + TEST_CHECK_RET(expected == NULL); + TEST_CHECK_RET(uvm_range_tree_last(&state->tree) == prev); TEST_CHECK_RET(iter_count == state->count); + TEST_NV_CHECK_RET(rtt_check_between(state, prev, NULL)); iter_count = 0; expected = NULL; @@ -381,13 +487,17 @@ static NV_STATUS rtt_check_iterator_all(rtt_state_t *state) TEST_CHECK_RET(prev->end < node->start); TEST_CHECK_RET(uvm_range_tree_prev(&state->tree, node) == prev); + // Skip rtt_check_between since it was done in the loop above + ++iter_count; prev = node; expected = uvm_range_tree_next(&state->tree, node); } - TEST_CHECK_RET(expected == NULL); + TEST_CHECK_RET(expected == NULL); + TEST_CHECK_RET(uvm_range_tree_last(&state->tree) == prev); TEST_CHECK_RET(iter_count == state->count); + return NV_OK; } @@ -424,20 +534,32 @@ static NV_STATUS rtt_range_add_check(rtt_state_t *state, rtt_range_t *range) } } - status = rtt_range_add(state, range, &node); - + // Verify tree state if (overlap) { - // Verify failure - MEM_NV_CHECK_RET(status, NV_ERR_UVM_ADDRESS_IN_USE); - - // The tree said there's already a range there. Check whether its - // internal state is consistent. node = uvm_range_tree_iter_first(&state->tree, range->start, range->end); TEST_CHECK_RET(node); TEST_CHECK_RET(rtt_range_overlaps_node(node, range)); } else { - // Verify success + NvU64 hole_start, hole_end; + + TEST_NV_CHECK_RET(uvm_range_tree_find_hole(&state->tree, range->start, &hole_start, &hole_end)); + TEST_CHECK_RET(hole_start <= range->start); + TEST_CHECK_RET(hole_end >= range->end); + + hole_start = range->start; + hole_end = range->end; + TEST_NV_CHECK_RET(uvm_range_tree_find_hole_in(&state->tree, range->start, &hole_start, &hole_end)); + TEST_CHECK_RET(hole_start == range->start); + TEST_CHECK_RET(hole_end == range->end); + } + + status = rtt_range_add(state, range, &node); + + if (overlap) { + MEM_NV_CHECK_RET(status, NV_ERR_UVM_ADDRESS_IN_USE); + } + else { MEM_NV_CHECK_RET(status, NV_OK); status = rtt_check_node(state, node); } @@ -450,6 +572,7 @@ static NV_STATUS rtt_index_remove_check(rtt_state_t *state, size_t index) { uvm_range_tree_node_t *node, *prev, *next; NvU64 start, end; + NvU64 hole_start, hole_end; NV_STATUS status; TEST_CHECK_RET(index < state->count); @@ -472,12 +595,35 @@ static NV_STATUS rtt_index_remove_check(rtt_state_t *state, size_t index) TEST_CHECK_RET(uvm_range_tree_find(&state->tree, start) == NULL); TEST_CHECK_RET(uvm_range_tree_find(&state->tree, end) == NULL); TEST_CHECK_RET(uvm_range_tree_iter_first(&state->tree, start, end) == NULL); - if (prev) + + hole_start = start; + hole_end = end; + TEST_NV_CHECK_RET(uvm_range_tree_find_hole_in(&state->tree, start, &hole_start, &hole_end)); + TEST_CHECK_RET(hole_start == start); + TEST_CHECK_RET(hole_end == end); + + TEST_NV_CHECK_RET(uvm_range_tree_find_hole(&state->tree, start, &hole_start, &hole_end)); + TEST_CHECK_RET(hole_start <= start); + TEST_CHECK_RET(hole_end >= end); + + if (prev) { TEST_CHECK_RET(uvm_range_tree_next(&state->tree, prev) == next); - if (next) + TEST_CHECK_RET(hole_start == prev->end + 1); + } + + if (next) { TEST_CHECK_RET(uvm_range_tree_prev(&state->tree, next) == prev); + TEST_CHECK_RET(hole_end == next->start - 1); + } + else { + TEST_CHECK_RET(uvm_range_tree_last(&state->tree) == prev); + } + if (!prev && !next) { TEST_CHECK_RET(uvm_range_tree_empty(&state->tree)); + TEST_CHECK_RET(uvm_range_tree_last(&state->tree) == NULL); + TEST_CHECK_RET(hole_start == 0); + TEST_CHECK_RET(hole_end == ULLONG_MAX); TEST_CHECK_RET(state->count == 0); } else { @@ -749,10 +895,11 @@ static NV_STATUS rtt_index_merge_check_next_val(rtt_state_t *state, NvU64 addr) static NV_STATUS rtt_directed(rtt_state_t *state) { - uvm_range_tree_node_t *node; + uvm_range_tree_node_t *node, *next; // Empty tree TEST_CHECK_RET(uvm_range_tree_empty(&state->tree)); + TEST_CHECK_RET(uvm_range_tree_last(&state->tree) == NULL); TEST_CHECK_RET(uvm_range_tree_find(&state->tree, 0) == NULL); TEST_CHECK_RET(uvm_range_tree_find(&state->tree, ULLONG_MAX) == NULL); uvm_range_tree_for_each(node, &state->tree) @@ -763,6 +910,13 @@ static NV_STATUS rtt_directed(rtt_state_t *state) TEST_CHECK_RET(0); uvm_range_tree_for_each_in(node, &state->tree, ULLONG_MAX, ULLONG_MAX) TEST_CHECK_RET(0); + uvm_range_tree_for_each_in_safe(node, next, &state->tree, 0, 0) + TEST_CHECK_RET(0); + uvm_range_tree_for_each_in_safe(node, next, &state->tree, 0, ULLONG_MAX) + TEST_CHECK_RET(0); + uvm_range_tree_for_each_in_safe(node, next, &state->tree, ULLONG_MAX, ULLONG_MAX) + TEST_CHECK_RET(0); + TEST_NV_CHECK_RET(rtt_check_between(state, NULL, NULL)); // Consume entire range MEM_NV_CHECK_RET(rtt_range_add_check_val(state, 0, ULLONG_MAX), NV_OK); @@ -1038,8 +1192,8 @@ static NV_STATUS rtt_batch_remove(rtt_state_t *state, UVM_TEST_RANGE_TREE_RANDOM return NV_OK; } -// Attempts to shrink a randomly-selected range in the tree. On selecting a range -// of size 1, the attempt is repeated with another range up to the +// Attempts to shrink a randomly-selected range in the tree. On selecting a +// range of size 1, the attempt is repeated with another range up to the // params->max_attempts threshold. static NV_STATUS rtt_rand_shrink(rtt_state_t *state, UVM_TEST_RANGE_TREE_RANDOM_PARAMS *params) { @@ -1151,11 +1305,12 @@ static NV_STATUS rtt_rand_split(rtt_state_t *state, UVM_TEST_RANGE_TREE_RANDOM_P return NV_OK; } -// Attempts to merge a randomly-selected range in the tree in a randomly-selected -// direction (next or prev). On selecting a range with a non-adjacent neighbor, -// the attempt is repeated with another range up to the params->max_attempts -// threshold. On reaching the attempt threshold the RNG probabilities are -// adjusted to prefer split operations and NV_ERR_BUSY_RETRY is returned. +// Attempts to merge a randomly-selected range in the tree in a randomly- +// selected direction (next or prev). On selecting a range with a non-adjacent +// neighbor, the attempt is repeated with another range up to the +// params->max_attempts threshold. On reaching the attempt threshold the RNG +// probabilities are adjusted to prefer split operations and NV_ERR_BUSY_RETRY +// is returned. static NV_STATUS rtt_rand_merge(rtt_state_t *state, UVM_TEST_RANGE_TREE_RANDOM_PARAMS *params) { uvm_range_tree_node_t *node; @@ -1236,20 +1391,113 @@ static NV_STATUS rtt_rand_collision_check(rtt_state_t *state, NvU64 max_end) // in that range in order. static NV_STATUS rtt_rand_iterator_check(rtt_state_t *state, NvU64 max_end) { - uvm_range_tree_node_t *node, *prev = NULL; + uvm_range_tree_node_t *node; + uvm_range_tree_node_t *prev = NULL, *first = NULL, *last = NULL, *next = NULL; size_t i, target_count = 0, iter_count = 0; + NvU64 hole_start, hole_end, test_start, test_end; rtt_range_t range; // Generate the range to check rtt_get_rand_range(&state->rng, max_end, &range); // Phase 1: Iterate through the unordered list, counting how many nodes we - // ought to see from the tree iterator. - for (i = 0; i < state->count; i++) - target_count += rtt_range_overlaps_node(state->nodes[i], &range); + // ought to see from the tree iterator and finding the boundary nodes. + for (i = 0; i < state->count; i++) { + node = state->nodes[i]; + + if (rtt_range_overlaps_node(node, &range)) { + ++target_count; + + // first is the lowest node with any overlap + if (!first || first->start > node->start) + first = node; + + // last is the highest node with any overlap + if (!last || last->end < node->end) + last = node; + } + else { + // prev is the highest node with end < range.start + if (node->end < range.start && (!prev || node->end > prev->end)) + prev = node; + + // next is the lowest node with start > range.end + if (node->start > range.end && (!next || node->start < next->start)) + next = node; + } + } + + // Phase 2: Use the tree iterators + + // The holes between the nodes will be checked within the iterator loop. + // Here we check the holes at the start and end of the range, if any. + if (first) { + if (range.start < first->start) { + // Check hole at range.start + hole_start = prev ? prev->end + 1 : 0; + hole_end = first->start - 1; + TEST_NV_CHECK_RET(uvm_range_tree_find_hole(&state->tree, range.start, &test_start, &test_end)); + TEST_CHECK_RET(test_start == hole_start); + TEST_CHECK_RET(test_end == hole_end); + + test_start = range.start; + test_end = ULLONG_MAX; + TEST_NV_CHECK_RET(uvm_range_tree_find_hole_in(&state->tree, range.start, &test_start, &test_end)); + TEST_CHECK_RET(test_start == range.start); + TEST_CHECK_RET(test_end == hole_end); + } + + // Else, no hole at start + } + else { + // No nodes intersect the range + UVM_ASSERT(target_count == 0); + UVM_ASSERT(!last); + + hole_start = prev ? prev->end + 1 : 0; + hole_end = next ? next->start - 1 : ULLONG_MAX; + TEST_NV_CHECK_RET(uvm_range_tree_find_hole(&state->tree, range.start, &test_start, &test_end)); + TEST_CHECK_RET(test_start == hole_start); + TEST_CHECK_RET(test_end == hole_end); + + test_start = range.start; + test_end = range.end; + TEST_NV_CHECK_RET(uvm_range_tree_find_hole_in(&state->tree, range.start, &test_start, &test_end)); + TEST_CHECK_RET(test_start == range.start); + TEST_CHECK_RET(test_end == range.end); + } + + if (last && range.end > last->end) { + // Check hole at range.end + hole_start = last->end + 1; + hole_end = next ? next->start - 1 : ULLONG_MAX; + TEST_NV_CHECK_RET(uvm_range_tree_find_hole(&state->tree, range.end, &test_start, &test_end)); + TEST_CHECK_RET(test_start == hole_start); + TEST_CHECK_RET(test_end == hole_end); + + test_start = 0; + test_end = range.end; + TEST_NV_CHECK_RET(uvm_range_tree_find_hole_in(&state->tree, range.end, &test_start, &test_end)); + TEST_CHECK_RET(test_start == hole_start); + TEST_CHECK_RET(test_end == range.end); + } - // Phase 2: Use the tree iterator uvm_range_tree_for_each_in(node, &state->tree, range.start, range.end) { + TEST_CHECK_RET(rtt_range_overlaps_node(node, &range)); + if (prev) { + TEST_CHECK_RET(prev->end < node->start); + TEST_NV_CHECK_RET(rtt_check_between(state, prev, node)); + } + + ++iter_count; + prev = node; + } + + TEST_CHECK_RET(iter_count == target_count); + + prev = NULL; + iter_count = 0; + uvm_range_tree_for_each_in_safe(node, next, &state->tree, range.start, range.end) { TEST_CHECK_RET(rtt_range_overlaps_node(node, &range)); if (prev) TEST_CHECK_RET(prev->end < node->start); @@ -1277,9 +1525,9 @@ static rtt_op_t rtt_get_rand_op(rtt_state_t *state, UVM_TEST_RANGE_TREE_RANDOM_P if (state->count == 1 && state->count == params->max_ranges) return RTT_OP_REMOVE; - // r_group selects between the two groups of operations, either {add/remove/shrink} - // or {merge/split}. r_sub selects the sub operation within that group based - // on the current probability settings. + // r_group selects between the two groups of operations, either {add/remove/ + // shrink} or {merge/split}. r_sub selects the sub operation within that + // group based on the current probability settings. r_group = uvm_test_rng_range_32(&state->rng, 1, 100); r_sub = uvm_test_rng_range_32(&state->rng, 1, 100); @@ -1287,7 +1535,9 @@ static rtt_op_t rtt_get_rand_op(rtt_state_t *state, UVM_TEST_RANGE_TREE_RANDOM_P if (r_group <= params->add_remove_shrink_group_probability) { if (r_sub <= state->shrink_probability) return RTT_OP_SHRINK; - // After giving shrink a chance, redo the randomization for add/remove. + + // After giving shrink a chance, redo the randomization for add/ + // remove. r_sub = uvm_test_rng_range_32(&state->rng, 1, 100); if (r_sub <= state->add_chance) diff --git a/kernel-open/nvidia-uvm/uvm_rm_mem_test.c b/kernel-open/nvidia-uvm/uvm_rm_mem_test.c index 3356be4a8..c436fe2d9 100644 --- a/kernel-open/nvidia-uvm/uvm_rm_mem_test.c +++ b/kernel-open/nvidia-uvm/uvm_rm_mem_test.c @@ -60,10 +60,22 @@ static NV_STATUS map_cpu(uvm_rm_mem_t *rm_mem) return NV_OK; } +static NV_STATUS check_alignment(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu, NvU64 alignment) +{ + // Alignment requirements only apply to mappings in the UVM-owned VA space + if (alignment != 0) { + bool is_proxy_va_space = false; + NvU64 gpu_va = uvm_rm_mem_get_gpu_va(rm_mem, gpu, is_proxy_va_space); + + TEST_CHECK_RET(IS_ALIGNED(gpu_va, alignment)); + } + + return NV_OK; +} + static NV_STATUS map_gpu_owner(uvm_rm_mem_t *rm_mem, NvU64 alignment) { uvm_gpu_t *gpu = rm_mem->gpu_owner; - NvU64 gpu_va; // The memory should have been automatically mapped in the GPU owner TEST_CHECK_RET(uvm_rm_mem_mapped_on_gpu(rm_mem, gpu)); @@ -73,9 +85,7 @@ static NV_STATUS map_gpu_owner(uvm_rm_mem_t *rm_mem, NvU64 alignment) // located in vidmem. TEST_CHECK_RET(uvm_rm_mem_mapped_on_gpu_proxy(rm_mem, gpu) == uvm_gpu_uses_proxy_channel_pool(gpu)); - gpu_va = uvm_rm_mem_get_gpu_va(rm_mem, gpu, uvm_rm_mem_mapped_on_gpu_proxy(rm_mem, gpu)); - if (alignment) - TEST_CHECK_RET(IS_ALIGNED(gpu_va, alignment)); + TEST_NV_CHECK_RET(check_alignment(rm_mem, gpu, alignment)); // Explicitly mapping or unmapping to the GPU that owns the allocation is // not allowed, so the testing related to GPU owners is simpler than that of @@ -87,7 +97,6 @@ static NV_STATUS map_other_gpus(uvm_rm_mem_t *rm_mem, uvm_va_space_t *va_space, { uvm_gpu_t *gpu_owner = rm_mem->gpu_owner; uvm_gpu_t *gpu; - NvU64 gpu_va; for_each_va_space_gpu(gpu, va_space) { if (gpu == gpu_owner) @@ -119,9 +128,7 @@ static NV_STATUS map_other_gpus(uvm_rm_mem_t *rm_mem, uvm_va_space_t *va_space, TEST_CHECK_RET(uvm_rm_mem_mapped_on_gpu_proxy(rm_mem, gpu) == uvm_gpu_uses_proxy_channel_pool(gpu)); - gpu_va = uvm_rm_mem_get_gpu_va(rm_mem, gpu, uvm_rm_mem_mapped_on_gpu_proxy(rm_mem, gpu)); - if (alignment) - TEST_CHECK_RET(IS_ALIGNED(gpu_va, alignment)); + TEST_NV_CHECK_RET(check_alignment(rm_mem, gpu, alignment)); } return NV_OK; diff --git a/kernel-open/nvidia-uvm/uvm_test.c b/kernel-open/nvidia-uvm/uvm_test.c index 2b71594fa..f4f8cc136 100644 --- a/kernel-open/nvidia-uvm/uvm_test.c +++ b/kernel-open/nvidia-uvm/uvm_test.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2021 NVIDIA Corporation + Copyright (c) 2015-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -247,6 +247,7 @@ long uvm_test_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_CHANNEL_STRESS, uvm_test_channel_stress); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_CE_SANITY, uvm_test_ce_sanity); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_HOST_SANITY, uvm_test_host_sanity); + UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_VA_SPACE_MM_OR_CURRENT_RETAIN, uvm_test_va_space_mm_or_current_retain); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_VA_BLOCK_INFO, uvm_test_va_block_info); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_LOCK_SANITY, uvm_test_lock_sanity); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_PERF_UTILS_SANITY, uvm_test_perf_utils_sanity); @@ -328,6 +329,8 @@ long uvm_test_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) uvm_test_va_range_inject_add_gpu_va_space_error); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_DESTROY_GPU_VA_SPACE_DELAY, uvm_test_destroy_gpu_va_space_delay); UVM_ROUTE_CMD_STACK_NO_INIT_CHECK(UVM_TEST_CGROUP_ACCOUNTING_SUPPORTED, uvm_test_cgroup_accounting_supported); + UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_HMM_INIT, uvm_test_hmm_init); + UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_SPLIT_INVALIDATE_DELAY, uvm_test_split_invalidate_delay); } return -EINVAL; diff --git a/kernel-open/nvidia-uvm/uvm_test_ioctl.h b/kernel-open/nvidia-uvm/uvm_test_ioctl.h index b127aa8f2..3da600df0 100644 --- a/kernel-open/nvidia-uvm/uvm_test_ioctl.h +++ b/kernel-open/nvidia-uvm/uvm_test_ioctl.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2021 NVidia Corporation + Copyright (c) 2015-2022 NVidia Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -23,9 +23,7 @@ #ifndef __UVM_TEST_IOCTL_H__ #define __UVM_TEST_IOCTL_H__ -#ifndef __KERNEL__ -#endif #include "uvm_types.h" #include "uvm_ioctl.h" #include "nv_uvm_types.h" @@ -151,6 +149,14 @@ typedef enum UVM_TEST_VA_RANGE_TYPE_MAX } UVM_TEST_VA_RANGE_TYPE; +typedef enum +{ + UVM_TEST_RANGE_SUBTYPE_INVALID = 0, + UVM_TEST_RANGE_SUBTYPE_UVM, + UVM_TEST_RANGE_SUBTYPE_HMM, + UVM_TEST_RANGE_SUBTYPE_MAX +} UVM_TEST_RANGE_SUBTYPE; + // Keep this in sync with uvm_read_duplication_t in uvm_va_range.h typedef enum { @@ -169,6 +175,7 @@ typedef struct NvBool is_zombie; // Out // Note: if this is a zombie, this field is meaningless. NvBool owned_by_calling_process; // Out + NvU32 subtype; // Out (UVM_TEST_RANGE_SUBTYPE) } UVM_TEST_VA_RANGE_INFO_MANAGED; #define UVM_TEST_VA_RANGE_INFO UVM_TEST_IOCTL_BASE(4) @@ -176,6 +183,10 @@ typedef struct { NvU64 lookup_address NV_ALIGN_BYTES(8); // In + // For HMM ranges va_range_start/end will contain the lookup address but not + // neccessarily the maximal range over which the returned policy applies. + // For example there could be adjacent ranges with the same policy, implying + // the returned range could be as small as a page in the worst case for HMM. NvU64 va_range_start NV_ALIGN_BYTES(8); // Out NvU64 va_range_end NV_ALIGN_BYTES(8); // Out, inclusive NvU32 read_duplication; // Out (UVM_TEST_READ_DUPLICATION_POLICY) @@ -536,12 +547,14 @@ typedef struct // If user_pages_allocation_retry_force_count is non-0 then the next count user // memory allocations under the VA block will be forced to do allocation-retry. // +// If cpu_pages_allocation_error_count is not zero, the subsequent operations +// that need to allocate CPU pages will fail with NV_ERR_NO_MEMORY for +// cpu_pages_allocation_error_count times. If cpu_pages_allocation_error_count +// is equal to ~0U, the count is infinite. +// // If eviction_failure is NV_TRUE, the next eviction attempt from the VA block // will fail with NV_ERR_NO_MEMORY. // -// If cpu_pages_allocation_error is NV_TRUE, the subsequent operations that -// need to allocate CPU pages will fail with NV_ERR_NO_MEMORY. -// // If populate_failure is NV_TRUE, a retry error will be injected after the next // successful user memory allocation under the VA block but before that // allocation is used by the block. This is similar to @@ -558,8 +571,8 @@ typedef struct NvU32 page_table_allocation_retry_force_count; // In NvU32 user_pages_allocation_retry_force_count; // In NvU32 cpu_chunk_allocation_size_mask; // In + NvU32 cpu_pages_allocation_error_count; // In NvBool eviction_error; // In - NvBool cpu_pages_allocation_error; // In NvBool populate_error; // In NV_STATUS rmStatus; // Out } UVM_TEST_VA_BLOCK_INJECT_ERROR_PARAMS; @@ -1111,10 +1124,14 @@ typedef struct // // If migrate_vma_allocation_fail_nth is greater than 0, the nth page // allocation within migrate_vma will fail. +// +// If va_block_allocation_fail_nth is greater than 0, the nth call to +// uvm_va_block_find_create() will fail with NV_ERR_NO_MEMORY. #define UVM_TEST_VA_SPACE_INJECT_ERROR UVM_TEST_IOCTL_BASE(72) typedef struct { NvU32 migrate_vma_allocation_fail_nth; // In + NvU32 va_block_allocation_fail_nth; // In NV_STATUS rmStatus; // Out } UVM_TEST_VA_SPACE_INJECT_ERROR_PARAMS; @@ -1341,6 +1358,28 @@ typedef struct NV_STATUS rmStatus; // Out } UVM_TEST_HOST_SANITY_PARAMS; +// Calls uvm_va_space_mm_or_current_retain() on a VA space, +// then releases the va_space_mm and returns. +#define UVM_TEST_VA_SPACE_MM_OR_CURRENT_RETAIN UVM_TEST_IOCTL_BASE(89) +typedef struct +{ + // User address of a flag to act as a semaphore. If non-NULL, the address + // is set to 1 after successful retain but before the sleep. + NvU64 retain_done_ptr NV_ALIGN_BYTES(8); // In + + // Approximate duration for which to sleep with the va_space_mm retained. + NvU64 sleep_us NV_ALIGN_BYTES(8); // In + + // On success, this contains the value of mm->mm_users before mmput() is + // called. + NvU64 mm_users NV_ALIGN_BYTES(8); // Out + + // NV_ERR_PAGE_TABLE_NOT_AVAIL Could not retain va_space_mm + // (uvm_va_space_mm_or_current_retain returned + // NULL) + NV_STATUS rmStatus; // Out +} UVM_TEST_VA_SPACE_MM_OR_CURRENT_RETAIN_PARAMS; + #define UVM_TEST_GET_USER_SPACE_END_ADDRESS UVM_TEST_IOCTL_BASE(90) typedef struct { @@ -1396,6 +1435,19 @@ typedef struct NV_STATUS rmStatus; // Out } UVM_TEST_CGROUP_ACCOUNTING_SUPPORTED_PARAMS; +#define UVM_TEST_HMM_INIT UVM_TEST_IOCTL_BASE(97) +typedef struct +{ + NV_STATUS rmStatus; // Out +} UVM_TEST_HMM_INIT_PARAMS; + +#define UVM_TEST_SPLIT_INVALIDATE_DELAY UVM_TEST_IOCTL_BASE(98) +typedef struct +{ + NvU64 delay_us; // In + NV_STATUS rmStatus; // Out +} UVM_TEST_SPLIT_INVALIDATE_DELAY_PARAMS; + #ifdef __cplusplus } #endif diff --git a/kernel-open/nvidia-uvm/uvm_thread_context.c b/kernel-open/nvidia-uvm/uvm_thread_context.c index 03d006d8a..5996d8abb 100644 --- a/kernel-open/nvidia-uvm/uvm_thread_context.c +++ b/kernel-open/nvidia-uvm/uvm_thread_context.c @@ -430,10 +430,12 @@ static bool thread_context_non_interrupt_add(uvm_thread_context_t *thread_contex if (thread_context->array_index == UVM_THREAD_CONTEXT_ARRAY_SIZE) { NvU64 old = atomic64_cmpxchg(&array_entry->task, 0, task); - // Task already added a different thread context. There is nothing - // to undo because the current thread context has not been inserted. - if (old == task) + // Task already added a different thread context. The current thread + // context has not been inserted but needs to be freed. + if (old == task) { + thread_context_non_interrupt_deinit(thread_context); return false; + } // Speculatively add the current thread context. if (old == 0) @@ -444,6 +446,7 @@ static bool thread_context_non_interrupt_add(uvm_thread_context_t *thread_contex // Task already added a different thread context to the array, so // undo the speculative insertion atomic64_set(&table_entry->array[thread_context->array_index].task, 0); + thread_context_non_interrupt_deinit(thread_context); return false; } @@ -474,6 +477,9 @@ static bool thread_context_non_interrupt_add(uvm_thread_context_t *thread_contex added = true; } + if (!added) + thread_context_non_interrupt_deinit(thread_context); + spin_unlock_irqrestore(&table_entry->tree_lock, flags); return added; } diff --git a/kernel-open/nvidia-uvm/uvm_tools.c b/kernel-open/nvidia-uvm/uvm_tools.c index 9363de8e8..809d41772 100644 --- a/kernel-open/nvidia-uvm/uvm_tools.c +++ b/kernel-open/nvidia-uvm/uvm_tools.c @@ -218,7 +218,7 @@ static void uvm_put_user_pages_dirty(struct page **pages, NvU64 page_count) for (i = 0; i < page_count; i++) { set_page_dirty(pages[i]); - put_page(pages[i]); + NV_UNPIN_USER_PAGE(pages[i]); } } @@ -262,7 +262,7 @@ static NV_STATUS map_user_pages(NvU64 user_va, NvU64 size, void **addr, struct p } nv_mmap_read_lock(current->mm); - ret = NV_GET_USER_PAGES(user_va, num_pages, 1, 0, *pages, vmas); + ret = NV_PIN_USER_PAGES(user_va, num_pages, FOLL_WRITE, *pages, vmas); nv_mmap_read_unlock(current->mm); if (ret != num_pages) { status = NV_ERR_INVALID_ARGUMENT; @@ -1116,6 +1116,19 @@ void uvm_tools_broadcast_access_counter(uvm_gpu_t *gpu, uvm_tools_broadcast_event(&entry); } +void uvm_tools_test_hmm_split_invalidate(uvm_va_space_t *va_space) +{ + UvmEventEntry entry; + + if (!va_space->tools.enabled) + return; + + entry.testEventData.splitInvalidate.eventType = UvmEventTypeTestHmmSplitInvalidate; + uvm_down_read(&va_space->tools.lock); + uvm_tools_record_event(va_space, &entry); + uvm_up_read(&va_space->tools.lock); +} + // This function is used as a begin marker to group all migrations within a VA // block that are performed in the same call to // block_copy_resident_pages_between. All of these are pushed to the same @@ -2101,8 +2114,7 @@ exit: uvm_global_mask_release(retained_global_gpus); - if (mm) - uvm_va_space_mm_or_current_release(va_space, mm); + uvm_va_space_mm_or_current_release(va_space, mm); uvm_kvfree(global_gpus); uvm_kvfree(retained_global_gpus); diff --git a/kernel-open/nvidia-uvm/uvm_tools.h b/kernel-open/nvidia-uvm/uvm_tools.h index 7b5a5be9e..988b10f46 100644 --- a/kernel-open/nvidia-uvm/uvm_tools.h +++ b/kernel-open/nvidia-uvm/uvm_tools.h @@ -115,6 +115,8 @@ void uvm_tools_broadcast_access_counter(uvm_gpu_t *gpu, const uvm_access_counter_buffer_entry_t *buffer_entry, bool on_managed); +void uvm_tools_test_hmm_split_invalidate(uvm_va_space_t *va_space); + // schedules completed events and then waits from the to be dispatched void uvm_tools_flush_events(void); diff --git a/kernel-open/nvidia-uvm/uvm_types.h b/kernel-open/nvidia-uvm/uvm_types.h index 088ecc89a..60d3d934c 100644 --- a/kernel-open/nvidia-uvm/uvm_types.h +++ b/kernel-open/nvidia-uvm/uvm_types.h @@ -34,9 +34,6 @@ #include "nvstatus.h" #include "nvCpuUuid.h" -#ifndef __KERNEL__ - -#endif /******************************************************************************* UVM stream types @@ -359,9 +356,10 @@ typedef enum UvmEventNumTypes, // ---- Private event types for uvm tests - UvmEventTestTypesFirst = 63, + UvmEventTestTypesFirst = 62, - UvmEventTypeTestAccessCounter = UvmEventTestTypesFirst, + UvmEventTypeTestHmmSplitInvalidate = UvmEventTestTypesFirst, + UvmEventTypeTestAccessCounter = UvmEventTestTypesFirst + 1, UvmEventTestTypesLast = UvmEventTypeTestAccessCounter, @@ -387,6 +385,7 @@ typedef enum #define UVM_EVENT_ENABLE_MAP_REMOTE ((NvU64)1 << UvmEventTypeMapRemote) #define UVM_EVENT_ENABLE_EVICTION ((NvU64)1 << UvmEventTypeEviction) #define UVM_EVENT_ENABLE_TEST_ACCESS_COUNTER ((NvU64)1 << UvmEventTypeTestAccessCounter) +#define UVM_EVENT_ENABLE_TEST_HMM_SPLIT_INVALIDATE ((NvU64)1 << UvmEventTypeTestHmmSplitInvalidate) //------------------------------------------------------------------------------ // Information associated with a memory violation event @@ -977,6 +976,11 @@ typedef struct NvU64 instancePtr; } UvmEventTestAccessCounterInfo; +typedef struct +{ + NvU8 eventType; +} UvmEventTestSplitInvalidateInfo; + //------------------------------------------------------------------------------ // Entry added in the event queue buffer when an enabled event occurs. For // compatibility with all tools ensure that this structure is 64 bit aligned. @@ -1010,6 +1014,7 @@ typedef struct NvU8 eventType; UvmEventTestAccessCounterInfo accessCounter; + UvmEventTestSplitInvalidateInfo splitInvalidate; } testEventData; }; } UvmEventEntry; diff --git a/kernel-open/nvidia-uvm/uvm_user_channel.c b/kernel-open/nvidia-uvm/uvm_user_channel.c index a6fbcefc9..937f19d7e 100644 --- a/kernel-open/nvidia-uvm/uvm_user_channel.c +++ b/kernel-open/nvidia-uvm/uvm_user_channel.c @@ -618,7 +618,7 @@ static NV_STATUS uvm_register_channel(uvm_va_space_t *va_space, uvm_va_space_up_read_rm(va_space); // The mm needs to be locked in order to remove stale HMM va_blocks. - mm = uvm_va_space_mm_retain_lock(va_space); + mm = uvm_va_space_mm_or_current_retain_lock(va_space); // We have the RM objects now so we know what the VA range layout should be. // Re-take the VA space lock in write mode to create and insert them. @@ -653,10 +653,8 @@ static NV_STATUS uvm_register_channel(uvm_va_space_t *va_space, if (status != NV_OK) goto error_under_write; - if (mm) { + if (mm) uvm_up_read_mmap_lock_out_of_order(mm); - uvm_va_space_mm_release(va_space); - } // The subsequent mappings will need to call into RM, which means we must // downgrade the VA space lock to read mode. Although we're in read mode no @@ -681,6 +679,7 @@ static NV_STATUS uvm_register_channel(uvm_va_space_t *va_space, goto error_under_read; uvm_va_space_up_read_rm(va_space); + uvm_va_space_mm_or_current_release(va_space, mm); uvm_gpu_release(gpu); return NV_OK; @@ -688,7 +687,7 @@ error_under_write: if (user_channel->gpu_va_space) uvm_user_channel_detach(user_channel, &deferred_free_list); uvm_va_space_up_write(va_space); - uvm_va_space_mm_release_unlock(va_space, mm); + uvm_va_space_mm_or_current_release_unlock(va_space, mm); uvm_deferred_free_object_list(&deferred_free_list); uvm_gpu_release(gpu); return status; @@ -714,10 +713,12 @@ error_under_read: if (user_channel->gpu_va_space) { uvm_user_channel_detach(user_channel, &deferred_free_list); uvm_va_space_up_write(va_space); + uvm_va_space_mm_or_current_release(va_space, mm); uvm_deferred_free_object_list(&deferred_free_list); } else { uvm_va_space_up_write(va_space); + uvm_va_space_mm_or_current_release(va_space, mm); } uvm_user_channel_release(user_channel); diff --git a/kernel-open/nvidia-uvm/uvm_va_block.c b/kernel-open/nvidia-uvm/uvm_va_block.c index f549b5289..fdfc1a07b 100644 --- a/kernel-open/nvidia-uvm/uvm_va_block.c +++ b/kernel-open/nvidia-uvm/uvm_va_block.c @@ -105,6 +105,36 @@ uvm_va_space_t *uvm_va_block_get_va_space(uvm_va_block_t *va_block) return va_space; } +bool uvm_va_block_check_policy_is_valid(uvm_va_block_t *va_block, + uvm_va_policy_t *policy, + uvm_va_block_region_t region) +{ + uvm_assert_mutex_locked(&va_block->lock); + + if (uvm_va_block_is_hmm(va_block)) { + uvm_va_policy_node_t *node; + + if (policy == &uvm_va_policy_default) { + // There should only be the default policy within the region. + node = uvm_va_policy_node_iter_first(va_block, + uvm_va_block_region_start(va_block, region), + uvm_va_block_region_end(va_block, region)); + UVM_ASSERT(!node); + } + else { + // The policy node should cover the region. + node = uvm_va_policy_node_from_policy(policy); + UVM_ASSERT(node->node.start <= uvm_va_block_region_start(va_block, region)); + UVM_ASSERT(node->node.end >= uvm_va_block_region_end(va_block, region)); + } + } + else { + UVM_ASSERT(policy == uvm_va_range_get_policy(va_block->va_range)); + } + + return true; +} + static NvU64 block_gpu_pte_flag_cacheable(uvm_va_block_t *block, uvm_gpu_t *gpu, uvm_processor_id_t resident_id) { uvm_va_space_t *va_space = uvm_va_block_get_va_space(block); @@ -589,7 +619,7 @@ NV_STATUS uvm_va_block_create(uvm_va_range_t *va_range, UVM_ASSERT(size <= UVM_VA_BLOCK_SIZE); if (va_range) { - // Create a UVM managed va_block. + // Create a managed va_block. UVM_ASSERT(start >= va_range->node.start); UVM_ASSERT(end <= va_range->node.end); UVM_ASSERT(va_range->type == UVM_VA_RANGE_TYPE_MANAGED); @@ -617,6 +647,7 @@ NV_STATUS uvm_va_block_create(uvm_va_range_t *va_range, block->end = end; block->va_range = va_range; uvm_tracker_init(&block->tracker); + block->prefetch_info.last_migration_proc_id = UVM_ID_INVALID; nv_kthread_q_item_init(&block->eviction_mappings_q_item, block_deferred_eviction_mappings_entry, block); @@ -636,7 +667,7 @@ static void block_gpu_unmap_phys_all_cpu_pages(uvm_va_block_t *block, uvm_gpu_t gpu_mapping_addr = uvm_cpu_chunk_get_gpu_mapping_addr(block, page_index, chunk, gpu->id); if (gpu_mapping_addr != 0) { uvm_pmm_sysmem_mappings_remove_gpu_mapping(&gpu->pmm_reverse_sysmem_mappings, gpu_mapping_addr); - uvm_gpu_unmap_cpu_pages(gpu, gpu_mapping_addr, uvm_cpu_chunk_get_size(chunk)); + uvm_gpu_unmap_cpu_pages(gpu->parent, gpu_mapping_addr, uvm_cpu_chunk_get_size(chunk)); uvm_cpu_chunk_set_gpu_mapping_addr(block, page_index, chunk, gpu->id, 0); } } @@ -657,7 +688,7 @@ static NV_STATUS block_gpu_map_phys_all_cpu_pages(uvm_va_block_t *block, uvm_gpu UVM_ASSERT_MSG(gpu_mapping_addr == 0, "GPU%u DMA address 0x%llx\n", uvm_id_value(gpu->id), gpu_mapping_addr); - status = uvm_gpu_map_cpu_pages(gpu, + status = uvm_gpu_map_cpu_pages(gpu->parent, uvm_cpu_chunk_get_cpu_page(block, chunk, page_index), chunk_size, &gpu_mapping_addr); @@ -846,7 +877,7 @@ static void block_unmap_cpu_chunk_on_gpus(uvm_va_block_t *block, uvm_cpu_chunk_t gpu = block_get_gpu(block, id); uvm_pmm_sysmem_mappings_remove_gpu_mapping(&gpu->pmm_reverse_sysmem_mappings, gpu_mapping_addr); - uvm_gpu_unmap_cpu_pages(gpu, gpu_mapping_addr, uvm_cpu_chunk_get_size(chunk)); + uvm_gpu_unmap_cpu_pages(gpu->parent, gpu_mapping_addr, uvm_cpu_chunk_get_size(chunk)); uvm_cpu_chunk_set_gpu_mapping_addr(block, page_index, chunk, id, 0); } } @@ -880,7 +911,7 @@ static NV_STATUS block_map_cpu_chunk_on_gpus(uvm_va_block_t *block, uvm_page_ind UVM_ASSERT_MSG(gpu_mapping_addr == 0, "GPU%u DMA address 0x%llx\n", uvm_id_value(id), gpu_mapping_addr); gpu = block_get_gpu(block, id); - status = uvm_gpu_map_cpu_pages(gpu, + status = uvm_gpu_map_cpu_pages(gpu->parent, uvm_cpu_chunk_get_cpu_page(block, chunk, chunk_region.first), chunk_size, &gpu_mapping_addr); @@ -1014,9 +1045,14 @@ static NV_STATUS block_populate_page_cpu(uvm_va_block_t *block, uvm_page_index_t UVM_ASSERT(!uvm_page_mask_test(&block->cpu.resident, page_index)); // Return out of memory error if the tests have requested it. As opposed to - // other error injection settings, this one is persistent. - if (block_test && block_test->inject_cpu_pages_allocation_error) + // other error injection settings, this one fails N times and then succeeds. + // TODO: Bug 3701182: This will print a warning in Linux kernels newer than + // 5.16.0-rc1+. + if (block_test && block_test->inject_cpu_pages_allocation_error_count) { + if (block_test->inject_cpu_pages_allocation_error_count != ~(NvU32)0) + block_test->inject_cpu_pages_allocation_error_count--; return NV_ERR_NO_MEMORY; + } status = uvm_cpu_chunk_alloc(block, page_index, mm, &chunk); if (status != NV_OK) @@ -1178,6 +1214,26 @@ uvm_va_block_region_t uvm_va_block_big_page_region_all(uvm_va_block_t *va_block, return range_big_page_region_all(va_block->start, va_block->end, big_page_size); } +uvm_va_block_region_t uvm_va_block_big_page_region_subset(uvm_va_block_t *va_block, + uvm_va_block_region_t region, + NvU32 big_page_size) +{ + NvU64 start = uvm_va_block_region_start(va_block, region); + NvU64 end = uvm_va_block_region_end(va_block, region); + uvm_va_block_region_t big_region; + + UVM_ASSERT(start < va_block->end); + UVM_ASSERT(end <= va_block->end); + + big_region = range_big_page_region_all(start, end, big_page_size); + if (big_region.outer) { + big_region.first += region.first; + big_region.outer += region.first; + } + + return big_region; +} + size_t uvm_va_block_num_big_pages(uvm_va_block_t *va_block, NvU32 big_page_size) { return range_num_big_pages(va_block->start, va_block->end, big_page_size); @@ -2159,13 +2215,21 @@ static uvm_gpu_address_t block_phys_page_copy_address(uvm_va_block_t *block, return copy_addr; } -uvm_gpu_phys_address_t uvm_va_block_gpu_phys_page_address(uvm_va_block_t *va_block, +uvm_gpu_phys_address_t uvm_va_block_res_phys_page_address(uvm_va_block_t *va_block, uvm_page_index_t page_index, + uvm_processor_id_t residency, uvm_gpu_t *gpu) { uvm_assert_mutex_locked(&va_block->lock); - return block_phys_page_address(va_block, block_phys_page(gpu->id, page_index), gpu); + return block_phys_page_address(va_block, block_phys_page(residency, page_index), gpu); +} + +uvm_gpu_phys_address_t uvm_va_block_gpu_phys_page_address(uvm_va_block_t *va_block, + uvm_page_index_t page_index, + uvm_gpu_t *gpu) +{ + return uvm_va_block_res_phys_page_address(va_block, page_index, gpu->id, gpu); } // Begin a push appropriate for copying data from src_id processor to dst_id processor. @@ -2327,12 +2391,17 @@ typedef enum BLOCK_TRANSFER_MODE_INTERNAL_MOVE_TO_STAGE = 3, BLOCK_TRANSFER_MODE_INTERNAL_MOVE_FROM_STAGE = 4, BLOCK_TRANSFER_MODE_INTERNAL_COPY_TO_STAGE = 5, - BLOCK_TRANSFER_MODE_INTERNAL_COPY_FROM_STAGE = 6 + BLOCK_TRANSFER_MODE_INTERNAL_COPY_FROM_STAGE = 6, + BLOCK_TRANSFER_MODE_INTERNAL_COPY_ONLY = 7 } block_transfer_mode_internal_t; static uvm_va_block_transfer_mode_t get_block_transfer_mode_from_internal(block_transfer_mode_internal_t transfer_mode) { switch (transfer_mode) { + // For HMM, BLOCK_TRANSFER_MODE_INTERNAL_COPY_ONLY is just part of a + // two phase move. First the pages are copied, then after + // migrate_vma_pages() succeeds, residency and mapping are updated. + case BLOCK_TRANSFER_MODE_INTERNAL_COPY_ONLY: case BLOCK_TRANSFER_MODE_INTERNAL_MOVE: case BLOCK_TRANSFER_MODE_INTERNAL_MOVE_TO_STAGE: case BLOCK_TRANSFER_MODE_INTERNAL_MOVE_FROM_STAGE: @@ -2391,6 +2460,57 @@ static uvm_va_block_region_t block_phys_contig_region(uvm_va_block_t *block, } } +typedef struct +{ + // Location of the memory + uvm_processor_id_t id; + + // Whether the whole block has a single physically-contiguous chunk of + // storage on the processor. + bool is_block_contig; + + // Starting address of the physically-contiguous allocation, from the view + // of the copying GPU. Valid only if is_block_contig. + uvm_gpu_address_t address; +} block_copy_addr_t; + +typedef struct +{ + block_copy_addr_t src; + block_copy_addr_t dst; +} block_copy_state_t; + +// Like block_phys_page_copy_address, but uses the address cached in bca when +// possible. +static uvm_gpu_address_t block_copy_get_address(uvm_va_block_t *block, + block_copy_addr_t *bca, + uvm_page_index_t page_index, + uvm_gpu_t *copying_gpu) +{ + if (bca->is_block_contig) { + uvm_gpu_address_t addr = bca->address; + addr.address += page_index * PAGE_SIZE; + UVM_ASSERT(block_phys_copy_contig_check(block, page_index, &bca->address, bca->id, copying_gpu)); + return addr; + } + + return block_phys_page_copy_address(block, block_phys_page(bca->id, page_index), copying_gpu); +} + +static void block_copy_push(uvm_va_block_t *block, + block_copy_state_t *state, + uvm_va_block_region_t region, + uvm_push_t *push) +{ + + uvm_gpu_t *copying_gpu = uvm_push_get_gpu(push); + uvm_push_set_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); + copying_gpu->parent->ce_hal->memcopy(push, + block_copy_get_address(block, &state->dst, region.first, copying_gpu), + block_copy_get_address(block, &state->src, region.first, copying_gpu), + uvm_va_block_region_size(region)); +} + // Copies pages resident on the src_id processor to the dst_id processor // // The function adds the pages that were successfully copied to the output @@ -2403,7 +2523,7 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, uvm_processor_id_t dst_id, uvm_processor_id_t src_id, uvm_va_block_region_t region, - const uvm_page_mask_t *page_mask, + uvm_page_mask_t *copy_mask, const uvm_page_mask_t *prefetch_page_mask, block_transfer_mode_internal_t transfer_mode, uvm_page_mask_t *migrated_pages, @@ -2418,7 +2538,6 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, uvm_page_index_t page_index; uvm_page_index_t contig_start_index = region.outer; uvm_page_index_t last_index = region.outer; - uvm_page_mask_t *copy_mask = &block_context->make_resident.copy_resident_pages_between_mask; uvm_range_group_range_t *rgr = NULL; bool rgr_has_changed = false; uvm_make_resident_cause_t cause = block_context->make_resident.cause; @@ -2426,26 +2545,21 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, const bool may_prefetch = (cause == UVM_MAKE_RESIDENT_CAUSE_REPLAYABLE_FAULT || cause == UVM_MAKE_RESIDENT_CAUSE_NON_REPLAYABLE_FAULT || cause == UVM_MAKE_RESIDENT_CAUSE_ACCESS_COUNTER) && !!prefetch_page_mask; - const bool is_src_phys_contig = is_block_phys_contig(block, src_id); - const bool is_dst_phys_contig = is_block_phys_contig(block, dst_id); - uvm_gpu_address_t contig_src_address = {0}; - uvm_gpu_address_t contig_dst_address = {0}; + block_copy_state_t state = {0}; uvm_va_range_t *va_range = block->va_range; uvm_va_space_t *va_space = uvm_va_block_get_va_space(block); const uvm_va_block_transfer_mode_t block_transfer_mode = get_block_transfer_mode_from_internal(transfer_mode); + state.src.id = src_id; + state.dst.id = dst_id; + state.src.is_block_contig = is_block_phys_contig(block, src_id); + state.dst.is_block_contig = is_block_phys_contig(block, dst_id); + *copied_pages = 0; - if (uvm_id_equal(dst_id, src_id)) - return NV_OK; - - uvm_page_mask_init_from_region(copy_mask, region, src_resident_mask); - - if (page_mask) - uvm_page_mask_and(copy_mask, copy_mask, page_mask); - - // If there are not pages to be copied, exit early - if (!uvm_page_mask_andnot(copy_mask, copy_mask, dst_resident_mask)) + // If there are no pages to be copied, exit early + if (!uvm_page_mask_andnot(copy_mask, copy_mask, dst_resident_mask) || + !uvm_page_mask_andnot(copy_mask, copy_mask, migrated_pages)) return NV_OK; // uvm_range_group_range_iter_first should only be called when the va_space @@ -2458,6 +2572,7 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, rgr_has_changed = true; } + // TODO: Bug 3745051: This function is complicated and needs refactoring for_each_va_block_page_in_region_mask(page_index, copy_mask, region) { NvU64 page_start = uvm_va_block_cpu_page_address(block, page_index); uvm_make_resident_cause_t page_cause = (may_prefetch && uvm_page_mask_test(prefetch_page_mask, page_index))? @@ -2553,29 +2668,19 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, // NVLINK links. Therefore, for physically-contiguous block // storage, we cache the start address and compute the page address // using the page index. - if (is_src_phys_contig) - contig_src_address = block_phys_page_copy_address(block, block_phys_page(src_id, 0), copying_gpu); - if (is_dst_phys_contig) - contig_dst_address = block_phys_page_copy_address(block, block_phys_page(dst_id, 0), copying_gpu); + if (state.src.is_block_contig) + state.src.address = block_phys_page_copy_address(block, block_phys_page(src_id, 0), copying_gpu); + if (state.dst.is_block_contig) + state.dst.address = block_phys_page_copy_address(block, block_phys_page(dst_id, 0), copying_gpu); } else if ((page_index != last_index + 1) || contig_cause != page_cause) { uvm_va_block_region_t contig_region = uvm_va_block_region(contig_start_index, last_index + 1); - size_t contig_region_size = uvm_va_block_region_size(contig_region); UVM_ASSERT(uvm_va_block_region_contains_region(region, contig_region)); // If both src and dst are physically-contiguous, consolidate copies // of contiguous pages into a single method. - if (is_src_phys_contig && is_dst_phys_contig) { - uvm_gpu_address_t src_address = contig_src_address; - uvm_gpu_address_t dst_address = contig_dst_address; - - src_address.address += contig_start_index * PAGE_SIZE; - dst_address.address += contig_start_index * PAGE_SIZE; - - uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); - - copying_gpu->parent->ce_hal->memcopy(&push, dst_address, src_address, contig_region_size); - } + if (state.src.is_block_contig && state.dst.is_block_contig) + block_copy_push(block, &state, contig_region, &push); uvm_perf_event_notify_migration(&va_space->perf_events, &push, @@ -2583,7 +2688,7 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, dst_id, src_id, uvm_va_block_region_start(block, contig_region), - contig_region_size, + uvm_va_block_region_size(contig_region), block_transfer_mode, contig_cause, &block_context->make_resident); @@ -2592,34 +2697,8 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, contig_cause = page_cause; } - if (is_src_phys_contig) - UVM_ASSERT(block_phys_copy_contig_check(block, page_index, &contig_src_address, src_id, copying_gpu)); - if (is_dst_phys_contig) - UVM_ASSERT(block_phys_copy_contig_check(block, page_index, &contig_dst_address, dst_id, copying_gpu)); - - if (!is_src_phys_contig || !is_dst_phys_contig) { - uvm_gpu_address_t src_address; - uvm_gpu_address_t dst_address; - - if (is_src_phys_contig) { - src_address = contig_src_address; - src_address.address += page_index * PAGE_SIZE; - } - else { - src_address = block_phys_page_copy_address(block, block_phys_page(src_id, page_index), copying_gpu); - } - - if (is_dst_phys_contig) { - dst_address = contig_dst_address; - dst_address.address += page_index * PAGE_SIZE; - } - else { - dst_address = block_phys_page_copy_address(block, block_phys_page(dst_id, page_index), copying_gpu); - } - - uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); - copying_gpu->parent->ce_hal->memcopy(&push, dst_address, src_address, PAGE_SIZE); - } + if (!state.src.is_block_contig || !state.dst.is_block_contig) + block_copy_push(block, &state, uvm_va_block_region_for_page(page_index), &push); last_index = page_index; } @@ -2627,19 +2706,10 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, // Copy the remaining pages if (copying_gpu) { uvm_va_block_region_t contig_region = uvm_va_block_region(contig_start_index, last_index + 1); - size_t contig_region_size = uvm_va_block_region_size(contig_region); UVM_ASSERT(uvm_va_block_region_contains_region(region, contig_region)); - if (is_src_phys_contig && is_dst_phys_contig) { - uvm_gpu_address_t src_address = contig_src_address; - uvm_gpu_address_t dst_address = contig_dst_address; - - src_address.address += contig_start_index * PAGE_SIZE; - dst_address.address += contig_start_index * PAGE_SIZE; - - uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); - copying_gpu->parent->ce_hal->memcopy(&push, dst_address, src_address, contig_region_size); - } + if (state.src.is_block_contig && state.dst.is_block_contig) + block_copy_push(block, &state, contig_region, &push); uvm_perf_event_notify_migration(&va_space->perf_events, &push, @@ -2647,7 +2717,7 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, dst_id, src_id, uvm_va_block_region_start(block, contig_region), - contig_region_size, + uvm_va_block_region_size(contig_region), block_transfer_mode, contig_cause, &block_context->make_resident); @@ -2673,8 +2743,11 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, if (*copied_pages) { uvm_page_mask_or(migrated_pages, migrated_pages, copy_mask); - uvm_page_mask_or(dst_resident_mask, dst_resident_mask, copy_mask); - block_set_resident_processor(block, dst_id); + // For HMM, the residency is updated after migrate_vma_pages() succeeds. + if (transfer_mode != BLOCK_TRANSFER_MODE_INTERNAL_COPY_ONLY) { + uvm_page_mask_or(dst_resident_mask, dst_resident_mask, copy_mask); + block_set_resident_processor(block, dst_id); + } if (transfer_mode == BLOCK_TRANSFER_MODE_INTERNAL_MOVE_FROM_STAGE) { // Check whether there are any resident pages left on src @@ -2682,7 +2755,8 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, block_clear_resident_processor(block, src_id); } - // If we are staging the copy due to read duplication, we keep the copy there + // If we are staging the copy due to read duplication, we keep the copy + // there if (transfer_mode == BLOCK_TRANSFER_MODE_INTERNAL_COPY || transfer_mode == BLOCK_TRANSFER_MODE_INTERNAL_COPY_TO_STAGE) uvm_page_mask_or(&block->read_duplicated_pages, &block->read_duplicated_pages, copy_mask); @@ -2746,23 +2820,30 @@ static NV_STATUS block_copy_resident_pages_mask(uvm_va_block_t *block, uvm_va_space_t *va_space = uvm_va_block_get_va_space(block); uvm_processor_id_t src_id; uvm_processor_mask_t search_mask; + uvm_page_mask_t *copy_mask = &block_context->make_resident.copy_resident_pages_between_mask; uvm_processor_mask_copy(&search_mask, src_processor_mask); *copied_pages_out = 0; for_each_closest_id(src_id, &search_mask, dst_id, va_space) { + uvm_page_mask_t *src_resident_mask = uvm_va_block_resident_mask_get(block, src_id); NV_STATUS status; NvU32 copied_pages_from_src; UVM_ASSERT(!uvm_id_equal(src_id, dst_id)); + uvm_page_mask_init_from_region(copy_mask, region, src_resident_mask); + + if (page_mask) + uvm_page_mask_and(copy_mask, copy_mask, page_mask); + status = block_copy_resident_pages_between(block, block_context, dst_id, src_id, region, - page_mask, + copy_mask, prefetch_page_mask, transfer_mode, migrated_pages, @@ -2852,7 +2933,10 @@ static void block_copy_set_first_touch_residency(uvm_va_block_t *block, // // If UVM_VA_BLOCK_TRANSFER_MODE_COPY is passed, processors that already have a // copy of the page will keep it. Conversely, if UVM_VA_BLOCK_TRANSFER_MODE_MOVE -// is passed, the page will no longer be resident in any processor other than dst_id. +// is passed, the page will no longer be resident in any processor other than +// dst_id. If UVM_VA_BLOCK_TRANSFER_MODE_COPY_ONLY is passed, the destination +// pages are copied into but the residency bits for source and destination are +// not updated. static NV_STATUS block_copy_resident_pages(uvm_va_block_t *block, uvm_va_block_context_t *block_context, uvm_processor_id_t dst_id, @@ -2903,6 +2987,13 @@ static NV_STATUS block_copy_resident_pages(uvm_va_block_t *block, uvm_processor_mask_and(&src_processor_mask, block_get_can_copy_from_mask(block, dst_id), &block->resident); uvm_processor_mask_clear(&src_processor_mask, dst_id); + if (transfer_mode == UVM_VA_BLOCK_TRANSFER_MODE_MOVE) + transfer_mode_internal = BLOCK_TRANSFER_MODE_INTERNAL_MOVE; + else if (transfer_mode == UVM_VA_BLOCK_TRANSFER_MODE_COPY) + transfer_mode_internal = BLOCK_TRANSFER_MODE_INTERNAL_COPY; + else + transfer_mode_internal = BLOCK_TRANSFER_MODE_INTERNAL_COPY_ONLY; + status = block_copy_resident_pages_mask(block, block_context, dst_id, @@ -2910,9 +3001,7 @@ static NV_STATUS block_copy_resident_pages(uvm_va_block_t *block, region, copy_page_mask, prefetch_page_mask, - transfer_mode == UVM_VA_BLOCK_TRANSFER_MODE_COPY? - BLOCK_TRANSFER_MODE_INTERNAL_COPY: - BLOCK_TRANSFER_MODE_INTERNAL_MOVE, + transfer_mode_internal, missing_pages_count, migrated_pages, &pages_copied, @@ -2940,7 +3029,9 @@ static NV_STATUS block_copy_resident_pages(uvm_va_block_t *block, uvm_page_mask_zero(staged_pages); - if (UVM_ID_IS_CPU(dst_id)) { + if (transfer_mode == UVM_VA_BLOCK_TRANSFER_MODE_COPY_ONLY) + transfer_mode_internal = BLOCK_TRANSFER_MODE_INTERNAL_COPY_ONLY; + else if (UVM_ID_IS_CPU(dst_id)) { transfer_mode_internal = transfer_mode == UVM_VA_BLOCK_TRANSFER_MODE_COPY? BLOCK_TRANSFER_MODE_INTERNAL_COPY: BLOCK_TRANSFER_MODE_INTERNAL_MOVE; @@ -2981,6 +3072,13 @@ static NV_STATUS block_copy_resident_pages(uvm_va_block_t *block, goto out; uvm_tracker_clear(&local_tracker); + if (transfer_mode == UVM_VA_BLOCK_TRANSFER_MODE_MOVE) + transfer_mode_internal = BLOCK_TRANSFER_MODE_INTERNAL_MOVE_FROM_STAGE; + else if (transfer_mode == UVM_VA_BLOCK_TRANSFER_MODE_COPY) + transfer_mode_internal = BLOCK_TRANSFER_MODE_INTERNAL_COPY_FROM_STAGE; + else + transfer_mode_internal = BLOCK_TRANSFER_MODE_INTERNAL_COPY_ONLY; + // Now copy staged pages from the CPU to the destination. status = block_copy_resident_pages_between(block, block_context, @@ -2989,9 +3087,7 @@ static NV_STATUS block_copy_resident_pages(uvm_va_block_t *block, region, staged_pages, prefetch_page_mask, - transfer_mode == UVM_VA_BLOCK_TRANSFER_MODE_COPY? - BLOCK_TRANSFER_MODE_INTERNAL_COPY_FROM_STAGE: - BLOCK_TRANSFER_MODE_INTERNAL_MOVE_FROM_STAGE, + transfer_mode_internal, migrated_pages, &pages_copied, &local_tracker); @@ -3010,7 +3106,8 @@ out: // Pages that weren't resident anywhere else were populated at the // destination directly. Mark them as resident now. We only do it if there // have been no errors because we cannot identify which pages failed. - if (status == NV_OK && missing_pages_count > 0) + // For HMM, don't do this until migrate_vma_pages() succeeds. + if (status == NV_OK && missing_pages_count > 0 && transfer_mode != UVM_VA_BLOCK_TRANSFER_MODE_COPY_ONLY) block_copy_set_first_touch_residency(block, block_context, dst_id, region, page_mask); // Break read duplication @@ -3048,14 +3145,15 @@ out: return status == NV_OK ? tracker_status : status; } -NV_STATUS uvm_va_block_make_resident(uvm_va_block_t *va_block, +static NV_STATUS block_make_resident(uvm_va_block_t *va_block, uvm_va_block_retry_t *va_block_retry, uvm_va_block_context_t *va_block_context, uvm_processor_id_t dest_id, uvm_va_block_region_t region, const uvm_page_mask_t *page_mask, const uvm_page_mask_t *prefetch_page_mask, - uvm_make_resident_cause_t cause) + uvm_make_resident_cause_t cause, + uvm_va_block_transfer_mode_t transfer_mode) { NV_STATUS status; uvm_processor_mask_t unmap_processor_mask; @@ -3073,6 +3171,7 @@ NV_STATUS uvm_va_block_make_resident(uvm_va_block_t *va_block, uvm_assert_mutex_locked(&va_block->lock); UVM_ASSERT(uvm_va_block_is_hmm(va_block) || va_block->va_range->type == UVM_VA_RANGE_TYPE_MANAGED); + UVM_ASSERT(uvm_va_block_check_policy_is_valid(va_block, va_block_context->policy, region)); resident_mask = block_resident_mask_get_alloc(va_block, dest_id); if (!resident_mask) @@ -3122,7 +3221,7 @@ NV_STATUS uvm_va_block_make_resident(uvm_va_block_t *va_block, region, page_mask, prefetch_page_mask, - UVM_VA_BLOCK_TRANSFER_MODE_MOVE); + transfer_mode); if (status != NV_OK) return status; @@ -3132,12 +3231,95 @@ NV_STATUS uvm_va_block_make_resident(uvm_va_block_t *va_block, // // Skip this if we didn't do anything (the input region and/or page mask was // empty). - if (uvm_processor_mask_test(&va_block->resident, dest_id)) + if (transfer_mode == UVM_VA_BLOCK_TRANSFER_MODE_MOVE && uvm_processor_mask_test(&va_block->resident, dest_id)) block_mark_memory_used(va_block, dest_id); return NV_OK; } +NV_STATUS uvm_va_block_make_resident(uvm_va_block_t *va_block, + uvm_va_block_retry_t *va_block_retry, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t dest_id, + uvm_va_block_region_t region, + const uvm_page_mask_t *page_mask, + const uvm_page_mask_t *prefetch_page_mask, + uvm_make_resident_cause_t cause) +{ + return block_make_resident(va_block, + va_block_retry, + va_block_context, + dest_id, + region, + page_mask, + prefetch_page_mask, + cause, + UVM_VA_BLOCK_TRANSFER_MODE_MOVE); +} + +NV_STATUS uvm_va_block_make_resident_pre(uvm_va_block_t *va_block, + uvm_va_block_retry_t *va_block_retry, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t dest_id, + uvm_va_block_region_t region, + const uvm_page_mask_t *page_mask, + const uvm_page_mask_t *prefetch_page_mask, + uvm_make_resident_cause_t cause) +{ + return block_make_resident(va_block, + va_block_retry, + va_block_context, + dest_id, + region, + page_mask, + prefetch_page_mask, + cause, + UVM_VA_BLOCK_TRANSFER_MODE_COPY_ONLY); +} + +void uvm_va_block_make_resident_post(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_va_block_region_t region, + const uvm_page_mask_t *page_mask) +{ + uvm_page_mask_t *migrated_pages = &va_block_context->make_resident.pages_migrated; + uvm_processor_id_t dst_id = va_block_context->make_resident.dest_id; + uvm_page_mask_t *dst_resident_mask = uvm_va_block_resident_mask_get(va_block, dst_id); + + uvm_assert_mutex_locked(&va_block->lock); + + if (page_mask) + uvm_page_mask_and(migrated_pages, migrated_pages, page_mask); + + if (!uvm_page_mask_empty(migrated_pages)) { + // The migrated pages are now resident on the destination. + uvm_page_mask_or(dst_resident_mask, dst_resident_mask, migrated_pages); + block_set_resident_processor(va_block, dst_id); + } + + // Pages that weren't resident anywhere else were populated at the + // destination directly. Mark them as resident now. We only do it if there + // have been no errors because we cannot identify which pages failed. + // For HMM, don't do this until migrate_vma_pages() succeeds. + block_copy_set_first_touch_residency(va_block, va_block_context, dst_id, region, page_mask); + + // Any move operation implies that mappings have been removed from all + // non-UVM-Lite GPUs. + uvm_page_mask_andnot(&va_block->maybe_mapped_pages, &va_block->maybe_mapped_pages, migrated_pages); + + // Break read duplication and clear residency from other processors. + break_read_duplication_in_region(va_block, va_block_context, dst_id, region, page_mask); + + // Update eviction heuristics, if needed. Notably this could repeat the call + // done in block_set_resident_processor(), but that doesn't do anything bad + // and it's simpler to keep it in both places. + // + // Skip this if we didn't do anything (the input region and/or page mask was + // empty). + if (uvm_processor_mask_test(&va_block->resident, dst_id)) + block_mark_memory_used(va_block, dst_id); +} + // Combination function which prepares the input {region, page_mask} for // entering read-duplication. It: // - Unmaps all processors but revoke_id @@ -3198,6 +3380,10 @@ NV_STATUS uvm_va_block_make_resident_read_duplicate(uvm_va_block_t *va_block, NV_STATUS status = NV_OK; uvm_processor_id_t src_id; + // TODO: Bug 3660922: need to implement HMM read duplication support. + UVM_ASSERT(!uvm_va_block_is_hmm(va_block)); + UVM_ASSERT(va_block_context->policy = uvm_va_range_get_policy(va_block->va_range)); + va_block_context->make_resident.dest_id = dest_id; va_block_context->make_resident.cause = cause; @@ -3568,7 +3754,7 @@ static bool block_check_mappings_page(uvm_va_block_t *block, uvm_page_index_t pa // Processors with mappings must have access to the processor that // has the valid copy UVM_ASSERT_MSG(uvm_processor_mask_subset(&read_mappings, residency_accessible_from), - "Not all processors have access to %s\n", + "Not all processors have access to %s\n" "Resident: 0x%lx - Mappings R: 0x%lx W: 0x%lx A: 0x%lx -" "Access: 0x%lx - Native Atomics: 0x%lx - SWA: 0x%lx\n", uvm_va_space_processor_name(va_space, residency), @@ -3909,9 +4095,12 @@ static void block_unmap_cpu(uvm_va_block_t *block, uvm_va_block_region_t region, if (!block_has_valid_mapping_cpu(block, subregion)) continue; - unmap_mapping_range(&va_space->mapping, - uvm_va_block_region_start(block, subregion), - uvm_va_block_region_size(subregion), 1); + // We can't actually unmap HMM ranges from the CPU here. + // It happens as part of migrate_vma_setup(). + if (!uvm_va_block_is_hmm(block)) + unmap_mapping_range(&va_space->mapping, + uvm_va_block_region_start(block, subregion), + uvm_va_block_region_size(subregion), 1); for (pte_bit = 0; pte_bit < UVM_PTE_BITS_CPU_MAX; pte_bit++) uvm_page_mask_region_clear(&block->cpu.pte_bits[pte_bit], subregion); @@ -5406,7 +5595,7 @@ static void block_gpu_compute_new_pte_state(uvm_va_block_t *block, uvm_page_index_t page_index; size_t big_page_index; DECLARE_BITMAP(big_ptes_not_covered, MAX_BIG_PAGES_PER_UVM_VA_BLOCK); - bool can_make_new_big_ptes, region_full; + bool can_make_new_big_ptes; memset(new_pte_state, 0, sizeof(*new_pte_state)); new_pte_state->needs_4k = true; @@ -5469,14 +5658,11 @@ static void block_gpu_compute_new_pte_state(uvm_va_block_t *block, __set_bit(big_page_index, new_pte_state->big_ptes_covered); - region_full = uvm_page_mask_region_full(page_mask_after, big_page_region); - if (region_full && UVM_ID_IS_INVALID(resident_id)) - __set_bit(big_page_index, new_pte_state->big_ptes_fully_unmapped); - - // When mapping sysmem, we can use big pages only if we are mapping all pages - // in the big page subregion and the CPU pages backing the subregion are - // physically contiguous. - if (can_make_new_big_ptes && region_full && + // When mapping sysmem, we can use big pages only if we are mapping all + // pages in the big page subregion and the CPU pages backing the + // subregion are physically contiguous. + if (can_make_new_big_ptes && + uvm_page_mask_region_full(page_mask_after, big_page_region) && (!UVM_ID_IS_CPU(resident_id) || (contig_region.first <= big_page_region.first && contig_region.outer >= big_page_region.outer))) { __set_bit(big_page_index, new_pte_state->big_ptes); @@ -5988,6 +6174,42 @@ static NV_STATUS uvm_cpu_insert_page(struct vm_area_struct *vma, return NV_OK; } +static uvm_prot_t compute_logical_prot(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_page_index_t page_index) +{ + struct vm_area_struct *vma; + uvm_prot_t logical_prot; + + if (uvm_va_block_is_hmm(va_block)) { + NvU64 addr = uvm_va_block_cpu_page_address(va_block, page_index); + + logical_prot = uvm_hmm_compute_logical_prot(va_block, va_block_context, addr); + } + else { + uvm_va_range_t *va_range = va_block->va_range; + + UVM_ASSERT(va_range->type == UVM_VA_RANGE_TYPE_MANAGED); + + // Zombified VA ranges no longer have a vma, so they have no permissions + if (uvm_va_range_is_managed_zombie(va_range)) { + logical_prot = UVM_PROT_NONE; + } + else { + vma = uvm_va_range_vma(va_range); + + if (!(vma->vm_flags & VM_READ)) + logical_prot = UVM_PROT_NONE; + else if (!(vma->vm_flags & VM_WRITE)) + logical_prot = UVM_PROT_READ_ONLY; + else + logical_prot = UVM_PROT_READ_WRITE_ATOMIC; + } + } + + return logical_prot; +} + // Creates or upgrades a CPU mapping for the given page, updating the block's // mapping and pte_bits bitmaps as appropriate. Upon successful return, the page // will be mapped with at least new_prot permissions. @@ -6008,6 +6230,7 @@ static NV_STATUS uvm_cpu_insert_page(struct vm_area_struct *vma, // - Ensure that the block hasn't been killed (block->va_range is present) // - Update the pte/mapping tracking state on success static NV_STATUS block_map_cpu_page_to(uvm_va_block_t *block, + uvm_va_block_context_t *va_block_context, uvm_processor_id_t resident_id, uvm_page_index_t page_index, uvm_prot_t new_prot) @@ -6041,7 +6264,7 @@ static NV_STATUS block_map_cpu_page_to(uvm_va_block_t *block, // Check for existing VMA permissions. They could have been modified after // the initial mmap by mprotect. - if (!uvm_va_block_is_hmm(block) && new_prot > uvm_va_range_logical_prot(va_range)) + if (new_prot > compute_logical_prot(block, va_block_context, page_index)) return NV_ERR_INVALID_ACCESS_TYPE; if (uvm_va_block_is_hmm(block)) { @@ -6155,6 +6378,7 @@ static NV_STATUS block_map_cpu_to(uvm_va_block_t *block, for_each_va_block_page_in_region_mask(page_index, pages_to_map, region) { status = block_map_cpu_page_to(block, + block_context, resident_id, page_index, new_prot); @@ -6389,6 +6613,7 @@ NV_STATUS uvm_va_block_map(uvm_va_block_t *va_block, UVM_ASSERT(new_prot != UVM_PROT_NONE); UVM_ASSERT(new_prot < UVM_PROT_MAX); uvm_assert_mutex_locked(&va_block->lock); + UVM_ASSERT(uvm_va_block_check_policy_is_valid(va_block, va_block_context->policy, region)); // Mapping is not supported on the eviction path that doesn't hold the VA // space lock. @@ -6730,6 +6955,8 @@ NV_STATUS uvm_va_block_map_mask(uvm_va_block_t *va_block, NV_STATUS tracker_status; uvm_processor_id_t id; + UVM_ASSERT(uvm_va_block_check_policy_is_valid(va_block, va_block_context->policy, region)); + for_each_id_in_mask(id, map_processor_mask) { status = uvm_va_block_map(va_block, va_block_context, @@ -7176,28 +7403,8 @@ static NV_STATUS block_evict_pages_from_gpu(uvm_va_block_t *va_block, uvm_gpu_t uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); uvm_va_block_context_t *block_context = uvm_va_space_block_context(va_space, mm); - if (!uvm_va_block_is_hmm(va_block)) - block_context->policy = uvm_va_range_get_policy(va_block->va_range); - // Move all subregions resident on the GPU to the CPU for_each_va_block_subregion_in_mask(subregion, resident, region) { - // Need to set block_context->policy for HMM. - if (uvm_va_block_is_hmm(va_block)) { - uvm_va_policy_node_t *node; - - node = uvm_va_policy_node_find(va_block, uvm_va_block_region_start(va_block, subregion)); - if (node) { - uvm_page_index_t outer = uvm_va_block_cpu_page_index(va_block, - node->node.end) + 1; - // If the policy doesn't cover the subregion, truncate the - // subregion. - if (subregion.outer > outer) - subregion.outer = outer; - block_context->policy = &node->policy; - } - else - block_context->policy = &uvm_va_policy_default; - } status = uvm_va_block_migrate_locked(va_block, NULL, block_context, @@ -7630,13 +7837,82 @@ error: return status; } +static NV_STATUS block_split_cpu_chunk_to_size(uvm_va_block_t *block, + uvm_page_index_t page_index, + uvm_cpu_chunk_t *chunk, + uvm_chunk_size_t new_size) +{ + size_t num_new_chunks = uvm_cpu_chunk_get_size(chunk) / new_size; + uvm_cpu_chunk_t **new_chunks = NULL; + uvm_gpu_t *gpu; + NvU64 gpu_mapping_addr; + uvm_processor_mask_t gpu_split_mask; + uvm_gpu_id_t id; + NV_STATUS status; + size_t i; + + UVM_ASSERT(IS_ALIGNED(uvm_cpu_chunk_get_size(chunk), new_size)); + + uvm_processor_mask_zero(&gpu_split_mask); + for_each_gpu_id(id) { + if (!uvm_va_block_gpu_state_get(block, id)) + continue; + + // If the parent chunk has not been mapped, there is nothing to split. + gpu_mapping_addr = uvm_cpu_chunk_get_gpu_mapping_addr(block, page_index, chunk, id); + if (gpu_mapping_addr == 0) + continue; + + gpu = block_get_gpu(block, id); + status = uvm_pmm_sysmem_mappings_split_gpu_mappings(&gpu->pmm_reverse_sysmem_mappings, + gpu_mapping_addr, + new_size); + if (status != NV_OK) + goto merge; + + uvm_processor_mask_set(&gpu_split_mask, id); + } + + uvm_cpu_chunk_remove_from_block(block, chunk, page_index); + new_chunks = uvm_kvmalloc(num_new_chunks * sizeof(*new_chunks)); + if (new_chunks) + status = uvm_cpu_chunk_split(block, chunk, new_size, UVM_CPU_CHUNK_PAGE_INDEX(chunk, page_index), new_chunks); + else + status = NV_ERR_NO_MEMORY; + + if (status != NV_OK) { + uvm_cpu_chunk_insert_in_block(block, chunk, UVM_CPU_CHUNK_PAGE_INDEX(chunk, page_index)); + +merge: + for_each_gpu_id_in_mask (id, &gpu_split_mask) { + gpu_mapping_addr = uvm_cpu_chunk_get_gpu_mapping_addr(block, page_index, chunk, id); + gpu = block_get_gpu(block, id); + uvm_pmm_sysmem_mappings_merge_gpu_mappings(&gpu->pmm_reverse_sysmem_mappings, + gpu_mapping_addr, + uvm_cpu_chunk_get_size(chunk)); + } + } else { + for (i = 0; i < num_new_chunks; i++) { + status = uvm_cpu_chunk_insert_in_block(block, + new_chunks[i], + UVM_CPU_CHUNK_PAGE_INDEX(new_chunks[i], + (page_index + + (i * (new_size / PAGE_SIZE))))); + UVM_ASSERT(status == NV_OK); + } + } + + uvm_kvfree(new_chunks); + return status; +} + // Perform any CPU chunk splitting that may be required for this block split. // Just like block_presplit_gpu_chunks, no chunks are moved to the new block. static NV_STATUS block_presplit_cpu_chunks(uvm_va_block_t *existing, uvm_va_block_t *new) { uvm_page_index_t page_index = uvm_va_block_cpu_page_index(existing, new->start); uvm_cpu_chunk_t *splitting_chunk; - uvm_chunk_size_t split_sizes = uvm_cpu_chunk_get_allocation_sizes(); + uvm_chunk_sizes_mask_t split_sizes = uvm_cpu_chunk_get_allocation_sizes(); uvm_chunk_size_t subchunk_size; NV_STATUS status = NV_OK; @@ -7660,32 +7936,7 @@ static NV_STATUS block_presplit_cpu_chunks(uvm_va_block_t *existing, uvm_va_bloc split_sizes &= ~(IS_ALIGNED(new->start, UVM_CHUNK_SIZE_64K) ? UVM_CHUNK_SIZE_64K - 1 : 0); for_each_chunk_size_rev(subchunk_size, split_sizes) { - uvm_gpu_id_t id; - - UVM_ASSERT(IS_ALIGNED(uvm_cpu_chunk_get_size(splitting_chunk), subchunk_size)); - - for_each_gpu_id(id) { - uvm_gpu_t *gpu; - - if (!uvm_va_block_gpu_state_get(existing, id)) - continue; - - // If the parent chunk has not been mapped, there is nothing to split. - if (uvm_cpu_chunk_get_gpu_mapping_addr(existing, page_index, splitting_chunk, id) == 0) - continue; - - gpu = block_get_gpu(existing, id); - status = uvm_pmm_sysmem_mappings_split_gpu_mappings(&gpu->pmm_reverse_sysmem_mappings, - uvm_cpu_chunk_get_gpu_mapping_addr(existing, - page_index, - splitting_chunk, - id), - subchunk_size); - if (status != NV_OK) - return status; - } - - status = uvm_cpu_chunk_split(existing, splitting_chunk, subchunk_size); + status = block_split_cpu_chunk_to_size(existing, page_index, splitting_chunk, subchunk_size); if (status != NV_OK) return status; @@ -7695,36 +7946,114 @@ static NV_STATUS block_presplit_cpu_chunks(uvm_va_block_t *existing, uvm_va_bloc return NV_OK; } -static void block_merge_cpu_chunks(uvm_va_block_t *existing, uvm_va_block_t *new) +static NV_STATUS block_merge_cpu_chunks_to_size(uvm_va_block_t *block, + uvm_chunk_size_t size, + uvm_page_index_t page_index) { - uvm_page_index_t page_index = uvm_va_block_cpu_page_index(existing, new->start); - uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(existing, page_index); - uvm_va_space_t *va_space = existing->va_range->va_space; + uvm_cpu_chunk_t *chunk; + size_t num_merge_chunks; + uvm_chunk_size_t chunk_size; + uvm_cpu_chunk_t **merge_chunks; uvm_gpu_id_t id; + size_t i; + NV_STATUS status; - if (!chunk) - return; + chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); + chunk_size = uvm_cpu_chunk_get_size(chunk); + num_merge_chunks = size / chunk_size; - // Merge the CPU chunk. If a merge was not done, nothing else needs to be done. - chunk = uvm_cpu_chunk_merge(existing, chunk); - if (!chunk) - return; + // It's OK if we can't merge here. We know that the CPU chunk split + // operation completed successfully. Therefore, the CPU chunks are in a + // sane state. + merge_chunks = uvm_kvmalloc(num_merge_chunks * sizeof(*merge_chunks)); + if (!merge_chunks) + return NV_ERR_NO_MEMORY; + + for (i = 0; i < num_merge_chunks; i++) { + merge_chunks[i] = uvm_cpu_chunk_get_chunk_for_page(block, page_index + (i * (chunk_size / PAGE_SIZE))); + UVM_ASSERT(merge_chunks[i]); + UVM_ASSERT(uvm_cpu_chunk_get_size(merge_chunks[i]) == chunk_size); + uvm_cpu_chunk_remove_from_block(block, merge_chunks[i], page_index + (i * (chunk_size / PAGE_SIZE))); + } + + // Merge the CPU chunk. If a merge was not done, re-insert the original chunks. + status = uvm_cpu_chunk_merge(block, merge_chunks, num_merge_chunks, size, &chunk); + if (status == NV_WARN_NOTHING_TO_DO) { + for (i = 0; i < num_merge_chunks; i++) + uvm_cpu_chunk_insert_in_block(block, merge_chunks[i], page_index + (i * (chunk_size / PAGE_SIZE))); + + goto done; + } + + UVM_ASSERT(status == NV_OK); + + status = uvm_cpu_chunk_insert_in_block(block, chunk, page_index); + UVM_ASSERT(status == NV_OK); for_each_gpu_id(id) { NvU64 gpu_mapping_addr; uvm_gpu_t *gpu; - if (!uvm_va_block_gpu_state_get(existing, id)) + if (!uvm_va_block_gpu_state_get(block, id)) continue; - gpu_mapping_addr = uvm_cpu_chunk_get_gpu_mapping_addr(existing, page_index, chunk, id); + gpu_mapping_addr = uvm_cpu_chunk_get_gpu_mapping_addr(block, page_index, chunk, id); if (gpu_mapping_addr == 0) continue; - gpu = uvm_va_space_get_gpu(va_space, id); - uvm_pmm_sysmem_mappings_merge_gpu_mappings(&gpu->pmm_reverse_sysmem_mappings, - gpu_mapping_addr, - uvm_cpu_chunk_get_size(chunk)); + gpu = block_get_gpu(block, id); + uvm_pmm_sysmem_mappings_merge_gpu_mappings(&gpu->pmm_reverse_sysmem_mappings, gpu_mapping_addr, size); + } + +done: + uvm_kvfree(merge_chunks); + return status; +} + +static void block_merge_cpu_chunks(uvm_va_block_t *existing, uvm_va_block_t *new) +{ + uvm_page_index_t page_index = uvm_va_block_cpu_page_index(existing, new->start); + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(existing, page_index); + uvm_chunk_sizes_mask_t merge_sizes = uvm_cpu_chunk_get_allocation_sizes(); + uvm_chunk_size_t largest_size; + uvm_chunk_size_t chunk_size; + uvm_chunk_size_t merge_size; + size_t block_size = uvm_va_block_size(existing); + NV_STATUS status; + + if (!chunk) + return; + + chunk_size = uvm_cpu_chunk_get_size(chunk); + + // Remove all CPU chunk sizes above the size of the existing VA block. + // Since block sizes are not always powers of 2, use the largest power of 2 + // less than or equal to the block size since we can't merge to a size + // larger than the block's size. + largest_size = rounddown_pow_of_two(block_size); + merge_sizes &= (largest_size | (largest_size - 1)); + + // Remove all CPU chunk sizes smaller than the size of the chunk being merged up. + merge_sizes &= ~(chunk_size | (chunk_size - 1)); + + for_each_chunk_size(merge_size, merge_sizes) { + uvm_va_block_region_t chunk_region; + + // The block has to fully contain the VA range after the merge. + if (!uvm_va_block_contains_address(existing, UVM_ALIGN_DOWN(new->start, merge_size)) || + !uvm_va_block_contains_address(existing, UVM_ALIGN_DOWN(new->start, merge_size) + merge_size - 1)) + break; + + chunk_region = uvm_va_block_chunk_region(existing, merge_size, page_index); + + // If not all pages in the region covered by the chunk are allocated, + // we can't merge. + if (!uvm_page_mask_region_full(&existing->cpu.allocated, chunk_region)) + break; + + status = block_merge_cpu_chunks_to_size(existing, merge_size, chunk_region.first); + if (status != NV_OK) + break; } } @@ -7737,7 +8066,7 @@ static NV_STATUS block_split_preallocate_no_retry(uvm_va_block_t *existing, uvm_ uvm_gpu_t *gpu; uvm_gpu_id_t id; uvm_page_index_t split_page_index; - uvm_va_range_t *existing_va_range = existing->va_range; + uvm_va_block_test_t *block_test; status = block_presplit_cpu_chunks(existing, new); if (status != NV_OK) @@ -7759,8 +8088,13 @@ static NV_STATUS block_split_preallocate_no_retry(uvm_va_block_t *existing, uvm_ } } - if (existing_va_range && existing_va_range->inject_split_error) { - existing_va_range->inject_split_error = false; + block_test = uvm_va_block_get_test(existing); + if (block_test && block_test->inject_split_error) { + block_test->inject_split_error = false; + if (!uvm_va_block_is_hmm(existing)) { + UVM_ASSERT(existing->va_range->inject_split_error); + existing->va_range->inject_split_error = false; + } status = NV_ERR_NO_MEMORY; goto error; } @@ -8330,8 +8664,10 @@ NV_STATUS uvm_va_block_split_locked(uvm_va_block_t *existing_va_block, block_set_processor_masks(existing_va_block); block_set_processor_masks(new_block); - if (uvm_va_block_is_hmm(existing_va_block)) + if (uvm_va_block_is_hmm(existing_va_block)) { + uvm_hmm_va_block_split_tree(existing_va_block, new_block); uvm_va_policy_node_split_move(existing_va_block, new_block); + } out: // Run checks on existing_va_block even on failure, since an error must @@ -8363,7 +8699,7 @@ static bool block_region_might_read_duplicate(uvm_va_block_t *va_block, if (!uvm_va_space_can_read_duplicate(va_space, NULL)) return false; - // TODO: Bug 2046423: need to implement read duplication support in Linux. + // TODO: Bug 3660922: need to implement HMM read duplication support. if (uvm_va_block_is_hmm(va_block) || uvm_va_range_get_policy(va_range)->read_duplication == UVM_READ_DUPLICATION_DISABLED) return false; @@ -8382,22 +8718,20 @@ static bool block_region_might_read_duplicate(uvm_va_block_t *va_block, // could be changed in the future to optimize multiple faults/counters on // contiguous pages. static uvm_prot_t compute_new_permission(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, uvm_page_index_t page_index, uvm_processor_id_t fault_processor_id, uvm_processor_id_t new_residency, uvm_fault_access_type_t access_type) { - uvm_va_range_t *va_range; uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); uvm_prot_t logical_prot, new_prot; // TODO: Bug 1766432: Refactor into policies. Current policy is // query_promote: upgrade access privileges to avoid future faults IF // they don't trigger further revocations. - va_range = va_block->va_range; - new_prot = uvm_fault_access_type_to_prot(access_type); - logical_prot = uvm_va_range_logical_prot(va_range); + logical_prot = compute_logical_prot(va_block, va_block_context, page_index); UVM_ASSERT(logical_prot >= new_prot); @@ -8542,7 +8876,10 @@ NV_STATUS uvm_va_block_add_mappings_after_migration(uvm_va_block_t *va_block, uvm_va_policy_t *policy = va_block_context->policy; uvm_processor_id_t preferred_location; - // Read duplication takes precedence over SetAccesedBy. + uvm_assert_mutex_locked(&va_block->lock); + UVM_ASSERT(uvm_va_block_check_policy_is_valid(va_block, policy, region)); + + // Read duplication takes precedence over SetAccessedBy. // // Exclude ranges with read duplication set... if (uvm_va_policy_is_read_duplicate(policy, va_space)) { @@ -8764,6 +9101,8 @@ NV_STATUS uvm_va_block_add_mappings(uvm_va_block_t *va_block, uvm_range_group_range_iter_t iter; uvm_prot_t prot_to_map; + UVM_ASSERT(uvm_va_block_check_policy_is_valid(va_block, va_block_context->policy, region)); + if (UVM_ID_IS_CPU(processor_id) && !uvm_va_block_is_hmm(va_block)) { if (!uvm_va_range_vma_check(va_range, va_block_context->mm)) return NV_OK; @@ -8778,7 +9117,7 @@ NV_STATUS uvm_va_block_add_mappings(uvm_va_block_t *va_block, va_block_context->mask_by_prot[prot_to_map - 1].count = 0; for_each_va_block_page_in_region_mask(page_index, page_mask, region) { - // Read duplication takes precedence over SetAccesedBy. Exclude pages + // Read duplication takes precedence over SetAccessedBy. Exclude pages // read-duplicated by performance heuristics if (uvm_page_mask_test(&va_block->read_duplicated_pages, page_index)) continue; @@ -8882,6 +9221,7 @@ static bool map_remote_on_atomic_fault(uvm_va_space_t *va_space, // could be changed in the future to optimize multiple faults or access // counter notifications on contiguous pages. static uvm_processor_id_t block_select_residency(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, uvm_page_index_t page_index, uvm_processor_id_t processor_id, NvU32 access_type_mask, @@ -8895,7 +9235,9 @@ static uvm_processor_id_t block_select_residency(uvm_va_block_t *va_block, bool may_read_duplicate; uvm_processor_id_t preferred_location; - if (is_uvm_fault_force_sysmem_set()) { + // TODO: Bug 3660968: Remove uvm_hmm_force_sysmem_set() check as soon as + // HMM migration is implemented VMAs other than anonymous memory. + if (is_uvm_fault_force_sysmem_set() || uvm_hmm_must_use_sysmem(va_block, va_block_context)) { *read_duplicate = false; return UVM_ID_CPU; } @@ -8990,6 +9332,7 @@ static uvm_processor_id_t block_select_residency(uvm_va_block_t *va_block, } uvm_processor_id_t uvm_va_block_select_residency(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, uvm_page_index_t page_index, uvm_processor_id_t processor_id, NvU32 access_type_mask, @@ -8998,14 +9341,24 @@ uvm_processor_id_t uvm_va_block_select_residency(uvm_va_block_t *va_block, uvm_service_operation_t operation, bool *read_duplicate) { - uvm_processor_id_t id = block_select_residency(va_block, - page_index, - processor_id, - access_type_mask, - policy, - thrashing_hint, - operation, - read_duplicate); + uvm_processor_id_t id; + + UVM_ASSERT(uvm_va_block_check_policy_is_valid(va_block, + va_block_context->policy, + uvm_va_block_region_for_page(page_index))); + UVM_ASSERT(uvm_hmm_va_block_context_vma_is_valid(va_block, + va_block_context, + uvm_va_block_region_for_page(page_index))); + + id = block_select_residency(va_block, + va_block_context, + page_index, + processor_id, + access_type_mask, + policy, + thrashing_hint, + operation, + read_duplicate); // If the intended residency doesn't have memory, fall back to the CPU. if (!block_processor_has_memory(va_block, id)) { @@ -9035,32 +9388,13 @@ static bool check_access_counters_dont_revoke(uvm_va_block_t *block, return true; } -NV_STATUS uvm_va_block_service_locked(uvm_processor_id_t processor_id, - uvm_va_block_t *va_block, - uvm_va_block_retry_t *block_retry, - uvm_service_block_context_t *service_context) +// Update service_context->prefetch_hint, service_context->per_processor_masks, +// and service_context->region. +static void uvm_va_block_get_prefetch_hint(uvm_va_block_t *va_block, + uvm_service_block_context_t *service_context) { - NV_STATUS status = NV_OK; uvm_processor_id_t new_residency; - uvm_prot_t new_prot; - uvm_va_range_t *va_range = va_block->va_range; uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); - uvm_perf_prefetch_hint_t prefetch_hint = UVM_PERF_PREFETCH_HINT_NONE(); - uvm_processor_mask_t processors_involved_in_cpu_migration; - - uvm_assert_mutex_locked(&va_block->lock); - UVM_ASSERT(va_range->type == UVM_VA_RANGE_TYPE_MANAGED); - - // GPU fault servicing must be done under the VA space read lock. GPU fault - // servicing is required for RM to make forward progress, and we allow other - // threads to call into RM while holding the VA space lock in read mode. If - // we took the VA space lock in write mode on the GPU fault service path, - // we could deadlock because the thread in RM which holds the VA space lock - // for read wouldn't be able to complete until fault servicing completes. - if (service_context->operation != UVM_SERVICE_OPERATION_REPLAYABLE_FAULTS || UVM_ID_IS_CPU(processor_id)) - uvm_assert_rwsem_locked(&va_space->lock); - else - uvm_assert_rwsem_locked_read(&va_space->lock); // Performance heuristics policy: we only consider prefetching when there // are migrations to a single processor, only. @@ -9074,20 +9408,20 @@ NV_STATUS uvm_va_block_service_locked(uvm_processor_id_t processor_id, // Update prefetch tracking structure with the pages that will migrate // due to faults - uvm_perf_prefetch_prenotify_fault_migrations(va_block, - &service_context->block_context, - new_residency, - new_residency_mask, - service_context->region); - - prefetch_hint = uvm_perf_prefetch_get_hint(va_block, new_residency_mask); + uvm_perf_prefetch_get_hint(va_block, + &service_context->block_context, + new_residency, + new_residency_mask, + service_context->region, + &service_context->prefetch_bitmap_tree, + &service_context->prefetch_hint); // Obtain the prefetch hint and give a fake fault access type to the // prefetched pages - if (UVM_ID_IS_VALID(prefetch_hint.residency)) { - UVM_ASSERT(prefetch_hint.prefetch_pages_mask != NULL); + if (UVM_ID_IS_VALID(service_context->prefetch_hint.residency)) { + const uvm_page_mask_t *prefetch_pages_mask = &service_context->prefetch_hint.prefetch_pages_mask; - for_each_va_block_page_in_mask(page_index, prefetch_hint.prefetch_pages_mask, va_block) { + for_each_va_block_page_in_mask(page_index, prefetch_pages_mask, va_block) { UVM_ASSERT(!uvm_page_mask_test(new_residency_mask, page_index)); service_context->access_type[page_index] = UVM_FAULT_ACCESS_TYPE_PREFETCH; @@ -9102,9 +9436,43 @@ NV_STATUS uvm_va_block_service_locked(uvm_processor_id_t processor_id, } } - service_context->region = uvm_va_block_region_from_block(va_block); + uvm_page_mask_or(new_residency_mask, new_residency_mask, prefetch_pages_mask); + service_context->region = uvm_va_block_region_from_mask(va_block, new_residency_mask); } } + else { + service_context->prefetch_hint.residency = UVM_ID_INVALID; + } +} + +NV_STATUS uvm_va_block_service_locked(uvm_processor_id_t processor_id, + uvm_va_block_t *va_block, + uvm_va_block_retry_t *block_retry, + uvm_service_block_context_t *service_context) +{ + NV_STATUS status = NV_OK; + uvm_processor_id_t new_residency; + uvm_prot_t new_prot; + uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); + uvm_processor_mask_t processors_involved_in_cpu_migration; + + uvm_assert_mutex_locked(&va_block->lock); + UVM_ASSERT(uvm_va_block_check_policy_is_valid(va_block, + service_context->block_context.policy, + service_context->region)); + + // GPU fault servicing must be done under the VA space read lock. GPU fault + // servicing is required for RM to make forward progress, and we allow other + // threads to call into RM while holding the VA space lock in read mode. If + // we took the VA space lock in write mode on the GPU fault service path, + // we could deadlock because the thread in RM which holds the VA space lock + // for read wouldn't be able to complete until fault servicing completes. + if (service_context->operation != UVM_SERVICE_OPERATION_REPLAYABLE_FAULTS || UVM_ID_IS_CPU(processor_id)) + uvm_assert_rwsem_locked(&va_space->lock); + else + uvm_assert_rwsem_locked_read(&va_space->lock); + + uvm_va_block_get_prefetch_hint(va_block, service_context); for (new_prot = UVM_PROT_READ_ONLY; new_prot < UVM_PROT_MAX; ++new_prot) service_context->mappings_by_prot[new_prot-1].count = 0; @@ -9137,11 +9505,10 @@ NV_STATUS uvm_va_block_service_locked(uvm_processor_id_t processor_id, uvm_page_mask_zero(did_migrate_mask); uvm_processor_mask_zero(all_involved_processors); - if (UVM_ID_IS_VALID(prefetch_hint.residency)) { - UVM_ASSERT(uvm_id_equal(prefetch_hint.residency, new_residency)); - UVM_ASSERT(prefetch_hint.prefetch_pages_mask != NULL); + if (UVM_ID_IS_VALID(service_context->prefetch_hint.residency)) { + UVM_ASSERT(uvm_id_equal(service_context->prefetch_hint.residency, new_residency)); - uvm_page_mask_or(new_residency_mask, new_residency_mask, prefetch_hint.prefetch_pages_mask); + uvm_page_mask_or(new_residency_mask, new_residency_mask, &service_context->prefetch_hint.prefetch_pages_mask); } if (service_context->read_duplicate_count == 0 || @@ -9156,7 +9523,7 @@ NV_STATUS uvm_va_block_service_locked(uvm_processor_id_t processor_id, service_context->read_duplicate_count == 0? new_residency_mask: &service_context->block_context.caller_page_mask, - prefetch_hint.prefetch_pages_mask, + &service_context->prefetch_hint.prefetch_pages_mask, cause); if (status != NV_OK) return status; @@ -9172,7 +9539,7 @@ NV_STATUS uvm_va_block_service_locked(uvm_processor_id_t processor_id, new_residency, service_context->region, &service_context->block_context.caller_page_mask, - prefetch_hint.prefetch_pages_mask, + &service_context->prefetch_hint.prefetch_pages_mask, cause); if (status != NV_OK) return status; @@ -9193,6 +9560,7 @@ NV_STATUS uvm_va_block_service_locked(uvm_processor_id_t processor_id, // the new residency for_each_va_block_page_in_region_mask(page_index, new_residency_mask, service_context->region) { new_prot = compute_new_permission(va_block, + &service_context->block_context, page_index, processor_id, new_residency, @@ -9465,6 +9833,65 @@ NV_STATUS uvm_va_block_service_locked(uvm_processor_id_t processor_id, return NV_OK; } +NV_STATUS uvm_va_block_check_logical_permissions(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t processor_id, + uvm_page_index_t page_index, + uvm_fault_type_t access_type, + bool allow_migration) +{ + uvm_va_range_t *va_range = va_block->va_range; + uvm_prot_t access_prot = uvm_fault_access_type_to_prot(access_type); + + UVM_ASSERT(uvm_va_block_check_policy_is_valid(va_block, + va_block_context->policy, + uvm_va_block_region_for_page(page_index))); + UVM_ASSERT(uvm_hmm_va_block_context_vma_is_valid(va_block, + va_block_context, + uvm_va_block_region_for_page(page_index))); + + // CPU permissions are checked later by block_map_cpu_page. + // + // TODO: Bug 1766124: permissions are checked by block_map_cpu_page because + // it can also be called from change_pte. Make change_pte call this + // function and only check CPU permissions here. + if (UVM_ID_IS_GPU(processor_id)) { + if (va_range && uvm_va_range_is_managed_zombie(va_range)) + return NV_ERR_INVALID_ADDRESS; + + // GPU faults only check vma permissions if a mm is registered with the + // VA space (ie. uvm_va_space_mm_retain_lock(va_space) != NULL) or if + // uvm_enable_builtin_tests is set, because the Linux kernel can change + // vm_flags at any moment (for example on mprotect) and here we are not + // guaranteed to have vma->vm_mm->mmap_lock. During tests we ensure that + // this scenario does not happen. + if ((va_block_context->mm || uvm_enable_builtin_tests) && + (access_prot > compute_logical_prot(va_block, va_block_context, page_index))) + return NV_ERR_INVALID_ACCESS_TYPE; + } + + // Non-migratable range: + // - CPU accesses are always fatal, regardless of the VA range residency + // - GPU accesses are fatal if the GPU can't map the preferred location + if (!allow_migration) { + UVM_ASSERT(!uvm_va_block_is_hmm(va_block)); + + if (UVM_ID_IS_CPU(processor_id)) { + return NV_ERR_INVALID_OPERATION; + } + else { + uvm_va_space_t *va_space = va_range->va_space; + + return uvm_processor_mask_test( + &va_space->accessible_from[uvm_id_value(uvm_va_range_get_policy(va_range)->preferred_location)], + processor_id)? + NV_OK : NV_ERR_INVALID_ACCESS_TYPE; + } + } + + return NV_OK; +} + // Check if we are faulting on a page with valid permissions to check if we can // skip fault handling. See uvm_va_block_t::cpu::fault_authorized for more // details @@ -9528,19 +9955,6 @@ static NV_STATUS block_cpu_fault_locked(uvm_va_block_t *va_block, UVM_ASSERT(fault_addr >= va_block->start); UVM_ASSERT(fault_addr <= va_block->end); - // There are up to three mm_structs to worry about, and they might all be - // different: - // - // 1) vma->vm_mm - // 2) current->mm - // 3) va_space->va_space_mm.mm (though note that if this is valid, then it - // must match vma->vm_mm). - // - // The kernel guarantees that vma->vm_mm has a reference taken with - // mmap_lock held on the CPU fault path, so tell the fault handler to use - // that one. current->mm might differ if we're on the access_process_vm - // (ptrace) path or if another driver is calling get_user_pages. - service_context->block_context.mm = uvm_va_range_vma(va_range)->vm_mm; uvm_assert_mmap_lock_locked(service_context->block_context.mm); service_context->block_context.policy = uvm_va_policy_get(va_block, fault_addr); @@ -9556,8 +9970,11 @@ static NV_STATUS block_cpu_fault_locked(uvm_va_block_t *va_block, } // Check logical permissions - status = uvm_va_range_check_logical_permissions(va_block->va_range, + page_index = uvm_va_block_cpu_page_index(va_block, fault_addr); + status = uvm_va_block_check_logical_permissions(va_block, + &service_context->block_context, UVM_ID_CPU, + page_index, fault_access_type, uvm_range_group_address_migratable(va_space, fault_addr)); if (status != NV_OK) @@ -9565,7 +9982,6 @@ static NV_STATUS block_cpu_fault_locked(uvm_va_block_t *va_block, uvm_processor_mask_zero(&service_context->cpu_fault.gpus_to_check_for_ecc); - page_index = uvm_va_block_cpu_page_index(va_block, fault_addr); if (skip_cpu_fault_with_valid_permissions(va_block, page_index, fault_access_type)) return NV_OK; @@ -9588,6 +10004,7 @@ static NV_STATUS block_cpu_fault_locked(uvm_va_block_t *va_block, // Compute new residency and update the masks new_residency = uvm_va_block_select_residency(va_block, + &service_context->block_context, page_index, UVM_ID_CPU, uvm_fault_access_type_mask_bit(fault_access_type), @@ -9689,7 +10106,6 @@ NV_STATUS uvm_va_block_find(uvm_va_space_t *va_space, NvU64 addr, uvm_va_block_t } NV_STATUS uvm_va_block_find_create(uvm_va_space_t *va_space, - struct mm_struct *mm, NvU64 addr, uvm_va_block_context_t *va_block_context, uvm_va_block_t **out_block) @@ -9697,9 +10113,12 @@ NV_STATUS uvm_va_block_find_create(uvm_va_space_t *va_space, uvm_va_range_t *va_range; size_t index; + if (uvm_enable_builtin_tests && atomic_dec_if_positive(&va_space->test.va_block_allocation_fail_nth) == 0) + return NV_ERR_NO_MEMORY; + va_range = uvm_va_range_find(va_space, addr); if (!va_range) { - if (!mm) + if (!va_block_context || !va_block_context->mm) return NV_ERR_INVALID_ADDRESS; return uvm_hmm_va_block_find_create(va_space, addr, va_block_context, out_block); } @@ -9738,6 +10157,8 @@ NV_STATUS uvm_va_block_write_from_cpu(uvm_va_block_t *va_block, if (UVM_ID_IS_INVALID(proc)) proc = UVM_ID_CPU; + block_context->policy = uvm_va_policy_get(va_block, dst); + // Use make_resident() in all cases to break read-duplication, but // block_retry can be NULL as if the page is not resident yet we will make // it resident on the CPU. @@ -10222,12 +10643,19 @@ NV_STATUS uvm_test_va_block_inject_error(UVM_TEST_VA_BLOCK_INJECT_ERROR_PARAMS * struct mm_struct *mm; uvm_va_block_t *va_block; uvm_va_block_test_t *va_block_test; + uvm_va_block_context_t *block_context = NULL; NV_STATUS status = NV_OK; - mm = uvm_va_space_mm_retain_lock(va_space); + mm = uvm_va_space_mm_or_current_retain_lock(va_space); uvm_va_space_down_read(va_space); - status = uvm_va_block_find_create(va_space, mm, params->lookup_address, NULL, &va_block); + block_context = uvm_va_block_context_alloc(mm); + if (!block_context) { + status = NV_ERR_NO_MEMORY; + goto out; + } + + status = uvm_va_block_find_create(va_space, params->lookup_address, block_context, &va_block); if (status != NV_OK) goto out; @@ -10248,8 +10676,8 @@ NV_STATUS uvm_test_va_block_inject_error(UVM_TEST_VA_BLOCK_INJECT_ERROR_PARAMS * if (params->eviction_error) va_block_test->inject_eviction_error = params->eviction_error; - if (params->cpu_pages_allocation_error) - va_block_test->inject_cpu_pages_allocation_error = params->cpu_pages_allocation_error; + if (params->cpu_pages_allocation_error_count) + va_block_test->inject_cpu_pages_allocation_error_count = params->cpu_pages_allocation_error_count; if (params->populate_error) va_block_test->inject_populate_error = params->populate_error; @@ -10258,7 +10686,8 @@ NV_STATUS uvm_test_va_block_inject_error(UVM_TEST_VA_BLOCK_INJECT_ERROR_PARAMS * out: uvm_va_space_up_read(va_space); - uvm_va_space_mm_release_unlock(va_space, mm); + uvm_va_space_mm_or_current_release_unlock(va_space, mm); + uvm_va_block_context_free(block_context); return status; } @@ -10329,7 +10758,7 @@ NV_STATUS uvm_test_change_pte_mapping(UVM_TEST_CHANGE_PTE_MAPPING_PARAMS *params goto out; } - status = uvm_va_block_find_create(va_space, mm, params->va, block_context, &block); + status = uvm_va_block_find_create(va_space, params->va, block_context, &block); if (status != NV_OK) goto out; diff --git a/kernel-open/nvidia-uvm/uvm_va_block.h b/kernel-open/nvidia-uvm/uvm_va_block.h index e5858d920..f4b847b78 100644 --- a/kernel-open/nvidia-uvm/uvm_va_block.h +++ b/kernel-open/nvidia-uvm/uvm_va_block.h @@ -249,7 +249,7 @@ struct uvm_va_block_struct // Lock protecting the block. See the comment at the top of uvm.c. uvm_mutex_t lock; - // Parent VA range. UVM managed blocks have this set. HMM blocks will have + // Parent VA range. Managed blocks have this set. HMM blocks will have // va_range set to NULL and hmm.va_space set instead. Dead blocks that are // waiting for the last ref count to be removed have va_range and // hmm.va_space set to NULL (could be either type of block). @@ -437,13 +437,22 @@ struct uvm_va_block_struct uvm_perf_module_data_desc_t perf_modules_data[UVM_PERF_MODULE_TYPE_COUNT]; + // Prefetch infomation that is updated while holding the va_block lock but + // records state while the lock is not held. + struct + { + uvm_processor_id_t last_migration_proc_id; + + NvU16 fault_migrations_to_last_proc; + } prefetch_info; + #if UVM_IS_CONFIG_HMM() struct { // The MMU notifier is registered per va_block. struct mmu_interval_notifier notifier; - // Parent VA space pointer. It is NULL for UVM managed blocks or if + // Parent VA space pointer. It is NULL for managed blocks or if // the HMM block is dead. This field can be read while holding the // block lock and is only modified while holding the va_space write // lock and va_block lock (same as the va_range pointer). @@ -488,21 +497,27 @@ struct uvm_va_block_wrapper_struct // uvm_cpu_chunk_allocation_sizes module parameter. NvU32 cpu_chunk_allocation_size_mask; - // Force the next eviction attempt on this block to fail. Used for - // testing only. - bool inject_eviction_error; - // Subsequent operations that need to allocate CPU pages will fail. As - // opposed to other error injection settings, this one is persistent. + // opposed to other error injection settings, this one fails N times + // and then succeeds instead of failing on the Nth try. A value of ~0u + // means fail indefinitely. // This is because this error is supposed to be fatal and tests verify // the state of the VA blocks after the failure. However, some tests // use kernels to trigger migrations and a fault replay could trigger // a successful migration if this error flag is cleared. - bool inject_cpu_pages_allocation_error; + NvU32 inject_cpu_pages_allocation_error_count; + + // Force the next eviction attempt on this block to fail. Used for + // testing only. + bool inject_eviction_error; // Force the next successful chunk allocation to then fail. Used for testing // only to simulate driver metadata allocation failure. bool inject_populate_error; + + // Force the next split on this block to fail. + // Set by error injection ioctl for testing purposes only. + bool inject_split_error; } test; }; @@ -639,8 +654,18 @@ static void uvm_va_block_context_init(uvm_va_block_context_t *va_block_context, memset(va_block_context, 0xff, sizeof(*va_block_context)); va_block_context->mm = mm; +#if UVM_IS_CONFIG_HMM() + va_block_context->hmm.vma = NULL; +#endif } +// Check that a single policy covers the given region for the given va_block. +// This always returns true and is intended to only be used with UVM_ASSERT(). +// Locking: the va_block lock must be held. +bool uvm_va_block_check_policy_is_valid(uvm_va_block_t *va_block, + uvm_va_policy_t *policy, + uvm_va_block_region_t region); + // TODO: Bug 1766480: Using only page masks instead of a combination of regions // and page masks could simplify the below APIs and their implementations // at the cost of having to scan the whole mask for small regions. @@ -651,8 +676,10 @@ static void uvm_va_block_context_init(uvm_va_block_context_t *va_block_context, // pages in the region which are present in the mask. // // prefetch_page_mask may be passed as a subset of page_mask when cause is -// UVM_MAKE_RESIDENT_CAUSE_FAULT to indicate pages that have been pulled due -// to automatic page prefetching heuristics. For pages in this mask, +// UVM_MAKE_RESIDENT_CAUSE_REPLAYABLE_FAULT, +// UVM_MAKE_RESIDENT_CAUSE_NON_REPLAYABLE_FAULT, or +// UVM_MAKE_RESIDENT_CAUSE_ACCESS_COUNTER to indicate pages that have been +// pulled due to automatic page prefetching heuristics. For pages in this mask, // UVM_MAKE_RESIDENT_CAUSE_PREFETCH will be reported in migration events, // instead. // @@ -674,20 +701,24 @@ static void uvm_va_block_context_init(uvm_va_block_context_t *va_block_context, // block's lock has been unlocked and relocked as part of the call and that the // whole sequence of operations performed under the block's lock needs to be // attempted again. To facilitate that, the caller needs to provide the same -// va_block_retry struct for each attempt that has been initialized before the first -// attempt and needs to be deinitialized after the last one. Most callers can -// just use UVM_VA_BLOCK_LOCK_RETRY() that takes care of that for the caller. +// va_block_retry struct for each attempt that has been initialized before the +// first attempt and needs to be deinitialized after the last one. Most callers +// can just use UVM_VA_BLOCK_LOCK_RETRY() that takes care of that for the +// caller. // // If dest_id is the CPU then va_block_retry can be NULL and allocation-retry of // user memory is guaranteed not to happen. Allocation-retry of page tables can // still occur though. // -// va_block_context must be non-NULL. This function will set a bit in +// va_block_context must not be NULL. This function will set a bit in // va_block_context->make_resident.pages_changed_residency for each page that // changed residency (due to a migration or first population) as a result of the // operation. This function only sets bits in that mask. It is the caller's // responsiblity to zero the mask or not first. // +// va_block_context->policy must also be set by the caller for the given region. +// See the comments for uvm_va_block_check_policy_is_valid(). +// // Notably any status other than NV_OK indicates that the block's lock might // have been unlocked and relocked. // @@ -710,6 +741,8 @@ NV_STATUS uvm_va_block_make_resident(uvm_va_block_t *va_block, // where they are unmapped // - All remote mappings (due to either SetAccessedBy or performance heuristics) // are broken +// - Only managed va_blocks are supported. +// TODO: Bug 3660922: need to implement HMM read duplication support. // - LOCKING: If va_block_context->mm != NULL, va_block_context->mm->mmap_lock // must be held in at least read mode. NV_STATUS uvm_va_block_make_resident_read_duplicate(uvm_va_block_t *va_block, @@ -721,6 +754,34 @@ NV_STATUS uvm_va_block_make_resident_read_duplicate(uvm_va_block_t *va_block, const uvm_page_mask_t *prefetch_page_mask, uvm_make_resident_cause_t cause); +// Similar to uvm_va_block_make_resident() (read documentation there). The +// difference is that source pages are only copied to the destination and the +// residency is not updated until uvm_va_block_make_resident_post() is called. +// Otherwise, the combination of uvm_va_block_make_resident_pre() and +// uvm_va_block_make_resident_post() should be the same as just calling +// uvm_va_block_make_resident(). +// This split is needed when using migrate_vma_setup() and migrate_vma_pages() +// so that when migrate_vma_pages() indicates a page is not migrating, the +// va_block state is not updated. +// LOCKING: The caller must hold the va_block lock. +NV_STATUS uvm_va_block_make_resident_pre(uvm_va_block_t *va_block, + uvm_va_block_retry_t *va_block_retry, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t dest_id, + uvm_va_block_region_t region, + const uvm_page_mask_t *page_mask, + const uvm_page_mask_t *prefetch_page_mask, + uvm_make_resident_cause_t cause); + +// The page_mask must be the same or a subset of the page_mask passed to +// uvm_va_block_make_resident_pre(). This step updates the residency and breaks +// read duplication. +// LOCKING: The caller must hold the va_block lock. +void uvm_va_block_make_resident_post(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_va_block_region_t region, + const uvm_page_mask_t *page_mask); + // Creates or upgrades a mapping from the input processor to the given virtual // address region. Pages which already have new_prot permissions or higher are // skipped, so this call ensures that the range is mapped with at least new_prot @@ -749,7 +810,8 @@ NV_STATUS uvm_va_block_make_resident_read_duplicate(uvm_va_block_t *va_block, // pages because the earlier operation can cause a PTE split or merge which is // assumed by the later operation. // -// va_block_context must not be NULL. +// va_block_context must not be NULL and va_block_context->policy must be valid. +// See the comments for uvm_va_block_check_policy_is_valid(). // // If allocation-retry was required as part of the operation and was successful, // NV_ERR_MORE_PROCESSING_REQUIRED is returned. In this case, the entries in the @@ -805,7 +867,7 @@ NV_STATUS uvm_va_block_map_mask(uvm_va_block_t *va_block, // pages because the earlier operation can cause a PTE split or merge which is // assumed by the later operation. // -// va_block_context must not be NULL. +// va_block_context must not be NULL. The va_block_context->policy is unused. // // If allocation-retry was required as part of the operation and was successful, // NV_ERR_MORE_PROCESSING_REQUIRED is returned. In this case, the entries in the @@ -837,12 +899,20 @@ NV_STATUS uvm_va_block_unmap_mask(uvm_va_block_t *va_block, // up-to-date data. // - Unmap the preferred location's processor from any pages in this region // which are not resident on the preferred location. +// +// va_block_context must not be NULL and va_block_context->policy must be valid. +// See the comments for uvm_va_block_check_policy_is_valid(). +// // LOCKING: The caller must hold the VA block lock. NV_STATUS uvm_va_block_set_preferred_location_locked(uvm_va_block_t *va_block, uvm_va_block_context_t *va_block_context); // Maps the given processor to all resident pages in this block, as allowed by // location and policy. Waits for the operation to complete before returning. +// This function should only be called with managed va_blocks. +// +// va_block_context must not be NULL and va_block_context->policy must be valid. +// See the comments for uvm_va_block_check_policy_is_valid(). // // LOCKING: This takes and releases the VA block lock. If va_block_context->mm // != NULL, va_block_context->mm->mmap_lock must be held in at least @@ -852,8 +922,10 @@ NV_STATUS uvm_va_block_set_accessed_by(uvm_va_block_t *va_block, uvm_processor_id_t processor_id); // Breaks SetAccessedBy and remote mappings +// This function should only be called with managed va_blocks. // -// va_block_context must NOT be NULL +// va_block_context must not be NULL and va_block_context->policy must be valid. +// See the comments for uvm_va_block_check_policy_is_valid(). // // LOCKING: This takes and releases the VA block lock. If va_block_context->mm // != NULL, va_block_context->mm->mmap_lock must be held in at least @@ -862,8 +934,10 @@ NV_STATUS uvm_va_block_set_read_duplication(uvm_va_block_t *va_block, uvm_va_block_context_t *va_block_context); // Restores SetAccessedBy mappings +// This function should only be called with managed va_blocks. // -// va_block_context must NOT be NULL +// va_block_context must not be NULL and va_block_context->policy must be valid. +// See the comments for uvm_va_block_check_policy_is_valid(). // // LOCKING: This takes and releases the VA block lock. If va_block_context->mm // != NULL, va_block_context->mm->mmap_lock must be held in at least @@ -871,6 +945,29 @@ NV_STATUS uvm_va_block_set_read_duplication(uvm_va_block_t *va_block, NV_STATUS uvm_va_block_unset_read_duplication(uvm_va_block_t *va_block, uvm_va_block_context_t *va_block_context); +// Check if processor_id is allowed to access the va_block with access_type +// permissions. Return values: +// +// NV_ERR_INVALID_ADDRESS The VA block is logically dead (zombie) +// NV_ERR_INVALID_ACCESS_TYPE The vma corresponding to the VA range does not +// allow access_type permissions, or migration is +// disallowed and processor_id cannot access the +// range remotely (UVM-Lite). +// NV_ERR_INVALID_OPERATION The access would violate the policies specified +// by UvmPreventMigrationRangeGroups. +// +// va_block_context must not be NULL, va_block_context->policy must be valid, +// and if the va_block is a HMM block, va_block_context->hmm.vma must be valid +// which also means the va_block_context->mm is not NULL, retained, and locked +// for at least read. +// Locking: the va_block lock must be held. +NV_STATUS uvm_va_block_check_logical_permissions(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_processor_id_t processor_id, + uvm_page_index_t page_index, + uvm_fault_type_t access_type, + bool allow_migration); + // API for access privilege revocation // // Revoke prot_to_revoke access permissions for the given processor. @@ -898,7 +995,7 @@ NV_STATUS uvm_va_block_unset_read_duplication(uvm_va_block_t *va_block, // different pages because the earlier operation can cause a PTE split or merge // which is assumed by the later operation. // -// va_block_context must not be NULL. +// va_block_context must not be NULL. The va_block_context->policy is unused. // // If allocation-retry was required as part of the operation and was successful, // NV_ERR_MORE_PROCESSING_REQUIRED is returned. In this case, the entries in the @@ -938,7 +1035,8 @@ NV_STATUS uvm_va_block_revoke_prot_mask(uvm_va_block_t *va_block, // processor_id, which triggered the migration and should have already been // mapped). // -// va_block_context must not be NULL. +// va_block_context must not be NULL and va_block_context->policy must be valid. +// See the comments for uvm_va_block_check_policy_is_valid(). // // This function acquires/waits for the va_block tracker and updates that // tracker with any new work pushed. @@ -968,7 +1066,8 @@ NV_STATUS uvm_va_block_add_mappings_after_migration(uvm_va_block_t *va_block, // Note that this can return NV_ERR_MORE_PROCESSING_REQUIRED just like // uvm_va_block_map() indicating that the operation needs to be retried. // -// va_block_context must not be NULL. +// va_block_context must not be NULL and va_block_context->policy must be valid. +// See the comments for uvm_va_block_check_policy_is_valid(). // // LOCKING: The caller must hold the va block lock. If va_block_context->mm != // NULL, va_block_context->mm->mmap_lock must be held in at least read @@ -989,6 +1088,8 @@ NV_STATUS uvm_va_block_add_gpu_va_space(uvm_va_block_t *va_block, uvm_gpu_va_spa // If mm != NULL, that mm is used for any CPU mappings which may be created as // a result of this call. See uvm_va_block_context_t::mm for details. // +// va_block_context must not be NULL. The va_block_context->policy is unused. +// // LOCKING: The caller must hold the va_block lock. If block_context->mm is not // NULL, the caller must hold mm->mmap_lock in at least read mode. void uvm_va_block_remove_gpu_va_space(uvm_va_block_t *va_block, @@ -1057,10 +1158,7 @@ NV_STATUS uvm_va_block_split(uvm_va_block_t *existing_va_block, // Exactly the same split semantics as uvm_va_block_split, including error // handling except the existing_va_block block lock needs to be held and // the new_va_block has to be preallocated. -// -// new_va_block's va_range is set to new_va_range before any reverse mapping is -// established to the new block, but the caller is responsible for inserting the -// new block into the range. +// Also note that the existing_va_block lock may be dropped and re-acquired. NV_STATUS uvm_va_block_split_locked(uvm_va_block_t *existing_va_block, NvU64 new_end, uvm_va_block_t *new_va_block, @@ -1076,6 +1174,7 @@ NV_STATUS uvm_va_block_split_locked(uvm_va_block_t *existing_va_block, // - va_space lock must be held in at least read mode // // service_context->block_context.mm is ignored and vma->vm_mm is used instead. +// service_context->block_context.policy is set by this function. // // Returns NV_ERR_INVALID_ACCESS_TYPE if a CPU mapping to fault_addr cannot be // accessed, for example because it's within a range group which is non- @@ -1089,6 +1188,8 @@ NV_STATUS uvm_va_block_cpu_fault(uvm_va_block_t *va_block, // (migrations, cache invalidates, etc.) in response to the given service block // context // +// service_context->block_context.policy is set by this function. +// // Locking: // - service_context->block_context.mm->mmap_lock must be held in at least // read mode, if valid. @@ -1132,10 +1233,18 @@ static inline NvU64 uvm_va_block_cpu_page_address(uvm_va_block_t *block, uvm_pag return block->start + PAGE_SIZE * page_index; } +// Get the physical address on the given GPU for given residency +uvm_gpu_phys_address_t uvm_va_block_res_phys_page_address(uvm_va_block_t *va_block, + uvm_page_index_t page_index, + uvm_processor_id_t residency, + uvm_gpu_t *gpu); + // Get the page physical address on the given GPU // // This will assert that GPU state is indeed present. -uvm_gpu_phys_address_t uvm_va_block_gpu_phys_page_address(uvm_va_block_t *va_block, uvm_page_index_t page_index, uvm_gpu_t *gpu); +uvm_gpu_phys_address_t uvm_va_block_gpu_phys_page_address(uvm_va_block_t *va_block, + uvm_page_index_t page_index, + uvm_gpu_t *gpu); static bool uvm_va_block_contains_address(uvm_va_block_t *block, NvU64 address) { @@ -1191,26 +1300,28 @@ NV_STATUS uvm_va_block_find(uvm_va_space_t *va_space, NvU64 addr, uvm_va_block_t // Same as uvm_va_block_find except that the block is created if not found. // If addr is covered by a UVM_VA_RANGE_TYPE_MANAGED va_range, a managed block -// will be created. Otherwise, if addr is not covered by any va_range, mm is -// non-NULL, and HMM is enabled in the va_space, an HMM block will be created. -// In either case, if mm is non-NULL, it must be retained and locked in at -// least read mode. Return values: +// will be created. Otherwise, if addr is not covered by any va_range, HMM is +// enabled in the va_space, and va_block_context and va_block_context->mm are +// non-NULL, then a HMM block will be created and va_block_context->hmm.vma is +// set to the VMA covering 'addr'. The va_block_context->policy field is left +// unchanged. +// In either case, if va_block_context->mm is non-NULL, it must be retained and +// locked in at least read mode. Return values: // NV_ERR_INVALID_ADDRESS addr is not a UVM_VA_RANGE_TYPE_MANAGED va_range nor // a HMM enabled VMA. // NV_ERR_NO_MEMORY memory could not be allocated. NV_STATUS uvm_va_block_find_create(uvm_va_space_t *va_space, - struct mm_struct *mm, NvU64 addr, uvm_va_block_context_t *va_block_context, uvm_va_block_t **out_block); -// Same as uvm_va_block_find_create except that only UVM managed va_blocks are +// Same as uvm_va_block_find_create except that only managed va_blocks are // created if not already present in the VA range. static NV_STATUS uvm_va_block_find_create_managed(uvm_va_space_t *va_space, NvU64 addr, uvm_va_block_t **out_block) { - return uvm_va_block_find_create(va_space, NULL, addr, NULL, out_block); + return uvm_va_block_find_create(va_space, addr, NULL, out_block); } // Look up a chunk backing a specific address within the VA block. Returns NULL if none. @@ -1232,7 +1343,8 @@ typedef enum // The caller needs to handle allocation-retry. va_block_retry can be NULL if // the destination is the CPU. // -// va_block_context must not be NULL. +// va_block_context must not be NULL and va_block_context->policy must be valid. +// See the comments for uvm_va_block_check_policy_is_valid(). // // LOCKING: The caller must hold the va_block lock. If va_block_context->mm != // NULL, va_block_context->mm->mmap_lock must be held in at least @@ -1249,6 +1361,9 @@ NV_STATUS uvm_va_block_migrate_locked(uvm_va_block_t *va_block, // // The [dst, dst + size) range has to fit within a single PAGE_SIZE page. // +// va_block_context must not be NULL. The caller is not required to set +// va_block_context->policy. +// // The caller needs to support allocation-retry of page tables. // // LOCKING: The caller must hold the va_block lock @@ -1317,6 +1432,8 @@ void uvm_va_block_mark_cpu_dirty(uvm_va_block_t *va_block); // successful, NV_ERR_MORE_PROCESSING_REQUIRED is returned. In this case the // block's lock was unlocked and relocked. // +// va_block_context must not be NULL. The va_block_context->policy is unused. +// // LOCKING: The caller must hold the va_block lock. NV_STATUS uvm_va_block_set_cancel(uvm_va_block_t *va_block, uvm_va_block_context_t *block_context, uvm_gpu_t *gpu); @@ -1396,6 +1513,26 @@ static uvm_va_block_region_t uvm_va_block_region_from_block(uvm_va_block_t *va_b return uvm_va_block_region(0, uvm_va_block_num_cpu_pages(va_block)); } +// Create a block region from a va block and page mask. Note that the region +// covers the first through the last set bit and may have unset bits in between. +static uvm_va_block_region_t uvm_va_block_region_from_mask(uvm_va_block_t *va_block, const uvm_page_mask_t *page_mask) +{ + uvm_va_block_region_t region; + uvm_page_index_t outer = uvm_va_block_num_cpu_pages(va_block); + + region.first = find_first_bit(page_mask->bitmap, outer); + if (region.first >= outer) { + region = uvm_va_block_region(0, 0); + } + else { + // At least one bit is set so find_last_bit() should not return 'outer'. + region.outer = find_last_bit(page_mask->bitmap, outer) + 1; + UVM_ASSERT(region.outer <= outer); + } + + return region; +} + static bool uvm_page_mask_test(const uvm_page_mask_t *mask, uvm_page_index_t page_index) { UVM_ASSERT(page_index < PAGES_PER_UVM_VA_BLOCK); @@ -1715,61 +1852,6 @@ static NvU64 uvm_reverse_map_end(const uvm_reverse_map_t *reverse_map) #define for_each_va_block_page(page_index, va_block) \ for_each_va_block_page_in_region((page_index), uvm_va_block_region_from_block(va_block)) -static void uvm_va_block_bitmap_tree_init_from_page_count(uvm_va_block_bitmap_tree_t *bitmap_tree, size_t page_count) -{ - bitmap_tree->leaf_count = page_count; - bitmap_tree->level_count = ilog2(roundup_pow_of_two(page_count)) + 1; - uvm_page_mask_zero(&bitmap_tree->pages); -} - -static void uvm_va_block_bitmap_tree_init(uvm_va_block_bitmap_tree_t *bitmap_tree, uvm_va_block_t *va_block) -{ - size_t num_pages = uvm_va_block_num_cpu_pages(va_block); - uvm_va_block_bitmap_tree_init_from_page_count(bitmap_tree, num_pages); -} - -static void uvm_va_block_bitmap_tree_iter_init(const uvm_va_block_bitmap_tree_t *bitmap_tree, - uvm_page_index_t page_index, - uvm_va_block_bitmap_tree_iter_t *iter) -{ - UVM_ASSERT(bitmap_tree->level_count > 0); - UVM_ASSERT_MSG(page_index < bitmap_tree->leaf_count, - "%zd vs %zd", - (size_t)page_index, - (size_t)bitmap_tree->leaf_count); - - iter->level_idx = bitmap_tree->level_count - 1; - iter->node_idx = page_index; -} - -static uvm_va_block_region_t uvm_va_block_bitmap_tree_iter_get_range(const uvm_va_block_bitmap_tree_t *bitmap_tree, - const uvm_va_block_bitmap_tree_iter_t *iter) -{ - NvU16 range_leaves = uvm_perf_tree_iter_leaf_range(bitmap_tree, iter); - NvU16 range_start = uvm_perf_tree_iter_leaf_range_start(bitmap_tree, iter); - uvm_va_block_region_t subregion = uvm_va_block_region(range_start, range_start + range_leaves); - - UVM_ASSERT(iter->level_idx >= 0); - UVM_ASSERT(iter->level_idx < bitmap_tree->level_count); - - return subregion; -} - -static NvU16 uvm_va_block_bitmap_tree_iter_get_count(const uvm_va_block_bitmap_tree_t *bitmap_tree, - const uvm_va_block_bitmap_tree_iter_t *iter) -{ - uvm_va_block_region_t subregion = uvm_va_block_bitmap_tree_iter_get_range(bitmap_tree, iter); - - return uvm_page_mask_region_weight(&bitmap_tree->pages, subregion); -} - -#define uvm_va_block_bitmap_tree_traverse_counters(counter,tree,page,iter) \ - for (uvm_va_block_bitmap_tree_iter_init((tree), (page), (iter)), \ - (counter) = uvm_va_block_bitmap_tree_iter_get_count((tree), (iter)); \ - (iter)->level_idx >= 0; \ - (counter) = --(iter)->level_idx < 0? 0: \ - uvm_va_block_bitmap_tree_iter_get_count((tree), (iter))) - // Return the block region covered by the given chunk size. page_index must be // any page within the block known to be covered by the chunk. static uvm_va_block_region_t uvm_va_block_chunk_region(uvm_va_block_t *block, @@ -1898,6 +1980,12 @@ uvm_va_block_region_t uvm_va_block_big_page_region(uvm_va_block_t *va_block, // returned. uvm_va_block_region_t uvm_va_block_big_page_region_all(uvm_va_block_t *va_block, NvU32 big_page_size); +// Returns the largest sub-region region of 'region' which can fit big pages. +// If the region cannot fit any big pages, an invalid region (0, 0) is returned. +uvm_va_block_region_t uvm_va_block_big_page_region_subset(uvm_va_block_t *va_block, + uvm_va_block_region_t region, + NvU32 big_page_size); + // Returns the big page index (the bit index within // uvm_va_block_gpu_state_t::big_ptes) corresponding to page_index. If // page_index cannot be covered by a big PTE due to alignment or block size, @@ -1907,7 +1995,14 @@ size_t uvm_va_block_big_page_index(uvm_va_block_t *va_block, uvm_page_index_t pa // Returns the new residency for a page that faulted or triggered access // counter notifications. The read_duplicate output parameter indicates if the // page meets the requirements to be read-duplicated +// va_block_context must not be NULL, va_block_context->policy must be valid, +// and if the va_block is a HMM block, va_block_context->hmm.vma must be valid +// which also means the va_block_context->mm is not NULL, retained, and locked +// for at least read. See the comments for uvm_va_block_check_policy_is_valid() +// and uvm_hmm_va_block_context_vma_is_valid() in uvm_hmm.h. +// Locking: the va_block lock must be held. uvm_processor_id_t uvm_va_block_select_residency(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, uvm_page_index_t page_index, uvm_processor_id_t processor_id, NvU32 access_type_mask, diff --git a/kernel-open/nvidia-uvm/uvm_va_block_types.h b/kernel-open/nvidia-uvm/uvm_va_block_types.h index bda9a3062..8f5e233bb 100644 --- a/kernel-open/nvidia-uvm/uvm_va_block_types.h +++ b/kernel-open/nvidia-uvm/uvm_va_block_types.h @@ -75,28 +75,6 @@ typedef struct DECLARE_BITMAP(bitmap, PAGES_PER_UVM_VA_BLOCK); } uvm_page_mask_t; -// Encapsulates a counter tree built on top of a page mask bitmap in -// which each leaf represents a page in the block. It contains -// leaf_count and level_count so that it can use some macros for -// perf trees -typedef struct -{ - uvm_page_mask_t pages; - - NvU16 leaf_count; - - NvU8 level_count; -} uvm_va_block_bitmap_tree_t; - -// Iterator for the bitmap tree. It contains level_idx and node_idx so -// that it can use some macros for perf trees -typedef struct -{ - s8 level_idx; - - uvm_page_index_t node_idx; -} uvm_va_block_bitmap_tree_iter_t; - // When updating GPU PTEs, this struct describes the new arrangement of PTE // sizes. It is calculated before the operation is applied so we know which PTE // sizes to allocate. @@ -127,11 +105,6 @@ typedef struct // that region should be 4k, and that some of those 4k PTEs will be written // by the operation. DECLARE_BITMAP(big_ptes_covered, MAX_BIG_PAGES_PER_UVM_VA_BLOCK); - - // These are the big PTE regions which will no longer have any valid - // mappings after the operation. Only the bits which are set in - // big_ptes_covered are valid. - DECLARE_BITMAP(big_ptes_fully_unmapped, MAX_BIG_PAGES_PER_UVM_VA_BLOCK); } uvm_va_block_new_pte_state_t; // Event that triggered the call to uvm_va_block_make_resident/ @@ -269,7 +242,8 @@ typedef struct typedef enum { UVM_VA_BLOCK_TRANSFER_MODE_MOVE = 1, - UVM_VA_BLOCK_TRANSFER_MODE_COPY = 2 + UVM_VA_BLOCK_TRANSFER_MODE_COPY = 2, + UVM_VA_BLOCK_TRANSFER_MODE_COPY_ONLY = 3 } uvm_va_block_transfer_mode_t; struct uvm_reverse_map_struct diff --git a/kernel-open/nvidia-uvm/uvm_va_policy.c b/kernel-open/nvidia-uvm/uvm_va_policy.c index fd4e67b04..5efa1ca58 100644 --- a/kernel-open/nvidia-uvm/uvm_va_policy.c +++ b/kernel-open/nvidia-uvm/uvm_va_policy.c @@ -49,8 +49,9 @@ uvm_va_policy_t *uvm_va_policy_get(uvm_va_block_t *va_block, NvU64 addr) return node ? &node->policy : &uvm_va_policy_default; } - else + else { return uvm_va_range_get_policy(va_block->va_range); + } } #if UVM_IS_CONFIG_HMM() diff --git a/kernel-open/nvidia-uvm/uvm_va_policy.h b/kernel-open/nvidia-uvm/uvm_va_policy.h index 2d3159980..59963c515 100644 --- a/kernel-open/nvidia-uvm/uvm_va_policy.h +++ b/kernel-open/nvidia-uvm/uvm_va_policy.h @@ -50,7 +50,7 @@ typedef enum // // A policy covers one or more contiguous Linux VMAs or portion of a VMA and // does not cover non-existant VMAs. -// The VA range is determined from either the uvm_va_range_t for UVM managed +// The VA range is determined from either the uvm_va_range_t for managed // allocations or the uvm_va_policy_node_t for HMM allocations. // typedef struct uvm_va_policy_struct @@ -94,6 +94,12 @@ bool uvm_va_policy_is_read_duplicate(uvm_va_policy_t *policy, uvm_va_space_t *va // Locking: The va_block lock must be held. uvm_va_policy_t *uvm_va_policy_get(uvm_va_block_t *va_block, NvU64 addr); +// Return a uvm_va_policy_node_t given a uvm_va_policy_t pointer. +static uvm_va_policy_node_t *uvm_va_policy_node_from_policy(uvm_va_policy_t *policy) +{ + return container_of(policy, uvm_va_policy_node_t, policy); +} + #if UVM_IS_CONFIG_HMM() // Module load/exit @@ -239,6 +245,11 @@ static NV_STATUS uvm_va_policy_set_range(uvm_va_block_t *va_block, return NV_OK; } +static uvm_va_policy_node_t *uvm_va_policy_node_iter_first(uvm_va_block_t *va_block, NvU64 start, NvU64 end) +{ + return NULL; +} + #endif // UVM_IS_CONFIG_HMM() #endif // __UVM_VA_POLICY_H__ diff --git a/kernel-open/nvidia-uvm/uvm_va_range.c b/kernel-open/nvidia-uvm/uvm_va_range.c index f585aa2dc..e89edfbf0 100644 --- a/kernel-open/nvidia-uvm/uvm_va_range.c +++ b/kernel-open/nvidia-uvm/uvm_va_range.c @@ -1071,25 +1071,37 @@ static NV_STATUS uvm_va_range_split_blocks(uvm_va_range_t *existing, uvm_va_rang } // uvm_va_block_split gets first crack at injecting an error. If it did so, - // we wouldn't be here. However, not all splits will call uvm_va_block_split - // so we need an extra check here. We can't push this injection later since - // all paths past this point assume success, so they modify existing's - // state. + // we wouldn't be here. However, not all va_range splits will call + // uvm_va_block_split so we need an extra check here. We can't push this + // injection later since all paths past this point assume success, so they + // modify the state of 'existing' range. + // + // Even if there was no block split above, there is no guarantee that one + // of our blocks doesn't have the 'inject_split_error' flag set. We clear + // that here to prevent multiple errors caused by one + // 'uvm_test_va_range_inject_split_error' call. if (existing->inject_split_error) { UVM_ASSERT(!block); existing->inject_split_error = false; + + for_each_va_block_in_va_range(existing, block) { + uvm_va_block_test_t *block_test = uvm_va_block_get_test(block); + if (block_test) + block_test->inject_split_error = false; + } + return NV_ERR_NO_MEMORY; } existing_blocks = split_index + new_index; - // Copy existing's blocks over to new, accounting for the explicit + // Copy existing's blocks over to the new range, accounting for the explicit // assignment above in case we did a block split. There are two general // cases: // // No split: - // split_index - // v + // split_index + // v // existing (before) [----- A ----][----- B ----][----- C ----] // existing (after) [----- A ----] // new [----- B ----][----- C ----] @@ -1701,86 +1713,6 @@ void uvm_vma_wrapper_destroy(uvm_vma_wrapper_t *vma_wrapper) kmem_cache_free(g_uvm_vma_wrapper_cache, vma_wrapper); } -uvm_prot_t uvm_va_range_logical_prot(uvm_va_range_t *va_range) -{ - uvm_prot_t logical_prot; - struct vm_area_struct *vma; - - UVM_ASSERT(va_range); - UVM_ASSERT_MSG(va_range->type == UVM_VA_RANGE_TYPE_MANAGED, "type: %d\n", va_range->type); - - // Zombified VA ranges no longer have a vma, so they have no permissions - if (uvm_va_range_is_managed_zombie(va_range)) - return UVM_PROT_NONE; - - vma = uvm_va_range_vma(va_range); - - if (!(vma->vm_flags & VM_READ)) - logical_prot = UVM_PROT_NONE; - else if (!(vma->vm_flags & VM_WRITE)) - logical_prot = UVM_PROT_READ_ONLY; - else - logical_prot = UVM_PROT_READ_WRITE_ATOMIC; - - return logical_prot; -} - -static bool fault_check_range_permission(uvm_va_range_t *va_range, uvm_fault_access_type_t access_type) -{ - uvm_prot_t logical_prot = uvm_va_range_logical_prot(va_range); - uvm_prot_t fault_prot = uvm_fault_access_type_to_prot(access_type); - - return fault_prot <= logical_prot; -} - -NV_STATUS uvm_va_range_check_logical_permissions(uvm_va_range_t *va_range, - uvm_processor_id_t processor_id, - uvm_fault_type_t access_type, - bool allow_migration) -{ - // CPU permissions are checked later by block_map_cpu_page. - // - // TODO: Bug 1766124: permissions are checked by block_map_cpu_page because - // it can also be called from change_pte. Make change_pte call this - // function and only check CPU permissions here. - if (UVM_ID_IS_GPU(processor_id)) { - // Zombified VA ranges no longer have a vma, so they have no permissions - if (uvm_va_range_is_managed_zombie(va_range)) - return NV_ERR_INVALID_ADDRESS; - - // GPU faults only check vma permissions if uvm_enable_builtin_tests is - // set, because the Linux kernel can change vm_flags at any moment (for - // example on mprotect) and here we are not guaranteed to have - // vma->vm_mm->mmap_lock. During tests we ensure that this scenario - // does not happen - // - // TODO: Bug 1896799: On HMM/ATS we could look up the mm here and do - // this check safely. - if (uvm_enable_builtin_tests && !fault_check_range_permission(va_range, access_type)) - return NV_ERR_INVALID_ACCESS_TYPE; - } - - // Non-migratable range: - // - CPU accesses are always fatal, regardless of the VA range residency - // - GPU accesses are fatal if the GPU can't map the preferred location - if (!allow_migration) { - if (UVM_ID_IS_CPU(processor_id)) { - return NV_ERR_INVALID_OPERATION; - } - else { - uvm_processor_id_t preferred_location = uvm_va_range_get_policy(va_range)->preferred_location; - - return uvm_processor_mask_test(&va_range->va_space->accessible_from[uvm_id_value(preferred_location)], - processor_id) ? - NV_OK : NV_ERR_INVALID_ACCESS_TYPE; - } - } - - return NV_OK; -} - - - static NvU64 sked_reflected_pte_maker(uvm_page_table_range_vec_t *range_vec, NvU64 offset, void *caller_data) { (void)caller_data; @@ -1801,7 +1733,7 @@ static NV_STATUS uvm_map_sked_reflected_range(uvm_va_space_t *va_space, UVM_MAP_ return NV_ERR_INVALID_ADDRESS; // The mm needs to be locked in order to remove stale HMM va_blocks. - mm = uvm_va_space_mm_retain_lock(va_space); + mm = uvm_va_space_mm_or_current_retain_lock(va_space); uvm_va_space_down_write(va_space); gpu = uvm_va_space_get_gpu_by_uuid_with_gpu_va_space(va_space, ¶ms->gpuUuid); @@ -1856,7 +1788,7 @@ done: uvm_va_range_destroy(va_range, NULL); uvm_va_space_up_write(va_space); - uvm_va_space_mm_release_unlock(va_space, mm); + uvm_va_space_mm_or_current_release_unlock(va_space, mm); return status; } @@ -1888,7 +1820,7 @@ NV_STATUS uvm_api_alloc_semaphore_pool(UVM_ALLOC_SEMAPHORE_POOL_PARAMS *params, return NV_ERR_INVALID_ARGUMENT; // The mm needs to be locked in order to remove stale HMM va_blocks. - mm = uvm_va_space_mm_retain_lock(va_space); + mm = uvm_va_space_mm_or_current_retain_lock(va_space); uvm_va_space_down_write(va_space); status = uvm_va_range_create_semaphore_pool(va_space, @@ -1920,7 +1852,7 @@ done: unlock: uvm_va_space_up_write(va_space); - uvm_va_space_mm_release_unlock(va_space, mm); + uvm_va_space_mm_or_current_release_unlock(va_space, mm); return status; } @@ -1931,15 +1863,16 @@ NV_STATUS uvm_test_va_range_info(UVM_TEST_VA_RANGE_INFO_PARAMS *params, struct f uvm_processor_id_t processor_id; struct vm_area_struct *vma; NV_STATUS status = NV_OK; + struct mm_struct *mm; va_space = uvm_va_space_get(filp); - uvm_down_read_mmap_lock(current->mm); + mm = uvm_va_space_mm_or_current_retain_lock(va_space); uvm_va_space_down_read(va_space); va_range = uvm_va_range_find(va_space, params->lookup_address); if (!va_range) { - status = NV_ERR_INVALID_ADDRESS; + status = uvm_hmm_va_range_info(va_space, mm, params); goto out; } @@ -1976,18 +1909,21 @@ NV_STATUS uvm_test_va_range_info(UVM_TEST_VA_RANGE_INFO_PARAMS *params, struct f switch (va_range->type) { case UVM_VA_RANGE_TYPE_MANAGED: + + params->managed.subtype = UVM_TEST_RANGE_SUBTYPE_UVM; if (!va_range->managed.vma_wrapper) { params->managed.is_zombie = NV_TRUE; goto out; } params->managed.is_zombie = NV_FALSE; - vma = uvm_va_range_vma_current(va_range); + vma = uvm_va_range_vma_check(va_range, mm); if (!vma) { - // We aren't in the same mm as the one which owns the vma + // We aren't in the same mm as the one which owns the vma, and + // we don't have that mm locked. params->managed.owned_by_calling_process = NV_FALSE; goto out; } - params->managed.owned_by_calling_process = NV_TRUE; + params->managed.owned_by_calling_process = (mm == current->mm ? NV_TRUE : NV_FALSE); params->managed.vma_start = vma->vm_start; params->managed.vma_end = vma->vm_end - 1; break; @@ -1997,7 +1933,7 @@ NV_STATUS uvm_test_va_range_info(UVM_TEST_VA_RANGE_INFO_PARAMS *params, struct f out: uvm_va_space_up_read(va_space); - uvm_up_read_mmap_lock(current->mm); + uvm_va_space_mm_or_current_release_unlock(va_space, mm); return status; } @@ -2031,20 +1967,40 @@ NV_STATUS uvm_test_va_range_inject_split_error(UVM_TEST_VA_RANGE_INJECT_SPLIT_ER { uvm_va_space_t *va_space = uvm_va_space_get(filp); uvm_va_range_t *va_range; + struct mm_struct *mm; NV_STATUS status = NV_OK; + mm = uvm_va_space_mm_or_current_retain_lock(va_space); uvm_va_space_down_write(va_space); va_range = uvm_va_range_find(va_space, params->lookup_address); - if (!va_range || va_range->type != UVM_VA_RANGE_TYPE_MANAGED) { + if (!va_range) { + if (!mm) + status = NV_ERR_INVALID_ADDRESS; + else + status = uvm_hmm_test_va_block_inject_split_error(va_space, params->lookup_address); + } + else if (va_range->type != UVM_VA_RANGE_TYPE_MANAGED) { status = NV_ERR_INVALID_ADDRESS; - goto out; + } + else { + uvm_va_block_t *va_block; + size_t split_index; + + va_range->inject_split_error = true; + + split_index = uvm_va_range_block_index(va_range, params->lookup_address); + va_block = uvm_va_range_block(va_range, split_index); + if (va_block) { + uvm_va_block_test_t *block_test = uvm_va_block_get_test(va_block); + + if (block_test) + block_test->inject_split_error = true; + } } - va_range->inject_split_error = true; - -out: uvm_va_space_up_write(va_space); + uvm_va_space_mm_or_current_release_unlock(va_space, mm); return status; } diff --git a/kernel-open/nvidia-uvm/uvm_va_range.h b/kernel-open/nvidia-uvm/uvm_va_range.h index ee01863d2..3c4088454 100644 --- a/kernel-open/nvidia-uvm/uvm_va_range.h +++ b/kernel-open/nvidia-uvm/uvm_va_range.h @@ -141,7 +141,7 @@ typedef struct // process is sharing the UVM file descriptor. uvm_vma_wrapper_t *vma_wrapper; - // UVM managed allocations only use this policy and never use the policy + // Managed allocations only use this policy and never use the policy // stored in the va_block for HMM allocations. uvm_va_policy_t policy; @@ -851,24 +851,6 @@ NV_STATUS uvm_va_range_unset_read_duplication(uvm_va_range_t *va_range, struct m uvm_vma_wrapper_t *uvm_vma_wrapper_alloc(struct vm_area_struct *vma); void uvm_vma_wrapper_destroy(uvm_vma_wrapper_t *vma_wrapper); -// Return the memory access permissions for the vma bound to the given VA range -uvm_prot_t uvm_va_range_logical_prot(uvm_va_range_t *va_range); - -// Check if processor_id is allowed to access the managed va_range with -// access_type permissions. Return values: -// -// NV_ERR_INVALID_ADDRESS The VA range is logically dead (zombie) -// NV_ERR_INVALID_ACCESS_TYPE The vma corresponding to the VA range does not -// allow access_type permissions, or migration is -// disallowed and processor_id cannot access the -// range remotely (UVM-Lite). -// NV_ERR_INVALID_OPERATION The access would violate the policies specified -// by UvmPreventMigrationRangeGroups. -NV_STATUS uvm_va_range_check_logical_permissions(uvm_va_range_t *va_range, - uvm_processor_id_t processor_id, - uvm_fault_type_t access_type, - bool allow_migration); - static uvm_va_policy_t *uvm_va_range_get_policy(uvm_va_range_t *va_range) { UVM_ASSERT(va_range->type == UVM_VA_RANGE_TYPE_MANAGED); diff --git a/kernel-open/nvidia-uvm/uvm_va_space.c b/kernel-open/nvidia-uvm/uvm_va_space.c index 72790c784..ce1681d83 100644 --- a/kernel-open/nvidia-uvm/uvm_va_space.c +++ b/kernel-open/nvidia-uvm/uvm_va_space.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2021 NVIDIA Corporation + Copyright (c) 2015-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -930,7 +930,13 @@ NV_STATUS uvm_va_space_unregister_gpu(uvm_va_space_t *va_space, const NvProcesso uvm_processor_mask_clear(&va_space->gpu_unregister_in_progress, gpu->id); uvm_va_space_up_write(va_space); - uvm_va_space_mm_or_current_release_unlock(va_space, mm); + + // Unlock the mm since the call to uvm_deferred_free_object_list() requires + // that we don't hold any locks. We don't release the mm yet because that + // could call uvm_va_space_mm_shutdown() which waits for the deferred free + // list to be empty which would cause a deadlock. + if (mm) + uvm_up_read_mmap_lock(mm); uvm_deferred_free_object_list(&deferred_free_list); @@ -949,6 +955,8 @@ NV_STATUS uvm_va_space_unregister_gpu(uvm_va_space_t *va_space, const NvProcesso uvm_mutex_unlock(&g_uvm_global.global_lock); + uvm_va_space_mm_or_current_release(va_space, mm); + return NV_OK; } @@ -1611,11 +1619,20 @@ NV_STATUS uvm_va_space_unregister_gpu_va_space(uvm_va_space_t *va_space, const N } uvm_va_space_up_write(va_space); - uvm_va_space_mm_or_current_release_unlock(va_space, mm); + + // Unlock the mm since the call to uvm_deferred_free_object_list() requires + // that we don't hold any locks. We don't release the mm yet because that + // could call uvm_va_space_mm_shutdown() which waits for the deferred free + // list to be empty which would cause a deadlock. + if (mm) + uvm_up_read_mmap_lock(mm); uvm_deferred_free_object_list(&deferred_free_list); uvm_gpu_va_space_release(gpu_va_space); uvm_gpu_release(gpu); + + uvm_va_space_mm_or_current_release(va_space, mm); + return status; } @@ -1958,6 +1975,7 @@ NV_STATUS uvm_test_va_space_inject_error(UVM_TEST_VA_SPACE_INJECT_ERROR_PARAMS * uvm_va_space_t *va_space = uvm_va_space_get(filp); atomic_set(&va_space->test.migrate_vma_allocation_fail_nth, params->migrate_vma_allocation_fail_nth); + atomic_set(&va_space->test.va_block_allocation_fail_nth, params->va_block_allocation_fail_nth); return NV_OK; } @@ -2068,3 +2086,235 @@ NV_STATUS uvm_test_destroy_gpu_va_space_delay(UVM_TEST_DESTROY_GPU_VA_SPACE_DELA return NV_OK; } + +// List of fault service contexts for CPU faults +static LIST_HEAD(g_cpu_service_block_context_list); + +static uvm_spinlock_t g_cpu_service_block_context_list_lock; + +NV_STATUS uvm_service_block_context_init(void) +{ + unsigned num_preallocated_contexts = 4; + + uvm_spin_lock_init(&g_cpu_service_block_context_list_lock, UVM_LOCK_ORDER_LEAF); + + // Pre-allocate some fault service contexts for the CPU and add them to the global list + while (num_preallocated_contexts-- > 0) { + uvm_service_block_context_t *service_context = uvm_kvmalloc(sizeof(*service_context)); + if (!service_context) + return NV_ERR_NO_MEMORY; + + list_add(&service_context->cpu_fault.service_context_list, &g_cpu_service_block_context_list); + } + + return NV_OK; +} + +void uvm_service_block_context_exit(void) +{ + uvm_service_block_context_t *service_context, *service_context_tmp; + + // Free fault service contexts for the CPU and add clear the global list + list_for_each_entry_safe(service_context, service_context_tmp, &g_cpu_service_block_context_list, + cpu_fault.service_context_list) { + uvm_kvfree(service_context); + } + INIT_LIST_HEAD(&g_cpu_service_block_context_list); +} + +// Get a fault service context from the global list or allocate a new one if +// there are no available entries. +static uvm_service_block_context_t *service_block_context_cpu_alloc(void) +{ + uvm_service_block_context_t *service_context; + + uvm_spin_lock(&g_cpu_service_block_context_list_lock); + + service_context = list_first_entry_or_null(&g_cpu_service_block_context_list, uvm_service_block_context_t, + cpu_fault.service_context_list); + + if (service_context) + list_del(&service_context->cpu_fault.service_context_list); + + uvm_spin_unlock(&g_cpu_service_block_context_list_lock); + + if (!service_context) + service_context = uvm_kvmalloc(sizeof(*service_context)); + + return service_context; +} + +// Put a fault service context in the global list. +static void service_block_context_cpu_free(uvm_service_block_context_t *service_context) +{ + uvm_spin_lock(&g_cpu_service_block_context_list_lock); + + list_add(&service_context->cpu_fault.service_context_list, &g_cpu_service_block_context_list); + + uvm_spin_unlock(&g_cpu_service_block_context_list_lock); +} + +static vm_fault_t uvm_va_space_cpu_fault(uvm_va_space_t *va_space, + struct vm_area_struct *vma, + struct vm_fault *vmf, + bool is_hmm) +{ + uvm_va_block_t *va_block; + NvU64 fault_addr = nv_page_fault_va(vmf); + bool is_write = vmf->flags & FAULT_FLAG_WRITE; + NV_STATUS status = uvm_global_get_status(); + bool tools_enabled; + bool major_fault = false; + uvm_service_block_context_t *service_context; + uvm_global_processor_mask_t gpus_to_check_for_ecc; + + if (status != NV_OK) + goto convert_error; + + // TODO: Bug 2583279: Lock tracking is disabled for the power management + // lock in order to suppress reporting of a lock policy violation. + // The violation consists in acquiring the power management lock multiple + // times, and it is manifested as an error during release. The + // re-acquisition of the power management locks happens upon re-entry in the + // UVM module, and it is benign on itself, but when combined with certain + // power management scenarios, it is indicative of a potential deadlock. + // Tracking will be re-enabled once the power management locking strategy is + // modified to avoid deadlocks. + if (!uvm_down_read_trylock_no_tracking(&g_uvm_global.pm.lock)) { + status = NV_ERR_BUSY_RETRY; + goto convert_error; + } + + service_context = service_block_context_cpu_alloc(); + if (!service_context) { + status = NV_ERR_NO_MEMORY; + goto unlock; + } + + service_context->cpu_fault.wakeup_time_stamp = 0; + + // There are up to three mm_structs to worry about, and they might all be + // different: + // + // 1) vma->vm_mm + // 2) current->mm + // 3) va_space->va_space_mm.mm (though note that if this is valid, then it + // must match vma->vm_mm). + // + // The kernel guarantees that vma->vm_mm has a reference taken with + // mmap_lock held on the CPU fault path, so tell the fault handler to use + // that one. current->mm might differ if we're on the access_process_vm + // (ptrace) path or if another driver is calling get_user_pages. + service_context->block_context.mm = vma->vm_mm; + + // The mmap_lock might be held in write mode, but the mode doesn't matter + // for the purpose of lock ordering and we don't rely on it being in write + // anywhere so just record it as read mode in all cases. + uvm_record_lock_mmap_lock_read(vma->vm_mm); + + do { + bool do_sleep = false; + + if (status == NV_WARN_MORE_PROCESSING_REQUIRED) { + NvU64 now = NV_GETTIME(); + if (now < service_context->cpu_fault.wakeup_time_stamp) + do_sleep = true; + + if (do_sleep) + uvm_tools_record_throttling_start(va_space, fault_addr, UVM_ID_CPU); + + // Drop the VA space lock while we sleep + uvm_va_space_up_read(va_space); + + // usleep_range is preferred because msleep has a 20ms granularity + // and udelay uses a busy-wait loop. usleep_range uses + // high-resolution timers and, by adding a range, the Linux + // scheduler may coalesce our wakeup with others, thus saving some + // interrupts. + if (do_sleep) { + unsigned long nap_us = (service_context->cpu_fault.wakeup_time_stamp - now) / 1000; + + usleep_range(nap_us, nap_us + nap_us / 2); + } + } + + uvm_va_space_down_read(va_space); + + if (do_sleep) + uvm_tools_record_throttling_end(va_space, fault_addr, UVM_ID_CPU); + + if (!is_hmm) { + status = uvm_va_block_find_create_managed(va_space, fault_addr, &va_block); + if (status != NV_OK) { + UVM_ASSERT_MSG(status == NV_ERR_NO_MEMORY, "status: %s\n", nvstatusToString(status)); + break; + } + + // Watch out, current->mm might not be vma->vm_mm + UVM_ASSERT(vma == uvm_va_range_vma(va_block->va_range)); + } + + // Loop until thrashing goes away. + status = uvm_va_block_cpu_fault(va_block, fault_addr, is_write, service_context); + } while (status == NV_WARN_MORE_PROCESSING_REQUIRED); + + if (status != NV_OK) { + UvmEventFatalReason reason; + + reason = uvm_tools_status_to_fatal_fault_reason(status); + UVM_ASSERT(reason != UvmEventFatalReasonInvalid); + + uvm_tools_record_cpu_fatal_fault(va_space, fault_addr, is_write, reason); + } + + tools_enabled = va_space->tools.enabled; + + if (status == NV_OK) { + uvm_va_space_global_gpus_in_mask(va_space, + &gpus_to_check_for_ecc, + &service_context->cpu_fault.gpus_to_check_for_ecc); + uvm_global_mask_retain(&gpus_to_check_for_ecc); + } + + uvm_va_space_up_read(va_space); + uvm_record_unlock_mmap_lock_read(vma->vm_mm); + + if (status == NV_OK) { + status = uvm_global_mask_check_ecc_error(&gpus_to_check_for_ecc); + uvm_global_mask_release(&gpus_to_check_for_ecc); + } + + if (tools_enabled) + uvm_tools_flush_events(); + + // Major faults involve I/O in order to resolve the fault. + // If any pages were DMA'ed between the GPU and host memory, that makes it + // a major fault. A process can also get statistics for major and minor + // faults by calling readproc(). + major_fault = service_context->cpu_fault.did_migrate; + service_block_context_cpu_free(service_context); + +unlock: + // TODO: Bug 2583279: See the comment above the matching lock acquisition + uvm_up_read_no_tracking(&g_uvm_global.pm.lock); + +convert_error: + switch (status) { + case NV_OK: + case NV_ERR_BUSY_RETRY: + return VM_FAULT_NOPAGE | (major_fault ? VM_FAULT_MAJOR : 0); + case NV_ERR_NO_MEMORY: + return VM_FAULT_OOM; + default: + return VM_FAULT_SIGBUS; + } +} + +vm_fault_t uvm_va_space_cpu_fault_managed(uvm_va_space_t *va_space, + struct vm_area_struct *vma, + struct vm_fault *vmf) +{ + UVM_ASSERT(va_space == uvm_va_space_get(vma->vm_file)); + + return uvm_va_space_cpu_fault(va_space, vma, vmf, false); +} diff --git a/kernel-open/nvidia-uvm/uvm_va_space.h b/kernel-open/nvidia-uvm/uvm_va_space.h index 6ff843244..20f94e207 100644 --- a/kernel-open/nvidia-uvm/uvm_va_space.h +++ b/kernel-open/nvidia-uvm/uvm_va_space.h @@ -353,10 +353,14 @@ struct uvm_va_space_struct atomic_t migrate_vma_allocation_fail_nth; + atomic_t va_block_allocation_fail_nth; + uvm_thread_context_wrapper_t *dummy_thread_context_wrappers; size_t num_dummy_thread_context_wrappers; atomic64_t destroy_gpu_va_space_delay_us; + + atomic64_t split_invalidate_delay_us; } test; // Queue item for deferred f_ops->release() handling @@ -517,10 +521,10 @@ uvm_gpu_t *uvm_va_space_get_gpu_by_uuid_with_gpu_va_space(uvm_va_space_t *va_spa // LOCKING: The function takes and releases the VA space lock in read mode. uvm_gpu_t *uvm_va_space_retain_gpu_by_uuid(uvm_va_space_t *va_space, const NvProcessorUuid *gpu_uuid); -// Returns whether read-duplication is supported +// Returns whether read-duplication is supported. // If gpu is NULL, returns the current state. -// otherwise, it retuns what the result would be once the gpu's va space is added or removed -// (by inverting the gpu's current state) +// otherwise, it returns what the result would be once the gpu's va space is +// added or removed (by inverting the gpu's current state). bool uvm_va_space_can_read_duplicate(uvm_va_space_t *va_space, uvm_gpu_t *changing_gpu); // Register a gpu in the va space @@ -846,4 +850,22 @@ NV_STATUS uvm_test_get_pageable_mem_access_type(UVM_TEST_GET_PAGEABLE_MEM_ACCESS NV_STATUS uvm_test_enable_nvlink_peer_access(UVM_TEST_ENABLE_NVLINK_PEER_ACCESS_PARAMS *params, struct file *filp); NV_STATUS uvm_test_disable_nvlink_peer_access(UVM_TEST_DISABLE_NVLINK_PEER_ACCESS_PARAMS *params, struct file *filp); NV_STATUS uvm_test_destroy_gpu_va_space_delay(UVM_TEST_DESTROY_GPU_VA_SPACE_DELAY_PARAMS *params, struct file *filp); + +// Handle a CPU fault in the given VA space for a managed allocation, +// performing any operations necessary to establish a coherent CPU mapping +// (migrations, cache invalidates, etc.). +// +// Locking: +// - vma->vm_mm->mmap_lock must be held in at least read mode. Note, that +// might not be the same as current->mm->mmap_lock. +// Returns: +// VM_FAULT_NOPAGE: if page was faulted in OK +// (possibly or'ed with VM_FAULT_MAJOR if a migration was needed). +// VM_FAULT_OOM: if system memory wasn't available. +// VM_FAULT_SIGBUS: if a CPU mapping to fault_addr cannot be accessed, +// for example because it's within a range group which is non-migratable. +vm_fault_t uvm_va_space_cpu_fault_managed(uvm_va_space_t *va_space, + struct vm_area_struct *vma, + struct vm_fault *vmf); + #endif // __UVM_VA_SPACE_H__ diff --git a/kernel-open/nvidia-uvm/uvm_va_space_mm.c b/kernel-open/nvidia-uvm/uvm_va_space_mm.c index 5b63d3b90..cca3d5143 100644 --- a/kernel-open/nvidia-uvm/uvm_va_space_mm.c +++ b/kernel-open/nvidia-uvm/uvm_va_space_mm.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2018-2021 NVIDIA Corporation + Copyright (c) 2018-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -30,39 +30,41 @@ #include "uvm_test.h" #include "uvm_test_ioctl.h" +#if defined(NV_LINUX_SCHED_MM_H_PRESENT) +#include +#elif defined(NV_LINUX_SCHED_H_PRESENT) +#include +#endif + // // This comment block describes some implementation rationale. See the header // for the API descriptions. // // ========================= Retain count vs mm_users ========================== // -// uvm_va_space_mm manages its own retained ref count and wait queue. When the -// mm is disabled via mmu_notifier_release, we use the wait queue to wait for -// the ref count to go to 0. +// We use two methods to guarantee the mm is available and won't be destroyed. // -// An alternative is to scrap all that and just use mm_users. Retain would call -// something like mmget_not_zero(mm), and release would use mmput(). No -// additional count would be needed, since we'd be guaranteed that the mm_struct -// couldn't start teardown while we have the count. +// On the call paths where mmput() can be called, we call +// uvm_va_space_mm_or_current_retain() which calls mmget_not_zero(). This +// prevents mm teardown and avoids races with uvm_va_space_mm_shutdown() since +// it prevents mmput() -> __mmput() -> exit_mmap() -> mmu_notifier_release() -> +// uvm_va_space_mm_shutdown() until uvm_va_space_mm_or_current_release(), and +// we guarantee that we can't call uvm_va_space_mm_unregister() -> +// mmu_notifier_unregister() -> uvm_va_space_mm_shutdown() path when someone is +// about to call uvm_va_space_mm_or_current_retain(). +// Kernel calls like mmu_interval_notifier_insert() require mm_users to be +// greater than 0. In general, these are the ioctl paths. // -// There are two reasons we don't take that approach. The first is that we -// cannot call mmput() on all paths which retain a va_space_mm, particularly the -// GPU fault handler. mmput() may result in exit_mmap(), which could result in -// RM calls and VA space destroy. Those need to wait for the GPU fault handler -// to finish, so if we took that approach we'd deadlock. -// -// There is a recent mmput_async() addition to the kernel which would resolve -// this problem. As of v5.2 it was not exported for drivers, although that -// appears to be in the works. However, even if exported we would have to -// implement a fallback path for earlier kernels, and the complexity of such a -// path would be significant. -// -// The second problem is that mmget_not_zero() approach is susceptible to -// livelock problems. Two threads, say the fault handlers for two GPUs, could -// conceivably keep mm_users high by constantly retaining and releasing, -// preventing the mm from ever being torn down. The va_space_mm implementation -// below does not have this problem because mm shutdown causes later retains to -// fail, which guarantees that the count will eventually go to 0. +// On the replayable GPU fault handling path, we need the mm to be able to +// service faults in the window when mm_users == 0 but mmu_notifier_release() +// hasn't yet been called. We can't call mmput() because it may result in +// exit_mmap(), which could result in RM calls and VA space destroy. Those need +// to wait for the GPU fault handler to finish, so on that path we use an +// internal retained reference count and wait queue. When the mm is disabled +// via mmu_notifier_release(), we use the wait queue to wait for the reference +// count to go to 0. +// We also use this path for older Linux kernels where mm_users > 0 isn't +// required. // // ============================ Handling mm teardown =========================== // @@ -195,8 +197,20 @@ bool uvm_va_space_mm_enabled(uvm_va_space_t *va_space) static void uvm_va_space_mm_shutdown(uvm_va_space_t *va_space); +#if !defined(NV_MMGET_NOT_ZERO_PRESENT) +static bool mmget_not_zero(struct mm_struct *mm) +{ + return atomic_inc_not_zero(&mm->mm_users); +} +#endif + #if UVM_CAN_USE_MMU_NOTIFIERS() + static void uvm_mmput(struct mm_struct *mm) + { + mmput(mm); + } + static uvm_va_space_t *get_va_space(struct mmu_notifier *mn) { // This may be called without a thread context present, so be careful @@ -264,6 +278,11 @@ static void uvm_va_space_mm_shutdown(uvm_va_space_t *va_space); mmu_notifier_unregister(&va_space_mm->mmu_notifier, va_space_mm->mm); } #else + static void uvm_mmput(struct mm_struct *mm) + { + UVM_ASSERT(0); + } + static int uvm_mmu_notifier_register(uvm_va_space_mm_t *va_space_mm) { UVM_ASSERT(0); @@ -371,12 +390,12 @@ struct mm_struct *uvm_va_space_mm_or_current_retain(uvm_va_space_t *va_space) return NULL; // If the va_space_mm matches current->mm then it would be safe but sub- - // optimal to call uvm_va_space_mm_retain(). current->mm is always valid to + // optimal to call mmget_not_zero(). current->mm is always valid to // use when non-NULL so there is no need to retain it. if (!uvm_va_space_mm_enabled(va_space) || va_space_mm->mm == current->mm) return current->mm; - return uvm_va_space_mm_retain(va_space); + return mmget_not_zero(va_space_mm->mm) ? va_space_mm->mm : NULL; } void uvm_va_space_mm_release(uvm_va_space_t *va_space) @@ -408,8 +427,14 @@ void uvm_va_space_mm_release(uvm_va_space_t *va_space) void uvm_va_space_mm_or_current_release(uvm_va_space_t *va_space, struct mm_struct *mm) { + // We can't hold the VA space lock or mmap_lock across this function since + // mmput() may trigger uvm_va_space_mm_shutdown(), which takes those locks + // and also waits for other threads which may take those locks. + uvm_assert_unlocked_order(UVM_LOCK_ORDER_MMAP_LOCK); + uvm_assert_unlocked_order(UVM_LOCK_ORDER_VA_SPACE); + if (mm && mm != current->mm) - uvm_va_space_mm_release(va_space); + uvm_mmput(mm); } static void uvm_va_space_mm_shutdown_delay(uvm_va_space_t *va_space) @@ -587,14 +612,13 @@ static void uvm_va_space_mm_shutdown(uvm_va_space_t *va_space) static NV_STATUS mm_read64(struct mm_struct *mm, NvU64 addr, NvU64 *val) { long ret; - int write = 0, force = 0; struct page *page; NvU64 *mapping; UVM_ASSERT(IS_ALIGNED(addr, sizeof(*val))); uvm_down_read_mmap_lock(mm); - ret = NV_GET_USER_PAGES_REMOTE(NULL, mm, (unsigned long)addr, 1, write, force, &page, NULL); + ret = NV_PIN_USER_PAGES_REMOTE(mm, (unsigned long)addr, 1, 0, &page, NULL, NULL); uvm_up_read_mmap_lock(mm); if (ret < 0) @@ -605,7 +629,7 @@ static NV_STATUS mm_read64(struct mm_struct *mm, NvU64 addr, NvU64 *val) mapping = (NvU64 *)((char *)kmap(page) + (addr % PAGE_SIZE)); *val = *mapping; kunmap(page); - put_page(page); + NV_UNPIN_USER_PAGE(page); return NV_OK; } @@ -666,3 +690,33 @@ NV_STATUS uvm_test_va_space_mm_delay_shutdown(UVM_TEST_VA_SPACE_MM_DELAY_SHUTDOW return status; } + +NV_STATUS uvm_test_va_space_mm_or_current_retain(UVM_TEST_VA_SPACE_MM_OR_CURRENT_RETAIN_PARAMS *params, + struct file *filp) +{ + uvm_va_space_t *va_space = uvm_va_space_get(filp); + struct mm_struct *mm; + NV_STATUS status = NV_OK; + + mm = uvm_va_space_mm_or_current_retain(va_space); + if (!mm) + return NV_ERR_PAGE_TABLE_NOT_AVAIL; + + if (params->retain_done_ptr) { + NvU64 flag = true; + + if (nv_copy_to_user((void __user *)params->retain_done_ptr, &flag, sizeof(flag))) + status = NV_ERR_INVALID_ARGUMENT; + } + + if (status == NV_OK) { + if (params->sleep_us) + usleep_range(params->sleep_us, params->sleep_us + 1000); + + params->mm_users = atomic_read(&mm->mm_users); + } + + uvm_va_space_mm_or_current_release(va_space, mm); + + return status; +} diff --git a/kernel-open/nvidia-uvm/uvm_va_space_mm.h b/kernel-open/nvidia-uvm/uvm_va_space_mm.h index c866e16e8..c0a4dc7bb 100644 --- a/kernel-open/nvidia-uvm/uvm_va_space_mm.h +++ b/kernel-open/nvidia-uvm/uvm_va_space_mm.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2018-2021 NVIDIA Corporation + Copyright (c) 2018-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -95,8 +95,8 @@ bool uvm_va_space_mm_enabled(uvm_va_space_t *va_space); NV_STATUS uvm_va_space_mm_register(uvm_va_space_t *va_space); // De-associate the mm from the va_space. This function won't return until all -// in-flight retainers have called uvm_va_space_mm_release(). Subsequent calls -// to uvm_va_space_mm_retain() will return NULL. +// in-flight retainers have called uvm_va_space_mm_release(). +// uvm_va_space_mm_retain() and friends must not be called after this returns. // // This function may invoke uvm_va_space_mm_shutdown() so the caller must not // hold either mmap_lock or the VA space lock. Since this API must provide the @@ -128,10 +128,12 @@ struct mm_struct *uvm_va_space_mm_retain(uvm_va_space_t *va_space); // uvm_va_space_mm_or_current_retain(). // // If a non-NULL mm is returned, the guarantees described by -// uvm_va_space_mm_retain() apply. If uvm_va_space_mm_enabled() is false the -// caller is responsible for validating that the returned mm matches the desired -// mm before performing an operation such as vm_insert_page(). See -// uvm_va_range_vma_check(). +// uvm_va_space_mm_retain() apply. Unlike uvm_va_space_mm_retain() however, +// mm_users is guaranteed to be greater than 0 until +// uvm_va_space_mm_or_current_release(). +// If uvm_va_space_mm_enabled() is false, the caller is responsible for +// validating that the returned mm matches the desired mm before performing an +// operation such as vm_insert_page(). See uvm_va_range_vma_check(). // // This should not be called from a kernel thread. struct mm_struct *uvm_va_space_mm_or_current_retain(uvm_va_space_t *va_space); @@ -162,7 +164,9 @@ void uvm_va_space_mm_release(uvm_va_space_t *va_space); // Counterpart to uvm_va_space_mm_or_current_retain(). Must be called from the // same thread which called uvm_va_space_mm_or_current_retain(). mm may be NULL, -// in which case this is a no-op. +// in which case this is a no-op. This function may invoke +// uvm_va_space_mm_shutdown() so the caller must not hold either mmap_lock or +// the VA space lock. void uvm_va_space_mm_or_current_release(uvm_va_space_t *va_space, struct mm_struct *mm); static void uvm_va_space_mm_release_unlock(uvm_va_space_t *va_space, struct mm_struct *mm) @@ -175,12 +179,15 @@ static void uvm_va_space_mm_release_unlock(uvm_va_space_t *va_space, struct mm_s static void uvm_va_space_mm_or_current_release_unlock(uvm_va_space_t *va_space, struct mm_struct *mm) { - if (mm) + if (mm) { uvm_up_read_mmap_lock(mm); - uvm_va_space_mm_or_current_release(va_space, mm); + uvm_va_space_mm_or_current_release(va_space, mm); + } } NV_STATUS uvm_test_va_space_mm_retain(UVM_TEST_VA_SPACE_MM_RETAIN_PARAMS *params, struct file *filp); NV_STATUS uvm_test_va_space_mm_delay_shutdown(UVM_TEST_VA_SPACE_MM_DELAY_SHUTDOWN_PARAMS *params, struct file *filp); +NV_STATUS uvm_test_va_space_mm_or_current_retain(UVM_TEST_VA_SPACE_MM_OR_CURRENT_RETAIN_PARAMS *params, + struct file *filp); #endif // __UVM_VA_SPACE_MM_H__ diff --git a/kernel-open/nvidia/export_nvswitch.h b/kernel-open/nvidia/export_nvswitch.h index 489e87064..8d4ffb2ec 100644 --- a/kernel-open/nvidia/export_nvswitch.h +++ b/kernel-open/nvidia/export_nvswitch.h @@ -642,6 +642,12 @@ nvswitch_os_get_platform_time void ); +NvU64 +nvswitch_os_get_platform_time_epoch +( + void +); + #if (defined(_WIN32) || defined(_WIN64)) #define NVSWITCH_PRINT_ATTRIB(str, arg1) #else diff --git a/kernel-open/nvidia/linux_nvswitch.c b/kernel-open/nvidia/linux_nvswitch.c index 081d4474d..8cf1801ee 100644 --- a/kernel-open/nvidia/linux_nvswitch.c +++ b/kernel-open/nvidia/linux_nvswitch.c @@ -239,9 +239,6 @@ static long nvswitch_ctl_unlocked_ioctl(struct file *file, struct file_operations device_fops = { .owner = THIS_MODULE, -#if defined(NV_FILE_OPERATIONS_HAS_IOCTL) - .ioctl = nvswitch_device_ioctl, -#endif .unlocked_ioctl = nvswitch_device_unlocked_ioctl, .open = nvswitch_device_open, .release = nvswitch_device_release, @@ -251,9 +248,6 @@ struct file_operations device_fops = struct file_operations ctl_fops = { .owner = THIS_MODULE, -#if defined(NV_FILE_OPERATIONS_HAS_IOCTL) - .ioctl = nvswitch_ctl_ioctl, -#endif .unlocked_ioctl = nvswitch_ctl_unlocked_ioctl, }; @@ -574,6 +568,8 @@ nvswitch_deinit_device NVSWITCH_DEV *nvswitch_dev ) { + nvswitch_deinit_i2c_adapters(nvswitch_dev); + nvswitch_lib_disable_interrupts(nvswitch_dev->lib_device); nvswitch_shutdown_device_interrupt(nvswitch_dev); @@ -1452,16 +1448,12 @@ nvswitch_remove list_del(&nvswitch_dev->list_node); - nvswitch_deinit_i2c_adapters(nvswitch_dev); - - WARN_ON(!list_empty(&nvswitch_dev->i2c_adapter_list)); - - pci_set_drvdata(pci_dev, NULL); - nvswitch_deinit_background_tasks(nvswitch_dev); nvswitch_deinit_device(nvswitch_dev); + pci_set_drvdata(pci_dev, NULL); + pci_iounmap(pci_dev, nvswitch_dev->bar0); pci_release_regions(pci_dev); @@ -1822,8 +1814,7 @@ nvswitch_exit // // Get current time in seconds.nanoseconds -// In this implementation, the time is from epoch time -// (midnight UTC of January 1, 1970) +// In this implementation, the time is monotonic time // NvU64 nvswitch_os_get_platform_time @@ -1837,6 +1828,28 @@ nvswitch_os_get_platform_time return (NvU64) timespec64_to_ns(&ts); } +// +// Get current time in seconds.nanoseconds +// In this implementation, the time is from epoch time +// (midnight UTC of January 1, 1970). +// This implementation cannot be used for polling loops +// due to clock skew during system startup (bug 3302382, +// 3297170, 3273847, 3277478, 200693329). +// Instead, nvswitch_os_get_platform_time() is used +// for polling loops +// +NvU64 +nvswitch_os_get_platform_time_epoch +( + void +) +{ + struct timespec64 ts; + + ktime_get_real_ts64(&ts); + return (NvU64) timespec64_to_ns(&ts); +} + void nvswitch_os_print ( diff --git a/kernel-open/nvidia/nv-acpi.c b/kernel-open/nvidia/nv-acpi.c index 96e31faee..7db9db1d2 100644 --- a/kernel-open/nvidia/nv-acpi.c +++ b/kernel-open/nvidia/nv-acpi.c @@ -164,7 +164,7 @@ static void nv_acpi_powersource_hotplug_event(acpi_handle handle, u32 event_type if (nv_acpi_get_powersource(&ac_plugged) != NV_OK) return; - rm_system_event(pNvAcpiObject->sp, NV_SYSTEM_ACPI_BATTERY_POWER_EVENT, !ac_plugged); + rm_power_source_change_event(pNvAcpiObject->sp, !ac_plugged); } } /* diff --git a/kernel-open/nvidia/nv-caps.c b/kernel-open/nvidia/nv-caps.c index 673f8493e..7840414b4 100644 --- a/kernel-open/nvidia/nv-caps.c +++ b/kernel-open/nvidia/nv-caps.c @@ -62,6 +62,10 @@ static nv_cap_table_entry_t g_nv_cap_mig_table[] = {"/driver/nvidia/capabilities/mig/monitor"} }; +static nv_cap_table_entry_t g_nv_cap_sys_table[] = +{ +}; + #define NV_CAP_MIG_CI_ENTRIES(_gi) \ {_gi "/ci0/access"}, \ {_gi "/ci1/access"}, \ @@ -173,8 +177,6 @@ struct #define NV_CAP_NAME_BUF_SIZE 128 static struct proc_dir_entry *nv_cap_procfs_dir; -static struct proc_dir_entry *nv_cap_procfs_nvlink_minors; -static struct proc_dir_entry *nv_cap_procfs_mig_minors; static int nv_procfs_read_nvlink_minors(struct seq_file *s, void *v) { @@ -195,6 +197,25 @@ static int nv_procfs_read_nvlink_minors(struct seq_file *s, void *v) return 0; } +static int nv_procfs_read_sys_minors(struct seq_file *s, void *v) +{ + int i, count; + char name[NV_CAP_NAME_BUF_SIZE]; + + count = NV_CAP_NUM_ENTRIES(g_nv_cap_sys_table); + for (i = 0; i < count; i++) + { + if (sscanf(g_nv_cap_sys_table[i].name, + "/driver/nvidia/capabilities/%s", name) == 1) + { + name[sizeof(name) - 1] = '\0'; + seq_printf(s, "%s %d\n", name, g_nv_cap_sys_table[i].minor); + } + } + + return 0; +} + static int nv_procfs_read_mig_minors(struct seq_file *s, void *v) { int i, count, gpu; @@ -230,6 +251,8 @@ NV_DEFINE_SINGLE_PROCFS_FILE_READ_ONLY(nvlink_minors, nv_system_pm_lock); NV_DEFINE_SINGLE_PROCFS_FILE_READ_ONLY(mig_minors, nv_system_pm_lock); +NV_DEFINE_SINGLE_PROCFS_FILE_READ_ONLY(sys_minors, nv_system_pm_lock); + static void nv_cap_procfs_exit(void) { if (!nv_cap_procfs_dir) @@ -237,32 +260,39 @@ static void nv_cap_procfs_exit(void) return; } - nv_procfs_unregister_all(nv_cap_procfs_dir, nv_cap_procfs_dir); +#if defined(CONFIG_PROC_FS) + proc_remove(nv_cap_procfs_dir); +#endif nv_cap_procfs_dir = NULL; } int nv_cap_procfs_init(void) { + static struct proc_dir_entry *file_entry; + nv_cap_procfs_dir = NV_CREATE_PROC_DIR(NV_CAP_PROCFS_DIR, NULL); if (nv_cap_procfs_dir == NULL) { return -EACCES; } - nv_cap_procfs_mig_minors = NV_CREATE_PROC_FILE("mig-minors", - nv_cap_procfs_dir, - mig_minors, - NULL); - if (nv_cap_procfs_mig_minors == NULL) + file_entry = NV_CREATE_PROC_FILE("mig-minors", nv_cap_procfs_dir, + mig_minors, NULL); + if (file_entry == NULL) { goto cleanup; } - nv_cap_procfs_nvlink_minors = NV_CREATE_PROC_FILE("nvlink-minors", - nv_cap_procfs_dir, - nvlink_minors, - NULL); - if (nv_cap_procfs_nvlink_minors == NULL) + file_entry = NV_CREATE_PROC_FILE("nvlink-minors", nv_cap_procfs_dir, + nvlink_minors, NULL); + if (file_entry == NULL) + { + goto cleanup; + } + + file_entry = NV_CREATE_PROC_FILE("sys-minors", nv_cap_procfs_dir, + sys_minors, NULL); + if (file_entry == NULL) { goto cleanup; } @@ -320,6 +350,7 @@ static void nv_cap_tables_init(void) nv_cap_table_init(g_nv_cap_nvlink_table); nv_cap_table_init(g_nv_cap_mig_table); nv_cap_table_init(g_nv_cap_mig_gpu_table); + nv_cap_table_init(g_nv_cap_sys_table); } static ssize_t nv_cap_procfs_write(struct file *file, @@ -517,7 +548,7 @@ int NV_API_CALL nv_cap_validate_and_dup_fd(const nv_cap_t *cap, int fd) spin_lock(&files->file_lock); fdt = files_fdtable(files); - NV_SET_CLOSE_ON_EXEC(dup_fd, fdt); + __set_bit(dup_fd, fdt->close_on_exec); spin_unlock(&files->file_lock); } diff --git a/kernel-open/nvidia/nv-dma.c b/kernel-open/nvidia/nv-dma.c index 8d66b6139..f6d1a5a94 100644 --- a/kernel-open/nvidia/nv-dma.c +++ b/kernel-open/nvidia/nv-dma.c @@ -197,8 +197,7 @@ NV_STATUS nv_create_dma_map_scatterlist(nv_dma_map_t *dma_map) break; } -#if !defined(NV_SG_ALLOC_TABLE_FROM_PAGES_PRESENT) || \ - defined(NV_DOM0_KERNEL_PRESENT) +#if defined(NV_DOM0_KERNEL_PRESENT) { NvU64 page_idx = NV_DMA_SUBMAP_IDX_TO_PAGE_IDX(i); nv_fill_scatterlist(submap->sgt.sgl, @@ -774,14 +773,16 @@ static NvBool nv_dma_use_map_resource nv_dma_device_t *dma_dev ) { +#if defined(NV_DMA_MAP_RESOURCE_PRESENT) + const struct dma_map_ops *ops = get_dma_ops(dma_dev->dev); +#endif + if (nv_dma_remap_peer_mmio == NV_DMA_REMAP_PEER_MMIO_DISABLE) { return NV_FALSE; } #if defined(NV_DMA_MAP_RESOURCE_PRESENT) - const struct dma_map_ops *ops = get_dma_ops(dma_dev->dev); - if (ops == NULL) { /* On pre-5.0 kernels, if dma_map_resource() is present, then we diff --git a/kernel-open/nvidia/nv-dmabuf.c b/kernel-open/nvidia/nv-dmabuf.c index e28f37c3f..cb577a0d3 100644 --- a/kernel-open/nvidia/nv-dmabuf.c +++ b/kernel-open/nvidia/nv-dmabuf.c @@ -24,6 +24,15 @@ #include "nv-dmabuf.h" #if defined(CONFIG_DMA_SHARED_BUFFER) + +// +// The Linux kernel's dma_length in struct scatterlist is unsigned int +// which limits the maximum sg length to 4GB - 1. +// To get around this limitation, the BAR1 scatterlist returned by RM +// is split into (4GB - PAGE_SIZE) sized chunks to build the sg_table. +// +#define NV_DMA_BUF_SG_MAX_LEN ((NvU32)(NVBIT64(32) - PAGE_SIZE)) + typedef struct nv_dma_buf_mem_handle { NvHandle h_memory; @@ -77,24 +86,20 @@ nv_dma_buf_alloc_file_private( { nv_dma_buf_file_private_t *priv = NULL; - NV_KMALLOC(priv, sizeof(nv_dma_buf_file_private_t)); + NV_KZALLOC(priv, sizeof(nv_dma_buf_file_private_t)); if (priv == NULL) { return NULL; } - memset(priv, 0, sizeof(nv_dma_buf_file_private_t)); - mutex_init(&priv->lock); - NV_KMALLOC(priv->handles, num_handles * sizeof(priv->handles[0])); + NV_KZALLOC(priv->handles, num_handles * sizeof(priv->handles[0])); if (priv->handles == NULL) { goto failed; } - memset(priv->handles, 0, num_handles * sizeof(priv->handles[0])); - return priv; failed: @@ -257,26 +262,36 @@ nv_dma_buf_unmap_unlocked( nv_dma_device_t *peer_dma_dev, nv_dma_buf_file_private_t *priv, struct sg_table *sgt, - NvU32 count + NvU32 mapped_handle_count ) { NV_STATUS status; NvU32 i; NvU64 dma_len; NvU64 dma_addr; - NvU64 bar1_va; NvBool bar1_unmap_needed; struct scatterlist *sg = NULL; bar1_unmap_needed = (priv->bar1_va_ref_count == 0); - for_each_sg(sgt->sgl, sg, count, i) + sg = sgt->sgl; + for (i = 0; i < mapped_handle_count; i++) { - dma_addr = sg_dma_address(sg); - dma_len = priv->handles[i].size; - bar1_va = priv->handles[i].bar1_va; + NvU64 handle_size = priv->handles[i].size; - WARN_ON(sg_dma_len(sg) != priv->handles[i].size); + dma_addr = sg_dma_address(sg); + dma_len = 0; + + // + // Seek ahead in the scatterlist until the handle size is covered. + // IOVA unmap can then be done all at once instead of doing it + // one sg at a time. + // + while(handle_size != dma_len) + { + dma_len += sg_dma_len(sg); + sg = sg_next(sg); + } nv_dma_unmap_peer(peer_dma_dev, (dma_len / os_page_size), dma_addr); @@ -307,7 +322,8 @@ nv_dma_buf_map( nv_dma_device_t peer_dma_dev = {{ 0 }}; NvBool bar1_map_needed; NvBool bar1_unmap_needed; - NvU32 count = 0; + NvU32 mapped_handle_count = 0; + NvU32 num_sg_entries = 0; NvU32 i = 0; int rc = 0; @@ -352,20 +368,29 @@ nv_dma_buf_map( goto unlock_api_lock; } - NV_KMALLOC(sgt, sizeof(struct sg_table)); + NV_KZALLOC(sgt, sizeof(struct sg_table)); if (sgt == NULL) { goto unlock_gpu_lock; } - memset(sgt, 0, sizeof(struct sg_table)); + // + // Pre-calculate number of sg entries we need based on handle size. + // This is needed to allocate sg_table. + // + for (i = 0; i < priv->num_objects; i++) + { + NvU64 count = priv->handles[i].size + NV_DMA_BUF_SG_MAX_LEN - 1; + do_div(count, NV_DMA_BUF_SG_MAX_LEN); + num_sg_entries += count; + } // // RM currently returns contiguous BAR1, so we create as many - // sg entries as the number of handles being mapped. + // sg entries as num_sg_entries calculated above. // When RM can alloc discontiguous BAR1, this code will need to be revisited. // - rc = sg_alloc_table(sgt, priv->num_objects, GFP_KERNEL); + rc = sg_alloc_table(sgt, num_sg_entries, GFP_KERNEL); if (rc != 0) { goto free_sgt; @@ -375,7 +400,8 @@ nv_dma_buf_map( peer_dma_dev.addressable_range.limit = (NvU64)dev->dma_mask; bar1_map_needed = bar1_unmap_needed = (priv->bar1_va_ref_count == 0); - for_each_sg(sgt->sgl, sg, priv->num_objects, i) + sg = sgt->sgl; + for (i = 0; i < priv->num_objects; i++) { NvU64 dma_addr; NvU64 dma_len; @@ -393,9 +419,15 @@ nv_dma_buf_map( } } + mapped_handle_count++; + dma_addr = priv->handles[i].bar1_va; dma_len = priv->handles[i].size; + // + // IOVA map the full handle at once and then breakdown the range + // (dma_addr, dma_addr + dma_len) into smaller sg entries. + // status = nv_dma_map_peer(&peer_dma_dev, priv->nv->dma_dev, 0x1, (dma_len / os_page_size), &dma_addr); if (status != NV_OK) @@ -409,14 +441,23 @@ nv_dma_buf_map( priv->handles[i].bar1_va); } + mapped_handle_count--; + // Unmap remaining memory handles goto unmap_handles; } - sg_set_page(sg, NULL, dma_len, 0); - sg_dma_address(sg) = (dma_addr_t)dma_addr; - sg_dma_len(sg) = dma_len; - count++; + while(dma_len != 0) + { + NvU32 sg_len = NV_MIN(dma_len, NV_DMA_BUF_SG_MAX_LEN); + + sg_set_page(sg, NULL, sg_len, 0); + sg_dma_address(sg) = (dma_addr_t)dma_addr; + sg_dma_len(sg) = sg_len; + dma_addr += sg_len; + dma_len -= sg_len; + sg = sg_next(sg); + } } priv->bar1_va_ref_count++; @@ -432,7 +473,7 @@ nv_dma_buf_map( return sgt; unmap_handles: - nv_dma_buf_unmap_unlocked(sp, &peer_dma_dev, priv, sgt, count); + nv_dma_buf_unmap_unlocked(sp, &peer_dma_dev, priv, sgt, mapped_handle_count); sg_free_table(sgt); diff --git a/kernel-open/nvidia/nv-frontend.c b/kernel-open/nvidia/nv-frontend.c index b3dedd6e6..f5b871e6c 100644 --- a/kernel-open/nvidia/nv-frontend.c +++ b/kernel-open/nvidia/nv-frontend.c @@ -26,19 +26,11 @@ #include "nv-reg.h" #include "nv-frontend.h" -#if defined(MODULE_LICENSE) MODULE_LICENSE("Dual MIT/GPL"); -#endif -#if defined(MODULE_INFO) -MODULE_INFO(supported, "external"); -#endif -#if defined(MODULE_VERSION) -MODULE_VERSION(NV_VERSION_STRING); -#endif -#ifdef MODULE_ALIAS_CHARDEV_MAJOR +MODULE_INFO(supported, "external"); +MODULE_VERSION(NV_VERSION_STRING); MODULE_ALIAS_CHARDEV_MAJOR(NV_MAJOR_DEVICE_NUMBER); -#endif /* * MODULE_IMPORT_NS() is added by commit id 8651ec01daeda @@ -79,9 +71,6 @@ int nvidia_frontend_mmap(struct file *, struct vm_area_struct *); static struct file_operations nv_frontend_fops = { .owner = THIS_MODULE, .poll = nvidia_frontend_poll, -#if defined(NV_FILE_OPERATIONS_HAS_IOCTL) - .ioctl = nvidia_frontend_ioctl, -#endif .unlocked_ioctl = nvidia_frontend_unlocked_ioctl, #if NVCPU_IS_X86_64 || NVCPU_IS_AARCH64 .compat_ioctl = nvidia_frontend_compat_ioctl, diff --git a/kernel-open/nvidia/nv-i2c.c b/kernel-open/nvidia/nv-i2c.c index 0bfb18e9c..6fdf206a8 100644 --- a/kernel-open/nvidia/nv-i2c.c +++ b/kernel-open/nvidia/nv-i2c.c @@ -168,6 +168,17 @@ static int nv_i2c_algo_smbus_xfer( sizeof(data->block), (NvU8 *)data->block); break; + + case I2C_SMBUS_I2C_BLOCK_DATA: + rmStatus = rm_i2c_transfer(sp, nv, (void *)adapter, + (read_write == I2C_SMBUS_READ) ? + NV_I2C_CMD_BLOCK_READ : + NV_I2C_CMD_BLOCK_WRITE, + (NvU8)(addr & 0x7f), (NvU8)command, + (NvU8)data->block[0], + (NvU8 *)&data->block[1]); + break; + default: rc = -EINVAL; rmStatus = NV_ERR_INVALID_ARGUMENT; @@ -195,7 +206,8 @@ static u32 nv_i2c_algo_functionality(struct i2c_adapter *adapter) I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | - I2C_FUNC_SMBUS_BLOCK_DATA); + I2C_FUNC_SMBUS_BLOCK_DATA | + I2C_FUNC_SMBUS_I2C_BLOCK); } nv_kmem_cache_free_stack(sp); diff --git a/kernel-open/nvidia/nv-ibmnpu.c b/kernel-open/nvidia/nv-ibmnpu.c index fcf5dc45e..1926acf24 100644 --- a/kernel-open/nvidia/nv-ibmnpu.c +++ b/kernel-open/nvidia/nv-ibmnpu.c @@ -37,7 +37,6 @@ */ const NvU32 P9_L1D_CACHE_DEFAULT_BLOCK_SIZE = 0x80; -#if defined(NV_OF_GET_PROPERTY_PRESENT) static NvU32 nv_ibm_get_cpu_l1d_cache_block_size(void) { const __be32 *block_size_prop; @@ -60,12 +59,6 @@ static NvU32 nv_ibm_get_cpu_l1d_cache_block_size(void) return be32_to_cpu(*block_size_prop); } -#else -static NvU32 nv_ibm_get_cpu_l1d_cache_block_size(void) -{ - return P9_L1D_CACHE_DEFAULT_BLOCK_SIZE; -} -#endif /* * GPU device memory can be exposed to the kernel as NUMA node memory via the diff --git a/kernel-open/nvidia/nv-kthread-q.c b/kernel-open/nvidia/nv-kthread-q.c index 5a95f4a40..31a54cc05 100644 --- a/kernel-open/nvidia/nv-kthread-q.c +++ b/kernel-open/nvidia/nv-kthread-q.c @@ -169,7 +169,6 @@ void nv_kthread_q_stop(nv_kthread_q_t *q) // // This function is never invoked when there is no NUMA preference (preferred // node is NUMA_NO_NODE). -#if NV_KTHREAD_Q_SUPPORTS_AFFINITY() == 1 static struct task_struct *thread_create_on_node(int (*threadfn)(void *data), nv_kthread_q_t *q, int preferred_node, @@ -217,7 +216,6 @@ static struct task_struct *thread_create_on_node(int (*threadfn)(void *data), return thread[i]; } -#endif int nv_kthread_q_init_on_node(nv_kthread_q_t *q, const char *q_name, int preferred_node) { @@ -231,11 +229,7 @@ int nv_kthread_q_init_on_node(nv_kthread_q_t *q, const char *q_name, int preferr q->q_kthread = kthread_create(_main_loop, q, q_name); } else { -#if NV_KTHREAD_Q_SUPPORTS_AFFINITY() == 1 q->q_kthread = thread_create_on_node(_main_loop, q, preferred_node, q_name); -#else - return -ENOTSUPP; -#endif } if (IS_ERR(q->q_kthread)) { diff --git a/kernel-open/nvidia/nv-mmap.c b/kernel-open/nvidia/nv-mmap.c index 07a02e690..a67ea14cb 100644 --- a/kernel-open/nvidia/nv-mmap.c +++ b/kernel-open/nvidia/nv-mmap.c @@ -431,7 +431,7 @@ static int nvidia_mmap_numa( const nv_alloc_mapping_context_t *mmap_context) { NvU64 start, addr; - unsigned int pages; + NvU64 pages; NvU64 i; pages = NV_VMA_SIZE(vma) >> PAGE_SHIFT; @@ -680,13 +680,11 @@ int nvidia_mmap( return -EINVAL; } - down(&nvlfp->fops_sp_lock[NV_FOPS_STACK_INDEX_MMAP]); - - sp = nvlfp->fops_sp[NV_FOPS_STACK_INDEX_MMAP]; + sp = nv_nvlfp_get_sp(nvlfp, NV_FOPS_STACK_INDEX_MMAP); status = nvidia_mmap_helper(nv, nvlfp, sp, vma, NULL); - up(&nvlfp->fops_sp_lock[NV_FOPS_STACK_INDEX_MMAP]); + nv_nvlfp_put_sp(nvlfp, NV_FOPS_STACK_INDEX_MMAP); return status; } diff --git a/kernel-open/nvidia/nv-msi.c b/kernel-open/nvidia/nv-msi.c index 7efaeb4cb..a5a6a485b 100644 --- a/kernel-open/nvidia/nv-msi.c +++ b/kernel-open/nvidia/nv-msi.c @@ -36,7 +36,7 @@ void NV_API_CALL nv_init_msi(nv_state_t *nv) nv->interrupt_line = nvl->pci_dev->irq; nv->flags |= NV_FLAG_USES_MSI; nvl->num_intr = 1; - NV_KMALLOC(nvl->irq_count, sizeof(nv_irq_count_info_t) * nvl->num_intr); + NV_KZALLOC(nvl->irq_count, sizeof(nv_irq_count_info_t) * nvl->num_intr); if (nvl->irq_count == NULL) { @@ -47,7 +47,6 @@ void NV_API_CALL nv_init_msi(nv_state_t *nv) } else { - memset(nvl->irq_count, 0, sizeof(nv_irq_count_info_t) * nvl->num_intr); nvl->current_num_irq_tracked = 0; } } @@ -100,7 +99,7 @@ void NV_API_CALL nv_init_msix(nv_state_t *nv) msix_entries->entry = i; } - NV_KMALLOC(nvl->irq_count, sizeof(nv_irq_count_info_t) * num_intr); + NV_KZALLOC(nvl->irq_count, sizeof(nv_irq_count_info_t) * num_intr); if (nvl->irq_count == NULL) { @@ -109,7 +108,6 @@ void NV_API_CALL nv_init_msix(nv_state_t *nv) } else { - memset(nvl->irq_count, 0, sizeof(nv_irq_count_info_t) * num_intr); nvl->current_num_irq_tracked = 0; } rc = nv_pci_enable_msix(nvl, num_intr); diff --git a/kernel-open/nvidia/nv-nano-timer.c b/kernel-open/nvidia/nv-nano-timer.c new file mode 100644 index 000000000..453b66963 --- /dev/null +++ b/kernel-open/nvidia/nv-nano-timer.c @@ -0,0 +1,233 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#define __NO_VERSION__ + +#include // For container_of +#include +#include +#include +#include "os-interface.h" +#include "nv-linux.h" + +#if !defined(NVCPU_PPC64LE) +#define NV_NANO_TIMER_USE_HRTIMER 1 +#else +#define NV_NANO_TIMER_USE_HRTIMER 0 +#endif // !defined(NVCPU_PPC64LE) + +struct nv_nano_timer +{ +#if NV_NANO_TIMER_USE_HRTIMER + struct hrtimer hr_timer; // This parameter holds linux high resolution timer object + // can get replaced with platform specific timer object +#else + struct timer_list jiffy_timer; +#endif + nv_linux_state_t *nv_linux_state; + void (*nv_nano_timer_callback)(struct nv_nano_timer *nv_nstimer); + void *pTmrEvent; +}; + +/*! + * @brief runs nano second resolution timer callback +* + * @param[in] nv_nstimer Pointer to nv_nano_timer_t object + */ +static void +nvidia_nano_timer_callback( + nv_nano_timer_t *nv_nstimer) +{ + nv_state_t *nv = NULL; + nv_linux_state_t *nvl = nv_nstimer->nv_linux_state; + nvidia_stack_t *sp = NULL; + + if (nv_kmem_cache_alloc_stack(&sp) != 0) + { + nv_printf(NV_DBG_ERRORS, "NVRM: no cache memory \n"); + return; + } + + nv = NV_STATE_PTR(nvl); + + if (rm_run_nano_timer_callback(sp, nv, nv_nstimer->pTmrEvent) != NV_OK) + { + nv_printf(NV_DBG_ERRORS, "NVRM: Error in service of callback \n"); + } + + nv_kmem_cache_free_stack(sp); +} + +/*! + * @brief Allocates nano second resolution timer object + * + * @returns nv_nano_timer_t allocated pointer + */ +static nv_nano_timer_t *nv_alloc_nano_timer(void) +{ + nv_nano_timer_t *nv_nstimer; + + NV_KMALLOC(nv_nstimer, sizeof(nv_nano_timer_t)); + + if (nv_nstimer == NULL) + { + return NULL; + } + + memset(nv_nstimer, 0, sizeof(nv_nano_timer_t)); + + return nv_nstimer; +} + +#if NV_NANO_TIMER_USE_HRTIMER +static enum hrtimer_restart nv_nano_timer_callback_typed_data(struct hrtimer *hrtmr) +{ + struct nv_nano_timer *nv_nstimer = + container_of(hrtmr, struct nv_nano_timer, hr_timer); + + nv_nstimer->nv_nano_timer_callback(nv_nstimer); + + return HRTIMER_NORESTART; +} +#else +static inline void nv_jiffy_timer_callback_typed_data(struct timer_list *timer) +{ + struct nv_nano_timer *nv_nstimer = + container_of(timer, struct nv_nano_timer, jiffy_timer); + + nv_nstimer->nv_nano_timer_callback(nv_nstimer); +} + +static inline void nv_jiffy_timer_callback_anon_data(unsigned long arg) +{ + struct nv_nano_timer *nv_nstimer = (struct nv_nano_timer *)arg; + + nv_nstimer->nv_nano_timer_callback(nv_nstimer); +} +#endif + +/*! + * @brief Creates & initializes nano second resolution timer object + * + * @param[in] nv Per gpu linux state + * @param[in] tmrEvent pointer to TMR_EVENT + * @param[in] nv_nstimer Pointer to nv_nano_timer_t object + */ +void NV_API_CALL nv_create_nano_timer( + nv_state_t *nv, + void *pTmrEvent, + nv_nano_timer_t **pnv_nstimer) +{ + nv_linux_state_t *nvl = NV_GET_NVL_FROM_NV_STATE(nv); + nv_nano_timer_t *nv_nstimer = nv_alloc_nano_timer(); + + if (nv_nstimer == NULL) + { + nv_printf(NV_DBG_ERRORS, "NVRM: Not able to create timer object \n"); + *pnv_nstimer = NULL; + return; + } + + nv_nstimer->nv_linux_state = nvl; + nv_nstimer->pTmrEvent = pTmrEvent; + + nv_nstimer->nv_nano_timer_callback = nvidia_nano_timer_callback; + +#if NV_NANO_TIMER_USE_HRTIMER + hrtimer_init(&nv_nstimer->hr_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + nv_nstimer->hr_timer.function = nv_nano_timer_callback_typed_data; +#else +#if defined(NV_TIMER_SETUP_PRESENT) + timer_setup(&nv_nstimer->jiffy_timer, nv_jiffy_timer_callback_typed_data, 0); +#else + init_timer(&nv_nstimer->jiffy_timer); + nv_nstimer->jiffy_timer.function = nv_jiffy_timer_callback_anon_data; + nv_nstimer->jiffy_timer.data = (unsigned long)nv_nstimer; +#endif // NV_TIMER_SETUP_PRESENT +#endif // NV_NANO_TIMER_USE_HRTIMER + + *pnv_nstimer = nv_nstimer; +} + +/*! + * @brief Starts nano second resolution timer + * + * @param[in] nv Per gpu linux state + * @param[in] nv_nstimer Pointer to nv_nano_timer_t object + * @param[in] timens time in nano seconds + */ +void NV_API_CALL nv_start_nano_timer( + nv_state_t *nv, + nv_nano_timer_t *nv_nstimer, + NvU64 time_ns) +{ +#if NV_NANO_TIMER_USE_HRTIMER + ktime_t ktime = ktime_set(0, time_ns); + hrtimer_start(&nv_nstimer->hr_timer, ktime, HRTIMER_MODE_REL); +#else + unsigned long time_jiffies; + NvU32 time_us; + + time_us = (NvU32)(time_ns / 1000); + + if (time_us == 0) + { + nv_printf(NV_DBG_WARNINGS, "NVRM: Timer value cannot be less than 1 usec.\n"); + } + + time_jiffies = usecs_to_jiffies(time_us); + mod_timer(&nv_nstimer->jiffy_timer, jiffies + time_jiffies); +#endif +} + +/*! + * @brief Cancels nano second resolution timer + * + * @param[in] nv Per gpu linux state + * @param[in] nv_nstimer Pointer to nv_nano_timer_t object + */ +void NV_API_CALL nv_cancel_nano_timer( + nv_state_t *nv, + nv_nano_timer_t *nv_nstimer) +{ +#if NV_NANO_TIMER_USE_HRTIMER + hrtimer_cancel(&nv_nstimer->hr_timer); +#else + del_timer(&nv_nstimer->jiffy_timer); +#endif + +} + +/*! + * @brief Cancels & deletes nano second resolution timer object + * + * @param[in] nv Per gpu linux state + * @param[in] nv_nstimer Pointer to nv_nano_timer_t object + */ +void NV_API_CALL nv_destroy_nano_timer( + nv_state_t *nv, + nv_nano_timer_t *nv_nstimer) +{ + nv_cancel_nano_timer(nv, nv_nstimer); + NV_KFREE(nv_nstimer, sizeof(nv_nano_timer_t)); +} diff --git a/kernel-open/nvidia/nv-pci.c b/kernel-open/nvidia/nv-pci.c index 7544de27f..311d9fd12 100644 --- a/kernel-open/nvidia/nv-pci.c +++ b/kernel-open/nvidia/nv-pci.c @@ -172,6 +172,8 @@ nv_pci_probe NvBool prev_nv_ats_supported = nv_ats_supported; NV_STATUS status; NvBool last_bar_64bit = NV_FALSE; + NvU8 regs_bar_index = nv_bar_index_to_os_bar_index(pci_dev, + NV_GPU_BAR_INDEX_REGS); nv_printf(NV_DBG_SETUP, "NVRM: probing 0x%x 0x%x, class 0x%x\n", pci_dev->vendor, pci_dev->device, pci_dev->class); @@ -350,28 +352,26 @@ next_bar: goto failed; } - if (!request_mem_region(NV_PCI_RESOURCE_START(pci_dev, NV_GPU_BAR_INDEX_REGS), - NV_PCI_RESOURCE_SIZE(pci_dev, NV_GPU_BAR_INDEX_REGS), + if (!request_mem_region(NV_PCI_RESOURCE_START(pci_dev, regs_bar_index), + NV_PCI_RESOURCE_SIZE(pci_dev, regs_bar_index), nv_device_name)) { nv_printf(NV_DBG_ERRORS, "NVRM: request_mem_region failed for %dM @ 0x%llx. This can\n" "NVRM: occur when a driver such as rivatv is loaded and claims\n" "NVRM: ownership of the device's registers.\n", - (NV_PCI_RESOURCE_SIZE(pci_dev, NV_GPU_BAR_INDEX_REGS) >> 20), - (NvU64)NV_PCI_RESOURCE_START(pci_dev, NV_GPU_BAR_INDEX_REGS)); + (NV_PCI_RESOURCE_SIZE(pci_dev, regs_bar_index) >> 20), + (NvU64)NV_PCI_RESOURCE_START(pci_dev, regs_bar_index)); goto failed; } - NV_KMALLOC(nvl, sizeof(nv_linux_state_t)); + NV_KZALLOC(nvl, sizeof(nv_linux_state_t)); if (nvl == NULL) { nv_printf(NV_DBG_ERRORS, "NVRM: failed to allocate memory\n"); goto err_not_supported; } - os_mem_set(nvl, 0, sizeof(nv_linux_state_t)); - nv = NV_STATE_PTR(nvl); pci_set_drvdata(pci_dev, (void *)nvl); @@ -498,9 +498,7 @@ next_bar: if (nvidia_frontend_add_device((void *)&nv_fops, nvl) != 0) goto err_remove_device; -#if defined(NV_PM_VT_SWITCH_REQUIRED_PRESENT) pm_vt_switch_required(nvl->dev, NV_TRUE); -#endif nv_init_dynamic_power_management(sp, pci_dev); @@ -544,9 +542,7 @@ err_vgpu_kvm: #endif nv_procfs_remove_gpu(nvl); rm_cleanup_dynamic_power_management(sp, nv); -#if defined(NV_PM_VT_SWITCH_REQUIRED_PRESENT) pm_vt_switch_unregister(nvl->dev); -#endif err_remove_device: LOCK_NV_LINUX_DEVICES(); nv_linux_remove_device_locked(nvl); @@ -561,8 +557,8 @@ err_not_supported: { NV_KFREE(nvl, sizeof(nv_linux_state_t)); } - release_mem_region(NV_PCI_RESOURCE_START(pci_dev, NV_GPU_BAR_INDEX_REGS), - NV_PCI_RESOURCE_SIZE(pci_dev, NV_GPU_BAR_INDEX_REGS)); + release_mem_region(NV_PCI_RESOURCE_START(pci_dev, regs_bar_index), + NV_PCI_RESOURCE_SIZE(pci_dev, regs_bar_index)); NV_PCI_DISABLE_DEVICE(pci_dev); pci_set_drvdata(pci_dev, NULL); failed: @@ -576,6 +572,8 @@ nv_pci_remove(struct pci_dev *pci_dev) nv_linux_state_t *nvl = NULL; nv_state_t *nv; nvidia_stack_t *sp = NULL; + NvU8 regs_bar_index = nv_bar_index_to_os_bar_index(pci_dev, + NV_GPU_BAR_INDEX_REGS); nv_printf(NV_DBG_SETUP, "NVRM: removing GPU %04x:%02x:%02x.%x\n", NV_PCI_DOMAIN_NUMBER(pci_dev), NV_PCI_BUS_NUMBER(pci_dev), @@ -671,9 +669,7 @@ nv_pci_remove(struct pci_dev *pci_dev) UNLOCK_NV_LINUX_DEVICES(); -#if defined(NV_PM_VT_SWITCH_REQUIRED_PRESENT) pm_vt_switch_unregister(&pci_dev->dev); -#endif #if defined(NV_VGPU_KVM_BUILD) /* Arg 2 == NV_TRUE means that the PCI device should be removed */ @@ -717,8 +713,8 @@ nv_pci_remove(struct pci_dev *pci_dev) rm_i2c_remove_adapters(sp, nv); rm_free_private_state(sp, nv); - release_mem_region(NV_PCI_RESOURCE_START(pci_dev, NV_GPU_BAR_INDEX_REGS), - NV_PCI_RESOURCE_SIZE(pci_dev, NV_GPU_BAR_INDEX_REGS)); + release_mem_region(NV_PCI_RESOURCE_START(pci_dev, regs_bar_index), + NV_PCI_RESOURCE_SIZE(pci_dev, regs_bar_index)); num_nv_devices--; @@ -751,6 +747,11 @@ nv_pci_shutdown(struct pci_dev *pci_dev) return; } + if (nvl != NULL) + { + nvl->nv_state.is_shutdown = NV_TRUE; + } + /* pci_clear_master is not defined for !CONFIG_PCI */ #ifdef CONFIG_PCI pci_clear_master(pci_dev); @@ -1000,6 +1001,10 @@ struct pci_driver nv_pci_driver = { .probe = nv_pci_probe, .remove = nv_pci_remove, .shutdown = nv_pci_shutdown, +#if defined(NV_USE_VFIO_PCI_CORE) && \ + defined(NV_PCI_DRIVER_HAS_DRIVER_MANAGED_DMA) + .driver_managed_dma = NV_TRUE, +#endif #if defined(CONFIG_PM) .driver.pm = &nv_pm_ops, #endif diff --git a/kernel-open/nvidia/nv-procfs.c b/kernel-open/nvidia/nv-procfs.c index 01009907b..fae10184c 100644 --- a/kernel-open/nvidia/nv-procfs.c +++ b/kernel-open/nvidia/nv-procfs.c @@ -201,8 +201,6 @@ nv_procfs_read_power( const char *dynamic_power_status; const char *gc6_support; const char *gcoff_support; - NvU32 limitRated, limitCurr; - NV_STATUS status; if (nv_kmem_cache_alloc_stack(&sp) != 0) { @@ -220,20 +218,7 @@ nv_procfs_read_power( seq_printf(s, " Video Memory Self Refresh: %s\n", gc6_support); gcoff_support = rm_get_gpu_gcx_support(sp, nv, NV_FALSE); - seq_printf(s, " Video Memory Off: %s\n\n", gcoff_support); - - seq_printf(s, "Power Limits:\n"); - status = rm_get_clientnvpcf_power_limits(sp, nv, &limitRated, &limitCurr); - if (status != NV_OK) - { - seq_printf(s, " Default: N/A milliwatts\n"); - seq_printf(s, " GPU Boost: N/A milliwatts\n"); - } - else - { - seq_printf(s, " Default: %u milliwatts\n", limitRated); - seq_printf(s, " GPU Boost: %u milliwatts\n", limitCurr); - } + seq_printf(s, " Video Memory Off: %s\n", gcoff_support); nv_kmem_cache_free_stack(sp); return 0; @@ -288,13 +273,12 @@ nv_procfs_open_file( nv_procfs_private_t *nvpp = NULL; nvidia_stack_t *sp = NULL; - NV_KMALLOC(nvpp, sizeof(nv_procfs_private_t)); + NV_KZALLOC(nvpp, sizeof(nv_procfs_private_t)); if (nvpp == NULL) { nv_printf(NV_DBG_ERRORS, "NVRM: failed to allocate procfs private!\n"); return -ENOMEM; } - memset(nvpp, 0, sizeof(*nvpp)); NV_INIT_MUTEX(&nvpp->sp_lock); @@ -1384,7 +1368,7 @@ int nv_procfs_init(void) return 0; #if defined(CONFIG_PROC_FS) failed: - nv_procfs_unregister_all(proc_nvidia, proc_nvidia); + proc_remove(proc_nvidia); return -ENOMEM; #endif } @@ -1392,7 +1376,7 @@ failed: void nv_procfs_exit(void) { #if defined(CONFIG_PROC_FS) - nv_procfs_unregister_all(proc_nvidia, proc_nvidia); + proc_remove(proc_nvidia); #endif } @@ -1463,7 +1447,7 @@ int nv_procfs_add_gpu(nv_linux_state_t *nvl) failed: if (proc_nvidia_gpu) { - nv_procfs_unregister_all(proc_nvidia_gpu, proc_nvidia_gpu); + proc_remove(proc_nvidia_gpu); } return -1; #endif @@ -1472,6 +1456,6 @@ failed: void nv_procfs_remove_gpu(nv_linux_state_t *nvl) { #if defined(CONFIG_PROC_FS) - nv_procfs_unregister_all(nvl->proc_dir, nvl->proc_dir); + proc_remove(nvl->proc_dir); #endif } diff --git a/kernel-open/nvidia/nv-vm.c b/kernel-open/nvidia/nv-vm.c index d333a6930..2bfceb612 100644 --- a/kernel-open/nvidia/nv-vm.c +++ b/kernel-open/nvidia/nv-vm.c @@ -295,8 +295,18 @@ static NV_STATUS nv_alloc_coherent_pages( unsigned int gfp_mask; unsigned long virt_addr = 0; dma_addr_t bus_addr; - nv_linux_state_t *nvl = NV_GET_NVL_FROM_NV_STATE(nv); - struct device *dev = nvl->dev; + nv_linux_state_t *nvl; + struct device *dev; + + if (!nv) + { + nv_printf(NV_DBG_MEMINFO, + "NVRM: VM: %s: coherent page alloc on nvidiactl not supported\n", __FUNCTION__); + return NV_ERR_NOT_SUPPORTED; + } + + nvl = NV_GET_NVL_FROM_NV_STATE(nv); + dev = nvl->dev; gfp_mask = nv_compute_gfp_mask(nv, at); @@ -691,29 +701,3 @@ void nv_vm_unmap_pages( nv_vunmap(virt_addr, count); } -void nv_address_space_init_once(struct address_space *mapping) -{ -#if defined(NV_ADDRESS_SPACE_INIT_ONCE_PRESENT) - address_space_init_once(mapping); -#else - memset(mapping, 0, sizeof(*mapping)); - INIT_RADIX_TREE(&mapping->page_tree, GFP_ATOMIC); - -#if defined(NV_ADDRESS_SPACE_HAS_RWLOCK_TREE_LOCK) - // - // The .tree_lock member variable was changed from type rwlock_t, to - // spinlock_t, on 25 July 2008, by mainline commit - // 19fd6231279be3c3bdd02ed99f9b0eb195978064. - // - rwlock_init(&mapping->tree_lock); -#else - spin_lock_init(&mapping->tree_lock); -#endif - - spin_lock_init(&mapping->i_mmap_lock); - INIT_LIST_HEAD(&mapping->private_list); - spin_lock_init(&mapping->private_lock); - INIT_RAW_PRIO_TREE_ROOT(&mapping->i_mmap); - INIT_LIST_HEAD(&mapping->i_mmap_nonlinear); -#endif /* !NV_ADDRESS_SPACE_INIT_ONCE_PRESENT */ -} diff --git a/kernel-open/nvidia/nv.c b/kernel-open/nvidia/nv.c index 577a0e514..88abf782f 100644 --- a/kernel-open/nvidia/nv.c +++ b/kernel-open/nvidia/nv.c @@ -21,6 +21,14 @@ * DEALINGS IN THE SOFTWARE. */ +#include // for MODULE_FIRMWARE + +// must precede "nv.h" and "nv-firmware.h" includes +#define NV_FIRMWARE_PATH_FOR_FILENAME(filename) "nvidia/" NV_VERSION_STRING "/" filename +#define NV_FIRMWARE_DECLARE_GSP_FILENAME(filename) \ + MODULE_FIRMWARE(NV_FIRMWARE_PATH_FOR_FILENAME(filename)); +#include "nv-firmware.h" + #include "nvmisc.h" #include "os-interface.h" #include "nv-linux.h" @@ -90,11 +98,6 @@ const NvBool nv_is_rm_firmware_supported_os = NV_TRUE; char *rm_firmware_active = NULL; NV_MODULE_STRING_PARAMETER(rm_firmware_active); -#define NV_FIRMWARE_GSP_FILENAME "nvidia/" NV_VERSION_STRING "/gsp.bin" -#define NV_FIRMWARE_GSP_LOG_FILENAME "nvidia/" NV_VERSION_STRING "/gsp_log.bin" - -MODULE_FIRMWARE(NV_FIRMWARE_GSP_FILENAME); - /* * Global NVIDIA capability state, for GPU driver */ @@ -283,15 +286,13 @@ nv_alloc_t *nvos_create_alloc( nv_alloc_t *at; unsigned int pt_size, i; - NV_KMALLOC(at, sizeof(nv_alloc_t)); + NV_KZALLOC(at, sizeof(nv_alloc_t)); if (at == NULL) { nv_printf(NV_DBG_ERRORS, "NVRM: failed to allocate alloc info\n"); return NULL; } - memset(at, 0, sizeof(nv_alloc_t)); - at->dev = dev; pt_size = num_pages * sizeof(nvidia_pte_t *); if (os_alloc_mem((void **)&at->page_table, pt_size) != NV_OK) @@ -885,16 +886,18 @@ static void *nv_alloc_file_private(void) nv_linux_file_private_t *nvlfp; unsigned int i; - NV_KMALLOC(nvlfp, sizeof(nv_linux_file_private_t)); + NV_KZALLOC(nvlfp, sizeof(nv_linux_file_private_t)); if (!nvlfp) return NULL; - memset(nvlfp, 0, sizeof(nv_linux_file_private_t)); - - for (i = 0; i < NV_FOPS_STACK_INDEX_COUNT; ++i) + if (rm_is_altstack_in_use()) { - NV_INIT_MUTEX(&nvlfp->fops_sp_lock[i]); + for (i = 0; i < NV_FOPS_STACK_INDEX_COUNT; ++i) + { + NV_INIT_MUTEX(&nvlfp->fops_sp_lock[i]); + } } + init_waitqueue_head(&nvlfp->waitqueue); NV_SPIN_LOCK_INIT(&nvlfp->fp_lock); @@ -1167,7 +1170,7 @@ static int nv_start_device(nv_state_t *nv, nvidia_stack_t *sp) goto failed; } - if (nv_dev_is_pci(nvl->dev) && (nv->pci_info.device_id == 0)) + if (dev_is_pci(nvl->dev) && (nv->pci_info.device_id == 0)) { nv_printf(NV_DBG_ERRORS, "NVRM: open of non-existent GPU with minor number %d\n", nvl->minor_num); rc = -ENXIO; @@ -1210,7 +1213,7 @@ static int nv_start_device(nv_state_t *nv, nvidia_stack_t *sp) } #if defined(NV_LINUX_PCIE_MSI_SUPPORTED) - if (nv_dev_is_pci(nvl->dev)) + if (dev_is_pci(nvl->dev)) { if (!(nv->flags & NV_FLAG_PERSISTENT_SW_STATE)) { @@ -1354,7 +1357,7 @@ failed: if(nvl->irq_count) NV_KFREE(nvl->irq_count, nvl->num_intr * sizeof(nv_irq_count_info_t)); } - if (nv->flags & NV_FLAG_USES_MSIX) + else if (nv->flags & NV_FLAG_USES_MSIX) { nv->flags &= ~NV_FLAG_USES_MSIX; pci_disable_msix(nvl->pci_dev); @@ -1464,7 +1467,7 @@ static void nv_init_mapping_revocation(nv_linux_state_t *nvl, down(&nvl->mmap_lock); /* Set up struct address_space for use with unmap_mapping_range() */ - nv_address_space_init_once(&nvlfp->mapping); + address_space_init_once(&nvlfp->mapping); nvlfp->mapping.host = inode; nvlfp->mapping.a_ops = inode->i_mapping->a_ops; #if defined(NV_ADDRESS_SPACE_HAS_BACKING_DEV_INFO) @@ -1976,7 +1979,7 @@ static int nvidia_read_card_info(nv_ioctl_card_info_t *ci, size_t num_entries) ci[i].reg_address = nv->regs->cpu_address; ci[i].reg_size = nv->regs->size; ci[i].minor_number = nvl->minor_num; - if (nv_dev_is_pci(nvl->dev)) + if (dev_is_pci(nvl->dev)) { ci[i].fb_address = nv->fb->cpu_address; ci[i].fb_size = nv->fb->size; @@ -2015,8 +2018,7 @@ nvidia_ioctl( if (status < 0) return status; - down(&nvlfp->fops_sp_lock[NV_FOPS_STACK_INDEX_IOCTL]); - sp = nvlfp->fops_sp[NV_FOPS_STACK_INDEX_IOCTL]; + sp = nv_nvlfp_get_sp(nvlfp, NV_FOPS_STACK_INDEX_IOCTL); rmStatus = nv_check_gpu_state(nv); if (rmStatus == NV_ERR_GPU_IS_LOST) @@ -2327,7 +2329,7 @@ unlock: } done: - up(&nvlfp->fops_sp_lock[NV_FOPS_STACK_INDEX_IOCTL]); + nv_nvlfp_put_sp(nvlfp, NV_FOPS_STACK_INDEX_IOCTL); up_read(&nv_system_pm_lock); @@ -2392,7 +2394,7 @@ nvidia_isr( NvU64 currentTime = 0; NvBool found_irq = NV_FALSE; - rm_gpu_copy_mmu_faults_unlocked(nvl->sp[NV_DEV_STACK_ISR], nv, &rm_serviceable_fault_cnt); + rm_gpu_handle_mmu_faults(nvl->sp[NV_DEV_STACK_ISR], nv, &rm_serviceable_fault_cnt); rm_fault_handling_needed = (rm_serviceable_fault_cnt != 0); #if defined (NV_UVM_ENABLE) @@ -3546,23 +3548,10 @@ NvBool NV_API_CALL nv_is_rm_firmware_active( return NV_FALSE; } -const char *nv_firmware_path( - nv_firmware_t fw_type -) -{ - switch (fw_type) - { - case NV_FIRMWARE_GSP: - return NV_FIRMWARE_GSP_FILENAME; - case NV_FIRMWARE_GSP_LOG: - return NV_FIRMWARE_GSP_LOG_FILENAME; - } - return ""; -} - const void* NV_API_CALL nv_get_firmware( nv_state_t *nv, - nv_firmware_t fw_type, + nv_firmware_type_t fw_type, + nv_firmware_chip_family_t fw_chip_family, const void **fw_buf, NvU32 *fw_size ) @@ -3572,7 +3561,7 @@ const void* NV_API_CALL nv_get_firmware( // path is relative to /lib/firmware // if this fails it will print an error to dmesg - if (request_firmware(&fw, nv_firmware_path(fw_type), nvl->dev) != 0) + if (request_firmware(&fw, nv_firmware_path(fw_type, fw_chip_family), nvl->dev) != 0) return NULL; *fw_size = fw->size; @@ -3972,7 +3961,7 @@ nvidia_suspend( nv_linux_state_t *nvl; nv_state_t *nv; - if (nv_dev_is_pci(dev)) + if (dev_is_pci(dev)) { pci_dev = to_pci_dev(dev); nvl = pci_get_drvdata(pci_dev); @@ -4050,7 +4039,7 @@ nvidia_resume( nv_linux_state_t *nvl; nv_state_t *nv; - if (nv_dev_is_pci(dev)) + if (dev_is_pci(dev)) { pci_dev = to_pci_dev(dev); nvl = pci_get_drvdata(pci_dev); @@ -4904,7 +4893,7 @@ NV_STATUS NV_API_CALL nv_get_nvlink_line_rate( NvU32 *linerate ) { -#if defined(NV_PNV_PCI_GET_NPU_DEV_PRESENT) && defined(NV_OF_GET_PROPERTY_PRESENT) +#if defined(NV_PNV_PCI_GET_NPU_DEV_PRESENT) nv_linux_state_t *nvl; struct pci_dev *npuDev; @@ -5141,7 +5130,7 @@ void NV_API_CALL nv_audio_dynamic_power( struct pci_dev *audio_pci_dev, *pci_dev; struct snd_card *card; - if (!nv_dev_is_pci(dev)) + if (!dev_is_pci(dev)) return; pci_dev = to_pci_dev(dev); @@ -5291,45 +5280,19 @@ static int nv_match_dev_state(const void *data, struct file *filp, unsigned fd) return (data == nvl); } +NvBool NV_API_CALL nv_match_gpu_os_info(nv_state_t *nv, void *os_info) +{ + nv_linux_state_t *nvl = NV_GET_NVL_FROM_NV_STATE(nv); + + return nv_match_dev_state(nvl, os_info, -1); +} + NvBool NV_API_CALL nv_is_gpu_accessible(nv_state_t *nv) { struct files_struct *files = current->files; nv_linux_state_t *nvl = NV_GET_NVL_FROM_NV_STATE(nv); -#ifdef NV_ITERATE_FD_PRESENT return !!iterate_fd(files, 0, nv_match_dev_state, nvl); -#else - struct fdtable *fdtable; - int ret_val = 0; - int fd = 0; - - if (files == NULL) - return 0; - - spin_lock(&files->file_lock); - - for (fdtable = files_fdtable(files); fd < fdtable->max_fds; fd++) - { - struct file *filp; - -#ifdef READ_ONCE - filp = READ_ONCE(fdtable->fd[fd]); -#else - filp = ACCESS_ONCE(fdtable->fd[fd]); - smp_read_barrier_depends(); -#endif - if (filp == NULL) - continue; - - ret_val = nv_match_dev_state(nvl, filp, fd); - if (ret_val) - break; - } - - spin_unlock(&files->file_lock); - - return !!ret_val; -#endif } NvBool NV_API_CALL nv_platform_supports_s0ix(void) diff --git a/kernel-open/nvidia/nvidia-sources.Kbuild b/kernel-open/nvidia/nvidia-sources.Kbuild index 910a91cea..0ac73b671 100644 --- a/kernel-open/nvidia/nvidia-sources.Kbuild +++ b/kernel-open/nvidia/nvidia-sources.Kbuild @@ -4,6 +4,7 @@ NVIDIA_SOURCES_CXX ?= NVIDIA_SOURCES += nvidia/nv.c NVIDIA_SOURCES += nvidia/nv-pci.c NVIDIA_SOURCES += nvidia/nv-dmabuf.c +NVIDIA_SOURCES += nvidia/nv-nano-timer.c NVIDIA_SOURCES += nvidia/nv-acpi.c NVIDIA_SOURCES += nvidia/nv-cray.c NVIDIA_SOURCES += nvidia/nv-dma.c @@ -12,7 +13,6 @@ NVIDIA_SOURCES += nvidia/nv-mmap.c NVIDIA_SOURCES += nvidia/nv-p2p.c NVIDIA_SOURCES += nvidia/nv-pat.c NVIDIA_SOURCES += nvidia/nv-procfs.c -NVIDIA_SOURCES += nvidia/nv-procfs-utils.c NVIDIA_SOURCES += nvidia/nv-usermap.c NVIDIA_SOURCES += nvidia/nv-vm.c NVIDIA_SOURCES += nvidia/nv-vtophys.c diff --git a/kernel-open/nvidia/nvidia.Kbuild b/kernel-open/nvidia/nvidia.Kbuild index 3d3b48165..5d8b4d0b8 100644 --- a/kernel-open/nvidia/nvidia.Kbuild +++ b/kernel-open/nvidia/nvidia.Kbuild @@ -120,27 +120,21 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += set_memory_array_uc NV_CONFTEST_FUNCTION_COMPILE_TESTS += set_pages_array_uc NV_CONFTEST_FUNCTION_COMPILE_TESTS += ioremap_cache NV_CONFTEST_FUNCTION_COMPILE_TESTS += ioremap_wc -NV_CONFTEST_FUNCTION_COMPILE_TESTS += sg_alloc_table NV_CONFTEST_FUNCTION_COMPILE_TESTS += pci_get_domain_bus_and_slot NV_CONFTEST_FUNCTION_COMPILE_TESTS += get_num_physpages -NV_CONFTEST_FUNCTION_COMPILE_TESTS += efi_enabled NV_CONFTEST_FUNCTION_COMPILE_TESTS += pde_data -NV_CONFTEST_FUNCTION_COMPILE_TESTS += proc_remove -NV_CONFTEST_FUNCTION_COMPILE_TESTS += pm_vt_switch_required NV_CONFTEST_FUNCTION_COMPILE_TESTS += xen_ioemu_inject_msi NV_CONFTEST_FUNCTION_COMPILE_TESTS += phys_to_dma NV_CONFTEST_FUNCTION_COMPILE_TESTS += get_dma_ops NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_attr_macros NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_map_page_attrs NV_CONFTEST_FUNCTION_COMPILE_TESTS += write_cr4 -NV_CONFTEST_FUNCTION_COMPILE_TESTS += of_get_property NV_CONFTEST_FUNCTION_COMPILE_TESTS += of_find_node_by_phandle NV_CONFTEST_FUNCTION_COMPILE_TESTS += of_node_to_nid NV_CONFTEST_FUNCTION_COMPILE_TESTS += pnv_pci_get_npu_dev NV_CONFTEST_FUNCTION_COMPILE_TESTS += of_get_ibm_chip_id NV_CONFTEST_FUNCTION_COMPILE_TESTS += pci_bus_address NV_CONFTEST_FUNCTION_COMPILE_TESTS += pci_stop_and_remove_bus_device -NV_CONFTEST_FUNCTION_COMPILE_TESTS += pci_remove_bus_device NV_CONFTEST_FUNCTION_COMPILE_TESTS += register_cpu_notifier NV_CONFTEST_FUNCTION_COMPILE_TESTS += cpuhp_setup_state NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_map_resource @@ -148,10 +142,7 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += get_backlight_device_by_name NV_CONFTEST_FUNCTION_COMPILE_TESTS += timer_setup NV_CONFTEST_FUNCTION_COMPILE_TESTS += pci_enable_msix_range NV_CONFTEST_FUNCTION_COMPILE_TESTS += kernel_read_has_pointer_pos_arg -NV_CONFTEST_FUNCTION_COMPILE_TESTS += kernel_write -NV_CONFTEST_FUNCTION_COMPILE_TESTS += kthread_create_on_node -NV_CONFTEST_FUNCTION_COMPILE_TESTS += of_find_matching_node -NV_CONFTEST_FUNCTION_COMPILE_TESTS += dev_is_pci +NV_CONFTEST_FUNCTION_COMPILE_TESTS += kernel_write_has_pointer_pos_arg NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_direct_map_resource NV_CONFTEST_FUNCTION_COMPILE_TESTS += tegra_get_platform NV_CONFTEST_FUNCTION_COMPILE_TESTS += tegra_bpmp_send_receive @@ -161,18 +152,14 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += jiffies_to_timespec NV_CONFTEST_FUNCTION_COMPILE_TESTS += ktime_get_raw_ts64 NV_CONFTEST_FUNCTION_COMPILE_TESTS += ktime_get_real_ts64 NV_CONFTEST_FUNCTION_COMPILE_TESTS += full_name_hash -NV_CONFTEST_FUNCTION_COMPILE_TESTS += hlist_for_each_entry NV_CONFTEST_FUNCTION_COMPILE_TESTS += pci_enable_atomic_ops_to_root NV_CONFTEST_FUNCTION_COMPILE_TESTS += vga_tryget NV_CONFTEST_FUNCTION_COMPILE_TESTS += pgprot_decrypted NV_CONFTEST_FUNCTION_COMPILE_TESTS += cc_mkdec -NV_CONFTEST_FUNCTION_COMPILE_TESTS += iterate_fd NV_CONFTEST_FUNCTION_COMPILE_TESTS += seq_read_iter -NV_CONFTEST_FUNCTION_COMPILE_TESTS += sg_page_iter_page NV_CONFTEST_FUNCTION_COMPILE_TESTS += unsafe_follow_pfn NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_gem_object_get NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_gem_object_put_unlocked -NV_CONFTEST_FUNCTION_COMPILE_TESTS += set_close_on_exec NV_CONFTEST_FUNCTION_COMPILE_TESTS += add_memory_driver_managed NV_CONFTEST_FUNCTION_COMPILE_TESTS += device_property_read_u64 NV_CONFTEST_FUNCTION_COMPILE_TESTS += devm_of_platform_populate @@ -199,7 +186,9 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_buf_ops_has_map_atomic NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_buf_has_dynamic_attachment NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_buf_attachment_has_peer2peer NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_set_mask_and_coherent +NV_CONFTEST_FUNCTION_COMPILE_TESTS += devm_clk_bulk_get_all NV_CONFTEST_FUNCTION_COMPILE_TESTS += get_task_ioprio +NV_CONFTEST_FUNCTION_COMPILE_TESTS += mdev_set_iommu_device NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl_of_node_to_nid NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl_sme_active @@ -221,20 +210,14 @@ NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tegra_dram_types NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_pxm_to_node NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_screen_info -NV_CONFTEST_TYPE_COMPILE_TESTS += file_operations -NV_CONFTEST_TYPE_COMPILE_TESTS += kuid_t NV_CONFTEST_TYPE_COMPILE_TESTS += dma_ops NV_CONFTEST_TYPE_COMPILE_TESTS += swiotlb_dma_ops NV_CONFTEST_TYPE_COMPILE_TESTS += noncoherent_swiotlb_dma_ops NV_CONFTEST_TYPE_COMPILE_TESTS += vm_fault_has_address NV_CONFTEST_TYPE_COMPILE_TESTS += vm_insert_pfn_prot NV_CONFTEST_TYPE_COMPILE_TESTS += vmf_insert_pfn_prot -NV_CONFTEST_TYPE_COMPILE_TESTS += address_space_init_once NV_CONFTEST_TYPE_COMPILE_TESTS += vm_ops_fault_removed_vma_arg NV_CONFTEST_TYPE_COMPILE_TESTS += vmbus_channel_has_ringbuffer_page -NV_CONFTEST_TYPE_COMPILE_TESTS += device_driver_of_match_table -NV_CONFTEST_TYPE_COMPILE_TESTS += device_of_node -NV_CONFTEST_TYPE_COMPILE_TESTS += node_states_n_memory NV_CONFTEST_TYPE_COMPILE_TESTS += kmem_cache_has_kobj_remove_work NV_CONFTEST_TYPE_COMPILE_TESTS += sysfs_slab_unlink NV_CONFTEST_TYPE_COMPILE_TESTS += proc_ops @@ -243,10 +226,10 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += vmalloc_has_pgprot_t_arg NV_CONFTEST_TYPE_COMPILE_TESTS += mm_has_mmap_lock NV_CONFTEST_TYPE_COMPILE_TESTS += pci_channel_state NV_CONFTEST_TYPE_COMPILE_TESTS += pci_dev_has_ats_enabled -NV_CONFTEST_TYPE_COMPILE_TESTS += mt_device_gre NV_CONFTEST_TYPE_COMPILE_TESTS += remove_memory_has_nid_arg NV_CONFTEST_TYPE_COMPILE_TESTS += add_memory_driver_managed_has_mhp_flags_arg NV_CONFTEST_TYPE_COMPILE_TESTS += num_registered_fb +NV_CONFTEST_TYPE_COMPILE_TESTS += pci_driver_has_driver_managed_dma NV_CONFTEST_GENERIC_COMPILE_TESTS += dom0_kernel_present NV_CONFTEST_GENERIC_COMPILE_TESTS += nvidia_vgpu_kvm_build @@ -254,7 +237,10 @@ NV_CONFTEST_GENERIC_COMPILE_TESTS += nvidia_grid_build NV_CONFTEST_GENERIC_COMPILE_TESTS += nvidia_grid_csp_build NV_CONFTEST_GENERIC_COMPILE_TESTS += get_user_pages NV_CONFTEST_GENERIC_COMPILE_TESTS += get_user_pages_remote +NV_CONFTEST_GENERIC_COMPILE_TESTS += pin_user_pages +NV_CONFTEST_GENERIC_COMPILE_TESTS += pin_user_pages_remote NV_CONFTEST_GENERIC_COMPILE_TESTS += pm_runtime_available NV_CONFTEST_GENERIC_COMPILE_TESTS += vm_fault_t NV_CONFTEST_GENERIC_COMPILE_TESTS += pci_class_multimedia_hd_audio NV_CONFTEST_GENERIC_COMPILE_TESTS += drm_available +NV_CONFTEST_GENERIC_COMPILE_TESTS += vfio_pci_core_available diff --git a/kernel-open/nvidia/nvlink_linux.c b/kernel-open/nvidia/nvlink_linux.c index 6c44d949b..56aeae0eb 100644 --- a/kernel-open/nvidia/nvlink_linux.c +++ b/kernel-open/nvidia/nvlink_linux.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -101,7 +101,7 @@ static void nvlink_permissions_exit(void) return; } - NV_REMOVE_PROC_ENTRY(nvlink_permissions); + proc_remove(nvlink_permissions); nvlink_permissions = NULL; } @@ -133,7 +133,7 @@ static void nvlink_procfs_exit(void) return; } - NV_REMOVE_PROC_ENTRY(nvlink_procfs_dir); + proc_remove(nvlink_procfs_dir); nvlink_procfs_dir = NULL; } @@ -207,8 +207,6 @@ static int nvlink_fops_release(struct inode *inode, struct file *filp) nvlink_print(NVLINK_DBG_INFO, "nvlink driver close\n"); - WARN_ON(private == NULL); - mutex_lock(&nvlink_drvctx.lock); if (private->capability_fds.fabric_mgmt > 0) @@ -306,9 +304,6 @@ static const struct file_operations nvlink_fops = { .owner = THIS_MODULE, .open = nvlink_fops_open, .release = nvlink_fops_release, -#if defined(NV_FILE_OPERATIONS_HAS_IOCTL) - .ioctl = nvlink_fops_ioctl, -#endif .unlocked_ioctl = nvlink_fops_unlocked_ioctl, }; diff --git a/kernel-open/nvidia/os-interface.c b/kernel-open/nvidia/os-interface.c index 916eb1e11..749457109 100644 --- a/kernel-open/nvidia/os-interface.c +++ b/kernel-open/nvidia/os-interface.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -233,6 +233,90 @@ NV_STATUS NV_API_CALL os_release_semaphore return NV_OK; } +typedef struct rw_semaphore os_rwlock_t; + +void* NV_API_CALL os_alloc_rwlock(void) +{ + os_rwlock_t *os_rwlock = NULL; + + NV_STATUS rmStatus = os_alloc_mem((void *)&os_rwlock, sizeof(os_rwlock_t)); + if (rmStatus != NV_OK) + { + nv_printf(NV_DBG_ERRORS, "NVRM: failed to allocate rw_semaphore!\n"); + return NULL; + } + + init_rwsem(os_rwlock); + + return os_rwlock; +} + +void NV_API_CALL os_free_rwlock(void *pRwLock) +{ + os_rwlock_t *os_rwlock = (os_rwlock_t *)pRwLock; + os_free_mem(os_rwlock); +} + +NV_STATUS NV_API_CALL os_acquire_rwlock_read(void *pRwLock) +{ + os_rwlock_t *os_rwlock = (os_rwlock_t *)pRwLock; + + if (!NV_MAY_SLEEP()) + { + return NV_ERR_INVALID_REQUEST; + } + down_read(os_rwlock); + return NV_OK; +} + +NV_STATUS NV_API_CALL os_acquire_rwlock_write(void *pRwLock) +{ + os_rwlock_t *os_rwlock = (os_rwlock_t *)pRwLock; + + if (!NV_MAY_SLEEP()) + { + return NV_ERR_INVALID_REQUEST; + } + down_write(os_rwlock); + return NV_OK; +} + +NV_STATUS NV_API_CALL os_cond_acquire_rwlock_read(void *pRwLock) +{ + os_rwlock_t *os_rwlock = (os_rwlock_t *)pRwLock; + + if (down_read_trylock(os_rwlock)) + { + return NV_ERR_TIMEOUT_RETRY; + } + + return NV_OK; +} + +NV_STATUS NV_API_CALL os_cond_acquire_rwlock_write(void *pRwLock) +{ + os_rwlock_t *os_rwlock = (os_rwlock_t *)pRwLock; + + if (down_write_trylock(os_rwlock)) + { + return NV_ERR_TIMEOUT_RETRY; + } + + return NV_OK; +} + +void NV_API_CALL os_release_rwlock_read(void *pRwLock) +{ + os_rwlock_t *os_rwlock = (os_rwlock_t *)pRwLock; + up_read(os_rwlock); +} + +void NV_API_CALL os_release_rwlock_write(void *pRwLock) +{ + os_rwlock_t *os_rwlock = (os_rwlock_t *)pRwLock; + up_write(os_rwlock); +} + NvBool NV_API_CALL os_semaphore_may_sleep(void) { return NV_MAY_SLEEP(); @@ -473,6 +557,7 @@ NV_STATUS NV_API_CALL os_alloc_mem( NvU64 size ) { + NvU64 original_size = size; unsigned long alloc_size; if (address == NULL) @@ -481,6 +566,10 @@ NV_STATUS NV_API_CALL os_alloc_mem( *address = NULL; NV_MEM_TRACKING_PAD_SIZE(size); + // check for integer overflow on size + if (size < original_size) + return NV_ERR_INVALID_ARGUMENT; + // // NV_KMALLOC, nv_vmalloc take an input of 4 bytes in x86. To avoid // truncation and wrong allocation, below check is required. @@ -515,7 +604,7 @@ NV_STATUS NV_API_CALL os_alloc_mem( void NV_API_CALL os_free_mem(void *address) { - NvU32 size; + NvU64 size; NV_MEM_TRACKING_RETRIEVE_SIZE(address, size); @@ -1100,7 +1189,7 @@ NvBool NV_API_CALL os_pat_supported(void) NvBool NV_API_CALL os_is_efi_enabled(void) { - return NV_EFI_ENABLED(); + return efi_enabled(EFI_BOOT); } void NV_API_CALL os_get_screen_info( @@ -1760,7 +1849,6 @@ NV_STATUS NV_API_CALL os_write_file NvU64 offset ) { -#if defined(NV_KERNEL_WRITE_PRESENT) loff_t f_pos = offset; ssize_t num_written; int num_retries = NV_MAX_NUM_FILE_IO_RETRIES; @@ -1791,9 +1879,6 @@ retry: } return NV_OK; -#else - return NV_ERR_NOT_SUPPORTED; -#endif } NV_STATUS NV_API_CALL os_read_file diff --git a/kernel-open/nvidia/os-mlock.c b/kernel-open/nvidia/os-mlock.c index 2369baebf..e378245e0 100644 --- a/kernel-open/nvidia/os-mlock.c +++ b/kernel-open/nvidia/os-mlock.c @@ -222,7 +222,7 @@ NV_STATUS NV_API_CALL os_lock_user_pages( struct mm_struct *mm = current->mm; struct page **user_pages; NvU64 i, pinned; - NvBool write = DRF_VAL(_LOCK_USER_PAGES, _FLAGS, _WRITE, flags), force = 0; + unsigned int gup_flags = DRF_VAL(_LOCK_USER_PAGES, _FLAGS, _WRITE, flags) ? FOLL_WRITE : 0; int ret; if (!NV_MAY_SLEEP()) @@ -242,8 +242,8 @@ NV_STATUS NV_API_CALL os_lock_user_pages( } nv_mmap_read_lock(mm); - ret = NV_GET_USER_PAGES((unsigned long)address, - page_count, write, force, user_pages, NULL); + ret = NV_PIN_USER_PAGES((unsigned long)address, + page_count, gup_flags, user_pages, NULL); nv_mmap_read_unlock(mm); pinned = ret; @@ -255,7 +255,7 @@ NV_STATUS NV_API_CALL os_lock_user_pages( else if (pinned < page_count) { for (i = 0; i < pinned; i++) - put_page(user_pages[i]); + NV_UNPIN_USER_PAGE(user_pages[i]); os_free_mem(user_pages); return NV_ERR_INVALID_ADDRESS; } @@ -278,7 +278,7 @@ NV_STATUS NV_API_CALL os_unlock_user_pages( { if (write) set_page_dirty_lock(user_pages[i]); - put_page(user_pages[i]); + NV_UNPIN_USER_PAGE(user_pages[i]); } os_free_mem(user_pages); diff --git a/kernel-open/nvidia/procfs_nvswitch.c b/kernel-open/nvidia/procfs_nvswitch.c index a1230456e..5a4e13dc6 100644 --- a/kernel-open/nvidia/procfs_nvswitch.c +++ b/kernel-open/nvidia/procfs_nvswitch.c @@ -100,7 +100,7 @@ nvswitch_procfs_device_remove return; } - nv_procfs_unregister_all(nvswitch_dev->procfs_dir, nvswitch_dev->procfs_dir); + proc_remove(nvswitch_dev->procfs_dir); nvswitch_dev->procfs_dir = NULL; } @@ -155,7 +155,7 @@ nvswitch_procfs_exit return; } - nv_procfs_unregister_all(nvswitch_procfs_dir, nvswitch_procfs_dir); + proc_remove(nvswitch_procfs_dir); nvswitch_procfs_dir = NULL; } diff --git a/nv-compiler.sh b/nv-compiler.sh new file mode 100755 index 000000000..a89f2c688 --- /dev/null +++ b/nv-compiler.sh @@ -0,0 +1,82 @@ +#!/bin/sh +# SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# SPDX-License-Identifier: MIT +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +# + +set -e + +get_compiler_type() +{ + printf "#if defined(__clang__) + clang + #elif defined(__GNUC__) + gcc + #elif defined(__INTEL_COMPILER) + icc + #else + unknown + #endif" | $1 -E -P - +} + +get_original_version() +{ + printf "#if defined(__clang__) + __clang_major__ __clang_minor__ __clang_patchlevel__ + #elif defined(__GNUC__) + __GNUC__ __GNUC_MINOR__ __GNUC_PATCHLEVEL__ + #elif defined(__INTEL_COMPILER) + __INTEL_COMPILER __INTEL_COMPILER_UPDATE + #endif" | $1 -E -P - +} + +get_canonical_version() +{ + type=$(get_compiler_type $1) + set -- $(get_original_version $1) + + # get the version based on the type + if [ "$type" = "unknown" ]; then + echo >&2 "unknown compiler: bailing out" + exit 1 + elif [ "$type" = "icc" ]; then + echo >&2 "icc is not supported" + exit 1 + else + major=$1 + minor=$2 + fi + patch=$3 + echo $(($3 + $2 * 100 + $1 * 10000)) +} + +if [ "$1" = "type" ]; then + echo $(get_compiler_type $2) +elif [ "$1" = "version_is_at_least" ]; then + if [ -z "$3" ]; then + echo >&2 "minimum compiler version cannot be empty" + exit 1 + fi + version=$(get_canonical_version $2) + if [ "$version" -gt $(($3-1)) ]; then + echo "1" + fi +fi + diff --git a/src/common/displayport/inc/dp_configcaps.h b/src/common/displayport/inc/dp_configcaps.h index bf563aa0f..c85ae4fd8 100644 --- a/src/common/displayport/inc/dp_configcaps.h +++ b/src/common/displayport/inc/dp_configcaps.h @@ -217,7 +217,7 @@ namespace DisplayPort NvU8 activeLaneCount) = 0; virtual AuxRetry::status setIgnoreMSATimingParamters(bool msaTimingParamIgnoreEn) = 0; - virtual AuxRetry::status setLinkQualLaneSet(unsigned lane, LinkQualityPatternType linkQualPattern) = 0; + virtual AuxRetry::status setLinkQualLaneSet(unsigned lane, LinkQualityPatternType linkQualPattern) = 0; virtual AuxRetry::status setLinkQualPatternSet(LinkQualityPatternType linkQualPattern, unsigned laneCount = 0) = 0; }; @@ -486,7 +486,7 @@ namespace DisplayPort virtual bool getDpcdMultiStreamCap(void) = 0; // Set GPU DP support capability - virtual void setGpuDPSupportedVersions(bool supportDp1_2, bool supportDp1_4) = 0; + virtual void setGpuDPSupportedVersions(NvU32 gpuDPSupportedVersions) = 0; // Set GPU FEC support capability virtual void setGpuFECSupported(bool bSupportFEC) = 0; diff --git a/src/common/displayport/inc/dp_connector.h b/src/common/displayport/inc/dp_connector.h index 831bd7283..7f81a08fd 100644 --- a/src/common/displayport/inc/dp_connector.h +++ b/src/common/displayport/inc/dp_connector.h @@ -262,6 +262,7 @@ namespace DisplayPort virtual bool setPanelReplayConfig(panelReplayConfig prcfg) = 0; virtual bool isPanelReplaySupported() = 0; + virtual bool getPanelReplayStatus(PanelReplayStatus *pPrStatus) = 0; protected: virtual ~Device() {} diff --git a/src/common/displayport/inc/dp_deviceimpl.h b/src/common/displayport/inc/dp_deviceimpl.h index 0faaf0ffa..70dd68374 100644 --- a/src/common/displayport/inc/dp_deviceimpl.h +++ b/src/common/displayport/inc/dp_deviceimpl.h @@ -439,6 +439,7 @@ namespace DisplayPort bool isPanelReplaySupported(void); void getPanelReplayCaps(void); bool setPanelReplayConfig(panelReplayConfig prcfg); + bool getPanelReplayStatus(PanelReplayStatus *pPrStatus); NvBool getDSCSupport(); bool getFECSupport(); @@ -451,6 +452,7 @@ namespace DisplayPort bool parseDscCaps(const NvU8 *buffer, NvU32 bufferSize); bool parseBranchSpecificDscCaps(const NvU8 *buffer, NvU32 bufferSize); bool setDscEnable(bool enable); + bool setDscEnableDPToHDMIPCON(bool bDscEnable, bool bEnablePassThroughForPCON); bool getDscEnable(bool *pEnable); unsigned getDscVersionMajor(); unsigned getDscVersionMinor(); diff --git a/src/common/displayport/inc/dp_evoadapter.h b/src/common/displayport/inc/dp_evoadapter.h index 139306eda..b14d81a1b 100644 --- a/src/common/displayport/inc/dp_evoadapter.h +++ b/src/common/displayport/inc/dp_evoadapter.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -143,8 +143,13 @@ namespace DisplayPort bool _hasMultistream; bool _isPC2Disabled; bool _isEDP; - bool _isDP1_2Supported; - bool _isDP1_4Supported; + + // + // Bit mask for GPU supported DP versions. + // Defines the same as NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS.dpVersionsSupported + // + NvU32 _gpuSupportedDpVersions; + bool _isStreamCloningEnabled; bool _needForceRmEdid; bool _skipPowerdownEDPPanelWhenHeadDetach; @@ -198,14 +203,11 @@ namespace DisplayPort return _isPC2Disabled; } - virtual bool isDP1_2Supported() + virtual NvU32 getGpuDpSupportedVersions() { - return _isDP1_2Supported; - } - virtual bool isDP1_4Supported() - { - return _isDP1_4Supported; + return _gpuSupportedDpVersions; } + virtual bool isFECSupported() { return _isFECSupported; diff --git a/src/common/displayport/inc/dp_mainlink.h b/src/common/displayport/inc/dp_mainlink.h index 219e110b0..aac2f9a17 100644 --- a/src/common/displayport/inc/dp_mainlink.h +++ b/src/common/displayport/inc/dp_mainlink.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -129,7 +129,7 @@ namespace DisplayPort virtual NvU32 getSorIndex() = 0; virtual bool isInbandStereoSignalingSupported() = 0; - + virtual bool isEDP() = 0; virtual bool supportMSAOverMST() = 0; virtual bool isForceRmEdidRequired() = 0; @@ -175,8 +175,8 @@ namespace DisplayPort virtual bool hasIncreasedWatermarkLimits() = 0; virtual bool hasMultistream() = 0; virtual bool isPC2Disabled() = 0; - virtual bool isDP1_2Supported() = 0; - virtual bool isDP1_4Supported() = 0; + virtual NvU32 getGpuDpSupportedVersions() = 0; + virtual bool isStreamCloningEnabled() = 0; virtual NvU32 maxLinkRateSupported() = 0; virtual bool isLttprSupported() = 0; diff --git a/src/common/displayport/inc/dp_messages.h b/src/common/displayport/inc/dp_messages.h index 681695ad2..496b18a15 100644 --- a/src/common/displayport/inc/dp_messages.h +++ b/src/common/displayport/inc/dp_messages.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2010-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -116,10 +116,6 @@ namespace DisplayPort bool isBeingDestroyed; bool isPaused; - // Properties from regkey - bool bNoReplyTimerForBusyWaiting; - bool bDpcdProbingForBusyWaiting; - List messageReceivers; List notYetSentDownRequest; // Down Messages yet to be processed List notYetSentUpReply; // Up Reply Messages yet to be processed @@ -157,14 +153,6 @@ namespace DisplayPort mergerDownReply.mailboxInterrupt(); } - void applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatabase) - { - DP_ASSERT(dpRegkeyDatabase.bInitialized && - "All regkeys are invalid because dpRegkeyDatabase is not initialized!"); - bNoReplyTimerForBusyWaiting = dpRegkeyDatabase.bNoReplyTimerForBusyWaiting; - bDpcdProbingForBusyWaiting = dpRegkeyDatabase.bDpcdProbingForBusyWaiting; - } - MessageManager(DPCDHAL * hal, Timer * timer) : timer(timer), hal(hal), splitterDownRequest(hal, timer), diff --git a/src/common/displayport/inc/dp_regkeydatabase.h b/src/common/displayport/inc/dp_regkeydatabase.h index 03e251f8a..6e49227d7 100644 --- a/src/common/displayport/inc/dp_regkeydatabase.h +++ b/src/common/displayport/inc/dp_regkeydatabase.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -65,10 +65,6 @@ // #define NV_DP_DSC_MST_CAP_BUG_3143315 "DP_DSC_MST_CAP_BUG_3143315" -#define NV_DP_REGKEY_NO_REPLY_TIMER_FOR_BUSY_WAITING "NO_REPLY_TIMER_FOR_BUSY_WAITING" - -#define NV_DP_REGKEY_DPCD_PROBING_FOR_BUSY_WAITING "DP_DPCD_PROBING_FOR_BUSY_WAITING" - // // Data Base used to store all the regkey values. // The actual data base is declared statically in dp_evoadapter.cpp. @@ -100,8 +96,6 @@ struct DP_REGKEY_DATABASE bool bOptLinkKeptAliveSst; bool bBypassEDPRevCheck; bool bDscMstCapBug3143315; - bool bNoReplyTimerForBusyWaiting; - bool bDpcdProbingForBusyWaiting; }; #endif //INCLUDED_DP_REGKEYDATABASE_H diff --git a/src/common/displayport/inc/dp_watermark.h b/src/common/displayport/inc/dp_watermark.h index b9f05d094..4e1d3865e 100644 --- a/src/common/displayport/inc/dp_watermark.h +++ b/src/common/displayport/inc/dp_watermark.h @@ -54,6 +54,7 @@ namespace DisplayPort unsigned bitsPerComponent; // Bits per component bool bEnableDsc; // bEnableDsc=1 indicates DSC would be enabled for the mode DSC_MODE mode; // DSC Mode + bool bEnablePassThroughForPCON; ModesetInfo(): twoChannelAudioHz(0), eightChannelAudioHz(0), @@ -67,13 +68,14 @@ namespace DisplayPort rasterBlankEndX(0), bitsPerComponent(0), bEnableDsc(false), - mode(DSC_SINGLE) {} + mode(DSC_SINGLE), + bEnablePassThroughForPCON(false) {} ModesetInfo(unsigned newTwoChannelAudioHz, unsigned newEightChannelAudioHz, NvU64 newPixelClockHz, unsigned newRasterWidth, unsigned newRasterHeight, unsigned newSurfaceWidth, unsigned newSurfaceHeight, unsigned newDepth, unsigned newRasterBlankStartX=0, unsigned newRasterBlankEndX=0, bool newBEnableDsc = false, - DSC_MODE newMode = DSC_SINGLE): + DSC_MODE newMode = DSC_SINGLE, bool newBEnablePassThroughForPCON = false): twoChannelAudioHz(newTwoChannelAudioHz), eightChannelAudioHz(newEightChannelAudioHz), pixelClockHz(newPixelClockHz), @@ -86,7 +88,8 @@ namespace DisplayPort rasterBlankEndX(newRasterBlankEndX), bitsPerComponent(0), bEnableDsc(newBEnableDsc), - mode(newMode){} + mode(newMode), + bEnablePassThroughForPCON(newBEnablePassThroughForPCON) {} }; struct Watermark diff --git a/src/common/displayport/src/dp_configcaps.cpp b/src/common/displayport/src/dp_configcaps.cpp index 6bc038caf..7cd4389ee 100644 --- a/src/common/displayport/src/dp_configcaps.cpp +++ b/src/common/displayport/src/dp_configcaps.cpp @@ -40,8 +40,6 @@ struct DPCDHALImpl : DPCDHAL AuxRetry bus; Timer * timer; bool dpcdOffline; - bool gpuDP1_2Supported; - bool gpuDP1_4Supported; bool bGrantsPostLtRequest; bool pc2Disabled; bool uprequestEnable; @@ -54,6 +52,8 @@ struct DPCDHALImpl : DPCDHAL NvU32 overrideDpcdRev; NvU32 overrideDpcdMaxLaneCount; + NvU32 gpuDPSupportedVersions; + struct _LegacyPort: public LegacyPort { DwnStreamPortType type; @@ -226,8 +226,6 @@ struct DPCDHALImpl : DPCDHAL DPCDHALImpl(AuxBus * bus, Timer * timer) : bus(bus), timer(timer), - gpuDP1_2Supported(false), - gpuDP1_4Supported(false), bGrantsPostLtRequest(false), uprequestEnable(false), upstreamIsSource(false), @@ -235,7 +233,8 @@ struct DPCDHALImpl : DPCDHAL bGpuFECSupported(false), bBypassILREdpRevCheck(false), overrideDpcdMaxLinkRate(0), - overrideDpcdRev(0) + overrideDpcdRev(0), + gpuDPSupportedVersions(0) { // start with default caps. populateFakeDpcd(); @@ -390,8 +389,9 @@ struct DPCDHALImpl : DPCDHAL { DP_ASSERT(0 && "A DPRX with DPCD Rev. 1.4 (or higher) must have Extended Receiver Capability field."); } - - caps.supportsESI = (isAtLeastVersion(1,2) && gpuDP1_2Supported); // Support ESI register space only when GPU support DP1.2MST + // Support ESI register space only when GPU support DP1.2MST + caps.supportsESI = (isAtLeastVersion(1,2) && + FLD_TEST_DRF(0073_CTRL_CMD_DP, _GET_CAPS_DP_VERSIONS_SUPPORTED, _DP1_2, _YES, gpuDPSupportedVersions)); if (caps.eDpRevision >= NV_DPCD_EDP_REV_VAL_1_4 || this->bBypassILREdpRevCheck) { @@ -454,7 +454,9 @@ struct DPCDHALImpl : DPCDHAL DP_ASSERT(0 && "A DPRX with DPCD Rev. 1.1 (or higher) must have enhanced framing capability."); } - if (isAtLeastVersion(1,2) && gpuDP1_2Supported && caps.bPostLtAdjustmentSupport) + if (isAtLeastVersion(1,2) && + FLD_TEST_DRF(0073_CTRL_CMD_DP, _GET_CAPS_DP_VERSIONS_SUPPORTED, _DP1_2, _YES, gpuDPSupportedVersions) && + caps.bPostLtAdjustmentSupport) { // Source grants post Link training adjustment support bGrantsPostLtRequest = true; @@ -1033,6 +1035,9 @@ struct DPCDHALImpl : DPCDHAL caps.pconCaps.maxBpc = 8; break; } + + NvU8 pConColorConvCaps = basicCaps[infoByte0+3]; + caps.pconCaps.bConv444To420Supported = FLD_TEST_DRF(_DPCD, _DETAILED_CAP, _CONV_YCBCR444_TO_YCBCR420_SUPPORTED, _YES, pConColorConvCaps); break; } case NV_DPCD_DETAILED_CAP_INFO_DWNSTRM_PORT_TX_TYPE_OTHERS_NO_EDID: @@ -1231,7 +1236,8 @@ struct DPCDHALImpl : DPCDHAL // If the upstream DPTX and downstream DPRX both support TPS4, // TPS4 shall be used instead of POST_LT_ADJ_REQ. // - NvBool bTps4Supported = gpuDP1_4Supported && caps.bSupportsTPS4; + NvBool bTps4Supported = FLD_TEST_DRF(0073_CTRL_CMD_DP, _GET_CAPS_DP_VERSIONS_SUPPORTED, _DP1_4, _YES, gpuDPSupportedVersions) && + caps.bSupportsTPS4; return bGrantsPostLtRequest && !bTps4Supported; } @@ -2559,13 +2565,16 @@ struct DPCDHALImpl : DPCDHAL return caps.supportsMultistream; } - void setGpuDPSupportedVersions(bool supportDp1_2, bool supportDp1_4) + void setGpuDPSupportedVersions(NvU32 _gpuDPSupportedVersions) { - if (supportDp1_4) - DP_ASSERT(supportDp1_2 && "GPU supports DP1.4 should also support DP1.2!"); + bool bSupportDp1_2 = FLD_TEST_DRF(0073_CTRL_CMD_DP, _GET_CAPS_DP_VERSIONS_SUPPORTED, _DP1_2, _YES, gpuDPSupportedVersions); + bool bSupportDp1_4 = FLD_TEST_DRF(0073_CTRL_CMD_DP, _GET_CAPS_DP_VERSIONS_SUPPORTED, _DP1_4, _YES, gpuDPSupportedVersions); + if (bSupportDp1_4) + { + DP_ASSERT(bSupportDp1_2 && "GPU supports DP1.4 should also support DP1.2!"); + } - gpuDP1_2Supported = supportDp1_2; - gpuDP1_4Supported = supportDp1_4; + gpuDPSupportedVersions = _gpuDPSupportedVersions; } void setGpuFECSupported(bool bSupportFEC) diff --git a/src/common/displayport/src/dp_connectorimpl.cpp b/src/common/displayport/src/dp_connectorimpl.cpp index db6d7b79e..451602945 100644 --- a/src/common/displayport/src/dp_connectorimpl.cpp +++ b/src/common/displayport/src/dp_connectorimpl.cpp @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -141,7 +141,7 @@ ConnectorImpl::ConnectorImpl(MainLink * main, AuxBus * auxBus, Timer * timer, Co // If a GPU is DP1.2 or DP1.4 supported then set these capalibilities. // This is used for accessing DP1.2/DP1.4 specific register space & features // - hal->setGpuDPSupportedVersions(main->isDP1_2Supported(), main->isDP1_4Supported()); + hal->setGpuDPSupportedVersions(main->getGpuDpSupportedVersions()); // Set if GPU supports FEC. Check panel FEC caps only if GPU supports it. hal->setGpuFECSupported(main->isFECSupported()); @@ -657,7 +657,7 @@ create: // where we toggle the link state. Only after this we should read DSC caps in this case. // Following this assesslink calls fireEvents() which will report // the new devies to clients and client will have the correct DSC caps. - // + // bool bGpuDscSupported; // Check GPU DSC Support @@ -1229,14 +1229,14 @@ bool ConnectorImpl::compoundQueryAttach(Group * target, { // // Bug 3692417 - // Color format should only depend on device doing DSC decompression when DSC is enabled according to DP Spec. - // But when Synaptics VMM5320 is the parent of the device doing DSC decompression, if a certain color + // Color format should only depend on device doing DSC decompression when DSC is enabled according to DP Spec. + // But when Synaptics VMM5320 is the parent of the device doing DSC decompression, if a certain color // format is not supported by Synaptics Virtual Peer Device decoder(parent), even though it is pass through mode - // and panel supports the color format, panel cannot light up. Once Synaptics fixes this issue, we will modify + // and panel supports the color format, panel cannot light up. Once Synaptics fixes this issue, we will modify // the WAR to be applied only before the firmware version that fixes it. // if ((modesetParams.colorFormat == dpColorFormat_RGB && !dev->parent->dscCaps.dscDecoderColorFormatCaps.bRgb) || - (modesetParams.colorFormat == dpColorFormat_YCbCr444 && !dev->parent->dscCaps.dscDecoderColorFormatCaps.bYCbCr444) || + (modesetParams.colorFormat == dpColorFormat_YCbCr444 && !dev->parent->dscCaps.dscDecoderColorFormatCaps.bYCbCr444) || (modesetParams.colorFormat == dpColorFormat_YCbCr422 && !dev->parent->dscCaps.dscDecoderColorFormatCaps.bYCbCrSimple422)) { if (pDscParams->forceDsc == DSC_FORCE_ENABLE) @@ -2548,17 +2548,18 @@ bool ConnectorImpl::setDeviceDscState(Device * dev, bool bEnableDsc) bool ConnectorImpl::notifyAttachBegin(Group * target, // Group of panels we're attaching to this head const DpModesetParams &modesetParams) { - unsigned twoChannelAudioHz = modesetParams.modesetInfo.twoChannelAudioHz; - unsigned eightChannelAudioHz = modesetParams.modesetInfo.eightChannelAudioHz; - NvU64 pixelClockHz = modesetParams.modesetInfo.pixelClockHz; - unsigned rasterWidth = modesetParams.modesetInfo.rasterWidth; - unsigned rasterHeight = modesetParams.modesetInfo.rasterHeight; - unsigned rasterBlankStartX = modesetParams.modesetInfo.rasterBlankStartX; - unsigned rasterBlankEndX = modesetParams.modesetInfo.rasterBlankEndX; - unsigned depth = modesetParams.modesetInfo.depth; - bool bLinkTrainingStatus = true; - bool bEnableDsc = modesetParams.modesetInfo.bEnableDsc; + unsigned twoChannelAudioHz = modesetParams.modesetInfo.twoChannelAudioHz; + unsigned eightChannelAudioHz = modesetParams.modesetInfo.eightChannelAudioHz; + NvU64 pixelClockHz = modesetParams.modesetInfo.pixelClockHz; + unsigned rasterWidth = modesetParams.modesetInfo.rasterWidth; + unsigned rasterHeight = modesetParams.modesetInfo.rasterHeight; + unsigned rasterBlankStartX = modesetParams.modesetInfo.rasterBlankStartX; + unsigned rasterBlankEndX = modesetParams.modesetInfo.rasterBlankEndX; + unsigned depth = modesetParams.modesetInfo.depth; + bool bLinkTrainingStatus = true; + bool bEnableDsc = modesetParams.modesetInfo.bEnableDsc; bool bEnableFEC; + bool bEnablePassThroughForPCON = modesetParams.modesetInfo.bEnablePassThroughForPCON; if(preferredLinkConfig.isValid()) { @@ -2676,7 +2677,14 @@ bool ConnectorImpl::notifyAttachBegin(Group * target, // Gr { for (Device * dev = target->enumDevices(0); dev; dev = target->enumDevices(dev)) { - if(!setDeviceDscState(dev, bEnableDsc)) + if (bPConConnected) + { + if (!(((DeviceImpl *)dev)->setDscEnableDPToHDMIPCON(bEnableDsc, bEnablePassThroughForPCON))) + { + DP_ASSERT(!"DP-CONN> Failed to configure DSC on DP to HDMI PCON!"); + } + } + else if(!setDeviceDscState(dev, bEnableDsc)) { DP_ASSERT(!"DP-CONN> Failed to configure DSC on Sink!"); } @@ -3995,11 +4003,11 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig) if ((groupAttached->dscModeRequest == DSC_DUAL) && (groupAttached->dscModeActive != DSC_DUAL)) { // - // If current modeset group requires 2Head1OR and + // If current modeset group requires 2Head1OR and // - group is not active yet (first modeset on the group) // - group is active but not in 2Head1OR mode (last modeset on the group did not require 2Head1OR) // then re-train the link - // This is because for 2Head1OR mode, we need to set some LT parametes for slave SOR after + // This is because for 2Head1OR mode, we need to set some LT parametes for slave SOR after // successful LT on primary SOR without which 2Head1OR modeset will lead to HW hang. // bTwoHeadOneOrLinkRetrain = true; @@ -4090,9 +4098,9 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig) // // Check if we are already trained to the desired link config? // Make sure requested FEC state matches with the current FEC state of link. - // If 2Head1OR mode is requested, retrain if group is not active or - // last modeset on active group was not in 2Head1OR mode. - // bTwoHeadOneOrLinkRetrain tracks this requirement. + // If 2Head1OR mode is requested, retrain if group is not active or + // last modeset on active group was not in 2Head1OR mode. + // bTwoHeadOneOrLinkRetrain tracks this requirement. // // @@ -4222,8 +4230,8 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig) // // Make sure link is physically active and healthy, otherwise re-train. // Make sure requested FEC state matches with the current FEC state of link. - // If 2Head1OR mode is requested, retrain if group is not active or last modeset on active group - // was not in 2Head1OR mode. bTwoHeadOneOrLinkRetrain tracks this requirement. + // If 2Head1OR mode is requested, retrain if group is not active or last modeset on active group + // was not in 2Head1OR mode. bTwoHeadOneOrLinkRetrain tracks this requirement. // bRetrainToEnsureLinkStatus = (isLinkActive() && isLinkInD3()) || isLinkLost() || @@ -5670,7 +5678,7 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected) if (hal->getSupportsMultistream() && main->hasMultistream()) { bool bDeleteFirmwareVC = false; - const DP_REGKEY_DATABASE& dpRegkeyDatabase = main->getRegkeyDatabase(); + DP_LOG(("DP> Multistream panel detected, building message manager")); // @@ -5679,7 +5687,6 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected) // messageManager = new MessageManager(hal, timer); messageManager->registerReceiver(&ResStatus); - messageManager->applyRegkeyOverrides(dpRegkeyDatabase); // // Create a discovery manager to initiate detection diff --git a/src/common/displayport/src/dp_deviceimpl.cpp b/src/common/displayport/src/dp_deviceimpl.cpp index 39ce07f87..da6759baf 100644 --- a/src/common/displayport/src/dp_deviceimpl.cpp +++ b/src/common/displayport/src/dp_deviceimpl.cpp @@ -1517,6 +1517,47 @@ bool DeviceImpl::setPanelReplayConfig(panelReplayConfig prcfg) return false; } +bool DeviceImpl::getPanelReplayStatus(PanelReplayStatus *pPrStatus) +{ + NvU8 state = 0; + unsigned size = 0; + unsigned nakReason = NakUndefined; + + if (pPrStatus == NULL) + { + DP_ASSERT(0); + return false; + } + + if(AuxBus::success == this->getDpcdData(NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS, + &state, sizeof(state), &size, &nakReason)) + { + switch (DRF_VAL(_DPCD20, _PANEL_REPLAY_AND_FRAME_LOCK_STATUS, _PR_STATUS, state)) + { + case NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_PR_STATUS_STATE_0: + pPrStatus->prState = PanelReplay_Inactive; + break; + + case NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_PR_STATUS_STATE_1: + pPrStatus->prState = PanelReplay_CaptureAndDisplay; + break; + + case NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_PR_STATUS_STATE_2: + pPrStatus->prState = PanelReplay_DisplayFromRfb; + break; + + default: + pPrStatus->prState = PanelReplay_Undefined; + break; + } + return true; + } + else + { + return false; + } +} + bool DeviceImpl::getFECSupport() { NvU8 byte = 0; @@ -2043,6 +2084,54 @@ bool DeviceImpl::setDscEnable(bool enable) } } + + +bool DeviceImpl::setDscEnableDPToHDMIPCON(bool bDscEnable, bool bEnablePassThroughForPCON) +{ + NvU8 dscEnableByte = 0; + unsigned size = 0; + unsigned nakReason = NakUndefined; + AuxBus::status dscEnableStatus = AuxBus::success; + Address::StringBuffer buffer; + DP_USED(buffer); + + if (!this->isDSCPossible()) + { + DP_LOG(("DP-DEV> DSC is not supported on DP to HDMI PCON - %s")); + return false; + } + + if (bDscEnable) + { + if(bEnablePassThroughForPCON) + { + dscEnableByte = FLD_SET_DRF(_DPCD20, _DSC_PASS_THROUGH, _ENABLE, _YES, dscEnableByte); + DP_LOG(("DP-DEV> Enabling DSC Pass through on DP to HDMI PCON device - %s", + this->getTopologyAddress().toString(buffer))); + } + else + { + dscEnableByte = FLD_SET_DRF(_DPCD14, _DSC_ENABLE, _SINK, _YES, dscEnableByte); + DP_LOG(("DP-DEV> Enabling DSC decompression on DP to HDMI PCON device - %s", + this->getTopologyAddress().toString(buffer))); + } + + } + + dscEnableStatus = this->setDpcdData(NV_DPCD14_DSC_ENABLE, + &dscEnableByte, sizeof dscEnableByte, &size, &nakReason); + + if (dscEnableStatus != AuxBus::success) + { + DP_LOG(("DP-DEV> Setting DSC Enable on DP to HDMI PCON %s failed", + this->getTopologyAddress().toString(buffer))); + return false; + + } + + return true; +} + unsigned DeviceImpl::getDscVersionMajor() { return dscCaps.versionMajor; diff --git a/src/common/displayport/src/dp_evoadapter.cpp b/src/common/displayport/src/dp_evoadapter.cpp index c69e4698a..b77a1ad49 100644 --- a/src/common/displayport/src/dp_evoadapter.cpp +++ b/src/common/displayport/src/dp_evoadapter.cpp @@ -93,9 +93,7 @@ const struct {NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE_MST, &dpRegkeyDatabase.bOptLinkKeptAliveMst, DP_REG_VAL_BOOL}, {NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE_SST, &dpRegkeyDatabase.bOptLinkKeptAliveSst, DP_REG_VAL_BOOL}, {NV_DP_REGKEY_FORCE_EDP_ILR, &dpRegkeyDatabase.bBypassEDPRevCheck, DP_REG_VAL_BOOL}, - {NV_DP_DSC_MST_CAP_BUG_3143315, &dpRegkeyDatabase.bDscMstCapBug3143315, DP_REG_VAL_BOOL}, - {NV_DP_REGKEY_NO_REPLY_TIMER_FOR_BUSY_WAITING, &dpRegkeyDatabase.bNoReplyTimerForBusyWaiting, DP_REG_VAL_BOOL}, - {NV_DP_REGKEY_DPCD_PROBING_FOR_BUSY_WAITING, &dpRegkeyDatabase.bDpcdProbingForBusyWaiting, DP_REG_VAL_BOOL} + {NV_DP_DSC_MST_CAP_BUG_3143315, &dpRegkeyDatabase.bDscMstCapBug3143315, DP_REG_VAL_BOOL} }; EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) : @@ -279,8 +277,9 @@ void EvoMainLink::queryGPUCapability() // MST feature on particular sku, whenever requested through INF. // _hasMultistream = (params.bIsMultistreamSupported == NV_TRUE) && !_isMstDisabledByRegkey; - _isDP1_2Supported = (params.bIsDp12Supported == NV_TRUE) ? true : false; - _isDP1_4Supported = (params.bIsDp14Supported == NV_TRUE) ? true : false; + + _gpuSupportedDpVersions = params.dpVersionsSupported; + _isStreamCloningEnabled = (params.bIsSCEnabled == NV_TRUE) ? true : false; _hasIncreasedWatermarkLimits = (params.bHasIncreasedWatermarkLimits == NV_TRUE) ? true : false; diff --git a/src/common/displayport/src/dp_messages.cpp b/src/common/displayport/src/dp_messages.cpp index 961baebc4..9f79d2535 100644 --- a/src/common/displayport/src/dp_messages.cpp +++ b/src/common/displayport/src/dp_messages.cpp @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2010-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -63,27 +63,19 @@ bool MessageManager::send(MessageManager::Message * message, NakData & nakData) DP_USED(sb); NvU64 startTime, elapsedTime; - - if (bNoReplyTimerForBusyWaiting) - { - message->bBusyWaiting = true; - } + message->bBusyWaiting = true; post(message, &completion); startTime = timer->getTimeUs(); do { - if (bDpcdProbingForBusyWaiting) + hal->updateDPCDOffline(); + if (hal->isDpcdOffline()) { - hal->updateDPCDOffline(); - if (hal->isDpcdOffline()) - { - DP_LOG(("DP-MM> Device went offline while waiting for reply and so ignoring message %p (ID = %02X, target = %s)", - (Message*)this, ((Message*)this)->requestIdentifier, (((Message*)this)->state.target).toString(sb))); - - nakData = completion.nakData; - completion.failed = true; - break; - } + DP_LOG(("DP-MM> Device went offline while waiting for reply and so ignoring message %p (ID = %02X, target = %s)", + message, message->requestIdentifier, ((message->state).target).toString(sb))); + nakData = completion.nakData; + completion.failed = true; + break; } hal->notifyIRQ(); diff --git a/src/common/inc/displayport/displayport.h b/src/common/inc/displayport/displayport.h index 7fcd9aed2..8be93d5c5 100644 --- a/src/common/inc/displayport/displayport.h +++ b/src/common/inc/displayport/displayport.h @@ -289,6 +289,7 @@ typedef struct { NvBool bSourceControlModeSupported; NvBool bConcurrentLTSupported; + NvBool bConv444To420Supported; NvU8 maxTmdsClkRate; NvU8 maxBpc; NvU8 maxHdmiLinkBandwidthGbps; @@ -458,6 +459,20 @@ typedef struct PanelReplayConfig NvBool enablePanelReplay; } panelReplayConfig; +// PR state +typedef enum +{ + PanelReplay_Inactive = 0, + PanelReplay_CaptureAndDisplay = 1, + PanelReplay_DisplayFromRfb = 2, + PanelReplay_Undefined = 7 +} PanelReplayState; + +typedef struct +{ + PanelReplayState prState; +} PanelReplayStatus; + // Multiplier constant to get link frequency in KHZ // Maximum link rate of Main Link lanes = Value x 270M. // To get it to KHz unit, we need to multiply 270K. diff --git a/src/common/inc/displayport/dpcd20.h b/src/common/inc/displayport/dpcd20.h index 2c523a02e..29ce9a750 100644 --- a/src/common/inc/displayport/dpcd20.h +++ b/src/common/inc/displayport/dpcd20.h @@ -47,6 +47,18 @@ #define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE_NO (0x00000000) #define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE_YES (0x00000001) +#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS (0x00002022) +#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_PR_STATUS 2:0 +#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_PR_STATUS_STATE_0 (0x00000000) +#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_PR_STATUS_STATE_1 (0x00000001) +#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_PR_STATUS_STATE_2 (0x00000002) +#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_PR_STATUS_STATE_ERROR (0x00000007) +#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED 4:3 +#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED_LOCKED (0x00000000) +#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED_COASTING (0x00000001) +#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED_GOVERNING (0x00000002) +#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED_RELOCKING (0x00000003) + // BRANCH SPECIFIC DSC CAPS #define NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0 (0x000000A0) #define NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0_VALUE 7:0 @@ -55,4 +67,4 @@ #define NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_1_VALUE 7:0 #define NV_DPCD20_BRANCH_DSC_MAXIMUM_LINE_BUFFER_WIDTH (0x000000A2) -#define NV_DPCD20_BRANCH_DSC_MAXIMUM_LINE_BUFFER_WIDTH_VALUE 7:0 \ No newline at end of file +#define NV_DPCD20_BRANCH_DSC_MAXIMUM_LINE_BUFFER_WIDTH_VALUE 7:0 diff --git a/src/common/inc/gps.h b/src/common/inc/gps.h new file mode 100644 index 000000000..671b0ebbc --- /dev/null +++ b/src/common/inc/gps.h @@ -0,0 +1,51 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2011-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef GPS_H +#define GPS_H + +#define GPS_REVISION_ID 0x00000100 +#define GPS_2X_REVISION_ID 0x00000200 + +#define GPS_FUNC_SUPPORT 0x00000000 // Bit list of supported functions +#define GPS_FUNC_GETOBJBYTYPE 0x00000010 // Fetch any specific Object by Type +#define GPS_FUNC_GETALLOBJS 0x00000011 // Fetch all Objects +#define GPS_FUNC_GETCALLBACKS 0x00000013 // Get system requested callbacks +#define GPS_FUNC_PCONTROL 0x0000001C // GPU power control function +#define GPS_FUNC_PSHARESTATUS 0x00000020 // Get system requested Power Steering settings +#define GPS_FUNC_GETPSS 0x00000021 // Get _PSS object +#define GPS_FUNC_SETPPC 0x00000022 // Set _PPC object +#define GPS_FUNC_GETPPC 0x00000023 // Get _PPC object +#define GPS_FUNC_GETPPL 0x00000024 // Get CPU package power limits +#define GPS_FUNC_SETPPL 0x00000025 // Set CPU package power limits +#define GPS_FUNC_GETTRL 0x00000026 // Get CPU turbo ratio limits +#define GPS_FUNC_SETTRL 0x00000027 // Set CPU turbo ratio limits +#define GPS_FUNC_GETPPM 0x00000028 // Get system power modes +#define GPS_FUNC_SETPPM 0x00000029 // Set system power modes +#define GPS_FUNC_PSHAREPARAMS 0x0000002A // Get sensor information and capabilities + +#define GPS_EVENT_STATUS_CHANGE 0x000000C0 // when received call GPS_FUNC_PCONTROL, + // depends on whether system is GPS enabled. + +#endif // GPS_H + diff --git a/src/common/inc/jt.h b/src/common/inc/jt.h new file mode 100644 index 000000000..d832df8b4 --- /dev/null +++ b/src/common/inc/jt.h @@ -0,0 +1,94 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef JT_H +#define JT_H + +// +// JT ACPI _DSM method related definitions +// +#define JT_REVISION_ID 0x00000103 // Revision number + +// subfunction 0 is common use: NV_ACPI_ALL_FUNC_SUPPORT +// #define JT_FUNC_SUPPORT 0x00000000 // Function is supported? +#define JT_FUNC_CAPS 0x00000001 // Capabilities +#define JT_FUNC_POLICYSELECT 0x00000002 // Query Policy Selector Status (reserved for future use) +#define JT_FUNC_POWERCONTROL 0x00000003 // dGPU Power Control +#define JT_FUNC_PLATPOLICY 0x00000004 // Query the Platform Policies (reserved for future use) +#define JT_FUNC_DISPLAYSTATUS 0x00000005 // Query the Display Hot-Key +#define JT_FUNC_MDTL 0x00000006 // Display Hot-Key Toggle List + +// +// JT_FUNC_CAPS return buffer definitions +// +#define NV_JT_FUNC_CAPS_JT_ENABLED 0:0 +#define NV_JT_FUNC_CAPS_JT_ENABLED_FALSE 0x00000000 +#define NV_JT_FUNC_CAPS_JT_ENABLED_TRUE 0x00000001 +#define NV_JT_FUNC_CAPS_NVSR_ENABLED 2:1 +#define NV_JT_FUNC_CAPS_NVSR_ENABLED_TRUE 0x00000000 +#define NV_JT_FUNC_CAPS_NVSR_ENABLED_FALSE 0x00000001 +#define NV_JT_FUNC_CAPS_PPR 4:3 +#define NV_JT_FUNC_CAPS_PPR_GC6 0x00000000 +#define NV_JT_FUNC_CAPS_PPR_GC6S3SR 0x00000002 +#define NV_JT_FUNC_CAPS_SRPR 5:5 +#define NV_JT_FUNC_CAPS_SRPR_PANEL 0x00000000 +#define NV_JT_FUNC_CAPS_SRPR_SUSPEND 0x00000001 +#define NV_JT_FUNC_CAPS_FBPR 7:6 +#define NV_JT_FUNC_CAPS_FBPR_GC6_ON 0x00000000 +#define NV_JT_FUNC_CAPS_FBPR_GC6_S3 0x00000002 +#define NV_JT_FUNC_CAPS_GPR 9:8 +#define NV_JT_FUNC_CAPS_GPR_COMBINED 0x00000000 +#define NV_JT_FUNC_CAPS_GPR_PERGPU 0x00000001 +#define NV_JT_FUNC_CAPS_GCR 10:10 +#define NV_JT_FUNC_CAPS_GCR_EXTERNAL 0x00000000 +#define NV_JT_FUNC_CAPS_GCR_INTEGRATED 0x00000001 +#define NV_JT_FUNC_CAPS_PTH_ENABLED 11:11 +#define NV_JT_FUNC_CAPS_PTH_ENABLED_YES 0x00000000 +#define NV_JT_FUNC_CAPS_PTH_ENABLED_NO 0x00000001 +#define NV_JT_FUNC_CAPS_NOT 12:12 +#define NV_JT_FUNC_CAPS_NOT_GC6DONE 0x00000000 +#define NV_JT_FUNC_CAPS_NOT_LINKCHANGE 0x00000001 +#define NV_JT_FUNC_CAPS_MSHYB_ENABLED 13:13 +#define NV_JT_FUNC_CAPS_MSHYB_ENABLED_FALSE 0x00000000 +#define NV_JT_FUNC_CAPS_MSHYB_ENABLED_TRUE 0x00000001 +#define NV_JT_FUNC_CAPS_RPC 14:14 +#define NV_JT_FUNC_CAPS_RPC_DEFAULT 0x00000000 +#define NV_JT_FUNC_CAPS_RPC_FINEGRAIN 0x00000001 +#define NV_JT_FUNC_CAPS_GC6V 16:15 +#define NV_JT_FUNC_CAPS_GC6V_GC6E 0x00000000 +#define NV_JT_FUNC_CAPS_GC6V_GC6A 0x00000001 +#define NV_JT_FUNC_CAPS_GC6V_GC6R 0x00000002 +#define NV_JT_FUNC_CAPS_GEI_ENABLED 17:17 +#define NV_JT_FUNC_CAPS_GEI_ENABLED_FALSE 0x00000000 +#define NV_JT_FUNC_CAPS_GEI_ENABLED_TRUE 0x00000001 +#define NV_JT_FUNC_CAPS_GSW_ENABLED 18:18 +#define NV_JT_FUNC_CAPS_GSW_ENABLED_FALSE 0x00000000 +#define NV_JT_FUNC_CAPS_GSW_ENABLED_TRUE 0x00000001 +#define NV_JT_FUNC_CAPS_REVISION_ID 31:20 +#define NV_JT_FUNC_CAPS_REVISION_ID_1_00 0x00000100 +#define NV_JT_FUNC_CAPS_REVISION_ID_1_01 0x00000101 +#define NV_JT_FUNC_CAPS_REVISION_ID_1_03 0x00000103 +#define NV_JT_FUNC_CAPS_REVISION_ID_2_00 0x00000200 + +#endif // JT_H + diff --git a/src/common/inc/mxm_spec.h b/src/common/inc/mxm_spec.h new file mode 100644 index 000000000..4536afdb0 --- /dev/null +++ b/src/common/inc/mxm_spec.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993 - 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _MXM_SPEC_H_ +#define _MXM_SPEC_H_ + +/**************** Resource Manager Defines and Structures ******************\ +* * +* Module: MXM_SPEC.H * +* Defines used for MXM * +\***************************************************************************/ + + +// MXM3.x ACPI revision ID +#define ACPI_MXM_REVISION_ID 0x00000300 // MXM revision ID + +// Subfunctions of _DSM in MXM 3.x +#define NV_ACPI_DSM_MXM_FUNC_MXSS 0x00000000 // Supported Sub-Functions +#define NV_ACPI_DSM_MXM_FUNC_MXMI 0x00000018 // Platform MXM Capabilities +#define NV_ACPI_DSM_MXM_FUNC_MXMS 0x00000010 // Get the MXM Structure +#define NV_ACPI_DSM_MXM_FUNC_MXPP 0x00000004 // Get/Set Platform Policies +#define NV_ACPI_DSM_MXM_FUNC_MXDP 0x00000005 // Get/Set Display Config +#define NV_ACPI_DSM_MXM_FUNC_MDTL 0x00000006 // Get Display Toggle List +#define NV_ACPI_DSM_MXM_FUNC_MXCB 0x00000019 // Get Callbacks +#define NV_ACPI_DSM_MXM_FUNC_GETEVENTLIST 0x00000012 // Get Event List +#endif // _MXM_SPEC_H_ diff --git a/src/common/inc/nbci.h b/src/common/inc/nbci.h new file mode 100644 index 000000000..56f8351c2 --- /dev/null +++ b/src/common/inc/nbci.h @@ -0,0 +1,48 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993 - 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NBCI_H_ +#define NBCI_H_ + +/****************************************************************************** + * + * Provides the NBCI (NoteBook Common Interface) spec defines for + * use by multiple clients. + * +******************************************************************************/ + +#define NBCI_REVISION_ID 0x00000102 + +// NBCI _DSM function codes +#define NV_NBCI_FUNC_SUPPORT 0x00000000 +#define NV_NBCI_FUNC_PLATCAPS 0x00000001 +#define NV_NBCI_FUNC_PLATPOLICY 0x00000004 +#define NV_NBCI_FUNC_DISPLAYSTATUS 0x00000005 +#define NV_NBCI_FUNC_MDTL 0x00000006 +#define NV_NBCI_FUNC_GETOBJBYTYPE 0x00000010 +#define NV_NBCI_FUNC_GETALLOBJS 0x00000011 +#define NV_NBCI_FUNC_GETEVENTLIST 0x00000012 +#define NV_NBCI_FUNC_CALLBACKS 0x00000013 +#define NV_NBCI_FUNC_GETBACKLIGHT 0x00000014 +#define NV_NBCI_FUNC_MSTL 0x00000015 +#endif // NBCI_H_ diff --git a/src/common/inc/nvBldVer.h b/src/common/inc/nvBldVer.h index 0b8600315..b6cf3b5d2 100644 --- a/src/common/inc/nvBldVer.h +++ b/src/common/inc/nvBldVer.h @@ -36,26 +36,26 @@ // and then checked back in. You cannot make changes to these sections without // corresponding changes to the buildmeister script #ifndef NV_BUILD_BRANCH - #define NV_BUILD_BRANCH r521_90 + #define NV_BUILD_BRANCH r525_00 #endif #ifndef NV_PUBLIC_BRANCH - #define NV_PUBLIC_BRANCH r521_90 + #define NV_PUBLIC_BRANCH r525_00 #endif #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) -#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r520/r521_90-315" -#define NV_BUILD_CHANGELIST_NUM (31900380) +#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r525/r525_00-154" +#define NV_BUILD_CHANGELIST_NUM (31993960) #define NV_BUILD_TYPE "Official" -#define NV_BUILD_NAME "rel/gpu_drv/r520/r521_90-315" -#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31900380) +#define NV_BUILD_NAME "rel/gpu_drv/r525/r525_00-154" +#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31993960) #else /* Windows builds */ -#define NV_BUILD_BRANCH_VERSION "r521_90-15" -#define NV_BUILD_CHANGELIST_NUM (31900380) +#define NV_BUILD_BRANCH_VERSION "r525_00-178" +#define NV_BUILD_CHANGELIST_NUM (31990457) #define NV_BUILD_TYPE "Official" -#define NV_BUILD_NAME "522.25" -#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31900380) -#define NV_BUILD_BRANCH_BASE_VERSION R520 +#define NV_BUILD_NAME "526.52" +#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31990457) +#define NV_BUILD_BRANCH_BASE_VERSION R525 #endif // End buildmeister python edited section diff --git a/src/common/inc/nvCpuIntrinsics.h b/src/common/inc/nvCpuIntrinsics.h new file mode 100644 index 000000000..e1829af5b --- /dev/null +++ b/src/common/inc/nvCpuIntrinsics.h @@ -0,0 +1,439 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1998,2015,2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __NV_CPU_INTRINSICS_H_ +#define __NV_CPU_INTRINSICS_H_ + +#include +#include "cpuopsys.h" +#include "nvtypes.h" + +///////////////////////////////////// +// Page size +///////////////////////////////////// + +#if defined(NV_UNIX) && !defined(NV_CPU_INTRINSICS_KERNEL) +// Page size is dynamic on all Unix systems +#include +#define __NV_MEM_PAGE_SIZE_BYTES getpagesize() +#else +// And is static for all other known architectures. +#define __NV_MEM_PAGE_SIZE_BYTES 4096 +#endif // defined(NV_UNIX) + +#define __NV_MEM_PAGE_SIZE_MASK (__NV_MEM_PAGE_SIZE_BYTES - 1) + +#define __NV_PAGE_PAD(x) \ + (((x) + __NV_MEM_PAGE_SIZE_MASK) & ~(__NV_MEM_PAGE_SIZE_MASK)) + +///////////////////////////////////// +// Cache line size +///////////////////////////////////// + +#if defined(NVCPU_PPC) +#define __NV_CACHE_LINE_BYTES 32 +#else +#define __NV_CACHE_LINE_BYTES 64 +#endif + +///////////////////////////////////// +// Spin loop hint +///////////////////////////////////// + +#if defined(NVCPU_X86_64) + +// PAUSE (aka REP NOP) opcode is low-power on x86_64 +#if defined(NV_GNU_INLINE_ASM) +#define NV_SPIN_LOOP_HINT() { \ + asm(".byte 0xf3\n\t" \ + ".byte 0x90\n\t"); \ +} +#else +#define NV_SPIN_LOOP_HINT() _mm_pause() +#endif + +#elif defined(NVCPU_X86) + +// PAUSE (aka REP NOP) opcode is low-power on P4's +#if defined(NV_GNU_INLINE_ASM) +#define NV_SPIN_LOOP_HINT() { \ + asm(".byte 0xf3\n\t" \ + ".byte 0x90\n\t"); \ +} +#else +#define NV_SPIN_LOOP_HINT() _mm_pause() +#endif + +#elif defined(NVCPU_PPC) + +#define NV_PPC_CACHE_LINE_SIZE_IN_BYTES 32 +#define NV_PPC_CACHE_LINE_SIZE_IN_U32S 8 + +// Not implemented yet +#define NV_SPIN_LOOP_HINT() + +#elif defined(NVCPU_FAMILY_ARM) || defined(NVCPU_PPC64LE) + +// Not implemented yet +#define NV_SPIN_LOOP_HINT() + +#else +#error Unknown CPU type +#endif + +///////////////////////////////////// +// Atomic operations +///////////////////////////////////// + +#if defined(__GNUC__) || defined(__clang__) + +// Include stdbool.h to pick up a definition of false to use with the +// __atomic_* intrinsics below. +#if !defined(__cplusplus) +#include +#endif // !defined(__cplusplus) + +// Sets a 32-bit variable to the specified value as an atomic operation. +// The function returns the initial value of the destination memory location. +static NV_FORCEINLINE int __NVatomicExchange(volatile int *location, int value) +{ + return __sync_lock_test_and_set(location, value); +} + +// Sets a pointer variable to the specified value as an atomic operation. +// The function returns the initial value of the destination memory location. +static NV_FORCEINLINE void* __NVatomicExchangePointer(void * volatile *location, void *value) +{ + return __sync_lock_test_and_set(location, value); +} + +// Performs an atomic compare-and-exchange operation on the specified values. The function compares two +// specified 32-bit values and exchanges with another 32-bit value based on the outcome of the comparison. +// The function returns the initial value of the destination memory location. +static NV_FORCEINLINE int __NVatomicCompareExchange(int volatile *location, int newValue, int oldValue) +{ + return __sync_val_compare_and_swap(location, oldValue, newValue); +} + +// Performs an atomic compare-and-exchange operation on the specified values. The function compares two +// specified 64-bit values and exchanges with another 64-bit value based on the outcome of the comparison. +// The function returns the initial value of the destination memory location. +static NV_FORCEINLINE NvS64 __NVatomicCompareExchange64(NvS64 volatile *location, NvS64 newValue, NvS64 oldValue) +{ +#if NVCPU_IS_ARM && !defined(__clang__) + // GCC doesn't provided an ARMv7 64-bit sync-and-swap intrinsic, so define + // one using inline assembly. + NvU32 oldValLow = NvU64_LO32(oldValue); + NvU32 oldValHigh = NvU64_HI32(oldValue); + NvU32 newValLow = NvU64_LO32(newValue); + NvU32 newValHigh = NvU64_HI32(newValue); + NvU32 outValLow; + NvU32 outValHigh; + NvU32 res; + + // The ldrexd and strexd instructions require use of an adjacent even/odd + // pair of registers. GCC supports quad-word register operands and + // modifiers to enable assignment of 64-bit values to two suitable 32-bit + // registers, but Clang does not. To work around this, explicitly request + // some suitable registers in the clobber list and manually shift the + // necessary data in/out of them as needed. + __asm__ __volatile__ ( + "1: ldrexd r2, r3, [%[loc]]\n" + " mov %[res], #0\n" + " mov %[outLo], r2\n" + " mov %[outHi], r3\n" + " mov r2, %[newLo]\n" + " mov r3, %[newHi]\n" + " teq %[outLo], %[oldLo]\n" + " itt eq\n" + " teqeq %[outHi], %[oldHi]\n" + " strexdeq %[res], r2, r3, [%[loc]]\n" + " teq %[res], #0\n" + " bne 1b\n" + // Outputs + : [res] "=&r" (res), + [outLo] "=&r" (outValLow), [outHi] "=&r" (outValHigh), + "+Qo" (*location) + // Inputs + : [loc] "r" (location), + [oldLo] "r" (oldValLow), [oldHi] "r" (oldValHigh), + [newLo] "r" (newValLow), [newHi] "r" (newValHigh) + // Clobbers + : "memory", "cc", "r2", "r3"); + + __asm__ __volatile__ ("dmb" ::: "memory"); + + return (NvS64)(((NvU64)outValHigh << 32llu) | (NvU64)outValLow); +#else + __atomic_compare_exchange_n(location, &oldValue, newValue, false, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); + return oldValue; +#endif +} + +// Performs an atomic compare-and-exchange operation on the specified values. The function compares two +// specified pointer values and exchanges with another pointer value based on the outcome of the comparison. +// The function returns the initial value of the destination memory location. +static NV_FORCEINLINE void* __NVatomicCompareExchangePointer(void * volatile *location, void *newValue, void *oldValue) +{ + return __sync_val_compare_and_swap(location, oldValue, newValue); +} + +// Increments (increases by one) the value of the specified 32-bit variable as an atomic operation. +// The function returns the resulting incremented value. +static NV_FORCEINLINE int __NVatomicIncrement(int volatile *location) +{ + return __sync_add_and_fetch(location, 1); +} + +// Decrements (decreases by one) the value of the specified 32-bit variable as an atomic operation. +// The function returns the resulting decremented value. +static NV_FORCEINLINE int __NVatomicDecrement(int volatile *location) +{ + return __sync_sub_and_fetch(location, 1); +} + +// Adds the values of the specified 32-bit variables as an atomic operation. +// The function returns the resulting added value. +static NV_FORCEINLINE int __NVatomicExchangeAdd(int volatile *location, int value) +{ + return __sync_add_and_fetch(location, value); +} + +#ifdef NV_CPU_QUERY_LSE_CAPS +/* + * Embedding hand coded instructions only for the inc/dec calls. These are the ones that + * get called very often. The __NVatomicCompareExchange() and other calls for example, + * are called only at init time, and a few times at most. So, keeping this hand-coding + * minimal, and to only the most used ones. + * + * Disassembly for reference: + * b820003e ldadd w0, w30, [x1] + * 0b1e0000 add w0, w0, w30 + * + * x16, x17, x30 are added to the clobber list since there could be veneers that maybe + * generated. + */ +static NV_FORCEINLINE int __NVatomicIncrement_LSE(int volatile *location) +{ + register int w0 asm ("w0") = 1; + register volatile int *x1 asm ("x1") = location; + + asm volatile + ( + ".inst 0xb820003e \n" + "add w0, w0, w30" + : "+r" (w0), "+r" (x1) + : "r" (x1) + : "x16", "x17", "x30", "memory" + ); + + return w0; +} + +static NV_FORCEINLINE int __NVatomicDecrement_LSE(int volatile *location) +{ + register int w0 asm ("w0") = (int32_t)-1; + register volatile int *x1 asm ("x1") = location; + + asm volatile + ( + ".inst 0xb820003e \n" + "add w0, w0, w30" + : "+r" (w0), "+r" (x1) + : "r" (x1) + : "x16", "x17", "x30", "memory" + ); + + return w0; +} +#endif + +#else + +#error undefined architecture + +#endif + +///////////////////////////////////// +// Bit scan operations +///////////////////////////////////// + +// __NV_clz(mask) provides a generic count-leading-zeros. If "mask" is 0, then the return value is undefined. +// __NV_ctz(mask) provides a generic count-trailing-zeros. If "mask" is 0, then the return value is undefined. +// +// __NVbsfFirst(), __NVbsfNext(), __NVbsrFirst() and __NVbsrNext() are helper functions to implement +// generic bit scan operations over a 32 bit mask long the following template: +// +// for (__NVbsfFirst(&index, &mask, maskInit); mask; __NVbsfNext(&index, &mask)) { ... } +// +// These operations are implemented using gcc/MSVC builtins/intrinsics. A test program to verify the correct +// functionality of these routines is available at //sw/pvt/ddadap/bitscantest.c +// +// The scan process provides the next valid "index". In __NVbsfNext() the bit corresponding to the passed in +// (1 << index) will be masked out. +// +// bsf scan from the lsb to the msb, while bsr scans from the msb to the lsb. +// +// The use of inlines and defines below is dictated by insufficiencies of MSVC ... + +#if defined (__GNUC__) || defined(__clang__) + +static NV_FORCEINLINE int __NV_clz(unsigned int mask) { + return __builtin_clz(mask); +} + +static NV_FORCEINLINE int __NV_ctz(unsigned int mask) { + return __builtin_ctz(mask); +} + +static NV_FORCEINLINE int __NV_clzll(unsigned long long mask) { + return __builtin_clzll(mask); +} + +static NV_FORCEINLINE int __NV_ctzll(unsigned long long mask) { + return __builtin_ctzll(mask); +} + +#define __BitScanForward(_pindex, _mask) *((_pindex)) = __NV_ctz((_mask)) +#define __BitScanReverse(_pindex, _mask) *((_pindex)) = 31 - __NV_clz((_mask)) +#define __BitScanForward64(_pindex, _mask) *((_pindex)) = __NV_ctzll((_mask)) +#define __BitScanReverse64(_pindex, _mask) *((_pindex)) = 63 - __NV_clzll((_mask)) + +#else + +#error Unsupported compiler + +#endif // MSVC_VER + +#ifndef __BitScanForward64 +// Implement bit scan forward for 64 bit using 32 bit instructions +static NV_FORCEINLINE void _BitScanForward64on32(unsigned int *index, NvU64 mask) +{ + const unsigned int lowMask = (unsigned int)(mask & 0xFFFFFFFFULL); + + if (lowMask != 0) { + __BitScanForward(index, lowMask); + } else { + const unsigned int highMask = (unsigned int)(mask >> 32); + __BitScanForward(index, highMask); + *index += 32; + } +} + +#define __BitScanForward64(_pindex, _mask) _BitScanForward64on32((_pindex), (_mask)) +#endif // __BitScanForward64 + +#ifndef __BitScanReverse64 +// Implement bit scan reverse for 64 bit using 32 bit instructions +static NV_FORCEINLINE void _BitScanReverse64on32(unsigned int *index, NvU64 mask) +{ + const unsigned int highMask = (unsigned int)(mask >> 32); + + if (highMask != 0) { + __BitScanReverse(index, highMask); + *index += 32; + } else { + const unsigned int lowMask = (unsigned int)(mask & 0xFFFFFFFFULL); + __BitScanReverse(index, lowMask); + } +} + +#define __BitScanReverse64(_pindex, _mask) _BitScanReverse64on32((_pindex), (_mask)) +#endif // __BitScanReverse64 + +static NV_FORCEINLINE void __NVbsfFirst(unsigned int *pindex, unsigned int *pmask, unsigned int maskInit) +{ + *pmask = maskInit; + __BitScanForward(pindex, maskInit); +} + +static NV_FORCEINLINE void __NVbsfNext(unsigned int *pindex, unsigned int *pmask) +{ + unsigned int index, mask; + + index = *pindex; + mask = *pmask ^ (1ul << index); + + *pmask = mask; + __BitScanForward(pindex, mask); +} + +static NV_FORCEINLINE void __NVbsrFirst(unsigned int *pindex, unsigned int *pmask, unsigned int maskInit) +{ + *pmask = maskInit; + __BitScanReverse(pindex, maskInit); +} + +static NV_FORCEINLINE void __NVbsrNext(unsigned int *pindex, unsigned int *pmask) +{ + unsigned int index, mask; + + index = *pindex; + mask = *pmask ^ (1ul << index); + + *pmask = mask; + __BitScanReverse(pindex, mask); +} + +// Variations for 64 bit maks +static NV_FORCEINLINE void __NVbsfFirst64(unsigned int *pindex, NvU64 *pmask, NvU64 maskInit) +{ + *pmask = maskInit; + __BitScanForward64(pindex, maskInit); +} + +static NV_FORCEINLINE void __NVbsfNext64(unsigned int *pindex, NvU64 *pmask) +{ + unsigned int index; + NvU64 mask; + + index = *pindex; + mask = *pmask ^ (1ULL << index); + + *pmask = mask; + __BitScanForward64(pindex, mask); +} + +static NV_FORCEINLINE void __NVbsrFirst64(unsigned int *pindex, NvU64 *pmask, NvU64 maskInit) +{ + *pmask = maskInit; + __BitScanReverse64(pindex, maskInit); +} + +static NV_FORCEINLINE void __NVbsrNext64(unsigned int *pindex, NvU64 *pmask) +{ + unsigned int index; + NvU64 mask; + + index = *pindex; + mask = *pmask ^ (1ULL << index); + + *pmask = mask; + __BitScanReverse64(pindex, mask); +} + +#undef __BitScanForward +#undef __BitScanReverse +#undef __BitScanForward64 +#undef __BitScanReverse64 + +#endif // __NV_CPU_INTRINSICS_H_ diff --git a/src/common/inc/nvPNPVendorIds.h b/src/common/inc/nvPNPVendorIds.h index 3f286ab2c..b1c423809 100644 --- a/src/common/inc/nvPNPVendorIds.h +++ b/src/common/inc/nvPNPVendorIds.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2009 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -60,6 +60,7 @@ static const PNPVendorId PNPVendorIds[] = { "___", _VENDOR_NAME_ENTRY("Targa") }, { "@@@", _VENDOR_NAME_ENTRY("Sangyo") }, + { "AAA", _VENDOR_NAME_ENTRY("Avolites Ltd") }, { "AAC", _VENDOR_NAME_ENTRY("Acer") }, { "ABC", _VENDOR_NAME_ENTRY("AboCom System Inc") }, { "ABP", _VENDOR_NAME_ENTRY("Advanced System Products") }, @@ -109,6 +110,7 @@ static const PNPVendorId PNPVendorIds[] = { "ATT", _VENDOR_NAME_ENTRY("AT&T") }, { "ATX", _VENDOR_NAME_ENTRY("Athenix") }, { "AUO", _VENDOR_NAME_ENTRY("AU Optronics Corporation") }, + { "AUS", _VENDOR_NAME_ENTRY("Asustek Computer Inc") }, { "AVI", _VENDOR_NAME_ENTRY("AIR") }, { "AVO", _VENDOR_NAME_ENTRY("Avocent Corporation") }, { "AZU", _VENDOR_NAME_ENTRY("Azura") }, @@ -249,6 +251,7 @@ static const PNPVendorId PNPVendorIds[] = { "HEI", _VENDOR_NAME_ENTRY("Hyundai") }, { "HIT", _VENDOR_NAME_ENTRY("Hitachi/HINT") }, { "HMX", _VENDOR_NAME_ENTRY("HUMAX Co., Ltd.") }, + { "HPN", _VENDOR_NAME_ENTRY("HP Inc.") }, { "HSD", _VENDOR_NAME_ENTRY("HannStar Display Corp") }, { "HSL", _VENDOR_NAME_ENTRY("Hansol") }, { "HTC", _VENDOR_NAME_ENTRY("Hitachi") }, @@ -312,6 +315,7 @@ static const PNPVendorId PNPVendorIds[] = { "LCS", _VENDOR_NAME_ENTRY("Longshine Electronics") }, { "LEF", _VENDOR_NAME_ENTRY("Leaf Systems") }, { "LEN", _VENDOR_NAME_ENTRY("Lenovo Group Limited") }, + { "LGD", _VENDOR_NAME_ENTRY("LG Display") }, { "LGE", _VENDOR_NAME_ENTRY("LG Electronics") }, { "LKM", _VENDOR_NAME_ENTRY("Likom/LKM") }, { "LNK", _VENDOR_NAME_ENTRY("Link Technologies") }, @@ -346,6 +350,7 @@ static const PNPVendorId PNPVendorIds[] = { "MMX", _VENDOR_NAME_ENTRY("MAG Technology") }, { "MOR", _VENDOR_NAME_ENTRY("Morse Technology") }, { "MSI", _VENDOR_NAME_ENTRY("Microstep") }, + { "MST", _VENDOR_NAME_ENTRY("MS Telematica") }, { "MSV", _VENDOR_NAME_ENTRY("Mosgi") }, { "MTC", _VENDOR_NAME_ENTRY("Mitac") }, { "MTI", _VENDOR_NAME_ENTRY("Morse Technology") }, diff --git a/src/common/inc/nvSemaphoreCommon.h b/src/common/inc/nvSemaphoreCommon.h new file mode 100644 index 000000000..9179007a2 --- /dev/null +++ b/src/common/inc/nvSemaphoreCommon.h @@ -0,0 +1,196 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NV_SEMAPHORE_H__ +#define __NV_SEMAPHORE_H__ + +#include "nvtypes.h" +#include "nvCpuIntrinsics.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + NvU32 payload; + NvU32 reportValue; + NvU64 timer; +} NvReportSemaphore32; + +typedef volatile struct { + NvU64 reportValue; + NvU64 timer; +} NvReportSemaphore64; + +typedef volatile union { + NvReportSemaphore32 sema32; + NvReportSemaphore64 sema64; +} NvReportSemaphore; + +/* + * These structures can't change size. They map to the GPU and other driver + * components expect the same size. + */ +ct_assert(sizeof(NvReportSemaphore32) == 16); +ct_assert(sizeof(NvReportSemaphore64) == 16); +ct_assert(sizeof(NvReportSemaphore) == 16); + +/* + * Pre-Volta GPUs can only read/write a 32-bit semaphore. Rather than try to + * use multiple semaphore writes to emulate a full 64-bit write, which is prone + * to race conditions when the value wraps, derive the full 64-bit value by + * comparing the current GPU-accessible value with the the last value written by + * the CPU or submitted to be written by the GPU, which is stashed in the + * timestamp field of the semaphore by the CPU in both these cases. + */ +static inline void NvTimeSemFermiSetMaxSubmitted( + NvReportSemaphore32 *report, + const NvU64 value) +{ + NvU64 oldValue = + (NvU64)__NVatomicCompareExchange64((volatile NvS64 *)&report->timer, + 0, 0); + + // Atomically set report->timer to max(value, report->time). + while (oldValue < value) { + const NvU64 prevValue = + (NvU64)__NVatomicCompareExchange64((volatile NvS64 *)&report->timer, + (NvS64)value, + (NvS64)oldValue); + if (prevValue == oldValue) { + // The specified value was set. Done. + nvAssert(report->timer >= value); + break; + } + + oldValue = prevValue; + } +} + +static inline NvU64 NvTimeSemFermiGetPayload( + NvReportSemaphore32 *report) +{ + // The ordering of the two operations below is critical. Other threads + // may be submitting GPU work that modifies the semaphore value, or + // modifying it from the CPU themselves. Both of those operations first + // set the 64-bit max submitted/timer value, then modify or submit work + // to modify the 32-bit payload value. Consider this hypothetical timeline + // if the order of operations below is reversed: + // + // thread1: + // -SetMaxSubmitted(0x1); + // -report->payload = 0x1; + // + // thread2: + // -Reads 0x1 from report->timer + // + // thread1: + // -SetMaxSubmitted(0x7fffffff); + // -report->payload = 0x7fffffff; + // -SetMaxSubmitted(0x100000000); + // -report->payload = 0x00000000; + // + // thread2: + // -Reads 0x0 from report->payload + // + // The logic below would see 0 (payload) is less than 1 (max submitted) and + // determine a wrap is outstanding, subtract one from the high 32-bits of + // the max submitted value (0x00000000 - 0x1), overflow, and return the + // current 64-bit value as 0xffffffff00000000 when the correct value is + // 0x100000000. To avoid this, we must read the payload prior to reading + // the max submitted value from the timer field. The logic can correctly + // adjust the max submitted value back down if a wrap occurs between these + // two operations, but has no way to bump the max submitted value up if a + // wrap occurs with the opposite ordering. + NvU64 current = report->payload; + // Use an atomic exchange to ensure the 64-bit read is atomic even on 32-bit + // CPUs. + NvU64 submitted = (NvU64) + __NVatomicCompareExchange64((volatile NvS64 *)&report->timer, 0ll, 0ll); + + nvAssert(!(current & 0xFFFFFFFF00000000ull)); + + // The value is monotonically increasing, and differ by no more than + // 2^31 - 1. Hence, if the low word of the submitted value is less + // than the low word of the current value, exactly one 32-bit wrap + // occurred between the current value and the most recently + // submitted value. Walk back the high word to match the value + // associated with the current GPU-visible value. + if ((submitted & 0xFFFFFFFFull) < current) { + submitted -= 0x100000000ull; + } + + current |= (submitted & 0xFFFFFFFF00000000ull); + + return current; +} + +static inline void NvTimeSemFermiSetPayload( + NvReportSemaphore32 *report, + const NvU64 payload) +{ + // First save the actual value to the reserved/timer bits + NvTimeSemFermiSetMaxSubmitted(report, payload); + + // Then write the low bits to the GPU-accessible semaphore value. + report->payload = (NvU32)(payload & 0xFFFFFFFFULL); +} + +/* + * Volta and up. + */ + +static inline NvU64 NvTimeSemVoltaGetPayload( + NvReportSemaphore64 *report) +{ + return (NvU64) + __NVatomicCompareExchange64((volatile NvS64 *)&report->reportValue, + 0, 0); +} + +static inline void NvTimeSemVoltaSetPayload( + NvReportSemaphore64 *report, + const NvU64 payload) +{ + NvU64 oldPayload = 0; + + while (NV_TRUE) { + NvU64 prevPayload = (NvU64) + __NVatomicCompareExchange64((volatile NvS64 *)&report->reportValue, + (NvS64)payload, (NvS64)oldPayload); + + if (prevPayload == oldPayload) { + break; + } + + nvAssert(prevPayload < payload); + + oldPayload = prevPayload; + } +} + +#ifdef __cplusplus +}; +#endif + +#endif /* __NV_SEMAPHORE_H__ */ diff --git a/src/common/inc/nvUnixVersion.h b/src/common/inc/nvUnixVersion.h index f1545bf73..a4befbdcc 100644 --- a/src/common/inc/nvUnixVersion.h +++ b/src/common/inc/nvUnixVersion.h @@ -4,7 +4,7 @@ #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \ (defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1) -#define NV_VERSION_STRING "520.56.06" +#define NV_VERSION_STRING "525.53" #else diff --git a/src/common/inc/nvctassert.h b/src/common/inc/nvctassert.h index ae3de5688..f2bae18fa 100644 --- a/src/common/inc/nvctassert.h +++ b/src/common/inc/nvctassert.h @@ -83,7 +83,7 @@ * e.g. msvc compiler: * error C2118: negative subscript or subscript is too large * e.g. gcc 2.95.3: - * size of array `_compile_time_assertion_failed_in_line_555' is negative + * size of array '_compile_time_assertion_failed_in_line_555' is negative * * In case the condition 'b' is not constant, the msvc compiler throws * an error: diff --git a/src/common/inc/nvhybridacpi.h b/src/common/inc/nvhybridacpi.h new file mode 100644 index 000000000..8a43a8a55 --- /dev/null +++ b/src/common/inc/nvhybridacpi.h @@ -0,0 +1,75 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993 - 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVHYBRID_ACPI_H +#define NVHYBRID_ACPI_H + +#if defined(__cplusplus) +extern "C" +{ +#endif // defined(__cplusplus) + +/***************************************************************************** +* +* Module: nvAcpi.h +* +* Description: +* Header file for ACPI related things, including Hybrid and MXM +* +******************************************************************************/ + + + +#define NVHG_FUNC_SUPPORT 0x00000000 // Supported Sub-Functions +#define NVHG_FUNC_HYBRIDCAPS 0x00000001 // Capabilities & Mutex +#define NVHG_FUNC_POLICYSELECT 0x00000002 // Query Policy Selector Status +#define NVHG_FUNC_POWERCONTROL 0x00000003 // dGPU Power Control +#define NVHG_FUNC_PLATPOLICY 0x00000004 // Query/Set Platform Policy +#define NVHG_FUNC_DISPLAYSTATUS 0x00000005 // Get Display & Hot-Key information +#define NVHG_FUNC_MDTL 0x00000006 // Display Toggle List +#define NVHG_FUNC_HCSMBLIST 0x00000007 // List of available addresses (MCP7x Desktop Only) +#define NVHG_FUNC_HCSMBADDR 0x00000008 // Returns the SMBus address (MCP7x Desktop Only) +#define NVHG_FUNC_HCREADBYTE 0x00000009 // Read a byte from the EC (MCP7x Desktop Only) +#define NVHG_FUNC_HCSENDBYTE 0x0000000a // Send a command byte to the EC (MCP7x Desktop Only) +#define NVHG_FUNC_HCGETSTATUS 0x0000000b // Querying the status of the Adapters' Hybrid EC after an SMbus Host Notify (MCP7x Desktop Only) +#define NVHG_FUNC_HCTRIGDDC 0x0000000c // Trigger reading a DDC block (Montevina Hybrid & MCP7x) +#define NVHG_FUNC_HCGETDDC 0x0000000d // Get the DDC block (Montevina Hybrid & MCP7x) +#define NVHG_FUNC_GETMEMTABLE 0x0000000e // Get the system memory configuration +#define NVHG_FUNC_GETMEMCFG 0x0000000f // Get the system video memory settings +#define NVHG_FUNC_GETOBJBYTYPE 0x00000010 // Get the firmware object +#define NVHG_FUNC_GETALLOBJS 0x00000011 // Get the directory and all objects + +#define NVHG_FUNC_GETEVENTLIST 0x00000012 // Get the List of required Event Notifiers and their meaning +#define NVHG_FUNC_CALLBACKS 0x00000013 // Get the list of system-required callbacks +#define NVHG_FUNC_GETBACKLIGHT 0x00000014 // Get the backlight table + +#define NVHG_ERROR_SUCCESS 0x00000000 // Success +#define NVHG_ERROR_UNSPECIFIED 0x80000001 // Generic unspecified error code +#define NVHG_ERROR_UNSUPPORTED 0x80000002 // FunctionCode or SubFunctionCode not supported by this system +#define NVHG_ERROR_PARM_INVALID 0x80000003 // Parameter is invalid (i.e. start page beyond end of buffer) + +#if defined(__cplusplus) +} // extern "C" +#endif // defined(__cplusplus) + +#endif // _NVHYBRID_ACPI_H_ diff --git a/src/common/inc/nvop.h b/src/common/inc/nvop.h new file mode 100644 index 000000000..98b367910 --- /dev/null +++ b/src/common/inc/nvop.h @@ -0,0 +1,122 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVOP_H +#define NVOP_H + +#define NVOP_REVISION_ID 0x00000100 + +// subfunction 0 is common use: NV_ACPI_ALL_FUNC_SUPPORT +// #define NVOP_FUNC_SUPPORT 0x00000000 // Bit list of supported functions* +#define NVOP_FUNC_DISPLAYSTATUS 0x00000005 // Query the Display Hot-Key** +#define NVOP_FUNC_MDTL 0x00000006 // Query Display Toggle List** +#define NVOP_FUNC_HCSMBADDR 0x00000007 // Get the SBIOS SMBus address for hybrid uController +#define NVOP_FUNC_GETOBJBYTYPE 0x00000010 // Get the Firmware Object* +#define NVOP_FUNC_GETALLOBJS 0x00000011 // Get the directory and all Objects * +#define NVOP_FUNC_OPTIMUSCAPS 0x0000001A // Optimus Capabilities*** +#define NVOP_FUNC_OPTIMUSFLAG 0x0000001B // Update GPU MultiFunction State to sbios +// * Required if any other functions are used. +// ** Required for Optimus-specific display hotkey functionality +// *** Required for Optimus-specific dGPU subsystem power control + +// Function 1A: OPTIMUSCAPS +// Args +#define NVOP_FUNC_OPTIMUSCAPS_FLAGS 0:0 +#define NVOP_FUNC_OPTIMUSCAPS_FLAGS_ABSENT 0x00000000 +#define NVOP_FUNC_OPTIMUSCAPS_FLAGS_PRESENT 0x00000001 +#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_TARGET 1:1 +#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_TARGET_SBIOS 0x00000000 +#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_TARGET_DRIVER 0x00000001 +#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_WR_EN 2:2 +#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_WR_EN_FALSE 0x00000000 +#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_WR_EN_TRUE 0x00000001 +#define NVOP_FUNC_OPTIMUSCAPS_POWER_CONTROL 25:24 +#define NVOP_FUNC_OPTIMUSCAPS_POWER_CONTROL_DONOT_POWER_DOWN_DGPU 0x00000002 +#define NVOP_FUNC_OPTIMUSCAPS_POWER_CONTROL_POWER_DOWN_DGPU 0x00000003 + +// Returns +#define NVOP_FUNC_OPTIMUSCAPS_OPTIMUS_STATE 0:0 +#define NVOP_FUNC_OPTIMUSCAPS_OPTIMUS_STATE_DISABLED 0x00000000 +#define NVOP_FUNC_OPTIMUSCAPS_OPTIMUS_STATE_ENABLED 0x00000001 +#define NVOP_FUNC_OPTIMUSCAPS_DGPU_POWER 4:3 +#define NVOP_FUNC_OPTIMUSCAPS_DGPU_POWER_OFF 0x00000000 +#define NVOP_FUNC_OPTIMUSCAPS_DGPU_POWER_RESERVED1 0x00000001 +#define NVOP_FUNC_OPTIMUSCAPS_DGPU_POWER_RESERVED2 0x00000002 +#define NVOP_FUNC_OPTIMUSCAPS_DGPU_POWER_STABILIZED 0x00000003 +#define NVOP_FUNC_OPTIMUSCAPS_DGPU_HOTPLUG_CAPABILITIES 6:6 +#define NVOP_FUNC_OPTIMUSCAPS_DGPU_HOTPLUG_CAPABILITIES_COCONNECTED 0x00000001 +#define NVOP_FUNC_OPTIMUSCAPS_DGPU_MUXED_DDC 7:7 +#define NVOP_FUNC_OPTIMUSCAPS_DGPU_MUXED_DDC_FALSE 0x00000000 +#define NVOP_FUNC_OPTIMUSCAPS_DGPU_MUXED_DDC_TRUE 0x00000001 +#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_ACTUAL 8:8 +#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_ACTUAL_SBIOS 0x00000000 +#define NVOP_FUNC_OPTIMUSCAPS_CFG_SPACE_OWNER_ACTUAL_DRIVER 0x00000001 +#define NVOP_FUNC_OPTIMUSCAPS_OPTIMUS_CAPABILITIES 26:24 +#define NVOP_FUNC_OPTIMUSCAPS_OPTIMUS_CAPABILITIES_ABSENT 0x00000000 +#define NVOP_FUNC_OPTIMUSCAPS_OPTIMUS_CAPABILITIES_DYNAMIC_POWER_CONTROL 0x00000001 +#define NVOP_FUNC_OPTIMUSCAPS_OPTIMUS_HDAUDIO_CAPABILITIES 28:27 +#define NVOP_FUNC_OPTIMUSCAPS_OPTIMUS_HDAUDIO_CAPABILITIES_ABSENT 0x00000000 +#define NVOP_FUNC_OPTIMUSCAPS_OPTIMUS_HDAUDIO_CAPABILITIES_DISABLED 0x00000001 +#define NVOP_FUNC_OPTIMUSCAPS_OPTIMUS_HDAUDIO_CAPABILITIES_PRESENT 0x00000002 + +// Function 1B: OPTIMUSFLAG +// Args +#define NVOP_FUNC_OPTIMUSFLAG_AUDIOCODEC_CONTROL 0:0 +#define NVOP_FUNC_OPTIMUSFLAG_AUDIOCODEC_CONTROL_DISABLE 0x00000000 +#define NVOP_FUNC_OPTIMUSFLAG_AUDIOCODEC_CONTROL_ENABLE 0x00000001 + +#define NVOP_FUNC_OPTIMUSFLAG_AUDIOCODEC_STATECHANGE_REQUEST 1:1 +#define NVOP_FUNC_OPTIMUSFLAG_AUDIOCODEC_STATECHANGE_REQUEST_IGNORE 0x00000000 +#define NVOP_FUNC_OPTIMUSFLAG_AUDIOCODEC_STATECHANGE_REQUEST_EXECUTE 0x00000001 + +#define NVOP_FUNC_OPTIMUSFLAG_APPLICATIONS_COUNT 9:2 + +#define NVOP_FUNC_OPTIMUSFLAG_APPLICATIONS_COUNT_CHANGE_REQUEST 10:10 +#define NVOP_FUNC_OPTIMUSFLAG_APPLICATIONS_COUNT_CHANGE_REQUEST_IGNORE 0x000000000 +#define NVOP_FUNC_OPTIMUSFLAG_APPLICATIONS_COUNT_CHANGE_REQUEST_EXECUTE 0x000000001 + + +// Function 1B: OPTIMUSFLAG +// return +#define NVOP_RET_OPTIMUSFLAG_AUDIOCODEC_STATE 0:0 +#define NVOP_RET_OPTIMUSFLAG_AUDIOCODEC_STATE_DISABLE 0x00000000 +#define NVOP_RET_OPTIMUSFLAG_AUDIOCODEC_STATE_ENABLE 0x00000001 + +#define NVOP_RET_OPTIMUSFLAG_POLICY 3:2 +#define NVOP_RET_OPTIMUSFLAG_POLICY_GPU_POWEROFF 0x00000000 +#define NVOP_RET_OPTIMUSFLAG_POLICY_GPU_POWERON 0x00000001 + +#define NVOP_RET_OPTIMUSFLAG_POLICYCHANGE_REQUEST 4:4 +#define NVOP_RET_OPTIMUSFLAG_POLICYCHANGE_REQUEST_IGNORE 0x00000000 +#define NVOP_RET_OPTIMUSFLAG_POLICYCHANGE_REQUEST_EXECUTE 0x00000001 + +#define NVOP_RET_OPTIMUSFLAG_FORCE_GPU_POLICY 6:5 +#define NVOP_RET_OPTIMUSFLAG_FORCE_GPU_POLICY_OPTIMUS 0x00000000 +#define NVOP_RET_OPTIMUSFLAG_FORCE_GPU_POLICY_IGPU 0x00000001 +#define NVOP_RET_OPTIMUSFLAG_FORCE_GPU_POLICY_DGPU 0x00000002 + +#define NVOP_RET_OPTIMUSFLAG_FORCE_GPU_REQUEST 7:7 +#define NVOP_RET_OPTIMUSFLAG_FORCE_GPU_REQUEST_IGNORE 0x00000000 +#define NVOP_RET_OPTIMUSFLAG_FORCE_GPU_REQUEST_EXECUTE 0x00000001 +#endif // NVOP_H + diff --git a/src/common/inc/pex.h b/src/common/inc/pex.h new file mode 100644 index 000000000..e21ab56df --- /dev/null +++ b/src/common/inc/pex.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef PEX_H +#define PEX_H + +#define PEX_REVISION_ID 0x00000002 + +// subfunction 0 is common use: NV_ACPI_ALL_FUNC_SUPPORT +// #define PEX_FUNC_GETSUPPORTFUNCTION 0x00000000 // Get supported function +#define PEX_FUNC_GETSLOTINFO 0x00000001 // Get PCI Express Slot Information +#define PEX_FUNC_GETSLOTNUMBER 0x00000002 // Get PCI Express Slot Number +#define PEX_FUNC_GETVENDORTOKENID 0x00000003 // Get PCI Express Vendor Specific Token ID strings +#define PEX_FUNC_GETPCIBUSCAPS 0x00000004 // Get PCI Express Root Bus Capabilities +#define PEX_FUNC_IGNOREPCIBOOTCONFIG 0x00000005 // Indication to OS that PCI Boot config can be ignored +#define PEX_FUNC_GETLTRLATENCY 0x00000006 // Get PCI Express Latency Tolerance Reporting Info +#define PEX_FUNC_NAMEPCIDEVICE 0x00000007 // Get name of PCI or PCIE device +#define PEX_FUNC_SETLTRLATENCY 0x00000008 // Set PCI Express Latency Tolerance Reporting Values + +#endif // PEX_H diff --git a/src/common/inc/swref/published/ada/ad102/dev_bus.h b/src/common/inc/swref/published/ada/ad102/dev_bus.h new file mode 100644 index 000000000..30005f9a2 --- /dev/null +++ b/src/common/inc/swref/published/ada/ad102/dev_bus.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef ad102_dev_nv_bus_h +#define ad102_dev_nv_bus_h + +#define NV_PBUS_SW_SCRATCH(i) (0x00001400+(i)*4) /* RW-4A */ +#define NV_PBUS_SW_SCRATCH__SIZE_1 64 /* */ +#define NV_PBUS_SW_SCRATCH_FIELD 31:0 /* RWIVF */ +#define NV_PBUS_SW_SCRATCH_FIELD_INIT 0x00000000 /* RWI-V */ + +#endif // ad102_dev_nv_bus_h diff --git a/src/common/inc/swref/published/ada/ad102/dev_bus_addendum.h b/src/common/inc/swref/published/ada/ad102/dev_bus_addendum.h new file mode 100644 index 000000000..e1a616721 --- /dev/null +++ b/src/common/inc/swref/published/ada/ad102/dev_bus_addendum.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef ad102_dev_nv_bus_addendum_h +#define ad102_dev_nv_bus_addendum_h + +// Scratch bits for Global EROT Grant scratch bits +#define NV_PBUS_SW_GLOBAL_EROT_GRANT NV_PBUS_SW_SCRATCH(0) +#define NV_PBUS_SW_GLOBAL_EROT_GRANT_VALID 3:3 +#define NV_PBUS_SW_GLOBAL_EROT_GRANT_VALID_YES 1 +#define NV_PBUS_SW_GLOBAL_EROT_GRANT_VALID_NO 0 +#define NV_PBUS_SW_GLOBAL_EROT_GRANT_REQUEST 4:4 +#define NV_PBUS_SW_GLOBAL_EROT_GRANT_REQUEST_SET 1 +#define NV_PBUS_SW_GLOBAL_EROT_GRANT_REQUEST_CLEAR 0 +#define NV_PBUS_SW_GLOBAL_EROT_GRANT_ALLOW 5:5 +#define NV_PBUS_SW_GLOBAL_EROT_GRANT_ALLOW_YES 1 +#define NV_PBUS_SW_GLOBAL_EROT_GRANT_ALLOW_NO 0 + +#endif // ad102_dev_nv_bus_addendum_h diff --git a/src/common/inc/swref/published/disp/v03_00/dev_disp.h b/src/common/inc/swref/published/disp/v03_00/dev_disp.h index 138efcbf3..9b655541e 100644 --- a/src/common/inc/swref/published/disp/v03_00/dev_disp.h +++ b/src/common/inc/swref/published/disp/v03_00/dev_disp.h @@ -23,45 +23,51 @@ #ifndef __v03_00_dev_disp_h__ #define __v03_00_dev_disp_h__ -#define NV_PDISP_CHN_NUM_CORE 0 /* */ -#define NV_PDISP_CHN_NUM_WIN(i) (1+(i)) /* */ -#define NV_PDISP_CHN_NUM_WIN__SIZE_1 32 /* */ -#define NV_PDISP_CHN_NUM_WINIM(i) (33+(i)) /* */ -#define NV_PDISP_CHN_NUM_WINIM__SIZE_1 32 /* */ -#define NV_PDISP_CHN_NUM_CURS(i) (73+(i)) /* */ -#define NV_PDISP_CHN_NUM_CURS__SIZE_1 8 /* */ -#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* R--VF */ -#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */ -#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* R---V */ -#define NV_PDISP_FE_SW 0x00640FFF:0x00640000 /* RW--D */ -#define NV_PDISP_SF_USER_0 0x006F03FF:0x006F0000 /* RW--D */ -#define NV_UDISP_HASH_BASE 0x00000000 /* */ -#define NV_UDISP_HASH_LIMIT 0x00001FFF /* */ -#define NV_UDISP_OBJ_MEM_BASE 0x00002000 /* */ -#define NV_UDISP_OBJ_MEM_LIMIT 0x0000FFFF /* */ -#define NV_UDISP_HASH_TBL_CLIENT_ID (1*32+13):(1*32+0) /* RWXVF */ -#define NV_UDISP_HASH_TBL_INSTANCE (1*32+24):(1*32+14) /* RWXUF */ -#define NV_UDISP_HASH_TBL_CHN (1*32+31):(1*32+25) /* RWXUF */ -#define NV_DMA_TARGET_NODE (0*32+1):(0*32+0) /* RWXVF */ -#define NV_DMA_TARGET_NODE_PHYSICAL_NVM 0x00000001 /* RW--V */ -#define NV_DMA_TARGET_NODE_PHYSICAL_PCI 0x00000002 /* RW--V */ -#define NV_DMA_TARGET_NODE_PHYSICAL_PCI_COHERENT 0x00000003 /* RW--V */ -#define NV_DMA_ACCESS (0*32+2):(0*32+2) /* RWXVF */ -#define NV_DMA_ACCESS_READ_ONLY 0x00000000 /* RW--V */ -#define NV_DMA_ACCESS_READ_AND_WRITE 0x00000001 /* RW--V */ -#define NV_DMA_KIND (0*32+20):(0*32+20) /* RWXVF */ -#define NV_DMA_KIND_PITCH 0x00000000 /* RW--V */ -#define NV_DMA_KIND_BLOCKLINEAR 0x00000001 /* RW--V */ -#define NV_DMA_ADDRESS_BASE_LO (1*32+31):(1*32+0) /* RWXUF */ -#define NV_DMA_ADDRESS_BASE_HI (2*32+6):(2*32+0) /* RWXUF */ -#define NV_DMA_ADDRESS_LIMIT_LO (3*32+31):(3*32+0) /* RWXUF */ -#define NV_DMA_ADDRESS_LIMIT_HI (4*32+6):(4*32+0) /* RWXUF */ -#define NV_DMA_SIZE 20 /* */ -#define NV_UDISP_FE_CHN_ASSY_BASEADR_CORE 0x00680000 /* */ -#define NV_UDISP_FE_CHN_ARMED_BASEADR_CORE (0x00680000+32768) /* */ -#define NV_UDISP_FE_CHN_ASSY_BASEADR_WIN(i) ((0x00690000+(i)*4096)) /* */ -#define NV_UDISP_FE_CHN_ASSY_BASEADR_WINIM(i) ((0x00690000+((i+32)*4096))) /* */ -#define NV_UDISP_FE_CHN_ASSY_BASEADR_CURS(i) (0x006D8000+(i)*4096) /* RW-4A */ -#define NV_UDISP_FE_CHN_ASSY_BASEADR(i) ((i)>0?(((0x00690000+(i-1)*4096))):0x00680000) /* */ -#define NV_UDISP_FE_CHN_ASSY_BASEADR__SIZE_1 81 /* */ +#define NV_PDISP_CHN_NUM_CORE 0 /* */ +#define NV_PDISP_CHN_NUM_WIN(i) (1+(i)) /* */ +#define NV_PDISP_CHN_NUM_WIN__SIZE_1 32 /* */ +#define NV_PDISP_CHN_NUM_WINIM(i) (33+(i)) /* */ +#define NV_PDISP_CHN_NUM_WINIM__SIZE_1 32 /* */ +#define NV_PDISP_CHN_NUM_CURS(i) (73+(i)) /* */ +#define NV_PDISP_CHN_NUM_CURS__SIZE_1 8 /* */ +#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */ +#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_SW 0x00640FFF:0x00640000 /* RW--D */ +#define NV_PDISP_SF_USER_0 0x006F03FF:0x006F0000 /* RW--D */ +#define NV_UDISP_HASH_BASE 0x00000000 /* */ +#define NV_UDISP_HASH_LIMIT 0x00001FFF /* */ +#define NV_UDISP_OBJ_MEM_BASE 0x00002000 /* */ +#define NV_UDISP_OBJ_MEM_LIMIT 0x0000FFFF /* */ +#define NV_UDISP_HASH_TBL_CLIENT_ID (1*32+13):(1*32+0) /* RWXVF */ +#define NV_UDISP_HASH_TBL_INSTANCE (1*32+24):(1*32+14) /* RWXUF */ +#define NV_UDISP_HASH_TBL_CHN (1*32+31):(1*32+25) /* RWXUF */ +#define NV_DMA_TARGET_NODE (0*32+1):(0*32+0) /* RWXVF */ +#define NV_DMA_TARGET_NODE_PHYSICAL_NVM 0x00000001 /* RW--V */ +#define NV_DMA_TARGET_NODE_PHYSICAL_PCI 0x00000002 /* RW--V */ +#define NV_DMA_TARGET_NODE_PHYSICAL_PCI_COHERENT 0x00000003 /* RW--V */ +#define NV_DMA_ACCESS (0*32+2):(0*32+2) /* RWXVF */ +#define NV_DMA_ACCESS_READ_ONLY 0x00000000 /* RW--V */ +#define NV_DMA_ACCESS_READ_AND_WRITE 0x00000001 /* RW--V */ +#define NV_DMA_KIND (0*32+20):(0*32+20) /* RWXVF */ +#define NV_DMA_KIND_PITCH 0x00000000 /* RW--V */ +#define NV_DMA_KIND_BLOCKLINEAR 0x00000001 /* RW--V */ +#define NV_DMA_ADDRESS_BASE_LO (1*32+31):(1*32+0) /* RWXUF */ +#define NV_DMA_ADDRESS_BASE_HI (2*32+6):(2*32+0) /* RWXUF */ +#define NV_DMA_ADDRESS_LIMIT_LO (3*32+31):(3*32+0) /* RWXUF */ +#define NV_DMA_ADDRESS_LIMIT_HI (4*32+6):(4*32+0) /* RWXUF */ +#define NV_DMA_SIZE 20 /* */ +#define NV_UDISP_FE_CHN_ASSY_BASEADR_CORE 0x00680000 /* */ +#define NV_UDISP_FE_CHN_ARMED_BASEADR_CORE (0x00680000+32768) /* */ +#define NV_UDISP_FE_CHN_ASSY_BASEADR_WIN(i) ((0x00690000+(i)*4096)) /* */ +#define NV_UDISP_FE_CHN_ASSY_BASEADR_WINIM(i) ((0x00690000+((i+32)*4096))) /* */ +#define NV_UDISP_FE_CHN_ASSY_BASEADR_CURS(i) (0x006D8000+(i)*4096) /* RW-4A */ +#define NV_UDISP_FE_CHN_ASSY_BASEADR(i) ((i)>0?(((0x00690000+(i-1)*4096))):0x00680000) /* */ +#define NV_UDISP_FE_CHN_ASSY_BASEADR__SIZE_1 81 /* */ +#define NV_PDISP_RG_DPCA(i) (0x00616330+(i)*2048) /* R--4A */ +#define NV_PDISP_RG_DPCA__SIZE_1 8 /* */ +#define NV_PDISP_RG_DPCA_LINE_CNT 15:0 /* R--UF */ +#define NV_PDISP_RG_DPCA_FRM_CNT 31:16 /* R--UF */ +#define NV_PDISP_FE_FLIPLOCK 0x0061206C /* RW-4R */ +#define NV_PDISP_FE_FLIPLOCK_LSR_MIN_TIME 23:0 /* RWIVF */ #endif // __v03_00_dev_disp_h__ diff --git a/src/common/inc/swref/published/nv_arch.h b/src/common/inc/swref/published/nv_arch.h index 507ce6f1d..b09551c75 100644 --- a/src/common/inc/swref/published/nv_arch.h +++ b/src/common/inc/swref/published/nv_arch.h @@ -103,6 +103,10 @@ #define GPU_IMPLEMENTATION_AD104 0x04 +#define GPU_IMPLEMENTATION_AD106 0x06 + +#define GPU_IMPLEMENTATION_AD107 0x07 + #define GPU_IMPLEMENTATION_T124 0x00 #define GPU_IMPLEMENTATION_T132 0x00 #define GPU_IMPLEMENTATION_T210 0x00 diff --git a/src/common/inc/swref/published/nv_ref.h b/src/common/inc/swref/published/nv_ref.h index 1ca011257..5db05b3b8 100644 --- a/src/common/inc/swref/published/nv_ref.h +++ b/src/common/inc/swref/published/nv_ref.h @@ -149,6 +149,13 @@ #define NV_PMC_BOOT_42_ARCHITECTURE 28:24 /* */ #define NV_PMC_BOOT_42_CHIP_ID 28:20 /* R-XVF */ +#define NV_PMC_BOOT_42_ARCHITECTURE_TU100 0x00000016 /* */ +#define NV_PMC_BOOT_42_ARCHITECTURE_GA100 0x00000017 /* */ +#define NV_PMC_BOOT_42_ARCHITECTURE_GH100 0x00000018 /* */ +#define NV_PMC_BOOT_42_ARCHITECTURE_AD100 0x00000019 /* */ + +#define NV_PMC_BOOT_42_CHIP_ID_GA100 0x00000170 /* */ + /* dev_arapb_misc.h */ #define NV_PAPB_MISC_GP_HIDREV_CHIPID 15:8 /* ----F */ #define NV_PAPB_MISC_GP_HIDREV_MAJORREV 7:4 /* ----F */ diff --git a/src/common/inc/swref/published/nvswitch/lr10/dev_minion_ip.h b/src/common/inc/swref/published/nvswitch/lr10/dev_minion_ip.h index c6f6a76e7..273379f88 100644 --- a/src/common/inc/swref/published/nvswitch/lr10/dev_minion_ip.h +++ b/src/common/inc/swref/published/nvswitch/lr10/dev_minion_ip.h @@ -24,7 +24,6 @@ #ifndef __lr10_dev_minion_ip_h__ #define __lr10_dev_minion_ip_h__ /* This file is autogenerated. Do not edit */ -// did not include the regs that weren't approved for Tegra #define NV_CMINION_FALCON_CG2 0x00000134 /* RWI4R */ #define NV_CMINION_FALCON_CG2_SLCG 17:1 /* */ #define NV_CMINION_FALCON_CG2_SLCG_ENABLED 0 /* */ diff --git a/src/common/inc/swref/published/nvswitch/lr10/dev_soe_ip.h b/src/common/inc/swref/published/nvswitch/lr10/dev_soe_ip.h index 6bb1d563f..e4ebe1f59 100644 --- a/src/common/inc/swref/published/nvswitch/lr10/dev_soe_ip.h +++ b/src/common/inc/swref/published/nvswitch/lr10/dev_soe_ip.h @@ -284,7 +284,7 @@ #define NV_SOE_FALCON_MAILBOX1 0x0044 /* RW-4R */ #define NV_SOE_FALCON_MAILBOX1_DATA 31:0 /* RWIVF */ #define NV_SOE_FALCON_MAILBOX1_DATA_INIT 0x00000000 /* RWI-V */ -// check if all of these should be added + #define NV_SOE_FALCON_CPUCTL 0x0100 /* RW-4R */ #define NV_SOE_FALCON_CPUCTL_IINVAL 0:0 /* -WXVF */ #define NV_SOE_FALCON_CPUCTL_IINVAL_TRUE 0x00000001 /* -W--V */ diff --git a/src/common/inc/swref/published/nvswitch/lr10/dev_soe_ip_addendum.h b/src/common/inc/swref/published/nvswitch/lr10/dev_soe_ip_addendum.h index f0c6fe8fe..e8b663886 100644 --- a/src/common/inc/swref/published/nvswitch/lr10/dev_soe_ip_addendum.h +++ b/src/common/inc/swref/published/nvswitch/lr10/dev_soe_ip_addendum.h @@ -23,13 +23,6 @@ #ifndef __lr10_dev_soe_ip_addendum_h__ #define __lr10_dev_soe_ip_addendum_h__ -// -// The detail description about each of the mutex can be found in -// /drivers/resman/arch/nvalloc/common/inc/nv_mutex.h -// -// Enums in the following file will also need to be updated: -// /drivers/nvswitch/common/inc/soemutexreservation.h -// #define NV_SOE_MUTEX_DEFINES \ NV_MUTEX_ID_SOE_EMEM_ACCESS, \ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_cpr_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_cpr_ip.h new file mode 100644 index 000000000..dab2e7c45 --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_cpr_ip.h @@ -0,0 +1,108 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_cpr_ip_h__ +#define __ls10_dev_cpr_ip_h__ +#define NV_CPR_SYS_NVLW_CG1 0x00000110 /* RW-4R */ +#define NV_CPR_SYS_NVLW_CG1_SLCG 0:0 /* RWEVF */ +#define NV_CPR_SYS_NVLW_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ +#define NV_CPR_SYS_NVLW_CG1_SLCG_DISABLED 0x00000001 /* RWE-V */ +#define NV_CPR_SYS_NVLW_CG1_SLCG__PROD 0x00000000 /* RW--V */ +#define NV_CPR_SYS_INTR_CTRL(i) (0x00000130+(i)*0x4) /* RW-4A */ +#define NV_CPR_SYS_INTR_CTRL__SIZE_1 3 /* */ +#define NV_CPR_SYS_INTR_CTRL_MESSAGE 31:0 /* RWEVF */ +#define NV_CPR_SYS_INTR_CTRL_MESSAGE_INIT 0x00000000 /* RWE-V */ +#define NV_CPR_SYS_INTR_RETRIGGER(i) (0x00000150+(i)*0x4) /* RW-4A */ +#define NV_CPR_SYS_INTR_RETRIGGER__SIZE_1 3 /* */ +#define NV_CPR_SYS_INTR_RETRIGGER_TRIGGER 0:0 /* RWEVF */ +#define NV_CPR_SYS_INTR_RETRIGGER_TRIGGER__ONWRITE "oneToSet" /* */ +#define NV_CPR_SYS_INTR_RETRIGGER_TRIGGER_INIT 0x00000000 /* RWE-V */ +#define NV_CPR_SYS_INTR_RETRIGGER_TRIGGER_TRUE 0x00000001 /* RW--V */ +#define NV_CPR_SYS_NVLW_INTR_0_STATUS 0x000001a0 /* R--4R */ +#define NV_CPR_SYS_NVLW_INTR_0_STATUS_CPR_INTR 0:0 /* R-EVF */ +#define NV_CPR_SYS_NVLW_INTR_0_STATUS_CPR_INTR_INIT 0x00000000 /* R-E-V */ +#define NV_CPR_SYS_NVLW_INTR_0_STATUS_INTR0 31:31 /* R-EVF */ +#define NV_CPR_SYS_NVLW_INTR_0_STATUS_INTR0_INIT 0x00000000 /* R-E-V */ +#define NV_CPR_SYS_NVLW_INTR_1_STATUS 0x000001a4 /* R--4R */ +#define NV_CPR_SYS_NVLW_INTR_1_STATUS_CPR_INTR 0:0 /* R-EVF */ +#define NV_CPR_SYS_NVLW_INTR_1_STATUS_CPR_INTR_INIT 0x00000000 /* R-E-V */ +#define NV_CPR_SYS_NVLW_INTR_1_STATUS_INTR1 31:31 /* R-EVF */ +#define NV_CPR_SYS_NVLW_INTR_1_STATUS_INTR1_INIT 0x00000000 /* R-E-V */ +#define NV_CPR_SYS_NVLW_INTR_2_STATUS 0x000001a8 /* R--4R */ +#define NV_CPR_SYS_NVLW_INTR_2_STATUS_CPR_INTR 0:0 /* R-EVF */ +#define NV_CPR_SYS_NVLW_INTR_2_STATUS_CPR_INTR_INIT 0x00000000 /* R-E-V */ +#define NV_CPR_SYS_NVLW_INTR_2_STATUS_INTR2 31:31 /* R-EVF */ +#define NV_CPR_SYS_NVLW_INTR_2_STATUS_INTR2_INIT 0x00000000 /* R-E-V */ +#define NV_CPR_SYS_NVLW_INTR_0_MASK 0x000001c0 /* RW-4R */ +#define NV_CPR_SYS_NVLW_INTR_0_MASK_CPR_INTR 0:0 /* RWEVF */ +#define NV_CPR_SYS_NVLW_INTR_0_MASK_CPR_INTR_ENABLE 0x00000001 /* RW--V */ +#define NV_CPR_SYS_NVLW_INTR_0_MASK_CPR_INTR_DISABLE 0x00000000 /* RWE-V */ +#define NV_CPR_SYS_NVLW_INTR_0_MASK_INTR0 1:1 /* RWEVF */ +#define NV_CPR_SYS_NVLW_INTR_0_MASK_INTR0_ENABLE 0x00000001 /* RW--V */ +#define NV_CPR_SYS_NVLW_INTR_0_MASK_INTR0_DISABLE 0x00000000 /* RWE-V */ +#define NV_CPR_SYS_NVLW_INTR_1_MASK 0x000001c4 /* RW-4R */ +#define NV_CPR_SYS_NVLW_INTR_1_MASK_CPR_INTR 0:0 /* RWEVF */ +#define NV_CPR_SYS_NVLW_INTR_1_MASK_CPR_INTR_ENABLE 0x00000001 /* RW--V */ +#define NV_CPR_SYS_NVLW_INTR_1_MASK_CPR_INTR_DISABLE 0x00000000 /* RWE-V */ +#define NV_CPR_SYS_NVLW_INTR_1_MASK_INTR1 1:1 /* RWEVF */ +#define NV_CPR_SYS_NVLW_INTR_1_MASK_INTR1_ENABLE 0x00000001 /* RW--V */ +#define NV_CPR_SYS_NVLW_INTR_1_MASK_INTR1_DISABLE 0x00000000 /* RWE-V */ +#define NV_CPR_SYS_NVLW_INTR_2_MASK 0x000001c8 /* RW-4R */ +#define NV_CPR_SYS_NVLW_INTR_2_MASK_CPR_INTR 0:0 /* RWEVF */ +#define NV_CPR_SYS_NVLW_INTR_2_MASK_CPR_INTR_ENABLE 0x00000001 /* RW--V */ +#define NV_CPR_SYS_NVLW_INTR_2_MASK_CPR_INTR_DISABLE 0x00000000 /* RWE-V */ +#define NV_CPR_SYS_NVLW_INTR_2_MASK_INTR2 1:1 /* RWEVF */ +#define NV_CPR_SYS_NVLW_INTR_2_MASK_INTR2_ENABLE 0x00000001 /* RW--V */ +#define NV_CPR_SYS_NVLW_INTR_2_MASK_INTR2_DISABLE 0x00000000 /* RWE-V */ +#define NV_CPR_SYS_ERR_STATUS_0 0x00000200 /* RW-4R */ +#define NV_CPR_SYS_ERR_STATUS_0_ENGINE_RESET_ERR 0:0 /* RWIVF */ +#define NV_CPR_SYS_ERR_STATUS_0_ENGINE_RESET_ERR__ONWRITE "oneToClear" /* */ +#define NV_CPR_SYS_ERR_STATUS_0_ENGINE_RESET_ERR_NONE 0x00000000 /* RWI-V */ +#define NV_CPR_SYS_ERR_STATUS_0_ENGINE_RESET_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_CPR_SYS_ERR_LOG_EN_0 0x00000204 /* RW-4R */ +#define NV_CPR_SYS_ERR_LOG_EN_0_ENGINE_RESET_ERR 0:0 /* RWEVF */ +#define NV_CPR_SYS_ERR_LOG_EN_0_ENGINE_RESET_ERR__PROD 0x00000001 /* RW--V */ +#define NV_CPR_SYS_ERR_LOG_EN_0_ENGINE_RESET_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_CPR_SYS_ERR_LOG_EN_0_ENGINE_RESET_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_CPR_SYS_ERR_FATAL_REPORT_EN_0 0x00000208 /* RW-4R */ +#define NV_CPR_SYS_ERR_FATAL_REPORT_EN_0_ENGINE_RESET_ERR 0:0 /* RWEVF */ +#define NV_CPR_SYS_ERR_FATAL_REPORT_EN_0_ENGINE_RESET_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_CPR_SYS_ERR_FATAL_REPORT_EN_0_ENGINE_RESET_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_CPR_SYS_ERR_NON_FATAL_REPORT_EN_0 0x0000020c /* RW-4R */ +#define NV_CPR_SYS_ERR_NON_FATAL_REPORT_EN_0_ENGINE_RESET_ERR 0:0 /* RWEVF */ +#define NV_CPR_SYS_ERR_NON_FATAL_REPORT_EN_0_ENGINE_RESET_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_CPR_SYS_ERR_NON_FATAL_REPORT_EN_0_ENGINE_RESET_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_CPR_SYS_ERR_CORRECTABLE_REPORT_EN_0 0x00000210 /* RW-4R */ +#define NV_CPR_SYS_ERR_CORRECTABLE_REPORT_EN_0_ENGINE_RESET_ERR 0:0 /* RWEVF */ +#define NV_CPR_SYS_ERR_CORRECTABLE_REPORT_EN_0_ENGINE_RESET_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_CPR_SYS_ERR_CORRECTABLE_REPORT_EN_0_ENGINE_RESET_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_CPR_SYS_ERR_CONTAIN_EN_0 0x00000214 /* RW-4R */ +#define NV_CPR_SYS_ERR_CONTAIN_EN_0_ENGINE_RESET_ERR 0:0 /* RWEVF */ +#define NV_CPR_SYS_ERR_CONTAIN_EN_0_ENGINE_RESET_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_CPR_SYS_ERR_CONTAIN_EN_0_ENGINE_RESET_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_CPR_SYS_ERR_FIRST_0 0x0000021c /* RW-4R */ +#define NV_CPR_SYS_ERR_FIRST_0_ENGINE_RESET_ERR 0:0 /* RWIVF */ +#define NV_CPR_SYS_ERR_FIRST_0_ENGINE_RESET_ERR__ONWRITE "oneToClear" /* */ +#define NV_CPR_SYS_ERR_FIRST_0_ENGINE_RESET_ERR_NONE 0x00000000 /* RWI-V */ +#define NV_CPR_SYS_ERR_FIRST_0_ENGINE_RESET_ERR_CLEAR 0x00000001 /* RW--V */ +#endif // __ls10_dev_cpr_ip_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_ctrl_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_ctrl_ip.h new file mode 100644 index 000000000..0d2138e62 --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_ctrl_ip.h @@ -0,0 +1,68 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_ctrl_ip_h__ +#define __ls10_dev_ctrl_ip_h__ +/* This file is autogenerated. Do not edit */ +#define NV_CTRL 0x0001FFFF:0x00000000 /* RW--D */ +#define NV_CTRL_CPU_INTR_TOP(i) (0x00013400+(i)*4) /* R--4A */ +#define NV_CTRL_CPU_INTR_TOP__SIZE_1 64 /* */ +#define NV_CTRL_CPU_INTR_TOP_VALUE 31:0 /* R--VF */ +#define NV_CTRL_CPU_INTR_TOP_EN_SET(i) (0x00013800+(i)*4) /* RW-4A */ +#define NV_CTRL_CPU_INTR_TOP_EN_SET__SIZE_1 64 /* */ +#define NV_CTRL_CPU_INTR_TOP_EN_SET_VALUE 31:0 /* RWIVF */ +#define NV_CTRL_CPU_INTR_TOP_EN_SET_VALUE_INIT 0x00000000 /* R-I-V */ +#define NV_CTRL_CPU_INTR_TOP_EN_CLEAR(i) (0x00013C00+(i)*4) /* RW-4A */ +#define NV_CTRL_CPU_INTR_TOP_EN_CLEAR__SIZE_1 64 /* */ +#define NV_CTRL_CPU_INTR_TOP_EN_CLEAR_VALUE 31:0 /* RWIVF */ +#define NV_CTRL_CPU_INTR_TOP_EN_CLEAR_VALUE_INIT 0x00000000 /* R-I-V */ +#define NV_CTRL_CPU_INTR_LEAF(i) (0x00014000+(i)*4) /* RW-4A */ +#define NV_CTRL_CPU_INTR_LEAF__SIZE_1 1024 /* */ +#define NV_CTRL_CPU_INTR_LEAF_VALUE 31:0 /* RWIVF */ +#define NV_CTRL_CPU_INTR_LEAF_VALUE_INIT 0x00000000 /* R-I-V */ +#define NV_CTRL_CPU_INTR_LEAF_ARRAY_SIZE_PER_FN 16 /* */ +#define NV_CTRL_CPU_INTR_LEAF_EN_SET(i) (0x00018000+(i)*4) /* RW-4A */ +#define NV_CTRL_CPU_INTR_LEAF_EN_SET__SIZE_1 1024 /* */ +#define NV_CTRL_CPU_INTR_LEAF_EN_SET_VALUE 31:0 /* RWIVF */ +#define NV_CTRL_CPU_INTR_LEAF_EN_SET_VALUE_INIT 0x00000000 /* R-I-V */ +#define NV_CTRL_CPU_INTR_LEAF_EN_CLEAR(i) (0x0001C000+(i)*4) /* RW-4A */ +#define NV_CTRL_CPU_INTR_LEAF_EN_CLEAR__SIZE_1 1024 /* */ +#define NV_CTRL_CPU_INTR_LEAF_EN_CLEAR_VALUE 31:0 /* RWIVF */ +#define NV_CTRL_CPU_INTR_LEAF_EN_CLEAR_VALUE_INIT 0x00000000 /* R-I-V */ +#define NV_CTRL_CPU_INTR_LEAF_TRIGGER(i) (0x00006C00+(i)*4) /* -W-4A */ +#define NV_CTRL_CPU_INTR_LEAF_TRIGGER__SIZE_1 64 /* */ +#define NV_CTRL_CPU_INTR_LEAF_TRIGGER_VECTOR 11:0 /* -WXVF */ +#define NV_CTRL_PRI_CTRL_CG1 0x00006A00 /* RW-4R */ +#define NV_CTRL_PRI_CTRL_CG1_SLCG 2:1 /* */ +#define NV_CTRL_PRI_CTRL_CG1_SLCG_ENABLED 0x00000000 /* */ +#define NV_CTRL_PRI_CTRL_CG1_SLCG_DISABLED 0x00000003 /* */ +#define NV_CTRL_PRI_CTRL_CG1_SLCG__PROD 0x00000000 /* */ +#define NV_CTRL_PRI_CTRL_CG1_SLCG_CTRLPRI 1:1 /* RWIVF */ +#define NV_CTRL_PRI_CTRL_CG1_SLCG_CTRLPRI_ENABLED 0x00000000 /* RW--V */ +#define NV_CTRL_PRI_CTRL_CG1_SLCG_CTRLPRI_DISABLED 0x00000001 /* RWI-V */ +#define NV_CTRL_PRI_CTRL_CG1_SLCG_CTRLPRI__PROD 0x00000000 /* RW--V */ +#define NV_CTRL_PRI_CTRL_CG1_SLCG_MSIX 2:2 /* RWIVF */ +#define NV_CTRL_PRI_CTRL_CG1_SLCG_MSIX_ENABLED 0x00000000 /* RW--V */ +#define NV_CTRL_PRI_CTRL_CG1_SLCG_MSIX_DISABLED 0x00000001 /* RWI-V */ +#define NV_CTRL_PRI_CTRL_CG1_SLCG_MSIX__PROD 0x00000000 /* RW--V */ +#endif // __ls10_dev_ctrl_ip_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_ctrl_ip_addendum.h b/src/common/inc/swref/published/nvswitch/ls10/dev_ctrl_ip_addendum.h new file mode 100644 index 000000000..813824463 --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_ctrl_ip_addendum.h @@ -0,0 +1,65 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_ctrl_ip_addendum_h__ +#define __ls10_dev_ctrl_ip_addendum_h__ +// +// GIN _LEAF() mapping to IP blocks +// Refer to "Table 74. Laguna interrupt sources" in Laguna Seca IAS +// +#define NV_CTRL_CPU_INTR_NVLW_FATAL_IDX 0 +#define NV_CTRL_CPU_INTR_NVLW_NON_FATAL_IDX 1 +#define NV_CTRL_CPU_INTR_NVLW_CORRECTABLE_IDX 2 +#define NV_CTRL_CPU_INTR_NPG_FATAL_IDX 5 +#define NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX 6 +#define NV_CTRL_CPU_INTR_NPG_CORRECTABLE_IDX 7 +#define NV_CTRL_CPU_INTR_NXBAR_FATAL_IDX 8 +#define NV_CTRL_CPU_INTR_UNITS_IDX 9 +#define NV_CTRL_CPU_INTR_NVLW_FATAL NV_CTRL_CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NVLW_FATAL_IDX) +#define NV_CTRL_CPU_INTR_NVLW_FATAL_MASK 15:0 +#define NV_CTRL_CPU_INTR_NVLW_NON_FATAL NV_CTRL_CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NVLW_NON_FATAL_IDX) +#define NV_CTRL_CPU_INTR_NVLW_NON_FATAL_MASK 15:0 +#define NV_CTRL_CPU_INTR_NVLW_CORRECTABLE NV_CTRL_CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NVLW_CORRECTABLE_IDX) +#define NV_CTRL_CPU_INTR_NVLW_CORRECTABLE_MASK 15:0 +#define NV_CTRL_CPU_INTR_NPG_FATAL NV_CTRL_CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NPG_FATAL_IDX) +#define NV_CTRL_CPU_INTR_NPG_FATAL_MASK 15:0 +#define NV_CTRL_CPU_INTR_NPG_NON_FATAL NV_CTRL_CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX) +#define NV_CTRL_CPU_INTR_NPG_NON_FATAL_MASK 15:0 +#define NV_CTRL_CPU_INTR_NPG_CORRECTABLE NV_CTRL_CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NPG_CORRECTABLE_IDX) +#define NV_CTRL_CPU_INTR_NPG_CORRECTABLE_MASK 15:0 +#define NV_CTRL_CPU_INTR_NXBAR_FATAL NV_CTRL_CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NXBAR_FATAL_IDX) +#define NV_CTRL_CPU_INTR_NXBAR_FATAL_MASK 2:0 +#define NV_CTRL_CPU_INTR_UNITS NV_CTRL_CPU_INTR_LEAF(NV_CTRL_CPU_INTR_UNITS_IDX) +#define NV_CTRL_CPU_INTR_UNITS_PMGR_HOST 0:0 +#define NV_CTRL_CPU_INTR_UNITS_PTIMER 1:1 +#define NV_CTRL_CPU_INTR_UNITS_PTIMER_ALARM 2:2 +#define NV_CTRL_CPU_INTR_UNITS_SEC0_INTR0_0 7:7 +#define NV_CTRL_CPU_INTR_UNITS_SEC0_NOTIFY_0 8:8 +#define NV_CTRL_CPU_INTR_UNITS_SOE_SHIM_ILLEGAL_OP 11:11 +#define NV_CTRL_CPU_INTR_UNITS_SOE_SHIM_FLUSH 12:12 +#define NV_CTRL_CPU_INTR_UNITS_XTL_CPU 13:13 +#define NV_CTRL_CPU_INTR_UNITS_XAL_EP 14:14 +#define NV_CTRL_CPU_INTR_UNITS_PRIV_RING 15:15 +#define NV_CTRL_CPU_INTR_UNITS_FSP 16:16 + +#endif // __ls10_dev_ctrl_ip_addendum_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_egress_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_egress_ip.h new file mode 100644 index 000000000..2bf7b319a --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_egress_ip.h @@ -0,0 +1,1373 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_egress_ip_h__ +#define __ls10_dev_egress_ip_h__ +/* This file is autogenerated. Do not edit */ +#define NV_EGRESS 0x00004fff:0x00004000 /* RW--D */ +#define NV_EGRESS_CTRL 0x00004040 /* RW-4R */ +#define NV_EGRESS_CTRL_ZERO_OUT_SWXATTR_DISABLE 0:0 /* RWEVF */ +#define NV_EGRESS_CTRL_ZERO_OUT_SWXATTR_DISABLE_OFF 0x00000000 /* RWE-V */ +#define NV_EGRESS_CTRL_ZERO_OUT_SWXATTR_DISABLE_ON 0x00000001 /* RW--V */ +#define NV_EGRESS_CTRL_CTO_ENB 9:9 /* RWEVF */ +#define NV_EGRESS_CTRL_CTO_ENB_ON 0x00000001 /* RWE-V */ +#define NV_EGRESS_CTRL_CTO_ENB_OFF 0x00000000 /* RW--V */ +#define NV_EGRESS_CTRL_CTO_ENB__TPROD 0x00000000 /* RW--V */ +#define NV_EGRESS_CTO_TIMER_LIMIT 0x00004048 /* RW-4R */ +#define NV_EGRESS_CTO_TIMER_LIMIT_LIMIT 19:0 /* RWEVF */ +#define NV_EGRESS_CTO_TIMER_LIMIT_LIMIT_INIT 0x00003e77 /* RWE-V */ +#define NV_EGRESS_BUFFER_POINTERS0 0x00004310 /* R--4R */ +#define NV_EGRESS_BUFFER_POINTERS0_WRITE 7:0 /* R-EVF */ +#define NV_EGRESS_BUFFER_POINTERS0_WRITE_INIT 0x00000000 /* R-E-V */ +#define NV_EGRESS_BUFFER_POINTERS0_READ 23:16 /* R-EVF */ +#define NV_EGRESS_BUFFER_POINTERS0_READ_INIT 0x00000000 /* R-E-V */ +#define NV_EGRESS_BUFFER_POINTERS1 0x00004314 /* R--4R */ +#define NV_EGRESS_BUFFER_POINTERS1_WRITE 7:0 /* R-EVF */ +#define NV_EGRESS_BUFFER_POINTERS1_WRITE_INIT 0x00000000 /* R-E-V */ +#define NV_EGRESS_BUFFER_POINTERS1_READ 23:16 /* R-EVF */ +#define NV_EGRESS_BUFFER_POINTERS1_READ_INIT 0x00000000 /* R-E-V */ +#define NV_EGRESS_BUFFER_POINTERS2 0x00004318 /* R--4R */ +#define NV_EGRESS_BUFFER_POINTERS2_WRITE 7:0 /* R-EVF */ +#define NV_EGRESS_BUFFER_POINTERS2_WRITE_INIT 0x00000000 /* R-E-V */ +#define NV_EGRESS_BUFFER_POINTERS2_READ 23:16 /* R-EVF */ +#define NV_EGRESS_BUFFER_POINTERS2_READ_INIT 0x00000000 /* R-E-V */ +#define NV_EGRESS_BUFFER_POINTERS3 0x0000431c /* R--4R */ +#define NV_EGRESS_BUFFER_POINTERS3_WRITE 7:0 /* R-EVF */ +#define NV_EGRESS_BUFFER_POINTERS3_WRITE_INIT 0x00000000 /* R-E-V */ +#define NV_EGRESS_BUFFER_POINTERS3_READ 23:16 /* R-EVF */ +#define NV_EGRESS_BUFFER_POINTERS3_READ_INIT 0x00000000 /* R-E-V */ +#define NV_EGRESS_BUFFER_POINTERS4 0x00004320 /* R--4R */ +#define NV_EGRESS_BUFFER_POINTERS4_WRITE 7:0 /* R-EVF */ +#define NV_EGRESS_BUFFER_POINTERS4_WRITE_INIT 0x00000000 /* R-E-V */ +#define NV_EGRESS_BUFFER_POINTERS4_READ 23:16 /* R-EVF */ +#define NV_EGRESS_BUFFER_POINTERS4_READ_INIT 0x00000000 /* R-E-V */ +#define NV_EGRESS_BUFFER_POINTERS5 0x00004324 /* R--4R */ +#define NV_EGRESS_BUFFER_POINTERS5_WRITE 7:0 /* R-EVF */ +#define NV_EGRESS_BUFFER_POINTERS5_WRITE_INIT 0x00000040 /* R-E-V */ +#define NV_EGRESS_BUFFER_POINTERS5_READ 23:16 /* R-EVF */ +#define NV_EGRESS_BUFFER_POINTERS5_READ_INIT 0x00000040 /* R-E-V */ +#define NV_EGRESS_BUFFER_POINTERS6 0x00004328 /* R--4R */ +#define NV_EGRESS_BUFFER_POINTERS6_WRITE 7:0 /* R-EVF */ +#define NV_EGRESS_BUFFER_POINTERS6_WRITE_INIT 0x00000080 /* R-E-V */ +#define NV_EGRESS_BUFFER_POINTERS6_READ 23:16 /* R-EVF */ +#define NV_EGRESS_BUFFER_POINTERS6_READ_INIT 0x00000080 /* R-E-V */ +#define NV_EGRESS_BUFFER_POINTERS7 0x0000432c /* R--4R */ +#define NV_EGRESS_BUFFER_POINTERS7_WRITE 7:0 /* R-EVF */ +#define NV_EGRESS_BUFFER_POINTERS7_WRITE_INIT 0x000000c0 /* R-E-V */ +#define NV_EGRESS_BUFFER_POINTERS7_READ 23:16 /* R-EVF */ +#define NV_EGRESS_BUFFER_POINTERS7_READ_INIT 0x000000c0 /* R-E-V */ +#define NV_EGRESS_NCISOC_CREDIT0 0x00004370 /* R--4R */ +#define NV_EGRESS_NCISOC_CREDIT0_NUM 9:0 /* R-IVF */ +#define NV_EGRESS_NCISOC_CREDIT0_NUM_INIT 0x00000000 /* R-I-V */ +#define NV_EGRESS_NCISOC_CREDIT1 0x00004374 /* R--4R */ +#define NV_EGRESS_NCISOC_CREDIT1_NUM 9:0 /* R-IVF */ +#define NV_EGRESS_NCISOC_CREDIT1_NUM_INIT 0x00000000 /* R-I-V */ +#define NV_EGRESS_NCISOC_CREDIT2 0x00004378 /* R--4R */ +#define NV_EGRESS_NCISOC_CREDIT2_NUM 9:0 /* R-IVF */ +#define NV_EGRESS_NCISOC_CREDIT2_NUM_INIT 0x00000000 /* R-I-V */ +#define NV_EGRESS_NCISOC_CREDIT3 0x0000437c /* R--4R */ +#define NV_EGRESS_NCISOC_CREDIT3_NUM 9:0 /* R-IVF */ +#define NV_EGRESS_NCISOC_CREDIT3_NUM_INIT 0x00000000 /* R-I-V */ +#define NV_EGRESS_NCISOC_CREDIT4 0x00004380 /* R--4R */ +#define NV_EGRESS_NCISOC_CREDIT4_NUM 9:0 /* R-IVF */ +#define NV_EGRESS_NCISOC_CREDIT4_NUM_INIT 0x00000000 /* R-I-V */ +#define NV_EGRESS_NCISOC_CREDIT5 0x00004384 /* R--4R */ +#define NV_EGRESS_NCISOC_CREDIT5_NUM 9:0 /* R-IVF */ +#define NV_EGRESS_NCISOC_CREDIT5_NUM_INIT 0x00000000 /* R-I-V */ +#define NV_EGRESS_NCISOC_CREDIT6 0x00004388 /* R--4R */ +#define NV_EGRESS_NCISOC_CREDIT6_NUM 9:0 /* R-IVF */ +#define NV_EGRESS_NCISOC_CREDIT6_NUM_INIT 0x00000000 /* R-I-V */ +#define NV_EGRESS_NCISOC_CREDIT7 0x0000438c /* R--4R */ +#define NV_EGRESS_NCISOC_CREDIT7_NUM 9:0 /* R-IVF */ +#define NV_EGRESS_NCISOC_CREDIT7_NUM_INIT 0x00000000 /* R-I-V */ +#define NV_EGRESS_ERR_STATUS_0 0x00004400 /* RW-4R */ +#define NV_EGRESS_ERR_STATUS_0_EGRESSBUFERR 0:0 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_0_EGRESSBUFERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_0_EGRESSBUFERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_0_EGRESSBUFERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_0_PKTROUTEERR 1:1 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_0_PKTROUTEERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_0_PKTROUTEERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_0_PKTROUTEERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_0_SEQIDERR 2:2 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_0_SEQIDERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_0_SEQIDERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_0_SEQIDERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_0_NXBAR_HDR_ECC_LIMIT_ERR 3:3 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_0_NXBAR_HDR_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_0_NXBAR_HDR_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_0_NXBAR_HDR_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_0_NXBAR_HDR_ECC_DBE_ERR 4:4 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_0_NXBAR_HDR_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_0_NXBAR_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_0_NXBAR_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_0_RAM_OUT_HDR_ECC_LIMIT_ERR 5:5 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_0_RAM_OUT_HDR_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_0_RAM_OUT_HDR_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_0_RAM_OUT_HDR_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_0_RAM_OUT_HDR_ECC_DBE_ERR 6:6 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_0_RAM_OUT_HDR_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_0_RAM_OUT_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_0_RAM_OUT_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_0_NCISOCCREDITOVFL 7:7 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_0_NCISOCCREDITOVFL__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_0_NCISOCCREDITOVFL_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_0_NCISOCCREDITOVFL_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_0_REQTGTIDMISMATCHERR 8:8 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_0_REQTGTIDMISMATCHERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_0_REQTGTIDMISMATCHERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_0_REQTGTIDMISMATCHERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_0_RSPREQIDMISMATCHERR 9:9 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_0_RSPREQIDMISMATCHERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_0_RSPREQIDMISMATCHERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_0_RSPREQIDMISMATCHERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_0_URRSPERR 10:10 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_0_URRSPERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_0_URRSPERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_0_URRSPERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_0_PRIVRSPERR 11:11 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_0_PRIVRSPERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_0_PRIVRSPERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_0_PRIVRSPERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_0_HWRSPERR 12:12 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_0_HWRSPERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_0_HWRSPERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_0_HWRSPERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_0_NXBAR_HDR_PARITY_ERR 13:13 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_0_NXBAR_HDR_PARITY_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_0_NXBAR_HDR_PARITY_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_0_NXBAR_HDR_PARITY_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_0_NCISOC_CREDIT_PARITY_ERR 14:14 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_0_NCISOC_CREDIT_PARITY_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_0_NCISOC_CREDIT_PARITY_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_0_NCISOC_CREDIT_PARITY_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_0_NXBAR_FLITTYPE_MISMATCH_ERR 15:15 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_0_NXBAR_FLITTYPE_MISMATCH_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_0_NXBAR_FLITTYPE_MISMATCH_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_0_NXBAR_FLITTYPE_MISMATCH_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_0_CREDIT_TIME_OUT_ERR 16:16 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_0_CREDIT_TIME_OUT_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_0_CREDIT_TIME_OUT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_0_CREDIT_TIME_OUT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_0_RFU 17:17 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_0_RFU__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_0_RFU_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_0_RFU_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_0_INVALIDVCSET_ERR 18:18 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_0_INVALIDVCSET_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_0_INVALIDVCSET_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_0_INVALIDVCSET_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_0_NXBAR_SIDEBAND_PD_PARITY_ERR 19:19 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_0_NXBAR_SIDEBAND_PD_PARITY_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_0_NXBAR_SIDEBAND_PD_PARITY_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_0_NXBAR_SIDEBAND_PD_PARITY_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0 0x00004404 /* RW-4R */ +#define NV_EGRESS_ERR_LOG_EN_0_EGRESSBUFERR 0:0 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_0_EGRESSBUFERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_EGRESSBUFERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_0_EGRESSBUFERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_PKTROUTEERR 1:1 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_0_PKTROUTEERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_PKTROUTEERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_0_PKTROUTEERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_SEQIDERR 2:2 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_0_SEQIDERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_SEQIDERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_0_SEQIDERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_ECC_LIMIT_ERR 3:3 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_ECC_DBE_ERR 4:4 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR 5:5 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_RAM_OUT_HDR_ECC_DBE_ERR 6:6 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_0_RAM_OUT_HDR_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_RAM_OUT_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_0_RAM_OUT_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_NCISOCCREDITOVFL 7:7 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_0_NCISOCCREDITOVFL__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_NCISOCCREDITOVFL_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_0_NCISOCCREDITOVFL_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_REQTGTIDMISMATCHERR 8:8 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_0_REQTGTIDMISMATCHERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_REQTGTIDMISMATCHERR__TPROD 0x00000000 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_REQTGTIDMISMATCHERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_0_REQTGTIDMISMATCHERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_RSPREQIDMISMATCHERR 9:9 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_0_RSPREQIDMISMATCHERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_RSPREQIDMISMATCHERR__TPROD 0x00000000 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_RSPREQIDMISMATCHERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_0_RSPREQIDMISMATCHERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_URRSPERR 10:10 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_0_URRSPERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_URRSPERR__TPROD 0x00000000 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_URRSPERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_0_URRSPERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_PRIVRSPERR 11:11 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_0_PRIVRSPERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_PRIVRSPERR__TPROD 0x00000000 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_PRIVRSPERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_0_PRIVRSPERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_HWRSPERR 12:12 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_0_HWRSPERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_HWRSPERR__TPROD 0x00000000 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_HWRSPERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_0_HWRSPERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_PARITY_ERR 13:13 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_PARITY_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_NCISOC_CREDIT_PARITY_ERR 14:14 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_0_NCISOC_CREDIT_PARITY_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_NCISOC_CREDIT_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_0_NCISOC_CREDIT_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR 15:15 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_CREDIT_TIME_OUT_ERR 16:16 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_0_CREDIT_TIME_OUT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_CREDIT_TIME_OUT_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_CREDIT_TIME_OUT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_0_CREDIT_TIME_OUT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_RFU 17:17 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_0_RFU_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_0_RFU_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_INVALIDVCSET_ERR 18:18 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_0_INVALIDVCSET_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_INVALIDVCSET_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_INVALIDVCSET_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_0_INVALIDVCSET_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_SIDEBAND_PD_PARITY_ERR 19:19 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_SIDEBAND_PD_PARITY_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_SIDEBAND_PD_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_SIDEBAND_PD_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0 0x00004408 /* RW-4R */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_EGRESSBUFERR 0:0 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_EGRESSBUFERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_EGRESSBUFERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_EGRESSBUFERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_PKTROUTEERR 1:1 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_PKTROUTEERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_PKTROUTEERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_PKTROUTEERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_SEQIDERR 2:2 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_SEQIDERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_SEQIDERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_SEQIDERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_LIMIT_ERR 3:3 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_DBE_ERR 4:4 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR 5:5 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_DBE_ERR 6:6 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NCISOCCREDITOVFL 7:7 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NCISOCCREDITOVFL__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NCISOCCREDITOVFL_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NCISOCCREDITOVFL_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_REQTGTIDMISMATCHERR 8:8 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_REQTGTIDMISMATCHERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_REQTGTIDMISMATCHERR__TPROD 0x00000000 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_REQTGTIDMISMATCHERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_REQTGTIDMISMATCHERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RSPREQIDMISMATCHERR 9:9 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RSPREQIDMISMATCHERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RSPREQIDMISMATCHERR__TPROD 0x00000000 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RSPREQIDMISMATCHERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RSPREQIDMISMATCHERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_URRSPERR 10:10 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_URRSPERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_URRSPERR__TPROD 0x00000000 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_URRSPERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_URRSPERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_PRIVRSPERR 11:11 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_PRIVRSPERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_PRIVRSPERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_HWRSPERR 12:12 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_HWRSPERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_HWRSPERR__TPROD 0x00000000 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_HWRSPERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_HWRSPERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_PARITY_ERR 13:13 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_PARITY_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_CREDIT_PARITY_ERR 14:14 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_CREDIT_PARITY_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_CREDIT_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_CREDIT_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR 15:15 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_CREDIT_TIME_OUT_ERR 16:16 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_CREDIT_TIME_OUT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_CREDIT_TIME_OUT_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_CREDIT_TIME_OUT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_CREDIT_TIME_OUT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RFU 17:17 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RFU_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RFU_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_INVALIDVCSET_ERR 18:18 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_INVALIDVCSET_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_INVALIDVCSET_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_INVALIDVCSET_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_INVALIDVCSET_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_SIDEBAND_PD_PARITY_ERR 19:19 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_SIDEBAND_PD_PARITY_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_SIDEBAND_PD_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_SIDEBAND_PD_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0 0x0000440c /* RW-4R */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_EGRESSBUFERR 0:0 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_EGRESSBUFERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_EGRESSBUFERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_PKTROUTEERR 1:1 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_PKTROUTEERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_PKTROUTEERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_SEQIDERR 2:2 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_SEQIDERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_SEQIDERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_LIMIT_ERR 3:3 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_DBE_ERR 4:4 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR 5:5 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_DBE_ERR 6:6 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOCCREDITOVFL 7:7 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOCCREDITOVFL_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOCCREDITOVFL_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_REQTGTIDMISMATCHERR 8:8 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_REQTGTIDMISMATCHERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_REQTGTIDMISMATCHERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RSPREQIDMISMATCHERR 9:9 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RSPREQIDMISMATCHERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RSPREQIDMISMATCHERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_URRSPERR 10:10 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_URRSPERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_URRSPERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_PRIVRSPERR 11:11 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_PRIVRSPERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_PRIVRSPERR__TPROD 0x00000000 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_PRIVRSPERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_PRIVRSPERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_HWRSPERR 12:12 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_HWRSPERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_HWRSPERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_PARITY_ERR 13:13 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_CREDIT_PARITY_ERR 14:14 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_CREDIT_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_CREDIT_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR 15:15 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_CREDIT_TIME_OUT_ERR 16:16 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_CREDIT_TIME_OUT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_CREDIT_TIME_OUT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RFU 17:17 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RFU_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RFU_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_INVALIDVCSET_ERR 18:18 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_INVALIDVCSET_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_INVALIDVCSET_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_SIDEBAND_PD_PARITY_ERR 19:19 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_SIDEBAND_PD_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_SIDEBAND_PD_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0 0x00004410 /* RW-4R */ +#define NV_EGRESS_ERR_CONTAIN_EN_0 0x00004414 /* RW-4R */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_EGRESSBUFERR 0:0 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_EGRESSBUFERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_EGRESSBUFERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_EGRESSBUFERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_PKTROUTEERR 1:1 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_PKTROUTEERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_PKTROUTEERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_PKTROUTEERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_SEQIDERR 2:2 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_SEQIDERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_SEQIDERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_SEQIDERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_ECC_LIMIT_ERR 3:3 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_ECC_DBE_ERR 4:4 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR 5:5 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_RAM_OUT_HDR_ECC_DBE_ERR 6:6 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_RAM_OUT_HDR_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_RAM_OUT_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_RAM_OUT_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_NCISOCCREDITOVFL 7:7 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_NCISOCCREDITOVFL__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_NCISOCCREDITOVFL_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_NCISOCCREDITOVFL_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_REQTGTIDMISMATCHERR 8:8 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_REQTGTIDMISMATCHERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_REQTGTIDMISMATCHERR__TPROD 0x00000000 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_REQTGTIDMISMATCHERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_REQTGTIDMISMATCHERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_RSPREQIDMISMATCHERR 9:9 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_RSPREQIDMISMATCHERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_RSPREQIDMISMATCHERR__TPROD 0x00000000 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_RSPREQIDMISMATCHERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_RSPREQIDMISMATCHERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_URRSPERR 10:10 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_URRSPERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_URRSPERR__TPROD 0x00000000 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_URRSPERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_URRSPERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_PRIVRSPERR 11:11 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_PRIVRSPERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_PRIVRSPERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_HWRSPERR 12:12 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_HWRSPERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_HWRSPERR__TPROD 0x00000000 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_HWRSPERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_HWRSPERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_PARITY_ERR 13:13 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_PARITY_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_NCISOC_CREDIT_PARITY_ERR 14:14 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_NCISOC_CREDIT_PARITY_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_NCISOC_CREDIT_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_NCISOC_CREDIT_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR 15:15 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_CREDIT_TIME_OUT_ERR 16:16 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_CREDIT_TIME_OUT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_CREDIT_TIME_OUT_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_CREDIT_TIME_OUT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_CREDIT_TIME_OUT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_RFU 17:17 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_RFU_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_RFU_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_INVALIDVCSET_ERR 18:18 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_INVALIDVCSET_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_INVALIDVCSET_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_INVALIDVCSET_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_INVALIDVCSET_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_SIDEBAND_PD_PARITY_ERR 19:19 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_SIDEBAND_PD_PARITY_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_SIDEBAND_PD_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_SIDEBAND_PD_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_0 0x0000441c /* RW-4R */ +#define NV_EGRESS_ERR_FIRST_0_EGRESSBUFERR 0:0 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_0_EGRESSBUFERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_0_EGRESSBUFERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_0_EGRESSBUFERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_0_PKTROUTEERR 1:1 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_0_PKTROUTEERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_0_PKTROUTEERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_0_PKTROUTEERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_0_SEQIDERR 2:2 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_0_SEQIDERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_0_SEQIDERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_0_SEQIDERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_0_NXBAR_HDR_ECC_LIMIT_ERR 3:3 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_0_NXBAR_HDR_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_0_NXBAR_HDR_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_0_NXBAR_HDR_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_0_NXBAR_HDR_ECC_DBE_ERR 4:4 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_0_NXBAR_HDR_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_0_NXBAR_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_0_NXBAR_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_0_RAM_OUT_HDR_ECC_LIMIT_ERR 5:5 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_0_RAM_OUT_HDR_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_0_RAM_OUT_HDR_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_0_RAM_OUT_HDR_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_0_RAM_OUT_HDR_ECC_DBE_ERR 6:6 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_0_RAM_OUT_HDR_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_0_RAM_OUT_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_0_RAM_OUT_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_0_NCISOCCREDITOVFL 7:7 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_0_NCISOCCREDITOVFL__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_0_NCISOCCREDITOVFL_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_0_NCISOCCREDITOVFL_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_0_REQTGTIDMISMATCHERR 8:8 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_0_REQTGTIDMISMATCHERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_0_REQTGTIDMISMATCHERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_0_REQTGTIDMISMATCHERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_0_RSPREQIDMISMATCHERR 9:9 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_0_RSPREQIDMISMATCHERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_0_RSPREQIDMISMATCHERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_0_RSPREQIDMISMATCHERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_0_URRSPERR 10:10 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_0_URRSPERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_0_URRSPERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_0_URRSPERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_0_PRIVRSPERR 11:11 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_0_PRIVRSPERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_0_PRIVRSPERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_0_PRIVRSPERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_0_HWRSPERR 12:12 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_0_HWRSPERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_0_HWRSPERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_0_HWRSPERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_0_NXBAR_HDR_PARITY_ERR 13:13 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_0_NXBAR_HDR_PARITY_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_0_NXBAR_HDR_PARITY_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_0_NXBAR_HDR_PARITY_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_0_NCISOC_CREDIT_PARITY_ERR 14:14 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_0_NCISOC_CREDIT_PARITY_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_0_NCISOC_CREDIT_PARITY_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_0_NCISOC_CREDIT_PARITY_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_0_NXBAR_FLITTYPE_MISMATCH_ERR 15:15 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_0_NXBAR_FLITTYPE_MISMATCH_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_0_NXBAR_FLITTYPE_MISMATCH_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_0_NXBAR_FLITTYPE_MISMATCH_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_0_CREDIT_TIME_OUT_ERR 16:16 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_0_CREDIT_TIME_OUT_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_0_CREDIT_TIME_OUT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_0_CREDIT_TIME_OUT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_0_RFU 17:17 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_0_RFU__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_0_RFU_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_0_RFU_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_0_INVALIDVCSET_ERR 18:18 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_0_INVALIDVCSET_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_0_INVALIDVCSET_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_0_INVALIDVCSET_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_0_NXBAR_SIDEBAND_PD_PARITY_ERR 19:19 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_0_NXBAR_SIDEBAND_PD_PARITY_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_0_NXBAR_SIDEBAND_PD_PARITY_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_0_NXBAR_SIDEBAND_PD_PARITY_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_HEADER_LOG_4 0x00004430 /* R--4R */ +#define NV_EGRESS_ERR_HEADER_LOG_4_DW 31:0 /* R-DVF */ +#define NV_EGRESS_ERR_HEADER_LOG_4_DW_INIT 0x00000000 /* R-D-V */ +#define NV_EGRESS_ERR_HEADER_LOG_5 0x00004434 /* R--4R */ +#define NV_EGRESS_ERR_HEADER_LOG_5_DW 31:0 /* R-DVF */ +#define NV_EGRESS_ERR_HEADER_LOG_5_DW_INIT 0x00000000 /* R-D-V */ +#define NV_EGRESS_ERR_HEADER_LOG_6 0x00004438 /* R--4R */ +#define NV_EGRESS_ERR_HEADER_LOG_6_DW 31:0 /* R-DVF */ +#define NV_EGRESS_ERR_HEADER_LOG_6_DW_INIT 0x00000000 /* R-D-V */ +#define NV_EGRESS_ERR_HEADER_LOG_7 0x0000443c /* R--4R */ +#define NV_EGRESS_ERR_HEADER_LOG_7_DW 31:0 /* R-DVF */ +#define NV_EGRESS_ERR_HEADER_LOG_7_DW_INIT 0x00000000 /* R-D-V */ +#define NV_EGRESS_ERR_HEADER_LOG_8 0x00004440 /* R--4R */ +#define NV_EGRESS_ERR_HEADER_LOG_8_DW 31:0 /* R-DVF */ +#define NV_EGRESS_ERR_HEADER_LOG_8_DW_INIT 0x00000000 /* R-D-V */ +#define NV_EGRESS_ERR_HEADER_LOG_9 0x00004444 /* R--4R */ +#define NV_EGRESS_ERR_HEADER_LOG_9_DW 31:0 /* R-DVF */ +#define NV_EGRESS_ERR_HEADER_LOG_9_DW_INIT 0x00000000 /* R-D-V */ +#define NV_EGRESS_ERR_HEADER_LOG_10 0x00004448 /* R--4R */ +#define NV_EGRESS_ERR_HEADER_LOG_10_DW 31:0 /* R-DVF */ +#define NV_EGRESS_ERR_HEADER_LOG_10_DW_INIT 0x00000000 /* R-D-V */ +#define NV_EGRESS_ERR_HEADER_LOG_VALID 0x0000444c /* R--4R */ +#define NV_EGRESS_ERR_HEADER_LOG_VALID_HEADERVALID0 0:0 /* R-DVF */ +#define NV_EGRESS_ERR_HEADER_LOG_VALID_HEADERVALID0_INVALID 0x00000000 /* R-D-V */ +#define NV_EGRESS_ERR_HEADER_LOG_VALID_HEADERVALID0_VALID 0x00000001 /* R---V */ +#define NV_EGRESS_ERR_TIMESTAMP_LOG 0x00004450 /* R--4R */ +#define NV_EGRESS_ERR_TIMESTAMP_LOG_TIMESTAMP 23:0 /* R-DVF */ +#define NV_EGRESS_ERR_TIMESTAMP_LOG_TIMESTAMP_INIT 0x00000000 /* R-D-V */ +#define NV_EGRESS_ERR_MISC_LOG_0 0x00004454 /* R--4R */ +#define NV_EGRESS_ERR_MISC_LOG_0_SPORT 6:0 /* R-DVF */ +#define NV_EGRESS_ERR_MISC_LOG_0_SPORT_INIT 0x00000000 /* R-D-V */ +#define NV_EGRESS_ERR_MISC_LOG_0_ENCODEDVC 10:8 /* R-DVF */ +#define NV_EGRESS_ERR_MISC_LOG_0_ENCODEDVC_INIT 0x00000000 /* R-D-V */ +#define NV_EGRESS_ERR_ECC_CTRL 0x00004470 /* RW-4R */ +#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_ECC_ENABLE 0:0 /* RWEVF */ +#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_ECC_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_PARITY_ENABLE 1:1 /* RWEVF */ +#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_PARITY_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_PARITY_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_PARITY_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_SIDEBAND_PD_PARITY_ENABLE 2:2 /* RWEVF */ +#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_SIDEBAND_PD_PARITY_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_SIDEBAND_PD_PARITY_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_SIDEBAND_PD_PARITY_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_REDUCTION_ECC_ENABLE 3:3 /* RWEVF */ +#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_REDUCTION_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_REDUCTION_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_REDUCTION_ECC_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_REDUCTION_PARITY_ENABLE 4:4 /* RWEVF */ +#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_REDUCTION_PARITY_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_REDUCTION_PARITY_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_REDUCTION_PARITY_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_ECC_CTRL_MCRSPCTRLSTORE_ECC_ENABLE 5:5 /* RWEVF */ +#define NV_EGRESS_ERR_ECC_CTRL_MCRSPCTRLSTORE_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_ECC_CTRL_MCRSPCTRLSTORE_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_ECC_CTRL_MCRSPCTRLSTORE_ECC_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_ECC_CTRL_RBCTRLSTORE_ECC_ENABLE 6:6 /* RWEVF */ +#define NV_EGRESS_ERR_ECC_CTRL_RBCTRLSTORE_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_ECC_CTRL_RBCTRLSTORE_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_ECC_CTRL_RBCTRLSTORE_ECC_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_ECC_CTRL_MCREDSGT_ECC_ENABLE 7:7 /* RWEVF */ +#define NV_EGRESS_ERR_ECC_CTRL_MCREDSGT_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_ECC_CTRL_MCREDSGT_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_ECC_CTRL_MCREDSGT_ECC_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_ECC_CTRL_RAM_OUT_ECC_ENABLE 8:8 /* RWEVF */ +#define NV_EGRESS_ERR_ECC_CTRL_RAM_OUT_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_ECC_CTRL_RAM_OUT_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_ECC_CTRL_RAM_OUT_ECC_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_ECC_CTRL_NCISOC_ECC_ENABLE 9:9 /* RWEVF */ +#define NV_EGRESS_ERR_ECC_CTRL_NCISOC_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_ECC_CTRL_NCISOC_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_ECC_CTRL_NCISOC_ECC_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_ECC_CTRL_NCISOC_PARITY_ENABLE 10:10 /* RWEVF */ +#define NV_EGRESS_ERR_ECC_CTRL_NCISOC_PARITY_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_ECC_CTRL_NCISOC_PARITY_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_ECC_CTRL_NCISOC_PARITY_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_ECC_CTRL_MCREDBUF_ECC_ENABLE 11:11 /* RWEVF */ +#define NV_EGRESS_ERR_ECC_CTRL_MCREDBUF_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_ECC_CTRL_MCREDBUF_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_ECC_CTRL_MCREDBUF_ECC_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_ECC_CTRL_MCRSP_RAM_ECC_ENABLE 12:12 /* RWEVF */ +#define NV_EGRESS_ERR_ECC_CTRL_MCRSP_RAM_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_ECC_CTRL_MCRSP_RAM_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_ECC_CTRL_MCRSP_RAM_ECC_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NXBAR_ECC_ERROR_COUNTER 0x00004480 /* RW-4R */ +#define NV_EGRESS_ERR_NXBAR_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */ +#define NV_EGRESS_ERR_NXBAR_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_NXBAR_ECC_ERROR_COUNTER_LIMIT 0x00004484 /* RW-4R */ +#define NV_EGRESS_ERR_NXBAR_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */ +#define NV_EGRESS_ERR_NXBAR_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */ +#define NV_EGRESS_ERR_NXBAR_REDUCTION_ECC_ERROR_COUNTER 0x00004488 /* RW-4R */ +#define NV_EGRESS_ERR_NXBAR_REDUCTION_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */ +#define NV_EGRESS_ERR_NXBAR_REDUCTION_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_COUNTER 0x0000448c /* RW-4R */ +#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */ +#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_COUNTER_LIMIT 0x00004490 /* RW-4R */ +#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */ +#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */ +#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_ADDRESS 0x00004494 /* R--4R */ +#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_ADDRESS_ERROR_ADDRESS 7:0 /* R-DVF */ +#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */ +#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_ADDRESS_VALID 0x00004498 /* R--4R */ +#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */ +#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */ +#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */ +#define NV_EGRESS_ERR_NXBAR_REDUCTION_ECC_ERROR_COUNTER_LIMIT 0x0000449c /* RW-4R */ +#define NV_EGRESS_ERR_NXBAR_REDUCTION_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */ +#define NV_EGRESS_ERR_NXBAR_REDUCTION_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */ +#define NV_EGRESS_MCREDRAMADDR 0x00004520 /* RW-4R */ +#define NV_EGRESS_MCREDRAMADDR_RAM_ADDR 12:0 /* RWEVF */ +#define NV_EGRESS_MCREDRAMADDR_RAM_ADDR_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDRAMADDR_RAM_ADDR_MCREDSGT_DEPTH 0x000000ff /* RW--V */ +#define NV_EGRESS_MCREDRAMADDR_RAM_ADDR_MCRSPCTRLSTORE_DEPTH 0x000000ff /* RW--V */ +#define NV_EGRESS_MCREDRAMADDR_RAM_ADDR_RBCTRLSTORE_DEPTH 0x000000ff /* RW--V */ +#define NV_EGRESS_MCREDRAMADDR_RAM_ADDR_MCREDBUF_DEPTH 0x00001fff /* RW--V */ +#define NV_EGRESS_MCREDRAMADDR_RAM_SEL 18:17 /* RWEVF */ +#define NV_EGRESS_MCREDRAMADDR_RAM_SEL_SELECTSMCRSPCTRLSTORERAM 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDRAMADDR_RAM_SEL_SELECTSRBCTRLSTORERAM 0x00000001 /* RW--V */ +#define NV_EGRESS_MCREDRAMADDR_RAM_SEL_SELECTSMCREDSGTRAM 0x00000002 /* RW--V */ +#define NV_EGRESS_MCREDRAMADDR_RAM_SEL_SELECTSMCREDBUFRAM 0x00000003 /* RW--V */ +#define NV_EGRESS_MCREDRAMADDR_AUTO_INCR 31:31 /* RWEVF */ +#define NV_EGRESS_MCREDRAMADDR_AUTO_INCR_ENABLE 0x00000001 /* RWE-V */ +#define NV_EGRESS_MCREDRAMADDR_AUTO_INCR_DISABLE 0x00000000 /* RW--V */ +#define NV_EGRESS_MCRSPCTRLSTOREDATA0 0x00004524 /* RW-4R */ +#define NV_EGRESS_MCRSPCTRLSTOREDATA0_MCID 6:0 /* RWEVF */ +#define NV_EGRESS_MCRSPCTRLSTOREDATA0_MCID_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCRSPCTRLSTOREDATA0_MCSIZE 14:9 /* RWEVF */ +#define NV_EGRESS_MCRSPCTRLSTOREDATA0_MCSIZE_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCRSPCTRLSTOREDATA0_NVL_REQ_ATOMIC_NR 17:17 /* RWEVF */ +#define NV_EGRESS_MCRSPCTRLSTOREDATA0_NVL_REQ_ATOMIC_NR_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCRSPCTRLSTOREDATA0_VCSET 18:18 /* RWEVF */ +#define NV_EGRESS_MCRSPCTRLSTOREDATA0_VCSET_VCSET0 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCRSPCTRLSTOREDATA0_VCSET_VCSET1 0x00000001 /* RW--V */ +#define NV_EGRESS_MCRSPCTRLSTOREDATA0_MC_RSP_CNT 25:19 /* RWEVF */ +#define NV_EGRESS_MCRSPCTRLSTOREDATA0_MC_RSP_CNT_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCRSPCTRLSTOREDATA0_ECC 31:26 /* R-EVF */ +#define NV_EGRESS_MCRSPCTRLSTOREDATA0_ECC_INIT 0x00000000 /* R-E-V */ +#define NV_EGRESS_RBCTRLSTOREDATA0 0x00004528 /* RW-4R */ +#define NV_EGRESS_RBCTRLSTOREDATA0_MCID 6:0 /* RWEVF */ +#define NV_EGRESS_RBCTRLSTOREDATA0_MCID_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_RBCTRLSTOREDATA0_MCSIZE 14:9 /* RWEVF */ +#define NV_EGRESS_RBCTRLSTOREDATA0_MCSIZE_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_RBCTRLSTOREDATA0_VCSET 18:18 /* RWEVF */ +#define NV_EGRESS_RBCTRLSTOREDATA0_VCSET_VCSET0 0x00000000 /* RWE-V */ +#define NV_EGRESS_RBCTRLSTOREDATA0_VCSET_VCSET1 0x00000001 /* RW--V */ +#define NV_EGRESS_RBCTRLSTOREDATA0_RB_RSP_CNT 25:19 /* RWEVF */ +#define NV_EGRESS_RBCTRLSTOREDATA0_RB_RSP_CNT_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_RBCTRLSTOREDATA0_ECC 31:26 /* R-EVF */ +#define NV_EGRESS_RBCTRLSTOREDATA0_ECC_INIT 0x00000000 /* R-E-V */ +#define NV_EGRESS_RBCTRLSTOREDATA1 0x0000452c /* RW-4R */ +#define NV_EGRESS_RBCTRLSTOREDATA1_OPCMD 3:0 /* RWEVF */ +#define NV_EGRESS_RBCTRLSTOREDATA1_OPCMD_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_RBCTRLSTOREDATA1_OPSIZE 6:4 /* RWEVF */ +#define NV_EGRESS_RBCTRLSTOREDATA1_OPSIZE_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_RBCTRLSTOREDATA1_OPSIGN 7:7 /* RWEVF */ +#define NV_EGRESS_RBCTRLSTOREDATA1_OPSIGN_SIGNED 0x00000000 /* RWE-V */ +#define NV_EGRESS_RBCTRLSTOREDATA1_OPSIGN_UNSIGNED 0x00000001 /* RW--V */ +#define NV_EGRESS_RBCTRLSTOREDATA1_MP 9:8 /* RWEVF */ +#define NV_EGRESS_RBCTRLSTOREDATA1_MP_NO_MIXED_PRECISION 0x00000000 /* RWE-V */ +#define NV_EGRESS_RBCTRLSTOREDATA1_MP_2X_FABRIC_ONLY_MIXED_PRECISION 0x00000001 /* RW--V */ +#define NV_EGRESS_RBCTRLSTOREDATA1_MP_2X_MIXED_PRECISION 0x00000002 /* RW--V */ +#define NV_EGRESS_RBCTRLSTOREDATA1_NVL_REQ_SIZE 11:10 /* RWEVF */ +#define NV_EGRESS_RBCTRLSTOREDATA1_NVL_REQ_SIZE_32B 0x00000000 /* RWE-V */ +#define NV_EGRESS_RBCTRLSTOREDATA1_NVL_REQ_SIZE_64B 0x00000001 /* RW--V */ +#define NV_EGRESS_RBCTRLSTOREDATA1_NVL_REQ_SIZE_96B 0x00000002 /* RW--V */ +#define NV_EGRESS_RBCTRLSTOREDATA1_NVL_REQ_SIZE_128B 0x00000003 /* RW--V */ +#define NV_EGRESS_RBCTRLSTOREDATA1_RSVD 13:12 /* RWEVF */ +#define NV_EGRESS_RBCTRLSTOREDATA1_RSVD_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA0 0x00004530 /* RW-4R */ +#define NV_EGRESS_MCREDSGTDATA0_RBIDX0 6:0 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA0_RBIDX0_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA0_VLD_RBIDX0 7:7 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA0_VLD_RBIDX0_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA0_RBIDX1 14:8 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA0_RBIDX1_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA0_VLD_RBIDX1 15:15 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA0_VLD_RBIDX1_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA0_RBIDX2 22:16 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA0_RBIDX2_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA0_VLD_RBIDX2 23:23 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA0_VLD_RBIDX2_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA0_RBIDX3 30:24 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA0_RBIDX3_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA0_VLD_RBIDX3 31:31 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA0_VLD_RBIDX3_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA1 0x00004534 /* RW-4R */ +#define NV_EGRESS_MCREDSGTDATA1_RBIDX4 6:0 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA1_RBIDX4_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA1_VLD_RBIDX4 7:7 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA1_VLD_RBIDX4_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA1_RBIDX5 14:8 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA1_RBIDX5_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA1_VLD_RBIDX5 15:15 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA1_VLD_RBIDX5_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA1_RBIDX6 22:16 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA1_RBIDX6_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA1_VLD_RBIDX6 23:23 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA1_VLD_RBIDX6_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA1_RBIDX7 30:24 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA1_RBIDX7_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA1_VLD_RBIDX7 31:31 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA1_VLD_RBIDX7_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA2 0x00004538 /* RW-4R */ +#define NV_EGRESS_MCREDSGTDATA2_RBIDX8 6:0 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA2_RBIDX8_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA2_VLD_RBIDX8 7:7 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA2_VLD_RBIDX8_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA2_RBIDX9 14:8 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA2_RBIDX9_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA2_VLD_RBIDX9 15:15 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA2_VLD_RBIDX9_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA2_RBIDX10 22:16 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA2_RBIDX10_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA2_VLD_RBIDX10 23:23 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA2_VLD_RBIDX10_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA2_RBIDX11 30:24 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA2_RBIDX11_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA2_VLD_RBIDX11 31:31 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA2_VLD_RBIDX11_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA3 0x0000453c /* RW-4R */ +#define NV_EGRESS_MCREDSGTDATA3_RBIDX12 6:0 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA3_RBIDX12_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA3_VLD_RBIDX12 7:7 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA3_VLD_RBIDX12_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA3_RBIDX13 14:8 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA3_RBIDX13_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA3_VLD_RBIDX13 15:15 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA3_VLD_RBIDX13_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA3_RBIDX14 22:16 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA3_RBIDX14_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA3_VLD_RBIDX14 23:23 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA3_VLD_RBIDX14_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA3_RBIDX15 30:24 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA3_RBIDX15_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA3_VLD_RBIDX15 31:31 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA3_VLD_RBIDX15_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA4 0x00004540 /* RW-4R */ +#define NV_EGRESS_MCREDSGTDATA4_RBIDX16 6:0 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA4_RBIDX16_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA4_VLD_RBIDX16 7:7 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA4_VLD_RBIDX16_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA4_RBIDX17 14:8 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA4_RBIDX17_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA4_VLD_RBIDX17 15:15 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA4_VLD_RBIDX17_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA4_RBIDX18 22:16 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA4_RBIDX18_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA4_VLD_RBIDX18 23:23 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA4_VLD_RBIDX18_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA4_RBIDX19 30:24 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA4_RBIDX19_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA4_VLD_RBIDX19 31:31 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA4_VLD_RBIDX19_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA5 0x00004544 /* RW-4R */ +#define NV_EGRESS_MCREDSGTDATA5_RBIDX20 6:0 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA5_RBIDX20_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA5_VLD_RBIDX20 7:7 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA5_VLD_RBIDX20_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA5_RBIDX21 14:8 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA5_RBIDX21_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA5_VLD_RBIDX21 15:15 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA5_VLD_RBIDX21_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA5_RBIDX22 22:16 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA5_RBIDX22_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA5_VLD_RBIDX22 23:23 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA5_VLD_RBIDX22_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA5_RBIDX23 30:24 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA5_RBIDX23_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA5_VLD_RBIDX23 31:31 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA5_VLD_RBIDX23_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA6 0x00004548 /* RW-4R */ +#define NV_EGRESS_MCREDSGTDATA6_RBIDX24 6:0 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA6_RBIDX24_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA6_VLD_RBIDX24 7:7 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA6_VLD_RBIDX24_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA6_RBIDX25 14:8 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA6_RBIDX25_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA6_VLD_RBIDX25 15:15 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA6_VLD_RBIDX25_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA6_RBIDX26 22:16 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA6_RBIDX26_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA6_VLD_RBIDX26 23:23 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA6_VLD_RBIDX26_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA6_RBIDX27 30:24 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA6_RBIDX27_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA6_VLD_RBIDX27 31:31 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA6_VLD_RBIDX27_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA7 0x0000454c /* RW-4R */ +#define NV_EGRESS_MCREDSGTDATA7_RBIDX28 6:0 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA7_RBIDX28_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA7_VLD_RBIDX28 7:7 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA7_VLD_RBIDX28_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA7_RBIDX29 14:8 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA7_RBIDX29_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA7_VLD_RBIDX29 15:15 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA7_VLD_RBIDX29_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA7_RBIDX30 22:16 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA7_RBIDX30_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA7_VLD_RBIDX30 23:23 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA7_VLD_RBIDX30_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA7_RBIDX31 30:24 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA7_RBIDX31_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA7_VLD_RBIDX31 31:31 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA7_VLD_RBIDX31_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA8 0x00004550 /* RW-4R */ +#define NV_EGRESS_MCREDSGTDATA8_RSVD 1:0 /* RWEVF */ +#define NV_EGRESS_MCREDSGTDATA8_RSVD_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDSGTDATA8_ECC 13:4 /* R-EVF */ +#define NV_EGRESS_MCREDSGTDATA8_ECC_INIT 0x00000000 /* R-E-V */ +#define NV_EGRESS_MCREDBUFDATA0 0x00004554 /* RW-4R */ +#define NV_EGRESS_MCREDBUFDATA0_DATA_0 31:0 /* RWEVF */ +#define NV_EGRESS_MCREDBUFDATA0_DATA_0_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDBUFDATA1 0x00004558 /* RW-4R */ +#define NV_EGRESS_MCREDBUFDATA1_DATA_1 31:0 /* RWEVF */ +#define NV_EGRESS_MCREDBUFDATA1_DATA_1_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDBUFDATA2 0x0000455c /* RW-4R */ +#define NV_EGRESS_MCREDBUFDATA2_DATA_2 31:0 /* RWEVF */ +#define NV_EGRESS_MCREDBUFDATA2_DATA_2_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDBUFDATA3 0x00004560 /* RW-4R */ +#define NV_EGRESS_MCREDBUFDATA3_DATA_3 31:0 /* RWEVF */ +#define NV_EGRESS_MCREDBUFDATA3_DATA_3_INIT 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDBUFDATA4 0x00004564 /* RW-4R */ +#define NV_EGRESS_MCREDBUFDATA4_SRC_TRUNKPORT 0:0 /* RWEVF */ +#define NV_EGRESS_MCREDBUFDATA4_SRC_TRUNKPORT_ACCESS 0x00000000 /* RWE-V */ +#define NV_EGRESS_MCREDBUFDATA4_SRC_TRUNKPORT_TRUNK 0x00000001 /* RW--V */ +#define NV_EGRESS_MCREDBUFDATA4_ECC 31:23 /* R-EVF */ +#define NV_EGRESS_MCREDBUFDATA4_ECC_INIT 0x00000000 /* R-E-V */ +#define NV_EGRESS_ERR_MCRSPCTRLSTORE_ECC_ERROR_COUNTER 0x00004568 /* RW-4R */ +#define NV_EGRESS_ERR_MCRSPCTRLSTORE_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */ +#define NV_EGRESS_ERR_MCRSPCTRLSTORE_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_MCRSPCTRLSTORE_ECC_ERROR_COUNTER_LIMIT 0x0000456c /* RW-4R */ +#define NV_EGRESS_ERR_MCRSPCTRLSTORE_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */ +#define NV_EGRESS_ERR_MCRSPCTRLSTORE_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */ +#define NV_EGRESS_ERR_MCRSPCTRLSTORE_ECC_ERROR_ADDRESS 0x00004570 /* R--4R */ +#define NV_EGRESS_ERR_MCRSPCTRLSTORE_ECC_ERROR_ADDRESS_ERROR_ADDRESS 7:0 /* R-DVF */ +#define NV_EGRESS_ERR_MCRSPCTRLSTORE_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */ +#define NV_EGRESS_ERR_MCRSPCTRLSTORE_ECC_ERROR_ADDRESS_VALID 0x00004574 /* R--4R */ +#define NV_EGRESS_ERR_MCRSPCTRLSTORE_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */ +#define NV_EGRESS_ERR_MCRSPCTRLSTORE_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */ +#define NV_EGRESS_ERR_MCRSPCTRLSTORE_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */ +#define NV_EGRESS_ERR_RBCTRLSTORE_ECC_ERROR_COUNTER 0x00004578 /* RW-4R */ +#define NV_EGRESS_ERR_RBCTRLSTORE_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */ +#define NV_EGRESS_ERR_RBCTRLSTORE_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_RBCTRLSTORE_ECC_ERROR_COUNTER_LIMIT 0x0000457c /* RW-4R */ +#define NV_EGRESS_ERR_RBCTRLSTORE_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */ +#define NV_EGRESS_ERR_RBCTRLSTORE_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */ +#define NV_EGRESS_ERR_RBCTRLSTORE_ECC_ERROR_ADDRESS 0x00004580 /* R--4R */ +#define NV_EGRESS_ERR_RBCTRLSTORE_ECC_ERROR_ADDRESS_ERROR_ADDRESS 7:0 /* R-DVF */ +#define NV_EGRESS_ERR_RBCTRLSTORE_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */ +#define NV_EGRESS_ERR_RBCTRLSTORE_ECC_ERROR_ADDRESS_VALID 0x00004584 /* R--4R */ +#define NV_EGRESS_ERR_RBCTRLSTORE_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */ +#define NV_EGRESS_ERR_RBCTRLSTORE_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */ +#define NV_EGRESS_ERR_RBCTRLSTORE_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */ +#define NV_EGRESS_ERR_MCREDSGT_ECC_ERROR_COUNTER 0x00004588 /* RW-4R */ +#define NV_EGRESS_ERR_MCREDSGT_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */ +#define NV_EGRESS_ERR_MCREDSGT_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_MCREDSGT_ECC_ERROR_COUNTER_LIMIT 0x0000458c /* RW-4R */ +#define NV_EGRESS_ERR_MCREDSGT_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */ +#define NV_EGRESS_ERR_MCREDSGT_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */ +#define NV_EGRESS_ERR_MCREDSGT_ECC_ERROR_ADDRESS 0x00004590 /* R--4R */ +#define NV_EGRESS_ERR_MCREDSGT_ECC_ERROR_ADDRESS_ERROR_ADDRESS 7:0 /* R-DVF */ +#define NV_EGRESS_ERR_MCREDSGT_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */ +#define NV_EGRESS_ERR_MCREDSGT_ECC_ERROR_ADDRESS_VALID 0x00004594 /* R--4R */ +#define NV_EGRESS_ERR_MCREDSGT_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */ +#define NV_EGRESS_ERR_MCREDSGT_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */ +#define NV_EGRESS_ERR_MCREDSGT_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */ +#define NV_EGRESS_ERR_MCREDBUF_ECC_ERROR_COUNTER 0x00004598 /* RW-4R */ +#define NV_EGRESS_ERR_MCREDBUF_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */ +#define NV_EGRESS_ERR_MCREDBUF_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_MCREDBUF_ECC_ERROR_COUNTER_LIMIT 0x0000459c /* RW-4R */ +#define NV_EGRESS_ERR_MCREDBUF_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */ +#define NV_EGRESS_ERR_MCREDBUF_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */ +#define NV_EGRESS_ERR_MCREDBUF_ECC_ERROR_ADDRESS 0x000045a0 /* R--4R */ +#define NV_EGRESS_ERR_MCREDBUF_ECC_ERROR_ADDRESS_ERROR_ADDRESS 7:0 /* R-DVF */ +#define NV_EGRESS_ERR_MCREDBUF_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */ +#define NV_EGRESS_ERR_MCREDBUF_ECC_ERROR_ADDRESS_VALID 0x000045a4 /* R--4R */ +#define NV_EGRESS_ERR_MCREDBUF_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */ +#define NV_EGRESS_ERR_MCREDBUF_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */ +#define NV_EGRESS_ERR_MCREDBUF_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */ +#define NV_EGRESS_ERR_MCRSP_RAM_ECC_ERROR_COUNTER 0x000045a8 /* RW-4R */ +#define NV_EGRESS_ERR_MCRSP_RAM_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */ +#define NV_EGRESS_ERR_MCRSP_RAM_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_MCRSP_RAM_ECC_ERROR_COUNTER_LIMIT 0x000045ac /* RW-4R */ +#define NV_EGRESS_ERR_MCRSP_RAM_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */ +#define NV_EGRESS_ERR_MCRSP_RAM_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */ +#define NV_EGRESS_ERR_MCRSP_RAM_ECC_ERROR_ADDRESS 0x000045b0 /* R--4R */ +#define NV_EGRESS_ERR_MCRSP_RAM_ECC_ERROR_ADDRESS_ERROR_ADDRESS 9:0 /* R-DVF */ +#define NV_EGRESS_ERR_MCRSP_RAM_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */ +#define NV_EGRESS_ERR_MCRSP_RAM_ECC_ERROR_ADDRESS_VALID 0x000045b4 /* R--4R */ +#define NV_EGRESS_ERR_MCRSP_RAM_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */ +#define NV_EGRESS_ERR_MCRSP_RAM_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */ +#define NV_EGRESS_ERR_MCRSP_RAM_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */ +#define NV_EGRESS_ERR_STATUS_1 0x00004900 /* RW-4R */ +#define NV_EGRESS_ERR_STATUS_1_NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR 0:0 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_1_NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_1_NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_1_NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_1_NXBAR_REDUCTION_HDR_ECC_DBE_ERR 1:1 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_1_NXBAR_REDUCTION_HDR_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_1_NXBAR_REDUCTION_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_1_NXBAR_REDUCTION_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_1_NXBAR_REDUCTION_HDR_PARITY_ERR 2:2 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_1_NXBAR_REDUCTION_HDR_PARITY_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_1_NXBAR_REDUCTION_HDR_PARITY_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_1_NXBAR_REDUCTION_HDR_PARITY_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_1_NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR 3:3 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_1_NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_1_NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_1_NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_1_MCRSPCTRLSTORE_ECC_LIMIT_ERR 4:4 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_1_MCRSPCTRLSTORE_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_1_MCRSPCTRLSTORE_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_1_MCRSPCTRLSTORE_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_1_MCRSPCTRLSTORE_ECC_DBE_ERR 5:5 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_1_MCRSPCTRLSTORE_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_1_MCRSPCTRLSTORE_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_1_MCRSPCTRLSTORE_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_1_RBCTRLSTORE_ECC_LIMIT_ERR 6:6 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_1_RBCTRLSTORE_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_1_RBCTRLSTORE_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_1_RBCTRLSTORE_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_1_RBCTRLSTORE_ECC_DBE_ERR 7:7 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_1_RBCTRLSTORE_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_1_RBCTRLSTORE_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_1_RBCTRLSTORE_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_1_MCREDSGT_ECC_LIMIT_ERR 8:8 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_1_MCREDSGT_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_1_MCREDSGT_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_1_MCREDSGT_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_1_MCREDSGT_ECC_DBE_ERR 9:9 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_1_MCREDSGT_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_1_MCREDSGT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_1_MCREDSGT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_1_MCREDBUF_ECC_LIMIT_ERR 10:10 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_1_MCREDBUF_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_1_MCREDBUF_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_1_MCREDBUF_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_1_MCREDBUF_ECC_DBE_ERR 11:11 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_1_MCREDBUF_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_1_MCREDBUF_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_1_MCREDBUF_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_1_MCRSP_RAM_HDR_ECC_LIMIT_ERR 12:12 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_1_MCRSP_RAM_HDR_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_1_MCRSP_RAM_HDR_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_1_MCRSP_RAM_HDR_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_1_MCRSP_RAM_HDR_ECC_DBE_ERR 13:13 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_1_MCRSP_RAM_HDR_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_1_MCRSP_RAM_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_1_MCRSP_RAM_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_1_MCRSP_CNT_ERR 14:14 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_1_MCRSP_CNT_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_1_MCRSP_CNT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_1_MCRSP_CNT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_STATUS_1_RBRSP_CNT_ERR 15:15 /* RWDVF */ +#define NV_EGRESS_ERR_STATUS_1_RBRSP_CNT_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_STATUS_1_RBRSP_CNT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_STATUS_1_RBRSP_CNT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_1 0x00004904 /* RW-4R */ +#define NV_EGRESS_ERR_LOG_EN_1_NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR 0:0 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_1_NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_1_NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_1_NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_1_NXBAR_REDUCTION_HDR_ECC_DBE_ERR 1:1 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_1_NXBAR_REDUCTION_HDR_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_1_NXBAR_REDUCTION_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_1_NXBAR_REDUCTION_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_1_NXBAR_REDUCTION_HDR_PARITY_ERR 2:2 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_1_NXBAR_REDUCTION_HDR_PARITY_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_1_NXBAR_REDUCTION_HDR_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_1_NXBAR_REDUCTION_HDR_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_1_NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR 3:3 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_1_NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_1_NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_1_NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_1_MCRSPCTRLSTORE_ECC_LIMIT_ERR 4:4 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_1_MCRSPCTRLSTORE_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_1_MCRSPCTRLSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_1_MCRSPCTRLSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_1_MCRSPCTRLSTORE_ECC_DBE_ERR 5:5 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_1_MCRSPCTRLSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_1_MCRSPCTRLSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_1_MCRSPCTRLSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_1_RBCTRLSTORE_ECC_LIMIT_ERR 6:6 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_1_RBCTRLSTORE_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_1_RBCTRLSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_1_RBCTRLSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_1_RBCTRLSTORE_ECC_DBE_ERR 7:7 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_1_RBCTRLSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_1_RBCTRLSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_1_RBCTRLSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_1_MCREDSGT_ECC_LIMIT_ERR 8:8 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_1_MCREDSGT_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_1_MCREDSGT_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_1_MCREDSGT_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_1_MCREDSGT_ECC_DBE_ERR 9:9 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_1_MCREDSGT_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_1_MCREDSGT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_1_MCREDSGT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_1_MCREDBUF_ECC_LIMIT_ERR 10:10 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_1_MCREDBUF_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_1_MCREDBUF_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_1_MCREDBUF_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_1_MCREDBUF_ECC_DBE_ERR 11:11 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_1_MCREDBUF_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_1_MCREDBUF_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_1_MCREDBUF_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_1_MCRSP_RAM_HDR_ECC_LIMIT_ERR 12:12 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_1_MCRSP_RAM_HDR_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_1_MCRSP_RAM_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_1_MCRSP_RAM_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_1_MCRSP_RAM_HDR_ECC_DBE_ERR 13:13 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_1_MCRSP_RAM_HDR_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_1_MCRSP_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_1_MCRSP_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_1_MCRSP_CNT_ERR 14:14 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_1_MCRSP_CNT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_1_MCRSP_CNT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_1_MCRSP_CNT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_1_RBRSP_CNT_ERR 15:15 /* RWEVF */ +#define NV_EGRESS_ERR_LOG_EN_1_RBRSP_CNT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_LOG_EN_1_RBRSP_CNT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_LOG_EN_1_RBRSP_CNT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1 0x00004908 /* RW-4R */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR 0:0 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_NXBAR_REDUCTION_HDR_ECC_DBE_ERR 1:1 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_NXBAR_REDUCTION_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_NXBAR_REDUCTION_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_NXBAR_REDUCTION_HDR_PARITY_ERR 2:2 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_NXBAR_REDUCTION_HDR_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_NXBAR_REDUCTION_HDR_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR 3:3 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_MCRSPCTRLSTORE_ECC_LIMIT_ERR 4:4 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_MCRSPCTRLSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_MCRSPCTRLSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_MCRSPCTRLSTORE_ECC_DBE_ERR 5:5 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_MCRSPCTRLSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_MCRSPCTRLSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_MCRSPCTRLSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_RBCTRLSTORE_ECC_LIMIT_ERR 6:6 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_RBCTRLSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_RBCTRLSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_RBCTRLSTORE_ECC_DBE_ERR 7:7 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_RBCTRLSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_RBCTRLSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_RBCTRLSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_MCREDSGT_ECC_LIMIT_ERR 8:8 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_MCREDSGT_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_MCREDSGT_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_MCREDSGT_ECC_DBE_ERR 9:9 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_MCREDSGT_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_MCREDSGT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_MCREDSGT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_MCREDBUF_ECC_LIMIT_ERR 10:10 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_MCREDBUF_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_MCREDBUF_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_MCREDBUF_ECC_DBE_ERR 11:11 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_MCREDBUF_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_MCREDBUF_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_MCRSP_RAM_HDR_ECC_LIMIT_ERR 12:12 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_MCRSP_RAM_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_MCRSP_RAM_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_MCRSP_RAM_HDR_ECC_DBE_ERR 13:13 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_MCRSP_RAM_HDR_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_MCRSP_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_MCRSP_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_MCRSP_CNT_ERR 14:14 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_MCRSP_CNT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_MCRSP_CNT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_RBRSP_CNT_ERR 15:15 /* RWEVF */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_RBRSP_CNT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_FATAL_REPORT_EN_1_RBRSP_CNT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1 0x0000490c /* RW-4R */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR 0:0 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_NXBAR_REDUCTION_HDR_ECC_DBE_ERR 1:1 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_NXBAR_REDUCTION_HDR_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_NXBAR_REDUCTION_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_NXBAR_REDUCTION_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_NXBAR_REDUCTION_HDR_PARITY_ERR 2:2 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_NXBAR_REDUCTION_HDR_PARITY_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_NXBAR_REDUCTION_HDR_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_NXBAR_REDUCTION_HDR_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR 3:3 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_MCRSPCTRLSTORE_ECC_LIMIT_ERR 4:4 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_MCRSPCTRLSTORE_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_MCRSPCTRLSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_MCRSPCTRLSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_MCRSPCTRLSTORE_ECC_DBE_ERR 5:5 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_MCRSPCTRLSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_MCRSPCTRLSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_RBCTRLSTORE_ECC_LIMIT_ERR 6:6 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_RBCTRLSTORE_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_RBCTRLSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_RBCTRLSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_RBCTRLSTORE_ECC_DBE_ERR 7:7 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_RBCTRLSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_RBCTRLSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_MCREDSGT_ECC_LIMIT_ERR 8:8 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_MCREDSGT_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_MCREDSGT_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_MCREDSGT_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_MCREDSGT_ECC_DBE_ERR 9:9 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_MCREDSGT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_MCREDSGT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_MCREDBUF_ECC_LIMIT_ERR 10:10 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_MCREDBUF_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_MCREDBUF_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_MCREDBUF_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_MCREDBUF_ECC_DBE_ERR 11:11 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_MCREDBUF_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_MCREDBUF_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_MCREDBUF_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_MCRSP_RAM_HDR_ECC_LIMIT_ERR 12:12 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_MCRSP_RAM_HDR_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_MCRSP_RAM_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_MCRSP_RAM_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_MCRSP_RAM_HDR_ECC_DBE_ERR 13:13 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_MCRSP_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_MCRSP_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_MCRSP_CNT_ERR 14:14 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_MCRSP_CNT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_MCRSP_CNT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_MCRSP_CNT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_RBRSP_CNT_ERR 15:15 /* RWEVF */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_RBRSP_CNT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_RBRSP_CNT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_1_RBRSP_CNT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_1 0x00004910 /* RW-4R */ +#define NV_EGRESS_ERR_CONTAIN_EN_1 0x00004914 /* RW-4R */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR 0:0 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_NXBAR_REDUCTION_HDR_ECC_DBE_ERR 1:1 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_NXBAR_REDUCTION_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_NXBAR_REDUCTION_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_NXBAR_REDUCTION_HDR_PARITY_ERR 2:2 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_NXBAR_REDUCTION_HDR_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_NXBAR_REDUCTION_HDR_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR 3:3 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_MCRSPCTRLSTORE_ECC_LIMIT_ERR 4:4 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_MCRSPCTRLSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_MCRSPCTRLSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_MCRSPCTRLSTORE_ECC_DBE_ERR 5:5 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_MCRSPCTRLSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_MCRSPCTRLSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_MCRSPCTRLSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_RBCTRLSTORE_ECC_LIMIT_ERR 6:6 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_RBCTRLSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_RBCTRLSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_RBCTRLSTORE_ECC_DBE_ERR 7:7 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_RBCTRLSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_RBCTRLSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_RBCTRLSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_MCREDSGT_ECC_LIMIT_ERR 8:8 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_MCREDSGT_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_MCREDSGT_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_MCREDSGT_ECC_DBE_ERR 9:9 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_MCREDSGT_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_MCREDSGT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_MCREDSGT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_MCREDBUF_ECC_LIMIT_ERR 10:10 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_MCREDBUF_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_MCREDBUF_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_MCREDBUF_ECC_DBE_ERR 11:11 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_MCREDBUF_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_MCREDBUF_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_MCRSP_RAM_HDR_ECC_LIMIT_ERR 12:12 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_MCRSP_RAM_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_MCRSP_RAM_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_MCRSP_RAM_HDR_ECC_DBE_ERR 13:13 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_MCRSP_RAM_HDR_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_MCRSP_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_MCRSP_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_MCRSP_CNT_ERR 14:14 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_MCRSP_CNT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_MCRSP_CNT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_RBRSP_CNT_ERR 15:15 /* RWEVF */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_RBRSP_CNT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_EGRESS_ERR_CONTAIN_EN_1_RBRSP_CNT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_1 0x0000491c /* RW-4R */ +#define NV_EGRESS_ERR_FIRST_1_NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR 0:0 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_1_NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_1_NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_1_NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_1_NXBAR_REDUCTION_HDR_ECC_DBE_ERR 1:1 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_1_NXBAR_REDUCTION_HDR_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_1_NXBAR_REDUCTION_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_1_NXBAR_REDUCTION_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_1_NXBAR_REDUCTION_HDR_PARITY_ERR 2:2 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_1_NXBAR_REDUCTION_HDR_PARITY_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_1_NXBAR_REDUCTION_HDR_PARITY_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_1_NXBAR_REDUCTION_HDR_PARITY_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_1_NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR 3:3 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_1_NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_1_NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_1_NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_1_MCRSPCTRLSTORE_ECC_LIMIT_ERR 4:4 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_1_MCRSPCTRLSTORE_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_1_MCRSPCTRLSTORE_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_1_MCRSPCTRLSTORE_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_1_MCRSPCTRLSTORE_ECC_DBE_ERR 5:5 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_1_MCRSPCTRLSTORE_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_1_MCRSPCTRLSTORE_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_1_MCRSPCTRLSTORE_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_1_RBCTRLSTORE_ECC_LIMIT_ERR 6:6 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_1_RBCTRLSTORE_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_1_RBCTRLSTORE_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_1_RBCTRLSTORE_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_1_RBCTRLSTORE_ECC_DBE_ERR 7:7 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_1_RBCTRLSTORE_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_1_RBCTRLSTORE_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_1_RBCTRLSTORE_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_1_MCREDSGT_ECC_LIMIT_ERR 8:8 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_1_MCREDSGT_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_1_MCREDSGT_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_1_MCREDSGT_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_1_MCREDSGT_ECC_DBE_ERR 9:9 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_1_MCREDSGT_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_1_MCREDSGT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_1_MCREDSGT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_1_MCREDBUF_ECC_LIMIT_ERR 10:10 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_1_MCREDBUF_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_1_MCREDBUF_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_1_MCREDBUF_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_1_MCREDBUF_ECC_DBE_ERR 11:11 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_1_MCREDBUF_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_1_MCREDBUF_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_1_MCREDBUF_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_1_MCRSP_RAM_HDR_ECC_LIMIT_ERR 12:12 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_1_MCRSP_RAM_HDR_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_1_MCRSP_RAM_HDR_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_1_MCRSP_RAM_HDR_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_1_MCRSP_RAM_HDR_ECC_DBE_ERR 13:13 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_1_MCRSP_RAM_HDR_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_1_MCRSP_RAM_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_1_MCRSP_RAM_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_1_MCRSP_CNT_ERR 14:14 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_1_MCRSP_CNT_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_1_MCRSP_CNT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_1_MCRSP_CNT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_ERR_FIRST_1_RBRSP_CNT_ERR 15:15 /* RWDVF */ +#define NV_EGRESS_ERR_FIRST_1_RBRSP_CNT_ERR__ONWRITE "oneToClear" /* */ +#define NV_EGRESS_ERR_FIRST_1_RBRSP_CNT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_EGRESS_ERR_FIRST_1_RBRSP_CNT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_EGRESS_MC_ERR_HEADER_LOG_4 0x00004930 /* R--4R */ +#define NV_EGRESS_MC_ERR_HEADER_LOG_4_DW 31:0 /* R-DVF */ +#define NV_EGRESS_MC_ERR_HEADER_LOG_4_DW_INIT 0x00000000 /* R-D-V */ +#define NV_EGRESS_MC_ERR_HEADER_LOG_5 0x00004934 /* R--4R */ +#define NV_EGRESS_MC_ERR_HEADER_LOG_5_DW 31:0 /* R-DVF */ +#define NV_EGRESS_MC_ERR_HEADER_LOG_5_DW_INIT 0x00000000 /* R-D-V */ +#define NV_EGRESS_MC_ERR_HEADER_LOG_6 0x00004938 /* R--4R */ +#define NV_EGRESS_MC_ERR_HEADER_LOG_6_DW 31:0 /* R-DVF */ +#define NV_EGRESS_MC_ERR_HEADER_LOG_6_DW_INIT 0x00000000 /* R-D-V */ +#define NV_EGRESS_MC_ERR_HEADER_LOG_7 0x0000493c /* R--4R */ +#define NV_EGRESS_MC_ERR_HEADER_LOG_7_DW 31:0 /* R-DVF */ +#define NV_EGRESS_MC_ERR_HEADER_LOG_7_DW_INIT 0x00000000 /* R-D-V */ +#define NV_EGRESS_MC_ERR_HEADER_LOG_8 0x00004940 /* R--4R */ +#define NV_EGRESS_MC_ERR_HEADER_LOG_8_DW 31:0 /* R-DVF */ +#define NV_EGRESS_MC_ERR_HEADER_LOG_8_DW_INIT 0x00000000 /* R-D-V */ +#define NV_EGRESS_MC_ERR_HEADER_LOG_9 0x00004944 /* R--4R */ +#define NV_EGRESS_MC_ERR_HEADER_LOG_9_DW 31:0 /* R-DVF */ +#define NV_EGRESS_MC_ERR_HEADER_LOG_9_DW_INIT 0x00000000 /* R-D-V */ +#define NV_EGRESS_MC_ERR_HEADER_LOG_10 0x00004948 /* R--4R */ +#define NV_EGRESS_MC_ERR_HEADER_LOG_10_DW 31:0 /* R-DVF */ +#define NV_EGRESS_MC_ERR_HEADER_LOG_10_DW_INIT 0x00000000 /* R-D-V */ +#define NV_EGRESS_MC_ERR_HEADER_LOG_VALID 0x0000494c /* R--4R */ +#define NV_EGRESS_MC_ERR_HEADER_LOG_VALID_HEADERVALID0 0:0 /* R-DVF */ +#define NV_EGRESS_MC_ERR_HEADER_LOG_VALID_HEADERVALID0_INVALID 0x00000000 /* R-D-V */ +#define NV_EGRESS_MC_ERR_HEADER_LOG_VALID_HEADERVALID0_VALID 0x00000001 /* R---V */ +#define NV_EGRESS_MC_ERR_TIMESTAMP_LOG 0x00004950 /* R--4R */ +#define NV_EGRESS_MC_ERR_TIMESTAMP_LOG_TIMESTAMP 23:0 /* R-IVF */ +#define NV_EGRESS_MC_ERR_TIMESTAMP_LOG_TIMESTAMP_INIT 0x00000000 /* R-I-V */ +#define NV_EGRESS_MC_ERR_MISC_LOG_0 0x00004954 /* R--4R */ +#define NV_EGRESS_MC_ERR_MISC_LOG_0_SPORT 6:0 /* R-IVF */ +#define NV_EGRESS_MC_ERR_MISC_LOG_0_SPORT_INIT 0x00000000 /* R-I-V */ +#endif // __ls10_dev_egress_ip_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_falcon_v4.h b/src/common/inc/swref/published/nvswitch/ls10/dev_falcon_v4.h new file mode 100644 index 000000000..29162d70b --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_falcon_v4.h @@ -0,0 +1,330 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_falcon_v4_h__ +#define __ls10_dev_falcon_v4_h__ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK 0x0000028c /* RW-4R */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ +#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK 0x000003c4 /* RW-4R */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ +#define NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ +#define NV_PFALCON_FALCON_IRQSSET 0x00000000 /* -W-4R */ +#define NV_PFALCON_FALCON_IRQSSET_GPTMR 0:0 /* -WXVF */ +#define NV_PFALCON_FALCON_IRQSSET_GPTMR_SET 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_IRQSSET_WDTMR 1:1 /* -WXVF */ +#define NV_PFALCON_FALCON_IRQSSET_WDTMR_SET 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_IRQSSET_MTHD 2:2 /* -WXVF */ +#define NV_PFALCON_FALCON_IRQSSET_MTHD_SET 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_IRQSSET_CTXSW 3:3 /* -WXVF */ +#define NV_PFALCON_FALCON_IRQSSET_CTXSW_SET 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_IRQSSET_HALT 4:4 /* -WXVF */ +#define NV_PFALCON_FALCON_IRQSSET_HALT_SET 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_IRQSSET_EXTERR 5:5 /* -WXVF */ +#define NV_PFALCON_FALCON_IRQSSET_EXTERR_SET 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_IRQSSET_SWGEN0 6:6 /* -WXVF */ +#define NV_PFALCON_FALCON_IRQSSET_SWGEN0_SET 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_IRQSSET_SWGEN1 7:7 /* -WXVF */ +#define NV_PFALCON_FALCON_IRQSSET_SWGEN1_SET 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_IRQSSET_EXT 15:8 /* -WXVF */ +#define NV_PFALCON_FALCON_IRQSSET_DMA 16:16 /* -WXVF */ +#define NV_PFALCON_FALCON_IRQSSET_DMA_SET 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_IRQSSET_SHA 17:17 /* -WXVF */ +#define NV_PFALCON_FALCON_IRQSSET_SHA_SET 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_IRQSSET_MEMERR 18:18 /* -WXVF */ +#define NV_PFALCON_FALCON_IRQSSET_MEMERR_SET 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_IRQSSET_CTXSW_ERROR 19:19 /* -WXVF */ +#define NV_PFALCON_FALCON_IRQSSET_CTXSW_ERROR_SET 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_IRQSSET_ICD 22:22 /* -WXVF */ +#define NV_PFALCON_FALCON_IRQSSET_ICD_SET 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_IRQSSET_IOPMP 23:23 /* -WXVF */ +#define NV_PFALCON_FALCON_IRQSSET_IOPMP_SET 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_IRQSSET_CORE_MISMATCH 24:24 /* -WXVF */ +#define NV_PFALCON_FALCON_IRQSSET_CORE_MISMATCH_SET 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_IRQSCLR 0x00000004 /* -W-4R */ +#define NV_PFALCON_FALCON_IRQSCLR_GPTMR 0:0 /* -WXVF */ +#define NV_PFALCON_FALCON_IRQSCLR_GPTMR_SET 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_IRQSCLR_WDTMR 1:1 /* -WXVF */ +#define NV_PFALCON_FALCON_IRQSCLR_WDTMR_SET 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_IRQSCLR_MTHD 2:2 /* -WXVF */ +#define NV_PFALCON_FALCON_IRQSCLR_MTHD_SET 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_IRQSCLR_CTXSW 3:3 /* -WXVF */ +#define NV_PFALCON_FALCON_IRQSCLR_CTXSW_SET 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_IRQSCLR_HALT 4:4 /* -WXVF */ +#define NV_PFALCON_FALCON_IRQSCLR_HALT_SET 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_IRQSCLR_EXTERR 5:5 /* -WXVF */ +#define NV_PFALCON_FALCON_IRQSCLR_EXTERR_SET 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_IRQSCLR_SWGEN0 6:6 /* -WXVF */ +#define NV_PFALCON_FALCON_IRQSCLR_SWGEN0_SET 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_IRQSCLR_SWGEN1 7:7 /* -WXVF */ +#define NV_PFALCON_FALCON_IRQSCLR_SWGEN1_SET 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_IRQSCLR_EXT 15:8 /* */ +#define NV_PFALCON_FALCON_IRQSCLR_DMA 16:16 /* -WXVF */ +#define NV_PFALCON_FALCON_IRQSCLR_DMA_SET 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_IRQSCLR_SHA 17:17 /* -WXVF */ +#define NV_PFALCON_FALCON_IRQSCLR_SHA_SET 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_IRQSCLR_MEMERR 18:18 /* -WXVF */ +#define NV_PFALCON_FALCON_IRQSCLR_MEMERR_SET 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_IRQSCLR_CTXSW_ERROR 19:19 /* -WXVF */ +#define NV_PFALCON_FALCON_IRQSCLR_CTXSW_ERROR_SET 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_IRQSCLR_ICD 22:22 /* -WXVF */ +#define NV_PFALCON_FALCON_IRQSCLR_ICD_SET 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_IRQSCLR_IOPMP 23:23 /* -WXVF */ +#define NV_PFALCON_FALCON_IRQSCLR_IOPMP_SET 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_IRQSCLR_CORE_MISMATCH 24:24 /* -WXVF */ +#define NV_PFALCON_FALCON_IRQSCLR_CORE_MISMATCH_SET 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_IRQSTAT 0x00000008 /* R--4R */ +#define NV_PFALCON_FALCON_IRQSTAT_GPTMR 0:0 /* R-IVF */ +#define NV_PFALCON_FALCON_IRQSTAT_GPTMR_FALSE 0x00000000 /* R-I-V */ +#define NV_PFALCON_FALCON_IRQSTAT_GPTMR_TRUE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_IRQSTAT_WDTMR 1:1 /* R-IVF */ +#define NV_PFALCON_FALCON_IRQSTAT_WDTMR_FALSE 0x00000000 /* R-I-V */ +#define NV_PFALCON_FALCON_IRQSTAT_WDTMR_TRUE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_IRQSTAT_MTHD 2:2 /* R-IVF */ +#define NV_PFALCON_FALCON_IRQSTAT_MTHD_FALSE 0x00000000 /* R-I-V */ +#define NV_PFALCON_FALCON_IRQSTAT_MTHD_TRUE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_IRQSTAT_CTXSW 3:3 /* R-IVF */ +#define NV_PFALCON_FALCON_IRQSTAT_CTXSW_FALSE 0x00000000 /* R-I-V */ +#define NV_PFALCON_FALCON_IRQSTAT_CTXSW_TRUE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_IRQSTAT_HALT 4:4 /* R-IVF */ +#define NV_PFALCON_FALCON_IRQSTAT_HALT_FALSE 0x00000000 /* R-I-V */ +#define NV_PFALCON_FALCON_IRQSTAT_HALT_TRUE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_IRQSTAT_EXTERR 5:5 /* R-IVF */ +#define NV_PFALCON_FALCON_IRQSTAT_EXTERR_FALSE 0x00000000 /* R-I-V */ +#define NV_PFALCON_FALCON_IRQSTAT_EXTERR_TRUE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_IRQSTAT_SWGEN0 6:6 /* R-IVF */ +#define NV_PFALCON_FALCON_IRQSTAT_SWGEN0_FALSE 0x00000000 /* R-I-V */ +#define NV_PFALCON_FALCON_IRQSTAT_SWGEN0_TRUE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1 7:7 /* R-IVF */ +#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1_FALSE 0x00000000 /* R-I-V */ +#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1_TRUE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_IRQSTAT_EXT 15:8 /* */ +#define NV_PFALCON_FALCON_IRQSTAT_DMA 16:16 /* R-IVF */ +#define NV_PFALCON_FALCON_IRQSTAT_DMA_TRUE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_IRQSTAT_DMA_FALSE 0x00000000 /* R-I-V */ +#define NV_PFALCON_FALCON_IRQSTAT_SHA 17:17 /* R-IVF */ +#define NV_PFALCON_FALCON_IRQSTAT_SHA_TRUE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_IRQSTAT_SHA_FALSE 0x00000000 /* R-I-V */ +#define NV_PFALCON_FALCON_IRQSTAT_MEMERR 18:18 /* R-IVF */ +#define NV_PFALCON_FALCON_IRQSTAT_MEMERR_TRUE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_IRQSTAT_MEMERR_FALSE 0x00000000 /* R-I-V */ +#define NV_PFALCON_FALCON_IRQSTAT_CTXSW_ERROR 19:19 /* R-XVF */ +#define NV_PFALCON_FALCON_IRQSTAT_CTXSW_ERROR_TRUE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_IRQSTAT_CTXSW_ERROR_FALSE 0x00000000 /* R---V */ +#define NV_PFALCON_FALCON_IRQSTAT_ICD 22:22 /* R-XVF */ +#define NV_PFALCON_FALCON_IRQSTAT_ICD_TRUE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_IRQSTAT_ICD_FALSE 0x00000000 /* R---V */ +#define NV_PFALCON_FALCON_IRQSTAT_IOPMP 23:23 /* R-XVF */ +#define NV_PFALCON_FALCON_IRQSTAT_IOPMP_TRUE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_IRQSTAT_IOPMP_FALSE 0x00000000 /* R---V */ +#define NV_PFALCON_FALCON_IRQSTAT_CORE_MISMATCH 24:24 /* R-XVF */ +#define NV_PFALCON_FALCON_IRQSTAT_CORE_MISMATCH_TRUE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_IRQSTAT_CORE_MISMATCH_FALSE 0x00000000 /* R---V */ +#define NV_PFALCON_FALCON_IRQMODE 0x0000000c /* RW-4R */ +#define NV_PFALCON_FALCON_IRQMASK 0x00000018 /* R--4R */ +#define NV_PFALCON_FALCON_MAILBOX0 0x00000040 /* RW-4R */ +#define NV_PFALCON_FALCON_MAILBOX0_DATA 31:0 /* RWIVF */ +#define NV_PFALCON_FALCON_MAILBOX0_DATA_INIT 0x00000000 /* RWI-V */ +#define NV_PFALCON_FALCON_MAILBOX1 0x00000044 /* RW-4R */ +#define NV_PFALCON_FALCON_MAILBOX1_DATA 31:0 /* RWIVF */ +#define NV_PFALCON_FALCON_MAILBOX1_DATA_INIT 0x00000000 /* RWI-V */ +#define NV_PFALCON_FALCON_IDLESTATE 0x0000004c /* RW-4R */ +#define NV_PFALCON_FALCON_DMACTL 0x0000010c /* RW-4R */ +#define NV_PFALCON_FALCON_DMATRFBASE 0x00000110 /* RW-4R */ +#define NV_PFALCON_FALCON_DMATRFBASE_BASE 31:0 /* RWIVF */ +#define NV_PFALCON_FALCON_DMATRFBASE_BASE_INIT 0x00000000 /* RWI-V */ +#define NV_PFALCON_FALCON_DMATRFMOFFS 0x00000114 /* RW-4R */ +#define NV_PFALCON_FALCON_DMATRFMOFFS_OFFS 23:0 /* RWIVF */ +#define NV_PFALCON_FALCON_DMATRFMOFFS_OFFS_INIT 0x00000000 /* RWI-V */ +#define NV_PFALCON_FALCON_DMATRFCMD 0x00000118 /* RW-4R */ +#define NV_PFALCON_FALCON_DMATRFFBOFFS 0x0000011c /* RW-4R */ +#define NV_PFALCON_FALCON_DMATRFFBOFFS_OFFS 31:0 /* RWIVF */ +#define NV_PFALCON_FALCON_DMATRFFBOFFS_OFFS_INIT 0x00000000 /* RWI-V */ +#define NV_PFALCON_FALCON_DMEMC(i) (0x000001c0+(i)*8) /* RW-4A */ +#define NV_PFALCON_FALCON_DMEMC__SIZE_1 4 /* */ +#define NV_PFALCON_FALCON_DMEMC__DEVICE_MAP 0x00000006 /* */ +#define NV_PFALCON_FALCON_DMEMC__PRIV_LEVEL_MASK NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ +#define NV_PFALCON_FALCON_DMEMC_ADDRESS 23:0 /* RWIVF */ +#define NV_PFALCON_FALCON_DMEMC_ADDRESS_INIT 0x00000000 /* RWI-V */ +#define NV_PFALCON_FALCON_DMEMC_OFFS 7:2 /* */ +#define NV_PFALCON_FALCON_DMEMC_OFFS_INIT 0 /* */ +#define NV_PFALCON_FALCON_DMEMC_BLK 23:8 /* */ +#define NV_PFALCON_FALCON_DMEMC_BLK_INIT 0 /* */ +#define NV_PFALCON_FALCON_DMEMC_AINCW 24:24 /* RWIVF */ +#define NV_PFALCON_FALCON_DMEMC_AINCW_INIT 0x00000000 /* RWI-V */ +#define NV_PFALCON_FALCON_DMEMC_AINCW_TRUE 0x00000001 /* RW--V */ +#define NV_PFALCON_FALCON_DMEMC_AINCW_FALSE 0x00000000 /* RW--V */ +#define NV_PFALCON_FALCON_DMEMC_AINCR 25:25 /* RWIVF */ +#define NV_PFALCON_FALCON_DMEMC_AINCR_INIT 0x00000000 /* RWI-V */ +#define NV_PFALCON_FALCON_DMEMC_AINCR_TRUE 0x00000001 /* RW--V */ +#define NV_PFALCON_FALCON_DMEMC_AINCR_FALSE 0x00000000 /* RW--V */ +#define NV_PFALCON_FALCON_DMEMC_SETTAG 26:26 /* RWIVF */ +#define NV_PFALCON_FALCON_DMEMC_SETTAG_INIT 0x00000000 /* RWI-V */ +#define NV_PFALCON_FALCON_DMEMC_SETTAG_TRUE 0x00000001 /* RW--V */ +#define NV_PFALCON_FALCON_DMEMC_SETTAG_FALSE 0x00000000 /* RW--V */ +#define NV_PFALCON_FALCON_DMEMC_SETLVL 27:27 /* RWIVF */ +#define NV_PFALCON_FALCON_DMEMC_SETLVL_INIT 0x00000000 /* RWI-V */ +#define NV_PFALCON_FALCON_DMEMC_SETLVL_TRUE 0x00000001 /* RW--V */ +#define NV_PFALCON_FALCON_DMEMC_SETLVL_FALSE 0x00000000 /* RW--V */ +#define NV_PFALCON_FALCON_DMEMC_VA 28:28 /* RWIVF */ +#define NV_PFALCON_FALCON_DMEMC_VA_INIT 0x00000000 /* RWI-V */ +#define NV_PFALCON_FALCON_DMEMC_VA_TRUE 0x00000001 /* RW--V */ +#define NV_PFALCON_FALCON_DMEMC_VA_FALSE 0x00000000 /* RW--V */ +#define NV_PFALCON_FALCON_DMEMC_MISS 29:29 /* R-IVF */ +#define NV_PFALCON_FALCON_DMEMC_MISS_TRUE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_DMEMC_MISS_FALSE 0x00000000 /* R-I-V */ +#define NV_PFALCON_FALCON_DMEMC_MULTIHIT 30:30 /* R-IVF */ +#define NV_PFALCON_FALCON_DMEMC_MULTIHIT_TRUE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_DMEMC_MULTIHIT_FALSE 0x00000000 /* R-I-V */ +#define NV_PFALCON_FALCON_DMEMC_LVLERR 31:31 /* R-IVF */ +#define NV_PFALCON_FALCON_DMEMC_LVLERR_TRUE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_DMEMC_LVLERR_FALSE 0x00000000 /* R-I-V */ +#define NV_PFALCON_FALCON_DMEMD(i) (0x000001c4+(i)*8) /* RW-4A */ +#define NV_PFALCON_FALCON_DMEMD__SIZE_1 4 /* */ +#define NV_PFALCON_FALCON_DMEMD__DEVICE_MAP 0x00000006 /* */ +#define NV_PFALCON_FALCON_DMEMD__PRIV_LEVEL_MASK NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ +#define NV_PFALCON_FALCON_DMEMD_DATA 31:0 /* RWXVF */ +#define NV_PFALCON_FALCON_HWCFG3 0x00000278 /* R--4R */ +#define NV_PFALCON_FALCON_HWCFG3_IMEM_TOTAL_SIZE 11:0 /* R--VF */ +#define NV_PFALCON_FALCON_HWCFG3_DMEM_TOTAL_SIZE 27:16 /* R--VF */ +#define NV_PFALCON_FALCON_OS 0x00000080 /* RW-4R */ +#define NV_PFALCON_FALCON_OS_VERSION 31:0 /* RWIVF */ +#define NV_PFALCON_FALCON_OS_VERSION_INIT 0x00000000 /* RWI-V */ +#define NV_PFALCON_FALCON_CPUCTL 0x00000100 /* RW-4R */ +#define NV_PFALCON_FALCON_CPUCTL_IINVAL 0:0 /* -WXVF */ +#define NV_PFALCON_FALCON_CPUCTL_IINVAL_TRUE 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_CPUCTL_IINVAL_FALSE 0x00000000 /* -W--V */ +#define NV_PFALCON_FALCON_CPUCTL_STARTCPU 1:1 /* -WXVF */ +#define NV_PFALCON_FALCON_CPUCTL_STARTCPU_TRUE 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_CPUCTL_STARTCPU_FALSE 0x00000000 /* -W--V */ +#define NV_PFALCON_FALCON_CPUCTL_SRESET 2:2 /* -WXVF */ +#define NV_PFALCON_FALCON_CPUCTL_SRESET_TRUE 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_CPUCTL_SRESET_FALSE 0x00000000 /* -W--V */ +#define NV_PFALCON_FALCON_CPUCTL_HRESET 3:3 /* -WXVF */ +#define NV_PFALCON_FALCON_CPUCTL_HRESET_TRUE 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_CPUCTL_HRESET_FALSE 0x00000000 /* -W--V */ +#define NV_PFALCON_FALCON_CPUCTL_HALTED 4:4 /* R-XVF */ +#define NV_PFALCON_FALCON_CPUCTL_HALTED_TRUE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_CPUCTL_HALTED_FALSE 0x00000000 /* R---V */ +#define NV_PFALCON_FALCON_CPUCTL_STOPPED 5:5 /* R-XVF */ +#define NV_PFALCON_FALCON_CPUCTL_STOPPED_TRUE 0x00000001 /* R---V */ +#define NV_PFALCON_FALCON_CPUCTL_STOPPED_FALSE 0x00000000 /* R---V */ +#define NV_PFALCON_FALCON_CPUCTL_ALIAS_EN 6:6 /* RWIVF */ +#define NV_PFALCON_FALCON_CPUCTL_ALIAS_EN_TRUE 0x00000001 /* RW--V */ +#define NV_PFALCON_FALCON_CPUCTL_ALIAS_EN_FALSE 0x00000000 /* RW--V */ +#define NV_PFALCON_FALCON_CPUCTL_ALIAS_EN_INIT 0x00000000 /* RWI-V */ +#define NV_PFALCON_FALCON_CPUCTL_ALIAS 0x00000130 /* -W-4R */ +#define NV_PFALCON_FALCON_CPUCTL_ALIAS_STARTCPU 1:1 /* -WXVF */ +#define NV_PFALCON_FALCON_CPUCTL_ALIAS_STARTCPU_TRUE 0x00000001 /* -W--V */ +#define NV_PFALCON_FALCON_CPUCTL_ALIAS_STARTCPU_FALSE 0x00000000 /* -W--V */ +#endif // __ls10_dev_falcon_v4_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_fsp_pri.h b/src/common/inc/swref/published/nvswitch/ls10/dev_fsp_pri.h new file mode 100644 index 000000000..a9e9ee1e0 --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_fsp_pri.h @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_fsp_pri_h__ +#define __ls10_dev_fsp_pri_h__ +/* This file is autogenerated. Do not edit */ +#define NV_PFSP 0x8F3FFF:0x8F0000 /* RW--D */ +#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(i) (0x008f0320+(i)*4) /* RW-4A */ +#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_1 4 /* */ +#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2__DEVICE_MAP 0x00000016 /* */ +#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2_VAL 31:0 /* RWIVF */ +#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2_VAL_INIT 0x00000000 /* RWI-V */ +#endif // __ls10_dev_fsp_pri_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_ingress_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_ingress_ip.h new file mode 100644 index 000000000..3ab43aa9b --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_ingress_ip.h @@ -0,0 +1,1466 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_ingress_ip_h__ +#define __ls10_dev_ingress_ip_h__ +/* This file is autogenerated. Do not edit */ +#define NV_INGRESS 0x00001fff:0x00001000 /* RW--D */ +#define NV_INGRESS_REQRSPMAPADDR 0x00001080 /* RW-4R */ +#define NV_INGRESS_REQRSPMAPADDR_RAM_ADDRESS 13:0 /* RWEVF */ +#define NV_INGRESS_REQRSPMAPADDR_RAM_ADDRESS_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_REQRSPMAPADDR_RAM_ADDRESS_NORMREMAPTAB_DEPTH 0x00000fff /* RW--V */ +#define NV_INGRESS_REQRSPMAPADDR_RAM_ADDRESS_EXTAREMAPTAB_DEPTH 0x0000003f /* RW--V */ +#define NV_INGRESS_REQRSPMAPADDR_RAM_ADDRESS_EXTBREMAPTAB_DEPTH 0x0000003f /* RW--V */ +#define NV_INGRESS_REQRSPMAPADDR_RAM_ADDRESS_RID_TAB_DEPTH 0x000007ff /* RW--V */ +#define NV_INGRESS_REQRSPMAPADDR_RAM_ADDRESS_RLAN_TAB_DEPTH 0x000007ff /* RW--V */ +#define NV_INGRESS_REQRSPMAPADDR_RAM_SEL 18:16 /* RWEVF */ +#define NV_INGRESS_REQRSPMAPADDR_RAM_SEL_SELECTSNORMREMAPRAM 0x00000000 /* RWE-V */ +#define NV_INGRESS_REQRSPMAPADDR_RAM_SEL_SELECTSRIDROUTERAM 0x00000001 /* RW--V */ +#define NV_INGRESS_REQRSPMAPADDR_RAM_SEL_SELECTSRLANROUTERAM 0x00000002 /* RW--V */ +#define NV_INGRESS_REQRSPMAPADDR_RAM_SEL_SELECTSEXTAREMAPRAM 0x00000003 /* RW--V */ +#define NV_INGRESS_REQRSPMAPADDR_RAM_SEL_SELECTSEXTBREMAPRAM 0x00000004 /* RW--V */ +#define NV_INGRESS_REQRSPMAPADDR_AUTO_INCR 31:31 /* RWEVF */ +#define NV_INGRESS_REQRSPMAPADDR_AUTO_INCR_ENABLE 0x00000001 /* RWE-V */ +#define NV_INGRESS_REQRSPMAPADDR_AUTO_INCR_DISABLE 0x00000000 /* RW--V */ +#define NV_INGRESS_MCREMAPTABADDR 0x00001084 /* RW-4R */ +#define NV_INGRESS_MCREMAPTABADDR_RAM_ADDRESS 6:0 /* RWEVF */ +#define NV_INGRESS_MCREMAPTABADDR_RAM_ADDRESS_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_MCREMAPTABADDR_RAM_ADDRESS_MCREMAPTAB_DEPTH 0x0000007f /* RW--V */ +#define NV_INGRESS_MCREMAPTABADDR_AUTO_INCR 31:31 /* RWEVF */ +#define NV_INGRESS_MCREMAPTABADDR_AUTO_INCR_ENABLE 0x00000001 /* RWE-V */ +#define NV_INGRESS_MCREMAPTABADDR_AUTO_INCR_DISABLE 0x00000000 /* RW--V */ +#define NV_INGRESS_REMAPTABDATA0 0x00001090 /* RW-4R */ +#define NV_INGRESS_REMAPTABDATA0_RMAP_ADDR 12:0 /* RWEVF */ +#define NV_INGRESS_REMAPTABDATA0_RMAP_ADDR_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_REMAPTABDATA0_IRL_SEL 16:15 /* RWEVF */ +#define NV_INGRESS_REMAPTABDATA0_IRL_SEL_SELECTNONE 0x00000000 /* RWE-V */ +#define NV_INGRESS_REMAPTABDATA0_IRL_SEL_SELECTIRL0 0x00000001 /* RW--V */ +#define NV_INGRESS_REMAPTABDATA0_IRL_SEL_SELECTIRL1 0x00000002 /* RW--V */ +#define NV_INGRESS_REMAPTABDATA0_IRL_SEL_ENABLEERRRSP 0x00000003 /* RW--V */ +#define NV_INGRESS_REMAPTABDATA0_ECC 30:22 /* R-EVF */ +#define NV_INGRESS_REMAPTABDATA0_ECC_INIT 0x00000000 /* R-E-V */ +#define NV_INGRESS_REMAPTABDATA0_ACLVALID 31:31 /* RWEVF */ +#define NV_INGRESS_REMAPTABDATA0_ACLVALID_INVALID 0x00000000 /* RWE-V */ +#define NV_INGRESS_REMAPTABDATA0_ACLVALID_VALID 0x00000001 /* RW--V */ +#define NV_INGRESS_REMAPTABDATA1 0x00001094 /* RW-4R */ +#define NV_INGRESS_REMAPTABDATA1_REQCTXT_MSK 15:0 /* RWEVF */ +#define NV_INGRESS_REMAPTABDATA1_REQCTXT_MSK_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_REMAPTABDATA1_REQCTXT_CHK 31:16 /* RWEVF */ +#define NV_INGRESS_REMAPTABDATA1_REQCTXT_CHK_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_REMAPTABDATA2 0x00001098 /* RW-4R */ +#define NV_INGRESS_REMAPTABDATA2_REQCTXT_REP 15:0 /* RWEVF */ +#define NV_INGRESS_REMAPTABDATA2_REQCTXT_REP_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_REMAPTABDATA3 0x0000109c /* RW-4R */ +#define NV_INGRESS_REMAPTABDATA3_ADR_BASE 15:0 /* RWEVF */ +#define NV_INGRESS_REMAPTABDATA3_ADR_BASE_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_REMAPTABDATA3_ADR_LIMIT 31:16 /* RWEVF */ +#define NV_INGRESS_REMAPTABDATA3_ADR_LIMIT_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_REMAPTABDATA4 0x000010a0 /* RW-4R */ +#define NV_INGRESS_REMAPTABDATA4_TGTID 10:0 /* RWEVF */ +#define NV_INGRESS_REMAPTABDATA4_TGTID_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_REMAPTABDATA4_RFUNC 21:15 /* RWEVF */ +#define NV_INGRESS_REMAPTABDATA4_RFUNC_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_REMAPTABDATA4_RSVD 31:31 /* RWEVF */ +#define NV_INGRESS_REMAPTABDATA4_RSVD_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_REMAPTABDATA5 0x000010a4 /* RW-4R */ +#define NV_INGRESS_REMAPTABDATA5_ADR_BASE 1:0 /* RWEVF */ +#define NV_INGRESS_REMAPTABDATA5_ADR_BASE_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_REMAPTABDATA5_ADR_LIMIT 5:4 /* RWEVF */ +#define NV_INGRESS_REMAPTABDATA5_ADR_LIMIT_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA0 0x000010b0 /* RW-4R */ +#define NV_INGRESS_RIDTABDATA0_GSIZE 3:0 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA0_GSIZE_16X 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA0_GSIZE_1X 0x00000001 /* RW--V */ +#define NV_INGRESS_RIDTABDATA0_GSIZE_2X 0x00000002 /* RW--V */ +#define NV_INGRESS_RIDTABDATA0_GSIZE_3X 0x00000003 /* RW--V */ +#define NV_INGRESS_RIDTABDATA0_GSIZE_4X 0x00000004 /* RW--V */ +#define NV_INGRESS_RIDTABDATA0_GSIZE_5X 0x00000005 /* RW--V */ +#define NV_INGRESS_RIDTABDATA0_GSIZE_6X 0x00000006 /* RW--V */ +#define NV_INGRESS_RIDTABDATA0_GSIZE_7X 0x00000007 /* RW--V */ +#define NV_INGRESS_RIDTABDATA0_GSIZE_8X 0x00000008 /* RW--V */ +#define NV_INGRESS_RIDTABDATA0_GSIZE_9X 0x00000009 /* RW--V */ +#define NV_INGRESS_RIDTABDATA0_GSIZE_10X 0x0000000a /* RW--V */ +#define NV_INGRESS_RIDTABDATA0_GSIZE_11X 0x0000000b /* RW--V */ +#define NV_INGRESS_RIDTABDATA0_GSIZE_12X 0x0000000c /* RW--V */ +#define NV_INGRESS_RIDTABDATA0_GSIZE_13X 0x0000000d /* RW--V */ +#define NV_INGRESS_RIDTABDATA0_GSIZE_14X 0x0000000e /* RW--V */ +#define NV_INGRESS_RIDTABDATA0_GSIZE_15X 0x0000000f /* RW--V */ +#define NV_INGRESS_RIDTABDATA0_PORT0 10:5 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA0_PORT0_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA0_VC_MODE0 13:12 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA0_VC_MODE0_SAME 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA0_VC_MODE0_INVERT 0x00000001 /* RW--V */ +#define NV_INGRESS_RIDTABDATA0_VC_MODE0_ALWAYS0 0x00000002 /* RW--V */ +#define NV_INGRESS_RIDTABDATA0_VC_MODE0_ALWAYS1 0x00000003 /* RW--V */ +#define NV_INGRESS_RIDTABDATA0_PORT1 19:14 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA0_PORT1_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA0_VC_MODE1 22:21 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA0_VC_MODE1_SAME 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA0_VC_MODE1_INVERT 0x00000001 /* RW--V */ +#define NV_INGRESS_RIDTABDATA0_VC_MODE1_ALWAYS0 0x00000002 /* RW--V */ +#define NV_INGRESS_RIDTABDATA0_VC_MODE1_ALWAYS1 0x00000003 /* RW--V */ +#define NV_INGRESS_RIDTABDATA0_PORT2 28:23 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA0_PORT2_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA0_VC_MODE2 31:30 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA0_VC_MODE2_SAME 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA0_VC_MODE2_INVERT 0x00000001 /* RW--V */ +#define NV_INGRESS_RIDTABDATA0_VC_MODE2_ALWAYS0 0x00000002 /* RW--V */ +#define NV_INGRESS_RIDTABDATA0_VC_MODE2_ALWAYS1 0x00000003 /* RW--V */ +#define NV_INGRESS_RIDTABDATA1 0x000010b4 /* RW-4R */ +#define NV_INGRESS_RIDTABDATA1_PORT3 5:0 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA1_PORT3_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA1_VC_MODE3 8:7 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA1_VC_MODE3_SAME 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA1_VC_MODE3_INVERT 0x00000001 /* RW--V */ +#define NV_INGRESS_RIDTABDATA1_VC_MODE3_ALWAYS0 0x00000002 /* RW--V */ +#define NV_INGRESS_RIDTABDATA1_VC_MODE3_ALWAYS1 0x00000003 /* RW--V */ +#define NV_INGRESS_RIDTABDATA1_PORT4 14:9 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA1_PORT4_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA1_VC_MODE4 17:16 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA1_VC_MODE4_SAME 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA1_VC_MODE4_INVERT 0x00000001 /* RW--V */ +#define NV_INGRESS_RIDTABDATA1_VC_MODE4_ALWAYS0 0x00000002 /* RW--V */ +#define NV_INGRESS_RIDTABDATA1_VC_MODE4_ALWAYS1 0x00000003 /* RW--V */ +#define NV_INGRESS_RIDTABDATA1_PORT5 23:18 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA1_PORT5_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA1_VC_MODE5 26:25 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA1_VC_MODE5_SAME 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA1_VC_MODE5_INVERT 0x00000001 /* RW--V */ +#define NV_INGRESS_RIDTABDATA1_VC_MODE5_ALWAYS0 0x00000002 /* RW--V */ +#define NV_INGRESS_RIDTABDATA1_VC_MODE5_ALWAYS1 0x00000003 /* RW--V */ +#define NV_INGRESS_RIDTABDATA2 0x000010b8 /* RW-4R */ +#define NV_INGRESS_RIDTABDATA2_PORT6 5:0 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA2_PORT6_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA2_VC_MODE6 8:7 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA2_VC_MODE6_SAME 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA2_VC_MODE6_INVERT 0x00000001 /* RW--V */ +#define NV_INGRESS_RIDTABDATA2_VC_MODE6_ALWAYS0 0x00000002 /* RW--V */ +#define NV_INGRESS_RIDTABDATA2_VC_MODE6_ALWAYS1 0x00000003 /* RW--V */ +#define NV_INGRESS_RIDTABDATA2_PORT7 14:9 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA2_PORT7_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA2_VC_MODE7 17:16 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA2_VC_MODE7_SAME 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA2_VC_MODE7_INVERT 0x00000001 /* RW--V */ +#define NV_INGRESS_RIDTABDATA2_VC_MODE7_ALWAYS0 0x00000002 /* RW--V */ +#define NV_INGRESS_RIDTABDATA2_VC_MODE7_ALWAYS1 0x00000003 /* RW--V */ +#define NV_INGRESS_RIDTABDATA2_PORT8 23:18 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA2_PORT8_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA2_VC_MODE8 26:25 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA2_VC_MODE8_SAME 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA2_VC_MODE8_INVERT 0x00000001 /* RW--V */ +#define NV_INGRESS_RIDTABDATA2_VC_MODE8_ALWAYS0 0x00000002 /* RW--V */ +#define NV_INGRESS_RIDTABDATA2_VC_MODE8_ALWAYS1 0x00000003 /* RW--V */ +#define NV_INGRESS_RIDTABDATA3 0x000010bc /* RW-4R */ +#define NV_INGRESS_RIDTABDATA3_PORT9 5:0 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA3_PORT9_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA3_VC_MODE9 8:7 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA3_VC_MODE9_SAME 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA3_VC_MODE9_INVERT 0x00000001 /* RW--V */ +#define NV_INGRESS_RIDTABDATA3_VC_MODE9_ALWAYS0 0x00000002 /* RW--V */ +#define NV_INGRESS_RIDTABDATA3_VC_MODE9_ALWAYS1 0x00000003 /* RW--V */ +#define NV_INGRESS_RIDTABDATA3_PORT10 14:9 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA3_PORT10_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA3_VC_MODE10 17:16 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA3_VC_MODE10_SAME 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA3_VC_MODE10_INVERT 0x00000001 /* RW--V */ +#define NV_INGRESS_RIDTABDATA3_VC_MODE10_ALWAYS0 0x00000002 /* RW--V */ +#define NV_INGRESS_RIDTABDATA3_VC_MODE10_ALWAYS1 0x00000003 /* RW--V */ +#define NV_INGRESS_RIDTABDATA3_PORT11 23:18 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA3_PORT11_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA3_VC_MODE11 26:25 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA3_VC_MODE11_SAME 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA3_VC_MODE11_INVERT 0x00000001 /* RW--V */ +#define NV_INGRESS_RIDTABDATA3_VC_MODE11_ALWAYS0 0x00000002 /* RW--V */ +#define NV_INGRESS_RIDTABDATA3_VC_MODE11_ALWAYS1 0x00000003 /* RW--V */ +#define NV_INGRESS_RIDTABDATA4 0x000010c0 /* RW-4R */ +#define NV_INGRESS_RIDTABDATA4_PORT12 5:0 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA4_PORT12_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA4_VC_MODE12 8:7 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA4_VC_MODE12_SAME 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA4_VC_MODE12_INVERT 0x00000001 /* RW--V */ +#define NV_INGRESS_RIDTABDATA4_VC_MODE12_ALWAYS0 0x00000002 /* RW--V */ +#define NV_INGRESS_RIDTABDATA4_VC_MODE12_ALWAYS1 0x00000003 /* RW--V */ +#define NV_INGRESS_RIDTABDATA4_PORT13 14:9 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA4_PORT13_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA4_VC_MODE13 17:16 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA4_VC_MODE13_SAME 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA4_VC_MODE13_INVERT 0x00000001 /* RW--V */ +#define NV_INGRESS_RIDTABDATA4_VC_MODE13_ALWAYS0 0x00000002 /* RW--V */ +#define NV_INGRESS_RIDTABDATA4_VC_MODE13_ALWAYS1 0x00000003 /* RW--V */ +#define NV_INGRESS_RIDTABDATA4_PORT14 23:18 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA4_PORT14_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA4_VC_MODE14 26:25 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA4_VC_MODE14_SAME 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA4_VC_MODE14_INVERT 0x00000001 /* RW--V */ +#define NV_INGRESS_RIDTABDATA4_VC_MODE14_ALWAYS0 0x00000002 /* RW--V */ +#define NV_INGRESS_RIDTABDATA4_VC_MODE14_ALWAYS1 0x00000003 /* RW--V */ +#define NV_INGRESS_RIDTABDATA5 0x000010c4 /* RW-4R */ +#define NV_INGRESS_RIDTABDATA5_PORT15 5:0 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA5_PORT15_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA5_VC_MODE15 8:7 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA5_VC_MODE15_SAME 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA5_VC_MODE15_INVERT 0x00000001 /* RW--V */ +#define NV_INGRESS_RIDTABDATA5_VC_MODE15_ALWAYS0 0x00000002 /* RW--V */ +#define NV_INGRESS_RIDTABDATA5_VC_MODE15_ALWAYS1 0x00000003 /* RW--V */ +#define NV_INGRESS_RIDTABDATA5_RMOD 18:9 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA5_RMOD_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA5_ECC 30:22 /* R-EVF */ +#define NV_INGRESS_RIDTABDATA5_ECC_INIT 0x00000000 /* R-E-V */ +#define NV_INGRESS_RIDTABDATA5_ACLVALID 31:31 /* RWEVF */ +#define NV_INGRESS_RIDTABDATA5_ACLVALID_INVALID 0x00000000 /* RWE-V */ +#define NV_INGRESS_RIDTABDATA5_ACLVALID_VALID 0x00000001 /* RW--V */ +#define NV_INGRESS_RLANTABDATA0 0x000010d0 /* RW-4R */ +#define NV_INGRESS_RLANTABDATA0_GRP_SIZE_0 3:0 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA0_GRP_SIZE_0_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA0_GRP_SEL_0 8:5 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA0_GRP_SEL_0_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA0_GRP_SIZE_1 13:10 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA0_GRP_SIZE_1_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA0_GRP_SEL_1 18:15 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA0_GRP_SEL_1_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA0_GRP_SIZE_2 23:20 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA0_GRP_SIZE_2_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA0_GRP_SEL_2 28:25 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA0_GRP_SEL_2_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA1 0x000010d4 /* RW-4R */ +#define NV_INGRESS_RLANTABDATA1_GRP_SIZE_3 3:0 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA1_GRP_SIZE_3_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA1_GRP_SEL_3 8:5 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA1_GRP_SEL_3_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA1_GRP_SIZE_4 13:10 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA1_GRP_SIZE_4_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA1_GRP_SEL_4 18:15 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA1_GRP_SEL_4_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA1_GRP_SIZE_5 23:20 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA1_GRP_SIZE_5_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA1_GRP_SEL_5 28:25 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA1_GRP_SEL_5_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA2 0x000010d8 /* RW-4R */ +#define NV_INGRESS_RLANTABDATA2_GRP_SIZE_6 3:0 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA2_GRP_SIZE_6_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA2_GRP_SEL_6 8:5 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA2_GRP_SEL_6_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA2_GRP_SIZE_7 13:10 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA2_GRP_SIZE_7_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA2_GRP_SEL_7 18:15 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA2_GRP_SEL_7_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA2_GRP_SIZE_8 23:20 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA2_GRP_SIZE_8_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA2_GRP_SEL_8 28:25 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA2_GRP_SEL_8_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA3 0x000010dc /* RW-4R */ +#define NV_INGRESS_RLANTABDATA3_GRP_SIZE_9 3:0 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA3_GRP_SIZE_9_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA3_GRP_SEL_9 8:5 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA3_GRP_SEL_9_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA3_GRP_SIZE_10 13:10 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA3_GRP_SIZE_10_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA3_GRP_SEL_10 18:15 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA3_GRP_SEL_10_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA3_GRP_SIZE_11 23:20 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA3_GRP_SIZE_11_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA3_GRP_SEL_11 28:25 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA3_GRP_SEL_11_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA4 0x000010e0 /* RW-4R */ +#define NV_INGRESS_RLANTABDATA4_GRP_SIZE_12 3:0 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA4_GRP_SIZE_12_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA4_GRP_SEL_12 8:5 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA4_GRP_SEL_12_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA4_GRP_SIZE_13 13:10 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA4_GRP_SIZE_13_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA4_GRP_SEL_13 18:15 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA4_GRP_SEL_13_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA4_GRP_SIZE_14 23:20 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA4_GRP_SIZE_14_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA4_GRP_SEL_14 28:25 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA4_GRP_SEL_14_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA5 0x000010e4 /* RW-4R */ +#define NV_INGRESS_RLANTABDATA5_GRP_SIZE_15 3:0 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA5_GRP_SIZE_15_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA5_GRP_SEL_15 8:5 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA5_GRP_SEL_15_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA5_RSVD 21:20 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA5_RSVD_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA5_ECC 30:22 /* R-EVF */ +#define NV_INGRESS_RLANTABDATA5_ECC_INIT 0x00000000 /* R-E-V */ +#define NV_INGRESS_RLANTABDATA5_ACLVALID 31:31 /* RWEVF */ +#define NV_INGRESS_RLANTABDATA5_ACLVALID_INVALID 0x00000000 /* RWE-V */ +#define NV_INGRESS_RLANTABDATA5_ACLVALID_VALID 0x00000001 /* RW--V */ +#define NV_INGRESS_MCREMAPTABDATA0 0x000010f0 /* RW-4R */ +#define NV_INGRESS_MCREMAPTABDATA0_RMAP_ADDR 12:0 /* RWEVF */ +#define NV_INGRESS_MCREMAPTABDATA0_RMAP_ADDR_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_MCREMAPTABDATA0_IRL_SEL 16:15 /* RWEVF */ +#define NV_INGRESS_MCREMAPTABDATA0_IRL_SEL_SELECTNONE 0x00000000 /* RWE-V */ +#define NV_INGRESS_MCREMAPTABDATA0_IRL_SEL_SELECTIRL0 0x00000001 /* RW--V */ +#define NV_INGRESS_MCREMAPTABDATA0_IRL_SEL_SELECTIRL1 0x00000002 /* RW--V */ +#define NV_INGRESS_MCREMAPTABDATA0_IRL_SEL_ENABLEERRRSP 0x00000003 /* RW--V */ +#define NV_INGRESS_MCREMAPTABDATA0_ECC 30:22 /* R-EVF */ +#define NV_INGRESS_MCREMAPTABDATA0_ECC_INIT 0x00000000 /* R-E-V */ +#define NV_INGRESS_MCREMAPTABDATA0_ACLVALID 31:31 /* RWEVF */ +#define NV_INGRESS_MCREMAPTABDATA0_ACLVALID_INVALID 0x00000000 /* RWE-V */ +#define NV_INGRESS_MCREMAPTABDATA0_ACLVALID_VALID 0x00000001 /* RW--V */ +#define NV_INGRESS_MCREMAPTABDATA1 0x000010f4 /* RW-4R */ +#define NV_INGRESS_MCREMAPTABDATA1_REQCTXT_MSK 15:0 /* RWEVF */ +#define NV_INGRESS_MCREMAPTABDATA1_REQCTXT_MSK_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_MCREMAPTABDATA1_REQCTXT_CHK 31:16 /* RWEVF */ +#define NV_INGRESS_MCREMAPTABDATA1_REQCTXT_CHK_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_MCREMAPTABDATA2 0x000010f8 /* RW-4R */ +#define NV_INGRESS_MCREMAPTABDATA2_REQCTXT_REP 15:0 /* RWEVF */ +#define NV_INGRESS_MCREMAPTABDATA2_REQCTXT_REP_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_MCREMAPTABDATA3 0x000010fc /* RW-4R */ +#define NV_INGRESS_MCREMAPTABDATA3_ADR_BASE 15:0 /* RWEVF */ +#define NV_INGRESS_MCREMAPTABDATA3_ADR_BASE_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_MCREMAPTABDATA3_ADR_LIMIT 31:16 /* RWEVF */ +#define NV_INGRESS_MCREMAPTABDATA3_ADR_LIMIT_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_MCREMAPTABDATA4 0x00001100 /* RW-4R */ +#define NV_INGRESS_MCREMAPTABDATA4_MCID 6:0 /* RWEVF */ +#define NV_INGRESS_MCREMAPTABDATA4_MCID_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_MCREMAPTABDATA4_RFUNC 21:15 /* RWEVF */ +#define NV_INGRESS_MCREMAPTABDATA4_RFUNC_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_MCREMAPTABDATA4_ENB_REFLECT_MEM 22:22 /* RWEVF */ +#define NV_INGRESS_MCREMAPTABDATA4_ENB_REFLECT_MEM_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_MCREMAPTABDATA5 0x00001104 /* RW-4R */ +#define NV_INGRESS_MCREMAPTABDATA5_ADR_BASE 1:0 /* RWEVF */ +#define NV_INGRESS_MCREMAPTABDATA5_ADR_BASE_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_MCREMAPTABDATA5_ADR_LIMIT 5:4 /* RWEVF */ +#define NV_INGRESS_MCREMAPTABDATA5_ADR_LIMIT_INIT 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_STATUS_0 0x00001400 /* RW-4R */ +#define NV_INGRESS_ERR_STATUS_0_CMDDECODEERR 0:0 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_0_CMDDECODEERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_0_CMDDECODEERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_0_CMDDECODEERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_0_EXTAREMAPTAB_ECC_DBE_ERR 1:1 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_0_EXTAREMAPTAB_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_0_EXTAREMAPTAB_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_0_EXTAREMAPTAB_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_0_REQCONTEXTMISMATCHERR 2:2 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_0_REQCONTEXTMISMATCHERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_0_REQCONTEXTMISMATCHERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_0_REQCONTEXTMISMATCHERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_0_ACLFAIL 3:3 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_0_ACLFAIL__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_0_ACLFAIL_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_0_ACLFAIL_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_0_NCISOC_HDR_ECC_LIMIT_ERR 4:4 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_0_NCISOC_HDR_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_0_NCISOC_HDR_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_0_NCISOC_HDR_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_0_NCISOC_HDR_ECC_DBE_ERR 5:5 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_0_NCISOC_HDR_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_0_NCISOC_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_0_NCISOC_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_0_INVALIDVCSET 6:6 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_0_INVALIDVCSET__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_0_INVALIDVCSET_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_0_INVALIDVCSET_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_0_ADDRBOUNDSERR 7:7 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_0_ADDRBOUNDSERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_0_ADDRBOUNDSERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_0_ADDRBOUNDSERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_0_RIDTABCFGERR 8:8 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_0_RIDTABCFGERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_0_RIDTABCFGERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_0_RIDTABCFGERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_0_RLANTABCFGERR 9:9 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_0_RLANTABCFGERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_0_RLANTABCFGERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_0_RLANTABCFGERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_0_REMAPTAB_ECC_DBE_ERR 10:10 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_0_REMAPTAB_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_0_REMAPTAB_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_0_REMAPTAB_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_0_RIDTAB_ECC_DBE_ERR 11:11 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_0_RIDTAB_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_0_RIDTAB_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_0_RIDTAB_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_0_RLANTAB_ECC_DBE_ERR 12:12 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_0_RLANTAB_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_0_RLANTAB_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_0_RLANTAB_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_0_NCISOC_PARITY_ERR 13:13 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_0_NCISOC_PARITY_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_0_NCISOC_PARITY_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_0_NCISOC_PARITY_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_0_REMAPTAB_ECC_LIMIT_ERR 14:14 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_0_REMAPTAB_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_0_REMAPTAB_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_0_REMAPTAB_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_0_RIDTAB_ECC_LIMIT_ERR 15:15 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_0_RIDTAB_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_0_RIDTAB_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_0_RIDTAB_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_0_RLANTAB_ECC_LIMIT_ERR 16:16 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_0_RLANTAB_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_0_RLANTAB_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_0_RLANTAB_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_0_ADDRTYPEERR 17:17 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_0_ADDRTYPEERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_0_ADDRTYPEERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_0_ADDRTYPEERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_0_EXTAREMAPTAB_INDEX_ERR 18:18 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_0_EXTAREMAPTAB_INDEX_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_0_EXTAREMAPTAB_INDEX_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_0_EXTAREMAPTAB_INDEX_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_0_EXTBREMAPTAB_INDEX_ERR 19:19 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_0_EXTBREMAPTAB_INDEX_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_0_EXTBREMAPTAB_INDEX_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_0_EXTBREMAPTAB_INDEX_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_0_MCREMAPTAB_INDEX_ERR 20:20 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_0_MCREMAPTAB_INDEX_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_0_MCREMAPTAB_INDEX_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_0_MCREMAPTAB_INDEX_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_0_EXTBREMAPTAB_ECC_DBE_ERR 21:21 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_0_EXTBREMAPTAB_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_0_EXTBREMAPTAB_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_0_EXTBREMAPTAB_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_0_MCREMAPTAB_ECC_DBE_ERR 22:22 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_0_MCREMAPTAB_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_0_MCREMAPTAB_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_0_MCREMAPTAB_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_0_EXTAREMAPTAB_REQCONTEXTMISMATCHERR 23:23 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_0_EXTAREMAPTAB_REQCONTEXTMISMATCHERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_0_EXTAREMAPTAB_REQCONTEXTMISMATCHERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_0_EXTAREMAPTAB_REQCONTEXTMISMATCHERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_0_EXTBREMAPTAB_REQCONTEXTMISMATCHERR 24:24 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_0_EXTBREMAPTAB_REQCONTEXTMISMATCHERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_0_EXTBREMAPTAB_REQCONTEXTMISMATCHERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_0_EXTBREMAPTAB_REQCONTEXTMISMATCHERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_0_MCREMAPTAB_REQCONTEXTMISMATCHERR 25:25 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_0_MCREMAPTAB_REQCONTEXTMISMATCHERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_0_MCREMAPTAB_REQCONTEXTMISMATCHERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_0_MCREMAPTAB_REQCONTEXTMISMATCHERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_0_EXTAREMAPTAB_ACLFAIL 26:26 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_0_EXTAREMAPTAB_ACLFAIL__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_0_EXTAREMAPTAB_ACLFAIL_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_0_EXTAREMAPTAB_ACLFAIL_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_0_EXTBREMAPTAB_ACLFAIL 27:27 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_0_EXTBREMAPTAB_ACLFAIL__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_0_EXTBREMAPTAB_ACLFAIL_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_0_EXTBREMAPTAB_ACLFAIL_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_0_MCREMAPTAB_ACLFAIL 28:28 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_0_MCREMAPTAB_ACLFAIL__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_0_MCREMAPTAB_ACLFAIL_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_0_MCREMAPTAB_ACLFAIL_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_0_EXTAREMAPTAB_ADDRBOUNDSERR 29:29 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_0_EXTAREMAPTAB_ADDRBOUNDSERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_0_EXTAREMAPTAB_ADDRBOUNDSERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_0_EXTAREMAPTAB_ADDRBOUNDSERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_0_EXTBREMAPTAB_ADDRBOUNDSERR 30:30 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_0_EXTBREMAPTAB_ADDRBOUNDSERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_0_EXTBREMAPTAB_ADDRBOUNDSERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_0_EXTBREMAPTAB_ADDRBOUNDSERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_0_MCREMAPTAB_ADDRBOUNDSERR 31:31 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_0_MCREMAPTAB_ADDRBOUNDSERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_0_MCREMAPTAB_ADDRBOUNDSERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_0_MCREMAPTAB_ADDRBOUNDSERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0 0x00001404 /* RW-4R */ +#define NV_INGRESS_ERR_LOG_EN_0_CMDDECODEERR 0:0 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_0_CMDDECODEERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_CMDDECODEERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_0_CMDDECODEERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTAREMAPTAB_ECC_DBE_ERR 1:1 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTAREMAPTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTAREMAPTAB_ECC_DBE_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTAREMAPTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTAREMAPTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_REQCONTEXTMISMATCHERR 2:2 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_0_REQCONTEXTMISMATCHERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_REQCONTEXTMISMATCHERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_REQCONTEXTMISMATCHERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_0_REQCONTEXTMISMATCHERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_ACLFAIL 3:3 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_0_ACLFAIL__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_ACLFAIL__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_ACLFAIL_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_0_ACLFAIL_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_HDR_ECC_LIMIT_ERR 4:4 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_HDR_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_HDR_ECC_DBE_ERR 5:5 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_HDR_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_INVALIDVCSET 6:6 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_0_INVALIDVCSET__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_INVALIDVCSET__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_INVALIDVCSET_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_0_INVALIDVCSET_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_ADDRBOUNDSERR 7:7 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_0_ADDRBOUNDSERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_ADDRBOUNDSERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_ADDRBOUNDSERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_0_ADDRBOUNDSERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_RIDTABCFGERR 8:8 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_0_RIDTABCFGERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_RIDTABCFGERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_0_RIDTABCFGERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_RLANTABCFGERR 9:9 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_0_RLANTABCFGERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_RLANTABCFGERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_0_RLANTABCFGERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_REMAPTAB_ECC_DBE_ERR 10:10 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_0_REMAPTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_REMAPTAB_ECC_DBE_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_REMAPTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_0_REMAPTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_RIDTAB_ECC_DBE_ERR 11:11 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_0_RIDTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_RIDTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_0_RIDTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_RLANTAB_ECC_DBE_ERR 12:12 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_0_RLANTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_RLANTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_0_RLANTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_PARITY_ERR 13:13 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_PARITY_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_REMAPTAB_ECC_LIMIT_ERR 14:14 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_0_REMAPTAB_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_REMAPTAB_ECC_LIMIT_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_REMAPTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_0_REMAPTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_RIDTAB_ECC_LIMIT_ERR 15:15 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_0_RIDTAB_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_RIDTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_0_RIDTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_RLANTAB_ECC_LIMIT_ERR 16:16 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_0_RLANTAB_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_RLANTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_0_RLANTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_ADDRTYPEERR 17:17 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_0_ADDRTYPEERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_ADDRTYPEERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_ADDRTYPEERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_0_ADDRTYPEERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTAREMAPTAB_INDEX_ERR 18:18 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTAREMAPTAB_INDEX_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTAREMAPTAB_INDEX_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTAREMAPTAB_INDEX_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTAREMAPTAB_INDEX_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTBREMAPTAB_INDEX_ERR 19:19 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTBREMAPTAB_INDEX_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTBREMAPTAB_INDEX_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTBREMAPTAB_INDEX_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTBREMAPTAB_INDEX_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_MCREMAPTAB_INDEX_ERR 20:20 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_0_MCREMAPTAB_INDEX_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_MCREMAPTAB_INDEX_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_MCREMAPTAB_INDEX_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_0_MCREMAPTAB_INDEX_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTBREMAPTAB_ECC_DBE_ERR 21:21 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTBREMAPTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTBREMAPTAB_ECC_DBE_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTBREMAPTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTBREMAPTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_MCREMAPTAB_ECC_DBE_ERR 22:22 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_0_MCREMAPTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_MCREMAPTAB_ECC_DBE_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_MCREMAPTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_0_MCREMAPTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTAREMAPTAB_REQCONTEXTMISMATCHERR 23:23 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTAREMAPTAB_REQCONTEXTMISMATCHERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTAREMAPTAB_REQCONTEXTMISMATCHERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTAREMAPTAB_REQCONTEXTMISMATCHERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTAREMAPTAB_REQCONTEXTMISMATCHERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTBREMAPTAB_REQCONTEXTMISMATCHERR 24:24 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTBREMAPTAB_REQCONTEXTMISMATCHERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTBREMAPTAB_REQCONTEXTMISMATCHERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTBREMAPTAB_REQCONTEXTMISMATCHERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTBREMAPTAB_REQCONTEXTMISMATCHERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_MCREMAPTAB_REQCONTEXTMISMATCHERR 25:25 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_0_MCREMAPTAB_REQCONTEXTMISMATCHERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_MCREMAPTAB_REQCONTEXTMISMATCHERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_MCREMAPTAB_REQCONTEXTMISMATCHERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_0_MCREMAPTAB_REQCONTEXTMISMATCHERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTAREMAPTAB_ACLFAIL 26:26 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTAREMAPTAB_ACLFAIL__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTAREMAPTAB_ACLFAIL__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTAREMAPTAB_ACLFAIL_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTAREMAPTAB_ACLFAIL_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTBREMAPTAB_ACLFAIL 27:27 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTBREMAPTAB_ACLFAIL__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTBREMAPTAB_ACLFAIL__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTBREMAPTAB_ACLFAIL_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTBREMAPTAB_ACLFAIL_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_MCREMAPTAB_ACLFAIL 28:28 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_0_MCREMAPTAB_ACLFAIL__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_MCREMAPTAB_ACLFAIL__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_MCREMAPTAB_ACLFAIL_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_0_MCREMAPTAB_ACLFAIL_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTAREMAPTAB_ADDRBOUNDSERR 29:29 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTAREMAPTAB_ADDRBOUNDSERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTAREMAPTAB_ADDRBOUNDSERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTAREMAPTAB_ADDRBOUNDSERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTAREMAPTAB_ADDRBOUNDSERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTBREMAPTAB_ADDRBOUNDSERR 30:30 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTBREMAPTAB_ADDRBOUNDSERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTBREMAPTAB_ADDRBOUNDSERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTBREMAPTAB_ADDRBOUNDSERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_0_EXTBREMAPTAB_ADDRBOUNDSERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_MCREMAPTAB_ADDRBOUNDSERR 31:31 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_0_MCREMAPTAB_ADDRBOUNDSERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_MCREMAPTAB_ADDRBOUNDSERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_0_MCREMAPTAB_ADDRBOUNDSERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_0_MCREMAPTAB_ADDRBOUNDSERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0 0x00001408 /* RW-4R */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_CMDDECODEERR 0:0 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_CMDDECODEERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_CMDDECODEERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_CMDDECODEERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTAREMAPTAB_ECC_DBE_ERR 1:1 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTAREMAPTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTAREMAPTAB_ECC_DBE_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTAREMAPTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTAREMAPTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REQCONTEXTMISMATCHERR 2:2 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REQCONTEXTMISMATCHERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REQCONTEXTMISMATCHERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_ACLFAIL 3:3 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_ACLFAIL_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_ACLFAIL_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_LIMIT_ERR 4:4 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR 5:5 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_INVALIDVCSET 6:6 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_INVALIDVCSET__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_INVALIDVCSET__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_INVALIDVCSET_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_INVALIDVCSET_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_ADDRBOUNDSERR 7:7 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_ADDRBOUNDSERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_ADDRBOUNDSERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTABCFGERR 8:8 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTABCFGERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTABCFGERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTABCFGERR 9:9 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTABCFGERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTABCFGERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REMAPTAB_ECC_DBE_ERR 10:10 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REMAPTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REMAPTAB_ECC_DBE_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REMAPTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REMAPTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTAB_ECC_DBE_ERR 11:11 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTAB_ECC_DBE_ERR 12:12 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR 13:13 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REMAPTAB_ECC_LIMIT_ERR 14:14 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REMAPTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REMAPTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTAB_ECC_LIMIT_ERR 15:15 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTAB_ECC_LIMIT_ERR 16:16 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_ADDRTYPEERR 17:17 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_ADDRTYPEERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_ADDRTYPEERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTAREMAPTAB_INDEX_ERR 18:18 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTAREMAPTAB_INDEX_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTAREMAPTAB_INDEX_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTBREMAPTAB_INDEX_ERR 19:19 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTBREMAPTAB_INDEX_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTBREMAPTAB_INDEX_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_MCREMAPTAB_INDEX_ERR 20:20 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_MCREMAPTAB_INDEX_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_MCREMAPTAB_INDEX_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTBREMAPTAB_ECC_DBE_ERR 21:21 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTBREMAPTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTBREMAPTAB_ECC_DBE_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTBREMAPTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTBREMAPTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_MCREMAPTAB_ECC_DBE_ERR 22:22 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_MCREMAPTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_MCREMAPTAB_ECC_DBE_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_MCREMAPTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_MCREMAPTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTAREMAPTAB_REQCONTEXTMISMATCHERR 23:23 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTAREMAPTAB_REQCONTEXTMISMATCHERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTAREMAPTAB_REQCONTEXTMISMATCHERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTBREMAPTAB_REQCONTEXTMISMATCHERR 24:24 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTBREMAPTAB_REQCONTEXTMISMATCHERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTBREMAPTAB_REQCONTEXTMISMATCHERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_MCREMAPTAB_REQCONTEXTMISMATCHERR 25:25 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_MCREMAPTAB_REQCONTEXTMISMATCHERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_MCREMAPTAB_REQCONTEXTMISMATCHERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTAREMAPTAB_ACLFAIL 26:26 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTAREMAPTAB_ACLFAIL_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTAREMAPTAB_ACLFAIL_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTBREMAPTAB_ACLFAIL 27:27 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTBREMAPTAB_ACLFAIL_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTBREMAPTAB_ACLFAIL_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_MCREMAPTAB_ACLFAIL 28:28 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_MCREMAPTAB_ACLFAIL_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_MCREMAPTAB_ACLFAIL_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTAREMAPTAB_ADDRBOUNDSERR 29:29 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTAREMAPTAB_ADDRBOUNDSERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTAREMAPTAB_ADDRBOUNDSERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTBREMAPTAB_ADDRBOUNDSERR 30:30 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTBREMAPTAB_ADDRBOUNDSERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_EXTBREMAPTAB_ADDRBOUNDSERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_MCREMAPTAB_ADDRBOUNDSERR 31:31 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_MCREMAPTAB_ADDRBOUNDSERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_MCREMAPTAB_ADDRBOUNDSERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0 0x0000140c /* RW-4R */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_CMDDECODEERR 0:0 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_CMDDECODEERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_CMDDECODEERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTAREMAPTAB_ECC_DBE_ERR 1:1 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTAREMAPTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTAREMAPTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REQCONTEXTMISMATCHERR 2:2 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REQCONTEXTMISMATCHERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REQCONTEXTMISMATCHERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REQCONTEXTMISMATCHERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REQCONTEXTMISMATCHERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ACLFAIL 3:3 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ACLFAIL__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ACLFAIL__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ACLFAIL_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ACLFAIL_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_LIMIT_ERR 4:4 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR 5:5 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_INVALIDVCSET 6:6 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_INVALIDVCSET_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_INVALIDVCSET_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ADDRBOUNDSERR 7:7 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ADDRBOUNDSERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ADDRBOUNDSERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ADDRBOUNDSERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ADDRBOUNDSERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTABCFGERR 8:8 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTABCFGERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTABCFGERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTABCFGERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTABCFGERR 9:9 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTABCFGERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTABCFGERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTABCFGERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REMAPTAB_ECC_DBE_ERR 10:10 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REMAPTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REMAPTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTAB_ECC_DBE_ERR 11:11 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTAB_ECC_DBE_ERR 12:12 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR 13:13 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REMAPTAB_ECC_LIMIT_ERR 14:14 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REMAPTAB_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REMAPTAB_ECC_LIMIT_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REMAPTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REMAPTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTAB_ECC_LIMIT_ERR 15:15 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTAB_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTAB_ECC_LIMIT_ERR 16:16 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTAB_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ADDRTYPEERR 17:17 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ADDRTYPEERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ADDRTYPEERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ADDRTYPEERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ADDRTYPEERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTAREMAPTAB_INDEX_ERR 18:18 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTAREMAPTAB_INDEX_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTAREMAPTAB_INDEX_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTAREMAPTAB_INDEX_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTAREMAPTAB_INDEX_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTBREMAPTAB_INDEX_ERR 19:19 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTBREMAPTAB_INDEX_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTBREMAPTAB_INDEX_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTBREMAPTAB_INDEX_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTBREMAPTAB_INDEX_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_MCREMAPTAB_INDEX_ERR 20:20 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_MCREMAPTAB_INDEX_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_MCREMAPTAB_INDEX_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_MCREMAPTAB_INDEX_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_MCREMAPTAB_INDEX_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTBREMAPTAB_ECC_DBE_ERR 21:21 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTBREMAPTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTBREMAPTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_MCREMAPTAB_ECC_DBE_ERR 22:22 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_MCREMAPTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_MCREMAPTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTAREMAPTAB_REQCONTEXTMISMATCHERR 23:23 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTAREMAPTAB_REQCONTEXTMISMATCHERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTAREMAPTAB_REQCONTEXTMISMATCHERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTAREMAPTAB_REQCONTEXTMISMATCHERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTAREMAPTAB_REQCONTEXTMISMATCHERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTBREMAPTAB_REQCONTEXTMISMATCHERR 24:24 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTBREMAPTAB_REQCONTEXTMISMATCHERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTBREMAPTAB_REQCONTEXTMISMATCHERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTBREMAPTAB_REQCONTEXTMISMATCHERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTBREMAPTAB_REQCONTEXTMISMATCHERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_MCREMAPTAB_REQCONTEXTMISMATCHERR 25:25 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_MCREMAPTAB_REQCONTEXTMISMATCHERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_MCREMAPTAB_REQCONTEXTMISMATCHERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_MCREMAPTAB_REQCONTEXTMISMATCHERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_MCREMAPTAB_REQCONTEXTMISMATCHERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTAREMAPTAB_ACLFAIL 26:26 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTAREMAPTAB_ACLFAIL__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTAREMAPTAB_ACLFAIL__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTAREMAPTAB_ACLFAIL_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTAREMAPTAB_ACLFAIL_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTBREMAPTAB_ACLFAIL 27:27 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTBREMAPTAB_ACLFAIL__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTBREMAPTAB_ACLFAIL__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTBREMAPTAB_ACLFAIL_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTBREMAPTAB_ACLFAIL_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_MCREMAPTAB_ACLFAIL 28:28 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_MCREMAPTAB_ACLFAIL__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_MCREMAPTAB_ACLFAIL__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_MCREMAPTAB_ACLFAIL_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_MCREMAPTAB_ACLFAIL_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTAREMAPTAB_ADDRBOUNDSERR 29:29 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTAREMAPTAB_ADDRBOUNDSERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTAREMAPTAB_ADDRBOUNDSERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTAREMAPTAB_ADDRBOUNDSERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTAREMAPTAB_ADDRBOUNDSERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTBREMAPTAB_ADDRBOUNDSERR 30:30 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTBREMAPTAB_ADDRBOUNDSERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTBREMAPTAB_ADDRBOUNDSERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTBREMAPTAB_ADDRBOUNDSERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_EXTBREMAPTAB_ADDRBOUNDSERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_MCREMAPTAB_ADDRBOUNDSERR 31:31 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_MCREMAPTAB_ADDRBOUNDSERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_MCREMAPTAB_ADDRBOUNDSERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_MCREMAPTAB_ADDRBOUNDSERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_MCREMAPTAB_ADDRBOUNDSERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0 0x00001410 /* RW-4R */ +#define NV_INGRESS_ERR_CONTAIN_EN_0 0x00001414 /* RW-4R */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_CMDDECODEERR 0:0 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_CMDDECODEERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_CMDDECODEERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_CMDDECODEERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTAREMAPTAB_ECC_DBE_ERR 1:1 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTAREMAPTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTAREMAPTAB_ECC_DBE_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTAREMAPTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTAREMAPTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_REQCONTEXTMISMATCHERR 2:2 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_REQCONTEXTMISMATCHERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_REQCONTEXTMISMATCHERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_ACLFAIL 3:3 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_ACLFAIL_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_ACLFAIL_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_HDR_ECC_LIMIT_ERR 4:4 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_HDR_ECC_DBE_ERR 5:5 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_HDR_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_INVALIDVCSET 6:6 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_INVALIDVCSET__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_INVALIDVCSET__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_INVALIDVCSET_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_INVALIDVCSET_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_ADDRBOUNDSERR 7:7 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_ADDRBOUNDSERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_ADDRBOUNDSERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTABCFGERR 8:8 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTABCFGERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTABCFGERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTABCFGERR 9:9 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTABCFGERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTABCFGERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_REMAPTAB_ECC_DBE_ERR 10:10 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_REMAPTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_REMAPTAB_ECC_DBE_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_REMAPTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_REMAPTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTAB_ECC_DBE_ERR 11:11 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTAB_ECC_DBE_ERR 12:12 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_PARITY_ERR 13:13 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_PARITY_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_REMAPTAB_ECC_LIMIT_ERR 14:14 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_REMAPTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_REMAPTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTAB_ECC_LIMIT_ERR 15:15 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTAB_ECC_LIMIT_ERR 16:16 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_ADDRTYPEERR 17:17 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_ADDRTYPEERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_ADDRTYPEERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTAREMAPTAB_INDEX_ERR 18:18 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTAREMAPTAB_INDEX_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTAREMAPTAB_INDEX_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTBREMAPTAB_INDEX_ERR 19:19 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTBREMAPTAB_INDEX_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTBREMAPTAB_INDEX_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_MCREMAPTAB_INDEX_ERR 20:20 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_MCREMAPTAB_INDEX_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_MCREMAPTAB_INDEX_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTBREMAPTAB_ECC_DBE_ERR 21:21 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTBREMAPTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTBREMAPTAB_ECC_DBE_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTBREMAPTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTBREMAPTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_MCREMAPTAB_ECC_DBE_ERR 22:22 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_MCREMAPTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_MCREMAPTAB_ECC_DBE_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_MCREMAPTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_MCREMAPTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTAREMAPTAB_REQCONTEXTMISMATCHERR 23:23 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTAREMAPTAB_REQCONTEXTMISMATCHERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTAREMAPTAB_REQCONTEXTMISMATCHERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTBREMAPTAB_REQCONTEXTMISMATCHERR 24:24 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTBREMAPTAB_REQCONTEXTMISMATCHERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTBREMAPTAB_REQCONTEXTMISMATCHERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_MCREMAPTAB_REQCONTEXTMISMATCHERR 25:25 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_MCREMAPTAB_REQCONTEXTMISMATCHERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_MCREMAPTAB_REQCONTEXTMISMATCHERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTAREMAPTAB_ACLFAIL 26:26 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTAREMAPTAB_ACLFAIL_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTAREMAPTAB_ACLFAIL_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTBREMAPTAB_ACLFAIL 27:27 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTBREMAPTAB_ACLFAIL_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTBREMAPTAB_ACLFAIL_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_MCREMAPTAB_ACLFAIL 28:28 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_MCREMAPTAB_ACLFAIL_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_MCREMAPTAB_ACLFAIL_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTAREMAPTAB_ADDRBOUNDSERR 29:29 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTAREMAPTAB_ADDRBOUNDSERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTAREMAPTAB_ADDRBOUNDSERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTBREMAPTAB_ADDRBOUNDSERR 30:30 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTBREMAPTAB_ADDRBOUNDSERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_EXTBREMAPTAB_ADDRBOUNDSERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_MCREMAPTAB_ADDRBOUNDSERR 31:31 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_MCREMAPTAB_ADDRBOUNDSERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_0_MCREMAPTAB_ADDRBOUNDSERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_0 0x0000141c /* RW-4R */ +#define NV_INGRESS_ERR_FIRST_0_CMDDECODEERR 0:0 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_0_CMDDECODEERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_0_CMDDECODEERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_0_CMDDECODEERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_0_EXTAREMAPTAB_ECC_DBE_ERR 1:1 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_0_EXTAREMAPTAB_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_0_EXTAREMAPTAB_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_0_EXTAREMAPTAB_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_0_REQCONTEXTMISMATCHERR 2:2 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_0_REQCONTEXTMISMATCHERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_0_REQCONTEXTMISMATCHERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_0_REQCONTEXTMISMATCHERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_0_ACLFAIL 3:3 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_0_ACLFAIL__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_0_ACLFAIL_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_0_ACLFAIL_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_0_NCISOC_HDR_ECC_LIMIT_ERR 4:4 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_0_NCISOC_HDR_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_0_NCISOC_HDR_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_0_NCISOC_HDR_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_0_NCISOC_HDR_ECC_DBE_ERR 5:5 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_0_NCISOC_HDR_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_0_NCISOC_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_0_NCISOC_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_0_INVALIDVCSET 6:6 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_0_INVALIDVCSET__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_0_INVALIDVCSET_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_0_INVALIDVCSET_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_0_ADDRBOUNDSERR 7:7 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_0_ADDRBOUNDSERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_0_ADDRBOUNDSERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_0_ADDRBOUNDSERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_0_RIDTABCFGERR 8:8 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_0_RIDTABCFGERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_0_RIDTABCFGERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_0_RIDTABCFGERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_0_RLANTABCFGERR 9:9 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_0_RLANTABCFGERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_0_RLANTABCFGERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_0_RLANTABCFGERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_0_REMAPTAB_ECC_DBE_ERR 10:10 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_0_REMAPTAB_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_0_REMAPTAB_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_0_REMAPTAB_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_0_RIDTAB_ECC_DBE_ERR 11:11 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_0_RIDTAB_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_0_RIDTAB_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_0_RIDTAB_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_0_RLANTAB_ECC_DBE_ERR 12:12 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_0_RLANTAB_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_0_RLANTAB_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_0_RLANTAB_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_0_NCISOC_PARITY_ERR 13:13 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_0_NCISOC_PARITY_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_0_NCISOC_PARITY_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_0_NCISOC_PARITY_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_0_REMAPTAB_ECC_LIMIT_ERR 14:14 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_0_REMAPTAB_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_0_REMAPTAB_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_0_REMAPTAB_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_0_RIDTAB_ECC_LIMIT_ERR 15:15 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_0_RIDTAB_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_0_RIDTAB_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_0_RIDTAB_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_0_RLANTAB_ECC_LIMIT_ERR 16:16 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_0_RLANTAB_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_0_RLANTAB_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_0_RLANTAB_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_0_ADDRTYPEERR 17:17 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_0_ADDRTYPEERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_0_ADDRTYPEERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_0_ADDRTYPEERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_0_EXTAREMAPTAB_INDEX_ERR 18:18 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_0_EXTAREMAPTAB_INDEX_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_0_EXTAREMAPTAB_INDEX_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_0_EXTAREMAPTAB_INDEX_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_0_EXTBREMAPTAB_INDEX_ERR 19:19 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_0_EXTBREMAPTAB_INDEX_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_0_EXTBREMAPTAB_INDEX_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_0_EXTBREMAPTAB_INDEX_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_0_MCREMAPTAB_INDEX_ERR 20:20 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_0_MCREMAPTAB_INDEX_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_0_MCREMAPTAB_INDEX_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_0_MCREMAPTAB_INDEX_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_0_EXTBREMAPTAB_ECC_DBE_ERR 21:21 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_0_EXTBREMAPTAB_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_0_EXTBREMAPTAB_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_0_EXTBREMAPTAB_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_0_MCREMAPTAB_ECC_DBE_ERR 22:22 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_0_MCREMAPTAB_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_0_MCREMAPTAB_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_0_MCREMAPTAB_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_0_EXTAREMAPTAB_REQCONTEXTMISMATCHERR 23:23 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_0_EXTAREMAPTAB_REQCONTEXTMISMATCHERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_0_EXTAREMAPTAB_REQCONTEXTMISMATCHERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_0_EXTAREMAPTAB_REQCONTEXTMISMATCHERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_0_EXTBREMAPTAB_REQCONTEXTMISMATCHERR 24:24 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_0_EXTBREMAPTAB_REQCONTEXTMISMATCHERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_0_EXTBREMAPTAB_REQCONTEXTMISMATCHERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_0_EXTBREMAPTAB_REQCONTEXTMISMATCHERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_0_MCREMAPTAB_REQCONTEXTMISMATCHERR 25:25 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_0_MCREMAPTAB_REQCONTEXTMISMATCHERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_0_MCREMAPTAB_REQCONTEXTMISMATCHERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_0_MCREMAPTAB_REQCONTEXTMISMATCHERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_0_EXTAREMAPTAB_ACLFAIL 26:26 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_0_EXTAREMAPTAB_ACLFAIL__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_0_EXTAREMAPTAB_ACLFAIL_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_0_EXTAREMAPTAB_ACLFAIL_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_0_EXTBREMAPTAB_ACLFAIL 27:27 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_0_EXTBREMAPTAB_ACLFAIL__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_0_EXTBREMAPTAB_ACLFAIL_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_0_EXTBREMAPTAB_ACLFAIL_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_0_MCREMAPTAB_ACLFAIL 28:28 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_0_MCREMAPTAB_ACLFAIL__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_0_MCREMAPTAB_ACLFAIL_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_0_MCREMAPTAB_ACLFAIL_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_0_EXTAREMAPTAB_ADDRBOUNDSERR 29:29 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_0_EXTAREMAPTAB_ADDRBOUNDSERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_0_EXTAREMAPTAB_ADDRBOUNDSERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_0_EXTAREMAPTAB_ADDRBOUNDSERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_0_EXTBREMAPTAB_ADDRBOUNDSERR 30:30 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_0_EXTBREMAPTAB_ADDRBOUNDSERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_0_EXTBREMAPTAB_ADDRBOUNDSERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_0_EXTBREMAPTAB_ADDRBOUNDSERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_0_MCREMAPTAB_ADDRBOUNDSERR 31:31 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_0_MCREMAPTAB_ADDRBOUNDSERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_0_MCREMAPTAB_ADDRBOUNDSERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_0_MCREMAPTAB_ADDRBOUNDSERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_HEADER_LOG_4 0x00001430 /* R--4R */ +#define NV_INGRESS_ERR_HEADER_LOG_4_DW 31:0 /* R-DVF */ +#define NV_INGRESS_ERR_HEADER_LOG_4_DW_INIT 0x00000000 /* R-D-V */ +#define NV_INGRESS_ERR_HEADER_LOG_5 0x00001434 /* R--4R */ +#define NV_INGRESS_ERR_HEADER_LOG_5_DW 31:0 /* R-DVF */ +#define NV_INGRESS_ERR_HEADER_LOG_5_DW_INIT 0x00000000 /* R-D-V */ +#define NV_INGRESS_ERR_HEADER_LOG_6 0x00001438 /* R--4R */ +#define NV_INGRESS_ERR_HEADER_LOG_6_DW 31:0 /* R-DVF */ +#define NV_INGRESS_ERR_HEADER_LOG_6_DW_INIT 0x00000000 /* R-D-V */ +#define NV_INGRESS_ERR_HEADER_LOG_7 0x0000143c /* R--4R */ +#define NV_INGRESS_ERR_HEADER_LOG_7_DW 31:0 /* R-DVF */ +#define NV_INGRESS_ERR_HEADER_LOG_7_DW_INIT 0x00000000 /* R-D-V */ +#define NV_INGRESS_ERR_HEADER_LOG_8 0x00001440 /* R--4R */ +#define NV_INGRESS_ERR_HEADER_LOG_8_DW 31:0 /* R-DVF */ +#define NV_INGRESS_ERR_HEADER_LOG_8_DW_INIT 0x00000000 /* R-D-V */ +#define NV_INGRESS_ERR_HEADER_LOG_9 0x00001444 /* R--4R */ +#define NV_INGRESS_ERR_HEADER_LOG_9_DW 31:0 /* R-DVF */ +#define NV_INGRESS_ERR_HEADER_LOG_9_DW_INIT 0x00000000 /* R-D-V */ +#define NV_INGRESS_ERR_HEADER_LOG_VALID 0x00001448 /* R--4R */ +#define NV_INGRESS_ERR_HEADER_LOG_VALID_HEADERVALID0 0:0 /* R-DVF */ +#define NV_INGRESS_ERR_HEADER_LOG_VALID_HEADERVALID0_INVALID 0x00000000 /* R-D-V */ +#define NV_INGRESS_ERR_HEADER_LOG_VALID_HEADERVALID0_VALID 0x00000001 /* R---V */ +#define NV_INGRESS_ERR_TIMESTAMP_LOG 0x0000144c /* R--4R */ +#define NV_INGRESS_ERR_TIMESTAMP_LOG_TIMESTAMP 23:0 /* R-DVF */ +#define NV_INGRESS_ERR_TIMESTAMP_LOG_TIMESTAMP_INIT 0x00000000 /* R-D-V */ +#define NV_INGRESS_ERR_MISC_LOG_0 0x00001450 /* R--4R */ +#define NV_INGRESS_ERR_MISC_LOG_0_SPORT 5:0 /* R-DVF */ +#define NV_INGRESS_ERR_MISC_LOG_0_SPORT_INIT 0x00000000 /* R-D-V */ +#define NV_INGRESS_ERR_MISC_LOG_0_ENCODEDVC 10:8 /* R-DVF */ +#define NV_INGRESS_ERR_MISC_LOG_0_ENCODEDVC_CREQ0 0x00000000 /* R-D-V */ +#define NV_INGRESS_ERR_MISC_LOG_0_ENCODEDVC_RSP0 0x00000005 /* R---V */ +#define NV_INGRESS_ERR_MISC_LOG_0_ENCODEDVC_CREQ1 0x00000006 /* R---V */ +#define NV_INGRESS_ERR_MISC_LOG_0_ENCODEDVC_RSP1 0x00000007 /* R---V */ +#define NV_INGRESS_ERR_ECC_CTRL 0x00001470 /* RW-4R */ +#define NV_INGRESS_ERR_ECC_CTRL_NCISOC_HDR_ECC_ENABLE 0:0 /* RWEVF */ +#define NV_INGRESS_ERR_ECC_CTRL_NCISOC_HDR_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_ECC_CTRL_NCISOC_HDR_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_ECC_CTRL_NCISOC_HDR_ECC_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_ECC_CTRL_NCISOC_PARITY_ENABLE 1:1 /* RWEVF */ +#define NV_INGRESS_ERR_ECC_CTRL_NCISOC_PARITY_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_ECC_CTRL_NCISOC_PARITY_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_ECC_CTRL_NCISOC_PARITY_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_ECC_CTRL_MCREMAPTAB_ECC_ENABLE 5:5 /* RWEVF */ +#define NV_INGRESS_ERR_ECC_CTRL_MCREMAPTAB_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_ECC_CTRL_MCREMAPTAB_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_ECC_CTRL_MCREMAPTAB_ECC_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_ECC_CTRL_EXTAREMAPTAB_ECC_ENABLE 6:6 /* RWEVF */ +#define NV_INGRESS_ERR_ECC_CTRL_EXTAREMAPTAB_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_ECC_CTRL_EXTAREMAPTAB_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_ECC_CTRL_EXTAREMAPTAB_ECC_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_ECC_CTRL_EXTBREMAPTAB_ECC_ENABLE 7:7 /* RWEVF */ +#define NV_INGRESS_ERR_ECC_CTRL_EXTBREMAPTAB_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_ECC_CTRL_EXTBREMAPTAB_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_ECC_CTRL_EXTBREMAPTAB_ECC_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_ECC_CTRL_REMAPTAB_ECC_ENABLE 8:8 /* RWEVF */ +#define NV_INGRESS_ERR_ECC_CTRL_REMAPTAB_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_ECC_CTRL_REMAPTAB_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_ECC_CTRL_REMAPTAB_ECC_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_ECC_CTRL_RIDTAB_ECC_ENABLE 9:9 /* RWEVF */ +#define NV_INGRESS_ERR_ECC_CTRL_RIDTAB_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_ECC_CTRL_RIDTAB_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_ECC_CTRL_RIDTAB_ECC_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_ECC_CTRL_RLANTAB_ECC_ENABLE 10:10 /* RWEVF */ +#define NV_INGRESS_ERR_ECC_CTRL_RLANTAB_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_ECC_CTRL_RLANTAB_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_ECC_CTRL_RLANTAB_ECC_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_COUNTER 0x00001480 /* RW-4R */ +#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */ +#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_COUNTER_LIMIT 0x00001484 /* RW-4R */ +#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */ +#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */ +#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_ADDRESS 0x00001488 /* R--4R */ +#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_ADDRESS_ERROR_ADDRESS 15:0 /* R-DVF */ +#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */ +#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_ADDRESS_VALID 0x0000148c /* R--4R */ +#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */ +#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */ +#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */ +#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_COUNTER 0x00001490 /* RW-4R */ +#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */ +#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_COUNTER_LIMIT 0x00001494 /* RW-4R */ +#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */ +#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */ +#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_ADDRESS 0x00001498 /* R--4R */ +#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_ADDRESS_ERROR_ADDRESS 15:0 /* R-DVF */ +#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */ +#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_ADDRESS_VALID 0x0000149c /* R--4R */ +#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */ +#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */ +#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */ +#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_COUNTER 0x000014a0 /* RW-4R */ +#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */ +#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_COUNTER_LIMIT 0x000014a4 /* RW-4R */ +#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */ +#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */ +#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_ADDRESS 0x000014a8 /* R--4R */ +#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_ADDRESS_ERROR_ADDRESS 15:0 /* R-DVF */ +#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */ +#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_ADDRESS_VALID 0x000014ac /* R--4R */ +#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */ +#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */ +#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */ +#define NV_INGRESS_ERR_NCISOC_HDR_ECC_ERROR_COUNTER 0x000014b0 /* RW-4R */ +#define NV_INGRESS_ERR_NCISOC_HDR_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */ +#define NV_INGRESS_ERR_NCISOC_HDR_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_NCISOC_HDR_ECC_ERROR_COUNTER_LIMIT 0x000014b4 /* RW-4R */ +#define NV_INGRESS_ERR_NCISOC_HDR_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */ +#define NV_INGRESS_ERR_NCISOC_HDR_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */ +#define NV_INGRESS_ERR_EXTAREMAPTAB_ECC_ERROR_COUNTER 0x000014b8 /* RW-4R */ +#define NV_INGRESS_ERR_EXTAREMAPTAB_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */ +#define NV_INGRESS_ERR_EXTAREMAPTAB_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_EXTAREMAPTAB_ECC_ERROR_COUNTER_LIMIT 0x000014bc /* RW-4R */ +#define NV_INGRESS_ERR_EXTAREMAPTAB_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */ +#define NV_INGRESS_ERR_EXTAREMAPTAB_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */ +#define NV_INGRESS_ERR_EXTAREMAPTAB_ECC_ERROR_ADDRESS 0x000014c0 /* R--4R */ +#define NV_INGRESS_ERR_EXTAREMAPTAB_ECC_ERROR_ADDRESS_ERROR_ADDRESS 15:0 /* R-DVF */ +#define NV_INGRESS_ERR_EXTAREMAPTAB_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */ +#define NV_INGRESS_ERR_EXTAREMAPTAB_ECC_ERROR_ADDRESS_VALID 0x000014c4 /* R--4R */ +#define NV_INGRESS_ERR_EXTAREMAPTAB_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */ +#define NV_INGRESS_ERR_EXTAREMAPTAB_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */ +#define NV_INGRESS_ERR_EXTAREMAPTAB_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */ +#define NV_INGRESS_ERR_EXTBREMAPTAB_ECC_ERROR_COUNTER 0x000014c8 /* RW-4R */ +#define NV_INGRESS_ERR_EXTBREMAPTAB_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */ +#define NV_INGRESS_ERR_EXTBREMAPTAB_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_EXTBREMAPTAB_ECC_ERROR_COUNTER_LIMIT 0x000014cc /* RW-4R */ +#define NV_INGRESS_ERR_EXTBREMAPTAB_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */ +#define NV_INGRESS_ERR_EXTBREMAPTAB_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */ +#define NV_INGRESS_ERR_EXTBREMAPTAB_ECC_ERROR_ADDRESS 0x000014d0 /* R--4R */ +#define NV_INGRESS_ERR_EXTBREMAPTAB_ECC_ERROR_ADDRESS_ERROR_ADDRESS 15:0 /* R-DVF */ +#define NV_INGRESS_ERR_EXTBREMAPTAB_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */ +#define NV_INGRESS_ERR_EXTBREMAPTAB_ECC_ERROR_ADDRESS_VALID 0x000014d4 /* R--4R */ +#define NV_INGRESS_ERR_EXTBREMAPTAB_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */ +#define NV_INGRESS_ERR_EXTBREMAPTAB_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */ +#define NV_INGRESS_ERR_EXTBREMAPTAB_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */ +#define NV_INGRESS_ERR_MCREMAPTAB_ECC_ERROR_COUNTER 0x000014d8 /* RW-4R */ +#define NV_INGRESS_ERR_MCREMAPTAB_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */ +#define NV_INGRESS_ERR_MCREMAPTAB_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_MCREMAPTAB_ECC_ERROR_COUNTER_LIMIT 0x000014dc /* RW-4R */ +#define NV_INGRESS_ERR_MCREMAPTAB_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */ +#define NV_INGRESS_ERR_MCREMAPTAB_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */ +#define NV_INGRESS_ERR_MCREMAPTAB_ECC_ERROR_ADDRESS 0x000014e0 /* R--4R */ +#define NV_INGRESS_ERR_MCREMAPTAB_ECC_ERROR_ADDRESS_ERROR_ADDRESS 15:0 /* R-DVF */ +#define NV_INGRESS_ERR_MCREMAPTAB_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */ +#define NV_INGRESS_ERR_MCREMAPTAB_ECC_ERROR_ADDRESS_VALID 0x000014e4 /* R--4R */ +#define NV_INGRESS_ERR_MCREMAPTAB_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */ +#define NV_INGRESS_ERR_MCREMAPTAB_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */ +#define NV_INGRESS_ERR_MCREMAPTAB_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */ +#define NV_INGRESS_ERR_STATUS_1 0x00001700 /* RW-4R */ +#define NV_INGRESS_ERR_STATUS_1_EXTAREMAPTAB_ECC_LIMIT_ERR 0:0 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_1_EXTAREMAPTAB_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_1_EXTAREMAPTAB_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_1_EXTAREMAPTAB_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_1_EXTBREMAPTAB_ECC_LIMIT_ERR 1:1 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_1_EXTBREMAPTAB_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_1_EXTBREMAPTAB_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_1_EXTBREMAPTAB_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_1_MCREMAPTAB_ECC_LIMIT_ERR 2:2 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_1_MCREMAPTAB_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_1_MCREMAPTAB_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_1_MCREMAPTAB_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_1_MCCMDTOUCADDRERR 3:3 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_1_MCCMDTOUCADDRERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_1_MCCMDTOUCADDRERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_1_MCCMDTOUCADDRERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_1_READMCREFLECTMEMERR 4:4 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_1_READMCREFLECTMEMERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_1_READMCREFLECTMEMERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_1_READMCREFLECTMEMERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_1_EXTAREMAPTAB_ADDRTYPEERR 5:5 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_1_EXTAREMAPTAB_ADDRTYPEERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_1_EXTAREMAPTAB_ADDRTYPEERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_1_EXTAREMAPTAB_ADDRTYPEERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_1_EXTBREMAPTAB_ADDRTYPEERR 6:6 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_1_EXTBREMAPTAB_ADDRTYPEERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_1_EXTBREMAPTAB_ADDRTYPEERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_1_EXTBREMAPTAB_ADDRTYPEERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_STATUS_1_MCREMAPTAB_ADDRTYPEERR 7:7 /* RWDVF */ +#define NV_INGRESS_ERR_STATUS_1_MCREMAPTAB_ADDRTYPEERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_STATUS_1_MCREMAPTAB_ADDRTYPEERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_STATUS_1_MCREMAPTAB_ADDRTYPEERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_1 0x00001704 /* RW-4R */ +#define NV_INGRESS_ERR_LOG_EN_1_EXTAREMAPTAB_ECC_LIMIT_ERR 0:0 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_1_EXTAREMAPTAB_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_1_EXTAREMAPTAB_ECC_LIMIT_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_1_EXTAREMAPTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_1_EXTAREMAPTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_1_EXTBREMAPTAB_ECC_LIMIT_ERR 1:1 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_1_EXTBREMAPTAB_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_1_EXTBREMAPTAB_ECC_LIMIT_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_1_EXTBREMAPTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_1_EXTBREMAPTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_1_MCREMAPTAB_ECC_LIMIT_ERR 2:2 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_1_MCREMAPTAB_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_1_MCREMAPTAB_ECC_LIMIT_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_1_MCREMAPTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_1_MCREMAPTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_1_MCCMDTOUCADDRERR 3:3 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_1_MCCMDTOUCADDRERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_1_MCCMDTOUCADDRERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_1_MCCMDTOUCADDRERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_1_MCCMDTOUCADDRERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_1_READMCREFLECTMEMERR 4:4 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_1_READMCREFLECTMEMERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_1_READMCREFLECTMEMERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_1_READMCREFLECTMEMERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_1_READMCREFLECTMEMERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_1_EXTAREMAPTAB_ADDRTYPEERR 5:5 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_1_EXTAREMAPTAB_ADDRTYPEERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_1_EXTAREMAPTAB_ADDRTYPEERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_1_EXTAREMAPTAB_ADDRTYPEERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_1_EXTAREMAPTAB_ADDRTYPEERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_1_EXTBREMAPTAB_ADDRTYPEERR 6:6 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_1_EXTBREMAPTAB_ADDRTYPEERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_1_EXTBREMAPTAB_ADDRTYPEERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_1_EXTBREMAPTAB_ADDRTYPEERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_1_EXTBREMAPTAB_ADDRTYPEERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_1_MCREMAPTAB_ADDRTYPEERR 7:7 /* RWEVF */ +#define NV_INGRESS_ERR_LOG_EN_1_MCREMAPTAB_ADDRTYPEERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_1_MCREMAPTAB_ADDRTYPEERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_LOG_EN_1_MCREMAPTAB_ADDRTYPEERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_LOG_EN_1_MCREMAPTAB_ADDRTYPEERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_1 0x00001708 /* RW-4R */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_1_EXTAREMAPTAB_ECC_LIMIT_ERR 0:0 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_1_EXTAREMAPTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_1_EXTAREMAPTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_1_EXTBREMAPTAB_ECC_LIMIT_ERR 1:1 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_1_EXTBREMAPTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_1_EXTBREMAPTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_1_MCREMAPTAB_ECC_LIMIT_ERR 2:2 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_1_MCREMAPTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_1_MCREMAPTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_1_MCCMDTOUCADDRERR 3:3 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_1_MCCMDTOUCADDRERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_1_MCCMDTOUCADDRERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_1_READMCREFLECTMEMERR 4:4 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_1_READMCREFLECTMEMERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_1_READMCREFLECTMEMERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_1_EXTAREMAPTAB_ADDRTYPEERR 5:5 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_1_EXTAREMAPTAB_ADDRTYPEERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_1_EXTAREMAPTAB_ADDRTYPEERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_1_EXTBREMAPTAB_ADDRTYPEERR 6:6 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_1_EXTBREMAPTAB_ADDRTYPEERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_1_EXTBREMAPTAB_ADDRTYPEERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_1_MCREMAPTAB_ADDRTYPEERR 7:7 /* RWEVF */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_1_MCREMAPTAB_ADDRTYPEERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_FATAL_REPORT_EN_1_MCREMAPTAB_ADDRTYPEERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1 0x0000170c /* RW-4R */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_EXTAREMAPTAB_ECC_LIMIT_ERR 0:0 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_EXTAREMAPTAB_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_EXTAREMAPTAB_ECC_LIMIT_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_EXTAREMAPTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_EXTAREMAPTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_EXTBREMAPTAB_ECC_LIMIT_ERR 1:1 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_EXTBREMAPTAB_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_EXTBREMAPTAB_ECC_LIMIT_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_EXTBREMAPTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_EXTBREMAPTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_MCREMAPTAB_ECC_LIMIT_ERR 2:2 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_MCREMAPTAB_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_MCREMAPTAB_ECC_LIMIT_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_MCREMAPTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_MCREMAPTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_MCCMDTOUCADDRERR 3:3 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_MCCMDTOUCADDRERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_MCCMDTOUCADDRERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_MCCMDTOUCADDRERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_MCCMDTOUCADDRERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_READMCREFLECTMEMERR 4:4 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_READMCREFLECTMEMERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_READMCREFLECTMEMERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_READMCREFLECTMEMERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_READMCREFLECTMEMERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_EXTAREMAPTAB_ADDRTYPEERR 5:5 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_EXTAREMAPTAB_ADDRTYPEERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_EXTAREMAPTAB_ADDRTYPEERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_EXTAREMAPTAB_ADDRTYPEERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_EXTAREMAPTAB_ADDRTYPEERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_EXTBREMAPTAB_ADDRTYPEERR 6:6 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_EXTBREMAPTAB_ADDRTYPEERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_EXTBREMAPTAB_ADDRTYPEERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_EXTBREMAPTAB_ADDRTYPEERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_EXTBREMAPTAB_ADDRTYPEERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_MCREMAPTAB_ADDRTYPEERR 7:7 /* RWEVF */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_MCREMAPTAB_ADDRTYPEERR__PROD 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_MCREMAPTAB_ADDRTYPEERR__TPROD 0x00000000 /* RW--V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_MCREMAPTAB_ADDRTYPEERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_1_MCREMAPTAB_ADDRTYPEERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_1 0x00001710 /* RW-4R */ +#define NV_INGRESS_ERR_CONTAIN_EN_1 0x00001714 /* RW-4R */ +#define NV_INGRESS_ERR_CONTAIN_EN_1_EXTAREMAPTAB_ECC_LIMIT_ERR 0:0 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_1_EXTAREMAPTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_1_EXTAREMAPTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_1_EXTBREMAPTAB_ECC_LIMIT_ERR 1:1 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_1_EXTBREMAPTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_1_EXTBREMAPTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_1_MCREMAPTAB_ECC_LIMIT_ERR 2:2 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_1_MCREMAPTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_1_MCREMAPTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_1_MCCMDTOUCADDRERR 3:3 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_1_MCCMDTOUCADDRERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_1_MCCMDTOUCADDRERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_1_READMCREFLECTMEMERR 4:4 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_1_READMCREFLECTMEMERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_1_READMCREFLECTMEMERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_1_EXTAREMAPTAB_ADDRTYPEERR 5:5 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_1_EXTAREMAPTAB_ADDRTYPEERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_1_EXTAREMAPTAB_ADDRTYPEERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_1_EXTBREMAPTAB_ADDRTYPEERR 6:6 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_1_EXTBREMAPTAB_ADDRTYPEERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_1_EXTBREMAPTAB_ADDRTYPEERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_CONTAIN_EN_1_MCREMAPTAB_ADDRTYPEERR 7:7 /* RWEVF */ +#define NV_INGRESS_ERR_CONTAIN_EN_1_MCREMAPTAB_ADDRTYPEERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_INGRESS_ERR_CONTAIN_EN_1_MCREMAPTAB_ADDRTYPEERR_ENABLE 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_1 0x0000171c /* RW-4R */ +#define NV_INGRESS_ERR_FIRST_1_EXTAREMAPTAB_ECC_LIMIT_ERR 0:0 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_1_EXTAREMAPTAB_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_1_EXTAREMAPTAB_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_1_EXTAREMAPTAB_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_1_EXTBREMAPTAB_ECC_LIMIT_ERR 1:1 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_1_EXTBREMAPTAB_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_1_EXTBREMAPTAB_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_1_EXTBREMAPTAB_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_1_MCREMAPTAB_ECC_LIMIT_ERR 2:2 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_1_MCREMAPTAB_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_1_MCREMAPTAB_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_1_MCREMAPTAB_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_1_MCCMDTOUCADDRERR 3:3 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_1_MCCMDTOUCADDRERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_1_MCCMDTOUCADDRERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_1_MCCMDTOUCADDRERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_1_READMCREFLECTMEMERR 4:4 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_1_READMCREFLECTMEMERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_1_READMCREFLECTMEMERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_1_READMCREFLECTMEMERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_1_EXTAREMAPTAB_ADDRTYPEERR 5:5 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_1_EXTAREMAPTAB_ADDRTYPEERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_1_EXTAREMAPTAB_ADDRTYPEERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_1_EXTAREMAPTAB_ADDRTYPEERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_1_EXTBREMAPTAB_ADDRTYPEERR 6:6 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_1_EXTBREMAPTAB_ADDRTYPEERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_1_EXTBREMAPTAB_ADDRTYPEERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_1_EXTBREMAPTAB_ADDRTYPEERR_CLEAR 0x00000001 /* RW--V */ +#define NV_INGRESS_ERR_FIRST_1_MCREMAPTAB_ADDRTYPEERR 7:7 /* RWDVF */ +#define NV_INGRESS_ERR_FIRST_1_MCREMAPTAB_ADDRTYPEERR__ONWRITE "oneToClear" /* */ +#define NV_INGRESS_ERR_FIRST_1_MCREMAPTAB_ADDRTYPEERR_NONE 0x00000000 /* RWD-V */ +#define NV_INGRESS_ERR_FIRST_1_MCREMAPTAB_ADDRTYPEERR_CLEAR 0x00000001 /* RW--V */ +#endif // __ls10_dev_ingress_ip_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_master.h b/src/common/inc/swref/published/nvswitch/ls10/dev_master.h new file mode 100644 index 000000000..113b1588f --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_master.h @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_master_h__ +#define __ls10_dev_master_h__ +/* This file is autogenerated. Do not edit */ +#define NV_PMC 0x00000fff:0x00000000 /* RW--D */ +#define NV_PMC_BOOT_42 0x00000A00 /* R--4R */ +#define NV_PMC_BOOT_42_CHIP_ID 28:20 /* R-XVF */ +#define NV_PMC_BOOT_42_CHIP_ID_SVNP01 0x00000005 /* R---V */ +#define NV_PMC_BOOT_42_CHIP_ID_LR10 0x00000006 /* R---V */ +#define NV_PMC_BOOT_42_CHIP_ID_LS10 0x00000007 /* R---V */ +#endif // __ls10_dev_master_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_minion_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_minion_ip.h new file mode 100644 index 000000000..a72b553fd --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_minion_ip.h @@ -0,0 +1,500 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_minion_ip_h__ +#define __ls10_dev_minion_ip_h__ +/* This file is autogenerated. Do not edit */ +#define NV_CMINION_FALCON 0x000006ff:0x00000000 /* RW--D */ +#define NV_CMINION_RISCV 0x00000fff:0x00000700 /* RW--D */ +#define NV_MINION 0x00003FFF:0x00002000 /* RW--D */ +#define NV_CMINION_FALCON_IRQSCLR 0x00000004 /* -W-4R */ +#define NV_CMINION_FALCON_IRQSCLR_GPTMR 0:0 /* -WXVF */ +#define NV_CMINION_FALCON_IRQSCLR_GPTMR_SET 0x00000001 /* -W--V */ +#define NV_CMINION_FALCON_IRQSCLR_WDTMR 1:1 /* -WXVF */ +#define NV_CMINION_FALCON_IRQSCLR_WDTMR_SET 0x00000001 /* -W--V */ +#define NV_CMINION_FALCON_IRQSCLR_MTHD 2:2 /* -WXVF */ +#define NV_CMINION_FALCON_IRQSCLR_MTHD_SET 0x00000001 /* -W--V */ +#define NV_CMINION_FALCON_IRQSCLR_CTXSW 3:3 /* -WXVF */ +#define NV_CMINION_FALCON_IRQSCLR_CTXSW_SET 0x00000001 /* -W--V */ +#define NV_CMINION_FALCON_IRQSCLR_HALT 4:4 /* -WXVF */ +#define NV_CMINION_FALCON_IRQSCLR_HALT_SET 0x00000001 /* -W--V */ +#define NV_CMINION_FALCON_IRQSCLR_EXTERR 5:5 /* -WXVF */ +#define NV_CMINION_FALCON_IRQSCLR_EXTERR_SET 0x00000001 /* -W--V */ +#define NV_CMINION_FALCON_IRQSCLR_SWGEN0 6:6 /* -WXVF */ +#define NV_CMINION_FALCON_IRQSCLR_SWGEN0_SET 0x00000001 /* -W--V */ +#define NV_CMINION_FALCON_IRQSCLR_SWGEN1 7:7 /* -WXVF */ +#define NV_CMINION_FALCON_IRQSCLR_SWGEN1_SET 0x00000001 /* -W--V */ +#define NV_CMINION_FALCON_IRQSCLR_EXT 15:8 /* */ +#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ1 8:8 /* -WXVF */ +#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ1_SET 0x00000001 /* -W--V */ +#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ2 9:9 /* -WXVF */ +#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ2_SET 0x00000001 /* -W--V */ +#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ3 10:10 /* -WXVF */ +#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ3_SET 0x00000001 /* -W--V */ +#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ4 11:11 /* -WXVF */ +#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ4_SET 0x00000001 /* -W--V */ +#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ5 12:12 /* -WXVF */ +#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ5_SET 0x00000001 /* -W--V */ +#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ6 13:13 /* -WXVF */ +#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ6_SET 0x00000001 /* -W--V */ +#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ7 14:14 /* -WXVF */ +#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ7_SET 0x00000001 /* -W--V */ +#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ8 15:15 /* -WXVF */ +#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ8_SET 0x00000001 /* -W--V */ +#define NV_CMINION_FALCON_IRQSCLR_DMA 16:16 /* -WXVF */ +#define NV_CMINION_FALCON_IRQSCLR_DMA_SET 0x00000001 /* -W--V */ +#define NV_CMINION_FALCON_IRQSCLR_SHA 17:17 /* -WXVF */ +#define NV_CMINION_FALCON_IRQSCLR_SHA_SET 0x00000001 /* -W--V */ +#define NV_CMINION_FALCON_IRQSCLR_MEMERR 18:18 /* -WXVF */ +#define NV_CMINION_FALCON_IRQSCLR_MEMERR_SET 0x00000001 /* -W--V */ +#define NV_CMINION_FALCON_IRQSCLR_CTXSW_ERROR 19:19 /* -WXVF */ +#define NV_CMINION_FALCON_IRQSCLR_CTXSW_ERROR_SET 0x00000001 /* -W--V */ +#define NV_CMINION_FALCON_IRQSCLR_ICD 22:22 /* -WXVF */ +#define NV_CMINION_FALCON_IRQSCLR_ICD_SET 0x00000001 /* -W--V */ +#define NV_CMINION_FALCON_IRQSCLR_IOPMP 23:23 /* -WXVF */ +#define NV_CMINION_FALCON_IRQSCLR_IOPMP_SET 0x00000001 /* -W--V */ +#define NV_CMINION_FALCON_IRQSTAT 0x00000008 /* R--4R */ +#define NV_CMINION_FALCON_IRQSTAT_GPTMR 0:0 /* R-IVF */ +#define NV_CMINION_FALCON_IRQSTAT_GPTMR_FALSE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQSTAT_GPTMR_TRUE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQSTAT_WDTMR 1:1 /* R-IVF */ +#define NV_CMINION_FALCON_IRQSTAT_WDTMR_FALSE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQSTAT_WDTMR_TRUE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQSTAT_MTHD 2:2 /* R-IVF */ +#define NV_CMINION_FALCON_IRQSTAT_MTHD_FALSE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQSTAT_MTHD_TRUE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQSTAT_CTXSW 3:3 /* R-IVF */ +#define NV_CMINION_FALCON_IRQSTAT_CTXSW_FALSE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQSTAT_CTXSW_TRUE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQSTAT_HALT 4:4 /* R-IVF */ +#define NV_CMINION_FALCON_IRQSTAT_HALT_FALSE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQSTAT_HALT_TRUE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQSTAT_EXTERR 5:5 /* R-IVF */ +#define NV_CMINION_FALCON_IRQSTAT_EXTERR_FALSE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQSTAT_EXTERR_TRUE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQSTAT_SWGEN0 6:6 /* R-IVF */ +#define NV_CMINION_FALCON_IRQSTAT_SWGEN0_FALSE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQSTAT_SWGEN0_TRUE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQSTAT_SWGEN1 7:7 /* R-IVF */ +#define NV_CMINION_FALCON_IRQSTAT_SWGEN1_FALSE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQSTAT_SWGEN1_TRUE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQSTAT_EXT 15:8 /* */ +#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ1 8:8 /* R-IVF */ +#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ1_TRUE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ1_FALSE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ2 9:9 /* R-IVF */ +#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ2_TRUE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ2_FALSE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ3 10:10 /* R-IVF */ +#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ3_TRUE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ3_FALSE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ4 11:11 /* R-IVF */ +#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ4_TRUE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ4_FALSE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ5 12:12 /* R-IVF */ +#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ5_TRUE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ5_FALSE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ6 13:13 /* R-IVF */ +#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ6_TRUE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ6_FALSE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ7 14:14 /* R-IVF */ +#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ7_TRUE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ7_FALSE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ8 15:15 /* R-IVF */ +#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ8_TRUE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ8_FALSE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQSTAT_DMA 16:16 /* R-IVF */ +#define NV_CMINION_FALCON_IRQSTAT_DMA_TRUE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQSTAT_DMA_FALSE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQSTAT_SHA 17:17 /* R-IVF */ +#define NV_CMINION_FALCON_IRQSTAT_SHA_TRUE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQSTAT_SHA_FALSE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQSTAT_MEMERR 18:18 /* R-IVF */ +#define NV_CMINION_FALCON_IRQSTAT_MEMERR_TRUE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQSTAT_MEMERR_FALSE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQSTAT_CTXSW_ERROR 19:19 /* R-XVF */ +#define NV_CMINION_FALCON_IRQSTAT_CTXSW_ERROR_TRUE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQSTAT_CTXSW_ERROR_FALSE 0x00000000 /* R---V */ +#define NV_CMINION_FALCON_IRQSTAT_ICD 22:22 /* R-XVF */ +#define NV_CMINION_FALCON_IRQSTAT_ICD_TRUE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQSTAT_ICD_FALSE 0x00000000 /* R---V */ +#define NV_CMINION_FALCON_IRQSTAT_IOPMP 23:23 /* R-XVF */ +#define NV_CMINION_FALCON_IRQSTAT_IOPMP_TRUE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQSTAT_IOPMP_FALSE 0x00000000 /* R---V */ +#define NV_CMINION_FALCON_IRQMASK 0x00000018 /* R--4R */ +#define NV_CMINION_FALCON_IRQMASK_GPTMR 0:0 /* R-IVF */ +#define NV_CMINION_FALCON_IRQMASK_GPTMR_DISABLE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQMASK_GPTMR_ENABLE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQMASK_WDTMR 1:1 /* R-IVF */ +#define NV_CMINION_FALCON_IRQMASK_WDTMR_DISABLE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQMASK_WDTMR_ENABLE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQMASK_MTHD 2:2 /* R-IVF */ +#define NV_CMINION_FALCON_IRQMASK_MTHD_DISABLE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQMASK_MTHD_ENABLE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQMASK_CTXSW 3:3 /* R-IVF */ +#define NV_CMINION_FALCON_IRQMASK_CTXSW_DISABLE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQMASK_CTXSW_ENABLE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQMASK_HALT 4:4 /* R-IVF */ +#define NV_CMINION_FALCON_IRQMASK_HALT_DISABLE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQMASK_HALT_ENABLE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQMASK_EXTERR 5:5 /* R-IVF */ +#define NV_CMINION_FALCON_IRQMASK_EXTERR_DISABLE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQMASK_EXTERR_ENABLE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQMASK_SWGEN0 6:6 /* R-IVF */ +#define NV_CMINION_FALCON_IRQMASK_SWGEN0_DISABLE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQMASK_SWGEN0_ENABLE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQMASK_SWGEN1 7:7 /* R-IVF */ +#define NV_CMINION_FALCON_IRQMASK_SWGEN1_DISABLE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQMASK_SWGEN1_ENABLE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQMASK_EXT 15:8 /* */ +#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ1 8:8 /* R-IVF */ +#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ1_ENABLE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ1_DISABLE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ2 9:9 /* R-IVF */ +#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ2_ENABLE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ2_DISABLE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ3 10:10 /* R-IVF */ +#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ3_ENABLE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ3_DISABLE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ4 11:11 /* R-IVF */ +#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ4_ENABLE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ4_DISABLE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ5 12:12 /* R-IVF */ +#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ5_ENABLE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ5_DISABLE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ6 13:13 /* R-IVF */ +#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ6_ENABLE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ6_DISABLE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ7 14:14 /* R-IVF */ +#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ7_ENABLE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ7_DISABLE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ8 15:15 /* R-IVF */ +#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ8_ENABLE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ8_DISABLE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQMASK_DMA 16:16 /* R-IVF */ +#define NV_CMINION_FALCON_IRQMASK_DMA_ENABLE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQMASK_DMA_DISABLE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQMASK_SHA 17:17 /* R-IVF */ +#define NV_CMINION_FALCON_IRQMASK_SHA_ENABLE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQMASK_SHA_DISABLE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQMASK_MEMERR 18:18 /* R-IVF */ +#define NV_CMINION_FALCON_IRQMASK_MEMERR_ENABLE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQMASK_MEMERR_DISABLE 0x00000000 /* R-I-V */ +#define NV_CMINION_FALCON_IRQMASK_CTXSW_ERROR 19:19 /* R-IVF */ +#define NV_CMINION_FALCON_IRQMASK_CTXSW_ERROR_ENABLE 0x00000001 /* R-I-V */ +#define NV_CMINION_FALCON_IRQMASK_CTXSW_ERROR_DISABLE 0x00000000 /* R---V */ +#define NV_CMINION_FALCON_IRQMASK_ICD 22:22 /* R-XVF */ +#define NV_CMINION_FALCON_IRQMASK_ICD_ENABLE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQMASK_ICD_DISABLE 0x00000000 /* R---V */ +#define NV_CMINION_FALCON_IRQMASK_IOPMP 23:23 /* R-XVF */ +#define NV_CMINION_FALCON_IRQMASK_IOPMP_ENABLE 0x00000001 /* R---V */ +#define NV_CMINION_FALCON_IRQMASK_IOPMP_DISABLE 0x00000000 /* R---V */ +#define NV_CMINION_RISCV_CPUCTL 0x00000788 /* RW-4R */ +#define NV_CMINION_RISCV_CPUCTL_STARTCPU 0:0 /* -WIVF */ +#define NV_CMINION_RISCV_CPUCTL_STARTCPU_FALSE 0x00000000 /* -WI-V */ +#define NV_CMINION_RISCV_CPUCTL_STARTCPU_TRUE 0x00000001 /* -W--V */ +#define NV_CMINION_RISCV_CPUCTL_HALTED 4:4 /* R-IVF */ +#define NV_CMINION_RISCV_CPUCTL_HALTED_INIT 0x00000001 /* R-I-V */ +#define NV_CMINION_RISCV_CPUCTL_HALTED_TRUE 0x00000001 /* R---V */ +#define NV_CMINION_RISCV_CPUCTL_HALTED_FALSE 0x00000000 /* R---V */ +#define NV_CMINION_RISCV_CPUCTL_STOPPED 5:5 /* R-IVF */ +#define NV_CMINION_RISCV_CPUCTL_STOPPED_INIT 0x00000000 /* R-I-V */ +#define NV_CMINION_RISCV_CPUCTL_ACTIVE_STAT 7:7 /* R-IVF */ +#define NV_CMINION_RISCV_CPUCTL_ACTIVE_STAT_INACTIVE 0x00000000 /* R-I-V */ +#define NV_CMINION_RISCV_CPUCTL_ACTIVE_STAT_ACTIVE 0x00000001 /* R---V */ +#define NV_MINION_MINION_INTR 0x00002810 /* RW-4R */ +#define NV_MINION_MINION_INTR_FATAL 0:0 /* RWEVF */ +#define NV_MINION_MINION_INTR_FATAL_INIT 0x00000000 /* RWE-V */ +#define NV_MINION_MINION_INTR_NONFATAL 1:1 /* RWEVF */ +#define NV_MINION_MINION_INTR_NONFATAL_INIT 0x00000000 /* RWE-V */ +#define NV_MINION_MINION_INTR_FALCON_STALL 2:2 /* R-EVF */ +#define NV_MINION_MINION_INTR_FALCON_STALL_INIT 0x00000000 /* R-E-V */ +#define NV_MINION_MINION_INTR_FALCON_NOSTALL 3:3 /* R-EVF */ +#define NV_MINION_MINION_INTR_FALCON_NOSTALL_INIT 0x00000000 /* R-E-V */ +#define NV_MINION_MINION_INTR_LINK 31:16 /* R-EVF */ +#define NV_MINION_MINION_INTR_LINK_INIT 0x00000000 /* R-E-V */ +#define NV_MINION_MINION_INTR_STALL_EN 0x00002818 /* RW-4R */ +#define NV_MINION_MINION_INTR_STALL_EN_FATAL 0:0 /* RWEVF */ +#define NV_MINION_MINION_INTR_STALL_EN_FATAL_DISABLE 0x00000000 /* RWE-V */ +#define NV_MINION_MINION_INTR_STALL_EN_FATAL_ENABLE 0x00000001 /* RW--V */ +#define NV_MINION_MINION_INTR_STALL_EN_NONFATAL 1:1 /* RWEVF */ +#define NV_MINION_MINION_INTR_STALL_EN_NONFATAL_DISABLE 0x00000000 /* RWE-V */ +#define NV_MINION_MINION_INTR_STALL_EN_NONFATAL_ENABLE 0x00000001 /* RW--V */ +#define NV_MINION_MINION_INTR_STALL_EN_FALCON_STALL 2:2 /* RWEVF */ +#define NV_MINION_MINION_INTR_STALL_EN_FALCON_STALL_DISABLE 0x00000000 /* RW--V */ +#define NV_MINION_MINION_INTR_STALL_EN_FALCON_STALL_ENABLE 0x00000001 /* RWE-V */ +#define NV_MINION_MINION_INTR_STALL_EN_FALCON_NOSTALL 3:3 /* RWEVF */ +#define NV_MINION_MINION_INTR_STALL_EN_FALCON_NOSTALL_DISABLE 0x00000000 /* RWE-V */ +#define NV_MINION_MINION_INTR_STALL_EN_FALCON_NOSTALL_ENABLE 0x00000001 /* RW--V */ +#define NV_MINION_MINION_INTR_STALL_EN_LINK 31:16 /* RWEVF */ +#define NV_MINION_MINION_INTR_STALL_EN_LINK_DISABLE_ALL 0x00000000 /* RWE-V */ +#define NV_MINION_MINION_INTR_STALL_EN_LINK_ENABLE_ALL 0x0000ffff /* RW--V */ +#define NV_MINION_MINION_INTR_NONSTALL_EN 0x0000281c /* RW-4R */ +#define NV_MINION_MINION_INTR_NONSTALL_EN_FATAL 0:0 /* RWEVF */ +#define NV_MINION_MINION_INTR_NONSTALL_EN_FATAL_DISABLE 0x00000000 /* RWE-V */ +#define NV_MINION_MINION_INTR_NONSTALL_EN_FATAL_ENABLE 0x00000001 /* RW--V */ +#define NV_MINION_MINION_INTR_NONSTALL_EN_NONFATAL 1:1 /* RWEVF */ +#define NV_MINION_MINION_INTR_NONSTALL_EN_NONFATAL_DISABLE 0x00000000 /* RWE-V */ +#define NV_MINION_MINION_INTR_NONSTALL_EN_NONFATAL_ENABLE 0x00000001 /* RW--V */ +#define NV_MINION_MINION_INTR_NONSTALL_EN_FALCON_STALL 2:2 /* RWEVF */ +#define NV_MINION_MINION_INTR_NONSTALL_EN_FALCON_STALL_DISABLE 0x00000000 /* RWE-V */ +#define NV_MINION_MINION_INTR_NONSTALL_EN_FALCON_STALL_ENABLE 0x00000001 /* RW--V */ +#define NV_MINION_MINION_INTR_NONSTALL_EN_FALCON_NOSTALL 3:3 /* RWEVF */ +#define NV_MINION_MINION_INTR_NONSTALL_EN_FALCON_NOSTALL_DISABLE 0x00000000 /* RW--V */ +#define NV_MINION_MINION_INTR_NONSTALL_EN_FALCON_NOSTALL_ENABLE 0x00000001 /* RWE-V */ +#define NV_MINION_MINION_INTR_NONSTALL_EN_LINK 31:16 /* RWEVF */ +#define NV_MINION_MINION_INTR_NONSTALL_EN_LINK_DISABLE_ALL 0x00000000 /* RWE-V */ +#define NV_MINION_MINION_INTR_NONSTALL_EN_LINK_ENABLE_ALL 0x0000ffff /* RW--V */ +#define NV_MINION_MINION_STATUS 0x00002830 /* RW-4R */ +#define NV_MINION_MINION_STATUS_STATUS 7:0 /* RWEVF */ +#define NV_MINION_MINION_STATUS_STATUS_INIT 0x00000000 /* RW--V */ +#define NV_MINION_MINION_STATUS_STATUS_NOTBOOT 0x00000000 /* RWE-V */ +#define NV_MINION_MINION_STATUS_STATUS_BOOT 0x00000001 /* RW--V */ +#define NV_MINION_MINION_STATUS_INTR_CODE 31:8 /* RWEVF */ +#define NV_MINION_MINION_STATUS_INTR_CODE_INIT 0x00000000 /* RWE-V */ +#define NV_MINION_MISC_0 0x000028b0 /* RW-4R */ +#define NV_MINION_MISC_0_SCRATCH_SWRW_0 31:0 /* RWEVF */ +#define NV_MINION_MISC_0_SCRATCH_SWRW_0_INIT 0x00000000 /* RWE-V */ +#define NV_MINION_NVLINK_DL_CMD(i) (0x00002900+(i)*0x4) /* RW-4A */ +#define NV_MINION_NVLINK_DL_CMD__SIZE_1 4 /* */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND 7:0 /* RWEVF */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_NOP 0x00000000 /* RWE-V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITPHY 0x00000001 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_SWINTR 0x00000002 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITLANEENABLE 0x00000003 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITDLPL 0x00000004 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITRXTERM 0x00000005 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITTL 0x00000006 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITPLL 0x00000007 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_LANEDISABLE 0x00000008 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_LANESHUTDOWN 0x0000000c /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITPHASE1 0x0000000d /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITNEGOTIATE 0x0000000e /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITOPTIMIZE 0x0000000f /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_ENABLEPM 0x00000010 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_DISABLEPM 0x00000011 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_TXCLKSWITCH_PLL 0x00000014 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_TXCLKSWITCH_ALT 0x00000015 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_CLEARRESTORESTATE 0x00000017 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_SAVESTATE 0x00000018 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_READ_PHY_TRAINING_PARAMS 0x00000020 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_WRITE_PHY_TRAINING_PARAMS 0x00000021 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITPHASE5A 0x00000022 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_RESERVED1 0x00000023 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_RESERVED2 0x00000024 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_RESERVED3 0x00000025 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_READ_RX_BUFFER_START 0x00000030 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_READ_RX_BUFFER_MIDDLE 0x00000031 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_READ_RX_BUFFER_END 0x00000032 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_WRITE_TX_BUFFER_START 0x00000033 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_WRITE_TX_BUFFER_MIDDLE 0x00000034 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_WRITE_TX_BUFFER_END 0x00000035 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_CLEAR_RX_BUFFER 0x00000036 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_CLEAR_TX_BUFFER 0x00000037 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_CONFIGEOM 0x00000040 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_SETNEA 0x00000041 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_SETNEDR 0x00000042 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_SETNEDW 0x00000043 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_STARTEOM 0x00000044 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_ENDEOM 0x00000045 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_XAVIER_PLLOVERRIDE_ON 0x00000050 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_XAVIER_PLLOVERRIDE_OFF 0x00000051 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_XAVIER_CALIBRATEPLL 0x00000052 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_TURING_RXDET 0x00000058 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_ABORTRXDET 0x00000059 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_SET_BUFFER_READY 0x00000060 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_DLSTAT_CLR_DLERRCNT 0x00000070 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_DLSTAT_CLR_DLLPCNT 0x00000071 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_DLSTAT_CLR_DLTHROUGHPUTCNT 0x00000072 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_DLSTAT_CLR_MINION_MISCCNT 0x00000073 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_RESERVED4 0x00000074 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_RESERVED5 0x00000075 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_FAST 0x00000080 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_MEDIUM 0x00000081 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_SLOW 0x00000082 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_DEFAULT 0x00000083 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_RXCAL_EN_ALARM 0x00000084 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_INIT_CAL_DONE 0x00000085 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_SMF_VALUES_SLOW 0x00000086 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_SMF_VALUES_MEDIUM 0x00000087 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_SMF_VALUES_MEDIUM_SERIAL 0x00000088 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_SMF_VALUES_FAST 0x00000089 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_SMF_VALUES_FAST_ERRORS 0x0000008a /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_PLL_TIMEOUT 0x0000008b /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_UPHY_TABLES_DEFAULT 0x0000008c /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_UPHY_TABLES_SHORT 0x0000008d /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_UPHY_TABLES_FAST 0x0000008e /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_IOBIST_ECC 0x0000008f /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_RESERVED6 0x00000090 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_RESERVED7 0x00000091 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_SET_TIEBREAK_GT 0x00000092 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_PROTECTIONS_OFF 0x000000f0 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE 0x000000f1 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_COMMAND_ALWAYSFAULT 0x000000ff /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_FAULT 30:30 /* RWEVF */ +#define NV_MINION_NVLINK_DL_CMD_FAULT_FAULT_CLEAR 0x00000001 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_FAULT_NOFAULT_NOCLEAR 0x00000000 /* RWE-V */ +#define NV_MINION_NVLINK_DL_CMD_READY 31:31 /* RWEVF */ +#define NV_MINION_NVLINK_DL_CMD_READY_TRUE 0x00000001 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_READY_FALSE 0x00000000 /* RWE-V */ +#define NV_MINION_NVLINK_DL_CMD_DATA(i) (0x00002920+(i)*0x4) /* RW-4A */ +#define NV_MINION_NVLINK_DL_CMD_DATA__SIZE_1 4 /* */ +#define NV_MINION_NVLINK_DL_CMD_DATA_DATA 31:0 /* RWEVF */ +#define NV_MINION_NVLINK_DL_CMD_DATA_DATA_INIT 0x00000000 /* RWE-V */ +#define NV_MINION_NVLINK_DL_CMD_DATA_DATA_SET_BUFFER_READY_TX 0x00000001 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_DATA_DATA_SET_BUFFER_READY_RX 0x00000002 /* RW--V */ +#define NV_MINION_NVLINK_DL_CMD_DATA_DATA_SET_BUFFER_READY_TX_AND_RX 0x00000003 /* RW--V */ +#define NV_MINION_NVLINK_DL_STAT(i) (0x00002980+(i)*0x4) /* RW-4A */ +#define NV_MINION_NVLINK_DL_STAT__SIZE_1 4 /* */ +#define NV_MINION_NVLINK_DL_STAT_ARGS 15:0 /* RWEVF */ +#define NV_MINION_NVLINK_DL_STAT_ARGS_INIT 0x00000000 /* RWE-V */ +#define NV_MINION_NVLINK_DL_STAT_STATUSIDX 23:16 /* RWEVF */ +#define NV_MINION_NVLINK_DL_STAT_STATUSIDX_INIT 0x00000000 /* RWE-V */ +#define NV_MINION_NVLINK_DL_STAT_READY 31:31 /* RWEVF */ +#define NV_MINION_NVLINK_DL_STAT_READY_TRUE 0x00000001 /* RW--V */ +#define NV_MINION_NVLINK_DL_STAT_READY_FALSE 0x00000000 /* RWE-V */ +#define NV_MINION_NVLINK_DL_STATDATA(i) (0x000029c0+(i)*0x4) /* RW-4A */ +#define NV_MINION_NVLINK_DL_STATDATA__SIZE_1 4 /* */ +#define NV_MINION_NVLINK_DL_STATDATA_DATA 31:0 /* RWEVF */ +#define NV_MINION_NVLINK_DL_STATDATA_DATA_INIT 0x00000000 /* RWE-V */ +#define NV_MINION_NVLINK_LINK_INTR(i) (0x00002a00+(i)*0x4) /* RW-4A */ +#define NV_MINION_NVLINK_LINK_INTR__SIZE_1 4 /* */ +#define NV_MINION_NVLINK_LINK_INTR_CODE 7:0 /* RWEVF */ +#define NV_MINION_NVLINK_LINK_INTR_CODE_NA 0x00000000 /* RWE-V */ +#define NV_MINION_NVLINK_LINK_INTR_CODE_SWREQ 0x00000001 /* RW--V */ +#define NV_MINION_NVLINK_LINK_INTR_CODE_DLREQ 0x00000002 /* RW--V */ +#define NV_MINION_NVLINK_LINK_INTR_CODE_PMDISABLED 0x00000003 /* RW--V */ +#define NV_MINION_NVLINK_LINK_INTR_CODE_DLCMDFAULT 0x00000004 /* RW--V */ +#define NV_MINION_NVLINK_LINK_INTR_CODE_TLREQ 0x00000005 /* RW--V */ +#define NV_MINION_NVLINK_LINK_INTR_CODE_NOINIT 0x00000010 /* RW--V */ +#define NV_MINION_NVLINK_LINK_INTR_CODE_NOTIFY 0x00000017 /* RW--V */ +#define NV_MINION_NVLINK_LINK_INTR_CODE_LOCAL_CONFIG_ERR 0x00000018 /* RW--V */ +#define NV_MINION_NVLINK_LINK_INTR_CODE_NEGOTIATION_CONFIG_ERR 0x00000019 /* RW--V */ +#define NV_MINION_NVLINK_LINK_INTR_CODE_BADINIT 0x00000020 /* RW--V */ +#define NV_MINION_NVLINK_LINK_INTR_CODE_PMFAIL 0x00000021 /* RW--V */ +#define NV_MINION_NVLINK_LINK_INTR_CODE_INBAND_BUFFER_AVAILABLE 0x00000022 /* RW--V */ +#define NV_MINION_NVLINK_LINK_INTR_CODE_INBAND_BUFFER_COMPLETE 0x00000023 /* RW--V */ +#define NV_MINION_NVLINK_LINK_INTR_CODE_INBAND_BUFFER_FAIL 0x00000024 /* RW--V */ +#define NV_MINION_NVLINK_LINK_INTR_SUBCODE 15:8 /* RWEVF */ +#define NV_MINION_NVLINK_LINK_INTR_SUBCODE_INIT 0x00000000 /* RWE-V */ +#define NV_MINION_NVLINK_LINK_INTR_STATE 31:31 /* RWEVF */ +#define NV_MINION_NVLINK_LINK_INTR_STATE_INIT 0x00000000 /* RWE-V */ + +#define NV_MINION_ERR_STATUS_0 0x00002d00 /* RW-4R */ +#define NV_MINION_ERR_STATUS_0_MINION_IMEM_PARITY_ERR 0:0 /* RWIVF */ +#define NV_MINION_ERR_STATUS_0_MINION_IMEM_PARITY_ERR__ONWRITE "oneToClear" /* */ +#define NV_MINION_ERR_STATUS_0_MINION_IMEM_PARITY_ERR_NONE 0x00000000 /* RWI-V */ +#define NV_MINION_ERR_STATUS_0_MINION_IMEM_PARITY_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_MINION_ERR_STATUS_0_MINION_DMEM_PARITY_ERR 4:4 /* RWIVF */ +#define NV_MINION_ERR_STATUS_0_MINION_DMEM_PARITY_ERR__ONWRITE "oneToClear" /* */ +#define NV_MINION_ERR_STATUS_0_MINION_DMEM_PARITY_ERR_NONE 0x00000000 /* RWI-V */ +#define NV_MINION_ERR_STATUS_0_MINION_DMEM_PARITY_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_MINION_ERR_STATUS_0_MINION_MPU_PARITY_ERR 8:8 /* RWIVF */ +#define NV_MINION_ERR_STATUS_0_MINION_MPU_PARITY_ERR__ONWRITE "oneToClear" /* */ +#define NV_MINION_ERR_STATUS_0_MINION_MPU_PARITY_ERR_NONE 0x00000000 /* RWI-V */ +#define NV_MINION_ERR_STATUS_0_MINION_MPU_PARITY_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_MINION_ERR_STATUS_0_MINION_REG_PARITY_ERR 12:12 /* RWIVF */ +#define NV_MINION_ERR_STATUS_0_MINION_REG_PARITY_ERR__ONWRITE "oneToClear" /* */ +#define NV_MINION_ERR_STATUS_0_MINION_REG_PARITY_ERR_NONE 0x00000000 /* RWI-V */ +#define NV_MINION_ERR_STATUS_0_MINION_REG_PARITY_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_MINION_ERR_LOG_EN_0 0x00002d04 /* RW-4R */ +#define NV_MINION_ERR_LOG_EN_0_MINION_IMEM_PARITY_ERR 0:0 /* RWEVF */ +#define NV_MINION_ERR_LOG_EN_0_MINION_IMEM_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MINION_ERR_LOG_EN_0_MINION_IMEM_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MINION_ERR_LOG_EN_0_MINION_DMEM_PARITY_ERR 4:4 /* RWEVF */ +#define NV_MINION_ERR_LOG_EN_0_MINION_DMEM_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MINION_ERR_LOG_EN_0_MINION_DMEM_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MINION_ERR_LOG_EN_0_MINION_MPU_PARITY_ERR 8:8 /* RWEVF */ +#define NV_MINION_ERR_LOG_EN_0_MINION_MPU_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MINION_ERR_LOG_EN_0_MINION_MPU_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MINION_ERR_LOG_EN_0_MINION_REG_PARITY_ERR 12:12 /* RWEVF */ +#define NV_MINION_ERR_LOG_EN_0_MINION_REG_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MINION_ERR_LOG_EN_0_MINION_REG_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MINION_ERR_FATAL_REPORT_EN_0 0x00002d08 /* RW-4R */ +#define NV_MINION_ERR_FATAL_REPORT_EN_0_MINION_IMEM_PARITY_ERR 0:0 /* RWEVF */ +#define NV_MINION_ERR_FATAL_REPORT_EN_0_MINION_IMEM_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MINION_ERR_FATAL_REPORT_EN_0_MINION_IMEM_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MINION_ERR_FATAL_REPORT_EN_0_MINION_DMEM_PARITY_ERR 4:4 /* RWEVF */ +#define NV_MINION_ERR_FATAL_REPORT_EN_0_MINION_DMEM_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MINION_ERR_FATAL_REPORT_EN_0_MINION_DMEM_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MINION_ERR_FATAL_REPORT_EN_0_MINION_MPU_PARITY_ERR 8:8 /* RWEVF */ +#define NV_MINION_ERR_FATAL_REPORT_EN_0_MINION_MPU_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MINION_ERR_FATAL_REPORT_EN_0_MINION_MPU_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MINION_ERR_FATAL_REPORT_EN_0_MINION_REG_PARITY_ERR 12:12 /* RWEVF */ +#define NV_MINION_ERR_FATAL_REPORT_EN_0_MINION_REG_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MINION_ERR_FATAL_REPORT_EN_0_MINION_REG_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MINION_ERR_NON_FATAL_REPORT_EN_0 0x00002d0c /* RW-4R */ +#define NV_MINION_ERR_NON_FATAL_REPORT_EN_0_MINION_IMEM_PARITY_ERR 0:0 /* RWEVF */ +#define NV_MINION_ERR_NON_FATAL_REPORT_EN_0_MINION_IMEM_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MINION_ERR_NON_FATAL_REPORT_EN_0_MINION_IMEM_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MINION_ERR_NON_FATAL_REPORT_EN_0_MINION_DMEM_PARITY_ERR 4:4 /* RWEVF */ +#define NV_MINION_ERR_NON_FATAL_REPORT_EN_0_MINION_DMEM_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MINION_ERR_NON_FATAL_REPORT_EN_0_MINION_DMEM_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MINION_ERR_NON_FATAL_REPORT_EN_0_MINION_MPU_PARITY_ERR 8:8 /* RWEVF */ +#define NV_MINION_ERR_NON_FATAL_REPORT_EN_0_MINION_MPU_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MINION_ERR_NON_FATAL_REPORT_EN_0_MINION_MPU_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MINION_ERR_NON_FATAL_REPORT_EN_0_MINION_REG_PARITY_ERR 12:12 /* RWEVF */ +#define NV_MINION_ERR_NON_FATAL_REPORT_EN_0_MINION_REG_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MINION_ERR_NON_FATAL_REPORT_EN_0_MINION_REG_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MINION_ERR_CORRECTABLE_REPORT_EN_0 0x00002d10 /* RW-4R */ +#define NV_MINION_ERR_CONTAIN_EN_0 0x00002d14 /* RW-4R */ +#define NV_MINION_ERR_CONTAIN_EN_0_MINION_IMEM_PARITY_ERR 0:0 /* RWEVF */ +#define NV_MINION_ERR_CONTAIN_EN_0_MINION_IMEM_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MINION_ERR_CONTAIN_EN_0_MINION_IMEM_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MINION_ERR_CONTAIN_EN_0_MINION_DMEM_PARITY_ERR 4:4 /* RWEVF */ +#define NV_MINION_ERR_CONTAIN_EN_0_MINION_DMEM_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MINION_ERR_CONTAIN_EN_0_MINION_DMEM_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MINION_ERR_CONTAIN_EN_0_MINION_MPU_PARITY_ERR 8:8 /* RWEVF */ +#define NV_MINION_ERR_CONTAIN_EN_0_MINION_MPU_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MINION_ERR_CONTAIN_EN_0_MINION_MPU_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MINION_ERR_CONTAIN_EN_0_MINION_REG_PARITY_ERR 12:12 /* RWEVF */ +#define NV_MINION_ERR_CONTAIN_EN_0_MINION_REG_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MINION_ERR_CONTAIN_EN_0_MINION_REG_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MINION_ERR_FIRST_0 0x00002d1c /* RW-4R */ +#define NV_MINION_ERR_FIRST_0_MINION_IMEM_PARITY_ERR 0:0 /* RWIVF */ +#define NV_MINION_ERR_FIRST_0_MINION_IMEM_PARITY_ERR__ONWRITE "oneToClear" /* */ +#define NV_MINION_ERR_FIRST_0_MINION_IMEM_PARITY_ERR_NONE 0x00000000 /* RWI-V */ +#define NV_MINION_ERR_FIRST_0_MINION_IMEM_PARITY_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_MINION_ERR_FIRST_0_MINION_DMEM_PARITY_ERR 4:4 /* RWIVF */ +#define NV_MINION_ERR_FIRST_0_MINION_DMEM_PARITY_ERR__ONWRITE "oneToClear" /* */ +#define NV_MINION_ERR_FIRST_0_MINION_DMEM_PARITY_ERR_NONE 0x00000000 /* RWI-V */ +#define NV_MINION_ERR_FIRST_0_MINION_DMEM_PARITY_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_MINION_ERR_FIRST_0_MINION_MPU_PARITY_ERR 8:8 /* RWIVF */ +#define NV_MINION_ERR_FIRST_0_MINION_MPU_PARITY_ERR__ONWRITE "oneToClear" /* */ +#define NV_MINION_ERR_FIRST_0_MINION_MPU_PARITY_ERR_NONE 0x00000000 /* RWI-V */ +#define NV_MINION_ERR_FIRST_0_MINION_MPU_PARITY_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_MINION_ERR_FIRST_0_MINION_REG_PARITY_ERR 12:12 /* RWIVF */ +#define NV_MINION_ERR_FIRST_0_MINION_REG_PARITY_ERR__ONWRITE "oneToClear" /* */ +#define NV_MINION_ERR_FIRST_0_MINION_REG_PARITY_ERR_NONE 0x00000000 /* RWI-V */ +#define NV_MINION_ERR_FIRST_0_MINION_REG_PARITY_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_MINION_ERR_IMEM_ERROR_ADDRESS 0x00002d20 /* R--4R */ +#define NV_MINION_ERR_IMEM_ERROR_ADDRESS_ERROR_ADDRESS 15:0 /* R-IVF */ +#define NV_MINION_ERR_IMEM_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-I-V */ +#define NV_MINION_ERR_DMEM_ERROR_ADDRESS 0x00002d24 /* R--4R */ +#define NV_MINION_ERR_DMEM_ERROR_ADDRESS_ERROR_ADDRESS 15:0 /* R-IVF */ +#define NV_MINION_ERR_DMEM_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-I-V */ +#define NV_MINION_ERR_MPU_ERROR_ADDRESS 0x00002d28 /* R--4R */ +#define NV_MINION_ERR_MPU_ERROR_ADDRESS_ERROR_ADDRESS 15:0 /* R-IVF */ +#define NV_MINION_ERR_MPU_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-I-V */ + +#endif // __ls10_dev_minion_ip_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_minion_ip_addendum.h b/src/common/inc/swref/published/nvswitch/ls10/dev_minion_ip_addendum.h new file mode 100644 index 000000000..93cfc489b --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_minion_ip_addendum.h @@ -0,0 +1,352 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_minion_ip_addendum_h__ +#define __ls10_dev_minion_ip_addendum_h__ + +// ALARM Timings needed for EMU +#define NV_MINION_DL_CMD_DATA_RXCAL_EN_ALARM 0x50 +#define NV_MINION_DL_CMD_DATA_INIT_CAL_DONE 0x26 + +// filtering dev_minion_dlstat.ref for pattern (CMINION|MINION|NVLSTAT|PMINION|SWMINION) +#define NV_NVLSTAT 0x00000103:0x00000000 /* RW--D */ +#define NV_NVLSTAT_UC01 0x00000001 /* R--4R */ +#define NV_NVLSTAT_UC01_PM_STATE 31:31 /* R---F */ +#define NV_NVLSTAT_UC01_ACMODE_STATE 30:30 /* R---F */ +#define NV_NVLSTAT_UC01_LANES_ENABLED 29:29 /* R---F */ +#define NV_NVLSTAT_UC01_LANES_ENABLED_TRUE 0x1 /* R---V */ +#define NV_NVLSTAT_UC01_LANES_ENABLED_FALSE 0x0 /* R---V */ +#define NV_NVLSTAT_UC01_INBAND_BUFFER_FAIL 26:26 /* R---F */ +#define NV_NVLSTAT_UC01_INBAND_BUFFER_FAIL_TRUE 0x1 /* R---F */ +#define NV_NVLSTAT_UC01_INBAND_BUFFER_FAIL_FALSE 0x0 /* R---F */ +#define NV_NVLSTAT_UC01_INBAND_BUFFER_COMPLETE 25:25 /* R---F */ +#define NV_NVLSTAT_UC01_INBAND_BUFFER_COMPLETE_TRUE 0x1 /* R---F */ +#define NV_NVLSTAT_UC01_INBAND_BUFFER_COMPLETE_FALSE 0x0 /* R---F */ +#define NV_NVLSTAT_UC01_L2EXIT_DONE 24:24 /* R---F */ +#define NV_NVLSTAT_UC01_L2EXIT_DONE_SUCCESS 0x1 /* R---V */ +#define NV_NVLSTAT_UC01_L2EXIT_DONE_UNKNOWN 0x0 /* R---V */ +#define NV_NVLSTAT_UC01_TRAINING_BUFFER_STATUS 23:20 /* R---F */ +#define NV_NVLSTAT_UC01_SEARCH_ERROR 19:19 /* R---F */ +#define NV_NVLSTAT_UC01_TRAINING_GOOD 18:18 /* R---F */ +#define NV_NVLSTAT_UC01_TRAINING_GOOD_SUCCESS 0x1 /* R---V */ +#define NV_NVLSTAT_UC01_TRAINING_GOOD_UNKNOWN 0x0 /* R---V */ +#define NV_NVLSTAT_UC01_AUTOINIT_DONE 17:17 /* R---F */ +#define NV_NVLSTAT_UC01_AUTOINIT_DONE_SUCCESS 0x1 /* R---V */ +#define NV_NVLSTAT_UC01_AUTOINIT_DONE_UNKNOWN 0x0 /* R---V */ +#define NV_NVLSTAT_UC01_CONFIG_GOOD 16:16 /* R---F */ +#define NV_NVLSTAT_UC01_CONFIG_GOOD_SUCCESS 0x1 /* R---V */ +#define NV_NVLSTAT_UC01_CONFIG_GOOD_UNKNOWN 0x0 /* R---V */ +#define NV_NVLSTAT_UC01_LINK_STATE 15:0 /* R---F */ +#define NV_NVLSTAT_LNK0 0x00000010 /* R--4R */ +#define NV_NVLSTAT_LNK0_INTR_TX_FAULT_RAM 4:4 /* R---F */ +#define NV_NVLSTAT_LNK0_INTR_TX_FAULT_INTERFACE 5:5 /* R---F */ +#define NV_NVLSTAT_LNK0_INTR_TX_FAULT_SUBLINK_CHANGE 8:8 /* R---F */ +#define NV_NVLSTAT_LNK0_INTR_RX_FAULT_SUBLINK_CHANGE 16:16 /* R---F */ +#define NV_NVLSTAT_LNK0_INTR_RX_FAULT_DL_PROTOCOL 20:20 /* R---F */ +#define NV_NVLSTAT_LNK0_INTR_RX_FAULT_SHORT_ERROR_RATE 21:21 /* R---F */ +#define NV_NVLSTAT_LNK0_INTR_RX_FAULT_LONG_ERROR_RATE 22:22 /* R---F */ +#define NV_NVLSTAT_LNK0_INTR_LTSSM_PROTOCOL 29:29 /* R---F */ +#define NV_NVLSTAT_LNK1 0x00000011 /* R--4R */ +#define NV_NVLSTAT_LNK1_ERROR_COUNT1_RECOVERY_EVENTS_VALUE 30:0 /* R---F */ +#define NV_NVLSTAT_LNK1_ERROR_COUNT1_RECOVERY_EVENTS_VALUE_SRCOVF 0x000003ff /* R---V */ +#define NV_NVLSTAT_LNK1_ERROR_COUNT1_RECOVERY_EVENTS_OVER 31:31 /* R---F */ +#define NV_NVLSTAT_LNK1_ERROR_COUNT1_RECOVERY_EVENTS_OVER_OVER 0x1 /* R---V */ +#define NV_NVLSTAT_LNK1_ERROR_COUNT1_RECOVERY_EVENTS_OVER_OKAY 0x0 /* R---V */ +#define NV_NVLSTAT_LNK2 0x00000012 /* R--4R */ +#define NV_NVLSTAT_LNK2_RXDET_LINK_STATUS 9:8 /* R---F */ +#define NV_NVLSTAT_LNK2_RXDET_LINK_STATUS_UNINITIALIZED 0x0 /* R---V */ +#define NV_NVLSTAT_LNK2_RXDET_LINK_STATUS_SEARCH 0x1 /* R---V */ +#define NV_NVLSTAT_LNK2_RXDET_LINK_STATUS_FOUND 0x2 /* R---V */ +#define NV_NVLSTAT_LNK2_RXDET_LINK_STATUS_TIMEOUT 0x3 /* R---V */ +#define NV_NVLSTAT_LNK2_RXDET_LANE_STATUS 7:0 /* R---F */ +#define NV_NVLSTAT_LNK2_RXDET_LANE_STATUS_FOUND 0x0f /* R---V */ +#define NV_NVLSTAT_LNK3 0x00000013 /* R--4R */ +#define NV_NVLSTAT_LNK3_LINERATE 23:0 /* R---F */ +#define NV_NVLSTAT_LNK4 0x00000014 /* R--4R */ +#define NV_NVLSTAT_LNK4_LINKCLOCK 15:0 /* R---F */ +#define NV_NVLSTAT_LNK5 0x00000015 /* R--4R */ +#define NV_NVLSTAT_LNK5_DATARATE 31:0 /* R---F */ +#define NV_NVLSTAT_TX01 0x00000021 /* R--4R */ +#define NV_NVLSTAT_TX01_COUNT_TX_STATE_NVHS_VALUE 30:0 /* R---F */ +#define NV_NVLSTAT_TX01_COUNT_TX_STATE_NVHS_VALUE_SRCOVF 0x0000ffff /* R---V */ +#define NV_NVLSTAT_TX01_COUNT_TX_STATE_NVHS_OVER 31:31 /* R---F */ +#define NV_NVLSTAT_TX01_COUNT_TX_STATE_NVHS_OVER_OVER 0x1 /* R---V */ +#define NV_NVLSTAT_TX01_COUNT_TX_STATE_NVHS_OVER_OKAY 0x0 /* R---V */ +#define NV_NVLSTAT_TX02 0x00000022 /* R--4R */ +#define NV_NVLSTAT_TX02_COUNT_TX_STATE_OTHER_VALUE 30:0 /* R---F */ +#define NV_NVLSTAT_TX02_COUNT_TX_STATE_OTHER_VALUE_SRCOVF 0x0000ffff /* R---V */ +#define NV_NVLSTAT_TX02_COUNT_TX_STATE_OTHER_OVER 31:31 /* R---F */ +#define NV_NVLSTAT_TX02_COUNT_TX_STATE_OTHER_OVER_OVER 0x1 /* R---V */ +#define NV_NVLSTAT_TX02_COUNT_TX_STATE_OTHER_OVER_OKAY 0x0 /* R---V */ +#define NV_NVLSTAT_TX03 0x00000023 /* R--4R */ +#define NV_NVLSTAT_TX03_DELAY_LCL_LP_ENTER_VALUE 30:0 /* R---F */ +#define NV_NVLSTAT_TX03_DELAY_LCL_LP_ENTER_VALUE_SRCOVF 0x000000ff /* R---V */ +#define NV_NVLSTAT_TX03_DELAY_LCL_LP_ENTER_OVER 31:31 /* R---F */ +#define NV_NVLSTAT_TX03_DELAY_LCL_LP_ENTER_OVER_OVER 0x1 /* R---V */ +#define NV_NVLSTAT_TX03_DELAY_LCL_LP_ENTER_OVER_OKAY 0x0 /* R---V */ +#define NV_NVLSTAT_TX04 0x00000024 /* R--4R */ +#define NV_NVLSTAT_TX04_DELAY_LCL_LP_EXIT_VALUE 30:0 /* R---F */ +#define NV_NVLSTAT_TX04_DELAY_LCL_LP_EXIT_VALUE_SRCOVF 0x000000ff /* R---V */ +#define NV_NVLSTAT_TX04_DELAY_LCL_LP_EXIT_OVER 31:31 /* R---F */ +#define NV_NVLSTAT_TX04_DELAY_LCL_LP_EXIT_OVER_OVER 0x1 /* R---V */ +#define NV_NVLSTAT_TX04_DELAY_LCL_LP_EXIT_OVER_OKAY 0x0 /* R---V */ +#define NV_NVLSTAT_TX05 0x00000025 /* R--4R */ +#define NV_NVLSTAT_TX05_NUM_LCL_LP_EXIT_VALUE 30:0 /* R---F */ +#define NV_NVLSTAT_TX05_NUM_LCL_LP_EXIT_VALUE_SRCOVF 0x0000ffff /* R---V */ +#define NV_NVLSTAT_TX05_NUM_LCL_LP_EXIT_OVER 31:31 /* R---F */ +#define NV_NVLSTAT_TX05_NUM_LCL_LP_EXIT_OVER_OVER 0x1 /* R---V */ +#define NV_NVLSTAT_TX05_NUM_LCL_LP_EXIT_OVER_OKAY 0x0 /* R---V */ +#define NV_NVLSTAT_TX06 0x00000026 /* R--4R */ +#define NV_NVLSTAT_TX06_NUM_LCL_LP_ENTER_VALUE 30:0 /* R---F */ +#define NV_NVLSTAT_TX06_NUM_LCL_LP_ENTER_VALUE_SRCOVF 0x0000ffff /* R---V */ +#define NV_NVLSTAT_TX06_NUM_LCL_LP_ENTER_OVER 31:31 /* R---F */ +#define NV_NVLSTAT_TX06_NUM_LCL_LP_ENTER_OVER_OVER 0x1 /* R---V */ +#define NV_NVLSTAT_TX06_NUM_LCL_LP_ENTER_OVER_OKAY 0x0 /* R---V */ +#define NV_NVLSTAT_TX07 0x00000027 /* R--4R */ +#define NV_NVLSTAT_TX07_DELAY_LCL_FB_EXIT_OTHER_VALUE 30:0 /* R---F */ +#define NV_NVLSTAT_TX07_DELAY_LCL_FB_EXIT_OTHER_VALUE_SRCOVF 0x000000ff /* R---V */ +#define NV_NVLSTAT_TX07_DELAY_LCL_FB_EXIT_OTHER_OVER 31:31 /* R---F */ +#define NV_NVLSTAT_TX07_DELAY_LCL_FB_EXIT_OTHER_OVER_OVER 0x1 /* R---V */ +#define NV_NVLSTAT_TX07_DELAY_LCL_FB_EXIT_OTHER_OVER_OKAY 0x0 /* R---V */ +#define NV_NVLSTAT_TX08 0x00000028 /* R--4R */ +#define NV_NVLSTAT_TX08_DELAY_LCL_FB_ENTER_OTHER_VALUE 30:0 /* R---F */ +#define NV_NVLSTAT_TX08_DELAY_LCL_FB_ENTER_OTHER_VALUE_SRCOVF 0x000000ff /* R---V */ +#define NV_NVLSTAT_TX08_DELAY_LCL_FB_ENTER_OTHER_OVER 31:31 /* R---F */ +#define NV_NVLSTAT_TX08_DELAY_LCL_FB_ENTER_OTHER_OVER_OVER 0x1 /* R---V */ +#define NV_NVLSTAT_TX08_DELAY_LCL_FB_ENTER_OTHER_OVER_OKAY 0x0 /* R---V */ +#define NV_NVLSTAT_TX09 0x00000029 /* R--4R */ +#define NV_NVLSTAT_TX09_REPLAY_EVENTS_VALUE 30:0 /* R---F */ +#define NV_NVLSTAT_TX09_REPLAY_EVENTS_VALUE_SRCOVF 0x000000ff /* R---V */ +#define NV_NVLSTAT_TX09_REPLAY_EVENTS_OVER 31:31 /* R---F */ +#define NV_NVLSTAT_TX09_REPLAY_EVENTS_OVER_OVER 0x1 /* R---V */ +#define NV_NVLSTAT_TX09_REPLAY_EVENTS_OVER_OKAY 0x0 /* R---V */ +#define NV_NVLSTAT_TX10 0x0000002a /* R--4R */ +#define NV_NVLSTAT_TX10_COUNT_TX_STATE_SLEEP_VALUE 30:0 /* R---F */ +#define NV_NVLSTAT_TX10_COUNT_TX_STATE_SLEEP_VALUE_SRCOVF 0x0000ffff /* R---V */ +#define NV_NVLSTAT_TX10_COUNT_TX_STATE_SLEEP_OVER 31:31 /* R---F */ +#define NV_NVLSTAT_TX10_COUNT_TX_STATE_SLEEP_OVER_OVER 0x1 /* R---V */ +#define NV_NVLSTAT_TX10_COUNT_TX_STATE_SLEEP_OVER_OKAY 0x0 /* R---V */ +#define NV_NVLSTAT_TX11 0x0000002b /* R--4R */ +#define NV_NVLSTAT_TX11_NUM_RMT_LP_EXIT_VALUE 30:0 /* R---F */ +#define NV_NVLSTAT_TX11_NUM_RMT_LP_EXIT_VALUE_SRCOVF 0x0000ffff /* R---V */ +#define NV_NVLSTAT_TX11_NUM_RMT_LP_EXIT_OVER 31:31 /* R---F */ +#define NV_NVLSTAT_TX11_NUM_RMT_LP_EXIT_OVER_OVER 0x1 /* R---V */ +#define NV_NVLSTAT_TX11_NUM_RMT_LP_EXIT_OVER_OKAY 0x0 /* R---V */ +#define NV_NVLSTAT_TX12 0x0000002c /* R--4R */ +#define NV_NVLSTAT_TX12_TX_LPOCC_HIST 31:0 /* R---F */ +#define NV_NVLSTAT_TX13 0x0000002d /* R--4R */ +#define NV_NVLSTAT_TX13_TX_LPOCC_HIST 31:0 /* R---F */ +#define NV_NVLSTAT_TX14 0x0000002e /* R--4R */ +#define NV_NVLSTAT_TX14_TX_LPEXIT_HIST 31:0 /* R---F */ +#define NV_NVLSTAT_TX15 0x0000002f /* R--4R */ +#define NV_NVLSTAT_TX15_TX_LPEXIT_HIST 31:0 /* R---F */ +#define NV_NVLSTAT_RX00 0x00000040 /* R--4R */ +#define NV_NVLSTAT_RX00_REPLAY_EVENTS_VALUE 30:0 /* R---F */ +#define NV_NVLSTAT_RX00_REPLAY_EVENTS_VALUE_SRCOVF 0x0000ffff /* R---V */ +#define NV_NVLSTAT_RX00_REPLAY_EVENTS_OVER 31:31 /* R---F */ +#define NV_NVLSTAT_RX00_REPLAY_EVENTS_OVER_OVER 0x1 /* R---V */ +#define NV_NVLSTAT_RX00_REPLAY_EVENTS_OVER_OKAY 0x0 /* R---V */ +#define NV_NVLSTAT_RX01 0x00000041 /* R--4R */ +#define NV_NVLSTAT_RX01_FLIT_CRC_ERRORS_VALUE 30:0 /* R---F */ +#define NV_NVLSTAT_RX01_FLIT_CRC_ERRORS_VALUE_SRCOVF 0x7fffffff /* R---V */ +#define NV_NVLSTAT_RX01_FLIT_CRC_ERRORS_OVER 31:31 /* R---F */ +#define NV_NVLSTAT_RX01_FLIT_CRC_ERRORS_OVER_OVER 0x1 /* R---V */ +#define NV_NVLSTAT_RX01_FLIT_CRC_ERRORS_OVER_OKAY 0x0 /* R---V */ +#define NV_NVLSTAT_RX02 0x00000042 /* R--4R */ +#define NV_NVLSTAT_RX02_MASKED_CRC_ERRORS_VALUE 30:0 /* R---F */ +#define NV_NVLSTAT_RX02_MASKED_CRC_ERRORS_VALUE_SRCOVF 0x7fffffff /* R---V */ +#define NV_NVLSTAT_RX02_MASKED_CRC_ERRORS_OVER 31:31 /* R---F */ +#define NV_NVLSTAT_RX02_MASKED_CRC_ERRORS_OVER_OVER 0x1 /* R---V */ +#define NV_NVLSTAT_RX02_MASKED_CRC_ERRORS_OVER_OKAY 0x0 /* R---V */ +#define NV_NVLSTAT_RX03 0x00000043 /* R--4R */ +#define NV_NVLSTAT_RX03_DELAY_RMT_LP_ENTER_VALUE 30:0 /* R---F */ +#define NV_NVLSTAT_RX03_DELAY_RMT_LP_ENTER_VALUE_SRCOVF 0x000000ff /* R---V */ +#define NV_NVLSTAT_RX03_DELAY_RMT_LP_ENTER_OVER 31:31 /* R---F */ +#define NV_NVLSTAT_RX03_DELAY_RMT_LP_ENTER_OVER_OVER 0x1 /* R---V */ +#define NV_NVLSTAT_RX03_DELAY_RMT_LP_ENTER_OVER_OKAY 0x0 /* R---V */ +#define NV_NVLSTAT_RX04 0x00000044 /* R--4R */ +#define NV_NVLSTAT_RX04_DELAY_RMT_LP_EXIT_VALUE 30:0 /* R---F */ +#define NV_NVLSTAT_RX04_DELAY_RMT_LP_EXIT_VALUE_SRCOVF 0x000000ff /* R---V */ +#define NV_NVLSTAT_RX04_DELAY_RMT_LP_EXIT_OVER 31:31 /* R---F */ +#define NV_NVLSTAT_RX04_DELAY_RMT_LP_EXIT_OVER_OVER 0x1 /* R---V */ +#define NV_NVLSTAT_RX04_DELAY_RMT_LP_EXIT_OVER_OKAY 0x0 /* R---V */ +#define NV_NVLSTAT_RX05 0x00000045 /* R--4R */ +#define NV_NVLSTAT_RX05_DELAY_RMT_FB_ENTER_VALUE 30:0 /* R---F */ +#define NV_NVLSTAT_RX05_DELAY_RMT_FB_ENTER_VALUE_SRCOVF 0x000000ff /* R---V */ +#define NV_NVLSTAT_RX05_DELAY_RMT_FB_ENTER_OVER 31:31 /* R---F */ +#define NV_NVLSTAT_RX05_DELAY_RMT_FB_ENTER_OVER_OVER 0x1 /* R---V */ +#define NV_NVLSTAT_RX05_DELAY_RMT_FB_ENTER_OVER_OKAY 0x0 /* R---V */ +#define NV_NVLSTAT_RX06 0x00000046 /* R--4R */ +#define NV_NVLSTAT_RX06_DELAY_RMT_FB_EXIT_VALUE 30:0 /* R---F */ +#define NV_NVLSTAT_RX06_DELAY_RMT_FB_EXIT_VALUE_SRCOVF 0x000000ff /* R---V */ +#define NV_NVLSTAT_RX06_DELAY_RMT_FB_EXIT_OVER 31:31 /* R---F */ +#define NV_NVLSTAT_RX06_DELAY_RMT_FB_EXIT_OVER_OVER 0x1 /* R---V */ +#define NV_NVLSTAT_RX06_DELAY_RMT_FB_EXIT_OVER_OKAY 0x0 /* R---V */ +#define NV_NVLSTAT_RX08 0x00000048 /* R--4R */ +#define NV_NVLSTAT_RX08_ERRORLOG_ERR_CNT_MULTI 7:0 /* R---F */ +#define NV_NVLSTAT_RX09 0x00000049 /* R--4R */ +#define NV_NVLSTAT_RX09_ERRORLOG_ERR_CNT_7 31:24 /* R---F */ +#define NV_NVLSTAT_RX09_ERRORLOG_ERR_CNT_6 23:16 /* R---F */ +#define NV_NVLSTAT_RX09_ERRORLOG_ERR_CNT_5 15:8 /* R---F */ +#define NV_NVLSTAT_RX09_ERRORLOG_ERR_CNT_4 7:0 /* R---F */ +#define NV_NVLSTAT_RX10 0x0000004a /* R--4R */ +#define NV_NVLSTAT_RX10_ERRORLOG_ERR_CNT_3 31:24 /* R---F */ +#define NV_NVLSTAT_RX10_ERRORLOG_ERR_CNT_2 23:16 /* R---F */ +#define NV_NVLSTAT_RX10_ERRORLOG_ERR_CNT_1 15:8 /* R---F */ +#define NV_NVLSTAT_RX10_ERRORLOG_ERR_CNT_0 7:0 /* R---F */ +#define NV_NVLSTAT_RX11 0x0000004b /* R--4R */ +#define NV_NVLSTAT_RX11_ECC_DEC_FAILED_VALUE 30:0 /* R---F */ +#define NV_NVLSTAT_RX11_ECC_DEC_FAILED_VALUE_SRCOVF 0x00ffffff /* R---V */ +#define NV_NVLSTAT_RX11_ECC_DEC_FAILED_OVER 31:31 /* R---F */ +#define NV_NVLSTAT_RX11_ECC_DEC_FAILED_OVER_OVER 0x1 /* R---V */ +#define NV_NVLSTAT_RX11_ECC_DEC_FAILED_OVER_OKAY 0x0 /* R---V */ +#define NV_NVLSTAT_RX12 0x0000004c /* R--4R */ +#define NV_NVLSTAT_RX12_ECC_CORRECTED_ERR_L0_VALUE 30:0 /* R---F */ +#define NV_NVLSTAT_RX12_ECC_CORRECTED_ERR_L0_VALUE_SRCOVF 0x7fffffff /* R---V */ +#define NV_NVLSTAT_RX12_ECC_CORRECTED_ERR_L0_OVER 31:31 /* R---F */ +#define NV_NVLSTAT_RX12_ECC_CORRECTED_ERR_L0_OVER_OVER 0x1 /* R---V */ +#define NV_NVLSTAT_RX12_ECC_CORRECTED_ERR_L0_OVER_OKAY 0x0 /* R---V */ +#define NV_NVLSTAT_RX13 0x0000004d /* R--4R */ +#define NV_NVLSTAT_RX13_ECC_CORRECTED_ERR_L1_VALUE 30:0 /* R---F */ +#define NV_NVLSTAT_RX13_ECC_CORRECTED_ERR_L1_VALUE_SRCOVF 0x7fffffff /* R---V */ +#define NV_NVLSTAT_RX13_ECC_CORRECTED_ERR_L1_OVER 31:31 /* R---F */ +#define NV_NVLSTAT_RX13_ECC_CORRECTED_ERR_L1_OVER_OVER 0x1 /* R---V */ +#define NV_NVLSTAT_RX13_ECC_CORRECTED_ERR_L1_OVER_OKAY 0x0 /* R---V */ +#define NV_NVLSTAT_TR00 0x00000090 /* R--4R */ +#define NV_NVLSTAT_TR00_DATA 31:0 /* R---F */ +#define NV_NVLSTAT_TR01 0x00000091 /* R--4R */ +#define NV_NVLSTAT_TR01_DATA 31:0 /* R---F */ +#define NV_NVLSTAT_TR02 0x00000092 /* R--4R */ +#define NV_NVLSTAT_TR02_DATA 31:0 /* R---F */ +#define NV_NVLSTAT_TR03 0x00000093 /* R--4R */ +#define NV_NVLSTAT_TR03_DATA 31:0 /* R---F */ +#define NV_NVLSTAT_TR04 0x00000094 /* R--4R */ +#define NV_NVLSTAT_TR04_DATA 31:0 /* R---F */ +#define NV_NVLSTAT_TR05 0x00000095 /* R--4R */ +#define NV_NVLSTAT_TR05_DATA 31:0 /* R---F */ +#define NV_NVLSTAT_TR06 0x00000096 /* R--4R */ +#define NV_NVLSTAT_TR06_DATA 31:0 /* R---F */ +#define NV_NVLSTAT_TR07 0x00000097 /* R--4R */ +#define NV_NVLSTAT_TR07_DATA 31:0 /* R---F */ +#define NV_NVLSTAT_TR08 0x00000098 /* R--4R */ +#define NV_NVLSTAT_TR08_DATA 31:0 /* R---F */ +#define NV_NVLSTAT_TR09 0x00000099 /* R--4R */ +#define NV_NVLSTAT_TR09_DATA 31:0 /* R---F */ +#define NV_NVLSTAT_TR10 0x0000009a /* R--4R */ +#define NV_NVLSTAT_TR10_DATA 31:0 /* R---F */ +#define NV_NVLSTAT_TR11 0x0000009b /* R--4R */ +#define NV_NVLSTAT_TR11_DATA 31:0 /* R---F */ +#define NV_NVLSTAT_TR12 0x0000009c /* R--4R */ +#define NV_NVLSTAT_TR12_DATA 31:0 /* R---F */ +#define NV_NVLSTAT_TR13 0x0000009d /* R--4R */ +#define NV_NVLSTAT_TR13_DATA 31:0 /* R---F */ +#define NV_NVLSTAT_TR14 0x0000009e /* R--4R */ +#define NV_NVLSTAT_TR14_DATA 31:0 /* R---F */ +#define NV_NVLSTAT_TR15 0x0000009f /* R--4R */ +#define NV_NVLSTAT_TR15_DATA 31:0 /* R---F */ +#define NV_NVLSTAT_TR16 0x000000a0 /* R--4R */ +#define NV_NVLSTAT_TR16_L0FOM 15:0 /* R---F */ +#define NV_NVLSTAT_TR16_L1FOM 31:16 /* R---F */ +#define NV_NVLSTAT_TR17 0x000000a1 /* R--4R */ +#define NV_NVLSTAT_TR17_L2FOM 15:0 /* R---F */ +#define NV_NVLSTAT_TR17_L3FOM 31:16 /* R---F */ +#define NV_NVLSTAT_DB00 0x00000080 /* R--4R */ +#define NV_NVLSTAT_DB00_ERRORS_INJECTED_VALUE 30:0 /* R---F */ +#define NV_NVLSTAT_DB00_ERRORS_INJECTED_VALUE_SRCOVF 0x7fffffff /* R---V */ +#define NV_NVLSTAT_DB00_ERRORS_INJECTED_OVER 31:31 /* R---F */ +#define NV_NVLSTAT_DB00_ERRORS_INJECTED_OVER_OVER 0x1 /* R---V */ +#define NV_NVLSTAT_DB00_ERRORS_INJECTED_OVER_OKAY 0x0 /* R---V */ +#define NV_NVLSTAT_DB01 0x00000081 /* R--4R */ +#define NV_NVLSTAT_DB01_ERROR_COUNT_ERR_LANECRC_L3 31:24 /* R---F */ +#define NV_NVLSTAT_DB01_ERROR_COUNT_ERR_LANECRC_L2 23:16 /* R---F */ +#define NV_NVLSTAT_DB01_ERROR_COUNT_ERR_LANECRC_L1 15:8 /* R---F */ +#define NV_NVLSTAT_DB01_ERROR_COUNT_ERR_LANECRC_L0 7:0 /* R---F */ +#define NV_NVLSTAT_DB02 0x00000082 /* R--4R */ +#define NV_NVLSTAT_DB02_ERROR_COUNT_ERR_LANECRC_L7 31:24 /* R---F */ +#define NV_NVLSTAT_DB02_ERROR_COUNT_ERR_LANECRC_L6 23:16 /* R---F */ +#define NV_NVLSTAT_DB02_ERROR_COUNT_ERR_LANECRC_L5 15:8 /* R---F */ +#define NV_NVLSTAT_DB02_ERROR_COUNT_ERR_LANECRC_L4 7:0 /* R---F */ +#define NV_NVLSTAT_DB03 0x00000083 /* R--4R */ +#define NV_NVLSTAT_DB03_RXSLSM_ERR_CNTL_CLK_SWITCH_ERR 31:31 /* R---F */ +#define NV_NVLSTAT_DB03_RXSLSM_ERR_CNTL_OFF2SAFE_LINK_DET_ERR 2:2 /* R---F */ +#define NV_NVLSTAT_DB03_RXSLSM_ERR_CNTL_CONST_DET_ERR 1:1 /* R---F */ +#define NV_NVLSTAT_DB04 0x00000084 /* R--4R */ +#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_E2S_STROBE_NO_LD_ERR 23:23 /* R---F */ +#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_H2S_STROBE_NO_LD_ERR 22:22 /* R---F */ +#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_02S_STROBE_NO_LD_ERR 21:21 /* R---F */ +#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_E2S_SD_NO_LD_ERR 20:20 /* R---F */ +#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_H2S_SD_NO_LD_ERR 19:19 /* R---F */ +#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_O2S_SD_NO_LD_ERR 18:18 /* R---F */ +#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_RC_DEADLINE_ERR 15:15 /* R---F */ +#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_RC_TXPWR_ERR 14:14 /* R---F */ +#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_RC_RXPWR_ERR 13:13 /* R---F */ +#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_E2SAFE_LD_ERR 12:12 /* R---F */ +#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_SAFE_NO_LD_ERR 11:11 /* R---F */ +#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_FENCE_ERR 10:10 /* R---F */ +#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_HS2SAFE_LINK_DET_ERR 9:9 /* R---F */ +#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_TRAIN2SAFE_LINK_DET_ERR 8:8 /* R---F */ +#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_FIFO_SKEW_ERR 7:7 /* R---F */ +#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_SYM_ALIGN_END_ERR 6:6 /* R---F */ +#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_SYM_LOCK_ERR 5:5 /* R---F */ +#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_SCRAM_LOCK_ERR 4:4 /* R---F */ +#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_SAFE2NO_LINK_DET_ERR 3:3 /* R---F */ +#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_OFF2SAFE_LINK_DET_ERR 2:2 /* R---F */ +#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_CONST_DET_ERR 1:1 /* R---F */ +#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_FIFO_DRAIN_ERR 0:0 /* R---F */ +#define NV_NVLSTAT_DB05 0x00000085 /* R--4R */ +#define NV_NVLSTAT_DB05_TIMEOUT_LOG_SYM_LOCK_LANE 31:24 /* R---F */ +#define NV_NVLSTAT_DB05_TIMEOUT_LOG_SCRAM_LOCK_LANE 23:16 /* R---F */ +#define NV_NVLSTAT_DB05_TIMEOUT_LOG_CONST_DET_LANE 15:8 /* R---F */ +#define NV_NVLSTAT_DB05_TIMEOUT_LOG_FIFO_DRAIN_LANE 7:0 /* R---F */ +#define NV_NVLSTAT_DB06 0x00000086 /* R--4R */ +#define NV_NVLSTAT_DB06_TIMEOUT_LOG_SYM_ALIGN_END_LANE 31:24 /* R---F */ +#define NV_NVLSTAT_DB06_TIMEOUT_LOG_FIFO_SKEW_LANE 23:16 /* R---F */ +#define NV_NVLSTAT_DB07 0x00000087 /* R--4R */ +#define NV_NVLSTAT_DB07_FIFO_STATUS_RX_0_ENTRIES_USED_3 29:24 /* R---F */ +#define NV_NVLSTAT_DB07_FIFO_STATUS_RX_0_ENTRIES_USED_2 21:16 /* R---F */ +#define NV_NVLSTAT_DB07_FIFO_STATUS_RX_0_ENTRIES_USED_1 13:8 /* R---F */ +#define NV_NVLSTAT_DB07_FIFO_STATUS_RX_0_ENTRIES_USED_0 5:0 /* R---F */ +#define NV_NVLSTAT_DB08 0x00000088 /* R--4R */ +#define NV_NVLSTAT_DB08_FIFO_STATUS_RX_0_ENTRIES_USED_7 29:24 /* R---F */ +#define NV_NVLSTAT_DB08_FIFO_STATUS_RX_0_ENTRIES_USED_6 21:16 /* R---F */ +#define NV_NVLSTAT_DB08_FIFO_STATUS_RX_0_ENTRIES_USED_5 13:8 /* R---F */ +#define NV_NVLSTAT_DB08_FIFO_STATUS_RX_0_ENTRIES_USED_4 5:0 /* R---F */ +#define NV_NVLSTAT_DB09 0x00000089 /* R--4R */ +#define NV_NVLSTAT_DB09_SLSM_STATUS_RX_SURPRISE_LD_CNT_VALUE 30:0 /* R---F */ +#define NV_NVLSTAT_DB09_SLSM_STATUS_RX_SURPRISE_LD_CNT_VALUE_SRCOVF 0x000000ff /* R---V */ +#define NV_NVLSTAT_DB09_SLSM_STATUS_RX_SURPRISE_LD_CNT_OVER 31:31 /* R---F */ +#define NV_NVLSTAT_DB09_SLSM_STATUS_RX_SURPRISE_LD_CNT_OVER_OVER 0x1 /* R---V */ +#define NV_NVLSTAT_DB09_SLSM_STATUS_RX_SURPRISE_LD_CNT_OVER_OKAY 0x0 /* R---V */ +#define NV_NVLSTAT_DB10 0x0000008a /* R--4R */ +#define NV_NVLSTAT_DB10_DATA 31:0 /* R---F */ +#define NV_NVLSTAT_DB11 0x0000008b /* R--4R */ +#define NV_NVLSTAT_DB11_COUNT_PHY_REFRESH_PASS 15:0 /* R---F */ +#define NV_NVLSTAT_DB11_COUNT_PHY_REFRESH_FAIL 31:16 /* R---F */ +#define NV_NVLSTAT_MN00 0x000000ff /* R--4R */ +#define NV_NVLSTAT_MN00_LINK_INTR_SUBCODE 15:8 /* R---F */ +#define NV_NVLSTAT_MN00_LINK_INTR_CODE 7:0 /* R---F */ + +#define NV_MINION_INBAND_SEND_DATA_BUFFER_SIZE 7:0 +#define NV_MINION_INBAND_SEND_DATA_FLAGS 23:16 + +#endif // __ls10_dev_minion_ip_addendum_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_multicasttstate_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_multicasttstate_ip.h new file mode 100644 index 000000000..79fe067db --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_multicasttstate_ip.h @@ -0,0 +1,283 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_multicasttstate_ip_h__ +#define __ls10_dev_multicasttstate_ip_h__ +/* This file is autogenerated. Do not edit */ +#define NV_MULTICASTTSTATE 0x000027ff:0x00002000 /* RW--D */ +#define NV_MULTICASTTSTATE_ERR_STATUS_0 0x00002400 /* RW-4R */ +#define NV_MULTICASTTSTATE_ERR_STATUS_0_TAGPOOL_ECC_LIMIT_ERR 2:2 /* RWDVF */ +#define NV_MULTICASTTSTATE_ERR_STATUS_0_TAGPOOL_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_MULTICASTTSTATE_ERR_STATUS_0_TAGPOOL_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_MULTICASTTSTATE_ERR_STATUS_0_TAGPOOL_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_STATUS_0_TAGPOOL_ECC_DBE_ERR 3:3 /* RWDVF */ +#define NV_MULTICASTTSTATE_ERR_STATUS_0_TAGPOOL_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_MULTICASTTSTATE_ERR_STATUS_0_TAGPOOL_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_MULTICASTTSTATE_ERR_STATUS_0_TAGPOOL_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_STATUS_0_CRUMBSTORE_BUF_OVERWRITE_ERR 16:16 /* RWDVF */ +#define NV_MULTICASTTSTATE_ERR_STATUS_0_CRUMBSTORE_BUF_OVERWRITE_ERR__ONWRITE "oneToClear" /* */ +#define NV_MULTICASTTSTATE_ERR_STATUS_0_CRUMBSTORE_BUF_OVERWRITE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_MULTICASTTSTATE_ERR_STATUS_0_CRUMBSTORE_BUF_OVERWRITE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_LIMIT_ERR 18:18 /* RWDVF */ +#define NV_MULTICASTTSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_MULTICASTTSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_MULTICASTTSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_DBE_ERR 19:19 /* RWDVF */ +#define NV_MULTICASTTSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_MULTICASTTSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_MULTICASTTSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_STATUS_0_CRUMBSTORE_MCTO_ERR 20:20 /* RWDVF */ +#define NV_MULTICASTTSTATE_ERR_STATUS_0_CRUMBSTORE_MCTO_ERR__ONWRITE "oneToClear" /* */ +#define NV_MULTICASTTSTATE_ERR_STATUS_0_CRUMBSTORE_MCTO_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_MULTICASTTSTATE_ERR_STATUS_0_CRUMBSTORE_MCTO_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_LOG_EN_0 0x00002404 /* RW-4R */ +#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_LIMIT_ERR 2:2 /* RWEVF */ +#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_DBE_ERR 3:3 /* RWEVF */ +#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR 16:16 /* RWEVF */ +#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_LIMIT_ERR 18:18 /* RWEVF */ +#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_DBE_ERR 19:19 /* RWEVF */ +#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_CRUMBSTORE_MCTO_ERR 20:20 /* RWEVF */ +#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_CRUMBSTORE_MCTO_ERR__PROD 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_CRUMBSTORE_MCTO_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_ERR_LOG_EN_0_CRUMBSTORE_MCTO_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0 0x00002408 /* RW-4R */ +#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR 2:2 /* RWEVF */ +#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR 3:3 /* RWEVF */ +#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR 16:16 /* RWEVF */ +#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR 18:18 /* RWEVF */ +#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR 19:19 /* RWEVF */ +#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_MCTO_ERR 20:20 /* RWEVF */ +#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_MCTO_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_MCTO_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0 0x0000240c /* RW-4R */ +#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR 2:2 /* RWEVF */ +#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR 3:3 /* RWEVF */ +#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR 16:16 /* RWEVF */ +#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR 18:18 /* RWEVF */ +#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR 19:19 /* RWEVF */ +#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_MCTO_ERR 20:20 /* RWEVF */ +#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_MCTO_ERR__PROD 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_MCTO_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_MCTO_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_CORRECTABLE_REPORT_EN_0 0x00002410 /* RW-4R */ +#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0 0x00002414 /* RW-4R */ +#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_LIMIT_ERR 2:2 /* RWEVF */ +#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_DBE_ERR 3:3 /* RWEVF */ +#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR 16:16 /* RWEVF */ +#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_LIMIT_ERR 18:18 /* RWEVF */ +#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_DBE_ERR 19:19 /* RWEVF */ +#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_MCTO_ERR 20:20 /* RWEVF */ +#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_MCTO_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_MCTO_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_FIRST_0 0x0000241c /* RW-4R */ +#define NV_MULTICASTTSTATE_ERR_FIRST_0_TAGPOOL_ECC_LIMIT_ERR 2:2 /* RWDVF */ +#define NV_MULTICASTTSTATE_ERR_FIRST_0_TAGPOOL_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_MULTICASTTSTATE_ERR_FIRST_0_TAGPOOL_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_MULTICASTTSTATE_ERR_FIRST_0_TAGPOOL_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_FIRST_0_TAGPOOL_ECC_DBE_ERR 3:3 /* RWDVF */ +#define NV_MULTICASTTSTATE_ERR_FIRST_0_TAGPOOL_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_MULTICASTTSTATE_ERR_FIRST_0_TAGPOOL_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_MULTICASTTSTATE_ERR_FIRST_0_TAGPOOL_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_FIRST_0_CRUMBSTORE_BUF_OVERWRITE_ERR 16:16 /* RWDVF */ +#define NV_MULTICASTTSTATE_ERR_FIRST_0_CRUMBSTORE_BUF_OVERWRITE_ERR__ONWRITE "oneToClear" /* */ +#define NV_MULTICASTTSTATE_ERR_FIRST_0_CRUMBSTORE_BUF_OVERWRITE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_MULTICASTTSTATE_ERR_FIRST_0_CRUMBSTORE_BUF_OVERWRITE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_LIMIT_ERR 18:18 /* RWDVF */ +#define NV_MULTICASTTSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_MULTICASTTSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_MULTICASTTSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_DBE_ERR 19:19 /* RWDVF */ +#define NV_MULTICASTTSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_MULTICASTTSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_MULTICASTTSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_FIRST_0_CRUMBSTORE_MCTO_ERR 20:20 /* RWDVF */ +#define NV_MULTICASTTSTATE_ERR_FIRST_0_CRUMBSTORE_MCTO_ERR__ONWRITE "oneToClear" /* */ +#define NV_MULTICASTTSTATE_ERR_FIRST_0_CRUMBSTORE_MCTO_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_MULTICASTTSTATE_ERR_FIRST_0_CRUMBSTORE_MCTO_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_TIMESTAMP_LOG 0x00002450 /* R--4R */ +#define NV_MULTICASTTSTATE_ERR_TIMESTAMP_LOG_TIMESTAMP 23:0 /* R-DVF */ +#define NV_MULTICASTTSTATE_ERR_TIMESTAMP_LOG_TIMESTAMP_INIT 0x00000000 /* R-D-V */ +#define NV_MULTICASTTSTATE_ERR_ECC_CTRL 0x00002500 /* RW-4R */ +#define NV_MULTICASTTSTATE_ERR_ECC_CTRL_TAGPOOL_ECC_ENABLE 0:0 /* RWEVF */ +#define NV_MULTICASTTSTATE_ERR_ECC_CTRL_TAGPOOL_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_ECC_CTRL_TAGPOOL_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_ERR_ECC_CTRL_TAGPOOL_ECC_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_ECC_CTRL_CRUMBSTORE_ECC_ENABLE 1:1 /* RWEVF */ +#define NV_MULTICASTTSTATE_ERR_ECC_CTRL_CRUMBSTORE_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_ECC_CTRL_CRUMBSTORE_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_ERR_ECC_CTRL_CRUMBSTORE_ECC_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER 0x00002520 /* RW-4R */ +#define NV_MULTICASTTSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */ +#define NV_MULTICASTTSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */ +#define NV_MULTICASTTSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER_LIMIT 0x00002540 /* RW-4R */ +#define NV_MULTICASTTSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */ +#define NV_MULTICASTTSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */ +#define NV_MULTICASTTSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS 0x00002560 /* R--4R */ +#define NV_MULTICASTTSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_ERROR_ADDRESS 7:0 /* R-DVF */ +#define NV_MULTICASTTSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */ +#define NV_MULTICASTTSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_VALID 0x00002580 /* R--4R */ +#define NV_MULTICASTTSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */ +#define NV_MULTICASTTSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */ +#define NV_MULTICASTTSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */ +#define NV_MULTICASTTSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER 0x00002600 /* RW-4R */ +#define NV_MULTICASTTSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */ +#define NV_MULTICASTTSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */ +#define NV_MULTICASTTSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT 0x00002620 /* RW-4R */ +#define NV_MULTICASTTSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */ +#define NV_MULTICASTTSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */ +#define NV_MULTICASTTSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS 0x00002640 /* R--4R */ +#define NV_MULTICASTTSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_ERROR_ADDRESS 7:0 /* R-DVF */ +#define NV_MULTICASTTSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */ +#define NV_MULTICASTTSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID 0x00002660 /* R--4R */ +#define NV_MULTICASTTSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */ +#define NV_MULTICASTTSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */ +#define NV_MULTICASTTSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */ +#define NV_MULTICASTTSTATE_STAT_STALL_BUSY_CONTROL 0x00002700 /* RW-4R */ +#define NV_MULTICASTTSTATE_STAT_STALL_BUSY_CONTROL_ENABLE_TIMER 0:0 /* RWEVF */ +#define NV_MULTICASTTSTATE_STAT_STALL_BUSY_CONTROL_ENABLE_TIMER_DISABLE 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_STAT_STALL_BUSY_CONTROL_ENABLE_TIMER_ENABLE 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_STAT_STALL_BUSY_CONTROL_SNAP_ON_DEMAND 1:1 /* RWEVF */ +#define NV_MULTICASTTSTATE_STAT_STALL_BUSY_CONTROL_SNAP_ON_DEMAND__ONWRITE "oneToSet" /* */ +#define NV_MULTICASTTSTATE_STAT_STALL_BUSY_CONTROL_SNAP_ON_DEMAND_DISABLE 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_STAT_STALL_BUSY_CONTROL_SNAP_ON_DEMAND_ENABLE 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_STAT_WINDOW_0_HIGH 0x00002704 /* RW-4R */ +#define NV_MULTICASTTSTATE_STAT_WINDOW_0_HIGH_VALUE 15:0 /* RWEVF */ +#define NV_MULTICASTTSTATE_STAT_WINDOW_0_HIGH_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_STAT_WINDOW_0_LOW 0x00002708 /* RW-4R */ +#define NV_MULTICASTTSTATE_STAT_WINDOW_0_LOW_VALUE 31:0 /* RWEVF */ +#define NV_MULTICASTTSTATE_STAT_WINDOW_0_LOW_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_STAT_BUSY_TIMER_0_HIGH 0x0000270c /* RW-4R */ +#define NV_MULTICASTTSTATE_STAT_BUSY_TIMER_0_HIGH_VALUE 15:0 /* RWEVF */ +#define NV_MULTICASTTSTATE_STAT_BUSY_TIMER_0_HIGH_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_STAT_BUSY_TIMER_0_LOW 0x00002710 /* RW-4R */ +#define NV_MULTICASTTSTATE_STAT_BUSY_TIMER_0_LOW_VALUE 31:0 /* RWEVF */ +#define NV_MULTICASTTSTATE_STAT_BUSY_TIMER_0_LOW_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_STAT_STALL_TIMER_0_HIGH 0x00002714 /* RW-4R */ +#define NV_MULTICASTTSTATE_STAT_STALL_TIMER_0_HIGH_VALUE 15:0 /* RWEVF */ +#define NV_MULTICASTTSTATE_STAT_STALL_TIMER_0_HIGH_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_STAT_STALL_TIMER_0_LOW 0x00002718 /* RW-4R */ +#define NV_MULTICASTTSTATE_STAT_STALL_TIMER_0_LOW_VALUE 31:0 /* RWEVF */ +#define NV_MULTICASTTSTATE_STAT_STALL_TIMER_0_LOW_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_STAT_WINDOW_1_HIGH 0x0000271c /* RW-4R */ +#define NV_MULTICASTTSTATE_STAT_WINDOW_1_HIGH_VALUE 15:0 /* RWEVF */ +#define NV_MULTICASTTSTATE_STAT_WINDOW_1_HIGH_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_STAT_WINDOW_1_LOW 0x00002720 /* RW-4R */ +#define NV_MULTICASTTSTATE_STAT_WINDOW_1_LOW_VALUE 31:0 /* RWEVF */ +#define NV_MULTICASTTSTATE_STAT_WINDOW_1_LOW_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_STAT_BUSY_TIMER_1_HIGH 0x00002724 /* RW-4R */ +#define NV_MULTICASTTSTATE_STAT_BUSY_TIMER_1_HIGH_VALUE 15:0 /* RWEVF */ +#define NV_MULTICASTTSTATE_STAT_BUSY_TIMER_1_HIGH_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_STAT_BUSY_TIMER_1_LOW 0x00002728 /* RW-4R */ +#define NV_MULTICASTTSTATE_STAT_BUSY_TIMER_1_LOW_VALUE 31:0 /* RWEVF */ +#define NV_MULTICASTTSTATE_STAT_BUSY_TIMER_1_LOW_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_STAT_STALL_TIMER_1_HIGH 0x0000272c /* RW-4R */ +#define NV_MULTICASTTSTATE_STAT_STALL_TIMER_1_HIGH_VALUE 15:0 /* RWEVF */ +#define NV_MULTICASTTSTATE_STAT_STALL_TIMER_1_HIGH_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_STAT_STALL_TIMER_1_LOW 0x00002730 /* RW-4R */ +#define NV_MULTICASTTSTATE_STAT_STALL_TIMER_1_LOW_VALUE 31:0 /* RWEVF */ +#define NV_MULTICASTTSTATE_STAT_STALL_TIMER_1_LOW_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_STAT_RESIDENCY_CONTROL 0x00002734 /* RW-4R */ +#define NV_MULTICASTTSTATE_STAT_RESIDENCY_CONTROL_ENABLE_TIMER 0:0 /* RWEVF */ +#define NV_MULTICASTTSTATE_STAT_RESIDENCY_CONTROL_ENABLE_TIMER_DISABLE 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_STAT_RESIDENCY_CONTROL_ENABLE_TIMER_ENABLE 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_STAT_RESIDENCY_CONTROL_SNAP_ON_DEMAND 1:1 /* RWEVF */ +#define NV_MULTICASTTSTATE_STAT_RESIDENCY_CONTROL_SNAP_ON_DEMAND__ONWRITE "oneToSet" /* */ +#define NV_MULTICASTTSTATE_STAT_RESIDENCY_CONTROL_SNAP_ON_DEMAND_DISABLE 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_STAT_RESIDENCY_CONTROL_SNAP_ON_DEMAND_ENABLE 0x00000001 /* RW--V */ +#define NV_MULTICASTTSTATE_STAT_RESIDENCY_BIN_CTRL_LOW 0x00002738 /* RW-4R */ +#define NV_MULTICASTTSTATE_STAT_RESIDENCY_BIN_CTRL_LOW_LIMIT 23:0 /* RWEVF */ +#define NV_MULTICASTTSTATE_STAT_RESIDENCY_BIN_CTRL_LOW_LIMIT_INIT 0x0028b0ab /* RWE-V */ +#define NV_MULTICASTTSTATE_STAT_RESIDENCY_BIN_CTRL_HIGH 0x0000273c /* RW-4R */ +#define NV_MULTICASTTSTATE_STAT_RESIDENCY_BIN_CTRL_HIGH_LIMIT 23:0 /* RWEVF */ +#define NV_MULTICASTTSTATE_STAT_RESIDENCY_BIN_CTRL_HIGH_LIMIT_INIT 0x00cb7355 /* RWE-V */ +#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_CTRL 0x00002740 /* RW-4R */ +#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX 9:0 /* RWEVF */ +#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_MIN 0x00000000 /* RWE-V */ +#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_MAX 0x000002ff /* RW--V */ +#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_MCID_STRIDE 0x00000006 /* */ +#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_BIN_LOW_31_0 0x00000000 /* */ +#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_BIN_LOW_47_31 0x00000001 /* */ +#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_BIN_MED_31_0 0x00000002 /* */ +#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_BIN_MED_47_31 0x00000003 /* */ +#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_BIN_HIGH_31_0 0x00000004 /* */ +#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_BIN_HIGH_47_31 0x00000005 /* */ +#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_CTRL_AUTOINCR 31:31 /* RWEVF */ +#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_CTRL_AUTOINCR_OFF 0x00000000 /* RW--V */ +#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_CTRL_AUTOINCR_ON 0x00000001 /* RWE-V */ +#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_DATA 0x00002744 /* R--4R */ +#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_DATA_COUNT 31:0 /* R-XVF */ +#define NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_DATA__APERTURE_INDEX_OFFSET -0x00000004 /* */ +#endif // __ls10_dev_multicasttstate_ip_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_npg_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_npg_ip.h new file mode 100644 index 000000000..96ab447e2 --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_npg_ip.h @@ -0,0 +1,80 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_npg_ip_h__ +#define __ls10_dev_npg_ip_h__ +/* This file is autogenerated. Do not edit */ +#define NV_NPG 0x000007FFFF:0x00000000 /* RW--D */ +#define NV_NPG_CTRL_CLOCK_GATING 0x000000c8 /* RW-4R */ +#define NV_NPG_CTRL_CLOCK_GATING_CG1_SLCG 3:0 /* RWEVF */ +#define NV_NPG_CTRL_CLOCK_GATING_CG1_SLCG_INIT 0x0000000f /* RWE-V */ +#define NV_NPG_CTRL_CLOCK_GATING_CG1_SLCG__PROD 0x00000000 /* RW--V */ +#define NV_NPG_CTRL_CLOCK_GATING_CG1_BLCG 8:4 /* RWEVF */ +#define NV_NPG_CTRL_CLOCK_GATING_CG1_BLCG_INIT 0x0000001f /* RWE-V */ +#define NV_NPG_CTRL_CLOCK_GATING_CG1_BLCG__PROD 0x00000000 /* RW--V */ +#define NV_NPG_CONFIG_CLOCK_GATING 0x000000cc /* RW-4R */ +#define NV_NPG_CONFIG_CLOCK_GATING_CG1_BLCG_IDLE_DLY_CNT 5:0 /* RWEVF */ +#define NV_NPG_CONFIG_CLOCK_GATING_CG1_BLCG_IDLE_DLY_CNT_INIT 0x00000000 /* RWE-V */ +#define NV_NPG_CONFIG_CLOCK_GATING_CG1_BLCG_IDLE_CG_EN 6:6 /* RWEVF */ +#define NV_NPG_CONFIG_CLOCK_GATING_CG1_BLCG_IDLE_CG_EN_INIT 0x00000001 /* RWE-V */ +#define NV_NPG_CONFIG_CLOCK_GATING_CG1_BLCG_STALL_CG_EN 7:7 /* RWEVF */ +#define NV_NPG_CONFIG_CLOCK_GATING_CG1_BLCG_STALL_CG_EN_INIT 0x00000000 /* RWE-V */ +#define NV_NPG_CONFIG_CLOCK_GATING_CG1_BLCG_MONITOR_CG_EN 8:8 /* RWEVF */ +#define NV_NPG_CONFIG_CLOCK_GATING_CG1_BLCG_MONITOR_CG_EN_INIT 0x00000000 /* RWE-V */ +#define NV_NPG_CONFIG_CLOCK_GATING_CG1_BLCG_WAKEUP_DLY_CNT 12:9 /* RWEVF */ +#define NV_NPG_CONFIG_CLOCK_GATING_CG1_BLCG_WAKEUP_DLY_CNT_INIT 0x00000000 /* RWE-V */ +#define NV_NPG_NPG_INTERRUPT_STATUS 0x00000400 /* R--4R */ +#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_FNC_OR 0:0 /* R-EVF */ +#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_FNC_OR_INIT 0x00000000 /* R-E-V */ +#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_INT_STATUS 3:1 /* R-EVF */ +#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_INT_STATUS_INIT 0x00000000 /* R-E-V */ +#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_INT_STATUS_FATAL 0x00000001 /* R---V */ +#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_INT_STATUS_NONFATAL 0x00000002 /* R---V */ +#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_INT_STATUS_CORRECTABLE 0x00000004 /* R---V */ +#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_FNC_OR 4:4 /* R-EVF */ +#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_FNC_OR_INIT 0x00000000 /* R-E-V */ +#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_INT_STATUS 7:5 /* R-EVF */ +#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_INT_STATUS_INIT 0x00000000 /* R-E-V */ +#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_INT_STATUS_FATAL 0x00000001 /* R---V */ +#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_INT_STATUS_NONFATAL 0x00000002 /* R---V */ +#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_INT_STATUS_CORRECTABLE 0x00000004 /* R---V */ +#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_FNC_OR 8:8 /* R-EVF */ +#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_FNC_OR_INIT 0x00000000 /* R-E-V */ +#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_INT_STATUS 11:9 /* R-EVF */ +#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_INT_STATUS_INIT 0x00000000 /* R-E-V */ +#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_INT_STATUS_FATAL 0x00000001 /* R---V */ +#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_INT_STATUS_NONFATAL 0x00000002 /* R---V */ +#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_INT_STATUS_CORRECTABLE 0x00000004 /* R---V */ +#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_FNC_OR 12:12 /* R-EVF */ +#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_FNC_OR_INIT 0x00000000 /* R-E-V */ +#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_INT_STATUS 15:13 /* R-EVF */ +#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_INT_STATUS_INIT 0x00000000 /* R-E-V */ +#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_INT_STATUS_FATAL 0x00000001 /* R---V */ +#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_INT_STATUS_NONFATAL 0x00000002 /* R---V */ +#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_INT_STATUS_CORRECTABLE 0x00000004 /* R---V */ +#define NV_NPG_INTR_RETRIGGER(i) (0x00000580+(i)*0x4) /* RW-4A */ +#define NV_NPG_INTR_RETRIGGER__SIZE_1 3 /* */ +#define NV_NPG_INTR_RETRIGGER_TRIGGER 0:0 /* RWEVF */ +#define NV_NPG_INTR_RETRIGGER_TRIGGER__ONWRITE "oneToSet" /* */ +#define NV_NPG_INTR_RETRIGGER_TRIGGER_INIT 0x00000000 /* RWE-V */ +#endif // __ls10_dev_npg_ip_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_npgperf_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_npgperf_ip.h new file mode 100644 index 000000000..92f78f628 --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_npgperf_ip.h @@ -0,0 +1,40 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_npgperf_ip_h__ +#define __ls10_dev_npgperf_ip_h__ +/* This file is autogenerated. Do not edit */ +#define NV_NPGPERF 0x000003FF:0x00000000 /* RW--D */ +#define NV_NPGPERF_CTRL_CLOCK_GATING 0x000000c8 /* RW-4R */ +#define NV_NPGPERF_CTRL_CLOCK_GATING_CG1_SLCG 3:0 /* RWEVF */ +#define NV_NPGPERF_CTRL_CLOCK_GATING_CG1_SLCG_INIT 0x0000000f /* RWE-V */ +#define NV_NPGPERF_CTRL_CLOCK_GATING_CG1_SLCG__PROD 0x00000000 /* RW--V */ +#define NV_NPGPERF_PERF_CTRL_CLOCK_GATING 0x000000cc /* RW-4R */ +#define NV_NPGPERF_PERF_CTRL_CLOCK_GATING_CG1_SLCG 3:0 /* RWEVF */ +#define NV_NPGPERF_PERF_CTRL_CLOCK_GATING_CG1_SLCG_INIT 0x0000000f /* RWE-V */ +#define NV_NPGPERF_PERF_CTRL_CLOCK_GATING_CG1_SLCG__PROD 0x00000000 /* RW--V */ +#define NV_NPGPERF_PERF_CTRL_CLOCK_GATING_CONTEXT_FREEZE 7:4 /* RWEVF */ +#define NV_NPGPERF_PERF_CTRL_CLOCK_GATING_CONTEXT_FREEZE_DISABLED 0x00000000 /* RWE-V */ +#define NV_NPGPERF_PERF_CTRL_CLOCK_GATING_CONTEXT_FREEZE_ENABLED 0x00000001 /* RW--V */ +#define NV_NPGPERF_PERF_CTRL_CLOCK_GATING_CONTEXT_FREEZE__PROD 0x00000000 /* RW--V */ +#endif // __ls10_dev_npgperf_ip_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_nport_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_nport_ip.h new file mode 100644 index 000000000..b63932509 --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_nport_ip.h @@ -0,0 +1,470 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_nport_ip_h__ +#define __ls10_dev_nport_ip_h__ +/* This file is autogenerated. Do not edit */ +#define NV_NPORT 0x00007fff:0x00000000 /* RW--D */ +#define NV_NPORT_CTRL 0x00000040 /* RW-4R */ +#define NV_NPORT_CTRL_TRUNKLINKENB 0:0 /* RWEVF */ +#define NV_NPORT_CTRL_TRUNKLINKENB_TRUNKLINK 0x00000001 /* RW--V */ +#define NV_NPORT_CTRL_TRUNKLINKENB_ACCESSLINK 0x00000000 /* RWE-V */ +#define NV_NPORT_CTRL_TRUNKLINKENB__TPROD 0x00000001 /* RW--V */ +#define NV_NPORT_CTRL_EGDRAINENB 1:1 /* RWEVF */ +#define NV_NPORT_CTRL_EGDRAINENB_ENABLE 0x00000001 /* RW--V */ +#define NV_NPORT_CTRL_EGDRAINENB_DISABLE 0x00000000 /* RWE-V */ +#define NV_NPORT_CTRL_RTDRAINENB 2:2 /* RWEVF */ +#define NV_NPORT_CTRL_RTDRAINENB_ENABLE 0x00000001 /* RW--V */ +#define NV_NPORT_CTRL_RTDRAINENB_DISABLE 0x00000000 /* RWE-V */ +#define NV_NPORT_CTRL_SPARE 13:9 /* RWEVF */ +#define NV_NPORT_CTRL_SPARE_INIT 0x00000000 /* RWE-V */ +#define NV_NPORT_CTRL_ENROUTEDBI 16:16 /* RWEVF */ +#define NV_NPORT_CTRL_ENROUTEDBI_ENABLE 0x00000001 /* RWE-V */ +#define NV_NPORT_CTRL_ENROUTEDBI_DISABLE 0x00000000 /* RW--V */ +#define NV_NPORT_CTRL_ENEGRESSDBI 17:17 /* RWEVF */ +#define NV_NPORT_CTRL_ENEGRESSDBI_ENABLE 0x00000001 /* RWE-V */ +#define NV_NPORT_CTRL_ENEGRESSDBI_DISABLE 0x00000000 /* RW--V */ +#define NV_NPORT_CTRL_BUFFER_READY 0x00000044 /* RW-4R */ +#define NV_NPORT_CTRL_BUFFER_READY_BUFFERRDY 0:0 /* RWEVF */ +#define NV_NPORT_CTRL_BUFFER_READY_BUFFERRDY_ENABLE 0x00000001 /* RW--V */ +#define NV_NPORT_CTRL_BUFFER_READY_BUFFERRDY_DISABLE 0x00000000 /* RWE-V */ +#define NV_NPORT_CTRL_STOP 0x00000048 /* RW-4R */ +#define NV_NPORT_CTRL_STOP_INGRESS_STOP 0:0 /* RWEVF */ +#define NV_NPORT_CTRL_STOP_INGRESS_STOP_STOP 0x00000001 /* RW--V */ +#define NV_NPORT_CTRL_STOP_INGRESS_STOP_ALLOWTRAFFIC 0x00000000 /* RWE-V */ +#define NV_NPORT_CTRL_STOP_EGRESS_STOP 8:8 /* RWEVF */ +#define NV_NPORT_CTRL_STOP_EGRESS_STOP_STOP 0x00000001 /* RW--V */ +#define NV_NPORT_CTRL_STOP_EGRESS_STOP_ALLOWTRAFFIC 0x00000000 /* RWE-V */ +#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC 23:16 /* RWEVF */ +#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_ALLOWTRAFFIC 0x00000000 /* RWE-V */ +#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_STOPVC0 0x00000001 /* RW--V */ +#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_STOPVC1 0x00000002 /* RW--V */ +#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_STOPVC2 0x00000004 /* RW--V */ +#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_STOPVC3 0x00000008 /* RW--V */ +#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_STOPVC4 0x00000010 /* RW--V */ +#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_STOPVC5 0x00000020 /* RW--V */ +#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_STOPVC6 0x00000040 /* RW--V */ +#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_STOPVC7 0x00000080 /* RW--V */ +#define NV_NPORT_INITIALIZATION 0x0000004c /* RW-4R */ +#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_0 0:0 /* RWEVF */ +#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_0__ONWRITE "oneToClear" /* */ +#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_0_INIT 0x00000000 /* RWE-V */ +#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_0_HWINIT 0x00000001 /* RW--V */ +#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_1 1:1 /* RWEVF */ +#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_1__ONWRITE "oneToClear" /* */ +#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_1_INIT 0x00000000 /* RWE-V */ +#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_1_HWINIT 0x00000001 /* RW--V */ +#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_2 2:2 /* RWEVF */ +#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_2__ONWRITE "oneToClear" /* */ +#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_2_INIT 0x00000000 /* RWE-V */ +#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_2_HWINIT 0x00000001 /* RW--V */ +#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_3 3:3 /* RWEVF */ +#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_3__ONWRITE "oneToClear" /* */ +#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_3_INIT 0x00000000 /* RWE-V */ +#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_3_HWINIT 0x00000001 /* RW--V */ +#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_4 4:4 /* RWEVF */ +#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_4__ONWRITE "oneToClear" /* */ +#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_4_INIT 0x00000000 /* RWE-V */ +#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_4_HWINIT 0x00000001 /* RW--V */ +#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_5 5:5 /* RWEVF */ +#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_5__ONWRITE "oneToClear" /* */ +#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_5_INIT 0x00000000 /* RWE-V */ +#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_5_HWINIT 0x00000001 /* RW--V */ +#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_6 6:6 /* RWEVF */ +#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_6__ONWRITE "oneToClear" /* */ +#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_6_INIT 0x00000000 /* RWE-V */ +#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_6_HWINIT 0x00000001 /* RW--V */ +#define NV_NPORT_INITIALIZATION_LINKTABLEINIT 8:8 /* RWEVF */ +#define NV_NPORT_INITIALIZATION_LINKTABLEINIT__ONWRITE "oneToClear" /* */ +#define NV_NPORT_INITIALIZATION_LINKTABLEINIT_INIT 0x00000000 /* RWE-V */ +#define NV_NPORT_INITIALIZATION_LINKTABLEINIT_HWINIT 0x00000001 /* RW--V */ +#define NV_NPORT_INITIALIZATION_REMAPTABINIT 9:9 /* RWEVF */ +#define NV_NPORT_INITIALIZATION_REMAPTABINIT__ONWRITE "oneToClear" /* */ +#define NV_NPORT_INITIALIZATION_REMAPTABINIT_INIT 0x00000000 /* RWE-V */ +#define NV_NPORT_INITIALIZATION_REMAPTABINIT_HWINIT 0x00000001 /* RW--V */ +#define NV_NPORT_INITIALIZATION_RIDTABINIT 10:10 /* RWEVF */ +#define NV_NPORT_INITIALIZATION_RIDTABINIT__ONWRITE "oneToClear" /* */ +#define NV_NPORT_INITIALIZATION_RIDTABINIT_INIT 0x00000000 /* RWE-V */ +#define NV_NPORT_INITIALIZATION_RIDTABINIT_HWINIT 0x00000001 /* RW--V */ +#define NV_NPORT_INITIALIZATION_RLANTABINIT 11:11 /* RWEVF */ +#define NV_NPORT_INITIALIZATION_RLANTABINIT__ONWRITE "oneToClear" /* */ +#define NV_NPORT_INITIALIZATION_RLANTABINIT_INIT 0x00000000 /* RWE-V */ +#define NV_NPORT_INITIALIZATION_RLANTABINIT_HWINIT 0x00000001 /* RW--V */ +#define NV_NPORT_INITIALIZATION_MCREMAPTABINIT 12:12 /* RWEVF */ +#define NV_NPORT_INITIALIZATION_MCREMAPTABINIT__ONWRITE "oneToClear" /* */ +#define NV_NPORT_INITIALIZATION_MCREMAPTABINIT_INIT 0x00000000 /* RWE-V */ +#define NV_NPORT_INITIALIZATION_MCREMAPTABINIT_HWINIT 0x00000001 /* RW--V */ +#define NV_NPORT_INITIALIZATION_MCTAGSTATEINIT 13:13 /* RWEVF */ +#define NV_NPORT_INITIALIZATION_MCTAGSTATEINIT__ONWRITE "oneToClear" /* */ +#define NV_NPORT_INITIALIZATION_MCTAGSTATEINIT_INIT 0x00000000 /* RWE-V */ +#define NV_NPORT_INITIALIZATION_MCTAGSTATEINIT_HWINIT 0x00000001 /* RW--V */ +#define NV_NPORT_INITIALIZATION_RDTAGSTATEINIT 14:14 /* RWEVF */ +#define NV_NPORT_INITIALIZATION_RDTAGSTATEINIT__ONWRITE "oneToClear" /* */ +#define NV_NPORT_INITIALIZATION_RDTAGSTATEINIT_INIT 0x00000000 /* RWE-V */ +#define NV_NPORT_INITIALIZATION_RDTAGSTATEINIT_HWINIT 0x00000001 /* RW--V */ +#define NV_NPORT_INITIALIZATION_MCREDSGTINIT 15:15 /* RWEVF */ +#define NV_NPORT_INITIALIZATION_MCREDSGTINIT__ONWRITE "oneToClear" /* */ +#define NV_NPORT_INITIALIZATION_MCREDSGTINIT_INIT 0x00000000 /* RWE-V */ +#define NV_NPORT_INITIALIZATION_MCREDSGTINIT_HWINIT 0x00000001 /* RW--V */ +#define NV_NPORT_INITIALIZATION_MCREDBUFINIT 16:16 /* RWEVF */ +#define NV_NPORT_INITIALIZATION_MCREDBUFINIT__ONWRITE "oneToClear" /* */ +#define NV_NPORT_INITIALIZATION_MCREDBUFINIT_INIT 0x00000000 /* RWE-V */ +#define NV_NPORT_INITIALIZATION_MCREDBUFINIT_HWINIT 0x00000001 /* RW--V */ +#define NV_NPORT_INITIALIZATION_MCRIDINIT 17:17 /* RWEVF */ +#define NV_NPORT_INITIALIZATION_MCRIDINIT__ONWRITE "oneToClear" /* */ +#define NV_NPORT_INITIALIZATION_MCRIDINIT_INIT 0x00000000 /* RWE-V */ +#define NV_NPORT_INITIALIZATION_MCRIDINIT_HWINIT 0x00000001 /* RW--V */ +#define NV_NPORT_INITIALIZATION_EXTMCRIDINIT 18:18 /* RWEVF */ +#define NV_NPORT_INITIALIZATION_EXTMCRIDINIT__ONWRITE "oneToClear" /* */ +#define NV_NPORT_INITIALIZATION_EXTMCRIDINIT_INIT 0x00000000 /* RWE-V */ +#define NV_NPORT_INITIALIZATION_EXTMCRIDINIT_HWINIT 0x00000001 /* RW--V */ +#define NV_NPORT_CTRL_SLCG 0x00000050 /* RW-4R */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_INGRESS 0:0 /* RWEVF */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_INGRESS_ENABLE 0x00000001 /* RWE-V */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_INGRESS_DISABLE 0x00000000 /* RW--V */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_INGRESS__PROD 0x00000000 /* RW--V */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_ROUTE 1:1 /* RWEVF */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_ROUTE_ENABLE 0x00000001 /* RWE-V */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_ROUTE_DISABLE 0x00000000 /* RW--V */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_ROUTE__PROD 0x00000000 /* RW--V */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_EGRESS 2:2 /* RWEVF */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_EGRESS_ENABLE 0x00000001 /* RWE-V */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_EGRESS_DISABLE 0x00000000 /* RW--V */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_EGRESS__PROD 0x00000000 /* RW--V */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_STRACK 3:3 /* RWEVF */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_STRACK_ENABLE 0x00000001 /* RWE-V */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_STRACK_DISABLE 0x00000000 /* RW--V */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_STRACK__PROD 0x00000000 /* RW--V */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_TAGSTATE 4:4 /* RWEVF */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_TAGSTATE_ENABLE 0x00000001 /* RWE-V */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_TAGSTATE_DISABLE 0x00000000 /* RW--V */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_TAGSTATE__PROD 0x00000000 /* RW--V */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_TREX 5:5 /* RWEVF */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_TREX_ENABLE 0x00000001 /* RWE-V */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_TREX_DISABLE 0x00000000 /* RW--V */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_TREX__PROD 0x00000000 /* RW--V */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_MCTAGSTATE 6:6 /* RWEVF */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_MCTAGSTATE_ENABLE 0x00000001 /* RWE-V */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_MCTAGSTATE_DISABLE 0x00000000 /* RW--V */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_MCTAGSTATE__PROD 0x00000000 /* RW--V */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_RDTAGSTATE 7:7 /* RWEVF */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_RDTAGSTATE_ENABLE 0x00000001 /* RWE-V */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_RDTAGSTATE_DISABLE 0x00000000 /* RW--V */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_RDTAGSTATE__PROD 0x00000000 /* RW--V */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_WATCHPOINT 31:31 /* RWEVF */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_WATCHPOINT_ENABLE 0x00000001 /* RWE-V */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_WATCHPOINT_DISABLE 0x00000000 /* RW--V */ +#define NV_NPORT_CTRL_SLCG_DIS_CG_WATCHPOINT__PROD 0x00000000 /* RW--V */ +#define NV_NPORT_REQLINKID 0x00000054 /* RW-4R */ +#define NV_NPORT_REQLINKID_REQROUTINGID 8:0 /* RWEVF */ +#define NV_NPORT_REQLINKID_REQROUTINGID_INIT 0x00000000 /* RWE-V */ +#define NV_NPORT_REQLINKID_REQROUTINGID_UPPER 10:9 /* RWEVF */ +#define NV_NPORT_REQLINKID_REQROUTINGID_UPPER_INIT 0x00000000 /* RWE-V */ +#define NV_NPORT_REQLINKID_REQROUTINGLAN 18:15 /* RWEVF */ +#define NV_NPORT_REQLINKID_REQROUTINGLAN_INIT 0x00000000 /* RWE-V */ +#define NV_NPORT_CONTAIN_AND_DRAIN 0x0000005c /* RW-4R */ +#define NV_NPORT_CONTAIN_AND_DRAIN_CLEAR 18:18 /* RWIVF */ +#define NV_NPORT_CONTAIN_AND_DRAIN_CLEAR__ONWRITE "oneToClear" /* */ +#define NV_NPORT_CONTAIN_AND_DRAIN_CLEAR_ENABLE 0x00000001 /* RW--V */ +#define NV_NPORT_CONTAIN_AND_DRAIN_CLEAR_DISABLE 0x00000000 /* RWI-V */ +#define NV_NPORT_CONTAIN_AND_DRAIN_DIRTY 19:19 /* R-IVF */ +#define NV_NPORT_CONTAIN_AND_DRAIN_DIRTY_DIRTY 0x00000001 /* R---V */ +#define NV_NPORT_CONTAIN_AND_DRAIN_DIRTY_CLEAN 0x00000000 /* R-I-V */ +#define NV_NPORT_SRC_PORT_TYPE0 0x00000074 /* RW-4R */ +#define NV_NPORT_SRC_PORT_TYPE0_TRUNKPORT 31:0 /* RWEVF */ +#define NV_NPORT_SRC_PORT_TYPE0_TRUNKPORT_TRUNKPORT 0x00000001 /* RW--V */ +#define NV_NPORT_SRC_PORT_TYPE0_TRUNKPORT_ACCESSPORT 0x00000000 /* RWE-V */ +#define NV_NPORT_SRC_PORT_TYPE1 0x00000078 /* RW-4R */ +#define NV_NPORT_SRC_PORT_TYPE1_TRUNKPORT 31:0 /* RWEVF */ +#define NV_NPORT_SRC_PORT_TYPE1_TRUNKPORT_TRUNKPORT 0x00000001 /* RW--V */ +#define NV_NPORT_SRC_PORT_TYPE1_TRUNKPORT_ACCESSPORT 0x00000000 /* RWE-V */ +#define NV_NPORT_PORTSTAT_CONTROL 0x00000100 /* RW-4R */ +#define NV_NPORT_PORTSTAT_CONTROL_RANGESELECT 3:0 /* RWEVF */ +#define NV_NPORT_PORTSTAT_CONTROL_RANGESELECT_BITS13TO0 0x00000000 /* RWE-V */ +#define NV_NPORT_PORTSTAT_CONTROL_RANGESELECT_BITS15TO2 0x00000001 /* RW--V */ +#define NV_NPORT_PORTSTAT_CONTROL_RANGESELECT_BITS17TO4 0x00000002 /* RW--V */ +#define NV_NPORT_PORTSTAT_CONTROL_RANGESELECT_BITS19TO6 0x00000003 /* RW--V */ +#define NV_NPORT_PORTSTAT_CONTROL_RANGESELECT_BITS21TO8 0x00000004 /* RW--V */ +#define NV_NPORT_PORTSTAT_CONTROL_RANGESELECT_BITS23TO10 0x00000005 /* RW--V */ +#define NV_NPORT_PORTSTAT_SNAP_CONTROL 0x00000104 /* RW-4R */ +#define NV_NPORT_PORTSTAT_SNAP_CONTROL_STARTCOUNTER 0:0 /* RWEVF */ +#define NV_NPORT_PORTSTAT_SNAP_CONTROL_STARTCOUNTER_ENABLE 0x00000001 /* RW--V */ +#define NV_NPORT_PORTSTAT_SNAP_CONTROL_STARTCOUNTER_DISABLE 0x00000000 /* RWE-V */ +#define NV_NPORT_PORTSTAT_SNAP_CONTROL_SNAPONDEMAND 4:4 /* RWEVF */ +#define NV_NPORT_PORTSTAT_SNAP_CONTROL_SNAPONDEMAND_ENABLE 0x00000001 /* RW--V */ +#define NV_NPORT_PORTSTAT_SNAP_CONTROL_SNAPONDEMAND_DISABLE 0x00000000 /* RWE-V */ +#define NV_NPORT_PORTSTAT_LIMIT_LOW_0 0x00000108 /* RW-4R */ +#define NV_NPORT_PORTSTAT_LIMIT_LOW_0_LIMIT 23:0 /* RWEVF */ +#define NV_NPORT_PORTSTAT_LIMIT_LOW_0_LIMIT_INIT 0x000000c0 /* RWE-V */ +#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_0 0x0000010c /* RW-4R */ +#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_0_LIMIT 23:0 /* RWEVF */ +#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_0_LIMIT_INIT 0x00000140 /* RWE-V */ +#define NV_NPORT_PORTSTAT_LIMIT_HIGH_0 0x00000110 /* RW-4R */ +#define NV_NPORT_PORTSTAT_LIMIT_HIGH_0_LIMIT 23:0 /* RWEVF */ +#define NV_NPORT_PORTSTAT_LIMIT_HIGH_0_LIMIT_INIT 0x00000680 /* RWE-V */ +#define NV_NPORT_PORTSTAT_PACKET_COUNT_0_0 0x00000114 /* RW-4R */ +#define NV_NPORT_PORTSTAT_PACKET_COUNT_0_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_PACKET_COUNT_0_1 0x00000118 /* RW-4R */ +#define NV_NPORT_PORTSTAT_PACKET_COUNT_0_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_LOW_0_0 0x0000011c /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_LOW_0_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_LOW_0_1 0x00000120 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_LOW_0_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_0_0 0x00000124 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_0_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_0_1 0x00000128 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_0_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_HIGH_0_0 0x0000012c /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_HIGH_0_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_HIGH_0_1 0x00000130 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_HIGH_0_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_PANIC_0_0 0x00000134 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_PANIC_0_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_PANIC_0_1 0x00000138 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_PANIC_0_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_LIMIT_LOW_1 0x0000013c /* RW-4R */ +#define NV_NPORT_PORTSTAT_LIMIT_LOW_1_LIMIT 23:0 /* RWEVF */ +#define NV_NPORT_PORTSTAT_LIMIT_LOW_1_LIMIT_INIT 0x000000c0 /* RWE-V */ +#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_1 0x00000140 /* RW-4R */ +#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_1_LIMIT 23:0 /* RWEVF */ +#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_1_LIMIT_INIT 0x00000140 /* RWE-V */ +#define NV_NPORT_PORTSTAT_LIMIT_HIGH_1 0x00000144 /* RW-4R */ +#define NV_NPORT_PORTSTAT_LIMIT_HIGH_1_LIMIT 23:0 /* RWEVF */ +#define NV_NPORT_PORTSTAT_LIMIT_HIGH_1_LIMIT_INIT 0x00000680 /* RWE-V */ +#define NV_NPORT_PORTSTAT_PACKET_COUNT_1_0 0x00000148 /* RW-4R */ +#define NV_NPORT_PORTSTAT_PACKET_COUNT_1_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_PACKET_COUNT_1_1 0x0000014c /* RW-4R */ +#define NV_NPORT_PORTSTAT_PACKET_COUNT_1_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_LOW_1_0 0x00000150 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_LOW_1_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_LOW_1_1 0x00000154 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_LOW_1_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_1_0 0x00000158 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_1_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_1_1 0x0000015c /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_1_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_HIGH_1_0 0x00000160 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_HIGH_1_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_HIGH_1_1 0x00000164 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_HIGH_1_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_PANIC_1_0 0x00000168 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_PANIC_1_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_PANIC_1_1 0x0000016c /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_PANIC_1_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_LIMIT_LOW_2 0x00000170 /* RW-4R */ +#define NV_NPORT_PORTSTAT_LIMIT_LOW_2_LIMIT 23:0 /* RWEVF */ +#define NV_NPORT_PORTSTAT_LIMIT_LOW_2_LIMIT_INIT 0x000000c0 /* RWE-V */ +#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_2 0x00000174 /* RW-4R */ +#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_2_LIMIT 23:0 /* RWEVF */ +#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_2_LIMIT_INIT 0x00000140 /* RWE-V */ +#define NV_NPORT_PORTSTAT_LIMIT_HIGH_2 0x00000178 /* RW-4R */ +#define NV_NPORT_PORTSTAT_LIMIT_HIGH_2_LIMIT 23:0 /* RWEVF */ +#define NV_NPORT_PORTSTAT_LIMIT_HIGH_2_LIMIT_INIT 0x00000680 /* RWE-V */ +#define NV_NPORT_PORTSTAT_PACKET_COUNT_2_0 0x0000017c /* RW-4R */ +#define NV_NPORT_PORTSTAT_PACKET_COUNT_2_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_PACKET_COUNT_2_1 0x00000180 /* RW-4R */ +#define NV_NPORT_PORTSTAT_PACKET_COUNT_2_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_LOW_2_0 0x00000184 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_LOW_2_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_LOW_2_1 0x00000188 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_LOW_2_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_2_0 0x0000018c /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_2_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_2_1 0x00000190 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_2_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_HIGH_2_0 0x00000194 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_HIGH_2_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_HIGH_2_1 0x00000198 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_HIGH_2_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_PANIC_2_0 0x0000019c /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_PANIC_2_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_PANIC_2_1 0x000001a0 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_PANIC_2_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_LIMIT_LOW_3 0x000001a4 /* RW-4R */ +#define NV_NPORT_PORTSTAT_LIMIT_LOW_3_LIMIT 23:0 /* RWEVF */ +#define NV_NPORT_PORTSTAT_LIMIT_LOW_3_LIMIT_INIT 0x000000c0 /* RWE-V */ +#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_3 0x000001a8 /* RW-4R */ +#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_3_LIMIT 23:0 /* RWEVF */ +#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_3_LIMIT_INIT 0x00000140 /* RWE-V */ +#define NV_NPORT_PORTSTAT_LIMIT_HIGH_3 0x000001ac /* RW-4R */ +#define NV_NPORT_PORTSTAT_LIMIT_HIGH_3_LIMIT 23:0 /* RWEVF */ +#define NV_NPORT_PORTSTAT_LIMIT_HIGH_3_LIMIT_INIT 0x00000680 /* RWE-V */ +#define NV_NPORT_PORTSTAT_PACKET_COUNT_3_0 0x000001b0 /* RW-4R */ +#define NV_NPORT_PORTSTAT_PACKET_COUNT_3_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_PACKET_COUNT_3_1 0x000001b4 /* RW-4R */ +#define NV_NPORT_PORTSTAT_PACKET_COUNT_3_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_LOW_3_0 0x000001b8 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_LOW_3_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_LOW_3_1 0x000001bc /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_LOW_3_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_3_0 0x000001c0 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_3_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_3_1 0x000001c4 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_3_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_HIGH_3_0 0x000001c8 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_HIGH_3_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_HIGH_3_1 0x000001cc /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_HIGH_3_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_PANIC_3_0 0x000001d0 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_PANIC_3_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_PANIC_3_1 0x000001d4 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_PANIC_3_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_LIMIT_LOW_4 0x000001d8 /* RW-4R */ +#define NV_NPORT_PORTSTAT_LIMIT_LOW_4_LIMIT 23:0 /* RWEVF */ +#define NV_NPORT_PORTSTAT_LIMIT_LOW_4_LIMIT_INIT 0x000000c0 /* RWE-V */ +#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_4 0x000001dc /* RW-4R */ +#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_4_LIMIT 23:0 /* RWEVF */ +#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_4_LIMIT_INIT 0x00000140 /* RWE-V */ +#define NV_NPORT_PORTSTAT_LIMIT_HIGH_4 0x000001e0 /* RW-4R */ +#define NV_NPORT_PORTSTAT_LIMIT_HIGH_4_LIMIT 23:0 /* RWEVF */ +#define NV_NPORT_PORTSTAT_LIMIT_HIGH_4_LIMIT_INIT 0x00000680 /* RWE-V */ +#define NV_NPORT_PORTSTAT_PACKET_COUNT_4_0 0x000001e4 /* RW-4R */ +#define NV_NPORT_PORTSTAT_PACKET_COUNT_4_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_PACKET_COUNT_4_1 0x000001e8 /* RW-4R */ +#define NV_NPORT_PORTSTAT_PACKET_COUNT_4_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_LOW_4_0 0x000001ec /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_LOW_4_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_LOW_4_1 0x000001f0 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_LOW_4_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_4_0 0x000001f4 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_4_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_4_1 0x000001f8 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_4_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_HIGH_4_0 0x000001fc /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_HIGH_4_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_HIGH_4_1 0x00000200 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_HIGH_4_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_PANIC_4_0 0x00000204 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_PANIC_4_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_PANIC_4_1 0x00000208 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_PANIC_4_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_LIMIT_LOW_5 0x0000020c /* RW-4R */ +#define NV_NPORT_PORTSTAT_LIMIT_LOW_5_LIMIT 23:0 /* RWEVF */ +#define NV_NPORT_PORTSTAT_LIMIT_LOW_5_LIMIT_INIT 0x000000c0 /* RWE-V */ +#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_5 0x00000210 /* RW-4R */ +#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_5_LIMIT 23:0 /* RWEVF */ +#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_5_LIMIT_INIT 0x00000140 /* RWE-V */ +#define NV_NPORT_PORTSTAT_LIMIT_HIGH_5 0x00000214 /* RW-4R */ +#define NV_NPORT_PORTSTAT_LIMIT_HIGH_5_LIMIT 23:0 /* RWEVF */ +#define NV_NPORT_PORTSTAT_LIMIT_HIGH_5_LIMIT_INIT 0x00000680 /* RWE-V */ +#define NV_NPORT_PORTSTAT_PACKET_COUNT_5_0 0x00000218 /* RW-4R */ +#define NV_NPORT_PORTSTAT_PACKET_COUNT_5_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_PACKET_COUNT_5_1 0x0000021c /* RW-4R */ +#define NV_NPORT_PORTSTAT_PACKET_COUNT_5_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_LOW_5_0 0x00000220 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_LOW_5_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_LOW_5_1 0x00000224 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_LOW_5_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_5_0 0x00000228 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_5_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_5_1 0x0000022c /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_5_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_HIGH_5_0 0x00000230 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_HIGH_5_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_HIGH_5_1 0x00000234 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_HIGH_5_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_PANIC_5_0 0x00000238 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_PANIC_5_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_PANIC_5_1 0x0000023c /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_PANIC_5_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_LIMIT_LOW_6 0x00000240 /* RW-4R */ +#define NV_NPORT_PORTSTAT_LIMIT_LOW_6_LIMIT 23:0 /* RWEVF */ +#define NV_NPORT_PORTSTAT_LIMIT_LOW_6_LIMIT_INIT 0x000000c0 /* RWE-V */ +#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_6 0x00000244 /* RW-4R */ +#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_6_LIMIT 23:0 /* RWEVF */ +#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_6_LIMIT_INIT 0x00000140 /* RWE-V */ +#define NV_NPORT_PORTSTAT_LIMIT_HIGH_6 0x00000248 /* RW-4R */ +#define NV_NPORT_PORTSTAT_LIMIT_HIGH_6_LIMIT 23:0 /* RWEVF */ +#define NV_NPORT_PORTSTAT_LIMIT_HIGH_6_LIMIT_INIT 0x00000680 /* RWE-V */ +#define NV_NPORT_PORTSTAT_PACKET_COUNT_6_0 0x0000024c /* RW-4R */ +#define NV_NPORT_PORTSTAT_PACKET_COUNT_6_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_PACKET_COUNT_6_1 0x00000250 /* RW-4R */ +#define NV_NPORT_PORTSTAT_PACKET_COUNT_6_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_LOW_6_0 0x00000254 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_LOW_6_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_LOW_6_1 0x00000258 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_LOW_6_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_6_0 0x0000025c /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_6_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_6_1 0x00000260 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_6_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_HIGH_6_0 0x00000264 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_HIGH_6_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_HIGH_6_1 0x00000268 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_HIGH_6_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_PANIC_6_0 0x0000026c /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_PANIC_6_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_PANIC_6_1 0x00000270 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_PANIC_6_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_LIMIT_LOW_7 0x00000274 /* RW-4R */ +#define NV_NPORT_PORTSTAT_LIMIT_LOW_7_LIMIT 23:0 /* RWEVF */ +#define NV_NPORT_PORTSTAT_LIMIT_LOW_7_LIMIT_INIT 0x000000c0 /* RWE-V */ +#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_7 0x00000278 /* RW-4R */ +#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_7_LIMIT 23:0 /* RWEVF */ +#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_7_LIMIT_INIT 0x00000140 /* RWE-V */ +#define NV_NPORT_PORTSTAT_LIMIT_HIGH_7 0x0000027c /* RW-4R */ +#define NV_NPORT_PORTSTAT_LIMIT_HIGH_7_LIMIT 23:0 /* RWEVF */ +#define NV_NPORT_PORTSTAT_LIMIT_HIGH_7_LIMIT_INIT 0x00000680 /* RWE-V */ +#define NV_NPORT_PORTSTAT_PACKET_COUNT_7_0 0x00000280 /* RW-4R */ +#define NV_NPORT_PORTSTAT_PACKET_COUNT_7_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_PACKET_COUNT_7_1 0x00000284 /* RW-4R */ +#define NV_NPORT_PORTSTAT_PACKET_COUNT_7_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_LOW_7_0 0x00000288 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_LOW_7_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_LOW_7_1 0x0000028c /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_LOW_7_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_7_0 0x00000290 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_7_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_7_1 0x00000294 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_7_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_HIGH_7_0 0x00000298 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_HIGH_7_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_HIGH_7_1 0x0000029c /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_HIGH_7_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_PANIC_7_0 0x000002a0 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_PANIC_7_0_PACKETCOUNT 31:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_COUNT_PANIC_7_1 0x000002a4 /* RW-4R */ +#define NV_NPORT_PORTSTAT_COUNT_PANIC_7_1_PACKETCOUNT 15:0 /* RWXVF */ +#define NV_NPORT_PORTSTAT_SOURCE_FILTER_0 0x000002a8 /* RW-4R */ +#define NV_NPORT_PORTSTAT_SOURCE_FILTER_0_SRCFILTERBIT 31:0 /* RWEVF */ +#define NV_NPORT_PORTSTAT_SOURCE_FILTER_0_SRCFILTERBIT_INIT 0x00000000 /* RWE-V */ +#define NV_NPORT_PORTSTAT_SOURCE_FILTER_1 0x000002ac /* RW-4R */ +#define NV_NPORT_PORTSTAT_SOURCE_FILTER_1_SRCFILTERBIT 31:0 /* RWEVF */ +#define NV_NPORT_PORTSTAT_SOURCE_FILTER_1_SRCFILTERBIT_INIT 0x00000000 /* RWE-V */ +#define NV_NPORT_ERR_CONTROL_COMMON_NPORT 0x00000470 /* RW-4R */ +#define NV_NPORT_ERR_CONTROL_COMMON_NPORT_CORRECTABLEENABLE 0:0 /* RWEVF */ +#define NV_NPORT_ERR_CONTROL_COMMON_NPORT_CORRECTABLEENABLE_INIT 0x00000001 /* RWE-V */ +#define NV_NPORT_ERR_CONTROL_COMMON_NPORT_FATALENABLE 1:1 /* RWEVF */ +#define NV_NPORT_ERR_CONTROL_COMMON_NPORT_FATALENABLE_INIT 0x00000001 /* RWE-V */ +#define NV_NPORT_ERR_CONTROL_COMMON_NPORT_NONFATALENABLE 2:2 /* RWEVF */ +#define NV_NPORT_ERR_CONTROL_COMMON_NPORT_NONFATALENABLE_INIT 0x00000001 /* RWE-V */ +#define NV_NPORT_MCID_ERROR_VECTOR(i) (0x00000480+(i)*0x4) /* RW-4A */ +#define NV_NPORT_MCID_ERROR_VECTOR__SIZE_1 4 /* */ +#define NV_NPORT_MCID_ERROR_VECTOR_STATUS 31:0 /* RWEVF */ +#define NV_NPORT_MCID_ERROR_VECTOR_STATUS__ONWRITE "oneToClear" /* */ +#define NV_NPORT_MCID_ERROR_VECTOR_STATUS_INIT 0x00000000 /* RWE-V */ +#define NV_NPORT_MCID_ERROR_VECTOR_STATUS_CLEAR 0x00000001 /* RW--V */ +#define NV_NPORT_SCRATCH_WARM 0x00000fc0 /* RW-4R */ +#define NV_NPORT_SCRATCH_WARM_DATA 31:0 /* RWEVF */ +#define NV_NPORT_SCRATCH_WARM_DATA_INIT 0xdeadbaad /* RWE-V */ +#endif // __ls10_dev_nport_ip_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_nport_ip_addendum.h b/src/common/inc/swref/published/nvswitch/ls10/dev_nport_ip_addendum.h new file mode 100644 index 000000000..f521cb09b --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_nport_ip_addendum.h @@ -0,0 +1,37 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_nport_ip_addendum_h__ +#define __ls10_dev_nport_ip_addendum_h__ + +// VC mapping + +#define NV_NPORT_VC_MAPPING_CREQ0 0x0 +#define NV_NPORT_VC_MAPPING_RSP0 0x5 +#define NV_NPORT_VC_MAPPING_CREQ1 0x6 +#define NV_NPORT_VC_MAPPING_RSP1 0x7 + +#define NV_NPORT_SCRATCH_WARM_PORT_RESET_REQUIRED 0:0 + +#endif // __ls10_dev_nport_ip_addendum_h__ + diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_nv_xal_ep.h b/src/common/inc/swref/published/nvswitch/ls10/dev_nv_xal_ep.h new file mode 100644 index 000000000..ab473ec70 --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_nv_xal_ep.h @@ -0,0 +1,153 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_nv_xal_ep_h__ +#define __ls10_dev_nv_xal_ep_h__ +/* This file is autogenerated. Do not edit */ +#define NV_XAL_EP 0x00000FFF:0x00000000 /* RW--D */ +#define NV_XAL_EP_CG 0x00000A00 /* RW-4R */ +#define NV_XAL_EP_CG_IDLE_CG_DLY_CNT 5:0 /* RWIVF */ +#define NV_XAL_EP_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWI-V */ +#define NV_XAL_EP_CG_IDLE_CG_DLY_CNT__PROD 0x00000002 /* ----V */ +#define NV_XAL_EP_CG_IDLE_CG_EN 6:6 /* RWIVF */ +#define NV_XAL_EP_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ +#define NV_XAL_EP_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWI-V */ +#define NV_XAL_EP_CG_IDLE_CG_EN__PROD 0x00000001 /* ----V */ +#define NV_XAL_EP_CG_STATE_CG_EN 7:7 /* */ +#define NV_XAL_EP_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ +#define NV_XAL_EP_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ +#define NV_XAL_EP_CG_STATE_CG_EN__PROD 0x00000001 /* */ +#define NV_XAL_EP_CG_STALL_CG_DLY_CNT 13:8 /* */ +#define NV_XAL_EP_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ +#define NV_XAL_EP_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */ +#define NV_XAL_EP_CG_STALL_CG_EN 14:14 /* RWIVF */ +#define NV_XAL_EP_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ +#define NV_XAL_EP_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWI-V */ +#define NV_XAL_EP_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG_QUIESCENT_CG_EN 15:15 /* */ +#define NV_XAL_EP_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ +#define NV_XAL_EP_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ +#define NV_XAL_EP_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ +#define NV_XAL_EP_CG_WAKEUP_DLY_CNT 19:16 /* RWIVF */ +#define NV_XAL_EP_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWI-V */ +#define NV_XAL_EP_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG_THROT_CLK_CNT 23:20 /* */ +#define NV_XAL_EP_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ +#define NV_XAL_EP_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ +#define NV_XAL_EP_CG_DI_DT_SKEW_VAL 27:24 /* */ +#define NV_XAL_EP_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ +#define NV_XAL_EP_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ +#define NV_XAL_EP_CG_THROT_CLK_EN 28:28 /* */ +#define NV_XAL_EP_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ +#define NV_XAL_EP_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ +#define NV_XAL_EP_CG_THROT_CLK_EN__PROD 0x00000000 /* */ +#define NV_XAL_EP_CG_THROT_CLK_SW_OVER 29:29 /* */ +#define NV_XAL_EP_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ +#define NV_XAL_EP_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ +#define NV_XAL_EP_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ +#define NV_XAL_EP_CG_PAUSE_CG_EN 30:30 /* */ +#define NV_XAL_EP_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ +#define NV_XAL_EP_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ +#define NV_XAL_EP_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ +#define NV_XAL_EP_CG_HALT_CG_EN 31:31 /* */ +#define NV_XAL_EP_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ +#define NV_XAL_EP_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ +#define NV_XAL_EP_CG_HALT_CG_EN__PROD 0x00000000 /* */ +#define NV_XAL_EP_CG1 0x00000A04 /* RW-4R */ +#define NV_XAL_EP_CG1_MONITOR_CG_EN 0:0 /* RWIVF */ +#define NV_XAL_EP_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ +#define NV_XAL_EP_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWI-V */ +#define NV_XAL_EP_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG 24:2 /* */ +#define NV_XAL_EP_CG1_SLCG_ENABLED 0x00000000 /* */ +#define NV_XAL_EP_CG1_SLCG_DISABLED 0x007fffff /* */ +#define NV_XAL_EP_CG1_SLCG__PROD 0x00000000 /* */ +#define NV_XAL_EP_CG1_SLCG_DOWNARB 2:2 /* RWIVF */ +#define NV_XAL_EP_CG1_SLCG_DOWNARB_ENABLED 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG_DOWNARB_DISABLED 0x00000001 /* RWI-V */ +#define NV_XAL_EP_CG1_SLCG_DOWNARB__PROD 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG_UPARB 3:3 /* RWIVF */ +#define NV_XAL_EP_CG1_SLCG_UPARB_ENABLED 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG_UPARB_DISABLED 0x00000001 /* RWI-V */ +#define NV_XAL_EP_CG1_SLCG_UPARB__PROD 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG_PRIREQ 4:4 /* RWIVF */ +#define NV_XAL_EP_CG1_SLCG_PRIREQ_ENABLED 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG_PRIREQ_DISABLED 0x00000001 /* RWI-V */ +#define NV_XAL_EP_CG1_SLCG_PRIREQ__PROD 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG_PRIRSP 5:5 /* RWIVF */ +#define NV_XAL_EP_CG1_SLCG_PRIRSP_ENABLED 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG_PRIRSP_DISABLED 0x00000001 /* RWI-V */ +#define NV_XAL_EP_CG1_SLCG_PRIRSP__PROD 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG_JOIN 6:6 /* RWIVF */ +#define NV_XAL_EP_CG1_SLCG_JOIN_ENABLED 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG_JOIN_DISABLED 0x00000001 /* RWI-V */ +#define NV_XAL_EP_CG1_SLCG_JOIN__PROD 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG_JTAG 7:7 /* RWIVF */ +#define NV_XAL_EP_CG1_SLCG_JTAG_ENABLED 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG_JTAG_DISABLED 0x00000001 /* RWI-V */ +#define NV_XAL_EP_CG1_SLCG_JTAG__PROD 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG_PM 9:9 /* RWIVF */ +#define NV_XAL_EP_CG1_SLCG_PM_ENABLED 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG_PM_DISABLED 0x00000001 /* RWI-V */ +#define NV_XAL_EP_CG1_SLCG_PM__PROD 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG_UNROLL_MEM 10:10 /* RWIVF */ +#define NV_XAL_EP_CG1_SLCG_UNROLL_MEM_ENABLED 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG_UNROLL_MEM_DISABLED 0x00000001 /* RWI-V */ +#define NV_XAL_EP_CG1_SLCG_UNROLL_MEM__PROD 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG_MEMOP 11:11 /* RWIVF */ +#define NV_XAL_EP_CG1_SLCG_MEMOP_ENABLED 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG_MEMOP_DISABLED 0x00000001 /* RWI-V */ +#define NV_XAL_EP_CG1_SLCG_MEMOP__PROD 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG_MEMRSP 12:12 /* RWIVF */ +#define NV_XAL_EP_CG1_SLCG_MEMRSP_ENABLED 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG_MEMRSP_DISABLED 0x00000001 /* RWI-V */ +#define NV_XAL_EP_CG1_SLCG_MEMRSP__PROD 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG_MSIX 13:13 /* RWIVF */ +#define NV_XAL_EP_CG1_SLCG_MSIX_ENABLED 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG_MSIX_DISABLED 0x00000001 /* RWI-V */ +#define NV_XAL_EP_CG1_SLCG_MSIX__PROD 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG_RXMAP 14:14 /* RWIVF */ +#define NV_XAL_EP_CG1_SLCG_RXMAP_ENABLED 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG_RXMAP_DISABLED 0x00000001 /* RWI-V */ +#define NV_XAL_EP_CG1_SLCG_RXMAP__PROD 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG_FBI_UP 15:15 /* RWIVF */ +#define NV_XAL_EP_CG1_SLCG_FBI_UP_ENABLED 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG_FBI_UP_DISABLED 0x00000001 /* RWI-V */ +#define NV_XAL_EP_CG1_SLCG_FBI_UP__PROD 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG_TXMAP 16:16 /* RWIVF */ +#define NV_XAL_EP_CG1_SLCG_TXMAP_ENABLED 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG_TXMAP_DISABLED 0x00000001 /* RWI-V */ +#define NV_XAL_EP_CG1_SLCG_TXMAP__PROD 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG_PRI_TRACKER 21:21 /* RWIVF */ +#define NV_XAL_EP_CG1_SLCG_PRI_TRACKER_ENABLED 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG_PRI_TRACKER_DISABLED 0x00000001 /* RWI-V */ +#define NV_XAL_EP_CG1_SLCG_PRI_TRACKER__PROD 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG_FASTFLUSH 23:23 /* RWIVF */ +#define NV_XAL_EP_CG1_SLCG_FASTFLUSH_ENABLED 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG_FASTFLUSH_DISABLED 0x00000001 /* RWI-V */ +#define NV_XAL_EP_CG1_SLCG_FASTFLUSH__PROD 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG_DFD 24:24 /* RWIVF */ +#define NV_XAL_EP_CG1_SLCG_DFD_ENABLED 0x00000000 /* RW--V */ +#define NV_XAL_EP_CG1_SLCG_DFD_DISABLED 0x00000001 /* RWI-V */ +#define NV_XAL_EP_CG1_SLCG_DFD__PROD 0x00000000 /* RW--V */ +#endif // __ls10_dev_nv_xal_ep_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_nv_xpl.h b/src/common/inc/swref/published/nvswitch/ls10/dev_nv_xpl.h new file mode 100644 index 000000000..69ccb0555 --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_nv_xpl.h @@ -0,0 +1,256 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_nv_xpl_h__ +#define __ls10_dev_nv_xpl_h__ +/* This file is autogenerated. Do not edit */ +#define NV_XPL 0x00003fff:0x00000000 /* RW--D */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG 0x00002700 /* RWE4R */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_IDLE_CG_DLY_CNT__PROD 0x00 /* RW--V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_IDLE_CG_EN 6:6 /* RWEVF */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_STATE_CG_EN 7:7 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_STATE_CG_EN_ENABLED 0x1 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_STATE_CG_EN_DISABLED 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_STATE_CG_EN__PROD 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_STALL_CG_DLY_CNT 13:8 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_STALL_CG_EN 14:14 /* RWEVF */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_QUIESCENT_CG_EN 15:15 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_THROT_CLK_CNT 23:20 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_THROT_CLK_CNT__PROD 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_DI_DT_SKEW_VAL 27:24 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_THROT_CLK_EN 28:28 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_THROT_CLK_EN_ENABLED 0x1 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_THROT_CLK_EN_DISABLED 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_THROT_CLK_EN__PROD 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_THROT_CLK_SW_OVER 29:29 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_PAUSE_CG_EN 30:30 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_PAUSE_CG_EN__PROD 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_HALT_CG_EN 31:31 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_HALT_CG_EN_ENABLED 0x1 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_HALT_CG_EN_DISABLED 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG_HALT_CG_EN__PROD 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG1 0x00002704 /* RWE4R */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG1_SLCG 18:1 /* RWEVF */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG1_SLCG_ENABLED 0x00000 /* RW--V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG1_SLCG_DISABLED 0x3ffff /* RWE-V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_XCLK_CG1_SLCG__PROD 0x00000 /* RW--V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG 0x00002710 /* RWE4R */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_IDLE_CG_DLY_CNT__PROD 0x00 /* RW--V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_IDLE_CG_EN 6:6 /* RWEVF */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_STATE_CG_EN 7:7 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_STATE_CG_EN_ENABLED 0x1 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_STATE_CG_EN_DISABLED 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_STATE_CG_EN__PROD 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_STALL_CG_DLY_CNT 13:8 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_STALL_CG_EN 14:14 /* RWEVF */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_QUIESCENT_CG_EN 15:15 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_THROT_CLK_CNT 23:20 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_THROT_CLK_CNT__PROD 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_DI_DT_SKEW_VAL 27:24 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_THROT_CLK_EN 28:28 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_THROT_CLK_EN_ENABLED 0x1 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_THROT_CLK_EN_DISABLED 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_THROT_CLK_EN__PROD 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_THROT_CLK_SW_OVER 29:29 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_PAUSE_CG_EN 30:30 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_PAUSE_CG_EN__PROD 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_HALT_CG_EN 31:31 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_HALT_CG_EN_ENABLED 0x1 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_HALT_CG_EN_DISABLED 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG_HALT_CG_EN__PROD 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG1 0x00002714 /* RWE4R */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG1_SLCG 2:1 /* RWEVF */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG1_SLCG_ENABLED 0x0 /* RW--V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG1_SLCG_DISABLED 0x3 /* RWE-V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_TXCLK_CG1_SLCG__PROD 0x0 /* RW--V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG 0x00002720 /* RWE4R */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_IDLE_CG_DLY_CNT__PROD 0x00 /* RW--V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_IDLE_CG_EN 6:6 /* RWEVF */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_STATE_CG_EN 7:7 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_STATE_CG_EN_ENABLED 0x1 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_STATE_CG_EN_DISABLED 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_STATE_CG_EN__PROD 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_STALL_CG_DLY_CNT 13:8 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_STALL_CG_EN 14:14 /* RWEVF */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_QUIESCENT_CG_EN 15:15 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_THROT_CLK_CNT 23:20 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_THROT_CLK_CNT__PROD 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_DI_DT_SKEW_VAL 27:24 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_THROT_CLK_EN 28:28 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_THROT_CLK_EN_ENABLED 0x1 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_THROT_CLK_EN_DISABLED 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_THROT_CLK_EN__PROD 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_THROT_CLK_SW_OVER 29:29 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_PAUSE_CG_EN 30:30 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_PAUSE_CG_EN__PROD 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_HALT_CG_EN 31:31 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_HALT_CG_EN_ENABLED 0x1 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_HALT_CG_EN_DISABLED 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG_HALT_CG_EN__PROD 0x0 /* */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG1 0x00002724 /* RWE4R */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG1_SLCG 3:1 /* RWEVF */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG1_SLCG_ENABLED 0x0 /* RW--V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG1_SLCG_DISABLED 0x7 /* RWE-V */ +#define NV_XPL_PL_PAD_CTL_PRI_XPL_RXCLK_CG1_SLCG__PROD 0x0 /* RW--V */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG 0x00003a00 /* RWE4R */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_IDLE_CG_DLY_CNT_HWINIT 0x0b /* RWE-V */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_IDLE_CG_DLY_CNT__PROD 0x0b /* RW--V */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_IDLE_CG_EN 6:6 /* RWEVF */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_IDLE_CG_EN__PROD 0x0 /* RW--V */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_STATE_CG_EN 7:7 /* */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_STATE_CG_EN_ENABLED 0x1 /* */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_STATE_CG_EN_DISABLED 0x0 /* */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_STATE_CG_EN__PROD 0x0 /* */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_STALL_CG_DLY_CNT 13:8 /* */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_STALL_CG_EN 14:14 /* RWEVF */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_QUIESCENT_CG_EN 15:15 /* */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_WAKEUP_DLY_CNT_HWINIT 0xb /* RWE-V */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_WAKEUP_DLY_CNT__PROD 0xb /* RW--V */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_THROT_CLK_CNT 23:20 /* */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_THROT_CLK_CNT__PROD 0x0 /* */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_DI_DT_SKEW_VAL 27:24 /* */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_THROT_CLK_EN 28:28 /* */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_THROT_CLK_EN_ENABLED 0x1 /* */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_THROT_CLK_EN_DISABLED 0x0 /* */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_THROT_CLK_EN__PROD 0x0 /* */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_THROT_CLK_SW_OVER 29:29 /* */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_PAUSE_CG_EN 30:30 /* */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_PAUSE_CG_EN__PROD 0x0 /* */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_HALT_CG_EN 31:31 /* */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_HALT_CG_EN_ENABLED 0x1 /* */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_HALT_CG_EN_DISABLED 0x0 /* */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG_HALT_CG_EN__PROD 0x0 /* */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG1 0x00003a04 /* RWE4R */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG1_SLCG 9:1 /* RWEVF */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG1_SLCG_ENABLED 0x000 /* RW--V */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG1_SLCG_DISABLED 0x1ff /* RWE-V */ +#define NV_XPL_XTLQ_PRI_XTL_Q_CG1_SLCG__PROD 0x000 /* RW--V */ +#endif // __ls10_dev_nv_xpl_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_nvldl_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_nvldl_ip.h new file mode 100644 index 000000000..175a7de3c --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_nvldl_ip.h @@ -0,0 +1,473 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_nvldl_ip_h__ +#define __ls10_dev_nvldl_ip_h__ +/* This file is autogenerated. Do not edit */ +#define NV_NVLDL_TOP 0x00001FFF:0x00000000 /* RW--D */ +#define NV_NVLDL_TX 0x000027FF:0x00002000 /* RW--D */ +#define NV_NVLDL_RX 0x000037FF:0x00003000 /* RW--D */ +#define NV_NVLDL_TOP_LINK_STATE 0x00000000 /* R--4R */ +#define NV_NVLDL_TOP_LINK_STATE_STATE 7:0 /* R-XVF */ +#define NV_NVLDL_TOP_LINK_STATE_STATE_INIT 0x00000000 /* R---V */ +#define NV_NVLDL_TOP_LINK_STATE_STATE_HWPCFG 0x0000000c /* R---V */ +#define NV_NVLDL_TOP_LINK_STATE_STATE_HWCFG 0x00000001 /* R---V */ +#define NV_NVLDL_TOP_LINK_STATE_STATE_SWCFG 0x00000002 /* R---V */ +#define NV_NVLDL_TOP_LINK_STATE_STATE_ACTIVE 0x00000003 /* R---V */ +#define NV_NVLDL_TOP_LINK_STATE_STATE_FAULT 0x00000004 /* R---V */ +#define NV_NVLDL_TOP_LINK_STATE_STATE_SLEEP 0x00000005 /* R---V */ +#define NV_NVLDL_TOP_LINK_STATE_STATE_RCVY_AC 0x00000008 /* R---V */ +#define NV_NVLDL_TOP_LINK_STATE_STATE_RCVY_RX 0x0000000a /* R---V */ +#define NV_NVLDL_TOP_LINK_STATE_STATE_TRAIN 0x0000000b /* R---V */ +#define NV_NVLDL_TOP_LINK_STATE_STATE_TEST 0x0000000d /* R---V */ +#define NV_NVLDL_TOP_LINK_STATE_AN0_BUSY 12:12 /* R-XVF */ +#define NV_NVLDL_TOP_LINK_STATE_TL_BUSY 13:13 /* R-XVF */ +#define NV_NVLDL_TOP_LINK_STATE_DBG_SUBSTATE 31:16 /* R-XVF */ +#define NV_NVLDL_TOP_INTR 0x00000050 /* RW-4R */ +#define NV_NVLDL_TOP_INTR_TX_REPLAY 0:0 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_TX_REPLAY__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_TX_REPLAY_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_TX_RECOVERY_SHORT 1:1 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_TX_RECOVERY_SHORT__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_TX_RECOVERY_SHORT_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_TX_FAULT_RAM 4:4 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_TX_FAULT_RAM__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_TX_FAULT_RAM_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_TX_FAULT_INTERFACE 5:5 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_TX_FAULT_INTERFACE__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_TX_FAULT_INTERFACE_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_TX_FAULT_SUBLINK_CHANGE 8:8 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_TX_FAULT_SUBLINK_CHANGE__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_TX_FAULT_SUBLINK_CHANGE_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_TX_PL_ERROR 9:9 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_TX_PL_ERROR__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_TX_PL_ERROR_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_PHY_A 12:12 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_PHY_A__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_PHY_A_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_PHY_B 13:13 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_PHY_B__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_PHY_B_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_RX_FAULT_SUBLINK_CHANGE 16:16 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_RX_FAULT_SUBLINK_CHANGE__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_RX_FAULT_SUBLINK_CHANGE_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_RX_PL_ERROR 17:17 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_RX_PL_ERROR__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_RX_PL_ERROR_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_RX_FAULT_DL_PROTOCOL 20:20 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_RX_FAULT_DL_PROTOCOL__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_RX_FAULT_DL_PROTOCOL_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_RX_SHORT_ERROR_RATE 21:21 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_RX_SHORT_ERROR_RATE__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_RX_SHORT_ERROR_RATE_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_RX_LONG_ERROR_RATE 22:22 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_RX_LONG_ERROR_RATE__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_RX_LONG_ERROR_RATE_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_RX_ILA_TRIGGER 23:23 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_RX_ILA_TRIGGER__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_RX_ILA_TRIGGER_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_RX_CRC_COUNTER 24:24 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_RX_CRC_COUNTER__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_RX_CRC_COUNTER_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_LTSSM_FAULT_DOWN 27:27 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_LTSSM_FAULT_DOWN__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_LTSSM_FAULT_DOWN_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_LTSSM_FAULT_UP 28:28 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_LTSSM_FAULT_UP__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_LTSSM_FAULT_UP_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_LTSSM_PROTOCOL 29:29 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_LTSSM_PROTOCOL__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_LTSSM_PROTOCOL_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_MINION_REQUEST 30:30 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_MINION_REQUEST__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_MINION_REQUEST_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_SW2 0x00000054 /* RW-4R */ +#define NV_NVLDL_TOP_INTR_SW2_TX_REPLAY 0:0 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_SW2_TX_REPLAY__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_SW2_TX_REPLAY_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_SW2_TX_RECOVERY_SHORT 1:1 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_SW2_TX_RECOVERY_SHORT__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_SW2_TX_RECOVERY_SHORT_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_SW2_TX_FAULT_RAM 4:4 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_SW2_TX_FAULT_RAM__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_SW2_TX_FAULT_RAM_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_SW2_TX_FAULT_INTERFACE 5:5 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_SW2_TX_FAULT_INTERFACE__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_SW2_TX_FAULT_INTERFACE_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_SW2_TX_FAULT_SUBLINK_CHANGE 8:8 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_SW2_TX_FAULT_SUBLINK_CHANGE__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_SW2_TX_FAULT_SUBLINK_CHANGE_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_SW2_TX_PL_ERROR 9:9 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_SW2_TX_PL_ERROR__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_SW2_TX_PL_ERROR_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_SW2_PHY_A 12:12 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_SW2_PHY_A__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_SW2_PHY_A_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_SW2_PHY_B 13:13 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_SW2_PHY_B__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_SW2_PHY_B_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_SW2_RX_FAULT_SUBLINK_CHANGE 16:16 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_SW2_RX_FAULT_SUBLINK_CHANGE__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_SW2_RX_FAULT_SUBLINK_CHANGE_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_SW2_RX_PL_ERROR 17:17 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_SW2_RX_PL_ERROR__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_SW2_RX_PL_ERROR_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_SW2_RX_FAULT_DL_PROTOCOL 20:20 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_SW2_RX_FAULT_DL_PROTOCOL__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_SW2_RX_FAULT_DL_PROTOCOL_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_SW2_RX_SHORT_ERROR_RATE 21:21 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_SW2_RX_SHORT_ERROR_RATE__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_SW2_RX_SHORT_ERROR_RATE_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_SW2_RX_LONG_ERROR_RATE 22:22 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_SW2_RX_LONG_ERROR_RATE__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_SW2_RX_LONG_ERROR_RATE_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_SW2_RX_ILA_TRIGGER 23:23 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_SW2_RX_ILA_TRIGGER__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_SW2_RX_ILA_TRIGGER_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_SW2_RX_CRC_COUNTER 24:24 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_SW2_RX_CRC_COUNTER__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_SW2_RX_CRC_COUNTER_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_SW2_LTSSM_FAULT_DOWN 27:27 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_SW2_LTSSM_FAULT_DOWN__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_SW2_LTSSM_FAULT_DOWN_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_SW2_LTSSM_FAULT_UP 28:28 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_SW2_LTSSM_FAULT_UP__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_SW2_LTSSM_FAULT_UP_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_SW2_LTSSM_PROTOCOL 29:29 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_SW2_LTSSM_PROTOCOL__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_SW2_LTSSM_PROTOCOL_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_SW2_MINION_REQUEST 30:30 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_SW2_MINION_REQUEST__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_TOP_INTR_SW2_MINION_REQUEST_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_STALL_EN 0x00000058 /* RW-4R */ +#define NV_NVLDL_TOP_INTR_STALL_EN_TX_REPLAY 0:0 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_STALL_EN_TX_REPLAY_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_TX_RECOVERY_SHORT 1:1 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_STALL_EN_TX_RECOVERY_SHORT_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_TX_RECOVERY_SHORT_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_RAM 4:4 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_RAM_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_RAM_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_INTERFACE 5:5 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_INTERFACE_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_INTERFACE_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_SUBLINK_CHANGE 8:8 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_SUBLINK_CHANGE_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_SUBLINK_CHANGE_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_TX_PL_ERROR 9:9 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_STALL_EN_TX_PL_ERROR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_TX_PL_ERROR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_PHY_A 12:12 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_STALL_EN_PHY_A_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_PHY_A_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_PHY_B 13:13 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_STALL_EN_PHY_B_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_PHY_B_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_RX_FAULT_SUBLINK_CHANGE 16:16 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_STALL_EN_RX_FAULT_SUBLINK_CHANGE_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_RX_FAULT_SUBLINK_CHANGE_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_RX_PL_ERROR 17:17 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_STALL_EN_RX_PL_ERROR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_RX_PL_ERROR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_RX_FAULT_DL_PROTOCOL 20:20 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_STALL_EN_RX_FAULT_DL_PROTOCOL_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_RX_FAULT_DL_PROTOCOL_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_RX_SHORT_ERROR_RATE 21:21 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_STALL_EN_RX_SHORT_ERROR_RATE_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_RX_SHORT_ERROR_RATE_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_RX_LONG_ERROR_RATE 22:22 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_STALL_EN_RX_LONG_ERROR_RATE_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_RX_LONG_ERROR_RATE_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_RX_ILA_TRIGGER 23:23 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_STALL_EN_RX_ILA_TRIGGER_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_RX_ILA_TRIGGER_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_RX_CRC_COUNTER 24:24 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_STALL_EN_RX_CRC_COUNTER_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_RX_CRC_COUNTER_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_FAULT_DOWN 27:27 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_FAULT_DOWN_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_FAULT_DOWN_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_FAULT_UP 28:28 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_FAULT_UP_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_FAULT_UP_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_PROTOCOL 29:29 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_PROTOCOL_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_PROTOCOL_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_MINION_REQUEST 30:30 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_STALL_EN_MINION_REQUEST_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_STALL_EN_MINION_REQUEST_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN 0x0000005c /* RW-4R */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_REPLAY 0:0 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_REPLAY_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_RECOVERY_SHORT 1:1 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_RECOVERY_SHORT_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_RECOVERY_SHORT_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_RAM 4:4 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_RAM_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_RAM_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_INTERFACE 5:5 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_INTERFACE_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_INTERFACE_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_SUBLINK_CHANGE 8:8 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_SUBLINK_CHANGE_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_SUBLINK_CHANGE_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_PL_ERROR 9:9 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_PL_ERROR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_PL_ERROR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_PHY_A 12:12 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_PHY_A_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_PHY_A_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_PHY_B 13:13 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_PHY_B_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_PHY_B_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_FAULT_SUBLINK_CHANGE 16:16 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_FAULT_SUBLINK_CHANGE_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_FAULT_SUBLINK_CHANGE_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_PL_ERROR 17:17 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_PL_ERROR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_PL_ERROR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_FAULT_DL_PROTOCOL 20:20 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_FAULT_DL_PROTOCOL_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_FAULT_DL_PROTOCOL_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_SHORT_ERROR_RATE 21:21 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_SHORT_ERROR_RATE_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_SHORT_ERROR_RATE_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_LONG_ERROR_RATE 22:22 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_LONG_ERROR_RATE_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_LONG_ERROR_RATE_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_ILA_TRIGGER 23:23 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_ILA_TRIGGER_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_ILA_TRIGGER_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_CRC_COUNTER 24:24 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_CRC_COUNTER_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_CRC_COUNTER_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_FAULT_DOWN 27:27 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_FAULT_DOWN_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_FAULT_DOWN_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_FAULT_UP 28:28 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_FAULT_UP_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_FAULT_UP_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_PROTOCOL 29:29 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_PROTOCOL_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_PROTOCOL_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_MINION_REQUEST 30:30 /* RWEVF */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_MINION_REQUEST_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLDL_TOP_INTR_NONSTALL_EN_MINION_REQUEST_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_ERROR_COUNT_CTRL 0x00000080 /* RW-4R */ +#define NV_NVLDL_TOP_ERROR_COUNT_CTRL_CLEAR_RECOVERY 2:2 /* -WXVF */ +#define NV_NVLDL_TOP_ERROR_COUNT_CTRL_CLEAR_RECOVERY_CLEAR 0x00000001 /* -W--V */ +#define NV_NVLDL_TOP_ERROR_COUNT_CTRL_MASK_SEL 21:16 /* RWEVF */ +#define NV_NVLDL_TOP_ERROR_COUNT_CTRL_MASK_SEL_SAFEMODE 0x00000001 /* RW--V */ +#define NV_NVLDL_TOP_ERROR_COUNT_CTRL_MASK_SEL_STEADYHS 0x00000002 /* RWE-V */ +#define NV_NVLDL_TOP_ERROR_COUNT_CTRL_MASK_SEL_EARLYINITHS 0x00000004 /* RW--V */ +#define NV_NVLDL_TOP_ERROR_COUNT_CTRL_MASK_SEL_EARLYL1HS 0x00000008 /* RW--V */ +#define NV_NVLDL_TOP_ERROR_COUNT_CTRL_MASK_SEL_EARLYRCVYHS 0x00000010 /* RW--V */ +#define NV_NVLDL_TOP_ERROR_COUNT_CTRL_MASK_SEL_RSVD20 0x00000020 /* RW--V */ +#define NV_NVLDL_TOP_ERROR_COUNT_CTRL_MASK_DELAY 27:24 /* RWEUF */ +#define NV_NVLDL_TOP_ERROR_COUNT_CTRL_MASK_DELAY_INIT 0x00000001 /* RWE-V */ +#define NV_NVLDL_TX_SLSM_STATUS_TX 0x00002024 /* R--4R */ +#define NV_NVLDL_TX_SLSM_STATUS_TX_SUBSTATE 3:0 /* R-XVF */ +#define NV_NVLDL_TX_SLSM_STATUS_TX_SUBSTATE_STABLE 0x00000000 /* R---V */ +#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE 7:4 /* R-XVF */ +#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_HS 0x00000000 /* R---V */ +#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_TRAIN 0x00000005 /* R---V */ +#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_SAFE 0x00000006 /* R---V */ +#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_OFF 0x00000007 /* R---V */ +#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_TEST 0x00000008 /* R---V */ +#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_UNKNOWN 0x0000000d /* R---V */ +#define NV_NVLDL_TX_ERROR_COUNT_CTRL 0x00002280 /* -W-4R */ +#define NV_NVLDL_TX_ERROR_COUNT_CTRL_CLEAR_R4_RETRY 0:0 /* -WXVF */ +#define NV_NVLDL_TX_ERROR_COUNT_CTRL_CLEAR_R4_RETRY_CLEAR 0x00000001 /* -W--V */ +#define NV_NVLDL_TX_ERROR_COUNT_CTRL_CLEAR_REPLAY 8:8 /* -WXVF */ +#define NV_NVLDL_TX_ERROR_COUNT_CTRL_CLEAR_REPLAY_CLEAR 0x00000001 /* -W--V */ +#define NV_NVLDL_RX_SLSM_STATUS_RX 0x00003014 /* R--4R */ +#define NV_NVLDL_RX_SLSM_STATUS_RX_SUBSTATE 3:0 /* R-EVF */ +#define NV_NVLDL_RX_SLSM_STATUS_RX_SUBSTATE_STABLE 0x00000000 /* R-E-V */ +#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE 7:4 /* R-XVF */ +#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_HS 0x00000000 /* R---V */ +#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_TRAIN 0x00000005 /* R---V */ +#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_SAFE 0x00000006 /* R---V */ +#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_OFF 0x00000007 /* R---V */ +#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_TEST 0x00000008 /* R---V */ +#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_UNKNOWN 0x0000000d /* R---V */ +#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_FAULT 0x0000000e /* R---V */ +#define NV_NVLDL_RX_SLSM_STATUS_RX_UNEXPECTED_REMOTE_STATE_CNT 15:8 /* R-EVF */ +#define NV_NVLDL_RX_SLSM_STATUS_RX_UNEXPECTED_REMOTE_STATE_CNT_INIT 0x00000000 /* R-E-V */ +#define NV_NVLDL_RX_SLSM_STATUS_RX_FENCE_STATUS 31:31 /* R-EVF */ +#define NV_NVLDL_RX_SLSM_STATUS_RX_FENCE_STATUS_OFF 0x00000000 /* R-E-V */ +#define NV_NVLDL_RX_SLSM_STATUS_RX_FENCE_STATUS_ON 0x00000001 /* R---V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL 0x00003028 /* RW-4R */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_CONST_DET_ERR 1:1 /* RWEVF */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_CONST_DET_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_CONST_DET_ERR_OFF 0x00000000 /* RWE-V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_CONST_DET_ERR_ON 0x00000001 /* RW--V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_OFF2SAFE_LINK_DET_ERR 2:2 /* RWEVF */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_OFF2SAFE_LINK_DET_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_OFF2SAFE_LINK_DET_ERR_OFF 0x00000000 /* RWE-V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_OFF2SAFE_LINK_DET_ERR_ON 0x00000001 /* RW--V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SAFE_FINISH_ERR 3:3 /* RWEVF */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SAFE_FINISH_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SAFE_FINISH_ERR_OFF 0x00000000 /* RWE-V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SAFE_FINISH_ERR_ON 0x00000001 /* RW--V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SCRAM_LOCK_ERR 4:4 /* RWEVF */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SCRAM_LOCK_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SCRAM_LOCK_ERR_OFF 0x00000000 /* RWE-V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SCRAM_LOCK_ERR_ON 0x00000001 /* RW--V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SYM_LOCK_ERR 5:5 /* RWEVF */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SYM_LOCK_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SYM_LOCK_ERR_OFF 0x00000000 /* RWE-V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SYM_LOCK_ERR_ON 0x00000001 /* RW--V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SYM_ALIGN_END_ERR 6:6 /* RWEVF */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SYM_ALIGN_END_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SYM_ALIGN_END_ERR_OFF 0x00000000 /* RWE-V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SYM_ALIGN_END_ERR_ON 0x00000001 /* RW--V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FIFO_SKEW_ERR 7:7 /* RWEVF */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FIFO_SKEW_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FIFO_SKEW_ERR_OFF 0x00000000 /* RWE-V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FIFO_SKEW_ERR_ON 0x00000001 /* RW--V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_TRAIN2SAFE_LINK_DET_ERR 8:8 /* RWEVF */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_TRAIN2SAFE_LINK_DET_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_TRAIN2SAFE_LINK_DET_ERR_OFF 0x00000000 /* RWE-V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_TRAIN2SAFE_LINK_DET_ERR_ON 0x00000001 /* RW--V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_HS2SAFE_LINK_DET_ERR 9:9 /* RWEVF */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_HS2SAFE_LINK_DET_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_HS2SAFE_LINK_DET_ERR_OFF 0x00000000 /* RWE-V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_HS2SAFE_LINK_DET_ERR_ON 0x00000001 /* RW--V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FENCE_ERR 10:10 /* RWEVF */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FENCE_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FENCE_ERR_OFF 0x00000000 /* RWE-V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FENCE_ERR_ON 0x00000001 /* RW--V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FAULT2SAFE_LINK_DET_ERR 11:11 /* RWEVF */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FAULT2SAFE_LINK_DET_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FAULT2SAFE_LINK_DET_ERR_OFF 0x00000000 /* RWE-V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FAULT2SAFE_LINK_DET_ERR_ON 0x00000001 /* RW--V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FAULT2SAFE_SAFE_DET_ERR 12:12 /* RWEVF */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FAULT2SAFE_SAFE_DET_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FAULT2SAFE_SAFE_DET_ERR_OFF 0x00000000 /* RWE-V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FAULT2SAFE_SAFE_DET_ERR_ON 0x00000001 /* RW--V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SAFE_RETRY_ERR 13:13 /* RWEVF */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SAFE_RETRY_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SAFE_RETRY_ERR_OFF 0x00000000 /* RWE-V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SAFE_RETRY_ERR_ON 0x00000001 /* RW--V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_RC_DEADLINE_ERR 15:15 /* RWEVF */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_RC_DEADLINE_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_RC_DEADLINE_ERR_OFF 0x00000000 /* RWE-V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_RC_DEADLINE_ERR_ON 0x00000001 /* RW--V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_IOBIST_ECC_ALIGN_DONE_ERR 16:16 /* RWEVF */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_IOBIST_ECC_ALIGN_DONE_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_IOBIST_ECC_ALIGN_DONE_ERR_OFF 0x00000000 /* RWE-V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_IOBIST_ECC_ALIGN_DONE_ERR_ON 0x00000001 /* RW--V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_O2S_SD_NO_LD_ERR 18:18 /* RWEVF */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_O2S_SD_NO_LD_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_O2S_SD_NO_LD_ERR_OFF 0x00000000 /* RWE-V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_O2S_SD_NO_LD_ERR_ON 0x00000001 /* RW--V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_H2S_SD_NO_LD_ERR 19:19 /* RWEVF */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_H2S_SD_NO_LD_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_H2S_SD_NO_LD_ERR_OFF 0x00000000 /* RWE-V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_H2S_SD_NO_LD_ERR_ON 0x00000001 /* RW--V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_O2S_STROBE_NO_SD_ERR 21:21 /* RWEVF */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_O2S_STROBE_NO_SD_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_O2S_STROBE_NO_SD_ERR_OFF 0x00000000 /* RWE-V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_O2S_STROBE_NO_SD_ERR_ON 0x00000001 /* RW--V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_H2S_STROBE_NO_SD_ERR 22:22 /* RWEVF */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_H2S_STROBE_NO_SD_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_H2S_STROBE_NO_SD_ERR_OFF 0x00000000 /* RWE-V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_H2S_STROBE_NO_SD_ERR_ON 0x00000001 /* RW--V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_HS2SAFE_SAFE_DET_ERR 24:24 /* RWEVF */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_HS2SAFE_SAFE_DET_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_HS2SAFE_SAFE_DET_ERR_OFF 0x00000000 /* RWE-V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_HS2SAFE_SAFE_DET_ERR_ON 0x00000001 /* RW--V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_TRAIN2SAFE_SAFE_DET_ERR 25:25 /* RWEVF */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_TRAIN2SAFE_SAFE_DET_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_TRAIN2SAFE_SAFE_DET_ERR_OFF 0x00000000 /* RWE-V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_TRAIN2SAFE_SAFE_DET_ERR_ON 0x00000001 /* RW--V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_S2S_SAFE_DET_ERR 26:26 /* RWEVF */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_S2S_SAFE_DET_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_S2S_SAFE_DET_ERR_OFF 0x00000000 /* RWE-V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_S2S_SAFE_DET_ERR_ON 0x00000001 /* RW--V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_OFF2SAFE_SAFE_DET_ERR 27:27 /* RWEVF */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_OFF2SAFE_SAFE_DET_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_OFF2SAFE_SAFE_DET_ERR_OFF 0x00000000 /* RWE-V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_OFF2SAFE_SAFE_DET_ERR_ON 0x00000001 /* RW--V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_L2_FENCE_ERR 29:29 /* RWEVF */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_L2_FENCE_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_L2_FENCE_ERR_OFF 0x00000000 /* RWE-V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_L2_FENCE_ERR_ON 0x00000001 /* RW--V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_IOBIST_ECC_SCRAM_LOCK_ERR 30:30 /* RWEVF */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_IOBIST_ECC_SCRAM_LOCK_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_IOBIST_ECC_SCRAM_LOCK_ERR_OFF 0x00000000 /* RWE-V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_IOBIST_ECC_SCRAM_LOCK_ERR_ON 0x00000001 /* RW--V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_IOBIST_ECC_ALIGN_LOCK_ERR 31:31 /* RWEVF */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_IOBIST_ECC_ALIGN_LOCK_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_IOBIST_ECC_ALIGN_LOCK_ERR_OFF 0x00000000 /* RWE-V */ +#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_IOBIST_ECC_ALIGN_LOCK_ERR_ON 0x00000001 /* RW--V */ +#define NV_NVLDL_RX_ERROR_COUNT_CTRL 0x00003280 /* RW-4R */ +#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_FLIT_CRC 0:0 /* -WEVF */ +#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_FLIT_CRC_INIT 0x00000000 /* -WE-V */ +#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_FLIT_CRC_CLEAR 0x00000001 /* -W--V */ +#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_LANE_CRC 1:1 /* -WEVF */ +#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_LANE_CRC_INIT 0x00000000 /* -WE-V */ +#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_LANE_CRC_CLEAR 0x00000001 /* -W--V */ +#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_RATES 2:2 /* -WEVF */ +#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_RATES_INIT 0x00000000 /* -WE-V */ +#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_RATES_CLEAR 0x00000001 /* -W--V */ +#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_REPLAY 3:3 /* -WEVF */ +#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_REPLAY_INIT 0x00000000 /* -WE-V */ +#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_REPLAY_CLEAR 0x00000001 /* -W--V */ +#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_ECC_COUNTS 4:4 /* -WEVF */ +#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_ECC_COUNTS_INIT 0x00000000 /* -WE-V */ +#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_ECC_COUNTS_CLEAR 0x00000001 /* -W--V */ +#define NV_NVLDL_RX_ERROR_COUNT_CTRL_SHORT_RATE 8:8 /* RWEVF */ +#define NV_NVLDL_RX_ERROR_COUNT_CTRL_SHORT_RATE_ENABLE 0x00000001 /* RWE-V */ +#define NV_NVLDL_RX_ERROR_COUNT_CTRL_SHORT_RATE_DISABLE 0x00000000 /* RW--V */ +#define NV_NVLDL_RX_ERROR_COUNT_CTRL_LONG_RATE 9:9 /* RWEVF */ +#define NV_NVLDL_RX_ERROR_COUNT_CTRL_LONG_RATE_ENABLE 0x00000001 /* RWE-V */ +#define NV_NVLDL_RX_ERROR_COUNT_CTRL_LONG_RATE_DISABLE 0x00000000 /* RW--V */ +#define NV_NVLDL_RX_ERROR_COUNT_CTRL_RATE_COUNT_MODE 10:10 /* RWEVF */ +#define NV_NVLDL_RX_ERROR_COUNT_CTRL_RATE_COUNT_MODE_FLIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_RX_ERROR_COUNT_CTRL_RATE_COUNT_MODE_SEQUENCE 0x00000001 /* RW--V */ +#define NV_NVLDL_RX_ERROR_COUNT_CTRL_FLIT_COUNT_MODE 11:11 /* RWEVF */ +#define NV_NVLDL_RX_ERROR_COUNT_CTRL_FLIT_COUNT_MODE_FLIT 0x00000000 /* RW--V */ +#define NV_NVLDL_RX_ERROR_COUNT_CTRL_FLIT_COUNT_MODE_SEQUENCE 0x00000001 /* RWE-V */ +#define NV_NVLDL_RX_ERROR_COUNT_CTRL_RATE_COUNT_SRC 13:12 /* RWEVF */ +#define NV_NVLDL_RX_ERROR_COUNT_CTRL_RATE_COUNT_SRC_FLITCRC 0x00000000 /* RWE-V */ +#define NV_NVLDL_RX_ERROR_COUNT_CTRL_RATE_COUNT_SRC_ECCFAIL 0x00000001 /* RW--V */ +#define NV_NVLDL_RX_ERROR_COUNT_CTRL_RATE_COUNT_SRC_ECCCORR 0x00000002 /* RW--V */ +#define NV_NVLDL_RX_ERROR_RATE_CTRL 0x00003284 /* RW-4R */ +#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_THRESHOLD_MAN 2:0 /* RWEUF */ +#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_THRESHOLD_MAN_INIT 0x00000001 /* RWE-V */ +#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_THRESHOLD_EXP 3:3 /* RWEUF */ +#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_THRESHOLD_EXP_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_TIMESCALE_MAN 6:4 /* RWEUF */ +#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_TIMESCALE_MAN_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_TIMESCALE_EXP 11:8 /* RWEUF */ +#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_TIMESCALE_EXP_INIT 0x00000006 /* RWE-V */ +#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_THRESHOLD_MAN 18:16 /* RWEUF */ +#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_THRESHOLD_MAN_INIT 0x00000001 /* RWE-V */ +#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_THRESHOLD_EXP 19:19 /* RWEUF */ +#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_THRESHOLD_EXP_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_TIMESCALE_MAN 22:20 /* RWEUF */ +#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_TIMESCALE_MAN_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_TIMESCALE_EXP 28:24 /* RWEUF */ +#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_TIMESCALE_EXP_INIT 0x00000006 /* RWE-V */ +#endif // __ls10_dev_nvldl_ip_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_nvldl_ip_addendum.h b/src/common/inc/swref/published/nvswitch/ls10/dev_nvldl_ip_addendum.h new file mode 100644 index 000000000..71dfacd4a --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_nvldl_ip_addendum.h @@ -0,0 +1,36 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_nvldl_ip_addendum_h__ +#define __ls10_dev_nvldl_ip_addendum_h__ + +#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN 2:0 +#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN_DEFAULT 0x00000007 +#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP 3:3 +#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP_DEFAULT 0x00000000 +#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_MAN 6:4 +#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_MAN_DEFAULT 0x00000005 +#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP 12:8 +#define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP_DEFAULT 0x00000005 + +#endif // __ls10_dev_nvldl_ip_addendum_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_nvlipt_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_nvlipt_ip.h new file mode 100644 index 000000000..feaf634b9 --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_nvlipt_ip.h @@ -0,0 +1,66 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_nvlipt_ip_h__ +#define __ls10_dev_nvlipt_ip_h__ +/* This file is autogenerated. Do not edit */ +#define NV_NVLIPT_COMMON 0x000007FF:0x00000000 /* RW--D */ +#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_CHIP_SID_LO 0x00000108 /* R--4R */ +#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_CHIP_SID_LO_SID_31_0 31:0 /* R-IVF */ +#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_CHIP_SID_LO_SID_31_0_INIT 0x00000000 /* R-I-V */ +#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_CHIP_SID_HI 0x0000010c /* R--4R */ +#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_CHIP_SID_HI_SID_63_32 31:0 /* R-IVF */ +#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_CHIP_SID_HI_SID_63_32_INIT 0x00000000 /* R-I-V */ +#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_LINK_CONFIGURATION 0x00000114 /* RW-4R */ +#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_LINK_CONFIGURATION_NUM_LINKS_PER_NVLIPT 7:0 /* R-IVF */ +#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_LINK_CONFIGURATION_NUM_LINKS_PER_NVLIPT_INIT 0x00000004 /* R-I-V */ +#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_LINK_CONFIGURATION_NUM_LANES_PER_LINK 15:8 /* R-IVF */ +#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_LINK_CONFIGURATION_NUM_LANES_PER_LINK_INIT 0x00000002 /* R-I-V */ +#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_LINK_CONFIGURATION_NUM_USABLE_LINKS 26:24 /* RWIVF */ +#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_LINK_CONFIGURATION_NUM_USABLE_LINKS_INIT 0x00000004 /* RWI-V */ +#define NV_NVLIPT_COMMON_ERR_STATUS_0 0x00000280 /* RW-4R */ +#define NV_NVLIPT_COMMON_ERR_STATUS_0_CLKCTL_ILLEGAL_REQUEST 0:0 /* RWIVF */ +#define NV_NVLIPT_COMMON_ERR_STATUS_0_CLKCTL_ILLEGAL_REQUEST__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_COMMON_ERR_STATUS_0_CLKCTL_ILLEGAL_REQUEST_NONE 0x00000000 /* RWI-V */ +#define NV_NVLIPT_COMMON_ERR_STATUS_0_CLKCTL_ILLEGAL_REQUEST_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0 0x00000288 /* RW-4R */ +#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0_CLKCTL_ILLEGAL_REQUEST 0:0 /* RWEVF */ +#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0_CLKCTL_ILLEGAL_REQUEST_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0_CLKCTL_ILLEGAL_REQUEST_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0 0x00000294 /* RW-4R */ +#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0_CLKCTL_ILLEGAL_REQUEST 0:0 /* RWEVF */ +#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0_CLKCTL_ILLEGAL_REQUEST_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0_CLKCTL_ILLEGAL_REQUEST_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLIPT_COMMON_ERR_FIRST_0 0x0000029c /* RW-4R */ +#define NV_NVLIPT_COMMON_ERR_FIRST_0_CLKCTL_ILLEGAL_REQUEST 0:0 /* RWIVF */ +#define NV_NVLIPT_COMMON_ERR_FIRST_0_CLKCTL_ILLEGAL_REQUEST__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_COMMON_ERR_FIRST_0_CLKCTL_ILLEGAL_REQUEST_NONE 0x00000000 /* RWI-V */ +#define NV_NVLIPT_COMMON_ERR_FIRST_0_CLKCTL_ILLEGAL_REQUEST_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLIPT_COMMON_INTR_CONTROL_COMMON 0x00000300 /* RW-4R */ +#define NV_NVLIPT_COMMON_INTR_CONTROL_COMMON_INT0_EN 0:0 /* RWEVF */ +#define NV_NVLIPT_COMMON_INTR_CONTROL_COMMON_INT0_EN_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLIPT_COMMON_INTR_CONTROL_COMMON_INT0_EN_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLIPT_COMMON_INTR_CONTROL_COMMON_INT1_EN 1:1 /* RWEVF */ +#define NV_NVLIPT_COMMON_INTR_CONTROL_COMMON_INT1_EN_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLIPT_COMMON_INTR_CONTROL_COMMON_INT1_EN_ENABLE 0x00000001 /* RW--V */ +#endif // __ls10_dev_nvlipt_ip_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_nvlipt_lnk_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_nvlipt_lnk_ip.h new file mode 100644 index 000000000..a4ac4bf5d --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_nvlipt_lnk_ip.h @@ -0,0 +1,638 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_nvlipt_lnk_ip_h__ +#define __ls10_dev_nvlipt_lnk_ip_h__ +/* This file is autogenerated. Do not edit */ +#define NV_NVLIPT_LNK 0x000007FF:0x00000000 /* RW--D */ +#define NV_NVLIPT_LNK_CTRL_PRI_CLOCK_GATING_LINK 0x0000008c /* RW-4R */ +#define NV_NVLIPT_LNK_CTRL_PRI_CLOCK_GATING_LINK_TL_CG1_SLCG 0:0 /* RWEVF */ +#define NV_NVLIPT_LNK_CTRL_PRI_CLOCK_GATING_LINK_TL_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_PRI_CLOCK_GATING_LINK_TL_CG1_SLCG_DISABLED 0x00000001 /* RWE-V */ +#define NV_NVLIPT_LNK_CTRL_PRI_CLOCK_GATING_LINK_DL_CG1_SLCG 8:8 /* RWEVF */ +#define NV_NVLIPT_LNK_CTRL_PRI_CLOCK_GATING_LINK_DL_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_PRI_CLOCK_GATING_LINK_DL_CG1_SLCG_DISABLED 0x00000001 /* RWE-V */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL 0x00000090 /* RW-4R */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_SEL 1:0 /* RWEVF */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_SEL_LANE_CLK 0x00000000 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_SEL_TX_CLK 0x00000002 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_SEL_OFF 0x00000003 /* RWE-V */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_TXCLK_SEL 4:3 /* RWEVF */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_TXCLK_SEL_PLL_CLK 0x00000000 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_TXCLK_SEL_ALT_CLK 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_TXCLK_SEL_OFF 0x00000003 /* RWE-V */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_NCISOCCLK_SEL 6:6 /* RWEVF */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_NCISOCCLK_SEL_OFF 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_NCISOCCLK_SEL_ON 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_STS 17:16 /* R-EVF */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_STS_LANE_CLK 0x00000000 /* R---V */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_STS_TX_CLK 0x00000002 /* R---V */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_STS_OFF 0x00000003 /* R-E-V */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_TXCLK_STS 20:19 /* R-EVF */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_TXCLK_STS_PLL_CLK 0x00000000 /* R---V */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_TXCLK_STS_ALT_CLK 0x00000001 /* R---V */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_TXCLK_STS_OFF 0x00000003 /* R-E-V */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_NCISOCCLK_STS 21:21 /* R-EVF */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_NCISOCCLK_STS_OFF 0x00000000 /* R---V */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_NCISOCCLK_STS_ON 0x00000001 /* R-E-V */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_PLL_PWR 24:24 /* RWEVF */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_PLL_PWR_OFF 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_PLL_PWR_ON 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_PLL_PWR_STS 25:25 /* R-EVF */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_PLL_PWR_STS_OFF 0x00000000 /* R-E-V */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_PLL_PWR_STS_ON 0x00000001 /* R---V */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_PLL_PWR_ACK 26:26 /* R-EVF */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_PLL_PWR_ACK_OFF 0x00000000 /* R-E-V */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_PLL_PWR_ACK_ON 0x00000001 /* R---V */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_PLL_HW_DISABLE 29:29 /* RWEVF */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_PLL_HW_DISABLE_HW_CONTROL_ENABLED 0x00000000 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_PLL_HW_DISABLE_HW_CONTROL_DISABLED 0x00000001 /* RWE-V */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_TXCLK_HW_DISABLE 30:30 /* RWEVF */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_TXCLK_HW_DISABLE_HW_CONTROL_ENABLED 0x00000000 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_TXCLK_HW_DISABLE_HW_CONTROL_DISABLED 0x00000001 /* RWE-V */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_HW_DISABLE 31:31 /* RWEVF */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_HW_DISABLE_HW_CONTROL_ENABLED 0x00000000 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_HW_DISABLE_HW_CONTROL_DISABLED 0x00000001 /* RWE-V */ +#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_INFO 0x00000100 /* RW-4R */ +#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_INFO_CHIP_INFO 31:0 /* RWIVF */ +#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_INFO_CHIP_INFO_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE 0x00000104 /* RW-4R */ +#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE 7:0 /* RWIVF */ +#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE_NV2P1TUR 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE_NV3P0AMP 0x00000002 /* RW--V */ +#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE_NV3P0LRK 0x00000003 /* RW--V */ +#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE_BB3P0P9P 0x00000004 /* RW--V */ +#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE_BB3P0P10 0x00000005 /* RW--V */ +#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE_NV3P1AMP 0x00000006 /* RW--V */ +#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE_NV4P0HOP 0x00000007 /* RW--V */ +#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE_NV4P0LAG 0x00000008 /* RW--V */ +#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE_NV4P1GRC 0x00000009 /* RW--V */ +#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE_NV4P2HOP 0x0000000a /* RW--V */ +#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_SID_LO 0x00000108 /* RW-4R */ +#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_SID_LO_SID_31_0 31:0 /* RWIVF */ +#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_SID_LO_SID_31_0_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_SID_HI 0x0000010c /* RW-4R */ +#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_SID_HI_SID_63_32 31:0 /* RWIVF */ +#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_SID_HI_SID_63_32_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_LINK_INFO 0x00000110 /* RW-4R */ +#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_LINK_INFO_LINK_NUMBER 7:0 /* RWIVF */ +#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_LINK_INFO_LINK_NUMBER_INIT 0x000000ff /* RWI-V */ +#define NV_NVLIPT_LNK_TOPOLOGY_LOCAL_LINK_INFO 0x00000114 /* R--4R */ +#define NV_NVLIPT_LNK_TOPOLOGY_LOCAL_LINK_INFO_LINK_NUMBER 7:0 /* R-IVF */ +#define NV_NVLIPT_LNK_TOPOLOGY_LOCAL_LINK_INFO_LINK_NUMBER_INIT 0x000000ff /* R-I-V */ +#define NV_NVLIPT_LNK_ERR_STATUS_0 0x00000280 /* RW-4R */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_SLEEPWHILEACTIVELINK 0:0 /* RWIVF */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_SLEEPWHILEACTIVELINK__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_SLEEPWHILEACTIVELINK_NONE 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_SLEEPWHILEACTIVELINK_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_ILLEGALLINKSTATEREQUEST 1:1 /* RWIVF */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_ILLEGALLINKSTATEREQUEST__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_ILLEGALLINKSTATEREQUEST_NONE 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_ILLEGALLINKSTATEREQUEST_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_FAILEDMINIONREQUEST 2:2 /* RWIVF */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_FAILEDMINIONREQUEST__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_FAILEDMINIONREQUEST_NONE 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_FAILEDMINIONREQUEST_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_RESERVEDREQUESTVALUE 3:3 /* RWIVF */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_RESERVEDREQUESTVALUE__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_RESERVEDREQUESTVALUE_NONE 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_RESERVEDREQUESTVALUE_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_LINKSTATEWRITEWHILEBUSY 4:4 /* RWIVF */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_LINKSTATEWRITEWHILEBUSY__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_LINKSTATEWRITEWHILEBUSY_NONE 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_LINKSTATEWRITEWHILEBUSY_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_LINK_STATE_REQUEST_TIMEOUT 5:5 /* RWIVF */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_LINK_STATE_REQUEST_TIMEOUT__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_LINK_STATE_REQUEST_TIMEOUT_NONE 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_LINK_STATE_REQUEST_TIMEOUT_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR 6:6 /* RWIVF */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR_NONE 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_RSTSEQ_PHYCTL_TIMEOUT 7:7 /* RWIVF */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_RSTSEQ_PHYCTL_TIMEOUT__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_RSTSEQ_PHYCTL_TIMEOUT_NONE 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_RSTSEQ_PHYCTL_TIMEOUT_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_RSTSEQ_CLKCTL_TIMEOUT 8:8 /* RWIVF */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_RSTSEQ_CLKCTL_TIMEOUT__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_RSTSEQ_CLKCTL_TIMEOUT_NONE 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_RSTSEQ_CLKCTL_TIMEOUT_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_CLKCTL_REQUEST_TIMEOUT 9:9 /* RWIVF */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_CLKCTL_REQUEST_TIMEOUT__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_CLKCTL_REQUEST_TIMEOUT_NONE 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_ERR_STATUS_0_CLKCTL_REQUEST_TIMEOUT_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0 0x00000288 /* RW-4R */ +#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_SLEEPWHILEACTIVELINK 0:0 /* RWEVF */ +#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_SLEEPWHILEACTIVELINK_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_SLEEPWHILEACTIVELINK_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_ILLEGALLINKSTATEREQUEST 1:1 /* RWEVF */ +#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_ILLEGALLINKSTATEREQUEST_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_ILLEGALLINKSTATEREQUEST_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_FAILEDMINIONREQUEST 2:2 /* RWEVF */ +#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_FAILEDMINIONREQUEST_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_FAILEDMINIONREQUEST_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_RESERVEDREQUESTVALUE 3:3 /* RWEVF */ +#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_RESERVEDREQUESTVALUE_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_RESERVEDREQUESTVALUE_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_LINKSTATEWRITEWHILEBUSY 4:4 /* RWEVF */ +#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_LINKSTATEWRITEWHILEBUSY_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_LINKSTATEWRITEWHILEBUSY_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_LINK_STATE_REQUEST_TIMEOUT 5:5 /* RWEVF */ +#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_LINK_STATE_REQUEST_TIMEOUT_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_LINK_STATE_REQUEST_TIMEOUT_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR 6:6 /* RWEVF */ +#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_RSTSEQ_PHYCTL_TIMEOUT 7:7 /* RWEVF */ +#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_RSTSEQ_PHYCTL_TIMEOUT_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_RSTSEQ_PHYCTL_TIMEOUT_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_RSTSEQ_CLKCTL_TIMEOUT 8:8 /* RWEVF */ +#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_RSTSEQ_CLKCTL_TIMEOUT_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_RSTSEQ_CLKCTL_TIMEOUT_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_CLKCTL_REQUEST_TIMEOUT 9:9 /* RWEVF */ +#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_CLKCTL_REQUEST_TIMEOUT_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_CLKCTL_REQUEST_TIMEOUT_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0 0x0000028c /* RW-4R */ +#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_SLEEPWHILEACTIVELINK 0:0 /* RWEVF */ +#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_SLEEPWHILEACTIVELINK_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_SLEEPWHILEACTIVELINK_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_ILLEGALLINKSTATEREQUEST 1:1 /* RWEVF */ +#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_ILLEGALLINKSTATEREQUEST_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_ILLEGALLINKSTATEREQUEST_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_FAILEDMINIONREQUEST 2:2 /* RWEVF */ +#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_FAILEDMINIONREQUEST_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_FAILEDMINIONREQUEST_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_RESERVEDREQUESTVALUE 3:3 /* RWEVF */ +#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_RESERVEDREQUESTVALUE_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_RESERVEDREQUESTVALUE_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_LINKSTATEWRITEWHILEBUSY 4:4 /* RWEVF */ +#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_LINKSTATEWRITEWHILEBUSY_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_LINKSTATEWRITEWHILEBUSY_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_LINK_STATE_REQUEST_TIMEOUT 5:5 /* RWEVF */ +#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_LINK_STATE_REQUEST_TIMEOUT_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_LINK_STATE_REQUEST_TIMEOUT_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR 6:6 /* RWEVF */ +#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_RSTSEQ_PHYCTL_TIMEOUT 7:7 /* RWEVF */ +#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_RSTSEQ_PHYCTL_TIMEOUT_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_RSTSEQ_PHYCTL_TIMEOUT_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_RSTSEQ_CLKCTL_TIMEOUT 8:8 /* RWEVF */ +#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_RSTSEQ_CLKCTL_TIMEOUT_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_RSTSEQ_CLKCTL_TIMEOUT_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_CLKCTL_REQUEST_TIMEOUT 9:9 /* RWEVF */ +#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_CLKCTL_REQUEST_TIMEOUT_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_CLKCTL_REQUEST_TIMEOUT_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_CORRECTABLE_REPORT_EN_0 0x00000290 /* RW-4R */ +#define NV_NVLIPT_LNK_ERR_FIRST_0 0x0000029c /* RW-4R */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_SLEEPWHILEACTIVELINK 0:0 /* RWIVF */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_SLEEPWHILEACTIVELINK__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_SLEEPWHILEACTIVELINK_NONE 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_SLEEPWHILEACTIVELINK_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_ILLEGALLINKSTATEREQUEST 1:1 /* RWIVF */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_ILLEGALLINKSTATEREQUEST__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_ILLEGALLINKSTATEREQUEST_NONE 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_ILLEGALLINKSTATEREQUEST_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_FAILEDMINIONREQUEST 2:2 /* RWIVF */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_FAILEDMINIONREQUEST__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_FAILEDMINIONREQUEST_NONE 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_FAILEDMINIONREQUEST_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_RESERVEDREQUESTVALUE 3:3 /* RWIVF */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_RESERVEDREQUESTVALUE__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_RESERVEDREQUESTVALUE_NONE 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_RESERVEDREQUESTVALUE_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_LINKSTATEWRITEWHILEBUSY 4:4 /* RWIVF */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_LINKSTATEWRITEWHILEBUSY__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_LINKSTATEWRITEWHILEBUSY_NONE 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_LINKSTATEWRITEWHILEBUSY_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_LINK_STATE_REQUEST_TIMEOUT 5:5 /* RWIVF */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_LINK_STATE_REQUEST_TIMEOUT__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_LINK_STATE_REQUEST_TIMEOUT_NONE 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_LINK_STATE_REQUEST_TIMEOUT_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR 6:6 /* RWIVF */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR_NONE 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_RSTSEQ_PHYCTL_TIMEOUT 7:7 /* RWIVF */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_RSTSEQ_PHYCTL_TIMEOUT__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_RSTSEQ_PHYCTL_TIMEOUT_NONE 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_RSTSEQ_PHYCTL_TIMEOUT_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_RSTSEQ_CLKCTL_TIMEOUT 8:8 /* RWIVF */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_RSTSEQ_CLKCTL_TIMEOUT__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_RSTSEQ_CLKCTL_TIMEOUT_NONE 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_RSTSEQ_CLKCTL_TIMEOUT_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_CLKCTL_REQUEST_TIMEOUT 9:9 /* RWIVF */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_CLKCTL_REQUEST_TIMEOUT__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_CLKCTL_REQUEST_TIMEOUT_NONE 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_ERR_FIRST_0_CLKCTL_REQUEST_TIMEOUT_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_INTR_CONTROL_LINK 0x00000300 /* RW-4R */ +#define NV_NVLIPT_LNK_INTR_CONTROL_LINK_INT0_EN 0:0 /* RWEVF */ +#define NV_NVLIPT_LNK_INTR_CONTROL_LINK_INT0_EN_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_INTR_CONTROL_LINK_INT0_EN_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_INTR_CONTROL_LINK_INT1_EN 1:1 /* RWEVF */ +#define NV_NVLIPT_LNK_INTR_CONTROL_LINK_INT1_EN_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_INTR_CONTROL_LINK_INT1_EN_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_INTR_STATUS 0x00000304 /* RW-4R */ +#define NV_NVLIPT_LNK_INTR_STATUS_LINKSTATEREQUESTREADYSET 0:0 /* RWEVF */ +#define NV_NVLIPT_LNK_INTR_STATUS_LINKSTATEREQUESTREADYSET__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_LNK_INTR_STATUS_LINKSTATEREQUESTREADYSET_PENDING 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_INTR_STATUS_LINKSTATEREQUESTREADYSET_CLEAR 0x00000000 /* RW--V */ +#define NV_NVLIPT_LNK_INTR_STATUS_LINKSTATEREQUESTREADYSET_INIT 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_INTR_STATUS_MINIONREQUEST 1:1 /* RWEVF */ +#define NV_NVLIPT_LNK_INTR_STATUS_MINIONREQUEST__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_LNK_INTR_STATUS_MINIONREQUEST_PENDING 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_INTR_STATUS_MINIONREQUEST_CLEAR 0x00000000 /* RW--V */ +#define NV_NVLIPT_LNK_INTR_STATUS_MINIONREQUEST_INIT 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_INTR_INT0_EN 0x00000308 /* RW-4R */ +#define NV_NVLIPT_LNK_INTR_INT0_EN_LINKSTATEREQUESTREADYSET 0:0 /* RWEVF */ +#define NV_NVLIPT_LNK_INTR_INT0_EN_LINKSTATEREQUESTREADYSET_PENDING 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_INTR_INT0_EN_LINKSTATEREQUESTREADYSET_DISABLE 0x00000000 /* RW--V */ +#define NV_NVLIPT_LNK_INTR_INT0_EN_LINKSTATEREQUESTREADYSET_INIT 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_INTR_INT0_EN_MINIONREQUEST 1:1 /* RWEVF */ +#define NV_NVLIPT_LNK_INTR_INT0_EN_MINIONREQUEST_PENDING 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_INTR_INT0_EN_MINIONREQUEST_DISABLE 0x00000000 /* RW--V */ +#define NV_NVLIPT_LNK_INTR_INT0_EN_MINIONREQUEST_INIT 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_INTR_INT1_EN 0x0000030c /* RW-4R */ +#define NV_NVLIPT_LNK_INTR_INT1_EN_LINKSTATEREQUESTREADYSET 0:0 /* RWEVF */ +#define NV_NVLIPT_LNK_INTR_INT1_EN_LINKSTATEREQUESTREADYSET_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_INTR_INT1_EN_LINKSTATEREQUESTREADYSET_DISABLE 0x00000000 /* RW--V */ +#define NV_NVLIPT_LNK_INTR_INT1_EN_LINKSTATEREQUESTREADYSET_INIT 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_INTR_INT1_EN_MINIONREQUEST 1:1 /* RWEVF */ +#define NV_NVLIPT_LNK_INTR_INT1_EN_MINIONREQUEST_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_INTR_INT1_EN_MINIONREQUEST_DISABLE 0x00000000 /* RW--V */ +#define NV_NVLIPT_LNK_INTR_INT1_EN_MINIONREQUEST_INIT 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_INTR_MINION_STATUS 0x00000314 /* RW-4R */ +#define NV_NVLIPT_LNK_RESET_RSTSEQ_LINK_RESET 0x00000380 /* RW-4R */ +#define NV_NVLIPT_LNK_RESET_RSTSEQ_LINK_RESET_LINK_RESET 0:0 /* RWEVF */ +#define NV_NVLIPT_LNK_RESET_RSTSEQ_LINK_RESET_LINK_RESET_DEASSERT 0x00000000 /* RW--V */ +#define NV_NVLIPT_LNK_RESET_RSTSEQ_LINK_RESET_LINK_RESET_ASSERT 0x00000001 /* RWE-V */ +#define NV_NVLIPT_LNK_RESET_RSTSEQ_LINK_RESET_LINK_RESET_STATUS 1:1 /* R-EVF */ +#define NV_NVLIPT_LNK_RESET_RSTSEQ_LINK_RESET_LINK_RESET_STATUS_DEASSERTED 0x00000000 /* R---V */ +#define NV_NVLIPT_LNK_RESET_RSTSEQ_LINK_RESET_LINK_RESET_STATUS_ASSERTED 0x00000001 /* R-E-V */ +#define NV_NVLIPT_LNK_PWRM_CTRL 0x00000400 /* RW-4R */ +#define NV_NVLIPT_LNK_PWRM_CTRL_L1_CURRENT_STATE 2:2 /* R-EVF */ +#define NV_NVLIPT_LNK_PWRM_CTRL_L1_CURRENT_STATE_L1 0x00000001 /* R---V */ +#define NV_NVLIPT_LNK_PWRM_CTRL_L1_CURRENT_STATE_NOT_L1 0x00000000 /* R-E-V */ +#define NV_NVLIPT_LNK_PWRM_CTRL_L1_REMOTE_DESIRED 3:3 /* R-EVF */ +#define NV_NVLIPT_LNK_PWRM_CTRL_L1_REMOTE_DESIRED_L1 0x00000001 /* R---V */ +#define NV_NVLIPT_LNK_PWRM_CTRL_L1_REMOTE_DESIRED_ACTIVE 0x00000000 /* R-E-V */ +#define NV_NVLIPT_LNK_PWRM_CTRL_L1_HARDWARE_DESIRED 4:4 /* R-EVF */ +#define NV_NVLIPT_LNK_PWRM_CTRL_L1_HARDWARE_DESIRED_L1 0x00000001 /* R---V */ +#define NV_NVLIPT_LNK_PWRM_CTRL_L1_HARDWARE_DESIRED_ACTIVE 0x00000000 /* R-E-V */ +#define NV_NVLIPT_LNK_PWRM_CTRL_L1_SOFTWARE_DESIRED 8:8 /* RWEVF */ +#define NV_NVLIPT_LNK_PWRM_CTRL_L1_SOFTWARE_DESIRED_L1 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_PWRM_CTRL_L1_SOFTWARE_DESIRED_ACTIVE 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_PWRM_CTRL_L1_HARDWARE_DISABLE 9:9 /* RWEVF */ +#define NV_NVLIPT_LNK_PWRM_CTRL_L1_HARDWARE_DISABLE_HW_MONITOR_DISABLE 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_PWRM_CTRL_L1_HARDWARE_DISABLE_HW_MONITOR_ENABLED 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_PWRM_CTRL_L1_COUNT_ENABLE 10:10 /* RWEVF */ +#define NV_NVLIPT_LNK_PWRM_CTRL_L1_COUNT_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_PWRM_CTRL_L1_COUNT_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_PWRM_CTRL_L1D_ENABLE 11:11 /* RWEVF */ +#define NV_NVLIPT_LNK_PWRM_CTRL_L1D_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_PWRM_CTRL_L1D_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_PWRM_L1_ENTER_THRESHOLD 0x0000040c /* RW-4R */ +#define NV_NVLIPT_LNK_PWRM_L1_ENTER_THRESHOLD_THRESHOLD 12:0 /* RWEVF */ +#define NV_NVLIPT_LNK_PWRM_L1_ENTER_THRESHOLD_THRESHOLD_INIT 0x000001ff /* RWE-V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST 0x00000480 /* RW-4R */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST 3:0 /* RWEVF */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_NOP 0x00000000 /* RWE-V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_ACTIVE 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_L2 0x00000002 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_EMPTY 0x00000008 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_RESET 0x00000009 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_SHUTDOWN 0x0000000d /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS 15:8 /* R-EVF */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_INIT 0x00000000 /* R-E-V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_REQUEST_SUCCESSFUL 0x00000001 /* R---V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_ILLEGAL_STATE_REQUEST 0x00000002 /* R---V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_RESET_SEQ_TIMEOUT 0x00000003 /* R---V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_MINION_REQUEST_NOT_ENABLED 0x00000004 /* R---V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_REQUEST_TIMEOUT 0x00000005 /* R---V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_MINION_REQUEST_FAIL 0x00000080 /* R---V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_MINION_REQUEST_FAIL_FATAL 0x000000ff /* R---V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_ACTIVE_FAIL_BAD_STATE 0x00000081 /* R---V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_ACTIVE_FAIL_RXDET 0x00000082 /* R---V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_ACTIVE_FAIL_NEGOTIATION 0x00000083 /* R---V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_ACTIVE_FAIL_HS 0x00000084 /* R---V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_ERR 30:30 /* R-EVF */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_ERR_NOERR 0x00000000 /* R-E-V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_ERR_ERR 0x00000001 /* R---V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_READY 31:31 /* R-EVF */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_READY_INIT 0x00000001 /* R-E-V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS 0x00000484 /* R--4R */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_CURRENTLINKSTATE 3:0 /* R-EVF */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_CURRENTLINKSTATE_ACTIVE 0x00000001 /* R---V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_CURRENTLINKSTATE_L2 0x00000002 /* R---V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_CURRENTLINKSTATE_ACTIVE_PENDING 0x00000005 /* R---V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_CURRENTLINKSTATE_EMPTY 0x00000008 /* R---V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_CURRENTLINKSTATE_RESET 0x00000009 /* R-E-V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_CURRENTLINKSTATE_SHUTDOWN 0x0000000d /* R---V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_CURRENTLINKSTATE_CONTAIN 0x0000000e /* R---V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_CURRENTLINKSTATE_DISABLE 0x0000000f /* R---V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_TXTLBUFFEREMPTY 8:8 /* R-EVF */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_TXTLBUFFEREMPTY_INIT 0x00000000 /* R-E-V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_TXREPLAYBUFFEREMPTY 9:9 /* R-EVF */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_TXREPLAYBUFFEREMPTY_INIT 0x00000000 /* R-E-V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_RXTLBUFFEREMPTY 11:11 /* R-EVF */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_RXTLBUFFEREMPTY_INIT 0x00000000 /* R-E-V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_RMTTXBUFFEREMPTY 13:13 /* R-EVF */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_RMTTXBUFFEREMPTY_INIT 0x00000000 /* R-E-V */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_RMTRXBUFFEREMPTY 14:14 /* R-EVF */ +#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_RMTRXBUFFEREMPTY_INIT 0x00000000 /* R-E-V */ +#define NV_NVLIPT_LNK_DEBUG_CLEAR 0x00000504 /* RW-4R */ +#define NV_NVLIPT_LNK_DEBUG_CLEAR_CLEAR 0:0 /* RWIVF */ +#define NV_NVLIPT_LNK_DEBUG_CLEAR_CLEAR_ASSERT 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_DEBUG_CLEAR_CLEAR_DEASSERT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL 0x0000060c /* RW-4R */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE 15:8 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_100_00000_GBPS 0x00000009 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_106_25000_GBPS 0x0000000a /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_ILLEGAL_LINE_RATE 0x000000ff /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL 0x00000618 /* RW-4R */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_AC_DC_MODE 0:0 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_AC_DC_MODE_AC 0x00000001 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_AC_DC_MODE_DC 0x00000000 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_LINE_CODE_MODE 2:1 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_LINE_CODE_MODE_NRZ 0x00000000 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_LINE_CODE_MODE_PAM4 0x00000003 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_RECEIVER_DETECT_ENABLE 3:3 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_RECEIVER_DETECT_ENABLE_ENABLE 0x00000001 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_RECEIVER_DETECT_ENABLE_DISABLE 0x00000000 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_BLOCK_CODE_MODE 7:6 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_BLOCK_CODE_MODE_OFF 0x00000000 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_BLOCK_CODE_MODE_ECC89_ENABLED 0x00000001 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_FOM_FORMAT 10:8 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_FOM_FORMAT_INIT 0x00000005 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_FOM_FORMAT_FOMA 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_FOM_FORMAT_FOMB 0x00000002 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_FOM_FORMAT_FOMC 0x00000004 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_OPTIMIZATION_ALGORITHM 18:11 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_OPTIMIZATION_ALGORITHM_INIT 0x00000017 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_OPTIMIZATION_ALGORITHM_A0 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_OPTIMIZATION_ALGORITHM_A1 0x00000002 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_OPTIMIZATION_ALGORITHM_A2 0x00000004 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_OPTIMIZATION_ALGORITHM_A3 0x00000008 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_OPTIMIZATION_ALGORITHM_A4 0x00000010 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_OPTIMIZATION_ALGORITHM_A5 0x00000020 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_OPTIMIZATION_ALGORITHM_A6 0x00000040 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_OPTIMIZATION_ALGORITHM_A7 0x00000080 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_ADJUSTMENT_ALGORITHM 23:19 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_ADJUSTMENT_ALGORITHM_B0 0x00000001 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_ADJUSTMENT_ALGORITHM_B1 0x00000002 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_ADJUSTMENT_ALGORITHM_B2 0x00000004 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_ADJUSTMENT_ALGORITHM_B3 0x00000008 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_MINIMUM_TRAIN_TIME_MANTISSA 27:24 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_MINIMUM_TRAIN_TIME_MANTISSA_INIT 0x00000002 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_MINIMUM_TRAIN_TIME_EXPONENT 31:28 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_MINIMUM_TRAIN_TIME_EXPONENT_INIT 0x00000003 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2 0x00000624 /* RW-4R */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESTORE_PHY_TRAINING_PARAMS 0:0 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESTORE_PHY_TRAINING_PARAMS_ENABLE 0x00000001 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESTORE_PHY_TRAINING_PARAMS_DISABLE 0x00000000 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_ALI_ENABLE 1:1 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_ALI_ENABLE_ENABLE 0x00000001 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_ALI_ENABLE_DISABLE 0x00000000 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_L1_MINIMUM_RECALIBRATION_TIME_MANTISSA 6:2 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_L1_MINIMUM_RECALIBRATION_TIME_MANTISSA_INIT 0x00000001 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_L1_MINIMUM_RECALIBRATION_TIME_EXPONENT 11:8 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_L1_MINIMUM_RECALIBRATION_TIME_EXPONENT_INIT 0x00000004 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_L1_MAXIMUM_RECALIBRATION_PERIOD_MANTISSA 17:13 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_L1_MAXIMUM_RECALIBRATION_PERIOD_MANTISSA_INIT 0x00000019 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_L1_MAXIMUM_RECALIBRATION_PERIOD_EXPONENT 22:19 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_L1_MAXIMUM_RECALIBRATION_PERIOD_EXPONENT_INIT 0x00000004 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_DISABLE_UPHY_MICROCODE_LOAD 24:24 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_DISABLE_UPHY_MICROCODE_LOAD_UPHY_MICROCODE_LOAD_DISABLED 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_DISABLE_UPHY_MICROCODE_LOAD_UPHY_MICROCODE_LOAD_ENABLED 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_CHANNEL_TYPE 28:25 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_CHANNEL_TYPE_GENERIC 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_CHANNEL_TYPE_ACTIVE_0 0x00000004 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_CHANNEL_TYPE_ACTIVE_1 0x00000005 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_CHANNEL_TYPE_ACTIVE_CABLE_0 0x00000008 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_CHANNEL_TYPE_ACTIVE_CABLE_1 0x00000009 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_CHANNEL_TYPE_OPTICAL_CABLE_0 0x0000000c /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_CHANNEL_TYPE_OPTICAL_CABLE_1 0x0000000d /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_CHANNEL_TYPE_DIRECT_0 0x0000000e /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_29 29:29 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_29_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_30 30:30 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_30_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_31 31:31 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_31_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK 0x00000628 /* RW-4R */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_RESTORE_PHY_TRAINING_PARAMS 0:0 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_RESTORE_PHY_TRAINING_PARAMS__ONWRITE "oneToSet" /* */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_RESTORE_PHY_TRAINING_PARAMS_UNLOCKED 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_RESTORE_PHY_TRAINING_PARAMS_LOCKED 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_ALI_ENABLE 1:1 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_ALI_ENABLE__ONWRITE "oneToSet" /* */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_ALI_ENABLE_UNLOCKED 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_ALI_ENABLE_LOCKED 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_L1_MINIMUM_RECALIBRATION_TIME_MANTISSA 2:2 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_L1_MINIMUM_RECALIBRATION_TIME_MANTISSA__ONWRITE "oneToSet" /* */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_L1_MINIMUM_RECALIBRATION_TIME_MANTISSA_UNLOCKED 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_L1_MINIMUM_RECALIBRATION_TIME_MANTISSA_LOCKED 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_L1_MINIMUM_RECALIBRATION_TIME_EXPONENT 3:3 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_L1_MINIMUM_RECALIBRATION_TIME_EXPONENT__ONWRITE "oneToSet" /* */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_L1_MINIMUM_RECALIBRATION_TIME_EXPONENT_UNLOCKED 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_L1_MINIMUM_RECALIBRATION_TIME_EXPONENT_LOCKED 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_L1_MAXIMUM_RECALIBRATION_PERIOD_MANTISSA 4:4 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_L1_MAXIMUM_RECALIBRATION_PERIOD_MANTISSA__ONWRITE "oneToSet" /* */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_L1_MAXIMUM_RECALIBRATION_PERIOD_MANTISSA_UNLOCKED 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_L1_MAXIMUM_RECALIBRATION_PERIOD_MANTISSA_LOCKED 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_L1_MAXIMUM_RECALIBRATION_PERIOD_EXPONENT 5:5 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_L1_MAXIMUM_RECALIBRATION_PERIOD_EXPONENT__ONWRITE "oneToSet" /* */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_L1_MAXIMUM_RECALIBRATION_PERIOD_EXPONENT_UNLOCKED 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_L1_MAXIMUM_RECALIBRATION_PERIOD_EXPONENT_LOCKED 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_DISABLE_UPHY_MICROCODE_LOAD 6:6 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_DISABLE_UPHY_MICROCODE_LOAD__ONWRITE "oneToSet" /* */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_DISABLE_UPHY_MICROCODE_LOAD_UNLOCKED 0x00000000 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_DISABLE_UPHY_MICROCODE_LOAD_LOCKED 0x00000001 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CHANNEL_TYPE 7:7 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CHANNEL_TYPE__ONWRITE "oneToSet" /* */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CHANNEL_TYPE_UNLOCKED 0x00000000 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CHANNEL_TYPE_LOCKED 0x00000001 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_RESERVED_29 8:8 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_RESERVED_29__ONWRITE "oneToSet" /* */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_RESERVED_29_UNLOCKED 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_RESERVED_29_LOCKED 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_RESERVED_30 9:9 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_RESERVED_30__ONWRITE "oneToSet" /* */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_RESERVED_30_UNLOCKED 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_RESERVED_30_LOCKED 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_RESERVED_31 10:10 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_RESERVED_31__ONWRITE "oneToSet" /* */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_RESERVED_31_UNLOCKED 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_RESERVED_31_LOCKED 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR 0x0000062c /* RW-4R */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_RESTORE_PHY_TRAINING_PARAMS 0:0 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_RESTORE_PHY_TRAINING_PARAMS__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_RESTORE_PHY_TRAINING_PARAMS_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_RESTORE_PHY_TRAINING_PARAMS_UNLOCK 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_ALI_ENABLE 1:1 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_ALI_ENABLE__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_ALI_ENABLE_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_ALI_ENABLE_UNLOCK 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_L1_MINIMUM_RECALIBRATION_TIME_MANTISSA 2:2 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_L1_MINIMUM_RECALIBRATION_TIME_MANTISSA__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_L1_MINIMUM_RECALIBRATION_TIME_MANTISSA_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_L1_MINIMUM_RECALIBRATION_TIME_MANTISSA_UNLOCK 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_L1_MINIMUM_RECALIBRATION_TIME_EXPONENT 3:3 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_L1_MINIMUM_RECALIBRATION_TIME_EXPONENT__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_L1_MINIMUM_RECALIBRATION_TIME_EXPONENT_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_L1_MINIMUM_RECALIBRATION_TIME_EXPONENT_UNLOCK 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_L1_MAXIMUM_RECALIBRATION_PERIOD_MANTISSA 4:4 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_L1_MAXIMUM_RECALIBRATION_PERIOD_MANTISSA__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_L1_MAXIMUM_RECALIBRATION_PERIOD_MANTISSA_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_L1_MAXIMUM_RECALIBRATION_PERIOD_MANTISSA_UNLOCK 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_L1_MAXIMUM_RECALIBRATION_PERIOD_EXPONENT 5:5 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_L1_MAXIMUM_RECALIBRATION_PERIOD_EXPONENT__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_L1_MAXIMUM_RECALIBRATION_PERIOD_EXPONENT_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_L1_MAXIMUM_RECALIBRATION_PERIOD_EXPONENT_UNLOCK 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_DISABLE_UPHY_MICROCODE_LOAD 6:6 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_DISABLE_UPHY_MICROCODE_LOAD__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_DISABLE_UPHY_MICROCODE_LOAD_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_DISABLE_UPHY_MICROCODE_LOAD_UNLOCK 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_CHANNEL_TYPE 7:7 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_CHANNEL_TYPE__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_CHANNEL_TYPE_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_CHANNEL_TYPE_UNLOCK 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_RESERVED_29 8:8 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_RESERVED_29__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_RESERVED_29_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_RESERVED_29_UNLOCK 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_RESERVED_30 9:9 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_RESERVED_30__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_RESERVED_30_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_RESERVED_30_UNLOCK 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_RESERVED_31 10:10 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_RESERVED_31__ONWRITE "oneToClear" /* */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_RESERVED_31_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_LOCK_CLEAR_RESERVED_31_UNLOCK 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL 0x00000638 /* RW-4R */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_PWRM_L1_ENABLE 1:1 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_PWRM_L1_ENABLE_ENABLE 0x00000001 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_PWRM_L1_ENABLE_DISABLE 0x00000000 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_PWRM_L2_ENABLE 2:2 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_PWRM_L2_ENABLE_ENABLE 0x00000001 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_PWRM_L2_ENABLE_DISABLE 0x00000000 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_3 3:3 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_3_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_4 4:4 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_4_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_5 5:5 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_5_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_6 6:6 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_6_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_7 7:7 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_7_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_8 8:8 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_8_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_9 9:9 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_9_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_10 10:10 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_10_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_11 11:11 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_11_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_12 12:12 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_12_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_13 13:13 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_13_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_14 14:14 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_14_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_15 15:15 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_15_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_16 16:16 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_16_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_17 17:17 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_17_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_18 18:18 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_18_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_19 19:19 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_19_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_20 20:20 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_20_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_21 21:21 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_21_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_22 22:22 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_22_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_23 23:23 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_23_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_24 24:24 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_24_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_25 25:25 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_25_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_26 26:26 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_26_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_27 27:27 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_27_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_28 28:28 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_28_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_29 29:29 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_29_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_30 30:30 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_30_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_31 31:31 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_31_INIT 0x00000000 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_LOCK 0x0000063c /* RW-4R */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL 0x00000680 /* RW-4R */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_AC_DC_SUPPORT 1:0 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_AC_DC_SUPPORT_DC 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_AC_DC_SUPPORT_AC 0x00000002 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_AC_DC_SUPPORT_AC_AND_DC 0x00000003 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_LINE_CODE_SUPPORT 5:2 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_LINE_CODE_SUPPORT_INIT 0x00000009 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_LINE_CODE_SUPPORT_NRZ 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_LINE_CODE_SUPPORT_PAM4 0x00000008 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_RECEIVER_DETECT_SUPPORT 6:6 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_RECEIVER_DETECT_SUPPORT_SUPPORTED 0x00000001 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_RECEIVER_DETECT_SUPPORT_NOT_SUPPORTED 0x00000000 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_BLOCK_CODE_SUPPORT 9:7 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_BLOCK_CODE_SUPPORT_INIT 0x00000003 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_BLOCK_CODE_SUPPORT_NONE 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_BLOCK_CODE_SUPPORT_ECC89 0x00000002 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_FOM_FORMAT_SUPPORT 12:10 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_FOM_FORMAT_SUPPORT_INIT 0x00000005 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_FOM_FORMAT_SUPPORT_FOMA 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_FOM_FORMAT_SUPPORT_FOMB 0x00000002 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_FOM_FORMAT_SUPPORT_FOMC 0x00000004 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_OPTIMIZATION_ALGORITHM_SUPPORT 22:15 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_OPTIMIZATION_ALGORITHM_SUPPORT_INIT 0x00000017 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_OPTIMIZATION_ALGORITHM_SUPPORT_A0 0x00000001 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_OPTIMIZATION_ALGORITHM_SUPPORT_A1 0x00000002 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_OPTIMIZATION_ALGORITHM_SUPPORT_A2 0x00000004 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_OPTIMIZATION_ALGORITHM_SUPPORT_A3 0x00000008 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_OPTIMIZATION_ALGORITHM_SUPPORT_A4 0x00000010 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_OPTIMIZATION_ALGORITHM_SUPPORT_A5 0x00000020 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_OPTIMIZATION_ALGORITHM_SUPPORT_A6 0x00000040 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_OPTIMIZATION_ALGORITHM_SUPPORT_A7 0x00000080 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_ADJUSTMENT_ALGORITHM_SUPPORT 27:23 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_ADJUSTMENT_ALGORITHM_SUPPORT_B0 0x00000001 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_ADJUSTMENT_ALGORITHM_SUPPORT_B1 0x00000002 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_ADJUSTMENT_ALGORITHM_SUPPORT_B2 0x00000004 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_TXTRAIN_ADJUSTMENT_ALGORITHM_SUPPORT_B3 0x00000008 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_ALI_SUPPORT 28:28 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_ALI_SUPPORT_SUPPORTED 0x00000001 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_ALI_SUPPORT_NOT_SUPPORTED 0x00000000 /* RW--V */ +#endif // __ls10_dev_nvlipt_lnk_ip_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_nvlphyctl_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_nvlphyctl_ip.h new file mode 100644 index 000000000..a4f1a950d --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_nvlphyctl_ip.h @@ -0,0 +1,71 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_nvlphyctl_ip_h__ +#define __ls10_dev_nvlphyctl_ip_h__ +/* This file is autogenerated. Do not edit */ +#define NV_NVLPHYCTL 0x00002DFF:0x00002800 /* RW--D */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS 0x00002840 /* RW-4R */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PMREQ 3:0 /* RWEVF */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PMREQ_NOP 0x00000000 /* RWE-V */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PMREQ_TO_PSDI 0x00000002 /* RW--V */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PMREQ_TO_PSL0 0x00000004 /* RW--V */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PMREQ_TO_PSL1 0x00000006 /* RW--V */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PMREQ_TO_PSL2 0x00000008 /* RW--V */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PMSTS 7:4 /* R-EVF */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PMSTS_NOP 0x00000000 /* R---V */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PMSTS_PSDI 0x00000002 /* R---V */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PMSTS_PSL0 0x00000004 /* R---V */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PMSTS_PSL1 0x00000006 /* R---V */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PMSTS_PSL2 0x00000008 /* R-E-V */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PMSTS_PSERR 0x0000000a /* R---V */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PMBUSY 8:8 /* R-EVF */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PMBUSY_OFF 0x00000000 /* R-E-V */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PMBUSY_ON 0x00000001 /* R---V */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PSL1TXSLEEPVAL 10:9 /* RWEVF */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PSL1TXSLEEPVAL_INIT 0x00000002 /* RWE-V */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PSL1RXSLEEPVAL 12:11 /* RWEVF */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PSL1RXSLEEPVAL_INIT 0x00000003 /* RWE-V */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PSDITXSLEEPVAL 14:13 /* RWEVF */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PSDITXSLEEPVAL_INIT 0x00000000 /* RWE-V */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PSDIRXSLEEPVAL 16:15 /* RWEVF */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PSDIRXSLEEPVAL_INIT 0x00000000 /* RWE-V */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_TXCLK_SWITCH_TIMEOUT_ERR 17:17 /* RWEVF */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_TXCLK_SWITCH_TIMEOUT_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_TXCLK_SWITCH_TIMEOUT_ERR_OFF 0x00000000 /* RWE-V */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_TXCLK_SWITCH_TIMEOUT_ERR_ON 0x00000001 /* RW--V */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PHYARB_TIMEOUT_ERR 18:18 /* RWEVF */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PHYARB_TIMEOUT_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PHYARB_TIMEOUT_ERR_OFF 0x00000000 /* RWE-V */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_PHYARB_TIMEOUT_ERR_ON 0x00000001 /* RW--V */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_INVLD_PMREQ_ERR 19:19 /* RWEVF */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_INVLD_PMREQ_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_INVLD_PMREQ_ERR_OFF 0x00000000 /* RWE-V */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_INVLD_PMREQ_ERR_ON 0x00000001 /* RW--V */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_RSTPWRDN_DLY 20:20 /* RWEVF */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_RSTPWRDN_DLY_DIS 0x00000000 /* RWE-V */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_RSTPWRDN_DLY_EN 0x00000001 /* RW--V */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_RSTPWRDN_PSL2DLY 21:21 /* RWEVF */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_RSTPWRDN_PSL2DLY_DIS 0x00000000 /* RW--V */ +#define NV_NVLPHYCTL_COMMON_PSAVE_UCODE_CTRL_STS_RSTPWRDN_PSL2DLY_EN 0x00000001 /* RWE-V */ +#endif // __ls10_dev_nvlphyctl_ip_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_nvlsaw_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_nvlsaw_ip.h new file mode 100644 index 000000000..9b18d4479 --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_nvlsaw_ip.h @@ -0,0 +1,99 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_nvlsaw_ip_h__ +#define __ls10_dev_nvlsaw_ip_h__ +/* This file is autogenerated. Do not edit */ +#define NV_NVLSAW 0x000007FF:0x00000000 /* RW--D */ +#define NV_NVLSAW_GLBLLATENCYTIMERCTRL 0x00000040 /* RW-4R */ +#define NV_NVLSAW_GLBLLATENCYTIMERCTRL_ENABLE 0:0 /* RWEVF */ +#define NV_NVLSAW_GLBLLATENCYTIMERCTRL_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLSAW_GLBLLATENCYTIMERCTRL_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLSAW_GLBLLATENCYTIMERCTRL_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_NVLSAW_CTRL_CLOCK_GATING 0x00000064 /* RW-4R */ +#define NV_NVLSAW_CTRL_CLOCK_GATING_CG1_SLCG_SAW 0:0 /* RWEVF */ +#define NV_NVLSAW_CTRL_CLOCK_GATING_CG1_SLCG_SAW_ENABLED 0x00000000 /* RW--V */ +#define NV_NVLSAW_CTRL_CLOCK_GATING_CG1_SLCG_SAW_DISABLED 0x00000001 /* RWE-V */ +#define NV_NVLSAW_CTRL_CLOCK_GATING_CG1_SLCG_SAW__PROD 0x00000000 /* RW--V */ +#define NV_NVLSAW_CTRL_CLOCK_GATING_CG1_SLCG_PCIE 2:2 /* RWEVF */ +#define NV_NVLSAW_CTRL_CLOCK_GATING_CG1_SLCG_PCIE_ENABLED 0x00000000 /* RW--V */ +#define NV_NVLSAW_CTRL_CLOCK_GATING_CG1_SLCG_PCIE_DISABLED 0x00000001 /* RWE-V */ +#define NV_NVLSAW_CTRL_CLOCK_GATING_CG1_SLCG_PCIE__PROD 0x00000000 /* RW--V */ +#define NV_NVLSAW_SW_SCRATCH_0 0x000004e0 /* RW-4R */ +#define NV_NVLSAW_SW_SCRATCH_0_VALUE 31:0 /* RWEVF */ +#define NV_NVLSAW_SW_SCRATCH_0_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_NVLSAW_SW_SCRATCH_1 0x000004e4 /* RW-4R */ +#define NV_NVLSAW_SW_SCRATCH_1_VALUE 31:0 /* RWEVF */ +#define NV_NVLSAW_SW_SCRATCH_1_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_NVLSAW_SW_SCRATCH_2 0x000004e8 /* RW-4R */ +#define NV_NVLSAW_SW_SCRATCH_2_VALUE 31:0 /* RWEVF */ +#define NV_NVLSAW_SW_SCRATCH_2_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_NVLSAW_SW_SCRATCH_3 0x000004ec /* RW-4R */ +#define NV_NVLSAW_SW_SCRATCH_3_VALUE 31:0 /* RWEVF */ +#define NV_NVLSAW_SW_SCRATCH_3_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_NVLSAW_SW_SCRATCH_4 0x000004f0 /* RW-4R */ +#define NV_NVLSAW_SW_SCRATCH_4_VALUE 31:0 /* RWEVF */ +#define NV_NVLSAW_SW_SCRATCH_4_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_NVLSAW_SW_SCRATCH_5 0x000004f4 /* RW-4R */ +#define NV_NVLSAW_SW_SCRATCH_5_VALUE 31:0 /* RWEVF */ +#define NV_NVLSAW_SW_SCRATCH_5_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_NVLSAW_SW_SCRATCH_6 0x000004f8 /* RW-4R */ +#define NV_NVLSAW_SW_SCRATCH_6_VALUE 31:0 /* RWEVF */ +#define NV_NVLSAW_SW_SCRATCH_6_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_NVLSAW_SW_SCRATCH_7 0x000004fc /* RW-4R */ +#define NV_NVLSAW_SW_SCRATCH_7_VALUE 31:0 /* RWEVF */ +#define NV_NVLSAW_SW_SCRATCH_7_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_NVLSAW_SW_SCRATCH_8 0x00000500 /* RW-4R */ +#define NV_NVLSAW_SW_SCRATCH_8_VALUE 31:0 /* RWEVF */ +#define NV_NVLSAW_SW_SCRATCH_8_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_NVLSAW_SW_SCRATCH_9 0x00000504 /* RW-4R */ +#define NV_NVLSAW_SW_SCRATCH_9_VALUE 31:0 /* RWEVF */ +#define NV_NVLSAW_SW_SCRATCH_9_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_NVLSAW_SW_SCRATCH_10 0x00000508 /* RW-4R */ +#define NV_NVLSAW_SW_SCRATCH_10_VALUE 31:0 /* RWEVF */ +#define NV_NVLSAW_SW_SCRATCH_10_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_NVLSAW_SW_SCRATCH_11 0x0000050c /* RW-4R */ +#define NV_NVLSAW_SW_SCRATCH_11_VALUE 31:0 /* RWEVF */ +#define NV_NVLSAW_SW_SCRATCH_11_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_NVLSAW_SW_SCRATCH_12 0x00000510 /* RW-4R */ +#define NV_NVLSAW_SW_SCRATCH_12_VALUE 31:0 /* RWEVF */ +#define NV_NVLSAW_SW_SCRATCH_12_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_NVLSAW_SW_SCRATCH_13 0x00000514 /* RW-4R */ +#define NV_NVLSAW_SW_SCRATCH_13_VALUE 31:0 /* RWEVF */ +#define NV_NVLSAW_SW_SCRATCH_13_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_NVLSAW_SW_SCRATCH_14 0x00000518 /* RW-4R */ +#define NV_NVLSAW_SW_SCRATCH_14_VALUE 31:0 /* RWEVF */ +#define NV_NVLSAW_SW_SCRATCH_14_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_NVLSAW_SW_SCRATCH_15 0x0000051c /* RW-4R */ +#define NV_NVLSAW_SW_SCRATCH_15_VALUE 31:0 /* RWEVF */ +#define NV_NVLSAW_SW_SCRATCH_15_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_NVLSAW_PCIE_PRI_CLOCK_GATING 0x00000530 /* RW-4R */ +#define NV_NVLSAW_PCIE_PRI_CLOCK_GATING_CG1_SLCG 0:0 /* RWEVF */ +#define NV_NVLSAW_PCIE_PRI_CLOCK_GATING_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ +#define NV_NVLSAW_PCIE_PRI_CLOCK_GATING_CG1_SLCG_DISABLED 0x00000001 /* RWE-V */ +#define NV_NVLSAW_PCIE_PRI_CLOCK_GATING_CG1_SLCG__PROD 0x00000000 /* RW--V */ +#define NV_NVLSAW_SECURE_SCRATCH_WARM_GROUP_1(i) (0x00000c30+(i)*0x4) /* RW-4A */ +#define NV_NVLSAW_SECURE_SCRATCH_WARM_GROUP_1__SIZE_1 4 /* */ +#define NV_NVLSAW_SECURE_SCRATCH_WARM_GROUP_1_VALUE 31:0 /* RWEVF */ +#define NV_NVLSAW_SECURE_SCRATCH_WARM_GROUP_1_VALUE_INIT 0x00000000 /* RWE-V */ +#endif // __ls10_dev_nvlsaw_ip_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_nvlsaw_ip_addendum.h b/src/common/inc/swref/published/nvswitch/ls10/dev_nvlsaw_ip_addendum.h new file mode 100644 index 000000000..213927311 --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_nvlsaw_ip_addendum.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * @file dev_nvlsaw_ip_addendum.h + * @brief NVSwitch specific defines that are missing in the dev_nvlsaw_ip.h manual. + */ + +#ifndef __ls10_dev_nvlsaw_ip_addendum_h__ +#define __ls10_dev_nvlsaw_ip_addendum_h__ + +/* + * SOE ATTACH-DETACH registers to track SOE & Driver + * status for load and shutdown. + * + * SCRATCH_13 tracks status of SOE & + * SCRATCH_3 tracks status of driver + */ +#define NV_NVLSAW_SOE_ATTACH_DETACH NV_NVLSAW_SW_SCRATCH_3 +#define NV_NVLSAW_SOE_ATTACH_DETACH_STATUS 0:0 +#define NV_NVLSAW_SOE_ATTACH_DETACH_STATUS_ATTACHED 0x1 +#define NV_NVLSAW_SOE_ATTACH_DETACH_STATUS_DETACHED 0x0 + +#define NV_NVLSAW_DRIVER_ATTACH_DETACH NV_NVLSAW_SW_SCRATCH_13 +#define NV_NVLSAW_DRIVER_ATTACH_DETACH_STATUS 0:0 +#define NV_NVLSAW_DRIVER_ATTACH_DETACH_STATUS_ATTACHED 0x1 +#define NV_NVLSAW_DRIVER_ATTACH_DETACH_STATUS_DETACHED 0x0 +#define NV_NVLSAW_DRIVER_ATTACH_DETACH_DEVICE_RESET_REQUIRED 5:5 +#define NV_NVLSAW_DRIVER_ATTACH_DETACH_DEVICE_BLACKLIST_REASON 10:6 +#define NV_NVLSAW_DRIVER_ATTACH_DETACH_DEVICE_FABRIC_STATE 13:11 +#define NV_NVLSAW_DRIVER_ATTACH_DETACH_DRIVER_FABRIC_STATE 16:14 +#define NV_NVLSAW_DRIVER_ATTACH_DETACH_FABRIC_MANAGER_ERROR 23:17 +#define NV_NVLSAW_DRIVER_ATTACH_DETACH_EVENT_MESSAGE_COUNT 31:24 + +#endif //__ls10_dev_nvlsaw_ip_addendum_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_nvltlc_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_nvltlc_ip.h new file mode 100644 index 000000000..0ba19f66c --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_nvltlc_ip.h @@ -0,0 +1,940 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_nvltlc_ip_h__ +#define __ls10_dev_nvltlc_ip_h__ +/* This file is autogenerated. Do not edit */ +#define NV_NVLTLC_TX_SYS 0x000007FF:0x00000000 /* RW--D */ +#define NV_NVLTLC_RX_SYS 0x00000FFF:0x00000800 /* RW--D */ +#define NV_NVLTLC_TX_LNK 0x000017FF:0x00001000 /* RW--D */ +#define NV_NVLTLC_RX_LNK 0x00001FFF:0x00001800 /* RW--D */ +#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_READY 0x00000124 /* RW-4R */ +#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_READY_BUFFERRDY 0:0 /* RWEVF */ +#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_READY_BUFFERRDY__ONWRITE "oneToSet" /* */ +#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_READY_BUFFERRDY_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_READY_BUFFERRDY_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_SYS_ERR_STATUS_0 0x00000280 /* RW-4R */ +#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_PARITY_ERR 0:0 /* RWDVF */ +#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_PARITY_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_PARITY_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_PARITY_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_HDR_ECC_DBE_ERR 8:8 /* RWDVF */ +#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_HDR_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_DAT_ECC_DBE_ERR 9:9 /* RWDVF */ +#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_DAT_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_DAT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_DAT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_ECC_LIMIT_ERR 10:10 /* RWDVF */ +#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXPOISONDET 23:23 /* RWDVF */ +#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXPOISONDET__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXPOISONDET_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXPOISONDET_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXRSPSTATUS_HW_ERR 24:24 /* RWDVF */ +#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXRSPSTATUS_HW_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXRSPSTATUS_HW_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXRSPSTATUS_HW_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXRSPSTATUS_UR_ERR 25:25 /* RWDVF */ +#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXRSPSTATUS_UR_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXRSPSTATUS_UR_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXRSPSTATUS_UR_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXRSPSTATUS_PRIV_ERR 26:26 /* RWDVF */ +#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXRSPSTATUS_PRIV_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXRSPSTATUS_PRIV_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXRSPSTATUS_PRIV_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0 0x00000288 /* RW-4R */ +#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR 0:0 /* RWEVF */ +#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR 8:8 /* RWEVF */ +#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_DAT_ECC_DBE_ERR 9:9 /* RWEVF */ +#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_ECC_LIMIT_ERR 10:10 /* RWEVF */ +#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXPOISONDET 23:23 /* RWEVF */ +#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXPOISONDET_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXPOISONDET_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXRSPSTATUS_HW_ERR 24:24 /* RWEVF */ +#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXRSPSTATUS_HW_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXRSPSTATUS_HW_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXRSPSTATUS_UR_ERR 25:25 /* RWEVF */ +#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXRSPSTATUS_UR_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXRSPSTATUS_UR_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXRSPSTATUS_PRIV_ERR 26:26 /* RWEVF */ +#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXRSPSTATUS_PRIV_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXRSPSTATUS_PRIV_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_SYS_ERR_FIRST_0 0x0000029c /* RW-4R */ +#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_PARITY_ERR 0:0 /* RWDVF */ +#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_PARITY_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_PARITY_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_PARITY_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_HDR_ECC_DBE_ERR 8:8 /* RWDVF */ +#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_HDR_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_DAT_ECC_DBE_ERR 9:9 /* RWDVF */ +#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_DAT_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_DAT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_DAT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_ECC_LIMIT_ERR 10:10 /* RWDVF */ +#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXPOISONDET 23:23 /* RWDVF */ +#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXPOISONDET__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXPOISONDET_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXPOISONDET_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXRSPSTATUS_HW_ERR 24:24 /* RWDVF */ +#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXRSPSTATUS_HW_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXRSPSTATUS_HW_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXRSPSTATUS_HW_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXRSPSTATUS_UR_ERR 25:25 /* RWDVF */ +#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXRSPSTATUS_UR_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXRSPSTATUS_UR_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXRSPSTATUS_UR_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXRSPSTATUS_PRIV_ERR 26:26 /* RWDVF */ +#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXRSPSTATUS_PRIV_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXRSPSTATUS_PRIV_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXRSPSTATUS_PRIV_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_READY 0x00000924 /* RW-4R */ +#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_READY_BUFFERRDY 0:0 /* RWEVF */ +#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_READY_BUFFERRDY__ONWRITE "oneToSet" /* */ +#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_READY_BUFFERRDY_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_READY_BUFFERRDY_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_SYS_ERR_STATUS_0 0x00000a80 /* RW-4R */ +#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_NCISOC_PARITY_ERR 0:0 /* RWDVF */ +#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_NCISOC_PARITY_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_NCISOC_PARITY_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_NCISOC_PARITY_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_HDR_RAM_ECC_DBE_ERR 1:1 /* RWDVF */ +#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_HDR_RAM_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_HDR_RAM_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_HDR_RAM_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_HDR_RAM_ECC_LIMIT_ERR 2:2 /* RWDVF */ +#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_HDR_RAM_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_HDR_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_HDR_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT0_RAM_ECC_DBE_ERR 3:3 /* RWDVF */ +#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT0_RAM_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT0_RAM_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT0_RAM_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT0_RAM_ECC_LIMIT_ERR 4:4 /* RWDVF */ +#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT0_RAM_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT0_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT0_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT1_RAM_ECC_DBE_ERR 5:5 /* RWDVF */ +#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT1_RAM_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT1_RAM_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT1_RAM_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT1_RAM_ECC_LIMIT_ERR 6:6 /* RWDVF */ +#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT1_RAM_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT1_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT1_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0 0x00000a88 /* RW-4R */ +#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR 0:0 /* RWEVF */ +#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_HDR_RAM_ECC_DBE_ERR 1:1 /* RWEVF */ +#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_HDR_RAM_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_HDR_RAM_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_HDR_RAM_ECC_LIMIT_ERR 2:2 /* RWEVF */ +#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_HDR_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_HDR_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT0_RAM_ECC_DBE_ERR 3:3 /* RWEVF */ +#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT0_RAM_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT0_RAM_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT0_RAM_ECC_LIMIT_ERR 4:4 /* RWEVF */ +#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT0_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT0_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT1_RAM_ECC_DBE_ERR 5:5 /* RWEVF */ +#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT1_RAM_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT1_RAM_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT1_RAM_ECC_LIMIT_ERR 6:6 /* RWEVF */ +#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT1_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT1_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_SYS_ERR_FIRST_0 0x00000a9c /* RW-4R */ +#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_NCISOC_PARITY_ERR 0:0 /* RWDVF */ +#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_NCISOC_PARITY_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_NCISOC_PARITY_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_NCISOC_PARITY_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_HDR_RAM_ECC_DBE_ERR 1:1 /* RWDVF */ +#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_HDR_RAM_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_HDR_RAM_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_HDR_RAM_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_HDR_RAM_ECC_LIMIT_ERR 2:2 /* RWDVF */ +#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_HDR_RAM_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_HDR_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_HDR_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT0_RAM_ECC_DBE_ERR 3:3 /* RWDVF */ +#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT0_RAM_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT0_RAM_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT0_RAM_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT0_RAM_ECC_LIMIT_ERR 4:4 /* RWDVF */ +#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT0_RAM_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT0_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT0_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT1_RAM_ECC_DBE_ERR 5:5 /* RWDVF */ +#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT1_RAM_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT1_RAM_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT1_RAM_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT1_RAM_ECC_LIMIT_ERR 6:6 /* RWDVF */ +#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT1_RAM_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT1_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT1_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0 0x00001280 /* RW-4R */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_TXDLCREDITPARITYERR 17:17 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_TXDLCREDITPARITYERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_TXDLCREDITPARITYERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_TXDLCREDITPARITYERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_CREQ_RAM_HDR_ECC_DBE_ERR 18:18 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_CREQ_RAM_HDR_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_CREQ_RAM_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_CREQ_RAM_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_CREQ_RAM_DAT_ECC_DBE_ERR 19:19 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_CREQ_RAM_DAT_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_CREQ_RAM_DAT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_CREQ_RAM_DAT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_CREQ_RAM_ECC_LIMIT_ERR 20:20 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_CREQ_RAM_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_CREQ_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_CREQ_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP_RAM_HDR_ECC_DBE_ERR 21:21 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP_RAM_HDR_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP_RAM_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP_RAM_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP_RAM_DAT_ECC_DBE_ERR 22:22 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP_RAM_DAT_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP_RAM_DAT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP_RAM_DAT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP_RAM_ECC_LIMIT_ERR 23:23 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP_RAM_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_COM_RAM_HDR_ECC_DBE_ERR 24:24 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_COM_RAM_HDR_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_COM_RAM_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_COM_RAM_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_COM_RAM_DAT_ECC_DBE_ERR 25:25 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_COM_RAM_DAT_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_COM_RAM_DAT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_COM_RAM_DAT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_COM_RAM_ECC_LIMIT_ERR 26:26 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_COM_RAM_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_COM_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_COM_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP1_RAM_HDR_ECC_DBE_ERR 27:27 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP1_RAM_HDR_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP1_RAM_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP1_RAM_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP1_RAM_DAT_ECC_DBE_ERR 28:28 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP1_RAM_DAT_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP1_RAM_DAT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP1_RAM_DAT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP1_RAM_ECC_LIMIT_ERR 29:29 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP1_RAM_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP1_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP1_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0 0x00001288 /* RW-4R */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_TXDLCREDITPARITYERR 17:17 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_TXDLCREDITPARITYERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_TXDLCREDITPARITYERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_CREQ_RAM_HDR_ECC_DBE_ERR 18:18 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_CREQ_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_CREQ_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_CREQ_RAM_DAT_ECC_DBE_ERR 19:19 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_CREQ_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_CREQ_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_CREQ_RAM_ECC_LIMIT_ERR 20:20 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_CREQ_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_CREQ_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP_RAM_HDR_ECC_DBE_ERR 21:21 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP_RAM_DAT_ECC_DBE_ERR 22:22 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP_RAM_ECC_LIMIT_ERR 23:23 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_COM_RAM_HDR_ECC_DBE_ERR 24:24 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_COM_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_COM_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_COM_RAM_DAT_ECC_DBE_ERR 25:25 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_COM_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_COM_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_COM_RAM_ECC_LIMIT_ERR 26:26 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_COM_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_COM_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP1_RAM_HDR_ECC_DBE_ERR 27:27 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP1_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP1_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP1_RAM_DAT_ECC_DBE_ERR 28:28 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP1_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP1_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP1_RAM_ECC_LIMIT_ERR 29:29 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP1_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP1_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0 0x0000128c /* RW-4R */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_TXDLCREDITPARITYERR 17:17 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_TXDLCREDITPARITYERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_TXDLCREDITPARITYERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_CREQ_RAM_HDR_ECC_DBE_ERR 18:18 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_CREQ_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_CREQ_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_CREQ_RAM_DAT_ECC_DBE_ERR 19:19 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_CREQ_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_CREQ_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_CREQ_RAM_ECC_LIMIT_ERR 20:20 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_CREQ_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_CREQ_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP_RAM_HDR_ECC_DBE_ERR 21:21 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP_RAM_DAT_ECC_DBE_ERR 22:22 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP_RAM_ECC_LIMIT_ERR 23:23 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_COM_RAM_HDR_ECC_DBE_ERR 24:24 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_COM_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_COM_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_COM_RAM_DAT_ECC_DBE_ERR 25:25 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_COM_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_COM_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_COM_RAM_ECC_LIMIT_ERR 26:26 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_COM_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_COM_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP1_RAM_HDR_ECC_DBE_ERR 27:27 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP1_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP1_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP1_RAM_DAT_ECC_DBE_ERR 28:28 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP1_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP1_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP1_RAM_ECC_LIMIT_ERR 29:29 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP1_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP1_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0 0x0000129c /* RW-4R */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_TXDLCREDITPARITYERR 17:17 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_TXDLCREDITPARITYERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_TXDLCREDITPARITYERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_TXDLCREDITPARITYERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_CREQ_RAM_HDR_ECC_DBE_ERR 18:18 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_CREQ_RAM_HDR_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_CREQ_RAM_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_CREQ_RAM_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_CREQ_RAM_DAT_ECC_DBE_ERR 19:19 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_CREQ_RAM_DAT_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_CREQ_RAM_DAT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_CREQ_RAM_DAT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_CREQ_RAM_ECC_LIMIT_ERR 20:20 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_CREQ_RAM_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_CREQ_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_CREQ_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP_RAM_HDR_ECC_DBE_ERR 21:21 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP_RAM_HDR_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP_RAM_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP_RAM_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP_RAM_DAT_ECC_DBE_ERR 22:22 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP_RAM_DAT_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP_RAM_DAT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP_RAM_DAT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP_RAM_ECC_LIMIT_ERR 23:23 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP_RAM_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_COM_RAM_HDR_ECC_DBE_ERR 24:24 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_COM_RAM_HDR_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_COM_RAM_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_COM_RAM_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_COM_RAM_DAT_ECC_DBE_ERR 25:25 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_COM_RAM_DAT_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_COM_RAM_DAT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_COM_RAM_DAT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_COM_RAM_ECC_LIMIT_ERR 26:26 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_COM_RAM_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_COM_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_COM_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP1_RAM_HDR_ECC_DBE_ERR 27:27 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP1_RAM_HDR_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP1_RAM_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP1_RAM_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP1_RAM_DAT_ECC_DBE_ERR 28:28 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP1_RAM_DAT_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP1_RAM_DAT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP1_RAM_DAT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP1_RAM_ECC_LIMIT_ERR 29:29 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP1_RAM_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP1_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP1_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_1 0x000012a0 /* RW-4R */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC0 0:0 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC0__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC0_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC0_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC1 1:1 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC1__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC1_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC1_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC2 2:2 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC2__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC2_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC2_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC3 3:3 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC3__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC3_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC3_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC4 4:4 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC4__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC4_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC4_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC5 5:5 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC5__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC5_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC5_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC6 6:6 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC6__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC6_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC6_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC7 7:7 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC7__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC7_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_TIMEOUT_VC7_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1 0x000012ac /* RW-4R */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC0 0:0 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC0_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC0_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC1 1:1 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC1_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC1_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC2 2:2 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC2_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC2_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC3 3:3 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC3_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC3_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC4 4:4 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC4_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC4_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC5 5:5 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC5_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC5_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC6 6:6 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC6_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC6_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC7 7:7 /* RWEVF */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC7_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_TIMEOUT_VC7_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_1 0x000012bc /* RW-4R */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC0 0:0 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC0__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC0_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC0_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC1 1:1 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC1__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC1_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC1_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC2 2:2 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC2__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC2_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC2_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC3 3:3 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC3__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC3_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC3_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC4 4:4 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC4__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC4_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC4_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC5 5:5 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC5__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC5_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC5_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC6 6:6 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC6__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC6_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC6_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC7 7:7 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC7__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC7_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_TIMEOUT_VC7_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0(i) (0x0000150c+(i)*0x54) /* RW-4A */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0__SIZE_1 4 /* */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_UNIT 2:1 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_UNIT_CYCLES 0x00000000 /* RW--V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_UNIT_PACKETS 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_UNIT_FLITS 0x00000002 /* RW--V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_UNIT_BYTES 0x00000003 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER 7:3 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_INIT 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_HEAD 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_AE 0x00000002 /* RW--V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_BE 0x00000004 /* RW--V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_DATA 0x00000008 /* RW--V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_IDLE 0x00000010 /* RW--V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_VCSETFILTERMODE 9:8 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_VCSETFILTERMODE_INIT 0x00000003 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_VCSETFILTERMODE_NONE 0x00000000 /* RW--V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_VCSETFILTERMODE_VCSET0 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_VCSETFILTERMODE_VCSET1 0x00000002 /* RW--V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_AN_FILTER 13:12 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_AN_FILTER_AN1 0x00000001 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_AN_FILTER_AN2 0x00000002 /* RW--V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_AN_FILTER_AN1_AND_AN2 0x00000003 /* RW--V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE 19:17 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_ONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_TWO 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_FOUR 0x00000002 /* RW--V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_EIGHT 0x00000003 /* RW--V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_SIXTEEN 0x00000004 /* RW--V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_THIRTYTWO 0x00000005 /* RW--V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_SIXTYFOUR 0x00000006 /* RW--V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_ONETWENTYEIGHT 0x00000007 /* RW--V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_ENABLE 24:24 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_ENABLE_DISABLE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_RESET 25:25 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_RESET__ONWRITE "oneToSet" /* */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_RESET_INIT 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_CAPTURE 26:26 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_CAPTURE__ONWRITE "oneToSet" /* */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_CAPTURE_INIT 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_HW_TP_ENABLE 30:30 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_HW_TP_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_HW_TP_ENABLE_DISABLE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_HW_TP_CAPTURE_ENABLE 31:31 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_HW_TP_CAPTURE_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_HW_TP_CAPTURE_ENABLE_DISABLE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_LO(i) (0x0000154c+(i)*0x54) /* RW-4A */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_LO__SIZE_1 4 /* */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_LO_COUNT 31:0 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_LO_COUNT_INIT 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HI(i) (0x00001550+(i)*0x54) /* RW-4A */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HI__SIZE_1 4 /* */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HI_COUNT 30:0 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HI_COUNT_INIT 0x00000000 /* RWD-V */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HI_ROLLOVER 31:31 /* RWDVF */ +#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HI_ROLLOVER_INIT 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0 0x00001a80 /* RW-4R */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXDLHDRPARITYERR 0:0 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXDLHDRPARITYERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXDLHDRPARITYERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXDLHDRPARITYERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXDLDATAPARITYERR 1:1 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXDLDATAPARITYERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXDLDATAPARITYERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXDLDATAPARITYERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXDLCTRLPARITYERR 2:2 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXDLCTRLPARITYERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXDLCTRLPARITYERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXDLCTRLPARITYERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXPKTLENERR 6:6 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXPKTLENERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXPKTLENERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXPKTLENERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RSVCACHEATTRPROBEREQERR 10:10 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RSVCACHEATTRPROBEREQERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RSVCACHEATTRPROBEREQERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RSVCACHEATTRPROBEREQERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RSVCACHEATTRPROBERSPERR 11:11 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RSVCACHEATTRPROBERSPERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RSVCACHEATTRPROBERSPERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RSVCACHEATTRPROBERSPERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_DATLENGTRMWREQMAXERR 12:12 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_DATLENGTRMWREQMAXERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_DATLENGTRMWREQMAXERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_DATLENGTRMWREQMAXERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_DATLENLTATRRSPMINERR 13:13 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_DATLENLTATRRSPMINERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_DATLENLTATRRSPMINERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_DATLENLTATRRSPMINERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_INVALIDCACHEATTRPOERR 14:14 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_INVALIDCACHEATTRPOERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_INVALIDCACHEATTRPOERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_INVALIDCACHEATTRPOERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_HW_ERR 16:16 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_HW_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_HW_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_HW_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_UR_ERR 17:17 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_UR_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_UR_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_UR_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_PRIV_ERR 18:18 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_PRIV_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_PRIV_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_PRIV_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_INVALID_COLLAPSED_RESPONSE_ERR 19:19 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_INVALID_COLLAPSED_RESPONSE_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_INVALID_COLLAPSED_RESPONSE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_INVALID_COLLAPSED_RESPONSE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_DATA_HW_ERR 20:20 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_DATA_HW_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_DATA_HW_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_DATA_HW_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_DATA_UR_ERR 21:21 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_DATA_UR_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_DATA_UR_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_DATA_UR_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_DATA_PRIV_ERR 22:22 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_DATA_PRIV_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_DATA_PRIV_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_DATA_PRIV_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_DATLEN192PACKETERR 23:23 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_DATLEN192PACKETERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_DATLEN192PACKETERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_DATLEN192PACKETERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0 0x00001a88 /* RW-4R */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXDLHDRPARITYERR 0:0 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXDLHDRPARITYERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXDLHDRPARITYERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXDLDATAPARITYERR 1:1 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXDLDATAPARITYERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXDLDATAPARITYERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXDLCTRLPARITYERR 2:2 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXDLCTRLPARITYERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXDLCTRLPARITYERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXPKTLENERR 6:6 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXPKTLENERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXPKTLENERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RSVCACHEATTRPROBEREQERR 10:10 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RSVCACHEATTRPROBEREQERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RSVCACHEATTRPROBEREQERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RSVCACHEATTRPROBERSPERR 11:11 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RSVCACHEATTRPROBERSPERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RSVCACHEATTRPROBERSPERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_DATLENGTRMWREQMAXERR 12:12 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_DATLENGTRMWREQMAXERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_DATLENGTRMWREQMAXERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_DATLENLTATRRSPMINERR 13:13 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_DATLENLTATRRSPMINERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_DATLENLTATRRSPMINERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_INVALIDCACHEATTRPOERR 14:14 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_INVALIDCACHEATTRPOERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_INVALIDCACHEATTRPOERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_HW_ERR 16:16 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_HW_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_HW_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_UR_ERR 17:17 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_UR_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_UR_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_PRIV_ERR 18:18 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_PRIV_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_PRIV_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_INVALID_COLLAPSED_RESPONSE_ERR 19:19 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_INVALID_COLLAPSED_RESPONSE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_INVALID_COLLAPSED_RESPONSE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_HW_ERR 20:20 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_HW_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_HW_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_UR_ERR 21:21 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_UR_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_UR_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_PRIV_ERR 22:22 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_PRIV_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_PRIV_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_DATLEN192PACKETERR 23:23 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_DATLEN192PACKETERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_DATLEN192PACKETERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0 0x00001a8c /* RW-4R */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXDLHDRPARITYERR 0:0 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXDLHDRPARITYERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXDLHDRPARITYERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXDLDATAPARITYERR 1:1 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXDLDATAPARITYERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXDLDATAPARITYERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXDLCTRLPARITYERR 2:2 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXDLCTRLPARITYERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXDLCTRLPARITYERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXPKTLENERR 6:6 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXPKTLENERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXPKTLENERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSVCACHEATTRPROBEREQERR 10:10 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSVCACHEATTRPROBEREQERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSVCACHEATTRPROBEREQERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSVCACHEATTRPROBERSPERR 11:11 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSVCACHEATTRPROBERSPERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSVCACHEATTRPROBERSPERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_DATLENGTRMWREQMAXERR 12:12 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_DATLENGTRMWREQMAXERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_DATLENGTRMWREQMAXERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_DATLENLTATRRSPMINERR 13:13 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_DATLENLTATRRSPMINERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_DATLENLTATRRSPMINERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_INVALIDCACHEATTRPOERR 14:14 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_INVALIDCACHEATTRPOERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_INVALIDCACHEATTRPOERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_HW_ERR 16:16 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_HW_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_HW_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_UR_ERR 17:17 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_UR_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_UR_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_PRIV_ERR 18:18 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_PRIV_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_PRIV_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_INVALID_COLLAPSED_RESPONSE_ERR 19:19 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_INVALID_COLLAPSED_RESPONSE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_INVALID_COLLAPSED_RESPONSE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_HW_ERR 20:20 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_HW_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_HW_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_UR_ERR 21:21 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_UR_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_UR_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_PRIV_ERR 22:22 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_PRIV_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_DATA_PRIV_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_DATLEN192PACKETERR 23:23 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_DATLEN192PACKETERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_DATLEN192PACKETERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0 0x00001a9c /* RW-4R */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXDLHDRPARITYERR 0:0 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXDLHDRPARITYERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXDLHDRPARITYERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXDLHDRPARITYERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXDLDATAPARITYERR 1:1 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXDLDATAPARITYERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXDLDATAPARITYERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXDLDATAPARITYERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXDLCTRLPARITYERR 2:2 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXDLCTRLPARITYERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXDLCTRLPARITYERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXDLCTRLPARITYERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXPKTLENERR 6:6 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXPKTLENERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXPKTLENERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXPKTLENERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RSVCACHEATTRPROBEREQERR 10:10 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RSVCACHEATTRPROBEREQERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RSVCACHEATTRPROBEREQERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RSVCACHEATTRPROBEREQERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RSVCACHEATTRPROBERSPERR 11:11 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RSVCACHEATTRPROBERSPERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RSVCACHEATTRPROBERSPERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RSVCACHEATTRPROBERSPERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_DATLENGTRMWREQMAXERR 12:12 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_DATLENGTRMWREQMAXERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_DATLENGTRMWREQMAXERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_DATLENGTRMWREQMAXERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_DATLENLTATRRSPMINERR 13:13 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_DATLENLTATRRSPMINERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_DATLENLTATRRSPMINERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_DATLENLTATRRSPMINERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_INVALIDCACHEATTRPOERR 14:14 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_INVALIDCACHEATTRPOERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_INVALIDCACHEATTRPOERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_INVALIDCACHEATTRPOERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_HW_ERR 16:16 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_HW_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_HW_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_HW_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_UR_ERR 17:17 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_UR_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_UR_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_UR_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_PRIV_ERR 18:18 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_PRIV_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_PRIV_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_PRIV_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_INVALID_COLLAPSED_RESPONSE_ERR 19:19 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_INVALID_COLLAPSED_RESPONSE_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_INVALID_COLLAPSED_RESPONSE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_INVALID_COLLAPSED_RESPONSE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_DATA_HW_ERR 20:20 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_DATA_HW_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_DATA_HW_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_DATA_HW_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_DATA_UR_ERR 21:21 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_DATA_UR_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_DATA_UR_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_DATA_UR_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_DATA_PRIV_ERR 22:22 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_DATA_PRIV_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_DATA_PRIV_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_DATA_PRIV_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_DATLEN192PACKETERR 23:23 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_DATLEN192PACKETERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_DATLEN192PACKETERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_DATLEN192PACKETERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_1 0x00001aa0 /* RW-4R */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_RXHDROVFERR 7:0 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_RXHDROVFERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_RXHDROVFERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_RXHDROVFERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_RXDATAOVFERR 15:8 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_RXDATAOVFERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_RXDATAOVFERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_RXDATAOVFERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_STOMPDETERR 16:16 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_STOMPDETERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_STOMPDETERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_STOMPDETERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_RXPOISONERR 17:17 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_RXPOISONERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_RXPOISONERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_RXPOISONERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_HEARTBEAT_TIMEOUT_ERR 18:18 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_HEARTBEAT_TIMEOUT_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_HEARTBEAT_TIMEOUT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_HEARTBEAT_TIMEOUT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1 0x00001aa8 /* RW-4R */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_RXHDROVFERR 7:0 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_RXHDROVFERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_RXHDROVFERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_RXDATAOVFERR 15:8 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_RXDATAOVFERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_RXDATAOVFERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_STOMPDETERR 16:16 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_STOMPDETERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_STOMPDETERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_RXPOISONERR 17:17 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_RXPOISONERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_RXPOISONERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_HEARTBEAT_TIMEOUT_ERR 18:18 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_HEARTBEAT_TIMEOUT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_HEARTBEAT_TIMEOUT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1 0x00001aac /* RW-4R */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_RXHDROVFERR 7:0 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_RXHDROVFERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_RXHDROVFERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_RXDATAOVFERR 15:8 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_RXDATAOVFERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_RXDATAOVFERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_STOMPDETERR 16:16 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_STOMPDETERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_STOMPDETERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_RXPOISONERR 17:17 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_RXPOISONERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_RXPOISONERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_HEARTBEAT_TIMEOUT_ERR 18:18 /* RWEVF */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_HEARTBEAT_TIMEOUT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_HEARTBEAT_TIMEOUT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1 0x00001ab8 /* RW-4R */ +#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_RXHDROVFERR 7:0 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_RXHDROVFERR__ONWRITE "oneToSet" /* */ +#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_RXHDROVFERR_INIT 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_RXHDROVFERR_INSERT 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_RXDATAOVFERR 15:8 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_RXDATAOVFERR__ONWRITE "oneToSet" /* */ +#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_RXDATAOVFERR_INIT 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_RXDATAOVFERR_INSERT 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_STOMPDETERR 16:16 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_STOMPDETERR__ONWRITE "oneToSet" /* */ +#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_STOMPDETERR_INIT 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_STOMPDETERR_INSERT 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_RXPOISONERR 17:17 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_RXPOISONERR__ONWRITE "oneToSet" /* */ +#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_RXPOISONERR_INIT 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_RXPOISONERR_INSERT 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_HEARTBEAT_TIMEOUT_ERR 18:18 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_HEARTBEAT_TIMEOUT_ERR__ONWRITE "oneToSet" /* */ +#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_HEARTBEAT_TIMEOUT_ERR_INIT 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_HEARTBEAT_TIMEOUT_ERR_INSERT 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_1 0x00001abc /* RW-4R */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_RXHDROVFERR 7:0 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_RXHDROVFERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_RXHDROVFERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_RXHDROVFERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_RXDATAOVFERR 15:8 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_RXDATAOVFERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_RXDATAOVFERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_RXDATAOVFERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_STOMPDETERR 16:16 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_STOMPDETERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_STOMPDETERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_STOMPDETERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_RXPOISONERR 17:17 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_RXPOISONERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_RXPOISONERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_RXPOISONERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_HEARTBEAT_TIMEOUT_ERR 18:18 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_HEARTBEAT_TIMEOUT_ERR__ONWRITE "oneToClear" /* */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_HEARTBEAT_TIMEOUT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_HEARTBEAT_TIMEOUT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0(i) (0x00001d0c+(i)*0x54) /* RW-4A */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0__SIZE_1 4 /* */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_UNIT 2:1 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_UNIT_CYCLES 0x00000000 /* RW--V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_UNIT_PACKETS 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_UNIT_FLITS 0x00000002 /* RW--V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_UNIT_BYTES 0x00000003 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER 7:3 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_INIT 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_HEAD 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_AE 0x00000002 /* RW--V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_BE 0x00000004 /* RW--V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_DATA 0x00000008 /* RW--V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_IDLE 0x00000010 /* RW--V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_VCSETFILTERMODE 9:8 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_VCSETFILTERMODE_INIT 0x00000003 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_VCSETFILTERMODE_NONE 0x00000000 /* RW--V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_VCSETFILTERMODE_VCSET0 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_VCSETFILTERMODE_VCSET1 0x00000002 /* RW--V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_AN_FILTER 13:12 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_AN_FILTER_AN1 0x00000001 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_AN_FILTER_AN2 0x00000002 /* RW--V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_AN_FILTER_AN1_AND_AN2 0x00000003 /* RW--V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE 19:17 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_ONE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_TWO 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_FOUR 0x00000002 /* RW--V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_EIGHT 0x00000003 /* RW--V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_SIXTEEN 0x00000004 /* RW--V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_THIRTYTWO 0x00000005 /* RW--V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_SIXTYFOUR 0x00000006 /* RW--V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_ONETWENTYEIGHT 0x00000007 /* RW--V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_ENABLE 24:24 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_ENABLE_DISABLE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_RESET 25:25 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_RESET__ONWRITE "oneToSet" /* */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_RESET_INIT 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_CAPTURE 26:26 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_CAPTURE__ONWRITE "oneToSet" /* */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_CAPTURE_INIT 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_HW_TP_ENABLE 30:30 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_HW_TP_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_HW_TP_ENABLE_DISABLE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_HW_TP_CAPTURE_ENABLE 31:31 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_HW_TP_CAPTURE_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_HW_TP_CAPTURE_ENABLE_DISABLE 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_LO(i) (0x00001d4c+(i)*0x54) /* RW-4A */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_LO__SIZE_1 4 /* */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_LO_COUNT 31:0 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_LO_COUNT_INIT 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_HI(i) (0x00001d50+(i)*0x54) /* RW-4A */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_HI__SIZE_1 4 /* */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_HI_COUNT 30:0 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_HI_COUNT_INIT 0x00000000 /* RWD-V */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_HI_ROLLOVER 31:31 /* RWDVF */ +#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_HI_ROLLOVER_INIT 0x00000000 /* RWD-V */ +#endif // __ls10_dev_nvltlc_ip_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_nvlw_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_nvlw_ip.h new file mode 100644 index 000000000..1c762b6f3 --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_nvlw_ip.h @@ -0,0 +1,211 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_nvlw_ip_h__ +#define __ls10_dev_nvlw_ip_h__ +/* This file is autogenerated. Do not edit */ +#define NV_NVLW 0x0000FFF:0x00000000 /* RW--D */ +#define NV_NVLW_TOP_INTR_0_STATUS 0x00000200 /* R--4R */ +#define NV_NVLW_TOP_INTR_0_STATUS_LINK 3:0 /* R-EVF */ +#define NV_NVLW_TOP_INTR_0_STATUS_LINK_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_TOP_INTR_0_STATUS_COMMON 31:31 /* R-EVF */ +#define NV_NVLW_TOP_INTR_0_STATUS_COMMON_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_TOP_INTR_1_STATUS 0x00000204 /* R--4R */ +#define NV_NVLW_TOP_INTR_1_STATUS_LINK 3:0 /* R-EVF */ +#define NV_NVLW_TOP_INTR_1_STATUS_LINK_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_TOP_INTR_1_STATUS_COMMON 31:31 /* R-EVF */ +#define NV_NVLW_TOP_INTR_1_STATUS_COMMON_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_TOP_INTR_2_STATUS 0x00000208 /* R--4R */ +#define NV_NVLW_TOP_INTR_2_STATUS_LINK 3:0 /* R-EVF */ +#define NV_NVLW_TOP_INTR_2_STATUS_LINK_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_TOP_INTR_2_STATUS_COMMON 31:31 /* R-EVF */ +#define NV_NVLW_TOP_INTR_2_STATUS_COMMON_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_COMMON_INTR_0_MASK 0x00000220 /* RW-4R */ +#define NV_NVLW_COMMON_INTR_0_MASK_FATAL 0:0 /* RWEVF */ +#define NV_NVLW_COMMON_INTR_0_MASK_FATAL_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLW_COMMON_INTR_0_MASK_FATAL_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLW_COMMON_INTR_0_MASK_NONFATAL 1:1 /* RWEVF */ +#define NV_NVLW_COMMON_INTR_0_MASK_NONFATAL_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLW_COMMON_INTR_0_MASK_NONFATAL_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLW_COMMON_INTR_0_MASK_CORRECTABLE 2:2 /* RWEVF */ +#define NV_NVLW_COMMON_INTR_0_MASK_CORRECTABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLW_COMMON_INTR_0_MASK_CORRECTABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLW_COMMON_INTR_0_MASK_INTR0 3:3 /* RWEVF */ +#define NV_NVLW_COMMON_INTR_0_MASK_INTR0_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLW_COMMON_INTR_0_MASK_INTR0_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLW_COMMON_INTR_0_MASK_INTR1 4:4 /* RWEVF */ +#define NV_NVLW_COMMON_INTR_0_MASK_INTR1_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLW_COMMON_INTR_0_MASK_INTR1_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLW_COMMON_INTR_0_STATUS 0x00000224 /* R--4R */ +#define NV_NVLW_COMMON_INTR_0_STATUS_FATAL 0:0 /* R-EVF */ +#define NV_NVLW_COMMON_INTR_0_STATUS_FATAL_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_COMMON_INTR_0_STATUS_NONFATAL 1:1 /* R-EVF */ +#define NV_NVLW_COMMON_INTR_0_STATUS_NONFATAL_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_COMMON_INTR_0_STATUS_CORRECTABLE 2:2 /* R-EVF */ +#define NV_NVLW_COMMON_INTR_0_STATUS_CORRECTABLE_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_COMMON_INTR_0_STATUS_INTR0 3:3 /* R-EVF */ +#define NV_NVLW_COMMON_INTR_0_STATUS_INTR0_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_COMMON_INTR_0_STATUS_INTR1 4:4 /* R-EVF */ +#define NV_NVLW_COMMON_INTR_0_STATUS_INTR1_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_COMMON_INTR_1_MASK 0x00000228 /* RW-4R */ +#define NV_NVLW_COMMON_INTR_1_MASK_FATAL 0:0 /* RWEVF */ +#define NV_NVLW_COMMON_INTR_1_MASK_FATAL_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLW_COMMON_INTR_1_MASK_FATAL_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLW_COMMON_INTR_1_MASK_NONFATAL 1:1 /* RWEVF */ +#define NV_NVLW_COMMON_INTR_1_MASK_NONFATAL_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLW_COMMON_INTR_1_MASK_NONFATAL_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLW_COMMON_INTR_1_MASK_CORRECTABLE 2:2 /* RWEVF */ +#define NV_NVLW_COMMON_INTR_1_MASK_CORRECTABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLW_COMMON_INTR_1_MASK_CORRECTABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLW_COMMON_INTR_1_MASK_INTR0 3:3 /* RWEVF */ +#define NV_NVLW_COMMON_INTR_1_MASK_INTR0_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLW_COMMON_INTR_1_MASK_INTR0_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLW_COMMON_INTR_1_MASK_INTR1 4:4 /* RWEVF */ +#define NV_NVLW_COMMON_INTR_1_MASK_INTR1_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLW_COMMON_INTR_1_MASK_INTR1_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLW_COMMON_INTR_1_STATUS 0x0000022c /* R--4R */ +#define NV_NVLW_COMMON_INTR_1_STATUS_FATAL 0:0 /* R-EVF */ +#define NV_NVLW_COMMON_INTR_1_STATUS_FATAL_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_COMMON_INTR_1_STATUS_NONFATAL 1:1 /* R-EVF */ +#define NV_NVLW_COMMON_INTR_1_STATUS_NONFATAL_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_COMMON_INTR_1_STATUS_CORRECTABLE 2:2 /* R-EVF */ +#define NV_NVLW_COMMON_INTR_1_STATUS_CORRECTABLE_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_COMMON_INTR_1_STATUS_INTR0 3:3 /* R-EVF */ +#define NV_NVLW_COMMON_INTR_1_STATUS_INTR0_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_COMMON_INTR_1_STATUS_INTR1 4:4 /* R-EVF */ +#define NV_NVLW_COMMON_INTR_1_STATUS_INTR1_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_COMMON_INTR_2_MASK 0x00000230 /* RW-4R */ +#define NV_NVLW_COMMON_INTR_2_MASK_FATAL 0:0 /* RWEVF */ +#define NV_NVLW_COMMON_INTR_2_MASK_FATAL_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLW_COMMON_INTR_2_MASK_FATAL_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLW_COMMON_INTR_2_MASK_NONFATAL 1:1 /* RWEVF */ +#define NV_NVLW_COMMON_INTR_2_MASK_NONFATAL_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLW_COMMON_INTR_2_MASK_NONFATAL_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLW_COMMON_INTR_2_MASK_CORRECTABLE 2:2 /* RWEVF */ +#define NV_NVLW_COMMON_INTR_2_MASK_CORRECTABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLW_COMMON_INTR_2_MASK_CORRECTABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLW_COMMON_INTR_2_MASK_INTR0 3:3 /* RWEVF */ +#define NV_NVLW_COMMON_INTR_2_MASK_INTR0_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLW_COMMON_INTR_2_MASK_INTR0_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLW_COMMON_INTR_2_MASK_INTR1 4:4 /* RWEVF */ +#define NV_NVLW_COMMON_INTR_2_MASK_INTR1_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLW_COMMON_INTR_2_MASK_INTR1_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLW_COMMON_INTR_2_STATUS 0x00000234 /* R--4R */ +#define NV_NVLW_COMMON_INTR_2_STATUS_FATAL 0:0 /* R-EVF */ +#define NV_NVLW_COMMON_INTR_2_STATUS_FATAL_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_COMMON_INTR_2_STATUS_NONFATAL 1:1 /* R-EVF */ +#define NV_NVLW_COMMON_INTR_2_STATUS_NONFATAL_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_COMMON_INTR_2_STATUS_CORRECTABLE 2:2 /* R-EVF */ +#define NV_NVLW_COMMON_INTR_2_STATUS_CORRECTABLE_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_COMMON_INTR_2_STATUS_INTR0 3:3 /* R-EVF */ +#define NV_NVLW_COMMON_INTR_2_STATUS_INTR0_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_COMMON_INTR_2_STATUS_INTR1 4:4 /* R-EVF */ +#define NV_NVLW_COMMON_INTR_2_STATUS_INTR1_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_LINK_INTR_0_MASK(i) (0x00000300+(i)*0x40) /* RW-4A */ +#define NV_NVLW_LINK_INTR_0_MASK__SIZE_1 4 /* */ +#define NV_NVLW_LINK_INTR_0_MASK_FATAL 0:0 /* RWEVF */ +#define NV_NVLW_LINK_INTR_0_MASK_FATAL_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLW_LINK_INTR_0_MASK_FATAL_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLW_LINK_INTR_0_MASK_NONFATAL 1:1 /* RWEVF */ +#define NV_NVLW_LINK_INTR_0_MASK_NONFATAL_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLW_LINK_INTR_0_MASK_NONFATAL_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLW_LINK_INTR_0_MASK_CORRECTABLE 2:2 /* RWEVF */ +#define NV_NVLW_LINK_INTR_0_MASK_CORRECTABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLW_LINK_INTR_0_MASK_CORRECTABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLW_LINK_INTR_0_MASK_INTR0 3:3 /* RWEVF */ +#define NV_NVLW_LINK_INTR_0_MASK_INTR0_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLW_LINK_INTR_0_MASK_INTR0_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLW_LINK_INTR_0_MASK_INTR1 4:4 /* RWEVF */ +#define NV_NVLW_LINK_INTR_0_MASK_INTR1_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLW_LINK_INTR_0_MASK_INTR1_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLW_LINK_INTR_0_STATUS(i) (0x00000304+(i)*0x40) /* R--4A */ +#define NV_NVLW_LINK_INTR_0_STATUS__SIZE_1 4 /* */ +#define NV_NVLW_LINK_INTR_0_STATUS_FATAL 0:0 /* R-EVF */ +#define NV_NVLW_LINK_INTR_0_STATUS_FATAL_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_LINK_INTR_0_STATUS_NONFATAL 1:1 /* R-EVF */ +#define NV_NVLW_LINK_INTR_0_STATUS_NONFATAL_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_LINK_INTR_0_STATUS_CORRECTABLE 2:2 /* R-EVF */ +#define NV_NVLW_LINK_INTR_0_STATUS_CORRECTABLE_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_LINK_INTR_0_STATUS_INTR0 3:3 /* R-EVF */ +#define NV_NVLW_LINK_INTR_0_STATUS_INTR0_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_LINK_INTR_0_STATUS_INTR1 4:4 /* R-EVF */ +#define NV_NVLW_LINK_INTR_0_STATUS_INTR1_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_LINK_INTR_1_MASK(i) (0x00000308+(i)*0x40) /* RW-4A */ +#define NV_NVLW_LINK_INTR_1_MASK__SIZE_1 4 /* */ +#define NV_NVLW_LINK_INTR_1_MASK_FATAL 0:0 /* RWEVF */ +#define NV_NVLW_LINK_INTR_1_MASK_FATAL_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLW_LINK_INTR_1_MASK_FATAL_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLW_LINK_INTR_1_MASK_NONFATAL 1:1 /* RWEVF */ +#define NV_NVLW_LINK_INTR_1_MASK_NONFATAL_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLW_LINK_INTR_1_MASK_NONFATAL_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLW_LINK_INTR_1_MASK_CORRECTABLE 2:2 /* RWEVF */ +#define NV_NVLW_LINK_INTR_1_MASK_CORRECTABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLW_LINK_INTR_1_MASK_CORRECTABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLW_LINK_INTR_1_MASK_INTR0 3:3 /* RWEVF */ +#define NV_NVLW_LINK_INTR_1_MASK_INTR0_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLW_LINK_INTR_1_MASK_INTR0_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLW_LINK_INTR_1_MASK_INTR1 4:4 /* RWEVF */ +#define NV_NVLW_LINK_INTR_1_MASK_INTR1_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLW_LINK_INTR_1_MASK_INTR1_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLW_LINK_INTR_1_STATUS(i) (0x0000030c+(i)*0x40) /* R--4A */ +#define NV_NVLW_LINK_INTR_1_STATUS__SIZE_1 4 /* */ +#define NV_NVLW_LINK_INTR_1_STATUS_FATAL 0:0 /* R-EVF */ +#define NV_NVLW_LINK_INTR_1_STATUS_FATAL_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_LINK_INTR_1_STATUS_NONFATAL 1:1 /* R-EVF */ +#define NV_NVLW_LINK_INTR_1_STATUS_NONFATAL_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_LINK_INTR_1_STATUS_CORRECTABLE 2:2 /* R-EVF */ +#define NV_NVLW_LINK_INTR_1_STATUS_CORRECTABLE_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_LINK_INTR_1_STATUS_INTR0 3:3 /* R-EVF */ +#define NV_NVLW_LINK_INTR_1_STATUS_INTR0_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_LINK_INTR_1_STATUS_INTR1 4:4 /* R-EVF */ +#define NV_NVLW_LINK_INTR_1_STATUS_INTR1_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_LINK_INTR_2_MASK(i) (0x00000310+(i)*0x40) /* RW-4A */ +#define NV_NVLW_LINK_INTR_2_MASK__SIZE_1 4 /* */ +#define NV_NVLW_LINK_INTR_2_MASK_FATAL 0:0 /* RWEVF */ +#define NV_NVLW_LINK_INTR_2_MASK_FATAL_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLW_LINK_INTR_2_MASK_FATAL_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLW_LINK_INTR_2_MASK_NONFATAL 1:1 /* RWEVF */ +#define NV_NVLW_LINK_INTR_2_MASK_NONFATAL_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLW_LINK_INTR_2_MASK_NONFATAL_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLW_LINK_INTR_2_MASK_CORRECTABLE 2:2 /* RWEVF */ +#define NV_NVLW_LINK_INTR_2_MASK_CORRECTABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLW_LINK_INTR_2_MASK_CORRECTABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLW_LINK_INTR_2_MASK_INTR0 3:3 /* RWEVF */ +#define NV_NVLW_LINK_INTR_2_MASK_INTR0_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLW_LINK_INTR_2_MASK_INTR0_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLW_LINK_INTR_2_MASK_INTR1 4:4 /* RWEVF */ +#define NV_NVLW_LINK_INTR_2_MASK_INTR1_ENABLE 0x00000001 /* RW--V */ +#define NV_NVLW_LINK_INTR_2_MASK_INTR1_DISABLE 0x00000000 /* RWE-V */ +#define NV_NVLW_LINK_INTR_2_STATUS(i) (0x00000314+(i)*0x40) /* R--4A */ +#define NV_NVLW_LINK_INTR_2_STATUS__SIZE_1 4 /* */ +#define NV_NVLW_LINK_INTR_2_STATUS_FATAL 0:0 /* R-EVF */ +#define NV_NVLW_LINK_INTR_2_STATUS_FATAL_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_LINK_INTR_2_STATUS_NONFATAL 1:1 /* R-EVF */ +#define NV_NVLW_LINK_INTR_2_STATUS_NONFATAL_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_LINK_INTR_2_STATUS_CORRECTABLE 2:2 /* R-EVF */ +#define NV_NVLW_LINK_INTR_2_STATUS_CORRECTABLE_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_LINK_INTR_2_STATUS_INTR0 3:3 /* R-EVF */ +#define NV_NVLW_LINK_INTR_2_STATUS_INTR0_INIT 0x00000000 /* R-E-V */ +#define NV_NVLW_LINK_INTR_2_STATUS_INTR1 4:4 /* R-EVF */ +#define NV_NVLW_LINK_INTR_2_STATUS_INTR1_INIT 0x00000000 /* R-E-V */ +#endif // __ls10_dev_nvlw_ip_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_nvs_top.h b/src/common/inc/swref/published/nvswitch/ls10/dev_nvs_top.h new file mode 100644 index 000000000..875cfc3c0 --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_nvs_top.h @@ -0,0 +1,135 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_nvs_top_h__ +#define __ls10_dev_nvs_top_h__ +/* This file is autogenerated. Do not edit */ +#define NV_SWPTOP /* R--4P */ +#define NV_SWPTOP_TABLE_BASE_ADDRESS_OFFSET 0x0002c000 /* */ +#define NV_SWPTOP_ENTRY 1:0 /* R-EVF */ +#define NV_SWPTOP_ENTRY_INVALID 0x00000000 /* R-E-V */ +#define NV_SWPTOP_ENTRY_ENUM 0x00000001 /* R---V */ +#define NV_SWPTOP_ENTRY_DATA1 0x00000002 /* R---V */ +#define NV_SWPTOP_ENTRY_DATA2 0x00000003 /* R---V */ +#define NV_SWPTOP_CONTENTS 30:2 /* R-EVF */ +#define NV_SWPTOP_CONTENTS_INIT 0x00000000 /* R-E-V */ +#define NV_SWPTOP_CHAIN 31:31 /* R-EVF */ +#define NV_SWPTOP_CHAIN_DISABLE 0x00000000 /* R-E-V */ +#define NV_SWPTOP_CHAIN_ENABLE 0x00000001 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE 9:2 /* R--UF */ +#define NV_SWPTOP_ENUM_DEVICE_INVALID 0x0 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_PTOP 0x1 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_SIOCTRL 0x2 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_SIOCTRL_BCAST 0x3 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_NPG 0x4 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_NPG_BCAST 0x5 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_SWX 0x6 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_SWX_BCAST 0x7 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_CLKS 0x8 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_FUSE 0x9 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_JTAG 0xa /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_PMGR 0xb /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_SAW 0xc /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_XP3G 0xd /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_XVE 0xe /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_ROM 0xf /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_EXTDEV 0x10 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_PRIVMAIN 0x11 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_PRIVLOC 0x12 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_NVLW 0x13 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_NVLW_BCAST 0x14 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_NXBAR 0x15 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_NXBAR_BCAST 0x16 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_PXBAR 0x17 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_PXBAR_BCAST 0x18 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_PCIE 0x19 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_PCIE_BCAST 0x1a /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_PTIMER 0x1b /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_TSENSE 0x1c /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_SOE 0x1d /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_SMR 0x1e /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_I2C 0x1f /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_SMBPBI 0x20 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_SE 0x21 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_THERM 0x22 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_XAL 0x23 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_XPL 0x24 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_XTL 0x25 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_GIN 0x26 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_GPU_PTOP 0x27 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_PRISEQ 0x28 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_UXL 0x29 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_PMC 0x2a /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_PBUS 0x2b /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_ROM2 0x2c /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_GPIO 0x2d /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_XAL_FUNC 0x2e /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_XTL_CONFIG 0x2f /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_FSP 0x30 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_CLKS_SYS 0x31 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_CLKS_SYSB 0x32 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_CLKS_P0 0x33 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_CLKS_P0_BCAST 0x34 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_SAW_PM 0x35 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_PCIE_PM 0x36 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_PRT_PRI_HUB 0x37 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_PRT_PRI_RS_CTRL 0x38 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_PRT_PRI_HUB_BCAST 0x39 /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_PRT_PRI_RS_CTRL_BCAST 0x3a /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_SYS_PRI_HUB 0x3b /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_SYS_PRI_RS_CTRL 0x3c /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_SYSB_PRI_HUB 0x3d /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_SYSB_PRI_RS_CTRL 0x3e /* R---V */ +#define NV_SWPTOP_ENUM_DEVICE_PRI_MASTER_RS 0x3f /* R---V */ +#define NV_SWPTOP_ENUM_ID 17:10 /* R--UF */ +#define NV_SWPTOP_ENUM_MANUALS_TYPE 19:18 /* R--UF */ +#define NV_SWPTOP_ENUM_MANUALS_TYPE_ZERO_OFFSET 0x0 /* R---V */ +#define NV_SWPTOP_ENUM_MANUALS_TYPE_BAR0_OFFSET 0x1 /* R---V */ +#define NV_SWPTOP_ENUM_VERSION 30:20 /* R--UF */ +#define NV_SWPTOP_ENUM_VERSION_1 0x1 /* R---V */ +#define NV_SWPTOP_ENUM_VERSION_2 0x2 /* R---V */ +#define NV_SWPTOP_ENUM_VERSION_3 0x3 /* R---V */ +#define NV_SWPTOP_DATA1_RESET 6:2 /* R--UF */ +#define NV_SWPTOP_DATA1_INTR 11:7 /* R--UF */ +#define NV_SWPTOP_DATA1_RESERVED2 11:2 /* R--UF */ +#define NV_SWPTOP_DATA1_CLUSTER_TYPE 16:12 /* R--UF */ +#define NV_SWPTOP_DATA1_CLUSTER_TYPE_INVALID 0x0 /* R---V */ +#define NV_SWPTOP_DATA1_CLUSTER_TYPE_SYS 0x1 /* R---V */ +#define NV_SWPTOP_DATA1_CLUSTER_TYPE_PRT 0x2 /* R---V */ +#define NV_SWPTOP_DATA1_CLUSTER_TYPE_SYSB 0x3 /* R---V */ +#define NV_SWPTOP_DATA1_CLUSTER_NUMBER 21:17 /* R--UF */ +#define NV_SWPTOP_DATA1_RESERVED 30:22 /* R--UF */ + #define NV_SWPTOP_DATA1_PTOP_LENGTH 30:2 /* R--UF */ +#define NV_SWPTOP_DATA2_TYPE 30:26 /* R--UF */ +#define NV_SWPTOP_DATA2_TYPE_INVALID 0x0 /* R---V */ +#define NV_SWPTOP_DATA2_TYPE_RESERVED 0x1 /* R---V */ +#define NV_SWPTOP_DATA2_TYPE_RESETREG 0x2 /* R---V */ +#define NV_SWPTOP_DATA2_TYPE_INTRREG 0x3 /* R---V */ +#define NV_SWPTOP_DATA2_TYPE_DISCOVERY 0x4 /* R---V */ +#define NV_SWPTOP_DATA2_TYPE_UNICAST 0x5 /* R---V */ +#define NV_SWPTOP_DATA2_TYPE_BROADCAST 0x6 /* R---V */ +#define NV_SWPTOP_DATA2_TYPE_MULTICAST0 0x7 /* R---V */ +#define NV_SWPTOP_DATA2_TYPE_MULTICAST1 0x8 /* R---V */ +#define NV_SWPTOP_DATA2_TYPE_MULTICAST2 0x9 /* R---V */ +#define NV_SWPTOP_DATA2_ADDR 25:2 /* R--UF */ +#endif // __ls10_dev_nvs_top_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_nxbar_tcp_global_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_nxbar_tcp_global_ip.h new file mode 100644 index 000000000..124a9ff10 --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_nxbar_tcp_global_ip.h @@ -0,0 +1,75 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_nxbar_tcp_global_ip_h__ +#define __ls10_dev_nxbar_tcp_global_ip_h__ +/* This file is autogenerated. Do not edit */ +#define NV_NXBAR_TCP 0x0001FFFF:0x0000000 /* RW--D */ +#define NV_NXBAR_TCP_ERROR_STATUS 0x00000090 /* R--4R */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILE0 0:0 /* R--VF */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILE0_DEFAULT 0x00000000 /* R---V */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILE1 1:1 /* R--VF */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILE1_DEFAULT 0x00000000 /* R---V */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILE2 2:2 /* R--VF */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILE2_DEFAULT 0x00000000 /* R---V */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILE3 3:3 /* R--VF */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILE3_DEFAULT 0x00000000 /* R---V */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILE4 4:4 /* R--VF */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILE4_DEFAULT 0x00000000 /* R---V */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILE5 5:5 /* R--VF */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILE5_DEFAULT 0x00000000 /* R---V */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILE6 6:6 /* R--VF */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILE6_DEFAULT 0x00000000 /* R---V */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILE7 7:7 /* R--VF */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILE7_DEFAULT 0x00000000 /* R---V */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILE8 8:8 /* R--VF */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILE8_DEFAULT 0x00000000 /* R---V */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILE9 9:9 /* R--VF */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILE9_DEFAULT 0x00000000 /* R---V */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILE10 10:10 /* R--VF */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILE10_DEFAULT 0x00000000 /* R---V */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILE11 11:11 /* R--VF */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILE11_DEFAULT 0x00000000 /* R---V */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT0 16:16 /* R--VF */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT0_DEFAULT 0x00000000 /* R---V */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT1 17:17 /* R--VF */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT1_DEFAULT 0x00000000 /* R---V */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT2 18:18 /* R--VF */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT2_DEFAULT 0x00000000 /* R---V */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT3 19:19 /* R--VF */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT3_DEFAULT 0x00000000 /* R---V */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT4 20:20 /* R--VF */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT4_DEFAULT 0x00000000 /* R---V */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT5 21:21 /* R--VF */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT5_DEFAULT 0x00000000 /* R---V */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT6 22:22 /* R--VF */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT6_DEFAULT 0x00000000 /* R---V */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT7 23:23 /* R--VF */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT7_DEFAULT 0x00000000 /* R---V */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT8 24:24 /* R--VF */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT8_DEFAULT 0x00000000 /* R---V */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT9 25:25 /* R--VF */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT9_DEFAULT 0x00000000 /* R---V */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT10 26:26 /* R--VF */ +#define NV_NXBAR_TCP_ERROR_STATUS_TILEOUT10_DEFAULT 0x00000000 /* R---V */ +#endif // __ls10_dev_nxbar_tcp_global_ip_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_nxbar_tile_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_nxbar_tile_ip.h new file mode 100644 index 000000000..5a1b74680 --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_nxbar_tile_ip.h @@ -0,0 +1,189 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_nxbar_tile_ip_h__ +#define __ls10_dev_nxbar_tile_ip_h__ +/* This file is autogenerated. Do not edit */ +#define NV_NXBAR_TILE 0x00000FFF:0x00000000 /* RW--D */ +#define NV_NXBAR_TILE_CTRL0 0x00000040 /* RW-4R */ +#define NV_NXBAR_TILE_CTRL0_MULTI_VALID_XFN_CTRL 0:0 /* RWEVF */ +#define NV_NXBAR_TILE_CTRL0_MULTI_VALID_XFN_CTRL_ENABLE 0x00000000 /* RWE-V */ +#define NV_NXBAR_TILE_CTRL0_MULTI_VALID_XFN_CTRL_DISABLE 0x00000001 /* RW--V */ +#define NV_NXBAR_TILE_CTRL0_PARTIAL_RAM_WR_CTRL 8:8 /* RWEVF */ +#define NV_NXBAR_TILE_CTRL0_PARTIAL_RAM_WR_CTRL_ENABLE 0x00000000 /* RWE-V */ +#define NV_NXBAR_TILE_CTRL0_PARTIAL_RAM_WR_CTRL_DISABLE 0x00000001 /* RW--V */ +#define NV_NXBAR_TILE_CTRL0_PRI_FGCG_CTRL 16:16 /* RWEVF */ +#define NV_NXBAR_TILE_CTRL0_PRI_FGCG_CTRL_ENABLE 0x00000001 /* RW--V */ +#define NV_NXBAR_TILE_CTRL0_PRI_FGCG_CTRL_DISABLE 0x00000000 /* RWE-V */ +#define NV_NXBAR_TILE_CTRL0_PRI_FGCG_CTRL__PROD 0x00000001 /* RW--V */ +#define NV_NXBAR_TILE_ERR_STATUS 0x00000064 /* RW-4R */ +#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_STATUS_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_STATUS_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_STATUS_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_STATUS_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_PKT_INVALID_DST 7:7 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_PKT_INVALID_DST_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_PKT_PARITY_ERROR 8:8 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_PKT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_SIDEBAND_PARITY_ERROR 9:9 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_SIDEBAND_PARITY_ERROR_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_REDUCTION_PKT_ERROR 10:10 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_REDUCTION_PKT_ERROR_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN 0x0000006c /* RW-4R */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW_ENABLED 0x00000001 /* RW--V */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW__PROD 0x00000001 /* RW--V */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW_ENABLED 0x00000001 /* RW--V */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW__PROD 0x00000001 /* RW--V */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW_ENABLED 0x00000001 /* RW--V */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW__PROD 0x00000001 /* RW--V */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW_ENABLED 0x00000001 /* RW--V */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW__PROD 0x00000001 /* RW--V */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT_ENABLED 0x00000001 /* RW--V */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT__PROD 0x00000001 /* RW--V */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT_ENABLED 0x00000001 /* RW--V */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT__PROD 0x00000001 /* RW--V */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC_ENABLED 0x00000001 /* RW--V */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC__PROD 0x00000001 /* RW--V */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_PKT_INVALID_DST 7:7 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_PKT_INVALID_DST_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_PKT_INVALID_DST_ENABLED 0x00000001 /* RW--V */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_PKT_INVALID_DST__PROD 0x00000001 /* RW--V */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_PKT_PARITY_ERROR 8:8 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_PKT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_PKT_PARITY_ERROR_ENABLED 0x00000001 /* RW--V */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_PKT_PARITY_ERROR__PROD 0x00000001 /* RW--V */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_SIDEBAND_PARITY_ERROR 9:9 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_SIDEBAND_PARITY_ERROR_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_SIDEBAND_PARITY_ERROR_ENABLED 0x00000001 /* RW--V */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_SIDEBAND_PARITY_ERROR__PROD 0x00000001 /* RW--V */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_REDUCTION_PKT_ERROR 10:10 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_REDUCTION_PKT_ERROR_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_REDUCTION_PKT_ERROR_ENABLED 0x00000001 /* RW--V */ +#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_REDUCTION_PKT_ERROR__PROD 0x00000001 /* RW--V */ +#define NV_NXBAR_TILE_ERR_FIRST 0x00000070 /* RW-4R */ +#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_FIRST_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_FIRST_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_FIRST_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_FIRST_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_PKT_INVALID_DST 7:7 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_PKT_INVALID_DST_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_PKT_PARITY_ERROR 8:8 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_PKT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_SIDEBAND_PARITY_ERROR 9:9 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_SIDEBAND_PARITY_ERROR_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_REDUCTION_PKT_ERROR 10:10 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_REDUCTION_PKT_ERROR_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_FIRST_LOG_VC 15:12 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_FIRST_LOG_VC_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_FIRST_LOG_SRC 19:16 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_FIRST_LOG_SRC_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_ERR_FIRST_LOG_DST 27:24 /* RWIVF */ +#define NV_NXBAR_TILE_ERR_FIRST_LOG_DST_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG 0x00000048 /* RWE4R */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_IDLE_CG_DLY_CNT__PROD 0x00000008 /* RW--V */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_IDLE_CG_EN 6:6 /* RWEVF */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_STATE_CG_EN 7:7 /* */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_STATE_CG_EN__PROD 0x00000000 /* */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_STALL_CG_DLY_CNT 13:8 /* */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_STALL_CG_EN 14:14 /* RWEVF */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_QUIESCENT_CG_EN 15:15 /* */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_THROT_CLK_CNT 23:20 /* */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_DI_DT_SKEW_VAL 27:24 /* */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_THROT_CLK_EN 28:28 /* */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_THROT_CLK_EN__PROD 0x00000000 /* */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_THROT_CLK_SW_OVER 29:29 /* */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_PAUSE_CG_EN 30:30 /* */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_HALT_CG_EN 31:31 /* */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_HALT_CG_EN__PROD 0x00000000 /* */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG1 0x0000004C /* RWE4R */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ +#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ +#endif // __ls10_dev_nxbar_tile_ip_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_nxbar_tileout_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_nxbar_tileout_ip.h new file mode 100644 index 000000000..0c1d611f4 --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_nxbar_tileout_ip.h @@ -0,0 +1,165 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_nxbar_tileout_ip_h__ +#define __ls10_dev_nxbar_tileout_ip_h__ +/* This file is autogenerated. Do not edit */ +#define NV_NXBAR_TILEOUT 0x00000FFF:0x0000000 /* RW--D */ +#define NV_NXBAR_TILEOUT_CTRL0 0x00000040 /* RW-4R */ +#define NV_NXBAR_TILEOUT_CTRL0_MULTI_VALID_XFN_CTRL 0:0 /* RWEVF */ +#define NV_NXBAR_TILEOUT_CTRL0_MULTI_VALID_XFN_CTRL_ENABLE 0x00000000 /* RWE-V */ +#define NV_NXBAR_TILEOUT_CTRL0_MULTI_VALID_XFN_CTRL_DISABLE 0x00000001 /* RW--V */ +#define NV_NXBAR_TILEOUT_CTRL0_PARTIAL_RAM_WR_CTRL 8:8 /* RWEVF */ +#define NV_NXBAR_TILEOUT_CTRL0_PARTIAL_RAM_WR_CTRL_ENABLE 0x00000000 /* RWE-V */ +#define NV_NXBAR_TILEOUT_CTRL0_PARTIAL_RAM_WR_CTRL_DISABLE 0x00000001 /* RW--V */ +#define NV_NXBAR_TILEOUT_CTRL0_PRI_FGCG_CTRL 16:16 /* RWEVF */ +#define NV_NXBAR_TILEOUT_CTRL0_PRI_FGCG_CTRL_ENABLE 0x00000001 /* RW--V */ +#define NV_NXBAR_TILEOUT_CTRL0_PRI_FGCG_CTRL_DISABLE 0x00000000 /* RWE-V */ +#define NV_NXBAR_TILEOUT_CTRL0_PRI_FGCG_CTRL__PROD 0x00000001 /* RW--V */ +#define NV_NXBAR_TILEOUT_ERR_STATUS 0x00000064 /* RW-4R */ +#define NV_NXBAR_TILEOUT_ERR_STATUS_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */ +#define NV_NXBAR_TILEOUT_ERR_STATUS_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILEOUT_ERR_STATUS_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */ +#define NV_NXBAR_TILEOUT_ERR_STATUS_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILEOUT_ERR_STATUS_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */ +#define NV_NXBAR_TILEOUT_ERR_STATUS_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILEOUT_ERR_STATUS_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */ +#define NV_NXBAR_TILEOUT_ERR_STATUS_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILEOUT_ERR_STATUS_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */ +#define NV_NXBAR_TILEOUT_ERR_STATUS_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILEOUT_ERR_STATUS_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */ +#define NV_NXBAR_TILEOUT_ERR_STATUS_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILEOUT_ERR_STATUS_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */ +#define NV_NXBAR_TILEOUT_ERR_STATUS_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILEOUT_ERR_STATUS_EGRESS_CDT_PARITY_ERROR 7:7 /* RWIVF */ +#define NV_NXBAR_TILEOUT_ERR_STATUS_EGRESS_CDT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN 0x0000006c /* RW-4R */ +#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */ +#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW_ENABLED 0x00000001 /* RW--V */ +#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW__PROD 0x00000001 /* RW--V */ +#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */ +#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW_ENABLED 0x00000001 /* RW--V */ +#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW__PROD 0x00000001 /* RW--V */ +#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */ +#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW_ENABLED 0x00000001 /* RW--V */ +#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW__PROD 0x00000001 /* RW--V */ +#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */ +#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW_ENABLED 0x00000001 /* RW--V */ +#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW__PROD 0x00000001 /* RW--V */ +#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */ +#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT_ENABLED 0x00000001 /* RW--V */ +#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT__PROD 0x00000001 /* RW--V */ +#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */ +#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT_ENABLED 0x00000001 /* RW--V */ +#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT__PROD 0x00000001 /* RW--V */ +#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */ +#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC_ENABLED 0x00000001 /* RW--V */ +#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC__PROD 0x00000001 /* RW--V */ +#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR 7:7 /* RWIVF */ +#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR_ENABLED 0x00000001 /* RW--V */ +#define NV_NXBAR_TILEOUT_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR__PROD 0x00000001 /* RW--V */ +#define NV_NXBAR_TILEOUT_ERR_FIRST 0x00000070 /* RW-4R */ +#define NV_NXBAR_TILEOUT_ERR_FIRST_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */ +#define NV_NXBAR_TILEOUT_ERR_FIRST_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILEOUT_ERR_FIRST_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */ +#define NV_NXBAR_TILEOUT_ERR_FIRST_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILEOUT_ERR_FIRST_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */ +#define NV_NXBAR_TILEOUT_ERR_FIRST_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILEOUT_ERR_FIRST_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */ +#define NV_NXBAR_TILEOUT_ERR_FIRST_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILEOUT_ERR_FIRST_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */ +#define NV_NXBAR_TILEOUT_ERR_FIRST_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILEOUT_ERR_FIRST_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */ +#define NV_NXBAR_TILEOUT_ERR_FIRST_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILEOUT_ERR_FIRST_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */ +#define NV_NXBAR_TILEOUT_ERR_FIRST_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILEOUT_ERR_FIRST_EGRESS_CDT_PARITY_ERROR 7:7 /* RWIVF */ +#define NV_NXBAR_TILEOUT_ERR_FIRST_EGRESS_CDT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILEOUT_ERR_FIRST_LOG_VC 15:12 /* RWIVF */ +#define NV_NXBAR_TILEOUT_ERR_FIRST_LOG_VC_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILEOUT_ERR_FIRST_LOG_SRC 19:16 /* RWIVF */ +#define NV_NXBAR_TILEOUT_ERR_FIRST_LOG_SRC_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILEOUT_ERR_FIRST_LOG_DST 25:24 /* RWIVF */ +#define NV_NXBAR_TILEOUT_ERR_FIRST_LOG_DST_INIT 0x00000000 /* RWI-V */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG 0x00000048 /* RWE4R */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_IDLE_CG_DLY_CNT__PROD 0x00000008 /* RW--V */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_IDLE_CG_EN 6:6 /* RWEVF */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_STATE_CG_EN 7:7 /* */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_STATE_CG_EN__PROD 0x00000000 /* */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_STALL_CG_DLY_CNT 13:8 /* */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_STALL_CG_EN 14:14 /* RWEVF */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_QUIESCENT_CG_EN 15:15 /* */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_THROT_CLK_CNT 23:20 /* */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_DI_DT_SKEW_VAL 27:24 /* */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_THROT_CLK_EN 28:28 /* */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_THROT_CLK_EN__PROD 0x00000000 /* */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_THROT_CLK_SW_OVER 29:29 /* */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_PAUSE_CG_EN 30:30 /* */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_HALT_CG_EN 31:31 /* */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG_HALT_CG_EN__PROD 0x00000000 /* */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG1 0x0000004C /* RWE4R */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ +#define NV_NXBAR_TILEOUT_PRI_NXBAR_TILEOUT_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ +#endif // __ls10_dev_nxbar_tileout_ip_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_perf.h b/src/common/inc/swref/published/nvswitch/ls10/dev_perf.h new file mode 100644 index 000000000..4e822703c --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_perf.h @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_perf_h__ +#define __ls10_dev_perf_h__ +/* This file is autogenerated. Do not edit */ +#define NV_PERF_PMM_PERDOMAIN_OFFSET 0x00000200 /* */ +#define NV_PERF_PMM 0x000003FF:0x00000000 /* RW--D */ +#define NV_PERF_PMMROUTER 0x000001FF:0x00000000 /* RW--D */ +#define NV_PERF_PMMROUTER_CG2 0x00000040 /* RW-4R */ +#define NV_PERF_PMMROUTER_CG2_SLCG 31:31 /* RWEVF */ +#define NV_PERF_PMMROUTER_CG2_SLCG_ENABLED 0x00000000 /* RWE-V */ +#define NV_PERF_PMMROUTER_CG2_SLCG_DISABLED 0x00000001 /* RW--V */ +#define NV_PERF_PMMROUTER_CG1_SECURE 0x00000054 /* RW-4R */ +#define NV_PERF_PMMROUTER_CG1_SECURE_FLCG_PERFMON 31:31 /* RWEUF */ +#define NV_PERF_PMMROUTER_CG1_SECURE_FLCG_PERFMON_DISABLED 0x00000000 /* RWE-V */ +#define NV_PERF_PMMROUTER_CG1_SECURE_FLCG_PERFMON__PROD 0x00000001 /* RW--V */ +#define NV_PERF_PMMROUTER_CG1_SECURE_FLCG_PERFMON_ENABLED 0x00000001 /* RW--V */ +#define NV_PERF_PMMROUTER_PERFMON_CG2_SECURE 0x00000058 /* RW-4R */ +#define NV_PERF_PMMROUTER_PERFMON_CG2_SECURE_SLCG 31:31 /* RWEUF */ +#define NV_PERF_PMMROUTER_PERFMON_CG2_SECURE_SLCG_ENABLED 0x00000000 /* RWE-V */ +#define NV_PERF_PMMROUTER_PERFMON_CG2_SECURE_SLCG__PROD 0x00000000 /* RW--V */ +#define NV_PERF_PMMROUTER_PERFMON_CG2_SECURE_SLCG_DISABLED 0x00000001 /* RW--V */ +#endif // __ls10_dev_perf_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_pmgr.h b/src/common/inc/swref/published/nvswitch/ls10/dev_pmgr.h new file mode 100644 index 000000000..ba00c7f32 --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_pmgr.h @@ -0,0 +1,85 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_pmgr_h__ +#define __ls10_dev_pmgr_h__ +/* This file is autogenerated. Do not edit */ +#define NV_PMGR_ALL 0x003FFFFF:0x0000D000 /* RW--D */ +#define NV_PMGR_I2C_PRIV_LEVEL_MASK(i) (0x0000D7A0 + (i)*0x4) /* RW-4A */ +#define NV_PMGR_I2C_PRIV_LEVEL_MASK__SIZE_1 10 /* */ +#define NV_PMGR_I2C_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ +#define NV_PMGR_I2C_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */ +#define NV_PMGR_I2C_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ +#define NV_PMGR_I2C_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_i2cx_wr_secure" /* */ +#define NV_PMGR_I2C_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */ +#define NV_PMGR_I2C_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLED_FUSE1 0x0000000E /* RW--V */ +#define NV_PMGR_I2C_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE2 0x0000000C /* RW--V */ +#define NV_PMGR_I2C_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE3 0x00000008 /* RW--V */ +#define NV_PMGR_I2C_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ +#define NV_PMGR_I2C_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ +#define NV_PMGR_I2C_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ +#define NV_PMGR_I2C_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ +#define NV_PMGR_I2C_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ +#define NV_PMGR_I2C_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ +#define NV_PMGR_I2C_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ +#define NV_PMGR_I2C_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ +#define NV_PMGR_I2C_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ +#define NV_PMGR_I2C_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ +#define NV_PMGR_I2C_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ +#define NV_PMGR_I2C_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ +#define NV_PMGR_I2C_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ +#define NV_PMGR_I2C_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_pmgr_i2cx_wr_secure"/* */ +#define NV_PMGR_I2C_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWI-V */ +#define NV_PMGR_I2C_PRIV_LEVEL_MASK_SOURCE_ENABLE_INIT_FUSE1 0x0008094F /* RW--V */ +#define NV_PMGR_I2C_PRIV_LEVEL_MASK_SOURCE_ENABLE_INIT_FUSE2 0x0008094F /* RW--V */ +#define NV_PMGR_I2C_PRIV_LEVEL_MASK_SOURCE_ENABLE_INIT_FUSE3 0x0008094F /* RW--V */ +#define NV_PMGR_I2C_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 +#define NV_PMGR_I2C_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 +#define NV_PMGR_I2C_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 +#define NV_PMGR_GPIO_INPUT_CNTL_1 0x0000D740 /* RW-4R */ +#define NV_PMGR_GPIO_INPUT_CNTL_1_PINNUM 7:0 /* RWIVF */ +#define NV_PMGR_GPIO_INPUT_CNTL_1_PINNUM_INIT 0x00000001 /* RWI-V */ +#define NV_PMGR_GPIO_INPUT_CNTL_1_INV 8:8 /* RWIVF */ +#define NV_PMGR_GPIO_INPUT_CNTL_1_INV_NO 0x00000000 /* RWI-V */ +#define NV_PMGR_GPIO_INPUT_CNTL_1_INV_YES 0x00000001 /* RW--V */ +#define NV_PMGR_GPIO_INPUT_CNTL_1_READ 9:9 /* R--VF */ +#define NV_PMGR_GPIO_INPUT_CNTL_1_READ_0 0x00000000 /* R---V */ +#define NV_PMGR_GPIO_INPUT_CNTL_1_READ_1 0x00000001 /* R---V */ +#define NV_PMGR_GPIO_INPUT_CNTL_1_BYPASS_FILTER 10:10 /* RWIVF */ +#define NV_PMGR_GPIO_INPUT_CNTL_1_BYPASS_FILTER_INIT 0x00000000 /* RWI-V */ +#define NV_PMGR_GPIO_INPUT_CNTL_1_BYPASS_FILTER_NO 0x00000000 /* RW--V */ +#define NV_PMGR_GPIO_INPUT_CNTL_1_BYPASS_FILTER_YES 0x00000001 /* RW--V */ +#define NV_PMGR_GPIO_INPUT_CNTL(i) 0x0000D740 + ((i)-1) * (0x0000D744 - 0x0000D740) /* */ +#define NV_PMGR_GPIO_INPUT_CNTL__SIZE_1 25 /* */ +#define NV_PMGR_GPIO_INPUT_CNTL_PINNUM 7:0 /* */ +#define NV_PMGR_GPIO_INPUT_CNTL_PINNUM_UNUSED 0x000000FF /* */ +#define NV_PMGR_GPIO_INPUT_CNTL_INV 8:8 /* */ +#define NV_PMGR_GPIO_INPUT_CNTL_INV_NO 0x00000000 /* */ +#define NV_PMGR_GPIO_INPUT_CNTL_INV_YES 0x00000001 /* */ +#define NV_PMGR_GPIO_INPUT_CNTL_READ 9:9 /* */ +#define NV_PMGR_GPIO_INPUT_CNTL_READ_0 0x00000000 /* */ +#define NV_PMGR_GPIO_INPUT_CNTL_READ_1 0x00000001 /* */ +#define NV_PMGR_GPIO_INPUT_CNTL_BYPASS_FILTER 10:10 /* */ +#define NV_PMGR_GPIO_INPUT_CNTL_BYPASS_FILTER_NO 0x00000000 /* */ +#define NV_PMGR_GPIO_INPUT_CNTL_BYPASS_FILTER_YES 0x00000001 /* */ +#endif // __ls10_dev_pmgr_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_pri_hub_prt_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_pri_hub_prt_ip.h new file mode 100644 index 000000000..ef54c0aa8 --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_pri_hub_prt_ip.h @@ -0,0 +1,73 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_pri_hub_prt_ip_h__ +#define __ls10_dev_pri_hub_prt_ip_h__ +/* This file is autogenerated. Do not edit */ +#define NV_PPRIV_PRT 0x000007ff:0x00000000 /* RW--D */ +#define NV_PPRIV_PRT_PRIV_ERROR_ADR 0x00000020 /* R--4R */ +#define NV_PPRIV_PRT_PRIV_ERROR_WRDAT 0x00000024 /* R--4R */ +#define NV_PPRIV_PRT_PRIV_ERROR_INFO 0x00000028 /* R--4R */ +#define NV_PPRIV_PRT_PRIV_ERROR_CODE 0x0000002c /* R--4R */ +#define NV_PPRIV_PRT_CG1 0x00000150 /* RW-4R */ +#define NV_PPRIV_PRT_CG1_SLCG 10:0 /* */ +#define NV_PPRIV_PRT_CG1_SLCG_ENABLED 0x000 /* */ +#define NV_PPRIV_PRT_CG1_SLCG_DISABLED 0x7ff /* */ +#define NV_PPRIV_PRT_CG1_SLCG__PROD 0x000 /* */ +#define NV_PPRIV_PRT_CG1_SLCG_SLOWCLK 0:0 /* RWBVF */ +#define NV_PPRIV_PRT_CG1_SLCG_SLOWCLK_ENABLED 0x0 /* RW--V */ +#define NV_PPRIV_PRT_CG1_SLCG_SLOWCLK_DISABLED 0x1 /* RWB-V */ +#define NV_PPRIV_PRT_CG1_SLCG_SLOWCLK__PROD 0x0 /* RW--V */ +#define NV_PPRIV_PRT_CG1_SLCG_PRIV_CONFIG_REGS 1:1 /* RWBVF */ +#define NV_PPRIV_PRT_CG1_SLCG_PRIV_CONFIG_REGS_ENABLED 0x0 /* RW--V */ +#define NV_PPRIV_PRT_CG1_SLCG_PRIV_CONFIG_REGS_DISABLED 0x1 /* RWB-V */ +#define NV_PPRIV_PRT_CG1_SLCG_PRIV_CONFIG_REGS__PROD 0x0 /* RW--V */ +#define NV_PPRIV_PRT_CG1_SLCG_PRIV_FUNNEL_DECODER 2:2 /* RWBVF */ +#define NV_PPRIV_PRT_CG1_SLCG_PRIV_FUNNEL_DECODER_ENABLED 0x0 /* RW--V */ +#define NV_PPRIV_PRT_CG1_SLCG_PRIV_FUNNEL_DECODER_DISABLED 0x1 /* RWB-V */ +#define NV_PPRIV_PRT_CG1_SLCG_PRIV_FUNNEL_DECODER__PROD 0x0 /* RW--V */ +#define NV_PPRIV_PRT_CG1_SLCG_PRIV_FUNNEL_ARB 3:3 /* RWBVF */ +#define NV_PPRIV_PRT_CG1_SLCG_PRIV_FUNNEL_ARB_ENABLED 0x0 /* RW--V */ +#define NV_PPRIV_PRT_CG1_SLCG_PRIV_FUNNEL_ARB_DISABLED 0x1 /* RWB-V */ +#define NV_PPRIV_PRT_CG1_SLCG_PRIV_FUNNEL_ARB__PROD 0x0 /* RW--V */ +#define NV_PPRIV_PRT_CG1_SLCG_PRIV_HISTORY_BUFFER 4:4 /* RWBVF */ +#define NV_PPRIV_PRT_CG1_SLCG_PRIV_HISTORY_BUFFER_ENABLED 0x0 /* RW--V */ +#define NV_PPRIV_PRT_CG1_SLCG_PRIV_HISTORY_BUFFER_DISABLED 0x1 /* RWB-V */ +#define NV_PPRIV_PRT_CG1_SLCG_PRIV_HISTORY_BUFFER__PROD 0x0 /* RW--V */ +#define NV_PPRIV_PRT_CG1_SLCG_PRIV_MASTER 5:5 /* RWBVF */ +#define NV_PPRIV_PRT_CG1_SLCG_PRIV_MASTER_ENABLED 0x0 /* RW--V */ +#define NV_PPRIV_PRT_CG1_SLCG_PRIV_MASTER_DISABLED 0x1 /* RWB-V */ +#define NV_PPRIV_PRT_CG1_SLCG_PRIV_MASTER__PROD 0x0 /* RW--V */ +#define NV_PPRIV_PRT_CG1_SLCG_PRIV_SLAVE 6:6 /* RWBVF */ +#define NV_PPRIV_PRT_CG1_SLCG_PRIV_SLAVE_ENABLED 0x0 /* RW--V */ +#define NV_PPRIV_PRT_CG1_SLCG_PRIV_SLAVE_DISABLED 0x1 /* RWB-V */ +#define NV_PPRIV_PRT_CG1_SLCG_PRIV_SLAVE__PROD 0x0 /* RW--V */ +#define NV_PPRIV_PRT_CG1_SLCG_LOC_PRIV 9:9 /* RWBVF */ +#define NV_PPRIV_PRT_CG1_SLCG_LOC_PRIV_ENABLED 0x0 /* RW--V */ +#define NV_PPRIV_PRT_CG1_SLCG_LOC_PRIV_DISABLED 0x1 /* RWB-V */ +#define NV_PPRIV_PRT_CG1_SLCG_LOC_PRIV__PROD 0x0 /* RW--V */ +#define NV_PPRIV_PRT_CG1_SLCG_PM 10:10 /* RWBVF */ +#define NV_PPRIV_PRT_CG1_SLCG_PM_ENABLED 0x0 /* RW--V */ +#define NV_PPRIV_PRT_CG1_SLCG_PM_DISABLED 0x1 /* RWB-V */ +#define NV_PPRIV_PRT_CG1_SLCG_PM__PROD 0x0 /* RW--V */ +#endif // __ls10_dev_pri_hub_prt_ip_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_pri_hub_sys_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_pri_hub_sys_ip.h new file mode 100644 index 000000000..0c08fb972 --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_pri_hub_sys_ip.h @@ -0,0 +1,86 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_pri_hub_sys_ip_h__ +#define __ls10_dev_pri_hub_sys_ip_h__ +/* This file is autogenerated. Do not edit */ +#define NV_PPRIV_SYS 0x000007ff:0x00000000 /* RW--D */ +#define NV_PPRIV_SYS_PRIV_ERROR_ADR 0x00000020 /* R--4R */ +#define NV_PPRIV_SYS_PRIV_ERROR_WRDAT 0x00000024 /* R--4R */ +#define NV_PPRIV_SYS_PRIV_ERROR_INFO 0x00000028 /* R--4R */ +#define NV_PPRIV_SYS_PRIV_ERROR_CODE 0x0000002c /* R--4R */ +#define NV_PPRIV_SYS_PRI_RING_INIT 0x00000174 /* RW-4R */ +#define NV_PPRIV_SYS_PRI_RING_INIT_STATUS 2:0 /* R--VF */ +#define NV_PPRIV_SYS_PRI_RING_INIT_STATUS_DEAD 0x0 /* R---V */ +#define NV_PPRIV_SYS_PRI_RING_INIT_STATUS_CMD_RDY 0x1 /* R---V */ +#define NV_PPRIV_SYS_PRI_RING_INIT_STATUS_ALIVE_IN_SAFE_MODE 0x2 /* R---V */ +#define NV_PPRIV_SYS_PRI_RING_INIT_STATUS_ERROR 0x3 /* R---V */ +#define NV_PPRIV_SYS_PRI_RING_INIT_STATUS_ALIVE 0x4 /* R---V */ +#define NV_PPRIV_SYS_PRI_RING_INIT_CMD 9:8 /* RWBVF */ +#define NV_PPRIV_SYS_PRI_RING_INIT_CMD_NONE 0x0 /* RWB-V */ +#define NV_PPRIV_SYS_PRI_RING_INIT_CMD_ENUMERATE_AND_START 0x1 /* RW--T */ +#define NV_PPRIV_SYS_PRI_RING_INIT_CMD_SAFE_START 0x2 /* RW--T */ +#define NV_PPRIV_SYS_PRI_RING_INIT_CMD_TOGGLE_RESET 0x3 /* RW--T */ +#define NV_PPRIV_SYS_CG1 0x00000150 /* RW-4R */ +#define NV_PPRIV_SYS_CG1_SLCG 10:0 /* */ +#define NV_PPRIV_SYS_CG1_SLCG_ENABLED 0x000 /* */ +#define NV_PPRIV_SYS_CG1_SLCG_DISABLED 0x7ff /* */ +#define NV_PPRIV_SYS_CG1_SLCG__PROD 0x000 /* */ +#define NV_PPRIV_SYS_CG1_SLCG_SLOWCLK 0:0 /* RWBVF */ +#define NV_PPRIV_SYS_CG1_SLCG_SLOWCLK_ENABLED 0x0 /* RW--V */ +#define NV_PPRIV_SYS_CG1_SLCG_SLOWCLK_DISABLED 0x1 /* RWB-V */ +#define NV_PPRIV_SYS_CG1_SLCG_SLOWCLK__PROD 0x0 /* RW--V */ +#define NV_PPRIV_SYS_CG1_SLCG_PRIV_CONFIG_REGS 1:1 /* RWBVF */ +#define NV_PPRIV_SYS_CG1_SLCG_PRIV_CONFIG_REGS_ENABLED 0x0 /* RW--V */ +#define NV_PPRIV_SYS_CG1_SLCG_PRIV_CONFIG_REGS_DISABLED 0x1 /* RWB-V */ +#define NV_PPRIV_SYS_CG1_SLCG_PRIV_CONFIG_REGS__PROD 0x0 /* RW--V */ +#define NV_PPRIV_SYS_CG1_SLCG_PRIV_FUNNEL_DECODER 2:2 /* RWBVF */ +#define NV_PPRIV_SYS_CG1_SLCG_PRIV_FUNNEL_DECODER_ENABLED 0x0 /* RW--V */ +#define NV_PPRIV_SYS_CG1_SLCG_PRIV_FUNNEL_DECODER_DISABLED 0x1 /* RWB-V */ +#define NV_PPRIV_SYS_CG1_SLCG_PRIV_FUNNEL_DECODER__PROD 0x0 /* RW--V */ +#define NV_PPRIV_SYS_CG1_SLCG_PRIV_FUNNEL_ARB 3:3 /* RWBVF */ +#define NV_PPRIV_SYS_CG1_SLCG_PRIV_FUNNEL_ARB_ENABLED 0x0 /* RW--V */ +#define NV_PPRIV_SYS_CG1_SLCG_PRIV_FUNNEL_ARB_DISABLED 0x1 /* RWB-V */ +#define NV_PPRIV_SYS_CG1_SLCG_PRIV_FUNNEL_ARB__PROD 0x0 /* RW--V */ +#define NV_PPRIV_SYS_CG1_SLCG_PRIV_HISTORY_BUFFER 4:4 /* RWBVF */ +#define NV_PPRIV_SYS_CG1_SLCG_PRIV_HISTORY_BUFFER_ENABLED 0x0 /* RW--V */ +#define NV_PPRIV_SYS_CG1_SLCG_PRIV_HISTORY_BUFFER_DISABLED 0x1 /* RWB-V */ +#define NV_PPRIV_SYS_CG1_SLCG_PRIV_HISTORY_BUFFER__PROD 0x0 /* RW--V */ +#define NV_PPRIV_SYS_CG1_SLCG_PRIV_MASTER 5:5 /* RWBVF */ +#define NV_PPRIV_SYS_CG1_SLCG_PRIV_MASTER_ENABLED 0x0 /* RW--V */ +#define NV_PPRIV_SYS_CG1_SLCG_PRIV_MASTER_DISABLED 0x1 /* RWB-V */ +#define NV_PPRIV_SYS_CG1_SLCG_PRIV_MASTER__PROD 0x0 /* RW--V */ +#define NV_PPRIV_SYS_CG1_SLCG_PRIV_SLAVE 6:6 /* RWBVF */ +#define NV_PPRIV_SYS_CG1_SLCG_PRIV_SLAVE_ENABLED 0x0 /* RW--V */ +#define NV_PPRIV_SYS_CG1_SLCG_PRIV_SLAVE_DISABLED 0x1 /* RWB-V */ +#define NV_PPRIV_SYS_CG1_SLCG_PRIV_SLAVE__PROD 0x0 /* RW--V */ +#define NV_PPRIV_SYS_CG1_SLCG_LOC_PRIV 9:9 /* RWBVF */ +#define NV_PPRIV_SYS_CG1_SLCG_LOC_PRIV_ENABLED 0x0 /* RW--V */ +#define NV_PPRIV_SYS_CG1_SLCG_LOC_PRIV_DISABLED 0x1 /* RWB-V */ +#define NV_PPRIV_SYS_CG1_SLCG_LOC_PRIV__PROD 0x0 /* RW--V */ +#define NV_PPRIV_SYS_CG1_SLCG_PM 10:10 /* RWBVF */ +#define NV_PPRIV_SYS_CG1_SLCG_PM_ENABLED 0x0 /* RW--V */ +#define NV_PPRIV_SYS_CG1_SLCG_PM_DISABLED 0x1 /* RWB-V */ +#define NV_PPRIV_SYS_CG1_SLCG_PM__PROD 0x0 /* RW--V */ +#endif // __ls10_dev_pri_hub_sys_ip_h__ + diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_pri_hub_sysb_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_pri_hub_sysb_ip.h new file mode 100644 index 000000000..f03e7f696 --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_pri_hub_sysb_ip.h @@ -0,0 +1,74 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_pri_hub_sysb_ip_h__ +#define __ls10_dev_pri_hub_sysb_ip_h__ +/* This file is autogenerated. Do not edit */ +#define NV_PPRIV_SYSB 0x000007ff:0x00000000 /* RW--D */ +#define NV_PPRIV_SYSB_PRIV_ERROR_ADR 0x00000020 /* R--4R */ +#define NV_PPRIV_SYSB_PRIV_ERROR_WRDAT 0x00000024 /* R--4R */ +#define NV_PPRIV_SYSB_PRIV_ERROR_INFO 0x00000028 /* R--4R */ +#define NV_PPRIV_SYSB_PRIV_ERROR_CODE 0x0000002c /* R--4R */ +#define NV_PPRIV_SYSB_CG1 0x00000150 /* RW-4R */ +#define NV_PPRIV_SYSB_CG1_SLCG 10:0 /* */ +#define NV_PPRIV_SYSB_CG1_SLCG_ENABLED 0x000 /* */ +#define NV_PPRIV_SYSB_CG1_SLCG_DISABLED 0x7ff /* */ +#define NV_PPRIV_SYSB_CG1_SLCG__PROD 0x000 /* */ +#define NV_PPRIV_SYSB_CG1_SLCG_SLOWCLK 0:0 /* RWBVF */ +#define NV_PPRIV_SYSB_CG1_SLCG_SLOWCLK_ENABLED 0x0 /* RW--V */ +#define NV_PPRIV_SYSB_CG1_SLCG_SLOWCLK_DISABLED 0x1 /* RWB-V */ +#define NV_PPRIV_SYSB_CG1_SLCG_SLOWCLK__PROD 0x0 /* RW--V */ +#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_CONFIG_REGS 1:1 /* RWBVF */ +#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_CONFIG_REGS_ENABLED 0x0 /* RW--V */ +#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_CONFIG_REGS_DISABLED 0x1 /* RWB-V */ +#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_CONFIG_REGS__PROD 0x0 /* RW--V */ +#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_FUNNEL_DECODER 2:2 /* RWBVF */ +#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_FUNNEL_DECODER_ENABLED 0x0 /* RW--V */ +#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_FUNNEL_DECODER_DISABLED 0x1 /* RWB-V */ +#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_FUNNEL_DECODER__PROD 0x0 /* RW--V */ +#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_FUNNEL_ARB 3:3 /* RWBVF */ +#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_FUNNEL_ARB_ENABLED 0x0 /* RW--V */ +#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_FUNNEL_ARB_DISABLED 0x1 /* RWB-V */ +#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_FUNNEL_ARB__PROD 0x0 /* RW--V */ +#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_HISTORY_BUFFER 4:4 /* RWBVF */ +#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_HISTORY_BUFFER_ENABLED 0x0 /* RW--V */ +#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_HISTORY_BUFFER_DISABLED 0x1 /* RWB-V */ +#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_HISTORY_BUFFER__PROD 0x0 /* RW--V */ +#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_MASTER 5:5 /* RWBVF */ +#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_MASTER_ENABLED 0x0 /* RW--V */ +#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_MASTER_DISABLED 0x1 /* RWB-V */ +#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_MASTER__PROD 0x0 /* RW--V */ +#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_SLAVE 6:6 /* RWBVF */ +#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_SLAVE_ENABLED 0x0 /* RW--V */ +#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_SLAVE_DISABLED 0x1 /* RWB-V */ +#define NV_PPRIV_SYSB_CG1_SLCG_PRIV_SLAVE__PROD 0x0 /* RW--V */ +#define NV_PPRIV_SYSB_CG1_SLCG_LOC_PRIV 9:9 /* RWBVF */ +#define NV_PPRIV_SYSB_CG1_SLCG_LOC_PRIV_ENABLED 0x0 /* RW--V */ +#define NV_PPRIV_SYSB_CG1_SLCG_LOC_PRIV_DISABLED 0x1 /* RWB-V */ +#define NV_PPRIV_SYSB_CG1_SLCG_LOC_PRIV__PROD 0x0 /* RW--V */ +#define NV_PPRIV_SYSB_CG1_SLCG_PM 10:10 /* RWBVF */ +#define NV_PPRIV_SYSB_CG1_SLCG_PM_ENABLED 0x0 /* RW--V */ +#define NV_PPRIV_SYSB_CG1_SLCG_PM_DISABLED 0x1 /* RWB-V */ +#define NV_PPRIV_SYSB_CG1_SLCG_PM__PROD 0x0 /* RW--V */ +#endif // __ls10_dev_pri_hub_sysb_ip_h__ + diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_pri_masterstation_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_pri_masterstation_ip.h new file mode 100644 index 000000000..f38e21baa --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_pri_masterstation_ip.h @@ -0,0 +1,82 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_pri_masterstation_ip_h__ +#define __ls10_dev_pri_masterstation_ip_h__ +/* This file is autogenerated. Do not edit */ +#define NV_PPRIV_MASTER_RING_COMMAND 0x0000004c /* RW-4R */ +#define NV_PPRIV_MASTER_RING_COMMAND_CMD 5:0 /* RWBVF */ +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_START_RING_RESET_VAL_0 0x01 /* RW--T */ +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_CMD_RESET_VAL_1 0x00 /* RWB-V */ +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_CMD 0x00 /* RW--V */ +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_START_RING 0x01 /* RW--T */ +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ACK_INTERRUPT 0x02 /* RW--T */ +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS 0x03 /* RW--T */ +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_AND_START_RING 0x04 /* RW--T */ +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_TAG_ENUMERATE_AND_START_RING 0x05 /* RW--T */ +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP 9:6 /* RWBVF */ +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_ALL 0x0 /* RWB-V */ +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_GPC 0x1 /* RW--V */ +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_FBP 0x2 /* RW--V */ +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_SYS 0x3 /* RW--V */ +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_L2 0x4 /* RW--V */ +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_SYSB 0x5 /* RW--V */ +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_ALL 0x8 /* RW--V */ +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_GPC 0x9 /* RW--V */ +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_FBP 0xa /* RW--V */ +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_SYS 0xb /* RW--V */ +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_L2 0xc /* RW--V */ +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_SYSB 0xd /* RW--V */ +#define NV_PPRIV_MASTER_RING_START_RESULTS 0x00000050 /* R--4R */ +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY 0:0 /* R-BVF */ +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_PASS 0x1 /* R---V */ +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_FAIL 0x0 /* R-B-V */ +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0 0x00000058 /* R--4R */ +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_FBP 31:16 /* R-BVF */ +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_FBP_V 0x0000 /* R-B-V */ +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_SYS 8:8 /* R-BVF */ +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_SYS_V 0x0 /* R-B-V */ +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_SYSB 9:9 /* R-BVF */ +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_SYSB_V 0x0 /* R-B-V */ +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_RING_START_CONN_FAULT 0:0 /* R-BVF */ +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_RING_START_CONN_FAULT_V 0x0 /* R-B-V */ +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_DISCONNECT_FAULT 1:1 /* R-BVF */ +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_DISCONNECT_FAULT_V 0x0 /* R-B-V */ +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_OVERFLOW_FAULT 2:2 /* R-BVF */ +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_OVERFLOW_FAULT_V 0x0 /* R-B-V */ +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_RING_ENUMERATION_FAULT 3:3 /* R-BVF */ +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_RING_ENUMERATION_FAULT_V 0x0 /* R-B-V */ +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GPC_RS_MAP_CONFIG_FAULT 4:4 /* R-BVF */ +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GPC_RS_MAP_CONFIG_FAULT_V 0x0 /* R-B-V */ +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_DEBUG_INTR_FAULT 5:5 /* R-BVF */ +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_DEBUG_INTR_FAULT_V 0x0 /* R-B-V */ +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1 0x0000005c /* R--4R */ +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1_GBL_WRITE_ERROR_GPC 31:0 /* R-BVF */ +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1_GBL_WRITE_ERROR_GPC_V 0x00000000 /* R-B-V */ +#define NV_PPRIV_MASTER 0x000003ff:0x00000000 /* RW--D */ +#define NV_PPRIV_MASTER_CG1 0x000000a8 /* RW-4R */ +#define NV_PPRIV_MASTER_CG1_SLCG 0:0 /* RWBVF */ +#define NV_PPRIV_MASTER_CG1_SLCG__PROD 0x0 /* RW--V */ +#define NV_PPRIV_MASTER_CG1_SLCG_ENABLED 0x0 /* RW--V */ +#define NV_PPRIV_MASTER_CG1_SLCG_DISABLED 0x1 /* RWB-V */ +#endif // __ls10_dev_pri_masterstation_ip_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_pri_ringstation_prt_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_pri_ringstation_prt_ip.h new file mode 100644 index 000000000..11d356e09 --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_pri_ringstation_prt_ip.h @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_pri_ringstation_prt_ip_h__ +#define __ls10_dev_pri_ringstation_prt_ip_h__ +/* This file is autogenerated. Do not edit */ +#define NV_PPRIV_RS_CTRL_PRT 0x000000ff:0x00000000 /* RW--D */ +#define NV_PPRIV_RS_CTRL_PRT_CG1 0x00000048 /* RW-4R */ +#define NV_PPRIV_RS_CTRL_PRT_CG1_SLCG 1:0 /* RWBVF */ +#define NV_PPRIV_RS_CTRL_PRT_CG1_SLCG_ENABLED 0x0 /* RW--V */ +#define NV_PPRIV_RS_CTRL_PRT_CG1_SLCG_DISABLED 0x3 /* RWB-V */ +#define NV_PPRIV_RS_CTRL_PRT_CG1_SLCG__PROD 0x0 /* RW--V */ +#endif // __ls10_dev_pri_ringstation_prt_ip_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_pri_ringstation_sys_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_pri_ringstation_sys_ip.h new file mode 100644 index 000000000..ecba469c6 --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_pri_ringstation_sys_ip.h @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_pri_ringstation_sys_ip_h__ +#define __ls10_dev_pri_ringstation_sys_ip_h__ +/* This file is autogenerated. Do not edit */ +#define NV_PPRIV_RS_CTRL_SYS 0x000000ff:0x00000000 /* RW--D */ +#define NV_PPRIV_RS_CTRL_SYS_CG1 0x00000048 /* RW-4R */ +#define NV_PPRIV_RS_CTRL_SYS_CG1_SLCG 1:0 /* RWBVF */ +#define NV_PPRIV_RS_CTRL_SYS_CG1_SLCG_ENABLED 0x0 /* RW--V */ +#define NV_PPRIV_RS_CTRL_SYS_CG1_SLCG_DISABLED 0x3 /* RWB-V */ +#define NV_PPRIV_RS_CTRL_SYS_CG1_SLCG__PROD 0x0 /* RW--V */ +#endif // __ls10_dev_pri_ringstation_sys_ip_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_pri_ringstation_sysb_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_pri_ringstation_sysb_ip.h new file mode 100644 index 000000000..71e40991e --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_pri_ringstation_sysb_ip.h @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_pri_ringstation_sysb_ip_h__ +#define __ls10_dev_pri_ringstation_sysb_ip_h__ +/* This file is autogenerated. Do not edit */ +#define NV_PPRIV_RS_CTRL_SYSB 0x000000ff:0x00000000 /* RW--D */ +#define NV_PPRIV_RS_CTRL_SYSB_CG1 0x00000048 /* RW-4R */ +#define NV_PPRIV_RS_CTRL_SYSB_CG1_SLCG 1:0 /* RWBVF */ +#define NV_PPRIV_RS_CTRL_SYSB_CG1_SLCG_ENABLED 0x0 /* RW--V */ +#define NV_PPRIV_RS_CTRL_SYSB_CG1_SLCG_DISABLED 0x3 /* RWB-V */ +#define NV_PPRIV_RS_CTRL_SYSB_CG1_SLCG__PROD 0x0 /* RW--V */ +#endif // __ls10_dev_pri_ringstation_sysb_ip_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_reductiontstate_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_reductiontstate_ip.h new file mode 100644 index 000000000..d639307b0 --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_reductiontstate_ip.h @@ -0,0 +1,283 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_reductiontstate_ip_h__ +#define __ls10_dev_reductiontstate_ip_h__ +/* This file is autogenerated. Do not edit */ +#define NV_REDUCTIONTSTATE 0x00002fff:0x00002800 /* RW--D */ +#define NV_REDUCTIONTSTATE_ERR_STATUS_0 0x00002c00 /* RW-4R */ +#define NV_REDUCTIONTSTATE_ERR_STATUS_0_TAGPOOL_ECC_LIMIT_ERR 2:2 /* RWDVF */ +#define NV_REDUCTIONTSTATE_ERR_STATUS_0_TAGPOOL_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_REDUCTIONTSTATE_ERR_STATUS_0_TAGPOOL_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_REDUCTIONTSTATE_ERR_STATUS_0_TAGPOOL_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_STATUS_0_TAGPOOL_ECC_DBE_ERR 3:3 /* RWDVF */ +#define NV_REDUCTIONTSTATE_ERR_STATUS_0_TAGPOOL_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_REDUCTIONTSTATE_ERR_STATUS_0_TAGPOOL_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_REDUCTIONTSTATE_ERR_STATUS_0_TAGPOOL_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_STATUS_0_CRUMBSTORE_BUF_OVERWRITE_ERR 16:16 /* RWDVF */ +#define NV_REDUCTIONTSTATE_ERR_STATUS_0_CRUMBSTORE_BUF_OVERWRITE_ERR__ONWRITE "oneToClear" /* */ +#define NV_REDUCTIONTSTATE_ERR_STATUS_0_CRUMBSTORE_BUF_OVERWRITE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_REDUCTIONTSTATE_ERR_STATUS_0_CRUMBSTORE_BUF_OVERWRITE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_LIMIT_ERR 18:18 /* RWDVF */ +#define NV_REDUCTIONTSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_REDUCTIONTSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_REDUCTIONTSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_DBE_ERR 19:19 /* RWDVF */ +#define NV_REDUCTIONTSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_REDUCTIONTSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_REDUCTIONTSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_STATUS_0_CRUMBSTORE_RTO_ERR 20:20 /* RWDVF */ +#define NV_REDUCTIONTSTATE_ERR_STATUS_0_CRUMBSTORE_RTO_ERR__ONWRITE "oneToClear" /* */ +#define NV_REDUCTIONTSTATE_ERR_STATUS_0_CRUMBSTORE_RTO_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_REDUCTIONTSTATE_ERR_STATUS_0_CRUMBSTORE_RTO_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0 0x00002c04 /* RW-4R */ +#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_LIMIT_ERR 2:2 /* RWEVF */ +#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_DBE_ERR 3:3 /* RWEVF */ +#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR 16:16 /* RWEVF */ +#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_LIMIT_ERR 18:18 /* RWEVF */ +#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_DBE_ERR 19:19 /* RWEVF */ +#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_CRUMBSTORE_RTO_ERR 20:20 /* RWEVF */ +#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_CRUMBSTORE_RTO_ERR__PROD 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_CRUMBSTORE_RTO_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_ERR_LOG_EN_0_CRUMBSTORE_RTO_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0 0x00002c08 /* RW-4R */ +#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR 2:2 /* RWEVF */ +#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR 3:3 /* RWEVF */ +#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR 16:16 /* RWEVF */ +#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR 18:18 /* RWEVF */ +#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR 19:19 /* RWEVF */ +#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_RTO_ERR 20:20 /* RWEVF */ +#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_RTO_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_RTO_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0 0x00002c0c /* RW-4R */ +#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR 2:2 /* RWEVF */ +#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR 3:3 /* RWEVF */ +#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR 16:16 /* RWEVF */ +#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR 18:18 /* RWEVF */ +#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR 19:19 /* RWEVF */ +#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_RTO_ERR 20:20 /* RWEVF */ +#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_RTO_ERR__PROD 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_RTO_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_RTO_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_CORRECTABLE_REPORT_EN_0 0x00002c10 /* RW-4R */ +#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0 0x00002c14 /* RW-4R */ +#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_LIMIT_ERR 2:2 /* RWEVF */ +#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_DBE_ERR 3:3 /* RWEVF */ +#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR 16:16 /* RWEVF */ +#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_BUF_OVERWRITE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_LIMIT_ERR 18:18 /* RWEVF */ +#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_DBE_ERR 19:19 /* RWEVF */ +#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_RTO_ERR 20:20 /* RWEVF */ +#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_RTO_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_RTO_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_FIRST_0 0x00002c1c /* RW-4R */ +#define NV_REDUCTIONTSTATE_ERR_FIRST_0_TAGPOOL_ECC_LIMIT_ERR 2:2 /* RWDVF */ +#define NV_REDUCTIONTSTATE_ERR_FIRST_0_TAGPOOL_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_REDUCTIONTSTATE_ERR_FIRST_0_TAGPOOL_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_REDUCTIONTSTATE_ERR_FIRST_0_TAGPOOL_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_FIRST_0_TAGPOOL_ECC_DBE_ERR 3:3 /* RWDVF */ +#define NV_REDUCTIONTSTATE_ERR_FIRST_0_TAGPOOL_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_REDUCTIONTSTATE_ERR_FIRST_0_TAGPOOL_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_REDUCTIONTSTATE_ERR_FIRST_0_TAGPOOL_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_FIRST_0_CRUMBSTORE_BUF_OVERWRITE_ERR 16:16 /* RWDVF */ +#define NV_REDUCTIONTSTATE_ERR_FIRST_0_CRUMBSTORE_BUF_OVERWRITE_ERR__ONWRITE "oneToClear" /* */ +#define NV_REDUCTIONTSTATE_ERR_FIRST_0_CRUMBSTORE_BUF_OVERWRITE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_REDUCTIONTSTATE_ERR_FIRST_0_CRUMBSTORE_BUF_OVERWRITE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_LIMIT_ERR 18:18 /* RWDVF */ +#define NV_REDUCTIONTSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_REDUCTIONTSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_REDUCTIONTSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_DBE_ERR 19:19 /* RWDVF */ +#define NV_REDUCTIONTSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_REDUCTIONTSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_REDUCTIONTSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_FIRST_0_CRUMBSTORE_RTO_ERR 20:20 /* RWDVF */ +#define NV_REDUCTIONTSTATE_ERR_FIRST_0_CRUMBSTORE_RTO_ERR__ONWRITE "oneToClear" /* */ +#define NV_REDUCTIONTSTATE_ERR_FIRST_0_CRUMBSTORE_RTO_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_REDUCTIONTSTATE_ERR_FIRST_0_CRUMBSTORE_RTO_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_TIMESTAMP_LOG 0x00002c50 /* R--4R */ +#define NV_REDUCTIONTSTATE_ERR_TIMESTAMP_LOG_TIMESTAMP 23:0 /* R-DVF */ +#define NV_REDUCTIONTSTATE_ERR_TIMESTAMP_LOG_TIMESTAMP_INIT 0x00000000 /* R-D-V */ +#define NV_REDUCTIONTSTATE_ERR_ECC_CTRL 0x00002d00 /* RW-4R */ +#define NV_REDUCTIONTSTATE_ERR_ECC_CTRL_TAGPOOL_ECC_ENABLE 0:0 /* RWEVF */ +#define NV_REDUCTIONTSTATE_ERR_ECC_CTRL_TAGPOOL_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_ECC_CTRL_TAGPOOL_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_ERR_ECC_CTRL_TAGPOOL_ECC_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_ECC_CTRL_CRUMBSTORE_ECC_ENABLE 1:1 /* RWEVF */ +#define NV_REDUCTIONTSTATE_ERR_ECC_CTRL_CRUMBSTORE_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_ECC_CTRL_CRUMBSTORE_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_ERR_ECC_CTRL_CRUMBSTORE_ECC_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER 0x00002d20 /* RW-4R */ +#define NV_REDUCTIONTSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */ +#define NV_REDUCTIONTSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */ +#define NV_REDUCTIONTSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER_LIMIT 0x00002d40 /* RW-4R */ +#define NV_REDUCTIONTSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */ +#define NV_REDUCTIONTSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */ +#define NV_REDUCTIONTSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS 0x00002d60 /* R--4R */ +#define NV_REDUCTIONTSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_ERROR_ADDRESS 7:0 /* R-DVF */ +#define NV_REDUCTIONTSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */ +#define NV_REDUCTIONTSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_VALID 0x00002d80 /* R--4R */ +#define NV_REDUCTIONTSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */ +#define NV_REDUCTIONTSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */ +#define NV_REDUCTIONTSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */ +#define NV_REDUCTIONTSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER 0x00002e00 /* RW-4R */ +#define NV_REDUCTIONTSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */ +#define NV_REDUCTIONTSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */ +#define NV_REDUCTIONTSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT 0x00002e20 /* RW-4R */ +#define NV_REDUCTIONTSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */ +#define NV_REDUCTIONTSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */ +#define NV_REDUCTIONTSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS 0x00002e40 /* R--4R */ +#define NV_REDUCTIONTSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_ERROR_ADDRESS 7:0 /* R-DVF */ +#define NV_REDUCTIONTSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */ +#define NV_REDUCTIONTSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID 0x00002e60 /* R--4R */ +#define NV_REDUCTIONTSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */ +#define NV_REDUCTIONTSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */ +#define NV_REDUCTIONTSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */ +#define NV_REDUCTIONTSTATE_STAT_STALL_BUSY_CONTROL 0x00002f00 /* RW-4R */ +#define NV_REDUCTIONTSTATE_STAT_STALL_BUSY_CONTROL_ENABLE_TIMER 0:0 /* RWEVF */ +#define NV_REDUCTIONTSTATE_STAT_STALL_BUSY_CONTROL_ENABLE_TIMER_DISABLE 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_STAT_STALL_BUSY_CONTROL_ENABLE_TIMER_ENABLE 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_STAT_STALL_BUSY_CONTROL_SNAP_ON_DEMAND 1:1 /* RWEVF */ +#define NV_REDUCTIONTSTATE_STAT_STALL_BUSY_CONTROL_SNAP_ON_DEMAND__ONWRITE "oneToSet" /* */ +#define NV_REDUCTIONTSTATE_STAT_STALL_BUSY_CONTROL_SNAP_ON_DEMAND_DISABLE 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_STAT_STALL_BUSY_CONTROL_SNAP_ON_DEMAND_ENABLE 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_STAT_WINDOW_0_HIGH 0x00002f04 /* RW-4R */ +#define NV_REDUCTIONTSTATE_STAT_WINDOW_0_HIGH_VALUE 15:0 /* RWEVF */ +#define NV_REDUCTIONTSTATE_STAT_WINDOW_0_HIGH_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_STAT_WINDOW_0_LOW 0x00002f08 /* RW-4R */ +#define NV_REDUCTIONTSTATE_STAT_WINDOW_0_LOW_VALUE 31:0 /* RWEVF */ +#define NV_REDUCTIONTSTATE_STAT_WINDOW_0_LOW_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_STAT_BUSY_TIMER_0_HIGH 0x00002f0c /* RW-4R */ +#define NV_REDUCTIONTSTATE_STAT_BUSY_TIMER_0_HIGH_VALUE 15:0 /* RWEVF */ +#define NV_REDUCTIONTSTATE_STAT_BUSY_TIMER_0_HIGH_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_STAT_BUSY_TIMER_0_LOW 0x00002f10 /* RW-4R */ +#define NV_REDUCTIONTSTATE_STAT_BUSY_TIMER_0_LOW_VALUE 31:0 /* RWEVF */ +#define NV_REDUCTIONTSTATE_STAT_BUSY_TIMER_0_LOW_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_STAT_STALL_TIMER_0_HIGH 0x00002f14 /* RW-4R */ +#define NV_REDUCTIONTSTATE_STAT_STALL_TIMER_0_HIGH_VALUE 15:0 /* RWEVF */ +#define NV_REDUCTIONTSTATE_STAT_STALL_TIMER_0_HIGH_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_STAT_STALL_TIMER_0_LOW 0x00002f18 /* RW-4R */ +#define NV_REDUCTIONTSTATE_STAT_STALL_TIMER_0_LOW_VALUE 31:0 /* RWEVF */ +#define NV_REDUCTIONTSTATE_STAT_STALL_TIMER_0_LOW_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_STAT_WINDOW_1_HIGH 0x00002f1c /* RW-4R */ +#define NV_REDUCTIONTSTATE_STAT_WINDOW_1_HIGH_VALUE 15:0 /* RWEVF */ +#define NV_REDUCTIONTSTATE_STAT_WINDOW_1_HIGH_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_STAT_WINDOW_1_LOW 0x00002f20 /* RW-4R */ +#define NV_REDUCTIONTSTATE_STAT_WINDOW_1_LOW_VALUE 31:0 /* RWEVF */ +#define NV_REDUCTIONTSTATE_STAT_WINDOW_1_LOW_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_STAT_BUSY_TIMER_1_HIGH 0x00002f24 /* RW-4R */ +#define NV_REDUCTIONTSTATE_STAT_BUSY_TIMER_1_HIGH_VALUE 15:0 /* RWEVF */ +#define NV_REDUCTIONTSTATE_STAT_BUSY_TIMER_1_HIGH_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_STAT_BUSY_TIMER_1_LOW 0x00002f28 /* RW-4R */ +#define NV_REDUCTIONTSTATE_STAT_BUSY_TIMER_1_LOW_VALUE 31:0 /* RWEVF */ +#define NV_REDUCTIONTSTATE_STAT_BUSY_TIMER_1_LOW_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_STAT_STALL_TIMER_1_HIGH 0x00002f2c /* RW-4R */ +#define NV_REDUCTIONTSTATE_STAT_STALL_TIMER_1_HIGH_VALUE 15:0 /* RWEVF */ +#define NV_REDUCTIONTSTATE_STAT_STALL_TIMER_1_HIGH_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_STAT_STALL_TIMER_1_LOW 0x00002f30 /* RW-4R */ +#define NV_REDUCTIONTSTATE_STAT_STALL_TIMER_1_LOW_VALUE 31:0 /* RWEVF */ +#define NV_REDUCTIONTSTATE_STAT_STALL_TIMER_1_LOW_VALUE_INIT 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_CONTROL 0x00002f34 /* RW-4R */ +#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_CONTROL_ENABLE_TIMER 0:0 /* RWEVF */ +#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_CONTROL_ENABLE_TIMER_DISABLE 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_CONTROL_ENABLE_TIMER_ENABLE 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_CONTROL_SNAP_ON_DEMAND 1:1 /* RWEVF */ +#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_CONTROL_SNAP_ON_DEMAND__ONWRITE "oneToSet" /* */ +#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_CONTROL_SNAP_ON_DEMAND_DISABLE 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_CONTROL_SNAP_ON_DEMAND_ENABLE 0x00000001 /* RW--V */ +#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_BIN_CTRL_LOW 0x00002f38 /* RW-4R */ +#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_BIN_CTRL_LOW_LIMIT 23:0 /* RWEVF */ +#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_BIN_CTRL_LOW_LIMIT_INIT 0x0028b0ab /* RWE-V */ +#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_BIN_CTRL_HIGH 0x00002f3c /* RW-4R */ +#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_BIN_CTRL_HIGH_LIMIT 23:0 /* RWEVF */ +#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_BIN_CTRL_HIGH_LIMIT_INIT 0x00cb7355 /* RWE-V */ +#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_CTRL 0x00002f40 /* RW-4R */ +#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX 9:0 /* RWEVF */ +#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_MIN 0x00000000 /* RWE-V */ +#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_MAX 0x000002ff /* RW--V */ +#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_MCID_STRIDE 0x00000006 /* */ +#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_BIN_LOW_31_0 0x00000000 /* */ +#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_BIN_LOW_47_32 0x00000001 /* */ +#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_BIN_MED_31_0 0x00000002 /* */ +#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_BIN_MED_47_32 0x00000003 /* */ +#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_BIN_HIGH_31_0 0x00000004 /* */ +#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_BIN_HIGH_47_32 0x00000005 /* */ +#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_CTRL_AUTOINCR 10:10 /* RWEVF */ +#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_CTRL_AUTOINCR_OFF 0x00000000 /* RW--V */ +#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_CTRL_AUTOINCR_ON 0x00000001 /* RWE-V */ +#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_DATA 0x00002f44 /* R--4R */ +#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_DATA_COUNT 31:0 /* R-XVF */ +#define NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_DATA__APERTURE_INDEX_OFFSET -0x00000004 /* */ +#endif // __ls10_dev_reductiontstate_ip_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_riscv_pri.h b/src/common/inc/swref/published/nvswitch/ls10/dev_riscv_pri.h new file mode 100644 index 000000000..59a5d37bc --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_riscv_pri.h @@ -0,0 +1,84 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_riscv_pri_h__ +#define __ls10_dev_riscv_pri_h__ +/* This file is autogenerated. Do not edit */ +#define NV_FALCON2_SOE_BASE 0x00841000 +#define NV_PRISCV_RISCV_IRQMASK 0x00000528 /* R--4R */ +#define NV_PRISCV_RISCV_IRQDEST 0x0000052c /* RW-4R */ +#define NV_PRISCV_RISCV_IRQDELEG 0x00000534 /* RW-4R */ +#define NV_PRISCV_RISCV_CPUCTL 0x00000388 /* RW-4R */ +#define NV_PRISCV_RISCV_RPC 0x000003ec /* R--4R */ +#define NV_PRISCV_RISCV_TRACECTL 0x00000400 /* RW-4R */ +#define NV_PRISCV_RISCV_TRACECTL_LOW_THSHD 7:0 /* RWIVF */ +#define NV_PRISCV_RISCV_TRACECTL_LOW_THSHD_INIT 0x00000000 /* RWI-V */ +#define NV_PRISCV_RISCV_TRACECTL_HIGH_THSHD 15:8 /* RWIVF */ +#define NV_PRISCV_RISCV_TRACECTL_HIGH_THSHD_INIT 0x000000ff /* RWI-V */ +#define NV_PRISCV_RISCV_TRACECTL_UMODE_ENABLE 20:20 /* RWIVF */ +#define NV_PRISCV_RISCV_TRACECTL_UMODE_ENABLE_FALSE 0x00000000 /* RWI-V */ +#define NV_PRISCV_RISCV_TRACECTL_UMODE_ENABLE_TRUE 0x00000001 /* RW--V */ +#define NV_PRISCV_RISCV_TRACECTL_SMODE_ENABLE 21:21 /* RWIVF */ +#define NV_PRISCV_RISCV_TRACECTL_SMODE_ENABLE_FALSE 0x00000000 /* RWI-V */ +#define NV_PRISCV_RISCV_TRACECTL_SMODE_ENABLE_TRUE 0x00000001 /* RW--V */ +#define NV_PRISCV_RISCV_TRACECTL_MMODE_ENABLE 23:23 /* RWIVF */ +#define NV_PRISCV_RISCV_TRACECTL_MMODE_ENABLE_FALSE 0x00000000 /* RWI-V */ +#define NV_PRISCV_RISCV_TRACECTL_MMODE_ENABLE_TRUE 0x00000001 /* RW--V */ +#define NV_PRISCV_RISCV_TRACECTL_MODE 25:24 /* RWIVF */ +#define NV_PRISCV_RISCV_TRACECTL_MODE_FULL 0x00000000 /* RWI-V */ +#define NV_PRISCV_RISCV_TRACECTL_MODE_REDUCED 0x00000001 /* RW--V */ +#define NV_PRISCV_RISCV_TRACECTL_MODE_STACK 0x00000002 /* RW--V */ +#define NV_PRISCV_RISCV_TRACECTL_BELOW_LO 27:27 /* RWIVF */ +#define NV_PRISCV_RISCV_TRACECTL_BELOW_LO_INIT 0x00000000 /* RWI-V */ +#define NV_PRISCV_RISCV_TRACECTL_ABOVE_HI 28:28 /* RWIVF */ +#define NV_PRISCV_RISCV_TRACECTL_ABOVE_HI_INIT 0x00000000 /* RWI-V */ +#define NV_PRISCV_RISCV_TRACECTL_INTR_ENABLE 29:29 /* R-IVF */ +#define NV_PRISCV_RISCV_TRACECTL_INTR_ENABLE_FALSE 0x00000000 /* R-I-V */ +#define NV_PRISCV_RISCV_TRACECTL_INTR_ENABLE_TRUE 0x00000001 /* R---V */ +#define NV_PRISCV_RISCV_TRACECTL_FULL 30:30 /* RWIVF */ +#define NV_PRISCV_RISCV_TRACECTL_FULL_INIT 0x00000000 /* RWI-V */ +#define NV_PRISCV_RISCV_TRACECTL_EMPTY 31:31 /* RWIVF */ +#define NV_PRISCV_RISCV_TRACECTL_EMPTY_INIT 0x00000000 /* RWI-V */ +#define NV_PRISCV_RISCV_TRACE_RDIDX 0x00000404 /* RW-4R */ +#define NV_PRISCV_RISCV_TRACE_RDIDX_RDIDX 7:0 /* RWIVF */ +#define NV_PRISCV_RISCV_TRACE_RDIDX_RDIDX_INIT 0x00000000 /* RWI-V */ +#define NV_PRISCV_RISCV_TRACE_RDIDX_RSVD0 15:8 /* R-IVF */ +#define NV_PRISCV_RISCV_TRACE_RDIDX_RSVD0_INIT 0x00000000 /* R-I-V */ +#define NV_PRISCV_RISCV_TRACE_RDIDX_MAXIDX 23:16 /* R-IVF */ +#define NV_PRISCV_RISCV_TRACE_RDIDX_MAXIDX_INIT 0x0000003f /* R-I-V */ +#define NV_PRISCV_RISCV_TRACE_RDIDX_RSVD1 31:24 /* R-IVF */ +#define NV_PRISCV_RISCV_TRACE_RDIDX_RSVD1_INIT 0x00000000 /* R-I-V */ +#define NV_PRISCV_RISCV_TRACE_WTIDX 0x00000408 /* RW-4R */ +#define NV_PRISCV_RISCV_TRACE_WTIDX_WTIDX 31:24 /* RWIVF */ +#define NV_PRISCV_RISCV_TRACE_WTIDX_WTIDX_INIT 0x00000000 /* RWI-V */ +#define NV_PRISCV_RISCV_TRACE_WTIDX_RSVD1 23:0 /* R-IVF */ +#define NV_PRISCV_RISCV_TRACE_WTIDX_RSVD1_INIT 0x00000000 /* R-I-V */ +#define NV_PRISCV_RISCV_TRACEPC_HI 0x00000410 /* RW-4R */ +#define NV_PRISCV_RISCV_TRACEPC_LO 0x0000040c /* RW-4R */ +#define NV_PRISCV_RISCV_PRIV_ERR_STAT 0x00000500 /* RW-4R */ +#define NV_PRISCV_RISCV_PRIV_ERR_INFO 0x00000504 /* R--4R */ +#define NV_PRISCV_RISCV_PRIV_ERR_ADDR 0x00000508 /* R--4R */ +#define NV_PRISCV_RISCV_PRIV_ERR_ADDR_HI 0x0000050c /* R--4R */ +#define NV_PRISCV_RISCV_HUB_ERR_STAT 0x00000510 /* RW-4R */ +#define NV_PRISCV_RISCV_BCR_CTRL 0x00000668 /* RW-4R */ +#endif // __ls10_dev_riscv_pri_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_route_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_route_ip.h new file mode 100644 index 000000000..ce6266615 --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_route_ip.h @@ -0,0 +1,804 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_route_ip_h__ +#define __ls10_dev_route_ip_h__ +/* This file is autogenerated. Do not edit */ +#define NV_ROUTE 0x00005fff:0x00005000 /* RW--D */ +#define NV_ROUTE_REG_TABLE_ADDRESS 0x00005080 /* RW-4R */ +#define NV_ROUTE_REG_TABLE_ADDRESS_INDEX 7:0 /* RWEVF */ +#define NV_ROUTE_REG_TABLE_ADDRESS_INDEX_MIN 0x00000000 /* RWE-V */ +#define NV_ROUTE_REG_TABLE_ADDRESS_INDEX_GLTAB_DEPTH 0x000000ff /* RW--V */ +#define NV_ROUTE_REG_TABLE_ADDRESS_AUTO_INCR 31:31 /* RWEVF */ +#define NV_ROUTE_REG_TABLE_ADDRESS_AUTO_INCR_DISABLE 0x00000000 /* RW--V */ +#define NV_ROUTE_REG_TABLE_ADDRESS_AUTO_INCR_ENABLE 0x00000001 /* RWE-V */ +#define NV_ROUTE_REG_TABLE_DATA0 0x00005090 /* RW-4R */ +#define NV_ROUTE_REG_TABLE_DATA0_GLX_0 3:0 /* RWEVF */ +#define NV_ROUTE_REG_TABLE_DATA0_GLX_0_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_REG_TABLE_DATA0_GLX_1 7:4 /* RWEVF */ +#define NV_ROUTE_REG_TABLE_DATA0_GLX_1_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_REG_TABLE_DATA0_GLX_2 11:8 /* RWEVF */ +#define NV_ROUTE_REG_TABLE_DATA0_GLX_2_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_REG_TABLE_DATA0_GLX_3 15:12 /* RWEVF */ +#define NV_ROUTE_REG_TABLE_DATA0_GLX_3_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_REG_TABLE_DATA0_GLX_4 19:16 /* RWEVF */ +#define NV_ROUTE_REG_TABLE_DATA0_GLX_4_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_REG_TABLE_DATA0_GLX_5 23:20 /* RWEVF */ +#define NV_ROUTE_REG_TABLE_DATA0_GLX_5_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_REG_TABLE_DATA0_GLX_6 27:24 /* RWEVF */ +#define NV_ROUTE_REG_TABLE_DATA0_GLX_6_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_REG_TABLE_DATA0_GLX_7 31:28 /* RWEVF */ +#define NV_ROUTE_REG_TABLE_DATA0_GLX_7_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_REG_TABLE_DATA1 0x00005094 /* RW-4R */ +#define NV_ROUTE_REG_TABLE_DATA1_GLX_8 3:0 /* RWEVF */ +#define NV_ROUTE_REG_TABLE_DATA1_GLX_8_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_REG_TABLE_DATA1_GLX_9 7:4 /* RWEVF */ +#define NV_ROUTE_REG_TABLE_DATA1_GLX_9_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_REG_TABLE_DATA1_GLX_10 11:8 /* RWEVF */ +#define NV_ROUTE_REG_TABLE_DATA1_GLX_10_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_REG_TABLE_DATA1_GLX_11 15:12 /* RWEVF */ +#define NV_ROUTE_REG_TABLE_DATA1_GLX_11_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_REG_TABLE_DATA1_GLX_12 19:16 /* RWEVF */ +#define NV_ROUTE_REG_TABLE_DATA1_GLX_12_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_REG_TABLE_DATA1_GLX_13 23:20 /* RWEVF */ +#define NV_ROUTE_REG_TABLE_DATA1_GLX_13_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_REG_TABLE_DATA1_GLX_14 27:24 /* RWEVF */ +#define NV_ROUTE_REG_TABLE_DATA1_GLX_14_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_REG_TABLE_DATA1_GLX_15 31:28 /* RWEVF */ +#define NV_ROUTE_REG_TABLE_DATA1_GLX_15_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_REG_TABLE_DATA2 0x00005098 /* R--4R */ +#define NV_ROUTE_REG_TABLE_DATA2_ECC 7:0 /* R-EVF */ +#define NV_ROUTE_REG_TABLE_DATA2_ECC_INIT 0x00000000 /* R-E-V */ +#define NV_ROUTE_CMD_ROUTE_TABLE0 0x000050a0 /* RW-4R */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN0 1:0 /* RWEVF */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN0_SPRAY 0x00000000 /* RWE-V */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN0_RESERVED 0x00000001 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN0_RANDOM 0x00000002 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN0_ALTERNATE 0x00000003 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN1 5:4 /* RWEVF */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN1_SPRAY 0x00000000 /* RWE-V */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN1_RESERVED 0x00000001 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN1_RANDOM 0x00000002 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN1_ALTERNATE 0x00000003 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN2 9:8 /* RWEVF */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN2_SPRAY 0x00000000 /* RWE-V */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN2_RESERVED 0x00000001 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN2_RANDOM 0x00000002 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN2_ALTERNATE 0x00000003 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN3 13:12 /* RWEVF */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN3_SPRAY 0x00000000 /* RWE-V */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN3_RESERVED 0x00000001 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN3_RANDOM 0x00000002 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN3_ALTERNATE 0x00000003 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN4 17:16 /* RWEVF */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN4_SPRAY 0x00000000 /* RWE-V */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN4_RESERVED 0x00000001 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN4_RANDOM 0x00000002 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN4_ALTERNATE 0x00000003 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN5 21:20 /* RWEVF */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN5_SPRAY 0x00000000 /* RWE-V */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN5_RESERVED 0x00000001 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN5_RANDOM 0x00000002 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN5_ALTERNATE 0x00000003 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN6 25:24 /* RWEVF */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN6_SPRAY 0x00000000 /* RWE-V */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN6_RESERVED 0x00000001 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN6_RANDOM 0x00000002 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN6_ALTERNATE 0x00000003 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN7 29:28 /* RWEVF */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN7_SPRAY 0x00000000 /* RWE-V */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN7_RESERVED 0x00000001 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN7_RANDOM 0x00000002 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN7_ALTERNATE 0x00000003 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE1 0x000050a4 /* RW-4R */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN8 1:0 /* RWEVF */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN8_SPRAY 0x00000000 /* RWE-V */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN8_RESERVED 0x00000001 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN8_RANDOM 0x00000002 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN8_ALTERNATE 0x00000003 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN9 5:4 /* RWEVF */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN9_SPRAY 0x00000000 /* RWE-V */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN9_RESERVED 0x00000001 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN9_RANDOM 0x00000002 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN9_ALTERNATE 0x00000003 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN10 9:8 /* RWEVF */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN10_SPRAY 0x00000000 /* RWE-V */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN10_RESERVED 0x00000001 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN10_RANDOM 0x00000002 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN10_ALTERNATE 0x00000003 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN11 13:12 /* RWEVF */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN11_SPRAY 0x00000000 /* RWE-V */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN11_RESERVED 0x00000001 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN11_RANDOM 0x00000002 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN11_ALTERNATE 0x00000003 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN12 17:16 /* RWEVF */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN12_SPRAY 0x00000000 /* RWE-V */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN12_RESERVED 0x00000001 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN12_RANDOM 0x00000002 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN12_ALTERNATE 0x00000003 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN13 21:20 /* RWEVF */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN13_SPRAY 0x00000000 /* RWE-V */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN13_RESERVED 0x00000001 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN13_RANDOM 0x00000002 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN13_ALTERNATE 0x00000003 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN14 25:24 /* RWEVF */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN14_SPRAY 0x00000000 /* RWE-V */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN14_RESERVED 0x00000001 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN14_RANDOM 0x00000002 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN14_ALTERNATE 0x00000003 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN15 29:28 /* RWEVF */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN15_SPRAY 0x00000000 /* RWE-V */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN15_RESERVED 0x00000001 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN15_RANDOM 0x00000002 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN15_ALTERNATE 0x00000003 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE2 0x000050a8 /* RW-4R */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN16 1:0 /* RWEVF */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN16_SPRAY 0x00000000 /* RWE-V */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN16_RESERVED 0x00000001 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN16_RANDOM 0x00000002 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN16_ALTERNATE 0x00000003 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN17 5:4 /* RWEVF */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN17_SPRAY 0x00000000 /* RWE-V */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN17_RESERVED 0x00000001 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN17_RANDOM 0x00000002 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN17_ALTERNATE 0x00000003 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN18 9:8 /* RWEVF */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN18_SPRAY 0x00000000 /* RWE-V */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN18_RESERVED 0x00000001 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN18_RANDOM 0x00000002 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN18_ALTERNATE 0x00000003 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN19 13:12 /* RWEVF */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN19_SPRAY 0x00000000 /* RWE-V */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN19_RESERVED 0x00000001 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN19_RANDOM 0x00000002 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN19_ALTERNATE 0x00000003 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN20 17:16 /* RWEVF */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN20_SPRAY 0x00000000 /* RWE-V */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN20_RESERVED 0x00000001 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN20_RANDOM 0x00000002 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN20_ALTERNATE 0x00000003 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN21 21:20 /* RWEVF */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN21_SPRAY 0x00000000 /* RWE-V */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN21_RESERVED 0x00000001 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN21_RANDOM 0x00000002 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN21_ALTERNATE 0x00000003 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN22 25:24 /* RWEVF */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN22_SPRAY 0x00000000 /* RWE-V */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN22_RESERVED 0x00000001 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN22_RANDOM 0x00000002 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN22_ALTERNATE 0x00000003 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN23 29:28 /* RWEVF */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN23_SPRAY 0x00000000 /* RWE-V */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN23_RESERVED 0x00000001 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN23_RANDOM 0x00000002 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN23_ALTERNATE 0x00000003 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE3 0x000050ac /* RW-4R */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN24 1:0 /* RWEVF */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN24_SPRAY 0x00000000 /* RWE-V */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN24_RESERVED 0x00000001 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN24_RANDOM 0x00000002 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN24_ALTERNATE 0x00000003 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN25 5:4 /* RWEVF */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN25_SPRAY 0x00000000 /* RWE-V */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN25_RESERVED 0x00000001 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN25_RANDOM 0x00000002 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN25_ALTERNATE 0x00000003 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN26 9:8 /* RWEVF */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN26_SPRAY 0x00000000 /* RWE-V */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN26_RESERVED 0x00000001 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN26_RANDOM 0x00000002 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN26_ALTERNATE 0x00000003 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN27 13:12 /* RWEVF */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN27_SPRAY 0x00000000 /* RWE-V */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN27_RESERVED 0x00000001 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN27_RANDOM 0x00000002 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN27_ALTERNATE 0x00000003 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN28 17:16 /* RWEVF */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN28_SPRAY 0x00000000 /* RWE-V */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN28_RESERVED 0x00000001 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN28_RANDOM 0x00000002 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN28_ALTERNATE 0x00000003 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN29 21:20 /* RWEVF */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN29_SPRAY 0x00000000 /* RWE-V */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN29_RESERVED 0x00000001 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN29_RANDOM 0x00000002 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN29_ALTERNATE 0x00000003 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN30 25:24 /* RWEVF */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN30_SPRAY 0x00000000 /* RWE-V */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN30_RESERVED 0x00000001 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN30_RANDOM 0x00000002 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN30_ALTERNATE 0x00000003 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN31 29:28 /* RWEVF */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN31_SPRAY 0x00000000 /* RWE-V */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN31_RESERVED 0x00000001 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN31_RANDOM 0x00000002 /* RW--V */ +#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN31_ALTERNATE 0x00000003 /* RW--V */ +#define NV_ROUTE_ERR_STATUS_0 0x00005400 /* RW-4R */ +#define NV_ROUTE_ERR_STATUS_0_ROUTEBUFERR 0:0 /* RWDVF */ +#define NV_ROUTE_ERR_STATUS_0_ROUTEBUFERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_STATUS_0_ROUTEBUFERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_STATUS_0_ROUTEBUFERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_STATUS_0_NOPORTDEFINEDERR 1:1 /* RWDVF */ +#define NV_ROUTE_ERR_STATUS_0_NOPORTDEFINEDERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_STATUS_0_NOPORTDEFINEDERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_STATUS_0_NOPORTDEFINEDERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_STATUS_0_INVALIDROUTEPOLICYERR 2:2 /* RWDVF */ +#define NV_ROUTE_ERR_STATUS_0_INVALIDROUTEPOLICYERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_STATUS_0_INVALIDROUTEPOLICYERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_STATUS_0_INVALIDROUTEPOLICYERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_STATUS_0_GLT_ECC_LIMIT_ERR 3:3 /* RWDVF */ +#define NV_ROUTE_ERR_STATUS_0_GLT_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_STATUS_0_GLT_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_STATUS_0_GLT_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_STATUS_0_GLT_ECC_DBE_ERR 4:4 /* RWDVF */ +#define NV_ROUTE_ERR_STATUS_0_GLT_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_STATUS_0_GLT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_STATUS_0_GLT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_STATUS_0_PDCTRLPARERR 6:6 /* RWDVF */ +#define NV_ROUTE_ERR_STATUS_0_PDCTRLPARERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_STATUS_0_PDCTRLPARERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_STATUS_0_PDCTRLPARERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_STATUS_0_NVS_ECC_LIMIT_ERR 7:7 /* RWDVF */ +#define NV_ROUTE_ERR_STATUS_0_NVS_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_STATUS_0_NVS_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_STATUS_0_NVS_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_STATUS_0_NVS_ECC_DBE_ERR 8:8 /* RWDVF */ +#define NV_ROUTE_ERR_STATUS_0_NVS_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_STATUS_0_NVS_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_STATUS_0_NVS_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_STATUS_0_CDTPARERR 9:9 /* RWDVF */ +#define NV_ROUTE_ERR_STATUS_0_CDTPARERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_STATUS_0_CDTPARERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_STATUS_0_CDTPARERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_STATUS_0_MCRID_ECC_LIMIT_ERR 10:10 /* RWDVF */ +#define NV_ROUTE_ERR_STATUS_0_MCRID_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_STATUS_0_MCRID_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_STATUS_0_MCRID_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_STATUS_0_MCRID_ECC_DBE_ERR 11:11 /* RWDVF */ +#define NV_ROUTE_ERR_STATUS_0_MCRID_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_STATUS_0_MCRID_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_STATUS_0_MCRID_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_STATUS_0_EXTMCRID_ECC_LIMIT_ERR 12:12 /* RWDVF */ +#define NV_ROUTE_ERR_STATUS_0_EXTMCRID_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_STATUS_0_EXTMCRID_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_STATUS_0_EXTMCRID_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_STATUS_0_EXTMCRID_ECC_DBE_ERR 13:13 /* RWDVF */ +#define NV_ROUTE_ERR_STATUS_0_EXTMCRID_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_STATUS_0_EXTMCRID_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_STATUS_0_EXTMCRID_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_STATUS_0_RAM_ECC_LIMIT_ERR 14:14 /* RWDVF */ +#define NV_ROUTE_ERR_STATUS_0_RAM_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_STATUS_0_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_STATUS_0_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_STATUS_0_RAM_ECC_DBE_ERR 15:15 /* RWDVF */ +#define NV_ROUTE_ERR_STATUS_0_RAM_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_STATUS_0_RAM_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_STATUS_0_RAM_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_STATUS_0_INVALID_MCRID_ERR 16:16 /* RWDVF */ +#define NV_ROUTE_ERR_STATUS_0_INVALID_MCRID_ERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_STATUS_0_INVALID_MCRID_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_STATUS_0_INVALID_MCRID_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_STATUS_0_MC_TRIGGER_ERR 17:17 /* RWDVF */ +#define NV_ROUTE_ERR_STATUS_0_MC_TRIGGER_ERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_STATUS_0_MC_TRIGGER_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_STATUS_0_MC_TRIGGER_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_LOG_EN_0 0x00005404 /* RW-4R */ +#define NV_ROUTE_ERR_LOG_EN_0_ROUTEBUFERR 0:0 /* RWEVF */ +#define NV_ROUTE_ERR_LOG_EN_0_ROUTEBUFERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_LOG_EN_0_ROUTEBUFERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_LOG_EN_0_ROUTEBUFERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_LOG_EN_0_NOPORTDEFINEDERR 1:1 /* RWEVF */ +#define NV_ROUTE_ERR_LOG_EN_0_NOPORTDEFINEDERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_LOG_EN_0_NOPORTDEFINEDERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_LOG_EN_0_NOPORTDEFINEDERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_LOG_EN_0_INVALIDROUTEPOLICYERR 2:2 /* RWEVF */ +#define NV_ROUTE_ERR_LOG_EN_0_INVALIDROUTEPOLICYERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_LOG_EN_0_INVALIDROUTEPOLICYERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_LOG_EN_0_INVALIDROUTEPOLICYERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_LOG_EN_0_GLT_ECC_LIMIT_ERR 3:3 /* RWEVF */ +#define NV_ROUTE_ERR_LOG_EN_0_GLT_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_LOG_EN_0_GLT_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_LOG_EN_0_GLT_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_LOG_EN_0_GLT_ECC_DBE_ERR 4:4 /* RWEVF */ +#define NV_ROUTE_ERR_LOG_EN_0_GLT_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_LOG_EN_0_GLT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_LOG_EN_0_GLT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_LOG_EN_0_PDCTRLPARERR 6:6 /* RWEVF */ +#define NV_ROUTE_ERR_LOG_EN_0_PDCTRLPARERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_LOG_EN_0_PDCTRLPARERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_LOG_EN_0_PDCTRLPARERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_LOG_EN_0_NVS_ECC_LIMIT_ERR 7:7 /* RWEVF */ +#define NV_ROUTE_ERR_LOG_EN_0_NVS_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_LOG_EN_0_NVS_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_LOG_EN_0_NVS_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_LOG_EN_0_NVS_ECC_DBE_ERR 8:8 /* RWEVF */ +#define NV_ROUTE_ERR_LOG_EN_0_NVS_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_LOG_EN_0_NVS_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_LOG_EN_0_NVS_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_LOG_EN_0_CDTPARERR 9:9 /* RWEVF */ +#define NV_ROUTE_ERR_LOG_EN_0_CDTPARERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_LOG_EN_0_CDTPARERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_LOG_EN_0_CDTPARERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_LOG_EN_0_MCRID_ECC_LIMIT_ERR 10:10 /* RWEVF */ +#define NV_ROUTE_ERR_LOG_EN_0_MCRID_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_LOG_EN_0_MCRID_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_LOG_EN_0_MCRID_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_LOG_EN_0_MCRID_ECC_DBE_ERR 11:11 /* RWEVF */ +#define NV_ROUTE_ERR_LOG_EN_0_MCRID_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_LOG_EN_0_MCRID_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_LOG_EN_0_MCRID_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_LOG_EN_0_EXTMCRID_ECC_LIMIT_ERR 12:12 /* RWEVF */ +#define NV_ROUTE_ERR_LOG_EN_0_EXTMCRID_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_LOG_EN_0_EXTMCRID_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_LOG_EN_0_EXTMCRID_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_LOG_EN_0_EXTMCRID_ECC_DBE_ERR 13:13 /* RWEVF */ +#define NV_ROUTE_ERR_LOG_EN_0_EXTMCRID_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_LOG_EN_0_EXTMCRID_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_LOG_EN_0_EXTMCRID_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_LOG_EN_0_RAM_ECC_LIMIT_ERR 14:14 /* RWEVF */ +#define NV_ROUTE_ERR_LOG_EN_0_RAM_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_LOG_EN_0_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_LOG_EN_0_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_LOG_EN_0_RAM_ECC_DBE_ERR 15:15 /* RWEVF */ +#define NV_ROUTE_ERR_LOG_EN_0_RAM_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_LOG_EN_0_RAM_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_LOG_EN_0_RAM_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_LOG_EN_0_INVALID_MCRID_ERR 16:16 /* RWEVF */ +#define NV_ROUTE_ERR_LOG_EN_0_INVALID_MCRID_ERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_LOG_EN_0_INVALID_MCRID_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_LOG_EN_0_INVALID_MCRID_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_LOG_EN_0_MC_TRIGGER_ERR 17:17 /* RWEVF */ +#define NV_ROUTE_ERR_LOG_EN_0_MC_TRIGGER_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_LOG_EN_0_MC_TRIGGER_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0 0x00005408 /* RW-4R */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_ROUTEBUFERR 0:0 /* RWEVF */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_ROUTEBUFERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_ROUTEBUFERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_ROUTEBUFERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_NOPORTDEFINEDERR 1:1 /* RWEVF */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_NOPORTDEFINEDERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_NOPORTDEFINEDERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_INVALIDROUTEPOLICYERR 2:2 /* RWEVF */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_INVALIDROUTEPOLICYERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_INVALIDROUTEPOLICYERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_GLT_ECC_LIMIT_ERR 3:3 /* RWEVF */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_GLT_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_GLT_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_GLT_ECC_DBE_ERR 4:4 /* RWEVF */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_GLT_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_GLT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_GLT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_PDCTRLPARERR 6:6 /* RWEVF */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_PDCTRLPARERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_PDCTRLPARERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_PDCTRLPARERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_NVS_ECC_LIMIT_ERR 7:7 /* RWEVF */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_NVS_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_NVS_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_NVS_ECC_DBE_ERR 8:8 /* RWEVF */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_NVS_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_NVS_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_NVS_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_CDTPARERR 9:9 /* RWEVF */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_CDTPARERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_CDTPARERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_CDTPARERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_MCRID_ECC_LIMIT_ERR 10:10 /* RWEVF */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_MCRID_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_MCRID_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_MCRID_ECC_DBE_ERR 11:11 /* RWEVF */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_MCRID_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_MCRID_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_MCRID_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_EXTMCRID_ECC_LIMIT_ERR 12:12 /* RWEVF */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_EXTMCRID_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_EXTMCRID_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_EXTMCRID_ECC_DBE_ERR 13:13 /* RWEVF */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_EXTMCRID_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_EXTMCRID_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_EXTMCRID_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_RAM_ECC_LIMIT_ERR 14:14 /* RWEVF */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_RAM_ECC_DBE_ERR 15:15 /* RWEVF */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_RAM_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_RAM_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_RAM_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_INVALID_MCRID_ERR 16:16 /* RWEVF */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_INVALID_MCRID_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_INVALID_MCRID_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_MC_TRIGGER_ERR 17:17 /* RWEVF */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_MC_TRIGGER_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_MC_TRIGGER_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0 0x0000540c /* RW-4R */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_ROUTEBUFERR 0:0 /* RWEVF */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_ROUTEBUFERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_ROUTEBUFERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NOPORTDEFINEDERR 1:1 /* RWEVF */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NOPORTDEFINEDERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NOPORTDEFINEDERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NOPORTDEFINEDERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_INVALIDROUTEPOLICYERR 2:2 /* RWEVF */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_INVALIDROUTEPOLICYERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_INVALIDROUTEPOLICYERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_INVALIDROUTEPOLICYERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_GLT_ECC_LIMIT_ERR 3:3 /* RWEVF */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_GLT_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_GLT_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_GLT_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_GLT_ECC_DBE_ERR 4:4 /* RWEVF */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_GLT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_GLT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_PDCTRLPARERR 6:6 /* RWEVF */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_PDCTRLPARERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_PDCTRLPARERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NVS_ECC_LIMIT_ERR 7:7 /* RWEVF */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NVS_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NVS_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NVS_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NVS_ECC_DBE_ERR 8:8 /* RWEVF */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NVS_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NVS_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_CDTPARERR 9:9 /* RWEVF */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_CDTPARERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_CDTPARERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_MCRID_ECC_LIMIT_ERR 10:10 /* RWEVF */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_MCRID_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_MCRID_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_MCRID_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_MCRID_ECC_DBE_ERR 11:11 /* RWEVF */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_MCRID_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_MCRID_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_EXTMCRID_ECC_LIMIT_ERR 12:12 /* RWEVF */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_EXTMCRID_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_EXTMCRID_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_EXTMCRID_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_EXTMCRID_ECC_DBE_ERR 13:13 /* RWEVF */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_EXTMCRID_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_EXTMCRID_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_RAM_ECC_LIMIT_ERR 14:14 /* RWEVF */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_RAM_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_RAM_ECC_DBE_ERR 15:15 /* RWEVF */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_RAM_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_RAM_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_INVALID_MCRID_ERR 16:16 /* RWEVF */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_INVALID_MCRID_ERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_INVALID_MCRID_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_INVALID_MCRID_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_MC_TRIGGER_ERR 17:17 /* RWEVF */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_MC_TRIGGER_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_MC_TRIGGER_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0 0x00005410 /* RW-4R */ +#define NV_ROUTE_ERR_CONTAIN_EN_0 0x00005414 /* RW-4R */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_ROUTEBUFERR 0:0 /* RWEVF */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_ROUTEBUFERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_ROUTEBUFERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_ROUTEBUFERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_NOPORTDEFINEDERR 1:1 /* RWEVF */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_NOPORTDEFINEDERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_NOPORTDEFINEDERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_INVALIDROUTEPOLICYERR 2:2 /* RWEVF */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_INVALIDROUTEPOLICYERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_INVALIDROUTEPOLICYERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_GLT_ECC_LIMIT_ERR 3:3 /* RWEVF */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_GLT_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_GLT_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_GLT_ECC_DBE_ERR 4:4 /* RWEVF */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_GLT_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_GLT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_GLT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_PDCTRLPARERR 6:6 /* RWEVF */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_PDCTRLPARERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_PDCTRLPARERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_PDCTRLPARERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_NVS_ECC_LIMIT_ERR 7:7 /* RWEVF */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_NVS_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_NVS_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_NVS_ECC_DBE_ERR 8:8 /* RWEVF */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_NVS_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_NVS_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_NVS_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_CDTPARERR 9:9 /* RWEVF */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_CDTPARERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_CDTPARERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_CDTPARERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_MCRID_ECC_LIMIT_ERR 10:10 /* RWEVF */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_MCRID_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_MCRID_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_MCRID_ECC_DBE_ERR 11:11 /* RWEVF */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_MCRID_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_MCRID_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_MCRID_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_EXTMCRID_ECC_LIMIT_ERR 12:12 /* RWEVF */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_EXTMCRID_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_EXTMCRID_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_EXTMCRID_ECC_DBE_ERR 13:13 /* RWEVF */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_EXTMCRID_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_EXTMCRID_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_EXTMCRID_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_RAM_ECC_LIMIT_ERR 14:14 /* RWEVF */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_RAM_ECC_DBE_ERR 15:15 /* RWEVF */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_RAM_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_RAM_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_RAM_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_INVALID_MCRID_ERR 16:16 /* RWEVF */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_INVALID_MCRID_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_INVALID_MCRID_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_MC_TRIGGER_ERR 17:17 /* RWEVF */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_MC_TRIGGER_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_CONTAIN_EN_0_MC_TRIGGER_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FIRST_0 0x0000541c /* RW-4R */ +#define NV_ROUTE_ERR_FIRST_0_ROUTEBUFERR 0:0 /* RWDVF */ +#define NV_ROUTE_ERR_FIRST_0_ROUTEBUFERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_FIRST_0_ROUTEBUFERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_FIRST_0_ROUTEBUFERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FIRST_0_NOPORTDEFINEDERR 1:1 /* RWDVF */ +#define NV_ROUTE_ERR_FIRST_0_NOPORTDEFINEDERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_FIRST_0_NOPORTDEFINEDERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_FIRST_0_NOPORTDEFINEDERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FIRST_0_INVALIDROUTEPOLICYERR 2:2 /* RWDVF */ +#define NV_ROUTE_ERR_FIRST_0_INVALIDROUTEPOLICYERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_FIRST_0_INVALIDROUTEPOLICYERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_FIRST_0_INVALIDROUTEPOLICYERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FIRST_0_GLT_ECC_LIMIT_ERR 3:3 /* RWDVF */ +#define NV_ROUTE_ERR_FIRST_0_GLT_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_FIRST_0_GLT_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_FIRST_0_GLT_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FIRST_0_GLT_ECC_DBE_ERR 4:4 /* RWDVF */ +#define NV_ROUTE_ERR_FIRST_0_GLT_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_FIRST_0_GLT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_FIRST_0_GLT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FIRST_0_PDCTRLPARERR 6:6 /* RWDVF */ +#define NV_ROUTE_ERR_FIRST_0_PDCTRLPARERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_FIRST_0_PDCTRLPARERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_FIRST_0_PDCTRLPARERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FIRST_0_NVS_ECC_LIMIT_ERR 7:7 /* RWDVF */ +#define NV_ROUTE_ERR_FIRST_0_NVS_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_FIRST_0_NVS_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_FIRST_0_NVS_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FIRST_0_NVS_ECC_DBE_ERR 8:8 /* RWDVF */ +#define NV_ROUTE_ERR_FIRST_0_NVS_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_FIRST_0_NVS_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_FIRST_0_NVS_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FIRST_0_CDTPARERR 9:9 /* RWDVF */ +#define NV_ROUTE_ERR_FIRST_0_CDTPARERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_FIRST_0_CDTPARERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_FIRST_0_CDTPARERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FIRST_0_MCRID_ECC_LIMIT_ERR 10:10 /* RWDVF */ +#define NV_ROUTE_ERR_FIRST_0_MCRID_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_FIRST_0_MCRID_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_FIRST_0_MCRID_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FIRST_0_MCRID_ECC_DBE_ERR 11:11 /* RWDVF */ +#define NV_ROUTE_ERR_FIRST_0_MCRID_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_FIRST_0_MCRID_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_FIRST_0_MCRID_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FIRST_0_EXTMCRID_ECC_LIMIT_ERR 12:12 /* RWDVF */ +#define NV_ROUTE_ERR_FIRST_0_EXTMCRID_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_FIRST_0_EXTMCRID_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_FIRST_0_EXTMCRID_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FIRST_0_EXTMCRID_ECC_DBE_ERR 13:13 /* RWDVF */ +#define NV_ROUTE_ERR_FIRST_0_EXTMCRID_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_FIRST_0_EXTMCRID_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_FIRST_0_EXTMCRID_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FIRST_0_RAM_ECC_LIMIT_ERR 14:14 /* RWDVF */ +#define NV_ROUTE_ERR_FIRST_0_RAM_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_FIRST_0_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_FIRST_0_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FIRST_0_RAM_ECC_DBE_ERR 15:15 /* RWDVF */ +#define NV_ROUTE_ERR_FIRST_0_RAM_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_FIRST_0_RAM_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_FIRST_0_RAM_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FIRST_0_INVALID_MCRID_ERR 16:16 /* RWDVF */ +#define NV_ROUTE_ERR_FIRST_0_INVALID_MCRID_ERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_FIRST_0_INVALID_MCRID_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_FIRST_0_INVALID_MCRID_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_FIRST_0_MC_TRIGGER_ERR 17:17 /* RWDVF */ +#define NV_ROUTE_ERR_FIRST_0_MC_TRIGGER_ERR__ONWRITE "oneToClear" /* */ +#define NV_ROUTE_ERR_FIRST_0_MC_TRIGGER_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_FIRST_0_MC_TRIGGER_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_HEADER_LOG_4 0x00005430 /* R--4R */ +#define NV_ROUTE_ERR_HEADER_LOG_4_DW 31:0 /* R-DVF */ +#define NV_ROUTE_ERR_HEADER_LOG_4_DW_INIT 0x00000000 /* R-D-V */ +#define NV_ROUTE_ERR_HEADER_LOG_5 0x00005434 /* R--4R */ +#define NV_ROUTE_ERR_HEADER_LOG_5_DW 31:0 /* R-DVF */ +#define NV_ROUTE_ERR_HEADER_LOG_5_DW_INIT 0x00000000 /* R-D-V */ +#define NV_ROUTE_ERR_HEADER_LOG_6 0x00005438 /* R--4R */ +#define NV_ROUTE_ERR_HEADER_LOG_6_DW 31:0 /* R-DVF */ +#define NV_ROUTE_ERR_HEADER_LOG_6_DW_INIT 0x00000000 /* R-D-V */ +#define NV_ROUTE_ERR_HEADER_LOG_7 0x0000543c /* R--4R */ +#define NV_ROUTE_ERR_HEADER_LOG_7_DW 31:0 /* R-DVF */ +#define NV_ROUTE_ERR_HEADER_LOG_7_DW_INIT 0x00000000 /* R-D-V */ +#define NV_ROUTE_ERR_HEADER_LOG_8 0x00005440 /* R--4R */ +#define NV_ROUTE_ERR_HEADER_LOG_8_DW 31:0 /* R-DVF */ +#define NV_ROUTE_ERR_HEADER_LOG_8_DW_INIT 0x00000000 /* R-D-V */ +#define NV_ROUTE_ERR_HEADER_LOG_9 0x00005444 /* R--4R */ +#define NV_ROUTE_ERR_HEADER_LOG_9_DW 31:0 /* R-DVF */ +#define NV_ROUTE_ERR_HEADER_LOG_9_DW_INIT 0x00000000 /* R-D-V */ +#define NV_ROUTE_ERR_HEADER_LOG_10 0x00005448 /* R--4R */ +#define NV_ROUTE_ERR_HEADER_LOG_10_DW 31:0 /* R-DVF */ +#define NV_ROUTE_ERR_HEADER_LOG_10_DW_INIT 0x00000000 /* R-D-V */ +#define NV_ROUTE_ERR_HEADER_LOG_VALID 0x0000544c /* R--4R */ +#define NV_ROUTE_ERR_HEADER_LOG_VALID_HEADERVALID0 0:0 /* R-DVF */ +#define NV_ROUTE_ERR_HEADER_LOG_VALID_HEADERVALID0_INVALID 0x00000000 /* R-D-V */ +#define NV_ROUTE_ERR_HEADER_LOG_VALID_HEADERVALID0_VALID 0x00000001 /* R---V */ +#define NV_ROUTE_ERR_TIMESTAMP_LOG 0x00005450 /* R--4R */ +#define NV_ROUTE_ERR_TIMESTAMP_LOG_TIMESTAMP 23:0 /* R-DVF */ +#define NV_ROUTE_ERR_TIMESTAMP_LOG_TIMESTAMP_INIT 0x00000000 /* R-D-V */ +#define NV_ROUTE_ERR_MISC_LOG_0 0x00005454 /* R--4R */ +#define NV_ROUTE_ERR_MISC_LOG_0_SPORT 5:0 /* R-DVF */ +#define NV_ROUTE_ERR_MISC_LOG_0_SPORT_INIT 0x00000000 /* R-D-V */ +#define NV_ROUTE_ERR_MISC_LOG_0_ENCODEDVC 10:8 /* R-DVF */ +#define NV_ROUTE_ERR_MISC_LOG_0_ENCODEDVC_INIT 0x00000000 /* R-D-V */ +#define NV_ROUTE_ERR_ECC_CTRL 0x00005470 /* RW-4R */ +#define NV_ROUTE_ERR_ECC_CTRL_GLT_ECC_ENABLE 0:0 /* RWEVF */ +#define NV_ROUTE_ERR_ECC_CTRL_GLT_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_ECC_CTRL_GLT_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_ECC_CTRL_GLT_ECC_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_ECC_CTRL_NVS_ECC_ENABLE 2:2 /* RWEVF */ +#define NV_ROUTE_ERR_ECC_CTRL_NVS_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_ECC_CTRL_NVS_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_ECC_CTRL_NVS_ECC_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_ECC_CTRL_MCRID_ECC_ENABLE 3:3 /* RWEVF */ +#define NV_ROUTE_ERR_ECC_CTRL_MCRID_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_ECC_CTRL_MCRID_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_ECC_CTRL_MCRID_ECC_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_ECC_CTRL_EXTMCRID_ECC_ENABLE 4:4 /* RWEVF */ +#define NV_ROUTE_ERR_ECC_CTRL_EXTMCRID_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_ECC_CTRL_EXTMCRID_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_ECC_CTRL_EXTMCRID_ECC_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_ECC_CTRL_ECCWRITEBACKENBGLT 5:5 /* RWEVF */ +#define NV_ROUTE_ERR_ECC_CTRL_ECCWRITEBACKENBGLT_DISABLE 0x00000000 /* RW--V */ +#define NV_ROUTE_ERR_ECC_CTRL_ECCWRITEBACKENBGLT_ENABLE 0x00000001 /* RWE-V */ +#define NV_ROUTE_ERR_ECC_CTRL_ECCWRITEBACKMCRIDENB 6:6 /* RWEVF */ +#define NV_ROUTE_ERR_ECC_CTRL_ECCWRITEBACKMCRIDENB_DISABLE 0x00000000 /* RW--V */ +#define NV_ROUTE_ERR_ECC_CTRL_ECCWRITEBACKMCRIDENB_ENABLE 0x00000001 /* RWE-V */ +#define NV_ROUTE_ERR_ECC_CTRL_ECCWRITEBACKEXTMCRIDENB 7:7 /* RWEVF */ +#define NV_ROUTE_ERR_ECC_CTRL_ECCWRITEBACKEXTMCRIDENB_DISABLE 0x00000000 /* RW--V */ +#define NV_ROUTE_ERR_ECC_CTRL_ECCWRITEBACKEXTMCRIDENB_ENABLE 0x00000001 /* RWE-V */ +#define NV_ROUTE_ERR_ECC_CTRL_RAM_ECC_ENABLE 8:8 /* RWEVF */ +#define NV_ROUTE_ERR_ECC_CTRL_RAM_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_ECC_CTRL_RAM_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_ECC_CTRL_RAM_ECC_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_ROUTE_ERR_GLT_ECC_ERROR_COUNTER 0x00005480 /* RW-4R */ +#define NV_ROUTE_ERR_GLT_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */ +#define NV_ROUTE_ERR_GLT_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_GLT_ECC_ERROR_COUNTER_LIMIT 0x00005484 /* RW-4R */ +#define NV_ROUTE_ERR_GLT_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */ +#define NV_ROUTE_ERR_GLT_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */ +#define NV_ROUTE_ERR_GLT_ECC_ERROR_ADDRESS 0x00005488 /* R--4R */ +#define NV_ROUTE_ERR_GLT_ECC_ERROR_ADDRESS_ERROR_ADDRESS 7:0 /* R-DVF */ +#define NV_ROUTE_ERR_GLT_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */ +#define NV_ROUTE_ERR_GLT_ECC_ERROR_ADDRESS_VALID 0x0000548c /* R--4R */ +#define NV_ROUTE_ERR_GLT_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */ +#define NV_ROUTE_ERR_GLT_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */ +#define NV_ROUTE_ERR_GLT_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */ +#define NV_ROUTE_ERR_NVS_ECC_ERROR_COUNTER 0x00005490 /* RW-4R */ +#define NV_ROUTE_ERR_NVS_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */ +#define NV_ROUTE_ERR_NVS_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_NVS_ECC_ERROR_COUNTER_LIMIT 0x00005494 /* RW-4R */ +#define NV_ROUTE_ERR_NVS_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */ +#define NV_ROUTE_ERR_NVS_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */ +#define NV_ROUTE_ERR_MCRID_ECC_ERROR_COUNTER 0x00005498 /* RW-4R */ +#define NV_ROUTE_ERR_MCRID_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */ +#define NV_ROUTE_ERR_MCRID_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_MCRID_ECC_ERROR_COUNTER_LIMIT 0x0000549c /* RW-4R */ +#define NV_ROUTE_ERR_MCRID_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */ +#define NV_ROUTE_ERR_MCRID_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */ +#define NV_ROUTE_ERR_MCRID_ECC_ERROR_ADDRESS 0x000054a0 /* R--4R */ +#define NV_ROUTE_ERR_MCRID_ECC_ERROR_ADDRESS_ERROR_ADDRESS 6:0 /* R-DVF */ +#define NV_ROUTE_ERR_MCRID_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */ +#define NV_ROUTE_ERR_MCRID_ECC_ERROR_ADDRESS_VALID 0x000054a4 /* R--4R */ +#define NV_ROUTE_ERR_MCRID_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */ +#define NV_ROUTE_ERR_MCRID_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */ +#define NV_ROUTE_ERR_MCRID_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */ +#define NV_ROUTE_ERR_EXTMCRID_ECC_ERROR_COUNTER 0x000054a8 /* RW-4R */ +#define NV_ROUTE_ERR_EXTMCRID_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */ +#define NV_ROUTE_ERR_EXTMCRID_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_EXTMCRID_ECC_ERROR_COUNTER_LIMIT 0x000054ac /* RW-4R */ +#define NV_ROUTE_ERR_EXTMCRID_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */ +#define NV_ROUTE_ERR_EXTMCRID_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */ +#define NV_ROUTE_ERR_EXTMCRID_ECC_ERROR_ADDRESS 0x000054b0 /* R--4R */ +#define NV_ROUTE_ERR_EXTMCRID_ECC_ERROR_ADDRESS_ERROR_ADDRESS 3:0 /* R-DVF */ +#define NV_ROUTE_ERR_EXTMCRID_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */ +#define NV_ROUTE_ERR_EXTMCRID_ECC_ERROR_ADDRESS_VALID 0x000054b4 /* R--4R */ +#define NV_ROUTE_ERR_EXTMCRID_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */ +#define NV_ROUTE_ERR_EXTMCRID_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */ +#define NV_ROUTE_ERR_EXTMCRID_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */ +#define NV_ROUTE_MCRID_ECC 0x000054b8 /* R--4R */ +#define NV_ROUTE_MCRID_ECC_MCRID_ECC 10:0 /* R-EVF */ +#define NV_ROUTE_MCRID_ECC_MCRID_ECC_INIT 0x00000000 /* R-E-V */ +#define NV_ROUTE_MCRID_ECC_EXTMCRID_ECC 26:16 /* R-EVF */ +#define NV_ROUTE_MCRID_ECC_EXTMCRID_ECC_INIT 0x00000000 /* R-E-V */ +#define NV_ROUTE_ERR_RAM_ECC_ERROR_COUNTER 0x000054bc /* RW-4R */ +#define NV_ROUTE_ERR_RAM_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */ +#define NV_ROUTE_ERR_RAM_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */ +#define NV_ROUTE_ERR_RAM_ECC_ERROR_COUNTER_LIMIT 0x000054c0 /* RW-4R */ +#define NV_ROUTE_ERR_RAM_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */ +#define NV_ROUTE_ERR_RAM_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */ +#define NV_ROUTE_RIDTABADDR 0x00005600 /* RW-4R */ +#define NV_ROUTE_RIDTABADDR_INDEX 6:0 /* RWEVF */ +#define NV_ROUTE_RIDTABADDR_INDEX_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_RIDTABADDR_INDEX_MCRIDTAB_DEPTH 0x0000007f /* RW--V */ +#define NV_ROUTE_RIDTABADDR_INDEX_MCRIDEXTTAB_DEPTH 0x0000000f /* RW--V */ +#define NV_ROUTE_RIDTABADDR_RAM_SEL 16:16 /* RWEVF */ +#define NV_ROUTE_RIDTABADDR_RAM_SEL_SELECTSMCRIDROUTERAM 0x00000000 /* RWE-V */ +#define NV_ROUTE_RIDTABADDR_RAM_SEL_SELECTSEXTMCRIDROUTERAM 0x00000001 /* RW--V */ +#define NV_ROUTE_RIDTABADDR_AUTO_INCR 31:31 /* RWEVF */ +#define NV_ROUTE_RIDTABADDR_AUTO_INCR_ENABLE 0x00000001 /* RWE-V */ +#define NV_ROUTE_RIDTABADDR_AUTO_INCR_DISABLE 0x00000000 /* RW--V */ +#define NV_ROUTE_RIDTABDATA0 0x00005610 /* RW-4R */ +#define NV_ROUTE_RIDTABDATA0_MCPL_SIZE 5:0 /* RWEVF */ +#define NV_ROUTE_RIDTABDATA0_MCPL_SIZE_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_RIDTABDATA0_MCPL_SPRAY_SIZE 11:8 /* RWEVF */ +#define NV_ROUTE_RIDTABDATA0_MCPL_SPRAY_SIZE_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_RIDTABDATA0_MCPL_RID_EXT_PTR 19:16 /* RWEVF */ +#define NV_ROUTE_RIDTABDATA0_MCPL_RID_EXT_PTR_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_RIDTABDATA0_MCPL_NO_DYN_RSP 29:29 /* RWEVF */ +#define NV_ROUTE_RIDTABDATA0_MCPL_NO_DYN_RSP_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_RIDTABDATA0_MCPL_RID_EXT_PTR_VAL 30:30 /* RWEVF */ +#define NV_ROUTE_RIDTABDATA0_MCPL_RID_EXT_PTR_VAL_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_RIDTABDATA0_VALID 31:31 /* RWEVF */ +#define NV_ROUTE_RIDTABDATA0_VALID_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_RIDTABDATA0_VALID_VALID 0x00000001 /* RW--V */ +#define NV_ROUTE_RIDTABDATA1 0x00005614 /* RW-4R */ +#define NV_ROUTE_RIDTABDATA1_MCPL_E_PORT 3:0 /* RWEVF */ +#define NV_ROUTE_RIDTABDATA1_MCPL_E_PORT_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_RIDTABDATA1_MCPL_E_ALTPATH 4:4 /* RWEVF */ +#define NV_ROUTE_RIDTABDATA1_MCPL_E_ALTPATH_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_RIDTABDATA1_MCPL_E_REQ_VCHOP 6:5 /* RWEVF */ +#define NV_ROUTE_RIDTABDATA1_MCPL_E_REQ_VCHOP_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_RIDTABDATA1_MCPL_O_PORT 10:7 /* RWEVF */ +#define NV_ROUTE_RIDTABDATA1_MCPL_O_PORT_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_RIDTABDATA1_MCPL_O_ALTPATH 11:11 /* RWEVF */ +#define NV_ROUTE_RIDTABDATA1_MCPL_O_ALTPATH_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_RIDTABDATA1_MCPL_O_REQ_VCHOP 13:12 /* RWEVF */ +#define NV_ROUTE_RIDTABDATA1_MCPL_O_REQ_VCHOP_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_RIDTABDATA1_MCPL_TCP 15:14 /* RWEVF */ +#define NV_ROUTE_RIDTABDATA1_MCPL_TCP_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_RIDTABDATA1_MCPL_PORT_FLAG 16:16 /* RWEVF */ +#define NV_ROUTE_RIDTABDATA1_MCPL_PORT_FLAG_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_RIDTABDATA1_MCPL_RND_CONTINUE 17:17 /* RWEVF */ +#define NV_ROUTE_RIDTABDATA1_MCPL_RND_CONTINUE_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_RIDTABDATA1_MCPL_LAST_RND 18:18 /* RWEVF */ +#define NV_ROUTE_RIDTABDATA1_MCPL_LAST_RND_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_RIDTABDATA2 0x00005618 /* RW-4R */ +#define NV_ROUTE_RIDTABDATA2_MCPL_STR_PTR0 4:0 /* RWEVF */ +#define NV_ROUTE_RIDTABDATA2_MCPL_STR_PTR0_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_RIDTABDATA2_MCPL_STR_PTR1 12:8 /* RWEVF */ +#define NV_ROUTE_RIDTABDATA2_MCPL_STR_PTR1_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_RIDTABDATA2_MCPL_STR_PTR2 20:16 /* RWEVF */ +#define NV_ROUTE_RIDTABDATA2_MCPL_STR_PTR2_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_RIDTABDATA2_MCPL_STR_PTR3 28:24 /* RWEVF */ +#define NV_ROUTE_RIDTABDATA2_MCPL_STR_PTR3_INIT 0x00000000 /* RWE-V */ +#define NV_ROUTE_ERR_RAM_ECC_ERROR_ADDRESS 0x0000561c /* R--4R */ +#define NV_ROUTE_ERR_RAM_ECC_ERROR_ADDRESS_ERROR_ADDRESS 8:0 /* R-DVF */ +#define NV_ROUTE_ERR_RAM_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */ +#define NV_ROUTE_ERR_RAM_ECC_ERROR_ADDRESS_VALID 0x00005620 /* R--4R */ +#define NV_ROUTE_ERR_RAM_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */ +#define NV_ROUTE_ERR_RAM_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */ +#define NV_ROUTE_ERR_RAM_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */ +#endif // __ls10_dev_route_ip_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_route_ip_addendum.h b/src/common/inc/swref/published/nvswitch/ls10/dev_route_ip_addendum.h new file mode 100644 index 000000000..eb3030f16 --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_route_ip_addendum.h @@ -0,0 +1,31 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_route_ip_addendum_h__ +#define __ls10_dev_route_ip_addendum_h__ + +// NV_ROUTE_REG_TABLE_DATA0 definition in the manuals have no indexing. + +#define NV_ROUTE_REG_TABLE_DATA0_GLX(i) 4*(i)+3:4*(i)+0 + +#endif // __ls10_dev_route_ip_addendum_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_se_pri.h b/src/common/inc/swref/published/nvswitch/ls10/dev_se_pri.h new file mode 100644 index 000000000..b6bd910bd --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_se_pri.h @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_se_pri_h__ +#define __ls10_dev_se_pri_h__ +/* This file is autogenerated. Do not edit */ +#define NV_PSE 0x001dffff:0x001d8000 /* RW--D */ +#define NV_PSE_CG1 0x001df130 /* RW-4R */ +#define NV_PSE_CG1_SLCG 8:1 /* RWIVF */ +#define NV_PSE_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ +#define NV_PSE_CG1_SLCG_DISABLED 0x000000ff /* RWI-V */ +#define NV_PSE_CG1_SLCG__PROD 0x000000ff /* RW--V */ +#endif // __ls10_dev_se_pri_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_soe_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_soe_ip.h new file mode 100644 index 000000000..4017f58ed --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_soe_ip.h @@ -0,0 +1,364 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_soe_ip_h__ +#define __ls10_dev_soe_ip_h__ +/* This file is autogenerated. Do not edit */ +#define NV_SOE 0x3fff:0x0000 /* RW--D */ +#define NV_SOE_FALCON_IRQSTAT 0x0008 /* R--4R */ +#define NV_SOE_FALCON_IRQSTAT__DEVICE_MAP 0x00000002 /* */ +#define NV_SOE_FALCON_IRQSTAT_GPTMR 0:0 /* R-IVF */ +#define NV_SOE_FALCON_IRQSTAT_GPTMR_FALSE 0x00000000 /* R-I-V */ +#define NV_SOE_FALCON_IRQSTAT_GPTMR_TRUE 0x00000001 /* R---V */ +#define NV_SOE_FALCON_IRQSTAT_WDTMR 1:1 /* R-IVF */ +#define NV_SOE_FALCON_IRQSTAT_WDTMR_FALSE 0x00000000 /* R-I-V */ +#define NV_SOE_FALCON_IRQSTAT_WDTMR_TRUE 0x00000001 /* R---V */ +#define NV_SOE_FALCON_IRQSTAT_MTHD 2:2 /* R-IVF */ +#define NV_SOE_FALCON_IRQSTAT_MTHD_FALSE 0x00000000 /* R-I-V */ +#define NV_SOE_FALCON_IRQSTAT_MTHD_TRUE 0x00000001 /* R---V */ +#define NV_SOE_FALCON_IRQSTAT_CTXSW 3:3 /* R-IVF */ +#define NV_SOE_FALCON_IRQSTAT_CTXSW_FALSE 0x00000000 /* R-I-V */ +#define NV_SOE_FALCON_IRQSTAT_CTXSW_TRUE 0x00000001 /* R---V */ +#define NV_SOE_FALCON_IRQSTAT_HALT 4:4 /* R-IVF */ +#define NV_SOE_FALCON_IRQSTAT_HALT_FALSE 0x00000000 /* R-I-V */ +#define NV_SOE_FALCON_IRQSTAT_HALT_TRUE 0x00000001 /* R---V */ +#define NV_SOE_FALCON_IRQSTAT_EXTERR 5:5 /* R-IVF */ +#define NV_SOE_FALCON_IRQSTAT_EXTERR_FALSE 0x00000000 /* R-I-V */ +#define NV_SOE_FALCON_IRQSTAT_EXTERR_TRUE 0x00000001 /* R---V */ +#define NV_SOE_FALCON_IRQSTAT_SWGEN0 6:6 /* R-IVF */ +#define NV_SOE_FALCON_IRQSTAT_SWGEN0_FALSE 0x00000000 /* R-I-V */ +#define NV_SOE_FALCON_IRQSTAT_SWGEN0_TRUE 0x00000001 /* R---V */ +#define NV_SOE_FALCON_IRQSTAT_SWGEN1 7:7 /* R-IVF */ +#define NV_SOE_FALCON_IRQSTAT_SWGEN1_FALSE 0x00000000 /* R-I-V */ +#define NV_SOE_FALCON_IRQSTAT_SWGEN1_TRUE 0x00000001 /* R---V */ +#define NV_SOE_FALCON_IRQSTAT_EXT 15:8 /* */ +#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ1 8:8 /* R-IVF */ +#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ1_TRUE 0x00000001 /* R---V */ +#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ1_FALSE 0x00000000 /* R-I-V */ +#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ2 9:9 /* R-IVF */ +#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ2_TRUE 0x00000001 /* R---V */ +#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ2_FALSE 0x00000000 /* R-I-V */ +#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ3 10:10 /* R-IVF */ +#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ3_TRUE 0x00000001 /* R---V */ +#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ3_FALSE 0x00000000 /* R-I-V */ +#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ4 11:11 /* R-IVF */ +#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ4_TRUE 0x00000001 /* R---V */ +#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ4_FALSE 0x00000000 /* R-I-V */ +#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ5 12:12 /* R-IVF */ +#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ5_TRUE 0x00000001 /* R---V */ +#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ5_FALSE 0x00000000 /* R-I-V */ +#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ6 13:13 /* R-IVF */ +#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ6_TRUE 0x00000001 /* R---V */ +#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ6_FALSE 0x00000000 /* R-I-V */ +#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ7 14:14 /* R-IVF */ +#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ7_TRUE 0x00000001 /* R---V */ +#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ7_FALSE 0x00000000 /* R-I-V */ +#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ8 15:15 /* R-IVF */ +#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ8_TRUE 0x00000001 /* R---V */ +#define NV_SOE_FALCON_IRQSTAT_EXT_EXTIRQ8_FALSE 0x00000000 /* R-I-V */ +#define NV_SOE_FALCON_IRQSTAT_DMA 16:16 /* R-IVF */ +#define NV_SOE_FALCON_IRQSTAT_DMA_TRUE 0x00000001 /* R---V */ +#define NV_SOE_FALCON_IRQSTAT_DMA_FALSE 0x00000000 /* R-I-V */ +#define NV_SOE_FALCON_IRQSTAT_SHA 17:17 /* R-IVF */ +#define NV_SOE_FALCON_IRQSTAT_SHA_TRUE 0x00000001 /* R---V */ +#define NV_SOE_FALCON_IRQSTAT_SHA_FALSE 0x00000000 /* R-I-V */ +#define NV_SOE_FALCON_IRQSTAT_MEMERR 18:18 /* R-IVF */ +#define NV_SOE_FALCON_IRQSTAT_MEMERR_TRUE 0x00000001 /* R---V */ +#define NV_SOE_FALCON_IRQSTAT_MEMERR_FALSE 0x00000000 /* R-I-V */ +#define NV_SOE_FALCON_IRQSTAT_CTXSW_ERROR 19:19 /* R-XVF */ +#define NV_SOE_FALCON_IRQSTAT_CTXSW_ERROR_TRUE 0x00000001 /* R---V */ +#define NV_SOE_FALCON_IRQSTAT_CTXSW_ERROR_FALSE 0x00000000 /* R---V */ +#define NV_SOE_FALCON_IRQSTAT_GDMA 20:20 /* R-XVF */ +#define NV_SOE_FALCON_IRQSTAT_GDMA_TRUE 0x00000001 /* R---V */ +#define NV_SOE_FALCON_IRQSTAT_GDMA_FALSE 0x00000000 /* R---V */ +#define NV_SOE_FALCON_IRQSTAT_ICD 22:22 /* R-XVF */ +#define NV_SOE_FALCON_IRQSTAT_ICD_TRUE 0x00000001 /* R---V */ +#define NV_SOE_FALCON_IRQSTAT_ICD_FALSE 0x00000000 /* R---V */ +#define NV_SOE_FALCON_IRQSTAT_IOPMP 23:23 /* R-XVF */ +#define NV_SOE_FALCON_IRQSTAT_IOPMP_TRUE 0x00000001 /* R---V */ +#define NV_SOE_FALCON_IRQSTAT_IOPMP_FALSE 0x00000000 /* R---V */ +#define NV_SOE_FALCON_IRQSTAT_CORE_MISMATCH 24:24 /* R-XVF */ +#define NV_SOE_FALCON_IRQSTAT_CORE_MISMATCH_TRUE 0x00000001 /* R---V */ +#define NV_SOE_FALCON_IRQSTAT_CORE_MISMATCH_FALSE 0x00000000 /* R---V */ +#define NV_SOE_FALCON_IRQSTAT_SE_SAP 25:25 /* R-XVF */ +#define NV_SOE_FALCON_IRQSTAT_SE_SAP_SET 0x00000001 /* R---V */ +#define NV_SOE_FALCON_IRQSTAT_SE_PKA 26:26 /* R-XVF */ +#define NV_SOE_FALCON_IRQSTAT_SE_PKA_SET 0x00000001 /* R---V */ +#define NV_SOE_FALCON_IRQSTAT_SE_RNG 27:27 /* R-XVF */ +#define NV_SOE_FALCON_IRQSTAT_SE_RNG_SET 0x00000001 /* R---V */ +#define NV_SOE_FALCON_IRQSTAT_SE_KEYMOVER 28:28 /* R-XVF */ +#define NV_SOE_FALCON_IRQSTAT_SE_KEYMOVER_SET 0x00000001 /* R---V */ +#define NV_SOE_FALCON_CGCTL 0x00a0 /* RW-4R */ +#define NV_SOE_FALCON_CGCTL__DEVICE_MAP 0x00000000 /* */ +#define NV_SOE_FALCON_CGCTL_CG_OVERRIDE 0:0 /* RWIVF */ +#define NV_SOE_FALCON_CGCTL_CG_OVERRIDE_INIT 0x00000000 /* RWI-V */ +#define NV_SOE_FALCON_CG2 0x0134 /* RW-4R */ +#define NV_SOE_FALCON_CG2__DEVICE_MAP 0x00000000 /* */ +#define NV_SOE_FALCON_CG2_SLCG 17:1 /* */ +#define NV_SOE_FALCON_CG2_SLCG_ENABLED 0 /* */ +#define NV_SOE_FALCON_CG2_SLCG_DISABLED 0x1FFFF /* */ +#define NV_SOE_FALCON_CG2_SLCG__PROD 0x000A0 /* */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_DMA 1:1 /* RWIVF */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_DMA_ENABLED 0x00000000 /* RW--V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_DMA_DISABLED 0x00000001 /* RWI-V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM 2:2 /* RWIVF */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_ENABLED 0x00000000 /* RW--V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_DISABLED 0x00000001 /* RWI-V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_PIPE 3:3 /* RWIVF */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_PIPE_ENABLED 0x00000000 /* RW--V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_PIPE_DISABLED 0x00000001 /* RWI-V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_DIV 4:4 /* RWIVF */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_DIV_ENABLED 0x00000000 /* RW--V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_DIV_DISABLED 0x00000001 /* RWI-V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_ICD 5:5 /* RWIVF */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_ICD_ENABLED 0x00000000 /* RW--V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_ICD_DISABLED 0x00000001 /* RWI-V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_CFG 6:6 /* RWIVF */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_CFG_ENABLED 0x00000000 /* RW--V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_CFG_DISABLED 0x00000001 /* RWI-V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_CTXSW 7:7 /* RWIVF */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_CTXSW_ENABLED 0x00000000 /* RW--V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_CTXSW_DISABLED 0x00000001 /* RWI-V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_PMB 8:8 /* RWIVF */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_PMB_ENABLED 0x00000000 /* RW--V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_PMB_DISABLED 0x00000001 /* RWI-V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_RF 9:9 /* RWIVF */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_RF_ENABLED 0x00000000 /* RW--V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_RF_DISABLED 0x00000001 /* RWI-V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_MUL 10:10 /* RWIVF */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_MUL_ENABLED 0x00000000 /* RW--V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_MUL_DISABLED 0x00000001 /* RWI-V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_LDST 11:11 /* RWIVF */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_LDST_ENABLED 0x00000000 /* RW--V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_LDST_DISABLED 0x00000001 /* RWI-V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_TSYNC 12:12 /* RWIVF */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_TSYNC_ENABLED 0x00000000 /* RW--V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_TSYNC_DISABLED 0x00000001 /* RWI-V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_GPTMR 13:13 /* RWIVF */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_GPTMR_ENABLED 0x00000000 /* RW--V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_GPTMR_DISABLED 0x00000001 /* RWI-V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_WDTMR 14:14 /* RWIVF */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_WDTMR_ENABLED 0x00000000 /* RW--V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_WDTMR_DISABLED 0x00000001 /* RWI-V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_IRQSTAT 15:15 /* RWIVF */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_IRQSTAT_ENABLED 0x00000000 /* RW--V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_IRQSTAT_DISABLED 0x00000001 /* RWI-V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_TOP 16:16 /* RWIVF */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_TOP_ENABLED 0x00000000 /* RW--V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_TOP_DISABLED 0x00000001 /* RWI-V */ +#define NV_SOE_FALCON_CG2_SLCG_FBIF 17:17 /* RWIVF */ +#define NV_SOE_FALCON_CG2_SLCG_FBIF_ENABLED 0x00000000 /* RW--V */ +#define NV_SOE_FALCON_CG2_SLCG_FBIF_DISABLED 0x00000001 /* RWI-V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_SHA 18:18 /* RWIVF */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_SHA__PROD 0x00000001 /* RW--V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_SHA_ENABLED 0x00000000 /* RW--V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_SHA_DISABLED 0x00000001 /* RWI-V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_GDMA 19:19 /* RWIVF */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_GDMA__PROD 0x00000001 /* RW--V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_GDMA_ENABLED 0x00000000 /* RW--V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_GDMA_DISABLED 0x00000001 /* RWI-V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_TSE 20:20 /* RWIVF */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_TSE__PROD 0x00000001 /* RW--V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_TSE_ENABLED 0x00000000 /* RW--V */ +#define NV_SOE_FALCON_CG2_SLCG_FALCON_TSE_DISABLED 0x00000001 /* RWI-V */ +#define NV_SOE_RISCV_IRQMASK 0x1528 /* R--4R */ +#define NV_SOE_RISCV_IRQMASK__DEVICE_MAP 0x00000002 /* */ +#define NV_SOE_RISCV_IRQMASK_GPTMR 0:0 /* R-IVF */ +#define NV_SOE_RISCV_IRQMASK_GPTMR_UNSET 0x00000000 /* R-I-V */ +#define NV_SOE_RISCV_IRQMASK_GPTMR_SET 0x00000001 /* R---V */ +#define NV_SOE_RISCV_IRQMASK_WDTMR 1:1 /* R-IVF */ +#define NV_SOE_RISCV_IRQMASK_WDTMR_UNSET 0x00000000 /* R-I-V */ +#define NV_SOE_RISCV_IRQMASK_WDTMR_SET 0x00000001 /* R---V */ +#define NV_SOE_RISCV_IRQMASK_MTHD 2:2 /* R-IVF */ +#define NV_SOE_RISCV_IRQMASK_MTHD_UNSET 0x00000000 /* R-I-V */ +#define NV_SOE_RISCV_IRQMASK_MTHD_SET 0x00000001 /* R---V */ +#define NV_SOE_RISCV_IRQMASK_CTXSW 3:3 /* R-IVF */ +#define NV_SOE_RISCV_IRQMASK_CTXSW_UNSET 0x00000000 /* R-I-V */ +#define NV_SOE_RISCV_IRQMASK_CTXSW_SET 0x00000001 /* R---V */ +#define NV_SOE_RISCV_IRQMASK_HALT 4:4 /* R-IVF */ +#define NV_SOE_RISCV_IRQMASK_HALT_UNSET 0x00000000 /* R-I-V */ +#define NV_SOE_RISCV_IRQMASK_HALT_SET 0x00000001 /* R---V */ +#define NV_SOE_RISCV_IRQMASK_EXTERR 5:5 /* R-IVF */ +#define NV_SOE_RISCV_IRQMASK_EXTERR_UNSET 0x00000000 /* R-I-V */ +#define NV_SOE_RISCV_IRQMASK_EXTERR_SET 0x00000001 /* R---V */ +#define NV_SOE_RISCV_IRQMASK_SWGEN0 6:6 /* R-IVF */ +#define NV_SOE_RISCV_IRQMASK_SWGEN0_UNSET 0x00000000 /* R-I-V */ +#define NV_SOE_RISCV_IRQMASK_SWGEN0_SET 0x00000001 /* R---V */ +#define NV_SOE_RISCV_IRQMASK_SWGEN1 7:7 /* R-IVF */ +#define NV_SOE_RISCV_IRQMASK_SWGEN1_UNSET 0x00000000 /* R-I-V */ +#define NV_SOE_RISCV_IRQMASK_SWGEN1_SET 0x00000001 /* R---V */ +#define NV_SOE_RISCV_IRQDEST 0x152c /* RW-4R */ +#define NV_SOE_RISCV_IRQDEST__DEVICE_MAP 0x00000002 /* */ +#define NV_SOE_RISCV_IRQDEST_GPTMR 0:0 /* RWIVF */ +#define NV_SOE_RISCV_IRQDEST_GPTMR_RISCV 0x00000000 /* RWI-V */ +#define NV_SOE_RISCV_IRQDEST_GPTMR_HOST 0x00000001 /* RW--V */ +#define NV_SOE_RISCV_IRQDEST_WDTMR 1:1 /* RWIVF */ +#define NV_SOE_RISCV_IRQDEST_WDTMR_RISCV 0x00000000 /* RWI-V */ +#define NV_SOE_RISCV_IRQDEST_WDTMR_HOST 0x00000001 /* RW--V */ +#define NV_SOE_RISCV_IRQDEST_MTHD 2:2 /* RWIVF */ +#define NV_SOE_RISCV_IRQDEST_MTHD_RISCV 0x00000000 /* RWI-V */ +#define NV_SOE_RISCV_IRQDEST_MTHD_HOST 0x00000001 /* RW--V */ +#define NV_SOE_RISCV_IRQDEST_CTXSW 3:3 /* RWIVF */ +#define NV_SOE_RISCV_IRQDEST_CTXSW_RISCV 0x00000000 /* RWI-V */ +#define NV_SOE_RISCV_IRQDEST_CTXSW_HOST 0x00000001 /* RW--V */ +#define NV_SOE_RISCV_IRQDEST_HALT 4:4 /* RWIVF */ +#define NV_SOE_RISCV_IRQDEST_HALT_RISCV 0x00000000 /* RWI-V */ +#define NV_SOE_RISCV_IRQDEST_HALT_HOST 0x00000001 /* RW--V */ +#define NV_SOE_RISCV_IRQDEST_EXTERR 5:5 /* RWIVF */ +#define NV_SOE_RISCV_IRQDEST_EXTERR_RISCV 0x00000000 /* RWI-V */ +#define NV_SOE_RISCV_IRQDEST_EXTERR_HOST 0x00000001 /* RW--V */ +#define NV_SOE_RISCV_IRQDEST_SWGEN0 6:6 /* RWIVF */ +#define NV_SOE_RISCV_IRQDEST_SWGEN0_RISCV 0x00000000 /* RWI-V */ +#define NV_SOE_RISCV_IRQDEST_SWGEN0_HOST 0x00000001 /* RW--V */ +#define NV_SOE_RISCV_IRQDEST_SWGEN1 7:7 /* RWIVF */ +#define NV_SOE_RISCV_IRQDEST_SWGEN1_RISCV 0x00000000 /* RWI-V */ +#define NV_SOE_RISCV_IRQDEST_SWGEN1_HOST 0x00000001 /* RW--V */ +#define NV_SOE_RISCV_IRQDEST_EXT 15:8 /* */ +#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ1 8:8 /* RWIVF */ +#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ1_RISCV 0x00000000 /* RWI-V */ +#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ1_HOST 0x00000001 /* RW--V */ +#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ2 9:9 /* RWIVF */ +#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ2_RISCV 0x00000000 /* RWI-V */ +#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ2_HOST 0x00000001 /* RW--V */ +#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ3 10:10 /* RWIVF */ +#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ3_RISCV 0x00000000 /* RWI-V */ +#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ3_HOST 0x00000001 /* RW--V */ +#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ4 11:11 /* RWIVF */ +#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ4_RISCV 0x00000000 /* RWI-V */ +#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ4_HOST 0x00000001 /* RW--V */ +#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ5 12:12 /* RWIVF */ +#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ5_RISCV 0x00000000 /* RWI-V */ +#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ5_HOST 0x00000001 /* RW--V */ +#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ6 13:13 /* RWIVF */ +#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ6_RISCV 0x00000000 /* RWI-V */ +#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ6_HOST 0x00000001 /* RW--V */ +#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ7 14:14 /* RWIVF */ +#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ7_RISCV 0x00000000 /* RWI-V */ +#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ7_HOST 0x00000001 /* RW--V */ +#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ8 15:15 /* RWIVF */ +#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ8_RISCV 0x00000000 /* RWI-V */ +#define NV_SOE_RISCV_IRQDEST_EXT_EXTIRQ8_HOST 0x00000001 /* RW--V */ +#define NV_SOE_RISCV_IRQDEST_DMA 16:16 /* RWIVF */ +#define NV_SOE_RISCV_IRQDEST_DMA_RISCV 0x00000000 /* RWI-V */ +#define NV_SOE_RISCV_IRQDEST_DMA_HOST 0x00000001 /* RW--V */ +#define NV_SOE_RISCV_IRQDEST_SHA 17:17 /* RWIVF */ +#define NV_SOE_RISCV_IRQDEST_SHA_RISCV 0x00000000 /* RWI-V */ +#define NV_SOE_RISCV_IRQDEST_SHA_HOST 0x00000001 /* RW--V */ +#define NV_SOE_RISCV_IRQDEST_MEMERR 18:18 /* RWIVF */ +#define NV_SOE_RISCV_IRQDEST_MEMERR_RISCV 0x00000000 /* RWI-V */ +#define NV_SOE_RISCV_IRQDEST_MEMERR_HOST 0x00000001 /* RW--V */ +#define NV_SOE_RISCV_IRQDEST_CTXSW_ERROR 19:19 /* R-IVF */ +#define NV_SOE_RISCV_IRQDEST_CTXSW_ERROR_RISCV 0x00000000 /* R---V */ +#define NV_SOE_RISCV_IRQDEST_CTXSW_ERROR_HOST 0x00000001 /* R-I-V */ +#define NV_SOE_RISCV_IRQDEST_GDMA 20:20 /* RWIVF */ +#define NV_SOE_RISCV_IRQDEST_GDMA_RISCV 0x00000000 /* RWI-V */ +#define NV_SOE_RISCV_IRQDEST_GDMA_HOST 0x00000001 /* RW--V */ +#define NV_SOE_RISCV_IRQDEST_ICD 22:22 /* RWIVF */ +#define NV_SOE_RISCV_IRQDEST_ICD_RISCV 0x00000000 /* RWI-V */ +#define NV_SOE_RISCV_IRQDEST_ICD_HOST 0x00000001 /* RW--V */ +#define NV_SOE_RISCV_IRQDEST_IOPMP 23:23 /* RWIVF */ +#define NV_SOE_RISCV_IRQDEST_IOPMP_RISCV 0x00000000 /* RWI-V */ +#define NV_SOE_RISCV_IRQDEST_IOPMP_HOST 0x00000001 /* RW--V */ +#define NV_SOE_RISCV_IRQDEST_CORE_MISMATCH 24:24 /* R-IVF */ +#define NV_SOE_RISCV_IRQDEST_CORE_MISMATCH_RISCV 0x00000000 /* R---V */ +#define NV_SOE_RISCV_IRQDEST_CORE_MISMATCH_HOST 0x00000001 /* R-I-V */ +#define NV_SOE_RISCV_IRQDEST_SE_SAP 25:25 /* RWIVF */ +#define NV_SOE_RISCV_IRQDEST_SE_SAP_RISCV 0x00000000 /* RWI-V */ +#define NV_SOE_RISCV_IRQDEST_SE_SAP_HOST 0x00000001 /* RW--V */ +#define NV_SOE_RISCV_IRQDEST_SE_PKA 26:26 /* RWIVF */ +#define NV_SOE_RISCV_IRQDEST_SE_PKA_RISCV 0x00000000 /* RWI-V */ +#define NV_SOE_RISCV_IRQDEST_SE_PKA_HOST 0x00000001 /* RW--V */ +#define NV_SOE_RISCV_IRQDEST_SE_RNG 27:27 /* RWIVF */ +#define NV_SOE_RISCV_IRQDEST_SE_RNG_RISCV 0x00000000 /* RWI-V */ +#define NV_SOE_RISCV_IRQDEST_SE_RNG_HOST 0x00000001 /* RW--V */ +#define NV_SOE_RISCV_IRQDEST_SE_KEYMOVER 28:28 /* RWIVF */ +#define NV_SOE_RISCV_IRQDEST_SE_KEYMOVER_RISCV 0x00000000 /* RWI-V */ +#define NV_SOE_RISCV_IRQDEST_SE_KEYMOVER_HOST 0x00000001 /* RW--V */ +#define NV_SOE_RISCV_CPUCTL 0x1388 /* RW-4R */ +#define NV_SOE_RISCV_CPUCTL_STARTCPU 0:0 /* -WIVF */ +#define NV_SOE_RISCV_CPUCTL_STARTCPU_FALSE 0x00000000 /* -WI-V */ +#define NV_SOE_RISCV_CPUCTL_STARTCPU_TRUE 0x00000001 /* -W--V */ +#define NV_SOE_RISCV_CPUCTL_HALTED 4:4 /* R-IVF */ +#define NV_SOE_RISCV_CPUCTL_HALTED_INIT 0x00000001 /* R-I-V */ +#define NV_SOE_RISCV_CPUCTL_HALTED_TRUE 0x00000001 /* R---V */ +#define NV_SOE_RISCV_CPUCTL_HALTED_FALSE 0x00000000 /* R---V */ +#define NV_SOE_RISCV_CPUCTL_STOPPED 5:5 /* R-IVF */ +#define NV_SOE_RISCV_CPUCTL_STOPPED_INIT 0x00000000 /* R-I-V */ +#define NV_SOE_RISCV_CPUCTL_ACTIVE_STAT 7:7 /* R-IVF */ +#define NV_SOE_RISCV_CPUCTL_ACTIVE_STAT_INACTIVE 0x00000000 /* R-I-V */ +#define NV_SOE_RISCV_CPUCTL_ACTIVE_STAT_ACTIVE 0x00000001 /* R---V */ +#define NV_SOE_RISCV_CG 0x1398 /* RW-4R */ +#define NV_SOE_RISCV_CG__DEVICE_MAP 0x00000000 /* */ +#define NV_SOE_RISCV_CG_SLCG 1:0 /* */ +#define NV_SOE_RISCV_CG_SLCG_DISABLED 0 /* */ +#define NV_SOE_RISCV_CG_SLCG_ENABLED 3 /* */ +#define NV_SOE_RISCV_CG_SLCG__PROD 3 /* */ +#define NV_SOE_RISCV_CG_SLCG_EXT 0:0 /* RWIVF */ +#define NV_SOE_RISCV_CG_SLCG_EXT_DISABLED 0x00000000 /* RWI-V */ +#define NV_SOE_RISCV_CG_SLCG_EXT_ENABLED 0x00000001 /* RW--V */ +#define NV_SOE_RISCV_CG_SLCG_CORE 1:1 /* RWIVF */ +#define NV_SOE_RISCV_CG_SLCG_CORE_DISABLED 0x00000000 /* RWI-V */ +#define NV_SOE_RISCV_CG_SLCG_CORE_ENABLED 0x00000001 /* RW--V */ +#define NV_SOE_RISCV_CG_RSVD 31:2 /* R-IVF */ +#define NV_SOE_RISCV_CG_RSVD_INIT 0x00000000 /* R-I-V */ +#define NV_SOE_RISCV_CG_CORE_SLCG 1:1 /* */ +#define NV_SOE_RISCV_CG_SLCG_DISABLE 0 /* */ +#define NV_SOE_RISCV_CG_SLCG_ENABLE 1 /* */ +#define NV_SOE_RISCV_CG_CORE_SLCG_DISABLE 0 /* */ +#define NV_SOE_RISCV_CG_CORE_SLCG_ENABLE 1 /* */ +#define NV_SOE_PRIV_BLOCKER_CTRL_CG1 0x0e28 /* RW-4R */ +#define NV_SOE_PRIV_BLOCKER_CTRL_CG1_SLCG 0:0 /* RWIVF */ +#define NV_SOE_PRIV_BLOCKER_CTRL_CG1_SLCG_DISABLED 0x00000001 /* RWI-V */ +#define NV_SOE_PRIV_BLOCKER_CTRL_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ +#define NV_SOE_PRIV_BLOCKER_CTRL_CG1_SLCG__PROD 0x00000000 /* RW--V */ +#define NV_SOE_BAR0_TMOUT 0x070c /* RW-4R */ +#define NV_SOE_BAR0_TMOUT_CYCLES 31:0 /* RWIVF */ +#define NV_SOE_BAR0_TMOUT_CYCLES_INIT 0x01f2a737 /* RWI-V */ +#define NV_SOE_BAR0_TMOUT_CYCLES__PROD 0x01f2a737 /* RW--V */ +#define NV_SOE_MISC_CG1 0x083c /* RW-4R */ +#define NV_SOE_MISC_CG1_SLCG 31:0 /* RWIVF */ +#define NV_SOE_MISC_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ +#define NV_SOE_MISC_CG1_SLCG_DISABLED 0x8000003d /* RWI-V */ +#define NV_SOE_MISC_CG1_SLCG__PROD 0x0000003c /* RW--V */ +#define NV_SOE_MISC_CG1_SLCG_FALCON 0:0 /* */ +#define NV_SOE_MISC_CG1_SLCG_FALCON_ENABLED 0 /* */ +#define NV_SOE_MISC_CG1_SLCG_FALCON_DISABLED 1 /* */ +#define NV_SOE_MISC_CG1_SLCG_SCP 2:2 /* */ +#define NV_SOE_MISC_CG1_SLCG_SCP_ENABLED 0 /* */ +#define NV_SOE_MISC_CG1_SLCG_SCP_DISABLED 1 /* */ +#define NV_SOE_MISC_CG1_SLCG_CSBMASTER 3:3 /* */ +#define NV_SOE_MISC_CG1_SLCG_CSBMASTER_ENABLED 0 /* */ +#define NV_SOE_MISC_CG1_SLCG_CSBMASTER_DISABLED 1 /* */ +#define NV_SOE_MISC_CG1_SLCG_BAR0 4:4 /* */ +#define NV_SOE_MISC_CG1_SLCG_BAR0_ENABLED 0 /* */ +#define NV_SOE_MISC_CG1_SLCG_BAR0_DISABLED 1 /* */ +#define NV_SOE_MISC_CG1_SLCG_MISC 5:5 /* */ +#define NV_SOE_MISC_CG1_SLCG_MISC_ENABLED 0 /* */ +#define NV_SOE_MISC_CG1_SLCG_MISC_DISABLED 1 /* */ +#define NV_SOE_MISC_CG1_SLCG_TOP 31:31 /* */ +#define NV_SOE_MISC_CG1_SLCG_TOP_ENABLED 0x00000000 /* */ +#define NV_SOE_MISC_CG1_SLCG_TOP_DISABLED 0x00000001 /* */ +#define NV_SOE_MISC_TOP_CG 0x0840 /* RW-4R */ +#define NV_SOE_MISC_TOP_CG_IDLE_CG_DLY_CNT 5:0 /* RWIVF */ +#define NV_SOE_MISC_TOP_CG_IDLE_CG_DLY_CNT_INIT 0x0000001f /* RWI-V */ +#endif // __ls10_dev_soe_ip_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_soe_ip_addendum.h b/src/common/inc/swref/published/nvswitch/ls10/dev_soe_ip_addendum.h new file mode 100644 index 000000000..b009657db --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_soe_ip_addendum.h @@ -0,0 +1,60 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_soe_ip_addendum_h__ +#define __ls10_dev_soe_ip_addendum_h__ + +#define NV_SOE_MUTEX_DEFINES \ + NV_MUTEX_ID_SOE_EMEM_ACCESS, \ + +#define NV_SOE_EMEM_ACCESS_PORT_NVSWITCH (0) +#define NV_SOE_EMEM_ACCESS_PORT_NVWATCH (1) +#define UNUSED_EMEM_ACCESS_PORT_2 (2) +#define UNUSED_EMEM_ACCESS_PORT_3 (3) + +#define NUM_SAW_ENGINE 1 +#define NUM_NVLINK_ENGINE 9 + +#define NUM_TLC_ENGINE 64 +#define NUM_NVLIPT_LNK_ENGINE 64 + +#define NUM_NPG_ENGINE 16 +#define NUM_NPG_BCAST_ENGINE 1 +#define NUM_NPORT_ENGINE 64 +#define NUM_NPORT_MULTICAST_BCAST_ENGINE 1 +#define NUM_NXBAR_ENGINE 3 +#define NUM_NXBAR_BCAST_ENGINE 1 +#define NUM_TILE_ENGINE 36 +#define NUM_TILE_MULTICAST_BCAST_ENGINE 1 +#define NUM_NVLW_ENGINE 16 +#define NUM_BUS_ENGINE 1 +#define NUM_GIN_ENGINE 1 +#define NUM_MINION_ENGINE NUM_NVLW_ENGINE +#define NUM_MINION_BCAST_ENGINE 1 +#define NUM_NVLIPT_ENGINE NUM_NVLW_ENGINE +#define NUM_NVLIPT_BCAST_ENGINE 1 +#define NUM_SYS_PRI_HUB 1 +#define NUM_PRI_MASTER_RS 1 +#define NUM_LINKS_PER_MINION (NUM_NPORT_ENGINE / NUM_MINION_ENGINE) + +#endif // __ls10_dev_soe_ip_addendum_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_sourcetrack_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_sourcetrack_ip.h new file mode 100644 index 000000000..8ba52e3d4 --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_sourcetrack_ip.h @@ -0,0 +1,217 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_sourcetrack_ip_h__ +#define __ls10_dev_sourcetrack_ip_h__ +/* This file is autogenerated. Do not edit */ +#define NV_SOURCETRACK 0x00006fff:0x00006000 /* RW--D */ +#define NV_SOURCETRACK_CTRL 0x00006040 /* RW-4R */ +#define NV_SOURCETRACK_CTRL_COL_RSP_DIS 0:0 /* RWEVF */ +#define NV_SOURCETRACK_CTRL_COL_RSP_DIS_DISABLED 0x00000000 /* RWE-V */ +#define NV_SOURCETRACK_CTRL_COL_RSP_DIS_ENABLED 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_CTRL_STO_ENB 9:9 /* RWEVF */ +#define NV_SOURCETRACK_CTRL_STO_ENB_ENABLED 0x00000001 /* RWE-V */ +#define NV_SOURCETRACK_CTRL_STO_ENB_DISABLED 0x00000000 /* RW--V */ +#define NV_SOURCETRACK_MULTISEC_TIMER0 0x00006044 /* RW-4R */ +#define NV_SOURCETRACK_MULTISEC_TIMER0_TIMERVAL0 19:0 /* RWEVF */ +#define NV_SOURCETRACK_MULTISEC_TIMER0_TIMERVAL0_INIT 0x00003e80 /* RWE-V */ +#define NV_SOURCETRACK_ERR_STATUS_0 0x00006400 /* RW-4R */ +#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR 0:0 /* RWDVF */ +#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR 1:1 /* RWDVF */ +#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_STATUS_0_DUP_CREQ_TCEN0_TAG_ERR 2:2 /* RWDVF */ +#define NV_SOURCETRACK_ERR_STATUS_0_DUP_CREQ_TCEN0_TAG_ERR__ONWRITE "oneToClear" /* */ +#define NV_SOURCETRACK_ERR_STATUS_0_DUP_CREQ_TCEN0_TAG_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_SOURCETRACK_ERR_STATUS_0_DUP_CREQ_TCEN0_TAG_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_STATUS_0_INVALID_TCEN0_RSP_ERR 3:3 /* RWDVF */ +#define NV_SOURCETRACK_ERR_STATUS_0_INVALID_TCEN0_RSP_ERR__ONWRITE "oneToClear" /* */ +#define NV_SOURCETRACK_ERR_STATUS_0_INVALID_TCEN0_RSP_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_SOURCETRACK_ERR_STATUS_0_INVALID_TCEN0_RSP_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_STATUS_0_INVALID_TCEN1_RSP_ERR 4:4 /* RWDVF */ +#define NV_SOURCETRACK_ERR_STATUS_0_INVALID_TCEN1_RSP_ERR__ONWRITE "oneToClear" /* */ +#define NV_SOURCETRACK_ERR_STATUS_0_INVALID_TCEN1_RSP_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_SOURCETRACK_ERR_STATUS_0_INVALID_TCEN1_RSP_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_STATUS_0_SOURCETRACK_TIME_OUT_ERR 5:5 /* RWDVF */ +#define NV_SOURCETRACK_ERR_STATUS_0_SOURCETRACK_TIME_OUT_ERR__ONWRITE "oneToClear" /* */ +#define NV_SOURCETRACK_ERR_STATUS_0_SOURCETRACK_TIME_OUT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_SOURCETRACK_ERR_STATUS_0_SOURCETRACK_TIME_OUT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_LOG_EN_0 0x00006404 /* RW-4R */ +#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR 0:0 /* RWEVF */ +#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR 1:1 /* RWEVF */ +#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_LOG_EN_0_DUP_CREQ_TCEN0_TAG_ERR 2:2 /* RWEVF */ +#define NV_SOURCETRACK_ERR_LOG_EN_0_DUP_CREQ_TCEN0_TAG_ERR__PROD 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_LOG_EN_0_DUP_CREQ_TCEN0_TAG_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_SOURCETRACK_ERR_LOG_EN_0_DUP_CREQ_TCEN0_TAG_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_SOURCETRACK_ERR_LOG_EN_0_DUP_CREQ_TCEN0_TAG_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_LOG_EN_0_INVALID_TCEN0_RSP_ERR 3:3 /* RWEVF */ +#define NV_SOURCETRACK_ERR_LOG_EN_0_INVALID_TCEN0_RSP_ERR__PROD 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_LOG_EN_0_INVALID_TCEN0_RSP_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_SOURCETRACK_ERR_LOG_EN_0_INVALID_TCEN0_RSP_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_SOURCETRACK_ERR_LOG_EN_0_INVALID_TCEN0_RSP_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_LOG_EN_0_INVALID_TCEN1_RSP_ERR 4:4 /* RWEVF */ +#define NV_SOURCETRACK_ERR_LOG_EN_0_INVALID_TCEN1_RSP_ERR__PROD 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_LOG_EN_0_INVALID_TCEN1_RSP_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_SOURCETRACK_ERR_LOG_EN_0_INVALID_TCEN1_RSP_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_SOURCETRACK_ERR_LOG_EN_0_INVALID_TCEN1_RSP_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_LOG_EN_0_SOURCETRACK_TIME_OUT_ERR 5:5 /* RWEVF */ +#define NV_SOURCETRACK_ERR_LOG_EN_0_SOURCETRACK_TIME_OUT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_LOG_EN_0_SOURCETRACK_TIME_OUT_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_SOURCETRACK_ERR_LOG_EN_0_SOURCETRACK_TIME_OUT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_SOURCETRACK_ERR_LOG_EN_0_SOURCETRACK_TIME_OUT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0 0x00006408 /* RW-4R */ +#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR 0:0 /* RWEVF */ +#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR 1:1 /* RWEVF */ +#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_DUP_CREQ_TCEN0_TAG_ERR 2:2 /* RWEVF */ +#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_DUP_CREQ_TCEN0_TAG_ERR__PROD 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_DUP_CREQ_TCEN0_TAG_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_DUP_CREQ_TCEN0_TAG_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_DUP_CREQ_TCEN0_TAG_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_INVALID_TCEN0_RSP_ERR 3:3 /* RWEVF */ +#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_INVALID_TCEN0_RSP_ERR__PROD 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_INVALID_TCEN0_RSP_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_INVALID_TCEN0_RSP_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_INVALID_TCEN0_RSP_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_INVALID_TCEN1_RSP_ERR 4:4 /* RWEVF */ +#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_INVALID_TCEN1_RSP_ERR__PROD 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_INVALID_TCEN1_RSP_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_INVALID_TCEN1_RSP_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_INVALID_TCEN1_RSP_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_SOURCETRACK_TIME_OUT_ERR 5:5 /* RWEVF */ +#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_SOURCETRACK_TIME_OUT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_SOURCETRACK_TIME_OUT_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_SOURCETRACK_TIME_OUT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_SOURCETRACK_TIME_OUT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0 0x0000640c /* RW-4R */ +#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR 0:0 /* RWEVF */ +#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR 1:1 /* RWEVF */ +#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_DUP_CREQ_TCEN0_TAG_ERR 2:2 /* RWEVF */ +#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_DUP_CREQ_TCEN0_TAG_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_DUP_CREQ_TCEN0_TAG_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_INVALID_TCEN0_RSP_ERR 3:3 /* RWEVF */ +#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_INVALID_TCEN0_RSP_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_INVALID_TCEN0_RSP_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_INVALID_TCEN1_RSP_ERR 4:4 /* RWEVF */ +#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_INVALID_TCEN1_RSP_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_INVALID_TCEN1_RSP_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_SOURCETRACK_TIME_OUT_ERR 5:5 /* RWEVF */ +#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_SOURCETRACK_TIME_OUT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_SOURCETRACK_TIME_OUT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_CORRECTABLE_REPORT_EN_0 0x00006410 /* RW-4R */ +#define NV_SOURCETRACK_ERR_CONTAIN_EN_0 0x00006414 /* RW-4R */ +#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR 0:0 /* RWEVF */ +#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR 1:1 /* RWEVF */ +#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_DUP_CREQ_TCEN0_TAG_ERR 2:2 /* RWEVF */ +#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_DUP_CREQ_TCEN0_TAG_ERR__PROD 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_DUP_CREQ_TCEN0_TAG_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_DUP_CREQ_TCEN0_TAG_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_DUP_CREQ_TCEN0_TAG_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_INVALID_TCEN0_RSP_ERR 3:3 /* RWEVF */ +#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_INVALID_TCEN0_RSP_ERR__PROD 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_INVALID_TCEN0_RSP_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_INVALID_TCEN0_RSP_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_INVALID_TCEN0_RSP_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_INVALID_TCEN1_RSP_ERR 4:4 /* RWEVF */ +#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_INVALID_TCEN1_RSP_ERR__PROD 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_INVALID_TCEN1_RSP_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_INVALID_TCEN1_RSP_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_INVALID_TCEN1_RSP_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_SOURCETRACK_TIME_OUT_ERR 5:5 /* RWEVF */ +#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_SOURCETRACK_TIME_OUT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_SOURCETRACK_TIME_OUT_ERR__TPROD 0x00000000 /* RW--V */ +#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_SOURCETRACK_TIME_OUT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_SOURCETRACK_TIME_OUT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_FIRST_0 0x0000641c /* RW-4R */ +#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR 0:0 /* RWDVF */ +#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR 1:1 /* RWDVF */ +#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_FIRST_0_DUP_CREQ_TCEN0_TAG_ERR 2:2 /* RWDVF */ +#define NV_SOURCETRACK_ERR_FIRST_0_DUP_CREQ_TCEN0_TAG_ERR__ONWRITE "oneToClear" /* */ +#define NV_SOURCETRACK_ERR_FIRST_0_DUP_CREQ_TCEN0_TAG_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_SOURCETRACK_ERR_FIRST_0_DUP_CREQ_TCEN0_TAG_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_FIRST_0_INVALID_TCEN0_RSP_ERR 3:3 /* RWDVF */ +#define NV_SOURCETRACK_ERR_FIRST_0_INVALID_TCEN0_RSP_ERR__ONWRITE "oneToClear" /* */ +#define NV_SOURCETRACK_ERR_FIRST_0_INVALID_TCEN0_RSP_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_SOURCETRACK_ERR_FIRST_0_INVALID_TCEN0_RSP_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_FIRST_0_INVALID_TCEN1_RSP_ERR 4:4 /* RWDVF */ +#define NV_SOURCETRACK_ERR_FIRST_0_INVALID_TCEN1_RSP_ERR__ONWRITE "oneToClear" /* */ +#define NV_SOURCETRACK_ERR_FIRST_0_INVALID_TCEN1_RSP_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_SOURCETRACK_ERR_FIRST_0_INVALID_TCEN1_RSP_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_FIRST_0_SOURCETRACK_TIME_OUT_ERR 5:5 /* RWDVF */ +#define NV_SOURCETRACK_ERR_FIRST_0_SOURCETRACK_TIME_OUT_ERR__ONWRITE "oneToClear" /* */ +#define NV_SOURCETRACK_ERR_FIRST_0_SOURCETRACK_TIME_OUT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_SOURCETRACK_ERR_FIRST_0_SOURCETRACK_TIME_OUT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_ECC_CTRL 0x00006470 /* RW-4R */ +#define NV_SOURCETRACK_ERR_ECC_CTRL_CREQ_TCEN0_CRUMBSTORE_ECC_ENABLE 0:0 /* RWEVF */ +#define NV_SOURCETRACK_ERR_ECC_CTRL_CREQ_TCEN0_CRUMBSTORE_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_ECC_CTRL_CREQ_TCEN0_CRUMBSTORE_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_SOURCETRACK_ERR_ECC_CTRL_CREQ_TCEN0_CRUMBSTORE_ECC_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_COUNTER 0x00006480 /* RW-4R */ +#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */ +#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */ +#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT 0x00006484 /* RW-4R */ +#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */ +#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */ +#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_ADDRESS 0x00006488 /* R--4R */ +#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_ADDRESS_ERROR_ADDRESS 9:0 /* R-DVF */ +#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */ +#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID 0x0000648c /* R--4R */ +#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */ +#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */ +#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */ +#endif // __ls10_dev_sourcetrack_ip_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_therm.h b/src/common/inc/swref/published/nvswitch/ls10/dev_therm.h new file mode 100644 index 000000000..2b73655c3 --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_therm.h @@ -0,0 +1,183 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_therm_h__ +#define __ls10_dev_therm_h__ +/* This file is autogenerated. Do not edit */ +#define NV_THERM 0x067fff:0x066000 /* RW--D */ +#define NV_THERM_I2CS_SCRATCH 0x000660bc /* RW-4R */ +#define NV_THERM_I2CS_SCRATCH_DATA 31:0 /* RWIVF */ +#define NV_THERM_I2CS_SCRATCH_DATA_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_0 0x00066f10 /* RW-4R */ +#define NV_THERM_TSENSE_U2_A_0_BJT_0_TEMPERATURE 13:0 /* R-IVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_0_TEMPERATURE_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_0_SOURCE 16:16 /* R-IVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_0_SOURCE_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_0_TEMPERATURE_VALID 30:30 /* R-IVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_0_TEMPERATURE_VALID_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_0_TEMPERATURE_EN 31:31 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_0_TEMPERATURE_EN_INIT 0x00000001 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_1 0x00066f14 /* RW-4R */ +#define NV_THERM_TSENSE_U2_A_0_BJT_1_TEMPERATURE 13:0 /* R-IVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_1_TEMPERATURE_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_1_SOURCE 16:16 /* R-IVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_1_SOURCE_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_1_TEMPERATURE_VALID 30:30 /* R-IVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_1_TEMPERATURE_VALID_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_1_TEMPERATURE_EN 31:31 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_1_TEMPERATURE_EN_INIT 0x00000001 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_2 0x00066f18 /* RW-4R */ +#define NV_THERM_TSENSE_U2_A_0_BJT_2_TEMPERATURE 13:0 /* R-IVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_2_TEMPERATURE_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_2_SOURCE 16:16 /* R-IVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_2_SOURCE_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_2_TEMPERATURE_VALID 30:30 /* R-IVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_2_TEMPERATURE_VALID_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_2_TEMPERATURE_EN 31:31 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_2_TEMPERATURE_EN_INIT 0x00000001 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_3 0x00066f1c /* RW-4R */ +#define NV_THERM_TSENSE_U2_A_0_BJT_3_TEMPERATURE 13:0 /* R-IVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_3_TEMPERATURE_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_3_SOURCE 16:16 /* R-IVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_3_SOURCE_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_3_TEMPERATURE_VALID 30:30 /* R-IVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_3_TEMPERATURE_VALID_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_3_TEMPERATURE_EN 31:31 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_3_TEMPERATURE_EN_INIT 0x00000001 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_4 0x00066f20 /* RW-4R */ +#define NV_THERM_TSENSE_U2_A_0_BJT_4_TEMPERATURE 13:0 /* R-IVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_4_TEMPERATURE_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_4_SOURCE 16:16 /* R-IVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_4_SOURCE_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_4_TEMPERATURE_VALID 30:30 /* R-IVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_4_TEMPERATURE_VALID_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_4_TEMPERATURE_EN 31:31 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_4_TEMPERATURE_EN_INIT 0x00000001 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_5 0x00066f24 /* RW-4R */ +#define NV_THERM_TSENSE_U2_A_0_BJT_5_TEMPERATURE 13:0 /* R-IVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_5_TEMPERATURE_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_5_SOURCE 16:16 /* R-IVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_5_SOURCE_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_5_TEMPERATURE_VALID 30:30 /* R-IVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_5_TEMPERATURE_VALID_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_5_TEMPERATURE_EN 31:31 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_5_TEMPERATURE_EN_INIT 0x00000001 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_0_TEMPERATURE_MODIFICATIONS 0x00066f28 /* RW-4R */ +#define NV_THERM_TSENSE_U2_A_0_BJT_0_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET 13:0 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_0_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_0_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE 29:16 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_0_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_0_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN 31:31 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_0_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_1_TEMPERATURE_MODIFICATIONS 0x00066f2c /* RW-4R */ +#define NV_THERM_TSENSE_U2_A_0_BJT_1_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET 13:0 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_1_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_1_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE 29:16 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_1_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_1_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN 31:31 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_1_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_2_TEMPERATURE_MODIFICATIONS 0x00066f30 /* RW-4R */ +#define NV_THERM_TSENSE_U2_A_0_BJT_2_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET 13:0 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_2_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_2_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE 29:16 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_2_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_2_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN 31:31 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_2_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_3_TEMPERATURE_MODIFICATIONS 0x00066f34 /* RW-4R */ +#define NV_THERM_TSENSE_U2_A_0_BJT_3_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET 13:0 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_3_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_3_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE 29:16 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_3_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_3_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN 31:31 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_3_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_4_TEMPERATURE_MODIFICATIONS 0x00066f38 /* RW-4R */ +#define NV_THERM_TSENSE_U2_A_0_BJT_4_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET 13:0 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_4_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_4_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE 29:16 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_4_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_4_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN 31:31 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_4_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_5_TEMPERATURE_MODIFICATIONS 0x00066f3c /* RW-4R */ +#define NV_THERM_TSENSE_U2_A_0_BJT_5_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET 13:0 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_5_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_5_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE 29:16 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_5_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_5_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN 31:31 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_5_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_MAXIMUM_TEMPERATURE 0x00066f40 /* R--4R */ +#define NV_THERM_TSENSE_MAXIMUM_TEMPERATURE_MAXIMUM_TEMPERATURE 13:0 /* R--VF */ +#define NV_THERM_TSENSE_MAXIMUM_TEMPERATURE_MAX_TEMP_SENSE_NUMBER 24:16 /* R--VF */ +#define NV_THERM_TSENSE_THRESHOLD_TEMPERATURES 0x00066f44 /* RW-4R */ +#define NV_THERM_TSENSE_THRESHOLD_TEMPERATURES_WARNING_TEMPERATURE 13:0 /* RWIVF */ +#define NV_THERM_TSENSE_THRESHOLD_TEMPERATURES_WARNING_TEMPERATURE_INIT 0x00000c80 /* RWI-V */ +#define NV_THERM_TSENSE_THRESHOLD_TEMPERATURES_OVERTEMP_TEMPERATURE 29:16 /* RWIVF */ +#define NV_THERM_TSENSE_THRESHOLD_TEMPERATURES_OVERTEMP_TEMPERATURE_INIT 0x00000dc0 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_6 0x00066fa0 /* RW-4R */ +#define NV_THERM_TSENSE_U2_A_0_BJT_6_TEMPERATURE 13:0 /* R-IVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_6_TEMPERATURE_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_6_SOURCE 16:16 /* R-IVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_6_SOURCE_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_6_TEMPERATURE_VALID 30:30 /* R-IVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_6_TEMPERATURE_VALID_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_6_TEMPERATURE_EN 31:31 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_6_TEMPERATURE_EN_INIT 0x00000001 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_7 0x00066fa4 /* RW-4R */ +#define NV_THERM_TSENSE_U2_A_0_BJT_7_TEMPERATURE 13:0 /* R-IVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_7_TEMPERATURE_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_7_SOURCE 16:16 /* R-IVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_7_SOURCE_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_7_TEMPERATURE_VALID 30:30 /* R-IVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_7_TEMPERATURE_VALID_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_7_TEMPERATURE_EN 31:31 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_7_TEMPERATURE_EN_INIT 0x00000001 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_8 0x00066fa8 /* RW-4R */ +#define NV_THERM_TSENSE_U2_A_0_BJT_8_TEMPERATURE 13:0 /* R-IVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_8_TEMPERATURE_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_8_SOURCE 16:16 /* R-IVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_8_SOURCE_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_8_TEMPERATURE_VALID 30:30 /* R-IVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_8_TEMPERATURE_VALID_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_8_TEMPERATURE_EN 31:31 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_8_TEMPERATURE_EN_INIT 0x00000001 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_6_TEMPERATURE_MODIFICATIONS 0x00066fb0 /* RW-4R */ +#define NV_THERM_TSENSE_U2_A_0_BJT_6_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET 13:0 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_6_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_6_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE 29:16 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_6_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_6_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN 31:31 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_6_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_7_TEMPERATURE_MODIFICATIONS 0x00066fb4 /* RW-4R */ +#define NV_THERM_TSENSE_U2_A_0_BJT_7_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET 13:0 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_7_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_7_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE 29:16 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_7_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_7_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN 31:31 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_7_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_8_TEMPERATURE_MODIFICATIONS 0x00066fb8 /* RW-4R */ +#define NV_THERM_TSENSE_U2_A_0_BJT_8_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET 13:0 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_8_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_8_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE 29:16 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_8_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_TSENSE_U2_A_0_BJT_8_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN 31:31 /* RWIVF */ +#define NV_THERM_TSENSE_U2_A_0_BJT_8_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN_INIT 0x00000000 /* RWI-V */ +#endif // __ls10_dev_therm_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_timer_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_timer_ip.h new file mode 100644 index 000000000..af31411c3 --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_timer_ip.h @@ -0,0 +1,37 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_timer_ip_h__ +#define __ls10_dev_timer_ip_h__ +/* This file is autogenerated. Do not edit */ +#define NV_PTIMER 0x00000FFF:0x00000000 /* RW--D */ +#define NV_PTIMER_PRI_TMR_CG1 0x00000600 /* RW-4R */ +#define NV_PTIMER_PRI_TMR_CG1_MONITOR_CG_EN 0:0 /* RWIVF */ +#define NV_PTIMER_PRI_TMR_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ +#define NV_PTIMER_PRI_TMR_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWI-V */ +#define NV_PTIMER_PRI_TMR_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ +#define NV_PTIMER_PRI_TMR_CG1_SLCG 1:1 /* RWIVF */ +#define NV_PTIMER_PRI_TMR_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ +#define NV_PTIMER_PRI_TMR_CG1_SLCG_DISABLED 0x00000001 /* RWI-V */ +#define NV_PTIMER_PRI_TMR_CG1_SLCG__PROD 0x00000000 /* RW--V */ +#endif // __ls10_dev_timer_ip_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_trim.h b/src/common/inc/swref/published/nvswitch/ls10/dev_trim.h new file mode 100644 index 000000000..2ca0987fa --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_trim.h @@ -0,0 +1,213 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_trim_h__ +#define __ls10_dev_trim_h__ +/* This file is autogenerated. Do not edit */ +#define NV_CLOCK_NVSW_SYS 0x00001FFF:0x00000000 /* RW--D */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER 0x00000080 /* RW-4R */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL 5:0 /* RWEUF */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY1 0x00000000 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY2 0x00000002 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY3 0x00000004 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY4 0x00000006 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY5 0x00000008 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY6 0x0000000A /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY7 0x0000000C /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY8 0x0000000E /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY9 0x00000010 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY10 0x00000012 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY11 0x00000014 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY12 0x00000016 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY13 0x00000018 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY14 0x0000001A /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY15 0x0000001C /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY16 0x0000001E /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY17 0x00000020 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY18 0x00000022 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY19 0x00000024 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY20 0x00000026 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY21 0x00000028 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY22 0x0000002A /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY23 0x0000002C /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY24 0x0000002E /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY25 0x00000030 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY26 0x00000032 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY27 0x00000034 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY28 0x00000036 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY29 0x00000038 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY30 0x0000003A /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY31 0x0000003C /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DIVIDER_SEL_INIT 0x00000002 /* RWE-V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_ASYNC_MODE 11:8 /* RWEUF */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_ASYNC_MODE_INIT 0x00000000 /* RWE-V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL 15:12 /* RWEUF */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_PEX_REFCLK 0x00000001 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_PEX_REFCLK_1 0x00000002 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_PEX_REFCLK_2 0x00000004 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_SWITCHPLL 0x00000008 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_INIT 0x00000001 /* RWE-V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_GATE_CLOCK 16:16 /* RWEUF */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_GATE_CLOCK_INIT 0x00000000 /* RWE-V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_GATE_CLOCK_GATED 0x00000001 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_BYPASS_FSM 17:17 /* RWEUF */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_BYPASS_FSM_INIT 0x00000000 /* RWE-V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_BYPASS_FSM_BYPASSED 0x00000001 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_SWITCH_STATUS 21:18 /* R--UF */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_SWITCH_DIVIDER_DONE 22:22 /* R--UF */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_STATUS_DONE_2 23:23 /* R--UF */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_STATUS_DONE_3 24:24 /* R--UF */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_DEBUG_OUT_STATE 27:25 /* R--UF */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_SPARE 30:28 /* RWEUF */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_SPARE_INIT 0x00000000 /* RWE-V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_SW_FSM_EN 31:31 /* RWEUF */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_SW_FSM_EN_INIT 0x00000000 /* RWE-V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_SW_FSM_EN_ASSERT 0x00000001 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHCLK_SWITCH_DIVIDER_SW_FSM_EN_DEASSERT 0x00000000 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER 0x00000088 /* RW-4R */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL 5:0 /* RWEUF */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY1 0x00000000 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY2 0x00000002 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY3 0x00000004 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY4 0x00000006 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY5 0x00000008 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY6 0x0000000A /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY7 0x0000000C /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY8 0x0000000E /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY9 0x00000010 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY10 0x00000012 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY11 0x00000014 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY12 0x00000016 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY13 0x00000018 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY14 0x0000001A /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY15 0x0000001C /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY16 0x0000001E /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY17 0x00000020 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY18 0x00000022 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY19 0x00000024 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY20 0x00000026 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY21 0x00000028 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY22 0x0000002A /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY23 0x0000002C /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY24 0x0000002E /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY25 0x00000030 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY26 0x00000032 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY27 0x00000034 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY28 0x00000036 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY29 0x00000038 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY30 0x0000003A /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY31 0x0000003C /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DIVIDER_SEL_INIT 0x00000004 /* RWE-V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_ASYNC_MODE 11:8 /* RWEUF */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_ASYNC_MODE_INIT 0x00000000 /* RWE-V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL 15:12 /* RWEUF */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_PEX_REFCLK 0x00000001 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_PEX_REFCLK_1 0x00000002 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_PEX_REFCLK_2 0x00000004 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_SWITCHPLL 0x00000008 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_INIT 0x00000001 /* RWE-V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_GATE_CLOCK 16:16 /* RWEUF */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_GATE_CLOCK_INIT 0x00000000 /* RWE-V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_GATE_CLOCK_GATED 0x00000001 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_BYPASS_FSM 17:17 /* RWEUF */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_BYPASS_FSM_INIT 0x00000000 /* RWE-V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_BYPASS_FSM_BYPASSED 0x00000001 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_SWITCH_STATUS 21:18 /* R--UF */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_SWITCH_DIVIDER_DONE 22:22 /* R--UF */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_STATUS_DONE_2 23:23 /* R--UF */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_STATUS_DONE_3 24:24 /* R--UF */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_DEBUG_OUT_STATE 27:25 /* R--UF */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_SPARE 30:28 /* RWEUF */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_SPARE_INIT 0x00000000 /* RWE-V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_SW_FSM_EN 31:31 /* RWEUF */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_SW_FSM_EN_INIT 0x00000000 /* RWE-V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_SW_FSM_EN_ASSERT 0x00000001 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SYSTEM_CLK_SWITCH_DIVIDER_SW_FSM_EN_DEASSERT 0x00000000 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_RX_BYPASS_REFCLK 0x000000C4 /* RW-4R */ +#define NV_CLOCK_NVSW_SYS_RX_BYPASS_REFCLK_DISABLE 0:0 /* RWEUF */ +#define NV_CLOCK_NVSW_SYS_RX_BYPASS_REFCLK_DISABLE_INIT 0x00000001 /* RWE-V */ +#define NV_CLOCK_NVSW_SYS_RX_BYPASS_REFCLK_DIV 13:4 /* RWEUF */ +#define NV_CLOCK_NVSW_SYS_RX_BYPASS_REFCLK_DIV_INIT 0x0000000C /* RWE-V */ +#define NV_CLOCK_NVSW_SYS_RX_BYPASS_REFCLK_REFCLK_BUF_EN_CYA 14:14 /* RWEUF */ +#define NV_CLOCK_NVSW_SYS_RX_BYPASS_REFCLK_REFCLK_BUF_EN_CYA_INIT 0x00000000 /* RWE-V */ +#define NV_CLOCK_NVSW_SYS_RX_BYPASS_REFCLK_REFCLK_BUF_EN_OVERRIDE 15:15 /* RWEUF */ +#define NV_CLOCK_NVSW_SYS_RX_BYPASS_REFCLK_REFCLK_BUF_EN_OVERRIDE_INIT 0x00000000 /* RWE-V */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG 0x00000100 /* RW-4R */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_ENABLE 0:0 /* RWEUF */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_ENABLE_INIT 0x00000000 /* RWE-V */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_ENABLE_NO 0x00000000 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_ENABLE_YES 0x00000001 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_IDDQ 1:1 /* RWEUF */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_IDDQ_INIT 0x00000001 /* RWE-V */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_IDDQ_POWER_ON 0x00000000 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_IDDQ_POWER_OFF 0x00000001 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_EN_LCKDET 4:4 /* RWEUF */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_EN_LCKDET_INIT 0x00000001 /* RWE-V */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_EN_LCKDET_POWER_ON 0x00000001 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_EN_LCKDET_POWER_OFF 0x00000000 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_LOCK_OVERRIDE 5:5 /* RWEUF */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_LOCK_OVERRIDE_INIT 0x00000000 /* RWE-V */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_LOCK_OVERRIDE_DISABLE 0x00000000 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_LOCK_OVERRIDE_ENABLE 0x00000001 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_PLL_LOCK 17:17 /* R--UF */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_PLL_LOCK_FALSE 0x00000000 /* R---V */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_PLL_LOCK_TRUE 0x00000001 /* R---V */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_BYPASSPLL_CYA 21:21 /* RWEUF */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_BYPASSPLL_CYA_INIT 0x00000000 /* RWE-V */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_SEL_TESTOUT 28:26 /* RWEUF */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CFG_SEL_TESTOUT_INIT 0x00000000 /* RWE-V */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF 0x00000104 /* RW-4R */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_MDIV 7:0 /* RWEUF */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_MDIV_MIN 0x00000001 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_MDIV_MAX 0x000000FF /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_MDIV_INIT 0x00000005 /* RWE-V */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_NDIV 15:8 /* RWEUF */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_NDIV_MIN 0x00000008 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_NDIV_MAX 0x000000FF /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_NDIV_INIT 0x00000085 /* RWE-V */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_PLDIV 21:16 /* RWEUF */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_PLDIV_INIT 0x00000001 /* RWE-V */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_PLDIV_MIN 0x00000001 /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_PLDIV_MAX 0x0000001F /* RW--V */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CTRL 0x00000108 /* RW-4R */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CTRL_KCP 19:18 /* RWEUF */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CTRL_KCP_INIT 0x00000000 /* RWE-V */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CTRL_KVCO 22:20 /* RWEUF */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CTRL_KVCO_INIT 0x00000000 /* RWE-V */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_CTRL_PLL_FREQLOCK 28:28 /* R--UF */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_SECURE_0 0x00000118 /* RW-4R */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_SECURE_0_VREG_CTRL 1:0 /* RWEUF */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_SECURE_0_VREG_CTRL_INIT 0x00000000 /* RWE-V */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_SECURE_0_VREG_CTRL_1V0 0x00000000 /* R---V */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_SECURE_0_VREG_CTRL_1V05 0x00000001 /* R---V */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_SECURE_0_VREG_CTRL_1V1 0x00000002 /* R---V */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_SECURE_0_VREG_CTRL_0V95 0x00000003 /* R---V */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_SECURE 0x0000011c /* RW-4R */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_SECURE_SETUP 31:0 /* RWEUF */ +#define NV_CLOCK_NVSW_SYS_SWITCHPLL_SECURE_SETUP_INIT 0x00000000 /* RWE-V */ +#define NV_CLOCK_NVSW_PRT_NVLINK_UPHY0_PLL0_SLCG 0x00000330 /* RW-4R */ +#define NV_CLOCK_NVSW_PRT_NVLINK_UPHY0_PLL0_SLCG_CFGSM 1:1 /* RWEVF */ +#define NV_CLOCK_NVSW_PRT_NVLINK_UPHY0_PLL0_SLCG_CFGSM_ENABLED 0x00000000 /* RW--V */ +#define NV_CLOCK_NVSW_PRT_NVLINK_UPHY0_PLL0_SLCG_CFGSM_DISABLED 0x00000001 /* RWE-V */ +#define NV_CLOCK_NVSW_PRT_NVLINK_UPHY0_PLL0_SLCG_CFGSM__PROD 0x00000000 /* RW--V */ +#endif // __ls10_dev_trim_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_tstate_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_tstate_ip.h new file mode 100644 index 000000000..1ed7e2237 --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_tstate_ip.h @@ -0,0 +1,274 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_tstate_ip_h__ +#define __ls10_dev_tstate_ip_h__ +/* This file is autogenerated. Do not edit */ +#define NV_TSTATE 0x00003fff:0x00003000 /* RW--D */ +#define NV_TSTATE_TAGSTATECONTROL 0x00003040 /* RW-4R */ +#define NV_TSTATE_TAGSTATECONTROL_ATO_ENB 9:9 /* RWEVF */ +#define NV_TSTATE_TAGSTATECONTROL_ATO_ENB_ON 0x00000001 /* RWE-V */ +#define NV_TSTATE_TAGSTATECONTROL_ATO_ENB_OFF 0x00000000 /* RW--V */ +#define NV_TSTATE_ATO_TIMER_LIMIT 0x00003048 /* RW-4R */ +#define NV_TSTATE_ATO_TIMER_LIMIT_LIMIT 19:0 /* RWEVF */ +#define NV_TSTATE_ATO_TIMER_LIMIT_LIMIT_INIT 0x00000355 /* RWE-V */ +#define NV_TSTATE_ERR_STATUS_0 0x00003400 /* RW-4R */ +#define NV_TSTATE_ERR_STATUS_0_TAGPOOLBUFERR 0:0 /* RWDVF */ +#define NV_TSTATE_ERR_STATUS_0_TAGPOOLBUFERR__ONWRITE "oneToClear" /* */ +#define NV_TSTATE_ERR_STATUS_0_TAGPOOLBUFERR_NONE 0x00000000 /* RWD-V */ +#define NV_TSTATE_ERR_STATUS_0_TAGPOOLBUFERR_CLEAR 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_STATUS_0_TAGPOOL_ECC_LIMIT_ERR 1:1 /* RWDVF */ +#define NV_TSTATE_ERR_STATUS_0_TAGPOOL_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_TSTATE_ERR_STATUS_0_TAGPOOL_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_TSTATE_ERR_STATUS_0_TAGPOOL_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_STATUS_0_TAGPOOL_ECC_DBE_ERR 2:2 /* RWDVF */ +#define NV_TSTATE_ERR_STATUS_0_TAGPOOL_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_TSTATE_ERR_STATUS_0_TAGPOOL_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_TSTATE_ERR_STATUS_0_TAGPOOL_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_STATUS_0_CRUMBSTOREBUFERR 3:3 /* RWDVF */ +#define NV_TSTATE_ERR_STATUS_0_CRUMBSTOREBUFERR__ONWRITE "oneToClear" /* */ +#define NV_TSTATE_ERR_STATUS_0_CRUMBSTOREBUFERR_NONE 0x00000000 /* RWD-V */ +#define NV_TSTATE_ERR_STATUS_0_CRUMBSTOREBUFERR_CLEAR 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_LIMIT_ERR 4:4 /* RWDVF */ +#define NV_TSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_TSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_TSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_DBE_ERR 5:5 /* RWDVF */ +#define NV_TSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_TSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_TSTATE_ERR_STATUS_0_CRUMBSTORE_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_STATUS_0_ATO_ERR 6:6 /* RWDVF */ +#define NV_TSTATE_ERR_STATUS_0_ATO_ERR__ONWRITE "oneToClear" /* */ +#define NV_TSTATE_ERR_STATUS_0_ATO_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_TSTATE_ERR_STATUS_0_ATO_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_STATUS_0_CAMRSP_ERR 7:7 /* RWDVF */ +#define NV_TSTATE_ERR_STATUS_0_CAMRSP_ERR__ONWRITE "oneToClear" /* */ +#define NV_TSTATE_ERR_STATUS_0_CAMRSP_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_TSTATE_ERR_STATUS_0_CAMRSP_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_LOG_EN_0 0x00003404 /* RW-4R */ +#define NV_TSTATE_ERR_LOG_EN_0_TAGPOOLBUFERR 0:0 /* RWEVF */ +#define NV_TSTATE_ERR_LOG_EN_0_TAGPOOLBUFERR__PROD 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_LOG_EN_0_TAGPOOLBUFERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_LOG_EN_0_TAGPOOLBUFERR_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_LIMIT_ERR 1:1 /* RWEVF */ +#define NV_TSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_DBE_ERR 2:2 /* RWEVF */ +#define NV_TSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_LOG_EN_0_TAGPOOL_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_LOG_EN_0_CRUMBSTOREBUFERR 3:3 /* RWEVF */ +#define NV_TSTATE_ERR_LOG_EN_0_CRUMBSTOREBUFERR__PROD 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_LOG_EN_0_CRUMBSTOREBUFERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_LOG_EN_0_CRUMBSTOREBUFERR_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_LIMIT_ERR 4:4 /* RWEVF */ +#define NV_TSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_DBE_ERR 5:5 /* RWEVF */ +#define NV_TSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_LOG_EN_0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_LOG_EN_0_ATO_ERR 6:6 /* RWEVF */ +#define NV_TSTATE_ERR_LOG_EN_0_ATO_ERR__PROD 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_LOG_EN_0_ATO_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_LOG_EN_0_ATO_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_LOG_EN_0_CAMRSP_ERR 7:7 /* RWEVF */ +#define NV_TSTATE_ERR_LOG_EN_0_CAMRSP_ERR__PROD 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_LOG_EN_0_CAMRSP_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_LOG_EN_0_CAMRSP_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_FATAL_REPORT_EN_0 0x00003408 /* RW-4R */ +#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOLBUFERR 0:0 /* RWEVF */ +#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOLBUFERR__PROD 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOLBUFERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOLBUFERR_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR 1:1 /* RWEVF */ +#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR 2:2 /* RWEVF */ +#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTOREBUFERR 3:3 /* RWEVF */ +#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTOREBUFERR__PROD 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTOREBUFERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTOREBUFERR_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR 4:4 /* RWEVF */ +#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR 5:5 /* RWEVF */ +#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_ATO_ERR 6:6 /* RWEVF */ +#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_ATO_ERR__PROD 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_ATO_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_ATO_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_CAMRSP_ERR 7:7 /* RWEVF */ +#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_CAMRSP_ERR__PROD 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_CAMRSP_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_FATAL_REPORT_EN_0_CAMRSP_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0 0x0000340c /* RW-4R */ +#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOLBUFERR 0:0 /* RWEVF */ +#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOLBUFERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOLBUFERR_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR 1:1 /* RWEVF */ +#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR 2:2 /* RWEVF */ +#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_TAGPOOL_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTOREBUFERR 3:3 /* RWEVF */ +#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTOREBUFERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTOREBUFERR_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR 4:4 /* RWEVF */ +#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR 5:5 /* RWEVF */ +#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_ATO_ERR 6:6 /* RWEVF */ +#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_ATO_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_ATO_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_CAMRSP_ERR 7:7 /* RWEVF */ +#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_CAMRSP_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_NON_FATAL_REPORT_EN_0_CAMRSP_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_CORRECTABLE_REPORT_EN_0 0x00003410 /* RW-4R */ +#define NV_TSTATE_ERR_CONTAIN_EN_0 0x00003414 /* RW-4R */ +#define NV_TSTATE_ERR_CONTAIN_EN_0_TAGPOOLBUFERR 0:0 /* RWEVF */ +#define NV_TSTATE_ERR_CONTAIN_EN_0_TAGPOOLBUFERR__PROD 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_CONTAIN_EN_0_TAGPOOLBUFERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_CONTAIN_EN_0_TAGPOOLBUFERR_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_LIMIT_ERR 1:1 /* RWEVF */ +#define NV_TSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_DBE_ERR 2:2 /* RWEVF */ +#define NV_TSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_CONTAIN_EN_0_TAGPOOL_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_CONTAIN_EN_0_CRUMBSTOREBUFERR 3:3 /* RWEVF */ +#define NV_TSTATE_ERR_CONTAIN_EN_0_CRUMBSTOREBUFERR__PROD 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_CONTAIN_EN_0_CRUMBSTOREBUFERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_CONTAIN_EN_0_CRUMBSTOREBUFERR_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_LIMIT_ERR 4:4 /* RWEVF */ +#define NV_TSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_DBE_ERR 5:5 /* RWEVF */ +#define NV_TSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_CONTAIN_EN_0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_CONTAIN_EN_0_ATO_ERR 6:6 /* RWEVF */ +#define NV_TSTATE_ERR_CONTAIN_EN_0_ATO_ERR__PROD 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_CONTAIN_EN_0_ATO_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_CONTAIN_EN_0_ATO_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_CONTAIN_EN_0_CAMRSP_ERR 7:7 /* RWEVF */ +#define NV_TSTATE_ERR_CONTAIN_EN_0_CAMRSP_ERR__PROD 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_CONTAIN_EN_0_CAMRSP_ERR_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_CONTAIN_EN_0_CAMRSP_ERR_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_FIRST_0 0x0000341c /* RW-4R */ +#define NV_TSTATE_ERR_FIRST_0_TAGPOOLBUFERR 0:0 /* RWDVF */ +#define NV_TSTATE_ERR_FIRST_0_TAGPOOLBUFERR__ONWRITE "oneToClear" /* */ +#define NV_TSTATE_ERR_FIRST_0_TAGPOOLBUFERR_NONE 0x00000000 /* RWD-V */ +#define NV_TSTATE_ERR_FIRST_0_TAGPOOLBUFERR_CLEAR 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_FIRST_0_TAGPOOL_ECC_LIMIT_ERR 1:1 /* RWDVF */ +#define NV_TSTATE_ERR_FIRST_0_TAGPOOL_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_TSTATE_ERR_FIRST_0_TAGPOOL_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_TSTATE_ERR_FIRST_0_TAGPOOL_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_FIRST_0_TAGPOOL_ECC_DBE_ERR 2:2 /* RWDVF */ +#define NV_TSTATE_ERR_FIRST_0_TAGPOOL_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_TSTATE_ERR_FIRST_0_TAGPOOL_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_TSTATE_ERR_FIRST_0_TAGPOOL_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_FIRST_0_CRUMBSTOREBUFERR 3:3 /* RWDVF */ +#define NV_TSTATE_ERR_FIRST_0_CRUMBSTOREBUFERR__ONWRITE "oneToClear" /* */ +#define NV_TSTATE_ERR_FIRST_0_CRUMBSTOREBUFERR_NONE 0x00000000 /* RWD-V */ +#define NV_TSTATE_ERR_FIRST_0_CRUMBSTOREBUFERR_CLEAR 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_LIMIT_ERR 4:4 /* RWDVF */ +#define NV_TSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_LIMIT_ERR__ONWRITE "oneToClear" /* */ +#define NV_TSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_TSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_DBE_ERR 5:5 /* RWDVF */ +#define NV_TSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_DBE_ERR__ONWRITE "oneToClear" /* */ +#define NV_TSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_TSTATE_ERR_FIRST_0_CRUMBSTORE_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_FIRST_0_ATO_ERR 6:6 /* RWDVF */ +#define NV_TSTATE_ERR_FIRST_0_ATO_ERR__ONWRITE "oneToClear" /* */ +#define NV_TSTATE_ERR_FIRST_0_ATO_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_TSTATE_ERR_FIRST_0_ATO_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_FIRST_0_CAMRSP_ERR 7:7 /* RWDVF */ +#define NV_TSTATE_ERR_FIRST_0_CAMRSP_ERR__ONWRITE "oneToClear" /* */ +#define NV_TSTATE_ERR_FIRST_0_CAMRSP_ERR_NONE 0x00000000 /* RWD-V */ +#define NV_TSTATE_ERR_FIRST_0_CAMRSP_ERR_CLEAR 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_DEBUG 0x00003420 /* R--4R */ +#define NV_TSTATE_ERR_DEBUG_ATO_SOURCE 7:0 /* R-DVF */ +#define NV_TSTATE_ERR_DEBUG_ATO_SOURCE_INIT 0x00000000 /* R-D-V */ +#define NV_TSTATE_ERR_TIMESTAMP_LOG 0x00003450 /* R--4R */ +#define NV_TSTATE_ERR_TIMESTAMP_LOG_TIMESTAMP 23:0 /* R-DVF */ +#define NV_TSTATE_ERR_TIMESTAMP_LOG_TIMESTAMP_INIT 0x00000000 /* R-D-V */ +#define NV_TSTATE_ERR_MISC_LOG_0 0x00003454 /* R--4R */ +#define NV_TSTATE_ERR_MISC_LOG_0_ENCODEDVC 10:8 /* R-DVF */ +#define NV_TSTATE_ERR_MISC_LOG_0_ENCODEDVC_CREQ 0x00000000 /* R-D-V */ +#define NV_TSTATE_ERR_MISC_LOG_0_ENCODEDVC_DGD 0x00000001 /* R---V */ +#define NV_TSTATE_ERR_MISC_LOG_0_ENCODEDVC_ATR 0x00000002 /* R---V */ +#define NV_TSTATE_ERR_MISC_LOG_0_ENCODEDVC_ATSD 0x00000003 /* R---V */ +#define NV_TSTATE_ERR_MISC_LOG_0_ENCODEDVC_PROBE 0x00000004 /* R---V */ +#define NV_TSTATE_ERR_MISC_LOG_0_ENCODEDVC_CREQ_TD 0x00000005 /* R---V */ +#define NV_TSTATE_ERR_MISC_LOG_0_ENCODEDVC_DGD_TD 0x00000006 /* R---V */ +#define NV_TSTATE_ERR_ECC_CTRL 0x00003470 /* RW-4R */ +#define NV_TSTATE_ERR_ECC_CTRL_CRUMBSTORE_ECC_ENABLE 0:0 /* RWEVF */ +#define NV_TSTATE_ERR_ECC_CTRL_CRUMBSTORE_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_ECC_CTRL_CRUMBSTORE_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_ECC_CTRL_CRUMBSTORE_ECC_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_ECC_CTRL_TAGPOOL_ECC_ENABLE 1:1 /* RWEVF */ +#define NV_TSTATE_ERR_ECC_CTRL_TAGPOOL_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_ECC_CTRL_TAGPOOL_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */ +#define NV_TSTATE_ERR_ECC_CTRL_TAGPOOL_ECC_ENABLE__PROD 0x00000001 /* RW--V */ +#define NV_TSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER 0x00003480 /* RW-4R */ +#define NV_TSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */ +#define NV_TSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */ +#define NV_TSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT 0x00003484 /* RW-4R */ +#define NV_TSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */ +#define NV_TSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */ +#define NV_TSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS 0x00003488 /* R--4R */ +#define NV_TSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_ERROR_ADDRESS 9:0 /* R-DVF */ +#define NV_TSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */ +#define NV_TSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID 0x0000348c /* R--4R */ +#define NV_TSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */ +#define NV_TSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */ +#define NV_TSTATE_ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */ +#define NV_TSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER 0x00003490 /* RW-4R */ +#define NV_TSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */ +#define NV_TSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */ +#define NV_TSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER_LIMIT 0x00003494 /* RW-4R */ +#define NV_TSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */ +#define NV_TSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */ +#define NV_TSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS 0x00003498 /* R--4R */ +#define NV_TSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_ERROR_ADDRESS 9:0 /* R-DVF */ +#define NV_TSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */ +#define NV_TSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_VALID 0x0000349c /* R--4R */ +#define NV_TSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */ +#define NV_TSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */ +#define NV_TSTATE_ERR_TAGPOOL_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */ +#endif // __ls10_dev_tstate_ip_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_xtl_ep_pri.h b/src/common/inc/swref/published/nvswitch/ls10/dev_xtl_ep_pri.h new file mode 100644 index 000000000..cc7414361 --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_xtl_ep_pri.h @@ -0,0 +1,86 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_dev_xtl_ep_pri_h__ +#define __ls10_dev_xtl_ep_pri_h__ +/* This file is autogenerated. Do not edit */ +#define NV_XTL 0x91FFF:0x91000 /* RW--D */ +#define NV_XTL_EP_PRI 0x00FFF:0x00000 /* RW--D */ +#define NV_XTL_EP_PRI_XTL_EP_CG 0x00000F00 /* RWI4R */ +#define NV_XTL_EP_PRI_XTL_EP_CG_IDLE_CG_DLY_CNT 5:0 /* RWIVF */ +#define NV_XTL_EP_PRI_XTL_EP_CG_IDLE_CG_DLY_CNT_HWINIT 0x0000000B /* RWI-V */ +#define NV_XTL_EP_PRI_XTL_EP_CG_IDLE_CG_DLY_CNT__PROD 0x0000000B /* RW--V */ +#define NV_XTL_EP_PRI_XTL_EP_CG_IDLE_CG_EN 6:6 /* RWIVF */ +#define NV_XTL_EP_PRI_XTL_EP_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ +#define NV_XTL_EP_PRI_XTL_EP_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWI-V */ +#define NV_XTL_EP_PRI_XTL_EP_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ +#define NV_XTL_EP_PRI_XTL_EP_CG_STATE_CG_EN 7:7 /* */ +#define NV_XTL_EP_PRI_XTL_EP_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ +#define NV_XTL_EP_PRI_XTL_EP_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ +#define NV_XTL_EP_PRI_XTL_EP_CG_STATE_CG_EN__PROD 0x00000000 /* */ +#define NV_XTL_EP_PRI_XTL_EP_CG_STALL_CG_DLY_CNT 13:8 /* */ +#define NV_XTL_EP_PRI_XTL_EP_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ +#define NV_XTL_EP_PRI_XTL_EP_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */ +#define NV_XTL_EP_PRI_XTL_EP_CG_STALL_CG_EN 14:14 /* RWIVF */ +#define NV_XTL_EP_PRI_XTL_EP_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ +#define NV_XTL_EP_PRI_XTL_EP_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWI-V */ +#define NV_XTL_EP_PRI_XTL_EP_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ +#define NV_XTL_EP_PRI_XTL_EP_CG_QUIESCENT_CG_EN 15:15 /* */ +#define NV_XTL_EP_PRI_XTL_EP_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ +#define NV_XTL_EP_PRI_XTL_EP_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ +#define NV_XTL_EP_PRI_XTL_EP_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ +#define NV_XTL_EP_PRI_XTL_EP_CG_WAKEUP_DLY_CNT 19:16 /* RWIVF */ +#define NV_XTL_EP_PRI_XTL_EP_CG_WAKEUP_DLY_CNT_HWINIT 0x0000000B /* RWI-V */ +#define NV_XTL_EP_PRI_XTL_EP_CG_WAKEUP_DLY_CNT__PROD 0x0000000B /* RW--V */ +#define NV_XTL_EP_PRI_XTL_EP_CG_THROT_CLK_CNT 23:20 /* */ +#define NV_XTL_EP_PRI_XTL_EP_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ +#define NV_XTL_EP_PRI_XTL_EP_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ +#define NV_XTL_EP_PRI_XTL_EP_CG_DI_DT_SKEW_VAL 27:24 /* */ +#define NV_XTL_EP_PRI_XTL_EP_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ +#define NV_XTL_EP_PRI_XTL_EP_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ +#define NV_XTL_EP_PRI_XTL_EP_CG_THROT_CLK_EN 28:28 /* */ +#define NV_XTL_EP_PRI_XTL_EP_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ +#define NV_XTL_EP_PRI_XTL_EP_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ +#define NV_XTL_EP_PRI_XTL_EP_CG_THROT_CLK_EN__PROD 0x00000000 /* */ +#define NV_XTL_EP_PRI_XTL_EP_CG_THROT_CLK_SW_OVER 29:29 /* */ +#define NV_XTL_EP_PRI_XTL_EP_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ +#define NV_XTL_EP_PRI_XTL_EP_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ +#define NV_XTL_EP_PRI_XTL_EP_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ +#define NV_XTL_EP_PRI_XTL_EP_CG_PAUSE_CG_EN 30:30 /* */ +#define NV_XTL_EP_PRI_XTL_EP_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ +#define NV_XTL_EP_PRI_XTL_EP_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ +#define NV_XTL_EP_PRI_XTL_EP_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ +#define NV_XTL_EP_PRI_XTL_EP_CG_HALT_CG_EN 31:31 /* */ +#define NV_XTL_EP_PRI_XTL_EP_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ +#define NV_XTL_EP_PRI_XTL_EP_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ +#define NV_XTL_EP_PRI_XTL_EP_CG_HALT_CG_EN__PROD 0x00000000 /* */ +#define NV_XTL_EP_PRI_XTL_EP_CG1 0x00000F04 /* RWI4R */ +#define NV_XTL_EP_PRI_XTL_EP_CG1_MONITOR_CG_EN 0:0 /* RWIVF */ +#define NV_XTL_EP_PRI_XTL_EP_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ +#define NV_XTL_EP_PRI_XTL_EP_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWI-V */ +#define NV_XTL_EP_PRI_XTL_EP_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ +#define NV_XTL_EP_PRI_XTL_EP_CG1_SLCG 15:1 /* RWIVF */ +#define NV_XTL_EP_PRI_XTL_EP_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ +#define NV_XTL_EP_PRI_XTL_EP_CG1_SLCG_DISABLED 0x00007FFF /* RWI-V */ +#define NV_XTL_EP_PRI_XTL_EP_CG1_SLCG__PROD 0x00000000 /* RW--V */ +#endif // __ls10_dev_xtl_ep_pri_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/npgip_discovery.h b/src/common/inc/swref/published/nvswitch/ls10/npgip_discovery.h new file mode 100644 index 000000000..a8dfc2a4e --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/npgip_discovery.h @@ -0,0 +1,70 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_npgip_discovery_h__ +#define __ls10_npgip_discovery_h__ +/* This file is autogenerated. Do not edit */ +#define NV_NPG_DISCOVERY /* R--4P */ +#define NV_NPG_DISCOVERY_ENTRY 1:0 /* R-EVF */ +#define NV_NPG_DISCOVERY_ENTRY_INVALID 0x00000000 /* R-E-V */ +#define NV_NPG_DISCOVERY_ENTRY_ENUM 0x00000001 /* R---V */ +#define NV_NPG_DISCOVERY_ENTRY_DATA1 0x00000002 /* R---V */ +#define NV_NPG_DISCOVERY_ENTRY_DATA2 0x00000003 /* R---V */ +#define NV_NPG_DISCOVERY_CONTENTS 30:2 /* R-EVF */ +#define NV_NPG_DISCOVERY_CONTENTS_INIT 0x00000000 /* R-E-V */ +#define NV_NPG_DISCOVERY_CHAIN 31:31 /* R-EVF */ +#define NV_NPG_DISCOVERY_CHAIN_DISABLE 0x00000000 /* R-E-V */ +#define NV_NPG_DISCOVERY_CHAIN_ENABLE 0x00000001 /* R---V */ +#define NV_NPG_DISCOVERY_ENUM_DEVICE 7:2 /* R--UF */ +#define NV_NPG_DISCOVERY_ENUM_DEVICE_INVALID 0x0 /* R---V */ +#define NV_NPG_DISCOVERY_ENUM_DEVICE_NPG 0x1 /* R---V */ +#define NV_NPG_DISCOVERY_ENUM_DEVICE_NPORT 0x2 /* R---V */ +#define NV_NPG_DISCOVERY_ENUM_DEVICE_NPORT_MULTICAST 0x3 /* R---V */ +#define NV_NPG_DISCOVERY_ENUM_DEVICE_NPG_PERFMON 0x4 /* R---V */ +#define NV_NPG_DISCOVERY_ENUM_DEVICE_NPORT_PERFMON 0x5 /* R---V */ +#define NV_NPG_DISCOVERY_ENUM_DEVICE_NPORT_PERFMON_MULTICAST 0x6 /* R---V */ +#define NV_NPG_DISCOVERY_ENUM_ID 15:8 /* R--UF */ +#define NV_NPG_DISCOVERY_ENUM_RESERVED 19:16 /* R--UF */ +#define NV_NPG_DISCOVERY_ENUM_VERSION 30:20 /* R--UF */ +#define NV_NPG_DISCOVERY_ENUM_VERSION_1 0x1 /* R---V */ +#define NV_NPG_DISCOVERY_ENUM_VERSION_2 0x2 /* R---V */ +#define NV_NPG_DISCOVERY_ENUM_VERSION_3 0x3 /* R---V */ +#define NV_NPG_DISCOVERY_DATA1_RESET 6:2 /* R--UF */ +#define NV_NPG_DISCOVERY_DATA1_INTR 11:7 /* R--UF */ +#define NV_NPG_DISCOVERY_DATA1_RESERVED2 11:2 /* R--UF */ +#define NV_NPG_DISCOVERY_DATA1_NPG_LENGTH 30:12 /* R--UF */ +#define NV_NPG_DISCOVERY_DATA1_RESERVED 30:12 /* R--UF */ +#define NV_NPG_DISCOVERY_DATA2_TYPE 30:26 /* R--UF */ +#define NV_NPG_DISCOVERY_DATA2_TYPE_INVALID 0x0 /* R---V */ +#define NV_NPG_DISCOVERY_DATA2_TYPE_RESERVED 0x1 /* R---V */ +#define NV_NPG_DISCOVERY_DATA2_TYPE_RESETREG 0x2 /* R---V */ +#define NV_NPG_DISCOVERY_DATA2_TYPE_INTRREG 0x3 /* R---V */ +#define NV_NPG_DISCOVERY_DATA2_TYPE_DISCOVERY 0x4 /* R---V */ +#define NV_NPG_DISCOVERY_DATA2_TYPE_UNICAST 0x5 /* R---V */ +#define NV_NPG_DISCOVERY_DATA2_TYPE_BROADCAST 0x6 /* R---V */ +#define NV_NPG_DISCOVERY_DATA2_TYPE_MULTICAST0 0x7 /* R---V */ +#define NV_NPG_DISCOVERY_DATA2_TYPE_MULTICAST1 0x8 /* R---V */ +#define NV_NPG_DISCOVERY_DATA2_TYPE_MULTICAST2 0x9 /* R---V */ +#define NV_NPG_DISCOVERY_DATA2_ADDR 25:2 /* R--UF */ +#define NV_NPG_DISCOVERY_PRI_BASE_ALIGN 12 /* */ +#endif // __ls10_npgip_discovery_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/nvlinkip_discovery.h b/src/common/inc/swref/published/nvswitch/ls10/nvlinkip_discovery.h new file mode 100644 index 000000000..cc2f10f6f --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/nvlinkip_discovery.h @@ -0,0 +1,95 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_nvlinkip_discovery_h__ +#define __ls10_nvlinkip_discovery_h__ +/* This file is autogenerated. Do not edit */ +#define NV_NVLINKIP_DISCOVERY_COMMON /* R--4P */ +#define NV_NVLINKIP_DISCOVERY_COMMON_ENTRY 1:0 /* R-EVF */ +#define NV_NVLINKIP_DISCOVERY_COMMON_ENTRY_INVALID 0x00000000 /* R-E-V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_ENTRY_ENUM 0x00000001 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_ENTRY_DATA1 0x00000002 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_ENTRY_DATA2 0x00000003 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_CONTENTS 30:2 /* R-EVF */ +#define NV_NVLINKIP_DISCOVERY_COMMON_CONTENTS_INIT 0x00000000 /* R-E-V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_CHAIN 31:31 /* R-EVF */ +#define NV_NVLINKIP_DISCOVERY_COMMON_CHAIN_DISABLE 0x00000000 /* R-E-V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_CHAIN_ENABLE 0x00000001 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE 7:2 /* R--UF */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_INVALID 0x0 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_IOCTRL 0x1 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_NVLTL 0x2 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_NVLINK 0x3 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_MINION 0x4 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_NVLIPT 0x5 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_NVLTLC 0x6 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_IOCTRLMIF 0x7 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_DLPL_MULTICAST 0x8 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_NVLTLC_MULTICAST 0x9 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_IOCTRLMIF_MULTICAST 0xA /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_DLPL 0xB /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_SIOCTRL 0xC /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_TIOCTRL 0xD /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_SIOCTRL_PERFMON 0xE /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_NVLIPT_SYS_PERFMON 0xF /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_TX_PERFMON_MULTICAST 0x10 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_RX_PERFMON_MULTICAST 0x11 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_TX_PERFMON 0x12 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_RX_PERFMON 0x13 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_NVLW 0x14 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_NVLW_PERFMON 0x15 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_NVLDL 0x16 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_NVLDL_MULTICAST 0x17 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_SYS_PERFMON 0x18 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_SYS_PERFMON_MULTICAST 0x19 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_NVLIPT_LNK 0x1A /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_NVLIPT_LNK_MULTICAST 0x1B /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_PLL 0x1C /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_CPR 0x1D /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_ID 15:8 /* R--UF */ +#define NV_NVLINKIP_DISCOVERY_COMMON_RESERVED 19:16 /* R--UF */ +#define NV_NVLINKIP_DISCOVERY_COMMON_VERSION 30:20 /* R--UF */ +#define NV_NVLINKIP_DISCOVERY_COMMON_VERSION_NVLINK10 0x1 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_VERSION_NVLINK20 0x2 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_VERSION_3 0x3 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_VERSION_NVLINK22 0x4 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_VERSION_NVLINK30 0x5 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_VERSION_NVLINK31 0x6 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_VERSION_NVLINK40 0x7 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DATA1_RESERVED 30:12 /* R--UF */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DATA1_IOCTRL_LENGTH 30:12 /* R--UF */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DATA1_RESERVED2 11:2 /* R--UF */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DATA2_TYPE 30:26 /* R--UF */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DATA2_TYPE_INVALID 0x0 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DATA2_TYPE_PLLCONTROL 0x1 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DATA2_TYPE_RESETREG 0x2 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DATA2_TYPE_INTRREG 0x3 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DATA2_TYPE_DISCOVERY 0x4 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DATA2_TYPE_UNICAST 0x5 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DATA2_TYPE_BROADCAST 0x6 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DATA2_TYPE_MULTICAST0 0x7 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DATA2_TYPE_MULTICAST1 0x8 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DATA2_TYPE_MULTICAST2 0x9 /* R---V */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DATA2_ADDR 25:2 /* R--UF */ +#define NV_NVLINKIP_DISCOVERY_COMMON_DATA2_ADDR_ALIGN 2 /* */ +#endif // __ls10_nvlinkip_discovery_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/nxbar_discovery.h b/src/common/inc/swref/published/nvswitch/ls10/nxbar_discovery.h new file mode 100644 index 000000000..40b909d46 --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/nxbar_discovery.h @@ -0,0 +1,74 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_nxbar_discovery_h__ +#define __ls10_nxbar_discovery_h__ +/* This file is autogenerated. Do not edit */ +#define NV_NXBAR_DISCOVERY /* R--4P */ +#define NV_NXBAR_DISCOVERY_ENTRY 1:0 /* R-EVF */ +#define NV_NXBAR_DISCOVERY_ENTRY_INVALID 0x00000000 /* R-E-V */ +#define NV_NXBAR_DISCOVERY_ENTRY_ENUM 0x00000001 /* R---V */ +#define NV_NXBAR_DISCOVERY_ENTRY_DATA1 0x00000002 /* R---V */ +#define NV_NXBAR_DISCOVERY_ENTRY_DATA2 0x00000003 /* R---V */ +#define NV_NXBAR_DISCOVERY_CONTENTS 30:2 /* R-EVF */ +#define NV_NXBAR_DISCOVERY_CONTENTS_INIT 0x00000000 /* R-E-V */ +#define NV_NXBAR_DISCOVERY_CHAIN 31:31 /* R-EVF */ +#define NV_NXBAR_DISCOVERY_CHAIN_DISABLE 0x00000000 /* R-E-V */ +#define NV_NXBAR_DISCOVERY_CHAIN_ENABLE 0x00000001 /* R---V */ +#define NV_NXBAR_DISCOVERY_ENUM_DEVICE 7:2 /* R--UF */ +#define NV_NXBAR_DISCOVERY_ENUM_DEVICE_INVALID 0x0 /* R---V */ +#define NV_NXBAR_DISCOVERY_ENUM_DEVICE_NXBAR 0x1 /* R---V */ +#define NV_NXBAR_DISCOVERY_ENUM_DEVICE_TILE 0x2 /* R---V */ +#define NV_NXBAR_DISCOVERY_ENUM_DEVICE_TILE_MULTICAST 0x3 /* R---V */ +#define NV_NXBAR_DISCOVERY_ENUM_DEVICE_NXBAR_PERFMON 0x4 /* R---V */ +#define NV_NXBAR_DISCOVERY_ENUM_DEVICE_TILE_PERFMON 0x5 /* R---V */ +#define NV_NXBAR_DISCOVERY_ENUM_DEVICE_TILE_PERFMON_MULTICAST 0x6 /* R---V */ +#define NV_NXBAR_DISCOVERY_ENUM_DEVICE_TILEOUT 0x7 /* R---V */ +#define NV_NXBAR_DISCOVERY_ENUM_DEVICE_TILEOUT_MULTICAST 0x8 /* R---V */ +#define NV_NXBAR_DISCOVERY_ENUM_DEVICE_TILEOUT_PERFMON 0x9 /* R---V */ +#define NV_NXBAR_DISCOVERY_ENUM_DEVICE_TILEOUT_PERFMON_MULTICAST 0xA /* R---V */ +#define NV_NXBAR_DISCOVERY_ENUM_ID 15:8 /* R--UF */ +#define NV_NXBAR_DISCOVERY_ENUM_RESERVED 19:16 /* R--UF */ +#define NV_NXBAR_DISCOVERY_ENUM_VERSION 30:20 /* R--UF */ +#define NV_NXBAR_DISCOVERY_ENUM_VERSION_1 0x1 /* R---V */ +#define NV_NXBAR_DISCOVERY_ENUM_VERSION_2 0x2 /* R---V */ +#define NV_NXBAR_DISCOVERY_ENUM_VERSION_3 0x3 /* R---V */ +#define NV_NXBAR_DISCOVERY_DATA1_RESET 6:2 /* R--UF */ +#define NV_NXBAR_DISCOVERY_DATA1_INTR 11:7 /* R--UF */ +#define NV_NXBAR_DISCOVERY_DATA1_RESERVED2 11:2 /* R--UF */ +#define NV_NXBAR_DISCOVERY_DATA1_NXBAR_LENGTH 30:12 /* R--UF */ +#define NV_NXBAR_DISCOVERY_DATA1_RESERVED 30:12 /* R--UF */ +#define NV_NXBAR_DISCOVERY_DATA2_TYPE 30:26 /* R--UF */ +#define NV_NXBAR_DISCOVERY_DATA2_TYPE_INVALID 0x0 /* R---V */ +#define NV_NXBAR_DISCOVERY_DATA2_TYPE_RESERVED 0x1 /* R---V */ +#define NV_NXBAR_DISCOVERY_DATA2_TYPE_RESETREG 0x2 /* R---V */ +#define NV_NXBAR_DISCOVERY_DATA2_TYPE_INTRREG 0x3 /* R---V */ +#define NV_NXBAR_DISCOVERY_DATA2_TYPE_DISCOVERY 0x4 /* R---V */ +#define NV_NXBAR_DISCOVERY_DATA2_TYPE_UNICAST 0x5 /* R---V */ +#define NV_NXBAR_DISCOVERY_DATA2_TYPE_BROADCAST 0x6 /* R---V */ +#define NV_NXBAR_DISCOVERY_DATA2_TYPE_MULTICAST0 0x7 /* R---V */ +#define NV_NXBAR_DISCOVERY_DATA2_TYPE_MULTICAST1 0x8 /* R---V */ +#define NV_NXBAR_DISCOVERY_DATA2_TYPE_MULTICAST2 0x9 /* R---V */ +#define NV_NXBAR_DISCOVERY_DATA2_ADDR 25:2 /* R--UF */ +#define NV_NXBAR_DISCOVERY_PRI_BASE_ALIGN 12 /* */ +#endif // __ls10_nxbar_discovery_h__ diff --git a/src/common/inc/swref/published/pcie_switch/pcie_switch_ref.h b/src/common/inc/swref/published/pcie_switch/pcie_switch_ref.h index 064a0a529..2b27fb49b 100644 --- a/src/common/inc/swref/published/pcie_switch/pcie_switch_ref.h +++ b/src/common/inc/swref/published/pcie_switch/pcie_switch_ref.h @@ -26,6 +26,7 @@ #include "published/br03/dev_br03_xvd.h" #include "published/br03/dev_br03_xvu.h" #include "published/br04/br04_ref.h" +#include "nvdevid.h" // // This file has the vendor and device IDs of all supported PCIe switches diff --git a/src/common/modeset/hdmipacket/nvhdmipkt.h b/src/common/modeset/hdmipacket/nvhdmipkt.h index aff0311ba..8371b6402 100644 --- a/src/common/modeset/hdmipacket/nvhdmipkt.h +++ b/src/common/modeset/hdmipacket/nvhdmipkt.h @@ -254,6 +254,7 @@ typedef struct _tagNVHDMIPKT_CALLBACK NvBool expression); } NVHDMIPKT_CALLBACK; + /*********************** HDMI Library interface to write hdmi ctrl/packet ***********************/ typedef void* NvHdmiPkt_Handle; #define NVHDMIPKT_INVALID_HANDLE ((NvHdmiPkt_Handle)0) @@ -300,6 +301,7 @@ NvHdmiPkt_PacketWrite(NvHdmiPkt_Handle libHandle, NvU32 packetLen, NvU8 const *const pPacket); + /***************************** Interface to initialize HDMI Library *****************************/ /************************************************************************************************ diff --git a/src/common/modeset/hdmipacket/nvhdmipkt_0073.c b/src/common/modeset/hdmipacket/nvhdmipkt_0073.c index a5baf8bf2..07cfc7b22 100644 --- a/src/common/modeset/hdmipacket/nvhdmipkt_0073.c +++ b/src/common/modeset/hdmipacket/nvhdmipkt_0073.c @@ -388,4 +388,5 @@ initializeHdmiPktInterface0073(NVHDMIPKT_CLASS* pClass) pClass->hdmiQueryFRLConfig = hdmiQueryFRLConfigDummy; pClass->hdmiSetFRLConfig = hdmiSetFRLConfigDummy; pClass->hdmiClearFRLConfig = hdmiClearFRLConfigDummy; + } diff --git a/src/common/modeset/hdmipacket/nvhdmipkt_9171.c b/src/common/modeset/hdmipacket/nvhdmipkt_9171.c index 3c96934f9..ae29ff3d3 100644 --- a/src/common/modeset/hdmipacket/nvhdmipkt_9171.c +++ b/src/common/modeset/hdmipacket/nvhdmipkt_9171.c @@ -846,4 +846,5 @@ initializeHdmiPktInterface9171(NVHDMIPKT_CLASS* pClass) pClass->hdmiQueryFRLConfig = hdmiQueryFRLConfigDummy; pClass->hdmiSetFRLConfig = hdmiSetFRLConfigDummy; pClass->hdmiClearFRLConfig = hdmiClearFRLConfigDummy; + } diff --git a/src/common/modeset/hdmipacket/nvhdmipkt_common.h b/src/common/modeset/hdmipacket/nvhdmipkt_common.h index 771e9e7fe..bf3fcb3b7 100644 --- a/src/common/modeset/hdmipacket/nvhdmipkt_common.h +++ b/src/common/modeset/hdmipacket/nvhdmipkt_common.h @@ -110,5 +110,4 @@ extern NVHDMIPKT_RESULT hdmiClearFRLConfigDummy(NVHDMIPKT_CLASS *pThis, NvU32 subDevice, NvU32 displayId); - #endif //_NVHDMIPKT_COMMON_H_ diff --git a/src/common/modeset/timing/displayid20.h b/src/common/modeset/timing/displayid20.h index 006d279be..951f38256 100644 --- a/src/common/modeset/timing/displayid20.h +++ b/src/common/modeset/timing/displayid20.h @@ -1,6 +1,6 @@ //***************************************************************************** // -// SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +// SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-License-Identifier: MIT // // Permission is hereby granted, free of charge, to any person obtaining a @@ -100,14 +100,20 @@ typedef struct _tagDISPLAYID_2_0_DATA_BLOCK_HEADER #define DISPLAYID_2_0_BLOCK_TYPE_TIMING_7 0x22 #define DISPLAYID_2_0_BLOCK_TYPE_TIMING_8 0x23 #define DISPLAYID_2_0_BLOCK_TYPE_TIMING_9 0x24 -#define DISPLAYID_2_0_BLOCK_TYPE_TIMING_10 0x2A #define DISPLAYID_2_0_BLOCK_TYPE_RANGE_LIMITS 0x25 #define DISPLAYID_2_0_BLOCK_TYPE_INTERFACE_FEATURES 0x26 #define DISPLAYID_2_0_BLOCK_TYPE_STEREO 0x27 #define DISPLAYID_2_0_BLOCK_TYPE_TILED_DISPLAY 0x28 #define DISPLAYID_2_0_BLOCK_TYPE_CONTAINER_ID 0x29 +#define DISPLAYID_2_0_BLOCK_TYPE_TIMING_10 0x2A +#define DISPLAYID_2_0_BLOCK_TYPE_ADAPTIVE_SYNC 0x2B +#define DISPLAYID_2_0_BLOCK_TYPE_ARVR_HMD 0x2C +#define DISPLAYID_2_0_BLOCK_TYPE_ARVR_LAYER 0x2D +// 0x7D - 0x2E RESERVED for Additional VESA-defined Data Blocks #define DISPLAYID_2_0_BLOCK_TYPE_VENDOR_SPEC 0x7E +// 0x80 - 0x7F RESERVED #define DISPLAYID_2_0_BLOCK_TYPE_CTA_DATA 0x81 +// 0xFF - 0x82 RESERVED for additional data blocks related to external standards organization(s). #define DISPLAYID_2_0_PRODUCT_NAME_STRING_MAX_LEN ((0xFB - 0xF) + 1) @@ -236,7 +242,7 @@ typedef struct _tag_DISPLAYID_2_0_TIMING_7_DESCRIPTOR NvU8 interface_frame_scanning_type : 1; NvU8 stereo_support : 2; NvU8 is_preferred_or_ycc420 : 1; - }options; + } options; struct { @@ -246,7 +252,7 @@ typedef struct _tag_DISPLAYID_2_0_TIMING_7_DESCRIPTOR NvU8 front_porch_pixels_high : 7; NvU8 sync_polarity : 1; NvU8 sync_width_pixels[2]; - }horizontal; + } horizontal; struct { @@ -256,8 +262,7 @@ typedef struct _tag_DISPLAYID_2_0_TIMING_7_DESCRIPTOR NvU8 front_porch_lines_high : 7; NvU8 sync_polarity : 1; NvU8 sync_width_lines[2]; - }vertical; - + } vertical; } DISPLAYID_2_0_TIMING_7_DESCRIPTOR; #define DISPLAYID_2_0_TIMING_7_MAX_DESCRIPTORS 12 @@ -336,11 +341,11 @@ typedef struct _tagDISPLAYID_2_0_TIMING_8_BLOCK typedef struct _TAG_DISPLAYID_2_0_TIMING_9_DESCRIPTOR { struct { - NvU8 timing_formula:3; - NvU8 reserved0:1; - NvU8 fractional_refresh_rate_support:1; - NvU8 stereo_support:2; - NvU8 reserved1:1; + NvU8 timing_formula :3; + NvU8 reserved0 :1; + NvU8 rr_1000div1001_support :1; + NvU8 stereo_support :2; + NvU8 reserved1 :1; } options; NvU8 horizontal_active_pixels[2]; @@ -350,10 +355,10 @@ typedef struct _TAG_DISPLAYID_2_0_TIMING_9_DESCRIPTOR #define DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_STANDARD 0 #define DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_REDUCED_BLANKING_1 1 -#define DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_REDUCED_BLANKING_2 2 -#define DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_REDUCED_BLANKING_3 3 +#define DISPLAYID_2_0_TIMING_FORMULA_CVT_2_0_REDUCED_BLANKING_2 2 +#define DISPLAYID_2_0_TIMING_FORMULA_CVT_2_0_REDUCED_BLANKING_3 3 -#define DISPLAYID_2_0_TIMING_9_MAX_DESCRIPTORS 41 +#define DISPLAYID_2_0_TIMING_9_MAX_DESCRIPTORS 18 typedef struct _tagDISPLAYID_2_0_TIMING_9_BLOCK { @@ -379,8 +384,8 @@ typedef struct _DISPLAYID_2_0_TIMING_10_6BYTES_DESCRIPTOR { struct { NvU8 timing_formula :3; - NvU8 reserved0 :1; - NvU8 vrr_or_hblank :1; + NvU8 early_vsync :1; + NvU8 rr1000div1001_or_hblank :1; NvU8 stereo_support :2; NvU8 ycc420_support :1; } options; @@ -398,8 +403,8 @@ typedef struct _DISPLAYID_2_0_TIMING_10_7BYTES_DESCRIPTOR NvU8 additional_vblank_timing :3; } DISPLAYID_2_0_TIMING_10_7BYTES_DESCRIPTOR; -#define DISPLAYID_2_0_TIMING_10_MAX_6BYTES_DESCRIPTORS 41 -#define DISPLAYID_2_0_TIMING_10_MAX_7BYTES_DESCRIPTORS 35 +#define DISPLAYID_2_0_TIMING_10_MAX_6BYTES_DESCRIPTORS 18 +#define DISPLAYID_2_0_TIMING_10_MAX_7BYTES_DESCRIPTORS 16 typedef struct _DISPLAYID_2_0_TIMING_10_BLOCK { @@ -416,10 +421,11 @@ typedef struct _tagDISPLAYID_2_0_RANGE_LIMITS_BLOCK NvU8 pixel_clock_max[3]; NvU8 vertical_frequency_min; NvU8 vertical_frequency_max_7_0; + struct { - NvU8 vertical_frequency_max_9_8:2; - NvU8 reserved:5; - NvU8 seamless_dynamic_video_timing_change:1; + NvU8 vertical_frequency_max_9_8 :2; + NvU8 reserved :5; + NvU8 seamless_dynamic_video_timing_change :1; } dynamic_video_timing_range_support; } DISPLAYID_2_0_RANGE_LIMITS_BLOCK; @@ -677,6 +683,51 @@ typedef struct _tagDISPLAYID_2_0_CONTAINERID_BLOCK NvU8 container_id[DISPLAYID_2_0_CONTAINERID_BLOCK_PAYLOAD_LENGTH]; } DISPLAYID_2_0_CONTAINERID_BLOCK; +#define DISPLAYID_2_0_ADAPTIVE_SYNC_DETAILED_TIMING_COUNT 4 +typedef struct _tagDISPLAYID_2_0_ADAPTIVE_SYNC_BLOCK_HEADER +{ + NvU8 type; // Adaptive-Sync (0x2B) + NvU8 revision :3; + NvU8 reserved0 :1; + NvU8 payload_bytes_adaptive_sync_len :3; + NvU8 reserved1 :1; + NvU8 payload_bytes; +} DISPLAYID_2_0_ADAPTIVE_SYNC_BLOCK_HEADER; + +typedef struct _tagDISPLAYID_2_0_ADAPTIVE_SYNC_DESCRIPTOR +{ + struct + { + NvU8 range : 1; + NvU8 successive_frame_inc_tolerance : 1; + NvU8 modes : 2; + NvU8 seamless_transition_not_support: 1; + NvU8 successive_frame_dec_tolerance : 1; + NvU8 reserved : 2; + } operation_range_info; + + // 6.2 format (six integer bits and two fractional bits) + // six integer bits == 0 - 63ms + // two fractional bits == 0.00(00), 0.25(01b),0.50(10), 0.75(11b) + NvU8 max_single_frame_inc; + NvU8 min_refresh_rate; + struct + { + NvU8 max_rr_7_0; + NvU8 max_rr_9_8 : 2; + NvU8 reserved : 6; + } max_refresh_rate; + + // same as max_single_frame_inc expression + NvU8 max_single_frame_dec; +} DISPLAYID_2_0_ADAPTIVE_SYNC_DESCRIPTOR; + +typedef struct _tagDISPLAYID_2_0_ADAPTIVE_SYNC_BLOCK +{ + DISPLAYID_2_0_ADAPTIVE_SYNC_BLOCK_HEADER header; + DISPLAYID_2_0_ADAPTIVE_SYNC_DESCRIPTOR descriptors[DISPLAYID_2_0_ADAPTIVE_SYNC_DETAILED_TIMING_COUNT]; +} DISPLAYID_2_0_ADAPTIVE_SYNC_BLOCK; + typedef struct _tagDISPLAYID_2_0_VENDOR_SPECIFIC_BLOCK { DISPLAYID_2_0_DATA_BLOCK_HEADER header; diff --git a/src/common/modeset/timing/dpsdp.h b/src/common/modeset/timing/dpsdp.h index 43754d6c5..a29dc8779 100644 --- a/src/common/modeset/timing/dpsdp.h +++ b/src/common/modeset/timing/dpsdp.h @@ -49,8 +49,8 @@ typedef enum tagSDP_VSC_REVNUM { SDP_VSC_REVNUM_STEREO = 1, SDP_VSC_REVNUM_STEREO_PSR, - SDP_VSC_REVNUM_STEREO_PSR2, - SDP_VSC_REVNUM_PSR2_EXTN, + SDP_VSC_REVNUM_STEREO_PSR2, + SDP_VSC_REVNUM_PSR2_EXTN, SDP_VSC_REVNUM_STEREO_PSR2_COLOR, SDP_VSC_REVNUM_STEREO_PR, SDP_VSC_REVNUM_STEREO_PR_COLOR, @@ -60,7 +60,7 @@ typedef enum tagSDP_VSC_VALID_DATA_BYTES { SDP_VSC_VALID_DATA_BYTES_STEREO = 1, SDP_VSC_VALID_DATA_BYTES_STEREO_PSR = 8, - SDP_VSC_VALID_DATA_BYTES_PSR2 = 12, + SDP_VSC_VALID_DATA_BYTES_PSR2 = 12, SDP_VSC_VALID_DATA_BYTES_PSR2_COLOR = 19, SDP_VSC_VALID_DATA_BYTES_PR = 16, SDP_VSC_VALID_DATA_BYTES_PR_COLOR = 19, @@ -161,7 +161,7 @@ typedef enum tagSDP_VSC_COLOR_FMT_Y_COLORIMETRY typedef struct tagDPSDP_DP_VSC_SDP_DESCRIPTOR { NvU8 dataSize; // the db data size - + // header struct { @@ -174,11 +174,11 @@ typedef struct tagDPSDP_DP_VSC_SDP_DESCRIPTOR } hb; // data content - struct + struct { - // Stereo field. Note: Needs to be expanded when needed. Refer to DP1.3 spec. + // Stereo field. Note: Needs to be expanded when needed. Refer to DP1.3 spec. NvU8 stereoInterface; // DB0 - // PSR Field. Note: Needs to be expanded when needed. Refer to DP1.3 spec. + // PSR Field. Note: Needs to be expanded when needed. Refer to DP1.3 spec. NvU8 psrState : 1; //DB1 NvU8 psrUpdateRfb : 1; NvU8 psrCrcValid : 1; @@ -203,7 +203,7 @@ typedef struct tagDPSDP_DP_VSC_SDP_DESCRIPTOR NvU8 db14; NvU8 db15; - // Colorimetry Infoframe Secondary Data Package following DP1.3 spec + // Colorimetry Infoframe Secondary Data Package following DP1.3 spec NvU8 colorimetryFormat : 4; // DB16 infoframe per DP1.3 spec NvU8 pixEncoding : 4; // DB16 infoframe per DP1.3 spec @@ -229,7 +229,7 @@ typedef struct tagDPSDP_DP_VSC_SDP_DESCRIPTOR typedef struct tagDPSDP_DP_PR_VSC_SDP_DESCRIPTOR { NvU8 dataSize; // the db data size - + // header struct { @@ -242,11 +242,11 @@ typedef struct tagDPSDP_DP_PR_VSC_SDP_DESCRIPTOR } hb; // data content - struct + struct { - // Stereo field. Note: Needs to be expanded when needed. Refer to DP1.3 spec. + // Stereo field. Note: Needs to be expanded when needed. Refer to DP1.3 spec. NvU8 stereoInterface; // DB0 - // PSR Field. Note: Needs to be expanded when needed. Refer to DP1.3 spec. + // PSR Field. Note: Needs to be expanded when needed. Refer to DP1.3 spec. NvU8 prState : 1; // DB1 NvU8 prReserved : 1; // Always ZERO NvU8 prCrcValid : 1; @@ -268,7 +268,7 @@ typedef struct tagDPSDP_DP_PR_VSC_SDP_DESCRIPTOR NvU8 db14; NvU8 db15; - // Colorimetry Infoframe Secondary Data Package following DP1.3 spec + // Colorimetry Infoframe Secondary Data Package following DP1.3 spec NvU8 colorimetryFormat : 4; // DB16 infoframe per DP1.3 spec NvU8 pixEncoding : 4; // DB16 infoframe per DP1.3 spec @@ -294,12 +294,12 @@ typedef struct tagDPSDP_DP_PR_VSC_SDP_DESCRIPTOR typedef struct tagDPSDP_DESCRIPTOR { NvU8 dataSize; - + // header byte - struct + struct { NvU8 hb0; - NvU8 hb1; + NvU8 hb1; NvU8 hb2; NvU8 hb3; } hb; @@ -308,7 +308,7 @@ typedef struct tagDPSDP_DESCRIPTOR struct { NvU8 db0; - NvU8 db1; + NvU8 db1; NvU8 db2; NvU8 db3; NvU8 db4; diff --git a/src/common/modeset/timing/edid.h b/src/common/modeset/timing/edid.h index fec2ff732..ac2392c38 100644 --- a/src/common/modeset/timing/edid.h +++ b/src/common/modeset/timing/edid.h @@ -30,12 +30,12 @@ #ifndef __EDID_H_ #define __EDID_H_ -#include "nvtiming.h" #include "nvtiming_pvt.h" +#include "displayid.h" +#include "displayid20.h" // EDID 1.x detailed timing template - #define NVT_PVT_EDID_LDD_PAYLOAD_SIZE 13 typedef struct _tagEDID_LONG_DISPLAY_DESCRIPTOR @@ -286,7 +286,6 @@ typedef struct _tagEIA861EXTENSION NvU8 checksum; // 0x7F }EIA861EXTENSION; - typedef struct _tagVTBEXTENSION { NvU8 tag; // 0x00 @@ -298,6 +297,18 @@ typedef struct _tagVTBEXTENSION NvU8 checksum; }VTBEXTENSION; +// EDID DisplayID extension block template +typedef struct _tagDIDEXTENSION +{ + NvU8 tag; // 0x00 + NvU8 struct_version; // 0x01 + NvU8 length; // 0x02 + NvU8 use_case; // 0x03 + NvU8 ext_count; // 0x04 + NvU8 data[NVT_DID_MAX_EXT_PAYLOAD]; // 0x05 - 0x7E + NvU8 checksum; // 0x7F +}DIDEXTENSION; + // video signal interface mask #define NVT_PVT_EDID_INPUT_ISDIGITAL_MASK 0x80 // 0==analog #define NVT_PVT_EDID_INPUT_ISDIGITAL_SHIFT 7 diff --git a/src/common/modeset/timing/nvt_displayid20.c b/src/common/modeset/timing/nvt_displayid20.c index 234ca64fb..072d36159 100644 --- a/src/common/modeset/timing/nvt_displayid20.c +++ b/src/common/modeset/timing/nvt_displayid20.c @@ -42,19 +42,22 @@ static NVT_STATUS parseDisplayId20SectionDataBlocks(const DISPLAYID_2_0_SECTION static NVT_STATUS parseDisplayId20ExtensionSection(const DISPLAYID_2_0_SECTION *pSection, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // DisplayID20 Data Block Tag Alloction -static NVT_STATUS parseDisplayId20ProductIdentity(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_PRODUCT_IDENTITY *pProductIdentity); // 0x20 Product Identificaton Block Tag -static NVT_STATUS parseDisplayId20DisplayParam(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_DISPLAY_PARAMETERS *pDisplayParam); // 0x21 Display Parameters -static NVT_STATUS parseDisplayId20Timing7(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x22 Type VII Timing - Detailed Timing -static NVT_STATUS parseDisplayId20Timing8(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x23 Type VIII Timing - Enumerated Timing -static NVT_STATUS parseDisplayId20Timing9(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x24 Type IX Timing - Formula-based -static NVT_STATUS parseDisplayId20Timing10(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x24 Type X Timing - Formula-based RR up to 1024Hz -static NVT_STATUS parseDisplayId20RangeLimit(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_RANGE_LIMITS *pRangeLimits); // 0x25 Dynamic Video Timing Range Limits -static NVT_STATUS parseDisplayId20DisplayInterfaceFeatures(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_INTERFACE_FEATURES *pInterfaceFeatures); // 0x26 Display Interface Features -static NVT_STATUS parseDisplayId20Stereo(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x27 Stereo Display Interface -static NVT_STATUS parseDisplayId20TiledDisplay(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_TILED_DISPLAY_TOPOLOGY *pTileTopo); // 0x28 Tiled Display Topology -static NVT_STATUS parseDisplayId20ContainerId(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_CONTAINERID *pContainerId); // 0x29 ContainerID -static NVT_STATUS parseDisplayId20VendorSpecific(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_VENDOR_SPECIFIC *pVendorSpecific); // 0x7E Vendor-specific -static NVT_STATUS parseDisplayId20CtaData(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x81 CTA DisplayID +static NVT_STATUS parseDisplayId20ProductIdentity(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x20 Product Identificaton Block Tag +static NVT_STATUS parseDisplayId20DisplayParam(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x21 Display Parameters +static NVT_STATUS parseDisplayId20Timing7(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x22 Type VII Timing - Detailed Timing +static NVT_STATUS parseDisplayId20Timing8(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x23 Type VIII Timing - Enumerated Timing +static NVT_STATUS parseDisplayId20Timing9(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x24 Type IX Timing - Formula-based +static NVT_STATUS parseDisplayId20RangeLimit(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x25 Dynamic Video Timing Range Limits +static NVT_STATUS parseDisplayId20DisplayInterfaceFeatures(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x26 Display Interface Features +static NVT_STATUS parseDisplayId20Stereo(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x27 Stereo Display Interface +static NVT_STATUS parseDisplayId20TiledDisplay(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x28 Tiled Display Topology +static NVT_STATUS parseDisplayId20ContainerId(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x29 ContainerID +static NVT_STATUS parseDisplayId20Timing10(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2A Type X Timing - Formula-based RR up to 1024Hz +static NVT_STATUS parseDisplayId20AdaptiveSync(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2B Adaptive-Sync +static NVT_STATUS parseDisplayId20ARVRHMD(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2C ARVR HMD +static NVT_STATUS parseDisplayId20ARVRLayer(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2D ARVR Layer +static NVT_STATUS parseDisplayId20VendorSpecific(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x7E Vendor-specific +static NVT_STATUS parseDisplayId20CtaData(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x81 CTA DisplayID // Helper function static NVT_STATUS getPrimaryUseCase(NvU8 product_type, NVT_DISPLAYID_PRODUCT_PRIMARY_USE_CASE *primary_use_case); @@ -155,7 +158,7 @@ NvU32 NvTiming_DisplayID2ValidationMask( if (!pDisplayId20Info->valid_data_blocks.product_id_present) { - ret |= NVT_DID2_VALIDATION_ERR_MASK(NVT_DID2_VALIDATION_ERR_PRODUCT_ID); + ret |= NVT_DID2_VALIDATION_ERR_MASK(NVT_DID2_VALIDATION_ERR_PRODUCT_IDENTIFY); } if (pDisplayId20Info->primary_use_case >= PRODUCT_PRIMARY_USE_GENERIC_DISPLAY && @@ -362,6 +365,18 @@ parseDisplayId20SectionDataBlocks( case DISPLAYID_2_0_BLOCK_TYPE_CONTAINER_ID: pDisplayIdInfo->valid_data_blocks.container_id_present = NV_TRUE; break; + case DISPLAYID_2_0_BLOCK_TYPE_TIMING_10: + pDisplayIdInfo->valid_data_blocks.type10Timing_present = NV_TRUE; + break; + case DISPLAYID_2_0_BLOCK_TYPE_ADAPTIVE_SYNC: + pDisplayIdInfo->valid_data_blocks.adaptive_sync_present = NV_TRUE; + break; + case DISPLAYID_2_0_BLOCK_TYPE_ARVR_HMD: + pDisplayIdInfo->valid_data_blocks.arvr_hmd_present = NV_TRUE; + break; + case DISPLAYID_2_0_BLOCK_TYPE_ARVR_LAYER: + pDisplayIdInfo->valid_data_blocks.arvr_layer_present = NV_TRUE; + break; case DISPLAYID_2_0_BLOCK_TYPE_VENDOR_SPEC: pDisplayIdInfo->valid_data_blocks.vendor_specific_present = NV_TRUE; break; @@ -390,10 +405,10 @@ parseDisplayId20DataBlock( switch (pDataBlock->type) { case DISPLAYID_2_0_BLOCK_TYPE_PRODUCT_IDENTITY: - status = parseDisplayId20ProductIdentity(pDataBlock, &pDisplayIdInfo->product_identity); + status = parseDisplayId20ProductIdentity(pDataBlock, pDisplayIdInfo); break; case DISPLAYID_2_0_BLOCK_TYPE_DISPLAY_PARAM: - status = parseDisplayId20DisplayParam(pDataBlock, &pDisplayIdInfo->display_param); + status = parseDisplayId20DisplayParam(pDataBlock, pDisplayIdInfo); break; case DISPLAYID_2_0_BLOCK_TYPE_TIMING_7: status = parseDisplayId20Timing7(pDataBlock, pDisplayIdInfo); @@ -408,22 +423,31 @@ parseDisplayId20DataBlock( status = parseDisplayId20Timing10(pDataBlock, pDisplayIdInfo); break; case DISPLAYID_2_0_BLOCK_TYPE_RANGE_LIMITS: - status = parseDisplayId20RangeLimit(pDataBlock, &pDisplayIdInfo->range_limits); + status = parseDisplayId20RangeLimit(pDataBlock, pDisplayIdInfo); break; case DISPLAYID_2_0_BLOCK_TYPE_INTERFACE_FEATURES: - status = parseDisplayId20DisplayInterfaceFeatures(pDataBlock, &pDisplayIdInfo->interface_features); + status = parseDisplayId20DisplayInterfaceFeatures(pDataBlock, pDisplayIdInfo); break; case DISPLAYID_2_0_BLOCK_TYPE_STEREO: status = parseDisplayId20Stereo(pDataBlock, pDisplayIdInfo); break; case DISPLAYID_2_0_BLOCK_TYPE_TILED_DISPLAY: - status = parseDisplayId20TiledDisplay(pDataBlock, &pDisplayIdInfo->tile_topo); + status = parseDisplayId20TiledDisplay(pDataBlock, pDisplayIdInfo); break; case DISPLAYID_2_0_BLOCK_TYPE_CONTAINER_ID: - status = parseDisplayId20ContainerId(pDataBlock, &pDisplayIdInfo->container_id); + status = parseDisplayId20ContainerId(pDataBlock, pDisplayIdInfo); + break; + case DISPLAYID_2_0_BLOCK_TYPE_ADAPTIVE_SYNC: + status = parseDisplayId20AdaptiveSync(pDataBlock, pDisplayIdInfo); + break; + case DISPLAYID_2_0_BLOCK_TYPE_ARVR_HMD: + status = parseDisplayId20ARVRHMD(pDataBlock, pDisplayIdInfo); + break; + case DISPLAYID_2_0_BLOCK_TYPE_ARVR_LAYER: + status = parseDisplayId20ARVRLayer(pDataBlock, pDisplayIdInfo); break; case DISPLAYID_2_0_BLOCK_TYPE_VENDOR_SPEC: - status = parseDisplayId20VendorSpecific(pDataBlock, &pDisplayIdInfo->vendor_specific); + status = parseDisplayId20VendorSpecific(pDataBlock, pDisplayIdInfo); break; case DISPLAYID_2_0_BLOCK_TYPE_CTA_DATA: status = parseDisplayId20CtaData(pDataBlock, pDisplayIdInfo); @@ -439,42 +463,42 @@ CODE_SEGMENT(PAGE_DD_CODE) NVT_STATUS parseDisplayId20ProductIdentity( const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, - NVT_DISPLAYID_PRODUCT_IDENTITY *pProductIdentity) + NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo) { - NVT_STATUS status = NVT_STATUS_SUCCESS; - const DISPLAYID_2_0_PROD_IDENTIFICATION_BLOCK *pProductIdBlock = NULL; + NVT_STATUS status = NVT_STATUS_SUCCESS; + NVT_DISPLAYID_PRODUCT_IDENTITY *pProductIdentity = NULL; + const DISPLAYID_2_0_PROD_IDENTIFICATION_BLOCK *pProductIdBlock = NULL; - if (pDataBlock->type == DISPLAYID_2_0_BLOCK_TYPE_PRODUCT_IDENTITY) + pProductIdBlock = (const DISPLAYID_2_0_PROD_IDENTIFICATION_BLOCK *)pDataBlock; + + // add more validation if needed + + if (pDisplayIdInfo == NULL) return status; + + pProductIdentity = &pDisplayIdInfo->product_identity; + + pProductIdentity->vendor_id = (pProductIdBlock->vendor[0] << 16) | + (pProductIdBlock->vendor[1] << 8) | + (pProductIdBlock->vendor[2]); + pProductIdentity->product_id = (pProductIdBlock->product_code[0]) | + (pProductIdBlock->product_code[1] << 8); + pProductIdentity->serial_number = (pProductIdBlock->serial_number[0]) | + (pProductIdBlock->serial_number[1] << 8) | + (pProductIdBlock->serial_number[2] << 16) | + (pProductIdBlock->serial_number[3] << 24); + pProductIdentity->week = (pProductIdBlock->model_tag >= 1 && pProductIdBlock->model_tag <= 52) ? + pProductIdBlock->model_tag : 0; + pProductIdentity->year = (pProductIdBlock->model_tag == 0xFF) ? + pProductIdBlock->model_year : + pProductIdBlock->model_year + 2000; + + if (pProductIdBlock->product_name_string_size != 0) { - pProductIdBlock = (const DISPLAYID_2_0_PROD_IDENTIFICATION_BLOCK *)pDataBlock; - - pProductIdentity->vendor_id = (pProductIdBlock->vendor[0] << 16) | - (pProductIdBlock->vendor[1] << 8) | - (pProductIdBlock->vendor[2]); - pProductIdentity->product_id = (pProductIdBlock->product_code[0]) | - (pProductIdBlock->product_code[1] << 8); - pProductIdentity->serial_number = (pProductIdBlock->serial_number[0]) | - (pProductIdBlock->serial_number[1] << 8) | - (pProductIdBlock->serial_number[2] << 16) | - (pProductIdBlock->serial_number[3] << 24); - pProductIdentity->week = (pProductIdBlock->model_tag >= 1 && pProductIdBlock->model_tag <= 52) ? - pProductIdBlock->model_tag : 0; - pProductIdentity->year = (pProductIdBlock->model_tag == 0xFF) ? - pProductIdBlock->model_year : - pProductIdBlock->model_year + 2000; - - if (pProductIdBlock->product_name_string_size != 0) - { - NVMISC_STRNCPY((char *)pProductIdentity->product_string, - (const char *)pProductIdBlock->product_name_string, - pProductIdBlock->product_name_string_size); - } - pProductIdentity->product_string[pProductIdBlock->product_name_string_size] = '\0'; - } - else - { - return NVT_STATUS_ERR; + NVMISC_STRNCPY((char *)pProductIdentity->product_string, + (const char *)pProductIdBlock->product_name_string, + pProductIdBlock->product_name_string_size); } + pProductIdentity->product_string[pProductIdBlock->product_name_string_size] = '\0'; return status; } @@ -484,91 +508,94 @@ CODE_SEGMENT(PAGE_DD_CODE) static NVT_STATUS parseDisplayId20DisplayParam( const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, - NVT_DISPLAYID_DISPLAY_PARAMETERS *pDisplayParam) + NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo) { - NVT_STATUS status = NVT_STATUS_SUCCESS; - const DISPLAYID_2_0_DISPLAY_PARAM_BLOCK *pDisplayParamBlock = NULL; + NVT_STATUS status = NVT_STATUS_SUCCESS; + const DISPLAYID_2_0_DISPLAY_PARAM_BLOCK *pDisplayParamBlock = NULL; + NVT_DISPLAYID_DISPLAY_PARAMETERS *pDisplayParam = NULL; - if ((pDataBlock->type == DISPLAYID_2_0_BLOCK_TYPE_DISPLAY_PARAM) && - (pDataBlock->data_bytes == DISPLAYID_2_0_DISPLAY_PARAM_BLOCK_PAYLOAD_LENGTH)) + if (pDataBlock->data_bytes != DISPLAYID_2_0_DISPLAY_PARAM_BLOCK_PAYLOAD_LENGTH) { - pDisplayParamBlock = (const DISPLAYID_2_0_DISPLAY_PARAM_BLOCK *)pDataBlock; + return NVT_STATUS_ERR; + } - pDisplayParam->revision = pDisplayParamBlock->header.revision; - pDisplayParam->h_image_size_micro_meter = (pDisplayParamBlock->horizontal_image_size[1] << 8 | - pDisplayParamBlock->horizontal_image_size[0]) * - (pDisplayParamBlock->header.image_size_multiplier ? 1000 : 100); - pDisplayParam->v_image_size_micro_meter = (pDisplayParamBlock->vertical_image_size[1] << 8 | - pDisplayParamBlock->vertical_image_size[0]) * - (pDisplayParamBlock->header.image_size_multiplier ? 1000 : 100); - pDisplayParam->h_pixels = pDisplayParamBlock->horizontal_pixel_count[1] << 8 | - pDisplayParamBlock->horizontal_pixel_count[0]; - pDisplayParam->v_pixels = pDisplayParamBlock->vertical_pixel_count[1] << 8 | - pDisplayParamBlock->vertical_pixel_count[0]; + // Add more validation here if needed - pDisplayParam->scan_orientation = pDisplayParamBlock->feature.scan_orientation; - pDisplayParam->audio_speakers_integrated = pDisplayParamBlock->feature.audio_speaker_information ? AUDIO_SPEAKER_INTEGRATED_NOT_SUPPORTED : AUDIO_SPEAKER_INTEGRATED_SUPPORTED; - pDisplayParam->color_map_standard = pDisplayParamBlock->feature.color_information ? COLOR_MAP_CIE_1976 : COLOR_MAP_CIE_1931; + if (pDisplayIdInfo == NULL) return status; - // 12 bits Binary Fraction Representations - pDisplayParam->primaries[0].x = pDisplayParamBlock->primary_color_1_chromaticity.color_bits_mid.color_x_bits_high << 8 | - pDisplayParamBlock->primary_color_1_chromaticity.color_x_bits_low; - pDisplayParam->primaries[0].y = pDisplayParamBlock->primary_color_1_chromaticity.color_y_bits_high << 4 | - pDisplayParamBlock->primary_color_1_chromaticity.color_bits_mid.color_y_bits_low; - pDisplayParam->primaries[1].x = pDisplayParamBlock->primary_color_2_chromaticity.color_bits_mid.color_x_bits_high << 8 | - pDisplayParamBlock->primary_color_2_chromaticity.color_x_bits_low; - pDisplayParam->primaries[1].y = pDisplayParamBlock->primary_color_2_chromaticity.color_y_bits_high << 4 | - pDisplayParamBlock->primary_color_2_chromaticity.color_bits_mid.color_y_bits_low; - pDisplayParam->primaries[2].x = pDisplayParamBlock->primary_color_3_chromaticity.color_bits_mid.color_x_bits_high << 8 | - pDisplayParamBlock->primary_color_3_chromaticity.color_x_bits_low; - pDisplayParam->primaries[2].y = pDisplayParamBlock->primary_color_3_chromaticity.color_y_bits_high << 4 | - pDisplayParamBlock->primary_color_3_chromaticity.color_bits_mid.color_y_bits_low; - pDisplayParam->white.x = pDisplayParamBlock->white_point_chromaticity.color_bits_mid.color_x_bits_high << 8 | - pDisplayParamBlock->white_point_chromaticity.color_x_bits_low; - pDisplayParam->white.y = pDisplayParamBlock->white_point_chromaticity.color_y_bits_high << 4 | - pDisplayParamBlock->white_point_chromaticity.color_bits_mid.color_y_bits_low; + pDisplayParamBlock = (const DISPLAYID_2_0_DISPLAY_PARAM_BLOCK *)pDataBlock; + pDisplayParam = &pDisplayIdInfo->display_param; - // IEEE 754 half-precision binary floating-point format - pDisplayParam->native_max_luminance_full_coverage = pDisplayParamBlock->max_luminance_full_coverage[1] << 8 | - pDisplayParamBlock->max_luminance_full_coverage[0]; - pDisplayParam->native_max_luminance_1_percent_rect_coverage = pDisplayParamBlock->max_luminance_1_percent_rectangular_coverage[1] << 8 | - pDisplayParamBlock->max_luminance_1_percent_rectangular_coverage[0]; - pDisplayParam->native_min_luminance = pDisplayParamBlock->min_luminance[1] << 8 | - pDisplayParamBlock->min_luminance[0]; + pDisplayParam->revision = pDisplayParamBlock->header.revision; + pDisplayParam->h_image_size_micro_meter = (pDisplayParamBlock->horizontal_image_size[1] << 8 | + pDisplayParamBlock->horizontal_image_size[0]) * + (pDisplayParamBlock->header.image_size_multiplier ? 1000 : 100); + pDisplayParam->v_image_size_micro_meter = (pDisplayParamBlock->vertical_image_size[1] << 8 | + pDisplayParamBlock->vertical_image_size[0]) * + (pDisplayParamBlock->header.image_size_multiplier ? 1000 : 100); + pDisplayParam->h_pixels = pDisplayParamBlock->horizontal_pixel_count[1] << 8 | + pDisplayParamBlock->horizontal_pixel_count[0]; + pDisplayParam->v_pixels = pDisplayParamBlock->vertical_pixel_count[1] << 8 | + pDisplayParamBlock->vertical_pixel_count[0]; - if (pDisplayParamBlock->feature.luminance_information == 0) - { - pDisplayParam->native_luminance_info = NATIVE_LUMINANCE_INFO_MIN_GURANTEE_VALUE; - } - else if (pDisplayParamBlock->feature.luminance_information == 1) - { - pDisplayParam->native_luminance_info = NATIVE_LUMINANCE_INFO_SOURCE_DEVICE_GUIDANCE; - } - else - { - return NVT_STATUS_ERR; - } + pDisplayParam->scan_orientation = pDisplayParamBlock->feature.scan_orientation; + pDisplayParam->audio_speakers_integrated = pDisplayParamBlock->feature.audio_speaker_information ? AUDIO_SPEAKER_INTEGRATED_NOT_SUPPORTED : AUDIO_SPEAKER_INTEGRATED_SUPPORTED; + pDisplayParam->color_map_standard = pDisplayParamBlock->feature.color_information ? COLOR_MAP_CIE_1976 : COLOR_MAP_CIE_1931; - UPDATE_BPC_FOR_COLORFORMAT(pDisplayParam->native_color_depth, - pDisplayParamBlock->color_depth_and_device_technology.color_depth == NATIVE_COLOR_BPC_6, - pDisplayParamBlock->color_depth_and_device_technology.color_depth == NATIVE_COLOR_BPC_8, - pDisplayParamBlock->color_depth_and_device_technology.color_depth == NATIVE_COLOR_BPC_10, - pDisplayParamBlock->color_depth_and_device_technology.color_depth == NATIVE_COLOR_BPC_12, - 0, - pDisplayParamBlock->color_depth_and_device_technology.color_depth == NATIVE_COLOR_BPC_16); + // 12 bits Binary Fraction Representations + pDisplayParam->primaries[0].x = pDisplayParamBlock->primary_color_1_chromaticity.color_bits_mid.color_x_bits_high << 8 | + pDisplayParamBlock->primary_color_1_chromaticity.color_x_bits_low; + pDisplayParam->primaries[0].y = pDisplayParamBlock->primary_color_1_chromaticity.color_y_bits_high << 4 | + pDisplayParamBlock->primary_color_1_chromaticity.color_bits_mid.color_y_bits_low; + pDisplayParam->primaries[1].x = pDisplayParamBlock->primary_color_2_chromaticity.color_bits_mid.color_x_bits_high << 8 | + pDisplayParamBlock->primary_color_2_chromaticity.color_x_bits_low; + pDisplayParam->primaries[1].y = pDisplayParamBlock->primary_color_2_chromaticity.color_y_bits_high << 4 | + pDisplayParamBlock->primary_color_2_chromaticity.color_bits_mid.color_y_bits_low; + pDisplayParam->primaries[2].x = pDisplayParamBlock->primary_color_3_chromaticity.color_bits_mid.color_x_bits_high << 8 | + pDisplayParamBlock->primary_color_3_chromaticity.color_x_bits_low; + pDisplayParam->primaries[2].y = pDisplayParamBlock->primary_color_3_chromaticity.color_y_bits_high << 4 | + pDisplayParamBlock->primary_color_3_chromaticity.color_bits_mid.color_y_bits_low; + pDisplayParam->white.x = pDisplayParamBlock->white_point_chromaticity.color_bits_mid.color_x_bits_high << 8 | + pDisplayParamBlock->white_point_chromaticity.color_x_bits_low; + pDisplayParam->white.y = pDisplayParamBlock->white_point_chromaticity.color_y_bits_high << 4 | + pDisplayParamBlock->white_point_chromaticity.color_bits_mid.color_y_bits_low; - pDisplayParam->device_technology = pDisplayParamBlock->color_depth_and_device_technology.device_technology; - if (pDisplayParam->revision == 1) - { - pDisplayParam->device_theme_Preference = pDisplayParamBlock->color_depth_and_device_technology.device_theme_preference; - } - pDisplayParam->gamma_x100 = (pDisplayParamBlock->gamma_EOTF + 100); + // IEEE 754 half-precision binary floating-point format + pDisplayParam->native_max_luminance_full_coverage = pDisplayParamBlock->max_luminance_full_coverage[1] << 8 | + pDisplayParamBlock->max_luminance_full_coverage[0]; + pDisplayParam->native_max_luminance_1_percent_rect_coverage = pDisplayParamBlock->max_luminance_1_percent_rectangular_coverage[1] << 8 | + pDisplayParamBlock->max_luminance_1_percent_rectangular_coverage[0]; + pDisplayParam->native_min_luminance = pDisplayParamBlock->min_luminance[1] << 8 | + pDisplayParamBlock->min_luminance[0]; + + if (pDisplayParamBlock->feature.luminance_information == 0) + { + pDisplayParam->native_luminance_info = NATIVE_LUMINANCE_INFO_MIN_GURANTEE_VALUE; + } + else if (pDisplayParamBlock->feature.luminance_information == 1) + { + pDisplayParam->native_luminance_info = NATIVE_LUMINANCE_INFO_SOURCE_DEVICE_GUIDANCE; } else { return NVT_STATUS_ERR; } + UPDATE_BPC_FOR_COLORFORMAT(pDisplayParam->native_color_depth, + pDisplayParamBlock->color_depth_and_device_technology.color_depth == NATIVE_COLOR_BPC_6, + pDisplayParamBlock->color_depth_and_device_technology.color_depth == NATIVE_COLOR_BPC_8, + pDisplayParamBlock->color_depth_and_device_technology.color_depth == NATIVE_COLOR_BPC_10, + pDisplayParamBlock->color_depth_and_device_technology.color_depth == NATIVE_COLOR_BPC_12, + 0, + pDisplayParamBlock->color_depth_and_device_technology.color_depth == NATIVE_COLOR_BPC_16); + + pDisplayParam->device_technology = pDisplayParamBlock->color_depth_and_device_technology.device_technology; + if (pDisplayParam->revision == 1) + { + pDisplayParam->device_theme_Preference = pDisplayParamBlock->color_depth_and_device_technology.device_theme_preference; + } + pDisplayParam->gamma_x100 = (pDisplayParamBlock->gamma_EOTF + 100); + return status; } @@ -587,12 +614,6 @@ parseDisplayId20Timing7( NVT_TIMING newTiming; - if (pDataBlock->type != DISPLAYID_2_0_BLOCK_TYPE_TIMING_7) - { - nvt_assert(0); - return NVT_STATUS_ERR; - } - pTiming7Block = (const DISPLAYID_2_0_TIMING_7_BLOCK *)pDataBlock; // Based on the DisplayID_2_0_E7 spec: @@ -613,8 +634,11 @@ parseDisplayId20Timing7( return NVT_STATUS_ERR; } - startSeqNumber = getExistedTimingSeqNumber(pDisplayIdInfo, NVT_TYPE_DISPLAYID_7); - + if (pDisplayIdInfo != NULL) + { + startSeqNumber = getExistedTimingSeqNumber(pDisplayIdInfo, NVT_TYPE_DISPLAYID_7); + } + for (i = 0; i < descriptorCount; i++) { NVMISC_MEMSET(&newTiming, 0, sizeof(newTiming)); @@ -625,6 +649,10 @@ parseDisplayId20Timing7( break; } } + else + { + if (pDisplayIdInfo == NULL) return NVT_STATUS_ERR; + } } } @@ -645,13 +673,6 @@ parseDisplayId20Timing8( NvU8 startSeqNumber = 0; NvU8 i; - - if (pDataBlock->type != DISPLAYID_2_0_BLOCK_TYPE_TIMING_8) - { - nvt_assert(0); - return NVT_STATUS_ERR; - } - pTiming8Block = (const DISPLAYID_2_0_TIMING_8_BLOCK *)pDataBlock; // 1-byte descriptor timing code @@ -669,7 +690,11 @@ parseDisplayId20Timing8( } codeType = pTiming8Block->header.timing_code_type; - startSeqNumber = getExistedTimingSeqNumber(pDisplayIdInfo, NVT_TYPE_DISPLAYID_8); + + if (pDisplayIdInfo != NULL) + { + startSeqNumber = getExistedTimingSeqNumber(pDisplayIdInfo, NVT_TYPE_DISPLAYID_8); + } for (i = 0; i < codeCount; i++) { @@ -680,6 +705,7 @@ parseDisplayId20Timing8( if (NvTiming_EnumDMT((NvU32)(pTiming8Block->timing_code_1[i].timing_code), &newTiming) != NVT_STATUS_SUCCESS) { + if (pDisplayIdInfo == NULL) return NVT_STATUS_ERR; break; } } @@ -688,6 +714,7 @@ parseDisplayId20Timing8( if (NvTiming_EnumCEA861bTiming((NvU32)(pTiming8Block->timing_code_1[i].timing_code), &newTiming) != NVT_STATUS_SUCCESS) { + if (pDisplayIdInfo == NULL) return NVT_STATUS_ERR; break; } } @@ -696,6 +723,7 @@ parseDisplayId20Timing8( if (NvTiming_EnumHdmiVsdbExtendedTiming((NvU32)(pTiming8Block->timing_code_1[i].timing_code), &newTiming) != NVT_STATUS_SUCCESS) { + if (pDisplayIdInfo == NULL) return NVT_STATUS_ERR; break; } } @@ -705,7 +733,7 @@ parseDisplayId20Timing8( break; } - newTiming.etc.flag |= ((pTiming8Block->header.revision >= 1) && pTiming8Block->header.is_support_yuv420) ? NVT_FLAG_DISPLAYID_2_0_EXPLICT_YUV420 : 0; + newTiming.etc.flag |= ((pTiming8Block->header.revision >= 1) && pTiming8Block->header.is_support_yuv420) ? NVT_FLAG_DISPLAYID_T7_T8_EXPLICT_YUV420 : 0; newTiming.etc.status = NVT_STATUS_DISPLAYID_8N(++startSeqNumber); NVT_SNPRINTF((char *)newTiming.etc.name, sizeof(newTiming.etc.name), "DID20-Type8:#%3d:%dx%dx%3d.%03dHz/%s", @@ -743,12 +771,6 @@ parseDisplayId20Timing9( NvU8 startSeqNumber = 0; NvU8 i = 0; - if (pDataBlock->type != DISPLAYID_2_0_BLOCK_TYPE_TIMING_9) - { - nvt_assert(0); - return NVT_STATUS_ERR; - } - descriptorCount = pDataBlock->data_bytes / sizeof(DISPLAYID_2_0_TIMING_9_DESCRIPTOR); if (descriptorCount < 1 || descriptorCount > DISPLAYID_2_0_TIMING_9_MAX_DESCRIPTORS) { @@ -758,7 +780,10 @@ parseDisplayId20Timing9( pTiming9Block = (const DISPLAYID_2_0_TIMING_9_BLOCK *)pDataBlock; - startSeqNumber = getExistedTimingSeqNumber(pDisplayIdInfo, NVT_TYPE_DISPLAYID_9); + if (pDisplayIdInfo != NULL) + { + startSeqNumber = getExistedTimingSeqNumber(pDisplayIdInfo, NVT_TYPE_DISPLAYID_9); + } for (i = 0; i < descriptorCount; i++) { @@ -771,6 +796,10 @@ parseDisplayId20Timing9( break; } } + else + { + if (pDisplayIdInfo == NULL) return NVT_STATUS_ERR; + } } return status; @@ -787,6 +816,7 @@ parseDisplayId20Timing10( NvU32 descriptorCount = 0; NvU8 startSeqNumber = 0; NvU8 i = 0; + NvU8 eachOfDescriptorsSize = sizeof(DISPLAYID_2_0_TIMING_10_6BYTES_DESCRIPTOR); NVT_TIMING newTiming; @@ -819,19 +849,28 @@ parseDisplayId20Timing10( } } - startSeqNumber = getExistedTimingSeqNumber(pDisplayIdInfo, NVT_TYPE_DISPLAYID_10); + eachOfDescriptorsSize += pTiming10Block->header.payload_bytes_len; + + if (pDisplayIdInfo != NULL) + { + startSeqNumber = getExistedTimingSeqNumber(pDisplayIdInfo, NVT_TYPE_DISPLAYID_10); + } for (i = 0; i < descriptorCount; i++) { NVMISC_MEMSET(&newTiming, 0, sizeof(newTiming)); - if (NVT_STATUS_SUCCESS == parseDisplayId20Timing10Descriptor(&pTiming10Block->descriptors[i], &newTiming, pTiming10Block->header.payload_bytes_len, startSeqNumber+i)) + if (NVT_STATUS_SUCCESS == parseDisplayId20Timing10Descriptor(&pTiming10Block->descriptors[i*eachOfDescriptorsSize], &newTiming, pTiming10Block->header.payload_bytes_len, startSeqNumber+i)) { if (!assignNextAvailableDisplayId20Timing(pDisplayIdInfo, &newTiming)) { break; } } + else + { + if (pDisplayIdInfo == NULL) return NVT_STATUS_ERR; + } } return status; @@ -841,41 +880,54 @@ CODE_SEGMENT(PAGE_DD_CODE) static NVT_STATUS parseDisplayId20RangeLimit( const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, - NVT_DISPLAYID_RANGE_LIMITS *pRangeLimits) + NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo) { NVT_STATUS status = NVT_STATUS_SUCCESS; const DISPLAYID_2_0_RANGE_LIMITS_BLOCK *pRangeLimitsBlock = NULL; + NVT_DISPLAYID_RANGE_LIMITS rangeLimits = {0}; - if ((pDataBlock->type == DISPLAYID_2_0_BLOCK_TYPE_RANGE_LIMITS) && - (pDataBlock->data_bytes == DISPLAYID_2_0_RANGE_LIMITS_BLOCK_PAYLOAD_LENGTH)) - { - pRangeLimitsBlock = (const DISPLAYID_2_0_RANGE_LIMITS_BLOCK *)pDataBlock; - - pRangeLimits->revision = pDataBlock->revision; - - pRangeLimits->pclk_min = (pRangeLimitsBlock->pixel_clock_min[2] << 16 | - pRangeLimitsBlock->pixel_clock_min[1] << 8 | - pRangeLimitsBlock->pixel_clock_min[0]) + 1; - pRangeLimits->pclk_max = (pRangeLimitsBlock->pixel_clock_max[2] << 16 | - pRangeLimitsBlock->pixel_clock_max[1] << 8 | - pRangeLimitsBlock->pixel_clock_max[0]) + 1; - pRangeLimits->vfreq_min = pRangeLimitsBlock->vertical_frequency_min; - if (pRangeLimits->revision == 1) - { - pRangeLimits->vfreq_max = pRangeLimitsBlock->dynamic_video_timing_range_support.vertical_frequency_max_9_8 << 8 | pRangeLimitsBlock->vertical_frequency_max_7_0; - } - else - { - pRangeLimits->vfreq_max = pRangeLimitsBlock->vertical_frequency_max_7_0; - } - - pRangeLimits->seamless_dynamic_video_timing_change = pRangeLimitsBlock->dynamic_video_timing_range_support.seamless_dynamic_video_timing_change; - } - else + // basic sanity check + if (pDataBlock->data_bytes != DISPLAYID_2_0_RANGE_LIMITS_BLOCK_PAYLOAD_LENGTH) { return NVT_STATUS_ERR; } + pRangeLimitsBlock = (const DISPLAYID_2_0_RANGE_LIMITS_BLOCK *)pDataBlock; + + rangeLimits.revision = pDataBlock->revision; + + rangeLimits.pclk_min = (pRangeLimitsBlock->pixel_clock_min[2] << 16 | + pRangeLimitsBlock->pixel_clock_min[1] << 8 | + pRangeLimitsBlock->pixel_clock_min[0]) + 1; + rangeLimits.pclk_max = (pRangeLimitsBlock->pixel_clock_max[2] << 16 | + pRangeLimitsBlock->pixel_clock_max[1] << 8 | + pRangeLimitsBlock->pixel_clock_max[0]) + 1; + rangeLimits.vfreq_min = pRangeLimitsBlock->vertical_frequency_min; + if (rangeLimits.revision == 1) + { + rangeLimits.vfreq_max = pRangeLimitsBlock->dynamic_video_timing_range_support.vertical_frequency_max_9_8 << 8 | + pRangeLimitsBlock->vertical_frequency_max_7_0; + } + else + { + rangeLimits.vfreq_max = pRangeLimitsBlock->vertical_frequency_max_7_0; + } + + rangeLimits.seamless_dynamic_video_timing_change = pRangeLimitsBlock->dynamic_video_timing_range_support.seamless_dynamic_video_timing_change; + + if (pDisplayIdInfo == NULL) + { + if (rangeLimits.vfreq_min > rangeLimits.vfreq_max || rangeLimits.pclk_min > rangeLimits.pclk_max || + rangeLimits.vfreq_min == 0 || rangeLimits.vfreq_max == 0) + { + nvt_assert(0 && "wrong range limit"); + status = NVT_STATUS_ERR; + } + return status; + } + + NVMISC_MEMCPY(&pDisplayIdInfo->range_limits, &rangeLimits, sizeof(NVT_DISPLAYID_RANGE_LIMITS)); + return status; } @@ -889,112 +941,117 @@ CODE_SEGMENT(PAGE_DD_CODE) static NVT_STATUS parseDisplayId20DisplayInterfaceFeatures( const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, - NVT_DISPLAYID_INTERFACE_FEATURES *pInterfaceFeatures) + NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo) { NVT_STATUS status = NVT_STATUS_SUCCESS; NvU32 i = 0; const DISPLAYID_2_0_INTERFACE_FEATURES_BLOCK *pInterfaceFeaturesBlock = NULL; + NVT_DISPLAYID_INTERFACE_FEATURES *pInterfaceFeatures = NULL; - if (pDataBlock->type == DISPLAYID_2_0_BLOCK_TYPE_INTERFACE_FEATURES && - pDataBlock->data_bytes >= DISPLAYID_2_0_INTERFACE_FEATURES_BLOCK_PAYLOAD_LENGTH_MIN) - { - pInterfaceFeaturesBlock = (const DISPLAYID_2_0_INTERFACE_FEATURES_BLOCK *)pDataBlock; - pInterfaceFeatures->revision = pDataBlock->revision; - - UPDATE_BPC_FOR_COLORFORMAT(pInterfaceFeatures->rgb444, - pInterfaceFeaturesBlock->interface_color_depth_rgb.bit_per_primary_6, - pInterfaceFeaturesBlock->interface_color_depth_rgb.bit_per_primary_8, - pInterfaceFeaturesBlock->interface_color_depth_rgb.bit_per_primary_10, - pInterfaceFeaturesBlock->interface_color_depth_rgb.bit_per_primary_12, - pInterfaceFeaturesBlock->interface_color_depth_rgb.bit_per_primary_14, - pInterfaceFeaturesBlock->interface_color_depth_rgb.bit_per_primary_16); - UPDATE_BPC_FOR_COLORFORMAT(pInterfaceFeatures->yuv444, - pInterfaceFeaturesBlock->interface_color_depth_ycbcr444.bit_per_primary_6, - pInterfaceFeaturesBlock->interface_color_depth_ycbcr444.bit_per_primary_8, - pInterfaceFeaturesBlock->interface_color_depth_ycbcr444.bit_per_primary_10, - pInterfaceFeaturesBlock->interface_color_depth_ycbcr444.bit_per_primary_12, - pInterfaceFeaturesBlock->interface_color_depth_ycbcr444.bit_per_primary_14, - pInterfaceFeaturesBlock->interface_color_depth_ycbcr444.bit_per_primary_16); - UPDATE_BPC_FOR_COLORFORMAT(pInterfaceFeatures->yuv422, - 0, - pInterfaceFeaturesBlock->interface_color_depth_ycbcr422.bit_per_primary_8, - pInterfaceFeaturesBlock->interface_color_depth_ycbcr422.bit_per_primary_10, - pInterfaceFeaturesBlock->interface_color_depth_ycbcr422.bit_per_primary_12, - pInterfaceFeaturesBlock->interface_color_depth_ycbcr422.bit_per_primary_14, - pInterfaceFeaturesBlock->interface_color_depth_ycbcr422.bit_per_primary_16); - UPDATE_BPC_FOR_COLORFORMAT(pInterfaceFeatures->yuv420, - 0, - pInterfaceFeaturesBlock->interface_color_depth_ycbcr420.bit_per_primary_8, - pInterfaceFeaturesBlock->interface_color_depth_ycbcr420.bit_per_primary_10, - pInterfaceFeaturesBlock->interface_color_depth_ycbcr420.bit_per_primary_12, - pInterfaceFeaturesBlock->interface_color_depth_ycbcr420.bit_per_primary_14, - pInterfaceFeaturesBlock->interface_color_depth_ycbcr420.bit_per_primary_16); - - // * 74.25MP/s - pInterfaceFeatures->yuv420_min_pclk = pInterfaceFeaturesBlock->min_pixel_rate_ycbcr420 * - 7425; - - pInterfaceFeatures->audio_capability.support_48khz = - pInterfaceFeaturesBlock->audio_capability.sample_rate_48_khz; - pInterfaceFeatures->audio_capability.support_44_1khz = - pInterfaceFeaturesBlock->audio_capability.sample_rate_44_1_khz; - pInterfaceFeatures->audio_capability.support_32khz = - pInterfaceFeaturesBlock->audio_capability.sample_rate_32_khz; - - if (pInterfaceFeaturesBlock->color_space_and_eotf_1.color_space_srgb_eotf_srgb) - { - ADD_COLOR_SPACE_EOTF_COMBINATION(pInterfaceFeatures, - INTERFACE_COLOR_SPACE_SRGB, - INTERFACE_EOTF_SRGB); - } - if (pInterfaceFeaturesBlock->color_space_and_eotf_1.color_space_bt601_eotf_bt601) - { - ADD_COLOR_SPACE_EOTF_COMBINATION(pInterfaceFeatures, - INTERFACE_COLOR_SPACE_BT601, - INTERFACE_EOTF_BT601); - } - if (pInterfaceFeaturesBlock->color_space_and_eotf_1.color_space_bt709_eotf_bt1886) - { - ADD_COLOR_SPACE_EOTF_COMBINATION(pInterfaceFeatures, - INTERFACE_COLOR_SPACE_BT709, - INTERFACE_EOTF_BT1886); - } - if (pInterfaceFeaturesBlock->color_space_and_eotf_1.color_space_adobe_rgb_eotf_adobe_rgb) - { - ADD_COLOR_SPACE_EOTF_COMBINATION(pInterfaceFeatures, - INTERFACE_COLOR_SPACE_ADOBE_RGB, - INTERFACE_EOTF_ADOBE_RGB); - } - if (pInterfaceFeaturesBlock->color_space_and_eotf_1.color_space_dci_p3_eotf_dci_p3) - { - ADD_COLOR_SPACE_EOTF_COMBINATION(pInterfaceFeatures, - INTERFACE_COLOR_SPACE_DCI_P3, - INTERFACE_EOTF_DCI_P3); - } - if (pInterfaceFeaturesBlock->color_space_and_eotf_1.color_space_bt2020_eotf_bt2020) - { - ADD_COLOR_SPACE_EOTF_COMBINATION(pInterfaceFeatures, - INTERFACE_COLOR_SPACE_BT2020, - INTERFACE_EOTF_BT2020); - } - if (pInterfaceFeaturesBlock->color_space_and_eotf_1.color_space_bt2020_eotf_smpte_st2084) - { - ADD_COLOR_SPACE_EOTF_COMBINATION(pInterfaceFeatures, - INTERFACE_COLOR_SPACE_BT2020, - INTERFACE_EOTF_SMPTE_ST2084); - } - - for (i = 0; i < pInterfaceFeaturesBlock->additional_color_space_and_eotf_count.count; i++) - { - ADD_COLOR_SPACE_EOTF_COMBINATION(pInterfaceFeatures, - pInterfaceFeaturesBlock->additional_color_space_and_eotf[i].color_space, - pInterfaceFeaturesBlock->additional_color_space_and_eotf[i].eotf); - } - } - else + if (pDataBlock->data_bytes < DISPLAYID_2_0_INTERFACE_FEATURES_BLOCK_PAYLOAD_LENGTH_MIN) { return NVT_STATUS_ERR; } + + // Add more validation here if needed. + + if (pDisplayIdInfo == NULL) return status; + + pInterfaceFeatures = &pDisplayIdInfo->interface_features; + + pInterfaceFeaturesBlock = (const DISPLAYID_2_0_INTERFACE_FEATURES_BLOCK *)pDataBlock; + pInterfaceFeatures->revision = pDataBlock->revision; + + UPDATE_BPC_FOR_COLORFORMAT(pInterfaceFeatures->rgb444, + pInterfaceFeaturesBlock->interface_color_depth_rgb.bit_per_primary_6, + pInterfaceFeaturesBlock->interface_color_depth_rgb.bit_per_primary_8, + pInterfaceFeaturesBlock->interface_color_depth_rgb.bit_per_primary_10, + pInterfaceFeaturesBlock->interface_color_depth_rgb.bit_per_primary_12, + pInterfaceFeaturesBlock->interface_color_depth_rgb.bit_per_primary_14, + pInterfaceFeaturesBlock->interface_color_depth_rgb.bit_per_primary_16); + UPDATE_BPC_FOR_COLORFORMAT(pInterfaceFeatures->yuv444, + pInterfaceFeaturesBlock->interface_color_depth_ycbcr444.bit_per_primary_6, + pInterfaceFeaturesBlock->interface_color_depth_ycbcr444.bit_per_primary_8, + pInterfaceFeaturesBlock->interface_color_depth_ycbcr444.bit_per_primary_10, + pInterfaceFeaturesBlock->interface_color_depth_ycbcr444.bit_per_primary_12, + pInterfaceFeaturesBlock->interface_color_depth_ycbcr444.bit_per_primary_14, + pInterfaceFeaturesBlock->interface_color_depth_ycbcr444.bit_per_primary_16); + UPDATE_BPC_FOR_COLORFORMAT(pInterfaceFeatures->yuv422, + 0, + pInterfaceFeaturesBlock->interface_color_depth_ycbcr422.bit_per_primary_8, + pInterfaceFeaturesBlock->interface_color_depth_ycbcr422.bit_per_primary_10, + pInterfaceFeaturesBlock->interface_color_depth_ycbcr422.bit_per_primary_12, + pInterfaceFeaturesBlock->interface_color_depth_ycbcr422.bit_per_primary_14, + pInterfaceFeaturesBlock->interface_color_depth_ycbcr422.bit_per_primary_16); + UPDATE_BPC_FOR_COLORFORMAT(pInterfaceFeatures->yuv420, + 0, + pInterfaceFeaturesBlock->interface_color_depth_ycbcr420.bit_per_primary_8, + pInterfaceFeaturesBlock->interface_color_depth_ycbcr420.bit_per_primary_10, + pInterfaceFeaturesBlock->interface_color_depth_ycbcr420.bit_per_primary_12, + pInterfaceFeaturesBlock->interface_color_depth_ycbcr420.bit_per_primary_14, + pInterfaceFeaturesBlock->interface_color_depth_ycbcr420.bit_per_primary_16); + + // * 74.25MP/s + pInterfaceFeatures->yuv420_min_pclk = pInterfaceFeaturesBlock->min_pixel_rate_ycbcr420 * + 7425; + + pInterfaceFeatures->audio_capability.support_48khz = + pInterfaceFeaturesBlock->audio_capability.sample_rate_48_khz; + pInterfaceFeatures->audio_capability.support_44_1khz = + pInterfaceFeaturesBlock->audio_capability.sample_rate_44_1_khz; + pInterfaceFeatures->audio_capability.support_32khz = + pInterfaceFeaturesBlock->audio_capability.sample_rate_32_khz; + + if (pInterfaceFeaturesBlock->color_space_and_eotf_1.color_space_srgb_eotf_srgb) + { + ADD_COLOR_SPACE_EOTF_COMBINATION(pInterfaceFeatures, + INTERFACE_COLOR_SPACE_SRGB, + INTERFACE_EOTF_SRGB); + } + if (pInterfaceFeaturesBlock->color_space_and_eotf_1.color_space_bt601_eotf_bt601) + { + ADD_COLOR_SPACE_EOTF_COMBINATION(pInterfaceFeatures, + INTERFACE_COLOR_SPACE_BT601, + INTERFACE_EOTF_BT601); + } + if (pInterfaceFeaturesBlock->color_space_and_eotf_1.color_space_bt709_eotf_bt1886) + { + ADD_COLOR_SPACE_EOTF_COMBINATION(pInterfaceFeatures, + INTERFACE_COLOR_SPACE_BT709, + INTERFACE_EOTF_BT1886); + } + if (pInterfaceFeaturesBlock->color_space_and_eotf_1.color_space_adobe_rgb_eotf_adobe_rgb) + { + ADD_COLOR_SPACE_EOTF_COMBINATION(pInterfaceFeatures, + INTERFACE_COLOR_SPACE_ADOBE_RGB, + INTERFACE_EOTF_ADOBE_RGB); + } + if (pInterfaceFeaturesBlock->color_space_and_eotf_1.color_space_dci_p3_eotf_dci_p3) + { + ADD_COLOR_SPACE_EOTF_COMBINATION(pInterfaceFeatures, + INTERFACE_COLOR_SPACE_DCI_P3, + INTERFACE_EOTF_DCI_P3); + } + if (pInterfaceFeaturesBlock->color_space_and_eotf_1.color_space_bt2020_eotf_bt2020) + { + ADD_COLOR_SPACE_EOTF_COMBINATION(pInterfaceFeatures, + INTERFACE_COLOR_SPACE_BT2020, + INTERFACE_EOTF_BT2020); + } + if (pInterfaceFeaturesBlock->color_space_and_eotf_1.color_space_bt2020_eotf_smpte_st2084) + { + ADD_COLOR_SPACE_EOTF_COMBINATION(pInterfaceFeatures, + INTERFACE_COLOR_SPACE_BT2020, + INTERFACE_EOTF_SMPTE_ST2084); + } + + for (i = 0; i < pInterfaceFeaturesBlock->additional_color_space_and_eotf_count.count; i++) + { + ADD_COLOR_SPACE_EOTF_COMBINATION(pInterfaceFeatures, + pInterfaceFeaturesBlock->additional_color_space_and_eotf[i].color_space, + pInterfaceFeaturesBlock->additional_color_space_and_eotf[i].eotf); + } + return status; } @@ -1006,6 +1063,8 @@ parseDisplayId20Stereo( { NVT_STATUS status = NVT_STATUS_SUCCESS; + if (pDisplayIdInfo == NULL) return status; + // TODO: Implement the parsing here. return status; @@ -1015,60 +1074,62 @@ CODE_SEGMENT(PAGE_DD_CODE) static NVT_STATUS parseDisplayId20TiledDisplay( const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, - NVT_DISPLAYID_TILED_DISPLAY_TOPOLOGY *pTileTopo) + NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo) { NVT_STATUS status = NVT_STATUS_SUCCESS; const DISPLAYID_2_0_TILED_DISPLAY_BLOCK *pTiledDisplayBlock = NULL; + NVT_DISPLAYID_TILED_DISPLAY_TOPOLOGY *pTileTopo = NULL; - if ((pDataBlock->type == DISPLAYID_2_0_BLOCK_TYPE_TILED_DISPLAY) && - (pDataBlock->data_bytes == DISPLAYID_2_0_TILED_DISPLAY_BLOCK_PAYLOAD_LENGTH)) - { - pTiledDisplayBlock = (const DISPLAYID_2_0_TILED_DISPLAY_BLOCK *)pDataBlock; - - pTileTopo->revision = pDataBlock->revision; - - pTileTopo->capability.bSingleEnclosure = pTiledDisplayBlock->capability.single_enclosure; - pTileTopo->capability.bHasBezelInfo = pTiledDisplayBlock->capability.has_bezel_info; - pTileTopo->capability.multi_tile_behavior = pTiledDisplayBlock->capability.multi_tile_behavior; - pTileTopo->capability.single_tile_behavior = pTiledDisplayBlock->capability.single_tile_behavior; - - pTileTopo->topology.row = ((pTiledDisplayBlock->topo_loc_high.row << 5) | - (pTiledDisplayBlock->topo_low.row)) + 1; - pTileTopo->topology.col = ((pTiledDisplayBlock->topo_loc_high.col << 5) | - (pTiledDisplayBlock->topo_low.col)) + 1; - pTileTopo->location.x = ((pTiledDisplayBlock->topo_loc_high.x << 5) | - (pTiledDisplayBlock->loc_low.x)); - pTileTopo->location.y = ((pTiledDisplayBlock->topo_loc_high.y << 5) | - (pTiledDisplayBlock->loc_low.y)); - - pTileTopo->native_resolution.width = ((pTiledDisplayBlock->native_resolution.width_high << 8) | - pTiledDisplayBlock->native_resolution.width_low) + 1; - pTileTopo->native_resolution.height = ((pTiledDisplayBlock->native_resolution.height_high << 8) | - pTiledDisplayBlock->native_resolution.height_low) + 1; - - pTileTopo->bezel_info.top = (pTiledDisplayBlock->bezel_info.top * - pTiledDisplayBlock->bezel_info.pixel_density) / 10; - pTileTopo->bezel_info.bottom = (pTiledDisplayBlock->bezel_info.bottom * - pTiledDisplayBlock->bezel_info.pixel_density) / 10; - pTileTopo->bezel_info.right = (pTiledDisplayBlock->bezel_info.right * - pTiledDisplayBlock->bezel_info.pixel_density) / 10; - pTileTopo->bezel_info.left = (pTiledDisplayBlock->bezel_info.left * - pTiledDisplayBlock->bezel_info.pixel_density) / 10; - - pTileTopo->tile_topology_id.vendor_id = pTiledDisplayBlock->topo_id.vendor_id[0] << 16 | - pTiledDisplayBlock->topo_id.vendor_id[1] << 8 | - pTiledDisplayBlock->topo_id.vendor_id[2]; - pTileTopo->tile_topology_id.product_id = pTiledDisplayBlock->topo_id.product_id[1] << 8 | - pTiledDisplayBlock->topo_id.product_id[0]; - pTileTopo->tile_topology_id.serial_number = pTiledDisplayBlock->topo_id.serial_number[3] << 24 | - pTiledDisplayBlock->topo_id.serial_number[2] << 16 | - pTiledDisplayBlock->topo_id.serial_number[1] << 8 | - pTiledDisplayBlock->topo_id.serial_number[0]; - } - else + if (pDataBlock->data_bytes != DISPLAYID_2_0_TILED_DISPLAY_BLOCK_PAYLOAD_LENGTH) { return NVT_STATUS_ERR; } + + if (pDisplayIdInfo == NULL) return status; + + pTiledDisplayBlock = (const DISPLAYID_2_0_TILED_DISPLAY_BLOCK *)pDataBlock; + pTileTopo = &pDisplayIdInfo->tile_topo; + + pTileTopo->revision = pDataBlock->revision; + + pTileTopo->capability.bSingleEnclosure = pTiledDisplayBlock->capability.single_enclosure; + pTileTopo->capability.bHasBezelInfo = pTiledDisplayBlock->capability.has_bezel_info; + pTileTopo->capability.multi_tile_behavior = pTiledDisplayBlock->capability.multi_tile_behavior; + pTileTopo->capability.single_tile_behavior = pTiledDisplayBlock->capability.single_tile_behavior; + + pTileTopo->topology.row = ((pTiledDisplayBlock->topo_loc_high.row << 5) | + (pTiledDisplayBlock->topo_low.row)) + 1; + pTileTopo->topology.col = ((pTiledDisplayBlock->topo_loc_high.col << 5) | + (pTiledDisplayBlock->topo_low.col)) + 1; + pTileTopo->location.x = ((pTiledDisplayBlock->topo_loc_high.x << 5) | + (pTiledDisplayBlock->loc_low.x)); + pTileTopo->location.y = ((pTiledDisplayBlock->topo_loc_high.y << 5) | + (pTiledDisplayBlock->loc_low.y)); + + pTileTopo->native_resolution.width = ((pTiledDisplayBlock->native_resolution.width_high << 8) | + pTiledDisplayBlock->native_resolution.width_low) + 1; + pTileTopo->native_resolution.height = ((pTiledDisplayBlock->native_resolution.height_high << 8) | + pTiledDisplayBlock->native_resolution.height_low) + 1; + + pTileTopo->bezel_info.top = (pTiledDisplayBlock->bezel_info.top * + pTiledDisplayBlock->bezel_info.pixel_density) / 10; + pTileTopo->bezel_info.bottom = (pTiledDisplayBlock->bezel_info.bottom * + pTiledDisplayBlock->bezel_info.pixel_density) / 10; + pTileTopo->bezel_info.right = (pTiledDisplayBlock->bezel_info.right * + pTiledDisplayBlock->bezel_info.pixel_density) / 10; + pTileTopo->bezel_info.left = (pTiledDisplayBlock->bezel_info.left * + pTiledDisplayBlock->bezel_info.pixel_density) / 10; + + pTileTopo->tile_topology_id.vendor_id = pTiledDisplayBlock->topo_id.vendor_id[0] << 16 | + pTiledDisplayBlock->topo_id.vendor_id[1] << 8 | + pTiledDisplayBlock->topo_id.vendor_id[2]; + pTileTopo->tile_topology_id.product_id = pTiledDisplayBlock->topo_id.product_id[1] << 8 | + pTiledDisplayBlock->topo_id.product_id[0]; + pTileTopo->tile_topology_id.serial_number = pTiledDisplayBlock->topo_id.serial_number[3] << 24 | + pTiledDisplayBlock->topo_id.serial_number[2] << 16 | + pTiledDisplayBlock->topo_id.serial_number[1] << 8 | + pTiledDisplayBlock->topo_id.serial_number[0]; + return status; } @@ -1076,83 +1137,192 @@ CODE_SEGMENT(PAGE_DD_CODE) static NVT_STATUS parseDisplayId20ContainerId( const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, - NVT_DISPLAYID_CONTAINERID *pContainerId) + NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo) { NVT_STATUS status = NVT_STATUS_SUCCESS; const DISPLAYID_2_0_CONTAINERID_BLOCK *pContainerIdBlock = NULL; + NVT_DISPLAYID_CONTAINERID *pContainerId = NULL; - if ((pDataBlock->type == DISPLAYID_2_0_BLOCK_TYPE_CONTAINER_ID) && - (pDataBlock->data_bytes == DISPLAYID_2_0_CONTAINERID_BLOCK_PAYLOAD_LENGTH)) + if (pDataBlock->data_bytes != DISPLAYID_2_0_CONTAINERID_BLOCK_PAYLOAD_LENGTH) { - pContainerIdBlock = (const DISPLAYID_2_0_CONTAINERID_BLOCK *)pDataBlock; - - pContainerId->revision = pDataBlock->revision; - pContainerId->data1 = pContainerIdBlock->container_id[0] << 24 | - pContainerIdBlock->container_id[1] << 16 | - pContainerIdBlock->container_id[2] << 8 | - pContainerIdBlock->container_id[3]; - pContainerId->data2 = pContainerIdBlock->container_id[4] << 8 | - pContainerIdBlock->container_id[5]; - pContainerId->data3 = pContainerIdBlock->container_id[6] << 8 | - pContainerIdBlock->container_id[7]; - pContainerId->data4 = pContainerIdBlock->container_id[8] << 8 | - pContainerIdBlock->container_id[9]; - pContainerId->data5[0] = pContainerIdBlock->container_id[10]; - pContainerId->data5[1] = pContainerIdBlock->container_id[11]; - pContainerId->data5[2] = pContainerIdBlock->container_id[12]; - pContainerId->data5[3] = pContainerIdBlock->container_id[13]; - pContainerId->data5[4] = pContainerIdBlock->container_id[14]; - pContainerId->data5[5] = pContainerIdBlock->container_id[15]; + return NVT_STATUS_ERR; } - else + + if (pDisplayIdInfo == NULL) return status; + + pContainerIdBlock = (const DISPLAYID_2_0_CONTAINERID_BLOCK *)pDataBlock; + pContainerId = &pDisplayIdInfo->container_id; + + pContainerId->revision = pDataBlock->revision; + pContainerId->data1 = pContainerIdBlock->container_id[0] << 24 | + pContainerIdBlock->container_id[1] << 16 | + pContainerIdBlock->container_id[2] << 8 | + pContainerIdBlock->container_id[3]; + pContainerId->data2 = pContainerIdBlock->container_id[4] << 8 | + pContainerIdBlock->container_id[5]; + pContainerId->data3 = pContainerIdBlock->container_id[6] << 8 | + pContainerIdBlock->container_id[7]; + pContainerId->data4 = pContainerIdBlock->container_id[8] << 8 | + pContainerIdBlock->container_id[9]; + pContainerId->data5[0] = pContainerIdBlock->container_id[10]; + pContainerId->data5[1] = pContainerIdBlock->container_id[11]; + pContainerId->data5[2] = pContainerIdBlock->container_id[12]; + pContainerId->data5[3] = pContainerIdBlock->container_id[13]; + pContainerId->data5[4] = pContainerIdBlock->container_id[14]; + pContainerId->data5[5] = pContainerIdBlock->container_id[15]; + + return status; +} + +CODE_SEGMENT(PAGE_DD_CODE) +static NVT_STATUS +parseDisplayId20AdaptiveSync( + const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, + NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo) +{ + NVT_STATUS status = NVT_STATUS_SUCCESS; + const DISPLAYID_2_0_ADAPTIVE_SYNC_BLOCK *pAdaptiveSyncBlock = NULL; + NvU32 descriptorCnt = 0; + NvU8 i = 0; + NvU8 minRR = 0; + NvU16 maxRR = 0; + + pAdaptiveSyncBlock = (const DISPLAYID_2_0_ADAPTIVE_SYNC_BLOCK *)pDataBlock; + + if (pAdaptiveSyncBlock->header.payload_bytes_adaptive_sync_len == 0) { - status = NVT_STATUS_ERR; + // Sanity check + if (pDataBlock->data_bytes % sizeof(DISPLAYID_2_0_ADAPTIVE_SYNC_DESCRIPTOR) != 0) + { + nvt_assert(0); + status = NVT_STATUS_ERR; + } + + descriptorCnt = pDataBlock->data_bytes / sizeof(DISPLAYID_2_0_ADAPTIVE_SYNC_DESCRIPTOR); + + if (descriptorCnt < 1) return NVT_STATUS_ERR; + + if (pDisplayIdInfo == NULL) + { + for (i = 0; i < descriptorCnt; i++) + { + minRR = pAdaptiveSyncBlock->descriptors[i].min_refresh_rate; + maxRR = (pAdaptiveSyncBlock->descriptors[i].max_refresh_rate.max_rr_9_8 << 8 | + pAdaptiveSyncBlock->descriptors[i].max_refresh_rate.max_rr_7_0) + 1; + if (minRR > (maxRR + 1) || minRR == 0 || maxRR == 0) + { + nvt_assert(0); + status = NVT_STATUS_ERR; + } + } + return status; + } + + pDisplayIdInfo->total_adaptive_sync_descriptor = descriptorCnt; + + for (i = 0; i < descriptorCnt; i++) + { + // Byte 0 Adaptive-Sync Operation and Range Information + pDisplayIdInfo->adaptive_sync_descriptor[i].u.information.adaptive_sync_range = pAdaptiveSyncBlock->descriptors[i].operation_range_info.range; + pDisplayIdInfo->adaptive_sync_descriptor[i].u.information.duration_inc_flicker_perf = pAdaptiveSyncBlock->descriptors[i].operation_range_info.successive_frame_inc_tolerance; + pDisplayIdInfo->adaptive_sync_descriptor[i].u.information.modes = pAdaptiveSyncBlock->descriptors[i].operation_range_info.modes; + pDisplayIdInfo->adaptive_sync_descriptor[i].u.information.seamless_not_support = pAdaptiveSyncBlock->descriptors[i].operation_range_info.seamless_transition_not_support; + pDisplayIdInfo->adaptive_sync_descriptor[i].u.information.duration_dec_flicker_perf = pAdaptiveSyncBlock->descriptors[i].operation_range_info.successive_frame_dec_tolerance; + + // 6.2 format (six integer bits and two fractional bits) a value range of 0.00 to 63.75ms + pDisplayIdInfo->adaptive_sync_descriptor[i].max_duration_inc = pAdaptiveSyncBlock->descriptors[i].max_single_frame_inc; + pDisplayIdInfo->adaptive_sync_descriptor[i].min_rr = pAdaptiveSyncBlock->descriptors[i].min_refresh_rate; + pDisplayIdInfo->adaptive_sync_descriptor[i].max_rr = (pAdaptiveSyncBlock->descriptors[i].max_refresh_rate.max_rr_9_8 << 8 | + pAdaptiveSyncBlock->descriptors[i].max_refresh_rate.max_rr_7_0) + 1; + // 6.2 format (six integer bits and two fractional bits) a value range of 0.00 to 63.75ms + pDisplayIdInfo->adaptive_sync_descriptor[i].max_duration_dec = pAdaptiveSyncBlock->descriptors[i].max_single_frame_dec; + } + } + else // all other values are RESERVED. + { + if (pDisplayIdInfo == NULL) return NVT_STATUS_ERR; } return status; } +CODE_SEGMENT(PAGE_DD_CODE) +static NVT_STATUS +parseDisplayId20ARVRHMD( + const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, + NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo) +{ + NVT_STATUS status = NVT_STATUS_SUCCESS; + + if (pDisplayIdInfo == NULL) return status; + + // TODO: Implement the parsing here. + + return status; +} + +CODE_SEGMENT(PAGE_DD_CODE) +static NVT_STATUS +parseDisplayId20ARVRLayer( + const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, + NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo) +{ + NVT_STATUS status = NVT_STATUS_SUCCESS; + + if (pDisplayIdInfo == NULL) return status; + + // TODO: Implement the parsing here. + + return status; +} + + + CODE_SEGMENT(PAGE_DD_CODE) static NVT_STATUS parseDisplayId20VendorSpecific( const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, - NVT_DISPLAYID_VENDOR_SPECIFIC *pVendorSpecific) + NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo) { NVT_STATUS status = NVT_STATUS_SUCCESS; const DISPLAYID_2_0_VENDOR_SPECIFIC_BLOCK *block = NULL; + NVT_DISPLAYID_VENDOR_SPECIFIC *pVendorSpecific = NULL; NvU32 ieee_oui = 0; - if (pDataBlock->type == DISPLAYID_2_0_BLOCK_TYPE_VENDOR_SPEC) + // Add more validation here if needed + + if (pDisplayIdInfo == NULL) return status; + + block = (const DISPLAYID_2_0_VENDOR_SPECIFIC_BLOCK*)pDataBlock; + pVendorSpecific = &pDisplayIdInfo->vendor_specific; + + ieee_oui = (NvU32)((block->vendor_id[0] << 16) | + (block->vendor_id[1] << 8) | + (block->vendor_id[2])); + + switch (ieee_oui) { - block = (const DISPLAYID_2_0_VENDOR_SPECIFIC_BLOCK*)pDataBlock; - ieee_oui = (NvU32)((block->vendor_id[0] << 16) | - (block->vendor_id[1] << 8) | - (block->vendor_id[2])); - - switch (ieee_oui) + case NVT_VESA_VENDOR_SPECIFIC_IEEE_ID: + // TODO: below parser shall be updated if DID21 changed in the future + if (pDataBlock->data_bytes == NVT_VESA_VENDOR_SPECIFIC_LENGTH) { - case NVT_VESA_VENDOR_SPECIFIC_IEEE_ID: - // TODO: below parser shall be updated if DID21 changed in the future - if (pDataBlock->data_bytes == NVT_VESA_VENDOR_SPECIFIC_LENGTH) - { - pVendorSpecific->vesaVsdb.data_struct_type.type = block->vendor_specific_data[3] & NVT_VESA_ORG_VSDB_DATA_TYPE_MASK; - pVendorSpecific->vesaVsdb.data_struct_type.color_space_and_eotf = (block->vendor_specific_data[3] & NVT_VESA_ORG_VSDB_COLOR_SPACE_AND_EOTF_MASK) >> NVT_VESA_ORG_VSDB_COLOR_SPACE_AND_EOTF_SHIFT; + pVendorSpecific->vesaVsdb.data_struct_type.type = block->vendor_specific_data[3] & NVT_VESA_ORG_VSDB_DATA_TYPE_MASK; + pVendorSpecific->vesaVsdb.data_struct_type.color_space_and_eotf = (block->vendor_specific_data[3] & NVT_VESA_ORG_VSDB_COLOR_SPACE_AND_EOTF_MASK) >> NVT_VESA_ORG_VSDB_COLOR_SPACE_AND_EOTF_SHIFT; - pVendorSpecific->vesaVsdb.overlapping.pixels_overlapping_count = block->vendor_specific_data[4] & NVT_VESA_ORG_VSDB_PIXELS_OVERLAPPING_MASK; - pVendorSpecific->vesaVsdb.overlapping.multi_sst = (block->vendor_specific_data[4] & NVT_VESA_ORG_VSDB_MULTI_SST_MODE_MASK) >> NVT_VESA_ORG_VSDB_MULTI_SST_MODE_SHIFT; + pVendorSpecific->vesaVsdb.overlapping.pixels_overlapping_count = block->vendor_specific_data[4] & NVT_VESA_ORG_VSDB_PIXELS_OVERLAPPING_MASK; + pVendorSpecific->vesaVsdb.overlapping.multi_sst = (block->vendor_specific_data[4] & NVT_VESA_ORG_VSDB_MULTI_SST_MODE_MASK) >> NVT_VESA_ORG_VSDB_MULTI_SST_MODE_SHIFT; - pVendorSpecific->vesaVsdb.pass_through_integer.pass_through_integer_dsc = block->vendor_specific_data[5] & NVT_VESA_ORG_VSDB_PASS_THROUGH_INTEGER_MASK; - pVendorSpecific->vesaVsdb.pass_through_fractional.pass_through_fraction_dsc = block->vendor_specific_data[6] & NVT_VESA_ORG_VSDB_PASS_THROUGH_FRACTIOINAL_MASK; - } - else - { - status = NVT_STATUS_ERR; - } - break; - - default: - break; + pVendorSpecific->vesaVsdb.pass_through_integer.pass_through_integer_dsc = block->vendor_specific_data[5] & NVT_VESA_ORG_VSDB_PASS_THROUGH_INTEGER_MASK; + pVendorSpecific->vesaVsdb.pass_through_fractional.pass_through_fraction_dsc = block->vendor_specific_data[6] & NVT_VESA_ORG_VSDB_PASS_THROUGH_FRACTIOINAL_MASK; } + else + { + status = NVT_STATUS_ERR; + } + break; + + default: + break; } return status; @@ -1166,50 +1336,50 @@ parseDisplayId20CtaData( { NVT_STATUS status = NVT_STATUS_SUCCESS; - const DISPLAYID_2_0_CTA_BLOCK * ctaBlock = NULL; NVT_EDID_CEA861_INFO *p861Info = NULL; + const DISPLAYID_2_0_CTA_BLOCK * ctaBlock = NULL; NvU8 *pcta_data = NULL; - if (pDataBlock->type == DISPLAYID_2_0_BLOCK_TYPE_CTA_DATA) + ctaBlock = (const DISPLAYID_2_0_CTA_BLOCK *)pDataBlock; + + // WAR here to add a (size_t) cast for casting member from const to non-const in order to avoid Linux old compiler failed in DVS. + pcta_data = (NvU8 *)(size_t)ctaBlock->cta_data; + + if (pDisplayIdInfo == NULL) { - ctaBlock = (const DISPLAYID_2_0_CTA_BLOCK *)pDataBlock; - - // WAR here to add a (size_t) cast for casting member from const to non-const in order to avoid Linux old compiler failed in DVS. - pcta_data = (NvU8 *)(size_t)ctaBlock->cta_data; - - status = parseCta861DataBlockInfo(pcta_data, pDataBlock->data_bytes, &pDisplayIdInfo->cta.cta861_info); - if (status != NVT_STATUS_SUCCESS) - { - return status; - } - - p861Info = &pDisplayIdInfo->cta.cta861_info; - - parseCta861VsdbBlocks(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK); - - parseCta861HfScdb(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK); - - // This CTA 861 function to parse 861 part - parse861bShortTiming(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK); - - // yuv420-only video - parse861bShortYuv420Timing(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK); - - parseCea861HdrStaticMetadataDataBlock(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK); - - // CEA861-F at 7.5.12 section about VFPDB block. - if (p861Info->total_vfpdb != 0) - { - parse861bShortPreferredTiming(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK); - } - + status = parseCta861DataBlockInfo(pcta_data, pDataBlock->data_bytes, NULL); return status; - } else { - return NVT_STATUS_ERR; + status = parseCta861DataBlockInfo(pcta_data, pDataBlock->data_bytes, &pDisplayIdInfo->cta.cta861_info); } + + if (status != NVT_STATUS_SUCCESS) + { + return status; + } + + p861Info = &(pDisplayIdInfo->cta.cta861_info); + + parseCta861VsdbBlocks(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK); + parseCta861HfScdb(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK); + // This CTA 861 function to parse 861 part + parse861bShortTiming(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK); + // yuv420-only video + parse861bShortYuv420Timing(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK); + + parseCea861HdrStaticMetadataDataBlock(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK); + parseCea861DvStaticMetadataDataBlock(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK); + parseCea861Hdr10PlusDataBlock(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK); + + // CEA861-F at 7.5.12 section about VFPDB block. + if (p861Info->total_vfpdb > 0) + { + parse861bShortPreferredTiming(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK); + } + + return status; } // Helper function @@ -1305,6 +1475,8 @@ assignNextAvailableDisplayId20Timing( NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo, const NVT_TIMING *pTiming) { + if (pDisplayIdInfo == NULL) return NV_TRUE; + if (pDisplayIdInfo->total_timings >= COUNT(pDisplayIdInfo->timing)) { return NV_FALSE; @@ -1423,10 +1595,11 @@ parseDisplayId20Timing7Descriptor( pTiming->HTotal, pTiming->VTotal); - pTiming->etc.flag |= (revision >= DISPLAYID_2_0_TYPE7_DSC_PASSTHRU_REVISION ) ? NVT_FLAG_DISPLAYID_7_DSC_PASSTHRU : 0; + pTiming->etc.flag |= (revision >= DISPLAYID_2_0_TYPE7_DSC_PASSTHRU_REVISION ) ? NVT_FLAG_DISPLAYID_T7_DSC_PASSTHRU : 0; + if (revision >= DISPLAYID_2_0_TYPE7_YCC420_SUPPORT_REVISION) { - pTiming->etc.flag |= pDescriptor->options.is_preferred_or_ycc420 ? NVT_FLAG_DISPLAYID_2_0_EXPLICT_YUV420 : 0; + pTiming->etc.flag |= pDescriptor->options.is_preferred_or_ycc420 ? NVT_FLAG_DISPLAYID_T7_T8_EXPLICT_YUV420 : 0; if (pDescriptor->options.is_preferred_or_ycc420) // YCC 420 support { @@ -1478,8 +1651,8 @@ parseDisplayId20Timing9Descriptor( case DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_REDUCED_BLANKING_1: status = NvTiming_CalcCVT_RB(width, height, rr, NVT_PROGRESSIVE, pTiming); break; - case DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_REDUCED_BLANKING_2: - status = NvTiming_CalcCVT_RB2(width, height, rr, pDescriptor->options.fractional_refresh_rate_support, pTiming); + case DISPLAYID_2_0_TIMING_FORMULA_CVT_2_0_REDUCED_BLANKING_2: + status = NvTiming_CalcCVT_RB2(width, height, rr, pDescriptor->options.rr_1000div1001_support, pTiming); break; default: status = NVT_STATUS_ERR; @@ -1511,7 +1684,7 @@ parseDisplayId20Timing9Descriptor( (int)pTiming->etc.rrx1k%1000, (pTiming->interlaced ? "I":"P")); } - else if (pDescriptor->options.timing_formula == DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_REDUCED_BLANKING_2) + else if (pDescriptor->options.timing_formula == DISPLAYID_2_0_TIMING_FORMULA_CVT_2_0_REDUCED_BLANKING_2) { NVT_SNPRINTF((char *)pTiming->etc.name, sizeof(pTiming->etc.name), "DID20-Type9-RB2:#%3d:%dx%dx%3d.%03dHz/%s", (int)NVT_GET_TIMING_STATUS_SEQ(pTiming->etc.status), @@ -1563,29 +1736,37 @@ parseDisplayId20Timing10Descriptor( case DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_REDUCED_BLANKING_1: status = NvTiming_CalcCVT_RB(width, height, rr, NVT_PROGRESSIVE, pTiming); break; - case DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_REDUCED_BLANKING_2: - status = NvTiming_CalcCVT_RB2(width, height, rr, p6bytesDescriptor->options.vrr_or_hblank, pTiming); + case DISPLAYID_2_0_TIMING_FORMULA_CVT_2_0_REDUCED_BLANKING_2: + status = NvTiming_CalcCVT_RB2(width, height, rr, p6bytesDescriptor->options.rr1000div1001_or_hblank, pTiming); break; - case DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_REDUCED_BLANKING_3: + case DISPLAYID_2_0_TIMING_FORMULA_CVT_2_0_REDUCED_BLANKING_3: { - /* Will uncomment this if we used the new RB3 interface. - NvU32 hBlankValue = 0; - - if (p6bytesDescriptor->options.vrr_or_hblank == 0) // Horizontal Blank in Pixels = [Field Value] * 8 + 80 + NvU32 deltaHBlank = 0; + + if (p7bytesDescriptor != NULL) { - hBlankValue = p7bytesDescriptor->delta_hblank * 8 + 80; - } - else if (p6bytesDescriptor->options.vrr_or_hblank == 1) - { - if (p7bytesDescriptor->delta_hblank <= 5) - hBlankValue = p7bytesDescriptor->delta_hblank * 8 + 160; - else // if 5 < Field Value <=7 - hBlankValue = 160 - (p7bytesDescriptor->delta_hblank * 8); - } - */ + if (p6bytesDescriptor->options.rr1000div1001_or_hblank == 0) // Horizontal Blank in Pixels = [Field Value] * 8 + 80 + { + deltaHBlank = p7bytesDescriptor->delta_hblank * 8; + } + else if (p6bytesDescriptor->options.rr1000div1001_or_hblank == 1) + { + if (p7bytesDescriptor->delta_hblank <= 5) + deltaHBlank = (p7bytesDescriptor->delta_hblank * 8 + 160) - 80; + else // if 5 < Field Value <=7 + deltaHBlank = (160 - ((p7bytesDescriptor->delta_hblank - 5) * 8)) - 80; + } + + status = NvTiming_CalcCVT_RB3(width, height, rr, deltaHBlank, p7bytesDescriptor->additional_vblank_timing * 35, p6bytesDescriptor->options.early_vsync, pTiming); + } + else // 6 bytes descriptor + { + if (p6bytesDescriptor->options.rr1000div1001_or_hblank == 1) + deltaHBlank = 80; + + status = NvTiming_CalcCVT_RB3(width, height, rr, deltaHBlank, 0, p6bytesDescriptor->options.early_vsync, pTiming); + } - // TODO : Need to handle 7:5 bit at 6 byte -Additional Vertical Blank Time in % of frame time for the defined Refresh Rate - //status = NvTiming_CalcCVT_RB3(width, height, rr, hBlankValue, pTiming); break; } } @@ -1622,7 +1803,7 @@ parseDisplayId20Timing10Descriptor( (int)pTiming->etc.rrx1k%1000, (pTiming->interlaced ? "I":"P")); } - else if (p6bytesDescriptor->options.timing_formula == DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_REDUCED_BLANKING_2) + else if (p6bytesDescriptor->options.timing_formula == DISPLAYID_2_0_TIMING_FORMULA_CVT_2_0_REDUCED_BLANKING_2) { NVT_SNPRINTF((char *)pTiming->etc.name, sizeof(pTiming->etc.name), "DID20-Type10RB2:#%3d:%dx%dx%3d.%03dHz/%s", (int)NVT_GET_TIMING_STATUS_SEQ(pTiming->etc.status), @@ -1632,7 +1813,7 @@ parseDisplayId20Timing10Descriptor( (int)pTiming->etc.rrx1k%1000, (pTiming->interlaced ? "I":"P")); } - else if (p6bytesDescriptor->options.timing_formula == DISPLAYID_2_0_TIMING_FORMULA_CVT_1_2_REDUCED_BLANKING_3) + else if (p6bytesDescriptor->options.timing_formula == DISPLAYID_2_0_TIMING_FORMULA_CVT_2_0_REDUCED_BLANKING_3) { NVT_SNPRINTF((char *)pTiming->etc.name, sizeof(pTiming->etc.name), "DID20-Type10RB3:#%3d:%dx%dx%3d.%03dHz/%s", (int)NVT_GET_TIMING_STATUS_SEQ(pTiming->etc.status), diff --git a/src/common/modeset/timing/nvt_dsc_pps.c b/src/common/modeset/timing/nvt_dsc_pps.c index ec725b314..c24a8e6c6 100644 --- a/src/common/modeset/timing/nvt_dsc_pps.c +++ b/src/common/modeset/timing/nvt_dsc_pps.c @@ -2171,7 +2171,13 @@ DSC_GeneratePPS if (*pBitsPerPixelX16 != 0) { *pBitsPerPixelX16 = DSC_AlignDownForBppPrecision(*pBitsPerPixelX16, pDscInfo->sinkCaps.bitsPerPixelPrecision); - if (*pBitsPerPixelX16 > in->bits_per_pixel) + + // The calculation of in->bits_per_pixel here in PPSlib, which is the maximum bpp that is allowed by available bandwidth, + // which is applicable to DP alone and not to HDMI FRL. + // Before calling PPS lib to generate PPS data, HDMI library has done calculation according to HDMI2.1 spec + // to determine if FRL rate is sufficient for the requested bpp. So restricting the condition to DP alone. + if ((pWARData && (pWARData->connectorType == DSC_DP)) && + (*pBitsPerPixelX16 > in->bits_per_pixel)) { DSC_Print("ERROR - Invalid bits per pixel value specified."); ret = NVT_STATUS_INVALID_PARAMETER; diff --git a/src/common/modeset/timing/nvt_edid.c b/src/common/modeset/timing/nvt_edid.c index 4e5f34c63..9fff6341f 100644 --- a/src/common/modeset/timing/nvt_edid.c +++ b/src/common/modeset/timing/nvt_edid.c @@ -1,6 +1,6 @@ //***************************************************************************** // -// SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +// SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-License-Identifier: MIT // // Permission is hereby granted, free of charge, to any person obtaining a @@ -217,7 +217,7 @@ NvU32 getEdidVersion(NvU8 *pEdid, NvU32 *pVer) *pVer = (((NvU32) p->bVersionNumber) << 8) + ((NvU32) p->bRevisionNumber); } - else if ((pEdid[0] & 0xF0) == 0x20 && (pEdid[0] & 0x0F) >=0) + else if ((pEdid[0] & 0xF0) == 0x20) *pVer = (((NvU32) (pEdid[0] & 0XF0) << 4) + (NvU32) (pEdid[0] & 0X0F)) ; // DisplayID version 2.x else return NVT_STATUS_ERR; // un-recongnized EDID version @@ -432,10 +432,9 @@ void parseEdidStandardTimingDescriptor(NvU16 timing, NVT_EDID_INFO *pInfo, NvU32 NVT_SNPRINTF((char *)pT->etc.name, 40, "EDID-STD(DMT):%dx%dx%dHz", (int)width, (int)height, (int)rr); pT->etc.name[39] = '\0'; } - else if (pInfo->version >= NVT_EDID_VER_1_4) + // EDID1.4 and above defaults to CVT, instead of GTF. GTF is deprecated as of 1.4. + else if ((pInfo->version >= NVT_EDID_VER_1_4) && (NvTiming_CalcCVT(width, height, rr, NVT_PROGRESSIVE, pT) == NVT_STATUS_SUCCESS)) { - // EDID1.4 and above defaults to CVT, instead of GTF. GTF is deprecated as of 1.4. - NvTiming_CalcCVT(width, height, rr, NVT_PROGRESSIVE, pT); pT->etc.status = NVT_STATUS_EDID_STDn(count); NVT_SNPRINTF((char *)pT->etc.name, 40, "EDID-STD(CVT):%dx%dx%dHz", (int)width, (int)height, (int)rr); pT->etc.name[39] = '\0'; @@ -443,10 +442,12 @@ void parseEdidStandardTimingDescriptor(NvU16 timing, NVT_EDID_INFO *pInfo, NvU32 else { // if the mode is not found in DMT, use GTF timing - NvTiming_CalcGTF(width, height, rr, NVT_PROGRESSIVE, pT); + if (NvTiming_CalcGTF(width, height, rr, NVT_PROGRESSIVE, pT) == NVT_STATUS_SUCCESS) + { + NVT_SNPRINTF((char *)pT->etc.name, 40, "EDID-STD(GTF):%dx%dx%dHz", (int)width, (int)height, (int)rr); + pT->etc.name[39] = '\0'; + } pT->etc.status = NVT_STATUS_EDID_STDn(count); - NVT_SNPRINTF((char *)pT->etc.name, 40, "EDID-STD(GTF):%dx%dx%dHz", (int)width, (int)height, (int)rr); - pT->etc.name[39] = '\0'; } } @@ -1055,7 +1056,10 @@ NVT_STATUS NV_STDCALL NvTiming_ParseEDIDInfo(NvU8 *pEdid, NvU32 length, NVT_EDID parseCea861HdrStaticMetadataDataBlock(p861Info, pInfo, FROM_CTA861_EXTENSION); // parse Dolby Vision related information from the DV vendor specific video data block - parseCea861DvStaticMetadataDataBlock(p861Info, &pInfo->dv_static_metadata_info); + parseCea861DvStaticMetadataDataBlock(p861Info, pInfo, FROM_CTA861_EXTENSION); + + // parse HDR10+ related information from the HDR10+ LLC Vendor Specific Video Data Block + parseCea861Hdr10PlusDataBlock(p861Info, pInfo, FROM_CTA861_EXTENSION); // Timings are listed (or shall) be listed in priority order // So read SVD, yuv420 SVDs first before reading detailed timings @@ -1955,7 +1959,15 @@ NVT_STATUS NvTiming_GetEDIDBasedASPRTiming( NvU16 width, NvU16 height, NvU16 rr, return NVT_STATUS_ERR; } -// check whether EDID is valid +/** + * + * @brief check EDID raw data is valid or not, and it will return the err flags if it existed + * @param pEdid : this is a pointer to EDID data + * @param length : read length of EDID + * @param bIsTrongValidation : true - added more check + * false- only header and checksum and size check + * + */ CODE_SEGMENT(PAGE_DD_CODE) NvU32 NvTiming_EDIDValidationMask(NvU8 *pEdid, NvU32 length, NvBool bIsStrongValidation) { @@ -2120,8 +2132,369 @@ NvU32 NvTiming_EDIDValidationMask(NvU8 *pEdid, NvU32 length, NvBool bIsStrongVal break; } } + } + return ret; +} +/** + * + * @brief sanity check EDID binary frequently used data block is valid or not, + * and it will return error checkpoint flag if it existed + * @param pEdid : this is a pointer to EDID raw data + * @param length : read length of EDID + * + */ +CODE_SEGMENT(PAGE_DD_CODE) +NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length) +{ + NvU32 i, j, version, extnCount; + EDIDV1STRUC *p = (EDIDV1STRUC *)pEdid; + EDID_LONG_DISPLAY_DESCRIPTOR *pLdd; + NvU8 *pExt; + DETAILEDTIMINGDESCRIPTOR *pDTD; + // For CTA861 + NvU8 ctaDTD_Offset; + NvU8 *pData_collection; + NvU32 ctaBlockTag, ctaPayload, vic; + // For DisplayID + DIDEXTENSION *pDisplayid; + NvU8 did_section_length = 0x79; + NvU8 did2ExtCount = 0; + DISPLAYID_2_0_DATA_BLOCK_HEADER *pDID2Header; + DISPLAYID_DATA_BLOCK_HEADER *pHeader; + NvU8 block_length = 0; + NvBool bAllZero = NV_TRUE; + NvU32 ret = 0; + + // check the EDID base size to avoid accessing beyond the EDID buffer, do not proceed with + // further validation. + if (length < sizeof(EDIDV1STRUC)) + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_SIZE); + + // check the EDID version and signature + if (getEdidVersion(pEdid, &version) != NVT_STATUS_SUCCESS) + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_HEADER); + + // check block 0 checksum value + if (!isChecksumValid(pEdid)) + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_CHECKSUM); + + if (p->bVersionNumber != 0x01 || p->bRevisionNumber > 0x04) + { + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_VERSION); + } + + // 18bytes in DTD or Display Descriptor check + for (i = 0; i < NVT_EDID_MAX_LONG_DISPLAY_DESCRIPTOR; i++) + { + if (*((NvU16 *)&p->DetailedTimingDesc[i]) != 0) + { + // This block is not a Display Descriptor. + // It must be a valid timing definition + // validate the block by passing NULL as the NVTIMING parameter to parseEdidDetailedTimingDescriptor + if (parseEdidDetailedTimingDescriptor((NvU8 *)&p->DetailedTimingDesc[i], NULL) != NVT_STATUS_SUCCESS) + { + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_DTD); + } + else + { + // check the max image size in monitor and its DTD defines value + if (p->bMaxHorizImageSize != 0 && p->bMaxVertImageSize != 0) + { + DETAILEDTIMINGDESCRIPTOR *pDTD = (DETAILEDTIMINGDESCRIPTOR *)&p->DetailedTimingDesc[i]; + NvU16 hDTDImageSize = (pDTD->bDTHorizVertImage & 0xF0) << 4 | pDTD->bDTHorizontalImage; + NvU16 vDTDImageSize = (pDTD->bDTHorizVertImage & 0x0F) << 8 | pDTD->bDTVerticalImage; + + if ((hDTDImageSize/10) > p->bMaxHorizImageSize || (vDTDImageSize/10) > p->bMaxVertImageSize) + { + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_DTD); + } + } + } + } + else + { + pLdd = (EDID_LONG_DISPLAY_DESCRIPTOR *)&p->DetailedTimingDesc[i]; + + // This block is a display descriptor, validate + if (((EDID_LONG_DISPLAY_DESCRIPTOR *)&p->DetailedTimingDesc[i])->rsvd != 0 || // (00 00 00)h indicates Display Descriptor + (pLdd->tag >= 0x11 && pLdd->tag <= 0xF6)) // Reserved : Do Not Use + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_DESCRIPTOR); + + if (pLdd->tag == NVT_EDID_DISPLAY_DESCRIPTOR_DRL && (version == 0x103 || (version == 0x104 && (p->bFeatureSupport & 1)))) + { + EDID_MONITOR_RANGE_LIMIT *pRangeLimit = (EDID_MONITOR_RANGE_LIMIT *)pLdd->data; + NvU8 max_v_rate_offset, min_v_rate_offset, max_h_rate_offset, min_h_rate_offset; + + // add 255Hz offsets as needed before doing the check, use descriptor->rsvd2 + nvt_assert(!(pLdd->rsvd2 & 0xF0)); + + max_v_rate_offset = pLdd->rsvd2 & NVT_PVT_EDID_RANGE_OFFSET_VER_MAX ? NVT_PVT_EDID_RANGE_OFFSET_AMOUNT : 0; + min_v_rate_offset = pLdd->rsvd2 & NVT_PVT_EDID_RANGE_OFFSET_VER_MIN ? NVT_PVT_EDID_RANGE_OFFSET_AMOUNT : 0; + max_h_rate_offset = pLdd->rsvd2 & NVT_PVT_EDID_RANGE_OFFSET_HOR_MAX ? NVT_PVT_EDID_RANGE_OFFSET_AMOUNT : 0; + min_h_rate_offset = pLdd->rsvd2 & NVT_PVT_EDID_RANGE_OFFSET_HOR_MIN ? NVT_PVT_EDID_RANGE_OFFSET_AMOUNT : 0; + + if ((pRangeLimit->minVRate + min_v_rate_offset) > (pRangeLimit->maxVRate + max_v_rate_offset) || + (pRangeLimit->minHRate + min_h_rate_offset) > (pRangeLimit->maxHRate + max_h_rate_offset) || + pRangeLimit->maxVRate == 0 || + pRangeLimit->maxHRate == 0) + { + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_RANGE_LIMIT); + } + } + } + } + + // extension and size check + if ((NvU32)(p->bExtensionFlag + 1) * sizeof(EDIDV1STRUC) > length) + { + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXTENSION_COUNT); + } + + // validate extension blocks + for (j = 1; j <= p->bExtensionFlag; j++) + { + pExt = pEdid + sizeof(EDIDV1STRUC) * j; + + // check for 861 extension + switch (*pExt) + { + case NVT_EDID_EXTENSION_CTA: + ctaDTD_Offset = ((EIA861EXTENSION *)pExt)->offset; + // first sanity check on the extension block + if (get861ExtInfo(pExt, sizeof(EIA861EXTENSION), NULL) != NVT_STATUS_SUCCESS || + ((EIA861EXTENSION *)pExt)->revision < NVT_CEA861_REV_B) + { + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_CTA_BASIC); + } + + // 0 indicated there is no DTD and data collection in this block + if (ctaDTD_Offset == 0) + { + if(!isChecksumValid(pExt)) + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_CTA_CHECKSUM); + continue; + } + + // validate SVD block + ctaBlockTag = NVT_CEA861_GET_SHORT_DESCRIPTOR_TAG(((EIA861EXTENSION *)pExt)->data[0]); + pData_collection = ((EIA861EXTENSION *)pExt)->data; + + while ((ctaDTD_Offset - 4) > 0 && pData_collection != &pExt[ctaDTD_Offset] && + ctaBlockTag > NVT_CEA861_TAG_RSVD && ctaBlockTag <= NVT_CEA861_TAG_EXTENDED_FLAG) + { + ctaBlockTag = NVT_CEA861_GET_SHORT_DESCRIPTOR_TAG(*pData_collection); + ctaPayload = NVT_CEA861_GET_SHORT_DESCRIPTOR_SIZE(*pData_collection); + + if (parseCta861DataBlockInfo(pData_collection, (NvU32)ctaDTD_Offset - 4, NULL) == NVT_STATUS_SUCCESS) + { + pData_collection++; + if (ctaBlockTag == NVT_CEA861_TAG_VIDEO) + { + for (i=0; i < ctaPayload; i++) + { + vic = NVT_GET_CTA_8BIT_VIC(*pData_collection); + if (vic == 0 || vic > 255 || (vic >= 128 && vic <=192)) + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_CTA_SVD); + pData_collection++; + } + } + else if (ctaBlockTag == NVT_CEA861_TAG_EXTENDED_FLAG) + { + if (*pData_collection == NVT_CEA861_EXT_TAG_HF_EEODB) + { + if ((p->bVersionNumber != 0x01) || (p->bRevisionNumber != 0x03)) + { + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_CTA_INVALID_DATA_BLOCK); + pData_collection += ctaPayload; + } + else + { + ret &= ~NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXTENSION_COUNT); + extnCount = *(++pData_collection); + // check the EDID extension count value again because EDID extension block count + // value in EEODB override it and source shall ignore extension flag > 1 value + if ((extnCount + 1) != (length / (sizeof(EDIDV1STRUC)))) + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXTENSION_COUNT); + pData_collection++; + } + } + else + pData_collection += ctaPayload; + } + else if (ctaBlockTag == NVT_CEA861_TAG_RSVD || ctaBlockTag == NVT_CEA861_TAG_RSVD1) + { + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_CTA_TAG); + pData_collection += ctaPayload; + } + else + pData_collection += ctaPayload; + } + else + { + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_CTA_INVALID_DATA_BLOCK); + pData_collection += ctaPayload; + } + } + + // validate DTD blocks + pDTD = (DETAILEDTIMINGDESCRIPTOR *)&pExt[((EIA861EXTENSION *)pExt)->offset]; + while (pDTD->wDTPixelClock != 0 && (NvU8 *)pDTD - pExt < (int)sizeof(EIA861EXTENSION)) + { + if (parseEdidDetailedTimingDescriptor((NvU8 *)pDTD, NULL) != NVT_STATUS_SUCCESS) + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_DTD); + else + { + // check the max image size and + if (p->bMaxHorizImageSize != 0 && p->bMaxVertImageSize != 0) + { + NvU16 hDTDImageSize = (pDTD->bDTHorizVertImage & 0xF0) << 4 | pDTD->bDTHorizontalImage; + NvU16 vDTDImageSize = (pDTD->bDTHorizVertImage & 0x0F) << 8 | pDTD->bDTVerticalImage; + + if ((hDTDImageSize/10) > (p->bMaxHorizImageSize) || (vDTDImageSize/10) > p->bMaxVertImageSize) + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_CTA_DTD); + } + } + pDTD++; + } + + if(!isChecksumValid(pExt)) + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_CTA_CHECKSUM); + break; + case NVT_EDID_EXTENSION_DISPLAYID: + pDisplayid = ((DIDEXTENSION *)pExt); + if (pDisplayid->ext_count != 0) + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_DID_EXTCOUNT); + + if (pDisplayid->length != 0x79) + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_DID_SEC_SIZE); + + if (!isChecksumValid(pExt)) + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_DID_CHECKSUM); + + // check the DID2 data blocks + if ((pDisplayid->struct_version & 0xF0) >> 4 == 2) + { + if ((pDisplayid->struct_version & 0xFF) == 0x21) + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_DID_VERSION); + + did2ExtCount++; + + if (pDisplayid->use_case == 0 && did2ExtCount == 1) + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_DID2_USE_CASE); + + // check the DisplayId2 valid timing + pDID2Header = (DISPLAYID_2_0_DATA_BLOCK_HEADER*)pDisplayid->data; + pData_collection = pDisplayid->data; + + // Sanity check every data blocks + while (((pDID2Header->type >= DISPLAYID_2_0_BLOCK_TYPE_PRODUCT_IDENTITY && + pDID2Header->type <= DISPLAYID_2_0_BLOCK_TYPE_ARVR_LAYER) || + pDID2Header->type == DISPLAYID_2_0_BLOCK_TYPE_VENDOR_SPEC || + pDID2Header->type == DISPLAYID_2_0_BLOCK_TYPE_CTA_DATA) && pDID2Header->data_bytes != 0 && + (pData_collection - pExt < (int)sizeof(DIDEXTENSION))) + { + if (parseDisplayId20EDIDExtDataBlocks(pData_collection, did_section_length, &block_length, NULL) == NVT_STATUS_ERR) + { + if (pDID2Header->type == DISPLAYID_2_0_BLOCK_TYPE_TIMING_7) + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_DID2_TYPE7); + + if (pDID2Header->type == DISPLAYID_2_0_BLOCK_TYPE_RANGE_LIMITS) + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_RANGE_LIMIT); + + if (pDID2Header->type == DISPLAYID_2_0_BLOCK_TYPE_ADAPTIVE_SYNC) + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_DID2_ADAPTIVE_SYNC); + // add more data blocks tag here to evaluate + } + pData_collection += block_length; + pDID2Header = (DISPLAYID_2_0_DATA_BLOCK_HEADER*)pData_collection; + } + + // compare the remain 0 value are correct or not before meet checksum byte + for (i = 0; i <= (NvU32)(&pDisplayid->data[NVT_DID_MAX_EXT_PAYLOAD-1] - pData_collection); i++) + { + if (pData_collection[i] != 0) + { + bAllZero = NV_FALSE; + break; + } + } + + // if the first tag failed, ignore all the tags afterward then + if (!bAllZero && + (pDID2Header->type < DISPLAYID_2_0_BLOCK_TYPE_PRODUCT_IDENTITY || + (pDID2Header->type > DISPLAYID_2_0_BLOCK_TYPE_ARVR_LAYER && + pDID2Header->type != DISPLAYID_2_0_BLOCK_TYPE_VENDOR_SPEC && + pDID2Header->type != DISPLAYID_2_0_BLOCK_TYPE_CTA_DATA)) && + (pData_collection - pExt < (int)sizeof(DIDEXTENSION))) + { + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_DID2_TAG); + continue; + } + } + else if ((pDisplayid->struct_version & 0xFF) == 0x12 || (pDisplayid->struct_version & 0xFF) == 0x13) + { + if ((pDisplayid->struct_version & 0xFF) == 0x13) + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_DID_VERSION); + + pHeader = (DISPLAYID_DATA_BLOCK_HEADER*)pDisplayid->data; + pData_collection = pDisplayid->data; + + // Sanity check every data blocks + while ((pHeader->type <= NVT_DISPLAYID_BLOCK_TYPE_TILEDDISPLAY || + pHeader->type == NVT_DISPLAYID_BLOCK_TYPE_CTA_DATA || + pHeader->type == NVT_DISPLAYID_BLOCK_TYPE_VENDOR_SPEC) && pHeader->data_bytes != 0 && + (pData_collection - pExt < (int)sizeof(DIDEXTENSION))) + { + if (parseDisplayIdBlock(pData_collection, did_section_length, &block_length, NULL) == NVT_STATUS_ERR) + { + if (pHeader->type == NVT_DISPLAYID_BLOCK_TYPE_TIMING_1) + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_DID13_TYPE1); + + if (pHeader->type == NVT_DISPLAYID_BLOCK_TYPE_RANGE_LIMITS) + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_RANGE_LIMIT); + + // add more data blocks tag here to evaluate + } + pData_collection += block_length; + pHeader = (DISPLAYID_DATA_BLOCK_HEADER*)pData_collection; + } + + // compare the remain 0 value are correct or not before meet checksum byte + for (i = 0; i <= (NvU32)(&pDisplayid->data[NVT_DID_MAX_EXT_PAYLOAD-1] - pData_collection); i++) + { + if (pData_collection[i] != 0) + { + bAllZero = NV_FALSE; + break; + } + } + + // if the first tag failed, ignore all the tags afterward then + if (!bAllZero && + pHeader->type > NVT_DISPLAYID_BLOCK_TYPE_TILEDDISPLAY && + pHeader->type != NVT_DISPLAYID_BLOCK_TYPE_CTA_DATA && + pHeader->type != NVT_DISPLAYID_BLOCK_TYPE_VENDOR_SPEC && + (pData_collection - pExt < (int)sizeof(DIDEXTENSION))) + { + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_DID13_TAG); + continue; + } + } + else + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_DID_VERSION); + break; + default: + // the useful extension only CTA (0x02) and DisplayID (0x70) + if ( *pExt != NVT_EDID_EXTENSION_VTB && *pExt != NVT_EDID_EXTENSION_DI && + *pExt != NVT_EDID_EXTENSION_LS && *pExt != NVT_EDID_EXTENSION_DPVL && + *pExt != NVT_EDID_EXTENSION_BM && *pExt != NVT_EDID_EXTENSION_OEM ) + { + ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXTENSION_TAG); + } + break; + } } return ret; @@ -2335,6 +2708,8 @@ CODE_SEGMENT(PAGE_DD_CODE) NvBool assignNextAvailableTiming(NVT_EDID_INFO *pInfo, const NVT_TIMING *pTiming) { + if (pInfo == NULL) return NV_TRUE; + // Don't write past the end of // pInfo->timing[NVT_EDID_MAX_TOTAL_TIMING] if (pInfo->total_timings >= COUNT(pInfo->timing)) { @@ -2386,7 +2761,7 @@ NvU32 NvTiming_CalculateEDIDCRC32(NvU8* pEDIDBuffer, NvU32 edidsize) return calculateCRC32(pEDIDBuffer, edidsize); } -//Calculates EDID's CRC after purging 'Week of Manufacture', 'Year of Manufacture', +//Calculates EDID/DisplayID2 CRC after purging 'Week of Manufacture', 'Year of Manufacture', //'Product ID String' & 'Serial Number' from EDID CODE_SEGMENT(PAGE_DD_CODE) NvU32 NvTiming_CalculateCommonEDIDCRC32(NvU8* pEDIDBuffer, NvU32 edidVersion) @@ -2403,30 +2778,64 @@ NvU32 NvTiming_CalculateCommonEDIDCRC32(NvU8* pEDIDBuffer, NvU32 edidVersion) // Transfer over the original EDID buffer NVMISC_MEMCPY(CommonEDIDBuffer, pEDIDBuffer, 256); - // Wipe out the Serial Number, Week of Manufacture, and Year of Manufacture or Model Year - NVMISC_MEMSET(CommonEDIDBuffer + 0x0C, 0, 6); - - // Wipe out the checksums - CommonEDIDBuffer[0x7F] = 0; - CommonEDIDBuffer[0xFF] = 0; - - // We also need to zero out any "EDID Other Monitor Descriptors" (https://en.wikipedia.org/wiki/Extended_display_identification_data) - for (edidBufferIndex = 54; edidBufferIndex <= 108; edidBufferIndex += 18) + if ((pEDIDBuffer[0] & 0xF0) == 0x20) { - if (CommonEDIDBuffer[edidBufferIndex] == 0 && CommonEDIDBuffer[edidBufferIndex+1] == 0) + /* + typedef struct DisplayId2Struct { - // Wipe this block out. It contains OEM-specific details that contain things like serial numbers - NVMISC_MEMSET(CommonEDIDBuffer + edidBufferIndex, 0, 18); - } - } + NvU8 bVersion; // 0x00 + NvU8 bSectionBytes; // 0x01 - section length, exclusive the five mandatory bytes. + NvU8 bwPrimaryUseCase; // 0x02 + NvU8 bExtensionCount; // 0x03 + // 0x20 DisplayId2 Standalone always exists Product Identification data block + NvU8 bProductIdtag; // 0x04 + NvU8 bPIDRevision; // 0x05 + NvU8 bPayloadByte; // 0x06 + NvU8 bManuId[3]; // 0x07-0x09 + NvU16 wProductId; // 0x0A-0x0B + NvU32 dwSerialNum; // 0x0C-0x0F + NvU16 wWeekandYear; // 0x10-0x11 + NvU8 SizeOfProductNameString; // 0x12 + } DISPLAY_ID2_FIXED_FORMAT; + */ - // Check what size we should do the compare against - if ( edidVersion > NVT_EDID_VER_1_4 ) - { + // Wipe out the Serial Number, Week of Manufacture, and Year of Manufacture or Model Year + NVMISC_MEMSET(CommonEDIDBuffer + 0x0C, 0, 6); + + // Wipe out the checksums + CommonEDIDBuffer[CommonEDIDBuffer[1]+5/*mandatory bytes*/-1] = 0; + CommonEDIDBuffer[0xFF] = 0; + + // zero out any Produc Name in Prodcut Identification data block + if (CommonEDIDBuffer[0x12] != 0) + { + NVMISC_MEMSET(CommonEDIDBuffer + 0x13, 0, CommonEDIDBuffer[0x12]); + CommonEDIDBuffer[0x12] = 0; + } + + // displayId2 standalone uses 256 length sections commonEDIDBufferSize = 256; } - else + else { + // Wipe out the Serial Number, Week of Manufacture, and Year of Manufacture or Model Year + NVMISC_MEMSET(CommonEDIDBuffer + 0x0C, 0, 6); + + // Wipe out the checksums + CommonEDIDBuffer[0x7F] = 0; + CommonEDIDBuffer[0xFF] = 0; + + // We also need to zero out any "EDID Other Monitor Descriptors" (http://en.wikipedia.org/wiki/Extended_display_identification_data) + for (edidBufferIndex = 54; edidBufferIndex <= 108; edidBufferIndex += 18) + { + if (CommonEDIDBuffer[edidBufferIndex] == 0 && CommonEDIDBuffer[edidBufferIndex+1] == 0) + { + // Wipe this block out. It contains OEM-specific details that contain things like serial numbers + NVMISC_MEMSET(CommonEDIDBuffer + edidBufferIndex, 0, 18); + } + } + + // Check what size we should do the compare against commonEDIDBufferSize = 128; } diff --git a/src/common/modeset/timing/nvt_edidext_861.c b/src/common/modeset/timing/nvt_edidext_861.c index 4dd5b859f..7fc19e443 100644 --- a/src/common/modeset/timing/nvt_edidext_861.c +++ b/src/common/modeset/timing/nvt_edidext_861.c @@ -880,7 +880,7 @@ void parseCea861HdrStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, } CODE_SEGMENT(PAGE_DD_CODE) -void parseCea861DvStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, NVT_DV_STATIC_METADATA *pDvInfo) +void parseCea861DvStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag) { NvU32 vsvdbVersion = 0; NVT_DV_STATIC_METADATA_TYPE0 *pDvType0 = NULL; @@ -888,7 +888,26 @@ void parseCea861DvStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, NVT_DV_ NVT_DV_STATIC_METADATA_TYPE1_1 *pvDvType1_1 = NULL; NVT_DV_STATIC_METADATA_TYPE2 *pDvType2 = NULL; - if (pExt861 == NULL || pDvInfo == NULL) + NVT_EDID_INFO *pInfo = NULL; + NVT_DISPLAYID_2_0_INFO *pDisplayID20 = NULL; + NVT_DV_STATIC_METADATA *pDvInfo = NULL; + + if (pExt861 == NULL || pRawInfo == NULL) + { + return; + } + + if (flag == FROM_CTA861_EXTENSION || flag == FROM_DISPLAYID_13_DATA_BLOCK) + { + pInfo = (NVT_EDID_INFO *)pRawInfo; + pDvInfo = &pInfo->dv_static_metadata_info; + } + else if (flag == FROM_DISPLAYID_20_DATA_BLOCK) + { + pDisplayID20 = (NVT_DISPLAYID_2_0_INFO *)pRawInfo; + pDvInfo = &pDisplayID20->cta.dvInfo; + } + else { return; } @@ -898,6 +917,7 @@ void parseCea861DvStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, NVT_DV_ return; } + //init NVMISC_MEMSET(pDvInfo, 0, sizeof(NVT_DV_STATIC_METADATA)); @@ -1004,10 +1024,10 @@ void parseCea861DvStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, NVT_DV_ pDvInfo->supports_backlight_control = pDvType2->supports_backlight_control; pDvInfo->supports_YUV422_12bit = pDvType2->supports_YUV422_12bit; pDvInfo->dm_version = pDvType2->dm_version; - pDvInfo->backlt_min_luma = pDvType2->backlt_min_luma; pDvInfo->supports_global_dimming = pDvType2->supports_global_dimming; pDvInfo->target_min_luminance = pDvType2->target_min_luminance; pDvInfo->interface_supported_by_sink = pDvType2->interface_supported_by_sink; + pDvInfo->parity = pDvType2->parity; pDvInfo->target_max_luminance = pDvType2->target_max_luminance; pDvInfo->cc_green_x = NVT_DOLBY_CHROMATICITY_MSB_GX | pDvType2->unique_Gx; pDvInfo->cc_green_y = NVT_DOLBY_CHROMATICITY_MSB_GY | pDvType2->unique_Gy; @@ -1213,8 +1233,13 @@ NVT_STATUS get861ExtInfo(NvU8 *p, NvU32 size, NVT_EDID_CEA861_INFO *p861info) return NVT_STATUS_ERR; } + // DTD offset sanity check + if (p[2] >= 1 && p[2] <= 3) + { + return NVT_STATUS_ERR; + } - // don't do anything further if p is NULL + // don't do anything further if p861info is NULL if (p861info == NULL) { return NVT_STATUS_SUCCESS; @@ -1251,7 +1276,8 @@ NVT_STATUS get861ExtInfo(NvU8 *p, NvU32 size, NVT_EDID_CEA861_INFO *p861info) return parseCta861DataBlockInfo(&p[4], dtd_offset - 4, p861info); } -// get the 861 extension tags info +// 1. get the 861 extension tags info +// 2. or validation purpose if p861info == NULL CODE_SEGMENT(PAGE_DD_CODE) NVT_STATUS parseCta861DataBlockInfo(NvU8 *p, NvU32 size, @@ -1265,6 +1291,7 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p, NvU32 yuv420vdb_index = 0; NvU32 yuv420cmdb_index = 0; NvU8 svr_index = 0; + NvU32 ieee_id = 0; NvU32 tag, ext_tag, payload; i= 0; @@ -1276,6 +1303,42 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p, // move the pointer to the payload section i++; + + // NvTiming_EDIDValidationMask will use the different tag/payload value to make sure each of cta861 data block legal + if (p861info == NULL) + { + switch(tag) + { + case NVT_CEA861_TAG_AUDIO: + case NVT_CEA861_TAG_VIDEO: + case NVT_CEA861_TAG_SPEAKER_ALLOC: + case NVT_CEA861_TAG_VESA_DTC: + case NVT_CEA861_TAG_RSVD: + case NVT_CEA861_TAG_RSVD1: + break; + case NVT_CEA861_TAG_VENDOR: + if (payload < 3) return NVT_STATUS_ERR; + break; + case NVT_CEA861_TAG_EXTENDED_FLAG: + if (payload >= 1) + { + ext_tag = p[i]; + if (ext_tag == NVT_CEA861_EXT_TAG_VIDEO_CAP && payload < 2) return NVT_STATUS_ERR; + else if (ext_tag == NVT_CEA861_EXT_TAG_COLORIMETRY && payload < 3) return NVT_STATUS_ERR; + else if (ext_tag == NVT_CEA861_EXT_TAG_VIDEO_FORMAT_PREFERENCE && payload < 2) return NVT_STATUS_ERR; + else if (ext_tag == NVT_CEA861_EXT_TAG_YCBCR420_VIDEO && payload < 2) return NVT_STATUS_ERR; + else if (ext_tag == NVT_CEA861_EXT_TAG_YCBCR420_CAP && payload < 1) return NVT_STATUS_ERR; + else if (ext_tag == NVT_CEA861_EXT_TAG_HDR_STATIC_METADATA && payload < 3) return NVT_STATUS_ERR; + else if (ext_tag == NVT_CEA861_EXT_TAG_VENDOR_SPECIFIC_VIDEO && payload < 4) return NVT_STATUS_ERR; + else if (ext_tag == NVT_CTA861_EXT_TAG_SCDB && payload < 7) return NVT_STATUS_ERR; + else if (ext_tag == NVT_CEA861_EXT_TAG_HF_EEODB && payload != 2) return NVT_STATUS_ERR; + } + break; + default: + break; + } + return NVT_STATUS_SUCCESS; + } // loop through all descriptors if (tag == NVT_CEA861_TAG_VIDEO) @@ -1447,30 +1510,46 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p, p861info->valid.hdr_static_metadata = 1; } - else if(ext_tag == NVT_CEA861_EXT_TAG_VENDOR_SPECIFIC_VIDEO && ((payload >= 14) || (payload >= 11))) //version 2 of VSDB has 11 bytes of data and version 1 has 14 + else if(ext_tag == NVT_CEA861_EXT_TAG_VENDOR_SPECIFIC_VIDEO) { + ieee_id = p[i + 1]; //IEEE ID low byte + ieee_id |= (p[i + 2]) << 8; //IEEE ID middle byte + ieee_id |= (p[i + 3]) << 16; //IEEE ID high byte - // exclude the extended tag - i++; payload--; - - p861info->vsvdb.ieee_id = p[i]; //IEEE ID low byte - p861info->vsvdb.ieee_id |= (p[i + 1]) << 8; //IEEE ID middle byte - p861info->vsvdb.ieee_id |= (p[i + 2]) << 16; //IEEE ID high byte - - p861info->vsvdb.vendor_data_size = payload - 3; - - // move the pointer to the payload - i += 3; - - // get the other vendor specific video data - for (j = 0; j < payload - 3; j++, i++) + if ((ieee_id == NVT_CEA861_DV_IEEE_ID) || (ieee_id == NVT_CEA861_HDR10PLUS_IEEE_ID)) { - if (j < NVT_CEA861_VSDB_PAYLOAD_MAX_LENGTH) + // exclude the extended tag + i++; payload--; + + p861info->vsvdb.ieee_id = ieee_id; + p861info->vsvdb.vendor_data_size = payload - 3; + + // move the pointer to the payload + i += 3; + + // get the other vendor specific video data + for (j = 0; j < payload - 3; j++, i++) { - p861info->vsvdb.vendor_data[j] = p[i]; + if (j < NVT_CEA861_VSVDB_PAYLOAD_MAX_LENGTH) + { + p861info->vsvdb.vendor_data[j] = p[i]; + } + } + + if (p861info->vsvdb.ieee_id == NVT_CEA861_DV_IEEE_ID) + { + p861info->valid.dv_static_metadata = 1; + } + else if (p861info->vsvdb.ieee_id == NVT_CEA861_HDR10PLUS_IEEE_ID) + { + p861info->valid.hdr10Plus = 1; } } - p861info->valid.dv_static_metadata = 1; + else + { + // skip the unsupported extended block + i += payload; + } } else if(ext_tag == NVT_CTA861_EXT_TAG_SCDB && payload >= 7) // sizeof(HDMI Forum Sink Capability Data Block) ranges between 7 to 31 bytes { @@ -1528,6 +1607,9 @@ NVT_STATUS NvTiming_EnumCEA861bTiming(NvU32 ceaFormat, NVT_TIMING *pT) ceaFormat = NVT_GET_CTA_8BIT_VIC(ceaFormat); + if (ceaFormat ==0) + return NVT_STATUS_ERR; + *pT = EIA861B[ceaFormat - 1]; // calculate the pixel clock @@ -2935,8 +3017,49 @@ void parseEdidHdmiForumVSDB(VSDB_DATA *pVsdb, NVT_HDMI_FORUM_INFO *pHdmiInfo) default: break; + } +} + +CODE_SEGMENT(PAGE_DD_CODE) +void parseCea861Hdr10PlusDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag) +{ + NVT_EDID_INFO *pInfo = NULL; + NVT_DISPLAYID_2_0_INFO *pDisplayID20 = NULL; + NVT_HDR10PLUS_INFO *pHdr10PlusInfo = NULL; + + if (pExt861 == NULL || pRawInfo == NULL) + { + return; } - + + if (flag == FROM_CTA861_EXTENSION || flag == FROM_DISPLAYID_13_DATA_BLOCK) + { + pInfo = (NVT_EDID_INFO *)pRawInfo; + pHdr10PlusInfo = &pInfo->hdr10PlusInfo; + } + else if (flag == FROM_DISPLAYID_20_DATA_BLOCK) + { + pDisplayID20 = (NVT_DISPLAYID_2_0_INFO *)pRawInfo; + pHdr10PlusInfo = &pDisplayID20->cta.hdr10PlusInfo; + } + else + { + return; + } + + if(pExt861->vsvdb.ieee_id != NVT_CEA861_HDR10PLUS_IEEE_ID) + { + return; + } + + NVMISC_MEMSET(pHdr10PlusInfo, 0, sizeof(NVT_HDR10PLUS_INFO)); + + if (pExt861->vsvdb.vendor_data_size < sizeof(NVT_HDR10PLUS_INFO)) + { + return; + } + + NVMISC_MEMCPY(pHdr10PlusInfo, &pExt861->vsvdb.vendor_data, sizeof(NVT_HDR10PLUS_INFO)); } POP_SEGMENTS diff --git a/src/common/modeset/timing/nvt_edidext_displayid.c b/src/common/modeset/timing/nvt_edidext_displayid.c index e0b3a17a2..7862d848a 100644 --- a/src/common/modeset/timing/nvt_edidext_displayid.c +++ b/src/common/modeset/timing/nvt_edidext_displayid.c @@ -1,6 +1,6 @@ //***************************************************************************** // -// SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +// SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-License-Identifier: MIT // // Permission is hereby granted, free of charge, to any person obtaining a @@ -30,7 +30,6 @@ #include "nvBinSegment.h" #include "nvmisc.h" -#include "displayid.h" #include "edid.h" PUSH_SEGMENTS @@ -38,10 +37,6 @@ PUSH_SEGMENTS static NVT_STATUS parseDisplayIdSection(DISPLAYID_SECTION * section, NvU32 max_length, NVT_EDID_INFO *pEdidInfo); -static NVT_STATUS parseDisplayIdBlock(NvU8 * block, - NvU8 max_length, - NvU8 * pLength, - NVT_EDID_INFO *pEdidInfo); // Specific blocks that can be parsed based on DisplayID static NVT_STATUS parseDisplayIdProdIdentityBlock(NvU8 * block, NVT_DISPLAYID_INFO *pInfo); @@ -51,7 +46,7 @@ static NVT_STATUS parseDisplayIdTiming1(NvU8 * block, NVT_EDID_INFO *pEdidInfo); static NVT_STATUS parseDisplayIdTiming2(NvU8 * block, NVT_EDID_INFO *pEdidInfo); static NVT_STATUS parseDisplayIdTiming3(NvU8 * block, NVT_EDID_INFO *pEdidInfo); static NVT_STATUS parseDisplayIdTiming4(NvU8 * block, NVT_EDID_INFO *pEdidInfo); -static NVT_STATUS parseDisplayIdTiming5(NvU8 * block, NVT_EDID_INFO *pEdidInfo, NVT_DISPLAYID_INFO *pInfo); +static NVT_STATUS parseDisplayIdTiming5(NvU8 * block, NVT_EDID_INFO *pEdidInfo); static NVT_STATUS parseDisplayIdTimingVesa(NvU8 * block, NVT_EDID_INFO *pEdidInfo); static NVT_STATUS parseDisplayIdTimingEIA(NvU8 * block, NVT_EDID_INFO *pEdidInfo); static NVT_STATUS parseDisplayIdRangeLimits(NvU8 * block, NVT_DISPLAYID_INFO *pInfo); @@ -63,7 +58,7 @@ static NVT_STATUS parseDisplayIdTransferChar(NvU8 * block, NVT_DISPLAYID_INFO *p static NVT_STATUS parseDisplayIdDisplayInterface(NvU8 * block, NVT_DISPLAYID_INFO *pInfo); static NVT_STATUS parseDisplayIdStereo(NvU8 * block, NVT_DISPLAYID_INFO *pInfo); static NVT_STATUS parseDisplayIdTiledDisplay(NvU8 * block, NVT_DISPLAYID_INFO *pInfo); -static NVT_STATUS parseDisplayIdCtaData(NvU8 * block, NVT_EDID_INFO *pInfo, NVT_DISPLAYID_INFO *pDisplayIdInfo); +static NVT_STATUS parseDisplayIdCtaData(NvU8 * block, NVT_EDID_INFO *pInfo); static NVT_STATUS parseDisplayIdDisplayInterfaceFeatures(NvU8 * block, NVT_DISPLAYID_INFO *pInfo); static NVT_STATUS parseDisplayIdTiming1Descriptor(DISPLAYID_TIMING_1_DESCRIPTOR * desc, NVT_TIMING *pT); @@ -232,7 +227,7 @@ static NVT_STATUS parseDisplayIdSection(DISPLAYID_SECTION * section, while (block_location < section->section_bytes) { DISPLAYID_DATA_BLOCK_HEADER * hdr = (DISPLAYID_DATA_BLOCK_HEADER *) (section->data + block_location); - NvU8 is_prod_id = remaining_length > 3 && block_location == 0 && hdr->type == 0 && hdr->data_bytes > 0; + NvBool is_prod_id = remaining_length > 3 && block_location == 0 && hdr->type == 0 && hdr->data_bytes > 0; NvU8 i; // Check the padding. @@ -265,90 +260,106 @@ static NVT_STATUS parseDisplayIdSection(DISPLAYID_SECTION * section, return NVT_STATUS_SUCCESS; } +/** + * @brief Parses a displayID data block + * @param block The DisplayID data block to parse + * @param max_length The indicated total length of the each data block for checking + * @param pLength return the indicated length of the each data block + * @param pEdidInfo EDID struct containing DisplayID information and + * the timings or validation purpose if it is NULL + */ CODE_SEGMENT(PAGE_DD_CODE) -static NVT_STATUS parseDisplayIdBlock(NvU8 * block, - NvU8 max_length, - NvU8 * pLength, - NVT_EDID_INFO *pEdidInfo) +NVT_STATUS parseDisplayIdBlock(NvU8* pBlock, + NvU8 max_length, + NvU8* pLength, + NVT_EDID_INFO *pEdidInfo) { - DISPLAYID_DATA_BLOCK_HEADER * hdr = (DISPLAYID_DATA_BLOCK_HEADER *) block; - NVT_DISPLAYID_INFO *pInfo = &pEdidInfo->ext_displayid; + DISPLAYID_DATA_BLOCK_HEADER * hdr = (DISPLAYID_DATA_BLOCK_HEADER *) pBlock; + NVT_STATUS ret = NVT_STATUS_SUCCESS; + NVT_DISPLAYID_INFO *pInfo; - if (block == NULL || max_length <= NVT_DISPLAYID_DATABLOCK_HEADER_LEN) + if (pBlock == NULL || max_length <= NVT_DISPLAYID_DATABLOCK_HEADER_LEN) return NVT_STATUS_ERR; + if (hdr->data_bytes > max_length - NVT_DISPLAYID_DATABLOCK_HEADER_LEN) return NVT_STATUS_ERR; + pInfo = pEdidInfo == NULL ? NULL : &pEdidInfo->ext_displayid; + *pLength = hdr->data_bytes + NVT_DISPLAYID_DATABLOCK_HEADER_LEN; switch (hdr->type) { case NVT_DISPLAYID_BLOCK_TYPE_PRODUCT_IDENTITY: - parseDisplayIdProdIdentityBlock(block, pInfo); + ret = parseDisplayIdProdIdentityBlock(pBlock, pInfo); break; case NVT_DISPLAYID_BLOCK_TYPE_DISPLAY_PARAM: - parseDisplayIdParam(block, pInfo); + ret = parseDisplayIdParam(pBlock, pInfo); break; case NVT_DISPLAYID_BLOCK_TYPE_COLOR_CHAR: - parseDisplayIdColorChar(block, pInfo); + ret = parseDisplayIdColorChar(pBlock, pInfo); break; case NVT_DISPLAYID_BLOCK_TYPE_TIMING_1: - parseDisplayIdTiming1(block, pEdidInfo); + ret = parseDisplayIdTiming1(pBlock, pEdidInfo); break; case NVT_DISPLAYID_BLOCK_TYPE_TIMING_2: - parseDisplayIdTiming2(block, pEdidInfo); + ret = parseDisplayIdTiming2(pBlock, pEdidInfo); break; case NVT_DISPLAYID_BLOCK_TYPE_TIMING_3: - parseDisplayIdTiming3(block, pEdidInfo); + ret = parseDisplayIdTiming3(pBlock, pEdidInfo); break; case NVT_DISPLAYID_BLOCK_TYPE_TIMING_4: - parseDisplayIdTiming4(block, pEdidInfo); + ret = parseDisplayIdTiming4(pBlock, pEdidInfo); break; case NVT_DISPLAYID_BLOCK_TYPE_TIMING_5: - parseDisplayIdTiming5(block, pEdidInfo, pInfo); + ret = parseDisplayIdTiming5(pBlock, pEdidInfo); break; case NVT_DISPLAYID_BLOCK_TYPE_TIMING_VESA: - parseDisplayIdTimingVesa(block, pEdidInfo); + ret = parseDisplayIdTimingVesa(pBlock, pEdidInfo); break; case NVT_DISPLAYID_BLOCK_TYPE_TIMING_CEA: - parseDisplayIdTimingEIA(block, pEdidInfo); + ret = parseDisplayIdTimingEIA(pBlock, pEdidInfo); break; case NVT_DISPLAYID_BLOCK_TYPE_RANGE_LIMITS: - parseDisplayIdRangeLimits(block, pInfo); + ret = parseDisplayIdRangeLimits(pBlock, pInfo); break; case NVT_DISPLAYID_BLOCK_TYPE_SERIAL_NUMBER: - parseDisplayIdSerialNumber(block, pInfo); + ret = parseDisplayIdSerialNumber(pBlock, pInfo); break; case NVT_DISPLAYID_BLOCK_TYPE_ASCII_STRING: - parseDisplayIdAsciiString(block, pInfo); + ret = parseDisplayIdAsciiString(pBlock, pInfo); break; case NVT_DISPLAYID_BLOCK_TYPE_DEVICE_DATA: - parseDisplayIdDeviceData(block, pInfo); + ret = parseDisplayIdDeviceData(pBlock, pInfo); break; case NVT_DISPLAYID_BLOCK_TYPE_INTERFACE_POWER: - parseDisplayIdInterfacePower(block, pInfo); + ret = parseDisplayIdInterfacePower(pBlock, pInfo); break; case NVT_DISPLAYID_BLOCK_TYPE_TRANSFER_CHAR: - parseDisplayIdTransferChar(block, pInfo); + ret = parseDisplayIdTransferChar(pBlock, pInfo); break; case NVT_DISPLAYID_BLOCK_TYPE_DISPLAY_INTERFACE: - parseDisplayIdDisplayInterface(block, pInfo); + ret = parseDisplayIdDisplayInterface(pBlock, pInfo); break; case NVT_DISPLAYID_BLOCK_TYPE_STEREO: - parseDisplayIdStereo(block, pInfo); + ret = parseDisplayIdStereo(pBlock, pInfo); break; case NVT_DISPLAYID_BLOCK_TYPE_TILEDDISPLAY: - parseDisplayIdTiledDisplay(block, pInfo); + ret = parseDisplayIdTiledDisplay(pBlock, pInfo); break; case NVT_DISPLAYID_BLOCK_TYPE_CTA_DATA: - parseDisplayIdCtaData(block, pEdidInfo, pInfo); + ret = parseDisplayIdCtaData(pBlock, pEdidInfo); break; case NVT_DISPLAYID_BLOCK_TYPE_DISPLAY_INTERFACE_FEATURES: - parseDisplayIdDisplayInterfaceFeatures(block, pInfo); + ret = parseDisplayIdDisplayInterfaceFeatures(pBlock, pInfo); break; default: + ret = NVT_STATUS_ERR; break; } + + if (pEdidInfo == NULL) return ret; + return NVT_STATUS_SUCCESS; } CODE_SEGMENT(PAGE_DD_CODE) @@ -371,6 +382,8 @@ static NVT_STATUS parseDisplayIdColorChar(NvU8 * block, NVT_DISPLAYID_INFO *pInf return NVT_STATUS_ERR; } + if (pInfo == NULL) return NVT_STATUS_SUCCESS; + for (i = 0; i < prim_num; i++) { x_p = (blk->points)[i].color_x_bits_low + @@ -408,6 +421,8 @@ static NVT_STATUS parseDisplayIdProdIdentityBlock(NvU8 * block, NVT_DISPLAYID_IN return NVT_STATUS_ERR; } + if (pInfo == NULL) return NVT_STATUS_SUCCESS; + pInfo->vendor_id = (blk->vendor)[2] | ((blk->vendor)[1] << 8) | ((blk->vendor)[0] << 16); pInfo->product_id = blk->product_code; pInfo->serial_number = blk->serial_number; @@ -432,6 +447,8 @@ static NVT_STATUS parseDisplayIdParam(NvU8 * block, NVT_DISPLAYID_INFO *pInfo) return NVT_STATUS_ERR; } + if (pInfo == NULL) return NVT_STATUS_SUCCESS; + pInfo->horiz_size = blk->horizontal_image_size; pInfo->vert_size = blk->vertical_image_size; pInfo->horiz_pixels = blk->horizontal_pixel_count; @@ -474,11 +491,17 @@ static NVT_STATUS parseDisplayIdTiming1(NvU8 * block, NVT_EDID_INFO *pEdidInfo) if (parseDisplayIdTiming1Descriptor(blk->descriptors + i, &newTiming) == NVT_STATUS_SUCCESS) { + if (pEdidInfo == NULL) continue; + if (!assignNextAvailableTiming(pEdidInfo, &newTiming)) { break; } } + else + { + if (pEdidInfo == NULL) return NVT_STATUS_ERR; + } } return NVT_STATUS_SUCCESS; } @@ -610,11 +633,17 @@ static NVT_STATUS parseDisplayIdTiming2(NvU8 * block, NVT_EDID_INFO *pEdidInfo) if (parseDisplayIdTiming2Descriptor(blk->descriptors + i, &newTiming) == NVT_STATUS_SUCCESS) { + if (pEdidInfo == NULL) continue; + if (!assignNextAvailableTiming(pEdidInfo, &newTiming)) { break; } } + else + { + if (pEdidInfo == NULL) return NVT_STATUS_ERR; + } } return NVT_STATUS_SUCCESS; } @@ -777,11 +806,17 @@ static NVT_STATUS parseDisplayIdTiming3(NvU8 * block, NVT_EDID_INFO *pEdidInfo) if (parseDisplayIdTiming3Descriptor(blk->descriptors + i, &newTiming) == NVT_STATUS_SUCCESS) { + if (pEdidInfo == NULL) continue; + if (!assignNextAvailableTiming(pEdidInfo, &newTiming)) { break; } } + else + { + if (pEdidInfo == NULL) return NVT_STATUS_ERR; + } } return NVT_STATUS_SUCCESS; } @@ -806,11 +841,17 @@ static NVT_STATUS parseDisplayIdTiming4(NvU8 * block, NVT_EDID_INFO *pEdidInfo) if (NvTiming_EnumDMT((NvU32)(blk->timing_codes[i]), &newTiming) == NVT_STATUS_SUCCESS) { + if (pEdidInfo == NULL) continue; + if (!assignNextAvailableTiming(pEdidInfo, &newTiming)) { break; } } + else + { + if (pEdidInfo == NULL) return NVT_STATUS_ERR; + } } return NVT_STATUS_SUCCESS; } @@ -837,7 +878,7 @@ static NVT_STATUS parseDisplayIdTiming5Descriptor(DISPLAYID_TIMING_5_DESCRIPTOR } CODE_SEGMENT(PAGE_DD_CODE) -static NVT_STATUS parseDisplayIdTiming5(NvU8 * block, NVT_EDID_INFO *pEdidInfo, NVT_DISPLAYID_INFO *pInfo) +static NVT_STATUS parseDisplayIdTiming5(NvU8 * block, NVT_EDID_INFO *pEdidInfo) { NvU16 i; NVT_TIMING newTiming; @@ -854,11 +895,17 @@ static NVT_STATUS parseDisplayIdTiming5(NvU8 * block, NVT_EDID_INFO *pEdidInfo, if (parseDisplayIdTiming5Descriptor(blk->descriptors + i, &newTiming) == NVT_STATUS_SUCCESS) { + if (pEdidInfo == NULL) continue; + if (!assignNextAvailableTiming(pEdidInfo, &newTiming)) { break; } } + else + { + if (pEdidInfo == NULL) return NVT_STATUS_ERR; + } } return NVT_STATUS_SUCCESS; } @@ -887,11 +934,17 @@ static NVT_STATUS parseDisplayIdTimingVesa(NvU8 * block, NVT_EDID_INFO *pEdidInf if (NvTiming_EnumDMT((NvU32)(i * 8 + j + 1), &newTiming) == NVT_STATUS_SUCCESS) { + if (pEdidInfo == NULL) continue; + if (!assignNextAvailableTiming(pEdidInfo, &newTiming)) { break; } } + else + { + if (pEdidInfo == NULL) return NVT_STATUS_ERR; + } } } } @@ -922,11 +975,17 @@ static NVT_STATUS parseDisplayIdTimingEIA(NvU8 * block, NVT_EDID_INFO *pEdidInfo if (NvTiming_EnumCEA861bTiming((NvU32)(i * 8 + j + 1), &newTiming) == NVT_STATUS_SUCCESS) { + if (pEdidInfo == NULL) continue; + if (!assignNextAvailableTiming(pEdidInfo, &newTiming)) { break; } } + else + { + if (pEdidInfo == NULL) return NVT_STATUS_ERR; + } } } } @@ -938,8 +997,31 @@ static NVT_STATUS parseDisplayIdRangeLimits(NvU8 * block, NVT_DISPLAYID_INFO *pI { NVT_DISPLAYID_RANGE_LIMITS * rl; DISPLAYID_RANGE_LIMITS_BLOCK * blk = (DISPLAYID_RANGE_LIMITS_BLOCK *)block; - if ((blk->header.data_bytes != DISPLAYID_RANGE_LIMITS_BLOCK_LEN) || - (pInfo->rl_num >= NVT_DISPLAYID_RANGE_LIMITS_MAX_COUNT)) + NVT_STATUS status = NVT_STATUS_SUCCESS; + NvU32 minPclk = 0; + NvU32 maxPclk = 0; + + if (blk->header.data_bytes != DISPLAYID_RANGE_LIMITS_BLOCK_LEN) + { + // Assert since this error is ignored + nvt_assert(0); + return NVT_STATUS_ERR; + } + + minPclk = blk->pixel_clock_min[0] | (blk->pixel_clock_min[1] << 8) | (blk->pixel_clock_min[2] << 16); + maxPclk = blk->pixel_clock_max[0] | (blk->pixel_clock_max[1] << 8) | (blk->pixel_clock_max[2] << 16); + + if (blk->vertical_refresh_rate_min == 0 || blk->vertical_refresh_rate_max == 0 || + blk->vertical_refresh_rate_min > blk->vertical_refresh_rate_max || + minPclk > maxPclk) + { + nvt_assert(0 && "wrong range limit"); + status = NVT_STATUS_ERR; + } + + if (pInfo == NULL) return status; + + if (pInfo->rl_num >= NVT_DISPLAYID_RANGE_LIMITS_MAX_COUNT) { // Assert since this error is ignored nvt_assert(0); @@ -949,8 +1031,8 @@ static NVT_STATUS parseDisplayIdRangeLimits(NvU8 * block, NVT_DISPLAYID_INFO *pI rl = pInfo->range_limits + pInfo->rl_num; (pInfo->rl_num)++; - rl->pclk_min = blk->pixel_clock_min[0] | (blk->pixel_clock_min[1] << 8) | (blk->pixel_clock_min[2] << 16); - rl->pclk_max = blk->pixel_clock_max[0] | (blk->pixel_clock_max[1] << 8) | (blk->pixel_clock_max[2] << 16); + rl->pclk_min = minPclk; + rl->pclk_max = maxPclk; rl->interlaced = DRF_VAL(T_DISPLAYID, _RANGE_LIMITS, _INTERLACE, blk->optns); rl->cvt = DRF_VAL(T_DISPLAYID, _RANGE_LIMITS, _CVT_STANDARD, blk->optns); @@ -978,6 +1060,8 @@ static NVT_STATUS parseDisplayIdSerialNumber(NvU8 * block, NVT_DISPLAYID_INFO *p return NVT_STATUS_ERR; } + if (pInfo == NULL) return NVT_STATUS_SUCCESS; + // Nothing is currently done to store any ASCII Serial Number, if it is // required. Code here may need to be modified sometime in the future, along // with NVT_DISPLAYID_INFO struct @@ -995,6 +1079,8 @@ static NVT_STATUS parseDisplayIdAsciiString(NvU8 * block, NVT_DISPLAYID_INFO *pI return NVT_STATUS_ERR; } + if (pInfo == NULL) return NVT_STATUS_SUCCESS; + // Nothing is currently done to store any ASCII String Data, if it is // required. Code here may need to be modified sometime in the future, along // with NVT_DISPLAYID_INFO struct @@ -1012,6 +1098,8 @@ static NVT_STATUS parseDisplayIdDeviceData(NvU8 * block, NVT_DISPLAYID_INFO *pIn return NVT_STATUS_ERR; } + if (pInfo == NULL) return NVT_STATUS_SUCCESS; + pInfo->tech_type = blk->technology; pInfo->device_op_mode = DRF_VAL(T_DISPLAYID, _DEVICE, _OPERATING_MODE, blk->operating_mode); @@ -1048,6 +1136,8 @@ static NVT_STATUS parseDisplayIdInterfacePower(NvU8 * block, NVT_DISPLAYID_INFO return NVT_STATUS_ERR; } + if (pInfo == NULL) return NVT_STATUS_SUCCESS; + // Note specifically that the data inside T1/T2 variables are the exact // interface power data. the millisecond increments are dependent on the // DisplayID specification. @@ -1065,6 +1155,8 @@ static NVT_STATUS parseDisplayIdInterfacePower(NvU8 * block, NVT_DISPLAYID_INFO CODE_SEGMENT(PAGE_DD_CODE) static NVT_STATUS parseDisplayIdTransferChar(NvU8 * block, NVT_DISPLAYID_INFO *pInfo) { + if (pInfo == NULL) return NVT_STATUS_SUCCESS; + // Transfer Characteristics are currently not supported, but parsing of the // block should be added in the future when more specifications on monitors // that require this information is located here. @@ -1081,6 +1173,9 @@ static NVT_STATUS parseDisplayIdDisplayInterface(NvU8 * block, NVT_DISPLAYID_INF nvt_assert(0); return NVT_STATUS_ERR; } + + if (pInfo == NULL) return NVT_STATUS_SUCCESS; + pInfo->supported_displayId2_0 = 0; // Type/Link Info @@ -1152,6 +1247,8 @@ static NVT_STATUS parseDisplayIdStereo(NvU8 * block, NVT_DISPLAYID_INFO *pInfo) return NVT_STATUS_ERR; } + if (pInfo == NULL) return NVT_STATUS_SUCCESS; + sub = blk->timing_sub_block; pInfo->stereo_code = blk->stereo_code; @@ -1196,6 +1293,8 @@ static NVT_STATUS parseDisplayIdTiledDisplay(NvU8 * block, NVT_DISPLAYID_INFO *p return NVT_STATUS_ERR; } + if (pInfo == NULL) return NVT_STATUS_SUCCESS; + // For revision 0, we only allow one tiled display data block. if (!blk->header.revision && pInfo->tile_topology_id.vendor_id) return NVT_STATUS_SUCCESS; @@ -1237,17 +1336,22 @@ static NVT_STATUS parseDisplayIdTiledDisplay(NvU8 * block, NVT_DISPLAYID_INFO *p } CODE_SEGMENT(PAGE_DD_CODE) -static NVT_STATUS parseDisplayIdCtaData(NvU8 * block, NVT_EDID_INFO *pInfo, NVT_DISPLAYID_INFO *pDisplayIdInfo) +static NVT_STATUS parseDisplayIdCtaData(NvU8 * block, NVT_EDID_INFO *pInfo) { DISPLAYID_DATA_BLOCK_HEADER * blk = (DISPLAYID_DATA_BLOCK_HEADER*)block; - NVT_EDID_CEA861_INFO *p861info = &pInfo->ext861; + NVT_EDID_CEA861_INFO *p861info; if (blk->data_bytes > NVT_DISPLAYID_DATABLOCK_MAX_PAYLOAD_LEN) { // Assert since this error is ignored nvt_assert(0); return NVT_STATUS_ERR; } - pDisplayIdInfo->cea_data_block_present = 1; + + if (pInfo == NULL) return NVT_STATUS_SUCCESS; + + p861info = &pInfo->ext861; + + pInfo->ext_displayid.cea_data_block_present = 1; p861info->revision = blk->revision; //parse CEA tags which starts at 3rd byte from block @@ -1287,6 +1391,9 @@ static NVT_STATUS parseDisplayIdDisplayInterfaceFeatures(NvU8 * block, NVT_DISPL nvt_assert(0); return NVT_STATUS_ERR; } + + if (pInfo == NULL) return NVT_STATUS_SUCCESS; + pInfo->supported_displayId2_0 = 1; // Color Depths @@ -1342,5 +1449,4 @@ static NVT_STATUS parseDisplayIdDisplayInterfaceFeatures(NvU8 * block, NVT_DISPL return NVT_STATUS_SUCCESS; } - POP_SEGMENTS diff --git a/src/common/modeset/timing/nvt_edidext_displayid20.c b/src/common/modeset/timing/nvt_edidext_displayid20.c index 88bf0e110..2a2ad1955 100644 --- a/src/common/modeset/timing/nvt_edidext_displayid20.c +++ b/src/common/modeset/timing/nvt_edidext_displayid20.c @@ -30,14 +30,12 @@ #include "nvBinSegment.h" #include "nvmisc.h" -#include "displayid20.h" #include "edid.h" PUSH_SEGMENTS // DisplayId2 as EDID extension entry point functions static NVT_STATUS parseDisplayId20EDIDExtSection(DISPLAYID_2_0_SECTION *section, NVT_EDID_INFO *pEdidInfo); -static NVT_STATUS parseDisplayId20EDIDExtDataBlocks(DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NvU8 remainSectionLength, NvU8 *pCurrentDBLength, NVT_EDID_INFO *pEdidInfo); /** * @@ -70,8 +68,7 @@ getDisplayId20EDIDExtInfo( // The function name if (computeDisplayId20SectionCheckSum(p, sizeof(EDIDV1STRUC)) != 0) { - return NVT_STATUS_ERR; - // ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_CHECK_SUM); + nvt_assert(0 && "displayid2ext invalid checksum"); } extSection = (DISPLAYID_2_0_SECTION *)(p + 1); @@ -105,16 +102,20 @@ parseDisplayId20EDIDExtSection( if (extSection->header.version == DISPLAYID_2_0_VERSION) { - if (((pEdidInfo->total_did2_extensions == 1) && (extSection->header.product_type == 0 || + if (((pEdidInfo->total_did2_extensions == 1) && (extSection->header.product_type == DISPLAYID_2_0_PROD_EXTENSION || extSection->header.product_type > DISPLAYID_2_0_PROD_HMD_AR || - extSection->header.extension_count != 0)) || - (pEdidInfo->total_did2_extensions > 1 && extSection->header.product_type != 0)) + extSection->header.extension_count != DISPLAYID_2_0_PROD_EXTENSION)) || + (pEdidInfo->total_did2_extensions > 1 && extSection->header.product_type != DISPLAYID_2_0_PROD_EXTENSION)) { nvt_assert(0); // product_type value set incorrect in Display Product Primary Use Case field } pEdidInfo->ext_displayid20.version = extSection->header.version; pEdidInfo->ext_displayid20.revision = extSection->header.revision; + if (pEdidInfo->total_did2_extensions == 1) + { + pEdidInfo->ext_displayid20.primary_use_case = extSection->header.product_type; + } pEdidInfo->ext_displayid20.as_edid_extension = NV_TRUE; } else @@ -152,11 +153,10 @@ parseDisplayId20EDIDExtSection( } else { - if (parseDisplayId20EDIDExtDataBlocks( - dbHeader, - extSection->header.section_bytes - datablock_location, - &datablock_length, - pEdidInfo) != NVT_STATUS_SUCCESS) + if (parseDisplayId20EDIDExtDataBlocks((NvU8 *)(extSection->data + datablock_location), + extSection->header.section_bytes - datablock_location, + &datablock_length, + pEdidInfo) != NVT_STATUS_SUCCESS) return NVT_STATUS_ERR; } @@ -169,39 +169,49 @@ parseDisplayId20EDIDExtSection( /* * @brief DisplayId20 as EDID extension block's "Data Block" entry point functions + * For validation, passed the NULL pEdidInfo, and client will check the return value */ CODE_SEGMENT(PAGE_DD_CODE) -static NVT_STATUS +NVT_STATUS parseDisplayId20EDIDExtDataBlocks( - DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, + NvU8 *pDataBlock, NvU8 RemainSectionLength, NvU8 *pCurrentDBLength, NVT_EDID_INFO *pEdidInfo) { + DISPLAYID_2_0_DATA_BLOCK_HEADER * block_header = (DISPLAYID_2_0_DATA_BLOCK_HEADER *) pDataBlock; NVT_STATUS status = NVT_STATUS_SUCCESS; NVT_DISPLAYID_2_0_INFO *pDisplayId20Info = NULL; - + // size sanity checking if ((pDataBlock == NULL || RemainSectionLength <= NVT_DISPLAYID_DATABLOCK_HEADER_LEN) || - (pDataBlock->data_bytes > RemainSectionLength - NVT_DISPLAYID_DATABLOCK_HEADER_LEN)) + (block_header->data_bytes > RemainSectionLength - NVT_DISPLAYID_DATABLOCK_HEADER_LEN)) return NVT_STATUS_ERR; - if (pDataBlock->type < DISPLAYID_2_0_BLOCK_TYPE_PRODUCT_IDENTITY) + if (block_header->type < DISPLAYID_2_0_BLOCK_TYPE_PRODUCT_IDENTITY) { return NVT_STATUS_INVALID_PARAMETER; } - - pDisplayId20Info = &pEdidInfo->ext_displayid20; - *pCurrentDBLength = pDataBlock->data_bytes + NVT_DISPLAYID_DATABLOCK_HEADER_LEN; + if (pEdidInfo != NULL) + { + pDisplayId20Info = &(pEdidInfo->ext_displayid20); + } - status = parseDisplayId20DataBlock(pDataBlock, pDisplayId20Info); + *pCurrentDBLength = block_header->data_bytes + NVT_DISPLAYID_DATABLOCK_HEADER_LEN; + + status = parseDisplayId20DataBlock(block_header, pDisplayId20Info); + + if (pDisplayId20Info == NULL) return status; // TODO : All the data blocks shall sync the data from the datablock in DisplayID2_0 to pEdidInfo if (status == NVT_STATUS_SUCCESS && pDisplayId20Info->as_edid_extension == NV_TRUE) { - switch (pDataBlock->type) + switch (block_header->type) { + case DISPLAYID_2_0_BLOCK_TYPE_PRODUCT_IDENTITY: + pDisplayId20Info->valid_data_blocks.product_id_present = NV_TRUE; + break; case DISPLAYID_2_0_BLOCK_TYPE_INTERFACE_FEATURES: pDisplayId20Info->valid_data_blocks.interface_feature_present = NV_TRUE; @@ -234,15 +244,16 @@ parseDisplayId20EDIDExtDataBlocks( pDisplayId20Info->valid_data_blocks.cta_data_present = NV_TRUE; // copy all the vendor specific data block from DisplayId20 to pEdidInfo - // TODO: mixed CTA extension block and DID2.0 extension block is not handled + // NOTE: mixed CTA extension block and DID2.0 extension block are not handled NVMISC_MEMCPY(&pEdidInfo->hdmiLlcInfo, &pDisplayId20Info->vendor_specific.hdmiLlc, sizeof(NVT_HDMI_LLC_INFO)); NVMISC_MEMCPY(&pEdidInfo->hdmiForumInfo, &pDisplayId20Info->vendor_specific.hfvs, sizeof(NVT_HDMI_FORUM_INFO)); NVMISC_MEMCPY(&pEdidInfo->nvdaVsdbInfo, &pDisplayId20Info->vendor_specific.nvVsdb, sizeof(NVDA_VSDB_PARSED_INFO)); NVMISC_MEMCPY(&pEdidInfo->msftVsdbInfo, &pDisplayId20Info->vendor_specific.msftVsdb, sizeof(MSFT_VSDB_PARSED_INFO)); NVMISC_MEMCPY(&pEdidInfo->hdr_static_metadata_info, &pDisplayId20Info->cta.hdrInfo, sizeof(NVT_HDR_STATIC_METADATA)); NVMISC_MEMCPY(&pEdidInfo->dv_static_metadata_info, &pDisplayId20Info->cta.dvInfo, sizeof(NVT_DV_STATIC_METADATA)); + NVMISC_MEMCPY(&pEdidInfo->hdr10PlusInfo, &pDisplayId20Info->cta.hdr10PlusInfo, sizeof(NVT_HDR10PLUS_INFO)); - // If the CTA861 extension existed already, we need to transfer the revision/basic_caps to cta embedded in DID20. + // If the CTA861 extension existed already, we need to synced the revision/basic_caps to CTA which is embedded in DID20 if (pEdidInfo->ext861.revision >= NVT_CEA861_REV_B) { pDisplayId20Info->cta.cta861_info.revision = pEdidInfo->ext861.revision; @@ -268,7 +279,36 @@ parseDisplayId20EDIDExtDataBlocks( } break; - + case DISPLAYID_2_0_BLOCK_TYPE_STEREO: + pDisplayId20Info->valid_data_blocks.stereo_interface_present = NV_TRUE; + break; + case DISPLAYID_2_0_BLOCK_TYPE_TILED_DISPLAY: + pDisplayId20Info->valid_data_blocks.tiled_display_present = NV_TRUE; + break; + case DISPLAYID_2_0_BLOCK_TYPE_CONTAINER_ID: + pDisplayId20Info->valid_data_blocks.container_id_present = NV_TRUE; + break; + case DISPLAYID_2_0_BLOCK_TYPE_TIMING_7: + pDisplayId20Info->valid_data_blocks.type7Timing_present = NV_TRUE; + break; + case DISPLAYID_2_0_BLOCK_TYPE_TIMING_8: + pDisplayId20Info->valid_data_blocks.type8Timing_present = NV_TRUE; + break; + case DISPLAYID_2_0_BLOCK_TYPE_TIMING_9: + pDisplayId20Info->valid_data_blocks.type9Timing_present = NV_TRUE; + break; + case DISPLAYID_2_0_BLOCK_TYPE_TIMING_10: + pDisplayId20Info->valid_data_blocks.type10Timing_present = NV_TRUE; + break; + case DISPLAYID_2_0_BLOCK_TYPE_RANGE_LIMITS: + pDisplayId20Info->valid_data_blocks.dynamic_range_limit_present = NV_TRUE; + break; + case DISPLAYID_2_0_BLOCK_TYPE_ADAPTIVE_SYNC: + pDisplayId20Info->valid_data_blocks.adaptive_sync_present = NV_TRUE; + break; + case DISPLAYID_2_0_BLOCK_TYPE_VENDOR_SPEC: + pDisplayId20Info->valid_data_blocks.vendor_specific_present = NV_TRUE; + break; default: break; } diff --git a/src/common/modeset/timing/nvtiming.h b/src/common/modeset/timing/nvtiming.h index cf96ebdde..e75f95971 100644 --- a/src/common/modeset/timing/nvtiming.h +++ b/src/common/modeset/timing/nvtiming.h @@ -356,7 +356,7 @@ typedef enum NVT_TV_FORMAT #define NVT_STATUS_NTSC_TV NVT_DEF_TIMING_STATUS(NVT_TYPE_NTSC_TV, 0) // TVN #define NVT_STATUS_PAL_TV NVT_DEF_TIMING_STATUS(NVT_TYPE_PAL_TV, 0) // TVP #define NVT_STATUS_CVT NVT_DEF_TIMING_STATUS(NVT_TYPE_CVT, 0) // CVT timing with regular blanking -#define NVT_STATUS_CVT_RB NVT_DEF_TIMING_STATUS(NVT_TYPE_CVT_RB, 0) // CVT_RB timing +#define NVT_STATUS_CVT_RB NVT_DEF_TIMING_STATUS(NVT_TYPE_CVT_RB, 0) // CVT_RB timing V1 #define NVT_STATUS_CVT_RB_2 NVT_DEF_TIMING_STATUS(NVT_TYPE_CVT_RB_2, 0) // CVT_RB timing V2 #define NVT_STATUS_CVT_RB_3 NVT_DEF_TIMING_STATUS(NVT_TYPE_CVT_RB_3, 0) // CVT_RB timing V3 #define NVT_STATUS_CUST NVT_DEF_TIMING_STATUS(NVT_TYPE_CUST, 0) // Customized timing @@ -814,6 +814,7 @@ typedef struct VSDB_DATA // vendor specific video data //******************************* #define NVT_CEA861_DV_IEEE_ID 0x00D046 +#define NVT_CEA861_HDR10PLUS_IEEE_ID 0x90848B #define NVT_CEA861_VSVDB_PAYLOAD_MAX_LENGTH 25 // max allowed vendor specific video data block payload (in byte) #define NVT_CEA861_VSVDB_VERSION_MASK 0xE0 // vsdb version mask #define NVT_CEA861_VSVDB_VERSION_MASK_SHIFT 5 // vsdb version shift mask @@ -941,13 +942,13 @@ typedef struct tagNVT_DV_STATIC_METADATA_TYPE2 NvU8 VSVDB_version : 3; // second byte - NvU8 backlt_min_luma : 2; + NvU8 reserved : 2; NvU8 supports_global_dimming : 1; NvU8 target_min_luminance : 5; // third byte NvU8 interface_supported_by_sink : 2; - NvU8 reserved : 1; + NvU8 parity : 1; NvU8 target_max_luminance : 5; //fourth byte @@ -967,6 +968,14 @@ typedef struct tagNVT_DV_STATIC_METADATA_TYPE2 NvU8 unique_Ry : 5; } NVT_DV_STATIC_METADATA_TYPE2; + +typedef struct tagNVT_HDR10PLUS_INFO +{ + // first byte + NvU8 application_version : 2; + NvU8 full_frame_peak_luminance_index : 2; + NvU8 peak_luminance_index : 4; +} NVT_HDR10PLUS_INFO; #pragma pack() //*************************** @@ -1111,6 +1120,7 @@ typedef struct tagNVT_VALID_EXTENDED_BLOCKS NvU32 y420cmdb : 1; NvU32 hdr_static_metadata : 1; NvU32 dv_static_metadata : 1; + NvU32 hdr10Plus : 1; NvU32 SCDB : 1; NvU32 HF_EEODB : 1; } NVT_VALID_EXTENDED_BLOCKS; @@ -1799,7 +1809,7 @@ typedef struct tagNVT_EDID_DD_DUMMY_DESCRIPTOR // // // -//*** (Tag = 0x0F) ***/ +//*** (Tag = 0x00 to 0x0F) ***/ // Manufacturer Special Data typedef struct tagNVT_EDID_DD_MANUF_DATA { @@ -2169,6 +2179,7 @@ typedef struct tagNVT_DV_STATIC_METADATA NvU32 backlt_min_luma : 2; NvU32 interface_supported_by_sink : 2; NvU32 supports_10b_12b_444 : 2; + NvU32 parity : 1; }NVT_DV_STATIC_METADATA; //*********************************** @@ -2182,7 +2193,6 @@ typedef struct tagNVT_DV_STATIC_METADATA #define NVT_DISPLAY_2_0_CAP_YCbCr_422 0x10 // DTV monitor supports YCbCr4:2:2 // vendor specific - #define NVT_VESA_VENDOR_SPECIFIC_IEEE_ID 0x3A0292 #define NVT_VESA_VENDOR_SPECIFIC_LENGTH 7 @@ -2195,6 +2205,9 @@ typedef struct tagNVT_DV_STATIC_METADATA #define NVT_VESA_ORG_VSDB_PASS_THROUGH_INTEGER_MASK 0x3F #define NVT_VESA_ORG_VSDB_PASS_THROUGH_FRACTIOINAL_MASK 0x0F +// adaptive-sync +#define NVT_ADAPTIVE_SYNC_DESCRIPTOR_MAX_COUNT 0x04 + typedef enum _tagNVT_DISPLAYID_PRODUCT_PRIMARY_USE_CASE { PRODUCT_PRIMARY_USE_TEST_EQUIPMENT = 1, @@ -2383,6 +2396,28 @@ typedef struct _tagNVT_DISPLAYID_DISPLAY_PARAMETERS NvBool audio_speakers_integrated; } NVT_DISPLAYID_DISPLAY_PARAMETERS; +typedef struct _tagNVT_DISPLAYID_ADAPTIVE_SYNC +{ + union + { + NvU8 operation_range_info; + struct + { + NvU8 adaptive_sync_range : 1; + NvU8 duration_inc_flicker_perf : 1; + NvU8 modes : 2; + NvU8 seamless_not_support : 1; + NvU8 duration_dec_flicker_perf : 1; + NvU8 reserved : 2; + } information; + } u; + + NvU8 max_duration_inc; + NvU8 min_rr; + NvU16 max_rr; + NvU8 max_duration_dec; +} NVT_DISPLAYID_ADAPTIVE_SYNC; + typedef struct _tagVESA_VSDB_PARSED_INFO { struct @@ -2411,7 +2446,6 @@ typedef struct _tagVESA_VSDB_PARSED_INFO NvU8 pass_through_fraction_dsc : 4; NvU8 reserved : 4; } pass_through_fractional; - } VESA_VSDB_PARSED_INFO; typedef struct _tagNVT_DISPLAYID_VENDOR_SPECIFIC @@ -2427,7 +2461,8 @@ typedef struct _tagNVT_DISPLAYID_CTA { NVT_EDID_CEA861_INFO cta861_info; NVT_HDR_STATIC_METADATA hdrInfo; - NVT_DV_STATIC_METADATA dvInfo; + NVT_DV_STATIC_METADATA dvInfo; + NVT_HDR10PLUS_INFO hdr10PlusInfo; } NVT_DISPLAYID_CTA; typedef struct _tagNVT_VALID_DATA_BLOCKS @@ -2442,6 +2477,10 @@ typedef struct _tagNVT_VALID_DATA_BLOCKS NvBool stereo_interface_present; NvBool tiled_display_present; NvBool container_id_present; + NvBool type10Timing_present; + NvBool adaptive_sync_present; + NvBool arvr_hmd_present; + NvBool arvr_layer_present; NvBool vendor_specific_present; NvBool cta_data_present; } NVT_VALID_DATA_BLOCKS; @@ -2494,6 +2533,10 @@ typedef struct _tagNVT_DISPLAYID_2_0_INFO // ContainerID Data Block (Mandatory for Multi-function Device) NVT_DISPLAYID_CONTAINERID container_id; + // Adaptive-Sync Data Block (Mandatory for display device supports Adaptive-Sync) + NvU32 total_adaptive_sync_descriptor; + NVT_DISPLAYID_ADAPTIVE_SYNC adaptive_sync_descriptor[NVT_ADAPTIVE_SYNC_DESCRIPTOR_MAX_COUNT]; + // Vendor-specific Data Block (Not Mandatory) NVT_DISPLAYID_VENDOR_SPECIFIC vendor_specific; @@ -2632,6 +2675,9 @@ typedef struct tagNVT_EDID_INFO // DV capability information from the DV Metadata Data Block NVT_DV_STATIC_METADATA dv_static_metadata_info; + // HDR10+ capability information from the HDR10+ LLC VSVDB + NVT_HDR10PLUS_INFO hdr10PlusInfo; + // HDMI LLC info NVT_HDMI_LLC_INFO hdmiLlcInfo; @@ -5182,28 +5228,60 @@ typedef enum typedef enum { - // errors returned as a bitmask by NvTiming_EDIDValidationMask() + // errors returned as a bitmask by NvTiming_EDIDValidationMask() NVT_EDID_VALIDATION_ERR_EXT = 0, NVT_EDID_VALIDATION_ERR_VERSION, NVT_EDID_VALIDATION_ERR_SIZE, NVT_EDID_VALIDATION_ERR_CHECKSUM, NVT_EDID_VALIDATION_ERR_RANGE_LIMIT, NVT_EDID_VALIDATION_ERR_DTD, + NVT_EDID_VALIDATION_ERR_HEADER, NVT_EDID_VALIDATION_ERR_EXT_DTD, + NVT_EDID_VALIDATION_ERR_EXTENSION_TAG, + NVT_EDID_VALIDATION_ERR_EXTENSION_COUNT, + NVT_EDID_VALIDATION_ERR_DESCRIPTOR, + NVT_EDID_VALIDATION_ERR_EXT_CTA_BASIC, + NVT_EDID_VALIDATION_ERR_EXT_CTA_DTD, + NVT_EDID_VALIDATION_ERR_EXT_CTA_TAG, + NVT_EDID_VALIDATION_ERR_EXT_CTA_SVD, + NVT_EDID_VALIDATION_ERR_EXT_CTA_INVALID_DATA_BLOCK, + NVT_EDID_VALIDATION_ERR_EXT_CTA_CHECKSUM, + NVT_EDID_VALIDATION_ERR_EXT_DID_VERSION, + NVT_EDID_VALIDATION_ERR_EXT_DID_EXTCOUNT, + NVT_EDID_VALIDATION_ERR_EXT_DID_CHECKSUM, + NVT_EDID_VALIDATION_ERR_EXT_DID_SEC_SIZE, + NVT_EDID_VALIDATION_ERR_EXT_DID13_TAG, + NVT_EDID_VALIDATION_ERR_EXT_DID13_TYPE1, + NVT_EDID_VALIDATION_ERR_EXT_DID2_TAG, + NVT_EDID_VALIDATION_ERR_EXT_DID2_USE_CASE, + NVT_EDID_VALIDATION_ERR_EXT_DID2_MANDATORY_BLOCKS, + NVT_EDID_VALIDATION_ERR_EXT_DID2_TYPE7, + NVT_EDID_VALIDATION_ERR_EXT_DID2_TYPE10, + NVT_EDID_VALIDATION_ERR_EXT_RANGE_LIMIT, + NVT_EDID_VALIDATION_ERR_EXT_DID2_ADAPTIVE_SYNC, } NVT_EDID_VALIDATION_ERR_STATUS; #define NVT_EDID_VALIDATION_ERR_MASK(x) NVBIT32(x) +//************************************* +// The DisplayID2 validation Mask +//************************************* typedef enum { // errors returned as a bitmask by NvTiming_DisplayID2ValidationMask() - NVT_DID2_VALIDATION_ERR_EXT = 0, - NVT_DID2_VALIDATION_ERR_VERSION, + NVT_DID2_VALIDATION_ERR_VERSION = 0, NVT_DID2_VALIDATION_ERR_SIZE, - NVT_DID2_VALIDATION_ERR_CHECKSUM, - NVT_DID2_VALIDATION_ERR_PRODUCT_ID, + NVT_DID2_VALIDATION_ERR_CHECKSUM, NVT_DID2_VALIDATION_ERR_NO_DATA_BLOCK, + NVT_EDID_VALIDATION_ERR_TAG, NVT_DID2_VALIDATION_ERR_RANGE_LIMIT, NVT_DID2_VALIDATION_ERR_NATIVE_DTD, + NVT_DID2_VALIDATION_ERR_MANDATORY_BLOCKS, + NVT_DID2_VALIDATION_ERR_PRODUCT_IDENTIFY, + NVT_DID2_VALIDATION_ERR_PARAMETER, + NVT_DID2_VALIDATION_ERR_INTERFACE, + NVT_DID2_VALIDATION_ERR_TYPE7, + NVT_DID2_VALIDATION_ERR_TYPE10, + NVT_DID2_VALIDATION_ERR_ADAPTIVE_SYNC, } NVT_DID2_VALIDATION_ERR_STATUS; #define NVT_DID2_VALIDATION_ERR_MASK(x) NVBIT32(x) @@ -5229,9 +5307,9 @@ typedef enum #define NVT_FLAG_DTD1_PREFERRED_TIMING 0x00080000 #define NVT_FLAG_DISPLAYID_DTD_PREFERRED_TIMING 0x00100000 #define NVT_FLAG_CEA_PREFERRED_TIMING 0x00200000 -#define NVT_FLAG_DISPLAYID_7_DSC_PASSTHRU 0x00400000 +#define NVT_FLAG_DISPLAYID_T7_DSC_PASSTHRU 0x00400000 #define NVT_FLAG_DISPLAYID_2_0_TIMING 0x00800000 // this one for the CTA861 embedded in DID20 -#define NVT_FLAG_DISPLAYID_2_0_EXPLICT_YUV420 0x01000000 // DID2 E7 spec. supported yuv420 indicated +#define NVT_FLAG_DISPLAYID_T7_T8_EXPLICT_YUV420 0x01000000 // DID2 E7 spec. supported yuv420 indicated #define NVT_FLAG_INTERLACED_MASK (NVT_FLAG_INTERLACED_TIMING | NVT_FLAG_INTERLACED_TIMING2) @@ -5299,6 +5377,7 @@ NvU32 NvTiming_GetVESADisplayDescriptorVersion(NvU8 *rawData, NvU32 *pVer); // EDID entry parse NVT_STATUS NV_STDCALL NvTiming_ParseEDIDInfo(NvU8 *pEdid, NvU32 length, NVT_EDID_INFO *pEdidInfo); NvU32 NvTiming_EDIDValidationMask(NvU8 *pEdid, NvU32 length, NvBool bIsStrongValidation); +NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length); NVT_STATUS NvTiming_EDIDValidation(NvU8 *pEdid, NvU32 length, NvBool bIsStrongValidation); // DisplayID20 standalone entry parse diff --git a/src/common/modeset/timing/nvtiming_pvt.h b/src/common/modeset/timing/nvtiming_pvt.h index d96846ec6..0e33e08e4 100644 --- a/src/common/modeset/timing/nvtiming_pvt.h +++ b/src/common/modeset/timing/nvtiming_pvt.h @@ -78,8 +78,9 @@ void parseEdidHdmiForumVSDB(VSDB_DATA *pVsdb, NVT_HDMI_FORUM_INFO *pHdmiIn void getEdidHDM1_4bVsdbTiming(NVT_EDID_INFO *pInfo); void parseEdidHDMILLCTiming(NVT_EDID_INFO *pInfo, VSDB_DATA *pVsdb, NvU32 *pSupported, HDMI3DSUPPORTMAP * pM); void parseEdidNvidiaVSDBBlock(VSDB_DATA *pVsdb, NVDA_VSDB_PARSED_INFO *vsdbInfo); -void parseCea861HdrStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN); -void parseCea861DvStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, NVT_DV_STATIC_METADATA *pDvInfo); +void parseCea861HdrStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); +void parseCea861DvStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); +void parseCea861Hdr10PlusDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); NvBool isMatchedCTA861Timing(NVT_EDID_INFO *pInfo, NVT_TIMING *pT); NvU32 isHdmi3DStereoType(NvU8 StereoStructureType); NvU32 getCEA861TimingAspectRatio(NvU32 vic); @@ -91,7 +92,9 @@ void getMonitorDescriptorString(NvU8 *pEdid, NvU8 tag, char *str, int once // DispalyID base / extension related functions NvU32 getDID2Version(NvU8 *pData, NvU32 *pVer); NVT_STATUS getDisplayIdEDIDExtInfo(NvU8* pEdid, NvU32 edidSize, NVT_EDID_INFO* pEdidInfo); +NVT_STATUS parseDisplayIdBlock(NvU8* pBlock, NvU8 max_length, NvU8* pLength, NVT_EDID_INFO* pEdidInfo); NVT_STATUS getDisplayId20EDIDExtInfo(NvU8* pDisplayid, NvU32 edidSize, NVT_EDID_INFO* pEdidInfo); +NVT_STATUS parseDisplayId20EDIDExtDataBlocks(NvU8* pDataBlock, NvU8 remainSectionLength, NvU8* pCurrentDBLength, NVT_EDID_INFO* pEdidInfo); void updateColorFormatForDisplayIdExtnTimings(NVT_EDID_INFO* pInfo, NvU32 timingIdx); void updateColorFormatForDisplayId20ExtnTimings(NVT_EDID_INFO* pInfo, NvU32 timingIdx); NvBool assignNextAvailableDisplayId20Timing(NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo, const NVT_TIMING *pTiming); diff --git a/kernel-open/nvidia/nvlink_inband_drv_header.h b/src/common/nvlink/inband/interface/nvlink_inband_drv_header.h similarity index 52% rename from kernel-open/nvidia/nvlink_inband_drv_header.h rename to src/common/nvlink/inband/interface/nvlink_inband_drv_header.h index 1521c479b..df97ed36d 100644 --- a/kernel-open/nvidia/nvlink_inband_drv_header.h +++ b/src/common/nvlink/inband/interface/nvlink_inband_drv_header.h @@ -1,24 +1,25 @@ -/******************************************************************************* - Copyright (c) 2022 NVidia Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. -*******************************************************************************/ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #ifndef NVLINK_INBAND_DRV_HDR_H #define NVLINK_INBAND_DRV_HDR_H diff --git a/kernel-open/nvidia/nvlink_inband_msg.h b/src/common/nvlink/inband/interface/nvlink_inband_msg.h similarity index 68% rename from kernel-open/nvidia/nvlink_inband_msg.h rename to src/common/nvlink/inband/interface/nvlink_inband_msg.h index 2618cefdb..ab08017fe 100644 --- a/kernel-open/nvidia/nvlink_inband_msg.h +++ b/src/common/nvlink/inband/interface/nvlink_inband_msg.h @@ -1,24 +1,25 @@ -/******************************************************************************* - Copyright (c) 2022 NVidia Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. -*******************************************************************************/ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #ifndef NVLINK_INBAND_MSG_HDR_H #define NVLINK_INBAND_MSG_HDR_H @@ -58,6 +59,7 @@ #define NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_REQ 2 #define NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_RSP 3 #define NVLINK_INBAND_MSG_TYPE_MC_TEAM_RELEASE_REQ 4 +#define NVLINK_INBAND_MSG_TYPE_MAX 5 /* Nvlink Inband message packet header */ typedef struct @@ -76,14 +78,14 @@ typedef struct typedef struct { - NvU32 pciInfo; /* Encoded as Bus:Device:Function.(debug only) */ + NvU64 pciInfo; /* Encoded as Domain(63:32):Bus(15:8):Device(0:7). (debug only) */ NvU8 moduleId; /* GPIO based physical/module ID of the GPU. (debug only) */ - NvUuid uuid; /* UUID of the GPU. (debug only) */ + NvUuid gpuUuid; /* UUID of the GPU. (debug only) */ NvU64 discoveredLinkMask; /* GPU's discovered NVLink mask info. (debug only) */ NvU64 enabledLinkMask; /* GPU's currently enabled NvLink mask info. (debug only) */ NvU32 gpuCapMask; /* GPU capabilities, one of NVLINK_INBAND_GPU_PROBE_CAPS */ - NvU8 reserved[16]; /* For future use. Must be initialized to zero */ + NvU8 reserved[32]; /* For future use. Must be initialized to zero */ } nvlink_inband_gpu_probe_req_t; typedef struct @@ -97,17 +99,16 @@ typedef struct typedef struct { - NvU64 gpuHandle; /* Unique handle assigned by initialization entity for this GPU */ - NvU32 gfId; /* GFID which supports NVLink */ - NvU64 fmCaps; /* Capability of FM e.g. what features FM support. */ - NvU16 nodeId; /* Node ID of the system where this GPU belongs */ - NvU16 fabricPartitionId; /* Partition ID if the GPU belongs to a fabric partition */ - NvU16 clusterId; /* Cluster ID to which this node belongs */ - NvU64 gpaAddress; /* GPA starting address for the GPU */ - NvU64 gpaAddressRange; /* GPU GPA address range */ - NvU64 flaAddress; /* FLA starting address for the GPU */ - NvU64 flaAddressRange; /* GPU FLA address range */ - NvU8 reserved[32]; /* For future use. Must be initialized to zero */ + NvU64 gpuHandle; /* Unique handle assigned by initialization entity for this GPU */ + NvU32 gfId; /* GFID which supports NVLink */ + NvU64 fmCaps; /* Capability of FM e.g. what features FM support. */ + NvUuid clusterUuid; /* Cluster UUID to which this node belongs */ + NvU16 fabricPartitionId; /* Partition ID if the GPU belongs to a fabric partition */ + NvU64 gpaAddress; /* GPA starting address for the GPU */ + NvU64 gpaAddressRange; /* GPU GPA address range */ + NvU64 flaAddress; /* FLA starting address for the GPU */ + NvU64 flaAddressRange; /* GPU FLA address range */ + NvU8 reserved[32]; /* For future use. Must be initialized to zero */ } nvlink_inband_gpu_probe_rsp_t; typedef struct diff --git a/src/common/nvlink/interface/nvlink.h b/src/common/nvlink/interface/nvlink.h index 8dd71eab5..46d74efbe 100644 --- a/src/common/nvlink/interface/nvlink.h +++ b/src/common/nvlink/interface/nvlink.h @@ -108,7 +108,7 @@ struct nvlink_device // Device type and status NvU64 type; NvBool initialized; - + // Training type: ALI or Non-ALI NvBool enableALI; @@ -328,7 +328,7 @@ typedef struct nvlink_inband_data nvlink_inband_data; #define NVLINK_LINKSTATE_CONTAIN 0x19 // TL is in contain mode #define NVLINK_LINKSTATE_INITTL 0x1A // INITTL #define NVLINK_LINKSTATE_INITPHASE5 0x1B // INITPHASE5 -#define NVLINK_LINKSTATE_ALI 0x1C // ALI +#define NVLINK_LINKSTATE_ALI 0x1C // ALI #define NVLINK_LINKSTATE_ACTIVE_PENDING 0x1D // Intermediate state for a link going to active #define NVLINK_LINKSTATE_INVALID 0xFF // Invalid state diff --git a/src/common/nvlink/interface/nvlink_lib_ctrl.h b/src/common/nvlink/interface/nvlink_lib_ctrl.h index d1e1bb04b..1a481c69d 100644 --- a/src/common/nvlink/interface/nvlink_lib_ctrl.h +++ b/src/common/nvlink/interface/nvlink_lib_ctrl.h @@ -89,7 +89,7 @@ typedef struct typedef struct { NvU16 nodeId; - NvU32 linkIndex; + NvU16 linkIndex; nvlink_pci_dev_info pciInfo; } nvlink_endpoint; @@ -117,7 +117,7 @@ typedef struct typedef struct { NvU16 nodeId; - NvU32 linkIndex; + NvU16 linkIndex; nvlink_pci_dev_info pciInfo; NvU8 devUuid[NVLINK_UUID_LEN]; NvU32 devType; @@ -189,9 +189,9 @@ typedef enum /* link and sublink state of an nvlink endpoint */ typedef struct { - NvU32 linkMode; - NvU32 txSubLinkMode; - NvU32 rxSubLinkMode; + NvU8 linkMode; + NvU8 txSubLinkMode; + NvU8 rxSubLinkMode; } nvlink_link_state; /* @@ -354,7 +354,7 @@ typedef struct */ typedef struct { - NvU32 linkIndex; + NvU16 linkIndex; NvBool initStatus; } nvlink_link_init_status; @@ -503,7 +503,7 @@ typedef struct */ typedef struct { - NvU32 linkIndex; + NvU16 linkIndex; NV_DECLARE_ALIGNED(NvU64 tokenValue, 8); } nvlink_token_info; @@ -1111,6 +1111,11 @@ typedef struct NvU32 endStatesCount; } nvlink_get_device_link_states; +/* + * Note: Verify that new parameter structs for IOCTLs satisfy + * sizing restrictions for all OSs they could be used in. + */ + #define CTRL_NVLINK_CHECK_VERSION 0x01 #define CTRL_NVLINK_SET_NODE_ID 0x02 #define CTRL_NVLINK_SET_TX_COMMON_MODE 0x03 diff --git a/src/common/nvlink/kernel/nvlink/core/nvlink_conn_mgmt.c b/src/common/nvlink/kernel/nvlink/core/nvlink_conn_mgmt.c index 1698296d4..53290ec59 100644 --- a/src/common/nvlink/kernel/nvlink/core/nvlink_conn_mgmt.c +++ b/src/common/nvlink/kernel/nvlink/core/nvlink_conn_mgmt.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2019-2020 NVidia Corporation + Copyright (c) 2019-2022 NVidia Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -41,6 +41,11 @@ nvlink_core_get_intranode_conn { nvlink_intranode_conn *tmpConn = NULL; + if ((endpoint == NULL) || (conn == NULL)) + { + return; + } + FOR_EACH_CONNECTION(tmpConn, nvlinkLibCtx.nv_intraconn_head, node) { if (tmpConn->end0 == endpoint || tmpConn->end1 == endpoint) @@ -66,6 +71,11 @@ nvlink_core_get_internode_conn { nvlink_internode_conn *tmpConn = NULL; + if ((localLink == NULL) || (conn == NULL)) + { + return; + } + FOR_EACH_CONNECTION(tmpConn, nvlinkLibCtx.nv_interconn_head, node) { if (tmpConn->local_end == localLink) @@ -93,6 +103,11 @@ nvlink_core_add_intranode_conn { nvlink_intranode_conn *conn = NULL; + if ((end0 == NULL) || (end1 == NULL)) + { + return NVL_BAD_ARGS; + } + // don't do anything if we have an intranode connecction nvlink_core_get_intranode_conn(end0, &conn); @@ -163,6 +178,11 @@ nvlink_core_add_internode_conn { nvlink_internode_conn *conn = NULL; + if ((localLink == NULL) || (remoteEndPoint == NULL)) + { + return NVL_BAD_ARGS; + } + // Don't do anything if we have an internode connecction for local link nvlink_core_get_internode_conn(localLink, &conn); if (conn != NULL) @@ -208,6 +228,9 @@ nvlink_core_remove_intranode_conn nvlink_intranode_conn *conn ) { + if (conn == NULL) + return; + // Remove the connection from the list of connections nvListDel(&conn->node); @@ -245,6 +268,9 @@ nvlink_core_remove_internode_conn { nvlink_internode_conn *conn = NULL; + if (localLink == NULL) + return; + nvlink_core_get_internode_conn(localLink, &conn); if (conn != NULL) @@ -269,6 +295,11 @@ nvlink_core_check_intranode_conn_state NvU64 linkMode ) { + if (conn == NULL) + { + return NVL_BAD_ARGS; + } + switch (linkMode) { case NVLINK_LINKSTATE_OFF: @@ -485,6 +516,11 @@ nvlink_core_copy_intranode_conn_info nvlink_conn_info *conn_info ) { + if ((remote_end == NULL) || (conn_info == NULL)) + { + return; + } + // copy the remote device pci information conn_info->domain = remote_end->dev->pciInfo.domain; conn_info->bus = remote_end->dev->pciInfo.bus; @@ -520,6 +556,11 @@ nvlink_core_copy_internode_conn_info nvlink_conn_info *conn_info ) { + if ((remote_end == NULL) || (conn_info == NULL)) + { + return; + } + // copy the remote device pci information conn_info->domain = remote_end->pciInfo.domain; conn_info->bus = remote_end->pciInfo.bus; diff --git a/src/common/nvlink/kernel/nvlink/core/nvlink_discovery.c b/src/common/nvlink/kernel/nvlink/core/nvlink_discovery.c index 2cd2c2a64..00c8d2fb5 100644 --- a/src/common/nvlink/kernel/nvlink/core/nvlink_discovery.c +++ b/src/common/nvlink/kernel/nvlink/core/nvlink_discovery.c @@ -54,6 +54,12 @@ nvlink_core_discover_and_get_remote_end nvlink_device *dev = NULL; nvlink_link *link = NULL; NvU32 linkCount = 0; + + if ((end == NULL) || (remote_end == NULL)) + { + return; + } + nvlink_link **pLinks = (nvlink_link **)nvlink_malloc( sizeof(nvlink_link *) * NVLINK_MAX_SYSTEM_LINK_NUM); if (pLinks == NULL) @@ -224,12 +230,11 @@ _nvlink_core_discover_topology(void) isTokenFound = NV_TRUE; // - // If a token is found mark bInitnegotiateConfigGood as - // True since we can only finish off discovery if - // INITNEGOTIATE has finished in order to get topology info from - // MINION + // If R4 tokens were used for NVLink3.0+, then mark initnegotiate + // passed, since ALT training won't get kicked off without it. // - if ((end0->version >= NVLINK_DEVICE_VERSION_30)) + if ((end0->version >= NVLINK_DEVICE_VERSION_30) && + ((end0->localSid == 0) || (end0->remoteSid == 0))) { end0->bInitnegotiateConfigGood = NV_TRUE; end1->bInitnegotiateConfigGood = NV_TRUE; diff --git a/src/common/nvlink/kernel/nvlink/core/nvlink_initialize.c b/src/common/nvlink/kernel/nvlink/core/nvlink_initialize.c index f2d50b4eb..b203a1085 100644 --- a/src/common/nvlink/kernel/nvlink/core/nvlink_initialize.c +++ b/src/common/nvlink/kernel/nvlink/core/nvlink_initialize.c @@ -46,7 +46,11 @@ nvlink_core_init_links_from_off_to_swcfg NvU32 i; // Sanity check the links array - nvlink_assert(pLinks != NULL); + if (pLinks == NULL) + { + nvlink_assert(0); + return; + } // Return early if there are no links to initialize if (numLinks == 0) @@ -65,6 +69,9 @@ nvlink_core_init_links_from_off_to_swcfg { for (i = 0; i < numLinks; i++) { + if (pLinks[i] == NULL) + continue; + status = pLinks[i]->link_handlers->get_dl_link_mode(pLinks[i], &linkMode); if ((status != NVL_SUCCESS) || (linkMode == NVLINK_LINKSTATE_FAIL) || (linkMode == NVLINK_LINKSTATE_FAULT)) @@ -84,6 +91,9 @@ nvlink_core_init_links_from_off_to_swcfg { for (i = 0; i < numLinks; i++) { + if (pLinks[i] == NULL) + continue; + // If receiver detect has passed for the link, move to next link if (pLinks[i]->bRxDetected) continue; @@ -107,6 +117,9 @@ nvlink_core_init_links_from_off_to_swcfg { for (i = 0; i < numLinks; i++) { + if (pLinks[i] == NULL) + continue; + // In NVLink3.0 and 3.1, RXDET must be called serially - done above (Bug 2546220) if (!((pLinks[i]->version == NVLINK_DEVICE_VERSION_30) || (pLinks[i]->version == NVLINK_DEVICE_VERSION_31))) @@ -143,6 +156,9 @@ nvlink_core_init_links_from_off_to_swcfg { for (i = 0; i < numLinks; i++) { + if (pLinks[i] == NULL) + continue; + // If receiver detect failed for the link, move to next link if (!pLinks[i]->bRxDetected || pLinks[i]->bTxCommonModeFail) continue; @@ -172,6 +188,9 @@ nvlink_core_init_links_from_off_to_swcfg { for (i = 0; i < numLinks; i++) { + if (pLinks[i] == NULL) + continue; + // If receiver detect failed for the link, move to next link if (!pLinks[i]->bRxDetected || pLinks[i]->bTxCommonModeFail) continue; @@ -190,6 +209,9 @@ nvlink_core_init_links_from_off_to_swcfg // Put the links in SAFE mode for (i = 0; i < numLinks; i++) { + if (pLinks[i] == NULL) + continue; + // If receiver detect failed for the link, move to next link if (!pLinks[i]->bRxDetected || pLinks[i]->bTxCommonModeFail) continue; @@ -243,6 +265,9 @@ nvlink_core_init_links_from_off_to_swcfg // Poll for links to enter SAFE mode for (i = 0; i < numLinks; i++) { + if (pLinks[i] == NULL) + continue; + status = nvlink_core_wait_for_link_init(pLinks[i]); if (status == NVL_SUCCESS) { @@ -275,7 +300,11 @@ nvlink_core_init_links_from_off_to_swcfg_non_ALI NvU32 i; // Sanity check the links array - nvlink_assert(pLinks != NULL); + if (pLinks == NULL) + { + nvlink_assert(0); + return; + } // Return early if there are no links to initialize if (numLinks == 0) @@ -294,6 +323,9 @@ nvlink_core_init_links_from_off_to_swcfg_non_ALI { for (i = 0; i < numLinks; i++) { + if (pLinks[i] == NULL) + continue; + status = pLinks[i]->link_handlers->get_dl_link_mode(pLinks[i], &linkMode); if ((status != NVL_SUCCESS) || (linkMode == NVLINK_LINKSTATE_FAIL) || (linkMode == NVLINK_LINKSTATE_FAULT)) @@ -313,6 +345,9 @@ nvlink_core_init_links_from_off_to_swcfg_non_ALI { for (i = 0; i < numLinks; i++) { + if (pLinks[i] == NULL) + continue; + // In NVLink3.0 and 3.1, RXDET must be called serially - done above (Bug 2546220) if (!((pLinks[i]->version == NVLINK_DEVICE_VERSION_30) || (pLinks[i]->version == NVLINK_DEVICE_VERSION_31))) @@ -348,6 +383,9 @@ nvlink_core_init_links_from_off_to_swcfg_non_ALI { for (i = 0; i < numLinks; i++) { + if (pLinks[i] == NULL) + continue; + // If receiver detect failed for the link, move to next link if (!pLinks[i]->bRxDetected || pLinks[i]->bTxCommonModeFail) continue; @@ -371,6 +409,9 @@ nvlink_core_init_links_from_off_to_swcfg_non_ALI { for (i = 0; i < numLinks; i++) { + if (pLinks[i] == NULL) + continue; + // If receiver detect failed for the link, move to next link if (!pLinks[i]->bRxDetected || pLinks[i]->bTxCommonModeFail || pLinks[i]->bInitphase5Fails) continue; @@ -389,6 +430,9 @@ nvlink_core_init_links_from_off_to_swcfg_non_ALI // Step 5: Put the links in SAFE mode for (i = 0; i < numLinks; i++) { + if (pLinks[i] == NULL) + continue; + // If receiver detect failed for the link, move to next link if (!pLinks[i]->bRxDetected || pLinks[i]->bTxCommonModeFail || pLinks[i]->bInitphase5Fails) continue; @@ -442,6 +486,9 @@ nvlink_core_init_links_from_off_to_swcfg_non_ALI // Poll for links to enter SAFE mode for (i = 0; i < numLinks; i++) { + if (pLinks[i] == NULL) + continue; + status = nvlink_core_wait_for_link_init(pLinks[i]); if (status == NVL_SUCCESS) { @@ -473,7 +520,11 @@ nvlink_core_initphase5 NvU32 i; // Sanity check the links array - nvlink_assert(links != NULL); + if (links == NULL) + { + nvlink_assert(0); + return NVL_BAD_ARGS; + } // Return early if link array is empty if (numLinks == 0) @@ -489,6 +540,9 @@ nvlink_core_initphase5 NvlStatus status = NVL_SUCCESS; NvU64 dlLinkMode = 0; + if (links[i] == NULL) + continue; + // INITPHASE5 is supported only for NVLINK version >= 4.0 if (links[i]->version < NVLINK_DEVICE_VERSION_40) continue; @@ -562,7 +616,11 @@ nvlink_core_initphase1 NvU32 i; // Sanity check the links array - nvlink_assert(links != NULL); + if (links == NULL) + { + nvlink_assert(0); + return NVL_BAD_ARGS; + } // Return early if link array is empty if (numLinks == 0) @@ -584,6 +642,9 @@ nvlink_core_initphase1 NvU32 rxSubMode = 0; NvBool bPhyUnlocked = NV_FALSE; + if (links[i] == NULL) + continue; + // INITPHASE1 is supported only for NVLINK version >= 3.0 if (links[i]->version < NVLINK_DEVICE_VERSION_30) continue; @@ -690,7 +751,11 @@ nvlink_core_rx_init_term NvU32 i; // Sanity check the links array - nvlink_assert(links != NULL); + if (links == NULL) + { + nvlink_assert(0); + return NVL_BAD_ARGS; + } // Return early if link array is empty if (numLinks == 0) @@ -705,6 +770,9 @@ nvlink_core_rx_init_term { NvU64 linkMode = NVLINK_LINKSTATE_OFF; + if (links[i] == NULL) + continue; + if (links[i]->version < NVLINK_DEVICE_VERSION_22) continue; @@ -797,7 +865,11 @@ nvlink_core_set_rx_detect NvU32 i; // Sanity check the links array - nvlink_assert(links != NULL); + if (links == NULL) + { + nvlink_assert(0); + return NVL_BAD_ARGS; + } // Return early if link array is empty if (numLinks == 0) @@ -813,6 +885,9 @@ nvlink_core_set_rx_detect NvlStatus status = NVL_SUCCESS; NvU64 linkMode = NVLINK_LINKSTATE_OFF; + if (links[i] == NULL) + continue; + if (links[i]->version < NVLINK_DEVICE_VERSION_22) continue; @@ -933,7 +1008,11 @@ nvlink_core_get_rx_detect NvU32 i; // Sanity check the links array - nvlink_assert(links != NULL); + if (links == NULL) + { + nvlink_assert(0); + return NVL_BAD_ARGS; + } // Return early if link array is empty if (numLinks == 0) @@ -948,6 +1027,9 @@ nvlink_core_get_rx_detect { NvU64 linkMode = NVLINK_LINKSTATE_OFF; + if (links[i] == NULL) + continue; + // If receiver detect has passed for the link, move to next link if (links[i]->bRxDetected) continue; @@ -1048,7 +1130,11 @@ nvlink_core_enable_common_mode NvU32 i; // Sanity check the links array - nvlink_assert(links != NULL); + if (links == NULL) + { + nvlink_assert(0); + return NVL_BAD_ARGS; + } // Return early if link array is empty if (numLinks == 0) @@ -1063,6 +1149,9 @@ nvlink_core_enable_common_mode { NvU64 linkMode = NVLINK_LINKSTATE_OFF; + if (links[i] == NULL) + continue; + if (!links[i]->bRxDetected) { // link did not pass RXDET, don't do anything @@ -1157,7 +1246,11 @@ nvlink_core_calibrate_links NvU32 i; // Sanity check the links array - nvlink_assert(links != NULL); + if (links == NULL) + { + nvlink_assert(0); + return NVL_BAD_ARGS; + } // Return early if link array is empty if (numLinks == 0) @@ -1173,6 +1266,9 @@ nvlink_core_calibrate_links NvlStatus status = NVL_SUCCESS; NvU64 linkMode = NVLINK_LINKSTATE_OFF; + if (links[i] == NULL) + continue; + // If receiver detect failed for the link, move to next link if (!links[i]->bRxDetected || links[i]->bTxCommonModeFail) continue; @@ -1260,7 +1356,11 @@ nvlink_core_disable_common_mode NvU32 i; // Sanity check the links array - nvlink_assert(links != NULL); + if (links == NULL) + { + nvlink_assert(0); + return NVL_BAD_ARGS; + } // Return early if link array is empty if (numLinks == 0) @@ -1276,6 +1376,9 @@ nvlink_core_disable_common_mode NvlStatus status = NVL_SUCCESS; NvU64 linkMode = NVLINK_LINKSTATE_OFF; + if (links[i] == NULL) + continue; + if (!links[i]->bRxDetected || links[i]->bTxCommonModeFail) { // link did not pass RXDET or failed in common mode, don't do anything @@ -1368,7 +1471,11 @@ nvlink_core_enable_data NvU32 i; // Sanity check the links array - nvlink_assert(links != NULL); + if (links == NULL) + { + nvlink_assert(0); + return NVL_BAD_ARGS; + } // Return early if link array is empty if (numLinks == 0) @@ -1384,6 +1491,9 @@ nvlink_core_enable_data NvlStatus status = NVL_SUCCESS; NvU64 linkMode = NVLINK_LINKSTATE_OFF; + if (links[i] == NULL) + continue; + // If receiver detect failed for the link, move to next link if (!links[i]->bRxDetected || links[i]->bTxCommonModeFail) continue; @@ -1473,7 +1583,11 @@ nvlink_core_initnegotiate NvU32 i; // Sanity check the links array - nvlink_assert(links != NULL); + if (links == NULL) + { + nvlink_assert(0); + return NVL_BAD_ARGS; + } // Return early if link array is empty if (numLinks == 0) @@ -1489,6 +1603,9 @@ nvlink_core_initnegotiate NvlStatus status = NVL_SUCCESS; NvU64 linkMode = NVLINK_LINKSTATE_OFF; + if (links[i] == NULL) + continue; + // If receiver detect failed for the link, move to next link if (!links[i]->bRxDetected || links[i]->bTxCommonModeFail || links[i]->bSafeTransitionFail || links[i]->bInitphase5Fails) @@ -1543,6 +1660,9 @@ nvlink_core_initnegotiate NvlStatus status = NVL_SUCCESS; NvU64 linkMode = NVLINK_LINKSTATE_OFF; + if (links[i] == NULL) + continue; + // If receiver detect failed for the link, move to next link if (!links[i]->bRxDetected || links[i]->bTxCommonModeFail || links[i]->bSafeTransitionFail) @@ -1606,6 +1726,12 @@ nvlink_core_wait_for_link_init NvlStatus status = NVL_SUCCESS; NvU64 linkMode = NVLINK_LINKSTATE_OFF; + if (link == NULL) + { + nvlink_assert(0); + return NVL_BAD_ARGS; + } + // // Check for SW fail flags to exit early // diff --git a/src/common/nvlink/kernel/nvlink/core/nvlink_ioctl.c b/src/common/nvlink/kernel/nvlink/core/nvlink_ioctl.c index cfbc5707f..611a475ac 100644 --- a/src/common/nvlink/kernel/nvlink/core/nvlink_ioctl.c +++ b/src/common/nvlink/kernel/nvlink/core/nvlink_ioctl.c @@ -298,6 +298,11 @@ nvlink_core_get_endpoint_state NvU64 dlState = NVLINK_LINKSTATE_INVALID; NvU64 tlState = NVLINK_LINKSTATE_INVALID; + if ((link == NULL) || (linkState == NULL)) + { + return; + } + // // This is a best case effort to return the current state of the link // to user as part of the ioctl call. Typically, this call should succeed @@ -343,6 +348,11 @@ nvlink_core_get_device_by_devinfo { nvlink_device *tmpDev = NULL; + if ((devInfo == NULL) || (devInfo == NULL)) + { + return; + } + FOR_EACH_DEVICE_REGISTERED(tmpDev, nvlinkLibCtx.nv_devicelist_head, node) { if ( (tmpDev->nodeId == devInfo->nodeId) && @@ -376,6 +386,11 @@ nvlink_core_get_link_by_endpoint nvlink_device *tmpDev = NULL; nvlink_link *tmpLink = NULL; + if ((endPoint == NULL) || (link == NULL)) + { + return; + } + FOR_EACH_DEVICE_REGISTERED(tmpDev, nvlinkLibCtx.nv_devicelist_head, node) { if ((tmpDev->nodeId == endPoint->nodeId) && @@ -412,6 +427,11 @@ nvlink_core_copy_endpoint_info nvlink_endpoint *endPointInfo ) { + if ((connLink == NULL) || (endPointInfo == NULL)) + { + return; + } + nvlink_device *dev = connLink->dev; endPointInfo->pciInfo.domain = dev->pciInfo.domain; @@ -435,6 +455,11 @@ nvlink_core_copy_device_info nvlink_detailed_dev_info *devInfo ) { + if ((tmpDev == NULL) || (devInfo == NULL)) + { + return; + } + devInfo->pciInfo.domain = tmpDev->pciInfo.domain; devInfo->pciInfo.bus = tmpDev->pciInfo.bus; devInfo->pciInfo.device = tmpDev->pciInfo.device; @@ -478,13 +503,20 @@ nvlink_core_link_init_async NvU32 i; // Sanity check the links array for non-zero links - nvlink_assert((links != NULL) && (numLinks > 0)); + if ((links == NULL) || (numLinks == 0)) + { + nvlink_assert(0); + return NVL_BAD_ARGS; + } for (i = 0; i < numLinks; i++) { NvlStatus status = NVL_SUCCESS; NvU64 linkMode = NVLINK_LINKSTATE_OFF; + if (links[i] == NULL) + continue; + if (!links[i]->bRxDetected || links[i]->bTxCommonModeFail) { // link did not pass RXDET or failed in common mode, don't do anything @@ -540,6 +572,9 @@ nvlink_core_get_link_discovery_token { NvU64 token = 0; + if (link == NULL) + return token; + // // generate a unique token value for discovering connections. // link->token is the memory address of the allocated link object, @@ -570,6 +605,11 @@ nvlink_core_write_link_discovery_token NvlStatus status = NVL_SUCCESS; NvU64 linkMode = NVLINK_LINKSTATE_OFF; + if (link == NULL) + { + return NVL_BAD_ARGS; + } + // Packet injection can only happen if link is in SWCFG/ACTIVE status = link->link_handlers->get_dl_link_mode(link, &linkMode); if (status != NVL_SUCCESS) @@ -613,6 +653,11 @@ nvlink_core_read_link_discovery_token NvlStatus status = NVL_SUCCESS; NvU64 linkMode = NVLINK_LINKSTATE_OFF; + if (link == NULL) + { + return 0; + } + status = link->link_handlers->get_dl_link_mode(link, &linkMode); if (status != NVL_SUCCESS) { @@ -654,6 +699,11 @@ nvlink_core_correlate_conn_by_token nvlink_link *dstLink = NULL; NvU64 readToken = 0; + if (srcLink == NULL) + { + return; + } + FOR_EACH_DEVICE_REGISTERED(dev, nvlinkLibCtx.nv_devicelist_head, node) { FOR_EACH_LINK_REGISTERED(dstLink, dev, node) diff --git a/src/common/nvlink/kernel/nvlink/core/nvlink_link_mgmt.c b/src/common/nvlink/kernel/nvlink/core/nvlink_link_mgmt.c index 3678738fc..a76989085 100644 --- a/src/common/nvlink/kernel/nvlink/core/nvlink_link_mgmt.c +++ b/src/common/nvlink/kernel/nvlink/core/nvlink_link_mgmt.c @@ -45,6 +45,11 @@ nvlink_core_check_link_state NvU64 crntTlLinkMode = NVLINK_LINKSTATE_OFF; NvlStatus status = NVL_SUCCESS; + if (link == NULL) + { + return NV_FALSE; + } + switch (linkState) { case NVLINK_LINKSTATE_OFF: @@ -129,6 +134,11 @@ nvlink_core_check_tx_sublink_state NvU64 crntTxSublinkMode = NVLINK_SUBLINK_STATE_TX_OFF; NvU32 crntTxSublinkSubMode = NVLINK_SUBLINK_SUBSTATE_TX_STABLE; + if (link == NULL) + { + return NV_FALSE; + } + status = link->link_handlers->get_tx_mode(link, &crntTxSublinkMode, &crntTxSublinkSubMode); @@ -194,6 +204,11 @@ nvlink_core_check_rx_sublink_state NvU64 crntRxSublinkMode = NVLINK_SUBLINK_STATE_RX_OFF; NvU32 crntRxSublinkSubMode = NVLINK_SUBLINK_SUBSTATE_RX_STABLE; + if (link == NULL) + { + return NV_FALSE; + } + status = link->link_handlers->get_rx_mode(link, &crntRxSublinkMode, &crntRxSublinkSubMode); @@ -258,6 +273,11 @@ nvlink_core_poll_link_state { NvU64 currentLinkState = ~0; + if (link == NULL) + { + return NVL_BAD_ARGS; + } + link->link_handlers->get_dl_link_mode(link, ¤tLinkState); while (currentLinkState != linkState) @@ -316,6 +336,11 @@ nvlink_core_poll_sublink_state { NvlStatus status = NVL_SUCCESS; + if ((localTxSubLink == NULL) || (remoteRxSubLink == NULL)) + { + return NVL_BAD_ARGS; + } + // check for tx sublink if a valid link is specified if (localTxSubLink) { @@ -369,6 +394,11 @@ nvlink_core_poll_tx_sublink_state NvU64 currentTxSublinkState = ~0; NvU32 currentTxSublinkSubState = ~0; + if (link == NULL) + { + return NVL_BAD_ARGS; + } + link->link_handlers->get_tx_mode(link, ¤tTxSublinkState, ¤tTxSublinkSubState); @@ -427,6 +457,11 @@ nvlink_core_poll_rx_sublink_state NvU64 currentRxSublinkState = ~0; NvU32 currentRxSublinkSubState = ~0; + if (link == NULL) + { + return NVL_BAD_ARGS; + } + link->link_handlers->get_rx_mode(link, ¤tRxSublinkState, ¤tRxSublinkSubState); diff --git a/src/common/nvlink/kernel/nvlink/core/nvlink_logger.c b/src/common/nvlink/kernel/nvlink/core/nvlink_logger.c index 52cb95b65..e854108b3 100644 --- a/src/common/nvlink/kernel/nvlink/core/nvlink_logger.c +++ b/src/common/nvlink/kernel/nvlink/core/nvlink_logger.c @@ -45,6 +45,9 @@ nvlink_core_print_link_state NvU32 txSublinkSubMode = 0; NvU32 rxSublinkSubMode = 0; + if (link == NULL) + return; + link->link_handlers->get_dl_link_mode(link, &linkMode); link->link_handlers->get_tx_mode(link, &txSublinkMode, &txSublinkSubMode); link->link_handlers->get_rx_mode(link, &rxSublinkMode, &rxSublinkSubMode); @@ -86,6 +89,9 @@ _nvlink_core_print_link nvlink_link *link ) { + if (link == NULL) + return; + switch (link->dev->type) { case NVLINK_DEVICE_TYPE_GPU: diff --git a/src/common/nvlink/kernel/nvlink/core/nvlink_shutdown.c b/src/common/nvlink/kernel/nvlink/core/nvlink_shutdown.c index c070a2852..5bbafa8da 100644 --- a/src/common/nvlink/kernel/nvlink/core/nvlink_shutdown.c +++ b/src/common/nvlink/kernel/nvlink/core/nvlink_shutdown.c @@ -61,6 +61,9 @@ nvlink_core_powerdown_intranode_conns_from_active_to_L2 return NVL_ERR_GENERIC; } + if (conns[0] == NULL) + return NVL_ERR_GENERIC; + // Set the version. Currently, only one version is supported on a chip version = conns[0]->end0->version; @@ -71,6 +74,9 @@ nvlink_core_powerdown_intranode_conns_from_active_to_L2 { for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + status = nvlink_core_check_intranode_conn_state(conns[i], NVLINK_LINKSTATE_HS); if ((status == NVL_SUCCESS) || (status == NVL_ERR_INVALID_STATE)) { @@ -98,6 +104,9 @@ nvlink_core_powerdown_intranode_conns_from_active_to_L2 // STEP 0: Disable HeartBeat on the endpoints of all connections for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + conns[i]->end0->link_handlers->set_dl_link_mode(conns[i]->end0, NVLINK_LINKSTATE_DISABLE_HEARTBEAT, flags); @@ -114,6 +123,9 @@ nvlink_core_powerdown_intranode_conns_from_active_to_L2 // STEP 1: Disable PM on the endpoints of all connections for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + conns[i]->end0->link_handlers->set_dl_link_mode(conns[i]->end0, NVLINK_LINKSTATE_DISABLE_PM, flags); @@ -132,6 +144,9 @@ nvlink_core_powerdown_intranode_conns_from_active_to_L2 { for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + status = conns[i]->end0->link_handlers->get_dl_link_mode(conns[i]->end0, &linkMode); if ((status != NVL_SUCCESS) || (linkMode == NVLINK_LINKSTATE_FAIL) || (linkMode == NVLINK_LINKSTATE_FAULT)) @@ -155,6 +170,9 @@ nvlink_core_powerdown_intranode_conns_from_active_to_L2 // Check for each connection, if both the ends and their sublinks are in HS mode for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + status = nvlink_core_check_intranode_conn_state(conns[i], NVLINK_LINKSTATE_HS); if (status == NVL_ERR_INVALID_STATE) { @@ -186,6 +204,9 @@ nvlink_core_powerdown_intranode_conns_from_active_to_L2 // for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + // Wait for the end0 to go to SWCFG status = nvlink_core_poll_link_state(conns[i]->end0, NVLINK_LINKSTATE_SAFE, @@ -212,6 +233,9 @@ nvlink_core_powerdown_intranode_conns_from_active_to_L2 // STEP 3: Change sub-link state to SAFE on all endpoints for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + conns[i]->end0->link_handlers->set_tx_mode(conns[i]->end0, NVLINK_SUBLINK_STATE_TX_SAFE, flags); @@ -228,6 +252,9 @@ nvlink_core_powerdown_intranode_conns_from_active_to_L2 // Poll for all endpoints sub-link state to reach SAFE for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + // Wait for sublinks to go to SAFE status = nvlink_core_poll_sublink_state(conns[i]->end0, NVLINK_SUBLINK_STATE_TX_SAFE, @@ -261,6 +288,9 @@ nvlink_core_powerdown_intranode_conns_from_active_to_L2 // STEP 4: Save link state on all the endpoints for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + if (!conns[i]->end0->bStateSaved) { conns[i]->end0->link_handlers->set_dl_link_mode(conns[i]->end0, @@ -281,6 +311,9 @@ nvlink_core_powerdown_intranode_conns_from_active_to_L2 { for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + status = conns[i]->end0->link_handlers->get_dl_link_mode(conns[i]->end0, &linkMode); if ((status != NVL_SUCCESS) || (linkMode == NVLINK_LINKSTATE_FAIL) || (linkMode == NVLINK_LINKSTATE_FAULT)) @@ -304,6 +337,9 @@ nvlink_core_powerdown_intranode_conns_from_active_to_L2 // STEP 5: Trigger the sleep request on all the endpoints for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + // // Send SLEEP request on one end of connection if not in loopback. // Don' poll, since transition will happen when both ends get the request @@ -327,6 +363,9 @@ nvlink_core_powerdown_intranode_conns_from_active_to_L2 // Finally check the connection states for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + status = nvlink_core_check_intranode_conn_state(conns[i], NVLINK_LINKSTATE_SLEEP); if (status != NVL_SUCCESS) { @@ -392,6 +431,9 @@ nvlink_core_powerdown_intranode_conns_from_active_to_off for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + // Disable Power Management before moving link out of Active conns[i]->end0->link_handlers->set_dl_link_mode(conns[i]->end0, NVLINK_LINKSTATE_DISABLE_PM, @@ -418,6 +460,9 @@ nvlink_core_powerdown_intranode_conns_from_active_to_off // Poll for links to reach SWCFG & initiate sublinks to SAFE state for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + // Wait for the end0 to go to SWCFG status = nvlink_core_poll_link_state(conns[i]->end0, NVLINK_LINKSTATE_SAFE, @@ -430,7 +475,7 @@ nvlink_core_powerdown_intranode_conns_from_active_to_off // to track Failure conns[i]->end0->inSWCFG = NV_FALSE; - } + } else { conns[i]->end0->inSWCFG = NV_TRUE; @@ -448,14 +493,14 @@ nvlink_core_powerdown_intranode_conns_from_active_to_off // to track Failure conns[i]->end1->inSWCFG = NV_FALSE; - } + } else { conns[i]->end1->inSWCFG = NV_TRUE; } // Change each sublink state to SAFE - if(conns[i]->end0->inSWCFG == NV_TRUE) + if(conns[i]->end0->inSWCFG == NV_TRUE) { conns[i]->end0->link_handlers->set_tx_mode(conns[i]->end0, NVLINK_SUBLINK_STATE_TX_SAFE, @@ -473,6 +518,9 @@ nvlink_core_powerdown_intranode_conns_from_active_to_off // Poll for sublinks to reach SAFE state for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + // Wait for sublinks to go to SAFE if(conns[i]->end0->inSWCFG == NV_TRUE) { @@ -623,6 +671,9 @@ nvlink_core_powerdown_intranode_conns_from_active_to_swcfg for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + // Disable Power Management before moving link out of Active conns[i]->end0->link_handlers->set_dl_link_mode(conns[i]->end0, NVLINK_LINKSTATE_DISABLE_PM, @@ -651,6 +702,9 @@ nvlink_core_powerdown_intranode_conns_from_active_to_swcfg // for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + // Wait for the end0 to go to SWCFG status = nvlink_core_poll_link_state(conns[i]->end0, NVLINK_LINKSTATE_SAFE, @@ -694,6 +748,9 @@ nvlink_core_powerdown_intranode_conns_from_active_to_swcfg // Wait for sublinks to go to SAFE for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + status = nvlink_core_poll_sublink_state(conns[i]->end0, NVLINK_SUBLINK_STATE_TX_SAFE, NVLINK_SUBLINK_SUBSTATE_TX_STABLE, @@ -736,6 +793,9 @@ nvlink_core_powerdown_intranode_conns_from_active_to_swcfg // Update tracking info for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_INFO, "%s: Connection is in SAFE mode. ", __FUNCTION__)); @@ -779,6 +839,9 @@ nvlink_core_reset_intranode_conns for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + // // Reset both ends of this connection. // This path should enable/init those link endpoints as well. @@ -825,6 +888,9 @@ _nvlink_core_clear_link_state nvlink_link *link ) { + if (link == NULL) + return; + // Receiver Detect needs to happen again link->bRxDetected = NV_FALSE; @@ -874,8 +940,8 @@ nvlink_core_powerdown_floorswept_conns_to_off ) { NvU32 i,j; - nvlink_intranode_conn **connsToShutdown; - nvlink_intranode_conn **visitedConns; + nvlink_intranode_conn **connsToShutdown = NULL; + nvlink_intranode_conn **visitedConns = NULL; nvlink_intranode_conn *conn; NvU32 connCount; NvU32 numConnsToShutdown; @@ -926,10 +992,15 @@ nvlink_core_powerdown_floorswept_conns_to_off if (links[j]->linkNumber >= numLinksPerIoctrl*i && links[j]->linkNumber < numLinksPerIoctrl*(i+1)) { + conn = NULL; nvlink_core_get_intranode_conn(links[j], &(conn)); if (conn == NULL || - _nvlink_core_check_if_conn_in_array(visitedConns, connCount, conn)) + _nvlink_core_check_if_conn_in_array(visitedConns, connCount, conn) || + (conn->end0 == NULL || conn->end1 == NULL)) { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, + "%s: AC debug -- conn gotten: 0x%x\n", + __FUNCTION__, conn)); continue; } else if(nvlink_core_check_intranode_conn_state(conn, NVLINK_LINKSTATE_OFF) == diff --git a/src/common/nvlink/kernel/nvlink/core/nvlink_training.c b/src/common/nvlink/kernel/nvlink/core/nvlink_training.c index d2d0a2d9d..b1de6c7ae 100644 --- a/src/common/nvlink/kernel/nvlink/core/nvlink_training.c +++ b/src/common/nvlink/kernel/nvlink/core/nvlink_training.c @@ -34,14 +34,22 @@ NvlStatus nvlink_core_train_check_link_ready_ALI ( nvlink_link **links, - NvU32 linkCount + NvU32 linkCount ) { - NvU32 i = 0; + NvU32 i = 0; NvlStatus status = NVL_SUCCESS; + if (links == NULL) + { + return NVL_BAD_ARGS; + } + for (i = 0; i < linkCount; i++) { + if (links[i] == NULL) + continue; + if (!nvlink_core_check_link_state(links[i], NVLINK_LINKSTATE_ALI)) { // If link is not in active, update status to be error and continue @@ -89,6 +97,9 @@ nvlink_core_train_internode_conns_from_swcfg_to_active for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + // Don't do anything if the link is already at HS. if ((nvlink_core_check_link_state(conns[i]->local_end, NVLINK_LINKSTATE_HS)) && (nvlink_core_check_tx_sublink_state(conns[i]->local_end, @@ -133,7 +144,7 @@ nvlink_core_train_internode_conns_from_swcfg_to_active for (i = 0; i < connCount; i++) { - if (skipConn[i]) + if ((conns[i] == NULL) || skipConn[i]) { continue; } @@ -151,6 +162,8 @@ nvlink_core_train_internode_conns_from_swcfg_to_active for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; // Wait for the link state to change. status = nvlink_core_poll_link_state(conns[i]->local_end, @@ -202,6 +215,11 @@ nvlink_core_train_internode_conn_sublink_from_safe_to_hs { NvlStatus status = NVL_SUCCESS; + if (conn == NULL) + { + return NVL_BAD_ARGS; + } + // NVLink 3.0 onwards this is handled through INITOPTIMIZE, return error if (conn->local_end->version >= NVLINK_DEVICE_VERSION_30) { @@ -328,6 +346,9 @@ nvlink_core_train_intranode_conns_from_from_L2_to_active // STEP 1: Reset all endpoints of the links. This clears any link state for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + conns[i]->end0->link_handlers->set_dl_link_mode(conns[i]->end0, NVLINK_LINKSTATE_RESET, flags); @@ -339,6 +360,9 @@ nvlink_core_train_intranode_conns_from_from_L2_to_active // STEP 2: NVLink 3 and beyond, we also need to perform INITPHASE1 for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + conns[i]->end0->link_handlers->set_dl_link_mode(conns[i]->end0, NVLINK_LINKSTATE_INITPHASE1, flags); @@ -355,6 +379,9 @@ nvlink_core_train_intranode_conns_from_from_L2_to_active { for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + status = conns[i]->end0->link_handlers->get_dl_link_mode(conns[i]->end0, &linkMode); if ((status != NVL_SUCCESS) || (linkMode == NVLINK_LINKSTATE_FAIL) || (linkMode == NVLINK_LINKSTATE_FAULT)) @@ -374,6 +401,9 @@ nvlink_core_train_intranode_conns_from_from_L2_to_active // Verify that all the endpoints are now in INIT state for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + status = nvlink_core_check_intranode_conn_state(conns[i], NVLINK_LINKSTATE_OFF); if (status != NVL_SUCCESS) { @@ -389,6 +419,9 @@ nvlink_core_train_intranode_conns_from_from_L2_to_active // STEP 3: Restore all end point state saved while entering SLEEP state for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + if (conns[i]->end0->bStateSaved) { conns[i]->end0->link_handlers->set_dl_link_mode(conns[i]->end0, @@ -409,6 +442,9 @@ nvlink_core_train_intranode_conns_from_from_L2_to_active { for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + status = conns[i]->end0->link_handlers->get_dl_link_mode(conns[i]->end0, &linkMode); if ((status != NVL_SUCCESS) || (linkMode == NVLINK_LINKSTATE_FAIL) || (linkMode == NVLINK_LINKSTATE_FAULT)) @@ -428,6 +464,9 @@ nvlink_core_train_intranode_conns_from_from_L2_to_active // STEP 4: Initialize RX Termination on all end points for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + conns[i]->end0->link_handlers->set_rx_mode(conns[i]->end0, NVLINK_SUBLINK_STATE_RX_INIT_TERM, flags); @@ -441,6 +480,9 @@ nvlink_core_train_intranode_conns_from_from_L2_to_active { for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + status = conns[i]->end0->link_handlers->get_dl_link_mode(conns[i]->end0, &linkMode); if ((status != NVL_SUCCESS) || (linkMode == NVLINK_LINKSTATE_FAIL) || (linkMode == NVLINK_LINKSTATE_FAULT)) @@ -460,6 +502,9 @@ nvlink_core_train_intranode_conns_from_from_L2_to_active // STEP 5: Enable Common mode on Tx's of all endpoints for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + if (!((conns[i]->end0->tx_sublink_state == NVLINK_SUBLINK_STATE_TX_COMMON_MODE) || (conns[i]->end0->tx_sublink_state == NVLINK_SUBLINK_STATE_TX_COMMON_MODE_DISABLE) || (conns[i]->end0->tx_sublink_state == NVLINK_SUBLINK_STATE_TX_DATA_READY))) @@ -483,6 +528,9 @@ nvlink_core_train_intranode_conns_from_from_L2_to_active { for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + status = conns[i]->end0->link_handlers->get_dl_link_mode(conns[i]->end0, &linkMode); if ((status != NVL_SUCCESS) || (linkMode == NVLINK_LINKSTATE_FAIL) || (linkMode == NVLINK_LINKSTATE_FAULT)) @@ -502,6 +550,9 @@ nvlink_core_train_intranode_conns_from_from_L2_to_active // STEP 6: Put all Rx's in RXCAL for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + if (conns[i]->end0->rx_sublink_state != NVLINK_SUBLINK_STATE_RX_RXCAL) { conns[i]->end0->link_handlers->set_rx_mode(conns[i]->end0, @@ -519,6 +570,9 @@ nvlink_core_train_intranode_conns_from_from_L2_to_active // STEP 7: Disable Tx common mode for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + if (!((conns[i]->end0->tx_sublink_state == NVLINK_SUBLINK_STATE_TX_COMMON_MODE_DISABLE) || (conns[i]->end0->tx_sublink_state == NVLINK_SUBLINK_STATE_TX_DATA_READY))) { @@ -538,6 +592,9 @@ nvlink_core_train_intranode_conns_from_from_L2_to_active // STEP 8: Set Data Ready and Enable for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + if (conns[i]->end0->tx_sublink_state != NVLINK_SUBLINK_STATE_TX_DATA_READY) { conns[i]->end0->link_handlers->set_tx_mode(conns[i]->end0, @@ -557,6 +614,9 @@ nvlink_core_train_intranode_conns_from_from_L2_to_active { for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + status = conns[i]->end0->link_handlers->get_dl_link_mode(conns[i]->end0, &linkMode); if ((status != NVL_SUCCESS) || (linkMode == NVLINK_LINKSTATE_FAIL) || (linkMode == NVLINK_LINKSTATE_FAULT)) @@ -576,6 +636,9 @@ nvlink_core_train_intranode_conns_from_from_L2_to_active // STEP 9: Set link mode to SAFE for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + conns[i]->end0->link_handlers->set_dl_link_mode(conns[i]->end0, NVLINK_LINKSTATE_SAFE, flags); @@ -590,6 +653,9 @@ nvlink_core_train_intranode_conns_from_from_L2_to_active // Verify all the endpoints link state now reflect SAFE state for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + status = nvlink_core_poll_link_state(conns[i]->end0, NVLINK_LINKSTATE_SAFE, NVLINK_TRANSITION_SAFE_TIMEOUT); @@ -634,6 +700,9 @@ nvlink_core_train_intranode_conns_from_from_L2_to_active // STEP 9: Set INITNEOGOTIATE for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + conns[i]->end0->link_handlers->set_dl_link_mode(conns[i]->end0, NVLINK_LINKSTATE_INITNEGOTIATE, flags); @@ -651,6 +720,9 @@ nvlink_core_train_intranode_conns_from_from_L2_to_active // STEP 8: Set POST_INITNEGOTIATE for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + conns[i]->end0->link_handlers->set_dl_link_mode(conns[i]->end0, NVLINK_LINKSTATE_POST_INITNEGOTIATE, flags); @@ -684,6 +756,9 @@ nvlink_core_train_intranode_conns_from_from_L2_to_active for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + // Update the power state transition status of the link conns[i]->end0->powerStateTransitionStatus = nvlink_power_state_in_L0; conns[i]->end1->powerStateTransitionStatus = nvlink_power_state_in_L0; @@ -729,6 +804,9 @@ nvlink_core_train_intranode_conns_from_swcfg_to_active_non_ALI // Trigger INITOPTIMIZE on both ends of the connection for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + conns[i]->end0->link_handlers->set_dl_link_mode(conns[i]->end0, NVLINK_LINKSTATE_INITOPTIMIZE, flags); @@ -745,6 +823,9 @@ nvlink_core_train_intranode_conns_from_swcfg_to_active_non_ALI // Trigger POST_INITOPTIMIZE (Checks INITOPTIMIZE was successful) on both ends of the connection for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + conns[i]->end0->link_handlers->set_dl_link_mode(conns[i]->end0, NVLINK_LINKSTATE_POST_INITOPTIMIZE, flags); @@ -761,6 +842,9 @@ nvlink_core_train_intranode_conns_from_swcfg_to_active_non_ALI // Set link modes to ACTIVE for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + // Some settings required before moving to ACTIVE _nvlink_core_set_link_pre_active_settings(conns[i]->end0, flags); _nvlink_core_set_link_pre_active_settings(conns[i]->end1, flags); @@ -783,6 +867,8 @@ nvlink_core_train_intranode_conns_from_swcfg_to_active_non_ALI // Verify link mode HS on the endpoints for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; pollStatus = nvlink_core_poll_link_state(conns[i]->end0, NVLINK_LINKSTATE_HS, @@ -881,6 +967,9 @@ nvlink_core_train_intranode_conns_from_swcfg_to_active_ALT for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + status = conns[i]->end0->link_handlers->get_dl_link_mode(conns[i]->end0, &linkMode); if (status != NVL_SUCCESS) { @@ -903,7 +992,7 @@ nvlink_core_train_intranode_conns_from_swcfg_to_active_ALT // Trigger INITOPTIMIZE on both ends of the connection for (i = 0; i < connCount; i++) { - if (skipConn[i]) + if ((conns[i] == NULL) || skipConn[i]) { continue; } @@ -924,7 +1013,7 @@ nvlink_core_train_intranode_conns_from_swcfg_to_active_ALT // Trigger POST_INITOPTIMIZE (Checks INITOPTIMIZE was successful) on both ends of the connection for (i = 0; i < connCount; i++) { - if (skipConn[i]) + if ((conns[i] == NULL) || skipConn[i]) { continue; } @@ -945,7 +1034,7 @@ nvlink_core_train_intranode_conns_from_swcfg_to_active_ALT // Set link modes to ACTIVE for (i = 0; i < connCount; i++) { - if (skipConn[i]) + if ((conns[i] == NULL) || skipConn[i]) { continue; } @@ -966,7 +1055,7 @@ nvlink_core_train_intranode_conns_from_swcfg_to_active_ALT // Verify link mode HS on the endpoints for (i = 0; i < connCount; i++) { - if (skipConn[i]) + if ((conns[i] == NULL) || skipConn[i]) { continue; } @@ -1067,6 +1156,9 @@ nvlink_core_train_intranode_conns_from_swcfg_to_active_legacy // Enable PRBS generator on both ends of the link for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + _nvlink_core_set_sublink_pre_hs_settings(conns[i]->end0, flags); _nvlink_core_set_sublink_pre_hs_settings(conns[i]->end1, flags); } @@ -1074,6 +1166,9 @@ nvlink_core_train_intranode_conns_from_swcfg_to_active_legacy // Put TX sublink on both ends in High Speed for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + conns[i]->end0->link_handlers->set_tx_mode(conns[i]->end0, NVLINK_SUBLINK_STATE_TX_HS, flags); @@ -1085,6 +1180,9 @@ nvlink_core_train_intranode_conns_from_swcfg_to_active_legacy // Wait for sublinks to go in High Speed. for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + pollStatus = nvlink_core_poll_sublink_state(conns[i]->end0, NVLINK_SUBLINK_STATE_TX_HS, NVLINK_SUBLINK_SUBSTATE_TX_STABLE, @@ -1121,6 +1219,9 @@ nvlink_core_train_intranode_conns_from_swcfg_to_active_legacy // Some settings required before moving to ACTIVE for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + _nvlink_core_set_link_pre_active_settings(conns[i]->end0, flags); _nvlink_core_set_link_pre_active_settings(conns[i]->end1, flags); @@ -1136,6 +1237,9 @@ nvlink_core_train_intranode_conns_from_swcfg_to_active_legacy // Verify link mode HS on the endpoints for (i = 0; i < connCount; i++) { + if (conns[i] == NULL) + continue; + pollStatus = nvlink_core_poll_link_state(conns[i]->end1, NVLINK_LINKSTATE_HS, NVLINK_TRANSITION_HS_TIMEOUT); @@ -1198,6 +1302,9 @@ _nvlink_core_set_sublink_pre_hs_settings NvU32 flags ) { + if (link == NULL) + return; + // // Before training the sublinks to HS, the PROD values must be loaded. // On Volta/NVSwitch, the PROD values get loaded by UCODE during DLPL Init. @@ -1225,6 +1332,9 @@ _nvlink_core_set_link_pre_active_settings NvU32 flags ) { + if (link == NULL) + return; + // Some settings required before moving to ACTIVE link->link_handlers->set_dl_link_mode(link, NVLINK_LINKSTATE_PRE_HS, flags); } @@ -1243,6 +1353,9 @@ _nvlink_core_set_link_post_active_settings NvU32 flags ) { + if (link == NULL) + return; + link->link_handlers->training_complete(link); link->link_handlers->set_tx_mode(link, NVLINK_SUBLINK_STATE_TX_POST_HS, flags); diff --git a/src/common/nvlink/kernel/nvlink/interface/nvlink_ioctl_entry.c b/src/common/nvlink/kernel/nvlink/interface/nvlink_ioctl_entry.c index 807158355..13591e33d 100644 --- a/src/common/nvlink/kernel/nvlink/interface/nvlink_ioctl_entry.c +++ b/src/common/nvlink/kernel/nvlink/interface/nvlink_ioctl_entry.c @@ -3573,10 +3573,10 @@ nvlink_lib_ctrl_get_device_link_states // FOR_EACH_LINK_REGISTERED(endpoint, dev, node) { - if (numLinks >= NVLINK_MAX_NVLINK_ENDPOINTS) + if (numLinks >= NVLINK_MAX_SYSTEM_LINK_NUM) { NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, - "%s: numLinks >= NVLINK_MAX_NVLINK_ENDPOINTS", + "%s: numLinks >= NVLINK_MAX_SYSTEM_LINK_NUM", __FUNCTION__)); nvlink_assert(0); diff --git a/src/common/nvswitch/common/inc/rmsoecmdif.h b/src/common/nvswitch/common/inc/rmsoecmdif.h index 12e6871d6..eac20c0da 100644 --- a/src/common/nvswitch/common/inc/rmsoecmdif.h +++ b/src/common/nvswitch/common/inc/rmsoecmdif.h @@ -116,7 +116,7 @@ typedef struct #define RM_SOE_TASK_ID_CHNMGMT 0x0B #define RM_SOE_TASK_ID_RMMSG 0x0C // Add new task ID here... -#define RM_SOE_TASK_ID__END 0x0C +#define RM_SOE_TASK_ID__END 0x0D /*! * Unit-identifiers: @@ -139,8 +139,7 @@ typedef struct #define RM_SOE_UNIT_IFR (0x0C) #define RM_SOE_UNIT_CHNMGMT (0x0D) // Add new unit ID here... -#define RM_SOE_UNIT_END (0x0D) - +#define RM_SOE_UNIT_END (0x0E) #endif // _RMSOECMDIF_H_ diff --git a/src/common/nvswitch/common/inc/soe/soeifcore.h b/src/common/nvswitch/common/inc/soe/soeifcore.h index 29412d9ab..4af463fd9 100644 --- a/src/common/nvswitch/common/inc/soe/soeifcore.h +++ b/src/common/nvswitch/common/inc/soe/soeifcore.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -51,6 +51,26 @@ enum * Run DMA self-test */ RM_SOE_CORE_CMD_DMA_SELFTEST, + + /*! + * Perform I2C transaction + */ + RM_SOE_CORE_CMD_I2C_ACCESS, + + /*! + * Issue NPORT Reset + */ + RM_SOE_CORE_CMD_ISSUE_NPORT_RESET, + + /*! + * Restore NPORT state + */ + RM_SOE_CORE_CMD_RESTORE_NPORT_STATE, + + /*! + * Set NPORT TPROD state + */ + RM_SOE_CORE_CMD_SET_NPORT_TPROD_STATE }; // Timeout for SOE reset callback function @@ -63,6 +83,10 @@ enum #define RM_SOE_DMA_READ_TEST_SUBCMD 0x00 #define RM_SOE_DMA_WRITE_TEST_SUBCMD 0x01 + +#define SOE_I2C_DMA_BUF_SIZE 512 +#define SOE_I2C_STATUS_INDEX (SOE_I2C_DMA_BUF_SIZE - 1) + /*! * CORE queue command payload */ @@ -83,10 +107,39 @@ typedef struct NvU16 xferSize; } RM_SOE_CORE_CMD_DMA_TEST; +typedef struct +{ + NvU8 cmdType; + RM_FLCN_U64 dmaHandle; + NvU16 xferSize; +} RM_SOE_CORE_CMD_I2C; + +typedef struct +{ + NvU8 cmdType; + NvU32 nport; +} RM_SOE_CORE_CMD_NPORT_RESET; + +typedef struct +{ + NvU8 cmdType; + NvU32 nport; +} RM_SOE_CORE_CMD_NPORT_STATE; + +typedef struct +{ + NvU8 cmdType; + NvU32 nport; +} RM_SOE_CORE_CMD_NPORT_TPROD_STATE; + typedef union { NvU8 cmdType; RM_SOE_CORE_CMD_BIOS bios; RM_SOE_CORE_CMD_DMA_TEST dma_test; + RM_SOE_CORE_CMD_I2C i2c; + RM_SOE_CORE_CMD_NPORT_RESET nportReset; + RM_SOE_CORE_CMD_NPORT_STATE nportState; + RM_SOE_CORE_CMD_NPORT_TPROD_STATE nportTprodState; } RM_SOE_CORE_CMD; #endif // _SOECORE_H_ diff --git a/src/common/nvswitch/common/inc/soe/soeififr.h b/src/common/nvswitch/common/inc/soe/soeififr.h index 6a3347793..3a70d6f48 100644 --- a/src/common/nvswitch/common/inc/soe/soeififr.h +++ b/src/common/nvswitch/common/inc/soe/soeififr.h @@ -30,8 +30,12 @@ enum { - RM_SOE_IFR_READ, - RM_SOE_IFR_WRITE, + RM_SOE_IFR_READ, + RM_SOE_IFR_WRITE, + RM_SOE_IFR_BBX_INITIALIZE, + RM_SOE_IFR_BBX_SHUTDOWN, + RM_SOE_IFR_BBX_SXID_ADD, + RM_SOE_IFR_BBX_SXID_GET, }; typedef struct @@ -43,10 +47,39 @@ typedef struct char fileName[INFOROM_FS_FILE_NAME_SIZE]; } RM_SOE_IFR_CMD_PARAMS; +typedef struct +{ + NvU8 cmdType; + RM_FLCN_U64 time; + NvU8 osType; + NvU32 osVersion; +} RM_SOE_IFR_CMD_BBX_INIT_PARAMS; + +typedef struct +{ + NvU8 cmdType; +} RM_SOE_IFR_CMD_BBX_SHUTDOWN_PARAMS; + +typedef struct +{ + NvU8 cmdType; + NvU32 exceptionType; + NvU32 data[3]; +} RM_SOE_IFR_CMD_BBX_SXID_ADD_PARAMS; + +typedef struct +{ + NvU8 cmdType; + RM_FLCN_U64 dmaHandle; +} RM_SOE_IFR_CMD_BBX_SXID_GET_PARAMS; + typedef union { NvU8 cmdType; RM_SOE_IFR_CMD_PARAMS params; + RM_SOE_IFR_CMD_BBX_INIT_PARAMS bbxInit; + RM_SOE_IFR_CMD_BBX_SXID_ADD_PARAMS bbxSxidAdd; + RM_SOE_IFR_CMD_BBX_SXID_GET_PARAMS bbxSxidGet; } RM_SOE_IFR_CMD; #endif // _SOEIFIFR_H_ diff --git a/src/common/nvswitch/common/inc/soe/soeifsmbpbi.h b/src/common/nvswitch/common/inc/soe/soeifsmbpbi.h index 6c2cf9bf4..4c3038852 100644 --- a/src/common/nvswitch/common/inc/soe/soeifsmbpbi.h +++ b/src/common/nvswitch/common/inc/soe/soeifsmbpbi.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -32,6 +32,8 @@ * Command Messages between driver and SMBPBI unit of SOE */ +#include "oob/smbpbi.h" + /*! * Test command/event type */ @@ -41,6 +43,8 @@ enum RM_SOE_SMBPBI_CMD_ID_INIT, RM_SOE_SMBPBI_CMD_ID_UNLOAD, RM_SOE_SMBPBI_CMD_ID_SET_LINK_ERROR_INFO, + RM_SOE_SMBPBI_CMD_ID_LOG_MESSAGE, + RM_SOE_SMBPBI_CMD_ID_INIT_DATA, }; /*! @@ -102,6 +106,37 @@ typedef struct } RM_SOE_SMBPBI_CMD_SET_LINK_ERROR_INFO, *PRM_SOE_SMBPBI_CMD_SET_LINK_ERROR_INFO; +/*! + * SMBPBI queue log message command payload + * TOFIX: Command size may not exceed 0x80, so we have + * to split the message into multiple segments. + * We anticipate that the max cmd size will be increased. + */ +#define RM_SOE_SMBPBI_CMD_LOG_MESSAGE_MAX_STRING 80 +#define RM_SOE_SMBPBI_CMD_LOG_MESSAGE_STRING_SEGMENT_SZ 42 +typedef struct +{ + NvU8 cmdType; + NvU8 msgLen; + NvU8 msgOffset; + NvU8 segSize; + NvU32 sxidId; + NvU32 timeStamp; + NvU8 errorString[RM_SOE_SMBPBI_CMD_LOG_MESSAGE_STRING_SEGMENT_SZ]; +} RM_SOE_SMBPBI_CMD_LOG_MESSAGE, +*PRM_SOE_SMBPBI_CMD_LOG_MESSAGE; + +/*! + * SMBPBI init data command payload + */ +#define RM_SOE_SMBPBI_CMD_INIT_DATA_MAX_STRING 16 +typedef struct +{ + NvU8 cmdType; + NvU8 driverVersionString[RM_SOE_SMBPBI_CMD_INIT_DATA_MAX_STRING]; +} RM_SOE_SMBPBI_CMD_INIT_DATA, +*PRM_SOE_SMBPBI_CMD_INIT_DATA; + /*! * SMBPBI queue command payload */ @@ -112,6 +147,8 @@ typedef union RM_SOE_SMBPBI_CMD_INIT init; RM_SOE_SMBPBI_CMD_UNLOAD unload; RM_SOE_SMBPBI_CMD_SET_LINK_ERROR_INFO linkErrorInfo; + RM_SOE_SMBPBI_CMD_LOG_MESSAGE logMessage; + RM_SOE_SMBPBI_CMD_INIT_DATA initData; } RM_SOE_SMBPBI_CMD; #endif // _SOEIFSMBPBI_H_ diff --git a/src/common/nvswitch/interface/ctrl_dev_nvswitch.h b/src/common/nvswitch/interface/ctrl_dev_nvswitch.h index 12ffd208f..ca6090d2c 100644 --- a/src/common/nvswitch/interface/ctrl_dev_nvswitch.h +++ b/src/common/nvswitch/interface/ctrl_dev_nvswitch.h @@ -960,7 +960,14 @@ typedef enum nvswitch_err_type NVSWITCH_ERR_HW_NPORT_ROUTE_NVS_ECC_LIMIT_ERR = 15011, NVSWITCH_ERR_HW_NPORT_ROUTE_NVS_ECC_DBE_ERR = 15012, NVSWITCH_ERR_HW_NPORT_ROUTE_CDTPARERR = 15013, - NVSWITCH_ERR_HW_NPORT_ROUTE_LAST = 15021, /* NOTE: Must be last */ + NVSWITCH_ERR_HW_NPORT_ROUTE_MCRID_ECC_LIMIT_ERR = 15014, + NVSWITCH_ERR_HW_NPORT_ROUTE_MCRID_ECC_DBE_ERR = 15015, + NVSWITCH_ERR_HW_NPORT_ROUTE_EXTMCRID_ECC_LIMIT_ERR = 15016, + NVSWITCH_ERR_HW_NPORT_ROUTE_EXTMCRID_ECC_DBE_ERR = 15017, + NVSWITCH_ERR_HW_NPORT_ROUTE_RAM_ECC_LIMIT_ERR = 15018, + NVSWITCH_ERR_HW_NPORT_ROUTE_RAM_ECC_DBE_ERR = 15019, + NVSWITCH_ERR_HW_NPORT_ROUTE_INVALID_MCRID_ERR = 15020, + NVSWITCH_ERR_HW_NPORT_ROUTE_LAST, /* NOTE: Must be last */ /* NPORT: Nport errors */ NVSWITCH_ERR_HW_NPORT = 16000, @@ -1212,6 +1219,7 @@ typedef enum nvswitch_err_type NVSWITCH_ERR_HW_NVLIPT_LNK_SLEEPWHILEACTIVELINK = 25007, NVSWITCH_ERR_HW_NVLIPT_LNK_RSTSEQ_PHYCTL_TIMEOUT = 25008, NVSWITCH_ERR_HW_NVLIPT_LNK_RSTSEQ_CLKCTL_TIMEOUT = 25009, + NVSWITCH_ERR_HW_NVLIPT_LNK_ALI_TRAINING_FAIL = 25010, NVSWITCH_ERR_HW_NVLIPT_LNK_LAST, /* Note: Must be last */ /* SOE errors */ @@ -1226,6 +1234,26 @@ typedef enum nvswitch_err_type NVSWITCH_ERR_HW_SOE_WATCHDOG = 26008, NVSWITCH_ERR_HW_SOE_LAST, /* Note: Must be last */ + /* NPORT: Multicast Tstate errors */ + NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE = 28000, + NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_TAGPOOL_ECC_LIMIT_ERR = 28001, + NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_TAGPOOL_ECC_DBE_ERR = 28002, + NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_CRUMBSTORE_ECC_LIMIT_ERR = 28003, + NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_CRUMBSTORE_ECC_DBE_ERR = 28004, + NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_CRUMBSTORE_BUF_OVERWRITE_ERR = 28005, + NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_CRUMBSTORE_MCTO_ERR = 28006, + NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_LAST, /* Note: Must be last */ + + /* NPORT: Reduction Tstate errors */ + NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE = 29000, + NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_TAGPOOL_ECC_LIMIT_ERR = 29001, + NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_TAGPOOL_ECC_DBE_ERR = 29002, + NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_CRUMBSTORE_ECC_LIMIT_ERR = 29003, + NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_CRUMBSTORE_ECC_DBE_ERR = 29004, + NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_CRUMBSTORE_BUF_OVERWRITE_ERR = 29005, + NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_CRUMBSTORE_RTO_ERR = 29006, + NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_LAST, /* Note: Must be last */ + /* Please update nvswitch_translate_hw_errors with a newly added error class. */ NVSWITCH_ERR_LAST /* See enum modification guidelines at the top of this file */ @@ -1829,10 +1857,12 @@ typedef struct /* NVLink link states */ #define NVSWITCH_NVLINK_STATUS_LINK_STATE_INIT (0x00000000) +#define NVSWITCH_NVLINK_STATUS_LINK_STATE_HWPCFG (0x0000000c) #define NVSWITCH_NVLINK_STATUS_LINK_STATE_HWCFG (0x00000001) #define NVSWITCH_NVLINK_STATUS_LINK_STATE_SWCFG (0x00000002) #define NVSWITCH_NVLINK_STATUS_LINK_STATE_ACTIVE (0x00000003) #define NVSWITCH_NVLINK_STATUS_LINK_STATE_FAULT (0x00000004) +#define NVSWITCH_NVLINK_STATUS_LINK_STATE_SLEEP (0x00000005) #define NVSWITCH_NVLINK_STATUS_LINK_STATE_RECOVERY (0x00000006) #define NVSWITCH_NVLINK_STATUS_LINK_STATE_INVALID (0xFFFFFFFF) @@ -2057,6 +2087,21 @@ typedef struct nvswitch_get_bios_info NvU64 version; } NVSWITCH_GET_BIOS_INFO_PARAMS; +#define NVSWITCH_INFOROM_VERSION_LEN 16 +/* + * CTRL_NVSWITCH_GET_INFOROM_VERSION + * + * Control call to get INFOROM information. + * + * Parameters: + * version [OUT] + * Inforom version in char value. + */ +typedef struct nvswitch_get_inforom_version +{ + NvU8 version[NVSWITCH_INFOROM_VERSION_LEN]; +} NVSWITCH_GET_INFOROM_VERSION_PARAMS; + /* * CTRL_NVSWITCH_BLACKLIST_DEVICE * @@ -2166,8 +2211,9 @@ typedef struct nvswitch_set_training_error_info #define NVSWITCH_DEVICE_EVENT_NONFATAL 1 #define NVSWITCH_DEVICE_EVENT_PORT_UP 2 #define NVSWITCH_DEVICE_EVENT_PORT_DOWN 3 -#define NVSWITCH_DEVICE_EVENT_INBAND_DATA 4 -#define NVSWITCH_DEVICE_EVENT_COUNT 5 +#define NVSWITCH_DEVICE_EVENT_FABRIC_STATE 4 +#define NVSWITCH_DEVICE_EVENT_INBAND_DATA 5 +#define NVSWITCH_DEVICE_EVENT_COUNT 6 #define NVSWITCH_REGISTER_EVENTS_MAX_EVENT_IDS (500) /* @@ -2248,6 +2294,158 @@ typedef struct nvswitch_get_fatal_error_scope_params NvBool port[NVSWITCH_MAX_PORTS]; } NVSWITCH_GET_FATAL_ERROR_SCOPE_PARAMS; +/* + * CTRL_NVSWITCH_SET_MC_RID_TABLE + * + * Control for programming an ingress multicast RID table entry. + * This interface is only supported on LS10 architecture. All others will + * return an error. Architecture can be queried using _GET_INFO_INDEX_ARCH. + * + * Parameters: + * portNum [IN] + * A valid port number present in the port masks returned by + * NVSWITCH_GET_INFO + * index [IN] + * Index within the multicast RID table to be programmed. This is + * equivalent to MCID. + * extendedTable [IN] + * boolean: Set the requested entry in the extended table + * else set the requested entry in the main table + * ports [IN] + * The list of ports. For each multicast request, the address hash + * selects the multicast port string, and hardware multicasts to ports + * in that string. + * vcHop [IN] + * Array of VC hop values for each port. + * mcSize [IN] + * Number of ports in the multicast group (must be a nonzero value). + * Must be the number of ports in the main table, plus the extended table + * if that is used. + * Must be the same for all spray groups. + * Caller is responsible for ensuring the above conditions, as the driver + * provides only minimal range checking. + * numSprayGroups [IN] + * Number of groups to spray over. This must be a nonzero value. + * portsPerSprayGroup [IN] + * Array, number of ports contained in each spray group. + * Note these must all be the same size unless an extended entry + * is used, + * _and_ numSprayGroups is the same for both the main entry and extended + * entry, + * _and_ the sum of ports in the main and extended groups equals + * mcSize for each spray group. + * FM is responsible for providing the correct value. Driver provides only + * minimal range checking. + * replicaOffset [IN] + * Array, offsets within each spray group to the primary replica port for the group. + * The caller should specify mcSize primaryReplicas. + * replicaValid [IN] + * boolean: Array, set the primary replica according to the replicaOffset array. + * else let hardware choose a default primary replica port + * extendedPtr [IN] + * pointer to the extended table to append to the multicast table entry + * can only be valid in the main table entries + * extendedValid [IN] + * boolean: Use the extended index to append to the main table string. + * else the main string specifies the complete operation for its MCID + * noDynRsp [IN] + * boolean: no dynamic alt selection on MC responses. This field has no meaning in + * the extended table + * entryValid + * boolean: flag this entry in the MC RID table as valid + */ + +#define NVSWITCH_MC_MAX_PORTS 64 +#define NVSWITCH_MC_MAX_SPRAYGROUPS 16 + +#define NVSWITCH_MC_VCHOP_PASS 0 +#define NVSWITCH_MC_VCHOP_INVERT 1 +#define NVSWITCH_MC_VCHOP_FORCE0 2 +#define NVSWITCH_MC_VCHOP_FORCE1 3 + +typedef struct nvswitch_set_mc_rid_table_params +{ + NvU32 portNum; + NvU32 index; + NvBool extendedTable; + NvU32 ports[NVSWITCH_MC_MAX_PORTS]; + NvU8 vcHop[NVSWITCH_MC_MAX_PORTS]; + NvU32 mcSize; + NvU32 numSprayGroups; + NvU32 portsPerSprayGroup[NVSWITCH_MC_MAX_SPRAYGROUPS]; + NvU32 replicaOffset[NVSWITCH_MC_MAX_SPRAYGROUPS]; + NvBool replicaValid[NVSWITCH_MC_MAX_SPRAYGROUPS]; + NvU32 extendedPtr; + NvBool extendedValid; + NvBool noDynRsp; + NvBool entryValid; +} NVSWITCH_SET_MC_RID_TABLE_PARAMS; + +/* + * CTRL_NVSWITCH_GET_MC_RID_TABLE + * + * Control for reading an ingress multicast RID table entry. + * This interface is only supported on LS10 architecture. All others will + * return an error. Architecture can be queried using _GET_INFO_INDEX_ARCH. + * + * Parameters: + * portNum [IN] + * A valid port number present in the port masks returned by + * NVSWITCH_GET_INFO + * index [IN] + * Index within the multicast RID table to be retrieved. This is + * equivalent to MCID. + * extendedTable [IN] + * boolean: Get the requested entry from the extended table. + * Else get the requested entry from the main table. + * ports [OUT] + * The list of ports. Port order within spray groups is not guaranteed + * to be preserved. + * vcHop [OUT] + * Array containing VC hop values for each entry in the ports array. + * mcSize [OUT] + * Number of ports in the multicast group. + * numSprayGroups [OUT] + * Number of groups to spray over. + * portsPerSprayGroup [OUT] + * Array, each element contains the number of ports within each corresponding + * spray group. + * replicaOffset [OUT] + * Array, offsets within each spray group to the primary replica port + * for the group. + * replicaValid [OUT] + * boolean: Array, specifies whether each entry in the replicaOffset + * array is valid. + * extendedPtr [OUT] + * Pointer to the extended table appended to the main table entry. + * Only valid for main table entries. + * extendedValid [OUT] + * boolean: Whether the extendedPtr is valid. + * noDynRsp [IN] + * boolean: no dynamic alt selection on MC responses. + * This field has no meaning in the extended table. + * entryValid + * boolean: Whether this entry in the MC RID table is valid + */ + +typedef struct nvswitch_get_mc_rid_table_params +{ + NvU32 portNum; + NvU32 index; + NvBool extendedTable; + NvU32 ports[NVSWITCH_MC_MAX_PORTS]; + NvU8 vcHop[NVSWITCH_MC_MAX_PORTS]; + NvU32 mcSize; + NvU32 numSprayGroups; + NvU32 portsPerSprayGroup[NVSWITCH_MC_MAX_SPRAYGROUPS]; + NvU32 replicaOffset[NVSWITCH_MC_MAX_SPRAYGROUPS]; + NvBool replicaValid[NVSWITCH_MC_MAX_SPRAYGROUPS]; + NvU32 extendedPtr; + NvBool extendedValid; + NvBool noDynRsp; + NvBool entryValid; +} NVSWITCH_GET_MC_RID_TABLE_PARAMS; + #define NVSWITCH_I2C_SMBUS_CMD_QUICK 0 #define NVSWITCH_I2C_SMBUS_CMD_BYTE 1 #define NVSWITCH_I2C_SMBUS_CMD_BYTE_DATA 2 @@ -2875,7 +3073,7 @@ typedef struct nvswitch_get_rd_stall_busy typedef struct nvswitch_get_multicast_id_error_vector { NvU32 link; - NvU32 error_vector[NVSWITCH_MC_ID_ERROR_VECTOR_COUNT / sizeof(NvU32)]; + NvU32 error_vector[NVSWITCH_MC_ID_ERROR_VECTOR_COUNT / 32]; } NVSWITCH_GET_MULTICAST_ID_ERROR_VECTOR; /* @@ -2894,9 +3092,104 @@ typedef struct nvswitch_get_multicast_id_error_vector typedef struct nvswitch_clear_multicast_id_error_vector { NvU32 link; - NvU32 error_vector[NVSWITCH_MC_ID_ERROR_VECTOR_COUNT / sizeof(NvU32)]; + NvU32 error_vector[NVSWITCH_MC_ID_ERROR_VECTOR_COUNT / 32]; } NVSWITCH_CLEAR_MULTICAST_ID_ERROR_VECTOR; +/* + * NVSWITCH_NVLINK_ERR_INFO + * Error information per link + * + * Parameters: + * TLErrlog + * Returns the error mask for NVLINK TL errors + * Used in Pascal + * + * TLIntrEn + * Returns the intr enable mask for NVLINK TL errors + * Used in Pascal + * + * TLCTxErrStatus0 + * Returns the TLC Tx Error Mask 0 + * Used in Volta + * + * TLCRxErrStatus0 + * Returns the TLC Rx Error Mask 0 + * Used in Volta + * + * TLCRxErrStatus1 + * Returns the TLC Rx Error Mask 1 + * Used in Volta + * + * TLCTxErrLogEn0 + * Returns the TLC Tx Error Log En 0 + * Used in Volta + * + * TLCRxErrLogEn0 + * Returns the TLC Rx Error Log En 0 + * Used in Volta + * + * TLCRxErrLogEn1 + * Returns the TLC Rx Error Log En 1 + * Used in Volta + * + * MIFTxErrStatus0 + * Returns the MIF Rx Error Mask 0 + * Used in Volta + * + * MIFRxErrStatus0 + * Returns the MIF Tx Error Mask 0 + * Used in Volta + * + * DLSpeedStatusTx + * Returns the NVLINK DL speed status for sublink Tx + * + * DLSpeedStatusRx + * Returns the NVLINK DL speed status for sublink Rx + * + * bExcessErrorDL + * Returns true for excessive error rate interrupt from DL + */ +typedef struct +{ + NvU32 TLErrlog; + NvU32 TLIntrEn; + NvU32 TLCTxErrStatus0; + NvU32 TLCRxErrStatus0; + NvU32 TLCRxErrStatus1; + NvU32 TLCTxErrLogEn0; + NvU32 TLCRxErrLogEn0; + NvU32 TLCRxErrLogEn1; + NvU32 MIFTxErrStatus0; + NvU32 MIFRxErrStatus0; + NvU32 DLSpeedStatusTx; + NvU32 DLSpeedStatusRx; + NvBool bExcessErrorDL; +} NVSWITCH_NVLINK_ERR_INFO; + +/* + * CTRL_NVSWITCH_GET_ERR_INFO + * This command is used to query the NVLINK error information + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +/* + * NVSWITCH_NVLINK_GET_ERR_INFO_PARAMS + * + * linkMask + * Returns the mask of links enabled + * + * linkErrInfo + * Returns the error information for all the links + */ +typedef struct +{ + NV_DECLARE_ALIGNED(NvU64 linkMask, 8); + NVSWITCH_NVLINK_ERR_INFO linkErrInfo[NVSWITCH_NVLINK_MAX_LINKS]; +} NVSWITCH_NVLINK_GET_ERR_INFO_PARAMS; + #define NVSWITCH_INBAND_DATA_SIZE 4096 /* @@ -3006,6 +3299,29 @@ typedef struct nvswitch_get_sw_info_params NvU32 info[NVSWITCH_GET_SW_INFO_COUNT_MAX]; } NVSWITCH_GET_SW_INFO_PARAMS; +/* + * CTRL_NVSWITCH_CLEAR_COUNTERS + * This command clears/resets the counters for the specified types. + * + * [in] linkMask + * This parameter specifies for which links we want to clear the + * counters. + * + * [in] counterMask + * This parameter specifies the input mask for desired counters to be + * cleared. Note that all counters cannot be cleared. + * + * NOTE: Bug# 2098529: On Turing all DL errors and LP counters are cleared + * together. They cannot be cleared individually per error type. RM + * would possibly move to a new API on Ampere and beyond + */ + +typedef struct +{ + NV_DECLARE_ALIGNED(NvU64 linkMask, 8); + NvU32 counterMask; +} NVSWITCH_NVLINK_CLEAR_COUNTERS_PARAMS; + /* * NVSWITCH_CTRL_I2C_DEVICE_INFO * @@ -3246,6 +3562,88 @@ typedef struct NvU8 message[NVSWITCH_CTRL_I2C_MESSAGE_LENGTH_MAX]; } NVSWITCH_CTRL_I2C_INDEXED_PARAMS; +/* + * Structure to store register values required to debug ALI training failures + * + * dlstatMn00 + * DLSTAT MN00 register value (subcode and code) + * dlstatUc01 + * DLSTAT UC01 register value + * dlstatLinkIntr + * NV_MINION_NVLINK_LINK_INTR (subcode, code and state) + */ +typedef struct nvswitch_minion_ali_debug_registers +{ + NvU32 dlstatMn00; + NvU32 dlstatUc01; + NvU32 dlstatLinkIntr; +} NVSWITCH_MINION_ALI_DEBUG_REGISTERS; + +/* + * CTRL_NVSWITCH_REGISTER_READ/WRITE + * + * This provides direct access to the MMIO space. + */ + +typedef struct +{ + NvU32 engine; // REGISTER_RW_ENGINE_* + NvU32 instance; // engine instance + NvU32 offset; // Register offset within device/instance + NvU32 val; // out: register value read +} NVSWITCH_REGISTER_READ; + +typedef struct +{ + NvU32 engine; // REGISTER_RW_ENGINE_* + NvU32 instance; // engine instance + NvBool bcast; // Unicast or broadcast + NvU32 offset; // Register offset within engine/instance + NvU32 val; // in: register value to write +} NVSWITCH_REGISTER_WRITE; + +#define REGISTER_RW_ENGINE_RAW 0x00 + +#define REGISTER_RW_ENGINE_CLKS 0x10 +#define REGISTER_RW_ENGINE_FUSE 0x11 +#define REGISTER_RW_ENGINE_JTAG 0x12 +#define REGISTER_RW_ENGINE_PMGR 0x13 +#define REGISTER_RW_ENGINE_SAW 0x14 +#define REGISTER_RW_ENGINE_XP3G 0x15 +#define REGISTER_RW_ENGINE_XVE 0x16 +#define REGISTER_RW_ENGINE_SOE 0x17 +#define REGISTER_RW_ENGINE_SMR 0x18 +#define REGISTER_RW_ENGINE_SE 0x19 +#define REGISTER_RW_ENGINE_CLKS_SYS 0x1A +#define REGISTER_RW_ENGINE_CLKS_SYSB 0x1B +#define REGISTER_RW_ENGINE_CLKS_P0 0x1C +#define REGISTER_RW_ENGINE_XPL 0x1D +#define REGISTER_RW_ENGINE_XTL 0x1E + +#define REGISTER_RW_ENGINE_SIOCTRL 0x20 +#define REGISTER_RW_ENGINE_MINION 0x21 +#define REGISTER_RW_ENGINE_NVLIPT 0x22 +#define REGISTER_RW_ENGINE_NVLTLC 0x23 +#define REGISTER_RW_ENGINE_NVLTLC_MULTICAST 0x24 +#define REGISTER_RW_ENGINE_DLPL 0x25 +#define REGISTER_RW_ENGINE_NVLW 0x26 +#define REGISTER_RW_ENGINE_NVLIPT_LNK 0x27 +#define REGISTER_RW_ENGINE_NVLIPT_LNK_MULTICAST 0x28 +#define REGISTER_RW_ENGINE_NVLDL 0x29 +#define REGISTER_RW_ENGINE_NVLDL_MULTICAST 0x2a +#define REGISTER_RW_ENGINE_PLL 0x2b + +#define REGISTER_RW_ENGINE_NPG 0x30 +#define REGISTER_RW_ENGINE_NPORT 0x31 +#define REGISTER_RW_ENGINE_NPORT_MULTICAST 0x32 + +#define REGISTER_RW_ENGINE_SWX 0x40 +#define REGISTER_RW_ENGINE_AFS 0x41 +#define REGISTER_RW_ENGINE_NXBAR 0x42 +#define REGISTER_RW_ENGINE_TILE 0x43 +#define REGISTER_RW_ENGINE_TILE_MULTICAST 0x44 +#define REGISTER_RW_ENGINE_TILEOUT 0x45 +#define REGISTER_RW_ENGINE_TILEOUT_MULTICAST 0x46 /* * CTRL call command list. @@ -3294,6 +3692,8 @@ typedef struct #define CTRL_NVSWITCH_UNREGISTER_EVENTS 0x25 #define CTRL_NVSWITCH_SET_TRAINING_ERROR_INFO 0x26 #define CTRL_NVSWITCH_GET_FATAL_ERROR_SCOPE 0x27 +#define CTRL_NVSWITCH_SET_MC_RID_TABLE 0x28 +#define CTRL_NVSWITCH_GET_MC_RID_TABLE 0x29 #define CTRL_NVSWITCH_GET_COUNTERS 0x2A #define CTRL_NVSWITCH_GET_NVLINK_ECC_ERRORS 0x2B #define CTRL_NVSWITCH_I2C_SMBUS_COMMAND 0x2C @@ -3322,10 +3722,14 @@ typedef struct #define CTRL_NVSWITCH_GET_SW_INFO 0x47 #define CTRL_NVSWITCH_RESERVED_6 0x48 #define CTRL_NVSWITCH_RESERVED_7 0x49 -/* - * DO NOT ADD CODE AFTER THIS LINE. - * If the command hits 0xA0, see ctrl_dev_internal_nvswitch.h to adjust the internal range. - */ +#define CTRL_NVSWITCH_RESERVED_8 0x4A +#define CTRL_NVSWITCH_RESERVED_9 0x4B +#define CTRL_NVSWITCH_RESERVED_10 0x4C +#define CTRL_NVSWITCH_REGISTER_READ 0x4D +#define CTRL_NVSWITCH_REGISTER_WRITE 0x4E +#define CTRL_NVSWITCH_GET_INFOROM_VERSION 0x4F +#define CTRL_NVSWITCH_GET_ERR_INFO 0x50 +#define CTRL_NVSWITCH_CLEAR_COUNTERS 0x51 #ifdef __cplusplus } diff --git a/src/common/nvswitch/interface/export_nvswitch.h b/src/common/nvswitch/interface/export_nvswitch.h index 77d41bd51..42d60c3f0 100644 --- a/src/common/nvswitch/interface/export_nvswitch.h +++ b/src/common/nvswitch/interface/export_nvswitch.h @@ -642,6 +642,12 @@ nvswitch_os_get_platform_time void ); +NvU64 +nvswitch_os_get_platform_time_epoch +( + void +); + #define NVSWITCH_PRINT_ATTRIB(str, arg1) \ __attribute__ ((format (printf, (str), (arg1)))) diff --git a/src/common/nvswitch/kernel/bios_nvswitch.c b/src/common/nvswitch/kernel/bios_nvswitch.c index f6a752495..de238e088 100644 --- a/src/common/nvswitch/kernel/bios_nvswitch.c +++ b/src/common/nvswitch/kernel/bios_nvswitch.c @@ -81,7 +81,7 @@ _nvswitch_core_bios_read nvswitch_os_memset(&cmd, 0, sizeof(cmd)); cmd.hdr.unitId = RM_SOE_UNIT_CORE; - cmd.hdr.size = sizeof(cmd); + cmd.hdr.size = RM_SOE_CMD_SIZE(CORE, BIOS); cmd.cmd.core.bios.cmdType = readType; RM_FLCN_U64_PACK(&pParams->dmaHandle, &dmaHandle); pParams->offset = offset; diff --git a/src/common/nvswitch/kernel/error_nvswitch.c b/src/common/nvswitch/kernel/error_nvswitch.c index ee1676710..e1c6aba91 100644 --- a/src/common/nvswitch/kernel/error_nvswitch.c +++ b/src/common/nvswitch/kernel/error_nvswitch.c @@ -40,12 +40,13 @@ _nvswitch_dump_error_entry if ((error_entry != NULL) && (error_entry->error_src == NVSWITCH_ERROR_SRC_HW)) { - NVSWITCH_PRINT_SXID(device, error_entry->error_type, + NVSWITCH_PRINT_SXID_NO_BBX(device, error_entry->error_type, "Severity %d Engine instance %02d Sub-engine instance %02d\n", error_entry->severity, error_entry->instance, error_entry->subinstance); - NVSWITCH_PRINT_SXID(device, error_entry->error_type, - "Data {0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x}\n", + NVSWITCH_PRINT_SXID_NO_BBX(device, error_entry->error_type, + "Data {0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x}\n", + error_entry->data.raw.flags, error_entry->data.raw.data[0], error_entry->data.raw.data[1], error_entry->data.raw.data[2], error_entry->data.raw.data[3], error_entry->data.raw.data[4], error_entry->data.raw.data[5], @@ -61,7 +62,7 @@ _nvswitch_dump_error_entry (error_entry->data.raw.data[15] != 0)) { - NVSWITCH_PRINT_SXID(device, error_entry->error_type, + NVSWITCH_PRINT_SXID_NO_BBX(device, error_entry->error_type, "Data {0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x}\n", error_entry->data.raw.data[ 8], error_entry->data.raw.data[ 9], error_entry->data.raw.data[10], error_entry->data.raw.data[11], @@ -394,10 +395,20 @@ nvswitch_translate_hw_error { return NVSWITCH_ERR_HW_SOE; } + else if ((type >= NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE) && + (type < NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_LAST)) + { + return NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE; + } + else if ((type >= NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE) && + (type < NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_LAST)) + { + return NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE; + } else { // Update this assert after adding a new translation entry above - ct_assert(NVSWITCH_ERR_HW_SOE_LAST == (NVSWITCH_ERR_LAST - 1)); + ct_assert(NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_LAST == (NVSWITCH_ERR_LAST - 1)); NVSWITCH_PRINT(NULL, ERROR, "%s: Undefined error type\n", __FUNCTION__); diff --git a/src/common/nvswitch/kernel/flcn/flcn_nvswitch.c b/src/common/nvswitch/kernel/flcn/flcn_nvswitch.c index 5a6a1abd6..99101ad52 100644 --- a/src/common/nvswitch/kernel/flcn/flcn_nvswitch.c +++ b/src/common/nvswitch/kernel/flcn/flcn_nvswitch.c @@ -409,6 +409,11 @@ flcnSetupHal flcnSetupHal_LR10(pFlcn); goto _flcnSetupHal_success; } + if (nvswitch_is_ls10_device_id(pci_device_id)) + { + flcnSetupHal_LS10(pFlcn); + goto _flcnSetupHal_success; + } NVSWITCH_PRINT(NULL, ERROR, "Flcn hal can't be setup due to unknown device id\n"); diff --git a/src/common/nvswitch/kernel/flcn/flcnqueue_dmem_nvswitch.c b/src/common/nvswitch/kernel/flcn/flcnqueue_dmem_nvswitch.c index b31be1ecd..a587ef70a 100644 --- a/src/common/nvswitch/kernel/flcn/flcnqueue_dmem_nvswitch.c +++ b/src/common/nvswitch/kernel/flcn/flcnqueue_dmem_nvswitch.c @@ -264,13 +264,6 @@ _flcnQueueOpenWrite_dmem status = _flcnQueueHasRoom_dmem(device, pFlcn, pQueue, writeSize, &bRewind); if (NV_OK != status) { - if (NV_ERR_INSUFFICIENT_RESOURCES == status) - { - NVSWITCH_PRINT(device, INFO, - "%s: queue is too full to write data (write-size=0x%x).\n", - __FUNCTION__, writeSize); - } - return status; } diff --git a/src/common/nvswitch/kernel/flcn/flcnqueue_nvswitch.c b/src/common/nvswitch/kernel/flcn/flcnqueue_nvswitch.c index 3b41b0544..8abf2600e 100644 --- a/src/common/nvswitch/kernel/flcn/flcnqueue_nvswitch.c +++ b/src/common/nvswitch/kernel/flcn/flcnqueue_nvswitch.c @@ -28,6 +28,12 @@ #include "rmflcncmdif_nvswitch.h" #include "common_nvswitch.h" +// +// Yield the CPU temporarily after openWrite() in _flcnQueueCmdWrite_IMPL() +// fails this many times in a row. +// +#define FLCN_QUEUE_CMD_WRITE_SLEEP_TRIES 1024 + /*! * @file flcnqueue_nvswitch.c * @brief Provides all the fundamental logic for reading/writing queues. @@ -437,6 +443,7 @@ _flcnQueueCmdWrite_IMPL PFLCNQUEUE pQueue; PFALCON_QUEUE_INFO pQueueInfo = pFlcn->pQueueInfo; NvBool bKeepPolling; + NvU32 nTries = 0; NVSWITCH_ASSERT(pTimeout != NULL); NVSWITCH_ASSERT(pQueueInfo != NULL); @@ -464,6 +471,17 @@ _flcnQueueCmdWrite_IMPL __FUNCTION__, pQueue->queueLogId); return NV_ERR_FLCN_ERROR; } + + if (++nTries < 4) + { + NVSWITCH_PRINT(device, INFO, + "%s: queue is too full to write data (write-size=0x%x).\n", + __FUNCTION__, pCmd->cmdGen.hdr.size); + } + else if ((nTries % FLCN_QUEUE_CMD_WRITE_SLEEP_TRIES) == 0) + { + nvswitch_os_sleep(1); + } } else { @@ -474,29 +492,27 @@ _flcnQueueCmdWrite_IMPL if (status == NV_ERR_INSUFFICIENT_RESOURCES) { +#if defined(DEBUG) + RM_FLCN_CMD FlcnCmd; + NV_STATUS dumpStatus; + + dumpStatus = flcnRtosDumpCmdQueue_nvswitch(device, pFlcn, queueLogId, &FlcnCmd); + if (dumpStatus != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Dumping Falcon Command queue completed with status 0x%x \n", + __FUNCTION__ , dumpStatus); + } +#endif // DEBUG + NVSWITCH_PRINT(device, ERROR, - "%s: Timeout while waiting for space (queueLogId=0x%x).\n", - __FUNCTION__, pQueue->queueLogId); + "%s: Timeout after %d tries while waiting for space (queueLogId=0x%x).\n" + "Command queue:\n", + __FUNCTION__, nTries, pQueue->queueLogId); + return NV_ERR_TIMEOUT; } - // - // if failed to write Command due to no space, - // dump the queue contents if debug flag is on - // -#if defined(DEBUG) - if (status == NV_ERR_INSUFFICIENT_RESOURCES) - { - RM_FLCN_CMD FlcnCmd; - NV_STATUS dumpstatus; - - dumpstatus = flcnRtosDumpCmdQueue_nvswitch(device, pFlcn, queueLogId, &FlcnCmd); - NVSWITCH_PRINT(device, ERROR, - "%s: Dumping Falcon Command queue completed with status =0x%x \n", - __FUNCTION__ , dumpstatus ); - } -#endif - if (status != NV_OK) { NVSWITCH_PRINT(device, WARN, @@ -516,7 +532,7 @@ _flcnQueueCmdWrite_IMPL status = pQueue->close(device, pFlcn, pQueue, NV_TRUE); if (status == NV_OK) { - NVSWITCH_PRINT(device, INFO, + NVSWITCH_PRINT(device, MMIO, "%s: command queued (unit-id=0x%x).\n", __FUNCTION__, pCmd->cmdGen.hdr.unitId); } @@ -1563,7 +1579,7 @@ _flcnQueueCmdValidate * @return NV_ERR_TIMEOUT * A timeout occurred before the command completed. */ -NV_STATUS +static NV_STATUS _flcnQueueCmdWait_IMPL ( nvswitch_device *device, @@ -1628,4 +1644,3 @@ flcnQueueSetupHal pHal->queueCmdPostNonBlocking = _flcnQueueCmdPostNonBlocking_IMPL; pHal->queueCmdWait = _flcnQueueCmdWait_IMPL; } - diff --git a/src/common/nvswitch/kernel/flcn/flcnqueuerd_nvswitch.c b/src/common/nvswitch/kernel/flcn/flcnqueuerd_nvswitch.c index 5a06856b6..3280482ed 100644 --- a/src/common/nvswitch/kernel/flcn/flcnqueuerd_nvswitch.c +++ b/src/common/nvswitch/kernel/flcn/flcnqueuerd_nvswitch.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -72,7 +72,7 @@ static NV_STATUS _flcnQueueReaderReadBody (nvswitch_device *, PFLCN, FLCNQUE "status=0x%x).\n", __FUNCTION__, (id), (status)) #define NVSWITCH_PRINT_QUEUE_READER_PRINT_HDR_READ_INFO(offset) \ - NVSWITCH_PRINT(device, INFO, \ + NVSWITCH_PRINT(device, MMIO, \ "%s: Reading a header from DMEM @ 0x%x.\n", \ __FUNCTION__, (offset)) diff --git a/src/common/nvswitch/kernel/inc/common_nvswitch.h b/src/common/nvswitch/kernel/inc/common_nvswitch.h index 8ea0c39b8..95207f9f3 100644 --- a/src/common/nvswitch/kernel/inc/common_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/common_nvswitch.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -152,6 +152,17 @@ static NV_INLINE void nvswitch_clear_flags(NvU32 *val, NvU32 flags) nvswitch_inforom_bbx_add_sxid(_d, _sxid, 0, 0, 0); \ } while(0) +#define NVSWITCH_PRINT_SXID_NO_BBX(_d, _sxid, _fmt, ...) \ + do \ + { \ + NVSWITCH_ASSERT(nvswitch_translate_hw_error(_sxid) != NVSWITCH_NVLINK_HW_GENERIC); \ + nvswitch_os_print(NVSWITCH_DBG_LEVEL_ERROR, \ + "nvidia-%s: SXid (PCI:" NVLINK_PCI_DEV_FMT "): %05d, " _fmt, \ + (_d)->name, NVLINK_PCI_DEV_FMT_ARGS(&(_d)->nvlink_device->pciInfo), _sxid, \ + ##__VA_ARGS__); \ + nvswitch_lib_smbpbi_log_sxid(_d, _sxid, _fmt, ##__VA_ARGS__); \ + } while(0) + #define NVSWITCH_DEV_CMD_DISPATCH_WITH_PRIVATE_DATA(cmd, function, type, private)\ case cmd: \ { \ @@ -189,18 +200,9 @@ static NV_INLINE void nvswitch_clear_flags(NvU32 *val, NvU32 flags) #define NVSWITCH_MODS_CMDS_SUPPORTED NV_FALSE -#if defined(DEBUG) || defined(DEVELOP) || defined(NV_MODS) -#define NVSWITCH_TEST_CMDS_SUPPORTED NV_TRUE -#else -#define NVSWITCH_TEST_CMDS_SUPPORTED NV_FALSE -#endif - #define NVSWITCH_DEV_CMD_DISPATCH_MODS(cmd, function, type) \ NVSWITCH_DEV_CMD_DISPATCH_HELPER(cmd, NVSWITCH_MODS_CMDS_SUPPORTED, function, type) -#define NVSWITCH_DEV_CMD_DISPATCH_TEST(cmd, function, type) \ - NVSWITCH_DEV_CMD_DISPATCH_HELPER(cmd, NVSWITCH_TEST_CMDS_SUPPORTED, function, type) - #define NVSWITCH_MAX_NUM_LINKS 100 #if NVSWITCH_MAX_NUM_LINKS <= 100 #define NVSWITCH_LINK_INSTANCE_LEN 2 @@ -251,9 +253,13 @@ typedef struct NvU32 select_uphy_tables; NvU32 link_training_mode; NvU32 i2c_access_control; + NvU32 force_kernel_i2c; NvU32 link_recal_settings; NvU32 crc_bit_error_rate_short; NvU32 crc_bit_error_rate_long; + NvU32 lp_threshold; + NvU32 minion_intr; + NvU32 surpress_link_errors_for_gpu_reset; } NVSWITCH_REGKEY_TYPE; // @@ -261,14 +267,28 @@ typedef struct // typedef struct NVSWITCH_TASK { + struct NVSWITCH_TASK *prev; struct NVSWITCH_TASK *next; - void (*task_fn)(nvswitch_device *); + void (*task_fn_vdptr)(nvswitch_device *, void *); + void (*task_fn_devptr)(nvswitch_device *); + void *task_args; NvU64 period_nsec; NvU64 last_run_nsec; NvU32 flags; } NVSWITCH_TASK_TYPE; -#define NVSWITCH_TASK_TYPE_FLAGS_ALWAYS_RUN 0x1 // Run even the if not initialized +#define NVSWITCH_TASK_TYPE_FLAGS_RUN_EVEN_IF_DEVICE_NOT_INITIALIZED 0x1 // Run even the if not initialized +#define NVSWITCH_TASK_TYPE_FLAGS_RUN_ONCE 0x2 // Only run the task once. Memory for task struct and args will be freed by dispatcher after running. +#define NVSWITCH_TASK_TYPE_FLAGS_VOID_PTR_ARGS 0x4 // Function accepts args as void * args. + +// +// Wrapper struct for deffered SXID errors +// +typedef struct +{ + NvU32 nvlipt_instance; + NvU32 link; +} NVSWITCH_DEFERRED_ERROR_REPORTING_ARGS; // // PLL @@ -487,6 +507,7 @@ typedef struct NVSWITCH_TIMEOUT #define NVSWITCH_INTERVAL_50USEC_IN_NS 50000LL #define NVSWITCH_INTERVAL_1MSEC_IN_NS 1000000LL #define NVSWITCH_INTERVAL_5MSEC_IN_NS 5000000LL +#define NVSWITCH_INTERVAL_750MSEC_IN_NS 750000000LL #define NVSWITCH_INTERVAL_1SEC_IN_NS 1000000000LL #define NVSWITCH_INTERVAL_4SEC_IN_NS 4000000000LL @@ -516,8 +537,12 @@ void nvswitch_reg_write_32(nvswitch_device *device, NvU32 offset, NvU32 data); NvU64 nvswitch_read_64bit_counter(nvswitch_device *device, NvU32 lo_offset, NvU32 hi_offset); void nvswitch_timeout_create(NvU64 timeout_ns, NVSWITCH_TIMEOUT *time); NvBool nvswitch_timeout_check(NVSWITCH_TIMEOUT *time); -void nvswitch_task_create(nvswitch_device *device, -void (*task_fn)(nvswitch_device *device), NvU64 period_nsec, NvU32 flags); +NvlStatus nvswitch_task_create(nvswitch_device *device, + void (*task_fn)(nvswitch_device *device), + NvU64 period_nsec, NvU32 flags); +NvlStatus nvswitch_task_create_args(nvswitch_device* device, void *fn_args, + void (*task_fn)(nvswitch_device* device, void *fn_args), + NvU64 period_nsec, NvU32 flags); void nvswitch_tasks_destroy(nvswitch_device *device); void nvswitch_free_chipdevice(nvswitch_device *device); @@ -535,6 +560,7 @@ void nvswitch_reset_persistent_link_hw_state(nvswitch_device *device, NvU32 void nvswitch_store_topology_information(nvswitch_device *device, nvlink_link *link); NvlStatus nvswitch_launch_ALI(nvswitch_device *device); +NvlStatus nvswitch_launch_ALI_link_training(nvswitch_device *device, nvlink_link *link, NvBool bSync); NvlStatus nvswitch_inband_read_data(nvswitch_device *device, NvU8 *dest, NvU32 linkId, NvU32 *dataSize); void nvswitch_filter_messages(nvswitch_device *device, NvU32 linkId); NvlStatus nvswitch_set_training_mode(nvswitch_device *device); diff --git a/src/common/nvswitch/kernel/inc/haldef_nvswitch.h b/src/common/nvswitch/kernel/inc/haldef_nvswitch.h index b061a5219..02a6025ee 100644 --- a/src/common/nvswitch/kernel/inc/haldef_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/haldef_nvswitch.h @@ -94,6 +94,8 @@ _op(NvlStatus, nvswitch_ctrl_set_latency_bins, (nvswitch_device *device, NVSWITCH_SET_LATENCY_BINS *p), _arch) \ _op(NvlStatus, nvswitch_ctrl_get_ingress_reqlinkid, (nvswitch_device *device, NVSWITCH_GET_INGRESS_REQLINKID_PARAMS *params), _arch) \ _op(NvU32, nvswitch_i2c_get_port_info, (nvswitch_device *device, NvU32 port), _arch) \ + _op(NvlStatus, nvswitch_ctrl_register_read, (nvswitch_device *device, NVSWITCH_REGISTER_READ *p), _arch) \ + _op(NvlStatus, nvswitch_ctrl_register_write, (nvswitch_device *device, NVSWITCH_REGISTER_WRITE *p), _arch) \ _op(NvlStatus, nvswitch_ctrl_i2c_indexed, (nvswitch_device *device, NVSWITCH_CTRL_I2C_INDEXED_PARAMS *pParams), _arch) \ _op(NvlStatus, nvswitch_ctrl_therm_read_temperature, (nvswitch_device *device, NVSWITCH_CTRL_GET_TEMPERATURE_PARAMS *info), _arch) \ _op(NvlStatus, nvswitch_ctrl_therm_get_temperature_limit, (nvswitch_device *device, NVSWITCH_CTRL_GET_TEMPERATURE_LIMIT_PARAMS *info), _arch) \ @@ -122,7 +124,9 @@ _op(NvBool, nvswitch_is_smbpbi_supported, (nvswitch_device *device), _arch) \ _op(NvlStatus, nvswitch_post_init_device_setup, (nvswitch_device *device), _arch) \ _op(void, nvswitch_post_init_blacklist_device_setup, (nvswitch_device *device), _arch) \ - _op(NvlStatus, nvswitch_setup_link_system_registers, (nvswitch_device *device), _arch) \ + _op(NvlStatus, nvswitch_setup_system_registers, (nvswitch_device *device), _arch) \ + _op(void, nvswitch_setup_link_system_registers, (nvswitch_device *device, nvlink_link *link), _arch) \ + _op(void, nvswitch_load_link_disable_settings, (nvswitch_device *device, nvlink_link *link), _arch) \ _op(NvlStatus, nvswitch_read_vbios_link_entries, (nvswitch_device *device, NvU32 tblPtr,NvU32 expected_link_entriesCount,NVLINK_CONFIG_DATA_LINKENTRY *link_entries, NvU32 *identified_link_entriesCount), _arch) \ _op(NvlStatus, nvswitch_vbios_read_structure, (nvswitch_device *device, void *structure, NvU32 offset, NvU32 *ppacked_size, const char *format), _arch) \ _op(NvlStatus, nvswitch_get_nvlink_ecc_errors, (nvswitch_device *device, NVSWITCH_GET_NVLINK_ECC_ERRORS_PARAMS *p), _arch) \ @@ -137,19 +141,25 @@ _op(void, nvswitch_load_uuid, (nvswitch_device *device), _arch) \ _op(void, nvswitch_i2c_set_hw_speed_mode, (nvswitch_device *device, NvU32 port, NvU32 speedMode), _arch) \ _op(NvlStatus, nvswitch_ctrl_get_bios_info, (nvswitch_device *device, NVSWITCH_GET_BIOS_INFO_PARAMS *p), _arch) \ + _op(NvlStatus, nvswitch_ctrl_get_inforom_version, (nvswitch_device *device, NVSWITCH_GET_INFOROM_VERSION_PARAMS *p), _arch) \ _op(NvlStatus, nvswitch_read_oob_blacklist_state, (nvswitch_device *device), _arch) \ _op(NvlStatus, nvswitch_write_fabric_state, (nvswitch_device *device), _arch) \ _op(void, nvswitch_initialize_oms_state, (nvswitch_device *device, INFOROM_OMS_STATE *pOmsState), _arch) \ _op(NvlStatus, nvswitch_oms_inforom_flush, (nvswitch_device *device), _arch) \ _op(void, nvswitch_inforom_ecc_get_total_errors, (nvswitch_device *device, INFOROM_ECC_OBJECT *pEccGeneric, NvU64 *corCount, NvU64 *uncCount), _arch) \ - _op(NvlStatus, nvswitch_bbx_setup_prologue, (nvswitch_device *device, void *pInforomBbxState), _arch) \ - _op(NvlStatus, nvswitch_bbx_setup_epilogue, (nvswitch_device *device, void *pInforomBbxState), _arch) \ - _op(NvlStatus, nvswitch_bbx_add_data_time, (nvswitch_device *device, void *pInforomBbxState, void *pInforomBbxData), _arch) \ - _op(NvlStatus, nvswitch_bbx_add_sxid, (nvswitch_device *device, void *pInforomBbxState, void *pInforomBbxData), _arch) \ - _op(NvlStatus, nvswitch_bbx_add_temperature, (nvswitch_device *device, void *pInforomBbxState, void *pInforomBbxData), _arch) \ - _op(void, nvswitch_bbx_set_initial_temperature, (nvswitch_device *device, void *pInforomBbxState, void *pInforomBbxData), _arch) \ - _op(NvlStatus, nvswitch_inforom_bbx_get_sxid, (nvswitch_device *device, NVSWITCH_GET_SXIDS_PARAMS *p), _arch) \ + _op(NvlStatus, nvswitch_bbx_add_sxid, (nvswitch_device *device, NvU32 exceptionType, NvU32 data0, NvU32 data1, NvU32 data2), _arch) \ + _op(NvlStatus, nvswitch_bbx_unload, (nvswitch_device *device), _arch) \ + _op(NvlStatus, nvswitch_bbx_load, (nvswitch_device *device, NvU64 time_ns, NvU8 osType, NvU32 osVersion), _arch) \ + _op(NvlStatus, nvswitch_bbx_get_sxid, (nvswitch_device *device, NVSWITCH_GET_SXIDS_PARAMS * params), _arch) \ + _op(NvlStatus, nvswitch_smbpbi_alloc, (nvswitch_device *device), _arch) \ + _op(NvlStatus, nvswitch_smbpbi_post_init_hal, (nvswitch_device *device), _arch) \ + _op(void, nvswitch_smbpbi_destroy_hal, (nvswitch_device *device), _arch) \ + _op(void, nvswitch_smbpbi_send_unload, (nvswitch_device *device), _arch) \ + _op(NvlStatus, nvswitch_smbpbi_dem_load, (nvswitch_device *device), _arch) \ + _op(void, nvswitch_smbpbi_dem_flush, (nvswitch_device *device), _arch) \ _op(NvlStatus, nvswitch_smbpbi_get_dem_num_messages, (nvswitch_device *device, NvU8 *pMsgCount), _arch) \ + _op(void, nvswitch_smbpbi_log_message, (nvswitch_device *device, NvU32 num, NvU32 msglen, NvU8 *osErrorString), _arch) \ + _op(NvlStatus, nvswitch_smbpbi_send_init_data, (nvswitch_device *device), _arch) \ _op(NvlStatus, nvswitch_set_minion_initialized, (nvswitch_device *device, NvU32 idx_minion, NvBool initialized), _arch) \ _op(NvBool, nvswitch_is_minion_initialized, (nvswitch_device *device, NvU32 idx_minion), _arch) \ _op(NvlStatus, nvswitch_get_link_public_id, (nvswitch_device *device, NvU32 linkId, NvU32 *publicId), _arch) \ @@ -206,13 +216,19 @@ _op(void, nvswitch_apply_recal_settings, (nvswitch_device *device, nvlink_link *), _arch) \ _op(NvlStatus, nvswitch_service_nvldl_fatal_link, (nvswitch_device *device, NvU32 nvliptInstance, NvU32 link), _arch) \ _op(NvlStatus, nvswitch_service_minion_link, (nvswitch_device *device, NvU32 link_id), _arch) \ - _op(NvlStatus, nvswitch_ctrl_get_sw_info, (nvswitch_device *device, NVSWITCH_GET_SW_INFO_PARAMS *p), _arch) + _op(NvlStatus, nvswitch_ctrl_get_sw_info, (nvswitch_device *device, NVSWITCH_GET_SW_INFO_PARAMS *p), _arch) \ + _op(NvlStatus, nvswitch_ctrl_get_err_info, (nvswitch_device *device, NVSWITCH_NVLINK_GET_ERR_INFO_PARAMS *ret), _arch) \ + _op(NvlStatus, nvswitch_ctrl_clear_counters, (nvswitch_device *device, NVSWITCH_NVLINK_CLEAR_COUNTERS_PARAMS *ret), _arch) #define NVSWITCH_HAL_FUNCTION_LIST_LS10(_op, _arch) \ _op(NvlStatus, nvswitch_launch_ALI, (nvswitch_device *device), _arch) \ - _op(NvlStatus, nvswitch_launch_ALI_link_training, (nvswitch_device *device, nvlink_link *link), _arch) \ + _op(NvlStatus, nvswitch_launch_ALI_link_training, (nvswitch_device *device, nvlink_link *link, NvBool bSync), _arch) \ _op(NvlStatus, nvswitch_ctrl_inband_send_data, (nvswitch_device *device, NVSWITCH_INBAND_SEND_DATA_PARAMS *p), _arch) \ _op(NvlStatus, nvswitch_ctrl_inband_read_data, (nvswitch_device *device, NVSWITCH_INBAND_READ_DATA_PARAMS *p), _arch) \ + _op(void, nvswitch_send_inband_nack, (nvswitch_device *device, NvU32 *msghdr, NvU32 linkId), _arch) \ + _op(NvU32, nvswitch_get_max_persistent_message_count, (nvswitch_device *device), _arch) \ + _op(NvlStatus, nvswitch_ctrl_set_mc_rid_table, (nvswitch_device *device, NVSWITCH_SET_MC_RID_TABLE_PARAMS *p), _arch) \ + _op(NvlStatus, nvswitch_ctrl_get_mc_rid_table, (nvswitch_device *device, NVSWITCH_GET_MC_RID_TABLE_PARAMS *p), _arch) \ _op(NvlStatus, nvswitch_ctrl_set_residency_bins, (nvswitch_device *device, NVSWITCH_SET_RESIDENCY_BINS *p), _arch) \ _op(NvlStatus, nvswitch_ctrl_get_residency_bins, (nvswitch_device *device, NVSWITCH_GET_RESIDENCY_BINS *p), _arch) \ _op(NvlStatus, nvswitch_ctrl_get_rb_stall_busy, (nvswitch_device *device, NVSWITCH_GET_RB_STALL_BUSY *p), _arch) \ diff --git a/src/common/nvswitch/kernel/inc/inforom/inforom_nvswitch.h b/src/common/nvswitch/kernel/inc/inforom/inforom_nvswitch.h index 98f43d2ba..9f800c608 100644 --- a/src/common/nvswitch/kernel/inc/inforom/inforom_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/inforom/inforom_nvswitch.h @@ -46,6 +46,20 @@ (destName)[2] = (srcName)[2]; \ } +// +// OS type defines. +// +#define INFOROM_BBX_OBJ_V1_00_SYSTEM_OS_TYPE_OTHER 0x0 +#define INFOROM_BBX_OBJ_V1_00_SYSTEM_OS_TYPE_WIN9X 0x1 +#define INFOROM_BBX_OBJ_V1_00_SYSTEM_OS_TYPE_WIN2K 0x2 +#define INFOROM_BBX_OBJ_V1_00_SYSTEM_OS_TYPE_WIN 0x4 +#define INFOROM_BBX_OBJ_V1_00_SYSTEM_OS_TYPE_UNIX 0x5 + +#define INFOROM_BBX_OBJ_V1_00_SYSTEM_OS_MAJOR 7:0 +#define INFOROM_BBX_OBJ_V1_00_SYSTEM_OS_MINOR 15:8 +#define INFOROM_BBX_OBJ_V1_00_SYSTEM_OS_BUILD 31:16 + + struct INFOROM_OBJECT_CACHE_ENTRY { INFOROM_OBJECT_HEADER_V1_00 header; @@ -110,6 +124,7 @@ NvlStatus nvswitch_inforom_load_object(nvswitch_device* device, const char *pObjectFormat, NvU8 *pPackedObject, void *pObject); void nvswitch_inforom_read_static_data(nvswitch_device *device, struct inforom *pInforom, RM_SOE_SMBPBI_INFOROM_DATA *pData); +void nvswitch_inforom_string_copy(inforom_U008 *pSrc, NvU8 *pDst, NvU32 size); // InfoROM RO APIs NvlStatus nvswitch_inforom_read_only_objects_load(nvswitch_device *device); @@ -151,8 +166,6 @@ void nvswitch_inforom_bbx_unload(nvswitch_device * device); NvlStatus nvswitch_inforom_bbx_add_sxid(nvswitch_device *device, NvU32 exceptionType, NvU32 data0, NvU32 data1, NvU32 data2); -void nvswitch_bbx_collect_current_time(nvswitch_device *device, - void *pBbxState); NvlStatus nvswitch_inforom_bbx_get_sxid(nvswitch_device *device, NVSWITCH_GET_SXIDS_PARAMS *params); diff --git a/src/common/nvswitch/kernel/inc/io_nvswitch.h b/src/common/nvswitch/kernel/inc/io_nvswitch.h index b3fc071b1..4a3305408 100644 --- a/src/common/nvswitch/kernel/inc/io_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/io_nvswitch.h @@ -125,7 +125,6 @@ typedef struct engine_descriptor _op(PTIMER) \ _op(CPR) \ _op(TILEOUT) \ - _op(TILEOUT_PERFMON) \ #define NVSWITCH_LIST_ALL_ENGINES(_op) \ _op(XVE) \ @@ -150,11 +149,6 @@ typedef struct engine_descriptor _op(NPORT_PERFMON) \ \ _op(NVLW_PERFMON) \ - _op(RX_PERFMON) \ - _op(TX_PERFMON) \ - \ - _op(NXBAR_PERFMON) \ - _op(TILE_PERFMON) \ #define ENGINE_ID_LIST(_eng) \ NVSWITCH_ENGINE_ID_##_eng, @@ -360,12 +354,6 @@ typedef struct NvBool bIsRepeaterMode; - // Check if BUFFER_COMPLETE is seen - volatile NvBool isBufferComplete; - - // Check if BUFFER_FAIL is seen - volatile NvBool isBufferFail; - // Minion Inband Data structure nvswitch_inband_receive_data inbandData; diff --git a/src/common/nvswitch/kernel/inc/lr10/inforom_lr10.h b/src/common/nvswitch/kernel/inc/lr10/inforom_lr10.h index 1196feb2e..b5d60ce43 100644 --- a/src/common/nvswitch/kernel/inc/lr10/inforom_lr10.h +++ b/src/common/nvswitch/kernel/inc/lr10/inforom_lr10.h @@ -108,56 +108,36 @@ nvswitch_oms_inforom_flush_lr10 struct nvswitch_device *device ); -NvlStatus -nvswitch_bbx_setup_prologue_lr10 -( - nvswitch_device *device, - void *pInforomBbxState -); - -NvlStatus -nvswitch_bbx_setup_epilogue_lr10 -( - nvswitch_device *device, - void *pInforomBbxState -); - -NvlStatus -nvswitch_bbx_add_data_time_lr10 -( - nvswitch_device *device, - void *pInforomBbxState, - void *pInforomBbxData -); - NvlStatus nvswitch_bbx_add_sxid_lr10 ( nvswitch_device *device, - void *pInforomBbxState, - void *pInforomBbxData + NvU32 exceptionType, + NvU32 data0, + NvU32 data1, + NvU32 data2 ); NvlStatus -nvswitch_bbx_add_temperature_lr10 +nvswitch_bbx_unload_lr10 ( - nvswitch_device *device, - void *pInforomBbxState, - void *pInforomBbxData -); - -void -nvswitch_bbx_set_initial_temperature_lr10 -( - nvswitch_device *device, - void *pInforomBbxState, - void *pInforomBbxData + nvswitch_device *device ); NvlStatus -nvswitch_inforom_bbx_get_sxid_lr10 +nvswitch_bbx_load_lr10 ( nvswitch_device *device, - NVSWITCH_GET_SXIDS_PARAMS *params + NvU64 time_ns, + NvU8 osType, + NvU32 osVersion ); + +NvlStatus +nvswitch_bbx_get_sxid_lr10 +( + nvswitch_device *device, + NVSWITCH_GET_SXIDS_PARAMS * params +); + #endif //_INFOROM_LR10_H_ diff --git a/src/common/nvswitch/kernel/inc/lr10/lr10.h b/src/common/nvswitch/kernel/inc/lr10/lr10.h index 454f6491c..93fd6a615 100644 --- a/src/common/nvswitch/kernel/inc/lr10/lr10.h +++ b/src/common/nvswitch/kernel/inc/lr10/lr10.h @@ -470,11 +470,6 @@ typedef struct _op(NPORT_PERFMON, _MULTICAST_BCAST) \ \ _op(NVLW_PERFMON, _BCAST) \ - _op(RX_PERFMON, _MULTICAST_BCAST) \ - _op(TX_PERFMON, _MULTICAST_BCAST) \ - \ - _op(NXBAR_PERFMON, _BCAST) \ - _op(TILE_PERFMON, _MULTICAST_BCAST) \ typedef struct { @@ -648,11 +643,20 @@ NvlStatus nvswitch_ctrl_get_nvlink_lp_counters_lr10(nvswitch_device *device, NVS NvlStatus nvswitch_service_nvldl_fatal_link_lr10(nvswitch_device *device, NvU32 nvliptInstance, NvU32 link); NvlStatus nvswitch_ctrl_inband_send_data_lr10(nvswitch_device *device, NVSWITCH_INBAND_SEND_DATA_PARAMS *p); NvlStatus nvswitch_ctrl_inband_read_data_lr10(nvswitch_device *device, NVSWITCH_INBAND_READ_DATA_PARAMS *p); -NvlStatus nvswitch_launch_ALI_link_training_lr10(nvswitch_device *device, nvlink_link *link); +void nvswitch_send_inband_nack_lr10(nvswitch_device *device, NvU32 *msghdr, NvU32 linkId); +NvU32 nvswitch_get_max_persistent_message_count_lr10(nvswitch_device *device); +NvlStatus nvswitch_launch_ALI_link_training_lr10(nvswitch_device *device, nvlink_link *link, NvBool bSync); NvlStatus nvswitch_service_minion_link_lr10(nvswitch_device *device, NvU32 nvliptInstance); void nvswitch_apply_recal_settings_lr10(nvswitch_device *device, nvlink_link *link); NvlStatus nvswitch_ctrl_get_sw_info_lr10(nvswitch_device *device, NVSWITCH_GET_SW_INFO_PARAMS *p); +void nvswitch_setup_link_system_registers_lr10(nvswitch_device *device, nvlink_link *link); +void nvswitch_load_link_disable_settings_lr10(nvswitch_device *device, nvlink_link *link); +NvBool nvswitch_is_smbpbi_supported_lr10(nvswitch_device *device); +NvlStatus nvswitch_ctrl_set_mc_rid_table_lr10(nvswitch_device *device, NVSWITCH_SET_MC_RID_TABLE_PARAMS *p); +NvlStatus nvswitch_ctrl_get_mc_rid_table_lr10(nvswitch_device *device, NVSWITCH_GET_MC_RID_TABLE_PARAMS *p); NvlStatus nvswitch_launch_ALI_lr10(nvswitch_device *device); +NvlStatus nvswitch_ctrl_get_bios_info_lr10(nvswitch_device *device, NVSWITCH_GET_BIOS_INFO_PARAMS *p); + #endif //_LR10_H_ diff --git a/src/common/nvswitch/kernel/inc/lr10/smbpbi_lr10.h b/src/common/nvswitch/kernel/inc/lr10/smbpbi_lr10.h index 182ff653b..90666ee45 100644 --- a/src/common/nvswitch/kernel/inc/lr10/smbpbi_lr10.h +++ b/src/common/nvswitch/kernel/inc/lr10/smbpbi_lr10.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -24,6 +24,24 @@ #ifndef _SMBPBI_LR10_H_ #define _SMBPBI_LR10_H_ +NvlStatus +nvswitch_smbpbi_alloc_lr10 +( + nvswitch_device *device +); + +NvlStatus +nvswitch_smbpbi_post_init_hal_lr10 +( + nvswitch_device *device +); + +void +nvswitch_smbpbi_destroy_hal_lr10 +( + nvswitch_device *device +); + NvlStatus nvswitch_smbpbi_get_dem_num_messages_lr10 ( @@ -31,4 +49,43 @@ nvswitch_smbpbi_get_dem_num_messages_lr10 NvU8 *pMsgCount ); +NvlStatus +nvswitch_inforom_dem_load_lr10 +( + nvswitch_device *device +); + +NvlStatus +nvswitch_smbpbi_dem_load_lr10 +( + nvswitch_device *device +); + +void +nvswitch_smbpbi_send_unload_lr10 +( + nvswitch_device *device +); + +void +nvswitch_smbpbi_dem_flush_lr10 +( + nvswitch_device *device +); + +void +nvswitch_smbpbi_log_message_lr10 +( + nvswitch_device *device, + NvU32 num, + NvU32 msglen, + NvU8 *osErrorString +); + +NvlStatus +nvswitch_smbpbi_send_init_data_lr10 +( + nvswitch_device *device +); + #endif //_SMBPBI_LR10_H_ diff --git a/src/common/nvswitch/kernel/inc/ls10/clock_ls10.h b/src/common/nvswitch/kernel/inc/ls10/clock_ls10.h new file mode 100644 index 000000000..bcf620347 --- /dev/null +++ b/src/common/nvswitch/kernel/inc/ls10/clock_ls10.h @@ -0,0 +1,45 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _CLOCK_LS10_H_ +#define _CLOCK_LS10_H_ + +NvlStatus +nvswitch_init_pll_config_ls10 +( + nvswitch_device *device +); + +NvlStatus +nvswitch_init_pll_ls10 +( + nvswitch_device *device +); + +void +nvswitch_init_clock_gating_ls10 +( + nvswitch_device *device +); + +#endif //_CLOCK_LS10_H_ diff --git a/src/common/nvswitch/kernel/inc/ls10/gfw_ls10.h b/src/common/nvswitch/kernel/inc/ls10/gfw_ls10.h new file mode 100644 index 000000000..46f74eb4a --- /dev/null +++ b/src/common/nvswitch/kernel/inc/ls10/gfw_ls10.h @@ -0,0 +1,49 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _GFW_LS10_H_ +#define _GFW_LS10_H_ + + + +#include "nvswitch/ls10/dev_nvlsaw_ip.h" +#include "nvswitch/ls10/dev_therm.h" +#include "nvswitch/ls10/dev_fsp_pri.h" + +// +// Transcribed from GFW ucode r5 v1 scratch definition for LS10 +// + +#define NV_NVLSAW_SW_SCRATCH(_index) (NV_NVLSAW_SW_SCRATCH_0 + (_index)*4) +#define NV_NVLSAW_SW_BIOS_VERSION NV_NVLSAW_SW_SCRATCH(6) +#define NV_NVLSAW_SW_OEM_BIOS_VERSION NV_NVLSAW_SW_SCRATCH(7) + +//----------------------------------------------------------------------------- +#define NV_GFW_GLOBAL_BOOT_PARTITION_PROGRESS NV_THERM_I2CS_SCRATCH +#define NV_GFW_GLOBAL_BOOT_PARTITION_PROGRESS_VALUE 7:0 +#define NV_GFW_GLOBAL_BOOT_PARTITION_PROGRESS_VALUE_SUCCESS 0x000000FF + +#define NV_NVLSAW_SW_OEM_BIOS_VERSION_BOARD_ID 31:16 + +#endif //_GFW_LS10_H_ + diff --git a/src/common/nvswitch/kernel/inc/ls10/inforom_ls10.h b/src/common/nvswitch/kernel/inc/ls10/inforom_ls10.h new file mode 100644 index 000000000..07f7e79fe --- /dev/null +++ b/src/common/nvswitch/kernel/inc/ls10/inforom_ls10.h @@ -0,0 +1,114 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _INFOROM_LS10_H_ +#define _INFOROM_LS10_H_ + +NvlStatus nvswitch_inforom_nvl_log_error_event_ls10 +( + nvswitch_device *device, + void *pNvlGeneric, + void *pNvlErrorEvent, + NvBool *bDirty +); + +NvlStatus nvswitch_inforom_nvl_update_link_correctable_error_info_ls10 +( + nvswitch_device *device, + void *pNvlGeneric, + void *pData, + NvU8 linkId, + NvU8 nvliptInstance, + NvU8 localLinkIdx, + void *pNvlErrorCounts, + NvBool *bDirty +); + +void +nvswitch_initialize_oms_state_ls10 +( + nvswitch_device *device, + INFOROM_OMS_STATE *pOmsState +); + +NvBool +nvswitch_oms_get_device_disable_ls10 +( + INFOROM_OMS_STATE *pOmsState +); + +void +nvswitch_oms_set_device_disable_ls10 +( + INFOROM_OMS_STATE *pOmsState, + NvBool bForceDeviceDisable +); + +NvlStatus +nvswitch_oms_inforom_flush_ls10 +( + struct nvswitch_device *device +); + +void +nvswitch_inforom_ecc_get_total_errors_ls10 +( + nvswitch_device *device, + INFOROM_ECC_OBJECT *pEccGeneric, + NvU64 *pCorrectedTotal, + NvU64 *pUncorrectedTotal +); + +NvlStatus +nvswitch_bbx_add_sxid_ls10 +( + nvswitch_device *device, + NvU32 exceptionType, + NvU32 data0, + NvU32 data1, + NvU32 data2 +); + +NvlStatus +nvswitch_bbx_unload_ls10 +( + nvswitch_device *device +); + +NvlStatus +nvswitch_bbx_load_ls10 +( + nvswitch_device *device, + NvU64 time_ns, + NvU8 osType, + NvU32 osVersion +); + +NvlStatus +nvswitch_bbx_get_sxid_ls10 +( + nvswitch_device *device, + NVSWITCH_GET_SXIDS_PARAMS * params +); + +#endif //_INFOROM_LS10_H_ diff --git a/src/common/nvswitch/kernel/inc/ls10/ls10.h b/src/common/nvswitch/kernel/inc/ls10/ls10.h new file mode 100644 index 000000000..80cf219f7 --- /dev/null +++ b/src/common/nvswitch/kernel/inc/ls10/ls10.h @@ -0,0 +1,993 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _LS10_H_ +#define _LS10_H_ + + + +#include "export_nvswitch.h" +#include "common_nvswitch.h" + +#include "ctrl_dev_nvswitch.h" + +#include "nvswitch/ls10/dev_master.h" + +#define NVSWITCH_NUM_LINKS_LS10 64 +#define NVSWITCH_NUM_LANES_LS10 2 + +#define NVSWITCH_LINKS_PER_MINION_LS10 4 +#define NVSWITCH_LINKS_PER_NVLIPT_LS10 4 +#define NVSWITCH_LINKS_PER_NVLW_LS10 4 +#define NVSWITCH_LINKS_PER_NPG_LS10 4 + +#define NVSWITCH_NPORT_PER_NPG_LS10 NVSWITCH_LINKS_PER_NPG_LS10 + +#define NUM_PTOP_ENGINE_LS10 1 +#define NUM_FUSE_ENGINE_LS10 1 +#define NUM_GIN_ENGINE_LS10 1 +#define NUM_JTAG_ENGINE_LS10 1 + +#define NUM_PMGR_ENGINE_LS10 1 +#define NUM_SAW_ENGINE_LS10 1 +#define NUM_ROM_ENGINE_LS10 1 +#define NUM_EXTDEV_ENGINE_LS10 1 +#define NUM_PTIMER_ENGINE_LS10 1 +#define NUM_SOE_ENGINE_LS10 1 +#define NUM_SMR_ENGINE_LS10 2 +#define NUM_SE_ENGINE_LS10 1 +#define NUM_THERM_ENGINE_LS10 1 +#define NUM_XAL_ENGINE_LS10 1 +#define NUM_XAL_FUNC_ENGINE_LS10 1 +#define NUM_XTL_CONFIG_ENGINE_LS10 1 +#define NUM_XPL_ENGINE_LS10 1 +#define NUM_XTL_ENGINE_LS10 1 +#define NUM_SYSCTRL_ENGINE_LS10 1 +#define NUM_UXL_ENGINE_LS10 1 +#define NUM_GPU_PTOP_ENGINE_LS10 1 +#define NUM_PMC_ENGINE_LS10 1 +#define NUM_PBUS_ENGINE_LS10 1 +#define NUM_ROM2_ENGINE_LS10 1 +#define NUM_GPIO_ENGINE_LS10 1 +#define NUM_FSP_ENGINE_LS10 1 + +#define NUM_CLKS_SYS_ENGINE_LS10 1 +#define NUM_CLKS_SYSB_ENGINE_LS10 1 +#define NUM_CLKS_P0_ENGINE_LS10 4 +#define NUM_CLKS_P0_BCAST_ENGINE_LS10 1 +#define NUM_SAW_PM_ENGINE_LS10 1 +#define NUM_PCIE_PM_ENGINE_LS10 1 +#define NUM_PRT_PRI_HUB_ENGINE_LS10 16 +#define NUM_PRT_PRI_RS_CTRL_ENGINE_LS10 16 +#define NUM_PRT_PRI_HUB_BCAST_ENGINE_LS10 1 +#define NUM_PRT_PRI_RS_CTRL_BCAST_ENGINE_LS10 1 +#define NUM_SYS_PRI_HUB_ENGINE_LS10 1 +#define NUM_SYS_PRI_RS_CTRL_ENGINE_LS10 1 +#define NUM_SYSB_PRI_HUB_ENGINE_LS10 1 +#define NUM_SYSB_PRI_RS_CTRL_ENGINE_LS10 1 +#define NUM_PRI_MASTER_RS_ENGINE_LS10 1 + +#define NUM_NPG_ENGINE_LS10 16 +#define NUM_NPG_PERFMON_ENGINE_LS10 NUM_NPG_ENGINE_LS10 +#define NUM_NPORT_ENGINE_LS10 (NUM_NPG_ENGINE_LS10 * NVSWITCH_NPORT_PER_NPG_LS10) +#define NUM_NPORT_MULTICAST_ENGINE_LS10 NUM_NPG_ENGINE_LS10 +#define NUM_NPORT_PERFMON_ENGINE_LS10 NUM_NPORT_ENGINE_LS10 +#define NUM_NPORT_PERFMON_MULTICAST_ENGINE_LS10 NUM_NPG_ENGINE_LS10 + +#define NUM_NPG_BCAST_ENGINE_LS10 1 +#define NUM_NPG_PERFMON_BCAST_ENGINE_LS10 NUM_NPG_BCAST_ENGINE_LS10 +#define NUM_NPORT_BCAST_ENGINE_LS10 NVSWITCH_NPORT_PER_NPG_LS10 +#define NUM_NPORT_MULTICAST_BCAST_ENGINE_LS10 NUM_NPG_BCAST_ENGINE_LS10 +#define NUM_NPORT_PERFMON_BCAST_ENGINE_LS10 NUM_NPORT_BCAST_ENGINE_LS10 +#define NUM_NPORT_PERFMON_MULTICAST_BCAST_ENGINE_LS10 NUM_NPG_BCAST_ENGINE_LS10 + +#define NUM_NVLW_ENGINE_LS10 16 +#define NUM_NVLIPT_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 +#define NUM_MINION_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 +#define NUM_PLL_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 +#define NUM_CPR_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 +#define NUM_NVLW_PERFMON_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 +#define NUM_NVLIPT_SYS_PERFMON_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 +#define NUM_NVLDL_MULTICAST_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 +#define NUM_NVLTLC_MULTICAST_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 +#define NUM_NVLIPT_LNK_MULTICAST_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 +#define NUM_SYS_PERFMON_MULTICAST_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 +#define NUM_TX_PERFMON_MULTICAST_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 +#define NUM_RX_PERFMON_MULTICAST_ENGINE_LS10 NUM_NVLW_ENGINE_LS10 +#define NUM_NVLDL_ENGINE_LS10 (NUM_NVLW_ENGINE_LS10 * NVSWITCH_LINKS_PER_NVLIPT_LS10) +#define NUM_NVLTLC_ENGINE_LS10 NUM_NVLDL_ENGINE_LS10 +#define NUM_NVLIPT_LNK_ENGINE_LS10 NUM_NVLDL_ENGINE_LS10 +#define NUM_SYS_PERFMON_ENGINE_LS10 NUM_NVLDL_ENGINE_LS10 +#define NUM_TX_PERFMON_ENGINE_LS10 NUM_NVLDL_ENGINE_LS10 +#define NUM_RX_PERFMON_ENGINE_LS10 NUM_NVLDL_ENGINE_LS10 + +#define NUM_NVLW_BCAST_ENGINE_LS10 1 +#define NUM_NVLIPT_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 +#define NUM_MINION_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 +#define NUM_PLL_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 +#define NUM_CPR_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 +#define NUM_NVLW_PERFMON_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 +#define NUM_NVLIPT_SYS_PERFMON_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 +#define NUM_NVLDL_MULTICAST_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 +#define NUM_NVLTLC_MULTICAST_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 +#define NUM_NVLIPT_LNK_MULTICAST_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 +#define NUM_SYS_PERFMON_MULTICAST_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 +#define NUM_TX_PERFMON_MULTICAST_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 +#define NUM_RX_PERFMON_MULTICAST_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10 +#define NUM_NVLDL_BCAST_ENGINE_LS10 NVSWITCH_LINKS_PER_NVLIPT_LS10 +#define NUM_NVLTLC_BCAST_ENGINE_LS10 NUM_NVLDL_BCAST_ENGINE_LS10 +#define NUM_NVLIPT_LNK_BCAST_ENGINE_LS10 NUM_NVLDL_BCAST_ENGINE_LS10 +#define NUM_SYS_PERFMON_BCAST_ENGINE_LS10 NUM_NVLDL_BCAST_ENGINE_LS10 +#define NUM_TX_PERFMON_BCAST_ENGINE_LS10 NUM_NVLDL_BCAST_ENGINE_LS10 +#define NUM_RX_PERFMON_BCAST_ENGINE_LS10 NUM_NVLDL_BCAST_ENGINE_LS10 + +#define NUM_NXBAR_ENGINE_LS10 3 +#define NUM_NXBAR_PERFMON_ENGINE_LS10 NUM_NXBAR_ENGINE_LS10 +#define NUM_TILE_MULTICAST_ENGINE_LS10 NUM_NXBAR_ENGINE_LS10 +#define NUM_TILE_PERFMON_MULTICAST_ENGINE_LS10 NUM_NXBAR_ENGINE_LS10 +#define NUM_TILE_ENGINE_LS10 (12 * NUM_NXBAR_ENGINE_LS10) +#define NUM_TILE_PERFMON_ENGINE_LS10 NUM_TILE_ENGINE_LS10 +#define NUM_TILEOUT_MULTICAST_ENGINE_LS10 NUM_NXBAR_ENGINE_LS10 +#define NUM_TILEOUT_PERFMON_MULTICAST_ENGINE_LS10 NUM_NXBAR_ENGINE_LS10 +#define NUM_TILEOUT_ENGINE_LS10 NUM_TILE_ENGINE_LS10 +#define NUM_TILEOUT_PERFMON_ENGINE_LS10 NUM_TILE_ENGINE_LS10 + +#define NUM_NXBAR_BCAST_ENGINE_LS10 1 +#define NUM_NXBAR_PERFMON_BCAST_ENGINE_LS10 NUM_NXBAR_BCAST_ENGINE_LS10 +#define NUM_TILE_MULTICAST_BCAST_ENGINE_LS10 NUM_NXBAR_BCAST_ENGINE_LS10 +#define NUM_TILE_PERFMON_MULTICAST_BCAST_ENGINE_LS10 NUM_NXBAR_BCAST_ENGINE_LS10 +#define NUM_TILE_BCAST_ENGINE_LS10 12 +#define NUM_TILE_PERFMON_BCAST_ENGINE_LS10 NUM_TILE_BCAST_ENGINE_LS10 +#define NUM_TILEOUT_MULTICAST_BCAST_ENGINE_LS10 NUM_NXBAR_BCAST_ENGINE_LS10 +#define NUM_TILEOUT_PERFMON_MULTICAST_BCAST_ENGINE_LS10 NUM_NXBAR_BCAST_ENGINE_LS10 +#define NUM_TILEOUT_BCAST_ENGINE_LS10 NUM_TILE_BCAST_ENGINE_LS10 +#define NUM_TILEOUT_PERFMON_BCAST_ENGINE_LS10 NUM_TILE_BCAST_ENGINE_LS10 +#define NUM_MAX_MCFLA_SLOTS_LS10 128 + +#define NPORT_TO_LINK_LS10(_device, _npg, _nport) \ + ( \ + NVSWITCH_ASSERT((_npg < NUM_NPG_ENGINE_LS10)) \ + , \ + NVSWITCH_ASSERT((_nport < NVSWITCH_NPORT_PER_NPG_LS10)) \ + , \ + ((_npg) * NVSWITCH_NPORT_PER_NPG_LS10 + (_nport)) \ + ) + +#define NVSWITCH_NUM_LINKS_PER_NVLIPT_LS10 (NVSWITCH_NUM_LINKS_LS10/NUM_NVLIPT_ENGINE_LS10) + +#define NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LS10(_physlinknum) \ + ((_physlinknum)%NVSWITCH_NUM_LINKS_PER_NVLIPT_LS10) + +#define NVSWITCH_NVLIPT_GET_LOCAL_LINK_MASK64_LS10(_nvlipt_idx) \ + (NVBIT64(NVSWITCH_LINKS_PER_NVLIPT_LS10) - 1) << (_nvlipt_idx * NVSWITCH_LINKS_PER_NVLIPT_LS10); + +#define DMA_ADDR_WIDTH_LS10 64 + +// +// Helpful IO wrappers +// + +#define NVSWITCH_NPORT_WR32_LS10(_d, _engidx, _dev, _reg, _data) \ + NVSWITCH_ENG_WR32(_d, NPORT, , _engidx, _dev, _reg, _data) + +#define NVSWITCH_NPORT_RD32_LS10(_d, _engidx, _dev, _reg) \ + NVSWITCH_ENG_RD32(_d, NPORT, , _engidx, _dev, _reg) + +#define NVSWITCH_MINION_WR32_LS10(_d, _engidx, _dev, _reg, _data) \ + NVSWITCH_ENG_WR32(_d, MINION, , _engidx, _dev, _reg, _data) + +#define NVSWITCH_MINION_RD32_LS10(_d, _engidx, _dev, _reg) \ + NVSWITCH_ENG_RD32(_d, MINION, , _engidx, _dev, _reg) + +#define NVSWITCH_MINION_WR32_BCAST_LS10(_d, _dev, _reg, _data) \ + NVSWITCH_ENG_WR32(_d, MINION, _BCAST, 0, _dev, _reg, _data) + +#define NVSWITCH_NPG_WR32_LS10(_d, _engidx, _dev, _reg, _data) \ + NVSWITCH_ENG_WR32(_d, NPG, , _engidx, _dev, _reg, _data) + +#define NVSWITCH_NPG_RD32_LS10(_d, _engidx, _dev, _reg) \ + NVSWITCH_ENG_RD32(_d, NPG, , _engidx, _dev, _reg) + +// +// Per-chip device information +// + +#define DISCOVERY_TYPE_UNDEFINED 0 +#define DISCOVERY_TYPE_DISCOVERY 1 +#define DISCOVERY_TYPE_UNICAST 2 +#define DISCOVERY_TYPE_BROADCAST 3 + +typedef struct +{ + NvBool valid; + NvU32 initialized; + NvU32 version; + NvU32 disc_type; + union + { + struct + { + NvU32 cluster; + NvU32 cluster_id; + NvU32 discovery; // Used for top level only + } top; + struct + { + NvU32 uc_addr; + } uc; + struct + { + NvU32 bc_addr; + NvU32 mc_addr[3]; + } bc; + } info; +} ENGINE_DISCOVERY_TYPE_LS10; + +#define NVSWITCH_DECLARE_ENGINE_UC_LS10(_engine) \ + ENGINE_DISCOVERY_TYPE_LS10 eng##_engine[NUM_##_engine##_ENGINE_LS10]; + +#define NVSWITCH_DECLARE_ENGINE_LS10(_engine) \ + ENGINE_DISCOVERY_TYPE_LS10 eng##_engine[NUM_##_engine##_ENGINE_LS10]; \ + ENGINE_DISCOVERY_TYPE_LS10 eng##_engine##_BCAST[NUM_##_engine##_BCAST_ENGINE_LS10]; + +#define NVSWITCH_LIST_LS10_ENGINE_UC(_op) \ + _op(PTOP) \ + _op(FUSE) \ + _op(GIN) \ + _op(JTAG) \ + _op(PMGR) \ + _op(SAW) \ + _op(ROM) \ + _op(EXTDEV) \ + _op(PTIMER) \ + _op(SOE) \ + _op(SMR) \ + _op(SE) \ + _op(THERM) \ + _op(XAL) \ + _op(XAL_FUNC) \ + _op(XTL_CONFIG) \ + _op(XPL) \ + _op(XTL) \ + _op(UXL) \ + _op(GPU_PTOP) \ + _op(PMC) \ + _op(PBUS) \ + _op(ROM2) \ + _op(GPIO) \ + _op(FSP) \ + _op(CLKS_SYS) \ + _op(CLKS_SYSB) \ + _op(CLKS_P0) \ + _op(CLKS_P0_BCAST) \ + _op(SAW_PM) \ + _op(PCIE_PM) \ + _op(SYS_PRI_HUB) \ + _op(SYS_PRI_RS_CTRL) \ + _op(SYSB_PRI_HUB) \ + _op(SYSB_PRI_RS_CTRL) \ + _op(PRI_MASTER_RS) \ + +#define NVSWITCH_LIST_PRI_HUB_LS10_ENGINE(_op) \ + _op(PRT_PRI_HUB) \ + _op(PRT_PRI_RS_CTRL) \ + _op(PRT_PRI_HUB_BCAST) \ + _op(PRT_PRI_RS_CTRL_BCAST) \ + +#define NVSWITCH_LIST_NPG_LS10_ENGINE(_op) \ + _op(NPG) \ + _op(NPG_PERFMON) \ + _op(NPORT) \ + _op(NPORT_MULTICAST) \ + _op(NPORT_PERFMON) \ + _op(NPORT_PERFMON_MULTICAST) + +#define NVSWITCH_LIST_NVLW_LS10_ENGINE(_op) \ + _op(NVLW) \ + _op(NVLIPT) \ + _op(MINION) \ + _op(CPR) \ + _op(NVLW_PERFMON) \ + _op(NVLIPT_SYS_PERFMON) \ + _op(NVLDL_MULTICAST) \ + _op(NVLTLC_MULTICAST) \ + _op(NVLIPT_LNK_MULTICAST) \ + _op(SYS_PERFMON_MULTICAST) \ + _op(TX_PERFMON_MULTICAST) \ + _op(RX_PERFMON_MULTICAST) \ + _op(NVLDL) \ + _op(NVLTLC) \ + _op(NVLIPT_LNK) \ + _op(SYS_PERFMON) \ + _op(TX_PERFMON) \ + _op(RX_PERFMON) + +#define NVSWITCH_LIST_NXBAR_LS10_ENGINE(_op) \ + _op(NXBAR) \ + _op(NXBAR_PERFMON) \ + _op(TILE_MULTICAST) \ + _op(TILE_PERFMON_MULTICAST) \ + _op(TILE) \ + _op(TILE_PERFMON) \ + _op(TILEOUT_MULTICAST) \ + _op(TILEOUT_PERFMON_MULTICAST) \ + _op(TILEOUT) \ + _op(TILEOUT_PERFMON) + +#define NVSWITCH_LIST_LS10_ENGINE(_op) \ + NVSWITCH_LIST_NPG_LS10_ENGINE(_op) \ + NVSWITCH_LIST_NVLW_LS10_ENGINE(_op) \ + NVSWITCH_LIST_NXBAR_LS10_ENGINE(_op) + +// +// The chip-specific engine list is used to generate the code to collect +// discovered unit information and coalesce it into the data structures used by +// the common IO library (see io_nvswitch.h). +// +// The PTOP discovery table presents the information on wrappers and sub-units +// in a hierarchical manner. The top level discovery contains information +// about top level UNICAST units and IP wrappers like NPG, NVLW, and NXBAR. +// Individual units within an IP wrapper are described in discovery sub-tables. +// Each IP wrapper may have MULTICAST descriptors to allow addressing sub-units +// within a wrapper and a cluster of IP wrappers will also have a BCAST +// discovery tables, which have MULTICAST descriptors within them. +// In order to collect all the useful unit information into a single container, +// we need to pick where to find each piece within the parsed discovery table. +// Top level IP wrappers like NPG have a BCAST range to broadcast reads/writes, +// but IP sub-units like NPORT have a MULTICAST range within the BCAST IP +// wrapper to broadcast to all the sub-units in all the IP wrappers. +// So in the lists below top level IP wrappers (NPG, NVLW, and NXBAR) point +// to the _BCAST IP wrapper, but sub-unit point to the _MULTICAST range inside +// the BCAST unit (_MULTICAST_BCAST). +// +// All IP-based (0-based register manuals) engines need to be listed here to +// generate chip-specific handlers as well as in the global common list of all +// engines that have ever existed on *ANY* architecture(s) in order for them +// use common IO wrappers. +// + +#define NVSWITCH_LIST_LS10_ENGINES(_op) \ + _op(GIN, ) \ + _op(XAL, ) \ + _op(XPL, ) \ + _op(XTL, ) \ + _op(SAW, ) \ + _op(SOE, ) \ + _op(SMR, ) \ + \ + _op(PRT_PRI_HUB, _BCAST) \ + _op(PRT_PRI_RS_CTRL, _BCAST) \ + _op(SYS_PRI_HUB, ) \ + _op(SYS_PRI_RS_CTRL, ) \ + _op(SYSB_PRI_HUB, ) \ + _op(SYSB_PRI_RS_CTRL, ) \ + _op(PRI_MASTER_RS, ) \ + _op(PTIMER, ) \ + _op(CLKS_SYS, ) \ + _op(CLKS_SYSB, ) \ + _op(CLKS_P0, _BCAST) \ + \ + _op(NPG, _BCAST) \ + _op(NPORT, _MULTICAST_BCAST) \ + \ + _op(NVLW, _BCAST) \ + _op(MINION, _BCAST) \ + _op(NVLIPT, _BCAST) \ + _op(CPR, _BCAST) \ + _op(NVLIPT_LNK, _MULTICAST_BCAST) \ + _op(NVLTLC, _MULTICAST_BCAST) \ + _op(NVLDL, _MULTICAST_BCAST) \ + \ + _op(NXBAR, _BCAST) \ + _op(TILE, _MULTICAST_BCAST) \ + _op(TILEOUT, _MULTICAST_BCAST) \ + \ + _op(NPG_PERFMON, _BCAST) \ + _op(NPORT_PERFMON, _MULTICAST_BCAST) \ + \ + _op(NVLW_PERFMON, _BCAST) \ + +// +// These field #defines describe which physical fabric address bits are +// relevant to the specific remap table address check/remap operation. +// + +#define NV_INGRESS_REMAP_ADDR_PHYS_LS10 51:39 /* LR10: 46:36 */ + +#define NV_INGRESS_REMAP_ADR_OFFSET_PHYS_LS10 38:21 /* LR10: 35:20 */ +#define NV_INGRESS_REMAP_ADR_BASE_PHYS_LS10 38:21 /* LR10: 35:20 */ +#define NV_INGRESS_REMAP_ADR_LIMIT_PHYS_LS10 38:21 /* LR10: 35:20 */ + +// +// Multicast REMAP table is not indexed through the same _RAM_SEL mechanism as +// other REMAP tables, but we want to be able to use the same set of APIs for +// all the REMAP tables, so define a special RAM_SEL value for MCREMAP that +// does not conflict with the existing definitions. +// +#define NV_INGRESS_REQRSPMAPADDR_RAM_SEL_SELECT_MULTICAST_REMAPRAM (DRF_MASK(NV_INGRESS_REQRSPMAPADDR_RAM_ADDRESS) + 1) + +// +// NPORT Portstat information +// + +// +// LS10 supports CREQ0(0), DNGRD(1), ATR(2), ATSD(3), PROBE(4), RSP0(5), CREQ1(6), and RSP1(7) VCs. +// But DNGRD(1), ATR(2), ATSD(3), and PROBE(4) will be never used. +// +#define NVSWITCH_NUM_VCS_LS10 8 + +typedef struct +{ + NvU32 count; + NvU32 low; + NvU32 medium; + NvU32 high; + NvU32 panic; +} +NVSWITCH_LATENCY_BINS_LS10; + +typedef struct +{ + NvU32 count; + NvU64 start_time_nsec; + NvU64 last_read_time_nsec; + NVSWITCH_LATENCY_BINS_LS10 accum_latency[NVSWITCH_NUM_LINKS_LS10]; +} +NVSWITCH_LATENCY_VC_LS10; + +typedef struct +{ + NvU32 sample_interval_msec; + NvU64 last_visited_time_nsec; + NVSWITCH_LATENCY_VC_LS10 latency[NVSWITCH_NUM_VCS_LS10]; +} NVSWITCH_LATENCY_STATS_LS10; + +#define NV_NPORT_PORTSTAT_LS10(_block, _reg, _vc, _hi_lo) (NV_NPORT_PORTSTAT ## _block ## _reg ## _0 ## _hi_lo + \ + _vc * (NV_NPORT_PORTSTAT ## _block ## _reg ## _1 ## _hi_lo - NV_NPORT_PORTSTAT ## _block ## _reg ## _0 ## _hi_lo)) + +#define NVSWITCH_NPORT_PORTSTAT_RD32_LS10(_d, _engidx, _block, _reg, _hi_lo, _vc) \ + ( \ + NVSWITCH_ASSERT(NVSWITCH_IS_LINK_ENG_VALID_LS10(_d, NPORT, _engidx)) \ + , \ + NVSWITCH_PRINT(_d, MMIO, \ + "%s: MEM_RD NPORT_PORTSTAT[%d]: %s,%s,_%s,%s (%06x+%04x)\n", \ + __FUNCTION__, \ + _engidx, \ + #_block, #_reg, #_vc, #_hi_lo, \ + NVSWITCH_GET_ENG(_d, NPORT, , _engidx), \ + NV_NPORT_PORTSTAT_LS10(_block, _reg, _vc, _hi_lo)) \ + , \ + nvswitch_reg_read_32(_d, \ + NVSWITCH_GET_ENG(_d, NPORT, , _engidx) + \ + NV_NPORT_PORTSTAT_LS10(_block, _reg, _vc, _hi_lo)) \ + ); \ + ((void)(_d)) + +#define NVSWITCH_PORTSTAT_BCAST_WR32_LS10(_d, _block, _reg, _idx, _data) \ + { \ + NVSWITCH_PRINT(_d, MMIO, \ + "%s: BCAST_WR NPORT_PORTSTAT: %s,%s (%06x+%04x) 0x%08x\n", \ + __FUNCTION__, \ + #_block, #_reg, \ + NVSWITCH_GET_ENG(_d, NPORT, _BCAST, 0), \ + NV_NPORT_PORTSTAT_LS10(_block, _reg, _idx, ), _data); \ + NVSWITCH_OFF_WR32(_d, \ + NVSWITCH_GET_ENG(_d, NPORT, _BCAST, 0) + \ + NV_NPORT_PORTSTAT_LS10(_block, _reg, _idx, ), _data); \ + } + +#define NVSWITCH_DEFERRED_LINK_STATE_CHECK_INTERVAL_NS (10 * NVSWITCH_INTERVAL_1SEC_IN_NS) +#define NVSWITCH_DEFERRED_FAULT_UP_CHECK_INTERVAL_NS (10 * NVSWITCH_INTERVAL_1MSEC_IN_NS) + +// Struct used for passing around error masks in error handling functions +typedef struct +{ + NvU32 dl; + NvU32 tlcRx0; + NvU32 tlcRx0Injected; + NvU32 tlcRx1; + NvU32 tlcRx1Injected; + NvU32 liptLnk; + NvU32 liptLnkInjected; +} NVLINK_LINK_ERROR_INFO_ERR_MASKS, *PNVLINK_LINK_ERROR_INFO_ERR_MASKS; + +typedef struct +{ + NvBool bLinkErrorsCallBackEnabled; + NvBool bLinkStateCallBackEnabled; + + NVLINK_LINK_ERROR_INFO_ERR_MASKS fatalIntrMask; + NVLINK_LINK_ERROR_INFO_ERR_MASKS nonFatalIntrMask; +} NVLINK_LINK_ERROR_REPORTING; + +typedef struct +{ + struct + { + NVSWITCH_ENGINE_DESCRIPTOR_TYPE common[NVSWITCH_ENGINE_ID_SIZE]; + } io; + + NVSWITCH_LIST_LS10_ENGINE_UC(NVSWITCH_DECLARE_ENGINE_UC_LS10) + NVSWITCH_LIST_PRI_HUB_LS10_ENGINE(NVSWITCH_DECLARE_ENGINE_UC_LS10) + NVSWITCH_LIST_LS10_ENGINE(NVSWITCH_DECLARE_ENGINE_LS10) + + // Interrupts + NvU32 intr_minion_dest; + + // VBIOS configuration Data + NVSWITCH_BIOS_NVLINK_CONFIG bios_config; + + // GPIO + const NVSWITCH_GPIO_INFO *gpio_pin; + NvU32 gpio_pin_size; + + // Latency statistics + NVSWITCH_LATENCY_STATS_LS10 *latency_stats; + + // External TDIODE info + NVSWITCH_TDIODE_INFO_TYPE tdiode; + + // + // Book-keep interrupt masks to restore them after reset. + // Note: There is no need to book-keep interrupt masks for NVLink units like + // DL, MINION, TLC etc. because NVLink init routines would setup them. + // + struct + { + NVSWITCH_INTERRUPT_MASK route; + NVSWITCH_INTERRUPT_MASK ingress[2]; + NVSWITCH_INTERRUPT_MASK egress[2]; + NVSWITCH_INTERRUPT_MASK tstate; + NVSWITCH_INTERRUPT_MASK sourcetrack; + NVSWITCH_INTERRUPT_MASK mc_tstate; + NVSWITCH_INTERRUPT_MASK red_tstate; + NVSWITCH_INTERRUPT_MASK tile; + NVSWITCH_INTERRUPT_MASK tileout; + } intr_mask; + + // Ganged Link table + NvU64 *ganged_link_table; + + //NVSWITCH Minion core + NvU32 minionEngArch; + + NvBool riscvManifestBoot; + + // Nvlink error reporting management + NVLINK_LINK_ERROR_REPORTING deferredLinkErrors[NVSWITCH_NUM_LINKS_LS10]; + +} ls10_device; + +// +// Helpful IO wrappers +// + +#define NVSWITCH_GET_CHIP_DEVICE_LS10(_device) \ + ( \ + ((_device)->chip_id == NV_PMC_BOOT_42_CHIP_ID_LS10) ? \ + ((ls10_device *) _device->chip_device) : \ + NULL \ + ) + +#define NVSWITCH_ENG_VALID_LS10(_d, _eng, _engidx) \ + ( \ + ((_engidx < NUM_##_eng##_ENGINE_LS10) && \ + (NVSWITCH_GET_CHIP_DEVICE_LS10(_d)->eng##_eng[_engidx].valid)) ? \ + NV_TRUE : NV_FALSE \ + ) + +#define NVSWITCH_ENG_WR32_LS10(_d, _eng, _bcast, _engidx, _dev, _reg, _data) \ + NVSWITCH_ENG_WR32(_d, _eng, _bcast, _engidx, _dev, _reg, _data) + +#define NVSWITCH_ENG_RD32_LS10(_d, _eng, _engidx, _dev, _reg) \ + NVSWITCH_ENG_RD32(_d, _eng, , _engidx, _dev, _reg) + +#define NVSWITCH_BCAST_WR32_LS10(_d, _eng, _dev, _reg, _data) \ + NVSWITCH_ENG_WR32(_d, _eng, _BCAST, 0, _dev, _reg, _data) + +#define NVSWITCH_BCAST_RD32_LS10(_d, _eng, _dev, _reg) \ + NVSWITCH_ENG_RD32(_d, _eng, _BCAST, 0, _dev, _reg) + +#define NVSWITCH_SOE_WR32_LS10(_d, _instance, _dev, _reg, _data) \ + NVSWITCH_ENG_WR32(_d, SOE, , _instance, _dev, _reg, _data) + +#define NVSWITCH_SOE_RD32_LS10(_d, _instance, _dev, _reg) \ + NVSWITCH_ENG_RD32(_d, SOE, , _instance, _dev, _reg) + +#define NVSWITCH_NPORT_BCAST_WR32_LS10(_d, _dev, _reg, _data) \ + NVSWITCH_ENG_WR32(_d, NPORT, _BCAST, 0, _dev, _reg, _data) + +#define NVSWITCH_SAW_WR32_LS10(_d, _dev, _reg, _data) \ + NVSWITCH_ENG_WR32(_d, SAW, , 0, _dev, _reg, _data) + +#define NVSWITCH_SAW_RD32_LS10(_d, _dev, _reg) \ + NVSWITCH_ENG_RD32(_d, SAW, , 0, _dev, _reg) + +#define NVSWITCH_NPORT_MC_BCAST_WR32_LS10(_d, _dev, _reg, _data) \ + NVSWITCH_BCAST_WR32_LS10(_d, NPORT, _dev, _reg, _data) + +// +// Tile Column consists of 12 Tile blocks and 11 (really 12) Tileout blocks. +// + +#define NUM_NXBAR_TILES_PER_TC_LS10 12 +#define NUM_NXBAR_TILEOUTS_PER_TC_LS10 12 + +#define TILE_INDEX_LS10(_device, _nxbar, _tile) \ + ( \ + NVSWITCH_ASSERT((_nxbar < NUM_NXBAR_ENGINE_LS10)) \ + , \ + NVSWITCH_ASSERT((_tile < NUM_NXBAR_TILES_PER_TC_LS10)) \ + , \ + ((_nxbar) * NUM_NXBAR_TILES_PER_TC_LS10 + (_tile)) \ + ) + +#define NVSWITCH_TILE_RD32(_d, _engidx, _dev, _reg) \ + NVSWITCH_ENG_RD32(_d, TILE, , _engidx, _dev, _reg) + +#define NVSWITCH_TILE_WR32(_d, _engidx, _dev, _reg, _data) \ + NVSWITCH_ENG_WR32(_d, TILE, , _engidx, _dev, _reg, _data) + +#define NVSWITCH_TILEOUT_RD32(_d, _engidx, _dev, _reg) \ + NVSWITCH_ENG_RD32(_d, TILEOUT, , _engidx, _dev, _reg) + +#define NVSWITCH_TILEOUT_WR32(_d, _engidx, _dev, _reg, _data) \ + NVSWITCH_ENG_WR32(_d, TILEOUT, , _engidx, _dev, _reg, _data) + +// +// Per link register access routines +// LINK_* MMIO wrappers are used to reference per-link engine instances +// + +#define NVSWITCH_IS_LINK_ENG_VALID_LS10(_d, _eng, _linknum) \ + NVSWITCH_IS_LINK_ENG_VALID(_d, _linknum, _eng) + +#define NVSWITCH_LINK_OFFSET_LS10(_d, _physlinknum, _eng, _dev, _reg) \ + NVSWITCH_LINK_OFFSET(_d, _physlinknum, _eng, _dev, _reg) + +#define NVSWITCH_LINK_WR32_LS10(_d, _physlinknum, _eng, _dev, _reg, _data) \ + NVSWITCH_LINK_WR32(_d, _physlinknum, _eng, _dev, _reg, _data) + +#define NVSWITCH_LINK_RD32_LS10(_d, _physlinknum, _eng, _dev, _reg) \ + NVSWITCH_LINK_RD32(_d, _physlinknum, _eng, _dev, _reg) + +#define NVSWITCH_LINK_WR32_IDX_LS10(_d, _physlinknum, _eng, _dev, _reg, _idx, _data) \ + NVSWITCH_LINK_WR32_IDX(_d, _physlinknum, _eng, _dev, _reg, _idx, _data) + +#define NVSWITCH_LINK_RD32_IDX_LS10(_d, _physlinknum, _eng, _dev, _reg, _idx) \ + NVSWITCH_LINK_RD32_IDX(_d, _physlinknum, _eng, _dev, _reg, _idx) + +#define NVSWITCH_MINION_LINK_WR32_LS10(_d, _physlinknum, _dev, _reg, _data) \ + NVSWITCH_LINK_WR32(_d, _physlinknum, MINION, _dev, _reg, _data) + +#define NVSWITCH_MINION_LINK_RD32_LS10(_d, _physlinknum, _dev, _reg) \ + NVSWITCH_LINK_RD32(_d, _physlinknum, MINION, _dev, _reg) + +// +// MINION +// + +typedef const struct +{ + NvU32 osCodeOffset; + NvU32 osCodeSize; + NvU32 osDataOffset; + NvU32 osDataSize; + NvU32 numApps; + NvU32 appCodeStart; + NvU32 appDataStart; + NvU32 codeOffset; + NvU32 codeSize; + NvU32 dataOffset; + NvU32 dataSize; +} FALCON_UCODE_HDR_INFO_LS10, *PFALCON_UCODE_HDR_INFO_LS10; + +typedef const struct +{ + // + // Version 1 + // Version 2 + // Vesrion 3 = for Partition boot + // Vesrion 4 = for eb riscv boot + // + NvU32 version; // structure version + NvU32 bootloaderOffset; + NvU32 bootloaderSize; + NvU32 bootloaderParamOffset; + NvU32 bootloaderParamSize; + NvU32 riscvElfOffset; + NvU32 riscvElfSize; + NvU32 appVersion; // Changelist number associated with the image + // + // Manifest contains information about Monitor and it is + // input to BR + // + NvU32 manifestOffset; + NvU32 manifestSize; + // + // Monitor Data offset within RISCV image and size + // + NvU32 monitorDataOffset; + NvU32 monitorDataSize; + // + // Monitor Code offset withtin RISCV image and size + // + NvU32 monitorCodeOffset; + NvU32 monitorCodeSize; + NvU32 bIsMonitorEnabled; + // + // Swbrom Code offset within RISCV image and size + // + NvU32 swbromCodeOffset; + NvU32 swbromCodeSize; + // + // Swbrom Data offset within RISCV image and size + // + NvU32 swbromDataOffset; + NvU32 swbromDataSize; +} RISCV_UCODE_HDR_INFO_LS10, *PRISCV_UCODE_HDR_INFO_LS10; + +// +// HAL functions shared by LR10 and used by LS10 +// + +#define nvswitch_is_link_valid_ls10 nvswitch_is_link_valid_lr10 +#define nvswitch_is_link_in_use_ls10 nvswitch_is_link_in_use_lr10 + +#define nvswitch_initialize_device_state_ls10 nvswitch_initialize_device_state_lr10 +#define nvswitch_deassert_link_reset_ls10 nvswitch_deassert_link_reset_lr10 +#define nvswitch_determine_platform_ls10 nvswitch_determine_platform_lr10 +#define nvswitch_get_swap_clk_default_ls10 nvswitch_get_swap_clk_default_lr10 +#define nvswitch_post_init_device_setup_ls10 nvswitch_post_init_device_setup_lr10 +#define nvswitch_set_training_error_info_ls10 nvswitch_set_training_error_info_lr10 +#define nvswitch_init_scratch_ls10 nvswitch_init_scratch_lr10 +#define nvswitch_hw_counter_shutdown_ls10 nvswitch_hw_counter_shutdown_lr10 +#define nvswitch_hw_counter_read_counter_ls10 nvswitch_hw_counter_read_counter_lr10 + +#define nvswitch_ecc_writeback_task_ls10 nvswitch_ecc_writeback_task_lr10 +#define nvswitch_ctrl_get_routing_id_ls10 nvswitch_ctrl_get_routing_id_lr10 +#define nvswitch_ctrl_set_routing_id_valid_ls10 nvswitch_ctrl_set_routing_id_valid_lr10 +#define nvswitch_ctrl_set_routing_id_ls10 nvswitch_ctrl_set_routing_id_lr10 +#define nvswitch_ctrl_set_routing_lan_ls10 nvswitch_ctrl_set_routing_lan_lr10 +#define nvswitch_ctrl_get_routing_lan_ls10 nvswitch_ctrl_get_routing_lan_lr10 +#define nvswitch_ctrl_set_routing_lan_valid_ls10 nvswitch_ctrl_set_routing_lan_valid_lr10 +#define nvswitch_ctrl_set_ingress_request_table_ls10 nvswitch_ctrl_set_ingress_request_table_lr10 +#define nvswitch_ctrl_get_ingress_request_table_ls10 nvswitch_ctrl_get_ingress_request_table_lr10 +#define nvswitch_ctrl_set_ingress_request_valid_ls10 nvswitch_ctrl_set_ingress_request_valid_lr10 +#define nvswitch_ctrl_get_ingress_response_table_ls10 nvswitch_ctrl_get_ingress_response_table_lr10 +#define nvswitch_ctrl_set_ingress_response_table_ls10 nvswitch_ctrl_set_ingress_response_table_lr10 + +#define nvswitch_ctrl_get_info_ls10 nvswitch_ctrl_get_info_lr10 + +#define nvswitch_ctrl_set_switch_port_config_ls10 nvswitch_ctrl_set_switch_port_config_lr10 +#define nvswitch_ctrl_get_fom_values_ls10 nvswitch_ctrl_get_fom_values_lr10 +#define nvswitch_ctrl_get_throughput_counters_ls10 nvswitch_ctrl_get_throughput_counters_lr10 + +#define nvswitch_save_nvlink_seed_data_from_minion_to_inforom_ls10 nvswitch_save_nvlink_seed_data_from_minion_to_inforom_lr10 +#define nvswitch_store_seed_data_from_inforom_to_corelib_ls10 nvswitch_store_seed_data_from_inforom_to_corelib_lr10 +#define nvswitch_corelib_clear_link_state_ls10 nvswitch_corelib_clear_link_state_lr10 + +#define nvswitch_read_oob_blacklist_state_ls10 nvswitch_read_oob_blacklist_state_lr10 + +#define nvswitch_corelib_add_link_ls10 nvswitch_corelib_add_link_lr10 +#define nvswitch_corelib_remove_link_ls10 nvswitch_corelib_remove_link_lr10 +#define nvswitch_corelib_set_tl_link_mode_ls10 nvswitch_corelib_set_tl_link_mode_lr10 +#define nvswitch_corelib_set_rx_mode_ls10 nvswitch_corelib_set_rx_mode_lr10 +#define nvswitch_corelib_set_rx_detect_ls10 nvswitch_corelib_set_rx_detect_lr10 +#define nvswitch_corelib_write_discovery_token_ls10 nvswitch_corelib_write_discovery_token_lr10 +#define nvswitch_corelib_read_discovery_token_ls10 nvswitch_corelib_read_discovery_token_lr10 + +#define nvswitch_inforom_nvl_get_minion_data_ls10 nvswitch_inforom_nvl_get_minion_data_lr10 +#define nvswitch_inforom_nvl_set_minion_data_ls10 nvswitch_inforom_nvl_set_minion_data_lr10 +#define nvswitch_inforom_nvl_get_max_correctable_error_rate_ls10 nvswitch_inforom_nvl_get_max_correctable_error_rate_lr10 +#define nvswitch_inforom_nvl_get_errors_ls10 nvswitch_inforom_nvl_get_errors_lr10 +#define nvswitch_inforom_ecc_log_error_event_ls10 nvswitch_inforom_ecc_log_error_event_lr10 +#define nvswitch_inforom_ecc_get_errors_ls10 nvswitch_inforom_ecc_get_errors_lr10 +#define nvswitch_inforom_bbx_get_sxid_ls10 nvswitch_inforom_bbx_get_sxid_lr10 + +#define nvswitch_vbios_read_structure_ls10 nvswitch_vbios_read_structure_lr10 + +#define nvswitch_setup_system_registers_ls10 nvswitch_setup_system_registers_lr10 + +#define nvswitch_minion_get_initoptimize_status_ls10 nvswitch_minion_get_initoptimize_status_lr10 + +#define nvswitch_poll_sublink_state_ls10 nvswitch_poll_sublink_state_lr10 +#define nvswitch_setup_link_loopback_mode_ls10 nvswitch_setup_link_loopback_mode_lr10 + +#define nvswitch_link_lane_reversed_ls10 nvswitch_link_lane_reversed_lr10 +#define nvswitch_request_tl_link_state_ls10 nvswitch_request_tl_link_state_lr10 + +#define nvswitch_i2c_get_port_info_ls10 nvswitch_i2c_get_port_info_lr10 +#define nvswitch_i2c_set_hw_speed_mode_ls10 nvswitch_i2c_set_hw_speed_mode_lr10 + +#define nvswitch_ctrl_get_err_info_ls10 nvswitch_ctrl_get_err_info_lr10 + +NvlStatus nvswitch_ctrl_get_err_info_lr10(nvswitch_device *device, NVSWITCH_NVLINK_GET_ERR_INFO_PARAMS *ret); + +NvBool nvswitch_is_link_valid_lr10(nvswitch_device *device, NvU32 link_id); +NvBool nvswitch_is_link_in_use_lr10(nvswitch_device *device, NvU32 link_id); + +NvlStatus nvswitch_initialize_device_state_lr10(nvswitch_device *device); +NvlStatus nvswitch_deassert_link_reset_lr10(nvswitch_device *device, nvlink_link *link); +void nvswitch_determine_platform_lr10(nvswitch_device *device); +NvU32 nvswitch_get_swap_clk_default_lr10(nvswitch_device *device); +NvlStatus nvswitch_post_init_device_setup_lr10(nvswitch_device *device); +NvlStatus nvswitch_set_training_error_info_lr10(nvswitch_device *device, NVSWITCH_SET_TRAINING_ERROR_INFO_PARAMS *pLinkTrainingErrorInfoParams); +void nvswitch_init_scratch_lr10(nvswitch_device *device); +void nvswitch_hw_counter_shutdown_lr10(nvswitch_device *device); +NvU64 nvswitch_hw_counter_read_counter_lr10(nvswitch_device *device); + +void nvswitch_ecc_writeback_task_lr10(nvswitch_device *device); +NvlStatus nvswitch_ctrl_get_routing_id_lr10(nvswitch_device *device, NVSWITCH_GET_ROUTING_ID_PARAMS *params); +NvlStatus nvswitch_ctrl_set_routing_id_valid_lr10(nvswitch_device *device, NVSWITCH_SET_ROUTING_ID_VALID *p); +NvlStatus nvswitch_ctrl_set_routing_id_lr10(nvswitch_device *device, NVSWITCH_SET_ROUTING_ID *p); +NvlStatus nvswitch_ctrl_set_routing_lan_lr10(nvswitch_device *device, NVSWITCH_SET_ROUTING_LAN *p); +NvlStatus nvswitch_ctrl_get_routing_lan_lr10(nvswitch_device *device, NVSWITCH_GET_ROUTING_LAN_PARAMS *params); +NvlStatus nvswitch_ctrl_set_routing_lan_valid_lr10(nvswitch_device *device, NVSWITCH_SET_ROUTING_LAN_VALID *p); +NvlStatus nvswitch_ctrl_set_ingress_request_table_lr10(nvswitch_device *device, NVSWITCH_SET_INGRESS_REQUEST_TABLE *p); +NvlStatus nvswitch_ctrl_get_ingress_request_table_lr10(nvswitch_device *device, NVSWITCH_GET_INGRESS_REQUEST_TABLE_PARAMS *params); +NvlStatus nvswitch_ctrl_set_ingress_request_valid_lr10(nvswitch_device *device, NVSWITCH_SET_INGRESS_REQUEST_VALID *p); +NvlStatus nvswitch_ctrl_get_ingress_response_table_lr10(nvswitch_device *device, NVSWITCH_GET_INGRESS_RESPONSE_TABLE_PARAMS *params); +NvlStatus nvswitch_ctrl_set_ingress_response_table_lr10(nvswitch_device *device, NVSWITCH_SET_INGRESS_RESPONSE_TABLE *p); + +NvlStatus nvswitch_ctrl_get_nvlink_status_lr10(nvswitch_device *device, NVSWITCH_GET_NVLINK_STATUS_PARAMS *ret); +NvlStatus nvswitch_ctrl_get_nvlink_status_ls10(nvswitch_device *device, NVSWITCH_GET_NVLINK_STATUS_PARAMS *ret); + +NvlStatus nvswitch_ctrl_get_info_lr10(nvswitch_device *device, NVSWITCH_GET_INFO *p); + +NvlStatus nvswitch_ctrl_set_switch_port_config_lr10(nvswitch_device *device, NVSWITCH_SET_SWITCH_PORT_CONFIG *p); +NvlStatus nvswitch_ctrl_get_fom_values_lr10(nvswitch_device *device, NVSWITCH_GET_FOM_VALUES_PARAMS *p); +NvlStatus nvswitch_ctrl_get_throughput_counters_lr10(nvswitch_device *device, NVSWITCH_GET_THROUGHPUT_COUNTERS_PARAMS *p); +void nvswitch_save_nvlink_seed_data_from_minion_to_inforom_lr10(nvswitch_device *device, NvU32 linkId); +void nvswitch_store_seed_data_from_inforom_to_corelib_lr10(nvswitch_device *device); +NvlStatus nvswitch_read_oob_blacklist_state_lr10(nvswitch_device *device); + +NvlStatus nvswitch_corelib_add_link_lr10(nvlink_link *link); +NvlStatus nvswitch_corelib_remove_link_lr10(nvlink_link *link); +NvlStatus nvswitch_corelib_get_dl_link_mode_lr10(nvlink_link *link, NvU64 *mode); +NvlStatus nvswitch_corelib_set_tl_link_mode_lr10(nvlink_link *link, NvU64 mode, NvU32 flags); +NvlStatus nvswitch_corelib_get_tx_mode_lr10(nvlink_link *link, NvU64 *mode, NvU32 *subMode); +NvlStatus nvswitch_corelib_set_rx_mode_lr10(nvlink_link *link, NvU64 mode, NvU32 flags); +NvlStatus nvswitch_corelib_get_rx_mode_lr10(nvlink_link *link, NvU64 *mode, NvU32 *subMode); +NvlStatus nvswitch_corelib_set_rx_detect_lr10(nvlink_link *link, NvU32 flags); +NvlStatus nvswitch_corelib_write_discovery_token_lr10(nvlink_link *link, NvU64 token); +NvlStatus nvswitch_corelib_read_discovery_token_lr10(nvlink_link *link, NvU64 *token); +NvlStatus nvswitch_corelib_set_dl_link_mode_lr10(nvlink_link *link, NvU64 mode, NvU32 flags); +NvlStatus nvswitch_corelib_set_tx_mode_lr10(nvlink_link *link, NvU64 mode, NvU32 flags); +NvlStatus nvswitch_corelib_get_tl_link_mode_lr10(nvlink_link *link, NvU64 *mode); +void nvswitch_init_buffer_ready_lr10(nvswitch_device *device, nvlink_link *link, NvBool bNportBufferReady); + +NvlStatus nvswitch_inforom_nvl_get_minion_data_lr10(nvswitch_device *device, void *pNvlGeneric, NvU8 linkId, NvU32 *seedData); +NvlStatus nvswitch_inforom_nvl_set_minion_data_lr10(nvswitch_device *device, void *pNvlGeneric, NvU8 linkId, NvU32 *seedData, NvU32 size, NvBool *bDirty); +NvlStatus nvswitch_inforom_nvl_get_max_correctable_error_rate_lr10(nvswitch_device *device, NVSWITCH_GET_NVLINK_MAX_CORRECTABLE_ERROR_RATES_PARAMS *params); +NvlStatus nvswitch_inforom_nvl_get_errors_lr10(nvswitch_device *device, NVSWITCH_GET_NVLINK_ERROR_COUNTS_PARAMS *params); +NvlStatus nvswitch_inforom_ecc_log_error_event_lr10(nvswitch_device *device, INFOROM_ECC_OBJECT *pEccGeneric, INFOROM_NVS_ECC_ERROR_EVENT *err_event); +NvlStatus nvswitch_inforom_ecc_get_errors_lr10(nvswitch_device *device, NVSWITCH_GET_ECC_ERROR_COUNTS_PARAMS *params); +NvlStatus nvswitch_inforom_bbx_get_sxid_lr10(nvswitch_device *device, NVSWITCH_GET_SXIDS_PARAMS *params); + +void nvswitch_init_dlpl_interrupts_lr10(nvlink_link *link); + +NvlStatus nvswitch_vbios_read_structure_lr10(nvswitch_device *device, void *structure, NvU32 offset, NvU32 *ppacked_size, const char *format); + +NvlStatus nvswitch_setup_system_registers_lr10(nvswitch_device *device); + +NvlStatus nvswitch_minion_get_initoptimize_status_lr10(nvswitch_device *device, NvU32 linkId); + +NvlStatus nvswitch_poll_sublink_state_lr10(nvswitch_device *device, nvlink_link *link); +void nvswitch_setup_link_loopback_mode_lr10(nvswitch_device *device, NvU32 linkNumber); + +NvBool nvswitch_link_lane_reversed_lr10(nvswitch_device *device, NvU32 linkId); +void nvswitch_store_topology_information_lr10(nvswitch_device *device, nvlink_link *link); + +NvlStatus nvswitch_request_tl_link_state_lr10(nvlink_link *link, NvU32 tlLinkState, NvBool bSync); +NvlStatus nvswitch_wait_for_tl_request_ready_lr10(nvlink_link *link); + +NvlStatus nvswitch_parse_bios_image_lr10(nvswitch_device *device); +NvU32 nvswitch_i2c_get_port_info_lr10(nvswitch_device *device, NvU32 port); +void nvswitch_i2c_set_hw_speed_mode_lr10(nvswitch_device *device, NvU32 port, NvU32 speedMode); +NvlStatus nvswitch_ctrl_i2c_indexed_lr10(nvswitch_device *device, NVSWITCH_CTRL_I2C_INDEXED_PARAMS *pParams); +void nvswitch_corelib_clear_link_state_lr10(nvlink_link *link); + +// +// Internal function declarations +// + +NvlStatus nvswitch_corelib_set_dl_link_mode_ls10(nvlink_link *link, NvU64 mode, NvU32 flags); +NvlStatus nvswitch_corelib_set_tx_mode_ls10(nvlink_link *link, NvU64 mode, NvU32 flags); +void nvswitch_init_lpwr_regs_ls10(nvlink_link *link); + +NvlStatus nvswitch_minion_service_falcon_interrupts_ls10(nvswitch_device *device, NvU32 instance); + +NvlStatus nvswitch_device_discovery_ls10(nvswitch_device *device, NvU32 discovery_offset); +void nvswitch_filter_discovery_ls10(nvswitch_device *device); +NvlStatus nvswitch_process_discovery_ls10(nvswitch_device *device); +void nvswitch_lib_enable_interrupts_ls10(nvswitch_device *device); +void nvswitch_lib_disable_interrupts_ls10(nvswitch_device *device); +NvlStatus nvswitch_lib_service_interrupts_ls10(nvswitch_device *device); +NvlStatus nvswitch_lib_check_interrupts_ls10(nvswitch_device *device); +void nvswitch_initialize_interrupt_tree_ls10(nvswitch_device *device); +void nvswitch_corelib_training_complete_ls10(nvlink_link *link); +NvlStatus nvswitch_init_nport_ls10(nvswitch_device *device); +NvlStatus nvswitch_corelib_get_rx_detect_ls10(nvlink_link *link); +void nvswitch_reset_persistent_link_hw_state_ls10(nvswitch_device *device, NvU32 linkNumber); +NvlStatus nvswitch_minion_get_rxdet_status_ls10(nvswitch_device *device, NvU32 linkId); +NvlStatus nvswitch_minion_restore_seed_data_ls10(nvswitch_device *device, NvU32 linkId, NvU32 *seedData); +NvlStatus nvswitch_minion_set_sim_mode_ls10(nvswitch_device *device, nvlink_link *link); +NvlStatus nvswitch_minion_set_smf_settings_ls10(nvswitch_device *device, nvlink_link *link); +NvlStatus nvswitch_minion_select_uphy_tables_ls10(nvswitch_device *device, nvlink_link *link); +NvlStatus nvswitch_set_training_mode_ls10(nvswitch_device *device); +NvlStatus nvswitch_corelib_get_tl_link_mode_ls10(nvlink_link *link, NvU64 *mode); +NvU32 nvswitch_get_sublink_width_ls10(nvswitch_device *device,NvU32 linkNumber); +NvlStatus nvswitch_parse_bios_image_ls10(nvswitch_device *device); +NvBool nvswitch_is_link_in_reset_ls10(nvswitch_device *device, nvlink_link *link); +void nvswitch_corelib_get_uphy_load_ls10(nvlink_link *link, NvBool *bUnlocked); +NvlStatus nvswitch_ctrl_get_nvlink_lp_counters_ls10(nvswitch_device *device, NVSWITCH_GET_NVLINK_LP_COUNTERS_PARAMS *params); +void nvswitch_init_buffer_ready_ls10(nvswitch_device *device, nvlink_link *link, NvBool bNportBufferReady); +void nvswitch_apply_recal_settings_ls10(nvswitch_device *device, nvlink_link *link); +NvlStatus nvswitch_corelib_get_dl_link_mode_ls10(nvlink_link *link, NvU64 *mode); +NvlStatus nvswitch_corelib_get_tx_mode_ls10(nvlink_link *link, NvU64 *mode, NvU32 *subMode); +NvlStatus nvswitch_corelib_get_rx_mode_ls10(nvlink_link *link, NvU64 *mode, NvU32 *subMode); +NvlStatus nvswitch_ctrl_get_sw_info_ls10(nvswitch_device *device, NVSWITCH_GET_SW_INFO_PARAMS *p); +NvlStatus nvswitch_launch_ALI_link_training_ls10(nvswitch_device *device, nvlink_link *link, NvBool bSync); +NvlStatus nvswitch_service_nvldl_fatal_link_ls10(nvswitch_device *device, NvU32 nvliptInstance, NvU32 link); +NvlStatus nvswitch_ctrl_inband_send_data_ls10(nvswitch_device *device, NVSWITCH_INBAND_SEND_DATA_PARAMS *p); +NvlStatus nvswitch_ctrl_inband_read_data_ls10(nvswitch_device *device, NVSWITCH_INBAND_READ_DATA_PARAMS *p); +void nvswitch_send_inband_nack_ls10(nvswitch_device *device, NvU32 *msghdr, NvU32 linkId); +NvU32 nvswitch_get_max_persistent_message_count_ls10(nvswitch_device *device); +NvlStatus nvswitch_service_minion_link_ls10(nvswitch_device *device, NvU32 nvliptInstance); +void nvswitch_apply_recal_settings_ls10(nvswitch_device *device, nvlink_link *link); +void nvswitch_store_topology_information_ls10(nvswitch_device *device, nvlink_link *link); +NvlStatus nvswitch_ctrl_i2c_indexed_ls10(nvswitch_device *device, NVSWITCH_CTRL_I2C_INDEXED_PARAMS *pParams); +NvBool nvswitch_i2c_is_device_access_allowed_ls10(nvswitch_device *device, NvU32 port, NvU8 addr, NvBool bIsRead); +NvlStatus nvswitch_minion_get_ali_debug_registers_ls10(nvswitch_device *device, nvlink_link *link, NVSWITCH_MINION_ALI_DEBUG_REGISTERS *params); +void nvswitch_setup_link_system_registers_ls10(nvswitch_device *device, nvlink_link *link); +void nvswitch_load_link_disable_settings_ls10(nvswitch_device *device, nvlink_link *link); +void nvswitch_execute_unilateral_link_shutdown_ls10(nvlink_link *link); + +void nvswitch_init_dlpl_interrupts_ls10(nvlink_link *link); +NvlStatus nvswitch_reset_and_drain_links_ls10(nvswitch_device *device, NvU64 link_mask); + +void nvswitch_service_minion_all_links_ls10(nvswitch_device *device); + +// +// SU generated functions +// + +NvlStatus nvswitch_nvs_top_prod_ls10(nvswitch_device *device); +NvlStatus nvswitch_apply_prod_nvlw_ls10(nvswitch_device *device); +NvlStatus nvswitch_apply_prod_nxbar_ls10(nvswitch_device *device); + +NvlStatus nvswitch_launch_ALI_ls10(nvswitch_device *device); + +NvlStatus nvswitch_ctrl_set_mc_rid_table_ls10(nvswitch_device *device, NVSWITCH_SET_MC_RID_TABLE_PARAMS *p); +NvlStatus nvswitch_ctrl_get_mc_rid_table_ls10(nvswitch_device *device, NVSWITCH_GET_MC_RID_TABLE_PARAMS *p); + +void nvswitch_init_dlpl_interrupts_ls10(nvlink_link *link); +NvlStatus nvswitch_reset_and_drain_links_ls10(nvswitch_device *device, NvU64 link_mask); + +void nvswitch_service_minion_all_links_ls10(nvswitch_device *device); + +NvBool nvswitch_is_inforom_supported_ls10(nvswitch_device *device); + +#endif //_LS10_H_ + diff --git a/src/common/nvswitch/kernel/inc/ls10/minion_ls10.h b/src/common/nvswitch/kernel/inc/ls10/minion_ls10.h new file mode 100644 index 000000000..bde66bf8a --- /dev/null +++ b/src/common/nvswitch/kernel/inc/ls10/minion_ls10.h @@ -0,0 +1,80 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _MINION_LS10_H_ +#define _MINION_LS10_H_ + +#include "ls10.h" +#include "nvlink_inband_drv_header.h" + +#define FALCON_IMEM_BLK_SIZE_BYTES_LS10 256 + +#define FALCON_CODE_HDR_OS_CODE_OFFSET_LS10 0 +#define FALCON_CODE_HDR_OS_CODE_SIZE_LS10 1 +#define FALCON_CODE_HDR_OS_DATA_OFFSET_LS10 2 +#define FALCON_CODE_HDR_OS_DATA_SIZE_LS10 3 +#define FALCON_CODE_HDR_NUM_APPS_LS10 4 +#define FALCON_CODE_HDR_APP_CODE_START_LS10 5 +#define FALCON_CODE_HDR_APP_DATA_START_LS10 ( FALCON_CODE_HDR_APP_CODE_START_LS10 + (FALCON_CODE_HDR_NUM_APPS_LS10 * 2)) +#define FALCON_CODE_HDR_CODE_OFFSET_LS10 0 +#define FALCON_CODE_HDR_CODE_SIZE_LS10 1 +#define FALCON_CODE_HDR_DATA_OFFSET_LS10 0 +#define FALCON_CODE_HDR_DATA_SIZE_LS10 1 + +#define NV_MINION_NVLINK_DL_STAT_ARGS_LANEID 15:12 +#define NV_MINION_NVLINK_DL_STAT_ARGS_ADDRS 11:0 + +// +// Inband data structure +// +typedef struct inband_send_data +{ + // Inband buffer at sender Minion + NvU8 *sendBuffer; + + // Number of bytes of data to be sent + NvU32 bufferSize; + + // Header + nvlink_inband_drv_hdr_t hdr; +} nvswitch_inband_send_data; + +// +// Internal function declarations +// +NvlStatus nvswitch_minion_get_dl_status_ls10(nvswitch_device *device, NvU32 linkId, NvU32 statusIdx, NvU32 statusArgs, NvU32 *statusData); +NvlStatus nvswitch_set_minion_initialized_ls10(nvswitch_device *device, NvU32 idx_minion, NvBool initialized); +NvBool nvswitch_is_minion_initialized_ls10(nvswitch_device *device, NvU32 idx_minion); +NvlStatus nvswitch_init_minion_ls10(nvswitch_device *device); +NvlStatus nvswitch_minion_send_command_ls10(nvswitch_device *device, NvU32 linkNumber, NvU32 command, NvU32 scratch0); +NvlStatus nvswitch_minion_riscv_get_physical_address_ls10(nvswitch_device *device,NvU32 idx_minion, NvU32 target, NvLength offset, NvU64 *pRiscvPa); +NvlStatus nvswitch_minion_set_sim_mode_ls10(nvswitch_device *device, nvlink_link *link); +NvlStatus nvswitch_minion_set_smf_settings_ls10(nvswitch_device *device, nvlink_link *link); +NvlStatus nvswitch_minion_select_uphy_tables_ls10(nvswitch_device *device, nvlink_link *link); +NvBool nvswitch_minion_is_riscv_active_ls10(nvswitch_device *device, NvU32 idx_minion); +NvlStatus nvswitch_minion_clear_dl_error_counters_ls10(nvswitch_device *device, NvU32 linkId); +NvlStatus nvswitch_minion_send_inband_data_ls10(nvswitch_device *device, NvU32 linkId, nvswitch_inband_send_data *inBandData); +void nvswitch_minion_receive_inband_data_ls10(nvswitch_device *device, NvU32 linkId); +NvlStatus nvswitch_minion_log_ali_debug_registers_ls10(nvswitch_device *device, nvlink_link *link); + +#endif //_MINION_LS10_H_ diff --git a/src/common/nvswitch/kernel/inc/ls10/minion_nvlink_defines_public_ls10.h b/src/common/nvswitch/kernel/inc/ls10/minion_nvlink_defines_public_ls10.h new file mode 100644 index 000000000..25da73164 --- /dev/null +++ b/src/common/nvswitch/kernel/inc/ls10/minion_nvlink_defines_public_ls10.h @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _MINION_NVLINK_DEFINES_PUBLIC_H_ +#define _MINION_NVLINK_DEFINES_PUBLIC_H_ + +// SUBCODES for DLCMD FAULT (uses DLCMDFAULR code) - dlCmdFault() - NVLINK_LINK_INT +typedef enum _MINION_STATUS + { + MINION_OK = 0, + MINION_ALARM_BUSY = 80, +} MINION_STATUS; + +#endif // _MINION_NVLINK_DEFINES_PUBLIC_H_ diff --git a/src/common/nvswitch/kernel/inc/ls10/multicast_ls10.h b/src/common/nvswitch/kernel/inc/ls10/multicast_ls10.h new file mode 100644 index 000000000..8d4bcc67c --- /dev/null +++ b/src/common/nvswitch/kernel/inc/ls10/multicast_ls10.h @@ -0,0 +1,128 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _MULTICAST_LS10_H_ +#define _MULTICAST_LS10_H_ + +#define NVSWITCH_MC_TCP_LIST_SIZE_LS10 NVSWITCH_NUM_LINKS_LS10 / 2 +#define NVSWITCH_MC_MAX_SPRAY_LS10 16 +#define NVSWITCH_MC_NUM_COLUMNS_LS10 6 +#define NVSWITCH_MC_NUM_COLUMN_PAIRS_LS10 NVSWITCH_MC_NUM_COLUMNS_LS10 / 2 +#define NVSWITCH_MC_PORTS_PER_COLUMN_LS10 11 +#define NVSWITCH_MC_MIN_PORTS_PER_GROUP_LS10 1 + +#define PRIMARY_REPLICA_NONE 0 +#define PRIMARY_REPLICA_EVEN 1 +#define PRIMARY_REPLICA_ODD 2 + +#define NVSWITCH_MC_INVALID 0xFF + +#define NVSWITCH_MC_NULL_PORT_LS10 0xF + +// +// Debug and trace print toggles +// To enable tracing, define NVSWITCH_MC_TRACE +// +#if defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS) +#define NVSWITCH_MC_DEBUG 1 +#endif + +typedef struct { + NvU32 column; + NvU32 port_offset; +} NVSWITCH_COLUMN_PORT_OFFSET_LS10; + +typedef struct { + NvU8 tcp; // Tile column pair + NvU8 tcpEPort; // Port index within even column + NvU8 tcpEVCHop; // VC selection + NvU8 tcpOPort; // Port index within odd column + NvU8 tcpOVCHop; // VC selection + NvU8 roundSize; // This is no longer part of the hardware structure. We retain it here + // because it is useful in various loops + NvU8 primaryReplica;// This field is not in hardware. This code uses it to + // track which port should be primary, so that it can make a pass over + // the assembled tcp directive list and adjust portFlag and + // continueRound as needed to indicate primary replica + // valid values are: + // PRIMARY_REPLICA_NONE (0b00): no primary replica in tcp + // PRIMARY_REPLICA_EVEN (0b01): even (0) port is primary replica + // PRIMARY_REPLICA_ODD (0b10): odd (1) port is primary replica + NvBool tcpEAltPath :1;// Alternative to select from odd column + NvBool tcpOAltPath :1;// Alternative to select from even column + NvBool lastRound :1;// last TCP directive of the last round in this multicast string + // could be multiple strings in case of spray + NvBool continueRound:1;// dual meaning: + // 1) if lastRound = 1 and continueRound = 1, primary replica is in + // this TCP directive and portFlag = 0/1 selects even/odd port + // 2) if lastRound = 0 there are more TCP directives for this round. + NvBool portFlag :1;// triple meaning: + // 1) if lastRound = 1 and continueRound = 1, primary replica is in + // this TCP directive and portFlag = 0/1 selects even/odd port + // 2) If the previous TCP directive was not used to select the even/odd + // port of its predecessor, and if portFlag of the previous TCP + // directive = 1, portFlag of this TCP directive = 0/1 selects + // the even/odd port of its predecessor + // 3) if the previous TCP directive's portFlag = 0, and if it was not + // used to select the even or odd port of its predecessor, this TCP + // directive's portFlag == 1, this TCP directive contains the + // primary replica, and the next TCP directive's portFlag = 0/1 + // selects the even/odd port of this TCP directive +} NVSWITCH_TCP_DIRECTIVE_LS10; + +typedef struct { + NvU8 index; + NvBool use_extended_table; + NvU8 mcpl_size; + NvU8 num_spray_groups; + NvU8 ext_ptr; + NvBool no_dyn_rsp; + NvBool ext_ptr_valid; + NvBool valid; + NVSWITCH_TCP_DIRECTIVE_LS10 directives[NVSWITCH_MC_TCP_LIST_SIZE_LS10]; + NvU8 spray_group_ptrs[NVSWITCH_MC_MAX_SPRAY_LS10]; +} NVSWITCH_MC_RID_ENTRY_LS10; + +NvlStatus nvswitch_mc_build_mcp_list_ls10(nvswitch_device *device, NvU32 *port_list, + NvU32 *ports_per_spray_string, + NvU32 *pri_replica_offsets, NvBool *replica_valid_array, + NvU8 *vchop_array, + NVSWITCH_MC_RID_ENTRY_LS10 *table_entry, + NvU32 *entries_used); + +NvlStatus nvswitch_mc_unwind_directives_ls10(nvswitch_device *device, + NVSWITCH_TCP_DIRECTIVE_LS10* directives, + NvU32 *ports, NvU8 *vc_hop, + NvU32 *ports_per_spray_group, NvU32 *replica_offset, + NvBool *replica_valid); + +NvlStatus nvswitch_mc_invalidate_mc_rid_entry_ls10(nvswitch_device *device, NvU32 port, NvU32 index, + NvBool use_extended_table, NvBool zero); + +NvlStatus nvswitch_mc_program_mc_rid_entry_ls10(nvswitch_device *device, NvU32 port, + NVSWITCH_MC_RID_ENTRY_LS10 *table_entry, + NvU32 directive_list_size); + +NvlStatus nvswitch_mc_read_mc_rid_entry_ls10(nvswitch_device *device, NvU32 port, + NVSWITCH_MC_RID_ENTRY_LS10 *table_entry); +#endif //_MULTICAST_LS10_H_ diff --git a/src/common/nvswitch/kernel/inc/ls10/pmgr_ls10.h b/src/common/nvswitch/kernel/inc/ls10/pmgr_ls10.h new file mode 100644 index 000000000..4b2d1aea8 --- /dev/null +++ b/src/common/nvswitch/kernel/inc/ls10/pmgr_ls10.h @@ -0,0 +1,68 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _PMGR_LS10_H_ +#define _PMGR_LS10_H_ + +#include "ls10.h" + +void +nvswitch_init_pmgr_ls10 +( + nvswitch_device *device +); + +void +nvswitch_init_pmgr_devices_ls10 +( + nvswitch_device *device +); + +NvU32 +nvswitch_read_physical_id_ls10 +( + nvswitch_device *device +); + +NvlStatus +nvswitch_get_rom_info_ls10 +( + nvswitch_device *device, + NVSWITCH_EEPROM_TYPE *eeprom +); + +void +nvswitch_i2c_set_hw_speed_mode_ls10 +( + nvswitch_device *device, + NvU32 port, + NvU32 speedMode +); + +NvBool +nvswitch_is_i2c_supported_ls10 +( + nvswitch_device *device +); + +#endif //_PMGR_LS10_H_ diff --git a/src/common/nvswitch/kernel/inc/ls10/smbpbi_ls10.h b/src/common/nvswitch/kernel/inc/ls10/smbpbi_ls10.h new file mode 100644 index 000000000..15843f290 --- /dev/null +++ b/src/common/nvswitch/kernel/inc/ls10/smbpbi_ls10.h @@ -0,0 +1,91 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _SMBPBI_LS10_H_ +#define _SMBPBI_LS10_H_ + +NvlStatus +nvswitch_smbpbi_alloc_ls10 +( + nvswitch_device *device +); + +NvlStatus +nvswitch_smbpbi_post_init_hal_ls10 +( + nvswitch_device *device +); + +void +nvswitch_smbpbi_destroy_hal_ls10 +( + nvswitch_device *device +); + +NvlStatus +nvswitch_smbpbi_get_dem_num_messages_ls10 +( + nvswitch_device *device, + NvU8 *pMsgCount +); + +NvlStatus +nvswitch_inforom_dem_load_ls10 +( + nvswitch_device *device +); + +NvlStatus +nvswitch_smbpbi_dem_load_ls10 +( + nvswitch_device *device +); + +void +nvswitch_smbpbi_send_unload_ls10 +( + nvswitch_device *device +); + +void +nvswitch_smbpbi_dem_flush_ls10 +( + nvswitch_device *device +); + +void +nvswitch_smbpbi_log_message_ls10 +( + nvswitch_device *device, + NvU32 num, + NvU32 msglen, + NvU8 *osErrorString +); + +NvlStatus +nvswitch_smbpbi_send_init_data_ls10 +( + nvswitch_device *device +); + +#endif //_SMBPBI_LS10_H_ diff --git a/src/common/nvswitch/kernel/inc/ls10/soe_ls10.h b/src/common/nvswitch/kernel/inc/ls10/soe_ls10.h new file mode 100644 index 000000000..53568b7f0 --- /dev/null +++ b/src/common/nvswitch/kernel/inc/ls10/soe_ls10.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _SOE_LS10_H_ +#define _SOE_LS10_H_ + +#include "ls10.h" + +// +// Functions shared with LR10 +// + +#include "rmflcncmdif_nvswitch.h" + +NvlStatus nvswitch_init_soe_ls10(nvswitch_device *device); +NvlStatus nvswitch_unload_soe_ls10(nvswitch_device *device); +NvlStatus nvswitch_soe_register_event_callbacks_ls10(nvswitch_device *device); +void nvswitch_cci_soe_callback_ls10(nvswitch_device *device, RM_FLCN_MSG *pGenMsg, + void *pParams, NvU32 seqDesc, NV_STATUS status); +NvlStatus nvswitch_set_nport_tprod_state_ls10(nvswitch_device *device, NvU32 nport); +void nvswitch_soe_unregister_events_ls10(nvswitch_device *device); +NvlStatus nvswitch_soe_register_event_callbacks_ls10(nvswitch_device *device); +NvlStatus nvswitch_soe_restore_nport_state_ls10(nvswitch_device *device, NvU32 nport); +NvlStatus nvswitch_soe_issue_nport_reset_ls10(nvswitch_device *device, NvU32 nport); + +#endif //_SOE_LS10_H_ diff --git a/src/common/nvswitch/kernel/inc/ls10/sugen_ls10.h b/src/common/nvswitch/kernel/inc/ls10/sugen_ls10.h new file mode 100644 index 000000000..e0a8eea0a --- /dev/null +++ b/src/common/nvswitch/kernel/inc/ls10/sugen_ls10.h @@ -0,0 +1,77 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _SUGEN_LS10_H_ +#define _SUGEN_LS10_H_ + + +#include "common_nvswitch.h" +#include "ls10/ls10.h" + +#include "nvswitch/ls10/dev_nvs_top.h" +#include "nvswitch/ls10/dev_pri_masterstation_ip.h" +#include "nvswitch/ls10/dev_pri_ringstation_sys_ip.h" +#include "nvswitch/ls10/dev_pri_ringstation_sysb_ip.h" +#include "nvswitch/ls10/dev_pri_ringstation_prt_ip.h" +#include "nvswitch/ls10/dev_pri_hub_sys_ip.h" +#include "nvswitch/ls10/dev_pri_hub_sysb_ip.h" +#include "nvswitch/ls10/dev_pri_hub_prt_ip.h" +#include "nvswitch/ls10/dev_nvlsaw_ip.h" +#include "nvswitch/ls10/dev_ctrl_ip.h" +#include "nvswitch/ls10/dev_timer_ip.h" +#include "nvswitch/ls10/dev_trim.h" +#include "nvswitch/ls10/dev_nv_xal_ep.h" +#include "nvswitch/ls10/dev_nv_xpl.h" +#include "nvswitch/ls10/dev_xtl_ep_pri.h" +#include "nvswitch/ls10/dev_soe_ip.h" +#include "nvswitch/ls10/dev_se_pri.h" +#include "nvswitch/ls10/dev_perf.h" +#include "nvswitch/ls10/dev_pmgr.h" +#include "nvswitch/ls10/dev_therm.h" + +// NVLW +#include "nvswitch/ls10/dev_nvlw_ip.h" +#include "nvswitch/ls10/dev_cpr_ip.h" +#include "nvswitch/ls10/dev_nvlipt_ip.h" +#include "nvswitch/ls10/dev_nvlipt_lnk_ip.h" +#include "nvswitch/ls10/dev_nvltlc_ip.h" +#include "nvswitch/ls10/dev_nvldl_ip.h" +#include "nvswitch/ls10/dev_minion_ip.h" + +// NPG/NPORT +#include "nvswitch/ls10/dev_npg_ip.h" +#include "nvswitch/ls10/dev_npgperf_ip.h" +#include "nvswitch/ls10/dev_nport_ip.h" +#include "nvswitch/ls10/dev_route_ip.h" +#include "nvswitch/ls10/dev_tstate_ip.h" +#include "nvswitch/ls10/dev_egress_ip.h" +#include "nvswitch/ls10/dev_ingress_ip.h" +#include "nvswitch/ls10/dev_sourcetrack_ip.h" +#include "nvswitch/ls10/dev_multicasttstate_ip.h" +#include "nvswitch/ls10/dev_reductiontstate_ip.h" + +// NXBAR +#include "nvswitch/ls10/dev_nxbar_tile_ip.h" +#include "nvswitch/ls10/dev_nxbar_tileout_ip.h" + +#endif //_SUGEN_LS10_H_ diff --git a/src/common/nvswitch/kernel/inc/ls10/therm_ls10.h b/src/common/nvswitch/kernel/inc/ls10/therm_ls10.h new file mode 100644 index 000000000..52be64153 --- /dev/null +++ b/src/common/nvswitch/kernel/inc/ls10/therm_ls10.h @@ -0,0 +1,53 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _THERM_LS10_H_ +#define _THERM_LS10_H_ + +NvlStatus +nvswitch_init_thermal_ls10 +( + nvswitch_device *device +); + +NvlStatus +nvswitch_ctrl_therm_read_temperature_ls10 +( + nvswitch_device *device, + NVSWITCH_CTRL_GET_TEMPERATURE_PARAMS *info +); + +NvlStatus +nvswitch_ctrl_therm_get_temperature_limit_ls10 +( + nvswitch_device *device, + NVSWITCH_CTRL_GET_TEMPERATURE_LIMIT_PARAMS *info +); + +void +nvswitch_monitor_thermal_alert_ls10 +( + nvswitch_device *device +); + +#endif //_THERM_LS10_H_ diff --git a/src/common/nvswitch/kernel/inc/pmgr_nvswitch.h b/src/common/nvswitch/kernel/inc/pmgr_nvswitch.h index 5bb1caf03..7f86d5e4c 100644 --- a/src/common/nvswitch/kernel/inc/pmgr_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/pmgr_nvswitch.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -301,6 +301,12 @@ struct NVSWITCH_OBJI2C // I2C device allow list NVSWITCH_I2C_DEVICE_DESCRIPTOR_TYPE *i2c_allow_list; NvU32 i2c_allow_list_size; + + // For I2C via SOE support + NvBool soeI2CSupported; + NvBool kernelI2CSupported; + void *pCpuAddr; + NvU64 dmaHandle; }; // diff --git a/src/common/nvswitch/kernel/inc/regkey_nvswitch.h b/src/common/nvswitch/kernel/inc/regkey_nvswitch.h index 10a1067c2..498dd6f7c 100644 --- a/src/common/nvswitch/kernel/inc/regkey_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/regkey_nvswitch.h @@ -323,6 +323,8 @@ #define NV_SWITCH_REGKEY_SPEED_CONTROL_SPEED_40G 0x0F #define NV_SWITCH_REGKEY_SPEED_CONTROL_SPEED_50G 0x10 #define NV_SWITCH_REGKEY_SPEED_CONTROL_SPEED_53_12500G 0x11 +#define NV_SWITCH_REGKEY_SPEED_CONTROL_SPEED_100_00000G 0x12 +#define NV_SWITCH_REGKEY_SPEED_CONTROL_SPEED_106_25000G 0x13 /* * Enable/Disable periodic flush to inforom. Default is disabled. @@ -516,13 +518,23 @@ #define NV_SWITCH_REGKEY_I2C_ACCESS_CONTROL_ENABLE 0x1 #define NV_SWITCH_REGKEY_I2C_ACCESS_CONTROL_DISABLE 0x0 +/* + * NV_SWITCH_REGKEY_FORCE_KERNEL_I2C - Used to force Kernel I2C path + * + * Private: Debug use only + */ +#define NV_SWITCH_REGKEY_FORCE_KERNEL_I2C "ForceKernelI2c" +#define NV_SWITCH_REGKEY_FORCE_KERNEL_I2C_DEFAULT 0x0 +#define NV_SWITCH_REGKEY_FORCE_KERNEL_I2C_ENABLE 0x1 +#define NV_SWITCH_REGKEY_FORCE_KERNEL_I2C_DISABLE 0x0 + /* * NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT - Configure the CRC bit error rate for the short interrupt * * Public: Available in release drivers */ #define NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT "CRCBitErrorRateShort" -#define NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_OFF 0x0 +#define NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_DEFAULT 0x0 #define NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN 2:0 #define NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP 3:3 #define NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_MAN 6:4 @@ -534,7 +546,7 @@ * Public: Available in release drivers */ #define NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_LONG "CRCBitErrorRateLong" -#define NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_LONG_OFF 0x000 +#define NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_LONG_DEFAULT 0x000 #define NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_LONG_BUG_3365481_CASE_1 0x803 #define NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_LONG_BUG_3365481_CASE_2 0x703 #define NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_LONG_BUG_3365481_CASE_5 0x34D @@ -544,4 +556,37 @@ #define NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_LONG_TIMESCALE_MAN 6:4 #define NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_LONG_TIMESCALE_EXP 12:8 +/* + * NV_SWITCH_REGKEY_SET_LP_THRESHOLD - Sets the LP Threshold Value + * + * Private: Debug use only + */ +#define NV_SWITCH_REGKEY_SET_LP_THRESHOLD "LPThreshold" +#define NV_SWITCH_REGKEY_SET_LP_THRESHOLD_DEFAULT 0x0 + +/* + * NV_SWITCH_REGKEY_MINION_INTERRUPTS - Enable/disable MINION interrupts + * + * Used for bug #3572329. To be removed once fmodel conflict is resolved. + * + * Public: Available in release drivers + */ +#define NV_SWITCH_REGKEY_MINION_INTERRUPTS "MINIONIntr" +#define NV_SWITCH_REGKEY_MINION_INTERRUPTS_DEFAULT 0x0 +#define NV_SWITCH_REGKEY_MINION_INTERRUPTS_ENABLE 0x1 +#define NV_SWITCH_REGKEY_MINION_INTERRUPTS_DISABLE 0x2 + +/* + * NV_SWITCH_REGKEY_SURPRESS_LINK_ERRORS_FOR_GPU_RESET - surpresses error prints/notifs + * + * When set, Heartbeat timeout, Short Error Rate and Fault Up interrupts won't be + * logged + * + * Public: Available in release drivers + */ + +#define NV_SWITCH_REGKEY_SURPRESS_LINK_ERRORS_FOR_GPU_RESET "SurpressLinkErrorsForGpuReset" +#define NV_SWITCH_REGKEY_SURPRESS_LINK_ERRORS_FOR_GPU_RESET_DISABLE 0x0 +#define NV_SWITCH_REGKEY_SURPRESS_LINK_ERRORS_FOR_GPU_RESET_ENABLE 0x1 + #endif //_REGKEY_NVSWITCH_H_ diff --git a/src/common/nvswitch/kernel/inc/smbpbi_nvswitch.h b/src/common/nvswitch/kernel/inc/smbpbi_nvswitch.h index bebea56f0..08b995079 100644 --- a/src/common/nvswitch/kernel/inc/smbpbi_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/smbpbi_nvswitch.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -45,6 +45,7 @@ struct smbpbi { SOE_SMBPBI_SHARED_SURFACE *sharedSurface; NvU64 dmaHandle; + NvU32 logMessageNesting; }; NvlStatus nvswitch_smbpbi_init(nvswitch_device *); @@ -55,6 +56,5 @@ NvlStatus nvswitch_smbpbi_set_link_error_info(nvswitch_device *, void nvswitch_smbpbi_unload(nvswitch_device *); void nvswitch_smbpbi_destroy(nvswitch_device *); NvlStatus nvswitch_smbpbi_refresh_ecc_counts(nvswitch_device *); -void nvswitch_smbpbi_log_message(nvswitch_device *device, NvU32 num, NvU32 msglen, NvU8 *osErrorString); #endif //_SMBPBI_NVSWITCH_H_ diff --git a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h index feccf9404..80a2ddf72 100644 --- a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h +++ b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h @@ -33,9 +33,9 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { - 0x00fec0d0, 0x0004fe00, 0x0017167e, 0x08f802f8, 0xa4b300f8, 0x64890a00, 0x9abf000f, 0x1100a0b3, + 0x00fec0d0, 0x0004fe00, 0x0017167e, 0x08f802f8, 0xa4b300f8, 0x8c890a00, 0x9abf000f, 0x1100a0b3, 0x0d00b0b3, 0xa001aa98, 0xf8a43dba, 0x0a02f800, 0xbd00f8ff, 0xfc30f494, 0x40fe02f9, 0x04009001, - 0x0db209a0, 0x0003237e, 0xa4b3afb2, 0x0dbf1601, 0x0a01d4b3, 0x002d8989, 0xa43d9d20, 0x00006b3e, + 0x0db209a0, 0x0003237e, 0xa4b3afb2, 0x0dbf1601, 0x0a01d4b3, 0x002e8989, 0xa43d9d20, 0x00006b3e, 0xfc09040a, 0x0bf4f9a6, 0xfbff0a05, 0x337e0405, 0xa0330000, 0xa0330a04, 0x02f80600, 0xb37e00f8, 0xafb20003, 0x0801a4b3, 0x00f8a43d, 0xfc09040a, 0x0bf4f9a6, 0x0a02f807, 0xbd00f8ff, 0xbdc4bdb4, 0x007e7ed4, 0xf900f800, 0xb2a2b222, 0xb2c0b2b1, 0xb21bb22a, 0x7eff0d0c, 0x3300007e, 0xfbf400a4, @@ -72,59 +72,59 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x3e00000e, 0xb2000491, 0x01147e1a, 0x092e7e00, 0x0a747e00, 0x0e1f9800, 0x000f1998, 0xf4f9a6fc, 0x1ab22a18, 0x4cb25bb2, 0x0002f47e, 0xb3091998, 0xb2180090, 0x05f57e8a, 0xb3a0b200, 0x7e0c01a4, 0x3e00000e, 0x000004c9, 0x0a9b7e01, 0xa6fc0f00, 0x251bf40f, 0x90b339bf, 0x6ab22000, 0xee023bb2, - 0x0005397e, 0x3400a9b3, 0x04f63eff, 0x3eef0000, 0x400004f6, 0x0ab2fe0c, 0x890c85fb, 0xbf000f70, - 0x8900f89a, 0xbf000f64, 0x8900f89a, 0xbf000f74, 0x0096b099, 0xf00bacf0, 0x00f801a6, 0x000f7889, - 0xa9a099bf, 0x000f7089, 0xa9b599bf, 0x0f00f801, 0x0f7c8901, 0xf89fa000, 0xb222f900, 0x7eb2b2a0, - 0x89000a74, 0xbf000f78, 0xa609bf9f, 0x110bf4f9, 0x000f7089, 0x09989fbf, 0xf4f9a601, 0x708d3318, - 0x0e98000f, 0xbfd9bf01, 0x029ebb2f, 0x18f49fa6, 0xbdd9bf20, 0x92e9bc14, 0xa0909fbc, 0x0f788929, - 0xa099bf00, 0xb5d9bf09, 0x903e0109, 0x01010005, 0x000a9b7e, 0x21fb1ab2, 0x000a747e, 0x000f748f, - 0x9990f9bf, 0x7ef9a001, 0xf8000a9b, 0x8002f900, 0xbf000f84, 0x0196b009, 0x7e070df4, 0x7e00000e, - 0x3e000a8f, 0x8e0005b3, 0x18001038, 0xefbf41a9, 0x9ac4abb2, 0xf4afa6ff, 0xeaa0050d, 0xb604a994, - 0xa9bc02a4, 0x0f8489a0, 0x10bb9000, 0x7ea0a9bc, 0xf8000bee, 0x9812f900, 0x909803a9, 0x24019003, - 0x517e1ab2, 0x7489000c, 0x99bf000f, 0x150094b3, 0x7e100a90, 0xb2000c51, 0x05c77e0a, 0x062b3e00, - 0x8a1bb200, 0x7e00103c, 0x89000bee, 0xbf000f64, 0x410f1899, 0x9918a4bd, 0xf4f92641, 0x010a050d, - 0x22f911fb, 0x000f6482, 0xb0b229bf, 0x000f7081, 0x7e249b90, 0xbf000c0f, 0xbc2abf19, 0xaa900009, - 0x0c517e10, 0xb529bf00, 0x19bf0490, 0x18f409a6, 0x1050890b, 0x067d3e00, 0x10548900, 0xbf9abf00, - 0x10bb902b, 0x000c0f7e, 0x30f421fb, 0x0f7489fc, 0xbf82f900, 0x0090b399, 0x89010f10, 0xa0000f7c, - 0x08453e9f, 0x0f648900, 0x0148fe00, 0x95bf91b2, 0x343d243d, 0x388064bd, 0x6c870010, 0x6884000f, - 0x8890000f, 0x06d23e24, 0x3d09bf00, 0x01999224, 0x09bf09a0, 0x000f848e, 0xb6049f94, 0x9fbc0294, + 0x0005397e, 0x3400a9b3, 0x04f63eff, 0x3eef0000, 0x400004f6, 0x0ab2fe0c, 0x890c85fb, 0xbf000f98, + 0x8900f89a, 0xbf000f8c, 0x8900f89a, 0xbf000f9c, 0x0096b099, 0xf00bacf0, 0x00f801a6, 0x000fa089, + 0xa9a099bf, 0x000f9889, 0xa9b599bf, 0x0f00f801, 0x0fa48901, 0xf89fa000, 0xb222f900, 0x7eb2b2a0, + 0x89000a74, 0xbf000fa0, 0xa609bf9f, 0x110bf4f9, 0x000f9889, 0x09989fbf, 0xf4f9a601, 0x988d3318, + 0x0e98000f, 0xbfd9bf01, 0x029ebb2f, 0x18f49fa6, 0xbdd9bf20, 0x92e9bc14, 0xa0909fbc, 0x0fa08929, + 0xa099bf00, 0xb5d9bf09, 0x903e0109, 0x01010005, 0x000a9b7e, 0x21fb1ab2, 0x000a747e, 0x000f9c8f, + 0x9990f9bf, 0x7ef9a001, 0xf8000a9b, 0x8002f900, 0xbf000fac, 0x0196b009, 0x7e070df4, 0x7e00000e, + 0x3e000a8f, 0x8e0005b3, 0x18001060, 0xefbf41a9, 0x9ac4abb2, 0xf4afa6ff, 0xeaa0050d, 0xb604a994, + 0xa9bc02a4, 0x0fac89a0, 0x10bb9000, 0x7ea0a9bc, 0xf8000bee, 0x9812f900, 0x909803a9, 0x24019003, + 0x517e1ab2, 0x9c89000c, 0x99bf000f, 0x150094b3, 0x7e100a90, 0xb2000c51, 0x05c77e0a, 0x062b3e00, + 0x8a1bb200, 0x7e001064, 0x89000bee, 0xbf000f8c, 0x410f1899, 0x9918a4bd, 0xf4f92641, 0x010a050d, + 0x22f911fb, 0x000f8c82, 0xb0b229bf, 0x000f9881, 0x7e249b90, 0xbf000c0f, 0xbc2abf19, 0xaa900009, + 0x0c517e10, 0xb529bf00, 0x19bf0490, 0x18f409a6, 0x1078890b, 0x067d3e00, 0x107c8900, 0xbf9abf00, + 0x10bb902b, 0x000c0f7e, 0x30f421fb, 0x0f9c89fc, 0xbf82f900, 0x0090b399, 0x89010f10, 0xa0000fa4, + 0x08453e9f, 0x0f8c8900, 0x0148fe00, 0x95bf91b2, 0x343d243d, 0x608064bd, 0x94870010, 0x9084000f, + 0x8890000f, 0x06d23e24, 0x3d09bf00, 0x01999224, 0x09bf09a0, 0x000fac8e, 0xb6049f94, 0x9fbc0294, 0x909ebc90, 0x99b399bf, 0xbf013d00, 0xb949bf7f, 0xf9a60099, 0xbf0f0bf4, 0x7eec0b1a, 0x3e000a95, - 0xbf000742, 0x0090b349, 0x0859983d, 0xfe940fbf, 0x02f4b604, 0x8ef0febc, 0xbc000f84, 0x9fa6f0fe, + 0xbf000742, 0x0090b349, 0x0859983d, 0xfe940fbf, 0x02f4b604, 0x8ef0febc, 0xbc000fac, 0x9fa6f0fe, 0xbf221bf4, 0x92b4bd49, 0x49a00199, 0x99b949bf, 0xa079a000, 0x7e1abf15, 0xb0000a89, 0x1ff500a6, - 0x0fbf00f9, 0xfd9409bf, 0x049e9404, 0xbc0294b6, 0x848e909e, 0x9ebc000f, 0x01999890, 0xbc02f4b6, + 0x0fbf00f9, 0xfd9409bf, 0x049e9404, 0xbc0294b6, 0xac8e909e, 0x9ebc000f, 0x01999890, 0xbc02f4b6, 0xfebcf0fd, 0x019998f0, 0xbf01f9b5, 0x049f9409, 0xbc0294b6, 0x9ebc909f, 0x019e9890, 0x9f9409bf, - 0x0294b604, 0x8f909fbc, 0xbc000f8c, 0xe9a6909f, 0xbf2c1bf4, 0x9409bf0f, 0x9e9404fd, 0x0294b604, - 0x8e909ebc, 0xbc000f84, 0x9998909e, 0x02f4b601, 0xbcf0fdbc, 0x9998f0fe, 0x01f9b501, 0x9f9409bf, - 0x0294b604, 0x8f909fbc, 0xbc000f84, 0x9998909f, 0x03999801, 0x1abf19a0, 0x000a617e, 0x1000a4b3, + 0x0294b604, 0x8f909fbc, 0xbc000fb4, 0xe9a6909f, 0xbf2c1bf4, 0x9409bf0f, 0x9e9404fd, 0x0294b604, + 0x8e909ebc, 0xbc000fac, 0x9998909e, 0x02f4b601, 0xbcf0fdbc, 0x9998f0fe, 0x01f9b501, 0x9f9409bf, + 0x0294b604, 0x8f909fbc, 0xbc000fac, 0x9998909f, 0x03999801, 0x1abf19a0, 0x000a617e, 0x1000a4b3, 0xeb0b1abf, 0x000a957e, 0x0007fa3e, 0x8bb21abf, 0x000a897e, 0xf400a6b0, 0x2210401f, 0x01331001, - 0x06013433, 0x09bf06bf, 0x94ff2ec4, 0x94b6049f, 0x909fbc02, 0x000f848f, 0xbf909fbc, 0xf5e9a699, - 0xbffeb31b, 0x009db309, 0x1abffea4, 0x7efe0b4b, 0x3e000a95, 0x330006d2, 0x890a0030, 0xa0001038, - 0x0ad07e96, 0x0485fb00, 0x748922f9, 0x99bf000f, 0xcd009db3, 0x106c8900, 0x899fbf00, 0xbf000f70, - 0x0099b999, 0x0bf4f9a6, 0x0f64890f, 0x0b9abf00, 0x0a957eec, 0x0f708e00, 0x8fe9bf00, 0x9000106c, - 0xe9a00199, 0x99b9e9bf, 0xbff9a000, 0x0094b3e9, 0x10548f1f, 0x10508e00, 0xbffcbf00, 0x0f788de9, - 0xa0f9a000, 0x90d9bfec, 0xd9a00199, 0x0010548f, 0x99bff9bf, 0x0a0094b3, 0x003e04bd, 0xf9bf0009, + 0x06013433, 0x09bf06bf, 0x94ff2ec4, 0x94b6049f, 0x909fbc02, 0x000fac8f, 0xbf909fbc, 0xf5e9a699, + 0xbffeb31b, 0x009db309, 0x1abffea4, 0x7efe0b4b, 0x3e000a95, 0x330006d2, 0x890a0030, 0xa0001060, + 0x0ad07e96, 0x0485fb00, 0x9c8922f9, 0x99bf000f, 0xcd009db3, 0x10948900, 0x899fbf00, 0xbf000f98, + 0x0099b999, 0x0bf4f9a6, 0x0f8c890f, 0x0b9abf00, 0x0a957eec, 0x0f988e00, 0x8fe9bf00, 0x90001094, + 0xe9a00199, 0x99b9e9bf, 0xbff9a000, 0x0094b3e9, 0x107c8f1f, 0x10788e00, 0xbffcbf00, 0x0fa08de9, + 0xa0f9a000, 0x90d9bfec, 0xd9a00199, 0x00107c8f, 0x99bff9bf, 0x0a0094b3, 0x003e04bd, 0xf9bf0009, 0x98039998, 0x003e0390, 0x2fbf0009, 0xa6040998, 0x3e08f4f9, 0x000c517e, 0x900d0998, 0x90b3240a, 0x517e0800, 0x0ab2000c, 0x0005c77e, 0x99bf19bf, 0x1f0090b3, 0x999819bf, 0x03909803, 0x0009083e, - 0x000f7082, 0x00105481, 0xb3100a90, 0x89bf0004, 0xbf001070, 0x0094b399, 0x09283e17, 0x10708f00, - 0x90f9bf00, 0xf9a00199, 0x000a877e, 0x32f921fb, 0x000f7481, 0xe90019bf, 0xc00099b3, 0x0a747e00, - 0x9219bf00, 0x19a00199, 0x9db319bf, 0x8900a800, 0xbf001074, 0x0099b399, 0x3c8f009d, 0xf9bf0010, - 0x0a0094b3, 0x703e04bd, 0xf9980009, 0x03909803, 0x648314bd, 0x3c82000f, 0xaa3e0010, 0x517e0009, + 0x000f9882, 0x00107c81, 0xb3100a90, 0x89bf0004, 0xbf001098, 0x0094b399, 0x09283e17, 0x10988f00, + 0x90f9bf00, 0xf9a00199, 0x000a877e, 0x32f921fb, 0x000f9c81, 0xe90019bf, 0xc00099b3, 0x0a747e00, + 0x9219bf00, 0x19a00199, 0x9db319bf, 0x8900a800, 0xbf00109c, 0x0099b399, 0x648f009d, 0xf9bf0010, + 0x0a0094b3, 0x703e04bd, 0xf9980009, 0x03909803, 0x8c8314bd, 0x6482000f, 0xaa3e0010, 0x517e0009, 0x0a90000c, 0x0c517e10, 0x7e0ab200, 0xbf0005c7, 0x410f1839, 0x99182ebf, 0xf4f92641, 0x0101050d, - 0x1100e0b3, 0x98032998, 0x0a900390, 0x0004b324, 0x10708fd1, 0xb3f9bf00, 0xb21b0090, 0x08487ef0, - 0x9209bf00, 0x09a00199, 0x94b309bf, 0xe03ef300, 0x10b30009, 0x7c890e01, 0x99bf000f, 0x160194b3, - 0x7c89f4bd, 0x0100000f, 0x0e7e9fa0, 0xf43e0000, 0x04bd0009, 0x000a9b7e, 0x31fb0ab2, 0x748932f9, - 0x99bf000f, 0xf70fa3b2, 0x550094b3, 0x4b00a0b3, 0x0005987e, 0x000f7081, 0x000f6482, 0x2abf10bf, - 0x900030bc, 0x517e10aa, 0x29bf000c, 0xbf0490b5, 0xf409a619, 0x50890b18, 0x423e0010, 0x5489000a, + 0x1100e0b3, 0x98032998, 0x0a900390, 0x0004b324, 0x10988fd1, 0xb3f9bf00, 0xb21b0090, 0x08487ef0, + 0x9209bf00, 0x09a00199, 0x94b309bf, 0xe03ef300, 0x10b30009, 0xa4890e01, 0x99bf000f, 0x160194b3, + 0xa489f4bd, 0x0100000f, 0x0e7e9fa0, 0xf43e0000, 0x04bd0009, 0x000a9b7e, 0x31fb0ab2, 0x9c8932f9, + 0x99bf000f, 0xf70fa3b2, 0x550094b3, 0x4b00a0b3, 0x0005987e, 0x000f9881, 0x000f8c82, 0x2abf10bf, + 0x900030bc, 0x517e10aa, 0x29bf000c, 0xbf0490b5, 0xf409a619, 0x78890b18, 0x423e0010, 0x7c89000a, 0x9abf0010, 0xbb902bbf, 0x0c0f7e10, 0x092e7e00, 0xb3010f00, 0x7e0a00a4, 0x0f00000e, 0xfbfab201, 0x00a0b331, 0x03a99811, 0x99b9afbf, 0xf0f9a600, 0x00f80bac, 0xf41032f4, 0x548f1132, 0xf9bf0005, - 0xa0019990, 0xf800f8f9, 0x10107e00, 0x7e00f800, 0xf8001885, 0x18b47e00, 0x8f00f800, 0xbf000554, + 0xa0019990, 0xf800f8f9, 0x10107e00, 0x7e00f800, 0xf8001842, 0x184a7e00, 0x8f00f800, 0xbf000554, 0x0094b3f9, 0x1032f41a, 0xbd1132f4, 0x7eee0ba4, 0xf4000a95, 0x31f41031, 0xbf00f811, 0x019992f9, - 0xf9bff9a0, 0x0a0094b3, 0xf41031f4, 0x00f81131, 0x0041407e, 0xc9fe00f8, 0x1495b601, 0x3c089033, + 0xf9bff9a0, 0x0a0094b3, 0xf41031f4, 0x00f81131, 0x0038a77e, 0xc9fe00f8, 0x1495b601, 0x3c089033, 0xf4089630, 0x9033130c, 0x90332002, 0x90333403, 0x1c3e1800, 0x9033000b, 0x9033280f, 0x94331810, 0x0c3e1e0a, 0x8a7e000b, 0x00f80006, 0x0013bc7e, 0xb07e00f8, 0x00f80013, 0x00f802f8, 0x00f802f8, - 0x0041557e, 0x000ad67e, 0x0041407e, 0x02f900f8, 0x0041557e, 0xcf020049, 0xa0800099, 0x0fbf0010, + 0x0038bc7e, 0x000ad67e, 0x0038a77e, 0x02f900f8, 0x0038bc7e, 0xcf020049, 0xc8800099, 0x0fbf0010, 0xf4049ffd, 0x487e170b, 0x8a7e0008, 0x0fbf0006, 0xfa010049, 0x623e009f, 0xa4bd000b, 0x957eda0b, - 0x407e000a, 0x01fb0041, 0x0041557e, 0x00185a7e, 0x0800a0b3, 0x00068a7e, 0x0041407e, 0x94bd00f8, + 0xa77e000a, 0x01fb0038, 0x0038bc7e, 0x0018397e, 0x0800a0b3, 0x00068a7e, 0x0038a77e, 0x94bd00f8, 0x000b8d3e, 0x3cf8b93c, 0x999099af, 0xf49ca601, 0x00f8f508, 0xa23ea9b2, 0x9b20000b, 0x9001cc92, 0xc4b30199, 0x00f8f800, 0xc73ee4bd, 0xae3c000b, 0x98be3cf8, 0x2601ee90, 0x0e0bf4f9, 0xf0fff4f0, 0xf9bcff94, 0xa600f8a2, 0xe508f4ec, 0x00f8a4bd, 0xb508af90, 0xff0901af, 0xb502a9b5, 0xafb503af, @@ -134,19 +134,19 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xfbb502bf, 0x04bab501, 0x9990a9bf, 0xf8a9a001, 0x01af9800, 0xb502a998, 0xaf9802f9, 0x01a99802, 0x9801f9b5, 0xf99804af, 0xf49aa601, 0xa998091b, 0x01f9b502, 0xa9b594bd, 0x92f9bf04, 0xf9a00199, 0x72f900f8, 0xb202b998, 0xb2b1b2a5, 0x1d9a95c2, 0xb2249034, 0x32e732d4, 0x009033a6, 0x7e23000f, - 0x330018d7, 0x011200a9, 0x119819bf, 0x2029bc01, 0x18f429a6, 0xa6ff0921, 0x0a0bf419, 0x3e011190, - 0x7e000cd3, 0x0b0000ea, 0x7e020002, 0x3e0018b4, 0xc4000db5, 0x45ffff23, 0xfd3f0095, 0x94f00593, + 0x3300184e, 0x011200a9, 0x119819bf, 0x2029bc01, 0x18f429a6, 0xa6ff0921, 0x0a0bf419, 0x3e011190, + 0x7e000cd3, 0x0b0000ea, 0x7e020002, 0x3e00184a, 0xc4000db5, 0x45ffff23, 0xfd3f0095, 0x94f00593, 0xd41bf503, 0x0a747e00, 0x0e067e00, 0x01fafe00, 0xfe081995, 0x7bfe009f, 0x01bcfe01, 0x95181994, 0x9ffd082f, 0x0097fe05, 0xe4ff69c4, 0x33ffffcf, 0xf10f0070, 0xb6f8fff4, 0x253e0894, 0xf4f1000d, 0x94b68fff, 0x95f9ff0c, 0x3e009bfe, 0xe5000d92, 0xfd010059, 0x9fb90593, 0x04f9fd01, 0x000d433e, 0xa601f5b6, 0xfb0cf4f4, 0xbd03fd95, 0x0d543ee4, 0x01d5b600, 0xd0b3e932, 0xee900c00, 0x00eeb301, 0x94f0f401, 0xff5ee4ff, 0x007033ff, 0x0794f014, 0xfd1094b6, 0x39fa059e, 0x0d893e05, 0x0794f000, 0xfd1094b6, 0x39fa059e, 0x024fbb06, 0xbc303fbc, 0x44b3505f, 0xaffe9d00, 0x00b7fe00, 0xf800cbfe, - 0x7e170003, 0x3300195a, 0x3d0600a4, 0x0a9b7e04, 0x0ddd7e00, 0xfb0a3200, 0xf4010971, 0xe43dfc30, + 0x7e170003, 0x3300186b, 0x3d0600a4, 0x0a9b7e04, 0x0ddd7e00, 0xfb0a3200, 0xf4010971, 0xe43dfc30, 0x7e009130, 0xf4000c82, 0x00f80430, 0x0efc30f4, 0x00e13001, 0x000c827e, 0xf80430f4, 0x0a747e00, - 0x10a48f00, 0xb3f9bf00, 0xbf0f0090, 0x019992f9, 0x003ef9a0, 0xea7e000e, 0x030b0000, 0x0018b47e, - 0x000a9b7e, 0x747e00f8, 0xa48e000a, 0xefbf0010, 0xf9a6ff09, 0xbf0e0bf4, 0x019990e9, 0x2c3ee9a0, - 0xea7e000e, 0x030b0000, 0x0018b47e, 0x000a9b7e, 0x12f900f8, 0xafbfb9b2, 0xa0b29e3f, 0xb204d192, + 0x10cc8f00, 0xb3f9bf00, 0xbf0f0090, 0x019992f9, 0x003ef9a0, 0xea7e000e, 0x030b0000, 0x00184a7e, + 0x000a9b7e, 0x747e00f8, 0xcc8e000a, 0xefbf0010, 0xf9a6ff09, 0xbf0e0bf4, 0x019990e9, 0x2c3ee9a0, + 0xea7e000e, 0x030b0000, 0x00184a7e, 0x000a9b7e, 0x12f900f8, 0xafbfb9b2, 0xa0b29e3f, 0xb204d192, 0x18fe20cb, 0x1cb2019e, 0x1801fe35, 0xfe35029e, 0x03991802, 0xbf03f935, 0x04aa90aa, 0x7e7e0aa0, 0x09bf000b, 0xa09091bc, 0xf411fb09, 0x62f9f430, 0xb2b2a3b2, 0xd532c6b2, 0x0c00b4b3, 0x043d09f8, 0x000f513e, 0x0001b918, 0xff94f001, 0xe4039990, 0xf501fc91, 0xbf00be0b, 0x7eff0baa, 0x980000de, @@ -154,22 +154,22 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xa0a6f010, 0xa60d0df4, 0x8d18f5fa, 0x0f0b3e00, 0x02399800, 0x08f4f9a6, 0x01399835, 0xa69019bc, 0x7518f49a, 0x3d063e98, 0x014ffe94, 0x351cff90, 0xf92003f9, 0x0902f935, 0x35fbb204, 0x4ab201f9, 0x040dc4bd, 0x3998e5f9, 0x9849a001, 0x1db20639, 0x2bb26cb2, 0x900140fe, 0x0ab22000, 0x41fe95f9, - 0x0142fe01, 0x90271190, 0x1ab22622, 0xf77e2bb2, 0x020a0040, 0x117eab32, 0x0abf0041, 0x00043998, - 0x3f95f901, 0x7e2b3f1a, 0xbf004111, 0x009b7e3a, 0xfb0a3200, 0x5d330c65, 0x3dff5c00, 0x0f4b3e04, - 0x3dbcb200, 0x8aabb2d4, 0x7e0010a8, 0xf8000e6b, 0x0dbcb200, 0x8aabb201, 0x7e0010a8, 0xf8000e6b, - 0xb212f900, 0xb3b132a0, 0xf80a00a4, 0x100e3e09, 0x2d808900, 0x0b9abf00, 0x00de7eff, 0xff19c400, + 0x0142fe01, 0x90271190, 0x1ab22622, 0x5e7e2bb2, 0x020a0038, 0x787eab32, 0x0abf0038, 0x00043998, + 0x3f95f901, 0x7e2b3f1a, 0xbf003878, 0x009b7e3a, 0xfb0a3200, 0x5d330c65, 0x3dff5c00, 0x0f4b3e04, + 0x3dbcb200, 0x8aabb2d4, 0x7e0010d0, 0xf8000e6b, 0x0dbcb200, 0x8aabb201, 0x7e0010d0, 0xf8000e6b, + 0xb212f900, 0xb3b132a0, 0xf80a00a4, 0x100e3e09, 0x2e808900, 0x0b9abf00, 0x00de7eff, 0xff19c400, 0x0301008f, 0xbc099e94, 0xefcfe0ef, 0x8099b800, 0x94b60001, 0x009dcf09, 0xf0020918, 0x09352095, 0xf40fa602, 0xf63e411b, 0xf918000f, 0x2094f002, 0x3f340bf4, 0x009433f9, 0xf8cbbc0b, 0x000fef3e, - 0xf001f918, 0x9990ff94, 0x049afd03, 0xf6f0f9bc, 0xff3e00ef, 0x1bc4000f, 0x8cfc0aff, 0xa6002d68, - 0xc91bf4fd, 0x002d8089, 0x9b7e9abf, 0x11fb0000, 0xd48b02f9, 0x127e0010, 0xa0320000, 0x0f00a033, - 0x0000ea7e, 0x7eff0bc4, 0x890018b4, 0xbf0010d4, 0x10d88990, 0x899fbf00, 0x180010c4, 0x9e35180e, + 0xf001f918, 0x9990ff94, 0x049afd03, 0xf6f0f9bc, 0xff3e00ef, 0x1bc4000f, 0x8cfc0aff, 0xa6002e68, + 0xc91bf4fd, 0x002e8089, 0x9b7e9abf, 0x11fb0000, 0xfc8b02f9, 0x127e0010, 0xa0320000, 0x0f00a033, + 0x0000ea7e, 0x7eff0bc4, 0x8900184a, 0xbf0010fc, 0x11008990, 0x899fbf00, 0x180010ec, 0x9e35180e, 0xf40fa60e, 0x0918101b, 0x00943319, 0x3ea4bd0a, 0x1800107a, 0xb4331d0b, 0xa4bd0a00, 0x00106f3e, - 0x3d200a90, 0x13607ec4, 0x00a6b000, 0x3d0e1ef4, 0x19093594, 0x0010d889, 0x01fb90a0, 0x89ffa4f0, - 0x8c003031, 0xbc003024, 0xacbcd0a9, 0x3fdf3fa0, 0x30318cae, 0xffe9c400, 0x20909cbc, 0x3024899f, - 0xfff4f000, 0x20f0f9bc, 0x20943dfe, 0xf900f8d9, 0x30318922, 0xffa0c400, 0x3f2009bc, 0x33a1322e, - 0x7e0c00e0, 0x3e00107c, 0x8f0010e0, 0x3f0010dc, 0xf4a926f9, 0x947d0d1b, 0xf975fe20, 0x01f97502, - 0x00303189, 0x91209f3f, 0x00302489, 0x3d0009bc, 0x20092094, 0x3024892f, 0xfff4f000, 0x20f0f9bc, - 0xf921fbf1, 0x10dc8f52, 0x32943d00, 0xb2c332b4, 0x35f5b2a2, 0x143d01f9, 0x00113a3e, 0x1110203f, + 0x3d200a90, 0x13607ec4, 0x00a6b000, 0x3d0e1ef4, 0x19093594, 0x00110089, 0x01fb90a0, 0x89ffa4f0, + 0x8c003131, 0xbc003124, 0xacbcd0a9, 0x3fdf3fa0, 0x31318cae, 0xffe9c400, 0x20909cbc, 0x3124899f, + 0xfff4f000, 0x20f0f9bc, 0x20943dfe, 0xf900f8d9, 0x31318922, 0xffa0c400, 0x3f2009bc, 0x33a1322e, + 0x7e0c00e0, 0x3e00107c, 0x8f0010e0, 0x3f001104, 0xf4a926f9, 0x947d0d1b, 0xf975fe20, 0x01f97502, + 0x00313189, 0x91209f3f, 0x00312489, 0x3d0009bc, 0x20092094, 0x3124892f, 0xfff4f000, 0x20f0f9bc, + 0xf921fbf1, 0x11048f52, 0x32943d00, 0xb2c332b4, 0x35f5b2a2, 0x143d01f9, 0x00113a3e, 0x1110203f, 0x01229001, 0x16000033, 0x3b320a32, 0x0010af7e, 0x33015918, 0x35070094, 0x14260150, 0xfbe008f4, 0xfc30f451, 0xb13212f9, 0x900140fe, 0x0bb20800, 0x0000127e, 0x0e1800bf, 0x0014331d, 0x4f02f806, 0xf3f1000b, 0x19c40000, 0xf49fa6ff, 0xed320b0c, 0x9f3ef43d, 0x02f80011, 0xed32f43d, 0x00119f3e, @@ -178,20 +178,20 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xfd19f918, 0xf935059a, 0x0415fb19, 0x0011417e, 0x0600a433, 0x00f802f8, 0xf9fc30f4, 0x32a0b212, 0x0a747eb1, 0xfe0ab200, 0x00900140, 0x7e0bb208, 0xbf000012, 0x18f43d00, 0x163e1d0d, 0xe9180012, 0x01ff1020, 0x2620ee90, 0x0d1bf491, 0x0100943d, 0x233ee920, 0xf9c40012, 0xe009bcff, 0x08f4fd26, - 0x7e043de0, 0x32000a9b, 0x0415fb0a, 0x0011d87e, 0x0600a433, 0x00f802f8, 0xa4f082f9, 0x30008fff, - 0x30188e00, 0x58fa7c00, 0xb298ea3c, 0xbdc632b7, 0xff94f034, 0x00055888, 0x8120597c, 0x3e0010dc, + 0x7e043de0, 0x32000a9b, 0x0415fb0a, 0x0011d87e, 0x0600a433, 0x00f802f8, 0xa4f082f9, 0x31008fff, + 0x31188e00, 0x58fa7c00, 0xb298ea3c, 0xbdc632b7, 0xff94f034, 0x00055888, 0x8120597c, 0x3e001104, 0x52001354, 0x29e40122, 0x9494ffff, 0x034ffe08, 0xb31ff995, 0xd0100190, 0x03000000, 0xf594f0ff, 0xbf00d51b, 0x01008e89, 0x089f9500, 0xfffff9e4, 0x18f59ea6, 0x99900010, 0x0894b601, 0x473e89a0, - 0x1f580013, 0x02195801, 0x1bf4f966, 0x000b4945, 0x000093f1, 0x0030248f, 0x18909fbc, 0x19180190, - 0xf4092601, 0x02f8051b, 0xb43d0a32, 0x00107c7e, 0x0030188e, 0x3cff09c4, 0x008ef8e9, 0xe97c0030, + 0x1f580013, 0x02195801, 0x1bf4f966, 0x000b4945, 0x000093f1, 0x0031248f, 0x18909fbc, 0x19180190, + 0xf4092601, 0x02f8051b, 0xb43d0a32, 0x00107c7e, 0x0031188e, 0x3cff09c4, 0x008ef8e9, 0xe97c0031, 0xf0102098, 0x1975fff4, 0xf09f7c01, 0x58021f75, 0x9b520219, 0xffb9e401, 0x021b75ff, 0xfe0894b6, 0xa995039a, 0x0190b31f, 0x3d7cb29d, 0x133f3ed4, 0x10c93f00, 0xcc9001dd, 0xff9fc401, 0x23009033, - 0x00300080, 0x80e80f7c, 0x3c003018, 0xbe66980f, 0xf00f08f4, 0xe97cff94, 0xf5b96690, 0x26ff6708, + 0x00310080, 0x80e80f7c, 0x3c003118, 0xbe66980f, 0xf00f08f4, 0xe97cff94, 0xf5b96690, 0x26ff6708, 0xd008f4d6, 0xe4ffafc4, 0xb6fffff9, 0x49fa0894, 0x01339004, 0x0cf52566, 0x07f8ff0d, 0x81fb3ab2, 0xc53252f9, 0xb332a4b2, 0x0800a0b3, 0x0c00b433, 0xff0a02f8, 0x0013ae3e, 0x41b2c43d, 0x0011037e, 0x043d24bd, 0x0013a73e, 0x00101a3f, 0x01119001, 0x1700a033, 0x3c324bb2, 0x387e5d32, 0x2abc0012, - 0x00a6b020, 0x260a1ef4, 0xdf08f403, 0x51fb2ab2, 0x0000ea7e, 0xb47e2f0b, 0x00f80018, 0x0000ea7e, - 0xb47e2f0b, 0x00f80018, 0xa93f22f9, 0xd0b2c1b2, 0x3204c0b4, 0xff94f0ed, 0x08f4b9a6, 0x9402f805, + 0x00a6b020, 0x260a1ef4, 0xdf08f403, 0x51fb2ab2, 0x0000ea7e, 0x4a7e2f0b, 0x00f80018, 0x0000ea7e, + 0x4a7e2f0b, 0x00f80018, 0xa93f22f9, 0xd0b2c1b2, 0x3204c0b4, 0xff94f0ed, 0x08f4b9a6, 0x9402f805, 0xb99402bf, 0x02ae9804, 0x5200c0b3, 0x3cf0f9bc, 0xa998f9ed, 0x18203402, 0x0e1e0dcc, 0x909fbc01, 0x98019235, 0xebbb02a9, 0x909fbc04, 0x980191b5, 0x9fbc02a9, 0x029db590, 0xbc02a998, 0x9cb5909f, 0x02a99803, 0xb4909fbc, 0x9fb505f0, 0x01a99804, 0xb5059efd, 0x543e01a9, 0xf9bc0014, 0x90e9bc90, @@ -209,1599 +209,1319 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xaabf0099, 0xf8a29abc, 0xb242f900, 0xb2b3b2a0, 0x00c0b3c1, 0x0b004929, 0xb20092cf, 0x0000b394, 0xf93ab212, 0x00a03305, 0x3e010a0a, 0xcf0015e8, 0x92bb0049, 0xf491a602, 0x04b3e608, 0xa43d0a00, 0x0015e83e, 0x05f93ab2, 0x000041fb, 0xd24e0041, 0x00000554, 0x90fc00f8, 0x0015ea7e, 0xf90188fe, - 0x00289880, 0x64d880f9, 0x9800000f, 0x47fe0088, 0xbd87a001, 0x0387b570, 0xfe0010f7, 0xb7b600a4, - 0x1fb9f002, 0xf9001bf7, 0x7e00f890, 0x3e0015ea, 0xf9001647, 0x3450daf2, 0x50db0000, 0x7e000032, - 0x7e0015f6, 0xf7000b68, 0x64d80010, 0x9800000f, 0x87980088, 0x0074fe00, 0xb6028798, 0x79f00277, - 0x0017f71f, 0x28a080fc, 0x88fe80fc, 0xf8f0fb00, 0xdaf2f901, 0x00003450, 0x003250db, 0x15f67e00, - 0x0b2e7e00, 0x16473e00, 0x1832f400, 0x50daf2f9, 0xdb000032, 0x00003050, 0x0015f67e, 0x000b207e, - 0x0016473e, 0xf91832f4, 0x0188fef2, 0x3b7e80f9, 0x80fc0040, 0xfb0088fe, 0xb201f8f0, 0xb0afb2a9, + 0x00289880, 0x8cd880f9, 0x9800000f, 0x47fe0088, 0xbd87a001, 0x0387b570, 0xfe0010f7, 0xb7b600a4, + 0x1fb9f002, 0xf9001bf7, 0x7e00f890, 0x3e0015ea, 0xf9001647, 0x3550daf2, 0x50db0000, 0x7e000033, + 0x7e0015f6, 0xf7000b68, 0x8cd80010, 0x9800000f, 0x87980088, 0x0074fe00, 0xb6028798, 0x79f00277, + 0x0017f71f, 0x28a080fc, 0x88fe80fc, 0xf8f0fb00, 0xdaf2f901, 0x00003550, 0x003350db, 0x15f67e00, + 0x0b2e7e00, 0x16473e00, 0x1832f400, 0x50daf2f9, 0xdb000033, 0x00003150, 0x0015f67e, 0x000b207e, + 0x0016473e, 0xf91832f4, 0x0188fef2, 0xa27e80f9, 0x80fc0037, 0xfb0088fe, 0xb201f8f0, 0xb0afb2a9, 0x1ef400a6, 0xb0bab22b, 0x1ef400b6, 0xacfaff13, 0xf496b9ff, 0x00f8051e, 0xf801aab9, 0x01bab900, 0xffacfaff, 0x1ff496b9, 0x16d83ef0, 0x01afb900, 0xb6b0bab2, 0xd81ff400, 0x0016dd3e, 0x95e0abff, - 0xbf9510a9, 0x01b9fd10, 0xbb01affd, 0xa4b600ab, 0x00aebb10, 0xdcdf00f8, 0xf4000005, 0x62f9fc30, - 0xffbffebf, 0x900149fe, 0x9ea01c99, 0x0005e0d9, 0xbd9fa000, 0x010089f4, 0x009ff601, 0xb87fff4f, - 0x003f0099, 0xdf009ff6, 0x03ff0000, 0x010099b8, 0x009ff600, 0x00ff808f, 0x0a0099b8, 0x009ff600, - 0xb810004f, 0x024a0099, 0xd6009ff6, 0x40000000, 0x011c0085, 0x0005f0d0, 0x02008400, 0x00008301, - 0xaaa0d210, 0xfd01beef, 0x227e080a, 0xa6fd001c, 0x280bf504, 0x0049cf00, 0xf50493fd, 0xde001e0b, - 0x000005f0, 0xf2fff4bd, 0x90e9a095, 0xee9001ff, 0x04f4b304, 0x17f03ef5, 0x0059cf00, 0xf40194f0, - 0x3cf4fa1b, 0xf009b21f, 0x99fa0593, 0xf503f806, 0xf590043c, 0xf590033c, 0xf5ac543c, 0xf5c4043c, - 0xb2d0333c, 0x0393f009, 0xf80599fa, 0x003cf403, 0xe9920ebf, 0xf491a601, 0x0e98250d, 0x01e99201, - 0x0df491a6, 0x020e981a, 0xa601e992, 0x0f0df491, 0x92030e98, 0x91a601e9, 0xff700cf5, 0x0005f0df, - 0xd094bd00, 0x000005dc, 0xa003f9b5, 0x01f9b5f9, 0xa002f9b5, 0x589a7e0e, 0x05e0d900, 0x99bf0000, - 0x09a0a4bd, 0x900149fe, 0x9fbf1c99, 0xf9a609bf, 0x7e070bf4, 0xfb0042e9, 0x30f40465, 0xd112f9fc, - 0x000005dc, 0x40fe19bf, 0x08009001, 0xcf7e09a0, 0x0fbf0019, 0xa4f019bf, 0xf4f9a6ff, 0xe97e070b, - 0x15fb0042, 0x05dcdf04, 0xffbf0000, 0xfefc30f4, 0x9fa00149, 0xf40031f4, 0x49fe0028, 0xd99fbf01, - 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xf40042e9, 0x00f80430, 0x0005dcde, 0xf4efbf00, 0x49fefc30, - 0xf89fa001, 0xbf9fbf02, 0xf4f9a6e9, 0xe97e070b, 0x30f40042, 0xf400f804, 0x12f9fc30, 0x0005dcd1, - 0xfe19bf00, 0x00900140, 0x7e09a008, 0xbf001a81, 0xa619bf0f, 0x070bf4f9, 0x0042e97e, 0xd90415fb, - 0x00001334, 0xf9fc30f4, 0x05dcd112, 0x9b180000, 0x0c9a180d, 0x40fe19bf, 0x08009001, 0xe67e09a0, - 0x0fbf001b, 0xf9a619bf, 0x7e070bf4, 0xfb0042e9, 0x30f40415, 0xd112f9fc, 0x000005dc, 0x40fe19bf, - 0x08009001, 0xe67e09a0, 0x0fbf001b, 0xf9a619bf, 0x7e070bf4, 0xfb0042e9, 0x30f40415, 0xd112f9fc, - 0x000005dc, 0x40fe19bf, 0x08009001, 0x517e09a0, 0x0fbf001b, 0xf9a619bf, 0x7e070bf4, 0xfb0042e9, - 0xdcdf0415, 0xbf000005, 0xfc30f4ff, 0xa00149fe, 0x1400899f, 0x0099cf02, 0xf40194f0, 0x1f7e180b, - 0x008f0047, 0xf9ce0213, 0x0195f000, 0x3e00f9f7, 0xf80019b5, 0x0149fe02, 0xdcd99fbf, 0xbf000005, - 0xf4f9a699, 0xe97e070b, 0x30f40042, 0xf400f804, 0xdcdff830, 0xf9000005, 0xfeffbf02, 0x99900149, - 0x3d9fa008, 0x2d89d9f4, 0x9f200000, 0xcf06004f, 0x004e00ff, 0x00eecf07, 0xcf020049, 0x9ffd0099, - 0x10ef9504, 0xfd00eeb9, 0xffb9049e, 0x049fff00, 0xf40109c4, 0x5e7e070b, 0x09e40044, 0x0bf41000, - 0xfe010f2f, 0x008e0149, 0x99900289, 0xce9f2007, 0xfe0f00e9, 0xf7049ffd, 0x08d900e9, 0xbf000013, - 0x014bfe9a, 0xbb90010c, 0x006e7e07, 0x0009e400, 0x00907380, 0x19827e08, 0x01004900, 0xfe0090f7, - 0x99900149, 0xd99ebf08, 0x000005dc, 0x89d99fbf, 0x3f00002d, 0xf4efa69a, 0xe97e070b, 0x05fb0042, - 0x05dcde08, 0xefbf0000, 0xfefc30f4, 0x010a0149, 0x9fbf9fa0, 0xf9a6e9bf, 0x7e070bf4, 0xf40042e9, - 0x00f80430, 0xdffc30f4, 0x000005dc, 0xffbf02f9, 0x900149fe, 0xa0b20499, 0xa9989fa0, 0x0194f003, - 0xbf0d0bf4, 0x1c227eaa, 0x1ad23e00, 0xcfa9bf00, 0x0f98009a, 0x01099803, 0xf0020e98, 0xa9ff02f4, - 0xf09ea694, 0x9a320b9c, 0x0c00f0b3, 0xf0009630, 0x9a320b9c, 0x900149fe, 0x9fbf0499, 0x0005dcd9, - 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf40405fb, 0x12f9ec30, 0x900149fe, 0xdcd10899, 0xa0000005, - 0x019bb59a, 0xb5029cb5, 0x9bb2039e, 0xdcb219bf, 0xda0140fe, 0x00001aa4, 0xa0180090, 0x15a97e09, - 0xbf0fbf00, 0xf4f9a619, 0xe97e070b, 0x15fb0042, 0x05dcd914, 0x99bf0000, 0x8efc30f4, 0xfe00b800, - 0xf9a0014f, 0xc400efcf, 0x1bf404f9, 0x3ea43d09, 0xc5001b7b, 0xe9f604f9, 0xfe010a00, 0x9fbf0149, - 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf80430f4, 0x05dcdf00, 0xffbf0000, 0xfefc30f4, - 0x9fa00149, 0x00900089, 0xf00099ce, 0x0bf40194, 0xf1008f1e, 0x00f9ce00, 0xf71095f0, 0xffb800f9, - 0xce025200, 0x95f000f9, 0x00f9f710, 0xbf0149fe, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, - 0x0430f400, 0xdcdf00f8, 0xbf000005, 0xfc30f4ff, 0xf00149fe, 0x9fa003b4, 0x8903a4f0, 0xb6009400, - 0xabfd02a4, 0x009af705, 0xbf0149fe, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, - 0x30f400f8, 0x05dcdffc, 0x02f90000, 0x49feffbf, 0x04999001, 0x9fa0a0b2, 0x000a747e, 0x01c0008f, - 0xc700f9cf, 0x90b34c99, 0x90b34700, 0x02f8f601, 0x001c403e, 0xc700f9cf, 0x90b34c99, 0x90b30e00, - 0x02f8f601, 0x001c543e, 0x01c20080, 0x7e0000cf, 0xfe000a9b, 0x99900149, 0xd99fbf04, 0x000005dc, - 0x0ab299bf, 0x0bf4f9a6, 0x1caa3e28, 0xc1008900, 0x0090f601, 0x0000f1df, 0x0099b880, 0x9ff70201, - 0x009fcf00, 0x543e9fb2, 0xe97e001c, 0x05fb0042, 0xfc30f404, 0x0005dcdf, 0xbf12f900, 0x0149feff, - 0xb2089990, 0xb29fa0a0, 0x0a747eb1, 0xc0008f00, 0x00f9cf01, 0xb34c99c7, 0xb33e0090, 0xf8f60190, - 0x1cd13e02, 0x00f9cf00, 0xb34c99c7, 0xb30e0090, 0xf8f60190, 0x1ce53e02, 0x0a9b7e00, 0x0149fe00, - 0xbf089990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x1d3a3e30, 0xc1008900, 0x0090f601, 0x010099b8, - 0x0091f600, 0x0000f2df, 0x0099b880, 0x9ff60202, 0x009fcf00, 0xe53e9fb2, 0xe97e001c, 0x15fb0042, - 0x05dcdf04, 0xfebf0000, 0xb8fc30f4, 0x000180aa, 0xb60149fe, 0x9ea009a4, 0xbf00aacf, 0xa6f9bf9e, - 0x070bf4e9, 0x0042e97e, 0xf80430f4, 0x05dcdf00, 0xffbf0000, 0x03010089, 0xb6fc30f4, 0xa9bc09a4, - 0x0149fea0, 0xabf69fa0, 0x0149fe00, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x30f40042, - 0xde00f804, 0x000005dc, 0x30f4efbf, 0x20008afc, 0x0149fe03, 0xaacf9fa0, 0xbf9fbf00, 0xf4f9a6e9, - 0xe97e070b, 0x30f40042, 0xdf00f804, 0x000005dc, 0x30f4ffbf, 0x0149fefc, 0x00899fa0, 0x9af60320, - 0xbd400f00, 0x009ff694, 0xbf0149fe, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, - 0xdcde00f8, 0xbf000005, 0xfc30f4ef, 0x0321008a, 0xa00149fe, 0x00aacf9f, 0xe9bf9fbf, 0x0bf4f9a6, - 0x42e97e07, 0x0430f400, 0xdcdf00f8, 0xbf000005, 0xfc30f4ff, 0xa00149fe, 0x1fa9959f, 0xa4f0c920, - 0x02a0b303, 0x03a0b30c, 0x01a4b308, 0x3ebaa00a, 0xbd001e57, 0xfeb9a094, 0x9fbf0149, 0x0005dcd9, - 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf80430f4, 0x05dcde00, 0xe9bf0000, 0xfefc30f4, 0xf9a0014f, - 0xa0e2a9c7, 0xeaa9c7b9, 0xaae7c9a0, 0xdaa00154, 0xe9bfffbf, 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0x5fbf0023, 0xf9a6e9bf, 0x34381bf4, 0xe89827b0, 0x987fbf01, 0xb03302e9, 0xb0b40a00, - 0x90b9bc0c, 0x1bf4f9a6, 0x1344df1e, 0xf9180000, 0x0094330c, 0x90f1b206, 0x24d920ff, 0xa6000028, - 0xed1bf4f9, 0x130010b3, 0xbf0c1c35, 0x0118b55b, 0x79bf1ba0, 0x900219b5, 0xee9001dd, 0x0ab0b40c, - 0x08f4dba6, 0x242d3ea4, 0x02499800, 0x4dfe5cbf, 0xb22ab201, 0x34dd901b, 0x2d3e95f9, 0x10b30024, - 0x49980f00, 0xb25cbf03, 0xf91bb22a, 0x4b903495, 0x11009433, 0x14bdff09, 0xa00e91b0, 0xa094bd79, - 0x01339059, 0xb4046690, 0x39a60d90, 0xff1408f5, 0x900149fe, 0x9fbf4c99, 0x0005dcd9, 0xa699bf00, - 0x070bf4f9, 0x0042e97e, 0xf42c85fb, 0xdcd9fc30, 0xf9000005, 0xf499bf62, 0x24d0fc30, 0xfe000028, - 0xff90014f, 0x3ff9a020, 0xb2a5b209, 0xb2c2b2b4, 0x009d33d3, 0xb4bd0111, 0xda14e44c, 0x00001344, - 0x000b947e, 0x06b294bd, 0x8a0091b0, 0xdb02c000, 0x000001fc, 0x00020cdc, 0x3d1a0d00, 0x1344d0e4, - 0x037e0000, 0x14bd0023, 0x94b309bf, 0x09981f13, 0x040a9802, 0x0001ccdb, 0x0344dc00, 0x91b00000, - 0x0e080d00, 0x23037e01, 0xb30dbf00, 0x983504d4, 0x0998040a, 0x01dcdb02, 0xa4dc0000, 0x0e000003, - 0x0091b001, 0x0023037e, 0xb0040a98, 0xdcdb0011, 0xdc000001, 0x000003d4, 0xe43d090d, 0x0023037e, - 0x94b309bf, 0x0a981c05, 0x0011b004, 0x0001dcdb, 0x0440dc00, 0x020d0000, 0x037ee43d, 0x09bf0023, - 0x371594b3, 0x98040a98, 0xecdb0209, 0xdc000001, 0x00000458, 0x010e040d, 0x7e0091b0, 0x98002303, - 0x11b0040a, 0x01ecdb00, 0x88dc0000, 0x0d000004, 0x7ee43d04, 0xbf002303, 0x1694b309, 0x040a981c, - 0xdb0011b0, 0x000001ec, 0x0004b8dc, 0x3d020d00, 0x23037ee4, 0x20009000, 0x1bf506a6, 0x0109ff2e, - 0x3d940920, 0x1358d902, 0x48df0000, 0xbc000013, 0xff0ad0d9, 0x002828de, 0xa6f9bf00, 0x2f1bf459, - 0xa601f998, 0x271bf449, 0x3308f918, 0xb3210194, 0xb0140120, 0x08f40126, 0xb3ff0a0d, 0x3e110224, - 0x980025ea, 0xec3e03fa, 0xdabf0025, 0x9020ff90, 0xfea620dd, 0x09c51bf4, 0xf4a9a6ff, 0x190f0d1b, - 0xf7110049, 0x02f8009f, 0x900149fe, 0x9fbf2099, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, - 0xfb0430f4, 0x30f40465, 0xd112f9f4, 0x000005dc, 0x40fe19bf, 0x10009001, 0x09a0caa0, 0xcbb594bd, - 0x02c9b501, 0x00130cd9, 0xfe9fbf00, 0x99900149, 0x019bb508, 0xb5b69aa0, 0xd8fab811, 0xb17e0002, - 0x0fbf001c, 0xf9a619bf, 0x7e070bf4, 0xfb0042e9, 0x30f40c15, 0xd252f9e8, 0x000005dc, 0x40fe29bf, - 0x18009001, 0x0cb50ba0, 0xb2e5b201, 0xfea3b2d4, 0x11900141, 0x7e19a02c, 0x7e000e06, 0x98000a74, - 0x0abf010b, 0x900140fe, 0x0cb22000, 0x0026267e, 0x4cb20bb2, 0x3ab25db2, 0x000dcc7e, 0x9b7ea032, - 0xdd7e000a, 0x1fbf000d, 0x0a3229bf, 0x0bf4f9a6, 0x42e97e07, 0x1855fb00, 0xf9e830f4, 0x05dcd252, - 0x29bf0000, 0x900140fe, 0x0ba01800, 0xb2010cb5, 0xb2d4b2e5, 0x0141fea3, 0xa02c1190, 0x0e067e19, - 0x0a747e00, 0x010b9800, 0x40fe0abf, 0x20009001, 0x267e0cb2, 0x0bb20026, 0x5db24cb2, 0xb97e3ab2, - 0xa032000d, 0x000a9b7e, 0x000ddd7e, 0x29bf1fbf, 0xf9a60a32, 0x7e070bf4, 0xfb0042e9, 0xdcd91855, - 0xbf000005, 0xfc30f499, 0x0a014ffe, 0x7ef9a004, 0x330042f5, 0x8a2e00a0, 0x7e120050, 0xf0001c22, - 0x0bf401a4, 0x00588a1f, 0x1c227e12, 0x00a0b300, 0x07a9c416, 0x0a0d1bf4, 0x42f57e02, 0x00a43300, - 0xfe02f806, 0x9fbf0149, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf80430f4, 0x130cd900, - 0x30f40000, 0xd112f9fc, 0x000005dc, 0x19bf9abf, 0xdb0140fe, 0x40000000, 0xb8080090, 0x0008b4aa, - 0xfa7e09a0, 0x0fbf009e, 0xf9a619bf, 0x7e070bf4, 0xfb0042e9, 0x0cd90415, 0xf4000013, 0x12f9fc30, - 0x0005dcd1, 0xbf9abf00, 0x0140fe19, 0x000000db, 0x08009040, 0x08c4aab8, 0x7e09a000, 0xbf009efa, - 0xa619bf0f, 0x070bf4f9, 0x0042e97e, 0xd90415fb, 0x0000130c, 0xf9fc30f4, 0x05dcd112, 0x9abf0000, - 0x40fe19bf, 0x0000db01, 0x00908000, 0xc4aab808, 0x09a00008, 0x009efa7e, 0x19bf0fbf, 0x0bf4f9a6, - 0x42e97e07, 0x0415fb00, 0x0005dcdf, 0xf4ffbf00, 0x49fefc30, 0xd99fa001, 0x0000130c, 0x008f99bf, - 0x9a9001c0, 0x00f9cf60, 0xb34c99c7, 0xb34a0090, 0xf8f60190, 0x28653e02, 0x00f9cf00, 0xb34c99c7, - 0xb30e0090, 0xf8f60190, 0x28793e02, 0xc2008b00, 0x00bbcf01, 0x040018d9, 0x05b9fd04, 0x009efa7e, - 0xbf0149fe, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x28d23e28, 0xc1008900, 0x009af601, 0x0000f1df, - 0x0099b880, 0x9ff70201, 0x009fcf00, 0x793e9fb2, 0xe97e0028, 0x30f40042, 0xf400f804, 0x0cd9fc30, - 0xf9000013, 0xb299bf22, 0x05dcd1a2, 0x40fe0000, 0xc89ab801, 0x19bf0008, 0xa00c0090, 0x1c227e09, - 0xbf0ebf00, 0xbb01091f, 0xa9fd0492, 0x0bacf004, 0x0bf4efa6, 0x42e97e07, 0x0425fb00, 0xd9fc30f4, - 0x000005dc, 0x99bf02f9, 0x90014ffe, 0xf9a004ff, 0x00130cd9, 0x8f9ebf00, 0xcf01c000, 0x99c700f9, - 0x0099b34c, 0x90b301d2, 0x02f8f501, 0x00293b3e, 0xc700f9cf, 0x99b34c99, 0xb301ae00, 0xf8f50190, - 0x29503e02, 0x00f9cf00, 0xb34c99c7, 0x01770099, 0xf50190b3, 0x653e02f8, 0xf9cf0029, 0x4c99c700, - 0x480099b3, 0x0190b301, 0x3e02f8f5, 0x7e00297a, 0xd90090c0, 0x00800000, 0xf49409ff, 0x317e070b, - 0x0cd9002d, 0xbf000013, 0xc0008f9e, 0x00f9cf01, 0xb34c99c7, 0x00f30099, 0xf50190b3, 0xad3e02f8, - 0xf9cf0029, 0x4c99c700, 0xcf0099b3, 0x0190b300, 0x3e02f8f5, 0xcf0029c2, 0x99c700f9, 0x0099b34c, - 0x90b30098, 0x02f8f501, 0x0029d73e, 0xc700f9cf, 0x90b34c99, 0x90b36e00, 0x02f8f601, 0x0029ec3e, - 0x007bff7e, 0x000000d9, 0x9409ff40, 0x7e070bf4, 0xd9007e13, 0x02000000, 0x000000df, 0xb409ff04, - 0xf4940fff, 0xbffd060b, 0x0000df05, 0x0fff0800, 0x060bf494, 0xd905bffd, 0x0000130c, 0xaab89abf, - 0x7e0008c4, 0xfe009efa, 0x99900149, 0xd99fbf04, 0x000005dc, 0xf9a699bf, 0x00e10bf5, 0x002b353e, - 0x01c20089, 0xff0099cf, 0x0995049d, 0x0194b31f, 0x2a003e97, 0xa4efb800, 0x00890008, 0x9ff601c1, - 0x00f1df00, 0x99b88000, 0xf7020100, 0x9fcf009f, 0x3e9fb200, 0x890029ec, 0xcf01c200, 0x008f009d, - 0xd73e01c0, 0xefb80029, 0x89000890, 0xf601c100, 0xf1df009f, 0xb8800000, 0x02010099, 0xcf009ff7, - 0x9fb2009f, 0x0029c23e, 0x01c20089, 0xff0099cf, 0x00d9049d, 0xff010000, 0x0bf59409, 0x8f3efeb9, - 0xefb80029, 0x89000898, 0xf601c100, 0xf1df009f, 0xb8800000, 0x02010099, 0xcf009ff7, 0x9fb2009f, - 0x00297a3e, 0x01c20089, 0x8f009dcf, 0x3e01c000, 0xb8002965, 0x000884ef, 0x01c10089, 0xdf009ff6, - 0x800000f1, 0x010099b8, 0x009ff702, 0xb2009fcf, 0x29503e9f, 0x42e97e00, 0x0405fb00, 0x0005dcdf, - 0xf4ffbf00, 0x49fefc30, 0x8f9fa001, 0xcf01c000, 0x99c700f9, 0x0090b34c, 0x0190b341, 0x3e02f8f6, - 0xcf002b4f, 0x99c700f9, 0x0090b34c, 0x0190b30e, 0x3e02f8f6, 0x8a002b63, 0xcf01c200, 0x49fe00aa, - 0xd99fbf01, 0x000005dc, 0xaac799bf, 0xf4f9a601, 0xb83e2d0b, 0xafb8002b, 0x89000380, 0xf601c100, - 0xf1df009f, 0xb8800000, 0x02010099, 0xcf009ff7, 0x9fb2009f, 0x002b633e, 0x0042e97e, 0xf80430f4, - 0xfc30f400, 0x0005dcd9, 0xbf82f900, 0x014ffe99, 0xa024ff90, 0x00a933f9, 0x04bd0087, 0x002838d7, - 0x8314bd00, 0x8601c000, 0xd501c100, 0x800000f1, 0x01c20084, 0x7b987abf, 0x7e0cb201, 0xf0004212, - 0x0bf401a4, 0xbd0bb248, 0x0ad4bdc4, 0x246b7e08, 0x7ea2b200, 0x33002b3c, 0xb83300a4, 0x0004002a, - 0xc70039cf, 0x99b34c99, 0xb300dc00, 0xf8f50190, 0x2c203e02, 0x0039cf00, 0xb34c99c7, 0x00b90099, - 0xf50190b3, 0x353e02f8, 0x0090002c, 0x00119101, 0xa42404b3, 0xa00014b3, 0x002cda3e, 0x38d804bd, - 0xbd000028, 0xc0008314, 0xc1008701, 0x00f1d601, 0x00858000, 0xfe0401c2, 0x8b988abf, 0x7e0cb201, - 0xf0004212, 0x0bf401a4, 0xbd0bb246, 0x0ad4bdc4, 0x246b7e08, 0x7ea2b200, 0x33002b3c, 0xb83100a4, - 0x0004002a, 0xc70039cf, 0x90b34c99, 0x90b37300, 0x02f8f601, 0x002ca43e, 0xc70039cf, 0x90b34c99, - 0x90b35100, 0x02f8f601, 0x002cb83e, 0x91010090, 0x04b30011, 0x14b3a624, 0x49fea200, 0x24999001, - 0xdcd99fbf, 0xbf000005, 0xa6a43d99, 0x410bf4f9, 0x002d2a3e, 0xf0004bcf, 0x6f7e01b5, 0x4a3e0047, - 0x6af6002c, 0x0035f700, 0x3e0039cf, 0xcf002c35, 0xb4fd005b, 0x476f7e04, 0x2ccc3e00, 0x007af600, - 0xcf0036f7, 0xb83e0039, 0xe97e002c, 0x85fb0042, 0xfc30f404, 0x0005dcdf, 0xbf02f900, 0x0149feff, - 0xa0049990, 0xc0008f9f, 0x00f9cf01, 0xb34c99c7, 0xb34f0090, 0xf8f60190, 0x2d493e02, 0x00f9cf00, - 0xb34c99c7, 0xb32a0090, 0xf8f60190, 0x2d5d3e02, 0x2dda7e00, 0x3009c400, 0x7e070bf4, 0xc4002e5a, - 0x0bf44009, 0x2e927e3d, 0x2dbf3e00, 0xc2008900, 0x0090cf01, 0xf40109c4, 0x713ede0b, 0x488f002d, - 0x008901b0, 0x9ff601c1, 0x00f1df00, 0x99b88000, 0xf7020100, 0x9fcf009f, 0x3e9fb200, 0xfe002d5d, - 0x99900149, 0xd99fbf04, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb0042e9, 0xdcdf0405, 0xbf000005, - 0xfc30f4ff, 0xa00149fe, 0xc0008f9f, 0x00f9cf01, 0xb34c99c7, 0xb3220090, 0xf8f60190, 0x2ded3e02, - 0x00f9cf00, 0xb34c99c7, 0xb3390090, 0xf8f60190, 0x2e013e02, 0xad248f00, 0xc1008901, 0x009ff601, - 0x99b8f4bd, 0xf6000100, 0xf2df009f, 0xb8800000, 0x02020099, 0xcf009ff6, 0x9fb2009f, 0x002e013e, - 0xbf0149fe, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, 0x30f400f8, 0xd112f9fc, - 0x000005dc, 0x048a19bf, 0xb4bd01ad, 0x900140fe, 0x09a00800, 0x0047e97e, 0x01ad848a, 0xe97eb4bd, - 0x0fbf0047, 0xf9a619bf, 0x7e070bf4, 0xfb0042e9, 0xdcdf0415, 0xbf000005, 0xfc30f4ff, 0xa00149fe, - 0xc0008f9f, 0x00f9cf01, 0xb34c99c7, 0xb3220090, 0xf8f60190, 0x2ea53e02, 0x00f9cf00, 0xb34c99c7, - 0xb3390090, 0xf8f60190, 0x2eb93e02, 0xada48f00, 0xc1008901, 0x009ff601, 0x99b8f4bd, 0xf6000100, - 0xf2df009f, 0xb8800000, 0x02020099, 0xcf009ff6, 0x9fb2009f, 0x002eb93e, 0xbf0149fe, 0x05dcd99f, - 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, 0xdcdf00f8, 0xbf000005, 0xfc30f4ff, 0x950149fe, - 0x9fa018be, 0xb995adb2, 0x055cdf10, 0x94760000, 0x08b5b608, 0x3ee59eff, 0x26002f5c, 0x1c1bf49b, - 0x6601f958, 0x141bf49e, 0xa43df97f, 0x5808d975, 0xdf7501ff, 0x2f643e09, 0x04ff9000, 0x9433f93f, - 0x010add00, 0xbf0149fe, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, 0xdcdf00f8, - 0xbf000005, 0xfc30f4ff, 0xa00149fe, 0x0aa9b29f, 0x00b0b302, 0x0895b60b, 0xb920a43d, 0xbf0149fe, - 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, 0x30f400f8, 0x05dcdffc, 0x02f90000, - 0x49feffbf, 0x04999001, 0x9fa0a0b2, 0x6500a0b3, 0xb305a998, 0xd95e0090, 0x0000130c, 0xaab89abf, - 0x7e0004e8, 0xe7001c22, 0xb30168a9, 0x4c0fff9a, 0x470090b3, 0xb314a5b6, 0x400fffaa, 0x3b00a0b3, - 0xb6050e98, 0xaf940c94, 0xa0a43d0c, 0x050e98e9, 0xf9bce9bf, 0x01efb5f0, 0xbd070f98, 0x98f9a094, - 0x0f980509, 0x9299bf07, 0xf9b50199, 0x30393e01, 0x3e350a00, 0x0a003039, 0x0149fe2e, 0xbf049990, - 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0405fb00, 0xd9fc30f4, 0x000005dc, 0x99bf32f9, - 0x90014ffe, 0xf9a010ff, 0xb9c4afb2, 0xf4020a03, 0xc9c4321b, 0xb8f2b2ff, 0x00392899, 0x01a2b3e7, - 0xbd029194, 0x309a3e04, 0x901ab200, 0x227e0100, 0x1190001c, 0x902aa004, 0x03a60422, 0x3ded08f4, - 0x0149fea4, 0xbf109990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0435fb00, 0xf9fc30f4, - 0x18a9bf12, 0xab1809af, 0x05dcd008, 0x99b80000, 0x94003969, 0x09bf029a, 0xf00141fe, 0x119001f4, - 0xf0ffbc08, 0x44d919a0, 0xf0008800, 0xb9fd01b4, 0x05bffd05, 0x001cb17e, 0x09bf1fbf, 0xf9a6a43d, - 0x7e070bf4, 0xfb0042e9, 0x30f40415, 0x05dcdffc, 0x22f90000, 0x49feffbf, 0x0c999001, 0x9fa0a0b2, - 0xc2b2b132, 0x00b3350a, 0x09bf6900, 0x610094b3, 0xb3010998, 0x8a5a0094, 0x7e00e204, 0xc4001c22, - 0xa9c4ff1e, 0xf49ea601, 0x943d091b, 0x0031813e, 0x09080f18, 0x01e4f0f3, 0xf002abc5, 0xb9fd01f4, - 0x02f4b604, 0xbffdfe09, 0xe2048a05, 0x04b9fd00, 0x7e05befd, 0x8a001cb1, 0x7e00e204, 0x09001c22, - 0x0020b301, 0x3d292006, 0x318f3ea4, 0xfe010a00, 0x99900149, 0xd99fbf0c, 0x000005dc, 0xf9a699bf, - 0x7e070bf4, 0xfb0042e9, 0x30f40425, 0x05dcdff8, 0x52f90000, 0x49feffbf, 0x1c999001, 0x9fa0a3b2, - 0xc272b0b2, 0x350ad4b2, 0xc70039b3, 0x00c97300, 0xd9b300ba, 0xbf00b500, 0x009db339, 0x399800b4, - 0x009db301, 0x088a00ac, 0x227e00e2, 0xa9c4001c, 0x0d0bf401, 0x02a2a9e7, 0xbb0294b6, 0x4cfe0209, - 0x3d3ab201, 0x1bcc90b4, 0x00310a7e, 0x8300ad33, 0x00008900, 0x0301c430, 0x09bc0405, 0xff19c400, - 0xb20209bb, 0x1c227e0a, 0xff19c400, 0xe4f259bc, 0xa6ffff29, 0x071df4f9, 0xffff2fe4, 0xf4bdfe32, - 0x0032563e, 0xf090913c, 0x94b60394, 0x95a9bc03, 0x90f9493c, 0xf93201ff, 0x08f4fe26, 0xffe9c4ea, - 0x7b040090, 0x20730229, 0x49bc0d00, 0x3e143d40, 0xfe003223, 0x99900149, 0xb29b3f1b, 0x7ec4bd3a, - 0x3e00310a, 0x0a00328f, 0x328f3e02, 0xfe010a00, 0x99900149, 0xd99fbf1c, 0x000005dc, 0xf9a699bf, - 0x7e070bf4, 0xfb0042e9, 0x30f40855, 0x05dcdffc, 0x02f90000, 0x49feffbf, 0x04999001, 0x9fa0a0b2, - 0xa0b3350e, 0xb43d1a00, 0x0a7ec4bd, 0xae320031, 0x0c00a433, 0xbc7e0ab2, 0xae320030, 0x900149fe, - 0x9fbf0499, 0x0005dcd9, 0x3299bf00, 0xf4f9a6ea, 0xe97e070b, 0x05fb0042, 0xf430f404, 0x0005dcd9, - 0xbf12f900, 0x014ffe99, 0x4b10ff90, 0xf9a003e8, 0x0016fc7e, 0x4afea0b2, 0x08aa9001, 0x817ea1b2, - 0xa08a0015, 0x227e00e5, 0xa6b0001c, 0x1c1ff400, 0x9c7e1ab2, 0xa0a60015, 0x0a090df4, 0x334b3e04, - 0x000e7e00, 0x33223e00, 0xfea43d00, 0x99900149, 0xd99fbf10, 0x000005dc, 0xf9a699bf, 0x7e070bf4, - 0xfb0042e9, 0x30f40c15, 0x05dcdffc, 0x02f90000, 0x49feffbf, 0x04999001, 0x9fa0b0b2, 0x3f01ad58, - 0x02a958af, 0x000000de, 0xffdce480, 0x03f4f0ff, 0xb60093f0, 0x9cbc12f4, 0x05fefd90, 0xf0019992, - 0xf9ffff94, 0x00d073b5, 0x01cf9218, 0x01000089, 0xff08f4b6, 0xf4f195b9, 0x9fffffff, 0x01aa18b5, - 0xf401a9c4, 0x00890a0b, 0xb9fd0200, 0xffa4f005, 0xf410a9c4, 0x00d90b0b, 0xfd080000, 0xa9c405b9, - 0x0b0bf404, 0x000000d9, 0x05b9fd20, 0x00e5a08a, 0x001cb17e, 0xf97e0ab2, 0x49fe0032, 0x04999001, - 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x05fb0042, 0xf830f404, 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0x06ff9815, - 0x100099b8, 0x00f4b300, 0x3e350af3, 0x98003584, 0xf99802fe, 0xbcffbf05, 0x9ea6909f, 0xf0089cf0, - 0x9a320196, 0x900149fe, 0x9fbf0c99, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf40815fb, - 0xdcdfe030, 0xf9000005, 0xb0ffbf82, 0x49fe09b1, 0x40999001, 0xa00140fe, 0x3c00909f, 0x0cb2a4b2, - 0x0050e87e, 0x395803bf, 0x03319802, 0xb60093f0, 0xe63e0c94, 0xe0b40035, 0xf49ea609, 0x1198130b, - 0x0099b806, 0x14b30010, 0xb83ef000, 0x19980037, 0x031f9805, 0xb6041e98, 0x9fbc0395, 0xf42ea620, - 0x43fe4f0c, 0x904ab201, 0x2bb23833, 0x3db2010c, 0x0031aa7e, 0xad33a032, 0xbf01a400, 0xff004f39, - 0x90014efe, 0x99bc34ee, 0x059ffd90, 0x2cb24ab2, 0xe9a0ebb2, 0x4a7e040d, 0xa032004b, 0x7e00ad33, - 0x05199801, 0xb5019990, 0xba3e0519, 0x7cd90037, 0x98000028, 0x49fe049e, 0x3c999001, 0x9ea09fb2, - 0x0036703e, 0x33091918, 0x98130090, 0xf1a00411, 0x14b3f1bf, 0xd43ef200, 0x39350037, 0x36a83e08, - 0x08b91800, 0x13009033, 0xa004bb98, 0xb31bbf1b, 0x3ef200b4, 0xbf0037b8, 0x7e4ab2bb, 0x32004a98, - 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0x0ae0b400, 0xb6ff89c4, 0x9ebc0c94, 0xa094bdb0, 0x04a9b5ab, 0x0fffb9e4, - 0x02241bf5, 0xb2014dfe, 0x90040c6a, 0xaa7e44dd, 0xa0330031, 0xa5320a00, 0x003b2b3e, 0xf11190b4, - 0x750fff94, 0x90b40239, 0x6c99e711, 0x03397501, 0xb61190b4, 0x39351f95, 0x11f0b408, 0x0ffff9e4, - 0x0fff9ab3, 0x6cf9e713, 0xff9ab301, 0x01090a0f, 0xbf093935, 0x0099b339, 0x7cdf0090, 0x18000028, - 0x99900dfb, 0x0ffc4a04, 0xf00991b0, 0xbb7effb4, 0x94bd0016, 0x91b0743d, 0xfffc090d, 0x91b094a9, - 0x3af13e0c, 0x0ba43d00, 0x40e57e1c, 0xb3a1b200, 0xf80c00a4, 0x3e050002, 0xb4003b58, 0x7ac40cb0, - 0x16fc7eff, 0xb5e4bd00, 0xb0b4061e, 0xfe040c09, 0xdd90014d, 0xb0babc40, 0x1bb56ab2, 0x31aa7e01, - 0x33a03200, 0x015500ad, 0xdf1090b4, 0x00ffffff, 0xa0049ffd, 0xf49fa619, 0x94bd071b, 0x1b9819a0, - 0x00b4b301, 0x0002f80c, 0x3b583e02, 0x0ce0b400, 0x92083f18, 0xb29001b9, 0x409ebc04, 0x0e00f033, - 0x00093918, 0x009d3335, 0x29900088, 0xb5f4bd04, 0x19b50414, 0x051fb503, 0x003ad73e, 0x2bb26ab2, - 0x4dfe040c, 0x3cdd9001, 0x0031aa7e, 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0x11004919, 0xf8009ff7, 0xb600f802, + 0xc4b30ca5, 0xff890f01, 0xa9ff07ff, 0xf8d9a094, 0xffff8900, 0x94a9ff07, 0x0f0d0bf4, 0x11004919, + 0xf8009ff7, 0xe700f802, 0xc702e2a9, 0xa0b39aaa, 0xa6b03005, 0x0f0cf405, 0x4300a0b3, 0x3504a4b3, + 0x001cf23e, 0x1a06a0b3, 0xf409a6b0, 0x063e260c, 0x190f001d, 0xf7110049, 0x02f8009f, 0x94b600f8, + 0x04b9b502, 0xaf9200f8, 0x0294b602, 0xf8f9b9bc, 0x49190f00, 0x9ff71100, 0xf802f800, 0x1fa99500, + 0xa4f0c920, 0x02a0b303, 0x03a0b30c, 0x01a4b308, 0xf8baa008, 0xa094bd00, 0xc700f8b9, 0xb9a0a2a9, + 0xa0e8a9c7, 0x54aae7c9, 0xf8daa001, 0x01c0b300, 0x0cc0b310, 0x0dc0b30c, 0x14c4b308, 0x4ca9e70a, + 0xf8d9a002, 0xe2a9e700, 0x9aaac702, 0x2c06a0b3, 0xf406a6b0, 0xa0b30f0c, 0xa4b31604, 0x983e2f05, + 0xa6b0001d, 0x240cf409, 0x001da03e, 0x0049190f, 0x009ff711, 0x00f802f8, 0xb50294b6, 0x00f804b9, + 0xb602af92, 0xb9bc0294, 0xf400f8f9, 0x82f9d430, 0x301590b4, 0xc1b027e1, 0x0ad1b00b, 0x94b6f4bd, + 0x0c91b002, 0x900149fe, 0x9fa04499, 0x20079990, 0x0b99929f, 0x95b29fa0, 0xa0049992, 0x9297b29f, + 0x9fa00499, 0x0005dcdf, 0x90ffbf00, 0x4efe1499, 0xa0a6b201, 0x34ee909f, 0xb4b20209, 0x14bde9a0, + 0x34bd84bd, 0x001eef3e, 0x277e6ab2, 0x49bf001a, 0x4bfea2b2, 0x014cfe01, 0x9044bb90, 0x95f94bcc, + 0xb31100b4, 0x008e0209, 0x9e0309b3, 0x010db300, 0x499800a8, 0xb27cb201, 0xfe5bb22a, 0xdd90014d, + 0x3295f938, 0x0be0b40c, 0xa53ed4bd, 0x5fbf001e, 0xf9a6e9bf, 0x34381bf4, 0xe89827b0, 0x987fbf01, + 0xb03302e9, 0xb0b40a00, 0x90b9bc0c, 0x1bf4f9a6, 0x1444df1e, 0xf9180000, 0x0094330c, 0x90f1b206, + 0x24d920ff, 0xa6000029, 0xed1bf4f9, 0x130010b3, 0xbf0c1c35, 0x0118b55b, 0x79bf1ba0, 0x900219b5, + 0xee9001dd, 0x0ab0b40c, 0x08f4dba6, 0x1ed53ea4, 0x02499800, 0x4dfe5cbf, 0xb22ab201, 0x34dd901b, + 0xd53e95f9, 0x10b3001e, 0x49980f00, 0xb25cbf03, 0xf91bb22a, 0x4b903495, 0x11009433, 0x14bdff09, + 0xa00e91b0, 0xa094bd79, 0x01339059, 0xb4046690, 0x39a60d90, 0xff1408f5, 0x900149fe, 0x9fbf4c99, + 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf92c85fb, 0x2924d062, 0x093f0000, 0xb2fc30f4, + 0xb2b4b2a5, 0x33d3b2c2, 0x0111009d, 0xe44cb4bd, 0x1444da14, 0x947e0000, 0x94bd000b, 0x91b006b2, + 0xc0008a00, 0x01fcdb02, 0x0cdc0000, 0x0d000002, 0xd0e43d1a, 0x00001444, 0x001dab7e, 0x09bf14bd, + 0x1f1394b3, 0x98020998, 0xccdb040a, 0xdc000001, 0x00000344, 0x0d0091b0, 0x7e010e08, 0xbf001dab, + 0x04d4b30d, 0x040a9835, 0xdb020998, 0x000001dc, 0x0003a4dc, 0xb0010e00, 0xab7e0091, 0x0a98001d, + 0x0011b004, 0x0001dcdb, 0x03d4dc00, 0x090d0000, 0xab7ee43d, 0x09bf001d, 0x1c0594b3, 0xb0040a98, + 0xdcdb0011, 0xdc000001, 0x00000440, 0xe43d020d, 0x001dab7e, 0x94b309bf, 0x0a983715, 0x02099804, + 0x0001ecdb, 0x0458dc00, 0x040d0000, 0x91b0010e, 0x1dab7e00, 0x040a9800, 0xdb0011b0, 0x000001ec, + 0x000488dc, 0x3d040d00, 0x1dab7ee4, 0xb309bf00, 0x981c1694, 0x11b0040a, 0x01ecdb00, 0xb8dc0000, + 0x0d000004, 0x7ee43d02, 0x90001dab, 0x06a62000, 0xff2e1bf5, 0x09200109, 0xd9023d94, 0x00001458, + 0x001448df, 0xd0d9bc00, 0x28deff0a, 0xbf000029, 0xf459a6f9, 0xf9982f1b, 0xf449a601, 0xf918271b, + 0x01943308, 0x0120b321, 0x0126b014, 0x0a0d08f4, 0x0224b3ff, 0x20803e11, 0x03fa9800, 0x0020823e, + 0xff90dabf, 0x20dd9020, 0x1bf4fea6, 0xa6ff09c5, 0x0d1bf4a9, 0x0049190f, 0x009ff711, 0x30f402f8, + 0xbd61fb04, 0xb5caa094, 0xc9b501cb, 0x140cd902, 0x9fbf0000, 0xfef830f4, 0x9bb50149, 0xb69aa001, + 0xfab811b5, 0x7e0002d8, 0xf4001a87, 0x00f80830, 0xf9e830f4, 0x05dcd252, 0x29bf0000, 0x900140fe, + 0x0ba01800, 0xb2010cb5, 0xb2d4b2e5, 0x0141fea3, 0xa02c1190, 0x0e067e19, 0x0a747e00, 0x010b9800, + 0x40fe0abf, 0x20009001, 0xa37e0cb2, 0x0bb20020, 0x5db24cb2, 0xcc7e3ab2, 0xa032000d, 0x000a9b7e, + 0x000ddd7e, 0x29bf1fbf, 0xf9a60a32, 0x7e070bf4, 0xfb003a31, 0x30f41855, 0xd252f9e8, 0x000005dc, + 0x40fe29bf, 0x18009001, 0x0cb50ba0, 0xb2e5b201, 0xfea3b2d4, 0x11900141, 0x7e19a02c, 0x7e000e06, + 0x98000a74, 0x0abf010b, 0x900140fe, 0x0cb22000, 0x0020a37e, 0x4cb20bb2, 0x3ab25db2, 0x000db97e, + 0x9b7ea032, 0xdd7e000a, 0x1fbf000d, 0x0a3229bf, 0x0bf4f9a6, 0x3a317e07, 0x1855fb00, 0x3d7e040a, + 0xa033003a, 0x508a2400, 0x277e1200, 0xa4f0001a, 0x150bf401, 0x1200588a, 0x001a277e, 0x1a00a0b3, + 0xf407a9c4, 0x02f8070b, 0x020a00f8, 0x003a3d7e, 0x0600a433, 0x00f802f8, 0x00140cd9, 0xdb9abf00, + 0x40000000, 0x08b4aab8, 0x83ed7e00, 0xd900f800, 0x0000140c, 0x00db9abf, 0xb8400000, 0x0008c4aa, + 0x0083ed7e, 0x0cd900f8, 0xbf000014, 0x0000db9a, 0xaab88000, 0x7e0008c4, 0xf80083ed, 0x140cd900, + 0x99bf0000, 0x01c0008f, 0xcf609a90, 0x99c700f9, 0x0090b34c, 0x0190b337, 0x3e02f8f6, 0xcf00222b, + 0x99c700f9, 0x0090b34c, 0x0190b30e, 0x3e02f8f6, 0x8b00223f, 0xcf01c200, 0x18d900bb, 0xfd040400, + 0xed7e05b9, 0x00f80083, 0x01c10089, 0xdf009af6, 0x800000f1, 0x010099b8, 0x009ff702, 0xb2009fcf, + 0x223f3e9f, 0xd902f900, 0x0000140c, 0xa0b299bf, 0x08c89ab8, 0x1a277e00, 0xbb010900, 0xa9fd0490, + 0x0bacf004, 0x02f901fb, 0x00140cd9, 0x8f9ebf00, 0xcf01c000, 0x99c700f9, 0x0099b34c, 0x90b301bb, + 0x02f8f501, 0x0022b33e, 0xc700f9cf, 0x99b34c99, 0xb3019700, 0xf8f50190, 0x22c83e02, 0x00f9cf00, + 0xb34c99c7, 0x01600099, 0xf50190b3, 0xdd3e02f8, 0xf9cf0022, 0x4c99c700, 0x310099b3, 0x0190b301, + 0x3e02f8f5, 0x7e0022f2, 0xd9007624, 0x00800000, 0xf49409ff, 0x317e070b, 0x0cd90026, 0xbf000014, + 0xc0008f9e, 0x00f9cf01, 0xb34c99c7, 0x00dc0099, 0xf50190b3, 0x253e02f8, 0xf9cf0023, 0x4c99c700, + 0xb80099b3, 0x0190b300, 0x3e02f8f5, 0xcf00233a, 0x99c700f9, 0x0099b34c, 0x90b30081, 0x02f8f501, + 0x00234f3e, 0xc700f9cf, 0x90b34c99, 0x90b35700, 0x02f8f601, 0x0023643e, 0x0065f57e, 0x000000d9, + 0x9409ff40, 0x7e070bf4, 0xd90067e7, 0x02000000, 0x000000df, 0xb409ff04, 0xf4940fff, 0xbffd060b, + 0x0000df05, 0x0fff0800, 0x060bf494, 0xd905bffd, 0x0000140c, 0xaab89abf, 0x7e0008c4, 0xfb0083ed, + 0xc2008901, 0x0099cf01, 0x95049dff, 0x94b31f09, 0x783eae01, 0xefb80023, 0x890008a4, 0xf601c100, + 0xf1df009f, 0xb8800000, 0x02010099, 0xcf009ff7, 0x9fb2009f, 0x0023643e, 0x01c20089, 0x8f009dcf, + 0x3e01c000, 0xb800234f, 0x000890ef, 0x01c10089, 0xdf009ff6, 0x800000f1, 0x010099b8, 0x009ff702, + 0xb2009fcf, 0x233a3e9f, 0xc2008900, 0x0099cf01, 0xd9049dff, 0x01000000, 0xf59409ff, 0x3efed00b, + 0xb8002307, 0x000898ef, 0x01c10089, 0xdf009ff6, 0x800000f1, 0x010099b8, 0x009ff702, 0xb2009fcf, + 0x22f23e9f, 0xc2008900, 0x009dcf01, 0x01c0008f, 0x0022dd3e, 0x0884efb8, 0xc1008900, 0x009ff601, + 0x0000f1df, 0x0099b880, 0x9ff70201, 0x009fcf00, 0xc83e9fb2, 0x008f0022, 0xf9cf01c0, 0x4c99c700, + 0x2e0090b3, 0xf60190b3, 0x9a3e02f8, 0xf9cf0024, 0x4c99c700, 0x0e0090b3, 0xf60190b3, 0xae3e02f8, + 0x008a0024, 0xaacf01c2, 0x01aac700, 0xafb800f8, 0x89000380, 0xf601c100, 0xf1df009f, 0xb8800000, + 0x02010099, 0xcf009ff7, 0x9fb2009f, 0x0024ae3e, 0xa93382f9, 0xbd008700, 0x2938d704, 0x14bd0000, + 0x01c00083, 0x01c10086, 0x0000f1d5, 0xc2008480, 0x987abf01, 0x0cb2017b, 0x0039797e, 0xf401a4f0, + 0x0bb2480b, 0xd4bdc4bd, 0x137e080a, 0xa2b2001f, 0x0024967e, 0x3300a433, 0x04002ab8, 0x0039cf00, + 0xb34c99c7, 0x00c60099, 0xf50190b3, 0x3d3e02f8, 0x39cf0025, 0x4c99c700, 0xa30099b3, 0x0190b300, + 0x3e02f8f5, 0x90002552, 0x11910100, 0x2404b300, 0x0014b3a4, 0x25f73ea0, 0xd804bd00, 0x00002938, + 0x008314bd, 0x008701c0, 0xf1d601c1, 0x85800000, 0x0401c200, 0x988abffe, 0x0cb2018b, 0x0039797e, + 0xf401a4f0, 0x0bb2460b, 0xd4bdc4bd, 0x137e080a, 0xa2b2001f, 0x0024967e, 0x3100a433, 0x04002ab8, + 0x0039cf00, 0xb34c99c7, 0xb35d0090, 0xf8f60190, 0x25c13e02, 0x0039cf00, 0xb34c99c7, 0xb33b0090, + 0xf8f60190, 0x25d53e02, 0x01009000, 0xb3001191, 0xb3a62404, 0x3da20014, 0xcf81fba4, 0xb5f0004b, + 0x3cfd7e01, 0x25673e00, 0x006af600, 0xcf0035f7, 0x523e0039, 0x5bcf0025, 0x04b4fd00, 0x003cfd7e, + 0x0025e93e, 0xf7007af6, 0x39cf0036, 0x25d53e00, 0x8f02f900, 0xcf01c000, 0x99c700f9, 0x0090b34c, + 0x0190b34f, 0x3e02f8f6, 0xcf002637, 0x99c700f9, 0x0090b34c, 0x0190b32a, 0x3e02f8f6, 0x7e00264b, + 0xc40026af, 0x0bf43009, 0x27087e07, 0x4009c400, 0x7e3d0bf4, 0x3e00271e, 0x890026ad, 0xcf01c200, + 0x09c40090, 0xde0bf401, 0x00265f3e, 0x01b0488f, 0x01c10089, 0xdf009ff6, 0x800000f1, 0x010099b8, + 0x009ff702, 0xb2009fcf, 0x264b3e9f, 0x8f01fb00, 0xcf01c000, 0x99c700f9, 0x0090b34c, 0x0190b322, + 0x3e02f8f6, 0xcf0026b3, 0x99c700f9, 0x0090b34c, 0x0190b339, 0x3e02f8f6, 0x8f0026c7, 0x8901ad24, + 0xf601c100, 0xf4bd009f, 0x010099b8, 0x009ff600, 0x0000f2df, 0x0099b880, 0x9ff60202, 0x009fcf00, + 0xc73e9fb2, 0x00f80026, 0x01ad048a, 0x507eb4bd, 0x848a003d, 0xb4bd01ad, 0x003d507e, 0x008f00f8, + 0xf9cf01c0, 0x4c99c700, 0x220090b3, 0xf60190b3, 0x223e02f8, 0xf9cf0027, 0x4c99c700, 0x390090b3, + 0xf60190b3, 0x363e02f8, 0xa48f0027, 0x008901ad, 0x9ff601c1, 0xb8f4bd00, 0x00010099, 0xdf009ff6, + 0x800000f2, 0x020099b8, 0x009ff602, 0xb2009fcf, 0x27363e9f, 0xe400f800, 0xc7ff00bf, 0xaeb2f0b9, + 0xdfd59fff, 0x0000055c, 0x0027ab3e, 0x1bf49b26, 0x01f9581a, 0x1bf49d66, 0x3df97f12, 0x08e975a4, + 0x7501ff58, 0x00f809ef, 0x3f04ff90, 0x009433f9, 0xf8010adf, 0x0aa9b200, 0x00b0b302, 0x3db92008, + 0xf900f8a4, 0xb3a0b202, 0x986500a0, 0x90b305a9, 0x0cd95e00, 0xbf000014, 0xe8aab89a, 0x277e0004, + 0xa9e7001a, 0x9ab30168, 0xb34c0fff, 0xb6470090, 0xaab314a5, 0xb3400fff, 0x983b00a0, 0x94b6050e, + 0x0caf940c, 0xe9a0a43d, 0xbf050e98, 0xf0f9bce9, 0x9801efb5, 0x94bd070f, 0x0998f9a0, 0x070f9805, + 0x999299bf, 0x01f9b501, 0x0028343e, 0x343e350a, 0x2e0a0028, 0xaf1801fb, 0x18aebf09, 0x44d908ab, + 0xf0008800, 0xeeb801f4, 0xbc003969, 0xea94f0ff, 0x01b4f002, 0xfd05b9fd, 0x877e05bf, 0xa43d001a, + 0x22f900f8, 0xb132a0b2, 0x350ac2b2, 0x690000b3, 0x94b309bf, 0x09986100, 0x0094b301, 0xe2048a5a, + 0x1a277e00, 0xff1ec400, 0xa601a9c4, 0x091bf49e, 0xc73e943d, 0x0f180028, 0xf0f30908, 0xabc501e4, + 0x01f4f002, 0xb604b9fd, 0xfe0902f4, 0x8a05bffd, 0xfd00e204, 0xbefd04b9, 0x1a877e05, 0xe2048a00, + 0x1a277e00, 0xb3010900, 0x20060020, 0x3ea43d29, 0x0a0028d5, 0xf421fb01, 0xdcdff830, 0xf9000005, + 0xfeffbf52, 0x99900149, 0xa0a3b21c, 0x72b0b29f, 0x0ad4b2c2, 0x0039b335, 0xc97300c7, 0xb300ba00, + 0x00b500d9, 0x9db339bf, 0x9800b400, 0x9db30139, 0x8a00ac00, 0x7e00e208, 0xc4001a27, 0x0bf401a9, + 0xa2a9e70d, 0x0294b602, 0xfe0209bb, 0x3ab2014c, 0xcc90b43d, 0x28627e1b, 0x00ad3300, 0x00890083, + 0x01c43000, 0xbc040503, 0x19c40009, 0x0209bbff, 0x277e0ab2, 0x19c4001a, 0xf259bcff, 0xffff29e4, + 0x1df4f9a6, 0xff2fe407, 0xbdfe32ff, 0x29833ef4, 0x90913c00, 0xb60394f0, 0xa9bc0394, 0xf9493c95, + 0x3201ff90, 0xf4fe26f9, 0xe9c4ea08, 0x040090ff, 0x7302297b, 0xbc0d0020, 0x143d4049, 0x0029503e, + 0x900149fe, 0x9b3f1b99, 0xc4bd3ab2, 0x0028627e, 0x0029bc3e, 0xbc3e020a, 0x010a0029, 0x900149fe, + 0x9fbf1c99, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf90855fb, 0xb2350902, 0x00a0b3a0, + 0xbdb43d1a, 0x28627ec4, 0x33a93200, 0xb20c00a4, 0x28367e0a, 0x32a93200, 0xf401fb9a, 0xdcd9f430, + 0xf9000005, 0xfe99bf12, 0xff90014f, 0x03e84b10, 0xfc7ef9a0, 0xa0b20016, 0x90014afe, 0xa1b208aa, + 0x0015817e, 0x00e5a08a, 0x001a277e, 0xf400a6b0, 0x1ab21c1f, 0x00159c7e, 0x0df4a0a6, 0x3e040a09, + 0x7e002a4d, 0x3e00000e, 0x3d002a24, 0x0149fea4, 0xbf109990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, + 0x3a317e07, 0x0c15fb00, 0xad5802f9, 0x58af3f01, 0xb0b202a9, 0xffffdce4, 0xf003f4f0, 0xf4b60093, + 0x909cbc12, 0x000000de, 0x01999280, 0xf005fefd, 0xf9ffff94, 0x00d073b5, 0x01cf9218, 0x01000089, + 0xff08f4b6, 0xf4f195b9, 0x9fffffff, 0x01aa18b5, 0xf401a9c4, 0x00890a0b, 0xb9fd0200, 0xffa4f005, + 0xf410a9c4, 0x00d90b0b, 0xfd080000, 0xa9c405b9, 0x0b0bf404, 0x000000d9, 0x05b9fd20, 0x00e5a08a, + 0x001a877e, 0xfb7e0ab2, 0x01fb0029, 0xdff830f4, 0x000005dc, 0xffbf42f9, 0x900149fe, 0xa3b21899, + 0xb1729fa0, 0x2000c073, 0x09ffdfc4, 0x029fbb40, 0xffffcfe4, 0xbb0294b6, 0xbfe4029f, 0xf9a6ffff, + 0x00b60cf5, 0x09ffdac4, 0xff12e440, 0x029abbff, 0xa60294b6, 0xa10cf529, 0x00c07300, 0xa2c9e756, + 0x03c0c401, 0xb8409abc, 0x0039284a, 0x7e02a4b6, 0xf0001a27, 0x0994ff04, 0x05a9bb03, 0x900149fe, + 0x9aa01499, 0x90bb0409, 0xf492a602, 0x19e4070d, 0x9c72ffff, 0xf002197b, 0x3ab20093, 0xbc014bfe, + 0xbb903039, 0x00c3f014, 0x000b7e7e, 0xb8014a90, 0x003928a9, 0x940144fe, 0x44900292, 0x2bcc3e14, + 0x70107200, 0x0df40416, 0xb2040005, 0x1a277e2a, 0xff09e400, 0x7b4aa0ff, 0x3ab20210, 0xbc042290, + 0x4bb23039, 0xffff0ce4, 0x000b7e7e, 0xd5001473, 0xd83ea43d, 0x020a002b, 0x900149fe, 0x9fbf1899, + 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf40845fb, 0xdcdff830, 0xf9000005, 0xfeffbf52, + 0x99900149, 0xa0a3b21c, 0x0ab1729f, 0x00b67102, 0x450cf401, 0x820144fe, 0x9000e4a0, 0x54bd1844, + 0x002c503e, 0x107245a0, 0xf4041670, 0x0400050d, 0x0ce43bb2, 0x4ab2ffff, 0x000b7e7e, 0x2ab24bbf, + 0x9002107b, 0x03f00422, 0x1a877e00, 0x3030bc00, 0xd4001473, 0x49fea43d, 0x1c999001, 0xdcd99fbf, + 0xbf000005, 0xf4f9a699, 0x317e070b, 0x55fb003a, 0xb252f908, 0x58c5b2b1, 0xb25802b4, 0x00a0b301, + 0xff43e454, 0xff20e4ff, 0x0034b3ff, 0x0004b30c, 0x2cd13e0c, 0x0000b300, 0x72dab210, 0x2bf37e2b, + 0x00a43300, 0x8b1ab232, 0x7e07a120, 0x33002a68, 0xb32400a4, 0xb0200030, 0xdcf00006, 0x01d6f00b, + 0x4b725ab2, 0xd4362c72, 0x2aec7e05, 0x2cd33e00, 0xfb350a00, 0xf830f451, 0x0005dcdf, 0xbf12f900, + 0x0149feff, 0xfe0c9990, 0x9fa00140, 0xb2080090, 0x7e0cb2b1, 0xbf004526, 0x02f9580f, 0xf003ff98, + 0x94b60093, 0x2d163e0c, 0xf491a600, 0xff98150b, 0x0099b806, 0xf4b30010, 0x350af300, 0x002d353e, + 0x9802fe98, 0xffbf05f9, 0xa6909fbc, 0x089cf09e, 0x320196f0, 0x0149fe9a, 0xbf0c9990, 0x05dcd99f, + 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0815fb00, 0xdfe030f4, 0x000005dc, 0xffbf82f9, 0xfe09b1b0, + 0x99900149, 0x0140fe40, 0x00909fa0, 0xb2a4b23c, 0x45267e0c, 0x5803bf00, 0x31980239, 0x0093f003, + 0x3e0c94b6, 0xb4002d97, 0x9ea609e0, 0x98130bf4, 0x99b80611, 0xb3001000, 0x3ef00014, 0x98002f69, + 0x1f980519, 0x041e9803, 0xbc0395b6, 0x2ea6209f, 0xfe4f0cf4, 0x4ab20143, 0xb2383390, 0xb2010c2b, + 0x28d77e3d, 0x33a03200, 0x01a400ad, 0x004f39bf, 0x014efeff, 0xbc34ee90, 0x9ffd9099, 0xb24ab205, + 0xa0ebb22c, 0x7e040de9, 0x3200406b, 0x00ad33a0, 0x1998017e, 0x01999005, 0x3e0519b5, 0xd9002f6b, + 0x0000297c, 0xfe049e98, 0x99900149, 0xa09fb23c, 0x2e213e9e, 0x09191800, 0x13009033, 0xa0041198, + 0xb3f1bff1, 0x3ef20014, 0x35002f85, 0x593e0839, 0xb918002e, 0x00903308, 0x04bb9813, 0x1bbf1ba0, + 0xf200b4b3, 0x002f693e, 0x4ab2bbbf, 0x003fb97e, 0xad33a032, 0xbf011900, 0x011f9811, 0x42fe3bbf, + 0xb54ab201, 0x1958013f, 0x30229004, 0x2db2040c, 0x7e043975, 0x320028d7, 0x00ad33a0, 0x1cbf00f2, + 0x2bb24ab2, 0x6b7e040d, 0xa0320040, 0xdf00ad33, 0xd92fbf00, 0x7fffffff, 0x4ab22bb2, 0xa004f9fd, + 0x0d3cbf2f, 0x406b7e04, 0x33a03200, 0x00c000ad, 0x98023958, 0x47fe0312, 0x0148fe01, 0x980093f0, + 0x77900331, 0x0c96942c, 0x3e288890, 0xb4002f60, 0x6ea609e0, 0xbf0a1bf4, 0x01999019, 0x1b9819a0, + 0x9815bf01, 0x4ab20513, 0x7db2040c, 0x0028d77e, 0xa100ad33, 0xde7fbf00, 0x00ffffff, 0xff3035bc, + 0x00de943e, 0xfdff0000, 0x9ffd04fe, 0x9879a005, 0x4ab2012c, 0x040d7bb2, 0x00406b7e, 0x7500a433, + 0x1b9823a0, 0x0c4ab203, 0x928db204, 0xd77e04bb, 0xa4330028, 0x2c985f00, 0xb24ab203, 0x92040d8b, + 0x6b7e04cc, 0xa4330040, 0x1f984b00, 0xb594bd02, 0x66b80529, 0xb5001000, 0x2298022f, 0x06119806, + 0x6f001db3, 0x2f6b3eff, 0xfe350000, 0x99900149, 0xd99fbf40, 0x000005dc, 0x0a3299bf, 0x0bf4f9a6, + 0x2f973e1d, 0x0141fe00, 0x1190fea0, 0x2e3e3e3c, 0x3ea03200, 0x7e002f6b, 0xfb003a31, 0x02f92085, + 0xa0b3a0b2, 0xa9985100, 0x0090b306, 0x140cd94a, 0x9abf0000, 0x04e0aab8, 0x1a277e00, 0xffa9e400, + 0xff9ab30f, 0x90b3380f, 0xaae73300, 0xaab3016c, 0xb32b0fff, 0x982600a0, 0x94b6060e, 0x0caf940c, + 0xe9a0a43d, 0xbf060e98, 0xf0f9bce9, 0x3e01efb5, 0x0a002ffb, 0x2ffb3e35, 0xfb2e0a00, 0xd830f401, + 0x0005dcdf, 0xbf82f900, 0x0149feff, 0xb2489990, 0xb39fa0a6, 0x982100a0, 0xfd0906a0, 0xbf920bbf, + 0xf4f9a601, 0x0f98110c, 0xa6ff0901, 0x070bf4f9, 0x1100f4b3, 0x020502f8, 0x7d006db3, 0x32c23e02, + 0x10bb9200, 0x7cdd100c, 0x7e000029, 0x320028d7, 0x00ad33a5, 0x7cda0264, 0xdb000029, 0x00000068, + 0xa87e080c, 0xadb3000b, 0x98027e00, 0x0fbf0109, 0x18f5f9a6, 0xfee40278, 0x1bf50fff, 0x6f980270, + 0x0149fe06, 0x3d449990, 0xb0ffbf84, 0x9ea00af1, 0x91b094bd, 0x329f3e0b, 0x0ba43d00, 0x384c7e14, + 0xb3a3b200, 0xf80c00a4, 0x3e050502, 0xb40032b5, 0x89c40ae0, 0x0c94b6ff, 0xbdb09ebc, 0xb5aba094, + 0xb9e404a9, 0x1bf50fff, 0x4dfe0224, 0x0c6ab201, 0x44dd9004, 0x0028d77e, 0x0a00a033, 0xb13ea532, + 0x90b40032, 0xff94f111, 0x0239750f, 0xe71190b4, 0x75016c99, 0x90b40339, 0x1f95b611, 0xb4083935, + 0xf9e411f0, 0x9ab30fff, 0xe7130fff, 0xb3016cf9, 0x0a0fff9a, 0x39350109, 0xb339bf09, 0x00900099, + 0x00297cdf, 0x0dfb1800, 0x4a049990, 0x91b00ffc, 0xffb4f009, 0x0016bb7e, 0x743d94bd, 0x090d91b0, + 0x94a9fffc, 0x3e0c91b0, 0x3d003277, 0x7e1c0ba4, 0xb200384c, 0x00a4b3a1, 0x0002f80c, 0x32de3e05, + 0x0cb0b400, 0x7eff7ac4, 0xbd0016fc, 0x061eb5e4, 0x0c09b0b4, 0x014dfe04, 0xbc40dd90, 0x6ab2b0ba, + 0x7e011bb5, 0x320028d7, 0x00ad33a0, 0x90b40155, 0xffffdf10, 0x9ffd00ff, 0xa619a004, 0x071bf49f, + 0x19a094bd, 0xb3011b98, 0xf80c00b4, 0x3e020002, 0xb40032de, 0x3f180ce0, 0x01b99208, 0xbc04b290, + 0xf033409e, 0x39180e00, 0x33350009, 0x0088009d, 0xbd042990, 0x0414b5f4, 0xb50319b5, 0x5d3e051f, + 0x6ab20032, 0x040c2bb2, 0x90014dfe, 0xd77e3cdd, 0xa0320028, 0xea00ad33, 0x0f90b400, 0xb3789fc7, + 0xfe2806f4, 0x6ab2014d, 0xb2042b90, 0x38dd904c, 0x00459a7e, 0xc800ad33, 0xb419bf00, 0x9fbc0ef0, + 0x3e19a090, 0xb3003250, 0xde2907f4, 0x00ffffff, 0x90049efd, 0x19b5042b, 0x0414b502, 0xb2031bb5, + 0x906ab24c, 0x9a7e141d, 0xa0320045, 0x0032583e, 0xa6042290, 0x8d0df424, 0x86000d33, 0x03399800, + 0x0b0094b3, 0x3e0331b5, 0xb4003271, 0xf1b50df0, 0x01771006, 0xde0d11b0, 0x0000297c, 0x260de918, + 0xca08f579, 0x04e998fe, 0x0b0094b3, 0x3e04e3b5, 0xb4003299, 0xf3b50bf0, 0x01881004, 0xde0b31b0, + 0x0000297c, 0x260ce918, 0xf008f589, 0x32c23efd, 0x00503300, 0x06699811, 0x9fa0ff0f, 0xb5066998, + 0x49fe019f, 0x48999001, 0xdcd99fbf, 0xbf000005, 0xa65a3299, 0x1f0bf4f9, 0x0032f03e, 0x0532a032, + 0x0032b13e, 0xb53e3505, 0x02050032, 0x0032b53e, 0x003a317e, 0xf42885fb, 0xdcdff430, 0xf9000005, + 0xfeffbf22, 0x99900149, 0x0142fe14, 0x94bd9fa0, 0xa00c2290, 0x3da37e29, 0x00a03300, 0xda040b56, + 0x00002944, 0x2db2bcb2, 0x0042d77e, 0xa433a032, 0x41fe4300, 0x10119001, 0x8e7e1ab2, 0xa0320033, + 0x3100a433, 0x2bbf1cbf, 0x24d1a4bd, 0x7e000014, 0xa000b06c, 0x00a0b31a, 0x7eb43d1a, 0xb300b104, + 0xbf1200a0, 0x7eff001a, 0x3e00b63b, 0x00003371, 0x0149feff, 0xbf149990, 0x05dcd99f, 0x99bf0000, + 0xf9a60a32, 0x7e070bf4, 0xfb003a31, 0x0e090c25, 0xa43da9a0, 0x30f400f8, 0x05dcdfd8, 0x62f90000, + 0x30f4ffbf, 0x0149fef4, 0xa04c9990, 0xb2a93f9f, 0x01a398a6, 0x0d019033, 0x60489d33, 0x35a33e03, + 0x04301800, 0x1b010d33, 0x03329801, 0x3d043198, 0x10dc4ba4, 0xd501004c, 0x00000644, 0x0038327e, + 0xa4b35aa0, 0x02f80c00, 0x1a3e0501, 0x49fe0037, 0x28999001, 0x00299cd4, 0xb51cb200, 0x91b50741, + 0x352bb201, 0x42b51540, 0xbd92a006, 0x10dc4ed4, 0x0020d07e, 0xad33a132, 0xbf015900, 0x33993f59, + 0x980d0090, 0x95f00149, 0x0149b508, 0x000644d9, 0x1899bf00, 0x90336999, 0x9cdf1300, 0x98000029, + 0x95f101f9, 0xf9b54000, 0x299cda01, 0x027e0000, 0x3098009c, 0x01027e02, 0x8aa3d900, 0xacb20000, + 0xb20091b0, 0xbdb4bd0d, 0x2e70da04, 0x01b00000, 0x08013001, 0xc87e010e, 0x9cd90013, 0xdf000029, + 0x1e000000, 0xfe509035, 0x99900149, 0x0142fe34, 0x22909fa0, 0xb2010a38, 0x94ee7e2b, 0x1fa43300, + 0xc42bbf1b, 0x1bf401b9, 0x01b5f014, 0x2ba0010a, 0x0095097e, 0x061fa033, 0xb4bd09f8, 0x097e020a, + 0x9cda0095, 0x7e000029, 0xfe009ab1, 0xb4bd014a, 0x010dc4bd, 0x7e34aa90, 0x3e0075b0, 0x33003574, + 0xd9320204, 0x00000644, 0xa0b39abf, 0xb4d97f00, 0x98000029, 0x9bbf019c, 0x9cd9f43d, 0xbd000029, + 0x159f35d4, 0x7e10dc4e, 0x320020d0, 0x356f3ea1, 0x030d3300, 0x0e7e0207, 0x39180001, 0x00903308, + 0x033e9824, 0x002a3cd9, 0x2a44df00, 0x9ea00000, 0xb5043e98, 0x3998019e, 0x98f9a005, 0xfeb5063e, + 0x1c391801, 0x21009033, 0x00299cdf, 0x08399800, 0x982dfe98, 0x9efd2efd, 0x2df9b505, 0xfd093998, + 0xf9b5059d, 0x01087e2e, 0x3e143d00, 0x33003574, 0x01ab001d, 0xb2016b18, 0x0f817e3a, 0xfe020900, + 0xff90014f, 0x3df92048, 0x02f93594, 0x09033318, 0xb2b4bd04, 0x03f335fa, 0x7e01f935, 0x3e000f71, + 0xfe00371a, 0x41fe0140, 0x44009001, 0xfe401190, 0x0ab20142, 0xb23c2290, 0x3d2cb21b, 0x75b07ed4, + 0x02399800, 0x010a0fbf, 0x1bf4f9a6, 0x0524de3c, 0xe93f0000, 0x0e009033, 0x1e0a943d, 0x063ee920, + 0xffd90036, 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0x03e84b00, 0x0016fc7e, 0x0200aab8, + 0x0aa5b600, 0x3e000af6, 0x40003b2f, 0x09cf0800, 0x03e84b00, 0x0016fc7e, 0x0200aab8, 0x0aa5b600, + 0xf601aa92, 0x0049000a, 0x009fcf09, 0xd9009af6, 0x00002928, 0xb50a004f, 0xf9cf0191, 0x0195f000, + 0x3e00f9f6, 0x4e003b75, 0xe9cf0a00, 0xfdfe0f00, 0xe9f6049f, 0x08004f00, 0xbd00f9cf, 0x00f9f694, + 0xcf09004f, 0x94bd00f9, 0xbd00f9f6, 0x2928d9f4, 0x9fb50000, 0xfba43d01, 0x2928d911, 0x99980000, + 0x0194b301, 0x68147e0a, 0xf800f800, 0xf900f802, 0x8aa0b202, 0x7e08d114, 0x3f001a27, 0x08aac709, + 0xa6ff94f0, 0x0bacf0a9, 0x02f901fb, 0x0189008f, 0xf000f9ce, 0xf9f78095, 0x43004e00, 0x0f00e9ce, + 0x049ffdfe, 0xd000e9f7, 0x0000140c, 0xaab80abf, 0x7e00034c, 0xbf001a27, 0x03abc509, 0x034c9ab8, + 0x1a877e00, 0xf901fb00, 0xc0008f12, 0xf430f401, 0xc700f9cf, 0x99b34c99, 0xb3008500, 0xf8f50190, + 0x3bf03e02, 0x00f9cf00, 0xb34c99c7, 0xb35f0090, 0xf8f60190, 0x3c053e02, 0x19e87e00, 0xb204bd00, + 0xbdc4bd0b, 0x7e0b0ad4, 0x90001f13, 0xa1900100, 0x7e1ab268, 0xe4001a27, 0xb30e00ab, 0x0b0e00be, + 0x877e1ab2, 0x04b3001a, 0x94bdd924, 0x9130b4bd, 0x0091b008, 0xbd0191b0, 0x3dd4bdc4, 0x1410dae4, + 0xc87e0000, 0x9c3e0013, 0x0089003c, 0x99cf01c2, 0x0194f000, 0x3e280bf4, 0x8f003c19, 0x8902851c, + 0xf601c100, 0xf1df009f, 0xb8800000, 0x02010099, 0xcf009ff7, 0x9fb2009f, 0x003c053e, 0xfb0c30f4, + 0xf430f411, 0x1c8ab4bd, 0x877e0285, 0x027e001a, 0xe7d90001, 0xb000003b, 0x94bd0091, 0x9130acb2, + 0x0191b008, 0x001410da, 0x4db4bd00, 0x010e2710, 0x0013c87e, 0xf80c30f4, 0x22067e00, 0x7e00f800, + 0xf80021ef, 0x21d87e00, 0x7e00f800, 0xf8002285, 0x22a67e00, 0x7e00f800, 0xf800530d, 0xc0008f00, + 0x00f9cf01, 0xb34c99c7, 0xb3220090, 0xf8f60190, 0x3d013e02, 0x00f9cf00, 0xb34c99c7, 0xb3330090, + 0xf8f60190, 0x3d153e02, 0xc1008900, 0x009af601, 0x010099b8, 0x009bf600, 0x0000f2df, 0x0099b880, + 0x9ff60202, 0x009fcf00, 0x153e9fb2, 0x00f8003d, 0x01c0008f, 0xc700f9cf, 0x90b34c99, 0x90b32200, + 0x02f8f601, 0x003d543e, 0xc700f9cf, 0x90b34c99, 0x90b33300, 0x02f8f601, 0x003d683e, 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0x7e005249, + 0x7e004d7d, 0x7e004df2, 0x7e005208, 0x7e005216, 0x7e0053af, 0x7e0053d2, 0x7e0053e7, 0x7e0053fc, + 0x7e005438, 0x7e00544d, 0x7e00591d, 0x7e00706d, 0x7e005462, 0x7e004ea6, 0x330059ae, 0xf80600a0, + 0x2c30f402, 0x30d911fb, 0xbf000014, 0x2e88da99, 0x99980000, 0xf895f905, 0xf8400a00, 0x0070df00, + 0x00492000, 0x009ff607, 0xcf03004e, 0xff4f00e9, 0x049ffdcf, 0x800095f1, 0x8f00e9f6, 0x4900b071, + 0x9ff60400, 0x15008f00, 0x00f9ce02, 0xf70195f0, 0x00f800f9, 0xf820004a, 0x01004f00, 0xf000f9ce, + 0xf9f71095, 0x07004f00, 0xf000f9ce, 0xf9f71095, 0x04004f00, 0xf000f9ce, 0xf9f71095, 0xd900f800, + 0x00001430, 0x8ada99bf, 0x9800002e, 0x95f90899, 0x367e00f8, 0xa433004e, 0xaddf1100, 0x49deadde, + 0x9ff61000, 0x7e02f800, 0x7e004e54, 0x7e004e15, 0xf8004e69, 0x90008900, 0x0099cf00, 0xf40194f0, + 0x0089150b, 0x9fcf00a5, 0xf0ef0e00, 0xfefd07f5, 0x009ff604, 0x008900f8, 0x9fcf0090, 0x01f9c400, + 0x3d071bf4, 0xc700f8a4, 0x96b024f9, 0x0b9cf002, 0x00f89a32, 0x0089050f, 0x9ff60180, 0xb8060f00, + 0x00010099, 0xf8009ff6, 0x02008900, 0x0099cf01, 0x1000008f, 0xf4049ffd, 0x34da181b, 0x7e008204, + 0xf0001a27, 0x1bf401a4, 0x0a02f809, 0x3d00f824, 0xd900f8a4, 0x00001430, 0x34da99bf, 0x98000014, + 0x95f90e99, 0x1e0a00f8, 0x00b99e7e, 0x0600a033, 0x00f802f8, 0x0100008f, 0xf6590049, 0x00f8009f, + 0x00900089, 0xf00099ce, 0x0bf40194, 0xf1008e20, 0x00e9ce00, 0x9ffdef0f, 0x00e9f704, 0x5200eeb8, + 0x00e9ce02, 0xf7049ffd, 0x00f800e9, 0x7e0a004a, 0xe7001a27, 0xb30114aa, 0x4f1e06a4, 0xf9cf4f00, + 0xe899c700, 0x110f94b3, 0xf000f9cf, 0x9cf0ff94, 0xf89a320b, 0xf8a43d00, 0x8902f900, 0xce009000, + 0x94f00099, 0xd70bf501, 0x514f7e00, 0xbdb4bd00, 0x0ad4bdc4, 0x1f137e09, 0xc8aa9000, 0x001a277e, + 0xa0b2010c, 0xb4bdd4bd, 0x137e0a0a, 0xf00b001f, 0xffc8aa90, 0x877eb40b, 0xc4bd001a, 0xb4bdd4bd, + 0x137ea4bd, 0xb4bd001f, 0xaab8a0b2, 0x7e000528, 0xb8001a87, 0x0005300a, 0x877eb4bd, 0x0ab8001a, + 0xbd000534, 0x1a877eb4, 0x0c0ab800, 0x040b0001, 0x001a877e, 0x01000ab8, 0x7e4a0b00, 0xb8001a87, + 0x0001040a, 0x877e4a0b, 0x0ab8001a, 0x0b000108, 0x1a877e42, 0x64009000, 0x277e0ab2, 0xfe09001a, + 0xb2b4a9ff, 0x1a877e0a, 0xe2f08a00, 0x1a277e00, 0x40abc500, 0x00e2f08a, 0x001a877e, 0x00e2f48a, + 0x001a277e, 0x8a40abc5, 0x7e00e2f4, 0x7e001a87, 0xbd005296, 0x8a0089f4, 0x009ff603, 0x12f901fb, + 0x00900089, 0xf00099ce, 0x0bf50194, 0xb4bd009e, 0xd4bdc4bd, 0x137e0b0a, 0x010c001f, 0xa1b2d4bd, + 0x0c0ab4bd, 0x001f137e, 0x1a90a0b2, 0x1a277e1c, 0x10abc500, 0x7e1c0a90, 0xb8001a87, 0x00501c1a, + 0x001a277e, 0xb810abc5, 0x00501c0a, 0x001a877e, 0x101c1ab8, 0x1a277e00, 0x10abc500, 0x101c0ab8, + 0x1a877e00, 0x1c1ab800, 0x277e0040, 0xabc5001a, 0x1c0ab810, 0x877e0040, 0x1ab8001a, 0x7e00301c, + 0xc5001a27, 0x0ab810ab, 0x7e00301c, 0xb8001a87, 0x00601c1a, 0x001a277e, 0xb810abc5, 0x00601c0a, + 0x001a877e, 0x00518a7e, 0x008e11fb, 0xe9cf0095, 0xcfff4f00, 0xf1049ffd, 0xf6200095, 0x008f00e9, + 0xf9cf01a1, 0x0195f000, 0x4e00f9f6, 0xe9cf2400, 0x00008f00, 0x059ffd06, 0x7e00e9f6, 0x8f004ec0, + 0xcf009500, 0x95f000f9, 0x00f9f620, 0xffffffdf, 0xc3008900, 0x009ff601, 0x00219c7e, 0x7e0a004a, + 0xc7001a27, 0x34de6ca9, 0x35000014, 0x030907e9, 0x350de935, 0xa9c70ce9, 0x04e93598, 0x3574a9c7, + 0x94bd05e9, 0xb570aac7, 0xea3502e9, 0x02008906, 0x0099cf01, 0x1000008f, 0xf4049ffd, 0x0109080b, + 0x7e0ee935, 0x7e004ffe, 0x3d004f19, 0x8900f8a4, 0xce009000, 0x94f00099, 0x2f0bf401, 0xd4bd010c, + 0x100ab4bd, 0x001f137e, 0x0100008b, 0x7e40aa90, 0xbd001a87, 0x0c0e0ab4, 0x7ed4bd01, 0x0b001f13, + 0x94aa9001, 0x001a877e, 0x12f900f8, 0x00900089, 0xf00099ce, 0x0bf40194, 0xbdb4bd5d, 0x0ad4bdc4, + 0x1f137e0d, 0xbd010c00, 0xbda1b2d4, 0x7e0e0ab4, 0xb2001f13, 0x0c1a90a0, 0x001a277e, 0x9010abc5, + 0x877e0c0a, 0xb4bd001a, 0xd4bdc4bd, 0x137e0f0a, 0xb4bd001f, 0x010ca1b2, 0x100ad4bd, 0x001f137e, + 0x1a90a0b2, 0x1a277e0c, 0x10abc500, 0x7e0c0a90, 0xfb001a87, 0x1430d911, 0x99bf0000, 0x002928da, + 0x11999800, 0x00f895f9, 0xc4bdb4bd, 0xa4bdd43d, 0x003aa97e, 0x30da00f8, 0x3d000029, 0x5e7f7eb4, + 0x2930d900, 0x99bf0000, 0x060094b3, 0x00f802f8, 0x001430d9, 0x3d9fbf00, 0x2e8bda94, 0xa9200000, + 0xf910f998, 0xf8a43d95, 0x140cd900, 0x9abf0000, 0xb803034b, 0x0002dcaa, 0x001a877e, 0x066f448a, + 0x001a277e, 0x000600d9, 0xffa4f100, 0x42408f3f, 0xd99aa00f, 0x00000604, 0x9fa0a43d, 0x30d900f8, + 0xbf000014, 0xda943d9f, 0x00002e8c, 0xf9bfa920, 0xa43d95f9, 0x02f900f8, 0xd4bdc4bd, 0x110ab4bd, + 0x001f137e, 0x0484a0b8, 0x7e0ab200, 0xc5001a27, 0x0ab201ab, 0x001a877e, 0x08b8c08a, 0x001a277e, + 0xa9fffb09, 0xb8c08ab4, 0x1a877e08, 0xb9408a00, 0x1a277e08, 0xffe00900, 0x408ab4a9, 0xb5f008b9, + 0x1a877e02, 0xbd01fb00, 0xbdc4bdb4, 0x7ea4bdd4, 0xd9001f13, 0x00001430, 0x0cd99fbf, 0xa0000014, + 0x2e8eda9a, 0xf9980000, 0xf895f90c, 0xd002f900, 0x0000140c, 0xff0b0abf, 0x08b8aab8, 0x1a877e00, + 0x0b0abf00, 0xbcaab8ff, 0x877e0008, 0x0abf001a, 0xaab8ff0b, 0x7e0008c0, 0xbf001a87, 0xb8ff0b0a, + 0x0008c4aa, 0x001a877e, 0x008b0abf, 0xaab87000, 0x7e0008d4, 0xbf001a87, 0x0000db0a, 0xaab80100, + 0x7e0008a8, 0xbf001a87, 0xffffdb0a, 0xaab80e03, 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0x0005dcd9, 0xa699bf00, 0xa10bf5f9, 0x65ee3e00, 0x60df9000, 0x01c10089, + 0xdf009ff6, 0x800000f1, 0x010099b8, 0x009ff702, 0xb2009fcf, 0x65013e9f, 0xc2008900, 0x0099cf01, + 0xe41095b6, 0xe420009f, 0xb33fff9e, 0xff4500fd, 0x0064d43e, 0x066f448f, 0x01c10089, 0xdf009ff6, + 0x800000f1, 0x010099b8, 0x009ff702, 0xb2009fcf, 0x64bb3e9f, 0xc2008900, 0x0099cf01, 0x20009fe4, + 0x3fff94f1, 0xcc00fdb3, 0x64943efe, 0x6f408f00, 0xc1008906, 0x009ff601, 0x0000f1df, 0x0099b880, + 0x9ff70201, 0x009fcf00, 0x7b3e9fb2, 0x317e0064, 0x35fb003a, 0x64177e0c, 0x3cd97e00, 0xdf00f800, + 0x00000608, 0xf9f430f4, 0xfef0b242, 0x99900149, 0x019fb514, 0x0005dcdf, 0xbdffbf00, 0x3591a014, + 0x01030191, 0x99909320, 0xa0a43208, 0xb23c029f, 0xb2b4bd0a, 0x0b947e2c, 0x35050900, 0x03350102, + 0x08013504, 0x35090435, 0x01350201, 0x8f092003, 0xcf01c000, 0x99c700f9, 0x0099b34c, 0x90b30166, + 0x02f8f501, 0x0066533e, 0xc700f9cf, 0x99b34c99, 0xb3013900, 0xf8f50190, 0x66683e02, 0x00008f00, + 0x0394b6fe, 0xdf95f9ff, 0x00000608, 0x8f03f9b5, 0xcf01c000, 0x99c700f9, 0x0099b34c, 0x90b300ed, + 0x02f8f501, 0x0066933e, 0xc700f9cf, 0x99b34c99, 0xb300c000, 0xf8f50190, 0x66a83e02, 0x00008f00, + 0x0394b6fe, 0xdf95f9ff, 0x00000608, 0x3304f9b5, 0xd9370040, 0x0000140c, 0x008e9fbf, 0xe9cf01c0, + 0x4c99c700, 0x6a0090b3, 0xf60190b3, 0xde3e02f8, 0xf9cf0066, 0x4c99c700, 0x3a0090b3, 0xf60190b3, + 0xf23e02f8, 0x00d90066, 0xbf000014, 0x014bfe9a, 0xbb90080c, 0x006e7e14, 0x0149fe00, 0xbf1c9990, + 0x05dcd99f, 0x99bf0000, 0x0bf5f9a6, 0xe03e00ba, 0x00890067, 0x99cf01c2, 0x0608de00, 0x9fc70000, + 0x1899c710, 0x3515ef35, 0x063e14e9, 0xff900067, 0xc1008960, 0x009ff601, 0x0000f1df, 0x0099b880, + 0x9ff70201, 0x009fcf00, 0xf23e9fb2, 0x00890066, 0x99cf01c2, 0x009fe400, 0xff94f120, 0x00fdb33f, + 0xc13eff40, 0x448f0066, 0x0089066f, 0x9ff601c1, 0x00f1df00, 0x99b88000, 0xf7020100, 0x9fcf009f, + 0x3e9fb200, 0x890066a8, 0xcf01c200, 0x9fe40099, 0x94f12000, 0xfdb33fff, 0x3efec700, 0x8f006681, + 0x89066f40, 0xf601c100, 0xf1df009f, 0xb8800000, 0x02010099, 0xcf009ff7, 0x9fb2009f, 0x0066683e, + 0x003a317e, 0xf90c45fb, 0x0604d902, 0x90bf0000, 0x003cdf7e, 0xf07e010a, 0x010a0024, 0x0065ff7e, + 0x0cb2010a, 0xabb2d43d, 0x003aa97e, 0x0600a033, 0x01fb02f8, 0x0062fc7e, 0x2600a433, 0xc4bdb4bd, + 0x020ad43d, 0x003aa97e, 0xf07ea43d, 0xa43d0024, 0x0065ff7e, 0x00221d7e, 0x003ce57e, 0xf07e00f8, + 0x00f80024, 0xdfcc30f4, 0x000005dc, 0xffbf82f9, 0x900149fe, 0x48fe5499, 0xfe9fa001, 0x99920144, + 0xfef4bd10, 0x46fe0147, 0x019fb501, 0x88909fa0, 0x4c449050, 0x90347790, 0x00d92466, 0xbf000014, 0x014bfe9a, 0xbb90080c, 0x7eff0d44, 0x320000c1, 0x00a433a5, 0x1200b4e9, 0x3433033f, 0x0918e005, - 0x45203404, 0x0f009033, 0x9d33e301, 0x3e008701, 0x18007f43, 0x0b98050a, 0x78e27e02, 0x3ea13200, - 0x18007fb1, 0x2b320801, 0x817e0ab2, 0x040f000f, 0x45354320, 0x024f3503, 0x0c001033, 0x7e011433, - 0x007f863e, 0xb2020998, 0xa07bb24a, 0x08099079, 0xb5019f98, 0x9f98017f, 0x027fb502, 0xb5039998, - 0xa43e0379, 0x0f98007f, 0x08099002, 0x6bb24ab2, 0x9f986fa0, 0x016fb501, 0xb5029f98, 0x9998026f, - 0x0369b503, 0x49351409, 0x0f617e01, 0x7efa3e00, 0x320ab200, 0x0f817e2b, 0x3d050f00, 0x358f2094, - 0x00180289, 0xb2040f03, 0x018f358a, 0xbd038035, 0x0f717eb4, 0x00193300, 0x02f8ff25, 0x007efa3e, - 0x0005dcdf, 0xf4ffbf00, 0x49fefc30, 0xb39fa001, 0xb02c02b0, 0x0cf402b6, 0x01b4b30b, 0x800f3e10, - 0x03b0b300, 0x04b0b32d, 0x3e020e3f, 0xbf008051, 0x8fe43da9, 0x3e0c0000, 0xbf00803d, 0xffff8fa9, - 0xfde43df3, 0x008f049f, 0x3d3e0800, 0xa9bf0080, 0xf3ffff8f, 0x9ffde43d, 0x00008f04, 0x059ffd04, - 0x00804f3e, 0xff8fa9bf, 0xe43df3ff, 0xa0049ffd, 0x0149fea9, 0xdcd99fbf, 0xbf000005, 0xa6ea3299, - 0x070bf4f9, 0x0042e97e, 0xf80430f4, 0xfc30f400, 0xdcd252f9, 0xbf000005, 0xb2b3b229, 0xb2d5b2c4, - 0x0141fea0, 0x0880008a, 0xa0181190, 0x1c227e19, 0xb60a6000, 0x3a6010a5, 0x08802c8a, 0x001c227e, - 0xa5b64a60, 0xbf5a6010, 0xa629bf1f, 0x070bf4f9, 0x0042e97e, 0xf40455fb, 0x22f9fc30, 0x0005dcd1, - 0xb219bf00, 0x0140fea2, 0x08d5008a, 0xa00c0090, 0x1c227e09, 0xf00fbf00, 0x2aa000a3, 0xf9a619bf, - 0x7e070bf4, 0xfb0042e9, 0x30f40425, 0xd122f9fc, 0x000005dc, 0xa2b219bf, 0x8a0140fe, 0x9008d540, - 0x09a00c00, 0x001c227e, 0xa3f00fbf, 0xbf2aa000, 0xf4f9a619, 0xe97e070b, 0x25fb0042, 0xfc30f404, - 0xdcd122f9, 0xbf000005, 0xfea2b219, 0x808a0140, 0x009008d5, 0x7e09a00c, 0xbf001c22, 0x00a3f00f, - 0x19bf2aa0, 0x0bf4f9a6, 0x42e97e07, 0x0425fb00, 0xf9fc30f4, 0x05dcd122, 0x19bf0000, 0x40fea2b2, - 0xd5808a01, 0x0c009008, 0x227e09a0, 0x2aa0001c, 0x19bf0fbf, 0x0bf4f9a6, 0x42e97e07, 0x0425fb00, - 0xf9fc30f4, 0x05dcd122, 0x19bf0000, 0x40fea2b2, 0xd6408a01, 0x0c009008, 0x227e09a0, 0x2aa0001c, - 0x19bf0fbf, 0x0bf4f9a6, 0x42e97e07, 0x0425fb00, 0xf9fc30f4, 0x05dcd122, 0x19bf0000, 0x40fea2b2, - 0x88548a01, 0x0c009008, 0x227e09a0, 0x0fbf001c, 0xa000a3f0, 0xa619bf2a, 0x070bf4f9, 0x0042e97e, - 0xf40425fb, 0x42f9fc30, 0x0005dcd1, 0xb219bf00, 0xb2b2b2a3, 0x0140fec4, 0x0884ac8a, 0xa0140090, - 0x1c227e09, 0xe8a9c700, 0xa9c729a0, 0xb639a0f0, 0x4aa018a5, 0x19bf0fbf, 0x0bf4f9a6, 0x42e97e07, - 0x0445fb00, 0xdffc30f4, 0x000005dc, 0xffbf12f9, 0x900149fe, 0xa0b20899, 0xb1b29fa0, 0x0880888a, - 0x001c227e, 0xb370a9c7, 0xb01a0290, 0x0cf40296, 0x0194b30b, 0x82613e1d, 0x0390b300, 0x0494b308, - 0xc709a011, 0xa4b3b4aa, 0x9a3e1004, 0x94bd0082, 0xb43e09a0, 0xa6b00082, 0x0f0cf404, 0x1801a0b3, - 0x3002a4b3, 0x0082943e, 0x1808a0b3, 0x2410a4b3, 0x0082aa3e, 0xa43e1aa0, 0x03090082, 0x0082a23e, - 0x19a00409, 0xb63ea43d, 0x05090082, 0x0082a23e, 0x19a094bd, 0x49feff0a, 0x08999001, 0xdcd99fbf, - 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x15fb0042, 0xfc30f404, 0x0005dcdf, 0xbf02f900, 0x0149feff, - 0xb2049990, 0x8a9fa0a0, 0x7e088088, 0xc7001c22, 0xa0b370aa, 0xa6b01a02, 0x0b0cf402, 0x1801a4b3, - 0x00830c3e, 0x0803a0b3, 0x0c04a4b3, 0xa43d0aa0, 0x00831a3e, 0xff0a94bd, 0x49fe09a0, 0x04999001, - 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x05fb0042, 0xfc30f404, 0xdcd112f9, 0xbf000005, - 0x0140fe19, 0x08c0408a, 0xa0080090, 0x1c227e09, 0xbf0fbf00, 0x1fa4f019, 0xa60bacf0, 0x070bf4f9, - 0x0042e97e, 0xd90415fb, 0x000005dc, 0x30f499bf, 0x014ffefc, 0x357ef9a0, 0xa4330083, 0xa4bd0a00, - 0x00838f3e, 0x08d32c8a, 0x001c227e, 0xfe12aac7, 0x9fbf0149, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, - 0x0042e97e, 0xf80430f4, 0xfc30f400, 0xdcd222f9, 0xbf000005, 0xfea0b229, 0x008a0141, 0x119008d1, - 0x7e19a00c, 0x89001c22, 0xf1ff0000, 0xffffff04, 0x008ab4a9, 0x0bff08d1, 0x1cb17eb5, 0xbf1fbf00, - 0xa6a43d29, 0x070bf4f9, 0x0042e97e, 0xf40425fb, 0xdcdff830, 0xf9000005, 0xfeffbf62, 0x99900149, - 0xb29c201f, 0x01999096, 0x9fa0a432, 0xb2c4d3b2, 0x7e080aff, 0xd9001c22, 0x40000000, 0x010504bd, - 0x3e14a9ff, 0xbc008451, 0x5abca002, 0x83a97ea4, 0x0014b300, 0x449dda1d, 0x6bb20000, 0xa97e3cb2, - 0xa4330015, 0x09f80c00, 0x583e040a, 0x00900084, 0xf4402601, 0xa43dd40c, 0x900149fe, 0x9fbf2099, - 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf40865fb, 0xdcdff830, 0xf9000005, 0xfeffbf12, - 0x99900149, 0xa0b1b20c, 0x8aabb29f, 0x7e08c040, 0xda001cb1, 0x00008367, 0x00dcb4bd, 0x7e01312d, - 0x0e0015a9, 0x00a03304, 0x0140fe1f, 0xb2080090, 0x82d17e0a, 0x33ae3200, 0xbf0d00a4, 0xf491a609, - 0x3e0e050b, 0x900149fe, 0x9fbf0c99, 0x0005dcd9, 0x3299bf00, 0xf4f9a6ea, 0xe97e070b, 0x15fb0042, - 0xfc30f408, 0x0005dcdf, 0xbf12f900, 0x0149feff, 0xb2089990, 0xb29fa0b0, 0xd1008aa1, 0x1c227e08, - 0x00008900, 0xff04f1ff, 0xb4a9ffff, 0x08d1008a, 0x7eb50bff, 0x8a001cb1, 0xf108d170, 0xdb03ff14, - 0xc0000000, 0xff1014b6, 0xb17eb51b, 0x748a001c, 0x227e08d1, 0x0089001c, 0xa3f00201, 0x009af700, - 0x900149fe, 0x9fbf0899, 0x0005dcd9, 0x3d99bf00, 0xf4f9a6a4, 0xe97e070b, 0x15fb0042, 0xfc30f404, - 0xdcd232f9, 0xbf000005, 0x32c13229, 0xd1708ab0, 0x0000db08, 0x43fec229, 0x10339001, 0xb17e39a0, - 0x748a001c, 0x227e08d1, 0xa4f1001c, 0x02dbfff8, 0xffa22900, 0x708ab5ab, 0xb17e08d1, 0x04f0001c, - 0x0f14f0ff, 0x940c0994, 0x94f1081f, 0x708affff, 0x04b608d1, 0x0000db04, 0x04f0a22a, 0x0509fdff, - 0xfd0501fd, 0x0bff050f, 0x1cb17eb5, 0xbf3fbf00, 0xa6a43d29, 0x070bf4f9, 0x0042e97e, 0xf40435fb, - 0x72f9d430, 0xfe15f0b4, 0x99900149, 0xb5a23220, 0xf0b4019f, 0x32b43214, 0xa0d632c5, 0x05dcdf9f, - 0xffbf0000, 0xb2289990, 0xb39fa0e3, 0x3d0a00e4, 0x872d3e24, 0x3dff0000, 0x32f4bd14, 0x953fbc0e, - 0xf40194f0, 0x0e260d0b, 0x32051bf4, 0x011110f0, 0xb301ff90, 0x30ea10f4, 0x0cf41016, 0xff1fc412, - 0xbcff09c4, 0x76b070f9, 0x0b0df410, 0x020209f8, 0x00872d3e, 0xa97e3ab2, 0x5c320083, 0x4b326d32, - 0x5d7e2a32, 0x3ab20085, 0x0083a97e, 0x08d1148a, 0x001c227e, 0xffff7f49, 0x148ab4a9, 0xb17e08d1, - 0x1a32001c, 0xc43d0b32, 0xef7e640d, 0xa2320083, 0x9d00ad33, 0x7e3ab200, 0x8a0083a9, 0x7e08d114, - 0xe5001c22, 0x8a4080ab, 0x7e08d114, 0x32001cb1, 0x0c0b321a, 0x25a08d01, 0x83ef7e26, 0x33a23200, - 0xb26e00a4, 0x83a97e3a, 0xd1148a00, 0x1c227e08, 0xbf7f4900, 0xff0143fe, 0x0132b4a9, 0x08d1148a, - 0x7e283390, 0x04001cb1, 0x870a3e01, 0xa440bc00, 0x0083a97e, 0x08d1148a, 0x001c227e, 0xb69000bc, - 0x39bc10a5, 0x01111090, 0x10c49a60, 0xf407a6ff, 0x49fede1e, 0x20999001, 0xbf019c98, 0xbd3ab29b, - 0x7e200ed4, 0x330026d8, 0xf80600a0, 0x0149fe02, 0xbf489990, 0x05dcd99f, 0x99bf0000, 0xf9a62a32, - 0x7e070bf4, 0xfb0042e9, 0x30f42c75, 0x05dcd9e8, 0x52f90000, 0x4ffe99bf, 0x2cff9001, 0xf9a0a2b2, - 0x08b8c08a, 0x001c227e, 0xc08aa5b2, 0x5bc508b8, 0x1cb17e04, 0x8335da00, 0xb4bd0000, 0x030d408c, - 0xa97e0400, 0xa9330015, 0x8a00a800, 0x7e08c040, 0xfe001c22, 0x2bb20141, 0xa0281190, 0x7e1ab21a, - 0x32007fe0, 0x00ad33a0, 0x19bf0089, 0x13b2f00f, 0xfd014afe, 0x95f0049f, 0x18aa9001, 0xa4b219a0, - 0xfaf07fd1, 0x15817e02, 0xb23abf00, 0x84737e2b, 0x33a03200, 0xb2213ea4, 0x159c7e4a, 0xf4a1a600, - 0x3abfea0d, 0x737e2bb2, 0xa4330084, 0x0400df3e, 0x0087f83e, 0x3a00a033, 0x900149fe, 0x99bf2899, - 0xfe0141fe, 0x11900142, 0x20229024, 0x2ab219a0, 0x0082d17e, 0x1a00a433, 0x1ab22bbf, 0x007fe07e, - 0x0e00a433, 0x408a1bbf, 0xb17e08c0, 0xc08a001c, 0x5bb208b8, 0x001cb17e, 0x900149fe, 0x9fbf2c99, - 0x0005dcd9, 0x3299bf00, 0xf4f9a60a, 0xe97e070b, 0x55fb0042, 0xdc30f418, 0x0005dcdf, 0xbf82f900, - 0xf830f4ff, 0x900149fe, 0x9fa04c99, 0x920140fe, 0xf4bd0c99, 0xfe2c0090, 0x93b20142, 0xa0019fb5, - 0x1320d89f, 0x22900000, 0x06020748, 0x0c059004, 0x3bb28abf, 0xff0d080c, 0x0000c17e, 0xf400a433, - 0x3f013198, 0x0a943319, 0x011998eb, 0x18041f18, 0x09a00134, 0x98041990, 0x0eb5019e, 0x029e9801, - 0x98020eb5, 0x0eb5039e, 0x04999803, 0x330409b5, 0x302a01f0, 0x08f401f6, 0x02f0330f, 0x03f4332e, - 0x89123eb3, 0x010a1800, 0x18030b18, 0x0d18020c, 0x855d7e04, 0x89303e00, 0x010a9800, 0x7e020b98, - 0x3e0084e1, 0x98008930, 0x4a7e010a, 0x303e0087, 0x59bf0089, 0x18010a18, 0x0c18030b, 0x040d1802, - 0xb0020e98, 0x59980091, 0x0191b001, 0x0085df7e, 0x6000ad33, 0x022a35ff, 0x1e182720, 0xb24b3203, - 0x0126351a, 0x7e032e35, 0xb2000f81, 0x7eb4bd2a, 0x3e000f71, 0xd9008890, 0x000005d4, 0xf9fc30f4, - 0x05dcd112, 0x9abf0000, 0x10db19bf, 0x0c000013, 0x0140fe01, 0xa0080090, 0x72e57e09, 0x89cc7e00, - 0xbf0fbf00, 0xf4f9a619, 0xe97e070b, 0x15fb0042, 0xfc30f404, 0xdcd112f9, 0xbf000005, 0x0140fe19, - 0xda080090, 0x00002d8d, 0x30d909a0, 0xbf000013, 0x20943d9f, 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0xd0b4320c, 0x0fffde0c, 0x004fff00, + 0x0c94b6f0, 0xfff4dfff, 0xfefdf55f, 0x0be0b404, 0xa005f9fd, 0x0af0b4ef, 0x90b4f3a0, 0x0998a009, + 0x7aa73e1f, 0x32060900, 0x1885fb9a, 0x010000d9, 0xffa4f001, 0xb6ffb4f0, 0xb4b614a4, 0xa0a9bc0f, + 0xabbc22f9, 0xb2c0b220, 0x242ab8d1, 0x277e0020, 0x0309001a, 0xb364aac7, 0x090c00a0, 0x04a0b301, + 0x20943d06, 0x142ab809, 0x277e0030, 0x0309001a, 0xb364aac7, 0x090c00a0, 0x04a0b301, 0x20943d06, + 0xf421fb19, 0xdcdff030, 0xf9000005, 0xf4ffbf32, 0x49fefc30, 0x20999001, 0x41fe9fa0, 0x9094bd01, + 0x4efe1c11, 0x9019a001, 0xe9a018ee, 0xd3b2c2b2, 0xb926ff09, 0xfe201bf4, 0x240b0140, 0xb2140090, + 0x87d77e0c, 0xffa4f000, 0x3c1fa4b3, 0x10a000bf, 0x007b6e3e, 0xf000e1b0, 0xb4f0ffa4, 0x0c1eb2ff, + 0x7e240d05, 0xf0008850, 0xa4b3ffa4, 0x49fe1a1f, 0x1c999001, 0x1f0a99bf, 0x49fe29a0, 0x18999001, + 0x39a099bf, 0x900149fe, 0x9fbf2099, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xfb0430f4, + 0x30f41035, 0x05dcdff0, 0x32f90000, 0x30f4ffbf, 0x0149fefc, 0xa0209990, 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0x059ffd16, 0x9eb2dfb2, 0xfdb2ecb2, 0xb0b4030f, + 0x03f4f013, 0xb9fffc09, 0xe5f9ff94, 0x0d00d4b3, 0x0fffff89, 0x0df4c9a6, 0x08e9c50a, 0x0083a03e, + 0xb694c9ff, 0x0fdf0494, 0xffff0000, 0xf9fdf4ef, 0xfff70905, 0xa03e94f9, 0x90b40083, 0x0895f013, + 0x0a10e0b4, 0xb4e2a01f, 0xf3a00ff0, 0xa011b0b4, 0x0149feb9, 0xbf689990, 0x05dcd99f, 0x99bf0000, + 0x0bf4f9a6, 0x83e63e28, 0x49e03400, 0x73b262b2, 0xe926ff09, 0xfb8b1bf5, 0x71b260b2, 0x007f7d3e, + 0xb13e090a, 0x317e0083, 0x85fb003a, 0xc0008f48, 0x00f9cf01, 0xb34c99c7, 0xb3220090, 0xf8f60190, + 0x83f13e02, 0x00f9cf00, 0xb34c99c7, 0xb3330090, 0xf8f60190, 0x84053e02, 0xc1008900, 0x009af601, + 0x010099b8, 0x009bf600, 0x0000f2df, 0x0099b880, 0x9ff60202, 0x009fcf00, 0x053e9fb2, 0x00f80084, + 0xaf95a9b2, 0xb0060a02, 0x0cf408f6, 0xf0bfa00c, 0x1f0a0394, 0x00f8c9a0, 0xbc01bb92, 0xbcffb0bc, + 0xffb4f0bc, 0xacf0aba6, 0xf900f808, 0xb2c0b202, 0x02a0b3dc, 0x02a6b039, 0xb30b0cf4, 0x3e1001a4, + 0xb3008491, 0xb32d07a0, 0x0a3b08a0, 0x84fa3e06, 0xb31f0a00, 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0x0aaf3200, 0x02f63004, 0xf0100cf4, 0x5cd9fff4, 0x0a00002a, 0xf99bbc1f, + 0x12f900f8, 0xb210af95, 0x08ae95b1, 0x00299cd0, 0x26ff0900, 0x3d1bf4e9, 0x26490918, 0xb21bf5f9, + 0x4a091800, 0x99331c0a, 0x3000ab01, 0x08f50196, 0x060a00a1, 0x9d029d33, 0x13099800, 0x1f0af43d, + 0x0918b9a0, 0x4a0f3549, 0x35019910, 0xf13e4909, 0x09180095, 0x330a0a4a, 0xd97a0094, 0x00002a5c, + 0xf4f099bf, 0xe899c7ff, 0xbc0694b6, 0xf6b0f0f9, 0x5e0cf43f, 0xe433030a, 0xf9905b0c, 0x4096b104, + 0x4e0cf400, 0xdf02f994, 0x00002a68, 0x7f909fbc, 0x019a589f, 0xf473080d, 0x09981b02, 0xf0290d04, + 0x90338094, 0x4b7e0f00, 0x01090075, 0x0935d43d, 0x299cdf50, 0xfe180000, 0xffd9c449, 0x0913f9b5, + 0x4af93502, 0x0affe4f0, 0x3e1ea01c, 0x0a0095f1, 0xf911fb04, 0xb2adb222, 0xe8a0c7b2, 0x06b0bbbf, + 0xcc0cf53f, 0xffbcc400, 0xb3ffaec4, 0x0a0d0fe4, 0x3fc6b005, 0x00bb0cf5, 0x002a5cd9, 0xc499bf00, + 0x99c7ff9f, 0x06f194e8, 0xb30694b6, 0xb32c0ee0, 0x0a440fe0, 0x0dedb31f, 0x097c009a, 0xff967190, + 0x8c0cf500, 0xff9fe400, 0x2a68d9ff, 0x9fbc0000, 0x3e2fa0f8, 0x7c00966d, 0x96719001, 0x0cf400ff, + 0xff9fe46f, 0x2a68d9ff, 0x9bbc0000, 0x3e1f0af9, 0xbc0096cf, 0x050af0c9, 0x94f0d9c7, 0x999002fb, + 0x029c9401, 0xb1e0cbbc, 0xf41000e6, 0x01bc440c, 0xb6030a90, 0xc9bc0294, 0x00f6b1f0, 0x320cf410, + 0x08f49ba6, 0xf49ea608, 0xb9a62008, 0xa6080df4, 0x1608f4bf, 0x002a68df, 0xa09fbc00, 0x7eb0bfbc, + 0x3e000b7e, 0x0a00966d, 0x96cf3e04, 0xfb030a00, 0xb1c9b221, 0xf40fffa6, 0x9abc2b0c, 0x0096b190, + 0x210cf410, 0x002a68de, 0x90aebc00, 0x0a00d033, 0xfa3e9ab2, 0xbab20096, 0x7e7e9bb2, 0x1f0a000b, + 0x040a00f8, 0x30f400f8, 0x05dcdfe4, 0x12f90000, 0x49feffbf, 0x20999001, 0x9fa0a0b2, 0xb4f0d1b2, + 0xb4edb2ff, 0xe0b40aa0, 0x0709c40b, 0x1bf49ba6, 0x2f0fc775, 0x900149fe, 0x9da00899, 0xb5029eb5, + 0x9fbc019a, 0xfe94bdb8, 0xff90014f, 0xb5f9a014, 0xf1b501fc, 0x2309c702, 0xf9bcbabf, 0x850fc7c8, + 0x3c8a09c7, 0xf4f0e09f, 0x910dc71f, 0x3c05cfbb, 0xeeb990d9, 0x1fd4f000, 0xb91fe4f0, 0xefbc0099, + 0x1f94f0e0, 0x9dbcff0f, 0x95f9bc90, 0xbb05febb, 0xfcfd049d, 0x0099b904, 0xfd04fdbb, 0x9ffd049a, + 0xfeb9a005, 0x99900149, 0xd99fbf20, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x30f41c15, + 0x05dcd9f4, 0x82f90000, 0xd1b299bf, 0x90014ffe, 0xf9a02cff, 0xff92dd3f, 0x091f0003, 0x01f03517, + 0x2002f035, 0xb2b6b2f9, 0x33a5b2e3, 0xdb1900d4, 0x00000528, 0x7e7e240c, 0x0909000b, 0x19200a32, + 0x0098813e, 0xd630030a, 0x780cf409, 0xc40147fe, 0xf8b2ffc4, 0x7790043d, 0x98783e24, 0xff09c400, + 0x92947bb2, 0xbc040c02, 0xd43da026, 0x0096d17e, 0x6b1fa433, 0xf9c47fbf, 0xf494a607, 0xf9c75e18, + 0x01991223, 0xf4019630, 0xfec7520c, 0xffe9c42f, 0xc7c8893c, 0xf9c78afd, 0x90d93c85, 0x0cf49c26, + 0x03e0333b, 0x91f9c738, 0x26909d3c, 0x2c0cf49c, 0x109052bc, 0x9fa00100, 0x0926193f, 0x0aa108f4, + 0x0149fe1f, 0xbf2c9990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x98b13e23, 0xbf0d0a00, 0xff0fc439, + 0x000000de, 0x049efdff, 0xa005f9fd, 0x98813e3f, 0x3a317e00, 0x0c85fb00, 0xd9a830f4, 0x000005dc, + 0x99bf82f9, 0xb2f830f4, 0x014ffea7, 0xa080ff90, 0xb0aabff9, 0xc1b00eb1, 0x68a6c70d, 0x30016912, + 0x0cf50396, 0xa9c7013b, 0x0a96306c, 0x01310cf5, 0xfe0141fe, 0x11900140, 0x50009057, 0x2010a5b6, + 0xb2b4bd19, 0x94e27e0c, 0x1fad3300, 0x09bf011d, 0xc40142fe, 0x2290ff6b, 0x04b4b658, 0xb9bc2ab2, + 0xb26c32b0, 0x7e7eb21d, 0x300097be, 0xad333fa1, 0xfe00f51f, 0x01080141, 0x3d401190, 0x08199024, + 0x3d0c1e90, 0xb054bd34, 0xe1b00c91, 0x9a0d3e0b, 0x1490b400, 0x100c1bb2, 0x59bcd43d, 0x7e4ab240, + 0x330096d1, 0x00c31fad, 0x1f9819bf, 0xffffde01, 0x9efde0ff, 0x021fb504, 0x203319a0, 0x043d0a00, + 0x0099a73e, 0xb40cb0b4, 0x1ab20bc0, 0x008d3e7e, 0xa0321fbf, 0xffffffde, 0x1f09c4e0, 0xb604fefd, + 0x9ffd1894, 0xb219a005, 0x0c1bb24a, 0x7e010d10, 0x330096d1, 0x33731fa4, 0x020a0020, 0x9a073e01, + 0x1f043300, 0x3e043d3f, 0xc40099f4, 0x1c98ff09, 0x031d9802, 0xfe0de0b4, 0xff90014f, 0xa8f9bc58, + 0xb00e90b4, 0x001001e1, 0xb03b3201, 0x7eb20091, 0x0097067e, 0x26579034, 0xd208f409, 0x009a073e, + 0x843d19bf, 0x101f9295, 0x55900133, 0xf5362610, 0x0aff4208, 0x0080331b, 0x9a233e11, 0x3e030a00, + 0x34009a26, 0x49fe3fa0, 0x80999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x30f4003a, + 0x5885fb08, 0xdff430f4, 0x000005dc, 0xffbf12f9, 0x900149fe, 0x41fe1099, 0x909fa001, 0xb84a0c11, + 0xb2040b00, 0x8c307e1c, 0x1fa43300, 0x0140fe2b, 0x9000b44a, 0x040b0800, 0x307e0cb2, 0xa433008c, + 0x19bf161f, 0x9fa60fbf, 0xf00b9cf0, 0x9a320196, 0x009a963e, 0x49fea43d, 0x10999001, 0xdcd99fbf, + 0xbf000005, 0xf4f9a699, 0x317e070b, 0x15fb003a, 0x04a9980c, 0xac90afb2, 0xf0010b59, 0x904a2095, + 0x04f9b500, 0x008c307e, 0x30f400f8, 0x05dcd990, 0x52f90000, 0x4ffe99bf, 0x84ff9001, 0xf9a0030e, + 0x0500ad33, 0x299cd901, 0x99180000, 0x00993359, 0xba3200f6, 0xbd014cfe, 0x20cc90b4, 0x0094e27e, + 0xad33ae32, 0xfe00e31f, 0xb84a0144, 0x1c449000, 0x4cb2040b, 0x008c307e, 0xad33ae32, 0xfe00cb1f, + 0xb44a0140, 0x18009000, 0x0cb2040b, 0x008c307e, 0xad33ae32, 0xbf00b31f, 0xa64abf09, 0xa60bf5a9, + 0xbcaa9000, 0x0b0140fe, 0x27009001, 0x307e0cb2, 0xae32008c, 0x911fad33, 0xfe093f00, 0x43b20142, + 0xf0282290, 0x0045ff94, 0x02915410, 0x009ba93e, 0x1be43abf, 0x5abcffff, 0xf4b9a692, 0x9bb2050d, + 0xaa90b072, 0x00b3f0bc, 0x307e2cb2, 0x0fe4008c, 0xae32ffff, 0x511fa433, 0x107b39bf, 0x202fbc02, + 0xf190f9bc, 0xa00fff94, 0x00147339, 0x0149fec7, 0xbf209990, 0x0799909a, 0x4bfe9c3f, 0x90010d01, + 0xc4f028bb, 0x02c4b6ff, 0x0096d17e, 0xa433ae32, 0x4cb2171f, 0x0b00b84a, 0x8af07e04, 0x3eae3200, + 0x0e009be5, 0x0149fe09, 0xbf849990, 0x05dcd99f, 0x99bf0000, 0xf9a6ea32, 0x7e070bf4, 0xfb003a31, + 0xa9987055, 0xf0008f04, 0x059ffd3f, 0xf804a9b5, 0x12aeb200, 0x040a10bf, 0xf926ee09, 0x332e0df4, + 0x7f0a00c4, 0x9c2c3eea, 0x01ea5800, 0x1800a073, 0xb926ff09, 0xe4140bf4, 0xbbffffa9, 0x94f0059b, + 0x071bf401, 0x00f8090a, 0x00f81f0a, 0xdff830f4, 0x000005dc, 0xffbf32f9, 0xfe0149fe, 0x99900140, + 0x0143fe14, 0xa2b29fa0, 0x0090b1b2, 0x12339013, 0x0b10ec4a, 0x7e0cb201, 0x33008b70, 0x3f741fa4, + 0x01a6300a, 0xb3690cf4, 0xf0210020, 0xa994ffa4, 0xb6240b05, 0x2cb202a4, 0xb8a0a9bc, 0x0010eeaa, + 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0xbd011458, 0xa029a094, 0x04109039, 0x4c72157f, 0x004da47d, 0x01e4bd80, 0x9e313e01, + 0x01c9c400, 0x7f200bf4, 0xf4fd660f, 0x1ebc0a1d, 0x9e263ea4, 0xf4fd6600, 0x1ebc0d1b, 0x05a9fd94, + 0x009e263e, 0xee90df72, 0x01c57601, 0x72020090, 0x00c473fd, 0xf06ebfd0, 0xa9c400d3, 0xffffdfff, + 0x94b6ff00, 0x04effd10, 0xff00008c, 0xfd059efd, 0x9dfd049c, 0xbf69a005, 0xff4ee429, 0xe8afc7ff, + 0xf110ed94, 0xfdff0094, 0xf9fd059d, 0xe42fa005, 0xb9ffff59, 0xe9ff00ee, 0x150bf4a4, 0x9cfd39bf, + 0x059afd04, 0x29bf39a0, 0x010095f1, 0x49fe29a0, 0x40999001, 0xdcd99fbf, 0xbf000005, 0xa6ba3299, + 0x070bf4f9, 0x003a317e, 0xf42865fb, 0xdcdff030, 0xf9000005, 0xfeffbf62, 0x99900149, 0xa0a13228, + 0x32b0329f, 0xb2d5b2c4, 0x04b630e6, 0x01120cf5, 0x00299cd9, 0x049e9800, 0x90ffb9c4, 0x9fc41199, + 0xbb080a1f, 0x99b905ef, 0x1f94f000, 0x0f909fbc, 0x05f9bbff, 0xb334feff, 0x00e9013d, 0x4ffe94bd, + 0x20ff9001, 0xb50142fe, 0x229001f9, 0xbdf9a01c, 0x7e2bb2a4, 0x33009c4c, 0x00c91fad, 0x3c322ab2, + 0x117e1b32, 0xad33009c, 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0xb3a0b200, 0xb46d00a4, + 0xf0011290, 0x1bf491a6, 0x014e9832, 0xb370efcd, 0x0f0600f4, 0x06291870, 0xbcff94f0, 0x9fbb909e, + 0x0149b502, 0x00ae983e, 0x3ab20bb2, 0x3e7e2cb2, 0xa0b200a4, 0x3400a4b3, 0xfe0265bb, 0xaa90014a, + 0xa6a97e34, 0x0060b300, 0x0b90b420, 0xbc8085bc, 0x91b09095, 0xace43e0b, 0x3e020000, 0x0000aec8, + 0xaec83e03, 0x0c00b400, 0x2bb23ab2, 0x00a60b7e, 0x79b594bd, 0xaee13e05, 0x3e030000, 0x0000aee1, + 0x0149fe02, 0xbf5c9990, 0x05dcd99f, 0x99bf0000, 0xf9a60ab2, 0x3e170bf4, 0x1800af07, 0x9d330629, + 0x3efe4f00, 0x7e00aebf, 0xf4003a31, 0x85fb0830, 0xdc30f434, 0x0005dcdf, 0xbf82f900, 0xf830f4ff, + 0x900149fe, 0x9fa04c99, 0xb20bb1b0, 0xb2d4b2c2, 0xb3a5b2e6, 0x011700b9, 0x1200e9b3, 0xfe94bd01, + 0xc43d0141, 0xa0481190, 0x7e1db219, 0xb200a63f, 0x00adb3a0, 0x19bf00fb, 0x98f042bc, 0x9fa60199, + 0x00ea08f5, 0x03005ab2, 0x00a5e97e, 0xa9b3a3b2, 0xbf00de00, 0x0c5c981b, 0x900140fe, 0x0ab23000, + 0x00a6277e, 0x2bcc0ab2, 0xa6c07e70, 0xb3a8b200, 0x00ad00ad, 0xfe7021cd, 0x80420147, 0x44779000, + 0x00b0373e, 0xbd0c00b4, 0x0979a094, 0xf409a6f0, 0x0200091b, 0x00b03e3e, 0x09a6f009, 0x00090df4, + 0xb03e3e03, 0x0bc0b400, 0xbd0704b6, 0xb20db2e4, 0xb0b4bd5a, 0x71b00021, 0xa5e37e01, 0xb25abf00, + 0xb22cb20b, 0xb7757e3d, 0xb27ebf00, 0xb23bb2a0, 0xb22cb25a, 0xa5e57e0d, 0x0004b300, 0xbd3ab245, + 0xa4107eb4, 0xb3a0b200, 0x003700a4, 0x0201bb70, 0x0df404a6, 0x9040b205, 0x6ab2101b, 0xb2b03bbc, + 0xb7957e0c, 0x014afe00, 0x900240bb, 0x60bc30aa, 0xa6a97e60, 0xb314bd00, 0xff6d004d, 0x5ab280b2, + 0x0b7e3bb2, 0x4c3e00a6, 0x020000b0, 0x900149fe, 0x9fbf4c99, 0x0005dcd9, 0xb299bf00, 0xf4f9a60a, + 0x317e070b, 0x30f4003a, 0x2485fb08, 0xd9f830f4, 0x000005dc, 0x99bf32f9, 0x90014ffe, 0xa1b214ff, + 0x94bdf9a0, 0xc3b2b2b2, 0x4b0140fe, 0x00900320, 0xb209a010, 0xb79b7e0a, 0xb309bf00, 0xb34c0090, + 0xa04800a4, 0xb509bf91, 0x0fbf0192, 0xb5100049, 0x0fbf04f9, 0xf9b52009, 0xb509bf05, 0x0fbf0693, + 0xf9350109, 0x3509bf1c, 0x0fbf2c9a, 0xf9b5f009, 0x900fbf0a, 0xf9b540f9, 0x900fbf0e, 0xf9b5c0f9, + 0x3e0abf0f, 0xbd00b0e9, 0x0149fea4, 0xbf149990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, + 0x0835fb00, 0xdfd030f4, 0x000005dc, 0xffbf82f9, 0x900149fe, 0xa3b25099, 0x02059fa0, 0xf800a9b3, + 0x00b63004, 0x350b9cf0, 0x94bd2ca9, 0x7e0ca9b5, 0xb200a5e9, 0xbd3abfa0, 0x00804cb4, 0x757e0db2, + 0xa5b200b7, 0xae00adb3, 0x33093f04, 0x049f4a9d, 0x33010918, 0x0497469d, 0x33020918, 0x048f469d, + 0x33030918, 0x0487539d, 0x18040e18, 0x0f180509, 0x070d1806, 0xf0ffe4f0, 0xf4f0ff94, 0x0894b6ff, + 0xfd10f4b6, 0xd4b6059e, 0x05f9fd18, 0xf505dffd, 0x05045b0b, 0x03d6b005, 0x045a0cf5, 0xb3013db5, + 0x490e01d4, 0x39b55000, 0xb1d73e02, 0x080d1800, 0x18090918, 0x0e180a0f, 0xffd4f00b, 0xf0ff94f0, + 0x94b6fff4, 0x10f4b608, 0xb6059dfd, 0xf9fd18e4, 0x05effd05, 0xb2023eb5, 0x7e0bb23a, 0x9800a60b, + 0xff09023a, 0xa9a60305, 0x04080bf5, 0x9007a5b6, 0x3ab5303b, 0xb6ce7e03, 0xb3a5b200, 0x03f500ad, + 0x09033b98, 0x343a90c0, 0xfd3fbb90, 0xb5b604b9, 0xb79b7e03, 0xb3a5b200, 0x03d900ad, 0xfe0147fe, + 0x77900148, 0x9044bd40, 0x88900179, 0x0991b03c, 0x00b3443e, 0x8ea0e4bd, 0x0f0044b3, 0xbd0c3a98, + 0x3efe0cb4, 0xb200b267, 0xb24bb23a, 0xa5787e7c, 0xb3a5b200, 0x039d00ad, 0x94f0793f, 0x120bf401, + 0xb20c3a98, 0x7eff0c4b, 0x3e00b672, 0xb200b341, 0xa32f7e7a, 0x00a0b300, 0x0c3a980f, 0xfd0c4bb2, + 0x00b2673e, 0x94f0793f, 0x0e1bf402, 0xb20c3a98, 0x3efd0c4b, 0xb400b336, 0x3ab209b0, 0x8db2010c, + 0x00a63f7e, 0x5d00a0b3, 0x3fb2793f, 0x99c724bd, 0x01999002, 0x980a91b0, 0x54b354f5, 0xb0b43900, + 0x0022bc09, 0x02bc030c, 0x0304b600, 0x014001b8, 0x1031bc00, 0x957e1ab2, 0x30bc00b7, 0x4309b800, + 0x95200001, 0xb45302b5, 0x0fb50af0, 0x3e81a054, 0x9000b301, 0xff900122, 0x1424b318, 0xb62e3ebe, + 0x3f8ebf00, 0x027f5879, 0x98077d18, 0x3a9803ee, 0x0299c70d, 0xcc00f3f0, 0x96cb70ff, 0xcb4bb21f, + 0x010cd8e6, 0xebf0d6cb, 0x7e01e0f6, 0x9800a2e5, 0x4bb20c3a, 0x727e6cb2, 0xa5b200b6, 0xb400adb3, + 0x01449002, 0xa6033b98, 0xeb08f54b, 0xbc94bdfe, 0x89a0b0bb, 0xb17e8ab2, 0xa5b200b7, 0x9400adb3, + 0xbd37b202, 0x547f9884, 0xbc9088bc, 0x94b69098, 0x4099b803, 0x39bc0001, 0x0b91b090, 0x5300f9b3, + 0x033c9802, 0x3d0fa0b4, 0xbc24bdb4, 0x44bdc0cc, 0x00b78c7e, 0x3e0f60b4, 0x9800b45f, 0x2bb20d3a, + 0x7e0c41b0, 0x3300a2f5, 0x00b500a9, 0xfe0c3a98, 0x2bb2014c, 0x7e38cc90, 0xb300b65b, 0x020c00ad, + 0xb40be0b4, 0xef980e90, 0xd899c703, 0x1bf59fa6, 0x3a98008e, 0x0c2bb20d, 0xa2ed7e01, 0x014cfe00, + 0x2bb23ab2, 0x7e30cc90, 0xb300a593, 0x981306a4, 0x2bb20c3a, 0x727efd0c, 0x5c3e00b6, 0xadb300b4, + 0x7401cb00, 0x93f01c90, 0x9099bc00, 0x7f0069bc, 0xff19e401, 0x091bf4ff, 0x5c3e0260, 0x3a9800b4, + 0x014cfe0c, 0xffff1be4, 0x7e34cc90, 0xb300b65b, 0x019800ad, 0x343af034, 0xf9263690, 0x60100df4, + 0xff1be402, 0x0c3a98ff, 0x00b4513e, 0xb20c3a98, 0x7efd0c2b, 0xb300b672, 0x017000ad, 0x98012290, + 0x2aa6033a, 0xff3708f5, 0x6eb264b2, 0xd43db43d, 0xc4bdf4bd, 0x00b4933e, 0x9473e97f, 0x010d0a00, + 0x00b48d3e, 0x0600d033, 0xcc90010b, 0x01ff9001, 0xa602ee90, 0xe308f4fa, 0x0b00c4b3, 0x3e547cb5, + 0x3300b5cf, 0x00a600b9, 0xb0013998, 0x0cf40296, 0xb2030930, 0x5479b56d, 0xf4bde4bd, 0x00b4d23e, + 0x9073d97f, 0x697c0a00, 0x01ee90e9, 0x9001ff90, 0x399802dd, 0xf4f9a603, 0x493ee908, 0x94bd00b5, + 0x79b5f101, 0xb224bd54, 0xb5233e1b, 0xe4407f00, 0xf4ffff09, 0xf10f260b, 0x1bf4bfa6, 0xff0be40b, + 0xb51b3eff, 0x0c3a9800, 0xffff0ce4, 0x00b6727e, 0xb900adb3, 0xff0be400, 0x9019b2ff, 0x44900122, + 0x9891b202, 0x29a60339, 0x09c508f4, 0xf5b9a6f1, 0x9800a00b, 0x3c980c3a, 0xb6727e0a, 0x00adb300, + 0x31b5008c, 0xb5cf3e0a, 0xbd6f7f00, 0x01c19294, 0xf05179b5, 0x04bd00f3, 0x3e527fb5, 0x7f00b587, + 0x014c584b, 0x900c3a98, 0xb3f00100, 0x00c3f000, 0x7e024490, 0xb300b672, 0xb45200a4, 0xe9980be0, + 0x70999001, 0xa601e9b5, 0xd608f401, 0x9808607c, 0xf00c0c3a, 0xffff0be4, 0x00b6727e, 0x2d00a4b3, + 0xe4014cfe, 0xb2ffff0b, 0x40cc903a, 0x00a5787e, 0x1900a4b3, 0x98469034, 0x94f0517f, 0xf0f9bcff, + 0x3e517fb5, 0x0a00b5cf, 0x3ea5b203, 0x9000b5da, 0x77900188, 0x148db318, 0x49fefd90, 0x3c999001, + 0x457e9abf, 0xf03e00b7, 0x030500b5, 0x00b5f23e, 0x0bb204bd, 0x0b7e3ab2, 0x50b300a6, 0x3a981a00, + 0x7e04bd0c, 0x9800b6c4, 0x30b50d3a, 0xb7457e0c, 0x0d30b500, 0x900149fe, 0x9fbf5099, 0x0005dcd9, + 0xb299bf00, 0xf4f9a65a, 0x343e110b, 0x010500b6, 0x00b5f03e, 0x003a317e, 0xf93085fb, 0x7ea0b202, + 0x9800a5e7, 0xc47e0c0a, 0x0a9800b6, 0xb7457e0d, 0x7e0ab200, 0xbd00b745, 0xbf01fba4, 0x0aafb2a9, + 0xf4b9a602, 0xb9900d18, 0x98f9bc01, 0xc9a0a4bd, 0xa9bf00f8, 0x020aafb2, 0x18f4b9a6, 0x01b9900b, + 0xfcbca4bd, 0xbf00f899, 0xb2afb2b9, 0xf4c9a6ca, 0xf10a0708, 0xfbb500f8, 0xb5fca002, 0x00f801fc, + 0xaf98a9bf, 0x90b9bc02, 0xfbbfa9a0, 0x08f49ba6, 0x029bbb08, 0xa998a9a0, 0xa6aabf01, 0x051bf4a9, + 0x00f8f10a, 0x0800a0b3, 0x00b7457e, 0x30f400f8, 0x05dcdff8, 0x32f90000, 0x49feffbf, 0x14999001, + 0x9fa0a0b2, 0xa0b3b3b2, 0xfd024200, 0x0cf4a2a6, 0x01ab903a, 0xb60141fe, 0x119002b4, 0x7e1ab210, + 0xb300b7b1, 0xbf2700a4, 0xb21db219, 0xa0e4bd2c, 0x90dfbf90, 0x9eb201e9, 0xa699fcbc, 0xf408f490, + 0x3da0ddbf, 0x00b72a3e, 0x49fe020a, 0x14999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, + 0x35fb003a, 0xda00f808, 0x00002944, 0x0041c77e, 0xf000a630, 0xa6f00bac, 0x01aab901, 0x44da00f8, + 0x7e000029, 0x30004142, 0xacf000a6, 0x01a6f00b, 0xf801aab9, 0x2944da00, 0xd77e0000, 0xa6300042, + 0x0bacf000, 0xb901a6f0, 0x00f801aa, 0x7effb4f0, 0xf8000b94, 0x0b7e7e00, 0xf900f800, 0x3da0b202, + 0x384c7ea4, 0x00a6b000, 0xa00b9cf0, 0xfb9ab20a, 0xb202f901, 0x7ea43da0, 0xb000382a, 0x9cf000a6, + 0xb20aa00b, 0xf401fb9a, 0xdcdfe430, 0xf9000005, 0xfeffbf82, 0x45fe0149, 0x3c999001, 0xa00147fe, + 0x2455909f, 0xd9347790, 0x0000141c, 0x4bfe9abf, 0x90080c01, 0xff0d2cbb, 0x0000c17e, 0xeb00a433, + 0x3f0c30b4, 0x0c943339, 0x043118e2, 0x0f001033, 0xb0011933, 0x3e043d00, 0x9800b96d, 0x2cd9023f, + 0x98000014, 0x34580431, 0x3f5fa00a, 0x0339989f, 0xb5183690, 0xff090159, 0xf43379a0, 0xf77e1800, + 0xa0320032, 0x2900ad33, 0xdf010901, 0x0000142c, 0x1272f920, 0xbd0043f0, 0xb8ad3e14, 0x0241bc00, + 0x010006b1, 0x40060df4, 0x947e0100, 0x24d9000b, 0xbf000014, 0xff2ce49a, 0xb26bb2ff, 0x1300de0d, + 0x117e0000, 0x7aa000af, 0xd400adb3, 0x985bbf00, 0x1d90015c, 0x7c0eb204, 0x10bc2020, 0x1300da10, + 0x367e0000, 0xa0320021, 0xc500ad33, 0x4cb4bd00, 0x00da0100, 0xa6000013, 0xa408f414, 0x00b95c3e, + 0xd9023f98, 0x0000142c, 0x58043498, 0x5fa00a32, 0x39989f3f, 0x18389003, 0x090159b5, 0x3379a0ff, + 0x7e1600f4, 0x320032f7, 0x00ad33a0, 0x2cdf0084, 0x20000014, 0xff26e4f1, 0x3e24bdff, 0xbc00b94d, + 0x16b11262, 0x0df40100, 0x01004106, 0x000b947e, 0x5c985bbf, 0x042d9001, 0x00da1eb2, 0x7e000013, + 0xe40020d0, 0xbcffff4c, 0xa0322021, 0x1db28bb2, 0x001300de, 0x40417c00, 0x3500a433, 0x001424d9, + 0x7e9abf00, 0xa000ac3b, 0x00a4b37a, 0x4cb4bd13, 0x00da0100, 0xa6000013, 0xa608f426, 0x5c985bbf, + 0xbd7ab201, 0x7e040ed4, 0x32002136, 0x2db034a0, 0x817e3ab2, 0x0d33000f, 0x30fe7100, 0x020f3a01, + 0x1838f130, 0x04090333, 0x30014afe, 0x31303991, 0x90b4bd3b, 0x717e38aa, 0xe73e000f, 0x02f900b7, + 0x002930d9, 0xbfa0b200, 0x7e640b9a, 0x090000de, 0x00a43310, 0xa6008961, 0x009fcf02, 0x1000f5f1, + 0x8a009ff6, 0x4b02a600, 0xc4bd1000, 0xbd27104d, 0x198b7ee4, 0x00a43300, 0x2930d915, 0x9abf0000, + 0x00009b7e, 0x123e0409, 0x0ab200ba, 0x7e03e84b, 0x890016fc, 0xb802a400, 0x000200aa, 0x920aa5b6, + 0x9af601aa, 0x01114f00, 0x020099b8, 0x009ff600, 0x9a32943d, 0x000001fb, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -1809,9 +1529,9 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00005600, 0x00005625, 0x0000564a, 0x0000566f, 0x00005694, 0x000056b9, 0x000056de, 0x00005703, - 0x00005728, 0x0000574d, 0x00005772, 0x00005797, 0x000057bc, 0x000057e1, 0x00005806, 0x0000582b, - 0x00005850, 0x00005875, 0x0000c350, 0x00003e80, 0x00004e20, 0x000061a8, 0x000064b5, 0x00007d00, + 0x00004a00, 0x00004a06, 0x00004a0c, 0x00004a12, 0x00004a18, 0x00004a1e, 0x00004a24, 0x00004a2a, + 0x00004a30, 0x00004a36, 0x00004a3c, 0x00004a42, 0x00004a48, 0x00004a4e, 0x00004a54, 0x00004a5a, + 0x00004a60, 0x00004a66, 0x0000c350, 0x00003e80, 0x00004e20, 0x000061a8, 0x000064b5, 0x00007d00, 0x00009c40, 0x0000cf85, 0x4953424e, 0x004c4520, 0x00412f4e, 0x00640077, 0x64310062, 0x62347734, 0x62327732, 0x32007733, 0x00773262, 0x00773531, 0x77316236, 0x00623700, 0x64317731, 0x62347731, 0x32313000, 0x36353433, 0x41393837, 0x45444342, 0x00000046, 0x00000000, 0x00000000, 0x00000000, @@ -1823,9 +1543,9 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x000021db, 0x00002222, 0x00002253, 0x00002292, 0x00001f4e, - 0x00001f95, 0x00001fc6, 0x00002017, 0x00002088, 0x000020cf, 0x00002119, 0x0000216a, 0x00001e2a, - 0x00001e71, 0x00001ea2, 0x00001eeb, 0x0000000c, 0x00000000, 0x00000000, 0x00000013, 0x00000001, + 0x00000000, 0x00000000, 0x00000000, 0x00001d1d, 0x00001d3b, 0x00001d4d, 0x00001d65, 0x00001bb0, + 0x00001bce, 0x00001be0, 0x00001c08, 0x00001c5e, 0x00001c7c, 0x00001c9f, 0x00001cc7, 0x00001b26, + 0x00001b44, 0x00001b56, 0x00001b76, 0x0000000c, 0x00000000, 0x00000000, 0x00000013, 0x00000001, 0x00000000, 0x00000013, 0x00000001, 0x00000001, 0x00000013, 0x00000001, 0x00000002, 0x00000013, 0x00000001, 0x00000003, 0x00000013, 0x00000001, 0x00000004, 0x00000013, 0x00000001, 0x00000005, 0x00000013, 0x00000001, 0x00000006, 0x00000013, 0x00000001, 0x00000007, 0x00000013, 0x00000001, @@ -1851,7 +1571,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x09000000, 0x09400000, 0x09800000, 0x09c00000, 0x0a01c000, 0x0a404038, 0x0a804040, 0x0ac04048, 0x0b004050, 0x0b420058, 0x0b8201ab, 0x11800000, 0x11c00000, 0x12000000, 0x12400000, 0x12800000, 0x12c00000, 0x00000001, 0x00001c08, 0x00101c09, 0x00201c0a, 0x0000bd08, 0x00209d09, 0x00309d0a, - 0x00011f08, 0x00113e09, 0x00311e0a, 0x00010309, 0x00000000, 0x0000ffff, 0x00004300, 0x46020f1f, + 0x00011f08, 0x00113e09, 0x00311e0a, 0x00010309, 0x00000000, 0x0000ffff, 0x00003b00, 0x46020f1f, 0x43010f1f, 0x44020f1f, 0x45020f1f, 0x601207ef, 0x601307ef, 0x601407ef, 0x601507ef, 0x801607ef, 0x253207c2, 0x25330fc2, 0x25340fc2, 0x25350fc2, 0x1152079d, 0x1253079d, 0x7014079d, 0x7015079d, 0x601203c8, 0x601307c8, 0x601407c8, 0xbb150720, 0x02172701, 0x00000000, 0x00000000, 0x00000000, @@ -2193,9 +1913,17 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00560000, 0x00420074, 0x007f0078, 0x008c0089, 0x004200c0, 0x00dc0042, 0x00051f00, 0x35040b08, - 0x0200001d, 0x00000000, 0x00000000, 0x00000000, 0x00000c00, 0x00000000, 0x00000000, 0x00000000, - 0x00003450, 0xcab00000, 0x00010000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x004a0000, 0x003a0060, 0x00690062, 0x00720070, 0x003a00a2, 0x00b9003a, 0x00031700, 0x31030808, + 0x02000018, 0x00000000, 0x00000000, 0x00000000, 0x00000c00, 0x00000000, 0x00000000, 0x00000000, + 0x00003550, 0xc9b00000, 0x00010000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -2476,7 +2204,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000001, 0x00000002, 0x00000000, 0x00000000, 0x00003100, 0x00000000, 0x0000de00, 0x00000000, + 0x00000001, 0x00000002, 0x00000000, 0x00000000, 0x00003200, 0x00000000, 0x0000bb00, 0x00000000, 0xe4f7f5ef, 0xee6f0434, 0xa742283d, 0xb837517d, 0x49e4d804, 0xd8d4d342, 0xa7c8bf31, 0xe15c25cf, 0x3acb76c7, 0x6ca73cfc, 0xc5002b4d, 0x9dc59b12, 0x8f11945c, 0xe814622b, 0xc745df38, 0xc179824e, 0x50ed0464, 0x40f4b2de, 0x4ea86960, 0xacb935cf, 0xf1b2d5f8, 0xa4ba5e6f, 0x90a0a1eb, 0x69da0dfa, @@ -2541,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x7a9040dd, 0x0251d13c, 0x4450ac04, 0xc13389f9, 0x1f789ab9, 0x340dcaa2, 0xa6b485f7, 0xee512b70, - 0x59823fc0, 0xf12a3ca4, 0x45b67ae9, 0xd31002ea, 0x6d8e8937, 0x3b58b368, 0x0fce515f, 0x46a7c8f4, + 0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0xa1f0af45, 0xc2521354, 0x427cca67, 0x3b102336, + 0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0xcdd28e1e, 0x6000ae0f, 0x492dfb26, 0x422cf074, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -2610,30 +2338,30 @@ const NvU32 soe_ucode_header_lr10_dbg[] = { /* .codeEntryPoint = */ 56832, /* .appVersion = */ 1, /* .appCodeStartOffset = */ 0, - /* .appCodeSize = */ 56832, + /* .appCodeSize = */ 47872, /* .appCodeImemOffset = */ 0, /* .appCodeIsSecure = */ 0, - /* .appDataStartOffset = */ 56832, - /* .appDataSize = */ 12544, + /* .appDataStartOffset = */ 47872, + /* .appDataSize = */ 12800, /* .appDataDmemOffset = */ 0, /* .appVersion = */ 1, - /* .appCodeStartOffset = */ 69376, + /* .appCodeStartOffset = */ 60672, /* .appCodeSize = */ 1024, /* .appCodeImemOffset = */ 56832, /* .appCodeIsSecure = */ 0, - /* .appDataStartOffset = */ 73728, + /* .appDataStartOffset = */ 65024, /* .appDataSize = */ 7424, /* .appDataDmemOffset = */ 56832, /* .appVersion = */ 1, - /* .appCodeStartOffset = */ 70400, + /* .appCodeStartOffset = */ 61696, /* .appCodeSize = */ 3328, /* .appCodeImemOffset = */ 57856, /* .appCodeIsSecure = */ 1, - /* .appDataStartOffset = */ 81152, + /* .appDataStartOffset = */ 72448, /* .appDataSize = */ 0, /* .appDataDmemOffset = */ 0, }; -const NvU32 soe_ucode_data_size_lr10_dbg = 20288; +const NvU32 soe_ucode_data_size_lr10_dbg = 18112; #endif //_SOE_UCODE_LR10_DBG_H_ diff --git a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h index 0e1a99519..41eac9e01 100644 --- a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h +++ b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h @@ -33,9 +33,9 @@ const NvU32 soe_ucode_data_lr10_prd[] = { - 0x00fec0d0, 0x0004fe00, 0x0017167e, 0x08f802f8, 0xa4b300f8, 0x64890a00, 0x9abf000f, 0x1100a0b3, + 0x00fec0d0, 0x0004fe00, 0x0017167e, 0x08f802f8, 0xa4b300f8, 0x8c890a00, 0x9abf000f, 0x1100a0b3, 0x0d00b0b3, 0xa001aa98, 0xf8a43dba, 0x0a02f800, 0xbd00f8ff, 0xfc30f494, 0x40fe02f9, 0x04009001, - 0x0db209a0, 0x0003237e, 0xa4b3afb2, 0x0dbf1601, 0x0a01d4b3, 0x002d8989, 0xa43d9d20, 0x00006b3e, + 0x0db209a0, 0x0003237e, 0xa4b3afb2, 0x0dbf1601, 0x0a01d4b3, 0x002e8989, 0xa43d9d20, 0x00006b3e, 0xfc09040a, 0x0bf4f9a6, 0xfbff0a05, 0x337e0405, 0xa0330000, 0xa0330a04, 0x02f80600, 0xb37e00f8, 0xafb20003, 0x0801a4b3, 0x00f8a43d, 0xfc09040a, 0x0bf4f9a6, 0x0a02f807, 0xbd00f8ff, 0xbdc4bdb4, 0x007e7ed4, 0xf900f800, 0xb2a2b222, 0xb2c0b2b1, 0xb21bb22a, 0x7eff0d0c, 0x3300007e, 0xfbf400a4, @@ -72,59 +72,59 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x3e00000e, 0xb2000491, 0x01147e1a, 0x092e7e00, 0x0a747e00, 0x0e1f9800, 0x000f1998, 0xf4f9a6fc, 0x1ab22a18, 0x4cb25bb2, 0x0002f47e, 0xb3091998, 0xb2180090, 0x05f57e8a, 0xb3a0b200, 0x7e0c01a4, 0x3e00000e, 0x000004c9, 0x0a9b7e01, 0xa6fc0f00, 0x251bf40f, 0x90b339bf, 0x6ab22000, 0xee023bb2, - 0x0005397e, 0x3400a9b3, 0x04f63eff, 0x3eef0000, 0x400004f6, 0x0ab2fe0c, 0x890c85fb, 0xbf000f70, - 0x8900f89a, 0xbf000f64, 0x8900f89a, 0xbf000f74, 0x0096b099, 0xf00bacf0, 0x00f801a6, 0x000f7889, - 0xa9a099bf, 0x000f7089, 0xa9b599bf, 0x0f00f801, 0x0f7c8901, 0xf89fa000, 0xb222f900, 0x7eb2b2a0, - 0x89000a74, 0xbf000f78, 0xa609bf9f, 0x110bf4f9, 0x000f7089, 0x09989fbf, 0xf4f9a601, 0x708d3318, - 0x0e98000f, 0xbfd9bf01, 0x029ebb2f, 0x18f49fa6, 0xbdd9bf20, 0x92e9bc14, 0xa0909fbc, 0x0f788929, - 0xa099bf00, 0xb5d9bf09, 0x903e0109, 0x01010005, 0x000a9b7e, 0x21fb1ab2, 0x000a747e, 0x000f748f, - 0x9990f9bf, 0x7ef9a001, 0xf8000a9b, 0x8002f900, 0xbf000f84, 0x0196b009, 0x7e070df4, 0x7e00000e, - 0x3e000a8f, 0x8e0005b3, 0x18001038, 0xefbf41a9, 0x9ac4abb2, 0xf4afa6ff, 0xeaa0050d, 0xb604a994, - 0xa9bc02a4, 0x0f8489a0, 0x10bb9000, 0x7ea0a9bc, 0xf8000bee, 0x9812f900, 0x909803a9, 0x24019003, - 0x517e1ab2, 0x7489000c, 0x99bf000f, 0x150094b3, 0x7e100a90, 0xb2000c51, 0x05c77e0a, 0x062b3e00, - 0x8a1bb200, 0x7e00103c, 0x89000bee, 0xbf000f64, 0x410f1899, 0x9918a4bd, 0xf4f92641, 0x010a050d, - 0x22f911fb, 0x000f6482, 0xb0b229bf, 0x000f7081, 0x7e249b90, 0xbf000c0f, 0xbc2abf19, 0xaa900009, - 0x0c517e10, 0xb529bf00, 0x19bf0490, 0x18f409a6, 0x1050890b, 0x067d3e00, 0x10548900, 0xbf9abf00, - 0x10bb902b, 0x000c0f7e, 0x30f421fb, 0x0f7489fc, 0xbf82f900, 0x0090b399, 0x89010f10, 0xa0000f7c, - 0x08453e9f, 0x0f648900, 0x0148fe00, 0x95bf91b2, 0x343d243d, 0x388064bd, 0x6c870010, 0x6884000f, - 0x8890000f, 0x06d23e24, 0x3d09bf00, 0x01999224, 0x09bf09a0, 0x000f848e, 0xb6049f94, 0x9fbc0294, + 0x0005397e, 0x3400a9b3, 0x04f63eff, 0x3eef0000, 0x400004f6, 0x0ab2fe0c, 0x890c85fb, 0xbf000f98, + 0x8900f89a, 0xbf000f8c, 0x8900f89a, 0xbf000f9c, 0x0096b099, 0xf00bacf0, 0x00f801a6, 0x000fa089, + 0xa9a099bf, 0x000f9889, 0xa9b599bf, 0x0f00f801, 0x0fa48901, 0xf89fa000, 0xb222f900, 0x7eb2b2a0, + 0x89000a74, 0xbf000fa0, 0xa609bf9f, 0x110bf4f9, 0x000f9889, 0x09989fbf, 0xf4f9a601, 0x988d3318, + 0x0e98000f, 0xbfd9bf01, 0x029ebb2f, 0x18f49fa6, 0xbdd9bf20, 0x92e9bc14, 0xa0909fbc, 0x0fa08929, + 0xa099bf00, 0xb5d9bf09, 0x903e0109, 0x01010005, 0x000a9b7e, 0x21fb1ab2, 0x000a747e, 0x000f9c8f, + 0x9990f9bf, 0x7ef9a001, 0xf8000a9b, 0x8002f900, 0xbf000fac, 0x0196b009, 0x7e070df4, 0x7e00000e, + 0x3e000a8f, 0x8e0005b3, 0x18001060, 0xefbf41a9, 0x9ac4abb2, 0xf4afa6ff, 0xeaa0050d, 0xb604a994, + 0xa9bc02a4, 0x0fac89a0, 0x10bb9000, 0x7ea0a9bc, 0xf8000bee, 0x9812f900, 0x909803a9, 0x24019003, + 0x517e1ab2, 0x9c89000c, 0x99bf000f, 0x150094b3, 0x7e100a90, 0xb2000c51, 0x05c77e0a, 0x062b3e00, + 0x8a1bb200, 0x7e001064, 0x89000bee, 0xbf000f8c, 0x410f1899, 0x9918a4bd, 0xf4f92641, 0x010a050d, + 0x22f911fb, 0x000f8c82, 0xb0b229bf, 0x000f9881, 0x7e249b90, 0xbf000c0f, 0xbc2abf19, 0xaa900009, + 0x0c517e10, 0xb529bf00, 0x19bf0490, 0x18f409a6, 0x1078890b, 0x067d3e00, 0x107c8900, 0xbf9abf00, + 0x10bb902b, 0x000c0f7e, 0x30f421fb, 0x0f9c89fc, 0xbf82f900, 0x0090b399, 0x89010f10, 0xa0000fa4, + 0x08453e9f, 0x0f8c8900, 0x0148fe00, 0x95bf91b2, 0x343d243d, 0x608064bd, 0x94870010, 0x9084000f, + 0x8890000f, 0x06d23e24, 0x3d09bf00, 0x01999224, 0x09bf09a0, 0x000fac8e, 0xb6049f94, 0x9fbc0294, 0x909ebc90, 0x99b399bf, 0xbf013d00, 0xb949bf7f, 0xf9a60099, 0xbf0f0bf4, 0x7eec0b1a, 0x3e000a95, - 0xbf000742, 0x0090b349, 0x0859983d, 0xfe940fbf, 0x02f4b604, 0x8ef0febc, 0xbc000f84, 0x9fa6f0fe, + 0xbf000742, 0x0090b349, 0x0859983d, 0xfe940fbf, 0x02f4b604, 0x8ef0febc, 0xbc000fac, 0x9fa6f0fe, 0xbf221bf4, 0x92b4bd49, 0x49a00199, 0x99b949bf, 0xa079a000, 0x7e1abf15, 0xb0000a89, 0x1ff500a6, - 0x0fbf00f9, 0xfd9409bf, 0x049e9404, 0xbc0294b6, 0x848e909e, 0x9ebc000f, 0x01999890, 0xbc02f4b6, + 0x0fbf00f9, 0xfd9409bf, 0x049e9404, 0xbc0294b6, 0xac8e909e, 0x9ebc000f, 0x01999890, 0xbc02f4b6, 0xfebcf0fd, 0x019998f0, 0xbf01f9b5, 0x049f9409, 0xbc0294b6, 0x9ebc909f, 0x019e9890, 0x9f9409bf, - 0x0294b604, 0x8f909fbc, 0xbc000f8c, 0xe9a6909f, 0xbf2c1bf4, 0x9409bf0f, 0x9e9404fd, 0x0294b604, - 0x8e909ebc, 0xbc000f84, 0x9998909e, 0x02f4b601, 0xbcf0fdbc, 0x9998f0fe, 0x01f9b501, 0x9f9409bf, - 0x0294b604, 0x8f909fbc, 0xbc000f84, 0x9998909f, 0x03999801, 0x1abf19a0, 0x000a617e, 0x1000a4b3, + 0x0294b604, 0x8f909fbc, 0xbc000fb4, 0xe9a6909f, 0xbf2c1bf4, 0x9409bf0f, 0x9e9404fd, 0x0294b604, + 0x8e909ebc, 0xbc000fac, 0x9998909e, 0x02f4b601, 0xbcf0fdbc, 0x9998f0fe, 0x01f9b501, 0x9f9409bf, + 0x0294b604, 0x8f909fbc, 0xbc000fac, 0x9998909f, 0x03999801, 0x1abf19a0, 0x000a617e, 0x1000a4b3, 0xeb0b1abf, 0x000a957e, 0x0007fa3e, 0x8bb21abf, 0x000a897e, 0xf400a6b0, 0x2210401f, 0x01331001, - 0x06013433, 0x09bf06bf, 0x94ff2ec4, 0x94b6049f, 0x909fbc02, 0x000f848f, 0xbf909fbc, 0xf5e9a699, - 0xbffeb31b, 0x009db309, 0x1abffea4, 0x7efe0b4b, 0x3e000a95, 0x330006d2, 0x890a0030, 0xa0001038, - 0x0ad07e96, 0x0485fb00, 0x748922f9, 0x99bf000f, 0xcd009db3, 0x106c8900, 0x899fbf00, 0xbf000f70, - 0x0099b999, 0x0bf4f9a6, 0x0f64890f, 0x0b9abf00, 0x0a957eec, 0x0f708e00, 0x8fe9bf00, 0x9000106c, - 0xe9a00199, 0x99b9e9bf, 0xbff9a000, 0x0094b3e9, 0x10548f1f, 0x10508e00, 0xbffcbf00, 0x0f788de9, - 0xa0f9a000, 0x90d9bfec, 0xd9a00199, 0x0010548f, 0x99bff9bf, 0x0a0094b3, 0x003e04bd, 0xf9bf0009, + 0x06013433, 0x09bf06bf, 0x94ff2ec4, 0x94b6049f, 0x909fbc02, 0x000fac8f, 0xbf909fbc, 0xf5e9a699, + 0xbffeb31b, 0x009db309, 0x1abffea4, 0x7efe0b4b, 0x3e000a95, 0x330006d2, 0x890a0030, 0xa0001060, + 0x0ad07e96, 0x0485fb00, 0x9c8922f9, 0x99bf000f, 0xcd009db3, 0x10948900, 0x899fbf00, 0xbf000f98, + 0x0099b999, 0x0bf4f9a6, 0x0f8c890f, 0x0b9abf00, 0x0a957eec, 0x0f988e00, 0x8fe9bf00, 0x90001094, + 0xe9a00199, 0x99b9e9bf, 0xbff9a000, 0x0094b3e9, 0x107c8f1f, 0x10788e00, 0xbffcbf00, 0x0fa08de9, + 0xa0f9a000, 0x90d9bfec, 0xd9a00199, 0x00107c8f, 0x99bff9bf, 0x0a0094b3, 0x003e04bd, 0xf9bf0009, 0x98039998, 0x003e0390, 0x2fbf0009, 0xa6040998, 0x3e08f4f9, 0x000c517e, 0x900d0998, 0x90b3240a, 0x517e0800, 0x0ab2000c, 0x0005c77e, 0x99bf19bf, 0x1f0090b3, 0x999819bf, 0x03909803, 0x0009083e, - 0x000f7082, 0x00105481, 0xb3100a90, 0x89bf0004, 0xbf001070, 0x0094b399, 0x09283e17, 0x10708f00, - 0x90f9bf00, 0xf9a00199, 0x000a877e, 0x32f921fb, 0x000f7481, 0xe90019bf, 0xc00099b3, 0x0a747e00, - 0x9219bf00, 0x19a00199, 0x9db319bf, 0x8900a800, 0xbf001074, 0x0099b399, 0x3c8f009d, 0xf9bf0010, - 0x0a0094b3, 0x703e04bd, 0xf9980009, 0x03909803, 0x648314bd, 0x3c82000f, 0xaa3e0010, 0x517e0009, + 0x000f9882, 0x00107c81, 0xb3100a90, 0x89bf0004, 0xbf001098, 0x0094b399, 0x09283e17, 0x10988f00, + 0x90f9bf00, 0xf9a00199, 0x000a877e, 0x32f921fb, 0x000f9c81, 0xe90019bf, 0xc00099b3, 0x0a747e00, + 0x9219bf00, 0x19a00199, 0x9db319bf, 0x8900a800, 0xbf00109c, 0x0099b399, 0x648f009d, 0xf9bf0010, + 0x0a0094b3, 0x703e04bd, 0xf9980009, 0x03909803, 0x8c8314bd, 0x6482000f, 0xaa3e0010, 0x517e0009, 0x0a90000c, 0x0c517e10, 0x7e0ab200, 0xbf0005c7, 0x410f1839, 0x99182ebf, 0xf4f92641, 0x0101050d, - 0x1100e0b3, 0x98032998, 0x0a900390, 0x0004b324, 0x10708fd1, 0xb3f9bf00, 0xb21b0090, 0x08487ef0, - 0x9209bf00, 0x09a00199, 0x94b309bf, 0xe03ef300, 0x10b30009, 0x7c890e01, 0x99bf000f, 0x160194b3, - 0x7c89f4bd, 0x0100000f, 0x0e7e9fa0, 0xf43e0000, 0x04bd0009, 0x000a9b7e, 0x31fb0ab2, 0x748932f9, - 0x99bf000f, 0xf70fa3b2, 0x550094b3, 0x4b00a0b3, 0x0005987e, 0x000f7081, 0x000f6482, 0x2abf10bf, - 0x900030bc, 0x517e10aa, 0x29bf000c, 0xbf0490b5, 0xf409a619, 0x50890b18, 0x423e0010, 0x5489000a, + 0x1100e0b3, 0x98032998, 0x0a900390, 0x0004b324, 0x10988fd1, 0xb3f9bf00, 0xb21b0090, 0x08487ef0, + 0x9209bf00, 0x09a00199, 0x94b309bf, 0xe03ef300, 0x10b30009, 0xa4890e01, 0x99bf000f, 0x160194b3, + 0xa489f4bd, 0x0100000f, 0x0e7e9fa0, 0xf43e0000, 0x04bd0009, 0x000a9b7e, 0x31fb0ab2, 0x9c8932f9, + 0x99bf000f, 0xf70fa3b2, 0x550094b3, 0x4b00a0b3, 0x0005987e, 0x000f9881, 0x000f8c82, 0x2abf10bf, + 0x900030bc, 0x517e10aa, 0x29bf000c, 0xbf0490b5, 0xf409a619, 0x78890b18, 0x423e0010, 0x7c89000a, 0x9abf0010, 0xbb902bbf, 0x0c0f7e10, 0x092e7e00, 0xb3010f00, 0x7e0a00a4, 0x0f00000e, 0xfbfab201, 0x00a0b331, 0x03a99811, 0x99b9afbf, 0xf0f9a600, 0x00f80bac, 0xf41032f4, 0x548f1132, 0xf9bf0005, - 0xa0019990, 0xf800f8f9, 0x10107e00, 0x7e00f800, 0xf8001885, 0x18b47e00, 0x8f00f800, 0xbf000554, + 0xa0019990, 0xf800f8f9, 0x10107e00, 0x7e00f800, 0xf8001842, 0x184a7e00, 0x8f00f800, 0xbf000554, 0x0094b3f9, 0x1032f41a, 0xbd1132f4, 0x7eee0ba4, 0xf4000a95, 0x31f41031, 0xbf00f811, 0x019992f9, - 0xf9bff9a0, 0x0a0094b3, 0xf41031f4, 0x00f81131, 0x0041407e, 0xc9fe00f8, 0x1495b601, 0x3c089033, + 0xf9bff9a0, 0x0a0094b3, 0xf41031f4, 0x00f81131, 0x0038a77e, 0xc9fe00f8, 0x1495b601, 0x3c089033, 0xf4089630, 0x9033130c, 0x90332002, 0x90333403, 0x1c3e1800, 0x9033000b, 0x9033280f, 0x94331810, 0x0c3e1e0a, 0x8a7e000b, 0x00f80006, 0x0013bc7e, 0xb07e00f8, 0x00f80013, 0x00f802f8, 0x00f802f8, - 0x0041557e, 0x000ad67e, 0x0041407e, 0x02f900f8, 0x0041557e, 0xcf020049, 0xa0800099, 0x0fbf0010, + 0x0038bc7e, 0x000ad67e, 0x0038a77e, 0x02f900f8, 0x0038bc7e, 0xcf020049, 0xc8800099, 0x0fbf0010, 0xf4049ffd, 0x487e170b, 0x8a7e0008, 0x0fbf0006, 0xfa010049, 0x623e009f, 0xa4bd000b, 0x957eda0b, - 0x407e000a, 0x01fb0041, 0x0041557e, 0x00185a7e, 0x0800a0b3, 0x00068a7e, 0x0041407e, 0x94bd00f8, + 0xa77e000a, 0x01fb0038, 0x0038bc7e, 0x0018397e, 0x0800a0b3, 0x00068a7e, 0x0038a77e, 0x94bd00f8, 0x000b8d3e, 0x3cf8b93c, 0x999099af, 0xf49ca601, 0x00f8f508, 0xa23ea9b2, 0x9b20000b, 0x9001cc92, 0xc4b30199, 0x00f8f800, 0xc73ee4bd, 0xae3c000b, 0x98be3cf8, 0x2601ee90, 0x0e0bf4f9, 0xf0fff4f0, 0xf9bcff94, 0xa600f8a2, 0xe508f4ec, 0x00f8a4bd, 0xb508af90, 0xff0901af, 0xb502a9b5, 0xafb503af, @@ -134,19 +134,19 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xfbb502bf, 0x04bab501, 0x9990a9bf, 0xf8a9a001, 0x01af9800, 0xb502a998, 0xaf9802f9, 0x01a99802, 0x9801f9b5, 0xf99804af, 0xf49aa601, 0xa998091b, 0x01f9b502, 0xa9b594bd, 0x92f9bf04, 0xf9a00199, 0x72f900f8, 0xb202b998, 0xb2b1b2a5, 0x1d9a95c2, 0xb2249034, 0x32e732d4, 0x009033a6, 0x7e23000f, - 0x330018d7, 0x011200a9, 0x119819bf, 0x2029bc01, 0x18f429a6, 0xa6ff0921, 0x0a0bf419, 0x3e011190, - 0x7e000cd3, 0x0b0000ea, 0x7e020002, 0x3e0018b4, 0xc4000db5, 0x45ffff23, 0xfd3f0095, 0x94f00593, + 0x3300184e, 0x011200a9, 0x119819bf, 0x2029bc01, 0x18f429a6, 0xa6ff0921, 0x0a0bf419, 0x3e011190, + 0x7e000cd3, 0x0b0000ea, 0x7e020002, 0x3e00184a, 0xc4000db5, 0x45ffff23, 0xfd3f0095, 0x94f00593, 0xd41bf503, 0x0a747e00, 0x0e067e00, 0x01fafe00, 0xfe081995, 0x7bfe009f, 0x01bcfe01, 0x95181994, 0x9ffd082f, 0x0097fe05, 0xe4ff69c4, 0x33ffffcf, 0xf10f0070, 0xb6f8fff4, 0x253e0894, 0xf4f1000d, 0x94b68fff, 0x95f9ff0c, 0x3e009bfe, 0xe5000d92, 0xfd010059, 0x9fb90593, 0x04f9fd01, 0x000d433e, 0xa601f5b6, 0xfb0cf4f4, 0xbd03fd95, 0x0d543ee4, 0x01d5b600, 0xd0b3e932, 0xee900c00, 0x00eeb301, 0x94f0f401, 0xff5ee4ff, 0x007033ff, 0x0794f014, 0xfd1094b6, 0x39fa059e, 0x0d893e05, 0x0794f000, 0xfd1094b6, 0x39fa059e, 0x024fbb06, 0xbc303fbc, 0x44b3505f, 0xaffe9d00, 0x00b7fe00, 0xf800cbfe, - 0x7e170003, 0x3300195a, 0x3d0600a4, 0x0a9b7e04, 0x0ddd7e00, 0xfb0a3200, 0xf4010971, 0xe43dfc30, + 0x7e170003, 0x3300186b, 0x3d0600a4, 0x0a9b7e04, 0x0ddd7e00, 0xfb0a3200, 0xf4010971, 0xe43dfc30, 0x7e009130, 0xf4000c82, 0x00f80430, 0x0efc30f4, 0x00e13001, 0x000c827e, 0xf80430f4, 0x0a747e00, - 0x10a48f00, 0xb3f9bf00, 0xbf0f0090, 0x019992f9, 0x003ef9a0, 0xea7e000e, 0x030b0000, 0x0018b47e, - 0x000a9b7e, 0x747e00f8, 0xa48e000a, 0xefbf0010, 0xf9a6ff09, 0xbf0e0bf4, 0x019990e9, 0x2c3ee9a0, - 0xea7e000e, 0x030b0000, 0x0018b47e, 0x000a9b7e, 0x12f900f8, 0xafbfb9b2, 0xa0b29e3f, 0xb204d192, + 0x10cc8f00, 0xb3f9bf00, 0xbf0f0090, 0x019992f9, 0x003ef9a0, 0xea7e000e, 0x030b0000, 0x00184a7e, + 0x000a9b7e, 0x747e00f8, 0xcc8e000a, 0xefbf0010, 0xf9a6ff09, 0xbf0e0bf4, 0x019990e9, 0x2c3ee9a0, + 0xea7e000e, 0x030b0000, 0x00184a7e, 0x000a9b7e, 0x12f900f8, 0xafbfb9b2, 0xa0b29e3f, 0xb204d192, 0x18fe20cb, 0x1cb2019e, 0x1801fe35, 0xfe35029e, 0x03991802, 0xbf03f935, 0x04aa90aa, 0x7e7e0aa0, 0x09bf000b, 0xa09091bc, 0xf411fb09, 0x62f9f430, 0xb2b2a3b2, 0xd532c6b2, 0x0c00b4b3, 0x043d09f8, 0x000f513e, 0x0001b918, 0xff94f001, 0xe4039990, 0xf501fc91, 0xbf00be0b, 0x7eff0baa, 0x980000de, @@ -154,22 +154,22 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xa0a6f010, 0xa60d0df4, 0x8d18f5fa, 0x0f0b3e00, 0x02399800, 0x08f4f9a6, 0x01399835, 0xa69019bc, 0x7518f49a, 0x3d063e98, 0x014ffe94, 0x351cff90, 0xf92003f9, 0x0902f935, 0x35fbb204, 0x4ab201f9, 0x040dc4bd, 0x3998e5f9, 0x9849a001, 0x1db20639, 0x2bb26cb2, 0x900140fe, 0x0ab22000, 0x41fe95f9, - 0x0142fe01, 0x90271190, 0x1ab22622, 0xf77e2bb2, 0x020a0040, 0x117eab32, 0x0abf0041, 0x00043998, - 0x3f95f901, 0x7e2b3f1a, 0xbf004111, 0x009b7e3a, 0xfb0a3200, 0x5d330c65, 0x3dff5c00, 0x0f4b3e04, - 0x3dbcb200, 0x8aabb2d4, 0x7e0010a8, 0xf8000e6b, 0x0dbcb200, 0x8aabb201, 0x7e0010a8, 0xf8000e6b, - 0xb212f900, 0xb3b132a0, 0xf80a00a4, 0x100e3e09, 0x2d808900, 0x0b9abf00, 0x00de7eff, 0xff19c400, + 0x0142fe01, 0x90271190, 0x1ab22622, 0x5e7e2bb2, 0x020a0038, 0x787eab32, 0x0abf0038, 0x00043998, + 0x3f95f901, 0x7e2b3f1a, 0xbf003878, 0x009b7e3a, 0xfb0a3200, 0x5d330c65, 0x3dff5c00, 0x0f4b3e04, + 0x3dbcb200, 0x8aabb2d4, 0x7e0010d0, 0xf8000e6b, 0x0dbcb200, 0x8aabb201, 0x7e0010d0, 0xf8000e6b, + 0xb212f900, 0xb3b132a0, 0xf80a00a4, 0x100e3e09, 0x2e808900, 0x0b9abf00, 0x00de7eff, 0xff19c400, 0x0301008f, 0xbc099e94, 0xefcfe0ef, 0x8099b800, 0x94b60001, 0x009dcf09, 0xf0020918, 0x09352095, 0xf40fa602, 0xf63e411b, 0xf918000f, 0x2094f002, 0x3f340bf4, 0x009433f9, 0xf8cbbc0b, 0x000fef3e, - 0xf001f918, 0x9990ff94, 0x049afd03, 0xf6f0f9bc, 0xff3e00ef, 0x1bc4000f, 0x8cfc0aff, 0xa6002d68, - 0xc91bf4fd, 0x002d8089, 0x9b7e9abf, 0x11fb0000, 0xd48b02f9, 0x127e0010, 0xa0320000, 0x0f00a033, - 0x0000ea7e, 0x7eff0bc4, 0x890018b4, 0xbf0010d4, 0x10d88990, 0x899fbf00, 0x180010c4, 0x9e35180e, + 0xf001f918, 0x9990ff94, 0x049afd03, 0xf6f0f9bc, 0xff3e00ef, 0x1bc4000f, 0x8cfc0aff, 0xa6002e68, + 0xc91bf4fd, 0x002e8089, 0x9b7e9abf, 0x11fb0000, 0xfc8b02f9, 0x127e0010, 0xa0320000, 0x0f00a033, + 0x0000ea7e, 0x7eff0bc4, 0x8900184a, 0xbf0010fc, 0x11008990, 0x899fbf00, 0x180010ec, 0x9e35180e, 0xf40fa60e, 0x0918101b, 0x00943319, 0x3ea4bd0a, 0x1800107a, 0xb4331d0b, 0xa4bd0a00, 0x00106f3e, - 0x3d200a90, 0x13607ec4, 0x00a6b000, 0x3d0e1ef4, 0x19093594, 0x0010d889, 0x01fb90a0, 0x89ffa4f0, - 0x8c003031, 0xbc003024, 0xacbcd0a9, 0x3fdf3fa0, 0x30318cae, 0xffe9c400, 0x20909cbc, 0x3024899f, - 0xfff4f000, 0x20f0f9bc, 0x20943dfe, 0xf900f8d9, 0x30318922, 0xffa0c400, 0x3f2009bc, 0x33a1322e, - 0x7e0c00e0, 0x3e00107c, 0x8f0010e0, 0x3f0010dc, 0xf4a926f9, 0x947d0d1b, 0xf975fe20, 0x01f97502, - 0x00303189, 0x91209f3f, 0x00302489, 0x3d0009bc, 0x20092094, 0x3024892f, 0xfff4f000, 0x20f0f9bc, - 0xf921fbf1, 0x10dc8f52, 0x32943d00, 0xb2c332b4, 0x35f5b2a2, 0x143d01f9, 0x00113a3e, 0x1110203f, + 0x3d200a90, 0x13607ec4, 0x00a6b000, 0x3d0e1ef4, 0x19093594, 0x00110089, 0x01fb90a0, 0x89ffa4f0, + 0x8c003131, 0xbc003124, 0xacbcd0a9, 0x3fdf3fa0, 0x31318cae, 0xffe9c400, 0x20909cbc, 0x3124899f, + 0xfff4f000, 0x20f0f9bc, 0x20943dfe, 0xf900f8d9, 0x31318922, 0xffa0c400, 0x3f2009bc, 0x33a1322e, + 0x7e0c00e0, 0x3e00107c, 0x8f0010e0, 0x3f001104, 0xf4a926f9, 0x947d0d1b, 0xf975fe20, 0x01f97502, + 0x00313189, 0x91209f3f, 0x00312489, 0x3d0009bc, 0x20092094, 0x3124892f, 0xfff4f000, 0x20f0f9bc, + 0xf921fbf1, 0x11048f52, 0x32943d00, 0xb2c332b4, 0x35f5b2a2, 0x143d01f9, 0x00113a3e, 0x1110203f, 0x01229001, 0x16000033, 0x3b320a32, 0x0010af7e, 0x33015918, 0x35070094, 0x14260150, 0xfbe008f4, 0xfc30f451, 0xb13212f9, 0x900140fe, 0x0bb20800, 0x0000127e, 0x0e1800bf, 0x0014331d, 0x4f02f806, 0xf3f1000b, 0x19c40000, 0xf49fa6ff, 0xed320b0c, 0x9f3ef43d, 0x02f80011, 0xed32f43d, 0x00119f3e, @@ -178,20 +178,20 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xfd19f918, 0xf935059a, 0x0415fb19, 0x0011417e, 0x0600a433, 0x00f802f8, 0xf9fc30f4, 0x32a0b212, 0x0a747eb1, 0xfe0ab200, 0x00900140, 0x7e0bb208, 0xbf000012, 0x18f43d00, 0x163e1d0d, 0xe9180012, 0x01ff1020, 0x2620ee90, 0x0d1bf491, 0x0100943d, 0x233ee920, 0xf9c40012, 0xe009bcff, 0x08f4fd26, - 0x7e043de0, 0x32000a9b, 0x0415fb0a, 0x0011d87e, 0x0600a433, 0x00f802f8, 0xa4f082f9, 0x30008fff, - 0x30188e00, 0x58fa7c00, 0xb298ea3c, 0xbdc632b7, 0xff94f034, 0x00055888, 0x8120597c, 0x3e0010dc, + 0x7e043de0, 0x32000a9b, 0x0415fb0a, 0x0011d87e, 0x0600a433, 0x00f802f8, 0xa4f082f9, 0x31008fff, + 0x31188e00, 0x58fa7c00, 0xb298ea3c, 0xbdc632b7, 0xff94f034, 0x00055888, 0x8120597c, 0x3e001104, 0x52001354, 0x29e40122, 0x9494ffff, 0x034ffe08, 0xb31ff995, 0xd0100190, 0x03000000, 0xf594f0ff, 0xbf00d51b, 0x01008e89, 0x089f9500, 0xfffff9e4, 0x18f59ea6, 0x99900010, 0x0894b601, 0x473e89a0, - 0x1f580013, 0x02195801, 0x1bf4f966, 0x000b4945, 0x000093f1, 0x0030248f, 0x18909fbc, 0x19180190, - 0xf4092601, 0x02f8051b, 0xb43d0a32, 0x00107c7e, 0x0030188e, 0x3cff09c4, 0x008ef8e9, 0xe97c0030, + 0x1f580013, 0x02195801, 0x1bf4f966, 0x000b4945, 0x000093f1, 0x0031248f, 0x18909fbc, 0x19180190, + 0xf4092601, 0x02f8051b, 0xb43d0a32, 0x00107c7e, 0x0031188e, 0x3cff09c4, 0x008ef8e9, 0xe97c0031, 0xf0102098, 0x1975fff4, 0xf09f7c01, 0x58021f75, 0x9b520219, 0xffb9e401, 0x021b75ff, 0xfe0894b6, 0xa995039a, 0x0190b31f, 0x3d7cb29d, 0x133f3ed4, 0x10c93f00, 0xcc9001dd, 0xff9fc401, 0x23009033, - 0x00300080, 0x80e80f7c, 0x3c003018, 0xbe66980f, 0xf00f08f4, 0xe97cff94, 0xf5b96690, 0x26ff6708, + 0x00310080, 0x80e80f7c, 0x3c003118, 0xbe66980f, 0xf00f08f4, 0xe97cff94, 0xf5b96690, 0x26ff6708, 0xd008f4d6, 0xe4ffafc4, 0xb6fffff9, 0x49fa0894, 0x01339004, 0x0cf52566, 0x07f8ff0d, 0x81fb3ab2, 0xc53252f9, 0xb332a4b2, 0x0800a0b3, 0x0c00b433, 0xff0a02f8, 0x0013ae3e, 0x41b2c43d, 0x0011037e, 0x043d24bd, 0x0013a73e, 0x00101a3f, 0x01119001, 0x1700a033, 0x3c324bb2, 0x387e5d32, 0x2abc0012, - 0x00a6b020, 0x260a1ef4, 0xdf08f403, 0x51fb2ab2, 0x0000ea7e, 0xb47e2f0b, 0x00f80018, 0x0000ea7e, - 0xb47e2f0b, 0x00f80018, 0xa93f22f9, 0xd0b2c1b2, 0x3204c0b4, 0xff94f0ed, 0x08f4b9a6, 0x9402f805, + 0x00a6b020, 0x260a1ef4, 0xdf08f403, 0x51fb2ab2, 0x0000ea7e, 0x4a7e2f0b, 0x00f80018, 0x0000ea7e, + 0x4a7e2f0b, 0x00f80018, 0xa93f22f9, 0xd0b2c1b2, 0x3204c0b4, 0xff94f0ed, 0x08f4b9a6, 0x9402f805, 0xb99402bf, 0x02ae9804, 0x5200c0b3, 0x3cf0f9bc, 0xa998f9ed, 0x18203402, 0x0e1e0dcc, 0x909fbc01, 0x98019235, 0xebbb02a9, 0x909fbc04, 0x980191b5, 0x9fbc02a9, 0x029db590, 0xbc02a998, 0x9cb5909f, 0x02a99803, 0xb4909fbc, 0x9fb505f0, 0x01a99804, 0xb5059efd, 0x543e01a9, 0xf9bc0014, 0x90e9bc90, @@ -209,1599 +209,1319 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xaabf0099, 0xf8a29abc, 0xb242f900, 0xb2b3b2a0, 0x00c0b3c1, 0x0b004929, 0xb20092cf, 0x0000b394, 0xf93ab212, 0x00a03305, 0x3e010a0a, 0xcf0015e8, 0x92bb0049, 0xf491a602, 0x04b3e608, 0xa43d0a00, 0x0015e83e, 0x05f93ab2, 0x000041fb, 0xd24e0041, 0x00000554, 0x90fc00f8, 0x0015ea7e, 0xf90188fe, - 0x00289880, 0x64d880f9, 0x9800000f, 0x47fe0088, 0xbd87a001, 0x0387b570, 0xfe0010f7, 0xb7b600a4, - 0x1fb9f002, 0xf9001bf7, 0x7e00f890, 0x3e0015ea, 0xf9001647, 0x3450daf2, 0x50db0000, 0x7e000032, - 0x7e0015f6, 0xf7000b68, 0x64d80010, 0x9800000f, 0x87980088, 0x0074fe00, 0xb6028798, 0x79f00277, - 0x0017f71f, 0x28a080fc, 0x88fe80fc, 0xf8f0fb00, 0xdaf2f901, 0x00003450, 0x003250db, 0x15f67e00, - 0x0b2e7e00, 0x16473e00, 0x1832f400, 0x50daf2f9, 0xdb000032, 0x00003050, 0x0015f67e, 0x000b207e, - 0x0016473e, 0xf91832f4, 0x0188fef2, 0x3b7e80f9, 0x80fc0040, 0xfb0088fe, 0xb201f8f0, 0xb0afb2a9, + 0x00289880, 0x8cd880f9, 0x9800000f, 0x47fe0088, 0xbd87a001, 0x0387b570, 0xfe0010f7, 0xb7b600a4, + 0x1fb9f002, 0xf9001bf7, 0x7e00f890, 0x3e0015ea, 0xf9001647, 0x3550daf2, 0x50db0000, 0x7e000033, + 0x7e0015f6, 0xf7000b68, 0x8cd80010, 0x9800000f, 0x87980088, 0x0074fe00, 0xb6028798, 0x79f00277, + 0x0017f71f, 0x28a080fc, 0x88fe80fc, 0xf8f0fb00, 0xdaf2f901, 0x00003550, 0x003350db, 0x15f67e00, + 0x0b2e7e00, 0x16473e00, 0x1832f400, 0x50daf2f9, 0xdb000033, 0x00003150, 0x0015f67e, 0x000b207e, + 0x0016473e, 0xf91832f4, 0x0188fef2, 0xa27e80f9, 0x80fc0037, 0xfb0088fe, 0xb201f8f0, 0xb0afb2a9, 0x1ef400a6, 0xb0bab22b, 0x1ef400b6, 0xacfaff13, 0xf496b9ff, 0x00f8051e, 0xf801aab9, 0x01bab900, 0xffacfaff, 0x1ff496b9, 0x16d83ef0, 0x01afb900, 0xb6b0bab2, 0xd81ff400, 0x0016dd3e, 0x95e0abff, - 0xbf9510a9, 0x01b9fd10, 0xbb01affd, 0xa4b600ab, 0x00aebb10, 0xdcdf00f8, 0xf4000005, 0x62f9fc30, - 0xffbffebf, 0x900149fe, 0x9ea01c99, 0x0005e0d9, 0xbd9fa000, 0x010089f4, 0x009ff601, 0xb87fff4f, - 0x003f0099, 0xdf009ff6, 0x03ff0000, 0x010099b8, 0x009ff600, 0x00ff808f, 0x0a0099b8, 0x009ff600, - 0xb810004f, 0x024a0099, 0xd6009ff6, 0x40000000, 0x011c0085, 0x0005f0d0, 0x02008400, 0x00008301, - 0xaaa0d210, 0xfd01beef, 0x227e080a, 0xa6fd001c, 0x280bf504, 0x0049cf00, 0xf50493fd, 0xde001e0b, - 0x000005f0, 0xf2fff4bd, 0x90e9a095, 0xee9001ff, 0x04f4b304, 0x17f03ef5, 0x0059cf00, 0xf40194f0, - 0x3cf4fa1b, 0xf009b21f, 0x99fa0593, 0xf503f806, 0xf590043c, 0xf590033c, 0xf5ac543c, 0xf5c4043c, - 0xb2d0333c, 0x0393f009, 0xf80599fa, 0x003cf403, 0xe9920ebf, 0xf491a601, 0x0e98250d, 0x01e99201, - 0x0df491a6, 0x020e981a, 0xa601e992, 0x0f0df491, 0x92030e98, 0x91a601e9, 0xff700cf5, 0x0005f0df, - 0xd094bd00, 0x000005dc, 0xa003f9b5, 0x01f9b5f9, 0xa002f9b5, 0x589a7e0e, 0x05e0d900, 0x99bf0000, - 0x09a0a4bd, 0x900149fe, 0x9fbf1c99, 0xf9a609bf, 0x7e070bf4, 0xfb0042e9, 0x30f40465, 0xd112f9fc, - 0x000005dc, 0x40fe19bf, 0x08009001, 0xcf7e09a0, 0x0fbf0019, 0xa4f019bf, 0xf4f9a6ff, 0xe97e070b, - 0x15fb0042, 0x05dcdf04, 0xffbf0000, 0xfefc30f4, 0x9fa00149, 0xf40031f4, 0x49fe0028, 0xd99fbf01, - 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xf40042e9, 0x00f80430, 0x0005dcde, 0xf4efbf00, 0x49fefc30, - 0xf89fa001, 0xbf9fbf02, 0xf4f9a6e9, 0xe97e070b, 0x30f40042, 0xf400f804, 0x12f9fc30, 0x0005dcd1, - 0xfe19bf00, 0x00900140, 0x7e09a008, 0xbf001a81, 0xa619bf0f, 0x070bf4f9, 0x0042e97e, 0xd90415fb, - 0x00001334, 0xf9fc30f4, 0x05dcd112, 0x9b180000, 0x0c9a180d, 0x40fe19bf, 0x08009001, 0xe67e09a0, - 0x0fbf001b, 0xf9a619bf, 0x7e070bf4, 0xfb0042e9, 0x30f40415, 0xd112f9fc, 0x000005dc, 0x40fe19bf, - 0x08009001, 0xe67e09a0, 0x0fbf001b, 0xf9a619bf, 0x7e070bf4, 0xfb0042e9, 0x30f40415, 0xd112f9fc, - 0x000005dc, 0x40fe19bf, 0x08009001, 0x517e09a0, 0x0fbf001b, 0xf9a619bf, 0x7e070bf4, 0xfb0042e9, - 0xdcdf0415, 0xbf000005, 0xfc30f4ff, 0xa00149fe, 0x1400899f, 0x0099cf02, 0xf40194f0, 0x1f7e180b, - 0x008f0047, 0xf9ce0213, 0x0195f000, 0x3e00f9f7, 0xf80019b5, 0x0149fe02, 0xdcd99fbf, 0xbf000005, - 0xf4f9a699, 0xe97e070b, 0x30f40042, 0xf400f804, 0xdcdff830, 0xf9000005, 0xfeffbf02, 0x99900149, - 0x3d9fa008, 0x2d89d9f4, 0x9f200000, 0xcf06004f, 0x004e00ff, 0x00eecf07, 0xcf020049, 0x9ffd0099, - 0x10ef9504, 0xfd00eeb9, 0xffb9049e, 0x049fff00, 0xf40109c4, 0x5e7e070b, 0x09e40044, 0x0bf41000, - 0xfe010f2f, 0x008e0149, 0x99900289, 0xce9f2007, 0xfe0f00e9, 0xf7049ffd, 0x08d900e9, 0xbf000013, - 0x014bfe9a, 0xbb90010c, 0x006e7e07, 0x0009e400, 0x00907380, 0x19827e08, 0x01004900, 0xfe0090f7, - 0x99900149, 0xd99ebf08, 0x000005dc, 0x89d99fbf, 0x3f00002d, 0xf4efa69a, 0xe97e070b, 0x05fb0042, - 0x05dcde08, 0xefbf0000, 0xfefc30f4, 0x010a0149, 0x9fbf9fa0, 0xf9a6e9bf, 0x7e070bf4, 0xf40042e9, - 0x00f80430, 0xdffc30f4, 0x000005dc, 0xffbf02f9, 0x900149fe, 0xa0b20499, 0xa9989fa0, 0x0194f003, - 0xbf0d0bf4, 0x1c227eaa, 0x1ad23e00, 0xcfa9bf00, 0x0f98009a, 0x01099803, 0xf0020e98, 0xa9ff02f4, - 0xf09ea694, 0x9a320b9c, 0x0c00f0b3, 0xf0009630, 0x9a320b9c, 0x900149fe, 0x9fbf0499, 0x0005dcd9, - 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf40405fb, 0x12f9ec30, 0x900149fe, 0xdcd10899, 0xa0000005, - 0x019bb59a, 0xb5029cb5, 0x9bb2039e, 0xdcb219bf, 0xda0140fe, 0x00001aa4, 0xa0180090, 0x15a97e09, - 0xbf0fbf00, 0xf4f9a619, 0xe97e070b, 0x15fb0042, 0x05dcd914, 0x99bf0000, 0x8efc30f4, 0xfe00b800, - 0xf9a0014f, 0xc400efcf, 0x1bf404f9, 0x3ea43d09, 0xc5001b7b, 0xe9f604f9, 0xfe010a00, 0x9fbf0149, - 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf80430f4, 0x05dcdf00, 0xffbf0000, 0xfefc30f4, - 0x9fa00149, 0x00900089, 0xf00099ce, 0x0bf40194, 0xf1008f1e, 0x00f9ce00, 0xf71095f0, 0xffb800f9, - 0xce025200, 0x95f000f9, 0x00f9f710, 0xbf0149fe, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, - 0x0430f400, 0xdcdf00f8, 0xbf000005, 0xfc30f4ff, 0xf00149fe, 0x9fa003b4, 0x8903a4f0, 0xb6009400, - 0xabfd02a4, 0x009af705, 0xbf0149fe, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, - 0x30f400f8, 0x05dcdffc, 0x02f90000, 0x49feffbf, 0x04999001, 0x9fa0a0b2, 0x000a747e, 0x01c0008f, - 0xc700f9cf, 0x90b34c99, 0x90b34700, 0x02f8f601, 0x001c403e, 0xc700f9cf, 0x90b34c99, 0x90b30e00, - 0x02f8f601, 0x001c543e, 0x01c20080, 0x7e0000cf, 0xfe000a9b, 0x99900149, 0xd99fbf04, 0x000005dc, - 0x0ab299bf, 0x0bf4f9a6, 0x1caa3e28, 0xc1008900, 0x0090f601, 0x0000f1df, 0x0099b880, 0x9ff70201, - 0x009fcf00, 0x543e9fb2, 0xe97e001c, 0x05fb0042, 0xfc30f404, 0x0005dcdf, 0xbf12f900, 0x0149feff, - 0xb2089990, 0xb29fa0a0, 0x0a747eb1, 0xc0008f00, 0x00f9cf01, 0xb34c99c7, 0xb33e0090, 0xf8f60190, - 0x1cd13e02, 0x00f9cf00, 0xb34c99c7, 0xb30e0090, 0xf8f60190, 0x1ce53e02, 0x0a9b7e00, 0x0149fe00, - 0xbf089990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x1d3a3e30, 0xc1008900, 0x0090f601, 0x010099b8, - 0x0091f600, 0x0000f2df, 0x0099b880, 0x9ff60202, 0x009fcf00, 0xe53e9fb2, 0xe97e001c, 0x15fb0042, - 0x05dcdf04, 0xfebf0000, 0xb8fc30f4, 0x000180aa, 0xb60149fe, 0x9ea009a4, 0xbf00aacf, 0xa6f9bf9e, - 0x070bf4e9, 0x0042e97e, 0xf80430f4, 0x05dcdf00, 0xffbf0000, 0x03010089, 0xb6fc30f4, 0xa9bc09a4, - 0x0149fea0, 0xabf69fa0, 0x0149fe00, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x30f40042, - 0xde00f804, 0x000005dc, 0x30f4efbf, 0x20008afc, 0x0149fe03, 0xaacf9fa0, 0xbf9fbf00, 0xf4f9a6e9, - 0xe97e070b, 0x30f40042, 0xdf00f804, 0x000005dc, 0x30f4ffbf, 0x0149fefc, 0x00899fa0, 0x9af60320, - 0xbd400f00, 0x009ff694, 0xbf0149fe, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, - 0xdcde00f8, 0xbf000005, 0xfc30f4ef, 0x0321008a, 0xa00149fe, 0x00aacf9f, 0xe9bf9fbf, 0x0bf4f9a6, - 0x42e97e07, 0x0430f400, 0xdcdf00f8, 0xbf000005, 0xfc30f4ff, 0xa00149fe, 0x1fa9959f, 0xa4f0c920, - 0x02a0b303, 0x03a0b30c, 0x01a4b308, 0x3ebaa00a, 0xbd001e57, 0xfeb9a094, 0x9fbf0149, 0x0005dcd9, - 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf80430f4, 0x05dcde00, 0xe9bf0000, 0xfefc30f4, 0xf9a0014f, - 0xa0e2a9c7, 0xeaa9c7b9, 0xaae7c9a0, 0xdaa00154, 0xe9bfffbf, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, - 0xdcdf00f8, 0xbf000005, 0xfc30f4ff, 0xa00149fe, 0x01c4b39f, 0x82a9e70e, 0x3ed9a003, 0xe7001ed1, - 0xb30116a9, 0x0f0e0090, 0x11004919, 0xf8009ff7, 0x0149fe02, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, - 0xe97e070b, 0x30f40042, 0xd900f804, 0x000005dc, 0x30f499bf, 0x014ffefc, 0xa9e7f9a0, 0xaac702e2, - 0x06a0b39a, 0x06a6b020, 0xb30f0cf4, 0xb31604a0, 0x3e2505a4, 0xb0001f21, 0x0cf409a6, 0x1f2b3e1a, - 0x0294b600, 0x3e04b9b5, 0x92001f34, 0x94b602af, 0xf9b9bc02, 0xbf0149fe, 0x05dcd99f, 0x99bf0000, - 0x0bf4f9a6, 0x42e97e07, 0x0430f400, 0xdcdf00f8, 0xbf000005, 0xfc30f4ff, 0xa00149fe, 0x1fa9959f, - 0xa4f0c920, 0x02a0b303, 0x03a0b30c, 0x01a4b308, 0x3ebaa00a, 0xbd001f7b, 0xfeb9a094, 0x9fbf0149, - 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf80430f4, 0x05dcde00, 0xe9bf0000, 0xfefc30f4, - 0xf9a0014f, 0xa0a2a9c7, 0xe8a9c7b9, 0xaae7c9a0, 0xdaa00154, 0xe9bfffbf, 0x0bf4f9a6, 0x42e97e07, - 0x0430f400, 0xdcdf00f8, 0xbf000005, 0xfc30f4ff, 0xb60149fe, 0x9fa00ca5, 0x1101c4b3, 0x07ffff89, - 0xa094a9ff, 0x1ffd3ed9, 0xffff8900, 0x94a9ff07, 0x0f0d0bf4, 0x11004919, 0xf8009ff7, 0x0149fe02, - 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x30f40042, 0xd900f804, 0x000005dc, 0x30f499bf, - 0x014ffefc, 0xa9e7f9a0, 0xaac702e2, 0x05a0b39a, 0x05a6b020, 0xb30b0cf4, 0x3e3700a0, 0xb3002064, - 0xb00e06a0, 0x0cf409a6, 0x20573e1e, 0x0294b600, 0x3e04b9b5, 0x9200206e, 0x94b602af, 0xf9b9bc02, - 0x00206e3e, 0x0049190f, 0x009ff711, 0x49fe02f8, 0xd99fbf01, 0x000005dc, 0xf9a699bf, 0x7e070bf4, - 0xf40042e9, 0x00f80430, 0x0005dcdf, 0xf4ffbf00, 0x49fefc30, 0x959fa001, 0xc9201fa9, 0xb303a4f0, - 0xb30c02a0, 0xb30803a0, 0xa00a01a4, 0x20b53eba, 0xa094bd00, 0x0149feb9, 0xdcd99fbf, 0xbf000005, - 0xf4f9a699, 0xe97e070b, 0x30f40042, 0xdf00f804, 0x000005dc, 0x30f4ffbf, 0x0149fefc, 0xa9c79fa0, - 0xc7b9a0a2, 0xc9a0e8a9, 0x0154a9e7, 0xaac7d9a0, 0x00a0b370, 0x49190f0e, 0x9ff71100, 0xfe02f800, - 0x9fbf0149, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf80430f4, 0x05dcdf00, 0xffbf0000, - 0xfefc30f4, 0xa5b60149, 0xb39fa00c, 0x891101c4, 0xff07ffff, 0xd9a094a9, 0x0021503e, 0x07ffff89, - 0xf494a9ff, 0x190f0d0b, 0xf7110049, 0x02f8009f, 0xbf0149fe, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, - 0x42e97e07, 0x0430f400, 0xdcd900f8, 0xbf000005, 0xfc30f499, 0xa0014ffe, 0xe2a9e7f9, 0x9aaac702, - 0x2005a0b3, 0xf405a6b0, 0xa0b30b0c, 0xb73e3700, 0xa0b30021, 0xa6b00e06, 0x1e0cf409, 0x0021aa3e, - 0xb50294b6, 0xc13e04b9, 0xaf920021, 0x0294b602, 0x3ef9b9bc, 0x0f0021c1, 0x11004919, 0xf8009ff7, - 0x0149fe02, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x30f40042, 0xdf00f804, 0x000005dc, - 0x30f4ffbf, 0x0149fefc, 0xa9959fa0, 0xf0c9201f, 0xa0b303a4, 0xa0b30c02, 0xa4b30803, 0xbaa00a01, - 0x0022083e, 0xb9a094bd, 0xbf0149fe, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, - 0xdcde00f8, 0xbf000005, 0xfc30f4e9, 0xa0014ffe, 0xa2a9c7f9, 0xa9c7b9a0, 0xe7c9a0e8, 0xa00154aa, - 0xbfffbfda, 0xf4f9a6e9, 0xe97e070b, 0x30f40042, 0xdf00f804, 0x000005dc, 0x30f4ffbf, 0x0149fefc, - 0xc0b39fa0, 0xc0b31001, 0xc0b30c0c, 0xc4b3080d, 0xa9e70a14, 0xd9a0024c, 0xbf0149fe, 0x05dcd99f, - 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, 0xdcd900f8, 0xbf000005, 0xfc30f499, 0xa0014ffe, - 0xe2a9e7f9, 0x9aaac702, 0x2e06a0b3, 0xf406a6b0, 0xa0b30f0c, 0xa4b31604, 0xd63e3305, 0xa6b00022, - 0x280cf409, 0x0022e03e, 0x0049190f, 0x009ff711, 0xe93e02f8, 0x94b60022, 0x04b9b502, 0x0022e93e, - 0xb602af92, 0xb9bc0294, 0x0149fef9, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x30f40042, - 0xf400f804, 0x82f9d430, 0x301590b4, 0xc1b027e1, 0x0ad1b00b, 0x94b6f4bd, 0x0c91b002, 0x900149fe, - 0x9fa04499, 0x20079990, 0x0b99929f, 0x95b29fa0, 0xa0049992, 0x9297b29f, 0x9fa00499, 0x0005dcdf, - 0x90ffbf00, 0x4efe1499, 0xa0a6b201, 0x34ee909f, 0xb4b20209, 0x84bde9a0, 0x14bd34bd, 0x0024473e, - 0x227e6ab2, 0x49bf001c, 0x4bfea2b2, 0x014cfe01, 0x9044bb90, 0x95f94bcc, 0xb31100b4, 0x008e0209, - 0x9e0309b3, 0x010db300, 0x499800a8, 0xb27cb201, 0xfe5bb22a, 0xdd90014d, 0x3295f938, 0x0be0b40c, - 0xfd3ed4bd, 0x5fbf0023, 0xf9a6e9bf, 0x34381bf4, 0xe89827b0, 0x987fbf01, 0xb03302e9, 0xb0b40a00, - 0x90b9bc0c, 0x1bf4f9a6, 0x1344df1e, 0xf9180000, 0x0094330c, 0x90f1b206, 0x24d920ff, 0xa6000028, - 0xed1bf4f9, 0x130010b3, 0xbf0c1c35, 0x0118b55b, 0x79bf1ba0, 0x900219b5, 0xee9001dd, 0x0ab0b40c, - 0x08f4dba6, 0x242d3ea4, 0x02499800, 0x4dfe5cbf, 0xb22ab201, 0x34dd901b, 0x2d3e95f9, 0x10b30024, - 0x49980f00, 0xb25cbf03, 0xf91bb22a, 0x4b903495, 0x11009433, 0x14bdff09, 0xa00e91b0, 0xa094bd79, - 0x01339059, 0xb4046690, 0x39a60d90, 0xff1408f5, 0x900149fe, 0x9fbf4c99, 0x0005dcd9, 0xa699bf00, - 0x070bf4f9, 0x0042e97e, 0xf42c85fb, 0xdcd9fc30, 0xf9000005, 0xf499bf62, 0x24d0fc30, 0xfe000028, - 0xff90014f, 0x3ff9a020, 0xb2a5b209, 0xb2c2b2b4, 0x009d33d3, 0xb4bd0111, 0xda14e44c, 0x00001344, - 0x000b947e, 0x06b294bd, 0x8a0091b0, 0xdb02c000, 0x000001fc, 0x00020cdc, 0x3d1a0d00, 0x1344d0e4, - 0x037e0000, 0x14bd0023, 0x94b309bf, 0x09981f13, 0x040a9802, 0x0001ccdb, 0x0344dc00, 0x91b00000, - 0x0e080d00, 0x23037e01, 0xb30dbf00, 0x983504d4, 0x0998040a, 0x01dcdb02, 0xa4dc0000, 0x0e000003, - 0x0091b001, 0x0023037e, 0xb0040a98, 0xdcdb0011, 0xdc000001, 0x000003d4, 0xe43d090d, 0x0023037e, - 0x94b309bf, 0x0a981c05, 0x0011b004, 0x0001dcdb, 0x0440dc00, 0x020d0000, 0x037ee43d, 0x09bf0023, - 0x371594b3, 0x98040a98, 0xecdb0209, 0xdc000001, 0x00000458, 0x010e040d, 0x7e0091b0, 0x98002303, - 0x11b0040a, 0x01ecdb00, 0x88dc0000, 0x0d000004, 0x7ee43d04, 0xbf002303, 0x1694b309, 0x040a981c, - 0xdb0011b0, 0x000001ec, 0x0004b8dc, 0x3d020d00, 0x23037ee4, 0x20009000, 0x1bf506a6, 0x0109ff2e, - 0x3d940920, 0x1358d902, 0x48df0000, 0xbc000013, 0xff0ad0d9, 0x002828de, 0xa6f9bf00, 0x2f1bf459, - 0xa601f998, 0x271bf449, 0x3308f918, 0xb3210194, 0xb0140120, 0x08f40126, 0xb3ff0a0d, 0x3e110224, - 0x980025ea, 0xec3e03fa, 0xdabf0025, 0x9020ff90, 0xfea620dd, 0x09c51bf4, 0xf4a9a6ff, 0x190f0d1b, - 0xf7110049, 0x02f8009f, 0x900149fe, 0x9fbf2099, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, - 0xfb0430f4, 0x30f40465, 0xd112f9f4, 0x000005dc, 0x40fe19bf, 0x10009001, 0x09a0caa0, 0xcbb594bd, - 0x02c9b501, 0x00130cd9, 0xfe9fbf00, 0x99900149, 0x019bb508, 0xb5b69aa0, 0xd8fab811, 0xb17e0002, - 0x0fbf001c, 0xf9a619bf, 0x7e070bf4, 0xfb0042e9, 0x30f40c15, 0xd252f9e8, 0x000005dc, 0x40fe29bf, - 0x18009001, 0x0cb50ba0, 0xb2e5b201, 0xfea3b2d4, 0x11900141, 0x7e19a02c, 0x7e000e06, 0x98000a74, - 0x0abf010b, 0x900140fe, 0x0cb22000, 0x0026267e, 0x4cb20bb2, 0x3ab25db2, 0x000dcc7e, 0x9b7ea032, - 0xdd7e000a, 0x1fbf000d, 0x0a3229bf, 0x0bf4f9a6, 0x42e97e07, 0x1855fb00, 0xf9e830f4, 0x05dcd252, - 0x29bf0000, 0x900140fe, 0x0ba01800, 0xb2010cb5, 0xb2d4b2e5, 0x0141fea3, 0xa02c1190, 0x0e067e19, - 0x0a747e00, 0x010b9800, 0x40fe0abf, 0x20009001, 0x267e0cb2, 0x0bb20026, 0x5db24cb2, 0xb97e3ab2, - 0xa032000d, 0x000a9b7e, 0x000ddd7e, 0x29bf1fbf, 0xf9a60a32, 0x7e070bf4, 0xfb0042e9, 0xdcd91855, - 0xbf000005, 0xfc30f499, 0x0a014ffe, 0x7ef9a004, 0x330042f5, 0x8a2e00a0, 0x7e120050, 0xf0001c22, - 0x0bf401a4, 0x00588a1f, 0x1c227e12, 0x00a0b300, 0x07a9c416, 0x0a0d1bf4, 0x42f57e02, 0x00a43300, - 0xfe02f806, 0x9fbf0149, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf80430f4, 0x130cd900, - 0x30f40000, 0xd112f9fc, 0x000005dc, 0x19bf9abf, 0xdb0140fe, 0x40000000, 0xb8080090, 0x0008b4aa, - 0xfa7e09a0, 0x0fbf009e, 0xf9a619bf, 0x7e070bf4, 0xfb0042e9, 0x0cd90415, 0xf4000013, 0x12f9fc30, - 0x0005dcd1, 0xbf9abf00, 0x0140fe19, 0x000000db, 0x08009040, 0x08c4aab8, 0x7e09a000, 0xbf009efa, - 0xa619bf0f, 0x070bf4f9, 0x0042e97e, 0xd90415fb, 0x0000130c, 0xf9fc30f4, 0x05dcd112, 0x9abf0000, - 0x40fe19bf, 0x0000db01, 0x00908000, 0xc4aab808, 0x09a00008, 0x009efa7e, 0x19bf0fbf, 0x0bf4f9a6, - 0x42e97e07, 0x0415fb00, 0x0005dcdf, 0xf4ffbf00, 0x49fefc30, 0xd99fa001, 0x0000130c, 0x008f99bf, - 0x9a9001c0, 0x00f9cf60, 0xb34c99c7, 0xb34a0090, 0xf8f60190, 0x28653e02, 0x00f9cf00, 0xb34c99c7, - 0xb30e0090, 0xf8f60190, 0x28793e02, 0xc2008b00, 0x00bbcf01, 0x040018d9, 0x05b9fd04, 0x009efa7e, - 0xbf0149fe, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x28d23e28, 0xc1008900, 0x009af601, 0x0000f1df, - 0x0099b880, 0x9ff70201, 0x009fcf00, 0x793e9fb2, 0xe97e0028, 0x30f40042, 0xf400f804, 0x0cd9fc30, - 0xf9000013, 0xb299bf22, 0x05dcd1a2, 0x40fe0000, 0xc89ab801, 0x19bf0008, 0xa00c0090, 0x1c227e09, - 0xbf0ebf00, 0xbb01091f, 0xa9fd0492, 0x0bacf004, 0x0bf4efa6, 0x42e97e07, 0x0425fb00, 0xd9fc30f4, - 0x000005dc, 0x99bf02f9, 0x90014ffe, 0xf9a004ff, 0x00130cd9, 0x8f9ebf00, 0xcf01c000, 0x99c700f9, - 0x0099b34c, 0x90b301d2, 0x02f8f501, 0x00293b3e, 0xc700f9cf, 0x99b34c99, 0xb301ae00, 0xf8f50190, - 0x29503e02, 0x00f9cf00, 0xb34c99c7, 0x01770099, 0xf50190b3, 0x653e02f8, 0xf9cf0029, 0x4c99c700, - 0x480099b3, 0x0190b301, 0x3e02f8f5, 0x7e00297a, 0xd90090c0, 0x00800000, 0xf49409ff, 0x317e070b, - 0x0cd9002d, 0xbf000013, 0xc0008f9e, 0x00f9cf01, 0xb34c99c7, 0x00f30099, 0xf50190b3, 0xad3e02f8, - 0xf9cf0029, 0x4c99c700, 0xcf0099b3, 0x0190b300, 0x3e02f8f5, 0xcf0029c2, 0x99c700f9, 0x0099b34c, - 0x90b30098, 0x02f8f501, 0x0029d73e, 0xc700f9cf, 0x90b34c99, 0x90b36e00, 0x02f8f601, 0x0029ec3e, - 0x007bff7e, 0x000000d9, 0x9409ff40, 0x7e070bf4, 0xd9007e13, 0x02000000, 0x000000df, 0xb409ff04, - 0xf4940fff, 0xbffd060b, 0x0000df05, 0x0fff0800, 0x060bf494, 0xd905bffd, 0x0000130c, 0xaab89abf, - 0x7e0008c4, 0xfe009efa, 0x99900149, 0xd99fbf04, 0x000005dc, 0xf9a699bf, 0x00e10bf5, 0x002b353e, - 0x01c20089, 0xff0099cf, 0x0995049d, 0x0194b31f, 0x2a003e97, 0xa4efb800, 0x00890008, 0x9ff601c1, - 0x00f1df00, 0x99b88000, 0xf7020100, 0x9fcf009f, 0x3e9fb200, 0x890029ec, 0xcf01c200, 0x008f009d, - 0xd73e01c0, 0xefb80029, 0x89000890, 0xf601c100, 0xf1df009f, 0xb8800000, 0x02010099, 0xcf009ff7, - 0x9fb2009f, 0x0029c23e, 0x01c20089, 0xff0099cf, 0x00d9049d, 0xff010000, 0x0bf59409, 0x8f3efeb9, - 0xefb80029, 0x89000898, 0xf601c100, 0xf1df009f, 0xb8800000, 0x02010099, 0xcf009ff7, 0x9fb2009f, - 0x00297a3e, 0x01c20089, 0x8f009dcf, 0x3e01c000, 0xb8002965, 0x000884ef, 0x01c10089, 0xdf009ff6, - 0x800000f1, 0x010099b8, 0x009ff702, 0xb2009fcf, 0x29503e9f, 0x42e97e00, 0x0405fb00, 0x0005dcdf, - 0xf4ffbf00, 0x49fefc30, 0x8f9fa001, 0xcf01c000, 0x99c700f9, 0x0090b34c, 0x0190b341, 0x3e02f8f6, - 0xcf002b4f, 0x99c700f9, 0x0090b34c, 0x0190b30e, 0x3e02f8f6, 0x8a002b63, 0xcf01c200, 0x49fe00aa, - 0xd99fbf01, 0x000005dc, 0xaac799bf, 0xf4f9a601, 0xb83e2d0b, 0xafb8002b, 0x89000380, 0xf601c100, - 0xf1df009f, 0xb8800000, 0x02010099, 0xcf009ff7, 0x9fb2009f, 0x002b633e, 0x0042e97e, 0xf80430f4, - 0xfc30f400, 0x0005dcd9, 0xbf82f900, 0x014ffe99, 0xa024ff90, 0x00a933f9, 0x04bd0087, 0x002838d7, - 0x8314bd00, 0x8601c000, 0xd501c100, 0x800000f1, 0x01c20084, 0x7b987abf, 0x7e0cb201, 0xf0004212, - 0x0bf401a4, 0xbd0bb248, 0x0ad4bdc4, 0x246b7e08, 0x7ea2b200, 0x33002b3c, 0xb83300a4, 0x0004002a, - 0xc70039cf, 0x99b34c99, 0xb300dc00, 0xf8f50190, 0x2c203e02, 0x0039cf00, 0xb34c99c7, 0x00b90099, - 0xf50190b3, 0x353e02f8, 0x0090002c, 0x00119101, 0xa42404b3, 0xa00014b3, 0x002cda3e, 0x38d804bd, - 0xbd000028, 0xc0008314, 0xc1008701, 0x00f1d601, 0x00858000, 0xfe0401c2, 0x8b988abf, 0x7e0cb201, - 0xf0004212, 0x0bf401a4, 0xbd0bb246, 0x0ad4bdc4, 0x246b7e08, 0x7ea2b200, 0x33002b3c, 0xb83100a4, - 0x0004002a, 0xc70039cf, 0x90b34c99, 0x90b37300, 0x02f8f601, 0x002ca43e, 0xc70039cf, 0x90b34c99, - 0x90b35100, 0x02f8f601, 0x002cb83e, 0x91010090, 0x04b30011, 0x14b3a624, 0x49fea200, 0x24999001, - 0xdcd99fbf, 0xbf000005, 0xa6a43d99, 0x410bf4f9, 0x002d2a3e, 0xf0004bcf, 0x6f7e01b5, 0x4a3e0047, - 0x6af6002c, 0x0035f700, 0x3e0039cf, 0xcf002c35, 0xb4fd005b, 0x476f7e04, 0x2ccc3e00, 0x007af600, - 0xcf0036f7, 0xb83e0039, 0xe97e002c, 0x85fb0042, 0xfc30f404, 0x0005dcdf, 0xbf02f900, 0x0149feff, - 0xa0049990, 0xc0008f9f, 0x00f9cf01, 0xb34c99c7, 0xb34f0090, 0xf8f60190, 0x2d493e02, 0x00f9cf00, - 0xb34c99c7, 0xb32a0090, 0xf8f60190, 0x2d5d3e02, 0x2dda7e00, 0x3009c400, 0x7e070bf4, 0xc4002e5a, - 0x0bf44009, 0x2e927e3d, 0x2dbf3e00, 0xc2008900, 0x0090cf01, 0xf40109c4, 0x713ede0b, 0x488f002d, - 0x008901b0, 0x9ff601c1, 0x00f1df00, 0x99b88000, 0xf7020100, 0x9fcf009f, 0x3e9fb200, 0xfe002d5d, - 0x99900149, 0xd99fbf04, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb0042e9, 0xdcdf0405, 0xbf000005, - 0xfc30f4ff, 0xa00149fe, 0xc0008f9f, 0x00f9cf01, 0xb34c99c7, 0xb3220090, 0xf8f60190, 0x2ded3e02, - 0x00f9cf00, 0xb34c99c7, 0xb3390090, 0xf8f60190, 0x2e013e02, 0xad248f00, 0xc1008901, 0x009ff601, - 0x99b8f4bd, 0xf6000100, 0xf2df009f, 0xb8800000, 0x02020099, 0xcf009ff6, 0x9fb2009f, 0x002e013e, - 0xbf0149fe, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, 0x30f400f8, 0xd112f9fc, - 0x000005dc, 0x048a19bf, 0xb4bd01ad, 0x900140fe, 0x09a00800, 0x0047e97e, 0x01ad848a, 0xe97eb4bd, - 0x0fbf0047, 0xf9a619bf, 0x7e070bf4, 0xfb0042e9, 0xdcdf0415, 0xbf000005, 0xfc30f4ff, 0xa00149fe, - 0xc0008f9f, 0x00f9cf01, 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0xda0140fe, 0x0000194b, 0xa0180090, 0x15a97e09, 0xbf0fbf00, + 0xf4f9a619, 0x317e070b, 0x15fb003a, 0xb8008e14, 0x00efcf00, 0xf404f9c4, 0xa43d071b, 0xf9c500f8, + 0x00e9f604, 0x00f8010a, 0x00900089, 0xf00099ce, 0x0bf40194, 0xf1008f1e, 0x00f9ce00, 0xf71095f0, + 0xffb800f9, 0xce025200, 0x95f000f9, 0x00f9f710, 0xb4f000f8, 0x03a4f003, 0x00940089, 0xfd02a4b6, + 0x9af705ab, 0xf900f800, 0x7ea0b202, 0x8f000a74, 0xcf01c000, 0x99c700f9, 0x0090b34c, 0x0190b331, + 0x3e02f8f6, 0xcf001a33, 0x99c700f9, 0x0090b34c, 0x0190b30e, 0x3e02f8f6, 0x80001a47, 0xcf01c200, + 0x9b7e0000, 0x0ab2000a, 0x008901fb, 0x90f601c1, 0x00f1df00, 0x99b88000, 0xf7020100, 0x9fcf009f, + 0x3e9fb200, 0xf9001a47, 0xb2a0b212, 0x0a747eb1, 0xc0008f00, 0x00f9cf01, 0xb34c99c7, 0xb3280090, + 0xf8f60190, 0x1a953e02, 0x00f9cf00, 0xb34c99c7, 0xb30e0090, 0xf8f60190, 0x1aa93e02, 0x0a9b7e00, + 0x8911fb00, 0xf601c100, 0x99b80090, 0xf6000100, 0xf2df0091, 0xb8800000, 0x02020099, 0xcf009ff6, + 0x9fb2009f, 0x001aa93e, 0x0180aab8, 0x09a4b600, 0xf800aacf, 0x01008900, 0x09a4b603, 0xf6a0a9bc, + 0x00f800ab, 0x0320008a, 0xf800aacf, 0x20008900, 0x009af603, 0x94bd400f, 0xf8009ff6, 0x21008a00, + 0x00aacf03, 0xa99500f8, 0xf0c9201f, 0xa0b303a4, 0xa0b30c02, 0xa4b30803, 0xbaa00801, 0x94bd00f8, + 0x00f8b9a0, 0xa0e2a9c7, 0xeaa9c7b9, 0xaae7c9a0, 0xdaa00154, 0xc4b300f8, 0xa9e70c01, 0xd9a00382, + 0xa9e700f8, 0x90b30116, 0x190f0e00, 0xf7110049, 0x02f8009f, 0xa9e700f8, 0xaac702e2, 0x06a0b39a, + 0x06a6b020, 0xb30f0cf4, 0xb31604a0, 0x3e2305a4, 0xb0001b9d, 0x0cf409a6, 0x1ba53e18, 0x0294b600, + 0xf804b9b5, 0x02af9200, 0xbc0294b6, 0x00f8f9b9, 0x201fa995, 0x03a4f0c9, 0x0c02a0b3, 0x0803a0b3, + 0x0801a4b3, 0x00f8baa0, 0xb9a094bd, 0xa9c700f8, 0xc7b9a0a2, 0xc9a0e8a9, 0x0154aae7, 0x00f8daa0, + 0xb30ca5b6, 0x890f01c4, 0xff07ffff, 0xd9a094a9, 0xff8900f8, 0xa9ff07ff, 0x0d0bf494, 0x0049190f, + 0x009ff711, 0x00f802f8, 0x02e2a9e7, 0xb39aaac7, 0xb03005a0, 0x0cf405a6, 0x00a0b30f, 0x04a4b343, + 0x1c333e35, 0x06a0b300, 0x09a6b01a, 0x3e260cf4, 0x0f001c47, 0x11004919, 0xf8009ff7, 0xb600f802, + 0xb9b50294, 0x9200f804, 0x94b602af, 0xf9b9bc02, 0x190f00f8, 0xf7110049, 0x02f8009f, 0xa99500f8, + 0xf0c9201f, 0xa0b303a4, 0xa0b30c02, 0xa4b30803, 0xbaa00801, 0x94bd00f8, 0x00f8b9a0, 0xa0a2a9c7, + 0xe8a9c7b9, 0xa9e7c9a0, 0xd9a00154, 0xb370aac7, 0x0f0e00a0, 0x11004919, 0xf8009ff7, 0xb600f802, + 0xc4b30ca5, 0xff890f01, 0xa9ff07ff, 0xf8d9a094, 0xffff8900, 0x94a9ff07, 0x0f0d0bf4, 0x11004919, + 0xf8009ff7, 0xe700f802, 0xc702e2a9, 0xa0b39aaa, 0xa6b03005, 0x0f0cf405, 0x4300a0b3, 0x3504a4b3, + 0x001cf23e, 0x1a06a0b3, 0xf409a6b0, 0x063e260c, 0x190f001d, 0xf7110049, 0x02f8009f, 0x94b600f8, + 0x04b9b502, 0xaf9200f8, 0x0294b602, 0xf8f9b9bc, 0x49190f00, 0x9ff71100, 0xf802f800, 0x1fa99500, + 0xa4f0c920, 0x02a0b303, 0x03a0b30c, 0x01a4b308, 0xf8baa008, 0xa094bd00, 0xc700f8b9, 0xb9a0a2a9, + 0xa0e8a9c7, 0x54aae7c9, 0xf8daa001, 0x01c0b300, 0x0cc0b310, 0x0dc0b30c, 0x14c4b308, 0x4ca9e70a, + 0xf8d9a002, 0xe2a9e700, 0x9aaac702, 0x2c06a0b3, 0xf406a6b0, 0xa0b30f0c, 0xa4b31604, 0x983e2f05, + 0xa6b0001d, 0x240cf409, 0x001da03e, 0x0049190f, 0x009ff711, 0x00f802f8, 0xb50294b6, 0x00f804b9, + 0xb602af92, 0xb9bc0294, 0xf400f8f9, 0x82f9d430, 0x301590b4, 0xc1b027e1, 0x0ad1b00b, 0x94b6f4bd, + 0x0c91b002, 0x900149fe, 0x9fa04499, 0x20079990, 0x0b99929f, 0x95b29fa0, 0xa0049992, 0x9297b29f, + 0x9fa00499, 0x0005dcdf, 0x90ffbf00, 0x4efe1499, 0xa0a6b201, 0x34ee909f, 0xb4b20209, 0x14bde9a0, + 0x34bd84bd, 0x001eef3e, 0x277e6ab2, 0x49bf001a, 0x4bfea2b2, 0x014cfe01, 0x9044bb90, 0x95f94bcc, + 0xb31100b4, 0x008e0209, 0x9e0309b3, 0x010db300, 0x499800a8, 0xb27cb201, 0xfe5bb22a, 0xdd90014d, + 0x3295f938, 0x0be0b40c, 0xa53ed4bd, 0x5fbf001e, 0xf9a6e9bf, 0x34381bf4, 0xe89827b0, 0x987fbf01, + 0xb03302e9, 0xb0b40a00, 0x90b9bc0c, 0x1bf4f9a6, 0x1444df1e, 0xf9180000, 0x0094330c, 0x90f1b206, + 0x24d920ff, 0xa6000029, 0xed1bf4f9, 0x130010b3, 0xbf0c1c35, 0x0118b55b, 0x79bf1ba0, 0x900219b5, + 0xee9001dd, 0x0ab0b40c, 0x08f4dba6, 0x1ed53ea4, 0x02499800, 0x4dfe5cbf, 0xb22ab201, 0x34dd901b, + 0xd53e95f9, 0x10b3001e, 0x49980f00, 0xb25cbf03, 0xf91bb22a, 0x4b903495, 0x11009433, 0x14bdff09, + 0xa00e91b0, 0xa094bd79, 0x01339059, 0xb4046690, 0x39a60d90, 0xff1408f5, 0x900149fe, 0x9fbf4c99, + 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf92c85fb, 0x2924d062, 0x093f0000, 0xb2fc30f4, + 0xb2b4b2a5, 0x33d3b2c2, 0x0111009d, 0xe44cb4bd, 0x1444da14, 0x947e0000, 0x94bd000b, 0x91b006b2, + 0xc0008a00, 0x01fcdb02, 0x0cdc0000, 0x0d000002, 0xd0e43d1a, 0x00001444, 0x001dab7e, 0x09bf14bd, + 0x1f1394b3, 0x98020998, 0xccdb040a, 0xdc000001, 0x00000344, 0x0d0091b0, 0x7e010e08, 0xbf001dab, + 0x04d4b30d, 0x040a9835, 0xdb020998, 0x000001dc, 0x0003a4dc, 0xb0010e00, 0xab7e0091, 0x0a98001d, + 0x0011b004, 0x0001dcdb, 0x03d4dc00, 0x090d0000, 0xab7ee43d, 0x09bf001d, 0x1c0594b3, 0xb0040a98, + 0xdcdb0011, 0xdc000001, 0x00000440, 0xe43d020d, 0x001dab7e, 0x94b309bf, 0x0a983715, 0x02099804, + 0x0001ecdb, 0x0458dc00, 0x040d0000, 0x91b0010e, 0x1dab7e00, 0x040a9800, 0xdb0011b0, 0x000001ec, + 0x000488dc, 0x3d040d00, 0x1dab7ee4, 0xb309bf00, 0x981c1694, 0x11b0040a, 0x01ecdb00, 0xb8dc0000, + 0x0d000004, 0x7ee43d02, 0x90001dab, 0x06a62000, 0xff2e1bf5, 0x09200109, 0xd9023d94, 0x00001458, + 0x001448df, 0xd0d9bc00, 0x28deff0a, 0xbf000029, 0xf459a6f9, 0xf9982f1b, 0xf449a601, 0xf918271b, + 0x01943308, 0x0120b321, 0x0126b014, 0x0a0d08f4, 0x0224b3ff, 0x20803e11, 0x03fa9800, 0x0020823e, + 0xff90dabf, 0x20dd9020, 0x1bf4fea6, 0xa6ff09c5, 0x0d1bf4a9, 0x0049190f, 0x009ff711, 0x30f402f8, + 0xbd61fb04, 0xb5caa094, 0xc9b501cb, 0x140cd902, 0x9fbf0000, 0xfef830f4, 0x9bb50149, 0xb69aa001, + 0xfab811b5, 0x7e0002d8, 0xf4001a87, 0x00f80830, 0xf9e830f4, 0x05dcd252, 0x29bf0000, 0x900140fe, + 0x0ba01800, 0xb2010cb5, 0xb2d4b2e5, 0x0141fea3, 0xa02c1190, 0x0e067e19, 0x0a747e00, 0x010b9800, + 0x40fe0abf, 0x20009001, 0xa37e0cb2, 0x0bb20020, 0x5db24cb2, 0xcc7e3ab2, 0xa032000d, 0x000a9b7e, + 0x000ddd7e, 0x29bf1fbf, 0xf9a60a32, 0x7e070bf4, 0xfb003a31, 0x30f41855, 0xd252f9e8, 0x000005dc, + 0x40fe29bf, 0x18009001, 0x0cb50ba0, 0xb2e5b201, 0xfea3b2d4, 0x11900141, 0x7e19a02c, 0x7e000e06, + 0x98000a74, 0x0abf010b, 0x900140fe, 0x0cb22000, 0x0020a37e, 0x4cb20bb2, 0x3ab25db2, 0x000db97e, + 0x9b7ea032, 0xdd7e000a, 0x1fbf000d, 0x0a3229bf, 0x0bf4f9a6, 0x3a317e07, 0x1855fb00, 0x3d7e040a, + 0xa033003a, 0x508a2400, 0x277e1200, 0xa4f0001a, 0x150bf401, 0x1200588a, 0x001a277e, 0x1a00a0b3, + 0xf407a9c4, 0x02f8070b, 0x020a00f8, 0x003a3d7e, 0x0600a433, 0x00f802f8, 0x00140cd9, 0xdb9abf00, + 0x40000000, 0x08b4aab8, 0x83ed7e00, 0xd900f800, 0x0000140c, 0x00db9abf, 0xb8400000, 0x0008c4aa, + 0x0083ed7e, 0x0cd900f8, 0xbf000014, 0x0000db9a, 0xaab88000, 0x7e0008c4, 0xf80083ed, 0x140cd900, + 0x99bf0000, 0x01c0008f, 0xcf609a90, 0x99c700f9, 0x0090b34c, 0x0190b337, 0x3e02f8f6, 0xcf00222b, + 0x99c700f9, 0x0090b34c, 0x0190b30e, 0x3e02f8f6, 0x8b00223f, 0xcf01c200, 0x18d900bb, 0xfd040400, + 0xed7e05b9, 0x00f80083, 0x01c10089, 0xdf009af6, 0x800000f1, 0x010099b8, 0x009ff702, 0xb2009fcf, + 0x223f3e9f, 0xd902f900, 0x0000140c, 0xa0b299bf, 0x08c89ab8, 0x1a277e00, 0xbb010900, 0xa9fd0490, + 0x0bacf004, 0x02f901fb, 0x00140cd9, 0x8f9ebf00, 0xcf01c000, 0x99c700f9, 0x0099b34c, 0x90b301bb, + 0x02f8f501, 0x0022b33e, 0xc700f9cf, 0x99b34c99, 0xb3019700, 0xf8f50190, 0x22c83e02, 0x00f9cf00, + 0xb34c99c7, 0x01600099, 0xf50190b3, 0xdd3e02f8, 0xf9cf0022, 0x4c99c700, 0x310099b3, 0x0190b301, + 0x3e02f8f5, 0x7e0022f2, 0xd9007624, 0x00800000, 0xf49409ff, 0x317e070b, 0x0cd90026, 0xbf000014, + 0xc0008f9e, 0x00f9cf01, 0xb34c99c7, 0x00dc0099, 0xf50190b3, 0x253e02f8, 0xf9cf0023, 0x4c99c700, + 0xb80099b3, 0x0190b300, 0x3e02f8f5, 0xcf00233a, 0x99c700f9, 0x0099b34c, 0x90b30081, 0x02f8f501, + 0x00234f3e, 0xc700f9cf, 0x90b34c99, 0x90b35700, 0x02f8f601, 0x0023643e, 0x0065f57e, 0x000000d9, + 0x9409ff40, 0x7e070bf4, 0xd90067e7, 0x02000000, 0x000000df, 0xb409ff04, 0xf4940fff, 0xbffd060b, + 0x0000df05, 0x0fff0800, 0x060bf494, 0xd905bffd, 0x0000140c, 0xaab89abf, 0x7e0008c4, 0xfb0083ed, + 0xc2008901, 0x0099cf01, 0x95049dff, 0x94b31f09, 0x783eae01, 0xefb80023, 0x890008a4, 0xf601c100, + 0xf1df009f, 0xb8800000, 0x02010099, 0xcf009ff7, 0x9fb2009f, 0x0023643e, 0x01c20089, 0x8f009dcf, + 0x3e01c000, 0xb800234f, 0x000890ef, 0x01c10089, 0xdf009ff6, 0x800000f1, 0x010099b8, 0x009ff702, + 0xb2009fcf, 0x233a3e9f, 0xc2008900, 0x0099cf01, 0xd9049dff, 0x01000000, 0xf59409ff, 0x3efed00b, + 0xb8002307, 0x000898ef, 0x01c10089, 0xdf009ff6, 0x800000f1, 0x010099b8, 0x009ff702, 0xb2009fcf, + 0x22f23e9f, 0xc2008900, 0x009dcf01, 0x01c0008f, 0x0022dd3e, 0x0884efb8, 0xc1008900, 0x009ff601, + 0x0000f1df, 0x0099b880, 0x9ff70201, 0x009fcf00, 0xc83e9fb2, 0x008f0022, 0xf9cf01c0, 0x4c99c700, + 0x2e0090b3, 0xf60190b3, 0x9a3e02f8, 0xf9cf0024, 0x4c99c700, 0x0e0090b3, 0xf60190b3, 0xae3e02f8, + 0x008a0024, 0xaacf01c2, 0x01aac700, 0xafb800f8, 0x89000380, 0xf601c100, 0xf1df009f, 0xb8800000, + 0x02010099, 0xcf009ff7, 0x9fb2009f, 0x0024ae3e, 0xa93382f9, 0xbd008700, 0x2938d704, 0x14bd0000, + 0x01c00083, 0x01c10086, 0x0000f1d5, 0xc2008480, 0x987abf01, 0x0cb2017b, 0x0039797e, 0xf401a4f0, + 0x0bb2480b, 0xd4bdc4bd, 0x137e080a, 0xa2b2001f, 0x0024967e, 0x3300a433, 0x04002ab8, 0x0039cf00, + 0xb34c99c7, 0x00c60099, 0xf50190b3, 0x3d3e02f8, 0x39cf0025, 0x4c99c700, 0xa30099b3, 0x0190b300, + 0x3e02f8f5, 0x90002552, 0x11910100, 0x2404b300, 0x0014b3a4, 0x25f73ea0, 0xd804bd00, 0x00002938, + 0x008314bd, 0x008701c0, 0xf1d601c1, 0x85800000, 0x0401c200, 0x988abffe, 0x0cb2018b, 0x0039797e, + 0xf401a4f0, 0x0bb2460b, 0xd4bdc4bd, 0x137e080a, 0xa2b2001f, 0x0024967e, 0x3100a433, 0x04002ab8, + 0x0039cf00, 0xb34c99c7, 0xb35d0090, 0xf8f60190, 0x25c13e02, 0x0039cf00, 0xb34c99c7, 0xb33b0090, + 0xf8f60190, 0x25d53e02, 0x01009000, 0xb3001191, 0xb3a62404, 0x3da20014, 0xcf81fba4, 0xb5f0004b, + 0x3cfd7e01, 0x25673e00, 0x006af600, 0xcf0035f7, 0x523e0039, 0x5bcf0025, 0x04b4fd00, 0x003cfd7e, + 0x0025e93e, 0xf7007af6, 0x39cf0036, 0x25d53e00, 0x8f02f900, 0xcf01c000, 0x99c700f9, 0x0090b34c, + 0x0190b34f, 0x3e02f8f6, 0xcf002637, 0x99c700f9, 0x0090b34c, 0x0190b32a, 0x3e02f8f6, 0x7e00264b, + 0xc40026af, 0x0bf43009, 0x27087e07, 0x4009c400, 0x7e3d0bf4, 0x3e00271e, 0x890026ad, 0xcf01c200, + 0x09c40090, 0xde0bf401, 0x00265f3e, 0x01b0488f, 0x01c10089, 0xdf009ff6, 0x800000f1, 0x010099b8, + 0x009ff702, 0xb2009fcf, 0x264b3e9f, 0x8f01fb00, 0xcf01c000, 0x99c700f9, 0x0090b34c, 0x0190b322, + 0x3e02f8f6, 0xcf0026b3, 0x99c700f9, 0x0090b34c, 0x0190b339, 0x3e02f8f6, 0x8f0026c7, 0x8901ad24, + 0xf601c100, 0xf4bd009f, 0x010099b8, 0x009ff600, 0x0000f2df, 0x0099b880, 0x9ff60202, 0x009fcf00, + 0xc73e9fb2, 0x00f80026, 0x01ad048a, 0x507eb4bd, 0x848a003d, 0xb4bd01ad, 0x003d507e, 0x008f00f8, + 0xf9cf01c0, 0x4c99c700, 0x220090b3, 0xf60190b3, 0x223e02f8, 0xf9cf0027, 0x4c99c700, 0x390090b3, + 0xf60190b3, 0x363e02f8, 0xa48f0027, 0x008901ad, 0x9ff601c1, 0xb8f4bd00, 0x00010099, 0xdf009ff6, + 0x800000f2, 0x020099b8, 0x009ff602, 0xb2009fcf, 0x27363e9f, 0xe400f800, 0xc7ff00bf, 0xaeb2f0b9, + 0xdfd59fff, 0x0000055c, 0x0027ab3e, 0x1bf49b26, 0x01f9581a, 0x1bf49d66, 0x3df97f12, 0x08e975a4, + 0x7501ff58, 0x00f809ef, 0x3f04ff90, 0x009433f9, 0xf8010adf, 0x0aa9b200, 0x00b0b302, 0x3db92008, + 0xf900f8a4, 0xb3a0b202, 0x986500a0, 0x90b305a9, 0x0cd95e00, 0xbf000014, 0xe8aab89a, 0x277e0004, + 0xa9e7001a, 0x9ab30168, 0xb34c0fff, 0xb6470090, 0xaab314a5, 0xb3400fff, 0x983b00a0, 0x94b6050e, + 0x0caf940c, 0xe9a0a43d, 0xbf050e98, 0xf0f9bce9, 0x9801efb5, 0x94bd070f, 0x0998f9a0, 0x070f9805, + 0x999299bf, 0x01f9b501, 0x0028343e, 0x343e350a, 0x2e0a0028, 0xaf1801fb, 0x18aebf09, 0x44d908ab, + 0xf0008800, 0xeeb801f4, 0xbc003969, 0xea94f0ff, 0x01b4f002, 0xfd05b9fd, 0x877e05bf, 0xa43d001a, + 0x22f900f8, 0xb132a0b2, 0x350ac2b2, 0x690000b3, 0x94b309bf, 0x09986100, 0x0094b301, 0xe2048a5a, + 0x1a277e00, 0xff1ec400, 0xa601a9c4, 0x091bf49e, 0xc73e943d, 0x0f180028, 0xf0f30908, 0xabc501e4, + 0x01f4f002, 0xb604b9fd, 0xfe0902f4, 0x8a05bffd, 0xfd00e204, 0xbefd04b9, 0x1a877e05, 0xe2048a00, + 0x1a277e00, 0xb3010900, 0x20060020, 0x3ea43d29, 0x0a0028d5, 0xf421fb01, 0xdcdff830, 0xf9000005, + 0xfeffbf52, 0x99900149, 0xa0a3b21c, 0x72b0b29f, 0x0ad4b2c2, 0x0039b335, 0xc97300c7, 0xb300ba00, + 0x00b500d9, 0x9db339bf, 0x9800b400, 0x9db30139, 0x8a00ac00, 0x7e00e208, 0xc4001a27, 0x0bf401a9, + 0xa2a9e70d, 0x0294b602, 0xfe0209bb, 0x3ab2014c, 0xcc90b43d, 0x28627e1b, 0x00ad3300, 0x00890083, + 0x01c43000, 0xbc040503, 0x19c40009, 0x0209bbff, 0x277e0ab2, 0x19c4001a, 0xf259bcff, 0xffff29e4, + 0x1df4f9a6, 0xff2fe407, 0xbdfe32ff, 0x29833ef4, 0x90913c00, 0xb60394f0, 0xa9bc0394, 0xf9493c95, + 0x3201ff90, 0xf4fe26f9, 0xe9c4ea08, 0x040090ff, 0x7302297b, 0xbc0d0020, 0x143d4049, 0x0029503e, + 0x900149fe, 0x9b3f1b99, 0xc4bd3ab2, 0x0028627e, 0x0029bc3e, 0xbc3e020a, 0x010a0029, 0x900149fe, + 0x9fbf1c99, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf90855fb, 0xb2350902, 0x00a0b3a0, + 0xbdb43d1a, 0x28627ec4, 0x33a93200, 0xb20c00a4, 0x28367e0a, 0x32a93200, 0xf401fb9a, 0xdcd9f430, + 0xf9000005, 0xfe99bf12, 0xff90014f, 0x03e84b10, 0xfc7ef9a0, 0xa0b20016, 0x90014afe, 0xa1b208aa, + 0x0015817e, 0x00e5a08a, 0x001a277e, 0xf400a6b0, 0x1ab21c1f, 0x00159c7e, 0x0df4a0a6, 0x3e040a09, + 0x7e002a4d, 0x3e00000e, 0x3d002a24, 0x0149fea4, 0xbf109990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, + 0x3a317e07, 0x0c15fb00, 0xad5802f9, 0x58af3f01, 0xb0b202a9, 0xffffdce4, 0xf003f4f0, 0xf4b60093, + 0x909cbc12, 0x000000de, 0x01999280, 0xf005fefd, 0xf9ffff94, 0x00d073b5, 0x01cf9218, 0x01000089, + 0xff08f4b6, 0xf4f195b9, 0x9fffffff, 0x01aa18b5, 0xf401a9c4, 0x00890a0b, 0xb9fd0200, 0xffa4f005, + 0xf410a9c4, 0x00d90b0b, 0xfd080000, 0xa9c405b9, 0x0b0bf404, 0x000000d9, 0x05b9fd20, 0x00e5a08a, + 0x001a877e, 0xfb7e0ab2, 0x01fb0029, 0xdff830f4, 0x000005dc, 0xffbf42f9, 0x900149fe, 0xa3b21899, + 0xb1729fa0, 0x2000c073, 0x09ffdfc4, 0x029fbb40, 0xffffcfe4, 0xbb0294b6, 0xbfe4029f, 0xf9a6ffff, + 0x00b60cf5, 0x09ffdac4, 0xff12e440, 0x029abbff, 0xa60294b6, 0xa10cf529, 0x00c07300, 0xa2c9e756, + 0x03c0c401, 0xb8409abc, 0x0039284a, 0x7e02a4b6, 0xf0001a27, 0x0994ff04, 0x05a9bb03, 0x900149fe, + 0x9aa01499, 0x90bb0409, 0xf492a602, 0x19e4070d, 0x9c72ffff, 0xf002197b, 0x3ab20093, 0xbc014bfe, + 0xbb903039, 0x00c3f014, 0x000b7e7e, 0xb8014a90, 0x003928a9, 0x940144fe, 0x44900292, 0x2bcc3e14, + 0x70107200, 0x0df40416, 0xb2040005, 0x1a277e2a, 0xff09e400, 0x7b4aa0ff, 0x3ab20210, 0xbc042290, + 0x4bb23039, 0xffff0ce4, 0x000b7e7e, 0xd5001473, 0xd83ea43d, 0x020a002b, 0x900149fe, 0x9fbf1899, + 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf40845fb, 0xdcdff830, 0xf9000005, 0xfeffbf52, + 0x99900149, 0xa0a3b21c, 0x0ab1729f, 0x00b67102, 0x450cf401, 0x820144fe, 0x9000e4a0, 0x54bd1844, + 0x002c503e, 0x107245a0, 0xf4041670, 0x0400050d, 0x0ce43bb2, 0x4ab2ffff, 0x000b7e7e, 0x2ab24bbf, + 0x9002107b, 0x03f00422, 0x1a877e00, 0x3030bc00, 0xd4001473, 0x49fea43d, 0x1c999001, 0xdcd99fbf, + 0xbf000005, 0xf4f9a699, 0x317e070b, 0x55fb003a, 0xb252f908, 0x58c5b2b1, 0xb25802b4, 0x00a0b301, + 0xff43e454, 0xff20e4ff, 0x0034b3ff, 0x0004b30c, 0x2cd13e0c, 0x0000b300, 0x72dab210, 0x2bf37e2b, + 0x00a43300, 0x8b1ab232, 0x7e07a120, 0x33002a68, 0xb32400a4, 0xb0200030, 0xdcf00006, 0x01d6f00b, + 0x4b725ab2, 0xd4362c72, 0x2aec7e05, 0x2cd33e00, 0xfb350a00, 0xf830f451, 0x0005dcdf, 0xbf12f900, + 0x0149feff, 0xfe0c9990, 0x9fa00140, 0xb2080090, 0x7e0cb2b1, 0xbf004526, 0x02f9580f, 0xf003ff98, + 0x94b60093, 0x2d163e0c, 0xf491a600, 0xff98150b, 0x0099b806, 0xf4b30010, 0x350af300, 0x002d353e, + 0x9802fe98, 0xffbf05f9, 0xa6909fbc, 0x089cf09e, 0x320196f0, 0x0149fe9a, 0xbf0c9990, 0x05dcd99f, + 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0815fb00, 0xdfe030f4, 0x000005dc, 0xffbf82f9, 0xfe09b1b0, + 0x99900149, 0x0140fe40, 0x00909fa0, 0xb2a4b23c, 0x45267e0c, 0x5803bf00, 0x31980239, 0x0093f003, + 0x3e0c94b6, 0xb4002d97, 0x9ea609e0, 0x98130bf4, 0x99b80611, 0xb3001000, 0x3ef00014, 0x98002f69, + 0x1f980519, 0x041e9803, 0xbc0395b6, 0x2ea6209f, 0xfe4f0cf4, 0x4ab20143, 0xb2383390, 0xb2010c2b, + 0x28d77e3d, 0x33a03200, 0x01a400ad, 0x004f39bf, 0x014efeff, 0xbc34ee90, 0x9ffd9099, 0xb24ab205, + 0xa0ebb22c, 0x7e040de9, 0x3200406b, 0x00ad33a0, 0x1998017e, 0x01999005, 0x3e0519b5, 0xd9002f6b, + 0x0000297c, 0xfe049e98, 0x99900149, 0xa09fb23c, 0x2e213e9e, 0x09191800, 0x13009033, 0xa0041198, + 0xb3f1bff1, 0x3ef20014, 0x35002f85, 0x593e0839, 0xb918002e, 0x00903308, 0x04bb9813, 0x1bbf1ba0, + 0xf200b4b3, 0x002f693e, 0x4ab2bbbf, 0x003fb97e, 0xad33a032, 0xbf011900, 0x011f9811, 0x42fe3bbf, + 0xb54ab201, 0x1958013f, 0x30229004, 0x2db2040c, 0x7e043975, 0x320028d7, 0x00ad33a0, 0x1cbf00f2, + 0x2bb24ab2, 0x6b7e040d, 0xa0320040, 0xdf00ad33, 0xd92fbf00, 0x7fffffff, 0x4ab22bb2, 0xa004f9fd, + 0x0d3cbf2f, 0x406b7e04, 0x33a03200, 0x00c000ad, 0x98023958, 0x47fe0312, 0x0148fe01, 0x980093f0, + 0x77900331, 0x0c96942c, 0x3e288890, 0xb4002f60, 0x6ea609e0, 0xbf0a1bf4, 0x01999019, 0x1b9819a0, + 0x9815bf01, 0x4ab20513, 0x7db2040c, 0x0028d77e, 0xa100ad33, 0xde7fbf00, 0x00ffffff, 0xff3035bc, + 0x00de943e, 0xfdff0000, 0x9ffd04fe, 0x9879a005, 0x4ab2012c, 0x040d7bb2, 0x00406b7e, 0x7500a433, + 0x1b9823a0, 0x0c4ab203, 0x928db204, 0xd77e04bb, 0xa4330028, 0x2c985f00, 0xb24ab203, 0x92040d8b, + 0x6b7e04cc, 0xa4330040, 0x1f984b00, 0xb594bd02, 0x66b80529, 0xb5001000, 0x2298022f, 0x06119806, + 0x6f001db3, 0x2f6b3eff, 0xfe350000, 0x99900149, 0xd99fbf40, 0x000005dc, 0x0a3299bf, 0x0bf4f9a6, + 0x2f973e1d, 0x0141fe00, 0x1190fea0, 0x2e3e3e3c, 0x3ea03200, 0x7e002f6b, 0xfb003a31, 0x02f92085, + 0xa0b3a0b2, 0xa9985100, 0x0090b306, 0x140cd94a, 0x9abf0000, 0x04e0aab8, 0x1a277e00, 0xffa9e400, + 0xff9ab30f, 0x90b3380f, 0xaae73300, 0xaab3016c, 0xb32b0fff, 0x982600a0, 0x94b6060e, 0x0caf940c, + 0xe9a0a43d, 0xbf060e98, 0xf0f9bce9, 0x3e01efb5, 0x0a002ffb, 0x2ffb3e35, 0xfb2e0a00, 0xd830f401, + 0x0005dcdf, 0xbf82f900, 0x0149feff, 0xb2489990, 0xb39fa0a6, 0x982100a0, 0xfd0906a0, 0xbf920bbf, + 0xf4f9a601, 0x0f98110c, 0xa6ff0901, 0x070bf4f9, 0x1100f4b3, 0x020502f8, 0x7d006db3, 0x32c23e02, + 0x10bb9200, 0x7cdd100c, 0x7e000029, 0x320028d7, 0x00ad33a5, 0x7cda0264, 0xdb000029, 0x00000068, + 0xa87e080c, 0xadb3000b, 0x98027e00, 0x0fbf0109, 0x18f5f9a6, 0xfee40278, 0x1bf50fff, 0x6f980270, + 0x0149fe06, 0x3d449990, 0xb0ffbf84, 0x9ea00af1, 0x91b094bd, 0x329f3e0b, 0x0ba43d00, 0x384c7e14, + 0xb3a3b200, 0xf80c00a4, 0x3e050502, 0xb40032b5, 0x89c40ae0, 0x0c94b6ff, 0xbdb09ebc, 0xb5aba094, + 0xb9e404a9, 0x1bf50fff, 0x4dfe0224, 0x0c6ab201, 0x44dd9004, 0x0028d77e, 0x0a00a033, 0xb13ea532, + 0x90b40032, 0xff94f111, 0x0239750f, 0xe71190b4, 0x75016c99, 0x90b40339, 0x1f95b611, 0xb4083935, + 0xf9e411f0, 0x9ab30fff, 0xe7130fff, 0xb3016cf9, 0x0a0fff9a, 0x39350109, 0xb339bf09, 0x00900099, + 0x00297cdf, 0x0dfb1800, 0x4a049990, 0x91b00ffc, 0xffb4f009, 0x0016bb7e, 0x743d94bd, 0x090d91b0, + 0x94a9fffc, 0x3e0c91b0, 0x3d003277, 0x7e1c0ba4, 0xb200384c, 0x00a4b3a1, 0x0002f80c, 0x32de3e05, + 0x0cb0b400, 0x7eff7ac4, 0xbd0016fc, 0x061eb5e4, 0x0c09b0b4, 0x014dfe04, 0xbc40dd90, 0x6ab2b0ba, + 0x7e011bb5, 0x320028d7, 0x00ad33a0, 0x90b40155, 0xffffdf10, 0x9ffd00ff, 0xa619a004, 0x071bf49f, + 0x19a094bd, 0xb3011b98, 0xf80c00b4, 0x3e020002, 0xb40032de, 0x3f180ce0, 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0x00e9f680, 0x00b0718f, 0xf6040049, 0x008f009f, 0xf9ce0215, 0x0195f000, 0xfe00f9f7, 0x9fbf0149, - 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf80430f4, 0x05dcde00, 0xefbf0000, 0xfefc30f4, - 0x004a0149, 0xbf9fa020, 0xa6e9bf9f, 0x070bf4f9, 0x0042e97e, 0xf80430f4, 0x05dcdf00, 0xffbf0000, - 0xfefc30f4, 0x9fa00149, 0xce01004f, 0x95f000f9, 0x00f9f710, 0xce07004f, 0x95f000f9, 0x00f9f710, - 0xce04004f, 0x95f000f9, 0x00f9f710, 0xbf0149fe, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, - 0x0430f400, 0x30f400f8, 0xd112f9fc, 0x000005dc, 0x40fe19bf, 0x08009001, 0x002d8ada, 0xd909a000, - 0x00001330, 0x999899bf, 0xbf95f908, 0xa619bf0f, 0x070bf4f9, 0x0042e97e, 0xd90415fb, 0x000005dc, - 0x30f499bf, 0x014ffefc, 0xad7ef9a0, 0xa433005d, 0xaddf1100, 0x49deadde, 0x9ff61000, 0x7e02f800, - 0x7e005df4, 0x7e005d65, 0xfe005e30, 0x9fbf0149, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, - 0xf80430f4, 0x05dcdf00, 0xffbf0000, 0xfefc30f4, 0x9fa00149, 0x00900089, 0xf00099cf, 0x0bf40194, - 0xa5008915, 0x009fcf00, 0xf5f0ef0e, 0x04fefd07, 0xfe009ff6, 0x9fbf0149, 0x0005dcd9, 0xa699bf00, - 0x070bf4f9, 0x0042e97e, 0xf80430f4, 0x05dcdf00, 0xffbf0000, 0xfefc30f4, 0x9fa00149, 0x00900089, - 0xc4009fcf, 0x1bf401f9, 0x3ea43d09, 0xc7005dda, 0x96b024f9, 0x0b9cf002, 0x49fe9a32, 0xd99fbf01, - 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xf40042e9, 0x00f80430, 0x0005dcdf, 0xf4ffbf00, 0x49fefc30, - 0x0f9fa001, 0x80008905, 0x009ff601, 0x99b8060f, 0xf6000100, 0x49fe009f, 0xd99fbf01, 0x000005dc, - 0xf9a699bf, 0x7e070bf4, 0xf40042e9, 0x00f80430, 0x0005dcdf, 0xf4ffbf00, 0x49fefc30, 0x899fa001, - 0xcf010200, 0x008f0099, 0x9ffd1000, 0x1a1bf404, 0x820434da, 0x1c227e00, 0x01a4f000, 0xf80b1bf4, - 0x3e240a02, 0x3d005e69, 0x0149fea4, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x30f40042, - 0xf400f804, 0x12f9fc30, 0x0005dcd1, 0xfe19bf00, 0x00900140, 0x1334da08, 0x09a00000, 0x001330d9, - 0x9899bf00, 0x95f90e99, 0x19bf0fbf, 0x0bf4f9a6, 0x42e97e07, 0x0415fb00, 0x0005dcd9, 0xf499bf00, - 0x4ffefc30, 0xa01e0a01, 0xdc647ef9, 0x00a03300, 0xfe02f806, 0x9fbf0149, 0x0005dcd9, 0xa699bf00, - 0x070bf4f9, 0x0042e97e, 0xf80430f4, 0x05dcdf00, 0xffbf0000, 0xfefc30f4, 0x9fa00149, 0x0100008f, - 0xf6590049, 0x49fe009f, 0xd99fbf01, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xf40042e9, 0x00f80430, - 0x0005dcdf, 0xf4ffbf00, 0x49fefc30, 0x899fa001, 0xce009000, 0x94f00099, 0x200bf401, 0x00f1008e, - 0x0f00e9ce, 0x049ffdef, 0xb800e9f7, 0x025200ee, 0xfd00e9ce, 0xe9f7049f, 0x0149fe00, 0xdcd99fbf, - 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x30f40042, 0xd900f804, 0x000005dc, 0x30f499bf, 0x014ffefc, - 0xa00a004a, 0x1c227ef9, 0x14aae700, 0x06a4b301, 0x4f004f20, 0xc700f9cf, 0x94b3e899, 0xf9cf130f, - 0xff94f000, 0x320b9cf0, 0x5faf3e9a, 0xfea43d00, 0x9fbf0149, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, - 0x0042e97e, 0xf80430f4, 0xfc30f400, 0x0005dcdf, 0xbf02f900, 0x0149feff, 0xa0049990, 0x9000899f, - 0x0099ce00, 0xf50194f0, 0x7e00d70b, 0xbd00627c, 0xbdc4bdb4, 0x7e090ad4, 0x9000246b, 0x227ec8aa, - 0x010c001c, 0xd4bda0b2, 0x0a0ab4bd, 0x00246b7e, 0xaa90f00b, 0xb40bffc8, 0x001cb17e, 0xd4bdc4bd, - 0xa4bdb4bd, 0x00246b7e, 0xa0b2b4bd, 0x0528aab8, 0x1cb17e00, 0x300ab800, 0xb4bd0005, 0x001cb17e, - 0x05340ab8, 0x7eb4bd00, 0xb8001cb1, 0x00010c0a, 0xb17e040b, 0x0ab8001c, 0x0b000100, 0x1cb17e4a, - 0x040ab800, 0x4a0b0001, 0x001cb17e, 0x01080ab8, 0x7e420b00, 0x90001cb1, 0x0ab26400, 0x001c227e, - 0xa9fffe09, 0x7e0ab2b4, 0x8a001cb1, 0x7e00e2f0, 0xc5001c22, 0xf08a40ab, 0xb17e00e2, 0xf48a001c, - 0x227e00e2, 0xabc5001c, 0xe2f48a40, 0x1cb17e00, 0x64e67e00, 0x89f4bd00, 0xf6038a00, 0x49fe009f, - 0x04999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x05fb0042, 0xfc30f404, 0x0005dcdf, - 0xbf12f900, 0x0149feff, 0xa0089990, 0x9000899f, 0x0099ce00, 0xf50194f0, 0xbd009e0b, 0xbdc4bdb4, - 0x7e0b0ad4, 0x0c00246b, 0xb2d4bd01, 0x0ab4bda1, 0x246b7e0c, 0x90a0b200, 0x227e1c1a, 0xabc5001c, - 0x1c0a9010, 0x001cb17e, 0x501c1ab8, 0x1c227e00, 0x10abc500, 0x501c0ab8, 0x1cb17e00, 0x1c1ab800, - 0x227e0010, 0xabc5001c, 0x1c0ab810, 0xb17e0010, 0x1ab8001c, 0x7e00401c, 0xc5001c22, 0x0ab810ab, - 0x7e00401c, 0xb8001cb1, 0x00301c1a, 0x001c227e, 0xb810abc5, 0x00301c0a, 0x001cb17e, 0x601c1ab8, - 0x1c227e00, 0x10abc500, 0x601c0ab8, 0x1cb17e00, 0x62de7e00, 0x0149fe00, 0xbf089990, 0x05dcd99f, - 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0415fb00, 0x0005dcdf, 0xf4ffbf00, 0x008efc30, 0x49fe0095, - 0xcf9fa001, 0xff4f00e9, 0x049ffdcf, 0x200095f1, 0x8f00e9f6, 0xcf01a100, 0x95f000f9, 0x00f9f601, - 0xcf24004e, 0x008f00e9, 0x9ffd0600, 0x00e9f605, 0x005f207e, 0x0095008f, 0xf000f9cf, 0xf9f62095, - 0xffffdf00, 0x008900ff, 0x9ff601c3, 0x273e7e00, 0x0a004a00, 0x001c227e, 0xde6ca9c7, 0x00001334, - 0x0907e935, 0x0de93503, 0xc70ce935, 0xe93598a9, 0x74a9c704, 0xbd05e935, 0x70aac794, 0x3502e9b5, - 0x008906ea, 0x99cf0102, 0x00008f00, 0x049ffd10, 0x09080bf4, 0x0ee93501, 0x0060d97e, 0x005fc97e, - 0xbf0149fe, 0x05dcd99f, 0x99bf0000, 0xf9a6a43d, 0x7e070bf4, 0xf40042e9, 0x00f80430, 0x0005dcdf, - 0xf4ffbf00, 0x49fefc30, 0x899fa001, 0xce009000, 0x94f00099, 0x2f0bf401, 0xd4bd010c, 0x100ab4bd, - 0x00246b7e, 0x0100008b, 0x7e40aa90, 0xbd001cb1, 0x0c0e0ab4, 0x7ed4bd01, 0x0b00246b, 0x94aa9001, - 0x001cb17e, 0xbf0149fe, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, 0x30f400f8, - 0x05dcdffc, 0x12f90000, 0x49feffbf, 0x08999001, 0x00899fa0, 0x99ce0090, 0x0194f000, 0xbd5d0bf4, - 0xbdc4bdb4, 0x7e0d0ad4, 0x0c00246b, 0xb2d4bd01, 0x0ab4bda1, 0x246b7e0e, 0x90a0b200, 0x227e0c1a, - 0xabc5001c, 0x0c0a9010, 0x001cb17e, 0xc4bdb4bd, 0x0f0ad4bd, 0x00246b7e, 0xa1b2b4bd, 0xd4bd010c, - 0x6b7e100a, 0xa0b20024, 0x7e0c1a90, 0xc5001c22, 0x0a9010ab, 0x1cb17e0c, 0x0149fe00, 0xbf089990, - 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0415fb00, 0xf9fc30f4, 0x05dcd112, 0x19bf0000, - 0x900140fe, 0x28da0800, 0xa0000028, 0x1330d909, 0x99bf0000, 0xf9119998, 0xbf0fbf95, 0xf4f9a619, - 0xe97e070b, 0x15fb0042, 0xfc30f404, 0xdcd112f9, 0xbf000005, 0x0140fe19, 0x0090a4bd, 0xa0b4bd08, - 0x3dc4bd09, 0x43617ed4, 0xbf0fbf00, 0xf4f9a619, 0xe97e070b, 0x15fb0042, 0x05dcdf04, 0xffbf0000, - 0xfefc30f4, 0x30da0149, 0xa0000028, 0x7eb43d9f, 0xd900733f, 0x00002830, 0x94b399bf, 0x02f80600, - 0xbf0149fe, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x42e97e07, 0x0430f400, 0x30f400f8, 0xd112f9fc, - 0x000005dc, 0x40fe19bf, 0x08009001, 0x002d8bda, 0xd909a000, 0x00001330, 0x943d9fbf, 0xf998a920, - 0xbf95f910, 0x3d19bf0f, 0xf4f9a6a4, 0xe97e070b, 0x15fb0042, 0x130cd904, 0x30f40000, 0xd112f9fc, - 0x000005dc, 0x19bf9abf, 0xfe03034b, 0xaab80140, 0x900002dc, 0x09a00800, 0x001cb17e, 0x066f448a, - 0x001c227e, 0x1ebf0dbf, 0x000600d9, 0xffa4f100, 0x42408f3f, 0xd99aa00f, 0x00000604, 0xa43d9fa0, - 0x0bf4dea6, 0x42e97e07, 0x0415fb00, 0xf9fc30f4, 0x05dcd112, 0x19bf0000, 0x900140fe, 0x8cda0800, - 0xa000002d, 0x1330d909, 0x9fbf0000, 0xa920943d, 0x95f9f9bf, 0x19bf0fbf, 0xf9a6a43d, 0x7e070bf4, - 0xfb0042e9, 0x30f40415, 0xd222f9fc, 0x000005dc, 0xc4bd29bf, 0xb4bdd4bd, 0x0a0141fe, 0x0c119011, - 0x6b7e19a0, 0xa0b80024, 0xb2000484, 0x1c227e0a, 0x01abc500, 0xb17e0ab2, 0xc08a001c, 0x227e08b8, - 0xfb09001c, 0x8ab4a9ff, 0x7e08b8c0, 0x8a001cb1, 0x7e08b940, 0x09001c22, 0xb4a9ffe0, 0x08b9408a, - 0x7e02b5f0, 0xbf001cb1, 0xa629bf1f, 0x070bf4f9, 0x0042e97e, 0xf40425fb, 0x12f9fc30, 0x0005dcd1, - 0xbd19bf00, 0xbdc4bdb4, 0x0140fed4, 0x0090a4bd, 0x7e09a008, 0xd900246b, 0x00001330, 0x0cd99fbf, - 0xa0000013, 0x2d8eda9a, 0xf9980000, 0xbf95f90c, 0xa619bf0f, 0x070bf4f9, 0x0042e97e, 0xf40415fb, - 0x22f9fc30, 0x00130cd0, 0x05dcd200, 0x0abf0000, 0xff0b29bf, 0xb80141fe, 0x0008b8aa, 0xa00c1190, - 0x1cb17e19, 0x0b0abf00, 0xbcaab8ff, 0xb17e0008, 0x0abf001c, 0xaab8ff0b, 0x7e0008c0, 0xbf001cb1, - 0xb8ff0b0a, 0x0008c4aa, 0x001cb17e, 0x008b0abf, 0xaab87000, 0x7e0008d4, 0xbf001cb1, 0x0000db0a, - 0xaab80100, 0x7e0008a8, 0xbf001cb1, 0xffffdb0a, 0xaab80e03, 0x7e0008e0, 0xbf001cb1, 0x0000db0a, - 0xaab8ce00, 0x7e0008b4, 0xbf001cb1, 0xa629bf1f, 0x070bf4f9, 0x0042e97e, 0xf40425fb, 0x12f9fc30, - 0x0005dcd1, 0xfe19bf00, 0x00900140, 0x2d8fda08, 0x09a00000, 0x001330d9, 0x9899bf00, 0x95f90799, - 0x19bf0fbf, 0x0bf4f9a6, 0x42e97e07, 0x0415fb00, 0xf9fc30f4, 0x05dcd112, 0x19bf0000, 0x900140fe, - 0x90da0800, 0xa000002d, 0x1330d909, 0x99bf0000, 0xf9099998, 0xbf0fbf95, 0xf4f9a619, 0xe97e070b, - 0x15fb0042, 0x05dcde04, 0xe9bf0000, 0xfefc30f4, 0x38dd014f, 0xa0000028, 0xbffcbff9, 0xa0ff09ef, - 0xb50f09d9, 0xcfa601d9, 0x7e070bf4, 0xf40042e9, 0x00f80430, 0xf9fc30f4, 0x05dcd112, 0x19bf0000, - 0x900140fe, 0x91da0800, 0xa000002d, 0x1330d909, 0x99bf0000, 0xf90a9998, 0xbf0fbf95, 0xf4f9a619, - 0xe97e070b, 0x15fb0042, 0x05dcdf04, 0xfebf0000, 0xfefc30f4, 0x9ea00149, 0xf9bf9ebf, 0x0bf4e9a6, - 0x42e97e07, 0x0430f400, 0x30f400f8, 0xd112f9fc, 0x000005dc, 0x40fe19bf, 0x08009001, 0x002d92da, - 0xd909a000, 0x00001330, 0x999899bf, 0xbf95f904, 0xa619bf0f, 0x070bf4f9, 0x0042e97e, 0xdf0415fb, - 0x000005dc, 0x30f4febf, 0x0149fefc, 0x9ebf9ea0, 0xe9a6f9bf, 0x7e070bf4, 0xf40042e9, 0x00f80430, - 0xf9fc30f4, 0x05dcd112, 0x19bf0000, 0x900140fe, 0x93da0800, 0xa000002d, 0x1330d909, 0x99bf0000, - 0xf9039998, 0xbf0fbf95, 0xf4f9a619, 0xe97e070b, 0x15fb0042, 0x05dcdf04, 0xfebf0000, 0xfefc30f4, - 0x9ea00149, 0xf9bf9ebf, 0x0bf4e9a6, 0x42e97e07, 0x0430f400, 0x30f400f8, 0xd112f9fc, 0x000005dc, - 0x40fe19bf, 0x08009001, 0x002878da, 0xd909a000, 0x00001330, 0x999899bf, 0xdf95f90f, 0x00002870, - 0x1ebf0dbf, 0x002844d9, 0x069fb500, 0x002868df, 0x059fb500, 0x9f35f4bd, 0xb59fa009, 0x9f35019f, - 0xb5320f08, 0xdea6039f, 0x7e070bf4, 0xfb0042e9, 0xdcdf0415, 0xbf000005, 0xfc30f4fe, 0xa00149fe, - 0xbf9ebf9e, 0xf4e9a6f9, 0xe97e070b, 0x30f40042, 0xf400f804, 0x12f9fc30, 0x0005dcd1, 0xfe19bf00, - 0x00900140, 0x2d94da08, 0x09a00000, 0x001330d9, 0x9899bf00, 0x95f90699, 0x19bf0fbf, 0x0bf4f9a6, - 0x42e97e07, 0x0415fb00, 0x0005dcdf, 0xf4febf00, 0x49fefc30, 0xbf9ea001, 0xa6f9bf9e, 0x070bf4e9, - 0x0042e97e, 0xf80430f4, 0xfc30f400, 0xdcd112f9, 0xbf000005, 0x0140fe19, 0xda080090, 0x00002898, - 0x30d909a0, 0xbf000013, 0x01999899, 0x0fbf95f9, 0xf9a619bf, 0x7e070bf4, 0xfb0042e9, 0x30f50415, - 0xdcdfff18, 0xf9000005, 0xfeffbf82, 0x99b80149, 0x0a000108, 0x7e9fa008, 0xb2001c22, 0x7e080aa0, - 0xd9001c22, 0x40000000, 0xf50409fd, 0x95044d1b, 0x99b31fa9, 0x3d044601, 0x01dc4ba4, 0x417e040c, - 0xa4b20040, 0x4500a9b3, 0x76a0b503, 0xb571a0b5, 0xa0b572a0, 0x74a0b573, 0xd975a0b5, 0x00002890, - 0x90014ffe, 0x44dae8ff, 0xb5000028, 0xb67e019f, 0xa232002f, 0x0900a033, 0x112ead33, 0x2844d903, - 0x99980000, 0x2890de07, 0x9fbf0000, 0xbb019998, 0xe9a0029f, 0x9b0099b3, 0x75499800, 0x8b009db3, - 0x0143fe00, 0x14bde5b2, 0xd6aa5547, 0x52494350, 0x3ea83390, 0xda0069fd, 0x00002890, 0x257e1bb2, - 0xa7660054, 0xda561bf4, 0x00002890, 0x7e181b90, 0xbf005425, 0x00a3f059, 0x9000a1bc, 0xf9a61c0f, - 0xda3a18f4, 0x00002890, 0x607e0bb2, 0xa6a60054, 0xb22a1bf4, 0x2890da0c, 0x3bb20000, 0x7aded4bd, - 0x7e000000, 0x3300525f, 0x982800a4, 0x9eb30139, 0xb50c10de, 0x073e7541, 0x1190006a, 0x9259bf01, - 0x19a63499, 0x989308f4, 0x99b37549, 0x33025f00, 0x025a002d, 0xb3744998, 0x0110009d, 0xb3754298, - 0x3e740024, 0xda006c69, 0x00002890, 0x257e2bb2, 0xa8660054, 0xda511bf4, 0x00002890, 0x7e022b90, - 0xa6005460, 0x401bf4a7, 0xda7442b5, 0x00002890, 0xbd082b90, 0x549b7e04, 0xc414bd00, 0x773effa3, - 0x02bc006a, 0x2890dab0, 0x00900000, 0x549b7e01, 0xffa4f000, 0xa6101abc, 0xe908f403, 0x09001033, - 0xa00156b5, 0x74499856, 0x240094b3, 0x3e012290, 0xd5006aa1, 0x00002890, 0x87b8ff48, 0xbd544942, - 0x9259bf64, 0x29a60399, 0xff7f08f5, 0xb3744c98, 0x027800cd, 0x006c693e, 0x98043b98, 0x30987449, - 0xff1ac403, 0x7e0009bc, 0xb20016fc, 0x000abc2b, 0x0cb2d4bd, 0x002890da, 0x0087de00, 0x5f7e0000, - 0xad330052, 0xbf018700, 0x754f9829, 0xb3032c98, 0xbc2a4994, 0x90dac0cf, 0xb2000028, 0xded4bd5b, - 0x0000008c, 0x00525f7e, 0x6100ad33, 0x0e5f9801, 0xbc754998, 0x49b5909f, 0x01111076, 0xc4053f98, - 0x9fa6ff19, 0x989408f4, 0x19b37641, 0xda013f00, 0x00002890, 0x9b7e1bb2, 0xad330054, 0xda012f02, - 0x00002890, 0x7e011b90, 0x3300549b, 0x011e08ad, 0xda0140fe, 0x00002890, 0xb27c0090, 0xbd0bb21c, - 0x0090ded4, 0x5f7e0000, 0xad330052, 0x9800ff00, 0x56b00505, 0x050df424, 0x49fe2405, 0x7c999001, - 0x98029e98, 0x40b2019f, 0x24bd94bd, 0xb5f01fbc, 0x41fe7049, 0x30febc01, 0x3e601190, 0xda006be8, - 0x00002890, 0x3cb21bb2, 0x95ded4bd, 0x7e000000, 0x3300525f, 0x3f3d00a4, 0x07339019, 0x20012290, - 0x04191809, 0x18010935, 0x09350819, 0x0c191802, 0x18030935, 0x09351019, 0x14191804, 0x18050935, - 0x09351819, 0x07009006, 0x08f425a6, 0x7042b5b5, 0xb0704198, 0x0cf42416, 0x3d24bd0b, 0x6c153e04, - 0x10004900, 0x0f0091f7, 0x1100490a, 0xf8009ff7, 0xbd043d02, 0x3e34bd24, 0x98006c5d, 0x9e94714f, - 0x02e9bb03, 0xb609f994, 0x9fbb06f4, 0xe0e9bc02, 0xb3904ebc, 0x3c270090, 0x94f0984e, 0x00903302, - 0xbd010a1d, 0xff0cc4b4, 0x0042667e, 0xff953bff, 0x9fb2a52a, 0xe2b2aeb2, 0x0010f3b2, 0xff09c401, - 0x08f491a6, 0x6c6d3eb9, 0xbd24bd00, 0x90008934, 0x0099ce00, 0xf50194f0, 0xbd00e10b, 0x3ef70544, - 0xc4006d1c, 0x0bf50129, 0xc4bd008d, 0x4bb2d4bd, 0x6b7e080a, 0xa0b20024, 0x0608a1b8, 0x7e1ab200, - 0xe5001c22, 0xb28000ab, 0x1cb17e1a, 0x2001b800, 0x1ab20006, 0x001c227e, 0xb204abc5, 0x1cb17e1a, - 0x0001b800, 0x1ab20006, 0x001c227e, 0x8000abe5, 0xb17e1ab2, 0x01b8001c, 0xb2000618, 0x1c227e1a, - 0xb4a5ff00, 0xb17e1ab2, 0x01b8001c, 0xb2000604, 0x1c227e1a, 0x00abe500, 0x7e1ab280, 0xb8001cb1, - 0x00061c00, 0x227e0ab2, 0xabc5001c, 0x7e0ab204, 0x90001cb1, 0x33950144, 0x01229d01, 0xf59523ff, - 0x3eff641b, 0xfe006d58, 0x90da0140, 0x90000028, 0xd4bd6000, 0x98de0bb2, 0x7e000000, 0x3300525f, - 0xff2a00ad, 0xfe0142fe, 0x03b20145, 0x2290143d, 0x24559098, 0x006b1c3e, 0xb80149fe, 0x00010899, - 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x83fb0042, 0x30f400e8, 0xd112f9fc, 0x000005dc, - 0xb4bd19bf, 0xfe00c04c, 0x9cda0140, 0x90000028, 0x09a00800, 0x000b947e, 0x001330d9, 0xda99bf00, - 0x00002958, 0xf90d9998, 0xbf0fbf95, 0xa6a43d19, 0x070bf4f9, 0x0042e97e, 0xd90415fb, 0x000005cc, - 0xf9fc30f4, 0x05dcd112, 0x9abf0000, 0x40fe19bf, 0x2d70db01, 0x00900000, 0xa0010c08, 0x72e57e09, - 0xbf0fbf00, 0xf4f9a619, 0xe97e070b, 0x15fb0042, 0x71477e04, 0x3d00f800, 0x73537ed4, 0xf400f800, - 0x12f9e430, 0xb0b2a1b2, 0x6100b0b3, 0xb004b998, 0x0cf40896, 0x0ba43d57, 0x40e57e44, 0x0aafb200, + 0x01b01c01, 0x08113001, 0xc04e0a0d, 0x05d8da00, 0x0a7e0000, 0x1cda005d, 0x0b000014, 0x7e080c04, + 0x33005937, 0x7e5c00a4, 0x7e005c97, 0x7e004db4, 0x7e005931, 0x7e000a74, 0x7e003cf7, 0x7e005249, + 0x7e004d7d, 0x7e004df2, 0x7e005208, 0x7e005216, 0x7e0053af, 0x7e0053d2, 0x7e0053e7, 0x7e0053fc, + 0x7e005438, 0x7e00544d, 0x7e00591d, 0x7e00706d, 0x7e005462, 0x7e004ea6, 0x330059ae, 0xf80600a0, + 0x2c30f402, 0x30d911fb, 0xbf000014, 0x2e88da99, 0x99980000, 0xf895f905, 0xf8400a00, 0x0070df00, + 0x00492000, 0x009ff607, 0xcf03004e, 0xff4f00e9, 0x049ffdcf, 0x800095f1, 0x8f00e9f6, 0x4900b071, + 0x9ff60400, 0x15008f00, 0x00f9ce02, 0xf70195f0, 0x00f800f9, 0xf820004a, 0x01004f00, 0xf000f9ce, + 0xf9f71095, 0x07004f00, 0xf000f9ce, 0xf9f71095, 0x04004f00, 0xf000f9ce, 0xf9f71095, 0xd900f800, + 0x00001430, 0x8ada99bf, 0x9800002e, 0x95f90899, 0x367e00f8, 0xa433004e, 0xaddf1100, 0x49deadde, + 0x9ff61000, 0x7e02f800, 0x7e004e54, 0x7e004e15, 0xf8004e69, 0x90008900, 0x0099cf00, 0xf40194f0, + 0x0089150b, 0x9fcf00a5, 0xf0ef0e00, 0xfefd07f5, 0x009ff604, 0x008900f8, 0x9fcf0090, 0x01f9c400, + 0x3d071bf4, 0xc700f8a4, 0x96b024f9, 0x0b9cf002, 0x00f89a32, 0x0089050f, 0x9ff60180, 0xb8060f00, + 0x00010099, 0xf8009ff6, 0x02008900, 0x0099cf01, 0x1000008f, 0xf4049ffd, 0x34da181b, 0x7e008204, + 0xf0001a27, 0x1bf401a4, 0x0a02f809, 0x3d00f824, 0xd900f8a4, 0x00001430, 0x34da99bf, 0x98000014, + 0x95f90e99, 0x1e0a00f8, 0x00b99e7e, 0x0600a033, 0x00f802f8, 0x0100008f, 0xf6590049, 0x00f8009f, + 0x00900089, 0xf00099ce, 0x0bf40194, 0xf1008e20, 0x00e9ce00, 0x9ffdef0f, 0x00e9f704, 0x5200eeb8, + 0x00e9ce02, 0xf7049ffd, 0x00f800e9, 0x7e0a004a, 0xe7001a27, 0xb30114aa, 0x4f1e06a4, 0xf9cf4f00, + 0xe899c700, 0x110f94b3, 0xf000f9cf, 0x9cf0ff94, 0xf89a320b, 0xf8a43d00, 0x8902f900, 0xce009000, + 0x94f00099, 0xd70bf501, 0x514f7e00, 0xbdb4bd00, 0x0ad4bdc4, 0x1f137e09, 0xc8aa9000, 0x001a277e, + 0xa0b2010c, 0xb4bdd4bd, 0x137e0a0a, 0xf00b001f, 0xffc8aa90, 0x877eb40b, 0xc4bd001a, 0xb4bdd4bd, + 0x137ea4bd, 0xb4bd001f, 0xaab8a0b2, 0x7e000528, 0xb8001a87, 0x0005300a, 0x877eb4bd, 0x0ab8001a, + 0xbd000534, 0x1a877eb4, 0x0c0ab800, 0x040b0001, 0x001a877e, 0x01000ab8, 0x7e4a0b00, 0xb8001a87, + 0x0001040a, 0x877e4a0b, 0x0ab8001a, 0x0b000108, 0x1a877e42, 0x64009000, 0x277e0ab2, 0xfe09001a, + 0xb2b4a9ff, 0x1a877e0a, 0xe2f08a00, 0x1a277e00, 0x40abc500, 0x00e2f08a, 0x001a877e, 0x00e2f48a, + 0x001a277e, 0x8a40abc5, 0x7e00e2f4, 0x7e001a87, 0xbd005296, 0x8a0089f4, 0x009ff603, 0x12f901fb, + 0x00900089, 0xf00099ce, 0x0bf50194, 0xb4bd009e, 0xd4bdc4bd, 0x137e0b0a, 0x010c001f, 0xa1b2d4bd, + 0x0c0ab4bd, 0x001f137e, 0x1a90a0b2, 0x1a277e1c, 0x10abc500, 0x7e1c0a90, 0xb8001a87, 0x00501c1a, + 0x001a277e, 0xb810abc5, 0x00501c0a, 0x001a877e, 0x101c1ab8, 0x1a277e00, 0x10abc500, 0x101c0ab8, + 0x1a877e00, 0x1c1ab800, 0x277e0040, 0xabc5001a, 0x1c0ab810, 0x877e0040, 0x1ab8001a, 0x7e00301c, + 0xc5001a27, 0x0ab810ab, 0x7e00301c, 0xb8001a87, 0x00601c1a, 0x001a277e, 0xb810abc5, 0x00601c0a, + 0x001a877e, 0x00518a7e, 0x008e11fb, 0xe9cf0095, 0xcfff4f00, 0xf1049ffd, 0xf6200095, 0x008f00e9, + 0xf9cf01a1, 0x0195f000, 0x4e00f9f6, 0xe9cf2400, 0x00008f00, 0x059ffd06, 0x7e00e9f6, 0x8f004ec0, + 0xcf009500, 0x95f000f9, 0x00f9f620, 0xffffffdf, 0xc3008900, 0x009ff601, 0x00219c7e, 0x7e0a004a, + 0xc7001a27, 0x34de6ca9, 0x35000014, 0x030907e9, 0x350de935, 0xa9c70ce9, 0x04e93598, 0x3574a9c7, + 0x94bd05e9, 0xb570aac7, 0xea3502e9, 0x02008906, 0x0099cf01, 0x1000008f, 0xf4049ffd, 0x0109080b, + 0x7e0ee935, 0x7e004ffe, 0x3d004f19, 0x8900f8a4, 0xce009000, 0x94f00099, 0x2f0bf401, 0xd4bd010c, + 0x100ab4bd, 0x001f137e, 0x0100008b, 0x7e40aa90, 0xbd001a87, 0x0c0e0ab4, 0x7ed4bd01, 0x0b001f13, + 0x94aa9001, 0x001a877e, 0x12f900f8, 0x00900089, 0xf00099ce, 0x0bf40194, 0xbdb4bd5d, 0x0ad4bdc4, + 0x1f137e0d, 0xbd010c00, 0xbda1b2d4, 0x7e0e0ab4, 0xb2001f13, 0x0c1a90a0, 0x001a277e, 0x9010abc5, + 0x877e0c0a, 0xb4bd001a, 0xd4bdc4bd, 0x137e0f0a, 0xb4bd001f, 0x010ca1b2, 0x100ad4bd, 0x001f137e, + 0x1a90a0b2, 0x1a277e0c, 0x10abc500, 0x7e0c0a90, 0xfb001a87, 0x1430d911, 0x99bf0000, 0x002928da, + 0x11999800, 0x00f895f9, 0xc4bdb4bd, 0xa4bdd43d, 0x003aa97e, 0x30da00f8, 0x3d000029, 0x5e7f7eb4, + 0x2930d900, 0x99bf0000, 0x060094b3, 0x00f802f8, 0x001430d9, 0x3d9fbf00, 0x2e8bda94, 0xa9200000, + 0xf910f998, 0xf8a43d95, 0x140cd900, 0x9abf0000, 0xb803034b, 0x0002dcaa, 0x001a877e, 0x066f448a, + 0x001a277e, 0x000600d9, 0xffa4f100, 0x42408f3f, 0xd99aa00f, 0x00000604, 0x9fa0a43d, 0x30d900f8, + 0xbf000014, 0xda943d9f, 0x00002e8c, 0xf9bfa920, 0xa43d95f9, 0x02f900f8, 0xd4bdc4bd, 0x110ab4bd, + 0x001f137e, 0x0484a0b8, 0x7e0ab200, 0xc5001a27, 0x0ab201ab, 0x001a877e, 0x08b8c08a, 0x001a277e, + 0xa9fffb09, 0xb8c08ab4, 0x1a877e08, 0xb9408a00, 0x1a277e08, 0xffe00900, 0x408ab4a9, 0xb5f008b9, + 0x1a877e02, 0xbd01fb00, 0xbdc4bdb4, 0x7ea4bdd4, 0xd9001f13, 0x00001430, 0x0cd99fbf, 0xa0000014, + 0x2e8eda9a, 0xf9980000, 0xf895f90c, 0xd002f900, 0x0000140c, 0xff0b0abf, 0x08b8aab8, 0x1a877e00, + 0x0b0abf00, 0xbcaab8ff, 0x877e0008, 0x0abf001a, 0xaab8ff0b, 0x7e0008c0, 0xbf001a87, 0xb8ff0b0a, + 0x0008c4aa, 0x001a877e, 0x008b0abf, 0xaab87000, 0x7e0008d4, 0xbf001a87, 0x0000db0a, 0xaab80100, + 0x7e0008a8, 0xbf001a87, 0xffffdb0a, 0xaab80e03, 0x7e0008e0, 0xbf001a87, 0x0000db0a, 0xaab8ce00, + 0x7e0008b4, 0xfb001a87, 0x1430d901, 0x99bf0000, 0x002e8fda, 0x07999800, 0x00f895f9, 0x001430d9, + 0xda99bf00, 0x00002e90, 0xf9099998, 0x0f00f895, 0x2938d9ff, 0x9fa00000, 0x9fb50f0f, 0xd900f801, + 0x00001430, 0x91da99bf, 0x9800002e, 0x95f90a99, 0x00f800f8, 0x001430d9, 0xda99bf00, 0x00002e92, + 0xf9049998, 0xf800f895, 0x1430d900, 0x99bf0000, 0x002e93da, 0x03999800, 0x00f895f9, 0x30d900f8, + 0xbf000014, 0x2978da99, 0x99980000, 0xdf95f90f, 0x00002970, 0x002944d9, 0x069fb500, 0x002968df, + 0x059fb500, 0x9f35f4bd, 0xb59fa009, 0x9f35019f, 0xb5320f08, 0x00f8039f, 0x30d900f8, 0xbf000014, + 0x2e94da99, 0x99980000, 0xf895f906, 0xd900f800, 0x00001430, 0x98da99bf, 0x98000029, 0x95f90199, + 0x30f500f8, 0xdcdfff18, 0xf9000005, 0xfeffbf82, 0x99b80149, 0x0a000108, 0x7e9fa008, 0xb2001a27, + 0x7e080aa0, 0xd9001a27, 0x40000000, 0xf50409fd, 0x95044d1b, 0x99b31fa9, 0x3d044601, 0x01dc4ba4, + 0xa87e040c, 0xa4b20037, 0x4500a9b3, 0x76a0b503, 0xb571a0b5, 0xa0b572a0, 0x74a0b573, 0xd975a0b5, + 0x00002990, 0x90014ffe, 0x44dae8ff, 0xb5000029, 0xc37e019f, 0xa2320027, 0x0900a033, 0x112ead33, + 0x2944d903, 0x99980000, 0x2990de07, 0x9fbf0000, 0xbb019998, 0xe9a0029f, 0x9b0099b3, 0x75499800, + 0x8b009db3, 0x0143fe00, 0x14bde5b2, 0xd6aa5547, 0x52494350, 0x3ea83390, 0xda005581, 0x00002990, + 0x117e1bb2, 0xa7660048, 0xda561bf4, 0x00002990, 0x7e181b90, 0xbf004811, 0x00a3f059, 0x9000a1bc, + 0xf9a61c0f, 0xda3a18f4, 0x00002990, 0x4c7e0bb2, 0xa6a60048, 0xb22a1bf4, 0x2990da0c, 0x3bb20000, + 0x7aded4bd, 0x7e000000, 0x33004674, 0x982800a4, 0x9eb30139, 0xb50c10de, 0x8b3e7541, 0x11900055, + 0x9259bf01, 0x19a63499, 0x989308f4, 0x99b37549, 0x33025f00, 0x025a002d, 0xb3744998, 0x0110009d, + 0xb3754298, 0x3e740024, 0xda0057ed, 0x00002990, 0x117e2bb2, 0xa8660048, 0xda511bf4, 0x00002990, + 0x7e022b90, 0xa600484c, 0x401bf4a7, 0xda7442b5, 0x00002990, 0xbd082b90, 0x48877e04, 0xc414bd00, + 0xfb3effa3, 0x02bc0055, 0x2990dab0, 0x00900000, 0x48877e01, 0xffa4f000, 0xa6101abc, 0xe908f403, + 0x09001033, 0xa00156b5, 0x74499856, 0x240094b3, 0x3e012290, 0xd5005625, 0x00002990, 0x87b8ff48, + 0xbd544942, 0x9259bf64, 0x29a60399, 0xff7f08f5, 0xb3744c98, 0x027800cd, 0x0057ed3e, 0x98043b98, + 0x30987449, 0xff1ac403, 0x7e0009bc, 0xb20016fc, 0x000abc2b, 0x0cb2d4bd, 0x002990da, 0x0087de00, + 0x747e0000, 0xad330046, 0xbf018700, 0x754f9829, 0xb3032c98, 0xbc2a4994, 0x90dac0cf, 0xb2000029, + 0xded4bd5b, 0x0000008c, 0x0046747e, 0x6100ad33, 0x0e5f9801, 0xbc754998, 0x49b5909f, 0x01111076, + 0xc4053f98, 0x9fa6ff19, 0x989408f4, 0x19b37641, 0xda013f00, 0x00002990, 0x877e1bb2, 0xad330048, + 0xda012f02, 0x00002990, 0x7e011b90, 0x33004887, 0x011e08ad, 0xda0140fe, 0x00002990, 0xb27c0090, + 0xbd0bb21c, 0x0090ded4, 0x747e0000, 0xad330046, 0x9800ff00, 0x56b00505, 0x050df424, 0x49fe2405, + 0x7c999001, 0x98029e98, 0x40b2019f, 0x24bd94bd, 0xb5f01fbc, 0x41fe7049, 0x30febc01, 0x3e601190, + 0xda00576c, 0x00002990, 0x3cb21bb2, 0x95ded4bd, 0x7e000000, 0x33004674, 0x3f3d00a4, 0x07339019, + 0x20012290, 0x04191809, 0x18010935, 0x09350819, 0x0c191802, 0x18030935, 0x09351019, 0x14191804, + 0x18050935, 0x09351819, 0x07009006, 0x08f425a6, 0x7042b5b5, 0xb0704198, 0x0cf42416, 0x3d24bd0b, + 0x57993e04, 0x10004900, 0x0f0091f7, 0x1100490a, 0xf8009ff7, 0xbd043d02, 0x3e34bd24, 0x980057e1, + 0x9e94714f, 0x02e9bb03, 0xb609f994, 0x9fbb06f4, 0xe0e9bc02, 0xb3904ebc, 0x3c270090, 0x94f0984e, + 0x00903302, 0xbd010a1d, 0xff0cc4b4, 0x0039cd7e, 0xff953bff, 0x9fb2a52a, 0xe2b2aeb2, 0x0010f3b2, + 0xff09c401, 0x08f491a6, 0x57f13eb9, 0xbd24bd00, 0x90008934, 0x0099ce00, 0xf50194f0, 0xbd00e10b, + 0x3ef70544, 0xc40058a0, 0x0bf50129, 0xc4bd008d, 0x4bb2d4bd, 0x137e080a, 0xa0b2001f, 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0xc0008f04, 0x00f9cf01, 0xb34c99c7, 0xb3660090, 0xf8f60190, 0x64ed3e02, + 0x00f9cf00, 0xb34c99c7, 0xb30e0090, 0xf8f60190, 0x65013e02, 0xc2008f00, 0x00ffcf01, 0x001400d9, + 0xde9abf00, 0x00000608, 0xc711f9c7, 0xe93519ff, 0x14ef3515, 0x0c014bfe, 0x10bb9008, 0x00006e7e, + 0x900149fe, 0x9fbf1899, 0x0005dcd9, 0xa699bf00, 0xa10bf5f9, 0x65ee3e00, 0x60df9000, 0x01c10089, + 0xdf009ff6, 0x800000f1, 0x010099b8, 0x009ff702, 0xb2009fcf, 0x65013e9f, 0xc2008900, 0x0099cf01, + 0xe41095b6, 0xe420009f, 0xb33fff9e, 0xff4500fd, 0x0064d43e, 0x066f448f, 0x01c10089, 0xdf009ff6, + 0x800000f1, 0x010099b8, 0x009ff702, 0xb2009fcf, 0x64bb3e9f, 0xc2008900, 0x0099cf01, 0x20009fe4, + 0x3fff94f1, 0xcc00fdb3, 0x64943efe, 0x6f408f00, 0xc1008906, 0x009ff601, 0x0000f1df, 0x0099b880, + 0x9ff70201, 0x009fcf00, 0x7b3e9fb2, 0x317e0064, 0x35fb003a, 0x64177e0c, 0x3cd97e00, 0xdf00f800, + 0x00000608, 0xf9f430f4, 0xfef0b242, 0x99900149, 0x019fb514, 0x0005dcdf, 0xbdffbf00, 0x3591a014, + 0x01030191, 0x99909320, 0xa0a43208, 0xb23c029f, 0xb2b4bd0a, 0x0b947e2c, 0x35050900, 0x03350102, + 0x08013504, 0x35090435, 0x01350201, 0x8f092003, 0xcf01c000, 0x99c700f9, 0x0099b34c, 0x90b30166, + 0x02f8f501, 0x0066533e, 0xc700f9cf, 0x99b34c99, 0xb3013900, 0xf8f50190, 0x66683e02, 0x00008f00, + 0x0394b6fe, 0xdf95f9ff, 0x00000608, 0x8f03f9b5, 0xcf01c000, 0x99c700f9, 0x0099b34c, 0x90b300ed, + 0x02f8f501, 0x0066933e, 0xc700f9cf, 0x99b34c99, 0xb300c000, 0xf8f50190, 0x66a83e02, 0x00008f00, + 0x0394b6fe, 0xdf95f9ff, 0x00000608, 0x3304f9b5, 0xd9370040, 0x0000140c, 0x008e9fbf, 0xe9cf01c0, + 0x4c99c700, 0x6a0090b3, 0xf60190b3, 0xde3e02f8, 0xf9cf0066, 0x4c99c700, 0x3a0090b3, 0xf60190b3, + 0xf23e02f8, 0x00d90066, 0xbf000014, 0x014bfe9a, 0xbb90080c, 0x006e7e14, 0x0149fe00, 0xbf1c9990, + 0x05dcd99f, 0x99bf0000, 0x0bf5f9a6, 0xe03e00ba, 0x00890067, 0x99cf01c2, 0x0608de00, 0x9fc70000, + 0x1899c710, 0x3515ef35, 0x063e14e9, 0xff900067, 0xc1008960, 0x009ff601, 0x0000f1df, 0x0099b880, + 0x9ff70201, 0x009fcf00, 0xf23e9fb2, 0x00890066, 0x99cf01c2, 0x009fe400, 0xff94f120, 0x00fdb33f, + 0xc13eff40, 0x448f0066, 0x0089066f, 0x9ff601c1, 0x00f1df00, 0x99b88000, 0xf7020100, 0x9fcf009f, + 0x3e9fb200, 0x890066a8, 0xcf01c200, 0x9fe40099, 0x94f12000, 0xfdb33fff, 0x3efec700, 0x8f006681, + 0x89066f40, 0xf601c100, 0xf1df009f, 0xb8800000, 0x02010099, 0xcf009ff7, 0x9fb2009f, 0x0066683e, + 0x003a317e, 0xf90c45fb, 0x0604d902, 0x90bf0000, 0x003cdf7e, 0xf07e010a, 0x010a0024, 0x0065ff7e, + 0x0cb2010a, 0xabb2d43d, 0x003aa97e, 0x0600a033, 0x01fb02f8, 0x0062fc7e, 0x2600a433, 0xc4bdb4bd, + 0x020ad43d, 0x003aa97e, 0xf07ea43d, 0xa43d0024, 0x0065ff7e, 0x00221d7e, 0x003ce57e, 0xf07e00f8, + 0x00f80024, 0xdfcc30f4, 0x000005dc, 0xffbf82f9, 0x900149fe, 0x48fe5499, 0xfe9fa001, 0x99920144, + 0xfef4bd10, 0x46fe0147, 0x019fb501, 0x88909fa0, 0x4c449050, 0x90347790, 0x00d92466, 0xbf000014, 0x014bfe9a, 0xbb90080c, 0x7eff0d44, 0x320000c1, 0x00a433a5, 0x1200b4e9, 0x3433033f, 0x0918e005, - 0x45203404, 0x0f009033, 0x9d33e301, 0x3e008701, 0x18007f43, 0x0b98050a, 0x78e27e02, 0x3ea13200, - 0x18007fb1, 0x2b320801, 0x817e0ab2, 0x040f000f, 0x45354320, 0x024f3503, 0x0c001033, 0x7e011433, - 0x007f863e, 0xb2020998, 0xa07bb24a, 0x08099079, 0xb5019f98, 0x9f98017f, 0x027fb502, 0xb5039998, - 0xa43e0379, 0x0f98007f, 0x08099002, 0x6bb24ab2, 0x9f986fa0, 0x016fb501, 0xb5029f98, 0x9998026f, - 0x0369b503, 0x49351409, 0x0f617e01, 0x7efa3e00, 0x320ab200, 0x0f817e2b, 0x3d050f00, 0x358f2094, - 0x00180289, 0xb2040f03, 0x018f358a, 0xbd038035, 0x0f717eb4, 0x00193300, 0x02f8ff25, 0x007efa3e, - 0x0005dcdf, 0xf4ffbf00, 0x49fefc30, 0xb39fa001, 0xb02c02b0, 0x0cf402b6, 0x01b4b30b, 0x800f3e10, - 0x03b0b300, 0x04b0b32d, 0x3e020e3f, 0xbf008051, 0x8fe43da9, 0x3e0c0000, 0xbf00803d, 0xffff8fa9, - 0xfde43df3, 0x008f049f, 0x3d3e0800, 0xa9bf0080, 0xf3ffff8f, 0x9ffde43d, 0x00008f04, 0x059ffd04, - 0x00804f3e, 0xff8fa9bf, 0xe43df3ff, 0xa0049ffd, 0x0149fea9, 0xdcd99fbf, 0xbf000005, 0xa6ea3299, - 0x070bf4f9, 0x0042e97e, 0xf80430f4, 0xfc30f400, 0xdcd252f9, 0xbf000005, 0xb2b3b229, 0xb2d5b2c4, - 0x0141fea0, 0x0880008a, 0xa0181190, 0x1c227e19, 0xb60a6000, 0x3a6010a5, 0x08802c8a, 0x001c227e, - 0xa5b64a60, 0xbf5a6010, 0xa629bf1f, 0x070bf4f9, 0x0042e97e, 0xf40455fb, 0x22f9fc30, 0x0005dcd1, - 0xb219bf00, 0x0140fea2, 0x08d5008a, 0xa00c0090, 0x1c227e09, 0xf00fbf00, 0x2aa000a3, 0xf9a619bf, - 0x7e070bf4, 0xfb0042e9, 0x30f40425, 0xd122f9fc, 0x000005dc, 0xa2b219bf, 0x8a0140fe, 0x9008d540, - 0x09a00c00, 0x001c227e, 0xa3f00fbf, 0xbf2aa000, 0xf4f9a619, 0xe97e070b, 0x25fb0042, 0xfc30f404, - 0xdcd122f9, 0xbf000005, 0xfea2b219, 0x808a0140, 0x009008d5, 0x7e09a00c, 0xbf001c22, 0x00a3f00f, - 0x19bf2aa0, 0x0bf4f9a6, 0x42e97e07, 0x0425fb00, 0xf9fc30f4, 0x05dcd122, 0x19bf0000, 0x40fea2b2, - 0xd5808a01, 0x0c009008, 0x227e09a0, 0x2aa0001c, 0x19bf0fbf, 0x0bf4f9a6, 0x42e97e07, 0x0425fb00, - 0xf9fc30f4, 0x05dcd122, 0x19bf0000, 0x40fea2b2, 0xd6408a01, 0x0c009008, 0x227e09a0, 0x2aa0001c, - 0x19bf0fbf, 0x0bf4f9a6, 0x42e97e07, 0x0425fb00, 0xf9fc30f4, 0x05dcd122, 0x19bf0000, 0x40fea2b2, - 0x88548a01, 0x0c009008, 0x227e09a0, 0x0fbf001c, 0xa000a3f0, 0xa619bf2a, 0x070bf4f9, 0x0042e97e, - 0xf40425fb, 0x42f9fc30, 0x0005dcd1, 0xb219bf00, 0xb2b2b2a3, 0x0140fec4, 0x0884ac8a, 0xa0140090, - 0x1c227e09, 0xe8a9c700, 0xa9c729a0, 0xb639a0f0, 0x4aa018a5, 0x19bf0fbf, 0x0bf4f9a6, 0x42e97e07, - 0x0445fb00, 0xdffc30f4, 0x000005dc, 0xffbf12f9, 0x900149fe, 0xa0b20899, 0xb1b29fa0, 0x0880888a, - 0x001c227e, 0xb370a9c7, 0xb01a0290, 0x0cf40296, 0x0194b30b, 0x82613e1d, 0x0390b300, 0x0494b308, - 0xc709a011, 0xa4b3b4aa, 0x9a3e1004, 0x94bd0082, 0xb43e09a0, 0xa6b00082, 0x0f0cf404, 0x1801a0b3, - 0x3002a4b3, 0x0082943e, 0x1808a0b3, 0x2410a4b3, 0x0082aa3e, 0xa43e1aa0, 0x03090082, 0x0082a23e, - 0x19a00409, 0xb63ea43d, 0x05090082, 0x0082a23e, 0x19a094bd, 0x49feff0a, 0x08999001, 0xdcd99fbf, - 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x15fb0042, 0xfc30f404, 0x0005dcdf, 0xbf02f900, 0x0149feff, - 0xb2049990, 0x8a9fa0a0, 0x7e088088, 0xc7001c22, 0xa0b370aa, 0xa6b01a02, 0x0b0cf402, 0x1801a4b3, - 0x00830c3e, 0x0803a0b3, 0x0c04a4b3, 0xa43d0aa0, 0x00831a3e, 0xff0a94bd, 0x49fe09a0, 0x04999001, - 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0xe97e070b, 0x05fb0042, 0xfc30f404, 0xdcd112f9, 0xbf000005, - 0x0140fe19, 0x08c0408a, 0xa0080090, 0x1c227e09, 0xbf0fbf00, 0x1fa4f019, 0xa60bacf0, 0x070bf4f9, - 0x0042e97e, 0xd90415fb, 0x000005dc, 0x30f499bf, 0x014ffefc, 0x357ef9a0, 0xa4330083, 0xa4bd0a00, - 0x00838f3e, 0x08d32c8a, 0x001c227e, 0xfe12aac7, 0x9fbf0149, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, - 0x0042e97e, 0xf80430f4, 0xfc30f400, 0xdcd222f9, 0xbf000005, 0xfea0b229, 0x008a0141, 0x119008d1, - 0x7e19a00c, 0x89001c22, 0xf1ff0000, 0xffffff04, 0x008ab4a9, 0x0bff08d1, 0x1cb17eb5, 0xbf1fbf00, - 0xa6a43d29, 0x070bf4f9, 0x0042e97e, 0xf40425fb, 0xdcdff830, 0xf9000005, 0xfeffbf62, 0x99900149, - 0xb29c201f, 0x01999096, 0x9fa0a432, 0xb2c4d3b2, 0x7e080aff, 0xd9001c22, 0x40000000, 0x010504bd, - 0x3e14a9ff, 0xbc008451, 0x5abca002, 0x83a97ea4, 0x0014b300, 0x449dda1d, 0x6bb20000, 0xa97e3cb2, - 0xa4330015, 0x09f80c00, 0x583e040a, 0x00900084, 0xf4402601, 0xa43dd40c, 0x900149fe, 0x9fbf2099, - 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x0042e97e, 0xf40865fb, 0xdcdff830, 0xf9000005, 0xfeffbf12, - 0x99900149, 0xa0b1b20c, 0x8aabb29f, 0x7e08c040, 0xda001cb1, 0x00008367, 0x00dcb4bd, 0x7e01312d, - 0x0e0015a9, 0x00a03304, 0x0140fe1f, 0xb2080090, 0x82d17e0a, 0x33ae3200, 0xbf0d00a4, 0xf491a609, - 0x3e0e050b, 0x900149fe, 0x9fbf0c99, 0x0005dcd9, 0x3299bf00, 0xf4f9a6ea, 0xe97e070b, 0x15fb0042, - 0xfc30f408, 0x0005dcdf, 0xbf12f900, 0x0149feff, 0xb2089990, 0xb29fa0b0, 0xd1008aa1, 0x1c227e08, - 0x00008900, 0xff04f1ff, 0xb4a9ffff, 0x08d1008a, 0x7eb50bff, 0x8a001cb1, 0xf108d170, 0xdb03ff14, - 0xc0000000, 0xff1014b6, 0xb17eb51b, 0x748a001c, 0x227e08d1, 0x0089001c, 0xa3f00201, 0x009af700, - 0x900149fe, 0x9fbf0899, 0x0005dcd9, 0x3d99bf00, 0xf4f9a6a4, 0xe97e070b, 0x15fb0042, 0xfc30f404, - 0xdcd232f9, 0xbf000005, 0x32c13229, 0xd1708ab0, 0x0000db08, 0x43fec229, 0x10339001, 0xb17e39a0, - 0x748a001c, 0x227e08d1, 0xa4f1001c, 0x02dbfff8, 0xffa22900, 0x708ab5ab, 0xb17e08d1, 0x04f0001c, - 0x0f14f0ff, 0x940c0994, 0x94f1081f, 0x708affff, 0x04b608d1, 0x0000db04, 0x04f0a22a, 0x0509fdff, - 0xfd0501fd, 0x0bff050f, 0x1cb17eb5, 0xbf3fbf00, 0xa6a43d29, 0x070bf4f9, 0x0042e97e, 0xf40435fb, - 0x72f9d430, 0xfe15f0b4, 0x99900149, 0xb5a23220, 0xf0b4019f, 0x32b43214, 0xa0d632c5, 0x05dcdf9f, - 0xffbf0000, 0xb2289990, 0xb39fa0e3, 0x3d0a00e4, 0x872d3e24, 0x3dff0000, 0x32f4bd14, 0x953fbc0e, - 0xf40194f0, 0x0e260d0b, 0x32051bf4, 0x011110f0, 0xb301ff90, 0x30ea10f4, 0x0cf41016, 0xff1fc412, - 0xbcff09c4, 0x76b070f9, 0x0b0df410, 0x020209f8, 0x00872d3e, 0xa97e3ab2, 0x5c320083, 0x4b326d32, - 0x5d7e2a32, 0x3ab20085, 0x0083a97e, 0x08d1148a, 0x001c227e, 0xffff7f49, 0x148ab4a9, 0xb17e08d1, - 0x1a32001c, 0xc43d0b32, 0xef7e640d, 0xa2320083, 0x9d00ad33, 0x7e3ab200, 0x8a0083a9, 0x7e08d114, - 0xe5001c22, 0x8a4080ab, 0x7e08d114, 0x32001cb1, 0x0c0b321a, 0x25a08d01, 0x83ef7e26, 0x33a23200, - 0xb26e00a4, 0x83a97e3a, 0xd1148a00, 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0x3e02f8f5, 0xcf00763a, 0x99c700f9, 0x0099b34c, 0x90b30125, 0x02f8f501, + 0x00764f3e, 0xffffffd9, 0xc4f9ff7f, 0x01c0008f, 0xc700f9cf, 0x99b34c99, 0xb300db00, 0xf8f50190, + 0x76703e02, 0x00f9cf00, 0xb34c99c7, 0xb30e0090, 0xf8f60190, 0x76853e02, 0xc0008f00, 0x00f9cf01, + 0xb34c99c7, 0x008d0099, 0xf50190b3, 0x9d3e02f8, 0xf9cf0076, 0x4c9dc700, 0x5e00d0b3, 0xf601d0b3, + 0xb23e02f8, 0xf9100076, 0x48e93501, 0xe100fd33, 0x0648d900, 0x4ffe0000, 0x01f9b501, 0x002e7cd9, + 0xa09abf00, 0x204809fd, 0xde0909f9, 0x00000648, 0x0409e920, 0x3502ecb5, 0x4bfe01fd, 0x03ed3501, + 0x3502ed35, 0x080c01e9, 0x00006e7e, 0x0077ad3e, 0xad3e09f8, 0x00890077, 0x99cf01c2, 0x299cde00, + 0xef180000, 0x26ff0948, 0x9d1bf4f9, 0x0077ad3e, 0x0660e08f, 0x01c10089, 0xdf009ff6, 0x800000f1, + 0x010099b8, 0x009ff702, 0xb2009fcf, 0x76b23e9f, 0x60e08f00, 0xc1008906, 0x009ff601, 0x010099b8, + 0x009cf600, 0x0000f2df, 0x0099b880, 0x9ff60202, 0x009fcf00, 0x853e9fb2, 0x00890076, 0x9fcf01c2, + 0x1ff99500, 0x8c0194b3, 0x0076643e, 0x0660e08f, 0x01c10089, 0xdf009ff6, 0x800000f1, 0x010099b8, + 0x009ff702, 0xb2009fcf, 0x764f3e9f, 0x0149fe00, 0xbf089990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, + 0x3a317e07, 0x0c30f400, 0x30f400f8, 0x05dcdff4, 0x22f90000, 0x49feffbf, 0x14999001, 0x9fa0c1b2, + 0x00299cd9, 0x019f9800, 0x00d9d2b2, 0x0e400000, 0x04f9fd08, 0x33750bf4, 0x0e1000a0, 0x01a43303, + 0x3ea0326c, 0x3d007809, 0x33040e04, 0x7e5e00b4, 0x33008a7a, 0x4b2400a0, 0x04330080, 0x884b0700, + 0x014afe00, 0xaa90080c, 0x8b2e7e0c, 0x33060e00, 0x3e3a00a4, 0xd9007883, 0x00000644, 0x080e99bf, + 0x290090b3, 0x90014ffe, 0x00330cff, 0x9e981000, 0x98fea020, 0x623e2199, 0x9e980078, 0x98fea022, + 0xf9b52399, 0x78833e01, 0x0149fe00, 0xbf149990, 0x05dcd99f, 0x99bf0000, 0xf9a6ea32, 0x3e200bf4, + 0xfe007898, 0x99900149, 0x0e9fbf0c, 0x981fa01f, 0x29a00199, 0x0078693e, 0x003a317e, 0x090c25fb, + 0x0aa9a024, 0xd900f81f, 0x0000299c, 0xf9e830f4, 0x2d9f9882, 0x98289298, 0x90982b91, 0x0df1b029, + 0x980bc1b0, 0xd1b02a9f, 0x09e1b00a, 0xbf2e9998, 0x64f2ffcc, 0xb07410ff, 0xc1b00e91, 0x0da0330c, + 0x0ea4330c, 0x78f93e10, 0xb264b200, 0x78ff3e75, 0xbd44bd00, 0x78ff3e54, 0x0d40b400, 0x090e50b4, + 0xf5b926ff, 0x9500851b, 0x4c9d015d, 0x5555d901, 0x33d05555, 0xff333333, 0xd9ffe4c9, 0xe24ebcf4, + 0xfff35fbc, 0xf994c4e0, 0x02e5b61e, 0xffe59eff, 0x0fd2d4f0, 0x950f0f0f, 0xe0ff02f1, 0xb410ffa4, + 0xbca0acbc, 0xb994b1bd, 0x04ae951c, 0xff04bf95, 0xeabce59e, 0xf1fbbce0, 0xdc04e2fd, 0x01010101, + 0xb2b4f2ff, 0x7eeab2cd, 0xb60038c2, 0xb0b318b5, 0x09090b24, 0x3300bdb3, 0x00b6b001, 0xf00b3cf0, + 0x84bd0136, 0x00799e3e, 0x0cffbac4, 0x7e240b40, 0x09008458, 0x00a93304, 0x58b20112, 0x7d9543b2, + 0x016c9d01, 0x333333d1, 0x5555d233, 0xc2ff5555, 0xf4d2ffe4, 0xbce26ebc, 0xe1fff37f, 0x1ef994c4, + 0xff02e5b6, 0xf1ffe59e, 0x0f0fd4d4, 0xf0950f0f, 0xa4e1ff02, 0xbcb401ff, 0xbdbca0ac, 0x1cb994b1, + 0x9504ae95, 0x9eff04bf, 0xe0eabce5, 0xfdf1fbbc, 0x01dc04e4, 0xff010101, 0xcdb2b4f4, 0xc27eeab2, + 0xb5950038, 0x2456b018, 0x009d0cf5, 0xb40de0b4, 0xfd950ef0, 0x01ec9d01, 0xffe4c2ff, 0xc0b4f4d2, + 0x0ed0b40d, 0xbce2cebc, 0xe1fff3df, 0x1ef994c4, 0xff02e5b6, 0xf1ffe59e, 0x02f095d4, 0xffa4e1ff, + 0xacbcb401, 0xb1bdbca0, 0x951cb994, 0xbf9504ae, 0xe59eff04, 0xbce0eabc, 0xe4fdf1fb, 0x0101dc04, + 0xf4ff0101, 0xb2cdb2b4, 0x38c27eea, 0x18b99500, 0xf42496b0, 0xd0b4320c, 0x0fffde0c, 0x004fff00, + 0x0c94b6f0, 0xfff4dfff, 0xfefdf55f, 0x0be0b404, 0xa005f9fd, 0x0af0b4ef, 0x90b4f3a0, 0x0998a009, + 0x7aa73e1f, 0x32060900, 0x1885fb9a, 0x010000d9, 0xffa4f001, 0xb6ffb4f0, 0xb4b614a4, 0xa0a9bc0f, + 0xabbc22f9, 0xb2c0b220, 0x242ab8d1, 0x277e0020, 0x0309001a, 0xb364aac7, 0x090c00a0, 0x04a0b301, + 0x20943d06, 0x142ab809, 0x277e0030, 0x0309001a, 0xb364aac7, 0x090c00a0, 0x04a0b301, 0x20943d06, + 0xf421fb19, 0xdcdff030, 0xf9000005, 0xf4ffbf32, 0x49fefc30, 0x20999001, 0x41fe9fa0, 0x9094bd01, + 0x4efe1c11, 0x9019a001, 0xe9a018ee, 0xd3b2c2b2, 0xb926ff09, 0xfe201bf4, 0x240b0140, 0xb2140090, + 0x87d77e0c, 0xffa4f000, 0x3c1fa4b3, 0x10a000bf, 0x007b6e3e, 0xf000e1b0, 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0x91a6f9bf, 0xa0091bf4, 0xab883efe, 0x01f99800, + 0x1bf491a6, 0x01feb506, 0x2ab24bb2, 0x00a60b7e, 0x130004b3, 0x90015590, 0x29988066, 0xf559a605, + 0x33fefa08, 0x98460070, 0x8db2042f, 0x2ab2e4bd, 0x0b00f1b0, 0x0070dc02, 0x41fe0000, 0x5c119001, + 0x7e0111b0, 0x9800a5e3, 0x2abf042c, 0xfb048bb2, 0x00b7477e, 0x2c981ebf, 0xbda0b204, 0xb22ab2b4, + 0xa5e57e0d, 0x0004b300, 0xbdff0406, 0xac003e04, 0x0c2a9800, 0xb2b003bc, 0x0100904c, 0x00b6727e, + 0xa60b90b4, 0xec08f409, 0xbc032f98, 0x29b59039, 0xf49fa609, 0x94bd0808, 0xbd0929b5, 0x0149fea4, + 0xbf609990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0830f400, 0xf43885fb, 0xdcd9cc30, + 0xf9000005, 0xf499bf82, 0x4ffef830, 0x5cff9001, 0xe1b0f9a0, 0xb2c8b20b, 0xb3a3b2d6, 0x028400b9, + 0x7f00e9b3, 0x2caf1802, 0xbd0141fe, 0x54119094, 0x030019a0, 0x6d00f933, 0xb2c43d02, 0xa63f7e1d, + 0xb3a0b200, 0x025e00ad, 0x68bc17bf, 0x017998f0, 0x08f59fa6, 0x7998024d, 0x0194b304, 0x3e05000a, + 0xb300aee1, 0x023e0069, 0x09027f98, 0xf5f9a6f0, 0xb2022a0b, 0xa5e97e3a, 0xb3a2b200, 0x021e00a9, + 0xb20c3c98, 0x0140fe7b, 0xb2340090, 0xa6277e0a, 0xb50ab200, 0x8bcc0570, 0xa6c07e70, 0xb3a0b200, + 0x01e900ad, 0x010d00b4, 0xf501a6f0, 0xf501ce0b, 0x3d01d00c, 0x00804cb4, 0x8c7e2ab2, 0x3abf00b7, + 0x4c070b94, 0x2db20080, 0x00b7757e, 0xb30ca1b0, 0x01b600ad, 0x18052918, 0x9476042f, 0xfff4f008, + 0x09e59fff, 0xf5e966ff, 0xe401980b, 0xa6ffffe9, 0x8e08f589, 0xbcf4bd01, 0x9918902f, 0x009d3309, + 0xff900182, 0x07f4b301, 0xaefb3ef2, 0xf28e3c00, 0x08f59f26, 0xfdc4016d, 0xff94f0ff, 0xa6529dbc, + 0x050df456, 0xd99065b2, 0xbca43d10, 0xc43db029, 0xa63ee4bd, 0xd6b100ad, 0x0cf5006f, 0x10b40145, + 0x98be3c0b, 0x26f81e3c, 0x170bf4f9, 0x39ff94f0, 0x9ffd0099, 0x00903304, 0x3c010a06, 0x010ce9bf, + 0x9001ee90, 0xe5a601dd, 0x33ce08f4, 0x00ed00c9, 0x94f0293f, 0x080bf408, 0xd000a933, 0xb294bd00, + 0x1491b03a, 0xb01391b0, 0x91301291, 0x014bfe5b, 0x7e5bbb90, 0xb200a6f8, 0x00adb3a0, 0x903400ef, + 0x0090335b, 0x7e3ab211, 0xb200a9d8, 0x00adb3a0, 0x00b400db, 0x1140b40d, 0x90014ffe, 0x2eb250ff, + 0xb0070d94, 0x804101f1, 0x0b3ab200, 0xb04cb201, 0xe37e0011, 0x0bb200a5, 0x3ab22cb2, 0x90014dfe, + 0xbd7e4cdd, 0xe0b400a4, 0xb2a0b214, 0xbd3ab21c, 0x7e0db2b4, 0xb300a5e5, 0x0091000d, 0xfe13b0b4, + 0xaa90014a, 0xa95c7e34, 0x0c3a9800, 0xfe0db0b4, 0xcc90014c, 0xb65b7e48, 0xb3a0b200, 0xb46d00a4, + 0xf0011290, 0x1bf491a6, 0x014e9832, 0xb370efcd, 0x0f0600f4, 0x06291870, 0xbcff94f0, 0x9fbb909e, + 0x0149b502, 0x00ae983e, 0x3ab20bb2, 0x3e7e2cb2, 0xa0b200a4, 0x3400a4b3, 0xfe0265bb, 0xaa90014a, + 0xa6a97e34, 0x0060b300, 0x0b90b420, 0xbc8085bc, 0x91b09095, 0xace43e0b, 0x3e020000, 0x0000aec8, + 0xaec83e03, 0x0c00b400, 0x2bb23ab2, 0x00a60b7e, 0x79b594bd, 0xaee13e05, 0x3e030000, 0x0000aee1, + 0x0149fe02, 0xbf5c9990, 0x05dcd99f, 0x99bf0000, 0xf9a60ab2, 0x3e170bf4, 0x1800af07, 0x9d330629, + 0x3efe4f00, 0x7e00aebf, 0xf4003a31, 0x85fb0830, 0xdc30f434, 0x0005dcdf, 0xbf82f900, 0xf830f4ff, + 0x900149fe, 0x9fa04c99, 0xb20bb1b0, 0xb2d4b2c2, 0xb3a5b2e6, 0x011700b9, 0x1200e9b3, 0xfe94bd01, + 0xc43d0141, 0xa0481190, 0x7e1db219, 0xb200a63f, 0x00adb3a0, 0x19bf00fb, 0x98f042bc, 0x9fa60199, + 0x00ea08f5, 0x03005ab2, 0x00a5e97e, 0xa9b3a3b2, 0xbf00de00, 0x0c5c981b, 0x900140fe, 0x0ab23000, + 0x00a6277e, 0x2bcc0ab2, 0xa6c07e70, 0xb3a8b200, 0x00ad00ad, 0xfe7021cd, 0x80420147, 0x44779000, + 0x00b0373e, 0xbd0c00b4, 0x0979a094, 0xf409a6f0, 0x0200091b, 0x00b03e3e, 0x09a6f009, 0x00090df4, + 0xb03e3e03, 0x0bc0b400, 0xbd0704b6, 0xb20db2e4, 0xb0b4bd5a, 0x71b00021, 0xa5e37e01, 0xb25abf00, + 0xb22cb20b, 0xb7757e3d, 0xb27ebf00, 0xb23bb2a0, 0xb22cb25a, 0xa5e57e0d, 0x0004b300, 0xbd3ab245, + 0xa4107eb4, 0xb3a0b200, 0x003700a4, 0x0201bb70, 0x0df404a6, 0x9040b205, 0x6ab2101b, 0xb2b03bbc, + 0xb7957e0c, 0x014afe00, 0x900240bb, 0x60bc30aa, 0xa6a97e60, 0xb314bd00, 0xff6d004d, 0x5ab280b2, + 0x0b7e3bb2, 0x4c3e00a6, 0x020000b0, 0x900149fe, 0x9fbf4c99, 0x0005dcd9, 0xb299bf00, 0xf4f9a60a, + 0x317e070b, 0x30f4003a, 0x2485fb08, 0xd9f830f4, 0x000005dc, 0x99bf32f9, 0x90014ffe, 0xa1b214ff, + 0x94bdf9a0, 0xc3b2b2b2, 0x4b0140fe, 0x00900320, 0xb209a010, 0xb79b7e0a, 0xb309bf00, 0xb34c0090, + 0xa04800a4, 0xb509bf91, 0x0fbf0192, 0xb5100049, 0x0fbf04f9, 0xf9b52009, 0xb509bf05, 0x0fbf0693, + 0xf9350109, 0x3509bf1c, 0x0fbf2c9a, 0xf9b5f009, 0x900fbf0a, 0xf9b540f9, 0x900fbf0e, 0xf9b5c0f9, + 0x3e0abf0f, 0xbd00b0e9, 0x0149fea4, 0xbf149990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, + 0x0835fb00, 0xdfd030f4, 0x000005dc, 0xffbf82f9, 0x900149fe, 0xa3b25099, 0x02059fa0, 0xf800a9b3, + 0x00b63004, 0x350b9cf0, 0x94bd2ca9, 0x7e0ca9b5, 0xb200a5e9, 0xbd3abfa0, 0x00804cb4, 0x757e0db2, + 0xa5b200b7, 0xae00adb3, 0x33093f04, 0x049f4a9d, 0x33010918, 0x0497469d, 0x33020918, 0x048f469d, + 0x33030918, 0x0487539d, 0x18040e18, 0x0f180509, 0x070d1806, 0xf0ffe4f0, 0xf4f0ff94, 0x0894b6ff, + 0xfd10f4b6, 0xd4b6059e, 0x05f9fd18, 0xf505dffd, 0x05045b0b, 0x03d6b005, 0x045a0cf5, 0xb3013db5, + 0x490e01d4, 0x39b55000, 0xb1d73e02, 0x080d1800, 0x18090918, 0x0e180a0f, 0xffd4f00b, 0xf0ff94f0, + 0x94b6fff4, 0x10f4b608, 0xb6059dfd, 0xf9fd18e4, 0x05effd05, 0xb2023eb5, 0x7e0bb23a, 0x9800a60b, + 0xff09023a, 0xa9a60305, 0x04080bf5, 0x9007a5b6, 0x3ab5303b, 0xb6ce7e03, 0xb3a5b200, 0x03f500ad, + 0x09033b98, 0x343a90c0, 0xfd3fbb90, 0xb5b604b9, 0xb79b7e03, 0xb3a5b200, 0x03d900ad, 0xfe0147fe, + 0x77900148, 0x9044bd40, 0x88900179, 0x0991b03c, 0x00b3443e, 0x8ea0e4bd, 0x0f0044b3, 0xbd0c3a98, + 0x3efe0cb4, 0xb200b267, 0xb24bb23a, 0xa5787e7c, 0xb3a5b200, 0x039d00ad, 0x94f0793f, 0x120bf401, + 0xb20c3a98, 0x7eff0c4b, 0x3e00b672, 0xb200b341, 0xa32f7e7a, 0x00a0b300, 0x0c3a980f, 0xfd0c4bb2, + 0x00b2673e, 0x94f0793f, 0x0e1bf402, 0xb20c3a98, 0x3efd0c4b, 0xb400b336, 0x3ab209b0, 0x8db2010c, + 0x00a63f7e, 0x5d00a0b3, 0x3fb2793f, 0x99c724bd, 0x01999002, 0x980a91b0, 0x54b354f5, 0xb0b43900, + 0x0022bc09, 0x02bc030c, 0x0304b600, 0x014001b8, 0x1031bc00, 0x957e1ab2, 0x30bc00b7, 0x4309b800, + 0x95200001, 0xb45302b5, 0x0fb50af0, 0x3e81a054, 0x9000b301, 0xff900122, 0x1424b318, 0xb62e3ebe, + 0x3f8ebf00, 0x027f5879, 0x98077d18, 0x3a9803ee, 0x0299c70d, 0xcc00f3f0, 0x96cb70ff, 0xcb4bb21f, + 0x010cd8e6, 0xebf0d6cb, 0x7e01e0f6, 0x9800a2e5, 0x4bb20c3a, 0x727e6cb2, 0xa5b200b6, 0xb400adb3, + 0x01449002, 0xa6033b98, 0xeb08f54b, 0xbc94bdfe, 0x89a0b0bb, 0xb17e8ab2, 0xa5b200b7, 0x9400adb3, + 0xbd37b202, 0x547f9884, 0xbc9088bc, 0x94b69098, 0x4099b803, 0x39bc0001, 0x0b91b090, 0x5300f9b3, + 0x033c9802, 0x3d0fa0b4, 0xbc24bdb4, 0x44bdc0cc, 0x00b78c7e, 0x3e0f60b4, 0x9800b45f, 0x2bb20d3a, + 0x7e0c41b0, 0x3300a2f5, 0x00b500a9, 0xfe0c3a98, 0x2bb2014c, 0x7e38cc90, 0xb300b65b, 0x020c00ad, + 0xb40be0b4, 0xef980e90, 0xd899c703, 0x1bf59fa6, 0x3a98008e, 0x0c2bb20d, 0xa2ed7e01, 0x014cfe00, + 0x2bb23ab2, 0x7e30cc90, 0xb300a593, 0x981306a4, 0x2bb20c3a, 0x727efd0c, 0x5c3e00b6, 0xadb300b4, + 0x7401cb00, 0x93f01c90, 0x9099bc00, 0x7f0069bc, 0xff19e401, 0x091bf4ff, 0x5c3e0260, 0x3a9800b4, + 0x014cfe0c, 0xffff1be4, 0x7e34cc90, 0xb300b65b, 0x019800ad, 0x343af034, 0xf9263690, 0x60100df4, + 0xff1be402, 0x0c3a98ff, 0x00b4513e, 0xb20c3a98, 0x7efd0c2b, 0xb300b672, 0x017000ad, 0x98012290, + 0x2aa6033a, 0xff3708f5, 0x6eb264b2, 0xd43db43d, 0xc4bdf4bd, 0x00b4933e, 0x9473e97f, 0x010d0a00, + 0x00b48d3e, 0x0600d033, 0xcc90010b, 0x01ff9001, 0xa602ee90, 0xe308f4fa, 0x0b00c4b3, 0x3e547cb5, + 0x3300b5cf, 0x00a600b9, 0xb0013998, 0x0cf40296, 0xb2030930, 0x5479b56d, 0xf4bde4bd, 0x00b4d23e, + 0x9073d97f, 0x697c0a00, 0x01ee90e9, 0x9001ff90, 0x399802dd, 0xf4f9a603, 0x493ee908, 0x94bd00b5, + 0x79b5f101, 0xb224bd54, 0xb5233e1b, 0xe4407f00, 0xf4ffff09, 0xf10f260b, 0x1bf4bfa6, 0xff0be40b, + 0xb51b3eff, 0x0c3a9800, 0xffff0ce4, 0x00b6727e, 0xb900adb3, 0xff0be400, 0x9019b2ff, 0x44900122, + 0x9891b202, 0x29a60339, 0x09c508f4, 0xf5b9a6f1, 0x9800a00b, 0x3c980c3a, 0xb6727e0a, 0x00adb300, + 0x31b5008c, 0xb5cf3e0a, 0xbd6f7f00, 0x01c19294, 0xf05179b5, 0x04bd00f3, 0x3e527fb5, 0x7f00b587, + 0x014c584b, 0x900c3a98, 0xb3f00100, 0x00c3f000, 0x7e024490, 0xb300b672, 0xb45200a4, 0xe9980be0, + 0x70999001, 0xa601e9b5, 0xd608f401, 0x9808607c, 0xf00c0c3a, 0xffff0be4, 0x00b6727e, 0x2d00a4b3, + 0xe4014cfe, 0xb2ffff0b, 0x40cc903a, 0x00a5787e, 0x1900a4b3, 0x98469034, 0x94f0517f, 0xf0f9bcff, + 0x3e517fb5, 0x0a00b5cf, 0x3ea5b203, 0x9000b5da, 0x77900188, 0x148db318, 0x49fefd90, 0x3c999001, + 0x457e9abf, 0xf03e00b7, 0x030500b5, 0x00b5f23e, 0x0bb204bd, 0x0b7e3ab2, 0x50b300a6, 0x3a981a00, + 0x7e04bd0c, 0x9800b6c4, 0x30b50d3a, 0xb7457e0c, 0x0d30b500, 0x900149fe, 0x9fbf5099, 0x0005dcd9, + 0xb299bf00, 0xf4f9a65a, 0x343e110b, 0x010500b6, 0x00b5f03e, 0x003a317e, 0xf93085fb, 0x7ea0b202, + 0x9800a5e7, 0xc47e0c0a, 0x0a9800b6, 0xb7457e0d, 0x7e0ab200, 0xbd00b745, 0xbf01fba4, 0x0aafb2a9, + 0xf4b9a602, 0xb9900d18, 0x98f9bc01, 0xc9a0a4bd, 0xa9bf00f8, 0x020aafb2, 0x18f4b9a6, 0x01b9900b, + 0xfcbca4bd, 0xbf00f899, 0xb2afb2b9, 0xf4c9a6ca, 0xf10a0708, 0xfbb500f8, 0xb5fca002, 0x00f801fc, + 0xaf98a9bf, 0x90b9bc02, 0xfbbfa9a0, 0x08f49ba6, 0x029bbb08, 0xa998a9a0, 0xa6aabf01, 0x051bf4a9, + 0x00f8f10a, 0x0800a0b3, 0x00b7457e, 0x30f400f8, 0x05dcdff8, 0x32f90000, 0x49feffbf, 0x14999001, + 0x9fa0a0b2, 0xa0b3b3b2, 0xfd024200, 0x0cf4a2a6, 0x01ab903a, 0xb60141fe, 0x119002b4, 0x7e1ab210, + 0xb300b7b1, 0xbf2700a4, 0xb21db219, 0xa0e4bd2c, 0x90dfbf90, 0x9eb201e9, 0xa699fcbc, 0xf408f490, + 0x3da0ddbf, 0x00b72a3e, 0x49fe020a, 0x14999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, + 0x35fb003a, 0xda00f808, 0x00002944, 0x0041c77e, 0xf000a630, 0xa6f00bac, 0x01aab901, 0x44da00f8, + 0x7e000029, 0x30004142, 0xacf000a6, 0x01a6f00b, 0xf801aab9, 0x2944da00, 0xd77e0000, 0xa6300042, + 0x0bacf000, 0xb901a6f0, 0x00f801aa, 0x7effb4f0, 0xf8000b94, 0x0b7e7e00, 0xf900f800, 0x3da0b202, + 0x384c7ea4, 0x00a6b000, 0xa00b9cf0, 0xfb9ab20a, 0xb202f901, 0x7ea43da0, 0xb000382a, 0x9cf000a6, + 0xb20aa00b, 0xf401fb9a, 0xdcdfe430, 0xf9000005, 0xfeffbf82, 0x45fe0149, 0x3c999001, 0xa00147fe, + 0x2455909f, 0xd9347790, 0x0000141c, 0x4bfe9abf, 0x90080c01, 0xff0d2cbb, 0x0000c17e, 0xeb00a433, + 0x3f0c30b4, 0x0c943339, 0x043118e2, 0x0f001033, 0xb0011933, 0x3e043d00, 0x9800b96d, 0x2cd9023f, + 0x98000014, 0x34580431, 0x3f5fa00a, 0x0339989f, 0xb5183690, 0xff090159, 0xf43379a0, 0xf77e1800, + 0xa0320032, 0x2900ad33, 0xdf010901, 0x0000142c, 0x1272f920, 0xbd0043f0, 0xb8ad3e14, 0x0241bc00, + 0x010006b1, 0x40060df4, 0x947e0100, 0x24d9000b, 0xbf000014, 0xff2ce49a, 0xb26bb2ff, 0x1300de0d, + 0x117e0000, 0x7aa000af, 0xd400adb3, 0x985bbf00, 0x1d90015c, 0x7c0eb204, 0x10bc2020, 0x1300da10, + 0x367e0000, 0xa0320021, 0xc500ad33, 0x4cb4bd00, 0x00da0100, 0xa6000013, 0xa408f414, 0x00b95c3e, + 0xd9023f98, 0x0000142c, 0x58043498, 0x5fa00a32, 0x39989f3f, 0x18389003, 0x090159b5, 0x3379a0ff, + 0x7e1600f4, 0x320032f7, 0x00ad33a0, 0x2cdf0084, 0x20000014, 0xff26e4f1, 0x3e24bdff, 0xbc00b94d, + 0x16b11262, 0x0df40100, 0x01004106, 0x000b947e, 0x5c985bbf, 0x042d9001, 0x00da1eb2, 0x7e000013, + 0xe40020d0, 0xbcffff4c, 0xa0322021, 0x1db28bb2, 0x001300de, 0x40417c00, 0x3500a433, 0x001424d9, + 0x7e9abf00, 0xa000ac3b, 0x00a4b37a, 0x4cb4bd13, 0x00da0100, 0xa6000013, 0xa608f426, 0x5c985bbf, + 0xbd7ab201, 0x7e040ed4, 0x32002136, 0x2db034a0, 0x817e3ab2, 0x0d33000f, 0x30fe7100, 0x020f3a01, + 0x1838f130, 0x04090333, 0x30014afe, 0x31303991, 0x90b4bd3b, 0x717e38aa, 0xe73e000f, 0x02f900b7, + 0x002930d9, 0xbfa0b200, 0x7e640b9a, 0x090000de, 0x00a43310, 0xa6008961, 0x009fcf02, 0x1000f5f1, + 0x8a009ff6, 0x4b02a600, 0xc4bd1000, 0xbd27104d, 0x198b7ee4, 0x00a43300, 0x2930d915, 0x9abf0000, + 0x00009b7e, 0x123e0409, 0x0ab200ba, 0x7e03e84b, 0x890016fc, 0xb802a400, 0x000200aa, 0x920aa5b6, + 0x9af601aa, 0x01114f00, 0x020099b8, 0x009ff600, 0x9a32943d, 0x000001fb, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -1809,9 +1529,9 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00005600, 0x00005625, 0x0000564a, 0x0000566f, 0x00005694, 0x000056b9, 0x000056de, 0x00005703, - 0x00005728, 0x0000574d, 0x00005772, 0x00005797, 0x000057bc, 0x000057e1, 0x00005806, 0x0000582b, - 0x00005850, 0x00005875, 0x0000c350, 0x00003e80, 0x00004e20, 0x000061a8, 0x000064b5, 0x00007d00, + 0x00004a00, 0x00004a06, 0x00004a0c, 0x00004a12, 0x00004a18, 0x00004a1e, 0x00004a24, 0x00004a2a, + 0x00004a30, 0x00004a36, 0x00004a3c, 0x00004a42, 0x00004a48, 0x00004a4e, 0x00004a54, 0x00004a5a, + 0x00004a60, 0x00004a66, 0x0000c350, 0x00003e80, 0x00004e20, 0x000061a8, 0x000064b5, 0x00007d00, 0x00009c40, 0x0000cf85, 0x4953424e, 0x004c4520, 0x00412f4e, 0x00640077, 0x64310062, 0x62347734, 0x62327732, 0x32007733, 0x00773262, 0x00773531, 0x77316236, 0x00623700, 0x64317731, 0x62347731, 0x32313000, 0x36353433, 0x41393837, 0x45444342, 0x00000046, 0x00000000, 0x00000000, 0x00000000, @@ -1823,9 +1543,9 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x000021db, 0x00002222, 0x00002253, 0x00002292, 0x00001f4e, - 0x00001f95, 0x00001fc6, 0x00002017, 0x00002088, 0x000020cf, 0x00002119, 0x0000216a, 0x00001e2a, - 0x00001e71, 0x00001ea2, 0x00001eeb, 0x0000000c, 0x00000000, 0x00000000, 0x00000013, 0x00000001, + 0x00000000, 0x00000000, 0x00000000, 0x00001d1d, 0x00001d3b, 0x00001d4d, 0x00001d65, 0x00001bb0, + 0x00001bce, 0x00001be0, 0x00001c08, 0x00001c5e, 0x00001c7c, 0x00001c9f, 0x00001cc7, 0x00001b26, + 0x00001b44, 0x00001b56, 0x00001b76, 0x0000000c, 0x00000000, 0x00000000, 0x00000013, 0x00000001, 0x00000000, 0x00000013, 0x00000001, 0x00000001, 0x00000013, 0x00000001, 0x00000002, 0x00000013, 0x00000001, 0x00000003, 0x00000013, 0x00000001, 0x00000004, 0x00000013, 0x00000001, 0x00000005, 0x00000013, 0x00000001, 0x00000006, 0x00000013, 0x00000001, 0x00000007, 0x00000013, 0x00000001, @@ -1851,7 +1571,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x09000000, 0x09400000, 0x09800000, 0x09c00000, 0x0a01c000, 0x0a404038, 0x0a804040, 0x0ac04048, 0x0b004050, 0x0b420058, 0x0b8201ab, 0x11800000, 0x11c00000, 0x12000000, 0x12400000, 0x12800000, 0x12c00000, 0x00000001, 0x00001c08, 0x00101c09, 0x00201c0a, 0x0000bd08, 0x00209d09, 0x00309d0a, - 0x00011f08, 0x00113e09, 0x00311e0a, 0x00010309, 0x00000000, 0x0000ffff, 0x00004300, 0x46020f1f, + 0x00011f08, 0x00113e09, 0x00311e0a, 0x00010309, 0x00000000, 0x0000ffff, 0x00003b00, 0x46020f1f, 0x43010f1f, 0x44020f1f, 0x45020f1f, 0x601207ef, 0x601307ef, 0x601407ef, 0x601507ef, 0x801607ef, 0x253207c2, 0x25330fc2, 0x25340fc2, 0x25350fc2, 0x1152079d, 0x1253079d, 0x7014079d, 0x7015079d, 0x601203c8, 0x601307c8, 0x601407c8, 0xbb150720, 0x02172701, 0x00000000, 0x00000000, 0x00000000, @@ -2193,9 +1913,17 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00560000, 0x00420074, 0x007f0078, 0x008c0089, 0x004200c0, 0x00dc0042, 0x00051f00, 0x35040b08, - 0x0200001d, 0x00000000, 0x00000000, 0x00000000, 0x00000c00, 0x00000000, 0x00000000, 0x00000000, - 0x00003450, 0xcab00000, 0x00010000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x004a0000, 0x003a0060, 0x00690062, 0x00720070, 0x003a00a2, 0x00b9003a, 0x00031700, 0x31030808, + 0x02000018, 0x00000000, 0x00000000, 0x00000000, 0x00000c00, 0x00000000, 0x00000000, 0x00000000, + 0x00003550, 0xc9b00000, 0x00010000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -2476,7 +2204,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000001, 0x00000002, 0x00000000, 0x00000000, 0x00003100, 0x00000000, 0x0000de00, 0x00000000, + 0x00000001, 0x00000002, 0x00000000, 0x00000000, 0x00003200, 0x00000000, 0x0000bb00, 0x00000000, 0xe4f7f5ef, 0xee6f0434, 0xa742283d, 0xb837517d, 0x49e4d804, 0xd8d4d342, 0xa7c8bf31, 0xe15c25cf, 0x3acb76c7, 0x6ca73cfc, 0xc5002b4d, 0x9dc59b12, 0x8f11945c, 0xe814622b, 0xc745df38, 0xc179824e, 0x50ed0464, 0x40f4b2de, 0x4ea86960, 0xacb935cf, 0xf1b2d5f8, 0xa4ba5e6f, 0x90a0a1eb, 0x69da0dfa, @@ -2541,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x7a9040dd, 0x0251d13c, 0x4450ac04, 0xc13389f9, 0x1f789ab9, 0x340dcaa2, 0xa6b485f7, 0xee512b70, - 0x59823fc0, 0xf12a3ca4, 0x45b67ae9, 0xd31002ea, 0x6d8e8937, 0x3b58b368, 0x0fce515f, 0x46a7c8f4, + 0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0xa1f0af45, 0xc2521354, 0x427cca67, 0x3b102336, + 0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0xcdd28e1e, 0x6000ae0f, 0x492dfb26, 0x422cf074, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -2610,30 +2338,30 @@ const NvU32 soe_ucode_header_lr10_prd[] = { /* .codeEntryPoint = */ 56832, /* .appVersion = */ 1, /* .appCodeStartOffset = */ 0, - /* .appCodeSize = */ 56832, + /* .appCodeSize = */ 47872, /* .appCodeImemOffset = */ 0, /* .appCodeIsSecure = */ 0, - /* .appDataStartOffset = */ 56832, - /* .appDataSize = */ 12544, + /* .appDataStartOffset = */ 47872, + /* .appDataSize = */ 12800, /* .appDataDmemOffset = */ 0, /* .appVersion = */ 1, - /* .appCodeStartOffset = */ 69376, + /* .appCodeStartOffset = */ 60672, /* .appCodeSize = */ 1024, /* .appCodeImemOffset = */ 56832, /* .appCodeIsSecure = */ 0, - /* .appDataStartOffset = */ 73728, + /* .appDataStartOffset = */ 65024, /* .appDataSize = */ 7424, /* .appDataDmemOffset = */ 56832, /* .appVersion = */ 1, - /* .appCodeStartOffset = */ 70400, + /* .appCodeStartOffset = */ 61696, /* .appCodeSize = */ 3328, /* .appCodeImemOffset = */ 57856, /* .appCodeIsSecure = */ 1, - /* .appDataStartOffset = */ 81152, + /* .appDataStartOffset = */ 72448, /* .appDataSize = */ 0, /* .appDataDmemOffset = */ 0, }; -const NvU32 soe_ucode_data_size_lr10_prd = 20288; +const NvU32 soe_ucode_data_size_lr10_prd = 18112; #endif //_SOE_UCODE_LR10_PRD_H_ diff --git a/src/common/nvswitch/kernel/inc/soe/haldefs_soe_nvswitch.h b/src/common/nvswitch/kernel/inc/soe/haldefs_soe_nvswitch.h index 3028282b6..2e9413948 100644 --- a/src/common/nvswitch/kernel/inc/soe/haldefs_soe_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/soe/haldefs_soe_nvswitch.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -28,6 +28,7 @@ #include "nvstatus.h" #include "flcnifcmn.h" #include "flcn/haldefs_flcnable_nvswitch.h" +#include "common_nvswitch.h" struct SOE; @@ -112,6 +113,9 @@ typedef struct { NvlStatus (*setPcieLinkSpeed)( struct nvswitch_device *device, NvU32 linkSpeed); + NvlStatus (*i2cAccess)( + struct nvswitch_device *device, + NVSWITCH_CTRL_I2C_INDEXED_PARAMS *pParams); } soe_hal; // HAL functions diff --git a/src/common/nvswitch/kernel/inc/soe/soe_nvswitch.h b/src/common/nvswitch/kernel/inc/soe/soe_nvswitch.h index d999b76f2..41d443a55 100644 --- a/src/common/nvswitch/kernel/inc/soe/soe_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/soe/soe_nvswitch.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,6 +27,7 @@ #include "nvlink_errors.h" #include "nvtypes.h" #include "nvstatus.h" +#include "common_nvswitch.h" typedef struct SOE SOE, *PSOE; struct FLCNABLE; @@ -55,5 +56,6 @@ NvlStatus soeGetPexEomStatus_HAL (struct nvswitch_device *device, NvU8 mo NvlStatus soeGetUphyDlnCfgSpace_HAL (struct nvswitch_device *device, NvU32 regAddress, NvU32 laneSelectMask, NvU16 *pRegValue); NvlStatus soeForceThermalSlowdown_HAL (struct nvswitch_device *device, NvBool slowdown, NvU32 periodUs); NvlStatus soeSetPcieLinkSpeed_HAL (struct nvswitch_device *device, NvU32 linkSpeed); +NvlStatus soeI2CAccess_HAL (struct nvswitch_device *device, NVSWITCH_CTRL_I2C_INDEXED_PARAMS *pParams); #endif //_SOE_NVSWITCH_H_ diff --git a/src/common/nvswitch/kernel/inc/soe/soe_priv_nvswitch.h b/src/common/nvswitch/kernel/inc/soe/soe_priv_nvswitch.h index 2bb172545..81419272f 100644 --- a/src/common/nvswitch/kernel/inc/soe/soe_priv_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/soe/soe_priv_nvswitch.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/common/nvswitch/kernel/inforom/ifrbbx_nvswitch.c b/src/common/nvswitch/kernel/inforom/ifrbbx_nvswitch.c index a3eca18d3..a92d9ee14 100644 --- a/src/common/nvswitch/kernel/inforom/ifrbbx_nvswitch.c +++ b/src/common/nvswitch/kernel/inforom/ifrbbx_nvswitch.c @@ -22,19 +22,8 @@ */ #include "common_nvswitch.h" -#include "regkey_nvswitch.h" -#include "nvVer.h" #include "inforom/inforom_nvswitch.h" -void -nvswitch_bbx_collect_current_time -( - nvswitch_device *device, - void *pBbxState -) -{ - return; -} NvlStatus nvswitch_inforom_bbx_add_sxid @@ -46,7 +35,15 @@ nvswitch_inforom_bbx_add_sxid NvU32 data2 ) { - return -NVL_ERR_NOT_SUPPORTED; + NvlStatus status; + + status = device->hal.nvswitch_bbx_add_sxid(device, exceptionType, data0, data1, data2); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "nvswitch_inforom_bbx_add_sxid failed, status=%d\n", status); + } + + return status; } void @@ -55,6 +52,14 @@ nvswitch_inforom_bbx_unload nvswitch_device *device ) { + NvlStatus status; + + status = device->hal.nvswitch_bbx_unload(device); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "nvswitch_inforom_bbx_unload failed, status=%d\n", status); + } + return; } @@ -64,7 +69,47 @@ nvswitch_inforom_bbx_load nvswitch_device *device ) { - return -NVL_ERR_NOT_SUPPORTED; + NvlStatus status; + NvU64 time_ns = 0; + NvU32 majorVer; + NvU32 minorVer; + NvU32 buildNum; + NvU8 osType; + NvU32 osVersion; + + osType = INFOROM_BBX_OBJ_V1_00_SYSTEM_OS_TYPE_UNIX; + + status = nvswitch_os_get_os_version(&majorVer, &minorVer, &buildNum); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to get OS version, status=%d\n", + __FUNCTION__, status); + return status; + } + + if ((majorVer > 0xff) || (minorVer > 0xff) || (buildNum > 0xffff)) + { + NVSWITCH_PRINT(device, ERROR, + "Unexpected OS versions found. majorVer: 0x%x minorVer: 0x%x buildNum: 0x%x\n", + majorVer, minorVer, buildNum); + return -NVL_ERR_NOT_SUPPORTED;; + } + + osVersion = + REF_NUM(INFOROM_BBX_OBJ_V1_00_SYSTEM_OS_MAJOR, majorVer) | + REF_NUM(INFOROM_BBX_OBJ_V1_00_SYSTEM_OS_MINOR, minorVer) | + REF_NUM(INFOROM_BBX_OBJ_V1_00_SYSTEM_OS_BUILD, buildNum); + + time_ns = nvswitch_os_get_platform_time_epoch(); + + status = device->hal.nvswitch_bbx_load(device, time_ns, osType, osVersion); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "nvswitch_inforom_bbx_load failed, status=%d\n", status); + } + + return status; } NvlStatus @@ -74,5 +119,14 @@ nvswitch_inforom_bbx_get_sxid NVSWITCH_GET_SXIDS_PARAMS *params ) { - return -NVL_ERR_NOT_SUPPORTED; + NvlStatus status; + + status = device->hal.nvswitch_bbx_get_sxid(device, params); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "nvswitch_inforom_bbx_load failed, status=%d\n", status); + } + + return status; } + diff --git a/src/common/nvswitch/kernel/inforom/inforom_nvswitch.c b/src/common/nvswitch/kernel/inforom/inforom_nvswitch.c index 4c8933572..89b666efa 100644 --- a/src/common/nvswitch/kernel/inforom/inforom_nvswitch.c +++ b/src/common/nvswitch/kernel/inforom/inforom_nvswitch.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -36,7 +36,6 @@ // Interface functions static NvlStatus _nvswitch_inforom_unpack_object(const char *, NvU8 *, NvU32 *); static NvlStatus _nvswitch_inforom_pack_object(const char *, NvU32 *, NvU8 *); -static void _nvswitch_inforom_string_copy(inforom_U008 *pSrc, NvU8 *pDst, NvU32 size); static NvlStatus _nvswitch_inforom_read_file(nvswitch_device *device, const char objectName[INFOROM_FS_FILE_NAME_SIZE], NvU32 packedObjectSize, NvU8 *pPackedObject); @@ -45,31 +44,6 @@ static NvlStatus _nvswitch_inforom_write_file(nvswitch_device *device, NvU32 packedObjectSize, NvU8 *pPackedObject); -/*! - * Interface to copy string of inforom object. - * inforom_U008 is NvU32, and we use 0xff bits to store the character. - * Therefore we need a special copy API. - * - * @param[in] pSrc Source pointer - * @param[out] pDst Destination pointer - * @param[in] length Length of the string - */ -static void -_nvswitch_inforom_string_copy -( - inforom_U008 *pSrc, - NvU8 *pDst, - NvU32 length -) -{ - NvU32 i; - - for (i = 0; i < length; ++i) - { - pDst[i] = (NvU8)(pSrc[i] & 0xff); - } -} - static NvlStatus _nvswitch_inforom_calc_packed_object_size ( @@ -337,6 +311,31 @@ _nvswitch_inforom_pack_object return NVL_SUCCESS; } +/*! + * Interface to copy string of inforom object. + * inforom_U008 is NvU32, and we use 0xff bits to store the character. + * Therefore we need a special copy API. + * + * @param[in] pSrc Source pointer + * @param[out] pDst Destination pointer + * @param[in] length Length of the string + */ +void +nvswitch_inforom_string_copy +( + inforom_U008 *pSrc, + NvU8 *pDst, + NvU32 length +) +{ + NvU32 i; + + for (i = 0; i < length; ++i) + { + pDst[i] = (NvU8)(pSrc[i] & 0xff); + } +} + /*! * Read and unpack an object from the InfoROM filesystem. * @@ -494,7 +493,7 @@ _nvswitch_inforom_read_file nvswitch_os_memset(pDmaBuf, 0, transferSize); cmdSeqDesc = 0; - nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS * 100, &timeout); + nvswitch_timeout_create(NVSWITCH_INTERVAL_750MSEC_IN_NS, &timeout); status = flcnQueueCmdPostBlocking(device, pFlcn, (PRM_FLCN_CMD)&soeCmd, NULL, NULL, SOE_RM_CMDQ_LOG_ID, &cmdSeqDesc, &timeout); if (status != NV_OK) @@ -592,7 +591,7 @@ _nvswitch_inforom_write_file } cmdSeqDesc = 0; - nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS * 100, &timeout); + nvswitch_timeout_create(NVSWITCH_INTERVAL_750MSEC_IN_NS, &timeout); status = flcnQueueCmdPostBlocking(device, pFlcn, (PRM_FLCN_CMD)&soeCmd, NULL, NULL, SOE_RM_CMDQ_LOG_ID, &cmdSeqDesc, &timeout); if (status != NV_OK) @@ -938,11 +937,11 @@ nvswitch_inforom_read_static_data { pData->OBD.bValid = NV_TRUE; pData->OBD.buildDate = (NvU32)pInforom->OBD.object.buildDate; - _nvswitch_inforom_string_copy(pInforom->OBD.object.marketingName, + nvswitch_inforom_string_copy(pInforom->OBD.object.marketingName, pData->OBD.marketingName, NV_ARRAY_ELEMENTS(pData->OBD.marketingName)); - _nvswitch_inforom_string_copy(pInforom->OBD.object.serialNumber, + nvswitch_inforom_string_copy(pInforom->OBD.object.serialNumber, pData->OBD.serialNum, NV_ARRAY_ELEMENTS(pData->OBD.serialNum)); @@ -956,7 +955,7 @@ nvswitch_inforom_read_static_data if (pInforom->OEM.bValid) { pData->OEM.bValid = NV_TRUE; - _nvswitch_inforom_string_copy(pInforom->OEM.object.oemInfo, + nvswitch_inforom_string_copy(pInforom->OEM.object.oemInfo, pData->OEM.oemInfo, NV_ARRAY_ELEMENTS(pData->OEM.oemInfo)); } @@ -964,7 +963,7 @@ nvswitch_inforom_read_static_data if (pInforom->IMG.bValid) { pData->IMG.bValid = NV_TRUE; - _nvswitch_inforom_string_copy(pInforom->IMG.object.version, + nvswitch_inforom_string_copy(pInforom->IMG.object.version, pData->IMG.inforomVer, NV_ARRAY_ELEMENTS(pData->IMG.inforomVer)); } @@ -1144,7 +1143,7 @@ nvswitch_initialize_inforom_objects status); } - status = nvswitch_inforom_dem_load(device); + status = device->hal.nvswitch_smbpbi_dem_load(device); if (status != NVL_SUCCESS) { NVSWITCH_PRINT(device, INFO, "Failed to load DEM object, rc: %d\n", diff --git a/src/common/nvswitch/kernel/lr10/inforom_lr10.c b/src/common/nvswitch/kernel/lr10/inforom_lr10.c index f0d7ff5ad..8cbd25be7 100644 --- a/src/common/nvswitch/kernel/lr10/inforom_lr10.c +++ b/src/common/nvswitch/kernel/lr10/inforom_lr10.c @@ -24,10 +24,13 @@ #include "common_nvswitch.h" #include "lr10/lr10.h" #include "lr10/inforom_lr10.h" +#include "lr10/therm_lr10.h" #include "inforom/ifrstruct.h" #include "nvswitch/lr10/dev_nvlsaw_ip.h" #include "nvswitch/lr10/dev_nvlsaw_ip_addendum.h" #include "nvswitch/lr10/dev_pmgr.h" +#include "nvVer.h" +#include "regkey_nvswitch.h" // // TODO: Split individual object hals to their own respective files @@ -744,75 +747,47 @@ nvswitch_oms_set_device_disable_lr10 _oms_update_entry_checksum(pVerData->pNext); } -NvlStatus -nvswitch_bbx_setup_prologue_lr10 -( - nvswitch_device *device, - void *pInforomBbxState -) -{ - return -NVL_ERR_NOT_SUPPORTED; -} - -NvlStatus -nvswitch_bbx_setup_epilogue_lr10 -( - nvswitch_device *device, - void *pInforomBbxState -) -{ - return -NVL_ERR_NOT_SUPPORTED; -} - -NvlStatus -nvswitch_bbx_add_data_time_lr10 -( - nvswitch_device *device, - void *pInforomBbxState, - void *pInforomBbxData -) -{ - return -NVL_ERR_NOT_SUPPORTED; -} - NvlStatus nvswitch_bbx_add_sxid_lr10 ( nvswitch_device *device, - void *pInforomBbxState, - void *pInforomBbxData + NvU32 exceptionType, + NvU32 data0, + NvU32 data1, + NvU32 data2 ) { return -NVL_ERR_NOT_SUPPORTED; } NvlStatus -nvswitch_bbx_add_temperature_lr10 +nvswitch_bbx_unload_lr10 ( - nvswitch_device *device, - void *pInforomBbxState, - void *pInforomBbxData + nvswitch_device *device ) { return -NVL_ERR_NOT_SUPPORTED; } -void -nvswitch_bbx_set_initial_temperature_lr10 -( - nvswitch_device *device, - void *pInforomBbxState, - void *pInforomBbxData -) -{ - return; -} NvlStatus -nvswitch_inforom_bbx_get_sxid_lr10 +nvswitch_bbx_load_lr10 ( nvswitch_device *device, - NVSWITCH_GET_SXIDS_PARAMS *params + NvU64 time_ns, + NvU8 osType, + NvU32 osVersion ) { return -NVL_ERR_NOT_SUPPORTED; } + +NvlStatus +nvswitch_bbx_get_sxid_lr10 +( + nvswitch_device *device, + NVSWITCH_GET_SXIDS_PARAMS * params +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + diff --git a/src/common/nvswitch/kernel/lr10/link_lr10.c b/src/common/nvswitch/kernel/lr10/link_lr10.c index ed55f1415..e5f41333f 100644 --- a/src/common/nvswitch/kernel/lr10/link_lr10.c +++ b/src/common/nvswitch/kernel/lr10/link_lr10.c @@ -399,7 +399,7 @@ nvswitch_init_dlpl_interrupts_lr10 _NVLDL_RX, _ERROR_RATE_CTRL); // Enable RX error rate short interrupt if the regkey is set - if (crcShortRegkeyVal != NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_OFF) + if (crcShortRegkeyVal != NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_DEFAULT) { shortRateMask = DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN) | DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP) | @@ -411,7 +411,7 @@ nvswitch_init_dlpl_interrupts_lr10 crcRegVal |= crcShortRegkeyVal; } // Enable RX error rate long interrupt if the regkey is set - if (crcLongRegkeyVal != NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_LONG_OFF) + if (crcLongRegkeyVal != NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_LONG_DEFAULT) { longRateMask = DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_LONG_THRESHOLD_MAN) | DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_LONG_THRESHOLD_EXP) | @@ -558,7 +558,15 @@ nvswitch_init_lpwr_regs_lr10 tempRegVal); //IC Enter Threshold - lpEntryThreshold = 16110000; + if (device->regkeys.lp_threshold == NV_SWITCH_REGKEY_SET_LP_THRESHOLD_DEFAULT) + { + // TODO: get from bios. Refer Bug 3626523 for more info. + lpEntryThreshold = 16110000; + } + else + { + lpEntryThreshold = device->regkeys.lp_threshold; + } tempRegVal = 0; tempRegVal = FLD_SET_DRF_NUM(_NVLTLC_TX_LNK, _PWRM_IC_LP_ENTER_THRESHOLD, _THRESHOLD, lpEntryThreshold, tempRegVal); @@ -2022,6 +2030,263 @@ nvswitch_execute_unilateral_link_shutdown_lr10 nvswitch_corelib_set_dl_link_mode_lr10(link, NVLINK_LINKSTATE_OFF, 0); } +static NvU32 +_nvswitch_get_nvlink_linerate_lr10 +( + nvswitch_device *device, + NvU32 val +) +{ + NvU32 lineRate = 0; + switch (val) + { + case NV_SWITCH_REGKEY_SPEED_CONTROL_SPEED_16G: + lineRate = NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_16_00000_GBPS; + break; + case NV_SWITCH_REGKEY_SPEED_CONTROL_SPEED_20G: + lineRate = NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_20_00000_GBPS; + break; + case NV_SWITCH_REGKEY_SPEED_CONTROL_SPEED_25G: + lineRate = NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_25_00000_GBPS; + break; + case NV_SWITCH_REGKEY_SPEED_CONTROL_SPEED_32G: + lineRate = NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_32_00000_GBPS; + break; + case NV_SWITCH_REGKEY_SPEED_CONTROL_SPEED_40G: + lineRate = NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_40_00000_GBPS; + break; + case NV_SWITCH_REGKEY_SPEED_CONTROL_SPEED_50G: + lineRate = NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_50_00000_GBPS; + break; + case NV_SWITCH_REGKEY_SPEED_CONTROL_SPEED_53_12500G: + lineRate = NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_53_12500_GBPS; + break; + default: + NVSWITCH_PRINT(device, SETUP, "%s:ERROR LINE_RATE = 0x%x requested by regkey\n", + __FUNCTION__, lineRate); + lineRate = NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_ILLEGAL_LINE_RATE; + } + return lineRate; +} + +void +nvswitch_setup_link_system_registers_lr10 +( + nvswitch_device *device, + nvlink_link *link +) +{ + NvU32 regval, fldval; + NvU32 lineRate = 0; + NVLINK_CONFIG_DATA_LINKENTRY *vbios_link_entry = NULL; + NVSWITCH_BIOS_NVLINK_CONFIG *bios_config; + + bios_config = nvswitch_get_bios_nvlink_config(device); + if ((bios_config == NULL) || (bios_config->bit_address == 0)) + { + NVSWITCH_PRINT(device, WARN, + "%s: VBIOS NvLink configuration table not found\n", + __FUNCTION__); + } + + // + // Identify the valid link entry to update. If not, proceed with the default settings + // + if ((bios_config == NULL) || (bios_config->bit_address == 0)) + { + NVSWITCH_PRINT(device, SETUP, + "%s: No override with VBIOS - VBIOS NvLink configuration table not found\n", + __FUNCTION__); + } + else + { + vbios_link_entry = &bios_config->link_vbios_entry[bios_config->link_base_entry_assigned][link->linkNumber]; + } + + // LINE_RATE SYSTEM register + if (device->regkeys.nvlink_speed_control != NV_SWITCH_REGKEY_SPEED_CONTROL_SPEED_DEFAULT) + { + regval = NVSWITCH_LINK_RD32_LR10(device, link->linkNumber, NVLIPT_LNK, + _NVLIPT_LNK_CTRL_SYSTEM_LINK, _CLK_CTRL); + lineRate = _nvswitch_get_nvlink_linerate_lr10(device, device->regkeys.nvlink_speed_control); + regval = FLD_SET_DRF_NUM(_NVLIPT_LNK_CTRL_SYSTEM_LINK, _CLK_CTRL, + _LINE_RATE, lineRate, regval); + NVSWITCH_PRINT(device, SETUP, "%s: LINE_RATE = 0x%x requested by regkey\n", + __FUNCTION__, lineRate); + NVSWITCH_LINK_WR32_LR10(device, link->linkNumber, NVLIPT_LNK, + _NVLIPT_LNK_CTRL_SYSTEM_LINK, _CLK_CTRL, regval); + } + + // TXTRAIN SYSTEM register + regval = NVSWITCH_LINK_RD32_LR10(device, link->linkNumber, NVLIPT_LNK, + _NVLIPT_LNK_CTRL_SYSTEM_LINK, _CHANNEL_CTRL); + + fldval = DRF_VAL(_SWITCH_REGKEY, _TXTRAIN_CONTROL, _FOM_FORMAT, + device->regkeys.txtrain_control); + if (fldval != NV_SWITCH_REGKEY_TXTRAIN_CONTROL_FOM_FORMAT_NOP) + { + NVSWITCH_PRINT(device, SETUP, "%s: FOM_FORMAT = 0x%x requested by regkey\n", + __FUNCTION__, fldval); + regval = FLD_SET_DRF_NUM(_NVLIPT_LNK_CTRL_SYSTEM_LINK, _CHANNEL_CTRL, + _TXTRAIN_FOM_FORMAT, fldval, regval); + } + else if (vbios_link_entry != NULL) + { + regval = FLD_SET_DRF_NUM(_NVLIPT_LNK, _CTRL_SYSTEM_LINK_CHANNEL_CTRL, _TXTRAIN_FOM_FORMAT, + DRF_VAL(_NVLINK_VBIOS,_PARAM5,_TXTRAIN_FOM_FORMAT, vbios_link_entry->nvLinkparam5), + regval); + } + + fldval = DRF_VAL(_SWITCH_REGKEY, _TXTRAIN_CONTROL, _OPTIMIZATION_ALGORITHM, + device->regkeys.txtrain_control); + if (fldval != NV_SWITCH_REGKEY_TXTRAIN_CONTROL_OPTIMIZATION_ALGORITHM_NOP) + { + NVSWITCH_PRINT(device, SETUP, "%s: OPTIMIZATION_ALGORITHM = 0x%x requested by regkey\n", + __FUNCTION__, fldval); + regval = FLD_SET_DRF_NUM(_NVLIPT_LNK_CTRL_SYSTEM_LINK, _CHANNEL_CTRL, + _TXTRAIN_OPTIMIZATION_ALGORITHM, fldval, regval); + } + else if (vbios_link_entry != NULL) + { + regval = FLD_SET_DRF_NUM(_NVLIPT_LNK, _CTRL_SYSTEM_LINK_CHANNEL_CTRL, _TXTRAIN_OPTIMIZATION_ALGORITHM, + vbios_link_entry->nvLinkparam4, regval); + } + + fldval = DRF_VAL(_SWITCH_REGKEY, _TXTRAIN_CONTROL, _ADJUSTMENT_ALGORITHM, + device->regkeys.txtrain_control); + if (fldval != NV_SWITCH_REGKEY_TXTRAIN_CONTROL_ADJUSTMENT_ALGORITHM_NOP) + { + NVSWITCH_PRINT(device, SETUP, "%s: ADJUSTMENT_ALGORITHM = 0x%x requested by regkey\n", + __FUNCTION__, fldval); + regval = FLD_SET_DRF_NUM(_NVLIPT_LNK_CTRL_SYSTEM_LINK, _CHANNEL_CTRL, + _TXTRAIN_ADJUSTMENT_ALGORITHM, fldval, regval); + } + else if (vbios_link_entry != NULL) + { + regval = FLD_SET_DRF_NUM(_NVLIPT_LNK, _CTRL_SYSTEM_LINK_CHANNEL_CTRL, _TXTRAIN_ADJUSTMENT_ALGORITHM, + DRF_VAL(_NVLINK_VBIOS,_PARAM5,_TXTRAIN_ADJUSTMENT_ALGORITHM, vbios_link_entry->nvLinkparam5), + regval); + } + + fldval = DRF_VAL(_SWITCH_REGKEY, _TXTRAIN_CONTROL, _MINIMUM_TRAIN_TIME_MANTISSA, + device->regkeys.txtrain_control); + if (fldval != NV_SWITCH_REGKEY_TXTRAIN_CONTROL_MINIMUM_TRAIN_TIME_MANTISSA_NOP) + { + NVSWITCH_PRINT(device, SETUP, "%s: MINIMUM_TRAIN_TIME_MANTISSA = 0x%x requested by regkey\n", + __FUNCTION__, fldval); + regval = FLD_SET_DRF_NUM(_NVLIPT_LNK_CTRL_SYSTEM_LINK, _CHANNEL_CTRL, + _TXTRAIN_MINIMUM_TRAIN_TIME_MANTISSA, fldval, regval); + } + else if (vbios_link_entry != NULL) + { + regval = FLD_SET_DRF_NUM(_NVLIPT_LNK, _CTRL_SYSTEM_LINK_CHANNEL_CTRL, _TXTRAIN_MINIMUM_TRAIN_TIME_MANTISSA, + DRF_VAL(_NVLINK_VBIOS,_PARAM6,_TXTRAIN_MINIMUM_TRAIN_TIME_MANTISSA, vbios_link_entry->nvLinkparam6), + regval); + } + + fldval = DRF_VAL(_SWITCH_REGKEY, _TXTRAIN_CONTROL, _MINIMUM_TRAIN_TIME_EXPONENT, + device->regkeys.txtrain_control); + if (fldval != NV_SWITCH_REGKEY_TXTRAIN_CONTROL_MINIMUM_TRAIN_TIME_EXPONENT_NOP) + { + NVSWITCH_PRINT(device, SETUP, "%s: MINIMUM_TRAIN_TIME_EXPONENT = 0x%x requested by regkey\n", + __FUNCTION__, fldval); + regval = FLD_SET_DRF_NUM(_NVLIPT_LNK_CTRL_SYSTEM_LINK, _CHANNEL_CTRL, + _TXTRAIN_MINIMUM_TRAIN_TIME_EXPONENT, fldval, regval); + } + else if (vbios_link_entry != NULL) + { + regval = FLD_SET_DRF_NUM(_NVLIPT_LNK, _CTRL_SYSTEM_LINK_CHANNEL_CTRL, _TXTRAIN_MINIMUM_TRAIN_TIME_EXPONENT, + DRF_VAL(_NVLINK_VBIOS,_PARAM6,_TXTRAIN_MINIMUM_TRAIN_TIME_EXPONENT, vbios_link_entry->nvLinkparam6), + regval); + } + + NVSWITCH_LINK_WR32_LR10(device, link->linkNumber, NVLIPT_LNK, + _NVLIPT_LNK_CTRL_SYSTEM_LINK, _CHANNEL_CTRL, regval); + + // Disable L2 (Bug 3176196) + regval = NVSWITCH_LINK_RD32_LR10(device, link->linkNumber, NVLIPT_LNK, _NVLIPT_LNK, _CTRL_SYSTEM_LINK_AN1_CTRL); + regval = FLD_SET_DRF(_NVLIPT_LNK, _CTRL_SYSTEM_LINK_AN1_CTRL, _PWRM_L2_ENABLE, _DISABLE, regval); + NVSWITCH_LINK_WR32_LR10(device, link->linkNumber, NVLIPT_LNK, _NVLIPT_LNK, _CTRL_SYSTEM_LINK_AN1_CTRL, regval); + + // SW WAR: Bug 3364420 + nvswitch_apply_recal_settings(device, link); + + return; +} + +void +nvswitch_load_link_disable_settings_lr10 +( + nvswitch_device *device, + nvlink_link *link +) +{ + NvU32 val; + NVLINK_CONFIG_DATA_LINKENTRY *vbios_link_entry = NULL; + NVSWITCH_BIOS_NVLINK_CONFIG *bios_config; + + bios_config = nvswitch_get_bios_nvlink_config(device); + if ((bios_config == NULL) || (bios_config->bit_address == 0)) + { + NVSWITCH_PRINT(device, WARN, + "%s: VBIOS NvLink configuration table not found\n", + __FUNCTION__); + } + + // SW CTRL - clear out LINK_DISABLE on driver load + val = NVSWITCH_LINK_RD32_LR10(device, link->linkNumber, + NVLIPT_LNK, _NVLIPT_LNK, _CTRL_SW_LINK_MODE_CTRL); + val = FLD_SET_DRF(_NVLIPT_LNK, _CTRL_SW_LINK_MODE_CTRL, _LINK_DISABLE, + _ENABLED, val); + NVSWITCH_LINK_WR32_LR10(device, link->linkNumber, + NVLIPT_LNK, _NVLIPT_LNK, _CTRL_SW_LINK_MODE_CTRL, val); + + // + // SYSTEM CTRL + // If the SYSTEM_CTRL setting had been overidden by another entity, + // it should also be locked, so this write would not take effect. + // + if (bios_config != NULL) + { + vbios_link_entry = &bios_config->link_vbios_entry[bios_config->link_base_entry_assigned][link->linkNumber]; + } + + val = NVSWITCH_LINK_RD32_LR10(device, link->linkNumber, + NVLIPT_LNK, _NVLIPT_LNK, _CTRL_SYSTEM_LINK_MODE_CTRL); + + if ((vbios_link_entry != NULL) && + (FLD_TEST_DRF(_NVLINK_VBIOS,_PARAM0, _LINK, _DISABLE, vbios_link_entry->nvLinkparam0))) + { + if (!nvswitch_is_link_in_reset(device, link)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: link #%d is not in reset, cannot set LINK_DISABLE\n", + __FUNCTION__, link->linkNumber); + return; + } + val = FLD_SET_DRF(_NVLIPT_LNK, _CTRL_SYSTEM_LINK_MODE_CTRL, _LINK_DISABLE, + _DISABLED, val); + NVSWITCH_LINK_WR32_LR10(device, link->linkNumber, + NVLIPT_LNK, _NVLIPT_LNK, _CTRL_SYSTEM_LINK_MODE_CTRL, val); + + // Set link to invalid and unregister from corelib + device->link[link->linkNumber].valid = NV_FALSE; + nvlink_lib_unregister_link(link); + nvswitch_destroy_link(link); + + return; + } + else + { + val = FLD_SET_DRF(_NVLIPT_LNK, _CTRL_SYSTEM_LINK_MODE_CTRL, _LINK_DISABLE, + _ENABLED, val); + NVSWITCH_LINK_WR32_LR10(device, link->linkNumber, + NVLIPT_LNK, _NVLIPT_LNK, _CTRL_SYSTEM_LINK_MODE_CTRL, val); + } + + return; +} + void nvswitch_reset_persistent_link_hw_state_lr10 ( @@ -2047,7 +2312,8 @@ NvlStatus nvswitch_launch_ALI_link_training_lr10 ( nvswitch_device *device, - nvlink_link *link + nvlink_link *link, + NvBool bSync ) { return NVL_ERR_NOT_IMPLEMENTED; diff --git a/src/common/nvswitch/kernel/lr10/lr10.c b/src/common/nvswitch/kernel/lr10/lr10.c index cb80bbc53..c2fbdffff 100644 --- a/src/common/nvswitch/kernel/lr10/lr10.c +++ b/src/common/nvswitch/kernel/lr10/lr10.c @@ -255,180 +255,6 @@ _nvswitch_setup_chiplib_forced_config_lr10 FOR_EACH_INDEX_IN_MASK_END; } -static NvU32 -_nvswitch_get_nvlink_linerate -( - nvswitch_device *device, - NvU32 val -) -{ - NvU32 lineRate = 0; - switch (val) - { - case NV_SWITCH_REGKEY_SPEED_CONTROL_SPEED_16G: - lineRate = NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_16_00000_GBPS; - break; - case NV_SWITCH_REGKEY_SPEED_CONTROL_SPEED_20G: - lineRate = NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_20_00000_GBPS; - break; - case NV_SWITCH_REGKEY_SPEED_CONTROL_SPEED_25G: - lineRate = NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_25_00000_GBPS; - break; - case NV_SWITCH_REGKEY_SPEED_CONTROL_SPEED_32G: - lineRate = NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_32_00000_GBPS; - break; - case NV_SWITCH_REGKEY_SPEED_CONTROL_SPEED_40G: - lineRate = NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_40_00000_GBPS; - break; - case NV_SWITCH_REGKEY_SPEED_CONTROL_SPEED_50G: - lineRate = NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_50_00000_GBPS; - break; - case NV_SWITCH_REGKEY_SPEED_CONTROL_SPEED_53_12500G: - lineRate = NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_53_12500_GBPS; - break; - default: - NVSWITCH_PRINT(device, SETUP, "%s:ERROR LINE_RATE = 0x%x requested by regkey\n", - __FUNCTION__, lineRate); - lineRate = NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_ILLEGAL_LINE_RATE; - } - return lineRate; -} - -static void -_nvswitch_setup_link_system_registers_lr10 -( - nvswitch_device *device, - NVSWITCH_BIOS_NVLINK_CONFIG *bios_config, - nvlink_link *link -) -{ - NvU32 regval, fldval; - NvU32 lineRate = 0; - NVLINK_CONFIG_DATA_LINKENTRY *vbios_link_entry = NULL; - - // - // Identify the valid link entry to update. If not, proceed with the default settings - // - if ((bios_config == NULL) || (bios_config->bit_address == 0)) - { - NVSWITCH_PRINT(device, SETUP, - "%s: No override with VBIOS - VBIOS NvLink configuration table not found\n", - __FUNCTION__); - } - else - { - vbios_link_entry = &bios_config->link_vbios_entry[bios_config->link_base_entry_assigned][link->linkNumber]; - } - - // LINE_RATE SYSTEM register - if (device->regkeys.nvlink_speed_control != NV_SWITCH_REGKEY_SPEED_CONTROL_SPEED_DEFAULT) - { - regval = NVSWITCH_LINK_RD32_LR10(device, link->linkNumber, NVLIPT_LNK, - _NVLIPT_LNK_CTRL_SYSTEM_LINK, _CLK_CTRL); - lineRate = _nvswitch_get_nvlink_linerate(device, device->regkeys.nvlink_speed_control); - regval = FLD_SET_DRF_NUM(_NVLIPT_LNK_CTRL_SYSTEM_LINK, _CLK_CTRL, - _LINE_RATE, lineRate, regval); - NVSWITCH_PRINT(device, SETUP, "%s: LINE_RATE = 0x%x requested by regkey\n", - __FUNCTION__, lineRate); - NVSWITCH_LINK_WR32_LR10(device, link->linkNumber, NVLIPT_LNK, - _NVLIPT_LNK_CTRL_SYSTEM_LINK, _CLK_CTRL, regval); - } - - // TXTRAIN SYSTEM register - regval = NVSWITCH_LINK_RD32_LR10(device, link->linkNumber, NVLIPT_LNK, - _NVLIPT_LNK_CTRL_SYSTEM_LINK, _CHANNEL_CTRL); - - fldval = DRF_VAL(_SWITCH_REGKEY, _TXTRAIN_CONTROL, _FOM_FORMAT, - device->regkeys.txtrain_control); - if (fldval != NV_SWITCH_REGKEY_TXTRAIN_CONTROL_FOM_FORMAT_NOP) - { - NVSWITCH_PRINT(device, SETUP, "%s: FOM_FORMAT = 0x%x requested by regkey\n", - __FUNCTION__, fldval); - regval = FLD_SET_DRF_NUM(_NVLIPT_LNK_CTRL_SYSTEM_LINK, _CHANNEL_CTRL, - _TXTRAIN_FOM_FORMAT, fldval, regval); - } - else if (vbios_link_entry != NULL) - { - regval = FLD_SET_DRF_NUM(_NVLIPT_LNK, _CTRL_SYSTEM_LINK_CHANNEL_CTRL, _TXTRAIN_FOM_FORMAT, - DRF_VAL(_NVLINK_VBIOS,_PARAM5,_TXTRAIN_FOM_FORMAT, vbios_link_entry->nvLinkparam5), - regval); - } - - fldval = DRF_VAL(_SWITCH_REGKEY, _TXTRAIN_CONTROL, _OPTIMIZATION_ALGORITHM, - device->regkeys.txtrain_control); - if (fldval != NV_SWITCH_REGKEY_TXTRAIN_CONTROL_OPTIMIZATION_ALGORITHM_NOP) - { - NVSWITCH_PRINT(device, SETUP, "%s: OPTIMIZATION_ALGORITHM = 0x%x requested by regkey\n", - __FUNCTION__, fldval); - regval = FLD_SET_DRF_NUM(_NVLIPT_LNK_CTRL_SYSTEM_LINK, _CHANNEL_CTRL, - _TXTRAIN_OPTIMIZATION_ALGORITHM, fldval, regval); - } - else if (vbios_link_entry != NULL) - { - regval = FLD_SET_DRF_NUM(_NVLIPT_LNK, _CTRL_SYSTEM_LINK_CHANNEL_CTRL, _TXTRAIN_OPTIMIZATION_ALGORITHM, - vbios_link_entry->nvLinkparam4, regval); - } - - fldval = DRF_VAL(_SWITCH_REGKEY, _TXTRAIN_CONTROL, _ADJUSTMENT_ALGORITHM, - device->regkeys.txtrain_control); - if (fldval != NV_SWITCH_REGKEY_TXTRAIN_CONTROL_ADJUSTMENT_ALGORITHM_NOP) - { - NVSWITCH_PRINT(device, SETUP, "%s: ADJUSTMENT_ALGORITHM = 0x%x requested by regkey\n", - __FUNCTION__, fldval); - regval = FLD_SET_DRF_NUM(_NVLIPT_LNK_CTRL_SYSTEM_LINK, _CHANNEL_CTRL, - _TXTRAIN_ADJUSTMENT_ALGORITHM, fldval, regval); - } - else if (vbios_link_entry != NULL) - { - regval = FLD_SET_DRF_NUM(_NVLIPT_LNK, _CTRL_SYSTEM_LINK_CHANNEL_CTRL, _TXTRAIN_ADJUSTMENT_ALGORITHM, - DRF_VAL(_NVLINK_VBIOS,_PARAM5,_TXTRAIN_ADJUSTMENT_ALGORITHM, vbios_link_entry->nvLinkparam5), - regval); - } - - fldval = DRF_VAL(_SWITCH_REGKEY, _TXTRAIN_CONTROL, _MINIMUM_TRAIN_TIME_MANTISSA, - device->regkeys.txtrain_control); - if (fldval != NV_SWITCH_REGKEY_TXTRAIN_CONTROL_MINIMUM_TRAIN_TIME_MANTISSA_NOP) - { - NVSWITCH_PRINT(device, SETUP, "%s: MINIMUM_TRAIN_TIME_MANTISSA = 0x%x requested by regkey\n", - __FUNCTION__, fldval); - regval = FLD_SET_DRF_NUM(_NVLIPT_LNK_CTRL_SYSTEM_LINK, _CHANNEL_CTRL, - _TXTRAIN_MINIMUM_TRAIN_TIME_MANTISSA, fldval, regval); - } - else if (vbios_link_entry != NULL) - { - regval = FLD_SET_DRF_NUM(_NVLIPT_LNK, _CTRL_SYSTEM_LINK_CHANNEL_CTRL, _TXTRAIN_MINIMUM_TRAIN_TIME_MANTISSA, - DRF_VAL(_NVLINK_VBIOS,_PARAM6,_TXTRAIN_MINIMUM_TRAIN_TIME_MANTISSA, vbios_link_entry->nvLinkparam6), - regval); - } - - fldval = DRF_VAL(_SWITCH_REGKEY, _TXTRAIN_CONTROL, _MINIMUM_TRAIN_TIME_EXPONENT, - device->regkeys.txtrain_control); - if (fldval != NV_SWITCH_REGKEY_TXTRAIN_CONTROL_MINIMUM_TRAIN_TIME_EXPONENT_NOP) - { - NVSWITCH_PRINT(device, SETUP, "%s: MINIMUM_TRAIN_TIME_EXPONENT = 0x%x requested by regkey\n", - __FUNCTION__, fldval); - regval = FLD_SET_DRF_NUM(_NVLIPT_LNK_CTRL_SYSTEM_LINK, _CHANNEL_CTRL, - _TXTRAIN_MINIMUM_TRAIN_TIME_EXPONENT, fldval, regval); - } - else if (vbios_link_entry != NULL) - { - regval = FLD_SET_DRF_NUM(_NVLIPT_LNK, _CTRL_SYSTEM_LINK_CHANNEL_CTRL, _TXTRAIN_MINIMUM_TRAIN_TIME_EXPONENT, - DRF_VAL(_NVLINK_VBIOS,_PARAM6,_TXTRAIN_MINIMUM_TRAIN_TIME_EXPONENT, vbios_link_entry->nvLinkparam6), - regval); - } - - NVSWITCH_LINK_WR32_LR10(device, link->linkNumber, NVLIPT_LNK, - _NVLIPT_LNK_CTRL_SYSTEM_LINK, _CHANNEL_CTRL, regval); - - // Disable L2 (Bug 3176196) - regval = NVSWITCH_LINK_RD32_LR10(device, link->linkNumber, NVLIPT_LNK, _NVLIPT_LNK, _CTRL_SYSTEM_LINK_AN1_CTRL); - regval = FLD_SET_DRF(_NVLIPT_LNK, _CTRL_SYSTEM_LINK_AN1_CTRL, _PWRM_L2_ENABLE, _DISABLE, regval); - NVSWITCH_LINK_WR32_LR10(device, link->linkNumber, NVLIPT_LNK, _NVLIPT_LNK, _CTRL_SYSTEM_LINK_AN1_CTRL, regval); - - // SW WAR: Bug 3364420 - nvswitch_apply_recal_settings(device, link); -} - /*! * @brief Parse packed little endian data and unpack into padded structure * @@ -1138,6 +964,7 @@ _nvswitch_vbios_fetch_nvlink_entries expected_link_entriesCount, bios_config->link_vbios_entry[base_entry_index], &bios_config->identified_Link_entries[base_entry_index]); + if (device->bIsNvlinkVbiosTableVersion2) { tblPtr += (expected_link_entriesCount * (sizeof(NVLINK_VBIOS_CONFIG_DATA_LINKENTRY_20)/sizeof(NvU32))); @@ -1270,69 +1097,6 @@ setup_link_vbios_overrides_done: return status; } -static void -_nvswitch_load_link_disable_settings_lr10 -( - nvswitch_device *device, - NVSWITCH_BIOS_NVLINK_CONFIG *bios_config, - nvlink_link *link -) -{ - NvU32 val; - NVLINK_CONFIG_DATA_LINKENTRY *vbios_link_entry = NULL; - - // SW CTRL - clear out LINK_DISABLE on driver load - val = NVSWITCH_LINK_RD32_LR10(device, link->linkNumber, - NVLIPT_LNK, _NVLIPT_LNK, _CTRL_SW_LINK_MODE_CTRL); - val = FLD_SET_DRF(_NVLIPT_LNK, _CTRL_SW_LINK_MODE_CTRL, _LINK_DISABLE, - _ENABLED, val); - NVSWITCH_LINK_WR32_LR10(device, link->linkNumber, - NVLIPT_LNK, _NVLIPT_LNK, _CTRL_SW_LINK_MODE_CTRL, val); - - // - // SYSTEM CTRL - // If the SYSTEM_CTRL setting had been overidden by another entity, - // it should also be locked, so this write would not take effect. - // - if (bios_config != NULL) - { - vbios_link_entry = &bios_config->link_vbios_entry[bios_config->link_base_entry_assigned][link->linkNumber]; - } - - val = NVSWITCH_LINK_RD32_LR10(device, link->linkNumber, - NVLIPT_LNK, _NVLIPT_LNK, _CTRL_SYSTEM_LINK_MODE_CTRL); - - if ((vbios_link_entry != NULL) && - (FLD_TEST_DRF(_NVLINK_VBIOS,_PARAM0, _LINK, _DISABLE, vbios_link_entry->nvLinkparam0))) - { - if (!nvswitch_is_link_in_reset(device, link)) - { - NVSWITCH_PRINT(device, ERROR, - "%s: link #%d is not in reset, cannot set LINK_DISABLE\n", - __FUNCTION__, link->linkNumber); - return; - } - val = FLD_SET_DRF(_NVLIPT_LNK, _CTRL_SYSTEM_LINK_MODE_CTRL, _LINK_DISABLE, - _DISABLED, val); - NVSWITCH_LINK_WR32_LR10(device, link->linkNumber, - NVLIPT_LNK, _NVLIPT_LNK, _CTRL_SYSTEM_LINK_MODE_CTRL, val); - - // Set link to invalid and unregister from corelib - device->link[link->linkNumber].valid = NV_FALSE; - nvlink_lib_unregister_link(link); - nvswitch_destroy_link(link); - - return; - } - else - { - val = FLD_SET_DRF(_NVLIPT_LNK, _CTRL_SYSTEM_LINK_MODE_CTRL, _LINK_DISABLE, - _ENABLED, val); - NVSWITCH_LINK_WR32_LR10(device, link->linkNumber, - NVLIPT_LNK, _NVLIPT_LNK, _CTRL_SYSTEM_LINK_MODE_CTRL, val); - } -} - /* * @Brief : Setting up system registers after device initialization * @@ -1341,7 +1105,7 @@ _nvswitch_load_link_disable_settings_lr10 * @param[in] device a reference to the device to initialize */ NvlStatus -nvswitch_setup_link_system_registers_lr10 +nvswitch_setup_system_registers_lr10 ( nvswitch_device *device ) @@ -1350,15 +1114,6 @@ nvswitch_setup_link_system_registers_lr10 NvU8 i; NvU32 val; NvU64 enabledLinkMask; - NVSWITCH_BIOS_NVLINK_CONFIG *bios_config; - - bios_config = nvswitch_get_bios_nvlink_config(device); - if ((bios_config == NULL) || (bios_config->bit_address == 0)) - { - NVSWITCH_PRINT(device, WARN, - "%s: VBIOS NvLink configuration table not found\n", - __FUNCTION__); - } enabledLinkMask = nvswitch_get_enabled_link_mask(device); @@ -1390,8 +1145,8 @@ nvswitch_setup_link_system_registers_lr10 _NVLIPT_LNK, _CTRL_SYSTEM_LINK_CHANNEL_CTRL, val); } - _nvswitch_setup_link_system_registers_lr10(device, bios_config, link); - _nvswitch_load_link_disable_settings_lr10(device, bios_config, link); + nvswitch_setup_link_system_registers(device, link); + nvswitch_load_link_disable_settings(device, link); } FOR_EACH_INDEX_IN_MASK_END; @@ -4672,6 +4427,121 @@ nvswitch_ctrl_get_counters_lr10 return NVL_SUCCESS; } +static void +nvswitch_ctrl_clear_throughput_counters_lr10 +( + nvswitch_device *device, + nvlink_link *link, + NvU32 counterMask +) +{ + NvU32 data; + + // TX + data = NVSWITCH_LINK_RD32_LR10(device, link->linkNumber, NVLTLC, _NVLTLC_TX_LNK, _DEBUG_TP_CNTR_CTRL); + if (counterMask & NVSWITCH_NVLINK_COUNTER_TL_TX0) + { + data = FLD_SET_DRF_NUM(_NVLTLC_TX_LNK, _DEBUG_TP_CNTR_CTRL, _RESETTX0, 0x1, data); + } + if (counterMask & NVSWITCH_NVLINK_COUNTER_TL_TX1) + { + data = FLD_SET_DRF_NUM(_NVLTLC_TX_LNK, _DEBUG_TP_CNTR_CTRL, _RESETTX1, 0x1, data); + } + NVSWITCH_LINK_WR32_LR10(device, link->linkNumber, NVLTLC, _NVLTLC_TX_LNK, _DEBUG_TP_CNTR_CTRL, data); + + // RX + data = NVSWITCH_LINK_RD32_LR10(device, link->linkNumber, NVLTLC, _NVLTLC_RX_LNK, _DEBUG_TP_CNTR_CTRL); + if (counterMask & NVSWITCH_NVLINK_COUNTER_TL_RX0) + { + data = FLD_SET_DRF_NUM(_NVLTLC_RX_LNK, _DEBUG_TP_CNTR_CTRL, _RESETRX0, 0x1, data); + } + if (counterMask & NVSWITCH_NVLINK_COUNTER_TL_RX1) + { + data = FLD_SET_DRF_NUM(_NVLTLC_RX_LNK, _DEBUG_TP_CNTR_CTRL, _RESETRX1, 0x1, data); + } + NVSWITCH_LINK_WR32_LR10(device, link->linkNumber, NVLTLC, _NVLTLC_RX_LNK, _DEBUG_TP_CNTR_CTRL, data); +} + +static NvlStatus +nvswitch_ctrl_clear_dl_error_counters_lr10 +( + nvswitch_device *device, + nvlink_link *link, + NvU32 counterMask +) +{ + NvU32 data; + + if ((!counterMask) || + (!(counterMask & (NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L0 | + NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L1 | + NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L2 | + NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L3 | + NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L4 | + NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L5 | + NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L6 | + NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L7 | + NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_ECC_COUNTS | + NVSWITCH_NVLINK_COUNTER_DL_TX_ERR_REPLAY | + NVSWITCH_NVLINK_COUNTER_DL_TX_ERR_RECOVERY)))) + { + NVSWITCH_PRINT(device, INFO, + "%s: Link%d: No error count clear request, counterMask (0x%x). Returning!\n", + __FUNCTION__, link->linkNumber, counterMask); + return NVL_SUCCESS; + } + + // With Minion initialized, send command to minion + if (nvswitch_is_minion_initialized(device, NVSWITCH_GET_LINK_ENG_INST(device, link->linkNumber, MINION))) + { + return nvswitch_minion_clear_dl_error_counters_lr10(device, link->linkNumber); + } + + // With Minion not-initialized, perform with the registers + if (counterMask & NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_FLIT) + { + data = NVSWITCH_LINK_RD32_LR10(device, link->linkNumber, NVLDL, _NVLDL_RX, _ERROR_COUNT_CTRL); + data = FLD_SET_DRF(_NVLDL_RX, _ERROR_COUNT_CTRL, _CLEAR_FLIT_CRC, _CLEAR, data); + data = FLD_SET_DRF(_NVLDL_RX, _ERROR_COUNT_CTRL, _CLEAR_RATES, _CLEAR, data); + NVSWITCH_LINK_WR32_LR10(device, link->linkNumber, NVLDL, _NVLDL_RX, _ERROR_COUNT_CTRL, data); + } + + if (counterMask & (NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L0 | + NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L1 | + NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L2 | + NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L3 | + NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L4 | + NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L5 | + NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L6 | + NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L7 | + NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_ECC_COUNTS)) + { + data = NVSWITCH_LINK_RD32_LR10(device, link->linkNumber, NVLDL, _NVLDL_RX, _ERROR_COUNT_CTRL); + data = FLD_SET_DRF(_NVLDL_RX, _ERROR_COUNT_CTRL, _CLEAR_LANE_CRC, _CLEAR, data); + data = FLD_SET_DRF(_NVLDL_RX, _ERROR_COUNT_CTRL, _CLEAR_RATES, _CLEAR, data); + if (counterMask & NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_ECC_COUNTS) + { + data = FLD_SET_DRF(_NVLDL_RX, _ERROR_COUNT_CTRL, _CLEAR_ECC_COUNTS, _CLEAR, data); + } + NVSWITCH_LINK_WR32_LR10(device, link->linkNumber, NVLDL, _NVLDL_RX, _ERROR_COUNT_CTRL, data); + } + + if (counterMask & NVSWITCH_NVLINK_COUNTER_DL_TX_ERR_REPLAY) + { + data = NVSWITCH_LINK_RD32_LR10(device, link->linkNumber, NVLDL, _NVLDL_TX, _ERROR_COUNT_CTRL); + data = FLD_SET_DRF(_NVLDL_TX, _ERROR_COUNT_CTRL, _CLEAR_REPLAY, _CLEAR, data); + NVSWITCH_LINK_WR32_LR10(device, link->linkNumber, NVLDL, _NVLDL_TX, _ERROR_COUNT_CTRL, data); + } + + if (counterMask & NVSWITCH_NVLINK_COUNTER_DL_TX_ERR_RECOVERY) + { + data = NVSWITCH_LINK_RD32_LR10(device, link->linkNumber, NVLDL, _NVLDL_TOP, _ERROR_COUNT_CTRL); + data = FLD_SET_DRF(_NVLDL_TOP, _ERROR_COUNT_CTRL, _CLEAR_RECOVERY, _CLEAR, data); + NVSWITCH_LINK_WR32_LR10(device, link->linkNumber, NVLDL, _NVLDL_TOP, _ERROR_COUNT_CTRL, data); + } + return NVL_SUCCESS; +} + /* * CTRL_NVSWITCH_GET_INFO * @@ -5327,6 +5197,547 @@ nvswitch_ctrl_get_ingress_reqlinkid_lr10 return NVL_SUCCESS; } +/* + * REGISTER_READ/_WRITE + * Provides direct access to the MMIO space for trusted clients like MODS. + * This API should not be exposed to unsecure clients. + */ + +/* + * _nvswitch_get_engine_base + * Used by REGISTER_READ/WRITE API. Looks up an engine based on device/instance + * and returns the base address in BAR0. + * + * register_rw_engine [in] REGISTER_RW_ENGINE_* + * instance [in] physical instance of device + * bcast [in] FALSE: find unicast base address + * TRUE: find broadcast base address + * base_addr [out] base address in BAR0 of requested device + * + * Returns NVL_SUCCESS: Device base address successfully found + * else device lookup failed + */ + +static NvlStatus +_nvswitch_get_engine_base_lr10 +( + nvswitch_device *device, + NvU32 register_rw_engine, // REGISTER_RW_ENGINE_* + NvU32 instance, // device instance + NvBool bcast, + NvU32 *base_addr +) +{ + NvU32 base = 0; + ENGINE_DESCRIPTOR_TYPE_LR10 *engine = NULL; + NvlStatus retval = NVL_SUCCESS; + lr10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LR10(device); + + // Find the engine descriptor matching the request + engine = NULL; + + switch (register_rw_engine) + { + case REGISTER_RW_ENGINE_RAW: + // Special case raw IO + if ((instance != 0) || + (bcast != NV_FALSE)) + { + retval = -NVL_BAD_ARGS; + } + break; + + case REGISTER_RW_ENGINE_CLKS: + case REGISTER_RW_ENGINE_FUSE: + case REGISTER_RW_ENGINE_JTAG: + case REGISTER_RW_ENGINE_PMGR: + case REGISTER_RW_ENGINE_XP3G: + // + // Legacy devices are always single-instance, unicast-only. + // These manuals are BAR0 offset-based, not IP-based. Treat them + // the same as RAW. + // + if ((instance != 0) || + (bcast != NV_FALSE)) + { + retval = -NVL_BAD_ARGS; + } + register_rw_engine = REGISTER_RW_ENGINE_RAW; + break; + + case REGISTER_RW_ENGINE_SAW: + if (bcast) + { + retval = -NVL_BAD_ARGS; + } + else + { + if (NVSWITCH_ENG_VALID_LR10(device, SAW, instance)) + { + engine = &chip_device->engSAW[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_XVE: + if (bcast) + { + retval = -NVL_BAD_ARGS; + } + else + { + if (NVSWITCH_ENG_VALID_LR10(device, XVE, instance)) + { + engine = &chip_device->engXVE[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_SOE: + if (bcast) + { + retval = -NVL_BAD_ARGS; + } + else + { + if (NVSWITCH_ENG_VALID_LR10(device, SOE, instance)) + { + engine = &chip_device->engSOE[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_SE: + if (bcast) + { + retval = -NVL_BAD_ARGS; + } + else + { + if (NVSWITCH_ENG_VALID_LR10(device, SE, instance)) + { + engine = &chip_device->engSE[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_NVLW: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LR10(device, NVLW_BCAST, instance)) + { + engine = &chip_device->engNVLW_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LR10(device, NVLW, instance)) + { + engine = &chip_device->engNVLW[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_MINION: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LR10(device, MINION_BCAST, instance)) + { + engine = &chip_device->engMINION_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LR10(device, MINION, instance)) + { + engine = &chip_device->engMINION[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_NVLIPT: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LR10(device, NVLIPT_BCAST, instance)) + { + engine = &chip_device->engNVLIPT_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LR10(device, NVLIPT, instance)) + { + engine = &chip_device->engNVLIPT[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_NVLTLC: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LR10(device, NVLTLC_BCAST, instance)) + { + engine = &chip_device->engNVLTLC_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LR10(device, NVLTLC, instance)) + { + engine = &chip_device->engNVLTLC[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_NVLTLC_MULTICAST: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LR10(device, NVLTLC_MULTICAST_BCAST, instance)) + { + engine = &chip_device->engNVLTLC_MULTICAST_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LR10(device, NVLTLC_MULTICAST, instance)) + { + engine = &chip_device->engNVLTLC_MULTICAST[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_NPG: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LR10(device, NPG_BCAST, instance)) + { + engine = &chip_device->engNPG_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LR10(device, NPG, instance)) + { + engine = &chip_device->engNPG[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_NPORT: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LR10(device, NPORT_BCAST, instance)) + { + engine = &chip_device->engNPORT_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LR10(device, NPORT, instance)) + { + engine = &chip_device->engNPORT[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_NPORT_MULTICAST: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LR10(device, NPORT_MULTICAST_BCAST, instance)) + { + engine = &chip_device->engNPORT_MULTICAST_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LR10(device, NPORT_MULTICAST, instance)) + { + engine = &chip_device->engNPORT_MULTICAST[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_NVLIPT_LNK: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LR10(device, NVLIPT_LNK_BCAST, instance)) + { + engine = &chip_device->engNVLIPT_LNK_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LR10(device, NVLIPT_LNK, instance)) + { + engine = &chip_device->engNVLIPT_LNK[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_NVLIPT_LNK_MULTICAST: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LR10(device, NVLIPT_LNK_MULTICAST_BCAST, instance)) + { + engine = &chip_device->engNVLIPT_LNK_MULTICAST_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LR10(device, NVLIPT_LNK_MULTICAST, instance)) + { + engine = &chip_device->engNVLIPT_LNK_MULTICAST[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_PLL: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LR10(device, PLL_BCAST, instance)) + { + engine = &chip_device->engPLL_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LR10(device, PLL, instance)) + { + engine = &chip_device->engPLL[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_NVLDL: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LR10(device, NVLDL_BCAST, instance)) + { + engine = &chip_device->engNVLDL_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LR10(device, NVLDL, instance)) + { + engine = &chip_device->engNVLDL[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_NVLDL_MULTICAST: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LR10(device, NVLDL_MULTICAST_BCAST, instance)) + { + engine = &chip_device->engNVLDL_MULTICAST_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LR10(device, NVLDL_MULTICAST, instance)) + { + engine = &chip_device->engNVLDL_MULTICAST[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_NXBAR: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LR10(device, NXBAR_BCAST, instance)) + { + engine = &chip_device->engNXBAR_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LR10(device, NXBAR, instance)) + { + engine = &chip_device->engNXBAR[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_TILE: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LR10(device, TILE_BCAST, instance)) + { + engine = &chip_device->engTILE_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LR10(device, TILE, instance)) + { + engine = &chip_device->engTILE[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_TILE_MULTICAST: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LR10(device, TILE_MULTICAST_BCAST, instance)) + { + engine = &chip_device->engTILE_MULTICAST_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LR10(device, TILE_MULTICAST, instance)) + { + engine = &chip_device->engTILE_MULTICAST[instance]; + } + } + break; + + default: + NVSWITCH_PRINT(device, ERROR, + "%s: unknown REGISTER_RW_ENGINE 0x%x\n", + __FUNCTION__, + register_rw_engine); + engine = NULL; + break; + } + + if (register_rw_engine == REGISTER_RW_ENGINE_RAW) + { + // Raw IO -- client provides full BAR0 offset + base = 0; + } + else + { + // Check engine descriptor was found and valid + if (engine == NULL) + { + retval = -NVL_BAD_ARGS; + NVSWITCH_PRINT(device, ERROR, + "%s: invalid REGISTER_RW_ENGINE/instance 0x%x(%d)\n", + __FUNCTION__, + register_rw_engine, + instance); + } + else if (!engine->valid) + { + retval = -NVL_UNBOUND_DEVICE; + NVSWITCH_PRINT(device, ERROR, + "%s: REGISTER_RW_ENGINE/instance 0x%x(%d) disabled or invalid\n", + __FUNCTION__, + register_rw_engine, + instance); + } + else + { + if (bcast && (engine->disc_type == DISCOVERY_TYPE_BROADCAST)) + { + // + // Caveat emptor: A read of a broadcast register is + // implementation-specific. + // + base = engine->info.bc.bc_addr; + } + else if ((!bcast) && (engine->disc_type == DISCOVERY_TYPE_UNICAST)) + { + base = engine->info.uc.uc_addr; + } + + if (base == 0) + { + NVSWITCH_PRINT(device, ERROR, + "%s: REGISTER_RW_ENGINE/instance 0x%x(%d) has %s base address 0!\n", + __FUNCTION__, + register_rw_engine, + instance, + (bcast ? "BCAST" : "UNICAST" )); + retval = -NVL_IO_ERROR; + } + } + } + + *base_addr = base; + return retval; +} + +/* + * CTRL_NVSWITCH_REGISTER_READ + * + * This provides direct access to the MMIO space for trusted clients like + * MODS. + * This API should not be exposed to unsecure clients. + */ + +static NvlStatus +nvswitch_ctrl_register_read_lr10 +( + nvswitch_device *device, + NVSWITCH_REGISTER_READ *p +) +{ + NvU32 base; + NvU32 data; + NvlStatus retval = NVL_SUCCESS; + + retval = _nvswitch_get_engine_base_lr10(device, p->engine, p->instance, NV_FALSE, &base); + if (retval != NVL_SUCCESS) + { + return retval; + } + + // Make sure target offset isn't out-of-range + if ((base + p->offset) >= device->nvlink_device->pciInfo.bars[0].barSize) + { + return -NVL_IO_ERROR; + } + + // + // Some legacy device manuals are not 0-based (IP style). + // + data = NVSWITCH_OFF_RD32(device, base + p->offset); + p->val = data; + + return NVL_SUCCESS; +} + +/* + * CTRL_NVSWITCH_REGISTER_WRITE + * + * This provides direct access to the MMIO space for trusted clients like + * MODS. + * This API should not be exposed to unsecure clients. + */ + +static NvlStatus +nvswitch_ctrl_register_write_lr10 +( + nvswitch_device *device, + NVSWITCH_REGISTER_WRITE *p +) +{ + NvU32 base; + NvlStatus retval = NVL_SUCCESS; + + retval = _nvswitch_get_engine_base_lr10(device, p->engine, p->instance, p->bcast, &base); + if (retval != NVL_SUCCESS) + { + return retval; + } + + // Make sure target offset isn't out-of-range + if ((base + p->offset) >= device->nvlink_device->pciInfo.bars[0].barSize) + { + return -NVL_IO_ERROR; + } + + // + // Some legacy device manuals are not 0-based (IP style). + // + NVSWITCH_OFF_WR32(device, base + p->offset, p->val); + + return NVL_SUCCESS; +} + NvlStatus nvswitch_ctrl_get_bios_info_lr10 ( @@ -5364,8 +5775,37 @@ nvswitch_ctrl_get_bios_info_lr10 return NVL_SUCCESS; } -static void -_nvlink_clear_corelib_state +NvlStatus +nvswitch_ctrl_get_inforom_version_lr10 +( + nvswitch_device *device, + NVSWITCH_GET_INFOROM_VERSION_PARAMS *p +) +{ + + struct inforom *pInforom = device->pInforom; + + if ((pInforom == NULL) || (!pInforom->IMG.bValid)) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + if (NV_ARRAY_ELEMENTS(pInforom->IMG.object.version) < + NVSWITCH_INFOROM_VERSION_LEN) + { + NVSWITCH_PRINT(device, ERROR, + "Inforom IMG object struct smaller than expected\n"); + return -NVL_ERR_INVALID_STATE; + } + + nvswitch_inforom_string_copy(pInforom->IMG.object.version, p->version, + NVSWITCH_INFOROM_VERSION_LEN); + + return NVL_SUCCESS; +} + +void +nvswitch_corelib_clear_link_state_lr10 ( nvlink_link *link ) @@ -5699,7 +6139,7 @@ nvswitch_reset_and_drain_links_lr10 (rx_sublink_mode == NVLINK_SUBLINK_STATE_RX_OFF)))) { nvswitch_execute_unilateral_link_shutdown_lr10(link_info); - _nvlink_clear_corelib_state(link_info); + nvswitch_corelib_clear_link_state_lr10(link_info); } // @@ -6278,7 +6718,21 @@ nvswitch_is_spi_supported_lr10 nvswitch_device *device ) { - return nvswitch_is_soe_supported(device); + if (IS_RTLSIM(device) || IS_EMULATION(device) || IS_FMODEL(device)) + { + NVSWITCH_PRINT(device, INFO, + "SPI is not supported on non-silicon platforms\n"); + return NV_FALSE; + } + + if (!nvswitch_is_soe_supported(device)) + { + NVSWITCH_PRINT(device, INFO, + "SPI is not supported since SOE is not supported\n"); + return NV_FALSE; + } + + return NV_TRUE; } NvBool @@ -6778,8 +7232,6 @@ nvswitch_get_link_eng_inst_lr10 case NVSWITCH_ENGINE_ID_NVLDL: case NVSWITCH_ENGINE_ID_NVLIPT_LNK: case NVSWITCH_ENGINE_ID_NPORT_PERFMON: - case NVSWITCH_ENGINE_ID_RX_PERFMON: - case NVSWITCH_ENGINE_ID_TX_PERFMON: eng_instance = link_id; break; default: @@ -6891,6 +7343,26 @@ nvswitch_ctrl_clear_multicast_id_error_vector_lr10 return -NVL_ERR_NOT_SUPPORTED; } +void +nvswitch_send_inband_nack_lr10 +( + nvswitch_device *device, + NvU32 *msghdr, + NvU32 linkId +) +{ + return; +} + +NvU32 +nvswitch_get_max_persistent_message_count_lr10 +( + nvswitch_device *device +) +{ + return 0; +} + /* * CTRL_NVSWITCH_INBAND_SEND_DATA */ @@ -7017,6 +7489,24 @@ NvlStatus nvswitch_ctrl_get_fatal_error_scope_lr10 return NVL_SUCCESS; } +NvlStatus nvswitch_ctrl_set_mc_rid_table_lr10 +( + nvswitch_device *device, + NVSWITCH_SET_MC_RID_TABLE_PARAMS *p +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +NvlStatus nvswitch_ctrl_get_mc_rid_table_lr10 +( + nvswitch_device *device, + NVSWITCH_GET_MC_RID_TABLE_PARAMS *p +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + void nvswitch_init_scratch_lr10 ( nvswitch_device *device @@ -7146,6 +7636,151 @@ nvswitch_ctrl_get_sw_info_lr10 return retval; } +NvlStatus +nvswitch_ctrl_get_err_info_lr10 +( + nvswitch_device *device, + NVSWITCH_NVLINK_GET_ERR_INFO_PARAMS *ret +) +{ + nvlink_link *link; + NvU32 data; + NvU8 i; + + ret->linkMask = nvswitch_get_enabled_link_mask(device); + + FOR_EACH_INDEX_IN_MASK(64, i, ret->linkMask) + { + link = nvswitch_get_link(device, i); + + if ((link == NULL) || + !NVSWITCH_IS_LINK_ENG_VALID_LR10(device, NVLDL, link->linkNumber) || + (i >= NVSWITCH_NVLINK_MAX_LINKS)) + { + continue; + } + + // TODO NVidia TL not supported + NVSWITCH_PRINT(device, WARN, + "%s WARNING: Nvidia %s register %s does not exist!\n", + __FUNCTION__, "NVLTL", "NV_NVLTL_TL_ERRLOG_REG"); + + NVSWITCH_PRINT(device, WARN, + "%s WARNING: Nvidia %s register %s does not exist!\n", + __FUNCTION__, "NVLTL", "NV_NVLTL_TL_INTEN_REG"); + + ret->linkErrInfo[i].TLErrlog = 0x0; + ret->linkErrInfo[i].TLIntrEn = 0x0; + + data = NVSWITCH_LINK_RD32_LR10(device, link->linkNumber, NVLDL, _NVLDL_TX, _SLSM_STATUS_TX); + ret->linkErrInfo[i].DLSpeedStatusTx = + DRF_VAL(_NVLDL_TX, _SLSM_STATUS_TX, _PRIMARY_STATE, data); + + data = NVSWITCH_LINK_RD32_LR10(device, link->linkNumber, NVLDL, _NVLDL_RX, _SLSM_STATUS_RX); + ret->linkErrInfo[i].DLSpeedStatusRx = + DRF_VAL(_NVLDL_RX, _SLSM_STATUS_RX, _PRIMARY_STATE, data); + + data = NVSWITCH_LINK_RD32_LR10(device, link->linkNumber, NVLDL, _NVLDL_TOP, _INTR); + ret->linkErrInfo[i].bExcessErrorDL = + !!DRF_VAL(_NVLDL_TOP, _INTR, _RX_SHORT_ERROR_RATE, data); + + if (ret->linkErrInfo[i].bExcessErrorDL) + { + NVSWITCH_LINK_WR32_LR10(device, link->linkNumber, NVLDL, _NVLDL_TOP, _INTR, + DRF_NUM(_NVLDL_TOP, _INTR, _RX_SHORT_ERROR_RATE, 0x1)); + } + } + FOR_EACH_INDEX_IN_MASK_END; + + return NVL_SUCCESS; +} + +static NvlStatus +nvswitch_ctrl_clear_counters_lr10 +( + nvswitch_device *device, + NVSWITCH_NVLINK_CLEAR_COUNTERS_PARAMS *ret +) +{ + nvlink_link *link; + NvU8 i; + NvU32 counterMask; + NvlStatus status = NVL_SUCCESS; + + counterMask = ret->counterMask; + + // Common usage allows one of these to stand for all of them + if ((counterMask) & ( NVSWITCH_NVLINK_COUNTER_TL_TX0 + | NVSWITCH_NVLINK_COUNTER_TL_TX1 + | NVSWITCH_NVLINK_COUNTER_TL_RX0 + | NVSWITCH_NVLINK_COUNTER_TL_RX1 + )) + { + counterMask |= ( NVSWITCH_NVLINK_COUNTER_TL_TX0 + | NVSWITCH_NVLINK_COUNTER_TL_TX1 + | NVSWITCH_NVLINK_COUNTER_TL_RX0 + | NVSWITCH_NVLINK_COUNTER_TL_RX1 + ); + } + + // Common usage allows one of these to stand for all of them + if ((counterMask) & ( NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_FLIT + | NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L0 + | NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L1 + | NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L2 + | NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L3 + | NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L4 + | NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L5 + | NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L6 + | NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L7 + | NVSWITCH_NVLINK_COUNTER_DL_TX_ERR_REPLAY + | NVSWITCH_NVLINK_COUNTER_DL_TX_ERR_RECOVERY + )) + { + counterMask |= ( NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_FLIT + | NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L0 + | NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L1 + | NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L2 + | NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L3 + | NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L4 + | NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L5 + | NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L6 + | NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L7 + | NVSWITCH_NVLINK_COUNTER_DL_TX_ERR_REPLAY + | NVSWITCH_NVLINK_COUNTER_DL_TX_ERR_RECOVERY + ); + } + + FOR_EACH_INDEX_IN_MASK(64, i, ret->linkMask) + { + link = nvswitch_get_link(device, i); + if (link == NULL) + { + continue; + } + + if (NVSWITCH_IS_LINK_ENG_VALID_LR10(device, NVLTLC, link->linkNumber)) + { + nvswitch_ctrl_clear_throughput_counters_lr10(device, link, counterMask); + } + if (NVSWITCH_IS_LINK_ENG_VALID_LR10(device, NVLDL, link->linkNumber)) + { + status = nvswitch_ctrl_clear_dl_error_counters_lr10(device, link, counterMask); + // Return early with failure on clearing through minion + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failure on clearing link counter mask 0x%x on link %d\n", + __FUNCTION__, counterMask, link->linkNumber); + break; + } + } + } + FOR_EACH_INDEX_IN_MASK_END; + + return status; +} + // // This function auto creates the lr10 HAL connectivity from the NVSWITCH_INIT_HAL // macro in haldef_nvswitch.h diff --git a/src/common/nvswitch/kernel/lr10/smbpbi_lr10.c b/src/common/nvswitch/kernel/lr10/smbpbi_lr10.c index 560b633e8..1410480c6 100644 --- a/src/common/nvswitch/kernel/lr10/smbpbi_lr10.c +++ b/src/common/nvswitch/kernel/lr10/smbpbi_lr10.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,6 +27,163 @@ #include "nvswitch/lr10/dev_nvlsaw_ip.h" #include "nvswitch/lr10/dev_nvlsaw_ip_addendum.h" +#include "flcn/flcn_nvswitch.h" +#include "rmflcncmdif_nvswitch.h" + +#define GET_PFIFO_FROM_DEVICE(dev) (&(dev)->pSmbpbi->sharedSurface->inforomObjects.DEM.object.v1) + +#define DEM_FIFO_SIZE INFOROM_DEM_OBJECT_V1_00_FIFO_SIZE +#define DEM_FIFO_PTR(x) ((x) % DEM_FIFO_SIZE) +#define DEM_PTR_DIFF(cur, next) (((next) > (cur)) ? ((next) - (cur)) : \ + (DEM_FIFO_SIZE - ((cur) - (next)))) +#define DEM_BYTES_OCCUPIED(pf) DEM_PTR_DIFF((pf)->readOffset, (pf)->writeOffset) +// +// See how much space is available in the FIFO. +// Must leave 1 word free so the write pointer does not +// catch up with the read pointer. That would be indistinguishable +// from an empty FIFO. +// +#define DEM_BYTES_AVAILABLE(pf) (DEM_PTR_DIFF((pf)->writeOffset, (pf)->readOffset) - \ + sizeof(NvU32)) +#define DEM_RECORD_SIZE_MAX (sizeof(NV_MSGBOX_DEM_RECORD) \ + + NV_MSGBOX_MAX_DRIVER_EVENT_MSG_TXT_SIZE) +#define DEM_RECORD_SIZE_MIN (sizeof(NV_MSGBOX_DEM_RECORD) + 1) + +#define FIFO_REC_LOOP_ITERATOR _curPtr +#define FIFO_REC_LOOP_REC_PTR _recPtr +#define FIFO_REC_LOOP_REC_SIZE _recSize +#define FIFO_REC_LOOP_START(pf, cond) \ +{ \ + NvU16 _nextPtr; \ + for (FIFO_REC_LOOP_ITERATOR = (pf)->readOffset; cond; FIFO_REC_LOOP_ITERATOR = _nextPtr) \ + { \ + NV_MSGBOX_DEM_RECORD *FIFO_REC_LOOP_REC_PTR = (NV_MSGBOX_DEM_RECORD *) \ + ((pf)->fifoBuffer + FIFO_REC_LOOP_ITERATOR); \ + NvU16 FIFO_REC_LOOP_REC_SIZE = \ + FIFO_REC_LOOP_REC_PTR->recordSize * sizeof(NvU32); + +#define FIFO_REC_LOOP_END \ + _nextPtr = DEM_FIFO_PTR(FIFO_REC_LOOP_ITERATOR + FIFO_REC_LOOP_REC_SIZE); \ + } \ +} + +static void _smbpbiDemInit(nvswitch_device *device, struct smbpbi *pSmbpbi, struct INFOROM_DEM_OBJECT_V1_00 *pFifo); + +NvlStatus +nvswitch_smbpbi_alloc_lr10 +( + nvswitch_device *device +) +{ + NV_STATUS status; + NvU64 dmaHandle; + void *cpuAddr; + + // Create DMA mapping for SMBPBI transactions + status = nvswitch_os_alloc_contig_memory(device->os_handle, &cpuAddr, + sizeof(SOE_SMBPBI_SHARED_SURFACE), + (device->dma_addr_width == 32)); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "Failed to allocate contig memory, rc:%d\n", + status); + return status; + } + + nvswitch_os_memset(cpuAddr, 0, sizeof(SOE_SMBPBI_SHARED_SURFACE)); + + status = nvswitch_os_map_dma_region(device->os_handle, cpuAddr, &dmaHandle, + sizeof(SOE_SMBPBI_SHARED_SURFACE), + NVSWITCH_DMA_DIR_BIDIRECTIONAL); + if (status == NVL_SUCCESS) + { + device->pSmbpbi->sharedSurface = cpuAddr; + device->pSmbpbi->dmaHandle = dmaHandle; + } + else + { + NVSWITCH_PRINT(device, ERROR, + "Failed to map dma region for SMBPBI shared surface, rc:%d\n", + status); + nvswitch_os_free_contig_memory(device->os_handle, cpuAddr, sizeof(SOE_SMBPBI_SHARED_SURFACE)); + } + + return status; +} + +NvlStatus +nvswitch_smbpbi_post_init_hal_lr10 +( + nvswitch_device *device +) +{ + struct smbpbi *pSmbpbi = device->pSmbpbi; + FLCN *pFlcn; + NvU64 dmaHandle; + RM_FLCN_CMD_SOE cmd; + NVSWITCH_TIMEOUT timeout; + NvU32 cmdSeqDesc; + RM_SOE_SMBPBI_CMD_INIT *pInitCmd = &cmd.cmd.smbpbiCmd.init; + NvlStatus status; + + if (!device->pInforom || !device->pSmbpbi->sharedSurface) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + // Populate shared surface with static InfoROM data + nvswitch_inforom_read_static_data(device, device->pInforom, + &device->pSmbpbi->sharedSurface->inforomObjects); + + pFlcn = device->pSoe->pFlcn; + dmaHandle = pSmbpbi->dmaHandle; + + nvswitch_os_memset(&cmd, 0, sizeof(cmd)); + cmd.hdr.unitId = RM_SOE_UNIT_SMBPBI; + cmd.hdr.size = RM_SOE_CMD_SIZE(SMBPBI, INIT); + cmd.cmd.smbpbiCmd.cmdType = RM_SOE_SMBPBI_CMD_ID_INIT; + RM_FLCN_U64_PACK(&pInitCmd->dmaHandle, &dmaHandle); + + // + // Make the interval twice the heartbeat period to avoid + // skew between driver and soe threads + // + pInitCmd->driverPollingPeriodUs = (NVSWITCH_HEARTBEAT_INTERVAL_NS / 1000) * 2; + + nvswitch_timeout_create(NVSWITCH_INTERVAL_1SEC_IN_NS, &timeout); + status = flcnQueueCmdPostBlocking(device, pFlcn, + (PRM_FLCN_CMD)&cmd, + NULL, // pMsg - not used for now + NULL, // pPayload - not used for now + SOE_RM_CMDQ_LOG_ID, + &cmdSeqDesc, + &timeout); + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, "%s: SMBPBI Init command failed. rc:%d\n", + __FUNCTION__, status); + } + + return status; +} + +void +nvswitch_smbpbi_destroy_hal_lr10 +( + nvswitch_device *device +) +{ + if (device->pSmbpbi && device->pSmbpbi->sharedSurface) + { + nvswitch_os_unmap_dma_region(device->os_handle, + device->pSmbpbi->sharedSurface, + device->pSmbpbi->dmaHandle, + sizeof(SOE_SMBPBI_SHARED_SURFACE), + NVSWITCH_DMA_DIR_BIDIRECTIONAL); + nvswitch_os_free_contig_memory(device->os_handle, device->pSmbpbi->sharedSurface, + sizeof(SOE_SMBPBI_SHARED_SURFACE)); + } +} NvlStatus nvswitch_smbpbi_get_dem_num_messages_lr10 @@ -41,3 +198,435 @@ nvswitch_smbpbi_get_dem_num_messages_lr10 return NVL_SUCCESS; } + +NvlStatus +nvswitch_smbpbi_dem_load_lr10 +( + nvswitch_device *device +) +{ + NvlStatus status; + NvU8 version = 0; + NvU8 subversion = 0; + struct inforom *pInforom = device->pInforom; + NvU8 *pPackedObject = NULL; + struct INFOROM_DEM_OBJECT_V1_00 *pFifo; + + if ((pInforom == NULL) || (device->pSmbpbi == NULL) || + (device->pSmbpbi->sharedSurface == NULL)) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + pFifo = GET_PFIFO_FROM_DEVICE(device); + + status = nvswitch_inforom_get_object_version_info(device, "DEM", &version, + &subversion); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, INFO, "no DEM object found, rc:%d\n", status); + goto nvswitch_inforom_dem_load_fail; + } + + if (!INFOROM_OBJECT_SUBVERSION_SUPPORTS_NVSWITCH(subversion)) + { + NVSWITCH_PRINT(device, WARN, "DEM v%u.%u not supported\n", + version, subversion); + status = -NVL_ERR_NOT_SUPPORTED; + goto nvswitch_inforom_dem_load_fail; + } + + NVSWITCH_PRINT(device, INFO, "DEM v%u.%u found\n", version, subversion); + + if (version != 1) + { + NVSWITCH_PRINT(device, WARN, "DEM v%u.%u not supported\n", + version, subversion); + status = -NVL_ERR_NOT_SUPPORTED; + goto nvswitch_inforom_dem_load_fail; + } + + pPackedObject = nvswitch_os_malloc(INFOROM_DEM_OBJECT_V1_00_PACKED_SIZE); + + if (pPackedObject == NULL) + { + status = -NVL_NO_MEM; + goto nvswitch_inforom_dem_load_fail; + } + + status = nvswitch_inforom_load_object(device, pInforom, "DEM", + INFOROM_DEM_OBJECT_V1_00_FMT, + pPackedObject, + pFifo); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "Failed to load DEM object, rc: %d\n", + status); + goto nvswitch_inforom_dem_load_fail; + } + +nvswitch_inforom_dem_load_fail: + + if (pPackedObject) + { + nvswitch_os_free(pPackedObject); + } + + // + // Mark the cached DEM as usable for Xid logging, even if we were + // unable to find it in the InfoROM image. + // + + device->pSmbpbi->sharedSurface->inforomObjects.DEM.bValid = NV_TRUE; + + _smbpbiDemInit(device, device->pSmbpbi, pFifo); + + return status; +} + +/*! + * Validate/Initialize the Driver Event Message (SXid) FIFO buffer + * + * @param[in] device device object pointer + * @param[in] pSmbpbi SMBPBI object pointer + * @param[in,out] pFifo DEM object pointer + * + * @return void + */ +static void +_smbpbiDemInit +( + nvswitch_device *device, + struct smbpbi *pSmbpbi, + struct INFOROM_DEM_OBJECT_V1_00 *pFifo +) +{ + NvU8 msgLeft; + unsigned recordsHeld = 0; + NvU16 FIFO_REC_LOOP_ITERATOR; + NvU16 bytesOccupied; + NvU16 bytesSeen; + NvBool status = NV_FALSE; + + // validate the FIFO buffer + + if ((DEM_FIFO_PTR(pFifo->writeOffset) != pFifo->writeOffset) || + (DEM_FIFO_PTR(pFifo->readOffset) != pFifo->readOffset) || + ((pFifo->writeOffset % sizeof(NvU32)) != 0) || + ((pFifo->readOffset % sizeof(NvU32)) != 0)) + { + goto smbpbiDemInit_exit; + } + + if (pFifo->writeOffset == pFifo->readOffset) + { + // The FIFO is empty + status = NV_TRUE; + goto smbpbiDemInit_exit; + } + + // + // This HAL extracts from a scratch register the count of DEM messages + // in the FIFO that has not yet been requested by the SMBPBI client. + // If the FIFO holds more messages than that, it means those in excess + // of this count have been delivered to the client by PreOS app. + // + if (device->hal.nvswitch_smbpbi_get_dem_num_messages(device, &msgLeft) != NVL_SUCCESS) + { + // assume the maximum + msgLeft = ~0; + } + + if (msgLeft == 0) + { + // Nothing of value in the FIFO. Lets reset it explicitly. + status = NV_TRUE; + pFifo->writeOffset = 0; + pFifo->readOffset = 0; + goto smbpbiDemInit_exit; + } + + // + // Count the messages in the FIFO, while also checking the structure + // for integrity. Reset the FIFO in case any corruption is found. + // + bytesOccupied = DEM_BYTES_OCCUPIED(pFifo); + + bytesSeen = 0; + FIFO_REC_LOOP_START(pFifo, bytesSeen < bytesOccupied) + if ((_recSize > DEM_RECORD_SIZE_MAX) || + (FIFO_REC_LOOP_REC_SIZE < DEM_RECORD_SIZE_MIN)) + { + goto smbpbiDemInit_exit; + } + + bytesSeen += FIFO_REC_LOOP_REC_SIZE; + ++recordsHeld; + FIFO_REC_LOOP_END + + if ((bytesSeen != bytesOccupied) || (msgLeft > recordsHeld)) + { + goto smbpbiDemInit_exit; + } + + // + // Advance the FIFO read ptr in order to remove those messages that + // have already been delivered to the client. + // + FIFO_REC_LOOP_START(pFifo, recordsHeld > msgLeft) + --recordsHeld; + FIFO_REC_LOOP_END + + pFifo->readOffset = FIFO_REC_LOOP_ITERATOR; + status = NV_TRUE; + +smbpbiDemInit_exit: + + if (!status) + { + // Reset the FIFO + pFifo->writeOffset = 0; + pFifo->readOffset = 0; + pFifo->seqNumber = 0; + } +} + +/*! + * A helper to create a new DEM FIFO record + * + * @param[in,out] pFifo DEM object pointer + * @param[in] num Xid number + * @param[in] osErrorString text message to store + * @param[in] msglen message size + * @param[out] pRecSize new record size in bytes + * + * @return ptr to the new record + * @return NULL if there's no room in the FIFO + * or dynamic allocation error + */ +static NV_MSGBOX_DEM_RECORD * +_makeNewRecord +( + INFOROM_DEM_OBJECT_V1_00 *pFifo, + NvU32 num, + NvU8 *osErrorString, + NvU32 msglen, + NvU32 *pRecSize +) +{ + NV_MSGBOX_DEM_RECORD *pNewRec; + + *pRecSize = NV_MIN(sizeof(NV_MSGBOX_DEM_RECORD) + msglen, + DEM_RECORD_SIZE_MAX); + + if ((*pRecSize > DEM_BYTES_AVAILABLE(pFifo)) || + ((pNewRec = nvswitch_os_malloc(*pRecSize)) == NULL)) + { + return NULL; + } + + // Fill the new record. + nvswitch_os_memset(pNewRec, 0, *pRecSize); + pNewRec->recordSize = NV_UNSIGNED_DIV_CEIL(*pRecSize, sizeof(NvU32)); + pNewRec->xidId = num; + pNewRec->seqNumber = pFifo->seqNumber++; + pNewRec->timeStamp = nvswitch_os_get_platform_time() / NVSWITCH_NSEC_PER_SEC; + + if (msglen > NV_MSGBOX_MAX_DRIVER_EVENT_MSG_TXT_SIZE) + { + // The text string is too long. Truncate and notify the client. + pNewRec->flags = FLD_SET_DRF(_MSGBOX, _DEM_RECORD_FLAGS, + _TRUNC, _SET, pNewRec->flags); + msglen = NV_MSGBOX_MAX_DRIVER_EVENT_MSG_TXT_SIZE - 1; + } + + nvswitch_os_memcpy(pNewRec->textMessage, osErrorString, msglen); + + return pNewRec; +} + +/*! + * A helper to add the new record to the DEM FIFO + * + * @param[in,out] pFifo DEM object pointer + * @param[in] pNewRec the new record + * @param[in] recSize new record size in bytes + * + * @return void + */ +static void +_addNewRecord +( + INFOROM_DEM_OBJECT_V1_00 *pFifo, + NV_MSGBOX_DEM_RECORD *pNewRec, + NvU32 recSize +) +{ + NvU16 rem; + NvU16 curPtr; + NvU16 copySz; + NvU8 *srcPtr; + + // Copy the new record into the FIFO, handling a possible wrap-around. + rem = recSize; + curPtr = pFifo->writeOffset; + srcPtr = (NvU8 *)pNewRec; + while (rem > 0) + { + copySz = NV_MIN(rem, DEM_FIFO_SIZE - curPtr); + nvswitch_os_memcpy(pFifo->fifoBuffer + curPtr, srcPtr, copySz); + rem -= copySz; + srcPtr += copySz; + curPtr = DEM_FIFO_PTR(curPtr + copySz); + } + + // Advance the FIFO write ptr. + pFifo->writeOffset = DEM_FIFO_PTR(pFifo->writeOffset + + (pNewRec->recordSize * sizeof(NvU32))); +} + +/*! + * Add a Driver Event Message (SXid) to the InfoROM DEM FIFO buffer + * + * @param[in] device device object pointer + * @param[in] num Xid number + * @param[in] msglen message size + * @param[in] osErrorString text message to store + * + * @return void + */ +void +nvswitch_smbpbi_log_message_lr10 +( + nvswitch_device *device, + NvU32 num, + NvU32 msglen, + NvU8 *osErrorString +) +{ + INFOROM_DEM_OBJECT_V1_00 *pFifo; + NvU32 recSize; + NvU16 FIFO_REC_LOOP_ITERATOR; + NV_MSGBOX_DEM_RECORD *pNewRec; + + if ((device->pSmbpbi == NULL) || + (device->pSmbpbi->sharedSurface == NULL)) + { + return; + } + + pFifo = GET_PFIFO_FROM_DEVICE(device); + + pNewRec = _makeNewRecord(pFifo, num, osErrorString, msglen, &recSize); + + if (pNewRec != NULL) + { + _addNewRecord(pFifo, pNewRec, recSize); + nvswitch_os_free(pNewRec); + } + else + { + // + // We are unable to log this message. Mark the latest record + // with a flag telling the client that message(s) were dropped. + // + + NvU16 bytesOccupied = DEM_BYTES_OCCUPIED(pFifo); + NvU16 bytesSeen; + NV_MSGBOX_DEM_RECORD *pLastRec = NULL; + + // Find the newest record + bytesSeen = 0; + FIFO_REC_LOOP_START(pFifo, bytesSeen < bytesOccupied) + pLastRec = FIFO_REC_LOOP_REC_PTR; + bytesSeen += FIFO_REC_LOOP_REC_SIZE; + FIFO_REC_LOOP_END + + if (pLastRec != NULL) + { + pLastRec->flags = FLD_SET_DRF(_MSGBOX, _DEM_RECORD_FLAGS, + _OVFL, _SET, pLastRec->flags); + } + } + + return; +} + +void +nvswitch_smbpbi_dem_flush_lr10 +( + nvswitch_device *device +) +{ + NvU8 *pPackedObject = NULL; + struct INFOROM_DEM_OBJECT_V1_00 *pFifo; + NvlStatus status = NVL_SUCCESS; + + pPackedObject = nvswitch_os_malloc(INFOROM_DEM_OBJECT_V1_00_PACKED_SIZE); + + if (pPackedObject == NULL) + { + status = -NVL_NO_MEM; + goto nvswitch_smbpbi_dem_flush_exit; + } + + pFifo = GET_PFIFO_FROM_DEVICE(device); + + status = nvswitch_inforom_write_object(device, "DEM", + INFOROM_DEM_OBJECT_V1_00_FMT, + pFifo, + pPackedObject); + +nvswitch_smbpbi_dem_flush_exit: + nvswitch_os_free(pPackedObject); + + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "DEM object write failed, status=%d\n", + status); + } +} + +void +nvswitch_smbpbi_send_unload_lr10 +( + nvswitch_device *device +) +{ + FLCN *pFlcn; + RM_FLCN_CMD_SOE cmd; + NVSWITCH_TIMEOUT timeout; + NvU32 cmdSeqDesc; + NvlStatus status; + + pFlcn = device->pSoe->pFlcn; + + nvswitch_os_memset(&cmd, 0, sizeof(cmd)); + cmd.hdr.unitId = RM_SOE_UNIT_SMBPBI; + cmd.hdr.size = RM_SOE_CMD_SIZE(SMBPBI, UNLOAD); + cmd.cmd.smbpbiCmd.cmdType = RM_SOE_SMBPBI_CMD_ID_UNLOAD; + + nvswitch_timeout_create(NVSWITCH_INTERVAL_1SEC_IN_NS, &timeout); + status = flcnQueueCmdPostBlocking(device, pFlcn, + (PRM_FLCN_CMD)&cmd, + NULL, // pMsg - not used for now + NULL, // pPayload - not used for now + SOE_RM_CMDQ_LOG_ID, + &cmdSeqDesc, + &timeout); + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, "%s: SMBPBI unload command failed. rc:%d\n", + __FUNCTION__, status); + } +} + +NvlStatus +nvswitch_smbpbi_send_init_data_lr10 +( + nvswitch_device *device +) +{ + return NVL_SUCCESS; +} + diff --git a/src/common/nvswitch/kernel/lr10/soe_lr10.c b/src/common/nvswitch/kernel/lr10/soe_lr10.c index 8a7d2f251..72b528ba2 100644 --- a/src/common/nvswitch/kernel/lr10/soe_lr10.c +++ b/src/common/nvswitch/kernel/lr10/soe_lr10.c @@ -1584,7 +1584,7 @@ _soeDmaStartTest nvswitch_os_memset(&cmd, 0, sizeof(cmd)); cmd.hdr.unitId = RM_SOE_UNIT_CORE; - cmd.hdr.size = sizeof(cmd); + cmd.hdr.size = RM_SOE_CMD_SIZE(CORE, DMA_TEST); pDmaCmd = &cmd.cmd.core.dma_test; RM_FLCN_U64_PACK(&pDmaCmd->dmaHandle, &dmaHandle); @@ -2064,7 +2064,7 @@ _soeForceThermalSlowdown_LR10 nvswitch_os_memset(&cmd, 0, sizeof(cmd)); cmd.hdr.unitId = RM_SOE_UNIT_THERM; - cmd.hdr.size = sizeof(cmd); + cmd.hdr.size = RM_SOE_CMD_SIZE(THERM, FORCE_SLOWDOWN); cmd.cmd.therm.cmdType = RM_SOE_THERM_FORCE_SLOWDOWN; cmd.cmd.therm.slowdown.slowdown = slowdown; cmd.cmd.therm.slowdown.periodUs = periodUs; diff --git a/src/common/nvswitch/kernel/ls10/clock_ls10.c b/src/common/nvswitch/kernel/ls10/clock_ls10.c new file mode 100644 index 000000000..fcd230bde --- /dev/null +++ b/src/common/nvswitch/kernel/ls10/clock_ls10.c @@ -0,0 +1,195 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include "common_nvswitch.h" +#include "ls10/ls10.h" +#include "ls10/clock_ls10.h" + +#include "nvswitch/ls10/dev_trim.h" +#include "nvswitch/ls10/dev_soe_ip.h" +#include "nvswitch/ls10/dev_npgperf_ip.h" +#include "nvswitch/ls10/dev_nvlw_ip.h" +#include "nvswitch/ls10/dev_nport_ip.h" +#include "nvswitch/ls10/dev_minion_ip.h" +#include "nvswitch/ls10/dev_timer_ip.h" +#include "nvswitch/ls10/dev_minion_ip.h" +#include "nvswitch/ls10/dev_pri_hub_prt_ip.h" +#include "nvswitch/ls10/dev_pri_masterstation_ip.h" + +// +// Initialize the software state of the switch PLL +// +NvlStatus +nvswitch_init_pll_config_ls10 +( + nvswitch_device *device +) +{ + NVSWITCH_PLL_LIMITS pll_limits; + NVSWITCH_PLL_INFO pll; + NvlStatus retval = NVL_SUCCESS; + + // + // These parameters could come from schmoo'ing API, settings file or a ROM. + // If no configuration ROM settings are present, use the PLL documentation + // + // PLL40G_SMALL_ESD.doc + // + + pll_limits.ref_min_mhz = 100; + pll_limits.ref_max_mhz = 100; + pll_limits.vco_min_mhz = 1750; + pll_limits.vco_max_mhz = 3800; + pll_limits.update_min_mhz = 13; // 13.5MHz + pll_limits.update_max_mhz = 38; // 38.4MHz + + pll_limits.m_min = NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_MDIV_MIN; + pll_limits.m_max = NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_MDIV_MAX; + pll_limits.n_min = NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_NDIV_MIN; + pll_limits.n_max = NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_NDIV_MAX; + pll_limits.pl_min = NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_PLDIV_MIN; + pll_limits.pl_max = NV_CLOCK_NVSW_SYS_SWITCHPLL_COEFF_PLDIV_MAX; + pll_limits.valid = NV_TRUE; + + // + // set well known coefficients to achieve frequency + // + + pll.src_freq_khz = 100000; // 100MHz + pll.M = 3; + pll.N = 80; + pll.PL = 2; + pll.dist_mode = 0; // Ignored. Only 1x supported + pll.refclk_div = NV_CLOCK_NVSW_SYS_RX_BYPASS_REFCLK_DIV_INIT; + + retval = nvswitch_validate_pll_config(device, &pll, pll_limits); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, WARN, + "Selecting default PLL setting.\n"); + + // Select default, safe clock + pll.src_freq_khz = 100000; // 100MHz + pll.M = 3; + pll.N = 80; + pll.PL = 2; + pll.dist_mode = 0; // Ignored. Only 1x supported + pll.refclk_div = NV_CLOCK_NVSW_SYS_RX_BYPASS_REFCLK_DIV_INIT; + + retval = nvswitch_validate_pll_config(device, &pll, pll_limits); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "Default PLL setting failed.\n"); + return retval; + } + } + + device->switch_pll = pll; + + return NVL_SUCCESS; +} + +// +// Check that the PLLs are initialized. VBIOS is expected to configure PLLs +// +NvlStatus +nvswitch_init_pll_ls10 +( + nvswitch_device *device +) +{ + NvU32 pllRegVal; + + // + // Clocks should only be initialized on silicon or a clocks netlist on emulation + // + if (IS_RTLSIM(device) || IS_EMULATION(device) || IS_FMODEL(device)) + { + NVSWITCH_PRINT(device, WARN, + "%s: Skipping setup of NVSwitch clocks\n", + __FUNCTION__); + return NVL_SUCCESS; + } + + pllRegVal = NVSWITCH_ENG_RD32(device, CLKS_SYS, , 0, _CLOCK_NVSW_SYS, _SWITCHPLL_CFG); + if (!FLD_TEST_DRF(_CLOCK_NVSW_SYS, _SWITCHPLL_CFG, _PLL_LOCK, _TRUE, pllRegVal)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: _PLL_LOCK failed\n", + __FUNCTION__); + return -NVL_INITIALIZATION_TOTAL_FAILURE; + } + + pllRegVal = NVSWITCH_ENG_RD32(device, CLKS_SYS, , 0, _CLOCK_NVSW_SYS, _SWITCHPLL_CTRL); + if (!FLD_TEST_DRF_NUM(_CLOCK_NVSW_SYS, _SWITCHPLL_CTRL, _PLL_FREQLOCK, 1, pllRegVal)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: _PLL_FREQLOCK failed\n", + __FUNCTION__); + return -NVL_INITIALIZATION_TOTAL_FAILURE; + } + + pllRegVal = NVSWITCH_ENG_RD32(device, CLKS_SYS, , 0, _CLOCK_NVSW_SYS, _SWITCHCLK_SWITCH_DIVIDER); + if (!FLD_TEST_DRF_NUM(_CLOCK_NVSW_SYS, _SWITCHCLK_SWITCH_DIVIDER, _SWITCH_DIVIDER_DONE, 1, pllRegVal)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: _SWITCH_DIVIDER_DONE failed\n", + __FUNCTION__); + return -NVL_INITIALIZATION_TOTAL_FAILURE; + } + + pllRegVal = NVSWITCH_ENG_RD32(device, CLKS_SYS, , 0, _CLOCK_NVSW_SYS, _SYSTEM_CLK_SWITCH_DIVIDER); + if (!FLD_TEST_DRF_NUM(_CLOCK_NVSW_SYS, _SYSTEM_CLK_SWITCH_DIVIDER, _SWITCH_DIVIDER_DONE, 1, pllRegVal)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: _SWITCH_DIVIDER_DONE for SYSTEMCLK failed\n", + __FUNCTION__); + return -NVL_INITIALIZATION_TOTAL_FAILURE; + } + + return NVL_SUCCESS; +} + +// +// Initialize clock gating. +// +void +nvswitch_init_clock_gating_ls10 +( + nvswitch_device *device +) +{ + // + // CG and PROD settings were already handled by: + // - nvswitch_nvs_top_prod_ls10 + // - nvswitch_npg_prod_ls10 + // - nvswitch_apply_prod_nvlw_ls10 + // - nvswitch_apply_prod_nxbar_ls10 + // + // which were all called by nvswitch_initialize_ip_wrappers_ls10 + + return; +} + diff --git a/src/common/nvswitch/kernel/ls10/discovery_ls10.c b/src/common/nvswitch/kernel/ls10/discovery_ls10.c new file mode 100644 index 000000000..82b9493c8 --- /dev/null +++ b/src/common/nvswitch/kernel/ls10/discovery_ls10.c @@ -0,0 +1,1391 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "common_nvswitch.h" +#include "ls10/ls10.h" + +#include "nvswitch/ls10/dev_nvs_top.h" +#include "nvswitch/ls10/nvlinkip_discovery.h" +#include "nvswitch/ls10/npgip_discovery.h" +#include "nvswitch/ls10/nxbar_discovery.h" +#include "nvswitch/ls10/dev_npg_ip.h" + +#include + +#define VERBOSE_MMIO_DISCOVERY 1 + +#define MAKE_DISCOVERY_LS10(_engine) \ + { \ + #_engine, \ + NUM_##_engine##_ENGINE_LS10, \ + NV_SWPTOP_ENUM_DEVICE_##_engine, \ + offsetof(ls10_device, eng##_engine) \ + }, + +typedef struct +{ + const char *engname; + NvU32 engcount_max; + NvU32 discovery_id; + size_t chip_device_engine_offset; +} +DISCOVERY_TABLE_TYPE_LS10; + +#define DISCOVERY_TYPE_UNDEFINED 0 +#define DISCOVERY_TYPE_DISCOVERY 1 +#define DISCOVERY_TYPE_UNICAST 2 +#define DISCOVERY_TYPE_BROADCAST 3 + +#define NVSWITCH_DISCOVERY_ENTRY_INVALID 0x0 +#define NVSWITCH_DISCOVERY_ENTRY_ENUM 0x1 +#define NVSWITCH_DISCOVERY_ENTRY_DATA1 0x2 +#define NVSWITCH_DISCOVERY_ENTRY_DATA2 0x3 + +typedef struct +{ + void (*parse_entry)(nvswitch_device *device, NvU32 entry, NvU32 *entry_type, NvBool *entry_chain); + void (*parse_enum)(nvswitch_device *device, NvU32 entry, NvU32 *entry_device, NvU32 *entry_id, NvU32 *entry_version); + void (*handle_data1)(nvswitch_device *device, NvU32 entry, ENGINE_DISCOVERY_TYPE_LS10 *engine, NvU32 entry_device, NvU32 *discovery_list_size); + void (*handle_data2)(nvswitch_device *device, NvU32 entry, ENGINE_DISCOVERY_TYPE_LS10 *engine, NvU32 entry_device); +} +NVSWITCH_DISCOVERY_HANDLERS_LS10; + +#define DISCOVERY_DUMP_ENGINE_LS10(_engine) \ + _discovery_dump_eng_ls10(device, #_engine, NVSWITCH_GET_CHIP_DEVICE_LS10(device)->eng##_engine, NUM_##_engine##_ENGINE_LS10); + +#define DISCOVERY_DUMP_BC_ENGINE_LS10(_engine) \ + DISCOVERY_DUMP_ENGINE_LS10(_engine##_BCAST) + +static void +_discovery_dump_eng_ls10 +( + nvswitch_device *device, + const char *eng_name, + ENGINE_DISCOVERY_TYPE_LS10 *engine, + NvU32 count +) +{ + NvU32 i; + + if (VERBOSE_MMIO_DISCOVERY) + { + for (i = 0; i < count; i++) + { + if (engine[i].valid) + { + if (engine[i].disc_type == DISCOVERY_TYPE_DISCOVERY) + { + NVSWITCH_PRINT(device, SETUP, + "%-24s[%2d]:V:%1x %s:%6x CL/ID:%2x/%2x\n", + eng_name, i, + engine[i].version, + "DI", + engine[i].info.top.discovery, + engine[i].info.top.cluster, engine[i].info.top.cluster_id); + } + else if (engine[i].disc_type == DISCOVERY_TYPE_UNICAST) + { + NVSWITCH_PRINT(device, SETUP, + "%-24s[%2d]:V:%1x %s:%6x\n", + eng_name, i, + engine[i].version, + "UC", + engine[i].info.uc.uc_addr); + } + else if (engine[i].disc_type == DISCOVERY_TYPE_BROADCAST) + { + NVSWITCH_PRINT(device, SETUP, + "%-24s[%2d]:V:%1x %s:%6x %s:%6x/%6x/%6x\n", + eng_name, i, + engine[i].version, + "BC", + engine[i].info.bc.bc_addr, + "MC", + engine[i].info.bc.mc_addr[0], + engine[i].info.bc.mc_addr[1], + engine[i].info.bc.mc_addr[2]); + } + else + { + NVSWITCH_PRINT(device, SETUP, + "%-24s[%2d]:V:%1x UNDEFINED\n", + eng_name, i, + engine[i].version); + } + } + else + { + NVSWITCH_PRINT(device, SETUP, + "%-24s[%2d]: INVALID\n", + eng_name, i); + } + } + } +} + +static NvlStatus +_nvswitch_device_discovery_ls10 +( + nvswitch_device *device, + NvU32 discovery_offset, + const DISCOVERY_TABLE_TYPE_LS10 *discovery_table, + NvU32 discovery_table_size, + NVSWITCH_DISCOVERY_HANDLERS_LS10 *discovery_handlers +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + ENGINE_DISCOVERY_TYPE_LS10 *engine = NULL; + NvU32 entry_type = NVSWITCH_DISCOVERY_ENTRY_INVALID; + NvBool entry_chain = NV_FALSE; + NvU32 entry = 0; + NvU32 entry_device = 0; + NvU32 entry_id = 0; + NvU32 entry_version = 0; + NvU32 entry_count = 0; + NvBool done = NV_FALSE; + NvlStatus retval = NVL_SUCCESS; + NvU32 i; + + // + // Must be at least two entries. We'll fix it up later when we find the length in the table + // + NvU32 discovery_list_size = 2; + + if (VERBOSE_MMIO_DISCOVERY) + { + NVSWITCH_PRINT(device, SETUP, + "%s: NvSwitch Engine discovery table @%x\n", + __FUNCTION__, + discovery_offset); + } + + while ((!done) && (entry_count < discovery_list_size)) + { + entry = NVSWITCH_OFF_RD32(device, discovery_offset); + discovery_handlers->parse_entry(device, entry, &entry_type, &entry_chain); + + switch (entry_type) + { + case NVSWITCH_DISCOVERY_ENTRY_ENUM: + NVSWITCH_ASSERT(engine == NULL); + discovery_handlers->parse_enum(device, entry, &entry_device, &entry_id, &entry_version); + + for(i = 0; i < discovery_table_size; i++) + { + if (entry_device == discovery_table[i].discovery_id) + { + // + // chip_device_engine_offset is a byte offset within + // the ls10_device structure; at that offset is a table + // of ENGINE_DISCOVERY_TYPE_LS10 entries. + // + ENGINE_DISCOVERY_TYPE_LS10 *entry_base = (ENGINE_DISCOVERY_TYPE_LS10 *) + ((NvU8 *)chip_device + discovery_table[i].chip_device_engine_offset); + + if (entry_id < discovery_table[i].engcount_max) + { + engine = entry_base + entry_id; + break; + } + else + { + NVSWITCH_PRINT(device, ERROR, + "%s:_ENUM: ERROR: %s[%d] out of engine range %d..%d\n", + __FUNCTION__, + discovery_table[i].engname, + entry_id, + 0, discovery_table[i].engcount_max-1); + } + } + } + + if (engine == NULL) + { + NVSWITCH_PRINT(device, ERROR, + "%s:_ENUM: ERROR: device=%x id=%x version=%x not recognized!\n", + __FUNCTION__, + entry_device, entry_id, entry_version); + } + + if (engine != NULL) + { + if ((engine->valid == NV_TRUE) && + (engine->disc_type != DISCOVERY_TYPE_DISCOVERY)) + { + NVSWITCH_PRINT(device, WARN, + "%s:_ENUM: WARNING: device=%x id=%x previously discovered!\n", + __FUNCTION__, + entry_device, entry_id); + } + engine->valid = NV_TRUE; + engine->version = entry_version; + } + + break; + + case NVSWITCH_DISCOVERY_ENTRY_DATA1: + discovery_handlers->handle_data1(device, entry, engine, entry_device, &discovery_list_size); + break; + + case NVSWITCH_DISCOVERY_ENTRY_DATA2: + if (engine == NULL) + { + NVSWITCH_PRINT(device, ERROR, + "%s:DATA2:engine == NULL. Skipping processing\n", + __FUNCTION__); + } + else + { + discovery_handlers->handle_data2(device, entry, engine, entry_device); + } + break; + + default: + NVSWITCH_PRINT(device, ERROR, + "%s:Unknown (%d)\n", + __FUNCTION__, entry_type); + NVSWITCH_ASSERT(0); + // Deliberate fallthrough + case NVSWITCH_DISCOVERY_ENTRY_INVALID: + // Invalid entry. Just ignore it + NVSWITCH_PRINT(device, SETUP, + "%s:_INVALID -- skip 0x%08x\n", + __FUNCTION__, entry); + break; + } + + if (!entry_chain) + { + // End of chain. Close the active engine + engine = NULL; + entry_device = 0; // Mark invalid + entry_id = ~0; + entry_version = ~0; + } + + discovery_offset += sizeof(NvU32); + entry_count++; + } + + if (entry_chain) + { + NVSWITCH_PRINT(device, ERROR, + "%s:Discovery list incorrectly terminated: chain end(%d)\n", + __FUNCTION__, + entry_chain); + NVSWITCH_ASSERT(!entry_chain); + } + + return retval; +} + +static void +_nvswitch_ptop_parse_entry_ls10 +( + nvswitch_device *device, + NvU32 entry, + NvU32 *entry_type, + NvBool *entry_chain +) +{ + NvU32 entry_type_ls10; + + entry_type_ls10 = DRF_VAL(_SWPTOP, _, ENTRY, entry); + *entry_chain = FLD_TEST_DRF(_SWPTOP, _, CHAIN, _ENABLE, entry); + + switch (entry_type_ls10) + { + case NV_SWPTOP_ENTRY_ENUM: + *entry_type = NVSWITCH_DISCOVERY_ENTRY_ENUM; + break; + case NV_SWPTOP_ENTRY_DATA1: + *entry_type = NVSWITCH_DISCOVERY_ENTRY_DATA1; + break; + case NV_SWPTOP_ENTRY_DATA2: + *entry_type = NVSWITCH_DISCOVERY_ENTRY_DATA2; + break; + default: + *entry_type = NVSWITCH_DISCOVERY_ENTRY_INVALID; + break; + } +} + +static void +_nvswitch_ptop_parse_enum_ls10 +( + nvswitch_device *device, + NvU32 entry, + NvU32 *entry_device, + NvU32 *entry_id, + NvU32 *entry_version +) +{ + *entry_device = DRF_VAL(_SWPTOP, _, ENUM_DEVICE, entry); + *entry_id = DRF_VAL(_SWPTOP, _, ENUM_ID, entry); + *entry_version = DRF_VAL(_SWPTOP, _, ENUM_VERSION, entry); +} + +static void +_nvswitch_ptop_handle_data1_ls10 +( + nvswitch_device *device, + NvU32 entry, + ENGINE_DISCOVERY_TYPE_LS10 *engine, + NvU32 entry_device, + NvU32 *discovery_list_size +) +{ + if (NV_SWPTOP_ENUM_DEVICE_PTOP == entry_device) + { + *discovery_list_size = DRF_VAL(_SWPTOP, _DATA1, _PTOP_LENGTH, entry); + return; + } + else + { + NVSWITCH_ASSERT(DRF_VAL(_SWPTOP, _DATA1, _RESERVED, entry) == 0); + } + + if (engine == NULL) + { + NVSWITCH_PRINT(device, ERROR, + "%s:DATA1:engine == NULL. Skipping processing\n", + __FUNCTION__); + return; + } + + engine->info.top.cluster = DRF_VAL(_SWPTOP, _DATA1, _CLUSTER_TYPE, entry); + engine->info.top.cluster_id = DRF_VAL(_SWPTOP, _DATA1, _CLUSTER_NUMBER, entry); + engine->disc_type = DISCOVERY_TYPE_DISCOVERY; +} + +static void +_nvswitch_ptop_handle_data2_ls10 +( + nvswitch_device *device, + NvU32 entry, + ENGINE_DISCOVERY_TYPE_LS10 *engine, + NvU32 entry_device +) +{ + NvU32 data2_type = DRF_VAL(_SWPTOP, _DATA2, _TYPE, entry); + NvU32 data2_addr = DRF_VAL(_SWPTOP, _DATA2, _ADDR, entry); + + switch(data2_type) + { + case NV_SWPTOP_DATA2_TYPE_DISCOVERY: + // Parse sub-discovery table + engine->disc_type = DISCOVERY_TYPE_DISCOVERY; + engine->info.top.discovery = data2_addr*sizeof(NvU32); + break; + case NV_SWPTOP_DATA2_TYPE_UNICAST: + engine->disc_type = DISCOVERY_TYPE_UNICAST; + engine->info.uc.uc_addr = data2_addr*sizeof(NvU32); + break; + case NV_SWPTOP_DATA2_TYPE_BROADCAST: + engine->disc_type = DISCOVERY_TYPE_BROADCAST; + engine->info.bc.bc_addr = data2_addr*sizeof(NvU32); + break; + case NV_SWPTOP_DATA2_TYPE_MULTICAST0: + case NV_SWPTOP_DATA2_TYPE_MULTICAST1: + case NV_SWPTOP_DATA2_TYPE_MULTICAST2: + { + NvU32 mc_idx = data2_type - NV_SWPTOP_DATA2_TYPE_MULTICAST0; + engine->disc_type = DISCOVERY_TYPE_BROADCAST; + engine->info.bc.mc_addr[mc_idx] = data2_addr*sizeof(NvU32); + } + break; + case NV_SWPTOP_DATA2_TYPE_INVALID: + NVSWITCH_PRINT(device, SETUP, + "%s:_DATA2: %s=%6x\n", + __FUNCTION__, + "_INVALID", data2_addr); + engine->disc_type = DISCOVERY_TYPE_UNDEFINED; + break; + default: + NVSWITCH_PRINT(device, SETUP, + "%s:_DATA2: Unknown type 0x%x (0x%08x)!\n", + __FUNCTION__, data2_type, entry); + engine->disc_type = DISCOVERY_TYPE_UNDEFINED; + NVSWITCH_ASSERT(0); + break; + } +} + +void +nvswitch_nvlw_parse_entry_ls10 +( + nvswitch_device *device, + NvU32 entry, + NvU32 *entry_type, + NvBool *entry_chain +) +{ + NvU32 entry_type_nvlw; + + entry_type_nvlw = DRF_VAL(_NVLINKIP, _DISCOVERY_COMMON, _ENTRY, entry); + *entry_chain = FLD_TEST_DRF(_NVLINKIP, _DISCOVERY_COMMON, _CHAIN, _ENABLE, entry); + + switch (entry_type_nvlw) + { + case NV_NVLINKIP_DISCOVERY_COMMON_ENTRY_ENUM: + *entry_type = NVSWITCH_DISCOVERY_ENTRY_ENUM; + break; + case NV_NVLINKIP_DISCOVERY_COMMON_ENTRY_DATA1: + *entry_type = NVSWITCH_DISCOVERY_ENTRY_DATA1; + break; + case NV_NVLINKIP_DISCOVERY_COMMON_ENTRY_DATA2: + *entry_type = NVSWITCH_DISCOVERY_ENTRY_DATA2; + break; + default: + *entry_type = NVSWITCH_DISCOVERY_ENTRY_INVALID; + break; + } +} + +void +nvswitch_nvlw_parse_enum_ls10 +( + nvswitch_device *device, + NvU32 entry, + NvU32 *entry_device, + NvU32 *entry_id, + NvU32 *entry_version +) +{ + NvU32 entry_reserved; + + *entry_device = DRF_VAL(_NVLINKIP, _DISCOVERY_COMMON, _DEVICE, entry); + *entry_id = DRF_VAL(_NVLINKIP, _DISCOVERY_COMMON, _ID, entry); + *entry_version = DRF_VAL(_NVLINKIP, _DISCOVERY_COMMON, _VERSION, entry); + + entry_reserved = DRF_VAL(_NVLINKIP, _DISCOVERY_COMMON, _RESERVED, entry); + NVSWITCH_ASSERT(entry_reserved == 0); + + if (*entry_version != NV_NVLINKIP_DISCOVERY_COMMON_VERSION_NVLINK40) + { + NVSWITCH_PRINT(device, ERROR, + "%s:_NVLINKIP, _DISCOVERY_COMMON, _VERSION = %x but expected %x (_NVLINK40).\n", + __FUNCTION__, *entry_version, NV_NVLINKIP_DISCOVERY_COMMON_VERSION_NVLINK40); + } +} + +void +nvswitch_nvlw_handle_data1_ls10 +( + nvswitch_device *device, + NvU32 entry, + ENGINE_DISCOVERY_TYPE_LS10 *engine, + NvU32 entry_device, + NvU32 *discovery_list_size +) +{ + if ((NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_IOCTRL == entry_device) || + (NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_SIOCTRL == entry_device) || + (NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_TIOCTRL == entry_device) || + (NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_NVLW == entry_device)) + { + *discovery_list_size = DRF_VAL(_NVLINKIP, _DISCOVERY_COMMON, _DATA1_IOCTRL_LENGTH, entry); + } + + if (engine == NULL) + { + NVSWITCH_PRINT(device, ERROR, + "%s:DATA1:engine == NULL. Skipping processing\n", + __FUNCTION__); + return; + } + + if ((NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_IOCTRL != entry_device) && + (NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_SIOCTRL != entry_device) && + (NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_TIOCTRL != entry_device) && + (NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_NVLW != entry_device)) + { + // Nothing specific needed to handle + if (0 != DRF_VAL(_NVLINKIP, _DISCOVERY_COMMON, _DATA1_RESERVED, entry)) + { + NVSWITCH_PRINT(device, WARN, + "%s:WARNING:IOCTRL _RESERVED field != 0 (entry %x -> %x)\n", + __FUNCTION__, + entry, DRF_VAL(_NVLINKIP, _DISCOVERY_COMMON, _DATA1_RESERVED, entry)); + } + } + + if (0 != DRF_VAL(_NVLINKIP, _DISCOVERY_COMMON, _DATA1_RESERVED2, entry)) + { + NVSWITCH_PRINT(device, WARN, + "%s:WARNING:IOCTRL _RESERVED2 field != 0 (entry %x -> %x)\n", + __FUNCTION__, + entry, DRF_VAL(_NVLINKIP, _DISCOVERY_COMMON, _DATA1_RESERVED2, entry)); + } +} + +void +nvswitch_nvlw_handle_data2_ls10 +( + nvswitch_device *device, + NvU32 entry, + ENGINE_DISCOVERY_TYPE_LS10 *engine, + NvU32 entry_device +) +{ + NvU32 data2_type = DRF_VAL(_NVLINKIP, _DISCOVERY_COMMON_DATA2, _TYPE, entry); + NvU32 data2_addr = DRF_VAL(_NVLINKIP, _DISCOVERY_COMMON_DATA2, _ADDR, entry); + + switch(data2_type) + { + + case NV_NVLINKIP_DISCOVERY_COMMON_DATA2_TYPE_DISCOVERY: + // Parse sub-discovery table + + // + // Currently _DISCOVERY is not used in the second + // level discovery. + // + NVSWITCH_ASSERT(0); + + break; + + case NV_NVLINKIP_DISCOVERY_COMMON_DATA2_TYPE_UNICAST: + engine->disc_type = DISCOVERY_TYPE_UNICAST; + engine->info.uc.uc_addr = data2_addr*sizeof(NvU32); + break; + + case NV_NVLINKIP_DISCOVERY_COMMON_DATA2_TYPE_BROADCAST: + engine->disc_type = DISCOVERY_TYPE_BROADCAST; + engine->info.bc.bc_addr = data2_addr*sizeof(NvU32); + break; + + case NV_NVLINKIP_DISCOVERY_COMMON_DATA2_TYPE_MULTICAST0: + case NV_NVLINKIP_DISCOVERY_COMMON_DATA2_TYPE_MULTICAST1: + case NV_NVLINKIP_DISCOVERY_COMMON_DATA2_TYPE_MULTICAST2: + { + NvU32 mc_idx = data2_type - NV_NVLINKIP_DISCOVERY_COMMON_DATA2_TYPE_MULTICAST0; + engine->disc_type = DISCOVERY_TYPE_BROADCAST; + engine->info.bc.mc_addr[mc_idx] = data2_addr*sizeof(NvU32); + } + break; + + case NV_NVLINKIP_DISCOVERY_COMMON_DATA2_TYPE_INVALID: + NVSWITCH_PRINT(device, ERROR, + "%s:_DATA2: %s=%6x\n", + __FUNCTION__, + "_INVALID", data2_addr); + engine->disc_type = DISCOVERY_TYPE_UNDEFINED; + break; + + default: + NVSWITCH_PRINT(device, ERROR, + "%s:_DATA2: Unknown!\n", + __FUNCTION__); + NVSWITCH_ASSERT(0); + break; + } +} + +static void +_nvswitch_npg_parse_entry_ls10 +( + nvswitch_device *device, + NvU32 entry, + NvU32 *entry_type, + NvBool *entry_chain +) +{ + NvU32 entry_type_npg; + + entry_type_npg = DRF_VAL(_NPG, _DISCOVERY, _ENTRY, entry); + *entry_chain = FLD_TEST_DRF(_NPG, _DISCOVERY, _CHAIN, _ENABLE, entry); + + switch (entry_type_npg) + { + case NV_NPG_DISCOVERY_ENTRY_ENUM: + *entry_type = NVSWITCH_DISCOVERY_ENTRY_ENUM; + break; + case NV_NPG_DISCOVERY_ENTRY_DATA1: + *entry_type = NVSWITCH_DISCOVERY_ENTRY_DATA1; + break; + case NV_NPG_DISCOVERY_ENTRY_DATA2: + *entry_type = NVSWITCH_DISCOVERY_ENTRY_DATA2; + break; + default: + *entry_type = NVSWITCH_DISCOVERY_ENTRY_INVALID; + break; + } +} + +static void +_nvswitch_npg_parse_enum_ls10 +( + nvswitch_device *device, + NvU32 entry, + NvU32 *entry_device, + NvU32 *entry_id, + NvU32 *entry_version +) +{ + *entry_device = DRF_VAL(_NPG, _DISCOVERY, _ENUM_DEVICE, entry); + *entry_id = DRF_VAL(_NPG, _DISCOVERY, _ENUM_ID, entry); + *entry_version = DRF_VAL(_NPG, _DISCOVERY, _ENUM_VERSION, entry); + NVSWITCH_ASSERT(DRF_VAL(_NPG, _DISCOVERY, _ENUM_RESERVED, entry) == 0); + + if (*entry_version != NV_NPG_DISCOVERY_ENUM_VERSION_3) + { + NVSWITCH_PRINT(device, ERROR, + "%s:_NPG_DISCOVERY_ENUM_VERSION = %x but expected %x (_VERSION_3).\n", + __FUNCTION__, *entry_version, NV_NPG_DISCOVERY_ENUM_VERSION_3); + } +} + +static void +_nvswitch_npg_handle_data1_ls10 +( + nvswitch_device *device, + NvU32 entry, + ENGINE_DISCOVERY_TYPE_LS10 *engine, + NvU32 entry_device, + NvU32 *discovery_list_size +) +{ + if (NV_NPG_DISCOVERY_ENUM_DEVICE_NPG == entry_device) + { + *discovery_list_size = DRF_VAL(_NPG, _DISCOVERY, _DATA1_NPG_LENGTH, entry); + } + else + { + NVSWITCH_ASSERT(0 == DRF_VAL(_NPG, _DISCOVERY, _DATA1_RESERVED, entry)); + } + + if (engine == NULL) + { + NVSWITCH_PRINT(device, SETUP, + "%s:DATA1:engine == NULL. Skipping processing\n", + __FUNCTION__); + return; + } +} + +static void +_nvswitch_npg_handle_data2_ls10 +( + nvswitch_device *device, + NvU32 entry, + ENGINE_DISCOVERY_TYPE_LS10 *engine, + NvU32 entry_device +) +{ + NvU32 data2_type = DRF_VAL(_NPG, _DISCOVERY_DATA2, _TYPE, entry); + NvU32 data2_addr = DRF_VAL(_NPG, _DISCOVERY_DATA2, _ADDR, entry); + + switch(data2_type) + { + case NV_NPG_DISCOVERY_DATA2_TYPE_DISCOVERY: + // Parse sub-discovery table + + // + // Currently _DISCOVERY is not used in the second + // level discovery. + // + NVSWITCH_ASSERT(0); + + break; + + case NV_NPG_DISCOVERY_DATA2_TYPE_UNICAST: + engine->disc_type = DISCOVERY_TYPE_UNICAST; + engine->info.uc.uc_addr = data2_addr*sizeof(NvU32); + break; + + case NV_NPG_DISCOVERY_DATA2_TYPE_BROADCAST: + engine->disc_type = DISCOVERY_TYPE_BROADCAST; + engine->info.bc.bc_addr = data2_addr*sizeof(NvU32); + break; + + case NV_NPG_DISCOVERY_DATA2_TYPE_MULTICAST0: + case NV_NPG_DISCOVERY_DATA2_TYPE_MULTICAST1: + case NV_NPG_DISCOVERY_DATA2_TYPE_MULTICAST2: + { + NvU32 mc_idx = data2_type - NV_NPG_DISCOVERY_DATA2_TYPE_MULTICAST0; + engine->disc_type = DISCOVERY_TYPE_BROADCAST; + engine->info.bc.mc_addr[mc_idx] = data2_addr*sizeof(NvU32); + } + break; + + case NV_NPG_DISCOVERY_DATA2_TYPE_INVALID: + NVSWITCH_PRINT(device, SETUP, + "%s:_DATA2: %s=%6x\n", + __FUNCTION__, + "_INVALID", data2_addr); + engine->disc_type = DISCOVERY_TYPE_UNDEFINED; + break; + + default: + NVSWITCH_PRINT(device, SETUP, + "%s:_DATA2: Unknown!\n", + __FUNCTION__); + NVSWITCH_ASSERT(0); + break; + } +} + +void +nvswitch_nxbar_parse_entry_ls10 +( + nvswitch_device *device, + NvU32 entry, + NvU32 *entry_type, + NvBool *entry_chain +) +{ + NvU32 entry_type_nxbar; + + entry_type_nxbar = DRF_VAL(_NXBAR, _DISCOVERY, _ENTRY, entry); + *entry_chain = FLD_TEST_DRF(_NXBAR, _DISCOVERY, _CHAIN, _ENABLE, entry); + + switch (entry_type_nxbar) + { + case NV_NXBAR_DISCOVERY_ENTRY_ENUM: + *entry_type = NVSWITCH_DISCOVERY_ENTRY_ENUM; + break; + case NV_NXBAR_DISCOVERY_ENTRY_DATA1: + *entry_type = NVSWITCH_DISCOVERY_ENTRY_DATA1; + break; + case NV_NXBAR_DISCOVERY_ENTRY_DATA2: + *entry_type = NVSWITCH_DISCOVERY_ENTRY_DATA2; + break; + default: + *entry_type = NVSWITCH_DISCOVERY_ENTRY_INVALID; + break; + } +} + +void +nvswitch_nxbar_parse_enum_ls10 +( + nvswitch_device *device, + NvU32 entry, + NvU32 *entry_device, + NvU32 *entry_id, + NvU32 *entry_version +) +{ + NvU32 entry_reserved; + + *entry_device = DRF_VAL(_NXBAR, _DISCOVERY, _ENUM_DEVICE, entry); + *entry_id = DRF_VAL(_NXBAR, _DISCOVERY, _ENUM_ID, entry); + *entry_version = DRF_VAL(_NXBAR, _DISCOVERY, _ENUM_VERSION, entry); + + entry_reserved = DRF_VAL(_NXBAR, _DISCOVERY, _ENUM_RESERVED, entry); + NVSWITCH_ASSERT(entry_reserved == 0); + + if (*entry_version != NV_NXBAR_DISCOVERY_ENUM_VERSION_3) + { + NVSWITCH_PRINT(device, ERROR, + "%s:_NXBAR_DISCOVERY_ENUM_VERSION = %x but expected %x (_VERSION_3).\n", + __FUNCTION__, *entry_version, NV_NXBAR_DISCOVERY_ENUM_VERSION_3); + } +} + +void +nvswitch_nxbar_handle_data1_ls10 +( + nvswitch_device *device, + NvU32 entry, + ENGINE_DISCOVERY_TYPE_LS10 *engine, + NvU32 entry_device, + NvU32 *discovery_list_size +) +{ + if (NV_NXBAR_DISCOVERY_ENUM_DEVICE_NXBAR == entry_device) + { + *discovery_list_size = DRF_VAL(_NXBAR, _DISCOVERY, _DATA1_NXBAR_LENGTH, entry); + } + + if (engine == NULL) + { + NVSWITCH_PRINT(device, ERROR, + "%s:DATA1:engine == NULL. Skipping processing\n", + __FUNCTION__); + return; + } + + if (NV_NXBAR_DISCOVERY_ENUM_DEVICE_NXBAR != entry_device) + { + NVSWITCH_ASSERT(DRF_VAL(_NXBAR, _DISCOVERY, _DATA1_RESERVED, entry) == 0); + } +} + +void +nvswitch_nxbar_handle_data2_ls10 +( + nvswitch_device *device, + NvU32 entry, + ENGINE_DISCOVERY_TYPE_LS10 *engine, + NvU32 entry_device +) +{ + NvU32 data2_type = DRF_VAL(_NXBAR, _DISCOVERY_DATA2, _TYPE, entry); + NvU32 data2_addr = DRF_VAL(_NXBAR, _DISCOVERY_DATA2, _ADDR, entry); + + switch(data2_type) + { + case NV_NXBAR_DISCOVERY_DATA2_TYPE_DISCOVERY: + // Parse sub-discovery table + + // + // Currently _DISCOVERY is not used in the second + // level discovery. + // + NVSWITCH_ASSERT(0); + + break; + + case NV_NXBAR_DISCOVERY_DATA2_TYPE_UNICAST: + engine->disc_type = DISCOVERY_TYPE_UNICAST; + engine->info.uc.uc_addr = data2_addr*sizeof(NvU32); + break; + + case NV_NXBAR_DISCOVERY_DATA2_TYPE_BROADCAST: + engine->disc_type = DISCOVERY_TYPE_BROADCAST; + engine->info.bc.bc_addr = data2_addr*sizeof(NvU32); + engine->info.bc.mc_addr[0] = 0; + engine->info.bc.mc_addr[1] = 0; + engine->info.bc.mc_addr[2] = 0; + break; + + case NV_NXBAR_DISCOVERY_DATA2_TYPE_MULTICAST0: + case NV_NXBAR_DISCOVERY_DATA2_TYPE_MULTICAST1: + case NV_NXBAR_DISCOVERY_DATA2_TYPE_MULTICAST2: + { + NvU32 mc_idx = data2_type - NV_NXBAR_DISCOVERY_DATA2_TYPE_MULTICAST0; + engine->info.bc.mc_addr[mc_idx] = data2_addr*sizeof(NvU32); + NVSWITCH_PRINT(device, ERROR, + "%s:_DATA2: NXBAR MULTICAST%d=0x%x but should be unused!\n", + __FUNCTION__, mc_idx, engine->info.bc.mc_addr[mc_idx]); + NVSWITCH_ASSERT(0); + } + break; + + case NV_NXBAR_DISCOVERY_DATA2_TYPE_INVALID: + NVSWITCH_PRINT(device, ERROR, + "%s:_DATA2: %s=%6x\n", + __FUNCTION__, + "_INVALID", data2_addr); + engine->disc_type = DISCOVERY_TYPE_UNDEFINED; + break; + + default: + NVSWITCH_PRINT(device, ERROR, + "%s:_DATA2: Unknown!\n", + __FUNCTION__); + NVSWITCH_ASSERT(0); + break; + } +} + +#define MAKE_DISCOVERY_NVLINK_UC_LS10(_eng) \ + { \ + #_eng, \ + NUM_##_eng##_ENGINE_LS10, \ + NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_##_eng, \ + offsetof(ls10_device, eng##_eng) \ + }, + +#define MAKE_DISCOVERY_NVLINK_BC_LS10(_eng) \ + { \ + #_eng "_BCAST", \ + NUM_##_eng##_BCAST_ENGINE_LS10, \ + NV_NVLINKIP_DISCOVERY_COMMON_DEVICE_##_eng, \ + offsetof(ls10_device, eng##_eng##_BCAST) \ + }, + +#define MAKE_DISCOVERY_NPG_UC_LS10(_eng) \ + { \ + #_eng, \ + NUM_##_eng##_ENGINE_LS10, \ + NV_NPG_DISCOVERY_ENUM_DEVICE_##_eng, \ + offsetof(ls10_device, eng##_eng) \ + }, + +#define MAKE_DISCOVERY_NPG_BC_LS10(_eng) \ + { \ + #_eng "_BCAST", \ + NUM_##_eng##_BCAST_ENGINE_LS10, \ + NV_NPG_DISCOVERY_ENUM_DEVICE_##_eng, \ + offsetof(ls10_device, eng##_eng##_BCAST) \ + }, + +#define MAKE_DISCOVERY_NXBAR_UC_LS10(_eng) \ + { \ + #_eng, \ + NUM_##_eng##_ENGINE_LS10, \ + NV_NXBAR_DISCOVERY_ENUM_DEVICE_##_eng, \ + offsetof(ls10_device, eng##_eng) \ + }, + +#define MAKE_DISCOVERY_NXBAR_BC_LS10(_eng) \ + { \ + #_eng "_BCAST", \ + NUM_##_eng##_BCAST_ENGINE_LS10, \ + NV_NXBAR_DISCOVERY_ENUM_DEVICE_##_eng, \ + offsetof(ls10_device, eng##_eng##_BCAST) \ + }, + +static +NVSWITCH_DISCOVERY_HANDLERS_LS10 discovery_handlers_ptop_ls10 = +{ + &_nvswitch_ptop_parse_entry_ls10, + &_nvswitch_ptop_parse_enum_ls10, + &_nvswitch_ptop_handle_data1_ls10, + &_nvswitch_ptop_handle_data2_ls10 +}; + +static +NVSWITCH_DISCOVERY_HANDLERS_LS10 discovery_handlers_npg_ls10 = +{ + &_nvswitch_npg_parse_entry_ls10, + &_nvswitch_npg_parse_enum_ls10, + &_nvswitch_npg_handle_data1_ls10, + &_nvswitch_npg_handle_data2_ls10 +}; + +static +NVSWITCH_DISCOVERY_HANDLERS_LS10 discovery_handlers_nvlw_ls10 = +{ + &nvswitch_nvlw_parse_entry_ls10, + &nvswitch_nvlw_parse_enum_ls10, + &nvswitch_nvlw_handle_data1_ls10, + &nvswitch_nvlw_handle_data2_ls10 +}; + +static +NVSWITCH_DISCOVERY_HANDLERS_LS10 discovery_handlers_nxbar_ls10 = +{ + &nvswitch_nxbar_parse_entry_ls10, + &nvswitch_nxbar_parse_enum_ls10, + &nvswitch_nxbar_handle_data1_ls10, + &nvswitch_nxbar_handle_data2_ls10 +}; + +// +// Parse top level PTOP engine discovery information to identify MMIO, interrupt, and +// reset information +// + +NvlStatus +nvswitch_device_discovery_ls10 +( + nvswitch_device *device, + NvU32 discovery_offset +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + + // + // The top level discovery table in PTOP describes all the top level + // unicast units, and also points to the sub-discovery tables of the IP + // wrappers. These IP wrapper sub-discovery tables are then examined in + // succession to build the MMIO map of units. Floorswept units will have + // discovery entries that are marked invalid. + // + static const DISCOVERY_TABLE_TYPE_LS10 discovery_table_ls10[] = + { + NVSWITCH_LIST_LS10_ENGINE_UC(MAKE_DISCOVERY_LS10) + NVSWITCH_LIST_PRI_HUB_LS10_ENGINE(MAKE_DISCOVERY_LS10) + MAKE_DISCOVERY_LS10(NPG) + MAKE_DISCOVERY_LS10(NPG_BCAST) + MAKE_DISCOVERY_LS10(NVLW) + MAKE_DISCOVERY_LS10(NVLW_BCAST) + MAKE_DISCOVERY_LS10(NXBAR) + MAKE_DISCOVERY_LS10(NXBAR_BCAST) + }; + NvU32 discovery_table_ls10_size = NV_ARRAY_ELEMENTS(discovery_table_ls10); + NvU32 i; + NvlStatus status; + + status = _nvswitch_device_discovery_ls10( + device, discovery_offset, discovery_table_ls10, discovery_table_ls10_size, + &discovery_handlers_ptop_ls10); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "MMIO discovery failed\n"); + return status; + } + + if (VERBOSE_MMIO_DISCOVERY) + { + NVSWITCH_PRINT(device, SETUP, + "PTOP Discovery\n"); + + NVSWITCH_LIST_LS10_ENGINE_UC(DISCOVERY_DUMP_ENGINE_LS10) + NVSWITCH_LIST_PRI_HUB_LS10_ENGINE(DISCOVERY_DUMP_ENGINE_LS10) + DISCOVERY_DUMP_ENGINE_LS10(NPG) + DISCOVERY_DUMP_ENGINE_LS10(NPG_BCAST) + DISCOVERY_DUMP_ENGINE_LS10(NVLW) + DISCOVERY_DUMP_ENGINE_LS10(NVLW_BCAST) + DISCOVERY_DUMP_ENGINE_LS10(NXBAR) + DISCOVERY_DUMP_ENGINE_LS10(NXBAR_BCAST) + } + + for (i = 0; i < NUM_NVLW_ENGINE_LS10; i++) + { + if (chip_device->engNVLW[i].valid && + (chip_device->engNVLW[i].info.top.discovery != 0)) + { + static const DISCOVERY_TABLE_TYPE_LS10 discovery_table_nvlw[] = + { + NVSWITCH_LIST_NVLW_LS10_ENGINE(MAKE_DISCOVERY_NVLINK_UC_LS10) + }; + NvU32 discovery_table_nvlw_size = NV_ARRAY_ELEMENTS(discovery_table_nvlw); + + status = _nvswitch_device_discovery_ls10( + device, chip_device->engNVLW[i].info.top.discovery, discovery_table_nvlw, + discovery_table_nvlw_size, &discovery_handlers_nvlw_ls10); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "NVLW[%d] discovery failed\n", i); + return status; + } + } + } + if (VERBOSE_MMIO_DISCOVERY) + { + NVSWITCH_PRINT(device, SETUP, + "NVLW[0..%d] Discovery\n", + NUM_NVLW_ENGINE_LS10-1); + NVSWITCH_LIST_NVLW_LS10_ENGINE(DISCOVERY_DUMP_ENGINE_LS10) + } + + for (i = 0; i < NUM_NVLW_BCAST_ENGINE_LS10; i++) + { + if (chip_device->engNVLW_BCAST[i].valid && + (chip_device->engNVLW_BCAST[i].info.top.discovery != 0)) + { + static const DISCOVERY_TABLE_TYPE_LS10 discovery_table_nvlw[] = + { + NVSWITCH_LIST_NVLW_LS10_ENGINE(MAKE_DISCOVERY_NVLINK_BC_LS10) + }; + NvU32 discovery_table_nvlw_size = NV_ARRAY_ELEMENTS(discovery_table_nvlw); + + status = _nvswitch_device_discovery_ls10( + device, chip_device->engNVLW_BCAST[i].info.top.discovery, discovery_table_nvlw, + discovery_table_nvlw_size, &discovery_handlers_nvlw_ls10); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "NVLW_BCAST[%d] discovery failed\n", i); + return status; + } + } + } + if (VERBOSE_MMIO_DISCOVERY) + { + NVSWITCH_PRINT(device, SETUP, + "NVLW_BCAST[0..%d] Discovery\n", + NUM_NVLW_BCAST_ENGINE_LS10-1); + NVSWITCH_LIST_NVLW_LS10_ENGINE(DISCOVERY_DUMP_BC_ENGINE_LS10) + } + + for (i = 0; i < NUM_NPG_ENGINE_LS10; i++) + { + if (chip_device->engNPG[i].valid && + (chip_device->engNPG[i].info.top.discovery != 0)) + { + static const DISCOVERY_TABLE_TYPE_LS10 discovery_table_npg[] = + { + NVSWITCH_LIST_NPG_LS10_ENGINE(MAKE_DISCOVERY_NPG_UC_LS10) + }; + NvU32 discovery_table_npg_size = NV_ARRAY_ELEMENTS(discovery_table_npg); + + status = _nvswitch_device_discovery_ls10( + device, chip_device->engNPG[i].info.top.discovery, discovery_table_npg, + discovery_table_npg_size, &discovery_handlers_npg_ls10); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "NPG[%d] discovery failed\n", i); + return status; + } + } + } + if (VERBOSE_MMIO_DISCOVERY) + { + NVSWITCH_PRINT(device, SETUP, + "NPG[0..%d] Discovery\n", + NUM_NPG_ENGINE_LS10-1); + NVSWITCH_LIST_NPG_LS10_ENGINE(DISCOVERY_DUMP_ENGINE_LS10) + } + + for (i = 0; i < NUM_NPG_BCAST_ENGINE_LS10; i++) + { + if (chip_device->engNPG_BCAST[i].valid && + (chip_device->engNPG_BCAST[i].info.top.discovery != 0)) + { + static const DISCOVERY_TABLE_TYPE_LS10 discovery_table_npg[] = + { + NVSWITCH_LIST_NPG_LS10_ENGINE(MAKE_DISCOVERY_NPG_BC_LS10) + }; + NvU32 discovery_table_npg_size = NV_ARRAY_ELEMENTS(discovery_table_npg); + + status = _nvswitch_device_discovery_ls10( + device, chip_device->engNPG_BCAST[i].info.top.discovery, discovery_table_npg, + discovery_table_npg_size, &discovery_handlers_npg_ls10); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "NPG_BCAST[%d] discovery failed\n", i); + return status; + } + } + } + if (VERBOSE_MMIO_DISCOVERY) + { + NVSWITCH_PRINT(device, SETUP, + "NPG_BCAST[%d] Discovery\n", + NUM_NPG_BCAST_ENGINE_LS10-1); + NVSWITCH_LIST_NPG_LS10_ENGINE(DISCOVERY_DUMP_BC_ENGINE_LS10) + } + + for (i = 0; i < NUM_NXBAR_ENGINE_LS10; i++) + { + if (chip_device->engNXBAR[i].valid && + (chip_device->engNXBAR[i].info.top.discovery != 0)) + { + static const DISCOVERY_TABLE_TYPE_LS10 discovery_table_nxbar[] = + { + NVSWITCH_LIST_NXBAR_LS10_ENGINE(MAKE_DISCOVERY_NXBAR_UC_LS10) + }; + NvU32 discovery_table_nxbar_size = NV_ARRAY_ELEMENTS(discovery_table_nxbar); + + status = _nvswitch_device_discovery_ls10( + device, chip_device->engNXBAR[i].info.top.discovery, + discovery_table_nxbar, discovery_table_nxbar_size, + &discovery_handlers_nxbar_ls10); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "NXBAR[%d] discovery failed\n", i); + return status; + } + } + } + if (VERBOSE_MMIO_DISCOVERY) + { + NVSWITCH_PRINT(device, SETUP, + "NXBAR[0..%d] Discovery\n", + NUM_NXBAR_ENGINE_LS10-1); + NVSWITCH_LIST_NXBAR_LS10_ENGINE(DISCOVERY_DUMP_ENGINE_LS10) + } + + for (i = 0; i < NUM_NXBAR_BCAST_ENGINE_LS10; i++) + { + if (chip_device->engNXBAR_BCAST[i].valid && + (chip_device->engNXBAR_BCAST[i].info.top.discovery != 0)) + { + static const DISCOVERY_TABLE_TYPE_LS10 discovery_table_nxbar[] = + { + NVSWITCH_LIST_NXBAR_LS10_ENGINE(MAKE_DISCOVERY_NXBAR_BC_LS10) + }; + NvU32 discovery_table_nxbar_size = NV_ARRAY_ELEMENTS(discovery_table_nxbar); + + status = _nvswitch_device_discovery_ls10( + device, chip_device->engNXBAR_BCAST[i].info.top.discovery, + discovery_table_nxbar, discovery_table_nxbar_size, + &discovery_handlers_nxbar_ls10); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "NXBAR_BCAST[%d] discovery failed\n", i); + return status; + } + } + } + if (VERBOSE_MMIO_DISCOVERY) + { + NVSWITCH_PRINT(device, SETUP, + "NXBAR_BCAST[0..%d] Discovery\n", + NUM_NXBAR_BCAST_ENGINE_LS10-1); + NVSWITCH_LIST_NXBAR_LS10_ENGINE(DISCOVERY_DUMP_BC_ENGINE_LS10) + } + + return status; +} + +// +// Filter engine discovery information to handle platform-specific differences. +// +// Emulation and RTL sims have devices that show up in the discovery table but +// are actually tied off and not present. On GPU the engine enables and +// floorsweeping info are used to disable devices that are not present. +// But a similar mechanism does not exist in NvSwitch. +// So instead we invalidate the devices that are known to be not-present on a +// given platform. +// + +void +nvswitch_filter_discovery_ls10 +( + nvswitch_device *device +) +{ +} + +#define NVSWITCH_PROCESS_DISCOVERY(_current, _engine, _multicast) \ + { \ + NvU32 i; \ + ct_assert(NUM_##_engine##_ENGINE_LS10 <= NVSWITCH_ENGINE_DESCRIPTOR_UC_SIZE); \ + \ + _current->eng_name = #_engine; \ + _current->eng_id = NVSWITCH_ENGINE_ID_##_engine; \ + _current->eng_count = NUM_##_engine##_ENGINE_LS10; \ + \ + for (i = 0; i < NUM_##_engine##_ENGINE_LS10; i++) \ + { \ + if (chip_device->eng##_engine[i].valid) \ + { \ + _current->uc_addr[i] = \ + chip_device->eng##_engine[i].info.uc.uc_addr; \ + } \ + } \ + \ + if (chip_device->eng##_engine##_multicast[0].valid) \ + { \ + _current->bc_addr = \ + chip_device->eng##_engine##_multicast[0].info.bc.bc_addr; \ + } \ + \ + _current->mc_addr_count = 0; \ + } \ + +#define NVSWITCH_PROCESS_COMMON(_engine, _multicast) \ + { \ + NVSWITCH_ENGINE_DESCRIPTOR_TYPE *current; \ + ct_assert(NVSWITCH_ENGINE_ID_##_engine < NVSWITCH_ENGINE_ID_SIZE); \ + \ + current = &chip_device->io.common[NVSWITCH_ENGINE_ID_##_engine]; \ + NVSWITCH_PROCESS_DISCOVERY(current, _engine, _multicast) \ + } + +// +// Process engine discovery information to associate engines +// + +NvlStatus +nvswitch_process_discovery_ls10 +( + nvswitch_device *device +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NvU32 i, j; + NvU64 localMinionLinkMask; + NvlStatus retval = NVL_SUCCESS; + NvU64 link_enable_mask; + + // + // Process per-link information + // + for (i = 0; i < NVSWITCH_NUM_LINKS_LS10; i++) + { + device->link[i].valid = + NVSWITCH_ENG_VALID_LS10(device, NVLTLC, NVSWITCH_GET_LINK_ENG_INST(device, i, NVLTLC)) && + NVSWITCH_ENG_VALID_LS10(device, NVLDL, NVSWITCH_GET_LINK_ENG_INST(device, i, NVLDL)) && + NVSWITCH_ENG_VALID_LS10(device, NVLIPT_LNK, NVSWITCH_GET_LINK_ENG_INST(device, i, NVLIPT_LNK)) && + NVSWITCH_ENG_VALID_LS10(device, NVLW, NVSWITCH_GET_LINK_ENG_INST(device, i, NVLW)) && + NVSWITCH_ENG_VALID_LS10(device, MINION, NVSWITCH_GET_LINK_ENG_INST(device, i, MINION)) && + NVSWITCH_ENG_VALID_LS10(device, NVLIPT, NVSWITCH_GET_LINK_ENG_INST(device, i, NVLIPT)); + } + + // + // Disable engines requested by regkey "LinkEnableMask". + // All the links are enabled by default. + // + link_enable_mask = ((NvU64)device->regkeys.link_enable_mask2 << 32 | + (NvU64)device->regkeys.link_enable_mask); + + for (i = 0; i < NVSWITCH_NUM_LINKS_LS10; i++) + { + if ((NVBIT64(i) & link_enable_mask) == 0) + { + NVSWITCH_PRINT(device, SETUP, + "%s: Disable link #%d\n", + __FUNCTION__, i); + device->link[i].valid = NV_FALSE; + chip_device->engNPORT[i].valid = NV_FALSE; + chip_device->engNPORT_PERFMON[i].valid = NV_FALSE; + chip_device->engNVLTLC[i].valid = NV_FALSE; + } + } + + // + // Go through all MINION engines and mark them + // as invalid if all links associated with that MINION + // are invalid + // + for (i =0; i < NUM_MINION_ENGINE_LS10; i++) + { + + // + // Get the local link mask asscotiated with this minion + // In this case there is a 1-1 association between NVLIPT + // and MINION instances + // + localMinionLinkMask = NVSWITCH_NVLIPT_GET_LOCAL_LINK_MASK64_LS10(i); + + // + // If there are no links from localMinionLinkMask in + // link_enable_mask then mark the MINION instance as invalid + // + if ((localMinionLinkMask & link_enable_mask) == 0) + { + chip_device->engMINION[i].valid = NV_FALSE; + } + } + + // + // Process common engine information + // + + // Mark all entries as invalid + for (i = 0; i < NVSWITCH_ENGINE_ID_SIZE; i++) + { + chip_device->io.common[i].eng_name = ""; + chip_device->io.common[i].eng_id = NVSWITCH_ENGINE_ID_SIZE; // Out of range + chip_device->io.common[i].eng_count = 0; + for (j = 0; j < NVSWITCH_ENGINE_DESCRIPTOR_UC_SIZE; j++) + { + chip_device->io.common[i].uc_addr[j] = NVSWITCH_BASE_ADDR_INVALID; + } + chip_device->io.common[i].bc_addr = NVSWITCH_BASE_ADDR_INVALID; + for (j = 0; j < NVSWITCH_ENGINE_DESCRIPTOR_MC_SIZE; j++) + { + chip_device->io.common[i].mc_addr[j] = NVSWITCH_BASE_ADDR_INVALID; + } + chip_device->io.common[i].mc_addr_count = 0; + } + + NVSWITCH_LIST_LS10_ENGINES(NVSWITCH_PROCESS_COMMON) + + return retval; +} + diff --git a/src/common/nvswitch/kernel/ls10/flcn_ls10.c b/src/common/nvswitch/kernel/ls10/flcn_ls10.c new file mode 100644 index 000000000..496f1b8cd --- /dev/null +++ b/src/common/nvswitch/kernel/ls10/flcn_ls10.c @@ -0,0 +1,376 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include "common_nvswitch.h" +#include "ls10/ls10.h" +#include "flcn/flcn_nvswitch.h" + +#include "nvswitch/ls10/dev_falcon_v4.h" +#include "nvswitch/ls10/dev_riscv_pri.h" + +// +// Functions shared with LR10 +// + +void flcnSetupHal_LR10(PFLCN pFlcn); + +static NvU32 +_flcnRiscvRegRead_LS10 +( + nvswitch_device *device, + PFLCN pFlcn, + NvU32 offset +) +{ + // Probably should perform some checks on the offset, the device, and the engine descriptor + return nvswitch_reg_read_32(device, NV_FALCON2_SOE_BASE + offset); +} + +static void +_flcnRiscvRegWrite_LS10 +( + nvswitch_device *device, + PFLCN pFlcn, + NvU32 offset, + NvU32 data +) +{ + // Probably should perform some checks on the offset, the device, and the engine descriptor + nvswitch_reg_write_32(device, NV_FALCON2_SOE_BASE + offset, data); +} + +/*! + * @brief Retrieve the size of the falcon data memory. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pFlcn Falcon object pointer + * @param[in] bFalconReachable If set, returns size that can be reached by Falcon + * + * @return IMEM size in bytes + */ +static NvU32 +_flcnDmemSize_LS10 +( + nvswitch_device *device, + PFLCN pFlcn +) +{ + NvU32 data = flcnRegRead_HAL(device, pFlcn, NV_PFALCON_FALCON_HWCFG3); + return (DRF_VAL(_PFALCON, _FALCON_HWCFG3, _DMEM_TOTAL_SIZE, data) << + FALCON_DMEM_BLKSIZE2); +} + +/* + * @brief Get the destination after masking + * off all but the OFFSET and BLOCK in IMEM + * + * @param[in] dst Destination in IMEM + * + * @returns dst with only OFFSET and BLOCK bits set + */ +static NvU32 +_flcnSetImemAddr_LS10 +( + nvswitch_device *device, + PFLCN pFlcn, + NvU32 dst +) +{ + NVSWITCH_ASSERT(0); + return 0; +} + +/*! + * + * @brief Copy contents of pSrc to IMEM + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pFlcn Falcon object pointer + * @param[in] dst Destination in IMEM + * @param[in] pSrc IMEM contents + * @param[in] sizeInBytes Total IMEM size in bytes + * @param[in] bSecure NV_TRUE if IMEM is signed + * @param[in] tag IMEM tag + * @param[in] port PMB port to copy IMEM + * + * @returns void + */ +static void +_flcnImemCopyTo_LS10 +( + nvswitch_device *device, + PFLCN pFlcn, + NvU32 dst, + NvU8 *pSrc, + NvU32 sizeBytes, + NvBool bSecure, + NvU32 tag, + NvU8 port +) +{ +} + +/*! + * + * @brief Mask the DMEM destination to have only the BLK and OFFSET bits set + * + * @param[in] dst Destination in DMEM + * + * @returns masked destination value in DMEM + */ + +static NvU32 +_flcnSetDmemAddr_LS10 +( + nvswitch_device *device, + PFLCN pFlcn, + NvU32 dst +) +{ + return (dst & (DRF_SHIFTMASK(NV_PFALCON_FALCON_DMEMC_OFFS) | + DRF_SHIFTMASK(NV_PFALCON_FALCON_DMEMC_BLK))); +} + +/*! + * Depending on the direction of the copy, copies 'sizeBytes' to/from 'pBuf' + * from/to DMEM offset 'dmemAddr' using DMEM access port 'port'. + * + * @param[in] pGpu GPU object pointer + * @param[in] pFlcn Falcon object pointer + * @param[in] dmemAddr The DMEM offset for the copy + * @param[in] pBuf The pointer to the buffer containing the data to copy + * @param[in] sizeBytes The number of bytes to copy + * @param[in] port The DMEM port index to use when accessing DMEM + * @param[in] bCopyFrom Boolean representing the copy direction (to/from DMEM) + * + * @return NV_OK if the data was successfully copied + * NV_ERR_INVALID_ARGUMENT if the input argument(s) is/are invalid + */ +static NV_STATUS +_flcnDmemTransfer_LS10 +( + nvswitch_device *device, + PFLCN pFlcn, + NvU32 dmemAddr, + NvU8 *pBuf, + NvU32 sizeBytes, + NvU8 port, + NvBool bCopyFrom +) +{ + NvU32 numWords; + NvU32 numBytes; + NvU32 *pData = (NvU32 *)pBuf; + NvU32 reg32; + NvU32 i; + + // simply return if the copy-size is zero + if (sizeBytes == 0) + { + NVSWITCH_PRINT(device, ERROR, "Zero-byte copy requested\n"); + NVSWITCH_ASSERT(0); + return -NVL_BAD_ARGS; + } + + // the DMEM address must be 4-byte aligned + if (!NV_IS_ALIGNED(dmemAddr, FLCN_DMEM_ACCESS_ALIGNMENT)) + { + NVSWITCH_PRINT(device, ERROR, "Source not 4-byte aligned. dmemAddr=0x%08x\n", dmemAddr); + NVSWITCH_ASSERT(0); + return -NVL_BAD_ARGS; + } + + // calculate the number of words and bytes + numWords = sizeBytes >> 2; + numBytes = sizeBytes & NVSWITCH_MASK_BITS(2); + + // mask off all but the OFFSET and BLOCK in DMEM offset + reg32 = flcnSetDmemAddr_HAL(device, pFlcn, dmemAddr); + + if (bCopyFrom) + { + // mark auto-increment on read + reg32 = FLD_SET_DRF_NUM(_PFALCON, _FALCON_DMEMC, _AINCR, 0x1, reg32); + } + else + { + // mark auto-increment on write + reg32 = FLD_SET_DRF_NUM(_PFALCON, _FALCON_DMEMC, _AINCW, 0x1, reg32); + } + + flcnRegWrite_HAL(device, pFlcn, NV_PFALCON_FALCON_DMEMC(port), reg32); + + // directly copy as many words as possible + for (i = 0; i < numWords; i++) + { + if (bCopyFrom) + { + pData[i] = flcnRegRead_HAL(device, pFlcn, NV_PFALCON_FALCON_DMEMD(port)); + } + else + { + flcnRegWrite_HAL(device, pFlcn, NV_PFALCON_FALCON_DMEMD(port), pData[i]); + } + } + + // Check if there are left over bytes to copy + if (numBytes > 0) + { + NvU32 bytesCopied = numWords << 2; + + // + // Read the contents first. If we're copying to the DMEM, we've set + // autoincrement on write, so reading does not modify the pointer. We + // can, thus, do a read/modify/write without needing to worry about the + // pointer having moved forward. There is no special explanation needed + // if we're copying from the DMEM since this is the last access to HW + // in that case. + // + reg32 = flcnRegRead_HAL(device, pFlcn, NV_PFALCON_FALCON_DMEMD(port)); + + if (bCopyFrom) + { + // Copy byte-by-byte into the buffer as required + for (i = 0; i < numBytes; i++) + { + pBuf[bytesCopied + i] = ((NvU8 *)®32)[i]; + } + } + else + { + // Modify what we read byte-by-byte before writing to dmem + for (i = 0; i < numBytes; i++) + { + ((NvU8 *)®32)[i] = pBuf[bytesCopied + i]; + } + flcnRegWrite_HAL(device, pFlcn, NV_PFALCON_FALCON_DMEMD(port), reg32); + } + } + return NVL_SUCCESS; +} + +static void +_flcnDbgInfoCaptureRiscvPcTrace_LS10 +( + nvswitch_device *device, + PFLCN pFlcn +) +{ + NvU32 ctl, ridx, widx, count, bufferSize; + NvBool full; + + flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACECTL, + DRF_DEF(_PRISCV_RISCV, _TRACECTL, _MODE, _FULL) | + DRF_DEF(_PRISCV_RISCV, _TRACECTL, _UMODE_ENABLE, _TRUE) | + DRF_DEF(_PRISCV_RISCV, _TRACECTL, _MMODE_ENABLE, _TRUE) | + DRF_DEF(_PRISCV_RISCV, _TRACECTL, _INTR_ENABLE, _FALSE) | + DRF_DEF(_PRISCV_RISCV, _TRACECTL, _HIGH_THSHD, _INIT)); + + ctl = flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACECTL); + + full = FLD_TEST_DRF_NUM(_PRISCV_RISCV, _TRACECTL,_FULL, 1, ctl); + + if (full) + { + NVSWITCH_PRINT(device, INFO, "%s: Trace buffer full. Entries may have been lost.\n", __FUNCTION__); + } + + // Reset and disable buffer, we don't need it during dump + flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACECTL, 0); + + widx = flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACE_WTIDX); + widx = DRF_VAL(_PRISCV_RISCV, _TRACE_WTIDX, _WTIDX, widx); + + ridx = flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACE_RDIDX); + bufferSize = DRF_VAL(_PRISCV_RISCV, _TRACE_RDIDX, _MAXIDX, ridx); + ridx = DRF_VAL(_PRISCV_RISCV, _TRACE_RDIDX, _RDIDX, ridx); + + count = widx > ridx ? widx - ridx : bufferSize + widx - ridx; + + // + // Trace buffer is full when write idx == read idx and full is set, + // otherwise it is empty. + // + if (widx == ridx && !full) + count = 0; + + if (count) + { + NvU32 entry; + NVSWITCH_PRINT(device, INFO, "%s: Tracebuffer has %d entries. Starting with latest.\n", __FUNCTION__, count); + ridx = widx; + for (entry = 0; entry < count; ++entry) + { + NvU64 pc; + + ridx = ridx > 0 ? ridx - 1 : bufferSize - 1; + flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACE_RDIDX, DRF_NUM(_PRISCV_RISCV, _TRACE_RDIDX, _RDIDX, ridx)); + pc = flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACEPC_HI); + pc = (pc << 32) | flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACEPC_LO); + NVSWITCH_PRINT(device, INFO, "%s: TRACE[%d] = 0x%16llx\n", __FUNCTION__, entry, pc); + } + } + else + { + NVSWITCH_PRINT(device, INFO, "%s: Trace buffer is empty.\n", __FUNCTION__); + } + + // reset trace buffer + flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACE_RDIDX, 0); + flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACE_WTIDX, 0); + + // Clear full and empty bits + ctl = FLD_SET_DRF_NUM(_PRISCV_RISCV, _TRACECTL, _FULL, 0, ctl); + ctl = FLD_SET_DRF_NUM(_PRISCV_RISCV, _TRACECTL, _EMPTY, 0, ctl); + flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACECTL, ctl); +} + +/** + * @brief set hal function pointers for functions defined in + * LS10 (i.e. this file) + * + * this function has to be at the end of the file so that all the + * other functions are already defined. + * + * @param[in] pFlcn The flcn for which to set hals + */ +void +flcnSetupHal_LS10 +( + PFLCN pFlcn +) +{ + flcn_hal *pHal = pFlcn->pHal; + + flcnSetupHal_LR10(pFlcn); + pHal->riscvRegRead = _flcnRiscvRegRead_LS10; + pHal->riscvRegWrite = _flcnRiscvRegWrite_LS10; + pHal->dmemTransfer = _flcnDmemTransfer_LS10; + pHal->setDmemAddr = _flcnSetDmemAddr_LS10; + pHal->imemCopyTo = _flcnImemCopyTo_LS10; + pHal->setImemAddr = _flcnSetImemAddr_LS10; + pHal->dmemSize = _flcnDmemSize_LS10; + pHal->dbgInfoCaptureRiscvPcTrace = _flcnDbgInfoCaptureRiscvPcTrace_LS10; +} + diff --git a/src/common/nvswitch/kernel/ls10/inforom_ls10.c b/src/common/nvswitch/kernel/ls10/inforom_ls10.c new file mode 100644 index 000000000..81a5d5120 --- /dev/null +++ b/src/common/nvswitch/kernel/ls10/inforom_ls10.c @@ -0,0 +1,257 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include "common_nvswitch.h" +#include "ls10/ls10.h" +#include "ls10/inforom_ls10.h" +#include "inforom/ifrstruct.h" +#include "soe/soeififr.h" +#include "rmsoecmdif.h" +#include "flcn/flcn_nvswitch.h" +#include "rmflcncmdif_nvswitch.h" + +NvlStatus +nvswitch_inforom_nvl_log_error_event_ls10 +( + nvswitch_device *device, + void *pNvlGeneric, + void *pNvlErrorEvent, + NvBool *bDirty +) +{ + return -NVL_ERR_NOT_IMPLEMENTED; +} + +NvlStatus nvswitch_inforom_nvl_update_link_correctable_error_info_ls10 +( + nvswitch_device *device, + void *pNvlGeneric, + void *pData, + NvU8 linkId, + NvU8 nvliptInstance, + NvU8 localLinkIdx, + void *pNvlErrorCounts, + NvBool *bDirty +) +{ + return -NVL_ERR_NOT_IMPLEMENTED; +} + +NvlStatus +nvswitch_oms_inforom_flush_ls10 +( + nvswitch_device *device +) +{ + return -NVL_ERR_NOT_IMPLEMENTED; +} + +void +nvswitch_initialize_oms_state_ls10 +( + nvswitch_device *device, + INFOROM_OMS_STATE *pOmsState +) +{ + return; +} + +NvBool +nvswitch_oms_get_device_disable_ls10 +( + INFOROM_OMS_STATE *pOmsState +) +{ + return NV_FALSE; +} + +void +nvswitch_oms_set_device_disable_ls10 +( + INFOROM_OMS_STATE *pOmsState, + NvBool bForceDeviceDisable +) +{ + return; +} + +void +nvswitch_inforom_ecc_get_total_errors_ls10 +( + nvswitch_device *device, + INFOROM_ECC_OBJECT *pEccGeneric, + NvU64 *pCorrectedTotal, + NvU64 *pUncorrectedTotal +) +{ + return; +} + +NvlStatus +nvswitch_bbx_add_sxid_ls10 +( + nvswitch_device *device, + NvU32 exceptionType, + NvU32 data0, + NvU32 data1, + NvU32 data2 +) +{ + NvlStatus status; + FLCN *pFlcn; + RM_FLCN_CMD_SOE bbxCmd; + NvU32 cmdSeqDesc; + NVSWITCH_TIMEOUT timeout; + + if (!nvswitch_is_inforom_supported_ls10(device)) + { + NVSWITCH_PRINT(device, INFO, "InfoROM is not supported, skipping\n"); + return NVL_SUCCESS; + } + + // Avoid logging SOE related SXIDs to prevent recursive errors + if (exceptionType > NVSWITCH_ERR_HW_SOE && exceptionType < NVSWITCH_ERR_HW_SOE_LAST) + { + NVSWITCH_PRINT(device, INFO, "Not logging SXID: %d to InfoROM\n", exceptionType); + return NVL_SUCCESS; + } + + pFlcn = device->pSoe->pFlcn; + nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout); + + nvswitch_os_memset(&bbxCmd, 0, sizeof(bbxCmd)); + bbxCmd.hdr.unitId = RM_SOE_UNIT_IFR; + bbxCmd.hdr.size = sizeof(bbxCmd); + bbxCmd.cmd.ifr.cmdType = RM_SOE_IFR_BBX_SXID_ADD; + bbxCmd.cmd.ifr.bbxSxidAdd.exceptionType = exceptionType; + bbxCmd.cmd.ifr.bbxSxidAdd.data[0] = data0; + bbxCmd.cmd.ifr.bbxSxidAdd.data[1] = data1; + bbxCmd.cmd.ifr.bbxSxidAdd.data[2] = data2; + + status = flcnQueueCmdPostBlocking(device, pFlcn, + (PRM_FLCN_CMD)&bbxCmd, + NULL, // pMsg + NULL, // pPayload + SOE_RM_CMDQ_LOG_ID, + &cmdSeqDesc, + &timeout); + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, "%s: BBX cmd %d failed. rc:%d\n", + __FUNCTION__, bbxCmd.cmd.ifr.cmdType, status); + } + + return status; +} + +NvlStatus +nvswitch_bbx_unload_ls10 +( + nvswitch_device *device +) +{ + NvlStatus status; + FLCN *pFlcn; + RM_FLCN_CMD_SOE bbxCmd; + NvU32 cmdSeqDesc; + NVSWITCH_TIMEOUT timeout; + + pFlcn = device->pSoe->pFlcn; + nvswitch_timeout_create(NVSWITCH_INTERVAL_750MSEC_IN_NS, &timeout); + + nvswitch_os_memset(&bbxCmd, 0, sizeof(bbxCmd)); + bbxCmd.hdr.unitId = RM_SOE_UNIT_IFR; + bbxCmd.hdr.size = sizeof(bbxCmd); + bbxCmd.cmd.ifr.cmdType = RM_SOE_IFR_BBX_SHUTDOWN; + + status = flcnQueueCmdPostBlocking(device, pFlcn, + (PRM_FLCN_CMD)&bbxCmd, + NULL, // pMsg + NULL, // pPayload + SOE_RM_CMDQ_LOG_ID, + &cmdSeqDesc, + &timeout); + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, "%s: BBX cmd %d failed. rc:%d\n", + __FUNCTION__, bbxCmd.cmd.ifr.cmdType, status); + } + + return status; +} + +NvlStatus +nvswitch_bbx_load_ls10 +( + nvswitch_device *device, + NvU64 time_ns, + NvU8 osType, + NvU32 osVersion +) +{ + NvlStatus status; + FLCN *pFlcn; + RM_FLCN_CMD_SOE bbxCmd; + NvU32 cmdSeqDesc = 0; + NVSWITCH_TIMEOUT timeout; + + pFlcn = device->pSoe->pFlcn; + nvswitch_timeout_create(NVSWITCH_INTERVAL_750MSEC_IN_NS, &timeout); + + nvswitch_os_memset(&bbxCmd, 0, sizeof(bbxCmd)); + bbxCmd.hdr.unitId = RM_SOE_UNIT_IFR; + bbxCmd.hdr.size = sizeof(bbxCmd); + bbxCmd.cmd.ifr.cmdType = RM_SOE_IFR_BBX_INITIALIZE; + bbxCmd.cmd.ifr.bbxInit.osType = osType; + bbxCmd.cmd.ifr.bbxInit.osVersion = osVersion; + RM_FLCN_U64_PACK(&bbxCmd.cmd.ifr.bbxInit.time, &time_ns); + + NVSWITCH_PRINT(device, INFO, "RM_SOE_IFR_BBX_INITIALIZE called, time_ns=%llu \n", time_ns); + + status = flcnQueueCmdPostBlocking(device, pFlcn, + (PRM_FLCN_CMD)&bbxCmd, + NULL, // pMsg + NULL, // pPayload + SOE_RM_CMDQ_LOG_ID, + &cmdSeqDesc, + &timeout); + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, "%s: BBX cmd %d failed. rc:%d\n", + __FUNCTION__, bbxCmd.cmd.ifr.cmdType, status); + } + + return status; +} + +NvlStatus +nvswitch_bbx_get_sxid_ls10 +( + nvswitch_device *device, + NVSWITCH_GET_SXIDS_PARAMS *params +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + diff --git a/src/common/nvswitch/kernel/ls10/intr_ls10.c b/src/common/nvswitch/kernel/ls10/intr_ls10.c new file mode 100644 index 000000000..de76ed7d0 --- /dev/null +++ b/src/common/nvswitch/kernel/ls10/intr_ls10.c @@ -0,0 +1,7294 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "common_nvswitch.h" +#include "intr_nvswitch.h" +#include "regkey_nvswitch.h" + +#include "ls10/ls10.h" +#include "ls10/minion_ls10.h" + +#include "nvswitch/ls10/dev_ctrl_ip.h" +#include "nvswitch/ls10/dev_pri_masterstation_ip.h" +#include "nvswitch/ls10/dev_pri_hub_sys_ip.h" +#include "nvswitch/ls10/dev_pri_hub_sysb_ip.h" +#include "nvswitch/ls10/dev_pri_hub_prt_ip.h" + +#include "nvswitch/ls10/dev_npg_ip.h" +#include "nvswitch/ls10/dev_nport_ip.h" +#include "nvswitch/ls10/dev_route_ip.h" +#include "nvswitch/ls10/dev_ingress_ip.h" +#include "nvswitch/ls10/dev_sourcetrack_ip.h" +#include "nvswitch/ls10/dev_egress_ip.h" +#include "nvswitch/ls10/dev_tstate_ip.h" +#include "nvswitch/ls10/dev_multicasttstate_ip.h" +#include "nvswitch/ls10/dev_reductiontstate_ip.h" + +#include "nvswitch/ls10/dev_nvlw_ip.h" +#include "nvswitch/ls10/dev_minion_ip.h" +#include "nvswitch/ls10/dev_cpr_ip.h" +#include "nvswitch/ls10/dev_nvlipt_ip.h" +#include "nvswitch/ls10/dev_nvlipt_lnk_ip.h" +#include "nvswitch/ls10/dev_nvltlc_ip.h" +#include "nvswitch/ls10/dev_nvldl_ip.h" + +#include "nvswitch/ls10/dev_nxbar_tcp_global_ip.h" +#include "nvswitch/ls10/dev_nxbar_tile_ip.h" +#include "nvswitch/ls10/dev_nxbar_tileout_ip.h" + +#include "nvswitch/ls10/dev_ctrl_ip_addendum.h" + +static void +_nvswitch_construct_ecc_error_event_ls10 +( + INFOROM_NVS_ECC_ERROR_EVENT *err_event, + NvU32 sxid, + NvU32 linkId, + NvBool bAddressValid, + NvU32 address, + NvBool bUncErr, + NvU32 errorCount +) +{ + err_event->sxid = sxid; + err_event->linkId = linkId; + err_event->bAddressValid = bAddressValid; + err_event->address = address; + err_event->bUncErr = bUncErr; + err_event->errorCount = errorCount; +} + +static void +_nvswitch_initialize_minion_interrupts +( + nvswitch_device *device, + NvU32 instance +) +{ + NvU32 intrEn, localDiscoveredLinks, globalLink, i; + localDiscoveredLinks = 0; + + // Tree 1 (non-stall) is disabled until there is a need + NVSWITCH_MINION_WR32_LS10(device, instance, _MINION, _MINION_INTR_NONSTALL_EN, 0); + + // Tree 0 (stall) is where we route _all_ MINION interrupts for now + intrEn = DRF_DEF(_MINION, _MINION_INTR_STALL_EN, _FATAL, _ENABLE) | + DRF_DEF(_MINION, _MINION_INTR_STALL_EN, _NONFATAL, _ENABLE) | + DRF_DEF(_MINION, _MINION_INTR_STALL_EN, _FALCON_STALL, _ENABLE) | + DRF_DEF(_MINION, _MINION_INTR_STALL_EN, _FALCON_NOSTALL, _DISABLE); + + for (i = 0; i < NVSWITCH_LINKS_PER_MINION_LS10; ++i) + { + // get the global link number of the link we are iterating over + globalLink = (instance * NVSWITCH_LINKS_PER_MINION_LS10) + i; + + // the link is valid place bit in link mask + if (device->link[globalLink].valid) + { + localDiscoveredLinks |= NVBIT(i); + } + } + + intrEn = FLD_SET_DRF_NUM(_MINION, _MINION_INTR_STALL_EN, _LINK, + localDiscoveredLinks, intrEn); + + { + // Disable interrupts only if explicitly requested to. Default to enable. + if (device->regkeys.minion_intr != NV_SWITCH_REGKEY_MINION_INTERRUPTS_DISABLE) + { + NVSWITCH_MINION_WR32_LS10(device, instance, _MINION, _MINION_INTR_STALL_EN, intrEn); + } + } +} + +static void +_nvswitch_initialize_nvlipt_interrupts_ls10 +( + nvswitch_device *device +) +{ + NvU32 i; + NvU32 regval = 0; + + // + // NVLipt interrupt routing (NVLIPT_COMMON, NVLIPT_LNK, NVLDL, NVLTLC) + // will be initialized by MINION NVLPROD flow + // + // We must enable interrupts at the top levels in NVLW, NVLIPT_COMMON, + // NVLIPT_LNK and MINION + // + + // NVLW + regval = DRF_NUM(_NVLW_COMMON, _INTR_0_MASK, _FATAL, 0x1) | + DRF_NUM(_NVLW_COMMON, _INTR_0_MASK, _NONFATAL, 0x0) | + DRF_NUM(_NVLW_COMMON, _INTR_0_MASK, _CORRECTABLE, 0x0) | + DRF_NUM(_NVLW_COMMON, _INTR_0_MASK, _INTR0, 0x1) | + DRF_NUM(_NVLW_COMMON, _INTR_0_MASK, _INTR1, 0x0); + NVSWITCH_BCAST_WR32_LS10(device, NVLW, _NVLW_COMMON, _INTR_0_MASK, regval); + + regval = DRF_NUM(_NVLW_COMMON, _INTR_1_MASK, _FATAL, 0x0) | + DRF_NUM(_NVLW_COMMON, _INTR_1_MASK, _NONFATAL, 0x1) | + DRF_NUM(_NVLW_COMMON, _INTR_1_MASK, _CORRECTABLE, 0x1) | + DRF_NUM(_NVLW_COMMON, _INTR_1_MASK, _INTR0, 0x0) | + DRF_NUM(_NVLW_COMMON, _INTR_1_MASK, _INTR1, 0x1); + NVSWITCH_BCAST_WR32_LS10(device, NVLW, _NVLW_COMMON, _INTR_1_MASK, regval); + + regval = DRF_NUM(_NVLW_COMMON, _INTR_2_MASK, _FATAL, 0x0) | + DRF_NUM(_NVLW_COMMON, _INTR_2_MASK, _NONFATAL, 0x0) | + DRF_NUM(_NVLW_COMMON, _INTR_2_MASK, _CORRECTABLE, 0x0) | + DRF_NUM(_NVLW_COMMON, _INTR_2_MASK, _INTR0, 0x0) | + DRF_NUM(_NVLW_COMMON, _INTR_2_MASK, _INTR1, 0x0); + NVSWITCH_BCAST_WR32_LS10(device, NVLW, _NVLW_COMMON, _INTR_2_MASK, regval); + + // NVLW link + for (i = 0; i < NV_NVLW_LINK_INTR_0_MASK__SIZE_1; i++) + { + regval = DRF_NUM(_NVLW_LINK, _INTR_0_MASK, _FATAL, 0x1) | + DRF_NUM(_NVLW_LINK, _INTR_0_MASK, _NONFATAL, 0x0) | + DRF_NUM(_NVLW_LINK, _INTR_0_MASK, _CORRECTABLE, 0x0) | + DRF_NUM(_NVLW_LINK, _INTR_0_MASK, _INTR0, 0x1) | + DRF_NUM(_NVLW_LINK, _INTR_0_MASK, _INTR1, 0x0); + NVSWITCH_BCAST_WR32_LS10(device, NVLW, _NVLW_LINK, _INTR_0_MASK(i), regval); + + regval = DRF_NUM(_NVLW_LINK, _INTR_1_MASK, _FATAL, 0x0) | + DRF_NUM(_NVLW_LINK, _INTR_1_MASK, _NONFATAL, 0x1) | + DRF_NUM(_NVLW_LINK, _INTR_1_MASK, _CORRECTABLE, 0x1) | + DRF_NUM(_NVLW_LINK, _INTR_1_MASK, _INTR0, 0x0) | + DRF_NUM(_NVLW_LINK, _INTR_1_MASK, _INTR1, 0x1); + NVSWITCH_BCAST_WR32_LS10(device, NVLW, _NVLW_LINK, _INTR_1_MASK(i), regval); + + regval = DRF_NUM(_NVLW_LINK, _INTR_2_MASK, _FATAL, 0x0) | + DRF_NUM(_NVLW_LINK, _INTR_2_MASK, _NONFATAL, 0x0) | + DRF_NUM(_NVLW_LINK, _INTR_2_MASK, _CORRECTABLE, 0x0) | + DRF_NUM(_NVLW_LINK, _INTR_2_MASK, _INTR0, 0x0) | + DRF_NUM(_NVLW_LINK, _INTR_2_MASK, _INTR1, 0x0); + NVSWITCH_BCAST_WR32_LS10(device, NVLW, _NVLW_LINK, _INTR_2_MASK(i), regval); + } + + // NVLIPT_COMMON + regval = DRF_NUM(_NVLIPT_COMMON, _INTR_CONTROL_COMMON, _INT0_EN, 0x1) | + DRF_NUM(_NVLIPT_COMMON, _INTR_CONTROL_COMMON, _INT1_EN, 0x1); + + NVSWITCH_BCAST_WR32_LS10(device, NVLIPT, _NVLIPT_COMMON, _INTR_CONTROL_COMMON, regval); + + // NVLIPT_LNK + regval = DRF_NUM(_NVLIPT_LNK, _INTR_CONTROL_LINK, _INT0_EN, 0x1) | + DRF_NUM(_NVLIPT_LNK, _INTR_CONTROL_LINK, _INT1_EN, 0x1); + NVSWITCH_BCAST_WR32_LS10(device, NVLIPT_LNK, _NVLIPT_LNK, _INTR_CONTROL_LINK, regval); + + // NVLIPT_LNK_INTR_1 + regval = DRF_NUM(_NVLIPT_LNK, _INTR_INT1_EN, _LINKSTATEREQUESTREADYSET, 0x1); + NVSWITCH_BCAST_WR32_LS10(device, NVLIPT_LNK, _NVLIPT_LNK, _INTR_INT1_EN, regval); + + // MINION + for (i = 0; i < NUM_MINION_ENGINE_LS10; ++i) + { + if (!NVSWITCH_ENG_VALID_LS10(device, MINION, i)) + { + continue; + } + + _nvswitch_initialize_minion_interrupts(device,i); + } + + // CPR + + regval = NVSWITCH_ENG_RD32(device, CPR, _BCAST, 0, _CPR_SYS, _ERR_LOG_EN_0); + regval = FLD_SET_DRF(_CPR_SYS, _ERR_LOG_EN_0, _ENGINE_RESET_ERR, __PROD, regval); + NVSWITCH_ENG_WR32(device, CPR, _BCAST, 0, _CPR_SYS, _ERR_LOG_EN_0, regval); + + regval = DRF_DEF(_CPR_SYS, _NVLW_INTR_0_MASK, _CPR_INTR, _ENABLE) | + DRF_DEF(_CPR_SYS, _NVLW_INTR_0_MASK, _INTR0, _ENABLE); + NVSWITCH_ENG_WR32(device, CPR, _BCAST, 0, _CPR_SYS, _NVLW_INTR_0_MASK, regval); + + regval = DRF_DEF(_CPR_SYS, _NVLW_INTR_1_MASK, _CPR_INTR, _DISABLE) | + DRF_DEF(_CPR_SYS, _NVLW_INTR_1_MASK, _INTR1, _ENABLE); + NVSWITCH_ENG_WR32(device, CPR, _BCAST, 0, _CPR_SYS, _NVLW_INTR_1_MASK, regval); + + regval = DRF_DEF(_CPR_SYS, _NVLW_INTR_2_MASK, _CPR_INTR, _DISABLE) | + DRF_DEF(_CPR_SYS, _NVLW_INTR_2_MASK, _INTR2, _ENABLE); + NVSWITCH_ENG_WR32(device, CPR, _BCAST, 0, _CPR_SYS, _NVLW_INTR_2_MASK, regval); +} + +static void +_nvswitch_initialize_route_interrupts +( + nvswitch_device *device +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + + chip_device->intr_mask.route.fatal = + DRF_DEF(_ROUTE, _ERR_FATAL_REPORT_EN_0, _ROUTEBUFERR, _ENABLE) | + DRF_DEF(_ROUTE, _ERR_FATAL_REPORT_EN_0, _GLT_ECC_DBE_ERR, _ENABLE) | + DRF_DEF(_ROUTE, _ERR_FATAL_REPORT_EN_0, _PDCTRLPARERR, _ENABLE) | + DRF_DEF(_ROUTE, _ERR_FATAL_REPORT_EN_0, _NVS_ECC_DBE_ERR, _ENABLE) | + DRF_DEF(_ROUTE, _ERR_FATAL_REPORT_EN_0, _CDTPARERR, _ENABLE) | + DRF_DEF(_ROUTE, _ERR_FATAL_REPORT_EN_0, _MCRID_ECC_DBE_ERR, _ENABLE) | + DRF_DEF(_ROUTE, _ERR_FATAL_REPORT_EN_0, _EXTMCRID_ECC_DBE_ERR, _ENABLE) | + DRF_DEF(_ROUTE, _ERR_FATAL_REPORT_EN_0, _RAM_ECC_DBE_ERR, _ENABLE); + + chip_device->intr_mask.route.nonfatal = + DRF_DEF(_ROUTE, _ERR_NON_FATAL_REPORT_EN_0, _NOPORTDEFINEDERR, _ENABLE) | + DRF_DEF(_ROUTE, _ERR_NON_FATAL_REPORT_EN_0, _INVALIDROUTEPOLICYERR, _ENABLE) | + DRF_DEF(_ROUTE, _ERR_NON_FATAL_REPORT_EN_0, _GLT_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_ROUTE, _ERR_NON_FATAL_REPORT_EN_0, _NVS_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_ROUTE, _ERR_NON_FATAL_REPORT_EN_0, _MCRID_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_ROUTE, _ERR_NON_FATAL_REPORT_EN_0, _EXTMCRID_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_ROUTE, _ERR_NON_FATAL_REPORT_EN_0, _RAM_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_ROUTE, _ERR_NON_FATAL_REPORT_EN_0, _INVALID_MCRID_ERR, _ENABLE); + // NOTE: _MC_TRIGGER_ERR is debug-use only +} + +static void +_nvswitch_initialize_ingress_interrupts +( + nvswitch_device *device +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + + chip_device->intr_mask.ingress[0].fatal = + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _CMDDECODEERR, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _EXTAREMAPTAB_ECC_DBE_ERR, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _NCISOC_HDR_ECC_DBE_ERR, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _INVALIDVCSET, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _REMAPTAB_ECC_DBE_ERR, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _RIDTAB_ECC_DBE_ERR, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _RLANTAB_ECC_DBE_ERR, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _NCISOC_PARITY_ERR, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _EXTBREMAPTAB_ECC_DBE_ERR, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _MCREMAPTAB_ECC_DBE_ERR, _ENABLE); + + chip_device->intr_mask.ingress[0].nonfatal = + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _REQCONTEXTMISMATCHERR, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _ACLFAIL, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _NCISOC_HDR_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _ADDRBOUNDSERR, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _RIDTABCFGERR, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _RLANTABCFGERR, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _REMAPTAB_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _RIDTAB_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _RLANTAB_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _ADDRTYPEERR, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_INDEX_ERR, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_INDEX_ERR, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_INDEX_ERR, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_REQCONTEXTMISMATCHERR, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_REQCONTEXTMISMATCHERR, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_REQCONTEXTMISMATCHERR, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_ACLFAIL, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_ACLFAIL, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_ACLFAIL, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_ADDRBOUNDSERR, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_ADDRBOUNDSERR, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_ADDRBOUNDSERR, _ENABLE); + + chip_device->intr_mask.ingress[1].fatal = 0; + + chip_device->intr_mask.ingress[1].nonfatal = + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _EXTAREMAPTAB_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _EXTBREMAPTAB_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCREMAPTAB_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCCMDTOUCADDRERR, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _READMCREFLECTMEMERR, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _EXTAREMAPTAB_ADDRTYPEERR, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _EXTBREMAPTAB_ADDRTYPEERR, _ENABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCREMAPTAB_ADDRTYPEERR, _ENABLE); +} + +static void +_nvswitch_initialize_egress_interrupts +( + nvswitch_device *device +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + + chip_device->intr_mask.egress[0].fatal = + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _EGRESSBUFERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _PKTROUTEERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _SEQIDERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _NXBAR_HDR_ECC_DBE_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _RAM_OUT_HDR_ECC_DBE_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _NCISOCCREDITOVFL, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _REQTGTIDMISMATCHERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _RSPREQIDMISMATCHERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _NXBAR_HDR_PARITY_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _NCISOC_CREDIT_PARITY_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _NXBAR_FLITTYPE_MISMATCH_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _CREDIT_TIME_OUT_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _INVALIDVCSET_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _NXBAR_SIDEBAND_PD_PARITY_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _URRSPERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _HWRSPERR, _ENABLE); + + chip_device->intr_mask.egress[0].nonfatal = + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _NXBAR_HDR_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _RAM_OUT_HDR_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _PRIVRSPERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _RFU, _DISABLE); + + chip_device->intr_mask.egress[1].fatal = + + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_1, _MCRSPCTRLSTORE_ECC_DBE_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_1, _RBCTRLSTORE_ECC_DBE_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_1, _MCREDSGT_ECC_DBE_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_1, _MCRSP_RAM_HDR_ECC_DBE_ERR, _ENABLE); + + chip_device->intr_mask.egress[1].nonfatal = + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCRSPCTRLSTORE_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _RBCTRLSTORE_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCREDSGT_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCREDBUF_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCRSP_RAM_HDR_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _NXBAR_REDUCTION_HDR_ECC_DBE_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _NXBAR_REDUCTION_HDR_PARITY_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCREDBUF_ECC_DBE_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCRSP_CNT_ERR, _ENABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _RBRSP_CNT_ERR, _ENABLE); +} + +static void +_nvswitch_initialize_tstate_interrupts +( + nvswitch_device *device +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + + chip_device->intr_mask.tstate.fatal = + DRF_DEF(_TSTATE, _ERR_FATAL_REPORT_EN_0, _TAGPOOLBUFERR, _ENABLE) | + DRF_DEF(_TSTATE, _ERR_FATAL_REPORT_EN_0, _TAGPOOL_ECC_DBE_ERR, _ENABLE) | + DRF_DEF(_TSTATE, _ERR_FATAL_REPORT_EN_0, _CRUMBSTOREBUFERR, _ENABLE) | + DRF_DEF(_TSTATE, _ERR_FATAL_REPORT_EN_0, _CRUMBSTORE_ECC_DBE_ERR, _ENABLE) | + DRF_DEF(_TSTATE, _ERR_FATAL_REPORT_EN_0, _ATO_ERR, _ENABLE) | + DRF_DEF(_TSTATE, _ERR_FATAL_REPORT_EN_0, _CAMRSP_ERR, _ENABLE); + + chip_device->intr_mask.tstate.nonfatal = + DRF_DEF(_TSTATE, _ERR_NON_FATAL_REPORT_EN_0, _TAGPOOL_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_TSTATE, _ERR_NON_FATAL_REPORT_EN_0, _CRUMBSTORE_ECC_LIMIT_ERR, _ENABLE); +} + +static void +_nvswitch_initialize_sourcetrack_interrupts +( + nvswitch_device *device +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + + chip_device->intr_mask.sourcetrack.fatal = + DRF_DEF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR, _ENABLE) | + DRF_DEF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _DUP_CREQ_TCEN0_TAG_ERR, _ENABLE) | + DRF_DEF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _INVALID_TCEN0_RSP_ERR, _ENABLE) | + DRF_DEF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _INVALID_TCEN1_RSP_ERR, _ENABLE) | + DRF_DEF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _SOURCETRACK_TIME_OUT_ERR, _ENABLE); + + chip_device->intr_mask.sourcetrack.nonfatal = + DRF_DEF(_SOURCETRACK, _ERR_NON_FATAL_REPORT_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR, _ENABLE); +} + +static void +_nvswitch_initialize_multicast_tstate_interrupts +( + nvswitch_device *device +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + + chip_device->intr_mask.mc_tstate.fatal = + DRF_DEF(_MULTICASTTSTATE, _ERR_FATAL_REPORT_EN_0, _TAGPOOL_ECC_DBE_ERR, _ENABLE) | + DRF_DEF(_MULTICASTTSTATE, _ERR_FATAL_REPORT_EN_0, _CRUMBSTORE_BUF_OVERWRITE_ERR, _ENABLE) | + DRF_DEF(_MULTICASTTSTATE, _ERR_FATAL_REPORT_EN_0, _CRUMBSTORE_ECC_DBE_ERR, _ENABLE); + + chip_device->intr_mask.mc_tstate.nonfatal = + DRF_DEF(_MULTICASTTSTATE, _ERR_NON_FATAL_REPORT_EN_0, _TAGPOOL_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_MULTICASTTSTATE, _ERR_NON_FATAL_REPORT_EN_0, _CRUMBSTORE_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_MULTICASTTSTATE, _ERR_NON_FATAL_REPORT_EN_0, _CRUMBSTORE_MCTO_ERR, _ENABLE); +} + +static void +_nvswitch_initialize_reduction_tstate_interrupts +( + nvswitch_device *device +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + + chip_device->intr_mask.red_tstate.fatal = + DRF_DEF(_REDUCTIONTSTATE, _ERR_FATAL_REPORT_EN_0, _TAGPOOL_ECC_DBE_ERR, _ENABLE) | + DRF_DEF(_REDUCTIONTSTATE, _ERR_FATAL_REPORT_EN_0, _CRUMBSTORE_BUF_OVERWRITE_ERR, _ENABLE) | + DRF_DEF(_REDUCTIONTSTATE, _ERR_FATAL_REPORT_EN_0, _CRUMBSTORE_ECC_DBE_ERR, _ENABLE); + + chip_device->intr_mask.red_tstate.nonfatal = + DRF_DEF(_REDUCTIONTSTATE, _ERR_NON_FATAL_REPORT_EN_0, _TAGPOOL_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_REDUCTIONTSTATE, _ERR_NON_FATAL_REPORT_EN_0, _CRUMBSTORE_ECC_LIMIT_ERR, _ENABLE) | + DRF_DEF(_REDUCTIONTSTATE, _ERR_NON_FATAL_REPORT_EN_0, _CRUMBSTORE_RTO_ERR, _ENABLE); +} + +void +_nvswitch_initialize_nport_interrupts_ls10 +( + nvswitch_device *device +) +{ + NvU32 val; + + val = + DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _CORRECTABLEENABLE, 1) | + DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _FATALENABLE, 1) | + DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _NONFATALENABLE, 1); + NVSWITCH_NPORT_BCAST_WR32_LS10(device, _NPORT, _ERR_CONTROL_COMMON_NPORT, val); + + _nvswitch_initialize_route_interrupts(device); + _nvswitch_initialize_ingress_interrupts(device); + _nvswitch_initialize_egress_interrupts(device); + _nvswitch_initialize_tstate_interrupts(device); + _nvswitch_initialize_sourcetrack_interrupts(device); + _nvswitch_initialize_multicast_tstate_interrupts(device); + _nvswitch_initialize_reduction_tstate_interrupts(device); +} + +void +_nvswitch_initialize_nxbar_interrupts_ls10 +( + nvswitch_device *device +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NvU32 report_fatal; + + report_fatal = + DRF_NUM(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_BUFFER_OVERFLOW, 1) | + DRF_NUM(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_BUFFER_UNDERFLOW, 1) | + DRF_NUM(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _EGRESS_CREDIT_OVERFLOW, 1) | + DRF_NUM(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _EGRESS_CREDIT_UNDERFLOW, 1) | + DRF_NUM(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_NON_BURSTY_PKT, 1) | + DRF_NUM(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_NON_STICKY_PKT, 1) | + DRF_NUM(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_BURST_GT_9_DATA_VC, 1) | + DRF_NUM(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_PKT_INVALID_DST, 1) | + DRF_NUM(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_PKT_PARITY_ERROR, 1) | + DRF_NUM(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_SIDEBAND_PARITY_ERROR, 1) | + DRF_NUM(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_REDUCTION_PKT_ERROR, 1); + + NVSWITCH_BCAST_WR32_LS10(device, NXBAR, _NXBAR_TILE, _ERR_FATAL_INTR_EN, report_fatal); + + chip_device->intr_mask.tile.fatal = report_fatal; + chip_device->intr_mask.tile.nonfatal = 0; + + report_fatal = + DRF_NUM(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _INGRESS_BUFFER_OVERFLOW, 1) | + DRF_NUM(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _INGRESS_BUFFER_UNDERFLOW, 1) | + DRF_NUM(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _EGRESS_CREDIT_OVERFLOW, 1) | + DRF_NUM(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _EGRESS_CREDIT_UNDERFLOW, 1) | + DRF_NUM(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _INGRESS_NON_BURSTY_PKT, 1) | + DRF_NUM(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _INGRESS_NON_STICKY_PKT, 1) | + DRF_NUM(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _INGRESS_BURST_GT_9_DATA_VC, 1) | + DRF_NUM(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _EGRESS_CDT_PARITY_ERROR, 1); + + NVSWITCH_BCAST_WR32_LS10(device, NXBAR, _NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, report_fatal); + + chip_device->intr_mask.tileout.fatal = report_fatal; + chip_device->intr_mask.tileout.nonfatal = 0; +} + +/* + * @brief Service MINION Falcon interrupts on the requested interrupt tree + * Falcon Interrupts are a little unique in how they are handled:#include + * IRQSTAT is used to read in interrupt status from FALCON + * IRQMASK is used to read in mask of interrupts + * IRQDEST is used to read in enabled interrupts that are routed to the HOST + * + * IRQSTAT & IRQMASK gives the pending interrupting on this minion + * + * @param[in] device MINION on this device + * @param[in] instance MINION instance + * + */ +NvlStatus +nvswitch_minion_service_falcon_interrupts_ls10 +( + nvswitch_device *device, + NvU32 instance +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + NvU32 pending, bit, unhandled, intr, link; + + link = instance * NVSWITCH_LINKS_PER_MINION_LS10; + report.raw_pending = NVSWITCH_MINION_RD32_LS10(device, instance, _CMINION, _FALCON_IRQSTAT); + report.raw_enable = chip_device->intr_minion_dest; + report.mask = NVSWITCH_MINION_RD32_LS10(device, instance, _CMINION, _FALCON_IRQMASK); + + pending = report.raw_pending & report.mask; + + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + + bit = DRF_NUM(_CMINION_FALCON, _IRQSTAT, _WDTMR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_MINION_WATCHDOG, "MINION Watchdog timer ran out", NV_TRUE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_CMINION_FALCON, _IRQSTAT, _HALT, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_MINION_HALT, "MINION HALT", NV_TRUE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_CMINION_FALCON, _IRQSTAT, _EXTERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_MINION_EXTERR, "MINION EXTERR", NV_TRUE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_CMINION_FALCON, _IRQSTAT, _SWGEN0, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_PRINT(device, INFO, + "%s: Received MINION Falcon SWGEN0 interrupt on MINION %d.\n", + __FUNCTION__, instance); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_CMINION_FALCON, _IRQSTAT, _SWGEN1, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_PRINT(device, INFO, + "%s: Received MINION Falcon SWGEN1 interrupt on MINION %d.\n", + __FUNCTION__, instance); + nvswitch_clear_flags(&unhandled, bit); + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + if (device->link[link].fatal_error_occurred) + { + intr = NVSWITCH_MINION_RD32_LS10(device, instance, _MINION, _MINION_INTR_STALL_EN); + intr = FLD_SET_DRF(_MINION, _MINION_INTR_STALL_EN, _FATAL, _DISABLE, intr); + intr = FLD_SET_DRF(_MINION, _MINION_INTR_STALL_EN, _FALCON_STALL, _DISABLE, intr); + intr = FLD_SET_DRF(_MINION, _MINION_INTR_STALL_EN, _FATAL, _DISABLE, intr); + intr = FLD_SET_DRF(_MINION, _MINION_INTR_STALL_EN, _NONFATAL, _DISABLE, intr); + NVSWITCH_MINION_WR32_LS10(device, instance, _MINION, _MINION_INTR_STALL_EN, intr); + } + + // Write to IRQSCLR to clear status of interrupt + NVSWITCH_MINION_WR32_LS10(device, instance, _CMINION, _FALCON_IRQSCLR, pending); + + if (unhandled != 0) + { + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +/* + * @Brief : Send priv ring command and wait for completion + * + * @Description : + * + * @param[in] device a reference to the device to initialize + * @param[in] cmd encoded priv ring command + */ +static NvlStatus +_nvswitch_ring_master_cmd_ls10 +( + nvswitch_device *device, + NvU32 cmd +) +{ + NvU32 value; + NVSWITCH_TIMEOUT timeout; + NvBool keepPolling; + + NVSWITCH_ENG_WR32(device, PRI_MASTER_RS, , 0, _PPRIV_MASTER, _RING_COMMAND, cmd); + + nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout); + do + { + keepPolling = (nvswitch_timeout_check(&timeout)) ? NV_FALSE : NV_TRUE; + + value = NVSWITCH_ENG_RD32(device, PRI_MASTER_RS, , 0, _PPRIV_MASTER, _RING_COMMAND); + if (FLD_TEST_DRF(_PPRIV_MASTER, _RING_COMMAND, _CMD, _NO_CMD, value)) + { + break; + } + + nvswitch_os_sleep(1); + } + while (keepPolling); + + if (!FLD_TEST_DRF(_PPRIV_MASTER, _RING_COMMAND, _CMD, _NO_CMD, value)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Timeout waiting for RING_COMMAND == NO_CMD (cmd=0x%x).\n", + __FUNCTION__, cmd); + return -NVL_INITIALIZATION_TOTAL_FAILURE; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_nvswitch_service_priv_ring_ls10 +( + nvswitch_device *device +) +{ + NvU32 pending, i; + NVSWITCH_PRI_ERROR_LOG_TYPE pri_error; + NvlStatus status = NVL_SUCCESS; + + pending = NVSWITCH_ENG_RD32(device, PRI_MASTER_RS, , 0, _PPRIV_MASTER, _RING_INTERRUPT_STATUS0); + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + // + // SYS + // + + if (FLD_TEST_DRF_NUM(_PPRIV_MASTER, _RING_INTERRUPT_STATUS0, + _GBL_WRITE_ERROR_SYS, 1, pending)) + { + pri_error.addr = NVSWITCH_ENG_RD32(device, SYS_PRI_HUB, , 0, _PPRIV_SYS, _PRIV_ERROR_ADR); + pri_error.data = NVSWITCH_ENG_RD32(device, SYS_PRI_HUB, , 0, _PPRIV_SYS, _PRIV_ERROR_WRDAT); + pri_error.info = NVSWITCH_ENG_RD32(device, SYS_PRI_HUB, , 0, _PPRIV_SYS, _PRIV_ERROR_INFO); + pri_error.code = NVSWITCH_ENG_RD32(device, SYS_PRI_HUB, , 0, _PPRIV_SYS, _PRIV_ERROR_CODE); + + NVSWITCH_REPORT_PRI_ERROR_NONFATAL(_HW_HOST_PRIV_ERROR, "PRI WRITE SYS error", NVSWITCH_PPRIV_WRITE_SYS, 0, pri_error); + + NVSWITCH_PRINT(device, ERROR, + "SYS PRI write error addr: 0x%08x data: 0x%08x info: 0x%08x code: 0x%08x\n", + pri_error.addr, pri_error.data, + pri_error.info, pri_error.code); + + pending = FLD_SET_DRF_NUM(_PPRIV_MASTER, _RING_INTERRUPT_STATUS0, + _GBL_WRITE_ERROR_SYS, 0, pending); + } + + // + // SYSB + // + + if (FLD_TEST_DRF_NUM(_PPRIV_MASTER, _RING_INTERRUPT_STATUS0, + _GBL_WRITE_ERROR_SYSB, 1, pending)) + { + pri_error.addr = NVSWITCH_ENG_RD32(device, SYSB_PRI_HUB, , 0, _PPRIV_SYS, _PRIV_ERROR_ADR); + pri_error.data = NVSWITCH_ENG_RD32(device, SYSB_PRI_HUB, , 0, _PPRIV_SYS, _PRIV_ERROR_WRDAT); + pri_error.info = NVSWITCH_ENG_RD32(device, SYSB_PRI_HUB, , 0, _PPRIV_SYS, _PRIV_ERROR_INFO); + pri_error.code = NVSWITCH_ENG_RD32(device, SYSB_PRI_HUB, , 0, _PPRIV_SYS, _PRIV_ERROR_CODE); + + NVSWITCH_REPORT_PRI_ERROR_NONFATAL(_HW_HOST_PRIV_ERROR, "PRI WRITE SYSB error", NVSWITCH_PPRIV_WRITE_SYS, 1, pri_error); + + NVSWITCH_PRINT(device, ERROR, + "SYSB PRI write error addr: 0x%08x data: 0x%08x info: 0x%08x code: 0x%08x\n", + pri_error.addr, pri_error.data, + pri_error.info, pri_error.code); + + pending = FLD_SET_DRF_NUM(_PPRIV_MASTER, _RING_INTERRUPT_STATUS0, + _GBL_WRITE_ERROR_SYSB, 0, pending); + } + + // + // per-PRT + // + + for (i = 0; i < NUM_PRT_PRI_HUB_ENGINE_LS10; i++) + { + if (DRF_VAL(_PPRIV_MASTER, _RING_INTERRUPT_STATUS0, + _GBL_WRITE_ERROR_FBP, pending) & NVBIT(i)) + { + pri_error.addr = NVSWITCH_ENG_RD32(device, PRT_PRI_HUB, , i, _PPRIV_PRT, _PRIV_ERROR_ADR); + pri_error.data = NVSWITCH_ENG_RD32(device, PRT_PRI_HUB, , i, _PPRIV_PRT, _PRIV_ERROR_WRDAT); + pri_error.info = NVSWITCH_ENG_RD32(device, PRT_PRI_HUB, , i, _PPRIV_PRT, _PRIV_ERROR_INFO); + pri_error.code = NVSWITCH_ENG_RD32(device, PRT_PRI_HUB, , i, _PPRIV_PRT, _PRIV_ERROR_CODE); + + NVSWITCH_REPORT_PRI_ERROR_NONFATAL(_HW_HOST_PRIV_ERROR, "PRI WRITE PRT error", NVSWITCH_PPRIV_WRITE_PRT, i, pri_error); + + NVSWITCH_PRINT(device, ERROR, + "PRT%d PRI write error addr: 0x%08x data: 0x%08x info: 0x%08x code: 0x%08x\n", + i, pri_error.addr, pri_error.data, pri_error.info, pri_error.code); + + pending &= ~DRF_NUM(_PPRIV_MASTER, _RING_INTERRUPT_STATUS0, + _GBL_WRITE_ERROR_FBP, NVBIT(i)); + } + } + + if (pending != 0) + { + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_PRIV_ERROR, + "Fatal, Unexpected PRI error\n"); + NVSWITCH_LOG_FATAL_DATA(device, _HW, _HW_HOST_PRIV_ERROR, 2, 0, NV_FALSE, &pending); + + NVSWITCH_PRINT(device, ERROR, + "Unexpected PRI error 0x%08x\n", pending); + return -NVL_MORE_PROCESSING_REQUIRED; + } + + // acknowledge the interrupt to the ringmaster + status = _nvswitch_ring_master_cmd_ls10(device, + DRF_DEF(_PPRIV_MASTER, _RING_COMMAND, _CMD, _ACK_INTERRUPT)); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "Timeout ACK'ing PRI error\n"); + // + // Don't return error code -- there is nothing kernel SW can do about it if ACK failed. + // Likely it is PLM protected and SOE needs to handle it. + // + } + + return NVL_SUCCESS; +} + +static NvlStatus +_nvswitch_collect_nport_error_info_ls10 +( + nvswitch_device *device, + NvU32 link, + NVSWITCH_RAW_ERROR_LOG_TYPE *data, + NvU32 *idx, + NvU32 register_start, + NvU32 register_end +) +{ + NvU32 register_block_size; + NvU32 i = *idx; + + if ((register_start > register_end) || + (register_start % sizeof(NvU32) != 0) || + (register_end % sizeof(NvU32) != 0)) + { + return -NVL_BAD_ARGS; + } + + register_block_size = (register_end - register_start)/sizeof(NvU32) + 1; + if ((i + register_block_size > NVSWITCH_RAW_ERROR_LOG_DATA_SIZE) || + (register_block_size > NVSWITCH_RAW_ERROR_LOG_DATA_SIZE)) + { + return -NVL_BAD_ARGS; + } + + do + { + data->data[i] = NVSWITCH_ENG_OFF_RD32(device, NPORT, , link, register_start); + register_start += sizeof(NvU32); + i++; + + } + while (register_start <= register_end); + + *idx = i; + return NVL_SUCCESS; +} + +static void +_nvswitch_collect_error_info_ls10 +( + nvswitch_device *device, + NvU32 link, + NvU32 collect_flags, // NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_* + NVSWITCH_RAW_ERROR_LOG_TYPE *data +) +{ + NvU32 val; + NvU32 i = 0; + NvlStatus status = NVL_SUCCESS; + + // + // The requested data 'collect_flags' is captured, if valid. + // if the error log buffer fills, then the currently captured data block + // could be truncated and subsequent blocks will be skipped. + // The 'flags' field in the log structure describes which blocks are + // actually captured. + // Captured blocks are packed, in order. + // + + data->flags = 0; + + // ROUTE + if (collect_flags & NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME) + { + status = _nvswitch_collect_nport_error_info_ls10(device, link, data, &i, + NV_ROUTE_ERR_TIMESTAMP_LOG, + NV_ROUTE_ERR_TIMESTAMP_LOG); + if (status == NVL_SUCCESS) + { + data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME; + NVSWITCH_PRINT(device, INFO, + "ROUTE: TIMESTAMP: 0x%08x\n", data->data[i-1]); + } + } + + val = NVSWITCH_ENG_RD32(device, NPORT, , link, _ROUTE, _ERR_HEADER_LOG_VALID); + if (FLD_TEST_DRF_NUM(_ROUTE, _ERR_HEADER_LOG_VALID, _HEADERVALID0, 1, val)) + { + if (collect_flags & NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_MISC) + { + status = _nvswitch_collect_nport_error_info_ls10(device, link, data, &i, + NV_ROUTE_ERR_MISC_LOG_0, + NV_ROUTE_ERR_MISC_LOG_0); + if (status == NVL_SUCCESS) + { + data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_MISC; + NVSWITCH_PRINT(device, INFO, + "ROUTE: MISC: 0x%08x\n", data->data[i-1]); + } + } + + if (collect_flags & NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_HDR) + { + status = _nvswitch_collect_nport_error_info_ls10(device, link, data, &i, + NV_ROUTE_ERR_HEADER_LOG_4, + NV_ROUTE_ERR_HEADER_LOG_10); + if (status == NVL_SUCCESS) + { + data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_HDR; + NVSWITCH_PRINT(device, INFO, + "ROUTE: HEADER: 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x,\n", + data->data[i-8], data->data[i-7], data->data[i-6], data->data[i-5], + data->data[i-4], data->data[i-3], data->data[i-2], data->data[i-1]); + } + } + } + + // INGRESS + if (collect_flags & NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_TIME) + { + status = _nvswitch_collect_nport_error_info_ls10(device, link, data, &i, + NV_INGRESS_ERR_TIMESTAMP_LOG, + NV_INGRESS_ERR_TIMESTAMP_LOG); + if (status == NVL_SUCCESS) + { + data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_TIME; + NVSWITCH_PRINT(device, INFO, + "INGRESS: TIMESTAMP: 0x%08x\n", data->data[i-1]); + } + } + + val = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_HEADER_LOG_VALID); + if (FLD_TEST_DRF_NUM(_INGRESS, _ERR_HEADER_LOG_VALID, _HEADERVALID0, 1, val)) + { + if (collect_flags & NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_MISC) + { + status = _nvswitch_collect_nport_error_info_ls10(device, link, data, &i, + NV_INGRESS_ERR_MISC_LOG_0, + NV_INGRESS_ERR_MISC_LOG_0); + if (status == NVL_SUCCESS) + { + data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_MISC; + NVSWITCH_PRINT(device, INFO, + "INGRESS: MISC: 0x%08x\n", data->data[i-1]); + } + } + + if (collect_flags & NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_HDR) + { + status = _nvswitch_collect_nport_error_info_ls10(device, link, data, &i, + NV_INGRESS_ERR_HEADER_LOG_4, + NV_INGRESS_ERR_HEADER_LOG_9); + if (status == NVL_SUCCESS) + { + data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_HDR; + NVSWITCH_PRINT(device, INFO, + "INGRESS: HEADER: 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x,\n", + data->data[i-7], data->data[i-6], data->data[i-5], data->data[i-4], + data->data[i-3], data->data[i-2], data->data[i-1]); + } + } + } + + // EGRESS + if (collect_flags & NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_TIME) + { + status = _nvswitch_collect_nport_error_info_ls10(device, link, data, &i, + NV_EGRESS_ERR_TIMESTAMP_LOG, + NV_EGRESS_ERR_TIMESTAMP_LOG); + if (status == NVL_SUCCESS) + { + data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_TIME; + NVSWITCH_PRINT(device, INFO, + "EGRESS: TIMESTAMP: 0x%08x\n", data->data[i-1]); + } + } + + val = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _ERR_HEADER_LOG_VALID); + if (FLD_TEST_DRF_NUM(_EGRESS, _ERR_HEADER_LOG_VALID, _HEADERVALID0, 1, val)) + { + if (collect_flags & NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MISC) + { + status = _nvswitch_collect_nport_error_info_ls10(device, link, data, &i, + NV_EGRESS_ERR_MISC_LOG_0, + NV_EGRESS_ERR_MISC_LOG_0); + if (status == NVL_SUCCESS) + { + data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MISC; + NVSWITCH_PRINT(device, INFO, + "EGRESS: MISC: 0x%08x\n", data->data[i-1]); + } + } + + if (collect_flags & NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_HDR) + { + status = _nvswitch_collect_nport_error_info_ls10(device, link, data, &i, + NV_EGRESS_ERR_HEADER_LOG_4, + NV_EGRESS_ERR_HEADER_LOG_10); + if (status == NVL_SUCCESS) + { + data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_HDR; + NVSWITCH_PRINT(device, INFO, + "EGRESS: HEADER: 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", + data->data[i-7], data->data[i-6], data->data[i-5], data->data[i-4], + data->data[i-3], data->data[i-2], data->data[i-1]); + } + } + } + + if (collect_flags & NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MC_TIME) + { + status = _nvswitch_collect_nport_error_info_ls10(device, link, data, &i, + NV_EGRESS_MC_ERR_TIMESTAMP_LOG, + NV_EGRESS_MC_ERR_TIMESTAMP_LOG); + if (status == NVL_SUCCESS) + { + data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MC_TIME; + NVSWITCH_PRINT(device, INFO, + "EGRESS: TIME MC: 0x%08x\n", data->data[i-1]); + } + } + + val = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _MC_ERR_HEADER_LOG_VALID); + if (FLD_TEST_DRF_NUM(_EGRESS, _MC_ERR_HEADER_LOG_VALID, _HEADERVALID0, 1, val)) + { + if (collect_flags & NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MC_MISC) + { + status = _nvswitch_collect_nport_error_info_ls10(device, link, data, &i, + NV_EGRESS_MC_ERR_MISC_LOG_0, + NV_EGRESS_MC_ERR_MISC_LOG_0); + if (status == NVL_SUCCESS) + { + data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MC_MISC; + NVSWITCH_PRINT(device, INFO, + "EGRESS: MISC MC: 0x%08x\n", data->data[i-1]); + } + } + + if (collect_flags & NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MC_HDR) + { + status = _nvswitch_collect_nport_error_info_ls10(device, link, data, &i, + NV_EGRESS_MC_ERR_HEADER_LOG_4, + NV_EGRESS_MC_ERR_HEADER_LOG_10); + if (status == NVL_SUCCESS) + { + data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MC_HDR; + NVSWITCH_PRINT(device, INFO, + "EGRESS MC: HEADER: 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", + data->data[i-7], data->data[i-6], data->data[i-5], data->data[i-4], + data->data[i-3], data->data[i-2], data->data[i-1]); + } + } + } + + if (collect_flags & NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_MC_TIME) + { + status = _nvswitch_collect_nport_error_info_ls10(device, link, data, &i, + NV_MULTICASTTSTATE_ERR_TIMESTAMP_LOG, + NV_MULTICASTTSTATE_ERR_TIMESTAMP_LOG); + if (status == NVL_SUCCESS) + { + data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_MC_TIME; + NVSWITCH_PRINT(device, INFO, + "MC TSTATE MC: 0x%08x\n", + data->data[i-1]); + } + } + + if (collect_flags & NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_RED_TIME) + { + status = _nvswitch_collect_nport_error_info_ls10(device, link, data, &i, + NV_REDUCTIONTSTATE_ERR_TIMESTAMP_LOG, + NV_REDUCTIONTSTATE_ERR_TIMESTAMP_LOG); + if (status == NVL_SUCCESS) + { + data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_RED_TIME; + NVSWITCH_PRINT(device, INFO, + "MC TSTATE RED: 0x%08x\n", + data->data[i-1]); + } + } + + while (i < NVSWITCH_RAW_ERROR_LOG_DATA_SIZE) + { + data->data[i++] = 0; + } +} + +static NvlStatus +_nvswitch_service_route_fatal_ls10 +( + nvswitch_device *device, + NvU32 link +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + NvU32 pending, bit, contain, unhandled; + NVSWITCH_RAW_ERROR_LOG_TYPE data = {0, { 0 }}; + INFOROM_NVS_ECC_ERROR_EVENT err_event = {0}; + + report.raw_pending = NVSWITCH_ENG_RD32(device, NPORT, , link, _ROUTE, _ERR_STATUS_0); + report.raw_enable = NVSWITCH_ENG_RD32(device, NPORT, , link, _ROUTE, _ERR_FATAL_REPORT_EN_0); + report.mask = report.raw_enable & chip_device->intr_mask.route.fatal; + pending = report.raw_pending & report.mask; + + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + + report.raw_first = NVSWITCH_ENG_RD32(device, NPORT, , link, _ROUTE, _ERR_FIRST_0); + contain = NVSWITCH_ENG_RD32(device, NPORT, , link, _ROUTE, _ERR_CONTAIN_EN_0); + + bit = DRF_NUM(_ROUTE, _ERR_STATUS_0, _ROUTEBUFERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME, + &data); + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_ROUTE_ROUTEBUFERR, "route buffer over/underflow", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_ROUTE_ROUTEBUFERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_ROUTE, _ERR_STATUS_0, _GLT_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NvBool bAddressValid = NV_FALSE; + NvU32 address = 0; + NvU32 addressValid = NVSWITCH_ENG_RD32(device, NPORT, , link, _ROUTE, + _ERR_GLT_ECC_ERROR_ADDRESS_VALID); + + if (FLD_TEST_DRF(_ROUTE_ERR_GLT, _ECC_ERROR_ADDRESS_VALID, _VALID, _VALID, + addressValid)) + { + address = NVSWITCH_ENG_RD32(device, NPORT, , link, _ROUTE, + _ERR_GLT_ECC_ERROR_ADDRESS); + bAddressValid = NV_TRUE; + } + + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_HDR, + &data); + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_ROUTE_GLT_ECC_DBE_ERR, "route GLT DBE", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_ROUTE_GLT_ECC_DBE_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_ROUTE_GLT_ECC_DBE_ERR, link, bAddressValid, + address, NV_TRUE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + bit = DRF_NUM(_ROUTE, _ERR_STATUS_0, _PDCTRLPARERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_HDR, + &data); + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_ROUTE_PDCTRLPARERR, "route parity", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_ROUTE_PDCTRLPARERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_ROUTE, _ERR_STATUS_0, _NVS_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_HDR, + &data); + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_ROUTE_NVS_ECC_DBE_ERR, "route incoming DBE", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_ROUTE_NVS_ECC_DBE_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_ROUTE_NVS_ECC_DBE_ERR, link, NV_FALSE, 0, + NV_TRUE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + + // Clear associated LIMIT_ERR interrupt + if (report.raw_pending & DRF_NUM(_ROUTE, _ERR_STATUS_0, _NVS_ECC_LIMIT_ERR, 1)) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _ROUTE, _ERR_STATUS_0, + DRF_NUM(_ROUTE, _ERR_STATUS_0, _NVS_ECC_LIMIT_ERR, 1)); + } + } + + bit = DRF_NUM(_ROUTE, _ERR_STATUS_0, _CDTPARERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME, + &data); + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_ROUTE_CDTPARERR, "route credit parity", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_ROUTE_CDTPARERR, data); + nvswitch_clear_flags(&unhandled, bit); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_ROUTE_CDTPARERR, link, NV_FALSE, 0, + NV_TRUE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + bit = DRF_NUM(_ROUTE, _ERR_STATUS_0, _MCRID_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_HDR, + &data); + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_ROUTE_MCRID_ECC_DBE_ERR, "MC route ECC", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_ROUTE_MCRID_ECC_DBE_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_ROUTE_MCRID_ECC_DBE_ERR, link, NV_FALSE, 0, + NV_TRUE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + bit = DRF_NUM(_ROUTE, _ERR_STATUS_0, _EXTMCRID_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_HDR, + &data); + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_ROUTE_EXTMCRID_ECC_DBE_ERR, "Extd MC route ECC", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_ROUTE_EXTMCRID_ECC_DBE_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_ROUTE_EXTMCRID_ECC_DBE_ERR, link, NV_FALSE, 0, + NV_TRUE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + bit = DRF_NUM(_ROUTE, _ERR_STATUS_0, _RAM_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_HDR, + &data); + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_ROUTE_RAM_ECC_DBE_ERR, "route RAM ECC", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_ROUTE_RAM_ECC_DBE_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_ROUTE_RAM_ECC_DBE_ERR, link, NV_FALSE, 0, + NV_TRUE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + // Disable interrupts that have occurred after fatal error. + // This helps prevent an interrupt storm if HW keeps triggering unnecessary stream of interrupts. + if (device->link[link].fatal_error_occurred) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _ROUTE, _ERR_FATAL_REPORT_EN_0, + report.raw_enable ^ pending); + } + + if (report.raw_first & report.mask) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _ROUTE, _ERR_FIRST_0, + report.raw_first & report.mask); + } + NVSWITCH_ENG_WR32(device, NPORT, , link, _ROUTE, _ERR_STATUS_0, pending); + + if (unhandled != 0) + { + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_nvswitch_service_route_nonfatal_ls10 +( + nvswitch_device *device, + NvU32 link +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + NvU32 pending, bit, unhandled; + NVSWITCH_RAW_ERROR_LOG_TYPE data = {0, { 0 }}; + INFOROM_NVS_ECC_ERROR_EVENT err_event = {0}; + + report.raw_pending = NVSWITCH_ENG_RD32(device, NPORT, , link, _ROUTE, _ERR_STATUS_0); + report.raw_enable = NVSWITCH_ENG_RD32(device, NPORT, , link, _ROUTE, _ERR_NON_FATAL_REPORT_EN_0); + report.mask = report.raw_enable & chip_device->intr_mask.route.nonfatal; + pending = report.raw_pending & report.mask; + + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + report.raw_first = NVSWITCH_ENG_RD32(device, NPORT, , link, _ROUTE, _ERR_FIRST_0); + + bit = DRF_NUM(_ROUTE, _ERR_STATUS_0, _NOPORTDEFINEDERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_HDR, + &data); + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_ROUTE_NOPORTDEFINEDERR, "route undefined route"); + NVSWITCH_REPORT_DATA(_HW_NPORT_ROUTE_NOPORTDEFINEDERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_ROUTE, _ERR_STATUS_0, _INVALIDROUTEPOLICYERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_HDR, + &data); + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_ROUTE_INVALIDROUTEPOLICYERR, "route invalid policy"); + NVSWITCH_REPORT_DATA(_HW_NPORT_ROUTE_INVALIDROUTEPOLICYERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_ROUTE, _ERR_STATUS_0, _NVS_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + // Ignore LIMIT error if DBE is pending + if (!(nvswitch_test_flags(report.raw_pending, + DRF_NUM(_ROUTE, _ERR_STATUS_0, _NVS_ECC_DBE_ERR, 1)))) + { + report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _ROUTE, _ERR_NVS_ECC_ERROR_COUNTER); + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME, + &data); + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_ROUTE_NVS_ECC_LIMIT_ERR, "route incoming ECC limit"); + NVSWITCH_REPORT_DATA(_HW_NPORT_ROUTE_NVS_ECC_LIMIT_ERR, data); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_ROUTE_NVS_ECC_LIMIT_ERR, link, NV_FALSE, 0, + NV_FALSE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_ROUTE, _ERR_STATUS_0, _GLT_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + // Ignore LIMIT error if DBE is pending + if (!(nvswitch_test_flags(report.raw_pending, + DRF_NUM(_ROUTE, _ERR_STATUS_0, _GLT_ECC_DBE_ERR, 1)))) + { + report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _ROUTE, _ERR_GLT_ECC_ERROR_COUNTER); + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME, + &data); + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_ROUTE_NVS_ECC_LIMIT_ERR, "GLT ECC limit"); + NVSWITCH_REPORT_DATA(_HW_NPORT_ROUTE_GLT_ECC_LIMIT_ERR, data); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_ROUTE_GLT_ECC_LIMIT_ERR, link, NV_FALSE, 0, + NV_FALSE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_ROUTE, _ERR_STATUS_0, _MCRID_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + // Ignore LIMIT error if DBE is pending + if (!(nvswitch_test_flags(report.raw_pending, + DRF_NUM(_ROUTE, _ERR_STATUS_0, _MCRID_ECC_DBE_ERR, 1)))) + { + report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _ROUTE, _ERR_MCRID_ECC_ERROR_COUNTER); + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME, + &data); + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_ROUTE_NVS_ECC_LIMIT_ERR, "MCRID ECC limit"); + NVSWITCH_REPORT_DATA(_HW_NPORT_ROUTE_MCRID_ECC_LIMIT_ERR, data); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_ROUTE_MCRID_ECC_LIMIT_ERR, link, NV_FALSE, 0, + NV_FALSE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_ROUTE, _ERR_STATUS_0, _EXTMCRID_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + // Ignore LIMIT error if DBE is pending + if (!(nvswitch_test_flags(report.raw_pending, + DRF_NUM(_ROUTE, _ERR_STATUS_0, _EXTMCRID_ECC_DBE_ERR, 1)))) + { + report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _ROUTE, _ERR_EXTMCRID_ECC_ERROR_COUNTER); + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME, + &data); + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_ROUTE_NVS_ECC_LIMIT_ERR, "EXTMCRID ECC limit"); + NVSWITCH_REPORT_DATA(_HW_NPORT_ROUTE_EXTMCRID_ECC_LIMIT_ERR, data); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_ROUTE_EXTMCRID_ECC_LIMIT_ERR, link, NV_FALSE, 0, + NV_FALSE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_ROUTE, _ERR_STATUS_0, _RAM_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + // Ignore LIMIT error if DBE is pending + if (!(nvswitch_test_flags(report.raw_pending, + DRF_NUM(_ROUTE, _ERR_STATUS_0, _RAM_ECC_DBE_ERR, 1)))) + { + report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _ROUTE, _ERR_RAM_ECC_ERROR_COUNTER); + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME, + &data); + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_ROUTE_RAM_ECC_LIMIT_ERR, "RAM ECC limit"); + NVSWITCH_REPORT_DATA(_HW_NPORT_ROUTE_RAM_ECC_LIMIT_ERR, data); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_ROUTE_RAM_ECC_LIMIT_ERR, link, NV_FALSE, 0, + NV_FALSE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_ROUTE, _ERR_STATUS_0, _INVALID_MCRID_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME, + &data); + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_ROUTE_INVALID_MCRID_ERR, "invalid MC route"); + NVSWITCH_REPORT_DATA(_HW_NPORT_ROUTE_INVALID_MCRID_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + // Disable interrupts that have occurred after fatal error. + // This helps prevent an interrupt storm if HW keeps triggering unnecessary stream of interrupts. + if (device->link[link].fatal_error_occurred) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _ROUTE, _ERR_NON_FATAL_REPORT_EN_0, + report.raw_enable ^ pending); + } + + if (report.raw_first & report.mask) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _ROUTE, _ERR_FIRST_0, + report.raw_first & report.mask); + } + + NVSWITCH_ENG_WR32(device, NPORT, , link, _ROUTE, _ERR_STATUS_0, pending); + + // + // Note, when traffic is flowing, if we reset ERR_COUNT before ERR_STATUS + // register, we won't see an interrupt again until counter wraps around. + // In that case, we will miss writing back many ECC victim entries. Hence, + // always clear _ERR_COUNT only after _ERR_STATUS register is cleared! + // + NVSWITCH_ENG_WR32(device, NPORT, , link, _ROUTE, _ERR_NVS_ECC_ERROR_COUNTER, 0x0); + + if (unhandled != 0) + { + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +// +// Ingress +// + +static NvlStatus +_nvswitch_service_ingress_fatal_ls10 +( + nvswitch_device *device, + NvU32 link +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + NvU32 pending, bit, contain, unhandled; + NVSWITCH_RAW_ERROR_LOG_TYPE data = {0, { 0 }}; + INFOROM_NVS_ECC_ERROR_EVENT err_event = {0}; + + report.raw_pending = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_STATUS_0); + report.raw_enable = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_FATAL_REPORT_EN_0); + report.mask = report.raw_enable & chip_device->intr_mask.ingress[0].fatal; + pending = report.raw_pending & report.mask; + + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + report.raw_first = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_FIRST_0); + contain = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_CONTAIN_EN_0); + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_HDR, + &data); + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _CMDDECODEERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_INGRESS_CMDDECODEERR, "ingress invalid command", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_INGRESS_CMDDECODEERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _EXTAREMAPTAB_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_EXTAREMAPTAB_ECC_ERROR_COUNTER); + report.data[1] = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_EXTAREMAPTAB_ECC_ERROR_ADDRESS); + report.data[2] = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_EXTAREMAPTAB_ECC_ERROR_ADDRESS_VALID); + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_INGRESS_EXTAREMAPTAB_ECC_DBE_ERR, "ingress ExtA remap DBE", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_INGRESS_EXTAREMAPTAB_ECC_DBE_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_INGRESS_EXTAREMAPTAB_ECC_DBE_ERR, link, NV_FALSE, 0, + NV_TRUE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _NCISOC_HDR_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_NCISOC_HDR_ECC_ERROR_COUNTER); + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_INGRESS_NCISOC_HDR_ECC_DBE_ERR, "ingress header DBE", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_INGRESS_NCISOC_HDR_ECC_DBE_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_INGRESS_NCISOC_HDR_ECC_DBE_ERR, link, NV_FALSE, 0, + NV_TRUE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + + // Clear associated LIMIT_ERR interrupt + if (report.raw_pending & DRF_NUM(_INGRESS, _ERR_STATUS_0, _NCISOC_HDR_ECC_LIMIT_ERR, 1)) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _INGRESS, _ERR_STATUS_0, + DRF_NUM(_INGRESS, _ERR_STATUS_0, _NCISOC_HDR_ECC_LIMIT_ERR, 1)); + } + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _INVALIDVCSET, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_INGRESS_INVALIDVCSET, "ingress invalid VCSet", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_INGRESS_INVALIDVCSET, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _REMAPTAB_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NvBool bAddressValid = NV_FALSE; + NvU32 address = 0; + NvU32 addressValid = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, + _ERR_REMAPTAB_ECC_ERROR_ADDRESS); + + if (FLD_TEST_DRF(_INGRESS_ERR_REMAPTAB, _ECC_ERROR_ADDRESS_VALID, _VALID, _VALID, + addressValid)) + { + address = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, + _ERR_REMAPTAB_ECC_ERROR_ADDRESS); + bAddressValid = NV_TRUE; + } + + report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_REMAPTAB_ECC_ERROR_COUNTER); + report.data[1] = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_REMAPTAB_ECC_ERROR_ADDRESS); + report.data[2] = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_REMAPTAB_ECC_ERROR_ADDRESS_VALID); + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_INGRESS_REMAPTAB_ECC_DBE_ERR, "ingress Remap DBE", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_INGRESS_REMAPTAB_ECC_DBE_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_INGRESS_REMAPTAB_ECC_DBE_ERR, link, bAddressValid, + address, NV_TRUE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _RIDTAB_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NvBool bAddressValid = NV_FALSE; + NvU32 address = 0; + NvU32 addressValid = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, + _ERR_RIDTAB_ECC_ERROR_ADDRESS_VALID); + + if (FLD_TEST_DRF(_INGRESS_ERR_RIDTAB, _ECC_ERROR_ADDRESS_VALID, _VALID, _VALID, + addressValid)) + { + address = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, + _ERR_RIDTAB_ECC_ERROR_ADDRESS); + bAddressValid = NV_TRUE; + } + + report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_RIDTAB_ECC_ERROR_COUNTER); + report.data[1] = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_RIDTAB_ECC_ERROR_ADDRESS); + report.data[2] = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_RIDTAB_ECC_ERROR_ADDRESS_VALID); + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_INGRESS_RIDTAB_ECC_DBE_ERR, "ingress RID DBE", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_INGRESS_RIDTAB_ECC_DBE_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_INGRESS_RIDTAB_ECC_DBE_ERR, link, bAddressValid, + address, NV_TRUE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _RLANTAB_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NvBool bAddressValid = NV_FALSE; + NvU32 address = 0; + NvU32 addressValid = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, + _ERR_RLANTAB_ECC_ERROR_ADDRESS_VALID); + + if (FLD_TEST_DRF(_INGRESS_ERR_RLANTAB, _ECC_ERROR_ADDRESS_VALID, _VALID, _VALID, + addressValid)) + { + address = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, + _ERR_RLANTAB_ECC_ERROR_ADDRESS); + bAddressValid = NV_TRUE; + } + + report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_RLANTAB_ECC_ERROR_COUNTER); + report.data[1] = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_RLANTAB_ECC_ERROR_ADDRESS); + report.data[2] = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_RLANTAB_ECC_ERROR_ADDRESS_VALID); + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_INGRESS_RLANTAB_ECC_DBE_ERR, "ingress RLAN DBE", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_INGRESS_RLANTAB_ECC_DBE_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_INGRESS_RLANTAB_ECC_DBE_ERR, link, bAddressValid, + address, NV_TRUE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _NCISOC_PARITY_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_INGRESS_NCISOC_PARITY_ERR, "ingress control parity", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_INGRESS_NCISOC_PARITY_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_INGRESS_NCISOC_PARITY_ERR, link, NV_FALSE, 0, + NV_TRUE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _EXTBREMAPTAB_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_EXTBREMAPTAB_ECC_ERROR_COUNTER); + report.data[1] = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_EXTBREMAPTAB_ECC_ERROR_ADDRESS); + report.data[2] = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_EXTBREMAPTAB_ECC_ERROR_ADDRESS_VALID); + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_INGRESS_EXTBREMAPTAB_ECC_DBE_ERR, "ingress ExtB remap DBE", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_INGRESS_EXTBREMAPTAB_ECC_DBE_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_INGRESS_EXTBREMAPTAB_ECC_DBE_ERR, link, NV_FALSE, 0, + NV_TRUE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _MCREMAPTAB_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_MCREMAPTAB_ECC_ERROR_COUNTER); + report.data[1] = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_MCREMAPTAB_ECC_ERROR_ADDRESS); + report.data[2] = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_MCREMAPTAB_ECC_ERROR_ADDRESS_VALID); + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_INGRESS_MCREMAPTAB_ECC_DBE_ERR, "ingress MC remap DBE", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_INGRESS_MCREMAPTAB_ECC_DBE_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_INGRESS_MCREMAPTAB_ECC_DBE_ERR, link, NV_FALSE, 0, + NV_TRUE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + // Disable interrupts that have occurred after fatal error. + // This helps prevent an interrupt storm if HW keeps triggering unnecessary stream of interrupts. + if (device->link[link].fatal_error_occurred) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _INGRESS, _ERR_FATAL_REPORT_EN_0, + report.raw_enable ^ pending); + } + + if (report.raw_first & report.mask) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _INGRESS, _ERR_FIRST_0, + report.raw_first & report.mask); + } + + NVSWITCH_ENG_WR32(device, NPORT, , link, _INGRESS, _ERR_STATUS_0, pending); + + if (unhandled != 0) + { + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_nvswitch_service_ingress_nonfatal_ls10 +( + nvswitch_device *device, + NvU32 link +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + NvU32 pending, bit, unhandled; + NvU32 pending_0, pending_1; + NvU32 raw_pending_0; + NVSWITCH_RAW_ERROR_LOG_TYPE data = {0, { 0 }}; + INFOROM_NVS_ECC_ERROR_EVENT err_event = {0}; + NvlStatus status = NVL_SUCCESS; + + // + // _ERR_STATUS_0 + // + report.raw_pending = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_STATUS_0); + report.raw_enable = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_NON_FATAL_REPORT_EN_0); + report.mask = report.raw_enable & chip_device->intr_mask.ingress[0].nonfatal; + + raw_pending_0 = report.raw_pending; + pending = (report.raw_pending & report.mask); + pending_0 = pending; + + if (pending == 0) + { + goto _nvswitch_service_ingress_nonfatal_ls10_err_status_1; + } + + unhandled = pending; + report.raw_first = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_FIRST_0); + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_HDR, + &data); + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _REQCONTEXTMISMATCHERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_REQCONTEXTMISMATCHERR, "ingress request context mismatch"); + NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_REQCONTEXTMISMATCHERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _ACLFAIL, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_ACLFAIL, "ingress invalid ACL"); + NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_ACLFAIL, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _NCISOC_HDR_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + // Ignore LIMIT error if DBE is pending + if (!(nvswitch_test_flags(report.raw_pending, + DRF_NUM(_INGRESS, _ERR_STATUS_0, _NCISOC_HDR_ECC_DBE_ERR, 1)))) + { + report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_NCISOC_HDR_ECC_ERROR_COUNTER); + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_NCISOC_HDR_ECC_LIMIT_ERR, "ingress header ECC"); + NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_NCISOC_HDR_ECC_LIMIT_ERR, data); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_INGRESS_NCISOC_HDR_ECC_LIMIT_ERR, link, NV_FALSE, 0, + NV_FALSE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _ADDRBOUNDSERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_ADDRBOUNDSERR, "ingress address bounds"); + NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_ADDRBOUNDSERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _RIDTABCFGERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_RIDTABCFGERR, "ingress RID packet"); + NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_RIDTABCFGERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _RLANTABCFGERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_RLANTABCFGERR, "ingress RLAN packet"); + NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_RLANTABCFGERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _REMAPTAB_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + // Ignore LIMIT error if DBE is pending + if (!(nvswitch_test_flags(report.raw_pending, + DRF_NUM(_INGRESS, _ERR_STATUS_0, _REMAPTAB_ECC_DBE_ERR, 1)))) + { + report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_REMAPTAB_ECC_ERROR_COUNTER); + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_REMAPTAB_ECC_LIMIT_ERR, "ingress remap ECC"); + NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_REMAPTAB_ECC_LIMIT_ERR, data); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_INGRESS_REMAPTAB_ECC_LIMIT_ERR, link, NV_FALSE, 0, + NV_FALSE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _RIDTAB_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + // Ignore LIMIT error if DBE is pending + if (!(nvswitch_test_flags(report.raw_pending, + DRF_NUM(_INGRESS, _ERR_STATUS_0, _RIDTAB_ECC_DBE_ERR, 1)))) + { + report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_RIDTAB_ECC_ERROR_COUNTER); + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_RIDTAB_ECC_LIMIT_ERR, "ingress RID ECC"); + NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_RIDTAB_ECC_LIMIT_ERR, data); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_INGRESS_RIDTAB_ECC_LIMIT_ERR, link, NV_FALSE, 0, + NV_FALSE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _RLANTAB_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + // Ignore LIMIT error if DBE is pending + if (!(nvswitch_test_flags(report.raw_pending, + DRF_NUM(_INGRESS, _ERR_STATUS_0, _RLANTAB_ECC_DBE_ERR, 1)))) + { + report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_RLANTAB_ECC_ERROR_COUNTER); + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_RLANTAB_ECC_LIMIT_ERR, "ingress RLAN ECC"); + NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_RLANTAB_ECC_LIMIT_ERR, data); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_INGRESS_RLANTAB_ECC_LIMIT_ERR, link, NV_FALSE, 0, + NV_FALSE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + nvswitch_clear_flags(&unhandled, bit); + } + + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _ADDRTYPEERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_ADDRTYPEERR, "ingress illegal address"); + NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_ADDRTYPEERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _EXTAREMAPTAB_INDEX_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_EXTAREMAPTAB_INDEX_ERR, "ingress ExtA remap index"); + NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_EXTAREMAPTAB_INDEX_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _EXTBREMAPTAB_INDEX_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_EXTBREMAPTAB_INDEX_ERR, "ingress ExtB remap index"); + NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_EXTBREMAPTAB_INDEX_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _MCREMAPTAB_INDEX_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_MCREMAPTAB_INDEX_ERR, "ingress MC remap index"); + NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_MCREMAPTAB_INDEX_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _EXTAREMAPTAB_REQCONTEXTMISMATCHERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_EXTAREMAPTAB_REQCONTEXTMISMATCHERR, "ingress ExtA request context mismatch"); + NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_EXTAREMAPTAB_REQCONTEXTMISMATCHERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _EXTBREMAPTAB_REQCONTEXTMISMATCHERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_EXTBREMAPTAB_REQCONTEXTMISMATCHERR, "ingress ExtB request context mismatch"); + NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_EXTBREMAPTAB_REQCONTEXTMISMATCHERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _MCREMAPTAB_REQCONTEXTMISMATCHERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_MCREMAPTAB_REQCONTEXTMISMATCHERR, "ingress MC request context mismatch"); + NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_MCREMAPTAB_REQCONTEXTMISMATCHERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _EXTAREMAPTAB_ACLFAIL, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_EXTAREMAPTAB_ACLFAIL, "ingress invalid ExtA ACL"); + NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_EXTAREMAPTAB_ACLFAIL, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _EXTBREMAPTAB_ACLFAIL, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_EXTBREMAPTAB_ACLFAIL, "ingress invalid ExtB ACL"); + NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_EXTBREMAPTAB_ACLFAIL, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _MCREMAPTAB_ACLFAIL, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_MCREMAPTAB_ACLFAIL, "ingress invalid MC ACL"); + NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_MCREMAPTAB_ACLFAIL, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _EXTAREMAPTAB_ADDRBOUNDSERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_EXTAREMAPTAB_ADDRBOUNDSERR, "ingress ExtA address bounds"); + NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_EXTAREMAPTAB_ADDRBOUNDSERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _EXTBREMAPTAB_ADDRBOUNDSERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_EXTBREMAPTAB_ADDRBOUNDSERR, "ingress ExtB address bounds"); + NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_EXTBREMAPTAB_ADDRBOUNDSERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_0, _MCREMAPTAB_ADDRBOUNDSERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_MCREMAPTAB_ADDRBOUNDSERR, "ingress MC address bounds"); + NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_MCREMAPTAB_ADDRBOUNDSERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + // Disable interrupts that have occurred after fatal error. + // This helps prevent an interrupt storm if HW keeps triggering unnecessary stream of interrupts. + if (device->link[link].fatal_error_occurred) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _INGRESS, _ERR_NON_FATAL_REPORT_EN_0, + report.raw_enable ^ pending); + } + + if (report.raw_first & report.mask) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _INGRESS, _ERR_FIRST_0, + report.raw_first & report.mask); + } + + if (unhandled != 0) + { + status = -NVL_MORE_PROCESSING_REQUIRED; + } + +_nvswitch_service_ingress_nonfatal_ls10_err_status_1: + // + // _ERR_STATUS_1 + // + report.raw_pending = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_STATUS_1); + report.raw_enable = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_NON_FATAL_REPORT_EN_1); + report.mask = report.raw_enable & chip_device->intr_mask.ingress[1].nonfatal; + + pending = (report.raw_pending & report.mask); + pending_1 = pending; + + if ((pending_0 == 0) && (pending_1 == 0)) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + report.raw_first = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_FIRST_1); + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_1, _EXTAREMAPTAB_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + // Ignore LIMIT error if DBE is pending + if (!(nvswitch_test_flags(raw_pending_0, + DRF_NUM(_INGRESS, _ERR_STATUS_0, _EXTAREMAPTAB_ECC_DBE_ERR, 1)))) + { + report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_EXTAREMAPTAB_ECC_ERROR_COUNTER); + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_EXTAREMAPTAB_ECC_LIMIT_ERR, "ingress ExtA remap ECC"); + NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_EXTAREMAPTAB_ECC_LIMIT_ERR, data); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_INGRESS_EXTAREMAPTAB_ECC_LIMIT_ERR, link, NV_FALSE, 0, + NV_FALSE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_1, _EXTBREMAPTAB_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + // Ignore LIMIT error if DBE is pending + if (!(nvswitch_test_flags(raw_pending_0, + DRF_NUM(_INGRESS, _ERR_STATUS_0, _EXTBREMAPTAB_ECC_DBE_ERR, 1)))) + { + report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_EXTBREMAPTAB_ECC_ERROR_COUNTER); + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_EXTBREMAPTAB_ECC_LIMIT_ERR, "ingress ExtB remap ECC"); + NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_EXTBREMAPTAB_ECC_LIMIT_ERR, data); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_INGRESS_EXTBREMAPTAB_ECC_LIMIT_ERR, link, NV_FALSE, 0, + NV_FALSE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_1, _MCREMAPTAB_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + // Ignore LIMIT error if DBE is pending + if (!(nvswitch_test_flags(raw_pending_0, + DRF_NUM(_INGRESS, _ERR_STATUS_0, _MCREMAPTAB_ECC_DBE_ERR, 1)))) + { + report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _INGRESS, _ERR_MCREMAPTAB_ECC_ERROR_COUNTER); + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_MCREMAPTAB_ECC_LIMIT_ERR, "ingress MC remap ECC"); + NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_MCREMAPTAB_ECC_LIMIT_ERR, data); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_INGRESS_MCREMAPTAB_ECC_LIMIT_ERR, link, NV_FALSE, 0, + NV_FALSE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_1, _MCCMDTOUCADDRERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_MCCMDTOUCADDRERR, "ingress MC command to uc"); + NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_MCCMDTOUCADDRERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_1, _READMCREFLECTMEMERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_READMCREFLECTMEMERR, "ingress read reflective"); + NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_READMCREFLECTMEMERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_1, _EXTAREMAPTAB_ADDRTYPEERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_EXTAREMAPTAB_ADDRTYPEERR, "ingress ExtA address type"); + NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_EXTAREMAPTAB_ADDRTYPEERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_1, _EXTBREMAPTAB_ADDRTYPEERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_EXTBREMAPTAB_ADDRTYPEERR, "ingress ExtB address type"); + NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_EXTBREMAPTAB_ADDRTYPEERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_INGRESS, _ERR_STATUS_1, _MCREMAPTAB_ADDRTYPEERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_INGRESS_MCREMAPTAB_ADDRTYPEERR, "ingress MC address type"); + NVSWITCH_REPORT_DATA(_HW_NPORT_INGRESS_MCREMAPTAB_ADDRTYPEERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + // Disable interrupts that have occurred after fatal error. + // This helps prevent an interrupt storm if HW keeps triggering unnecessary stream of interrupts. + if (device->link[link].fatal_error_occurred) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _INGRESS, _ERR_NON_FATAL_REPORT_EN_1, + report.raw_enable ^ pending); + } + + if (report.raw_first & report.mask) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _INGRESS, _ERR_FIRST_1, + report.raw_first & report.mask); + } + + NVSWITCH_ENG_WR32(device, NPORT, , link, _INGRESS, _ERR_STATUS_0, pending_0); + NVSWITCH_ENG_WR32(device, NPORT, , link, _INGRESS, _ERR_STATUS_1, pending_1); + + if (unhandled != 0) + { + status = -NVL_MORE_PROCESSING_REQUIRED; + } + + return status; +} + +// +// Tstate +// + +static NvlStatus +_nvswitch_service_tstate_nonfatal_ls10 +( + nvswitch_device *device, + NvU32 link +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + NvU32 pending, bit, unhandled; + NVSWITCH_RAW_ERROR_LOG_TYPE data = {0, { 0 }}; + INFOROM_NVS_ECC_ERROR_EVENT err_event = {0}; + + report.raw_pending = NVSWITCH_ENG_RD32(device, NPORT, , link, _TSTATE, _ERR_STATUS_0); + report.raw_enable = NVSWITCH_ENG_RD32(device, NPORT, , link, _TSTATE, _ERR_NON_FATAL_REPORT_EN_0); + report.mask = report.raw_enable & chip_device->intr_mask.tstate.nonfatal; + report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _TSTATE, _ERR_MISC_LOG_0); + pending = report.raw_pending & report.mask; + + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + report.raw_first = NVSWITCH_ENG_RD32(device, NPORT, , link, _TSTATE, _ERR_FIRST_0); + + bit = DRF_NUM(_TSTATE, _ERR_STATUS_0, _TAGPOOL_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + // Ignore LIMIT error if DBE is pending + if(!(nvswitch_test_flags(report.raw_pending, + DRF_NUM(_TSTATE, _ERR_STATUS_0, _TAGPOOL_ECC_DBE_ERR, 1)))) + { + NvBool bAddressValid = NV_FALSE; + NvU32 address = 0; + NvU32 addressValid = NVSWITCH_ENG_RD32(device, NPORT, , link, _TSTATE, + _ERR_TAGPOOL_ECC_ERROR_ADDRESS_VALID); + + if (FLD_TEST_DRF(_TSTATE_ERR_TAGPOOL, _ECC_ERROR_ADDRESS_VALID, _VALID, _VALID, + addressValid)) + { + address = NVSWITCH_ENG_RD32(device, NPORT, , link, _TSTATE, + _ERR_TAGPOOL_ECC_ERROR_ADDRESS); + bAddressValid = NV_TRUE; + } + + report.data[1] = NVSWITCH_ENG_RD32(device, NPORT, , link, _TSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER); + NVSWITCH_ENG_WR32(device, NPORT, , link, _TSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER, + DRF_DEF(_TSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER, _ERROR_COUNT, _INIT)); + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_TSTATE_TAGPOOL_ECC_LIMIT_ERR, "TS tag store single-bit threshold"); + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_HDR, + &data); + NVSWITCH_REPORT_DATA(_HW_NPORT_TSTATE_TAGPOOL_ECC_LIMIT_ERR, data); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_TSTATE_TAGPOOL_ECC_LIMIT_ERR, link, + bAddressValid, address, NV_FALSE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_TSTATE, _ERR_STATUS_0, _CRUMBSTORE_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + // Ignore LIMIT error if DBE is pending + if(!(nvswitch_test_flags(report.raw_pending, + DRF_NUM(_TSTATE, _ERR_STATUS_0, _CRUMBSTORE_ECC_DBE_ERR, 1)))) + { + NvBool bAddressValid = NV_FALSE; + NvU32 address = 0; + NvU32 addressValid = NVSWITCH_ENG_RD32(device, NPORT, , link, _TSTATE, + _ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID); + + if (FLD_TEST_DRF(_TSTATE_ERR_CRUMBSTORE, _ECC_ERROR_ADDRESS_VALID, _VALID, _VALID, + addressValid)) + { + address = NVSWITCH_ENG_RD32(device, NPORT, , link, _TSTATE, + _ERR_CRUMBSTORE_ECC_ERROR_ADDRESS); + bAddressValid = NV_TRUE; + } + + report.data[1] = NVSWITCH_ENG_RD32(device, NPORT, , link, _TSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER); + NVSWITCH_ENG_WR32(device, NPORT, , link, _TSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER, + DRF_DEF(_TSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER, _ERROR_COUNT, _INIT)); + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_TSTATE_CRUMBSTORE_ECC_LIMIT_ERR, "TS crumbstore single-bit threshold"); + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_HDR, + &data); + NVSWITCH_REPORT_DATA(_HW_NPORT_TSTATE_CRUMBSTORE_ECC_LIMIT_ERR, data); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_TSTATE_CRUMBSTORE_ECC_LIMIT_ERR, link, + bAddressValid, address, NV_FALSE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + nvswitch_clear_flags(&unhandled, bit); + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + // Disable interrupts that have occurred after fatal error. + // This helps prevent an interrupt storm if HW keeps triggering unnecessary stream of interrupts. + if (device->link[link].fatal_error_occurred) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _TSTATE, _ERR_NON_FATAL_REPORT_EN_0, + report.raw_enable ^ pending); + } + + if (report.raw_first & report.mask) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _TSTATE, _ERR_FIRST_0, + report.raw_first & report.mask); + } + + NVSWITCH_ENG_WR32(device, NPORT, , link, _TSTATE, _ERR_STATUS_0, pending); + + if (unhandled != 0) + { + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_nvswitch_service_tstate_fatal_ls10 +( + nvswitch_device *device, + NvU32 link +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + NvU32 pending, bit, contain, unhandled; + NVSWITCH_RAW_ERROR_LOG_TYPE data = {0, { 0 }}; + INFOROM_NVS_ECC_ERROR_EVENT err_event = {0}; + + report.raw_pending = NVSWITCH_ENG_RD32(device, NPORT, , link, _TSTATE, _ERR_STATUS_0); + report.raw_enable = NVSWITCH_ENG_RD32(device, NPORT, , link, _TSTATE, _ERR_FATAL_REPORT_EN_0); + report.mask = report.raw_enable & chip_device->intr_mask.tstate.fatal; + report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _TSTATE, _ERR_MISC_LOG_0); + pending = report.raw_pending & report.mask; + + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + report.raw_first = NVSWITCH_ENG_RD32(device, NPORT, , link, _TSTATE, _ERR_FIRST_0); + contain = NVSWITCH_ENG_RD32(device, NPORT, , link, _TSTATE, _ERR_CONTAIN_EN_0); + + bit = DRF_NUM(_TSTATE, _ERR_STATUS_0, _TAGPOOLBUFERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_TSTATE_TAGPOOLBUFERR, "TS pointer crossover", NV_FALSE); + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_HDR, + &data); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_TSTATE_TAGPOOLBUFERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_TSTATE, _ERR_STATUS_0, _TAGPOOL_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NvBool bAddressValid = NV_FALSE; + NvU32 address = 0; + NvU32 addressValid = NVSWITCH_ENG_RD32(device, NPORT, , link, _TSTATE, + _ERR_TAGPOOL_ECC_ERROR_ADDRESS_VALID); + + if (FLD_TEST_DRF(_TSTATE_ERR_TAGPOOL, _ECC_ERROR_ADDRESS_VALID, _VALID, _VALID, + addressValid)) + { + address = NVSWITCH_ENG_RD32(device, NPORT, , link, _TSTATE, + _ERR_TAGPOOL_ECC_ERROR_ADDRESS); + bAddressValid = NV_TRUE; + } + + report.data[1] = NVSWITCH_ENG_RD32(device, NPORT, , link, _TSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER); + NVSWITCH_ENG_WR32(device, NPORT, , link, _TSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER, + DRF_DEF(_TSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER, _ERROR_COUNT, _INIT)); + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_TSTATE_TAGPOOL_ECC_DBE_ERR, "TS tag store fatal ECC", NV_FALSE); + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_HDR, + &data); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_TSTATE_TAGPOOL_ECC_DBE_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_TSTATE_TAGPOOL_ECC_DBE_ERR, link, bAddressValid, + address, NV_TRUE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + + // Clear associated LIMIT_ERR interrupt + if (report.raw_pending & DRF_NUM(_TSTATE, _ERR_STATUS_0, _TAGPOOL_ECC_LIMIT_ERR, 1)) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _TSTATE, _ERR_STATUS_0, + DRF_NUM(_TSTATE, _ERR_STATUS_0, _TAGPOOL_ECC_LIMIT_ERR, 1)); + } + } + + bit = DRF_NUM(_TSTATE, _ERR_STATUS_0, _CRUMBSTOREBUFERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_TSTATE_CRUMBSTOREBUFERR, "TS crumbstore", NV_FALSE); + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_HDR, + &data); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_TSTATE_CRUMBSTOREBUFERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_TSTATE, _ERR_STATUS_0, _CRUMBSTORE_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NvBool bAddressValid = NV_FALSE; + NvU32 address = 0; + NvU32 addressValid = NVSWITCH_ENG_RD32(device, NPORT, , link, _TSTATE, + _ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID); + + if (FLD_TEST_DRF(_TSTATE_ERR_CRUMBSTORE, _ECC_ERROR_ADDRESS_VALID, _VALID, _VALID, + addressValid)) + { + address = NVSWITCH_ENG_RD32(device, NPORT, , link, _TSTATE, + _ERR_CRUMBSTORE_ECC_ERROR_ADDRESS); + bAddressValid = NV_TRUE; + } + + report.data[1] = NVSWITCH_ENG_RD32(device, NPORT, , link, _TSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER); + NVSWITCH_ENG_WR32(device, NPORT, , link, _TSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER, + DRF_DEF(_TSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER, _ERROR_COUNT, _INIT)); + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_TSTATE_CRUMBSTORE_ECC_DBE_ERR, "TS crumbstore fatal ECC", NV_FALSE); + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_HDR, + &data); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_TSTATE_CRUMBSTORE_ECC_DBE_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_TSTATE_CRUMBSTORE_ECC_DBE_ERR, link, bAddressValid, + address, NV_TRUE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + + // Clear associated LIMIT_ERR interrupt + if (report.raw_pending & DRF_NUM(_TSTATE, _ERR_STATUS_0, _CRUMBSTORE_ECC_LIMIT_ERR, 1)) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _TSTATE, _ERR_STATUS_0, + DRF_NUM(_TSTATE, _ERR_STATUS_0, _CRUMBSTORE_ECC_LIMIT_ERR, 1)); + } + } + + bit = DRF_NUM(_TSTATE, _ERR_STATUS_0, _ATO_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + if (FLD_TEST_DRF_NUM(_TSTATE, _ERR_FIRST_0, _ATO_ERR, 1, report.raw_first)) + { + report.data[1] = NVSWITCH_ENG_RD32(device, NPORT, , link, _TSTATE, _ERR_DEBUG); + } + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_TSTATE_ATO_ERR, "TS ATO timeout", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_TSTATE, _ERR_STATUS_0, _CAMRSP_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_TSTATE_CAMRSP_ERR, "Rsp Tag value out of range", NV_FALSE); + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_HDR, + &data); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_TSTATE_CAMRSP_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + // Disable interrupts that have occurred after fatal error. + // This helps prevent an interrupt storm if HW keeps triggering unnecessary stream of interrupts. + if (device->link[link].fatal_error_occurred) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _TSTATE, _ERR_FATAL_REPORT_EN_0, + report.raw_enable ^ pending); + } + + if (report.raw_first & report.mask) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _TSTATE, _ERR_FIRST_0, + report.raw_first & report.mask); + } + + NVSWITCH_ENG_WR32(device, NPORT, , link, _TSTATE, _ERR_STATUS_0, pending); + + if (unhandled != 0) + { + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +// +// Egress +// + +static NvlStatus +_nvswitch_service_egress_nonfatal_ls10 +( + nvswitch_device *device, + NvU32 link +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + NvU32 pending, bit, unhandled; + NvU32 pending_0, pending_1; + NVSWITCH_RAW_ERROR_LOG_TYPE data = {0, { 0 }}; + INFOROM_NVS_ECC_ERROR_EVENT err_event = {0}; + NvlStatus status = NVL_SUCCESS; + + report.raw_pending = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _ERR_STATUS_0); + report.raw_enable = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _ERR_NON_FATAL_REPORT_EN_0); + report.mask = report.raw_enable & chip_device->intr_mask.egress[0].nonfatal; + pending = report.raw_pending & report.mask; + pending_0 = pending; + + if (pending == 0) + { + goto _nvswitch_service_egress_nonfatal_ls10_err_status_1; + } + + unhandled = pending; + report.raw_first = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _ERR_FIRST_0); + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_HDR, + &data); + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_0, _NXBAR_HDR_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + // Ignore LIMIT error if DBE is pending + if (!(nvswitch_test_flags(report.raw_pending, + DRF_NUM(_EGRESS, _ERR_STATUS_0, _NXBAR_HDR_ECC_DBE_ERR, 1)))) + { + report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _ERR_NXBAR_ECC_ERROR_COUNTER); + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_EGRESS_NXBAR_HDR_ECC_LIMIT_ERR, "egress input ECC error limit"); + NVSWITCH_REPORT_DATA(_HW_NPORT_EGRESS_NXBAR_HDR_ECC_LIMIT_ERR, data); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_HDR_ECC_LIMIT_ERR, link, NV_FALSE, 0, + NV_FALSE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_0, _RAM_OUT_HDR_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + // Ignore LIMIT error if DBE is pending + if(!(nvswitch_test_flags(report.raw_pending, + DRF_NUM(_EGRESS, _ERR_STATUS_0, _RAM_OUT_HDR_ECC_DBE_ERR, 1)))) + { + NvBool bAddressValid = NV_FALSE; + NvU32 address = 0; + NvU32 addressValid = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, + _ERR_RAM_OUT_ECC_ERROR_ADDRESS_VALID); + + if (FLD_TEST_DRF(_EGRESS_ERR_RAM_OUT, _ECC_ERROR_ADDRESS_VALID, _VALID, _VALID, + addressValid)) + { + address = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, + _ERR_RAM_OUT_ECC_ERROR_ADDRESS); + bAddressValid = NV_TRUE; + } + + report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _ERR_RAM_OUT_ECC_ERROR_COUNTER); + report.data[1] = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _ERR_RAM_OUT_ECC_ERROR_ADDRESS); + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_EGRESS_RAM_OUT_HDR_ECC_LIMIT_ERR, "egress output ECC error limit"); + NVSWITCH_REPORT_DATA(_HW_NPORT_EGRESS_RAM_OUT_HDR_ECC_LIMIT_ERR, data); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_EGRESS_RAM_OUT_HDR_ECC_LIMIT_ERR, link, bAddressValid, address, + NV_FALSE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_0, _PRIVRSPERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_EGRESS_PRIVRSPERR, "egress non-posted PRIV error"); + NVSWITCH_REPORT_DATA(_HW_NPORT_EGRESS_PRIVRSPERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + // Disable interrupts that have occurred after fatal error. + // This helps prevent an interrupt storm if HW keeps triggering unnecessary stream of interrupts. + if (device->link[link].fatal_error_occurred) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_NON_FATAL_REPORT_EN_0, + report.raw_enable ^ pending); + } + + if (report.raw_first & report.mask) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_FIRST_0, + report.raw_first & report.mask); + } + + NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_STATUS_0, pending); + + // HACK: Clear all pending interrupts! + NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_STATUS_0, 0xFFFFFFFF); + + if (unhandled != 0) + { + status = -NVL_MORE_PROCESSING_REQUIRED; + } + +_nvswitch_service_egress_nonfatal_ls10_err_status_1: + report.raw_pending = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _ERR_STATUS_1); + report.raw_enable = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _ERR_NON_FATAL_REPORT_EN_1); + report.mask = report.raw_enable & chip_device->intr_mask.egress[1].nonfatal; + pending = report.raw_pending & report.mask; + pending_1 = pending; + + if ((pending_0 == 0) && (pending_1 == 0)) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + report.raw_first = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _ERR_FIRST_1); + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_1, _NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + // Ignore LIMIT error if DBE is pending + if (!(nvswitch_test_flags(report.raw_pending, + DRF_NUM(_EGRESS, _ERR_STATUS_1, _NXBAR_REDUCTION_HDR_ECC_DBE_ERR, 1)))) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_EGRESS_NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR, "egress reduction header ECC error limit"); + NVSWITCH_REPORT_DATA(_HW_NPORT_EGRESS_NXBAR_HDR_ECC_LIMIT_ERR, data); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR, link, NV_FALSE, 0, + NV_FALSE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_1, _MCRSPCTRLSTORE_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + // Ignore LIMIT error if DBE is pending + if (!(nvswitch_test_flags(report.raw_pending, + DRF_NUM(_EGRESS, _ERR_STATUS_1, _MCRSPCTRLSTORE_ECC_DBE_ERR, 1)))) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_EGRESS_MCRSPCTRLSTORE_ECC_LIMIT_ERR, "egress MC response ECC error limit"); + NVSWITCH_REPORT_DATA(_HW_NPORT_EGRESS_MCRSPCTRLSTORE_ECC_LIMIT_ERR, data); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_EGRESS_MCRSPCTRLSTORE_ECC_LIMIT_ERR, link, NV_FALSE, 0, + NV_FALSE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_1, _RBCTRLSTORE_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + // Ignore LIMIT error if DBE is pending + if (!(nvswitch_test_flags(report.raw_pending, + DRF_NUM(_EGRESS, _ERR_STATUS_1, _RBCTRLSTORE_ECC_DBE_ERR, 1)))) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_EGRESS_RBCTRLSTORE_ECC_LIMIT_ERR, "egress RB ECC error limit"); + NVSWITCH_REPORT_DATA(_HW_NPORT_EGRESS_RBCTRLSTORE_ECC_LIMIT_ERR, data); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_EGRESS_RBCTRLSTORE_ECC_LIMIT_ERR, link, NV_FALSE, 0, + NV_FALSE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_1, _MCREDSGT_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + // Ignore LIMIT error if DBE is pending + if (!(nvswitch_test_flags(report.raw_pending, + DRF_NUM(_EGRESS, _ERR_STATUS_1, _MCREDSGT_ECC_DBE_ERR, 1)))) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_EGRESS_MCREDSGT_ECC_LIMIT_ERR, "egress RSG ECC error limit"); + NVSWITCH_REPORT_DATA(_HW_NPORT_EGRESS_MCREDSGT_ECC_LIMIT_ERR, data); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_EGRESS_MCREDSGT_ECC_LIMIT_ERR, link, NV_FALSE, 0, + NV_FALSE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_1, _MCREDBUF_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + // Ignore LIMIT error if DBE is pending + if (!(nvswitch_test_flags(report.raw_pending, + DRF_NUM(_EGRESS, _ERR_STATUS_1, _MCREDBUF_ECC_DBE_ERR, 1)))) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_EGRESS_MCREDBUF_ECC_LIMIT_ERR, "egress MCRB ECC error limit"); + NVSWITCH_REPORT_DATA(_HW_NPORT_EGRESS_MCREDBUF_ECC_LIMIT_ERR, data); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_EGRESS_MCREDBUF_ECC_LIMIT_ERR, link, NV_FALSE, 0, + NV_FALSE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_1, _MCRSP_RAM_HDR_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + // Ignore LIMIT error if DBE is pending + if (!(nvswitch_test_flags(report.raw_pending, + DRF_NUM(_EGRESS, _ERR_STATUS_1, _MCRSP_RAM_HDR_ECC_DBE_ERR, 1)))) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_EGRESS_MCRSP_RAM_HDR_ECC_LIMIT_ERR, "egress MC header ECC error limit"); + NVSWITCH_REPORT_DATA(_HW_NPORT_EGRESS_MCRSP_RAM_HDR_ECC_LIMIT_ERR, data); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_EGRESS_MCRSP_RAM_HDR_ECC_LIMIT_ERR, link, NV_FALSE, 0, + NV_FALSE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_1, _NXBAR_REDUCTION_HDR_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_EGRESS_NXBAR_REDUCTION_HDR_ECC_DBE_ERR, "egress reduction header ECC DBE error"); + NVSWITCH_REPORT_DATA(_HW_NPORT_EGRESS_NXBAR_REDUCTION_HDR_ECC_DBE_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_REDUCTION_HDR_ECC_DBE_ERR, link, NV_FALSE, 0, + NV_TRUE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + + // Clear associated LIMIT_ERR interrupt + if (report.raw_pending & DRF_NUM(_EGRESS, _ERR_STATUS_1, _NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR, 1)) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_STATUS_1, + DRF_NUM(_EGRESS, _ERR_STATUS_1, _NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR, 1)); + } + } + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_1, _NXBAR_REDUCTION_HDR_PARITY_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_EGRESS_NXBAR_REDUCTION_HDR_PARITY_ERR, "egress reduction header parity error"); + NVSWITCH_REPORT_DATA(_HW_NPORT_EGRESS_NXBAR_REDUCTION_HDR_PARITY_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_1, _NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_EGRESS_NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR, "egress reduction flit mismatch error"); + NVSWITCH_REPORT_DATA(_HW_NPORT_EGRESS_NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_1, _MCREDBUF_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_EGRESS_MCREDBUF_ECC_DBE_ERR, "egress reduction buffer ECC DBE error"); + NVSWITCH_REPORT_DATA(_HW_NPORT_EGRESS_MCREDBUF_ECC_DBE_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_EGRESS_MCREDBUF_ECC_DBE_ERR, link, NV_FALSE, 0, + NV_TRUE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + + // Clear associated LIMIT_ERR interrupt + if (report.raw_pending & DRF_NUM(_EGRESS, _ERR_STATUS_1, _MCREDBUF_ECC_LIMIT_ERR, 1)) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_STATUS_1, + DRF_NUM(_EGRESS, _ERR_STATUS_1, _MCREDBUF_ECC_LIMIT_ERR, 1)); + } + } + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_1, _MCRSP_CNT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MC_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MC_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MC_HDR, + &data); + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_EGRESS_MCRSP_CNT_ERR, "egress MC response count error"); + NVSWITCH_REPORT_DATA(_HW_NPORT_EGRESS_MCRSP_CNT_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_1, _RBRSP_CNT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MC_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MC_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MC_HDR, + &data); + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_EGRESS_RBRSP_CNT_ERR, "egress reduction response count error"); + NVSWITCH_REPORT_DATA(_HW_NPORT_EGRESS_RBRSP_CNT_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + // Disable interrupts that have occurred after fatal error. + // This helps prevent an interrupt storm if HW keeps triggering unnecessary stream of interrupts. + if (device->link[link].fatal_error_occurred) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_NON_FATAL_REPORT_EN_1, + report.raw_enable ^ pending); + } + + if (report.raw_first & report.mask) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_FIRST_1, + report.raw_first & report.mask); + } + + NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_STATUS_1, pending); + + // Clear all pending interrupts! + NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_STATUS_1, 0xFFFFFFFF); + + if (unhandled != 0) + { + status = -NVL_MORE_PROCESSING_REQUIRED; + } + + return status; +} + +static NvlStatus +_nvswitch_service_egress_fatal_ls10 +( + nvswitch_device *device, + NvU32 link +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + NvU32 pending, bit, contain, unhandled; + NvU32 pending_0, pending_1; + NVSWITCH_RAW_ERROR_LOG_TYPE data = {0, { 0 }}; + NVSWITCH_RAW_ERROR_LOG_TYPE credit_data = {0, { 0 }}; + NVSWITCH_RAW_ERROR_LOG_TYPE buffer_data = {0, { 0 }}; + INFOROM_NVS_ECC_ERROR_EVENT err_event = {0}; + NvlStatus status = NVL_SUCCESS; + + report.raw_pending = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _ERR_STATUS_0); + report.raw_enable = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _ERR_FATAL_REPORT_EN_0); + report.mask = report.raw_enable & chip_device->intr_mask.egress[0].fatal; + pending = report.raw_pending & report.mask; + pending_0 = pending; + + if (pending == 0) + { + goto _nvswitch_service_egress_fatal_ls10_err_status_1; + } + + unhandled = pending; + report.raw_first = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _ERR_FIRST_0); + contain = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _ERR_CONTAIN_EN_0); + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_HDR, + &data); + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_0, _EGRESSBUFERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_EGRESS_EGRESSBUFERR, "egress crossbar overflow", NV_TRUE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_EGRESS_EGRESSBUFERR, data); + + buffer_data.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _BUFFER_POINTERS0); + buffer_data.data[1] = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _BUFFER_POINTERS1); + buffer_data.data[2] = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _BUFFER_POINTERS2); + buffer_data.data[3] = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _BUFFER_POINTERS3); + buffer_data.data[4] = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _BUFFER_POINTERS4); + buffer_data.data[5] = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _BUFFER_POINTERS5); + buffer_data.data[6] = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _BUFFER_POINTERS6); + buffer_data.data[7] = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _BUFFER_POINTERS7); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_EGRESS_EGRESSBUFERR, buffer_data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_0, _PKTROUTEERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_EGRESS_PKTROUTEERR, "egress packet route", NV_TRUE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_EGRESS_PKTROUTEERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_0, _SEQIDERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_EGRESS_SEQIDERR, "egress sequence ID error", NV_TRUE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_EGRESS_SEQIDERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_0, _NXBAR_HDR_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_EGRESS_NXBAR_HDR_ECC_DBE_ERR, "egress input ECC DBE error", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_EGRESS_NXBAR_HDR_ECC_DBE_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_HDR_ECC_DBE_ERR, link, NV_FALSE, 0, + NV_TRUE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + + // Clear associated LIMIT_ERR interrupt + if (report.raw_pending & DRF_NUM(_EGRESS, _ERR_STATUS_0, _NXBAR_HDR_ECC_LIMIT_ERR, 1)) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_STATUS_0, + DRF_NUM(_EGRESS, _ERR_STATUS_0, _NXBAR_HDR_ECC_LIMIT_ERR, 1)); + } + } + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_0, _RAM_OUT_HDR_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NvBool bAddressValid = NV_FALSE; + NvU32 address = 0; + NvU32 addressValid = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, + _ERR_RAM_OUT_ECC_ERROR_ADDRESS_VALID); + + if (FLD_TEST_DRF(_EGRESS_ERR_RAM_OUT, _ECC_ERROR_ADDRESS_VALID, _VALID, _VALID, + addressValid)) + { + address = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, + _ERR_RAM_OUT_ECC_ERROR_ADDRESS); + bAddressValid = NV_TRUE; + } + + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_EGRESS_RAM_OUT_HDR_ECC_DBE_ERR, "egress output ECC DBE error", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_EGRESS_RAM_OUT_HDR_ECC_DBE_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_EGRESS_RAM_OUT_HDR_ECC_DBE_ERR, link, bAddressValid, + address, NV_TRUE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + + // Clear associated LIMIT_ERR interrupt + if (report.raw_pending & DRF_NUM(_EGRESS, _ERR_STATUS_0, _RAM_OUT_HDR_ECC_LIMIT_ERR, 1)) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_STATUS_0, + DRF_NUM(_EGRESS, _ERR_STATUS_0, _RAM_OUT_HDR_ECC_LIMIT_ERR, 1)); + } + } + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_0, _NCISOCCREDITOVFL, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_EGRESS_NCISOCCREDITOVFL, "egress credit overflow", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_EGRESS_NCISOCCREDITOVFL, data); + + credit_data.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _NCISOC_CREDIT0); + credit_data.data[1] = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _NCISOC_CREDIT1); + credit_data.data[2] = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _NCISOC_CREDIT2); + credit_data.data[3] = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _NCISOC_CREDIT3); + credit_data.data[4] = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _NCISOC_CREDIT4); + credit_data.data[5] = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _NCISOC_CREDIT5); + credit_data.data[6] = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _NCISOC_CREDIT6); + credit_data.data[7] = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _NCISOC_CREDIT7); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_EGRESS_NCISOCCREDITOVFL, credit_data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_0, _REQTGTIDMISMATCHERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_EGRESS_REQTGTIDMISMATCHERR, "egress destination request ID error", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_EGRESS_REQTGTIDMISMATCHERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_0, _RSPREQIDMISMATCHERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_EGRESS_RSPREQIDMISMATCHERR, "egress destination response ID error", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_EGRESS_RSPREQIDMISMATCHERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_0, _URRSPERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_EGRESS_DROPNPURRSPERR, "egress non-posted UR error", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_EGRESS_DROPNPURRSPERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_0, _HWRSPERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_EGRESS_HWRSPERR, "egress non-posted HW error", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_EGRESS_HWRSPERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_0, _NXBAR_HDR_PARITY_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_EGRESS_NXBAR_HDR_PARITY_ERR, "egress control parity error", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_EGRESS_NXBAR_HDR_PARITY_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_HDR_PARITY_ERR, link, NV_FALSE, 0, + NV_TRUE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_0, _NCISOC_CREDIT_PARITY_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_EGRESS_NCISOC_CREDIT_PARITY_ERR, "egress credit parity error", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_EGRESS_NCISOC_CREDIT_PARITY_ERR, data); + + credit_data.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _NCISOC_CREDIT0); + credit_data.data[1] = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _NCISOC_CREDIT1); + credit_data.data[2] = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _NCISOC_CREDIT2); + credit_data.data[3] = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _NCISOC_CREDIT3); + credit_data.data[4] = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _NCISOC_CREDIT4); + credit_data.data[5] = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _NCISOC_CREDIT5); + credit_data.data[6] = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _NCISOC_CREDIT6); + credit_data.data[7] = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _NCISOC_CREDIT7); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_EGRESS_NCISOC_CREDIT_PARITY_ERR, credit_data); + nvswitch_clear_flags(&unhandled, bit); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_EGRESS_NCISOC_CREDIT_PARITY_ERR, link, NV_FALSE, 0, + NV_TRUE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_0, _NXBAR_FLITTYPE_MISMATCH_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_EGRESS_NXBAR_FLITTYPE_MISMATCH_ERR, "egress flit type mismatch", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_EGRESS_NXBAR_FLITTYPE_MISMATCH_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_0, _CREDIT_TIME_OUT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_EGRESS_CREDIT_TIME_OUT_ERR, "egress credit timeout", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_EGRESS_CREDIT_TIME_OUT_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_0, _NXBAR_SIDEBAND_PD_PARITY_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_EGRESS_NXBAR_SIDEBAND_PD_PARITY_ERR, "egress crossbar SB parity", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_EGRESS_NXBAR_SIDEBAND_PD_PARITY_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_0, _INVALIDVCSET_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_EGRESS_INVALIDVCSET_ERR, "egress invalid VC set", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_EGRESS_INVALIDVCSET_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + // Disable interrupts that have occurred after fatal error. + // This helps prevent an interrupt storm if HW keeps triggering unnecessary stream of interrupts. + if (device->link[link].fatal_error_occurred) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_FATAL_REPORT_EN_0, + report.raw_enable ^ pending); + } + + if (report.raw_first & report.mask) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_FIRST_0, + report.raw_first & report.mask); + } + + NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_STATUS_0, pending); + + if (unhandled != 0) + { + status = -NVL_MORE_PROCESSING_REQUIRED; + } + +_nvswitch_service_egress_fatal_ls10_err_status_1: + report.raw_pending = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _ERR_STATUS_1); + report.raw_enable = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _ERR_FATAL_REPORT_EN_1); + report.mask = report.raw_enable & chip_device->intr_mask.egress[1].fatal; + pending = report.raw_pending & report.mask; + pending_1 = pending; + + if ((pending_0 == 0) && (pending_1 == 0)) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + report.raw_first = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _ERR_FIRST_1); + contain = NVSWITCH_ENG_RD32(device, NPORT, , link, _EGRESS, _ERR_CONTAIN_EN_1); + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_1, _MCRSPCTRLSTORE_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_EGRESS_MCRSPCTRLSTORE_ECC_DBE_ERR, "egress MC response ECC DBE error", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_EGRESS_MCRSPCTRLSTORE_ECC_DBE_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_EGRESS_MCRSPCTRLSTORE_ECC_DBE_ERR, link, NV_FALSE, 0, + NV_TRUE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + + // Clear associated LIMIT_ERR interrupt + if (report.raw_pending & DRF_NUM(_EGRESS, _ERR_STATUS_1, _MCRSPCTRLSTORE_ECC_LIMIT_ERR, 1)) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_STATUS_1, + DRF_NUM(_EGRESS, _ERR_STATUS_1, _MCRSPCTRLSTORE_ECC_LIMIT_ERR, 1)); + } + } + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_1, _RBCTRLSTORE_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_EGRESS_RBCTRLSTORE_ECC_DBE_ERR, "egress reduction ECC DBE error", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_EGRESS_RBCTRLSTORE_ECC_DBE_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_EGRESS_RBCTRLSTORE_ECC_DBE_ERR, link, NV_FALSE, 0, + NV_TRUE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + + // Clear associated LIMIT_ERR interrupt + if (report.raw_pending & DRF_NUM(_EGRESS, _ERR_STATUS_1, _RBCTRLSTORE_ECC_LIMIT_ERR, 1)) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_STATUS_1, + DRF_NUM(_EGRESS, _ERR_STATUS_1, _RBCTRLSTORE_ECC_LIMIT_ERR, 1)); + } + } + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_1, _MCREDSGT_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_EGRESS_MCREDSGT_ECC_DBE_ERR, "egress MC SG ECC DBE error", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_EGRESS_MCREDSGT_ECC_DBE_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_EGRESS_MCREDSGT_ECC_DBE_ERR, link, NV_FALSE, 0, + NV_TRUE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + + // Clear associated LIMIT_ERR interrupt + if (report.raw_pending & DRF_NUM(_EGRESS, _ERR_STATUS_1, _MCREDSGT_ECC_LIMIT_ERR, 1)) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_STATUS_1, + DRF_NUM(_EGRESS, _ERR_STATUS_1, _MCREDSGT_ECC_LIMIT_ERR, 1)); + } + } + + bit = DRF_NUM(_EGRESS, _ERR_STATUS_1, _MCRSP_RAM_HDR_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_EGRESS_MCRSP_RAM_HDR_ECC_DBE_ERR, "egress MC ram ECC DBE error", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_EGRESS_MCRSP_RAM_HDR_ECC_DBE_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_EGRESS_MCRSP_RAM_HDR_ECC_DBE_ERR, link, NV_FALSE, 0, + NV_TRUE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + + // Clear associated LIMIT_ERR interrupt + if (report.raw_pending & DRF_NUM(_EGRESS, _ERR_STATUS_1, _MCRSP_RAM_HDR_ECC_LIMIT_ERR, 1)) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_STATUS_1, + DRF_NUM(_EGRESS, _ERR_STATUS_1, _MCRSP_RAM_HDR_ECC_LIMIT_ERR, 1)); + } + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + // Disable interrupts that have occurred after fatal error. + // This helps prevent an interrupt storm if HW keeps triggering unnecessary stream of interrupts. + if (device->link[link].fatal_error_occurred) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_FATAL_REPORT_EN_1, + report.raw_enable ^ pending); + } + + if (report.raw_first & report.mask) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_FIRST_1, + report.raw_first & report.mask); + } + + NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_STATUS_1, pending); + + // Clear all pending interrupts! + NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_STATUS_1, 0xFFFFFFFF); + + if (unhandled != 0) + { + status = -NVL_MORE_PROCESSING_REQUIRED; + } + + return status; +} + +static NvlStatus +_nvswitch_service_sourcetrack_nonfatal_ls10 +( + nvswitch_device *device, + NvU32 link +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + NvU32 pending, bit, unhandled; + INFOROM_NVS_ECC_ERROR_EVENT err_event = {0}; + + report.raw_pending = NVSWITCH_ENG_RD32(device, NPORT, , link, + _SOURCETRACK, _ERR_STATUS_0); + report.raw_enable = NVSWITCH_ENG_RD32(device, NPORT, , link, + _SOURCETRACK, _ERR_NON_FATAL_REPORT_EN_0); + report.mask = report.raw_enable & chip_device->intr_mask.sourcetrack.nonfatal; + + pending = report.raw_pending & report.mask; + + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + report.raw_first = NVSWITCH_ENG_RD32(device, NPORT, , link, _SOURCETRACK, _ERR_FIRST_0); + + bit = DRF_NUM(_SOURCETRACK, _ERR_STATUS_0, _CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + // Ignore LIMIT error if DBE is pending + if (!(nvswitch_test_flags(report.raw_pending, + DRF_NUM(_SOURCETRACK, _ERR_STATUS_0, _CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR, 1)))) + { + NvBool bAddressValid = NV_FALSE; + NvU32 address = 0; + NvU32 addressValid = NVSWITCH_ENG_RD32(device, NPORT, , link, _SOURCETRACK, + _ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID); + + if (FLD_TEST_DRF(_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE, _ECC_ERROR_ADDRESS_VALID, + _VALID, _VALID, addressValid)) + { + address = NVSWITCH_ENG_RD32(device, NPORT, , link, _SOURCETRACK, + _ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_ADDRESS); + bAddressValid = NV_TRUE; + } + + report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _SOURCETRACK, + _ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_COUNTER); + report.data[1] = NVSWITCH_ENG_RD32(device, NPORT, , link, _SOURCETRACK, + _ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_ADDRESS); + report.data[2] = NVSWITCH_ENG_RD32(device, NPORT, , link, _SOURCETRACK, + _ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID); + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_SOURCETRACK_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR, + "sourcetrack TCEN0 crumbstore ECC limit err"); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_SOURCETRACK_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR, link, + bAddressValid, address, NV_FALSE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + nvswitch_clear_flags(&unhandled, bit); + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + // + // Disable interrupts that have occurred after fatal error. + // This helps prevent an interrupt storm if HW keeps triggering unnecessary stream of interrupts. + // + if (device->link[link].fatal_error_occurred) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _SOURCETRACK, _ERR_NON_FATAL_REPORT_EN_0, + report.raw_enable ^ pending); + } + + if (report.raw_first & report.mask) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _SOURCETRACK, _ERR_FIRST_0, + report.raw_first & report.mask); + } + + NVSWITCH_ENG_WR32(device, NPORT, , link, _SOURCETRACK, _ERR_STATUS_0, pending); + + if (unhandled != 0) + { + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_nvswitch_service_sourcetrack_fatal_ls10 +( + nvswitch_device *device, + NvU32 link +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + NvU32 pending, bit, contain, unhandled; + INFOROM_NVS_ECC_ERROR_EVENT err_event = {0}; + + report.raw_pending = NVSWITCH_ENG_RD32(device, NPORT, , link, + _SOURCETRACK, _ERR_STATUS_0); + report.raw_enable = NVSWITCH_ENG_RD32(device, NPORT, , link, + _SOURCETRACK, _ERR_FATAL_REPORT_EN_0); + report.mask = report.raw_enable & chip_device->intr_mask.sourcetrack.fatal; + pending = report.raw_pending & report.mask; + + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + report.raw_first = NVSWITCH_ENG_RD32(device, NPORT, , link, _SOURCETRACK, _ERR_FIRST_0); + contain = NVSWITCH_ENG_RD32(device, NPORT, , link, _SOURCETRACK, _ERR_CONTAIN_EN_0); + + bit = DRF_NUM(_SOURCETRACK, _ERR_STATUS_0, _CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NvBool bAddressValid = NV_FALSE; + NvU32 address = 0; + NvU32 addressValid = NVSWITCH_ENG_RD32(device, NPORT, , link, _SOURCETRACK, + _ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID); + + if (FLD_TEST_DRF(_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE, _ECC_ERROR_ADDRESS_VALID, + _VALID, _VALID, addressValid)) + { + address = NVSWITCH_ENG_RD32(device, NPORT, , link, _SOURCETRACK, + _ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_ADDRESS); + bAddressValid = NV_TRUE; + } + + report.data[0] = NVSWITCH_ENG_RD32(device, NPORT, , link, _SOURCETRACK, + _ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_ADDRESS); + report.data[1] = NVSWITCH_ENG_RD32(device, NPORT, , link, _SOURCETRACK, + _ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID); + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_SOURCETRACK_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR, + "sourcetrack TCEN0 crumbstore DBE", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_SOURCETRACK_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR, + link, bAddressValid, address, NV_TRUE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + + // Clear associated LIMIT_ERR interrupt + if (report.raw_pending & DRF_NUM(_SOURCETRACK, _ERR_STATUS_0, _CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR, 1)) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _SOURCETRACK, _ERR_STATUS_0, + DRF_NUM(_SOURCETRACK, _ERR_STATUS_0, _CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR, 1)); + } + } + + bit = DRF_NUM(_SOURCETRACK, _ERR_STATUS_0, _DUP_CREQ_TCEN0_TAG_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_SOURCETRACK_DUP_CREQ_TCEN0_TAG_ERR, + "sourcetrack duplicate CREQ", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_SOURCETRACK, _ERR_STATUS_0, _INVALID_TCEN0_RSP_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_SOURCETRACK_INVALID_TCEN0_RSP_ERR, + "sourcetrack invalid TCEN0 CREQ", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_SOURCETRACK, _ERR_STATUS_0, _INVALID_TCEN1_RSP_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_SOURCETRACK_INVALID_TCEN1_RSP_ERR, + "sourcetrack invalid TCEN1 CREQ", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_SOURCETRACK, _ERR_STATUS_0, _SOURCETRACK_TIME_OUT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_SOURCETRACK_SOURCETRACK_TIME_OUT_ERR, + "sourcetrack timeout error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + // + // Disable interrupts that have occurred after fatal error. + // This helps prevent an interrupt storm if HW keeps triggering unnecessary stream of interrupts. + // + if (device->link[link].fatal_error_occurred) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _SOURCETRACK, _ERR_FATAL_REPORT_EN_0, + report.raw_enable ^ pending); + } + + if (report.raw_first & report.mask) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _SOURCETRACK, _ERR_FIRST_0, + report.raw_first & report.mask); + } + + NVSWITCH_ENG_WR32(device, NPORT, , link, _SOURCETRACK, _ERR_STATUS_0, pending); + + if (unhandled != 0) + { + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; + +} + +// +// Multicast Tstate +// + +static NvlStatus +_nvswitch_service_multicast_nonfatal_ls10 +( + nvswitch_device *device, + NvU32 link +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + NvU32 pending, bit, unhandled; + NVSWITCH_RAW_ERROR_LOG_TYPE data = {0, { 0 }}; + INFOROM_NVS_ECC_ERROR_EVENT err_event = {0}; + + report.raw_pending = NVSWITCH_ENG_RD32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_STATUS_0); + report.raw_enable = NVSWITCH_ENG_RD32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_NON_FATAL_REPORT_EN_0); + report.mask = report.raw_enable & chip_device->intr_mask.mc_tstate.nonfatal; + pending = report.raw_pending & report.mask; + + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + report.raw_first = NVSWITCH_ENG_RD32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_FIRST_0); + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_MC_TIME, + &data); + + bit = DRF_NUM(_MULTICASTTSTATE, _ERR_STATUS_0, _TAGPOOL_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + // Ignore LIMIT error if DBE is pending + if(!(nvswitch_test_flags(report.raw_pending, + DRF_NUM(_MULTICASTTSTATE, _ERR_STATUS_0, _TAGPOOL_ECC_DBE_ERR, 1)))) + { + NvBool bAddressValid = NV_FALSE; + NvU32 address = 0; + NvU32 addressValid = NVSWITCH_ENG_RD32(device, NPORT, , link, _MULTICASTTSTATE, + _ERR_TAGPOOL_ECC_ERROR_ADDRESS_VALID); + + if (FLD_TEST_DRF(_MULTICASTTSTATE_ERR_TAGPOOL, _ECC_ERROR_ADDRESS_VALID, _VALID, _VALID, + addressValid)) + { + address = NVSWITCH_ENG_RD32(device, NPORT, , link, _MULTICASTTSTATE, + _ERR_TAGPOOL_ECC_ERROR_ADDRESS); + bAddressValid = NV_TRUE; + } + + report.data[1] = NVSWITCH_ENG_RD32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER); + NVSWITCH_ENG_WR32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER, + DRF_DEF(_MULTICASTTSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER, _ERROR_COUNT, _INIT)); + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_MULTICASTTSTATE_TAGPOOL_ECC_LIMIT_ERR, "MC TS tag store single-bit threshold"); + NVSWITCH_REPORT_DATA(_HW_NPORT_MULTICASTTSTATE_TAGPOOL_ECC_LIMIT_ERR, data); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_TAGPOOL_ECC_LIMIT_ERR, link, + bAddressValid, address, NV_FALSE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_MULTICASTTSTATE, _ERR_STATUS_0, _CRUMBSTORE_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + // Ignore LIMIT error if DBE is pending + if(!(nvswitch_test_flags(report.raw_pending, + DRF_NUM(_MULTICASTTSTATE, _ERR_STATUS_0, _CRUMBSTORE_ECC_DBE_ERR, 1)))) + { + NvBool bAddressValid = NV_FALSE; + NvU32 address = 0; + NvU32 addressValid = NVSWITCH_ENG_RD32(device, NPORT, , link, _MULTICASTTSTATE, + _ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID); + + if (FLD_TEST_DRF(_MULTICASTTSTATE_ERR_CRUMBSTORE, _ECC_ERROR_ADDRESS_VALID, _VALID, _VALID, + addressValid)) + { + address = NVSWITCH_ENG_RD32(device, NPORT, , link, _MULTICASTTSTATE, + _ERR_CRUMBSTORE_ECC_ERROR_ADDRESS); + bAddressValid = NV_TRUE; + } + + report.data[1] = NVSWITCH_ENG_RD32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER); + NVSWITCH_ENG_WR32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER, + DRF_DEF(_MULTICASTTSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER, _ERROR_COUNT, _INIT)); + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_MULTICASTTSTATE_CRUMBSTORE_ECC_LIMIT_ERR, "MC TS crumbstore single-bit threshold"); + NVSWITCH_REPORT_DATA(_HW_NPORT_MULTICASTTSTATE_CRUMBSTORE_ECC_LIMIT_ERR, data); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_CRUMBSTORE_ECC_LIMIT_ERR, link, + bAddressValid, address, NV_FALSE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_MULTICASTTSTATE, _ERR_STATUS_0, _CRUMBSTORE_MCTO_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_MULTICASTTSTATE_CRUMBSTORE_MCTO_ERR, "MC TS crumbstore MCTO"); + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_HDR, + &data); + NVSWITCH_REPORT_DATA(_HW_NPORT_MULTICASTTSTATE_CRUMBSTORE_MCTO_ERR, data); + + nvswitch_clear_flags(&unhandled, bit); + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + // Disable interrupts that have occurred after fatal error. + // This helps prevent an interrupt storm if HW keeps triggering unnecessary stream of interrupts. + if (device->link[link].fatal_error_occurred) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_NON_FATAL_REPORT_EN_0, + report.raw_enable ^ pending); + } + + if (report.raw_first & report.mask) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_FIRST_0, + report.raw_first & report.mask); + } + + NVSWITCH_ENG_WR32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_STATUS_0, pending); + + if (unhandled != 0) + { + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_nvswitch_service_multicast_fatal_ls10 +( + nvswitch_device *device, + NvU32 link +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + NvU32 pending, bit, contain, unhandled; + NVSWITCH_RAW_ERROR_LOG_TYPE data = {0, { 0 }}; + INFOROM_NVS_ECC_ERROR_EVENT err_event = {0}; + + report.raw_pending = NVSWITCH_ENG_RD32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_STATUS_0); + report.raw_enable = NVSWITCH_ENG_RD32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_FATAL_REPORT_EN_0); + report.mask = report.raw_enable & chip_device->intr_mask.mc_tstate.fatal; + pending = report.raw_pending & report.mask; + + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + report.raw_first = NVSWITCH_ENG_RD32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_FIRST_0); + contain = NVSWITCH_ENG_RD32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_CONTAIN_EN_0); + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_MC_TIME, + &data); + + bit = DRF_NUM(_MULTICASTTSTATE, _ERR_STATUS_0, _TAGPOOL_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NvBool bAddressValid = NV_FALSE; + NvU32 address = 0; + NvU32 addressValid = NVSWITCH_ENG_RD32(device, NPORT, , link, _MULTICASTTSTATE, + _ERR_TAGPOOL_ECC_ERROR_ADDRESS_VALID); + + if (FLD_TEST_DRF(_MULTICASTTSTATE_ERR_TAGPOOL, _ECC_ERROR_ADDRESS_VALID, _VALID, _VALID, + addressValid)) + { + address = NVSWITCH_ENG_RD32(device, NPORT, , link, _MULTICASTTSTATE, + _ERR_TAGPOOL_ECC_ERROR_ADDRESS); + bAddressValid = NV_TRUE; + } + + report.data[1] = NVSWITCH_ENG_RD32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER); + NVSWITCH_ENG_WR32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER, + DRF_DEF(_MULTICASTTSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER, _ERROR_COUNT, _INIT)); + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_MULTICASTTSTATE_TAGPOOL_ECC_DBE_ERR, "MC TS tag store fatal ECC", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_MULTICASTTSTATE_TAGPOOL_ECC_DBE_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_TAGPOOL_ECC_DBE_ERR, link, bAddressValid, + address, NV_TRUE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + + // Clear associated LIMIT_ERR interrupt + if (report.raw_pending & DRF_NUM(_MULTICASTTSTATE, _ERR_STATUS_0, _TAGPOOL_ECC_LIMIT_ERR, 1)) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_STATUS_0, + DRF_NUM(_MULTICASTTSTATE, _ERR_STATUS_0, _TAGPOOL_ECC_LIMIT_ERR, 1)); + } + } + + bit = DRF_NUM(_MULTICASTTSTATE, _ERR_STATUS_0, _CRUMBSTORE_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NvBool bAddressValid = NV_FALSE; + NvU32 address = 0; + NvU32 addressValid = NVSWITCH_ENG_RD32(device, NPORT, , link, _MULTICASTTSTATE, + _ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID); + + if (FLD_TEST_DRF(_MULTICASTTSTATE_ERR_CRUMBSTORE, _ECC_ERROR_ADDRESS_VALID, _VALID, _VALID, + addressValid)) + { + address = NVSWITCH_ENG_RD32(device, NPORT, , link, _MULTICASTTSTATE, + _ERR_CRUMBSTORE_ECC_ERROR_ADDRESS); + bAddressValid = NV_TRUE; + } + + report.data[1] = NVSWITCH_ENG_RD32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER); + NVSWITCH_ENG_WR32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER, + DRF_DEF(_MULTICASTTSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER, _ERROR_COUNT, _INIT)); + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_MULTICASTTSTATE_CRUMBSTORE_ECC_DBE_ERR, "MC TS crumbstore fatal ECC", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_MULTICASTTSTATE_CRUMBSTORE_ECC_DBE_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_CRUMBSTORE_ECC_DBE_ERR, link, bAddressValid, + address, NV_TRUE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + + // Clear associated LIMIT_ERR interrupt + if (report.raw_pending & DRF_NUM(_MULTICASTTSTATE, _ERR_STATUS_0, _CRUMBSTORE_ECC_LIMIT_ERR, 1)) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_STATUS_0, + DRF_NUM(_MULTICASTTSTATE, _ERR_STATUS_0, _CRUMBSTORE_ECC_LIMIT_ERR, 1)); + } + } + + bit = DRF_NUM(_MULTICASTTSTATE, _ERR_STATUS_0, _CRUMBSTORE_BUF_OVERWRITE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_MULTICASTTSTATE_CRUMBSTORE_BUF_OVERWRITE_ERR, "MC crumbstore overwrite", NV_FALSE); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_MULTICASTTSTATE_CRUMBSTORE_BUF_OVERWRITE_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + // Disable interrupts that have occurred after fatal error. + // This helps prevent an interrupt storm if HW keeps triggering unnecessary stream of interrupts. + if (device->link[link].fatal_error_occurred) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_FATAL_REPORT_EN_0, + report.raw_enable ^ pending); + } + + if (report.raw_first & report.mask) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_FIRST_0, + report.raw_first & report.mask); + } + + NVSWITCH_ENG_WR32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_STATUS_0, pending); + + if (unhandled != 0) + { + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +// +// Reduction Tstate +// + +static NvlStatus +_nvswitch_service_reduction_nonfatal_ls10 +( + nvswitch_device *device, + NvU32 link +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + NvU32 pending, bit, unhandled; + NVSWITCH_RAW_ERROR_LOG_TYPE data = {0, { 0 }}; + INFOROM_NVS_ECC_ERROR_EVENT err_event = {0}; + + report.raw_pending = NVSWITCH_ENG_RD32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_STATUS_0); + report.raw_enable = NVSWITCH_ENG_RD32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_NON_FATAL_REPORT_EN_0); + report.mask = report.raw_enable & chip_device->intr_mask.mc_tstate.nonfatal; + pending = report.raw_pending & report.mask; + + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + report.raw_first = NVSWITCH_ENG_RD32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_FIRST_0); + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_RED_TIME, + &data); + + bit = DRF_NUM(_REDUCTIONTSTATE, _ERR_STATUS_0, _TAGPOOL_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + // Ignore LIMIT error if DBE is pending + if(!(nvswitch_test_flags(report.raw_pending, + DRF_NUM(_REDUCTIONTSTATE, _ERR_STATUS_0, _TAGPOOL_ECC_DBE_ERR, 1)))) + { + NvBool bAddressValid = NV_FALSE; + NvU32 address = 0; + NvU32 addressValid = NVSWITCH_ENG_RD32(device, NPORT, , link, _REDUCTIONTSTATE, + _ERR_TAGPOOL_ECC_ERROR_ADDRESS_VALID); + + if (FLD_TEST_DRF(_REDUCTIONTSTATE_ERR_TAGPOOL, _ECC_ERROR_ADDRESS_VALID, _VALID, _VALID, + addressValid)) + { + address = NVSWITCH_ENG_RD32(device, NPORT, , link, _REDUCTIONTSTATE, + _ERR_TAGPOOL_ECC_ERROR_ADDRESS); + bAddressValid = NV_TRUE; + } + + report.data[1] = NVSWITCH_ENG_RD32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER); + NVSWITCH_ENG_WR32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER, + DRF_DEF(_REDUCTIONTSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER, _ERROR_COUNT, _INIT)); + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_REDUCTIONTSTATE_TAGPOOL_ECC_LIMIT_ERR, "Red TS tag store single-bit threshold"); + NVSWITCH_REPORT_DATA(_HW_NPORT_REDUCTIONTSTATE_TAGPOOL_ECC_LIMIT_ERR, data); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_TAGPOOL_ECC_LIMIT_ERR, link, + bAddressValid, address, NV_FALSE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_REDUCTIONTSTATE, _ERR_STATUS_0, _CRUMBSTORE_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + // Ignore LIMIT error if DBE is pending + if(!(nvswitch_test_flags(report.raw_pending, + DRF_NUM(_REDUCTIONTSTATE, _ERR_STATUS_0, _CRUMBSTORE_ECC_DBE_ERR, 1)))) + { + NvBool bAddressValid = NV_FALSE; + NvU32 address = 0; + NvU32 addressValid = NVSWITCH_ENG_RD32(device, NPORT, , link, _REDUCTIONTSTATE, + _ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID); + + if (FLD_TEST_DRF(_REDUCTIONTSTATE_ERR_CRUMBSTORE, _ECC_ERROR_ADDRESS_VALID, _VALID, _VALID, + addressValid)) + { + address = NVSWITCH_ENG_RD32(device, NPORT, , link, _REDUCTIONTSTATE, + _ERR_CRUMBSTORE_ECC_ERROR_ADDRESS); + bAddressValid = NV_TRUE; + } + + report.data[1] = NVSWITCH_ENG_RD32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER); + NVSWITCH_ENG_WR32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER, + DRF_DEF(_REDUCTIONTSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER, _ERROR_COUNT, _INIT)); + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_REDUCTIONTSTATE_CRUMBSTORE_ECC_LIMIT_ERR, "Red TS crumbstore single-bit threshold"); + NVSWITCH_REPORT_DATA(_HW_NPORT_REDUCTIONTSTATE_CRUMBSTORE_ECC_LIMIT_ERR, data); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_CRUMBSTORE_ECC_LIMIT_ERR, link, + bAddressValid, address, NV_FALSE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + } + + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_REDUCTIONTSTATE, _ERR_STATUS_0, _CRUMBSTORE_RTO_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NPORT_REDUCTIONTSTATE_CRUMBSTORE_RTO_ERR, "Red TS crumbstore RTO"); + NVSWITCH_REPORT_DATA(_HW_NPORT_REDUCTIONTSTATE_CRUMBSTORE_RTO_ERR, data); + + nvswitch_clear_flags(&unhandled, bit); + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + // Disable interrupts that have occurred after fatal error. + // This helps prevent an interrupt storm if HW keeps triggering unnecessary stream of interrupts. + if (device->link[link].fatal_error_occurred) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_NON_FATAL_REPORT_EN_0, + report.raw_enable ^ pending); + } + + if (report.raw_first & report.mask) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_FIRST_0, + report.raw_first & report.mask); + } + + NVSWITCH_ENG_WR32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_STATUS_0, pending); + + if (unhandled != 0) + { + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_nvswitch_service_reduction_fatal_ls10 +( + nvswitch_device *device, + NvU32 link +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + NvU32 pending, bit, contain, unhandled; + NVSWITCH_RAW_ERROR_LOG_TYPE data = {0, { 0 }}; + INFOROM_NVS_ECC_ERROR_EVENT err_event = {0}; + + report.raw_pending = NVSWITCH_ENG_RD32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_STATUS_0); + report.raw_enable = NVSWITCH_ENG_RD32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_FATAL_REPORT_EN_0); + report.mask = report.raw_enable & chip_device->intr_mask.mc_tstate.fatal; + pending = report.raw_pending & report.mask; + + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + report.raw_first = NVSWITCH_ENG_RD32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_FIRST_0); + contain = NVSWITCH_ENG_RD32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_CONTAIN_EN_0); + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_RED_TIME, + &data); + + bit = DRF_NUM(_REDUCTIONTSTATE, _ERR_STATUS_0, _TAGPOOL_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NvBool bAddressValid = NV_FALSE; + NvU32 address = 0; + NvU32 addressValid = NVSWITCH_ENG_RD32(device, NPORT, , link, _REDUCTIONTSTATE, + _ERR_TAGPOOL_ECC_ERROR_ADDRESS_VALID); + + if (FLD_TEST_DRF(_REDUCTIONTSTATE_ERR_TAGPOOL, _ECC_ERROR_ADDRESS_VALID, _VALID, _VALID, + addressValid)) + { + address = NVSWITCH_ENG_RD32(device, NPORT, , link, _REDUCTIONTSTATE, + _ERR_TAGPOOL_ECC_ERROR_ADDRESS); + bAddressValid = NV_TRUE; + } + + report.data[1] = NVSWITCH_ENG_RD32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER); + NVSWITCH_ENG_WR32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER, + DRF_DEF(_REDUCTIONTSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER, _ERROR_COUNT, _INIT)); + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_REDUCTIONTSTATE_TAGPOOL_ECC_DBE_ERR, "Red TS tag store fatal ECC", NV_FALSE); + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_HDR, + &data); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_REDUCTIONTSTATE_TAGPOOL_ECC_DBE_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_TAGPOOL_ECC_DBE_ERR, link, bAddressValid, + address, NV_TRUE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + + // Clear associated LIMIT_ERR interrupt + if (report.raw_pending & DRF_NUM(_REDUCTIONTSTATE, _ERR_STATUS_0, _TAGPOOL_ECC_LIMIT_ERR, 1)) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_STATUS_0, + DRF_NUM(_REDUCTIONTSTATE, _ERR_STATUS_0, _TAGPOOL_ECC_LIMIT_ERR, 1)); + } + } + + bit = DRF_NUM(_REDUCTIONTSTATE, _ERR_STATUS_0, _CRUMBSTORE_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NvBool bAddressValid = NV_FALSE; + NvU32 address = 0; + NvU32 addressValid = NVSWITCH_ENG_RD32(device, NPORT, , link, _REDUCTIONTSTATE, + _ERR_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID); + + if (FLD_TEST_DRF(_REDUCTIONTSTATE_ERR_CRUMBSTORE, _ECC_ERROR_ADDRESS_VALID, _VALID, _VALID, + addressValid)) + { + address = NVSWITCH_ENG_RD32(device, NPORT, , link, _REDUCTIONTSTATE, + _ERR_CRUMBSTORE_ECC_ERROR_ADDRESS); + bAddressValid = NV_TRUE; + } + + report.data[1] = NVSWITCH_ENG_RD32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER); + NVSWITCH_ENG_WR32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER, + DRF_DEF(_REDUCTIONTSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER, _ERROR_COUNT, _INIT)); + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_REDUCTIONTSTATE_CRUMBSTORE_ECC_DBE_ERR, "Red TS crumbstore fatal ECC", NV_FALSE); + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_HDR, + &data); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_REDUCTIONTSTATE_CRUMBSTORE_ECC_DBE_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + + _nvswitch_construct_ecc_error_event_ls10(&err_event, + NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_CRUMBSTORE_ECC_DBE_ERR, link, bAddressValid, + address, NV_TRUE, 1); + + nvswitch_inforom_ecc_log_err_event(device, &err_event); + + // Clear associated LIMIT_ERR interrupt + if (report.raw_pending & DRF_NUM(_REDUCTIONTSTATE, _ERR_STATUS_0, _CRUMBSTORE_ECC_LIMIT_ERR, 1)) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_STATUS_0, + DRF_NUM(_REDUCTIONTSTATE, _ERR_STATUS_0, _CRUMBSTORE_ECC_LIMIT_ERR, 1)); + } + } + + bit = DRF_NUM(_REDUCTIONTSTATE, _ERR_STATUS_0, _CRUMBSTORE_BUF_OVERWRITE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_CONTAIN(_HW_NPORT_REDUCTIONTSTATE_CRUMBSTORE_BUF_OVERWRITE_ERR, "Red crumbstore overwrite", NV_FALSE); + _nvswitch_collect_error_info_ls10(device, link, + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_TIME | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_MISC | + NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_HDR, + &data); + NVSWITCH_REPORT_CONTAIN_DATA(_HW_NPORT_REDUCTIONTSTATE_CRUMBSTORE_BUF_OVERWRITE_ERR, data); + nvswitch_clear_flags(&unhandled, bit); + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + // Disable interrupts that have occurred after fatal error. + // This helps prevent an interrupt storm if HW keeps triggering unnecessary stream of interrupts. + if (device->link[link].fatal_error_occurred) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_FATAL_REPORT_EN_0, + report.raw_enable ^ pending); + } + + if (report.raw_first & report.mask) + { + NVSWITCH_ENG_WR32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_FIRST_0, + report.raw_first & report.mask); + } + + NVSWITCH_ENG_WR32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_STATUS_0, pending); + + if (unhandled != 0) + { + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_nvswitch_service_nport_fatal_ls10 +( + nvswitch_device *device, + NvU32 link +) +{ + NvlStatus status[7]; + + status[0] = _nvswitch_service_route_fatal_ls10(device, link); + status[1] = _nvswitch_service_ingress_fatal_ls10(device, link); + status[2] = _nvswitch_service_egress_fatal_ls10(device, link); + status[3] = _nvswitch_service_tstate_fatal_ls10(device, link); + status[4] = _nvswitch_service_sourcetrack_fatal_ls10(device, link); + status[5] = _nvswitch_service_multicast_fatal_ls10(device, link); + status[6] = _nvswitch_service_reduction_fatal_ls10(device, link); + + if ((status[0] != NVL_SUCCESS) && + (status[1] != NVL_SUCCESS) && + (status[2] != NVL_SUCCESS) && + (status[3] != NVL_SUCCESS) && + (status[4] != NVL_SUCCESS) && + (status[5] != NVL_SUCCESS) && + (status[6] != NVL_SUCCESS)) + { + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_nvswitch_service_npg_fatal_ls10 +( + nvswitch_device *device, + NvU32 npg +) +{ + NvU32 pending, mask, bit, unhandled; + NvU32 nport; + NvU32 link; + + pending = NVSWITCH_ENG_RD32(device, NPG, , npg, _NPG, _NPG_INTERRUPT_STATUS); + + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + mask = + DRF_DEF(_NPG, _NPG_INTERRUPT_STATUS, _DEV0_INT_STATUS, _FATAL) | + DRF_DEF(_NPG, _NPG_INTERRUPT_STATUS, _DEV1_INT_STATUS, _FATAL) | + DRF_DEF(_NPG, _NPG_INTERRUPT_STATUS, _DEV2_INT_STATUS, _FATAL) | + DRF_DEF(_NPG, _NPG_INTERRUPT_STATUS, _DEV3_INT_STATUS, _FATAL); + pending &= mask; + unhandled = pending; + + for (nport = 0; nport < NVSWITCH_NPORT_PER_NPG_LS10; nport++) + { + switch (nport) + { + case 0: + bit = DRF_DEF(_NPG, _NPG_INTERRUPT_STATUS, _DEV0_INT_STATUS, _FATAL); + break; + case 1: + bit = DRF_DEF(_NPG, _NPG_INTERRUPT_STATUS, _DEV1_INT_STATUS, _FATAL); + break; + case 2: + bit = DRF_DEF(_NPG, _NPG_INTERRUPT_STATUS, _DEV2_INT_STATUS, _FATAL); + break; + case 3: + bit = DRF_DEF(_NPG, _NPG_INTERRUPT_STATUS, _DEV3_INT_STATUS, _FATAL); + break; + } + if (nvswitch_test_flags(pending, bit)) + { + link = NPORT_TO_LINK_LS10(device, npg, nport); + if (NVSWITCH_ENG_IS_VALID(device, NPORT, link)) + { + if (_nvswitch_service_nport_fatal_ls10(device, link) == NVL_SUCCESS) + { + nvswitch_clear_flags(&unhandled, bit); + } + } + } + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + if (unhandled != 0) + { + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_nvswitch_service_nport_nonfatal_ls10 +( + nvswitch_device *device, + NvU32 link +) +{ + NvlStatus status[7]; + + status[0] = _nvswitch_service_route_nonfatal_ls10(device, link); + status[1] = _nvswitch_service_ingress_nonfatal_ls10(device, link); + status[2] = _nvswitch_service_egress_nonfatal_ls10(device, link); + status[3] = _nvswitch_service_tstate_nonfatal_ls10(device, link); + status[4] = _nvswitch_service_sourcetrack_nonfatal_ls10(device, link); + status[5] = _nvswitch_service_multicast_nonfatal_ls10(device, link); + status[6] = _nvswitch_service_reduction_nonfatal_ls10(device, link); + + if ((status[0] != NVL_SUCCESS) && + (status[1] != NVL_SUCCESS) && + (status[2] != NVL_SUCCESS) && + (status[3] != NVL_SUCCESS) && + (status[4] != NVL_SUCCESS) && + (status[5] != NVL_SUCCESS) && + (status[6] != NVL_SUCCESS)) + { + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_nvswitch_service_npg_nonfatal_ls10 +( + nvswitch_device *device, + NvU32 npg +) +{ + NvU32 pending, mask, bit, unhandled; + NvU32 nport; + NvU32 link; + + pending = NVSWITCH_ENG_RD32(device, NPG, , npg, _NPG, _NPG_INTERRUPT_STATUS); + + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + mask = + DRF_DEF(_NPG, _NPG_INTERRUPT_STATUS, _DEV0_INT_STATUS, _NONFATAL) | + DRF_DEF(_NPG, _NPG_INTERRUPT_STATUS, _DEV1_INT_STATUS, _NONFATAL) | + DRF_DEF(_NPG, _NPG_INTERRUPT_STATUS, _DEV2_INT_STATUS, _NONFATAL) | + DRF_DEF(_NPG, _NPG_INTERRUPT_STATUS, _DEV3_INT_STATUS, _NONFATAL); + pending &= mask; + unhandled = pending; + + for (nport = 0; nport < NVSWITCH_NPORT_PER_NPG_LS10; nport++) + { + switch (nport) + { + case 0: + bit = DRF_DEF(_NPG, _NPG_INTERRUPT_STATUS, _DEV0_INT_STATUS, _NONFATAL); + break; + case 1: + bit = DRF_DEF(_NPG, _NPG_INTERRUPT_STATUS, _DEV1_INT_STATUS, _NONFATAL); + break; + case 2: + bit = DRF_DEF(_NPG, _NPG_INTERRUPT_STATUS, _DEV2_INT_STATUS, _NONFATAL); + break; + case 3: + bit = DRF_DEF(_NPG, _NPG_INTERRUPT_STATUS, _DEV3_INT_STATUS, _NONFATAL); + break; + } + if (nvswitch_test_flags(pending, bit)) + { + link = NPORT_TO_LINK_LS10(device, npg, nport); + if (NVSWITCH_ENG_IS_VALID(device, NPORT, link)) + { + if (_nvswitch_service_nport_nonfatal_ls10(device, link) == NVL_SUCCESS) + { + nvswitch_clear_flags(&unhandled, bit); + } + } + } + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + if (unhandled != 0) + { + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_nvswitch_service_nvldl_fatal_ls10 +( + nvswitch_device *device, + NvU32 nvlipt_instance +) +{ + NvU64 enabledLinkMask, localLinkMask, localEnabledLinkMask, runtimeErrorMask = 0; + NvU32 i; + nvlink_link *link; + NvlStatus status = -NVL_MORE_PROCESSING_REQUIRED; + NVSWITCH_LINK_TRAINING_ERROR_INFO linkTrainingErrorInfo = { 0 }; + NVSWITCH_LINK_RUNTIME_ERROR_INFO linkRuntimeErrorInfo = { 0 }; + + enabledLinkMask = nvswitch_get_enabled_link_mask(device); + localLinkMask = NVSWITCH_NVLIPT_GET_LOCAL_LINK_MASK64_LS10(nvlipt_instance); + localEnabledLinkMask = enabledLinkMask & localLinkMask; + + FOR_EACH_INDEX_IN_MASK(64, i, localEnabledLinkMask) + { + link = nvswitch_get_link(device, i); + if (link == NULL) + { + // An interrupt on an invalid link should never occur + NVSWITCH_ASSERT(link != NULL); + continue; + } + + if (NVSWITCH_GET_LINK_ENG_INST(device, i, NVLIPT) != nvlipt_instance) + { + NVSWITCH_ASSERT(0); + break; + } + + if (nvswitch_is_link_in_reset(device, link)) + { + continue; + } + + if (device->hal.nvswitch_service_nvldl_fatal_link(device, nvlipt_instance, i) == NVL_SUCCESS) + { + runtimeErrorMask |= NVBIT64(i); + status = NVL_SUCCESS; + } + } + FOR_EACH_INDEX_IN_MASK_END; + + linkTrainingErrorInfo.isValid = NV_FALSE; + linkRuntimeErrorInfo.isValid = NV_TRUE; + linkRuntimeErrorInfo.mask0 = runtimeErrorMask; + + // Check runtimeErrorMask is non-zero before consuming it further. + if ((runtimeErrorMask != 0) && + (nvswitch_smbpbi_set_link_error_info(device, + &linkTrainingErrorInfo, &linkRuntimeErrorInfo) != NVL_SUCCESS)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: NVLDL[0x%x, 0x%llx]: Unable to send Runtime Error bitmask: 0x%llx,\n", + __FUNCTION__, + nvlipt_instance, localLinkMask, + runtimeErrorMask); + } + + return status; +} + +static NvlStatus +_nvswitch_service_nvltlc_tx_sys_fatal_ls10 +( + nvswitch_device *device, + NvU32 nvlipt_instance, + NvU32 link +) +{ + NvU32 pending, bit, unhandled; + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + + report.raw_pending = NVSWITCH_LINK_RD32_LS10(device, link, NVLTLC, _NVLTLC_TX_SYS, _ERR_STATUS_0); + report.raw_enable = NVSWITCH_LINK_RD32_LS10(device, link, NVLTLC, _NVLTLC_TX_SYS, _ERR_FATAL_REPORT_EN_0); + report.mask = report.raw_enable; + pending = report.raw_pending & report.mask; + + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + report.raw_first = NVSWITCH_LINK_RD32_LS10(device, link, NVLTLC, _NVLTLC_TX_SYS, _ERR_FIRST_0); + + bit = DRF_NUM(_NVLTLC_TX_SYS, _ERR_STATUS_0, _NCISOC_PARITY_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_TX_SYS_NCISOC_PARITY_ERR, "NCISOC Parity Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_TX_SYS, _ERR_STATUS_0, _NCISOC_HDR_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_TX_SYS_NCISOC_HDR_ECC_DBE_ERR, "NCISOC HDR ECC DBE Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_TX_SYS, _ERR_STATUS_0, _NCISOC_DAT_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_TX_SYS_NCISOC_DAT_ECC_DBE_ERR, "NCISOC DAT ECC DBE Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_TX_SYS, _ERR_STATUS_0, _NCISOC_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_TX_SYS_NCISOC_ECC_LIMIT_ERR, "NCISOC ECC Limit Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_TX_SYS, _ERR_STATUS_0, _TXPOISONDET, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_TXPOISONDET, "Poison Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_TX_SYS, _ERR_STATUS_0, _TXRSPSTATUS_HW_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_TX_SYS_TXRSPSTATUS_HW_ERR, "TX Response Status HW Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_TX_SYS, _ERR_STATUS_0, _TXRSPSTATUS_UR_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_TX_SYS_TXRSPSTATUS_UR_ERR, "TX Response Status UR Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_TX_SYS, _ERR_STATUS_0, _TXRSPSTATUS_PRIV_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_TX_SYS_TXRSPSTATUS_PRIV_ERR, "TX Response Status PRIV Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + if (report.raw_first & report.mask) + { + NVSWITCH_LINK_WR32_LS10(device, link, NVLTLC, _NVLTLC_TX_SYS, _ERR_FIRST_0, + report.raw_first & report.mask); + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + // Disable interrupts that have occurred after fatal error. + if (device->link[link].fatal_error_occurred) + { + NVSWITCH_LINK_WR32_LS10(device, link, NVLTLC, _NVLTLC_TX_SYS, _ERR_FATAL_REPORT_EN_0, + report.raw_enable ^ pending); + } + + NVSWITCH_LINK_WR32_LS10(device, link, NVLTLC, _NVLTLC_TX_SYS, _ERR_STATUS_0, pending); + + if (unhandled != 0) + { + NVSWITCH_PRINT(device, WARN, + "%s: Unhandled NVLTLC_TX_SYS interrupts, link: %d pending: 0x%x enabled: 0x%x.\n", + __FUNCTION__, link, pending, report.raw_enable); + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_nvswitch_service_nvltlc_rx_sys_fatal_ls10 +( + nvswitch_device *device, + NvU32 nvlipt_instance, + NvU32 link +) +{ + NvU32 pending, bit, unhandled; + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + + report.raw_pending = NVSWITCH_LINK_RD32_LS10(device, link, NVLTLC, _NVLTLC_RX_SYS, _ERR_STATUS_0); + report.raw_enable = NVSWITCH_LINK_RD32_LS10(device, link, NVLTLC, _NVLTLC_RX_SYS, _ERR_FATAL_REPORT_EN_0); + report.mask = report.raw_enable; + pending = report.raw_pending & report.mask; + + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + report.raw_first = NVSWITCH_LINK_RD32_LS10(device, link, NVLTLC, _NVLTLC_RX_SYS, _ERR_FIRST_0); + + bit = DRF_NUM(_NVLTLC_RX_SYS, _ERR_STATUS_0, _NCISOC_PARITY_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RX_SYS_NCISOC_PARITY_ERR, "NCISOC Parity Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_RX_SYS, _ERR_STATUS_0, _HDR_RAM_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RX_SYS_HDR_RAM_ECC_DBE_ERR, "HDR RAM ECC DBE Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_RX_SYS, _ERR_STATUS_0, _HDR_RAM_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RX_SYS_HDR_RAM_ECC_LIMIT_ERR, "HDR RAM ECC Limit Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_RX_SYS, _ERR_STATUS_0, _DAT0_RAM_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RX_SYS_DAT0_RAM_ECC_DBE_ERR, "DAT0 RAM ECC DBE Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_RX_SYS, _ERR_STATUS_0, _DAT0_RAM_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RX_SYS_DAT0_RAM_ECC_LIMIT_ERR, "DAT0 RAM ECC Limit Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_RX_SYS, _ERR_STATUS_0, _DAT1_RAM_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RX_SYS_DAT1_RAM_ECC_DBE_ERR, "DAT1 RAM ECC DBE Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_RX_SYS, _ERR_STATUS_0, _DAT1_RAM_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RX_SYS_DAT1_RAM_ECC_LIMIT_ERR, "DAT1 RAM ECC Limit Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + if (report.raw_first & report.mask) + { + NVSWITCH_LINK_WR32_LS10(device, link, NVLTLC, _NVLTLC_RX_SYS, _ERR_FIRST_0, + report.raw_first & report.mask); + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + // Disable interrupts that have occurred after fatal error. + if (device->link[link].fatal_error_occurred) + { + NVSWITCH_LINK_WR32_LS10(device, link, NVLTLC, _NVLTLC_RX_SYS, _ERR_FATAL_REPORT_EN_0, + report.raw_enable ^ pending); + } + + NVSWITCH_LINK_WR32_LS10(device, link, NVLTLC, _NVLTLC_RX_SYS, _ERR_STATUS_0, pending); + + if (unhandled != 0) + { + NVSWITCH_PRINT(device, WARN, + "%s: Unhandled NVLTLC_RX_SYS interrupts, link: %d pending: 0x%x enabled: 0x%x.\n", + __FUNCTION__, link, pending, report.raw_enable); + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_nvswitch_service_nvltlc_tx_lnk_fatal_0_ls10 +( + nvswitch_device *device, + NvU32 nvlipt_instance, + NvU32 link +) +{ + NvU32 pending, bit, unhandled; + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + + report.raw_pending = NVSWITCH_LINK_RD32_LS10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_STATUS_0); + report.raw_enable = NVSWITCH_LINK_RD32_LS10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_FATAL_REPORT_EN_0); + report.mask = report.raw_enable; + pending = report.raw_pending & report.mask; + + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + report.raw_first = NVSWITCH_LINK_RD32_LS10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_FIRST_0); + + bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_0, _TXDLCREDITPARITYERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_TXDLCREDITPARITYERR, "TX DL Credit Parity Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_0, _CREQ_RAM_HDR_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_TX_LNK_CREQ_RAM_HDR_ECC_DBE_ERR, "CREQ RAM HDR ECC DBE Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_0, _RSP_RAM_HDR_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_TX_LNK_RSP_RAM_HDR_ECC_DBE_ERR, "Response RAM HDR ECC DBE Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_0, _COM_RAM_HDR_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_TX_LNK_COM_RAM_HDR_ECC_DBE_ERR, "COM RAM HDR ECC DBE Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_0, _RSP1_RAM_HDR_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_TX_LNK_RSP1_RAM_HDR_ECC_DBE_ERR, "RSP1 RAM HDR ECC DBE Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_0, _RSP1_RAM_DAT_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_TX_LNK_RSP1_RAM_DAT_ECC_DBE_ERR, "RSP1 RAM DAT ECC DBE Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + // Disable interrupts that have occurred after fatal error. + if (device->link[link].fatal_error_occurred) + { + NVSWITCH_LINK_WR32_LS10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_FATAL_REPORT_EN_0, + report.raw_enable ^ pending); + } + + if (report.raw_first & report.mask) + { + NVSWITCH_LINK_WR32_LS10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_FIRST_0, + report.raw_first & report.mask); + } + NVSWITCH_LINK_WR32_LS10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_STATUS_0, pending); + + if (unhandled != 0) + { + NVSWITCH_PRINT(device, WARN, + "%s: Unhandled NVLTLC_TX_LNK _0 interrupts, link: %d pending: 0x%x enabled: 0x%x.\n", + __FUNCTION__, link, pending, report.raw_enable); + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_nvswitch_service_nvltlc_rx_lnk_fatal_0_ls10 +( + nvswitch_device *device, + NvU32 nvlipt_instance, + NvU32 link +) +{ + NvU32 pending, bit, unhandled; + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + + report.raw_pending = NVSWITCH_LINK_RD32_LS10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_STATUS_0); + report.raw_enable = NVSWITCH_LINK_RD32_LS10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_FATAL_REPORT_EN_0); + report.mask = report.raw_enable; + pending = report.raw_pending & report.mask; + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + report.raw_first = NVSWITCH_LINK_RD32_LS10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_FIRST_0); + + bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RXDLHDRPARITYERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RXDLHDRPARITYERR, "RX DL HDR Parity Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RXDLDATAPARITYERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RXDLDATAPARITYERR, "RX DL Data Parity Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RXDLCTRLPARITYERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RXDLCTRLPARITYERR, "RX DL Ctrl Parity Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RXPKTLENERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RXPKTLENERR, "RX Packet Length Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RSVCACHEATTRPROBEREQERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RSVCACHEATTRPROBEREQERR, "RSV Packet Status Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RSVCACHEATTRPROBERSPERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RSVCACHEATTRPROBERSPERR, "RSV CacheAttr Probe Rsp Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _DATLENGTRMWREQMAXERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_DATLENGTRMWREQMAXERR, "Data Length RMW Req Max Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _DATLENLTATRRSPMINERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_DATLENLTATRRSPMINERR, "Data Len Lt ATR RSP Min Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _INVALIDCACHEATTRPOERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_INVALIDCACHEATTRPOERR, "Invalid Cache Attr PO Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RXRSPSTATUS_HW_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RX_LNK_RXRSPSTATUS_HW_ERR, "RX Rsp Status HW Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RXRSPSTATUS_UR_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RX_LNK_RXRSPSTATUS_UR_ERR, "RX Rsp Status UR Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _INVALID_COLLAPSED_RESPONSE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RX_LNK_INVALID_COLLAPSED_RESPONSE_ERR, "Invalid Collapsed Response Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + // Disable interrupts that have occurred after fatal error. + if (device->link[link].fatal_error_occurred) + { + NVSWITCH_LINK_WR32_LS10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_FATAL_REPORT_EN_0, + report.raw_enable ^ pending); + } + + if (report.raw_first & report.mask) + { + NVSWITCH_LINK_WR32_LS10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_FIRST_0, + report.raw_first & report.mask); + } + NVSWITCH_LINK_WR32_LS10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_STATUS_0, pending); + + if (unhandled != 0) + { + NVSWITCH_PRINT(device, WARN, + "%s: Unhandled NVLTLC_RX_LNK _0 interrupts, link: %d pending: 0x%x enabled: 0x%x.\n", + __FUNCTION__, link, pending, report.raw_enable); + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_nvswitch_service_nvltlc_rx_lnk_fatal_1_ls10 +( + nvswitch_device *device, + NvU32 nvlipt_instance, + NvU32 link +) +{ + NvU32 pending, bit, unhandled; + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + + report.raw_pending = NVSWITCH_LINK_RD32_LS10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_STATUS_1); + report.raw_enable = NVSWITCH_LINK_RD32_LS10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_FATAL_REPORT_EN_1); + report.mask = report.raw_enable; + pending = report.raw_pending & report.mask; + + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + report.raw_first = NVSWITCH_LINK_RD32_LS10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_FIRST_1); + + bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_1, _RXHDROVFERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RXHDROVFERR, "RX HDR OVF Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_1, _RXDATAOVFERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RXDATAOVFERR, "RX Data OVF Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_1, _STOMPDETERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_STOMPDETERR, "Stomp Det Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_1, _RXPOISONERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RXPOISONERR, "RX Poison Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + // Disable interrupts that have occurred after fatal error. + if (device->link[link].fatal_error_occurred) + { + NVSWITCH_LINK_WR32_LS10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_FATAL_REPORT_EN_1, + report.raw_enable ^ pending); + } + + if (report.raw_first & report.mask) + { + NVSWITCH_LINK_WR32_LS10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_FIRST_1, + report.raw_first & report.mask); + } + NVSWITCH_LINK_WR32_LS10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_STATUS_1, pending); + + if (unhandled != 0) + { + NVSWITCH_PRINT(device, WARN, + "%s: Unhandled NVLTLC_RX_LNK _1 interrupts, link: %d pending: 0x%x enabled: 0x%x.\n", + __FUNCTION__, link, pending, report.raw_enable); + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +static NvBool +_nvswitch_is_ncisoc_clock_off_ls10 +( + nvswitch_device *device, + nvlink_link *link +) +{ + NvU32 clkStatus; + clkStatus = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, + NVLIPT_LNK, _NVLIPT_LNK, _CTRL_CLK_CTRL); + if(FLD_TEST_DRF(_NVLIPT_LNK, _CTRL_CLK_CTRL, _NCISOCCLK_STS, _OFF, clkStatus)) + { + return NV_TRUE; + } + return NV_FALSE; +} + +NvlStatus +_nvswitch_service_nvltlc_fatal_ls10 +( + nvswitch_device *device, + NvU32 nvlipt_instance +) +{ + NvU64 enabledLinkMask, localLinkMask, localEnabledLinkMask; + NvU32 i; + nvlink_link *link; + NvlStatus status = -NVL_MORE_PROCESSING_REQUIRED; + + enabledLinkMask = nvswitch_get_enabled_link_mask(device); + localLinkMask = NVSWITCH_NVLIPT_GET_LOCAL_LINK_MASK64_LS10(nvlipt_instance); + localEnabledLinkMask = enabledLinkMask & localLinkMask; + + FOR_EACH_INDEX_IN_MASK(64, i, localEnabledLinkMask) + { + link = nvswitch_get_link(device, i); + if (link == NULL) + { + // An interrupt on an invalid link should never occur + NVSWITCH_ASSERT(link != NULL); + continue; + } + + if (NVSWITCH_GET_LINK_ENG_INST(device, i, NVLIPT) != nvlipt_instance) + { + NVSWITCH_ASSERT(0); + break; + } + + // + // If link is in reset or NCISOC clock is off then + // don't need to check the link for NVLTLC errors + // as the IP's registers are off + // + if (nvswitch_is_link_in_reset(device, link) || + _nvswitch_is_ncisoc_clock_off_ls10(device, link)) + { + continue; + } + + if (_nvswitch_service_nvltlc_tx_sys_fatal_ls10(device, nvlipt_instance, i) == NVL_SUCCESS) + { + status = NVL_SUCCESS; + } + + if (_nvswitch_service_nvltlc_rx_sys_fatal_ls10(device, nvlipt_instance, i) == NVL_SUCCESS) + { + status = NVL_SUCCESS; + } + + if (_nvswitch_service_nvltlc_tx_lnk_fatal_0_ls10(device, nvlipt_instance, i) == NVL_SUCCESS) + { + status = NVL_SUCCESS; + } + + if (_nvswitch_service_nvltlc_rx_lnk_fatal_0_ls10(device, nvlipt_instance, i) == NVL_SUCCESS) + { + status = NVL_SUCCESS; + } + + if (_nvswitch_service_nvltlc_rx_lnk_fatal_1_ls10(device, nvlipt_instance, i) == NVL_SUCCESS) + { + status = NVL_SUCCESS; + } + } + FOR_EACH_INDEX_IN_MASK_END; + + return status; +} + +static NvlStatus +_nvswitch_service_nvlipt_common_fatal_ls10 +( + nvswitch_device *device, + NvU32 instance +) +{ + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + NvU32 pending, bit, contain, unhandled; + NvU32 link, local_link_idx; + + report.raw_pending = NVSWITCH_ENG_RD32(device, NVLIPT, , instance, _NVLIPT_COMMON, _ERR_STATUS_0); + report.raw_enable = NVSWITCH_ENG_RD32(device, NVLIPT, , instance, _NVLIPT_COMMON, _ERR_FATAL_REPORT_EN_0); + report.mask = report.raw_enable & (DRF_NUM(_NVLIPT_COMMON, _ERR_STATUS_0, _CLKCTL_ILLEGAL_REQUEST, 1)); + + pending = report.raw_pending & report.mask; + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + report.raw_first = NVSWITCH_ENG_RD32(device, NVLIPT, , instance, _NVLIPT_COMMON, _ERR_FIRST_0); + contain = NVSWITCH_ENG_RD32(device, NVLIPT, , instance, _NVLIPT_COMMON, _ERR_CONTAIN_EN_0); + + bit = DRF_NUM(_NVLIPT_COMMON, _ERR_STATUS_0, _CLKCTL_ILLEGAL_REQUEST, 1); + if (nvswitch_test_flags(pending, bit)) + { + for (local_link_idx = 0; local_link_idx < NVSWITCH_LINKS_PER_NVLIPT_LS10; local_link_idx++) + { + link = (instance * NVSWITCH_LINKS_PER_NVLIPT_LS10) + local_link_idx; + if (nvswitch_is_link_valid(device, link)) + { + NVSWITCH_REPORT_CONTAIN(_HW_NVLIPT_CLKCTL_ILLEGAL_REQUEST, "CLKCTL_ILLEGAL_REQUEST", NV_FALSE); + } + } + + nvswitch_clear_flags(&unhandled, bit); + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + // Disable interrupts that have occurred after fatal error. + for (local_link_idx = 0; local_link_idx < NVSWITCH_LINKS_PER_NVLIPT_LS10; local_link_idx++) + { + link = (instance * NVSWITCH_LINKS_PER_NVLIPT_LS10) + local_link_idx; + if (nvswitch_is_link_valid(device, link) && + (device->link[link].fatal_error_occurred)) + { + NVSWITCH_ENG_WR32(device, NVLIPT, , instance, _NVLIPT_COMMON, _ERR_FATAL_REPORT_EN_0, + report.raw_enable ^ pending); + break; + } + } + + // clear the interrupts + if (report.raw_first & report.mask) + { + NVSWITCH_ENG_WR32(device, NVLIPT, , instance, _NVLIPT_COMMON, _ERR_FIRST_0, + report.raw_first & report.mask); + } + NVSWITCH_ENG_WR32(device, NVLIPT, , instance, _NVLIPT_COMMON, _ERR_STATUS_0, pending); + + if (unhandled != 0) + { + NVSWITCH_PRINT(device, WARN, + "%s: Unhandled NVLIPT_COMMON FATAL interrupts, pending: 0x%x enabled: 0x%x.\n", + __FUNCTION__, pending, report.raw_enable); + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_nvswitch_service_nxbar_tile_ls10 +( + nvswitch_device *device, + NvU32 tile +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NvU32 pending, bit, unhandled; + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + NvU32 link = tile; + + report.raw_pending = NVSWITCH_TILE_RD32(device, tile, _NXBAR_TILE, _ERR_STATUS); + report.raw_enable = NVSWITCH_TILE_RD32(device, tile, _NXBAR_TILE, _ERR_FATAL_INTR_EN); + report.mask = chip_device->intr_mask.tile.fatal; + pending = report.raw_pending & report.mask; + + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + report.raw_first = NVSWITCH_TILE_RD32(device, tile, _NXBAR_TILE, _ERR_FIRST); + + bit = DRF_NUM(_NXBAR_TILE, _ERR_STATUS, _INGRESS_BUFFER_OVERFLOW, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NXBAR_TILE_INGRESS_BUFFER_OVERFLOW, "ingress SRC-VC buffer overflow", NV_TRUE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NXBAR_TILE, _ERR_STATUS, _INGRESS_BUFFER_UNDERFLOW, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NXBAR_TILE_INGRESS_BUFFER_UNDERFLOW, "ingress SRC-VC buffer underflow", NV_TRUE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NXBAR_TILE, _ERR_STATUS, _EGRESS_CREDIT_OVERFLOW, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NXBAR_TILE_EGRESS_CREDIT_OVERFLOW, "egress DST-VC credit overflow", NV_TRUE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NXBAR_TILE, _ERR_STATUS, _EGRESS_CREDIT_UNDERFLOW, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NXBAR_TILE_EGRESS_CREDIT_UNDERFLOW, "egress DST-VC credit underflow", NV_TRUE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NXBAR_TILE, _ERR_STATUS, _INGRESS_NON_BURSTY_PKT, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NXBAR_TILE_INGRESS_NON_BURSTY_PKT, "ingress packet burst error", NV_TRUE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NXBAR_TILE, _ERR_STATUS, _INGRESS_NON_STICKY_PKT, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NXBAR_TILE_INGRESS_NON_STICKY_PKT, "ingress packet sticky error", NV_TRUE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NXBAR_TILE, _ERR_STATUS, _INGRESS_BURST_GT_9_DATA_VC, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NXBAR_TILE_INGRESS_BURST_GT_9_DATA_VC, "possible bubbles at ingress", NV_TRUE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NXBAR_TILE, _ERR_STATUS, _INGRESS_PKT_INVALID_DST, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NXBAR_TILE_INGRESS_PKT_INVALID_DST, "ingress packet invalid dst error", NV_TRUE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NXBAR_TILE, _ERR_STATUS, _INGRESS_PKT_PARITY_ERROR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NXBAR_TILE_INGRESS_PKT_PARITY_ERROR, "ingress packet parity error", NV_TRUE); + nvswitch_clear_flags(&unhandled, bit); + } + + if (report.raw_first & report.mask) + { + NVSWITCH_TILE_WR32(device, tile, _NXBAR_TILE, _ERR_FIRST, + report.raw_first & report.mask); + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + // Disable interrupts that have occurred after fatal error. + // This helps prevent an interrupt storm if HW keeps triggering unnecessary stream of interrupts. + NVSWITCH_TILE_WR32(device, tile, _NXBAR_TILE, _ERR_FATAL_INTR_EN, + report.raw_enable ^ pending); + + NVSWITCH_TILE_WR32(device, link, _NXBAR_TILE, _ERR_STATUS, pending); + + if (unhandled != 0) + { + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_nvswitch_service_nxbar_tileout_ls10 +( + nvswitch_device *device, + NvU32 tileout +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NvU32 pending, bit, unhandled; + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + NvU32 link = tileout; + + report.raw_pending = NVSWITCH_TILEOUT_RD32(device, tileout, _NXBAR_TILEOUT, _ERR_STATUS); + report.raw_enable = NVSWITCH_TILEOUT_RD32(device, tileout, _NXBAR_TILEOUT, _ERR_FATAL_INTR_EN); + report.mask = chip_device->intr_mask.tileout.fatal; + pending = report.raw_pending & report.mask; + + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + report.raw_first = NVSWITCH_TILEOUT_RD32(device, tileout, _NXBAR_TILEOUT, _ERR_FIRST); + + bit = DRF_NUM(_NXBAR_TILEOUT, _ERR_STATUS, _INGRESS_BUFFER_OVERFLOW, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NXBAR_TILEOUT_INGRESS_BUFFER_OVERFLOW, "ingress SRC-VC buffer overflow", NV_TRUE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NXBAR_TILEOUT, _ERR_STATUS, _INGRESS_BUFFER_UNDERFLOW, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NXBAR_TILEOUT_INGRESS_BUFFER_UNDERFLOW, "ingress SRC-VC buffer underflow", NV_TRUE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NXBAR_TILEOUT, _ERR_STATUS, _EGRESS_CREDIT_OVERFLOW, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NXBAR_TILEOUT_EGRESS_CREDIT_OVERFLOW, "egress DST-VC credit overflow", NV_TRUE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NXBAR_TILEOUT, _ERR_STATUS, _EGRESS_CREDIT_UNDERFLOW, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NXBAR_TILEOUT_EGRESS_CREDIT_UNDERFLOW, "egress DST-VC credit underflow", NV_TRUE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NXBAR_TILEOUT, _ERR_STATUS, _INGRESS_NON_BURSTY_PKT, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NXBAR_TILEOUT_INGRESS_NON_BURSTY_PKT, "ingress packet burst error", NV_TRUE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NXBAR_TILEOUT, _ERR_STATUS, _INGRESS_NON_STICKY_PKT, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NXBAR_TILEOUT_INGRESS_NON_STICKY_PKT, "ingress packet sticky error", NV_TRUE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NXBAR_TILEOUT, _ERR_STATUS, _INGRESS_BURST_GT_9_DATA_VC, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NXBAR_TILEOUT_INGRESS_BURST_GT_9_DATA_VC, "possible bubbles at ingress", NV_TRUE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NXBAR_TILEOUT, _ERR_STATUS, _EGRESS_CDT_PARITY_ERROR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NXBAR_TILEOUT_EGRESS_CDT_PARITY_ERROR, "ingress credit parity error", NV_TRUE); + nvswitch_clear_flags(&unhandled, bit); + } + + if (report.raw_first & report.mask) + { + NVSWITCH_TILEOUT_WR32(device, tileout, _NXBAR_TILEOUT, _ERR_FIRST, + report.raw_first & report.mask); + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + // Disable interrupts that have occurred after fatal error. + // This helps prevent an interrupt storm if HW keeps triggering unnecessary stream of interrupts. + NVSWITCH_TILEOUT_WR32(device, tileout, _NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, + report.raw_enable ^ pending); + + NVSWITCH_TILEOUT_WR32(device, tileout, _NXBAR_TILEOUT, _ERR_STATUS, pending); + + if (unhandled != 0) + { + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_nvswitch_service_nxbar_fatal_ls10 +( + nvswitch_device *device, + NvU32 nxbar +) +{ + NvU32 pending, bit, unhandled; + NvU32 tile_idx; + NvU32 tile, tileout; + + pending = NVSWITCH_ENG_RD32(device, NXBAR, , nxbar, _NXBAR, _TCP_ERROR_STATUS); + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + + for (tile = 0; tile < NUM_NXBAR_TILES_PER_TC_LS10; tile++) + { + bit = DRF_NUM(_NXBAR, _TCP_ERROR_STATUS, _TILE0, 1) << tile; + if (nvswitch_test_flags(pending, bit)) + { + tile_idx = TILE_INDEX_LS10(device, nxbar, tile); + if (NVSWITCH_ENG_VALID_LS10(device, TILE, tile_idx)) + { + if (_nvswitch_service_nxbar_tile_ls10(device, tile_idx) == NVL_SUCCESS) + { + nvswitch_clear_flags(&unhandled, bit); + } + } + } + } + + for (tileout = 0; tileout < NUM_NXBAR_TILEOUTS_PER_TC_LS10; tileout++) + { + bit = DRF_NUM(_NXBAR, _TCP_ERROR_STATUS, _TILEOUT0, 1) << tileout; + if (nvswitch_test_flags(pending, bit)) + { + tile_idx = TILE_INDEX_LS10(device, nxbar, tileout); + if (NVSWITCH_ENG_VALID_LS10(device, TILEOUT, tile_idx)) + { + if (_nvswitch_service_nxbar_tileout_ls10(device, tile_idx) == NVL_SUCCESS) + { + nvswitch_clear_flags(&unhandled, bit); + } + } + } + } + + // TODO: Perform hot_reset to recover NXBAR + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + + if (unhandled != 0) + { + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +static void +_nvswitch_emit_link_errors_nvldl_fatal_link_ls10 +( + nvswitch_device *device, + NvU32 nvlipt_instance, + NvU32 link +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + NvU32 pending, bit; + + // Only enabled link errors are deffered + pending = chip_device->deferredLinkErrors[link].fatalIntrMask.dl; + report.raw_pending = pending; + report.raw_enable = pending; + report.mask = report.raw_enable; + + bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_UP, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_DLPL_LTSSM_FAULT_UP, "LTSSM Fault Up", NV_FALSE); + } +} + +static void +_nvswitch_emit_link_errors_nvldl_nonfatal_link_ls10 +( + nvswitch_device *device, + NvU32 link +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + NvU32 pending, bit; + + // Only enabled link errors are deffered + pending = chip_device->deferredLinkErrors[link].nonFatalIntrMask.dl; + report.raw_pending = pending; + report.raw_enable = pending; + report.mask = report.raw_enable; + + bit = DRF_NUM(_NVLDL_TOP, _INTR, _RX_SHORT_ERROR_RATE, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_DLPL_RX_SHORT_ERROR_RATE, "RX Short Error Rate"); + } +} + +static void +_nvswitch_emit_link_errors_nvltlc_rx_lnk_nonfatal_1_ls10 +( + nvswitch_device *device, + NvU32 nvlipt_instance, + NvU32 link +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + NvU32 pending, bit, injected; + + // Only enabled link errors are deffered + pending = chip_device->deferredLinkErrors[link].nonFatalIntrMask.tlcRx1; + injected = chip_device->deferredLinkErrors[link].nonFatalIntrMask.tlcRx1Injected; + report.raw_pending = pending; + report.raw_enable = pending; + report.mask = report.raw_enable; + + + bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_1, _HEARTBEAT_TIMEOUT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_RX_LNK_AN1_HEARTBEAT_TIMEOUT_ERR, "AN1 Heartbeat Timeout Error"); + + if (FLD_TEST_DRF_NUM(_NVLTLC_RX_LNK, _ERR_REPORT_INJECT_1, _HEARTBEAT_TIMEOUT_ERR, 0x0, injected)) + { + } + } +} + +static void +_nvswitch_emit_link_errors_nvlipt_lnk_nonfatal_ls10 +( + nvswitch_device *device, + NvU32 nvlipt_instance, + NvU32 link +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + NvU32 pending, bit; + + // Only enabled link errors are deffered + pending = chip_device->deferredLinkErrors[link].nonFatalIntrMask.liptLnk; + report.raw_pending = pending; + report.raw_enable = pending; + report.mask = report.raw_enable; + + bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _FAILEDMINIONREQUEST, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NVLIPT_LNK_FAILEDMINIONREQUEST, "_FAILEDMINIONREQUEST"); + + } +} + +static void +_nvswitch_emit_deferred_link_errors_ls10 +( + nvswitch_device *device, + NvU32 nvlipt_instance, + NvU32 link +) +{ + _nvswitch_emit_link_errors_nvldl_fatal_link_ls10(device, nvlipt_instance, link); + _nvswitch_emit_link_errors_nvldl_nonfatal_link_ls10(device, link); + _nvswitch_emit_link_errors_nvltlc_rx_lnk_nonfatal_1_ls10(device, nvlipt_instance, link); + _nvswitch_emit_link_errors_nvlipt_lnk_nonfatal_ls10(device, nvlipt_instance, link); +} + +static void +_nvswitch_clear_deferred_link_errors_ls10 +( + nvswitch_device *device, + NvU32 link +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NVLINK_LINK_ERROR_REPORTING *pLinkErrors; + + pLinkErrors = &chip_device->deferredLinkErrors[link]; + + nvswitch_os_memset(pLinkErrors, 0, sizeof(NVLINK_LINK_ERROR_REPORTING)); +} + +static void +_nvswitch_deferred_link_state_check_ls10 +( + nvswitch_device *device, + void *fn_args +) +{ + NVSWITCH_DEFERRED_ERROR_REPORTING_ARGS *pErrorReportParams = + (NVSWITCH_DEFERRED_ERROR_REPORTING_ARGS*)fn_args; + NvU32 nvlipt_instance = pErrorReportParams->nvlipt_instance; + NvU32 link = pErrorReportParams->link; + ls10_device *chip_device; + nvlink_link *pLink; + NvU64 linkState; + + chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + pLink = nvswitch_get_link(device, pErrorReportParams->link); + + if ((pLink == NULL) || + (device->hal.nvswitch_corelib_get_dl_link_mode(pLink, &linkState) != NVL_SUCCESS) || + ((linkState != NVLINK_LINKSTATE_HS) && (linkState != NVLINK_LINKSTATE_SLEEP))) + { + _nvswitch_emit_deferred_link_errors_ls10(device, nvlipt_instance, link); + } + + _nvswitch_clear_deferred_link_errors_ls10(device, link); + nvswitch_os_free(pErrorReportParams); + chip_device->deferredLinkErrors[link].bLinkStateCallBackEnabled = NV_FALSE; +} + +static void +_nvswitch_create_deferred_link_state_check_task_ls10 +( + nvswitch_device *device, + NvU32 nvlipt_instance, + NvU32 link +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NVSWITCH_DEFERRED_ERROR_REPORTING_ARGS *pErrorReportParams; + NvlStatus status; + + if (chip_device->deferredLinkErrors[link].bLinkStateCallBackEnabled) + { + return; + } + + status = NVL_ERR_GENERIC; + pErrorReportParams = nvswitch_os_malloc(sizeof(NVSWITCH_DEFERRED_ERROR_REPORTING_ARGS)); + if(pErrorReportParams != NULL) + { + pErrorReportParams->nvlipt_instance = nvlipt_instance; + pErrorReportParams->link = link; + + status = nvswitch_task_create_args(device, (void*)pErrorReportParams, + &_nvswitch_deferred_link_state_check_ls10, + NVSWITCH_DEFERRED_LINK_STATE_CHECK_INTERVAL_NS, + NVSWITCH_TASK_TYPE_FLAGS_RUN_ONCE | + NVSWITCH_TASK_TYPE_FLAGS_VOID_PTR_ARGS); + } + + if (status == NVL_SUCCESS) + { + chip_device->deferredLinkErrors[link].bLinkStateCallBackEnabled = NV_TRUE; + } + else + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to allocate memory. Cannot defer link state check.\n", + __FUNCTION__); + _nvswitch_emit_deferred_link_errors_ls10(device, nvlipt_instance, link); + _nvswitch_clear_deferred_link_errors_ls10(device, link); + nvswitch_os_free(pErrorReportParams); + } +} + +static void +_nvswitch_deferred_link_errors_check_ls10 +( + nvswitch_device *device, + void *fn_args +) +{ + NVSWITCH_DEFERRED_ERROR_REPORTING_ARGS *pErrorReportParams = + (NVSWITCH_DEFERRED_ERROR_REPORTING_ARGS*)fn_args; + NvU32 nvlipt_instance = pErrorReportParams->nvlipt_instance; + NvU32 link = pErrorReportParams->link; + ls10_device *chip_device; + NvU32 pending, bit; + + chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + + pending = chip_device->deferredLinkErrors[link].fatalIntrMask.dl; + bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_UP, 1); + if (nvswitch_test_flags(pending, bit)) + { + _nvswitch_create_deferred_link_state_check_task_ls10(device, nvlipt_instance, link); + } + else + { + _nvswitch_emit_deferred_link_errors_ls10(device, nvlipt_instance, link); + _nvswitch_clear_deferred_link_errors_ls10(device, link); + } + + nvswitch_os_free(pErrorReportParams); + chip_device->deferredLinkErrors[link].bLinkErrorsCallBackEnabled = NV_FALSE; +} + +static void +_nvswitch_create_deferred_link_errors_task_ls10 +( + nvswitch_device *device, + NvU32 nvlipt_instance, + NvU32 link +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NVSWITCH_DEFERRED_ERROR_REPORTING_ARGS *pErrorReportParams; + NvlStatus status; + + if (chip_device->deferredLinkErrors[link].bLinkErrorsCallBackEnabled) + { + return; + } + + status = NVL_ERR_GENERIC; + pErrorReportParams = nvswitch_os_malloc(sizeof(NVSWITCH_DEFERRED_ERROR_REPORTING_ARGS)); + if(pErrorReportParams != NULL) + { + pErrorReportParams->nvlipt_instance = nvlipt_instance; + pErrorReportParams->link = link; + + status = nvswitch_task_create_args(device, (void*)pErrorReportParams, + &_nvswitch_deferred_link_errors_check_ls10, + NVSWITCH_DEFERRED_FAULT_UP_CHECK_INTERVAL_NS, + NVSWITCH_TASK_TYPE_FLAGS_RUN_ONCE | + NVSWITCH_TASK_TYPE_FLAGS_VOID_PTR_ARGS); + } + + if (status == NVL_SUCCESS) + { + chip_device->deferredLinkErrors[link].bLinkErrorsCallBackEnabled = NV_TRUE; + } + else + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to create task. Cannot defer link error check.\n", + __FUNCTION__); + _nvswitch_emit_deferred_link_errors_ls10(device, nvlipt_instance, link); + _nvswitch_clear_deferred_link_errors_ls10(device, link); + nvswitch_os_free(pErrorReportParams); + } +} + +static NvlStatus +_nvswitch_service_nvldl_nonfatal_link_ls10 +( + nvswitch_device *device, + NvU32 nvlipt_instance, + NvU32 link +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NvU32 pending, bit, unhandled; + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + + report.raw_pending = NVSWITCH_LINK_RD32(device, link, NVLDL, _NVLDL_TOP, _INTR); + report.raw_enable = NVSWITCH_LINK_RD32(device, link, NVLDL, _NVLDL_TOP, _INTR_NONSTALL_EN); + report.mask = report.raw_enable; + pending = report.raw_pending & report.mask; + + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + + bit = DRF_NUM(_NVLDL_TOP, _INTR, _TX_REPLAY, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_DLPL_TX_REPLAY, "TX Replay Error"); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLDL_TOP, _INTR, _TX_RECOVERY_SHORT, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_DLPL_TX_RECOVERY_SHORT, "TX Recovery Short"); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLDL_TOP, _INTR, _RX_SHORT_ERROR_RATE, 1); + if (nvswitch_test_flags(pending, bit)) + { + chip_device->deferredLinkErrors[link].nonFatalIntrMask.dl |= bit; + _nvswitch_create_deferred_link_errors_task_ls10(device, nvlipt_instance, link); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLDL_TOP, _INTR, _RX_LONG_ERROR_RATE, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_DLPL_RX_LONG_ERROR_RATE, "RX Long Error Rate"); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLDL_TOP, _INTR, _RX_ILA_TRIGGER, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_DLPL_RX_ILA_TRIGGER, "RX ILA Trigger"); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLDL_TOP, _INTR, _RX_CRC_COUNTER, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_DLPL_RX_CRC_COUNTER, "RX CRC Counter"); + nvswitch_clear_flags(&unhandled, bit); + + // + // Mask CRC counter after first occurrance - otherwise, this interrupt + // will continue to fire once the CRC counter has hit the threshold + // See Bug 3341528 + // + report.raw_enable = report.raw_enable & (~bit); + NVSWITCH_LINK_WR32(device, link, NVLDL, _NVLDL_TOP, _INTR_NONSTALL_EN, + report.raw_enable); + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + NVSWITCH_LINK_WR32(device, link, NVLDL, _NVLDL_TOP, _INTR, pending); + + if (unhandled != 0) + { + NVSWITCH_PRINT(device, WARN, + "%s: Unhandled NVLDL nonfatal interrupts, link: %d pending: 0x%x enabled: 0x%x.\n", + __FUNCTION__, link, pending, report.raw_enable); + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_nvswitch_service_nvldl_nonfatal_ls10 +( + nvswitch_device *device, + NvU32 nvlipt_instance +) +{ + NvU64 enabledLinkMask, localLinkMask, localEnabledLinkMask; + NvU32 i; + nvlink_link *link; + NvlStatus status; + NvlStatus return_status = -NVL_NOT_FOUND; + + enabledLinkMask = nvswitch_get_enabled_link_mask(device); + localLinkMask = NVSWITCH_NVLIPT_GET_LOCAL_LINK_MASK64_LS10(nvlipt_instance); + localEnabledLinkMask = enabledLinkMask & localLinkMask; + + FOR_EACH_INDEX_IN_MASK(64, i, localEnabledLinkMask) + { + link = nvswitch_get_link(device, i); + if (link == NULL) + { + // An interrupt on an invalid link should never occur + NVSWITCH_ASSERT(link != NULL); + continue; + } + + if (NVSWITCH_GET_LINK_ENG_INST(device, i, NVLIPT) != nvlipt_instance) + { + NVSWITCH_ASSERT(0); + break; + } + + if (nvswitch_is_link_in_reset(device, link)) + { + continue; + } + + status = _nvswitch_service_nvldl_nonfatal_link_ls10(device, nvlipt_instance, i); + if (status != NVL_SUCCESS) + { + return_status = status; + } + } + FOR_EACH_INDEX_IN_MASK_END; + + return return_status; +} + +static NvlStatus +_nvswitch_service_nvltlc_rx_lnk_nonfatal_0_ls10 +( + nvswitch_device *device, + NvU32 nvlipt_instance, + NvU32 link +) +{ + NvU32 pending, bit, unhandled; + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + + report.raw_pending = NVSWITCH_LINK_RD32(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_STATUS_0); + report.raw_enable = NVSWITCH_LINK_RD32(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_NON_FATAL_REPORT_EN_0); + report.mask = report.raw_enable; + + pending = report.raw_pending & report.mask; + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + report.raw_first = NVSWITCH_LINK_RD32(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_FIRST_0); + + bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RXRSPSTATUS_PRIV_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_RX_LNK_RXRSPSTATUS_PRIV_ERR, "RX Rsp Status PRIV Error"); + nvswitch_clear_flags(&unhandled, bit); + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + if (report.raw_first & report.mask) + { + NVSWITCH_LINK_WR32(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_FIRST_0, + report.raw_first & report.mask); + } + NVSWITCH_LINK_WR32(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_STATUS_0, pending); + + if (unhandled != 0) + { + NVSWITCH_PRINT(device, WARN, + "%s: Unhandled NVLTLC_RX_LNK _0 interrupts, link: %d pending: 0x%x enabled: 0x%x.\n", + __FUNCTION__, link, pending, report.raw_enable); + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_nvswitch_service_nvltlc_tx_lnk_nonfatal_0_ls10 +( + nvswitch_device *device, + NvU32 nvlipt_instance, + NvU32 link +) +{ + NvU32 pending, bit, unhandled; + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + + report.raw_pending = NVSWITCH_LINK_RD32(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_STATUS_0); + report.raw_enable = NVSWITCH_LINK_RD32(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_NON_FATAL_REPORT_EN_0); + report.mask = report.raw_enable; + pending = report.raw_pending & report.mask; + + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + report.raw_first = NVSWITCH_LINK_RD32(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_FIRST_0); + + bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_0, _CREQ_RAM_DAT_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_CREQ_RAM_DAT_ECC_DBE_ERR, "CREQ RAM DAT ECC DBE Error"); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_0, _CREQ_RAM_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_CREQ_RAM_ECC_LIMIT_ERR, "CREQ RAM DAT ECC Limit Error"); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_0, _RSP_RAM_DAT_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_RSP_RAM_DAT_ECC_DBE_ERR, "Response RAM DAT ECC DBE Error"); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_0, _RSP_RAM_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_RSP_RAM_ECC_LIMIT_ERR, "Response RAM ECC Limit Error"); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_0, _COM_RAM_DAT_ECC_DBE_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_COM_RAM_DAT_ECC_DBE_ERR, "COM RAM DAT ECC DBE Error"); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_0, _COM_RAM_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_COM_RAM_ECC_LIMIT_ERR, "COM RAM ECC Limit Error"); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_0, _RSP1_RAM_ECC_LIMIT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_RSP1_RAM_ECC_LIMIT_ERR, "RSP1 RAM ECC Limit Error"); + nvswitch_clear_flags(&unhandled, bit); + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + // Disable interrupts that have occurred after fatal error. + if (device->link[link].fatal_error_occurred) + { + NVSWITCH_LINK_WR32(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_NON_FATAL_REPORT_EN_0, + report.raw_enable ^ pending); + } + + if (report.raw_first & report.mask) + { + NVSWITCH_LINK_WR32(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_FIRST_0, + report.raw_first & report.mask); + } + NVSWITCH_LINK_WR32(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_STATUS_0, pending); + + if (unhandled != 0) + { + NVSWITCH_PRINT(device, WARN, + "%s: Unhandled NVLTLC_TX_LNK _0 interrupts, link: %d pending: 0x%x enabled: 0x%x.\n", + __FUNCTION__, link, pending, report.raw_enable); + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_nvswitch_service_nvltlc_rx_lnk_nonfatal_1_ls10 +( + nvswitch_device *device, + NvU32 nvlipt_instance, + NvU32 link +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NvU32 pending, bit, unhandled, injected; + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + + report.raw_pending = NVSWITCH_LINK_RD32(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_STATUS_1); + report.raw_enable = NVSWITCH_LINK_RD32(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_NON_FATAL_REPORT_EN_1); + report.mask = report.raw_enable; + pending = report.raw_pending & report.mask; + + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + report.raw_first = NVSWITCH_LINK_RD32(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_FIRST_1); + injected = NVSWITCH_LINK_RD32(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_REPORT_INJECT_1); + + bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_1, _HEARTBEAT_TIMEOUT_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + chip_device->deferredLinkErrors[link].nonFatalIntrMask.tlcRx1 |= bit; + chip_device->deferredLinkErrors[link].nonFatalIntrMask.tlcRx1Injected |= injected; + _nvswitch_create_deferred_link_errors_task_ls10(device, nvlipt_instance, link); + + if (FLD_TEST_DRF_NUM(_NVLTLC_RX_LNK, _ERR_REPORT_INJECT_1, _HEARTBEAT_TIMEOUT_ERR, 0x0, injected)) + { + // + // WAR Bug 200627368: Mask off HBTO to avoid a storm + // During the start of reset_and_drain, all links on the GPU + // will go into contain, causing HBTO on other switch links connected + // to that GPU. For the switch side, these interrupts are not fatal, + // but until we get to reset_and_drain for this link, HBTO will continue + // to fire repeatedly. After reset_and_drain, HBTO will be re-enabled + // by MINION after links are trained. + // + report.raw_enable = report.raw_enable & (~bit); + NVSWITCH_LINK_WR32(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_NON_FATAL_REPORT_EN_1, + report.raw_enable); + } + nvswitch_clear_flags(&unhandled, bit); + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + // Disable interrupts that have occurred after fatal error. + if (device->link[link].fatal_error_occurred) + { + NVSWITCH_LINK_WR32(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_NON_FATAL_REPORT_EN_1, + report.raw_enable & (~pending)); + } + + if (report.raw_first & report.mask) + { + NVSWITCH_LINK_WR32(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_FIRST_1, + report.raw_first & report.mask); + } + NVSWITCH_LINK_WR32(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_STATUS_1, pending); + + if (unhandled != 0) + { + NVSWITCH_PRINT(device, WARN, + "%s: Unhandled NVLTLC_RX_LNK _1 interrupts, link: %d pending: 0x%x enabled: 0x%x.\n", + __FUNCTION__, link, pending, report.raw_enable); + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_nvswitch_service_nvltlc_tx_lnk_nonfatal_1_ls10 +( + nvswitch_device *device, + NvU32 nvlipt_instance, + NvU32 link +) +{ + NvU32 pending, bit, unhandled; + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + + report.raw_pending = NVSWITCH_LINK_RD32(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_STATUS_1); + report.raw_enable = NVSWITCH_LINK_RD32(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_NON_FATAL_REPORT_EN_1); + report.mask = report.raw_enable; + pending = report.raw_pending & report.mask; + + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + report.raw_first = NVSWITCH_LINK_RD32(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_FIRST_1); + + bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_1, _TIMEOUT_VC0, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC0, "AN1 Timeout VC0"); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_1, _TIMEOUT_VC1, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC1, "AN1 Timeout VC1"); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_1, _TIMEOUT_VC2, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC2, "AN1 Timeout VC2"); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_1, _TIMEOUT_VC3, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC3, "AN1 Timeout VC3"); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_1, _TIMEOUT_VC4, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC4, "AN1 Timeout VC4"); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_1, _TIMEOUT_VC5, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC5, "AN1 Timeout VC5"); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_1, _TIMEOUT_VC6, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC6, "AN1 Timeout VC6"); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_1, _TIMEOUT_VC7, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC7, "AN1 Timeout VC7"); + nvswitch_clear_flags(&unhandled, bit); + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + // Disable interrupts that have occurred after fatal error. + if (device->link[link].fatal_error_occurred) + { + NVSWITCH_LINK_WR32(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_NON_FATAL_REPORT_EN_1, + report.raw_enable ^ pending); + } + + if (report.raw_first & report.mask) + { + NVSWITCH_LINK_WR32(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_FIRST_1, + report.raw_first & report.mask); + } + NVSWITCH_LINK_WR32(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_STATUS_1, pending); + + if (unhandled != 0) + { + NVSWITCH_PRINT(device, WARN, + "%s: Unhandled NVLTLC_TX_LNK _1 interrupts, link: %d pending: 0x%x enabled: 0x%x.\n", + __FUNCTION__, link, pending, report.raw_enable); + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_nvswitch_service_nvltlc_nonfatal_ls10 +( + nvswitch_device *device, + NvU32 nvlipt_instance +) +{ + NvU64 enabledLinkMask, localLinkMask, localEnabledLinkMask; + NvU32 i; + nvlink_link *link; + NvlStatus status; + NvlStatus return_status = NVL_SUCCESS; + + enabledLinkMask = nvswitch_get_enabled_link_mask(device); + localLinkMask = NVSWITCH_NVLIPT_GET_LOCAL_LINK_MASK64_LS10(nvlipt_instance); + localEnabledLinkMask = enabledLinkMask & localLinkMask; + + FOR_EACH_INDEX_IN_MASK(64, i, localEnabledLinkMask) + { + link = nvswitch_get_link(device, i); + if (link == NULL) + { + // An interrupt on an invalid link should never occur + NVSWITCH_ASSERT(link != NULL); + continue; + } + + if (NVSWITCH_GET_LINK_ENG_INST(device, i, NVLIPT) != nvlipt_instance) + { + NVSWITCH_ASSERT(0); + break; + } + + // + // If link is in reset or NCISOC clock is off then + // don't need to check the link for NVLTLC errors + // as the IP's registers are off + // + if (nvswitch_is_link_in_reset(device, link) || + _nvswitch_is_ncisoc_clock_off_ls10(device, link)) + { + continue; + } + + status = _nvswitch_service_nvltlc_rx_lnk_nonfatal_0_ls10(device, nvlipt_instance, i); + if (status != NVL_SUCCESS) + { + return_status = status; + } + + status = _nvswitch_service_nvltlc_tx_lnk_nonfatal_0_ls10(device, nvlipt_instance, i); + if (status != NVL_SUCCESS) + { + return_status = status; + } + + status = _nvswitch_service_nvltlc_rx_lnk_nonfatal_1_ls10(device, nvlipt_instance, i); + if (status != NVL_SUCCESS) + { + return_status = status; + } + + status = _nvswitch_service_nvltlc_tx_lnk_nonfatal_1_ls10(device, nvlipt_instance, i); + if (status != NVL_SUCCESS) + { + return_status = status; + } + } + FOR_EACH_INDEX_IN_MASK_END; + + return return_status; +} + +static NvlStatus +_nvswitch_service_nvlipt_lnk_status_ls10 +( + nvswitch_device *device, + NvU32 nvlipt_instance, + NvU32 link_id +) +{ + NvU32 pending, enabled, unhandled, bit; + NvU64 mode; + nvlink_link *link; + link = nvswitch_get_link(device, link_id); + + pending = NVSWITCH_LINK_RD32(device, link_id, NVLIPT_LNK, _NVLIPT_LNK, _INTR_STATUS); + enabled = NVSWITCH_LINK_RD32(device, link_id, NVLIPT_LNK, _NVLIPT_LNK, _INTR_INT1_EN); + pending &= enabled; + unhandled = pending; + + bit = DRF_NUM(_NVLIPT_LNK, _INTR_STATUS, _LINKSTATEREQUESTREADYSET, 1); + if (nvswitch_test_flags(pending, bit)) + { + nvswitch_clear_flags(&unhandled, bit); + if(nvswitch_corelib_get_dl_link_mode_ls10(link, &mode) != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: nvlipt_lnk_status: Failed to check link mode! LinkId %d\n", + __FUNCTION__, link_id); + } + else if(mode == NVLINK_LINKSTATE_HS) + { + NVSWITCH_PRINT(device, INFO, "%s: nvlipt_lnk_status: Link is up!. LinkId %d\n", + __FUNCTION__, link_id); + if (nvswitch_lib_notify_client_events(device, + NVSWITCH_DEVICE_EVENT_PORT_UP) != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed to notify PORT_UP event. LinkId %d\n", + __FUNCTION__, link_id); + } + + // + // When a link comes up ensure that we finish off the post-training tasks: + // -- enabling per-link DL interrupts + // -- releasing buffer_ready on the link + // + nvswitch_corelib_training_complete_ls10(link); + nvswitch_init_buffer_ready(device, link, NV_TRUE); + } + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + NVSWITCH_LINK_WR32(device, link_id, NVLIPT_LNK, _NVLIPT_LNK, _INTR_STATUS, pending); + + if (unhandled != 0) + { + NVSWITCH_PRINT(device, WARN, + "%s: Unhandled NVLIPT_LNK STATUS interrupts, pending: 0x%x enabled: 0x%x.\n", + __FUNCTION__, pending, enabled); + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_nvswitch_service_nvlipt_lnk_nonfatal_ls10 +( + nvswitch_device *device, + NvU32 nvlipt_instance, + NvU32 link +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + NvU32 pending, bit, unhandled; + + report.raw_pending = NVSWITCH_LINK_RD32(device, link, NVLIPT_LNK, _NVLIPT_LNK, _ERR_STATUS_0); + report.raw_enable = NVSWITCH_LINK_RD32(device, link, NVLIPT_LNK, _NVLIPT_LNK, _ERR_NON_FATAL_REPORT_EN_0); + report.mask = report.raw_enable; + + pending = report.raw_pending & report.mask; + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + report.raw_first = NVSWITCH_LINK_RD32(device, link, NVLIPT_LNK, _NVLIPT_LNK, _ERR_FIRST_0); + + bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _ILLEGALLINKSTATEREQUEST, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NVLIPT_LNK_ILLEGALLINKSTATEREQUEST, "_HW_NVLIPT_LNK_ILLEGALLINKSTATEREQUEST"); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _FAILEDMINIONREQUEST, 1); + if (nvswitch_test_flags(pending, bit)) + { + chip_device->deferredLinkErrors[link].nonFatalIntrMask.liptLnk |= bit; + _nvswitch_create_deferred_link_errors_task_ls10(device, nvlipt_instance, link); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _RESERVEDREQUESTVALUE, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NVLIPT_LNK_RESERVEDREQUESTVALUE, "_RESERVEDREQUESTVALUE"); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _LINKSTATEWRITEWHILEBUSY, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NVLIPT_LNK_LINKSTATEWRITEWHILEBUSY, "_LINKSTATEWRITEWHILEBUSY"); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _LINK_STATE_REQUEST_TIMEOUT, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NVLIPT_LNK_LINK_STATE_REQUEST_TIMEOUT, "_LINK_STATE_REQUEST_TIMEOUT"); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _WRITE_TO_LOCKED_SYSTEM_REG_ERR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_NONFATAL(_HW_NVLIPT_LNK_WRITE_TO_LOCKED_SYSTEM_REG_ERR, "_WRITE_TO_LOCKED_SYSTEM_REG_ERR"); + nvswitch_clear_flags(&unhandled, bit); + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + if (report.raw_first & report.mask) + { + NVSWITCH_LINK_WR32(device, link, NVLIPT_LNK, _NVLIPT_LNK, _ERR_FIRST_0, + report.raw_first & report.mask); + } + NVSWITCH_LINK_WR32(device, link, NVLIPT_LNK, _NVLIPT_LNK, _ERR_STATUS_0, pending); + + if (unhandled != 0) + { + NVSWITCH_PRINT(device, WARN, + "%s: Unhandled NVLIPT_LNK NON_FATAL interrupts, pending: 0x%x enabled: 0x%x.\n", + __FUNCTION__, pending, report.raw_enable); + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_nvswitch_service_nvlipt_link_nonfatal_ls10 +( + nvswitch_device *device, + NvU32 instance +) +{ + NvU32 i, globalLink, bit, intrLink; + NvU32 interruptingLinks = 0; + NvU32 lnkStatusChangeLinks = 0; + NvlStatus status; + + for (i = 0; i < NVSWITCH_LINKS_PER_NVLIPT_LS10; ++i) + { + globalLink = (instance * NVSWITCH_LINKS_PER_NVLIPT_LS10) + i; + + intrLink = NVSWITCH_LINK_RD32(device, globalLink, NVLIPT_LNK, _NVLIPT_LNK, _ERR_STATUS_0); + + if(intrLink) + { + interruptingLinks |= NVBIT(i); + } + + intrLink = NVSWITCH_LINK_RD32(device, globalLink, NVLIPT_LNK, _NVLIPT_LNK, _INTR_STATUS); + + if(intrLink) + { + lnkStatusChangeLinks |= NVBIT(i); + } + } + + if(lnkStatusChangeLinks) + { + for (i = 0; i < NVSWITCH_LINKS_PER_NVLIPT_LS10; ++i) + { + bit = NVBIT(i); + globalLink = (instance * NVSWITCH_LINKS_PER_NVLIPT_LS10) + i; + if (nvswitch_test_flags(lnkStatusChangeLinks, bit)) + { + if( _nvswitch_service_nvlipt_lnk_status_ls10(device, instance, globalLink) != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, WARN, "%s: Could not process nvlipt link status interrupt. Continuing. LinkId %d\n", + __FUNCTION__, globalLink); + } + } + } + } + + if(interruptingLinks) + { + for (i = 0; i < NVSWITCH_LINKS_PER_NVLIPT_LS10; ++i) + { + bit = NVBIT(i); + globalLink = (instance * NVSWITCH_LINKS_PER_NVLIPT_LS10) + i; + if (nvswitch_test_flags(interruptingLinks, bit)) + { + status = _nvswitch_service_nvlipt_lnk_nonfatal_ls10(device, instance, globalLink); + if (status != NVL_SUCCESS && status != -NVL_NOT_FOUND) + { + return -NVL_MORE_PROCESSING_REQUIRED; + } + } + } + return NVL_SUCCESS; + } + else + { + return -NVL_NOT_FOUND; + } +} + + +NvlStatus +_nvswitch_service_minion_fatal_ls10 +( + nvswitch_device *device, + NvU32 instance +) +{ + NvU32 pending, bit, unhandled, mask; + + pending = NVSWITCH_MINION_RD32_LS10(device, instance, _MINION, _MINION_INTR); + mask = NVSWITCH_MINION_RD32_LS10(device, instance, _MINION, _MINION_INTR_STALL_EN); + + // Don't consider MINION Link interrupts in this handler + mask &= ~(DRF_NUM(_MINION, _MINION_INTR_STALL_EN, _LINK, NV_MINION_MINION_INTR_STALL_EN_LINK_ENABLE_ALL)); + + pending &= mask; + + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + + bit = DRF_NUM(_MINION, _MINION_INTR, _FALCON_STALL, 0x1); + if (nvswitch_test_flags(pending, bit)) + { + if (nvswitch_minion_service_falcon_interrupts_ls10(device, instance) == NVL_SUCCESS) + { + nvswitch_clear_flags(&unhandled, bit); + } + } + + bit = DRF_NUM(_MINION, _MINION_INTR, _NONFATAL, 0x1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_PRINT(device, ERROR, "%s: servicing minion nonfatal interrupt\n", + __FUNCTION__); + NVSWITCH_MINION_WR32_LS10(device, instance, _MINION, _MINION_INTR, bit); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_MINION, _MINION_INTR, _FATAL, 0x1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_PRINT(device, ERROR, "%s: servicing minion fatal interrupt\n", + __FUNCTION__); + NVSWITCH_MINION_WR32_LS10(device, instance, _MINION, _MINION_INTR, bit); + nvswitch_clear_flags(&unhandled, bit); + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + if (unhandled != 0) + { + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_nvswitch_service_nvlw_nonfatal_ls10 +( + nvswitch_device *device, + NvU32 instance +) +{ + NvlStatus status[3]; + + status[0] = _nvswitch_service_nvldl_nonfatal_ls10(device, instance); + status[1] = _nvswitch_service_nvltlc_nonfatal_ls10(device, instance); + status[2] = _nvswitch_service_nvlipt_link_nonfatal_ls10(device, instance); + + if ((status[0] != NVL_SUCCESS) && (status[0] != -NVL_NOT_FOUND) && + (status[1] != NVL_SUCCESS) && (status[1] != -NVL_NOT_FOUND) && + (status[2] != NVL_SUCCESS) && (status[2] != -NVL_NOT_FOUND)) + { + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +#if 0 +static NvlStatus +_nvswitch_service_soe_fatal_ls10 +( + nvswitch_device *device +) +{ + // We only support 1 SOE as of LS10. + if (soeService_HAL(device, (PSOE)device->pSoe) != 0) + { + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} +#endif //0 + +static NvlStatus +_nvswitch_service_nvlipt_lnk_fatal_ls10 +( + nvswitch_device *device, + NvU32 nvlipt_instance, + NvU32 link +) +{ + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + NvU32 pending, bit, unhandled; + + report.raw_pending = NVSWITCH_LINK_RD32(device, link, NVLIPT_LNK, _NVLIPT_LNK, _ERR_STATUS_0); + report.raw_enable = NVSWITCH_LINK_RD32(device, link, NVLIPT_LNK, _NVLIPT_LNK, _ERR_FATAL_REPORT_EN_0); + report.mask = report.raw_enable; + + pending = report.raw_pending & report.mask; + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + report.raw_first = NVSWITCH_LINK_RD32(device, link, NVLIPT_LNK, _NVLIPT_LNK, _ERR_FIRST_0); + + bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _SLEEPWHILEACTIVELINK, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLIPT_LNK_SLEEPWHILEACTIVELINK, "No non-empty link is detected", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _RSTSEQ_PHYCTL_TIMEOUT, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLIPT_LNK_RSTSEQ_PHYCTL_TIMEOUT, "Reset sequencer timed out waiting for a handshake from PHYCTL", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _RSTSEQ_CLKCTL_TIMEOUT, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_NVLIPT_LNK_RSTSEQ_CLKCTL_TIMEOUT, "Reset sequencer timed out waiting for a handshake from CLKCTL", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + // Disable interrupts that have occurred after fatal error. + if (device->link[link].fatal_error_occurred) + { + NVSWITCH_LINK_WR32(device, link, NVLIPT_LNK, _NVLIPT_LNK, _ERR_FATAL_REPORT_EN_0, + report.raw_enable ^ pending); + } + + // clear interrupts + if (report.raw_first & report.mask) + { + NVSWITCH_LINK_WR32(device, link, NVLIPT_LNK, _NVLIPT_LNK, _ERR_FIRST_0, + report.raw_first & report.mask); + } + NVSWITCH_LINK_WR32(device, link, NVLIPT_LNK, _NVLIPT_LNK, _ERR_STATUS_0, pending); + + if (unhandled != 0) + { + NVSWITCH_PRINT(device, WARN, + "%s: Unhandled NVLIPT_LNK FATAL interrupts, pending: 0x%x enabled: 0x%x.\n", + __FUNCTION__, pending, report.raw_enable); + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_nvswitch_service_nvlipt_link_fatal_ls10 +( + nvswitch_device *device, + NvU32 instance +) +{ + NvU32 i, globalLink, bit, intrLink; + NvU32 interruptingLinks = 0; + + //read in error status of current link + for (i = 0; i < NVSWITCH_LINKS_PER_NVLIPT_LS10; ++i) + { + globalLink = (instance * NVSWITCH_LINKS_PER_NVLIPT_LS10) + i; + + intrLink = NVSWITCH_LINK_RD32(device, globalLink, NVLIPT_LNK, _NVLIPT_LNK, _ERR_STATUS_0); + + if(intrLink) + { + interruptingLinks |= NVBIT(i); + } + } + + if(interruptingLinks) + { + for (i = 0; i < NVSWITCH_LINKS_PER_NVLIPT_LS10; ++i) + { + bit = NVBIT(i); + globalLink = (instance * NVSWITCH_LINKS_PER_NVLIPT_LS10) + i; + if (nvswitch_test_flags(interruptingLinks, bit)) + { + if( _nvswitch_service_nvlipt_lnk_fatal_ls10(device, instance, globalLink) != NVL_SUCCESS) + { + return -NVL_MORE_PROCESSING_REQUIRED; + } + } + } + return NVL_SUCCESS; + } + else + { + return -NVL_NOT_FOUND; + } +} + +static NvlStatus +_nvswitch_service_nvlw_fatal_ls10 +( + nvswitch_device *device, + NvU32 instance +) +{ + NvlStatus status[6]; + + status[0] = device->hal.nvswitch_service_minion_link(device, instance); + status[1] = _nvswitch_service_nvldl_fatal_ls10(device, instance); + status[2] = _nvswitch_service_nvltlc_fatal_ls10(device, instance); + status[3] = _nvswitch_service_minion_fatal_ls10(device, instance); + status[4] = _nvswitch_service_nvlipt_common_fatal_ls10(device, instance); + status[5] = _nvswitch_service_nvlipt_link_fatal_ls10(device, instance); + + + if (status[0] != NVL_SUCCESS && + status[1] != NVL_SUCCESS && + status[2] != NVL_SUCCESS && + status[3] != NVL_SUCCESS && + status[4] != NVL_SUCCESS && + status[5] != NVL_SUCCESS) + { + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +/* + * @Brief : Enable top level HW interrupts. + * + * @Description : + * + * @param[in] device operate on this device + */ +void +nvswitch_lib_enable_interrupts_ls10 +( + nvswitch_device *device +) +{ + NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_SET(NV_CTRL_CPU_INTR_NPG_FATAL_IDX), 0xFFFF); + NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_SET(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX), 0xFFFF); + NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_SET(NV_CTRL_CPU_INTR_NPG_CORRECTABLE_IDX), 0); + + NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_SET(NV_CTRL_CPU_INTR_NVLW_FATAL_IDX), 0xFFFF); + NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_SET(NV_CTRL_CPU_INTR_NVLW_NON_FATAL_IDX), 0xFFFF); + NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_SET(NV_CTRL_CPU_INTR_NVLW_CORRECTABLE_IDX), 0); + + NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_SET(NV_CTRL_CPU_INTR_NXBAR_FATAL_IDX), 0x7); + + NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_UNITS_IDX), 0xFFFFFFFF); + NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_SET(NV_CTRL_CPU_INTR_UNITS_IDX), + DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PMGR_HOST, 1) | + DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PTIMER, 1) | + DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PTIMER_ALARM, 1) | + DRF_NUM(_CTRL, _CPU_INTR_UNITS, _XTL_CPU, 1) | + DRF_NUM(_CTRL, _CPU_INTR_UNITS, _XAL_EP, 1) | + DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PRIV_RING, 1)); + + NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_TOP_EN_SET(0), 0xFFFFFFFF); +} + +/* + * @Brief : Disable top level HW interrupts. + * + * @Description : + * + * @param[in] device operate on this device + */ +void +nvswitch_lib_disable_interrupts_ls10 +( + nvswitch_device *device +) +{ + NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_FATAL_IDX), 0xFFFF); + NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX), 0xFFFF); + NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NPG_CORRECTABLE_IDX), 0); + + NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NVLW_FATAL_IDX), 0xFFFF); + NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NVLW_NON_FATAL_IDX), 0xFFFF); + NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NVLW_CORRECTABLE_IDX), 0); + + NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_NXBAR_FATAL_IDX), 0x7); + + NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF_EN_CLEAR(NV_CTRL_CPU_INTR_UNITS_IDX), + DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PMGR_HOST, 1) | + DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PTIMER, 1) | + DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PTIMER_ALARM, 1) | + DRF_NUM(_CTRL, _CPU_INTR_UNITS, _XTL_CPU, 1) | + DRF_NUM(_CTRL, _CPU_INTR_UNITS, _XAL_EP, 1) | + DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PRIV_RING, 1)); + + NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_TOP_EN_CLEAR(0), 0xFFFFFFFF); +} + +// +// Check if there are interrupts pending. +// +// On silicon/emulation we only use MSIs which are not shared, so this +// function does not need to be called. +// +NvlStatus +nvswitch_lib_check_interrupts_ls10 +( + nvswitch_device *device +) +{ + NvlStatus retval = NVL_SUCCESS; + NvU32 val; + + val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_TOP(0)); + if (DRF_NUM(_CTRL, _CPU_INTR_TOP, _VALUE, val) != 0) + { + retval = -NVL_MORE_PROCESSING_REQUIRED; + } + + return retval; +} + +static void +_nvswitch_retrigger_engine_intr_ls10 +( + nvswitch_device *device +) +{ + + // re-trigger engine to gin interrupts for CPR and NPG on the FATAL and NONFATAL trees + NVSWITCH_BCAST_WR32_LS10(device, CPR, _CPR_SYS, _INTR_RETRIGGER(0), 1); + NVSWITCH_BCAST_WR32_LS10(device, CPR, _CPR_SYS, _INTR_RETRIGGER(1), 1); + + NVSWITCH_BCAST_WR32_LS10(device, NPG, _NPG, _INTR_RETRIGGER(0), 1); + NVSWITCH_BCAST_WR32_LS10(device, NPG, _NPG, _INTR_RETRIGGER(1), 1); +} + +void +nvswitch_service_minion_all_links_ls10 +( + nvswitch_device *device +) +{ + NvU32 val, i; + + // Check NVLW + val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_NVLW_FATAL); + val = DRF_NUM(_CTRL, _CPU_INTR_NVLW_FATAL, _MASK, val); + if (val != 0) + { + NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, + _CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NVLW_FATAL_IDX), val); + + for (i = 0; i < DRF_SIZE(NV_CTRL_CPU_INTR_NVLW_FATAL_MASK); i++) + { + if (val & NVBIT(i)) + (void)_nvswitch_service_nvlw_fatal_ls10(device, i); + } + } +} + +// +// Service interrupt and re-enable interrupts. Interrupts should disabled when +// this is called. +// +NvlStatus +nvswitch_lib_service_interrupts_ls10 +( + nvswitch_device *device +) +{ + NvlStatus status = NVL_SUCCESS; + NvlStatus return_status = NVL_SUCCESS; + NvU32 val; + NvU32 i; + + // + // Interrupt handler steps: + // 1. Read Leaf interrupt + // 2. Clear leaf interrupt + // 3. Run leaf specific interrupt handler + // + val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_NVLW_FATAL); + val = DRF_NUM(_CTRL, _CPU_INTR_NVLW_FATAL, _MASK, val); + if (val != 0) + { + NVSWITCH_PRINT(device, INFO, "%s: NVLW FATAL interrupts pending = 0x%x\n", + __FUNCTION__, val); + + NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NVLW_FATAL_IDX), val); + + for (i = 0; i < DRF_SIZE(NV_CTRL_CPU_INTR_NVLW_FATAL_MASK); i++) + { + if (val & NVBIT(i)) + { + status = _nvswitch_service_nvlw_fatal_ls10(device, i); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, INFO, "%s: NVLW[%d] FATAL interrupt handling status = %d\n", + __FUNCTION__, i, status); + return_status = status; + } + } + } + } + + val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_NVLW_NON_FATAL); + val = DRF_NUM(_CTRL, _CPU_INTR_NVLW_NON_FATAL, _MASK, val); + if (val != 0) + { + NVSWITCH_PRINT(device, INFO, "%s: NVLW NON_FATAL interrupts pending = 0x%x\n", + __FUNCTION__, val); + NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NVLW_NON_FATAL_IDX), val); + for (i = 0; i < DRF_SIZE(NV_CTRL_CPU_INTR_NVLW_NON_FATAL_MASK); i++) + { + if (val & NVBIT(i)) + { + status = _nvswitch_service_nvlw_nonfatal_ls10(device, i); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, INFO, "%s: NVLW[%d] NON_FATAL interrupt handling status = %d\n", + __FUNCTION__, i, status); + return_status = status; + } + } + } + } + + val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_NVLW_CORRECTABLE); + val = DRF_NUM(_CTRL, _CPU_INTR_NVLW_CORRECTABLE, _MASK, val); + if (val != 0) + { + NVSWITCH_PRINT(device, ERROR, "%s: NVLW CORRECTABLE interrupts pending = 0x%x\n", + __FUNCTION__, val); + return_status = -NVL_MORE_PROCESSING_REQUIRED; + } + + // Check NPG + val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_NPG_FATAL); + val = DRF_NUM(_CTRL, _CPU_INTR_NPG_FATAL, _MASK, val); + if (val != 0) + { + NVSWITCH_PRINT(device, INFO, "%s: NPG FATAL interrupts pending = 0x%x\n", + __FUNCTION__, val); + NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NPG_FATAL_IDX), val); + for (i = 0; i < DRF_SIZE(NV_CTRL_CPU_INTR_NPG_FATAL_MASK); i++) + { + if (val & NVBIT(i)) + { + status = _nvswitch_service_npg_fatal_ls10(device, i); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, INFO, "%s: NPG[%d] FATAL interrupt handling status = %d\n", + __FUNCTION__, i, status); + return_status = status; + } + } + } + } + + val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_NPG_NON_FATAL); + val = DRF_NUM(_CTRL, _CPU_INTR_NPG_NON_FATAL, _MASK, val); + if (val != 0) + { + NVSWITCH_PRINT(device, INFO, "%s: NPG NON_FATAL interrupts pending = 0x%x\n", + __FUNCTION__, val); + NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NPG_NON_FATAL_IDX), val); + for (i = 0; i < DRF_SIZE(NV_CTRL_CPU_INTR_NPG_NON_FATAL_MASK); i++) + { + if (val & NVBIT(i)) + { + status = _nvswitch_service_npg_nonfatal_ls10(device, i); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, INFO, "%s: NPG[%d] NON_FATAL interrupt handling status = %d\n", + __FUNCTION__, i, status); + return_status = status; + } + } + } + } + + val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_NPG_CORRECTABLE); + val = DRF_NUM(_CTRL, _CPU_INTR_NPG_CORRECTABLE, _MASK, val); + if (val != 0) + { + NVSWITCH_PRINT(device, ERROR, "%s: NPG CORRECTABLE interrupts pending = 0x%x\n", + __FUNCTION__, val); + return_status = -NVL_MORE_PROCESSING_REQUIRED; + } + + // Check NXBAR + val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_NXBAR_FATAL); + val = DRF_NUM(_CTRL, _CPU_INTR_NXBAR_FATAL, _MASK, val); + if (val != 0) + { + NVSWITCH_PRINT(device, INFO, "%s: NXBAR FATAL interrupts pending = 0x%x\n", + __FUNCTION__, val); + NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF(NV_CTRL_CPU_INTR_NXBAR_FATAL_IDX), val); + for (i = 0; i < DRF_SIZE(NV_CTRL_CPU_INTR_NXBAR_FATAL_MASK); i++) + { + if (val & NVBIT(i)) + { + status = _nvswitch_service_nxbar_fatal_ls10(device, i); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, INFO, "%s: NXBAR[%d] FATAL interrupt handling status = %d\n", + __FUNCTION__, i, status); + return_status = status; + } + } + } + } + + // Check UNITS + val = NVSWITCH_ENG_RD32(device, GIN, , 0, _CTRL, _CPU_INTR_UNITS); + if (val != 0) + { + NVSWITCH_PRINT(device, INFO, "%s: UNIT interrupts pending = 0x%x\n", + __FUNCTION__, val); + + NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_LEAF(NV_CTRL_CPU_INTR_UNITS_IDX), val); + if (FLD_TEST_DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PMGR_HOST, 1, val)) + { + NVSWITCH_PRINT(device, ERROR, "%s: _PMGR_HOST interrupt pending\n", + __FUNCTION__); + return_status = -NVL_MORE_PROCESSING_REQUIRED; + } + if (FLD_TEST_DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PTIMER, 1, val)) + { + NVSWITCH_PRINT(device, ERROR, "%s: _PTIMER interrupt pending\n", + __FUNCTION__); + return_status = -NVL_MORE_PROCESSING_REQUIRED; + } + if (FLD_TEST_DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PTIMER_ALARM, 1, val)) + { + NVSWITCH_PRINT(device, ERROR, "%s: _PTIMER_ALARM interrupt pending\n", + __FUNCTION__); + return_status = -NVL_MORE_PROCESSING_REQUIRED; + } + if (FLD_TEST_DRF_NUM(_CTRL, _CPU_INTR_UNITS, _XTL_CPU, 1, val)) + { + NVSWITCH_PRINT(device, ERROR, "%s: _XTL_CPU interrupt pending\n", + __FUNCTION__); + return_status = -NVL_MORE_PROCESSING_REQUIRED; + } + if (FLD_TEST_DRF_NUM(_CTRL, _CPU_INTR_UNITS, _XAL_EP, 1, val)) + { + NVSWITCH_PRINT(device, ERROR, "%s: _XAL_EP interrupt pending\n", + __FUNCTION__); + return_status = -NVL_MORE_PROCESSING_REQUIRED; + } + if (FLD_TEST_DRF_NUM(_CTRL, _CPU_INTR_UNITS, _PRIV_RING, 1, val)) + { + status = _nvswitch_service_priv_ring_ls10(device); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: Problem handling PRI errors\n", + __FUNCTION__); + return_status = status; + } + } + } + + // step 4 -- retrigger engine interrupts + _nvswitch_retrigger_engine_intr_ls10(device); + + // step 5 -- retrigger top level GIN interrupts + NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_TOP_EN_CLEAR(0), 0xFFFFFFFF); + NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _CPU_INTR_TOP_EN_SET(0), 0xFFFFFFFF); + + return return_status; +} + +/* + * Initialize interrupt tree HW for all units. + * + * Init and servicing both depend on bits matching across STATUS/MASK + * and IErr STATUS/LOG/REPORT/CONTAIN registers. + */ +void +nvswitch_initialize_interrupt_tree_ls10 +( + nvswitch_device *device +) +{ + NvU64 link_mask = nvswitch_get_enabled_link_mask(device); + NvU32 i, val; + + // NPG/NPORT + _nvswitch_initialize_nport_interrupts_ls10(device); + + // NXBAR + _nvswitch_initialize_nxbar_interrupts_ls10(device); + + FOR_EACH_INDEX_IN_MASK(64, i, link_mask) + { + val = NVSWITCH_LINK_RD32(device, i, + NVLW, _NVLW, _LINK_INTR_0_MASK(i)); + val = FLD_SET_DRF(_NVLW, _LINK_INTR_0_MASK, _FATAL, _ENABLE, val); + val = FLD_SET_DRF(_NVLW, _LINK_INTR_0_MASK, _NONFATAL, _ENABLE, val); + val = FLD_SET_DRF(_NVLW, _LINK_INTR_0_MASK, _CORRECTABLE, _ENABLE, val); + val = FLD_SET_DRF(_NVLW, _LINK_INTR_0_MASK, _INTR0, _ENABLE, val); + val = FLD_SET_DRF(_NVLW, _LINK_INTR_0_MASK, _INTR1, _ENABLE, val); + NVSWITCH_LINK_WR32(device, i, NVLW, _NVLW, _LINK_INTR_0_MASK(i), val); + } + FOR_EACH_INDEX_IN_MASK_END; + + FOR_EACH_INDEX_IN_MASK(64, i, link_mask) + { + val = NVSWITCH_LINK_RD32(device, i, + NVLW, _NVLW, _LINK_INTR_1_MASK(i)); + val = FLD_SET_DRF(_NVLW, _LINK_INTR_1_MASK, _FATAL, _ENABLE, val); + val = FLD_SET_DRF(_NVLW, _LINK_INTR_1_MASK, _NONFATAL, _ENABLE, val); + val = FLD_SET_DRF(_NVLW, _LINK_INTR_1_MASK, _CORRECTABLE, _ENABLE, val); + val = FLD_SET_DRF(_NVLW, _LINK_INTR_1_MASK, _INTR0, _ENABLE, val); + val = FLD_SET_DRF(_NVLW, _LINK_INTR_1_MASK, _INTR1, _ENABLE, val); + NVSWITCH_LINK_WR32(device, i, NVLW, _NVLW, _LINK_INTR_1_MASK(i), val); + } + FOR_EACH_INDEX_IN_MASK_END; + + // NVLIPT + _nvswitch_initialize_nvlipt_interrupts_ls10(device); +} + +// +// Service Nvswitch NVLDL Fatal interrupts +// +NvlStatus +nvswitch_service_nvldl_fatal_link_ls10 +( + nvswitch_device *device, + NvU32 nvlipt_instance, + NvU32 link +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NvU32 pending, bit, unhandled; + NvBool bSkipIntrClear = NV_FALSE; + + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + + report.raw_pending = NVSWITCH_LINK_RD32(device, link, NVLDL, _NVLDL_TOP, _INTR); + report.raw_enable = NVSWITCH_LINK_RD32(device, link, NVLDL, _NVLDL_TOP, _INTR_STALL_EN); + report.mask = report.raw_enable; + pending = report.raw_pending & report.mask; + + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + + bit = DRF_NUM(_NVLDL_TOP, _INTR, _TX_FAULT_RAM, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_DLPL_TX_FAULT_RAM, "TX Fault Ram", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLDL_TOP, _INTR, _TX_FAULT_INTERFACE, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_DLPL_TX_FAULT_INTERFACE, "TX Fault Interface", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLDL_TOP, _INTR, _TX_FAULT_SUBLINK_CHANGE, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_DLPL_TX_FAULT_SUBLINK_CHANGE, "TX Fault Sublink Change", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLDL_TOP, _INTR, _RX_FAULT_SUBLINK_CHANGE, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_DLPL_RX_FAULT_SUBLINK_CHANGE, "RX Fault Sublink Change", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLDL_TOP, _INTR, _RX_FAULT_DL_PROTOCOL, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_DLPL_RX_FAULT_DL_PROTOCOL, "RX Fault DL Protocol", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_DOWN, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_DLPL_LTSSM_FAULT_DOWN, "LTSSM Fault Down", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_PROTOCOL, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_DLPL_LTSSM_PROTOCOL, "LTSSM Protocol Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLDL_TOP, _INTR, _PHY_A, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_DLPL_PHY_A, "PHY_A Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLDL_TOP, _INTR, _TX_PL_ERROR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_DLPL_TX_PL_ERROR, "TX_PL Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + bit = DRF_NUM(_NVLDL_TOP, _INTR, _RX_PL_ERROR, 1); + if (nvswitch_test_flags(pending, bit)) + { + NVSWITCH_REPORT_FATAL(_HW_DLPL_RX_PL_ERROR, "RX_PL Error", NV_FALSE); + nvswitch_clear_flags(&unhandled, bit); + } + + // + // Note: LTSSM_FAULT_UP must be the last interrupt serviced in the NVLDL + // Fatal tree. The last step of handling this interrupt is going into the + // reset_and_drain flow for the given link which will shutdown and reset + // the link. The reset portion will also wipe away any link state including + // pending DL interrupts. In order to log all error before wiping that state, + // service all other interrupts before this one + // + bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_UP, 1); + if (nvswitch_test_flags(pending, bit)) + { + chip_device->deferredLinkErrors[link].fatalIntrMask.dl |= bit; + _nvswitch_create_deferred_link_errors_task_ls10(device, nvlipt_instance, link); + + nvswitch_clear_flags(&unhandled, bit); + device->hal.nvswitch_reset_and_drain_links(device, NVBIT64(link)); + + // + // Since reset and drain will reset the link, including clearing + // pending interrupts, skip the clear write below. There are cases + // where link clocks will not be on after reset and drain so there + // maybe PRI errors on writing to the register + // + bSkipIntrClear = NV_TRUE; + } + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + // Disable interrupts that have occurred after fatal error. + if (device->link[link].fatal_error_occurred) + { + NVSWITCH_LINK_WR32(device, link, NVLDL, _NVLDL_TOP, _INTR_STALL_EN, + report.raw_enable ^ pending); + } + + if (!bSkipIntrClear) + { + NVSWITCH_LINK_WR32(device, link, NVLDL, _NVLDL_TOP, _INTR, pending); + } + + if (unhandled != 0) + { + NVSWITCH_PRINT(device, WARN, + "%s: Unhandled NVLDL fatal interrupts, link: %d pending: 0x%x enabled: 0x%x.\n", + __FUNCTION__, link, pending, report.raw_enable); + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_service_minion_link_ls10 +( + nvswitch_device *device, + NvU32 instance +) +{ + NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 }; + NvU32 pending, unhandled, minionIntr, linkIntr, reg, enabledLinks, bit; + NvU32 localLinkIdx, link; + + // + // _MINION_MINION_INTR shows all interrupts currently at the host on this minion + // Note: _MINIO_MINION_INTR is not used to clear link specific interrupts + // + minionIntr = NVSWITCH_MINION_RD32_LS10(device, instance, _MINION, _MINION_INTR); + + // get all possible interrupting links associated with this minion + report.raw_pending = DRF_VAL(_MINION, _MINION_INTR, _LINK, minionIntr); + + // read in the enaled minion interrupts on this minion + reg = NVSWITCH_MINION_RD32_LS10(device, instance, _MINION, _MINION_INTR_STALL_EN); + + // get the links with enabled interrupts on this minion + enabledLinks = DRF_VAL(_MINION, _MINION_INTR_STALL_EN, _LINK, reg); + + report.raw_enable = enabledLinks; + report.mask = report.raw_enable; + + // pending bit field contains interrupting links after being filtered + pending = report.raw_pending & report.mask; + + if (pending == 0) + { + return -NVL_NOT_FOUND; + } + + unhandled = pending; + + FOR_EACH_INDEX_IN_MASK(32, localLinkIdx, pending) + { + link = (instance * NVSWITCH_LINKS_PER_NVLIPT_LS10) + localLinkIdx; + bit = NVBIT(localLinkIdx); + + // read in the interrupt register for the given link + linkIntr = NVSWITCH_MINION_LINK_RD32_LS10(device, link, _MINION, _NVLINK_LINK_INTR(localLinkIdx)); + + // _STATE must be set for _CODE to be valid + if (!DRF_VAL(_MINION, _NVLINK_LINK_INTR, _STATE, linkIntr)) + { + continue; + } + + NVSWITCH_PRINT(device, INFO, + "%s: link[%d] {%d, %d} linkIntr = 0x%x\n", + __FUNCTION__, link, instance, localLinkIdx, linkIntr); + + // + // _MINION_INTR_LINK is a read-only register field for the host + // Host must write 1 to _NVLINK_LINK_INTR_STATE to clear the interrupt on the link + // + reg = DRF_NUM(_MINION, _NVLINK_LINK_INTR, _STATE, 1); + NVSWITCH_MINION_WR32_LS10(device, instance, _MINION, _NVLINK_LINK_INTR(localLinkIdx), reg); + + report.data[0] = linkIntr; + + switch(DRF_VAL(_MINION, _NVLINK_LINK_INTR, _CODE, linkIntr)) + { + case NV_MINION_NVLINK_LINK_INTR_CODE_NA: + NVSWITCH_REPORT_FATAL(_HW_MINION_FATAL_LINK_INTR, "Minion Link NA interrupt", NV_FALSE); + break; + case NV_MINION_NVLINK_LINK_INTR_CODE_SWREQ: + NVSWITCH_PRINT(device, INFO, + "%s: Received MINION Link SW Generate interrupt on MINION %d : link %d.\n", + __FUNCTION__, instance, link); + break; + case NV_MINION_NVLINK_LINK_INTR_CODE_DLREQ: + NVSWITCH_REPORT_NONFATAL(_HW_MINION_NONFATAL, "Minion Link DLREQ interrupt"); + break; + case NV_MINION_NVLINK_LINK_INTR_CODE_PMDISABLED: + NVSWITCH_REPORT_NONFATAL(_HW_MINION_NONFATAL, "Minion Link PMDISABLED interrupt"); + break; + case NV_MINION_NVLINK_LINK_INTR_CODE_DLCMDFAULT: + NVSWITCH_REPORT_FATAL(_HW_MINION_FATAL_LINK_INTR, "Minion Link DLCMDFAULT interrupt", NV_FALSE); + break; + case NV_MINION_NVLINK_LINK_INTR_CODE_TLREQ: + NVSWITCH_REPORT_NONFATAL(_HW_MINION_NONFATAL, "Minion Link TLREQ interrupt"); + break; + case NV_MINION_NVLINK_LINK_INTR_CODE_NOINIT: + NVSWITCH_REPORT_FATAL(_HW_MINION_FATAL_LINK_INTR, "Minion Link NOINIT interrupt", NV_FALSE); + break; + case NV_MINION_NVLINK_LINK_INTR_CODE_NOTIFY: + NVSWITCH_PRINT(device, INFO, + "%s: Received MINION NOTIFY interrupt on MINION %d : link %d.\n", + __FUNCTION__, instance, link); + break; + case NV_MINION_NVLINK_LINK_INTR_CODE_LOCAL_CONFIG_ERR: + NVSWITCH_REPORT_FATAL(_HW_MINION_FATAL_LINK_INTR, "Minion Link Local-Config-Error interrupt", NV_FALSE); + break; + case NV_MINION_NVLINK_LINK_INTR_CODE_NEGOTIATION_CONFIG_ERR: + NVSWITCH_REPORT_FATAL(_HW_MINION_FATAL_LINK_INTR, "Minion Link Negotiation Config Err Interrupt", NV_FALSE); + break; + case NV_MINION_NVLINK_LINK_INTR_CODE_BADINIT: + NVSWITCH_REPORT_FATAL(_HW_MINION_FATAL_LINK_INTR, "Minion Link BADINIT interrupt", NV_FALSE); + break; + case NV_MINION_NVLINK_LINK_INTR_CODE_PMFAIL: + NVSWITCH_REPORT_FATAL(_HW_MINION_FATAL_LINK_INTR, "Minion Link PMFAIL interrupt", NV_FALSE); + break; + case NV_MINION_NVLINK_LINK_INTR_CODE_INBAND_BUFFER_AVAILABLE: + { + NVSWITCH_PRINT(device, INFO, + "Received INBAND_BUFFER_AVAILABLE interrupt on MINION %d,\n", instance); + nvswitch_minion_receive_inband_data_ls10(device, link); + break; + } + + default: + NVSWITCH_REPORT_FATAL(_HW_MINION_FATAL_LINK_INTR, "Minion Interrupt code unknown", NV_FALSE); + } + nvswitch_clear_flags(&unhandled, bit); + + // Disable interrupt bit for the given link - fatal error ocurred before + if (device->link[link].fatal_error_occurred) + { + enabledLinks &= ~bit; + reg = DRF_NUM(_MINION, _MINION_INTR_STALL_EN, _LINK, enabledLinks); + NVSWITCH_MINION_LINK_WR32_LS10(device, link, _MINION, _MINION_INTR_STALL_EN, reg); + } + } + FOR_EACH_INDEX_IN_MASK_END; + + NVSWITCH_UNHANDLED_CHECK(device, unhandled); + + if (unhandled != 0) + { + return -NVL_MORE_PROCESSING_REQUIRED; + } + + return NVL_SUCCESS; +} + diff --git a/src/common/nvswitch/kernel/ls10/link_ls10.c b/src/common/nvswitch/kernel/ls10/link_ls10.c new file mode 100644 index 000000000..2ad3b012c --- /dev/null +++ b/src/common/nvswitch/kernel/ls10/link_ls10.c @@ -0,0 +1,1396 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvlink_export.h" + +#include "export_nvswitch.h" +#include "common_nvswitch.h" +#include "regkey_nvswitch.h" +#include "ls10/ls10.h" +#include "nvswitch/ls10/dev_nvldl_ip_addendum.h" + +#include "nvswitch/ls10/dev_nvldl_ip.h" +#include "nvswitch/ls10/dev_nvlipt_lnk_ip.h" +#include "nvswitch/ls10/dev_nvlphyctl_ip.h" +#include "nvswitch/ls10/dev_nvltlc_ip.h" +#include "nvswitch/ls10/dev_minion_ip.h" +#include "nvswitch/ls10/dev_nvlipt_lnk_ip.h" +#include "nvswitch/ls10/dev_nvlipt_ip.h" +#include "nvswitch/ls10/dev_nport_ip.h" +#include "nvswitch/ls10/dev_minion_ip_addendum.h" +#include "ls10/minion_nvlink_defines_public_ls10.h" + +static void +_nvswitch_configure_reserved_throughput_counters +( + nvlink_link *link +) +{ + nvswitch_device *device = link->dev->pDevInfo; + NvU32 linkNum = link->linkNumber; + + if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLTLC, link->linkNumber)) + { + NVSWITCH_PRINT(device, INFO, + "Invalid link, skipping NVLink throughput counter config for link %d\n", + link->linkNumber); + return; + } + + // + // Counters 0 and 2 will be reserved for monitoring tools + // Counters 1 and 3 will be user-configurable and used by devtools + // + + // Rx0 config + NVSWITCH_LINK_WR32_IDX_LS10(device, linkNum, NVLTLC, _NVLTLC_RX_LNK, _DEBUG_TP_CNTR_CTRL_0, 0, + DRF_DEF(_NVLTLC_RX_LNK, _DEBUG_TP_CNTR_CTRL_0, _UNIT, _FLITS) | + DRF_DEF(_NVLTLC_RX_LNK, _DEBUG_TP_CNTR_CTRL_0, _FLITFILTER, _DATA) | + DRF_DEF(_NVLTLC_RX_LNK, _DEBUG_TP_CNTR_CTRL_0, _VCSETFILTERMODE, _INIT) | + DRF_DEF(_NVLTLC_RX_LNK, _DEBUG_TP_CNTR_CTRL_0, _ENABLE, _ENABLE)); + + // Tx0 config + NVSWITCH_LINK_WR32_IDX_LS10(device, linkNum, NVLTLC, _NVLTLC_TX_LNK, _DEBUG_TP_CNTR_CTRL_0, 0, + DRF_DEF(_NVLTLC_TX_LNK, _DEBUG_TP_CNTR_CTRL_0, _UNIT, _FLITS) | + DRF_DEF(_NVLTLC_TX_LNK, _DEBUG_TP_CNTR_CTRL_0, _FLITFILTER, _DATA) | + DRF_DEF(_NVLTLC_TX_LNK, _DEBUG_TP_CNTR_CTRL_0, _VCSETFILTERMODE, _INIT) | + DRF_DEF(_NVLTLC_TX_LNK, _DEBUG_TP_CNTR_CTRL_0, _ENABLE, _ENABLE)); + + // Rx2 config + NVSWITCH_LINK_WR32_IDX_LS10(device, linkNum, NVLTLC, _NVLTLC_RX_LNK, _DEBUG_TP_CNTR_CTRL_0, 2, + DRF_DEF(_NVLTLC_RX_LNK, _DEBUG_TP_CNTR_CTRL_0, _UNIT, _FLITS) | + DRF_DEF(_NVLTLC_RX_LNK, _DEBUG_TP_CNTR_CTRL_0, _FLITFILTER, _HEAD) | + DRF_DEF(_NVLTLC_RX_LNK, _DEBUG_TP_CNTR_CTRL_0, _FLITFILTER, _AE) | + DRF_DEF(_NVLTLC_RX_LNK, _DEBUG_TP_CNTR_CTRL_0, _FLITFILTER, _BE) | + DRF_DEF(_NVLTLC_RX_LNK, _DEBUG_TP_CNTR_CTRL_0, _FLITFILTER, _DATA) | + DRF_DEF(_NVLTLC_RX_LNK, _DEBUG_TP_CNTR_CTRL_0, _VCSETFILTERMODE, _INIT) | + DRF_DEF(_NVLTLC_RX_LNK, _DEBUG_TP_CNTR_CTRL_0, _ENABLE, _ENABLE)); + + // Tx2 config + NVSWITCH_LINK_WR32_IDX_LS10(device, linkNum, NVLTLC, _NVLTLC_TX_LNK, _DEBUG_TP_CNTR_CTRL_0, 2, + DRF_DEF(_NVLTLC_TX_LNK, _DEBUG_TP_CNTR_CTRL_0, _UNIT, _FLITS) | + DRF_DEF(_NVLTLC_TX_LNK, _DEBUG_TP_CNTR_CTRL_0, _FLITFILTER, _HEAD) | + DRF_DEF(_NVLTLC_TX_LNK, _DEBUG_TP_CNTR_CTRL_0, _FLITFILTER, _AE) | + DRF_DEF(_NVLTLC_TX_LNK, _DEBUG_TP_CNTR_CTRL_0, _FLITFILTER, _BE) | + DRF_DEF(_NVLTLC_TX_LNK, _DEBUG_TP_CNTR_CTRL_0, _FLITFILTER, _DATA) | + DRF_DEF(_NVLTLC_TX_LNK, _DEBUG_TP_CNTR_CTRL_0, _VCSETFILTERMODE, _INIT) | + DRF_DEF(_NVLTLC_TX_LNK, _DEBUG_TP_CNTR_CTRL_0, _ENABLE, _ENABLE)); +} + +void +nvswitch_init_lpwr_regs_ls10 +( + nvlink_link *link +) +{ + nvswitch_device *device = link->dev->pDevInfo; + // NVSWITCH_BIOS_NVLINK_CONFIG *bios_config; + NvU32 linkNum = link->linkNumber; + NvU32 tempRegVal, lpEntryThreshold; + NvU8 softwareDesired; + NvBool bLpEnable; + + if (device->regkeys.enable_pm == NV_SWITCH_REGKEY_ENABLE_PM_NO) + { + return; + } + + // bios_config = nvswitch_get_bios_nvlink_config(device); + + // IC Enter Threshold + if (device->regkeys.lp_threshold == NV_SWITCH_REGKEY_SET_LP_THRESHOLD_DEFAULT) + { + // TODO: get from bios. Refer Bug 3626523 for more info. + lpEntryThreshold = 100; + } + else + { + lpEntryThreshold = device->regkeys.lp_threshold; + } + + tempRegVal = 0; + tempRegVal = FLD_SET_DRF_NUM(_NVLIPT, _LNK_PWRM_L1_ENTER_THRESHOLD, _THRESHOLD, lpEntryThreshold, tempRegVal); + NVSWITCH_LINK_WR32_LS10(device, linkNum, NVLIPT_LNK, _NVLIPT_LNK, _PWRM_L1_ENTER_THRESHOLD, tempRegVal); + + //LP Entry Enable + bLpEnable = NV_TRUE; + softwareDesired = (bLpEnable) ? 0x1 : 0x0; + + // TO-DO: The write to the AN1 register is not working. The logic here needs to be re-visited. + tempRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNum, NVLIPT_LNK, _NVLIPT_LNK, _CTRL_SYSTEM_LINK_AN1_CTRL); + tempRegVal = FLD_SET_DRF_NUM(_NVLIPT, _LNK_CTRL_SYSTEM_LINK_AN1_CTRL, _PWRM_L1_ENABLE, softwareDesired, tempRegVal); + NVSWITCH_LINK_WR32_LS10(device, linkNum, NVLIPT_LNK, _NVLIPT_LNK, _CTRL_SYSTEM_LINK_AN1_CTRL, tempRegVal); +} + +void +nvswitch_corelib_training_complete_ls10 +( + nvlink_link *link +) +{ + nvswitch_device *device = link->dev->pDevInfo; + + nvswitch_init_dlpl_interrupts(link); + _nvswitch_configure_reserved_throughput_counters(link); + + if (nvswitch_lib_notify_client_events(device, + NVSWITCH_DEVICE_EVENT_PORT_UP) != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed to notify PORT_UP event\n", + __FUNCTION__); + } + + return; +} + +NvlStatus +nvswitch_wait_for_tl_request_ready_ls10 +( + nvlink_link *link +) +{ + nvswitch_device *device = link->dev->pDevInfo; + NVSWITCH_MINION_ALI_DEBUG_REGISTERS params; + NvU32 nvldlErrCntl, nvldlTopLinkState, nvldlTopIntr, linkStateRequest; + NvlStatus status = nvswitch_wait_for_tl_request_ready_lr10(link); + + + if(status == -NVL_ERR_GENERIC) + { + linkStateRequest = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, + NVLIPT_LNK , _NVLIPT_LNK , _CTRL_LINK_STATE_REQUEST); + nvldlErrCntl = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, + NVLDL, _NVLDL_RX_RXSLSM , _ERR_CNTL); + nvldlTopLinkState = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, + NVLDL, _NVLDL_TOP , _LINK_STATE); + nvldlTopIntr = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, + NVLDL, _NVLDL_TOP , _INTR); + + nvswitch_minion_get_ali_debug_registers_ls10(device, link, ¶ms); + + NVSWITCH_PRINT(device, ERROR, + "%s: Ali Training failed on link #%d!:\n" + "NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST = 0x%x, " + "NV_NVLDL_RXSLSM_ERR_CNTL = 0x%x,\n" + "NV_NVLDL_TOP_LINK_STATE = 0x%x,\n" + "NV_NVLDL_TOP_INTR = 0x%x,\n" + "Minion DLSTAT MN00 = 0x%x\n" + "Minion DLSTAT UC01 = 0x%x\n" + "Minion DLSTAT UC01 = 0x%x\n", + __FUNCTION__, link->linkNumber, + linkStateRequest, + nvldlErrCntl, nvldlTopLinkState, nvldlTopIntr, + params.dlstatMn00, params.dlstatUc01, params.dlstatLinkIntr); + + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_NVLIPT_LNK_ALI_TRAINING_FAIL, + "ALI Training failure. Info 0x%x%x%x%x%x%x%x\n", + params.dlstatMn00, params.dlstatUc01, params.dlstatLinkIntr, + nvldlTopLinkState, nvldlTopIntr, nvldlErrCntl, linkStateRequest); + } + return status; +} + +static NvlStatus +_nvswitch_init_dl_pll +( + nvlink_link *link +) +{ + nvswitch_device *device = link->dev->pDevInfo; + NvlStatus status; + + status = nvswitch_minion_send_command(device, link->linkNumber, NV_MINION_NVLINK_DL_CMD_COMMAND_INITPLL, 0); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: INITPLL failed for link %d.\n", + __FUNCTION__, link->linkNumber); + NVSWITCH_ASSERT_INFO(NV_ERR_NVLINK_CLOCK_ERROR, NVBIT64(link->linkNumber), INITPLL_ERROR); + return NV_ERR_NVLINK_CLOCK_ERROR; + } + + status = nvswitch_minion_send_command(device, link->linkNumber, NV_MINION_NVLINK_DL_CMD_COMMAND_INITPHY, 0); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: INITPHY failed for link %d.\n", + __FUNCTION__, link->linkNumber); + NVSWITCH_ASSERT_INFO(NV_ERR_NVLINK_INIT_ERROR, NVBIT64(link->linkNumber), INITPHY_ERROR); + return NV_ERR_NVLINK_INIT_ERROR; + } + + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_corelib_set_tx_mode_ls10 +( + nvlink_link *link, + NvU64 mode, + NvU32 flags +) +{ + nvswitch_device *device = link->dev->pDevInfo; + NvU32 val; + NvlStatus status = NVL_SUCCESS; + + if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLDL, link->linkNumber)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: link #%d invalid\n", + __FUNCTION__, link->linkNumber); + return -NVL_UNBOUND_DEVICE; + } + + // check if link is in reset + if (nvswitch_is_link_in_reset(device, link)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: link #%d is still in reset, cannot change sub-link state\n", + __FUNCTION__, link->linkNumber); + return -NVL_ERR_INVALID_STATE; + } + + val = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, NVLDL, _NVLDL_TX, _SLSM_STATUS_TX); + + // Check if Sublink State Machine is ready to accept a sublink change request. + status = nvswitch_poll_sublink_state(device, link); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s : SLSM not ready to accept a state change request for(%s):(%s).\n", + __FUNCTION__, device->name, link->linkName); + return status; + } + + switch (mode) + { + case NVLINK_SUBLINK_STATE_TX_COMMON_MODE: + { + val = _nvswitch_init_dl_pll(link); + if (val != NVL_SUCCESS) + { + return val; + } + + break; + } + + default: + { + status = nvswitch_corelib_set_tx_mode_lr10(link, mode, flags); + } + } + + return status; +} + +NvU32 +nvswitch_get_sublink_width_ls10 +( + nvswitch_device *device, + NvU32 linkNumber +) +{ + NvU32 data = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLIPT, + _NVLIPT_COMMON, _TOPOLOGY_LOCAL_LINK_CONFIGURATION); + return DRF_VAL(_NVLIPT_COMMON, _TOPOLOGY_LOCAL_LINK_CONFIGURATION, _NUM_LANES_PER_LINK, data); +} + +void +nvswitch_corelib_get_uphy_load_ls10 +( + nvlink_link *link, + NvBool *bUnlocked +) +{ + *bUnlocked = NV_FALSE; +} + +NvlStatus +nvswitch_corelib_set_dl_link_mode_ls10 +( + nvlink_link *link, + NvU64 mode, + NvU32 flags +) +{ + nvswitch_device *device = link->dev->pDevInfo; + NvU32 val; + NvlStatus status = NVL_SUCCESS; + NvBool keepPolling; + NVSWITCH_TIMEOUT timeout; + + if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLDL, link->linkNumber)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: link #%d invalid\n", + __FUNCTION__, link->linkNumber); + return -NVL_UNBOUND_DEVICE; + } + + switch (mode) + { + case NVLINK_LINKSTATE_INITPHASE1: + { + // Apply appropriate SIMMODE settings + status = nvswitch_minion_set_sim_mode_ls10(device, link); + if (status != NVL_SUCCESS) + { + return NV_ERR_NVLINK_CONFIGURATION_ERROR; + } + + // Apply appropriate SMF settings + status = nvswitch_minion_set_smf_settings_ls10(device, link); + if (status != NVL_SUCCESS) + { + return NV_ERR_NVLINK_CONFIGURATION_ERROR; + } + + // Apply appropriate UPHY Table settings + status = nvswitch_minion_select_uphy_tables_ls10(device, link); + if (status != NVL_SUCCESS) + { + return NV_ERR_NVLINK_CONFIGURATION_ERROR; + } + + // Before INITPHASE1, apply NEA setting + nvswitch_setup_link_loopback_mode(device, link->linkNumber); + + status = nvswitch_minion_send_command(device, link->linkNumber, + NV_MINION_NVLINK_DL_CMD_COMMAND_INITPHASE1, 0); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s : INITPHASE1 failed for link (%s):(%s).\n", + __FUNCTION__, device->name, link->linkName); + NVSWITCH_ASSERT_INFO(NV_ERR_NVLINK_CONFIGURATION_ERROR, + NVBIT64(link->linkNumber), INITPHASE1_ERROR); + return NV_ERR_NVLINK_CONFIGURATION_ERROR; + } + + break; + } + + case NVLINK_LINKSTATE_POST_INITOPTIMIZE: + { + // Poll for TRAINING_GOOD + status = nvswitch_minion_get_initoptimize_status_ls10(device, link->linkNumber); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s Error polling for INITOPTIMIZE TRAINING_GOOD. Link (%s):(%s)\n", + __FUNCTION__, device->name, link->linkName); + NVSWITCH_ASSERT_INFO(NV_ERR_NVLINK_TRAINING_ERROR, NVBIT64(link->linkNumber), INITOPTIMIZE_ERROR); + return NV_ERR_NVLINK_TRAINING_ERROR; + } + break; + } + + case NVLINK_LINKSTATE_INITTL: + { + status = nvswitch_minion_send_command(device, link->linkNumber, + NV_MINION_NVLINK_DL_CMD_COMMAND_INITTL, 0); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s : INITTL failed for link (%s):(%s).\n", + __FUNCTION__, device->name, link->linkName); + NVSWITCH_ASSERT_INFO(NV_ERR_NVLINK_TRAINING_ERROR, NVBIT64(link->linkNumber), INITTL_ERROR); + return NV_ERR_NVLINK_CONFIGURATION_ERROR; + } + break; + } + case NVLINK_LINKSTATE_INITOPTIMIZE: + { + return nvswitch_corelib_set_dl_link_mode_lr10(link, mode, flags); + } + + case NVLINK_LINKSTATE_INITPHASE5: + { + status = nvswitch_minion_send_command(device, link->linkNumber, + NV_MINION_NVLINK_DL_CMD_COMMAND_INITPHASE5A, 0); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s : INITPHASE5A failed to be called for link (%s):(%s).\n", + __FUNCTION__, device->name, link->linkName); + NVSWITCH_ASSERT_INFO(NV_ERR_NVLINK_TRAINING_ERROR, NVBIT64(link->linkNumber), INITPHASE5_ERROR); + return NV_ERR_NVLINK_CONFIGURATION_ERROR; + } + + nvswitch_timeout_create(10 * NVSWITCH_INTERVAL_1MSEC_IN_NS, &timeout); + + do + { + keepPolling = (nvswitch_timeout_check(&timeout)) ? NV_FALSE : NV_TRUE; + + val = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, NVLDL, _NVLPHYCTL_COMMON, _PSAVE_UCODE_CTRL_STS); + if(FLD_TEST_DRF(_NVLPHYCTL_COMMON, _PSAVE_UCODE_CTRL_STS, _PMSTS, _PSL0, val)) + { + break; + } + + if(!keepPolling) + { + NVSWITCH_PRINT(device, ERROR, + "%s : Failed to poll for L0 on link (%s):(%s).\n", + __FUNCTION__, device->name, link->linkName); + NVSWITCH_ASSERT_INFO(NV_ERR_NVLINK_TRAINING_ERROR, NVBIT64(link->linkNumber), INITPHASE5_ERROR); + return NV_ERR_NVLINK_CONFIGURATION_ERROR; + + } + } + while (keepPolling); + + break; + } + default: + { + status = nvswitch_corelib_set_dl_link_mode_lr10(link, mode, flags); + } + } + + return status; +} + +NvlStatus +nvswitch_corelib_get_rx_detect_ls10 +( + nvlink_link *link +) +{ + NvlStatus status; + nvswitch_device *device = link->dev->pDevInfo; + + status = nvswitch_minion_get_rxdet_status_ls10(device, link->linkNumber); + + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, WARN, + "%s: Get RXDET failed for link %d.\n", + __FUNCTION__, link->linkNumber); + return status; + } + return NVL_SUCCESS; +} + +void +nvswitch_reset_persistent_link_hw_state_ls10 +( + nvswitch_device *device, + NvU32 linkNumber +) +{ + NvU32 regData; + NvU32 nvliptWarmResetDelayUs = (IS_RTLSIM(device) || IS_EMULATION(device)) ? 800:8; + + regData = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLIPT_LNK, + _NVLIPT_LNK, _DEBUG_CLEAR); + regData = FLD_SET_DRF_NUM(_NVLIPT_LNK, _DEBUG_CLEAR, _CLEAR, + NV_NVLIPT_LNK_DEBUG_CLEAR_CLEAR_ASSERT, regData); + NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLIPT_LNK, + _NVLIPT_LNK, _DEBUG_CLEAR, regData); + + NVSWITCH_NSEC_DELAY(nvliptWarmResetDelayUs * NVSWITCH_INTERVAL_1USEC_IN_NS); + + regData = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLIPT_LNK, + _NVLIPT_LNK, _DEBUG_CLEAR); + regData = FLD_SET_DRF_NUM(_NVLIPT_LNK, _DEBUG_CLEAR, _CLEAR, + NV_NVLIPT_LNK_DEBUG_CLEAR_CLEAR_DEASSERT, regData); + NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLIPT_LNK, + _NVLIPT_LNK, _DEBUG_CLEAR, regData); + + NVSWITCH_NSEC_DELAY(nvliptWarmResetDelayUs * NVSWITCH_INTERVAL_1USEC_IN_NS); + +} + +NvlStatus +nvswitch_corelib_get_tl_link_mode_ls10 +( + nvlink_link *link, + NvU64 *mode +) +{ +#if defined(INCLUDE_NVLINK_LIB) + + nvswitch_device *device = link->dev->pDevInfo; + NvU32 link_state; + NvU32 val = 0; + NvlStatus status = NVL_SUCCESS; + + *mode = NVLINK_LINKSTATE_OFF; + + if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLDL, link->linkNumber)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: link #%d invalid\n", + __FUNCTION__, link->linkNumber); + return -NVL_UNBOUND_DEVICE; + } + + // check if links are in reset + if (nvswitch_is_link_in_reset(device, link)) + { + *mode = NVLINK_LINKSTATE_RESET; + return NVL_SUCCESS; + } + + // Read state from NVLIPT HW + val = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, NVLIPT_LNK, + _NVLIPT_LNK, _CTRL_LINK_STATE_STATUS); + + link_state = DRF_VAL(_NVLIPT_LNK, _CTRL_LINK_STATE_STATUS, _CURRENTLINKSTATE, + val); + + switch(link_state) + { + case NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_CURRENTLINKSTATE_ACTIVE: + + // If using ALI, ensure that the request to active completed + if (link->dev->enableALI) + { + status = nvswitch_wait_for_tl_request_ready_ls10(link); + } + + *mode = (status == NVL_SUCCESS) ? NVLINK_LINKSTATE_HS:NVLINK_LINKSTATE_OFF; + break; + + case NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_CURRENTLINKSTATE_L2: + *mode = NVLINK_LINKSTATE_SLEEP; + break; + + case NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_CURRENTLINKSTATE_CONTAIN: + *mode = NVLINK_LINKSTATE_CONTAIN; + break; + + case NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_CURRENTLINKSTATE_ACTIVE_PENDING: + *mode = NVLINK_LINKSTATE_ACTIVE_PENDING; + break; + + default: + // Currently, only ACTIVE, L2 and CONTAIN states are supported + return NVL_ERR_INVALID_STATE; + break; + } + +#endif + + return status; +} + +NvBool +nvswitch_is_link_in_reset_ls10 +( + nvswitch_device *device, + nvlink_link *link +) +{ + NvU32 clkStatus; + NvU32 resetRequestStatus; + + clkStatus = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, + NVLIPT_LNK, _NVLIPT_LNK, _CTRL_CLK_CTRL); + + // Read the reset request register + resetRequestStatus = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, + NVLIPT_LNK, _NVLIPT_LNK, _RESET_RSTSEQ_LINK_RESET); + + // + // For link to be in reset either of 2 conditions should be true + // 1. On a cold-boot the RESET_RSTSEQ status should be ASSERTED reset + // 2. A link's current TL link state should be _RESET + // and all of the per link clocks, RXCLK, TXCLK and NCISOCCLK, should be off + // + if ((DRF_VAL(_NVLIPT_LNK, _RESET_RSTSEQ_LINK_RESET, _LINK_RESET_STATUS, resetRequestStatus) == + NV_NVLIPT_LNK_RESET_RSTSEQ_LINK_RESET_LINK_RESET_STATUS_ASSERTED) || + (FLD_TEST_DRF(_NVLIPT_LNK, _CTRL_CLK_CTRL, _RXCLK_STS, _OFF, clkStatus) && + FLD_TEST_DRF(_NVLIPT_LNK, _CTRL_CLK_CTRL, _TXCLK_STS, _OFF, clkStatus) && + FLD_TEST_DRF(_NVLIPT_LNK, _CTRL_CLK_CTRL, _NCISOCCLK_STS, _OFF, clkStatus))) + { + return NV_TRUE; + } + + return NV_FALSE; +} + +void +nvswitch_init_buffer_ready_ls10 +( + nvswitch_device *device, + nvlink_link *link, + NvBool bNportBufferReady +) +{ + NvU32 val; + NvU32 linkNum = link->linkNumber; + NvU64 forcedConfigLinkMask; + NvU32 localLinkNumber = linkNum % NVSWITCH_LINKS_PER_MINION_LS10; + NvU32 regData; + regData = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, + NVLTLC, _NVLTLC_TX_SYS, _CTRL_BUFFER_READY); + + // If buffer ready is set then return + if (FLD_TEST_DRF(_NVLTLC, _TX_SYS_CTRL_BUFFER_READY, _BUFFERRDY, _ENABLE, regData)) + { + return; + } + + forcedConfigLinkMask = ((NvU64)device->regkeys.chiplib_forced_config_link_mask) + + ((NvU64)device->regkeys.chiplib_forced_config_link_mask2 << 32); + + // + // Use legacy LS10 function to set buffer ready if + // running with forced config since MINION is not + // booted + // + if (forcedConfigLinkMask != 0) + { + nvswitch_init_buffer_ready_lr10(device, link, bNportBufferReady); + } + + if (FLD_TEST_DRF(_SWITCH_REGKEY, _SKIP_BUFFER_READY, _TLC, _NO, + device->regkeys.skip_buffer_ready)) + { + NVSWITCH_MINION_WR32_LS10(device, + NVSWITCH_GET_LINK_ENG_INST(device, linkNum, MINION), + _MINION, _NVLINK_DL_CMD_DATA(localLinkNumber), + NV_MINION_NVLINK_DL_CMD_DATA_DATA_SET_BUFFER_READY_TX_AND_RX); + + nvswitch_minion_send_command(device, linkNum, + NV_MINION_NVLINK_DL_CMD_COMMAND_SET_BUFFER_READY, 0); + } + + if (bNportBufferReady && + FLD_TEST_DRF(_SWITCH_REGKEY, _SKIP_BUFFER_READY, _NPORT, _NO, + device->regkeys.skip_buffer_ready)) + { + val = DRF_NUM(_NPORT, _CTRL_BUFFER_READY, _BUFFERRDY, 0x1); + NVSWITCH_LINK_WR32_LS10(device, linkNum, NPORT, _NPORT, _CTRL_BUFFER_READY, val); + } +} + +void +nvswitch_apply_recal_settings_ls10 +( + nvswitch_device *device, + nvlink_link *link +) +{ + NvU32 linkNumber = link->linkNumber; + NvU32 regVal; + NvU32 settingVal; + + // If no recal settings are set then return early + if (device->regkeys.link_recal_settings == NV_SWITCH_REGKEY_LINK_RECAL_SETTINGS_NOP) + { + return; + } + + regVal = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLIPT_LNK, _NVLIPT_LNK, + _CTRL_SYSTEM_LINK_CHANNEL_CTRL2); + + settingVal = DRF_VAL(_SWITCH_REGKEY, _LINK_RECAL_SETTINGS, _MIN_RECAL_TIME_MANTISSA, + device->regkeys.link_recal_settings); + if (settingVal != NV_SWITCH_REGKEY_LINK_RECAL_SETTINGS_NOP) + { + regVal = FLD_SET_DRF_NUM(_NVLIPT_LNK, _CTRL_SYSTEM_LINK_CHANNEL_CTRL2, + _L1_MINIMUM_RECALIBRATION_TIME_MANTISSA, settingVal, regVal); + } + + settingVal = DRF_VAL(_SWITCH_REGKEY, _LINK_RECAL_SETTINGS, _MIN_RECAL_TIME_EXPONENT, + device->regkeys.link_recal_settings); + if (settingVal != NV_SWITCH_REGKEY_LINK_RECAL_SETTINGS_NOP) + { + regVal = FLD_SET_DRF_NUM(_NVLIPT_LNK, _CTRL_SYSTEM_LINK_CHANNEL_CTRL2, + _L1_MINIMUM_RECALIBRATION_TIME_EXPONENT, 0x2, regVal); + } + + settingVal = DRF_VAL(_SWITCH_REGKEY, _LINK_RECAL_SETTINGS, _MAX_RECAL_PERIOD_MANTISSA, + device->regkeys.link_recal_settings); + if (settingVal != NV_SWITCH_REGKEY_LINK_RECAL_SETTINGS_NOP) + { + regVal = FLD_SET_DRF_NUM(_NVLIPT_LNK, _CTRL_SYSTEM_LINK_CHANNEL_CTRL2, + _L1_MAXIMUM_RECALIBRATION_PERIOD_MANTISSA, 0xf, regVal); + } + + settingVal = DRF_VAL(_SWITCH_REGKEY, _LINK_RECAL_SETTINGS, _MAX_RECAL_PERIOD_EXPONENT, + device->regkeys.link_recal_settings); + if (settingVal != NV_SWITCH_REGKEY_LINK_RECAL_SETTINGS_NOP) + { + regVal = FLD_SET_DRF_NUM(_NVLIPT_LNK, _CTRL_SYSTEM_LINK_CHANNEL_CTRL2, + _L1_MAXIMUM_RECALIBRATION_PERIOD_EXPONENT, 0x3, regVal); + } + + NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLIPT_LNK, _NVLIPT_LNK, + _CTRL_SYSTEM_LINK_CHANNEL_CTRL2, regVal); + + return; +} + +NvlStatus +nvswitch_corelib_get_dl_link_mode_ls10 +( + nvlink_link *link, + NvU64 *mode +) +{ + nvswitch_device *device = link->dev->pDevInfo; + NvU32 link_state; + NvU32 val = 0; + NvU64 tlLinkMode; + + *mode = NVLINK_LINKSTATE_OFF; + + if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLDL, link->linkNumber)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: link #%d invalid\n", + __FUNCTION__, link->linkNumber); + return -NVL_UNBOUND_DEVICE; + } + + // check if links are in reset + if (nvswitch_is_link_in_reset(device, link)) + { + *mode = NVLINK_LINKSTATE_RESET; + return NVL_SUCCESS; + } + + val = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, NVLDL, _NVLDL_TOP, _LINK_STATE); + + link_state = DRF_VAL(_NVLDL_TOP, _LINK_STATE, _STATE, val); + + switch (link_state) + { + case NV_NVLDL_TOP_LINK_STATE_STATE_INIT: + *mode = NVLINK_LINKSTATE_OFF; + break; + case NV_NVLDL_TOP_LINK_STATE_STATE_HWPCFG: + case NV_NVLDL_TOP_LINK_STATE_STATE_HWCFG: + *mode = NVLINK_LINKSTATE_DETECT; + break; + case NV_NVLDL_TOP_LINK_STATE_STATE_SWCFG: + *mode = NVLINK_LINKSTATE_SAFE; + break; + case NV_NVLDL_TOP_LINK_STATE_STATE_ACTIVE: + *mode = NVLINK_LINKSTATE_HS; + break; + case NV_NVLDL_TOP_LINK_STATE_STATE_SLEEP: + if (device->hal.nvswitch_corelib_get_tl_link_mode(link, &tlLinkMode) != NVL_SUCCESS || + tlLinkMode == NVLINK_LINKSTATE_SLEEP) + { + *mode = NVLINK_LINKSTATE_SLEEP; + } + else + { + *mode = NVLINK_LINKSTATE_HS; + } + break; + case NV_NVLDL_TOP_LINK_STATE_STATE_FAULT: + *mode = NVLINK_LINKSTATE_FAULT; + break; + case NV_NVLDL_TOP_LINK_STATE_STATE_RCVY_AC: + case NV_NVLDL_TOP_LINK_STATE_STATE_RCVY_RX: + *mode = NVLINK_LINKSTATE_RECOVERY; + break; + default: + *mode = NVLINK_LINKSTATE_OFF; + break; + } + + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_corelib_get_rx_mode_ls10 +( + nvlink_link *link, + NvU64 *mode, + NvU32 *subMode +) +{ + nvswitch_device *device = link->dev->pDevInfo; + NvU32 rx_sublink_state; + NvU32 data = 0; + NvU64 dlLinkMode; + *mode = NVLINK_SUBLINK_STATE_RX_OFF; + + if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLDL, link->linkNumber)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: link #%d invalid\n", + __FUNCTION__, link->linkNumber); + return -NVL_UNBOUND_DEVICE; + } + + // check if link is in reset + if (nvswitch_is_link_in_reset(device, link)) + { + *mode = NVLINK_SUBLINK_STATE_RX_OFF; + return NVL_SUCCESS; + } + + data = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, NVLDL, _NVLDL_RX, _SLSM_STATUS_RX); + + rx_sublink_state = DRF_VAL(_NVLDL_RX, _SLSM_STATUS_RX, _PRIMARY_STATE, data); + + // Return NVLINK_SUBLINK_SUBSTATE_RX_STABLE for sub-state + *subMode = NVLINK_SUBLINK_SUBSTATE_RX_STABLE; + + switch (rx_sublink_state) + { + case NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_HS: + *mode = NVLINK_SUBLINK_STATE_RX_HS; + break; + + case NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_TRAIN: + *mode = NVLINK_SUBLINK_STATE_RX_TRAIN; + break; + + case NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_SAFE: + *mode = NVLINK_SUBLINK_STATE_RX_SAFE; + break; + case NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_OFF: + if (device->hal.nvswitch_corelib_get_dl_link_mode(link, &dlLinkMode) != NVL_SUCCESS || + dlLinkMode != NVLINK_LINKSTATE_HS) + { + *mode = NVLINK_SUBLINK_STATE_RX_OFF; + } + else + { + *mode = NVLINK_SUBLINK_STATE_RX_LOW_POWER; + } + break; + + default: + *mode = NVLINK_SUBLINK_STATE_RX_OFF; + break; + } + + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_corelib_get_tx_mode_ls10 +( + nvlink_link *link, + NvU64 *mode, + NvU32 *subMode +) +{ + nvswitch_device *device = link->dev->pDevInfo; + NvU32 tx_sublink_state; + NvU64 dlLinkMode; + NvU32 data = 0; + + *mode = NVLINK_SUBLINK_STATE_TX_OFF; + + if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLDL, link->linkNumber)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: link #%d invalid\n", + __FUNCTION__, link->linkNumber); + return -NVL_UNBOUND_DEVICE; + } + + // check if link is in reset + if (nvswitch_is_link_in_reset(device, link)) + { + *mode = NVLINK_SUBLINK_STATE_TX_OFF; + return NVL_SUCCESS; + } + + data = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, NVLDL, _NVLDL_TX, _SLSM_STATUS_TX); + + tx_sublink_state = DRF_VAL(_NVLDL_TX, _SLSM_STATUS_TX, _PRIMARY_STATE, data); + + // Return NVLINK_SUBLINK_SUBSTATE_TX_STABLE for sub-state + *subMode = NVLINK_SUBLINK_SUBSTATE_TX_STABLE; + + switch (tx_sublink_state) + { + case NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_HS: + *mode = NVLINK_SUBLINK_STATE_TX_HS; + break; + + case NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_TRAIN: + *mode = NVLINK_SUBLINK_STATE_TX_TRAIN; + break; + + case NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_SAFE: + *mode = NVLINK_SUBLINK_STATE_TX_SAFE; + break; + + case NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_OFF: + if (device->hal.nvswitch_corelib_get_dl_link_mode(link, &dlLinkMode) != NVL_SUCCESS || + dlLinkMode != NVLINK_LINKSTATE_HS) + { + *mode = NVLINK_SUBLINK_STATE_TX_OFF; + } + else + { + *mode = NVLINK_SUBLINK_STATE_TX_LOW_POWER; + } + break; + + default: + *mode = NVLINK_SUBLINK_STATE_TX_OFF; + break; + } + + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_launch_ALI_link_training_ls10 +( + nvswitch_device *device, + nvlink_link *link, + NvBool bSync +) +{ + NvlStatus status = NVL_SUCCESS; + + if ((link == NULL) || + !NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLIPT_LNK, link->linkNumber) || + (link->linkNumber >= NVSWITCH_NVLINK_MAX_LINKS)) + { + return -NVL_UNBOUND_DEVICE; + } + + if (!nvswitch_is_link_in_reset(device, link)) + { + return NVL_SUCCESS; + } + + NVSWITCH_PRINT(device, INFO, + "%s: ALI launching on link: 0x%x\n", + __FUNCTION__, link->linkNumber); + + // Apply appropriate SIMMODE settings + status = nvswitch_minion_set_sim_mode_ls10(device, link); + if (status != NVL_SUCCESS) + { + return NV_ERR_NVLINK_CONFIGURATION_ERROR; + } + + // Apply appropriate SMF settings + status = nvswitch_minion_set_smf_settings_ls10(device, link); + if (status != NVL_SUCCESS) + { + return NV_ERR_NVLINK_CONFIGURATION_ERROR; + } + + // Apply appropriate UPHY Table settings + status = nvswitch_minion_select_uphy_tables_ls10(device, link); + if (status != NVL_SUCCESS) + { + return NV_ERR_NVLINK_CONFIGURATION_ERROR; + } + + // Before INITPHASE1, apply NEA setting + nvswitch_setup_link_loopback_mode(device, link->linkNumber); + + // + // Request active, but don't block. FM will come back and check + // active link status by blocking on this TLREQ's completion + // + status = nvswitch_request_tl_link_state_ls10(link, + NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_ACTIVE, + bSync); + + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: TL link state request to active for ALI failed for link: 0x%x\n", + __FUNCTION__, link->linkNumber); + } + + return status; +} + +void +nvswitch_store_topology_information_ls10 +( + nvswitch_device *device, + nvlink_link *link +) +{ + NvU32 tempval; + + link->bInitnegotiateConfigGood = NV_TRUE; + link->remoteSid = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, NVLIPT_LNK, + _NVLIPT_LNK, _TOPOLOGY_REMOTE_CHIP_SID_HI); + link->remoteSid = link->remoteSid << 32; + link->remoteSid |= NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, NVLIPT_LNK, + _NVLIPT_LNK, _TOPOLOGY_REMOTE_CHIP_SID_LO); + + tempval = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, NVLIPT_LNK, _NVLIPT_LNK, _TOPOLOGY_REMOTE_LINK_INFO); + link->remoteLinkId = DRF_VAL(_NVLIPT_LNK, _TOPOLOGY_REMOTE_LINK_INFO, _LINK_NUMBER, tempval); + + link->localSid = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, NVLIPT, + _NVLIPT_COMMON, _TOPOLOGY_LOCAL_CHIP_SID_HI); + link->localSid = link->localSid << 32; + link->localSid |= NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, NVLIPT, + _NVLIPT_COMMON, _TOPOLOGY_LOCAL_CHIP_SID_LO); + + tempval = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, NVLIPT_LNK, + _NVLIPT_LNK, _TOPOLOGY_REMOTE_CHIP_TYPE); + + // Update the remoteDeviceType with NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE values. + switch(tempval) + { + case NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE_NV3P0AMP: + case NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE_NV4P0HOP: + link->remoteDeviceType = NVSWITCH_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU; + break; + case NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE_NV3P0LRK: + case NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE_NV4P0LAG: + link->remoteDeviceType = NVSWITCH_NVLINK_DEVICE_INFO_DEVICE_TYPE_SWITCH; + break; + default: + link->remoteDeviceType = NVSWITCH_NVLINK_DEVICE_INFO_DEVICE_TYPE_NONE; + break; + } +} + +void +nvswitch_init_dlpl_interrupts_ls10 +( + nvlink_link *link +) +{ + nvswitch_device *device = link->dev->pDevInfo; + NvU32 linkNumber = link->linkNumber; + NvU32 intrRegVal; + NvU32 crcRegVal; + NvU32 shortRateMask; + NvU32 crcShortRegkeyVal = device->regkeys.crc_bit_error_rate_short; + + ct_assert(DRF_BASE(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN) == + DRF_BASE(NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_THRESHOLD_MAN)); + ct_assert(DRF_EXTENT(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN) == + DRF_EXTENT(NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_THRESHOLD_MAN)); + ct_assert(DRF_BASE(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP) == + DRF_BASE(NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_THRESHOLD_EXP)); + ct_assert(DRF_EXTENT(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP) == + DRF_EXTENT(NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_THRESHOLD_EXP)); + ct_assert(DRF_BASE(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_MAN) == + DRF_BASE(NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_TIMESCALE_MAN)); + ct_assert(DRF_EXTENT(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_MAN) == + DRF_EXTENT(NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_TIMESCALE_MAN)); + ct_assert(DRF_BASE(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP) == + DRF_BASE(NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_TIMESCALE_EXP)); + ct_assert(DRF_EXTENT(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP) == + DRF_EXTENT(NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_TIMESCALE_EXP)); + + // W1C any stale state. + NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, _NVLDL_TOP, _INTR, 0xffffffff); + NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, _NVLDL_TOP, _INTR_SW2, 0xffffffff); + + // Stall tree routes to INTR_A which is connected to NVLIPT fatal tree + + NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, _NVLDL_TOP, _INTR_STALL_EN, + DRF_DEF(_NVLDL_TOP, _INTR_STALL_EN, _TX_REPLAY, _DISABLE) | + DRF_DEF(_NVLDL_TOP, _INTR_STALL_EN, _TX_RECOVERY_SHORT, _DISABLE) | + DRF_DEF(_NVLDL_TOP, _INTR_STALL_EN, _LTSSM_FAULT_UP, _ENABLE) | + DRF_DEF(_NVLDL_TOP, _INTR_STALL_EN, _TX_FAULT_RAM, _ENABLE) | + DRF_DEF(_NVLDL_TOP, _INTR_STALL_EN, _TX_FAULT_INTERFACE, _ENABLE) | + DRF_DEF(_NVLDL_TOP, _INTR_STALL_EN, _TX_FAULT_SUBLINK_CHANGE, _DISABLE) | + DRF_DEF(_NVLDL_TOP, _INTR_STALL_EN, _RX_FAULT_SUBLINK_CHANGE, _DISABLE) | + DRF_DEF(_NVLDL_TOP, _INTR_STALL_EN, _RX_FAULT_DL_PROTOCOL, _ENABLE) | + DRF_DEF(_NVLDL_TOP, _INTR_STALL_EN, _RX_SHORT_ERROR_RATE, _DISABLE) | + DRF_DEF(_NVLDL_TOP, _INTR_STALL_EN, _RX_ILA_TRIGGER, _DISABLE) | + DRF_DEF(_NVLDL_TOP, _INTR_STALL_EN, _RX_CRC_COUNTER, _DISABLE) | + DRF_DEF(_NVLDL_TOP, _INTR_STALL_EN, _LTSSM_PROTOCOL, _DISABLE) | + DRF_DEF(_NVLDL_TOP, _INTR_STALL_EN, _MINION_REQUEST, _DISABLE)); + + // NONSTALL -> NONFATAL + NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, _NVLDL_TOP, _INTR_NONSTALL_EN, + DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _TX_REPLAY, _DISABLE) | + DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _TX_RECOVERY_SHORT, _DISABLE) | + DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _LTSSM_FAULT_UP, _DISABLE) | + DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _TX_FAULT_RAM, _DISABLE) | + DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _TX_FAULT_INTERFACE, _DISABLE) | + DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _TX_FAULT_SUBLINK_CHANGE, _DISABLE) | + DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_FAULT_SUBLINK_CHANGE, _DISABLE) | + DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_FAULT_DL_PROTOCOL, _DISABLE) | + DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_SHORT_ERROR_RATE, _DISABLE) | + DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_ILA_TRIGGER, _DISABLE) | + DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_CRC_COUNTER, _ENABLE) | + DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _LTSSM_PROTOCOL, _DISABLE) | + DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _MINION_REQUEST, _DISABLE)); + + intrRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL, + _NVLDL_TOP, _INTR_NONSTALL_EN); + crcRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL, + _NVLDL_RX, _ERROR_RATE_CTRL); + + // + // Enable RX error rate short interrupt. + // Please refer to Bug 3365481 for details about the CRC_BIT_ERROR_RATE_SHORT + // values used below. + // + + // Enable RX error rate short interrupt if the regkey is set + if (crcShortRegkeyVal != NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_DEFAULT) + { + shortRateMask = DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN) | + DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP) | + DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_MAN) | + DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP); + + intrRegVal |= DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_SHORT_ERROR_RATE, _ENABLE); + crcRegVal &= ~shortRateMask; + crcRegVal |= crcShortRegkeyVal; + } + else + { + shortRateMask = DRF_SHIFTMASK(NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN) | + DRF_SHIFTMASK(NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP) | + DRF_SHIFTMASK(NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_MAN) | + DRF_SHIFTMASK(NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP); + + intrRegVal |= DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_SHORT_ERROR_RATE, _ENABLE); + crcRegVal &= ~shortRateMask; + } + + NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, + _NVLDL_TOP, _INTR_NONSTALL_EN, intrRegVal); + NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, + _NVLDL_RX, _ERROR_RATE_CTRL, crcRegVal); +} + +static NvU32 +_nvswitch_get_nvlink_linerate_ls10 +( + nvswitch_device *device, + NvU32 val +) +{ + NvU32 lineRate = 0; + switch (val) + { + case NV_SWITCH_REGKEY_SPEED_CONTROL_SPEED_100_00000G: + lineRate = NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_100_00000_GBPS; + break; + case NV_SWITCH_REGKEY_SPEED_CONTROL_SPEED_106_25000G: + lineRate = NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_106_25000_GBPS; + break; + default: + NVSWITCH_PRINT(device, SETUP, "%s:ERROR LINE_RATE = 0x%x requested by regkey\n", + __FUNCTION__, lineRate); + lineRate = NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_ILLEGAL_LINE_RATE; + } + return lineRate; +} + +void +nvswitch_setup_link_system_registers_ls10 +( + nvswitch_device *device, + nvlink_link *link +) +{ + NvU32 regval, fldval; + NvU32 lineRate = 0; + + // LINE_RATE SYSTEM register + if (device->regkeys.nvlink_speed_control != NV_SWITCH_REGKEY_SPEED_CONTROL_SPEED_DEFAULT) + { + regval = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, NVLIPT_LNK, + _NVLIPT_LNK_CTRL_SYSTEM_LINK, _CLK_CTRL); + lineRate = _nvswitch_get_nvlink_linerate_ls10(device, device->regkeys.nvlink_speed_control); + regval = FLD_SET_DRF_NUM(_NVLIPT_LNK_CTRL_SYSTEM_LINK, _CLK_CTRL, + _LINE_RATE, lineRate, regval); + NVSWITCH_PRINT(device, SETUP, "%s: LINE_RATE = 0x%x requested by regkey\n", + __FUNCTION__, lineRate); + NVSWITCH_LINK_WR32_LS10(device, link->linkNumber, NVLIPT_LNK, + _NVLIPT_LNK_CTRL_SYSTEM_LINK, _CLK_CTRL, regval); + } + + // TXTRAIN SYSTEM register + regval = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, NVLIPT_LNK, + _NVLIPT_LNK_CTRL_SYSTEM_LINK, _CHANNEL_CTRL); + + fldval = DRF_VAL(_SWITCH_REGKEY, _TXTRAIN_CONTROL, _FOM_FORMAT, + device->regkeys.txtrain_control); + if (fldval != NV_SWITCH_REGKEY_TXTRAIN_CONTROL_FOM_FORMAT_NOP) + { + NVSWITCH_PRINT(device, SETUP, "%s: FOM_FORMAT = 0x%x requested by regkey\n", + __FUNCTION__, fldval); + regval = FLD_SET_DRF_NUM(_NVLIPT_LNK_CTRL_SYSTEM_LINK, _CHANNEL_CTRL, + _TXTRAIN_FOM_FORMAT, fldval, regval); + } + + fldval = DRF_VAL(_SWITCH_REGKEY, _TXTRAIN_CONTROL, _OPTIMIZATION_ALGORITHM, + device->regkeys.txtrain_control); + if (fldval != NV_SWITCH_REGKEY_TXTRAIN_CONTROL_OPTIMIZATION_ALGORITHM_NOP) + { + NVSWITCH_PRINT(device, SETUP, "%s: OPTIMIZATION_ALGORITHM = 0x%x requested by regkey\n", + __FUNCTION__, fldval); + regval = FLD_SET_DRF_NUM(_NVLIPT_LNK_CTRL_SYSTEM_LINK, _CHANNEL_CTRL, + _TXTRAIN_OPTIMIZATION_ALGORITHM, fldval, regval); + } + + fldval = DRF_VAL(_SWITCH_REGKEY, _TXTRAIN_CONTROL, _ADJUSTMENT_ALGORITHM, + device->regkeys.txtrain_control); + if (fldval != NV_SWITCH_REGKEY_TXTRAIN_CONTROL_ADJUSTMENT_ALGORITHM_NOP) + { + NVSWITCH_PRINT(device, SETUP, "%s: ADJUSTMENT_ALGORITHM = 0x%x requested by regkey\n", + __FUNCTION__, fldval); + regval = FLD_SET_DRF_NUM(_NVLIPT_LNK_CTRL_SYSTEM_LINK, _CHANNEL_CTRL, + _TXTRAIN_ADJUSTMENT_ALGORITHM, fldval, regval); + } + + fldval = DRF_VAL(_SWITCH_REGKEY, _TXTRAIN_CONTROL, _MINIMUM_TRAIN_TIME_MANTISSA, + device->regkeys.txtrain_control); + if (fldval != NV_SWITCH_REGKEY_TXTRAIN_CONTROL_MINIMUM_TRAIN_TIME_MANTISSA_NOP) + { + NVSWITCH_PRINT(device, SETUP, "%s: MINIMUM_TRAIN_TIME_MANTISSA = 0x%x requested by regkey\n", + __FUNCTION__, fldval); + regval = FLD_SET_DRF_NUM(_NVLIPT_LNK_CTRL_SYSTEM_LINK, _CHANNEL_CTRL, + _TXTRAIN_MINIMUM_TRAIN_TIME_MANTISSA, fldval, regval); + } + + fldval = DRF_VAL(_SWITCH_REGKEY, _TXTRAIN_CONTROL, _MINIMUM_TRAIN_TIME_EXPONENT, + device->regkeys.txtrain_control); + if (fldval != NV_SWITCH_REGKEY_TXTRAIN_CONTROL_MINIMUM_TRAIN_TIME_EXPONENT_NOP) + { + NVSWITCH_PRINT(device, SETUP, "%s: MINIMUM_TRAIN_TIME_EXPONENT = 0x%x requested by regkey\n", + __FUNCTION__, fldval); + regval = FLD_SET_DRF_NUM(_NVLIPT_LNK_CTRL_SYSTEM_LINK, _CHANNEL_CTRL, + _TXTRAIN_MINIMUM_TRAIN_TIME_EXPONENT, fldval, regval); + } + + NVSWITCH_LINK_WR32_LS10(device, link->linkNumber, NVLIPT_LNK, + _NVLIPT_LNK_CTRL_SYSTEM_LINK, _CHANNEL_CTRL, regval); + + nvswitch_apply_recal_settings(device, link); + + return; +} + +void +nvswitch_load_link_disable_settings_ls10 +( + nvswitch_device *device, + nvlink_link *link +) +{ + NvU32 regVal; + + // Read state from NVLIPT HW + regVal = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, NVLIPT_LNK, + _NVLIPT_LNK, _CTRL_LINK_STATE_STATUS); + + if (FLD_TEST_DRF(_NVLIPT_LNK, _CTRL_LINK_STATE_STATUS, _CURRENTLINKSTATE, _DISABLE, regVal)) + { + + // Set link to invalid and unregister from corelib + device->link[link->linkNumber].valid = NV_FALSE; + nvlink_lib_unregister_link(link); + nvswitch_destroy_link(link); + } + + return; +} + +void +nvswitch_execute_unilateral_link_shutdown_ls10 +( + nvlink_link *link +) +{ + nvswitch_device *device = link->dev->pDevInfo; + NvlStatus status = NVL_SUCCESS; + NvU32 retry_count = 3; + NvU32 link_state_request; + NvU32 link_state; + NvU32 stat_data; + NvU32 link_intr_subcode; + + if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLDL, link->linkNumber)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: link #%d invalid\n", + __FUNCTION__, link->linkNumber); + return; + } + + do + { + // + // Perform unilateral shutdown + // This follows "Unilateral variant" from NVLink 4.x Shutdown + // + // Status is explicitly ignored here since we are required to soldier-on + // in this scenario + // + status = nvswitch_request_tl_link_state_lr10(link, + NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_SHUTDOWN, NV_TRUE); + + if (status == NVL_SUCCESS) + { + return; + } + + + link_state_request = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, + NVLIPT_LNK , _NVLIPT_LNK , _CTRL_LINK_STATE_REQUEST); + + link_state = DRF_VAL(_NVLIPT_LNK, _CTRL_LINK_STATE_REQUEST, _STATUS, link_state_request); + + if (nvswitch_minion_get_dl_status(device, link->linkNumber, + NV_NVLSTAT_MN00, 0, &stat_data) == NVL_SUCCESS) + { + link_intr_subcode = DRF_VAL(_NVLSTAT, _MN00, _LINK_INTR_SUBCODE, stat_data); + } + + if ((link_state == NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_MINION_REQUEST_FAIL) && + (link_intr_subcode == MINION_ALARM_BUSY)) + { + NVSWITCH_PRINT(device, INFO, + "%s: Retrying shutdown due to Minion DLCMD Fault subcode = 0x%x\n", + __FUNCTION__, link_intr_subcode); + // + // We retry the shutdown sequence 3 times when we see a MINION_REQUEST_FAIL + // or MINION_ALARM_BUSY + // + retry_count--; + } + else + { + break; + } + + } while (retry_count); + + NVSWITCH_PRINT(device, ERROR, + "%s: NvLink Shutdown has failed for link %d\n", + __FUNCTION__, link->linkNumber); + + return; +} + diff --git a/src/common/nvswitch/kernel/ls10/ls10.c b/src/common/nvswitch/kernel/ls10/ls10.c new file mode 100644 index 000000000..97297d94b --- /dev/null +++ b/src/common/nvswitch/kernel/ls10/ls10.c @@ -0,0 +1,5624 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvlink_export.h" +#include "common_nvswitch.h" +#include "error_nvswitch.h" +#include "regkey_nvswitch.h" +#include "haldef_nvswitch.h" +#include "nvlink_inband_msg.h" + +#include "ls10/ls10.h" +#include "lr10/lr10.h" +#include "ls10/clock_ls10.h" +#include "ls10/inforom_ls10.h" +#include "ls10/minion_ls10.h" +#include "ls10/pmgr_ls10.h" +#include "ls10/therm_ls10.h" +#include "ls10/smbpbi_ls10.h" +#include "ls10/multicast_ls10.h" +#include "ls10/soe_ls10.h" +#include "ls10/gfw_ls10.h" + +#include "nvswitch/ls10/dev_nvs_top.h" +#include "nvswitch/ls10/dev_pri_masterstation_ip.h" +#include "nvswitch/ls10/dev_pri_hub_sys_ip.h" +#include "nvswitch/ls10/dev_nvlw_ip.h" +#include "nvswitch/ls10/dev_nvlsaw_ip.h" +#include "nvswitch/ls10/dev_nvlsaw_ip_addendum.h" +#include "nvswitch/ls10/dev_nvltlc_ip.h" +#include "nvswitch/ls10/dev_nvldl_ip.h" +#include "nvswitch/ls10/dev_nport_ip.h" +#include "nvswitch/ls10/dev_route_ip.h" +#include "nvswitch/ls10/dev_nport_ip_addendum.h" +#include "nvswitch/ls10/dev_route_ip_addendum.h" +#include "nvswitch/ls10/dev_ingress_ip.h" +#include "nvswitch/ls10/dev_egress_ip.h" +#include "nvswitch/ls10/dev_tstate_ip.h" +#include "nvswitch/ls10/dev_sourcetrack_ip.h" +#include "nvswitch/ls10/dev_cpr_ip.h" +#include "nvswitch/ls10/dev_nvlipt_lnk_ip.h" +#include "nvswitch/ls10/dev_minion_ip.h" +#include "nvswitch/ls10/dev_minion_ip_addendum.h" +#include "nvswitch/ls10/dev_multicasttstate_ip.h" +#include "nvswitch/ls10/dev_reductiontstate_ip.h" +#include "ls10/minion_nvlink_defines_public_ls10.h" + +#define NVSWITCH_IFR_MIN_BIOS_VER_LS10 0x9610170000ull +#define NVSWITCH_SMBPBI_MIN_BIOS_VER_LS10 0x9610170000ull + +void * +nvswitch_alloc_chipdevice_ls10 +( + nvswitch_device *device +) +{ + void *chip_device; + + chip_device = nvswitch_os_malloc(sizeof(ls10_device)); + if (NULL != chip_device) + { + nvswitch_os_memset(chip_device, 0, sizeof(ls10_device)); + } + + device->chip_id = NV_PMC_BOOT_42_CHIP_ID_LS10; + return(chip_device); +} + +/* + * @Brief : Initializes the PRI Ring + * + * @Description : An example of a function that we'd like to generate from SU. + * + * @paramin device a reference to the device to initialize + * + * @returns NVL_SUCCESS if the action succeeded + */ +NvlStatus +nvswitch_pri_ring_init_ls10 +( + nvswitch_device *device +) +{ + NvU32 checked_data; + NvU32 command; + NvBool keepPolling; + NVSWITCH_TIMEOUT timeout; + + if (!IS_FMODEL(device)) + { + // check if FSP successfully started + nvswitch_timeout_create(10 * NVSWITCH_INTERVAL_1SEC_IN_NS, &timeout); + do + { + keepPolling = (nvswitch_timeout_check(&timeout)) ? NV_FALSE : NV_TRUE; + + command = NVSWITCH_REG_RD32(device, _GFW_GLOBAL, _BOOT_PARTITION_PROGRESS); + if (FLD_TEST_DRF(_GFW_GLOBAL, _BOOT_PARTITION_PROGRESS, _VALUE, _SUCCESS, command)) + { + break; + } + + nvswitch_os_sleep(1); + } + while (keepPolling); + if (!FLD_TEST_DRF(_GFW_GLOBAL, _BOOT_PARTITION_PROGRESS, _VALUE, _SUCCESS, command)) + { + NvU32 i; + + NVSWITCH_PRINT(device, ERROR, "%s: -- _GFW_GLOBAL, _BOOT_PARTITION_PROGRESS (0x%x) != _SUCCESS --\n", + __FUNCTION__, command); + + for (i = 0; i <= 15; i++) + { + command = NVSWITCH_SAW_RD32_LS10(device, _NVLSAW, _SW_SCRATCH(i)); + NVSWITCH_PRINT(device, ERROR, "%s: -- NV_NVLSAW_SW_SCRATCH(%d) = 0x%08x\n", + __FUNCTION__, i, command); + } + + for (i = 0; i <= 2; i++) + { + command = NVSWITCH_REG_RD32(device, _PFSP, _FALCON_COMMON_SCRATCH_GROUP_2(i)); + NVSWITCH_PRINT(device, ERROR, "%s: -- NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(%d) = 0x%08x\n", + __FUNCTION__, i, command); + } + + return -NVL_INITIALIZATION_TOTAL_FAILURE; + } + + command = NVSWITCH_ENG_RD32(device, SYS_PRI_HUB, , 0, _PPRIV_SYS, _PRI_RING_INIT); + if (FLD_TEST_DRF(_PPRIV_SYS, _PRI_RING_INIT, _STATUS, _ALIVE, command)) + { + // _STATUS == ALIVE. Skipping + return NVL_SUCCESS; + } + + if (!FLD_TEST_DRF(_PPRIV_SYS, _PRI_RING_INIT, _STATUS, _ALIVE_IN_SAFE_MODE, command)) + { + NVSWITCH_PRINT(device, ERROR, "%s: -- Initial _STATUS (0x%x) != _ALIVE_IN_SAFE_MODE --\n", + __FUNCTION__, DRF_VAL(_PPRIV_SYS, _PRI_RING_INIT, _STATUS, command)); + return -NVL_ERR_GENERIC; + } + + // .Switch PRI Ring Init Sequence + + // ***** + + // . [SW] Enumerate and start the PRI Ring + + NVSWITCH_ENG_WR32(device, SYS_PRI_HUB, , 0, _PPRIV_SYS, _PRI_RING_INIT, + DRF_DEF(_PPRIV_SYS, _PRI_RING_INIT, _CMD, _ENUMERATE_AND_START)); + + // . [SW] Wait for the command to complete + + if (IS_EMULATION(device)) + { + nvswitch_timeout_create(10 * NVSWITCH_INTERVAL_1MSEC_IN_NS, &timeout); + } + else + { + nvswitch_timeout_create(NVSWITCH_INTERVAL_1MSEC_IN_NS, &timeout); + } + + do + { + keepPolling = (nvswitch_timeout_check(&timeout)) ? NV_FALSE : NV_TRUE; + command = NVSWITCH_ENG_RD32(device, SYS_PRI_HUB, , 0, _PPRIV_SYS, _PRI_RING_INIT); + + if ( FLD_TEST_DRF(_PPRIV_SYS,_PRI_RING_INIT,_CMD,_NONE,command) ) + { + break; + } + if ( keepPolling == NV_FALSE ) + { + NVSWITCH_PRINT(device, ERROR, "%s: -- Timeout waiting for _CMD == _NONE --\n", __FUNCTION__); + return -NVL_ERR_GENERIC; + } + } + while (keepPolling); + + // . [SW] Confirm PRI Ring initialized properly. Executing four reads to introduce a delay. + + if (IS_EMULATION(device)) + { + nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout); + } + else + { + nvswitch_timeout_create(NVSWITCH_INTERVAL_1MSEC_IN_NS, &timeout); + } + + do + { + keepPolling = (nvswitch_timeout_check(&timeout)) ? NV_FALSE : NV_TRUE; + command = NVSWITCH_ENG_RD32(device, SYS_PRI_HUB, , 0, _PPRIV_SYS, _PRI_RING_INIT); + + if ( FLD_TEST_DRF(_PPRIV_SYS, _PRI_RING_INIT, _STATUS, _ALIVE, command) ) + { + break; + } + if ( keepPolling == NV_FALSE ) + { + NVSWITCH_PRINT(device, ERROR, "%s: -- Timeout waiting for _STATUS == _ALIVE --\n", __FUNCTION__); + return -NVL_ERR_GENERIC; + } + } + while (keepPolling); + + // . [SW] PRI Ring Interrupt Status0 and Status1 should be clear unless there was an error. + + checked_data = NVSWITCH_ENG_RD32(device, PRI_MASTER_RS, , 0, _PPRIV_MASTER, _RING_INTERRUPT_STATUS0); + if ( !FLD_TEST_DRF_NUM(_PPRIV_MASTER, _RING_INTERRUPT_STATUS0, _DISCONNECT_FAULT, 0x0, checked_data) ) + { + NVSWITCH_PRINT(device, ERROR, "%s: _PPRIV_MASTER,_RING_INTERRUPT_STATUS0,_DISCONNECT_FAULT != 0x0\n", __FUNCTION__); + } + if ( !FLD_TEST_DRF_NUM(_PPRIV_MASTER, _RING_INTERRUPT_STATUS0, _GBL_WRITE_ERROR_FBP, 0x0, checked_data) ) + { + NVSWITCH_PRINT(device, ERROR, "%s: _PPRIV_MASTER,_RING_INTERRUPT_STATUS0,_GBL_WRITE_ERROR_FBP != 0x0\n", __FUNCTION__); + } + if ( !FLD_TEST_DRF_NUM(_PPRIV_MASTER, _RING_INTERRUPT_STATUS0, _GBL_WRITE_ERROR_SYS, 0x0, checked_data) ) + { + NVSWITCH_PRINT(device, ERROR, "%s: _PPRIV_MASTER,_RING_INTERRUPT_STATUS0,_GBL_WRITE_ERROR_SYS != 0x0\n", __FUNCTION__); + } + if ( !FLD_TEST_DRF_NUM(_PPRIV_MASTER, _RING_INTERRUPT_STATUS0, _OVERFLOW_FAULT, 0x0, checked_data) ) + { + NVSWITCH_PRINT(device, ERROR, "%s: _PPRIV_MASTER,_RING_INTERRUPT_STATUS0,_OVERFLOW_FAULT != 0x0\n", __FUNCTION__); + } + if ( !FLD_TEST_DRF_NUM(_PPRIV_MASTER, _RING_INTERRUPT_STATUS0, _RING_START_CONN_FAULT, 0x0, checked_data) ) + { + NVSWITCH_PRINT(device, ERROR, "%s: _PPRIV_MASTER,_RING_INTERRUPT_STATUS0,_RING_START_CONN_FAULT != 0x0\n", __FUNCTION__); + } + + checked_data = NVSWITCH_ENG_RD32(device, PRI_MASTER_RS, , 0, _PPRIV_MASTER, _RING_INTERRUPT_STATUS1); + if ( !FLD_TEST_DRF_NUM(_PPRIV_MASTER, _RING_INTERRUPT_STATUS1, _GBL_WRITE_ERROR_GPC, 0x0, checked_data) ) + { + NVSWITCH_PRINT(device, ERROR, "%s: _PPRIV_MASTER,_RING_INTERRUPT_STATUS1,_GBL_WRITE_ERROR_GPC != 0x0\n", __FUNCTION__); + } + + // ***** + } + + return NVL_SUCCESS; +} + +/* + * @Brief : Destroys an NvSwitch hardware state + * + * @Description : + * + * @param[in] device a reference to the device to initialize + */ +void +nvswitch_destroy_device_state_ls10 +( + nvswitch_device *device +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + + if (nvswitch_is_soe_supported(device)) + { + nvswitch_soe_unregister_events(device); + nvswitch_unload_soe_ls10(device); + } + + if (chip_device != NULL) + { + if ((chip_device->latency_stats) != NULL) + { + nvswitch_os_free(chip_device->latency_stats); + } + + if ((chip_device->ganged_link_table) != NULL) + { + nvswitch_os_free(chip_device->ganged_link_table); + } + + nvswitch_free_chipdevice(device); + } + + nvswitch_i2c_destroy(device); + + return; +} + +NvlStatus +nvswitch_initialize_pmgr_ls10 +( + nvswitch_device *device +) +{ + // Init PMGR info + nvswitch_init_pmgr_ls10(device); + nvswitch_init_pmgr_devices_ls10(device); + + return NVL_SUCCESS; +} + + +NvlStatus +nvswitch_initialize_ip_wrappers_ls10 +( + nvswitch_device *device +) +{ + NvlStatus status = NVL_SUCCESS; + + // + // Now that software knows the devices and addresses, it must take all + // the wrapper modules out of reset. + // + + status = nvswitch_nvs_top_prod_ls10(device); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: TOP PROD initialization failed.\n", + __FUNCTION__); + return status; + } + + status = nvswitch_apply_prod_nvlw_ls10(device); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: NVLW PROD initialization failed.\n", + __FUNCTION__); + return status; + } + + status = nvswitch_apply_prod_nxbar_ls10(device); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: NXBAR PROD initialization failed.\n", + __FUNCTION__); + return status; + } + + return status; +} + +void +nvswitch_set_ganged_link_table_ls10 +( + nvswitch_device *device, + NvU32 firstIndex, + NvU64 *ganged_link_table, + NvU32 numEntries +) +{ + NvU32 i; + + NVSWITCH_NPORT_MC_BCAST_WR32_LS10(device, _ROUTE, _REG_TABLE_ADDRESS, + DRF_NUM(_ROUTE, _REG_TABLE_ADDRESS, _INDEX, firstIndex) | + DRF_NUM(_ROUTE, _REG_TABLE_ADDRESS, _AUTO_INCR, 1)); + + for (i = 0; i < numEntries; i++) + { + NVSWITCH_NPORT_MC_BCAST_WR32_LS10(device, _ROUTE, _REG_TABLE_DATA1, + NvU64_HI32(ganged_link_table[i])); + + // HW will fill in the ECC + NVSWITCH_NPORT_MC_BCAST_WR32_LS10(device, _ROUTE, _REG_TABLE_DATA2, + 0); + + // + // Writing DATA0 triggers the latched data to be written to the table + // So write it last + // + NVSWITCH_NPORT_MC_BCAST_WR32_LS10(device, _ROUTE, _REG_TABLE_DATA0, + NvU64_LO32(ganged_link_table[i])); + } +} + +static NvlStatus +_nvswitch_init_ganged_link_routing_ls10 +( + nvswitch_device *device +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NvU32 gang_size; + NvU64 gang_entry; + NvU32 glt_entries = 16; + NvU32 glt_size = (NV_ROUTE_REG_TABLE_ADDRESS_INDEX_GLTAB_DEPTH + 1); + NvU64 *ganged_link_table = NULL; + NvU32 i; + NvU32 glt_index; + + // + // The ganged link routing table is composed of 256 entries of 64-bits in + // size. Each entry is divided into 16 4-bit fields GLX(i), where GLX(x) + // contains the distribution pattern for x ports. Zero ports is not a + // valid configuration, so GLX(0) corresponds with 16 ports. + // Each GLX(i) column therefore should contain a uniform distribution + // pattern for i ports. + // + // The ganged link routing table will be loaded with following values: + // (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), + // (1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1), + // (2,0,0,2,2,2,2,2,2,2,2,2,2,2,2,2), + // (3,0,1,0,3,3,3,3,3,3,3,3,3,3,3,3), + // : + // (E,0,0,2,2,4,2,2,6,2,4,1,2,7,2,E), + // (F,0,1,0,3,0,3,3,7,3,5,2,3,8,3,0) + // + // Refer table 22: Definition of size bits used with Ganged Link Number Table. + // + + //Alloc memory for Ganged Link Table + ganged_link_table = nvswitch_os_malloc(glt_size * sizeof(gang_entry)); + if (ganged_link_table == NULL) + { + NVSWITCH_PRINT(device, ERROR, + "Failed to allocate memory for GLT!!\n"); + return -NVL_NO_MEM; + } + + for (glt_index = 0; glt_index < glt_size; glt_index++) + { + gang_entry = 0; + for (i = 0; i < glt_entries; i++) + { + gang_size = ((i==0) ? 16 : i); + gang_entry |= + DRF_NUM64(_ROUTE, _REG_TABLE_DATA0, _GLX(i), glt_index % gang_size); + } + + ganged_link_table[glt_index] = gang_entry; + } + + nvswitch_set_ganged_link_table_ls10(device, 0, ganged_link_table, glt_size); + + chip_device->ganged_link_table = ganged_link_table; + + return NVL_SUCCESS; +} + +static void +_nvswitch_init_cmd_routing_ls10 +( + nvswitch_device *device +) +{ + NvU32 val; + + //Set Hash policy for the requests. + val = DRF_DEF(_ROUTE, _CMD_ROUTE_TABLE0, _RFUN1, _SPRAY) | + DRF_DEF(_ROUTE, _CMD_ROUTE_TABLE0, _RFUN2, _SPRAY) | + DRF_DEF(_ROUTE, _CMD_ROUTE_TABLE0, _RFUN4, _SPRAY) | + DRF_DEF(_ROUTE, _CMD_ROUTE_TABLE0, _RFUN7, _SPRAY); + NVSWITCH_NPORT_BCAST_WR32_LS10(device, _ROUTE, _CMD_ROUTE_TABLE0, val); + + // Set Random policy for reponses. + val = DRF_DEF(_ROUTE, _CMD_ROUTE_TABLE2, _RFUN16, _RANDOM) | + DRF_DEF(_ROUTE, _CMD_ROUTE_TABLE2, _RFUN17, _RANDOM); + NVSWITCH_NPORT_BCAST_WR32_LS10(device, _ROUTE, _CMD_ROUTE_TABLE2, val); +} + +static NvlStatus +_nvswitch_init_portstat_counters_ls10 +( + nvswitch_device *device +) +{ + NvlStatus retval; + NvU32 idx_channel; + NVSWITCH_SET_LATENCY_BINS default_latency_bins; + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + + chip_device->latency_stats = nvswitch_os_malloc(sizeof(NVSWITCH_LATENCY_STATS_LS10)); + if (chip_device->latency_stats == NULL) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed allocate memory for latency stats\n", + __FUNCTION__); + return -NVL_NO_MEM; + } + + nvswitch_os_memset(chip_device->latency_stats, 0, sizeof(NVSWITCH_LATENCY_STATS_LS10)); + + // + // These bin thresholds are values provided by Arch based off + // switch latency expectations. + // + for (idx_channel=0; idx_channel < NVSWITCH_NUM_VCS_LS10; idx_channel++) + { + default_latency_bins.bin[idx_channel].lowThreshold = 120; // 120ns + default_latency_bins.bin[idx_channel].medThreshold = 200; // 200ns + default_latency_bins.bin[idx_channel].hiThreshold = 1000; // 1us + } + + // + // 6 hour sample interval + // The 48-bit counters can theoretically rollover after ~12 hours of full + // throttle traffic. + // + chip_device->latency_stats->sample_interval_msec = 6 * 60 * 60 * 1000; + + retval = nvswitch_ctrl_set_latency_bins(device, &default_latency_bins); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed to set latency bins\n", + __FUNCTION__); + NVSWITCH_ASSERT(0); + return retval; + } + + NVSWITCH_NPORT_BCAST_WR32_LS10(device, _NPORT, _PORTSTAT_CONTROL, + DRF_DEF(_NPORT, _PORTSTAT_CONTROL, _RANGESELECT, _BITS13TO0)); + + NVSWITCH_NPORT_BCAST_WR32_LS10(device, _NPORT, _PORTSTAT_SOURCE_FILTER_0, + DRF_NUM(_NPORT, _PORTSTAT_SOURCE_FILTER_0, _SRCFILTERBIT, 0xFFFFFFFF)); + + NVSWITCH_NPORT_BCAST_WR32_LS10(device, _NPORT, _PORTSTAT_SOURCE_FILTER_1, + DRF_NUM(_NPORT, _PORTSTAT_SOURCE_FILTER_1, _SRCFILTERBIT, 0xFFFFFFFF)); + + NVSWITCH_SAW_WR32_LS10(device, _NVLSAW, _GLBLLATENCYTIMERCTRL, + DRF_DEF(_NVLSAW, _GLBLLATENCYTIMERCTRL, _ENABLE, _ENABLE)); + + NVSWITCH_NPORT_BCAST_WR32_LS10(device, _NPORT, _PORTSTAT_SNAP_CONTROL, + DRF_DEF(_NPORT, _PORTSTAT_SNAP_CONTROL, _STARTCOUNTER, _ENABLE) | + DRF_DEF(_NPORT, _PORTSTAT_SNAP_CONTROL, _SNAPONDEMAND, _DISABLE)); + + // Start & Clear Residency Counters + NVSWITCH_NPORT_BCAST_WR32_LS10(device, _MULTICASTTSTATE, _STAT_RESIDENCY_CONTROL, + DRF_DEF(_MULTICASTTSTATE, _STAT_RESIDENCY_CONTROL, _ENABLE_TIMER, _ENABLE) | + DRF_DEF(_MULTICASTTSTATE, _STAT_RESIDENCY_CONTROL, _SNAP_ON_DEMAND, _ENABLE)); + NVSWITCH_NPORT_BCAST_WR32_LS10(device, _MULTICASTTSTATE, _STAT_RESIDENCY_CONTROL, + DRF_DEF(_MULTICASTTSTATE, _STAT_RESIDENCY_CONTROL, _ENABLE_TIMER, _ENABLE) | + DRF_DEF(_MULTICASTTSTATE, _STAT_RESIDENCY_CONTROL, _SNAP_ON_DEMAND, _DISABLE)); + + NVSWITCH_NPORT_BCAST_WR32_LS10(device, _REDUCTIONTSTATE, _STAT_RESIDENCY_CONTROL, + DRF_DEF(_REDUCTIONTSTATE, _STAT_RESIDENCY_CONTROL, _ENABLE_TIMER, _ENABLE) | + DRF_DEF(_REDUCTIONTSTATE, _STAT_RESIDENCY_CONTROL, _SNAP_ON_DEMAND, _ENABLE)); + NVSWITCH_NPORT_BCAST_WR32_LS10(device, _REDUCTIONTSTATE, _STAT_RESIDENCY_CONTROL, + DRF_DEF(_REDUCTIONTSTATE, _STAT_RESIDENCY_CONTROL, _ENABLE_TIMER, _ENABLE) | + DRF_DEF(_REDUCTIONTSTATE, _STAT_RESIDENCY_CONTROL, _SNAP_ON_DEMAND, _DISABLE)); + + // Start & Clear Stall/Busy Counters + NVSWITCH_NPORT_BCAST_WR32_LS10(device, _MULTICASTTSTATE, _STAT_STALL_BUSY_CONTROL, + DRF_DEF(_MULTICASTTSTATE, _STAT_STALL_BUSY_CONTROL, _ENABLE_TIMER, _ENABLE) | + DRF_DEF(_MULTICASTTSTATE, _STAT_STALL_BUSY_CONTROL, _SNAP_ON_DEMAND, _ENABLE)); + NVSWITCH_NPORT_BCAST_WR32_LS10(device, _MULTICASTTSTATE, _STAT_STALL_BUSY_CONTROL, + DRF_DEF(_MULTICASTTSTATE, _STAT_STALL_BUSY_CONTROL, _ENABLE_TIMER, _ENABLE) | + DRF_DEF(_MULTICASTTSTATE, _STAT_STALL_BUSY_CONTROL, _SNAP_ON_DEMAND, _DISABLE)); + + NVSWITCH_NPORT_BCAST_WR32_LS10(device, _REDUCTIONTSTATE, _STAT_STALL_BUSY_CONTROL, + DRF_DEF(_REDUCTIONTSTATE, _STAT_STALL_BUSY_CONTROL, _ENABLE_TIMER, _ENABLE) | + DRF_DEF(_REDUCTIONTSTATE, _STAT_STALL_BUSY_CONTROL, _SNAP_ON_DEMAND, _ENABLE)); + NVSWITCH_NPORT_BCAST_WR32_LS10(device, _REDUCTIONTSTATE, _STAT_STALL_BUSY_CONTROL, + DRF_DEF(_REDUCTIONTSTATE, _STAT_STALL_BUSY_CONTROL, _ENABLE_TIMER, _ENABLE) | + DRF_DEF(_REDUCTIONTSTATE, _STAT_STALL_BUSY_CONTROL, _SNAP_ON_DEMAND, _DISABLE)); + + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_initialize_route_ls10 +( + nvswitch_device *device +) +{ + NvlStatus retval; + + retval = _nvswitch_init_ganged_link_routing_ls10(device); + if (NVL_SUCCESS != retval) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to initialize GLT\n", + __FUNCTION__); + goto nvswitch_initialize_route_exit; + } + + _nvswitch_init_cmd_routing_ls10(device); + + // Initialize Portstat Counters + retval = _nvswitch_init_portstat_counters_ls10(device); + if (NVL_SUCCESS != retval) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to initialize portstat counters\n", + __FUNCTION__); + goto nvswitch_initialize_route_exit; + } + + // TODO: Setup multicast/reductions + +nvswitch_initialize_route_exit: + return retval; +} + +NvlStatus +nvswitch_ctrl_get_counters_ls10 +( + nvswitch_device *device, + NVSWITCH_NVLINK_GET_COUNTERS_PARAMS *ret +) +{ + nvlink_link *link; + NvU8 i; + NvU32 counterMask; + NvU32 data; + NvU32 val; + NvU64 tx0TlCount; + NvU64 tx1TlCount; + NvU64 rx0TlCount; + NvU64 rx1TlCount; + NvU32 laneId; + NvBool bLaneReversed; + NvlStatus status; + NvBool minion_enabled; + + ct_assert(NVSWITCH_NUM_LANES_LS10 <= NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE__SIZE); + + link = nvswitch_get_link(device, ret->linkId); + if ((link == NULL) || + !NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLDL, link->linkNumber)) + { + return -NVL_BAD_ARGS; + } + + minion_enabled = nvswitch_is_minion_initialized(device, NVSWITCH_GET_LINK_ENG_INST(device, link->linkNumber, MINION)); + + counterMask = ret->counterMask; + + // Common usage allows one of these to stand for all of them + if (counterMask & (NVSWITCH_NVLINK_COUNTER_TL_TX0 | + NVSWITCH_NVLINK_COUNTER_TL_TX1 | + NVSWITCH_NVLINK_COUNTER_TL_RX0 | + NVSWITCH_NVLINK_COUNTER_TL_RX1)) + { + tx0TlCount = nvswitch_read_64bit_counter(device, + NVSWITCH_LINK_OFFSET_LS10(device, link->linkNumber, NVLTLC, _NVLTLC_TX_LNK, _DEBUG_TP_CNTR_LO(0)), + NVSWITCH_LINK_OFFSET_LS10(device, link->linkNumber, NVLTLC, _NVLTLC_TX_LNK, _DEBUG_TP_CNTR_HI(0))); + if (NVBIT64(63) & tx0TlCount) + { + ret->bTx0TlCounterOverflow = NV_TRUE; + tx0TlCount &= ~(NVBIT64(63)); + } + + tx1TlCount = nvswitch_read_64bit_counter(device, + NVSWITCH_LINK_OFFSET_LS10(device, link->linkNumber, NVLTLC, _NVLTLC_TX_LNK, _DEBUG_TP_CNTR_LO(1)), + NVSWITCH_LINK_OFFSET_LS10(device, link->linkNumber, NVLTLC, _NVLTLC_TX_LNK, _DEBUG_TP_CNTR_HI(1))); + if (NVBIT64(63) & tx1TlCount) + { + ret->bTx1TlCounterOverflow = NV_TRUE; + tx1TlCount &= ~(NVBIT64(63)); + } + + rx0TlCount = nvswitch_read_64bit_counter(device, + NVSWITCH_LINK_OFFSET_LS10(device, link->linkNumber, NVLTLC, _NVLTLC_RX_LNK, _DEBUG_TP_CNTR_LO(0)), + NVSWITCH_LINK_OFFSET_LS10(device, link->linkNumber, NVLTLC, _NVLTLC_RX_LNK, _DEBUG_TP_CNTR_HI(0))); + if (NVBIT64(63) & rx0TlCount) + { + ret->bRx0TlCounterOverflow = NV_TRUE; + rx0TlCount &= ~(NVBIT64(63)); + } + + rx1TlCount = nvswitch_read_64bit_counter(device, + NVSWITCH_LINK_OFFSET_LS10(device, link->linkNumber, NVLTLC, _NVLTLC_RX_LNK, _DEBUG_TP_CNTR_LO(1)), + NVSWITCH_LINK_OFFSET_LS10(device, link->linkNumber, NVLTLC, _NVLTLC_RX_LNK, _DEBUG_TP_CNTR_HI(1))); + if (NVBIT64(63) & rx1TlCount) + { + ret->bRx1TlCounterOverflow = NV_TRUE; + rx1TlCount &= ~(NVBIT64(63)); + } + + ret->nvlinkCounters[BIT_IDX_32(NVSWITCH_NVLINK_COUNTER_TL_TX0)] = tx0TlCount; + ret->nvlinkCounters[BIT_IDX_32(NVSWITCH_NVLINK_COUNTER_TL_TX1)] = tx1TlCount; + ret->nvlinkCounters[BIT_IDX_32(NVSWITCH_NVLINK_COUNTER_TL_RX0)] = rx0TlCount; + ret->nvlinkCounters[BIT_IDX_32(NVSWITCH_NVLINK_COUNTER_TL_RX1)] = rx1TlCount; + } + + if (counterMask & NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_FLIT) + { + if (minion_enabled) + { + status = nvswitch_minion_get_dl_status(device, link->linkNumber, + NV_NVLSTAT_RX01, 0, &data); + if (status != NVL_SUCCESS) + { + return status; + } + data = DRF_VAL(_NVLSTAT, _RX01, _FLIT_CRC_ERRORS_VALUE, data); + } + else + { + // MINION disabled + data = 0; + } + + ret->nvlinkCounters[BIT_IDX_32(NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_FLIT)] + = data; + } + + if (counterMask & NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_MASKED) + { + if (minion_enabled) + { + status = nvswitch_minion_get_dl_status(device, link->linkNumber, + NV_NVLSTAT_RX02, 0, &data); + if (status != NVL_SUCCESS) + { + return status; + } + data = DRF_VAL(_NVLSTAT, _RX02, _MASKED_CRC_ERRORS_VALUE, data); + } + else + { + // MINION disabled + data = 0; + } + + ret->nvlinkCounters[BIT_IDX_32(NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_MASKED)] + = data; + } + data = 0x0; + bLaneReversed = nvswitch_link_lane_reversed_ls10(device, link->linkNumber); + + for (laneId = 0; laneId < NVSWITCH_NUM_LANES_LS10; laneId++) + { + // + // HW may reverse the lane ordering or it may be overridden by SW. + // If so, invert the interpretation of the lane CRC errors. + // + i = (NvU8)((bLaneReversed) ? (NVSWITCH_NUM_LANES_LS10 - 1) - laneId : laneId); + + if (minion_enabled) + { + status = nvswitch_minion_get_dl_status(device, link->linkNumber, + NV_NVLSTAT_DB01, 0, &data); + if (status != NVL_SUCCESS) + { + return status; + } + } + else + { + // MINION disabled + data = 0; + } + + if (counterMask & NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L(laneId)) + { + val = BIT_IDX_32(NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L(laneId)); + + switch (i) + { + case 0: + ret->nvlinkCounters[val] + = DRF_VAL(_NVLSTAT, _DB01, _ERROR_COUNT_ERR_LANECRC_L0, data); + break; + case 1: + ret->nvlinkCounters[val] + = DRF_VAL(_NVLSTAT, _DB01, _ERROR_COUNT_ERR_LANECRC_L1, data); + break; + } + } + } + + if (counterMask & NVSWITCH_NVLINK_COUNTER_DL_TX_ERR_REPLAY) + { + if (minion_enabled) + { + status = nvswitch_minion_get_dl_status(device, link->linkNumber, + NV_NVLSTAT_TX09, 0, &data); + if (status != NVL_SUCCESS) + { + return status; + } + data = DRF_VAL(_NVLSTAT, _TX09, _REPLAY_EVENTS_VALUE, data); + } + else + { + // MINION disabled + data = 0; + } + + ret->nvlinkCounters[BIT_IDX_32(NVSWITCH_NVLINK_COUNTER_DL_TX_ERR_REPLAY)] + = data; + } + + if (counterMask & NVSWITCH_NVLINK_COUNTER_DL_TX_ERR_RECOVERY) + { + if (minion_enabled) + { + status = nvswitch_minion_get_dl_status(device, link->linkNumber, + NV_NVLSTAT_LNK1, 0, &data); + if (status != NVL_SUCCESS) + { + return status; + } + data = DRF_VAL(_NVLSTAT, _LNK1, _ERROR_COUNT1_RECOVERY_EVENTS_VALUE, data); + } + else + { + // MINION disabled + data = 0; + } + + ret->nvlinkCounters[BIT_IDX_32(NVSWITCH_NVLINK_COUNTER_DL_TX_ERR_RECOVERY)] + = data; + } + + if (counterMask & NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_REPLAY) + { + if (minion_enabled) + { + status = nvswitch_minion_get_dl_status(device, link->linkNumber, + NV_NVLSTAT_RX00, 0, &data); + if (status != NVL_SUCCESS) + { + return status; + } + data = DRF_VAL(_NVLSTAT, _RX00, _REPLAY_EVENTS_VALUE, data); + } + else + { + // MINION disabled + data = 0; + } + + ret->nvlinkCounters[BIT_IDX_32(NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_REPLAY)] + = data; + } + + if ((counterMask & NVSWITCH_NVLINK_COUNTER_PHY_REFRESH_PASS) || + (counterMask & NVSWITCH_NVLINK_COUNTER_PHY_REFRESH_FAIL)) + { + if (minion_enabled) + { + status = nvswitch_minion_get_dl_status(device, link->linkNumber, + NV_NVLSTAT_DB11, 0, &data); + if (status != NVL_SUCCESS) + { + return status; + } + } + else + { + // MINION disabled + data = 0; + } + + if (counterMask & NVSWITCH_NVLINK_COUNTER_PHY_REFRESH_PASS) + { + ret->nvlinkCounters[BIT_IDX_32(NVSWITCH_NVLINK_COUNTER_PHY_REFRESH_PASS)] + = DRF_VAL(_NVLSTAT_DB11, _COUNT_PHY_REFRESH, _PASS, data); + } + + if (counterMask & NVSWITCH_NVLINK_COUNTER_PHY_REFRESH_FAIL) + { + ret->nvlinkCounters[BIT_IDX_32(NVSWITCH_NVLINK_COUNTER_PHY_REFRESH_FAIL)] + = DRF_VAL(_NVLSTAT_DB11, _COUNT_PHY_REFRESH, _FAIL, data); + } + } + + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_ctrl_get_sw_info_ls10 +( + nvswitch_device *device, + NVSWITCH_GET_SW_INFO_PARAMS *p +) +{ + NvlStatus retval = NVL_SUCCESS; + NvU32 i; + + if (p->count > NVSWITCH_GET_SW_INFO_COUNT_MAX) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Invalid args\n", + __FUNCTION__); + return -NVL_BAD_ARGS; + } + + nvswitch_os_memset(p->info, 0, sizeof(NvU32)*NVSWITCH_GET_SW_INFO_COUNT_MAX); + + for (i = 0; i < p->count; i++) + { + switch (p->index[i]) + { + case NVSWITCH_GET_SW_INFO_INDEX_INFOROM_NVL_SUPPORTED: + p->info[i] = NV_FALSE; //TODO: Enable once NVL support is present (CTK-4163) + break; + case NVSWITCH_GET_SW_INFO_INDEX_INFOROM_BBX_SUPPORTED: + p->info[i] = NV_TRUE; + break; + default: + NVSWITCH_PRINT(device, ERROR, + "%s: Undefined NVSWITCH_GET_SW_INFO_INDEX 0x%x\n", + __FUNCTION__, + p->index[i]); + retval = -NVL_BAD_ARGS; + break; + } + } + + return retval; +} + +static void +nvswitch_ctrl_clear_throughput_counters_ls10 +( + nvswitch_device *device, + nvlink_link *link, + NvU32 counterMask +) +{ + NvU32 data; + + if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLTLC, link->linkNumber)) + { + return; + } + + // + // Common usage allows one of these to stand for all of them + // If one field is defined: perform a clear on counters 0 & 1 + // + + if ((counterMask) & ( NVSWITCH_NVLINK_COUNTER_TL_TX0 | + NVSWITCH_NVLINK_COUNTER_TL_TX1 | + NVSWITCH_NVLINK_COUNTER_TL_RX0 | + NVSWITCH_NVLINK_COUNTER_TL_RX1 )) + { + // TX 0 + data = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, NVLTLC, _NVLTLC_TX_LNK, _DEBUG_TP_CNTR_CTRL_0(0)); + data = FLD_SET_DRF_NUM(_NVLTLC_TX_LNK, _DEBUG_TP_CNTR_CTRL_0, _RESET, 0x1, data); + NVSWITCH_LINK_WR32_LS10(device, link->linkNumber, NVLTLC, _NVLTLC_TX_LNK, _DEBUG_TP_CNTR_CTRL_0(0), data); + + // TX 1 + data = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, NVLTLC, _NVLTLC_TX_LNK, _DEBUG_TP_CNTR_CTRL_0(1)); + data = FLD_SET_DRF_NUM(_NVLTLC_TX_LNK, _DEBUG_TP_CNTR_CTRL_0, _RESET, 0x1, data); + NVSWITCH_LINK_WR32_LS10(device, link->linkNumber, NVLTLC, _NVLTLC_TX_LNK, _DEBUG_TP_CNTR_CTRL_0(1), data); + + // RX 0 + data = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, NVLTLC, _NVLTLC_RX_LNK, _DEBUG_TP_CNTR_CTRL_0(0)); + data = FLD_SET_DRF_NUM(_NVLTLC_RX_LNK, _DEBUG_TP_CNTR_CTRL_0, _RESET, 0x1, data); + NVSWITCH_LINK_WR32_LS10(device, link->linkNumber, NVLTLC, _NVLTLC_RX_LNK, _DEBUG_TP_CNTR_CTRL_0(0), data); + + // RX 1 + data = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, NVLTLC, _NVLTLC_RX_LNK, _DEBUG_TP_CNTR_CTRL_0(1)); + data = FLD_SET_DRF_NUM(_NVLTLC_RX_LNK, _DEBUG_TP_CNTR_CTRL_0, _RESET, 0x1, data); + NVSWITCH_LINK_WR32_LS10(device, link->linkNumber, NVLTLC, _NVLTLC_RX_LNK, _DEBUG_TP_CNTR_CTRL_0(1), data); + } +} + +static void +nvswitch_ctrl_clear_lp_counters_ls10 +( + nvswitch_device *device, + nvlink_link *link, + NvU32 counterMask +) +{ + NvlStatus status; + + // Clears all LP counters + if (counterMask & NVSWITCH_NVLINK_LP_COUNTERS_DL) + { + status = nvswitch_minion_send_command(device, link->linkNumber, + NV_MINION_NVLINK_DL_CMD_COMMAND_DLSTAT_CLR_DLLPCNT, 0); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s : Failed to clear lp counts to MINION for link # %d\n", + __FUNCTION__, link->linkNumber); + } + } +} + +static NvlStatus +nvswitch_ctrl_clear_dl_error_counters_ls10 +( + nvswitch_device *device, + nvlink_link *link, + NvU32 counterMask +) +{ + NvU32 data; + + if ((!counterMask) || + (!(counterMask & (NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L0 | + NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L1 | + NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L2 | + NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L3 | + NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L4 | + NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L5 | + NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L6 | + NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L7 | + NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_ECC_COUNTS | + NVSWITCH_NVLINK_COUNTER_DL_TX_ERR_REPLAY | + NVSWITCH_NVLINK_COUNTER_DL_TX_ERR_RECOVERY)))) + { + NVSWITCH_PRINT(device, INFO, + "%s: Link%d: No error count clear request, counterMask (0x%x). Returning!\n", + __FUNCTION__, link->linkNumber, counterMask); + return NVL_SUCCESS; + } + + // With Minion initialized, send command to minion + if (nvswitch_is_minion_initialized(device, NVSWITCH_GET_LINK_ENG_INST(device, link->linkNumber, MINION))) + { + return nvswitch_minion_clear_dl_error_counters_ls10(device, link->linkNumber); + } + + // With Minion not-initialized, perform with the registers + if (counterMask & (NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L0 | + NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L1 | + NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L2 | + NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L3 | + NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L4 | + NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L5 | + NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L6 | + NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L7 | + NVSWITCH_NVLINK_COUNTER_DL_TX_ERR_REPLAY | + NVSWITCH_NVLINK_COUNTER_DL_TX_ERR_RECOVERY | + NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_FLIT | + NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_MASKED )) + { + data = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, NVLDL, _NVLDL_RX, _ERROR_COUNT_CTRL); + data = FLD_SET_DRF(_NVLDL_RX, _ERROR_COUNT_CTRL, _CLEAR_LANE_CRC, _CLEAR, data); + data = FLD_SET_DRF(_NVLDL_RX, _ERROR_COUNT_CTRL, _CLEAR_FLIT_CRC, _CLEAR, data); + data = FLD_SET_DRF(_NVLDL_TX, _ERROR_COUNT_CTRL, _CLEAR_REPLAY, _CLEAR, data); + data = FLD_SET_DRF(_NVLDL_TOP, _ERROR_COUNT_CTRL, _CLEAR_RECOVERY, _CLEAR, data); + data = FLD_SET_DRF(_NVLDL_RX, _ERROR_COUNT_CTRL, _CLEAR_RATES, _CLEAR, data); + NVSWITCH_LINK_WR32_LS10(device, link->linkNumber, NVLDL, _NVLDL_RX, _ERROR_COUNT_CTRL, data); + } + + if (counterMask & NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_ECC_COUNTS) + { + data = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, NVLDL, _NVLDL_RX, _ERROR_COUNT_CTRL); + data = FLD_SET_DRF(_NVLDL_RX, _ERROR_COUNT_CTRL, _CLEAR_LANE_CRC, _CLEAR, data); + data = FLD_SET_DRF(_NVLDL_RX, _ERROR_COUNT_CTRL, _CLEAR_RATES, _CLEAR, data); + data = FLD_SET_DRF(_NVLDL_RX, _ERROR_COUNT_CTRL, _CLEAR_ECC_COUNTS, _CLEAR, data); + } + + return NVL_SUCCESS; +} + +static void +_nvswitch_portstat_reset_latency_counters_ls10 +( + nvswitch_device *device +) +{ + // Set SNAPONDEMAND from 0->1 to reset the counters + NVSWITCH_NPORT_BCAST_WR32_LS10(device, _NPORT, _PORTSTAT_SNAP_CONTROL, + DRF_DEF(_NPORT, _PORTSTAT_SNAP_CONTROL, _STARTCOUNTER, _ENABLE) | + DRF_DEF(_NPORT, _PORTSTAT_SNAP_CONTROL, _SNAPONDEMAND, _ENABLE)); + + // Set SNAPONDEMAND back to 0. + NVSWITCH_NPORT_BCAST_WR32_LS10(device, _NPORT, _PORTSTAT_SNAP_CONTROL, + DRF_DEF(_NPORT, _PORTSTAT_SNAP_CONTROL, _STARTCOUNTER, _ENABLE) | + DRF_DEF(_NPORT, _PORTSTAT_SNAP_CONTROL, _SNAPONDEMAND, _DISABLE)); +} + +/* + * Disable interrupts comming from NPG & NVLW blocks. + */ +static void +_nvswitch_link_disable_interrupts_ls10 +( + nvswitch_device *device, + NvU32 link +) +{ + NvU32 localLinkIdx, instance; + + instance = link / NVSWITCH_LINKS_PER_NVLIPT_LS10; + localLinkIdx = link % NVSWITCH_LINKS_PER_NVLIPT_LS10; + + NVSWITCH_NPORT_WR32_LS10(device, link, _NPORT, _ERR_CONTROL_COMMON_NPORT, + DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _CORRECTABLEENABLE, 0x0) | + DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _FATALENABLE, 0x0) | + DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _NONFATALENABLE, 0x0)); + + NVSWITCH_ENG_WR32(device, NVLW, , instance, _NVLW, _LINK_INTR_0_MASK(localLinkIdx), + DRF_NUM(_NVLW, _LINK_INTR_0_MASK, _FATAL, 0x0) | + DRF_NUM(_NVLW, _LINK_INTR_0_MASK, _NONFATAL, 0x0) | + DRF_NUM(_NVLW, _LINK_INTR_0_MASK, _CORRECTABLE, 0x0)); + + NVSWITCH_ENG_WR32(device, NVLW, , instance, _NVLW, _LINK_INTR_1_MASK(localLinkIdx), + DRF_NUM(_NVLW, _LINK_INTR_1_MASK, _FATAL, 0x0) | + DRF_NUM(_NVLW, _LINK_INTR_1_MASK, _NONFATAL, 0x0) | + DRF_NUM(_NVLW, _LINK_INTR_1_MASK, _CORRECTABLE, 0x0)); + + NVSWITCH_ENG_WR32(device, NVLW, , instance, _NVLW, _LINK_INTR_2_MASK(localLinkIdx), + DRF_NUM(_NVLW, _LINK_INTR_2_MASK, _FATAL, 0x0) | + DRF_NUM(_NVLW, _LINK_INTR_2_MASK, _NONFATAL, 0x0) | + DRF_NUM(_NVLW, _LINK_INTR_2_MASK, _CORRECTABLE, 0x0)); +} + +/* + * Reset NPG & NVLW interrupt state. + */ +static void +_nvswitch_link_reset_interrupts_ls10 +( + nvswitch_device *device, + NvU32 link +) +{ + NvU32 regval; + NvU32 eng_instance = link / NVSWITCH_LINKS_PER_NVLIPT_LS10; + NvU32 localLinkNum = link % NVSWITCH_LINKS_PER_NVLIPT_LS10; + + NVSWITCH_NPORT_WR32_LS10(device, link, _NPORT, _ERR_CONTROL_COMMON_NPORT, + DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _CORRECTABLEENABLE, 0x1) | + DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _FATALENABLE, 0x1) | + DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _NONFATALENABLE, 0x1)); + + NVSWITCH_ENG_WR32(device, NVLW, , eng_instance, _NVLW, _LINK_INTR_0_MASK(localLinkNum), + DRF_NUM(_NVLW, _LINK_INTR_0_MASK, _FATAL, 0x1) | + DRF_NUM(_NVLW, _LINK_INTR_0_MASK, _NONFATAL, 0x0) | + DRF_NUM(_NVLW, _LINK_INTR_0_MASK, _CORRECTABLE, 0x0) | + DRF_NUM(_NVLW_LINK, _INTR_0_MASK, _INTR0, 0x1) | + DRF_NUM(_NVLW_LINK, _INTR_0_MASK, _INTR1, 0x0)); + + NVSWITCH_ENG_WR32(device, NVLW, , eng_instance, _NVLW, _LINK_INTR_1_MASK(localLinkNum), + DRF_NUM(_NVLW, _LINK_INTR_1_MASK, _FATAL, 0x0) | + DRF_NUM(_NVLW, _LINK_INTR_1_MASK, _NONFATAL, 0x1) | + DRF_NUM(_NVLW, _LINK_INTR_1_MASK, _CORRECTABLE, 0x1) | + DRF_NUM(_NVLW_LINK, _INTR_0_MASK, _INTR0, 0x0) | + DRF_NUM(_NVLW_LINK, _INTR_0_MASK, _INTR1, 0x1)); + + NVSWITCH_ENG_WR32(device, NVLW, , eng_instance, _NVLW, _LINK_INTR_2_MASK(localLinkNum), + DRF_NUM(_NVLW, _LINK_INTR_2_MASK, _FATAL, 0x0) | + DRF_NUM(_NVLW, _LINK_INTR_2_MASK, _NONFATAL, 0x0) | + DRF_NUM(_NVLW, _LINK_INTR_2_MASK, _CORRECTABLE, 0x0) | + DRF_NUM(_NVLW_LINK, _INTR_2_MASK, _INTR0, 0x0) | + DRF_NUM(_NVLW_LINK, _INTR_2_MASK, _INTR1, 0x0)); + + // NVLIPT_LNK + regval = NVSWITCH_LINK_RD32_LS10(device, link, NVLIPT_LNK, _NVLIPT_LNK, _INTR_CONTROL_LINK); + regval = regval | + DRF_NUM(_NVLIPT_LNK, _INTR_CONTROL_LINK, _INT0_EN, 0x1) | + DRF_NUM(_NVLIPT_LNK, _INTR_CONTROL_LINK, _INT1_EN, 0x1); + NVSWITCH_LINK_WR32_LS10(device, link, NVLIPT_LNK, _NVLIPT_LNK, _INTR_CONTROL_LINK, regval); + + // NVLIPT_LNK_INTR_1 + regval = NVSWITCH_LINK_RD32_LS10(device, link, NVLIPT_LNK, _NVLIPT_LNK, _INTR_INT1_EN); + regval = regval | DRF_NUM(_NVLIPT_LNK, _INTR_INT1_EN, _LINKSTATEREQUESTREADYSET, 0x1); + NVSWITCH_LINK_WR32_LS10(device, link, NVLIPT_LNK, _NVLIPT_LNK, _INTR_INT1_EN, regval); + + // Clear fatal error status + device->link[link].fatal_error_occurred = NV_FALSE; +} + +// +// Data collector which runs on a background thread, collecting latency stats. +// +// The latency counters have a maximum window period of about 12 hours +// (2^48 clk cycles). The counters reset after this period. So SW snaps +// the bins and records latencies every 6 hours. Setting SNAPONDEMAND from 0->1 +// snaps the latency counters and updates them to PRI registers for +// the SW to read. It then resets the counters to start collecting fresh latencies. +// + +void +nvswitch_internal_latency_bin_log_ls10 +( + nvswitch_device *device +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NvU32 idx_nport; + NvU32 idx_vc; + NvBool vc_valid; + NvU64 lo, hi; + NvU64 latency; + NvU64 time_nsec; + NvU32 link_type; // Access or trunk link + NvU64 last_visited_time_nsec; + + if (chip_device->latency_stats == NULL) + { + // Latency stat buffers not allocated yet + return; + } + + time_nsec = nvswitch_os_get_platform_time(); + last_visited_time_nsec = chip_device->latency_stats->last_visited_time_nsec; + + // Update last visited time + chip_device->latency_stats->last_visited_time_nsec = time_nsec; + + // Compare time stamp and reset the counters if the snap is missed + if (!IS_RTLSIM(device) || !IS_FMODEL(device)) + { + if ((last_visited_time_nsec != 0) && + ((time_nsec - last_visited_time_nsec) > + chip_device->latency_stats->sample_interval_msec * NVSWITCH_INTERVAL_1MSEC_IN_NS)) + { + NVSWITCH_PRINT(device, ERROR, + "Latency metrics recording interval missed. Resetting counters.\n"); + _nvswitch_portstat_reset_latency_counters_ls10(device); + return; + } + } + + for (idx_nport=0; idx_nport < NVSWITCH_LINK_COUNT(device); idx_nport++) + { + if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NPORT, idx_nport)) + { + continue; + } + + // Setting SNAPONDEMAND from 0->1 snaps the latencies and resets the counters + NVSWITCH_LINK_WR32_LS10(device, idx_nport, NPORT, _NPORT, _PORTSTAT_SNAP_CONTROL, + DRF_DEF(_NPORT, _PORTSTAT_SNAP_CONTROL, _STARTCOUNTER, _ENABLE) | + DRF_DEF(_NPORT, _PORTSTAT_SNAP_CONTROL, _SNAPONDEMAND, _ENABLE)); + + link_type = NVSWITCH_LINK_RD32_LS10(device, idx_nport, NPORT, _NPORT, _CTRL); + for (idx_vc = 0; idx_vc < NVSWITCH_NUM_VCS_LS10; idx_vc++) + { + vc_valid = NV_FALSE; + + // VC's CREQ0(0) and RSP0(5) are relevant on access links. + if (FLD_TEST_DRF(_NPORT, _CTRL, _TRUNKLINKENB, _ACCESSLINK, link_type) && + ((idx_vc == NV_NPORT_VC_MAPPING_CREQ0) || + (idx_vc == NV_NPORT_VC_MAPPING_RSP0))) + { + vc_valid = NV_TRUE; + } + + // VC's CREQ0(0), RSP0(5), CREQ1(6) and RSP1(7) are relevant on trunk links. + if (FLD_TEST_DRF(_NPORT, _CTRL, _TRUNKLINKENB, _TRUNKLINK, link_type) && + ((idx_vc == NV_NPORT_VC_MAPPING_CREQ0) || + (idx_vc == NV_NPORT_VC_MAPPING_RSP0) || + (idx_vc == NV_NPORT_VC_MAPPING_CREQ1) || + (idx_vc == NV_NPORT_VC_MAPPING_RSP1))) + { + vc_valid = NV_TRUE; + } + + // If the VC is not being used, skip reading it + if (!vc_valid) + { + continue; + } + + lo = NVSWITCH_NPORT_PORTSTAT_RD32_LS10(device, idx_nport, _COUNT, _LOW, _0, idx_vc); + hi = NVSWITCH_NPORT_PORTSTAT_RD32_LS10(device, idx_nport, _COUNT, _LOW, _1, idx_vc); + latency = lo | (hi << 32); + chip_device->latency_stats->latency[idx_vc].accum_latency[idx_nport].low += latency; + + lo = NVSWITCH_NPORT_PORTSTAT_RD32_LS10(device, idx_nport, _COUNT, _MEDIUM, _0, idx_vc); + hi = NVSWITCH_NPORT_PORTSTAT_RD32_LS10(device, idx_nport, _COUNT, _MEDIUM, _1, idx_vc); + chip_device->latency_stats->latency[idx_vc].accum_latency[idx_nport].medium += latency; + latency = lo | (hi << 32); + + lo = NVSWITCH_NPORT_PORTSTAT_RD32_LS10(device, idx_nport, _COUNT, _HIGH, _0, idx_vc); + hi = NVSWITCH_NPORT_PORTSTAT_RD32_LS10(device, idx_nport, _COUNT, _HIGH, _1, idx_vc); + chip_device->latency_stats->latency[idx_vc].accum_latency[idx_nport].high += latency; + latency = lo | (hi << 32); + + lo = NVSWITCH_NPORT_PORTSTAT_RD32_LS10(device, idx_nport, _COUNT, _PANIC, _0, idx_vc); + hi = NVSWITCH_NPORT_PORTSTAT_RD32_LS10(device, idx_nport, _COUNT, _PANIC, _1, idx_vc); + chip_device->latency_stats->latency[idx_vc].accum_latency[idx_nport].panic += latency; + latency = lo | (hi << 32); + + lo = NVSWITCH_NPORT_PORTSTAT_RD32_LS10(device, idx_nport, _PACKET, _COUNT, _0, idx_vc); + hi = NVSWITCH_NPORT_PORTSTAT_RD32_LS10(device, idx_nport, _PACKET, _COUNT, _1, idx_vc); + chip_device->latency_stats->latency[idx_vc].accum_latency[idx_nport].count += latency; + latency = lo | (hi << 32); + + // Note the time of this snap + chip_device->latency_stats->latency[idx_vc].last_read_time_nsec = time_nsec; + chip_device->latency_stats->latency[idx_vc].count++; + } + + // Disable SNAPONDEMAND after fetching the latencies + NVSWITCH_LINK_WR32_LS10(device, idx_nport, NPORT, _NPORT, _PORTSTAT_SNAP_CONTROL, + DRF_DEF(_NPORT, _PORTSTAT_SNAP_CONTROL, _STARTCOUNTER, _ENABLE) | + DRF_DEF(_NPORT, _PORTSTAT_SNAP_CONTROL, _SNAPONDEMAND, _DISABLE)); + } +} + +static NvlStatus +nvswitch_ctrl_set_ganged_link_table_ls10 +( + nvswitch_device *device, + NVSWITCH_SET_GANGED_LINK_TABLE *p +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +void +nvswitch_init_npg_multicast_ls10 +( + nvswitch_device *device +) +{ + NVSWITCH_PRINT(device, WARN, "%s: Function not implemented\n", __FUNCTION__); +} + +void +nvswitch_init_warm_reset_ls10 +( + nvswitch_device *device +) +{ + NVSWITCH_PRINT(device, WARN, "%s: Function not implemented\n", __FUNCTION__); + } + +// +// Implement reset and drain sequence for ls10 +// +NvlStatus +nvswitch_reset_and_drain_links_ls10 +( + nvswitch_device *device, + NvU64 link_mask +) +{ + NvlStatus status = NVL_SUCCESS; + nvlink_link *link_info = NULL; + NvU32 link; + NvU32 data32; + NvU32 retry_count = 3; + NvU32 link_state_request; + NvU32 link_state; + NvU32 stat_data; + NvU32 link_intr_subcode; + + if (link_mask == 0) + { + NVSWITCH_PRINT(device, ERROR, "%s: Invalid link_mask 0\n", + __FUNCTION__); + return -NVL_BAD_ARGS; + } + + // Check for inactive links + FOR_EACH_INDEX_IN_MASK(64, link, link_mask) + { + if (!nvswitch_is_link_valid(device, link)) + { + NVSWITCH_PRINT(device, ERROR, "%s: link #%d invalid\n", + __FUNCTION__, link); + continue; + } + + if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NPORT, link)) + { + NVSWITCH_PRINT(device, ERROR, "%s: NPORT #%d invalid\n", + __FUNCTION__, link); + continue; + } + + if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLW, link)) + { + NVSWITCH_PRINT(device, ERROR, "%s: NVLW #%d invalid\n", + __FUNCTION__, link); + continue; + } + } + FOR_EACH_INDEX_IN_MASK_END; + + FOR_EACH_INDEX_IN_MASK(64, link, link_mask) + { + link_info = nvswitch_get_link(device, link); + if (link_info == NULL) + { + NVSWITCH_PRINT(device, ERROR, "%s: invalid link %d\n", + __FUNCTION__, link); + continue; + } + + // Unregister links to make them unusable while reset is in progress. + nvlink_lib_unregister_link(link_info); + + // + // Step 1.0 : Check NXBAR error state. NXBAR errors are always fatal + // errors and are assumed to require a full power-on reset to recover. + // No incremental recovery is possible after a NXBAR error. + // + data32 = NVSWITCH_NPORT_RD32_LS10(device, link, _EGRESS, _ERR_STATUS_0); + if (FLD_TEST_DRF(_EGRESS, _ERR_STATUS_0, _EGRESSBUFERR, _CLEAR, data32) || + FLD_TEST_DRF(_EGRESS, _ERR_STATUS_0, _SEQIDERR, _CLEAR, data32) || + FLD_TEST_DRF(_EGRESS, _ERR_STATUS_0, _NXBAR_HDR_ECC_LIMIT_ERR, _CLEAR, data32) || + FLD_TEST_DRF(_EGRESS, _ERR_STATUS_0, _NXBAR_HDR_ECC_DBE_ERR, _CLEAR, data32) || + FLD_TEST_DRF(_EGRESS, _ERR_STATUS_0, _NXBAR_HDR_PARITY_ERR, _CLEAR, data32)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Fatal NXBAR error on link %d. Chip reset required\n", + __FUNCTION__, link); + + // Re-register links. + status = nvlink_lib_register_link(device->nvlink_device, link_info); + if (status != NVL_SUCCESS) + { + nvswitch_destroy_link(link_info); + return status; + } + + return -NVL_ERR_INVALID_STATE; + } + + // + // Step 2.0 : Disable NPG & NVLW interrupts + // + _nvswitch_link_disable_interrupts_ls10(device, link); + + // + // Step 3.0 : + // Prior to starting port reset, perform unilateral shutdown on the + // LS10 side of the link, in case the links are not shutdown. + // + nvswitch_execute_unilateral_link_shutdown_ls10(link_info); + nvswitch_corelib_clear_link_state_ls10(link_info); + + // + // Step 4.0 : Send command to SOE to perform the following steps : + // - Backup NPORT state before reset + // - Set the INGRESS_STOP bit of CTRL_STOP (0x48) + // - Assert debug_clear for the given port NPORT by writing to the + // DEBUG_CLEAR (0x144) register + // - Assert NPortWarmReset[i] using the WARMRESET (0x140) register + // + // nvswitch_soe_issue_nport_reset_ls10(device, link); + + // + // Step 5.0 : Issue Minion request to perform the link reset sequence + // We retry the Minion reset sequence 3 times, if we there is an error + // while trying to reset the first few times. Refer Bug 3799577 for + // more details. + // + do + { + status = nvswitch_request_tl_link_state_ls10(link_info, + NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_RESET, NV_TRUE); + + if (status == NVL_SUCCESS) + { + break; + } + else + { + + link_state_request = NVSWITCH_LINK_RD32_LS10(device, link_info->linkNumber, + NVLIPT_LNK , _NVLIPT_LNK , _CTRL_LINK_STATE_REQUEST); + + link_state = DRF_VAL(_NVLIPT_LNK, _CTRL_LINK_STATE_REQUEST, _STATUS, + link_state_request); + + if (nvswitch_minion_get_dl_status(device, link_info->linkNumber, + NV_NVLSTAT_MN00, 0, &stat_data) == NVL_SUCCESS) + { + link_intr_subcode = DRF_VAL(_NVLSTAT, _MN00, _LINK_INTR_SUBCODE, stat_data); + } + + if ((link_state == NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_MINION_REQUEST_FAIL) && + (link_intr_subcode == MINION_ALARM_BUSY)) + { + + status = nvswitch_request_tl_link_state_ls10(link_info, + NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_RESET, NV_TRUE); + + // + // We retry the shutdown sequence 3 times when we see a MINION_REQUEST_FAIL + // or MINION_ALARM_BUSY + // + retry_count--; + } + else + { + break; + } + } + } while(retry_count); + + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: NvLink Reset has failed for link %d\n", + __FUNCTION__, link); + + // Re-register links. + status = nvlink_lib_register_link(device->nvlink_device, link_info); + if (status != NVL_SUCCESS) + { + nvswitch_destroy_link(link_info); + return status; + } + return status; + } + + // + // Step 6.0 : Send command to SOE to perform the following steps : + // - Clear the INGRESS_STOP bit of CTRL_STOP (0x48) + // - Clear the CONTAIN_AND_DRAIN (0x5c) status + // - Assert NPORT INITIALIZATION and program the state tracking RAMS + // - Restore NPORT state after reset + // + // nvswitch_soe_restore_nport_state_ls10(device, link); + + // Step 7.0 : Re-program the routing table for DBEs + + // Step 8.0 : Reset NVLW and NPORT interrupt state + _nvswitch_link_reset_interrupts_ls10(device, link); + + // Re-register links. + status = nvlink_lib_register_link(device->nvlink_device, link_info); + if (status != NVL_SUCCESS) + { + nvswitch_destroy_link(link_info); + return status; + } + + // + // Launch ALI training to re-initialize and train the links + // nvswitch_launch_ALI_link_training(device, link_info); + // + // Request active, but don't block. FM will come back and check + // active link status by blocking on this TLREQ's completion + // + status = nvswitch_request_tl_link_state_ls10(link_info, + NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_ACTIVE, + NV_FALSE); + + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: TL link state request to active for ALI failed for link: 0x%x\n", + __FUNCTION__, link); + } + } + FOR_EACH_INDEX_IN_MASK_END; + + // TODO: CCI Links Support: Reset the CCI links + + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_set_nport_port_config_ls10 +( + nvswitch_device *device, + NVSWITCH_SET_SWITCH_PORT_CONFIG *p +) +{ + NvU32 val; + + if (p->requesterLinkID >= NVBIT( + DRF_SIZE(NV_NPORT_REQLINKID_REQROUTINGID) + + DRF_SIZE(NV_NPORT_REQLINKID_REQROUTINGID_UPPER))) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Invalid requester RID 0x%x\n", + __FUNCTION__, p->requesterLinkID); + return -NVL_BAD_ARGS; + } + + if (p->requesterLanID > DRF_MASK(NV_NPORT_REQLINKID_REQROUTINGLAN)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Invalid requester RLAN 0x%x\n", + __FUNCTION__, p->requesterLanID); + return -NVL_BAD_ARGS; + } + + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _NPORT, _CTRL); + switch (p->type) + { + case CONNECT_ACCESS_GPU: + case CONNECT_ACCESS_CPU: + case CONNECT_ACCESS_SWITCH: + val = FLD_SET_DRF(_NPORT, _CTRL, _TRUNKLINKENB, _ACCESSLINK, val); + break; + case CONNECT_TRUNK_SWITCH: + val = FLD_SET_DRF(_NPORT, _CTRL, _TRUNKLINKENB, _TRUNKLINK, val); + break; + default: + NVSWITCH_PRINT(device, ERROR, + "%s: invalid type #%d\n", + __FUNCTION__, p->type); + return -NVL_BAD_ARGS; + } + + // _ENDPOINT_COUNT deprecated on LS10 + + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _NPORT, _CTRL, val); + + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _NPORT, _REQLINKID, + DRF_NUM(_NPORT, _REQLINKID, _REQROUTINGID, p->requesterLinkID) | + DRF_NUM(_NPORT, _REQLINKID, _REQROUTINGID_UPPER, + p->requesterLinkID >> DRF_SIZE(NV_NPORT_REQLINKID_REQROUTINGID)) | + DRF_NUM(_NPORT, _REQLINKID, _REQROUTINGLAN, p->requesterLanID)); + + if (p->type == CONNECT_TRUNK_SWITCH) + { + if (IS_RTLSIM(device) || IS_EMULATION(device) || IS_FMODEL(device)) + { + // Set trunk specific settings (TPROD) on PRE-SILION + + // NPORT + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _NPORT, _CTRL); + val = FLD_SET_DRF(_NPORT, _CTRL, _EGDRAINENB, _DISABLE, val); + val = FLD_SET_DRF(_NPORT, _CTRL, _ENEGRESSDBI, _ENABLE, val); + val = FLD_SET_DRF(_NPORT, _CTRL, _ENROUTEDBI, _ENABLE, val); + val = FLD_SET_DRF(_NPORT, _CTRL, _RTDRAINENB, _DISABLE, val); + val = FLD_SET_DRF(_NPORT, _CTRL, _SPARE, _INIT, val); + val = FLD_SET_DRF(_NPORT, _CTRL, _TRUNKLINKENB, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _NPORT, _CTRL, val); + + // EGRESS + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _EGRESS, _CTRL); + val = FLD_SET_DRF(_EGRESS, _CTRL, _CTO_ENB, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _EGRESS, _CTRL, val); + + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _EGRESS, _ERR_CONTAIN_EN_0); + val = FLD_SET_DRF(_EGRESS, _ERR_CONTAIN_EN_0, _CREDIT_TIME_OUT_ERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_CONTAIN_EN_0, _HWRSPERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_CONTAIN_EN_0, _INVALIDVCSET_ERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_CONTAIN_EN_0, _REQTGTIDMISMATCHERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_CONTAIN_EN_0, _RSPREQIDMISMATCHERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_CONTAIN_EN_0, _URRSPERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _EGRESS, _ERR_CONTAIN_EN_0, val); + + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _EGRESS, _ERR_FATAL_REPORT_EN_0); + val = FLD_SET_DRF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _CREDIT_TIME_OUT_ERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _HWRSPERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _INVALIDVCSET_ERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _REQTGTIDMISMATCHERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _RSPREQIDMISMATCHERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _URRSPERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _EGRESS, _ERR_FATAL_REPORT_EN_0, val); + + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _EGRESS, _ERR_LOG_EN_0); + val = FLD_SET_DRF(_EGRESS, _ERR_LOG_EN_0, _CREDIT_TIME_OUT_ERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_LOG_EN_0, _HWRSPERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_LOG_EN_0, _INVALIDVCSET_ERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_LOG_EN_0, _REQTGTIDMISMATCHERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_LOG_EN_0, _RSPREQIDMISMATCHERR, __TPROD, val); + val = FLD_SET_DRF(_EGRESS, _ERR_LOG_EN_0, _URRSPERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _EGRESS, _ERR_LOG_EN_0, val); + + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _EGRESS, _ERR_NON_FATAL_REPORT_EN_0); + val = FLD_SET_DRF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _PRIVRSPERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _EGRESS, _ERR_NON_FATAL_REPORT_EN_0, val); + + // INGRESS + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _INGRESS, _ERR_CONTAIN_EN_0); + val = FLD_SET_DRF(_INGRESS, _ERR_CONTAIN_EN_0, _EXTAREMAPTAB_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_CONTAIN_EN_0, _EXTBREMAPTAB_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_CONTAIN_EN_0, _INVALIDVCSET, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_CONTAIN_EN_0, _MCREMAPTAB_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_CONTAIN_EN_0, _REMAPTAB_ECC_DBE_ERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _INGRESS, _ERR_CONTAIN_EN_0, val); + + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _INGRESS, _ERR_FATAL_REPORT_EN_0); + val = FLD_SET_DRF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _EXTAREMAPTAB_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _EXTBREMAPTAB_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _INVALIDVCSET, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _MCREMAPTAB_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _REMAPTAB_ECC_DBE_ERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _INGRESS, _ERR_FATAL_REPORT_EN_0, val); + + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _INGRESS, _ERR_LOG_EN_0); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_0, _EXTAREMAPTAB_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_0, _EXTBREMAPTAB_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_0, _INVALIDVCSET, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_0, _MCREMAPTAB_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_0, _REMAPTAB_ECC_DBE_ERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _INGRESS, _ERR_LOG_EN_0, val); + + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _INGRESS, _ERR_LOG_EN_1); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _EXTAREMAPTAB_ADDRTYPEERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _EXTAREMAPTAB_ECC_LIMIT_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _EXTBREMAPTAB_ADDRTYPEERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _EXTBREMAPTAB_ECC_LIMIT_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _MCCMDTOUCADDRERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _MCREMAPTAB_ADDRTYPEERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _MCREMAPTAB_ECC_LIMIT_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_LOG_EN_1, _READMCREFLECTMEMERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _INGRESS, _ERR_LOG_EN_1, val); + + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _INGRESS, _ERR_NON_FATAL_REPORT_EN_0); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _ACLFAIL, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _ADDRBOUNDSERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _ADDRTYPEERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_ACLFAIL, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_ADDRBOUNDSERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_INDEX_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_REQCONTEXTMISMATCHERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_ACLFAIL, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_ADDRBOUNDSERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_INDEX_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_REQCONTEXTMISMATCHERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_ACLFAIL, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_ADDRBOUNDSERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_INDEX_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_REQCONTEXTMISMATCHERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _REMAPTAB_ECC_LIMIT_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _REQCONTEXTMISMATCHERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _INGRESS, _ERR_NON_FATAL_REPORT_EN_0, val); + + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _INGRESS, _ERR_NON_FATAL_REPORT_EN_1); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _EXTAREMAPTAB_ADDRTYPEERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _EXTAREMAPTAB_ECC_LIMIT_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _EXTBREMAPTAB_ADDRTYPEERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _EXTBREMAPTAB_ECC_LIMIT_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCCMDTOUCADDRERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCREMAPTAB_ADDRTYPEERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCREMAPTAB_ECC_LIMIT_ERR, __TPROD, val); + val = FLD_SET_DRF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _READMCREFLECTMEMERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _INGRESS, _ERR_NON_FATAL_REPORT_EN_1, val); + + // SOURCETRACK + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_CONTAIN_EN_0); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _DUP_CREQ_TCEN0_TAG_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _INVALID_TCEN0_RSP_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _INVALID_TCEN1_RSP_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _SOURCETRACK_TIME_OUT_ERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_CONTAIN_EN_0, val); + + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_FATAL_REPORT_EN_0); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _DUP_CREQ_TCEN0_TAG_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _INVALID_TCEN0_RSP_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _INVALID_TCEN1_RSP_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _SOURCETRACK_TIME_OUT_ERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_FATAL_REPORT_EN_0, val); + + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_LOG_EN_0); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_LOG_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_LOG_EN_0, _DUP_CREQ_TCEN0_TAG_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_LOG_EN_0, _INVALID_TCEN0_RSP_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_LOG_EN_0, _INVALID_TCEN1_RSP_ERR, __TPROD, val); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_LOG_EN_0, _SOURCETRACK_TIME_OUT_ERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_LOG_EN_0, val); + + val = NVSWITCH_LINK_RD32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_NON_FATAL_REPORT_EN_0); + val = FLD_SET_DRF(_SOURCETRACK, _ERR_NON_FATAL_REPORT_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR, __TPROD, val); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _SOURCETRACK, _ERR_NON_FATAL_REPORT_EN_0, val); + } + else + { + // Set trunk specific settings (TPROD) in SOE + // nvswitch_set_nport_tprod_state_ls10(device, p->portNum); + } + } + else + { + // PROD setting assumes ACCESS link + } + + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _NPORT, _SRC_PORT_TYPE0, NvU64_LO32(p->trunkSrcMask)); + NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _NPORT, _SRC_PORT_TYPE1, NvU64_HI32(p->trunkSrcMask)); + + return NVL_SUCCESS; +} + +/* + * @brief Returns the ingress requester link id. + * + * @param[in] device nvswitch device + * @param[in] params NVSWITCH_GET_INGRESS_REQLINKID_PARAMS + * + * @returns NVL_SUCCESS if action succeeded, + * -NVL_ERR_INVALID_STATE invalid link + */ +NvlStatus +nvswitch_ctrl_get_ingress_reqlinkid_ls10 +( + nvswitch_device *device, + NVSWITCH_GET_INGRESS_REQLINKID_PARAMS *params +) +{ + NvU32 regval; + + if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NPORT, params->portNum)) + { + return -NVL_BAD_ARGS; + } + + regval = NVSWITCH_NPORT_RD32_LS10(device, params->portNum, _NPORT, _REQLINKID); + params->requesterLinkID = DRF_VAL(_NPORT, _REQLINKID, _REQROUTINGID, regval) | + (DRF_VAL(_NPORT, _REQLINKID, _REQROUTINGID_UPPER, regval) << + DRF_SIZE(NV_NPORT_REQLINKID_REQROUTINGID)); + + return NVL_SUCCESS; +} + +static NvlStatus +nvswitch_ctrl_get_internal_latency_ls10 +( + nvswitch_device *device, + NVSWITCH_GET_INTERNAL_LATENCY *pLatency +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NvU32 vc_selector = pLatency->vc_selector; + NvU32 idx_nport; + + // Validate VC selector + if (vc_selector >= NVSWITCH_NUM_VCS_LS10) + { + return -NVL_BAD_ARGS; + } + + nvswitch_os_memset(pLatency, 0, sizeof(*pLatency)); + pLatency->vc_selector = vc_selector; + + // Snap up-to-the moment stats + nvswitch_internal_latency_bin_log(device); + + for (idx_nport=0; idx_nport < NVSWITCH_LINK_COUNT(device); idx_nport++) + { + if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NPORT, idx_nport)) + { + continue; + } + + pLatency->egressHistogram[idx_nport].low = + chip_device->latency_stats->latency[vc_selector].accum_latency[idx_nport].low; + pLatency->egressHistogram[idx_nport].medium = + chip_device->latency_stats->latency[vc_selector].accum_latency[idx_nport].medium; + pLatency->egressHistogram[idx_nport].high = + chip_device->latency_stats->latency[vc_selector].accum_latency[idx_nport].high; + pLatency->egressHistogram[idx_nport].panic = + chip_device->latency_stats->latency[vc_selector].accum_latency[idx_nport].panic; + pLatency->egressHistogram[idx_nport].count = + chip_device->latency_stats->latency[vc_selector].accum_latency[idx_nport].count; + } + + pLatency->elapsed_time_msec = + (chip_device->latency_stats->latency[vc_selector].last_read_time_nsec - + chip_device->latency_stats->latency[vc_selector].start_time_nsec)/1000000ULL; + + chip_device->latency_stats->latency[vc_selector].start_time_nsec = + chip_device->latency_stats->latency[vc_selector].last_read_time_nsec; + + chip_device->latency_stats->latency[vc_selector].count = 0; + + // Clear accum_latency[] + for (idx_nport = 0; idx_nport < NVSWITCH_LINK_COUNT(device); idx_nport++) + { + chip_device->latency_stats->latency[vc_selector].accum_latency[idx_nport].low = 0; + chip_device->latency_stats->latency[vc_selector].accum_latency[idx_nport].medium = 0; + chip_device->latency_stats->latency[vc_selector].accum_latency[idx_nport].high = 0; + chip_device->latency_stats->latency[vc_selector].accum_latency[idx_nport].panic = 0; + chip_device->latency_stats->latency[vc_selector].accum_latency[idx_nport].count = 0; + } + + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_ctrl_set_latency_bins_ls10 +( + nvswitch_device *device, + NVSWITCH_SET_LATENCY_BINS *pLatency +) +{ + NvU32 vc_selector; + const NvU32 freq_mhz = 1330; + const NvU32 switchpll_hz = freq_mhz * 1000000ULL; // TODO: Verify this against POR clocks + const NvU32 min_threshold = 10; // Must be > zero to avoid div by zero + const NvU32 max_threshold = 10000; + + // Quick input validation and ns to register value conversion + for (vc_selector = 0; vc_selector < NVSWITCH_NUM_VCS_LS10; vc_selector++) + { + if ((pLatency->bin[vc_selector].lowThreshold > max_threshold) || + (pLatency->bin[vc_selector].lowThreshold < min_threshold) || + (pLatency->bin[vc_selector].medThreshold > max_threshold) || + (pLatency->bin[vc_selector].medThreshold < min_threshold) || + (pLatency->bin[vc_selector].hiThreshold > max_threshold) || + (pLatency->bin[vc_selector].hiThreshold < min_threshold) || + (pLatency->bin[vc_selector].lowThreshold > pLatency->bin[vc_selector].medThreshold) || + (pLatency->bin[vc_selector].medThreshold > pLatency->bin[vc_selector].hiThreshold)) + { + return -NVL_BAD_ARGS; + } + + pLatency->bin[vc_selector].lowThreshold = + switchpll_hz / (1000000000 / pLatency->bin[vc_selector].lowThreshold); + pLatency->bin[vc_selector].medThreshold = + switchpll_hz / (1000000000 / pLatency->bin[vc_selector].medThreshold); + pLatency->bin[vc_selector].hiThreshold = + switchpll_hz / (1000000000 / pLatency->bin[vc_selector].hiThreshold); + + NVSWITCH_PORTSTAT_BCAST_WR32_LS10(device, _LIMIT, _LOW, vc_selector, pLatency->bin[vc_selector].lowThreshold); + NVSWITCH_PORTSTAT_BCAST_WR32_LS10(device, _LIMIT, _MEDIUM, vc_selector, pLatency->bin[vc_selector].medThreshold); + NVSWITCH_PORTSTAT_BCAST_WR32_LS10(device, _LIMIT, _HIGH, vc_selector, pLatency->bin[vc_selector].hiThreshold); + } + + return NVL_SUCCESS; +} + +// +// MODS-only IOCTLS +// + +/* + * REGISTER_READ/_WRITE + * Provides direct access to the MMIO space for trusted clients like MODS. + * This API should not be exposed to unsecure clients. + */ + +/* + * _nvswitch_get_engine_base + * Used by REGISTER_READ/WRITE API. Looks up an engine based on device/instance + * and returns the base address in BAR0. + * + * register_rw_engine [in] REGISTER_RW_ENGINE_* + * instance [in] physical instance of device + * bcast [in] FALSE: find unicast base address + * TRUE: find broadcast base address + * base_addr [out] base address in BAR0 of requested device + * + * Returns NVL_SUCCESS: Device base address successfully found + * else device lookup failed + */ + +static NvlStatus +_nvswitch_get_engine_base_ls10 +( + nvswitch_device *device, + NvU32 register_rw_engine, // REGISTER_RW_ENGINE_* + NvU32 instance, // device instance + NvBool bcast, + NvU32 *base_addr +) +{ + NvU32 base = 0; + ENGINE_DISCOVERY_TYPE_LS10 *engine = NULL; + NvlStatus retval = NVL_SUCCESS; + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + + // Find the engine descriptor matching the request + engine = NULL; + + switch (register_rw_engine) + { + case REGISTER_RW_ENGINE_RAW: + // Special case raw IO + if ((instance != 0) || + (bcast != NV_FALSE)) + { + retval = -NVL_BAD_ARGS; + } + break; + + case REGISTER_RW_ENGINE_FUSE: + case REGISTER_RW_ENGINE_JTAG: + case REGISTER_RW_ENGINE_PMGR: + // + // Legacy devices are always single-instance, unicast-only. + // These manuals are BAR0 offset-based, not IP-based. Treat them + // the same as RAW. + // + if ((instance != 0) || + (bcast != NV_FALSE)) + { + retval = -NVL_BAD_ARGS; + } + register_rw_engine = REGISTER_RW_ENGINE_RAW; + break; + + case REGISTER_RW_ENGINE_SAW: + if (bcast) + { + retval = -NVL_BAD_ARGS; + } + else + { + if (NVSWITCH_ENG_VALID_LS10(device, SAW, instance)) + { + engine = &chip_device->engSAW[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_SOE: + if (bcast) + { + retval = -NVL_BAD_ARGS; + } + else + { + if (NVSWITCH_ENG_VALID_LS10(device, SOE, instance)) + { + engine = &chip_device->engSOE[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_SE: + if (bcast) + { + retval = -NVL_BAD_ARGS; + } + else + { + if (NVSWITCH_ENG_VALID_LS10(device, SE, instance)) + { + engine = &chip_device->engSE[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_CLKS_SYS: + if (bcast) + { + retval = -NVL_BAD_ARGS; + } + else + { + if (NVSWITCH_ENG_VALID_LS10(device, CLKS_SYS, instance)) + { + engine = &chip_device->engCLKS_SYS[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_CLKS_SYSB: + if (bcast) + { + retval = -NVL_BAD_ARGS; + } + else + { + if (NVSWITCH_ENG_VALID_LS10(device, CLKS_SYSB, instance)) + { + engine = &chip_device->engCLKS_SYSB[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_CLKS_P0: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LS10(device, CLKS_P0_BCAST, instance)) + { + engine = &chip_device->engCLKS_P0_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LS10(device, CLKS_P0, instance)) + { + engine = &chip_device->engCLKS_P0[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_XPL: + if (bcast) + { + retval = -NVL_BAD_ARGS; + } + else + { + if (NVSWITCH_ENG_VALID_LS10(device, XPL, instance)) + { + engine = &chip_device->engXPL[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_XTL: + if (bcast) + { + retval = -NVL_BAD_ARGS; + } + else + { + if (NVSWITCH_ENG_VALID_LS10(device, XTL, instance)) + { + engine = &chip_device->engXTL[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_NVLW: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LS10(device, NVLW_BCAST, instance)) + { + engine = &chip_device->engNVLW_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LS10(device, NVLW, instance)) + { + engine = &chip_device->engNVLW[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_MINION: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LS10(device, MINION_BCAST, instance)) + { + engine = &chip_device->engMINION_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LS10(device, MINION, instance)) + { + engine = &chip_device->engMINION[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_NVLIPT: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LS10(device, NVLIPT_BCAST, instance)) + { + engine = &chip_device->engNVLIPT_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LS10(device, NVLIPT, instance)) + { + engine = &chip_device->engNVLIPT[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_NVLTLC: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LS10(device, NVLTLC_BCAST, instance)) + { + engine = &chip_device->engNVLTLC_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LS10(device, NVLTLC, instance)) + { + engine = &chip_device->engNVLTLC[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_NVLTLC_MULTICAST: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LS10(device, NVLTLC_MULTICAST_BCAST, instance)) + { + engine = &chip_device->engNVLTLC_MULTICAST_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LS10(device, NVLTLC_MULTICAST, instance)) + { + engine = &chip_device->engNVLTLC_MULTICAST[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_NPG: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LS10(device, NPG_BCAST, instance)) + { + engine = &chip_device->engNPG_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LS10(device, NPG, instance)) + { + engine = &chip_device->engNPG[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_NPORT: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LS10(device, NPORT_BCAST, instance)) + { + engine = &chip_device->engNPORT_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LS10(device, NPORT, instance)) + { + engine = &chip_device->engNPORT[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_NPORT_MULTICAST: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LS10(device, NPORT_MULTICAST_BCAST, instance)) + { + engine = &chip_device->engNPORT_MULTICAST_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LS10(device, NPORT_MULTICAST, instance)) + { + engine = &chip_device->engNPORT_MULTICAST[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_NVLIPT_LNK: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LS10(device, NVLIPT_LNK_BCAST, instance)) + { + engine = &chip_device->engNVLIPT_LNK_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LS10(device, NVLIPT_LNK, instance)) + { + engine = &chip_device->engNVLIPT_LNK[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_NVLIPT_LNK_MULTICAST: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LS10(device, NVLIPT_LNK_MULTICAST_BCAST, instance)) + { + engine = &chip_device->engNVLIPT_LNK_MULTICAST_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LS10(device, NVLIPT_LNK_MULTICAST, instance)) + { + engine = &chip_device->engNVLIPT_LNK_MULTICAST[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_NVLDL: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LS10(device, NVLDL_BCAST, instance)) + { + engine = &chip_device->engNVLDL_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LS10(device, NVLDL, instance)) + { + engine = &chip_device->engNVLDL[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_NVLDL_MULTICAST: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LS10(device, NVLDL_MULTICAST_BCAST, instance)) + { + engine = &chip_device->engNVLDL_MULTICAST_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LS10(device, NVLDL_MULTICAST, instance)) + { + engine = &chip_device->engNVLDL_MULTICAST[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_NXBAR: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LS10(device, NXBAR_BCAST, instance)) + { + engine = &chip_device->engNXBAR_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LS10(device, NXBAR, instance)) + { + engine = &chip_device->engNXBAR[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_TILE: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LS10(device, TILE_BCAST, instance)) + { + engine = &chip_device->engTILE_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LS10(device, TILE, instance)) + { + engine = &chip_device->engTILE[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_TILE_MULTICAST: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LS10(device, TILE_MULTICAST_BCAST, instance)) + { + engine = &chip_device->engTILE_MULTICAST_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LS10(device, TILE_MULTICAST, instance)) + { + engine = &chip_device->engTILE_MULTICAST[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_TILEOUT: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LS10(device, TILEOUT_BCAST, instance)) + { + engine = &chip_device->engTILEOUT_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LS10(device, TILEOUT, instance)) + { + engine = &chip_device->engTILEOUT[instance]; + } + } + break; + + case REGISTER_RW_ENGINE_TILEOUT_MULTICAST: + if (bcast) + { + if (NVSWITCH_ENG_VALID_LS10(device, TILEOUT_MULTICAST_BCAST, instance)) + { + engine = &chip_device->engTILEOUT_MULTICAST_BCAST[instance]; + } + } + else + { + if (NVSWITCH_ENG_VALID_LS10(device, TILEOUT_MULTICAST, instance)) + { + engine = &chip_device->engTILEOUT_MULTICAST[instance]; + } + } + break; + + default: + NVSWITCH_PRINT(device, ERROR, + "%s: unknown REGISTER_RW_ENGINE 0x%x\n", + __FUNCTION__, + register_rw_engine); + engine = NULL; + break; + } + + if (register_rw_engine == REGISTER_RW_ENGINE_RAW) + { + // Raw IO -- client provides full BAR0 offset + base = 0; + } + else + { + // Check engine descriptor was found and valid + if (engine == NULL) + { + retval = -NVL_BAD_ARGS; + NVSWITCH_PRINT(device, ERROR, + "%s: invalid REGISTER_RW_ENGINE/instance 0x%x(%d)\n", + __FUNCTION__, + register_rw_engine, + instance); + } + else if (!engine->valid) + { + retval = -NVL_UNBOUND_DEVICE; + NVSWITCH_PRINT(device, ERROR, + "%s: REGISTER_RW_ENGINE/instance 0x%x(%d) disabled or invalid\n", + __FUNCTION__, + register_rw_engine, + instance); + } + else + { + if (bcast && (engine->disc_type == DISCOVERY_TYPE_BROADCAST)) + { + // + // Caveat emptor: A read of a broadcast register is + // implementation-specific. + // + base = engine->info.bc.bc_addr; + } + else if ((!bcast) && (engine->disc_type == DISCOVERY_TYPE_UNICAST)) + { + base = engine->info.uc.uc_addr; + } + + if (base == 0) + { + NVSWITCH_PRINT(device, ERROR, + "%s: REGISTER_RW_ENGINE/instance 0x%x(%d) has %s base address 0!\n", + __FUNCTION__, + register_rw_engine, + instance, + (bcast ? "BCAST" : "UNICAST" )); + retval = -NVL_IO_ERROR; + } + } + } + + *base_addr = base; + return retval; +} + +/* + * CTRL_NVSWITCH_REGISTER_READ + * + * This provides direct access to the MMIO space for trusted clients like + * MODS. + * This API should not be exposed to unsecure clients. + */ + +static NvlStatus +nvswitch_ctrl_register_read_ls10 +( + nvswitch_device *device, + NVSWITCH_REGISTER_READ *p +) +{ + NvU32 base; + NvU32 data; + NvlStatus retval = NVL_SUCCESS; + + retval = _nvswitch_get_engine_base_ls10(device, p->engine, p->instance, NV_FALSE, &base); + if (retval != NVL_SUCCESS) + { + return retval; + } + + // Make sure target offset isn't out-of-range + if ((base + p->offset) >= device->nvlink_device->pciInfo.bars[0].barSize) + { + return -NVL_IO_ERROR; + } + + // + // Some legacy device manuals are not 0-based (IP style). + // + data = NVSWITCH_OFF_RD32(device, base + p->offset); + p->val = data; + + return NVL_SUCCESS; +} + +/* + * CTRL_NVSWITCH_REGISTER_WRITE + * + * This provides direct access to the MMIO space for trusted clients like + * MODS. + * This API should not be exposed to unsecure clients. + */ + +static NvlStatus +nvswitch_ctrl_register_write_ls10 +( + nvswitch_device *device, + NVSWITCH_REGISTER_WRITE *p +) +{ + NvU32 base; + NvlStatus retval = NVL_SUCCESS; + + retval = _nvswitch_get_engine_base_ls10(device, p->engine, p->instance, p->bcast, &base); + if (retval != NVL_SUCCESS) + { + return retval; + } + + // Make sure target offset isn't out-of-range + if ((base + p->offset) >= device->nvlink_device->pciInfo.bars[0].barSize) + { + return -NVL_IO_ERROR; + } + + // + // Some legacy device manuals are not 0-based (IP style). + // + NVSWITCH_OFF_WR32(device, base + p->offset, p->val); + + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_get_nvlink_ecc_errors_ls10 +( + nvswitch_device *device, + NVSWITCH_GET_NVLINK_ECC_ERRORS_PARAMS *params +) +{ + NvU32 statData; + NvU8 i, j; + NvlStatus status; + NvBool bLaneReversed; + + nvswitch_os_memset(params->errorLink, 0, sizeof(params->errorLink)); + + FOR_EACH_INDEX_IN_MASK(64, i, params->linkMask) + { + nvlink_link *link; + NVSWITCH_LANE_ERROR *errorLane; + NvU8 offset; + NvBool minion_enabled; + NvU32 sublinkWidth; + + link = nvswitch_get_link(device, i); + sublinkWidth = device->hal.nvswitch_get_sublink_width(device, i); + + if ((link == NULL) || + !NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLDL, link->linkNumber) || + (i >= NVSWITCH_LINK_COUNT(device))) + { + return -NVL_BAD_ARGS; + } + + minion_enabled = nvswitch_is_minion_initialized(device, + NVSWITCH_GET_LINK_ENG_INST(device, link->linkNumber, MINION)); + + bLaneReversed = nvswitch_link_lane_reversed_ls10(device, link->linkNumber); + + for (j = 0; j < NVSWITCH_NUM_LANES_LS10; j++) + { + if (minion_enabled && (j < sublinkWidth)) + { + status = nvswitch_minion_get_dl_status(device, i, + (NV_NVLSTAT_RX12 + j), 0, &statData); + + if (status != NVL_SUCCESS) + { + return status; + } + offset = bLaneReversed ? ((sublinkWidth - 1) - j) : j; + errorLane = ¶ms->errorLink[i].errorLane[offset]; + errorLane->valid = NV_TRUE; + } + else + { + // MINION disabled + statData = 0; + offset = j; + errorLane = ¶ms->errorLink[i].errorLane[offset]; + errorLane->valid = NV_FALSE; + } + + errorLane->eccErrorValue = DRF_VAL(_NVLSTAT, _RX12, _ECC_CORRECTED_ERR_L0_VALUE, statData); + errorLane->overflowed = DRF_VAL(_NVLSTAT, _RX12, _ECC_CORRECTED_ERR_L0_OVER, statData); + } + + if (minion_enabled) + { + status = nvswitch_minion_get_dl_status(device, i, + NV_NVLSTAT_RX11, 0, &statData); + if (status != NVL_SUCCESS) + { + return status; + } + } + else + { + statData = 0; + } + + params->errorLink[i].eccDecFailed = DRF_VAL(_NVLSTAT, _RX11, _ECC_DEC_FAILED_VALUE, statData); + params->errorLink[i].eccDecFailedOverflowed = DRF_VAL(_NVLSTAT, _RX11, _ECC_DEC_FAILED_OVER, statData); + } + FOR_EACH_INDEX_IN_MASK_END; + + return NVL_SUCCESS; +} + +NvU32 +nvswitch_get_num_links_ls10 +( + nvswitch_device *device +) +{ + return NVSWITCH_NUM_LINKS_LS10; +} + + +void +nvswitch_set_fatal_error_ls10 +( + nvswitch_device *device, + NvBool device_fatal, + NvU32 link_id +) +{ + NvU32 reg; + + NVSWITCH_ASSERT(link_id < nvswitch_get_num_links(device)); + + // On first fatal error, notify PORT_DOWN + if (!device->link[link_id].fatal_error_occurred) + { + if (nvswitch_lib_notify_client_events(device, + NVSWITCH_DEVICE_EVENT_PORT_DOWN) != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed to notify PORT_DOWN event\n", + __FUNCTION__); + } + } + + device->link[link_id].fatal_error_occurred = NV_TRUE; + + if (device_fatal) + { + reg = NVSWITCH_SAW_RD32_LS10(device, _NVLSAW, _DRIVER_ATTACH_DETACH); + reg = FLD_SET_DRF_NUM(_NVLSAW, _DRIVER_ATTACH_DETACH, _DEVICE_RESET_REQUIRED, + 1, reg); + + NVSWITCH_SAW_WR32_LS10(device, _NVLSAW, _DRIVER_ATTACH_DETACH, reg); + } + else + { + reg = NVSWITCH_LINK_RD32(device, link_id, NPORT, _NPORT, _SCRATCH_WARM); + reg = FLD_SET_DRF_NUM(_NPORT, _SCRATCH_WARM, _PORT_RESET_REQUIRED, + 1, reg); + + NVSWITCH_LINK_WR32(device, link_id, NPORT, _NPORT, _SCRATCH_WARM, reg); + } +} + +static NvU32 +nvswitch_get_latency_sample_interval_msec_ls10 +( + nvswitch_device *device +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + return chip_device->latency_stats->sample_interval_msec; +} + +static NvU32 +nvswitch_get_device_dma_width_ls10 +( + nvswitch_device *device +) +{ + return DMA_ADDR_WIDTH_LS10; +} + +static NvU32 +nvswitch_get_link_ip_version_ls10 +( + nvswitch_device *device, + NvU32 link_id +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NvU32 nvldl_instance; + + nvldl_instance = NVSWITCH_GET_LINK_ENG_INST(device, link_id, NVLDL); + if (NVSWITCH_ENG_IS_VALID(device, NVLDL, nvldl_instance)) + { + return chip_device->engNVLDL[nvldl_instance].version; + } + else + { + NVSWITCH_PRINT(device, ERROR, + "%s: NVLink[0x%x] NVLDL instance invalid\n", + __FUNCTION__, link_id); + return 0; + } +} + +static NvBool +nvswitch_is_soe_supported_ls10 +( + nvswitch_device *device +) +{ + if (IS_FMODEL(device)) + { + NVSWITCH_PRINT(device, INFO, "SOE is not yet supported on fmodel\n"); + return NV_FALSE; + } + + return NV_TRUE; +} + +NvlStatus +_nvswitch_get_bios_version +( + nvswitch_device *device, + NvU64 *pVersion +) +{ + NVSWITCH_GET_BIOS_INFO_PARAMS p = { 0 }; + NvlStatus status; + + if (pVersion == NULL) + { + return NVL_BAD_ARGS; + } + + status = device->hal.nvswitch_ctrl_get_bios_info(device, &p); + if (status == NVL_SUCCESS) + { + *pVersion = p.version; + } + + return status; +} + +/* + * @Brief : Checks if Inforom is supported + * + */ +NvBool +nvswitch_is_inforom_supported_ls10 +( + nvswitch_device *device +) +{ + NvU64 version; + NvlStatus status; + + if (IS_RTLSIM(device) || IS_EMULATION(device) || IS_FMODEL(device)) + { + NVSWITCH_PRINT(device, INFO, + "INFOROM is not supported on non-silicon platform\n"); + return NV_FALSE; + } + + if (!nvswitch_is_soe_supported(device)) + { + NVSWITCH_PRINT(device, INFO, + "INFOROM is not supported since SOE is not supported\n"); + return NV_FALSE; + } + + status = _nvswitch_get_bios_version(device, &version); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: Error getting BIOS version\n", + __FUNCTION__); + return NV_FALSE; + } + + if (version >= NVSWITCH_IFR_MIN_BIOS_VER_LS10) + { + return NV_TRUE; + } + else + { + NVSWITCH_PRINT(device, WARN, + "INFOROM is not supported on this NVSwitch BIOS version.\n"); + return NV_FALSE; + } +} + +/* + * @Brief : Checks if Spi is supported + * + * Stubbing SOE Spi support on ls10. + * + */ +NvBool +nvswitch_is_spi_supported_ls10 +( + nvswitch_device *device +) +{ + NVSWITCH_PRINT(device, INFO, + "SPI is not supported on LS10\n"); + + return NV_FALSE; +} + +/* + * @Brief : Check if SMBPBI is supported + * + */ +NvBool +nvswitch_is_smbpbi_supported_ls10 +( + nvswitch_device *device +) +{ + NvU64 version; + NvlStatus status; + + if (!nvswitch_is_smbpbi_supported_lr10(device)) + { + return NV_FALSE; + } + + status = _nvswitch_get_bios_version(device, &version); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: Error getting BIOS version\n", + __FUNCTION__); + return NV_FALSE; + } + + if (version >= NVSWITCH_SMBPBI_MIN_BIOS_VER_LS10) + { + return NV_TRUE; + } + else + { + NVSWITCH_PRINT(device, WARN, + "SMBPBI is not supported on NVSwitch BIOS version %llx.\n", version); + return NV_FALSE; + } +} + +/* + * @Brief : Additional setup needed after blacklisted device initialization + * + * @Description : + * + * @param[in] device a reference to the device to initialize + */ +void +nvswitch_post_init_blacklist_device_setup_ls10 +( + nvswitch_device *device +) +{ + NVSWITCH_PRINT(device, WARN, "%s: Function not implemented\n", __FUNCTION__); + return; +} + +/* +* @brief: This function retrieves the NVLIPT public ID for a given global link idx +* @params[in] device reference to current nvswitch device +* @params[in] linkId link to retrieve NVLIPT public ID from +* @params[out] publicId Public ID of NVLIPT owning linkId +*/ +NvlStatus nvswitch_get_link_public_id_ls10 +( + nvswitch_device *device, + NvU32 linkId, + NvU32 *publicId +) +{ + NVSWITCH_PRINT(device, WARN, "%s: Function not implemented\n", __FUNCTION__); + return -NVL_ERR_NOT_IMPLEMENTED; +} + +/* +* @brief: This function retrieves the internal link idx for a given global link idx +* @params[in] device reference to current nvswitch device +* @params[in] linkId link to retrieve NVLIPT public ID from +* @params[out] localLinkIdx Internal link index of linkId +*/ +NvlStatus nvswitch_get_link_local_idx_ls10 +( + nvswitch_device *device, + NvU32 linkId, + NvU32 *localLinkIdx +) +{ + if (!device->hal.nvswitch_is_link_valid(device, linkId) || + (localLinkIdx == NULL)) + { + return -NVL_BAD_ARGS; + } + + *localLinkIdx = NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LS10(linkId); + + return NVL_SUCCESS; +} + +NvlStatus nvswitch_ctrl_get_fatal_error_scope_ls10 +( + nvswitch_device *device, + NVSWITCH_GET_FATAL_ERROR_SCOPE_PARAMS *pParams +) +{ + NvU32 linkId; + NvU32 reg = NVSWITCH_SAW_RD32_LS10(device, _NVLSAW, _DRIVER_ATTACH_DETACH); + pParams->device = FLD_TEST_DRF_NUM(_NVLSAW, _DRIVER_ATTACH_DETACH, _DEVICE_RESET_REQUIRED, + 1, reg); + + for (linkId = 0; linkId < NVSWITCH_MAX_PORTS; linkId++) + { + if (!nvswitch_is_link_valid(device, linkId)) + { + pParams->port[linkId] = NV_FALSE; + continue; + } + + reg = NVSWITCH_LINK_RD32(device, linkId, NPORT, _NPORT, _SCRATCH_WARM); + pParams->port[linkId] = FLD_TEST_DRF_NUM(_NPORT, _SCRATCH_WARM, + _PORT_RESET_REQUIRED, 1, reg); + } + + return NVL_SUCCESS; +} + +/* + * CTRL_NVSWITCH_SET_REMAP_POLICY + */ + +NvlStatus +nvswitch_get_remap_table_selector_ls10 +( + nvswitch_device *device, + NVSWITCH_TABLE_SELECT_REMAP table_selector, + NvU32 *remap_ram_sel +) +{ + NvU32 ram_sel = 0; + + switch (table_selector) + { + case NVSWITCH_TABLE_SELECT_REMAP_PRIMARY: + ram_sel = NV_INGRESS_REQRSPMAPADDR_RAM_SEL_SELECTSNORMREMAPRAM; + break; + case NVSWITCH_TABLE_SELECT_REMAP_EXTA: + ram_sel = NV_INGRESS_REQRSPMAPADDR_RAM_SEL_SELECTSEXTAREMAPRAM; + break; + case NVSWITCH_TABLE_SELECT_REMAP_EXTB: + ram_sel = NV_INGRESS_REQRSPMAPADDR_RAM_SEL_SELECTSEXTBREMAPRAM; + break; + case NVSWITCH_TABLE_SELECT_REMAP_MULTICAST: + ram_sel = NV_INGRESS_REQRSPMAPADDR_RAM_SEL_SELECT_MULTICAST_REMAPRAM; + break; + default: + NVSWITCH_PRINT(device, ERROR, "%s: invalid remap table selector (0x%x)\n", + __FUNCTION__, table_selector); + return -NVL_ERR_NOT_SUPPORTED; + break; + } + + if (remap_ram_sel) + { + *remap_ram_sel = ram_sel; + } + + return NVL_SUCCESS; +} + +NvU32 +nvswitch_get_ingress_ram_size_ls10 +( + nvswitch_device *device, + NvU32 ingress_ram_selector // NV_INGRESS_REQRSPMAPADDR_RAM_SEL_SELECT* +) +{ + NvU32 ram_size = 0; + + switch (ingress_ram_selector) + { + case NV_INGRESS_REQRSPMAPADDR_RAM_SEL_SELECTSNORMREMAPRAM: + ram_size = NV_INGRESS_REQRSPMAPADDR_RAM_ADDRESS_NORMREMAPTAB_DEPTH + 1; + break; + case NV_INGRESS_REQRSPMAPADDR_RAM_SEL_SELECTSEXTAREMAPRAM: + ram_size = NV_INGRESS_REQRSPMAPADDR_RAM_ADDRESS_EXTAREMAPTAB_DEPTH + 1; + break; + case NV_INGRESS_REQRSPMAPADDR_RAM_SEL_SELECTSEXTBREMAPRAM: + ram_size = NV_INGRESS_REQRSPMAPADDR_RAM_ADDRESS_EXTBREMAPTAB_DEPTH + 1; + break; + case NV_INGRESS_REQRSPMAPADDR_RAM_SEL_SELECTSRIDROUTERAM: + ram_size = NV_INGRESS_REQRSPMAPADDR_RAM_ADDRESS_RID_TAB_DEPTH + 1; + break; + case NV_INGRESS_REQRSPMAPADDR_RAM_SEL_SELECTSRLANROUTERAM: + ram_size = NV_INGRESS_REQRSPMAPADDR_RAM_ADDRESS_RLAN_TAB_DEPTH + 1; + break; + case NV_INGRESS_REQRSPMAPADDR_RAM_SEL_SELECT_MULTICAST_REMAPRAM: + ram_size = NV_INGRESS_MCREMAPTABADDR_RAM_ADDRESS_MCREMAPTAB_DEPTH + 1; + break; + default: + NVSWITCH_PRINT(device, ERROR, "%s: Unsupported ingress RAM selector (0x%x)\n", + __FUNCTION__, ingress_ram_selector); + break; + } + + return ram_size; +} + +static void +_nvswitch_set_remap_policy_ls10 +( + nvswitch_device *device, + NvU32 portNum, + NvU32 remap_ram_sel, + NvU32 firstIndex, + NvU32 numEntries, + NVSWITCH_REMAP_POLICY_ENTRY *remap_policy +) +{ + NvU32 i; + NvU32 remap_address; + NvU32 address_base; + NvU32 address_limit; + NvU32 rfunc; + + NVSWITCH_LINK_WR32_LS10(device, portNum, NPORT, _INGRESS, _REQRSPMAPADDR, + DRF_NUM(_INGRESS, _REQRSPMAPADDR, _RAM_ADDRESS, firstIndex) | + DRF_NUM(_INGRESS, _REQRSPMAPADDR, _RAM_SEL, remap_ram_sel) | + DRF_DEF(_INGRESS, _REQRSPMAPADDR, _AUTO_INCR, _ENABLE)); + + for (i = 0; i < numEntries; i++) + { + // Set each field if enabled, else set it to 0. + remap_address = DRF_VAL64(_INGRESS, _REMAP, _ADDR_PHYS_LS10, remap_policy[i].address); + address_base = DRF_VAL64(_INGRESS, _REMAP, _ADR_BASE_PHYS_LS10, remap_policy[i].addressBase); + address_limit = DRF_VAL64(_INGRESS, _REMAP, _ADR_LIMIT_PHYS_LS10, remap_policy[i].addressLimit); + rfunc = remap_policy[i].flags & + ( + NVSWITCH_REMAP_POLICY_FLAGS_REMAP_ADDR | + NVSWITCH_REMAP_POLICY_FLAGS_REQCTXT_CHECK | + NVSWITCH_REMAP_POLICY_FLAGS_REQCTXT_REPLACE | + NVSWITCH_REMAP_POLICY_FLAGS_ADR_BASE | + NVSWITCH_REMAP_POLICY_FLAGS_ADDR_TYPE + ); + // Handle re-used RFUNC[5] conflict between Limerock and Laguna Seca + if (rfunc & NVSWITCH_REMAP_POLICY_FLAGS_ADDR_TYPE) + { + // + // RFUNC[5] Limerock functionality was deprecated and replaced with + // a new function in Laguna Seca. So fix RFUNC if needed. + // + + rfunc &= ~NVSWITCH_REMAP_POLICY_FLAGS_ADDR_TYPE; + rfunc |= NVBIT(5); + } + + NVSWITCH_LINK_WR32_LS10(device, portNum, NPORT, _INGRESS, _REMAPTABDATA1, + DRF_NUM(_INGRESS, _REMAPTABDATA1, _REQCTXT_MSK, remap_policy[i].reqCtxMask) | + DRF_NUM(_INGRESS, _REMAPTABDATA1, _REQCTXT_CHK, remap_policy[i].reqCtxChk)); + NVSWITCH_LINK_WR32_LS10(device, portNum, NPORT, _INGRESS, _REMAPTABDATA2, + DRF_NUM(_INGRESS, _REMAPTABDATA2, _REQCTXT_REP, remap_policy[i].reqCtxRep)); + NVSWITCH_LINK_WR32_LS10(device, portNum, NPORT, _INGRESS, _REMAPTABDATA3, + DRF_NUM(_INGRESS, _REMAPTABDATA3, _ADR_BASE, address_base) | + DRF_NUM(_INGRESS, _REMAPTABDATA3, _ADR_LIMIT, address_limit)); + NVSWITCH_LINK_WR32_LS10(device, portNum, NPORT, _INGRESS, _REMAPTABDATA4, + DRF_NUM(_INGRESS, _REMAPTABDATA4, _TGTID, remap_policy[i].targetId) | + DRF_NUM(_INGRESS, _REMAPTABDATA4, _RFUNC, rfunc)); + // Get the upper bits of address_base/_limit + NVSWITCH_LINK_WR32_LS10(device, portNum, NPORT, _INGRESS, _REMAPTABDATA5, + DRF_NUM(_INGRESS, _REMAPTABDATA5, _ADR_BASE, + (address_base >> DRF_SIZE(NV_INGRESS_REMAPTABDATA3_ADR_BASE))) | + DRF_NUM(_INGRESS, _REMAPTABDATA5, _ADR_LIMIT, + (address_limit >> DRF_SIZE(NV_INGRESS_REMAPTABDATA3_ADR_LIMIT)))); + + // Write last and auto-increment + NVSWITCH_LINK_WR32_LS10(device, portNum, NPORT, _INGRESS, _REMAPTABDATA0, + DRF_NUM(_INGRESS, _REMAPTABDATA0, _RMAP_ADDR, remap_address) | + DRF_NUM(_INGRESS, _REMAPTABDATA0, _IRL_SEL, remap_policy[i].irlSelect) | + DRF_NUM(_INGRESS, _REMAPTABDATA0, _ACLVALID, remap_policy[i].entryValid)); + } +} + +static void +_nvswitch_set_mc_remap_policy_ls10 +( + nvswitch_device *device, + NvU32 portNum, + NvU32 firstIndex, + NvU32 numEntries, + NVSWITCH_REMAP_POLICY_ENTRY *remap_policy +) +{ + NvU32 i; + NvU32 remap_address; + NvU32 address_base; + NvU32 address_limit; + NvU32 rfunc; + NvU32 reflective; + + NVSWITCH_LINK_WR32_LS10(device, portNum, NPORT, _INGRESS, _MCREMAPTABADDR, + DRF_NUM(_INGRESS, _MCREMAPTABADDR, _RAM_ADDRESS, firstIndex) | + DRF_DEF(_INGRESS, _MCREMAPTABADDR, _AUTO_INCR, _ENABLE)); + + for (i = 0; i < numEntries; i++) + { + // Set each field if enabled, else set it to 0. + remap_address = DRF_VAL64(_INGRESS, _REMAP, _ADDR_PHYS_LS10, remap_policy[i].address); + address_base = DRF_VAL64(_INGRESS, _REMAP, _ADR_BASE_PHYS_LS10, remap_policy[i].addressBase); + address_limit = DRF_VAL64(_INGRESS, _REMAP, _ADR_LIMIT_PHYS_LS10, remap_policy[i].addressLimit); + rfunc = remap_policy[i].flags & + ( + NVSWITCH_REMAP_POLICY_FLAGS_REMAP_ADDR | + NVSWITCH_REMAP_POLICY_FLAGS_REQCTXT_CHECK | + NVSWITCH_REMAP_POLICY_FLAGS_REQCTXT_REPLACE | + NVSWITCH_REMAP_POLICY_FLAGS_ADR_BASE | + NVSWITCH_REMAP_POLICY_FLAGS_ADDR_TYPE + ); + // Handle re-used RFUNC[5] conflict between Limerock and Laguna Seca + if (rfunc & NVSWITCH_REMAP_POLICY_FLAGS_ADDR_TYPE) + { + // + // RFUNC[5] Limerock functionality was deprecated and replaced with + // a new function in Laguna Seca. So fix RFUNC if needed. + // + + rfunc &= ~NVSWITCH_REMAP_POLICY_FLAGS_ADDR_TYPE; + rfunc |= NVBIT(5); + } + reflective = (remap_policy[i].flags & NVSWITCH_REMAP_POLICY_FLAGS_REFLECTIVE ? 1 : 0); + + NVSWITCH_LINK_WR32_LS10(device, portNum, NPORT, _INGRESS, _MCREMAPTABDATA1, + DRF_NUM(_INGRESS, _MCREMAPTABDATA1, _REQCTXT_MSK, remap_policy[i].reqCtxMask) | + DRF_NUM(_INGRESS, _MCREMAPTABDATA1, _REQCTXT_CHK, remap_policy[i].reqCtxChk)); + NVSWITCH_LINK_WR32_LS10(device, portNum, NPORT, _INGRESS, _MCREMAPTABDATA2, + DRF_NUM(_INGRESS, _MCREMAPTABDATA2, _REQCTXT_REP, remap_policy[i].reqCtxRep)); + NVSWITCH_LINK_WR32_LS10(device, portNum, NPORT, _INGRESS, _MCREMAPTABDATA3, + DRF_NUM(_INGRESS, _MCREMAPTABDATA3, _ADR_BASE, address_base) | + DRF_NUM(_INGRESS, _MCREMAPTABDATA3, _ADR_LIMIT, address_limit)); + NVSWITCH_LINK_WR32_LS10(device, portNum, NPORT, _INGRESS, _MCREMAPTABDATA4, + DRF_NUM(_INGRESS, _MCREMAPTABDATA4, _MCID, remap_policy[i].targetId) | + DRF_NUM(_INGRESS, _MCREMAPTABDATA4, _RFUNC, rfunc) | + DRF_NUM(_INGRESS, _MCREMAPTABDATA4, _ENB_REFLECT_MEM, reflective)); + // Get the upper bits of address_base/_limit + NVSWITCH_LINK_WR32_LS10(device, portNum, NPORT, _INGRESS, _MCREMAPTABDATA5, + DRF_NUM(_INGRESS, _MCREMAPTABDATA5, _ADR_BASE, + (address_base >> DRF_SIZE(NV_INGRESS_MCREMAPTABDATA3_ADR_BASE))) | + DRF_NUM(_INGRESS, _MCREMAPTABDATA5, _ADR_LIMIT, + (address_limit >> DRF_SIZE(NV_INGRESS_MCREMAPTABDATA3_ADR_LIMIT)))); + + // Write last and auto-increment + NVSWITCH_LINK_WR32_LS10(device, portNum, NPORT, _INGRESS, _MCREMAPTABDATA0, + DRF_NUM(_INGRESS, _MCREMAPTABDATA0, _RMAP_ADDR, remap_address) | + DRF_NUM(_INGRESS, _MCREMAPTABDATA0, _IRL_SEL, remap_policy[i].irlSelect) | + DRF_NUM(_INGRESS, _MCREMAPTABDATA0, _ACLVALID, remap_policy[i].entryValid)); + } +} + +NvlStatus +nvswitch_ctrl_set_remap_policy_ls10 +( + nvswitch_device *device, + NVSWITCH_SET_REMAP_POLICY *p +) +{ + NvU32 i; + NvU32 rfunc; + NvU32 remap_ram_sel = ~0; + NvU32 ram_size; + NvlStatus retval = NVL_SUCCESS; + + // + // This function is used to read both normal and multicast REMAP table, + // so guarantee table definitions are identical. + // + ct_assert(DRF_SIZE(NV_INGRESS_REMAPTABDATA0_RMAP_ADDR) == DRF_SIZE(NV_INGRESS_MCREMAPTABDATA0_RMAP_ADDR)); + ct_assert(DRF_SIZE(NV_INGRESS_REMAPTABDATA0_IRL_SEL) == DRF_SIZE(NV_INGRESS_MCREMAPTABDATA0_IRL_SEL)); + ct_assert(DRF_SIZE(NV_INGRESS_REMAPTABDATA1_REQCTXT_MSK) == DRF_SIZE(NV_INGRESS_MCREMAPTABDATA1_REQCTXT_MSK)); + ct_assert(DRF_SIZE(NV_INGRESS_REMAPTABDATA1_REQCTXT_CHK) == DRF_SIZE(NV_INGRESS_MCREMAPTABDATA1_REQCTXT_CHK)); + ct_assert(DRF_SIZE(NV_INGRESS_REMAPTABDATA2_REQCTXT_REP) == DRF_SIZE(NV_INGRESS_MCREMAPTABDATA2_REQCTXT_REP)); + ct_assert(DRF_SIZE(NV_INGRESS_REMAPTABDATA3_ADR_BASE) == DRF_SIZE(NV_INGRESS_MCREMAPTABDATA3_ADR_BASE)); + ct_assert(DRF_SIZE(NV_INGRESS_REMAPTABDATA3_ADR_LIMIT) == DRF_SIZE(NV_INGRESS_MCREMAPTABDATA3_ADR_LIMIT)); + ct_assert(DRF_SIZE(NV_INGRESS_REMAPTABDATA4_RFUNC) == DRF_SIZE(NV_INGRESS_MCREMAPTABDATA4_RFUNC)); + ct_assert(DRF_SIZE(NV_INGRESS_REMAPTABDATA5_ADR_BASE) == DRF_SIZE(NV_INGRESS_MCREMAPTABDATA5_ADR_BASE)); + ct_assert(DRF_SIZE(NV_INGRESS_REMAPTABDATA5_ADR_LIMIT) == DRF_SIZE(NV_INGRESS_MCREMAPTABDATA5_ADR_LIMIT)); + + if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NPORT, p->portNum)) + { + NVSWITCH_PRINT(device, ERROR, + "NPORT port #%d not valid\n", + p->portNum); + return -NVL_BAD_ARGS; + } + + retval = nvswitch_get_remap_table_selector(device, p->tableSelect, &remap_ram_sel); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "Remap table #%d not supported\n", + p->tableSelect); + return retval; + } + ram_size = nvswitch_get_ingress_ram_size(device, remap_ram_sel); + + if ((p->firstIndex >= ram_size) || + (p->numEntries > NVSWITCH_REMAP_POLICY_ENTRIES_MAX) || + (p->firstIndex + p->numEntries > ram_size)) + { + NVSWITCH_PRINT(device, ERROR, + "remapPolicy[%d..%d] overflows range %d..%d or size %d.\n", + p->firstIndex, p->firstIndex + p->numEntries - 1, + 0, ram_size - 1, + NVSWITCH_REMAP_POLICY_ENTRIES_MAX); + return -NVL_BAD_ARGS; + } + + for (i = 0; i < p->numEntries; i++) + { + if (p->tableSelect == NVSWITCH_TABLE_SELECT_REMAP_MULTICAST) + { + if (p->remapPolicy[i].targetId & + ~DRF_MASK(NV_INGRESS_MCREMAPTABDATA4_MCID)) + { + NVSWITCH_PRINT(device, ERROR, + "remapPolicy[%d].targetId 0x%x out of valid MCID range (0x%x..0x%x)\n", + i, p->remapPolicy[i].targetId, + 0, DRF_MASK(NV_INGRESS_MCREMAPTABDATA4_MCID)); + return -NVL_BAD_ARGS; + } + } + else + { + if (p->remapPolicy[i].targetId & + ~DRF_MASK(NV_INGRESS_REMAPTABDATA4_TGTID)) + { + NVSWITCH_PRINT(device, ERROR, + "remapPolicy[%d].targetId 0x%x out of valid TGTID range (0x%x..0x%x)\n", + i, p->remapPolicy[i].targetId, + 0, DRF_MASK(NV_INGRESS_REMAPTABDATA4_TGTID)); + return -NVL_BAD_ARGS; + } + } + + if (p->remapPolicy[i].irlSelect & + ~DRF_MASK(NV_INGRESS_REMAPTABDATA0_IRL_SEL)) + { + NVSWITCH_PRINT(device, ERROR, + "remapPolicy[%d].irlSelect 0x%x out of valid range (0x%x..0x%x)\n", + i, p->remapPolicy[i].irlSelect, + 0, DRF_MASK(NV_INGRESS_REMAPTABDATA0_IRL_SEL)); + return -NVL_BAD_ARGS; + } + + rfunc = p->remapPolicy[i].flags & + ( + NVSWITCH_REMAP_POLICY_FLAGS_REMAP_ADDR | + NVSWITCH_REMAP_POLICY_FLAGS_REQCTXT_CHECK | + NVSWITCH_REMAP_POLICY_FLAGS_REQCTXT_REPLACE | + NVSWITCH_REMAP_POLICY_FLAGS_ADR_BASE | + NVSWITCH_REMAP_POLICY_FLAGS_ADDR_TYPE | + NVSWITCH_REMAP_POLICY_FLAGS_REFLECTIVE + ); + if (rfunc != p->remapPolicy[i].flags) + { + NVSWITCH_PRINT(device, ERROR, + "remapPolicy[%d].flags 0x%x has undefined flags (0x%x)\n", + i, p->remapPolicy[i].flags, + p->remapPolicy[i].flags ^ rfunc); + return -NVL_BAD_ARGS; + } + if ((rfunc & NVSWITCH_REMAP_POLICY_FLAGS_REFLECTIVE) && + (p->tableSelect != NVSWITCH_TABLE_SELECT_REMAP_MULTICAST)) + { + NVSWITCH_PRINT(device, ERROR, + "remapPolicy[%d].flags: REFLECTIVE mapping only supported for MC REMAP\n", + i); + return -NVL_BAD_ARGS; + } + + // Validate that only bits 51:39 are used + if (p->remapPolicy[i].address & + ~DRF_SHIFTMASK64(NV_INGRESS_REMAP_ADDR_PHYS_LS10)) + { + NVSWITCH_PRINT(device, ERROR, + "remapPolicy[%d].address 0x%llx & ~0x%llx != 0\n", + i, p->remapPolicy[i].address, + DRF_SHIFTMASK64(NV_INGRESS_REMAP_ADDR_PHYS_LS10)); + return -NVL_BAD_ARGS; + } + + if (p->remapPolicy[i].reqCtxMask & + ~DRF_MASK(NV_INGRESS_REMAPTABDATA1_REQCTXT_MSK)) + { + NVSWITCH_PRINT(device, ERROR, + "remapPolicy[%d].reqCtxMask 0x%x out of valid range (0x%x..0x%x)\n", + i, p->remapPolicy[i].reqCtxMask, + 0, DRF_MASK(NV_INGRESS_REMAPTABDATA1_REQCTXT_MSK)); + return -NVL_BAD_ARGS; + } + + if (p->remapPolicy[i].reqCtxChk & + ~DRF_MASK(NV_INGRESS_REMAPTABDATA1_REQCTXT_CHK)) + { + NVSWITCH_PRINT(device, ERROR, + "remapPolicy[%d].reqCtxChk 0x%x out of valid range (0x%x..0x%x)\n", + i, p->remapPolicy[i].reqCtxChk, + 0, DRF_MASK(NV_INGRESS_REMAPTABDATA1_REQCTXT_CHK)); + return -NVL_BAD_ARGS; + } + + if (p->remapPolicy[i].reqCtxRep & + ~DRF_MASK(NV_INGRESS_REMAPTABDATA2_REQCTXT_REP)) + { + NVSWITCH_PRINT(device, ERROR, + "remapPolicy[%d].reqCtxRep 0x%x out of valid range (0x%x..0x%x)\n", + i, p->remapPolicy[i].reqCtxRep, + 0, DRF_MASK(NV_INGRESS_REMAPTABDATA2_REQCTXT_REP)); + return -NVL_BAD_ARGS; + } + + // Validate that only bits 38:21 are used + if (p->remapPolicy[i].addressBase & + ~DRF_SHIFTMASK64(NV_INGRESS_REMAP_ADR_BASE_PHYS_LS10)) + { + NVSWITCH_PRINT(device, ERROR, + "remapPolicy[%d].addressBase 0x%llx & ~0x%llx != 0\n", + i, p->remapPolicy[i].addressBase, + DRF_SHIFTMASK64(NV_INGRESS_REMAP_ADR_BASE_PHYS_LS10)); + return -NVL_BAD_ARGS; + } + + // Validate that only bits 38:21 are used + if (p->remapPolicy[i].addressLimit & + ~DRF_SHIFTMASK64(NV_INGRESS_REMAP_ADR_LIMIT_PHYS_LS10)) + { + NVSWITCH_PRINT(device, ERROR, + "remapPolicy[%d].addressLimit 0x%llx & ~0x%llx != 0\n", + i, p->remapPolicy[i].addressLimit, + DRF_SHIFTMASK64(NV_INGRESS_REMAP_ADR_LIMIT_PHYS_LS10)); + return -NVL_BAD_ARGS; + } + + // Validate base & limit describe a region + if (p->remapPolicy[i].addressBase > p->remapPolicy[i].addressLimit) + { + NVSWITCH_PRINT(device, ERROR, + "remapPolicy[%d].addressBase/Limit invalid: 0x%llx > 0x%llx\n", + i, p->remapPolicy[i].addressBase, p->remapPolicy[i].addressLimit); + return -NVL_BAD_ARGS; + } + + // Validate limit - base doesn't overflow 64G + if ((p->remapPolicy[i].addressLimit - p->remapPolicy[i].addressBase) & + ~DRF_SHIFTMASK64(NV_INGRESS_REMAP_ADR_OFFSET_PHYS_LS10)) + { + NVSWITCH_PRINT(device, ERROR, + "remapPolicy[%d].addressLimit 0x%llx - addressBase 0x%llx overflows 64GB\n", + i, p->remapPolicy[i].addressLimit, p->remapPolicy[i].addressBase); + return -NVL_BAD_ARGS; + } + + // AddressOffset is deprecated in LS10 and later + if (p->remapPolicy[i].addressOffset != 0) + { + NVSWITCH_PRINT(device, ERROR, + "remapPolicy[%d].addressOffset deprecated\n", + i); + return -NVL_BAD_ARGS; + } + } + + if (p->tableSelect == NVSWITCH_TABLE_SELECT_REMAP_MULTICAST) + { + _nvswitch_set_mc_remap_policy_ls10(device, p->portNum, p->firstIndex, p->numEntries, p->remapPolicy); + } + else + { + _nvswitch_set_remap_policy_ls10(device, p->portNum, remap_ram_sel, p->firstIndex, p->numEntries, p->remapPolicy); + } + + return retval; +} + +/* + * CTRL_NVSWITCH_GET_REMAP_POLICY + */ + +#define NVSWITCH_NUM_REMAP_POLICY_REGS_LS10 6 + +NvlStatus +nvswitch_ctrl_get_remap_policy_ls10 +( + nvswitch_device *device, + NVSWITCH_GET_REMAP_POLICY_PARAMS *params +) +{ + NVSWITCH_REMAP_POLICY_ENTRY *remap_policy; + NvU32 remap_policy_data[NVSWITCH_NUM_REMAP_POLICY_REGS_LS10]; // 6 word/REMAP table entry + NvU32 table_index; + NvU32 remap_count; + NvU32 remap_address; + NvU32 address_base; + NvU32 address_limit; + NvU32 remap_ram_sel; + NvU32 ram_size; + NvlStatus retval; + + if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NPORT, params->portNum)) + { + NVSWITCH_PRINT(device, ERROR, + "NPORT port #%d not valid\n", + params->portNum); + return -NVL_BAD_ARGS; + } + + retval = nvswitch_get_remap_table_selector(device, params->tableSelect, &remap_ram_sel); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "Remap table #%d not supported\n", + params->tableSelect); + return retval; + } + + ram_size = nvswitch_get_ingress_ram_size(device, remap_ram_sel); + if ((params->firstIndex >= ram_size)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: remapPolicy first index %d out of range[%d..%d].\n", + __FUNCTION__, params->firstIndex, 0, ram_size - 1); + return -NVL_BAD_ARGS; + } + + nvswitch_os_memset(params->entry, 0, (NVSWITCH_REMAP_POLICY_ENTRIES_MAX * + sizeof(NVSWITCH_REMAP_POLICY_ENTRY))); + + table_index = params->firstIndex; + remap_policy = params->entry; + remap_count = 0; + + /* set table offset */ + if (params->tableSelect == NVSWITCH_TABLE_SELECT_REMAP_MULTICAST) + { + NVSWITCH_LINK_WR32_LS10(device, params->portNum, NPORT, _INGRESS, _MCREMAPTABADDR, + DRF_NUM(_INGRESS, _MCREMAPTABADDR, _RAM_ADDRESS, params->firstIndex) | + DRF_DEF(_INGRESS, _MCREMAPTABADDR, _AUTO_INCR, _ENABLE)); + } + else + { + NVSWITCH_LINK_WR32_LS10(device, params->portNum, NPORT, _INGRESS, _REQRSPMAPADDR, + DRF_NUM(_INGRESS, _REQRSPMAPADDR, _RAM_ADDRESS, params->firstIndex) | + DRF_NUM(_INGRESS, _REQRSPMAPADDR, _RAM_SEL, remap_ram_sel) | + DRF_DEF(_INGRESS, _REQRSPMAPADDR, _AUTO_INCR, _ENABLE)); + } + + while (remap_count < NVSWITCH_REMAP_POLICY_ENTRIES_MAX && + table_index < ram_size) + { + if (params->tableSelect == NVSWITCH_TABLE_SELECT_REMAP_MULTICAST) + { + remap_policy_data[0] = NVSWITCH_LINK_RD32_LS10(device, params->portNum, NPORT, _INGRESS, _MCREMAPTABDATA0); + remap_policy_data[1] = NVSWITCH_LINK_RD32_LS10(device, params->portNum, NPORT, _INGRESS, _MCREMAPTABDATA1); + remap_policy_data[2] = NVSWITCH_LINK_RD32_LS10(device, params->portNum, NPORT, _INGRESS, _MCREMAPTABDATA2); + remap_policy_data[3] = NVSWITCH_LINK_RD32_LS10(device, params->portNum, NPORT, _INGRESS, _MCREMAPTABDATA3); + remap_policy_data[4] = NVSWITCH_LINK_RD32_LS10(device, params->portNum, NPORT, _INGRESS, _MCREMAPTABDATA4); + remap_policy_data[5] = NVSWITCH_LINK_RD32_LS10(device, params->portNum, NPORT, _INGRESS, _MCREMAPTABDATA5); + } + else + { + remap_policy_data[0] = NVSWITCH_LINK_RD32_LS10(device, params->portNum, NPORT, _INGRESS, _REMAPTABDATA0); + remap_policy_data[1] = NVSWITCH_LINK_RD32_LS10(device, params->portNum, NPORT, _INGRESS, _REMAPTABDATA1); + remap_policy_data[2] = NVSWITCH_LINK_RD32_LS10(device, params->portNum, NPORT, _INGRESS, _REMAPTABDATA2); + remap_policy_data[3] = NVSWITCH_LINK_RD32_LS10(device, params->portNum, NPORT, _INGRESS, _REMAPTABDATA3); + remap_policy_data[4] = NVSWITCH_LINK_RD32_LS10(device, params->portNum, NPORT, _INGRESS, _REMAPTABDATA4); + remap_policy_data[5] = NVSWITCH_LINK_RD32_LS10(device, params->portNum, NPORT, _INGRESS, _REMAPTABDATA5); + } + + /* add to remap_entries list if nonzero */ + if (remap_policy_data[0] || remap_policy_data[1] || remap_policy_data[2] || + remap_policy_data[3] || remap_policy_data[4] || remap_policy_data[5]) + { + remap_policy[remap_count].irlSelect = + DRF_VAL(_INGRESS, _REMAPTABDATA0, _IRL_SEL, remap_policy_data[0]); + + remap_policy[remap_count].entryValid = + DRF_VAL(_INGRESS, _REMAPTABDATA0, _ACLVALID, remap_policy_data[0]); + + remap_address = + DRF_VAL(_INGRESS, _REMAPTABDATA0, _RMAP_ADDR, remap_policy_data[0]); + + remap_policy[remap_count].address = + DRF_NUM64(_INGRESS, _REMAP, _ADDR_PHYS_LS10, remap_address); + + remap_policy[remap_count].reqCtxMask = + DRF_VAL(_INGRESS, _REMAPTABDATA1, _REQCTXT_MSK, remap_policy_data[1]); + + remap_policy[remap_count].reqCtxChk = + DRF_VAL(_INGRESS, _REMAPTABDATA1, _REQCTXT_CHK, remap_policy_data[1]); + + remap_policy[remap_count].reqCtxRep = + DRF_VAL(_INGRESS, _REMAPTABDATA2, _REQCTXT_REP, remap_policy_data[2]); + + remap_policy[remap_count].addressOffset = 0; + + address_base = + DRF_VAL(_INGRESS, _REMAPTABDATA3, _ADR_BASE, remap_policy_data[3]) | + (DRF_VAL(_INGRESS, _REMAPTABDATA5, _ADR_BASE, remap_policy_data[5]) << + DRF_SIZE(NV_INGRESS_REMAPTABDATA3_ADR_BASE)); + + remap_policy[remap_count].addressBase = + DRF_NUM64(_INGRESS, _REMAP, _ADR_BASE_PHYS_LS10, address_base); + + address_limit = + DRF_VAL(_INGRESS, _REMAPTABDATA3, _ADR_LIMIT, remap_policy_data[3]) | + (DRF_VAL(_INGRESS, _REMAPTABDATA5, _ADR_LIMIT, remap_policy_data[5]) << + DRF_SIZE(NV_INGRESS_REMAPTABDATA3_ADR_LIMIT)); + + remap_policy[remap_count].addressLimit = + DRF_NUM64(_INGRESS, _REMAP, _ADR_LIMIT_PHYS_LS10, address_limit); + + if (params->tableSelect == NVSWITCH_TABLE_SELECT_REMAP_MULTICAST) + { + remap_policy[remap_count].targetId = + DRF_VAL(_INGRESS, _MCREMAPTABDATA4, _MCID, remap_policy_data[4]); + } + else + { + remap_policy[remap_count].targetId = + DRF_VAL(_INGRESS, _REMAPTABDATA4, _TGTID, remap_policy_data[4]); + } + + remap_policy[remap_count].flags = + DRF_VAL(_INGRESS, _REMAPTABDATA4, _RFUNC, remap_policy_data[4]); + // Handle re-used RFUNC[5] conflict between Limerock and Laguna Seca + if (remap_policy[remap_count].flags & NVBIT(5)) + { + remap_policy[remap_count].flags &= ~NVBIT(5); + remap_policy[remap_count].flags |= NVSWITCH_REMAP_POLICY_FLAGS_ADDR_TYPE; + } + if (params->tableSelect == NVSWITCH_TABLE_SELECT_REMAP_MULTICAST) + { + if (FLD_TEST_DRF_NUM(_INGRESS, _MCREMAPTABDATA4, _ENB_REFLECT_MEM, 1, remap_policy_data[4])) + { + remap_policy[remap_count].flags |= NVSWITCH_REMAP_POLICY_FLAGS_REFLECTIVE; + } + } + + remap_count++; + } + + table_index++; + } + + params->nextIndex = table_index; + params->numEntries = remap_count; + + return NVL_SUCCESS; +} + +/* + * CTRL_NVSWITCH_SET_REMAP_POLICY_VALID + */ +NvlStatus +nvswitch_ctrl_set_remap_policy_valid_ls10 +( + nvswitch_device *device, + NVSWITCH_SET_REMAP_POLICY_VALID *p +) +{ + NvU32 remap_ram; + NvU32 ram_address = p->firstIndex; + NvU32 remap_policy_data[NVSWITCH_NUM_REMAP_POLICY_REGS_LS10]; // 6 word/REMAP table entry + NvU32 i; + NvU32 remap_ram_sel; + NvU32 ram_size; + NvlStatus retval; + + if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NPORT, p->portNum)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: NPORT port #%d not valid\n", + __FUNCTION__, p->portNum); + return -NVL_BAD_ARGS; + } + + retval = nvswitch_get_remap_table_selector(device, p->tableSelect, &remap_ram_sel); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "Remap table #%d not supported\n", + p->tableSelect); + return retval; + } + + ram_size = nvswitch_get_ingress_ram_size(device, remap_ram_sel); + if ((p->firstIndex >= ram_size) || + (p->numEntries > NVSWITCH_REMAP_POLICY_ENTRIES_MAX) || + (p->firstIndex + p->numEntries > ram_size)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: remapPolicy[%d..%d] overflows range %d..%d or size %d.\n", + __FUNCTION__, p->firstIndex, p->firstIndex + p->numEntries - 1, + 0, ram_size - 1, + NVSWITCH_REMAP_POLICY_ENTRIES_MAX); + return -NVL_BAD_ARGS; + } + + if (p->tableSelect == NVSWITCH_TABLE_SELECT_REMAP_MULTICAST) + { + for (i = 0; i < p->numEntries; i++) + { + NVSWITCH_LINK_WR32_LS10(device, p->portNum, NPORT, _INGRESS, _MCREMAPTABADDR, + DRF_NUM(_INGRESS, _MCREMAPTABADDR, _RAM_ADDRESS, ram_address++) | + DRF_DEF(_INGRESS, _MCREMAPTABADDR, _AUTO_INCR, _DISABLE)); + + remap_policy_data[0] = NVSWITCH_LINK_RD32_LS10(device, p->portNum, NPORT, _INGRESS, _MCREMAPTABDATA0); + remap_policy_data[1] = NVSWITCH_LINK_RD32_LS10(device, p->portNum, NPORT, _INGRESS, _MCREMAPTABDATA1); + remap_policy_data[2] = NVSWITCH_LINK_RD32_LS10(device, p->portNum, NPORT, _INGRESS, _MCREMAPTABDATA2); + remap_policy_data[3] = NVSWITCH_LINK_RD32_LS10(device, p->portNum, NPORT, _INGRESS, _MCREMAPTABDATA3); + remap_policy_data[4] = NVSWITCH_LINK_RD32_LS10(device, p->portNum, NPORT, _INGRESS, _MCREMAPTABDATA4); + remap_policy_data[5] = NVSWITCH_LINK_RD32_LS10(device, p->portNum, NPORT, _INGRESS, _MCREMAPTABDATA5); + + // Set valid bit in REMAPTABDATA0. + remap_policy_data[0] = FLD_SET_DRF_NUM(_INGRESS, _MCREMAPTABDATA0, _ACLVALID, p->entryValid[i], remap_policy_data[0]); + + NVSWITCH_LINK_WR32_LS10(device, p->portNum, NPORT, _INGRESS, _MCREMAPTABDATA5, remap_policy_data[5]); + NVSWITCH_LINK_WR32_LS10(device, p->portNum, NPORT, _INGRESS, _MCREMAPTABDATA4, remap_policy_data[4]); + NVSWITCH_LINK_WR32_LS10(device, p->portNum, NPORT, _INGRESS, _MCREMAPTABDATA3, remap_policy_data[3]); + NVSWITCH_LINK_WR32_LS10(device, p->portNum, NPORT, _INGRESS, _MCREMAPTABDATA2, remap_policy_data[2]); + NVSWITCH_LINK_WR32_LS10(device, p->portNum, NPORT, _INGRESS, _MCREMAPTABDATA1, remap_policy_data[1]); + NVSWITCH_LINK_WR32_LS10(device, p->portNum, NPORT, _INGRESS, _MCREMAPTABDATA0, remap_policy_data[0]); + } + } + else + { + // Select REMAP POLICY RAM and disable Auto Increment. + remap_ram = + DRF_NUM(_INGRESS, _REQRSPMAPADDR, _RAM_SEL, remap_ram_sel) | + DRF_DEF(_INGRESS, _REQRSPMAPADDR, _AUTO_INCR, _DISABLE); + + for (i = 0; i < p->numEntries; i++) + { + /* set the ram address */ + remap_ram = FLD_SET_DRF_NUM(_INGRESS, _REQRSPMAPADDR, _RAM_ADDRESS, ram_address++, remap_ram); + NVSWITCH_LINK_WR32_LS10(device, p->portNum, NPORT, _INGRESS, _REQRSPMAPADDR, remap_ram); + + remap_policy_data[0] = NVSWITCH_LINK_RD32_LS10(device, p->portNum, NPORT, _INGRESS, _REMAPTABDATA0); + remap_policy_data[1] = NVSWITCH_LINK_RD32_LS10(device, p->portNum, NPORT, _INGRESS, _REMAPTABDATA1); + remap_policy_data[2] = NVSWITCH_LINK_RD32_LS10(device, p->portNum, NPORT, _INGRESS, _REMAPTABDATA2); + remap_policy_data[3] = NVSWITCH_LINK_RD32_LS10(device, p->portNum, NPORT, _INGRESS, _REMAPTABDATA3); + remap_policy_data[4] = NVSWITCH_LINK_RD32_LS10(device, p->portNum, NPORT, _INGRESS, _REMAPTABDATA4); + remap_policy_data[5] = NVSWITCH_LINK_RD32_LS10(device, p->portNum, NPORT, _INGRESS, _REMAPTABDATA5); + + // Set valid bit in REMAPTABDATA0. + remap_policy_data[0] = FLD_SET_DRF_NUM(_INGRESS, _REMAPTABDATA0, _ACLVALID, p->entryValid[i], remap_policy_data[0]); + + NVSWITCH_LINK_WR32_LS10(device, p->portNum, NPORT, _INGRESS, _REMAPTABDATA5, remap_policy_data[5]); + NVSWITCH_LINK_WR32_LS10(device, p->portNum, NPORT, _INGRESS, _REMAPTABDATA4, remap_policy_data[4]); + NVSWITCH_LINK_WR32_LS10(device, p->portNum, NPORT, _INGRESS, _REMAPTABDATA3, remap_policy_data[3]); + NVSWITCH_LINK_WR32_LS10(device, p->portNum, NPORT, _INGRESS, _REMAPTABDATA2, remap_policy_data[2]); + NVSWITCH_LINK_WR32_LS10(device, p->portNum, NPORT, _INGRESS, _REMAPTABDATA1, remap_policy_data[1]); + NVSWITCH_LINK_WR32_LS10(device, p->portNum, NPORT, _INGRESS, _REMAPTABDATA0, remap_policy_data[0]); + } + } + + return NVL_SUCCESS; +} + +NvlStatus nvswitch_ctrl_set_mc_rid_table_ls10 +( + nvswitch_device *device, + NVSWITCH_SET_MC_RID_TABLE_PARAMS *p +) +{ + NvlStatus ret; + NVSWITCH_MC_RID_ENTRY_LS10 table_entry; + NvU32 entries_used = 0; + + if (!nvswitch_is_link_valid(device, p->portNum)) + return -NVL_BAD_ARGS; + + // check if link is invalid or repeater + if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NPORT, p->portNum)) + { + NVSWITCH_PRINT(device, ERROR, "%s: NPORT invalid for port %d\n", + __FUNCTION__, p->portNum); + return -NVL_BAD_ARGS; + } + + // range check index + if (p->extendedTable && (p->index > NV_ROUTE_RIDTABADDR_INDEX_MCRIDEXTTAB_DEPTH)) + { + NVSWITCH_PRINT(device, ERROR, "%s: index %d out of range for extended table\n", + __FUNCTION__, p->index); + return -NVL_BAD_ARGS; + } + + if (p->index > NV_ROUTE_RIDTABADDR_INDEX_MCRIDTAB_DEPTH) + { + NVSWITCH_PRINT(device, ERROR, "%s: index %d out of range for main table\n", + __FUNCTION__, p->index); + return -NVL_BAD_ARGS; + } + + // if !entryValid, zero the table and return + if (!p->entryValid) + return nvswitch_mc_invalidate_mc_rid_entry_ls10(device, p->portNum, p->index, + p->extendedTable, NV_TRUE); + + // range check mcSize + if ((p->mcSize == 0) || (p->mcSize > NVSWITCH_NUM_LINKS_LS10)) + { + NVSWITCH_PRINT(device, ERROR, "%s: mcSize %d is invalid\n", __FUNCTION__, p->mcSize); + return -NVL_BAD_ARGS; + } + + // extended table cannot have an extended ptr + if (p->extendedTable && p->extendedValid) + { + NVSWITCH_PRINT(device, ERROR, "%s: extendedTable cannot have an extendedValid ptr\n", + __FUNCTION__); + return -NVL_BAD_ARGS; + } + + // set up table entry fields + table_entry.index = (NvU8)p->index; + table_entry.use_extended_table = p->extendedTable; + table_entry.mcpl_size = (NvU8)p->mcSize; + table_entry.num_spray_groups = (NvU8)p->numSprayGroups; + table_entry.ext_ptr = (NvU8)p->extendedPtr; + table_entry.no_dyn_rsp = p->noDynRsp; + table_entry.ext_ptr_valid = p->extendedValid; + table_entry.valid = p->entryValid; + + // build the directive list, remaining range checks are performed inside + ret = nvswitch_mc_build_mcp_list_ls10(device, p->ports, p->portsPerSprayGroup, p->replicaOffset, + p->replicaValid, p->vcHop, &table_entry, &entries_used); + + NVSWITCH_PRINT(device, INFO, "nvswitch_mc_build_mcp_list_ls10() returned %d, entries used: %d\n", + ret, entries_used); + + if (ret != NVL_SUCCESS) + return ret; + + // program the table + ret = nvswitch_mc_program_mc_rid_entry_ls10(device, p->portNum, &table_entry, entries_used); + + return ret; +} + +NvlStatus nvswitch_ctrl_get_mc_rid_table_ls10 +( + nvswitch_device *device, + NVSWITCH_GET_MC_RID_TABLE_PARAMS *p +) +{ + NvU32 ret; + NVSWITCH_MC_RID_ENTRY_LS10 table_entry; + NvU32 port = p->portNum; + + if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NPORT, port)) + { + NVSWITCH_PRINT(device, ERROR, "%s: NPORT invalid for port %d\n", + __FUNCTION__, port); + return -NVL_BAD_ARGS; + } + + // range check index + if (p->extendedTable && (p->index > NV_ROUTE_RIDTABADDR_INDEX_MCRIDEXTTAB_DEPTH)) + { + NVSWITCH_PRINT(device, ERROR, "%s: index %d out of range for extended table\n", + __FUNCTION__, p->index); + return -NVL_BAD_ARGS; + } + + if (p->index > NV_ROUTE_RIDTABADDR_INDEX_MCRIDTAB_DEPTH) + { + NVSWITCH_PRINT(device, ERROR, "%s: index %d out of range for main table\n", + __FUNCTION__, p->index); + return -NVL_BAD_ARGS; + } + + nvswitch_os_memset(&table_entry, 0, sizeof(NVSWITCH_MC_RID_ENTRY_LS10)); + + table_entry.index = (NvU8)p->index; + table_entry.use_extended_table = p->extendedTable; + + ret = nvswitch_mc_read_mc_rid_entry_ls10(device, port, &table_entry); + if (ret != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: nvswitch_mc_read_mc_rid_entry_ls10() returned %d\n", + __FUNCTION__, ret); + return ret; + } + + nvswitch_os_memset(p, 0, sizeof(NVSWITCH_GET_MC_RID_TABLE_PARAMS)); + + p->portNum = port; + p->index = table_entry.index; + p->extendedTable = table_entry.use_extended_table; + + ret = nvswitch_mc_unwind_directives_ls10(device, table_entry.directives, p->ports, + p->vcHop, p->portsPerSprayGroup, p->replicaOffset, + p->replicaValid); + if (ret != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: nvswitch_mc_unwind_directives_ls10() returned %d\n", + __FUNCTION__, ret); + return ret; + } + + p->mcSize = table_entry.mcpl_size; + p->numSprayGroups = table_entry.num_spray_groups; + p->extendedPtr = table_entry.ext_ptr; + p->noDynRsp = table_entry.no_dyn_rsp; + p->extendedValid = table_entry.ext_ptr_valid; + p->entryValid = table_entry.valid; + + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_write_fabric_state_ls10 +( + nvswitch_device *device +) +{ + NvU32 reg; + + if (device == NULL) + { + NVSWITCH_PRINT(device, ERROR, "%s: Called with invalid argument\n", __FUNCTION__); + return -NVL_BAD_ARGS; + } + + // bump the sequence number for each write + device->fabric_state_sequence_number++; + + reg = NVSWITCH_SAW_RD32_LS10(device, _NVLSAW, _DRIVER_ATTACH_DETACH); + + reg = FLD_SET_DRF_NUM(_NVLSAW, _DRIVER_ATTACH_DETACH, _DEVICE_BLACKLIST_REASON, + device->device_blacklist_reason, reg); + reg = FLD_SET_DRF_NUM(_NVLSAW, _DRIVER_ATTACH_DETACH, _DEVICE_FABRIC_STATE, + device->device_fabric_state, reg); + reg = FLD_SET_DRF_NUM(_NVLSAW, _DRIVER_ATTACH_DETACH, _DRIVER_FABRIC_STATE, + device->driver_fabric_state, reg); + reg = FLD_SET_DRF_NUM(_NVLSAW, _DRIVER_ATTACH_DETACH, _EVENT_MESSAGE_COUNT, + device->fabric_state_sequence_number, reg); + + NVSWITCH_SAW_WR32_LS10(device, _NVLSAW, _DRIVER_ATTACH_DETACH, reg); + + return NVL_SUCCESS; +} + +static NVSWITCH_ENGINE_DESCRIPTOR_TYPE * +_nvswitch_get_eng_descriptor_ls10 +( + nvswitch_device *device, + NVSWITCH_ENGINE_ID eng_id +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NVSWITCH_ENGINE_DESCRIPTOR_TYPE *engine = NULL; + + if (eng_id >= NVSWITCH_ENGINE_ID_SIZE) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Engine_ID 0x%x out of range 0..0x%x\n", + __FUNCTION__, + eng_id, NVSWITCH_ENGINE_ID_SIZE-1); + return NULL; + } + + engine = &(chip_device->io.common[eng_id]); + if (eng_id != engine->eng_id) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Requested Engine_ID 0x%x does not equal found Engine_ID 0x%x (%s)\n", + __FUNCTION__, + eng_id, engine->eng_id, engine->eng_name); + } + NVSWITCH_ASSERT(eng_id == engine->eng_id); + + return engine; +} + +NvU32 +nvswitch_get_eng_base_ls10 +( + nvswitch_device *device, + NVSWITCH_ENGINE_ID eng_id, + NvU32 eng_bcast, + NvU32 eng_instance +) +{ + NVSWITCH_ENGINE_DESCRIPTOR_TYPE *engine; + NvU32 base_addr = NVSWITCH_BASE_ADDR_INVALID; + + engine = _nvswitch_get_eng_descriptor_ls10(device, eng_id); + if (engine == NULL) + { + NVSWITCH_PRINT(device, ERROR, + "%s: ID 0x%x[%d] %s not found\n", + __FUNCTION__, + eng_id, eng_instance, + ( + (eng_bcast == NVSWITCH_GET_ENG_DESC_TYPE_UNICAST) ? "UC" : + (eng_bcast == NVSWITCH_GET_ENG_DESC_TYPE_BCAST) ? "BC" : + (eng_bcast == NVSWITCH_GET_ENG_DESC_TYPE_MULTICAST) ? "MC" : + "??" + )); + return NVSWITCH_BASE_ADDR_INVALID; + } + + if ((eng_bcast == NVSWITCH_GET_ENG_DESC_TYPE_UNICAST) && + (eng_instance < engine->eng_count)) + { + base_addr = engine->uc_addr[eng_instance]; + } + else if (eng_bcast == NVSWITCH_GET_ENG_DESC_TYPE_BCAST) + { + base_addr = engine->bc_addr; + } + else if ((eng_bcast == NVSWITCH_GET_ENG_DESC_TYPE_MULTICAST) && + (eng_instance < engine->mc_addr_count)) + { + base_addr = engine->mc_addr[eng_instance]; + } + else + { + NVSWITCH_PRINT(device, ERROR, + "%s: Unknown address space type 0x%x (not UC, BC, or MC)\n", + __FUNCTION__, + eng_bcast); + } + + // The NPORT engine can be marked as invalid when it is in Repeater Mode + if (base_addr == NVSWITCH_BASE_ADDR_INVALID) + { + NVSWITCH_PRINT(device, INFO, + "%s: ID 0x%x[%d] %s invalid address\n", + __FUNCTION__, + eng_id, eng_instance, + ( + (eng_bcast == NVSWITCH_GET_ENG_DESC_TYPE_UNICAST) ? "UC" : + (eng_bcast == NVSWITCH_GET_ENG_DESC_TYPE_BCAST) ? "BC" : + (eng_bcast == NVSWITCH_GET_ENG_DESC_TYPE_MULTICAST) ? "MC" : + "??" + )); + } + + return base_addr; +} + +NvU32 +nvswitch_get_eng_count_ls10 +( + nvswitch_device *device, + NVSWITCH_ENGINE_ID eng_id, + NvU32 eng_bcast +) +{ + NVSWITCH_ENGINE_DESCRIPTOR_TYPE *engine; + NvU32 eng_count = 0; + + engine = _nvswitch_get_eng_descriptor_ls10(device, eng_id); + if (engine == NULL) + { + NVSWITCH_PRINT(device, ERROR, + "%s: ID 0x%x %s not found\n", + __FUNCTION__, + eng_id, + ( + (eng_bcast == NVSWITCH_GET_ENG_DESC_TYPE_UNICAST) ? "UC" : + (eng_bcast == NVSWITCH_GET_ENG_DESC_TYPE_BCAST) ? "BC" : + (eng_bcast == NVSWITCH_GET_ENG_DESC_TYPE_MULTICAST) ? "MC" : + "??" + )); + return 0; + } + + if (eng_bcast == NVSWITCH_GET_ENG_DESC_TYPE_UNICAST) + { + eng_count = engine->eng_count; + } + else if (eng_bcast == NVSWITCH_GET_ENG_DESC_TYPE_BCAST) + { + if (engine->bc_addr == NVSWITCH_BASE_ADDR_INVALID) + { + eng_count = 0; + } + else + { + eng_count = 1; + } + } + else if (eng_bcast == NVSWITCH_GET_ENG_DESC_TYPE_MULTICAST) + { + eng_count = engine->mc_addr_count; + } + else + { + NVSWITCH_PRINT(device, ERROR, + "%s: Unknown address space type 0x%x (not UC, BC, or MC)\n", + __FUNCTION__, + eng_bcast); + } + + return eng_count; +} + +NvU32 +nvswitch_eng_rd_ls10 +( + nvswitch_device *device, + NVSWITCH_ENGINE_ID eng_id, + NvU32 eng_bcast, + NvU32 eng_instance, + NvU32 offset +) +{ + NvU32 base_addr = NVSWITCH_BASE_ADDR_INVALID; + NvU32 data; + + base_addr = nvswitch_get_eng_base_ls10(device, eng_id, eng_bcast, eng_instance); + if (base_addr == NVSWITCH_BASE_ADDR_INVALID) + { + NVSWITCH_PRINT(device, ERROR, + "%s: ID 0x%x[%d] %s invalid address\n", + __FUNCTION__, + eng_id, eng_instance, + ( + (eng_bcast == NVSWITCH_GET_ENG_DESC_TYPE_UNICAST) ? "UC" : + (eng_bcast == NVSWITCH_GET_ENG_DESC_TYPE_BCAST) ? "BC" : + (eng_bcast == NVSWITCH_GET_ENG_DESC_TYPE_MULTICAST) ? "MC" : + "??" + )); + NVSWITCH_ASSERT(base_addr != NVSWITCH_BASE_ADDR_INVALID); + return 0xBADFBADF; + } + + data = nvswitch_reg_read_32(device, base_addr + offset); + +#if defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS) + { + NVSWITCH_ENGINE_DESCRIPTOR_TYPE *engine = _nvswitch_get_eng_descriptor_ls10(device, eng_id); + + NVSWITCH_PRINT(device, MMIO, + "%s: ENG_RD %s(0x%x)[%d] @0x%08x+0x%06x = 0x%08x\n", + __FUNCTION__, + engine->eng_name, engine->eng_id, + eng_instance, + base_addr, offset, + data); + } +#endif //defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS) + + return data; +} + +void +nvswitch_eng_wr_ls10 +( + nvswitch_device *device, + NVSWITCH_ENGINE_ID eng_id, + NvU32 eng_bcast, + NvU32 eng_instance, + NvU32 offset, + NvU32 data +) +{ + NvU32 base_addr = NVSWITCH_BASE_ADDR_INVALID; + + base_addr = nvswitch_get_eng_base_ls10(device, eng_id, eng_bcast, eng_instance); + if (base_addr == NVSWITCH_BASE_ADDR_INVALID) + { + NVSWITCH_PRINT(device, ERROR, + "%s: ID 0x%x[%d] %s invalid address\n", + __FUNCTION__, + eng_id, eng_instance, + ( + (eng_bcast == NVSWITCH_GET_ENG_DESC_TYPE_UNICAST) ? "UC" : + (eng_bcast == NVSWITCH_GET_ENG_DESC_TYPE_BCAST) ? "BC" : + (eng_bcast == NVSWITCH_GET_ENG_DESC_TYPE_MULTICAST) ? "MC" : + "??" + )); + NVSWITCH_ASSERT(base_addr != NVSWITCH_BASE_ADDR_INVALID); + return; + } + + nvswitch_reg_write_32(device, base_addr + offset, data); + +#if defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS) + { + NVSWITCH_ENGINE_DESCRIPTOR_TYPE *engine = _nvswitch_get_eng_descriptor_ls10(device, eng_id); + + NVSWITCH_PRINT(device, MMIO, + "%s: ENG_WR %s(0x%x)[%d] @0x%08x+0x%06x = 0x%08x\n", + __FUNCTION__, + engine->eng_name, engine->eng_id, + eng_instance, + base_addr, offset, + data); + } +#endif //defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS) +} + +NvU32 +nvswitch_get_link_eng_inst_ls10 +( + nvswitch_device *device, + NvU32 link_id, + NVSWITCH_ENGINE_ID eng_id +) +{ + NvU32 eng_instance = NVSWITCH_ENGINE_INSTANCE_INVALID; + + if (link_id >= NVSWITCH_LINK_COUNT(device)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: link ID 0x%x out-of-range [0x0..0x%x]\n", + __FUNCTION__, + link_id, NVSWITCH_LINK_COUNT(device)-1); + return NVSWITCH_ENGINE_INSTANCE_INVALID; + } + + switch (eng_id) + { + case NVSWITCH_ENGINE_ID_NPG: + eng_instance = link_id / NVSWITCH_LINKS_PER_NPG_LS10; + break; + case NVSWITCH_ENGINE_ID_NVLIPT: + eng_instance = link_id / NVSWITCH_LINKS_PER_NVLIPT_LS10; + break; + case NVSWITCH_ENGINE_ID_NVLW: + case NVSWITCH_ENGINE_ID_NVLW_PERFMON: + eng_instance = link_id / NVSWITCH_LINKS_PER_NVLW_LS10; + break; + case NVSWITCH_ENGINE_ID_MINION: + eng_instance = link_id / NVSWITCH_LINKS_PER_MINION_LS10; + break; + case NVSWITCH_ENGINE_ID_NPORT: + case NVSWITCH_ENGINE_ID_NVLTLC: + case NVSWITCH_ENGINE_ID_NVLDL: + case NVSWITCH_ENGINE_ID_NVLIPT_LNK: + case NVSWITCH_ENGINE_ID_NPORT_PERFMON: + eng_instance = link_id; + break; + default: + NVSWITCH_PRINT(device, ERROR, + "%s: link ID 0x%x has no association with EngID 0x%x\n", + __FUNCTION__, + link_id, eng_id); + eng_instance = NVSWITCH_ENGINE_INSTANCE_INVALID; + break; + } + + return eng_instance; +} + +NvU32 +nvswitch_get_caps_nvlink_version_ls10 +( + nvswitch_device *device +) +{ + ct_assert(NVSWITCH_NVLINK_STATUS_NVLINK_VERSION_4_0 == + NVSWITCH_NVLINK_CAPS_NVLINK_VERSION_4_0); + return NVSWITCH_NVLINK_CAPS_NVLINK_VERSION_4_0; +} + + +NVSWITCH_BIOS_NVLINK_CONFIG * +nvswitch_get_bios_nvlink_config_ls10 +( + nvswitch_device *device +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + + return &chip_device->bios_config; +} + + +static void +_nvswitch_init_nport_ecc_control_ls10 +( + nvswitch_device *device +) +{ + // Set ingress ECC error limits + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _INGRESS, _ERR_NCISOC_HDR_ECC_ERROR_COUNTER, + DRF_NUM(_INGRESS, _ERR_NCISOC_HDR_ECC_ERROR_COUNTER, _ERROR_COUNT, 0x0)); + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _INGRESS, _ERR_NCISOC_HDR_ECC_ERROR_COUNTER_LIMIT, 1); + + // Set egress ECC error limits + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _EGRESS, _ERR_NXBAR_ECC_ERROR_COUNTER, + DRF_NUM(_EGRESS, _ERR_NXBAR_ECC_ERROR_COUNTER, _ERROR_COUNT, 0x0)); + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _EGRESS, _ERR_NXBAR_ECC_ERROR_COUNTER_LIMIT, 1); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _EGRESS, _ERR_RAM_OUT_ECC_ERROR_COUNTER, + DRF_NUM(_EGRESS, _ERR_RAM_OUT_ECC_ERROR_COUNTER, _ERROR_COUNT, 0x0)); + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _EGRESS, _ERR_RAM_OUT_ECC_ERROR_COUNTER_LIMIT, 1); + + // Set route ECC error limits + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _ROUTE, _ERR_NVS_ECC_ERROR_COUNTER, + DRF_NUM(_ROUTE, _ERR_NVS_ECC_ERROR_COUNTER, _ERROR_COUNT, 0x0)); + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _ROUTE, _ERR_NVS_ECC_ERROR_COUNTER_LIMIT, 1); + + // Set tstate ECC error limits + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _TSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER, + DRF_NUM(_TSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER, _ERROR_COUNT, 0x0)); + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _TSTATE, _ERR_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT, 1); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _TSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER, + DRF_NUM(_TSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER, _ERROR_COUNT, 0x0)); + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _TSTATE, _ERR_TAGPOOL_ECC_ERROR_COUNTER_LIMIT, 1); + + // Set sourcetrack ECC error limits to _PROD value + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _SOURCETRACK, _ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT, + DRF_NUM(_SOURCETRACK, _ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_COUNTER, _ERROR_COUNT, 0x0)); + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _SOURCETRACK, _ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT, 1); + + // Enable ECC/parity + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _INGRESS, _ERR_ECC_CTRL, + DRF_DEF(_INGRESS, _ERR_ECC_CTRL, _NCISOC_HDR_ECC_ENABLE, __PROD) | + DRF_DEF(_INGRESS, _ERR_ECC_CTRL, _NCISOC_PARITY_ENABLE, __PROD) | + DRF_DEF(_INGRESS, _ERR_ECC_CTRL, _REMAPTAB_ECC_ENABLE, __PROD) | + DRF_DEF(_INGRESS, _ERR_ECC_CTRL, _RIDTAB_ECC_ENABLE, __PROD) | + DRF_DEF(_INGRESS, _ERR_ECC_CTRL, _RLANTAB_ECC_ENABLE, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _EGRESS, _ERR_ECC_CTRL, + DRF_DEF(_EGRESS, _ERR_ECC_CTRL, _NXBAR_ECC_ENABLE, __PROD) | + DRF_DEF(_EGRESS, _ERR_ECC_CTRL, _NXBAR_PARITY_ENABLE, __PROD) | + DRF_DEF(_EGRESS, _ERR_ECC_CTRL, _RAM_OUT_ECC_ENABLE, __PROD) | + DRF_DEF(_EGRESS, _ERR_ECC_CTRL, _NCISOC_ECC_ENABLE, __PROD) | + DRF_DEF(_EGRESS, _ERR_ECC_CTRL, _NCISOC_PARITY_ENABLE, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _ROUTE, _ERR_ECC_CTRL, + DRF_DEF(_ROUTE, _ERR_ECC_CTRL, _GLT_ECC_ENABLE, __PROD) | + DRF_DEF(_ROUTE, _ERR_ECC_CTRL, _NVS_ECC_ENABLE, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _TSTATE, _ERR_ECC_CTRL, + DRF_DEF(_TSTATE, _ERR_ECC_CTRL, _CRUMBSTORE_ECC_ENABLE, __PROD) | + DRF_DEF(_TSTATE, _ERR_ECC_CTRL, _TAGPOOL_ECC_ENABLE, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _SOURCETRACK, _ERR_ECC_CTRL, + DRF_DEF(_SOURCETRACK, _ERR_ECC_CTRL, _CREQ_TCEN0_CRUMBSTORE_ECC_ENABLE, __PROD)); +} + +NvlStatus +nvswitch_init_nport_ls10 +( + nvswitch_device *device +) +{ + NvU32 data32, timeout; + NvU32 idx_nport; + NvU32 num_nports; + + num_nports = NVSWITCH_ENG_COUNT(device, NPORT, ); + + for (idx_nport = 0; idx_nport < num_nports; idx_nport++) + { + // Find the first valid nport + if (NVSWITCH_ENG_IS_VALID(device, NPORT, idx_nport)) + { + break; + } + } + + // This is a valid case, since all NPORTs can be in Repeater mode. + if (idx_nport == num_nports) + { + NVSWITCH_PRINT(device, INFO, "%s: No valid nports found! Skipping.\n", __FUNCTION__); + return NVL_SUCCESS; + } + + _nvswitch_init_nport_ecc_control_ls10(device); + + if (DRF_VAL(_SWITCH_REGKEY, _ATO_CONTROL, _DISABLE, device->regkeys.ato_control) == + NV_SWITCH_REGKEY_ATO_CONTROL_DISABLE_TRUE) + { + // ATO Disable + data32 = NVSWITCH_NPORT_RD32_LS10(device, idx_nport, _TSTATE, _TAGSTATECONTROL); + data32 = FLD_SET_DRF(_TSTATE, _TAGSTATECONTROL, _ATO_ENB, _OFF, data32); + NVSWITCH_NPORT_MC_BCAST_WR32_LS10(device, _TSTATE, _TAGSTATECONTROL, data32); + } + else + { + // ATO Enable + data32 = NVSWITCH_NPORT_RD32_LS10(device, idx_nport, _TSTATE, _TAGSTATECONTROL); + data32 = FLD_SET_DRF(_TSTATE, _TAGSTATECONTROL, _ATO_ENB, _ON, data32); + NVSWITCH_NPORT_MC_BCAST_WR32_LS10(device, _TSTATE, _TAGSTATECONTROL, data32); + + // ATO Timeout value + timeout = DRF_VAL(_SWITCH_REGKEY, _ATO_CONTROL, _TIMEOUT, device->regkeys.ato_control); + if (timeout != NV_SWITCH_REGKEY_ATO_CONTROL_TIMEOUT_DEFAULT) + { + NVSWITCH_NPORT_MC_BCAST_WR32_LS10(device, _TSTATE, _ATO_TIMER_LIMIT, + DRF_NUM(_TSTATE, _ATO_TIMER_LIMIT, _LIMIT, timeout)); + } + } + + if (DRF_VAL(_SWITCH_REGKEY, _STO_CONTROL, _DISABLE, device->regkeys.sto_control) == + NV_SWITCH_REGKEY_STO_CONTROL_DISABLE_TRUE) + { + // STO Disable + data32 = NVSWITCH_NPORT_RD32_LS10(device, idx_nport, _SOURCETRACK, _CTRL); + data32 = FLD_SET_DRF(_SOURCETRACK, _CTRL, _STO_ENB, _DISABLED, data32); + NVSWITCH_NPORT_MC_BCAST_WR32_LS10(device, _SOURCETRACK, _CTRL, data32); + } + else + { + // STO Enable + data32 = NVSWITCH_NPORT_RD32_LS10(device, idx_nport, _SOURCETRACK, _CTRL); + data32 = FLD_SET_DRF(_SOURCETRACK, _CTRL, _STO_ENB, _ENABLED, data32); + NVSWITCH_NPORT_MC_BCAST_WR32_LS10(device, _SOURCETRACK, _CTRL, data32); + + // STO Timeout value + timeout = DRF_VAL(_SWITCH_REGKEY, _STO_CONTROL, _TIMEOUT, device->regkeys.sto_control); + if (timeout != NV_SWITCH_REGKEY_STO_CONTROL_TIMEOUT_DEFAULT) + { + NVSWITCH_NPORT_MC_BCAST_WR32_LS10(device, _SOURCETRACK, _MULTISEC_TIMER0, + DRF_NUM(_SOURCETRACK, _MULTISEC_TIMER0, _TIMERVAL0, timeout)); + } + } + + NVSWITCH_NPORT_MC_BCAST_WR32_LS10(device, _NPORT, _CONTAIN_AND_DRAIN, + DRF_DEF(_NPORT, _CONTAIN_AND_DRAIN, _CLEAR, _ENABLE)); + + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_init_nxbar_ls10 +( + nvswitch_device *device +) +{ + NvlStatus status = NVL_SUCCESS; + + status = nvswitch_apply_prod_nxbar_ls10(device); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: NXBAR PRODs failed\n", + __FUNCTION__); + return status; + } + + return NVL_SUCCESS; +} + +static NvlStatus +nvswitch_clear_nport_rams_ls10 +( + nvswitch_device *device +) +{ + NvU32 idx_nport; + NvU64 nport_mask = 0; + NvU32 zero_init_mask; + NvU32 val; + NVSWITCH_TIMEOUT timeout; + NvBool keepPolling; + + // Build the mask of available NPORTs + for (idx_nport = 0; idx_nport < NVSWITCH_ENG_COUNT(device, NPORT, ); idx_nport++) + { + if (NVSWITCH_ENG_IS_VALID(device, NPORT, idx_nport)) + { + nport_mask |= NVBIT64(idx_nport); + } + } + + // Start the HW zero init + zero_init_mask = + DRF_DEF(_NPORT, _INITIALIZATION, _TAGPOOLINIT_0, _HWINIT) | + DRF_DEF(_NPORT, _INITIALIZATION, _LINKTABLEINIT, _HWINIT) | + DRF_DEF(_NPORT, _INITIALIZATION, _REMAPTABINIT, _HWINIT) | + DRF_DEF(_NPORT, _INITIALIZATION, _RIDTABINIT, _HWINIT) | + DRF_DEF(_NPORT, _INITIALIZATION, _RLANTABINIT, _HWINIT) | + DRF_DEF(_NPORT, _INITIALIZATION, _MCREMAPTABINIT, _HWINIT) | + DRF_DEF(_NPORT, _INITIALIZATION, _MCTAGSTATEINIT, _HWINIT) | + DRF_DEF(_NPORT, _INITIALIZATION, _RDTAGSTATEINIT, _HWINIT) | + DRF_DEF(_NPORT, _INITIALIZATION, _MCREDSGTINIT, _HWINIT) | + DRF_DEF(_NPORT, _INITIALIZATION, _MCREDBUFINIT, _HWINIT) | + DRF_DEF(_NPORT, _INITIALIZATION, _MCRIDINIT, _HWINIT) | + DRF_DEF(_NPORT, _INITIALIZATION, _EXTMCRIDINIT, _HWINIT); + + NVSWITCH_BCAST_WR32_LS10(device, NPORT, _NPORT, _INITIALIZATION, + zero_init_mask); + + nvswitch_timeout_create(25 * NVSWITCH_INTERVAL_1MSEC_IN_NS, &timeout); + + do + { + keepPolling = (nvswitch_timeout_check(&timeout)) ? NV_FALSE : NV_TRUE; + + // Check each enabled NPORT that is still pending until all are done + for (idx_nport = 0; idx_nport < NVSWITCH_ENG_COUNT(device, NPORT, ); idx_nport++) + { + if (NVSWITCH_ENG_IS_VALID(device, NPORT, idx_nport) && (nport_mask & NVBIT64(idx_nport))) + { + val = NVSWITCH_ENG_RD32_LS10(device, NPORT, idx_nport, _NPORT, _INITIALIZATION); + if (val == zero_init_mask) + { + nport_mask &= ~NVBIT64(idx_nport); + } + } + } + + if (nport_mask == 0) + { + break; + } + + nvswitch_os_sleep(1); + } + while (keepPolling); + + if (nport_mask != 0) + { + NVSWITCH_PRINT(device, WARN, + "%s: Timeout waiting for NV_NPORT_INITIALIZATION (0x%llx)\n", + __FUNCTION__, nport_mask); + return -NVL_ERR_INVALID_STATE; + } + + return NVL_SUCCESS; +} + +/* + * CTRL_NVSWITCH_SET_RESIDENCY_BINS + */ +static NvlStatus +nvswitch_ctrl_set_residency_bins_ls10 +( + nvswitch_device *device, + NVSWITCH_SET_RESIDENCY_BINS *p +) +{ + NvU64 threshold; + NvU64 max_threshold; + + if (p->bin.lowThreshold > p->bin.hiThreshold ) + { + NVSWITCH_PRINT(device, ERROR, + "SET_RESIDENCY_BINS: Low threshold (%d) > Hi threshold (%d)\n", + p->bin.lowThreshold, p->bin.hiThreshold); + return -NVL_BAD_ARGS; + } + + if (p->table_select == NVSWITCH_TABLE_SELECT_MULTICAST) + { + max_threshold = DRF_MASK(NV_MULTICASTTSTATE_STAT_RESIDENCY_BIN_CTRL_HIGH_LIMIT); + + threshold = (NvU64) p->bin.hiThreshold * 1333 / 1000; + if (threshold > max_threshold) + { + NVSWITCH_PRINT(device, ERROR, + "SET_RESIDENCY_BINS: Threshold overflow. %u > %llu max\n", + p->bin.hiThreshold, max_threshold * 1000 / 1333); + return -NVL_BAD_ARGS; + } + NVSWITCH_NPORT_BCAST_WR32_LS10(device, _MULTICASTTSTATE, _STAT_RESIDENCY_BIN_CTRL_HIGH, + DRF_NUM(_MULTICASTTSTATE, _STAT_RESIDENCY_BIN_CTRL_HIGH, _LIMIT, (NvU32)threshold)); + + threshold = (NvU64)p->bin.lowThreshold * 1333 / 1000; + NVSWITCH_NPORT_BCAST_WR32_LS10(device, _MULTICASTTSTATE, _STAT_RESIDENCY_BIN_CTRL_LOW, + DRF_NUM(_MULTICASTTSTATE, _STAT_RESIDENCY_BIN_CTRL_LOW, _LIMIT, (NvU32)threshold)); + } + else if (p->table_select == NVSWITCH_TABLE_SELECT_REDUCTION) + { + max_threshold = DRF_MASK(NV_REDUCTIONTSTATE_STAT_RESIDENCY_BIN_CTRL_HIGH_LIMIT); + + threshold = (NvU64) p->bin.hiThreshold * 1333 / 1000; + if (threshold > max_threshold) + { + NVSWITCH_PRINT(device, ERROR, + "SET_RESIDENCY_BINS: Threshold overflow. %u > %llu max\n", + p->bin.hiThreshold, max_threshold * 1000 / 1333); + return -NVL_BAD_ARGS; + } + NVSWITCH_NPORT_BCAST_WR32_LS10(device, _REDUCTIONTSTATE, _STAT_RESIDENCY_BIN_CTRL_HIGH, + DRF_NUM(_REDUCTIONTSTATE, _STAT_RESIDENCY_BIN_CTRL_HIGH, _LIMIT, (NvU32)threshold)); + + threshold = (NvU64)p->bin.lowThreshold * 1333 / 1000; + NVSWITCH_NPORT_BCAST_WR32_LS10(device, _REDUCTIONTSTATE, _STAT_RESIDENCY_BIN_CTRL_LOW, + DRF_NUM(_REDUCTIONTSTATE, _STAT_RESIDENCY_BIN_CTRL_LOW, _LIMIT, (NvU32)threshold)); + } + else + { + NVSWITCH_PRINT(device, ERROR, + "SET_RESIDENCY_BINS: Invalid table %d\n", p->table_select); + return -NVL_ERR_NOT_SUPPORTED; + } + + return NVL_SUCCESS; +} + +#define NVSWITCH_RESIDENCY_BIN_SIZE \ + ((NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_MAX + 1) / \ + NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_MCID_STRIDE) + +/* + * CTRL_NVSWITCH_GET_RESIDENCY_BINS + */ +static NvlStatus +nvswitch_ctrl_get_residency_bins_ls10 +( + nvswitch_device *device, + NVSWITCH_GET_RESIDENCY_BINS *p +) +{ + NvU64 val; + NvU64 val_hi; + NvU32 i; + NvU64 threshold; + + ct_assert( + NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_MCID_STRIDE == + NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_MCID_STRIDE); + ct_assert( + NV_MULTICASTTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_MAX == + NV_REDUCTIONTSTATE_STAT_RESIDENCY_COUNT_CTRL_INDEX_MAX); + + ct_assert(NVSWITCH_RESIDENCY_BIN_SIZE == NVSWITCH_RESIDENCY_SIZE); + + if (!nvswitch_is_link_valid(device, p->link)) + { + NVSWITCH_PRINT(device, ERROR, + "GET_RESIDENCY_BINS: Invalid link %d\n", p->link); + return -NVL_BAD_ARGS; + } + + if (p->table_select == NVSWITCH_TABLE_SELECT_MULTICAST) + { + // Snap the histogram + NVSWITCH_NPORT_WR32_LS10(device, p->link, _MULTICASTTSTATE, _STAT_RESIDENCY_CONTROL, + DRF_DEF(_MULTICASTTSTATE, _STAT_RESIDENCY_CONTROL, _ENABLE_TIMER, _ENABLE) | + DRF_DEF(_MULTICASTTSTATE, _STAT_RESIDENCY_CONTROL, _SNAP_ON_DEMAND, _ENABLE)); + + // Read high/low thresholds and convery clocks to nsec + val = NVSWITCH_NPORT_RD32_LS10(device, p->link, _MULTICASTTSTATE, _STAT_RESIDENCY_BIN_CTRL_LOW); + threshold = DRF_VAL(_MULTICASTTSTATE, _STAT_RESIDENCY_BIN_CTRL_LOW, _LIMIT, val); + p->bin.lowThreshold = threshold * 1000 / 1333; + + val = NVSWITCH_NPORT_RD32_LS10(device, p->link, _MULTICASTTSTATE, _STAT_RESIDENCY_BIN_CTRL_HIGH); + threshold = DRF_VAL(_MULTICASTTSTATE, _STAT_RESIDENCY_BIN_CTRL_HIGH, _LIMIT, val); + p->bin.hiThreshold = threshold * 1000 / 1333; + + NVSWITCH_NPORT_WR32_LS10(device, p->link, _MULTICASTTSTATE, _STAT_RESIDENCY_COUNT_CTRL, + DRF_NUM(_MULTICASTTSTATE, _STAT_RESIDENCY_COUNT_CTRL, _INDEX, 0) | + DRF_DEF(_MULTICASTTSTATE, _STAT_RESIDENCY_COUNT_CTRL, _AUTOINCR, _ON)); + for (i = 0; i < NVSWITCH_RESIDENCY_BIN_SIZE; i++) + { + // Low + val = NVSWITCH_NPORT_RD32_LS10(device, p->link, _MULTICASTTSTATE, _STAT_RESIDENCY_COUNT_DATA); + val_hi = NVSWITCH_NPORT_RD32_LS10(device, p->link, _MULTICASTTSTATE, _STAT_RESIDENCY_COUNT_DATA); + p->residency[i].low = (val_hi << 32) | val; + + // Medium + val = NVSWITCH_NPORT_RD32_LS10(device, p->link, _MULTICASTTSTATE, _STAT_RESIDENCY_COUNT_DATA); + val_hi = NVSWITCH_NPORT_RD32_LS10(device, p->link, _MULTICASTTSTATE, _STAT_RESIDENCY_COUNT_DATA); + p->residency[i].medium = (val_hi << 32) | val; + + // High + val = NVSWITCH_NPORT_RD32_LS10(device, p->link, _MULTICASTTSTATE, _STAT_RESIDENCY_COUNT_DATA); + val_hi = NVSWITCH_NPORT_RD32_LS10(device, p->link, _MULTICASTTSTATE, _STAT_RESIDENCY_COUNT_DATA); + p->residency[i].high = (val_hi << 32) | val; + } + + // Reset the histogram + NVSWITCH_NPORT_WR32_LS10(device, p->link, _MULTICASTTSTATE, _STAT_RESIDENCY_CONTROL, + DRF_DEF(_MULTICASTTSTATE, _STAT_RESIDENCY_CONTROL, _ENABLE_TIMER, _ENABLE) | + DRF_DEF(_MULTICASTTSTATE, _STAT_RESIDENCY_CONTROL, _SNAP_ON_DEMAND, _DISABLE)); + + } + else if (p->table_select == NVSWITCH_TABLE_SELECT_REDUCTION) + { + // Snap the histogram + NVSWITCH_NPORT_WR32_LS10(device, p->link, _REDUCTIONTSTATE, _STAT_RESIDENCY_CONTROL, + DRF_DEF(_REDUCTIONTSTATE, _STAT_RESIDENCY_CONTROL, _ENABLE_TIMER, _ENABLE) | + DRF_DEF(_REDUCTIONTSTATE, _STAT_RESIDENCY_CONTROL, _SNAP_ON_DEMAND, _ENABLE)); + + // Read high/low thresholds and convery clocks to nsec + val = NVSWITCH_NPORT_RD32_LS10(device, p->link, _REDUCTIONTSTATE, _STAT_RESIDENCY_BIN_CTRL_LOW); + threshold = DRF_VAL(_REDUCTIONTSTATE, _STAT_RESIDENCY_BIN_CTRL_LOW, _LIMIT, val); + p->bin.lowThreshold = threshold * 1000 / 1333; + + val = NVSWITCH_NPORT_RD32_LS10(device, p->link, _REDUCTIONTSTATE, _STAT_RESIDENCY_BIN_CTRL_HIGH); + threshold = DRF_VAL(_REDUCTIONTSTATE, _STAT_RESIDENCY_BIN_CTRL_HIGH, _LIMIT, val); + p->bin.hiThreshold = threshold * 1000 / 1333; + + NVSWITCH_NPORT_WR32_LS10(device, p->link, _REDUCTIONTSTATE, _STAT_RESIDENCY_COUNT_CTRL, + DRF_NUM(_REDUCTIONTSTATE, _STAT_RESIDENCY_COUNT_CTRL, _INDEX, 0) | + DRF_DEF(_REDUCTIONTSTATE, _STAT_RESIDENCY_COUNT_CTRL, _AUTOINCR, _ON)); + for (i = 0; i < NVSWITCH_RESIDENCY_BIN_SIZE; i++) + { + // Low + val = NVSWITCH_NPORT_RD32_LS10(device, p->link, _REDUCTIONTSTATE, _STAT_RESIDENCY_COUNT_DATA); + val_hi = NVSWITCH_NPORT_RD32_LS10(device, p->link, _REDUCTIONTSTATE, _STAT_RESIDENCY_COUNT_DATA); + p->residency[i].low = (val_hi << 32) | val; + + // Medium + val = NVSWITCH_NPORT_RD32_LS10(device, p->link, _REDUCTIONTSTATE, _STAT_RESIDENCY_COUNT_DATA); + val_hi = NVSWITCH_NPORT_RD32_LS10(device, p->link, _REDUCTIONTSTATE, _STAT_RESIDENCY_COUNT_DATA); + p->residency[i].medium = (val_hi << 32) | val; + + // High + val = NVSWITCH_NPORT_RD32_LS10(device, p->link, _REDUCTIONTSTATE, _STAT_RESIDENCY_COUNT_DATA); + val_hi = NVSWITCH_NPORT_RD32_LS10(device, p->link, _REDUCTIONTSTATE, _STAT_RESIDENCY_COUNT_DATA); + p->residency[i].high = (val_hi << 32) | val; + } + + // Reset the histogram + NVSWITCH_NPORT_WR32_LS10(device, p->link, _REDUCTIONTSTATE, _STAT_RESIDENCY_CONTROL, + DRF_DEF(_REDUCTIONTSTATE, _STAT_RESIDENCY_CONTROL, _ENABLE_TIMER, _ENABLE) | + DRF_DEF(_REDUCTIONTSTATE, _STAT_RESIDENCY_CONTROL, _SNAP_ON_DEMAND, _DISABLE)); + } + else + { + NVSWITCH_PRINT(device, ERROR, + "GET_RESIDENCY_BINS: Invalid table %d\n", p->table_select); + return -NVL_ERR_NOT_SUPPORTED; + } + + return NVL_SUCCESS; +} + +/* + * CTRL_NVSWITCH_GET_RB_STALL_BUSY + */ +static NvlStatus +nvswitch_ctrl_get_rb_stall_busy_ls10 +( + nvswitch_device *device, + NVSWITCH_GET_RB_STALL_BUSY *p +) +{ + NvU64 val; + NvU64 val_hi; + + if (!nvswitch_is_link_valid(device, p->link)) + { + NVSWITCH_PRINT(device, ERROR, + "GET_RB_STALL_BUSY: Invalid link %d\n", p->link); + return -NVL_BAD_ARGS; + } + + if (p->table_select == NVSWITCH_TABLE_SELECT_MULTICAST) + { + // Snap the histogram + NVSWITCH_NPORT_WR32_LS10(device, p->link, _MULTICASTTSTATE, _STAT_STALL_BUSY_CONTROL, + DRF_DEF(_MULTICASTTSTATE, _STAT_STALL_BUSY_CONTROL, _ENABLE_TIMER, _ENABLE) | + DRF_DEF(_MULTICASTTSTATE, _STAT_STALL_BUSY_CONTROL, _SNAP_ON_DEMAND, _ENABLE)); + + // + // VC0 + // + + // Total time + val = NVSWITCH_NPORT_RD32_LS10(device, p->link, _MULTICASTTSTATE, _STAT_WINDOW_0_LOW); + val_hi = NVSWITCH_NPORT_RD32_LS10(device, p->link, _MULTICASTTSTATE, _STAT_WINDOW_0_HIGH); + p->vc0.time = ((val_hi << 32) | val) * 1000 / 1333; // in ns + + // Busy + val = NVSWITCH_NPORT_RD32_LS10(device, p->link, _MULTICASTTSTATE, _STAT_BUSY_TIMER_0_LOW); + val_hi = NVSWITCH_NPORT_RD32_LS10(device, p->link, _MULTICASTTSTATE, _STAT_BUSY_TIMER_0_HIGH); + p->vc0.busy = ((val_hi << 32) | val) * 1000 / 1333; // in ns + + // Stall + val = NVSWITCH_NPORT_RD32_LS10(device, p->link, _MULTICASTTSTATE, _STAT_STALL_TIMER_0_LOW); + val_hi = NVSWITCH_NPORT_RD32_LS10(device, p->link, _MULTICASTTSTATE, _STAT_STALL_TIMER_0_HIGH); + p->vc0.stall = ((val_hi << 32) | val) * 1000 / 1333; // in ns + + // + // VC1 + // + + // Total time + val = NVSWITCH_NPORT_RD32_LS10(device, p->link, _MULTICASTTSTATE, _STAT_WINDOW_1_LOW); + val_hi = NVSWITCH_NPORT_RD32_LS10(device, p->link, _MULTICASTTSTATE, _STAT_WINDOW_1_HIGH); + p->vc1.time = ((val_hi << 32) | val) * 1000 / 1333; // in ns + + // Busy + val = NVSWITCH_NPORT_RD32_LS10(device, p->link, _MULTICASTTSTATE, _STAT_BUSY_TIMER_1_LOW); + val_hi = NVSWITCH_NPORT_RD32_LS10(device, p->link, _MULTICASTTSTATE, _STAT_BUSY_TIMER_1_HIGH); + p->vc1.busy = ((val_hi << 32) | val) * 1000 / 1333; // in ns + + // Stall + val = NVSWITCH_NPORT_RD32_LS10(device, p->link, _MULTICASTTSTATE, _STAT_STALL_TIMER_1_LOW); + val_hi = NVSWITCH_NPORT_RD32_LS10(device, p->link, _MULTICASTTSTATE, _STAT_STALL_TIMER_1_HIGH); + p->vc1.stall = ((val_hi << 32) | val) * 1000 / 1333; // in ns + + // Reset the busy/stall counters + NVSWITCH_NPORT_WR32_LS10(device, p->link, _MULTICASTTSTATE, _STAT_STALL_BUSY_CONTROL, + DRF_DEF(_MULTICASTTSTATE, _STAT_STALL_BUSY_CONTROL, _ENABLE_TIMER, _ENABLE) | + DRF_DEF(_MULTICASTTSTATE, _STAT_STALL_BUSY_CONTROL, _SNAP_ON_DEMAND, _DISABLE)); + } + else if (p->table_select == NVSWITCH_TABLE_SELECT_REDUCTION) + { + // Snap the histogram + NVSWITCH_NPORT_WR32_LS10(device, p->link, _REDUCTIONTSTATE, _STAT_STALL_BUSY_CONTROL, + DRF_DEF(_REDUCTIONTSTATE, _STAT_STALL_BUSY_CONTROL, _ENABLE_TIMER, _ENABLE) | + DRF_DEF(_REDUCTIONTSTATE, _STAT_STALL_BUSY_CONTROL, _SNAP_ON_DEMAND, _ENABLE)); + // + // VC0 + // + + // Total time + val = NVSWITCH_NPORT_RD32_LS10(device, p->link, _REDUCTIONTSTATE, _STAT_WINDOW_0_LOW); + val_hi = NVSWITCH_NPORT_RD32_LS10(device, p->link, _REDUCTIONTSTATE, _STAT_WINDOW_0_HIGH); + p->vc0.time = ((val_hi << 32) | val) * 1000 / 1333; // in ns + + // Busy + val = NVSWITCH_NPORT_RD32_LS10(device, p->link, _REDUCTIONTSTATE, _STAT_BUSY_TIMER_0_LOW); + val_hi = NVSWITCH_NPORT_RD32_LS10(device, p->link, _REDUCTIONTSTATE, _STAT_BUSY_TIMER_0_HIGH); + p->vc0.busy = ((val_hi << 32) | val) * 1000 / 1333; // in ns + + // Stall + val = NVSWITCH_NPORT_RD32_LS10(device, p->link, _REDUCTIONTSTATE, _STAT_STALL_TIMER_0_LOW); + val_hi = NVSWITCH_NPORT_RD32_LS10(device, p->link, _REDUCTIONTSTATE, _STAT_STALL_TIMER_0_HIGH); + p->vc0.stall = ((val_hi << 32) | val) * 1000 / 1333; // in ns + + // + // VC1 + // + + // Total time + val = NVSWITCH_NPORT_RD32_LS10(device, p->link, _REDUCTIONTSTATE, _STAT_WINDOW_1_LOW); + val_hi = NVSWITCH_NPORT_RD32_LS10(device, p->link, _REDUCTIONTSTATE, _STAT_WINDOW_1_HIGH); + p->vc1.time = ((val_hi << 32) | val) * 1000 / 1333; // in ns + + // Busy + val = NVSWITCH_NPORT_RD32_LS10(device, p->link, _REDUCTIONTSTATE, _STAT_BUSY_TIMER_1_LOW); + val_hi = NVSWITCH_NPORT_RD32_LS10(device, p->link, _REDUCTIONTSTATE, _STAT_BUSY_TIMER_1_HIGH); + p->vc1.busy = ((val_hi << 32) | val) * 1000 / 1333; // in ns + + // Stall + val = NVSWITCH_NPORT_RD32_LS10(device, p->link, _REDUCTIONTSTATE, _STAT_STALL_TIMER_1_LOW); + val_hi = NVSWITCH_NPORT_RD32_LS10(device, p->link, _REDUCTIONTSTATE, _STAT_STALL_TIMER_1_HIGH); + p->vc1.stall = ((val_hi << 32) | val) * 1000 / 1333; // in ns + + // Reset the histogram + NVSWITCH_NPORT_WR32_LS10(device, p->link, _REDUCTIONTSTATE, _STAT_STALL_BUSY_CONTROL, + DRF_DEF(_REDUCTIONTSTATE, _STAT_STALL_BUSY_CONTROL, _ENABLE_TIMER, _ENABLE) | + DRF_DEF(_REDUCTIONTSTATE, _STAT_STALL_BUSY_CONTROL, _SNAP_ON_DEMAND, _DISABLE)); + } + else + { + NVSWITCH_PRINT(device, ERROR, + "GET_RB_STALL_BUSY: Invalid table %d\n", p->table_select); + return -NVL_ERR_NOT_SUPPORTED; + } + + return NVL_SUCCESS; +} + +/* + * CTRL_NVSWITCH_GET_MULTICAST_ID_ERROR_VECTOR + */ +static NvlStatus +nvswitch_ctrl_get_multicast_id_error_vector_ls10 +( + nvswitch_device *device, + NVSWITCH_GET_MULTICAST_ID_ERROR_VECTOR *p +) +{ + NvU32 i; + + ct_assert(NV_NPORT_MCID_ERROR_VECTOR__SIZE_1 == (NVSWITCH_MC_ID_ERROR_VECTOR_COUNT / 32)); + + if (!NVSWITCH_IS_LINK_ENG_VALID(device, p->link, NPORT)) + { + NVSWITCH_PRINT(device, ERROR, + "GET_MULTICAST_ID_ERROR_VECTOR: Invalid link %d\n", p->link); + return -NVL_BAD_ARGS; + } + + for (i = 0; i < NV_NPORT_MCID_ERROR_VECTOR__SIZE_1; i++) + { + p->error_vector[i] = NVSWITCH_LINK_RD32(device, p->link, NPORT, _NPORT, + _MCID_ERROR_VECTOR(i)); + } + + return NVL_SUCCESS; +} + +/* + * CTRL_NVSWITCH_GET_MULTICAST_ID_ERROR_VECTOR + */ +static NvlStatus +nvswitch_ctrl_clear_multicast_id_error_vector_ls10 +( + nvswitch_device *device, + NVSWITCH_CLEAR_MULTICAST_ID_ERROR_VECTOR *p +) +{ + NvU32 i; + + ct_assert(NV_NPORT_MCID_ERROR_VECTOR__SIZE_1 == (NVSWITCH_MC_ID_ERROR_VECTOR_COUNT / 32)); + + if (!NVSWITCH_IS_LINK_ENG_VALID(device, p->link, NPORT)) + { + NVSWITCH_PRINT(device, ERROR, + "CLEAR_MULTICAST_ID_ERROR_VECTOR: Invalid link %d\n", p->link); + return -NVL_BAD_ARGS; + } + + for (i = 0; i < NV_NPORT_MCID_ERROR_VECTOR__SIZE_1; i++) + { + NVSWITCH_LINK_WR32(device, p->link, NPORT, _NPORT, + _MCID_ERROR_VECTOR(i), p->error_vector[i]); + } + + return NVL_SUCCESS; +} + +void +nvswitch_load_uuid_ls10 +( + nvswitch_device *device +) +{ + NvU32 regData[4]; + + // + // Read 128-bit UUID from secure scratch registers which must be + // populated by firmware. + // + regData[0] = NVSWITCH_SAW_RD32_LS10(device, _NVLSAW, _SECURE_SCRATCH_WARM_GROUP_1(0)); + regData[1] = NVSWITCH_SAW_RD32_LS10(device, _NVLSAW, _SECURE_SCRATCH_WARM_GROUP_1(1)); + regData[2] = NVSWITCH_SAW_RD32_LS10(device, _NVLSAW, _SECURE_SCRATCH_WARM_GROUP_1(2)); + regData[3] = NVSWITCH_SAW_RD32_LS10(device, _NVLSAW, _SECURE_SCRATCH_WARM_GROUP_1(3)); + + nvswitch_os_memcpy(&device->uuid.uuid, (NvU8 *)regData, NV_UUID_LEN); +} + +NvlStatus +nvswitch_launch_ALI_ls10 +( + nvswitch_device *device +) +{ + NvU64 enabledLinkMask; + NvU64 forcedConfgLinkMask = 0; + NvBool bEnableAli = NV_FALSE; + NvU64 i = 0; + nvlink_link *link; + + enabledLinkMask = nvswitch_get_enabled_link_mask(device); + forcedConfgLinkMask = ((NvU64)device->regkeys.chiplib_forced_config_link_mask) + + ((NvU64)device->regkeys.chiplib_forced_config_link_mask2 << 32); + + // + // Currently, we don't support a mix of forced/auto config links + // return early + // + if (forcedConfgLinkMask != 0) + { + return -NVL_ERR_NOT_SUPPORTED; + } + +#ifdef INCLUDE_NVLINK_LIB + bEnableAli = device->nvlink_device->enableALI; +#endif + + if (!bEnableAli) + { + NVSWITCH_PRINT(device, INFO, + "%s: ALI not supported on the given device\n", + __FUNCTION__); + return NVL_ERR_GENERIC; + } + + FOR_EACH_INDEX_IN_MASK(64, i, enabledLinkMask) + { + NVSWITCH_ASSERT(i < NVSWITCH_LINK_COUNT(device)); + + link = nvswitch_get_link(device, i); + + if ((link == NULL) || + !NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLIPT_LNK, link->linkNumber) || + (i >= NVSWITCH_NVLINK_MAX_LINKS)) + { + continue; + } + + nvswitch_launch_ALI_link_training(device, link, NV_FALSE); + } + FOR_EACH_INDEX_IN_MASK_END; + + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_set_training_mode_ls10 +( + nvswitch_device *device +) +{ + NvU64 enabledLinkMask, forcedConfgLinkMask; + + NvU32 regVal; + NvU64 i = 0; + nvlink_link *link; + + enabledLinkMask = nvswitch_get_enabled_link_mask(device); + forcedConfgLinkMask = ((NvU64)device->regkeys.chiplib_forced_config_link_mask) + + ((NvU64)device->regkeys.chiplib_forced_config_link_mask2 << 32); + + // + // Currently, we don't support a mix of forced/auto config links + // return early + // + if (forcedConfgLinkMask != 0) + { + NVSWITCH_PRINT(device, INFO, + "%s: Forced-config set, skipping setting up link training selection\n", + __FUNCTION__); + return NVL_SUCCESS; + } + + if (device->regkeys.link_training_mode == NV_SWITCH_REGKEY_LINK_TRAINING_SELECT_ALI) + { + // + // If ALI is force enabled then check to make sure ALI is supported + // and write to the SYSTEM_CTRL register to force it to enabled + // + FOR_EACH_INDEX_IN_MASK(64, i, enabledLinkMask) + { + NVSWITCH_ASSERT(i < NVSWITCH_LINK_COUNT(device)); + + link = nvswitch_get_link(device, i); + + if ((link == NULL) || + !NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLIPT_LNK, link->linkNumber) || + (i >= NVSWITCH_NVLINK_MAX_LINKS)) + { + continue; + } + + regVal = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, NVLIPT_LNK, _NVLIPT_LNK, + _CTRL_CAP_LOCAL_LINK_CHANNEL); + + if (!FLD_TEST_DRF(_NVLIPT_LNK, _CTRL_CAP_LOCAL_LINK_CHANNEL, _ALI_SUPPORT, _SUPPORTED, regVal)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: ALI training not supported! Regkey forcing ALI will be ignored\n",__FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + NVSWITCH_PRINT(device, INFO, + "%s: ALI training set on link: 0x%llx\n", + __FUNCTION__, i); + + regVal = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, NVLIPT_LNK, _NVLIPT_LNK, + _CTRL_SYSTEM_LINK_CHANNEL_CTRL2); + + regVal = FLD_SET_DRF(_NVLIPT_LNK, _CTRL_SYSTEM_LINK_CHANNEL_CTRL2, _ALI_ENABLE, _ENABLE, regVal); + NVSWITCH_LINK_WR32_LS10(device, link->linkNumber, NVLIPT_LNK, _NVLIPT_LNK, + _CTRL_SYSTEM_LINK_CHANNEL_CTRL2, regVal); + + } + FOR_EACH_INDEX_IN_MASK_END; + } + else if (device->regkeys.link_training_mode == NV_SWITCH_REGKEY_LINK_TRAINING_SELECT_NON_ALI) + { + // If non-ALI is force enabled then disable ALI + FOR_EACH_INDEX_IN_MASK(64, i, enabledLinkMask) + { + NVSWITCH_ASSERT(i < NVSWITCH_LINK_COUNT(device)); + + link = nvswitch_get_link(device, i); + + if ((link == NULL) || + !NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLIPT_LNK, link->linkNumber) || + (i >= NVSWITCH_NVLINK_MAX_LINKS)) + { + continue; + } + + regVal = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, NVLIPT_LNK, _NVLIPT_LNK, + _CTRL_SYSTEM_LINK_CHANNEL_CTRL2); + + regVal = FLD_SET_DRF(_NVLIPT_LNK, _CTRL_SYSTEM_LINK_CHANNEL_CTRL2, _ALI_ENABLE, _DISABLE, regVal); + NVSWITCH_LINK_WR32_LS10(device, link->linkNumber, NVLIPT_LNK, _NVLIPT_LNK, + _CTRL_SYSTEM_LINK_CHANNEL_CTRL2, regVal); + + } + FOR_EACH_INDEX_IN_MASK_END; + + } + else + { + // Else sanity check the SYSTEM register settings + FOR_EACH_INDEX_IN_MASK(64, i, enabledLinkMask) + { + NVSWITCH_ASSERT(i < NVSWITCH_LINK_COUNT(device)); + + link = nvswitch_get_link(device, i); + + if ((link == NULL) || + !NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLIPT_LNK, link->linkNumber) || + (i >= NVSWITCH_NVLINK_MAX_LINKS)) + { + continue; + } + + regVal = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, NVLIPT_LNK, _NVLIPT_LNK, + _CTRL_SYSTEM_LINK_CHANNEL_CTRL2); + + if (FLD_TEST_DRF(_NVLIPT_LNK, _CTRL_SYSTEM_LINK_CHANNEL_CTRL2, _ALI_ENABLE, _ENABLE, regVal)) + { + + regVal = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, NVLIPT_LNK, _NVLIPT_LNK, + _CTRL_CAP_LOCAL_LINK_CHANNEL); + + if (!FLD_TEST_DRF(_NVLIPT_LNK, _CTRL_CAP_LOCAL_LINK_CHANNEL, _ALI_SUPPORT, _SUPPORTED, regVal)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: ALI training not supported! Non-ALI will be used as the default.\n",__FUNCTION__); +#ifdef INCLUDE_NVLINK_LIB + device->nvlink_device->enableALI = NV_FALSE; +#endif + return NVL_SUCCESS; + } +#ifdef INCLUDE_NVLINK_LIB + device->nvlink_device->enableALI = NV_TRUE; +#endif + } + else + { + NVSWITCH_PRINT(device, ERROR, + "%s: ALI training not enabled! Non-ALI will be used as the default.\n",__FUNCTION__); +#ifdef INCLUDE_NVLINK_LIB + device->nvlink_device->enableALI = NV_FALSE; +#endif + return NVL_SUCCESS; + } + } + FOR_EACH_INDEX_IN_MASK_END; + } + + return NVL_SUCCESS; +} + +static void +_nvswitch_get_nvlink_power_state_ls10 +( + nvswitch_device *device, + NVSWITCH_GET_NVLINK_STATUS_PARAMS *ret +) +{ + nvlink_link *link; + NvU32 linkState; + NvU32 linkPowerState; + NvU8 i; + + // Determine power state for each enabled link + FOR_EACH_INDEX_IN_MASK(64, i, ret->enabledLinkMask) + { + NVSWITCH_ASSERT(i < NVSWITCH_LINK_COUNT(device)); + + link = nvswitch_get_link(device, i); + + if ((link == NULL) || + (i >= NVSWITCH_NVLINK_MAX_LINKS)) + { + continue; + } + + linkState = ret->linkInfo[i].linkState; + + switch (linkState) + { + case NVSWITCH_NVLINK_STATUS_LINK_STATE_ACTIVE: + linkPowerState = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber, NVLIPT_LNK, _NVLIPT_LNK, _PWRM_CTRL); + + if (FLD_TEST_DRF(_NVLIPT_LNK, _PWRM_CTRL, _L1_CURRENT_STATE, _L1, linkPowerState)) + { + linkPowerState = NVSWITCH_NVLINK_STATUS_LINK_POWER_STATE_L1; + } + else + { + linkPowerState = NVSWITCH_NVLINK_STATUS_LINK_POWER_STATE_L0; + } + break; + + default: + linkPowerState = NVSWITCH_NVLINK_STATUS_LINK_POWER_STATE_INVALID; + break; + } + + ret->linkInfo[i].linkPowerState = linkPowerState; + } + FOR_EACH_INDEX_IN_MASK_END; +} + +NvlStatus +nvswitch_ctrl_get_nvlink_status_ls10 +( + nvswitch_device *device, + NVSWITCH_GET_NVLINK_STATUS_PARAMS *ret +) +{ + NvlStatus retval = NVL_SUCCESS; + + retval = nvswitch_ctrl_get_nvlink_status_lr10(device, ret); + + if (retval != NVL_SUCCESS) + { + return retval; + } + + _nvswitch_get_nvlink_power_state_ls10(device, ret); + + return retval; +} + +NvlStatus +nvswitch_parse_bios_image_ls10 +( + nvswitch_device *device +) +{ + return nvswitch_parse_bios_image_lr10(device); +} + +static NvlStatus +nvswitch_split_and_send_inband_data_ls10 +( + nvswitch_device *device, + NvU32 linkId, + nvswitch_inband_send_data *inBandData +) +{ + NvlStatus status = NVL_SUCCESS; + NvU32 i; + NvU32 bytes; + NvU32 maxSplitSize = NVLINK_INBAND_MAX_XFER_SIZE; + NvU32 totalBytesToSend = inBandData->bufferSize; + NvU32 numChunks = NV_ALIGN_UP(inBandData->bufferSize, maxSplitSize) / + maxSplitSize; + + inBandData->hdr.data = NVLINK_INBAND_DRV_HDR_TYPE_START; + bytes = NV_MIN(totalBytesToSend, maxSplitSize); + + NVSWITCH_ASSERT(numChunks != 0); + + for (i = 0; i < numChunks; i++) + { + inBandData->bufferSize = bytes; + // Last chunk + if (i == (numChunks - 1)) + { + // + // A chunk can have both _START and _END set at the same time, if it + // is the only chunk being sent. + // + inBandData->hdr.data |= NVLINK_INBAND_DRV_HDR_TYPE_END; + inBandData->hdr.data &= ~NVLINK_INBAND_DRV_HDR_TYPE_MID; // clear + } + + status = nvswitch_minion_send_inband_data_ls10(device, linkId, inBandData); + if (status != NVL_SUCCESS) + return status; + + inBandData->sendBuffer += bytes; + totalBytesToSend -= bytes; + + bytes = NV_MIN(totalBytesToSend, maxSplitSize); + inBandData->hdr.data = NVLINK_INBAND_DRV_HDR_TYPE_MID; + } + + return NVL_SUCCESS; +} + +void +nvswitch_send_inband_nack_ls10 +( + nvswitch_device *device, + NvU32 *hdr, + NvU32 linkId +) +{ + NvlStatus status; + nvswitch_inband_send_data inBandData; + nvlink_inband_msg_header_t *msghdr = (nvlink_inband_msg_header_t *)hdr; + + msghdr->status = NV_ERR_FABRIC_MANAGER_NOT_PRESENT; + switch (msghdr->type) + { + case NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_REQ: + msghdr->type = NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_RSP; + break; + default: + NVSWITCH_PRINT(device, ERROR, "%s:Wrong HDR type for NACK\n", + __FUNCTION__); + return; + } + msghdr->length = 0; + + inBandData.sendBuffer = (NvU8 *)msghdr; + inBandData.bufferSize = sizeof(nvlink_inband_msg_header_t); + + status = nvswitch_split_and_send_inband_data_ls10(device, linkId, &inBandData); + + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s:Sending NACK failed\n", + __FUNCTION__); + } +} + +NvU32 +nvswitch_get_max_persistent_message_count_ls10 +( + nvswitch_device *device +) +{ + return NUM_MAX_MCFLA_SLOTS_LS10; +} + +/* + * CTRL_NVSWITCH_INBAND_SEND_DATA + */ +NvlStatus +nvswitch_ctrl_inband_send_data_ls10 +( + nvswitch_device *device, + NVSWITCH_INBAND_SEND_DATA_PARAMS *p +) +{ + NvlStatus status; + nvswitch_inband_send_data inBandData; + + // ct_assert(NVLINK_INBAND_MAX_MSG_SIZE >= NVSWITCH_INBAND_DATA_SIZE); + + if (p->dataSize == 0 || p->dataSize > NVSWITCH_INBAND_DATA_SIZE) + { + NVSWITCH_PRINT(device, ERROR, "Bad Inband data, got buffer of 0. Skipping Inband Send\n"); + return -NVL_BAD_ARGS; + } + + if (!device->hal.nvswitch_is_link_valid(device, p->linkId)) + { + NVSWITCH_PRINT(device, ERROR, "Bad linkId %d is wrong\n", p->linkId); + return -NVL_BAD_ARGS; + } + + inBandData.sendBuffer = p->buffer; + inBandData.bufferSize = p->dataSize; + + status = nvswitch_split_and_send_inband_data_ls10(device, p->linkId, &inBandData); + + if (status != NVL_SUCCESS) + { + return status; + } + + p->dataSent = p->dataSize; + + return NVL_SUCCESS; +} + +/* + * CTRL_NVSWITCH_INBAND_READ_DATA + */ +NvlStatus +nvswitch_ctrl_inband_read_data_ls10 +( + nvswitch_device *device, + NVSWITCH_INBAND_READ_DATA_PARAMS *p +) +{ + if (!device->hal.nvswitch_is_link_valid(device, p->linkId)) + { + NVSWITCH_PRINT(device, ERROR, "Bad linkId %d is wrong\n", p->linkId); + return -NVL_BAD_ARGS; + } + + return nvswitch_inband_read_data(device, p->buffer, p->linkId, &p->dataSize); +} + +NvlStatus +nvswitch_ctrl_get_nvlink_lp_counters_ls10 +( + nvswitch_device *device, + NVSWITCH_GET_NVLINK_LP_COUNTERS_PARAMS *params +) +{ + NvU32 counterValidMaskOut; + NvU32 counterValidMask; + NvU32 cntIdx; + NV_STATUS status; + NvU32 statData; + + if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLDL, params->linkId)) + { + return -NVL_BAD_ARGS; + } + + counterValidMaskOut = 0; + counterValidMask = params->counterValidMask; + + cntIdx = CTRL_NVSWITCH_GET_NVLINK_LP_COUNTERS_COUNT_TX_NVHS; + if (counterValidMask & NVBIT32(cntIdx)) + { + status = nvswitch_minion_get_dl_status(device, params->linkId, + NV_NVLSTAT_TX01, 0, &statData); + if (status != NVL_SUCCESS) + { + return status; + } + params->counterValues[cntIdx] = DRF_VAL(_NVLSTAT_TX01, _COUNT_TX_STATE, + _NVHS_VALUE, statData); + counterValidMaskOut |= NVBIT32(cntIdx); + } + + cntIdx = CTRL_NVSWITCH_GET_NVLINK_LP_COUNTERS_COUNT_TX_OTHER; + if (counterValidMask & NVBIT32(cntIdx)) + { + status = nvswitch_minion_get_dl_status(device, params->linkId, + NV_NVLSTAT_TX02, 0, &statData); + if (status != NVL_SUCCESS) + { + return status; + } + params->counterValues[cntIdx] = DRF_VAL(_NVLSTAT_TX02, _COUNT_TX_STATE, + _OTHER_VALUE, statData); + counterValidMaskOut |= NVBIT32(cntIdx); + } + + cntIdx = CTRL_NVSWITCH_GET_NVLINK_LP_COUNTERS_NUM_TX_LP_ENTER; + if (counterValidMask & NVBIT32(cntIdx)) + { + status = nvswitch_minion_get_dl_status(device, params->linkId, + NV_NVLSTAT_TX06, 0, &statData); + if (status != NVL_SUCCESS) + { + return status; + } + params->counterValues[cntIdx] = DRF_VAL(_NVLSTAT_TX06, _NUM_LCL, + _LP_ENTER_VALUE, statData); + counterValidMaskOut |= NVBIT32(cntIdx); + } + + cntIdx = CTRL_NVSWITCH_GET_NVLINK_LP_COUNTERS_NUM_TX_LP_EXIT; + if (counterValidMask & NVBIT32(cntIdx)) + { + status = nvswitch_minion_get_dl_status(device, params->linkId, + NV_NVLSTAT_TX05, 0, &statData); + if (status != NVL_SUCCESS) + { + return status; + } + params->counterValues[cntIdx] = DRF_VAL(_NVLSTAT_TX05, _NUM_LCL, + _LP_EXIT_VALUE, statData); + counterValidMaskOut |= NVBIT32(cntIdx); + } + + cntIdx = CTRL_NVSWITCH_GET_NVLINK_LP_COUNTERS_COUNT_TX_SLEEP; + if (counterValidMask & NVBIT32(cntIdx)) + { + status = nvswitch_minion_get_dl_status(device, params->linkId, + NV_NVLSTAT_TX10, 0, &statData); + if (status != NVL_SUCCESS) + { + return status; + } + params->counterValues[cntIdx] = DRF_VAL(_NVLSTAT_TX10, _COUNT_TX_STATE, + _SLEEP_VALUE, statData); + counterValidMaskOut |= NVBIT32(cntIdx); + } + + params->counterValidMask = counterValidMaskOut; + + return NVL_SUCCESS; +} + +static NvlStatus +nvswitch_ctrl_clear_counters_ls10 +( + nvswitch_device *device, + NVSWITCH_NVLINK_CLEAR_COUNTERS_PARAMS *ret +) +{ + nvlink_link *link; + NvU8 i; + NvU32 counterMask; + NvlStatus status = NVL_SUCCESS; + + counterMask = ret->counterMask; + + FOR_EACH_INDEX_IN_MASK(64, i, ret->linkMask) + { + link = nvswitch_get_link(device, i); + if (link == NULL) + { + continue; + } + + counterMask = ret->counterMask; + + if ((counterMask & NVSWITCH_NVLINK_COUNTER_PHY_REFRESH_PASS) || + (counterMask & NVSWITCH_NVLINK_COUNTER_PHY_REFRESH_FAIL)) + { + status = nvswitch_minion_send_command(device, link->linkNumber, + NV_MINION_NVLINK_DL_CMD_COMMAND_DLSTAT_CLR_MINION_MISCCNT, 0); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s : Failed to clear misc count to MINION for link # %d\n", + __FUNCTION__, link->linkNumber); + } + counterMask &= + ~(NVSWITCH_NVLINK_COUNTER_PHY_REFRESH_PASS | NVSWITCH_NVLINK_COUNTER_PHY_REFRESH_FAIL); + } + + nvswitch_ctrl_clear_throughput_counters_ls10(device, link, counterMask); + nvswitch_ctrl_clear_lp_counters_ls10(device, link, counterMask); + status = nvswitch_ctrl_clear_dl_error_counters_ls10(device, link, counterMask); + + // Return early with failure on clearing through minion + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failure on clearing link counter mask 0x%x on link %d\n", + __FUNCTION__, counterMask, link->linkNumber); + break; + } + } + FOR_EACH_INDEX_IN_MASK_END; + + return status; +} + +NvlStatus +nvswitch_read_vbios_link_entries_ls10 +( + nvswitch_device *device, + NvU32 tblPtr, + NvU32 expected_link_entriesCount, + NVLINK_CONFIG_DATA_LINKENTRY *link_entries, + NvU32 *identified_link_entriesCount +) +{ + NV_STATUS status = NV_ERR_INVALID_PARAMETER; + NvU32 i; + NVLINK_VBIOS_CONFIG_DATA_LINKENTRY_30 vbios_link_entry; + *identified_link_entriesCount = 0; + + for (i = 0; i < expected_link_entriesCount; i++) + { + if (!device->bIsNvlinkVbiosTableVersion2) + { + status = device->hal.nvswitch_vbios_read_structure(device, + &vbios_link_entry, + tblPtr, (NvU32 *)0, + NVLINK_CONFIG_DATA_LINKENTRY_FMT_30); + } + else + { + status = device->hal.nvswitch_vbios_read_structure(device, + &vbios_link_entry, + tblPtr, (NvU32 *)0, + NVLINK_CONFIG_DATA_LINKENTRY_FMT_20); + } + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Error on reading nvlink entry\n", + __FUNCTION__); + return status; + } + link_entries[i].nvLinkparam0 = (NvU8)vbios_link_entry.nvLinkparam0; + link_entries[i].nvLinkparam1 = (NvU8)vbios_link_entry.nvLinkparam1; + link_entries[i].nvLinkparam2 = (NvU8)vbios_link_entry.nvLinkparam2; + link_entries[i].nvLinkparam3 = (NvU8)vbios_link_entry.nvLinkparam3; + link_entries[i].nvLinkparam4 = (NvU8)vbios_link_entry.nvLinkparam4; + link_entries[i].nvLinkparam5 = (NvU8)vbios_link_entry.nvLinkparam5; + link_entries[i].nvLinkparam6 = (NvU8)vbios_link_entry.nvLinkparam6; + if (!device->bIsNvlinkVbiosTableVersion2) + { + link_entries[i].nvLinkparam7 = (NvU8)vbios_link_entry.nvLinkparam7; + link_entries[i].nvLinkparam8 = (NvU8)vbios_link_entry.nvLinkparam8; + link_entries[i].nvLinkparam9 = (NvU8)vbios_link_entry.nvLinkparam9; + } + if (!device->bIsNvlinkVbiosTableVersion2) + tblPtr += (sizeof(NVLINK_VBIOS_CONFIG_DATA_LINKENTRY_30)/sizeof(NvU32)); + else + tblPtr += (sizeof(NVLINK_VBIOS_CONFIG_DATA_LINKENTRY_20)/sizeof(NvU32)); + + + NVSWITCH_PRINT(device, SETUP, + "<<<---- NvLink ID 0x%x ---->>>\n", i); + NVSWITCH_PRINT(device, SETUP, + "NVLink Params 0 \t0x%x \tBinary:"BYTE_TO_BINARY_PATTERN"\n", vbios_link_entry.nvLinkparam0, BYTE_TO_BINARY(vbios_link_entry.nvLinkparam0)); + NVSWITCH_PRINT(device, SETUP, + "NVLink Params 1 \t0x%x \tBinary:"BYTE_TO_BINARY_PATTERN"\n", vbios_link_entry.nvLinkparam1, BYTE_TO_BINARY(vbios_link_entry.nvLinkparam1)); + NVSWITCH_PRINT(device, SETUP, + "NVLink Params 2 \t0x%x \tBinary:"BYTE_TO_BINARY_PATTERN"\n", vbios_link_entry.nvLinkparam2, BYTE_TO_BINARY(vbios_link_entry.nvLinkparam2)); + NVSWITCH_PRINT(device, SETUP, + "NVLink Params 3 \t0x%x \tBinary:"BYTE_TO_BINARY_PATTERN"\n", vbios_link_entry.nvLinkparam3, BYTE_TO_BINARY(vbios_link_entry.nvLinkparam3)); + NVSWITCH_PRINT(device, SETUP, + "NVLink Params 4 \t0x%x \tBinary:"BYTE_TO_BINARY_PATTERN"\n", vbios_link_entry.nvLinkparam4, BYTE_TO_BINARY(vbios_link_entry.nvLinkparam4)); + NVSWITCH_PRINT(device, SETUP, + "NVLink Params 5 \t0x%x \tBinary:"BYTE_TO_BINARY_PATTERN"\n", vbios_link_entry.nvLinkparam5, BYTE_TO_BINARY(vbios_link_entry.nvLinkparam5)); + NVSWITCH_PRINT(device, SETUP, + "NVLink Params 6 \t0x%x \tBinary:"BYTE_TO_BINARY_PATTERN"\n", vbios_link_entry.nvLinkparam6, BYTE_TO_BINARY(vbios_link_entry.nvLinkparam6)); + NVSWITCH_PRINT(device, SETUP, + "NVLink Params 7 \t0x%x \tBinary:"BYTE_TO_BINARY_PATTERN"\n", vbios_link_entry.nvLinkparam7, BYTE_TO_BINARY(vbios_link_entry.nvLinkparam7)); + NVSWITCH_PRINT(device, SETUP, + "NVLink Params 8 \t0x%x \tBinary:"BYTE_TO_BINARY_PATTERN"\n", vbios_link_entry.nvLinkparam8, BYTE_TO_BINARY(vbios_link_entry.nvLinkparam8)); + NVSWITCH_PRINT(device, SETUP, + "NVLink Params 9 \t0x%x \tBinary:"BYTE_TO_BINARY_PATTERN"\n", vbios_link_entry.nvLinkparam9, BYTE_TO_BINARY(vbios_link_entry.nvLinkparam9)); + NVSWITCH_PRINT(device, SETUP, + "<<<---- NvLink ID 0x%x ---->>>\n\n", i); + } + *identified_link_entriesCount = i; + return status; +} + +NvlStatus +nvswitch_ctrl_get_bios_info_ls10 +( + nvswitch_device *device, + NVSWITCH_GET_BIOS_INFO_PARAMS *p +) +{ + NvU32 biosVersionBytes; + NvU32 biosOemVersionBytes; + NvU32 biosMagic = 0x9610; + + // + // Example: 96.10.09.00.00 is the formatted version string + // | | | + // | | |__ BIOS OEM version byte + // | | + // |_________|_____ BIOS version bytes + // + biosVersionBytes = NVSWITCH_SAW_RD32_LS10(device, _NVLSAW_SW, _BIOS_VERSION); + biosOemVersionBytes = NVSWITCH_SAW_RD32_LS10(device, _NVLSAW_SW, _OEM_BIOS_VERSION); + + // + // LS10 is built out of core96 and the BIOS version will always begin with + // 96.10.xx.xx.xx + // + if ((biosVersionBytes >> 16) != biosMagic) + { + NVSWITCH_PRINT(device, ERROR, + "BIOS version not found in scratch register\n"); + return -NVL_ERR_INVALID_STATE; + } + + p->version = (((NvU64)biosVersionBytes) << 8) | (biosOemVersionBytes & 0xff); + + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_ctrl_get_inforom_version_ls10 +( + nvswitch_device *device, + NVSWITCH_GET_INFOROM_VERSION_PARAMS *p +) +{ + struct inforom *pInforom = device->pInforom; + + if ((pInforom == NULL) || (!pInforom->IMG.bValid)) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + if (NV_ARRAY_ELEMENTS(pInforom->IMG.object.version) < + NVSWITCH_INFOROM_VERSION_LEN) + { + NVSWITCH_PRINT(device, ERROR, + "Inforom IMG object struct smaller than expected\n"); + return -NVL_ERR_INVALID_STATE; + } + + nvswitch_inforom_string_copy(pInforom->IMG.object.version, p->version, + NVSWITCH_INFOROM_VERSION_LEN); + + return NVL_SUCCESS; +} + +// +// This function auto creates the ls10 HAL connectivity from the NVSWITCH_INIT_HAL +// macro in haldef_nvswitch.h +// +// Note: All hal fns must be implemented for each chip. +// There is no automatic stubbing here. +// +void nvswitch_setup_hal_ls10(nvswitch_device *device) +{ + device->chip_arch = NVSWITCH_GET_INFO_INDEX_ARCH_LS10; + device->chip_impl = NVSWITCH_GET_INFO_INDEX_IMPL_LS10; + + NVSWITCH_INIT_HAL(device, ls10); + NVSWITCH_INIT_HAL_LS10(device, ls10); +} + diff --git a/src/common/nvswitch/kernel/ls10/minion_ls10.c b/src/common/nvswitch/kernel/ls10/minion_ls10.c new file mode 100644 index 000000000..45da88d6a --- /dev/null +++ b/src/common/nvswitch/kernel/ls10/minion_ls10.c @@ -0,0 +1,975 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvlink_export.h" + +#include "common_nvswitch.h" +#include "ls10/ls10.h" +#include "ls10/minion_ls10.h" +#include "ls10/minion_nvlink_defines_public_ls10.h" +#include "regkey_nvswitch.h" + +#include "nvswitch/ls10/dev_minion_ip.h" +#include "nvswitch/ls10/dev_minion_ip_addendum.h" +#include "nvswitch/ls10/dev_ingress_ip.h" +#include "nvswitch/ls10/dev_egress_ip.h" +#include "nvswitch/ls10/dev_riscv_pri.h" +#include "nvswitch/ls10/dev_nvlphyctl_ip.h" + +#include "flcn/flcn_nvswitch.h" + +/* + * @Brief : Check if MINION is already running. + * + * The function assumes that if one of MINIONs is running, all of them are + * running. This approach needs to be fixed. + * + * TODO: Refactor minion code to check for each minion's status individually. + * + * @param[in] device Bootstrap MINIONs on this device + */ +static NvBool +_nvswitch_check_running_minions +( + nvswitch_device *device +) +{ + NvU32 data, i; + NvBool bMinionRunning = NV_FALSE; + + for (i = 0; i < NUM_MINION_ENGINE_LS10; i++) + { + if (!NVSWITCH_ENG_VALID_LS10(device, MINION, i)) + { + NVSWITCH_PRINT(device, SETUP, + "%s: MINION instance %d is not valid.\n", + __FUNCTION__, i); + continue; + } + + data = NVSWITCH_MINION_RD32_LS10(device, i, _CMINION, _FALCON_IRQSTAT); + if (FLD_TEST_DRF(_CMINION, _FALCON_IRQSTAT, _HALT, _FALSE, data)) + { + data = NVSWITCH_MINION_RD32_LS10(device, i, _MINION, _MINION_STATUS); + if (FLD_TEST_DRF(_MINION, _MINION_STATUS, _STATUS, _BOOT, data)) + { + // + // Set initialized flag if MINION is running. + // We don't want to bootstrap a falcon that is already running. + // + nvswitch_set_minion_initialized(device, i, NV_TRUE); + + NVSWITCH_PRINT(device, SETUP, + "%s: MINION instance %d is already bootstrapped.\n", + __FUNCTION__, i); + bMinionRunning = NV_TRUE; + } + } + } + + return bMinionRunning; +} + +NvlStatus +nvswitch_minion_get_dl_status_ls10 +( + nvswitch_device *device, + NvU32 linkId, + NvU32 statusIdx, + NvU32 statusArgs, + NvU32 *statusData +) +{ + NVSWITCH_TIMEOUT timeout; + NvBool keepPolling; + NvU32 regData, localLinkNumber; + localLinkNumber = linkId % NVSWITCH_LINKS_PER_MINION_LS10; + + if (NVSWITCH_IS_LINK_ENG_VALID_LS10(device, MINION, linkId) && + !nvswitch_is_minion_initialized(device, NVSWITCH_GET_LINK_ENG_INST(device, linkId, MINION))) + { + NVSWITCH_PRINT(device, ERROR, + "%s: MINION %d is not initialized for link %08x.\n", + __FUNCTION__, NVSWITCH_GET_LINK_ENG_INST(device, linkId, MINION), + linkId); + return -NVL_ERR_INVALID_STATE; + } + + // Query the DL status interface to get the data + NVSWITCH_MINION_LINK_WR32_LS10(device, linkId, _MINION, _NVLINK_DL_STAT(localLinkNumber), + DRF_NUM(_MINION, _NVLINK_DL_STAT, _ARGS, statusArgs) | + DRF_NUM(_MINION, _NVLINK_DL_STAT, _STATUSIDX, statusIdx)); + + if (IS_FMODEL(device) || IS_EMULATION(device) || IS_RTLSIM(device)) + { + nvswitch_timeout_create(20 * NVSWITCH_INTERVAL_1SEC_IN_NS, &timeout); + } + else + { + nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout); + } + + // Poll for READY bit to be set + do + { + keepPolling = (nvswitch_timeout_check(&timeout)) ? NV_FALSE : NV_TRUE; + + regData = NVSWITCH_MINION_LINK_RD32_LS10(device, linkId, _MINION, _NVLINK_DL_STAT(localLinkNumber)); + if (FLD_TEST_DRF_NUM(_MINION, _NVLINK_DL_STAT, _READY, 1, regData)) + { + *statusData = NVSWITCH_MINION_LINK_RD32_LS10(device, linkId, _MINION, _NVLINK_DL_STATDATA(localLinkNumber)); + return NVL_SUCCESS; + } + if (IS_FMODEL(device) || IS_RTLSIM(device)) + { + nvswitch_os_sleep(1); + } + } + while (keepPolling); + + NVSWITCH_PRINT(device, ERROR, + "%s: Timeout waiting for DL_STAT request to complete" + " NV_MINION_NVLINK_DL_STAT(%d) = 0x%08x\n", + __FUNCTION__, linkId, regData); + return -NVL_ERR_INVALID_STATE; +} + +/* + * @Brief : Send MINION DL CMD for a particular link + * + * @param[in] device Send command to MINION on this device + * @param[in] linkNumber DLCMD will be sent on this link number + * + * @return Returns true if the DLCMD passed + */ +NvlStatus +nvswitch_minion_send_command_ls10 +( + nvswitch_device *device, + NvU32 linkNumber, + NvU32 command, + NvU32 scratch0 +) +{ + NvU32 data = 0, localLinkNumber, statData = 0; + NvU32 ingressEccRegVal = 0, egressEccRegVal = 0; + NVSWITCH_TIMEOUT timeout; + NvBool keepPolling; + + localLinkNumber = linkNumber % NVSWITCH_LINKS_PER_MINION_LS10; + + if (NVSWITCH_IS_LINK_ENG_VALID_LS10(device, MINION, linkNumber) && + !nvswitch_is_minion_initialized(device, NVSWITCH_GET_LINK_ENG_INST(device, linkNumber, MINION))) + { + NVSWITCH_PRINT(device, ERROR, + "%s: MINION %d is not initialized for link %08x.\n", + __FUNCTION__, NVSWITCH_GET_LINK_ENG_INST(device, linkNumber, MINION), + linkNumber); + return NVL_SUCCESS; + } + + data = NVSWITCH_MINION_LINK_RD32_LS10(device, linkNumber, _MINION, _NVLINK_DL_CMD(localLinkNumber)); + if (FLD_TEST_DRF_NUM(_MINION, _NVLINK_DL_CMD, _FAULT, 1, data)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: MINION %d is in fault state. NV_MINION_NVLINK_DL_CMD(%d) = %08x\n", + __FUNCTION__, NVSWITCH_GET_LINK_ENG_INST(device, linkNumber, MINION), + linkNumber, data); + return -NVL_ERR_GENERIC; + } + + // Write to minion scratch if needed by command + switch (command) + { + case NV_MINION_NVLINK_DL_CMD_COMMAND_CONFIGEOM: + data = 0; + data = FLD_SET_DRF_NUM(_MINION, _MISC_0, _SCRATCH_SWRW_0, scratch0, data); + NVSWITCH_MINION_WR32_LS10(device, + NVSWITCH_GET_LINK_ENG_INST(device, linkNumber, MINION), _MINION, _MISC_0, data); + break; + case NV_MINION_NVLINK_DL_CMD_COMMAND_INITPHASE1: + // + // WAR bug 2708497 + // Before INITPHASE1, we must clear these values, then set back to + // _PROD after the call + // NV_INGRESS_ERR_ECC_CTRL_NCISOC_PARITY_ENABLE + // NV_EGRESS_ERR_ECC_CTRL_NCISOC_PARITY_ENABLE + // + + ingressEccRegVal = NVSWITCH_NPORT_RD32_LS10(device, linkNumber, _INGRESS, _ERR_ECC_CTRL); + NVSWITCH_NPORT_WR32_LS10(device, linkNumber, _INGRESS, _ERR_ECC_CTRL, + FLD_SET_DRF(_INGRESS, _ERR_ECC_CTRL, _NCISOC_PARITY_ENABLE, _DISABLE, ingressEccRegVal)); + + egressEccRegVal = NVSWITCH_NPORT_RD32_LS10(device, linkNumber, _EGRESS, _ERR_ECC_CTRL); + NVSWITCH_NPORT_WR32_LS10(device, linkNumber, _EGRESS, _ERR_ECC_CTRL, + FLD_SET_DRF(_EGRESS, _ERR_ECC_CTRL, _NCISOC_PARITY_ENABLE, _DISABLE, egressEccRegVal)); + break; + default: + break; + } + + data = FLD_SET_DRF_NUM(_MINION, _NVLINK_DL_CMD, _COMMAND, command, data); + data = FLD_SET_DRF_NUM(_MINION, _NVLINK_DL_CMD, _FAULT, 1, data); + NVSWITCH_MINION_LINK_WR32_LS10(device, linkNumber, _MINION, _NVLINK_DL_CMD(localLinkNumber), data); + + if (IS_FMODEL(device) || IS_EMULATION(device) || IS_RTLSIM(device)) + { + nvswitch_timeout_create(10 * NVSWITCH_INTERVAL_1SEC_IN_NS, &timeout); + } + else + { + nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout); + } + + // + // We will exit this if the command is successful OR + // if timeout waiting for the READY bit to be set OR + // if it generates a MINION FAULT + // + do + { + keepPolling = (nvswitch_timeout_check(&timeout)) ? NV_FALSE : NV_TRUE; + + data = NVSWITCH_MINION_LINK_RD32_LS10(device, linkNumber, _MINION, _NVLINK_DL_CMD(localLinkNumber)); + if (FLD_TEST_DRF_NUM(_MINION, _NVLINK_DL_CMD, _READY, 1, data)) + { + // The command has completed, success? + if (FLD_TEST_DRF_NUM(_MINION, _NVLINK_DL_CMD, _FAULT, 1, data)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: NVLink MINION command faulted!" + " NV_MINION_NVLINK_DL_CMD(%d) = 0x%08x\n", + __FUNCTION__, linkNumber, data); + + // Pull fault code and subcode + if (nvswitch_minion_get_dl_status(device, linkNumber, + NV_NVLSTAT_MN00, 0, &statData) == NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Minion DLCMD Fault code = 0x%x, Sub-code = 0x%x\n", + __FUNCTION__, + DRF_VAL(_NVLSTAT, _MN00, _LINK_INTR_CODE, statData), + DRF_VAL(_NVLSTAT, _MN00, _LINK_INTR_SUBCODE, statData)); + } + else + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to get code and subcode from DLSTAT, link %d\n", + __FUNCTION__, linkNumber); + } + + // Clear the fault and return + NVSWITCH_PRINT(device, ERROR, + "%s: Clearing NVLink MINION fault for link %d\n", + __FUNCTION__, linkNumber); + + data = FLD_SET_DRF_NUM(_MINION, _NVLINK_DL_CMD, _FAULT, 1, 0x0); + NVSWITCH_MINION_LINK_WR32_LS10(device, linkNumber, _MINION, _NVLINK_DL_CMD(localLinkNumber), data); + return -NVL_ERR_INVALID_STATE; + } + else + { + NVSWITCH_PRINT(device, SETUP, + "%s: NVLink MINION command %x was sent successfully for link %d\n", + __FUNCTION__, command, linkNumber); + break; + } + } + + nvswitch_os_sleep(1); + } + while (keepPolling); + + if (!FLD_TEST_DRF_NUM(_MINION, _NVLINK_DL_CMD, _READY, 1, data)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Timeout waiting for NVLink MINION command to complete!" + " NV_MINION_NVLINK_DL_CMD(%d) = 0x%08x\n", + __FUNCTION__, linkNumber, data); + return -NVL_ERR_INVALID_STATE; + } + + if (command == NV_MINION_NVLINK_DL_CMD_COMMAND_INITPHASE1) + { + NVSWITCH_NPORT_WR32_LS10(device, linkNumber, _INGRESS, _ERR_ECC_CTRL, ingressEccRegVal); + NVSWITCH_NPORT_WR32_LS10(device, linkNumber, _EGRESS, _ERR_ECC_CTRL, egressEccRegVal); + } + + return NVL_SUCCESS; +} + +/* + * @Brief : Bootstrap all MINIONs on the specified device + * + * @param[in] device Bootstrap MINIONs on this device + */ +NvlStatus +nvswitch_init_minion_ls10 +( + nvswitch_device *device +) +{ + NvlStatus status = NVL_SUCCESS; + + if (_nvswitch_check_running_minions(device)) + { + return NVL_SUCCESS; + } + + status = -NVL_INITIALIZATION_TOTAL_FAILURE; + + return status; +} + +NvlStatus +nvswitch_set_minion_initialized_ls10 +( + nvswitch_device *device, + NvU32 idx_minion, + NvBool initialized +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + + if (!NVSWITCH_ENG_VALID_LS10(device, MINION, idx_minion)) + { + return -NVL_BAD_ARGS; + } + + chip_device->engMINION[idx_minion].initialized = initialized; + return NVL_SUCCESS; +} + +NvBool +nvswitch_is_minion_initialized_ls10 +( + nvswitch_device *device, + NvU32 idx_minion +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + + if (!NVSWITCH_ENG_VALID_LS10(device, MINION, idx_minion)) + { + return NV_FALSE; + } + return (chip_device->engMINION[idx_minion].initialized != 0); +} + +NvlStatus +nvswitch_minion_set_sim_mode_ls10 +( + nvswitch_device *device, + nvlink_link *link +) +{ + NvlStatus status = NVL_SUCCESS; + NvU32 dlcmd; + NvU32 linkNumber = link->linkNumber; + NvU32 localLinkNumber = linkNumber % NVSWITCH_LINKS_PER_MINION_LS10; + + switch (device->regkeys.set_simmode) + { + case NV_SWITCH_REGKEY_MINION_SET_SIMMODE_FAST: + dlcmd = NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_FAST; + break; + case NV_SWITCH_REGKEY_MINION_SET_SIMMODE_MEDIUM: + dlcmd = NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_MEDIUM; + break; + case NV_SWITCH_REGKEY_MINION_SET_SIMMODE_SLOW: + dlcmd = NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_SLOW; + break; + default: + return NVL_SUCCESS; + } + + status = nvswitch_minion_send_command(device, linkNumber, dlcmd, 0); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: DLCMD 0x%x failed on link: %d\n", + __FUNCTION__, dlcmd, linkNumber); + return status; + } + + // Setting RXCAL_EN_ALARM timer value + NVSWITCH_MINION_LINK_WR32_LS10(device, linkNumber, _MINION, + _NVLINK_DL_CMD_DATA(localLinkNumber), + NV_MINION_DL_CMD_DATA_RXCAL_EN_ALARM); + + status = nvswitch_minion_send_command(device, linkNumber, + NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_RXCAL_EN_ALARM, 0); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: DLCMD DBG_SETSIMMODE_RXCAL_EN_ALARM failed on link: %d\n", + __FUNCTION__, linkNumber); + return status; + } + + // Setting INIT_CAL_DONE timer value + NVSWITCH_MINION_LINK_WR32_LS10(device, linkNumber, _MINION, + _NVLINK_DL_CMD_DATA(localLinkNumber), + NV_MINION_DL_CMD_DATA_INIT_CAL_DONE); + + status = nvswitch_minion_send_command(device, linkNumber, + NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_INIT_CAL_DONE, 0); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: DLCMD DBG_SETSIMMODE_INIT_CAL_DONE failed on link: %d\n", + __FUNCTION__, linkNumber); + return status; + } + + return status; +} + +NvlStatus +nvswitch_minion_set_smf_settings_ls10 +( + nvswitch_device *device, + nvlink_link *link +) +{ + NvlStatus status = NVL_SUCCESS; + NvU32 dlcmd; + NvU32 linkNumber = link->linkNumber; + + switch (device->regkeys.set_smf_settings) + { + case NV_SWITCH_REGKEY_MINION_SET_SMF_SETTINGS_SLOW: + dlcmd = NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_SMF_VALUES_SLOW; + break; + case NV_SWITCH_REGKEY_MINION_SET_SMF_SETTINGS_MEDIUM: + dlcmd = NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_SMF_VALUES_MEDIUM; + break; + case NV_SWITCH_REGKEY_MINION_SET_SMF_SETTINGS_FAST: + dlcmd = NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_SMF_VALUES_FAST; + break; + case NV_SWITCH_REGKEY_MINION_SET_SMF_SETTINGS_MEDIUM_SERIAL: + dlcmd = NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_SMF_VALUES_MEDIUM_SERIAL; + break; + default: + return NVL_SUCCESS; + } + + status = nvswitch_minion_send_command(device, linkNumber, dlcmd, 0); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: DLCMD 0x%x failed on link: %d\n", + __FUNCTION__, dlcmd, linkNumber); + return status; + } + + return status; +} + +NvlStatus +nvswitch_minion_select_uphy_tables_ls10 +( + nvswitch_device *device, + nvlink_link *link +) +{ + NvlStatus status = NVL_SUCCESS; + NvU32 dlcmd; + NvU32 linkNumber = link->linkNumber; + + switch (device->regkeys.select_uphy_tables) + { + case NV_SWITCH_REGKEY_MINION_SELECT_UPHY_TABLES_SHORT: + dlcmd = NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_UPHY_TABLES_SHORT; + break; + case NV_SWITCH_REGKEY_MINION_SELECT_UPHY_TABLES_FAST: + dlcmd = NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_SETSIMMODE_UPHY_TABLES_FAST; + break; + default: + return NVL_SUCCESS; + } + + status = nvswitch_minion_send_command(device, linkNumber, dlcmd, 0); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: DLCMD 0x%x failed on link: %d\n", + __FUNCTION__, dlcmd, linkNumber); + return status; + } + + return status; +} + + +NvlStatus +nvswitch_minion_get_rxdet_status_ls10 +( + nvswitch_device *device, + NvU32 linkId +) +{ + NvU32 statData; + NvlStatus status; + NVSWITCH_TIMEOUT timeout; + NvBool keepPolling; + + if (IS_FMODEL(device) || IS_EMULATION(device) || IS_RTLSIM(device)) + { + nvswitch_timeout_create(30*NVSWITCH_INTERVAL_1SEC_IN_NS, &timeout); + } + else + { + nvswitch_timeout_create(20 * NVSWITCH_INTERVAL_1MSEC_IN_NS, &timeout); + } + + // Poll for READY bit to be set + do + { + keepPolling = (nvswitch_timeout_check(&timeout)) ? NV_FALSE : NV_TRUE; + + // Check RXDET status on MINION DL STAT interface + status = nvswitch_minion_get_dl_status(device, linkId, NV_NVLSTAT_LNK2, 0, &statData); + if (status != NVL_SUCCESS) + { + return status; + } + + if (FLD_TEST_DRF(_NVLSTAT, _LNK2, _RXDET_LINK_STATUS, _FOUND, statData)) + { + NVSWITCH_PRINT(device, INFO, + "%s: RXDET LINK_STATUS = FOUND on link: %d\n", + __FUNCTION__, linkId); + + // Retrieve which lanes were found (should be all) + device->link[linkId].lane_rxdet_status_mask = + DRF_VAL(_NVLSTAT, _LNK2, _RXDET_LANE_STATUS, statData); + + // + // MINION doesn't have knowledge of lane reversal and therefore + // reports logical lanes. We must reverse the bitmask here if applicable + // since RM reports physical lanes. + // + if (nvswitch_link_lane_reversed_lr10(device, linkId)) + { + NVSWITCH_REVERSE_BITMASK_32(NVSWITCH_NUM_LANES_LS10, + device->link[linkId].lane_rxdet_status_mask); + } + + return NVL_SUCCESS; + } + + if (FLD_TEST_DRF(_NVLSTAT, _LNK2, _RXDET_LINK_STATUS, _TIMEOUT, statData)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: RXDET LINK_STATUS = TIMEOUT on link: %d\n", + __FUNCTION__, linkId); + + // Retrieve which lanes were found + device->link[linkId].lane_rxdet_status_mask = + DRF_VAL(_NVLSTAT, _LNK2, _RXDET_LANE_STATUS, statData); + + // + // MINION doesn't have knowledge of lane reversal and therefore + // reports logical lanes. We must reverse the bitmask here if applicable + // since RM reports physical lanes. + // + if (nvswitch_link_lane_reversed_lr10(device, linkId)) + { + NVSWITCH_REVERSE_BITMASK_32(NVSWITCH_NUM_LANES_LS10, + device->link[linkId].lane_rxdet_status_mask); + } + + return -NVL_ERR_INVALID_STATE; + } + + nvswitch_os_sleep(1); + } + while (keepPolling); + + NVSWITCH_PRINT(device, ERROR, + "%s: Timeout waiting for RXDET STATUS on link: %d\n", + __FUNCTION__, linkId); + + return -NVL_ERR_INVALID_STATE; +} + +/* + * @Brief : Check if the RISCV CPU has started + * + * @param[in] device The Nvswitch device + * @param[in] idx_minion MINION instance to use + */ +NvBool +nvswitch_minion_is_riscv_active_ls10 +( + nvswitch_device *device, + NvU32 idx_minion +) +{ + NvU32 val; + + val = NVSWITCH_MINION_RD32_LS10(device, idx_minion, _CMINION_RISCV, _CPUCTL); + + return FLD_TEST_DRF(_CMINION, _RISCV_CPUCTL, _ACTIVE_STAT, _ACTIVE, val); + +} + +NvlStatus +nvswitch_minion_clear_dl_error_counters_ls10 +( + nvswitch_device *device, + NvU32 linkId +) +{ + NvlStatus status; + + status = nvswitch_minion_send_command(device, linkId, + NV_MINION_NVLINK_DL_CMD_COMMAND_DLSTAT_CLR_DLERRCNT, 0); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s : Failed to clear error count to MINION for link # %d\n", + __FUNCTION__, linkId); + } + return status; +} + +NvlStatus +nvswitch_minion_send_inband_data_ls10 +( + nvswitch_device *device, + NvU32 linkId, + nvswitch_inband_send_data *inBandData +) +{ + NvlStatus status = NVL_SUCCESS; +#if defined(INCLUDE_NVLINK_LIB) + NvlStatus tempStatus = NVL_SUCCESS; + NvU32 localLinkNumber = linkId % NVSWITCH_LINKS_PER_MINION_LS10; + NvU8 *sendBuffer = inBandData->sendBuffer; + NvU32 bufferSize = inBandData->bufferSize; + NvU32 data = 0; + NvU32 regval = 0; + NvU32 statData = 0; + NVSWITCH_TIMEOUT timeout; + NvBool bKeepPolling = NV_TRUE; + + if (bufferSize == 0 || bufferSize > NVLINK_INBAND_MAX_XFER_SIZE) + { + NVSWITCH_PRINT(device, ERROR, "Bad Inband data size %d. Skipping Inband Send\n", bufferSize); + return -NVL_ERR_INVALID_STATE; + } + + // Buffer Size must be reduced by 1 as per the minion protocol + regval = DRF_NUM(_MINION, _INBAND_SEND_DATA, _BUFFER_SIZE, (bufferSize - 1)); + + regval |= DRF_NUM(_MINION, _INBAND_SEND_DATA, _FLAGS,inBandData->hdr.data); + + NVSWITCH_MINION_WR32_LS10(device, + NVSWITCH_GET_LINK_ENG_INST(device, linkId, MINION), + _MINION, _NVLINK_DL_CMD_DATA(localLinkNumber), + regval); + + status = nvswitch_minion_send_command(device, linkId, + NV_MINION_NVLINK_DL_CMD_COMMAND_WRITE_TX_BUFFER_START, 0); + + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "Link %d Inband Buffer transfer for TX_BUFFER_START failed\n", linkId); + return status; + } + + while (bufferSize != 0) + { + nvswitch_os_memcpy(&data, sendBuffer, NV_MIN(sizeof(data), bufferSize)); + + NVSWITCH_MINION_WR32_LS10(device, + NVSWITCH_GET_LINK_ENG_INST(device, linkId, MINION), + _MINION, _NVLINK_DL_CMD_DATA(localLinkNumber), + data); + + status = nvswitch_minion_send_command(device, linkId, + NV_MINION_NVLINK_DL_CMD_COMMAND_WRITE_TX_BUFFER_MIDDLE, 0); + + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "Link %d Inband Buffer transfer failed\n", linkId); + goto clear_buffer; + } + + bufferSize -= NV_MIN(sizeof(data), bufferSize); + sendBuffer += NV_MIN(sizeof(data), bufferSize); + } + + status = nvswitch_minion_send_command(device, linkId, + NV_MINION_NVLINK_DL_CMD_COMMAND_WRITE_TX_BUFFER_END, 0); + + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "Link %d Inband Buffer transfer for TX_BUFFER_END\n", linkId); + goto clear_buffer; + } + + // Wait for buffer complete or buffer fail + nvswitch_timeout_create(2 * NVSWITCH_INTERVAL_4SEC_IN_NS, &timeout); + do + { + bKeepPolling = !nvswitch_timeout_check(&timeout); + // DLSTAT need to explicitly checked + status = nvswitch_minion_get_dl_status(device, linkId, NV_NVLSTAT_UC01, 0, &statData); + + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, INFO,"%s : Failed to poll DLSTAT register for (%s):(%d)\n", + __FUNCTION__, device->name, linkId); + status = -NVL_ERR_INVALID_STATE; + goto clear_buffer; + } + + if (FLD_TEST_DRF(_NVLSTAT, _UC01, _INBAND_BUFFER_COMPLETE, _TRUE, statData)) + { + return NVL_SUCCESS; + } + + if (FLD_TEST_DRF(_NVLSTAT, _UC01, _INBAND_BUFFER_FAIL, _TRUE, statData)) + { + NVSWITCH_PRINT(device, ERROR, "Link %d Inband Buffer transfer BUFFER_FAILED\n", linkId); + status = -NVL_ERR_INVALID_STATE; + goto clear_buffer; + } + // + // Consider a case where both FM and RM trying to write on the same NVLink at the same time. + // Both are waiting on each other to read the buffer, but they have also blocked the ISR, + // as while waiting they hold the device lock. Thus, it is necessary to unblock one of them. + // And to do that we have service BUFFER_AVAILABLE while waiting. + // + nvswitch_service_minion_all_links_ls10(device); + + nvswitch_os_sleep(10); + + } while (bKeepPolling); + + NVSWITCH_PRINT(device, ERROR, "Link %d Inband Neither got BUFFER_FAIL nor BUFFER_COMPLETE\n", linkId); + +clear_buffer: + tempStatus = nvswitch_minion_send_command(device, linkId, + NV_MINION_NVLINK_DL_CMD_COMMAND_CLEAR_TX_BUFFER, + 0); + if (tempStatus != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "Link %d Inband Buffer transfer for TX_BUFFER_CLEAR\n", linkId); + return status; + } + + // Check if we received BUFFER_COMPLETE is seen while doing a BUFFER_CLEAR + tempStatus = nvswitch_minion_get_dl_status(device, linkId, NV_NVLSTAT_UC01, 0, &statData); + + if (tempStatus != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, INFO,"%s : Failed to poll DLSTAT register for (%s):(%d)\n", + __FUNCTION__, device->name, linkId); + return status; + } + + if (FLD_TEST_DRF(_NVLSTAT, _UC01, _INBAND_BUFFER_COMPLETE, _TRUE, statData)) + { + status = NVL_SUCCESS; + } + else + { + status = bKeepPolling ? status: -NVL_ERR_STATE_IN_USE; + } +#endif + return status; +} + +void +nvswitch_minion_receive_inband_data_ls10 +( + nvswitch_device *device, + NvU32 linkId +) +{ + NvlStatus status = NVL_SUCCESS; +#if defined(INCLUDE_NVLINK_LIB) + NvlStatus tempStatus = NVL_SUCCESS; + NvU32 numEntries = 0; + NvU32 i; + NvU32 localLinkNumber = linkId % NVSWITCH_LINKS_PER_MINION_LS10; + NvU8 *receiveBuffer; + NvU32 regVal, dataSize, remainingBuffer, bytesToXfer; + nvlink_inband_drv_hdr_t hdr; + + status = nvswitch_minion_send_command(device, linkId, + NV_MINION_NVLINK_DL_CMD_COMMAND_READ_RX_BUFFER_START, + 0); + if (status != NV_OK) + goto cleanup; + + regVal = NVSWITCH_MINION_RD32_LS10(device, + NVSWITCH_GET_LINK_ENG_INST(device, linkId, MINION), + _MINION, _NVLINK_DL_CMD_DATA(localLinkNumber)); + + // Add 1 to the data as per minion protocol + dataSize = DRF_VAL(_MINION, _INBAND_SEND_DATA, _BUFFER_SIZE, regVal) + 1; + hdr.data = DRF_VAL(_MINION, _INBAND_SEND_DATA, _FLAGS, regVal); + numEntries = NV_ALIGN_UP(dataSize, NVLINK_INBAND_MAX_XFER_AT_ONCE)/ + NVLINK_INBAND_MAX_XFER_AT_ONCE; + remainingBuffer = dataSize; + + if ((hdr.data & (NVLINK_INBAND_DRV_HDR_TYPE_START | + NVLINK_INBAND_DRV_HDR_TYPE_MID | + NVLINK_INBAND_DRV_HDR_TYPE_END)) == 0) + { + NVSWITCH_PRINT(device, ERROR, "InBand: HDR is wrong\n"); + goto cleanup; + } + + if (hdr.data & NVLINK_INBAND_DRV_HDR_TYPE_START) + { + if (device->link[linkId].inbandData.message != NULL) + { + NVSWITCH_PRINT(device, ERROR, "InBand: Got TYPE_START for existing data\n"); + NVSWITCH_ASSERT(0); + goto cleanup; + } + + device->link[linkId].inbandData.message = + nvswitch_os_malloc(sizeof(nvswitch_inband_data_list)); + if (device->link[linkId].inbandData.message == NULL) + { + status = -NVL_NO_MEM; + goto cleanup; + } + + device->link[linkId].inbandData.message->dataSize = 0; + } + + if (device->link[linkId].inbandData.message == NULL) + { + NVSWITCH_PRINT(device, ERROR, "InBand: Data being sent without _START\n"); + goto cleanup; + } + + receiveBuffer = device->link[linkId].inbandData.message->data; + + receiveBuffer += device->link[linkId].inbandData.message->dataSize; + + if (((dataSize + device->link[linkId].inbandData.message->dataSize) > + NVSWITCH_INBAND_DATA_SIZE) || + (dataSize > NVLINK_INBAND_MAX_XFER_SIZE) || + (dataSize == 0)) + { + NVSWITCH_PRINT(device, ERROR, "InBand: Msg is of wrong Size :DataSize = %d Msg Size= %d\n", + dataSize, device->link[linkId].inbandData.message->dataSize); + NVSWITCH_ASSERT(0); + goto cleanup; + } + + for (i = 0; i < numEntries; i++) + { + status = nvswitch_minion_send_command(device, linkId, + NV_MINION_NVLINK_DL_CMD_COMMAND_READ_RX_BUFFER_MIDDLE, 0); + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, "Link %d Inband Buffer receive" + "for entry %d failed\n", linkId, i); + goto cleanup; + } + + regVal = NVSWITCH_MINION_RD32_LS10(device, + NVSWITCH_GET_LINK_ENG_INST(device, linkId, MINION), + _MINION, _NVLINK_DL_CMD_DATA(localLinkNumber)); + + bytesToXfer = NV_MIN(remainingBuffer, NVLINK_INBAND_MAX_XFER_AT_ONCE); + + nvswitch_os_memcpy(receiveBuffer, ®Val, bytesToXfer); + + receiveBuffer += bytesToXfer; + remainingBuffer -= bytesToXfer; + } + + status = nvswitch_minion_send_command(device, linkId, + NV_MINION_NVLINK_DL_CMD_COMMAND_READ_RX_BUFFER_END, 0); + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, "Link %d Inband Buffer receive" + "for entry %d failed\n", linkId, numEntries); + goto cleanup; + } + + device->link[linkId].inbandData.message->dataSize += dataSize; + + if (hdr.data & NVLINK_INBAND_DRV_HDR_TYPE_END) + { + nvswitch_filter_messages(device, linkId); + } + + return; + +cleanup: + tempStatus = nvswitch_minion_send_command(device, linkId, + NV_MINION_NVLINK_DL_CMD_COMMAND_CLEAR_RX_BUFFER, + 0); + if (tempStatus != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "Link %d Inband Buffer transfer for RX_BUFFER_CLEAR\n", linkId); + return; + } + if (device->link[linkId].inbandData.message != NULL) + { + nvswitch_os_free(device->link[linkId].inbandData.message); + device->link[linkId].inbandData.message = NULL; + } + //TODO: Check if we need to send a failure msg to client? +#endif +} + +NvlStatus +nvswitch_minion_get_ali_debug_registers_ls10 +( + nvswitch_device *device, + nvlink_link *link, + NVSWITCH_MINION_ALI_DEBUG_REGISTERS *params +) +{ + NvU32 localLinkNumber = link->linkNumber % NVSWITCH_LINKS_PER_MINION_LS10; + if (!nvswitch_minion_get_dl_status(device, link->linkNumber, + NV_NVLSTAT_MN00, 0, &(params->dlstatMn00)) == NVL_SUCCESS) + { + NVSWITCH_PRINT(device, INFO,"%s : Failed to poll DLSTAT _MN00 register for (%s):(%d)\n", + __FUNCTION__, device->name, link->linkNumber); + } + + if (!nvswitch_minion_get_dl_status(device, link->linkNumber, NV_NVLSTAT_UC01, 0, &(params->dlstatUc01))) + { + NVSWITCH_PRINT(device, INFO,"%s : Failed to poll DLSTAT UC01 register for (%s):(%d)\n", + __FUNCTION__, device->name, link->linkNumber); + } + + params->dlstatLinkIntr = NVSWITCH_MINION_LINK_RD32_LS10(device, link->linkNumber, + _MINION, _NVLINK_LINK_INTR(localLinkNumber)); + + return NVL_SUCCESS; +} + diff --git a/src/common/nvswitch/kernel/ls10/multicast_ls10.c b/src/common/nvswitch/kernel/ls10/multicast_ls10.c new file mode 100644 index 000000000..faec64e03 --- /dev/null +++ b/src/common/nvswitch/kernel/ls10/multicast_ls10.c @@ -0,0 +1,1844 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "common_nvswitch.h" +#include "ls10/ls10.h" +#include "ls10/multicast_ls10.h" + +#include "nvswitch/ls10/dev_route_ip.h" + +// Source: IAS Table 44. Laguna NXbar TileCol Port Mapping +static const NVSWITCH_COLUMN_PORT_OFFSET_LS10 nvswitch_portmap_ls10[NVSWITCH_NUM_LINKS_LS10] = { + // ports 0 - 10 + { 0, 0 }, { 0, 1 }, { 0, 2 }, { 0, 3 }, + { 0, 4 }, { 0, 5 }, { 0, 6 }, { 0, 7 }, + { 0, 8 }, { 0, 9 }, { 0, 10 }, + // ports 11 - 16 + { 2, 0 }, { 2, 3 }, { 2, 4 }, { 2, 5 }, + { 2, 8 }, + //ports 16 - 26 + { 4, 10 }, { 4, 9 }, { 4, 8 }, { 4, 7 }, + { 4, 6 }, { 4, 5 }, { 4, 4 }, { 4, 3 }, + { 4, 2 }, { 4, 1 }, { 4, 0 }, + // ports 27 - 31 + { 2, 9 }, { 2, 7 }, { 2, 6 }, { 2, 2 }, + { 2, 1 }, + // ports 32 - 42 + { 1, 0 }, { 1, 1 }, { 1, 2 }, { 1, 3 }, + { 1, 4 }, { 1, 5 }, { 1, 6 }, { 1, 7 }, + { 1, 8 }, { 1, 9 }, { 1, 10 }, + // ports 43 - 47 + { 3, 0 }, { 3, 3 }, { 3, 4 }, { 3, 5 }, + { 3, 8 }, + // ports 48 - 58 + { 5, 10 }, { 5, 9 }, { 5, 8 }, { 5, 7 }, + { 5, 6 }, { 5, 5 }, { 5, 4 }, { 5, 3 }, + { 5, 2 }, { 5, 1 }, { 5, 0 }, + // ports 59 - 63 + { 3, 9 }, { 3, 7 }, { 3, 6 }, { 3, 2 }, + { 3, 1 } +}; + +static NvlStatus +_nvswitch_get_column_port_offset_ls10 +( + NvU32 port, + NVSWITCH_COLUMN_PORT_OFFSET_LS10 *column_port_offset +) +{ + if (port >= NVSWITCH_NUM_LINKS_LS10) + return -NVL_BAD_ARGS; + + *column_port_offset = nvswitch_portmap_ls10[port]; + + return NVL_SUCCESS; +} + +#if defined(NVSWITCH_MC_TRACE) +static void +_nvswitch_mc_print_directive +( + nvswitch_device *device, + NVSWITCH_TCP_DIRECTIVE_LS10 *mc_directive +) +{ + if (!mc_directive) + { + NVSWITCH_PRINT(device, ERROR, "%s: null directive pointer\n", __FUNCTION__); + return; + } + + NVSWITCH_PRINT(device, INFO, "TCP: %4d ", mc_directive->tcp); + + // pretty-print null ports + if (mc_directive->tcpEPort == NVSWITCH_MC_NULL_PORT_LS10) + { + NVSWITCH_PRINT(device, INFO, "EPort: X OPort: %4d", + mc_directive->tcpOPort); + } + else if (mc_directive->tcpOPort == NVSWITCH_MC_NULL_PORT_LS10) + { + NVSWITCH_PRINT(device, INFO, "EPort: %4d OPort: X", + mc_directive->tcpEPort); + } + else + { + NVSWITCH_PRINT(device, INFO, "EPort: %4d OPort: %4d", + mc_directive->tcpEPort, + mc_directive->tcpOPort); + } + + NVSWITCH_PRINT(device, INFO, "EAltPath: %4d OAltPath: %4d", + mc_directive->tcpEAltPath, + mc_directive->tcpOAltPath); + NVSWITCH_PRINT(device, INFO, "EVCHop: %4d OVCHop: %4d", + mc_directive->tcpEVCHop, + mc_directive->tcpOVCHop); + NVSWITCH_PRINT(device, INFO, "portFlag: %4d continueRound: %4d lastRound: %4d ", + mc_directive->portFlag, + mc_directive->continueRound, + mc_directive->lastRound); + NVSWITCH_PRINT(device, INFO, "\n"); +} + +static void +_nvswitch_mc_print_directives +( + nvswitch_device *device, + NVSWITCH_TCP_DIRECTIVE_LS10 *mcp_list, + NvU32 entries_used, + NvU8 *spray_group_ptrs, + NvU32 num_spray_groups +) +{ + NvU32 i, spray_group_offset, round, spray_group_idx, cur_entry_idx, entries_printed; + NvBool spray_group_done = NV_FALSE; + + if (num_spray_groups == 0) + { + NVSWITCH_PRINT(device, ERROR, "%s: No spray groups specified\n", __FUNCTION__); + return; + } + + if (num_spray_groups > NVSWITCH_MC_MAX_SPRAY_LS10) + { + NVSWITCH_PRINT(device, ERROR, "%s: Too many spray groups specified: %d\n", + __FUNCTION__, num_spray_groups); + return; + } + + if (entries_used > NVSWITCH_MC_TCP_LIST_SIZE_LS10) + { + NVSWITCH_PRINT(device, ERROR, "%s: Too many entries specified: %d\n", + __FUNCTION__, entries_used); + return; + } + + + NVSWITCH_PRINT(device, INFO, "Total spray groups %d\n", num_spray_groups); + + entries_printed = 0; + + // loop through spray groups + for (spray_group_idx = 0; spray_group_idx < num_spray_groups; spray_group_idx++) + { + spray_group_done = NV_FALSE; + spray_group_offset = spray_group_ptrs[spray_group_idx]; + cur_entry_idx = spray_group_offset; + round = 0; + + NVSWITCH_PRINT(device, INFO, "Spray group %d offset %d\n", spray_group_idx, + spray_group_offset); + + while (!spray_group_done) + { + if (entries_printed >= NVSWITCH_MC_TCP_LIST_SIZE_LS10) + { + NVSWITCH_PRINT(device, ERROR, "%s: Overflow of mcplist. Entries printed: %d\n", + __FUNCTION__, entries_printed); + return; + } + + NVSWITCH_PRINT(device, INFO, "Round %d, First mc_plist Index %d round size %d\n", + round, cur_entry_idx, mcp_list[cur_entry_idx].roundSize); + + for (i = 0; i < mcp_list[cur_entry_idx].roundSize; i++) + { + if ((i + cur_entry_idx) > NVSWITCH_MC_TCP_LIST_SIZE_LS10) + { + NVSWITCH_PRINT(device, ERROR, "%s: Overflow of mcplist. %d\n", + __FUNCTION__, i + cur_entry_idx); + } + + _nvswitch_mc_print_directive(device, &mcp_list[i + cur_entry_idx]); + entries_printed++; + + if (mcp_list[i + cur_entry_idx].lastRound) + { + NVSWITCH_PRINT(device, INFO, "Last round of spray group found at offset %d\n", + i + cur_entry_idx); + spray_group_done = NV_TRUE; + } + } + + round++; + cur_entry_idx += i; + } + + } +} +#endif // defined(NVSWITCH_MC_TRACE) + +// +// Build column-port bitmap. Each 32-bit portmap in the array represents a column. +// Each bit set in the portmap represents the column-relative port offset. +// +static NvlStatus +_nvswitch_mc_build_cpb +( + nvswitch_device *device, + NvU32 num_ports, + NvU32 *spray_group, + NvU32 num_columns, + NvU32 *cpb, + NvU8 *vchop_array_sg, + NvU8 vchop_map[NVSWITCH_MC_NUM_COLUMNS_LS10][NVSWITCH_MC_PORTS_PER_COLUMN_LS10] +) +{ + NvU32 i, ret; + NVSWITCH_COLUMN_PORT_OFFSET_LS10 cpo; + + if ((spray_group == NULL) || (cpb == NULL) || (num_ports == 0) || + (num_ports > NVSWITCH_NUM_LINKS_LS10)) + { + NVSWITCH_PRINT(device, ERROR, "%s: invalid arguments\n", __FUNCTION__); + return -NVL_BAD_ARGS; + } + + nvswitch_os_memset(cpb, 0, sizeof(*cpb) * num_columns); + nvswitch_os_memset(vchop_map, 0, sizeof(NvU8) * + NVSWITCH_MC_NUM_COLUMNS_LS10 * NVSWITCH_MC_PORTS_PER_COLUMN_LS10); + + for (i = 0; i < num_ports; i++) + { + ret = _nvswitch_get_column_port_offset_ls10(spray_group[i], &cpo); + if (ret != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: error getting column-port offset\n", __FUNCTION__); + return ret; + } + + if (nvswitch_test_flags(cpb[cpo.column], NVBIT(cpo.port_offset))) + { + NVSWITCH_PRINT(device, ERROR, "%s: duplicate port specified: %d\n", __FUNCTION__, + spray_group[i]); + return -NVL_BAD_ARGS; + } + + nvswitch_set_flags(&cpb[cpo.column], NVBIT(cpo.port_offset)); + + if (vchop_array_sg[i] > NVSWITCH_MC_VCHOP_FORCE1) + { + NVSWITCH_PRINT(device, ERROR, "%s: vchop value out of range: %d\n", __FUNCTION__, + vchop_array_sg[i]); + return -NVL_BAD_ARGS; + } + + + vchop_map[cpo.column][cpo.port_offset] = vchop_array_sg[i]; + } + + return NVL_SUCCESS; +} + +// +// Determine whether the given column/offset pair matches the given absolute +// primary_replica port number. +// +static NvBool +_is_primary_replica +( + NvU32 col, + NvU32 offset, + NvU32 primary_replica +) +{ + NVSWITCH_COLUMN_PORT_OFFSET_LS10 cpo; + + if (primary_replica == NVSWITCH_MC_INVALID) + return NV_FALSE; + + if (_nvswitch_get_column_port_offset_ls10(primary_replica, &cpo) != NVL_SUCCESS) + return NV_FALSE; + + if ((cpo.column == col) && (cpo.port_offset == offset)) + return NV_TRUE; + + return NV_FALSE; +} + +// +// This function compacts the directive list and updates port_list_size +// +static NvlStatus +_nvswitch_mc_compact_portlist +( + nvswitch_device *device, + NVSWITCH_TCP_DIRECTIVE_LS10 *port_list, + NvU32 *port_list_size +) +{ + NvU32 cur_portlist_pos, new_portlist_pos; + NVSWITCH_TCP_DIRECTIVE_LS10 *cur_dir, *old_list; + + if (port_list_size == NULL) + { + NVSWITCH_PRINT(device, ERROR, "%s: port list size ptr is null\n", __FUNCTION__); + return -NVL_BAD_ARGS; + } + + if ((port_list == NULL) || (*port_list_size == 0)) + return NVL_SUCCESS; + + if ((*port_list_size) > NVSWITCH_MC_TCP_LIST_SIZE_LS10) + { + NVSWITCH_PRINT(device, ERROR, "%s: port list size out of range\n", __FUNCTION__); + return -NVL_BAD_ARGS; + } + +#ifdef NVSWITCH_MC_DEBUG + NVSWITCH_PRINT(device, INFO, "%s: old size: %d\n", __FUNCTION__, *port_list_size); +#endif + + // create temporary directive list + old_list = nvswitch_os_malloc(sizeof(NVSWITCH_TCP_DIRECTIVE_LS10) * (*port_list_size)); + + if (!old_list) + { + NVSWITCH_PRINT(device, ERROR, "%s: error allocating temporary portlist\n", __FUNCTION__); + return -NVL_NO_MEM; + } + + nvswitch_os_memcpy(old_list, port_list, sizeof(NVSWITCH_TCP_DIRECTIVE_LS10) * (*port_list_size)); + + // rebuild list using only valid entries + new_portlist_pos = 0; + + for (cur_portlist_pos = 0; cur_portlist_pos < (*port_list_size); cur_portlist_pos++) + { + cur_dir = &old_list[cur_portlist_pos]; + + if (cur_dir->tcp != NVSWITCH_MC_INVALID) + { +#ifdef NVSWITCH_MC_TRACE + NVSWITCH_PRINT(device, INFO, "%s: valid directive:\n", __FUNCTION__); + _nvswitch_mc_print_directive(device, &old_list[cur_portlist_pos]); +#endif + nvswitch_os_memcpy(&port_list[new_portlist_pos], &old_list[cur_portlist_pos], + sizeof(NVSWITCH_TCP_DIRECTIVE_LS10)); + new_portlist_pos++; + } + } + + nvswitch_os_free(old_list); + +#ifdef NVSWITCH_MC_DEBUG + NVSWITCH_PRINT(device, INFO, "%s: new size: %d\n", __FUNCTION__, new_portlist_pos); +#endif + + *port_list_size = new_portlist_pos; + + return NVL_SUCCESS; +} + +// +// Set the round flags to indicate the size of each multicast round. +// See IAS section "6.12. Consistent MC Semantics" for more info. +// +static void +_nvswitch_mc_set_round_flags +( + NVSWITCH_TCP_DIRECTIVE_LS10 *port_list, + NvU32 port_list_size +) +{ + NvU32 cur_portlist_pos, round_size, round_start, round_end; + NVSWITCH_TCP_DIRECTIVE_LS10 *cur_dir, *next_dir; + + if ((port_list == NULL) || (port_list_size == 0)) + return; + + round_start = 0; + round_end = 0; + + for (cur_portlist_pos = 0; cur_portlist_pos < port_list_size; cur_portlist_pos++) + { + cur_dir = &port_list[cur_portlist_pos]; + + // special case: last element: end of round and last round + if (cur_portlist_pos == port_list_size - 1) + { + cur_dir->continueRound = NV_FALSE; + cur_dir->lastRound = NV_TRUE; + + round_end = cur_portlist_pos; + round_size = round_end - round_start + 1; + + // set the round size in the first directive + cur_dir = &port_list[round_start]; + cur_dir->roundSize = (NvU8)round_size; + } + else + { + // if next tcp is less than or equal to the current, then current is end of round + next_dir = &port_list[cur_portlist_pos + 1]; + if (next_dir->tcp <= cur_dir->tcp) + { + cur_dir->continueRound = NV_FALSE; + + round_end = cur_portlist_pos; + round_size = round_end - round_start + 1; + + // set the round size in the first directive + cur_dir = &port_list[round_start]; + cur_dir->roundSize = (NvU8)round_size; + + // advance round_start + round_start = cur_portlist_pos + 1; + } + } + } +} + +// +// Set the port flags to indicate primary replica port location. +// See IAS section "6.12. Consistent MC Semantics" for more info. +// +static void +_nvswitch_mc_set_port_flags +( + NVSWITCH_TCP_DIRECTIVE_LS10 *port_list, + NvU32 port_list_size +) +{ + NvU32 cur_portlist_pos; + NVSWITCH_TCP_DIRECTIVE_LS10 *cur_dir, *next_dir; + + if ((port_list == NULL) || (port_list_size == 0)) + return; + + for (cur_portlist_pos = 0; cur_portlist_pos < port_list_size; cur_portlist_pos++) + { + cur_dir = &port_list[cur_portlist_pos]; + + if (cur_dir->primaryReplica != PRIMARY_REPLICA_NONE) + { + if (cur_dir->lastRound) + { + cur_dir->continueRound = NV_TRUE; + + if (cur_dir->primaryReplica == PRIMARY_REPLICA_EVEN) + cur_dir->portFlag = 0; + if (cur_dir->primaryReplica == PRIMARY_REPLICA_ODD) + cur_dir->portFlag = 1; + } + else + { + // primary replica is in this directive, next directive specifies even or odd + cur_dir->portFlag = 1; + + if (cur_portlist_pos + 1 >= port_list_size) + { + NVSWITCH_ASSERT(0); + return; + } + + next_dir = &port_list[cur_portlist_pos + 1]; + + if (cur_dir->primaryReplica == PRIMARY_REPLICA_EVEN) + next_dir->portFlag = 0; + if (cur_dir->primaryReplica == PRIMARY_REPLICA_ODD) + next_dir->portFlag = 1; + } + } + } +} + +// +// This function "pops" the next port offset from the portlist bitmap. +// +static NV_INLINE NvU8 +_nvswitch_mc_get_next_port +( + NvU32 *portmap +) +{ + NvU32 port; + + if (!portmap) + { + NVSWITCH_ASSERT(0); + return NVSWITCH_MC_NULL_PORT_LS10; + } + + // + // We have to do some gymnastics here because LOWESTBITIDX_32 is + // destructive on the input variable, and the result is not assignable. + // + port = *portmap; + LOWESTBITIDX_32(port); + nvswitch_clear_flags(portmap, NVBIT(port)); + + if (port >= NVSWITCH_MC_PORTS_PER_COLUMN_LS10) + { + NVSWITCH_ASSERT(0); + return NVSWITCH_MC_NULL_PORT_LS10; + } + + return (NvU8)port; +} + +// +// This helper function generates a map of directive list offsets indexed by tile/column pair +// port offsets. This is used during construction of the directive list to point to where each +// newly constructed directive will be placed in the list. This process has to account for the +// fact that the middle two columns contain 10 ports each, while the rest have 11, all mapping +// into a 32-entry directive list. +// +static NV_INLINE void +_nvswitch_mc_build_mcplist_position_map +( + NvU32 port_offsets_by_tcp[NVSWITCH_MC_NUM_COLUMN_PAIRS_LS10][NVSWITCH_MC_PORTS_PER_COLUMN_LS10] +) +{ + NvU32 i, j, tcp; + + if (!port_offsets_by_tcp) + { + NVSWITCH_ASSERT(0); + return; + } + + for (tcp = 0; tcp < NVSWITCH_MC_NUM_COLUMN_PAIRS_LS10; tcp++) + { + if (tcp == 0) + { + j = 0; + for (i = 0; i < NVSWITCH_MC_PORTS_PER_COLUMN_LS10; i++) + { + port_offsets_by_tcp[tcp][i] = j; + j += NVSWITCH_MC_NUM_COLUMN_PAIRS_LS10; + } + } + + if (tcp == 1) + { + j = 1; + for (i = 0; i < NVSWITCH_MC_PORTS_PER_COLUMN_LS10 - 1; i++) + { + port_offsets_by_tcp[tcp][i] = j; + j += NVSWITCH_MC_NUM_COLUMN_PAIRS_LS10; + } + } + + if (tcp == 2) + { + j = 2; + for (i = 0; i < NVSWITCH_MC_PORTS_PER_COLUMN_LS10; i++) + { + port_offsets_by_tcp[tcp][i] = (j == NVSWITCH_MC_TCP_LIST_SIZE_LS10) ? + (NVSWITCH_MC_TCP_LIST_SIZE_LS10 - 1) : j; + j += NVSWITCH_MC_NUM_COLUMN_PAIRS_LS10; + } + } + } +} + +// +// Wrapper for the NUMSETBITS_32 macro, which is destructive on input. +// +static NV_INLINE NvU32 +_nvswitch_mc_get_pop_count +( + NvU32 i +) +{ + NvU32 tmp = i; + + NUMSETBITS_32(tmp); + + return tmp; +} + +// +// Build a list of TCP directives. This is the main conversion function which is used to build a +// TCP directive list for each spray group from a given column/port bitmap. +// +// @param device [in] pointer to the nvswitch device struct +// @param cpb [in] pointer to the column/port bitmap used to build directive list +// @param primary_replica [in] the primary replica port for this spray group, if specified +// @param vchop_map [in] array containing per-port vchop values in column/port format +// @param port_list [out] array where the newly built directive list is written +// @param entries_used [out] pointer to an int where the size of resulting list is written +// +static NvlStatus +_nvswitch_mc_build_portlist +( + nvswitch_device *device, + NvU32 *cpb, + NvU32 primary_replica, + NvU8 vchop_map[NVSWITCH_MC_NUM_COLUMNS_LS10][NVSWITCH_MC_PORTS_PER_COLUMN_LS10], + NVSWITCH_TCP_DIRECTIVE_LS10 *port_list, + NvU32 *entries_used +) +{ + NvU32 ecol_idx, ocol_idx, ecol_portcount, ocol_portcount, ecol_portmap, ocol_portmap; + NvU32 cur_portlist_pos, j, cur_portlist_slot, last_portlist_pos; + NvU8 cur_eport, cur_oport, i; + NvS32 extra_ports; + NvU32 port_offsets_by_tcp[NVSWITCH_MC_NUM_COLUMN_PAIRS_LS10][NVSWITCH_MC_PORTS_PER_COLUMN_LS10]; + NVSWITCH_TCP_DIRECTIVE_LS10 *cur_dir; + + if ((cpb == NULL) || (port_list == NULL)) + { + NVSWITCH_PRINT(device, ERROR, "%s: Invalid arguments\n", __FUNCTION__); + return -NVL_BAD_ARGS; + } + + _nvswitch_mc_build_mcplist_position_map(port_offsets_by_tcp); + + // + // process columns pairwise. if one column is larger than the other by 2 or more entries, + // set the port as alt path + // + + cur_portlist_pos = 0; + last_portlist_pos = 0; + cur_portlist_slot = 0; + + for ( i = 0; i < NVSWITCH_MC_NUM_COLUMN_PAIRS_LS10; i++ ) + { + ecol_idx = 2 * i; + ocol_idx = 2 * i + 1; + + ecol_portmap = cpb[ecol_idx]; + ocol_portmap = cpb[ocol_idx]; + + ecol_portcount = _nvswitch_mc_get_pop_count(ecol_portmap); + ocol_portcount = _nvswitch_mc_get_pop_count(ocol_portmap); + + extra_ports = ecol_portcount - ocol_portcount; + + // Start current portlist position on column offset of the current column + cur_portlist_slot = 0; + cur_portlist_pos = port_offsets_by_tcp[i][cur_portlist_slot]; + + if ( extra_ports >= 0 ) + { + // + // even column has more ports or both columns have an equal number + // iterate on odd column port count to go through both columns + // + for (j = 0; j < ocol_portcount; j++, cur_portlist_slot++) + { + cur_eport = _nvswitch_mc_get_next_port(&ecol_portmap); + cur_oport = _nvswitch_mc_get_next_port(&ocol_portmap); + if ((cur_eport == NVSWITCH_MC_NULL_PORT_LS10) || + (cur_oport == NVSWITCH_MC_NULL_PORT_LS10)) + { + return -NVL_ERR_GENERIC; + } + + // assign the ports to the current directive + cur_portlist_pos = port_offsets_by_tcp[i][cur_portlist_slot]; + cur_dir = &port_list[cur_portlist_pos]; + cur_dir->tcpEPort = cur_eport; + cur_dir->tcpOPort = cur_oport; + + cur_dir->tcpEVCHop = vchop_map[ecol_idx][cur_eport]; + cur_dir->tcpOVCHop = vchop_map[ocol_idx][cur_oport]; + + cur_dir->tcp = i; + +#ifdef NVSWITCH_MC_TRACE + NVSWITCH_PRINT(device, INFO, "%s: tcp: %d, extra: %d, cur_eport: %d, cur_oport %d\n", + __FUNCTION__, i, extra_ports, cur_eport, cur_oport); + NVSWITCH_PRINT(device, INFO, "%s: cur_portlist_pos: %d\n", __FUNCTION__, + cur_portlist_pos); +#endif + // set primary replica + if (_is_primary_replica(ocol_idx, cur_oport, primary_replica)) + cur_dir->primaryReplica = PRIMARY_REPLICA_ODD; + + if (_is_primary_replica(ecol_idx, cur_eport, primary_replica)) + cur_dir->primaryReplica = PRIMARY_REPLICA_EVEN; + + } + + // if both columns had the same number of ports, move on to the next column pair + if (!extra_ports) + { + last_portlist_pos = NV_MAX(last_portlist_pos, cur_portlist_pos); + continue; + } + + // + // otherwise, handle remaining ports in even column + // for the first extra port, assign it directly + // cur_portlist_slot is incremented by the last iteration, or 0 + // + cur_eport = _nvswitch_mc_get_next_port(&ecol_portmap); + if (cur_eport == NVSWITCH_MC_NULL_PORT_LS10) + { + return -NVL_ERR_GENERIC; + } + + cur_portlist_pos = port_offsets_by_tcp[i][cur_portlist_slot]; + cur_dir = &port_list[cur_portlist_pos]; + cur_dir->tcpEPort = cur_eport; + + cur_dir->tcpEVCHop = vchop_map[ecol_idx][cur_eport]; + + cur_dir->tcp = i; + +#ifdef NVSWITCH_MC_TRACE + NVSWITCH_PRINT(device, INFO, "%s: tcp: %d, extra: %d, cur_eport: %d\n", + __FUNCTION__, i, extra_ports, cur_eport); + NVSWITCH_PRINT(device, INFO, "%s: cur_portlist_pos: %d\n", __FUNCTION__, + cur_portlist_pos); +#endif + + // if this is the primary replica port, mark it + if (_is_primary_replica(ecol_idx, cur_eport, primary_replica)) + cur_dir->primaryReplica = PRIMARY_REPLICA_EVEN; + + extra_ports--; + + // if there are more, assign to altpath + while (extra_ports) + { + // get next port from even column + cur_eport = _nvswitch_mc_get_next_port(&ecol_portmap); + if (cur_eport == NVSWITCH_MC_NULL_PORT_LS10) + { + return -NVL_ERR_GENERIC; + } + + // assign it to odd port in current directive (altpath) + cur_dir->tcpOPort = cur_eport; + cur_dir->tcpOAltPath = NV_TRUE; + + cur_dir->tcpOVCHop = vchop_map[ecol_idx][cur_eport]; + +#ifdef NVSWITCH_MC_TRACE + NVSWITCH_PRINT(device, INFO, "%s: tcp: %d, extra: %d, cur_eport: %d (alt)\n", + __FUNCTION__, i, extra_ports, cur_eport); + NVSWITCH_PRINT(device, INFO, "%s: cur_portlist_pos: %d\n", __FUNCTION__, + cur_portlist_pos); +#endif + // if this is the primary replica port, mark _ODD due to altpath + if (_is_primary_replica(ecol_idx, cur_eport, primary_replica)) + cur_dir->primaryReplica = PRIMARY_REPLICA_ODD; + + extra_ports--; + + // if there are more ports remaining, start the next entry + if (extra_ports) + { + // advance the portlist entry + cur_portlist_slot++; + cur_portlist_pos = port_offsets_by_tcp[i][cur_portlist_slot]; + cur_dir = &port_list[cur_portlist_pos]; + + cur_eport = _nvswitch_mc_get_next_port(&ecol_portmap); + if (cur_eport == NVSWITCH_MC_NULL_PORT_LS10) + { + return -NVL_ERR_GENERIC; + } + + cur_dir->tcpEPort = cur_eport; + + cur_dir->tcpEVCHop = vchop_map[ecol_idx][cur_eport]; + + cur_dir->tcp = i; + +#ifdef NVSWITCH_MC_TRACE + NVSWITCH_PRINT(device, INFO, "%s: tcp: %d, extra: %d, cur_eport: %d\n", + __FUNCTION__, i, extra_ports, cur_eport); + NVSWITCH_PRINT(device, INFO, "%s: cur_portlist_pos: %d\n", __FUNCTION__, + cur_portlist_pos); +#endif + + // if this is the primary replica port, mark it + if (_is_primary_replica(ecol_idx, cur_eport, primary_replica)) + cur_dir->primaryReplica = PRIMARY_REPLICA_EVEN; + + extra_ports--; + } + } + } + else + { + // odd column has more ports + extra_ports = -extra_ports; + + // iterate over even column to go through port pairs + for (j = 0; j < ecol_portcount; j++, cur_portlist_slot++) + { + cur_eport = _nvswitch_mc_get_next_port(&ecol_portmap); + cur_oport = _nvswitch_mc_get_next_port(&ocol_portmap); + if ((cur_eport == NVSWITCH_MC_NULL_PORT_LS10) || + (cur_oport == NVSWITCH_MC_NULL_PORT_LS10)) + { + return -NVL_ERR_GENERIC; + } + + // assign the ports to the current directive + cur_portlist_pos = port_offsets_by_tcp[i][cur_portlist_slot]; + cur_dir = &port_list[cur_portlist_pos]; + cur_dir->tcpEPort = cur_eport; + cur_dir->tcpOPort = cur_oport; + + cur_dir->tcpEVCHop = vchop_map[ecol_idx][cur_eport]; + cur_dir->tcpOVCHop = vchop_map[ocol_idx][cur_oport]; + + cur_dir->tcp = i; + +#ifdef NVSWITCH_MC_TRACE + NVSWITCH_PRINT(device, INFO, "%s: tcp: %d, extra: %d, cur_eport: %d, cur_oport %d\n", + __FUNCTION__, i, extra_ports, cur_eport, cur_oport); + NVSWITCH_PRINT(device, INFO, "%s: cur_portlist_pos: %d\n", __FUNCTION__, + cur_portlist_pos); +#endif + if (_is_primary_replica(ocol_idx, cur_oport, primary_replica)) + cur_dir->primaryReplica = PRIMARY_REPLICA_ODD; + if (_is_primary_replica(ecol_idx, cur_eport, primary_replica)) + cur_dir->primaryReplica = PRIMARY_REPLICA_EVEN; + + } + + // handle the leftover ports in odd column + cur_oport = _nvswitch_mc_get_next_port(&ocol_portmap); + if (cur_oport == NVSWITCH_MC_NULL_PORT_LS10) + { + return -NVL_ERR_GENERIC; + } + + // cur_portlist_slot is incremented by the last iteration, or 0 + cur_portlist_pos = port_offsets_by_tcp[i][cur_portlist_slot]; + cur_dir = &port_list[cur_portlist_pos]; + + cur_dir->tcpOPort = cur_oport; + + cur_dir->tcpOVCHop = vchop_map[ocol_idx][cur_oport]; + + cur_dir->tcp = i; + +#ifdef NVSWITCH_MC_TRACE + NVSWITCH_PRINT(device, INFO, "%s: tcp: %d, extra: %d, cur_oport %d\n", + __FUNCTION__, i, extra_ports, cur_oport); + NVSWITCH_PRINT(device, INFO, "%s: cur_portlist_pos: %d\n", __FUNCTION__, + cur_portlist_pos); +#endif + + if (_is_primary_replica(ocol_idx, cur_oport, primary_replica)) + cur_dir->primaryReplica = PRIMARY_REPLICA_ODD; + + extra_ports--; + + // process any remaining ports in odd column + while (extra_ports) + { + // get next odd port + cur_oport = _nvswitch_mc_get_next_port(&ocol_portmap); + if (cur_oport == NVSWITCH_MC_NULL_PORT_LS10) + { + return -NVL_ERR_GENERIC; + } + + // set it as even altpath port in current directive + cur_dir->tcpEPort = cur_oport; + cur_dir->tcpEAltPath = NV_TRUE; + + cur_dir->tcpEVCHop = vchop_map[ocol_idx][cur_oport]; + +#ifdef NVSWITCH_MC_TRACE + NVSWITCH_PRINT(device, INFO, "%s: tcp: %d, extra: %d, cur_oport %d (alt)\n", + __FUNCTION__, i, extra_ports, cur_oport); + NVSWITCH_PRINT(device, INFO, "%s: cur_portlist_pos: %d\n", __FUNCTION__, + cur_portlist_pos); +#endif + // if this is the primary replica port, mark _EVEN due to altpath + if (_is_primary_replica(ocol_idx, cur_oport, primary_replica)) + cur_dir->primaryReplica = PRIMARY_REPLICA_EVEN; + + extra_ports--; + + // if there is another port, it goes in the next directive + if (extra_ports) + { + cur_portlist_slot++; + cur_portlist_pos = port_offsets_by_tcp[i][cur_portlist_slot]; + cur_dir = &port_list[cur_portlist_pos]; + + cur_oport = _nvswitch_mc_get_next_port(&ocol_portmap); + if (cur_oport == NVSWITCH_MC_NULL_PORT_LS10) + { + return -NVL_ERR_GENERIC; + } + + cur_dir->tcpOPort = cur_oport; + + cur_dir->tcpOVCHop = vchop_map[ocol_idx][cur_oport]; + + cur_dir->tcp = i; + +#ifdef NVSWITCH_MC_TRACE + NVSWITCH_PRINT(device, INFO, "%s: tcp: %d, extra: %d, cur_oport %d\n", + __FUNCTION__, i, extra_ports, cur_oport); + NVSWITCH_PRINT(device, INFO, "%s: cur_portlist_pos: %d\n", __FUNCTION__, + cur_portlist_pos); +#endif + + if (_is_primary_replica(ocol_idx, cur_oport, primary_replica)) + cur_dir->primaryReplica = PRIMARY_REPLICA_ODD; + + extra_ports--; + } + } + } + + last_portlist_pos = NV_MAX(last_portlist_pos, cur_portlist_pos); + } + + // set the lastRound flag for the last entry in the spray string + cur_dir = &port_list[last_portlist_pos]; + cur_dir->lastRound = NV_TRUE; + + *entries_used = last_portlist_pos + 1; + +#ifdef NVSWITCH_MC_DEBUG + NVSWITCH_PRINT(device, INFO, + "%s: entries_used: %d, cur_portlist_pos: %d last_portlist_pos: %d\n", + __FUNCTION__, *entries_used, cur_portlist_pos, last_portlist_pos); +#endif + + return NVL_SUCCESS; +} + +// +// Helper that initializes a given directive list to some base values. +// +static NV_INLINE NvlStatus +nvswitch_init_portlist_ls10 +( + nvswitch_device *device, + NVSWITCH_TCP_DIRECTIVE_LS10 *mcp_list, + NvU32 mcp_list_size +) +{ + NvU32 i; + + if (mcp_list_size > NVSWITCH_MC_TCP_LIST_SIZE_LS10) + { + NVSWITCH_PRINT(device, ERROR, "%s: mcp_list_size out of range (%d)\n", + __FUNCTION__, mcp_list_size); + return -NVL_BAD_ARGS; + } + + nvswitch_os_memset(mcp_list, 0, + sizeof(NVSWITCH_TCP_DIRECTIVE_LS10) * mcp_list_size); + + // + // initialize port list with invalid values + // continueRound will be fixed up when processing round flags + // + for ( i = 0; i < mcp_list_size; i ++ ) + { + mcp_list[i].tcp = NVSWITCH_MC_INVALID; + mcp_list[i].continueRound = NV_TRUE; + mcp_list[i].tcpEPort = NVSWITCH_MC_NULL_PORT_LS10; + mcp_list[i].tcpOPort = NVSWITCH_MC_NULL_PORT_LS10; + } + + return NVL_SUCCESS; +} + + +// +// Helper to traverse list of directives given in src and copy only valid entries to dst starting +// at dst_list_offset. +// +// This is used when building the final directive list from individual per-spray-group lists, +// ensuring that no invalid entries sneak in, as well as checking for a nontrivial corner case +// where a configuration of input spray groups can result in a directive list larger than the +// 32-entry space allowed in the table. This returns -NVL_MORE_PROCESSING_REQUIRED which is +// then propagated to the caller to adjust the input parameters and try again. +// +static NV_INLINE NvlStatus +_nvswitch_mc_copy_valid_entries_ls10 +( + nvswitch_device *device, + NVSWITCH_TCP_DIRECTIVE_LS10 *dst, + NVSWITCH_TCP_DIRECTIVE_LS10 *src, + NvU32 num_valid_entries, + NvU32 dst_list_offset +) +{ + NvU32 i; + + if (num_valid_entries + dst_list_offset > NVSWITCH_MC_TCP_LIST_SIZE_LS10) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Overflow of mcplist. num_valid_entries: %d, dst_list_offset: %d\n", + __FUNCTION__, num_valid_entries, dst_list_offset); + return -NVL_MORE_PROCESSING_REQUIRED; + } + + for (i = 0; i < num_valid_entries; i++) + { + if (src[i].tcp == NVSWITCH_MC_INVALID) + { + NVSWITCH_PRINT(device, ERROR, "%s: invalid entry at offset %d\n", __FUNCTION__, i); + return -NVL_ERR_GENERIC; + } + +#ifdef NVSWITCH_MC_TRACE + NVSWITCH_PRINT(device, INFO, "%s: copying entry from src[%d] to dst[%d]\n", + __FUNCTION__, i, dst_list_offset + i); + _nvswitch_mc_print_directive(device, &src[i]); +#endif + + nvswitch_os_memcpy(&dst[dst_list_offset + i], &src[i], sizeof(NVSWITCH_TCP_DIRECTIVE_LS10)); + } + + return NVL_SUCCESS; +} + + +// +// Build multicast directive list using the inputs given. +// +// @param device [in] pointer to the nvswitch device struct +// @param port_list [in] array of ports for all spray groups +// @param ports_per_spray_group [in] array specifying the size of each spray group +// @param pri_replica_offsets [in] array, offsets of primary replica ports for each spray group +// @param replica_valid_array [in] array, specifies which pri_replica_offsets are valid +// @param vchop_array [in] array of vchop values for each port given in port_list +// @param table_entry [out] pointer to table entry where directive list will be written +// @param entries_used [out] pointer, number of valid entries produced is written here +// +NvlStatus +nvswitch_mc_build_mcp_list_ls10 +( + nvswitch_device *device, + NvU32 *port_list, + NvU32 *ports_per_spray_group, + NvU32 *pri_replica_offsets, + NvBool *replica_valid_array, + NvU8 *vchop_array, + NVSWITCH_MC_RID_ENTRY_LS10 *table_entry, + NvU32 *entries_used +) +{ + NvU32 i, spray_group_idx, spray_group_size, num_spray_groups, ret; + NvU8 *spray_group_ptrs; + NvU32 spray_group_offset = 0; + NvU32 primary_replica_port = NVSWITCH_MC_INVALID; + NvU32 dir_entries_used_sg = 0; + NvU32 dir_entries_used = 0; + NvU32 mcplist_offset = 0; + NvU32 cpb[NVSWITCH_MC_NUM_COLUMNS_LS10] = { 0 }; + NvU8 vchop_map[NVSWITCH_MC_NUM_COLUMNS_LS10][NVSWITCH_MC_PORTS_PER_COLUMN_LS10]; + NVSWITCH_TCP_DIRECTIVE_LS10 tmp_mcp_list[NVSWITCH_MC_TCP_LIST_SIZE_LS10]; + NVSWITCH_TCP_DIRECTIVE_LS10 *mcp_list; + + NvU32 j; + + if ((device == NULL) || (port_list == NULL) || (ports_per_spray_group == NULL) || + (pri_replica_offsets == NULL) || (replica_valid_array == NULL) || (vchop_array == NULL) || + (table_entry == NULL) || (entries_used == NULL)) + { + return -NVL_BAD_ARGS; + } + + num_spray_groups = table_entry->num_spray_groups; + spray_group_ptrs = table_entry->spray_group_ptrs; + mcp_list = table_entry->directives; + + if (num_spray_groups == 0) + { + NVSWITCH_PRINT(device, ERROR, "%s: No spray groups specified\n", __FUNCTION__); + return -NVL_BAD_ARGS; + } + + if (num_spray_groups > NVSWITCH_MC_MAX_SPRAYGROUPS) + { + NVSWITCH_PRINT(device, ERROR, "%s: Too many spray groups specified: %d\n", + __FUNCTION__, num_spray_groups); + return -NVL_BAD_ARGS; + } + + for (i = 0, j = 0; i < num_spray_groups; i++) + { + if (ports_per_spray_group[i] < NVSWITCH_MC_MIN_PORTS_PER_GROUP_LS10) + { + NVSWITCH_PRINT(device, ERROR, "%s: Too few ports in spray group %d\n", + __FUNCTION__, i); + return -NVL_BAD_ARGS; + } + + if (ports_per_spray_group[i] > NVSWITCH_NUM_LINKS_LS10) + { + NVSWITCH_PRINT(device, ERROR, "%s: Too many ports in spray group %d\n", + __FUNCTION__, i); + return -NVL_BAD_ARGS; + } + + j += ports_per_spray_group[i]; + } + + if (j > NVSWITCH_NUM_LINKS_LS10) + { + NVSWITCH_PRINT(device, ERROR, "%s: Too many ports specified in total spray groups: %d\n", + __FUNCTION__, j); + return -NVL_BAD_ARGS; + } + + ret = nvswitch_init_portlist_ls10(device, mcp_list, NVSWITCH_MC_TCP_LIST_SIZE_LS10); + if (ret != NVL_SUCCESS) + return ret; + + // build spray strings for each spray group + for ( spray_group_idx = 0; spray_group_idx < num_spray_groups; spray_group_idx++ ) + { + spray_group_size = ports_per_spray_group[spray_group_idx]; + +#ifdef NVSWITCH_MC_DEBUG + NVSWITCH_PRINT(device, INFO, "%s: processing spray group %d size %d of %d total groups\n", + __FUNCTION__, spray_group_idx, spray_group_size, num_spray_groups); +#endif + + ret = nvswitch_init_portlist_ls10(device, tmp_mcp_list, NVSWITCH_MC_TCP_LIST_SIZE_LS10); + if (ret != NVL_SUCCESS) + return ret; + + ret = _nvswitch_mc_build_cpb(device, spray_group_size, &port_list[spray_group_offset], + NVSWITCH_MC_NUM_COLUMNS_LS10, cpb, + &vchop_array[spray_group_offset], vchop_map); + + if (ret != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: error building column-port bitmap for spray group %d: %d\n", + __FUNCTION__, spray_group_idx, ret); + return ret; + } + + // Set the offset to this spray group in the mcp list. + spray_group_ptrs[spray_group_idx] = (NvU8)dir_entries_used; + +#ifdef NVSWITCH_MC_TRACE + NVSWITCH_PRINT(device, INFO, "%s: spray group offset for group %d is %d\n", + __FUNCTION__, spray_group_idx, dir_entries_used); + + for (i = 0; i < NVSWITCH_MC_NUM_COLUMNS_LS10; i++) + { + NVSWITCH_PRINT(device, INFO, "%d Relative ports in column %d\n", + _nvswitch_mc_get_pop_count(cpb[i]), i); + + for ( j = 0; j < 32; j++ ) + { + if (nvswitch_test_flags(cpb[i], NVBIT(j))) + { + NVSWITCH_PRINT(device, INFO, "%4d", j); + } + } + NVSWITCH_PRINT(device, INFO, "\n"); + } +#endif + // if primary replica is specified for this spray group, find the port number + if (replica_valid_array[spray_group_idx]) + { + if (pri_replica_offsets[spray_group_idx] >= spray_group_size) + { + NVSWITCH_PRINT(device, ERROR, + "%s: primary replica offset %d is out of range for spray group %d\n", + __FUNCTION__, pri_replica_offsets[spray_group_idx], spray_group_idx); + return -NVL_BAD_ARGS; + } + + for (i = 0; i < spray_group_size; i++) + { + if (pri_replica_offsets[spray_group_idx] == i) + { + primary_replica_port = port_list[spray_group_offset + i]; +#ifdef NVSWITCH_MC_DEBUG + NVSWITCH_PRINT(device, INFO, "Primary replica port in spray group %d is %d\n", + spray_group_idx, primary_replica_port); +#endif + } + } + } +#ifdef NVSWITCH_MC_DEBUG + if (primary_replica_port == NVSWITCH_MC_INVALID) + NVSWITCH_PRINT(device, INFO, "%s: No primary replica specified for spray group %d\n", + __FUNCTION__, spray_group_idx); +#endif + + // process columns into spray group of multicast directives + mcplist_offset = dir_entries_used; + + if (mcplist_offset >= NVSWITCH_MC_TCP_LIST_SIZE_LS10) + { + NVSWITCH_PRINT(device, ERROR, "%s: Overflow: mcplist_offset is %d\n", + __FUNCTION__, mcplist_offset); + return -NVL_ERR_GENERIC; + } + +#ifdef NVSWITCH_MC_DEBUG + NVSWITCH_PRINT(device, INFO, "%s: building tmp mc portlist at mcp offset %d, size %d\n", + __FUNCTION__, mcplist_offset, spray_group_size); +#endif + + ret = _nvswitch_mc_build_portlist(device, cpb, primary_replica_port, vchop_map, + tmp_mcp_list, &dir_entries_used_sg); + + if (ret != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: error building MC portlist\n", __FUNCTION__); + return ret; + } + +#ifdef NVSWITCH_MC_DEBUG + NVSWITCH_PRINT(device, INFO, "%s: entries used after building portlist: %d\n", + __FUNCTION__, dir_entries_used_sg); +#endif + + ret = _nvswitch_mc_compact_portlist(device, tmp_mcp_list, &dir_entries_used_sg); + if (ret != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: error compacting MC portlist\n", __FUNCTION__); + return ret; + } + + _nvswitch_mc_set_round_flags(tmp_mcp_list, dir_entries_used_sg); + + _nvswitch_mc_set_port_flags(tmp_mcp_list, dir_entries_used_sg); + + //copy spray group entries into final portlist + ret = _nvswitch_mc_copy_valid_entries_ls10(device, mcp_list, tmp_mcp_list, + dir_entries_used_sg, mcplist_offset); + if (ret != NVL_SUCCESS) + return ret; + + dir_entries_used += dir_entries_used_sg; + + // increment position in the input port list + spray_group_offset += spray_group_size; + } + + *entries_used = dir_entries_used; + +#ifdef NVSWITCH_MC_TRACE + _nvswitch_mc_print_directives(device, mcp_list, *entries_used, spray_group_ptrs, + num_spray_groups); +#endif + + return NVL_SUCCESS; +} + +static NvU32 +_nvswitch_col_offset_to_port_ls10 +( + NvU32 col, + NvU32 offset +) +{ + NvU32 i; + NVSWITCH_COLUMN_PORT_OFFSET_LS10 cpo; + + if ((col > NVSWITCH_MC_NUM_COLUMNS_LS10) || (offset > NVSWITCH_MC_PORTS_PER_COLUMN_LS10)) + return NVSWITCH_MC_INVALID; + + for (i = 0; i < NVSWITCH_NUM_LINKS_LS10; i++) + { + cpo = nvswitch_portmap_ls10[i]; + + if ((cpo.column == col) && (cpo.port_offset == offset)) + return i; + } + + return NVSWITCH_MC_INVALID; +} + +NvlStatus +nvswitch_mc_unwind_directives_ls10 +( + nvswitch_device *device, + NVSWITCH_TCP_DIRECTIVE_LS10 directives[NVSWITCH_MC_TCP_LIST_SIZE_LS10], + NvU32 ports[NVSWITCH_MC_MAX_PORTS], + NvU8 vc_hop[NVSWITCH_MC_MAX_PORTS], + NvU32 ports_per_spray_group[NVSWITCH_MC_MAX_SPRAYGROUPS], + NvU32 replica_offset[NVSWITCH_MC_MAX_SPRAYGROUPS], + NvBool replica_valid[NVSWITCH_MC_MAX_SPRAYGROUPS] +) +{ + NvU32 ret = NVL_SUCCESS; + NvU32 i, port_idx, cur_sg, ports_in_cur_sg, port, primary_replica; + NVSWITCH_TCP_DIRECTIVE_LS10 cur_dir, prev_dir; + + cur_sg = 0; + port_idx = 0; + ports_in_cur_sg = 0; + + for (i = 0; i < NVSWITCH_MC_TCP_LIST_SIZE_LS10; i++) + { + cur_dir = directives[i]; + if (cur_dir.tcp == NVSWITCH_MC_INVALID) + { +#ifdef NVSWITCH_MC_DEBUG + NVSWITCH_PRINT(device, INFO, "%s: reached end of directive list (element %d)\n", + __FUNCTION__, i); +#endif + break; + } + + // + // Find primary replica. + // For more info, see: IAS 6.12. Consistent MC Semantics + // + + primary_replica = PRIMARY_REPLICA_NONE; + + // + // If lastRound = 1 and continueRound = 1, primary replica is in + // this TCP directive and portFlag = 0/1 selects even/odd port. + // + if ((cur_dir.lastRound) && (cur_dir.continueRound)) + { + if (cur_dir.portFlag) + primary_replica = PRIMARY_REPLICA_ODD; + else + primary_replica = PRIMARY_REPLICA_EVEN; + + } + // + // If the previous TCP directive's portFlag = 0, and if it was not + // used to select the even or odd port of its predecessor, and this + // directive's portFlag == 1, this TCP directive contains the + // primary replica, and the next TCP directive's portFlag = 0/1 + // selects the even/odd port of this TCP directive. + // + + // If we don't have the first or last directive and portFlag == 1 + else if ((i < (NVSWITCH_MC_TCP_LIST_SIZE_LS10 - 1)) && (i > 0) && (cur_dir.portFlag == 1)) + { + prev_dir = directives[i - 1]; + + // Is the previous directive in the same sg and is the portFlag == 0? + if ((prev_dir.lastRound == 0) && (prev_dir.portFlag == 0)) + { + // Check if there is no predecessor, or if the predecessor's portFlag == 0 + if ((i < 2) || (directives[i - 2].portFlag == 0)) + { + // The next directive's portFlags specify even or odd + if (directives[i + 1].portFlag) + primary_replica = PRIMARY_REPLICA_ODD; + else + primary_replica = PRIMARY_REPLICA_EVEN; + } + } + } + + if (cur_dir.tcpEPort != NVSWITCH_MC_NULL_PORT_LS10) + { + ports_in_cur_sg++; + + if (cur_dir.tcpEAltPath) + { + port = _nvswitch_col_offset_to_port_ls10(cur_dir.tcp * 2 + 1, cur_dir.tcpEPort); + } + else + { + port = _nvswitch_col_offset_to_port_ls10(cur_dir.tcp * 2, cur_dir.tcpEPort); + } + + if (port == NVSWITCH_MC_INVALID) + { + // if we get here, there's a bug when converting from col/offset to port number + NVSWITCH_ASSERT(0); + return -NVL_ERR_GENERIC; + } + + if (port_idx >= NVSWITCH_MC_MAX_PORTS) + { + // if we get here, there's a bug when incrementing the port index + NVSWITCH_ASSERT(0); + return -NVL_ERR_GENERIC; + } + + vc_hop[port_idx] = cur_dir.tcpEVCHop; + ports[port_idx] = port; + + if (primary_replica == PRIMARY_REPLICA_EVEN) + { + replica_offset[cur_sg] = port_idx; + replica_valid[cur_sg] = NV_TRUE; +#ifdef NVSWITCH_MC_TRACE + NVSWITCH_PRINT(device, INFO, "%s: primary replica is port %d, offset %d in sg %d\n", + __FUNCTION__, port, port_idx, cur_sg); +#endif + } + + port_idx++; + } + + if (cur_dir.tcpOPort != NVSWITCH_MC_NULL_PORT_LS10) + { + ports_in_cur_sg++; + + if (cur_dir.tcpOAltPath) + { + port = _nvswitch_col_offset_to_port_ls10(cur_dir.tcp * 2, cur_dir.tcpOPort); + } + else + { + port = _nvswitch_col_offset_to_port_ls10(cur_dir.tcp * 2 + 1, cur_dir.tcpOPort); + } + + if (port == NVSWITCH_MC_INVALID) + { + // if we get here, there's a bug when converting from col/offset to port number + NVSWITCH_ASSERT(0); + return -NVL_ERR_GENERIC; + } + + if (port_idx >= NVSWITCH_MC_MAX_PORTS) + { + // if we get here, there's a bug when incrementing the port index + NVSWITCH_ASSERT(0); + return -NVL_ERR_GENERIC; + } + + vc_hop[port_idx] = cur_dir.tcpOVCHop; + ports[port_idx] = port; + + if (primary_replica == PRIMARY_REPLICA_ODD) + { + replica_offset[cur_sg] = port_idx; + replica_valid[cur_sg] = NV_TRUE; +#ifdef NVSWITCH_MC_TRACE + NVSWITCH_PRINT(device, INFO, "%s: primary replica is port %d, offset %d in sg %d\n", + __FUNCTION__, port, port_idx, cur_sg); +#endif + } + + port_idx++; + } + + if (cur_dir.lastRound) + { +#ifdef NVSWITCH_MC_TRACE + NVSWITCH_PRINT(device, INFO, "%s: reached end of spray group %d, %d total ports\n", + __FUNCTION__, cur_sg, ports_in_cur_sg); +#endif + ports_per_spray_group[cur_sg] = ports_in_cur_sg; + ports_in_cur_sg = 0; + cur_sg++; + } + } + + return ret; +} + +// +// Invalidate an MCRID table entry. +// +// @param device [in] pointer to the nvswitch device struct +// @param port [in] port for which to invalidate the table entry +// @param index [in] index into the MCRID table +// @param use_extended_table [in] specifies whether to use the extended table, or main table +// @param zero [in] specifies whether to zero the entry as well as invalidate +// +NvlStatus +nvswitch_mc_invalidate_mc_rid_entry_ls10 +( + nvswitch_device *device, + NvU32 port, + NvU32 index, + NvBool use_extended_table, + NvBool zero +) +{ + NvU32 reg, i; + + if ((device == NULL) || (!nvswitch_is_link_valid(device, port))) + return -NVL_BAD_ARGS; + + if (use_extended_table && (index > NV_ROUTE_RIDTABADDR_INDEX_MCRIDEXTTAB_DEPTH)) + { + NVSWITCH_PRINT(device, ERROR, "%s: index %d out of range for extended table\n", + __FUNCTION__, index); + return -NVL_BAD_ARGS; + } + + if (index > NV_ROUTE_RIDTABADDR_INDEX_MCRIDTAB_DEPTH) + { + NVSWITCH_PRINT(device, ERROR, "%s: index %d out of range for main table\n", + __FUNCTION__, index); + return -NVL_BAD_ARGS; + } + + if (use_extended_table) + reg = FLD_SET_DRF(_ROUTE, _RIDTABADDR, _RAM_SEL, _SELECTSEXTMCRIDROUTERAM, 0); + else + reg = FLD_SET_DRF(_ROUTE, _RIDTABADDR, _RAM_SEL, _SELECTSMCRIDROUTERAM, 0); + + reg = FLD_SET_DRF_NUM(_ROUTE, _RIDTABADDR, _INDEX, index, reg); + NVSWITCH_NPORT_WR32_LS10(device, port, _ROUTE, _RIDTABADDR, reg); + + reg = FLD_SET_DRF_NUM(_ROUTE, _RIDTABDATA0, _VALID, 0, 0); + + if (!zero) + { + NVSWITCH_NPORT_WR32_LS10(device, port, _ROUTE, _RIDTABDATA0, reg); + return NVL_SUCCESS; + } + + for (i = 0; i < 4; i++) + { + NVSWITCH_NPORT_WR32_LS10(device, port, _ROUTE, _RIDTABDATA2, 0); + } + + for (i = 0; i < 32; i++) + { + NVSWITCH_NPORT_WR32_LS10(device, port, _ROUTE, _RIDTABDATA1, 0); + } + + NVSWITCH_NPORT_WR32_LS10(device, port, _ROUTE, _RIDTABDATA0, 0); + + return NVL_SUCCESS; +} + +// +// Program an MCRID table entry. +// +// @param device [in] pointer to the nvswitch device struct +// @param port [in] port for which to write the table entry +// @param table_entry [in] pointer to the table entry to write +// @param directive_list_size [in] size of the directive list contained in table_entry +// +NvlStatus +nvswitch_mc_program_mc_rid_entry_ls10 +( + nvswitch_device *device, + NvU32 port, + NVSWITCH_MC_RID_ENTRY_LS10 *table_entry, + NvU32 directive_list_size +) +{ + NvU32 i, reg; + NVSWITCH_TCP_DIRECTIVE_LS10 *cur_dir; + + if ((device == NULL) || (!nvswitch_is_link_valid(device, port)) || (table_entry == NULL)) + { + return -NVL_BAD_ARGS; + } + + if (table_entry->use_extended_table && + (table_entry->index > NV_ROUTE_RIDTABADDR_INDEX_MCRIDEXTTAB_DEPTH)) + { + NVSWITCH_PRINT(device, ERROR, "%s: index %d out of range for extended table\n", + __FUNCTION__, table_entry->index); + return -NVL_BAD_ARGS; + } + + if (table_entry->index > NV_ROUTE_RIDTABADDR_INDEX_MCRIDTAB_DEPTH) + { + NVSWITCH_PRINT(device, ERROR, "%s: index %d out of range for main table\n", + __FUNCTION__, table_entry->index); + return -NVL_BAD_ARGS; + } + + if (directive_list_size > NVSWITCH_MC_TCP_LIST_SIZE_LS10) + { + NVSWITCH_PRINT(device, ERROR, "%s: directive_list_size out of range\n", __FUNCTION__); + return -NVL_BAD_ARGS; + } + + if ((table_entry->num_spray_groups > NVSWITCH_MC_MAX_SPRAY_LS10) || + (table_entry->num_spray_groups == 0)) + { + NVSWITCH_PRINT(device, ERROR, "%s: num_spray_groups out of range\n", __FUNCTION__); + return -NVL_BAD_ARGS; + } + + if ((table_entry->mcpl_size > NVSWITCH_NUM_LINKS_LS10) || + (table_entry->mcpl_size == 0)) + { + NVSWITCH_PRINT(device, ERROR, "%s: mcpl_size out of range\n", __FUNCTION__); + return -NVL_BAD_ARGS; + } + + if (table_entry->ext_ptr_valid && + (table_entry->ext_ptr > NV_ROUTE_RIDTABADDR_INDEX_MCRIDEXTTAB_DEPTH)) + { + NVSWITCH_PRINT(device, ERROR, "%s: extended_ptr out of range\n", __FUNCTION__); + return -NVL_BAD_ARGS; + } + + if (table_entry->use_extended_table) + reg = FLD_SET_DRF(_ROUTE, _RIDTABADDR, _RAM_SEL, _SELECTSEXTMCRIDROUTERAM, 0); + else + reg = FLD_SET_DRF(_ROUTE, _RIDTABADDR, _RAM_SEL, _SELECTSMCRIDROUTERAM, 0); + + reg = FLD_SET_DRF_NUM(_ROUTE, _RIDTABADDR, _INDEX, table_entry->index, reg); + NVSWITCH_NPORT_WR32_LS10(device, port, _ROUTE, _RIDTABADDR, reg); + + // + // Write register 2. Each time this register is written it causes the + // mcpl_str_ptr index to increment by 4 (4 entries are written at a time). + // + i = 0; + while (i < table_entry->num_spray_groups) + { + +#ifdef NVSWITCH_MC_DEBUG + NVSWITCH_PRINT(device, INFO, "%s: writing offset %d for spray group %d\n", + __FUNCTION__, table_entry->spray_group_ptrs[i], i); +#endif + reg = FLD_SET_DRF_NUM(_ROUTE, _RIDTABDATA2, _MCPL_STR_PTR0, + table_entry->spray_group_ptrs[i], 0); + i++; + + if (i < table_entry->num_spray_groups) + { +#ifdef NVSWITCH_MC_DEBUG + NVSWITCH_PRINT(device, INFO, "%s: writing offset %d for spray group %d\n", + __FUNCTION__, table_entry->spray_group_ptrs[i], i); +#endif + reg = FLD_SET_DRF_NUM(_ROUTE, _RIDTABDATA2, _MCPL_STR_PTR1, + table_entry->spray_group_ptrs[i], reg); + i++; + } + + if (i < table_entry->num_spray_groups) + { +#ifdef NVSWITCH_MC_DEBUG + NVSWITCH_PRINT(device, INFO, "%s: writing offset %d for spray group %d\n", + __FUNCTION__, table_entry->spray_group_ptrs[i], i); +#endif + reg = FLD_SET_DRF_NUM(_ROUTE, _RIDTABDATA2, _MCPL_STR_PTR2, + table_entry->spray_group_ptrs[i], reg); + i++; + } + + if (i < table_entry->num_spray_groups) + { +#ifdef NVSWITCH_MC_DEBUG + NVSWITCH_PRINT(device, INFO, "%s: writing offset %d for spray group %d\n", + __FUNCTION__, table_entry->spray_group_ptrs[i], i); +#endif + reg = FLD_SET_DRF_NUM(_ROUTE, _RIDTABDATA2, _MCPL_STR_PTR3, + table_entry->spray_group_ptrs[i], reg); + i++; + } + + NVSWITCH_NPORT_WR32_LS10(device, port, _ROUTE, _RIDTABDATA2, reg); + } + + + // + // Write register 1. Each time this register is written it causes the mcpl_directive + // index to increment by 1. + // + + for (i = 0; i < directive_list_size; i++) + { + cur_dir = &table_entry->directives[i]; + + reg = FLD_SET_DRF_NUM(_ROUTE, _RIDTABDATA1, _MCPL_E_PORT, cur_dir->tcpEPort, 0); + reg = FLD_SET_DRF_NUM(_ROUTE, _RIDTABDATA1, _MCPL_E_ALTPATH, cur_dir->tcpEAltPath, reg); + reg = FLD_SET_DRF_NUM(_ROUTE, _RIDTABDATA1, _MCPL_E_REQ_VCHOP, cur_dir->tcpEVCHop, reg); + reg = FLD_SET_DRF_NUM(_ROUTE, _RIDTABDATA1, _MCPL_O_PORT, cur_dir->tcpOPort, reg); + reg = FLD_SET_DRF_NUM(_ROUTE, _RIDTABDATA1, _MCPL_O_ALTPATH, cur_dir->tcpOAltPath, reg); + reg = FLD_SET_DRF_NUM(_ROUTE, _RIDTABDATA1, _MCPL_O_REQ_VCHOP, cur_dir->tcpOVCHop, reg); + reg = FLD_SET_DRF_NUM(_ROUTE, _RIDTABDATA1, _MCPL_TCP, cur_dir->tcp, reg); + reg = FLD_SET_DRF_NUM(_ROUTE, _RIDTABDATA1, _MCPL_PORT_FLAG, cur_dir->portFlag, reg); + reg = FLD_SET_DRF_NUM(_ROUTE, _RIDTABDATA1, _MCPL_RND_CONTINUE, cur_dir->continueRound, reg); + reg = FLD_SET_DRF_NUM(_ROUTE, _RIDTABDATA1, _MCPL_LAST_RND, cur_dir->lastRound, reg); + + NVSWITCH_NPORT_WR32_LS10(device, port, _ROUTE, _RIDTABDATA1, reg); + } + + // + // Write register 0. + // + // Due to size limitations in HW, _MCPL_SIZE must be adjusted by one here. + // From the reference manuals: + // + // The number of expected responses at this switch hop for this MCID is MCPL_SIZE+1. + // + // For _MCPL_SPRAY_SIZE the value 0 represents 16. This requires no adjustment + // when writing, since 16 is truncated to 0 due to field width. + // + // The input parameters for both of these are guaranteed to be nonzero values. + // + reg = FLD_SET_DRF_NUM(_ROUTE, _RIDTABDATA0, _MCPL_SIZE, table_entry->mcpl_size - 1, 0); + reg = FLD_SET_DRF_NUM(_ROUTE, _RIDTABDATA0, _MCPL_SPRAY_SIZE, table_entry->num_spray_groups, + reg); + reg = FLD_SET_DRF_NUM(_ROUTE, _RIDTABDATA0, _MCPL_RID_EXT_PTR, table_entry->ext_ptr, reg); + reg = FLD_SET_DRF_NUM(_ROUTE, _RIDTABDATA0, _MCPL_RID_EXT_PTR_VAL, table_entry->ext_ptr_valid, + reg); + reg = FLD_SET_DRF_NUM(_ROUTE, _RIDTABDATA0, _VALID, 1, reg); + + if (!table_entry->use_extended_table) + reg = FLD_SET_DRF_NUM(_ROUTE, _RIDTABDATA0, _MCPL_NO_DYN_RSP, table_entry->no_dyn_rsp, reg); + + NVSWITCH_NPORT_WR32_LS10(device, port, _ROUTE, _RIDTABDATA0, reg); + + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_mc_read_mc_rid_entry_ls10 +( + nvswitch_device *device, + NvU32 port, + NVSWITCH_MC_RID_ENTRY_LS10 *table_entry +) +{ + NvU32 i, reg; + + if ((device == NULL) || (table_entry == NULL)) + return -NVL_BAD_ARGS; + + if (table_entry->use_extended_table && + (table_entry->index > NV_ROUTE_RIDTABADDR_INDEX_MCRIDEXTTAB_DEPTH)) + { + NVSWITCH_PRINT(device, ERROR, "%s: index %d out of range for extended table\n", + __FUNCTION__, table_entry->index); + return -NVL_BAD_ARGS; + } + + if (table_entry->index > NV_ROUTE_RIDTABADDR_INDEX_MCRIDTAB_DEPTH) + { + NVSWITCH_PRINT(device, ERROR, "%s: index %d out of range for main table\n", + __FUNCTION__, table_entry->index); + return -NVL_BAD_ARGS; + } + + // set the address + if (table_entry->use_extended_table) + reg = FLD_SET_DRF(_ROUTE, _RIDTABADDR, _RAM_SEL, _SELECTSEXTMCRIDROUTERAM, 0); + else + reg = FLD_SET_DRF(_ROUTE, _RIDTABADDR, _RAM_SEL, _SELECTSMCRIDROUTERAM, 0); + + reg = FLD_SET_DRF_NUM(_ROUTE, _RIDTABADDR, _INDEX, table_entry->index, reg); + NVSWITCH_NPORT_WR32_LS10(device, port, _ROUTE, _RIDTABADDR, reg); + + // read in the entry + reg = NVSWITCH_NPORT_RD32_LS10(device, port, _ROUTE, _RIDTABDATA0); + + // parse DATA0 + table_entry->valid = DRF_VAL(_ROUTE, _RIDTABDATA0, _VALID, reg); + + // if the entry is invalid, we're done + if (!table_entry->valid) + { + return NVL_SUCCESS; + } + + // + // Due to size limitations in HW, _MCPL_SIZE must be adjusted by one here. + // From the reference manuals: + // + // The number of expected responses at this switch hop for this MCID is MCPL_SIZE+1. + // + // For _MCPL_SPRAY_SIZE, the value 0 represents 16, so we need to adjust for that here. + // + table_entry->mcpl_size = DRF_VAL(_ROUTE, _RIDTABDATA0, _MCPL_SIZE, reg) + 1; + table_entry->num_spray_groups = DRF_VAL(_ROUTE, _RIDTABDATA0, _MCPL_SPRAY_SIZE, reg); + + if (table_entry->num_spray_groups == 0) + table_entry->num_spray_groups = 16; + + if (!table_entry->use_extended_table) + { + table_entry->ext_ptr = DRF_VAL(_ROUTE, _RIDTABDATA0, _MCPL_RID_EXT_PTR, reg); + table_entry->ext_ptr_valid = DRF_VAL(_ROUTE, _RIDTABDATA0, _MCPL_RID_EXT_PTR_VAL, reg); + } + + table_entry->no_dyn_rsp = DRF_VAL(_ROUTE, _RIDTABDATA0, _MCPL_NO_DYN_RSP, reg); + + // DATA1 contains the directives + + for (i = 0; i < NVSWITCH_MC_TCP_LIST_SIZE_LS10; i++) + { + reg = NVSWITCH_NPORT_RD32_LS10(device, port, _ROUTE, _RIDTABDATA1); + + table_entry->directives[i].tcpEPort = DRF_VAL(_ROUTE, _RIDTABDATA1, _MCPL_E_PORT, reg); + table_entry->directives[i].tcpEAltPath = DRF_VAL(_ROUTE, _RIDTABDATA1, _MCPL_E_ALTPATH, reg); + table_entry->directives[i].tcpEVCHop = DRF_VAL(_ROUTE, _RIDTABDATA1, _MCPL_E_REQ_VCHOP, reg); + table_entry->directives[i].tcpOPort = DRF_VAL(_ROUTE, _RIDTABDATA1, _MCPL_O_PORT, reg); + table_entry->directives[i].tcpOAltPath = DRF_VAL(_ROUTE, _RIDTABDATA1, _MCPL_O_ALTPATH, reg); + table_entry->directives[i].tcpOVCHop = DRF_VAL(_ROUTE, _RIDTABDATA1, _MCPL_O_REQ_VCHOP, reg); + table_entry->directives[i].tcp = DRF_VAL(_ROUTE, _RIDTABDATA1, _MCPL_TCP, reg); + table_entry->directives[i].portFlag = DRF_VAL(_ROUTE, _RIDTABDATA1, _MCPL_PORT_FLAG, reg); + table_entry->directives[i].continueRound = DRF_VAL(_ROUTE, _RIDTABDATA1, + _MCPL_RND_CONTINUE, reg); + table_entry->directives[i].lastRound = DRF_VAL(_ROUTE, _RIDTABDATA1, _MCPL_LAST_RND, reg); + } + + // DATA2 contains the spray group pointers. This register loads the next 4 pointers on each read. + i = 0; + while (i < table_entry->num_spray_groups) + { + reg = NVSWITCH_NPORT_RD32_LS10(device, port, _ROUTE, _RIDTABDATA2); + + table_entry->spray_group_ptrs[i] = DRF_VAL(_ROUTE, _RIDTABDATA2, _MCPL_STR_PTR0, reg); + i++; + + if (i < table_entry->num_spray_groups) + { + table_entry->spray_group_ptrs[i] = DRF_VAL(_ROUTE, _RIDTABDATA2, _MCPL_STR_PTR1, reg); + i++; + } + + if (i < table_entry->num_spray_groups) + { + table_entry->spray_group_ptrs[i] = DRF_VAL(_ROUTE, _RIDTABDATA2, _MCPL_STR_PTR2, reg); + i++; + } + + if (i < table_entry->num_spray_groups) + { + table_entry->spray_group_ptrs[i] = DRF_VAL(_ROUTE, _RIDTABDATA2, _MCPL_STR_PTR3, reg); + i++; + } + } + + return NVL_SUCCESS; +} + diff --git a/src/common/nvswitch/kernel/ls10/pmgr_ls10.c b/src/common/nvswitch/kernel/ls10/pmgr_ls10.c new file mode 100644 index 000000000..dbe8108c7 --- /dev/null +++ b/src/common/nvswitch/kernel/ls10/pmgr_ls10.c @@ -0,0 +1,349 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include "common_nvswitch.h" +#include "regkey_nvswitch.h" +#include "ls10/ls10.h" +#include "ls10/pmgr_ls10.h" +#include "error_nvswitch.h" +#include "pmgr_nvswitch.h" +#include "rom_nvswitch.h" +#include "export_nvswitch.h" +#include "soe/soe_nvswitch.h" +#include "soe/soeifcore.h" + +#include "nvswitch/ls10/dev_pmgr.h" + +static NvBool +_nvswitch_i2c_ports_priv_locked_ls10 +( + nvswitch_device *device +) +{ + NvU32 regVal; + + regVal = NVSWITCH_REG_RD32(device, _PMGR, _I2C_PRIV_LEVEL_MASK(NVSWITCH_I2C_PORT_I2CA)); + if (FLD_TEST_DRF(_PMGR, _I2C_PRIV_LEVEL_MASK, _WRITE_PROTECTION_LEVEL0, _DISABLE, regVal)) + { + return NV_TRUE; + } + + regVal = NVSWITCH_REG_RD32(device, _PMGR, _I2C_PRIV_LEVEL_MASK(NVSWITCH_I2C_PORT_I2CB)); + if (FLD_TEST_DRF(_PMGR, _I2C_PRIV_LEVEL_MASK, _WRITE_PROTECTION_LEVEL0, _DISABLE, regVal)) + { + return NV_TRUE; + } + + regVal = NVSWITCH_REG_RD32(device, _PMGR, _I2C_PRIV_LEVEL_MASK(NVSWITCH_I2C_PORT_I2CC)); + if (FLD_TEST_DRF(_PMGR, _I2C_PRIV_LEVEL_MASK, _WRITE_PROTECTION_LEVEL0, _DISABLE, regVal)) + { + return NV_TRUE; + } + + return NV_FALSE; +} + +static NvlStatus +_nvswitch_i2c_init_soe_ls10 +( + nvswitch_device *device +) +{ + NvlStatus ret; + PNVSWITCH_OBJI2C pI2c; + + pI2c = device->pI2c; + + if (!nvswitch_is_soe_supported(device)) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + // Setup DMA + ret = nvswitch_os_alloc_contig_memory(device->os_handle, &pI2c->pCpuAddr, SOE_I2C_DMA_BUF_SIZE, + (device->dma_addr_width == 32)); + if (ret != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: nvswitch_os_alloc_contig_memory returned %d\n", __FUNCTION__, ret); + return ret; + } + + nvswitch_os_memset(pI2c->pCpuAddr, 0, SOE_I2C_DMA_BUF_SIZE); + + ret = nvswitch_os_map_dma_region(device->os_handle, pI2c->pCpuAddr, &pI2c->dmaHandle, + SOE_I2C_DMA_BUF_SIZE, NVSWITCH_DMA_DIR_BIDIRECTIONAL); + if (ret != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: nvswitch_os_map_dma_region returned %d\n", __FUNCTION__, ret); + nvswitch_os_free_contig_memory(device->os_handle, pI2c->pCpuAddr, SOE_I2C_DMA_BUF_SIZE); + pI2c->pCpuAddr = NULL; + return ret; + } + + return NVL_SUCCESS; +} + +/*! @brief Set up a port to use a PMGR implementation. + * + * @param[in] device NvSwitch device + * @param[in] port The port identifier for the bus. + */ +static void +_nvswitch_i2c_set_port_pmgr_ls10 +( + nvswitch_device *device, + NvU32 port +) +{ + PNVSWITCH_OBJI2C pI2c = device->pI2c; + + NVSWITCH_ASSERT(port < NVSWITCH_MAX_I2C_PORTS); + + pI2c->PortInfo[port] = FLD_SET_DRF(_I2C, _PORTINFO, _DEFINED, _PRESENT, pI2c->PortInfo[port]); + pI2c->Ports[port].defaultSpeedMode = NVSWITCH_I2C_SPEED_MODE_100KHZ; + pI2c->PortInfo[port] = FLD_SET_DRF(_I2C, _PORTINFO, + _ACCESS_ALLOWED, _TRUE, + pI2c->PortInfo[port]); +} + +// +// Pre-initialize the software & hardware state of the switch I2C & GPIO interface +// +void +nvswitch_init_pmgr_ls10 +( + nvswitch_device *device +) +{ + PNVSWITCH_OBJI2C pI2c; + + // Initialize I2C object + nvswitch_i2c_init(device); + + pI2c = device->pI2c; + + if (pI2c != NULL) + { + pI2c->kernelI2CSupported = NV_TRUE; + pI2c->soeI2CSupported = NV_TRUE; + + if (_nvswitch_i2c_ports_priv_locked_ls10(device)) + { + NVSWITCH_PRINT(device, WARN, "%s: I2C ports priv locked!\n", __FUNCTION__); + pI2c->kernelI2CSupported = NV_FALSE; + } + + if (_nvswitch_i2c_init_soe_ls10(device) != NVL_SUCCESS) + { + pI2c->soeI2CSupported = NV_FALSE; + } + + // Setup the 3 I2C ports + _nvswitch_i2c_set_port_pmgr_ls10(device, NVSWITCH_I2C_PORT_I2CA); + _nvswitch_i2c_set_port_pmgr_ls10(device, NVSWITCH_I2C_PORT_I2CB); + _nvswitch_i2c_set_port_pmgr_ls10(device, NVSWITCH_I2C_PORT_I2CC); + } + +} + +static const NVSWITCH_GPIO_INFO nvswitch_gpio_pin_Default[] = +{ + NVSWITCH_DESCRIBE_GPIO_PIN( 0, _INSTANCE_ID0, 0, IN), // Instance ID bit 0 + NVSWITCH_DESCRIBE_GPIO_PIN( 1, _INSTANCE_ID1, 0, IN), // Instance ID bit 1 + NVSWITCH_DESCRIBE_GPIO_PIN( 2, _INSTANCE_ID2, 0, IN), // Instance ID bit 2 +}; + +static const NvU32 nvswitch_gpio_pin_Default_size = NV_ARRAY_ELEMENTS(nvswitch_gpio_pin_Default); + +// +// Initialize the software state of the switch I2C & GPIO interface +// Temporarily forcing default GPIO values. +// + +// TODO: This function should be updated with the board values from DCB. + +void +nvswitch_init_pmgr_devices_ls10 +( + nvswitch_device *device +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + PNVSWITCH_OBJI2C pI2c = device->pI2c; + + if (IS_FMODEL(device) || IS_EMULATION(device) || IS_RTLSIM(device)) + { + // GPIOs not modelled on non-silicon + chip_device->gpio_pin = NULL; + chip_device->gpio_pin_size = 0; + } + else + { + chip_device->gpio_pin = nvswitch_gpio_pin_Default; + chip_device->gpio_pin_size = nvswitch_gpio_pin_Default_size; + } + + pI2c->device_list = NULL; + pI2c->device_list_size = 0; +} + +NvlStatus +nvswitch_get_rom_info_ls10 +( + nvswitch_device *device, + NVSWITCH_EEPROM_TYPE *eeprom +) +{ + NVSWITCH_PRINT(device, WARN, "%s: Function not implemented\n", __FUNCTION__); + return NVL_SUCCESS; +} + +/*! + * RM Control command to determine the physical id of the device. + */ +NvU32 +nvswitch_read_physical_id_ls10 +( + nvswitch_device *device +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + NvU32 physical_id = 0; + NvU32 data; + NvU32 idx_gpio; + NvU32 input_inv; + NvU32 function_offset; + + for (idx_gpio = 0; idx_gpio < chip_device->gpio_pin_size; idx_gpio++) + { + if ((chip_device->gpio_pin[idx_gpio].function >= NVSWITCH_GPIO_ENTRY_FUNCTION_INSTANCE_ID0) && + (chip_device->gpio_pin[idx_gpio].function <= NVSWITCH_GPIO_ENTRY_FUNCTION_INSTANCE_ID6)) + { + if (chip_device->gpio_pin[idx_gpio].misc == NVSWITCH_GPIO_ENTRY_MISC_IO_INV_IN) + { + input_inv = NV_PMGR_GPIO_INPUT_CNTL_1_INV_YES; + } + else + { + input_inv = NV_PMGR_GPIO_INPUT_CNTL_1_INV_NO; + } + + NVSWITCH_REG_WR32(device, _PMGR, _GPIO_INPUT_CNTL_1, + DRF_NUM(_PMGR, _GPIO_INPUT_CNTL_1, _PINNUM, chip_device->gpio_pin[idx_gpio].pin) | + DRF_NUM(_PMGR, _GPIO_INPUT_CNTL_1, _INV, input_inv) | + DRF_DEF(_PMGR, _GPIO_INPUT_CNTL_1, _BYPASS_FILTER, _NO)); + + data = NVSWITCH_REG_RD32(device, _PMGR, _GPIO_INPUT_CNTL_1); + function_offset = chip_device->gpio_pin[idx_gpio].function - + NVSWITCH_GPIO_ENTRY_FUNCTION_INSTANCE_ID0; + physical_id |= + (DRF_VAL(_PMGR, _GPIO_INPUT_CNTL_1, _READ, data) << function_offset); + } + } + + NVSWITCH_PRINT(device, SETUP, "%s Device position Id = 0x%x\n", __FUNCTION__, physical_id); + + return physical_id; +} + +/*! + * RM Control command to perform indexed I2C. + */ +NvlStatus +nvswitch_ctrl_i2c_indexed_ls10 +( + nvswitch_device *device, + NVSWITCH_CTRL_I2C_INDEXED_PARAMS *pParams +) +{ + PNVSWITCH_OBJI2C pI2c; + + pI2c = device->pI2c; + + if (pI2c == NULL) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + if (pParams == NULL) + { + return -NVL_BAD_ARGS; + } + + // SW I2C only supported by kernel driver + if (device->regkeys.force_kernel_i2c == NV_SWITCH_REGKEY_FORCE_KERNEL_I2C_ENABLE || + FLD_TEST_DRF(SWITCH_CTRL, _I2C_FLAGS, _FLAVOR, _SW, pParams->flags)) + { + if (!pI2c->kernelI2CSupported) + { + return -NVL_ERR_NOT_SUPPORTED; + } + return nvswitch_ctrl_i2c_indexed_lr10(device, pParams); + } + + if (pI2c->soeI2CSupported) + { + return soeI2CAccess_HAL(device, pParams); + } + + return -NVL_ERR_NOT_SUPPORTED; +} + +/*! + * Return if I2C transactions can be supported. + * + * @param[in] device The NvSwitch Device. + * + */ +NvBool +nvswitch_is_i2c_supported_ls10 +( + nvswitch_device *device +) +{ + return ((device->pI2c != NULL) && + (device->pI2c->soeI2CSupported || device->pI2c->kernelI2CSupported)); +} + +/*! + * Return if I2C device and port is allowed access + * + * @param[in] device The NvSwitch Device. + * @param[in] port The I2C Port. + * @param[in] addr The I2C device to access. + * @param[in] bIsRead Boolean if I2C transaction is a read. + * + */ +NvBool +nvswitch_i2c_is_device_access_allowed_ls10 +( + nvswitch_device *device, + NvU32 port, + NvU8 addr, + NvBool bIsRead +) +{ + // Check will be performed in SOE + return NV_TRUE; +} diff --git a/src/common/nvswitch/kernel/ls10/smbpbi_ls10.c b/src/common/nvswitch/kernel/ls10/smbpbi_ls10.c new file mode 100644 index 000000000..8daa2a394 --- /dev/null +++ b/src/common/nvswitch/kernel/ls10/smbpbi_ls10.c @@ -0,0 +1,222 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "common_nvswitch.h" + +#include "flcn/flcn_nvswitch.h" +#include "rmflcncmdif_nvswitch.h" +#include "nvVer.h" + +NvlStatus +nvswitch_smbpbi_alloc_ls10 +( + nvswitch_device *device +) +{ + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_smbpbi_post_init_hal_ls10 +( + nvswitch_device *device +) +{ + return NVL_SUCCESS; +} + +void +nvswitch_smbpbi_destroy_hal_ls10 +( + nvswitch_device *device +) +{ +} + +NvlStatus +nvswitch_smbpbi_get_dem_num_messages_ls10 +( + nvswitch_device *device, + NvU8 *pMsgCount +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +NvlStatus +nvswitch_inforom_dem_load_ls10 +( + nvswitch_device *device +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +NvlStatus +nvswitch_smbpbi_dem_load_ls10 +( + nvswitch_device *device +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +void +nvswitch_smbpbi_log_message_ls10 +( + nvswitch_device *device, + NvU32 num, + NvU32 msglen, + NvU8 *osErrorString +) +{ + struct smbpbi *pSmbpbi = device->pSmbpbi; + RM_FLCN_CMD_SOE cmd; + RM_SOE_SMBPBI_CMD_LOG_MESSAGE *pLogCmd = &cmd.cmd.smbpbiCmd.logMessage; + NvU8 offset; + NvU8 segSize; + NVSWITCH_TIMEOUT timeout; + NvU32 cmdSeqDesc; + FLCN *pFlcn; + NvlStatus status; + + if ((pSmbpbi == NULL) || (device->pSoe == NULL) || + (pSmbpbi->logMessageNesting++ != 0)) + { + goto nvswitch_smbpbi_log_message_exit; + } + + pFlcn = device->pSoe->pFlcn; + + nvswitch_os_memset(&cmd, 0, sizeof(cmd)); + cmd.hdr.unitId = RM_SOE_UNIT_SMBPBI; + cmd.hdr.size = RM_SOE_CMD_SIZE(SMBPBI, LOG_MESSAGE); + cmd.cmd.smbpbiCmd.cmdType = RM_SOE_SMBPBI_CMD_ID_LOG_MESSAGE; + + msglen = NV_MIN(msglen, RM_SOE_SMBPBI_CMD_LOG_MESSAGE_MAX_STRING); + + pLogCmd->sxidId = num; + pLogCmd->msgLen = msglen; + pLogCmd->timeStamp = nvswitch_os_get_platform_time() / NVSWITCH_NSEC_PER_SEC; + + for (offset = 0; msglen > 0; offset += segSize) + { + segSize = NV_MIN(msglen, RM_SOE_SMBPBI_CMD_LOG_MESSAGE_STRING_SEGMENT_SZ); + nvswitch_os_memcpy(pLogCmd->errorString, osErrorString + offset, segSize); + + pLogCmd->msgOffset = offset; + pLogCmd->segSize = segSize; + + nvswitch_timeout_create(NVSWITCH_INTERVAL_1SEC_IN_NS, &timeout); + status = flcnQueueCmdPostBlocking(device, pFlcn, + (PRM_FLCN_CMD)&cmd, + NULL, // pMsg - not used for now + NULL, // pPayload - not used for now + SOE_RM_CMDQ_LOG_ID, + &cmdSeqDesc, + &timeout); + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, "%s: SMBPBI Log Message command failed. rc:%d\n", + __FUNCTION__, status); + break; + } + + msglen -= segSize; + } + + pSmbpbi->logMessageNesting = 0; + +nvswitch_smbpbi_log_message_exit: + return; +} + +NvlStatus +nvswitch_smbpbi_send_init_data_ls10 +( + nvswitch_device *device +) +{ + struct smbpbi *pSmbpbi = device->pSmbpbi; + RM_FLCN_CMD_SOE cmd; + RM_SOE_SMBPBI_CMD_INIT_DATA *pInitDataCmd = &cmd.cmd.smbpbiCmd.initData; + NVSWITCH_TIMEOUT timeout; + NvU32 cmdSeqDesc; + FLCN *pFlcn = device->pSoe->pFlcn; + NvlStatus status = NVL_SUCCESS; + + ct_assert(sizeof(NV_VERSION_STRING) <= sizeof(pInitDataCmd->driverVersionString)); + + if (pSmbpbi == NULL) + { + goto nvswitch_smbpbi_send_init_data_exit; + } + + nvswitch_os_memset(&cmd, 0, sizeof(cmd)); + cmd.hdr.unitId = RM_SOE_UNIT_SMBPBI; + cmd.hdr.size = RM_SOE_CMD_SIZE(SMBPBI, INIT_DATA); + cmd.cmd.smbpbiCmd.cmdType = RM_SOE_SMBPBI_CMD_ID_INIT_DATA; + + nvswitch_os_strncpy((char *)pInitDataCmd->driverVersionString, + NV_VERSION_STRING, + sizeof(pInitDataCmd->driverVersionString)); + pInitDataCmd->driverVersionString[sizeof(pInitDataCmd->driverVersionString) - 1] = 0; + + nvswitch_timeout_create(NVSWITCH_INTERVAL_1SEC_IN_NS, &timeout); + status = flcnQueueCmdPostBlocking(device, pFlcn, + (PRM_FLCN_CMD)&cmd, + NULL, // pMsg - not used for now + NULL, // pPayload - not used for now + SOE_RM_CMDQ_LOG_ID, + &cmdSeqDesc, + &timeout); + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, "%s: SMBPBI Init Data command failed. rc:%d\n", + __FUNCTION__, status); + } + else + { + NVSWITCH_PRINT(device, INFO, "%s: SMBPBI Init Data sent to SOE.\n", + __FUNCTION__); + } + +nvswitch_smbpbi_send_init_data_exit: + return status; +} + +void +nvswitch_smbpbi_send_unload_ls10 +( + nvswitch_device *device +) +{ +} + +void +nvswitch_smbpbi_dem_flush_ls10 +( + nvswitch_device *device +) +{ +} diff --git a/src/common/nvswitch/kernel/ls10/soe_ls10.c b/src/common/nvswitch/kernel/ls10/soe_ls10.c new file mode 100644 index 000000000..c8ee570c6 --- /dev/null +++ b/src/common/nvswitch/kernel/ls10/soe_ls10.c @@ -0,0 +1,1128 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "soe/soe_nvswitch.h" +#include "soe/soe_priv_nvswitch.h" + +#include "rmlsfm.h" + +#include "nvlink_export.h" + +#include "common_nvswitch.h" +#include "ls10/ls10.h" +#include "ls10/soe_ls10.h" +#include "lr10/soe_lr10.h" + +#include "nvswitch/ls10/dev_soe_ip.h" +#include "nvswitch/ls10/dev_soe_ip_addendum.h" +#include "nvswitch/ls10/dev_falcon_v4.h" +#include "nvswitch/ls10/dev_nvlsaw_ip.h" +#include "nvswitch/ls10/dev_nvlsaw_ip_addendum.h" +#include "nvswitch/ls10/dev_riscv_pri.h" + +#include "nvswitch/ls10/dev_nport_ip.h" +#include "nvswitch/ls10/dev_npg_ip.h" + +#include "flcn/flcnable_nvswitch.h" +#include "flcn/flcn_nvswitch.h" +#include "rmflcncmdif_nvswitch.h" +#include "soe/soeifcmn.h" + +/** + * @brief Sets pEngDescUc and pEngDescBc to the discovered + * engine that matches this flcnable instance + * + * @param[in] device nvswitch_device pointer + * @param[in] pSoe SOE pointer + * @param[out] pEngDescUc pointer to the UniCast Engine + * Descriptor + * @param[out] pEngDescBc pointer to the BroadCast Engine + * Descriptor + */ +static void +_soeFetchEngines_LS10 +( + nvswitch_device *device, + FLCNABLE *pSoe, + ENGINE_DESCRIPTOR_TYPE *pEngDescUc, + ENGINE_DESCRIPTOR_TYPE *pEngDescBc +) +{ + pEngDescUc->initialized = NV_FALSE; + if (NVSWITCH_ENG_IS_VALID(device, SOE, 0)) + { + pEngDescUc->base = NVSWITCH_GET_ENG(device, SOE, , 0); + } + else + { + pEngDescUc->base = 0; + } + + pEngDescBc->initialized = NV_FALSE; + pEngDescBc->base = 0; +} + +/* + * @Brief : Send a test command to SOE + * + * @param device The nvswitch device + */ +static NV_STATUS +_nvswitch_soe_send_test_cmd +( + nvswitch_device *device +) +{ + RM_FLCN_CMD_SOE cmd; + NVSWITCH_TIMEOUT timeout; + NvU32 cmdSeqDesc; + NV_STATUS status; + + FLCN *pFlcn = device->pSoe->pFlcn; + + nvswitch_os_memset(&cmd, 0, sizeof(cmd)); + + cmd.hdr.unitId = RM_SOE_UNIT_NULL; + // sending nothing but a header for UNIT_NULL + cmd.hdr.size = RM_FLCN_QUEUE_HDR_SIZE; + + nvswitch_timeout_create(NVSWITCH_INTERVAL_1SEC_IN_NS * 5, &timeout); + status = flcnQueueCmdPostBlocking(device, pFlcn, + (PRM_FLCN_CMD)&cmd, + NULL, // pMsg - not used for now + NULL, // pPayload - not used for now + SOE_RM_CMDQ_LOG_ID, + &cmdSeqDesc, + &timeout); + + NVSWITCH_ASSERT(status == NVL_SUCCESS); + return status; +} + +#if defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS) +/*! + * Helper function to dump some registers for debug. + * + * @param[in] device nvswitch_device pointer + */ +static void +dumpDebugRegisters +( + nvswitch_device *device +) +{ + FLCN *pFlcn = device->pSoe->pFlcn; + + NvU32 regOS = flcnRegRead_HAL(device, pFlcn, NV_PFALCON_FALCON_OS); + NvU32 regPC = flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_RPC); + NvU32 regCPUCTL = flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_CPUCTL); + NvU32 regIDLESTATE = flcnRegRead_HAL(device, pFlcn, NV_PFALCON_FALCON_IDLESTATE); + NvU32 regMAILBOX0 = flcnRegRead_HAL(device, pFlcn, NV_PFALCON_FALCON_MAILBOX0); + NvU32 regMAILBOX1 = flcnRegRead_HAL(device, pFlcn, NV_PFALCON_FALCON_MAILBOX1); + NvU32 regIRQSTAT = flcnRegRead_HAL(device, pFlcn, NV_PFALCON_FALCON_IRQSTAT); + NvU32 regIRQMODE = flcnRegRead_HAL(device, pFlcn, NV_PFALCON_FALCON_IRQMODE); + NvU32 regIRQMASK = flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_IRQMASK); + NvU32 regIRQDEST = flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_IRQDEST); + NvU32 regIRQDELEG = flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_IRQDELEG); + NvU32 regDMACTL = flcnRegRead_HAL(device, pFlcn, NV_PFALCON_FALCON_DMACTL); + NvU32 regDMATRFCMD = flcnRegRead_HAL(device, pFlcn, NV_PFALCON_FALCON_DMATRFCMD); + NvU32 regDMATRFBASE = flcnRegRead_HAL(device, pFlcn, NV_PFALCON_FALCON_DMATRFBASE); + NvU32 regDMATRFMOFFS = flcnRegRead_HAL(device, pFlcn, NV_PFALCON_FALCON_DMATRFMOFFS); + NvU32 regDMATRFFBOFFS = flcnRegRead_HAL(device, pFlcn, NV_PFALCON_FALCON_DMATRFFBOFFS); + NvU32 regPRIVERR_STAT = flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_PRIV_ERR_STAT); + NvU32 regPRIVERR_INFO = flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_PRIV_ERR_INFO); + NvU32 regPRIVERR_ADDR_HI = flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_PRIV_ERR_ADDR_HI); + NvU32 regPRIVERR_ADDR_LO = flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_PRIV_ERR_ADDR); + NvU32 regHUBERR_STAT = flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_HUB_ERR_STAT); + NvU32 regBCR_CTRL = flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_BCR_CTRL); + NvU32 regRESET_PLM = flcnRegRead_HAL(device, pFlcn, NV_PFALCON_FALCON_RESET_PRIV_LEVEL_MASK); + NvU32 regEXE_PLM = flcnRegRead_HAL(device, pFlcn, NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK); + + NVSWITCH_PRINT(device, ERROR, "Peregrine Registers:\n"); + NVSWITCH_PRINT(device, ERROR, "OS : 0x%08x\n", regOS); + NVSWITCH_PRINT(device, ERROR, "PC (lo32) : 0x%08x\n", regPC); + NVSWITCH_PRINT(device, ERROR, "CPUCTL : 0x%08x\n", regCPUCTL); + NVSWITCH_PRINT(device, ERROR, "IDLESTATE : 0x%08x\n", regIDLESTATE); + NVSWITCH_PRINT(device, ERROR, "MAILBOX0 : 0x%08x\n", regMAILBOX0); + NVSWITCH_PRINT(device, ERROR, "MAILBOX1 : 0x%08x\n", regMAILBOX1); + NVSWITCH_PRINT(device, ERROR, "IRQSTAT : 0x%08x\n", regIRQSTAT); + NVSWITCH_PRINT(device, ERROR, "IRQMODE : 0x%08x\n", regIRQMODE); + NVSWITCH_PRINT(device, ERROR, "IRQMASK : 0x%08x\n", regIRQMASK); + NVSWITCH_PRINT(device, ERROR, "IRQDEST : 0x%08x\n", regIRQDEST); + NVSWITCH_PRINT(device, ERROR, "IRQDELEG : 0x%08x\n", regIRQDELEG); + NVSWITCH_PRINT(device, ERROR, "DMACTL : 0x%08x\n", regDMACTL); + NVSWITCH_PRINT(device, ERROR, "DMATRFCMD : 0x%08x\n", regDMATRFCMD); + NVSWITCH_PRINT(device, ERROR, "DMATRFBASE : 0x%08x\n", regDMATRFBASE); + NVSWITCH_PRINT(device, ERROR, "DMATRFMOFFS : 0x%08x\n", regDMATRFMOFFS); + NVSWITCH_PRINT(device, ERROR, "DMATRFFBOFFS : 0x%08x\n", regDMATRFFBOFFS); + NVSWITCH_PRINT(device, ERROR, "PRIVERR_STAT : 0x%08x\n", regPRIVERR_STAT); + NVSWITCH_PRINT(device, ERROR, "PRIVERR_INFO : 0x%08x\n", regPRIVERR_INFO); + NVSWITCH_PRINT(device, ERROR, "PRIVERR_ADDR : 0x%08x%08x\n", regPRIVERR_ADDR_HI, regPRIVERR_ADDR_LO); + NVSWITCH_PRINT(device, ERROR, "HUBERR_STAT : 0x%08x\n", regHUBERR_STAT); + NVSWITCH_PRINT(device, ERROR, "BCR_CTRL : 0x%08x\n", regBCR_CTRL); + NVSWITCH_PRINT(device, ERROR, "RESET_PLM : 0x%08x\n", regRESET_PLM); + NVSWITCH_PRINT(device, ERROR, "EXE_PLM : 0x%08x\n", regEXE_PLM); +} +#endif // defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS) + +/* + * @Brief : Attach or Detach driver to SOE Queues + * + * @param[in] device + */ +static void +_nvswitch_soe_attach_detach_driver_ls10 +( + nvswitch_device *device, + NvBool bAttach +) +{ + NvU32 val; + + val = NVSWITCH_SAW_RD32_LS10(device, _NVLSAW, _DRIVER_ATTACH_DETACH); + + if (bAttach) + { + val = FLD_SET_DRF(_NVLSAW, _DRIVER_ATTACH_DETACH, _STATUS, + _ATTACHED, val); + } + else + { + val = FLD_SET_DRF(_NVLSAW, _DRIVER_ATTACH_DETACH, _STATUS, + _DETACHED, val); + } + + NVSWITCH_SAW_WR32_LS10(device, _NVLSAW, _DRIVER_ATTACH_DETACH, val); +} + +/* + * @Brief : Returns if SOE is attached to the Queues + * + * @param[in] device + */ +static NvBool +_nvswitch_is_soe_attached_ls10 +( + nvswitch_device *device +) +{ + NvU32 val; + + val = NVSWITCH_SAW_RD32_LS10(device, _NVLSAW, _SOE_ATTACH_DETACH); + + return FLD_TEST_DRF(_NVLSAW, _SOE_ATTACH_DETACH, _STATUS, _ATTACHED, val); +} + +// BACK UP Nport state and reset NPORT +NvlStatus +nvswitch_soe_issue_nport_reset_ls10 +( + nvswitch_device *device, + NvU32 nport +) +{ + FLCN *pFlcn = device->pSoe->pFlcn; + NvU32 cmdSeqDesc = 0; + NV_STATUS status; + RM_FLCN_CMD_SOE cmd; + NVSWITCH_TIMEOUT timeout; + RM_SOE_CORE_CMD_NPORT_RESET *pNportReset; + + nvswitch_os_memset(&cmd, 0, sizeof(cmd)); + + cmd.hdr.unitId = RM_SOE_UNIT_CORE; + cmd.hdr.size = RM_SOE_CMD_SIZE(CORE, NPORT_RESET); + + pNportReset = &cmd.cmd.core.nportReset; + pNportReset->nport = nport; + pNportReset->cmdType = RM_SOE_CORE_CMD_ISSUE_NPORT_RESET; + + nvswitch_timeout_create(NVSWITCH_INTERVAL_1SEC_IN_NS * 5, &timeout); + status = flcnQueueCmdPostBlocking(device, pFlcn, + (PRM_FLCN_CMD)&cmd, + NULL, // pMsg + NULL, // pPayload + SOE_RM_CMDQ_LOG_ID, + &cmdSeqDesc, + &timeout); + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed to send NPORT RESET command to SOE status 0x%x\n", + __FUNCTION__, status); + return -NVL_ERR_INVALID_STATE; + } + + return NVL_SUCCESS; +} + +// De-reset NPORT and restore NPORT state +NvlStatus +nvswitch_soe_restore_nport_state_ls10 +( + nvswitch_device *device, + NvU32 nport +) +{ + FLCN *pFlcn = device->pSoe->pFlcn; + NvU32 cmdSeqDesc = 0; + NV_STATUS status; + RM_FLCN_CMD_SOE cmd; + NVSWITCH_TIMEOUT timeout; + RM_SOE_CORE_CMD_NPORT_STATE *pNportState; + + nvswitch_os_memset(&cmd, 0, sizeof(cmd)); + + cmd.hdr.unitId = RM_SOE_UNIT_CORE; + cmd.hdr.size = sizeof(cmd); + + pNportState = &cmd.cmd.core.nportState; + pNportState->nport = nport; + pNportState->cmdType = RM_SOE_CORE_CMD_RESTORE_NPORT_STATE; + + nvswitch_timeout_create(NVSWITCH_INTERVAL_1SEC_IN_NS * 5, &timeout); + status = flcnQueueCmdPostBlocking(device, pFlcn, + (PRM_FLCN_CMD)&cmd, + NULL, // pMsg + NULL, // pPayload + SOE_RM_CMDQ_LOG_ID, + &cmdSeqDesc, + &timeout); + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed to send NPORT BACKUP command to SOE status 0x%x\n", + __FUNCTION__, status); + return -NVL_ERR_INVALID_STATE; + } + + return NVL_SUCCESS; +} + +/* + * @Brief : Set NPORT TPROD state in SOE + * + * @param[in] device + * @param[in] nport + */ +NvlStatus +nvswitch_set_nport_tprod_state_ls10 +( + nvswitch_device *device, + NvU32 nport +) +{ + FLCN *pFlcn = device->pSoe->pFlcn; + NvU32 cmdSeqDesc = 0; + NV_STATUS status; + RM_FLCN_CMD_SOE cmd; + NVSWITCH_TIMEOUT timeout; + RM_SOE_CORE_CMD_NPORT_TPROD_STATE *nportTprodState; + + nvswitch_os_memset(&cmd, 0, sizeof(cmd)); + + cmd.hdr.unitId = RM_SOE_UNIT_CORE; + cmd.hdr.size = RM_SOE_CMD_SIZE(CORE, NPORT_STATE); + + nportTprodState = &cmd.cmd.core.nportTprodState; + nportTprodState->nport = nport; + nportTprodState->cmdType = RM_SOE_CORE_CMD_SET_NPORT_TPROD_STATE; + + nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout); + status = flcnQueueCmdPostBlocking(device, pFlcn, + (PRM_FLCN_CMD)&cmd, + NULL, // pMsg + NULL, // pPayload + SOE_RM_CMDQ_LOG_ID, + &cmdSeqDesc, + &timeout); + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed to send NPORT SET_TPROD_STATE command to SOE, status 0x%x\n", + __FUNCTION__, status); + return -NVL_ERR_INVALID_STATE; + } + + return NVL_SUCCESS; +} + +/* + * @Brief : Init sequence for SOE FSP RISCV image + * + * The driver assumes SOE is already booted by FSP. + * Driver checks for SOE state and handshakes with a test command. + * If FSP or SOE fails to boot, driver fails and quits. + * + * @param[in] nvswitch device + */ +NvlStatus +nvswitch_init_soe_ls10 +( + nvswitch_device *device +) +{ + NvlStatus status; + NvU32 data; + FLCN *pFlcn = device->pSoe->pFlcn; + + // + // Check if SOE has halted unexpectedly. + // + // The explicit check is required because the interrupts + // are not yet enabled as the device is still initializing. + // + if (soeIsCpuHalted_HAL(device, ((PSOE)pFlcn->pFlcnable))) + { + NVSWITCH_PRINT(device, ERROR, + "%s: SOE halted\n", + __FUNCTION__); + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_BOOTSTRAP, + "SOE init Failed(0)\n"); + status = -NVL_ERR_INVALID_STATE; + goto nvswitch_init_soe_fail; + } + + // Check for SOE BOOT SUCCESS + data = flcnRegRead_HAL(device, pFlcn, NV_PFALCON_FALCON_MAILBOX1); + if (data != SOE_BOOTSTRAP_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: SOE boot failed\n", + __FUNCTION__); + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_BOOTSTRAP, + "SOE init failed(1)\n"); + status = -NVL_ERR_INVALID_STATE; + goto nvswitch_init_soe_fail; + } + + // Register SOE callbacks + status = nvswitch_soe_register_event_callbacks(device); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_COMMAND_QUEUE, + "Failed to register SOE events\n"); + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_BOOTSTRAP, + "SOE init failed(2)\n"); + return status; + } + + // Sanity the command and message queues as a final check + if (_nvswitch_soe_send_test_cmd(device) != NV_OK) + { + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_BOOTSTRAP, + "SOE init failed(2)\n"); + status = -NVL_ERR_INVALID_STATE; + goto nvswitch_init_soe_fail; + } + + NVSWITCH_PRINT(device, SETUP, + "%s: SOE successfully bootstrapped.\n", + __FUNCTION__); + + return NVL_SUCCESS; + +nvswitch_init_soe_fail : + // Log any failures SOE may have had during bootstrap + (void)soeService_HAL(device, ((PSOE)pFlcn->pFlcnable)); +#if defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS) + dumpDebugRegisters(device); +#endif // defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS) + + flcnDbgInfoCapturePcTrace_HAL(device, pFlcn); + NVSWITCH_ASSERT(0); + return status; +} + +/* + * @Brief : Shutdown SOE during driver unload + * + * @param[in] device Bootstrap SOE on this device + */ +NvlStatus +nvswitch_unload_soe_ls10 +( + nvswitch_device *device +) +{ + // Detach driver from SOE Queues + _nvswitch_soe_attach_detach_driver_ls10(device, NV_FALSE); + + return NVL_SUCCESS; +} + +/*! + * @brief : Register callback functions for events and messages from SOE + * + * @param[in] device nvswitch_device pointer + */ +NvlStatus +nvswitch_soe_register_event_callbacks_ls10 +( + nvswitch_device *device +) +{ + + NV_STATUS status; + PFLCN pFlcn = device->pSoe->pFlcn; + PSOE pSoe = (PSOE)device->pSoe; + + // Register Thermal callback funcion + status = flcnQueueEventRegister( + device, pFlcn, + RM_SOE_UNIT_THERM, + NULL, + nvswitch_therm_soe_callback_lr10, + NULL, + &pSoe->thermEvtDesc); + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to register thermal event handler.\n", + __FUNCTION__); + return -NVL_ERR_INVALID_STATE; + } + + return NVL_SUCCESS; +} + +void +nvswitch_soe_unregister_events_ls10 +( + nvswitch_device *device +) +{ + PFLCN pFlcn = device->pSoe->pFlcn; + PSOE pSoe = (PSOE)device->pSoe; + NV_STATUS status; + + // un-register thermal callback funcion + status = flcnQueueEventUnregister(device, pFlcn, + pSoe->thermEvtDesc); + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to un-register thermal event handler.\n", + __FUNCTION__); + } +} + +/*! + * @brief Determine if the SOE RISCV CPU is halted + * + * @param[in] device nvswitch_device pointer + * @param[in] pSoe SOE pointer + * + * @return NvBool reflecting the SOE Riscv CPU halted state + */ +static NvBool +_soeIsCpuHalted_LS10 +( + nvswitch_device *device, + PSOE pSoe +) +{ + NvU32 data; + + data = NVSWITCH_SOE_RD32_LS10(device, 0, _SOE_RISCV, _CPUCTL); + return FLD_TEST_DRF(_PFALCON, _FALCON_CPUCTL, _HALTED, _TRUE, data); +} + +static NvU32 +_soeIntrStatus_LS10 +( + nvswitch_device *device +) +{ + NvU32 irq, mask, dest; + + irq = NVSWITCH_SOE_RD32_LS10(device, 0, _SOE_FALCON, _IRQSTAT); + mask = NVSWITCH_SOE_RD32_LS10(device, 0, _SOE_RISCV, _IRQMASK); + dest = NVSWITCH_SOE_RD32_LS10(device, 0, _SOE_RISCV, _IRQDEST); + + return (irq & mask & dest); +} + +/*! + * @brief Top level service routine + * + * @param[in] device nvswitch_device pointer + * @param[in] pSoe SOE pointer + * + * @return 32-bit interrupt status AFTER all known interrupt-sources were + * serviced. + */ +static NvU32 +_soeService_LS10 +( + nvswitch_device *device, + PSOE pSoe +) +{ + NvBool bRecheckMsgQ = NV_FALSE; + NvU32 clearBits = 0; + NvU32 intrStatus; + PFLCN pFlcn = ENG_GET_FLCN(pSoe); + + if (pFlcn == NULL) + { + NVSWITCH_ASSERT(0); + return NV_ERR_INVALID_ARGUMENT; + } + + // Get the IRQ status and mask the sources not directed to host. + intrStatus = _soeIntrStatus_LS10(device); + + // Exit if there is nothing to do + if (intrStatus == 0) + { + return 0; + } + + // Service pending interrupts + if (intrStatus & DRF_DEF(_PFALCON, _FALCON_IRQSTAT, _WDTMR, _TRUE)) + { + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_WATCHDOG, + "SOE Watchdog error\n"); + NVSWITCH_PRINT(device, INFO, + "%s: Watchdog timer fired. We do not support this " + "yet.\n", __FUNCTION__); + NVSWITCH_ASSERT(0); + + clearBits |= DRF_DEF(_PFALCON, _FALCON_IRQSCLR, _WDTMR, _SET); + } + + if (intrStatus & DRF_DEF(_PFALCON, _FALCON_IRQSTAT, _EXTERR, _TRUE)) + { + clearBits |= DRF_DEF(_PFALCON, _FALCON_IRQSCLR, _EXTERR, _SET); + + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_EXTERR, "SOE EXTERR\n"); + } + + if (intrStatus & DRF_DEF(_PFALCON, _FALCON_IRQSTAT, _HALT, _TRUE)) + { + clearBits |= DRF_DEF(_PFALCON, _FALCON_IRQSCLR, _HALT, _SET); + + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_HALT, "SOE HALTED\n"); + soeServiceHalt_HAL(device, pSoe); + } + + if (intrStatus & DRF_DEF(_PFALCON, _FALCON_IRQSTAT, _SWGEN0, _TRUE)) + { + clearBits |= DRF_DEF(_PFALCON, _FALCON_IRQSCLR, _SWGEN0, _SET); + + NVSWITCH_PRINT(device, MMIO, + "%s: Received a message from SOE via SWGEN0\n", + __FUNCTION__); + soeProcessMessages_HAL(device, pSoe); + bRecheckMsgQ = NV_TRUE; + } + + if (intrStatus & DRF_DEF(_PFALCON, _FALCON_IRQSTAT, _SWGEN1, _TRUE)) + { + clearBits |= DRF_DEF(_PFALCON, _FALCON_IRQSCLR, _SWGEN1, _SET); + + NVSWITCH_PRINT(device, INFO, + "%s: Received a SWGEN1 interrupt\n", + __FUNCTION__); + } + + // Clear any sources that were serviced and get the new status. + flcnRegWrite_HAL(device, pFlcn, NV_PFALCON_FALCON_IRQSCLR, clearBits); + + // Re-read interrupt status before retriggering to return correct value + intrStatus = _soeIntrStatus_LS10(device); + + // + // If we just processed a SWGEN0 message queue interrupt, peek + // into the message queue and see if any messages were missed the last time + // the queue was purged (above). If it is not empty, re-generate SWGEN0 + // (since it is now cleared) and exit. As long as an interrupt is pending, + // this function will be re-entered and the message(s) will be processed. + // + if (bRecheckMsgQ) + { + PFALCON_QUEUE_INFO pQueueInfo; + FLCNQUEUE *pMsgQ; + + pQueueInfo = pFlcn->pQueueInfo; + + NVSWITCH_ASSERT(pQueueInfo != NULL); + NVSWITCH_ASSERT(pQueueInfo->pQueues != NULL); + + pMsgQ = &pQueueInfo->pQueues[SOE_RM_MSGQ_LOG_ID]; + + if (!pMsgQ->isEmpty(device, pFlcn, pMsgQ)) + { + // It is not necessary to RMW IRQSSET (zeros are ignored) + flcnRegWrite_HAL(device, pFlcn, NV_PFALCON_FALCON_IRQSSET, + DRF_DEF(_PFALCON, _FALCON_IRQSSET, _SWGEN0, _SET)); + } + } + + flcnIntrRetrigger_HAL(device, pFlcn); + + return intrStatus; +} + +/*! + * Called by soeService to handle a SOE halt. This function will dump the + * current status of SOE and then trap the CPU for further inspection for a + * debug build. + * + * @param[in] device nvswitch_device pointer + * @param[in] pSoe SOE object pointer + */ +static void +_soeServiceHalt_LS10 +( + nvswitch_device *device, + PSOE pSoe +) +{ + PFLCN pFlcn = ENG_GET_FLCN(pSoe); + + NVSWITCH_PRINT(device, ERROR, + "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n" + "!! ** SOE HALTED ** !!\n" + "!! Please file a bug with the following information. !!\n" + "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n\n"); + +#if defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS) + dumpDebugRegisters(device); +#endif // defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS) + + flcnDbgInfoCaptureRiscvPcTrace_HAL(device, pFlcn); + NVSWITCH_ASSERT(0); +} + +/*! + * Use the SOE INIT Message to construct, initialize or update SOE Queues. + * + * @param[in] device nvswitch_device pointer + * @param[in] pSoe SOE object pointer + * + * @return 'NV_OK' upon successful creation of all SOE Queues + */ +static NV_STATUS +_soeUpdateInitMsgQueuesInfo +( + nvswitch_device *device, + PSOE pSoe +) +{ + FLCNQUEUE *pQueue; + PFLCN pFlcn = ENG_GET_FLCN(pSoe); + PFALCON_QUEUE_INFO pQueueInfo; + NvU32 queueOffset; + NvU16 queueSize; + NvU8 queuePhyId; + NvU8 queueLogId; + NV_STATUS status; + + // + // No command should be longer than half the queue size. + // See _soeQueueCmdValidate_IMPL(). + // + ct_assert(sizeof(RM_FLCN_CMD_SOE) <= (SOE_CMD_QUEUE_LENGTH / 2)); + + NVSWITCH_ASSERT(pFlcn != NULL); + + pQueueInfo = pFlcn->pQueueInfo; + NVSWITCH_ASSERT(pQueueInfo != NULL); + + // Construct DMEM for CMDQ + queueOffset = SOE_EMEM_CHANNEL_CMDQ_OFFSET; + queueSize = SOE_CMD_QUEUE_LENGTH; + queuePhyId = 0; + queueLogId = SOE_RM_CMDQ_LOG_ID; + pQueue = &pQueueInfo->pQueues[queueLogId]; + status = flcnQueueConstruct_dmem_nvswitch( + device, + pFlcn, + &pQueue, // ppQueue + queueLogId, // Logical ID of the queue + queuePhyId, // Physical ID of the queue + queueOffset, // offset + queueSize, // size + RM_FLCN_QUEUE_HDR_SIZE); // cmdHdrSize + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Error constructing SOE CmdQueue (status=" + "0x%08x).\n", __FUNCTION__, status); + NVSWITCH_ASSERT(0); + return status; + } + + // Construct DMEM for MSGQ + queueOffset = SOE_EMEM_CHANNEL_MSGQ_OFFSET; + queueSize = SOE_MSG_QUEUE_LENGTH; + queuePhyId = 0; + queueLogId = SOE_RM_MSGQ_LOG_ID; + pQueue = &pQueueInfo->pQueues[queueLogId]; + status = flcnQueueConstruct_dmem_nvswitch( + device, + pFlcn, + &pQueue, // ppQueue + queueLogId, // Logical ID of the queue + queuePhyId, // Physical ID of the queue + queueOffset, // offset + queueSize, // size + RM_FLCN_QUEUE_HDR_SIZE); // cmdHdrSize + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Error constructing SOE MsgQueue (status=" + "0x%08x).\n", __FUNCTION__, status); + NVSWITCH_ASSERT(0); + return status; + } + + pFlcn->bOSReady = NV_TRUE; + + return NV_OK; +} + +static NV_STATUS +_soeWaitForInitAck_LS10 +( + nvswitch_device *device, + PSOE pSoe +) +{ + NV_STATUS status; + PFLCN pFlcn = ENG_GET_FLCN(pSoe); + + if (!_nvswitch_is_soe_attached_ls10(device)) + { + NVSWITCH_PRINT(device, ERROR, + "%s SOE is not to attached!\n", + __FUNCTION__); + NVSWITCH_ASSERT(0); + return NV_ERR_NOT_READY; + } + + // Update InitMsg Queue info before sending any commands + if (!pFlcn->bOSReady) + { + status = _soeUpdateInitMsgQueuesInfo(device, pSoe); + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, + "%s Failed to attach driver!\n", + __FUNCTION__); + NVSWITCH_ASSERT(0); + return status; + } + + // Attach driver to SOE Queues + _nvswitch_soe_attach_detach_driver_ls10(device, NV_TRUE); + } + + return NV_OK; +} + +/*! + * Purges all the messages from the SOE's message queue. Each message will + * be analyzed, clients will be notified of status, and events will be routed + * to all registered event listeners. + * + * @param[in] device nvswitch_device pointer + * @param[in] pSoe SOE object pointer + * + * @return 'NV_OK' if the message queue was successfully purged. + */ +static NV_STATUS +_soeProcessMessages_LS10 +( + nvswitch_device *device, + PSOE pSoe +) +{ + RM_FLCN_MSG_SOE soeMessage; + NV_STATUS status; + PFLCN pFlcn = ENG_GET_FLCN(pSoe); + + // Update InitMsg Queue info before recieving any messages + if (!pFlcn->bOSReady) + { + status = _soeUpdateInitMsgQueuesInfo(device, pSoe); + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, + "%s Failed to attach driver!\n", + __FUNCTION__); + NVSWITCH_ASSERT(0); + return status; + } + + // Attach driver to SOE Queues + _nvswitch_soe_attach_detach_driver_ls10(device, NV_TRUE); + } + + + // keep processing messages until no more exist in the message queue + while (NV_OK == (status = flcnQueueReadData( + device, + pFlcn, + SOE_RM_MSGQ_LOG_ID, + (RM_FLCN_MSG *)&soeMessage, NV_TRUE))) + { + NVSWITCH_PRINT(device, MMIO, + "%s: unitId=0x%02x, size=0x%02x, ctrlFlags=0x%02x, " \ + "seqNumId=0x%02x\n", + __FUNCTION__, + soeMessage.hdr.unitId, + soeMessage.hdr.size, + soeMessage.hdr.ctrlFlags, + soeMessage.hdr.seqNumId); + + // check to see if the message is a reply or an event. + if ((soeMessage.hdr.ctrlFlags &= RM_FLCN_QUEUE_HDR_FLAGS_EVENT) != 0) + { + flcnQueueEventHandle(device, pFlcn, (RM_FLCN_MSG *)&soeMessage, NV_OK); + } + // the message is a response from a previously queued command + else + { + flcnQueueResponseHandle(device, pFlcn, (RM_FLCN_MSG *)&soeMessage); + } + } + + // + // Status NV_ERR_NOT_READY implies, Queue is empty. + // Log the message in other error cases. + // + if (status != NV_ERR_NOT_READY) + { + NVSWITCH_PRINT(device, ERROR, + "%s: unexpected error while purging message queue (status=0x%x).\n", + __FUNCTION__, (status)); + } + + return status; +} + +static NV_STATUS +_soeHandleInitEvent_LS10 +( + nvswitch_device *device, + PFLCNABLE pSoe, + RM_FLCN_MSG *pGenMsg +) +{ + NVSWITCH_PRINT(device, ERROR, + "%s: Init handle event not Supported!\n", + __FUNCTION__); + NVSWITCH_ASSERT(0); + return NV_ERR_GENERIC; +} + +static NvlStatus +_soeI2CAccessSend +( + nvswitch_device *device, + void *cpuAddr, + NvU64 dmaHandle, + NvU16 xferSize +) +{ + FLCN *pFlcn = device->pSoe->pFlcn; + NvU32 cmdSeqDesc; + NV_STATUS status; + RM_FLCN_CMD_SOE cmd; + RM_SOE_CORE_CMD_I2C *pI2cCmd; + NVSWITCH_TIMEOUT timeout; + + nvswitch_os_memset(&cmd, 0, sizeof(cmd)); + + cmd.hdr.unitId = RM_SOE_UNIT_CORE; + cmd.hdr.size = RM_SOE_CMD_SIZE(CORE, I2C); + + pI2cCmd = &cmd.cmd.core.i2c; + RM_FLCN_U64_PACK(&pI2cCmd->dmaHandle, &dmaHandle); + pI2cCmd->xferSize = xferSize; + pI2cCmd->cmdType = RM_SOE_CORE_CMD_I2C_ACCESS; + + cmdSeqDesc = 0; + + nvswitch_timeout_create(NVSWITCH_INTERVAL_1SEC_IN_NS * 5, &timeout); + status = flcnQueueCmdPostBlocking(device, pFlcn, + (PRM_FLCN_CMD)&cmd, + NULL, // pMsg + NULL, // pPayload + SOE_RM_CMDQ_LOG_ID, + &cmdSeqDesc, + &timeout); + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed to send I2C command to SOE status 0x%x\n", + __FUNCTION__, status); + return -NVL_ERR_INVALID_STATE; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_soeI2cFlcnStatusToNvlStatus +( + NvU8 flcnStatus +) +{ + switch (flcnStatus) + { + case FLCN_OK: + return NVL_SUCCESS; + case FLCN_ERR_INVALID_ARGUMENT: + return -NVL_BAD_ARGS; + case FLCN_ERR_OBJECT_NOT_FOUND: + return -NVL_NOT_FOUND; + case FLCN_ERROR: + return -NVL_ERR_GENERIC; + case FLCN_ERR_INVALID_STATE: + return -NVL_ERR_INVALID_STATE; + case FLCN_ERR_MORE_PROCESSING_REQUIRED: + return -NVL_MORE_PROCESSING_REQUIRED; + case FLCN_ERR_TIMEOUT: + return -NVL_IO_ERROR; + case FLCN_ERR_I2C_BUSY: + return -NVL_ERR_STATE_IN_USE; + case FLCN_ERR_NOT_SUPPORTED: + return -NVL_ERR_NOT_SUPPORTED; + default: + return -NVL_ERR_GENERIC; + } +} + +static NvlStatus +_soeI2CAccess_LS10 +( + nvswitch_device *device, + NVSWITCH_CTRL_I2C_INDEXED_PARAMS *pParams +) +{ + NvlStatus ret; + NvU8 flcnRet; + PNVSWITCH_OBJI2C pI2c; + void *pCpuAddr; + NvU64 dmaHandle; + + if (pParams == NULL) + { + return -NVL_BAD_ARGS; + } + + pI2c = device->pI2c; + + if (pI2c == NULL || !pI2c->soeI2CSupported) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + pCpuAddr = pI2c->pCpuAddr; + dmaHandle = pI2c->dmaHandle; + + ret = nvswitch_os_sync_dma_region_for_cpu(device->os_handle, dmaHandle, + SOE_I2C_DMA_BUF_SIZE, + NVSWITCH_DMA_DIR_FROM_SYSMEM); + if (ret != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: nvswitch_os_sync_dma_region_for_cpu returned %d\n", + __FUNCTION__, ret); + return ret; + } + + // Required for error reporting from SOE to driver + ct_assert(sizeof(NVSWITCH_CTRL_I2C_INDEXED_PARAMS) < SOE_I2C_STATUS_INDEX); + + // Copy I2C struct into buffer + nvswitch_os_memcpy(pCpuAddr, pParams, sizeof(NVSWITCH_CTRL_I2C_INDEXED_PARAMS)); + + ret = nvswitch_os_sync_dma_region_for_device(device->os_handle, dmaHandle, + SOE_I2C_DMA_BUF_SIZE, + NVSWITCH_DMA_DIR_FROM_SYSMEM); + if (ret != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: nvswitch_os_sync_dma_region_for_device returned %d\n", + __FUNCTION__, ret); + return ret; + } + + // Send I2C access command to SOE + ret = _soeI2CAccessSend(device, pCpuAddr, dmaHandle, SOE_I2C_DMA_BUF_SIZE); + if (ret != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: _soeI2CAccessSend returned %d\n", + __FUNCTION__, ret); + return ret; + } + + // Get result + ret = nvswitch_os_sync_dma_region_for_cpu(device->os_handle, dmaHandle, + SOE_I2C_DMA_BUF_SIZE, + NVSWITCH_DMA_DIR_TO_SYSMEM); + if (ret != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: nvswitch_os_sync_dma_region_for_cpu returned %d\n", + __FUNCTION__, ret); + return ret; + } + + nvswitch_os_memcpy(pParams, pCpuAddr, sizeof(NVSWITCH_CTRL_I2C_INDEXED_PARAMS)); + + // Return value of the I2C operation that was performed in SOE + flcnRet = ((NvU8*)pCpuAddr)[SOE_I2C_STATUS_INDEX]; + ret = _soeI2cFlcnStatusToNvlStatus(flcnRet); + + return ret; +} + +/** + * @brief set hal function pointers for functions defined in LR10 (i.e. this file) + * + * this function has to be at the end of the file so that all the + * other functions are already defined. + * + * @param[in] pFlcnable The flcnable for which to set hals + */ +void +soeSetupHal_LS10 +( + SOE *pSoe +) +{ + soe_hal *pHal = pSoe->base.pHal; + flcnable_hal *pParentHal = (flcnable_hal *)pHal; + + soeSetupHal_LR10(pSoe); + + pParentHal->fetchEngines = _soeFetchEngines_LS10; + pParentHal->handleInitEvent = _soeHandleInitEvent_LS10; + + pHal->isCpuHalted = _soeIsCpuHalted_LS10; + pHal->service = _soeService_LS10; + pHal->serviceHalt = _soeServiceHalt_LS10; + pHal->processMessages = _soeProcessMessages_LS10; + pHal->waitForInitAck = _soeWaitForInitAck_LS10; + pHal->i2cAccess = _soeI2CAccess_LS10; +} + diff --git a/src/common/nvswitch/kernel/ls10/sugen_ls10.c b/src/common/nvswitch/kernel/ls10/sugen_ls10.c new file mode 100644 index 000000000..ff8781ac5 --- /dev/null +++ b/src/common/nvswitch/kernel/ls10/sugen_ls10.c @@ -0,0 +1,1512 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include "common_nvswitch.h" +#include "ls10/ls10.h" +#include "ls10/sugen_ls10.h" + +// +// AUTO-GENERATED FILE -- DO NOT MODIFY +// This file is automatically generated from SU scripts +// + + +/* + * @Brief : Fill In + * + * @Description : Fill In + * + * @paramin : Fill In + * + */ +#if 0 +NvlStatus +nvswitch_npg_prod_ls10 +( + nvswitch_device *device +) +{ + + + // .NPG PROD value application + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _EGRESS, _ERR_CONTAIN_EN_0, + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _CREDIT_TIME_OUT_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _EGRESSBUFERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _HWRSPERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _INVALIDVCSET_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _NCISOCCREDITOVFL, __PROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _NCISOC_CREDIT_PARITY_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _NXBAR_FLITTYPE_MISMATCH_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _NXBAR_HDR_ECC_DBE_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _NXBAR_HDR_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _NXBAR_HDR_PARITY_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _NXBAR_SIDEBAND_PD_PARITY_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _PKTROUTEERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _PRIVRSPERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _RAM_OUT_HDR_ECC_DBE_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _RAM_OUT_HDR_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _REQTGTIDMISMATCHERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _RFU, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _RSPREQIDMISMATCHERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _SEQIDERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _URRSPERR, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _EGRESS, _ERR_CONTAIN_EN_1, + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_1, _MCREDBUF_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_1, _MCREDBUF_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_1, _MCREDSGT_ECC_DBE_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_1, _MCREDSGT_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_1, _MCRSPCTRLSTORE_ECC_DBE_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_1, _MCRSPCTRLSTORE_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_1, _MCRSP_CNT_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_1, _MCRSP_RAM_HDR_ECC_DBE_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_1, _MCRSP_RAM_HDR_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_1, _NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_1, _NXBAR_REDUCTION_HDR_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_1, _NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_1, _NXBAR_REDUCTION_HDR_PARITY_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_1, _RBCTRLSTORE_ECC_DBE_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_1, _RBCTRLSTORE_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_1, _RBRSP_CNT_ERR, _DISABLE)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _EGRESS, _ERR_ECC_CTRL, + DRF_DEF(_EGRESS, _ERR_ECC_CTRL, _MCREDBUF_ECC_ENABLE, __PROD) | + DRF_DEF(_EGRESS, _ERR_ECC_CTRL, _MCREDSGT_ECC_ENABLE, __PROD) | + DRF_DEF(_EGRESS, _ERR_ECC_CTRL, _MCRSPCTRLSTORE_ECC_ENABLE, __PROD) | + DRF_DEF(_EGRESS, _ERR_ECC_CTRL, _MCRSP_RAM_ECC_ENABLE, __PROD) | + DRF_DEF(_EGRESS, _ERR_ECC_CTRL, _NCISOC_ECC_ENABLE, __PROD) | + DRF_DEF(_EGRESS, _ERR_ECC_CTRL, _NCISOC_PARITY_ENABLE, __PROD) | + DRF_DEF(_EGRESS, _ERR_ECC_CTRL, _NXBAR_ECC_ENABLE, __PROD) | + DRF_DEF(_EGRESS, _ERR_ECC_CTRL, _NXBAR_PARITY_ENABLE, __PROD) | + DRF_DEF(_EGRESS, _ERR_ECC_CTRL, _NXBAR_REDUCTION_ECC_ENABLE, __PROD) | + DRF_DEF(_EGRESS, _ERR_ECC_CTRL, _NXBAR_REDUCTION_PARITY_ENABLE, __PROD) | + DRF_DEF(_EGRESS, _ERR_ECC_CTRL, _NXBAR_SIDEBAND_PD_PARITY_ENABLE, __PROD) | + DRF_DEF(_EGRESS, _ERR_ECC_CTRL, _RAM_OUT_ECC_ENABLE, __PROD) | + DRF_DEF(_EGRESS, _ERR_ECC_CTRL, _RBCTRLSTORE_ECC_ENABLE, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _EGRESS, _ERR_FATAL_REPORT_EN_0, + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _CREDIT_TIME_OUT_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _EGRESSBUFERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _HWRSPERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _INVALIDVCSET_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _NCISOCCREDITOVFL, __PROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _NCISOC_CREDIT_PARITY_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _NXBAR_FLITTYPE_MISMATCH_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _NXBAR_HDR_ECC_DBE_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _NXBAR_HDR_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _NXBAR_HDR_PARITY_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _NXBAR_SIDEBAND_PD_PARITY_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _PKTROUTEERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _PRIVRSPERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _RAM_OUT_HDR_ECC_DBE_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _RAM_OUT_HDR_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _REQTGTIDMISMATCHERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _RFU, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _RSPREQIDMISMATCHERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _SEQIDERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _URRSPERR, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _EGRESS, _ERR_FATAL_REPORT_EN_1, + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_1, _MCREDBUF_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_1, _MCREDBUF_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_1, _MCREDSGT_ECC_DBE_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_1, _MCREDSGT_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_1, _MCRSPCTRLSTORE_ECC_DBE_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_1, _MCRSPCTRLSTORE_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_1, _MCRSP_CNT_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_1, _MCRSP_RAM_HDR_ECC_DBE_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_1, _MCRSP_RAM_HDR_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_1, _NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_1, _NXBAR_REDUCTION_HDR_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_1, _NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_1, _NXBAR_REDUCTION_HDR_PARITY_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_1, _RBCTRLSTORE_ECC_DBE_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_1, _RBCTRLSTORE_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_1, _RBRSP_CNT_ERR, _DISABLE)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _EGRESS, _ERR_LOG_EN_0, + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _CREDIT_TIME_OUT_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _EGRESSBUFERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _HWRSPERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _INVALIDVCSET_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _NCISOCCREDITOVFL, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _NCISOC_CREDIT_PARITY_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _NXBAR_FLITTYPE_MISMATCH_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _NXBAR_HDR_ECC_DBE_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _NXBAR_HDR_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _NXBAR_HDR_PARITY_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _NXBAR_SIDEBAND_PD_PARITY_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _PKTROUTEERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _PRIVRSPERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _RAM_OUT_HDR_ECC_DBE_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _RAM_OUT_HDR_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _REQTGTIDMISMATCHERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _RFU, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _RSPREQIDMISMATCHERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _SEQIDERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _URRSPERR, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _EGRESS, _ERR_LOG_EN_1, + DRF_DEF(_EGRESS, _ERR_LOG_EN_1, _MCREDBUF_ECC_DBE_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_1, _MCREDBUF_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_1, _MCREDSGT_ECC_DBE_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_1, _MCREDSGT_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_1, _MCRSPCTRLSTORE_ECC_DBE_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_1, _MCRSPCTRLSTORE_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_1, _MCRSP_CNT_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_1, _MCRSP_RAM_HDR_ECC_DBE_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_1, _MCRSP_RAM_HDR_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_1, _NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_1, _NXBAR_REDUCTION_HDR_ECC_DBE_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_1, _NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_1, _NXBAR_REDUCTION_HDR_PARITY_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_1, _RBCTRLSTORE_ECC_DBE_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_1, _RBCTRLSTORE_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_1, _RBRSP_CNT_ERR, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _EGRESS, _ERR_NON_FATAL_REPORT_EN_0, + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _CREDIT_TIME_OUT_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EGRESSBUFERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _HWRSPERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _INVALIDVCSET_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _NCISOCCREDITOVFL, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _NCISOC_CREDIT_PARITY_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _NXBAR_FLITTYPE_MISMATCH_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _NXBAR_HDR_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _NXBAR_HDR_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _NXBAR_HDR_PARITY_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _NXBAR_SIDEBAND_PD_PARITY_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _PKTROUTEERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _PRIVRSPERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _RAM_OUT_HDR_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _RAM_OUT_HDR_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _REQTGTIDMISMATCHERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _RFU, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _RSPREQIDMISMATCHERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _SEQIDERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _URRSPERR, _DISABLE)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _EGRESS, _ERR_NON_FATAL_REPORT_EN_1, + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCREDBUF_ECC_DBE_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCREDBUF_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCREDSGT_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCREDSGT_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCRSPCTRLSTORE_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCRSPCTRLSTORE_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCRSP_CNT_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCRSP_RAM_HDR_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCRSP_RAM_HDR_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _NXBAR_REDUCTION_HDR_ECC_DBE_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _NXBAR_REDUCTION_HDR_PARITY_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _RBCTRLSTORE_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _RBCTRLSTORE_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_1, _RBRSP_CNT_ERR, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _INGRESS, _ERR_CONTAIN_EN_0, + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _ACLFAIL, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _ADDRBOUNDSERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _ADDRTYPEERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _CMDDECODEERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _EXTAREMAPTAB_ACLFAIL, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _EXTAREMAPTAB_ADDRBOUNDSERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _EXTAREMAPTAB_ECC_DBE_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _EXTAREMAPTAB_INDEX_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _EXTAREMAPTAB_REQCONTEXTMISMATCHERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _EXTBREMAPTAB_ACLFAIL, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _EXTBREMAPTAB_ADDRBOUNDSERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _EXTBREMAPTAB_ECC_DBE_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _EXTBREMAPTAB_INDEX_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _EXTBREMAPTAB_REQCONTEXTMISMATCHERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _INVALIDVCSET, __PROD) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _MCREMAPTAB_ACLFAIL, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _MCREMAPTAB_ADDRBOUNDSERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _MCREMAPTAB_ECC_DBE_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _MCREMAPTAB_INDEX_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _MCREMAPTAB_REQCONTEXTMISMATCHERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _NCISOC_HDR_ECC_DBE_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _NCISOC_HDR_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _NCISOC_PARITY_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _REMAPTAB_ECC_DBE_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _REMAPTAB_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _REQCONTEXTMISMATCHERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _RIDTABCFGERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _RIDTAB_ECC_DBE_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _RIDTAB_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _RLANTABCFGERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _RLANTAB_ECC_DBE_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _RLANTAB_ECC_LIMIT_ERR, _DISABLE)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _INGRESS, _ERR_ECC_CTRL, + DRF_DEF(_INGRESS, _ERR_ECC_CTRL, _EXTAREMAPTAB_ECC_ENABLE, __PROD) | + DRF_DEF(_INGRESS, _ERR_ECC_CTRL, _EXTBREMAPTAB_ECC_ENABLE, __PROD) | + DRF_DEF(_INGRESS, _ERR_ECC_CTRL, _MCREMAPTAB_ECC_ENABLE, __PROD) | + DRF_DEF(_INGRESS, _ERR_ECC_CTRL, _NCISOC_HDR_ECC_ENABLE, __PROD) | + DRF_DEF(_INGRESS, _ERR_ECC_CTRL, _NCISOC_PARITY_ENABLE, __PROD) | + DRF_DEF(_INGRESS, _ERR_ECC_CTRL, _REMAPTAB_ECC_ENABLE, __PROD) | + DRF_DEF(_INGRESS, _ERR_ECC_CTRL, _RIDTAB_ECC_ENABLE, __PROD) | + DRF_DEF(_INGRESS, _ERR_ECC_CTRL, _RLANTAB_ECC_ENABLE, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _INGRESS, _ERR_FATAL_REPORT_EN_0, + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _ACLFAIL, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _ADDRBOUNDSERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _ADDRTYPEERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _CMDDECODEERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _EXTAREMAPTAB_ACLFAIL, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _EXTAREMAPTAB_ADDRBOUNDSERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _EXTAREMAPTAB_ECC_DBE_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _EXTAREMAPTAB_INDEX_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _EXTAREMAPTAB_REQCONTEXTMISMATCHERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _EXTBREMAPTAB_ACLFAIL, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _EXTBREMAPTAB_ADDRBOUNDSERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _EXTBREMAPTAB_ECC_DBE_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _EXTBREMAPTAB_INDEX_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _EXTBREMAPTAB_REQCONTEXTMISMATCHERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _INVALIDVCSET, __PROD) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _MCREMAPTAB_ACLFAIL, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _MCREMAPTAB_ADDRBOUNDSERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _MCREMAPTAB_ECC_DBE_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _MCREMAPTAB_INDEX_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _MCREMAPTAB_REQCONTEXTMISMATCHERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _NCISOC_HDR_ECC_DBE_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _NCISOC_HDR_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _NCISOC_PARITY_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _REMAPTAB_ECC_DBE_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _REMAPTAB_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _REQCONTEXTMISMATCHERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _RIDTABCFGERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _RIDTAB_ECC_DBE_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _RIDTAB_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _RLANTABCFGERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _RLANTAB_ECC_DBE_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _RLANTAB_ECC_LIMIT_ERR, _DISABLE)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _INGRESS, _ERR_LOG_EN_0, + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _ACLFAIL, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _ADDRBOUNDSERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _ADDRTYPEERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _CMDDECODEERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _EXTAREMAPTAB_ACLFAIL, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _EXTAREMAPTAB_ADDRBOUNDSERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _EXTAREMAPTAB_ECC_DBE_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _EXTAREMAPTAB_INDEX_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _EXTAREMAPTAB_REQCONTEXTMISMATCHERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _EXTBREMAPTAB_ACLFAIL, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _EXTBREMAPTAB_ADDRBOUNDSERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _EXTBREMAPTAB_ECC_DBE_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _EXTBREMAPTAB_INDEX_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _EXTBREMAPTAB_REQCONTEXTMISMATCHERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _INVALIDVCSET, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _MCREMAPTAB_ACLFAIL, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _MCREMAPTAB_ADDRBOUNDSERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _MCREMAPTAB_ECC_DBE_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _MCREMAPTAB_INDEX_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _MCREMAPTAB_REQCONTEXTMISMATCHERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _NCISOC_HDR_ECC_DBE_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _NCISOC_HDR_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _NCISOC_PARITY_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _REMAPTAB_ECC_DBE_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _REMAPTAB_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _REQCONTEXTMISMATCHERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _RIDTABCFGERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _RIDTAB_ECC_DBE_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _RIDTAB_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _RLANTABCFGERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _RLANTAB_ECC_DBE_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _RLANTAB_ECC_LIMIT_ERR, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _INGRESS, _ERR_LOG_EN_1, + DRF_DEF(_INGRESS, _ERR_LOG_EN_1, _EXTAREMAPTAB_ADDRTYPEERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_1, _EXTAREMAPTAB_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_1, _EXTBREMAPTAB_ADDRTYPEERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_1, _EXTBREMAPTAB_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_1, _MCCMDTOUCADDRERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_1, _MCREMAPTAB_ADDRTYPEERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_1, _MCREMAPTAB_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_1, _READMCREFLECTMEMERR, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _INGRESS, _ERR_NON_FATAL_REPORT_EN_0, + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _ACLFAIL, __PROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _ADDRBOUNDSERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _ADDRTYPEERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _CMDDECODEERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_ACLFAIL, __PROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_ADDRBOUNDSERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_INDEX_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_REQCONTEXTMISMATCHERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_ACLFAIL, __PROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_ADDRBOUNDSERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_INDEX_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_REQCONTEXTMISMATCHERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _INVALIDVCSET, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_ACLFAIL, __PROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_ADDRBOUNDSERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_INDEX_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_REQCONTEXTMISMATCHERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _NCISOC_HDR_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _NCISOC_HDR_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _NCISOC_PARITY_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _REMAPTAB_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _REMAPTAB_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _REQCONTEXTMISMATCHERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _RIDTABCFGERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _RIDTAB_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _RIDTAB_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _RLANTABCFGERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _RLANTAB_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _RLANTAB_ECC_LIMIT_ERR, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _INGRESS, _ERR_NON_FATAL_REPORT_EN_1, + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _EXTAREMAPTAB_ADDRTYPEERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _EXTAREMAPTAB_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _EXTBREMAPTAB_ADDRTYPEERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _EXTBREMAPTAB_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCCMDTOUCADDRERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCREMAPTAB_ADDRTYPEERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCREMAPTAB_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _READMCREFLECTMEMERR, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _MULTICASTTSTATE, _ERR_CONTAIN_EN_0, + DRF_DEF(_MULTICASTTSTATE, _ERR_CONTAIN_EN_0, _CRUMBSTORE_BUF_OVERWRITE_ERR, __PROD) | + DRF_DEF(_MULTICASTTSTATE, _ERR_CONTAIN_EN_0, _CRUMBSTORE_ECC_DBE_ERR, __PROD) | + DRF_DEF(_MULTICASTTSTATE, _ERR_CONTAIN_EN_0, _CRUMBSTORE_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_MULTICASTTSTATE, _ERR_CONTAIN_EN_0, _CRUMBSTORE_MCTO_ERR, _DISABLE) | + DRF_DEF(_MULTICASTTSTATE, _ERR_CONTAIN_EN_0, _TAGPOOL_ECC_DBE_ERR, __PROD) | + DRF_DEF(_MULTICASTTSTATE, _ERR_CONTAIN_EN_0, _TAGPOOL_ECC_LIMIT_ERR, _DISABLE)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _MULTICASTTSTATE, _ERR_ECC_CTRL, + DRF_DEF(_MULTICASTTSTATE, _ERR_ECC_CTRL, _CRUMBSTORE_ECC_ENABLE, __PROD) | + DRF_DEF(_MULTICASTTSTATE, _ERR_ECC_CTRL, _TAGPOOL_ECC_ENABLE, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _MULTICASTTSTATE, _ERR_FATAL_REPORT_EN_0, + DRF_DEF(_MULTICASTTSTATE, _ERR_FATAL_REPORT_EN_0, _CRUMBSTORE_BUF_OVERWRITE_ERR, __PROD) | + DRF_DEF(_MULTICASTTSTATE, _ERR_FATAL_REPORT_EN_0, _CRUMBSTORE_ECC_DBE_ERR, __PROD) | + DRF_DEF(_MULTICASTTSTATE, _ERR_FATAL_REPORT_EN_0, _CRUMBSTORE_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_MULTICASTTSTATE, _ERR_FATAL_REPORT_EN_0, _CRUMBSTORE_MCTO_ERR, _DISABLE) | + DRF_DEF(_MULTICASTTSTATE, _ERR_FATAL_REPORT_EN_0, _TAGPOOL_ECC_DBE_ERR, __PROD) | + DRF_DEF(_MULTICASTTSTATE, _ERR_FATAL_REPORT_EN_0, _TAGPOOL_ECC_LIMIT_ERR, _DISABLE)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _MULTICASTTSTATE, _ERR_LOG_EN_0, + DRF_DEF(_MULTICASTTSTATE, _ERR_LOG_EN_0, _CRUMBSTORE_BUF_OVERWRITE_ERR, __PROD) | + DRF_DEF(_MULTICASTTSTATE, _ERR_LOG_EN_0, _CRUMBSTORE_ECC_DBE_ERR, __PROD) | + DRF_DEF(_MULTICASTTSTATE, _ERR_LOG_EN_0, _CRUMBSTORE_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_MULTICASTTSTATE, _ERR_LOG_EN_0, _CRUMBSTORE_MCTO_ERR, __PROD) | + DRF_DEF(_MULTICASTTSTATE, _ERR_LOG_EN_0, _TAGPOOL_ECC_DBE_ERR, __PROD) | + DRF_DEF(_MULTICASTTSTATE, _ERR_LOG_EN_0, _TAGPOOL_ECC_LIMIT_ERR, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _MULTICASTTSTATE, _ERR_NON_FATAL_REPORT_EN_0, + DRF_DEF(_MULTICASTTSTATE, _ERR_NON_FATAL_REPORT_EN_0, _CRUMBSTORE_BUF_OVERWRITE_ERR, _DISABLE) | + DRF_DEF(_MULTICASTTSTATE, _ERR_NON_FATAL_REPORT_EN_0, _CRUMBSTORE_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_MULTICASTTSTATE, _ERR_NON_FATAL_REPORT_EN_0, _CRUMBSTORE_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_MULTICASTTSTATE, _ERR_NON_FATAL_REPORT_EN_0, _CRUMBSTORE_MCTO_ERR, __PROD) | + DRF_DEF(_MULTICASTTSTATE, _ERR_NON_FATAL_REPORT_EN_0, _TAGPOOL_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_MULTICASTTSTATE, _ERR_NON_FATAL_REPORT_EN_0, _TAGPOOL_ECC_LIMIT_ERR, __PROD)); + + NVSWITCH_ENG_WR32(device, NPG_PERFMON, _BCAST, 0, _NPGPERF, _CTRL_CLOCK_GATING, + DRF_DEF(_NPGPERF, _CTRL_CLOCK_GATING, _CG1_SLCG, __PROD)); + + NVSWITCH_ENG_WR32(device, NPG_PERFMON, _BCAST, 0, _NPGPERF, _PERF_CTRL_CLOCK_GATING, + DRF_DEF(_NPGPERF, _PERF_CTRL_CLOCK_GATING, _CG1_SLCG, __PROD) | + DRF_DEF(_NPGPERF, _PERF_CTRL_CLOCK_GATING, _CONTEXT_FREEZE, __PROD)); + + NVSWITCH_ENG_WR32(device, NPG, _BCAST, 0, _NPG, _CTRL_CLOCK_GATING, + DRF_DEF(_NPG, _CTRL_CLOCK_GATING, _CG1_BLCG, __PROD) | + DRF_DEF(_NPG, _CTRL_CLOCK_GATING, _CG1_SLCG, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _NPORT, _CTRL_SLCG, + DRF_DEF(_NPORT, _CTRL_SLCG, _DIS_CG_EGRESS, __PROD) | + DRF_DEF(_NPORT, _CTRL_SLCG, _DIS_CG_INGRESS, __PROD) | + DRF_DEF(_NPORT, _CTRL_SLCG, _DIS_CG_MCTAGSTATE, __PROD) | + DRF_DEF(_NPORT, _CTRL_SLCG, _DIS_CG_RDTAGSTATE, __PROD) | + DRF_DEF(_NPORT, _CTRL_SLCG, _DIS_CG_ROUTE, __PROD) | + DRF_DEF(_NPORT, _CTRL_SLCG, _DIS_CG_STRACK, __PROD) | + DRF_DEF(_NPORT, _CTRL_SLCG, _DIS_CG_TAGSTATE, __PROD) | + DRF_DEF(_NPORT, _CTRL_SLCG, _DIS_CG_TREX, __PROD) | + DRF_DEF(_NPORT, _CTRL_SLCG, _DIS_CG_WATCHPOINT, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT_PERFMON, _BCAST, 0, _PERF_PMM, ROUTER_CG1_SECURE, + DRF_DEF(_PERF_PMM, ROUTER_CG1_SECURE, _FLCG_PERFMON, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT_PERFMON, _BCAST, 0, _PERF_PMM, ROUTER_PERFMON_CG2_SECURE, + DRF_DEF(_PERF_PMM, ROUTER_PERFMON_CG2_SECURE, _SLCG, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _REDUCTIONTSTATE, _ERR_CONTAIN_EN_0, + DRF_DEF(_REDUCTIONTSTATE, _ERR_CONTAIN_EN_0, _CRUMBSTORE_BUF_OVERWRITE_ERR, __PROD) | + DRF_DEF(_REDUCTIONTSTATE, _ERR_CONTAIN_EN_0, _CRUMBSTORE_ECC_DBE_ERR, __PROD) | + DRF_DEF(_REDUCTIONTSTATE, _ERR_CONTAIN_EN_0, _CRUMBSTORE_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_REDUCTIONTSTATE, _ERR_CONTAIN_EN_0, _CRUMBSTORE_RTO_ERR, _DISABLE) | + DRF_DEF(_REDUCTIONTSTATE, _ERR_CONTAIN_EN_0, _TAGPOOL_ECC_DBE_ERR, __PROD) | + DRF_DEF(_REDUCTIONTSTATE, _ERR_CONTAIN_EN_0, _TAGPOOL_ECC_LIMIT_ERR, _DISABLE)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _REDUCTIONTSTATE, _ERR_ECC_CTRL, + DRF_DEF(_REDUCTIONTSTATE, _ERR_ECC_CTRL, _CRUMBSTORE_ECC_ENABLE, __PROD) | + DRF_DEF(_REDUCTIONTSTATE, _ERR_ECC_CTRL, _TAGPOOL_ECC_ENABLE, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _REDUCTIONTSTATE, _ERR_FATAL_REPORT_EN_0, + DRF_DEF(_REDUCTIONTSTATE, _ERR_FATAL_REPORT_EN_0, _CRUMBSTORE_BUF_OVERWRITE_ERR, __PROD) | + DRF_DEF(_REDUCTIONTSTATE, _ERR_FATAL_REPORT_EN_0, _CRUMBSTORE_ECC_DBE_ERR, __PROD) | + DRF_DEF(_REDUCTIONTSTATE, _ERR_FATAL_REPORT_EN_0, _CRUMBSTORE_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_REDUCTIONTSTATE, _ERR_FATAL_REPORT_EN_0, _CRUMBSTORE_RTO_ERR, _DISABLE) | + DRF_DEF(_REDUCTIONTSTATE, _ERR_FATAL_REPORT_EN_0, _TAGPOOL_ECC_DBE_ERR, __PROD) | + DRF_DEF(_REDUCTIONTSTATE, _ERR_FATAL_REPORT_EN_0, _TAGPOOL_ECC_LIMIT_ERR, _DISABLE)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _REDUCTIONTSTATE, _ERR_LOG_EN_0, + DRF_DEF(_REDUCTIONTSTATE, _ERR_LOG_EN_0, _CRUMBSTORE_BUF_OVERWRITE_ERR, __PROD) | + DRF_DEF(_REDUCTIONTSTATE, _ERR_LOG_EN_0, _CRUMBSTORE_ECC_DBE_ERR, __PROD) | + DRF_DEF(_REDUCTIONTSTATE, _ERR_LOG_EN_0, _CRUMBSTORE_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_REDUCTIONTSTATE, _ERR_LOG_EN_0, _CRUMBSTORE_RTO_ERR, __PROD) | + DRF_DEF(_REDUCTIONTSTATE, _ERR_LOG_EN_0, _TAGPOOL_ECC_DBE_ERR, __PROD) | + DRF_DEF(_REDUCTIONTSTATE, _ERR_LOG_EN_0, _TAGPOOL_ECC_LIMIT_ERR, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _REDUCTIONTSTATE, _ERR_NON_FATAL_REPORT_EN_0, + DRF_DEF(_REDUCTIONTSTATE, _ERR_NON_FATAL_REPORT_EN_0, _CRUMBSTORE_BUF_OVERWRITE_ERR, _DISABLE) | + DRF_DEF(_REDUCTIONTSTATE, _ERR_NON_FATAL_REPORT_EN_0, _CRUMBSTORE_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_REDUCTIONTSTATE, _ERR_NON_FATAL_REPORT_EN_0, _CRUMBSTORE_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_REDUCTIONTSTATE, _ERR_NON_FATAL_REPORT_EN_0, _CRUMBSTORE_RTO_ERR, __PROD) | + DRF_DEF(_REDUCTIONTSTATE, _ERR_NON_FATAL_REPORT_EN_0, _TAGPOOL_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_REDUCTIONTSTATE, _ERR_NON_FATAL_REPORT_EN_0, _TAGPOOL_ECC_LIMIT_ERR, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _ROUTE, _ERR_CONTAIN_EN_0, + DRF_DEF(_ROUTE, _ERR_CONTAIN_EN_0, _CDTPARERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_CONTAIN_EN_0, _EXTMCRID_ECC_DBE_ERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_CONTAIN_EN_0, _EXTMCRID_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_ROUTE, _ERR_CONTAIN_EN_0, _GLT_ECC_DBE_ERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_CONTAIN_EN_0, _GLT_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_ROUTE, _ERR_CONTAIN_EN_0, _INVALIDROUTEPOLICYERR, _DISABLE) | + DRF_DEF(_ROUTE, _ERR_CONTAIN_EN_0, _INVALID_MCRID_ERR, _DISABLE) | + DRF_DEF(_ROUTE, _ERR_CONTAIN_EN_0, _MCRID_ECC_DBE_ERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_CONTAIN_EN_0, _MCRID_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_ROUTE, _ERR_CONTAIN_EN_0, _MC_TRIGGER_ERR, _DISABLE) | + DRF_DEF(_ROUTE, _ERR_CONTAIN_EN_0, _NOPORTDEFINEDERR, _DISABLE) | + DRF_DEF(_ROUTE, _ERR_CONTAIN_EN_0, _NVS_ECC_DBE_ERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_CONTAIN_EN_0, _NVS_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_ROUTE, _ERR_CONTAIN_EN_0, _PDCTRLPARERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_CONTAIN_EN_0, _RAM_ECC_DBE_ERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_CONTAIN_EN_0, _RAM_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_ROUTE, _ERR_CONTAIN_EN_0, _ROUTEBUFERR, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _ROUTE, _ERR_ECC_CTRL, + DRF_DEF(_ROUTE, _ERR_ECC_CTRL, _ECCWRITEBACKENBGLT, _ENABLE) | + DRF_DEF(_ROUTE, _ERR_ECC_CTRL, _ECCWRITEBACKEXTMCRIDENB, _ENABLE) | + DRF_DEF(_ROUTE, _ERR_ECC_CTRL, _ECCWRITEBACKMCRIDENB, _ENABLE) | + DRF_DEF(_ROUTE, _ERR_ECC_CTRL, _EXTMCRID_ECC_ENABLE, __PROD) | + DRF_DEF(_ROUTE, _ERR_ECC_CTRL, _GLT_ECC_ENABLE, __PROD) | + DRF_DEF(_ROUTE, _ERR_ECC_CTRL, _MCRID_ECC_ENABLE, __PROD) | + DRF_DEF(_ROUTE, _ERR_ECC_CTRL, _NVS_ECC_ENABLE, __PROD) | + DRF_DEF(_ROUTE, _ERR_ECC_CTRL, _RAM_ECC_ENABLE, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _ROUTE, _ERR_FATAL_REPORT_EN_0, + DRF_DEF(_ROUTE, _ERR_FATAL_REPORT_EN_0, _CDTPARERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_FATAL_REPORT_EN_0, _EXTMCRID_ECC_DBE_ERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_FATAL_REPORT_EN_0, _EXTMCRID_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_ROUTE, _ERR_FATAL_REPORT_EN_0, _GLT_ECC_DBE_ERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_FATAL_REPORT_EN_0, _GLT_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_ROUTE, _ERR_FATAL_REPORT_EN_0, _INVALIDROUTEPOLICYERR, _DISABLE) | + DRF_DEF(_ROUTE, _ERR_FATAL_REPORT_EN_0, _INVALID_MCRID_ERR, _DISABLE) | + DRF_DEF(_ROUTE, _ERR_FATAL_REPORT_EN_0, _MCRID_ECC_DBE_ERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_FATAL_REPORT_EN_0, _MCRID_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_ROUTE, _ERR_FATAL_REPORT_EN_0, _MC_TRIGGER_ERR, _DISABLE) | + DRF_DEF(_ROUTE, _ERR_FATAL_REPORT_EN_0, _NOPORTDEFINEDERR, _DISABLE) | + DRF_DEF(_ROUTE, _ERR_FATAL_REPORT_EN_0, _NVS_ECC_DBE_ERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_FATAL_REPORT_EN_0, _NVS_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_ROUTE, _ERR_FATAL_REPORT_EN_0, _PDCTRLPARERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_FATAL_REPORT_EN_0, _RAM_ECC_DBE_ERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_FATAL_REPORT_EN_0, _RAM_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_ROUTE, _ERR_FATAL_REPORT_EN_0, _ROUTEBUFERR, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _ROUTE, _ERR_LOG_EN_0, + DRF_DEF(_ROUTE, _ERR_LOG_EN_0, _CDTPARERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_LOG_EN_0, _EXTMCRID_ECC_DBE_ERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_LOG_EN_0, _EXTMCRID_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_LOG_EN_0, _GLT_ECC_DBE_ERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_LOG_EN_0, _GLT_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_LOG_EN_0, _INVALIDROUTEPOLICYERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_LOG_EN_0, _INVALID_MCRID_ERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_LOG_EN_0, _MCRID_ECC_DBE_ERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_LOG_EN_0, _MCRID_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_LOG_EN_0, _MC_TRIGGER_ERR, _DISABLE) | + DRF_DEF(_ROUTE, _ERR_LOG_EN_0, _NOPORTDEFINEDERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_LOG_EN_0, _NVS_ECC_DBE_ERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_LOG_EN_0, _NVS_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_LOG_EN_0, _PDCTRLPARERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_LOG_EN_0, _RAM_ECC_DBE_ERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_LOG_EN_0, _RAM_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_LOG_EN_0, _ROUTEBUFERR, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _ROUTE, _ERR_NON_FATAL_REPORT_EN_0, + DRF_DEF(_ROUTE, _ERR_NON_FATAL_REPORT_EN_0, _CDTPARERR, _DISABLE) | + DRF_DEF(_ROUTE, _ERR_NON_FATAL_REPORT_EN_0, _EXTMCRID_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_ROUTE, _ERR_NON_FATAL_REPORT_EN_0, _EXTMCRID_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_NON_FATAL_REPORT_EN_0, _GLT_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_ROUTE, _ERR_NON_FATAL_REPORT_EN_0, _GLT_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_NON_FATAL_REPORT_EN_0, _INVALIDROUTEPOLICYERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_NON_FATAL_REPORT_EN_0, _INVALID_MCRID_ERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_NON_FATAL_REPORT_EN_0, _MCRID_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_ROUTE, _ERR_NON_FATAL_REPORT_EN_0, _MCRID_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_NON_FATAL_REPORT_EN_0, _MC_TRIGGER_ERR, _DISABLE) | + DRF_DEF(_ROUTE, _ERR_NON_FATAL_REPORT_EN_0, _NOPORTDEFINEDERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_NON_FATAL_REPORT_EN_0, _NVS_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_ROUTE, _ERR_NON_FATAL_REPORT_EN_0, _NVS_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_NON_FATAL_REPORT_EN_0, _PDCTRLPARERR, _DISABLE) | + DRF_DEF(_ROUTE, _ERR_NON_FATAL_REPORT_EN_0, _RAM_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_ROUTE, _ERR_NON_FATAL_REPORT_EN_0, _RAM_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_ROUTE, _ERR_NON_FATAL_REPORT_EN_0, _ROUTEBUFERR, _DISABLE)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _SOURCETRACK, _ERR_CONTAIN_EN_0, + DRF_DEF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR, __PROD) | + DRF_DEF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _DUP_CREQ_TCEN0_TAG_ERR, __PROD) | + DRF_DEF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _INVALID_TCEN0_RSP_ERR, __PROD) | + DRF_DEF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _INVALID_TCEN1_RSP_ERR, __PROD) | + DRF_DEF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _SOURCETRACK_TIME_OUT_ERR, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _SOURCETRACK, _ERR_ECC_CTRL, + DRF_DEF(_SOURCETRACK, _ERR_ECC_CTRL, _CREQ_TCEN0_CRUMBSTORE_ECC_ENABLE, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _SOURCETRACK, _ERR_FATAL_REPORT_EN_0, + DRF_DEF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR, __PROD) | + DRF_DEF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _DUP_CREQ_TCEN0_TAG_ERR, __PROD) | + DRF_DEF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _INVALID_TCEN0_RSP_ERR, __PROD) | + DRF_DEF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _INVALID_TCEN1_RSP_ERR, __PROD) | + DRF_DEF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _SOURCETRACK_TIME_OUT_ERR, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _SOURCETRACK, _ERR_LOG_EN_0, + DRF_DEF(_SOURCETRACK, _ERR_LOG_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR, __PROD) | + DRF_DEF(_SOURCETRACK, _ERR_LOG_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_SOURCETRACK, _ERR_LOG_EN_0, _DUP_CREQ_TCEN0_TAG_ERR, __PROD) | + DRF_DEF(_SOURCETRACK, _ERR_LOG_EN_0, _INVALID_TCEN0_RSP_ERR, __PROD) | + DRF_DEF(_SOURCETRACK, _ERR_LOG_EN_0, _INVALID_TCEN1_RSP_ERR, __PROD) | + DRF_DEF(_SOURCETRACK, _ERR_LOG_EN_0, _SOURCETRACK_TIME_OUT_ERR, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _SOURCETRACK, _ERR_NON_FATAL_REPORT_EN_0, + DRF_DEF(_SOURCETRACK, _ERR_NON_FATAL_REPORT_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_SOURCETRACK, _ERR_NON_FATAL_REPORT_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_SOURCETRACK, _ERR_NON_FATAL_REPORT_EN_0, _DUP_CREQ_TCEN0_TAG_ERR, _DISABLE) | + DRF_DEF(_SOURCETRACK, _ERR_NON_FATAL_REPORT_EN_0, _INVALID_TCEN0_RSP_ERR, _DISABLE) | + DRF_DEF(_SOURCETRACK, _ERR_NON_FATAL_REPORT_EN_0, _INVALID_TCEN1_RSP_ERR, _DISABLE) | + DRF_DEF(_SOURCETRACK, _ERR_NON_FATAL_REPORT_EN_0, _SOURCETRACK_TIME_OUT_ERR, _DISABLE)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _TSTATE, _ERR_CONTAIN_EN_0, + DRF_DEF(_TSTATE, _ERR_CONTAIN_EN_0, _ATO_ERR, __PROD) | + DRF_DEF(_TSTATE, _ERR_CONTAIN_EN_0, _CAMRSP_ERR, __PROD) | + DRF_DEF(_TSTATE, _ERR_CONTAIN_EN_0, _CRUMBSTOREBUFERR, __PROD) | + DRF_DEF(_TSTATE, _ERR_CONTAIN_EN_0, _CRUMBSTORE_ECC_DBE_ERR, __PROD) | + DRF_DEF(_TSTATE, _ERR_CONTAIN_EN_0, _CRUMBSTORE_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_TSTATE, _ERR_CONTAIN_EN_0, _TAGPOOLBUFERR, __PROD) | + DRF_DEF(_TSTATE, _ERR_CONTAIN_EN_0, _TAGPOOL_ECC_DBE_ERR, __PROD) | + DRF_DEF(_TSTATE, _ERR_CONTAIN_EN_0, _TAGPOOL_ECC_LIMIT_ERR, _DISABLE)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _TSTATE, _ERR_ECC_CTRL, + DRF_DEF(_TSTATE, _ERR_ECC_CTRL, _CRUMBSTORE_ECC_ENABLE, __PROD) | + DRF_DEF(_TSTATE, _ERR_ECC_CTRL, _TAGPOOL_ECC_ENABLE, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _TSTATE, _ERR_FATAL_REPORT_EN_0, + DRF_DEF(_TSTATE, _ERR_FATAL_REPORT_EN_0, _ATO_ERR, __PROD) | + DRF_DEF(_TSTATE, _ERR_FATAL_REPORT_EN_0, _CAMRSP_ERR, __PROD) | + DRF_DEF(_TSTATE, _ERR_FATAL_REPORT_EN_0, _CRUMBSTOREBUFERR, __PROD) | + DRF_DEF(_TSTATE, _ERR_FATAL_REPORT_EN_0, _CRUMBSTORE_ECC_DBE_ERR, __PROD) | + DRF_DEF(_TSTATE, _ERR_FATAL_REPORT_EN_0, _CRUMBSTORE_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_TSTATE, _ERR_FATAL_REPORT_EN_0, _TAGPOOLBUFERR, __PROD) | + DRF_DEF(_TSTATE, _ERR_FATAL_REPORT_EN_0, _TAGPOOL_ECC_DBE_ERR, __PROD) | + DRF_DEF(_TSTATE, _ERR_FATAL_REPORT_EN_0, _TAGPOOL_ECC_LIMIT_ERR, _DISABLE)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _TSTATE, _ERR_LOG_EN_0, + DRF_DEF(_TSTATE, _ERR_LOG_EN_0, _ATO_ERR, __PROD) | + DRF_DEF(_TSTATE, _ERR_LOG_EN_0, _CAMRSP_ERR, __PROD) | + DRF_DEF(_TSTATE, _ERR_LOG_EN_0, _CRUMBSTOREBUFERR, __PROD) | + DRF_DEF(_TSTATE, _ERR_LOG_EN_0, _CRUMBSTORE_ECC_DBE_ERR, __PROD) | + DRF_DEF(_TSTATE, _ERR_LOG_EN_0, _CRUMBSTORE_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_TSTATE, _ERR_LOG_EN_0, _TAGPOOLBUFERR, __PROD) | + DRF_DEF(_TSTATE, _ERR_LOG_EN_0, _TAGPOOL_ECC_DBE_ERR, __PROD) | + DRF_DEF(_TSTATE, _ERR_LOG_EN_0, _TAGPOOL_ECC_LIMIT_ERR, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _TSTATE, _ERR_NON_FATAL_REPORT_EN_0, + DRF_DEF(_TSTATE, _ERR_NON_FATAL_REPORT_EN_0, _ATO_ERR, _DISABLE) | + DRF_DEF(_TSTATE, _ERR_NON_FATAL_REPORT_EN_0, _CAMRSP_ERR, _DISABLE) | + DRF_DEF(_TSTATE, _ERR_NON_FATAL_REPORT_EN_0, _CRUMBSTOREBUFERR, _DISABLE) | + DRF_DEF(_TSTATE, _ERR_NON_FATAL_REPORT_EN_0, _CRUMBSTORE_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_TSTATE, _ERR_NON_FATAL_REPORT_EN_0, _CRUMBSTORE_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_TSTATE, _ERR_NON_FATAL_REPORT_EN_0, _TAGPOOLBUFERR, _DISABLE) | + DRF_DEF(_TSTATE, _ERR_NON_FATAL_REPORT_EN_0, _TAGPOOL_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_TSTATE, _ERR_NON_FATAL_REPORT_EN_0, _TAGPOOL_ECC_LIMIT_ERR, __PROD)); + + return NVL_SUCCESS; +} +#endif + + +/* + * @Brief : Fill In + * + * @Description : Fill In + * + * @paramin : Fill In + * + */ + +NvlStatus +nvswitch_apply_prod_nvlw_ls10 +( + nvswitch_device *device +) +{ + + + // .Apply PROD to NVLW registers + + NVSWITCH_ENG_WR32(device, CPR, _BCAST, 0, _CPR_SYS, _ERR_LOG_EN_0, + DRF_DEF(_CPR_SYS, _ERR_LOG_EN_0, _ENGINE_RESET_ERR, __PROD)); + + NVSWITCH_ENG_WR32(device, CPR, _BCAST, 0, _CPR_SYS, _NVLW_CG1, + DRF_DEF(_CPR_SYS, _NVLW_CG1, _SLCG, __PROD)); + + return NVL_SUCCESS; +} + + +/* + * @Brief : Fill In + * + * @Description : Fill In + * + * @paramin : Fill In + * + */ + +NvlStatus +nvswitch_apply_prod_nxbar_ls10 +( + nvswitch_device *device +) +{ + + + // .NXBAR PROD value application + + NVSWITCH_ENG_WR32(device, TILEOUT, _BCAST, 0, _NXBAR_TILEOUT, _CTRL0, + DRF_DEF(_NXBAR_TILEOUT, _CTRL0, _MULTI_VALID_XFN_CTRL, _ENABLE) | + DRF_DEF(_NXBAR_TILEOUT, _CTRL0, _PARTIAL_RAM_WR_CTRL, _ENABLE) | + DRF_DEF(_NXBAR_TILEOUT, _CTRL0, _PRI_FGCG_CTRL, __PROD)); + + NVSWITCH_ENG_WR32(device, TILEOUT, _BCAST, 0, _NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, + DRF_DEF(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _EGRESS_CDT_PARITY_ERROR, __PROD) | + DRF_DEF(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _EGRESS_CREDIT_OVERFLOW, __PROD) | + DRF_DEF(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _EGRESS_CREDIT_UNDERFLOW, __PROD) | + DRF_DEF(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _INGRESS_BUFFER_OVERFLOW, __PROD) | + DRF_DEF(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _INGRESS_BUFFER_UNDERFLOW, __PROD) | + DRF_DEF(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _INGRESS_BURST_GT_9_DATA_VC, __PROD) | + DRF_DEF(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _INGRESS_NON_BURSTY_PKT, __PROD) | + DRF_DEF(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _INGRESS_NON_STICKY_PKT, __PROD)); + + NVSWITCH_ENG_WR32(device, TILEOUT, _BCAST, 0, _NXBAR_TILEOUT, _PRI_NXBAR_TILEOUT_CG, + DRF_DEF(_NXBAR_TILEOUT, _PRI_NXBAR_TILEOUT_CG, _DI_DT_SKEW_VAL, __PROD) | + DRF_DEF(_NXBAR_TILEOUT, _PRI_NXBAR_TILEOUT_CG, _HALT_CG_EN, __PROD) | + DRF_DEF(_NXBAR_TILEOUT, _PRI_NXBAR_TILEOUT_CG, _IDLE_CG_DLY_CNT, __PROD) | + DRF_DEF(_NXBAR_TILEOUT, _PRI_NXBAR_TILEOUT_CG, _IDLE_CG_EN, __PROD) | + DRF_DEF(_NXBAR_TILEOUT, _PRI_NXBAR_TILEOUT_CG, _PAUSE_CG_EN, __PROD) | + DRF_DEF(_NXBAR_TILEOUT, _PRI_NXBAR_TILEOUT_CG, _QUIESCENT_CG_EN, __PROD) | + DRF_DEF(_NXBAR_TILEOUT, _PRI_NXBAR_TILEOUT_CG, _STALL_CG_DLY_CNT, __PROD) | + DRF_DEF(_NXBAR_TILEOUT, _PRI_NXBAR_TILEOUT_CG, _STALL_CG_EN, __PROD) | + DRF_DEF(_NXBAR_TILEOUT, _PRI_NXBAR_TILEOUT_CG, _STATE_CG_EN, __PROD) | + DRF_DEF(_NXBAR_TILEOUT, _PRI_NXBAR_TILEOUT_CG, _THROT_CLK_CNT, __PROD) | + DRF_DEF(_NXBAR_TILEOUT, _PRI_NXBAR_TILEOUT_CG, _THROT_CLK_EN, __PROD) | + DRF_DEF(_NXBAR_TILEOUT, _PRI_NXBAR_TILEOUT_CG, _THROT_CLK_SW_OVER, __PROD) | + DRF_DEF(_NXBAR_TILEOUT, _PRI_NXBAR_TILEOUT_CG, _WAKEUP_DLY_CNT, __PROD)); + + NVSWITCH_ENG_WR32(device, TILEOUT, _BCAST, 0, _NXBAR_TILEOUT, _PRI_NXBAR_TILEOUT_CG1, + DRF_DEF(_NXBAR_TILEOUT, _PRI_NXBAR_TILEOUT_CG1, _MONITOR_CG_EN, __PROD)); + + NVSWITCH_ENG_WR32(device, TILE, _BCAST, 0, _NXBAR_TILE, _CTRL0, + DRF_DEF(_NXBAR_TILE, _CTRL0, _MULTI_VALID_XFN_CTRL, _ENABLE) | + DRF_DEF(_NXBAR_TILE, _CTRL0, _PARTIAL_RAM_WR_CTRL, _ENABLE) | + DRF_DEF(_NXBAR_TILE, _CTRL0, _PRI_FGCG_CTRL, __PROD)); + + NVSWITCH_ENG_WR32(device, TILE, _BCAST, 0, _NXBAR_TILE, _ERR_FATAL_INTR_EN, + DRF_DEF(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _EGRESS_CREDIT_OVERFLOW, __PROD) | + DRF_DEF(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _EGRESS_CREDIT_UNDERFLOW, __PROD) | + DRF_DEF(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_BUFFER_OVERFLOW, __PROD) | + DRF_DEF(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_BUFFER_UNDERFLOW, __PROD) | + DRF_DEF(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_BURST_GT_9_DATA_VC, __PROD) | + DRF_DEF(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_NON_BURSTY_PKT, __PROD) | + DRF_DEF(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_NON_STICKY_PKT, __PROD) | + DRF_DEF(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_PKT_INVALID_DST, __PROD) | + DRF_DEF(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_PKT_PARITY_ERROR, __PROD) | + DRF_DEF(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_REDUCTION_PKT_ERROR, __PROD) | + DRF_DEF(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_SIDEBAND_PARITY_ERROR, __PROD)); + + NVSWITCH_ENG_WR32(device, TILE, _BCAST, 0, _NXBAR_TILE, _PRI_NXBAR_TILE_CG, + DRF_DEF(_NXBAR_TILE, _PRI_NXBAR_TILE_CG, _DI_DT_SKEW_VAL, __PROD) | + DRF_DEF(_NXBAR_TILE, _PRI_NXBAR_TILE_CG, _HALT_CG_EN, __PROD) | + DRF_DEF(_NXBAR_TILE, _PRI_NXBAR_TILE_CG, _IDLE_CG_DLY_CNT, __PROD) | + DRF_DEF(_NXBAR_TILE, _PRI_NXBAR_TILE_CG, _IDLE_CG_EN, __PROD) | + DRF_DEF(_NXBAR_TILE, _PRI_NXBAR_TILE_CG, _PAUSE_CG_EN, __PROD) | + DRF_DEF(_NXBAR_TILE, _PRI_NXBAR_TILE_CG, _QUIESCENT_CG_EN, __PROD) | + DRF_DEF(_NXBAR_TILE, _PRI_NXBAR_TILE_CG, _STALL_CG_DLY_CNT, __PROD) | + DRF_DEF(_NXBAR_TILE, _PRI_NXBAR_TILE_CG, _STALL_CG_EN, __PROD) | + DRF_DEF(_NXBAR_TILE, _PRI_NXBAR_TILE_CG, _STATE_CG_EN, __PROD) | + DRF_DEF(_NXBAR_TILE, _PRI_NXBAR_TILE_CG, _THROT_CLK_CNT, __PROD) | + DRF_DEF(_NXBAR_TILE, _PRI_NXBAR_TILE_CG, _THROT_CLK_EN, __PROD) | + DRF_DEF(_NXBAR_TILE, _PRI_NXBAR_TILE_CG, _THROT_CLK_SW_OVER, __PROD) | + DRF_DEF(_NXBAR_TILE, _PRI_NXBAR_TILE_CG, _WAKEUP_DLY_CNT, __PROD)); + + NVSWITCH_ENG_WR32(device, TILE, _BCAST, 0, _NXBAR_TILE, _PRI_NXBAR_TILE_CG1, + DRF_DEF(_NXBAR_TILE, _PRI_NXBAR_TILE_CG1, _MONITOR_CG_EN, __PROD)); + + return NVL_SUCCESS; +} + + +/* + * @Brief : Fill In + * + * @Description : Fill In + * + * @paramin : Fill In + * + */ + +NvlStatus +nvswitch_nvs_top_prod_ls10 +( + nvswitch_device *device +) +{ + NvU32 i; + + // .NVS_TOP PROD application + + NVSWITCH_ENG_WR32(device, CLKS_P0, , 0, _CLOCK_NVSW_PRT, _NVLINK_UPHY0_PLL0_SLCG, + DRF_DEF(_CLOCK_NVSW_PRT, _NVLINK_UPHY0_PLL0_SLCG, _CFGSM, __PROD)); + + NVSWITCH_ENG_WR32(device, CLKS_P0, , 1, _CLOCK_NVSW_PRT, _NVLINK_UPHY0_PLL0_SLCG, + DRF_DEF(_CLOCK_NVSW_PRT, _NVLINK_UPHY0_PLL0_SLCG, _CFGSM, __PROD)); + + NVSWITCH_ENG_WR32(device, CLKS_P0, , 2, _CLOCK_NVSW_PRT, _NVLINK_UPHY0_PLL0_SLCG, + DRF_DEF(_CLOCK_NVSW_PRT, _NVLINK_UPHY0_PLL0_SLCG, _CFGSM, __PROD)); + + NVSWITCH_ENG_WR32(device, CLKS_P0, , 3, _CLOCK_NVSW_PRT, _NVLINK_UPHY0_PLL0_SLCG, + DRF_DEF(_CLOCK_NVSW_PRT, _NVLINK_UPHY0_PLL0_SLCG, _CFGSM, __PROD)); + + NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _PRI_CTRL_CG1, + DRF_DEF(_CTRL, _PRI_CTRL_CG1, _SLCG_CTRLPRI, __PROD) | + DRF_DEF(_CTRL, _PRI_CTRL_CG1, _SLCG_MSIX, __PROD)); + + NVSWITCH_ENG_WR32(device, PRI_MASTER_RS, , 0, _PPRIV_MASTER, _CG1, + DRF_DEF(_PPRIV_MASTER, _CG1, _SLCG, __PROD)); + + // + // SU-generated code blindly writes each PRT_PRI_HUB and PRT_PRI_RS_CTRL + // without checking to see if it is floorswept. This code fragment is + // hand editted into SU-generated code to handle floorsweeping. + // + for (i = 0; i < NVSWITCH_ENG_COUNT(device, PRT_PRI_HUB, ); i++) + { + if (NVSWITCH_ENG_IS_VALID(device, PRT_PRI_HUB, i)) + { + NVSWITCH_ENG_WR32(device, PRT_PRI_HUB, , i, _PPRIV_PRT, _CG1, + DRF_DEF(_PPRIV_PRT, _CG1, _SLCG_LOC_PRIV, __PROD) | + DRF_DEF(_PPRIV_PRT, _CG1, _SLCG_PM, __PROD) | + DRF_DEF(_PPRIV_PRT, _CG1, _SLCG_PRIV_CONFIG_REGS, __PROD) | + DRF_DEF(_PPRIV_PRT, _CG1, _SLCG_PRIV_FUNNEL_ARB, __PROD) | + DRF_DEF(_PPRIV_PRT, _CG1, _SLCG_PRIV_FUNNEL_DECODER, __PROD) | + DRF_DEF(_PPRIV_PRT, _CG1, _SLCG_PRIV_HISTORY_BUFFER, __PROD) | + DRF_DEF(_PPRIV_PRT, _CG1, _SLCG_PRIV_MASTER, __PROD) | + DRF_DEF(_PPRIV_PRT, _CG1, _SLCG_PRIV_SLAVE, __PROD) | + DRF_DEF(_PPRIV_PRT, _CG1, _SLCG_SLOWCLK, __PROD)); + } + } + + for (i = 0; i < NVSWITCH_ENG_COUNT(device, PRT_PRI_RS_CTRL, ); i++) + { + if (NVSWITCH_ENG_IS_VALID(device, PRT_PRI_RS_CTRL, i)) + { + NVSWITCH_ENG_WR32(device, PRT_PRI_RS_CTRL, , i, _PPRIV_RS_CTRL_PRT, _CG1, + DRF_DEF(_PPRIV_RS_CTRL_PRT, _CG1, _SLCG, __PROD)); + } + } + + NVSWITCH_ENG_WR32(device, PTIMER, , 0, _PTIMER, _PRI_TMR_CG1, + DRF_DEF(_PTIMER, _PRI_TMR_CG1, _MONITOR_CG_EN, __PROD) | + DRF_DEF(_PTIMER, _PRI_TMR_CG1, _SLCG, __PROD)); + + NVSWITCH_ENG_WR32(device, SAW, , 0, _NVLSAW, _CTRL_CLOCK_GATING, + DRF_DEF(_NVLSAW, _CTRL_CLOCK_GATING, _CG1_SLCG_PCIE, __PROD) | + DRF_DEF(_NVLSAW, _CTRL_CLOCK_GATING, _CG1_SLCG_SAW, __PROD)); + + NVSWITCH_ENG_WR32(device, SAW, , 0, _NVLSAW, _GLBLLATENCYTIMERCTRL, + DRF_DEF(_NVLSAW, _GLBLLATENCYTIMERCTRL, _ENABLE, __PROD)); + + NVSWITCH_ENG_WR32(device, SAW, , 0, _NVLSAW, _PCIE_PRI_CLOCK_GATING, + DRF_DEF(_NVLSAW, _PCIE_PRI_CLOCK_GATING, _CG1_SLCG, __PROD)); + NVSWITCH_REG_WR32(device, _PSE, _CG1, + DRF_DEF(_PSE, _CG1, _SLCG, __PROD)); + + NVSWITCH_ENG_WR32(device, SOE, , 0, _SOE, _BAR0_TMOUT, + DRF_DEF(_SOE, _BAR0_TMOUT, _CYCLES, __PROD)); + + NVSWITCH_ENG_WR32(device, SOE, , 0, _SOE, _FALCON_CG2, + DRF_DEF(_SOE, _FALCON_CG2, _SLCG_FALCON_CFG, _DISABLED) | + DRF_DEF(_SOE, _FALCON_CG2, _SLCG_FALCON_CTXSW, _DISABLED) | + DRF_DEF(_SOE, _FALCON_CG2, _SLCG_FALCON_DIV, _DISABLED) | + DRF_DEF(_SOE, _FALCON_CG2, _SLCG_FALCON_DMA, _DISABLED) | + DRF_DEF(_SOE, _FALCON_CG2, _SLCG_FALCON_GC6_SR_FSM, _DISABLED) | + DRF_DEF(_SOE, _FALCON_CG2, _SLCG_FALCON_GDMA, __PROD) | + DRF_DEF(_SOE, _FALCON_CG2, _SLCG_FALCON_GPTMR, _DISABLED) | + DRF_DEF(_SOE, _FALCON_CG2, _SLCG_FALCON_ICD, _DISABLED) | + DRF_DEF(_SOE, _FALCON_CG2, _SLCG_FALCON_IRQSTAT, _DISABLED) | + DRF_DEF(_SOE, _FALCON_CG2, _SLCG_FALCON_LDST, _DISABLED) | + DRF_DEF(_SOE, _FALCON_CG2, _SLCG_FALCON_MUL, _DISABLED) | + DRF_DEF(_SOE, _FALCON_CG2, _SLCG_FALCON_PIPE, _DISABLED) | + DRF_DEF(_SOE, _FALCON_CG2, _SLCG_FALCON_PMB, _DISABLED) | + DRF_DEF(_SOE, _FALCON_CG2, _SLCG_FALCON_RF, _DISABLED) | + DRF_DEF(_SOE, _FALCON_CG2, _SLCG_FALCON_SHA, __PROD) | + DRF_DEF(_SOE, _FALCON_CG2, _SLCG_FALCON_TOP, _DISABLED) | + DRF_DEF(_SOE, _FALCON_CG2, _SLCG_FALCON_TSE, __PROD) | + DRF_DEF(_SOE, _FALCON_CG2, _SLCG_FALCON_TSYNC, _DISABLED) | + DRF_DEF(_SOE, _FALCON_CG2, _SLCG_FALCON_WDTMR, _DISABLED) | + DRF_DEF(_SOE, _FALCON_CG2, _SLCG_FBIF, _DISABLED)); + + NVSWITCH_ENG_WR32(device, SOE, , 0, _SOE, _MISC_CG1, + DRF_DEF(_SOE, _MISC_CG1, _SLCG, __PROD)); + + NVSWITCH_ENG_WR32(device, SOE, , 0, _SOE, _PRIV_BLOCKER_CTRL_CG1, + DRF_DEF(_SOE, _PRIV_BLOCKER_CTRL_CG1, _SLCG, __PROD)); + + NVSWITCH_ENG_WR32(device, SYSB_PRI_HUB, , 0, _PPRIV_SYSB, _CG1, + DRF_DEF(_PPRIV_SYSB, _CG1, _SLCG_LOC_PRIV, __PROD) | + DRF_DEF(_PPRIV_SYSB, _CG1, _SLCG_PM, __PROD) | + DRF_DEF(_PPRIV_SYSB, _CG1, _SLCG_PRIV_CONFIG_REGS, __PROD) | + DRF_DEF(_PPRIV_SYSB, _CG1, _SLCG_PRIV_FUNNEL_ARB, __PROD) | + DRF_DEF(_PPRIV_SYSB, _CG1, _SLCG_PRIV_FUNNEL_DECODER, __PROD) | + DRF_DEF(_PPRIV_SYSB, _CG1, _SLCG_PRIV_HISTORY_BUFFER, __PROD) | + DRF_DEF(_PPRIV_SYSB, _CG1, _SLCG_PRIV_MASTER, __PROD) | + DRF_DEF(_PPRIV_SYSB, _CG1, _SLCG_PRIV_SLAVE, __PROD) | + DRF_DEF(_PPRIV_SYSB, _CG1, _SLCG_SLOWCLK, __PROD)); + + NVSWITCH_ENG_WR32(device, SYSB_PRI_RS_CTRL, , 0, _PPRIV_RS_CTRL_SYSB, _CG1, + DRF_DEF(_PPRIV_RS_CTRL_SYSB, _CG1, _SLCG, __PROD)); + + NVSWITCH_ENG_WR32(device, SYS_PRI_HUB, , 0, _PPRIV_SYS, _CG1, + DRF_DEF(_PPRIV_SYS, _CG1, _SLCG_LOC_PRIV, __PROD) | + DRF_DEF(_PPRIV_SYS, _CG1, _SLCG_PM, __PROD) | + DRF_DEF(_PPRIV_SYS, _CG1, _SLCG_PRIV_CONFIG_REGS, __PROD) | + DRF_DEF(_PPRIV_SYS, _CG1, _SLCG_PRIV_FUNNEL_ARB, __PROD) | + DRF_DEF(_PPRIV_SYS, _CG1, _SLCG_PRIV_FUNNEL_DECODER, __PROD) | + DRF_DEF(_PPRIV_SYS, _CG1, _SLCG_PRIV_HISTORY_BUFFER, __PROD) | + DRF_DEF(_PPRIV_SYS, _CG1, _SLCG_PRIV_MASTER, __PROD) | + DRF_DEF(_PPRIV_SYS, _CG1, _SLCG_PRIV_SLAVE, __PROD) | + DRF_DEF(_PPRIV_SYS, _CG1, _SLCG_SLOWCLK, __PROD)); + + NVSWITCH_ENG_WR32(device, SYS_PRI_RS_CTRL, , 0, _PPRIV_RS_CTRL_SYS, _CG1, + DRF_DEF(_PPRIV_RS_CTRL_SYS, _CG1, _SLCG, __PROD)); + + NVSWITCH_ENG_WR32(device, XAL, , 0, _XAL_EP, _CG, + DRF_DEF(_XAL_EP, _CG, _IDLE_CG_DLY_CNT, __PROD) | + DRF_DEF(_XAL_EP, _CG, _IDLE_CG_EN, __PROD) | + DRF_DEF(_XAL_EP, _CG, _STALL_CG_EN, __PROD) | + DRF_DEF(_XAL_EP, _CG, _WAKEUP_DLY_CNT, __PROD)); + + NVSWITCH_ENG_WR32(device, XAL, , 0, _XAL_EP, _CG1, + DRF_DEF(_XAL_EP, _CG1, _MONITOR_CG_EN, __PROD) | + DRF_DEF(_XAL_EP, _CG1, _SLCG_DFD, __PROD) | + DRF_DEF(_XAL_EP, _CG1, _SLCG_DOWNARB, __PROD) | + DRF_DEF(_XAL_EP, _CG1, _SLCG_FASTFLUSH, __PROD) | + DRF_DEF(_XAL_EP, _CG1, _SLCG_FBI_UP, __PROD) | + DRF_DEF(_XAL_EP, _CG1, _SLCG_JOIN, __PROD) | + DRF_DEF(_XAL_EP, _CG1, _SLCG_JTAG, __PROD) | + DRF_DEF(_XAL_EP, _CG1, _SLCG_MEMOP, __PROD) | + DRF_DEF(_XAL_EP, _CG1, _SLCG_MEMRSP, __PROD) | + DRF_DEF(_XAL_EP, _CG1, _SLCG_MSIX, __PROD) | + DRF_DEF(_XAL_EP, _CG1, _SLCG_PM, __PROD) | + DRF_DEF(_XAL_EP, _CG1, _SLCG_PRIREQ, __PROD) | + DRF_DEF(_XAL_EP, _CG1, _SLCG_PRIRSP, __PROD) | + DRF_DEF(_XAL_EP, _CG1, _SLCG_PRI_TRACKER, __PROD) | + DRF_DEF(_XAL_EP, _CG1, _SLCG_RXMAP, __PROD) | + DRF_DEF(_XAL_EP, _CG1, _SLCG_TXMAP, __PROD) | + DRF_DEF(_XAL_EP, _CG1, _SLCG_UNROLL_MEM, __PROD) | + DRF_DEF(_XAL_EP, _CG1, _SLCG_UPARB, __PROD)); + + NVSWITCH_ENG_WR32(device, XPL, , 0, _XPL, _PL_PAD_CTL_PRI_XPL_RXCLK_CG, + DRF_DEF(_XPL, _PL_PAD_CTL_PRI_XPL_RXCLK_CG, _IDLE_CG_DLY_CNT, __PROD) | + DRF_DEF(_XPL, _PL_PAD_CTL_PRI_XPL_RXCLK_CG, _IDLE_CG_EN, __PROD) | + DRF_DEF(_XPL, _PL_PAD_CTL_PRI_XPL_RXCLK_CG, _STALL_CG_EN, __PROD) | + DRF_DEF(_XPL, _PL_PAD_CTL_PRI_XPL_RXCLK_CG, _WAKEUP_DLY_CNT, __PROD)); + + NVSWITCH_ENG_WR32(device, XPL, , 0, _XPL, _PL_PAD_CTL_PRI_XPL_RXCLK_CG1, + DRF_DEF(_XPL, _PL_PAD_CTL_PRI_XPL_RXCLK_CG1, _MONITOR_CG_EN, __PROD) | + DRF_DEF(_XPL, _PL_PAD_CTL_PRI_XPL_RXCLK_CG1, _SLCG, __PROD)); + + NVSWITCH_ENG_WR32(device, XPL, , 0, _XPL, _PL_PAD_CTL_PRI_XPL_TXCLK_CG, + DRF_DEF(_XPL, _PL_PAD_CTL_PRI_XPL_TXCLK_CG, _IDLE_CG_DLY_CNT, __PROD) | + DRF_DEF(_XPL, _PL_PAD_CTL_PRI_XPL_TXCLK_CG, _IDLE_CG_EN, __PROD) | + DRF_DEF(_XPL, _PL_PAD_CTL_PRI_XPL_TXCLK_CG, _STALL_CG_EN, __PROD) | + DRF_DEF(_XPL, _PL_PAD_CTL_PRI_XPL_TXCLK_CG, _WAKEUP_DLY_CNT, __PROD)); + + NVSWITCH_ENG_WR32(device, XPL, , 0, _XPL, _PL_PAD_CTL_PRI_XPL_TXCLK_CG1, + DRF_DEF(_XPL, _PL_PAD_CTL_PRI_XPL_TXCLK_CG1, _MONITOR_CG_EN, __PROD) | + DRF_DEF(_XPL, _PL_PAD_CTL_PRI_XPL_TXCLK_CG1, _SLCG, __PROD)); + + NVSWITCH_ENG_WR32(device, XPL, , 0, _XPL, _PL_PAD_CTL_PRI_XPL_XCLK_CG, + DRF_DEF(_XPL, _PL_PAD_CTL_PRI_XPL_XCLK_CG, _IDLE_CG_DLY_CNT, __PROD) | + DRF_DEF(_XPL, _PL_PAD_CTL_PRI_XPL_XCLK_CG, _IDLE_CG_EN, __PROD) | + DRF_DEF(_XPL, _PL_PAD_CTL_PRI_XPL_XCLK_CG, _STALL_CG_EN, __PROD) | + DRF_DEF(_XPL, _PL_PAD_CTL_PRI_XPL_XCLK_CG, _WAKEUP_DLY_CNT, __PROD)); + + NVSWITCH_ENG_WR32(device, XPL, , 0, _XPL, _PL_PAD_CTL_PRI_XPL_XCLK_CG1, + DRF_DEF(_XPL, _PL_PAD_CTL_PRI_XPL_XCLK_CG1, _MONITOR_CG_EN, __PROD) | + DRF_DEF(_XPL, _PL_PAD_CTL_PRI_XPL_XCLK_CG1, _SLCG, __PROD)); + + NVSWITCH_ENG_WR32(device, XPL, , 0, _XPL, _XTLQ_PRI_XTL_Q_CG, + DRF_DEF(_XPL, _XTLQ_PRI_XTL_Q_CG, _IDLE_CG_DLY_CNT, __PROD) | + DRF_DEF(_XPL, _XTLQ_PRI_XTL_Q_CG, _IDLE_CG_EN, __PROD) | + DRF_DEF(_XPL, _XTLQ_PRI_XTL_Q_CG, _STALL_CG_EN, __PROD) | + DRF_DEF(_XPL, _XTLQ_PRI_XTL_Q_CG, _WAKEUP_DLY_CNT, __PROD)); + + NVSWITCH_ENG_WR32(device, XPL, , 0, _XPL, _XTLQ_PRI_XTL_Q_CG1, + DRF_DEF(_XPL, _XTLQ_PRI_XTL_Q_CG1, _MONITOR_CG_EN, __PROD) | + DRF_DEF(_XPL, _XTLQ_PRI_XTL_Q_CG1, _SLCG, __PROD)); + + NVSWITCH_ENG_WR32(device, XTL, , 0, _XTL, _EP_PRI_XTL_EP_CG, + DRF_DEF(_XTL, _EP_PRI_XTL_EP_CG, _IDLE_CG_DLY_CNT, __PROD) | + DRF_DEF(_XTL, _EP_PRI_XTL_EP_CG, _IDLE_CG_EN, __PROD) | + DRF_DEF(_XTL, _EP_PRI_XTL_EP_CG, _STALL_CG_EN, __PROD) | + DRF_DEF(_XTL, _EP_PRI_XTL_EP_CG, _WAKEUP_DLY_CNT, __PROD)); + + NVSWITCH_ENG_WR32(device, XTL, , 0, _XTL, _EP_PRI_XTL_EP_CG1, + DRF_DEF(_XTL, _EP_PRI_XTL_EP_CG1, _MONITOR_CG_EN, __PROD) | + DRF_DEF(_XTL, _EP_PRI_XTL_EP_CG1, _SLCG, __PROD)); + + return NVL_SUCCESS; +} + + +/* + * @Brief : Fill In + * + * @Description : Fill In + * + * @paramin : Fill In + * + */ + +NvlStatus +nvswitch_npg_init_ls10 +( + nvswitch_device *device +) +{ + NvU32 command; + NvBool keepPolling; + NVSWITCH_TIMEOUT timeout; + + // .Non-Routing initialzation of NPG + + // . Clear all the routing rams, use broadcast write + + // .. _Note_ : There are 6 new RAMs to initialize + + NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _NPORT, _INITIALIZATION, + DRF_DEF(_NPORT, _INITIALIZATION, _EXTMCRIDINIT, _HWINIT) | + DRF_DEF(_NPORT, _INITIALIZATION, _LINKTABLEINIT, _HWINIT) | + DRF_DEF(_NPORT, _INITIALIZATION, _MCREDBUFINIT, _HWINIT) | + DRF_DEF(_NPORT, _INITIALIZATION, _MCREDSGTINIT, _HWINIT) | + DRF_DEF(_NPORT, _INITIALIZATION, _MCREMAPTABINIT, _HWINIT) | + DRF_DEF(_NPORT, _INITIALIZATION, _MCRIDINIT, _HWINIT) | + DRF_DEF(_NPORT, _INITIALIZATION, _MCTAGSTATEINIT, _HWINIT) | + DRF_DEF(_NPORT, _INITIALIZATION, _RDTAGSTATEINIT, _HWINIT) | + DRF_DEF(_NPORT, _INITIALIZATION, _REMAPTABINIT, _HWINIT) | + DRF_DEF(_NPORT, _INITIALIZATION, _RIDTABINIT, _HWINIT) | + DRF_DEF(_NPORT, _INITIALIZATION, _RLANTABINIT, _HWINIT) | + DRF_DEF(_NPORT, _INITIALIZATION, _TAGPOOLINIT_0, _HWINIT)); + + // . Ensure RAM initialization has completed, use broadcast read + + nvswitch_timeout_create(NVSWITCH_INTERVAL_1MSEC_IN_NS, &timeout); + + do + { + keepPolling = (nvswitch_timeout_check(&timeout)) ? NV_FALSE : NV_TRUE; + command = NVSWITCH_ENG_RD32(device, NPORT, _BCAST, 0, _NPORT, _INITIALIZATION); + + if ( FLD_TEST_DRF(_NPORT, _INITIALIZATION, _EXTMCRIDINIT, _HWINIT, command) && + FLD_TEST_DRF(_NPORT, _INITIALIZATION, _LINKTABLEINIT, _HWINIT, command) && + FLD_TEST_DRF(_NPORT, _INITIALIZATION, _MCREDBUFINIT, _HWINIT, command) && + FLD_TEST_DRF(_NPORT, _INITIALIZATION, _MCREDSGTINIT, _HWINIT, command) && + FLD_TEST_DRF(_NPORT, _INITIALIZATION, _MCREMAPTABINIT, _HWINIT, command) && + FLD_TEST_DRF(_NPORT, _INITIALIZATION, _MCRIDINIT, _HWINIT, command) && + FLD_TEST_DRF(_NPORT, _INITIALIZATION, _MCTAGSTATEINIT, _HWINIT, command) && + FLD_TEST_DRF(_NPORT, _INITIALIZATION, _RDTAGSTATEINIT, _HWINIT, command) && + FLD_TEST_DRF(_NPORT, _INITIALIZATION, _REMAPTABINIT, _HWINIT, command) && + FLD_TEST_DRF(_NPORT, _INITIALIZATION, _RIDTABINIT, _HWINIT, command) && + FLD_TEST_DRF(_NPORT, _INITIALIZATION, _RLANTABINIT, _HWINIT, command) && + FLD_TEST_DRF(_NPORT, _INITIALIZATION, _TAGPOOLINIT_0, _HWINIT, command) ) + { + break; + } + if ( keepPolling == NV_FALSE ) + { + NVSWITCH_PRINT(device, ERROR, "%s: -- Poll timeout for NPORT 0 _NPORT _INITIALIZATION --\n", __FUNCTION__); + return -NVL_ERR_GENERIC; + } + } + while (keepPolling); + + return NVL_SUCCESS; +} + + +/* + * @Brief : Fill In + * + * @Description : Fill In + * + * @paramin : Fill In + * + */ +#if 0 +NvlStatus +nvswitch_npg_trunk_prod_ls10 +( + nvswitch_device *device +) +{ + + + // .NPG PROD value for Trunk Links + + // _NOTE_: Added 8/11/2021 + + + // *** Software needs to update this function support passing of instance as it is hardcoded to port 0 + + NVSWITCH_ENG_WR32(device, NPORT, , 0, _EGRESS, _CTRL, + DRF_DEF(_EGRESS, _CTRL, _CTO_ENB, __TPROD) | + DRF_DEF(_EGRESS, _CTRL, _ZERO_OUT_SWXATTR_DISABLE, _OFF)); + + NVSWITCH_ENG_WR32(device, NPORT, , 0, _EGRESS, _ERR_CONTAIN_EN_0, + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _CREDIT_TIME_OUT_ERR, __TPROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _EGRESSBUFERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _HWRSPERR, __TPROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _INVALIDVCSET_ERR, __TPROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _NCISOCCREDITOVFL, __PROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _NCISOC_CREDIT_PARITY_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _NXBAR_FLITTYPE_MISMATCH_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _NXBAR_HDR_ECC_DBE_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _NXBAR_HDR_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _NXBAR_HDR_PARITY_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _NXBAR_SIDEBAND_PD_PARITY_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _PKTROUTEERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _PRIVRSPERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _RAM_OUT_HDR_ECC_DBE_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _RAM_OUT_HDR_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _REQTGTIDMISMATCHERR, __TPROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _RFU, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _RSPREQIDMISMATCHERR, __TPROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _SEQIDERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_CONTAIN_EN_0, _URRSPERR, __TPROD)); + + NVSWITCH_ENG_WR32(device, NPORT, , 0, _EGRESS, _ERR_FATAL_REPORT_EN_0, + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _CREDIT_TIME_OUT_ERR, __TPROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _EGRESSBUFERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _HWRSPERR, __TPROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _INVALIDVCSET_ERR, __TPROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _NCISOCCREDITOVFL, __PROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _NCISOC_CREDIT_PARITY_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _NXBAR_FLITTYPE_MISMATCH_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _NXBAR_HDR_ECC_DBE_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _NXBAR_HDR_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _NXBAR_HDR_PARITY_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _NXBAR_SIDEBAND_PD_PARITY_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _PKTROUTEERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _PRIVRSPERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _RAM_OUT_HDR_ECC_DBE_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _RAM_OUT_HDR_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _REQTGTIDMISMATCHERR, __TPROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _RFU, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _RSPREQIDMISMATCHERR, __TPROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _SEQIDERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_FATAL_REPORT_EN_0, _URRSPERR, __TPROD)); + + NVSWITCH_ENG_WR32(device, NPORT, , 0, _EGRESS, _ERR_LOG_EN_0, + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _CREDIT_TIME_OUT_ERR, __TPROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _EGRESSBUFERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _HWRSPERR, __TPROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _INVALIDVCSET_ERR, __TPROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _NCISOCCREDITOVFL, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _NCISOC_CREDIT_PARITY_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _NXBAR_FLITTYPE_MISMATCH_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _NXBAR_HDR_ECC_DBE_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _NXBAR_HDR_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _NXBAR_HDR_PARITY_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _NXBAR_SIDEBAND_PD_PARITY_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _PKTROUTEERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _PRIVRSPERR, __TPROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _RAM_OUT_HDR_ECC_DBE_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _RAM_OUT_HDR_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _REQTGTIDMISMATCHERR, __TPROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _RFU, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _RSPREQIDMISMATCHERR, __TPROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _SEQIDERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_LOG_EN_0, _URRSPERR, __TPROD)); + + NVSWITCH_ENG_WR32(device, NPORT, , 0, _EGRESS, _ERR_NON_FATAL_REPORT_EN_0, + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _CREDIT_TIME_OUT_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EGRESSBUFERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _HWRSPERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _INVALIDVCSET_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _NCISOCCREDITOVFL, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _NCISOC_CREDIT_PARITY_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _NXBAR_FLITTYPE_MISMATCH_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _NXBAR_HDR_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _NXBAR_HDR_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _NXBAR_HDR_PARITY_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _NXBAR_SIDEBAND_PD_PARITY_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _PKTROUTEERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _PRIVRSPERR, __TPROD) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _RAM_OUT_HDR_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _RAM_OUT_HDR_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _REQTGTIDMISMATCHERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _RFU, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _RSPREQIDMISMATCHERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _SEQIDERR, _DISABLE) | + DRF_DEF(_EGRESS, _ERR_NON_FATAL_REPORT_EN_0, _URRSPERR, _DISABLE)); + + NVSWITCH_ENG_WR32(device, NPORT, , 0, _INGRESS, _ERR_CONTAIN_EN_0, + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _ACLFAIL, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _ADDRBOUNDSERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _ADDRTYPEERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _CMDDECODEERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _EXTAREMAPTAB_ACLFAIL, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _EXTAREMAPTAB_ADDRBOUNDSERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _EXTAREMAPTAB_ECC_DBE_ERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _EXTAREMAPTAB_INDEX_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _EXTAREMAPTAB_REQCONTEXTMISMATCHERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _EXTBREMAPTAB_ACLFAIL, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _EXTBREMAPTAB_ADDRBOUNDSERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _EXTBREMAPTAB_ECC_DBE_ERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _EXTBREMAPTAB_INDEX_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _EXTBREMAPTAB_REQCONTEXTMISMATCHERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _INVALIDVCSET, __TPROD) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _MCREMAPTAB_ACLFAIL, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _MCREMAPTAB_ADDRBOUNDSERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _MCREMAPTAB_ECC_DBE_ERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _MCREMAPTAB_INDEX_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _MCREMAPTAB_REQCONTEXTMISMATCHERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _NCISOC_HDR_ECC_DBE_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _NCISOC_HDR_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _NCISOC_PARITY_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _REMAPTAB_ECC_DBE_ERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _REMAPTAB_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _REQCONTEXTMISMATCHERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _RIDTABCFGERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _RIDTAB_ECC_DBE_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _RIDTAB_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _RLANTABCFGERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _RLANTAB_ECC_DBE_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_CONTAIN_EN_0, _RLANTAB_ECC_LIMIT_ERR, _DISABLE)); + + NVSWITCH_ENG_WR32(device, NPORT, , 0, _INGRESS, _ERR_FATAL_REPORT_EN_0, + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _ACLFAIL, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _ADDRBOUNDSERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _ADDRTYPEERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _CMDDECODEERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _EXTAREMAPTAB_ACLFAIL, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _EXTAREMAPTAB_ADDRBOUNDSERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _EXTAREMAPTAB_ECC_DBE_ERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _EXTAREMAPTAB_INDEX_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _EXTAREMAPTAB_REQCONTEXTMISMATCHERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _EXTBREMAPTAB_ACLFAIL, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _EXTBREMAPTAB_ADDRBOUNDSERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _EXTBREMAPTAB_ECC_DBE_ERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _EXTBREMAPTAB_INDEX_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _EXTBREMAPTAB_REQCONTEXTMISMATCHERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _INVALIDVCSET, __TPROD) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _MCREMAPTAB_ACLFAIL, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _MCREMAPTAB_ADDRBOUNDSERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _MCREMAPTAB_ECC_DBE_ERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _MCREMAPTAB_INDEX_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _MCREMAPTAB_REQCONTEXTMISMATCHERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _NCISOC_HDR_ECC_DBE_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _NCISOC_HDR_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _NCISOC_PARITY_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _REMAPTAB_ECC_DBE_ERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _REMAPTAB_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _REQCONTEXTMISMATCHERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _RIDTABCFGERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _RIDTAB_ECC_DBE_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _RIDTAB_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _RLANTABCFGERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _RLANTAB_ECC_DBE_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_FATAL_REPORT_EN_0, _RLANTAB_ECC_LIMIT_ERR, _DISABLE)); + + NVSWITCH_ENG_WR32(device, NPORT, , 0, _INGRESS, _ERR_LOG_EN_0, + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _ACLFAIL, __TPROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _ADDRBOUNDSERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _ADDRTYPEERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _CMDDECODEERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _EXTAREMAPTAB_ACLFAIL, __TPROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _EXTAREMAPTAB_ADDRBOUNDSERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _EXTAREMAPTAB_ECC_DBE_ERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _EXTAREMAPTAB_INDEX_ERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _EXTAREMAPTAB_REQCONTEXTMISMATCHERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _EXTBREMAPTAB_ACLFAIL, __TPROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _EXTBREMAPTAB_ADDRBOUNDSERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _EXTBREMAPTAB_ECC_DBE_ERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _EXTBREMAPTAB_INDEX_ERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _EXTBREMAPTAB_REQCONTEXTMISMATCHERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _INVALIDVCSET, __TPROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _MCREMAPTAB_ACLFAIL, __TPROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _MCREMAPTAB_ADDRBOUNDSERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _MCREMAPTAB_ECC_DBE_ERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _MCREMAPTAB_INDEX_ERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _MCREMAPTAB_REQCONTEXTMISMATCHERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _NCISOC_HDR_ECC_DBE_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _NCISOC_HDR_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _NCISOC_PARITY_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _REMAPTAB_ECC_DBE_ERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _REMAPTAB_ECC_LIMIT_ERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _REQCONTEXTMISMATCHERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _RIDTABCFGERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _RIDTAB_ECC_DBE_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _RIDTAB_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _RLANTABCFGERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _RLANTAB_ECC_DBE_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_0, _RLANTAB_ECC_LIMIT_ERR, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, , 0, _INGRESS, _ERR_LOG_EN_1, + DRF_DEF(_INGRESS, _ERR_LOG_EN_1, _EXTAREMAPTAB_ADDRTYPEERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_1, _EXTAREMAPTAB_ECC_LIMIT_ERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_1, _EXTBREMAPTAB_ADDRTYPEERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_1, _EXTBREMAPTAB_ECC_LIMIT_ERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_1, _MCCMDTOUCADDRERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_1, _MCREMAPTAB_ADDRTYPEERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_1, _MCREMAPTAB_ECC_LIMIT_ERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_LOG_EN_1, _READMCREFLECTMEMERR, __TPROD)); + + NVSWITCH_ENG_WR32(device, NPORT, , 0, _INGRESS, _ERR_NON_FATAL_REPORT_EN_0, + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _ACLFAIL, __TPROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _ADDRBOUNDSERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _ADDRTYPEERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _CMDDECODEERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_ACLFAIL, __TPROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_ADDRBOUNDSERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_INDEX_ERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTAREMAPTAB_REQCONTEXTMISMATCHERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_ACLFAIL, __TPROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_ADDRBOUNDSERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_INDEX_ERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _EXTBREMAPTAB_REQCONTEXTMISMATCHERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _INVALIDVCSET, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_ACLFAIL, __TPROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_ADDRBOUNDSERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_INDEX_ERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _MCREMAPTAB_REQCONTEXTMISMATCHERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _NCISOC_HDR_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _NCISOC_HDR_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _NCISOC_PARITY_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _REMAPTAB_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _REMAPTAB_ECC_LIMIT_ERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _REQCONTEXTMISMATCHERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _RIDTABCFGERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _RIDTAB_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _RIDTAB_ECC_LIMIT_ERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _RLANTABCFGERR, __PROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _RLANTAB_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_0, _RLANTAB_ECC_LIMIT_ERR, __PROD)); + + NVSWITCH_ENG_WR32(device, NPORT, , 0, _INGRESS, _ERR_NON_FATAL_REPORT_EN_1, + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _EXTAREMAPTAB_ADDRTYPEERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _EXTAREMAPTAB_ECC_LIMIT_ERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _EXTBREMAPTAB_ADDRTYPEERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _EXTBREMAPTAB_ECC_LIMIT_ERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCCMDTOUCADDRERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCREMAPTAB_ADDRTYPEERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _MCREMAPTAB_ECC_LIMIT_ERR, __TPROD) | + DRF_DEF(_INGRESS, _ERR_NON_FATAL_REPORT_EN_1, _READMCREFLECTMEMERR, __TPROD)); + + NVSWITCH_ENG_WR32(device, NPORT, , 0, _NPORT, _CTRL, + DRF_DEF(_NPORT, _CTRL, _EGDRAINENB, _DISABLE) | + DRF_DEF(_NPORT, _CTRL, _ENEGRESSDBI, _ENABLE) | + DRF_DEF(_NPORT, _CTRL, _ENROUTEDBI, _ENABLE) | + DRF_DEF(_NPORT, _CTRL, _RTDRAINENB, _DISABLE) | + DRF_DEF(_NPORT, _CTRL, _SPARE, _INIT) | + DRF_DEF(_NPORT, _CTRL, _TRUNKLINKENB, __TPROD)); + + NVSWITCH_ENG_WR32(device, NPORT, , 0, _SOURCETRACK, _ERR_CONTAIN_EN_0, + DRF_DEF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR, __TPROD) | + DRF_DEF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _DUP_CREQ_TCEN0_TAG_ERR, __TPROD) | + DRF_DEF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _INVALID_TCEN0_RSP_ERR, __TPROD) | + DRF_DEF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _INVALID_TCEN1_RSP_ERR, __TPROD) | + DRF_DEF(_SOURCETRACK, _ERR_CONTAIN_EN_0, _SOURCETRACK_TIME_OUT_ERR, __TPROD)); + + NVSWITCH_ENG_WR32(device, NPORT, , 0, _SOURCETRACK, _ERR_FATAL_REPORT_EN_0, + DRF_DEF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR, __TPROD) | + DRF_DEF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR, _DISABLE) | + DRF_DEF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _DUP_CREQ_TCEN0_TAG_ERR, __TPROD) | + DRF_DEF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _INVALID_TCEN0_RSP_ERR, __TPROD) | + DRF_DEF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _INVALID_TCEN1_RSP_ERR, __TPROD) | + DRF_DEF(_SOURCETRACK, _ERR_FATAL_REPORT_EN_0, _SOURCETRACK_TIME_OUT_ERR, __TPROD)); + + NVSWITCH_ENG_WR32(device, NPORT, , 0, _SOURCETRACK, _ERR_LOG_EN_0, + DRF_DEF(_SOURCETRACK, _ERR_LOG_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR, __TPROD) | + DRF_DEF(_SOURCETRACK, _ERR_LOG_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR, __TPROD) | + DRF_DEF(_SOURCETRACK, _ERR_LOG_EN_0, _DUP_CREQ_TCEN0_TAG_ERR, __TPROD) | + DRF_DEF(_SOURCETRACK, _ERR_LOG_EN_0, _INVALID_TCEN0_RSP_ERR, __TPROD) | + DRF_DEF(_SOURCETRACK, _ERR_LOG_EN_0, _INVALID_TCEN1_RSP_ERR, __TPROD) | + DRF_DEF(_SOURCETRACK, _ERR_LOG_EN_0, _SOURCETRACK_TIME_OUT_ERR, __TPROD)); + + NVSWITCH_ENG_WR32(device, NPORT, , 0, _SOURCETRACK, _ERR_NON_FATAL_REPORT_EN_0, + DRF_DEF(_SOURCETRACK, _ERR_NON_FATAL_REPORT_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR, _DISABLE) | + DRF_DEF(_SOURCETRACK, _ERR_NON_FATAL_REPORT_EN_0, _CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR, __TPROD) | + DRF_DEF(_SOURCETRACK, _ERR_NON_FATAL_REPORT_EN_0, _DUP_CREQ_TCEN0_TAG_ERR, _DISABLE) | + DRF_DEF(_SOURCETRACK, _ERR_NON_FATAL_REPORT_EN_0, _INVALID_TCEN0_RSP_ERR, _DISABLE) | + DRF_DEF(_SOURCETRACK, _ERR_NON_FATAL_REPORT_EN_0, _INVALID_TCEN1_RSP_ERR, _DISABLE) | + DRF_DEF(_SOURCETRACK, _ERR_NON_FATAL_REPORT_EN_0, _SOURCETRACK_TIME_OUT_ERR, _DISABLE)); + + return NVL_SUCCESS; +} +#endif + +/* + * @Brief : Fill In + * + * @Description : Fill In + * + * @paramin : Fill In + * + */ + +NvlStatus +nvswitch_npg_buffer_ready_ls10 +( + nvswitch_device *device +) +{ + NvU32 checked_data; + + // .NPG Buffer Ready + + // . Enable Buffer_Ready for NPORT + + // *** Software needs to update this function support passing of instance as it is hardcoded to port 0 + + NVSWITCH_ENG_WR32(device, NPORT, , 0, _NPORT, _CTRL_BUFFER_READY, + DRF_DEF(_NPORT, _CTRL_BUFFER_READY, _BUFFERRDY, _ENABLE)); + + // . Read a Buffer_Ready register to confirm the writes completed. + + checked_data = NVSWITCH_ENG_RD32(device, NPORT, , 0, _NPORT, _CTRL_BUFFER_READY); + if ( !FLD_TEST_DRF(_NPORT, _CTRL_BUFFER_READY, _BUFFERRDY, _ENABLE, checked_data) ) + { + NVSWITCH_PRINT(device, ERROR, "%s: _NPORT, _CTRL_BUFFER_READY, _BUFFERRDY != _ENABLE\n", __FUNCTION__); + } + + return NVL_SUCCESS; +} + + +/* + * @Brief : Fill In + * + * @Description : Fill In + * + * @paramin : Fill In + * + */ + +NvlStatus +nvswitch_nvlw_buffer_ready_ls10 +( + nvswitch_device *device +) +{ + NvU32 checked_data; + NvU32 command; + NvBool keepPolling; + NVSWITCH_TIMEOUT timeout; + + // . NVLW Buffer Ready + + // :: [SW] Enable buffer ready as the last step in initialization + + // . [SW] Enable Buffer_Ready for NLVW + + // *** Software needs to update this function support passing of instance as it is hardcoded to port 0 + + NVSWITCH_ENG_WR32_IDX(device, MINION, , 0, _MINION, _NVLINK_DL_CMD_DATA, 0, + DRF_NUM(_MINION, _NVLINK_DL_CMD_DATA, _DATA, 0x3)); + + NVSWITCH_ENG_WR32_IDX(device, MINION, , 0, _MINION, _NVLINK_DL_CMD, 0, + DRF_DEF(_MINION, _NVLINK_DL_CMD, _COMMAND, _SET_BUFFER_READY)); + + nvswitch_timeout_create(NVSWITCH_INTERVAL_1MSEC_IN_NS, &timeout); + + do + { + keepPolling = (nvswitch_timeout_check(&timeout)) ? NV_FALSE : NV_TRUE; + command = NVSWITCH_ENG_RD32_IDX(device, MINION, , 0, _MINION, _NVLINK_DL_CMD, 0); + + if ( FLD_TEST_DRF(_MINION, _NVLINK_DL_CMD, _READY, _TRUE, command) ) + { + break; + } + if ( keepPolling == NV_FALSE ) + { + NVSWITCH_PRINT(device, ERROR, "%s: -- Poll timeout for MINION 0 _MINION _NVLINK_DL_CMD --\n", __FUNCTION__); + return -NVL_ERR_GENERIC; + } + } + while (keepPolling); + + checked_data = NVSWITCH_ENG_RD32_IDX(device, MINION, , 0, _MINION, _NVLINK_DL_CMD, 0); + if ( !FLD_TEST_DRF(_MINION, _NVLINK_DL_CMD, _FAULT, _NOFAULT_NOCLEAR, checked_data) ) + { + NVSWITCH_PRINT(device, ERROR, "%s: _MINION, _NVLINK_DL_CMD, _FAULT != _NOFAULT_NOCLEAR\n", __FUNCTION__); + } + + checked_data = NVSWITCH_ENG_RD32(device, NVLTLC, , 0, _NVLTLC, _RX_SYS_CTRL_BUFFER_READY); + if ( !FLD_TEST_DRF(_NVLTLC, _RX_SYS_CTRL_BUFFER_READY, _BUFFERRDY, _ENABLE, checked_data) ) + { + NVSWITCH_PRINT(device, ERROR, "%s: _NVLTLC, _RX_SYS_CTRL_BUFFER_READY, _BUFFERRDY != _ENABLE\n", __FUNCTION__); + } + + checked_data = NVSWITCH_ENG_RD32(device, NVLTLC, , 0, _NVLTLC, _TX_SYS_CTRL_BUFFER_READY); + if ( !FLD_TEST_DRF(_NVLTLC, _TX_SYS_CTRL_BUFFER_READY, _BUFFERRDY, _ENABLE, checked_data) ) + { + NVSWITCH_PRINT(device, ERROR, "%s: _NVLTLC, _TX_SYS_CTRL_BUFFER_READY, _BUFFERRDY != _ENABLE\n", __FUNCTION__); + } + + return NVL_SUCCESS; +} + diff --git a/src/common/nvswitch/kernel/ls10/therm_ls10.c b/src/common/nvswitch/kernel/ls10/therm_ls10.c new file mode 100644 index 000000000..1e061bfca --- /dev/null +++ b/src/common/nvswitch/kernel/ls10/therm_ls10.c @@ -0,0 +1,358 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "export_nvswitch.h" + +#include "common_nvswitch.h" +#include "ls10/ls10.h" +#include "ls10/therm_ls10.h" +#include "error_nvswitch.h" +#include "soe/soeiftherm.h" + +#include "nvswitch/ls10/dev_therm.h" + +// +// Thermal functions +// + +// +// Initialize thermal offsets for External Tdiode. +// + +NvlStatus +nvswitch_init_thermal_ls10 +( + nvswitch_device *device +) +{ + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + + // Mark everything invalid + chip_device->tdiode.method = NVSWITCH_THERM_METHOD_UNKNOWN; + + return NVL_SUCCESS; +} + +static void +_nvswitch_read_max_tsense_temperature_ls10 +( + nvswitch_device *device, + NVSWITCH_CTRL_GET_TEMPERATURE_PARAMS *info, + NvU32 channel +) +{ + NvU32 offset; + NvU32 temperature; + + temperature = NVSWITCH_REG_RD32(device, _THERM, _TSENSE_MAXIMUM_TEMPERATURE); + temperature = DRF_VAL(_THERM_TSENSE, _MAXIMUM_TEMPERATURE, _MAXIMUM_TEMPERATURE, temperature); + temperature = NV_TSENSE_FXP_9_5_TO_24_8(temperature); + + if (channel == NVSWITCH_THERM_CHANNEL_LR10_TSENSE_MAX) + { + offset = NVSWITCH_REG_RD32(device, _THERM, _TSENSE_U2_A_0_BJT_0_TEMPERATURE_MODIFICATIONS); + offset = DRF_VAL(_THERM_TSENSE, _U2_A_0_BJT_0_TEMPERATURE_MODIFICATIONS, _TEMPERATURE_OFFSET, offset); + + // Temperature of the sensor reported equals calculation of the max temperature reported + // from the TSENSE HUB plus the temperature offset programmed by SW. This offset needs to + // be substracted to get the actual temperature of the sensor. + temperature -= NV_TSENSE_FXP_9_5_TO_24_8(offset); + } + + info->temperature[channel] = temperature; + info->status[channel] = NVL_SUCCESS; +} + +static void +_nvswitch_read_external_tdiode_temperature_ls10 +( + nvswitch_device *device, + NVSWITCH_CTRL_GET_TEMPERATURE_PARAMS *info, + NvU32 channel +) +{ +} + +// +// nvswitch_therm_read_temperature +// +// Temperature and voltage are only available on SKUs which have thermal and +// voltage sensors. +// + +NvlStatus +nvswitch_ctrl_therm_read_temperature_ls10 +( + nvswitch_device *device, + NVSWITCH_CTRL_GET_TEMPERATURE_PARAMS *info +) +{ + NvU32 channel; + NvU32 val; + NvU32 offset; + + if (!info->channelMask) + { + NVSWITCH_PRINT(device, ERROR, + "%s: No channel given in the input.\n", + __FUNCTION__); + + return -NVL_BAD_ARGS; + } + + nvswitch_os_memset(info->temperature, 0x0, sizeof(info->temperature)); + + channel = NVSWITCH_THERM_CHANNEL_LS10_TSENSE_MAX; + if (info->channelMask & NVBIT(channel)) + { + _nvswitch_read_max_tsense_temperature_ls10(device, info, channel); + info->channelMask &= ~NVBIT(channel); + } + + channel = NVSWITCH_THERM_CHANNEL_LS10_TSENSE_OFFSET_MAX; + if (info->channelMask & NVBIT(channel)) + { + _nvswitch_read_max_tsense_temperature_ls10(device, info, channel); + info->channelMask &= ~NVBIT(channel); + } + + channel = NVSWITCH_THERM_CHANNEL_LS10_TDIODE; + if (info->channelMask & NVBIT(channel)) + { + _nvswitch_read_external_tdiode_temperature_ls10(device, info, channel); + info->channelMask &= ~NVBIT(channel); + } + + channel = NVSWITCH_THERM_CHANNEL_LS10_TDIODE_OFFSET; + if (info->channelMask & NVBIT(channel)) + { + _nvswitch_read_external_tdiode_temperature_ls10(device, info, channel); + info->channelMask &= ~NVBIT(channel); + } + + channel = NVSWITCH_THERM_CHANNEL_LS10_TSENSE_0; + if (info->channelMask & NVBIT(channel)) + { + offset = NVSWITCH_REG_RD32(device, _THERM, _TSENSE_U2_A_0_BJT_0_TEMPERATURE_MODIFICATIONS); + offset = DRF_VAL(_THERM_TSENSE, _U2_A_0_BJT_0_TEMPERATURE_MODIFICATIONS, _TEMPERATURE_OFFSET, offset); + offset = NV_TSENSE_FXP_9_5_TO_24_8(offset); + + val = NVSWITCH_REG_RD32(device, _THERM, _TSENSE_U2_A_0_BJT_0); + val = DRF_VAL(_THERM, _TSENSE_U2_A_0_BJT_0, _TEMPERATURE, val); + val = NV_TSENSE_FXP_9_5_TO_24_8(val); + val -= offset; + + info->temperature[channel] = val; + info->channelMask &= ~NVBIT(channel); + } + + channel = NVSWITCH_THERM_CHANNEL_LS10_TSENSE_1; + if (info->channelMask & NVBIT(channel)) + { + offset = NVSWITCH_REG_RD32(device, _THERM, _TSENSE_U2_A_0_BJT_1_TEMPERATURE_MODIFICATIONS); + offset = DRF_VAL(_THERM_TSENSE, _U2_A_0_BJT_1_TEMPERATURE_MODIFICATIONS, _TEMPERATURE_OFFSET, offset); + offset = NV_TSENSE_FXP_9_5_TO_24_8(offset); + + val = NVSWITCH_REG_RD32(device, _THERM, _TSENSE_U2_A_0_BJT_1); + val = DRF_VAL(_THERM, _TSENSE_U2_A_0_BJT_1, _TEMPERATURE, val); + val = NV_TSENSE_FXP_9_5_TO_24_8(val); + val -= offset; + + info->temperature[channel] = val; + info->channelMask &= ~NVBIT(channel); + } + + channel = NVSWITCH_THERM_CHANNEL_LS10_TSENSE_2; + if (info->channelMask & NVBIT(channel)) + { + offset = NVSWITCH_REG_RD32(device, _THERM, _TSENSE_U2_A_0_BJT_2_TEMPERATURE_MODIFICATIONS); + offset = DRF_VAL(_THERM_TSENSE, _U2_A_0_BJT_2_TEMPERATURE_MODIFICATIONS, _TEMPERATURE_OFFSET, offset); + offset = NV_TSENSE_FXP_9_5_TO_24_8(offset); + + val = NVSWITCH_REG_RD32(device, _THERM, _TSENSE_U2_A_0_BJT_2); + val = DRF_VAL(_THERM, _TSENSE_U2_A_0_BJT_2, _TEMPERATURE, val); + val = NV_TSENSE_FXP_9_5_TO_24_8(val); + val -= offset; + + info->temperature[channel] = val; + info->channelMask &= ~NVBIT(channel); + } + + channel = NVSWITCH_THERM_CHANNEL_LS10_TSENSE_3; + if (info->channelMask & NVBIT(channel)) + { + offset = NVSWITCH_REG_RD32(device, _THERM, _TSENSE_U2_A_0_BJT_3_TEMPERATURE_MODIFICATIONS); + offset = DRF_VAL(_THERM_TSENSE, _U2_A_0_BJT_3_TEMPERATURE_MODIFICATIONS, _TEMPERATURE_OFFSET, offset); + offset = NV_TSENSE_FXP_9_5_TO_24_8(offset); + + val = NVSWITCH_REG_RD32(device, _THERM, _TSENSE_U2_A_0_BJT_3); + val = DRF_VAL(_THERM, _TSENSE_U2_A_0_BJT_3, _TEMPERATURE, val); + val = NV_TSENSE_FXP_9_5_TO_24_8(val); + val -= offset; + + info->temperature[channel] = val; + info->channelMask &= ~NVBIT(channel); + } + + channel = NVSWITCH_THERM_CHANNEL_LS10_TSENSE_4; + if (info->channelMask & NVBIT(channel)) + { + offset = NVSWITCH_REG_RD32(device, _THERM, _TSENSE_U2_A_0_BJT_4_TEMPERATURE_MODIFICATIONS); + offset = DRF_VAL(_THERM_TSENSE, _U2_A_0_BJT_4_TEMPERATURE_MODIFICATIONS, _TEMPERATURE_OFFSET, offset); + offset = NV_TSENSE_FXP_9_5_TO_24_8(offset); + + val = NVSWITCH_REG_RD32(device, _THERM, _TSENSE_U2_A_0_BJT_4); + val = DRF_VAL(_THERM, _TSENSE_U2_A_0_BJT_4, _TEMPERATURE, val); + val = NV_TSENSE_FXP_9_5_TO_24_8(val); + val -= offset; + + info->temperature[channel] = val; + info->channelMask &= ~NVBIT(channel); + } + + channel = NVSWITCH_THERM_CHANNEL_LS10_TSENSE_5; + if (info->channelMask & NVBIT(channel)) + { + offset = NVSWITCH_REG_RD32(device, _THERM, _TSENSE_U2_A_0_BJT_5_TEMPERATURE_MODIFICATIONS); + offset = DRF_VAL(_THERM_TSENSE, _U2_A_0_BJT_5_TEMPERATURE_MODIFICATIONS, _TEMPERATURE_OFFSET, offset); + offset = NV_TSENSE_FXP_9_5_TO_24_8(offset); + + val = NVSWITCH_REG_RD32(device, _THERM, _TSENSE_U2_A_0_BJT_5); + val = DRF_VAL(_THERM, _TSENSE_U2_A_0_BJT_5, _TEMPERATURE, val); + val = NV_TSENSE_FXP_9_5_TO_24_8(val); + val -= offset; + + info->temperature[channel] = val; + info->channelMask &= ~NVBIT(channel); + } + + channel = NVSWITCH_THERM_CHANNEL_LS10_TSENSE_6; + if (info->channelMask & NVBIT(channel)) + { + offset = NVSWITCH_REG_RD32(device, _THERM, _TSENSE_U2_A_0_BJT_6_TEMPERATURE_MODIFICATIONS); + offset = DRF_VAL(_THERM_TSENSE, _U2_A_0_BJT_6_TEMPERATURE_MODIFICATIONS, _TEMPERATURE_OFFSET, offset); + offset = NV_TSENSE_FXP_9_5_TO_24_8(offset); + + val = NVSWITCH_REG_RD32(device, _THERM, _TSENSE_U2_A_0_BJT_6); + val = DRF_VAL(_THERM, _TSENSE_U2_A_0_BJT_6, _TEMPERATURE, val); + val = NV_TSENSE_FXP_9_5_TO_24_8(val); + val -= offset; + + info->temperature[channel] = val; + info->channelMask &= ~NVBIT(channel); + } + + channel = NVSWITCH_THERM_CHANNEL_LS10_TSENSE_7; + if (info->channelMask & NVBIT(channel)) + { + offset = NVSWITCH_REG_RD32(device, _THERM, _TSENSE_U2_A_0_BJT_7_TEMPERATURE_MODIFICATIONS); + offset = DRF_VAL(_THERM_TSENSE, _U2_A_0_BJT_7_TEMPERATURE_MODIFICATIONS, _TEMPERATURE_OFFSET, offset); + offset = NV_TSENSE_FXP_9_5_TO_24_8(offset); + + val = NVSWITCH_REG_RD32(device, _THERM, _TSENSE_U2_A_0_BJT_7); + val = DRF_VAL(_THERM, _TSENSE_U2_A_0_BJT_7, _TEMPERATURE, val); + val = NV_TSENSE_FXP_9_5_TO_24_8(val); + val -= offset; + + info->temperature[channel] = val; + info->channelMask &= ~NVBIT(channel); + } + + channel = NVSWITCH_THERM_CHANNEL_LS10_TSENSE_8; + if (info->channelMask & NVBIT(channel)) + { + offset = NVSWITCH_REG_RD32(device, _THERM, _TSENSE_U2_A_0_BJT_8_TEMPERATURE_MODIFICATIONS); + offset = DRF_VAL(_THERM_TSENSE, _U2_A_0_BJT_8_TEMPERATURE_MODIFICATIONS, _TEMPERATURE_OFFSET, offset); + offset = NV_TSENSE_FXP_9_5_TO_24_8(offset); + + val = NVSWITCH_REG_RD32(device, _THERM, _TSENSE_U2_A_0_BJT_8); + val = DRF_VAL(_THERM, _TSENSE_U2_A_0_BJT_8, _TEMPERATURE, val); + val = NV_TSENSE_FXP_9_5_TO_24_8(val); + val -= offset; + + info->temperature[channel] = val; + info->channelMask &= ~NVBIT(channel); + } + + if (info->channelMask) + { + NVSWITCH_PRINT(device, ERROR, + "%s: ChannelMask %x absent on LS10.\n", + __FUNCTION__, info->channelMask); + + return -NVL_BAD_ARGS; + } + + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_ctrl_therm_get_temperature_limit_ls10 +( + nvswitch_device *device, + NVSWITCH_CTRL_GET_TEMPERATURE_LIMIT_PARAMS *info +) +{ + NvU32 threshold; + NvU32 temperature; + + threshold = nvswitch_reg_read_32(device, NV_THERM_TSENSE_THRESHOLD_TEMPERATURES); + + switch (info->thermalEventId) + { + case NVSWITCH_CTRL_THERMAL_EVENT_ID_WARN: + { + // Get Slowdown temperature + temperature = DRF_VAL(_THERM_TSENSE, _THRESHOLD_TEMPERATURES, + _WARNING_TEMPERATURE, threshold); + break; + } + case NVSWITCH_CTRL_THERMAL_EVENT_ID_OVERT: + { + // Get Shutdown temperature + temperature = DRF_VAL(_THERM_TSENSE, _THRESHOLD_TEMPERATURES, + _OVERTEMP_TEMPERATURE, threshold); + break; + } + default: + { + NVSWITCH_PRINT(device, ERROR, "Invalid Thermal Event Id: 0x%x\n", info->thermalEventId); + return -NVL_BAD_ARGS; + } + } + + info->temperatureLimit = NV_TSENSE_FXP_9_5_TO_24_8(temperature); + + return NVL_SUCCESS; +} + +// Background task to monitor thermal warn and adjust link mode +void +nvswitch_monitor_thermal_alert_ls10 +( + nvswitch_device *device +) +{ + return; +} + diff --git a/src/common/nvswitch/kernel/nvswitch.c b/src/common/nvswitch/kernel/nvswitch.c index db6dbe40e..c02ee199b 100644 --- a/src/common/nvswitch/kernel/nvswitch.c +++ b/src/common/nvswitch/kernel/nvswitch.c @@ -31,6 +31,9 @@ #include "flcn/flcn_nvswitch.h" #include "soe/soe_nvswitch.h" #include "nvVer.h" +#include "nvlink_inband_msg.h" + +static NvlStatus _nvswitch_ctrl_inband_flush_data(nvswitch_device *device, NVSWITCH_INBAND_FLUSH_DATA_PARAMS *p); #define NVSWITCH_DEV_CMD_CHECK_ADMIN NVBIT64(0) #define NVSWITCH_DEV_CMD_CHECK_FM NVBIT64(1) @@ -297,6 +300,14 @@ _nvswitch_corelib_write_discovery_token NvU64 token ) { + nvswitch_device *device = link->dev->pDevInfo; + + if (link->version >= NVLINK_DEVICE_VERSION_40) + { + nvswitch_store_topology_information(device, link); + return NVL_SUCCESS; + } + return NVL_SUCCESS; } @@ -307,7 +318,7 @@ _nvswitch_corelib_ali_training ) { nvswitch_device *device = link->dev->pDevInfo; - return device->hal.nvswitch_launch_ALI_link_training(device, link); + return device->hal.nvswitch_launch_ALI_link_training(device, link, NV_FALSE); } void @@ -379,11 +390,15 @@ _nvswitch_init_device_regkeys NVSWITCH_INIT_REGKEY(_PUBLIC, crc_bit_error_rate_short, NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT, - NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_OFF); + NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_DEFAULT); NVSWITCH_INIT_REGKEY(_PUBLIC, crc_bit_error_rate_long, NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_LONG, - NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_LONG_OFF); + NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_LONG_DEFAULT); + + NVSWITCH_INIT_REGKEY(_PUBLIC, surpress_link_errors_for_gpu_reset, + NV_SWITCH_REGKEY_SURPRESS_LINK_ERRORS_FOR_GPU_RESET, + NV_SWITCH_REGKEY_SURPRESS_LINK_ERRORS_FOR_GPU_RESET_DISABLE); // // Debug use regkeys @@ -505,9 +520,21 @@ _nvswitch_init_device_regkeys NV_SWITCH_REGKEY_I2C_ACCESS_CONTROL, NV_SWITCH_REGKEY_I2C_ACCESS_CONTROL_DEFAULT); + NVSWITCH_INIT_REGKEY(_PRIVATE, force_kernel_i2c, + NV_SWITCH_REGKEY_FORCE_KERNEL_I2C, + NV_SWITCH_REGKEY_FORCE_KERNEL_I2C_DEFAULT); + NVSWITCH_INIT_REGKEY(_PRIVATE, link_recal_settings, NV_SWITCH_REGKEY_LINK_RECAL_SETTINGS, NV_SWITCH_REGKEY_LINK_RECAL_SETTINGS_NOP); + + NVSWITCH_INIT_REGKEY(_PRIVATE, lp_threshold, + NV_SWITCH_REGKEY_SET_LP_THRESHOLD, + NV_SWITCH_REGKEY_SET_LP_THRESHOLD_DEFAULT); + + NVSWITCH_INIT_REGKEY(_PUBLIC, minion_intr, + NV_SWITCH_REGKEY_MINION_INTERRUPTS, + NV_SWITCH_REGKEY_MINION_INTERRUPTS_DEFAULT); } NvU64 nvswitch_lib_deferred_task_dispatcher @@ -518,12 +545,14 @@ nvswitch_lib_deferred_task_dispatcher NvU64 time_nsec; NvU64 time_next_nsec = nvswitch_os_get_platform_time() + 100*NVSWITCH_INTERVAL_1MSEC_IN_NS; NVSWITCH_TASK_TYPE *task; + NVSWITCH_TASK_TYPE *prev_task; if (!NVSWITCH_IS_DEVICE_VALID(device)) { return NV_U64_MAX; } + prev_task = NULL; task = device->tasks; // Walk the task list, executing those whose next execution interval is at hand @@ -541,13 +570,50 @@ nvswitch_lib_deferred_task_dispatcher task->last_run_nsec = time_nsec; // Run the task if (NVSWITCH_IS_DEVICE_INITIALIZED(device) || - (task->flags & NVSWITCH_TASK_TYPE_FLAGS_ALWAYS_RUN)) - (*task->task_fn)(device); + (task->flags & NVSWITCH_TASK_TYPE_FLAGS_RUN_EVEN_IF_DEVICE_NOT_INITIALIZED)) + { + if(task->flags & NVSWITCH_TASK_TYPE_FLAGS_VOID_PTR_ARGS) + (*task->task_fn_vdptr)(device, task->task_args); // run task with provided args + else + (*task->task_fn_devptr)(device); + } } - + // Determine its next run time time_next_nsec = NV_MIN(task->last_run_nsec + task->period_nsec, time_next_nsec); - task = task->next; + + // Advance pointer. If run once flag is set and task ran, remove task from list. + if((task->flags & NVSWITCH_TASK_TYPE_FLAGS_RUN_ONCE) && + (task->last_run_nsec == time_nsec)) + { + prev_task = task->prev; + + // Removing from list head + if (prev_task == NULL) + { + device->tasks = task->next; + if (device->tasks != NULL) + { + device->tasks->prev = NULL; + } + nvswitch_os_free(task); + task = device->tasks; + } + else + { + prev_task->next = task->next; + if (prev_task->next != NULL) + { + prev_task->next->prev = prev_task; + } + nvswitch_os_free(task); + task = prev_task->next; + } + } + else + { + task = task->next; + } } time_nsec = nvswitch_os_get_platform_time(); @@ -568,6 +634,11 @@ _nvswitch_setup_hal nvswitch_setup_hal_lr10(device); return NVL_SUCCESS; } + if (nvswitch_is_ls10_device_id(pci_device_id)) + { + nvswitch_setup_hal_ls10(device); + return NVL_SUCCESS; + } NVSWITCH_PRINT(device, ERROR, "NVSwitch HAL setup failed - Unrecognized PCI Device ID\n"); return -NVL_ERR_NOT_SUPPORTED; @@ -648,6 +719,7 @@ nvswitch_is_soe_supported return device->hal.nvswitch_is_soe_supported(device); } + NvlStatus nvswitch_init_soe ( @@ -744,12 +816,12 @@ _nvswitch_post_init_device_setup } static NvlStatus -_nvswitch_setup_link_system_registers +_nvswitch_setup_system_registers ( nvswitch_device *device ) { - return device->hal.nvswitch_setup_link_system_registers(device); + return device->hal.nvswitch_setup_system_registers(device); } static void @@ -932,14 +1004,27 @@ nvswitch_ctrl_set_fm_driver_state( NVSWITCH_SET_FM_DRIVER_STATE_PARAMS *p ) { + NvU32 prev_fm_status; + if (!NVSWITCH_IS_DEVICE_ACCESSIBLE(device)) { return -NVL_BAD_ARGS; } + prev_fm_status = device->driver_fabric_state; device->driver_fabric_state = p->driverState; device->fabric_state_timestamp = nvswitch_os_get_platform_time(); + if (prev_fm_status != p->driverState) + { + if (nvswitch_lib_notify_client_events(device, + NVSWITCH_DEVICE_EVENT_FABRIC_STATE) != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed to notify event\n", + __FUNCTION__); + } + } + return NVL_SUCCESS; } @@ -1069,12 +1154,100 @@ _nvswitch_ctrl_unregister_events( return NVL_SUCCESS; } +/* + * @Brief : Sends NACK or drops given inband msg based on message type + * + * @Description : + * + * @param[in] device NvSwitch device to contain this link + * @param[in] linkId Link ID + * @param[in] msghdr Header to the message + * + */ +static void +nvswitch_send_nack_or_drop +( + nvswitch_device *device, + NvU32 linkId, + nvlink_inband_msg_header_t *msghdr +) +{ + switch(msghdr->type) + { + case NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_REQ: + device->hal.nvswitch_send_inband_nack(device, (NvU32 *)msghdr, linkId); + NVSWITCH_PRINT(device, ERROR, + "Sending NACK for message (type 0x%x)\n", msghdr->type); + return; + default: + // TODO: Add SXid in future if needed. + NVSWITCH_PRINT(device, ERROR, + "Dropping message (type 0x%x)\n", msghdr->type); + return; + } +} + +/* + * @Brief : Deletes all the entries in persistent or non-persistent lists. + * Send nacks if requested. + * + * @Description : + * + * @param[in] device NVSwitch device to contain this link + * @param[in] linkId Link number + * @param[in] bSendNack Send nacks if true + * @param[in] bNonPersistentOnly Clear only non-persistent list + */ +static void +_nvswitch_inband_clear_lists +( + nvswitch_device *device, + NvU32 linkId, + NvBool bSendNack, + NvBool bNonPersistentOnly +) +{ + nvswitch_inband_data_list *curr = NULL; + nvswitch_inband_data_list *next = NULL; + nvlink_inband_msg_header_t *msghdr = NULL; + + nvListForEachEntry_safe(curr, next, + &device->link[linkId].inbandData.nonpersistent_list, entry) + { + if (bSendNack) + { + msghdr = (nvlink_inband_msg_header_t *)curr->data; + nvswitch_send_nack_or_drop(device, linkId, msghdr); + } + + nvListDel(&curr->entry); + nvswitch_os_free(curr); + } + + if (bNonPersistentOnly) + return; + + nvListForEachEntry_safe(curr, next, + &device->link[linkId].inbandData.persistent_list, entry) + { + if (bSendNack) + { + msghdr = (nvlink_inband_msg_header_t *)curr->data; + nvswitch_send_nack_or_drop(device, linkId, msghdr); + } + + nvListDel(&curr->entry); + nvswitch_os_free(curr); + } +} + static void nvswitch_fabric_state_heartbeat( nvswitch_device *device ) { NvU64 age; + NvU32 linkId; if (!NVSWITCH_IS_DEVICE_VALID(device)) return; @@ -1086,6 +1259,18 @@ nvswitch_fabric_state_heartbeat( age > (NvU64)device->fm_timeout * 1000ULL * 1000ULL) device->driver_fabric_state = NVSWITCH_DRIVER_FABRIC_STATE_MANAGER_TIMEOUT; + // + // If FM is not running, clear pending non-persistent messages. Persistent + // messages can be processed by the FM when it restarts. + // + if (device->driver_fabric_state != NVSWITCH_DRIVER_FABRIC_STATE_CONFIGURED) + { + for (linkId = 0; linkId < nvswitch_get_num_links(device); linkId++) + _nvswitch_inband_clear_lists(device, linkId, + NV_TRUE /* Nack */, + NV_TRUE /* Non-persistent only */); + } + (void)device->hal.nvswitch_write_fabric_state(device); } @@ -1240,8 +1425,12 @@ nvswitch_lib_initialize_device nvswitch_task_create(device, &nvswitch_fabric_state_heartbeat, NVSWITCH_HEARTBEAT_INTERVAL_NS, - NVSWITCH_TASK_TYPE_FLAGS_ALWAYS_RUN); + NVSWITCH_TASK_TYPE_FLAGS_RUN_EVEN_IF_DEVICE_NOT_INITIALIZED); + // + // Blacklisted devices return successfully in order to preserve the fabric state heartbeat + // and ensure OOB utilities don't think the driver has died + // if (device->device_blacklist_reason == NVSWITCH_DEVICE_BLACKLIST_REASON_MANUAL_OUT_OF_BAND) { NVSWITCH_PRINT(device, SETUP, @@ -1250,13 +1439,13 @@ nvswitch_lib_initialize_device device->nvlink_device->pciInfo.bus, device->nvlink_device->pciInfo.device, device->nvlink_device->pciInfo.function); - return retval; + return NVL_SUCCESS; } if (is_blacklisted_by_os) { (void)nvswitch_lib_blacklist_device(device, NVSWITCH_DEVICE_BLACKLIST_REASON_MANUAL_IN_BAND); - return retval; + return NVL_SUCCESS; } for (link_num=0; link_num < nvswitch_get_num_links(device); link_num++) @@ -1365,6 +1554,7 @@ nvswitch_initialize_inforom_fail: nvswitch_initialize_device_state_fail: _nvswitch_destruct_soe(device); + nvswitch_tasks_destroy(device); return retval; } @@ -1426,7 +1616,7 @@ nvswitch_lib_post_init_device __FUNCTION__); } - retval = _nvswitch_setup_link_system_registers(device); + retval = _nvswitch_setup_system_registers(device); if (retval != NVL_SUCCESS) { return retval; @@ -1448,9 +1638,44 @@ nvswitch_lib_post_init_blacklist_device _nvswitch_post_init_blacklist_device_setup(device); } +void +_nvswitch_check_pending_data_and_notify +( + nvswitch_device *device, + NVSWITCH_CLIENT_EVENT *event +) +{ + switch (event->eventId) + { + case NVSWITCH_DEVICE_EVENT_INBAND_DATA: + { + NvU32 i; + + for (i = 0; i < nvswitch_get_num_links(device); i++) + { + if (!nvListIsEmpty(&device->link[i].inbandData.persistent_list) || + !nvListIsEmpty(&device->link[i].inbandData.nonpersistent_list)) + { + (void)nvswitch_os_notify_client_event(device->os_handle, + event->private_driver_data, + event->eventId); + } + } + break; + } + + default: + return; + } +} + /*! * @brief: Gets the client event associated with the file descriptor * if it already exists in the Device's client event list. + * + * If found, and if there is pending data for the event, + * the event is triggered before returning to unblock the + * client right away. */ NvlStatus nvswitch_lib_get_client_event @@ -1474,6 +1699,7 @@ nvswitch_lib_get_client_event if (curr->private_driver_data == osPrivate) { *ppClientEvent = curr; + _nvswitch_check_pending_data_and_notify(device, curr); return NVL_SUCCESS; } } @@ -1654,6 +1880,7 @@ nvswitch_lib_shutdown_device nvswitch_device *device ) { + NVSWITCH_INBAND_FLUSH_DATA_PARAMS p; if (!NVSWITCH_IS_DEVICE_ACCESSIBLE(device)) { @@ -1670,6 +1897,10 @@ nvswitch_lib_shutdown_device nvswitch_hw_counter_shutdown(device); + // FLUSH any pending messages to avoid memory leaks + p.linkMask = nvswitch_get_enabled_link_mask(device); + _nvswitch_ctrl_inband_flush_data(device, &p); + _nvswitch_unregister_links(device); nvswitch_destroy_error_log(device, &device->log_FATAL_ERRORS); @@ -1760,7 +1991,11 @@ nvswitch_lib_get_bios_version return -NVL_BAD_ARGS; ret = device->hal.nvswitch_ctrl_get_bios_info(device, &p); + + if (version != NULL) + { *version = p.version; + } return ret; } @@ -2250,7 +2485,7 @@ nvswitch_timeout_check return (time->timeout_ns <= time_current); } -void +NvlStatus nvswitch_task_create ( nvswitch_device *device, @@ -2259,23 +2494,74 @@ nvswitch_task_create NvU32 flags ) { - NVSWITCH_TASK_TYPE *task = nvswitch_os_malloc(sizeof(*task)); + NVSWITCH_TASK_TYPE *task; + task = nvswitch_os_malloc(sizeof(NVSWITCH_TASK_TYPE)); if (task == NULL) { NVSWITCH_PRINT(device, ERROR, "%s: Unable to allocate task.\n", __FUNCTION__); + return -NVL_NO_MEM; } else { - task->task_fn = task_fn; + task->task_fn_devptr = task_fn; + task->task_args = NULL; task->period_nsec = period_nsec; - task->last_run_nsec = 0; + task->last_run_nsec = nvswitch_os_get_platform_time(); // Prevent deferred tasks from being run immediately task->flags = flags; + task->prev = NULL; task->next = device->tasks; + if (device->tasks != NULL) + { + device->tasks->prev = task; + } device->tasks = task; } + + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_task_create_args +( + nvswitch_device *device, + void *fn_args, + void (*task_fn)(nvswitch_device* device, void *fn_args), + NvU64 period_nsec, + NvU32 flags +) +{ + NVSWITCH_TASK_TYPE *task; + task = nvswitch_os_malloc(sizeof(NVSWITCH_TASK_TYPE)); + + flags = flags | NVSWITCH_TASK_TYPE_FLAGS_VOID_PTR_ARGS; // ensure dispatcher always executes tasks passed through this function with args + + if (task == NULL) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Unable to allocate task.\n", + __FUNCTION__); + return -NVL_NO_MEM; + } + else + { + task->task_fn_vdptr = task_fn; + task->task_args = fn_args; + task->period_nsec = period_nsec; + task->last_run_nsec = nvswitch_os_get_platform_time(); // Prevent deferred tasks from being run immediately + task->flags = flags; + task->prev = NULL; + task->next = device->tasks; + if (device->tasks != NULL) + { + device->tasks->prev = task; + } + device->tasks = task; + } + + return NVL_SUCCESS; } void @@ -2544,7 +2830,7 @@ _nvswitch_ctrl_get_nvlipt_counters // // This control call is now deprecated. // New control call to fetch throughput counters is: - // _nvswitch_ctrl_get_throughput_counters + // nvswitch_ctrl_get_throughput_counters // return -NVL_ERR_NOT_SUPPORTED; } @@ -2559,7 +2845,7 @@ _nvswitch_ctrl_set_nvlipt_counter_config // // This control call is now deprecated. // New control call to fetch throughput counters is: - // _nvswitch_ctrl_get_throughput_counters_lr10 + // nvswitch_ctrl_get_throughput_counters_lr10 // // Setting counter config is not allowed on these // non-configurable counters. These counters are @@ -2578,7 +2864,7 @@ _nvswitch_ctrl_get_nvlipt_counter_config // // This control call is now deprecated. // New control call to fetch throughput counters is: - // _nvswitch_ctrl_get_throughput_counters_lr10 + // nvswitch_ctrl_get_throughput_counters_lr10 // // Getting counter config is useful if counters are // configurable. These counters are not configurable @@ -2587,6 +2873,26 @@ _nvswitch_ctrl_get_nvlipt_counter_config return -NVL_ERR_NOT_SUPPORTED; } +static NvlStatus +_nvswitch_ctrl_register_read +( + nvswitch_device *device, + NVSWITCH_REGISTER_READ *p +) +{ + return device->hal.nvswitch_ctrl_register_read(device, p); +} + +static NvlStatus +_nvswitch_ctrl_register_write +( + nvswitch_device *device, + NVSWITCH_REGISTER_WRITE *p +) +{ + return device->hal.nvswitch_ctrl_register_write(device, p); +} + NvU32 nvswitch_i2c_get_port_info ( @@ -2627,6 +2933,16 @@ _nvswitch_ctrl_get_bios_info return device->hal.nvswitch_ctrl_get_bios_info(device, p); } +static NvlStatus +_nvswitch_ctrl_get_inforom_version +( + nvswitch_device *device, + NVSWITCH_GET_INFOROM_VERSION_PARAMS *p +) +{ + return device->hal.nvswitch_ctrl_get_inforom_version(device, p); +} + NvlStatus nvswitch_ctrl_set_latency_bins ( @@ -2647,8 +2963,8 @@ _nvswitch_ctrl_get_ingress_reqlinkid return device->hal.nvswitch_ctrl_get_ingress_reqlinkid(device, params); } -static NvlStatus -_nvswitch_ctrl_get_throughput_counters +NvlStatus +nvswitch_ctrl_get_throughput_counters ( nvswitch_device *device, NVSWITCH_GET_THROUGHPUT_COUNTERS_PARAMS *p @@ -2724,6 +3040,26 @@ _nvswitch_ctrl_get_nvlink_ecc_errors return device->hal.nvswitch_get_nvlink_ecc_errors(device, params); } +static NvlStatus +_nvswitch_ctrl_set_mc_rid_table +( + nvswitch_device *device, + NVSWITCH_SET_MC_RID_TABLE_PARAMS *p +) +{ + return device->hal.nvswitch_ctrl_set_mc_rid_table(device, p); +} + +static NvlStatus +_nvswitch_ctrl_get_mc_rid_table +( + nvswitch_device *device, + NVSWITCH_GET_MC_RID_TABLE_PARAMS *p +) +{ + return device->hal.nvswitch_ctrl_get_mc_rid_table(device, p); +} + static NvlStatus _nvswitch_ctrl_set_residency_bins ( @@ -2794,38 +3130,6 @@ _nvswitch_ctrl_inband_read_data return device->hal.nvswitch_ctrl_inband_read_data(device, p); } -/* - * @Brief : Deletes all the entires in persistant or nonpersistant list - * - * @Description : - * - * @param[in] device NvSwitch device to contain this link - * @param[in] linkId link number of the link - * - */ -static void -_nvswitch_inband_clear_list -( - nvswitch_device *device, - NvU32 linkId -) -{ - nvswitch_inband_data_list *curr = NULL; - nvswitch_inband_data_list *next = NULL; - - nvListForEachEntry_safe(curr, next, &device->link[linkId].inbandData.persistent_list, entry) - { - nvListDel(&curr->entry); - nvswitch_os_free(curr); - } - - nvListForEachEntry_safe(curr, next, &device->link[linkId].inbandData.nonpersistent_list, entry) - { - nvListDel(&curr->entry); - nvswitch_os_free(curr); - } -} - static NvlStatus _nvswitch_ctrl_inband_flush_data ( @@ -2847,9 +3151,16 @@ _nvswitch_ctrl_inband_flush_data FOR_EACH_INDEX_IN_MASK(64, i, p->linkMask) { if (nvswitch_is_link_valid(device, i) && - (enabledLinkMask & NVBIT(i))) + (enabledLinkMask & NVBIT64(i))) { - _nvswitch_inband_clear_list(device, i); + // + // Flush is expected to clear both persistent and non-persistent + // list. FM does flush when it wants to drop (ignore) all pending + // messages w/o any NACKs. + // + _nvswitch_inband_clear_lists(device, i, + NV_FALSE /* Nack */, + NV_FALSE /* Non-persistent only */); } } FOR_EACH_INDEX_IN_MASK_END; @@ -2872,16 +3183,16 @@ _nvswitch_ctrl_inband_pending_data_stats for (link_num = 0; link_num < nvswitch_get_num_links(device); link_num++) { if (nvswitch_is_link_valid(device, link_num) && - (enabledLinkMask & NVBIT(link_num))) + (enabledLinkMask & NVBIT64(link_num))) { if (!nvListIsEmpty(&device->link[link_num].inbandData.persistent_list)) { - persistent_mask |= NVBIT(link_num); + persistent_mask |= NVBIT64(link_num); } if (!nvListIsEmpty(&device->link[link_num].inbandData.nonpersistent_list)) { - nonpersistent_mask |= NVBIT(link_num); + nonpersistent_mask |= NVBIT64(link_num); } } } @@ -3100,6 +3411,8 @@ nvswitch_inband_read_data if (nvListIsEmpty(&device->link[linkId].inbandData.persistent_list) && nvListIsEmpty(&device->link[linkId].inbandData.nonpersistent_list)) { + NVSWITCH_PRINT(device, ERROR, "%s: LinkId %d doesnt have any data to send\n", + __FUNCTION__, linkId); *dataSize = 0; return -NVL_NOT_FOUND; } @@ -3120,6 +3433,34 @@ nvswitch_inband_read_data return NVL_SUCCESS; } +/* + * @Brief : Returns NV_TRUE if the given inband msg + * needs to go to persistant list + * + * @Description : + * + * @param[in] device NvSwitch device to contain this link + * @param[in] msghdr Header to the message + * + */ + +static NvBool +nvswitch_is_message_persistent +( + nvswitch_device *device, + nvlink_inband_msg_header_t *msghdr +) +{ + // We expect only one message per received data + switch(msghdr->type) + { + case NVLINK_INBAND_MSG_TYPE_MC_TEAM_RELEASE_REQ: + return NV_TRUE; + default: + return NV_FALSE; + } +} + /* * @Brief : Moves the data into persistant or nonpersistant list * @@ -3136,6 +3477,60 @@ nvswitch_filter_messages NvU32 linkId ) { + NvlStatus status; + nvlink_inband_msg_header_t *msghdr = NULL; + nvswitch_inband_data_list *msg = device->link[linkId].inbandData.message; + NvU8 *buffer = device->link[linkId].inbandData.message->data; + NVSWITCH_DRIVER_FABRIC_STATE driver_fabric_state = 0; + NvBool bSendNackOrDrop = NV_FALSE; + + NVSWITCH_ASSERT(nvswitch_lib_read_fabric_state(device, NULL, NULL, + &driver_fabric_state) == NVL_SUCCESS); + + msghdr = (nvlink_inband_msg_header_t*)buffer; + + if (nvswitch_is_message_persistent(device, msghdr)) + { + if (nvListCount(&device->link[linkId].inbandData.persistent_list) < + device->hal.nvswitch_get_max_persistent_message_count(device)) + { + nvListAdd(&msg->entry, &device->link[linkId].inbandData.persistent_list); + } + else + { + bSendNackOrDrop = NV_TRUE; + } + } + else + { + if (driver_fabric_state == NVSWITCH_DRIVER_FABRIC_STATE_CONFIGURED) + { + nvListAdd(&msg->entry, + &device->link[linkId].inbandData.nonpersistent_list); + } + else + { + bSendNackOrDrop = NV_TRUE; + } + } + + if (bSendNackOrDrop) + { + nvswitch_send_nack_or_drop(device, linkId, msghdr); + nvswitch_os_free(msg); + } + else + { + status = nvswitch_lib_notify_client_events(device, + NVSWITCH_DEVICE_EVENT_INBAND_DATA); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed to notify INBAND_DATA event\n", + __FUNCTION__); + } + } + + device->link[linkId].inbandData.message = NULL; } /* @@ -3769,7 +4164,7 @@ nvswitch_lib_smbpbi_log_sxid { va_list arglist; int msglen; - char string[80]; + char string[RM_SOE_SMBPBI_CMD_LOG_MESSAGE_MAX_STRING]; va_start(arglist, pFormat); msglen = nvswitch_os_vsnprintf(string, sizeof(string), pFormat, arglist); @@ -3778,7 +4173,7 @@ nvswitch_lib_smbpbi_log_sxid if (!(msglen < 0)) { msglen = NV_MIN(msglen + 1, (int) sizeof(string)); - nvswitch_smbpbi_log_message(device, sxid, msglen, (NvU8 *) string); + device->hal.nvswitch_smbpbi_log_message(device, sxid, msglen, (NvU8 *) string); } } @@ -4191,10 +4586,51 @@ NvlStatus nvswitch_launch_ALI_link_training ( nvswitch_device *device, + nvlink_link *link, + NvBool bSync +) +{ + return device->hal.nvswitch_launch_ALI_link_training(device, link, bSync); +} + +static NvlStatus +_nvswitch_ctrl_get_err_info +( + nvswitch_device *device, + NVSWITCH_NVLINK_GET_ERR_INFO_PARAMS *ret +) +{ + return device->hal.nvswitch_ctrl_get_err_info(device, ret); +} + +static NvlStatus +_nvswitch_ctrl_clear_counters +( + nvswitch_device *device, + NVSWITCH_NVLINK_CLEAR_COUNTERS_PARAMS *ret +) +{ + return device->hal.nvswitch_ctrl_clear_counters(device, ret); +} + +void +nvswitch_setup_link_system_registers +( + nvswitch_device *device, nvlink_link *link ) { - return device->hal.nvswitch_launch_ALI_link_training(device, link); + device->hal.nvswitch_setup_link_system_registers(device, link); +} + +void +nvswitch_load_link_disable_settings +( + nvswitch_device *device, + nvlink_link *link +) +{ + device->hal.nvswitch_load_link_disable_settings(device, link); } NvlStatus @@ -4242,7 +4678,7 @@ nvswitch_lib_ctrl _nvswitch_ctrl_therm_read_temperature, NVSWITCH_CTRL_GET_TEMPERATURE_PARAMS); NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_THROUGHPUT_COUNTERS, - _nvswitch_ctrl_get_throughput_counters, + nvswitch_ctrl_get_throughput_counters, NVSWITCH_GET_THROUGHPUT_COUNTERS_PARAMS); NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_FATAL_ERROR_SCOPE, _nvswitch_ctrl_get_fatal_error_scope, @@ -4351,6 +4787,9 @@ nvswitch_lib_ctrl NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_BIOS_INFO, _nvswitch_ctrl_get_bios_info, NVSWITCH_GET_BIOS_INFO_PARAMS); + NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_INFOROM_VERSION, + _nvswitch_ctrl_get_inforom_version, + NVSWITCH_GET_INFOROM_VERSION_PARAMS); NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED( CTRL_NVSWITCH_BLACKLIST_DEVICE, nvswitch_ctrl_blacklist_device, @@ -4386,6 +4825,16 @@ nvswitch_lib_ctrl _nvswitch_ctrl_set_training_error_info, NVSWITCH_SET_TRAINING_ERROR_INFO_PARAMS, osPrivate, flags); + NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED( + CTRL_NVSWITCH_SET_MC_RID_TABLE, + _nvswitch_ctrl_set_mc_rid_table, + NVSWITCH_SET_MC_RID_TABLE_PARAMS, + osPrivate, flags); + NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED( + CTRL_NVSWITCH_GET_MC_RID_TABLE, + _nvswitch_ctrl_get_mc_rid_table, + NVSWITCH_GET_MC_RID_TABLE_PARAMS, + osPrivate, flags); NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED( CTRL_NVSWITCH_GET_COUNTERS, _nvswitch_ctrl_get_counters, @@ -4413,6 +4862,12 @@ nvswitch_lib_ctrl CTRL_NVSWITCH_RESERVED_4); NVSWITCH_DEV_CMD_DISPATCH_RESERVED( CTRL_NVSWITCH_RESERVED_5); + NVSWITCH_DEV_CMD_DISPATCH_RESERVED( + CTRL_NVSWITCH_RESERVED_8); + NVSWITCH_DEV_CMD_DISPATCH_RESERVED( + CTRL_NVSWITCH_RESERVED_9); + NVSWITCH_DEV_CMD_DISPATCH_RESERVED( + CTRL_NVSWITCH_RESERVED_10); NVSWITCH_DEV_CMD_DISPATCH( CTRL_NVSWITCH_GET_TEMPERATURE_LIMIT, _nvswitch_ctrl_therm_get_temperature_limit, @@ -4488,6 +4943,23 @@ nvswitch_lib_ctrl _nvswitch_ctrl_get_sw_info, NVSWITCH_GET_SW_INFO_PARAMS, osPrivate, flags); + NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(CTRL_NVSWITCH_REGISTER_READ, + _nvswitch_ctrl_register_read, + NVSWITCH_REGISTER_READ, + osPrivate, flags); + NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(CTRL_NVSWITCH_REGISTER_WRITE, + _nvswitch_ctrl_register_write, + NVSWITCH_REGISTER_WRITE, + osPrivate, flags); + NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(CTRL_NVSWITCH_GET_ERR_INFO, + _nvswitch_ctrl_get_err_info, + NVSWITCH_NVLINK_GET_ERR_INFO_PARAMS, + osPrivate, flags); + NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(CTRL_NVSWITCH_CLEAR_COUNTERS, + _nvswitch_ctrl_clear_counters, + NVSWITCH_NVLINK_CLEAR_COUNTERS_PARAMS, + osPrivate, flags); + default: nvswitch_os_print(NVSWITCH_DBG_LEVEL_INFO, "unknown ioctl %x\n", cmd); retval = -NVL_BAD_ARGS; diff --git a/src/common/nvswitch/kernel/pmgr_nvswitch.c b/src/common/nvswitch/kernel/pmgr_nvswitch.c index 8c59a9b3c..3721c0957 100644 --- a/src/common/nvswitch/kernel/pmgr_nvswitch.c +++ b/src/common/nvswitch/kernel/pmgr_nvswitch.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -24,6 +24,7 @@ #include "common_nvswitch.h" #include "error_nvswitch.h" #include "pmgr_nvswitch.h" +#include "soe/soeifcore.h" void nvswitch_i2c_init @@ -32,6 +33,12 @@ nvswitch_i2c_init ) { PNVSWITCH_OBJI2C pI2c = nvswitch_os_malloc(sizeof(struct NVSWITCH_OBJI2C)); + + if (pI2c == NULL) + { + device->pI2c = NULL; + return; + } nvswitch_os_memset(pI2c, 0, sizeof(struct NVSWITCH_OBJI2C)); device->pI2c = pI2c; } @@ -43,7 +50,18 @@ nvswitch_i2c_destroy ) { if (device->pI2c == NULL) + { return; + } + + if (device->pI2c->soeI2CSupported) + { + nvswitch_os_unmap_dma_region(device->os_handle, device->pI2c->pCpuAddr, device->pI2c->dmaHandle, + SOE_I2C_DMA_BUF_SIZE, NVSWITCH_DMA_DIR_BIDIRECTIONAL); + nvswitch_os_free_contig_memory(device->os_handle, device->pI2c->pCpuAddr, SOE_I2C_DMA_BUF_SIZE); + device->pI2c->pCpuAddr = NULL; + device->pI2c->dmaHandle = 0; + } nvswitch_os_free(device->pI2c); device->pI2c = NULL; diff --git a/src/common/nvswitch/kernel/smbpbi_nvswitch.c b/src/common/nvswitch/kernel/smbpbi_nvswitch.c index 6e4389073..3816cecbe 100644 --- a/src/common/nvswitch/kernel/smbpbi_nvswitch.c +++ b/src/common/nvswitch/kernel/smbpbi_nvswitch.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -32,47 +32,6 @@ #include "rmflcncmdif_nvswitch.h" -#define GET_PFIFO_FROM_DEVICE(dev) (&(dev)->pSmbpbi->sharedSurface->inforomObjects.DEM.object.v1) - -#define DEM_FIFO_SIZE INFOROM_DEM_OBJECT_V1_00_FIFO_SIZE -#define DEM_FIFO_PTR(x) ((x) % DEM_FIFO_SIZE) -#define DEM_PTR_DIFF(cur, next) (((next) > (cur)) ? ((next) - (cur)) : \ - (DEM_FIFO_SIZE - ((cur) - (next)))) -#define DEM_BYTES_OCCUPIED(pf) DEM_PTR_DIFF((pf)->readOffset, (pf)->writeOffset) -// -// See how much space is available in the FIFO. -// Must leave 1 word free so the write pointer does not -// catch up with the read pointer. That would be indistinguishable -// from an empty FIFO. -// -#define DEM_BYTES_AVAILABLE(pf) (DEM_PTR_DIFF((pf)->writeOffset, (pf)->readOffset) - \ - sizeof(NvU32)) -#define DEM_RECORD_SIZE_MAX (sizeof(NV_MSGBOX_DEM_RECORD) \ - + NV_MSGBOX_MAX_DRIVER_EVENT_MSG_TXT_SIZE) -#define DEM_RECORD_SIZE_MIN (sizeof(NV_MSGBOX_DEM_RECORD) + 1) - -#define FIFO_REC_LOOP_ITERATOR _curPtr -#define FIFO_REC_LOOP_REC_PTR _recPtr -#define FIFO_REC_LOOP_REC_SIZE _recSize -#define FIFO_REC_LOOP_START(pf, cond) \ -{ \ - NvU16 _nextPtr; \ - for (FIFO_REC_LOOP_ITERATOR = (pf)->readOffset; cond; FIFO_REC_LOOP_ITERATOR = _nextPtr) \ - { \ - NV_MSGBOX_DEM_RECORD *FIFO_REC_LOOP_REC_PTR = (NV_MSGBOX_DEM_RECORD *) \ - ((pf)->fifoBuffer + FIFO_REC_LOOP_ITERATOR); \ - NvU16 FIFO_REC_LOOP_REC_SIZE = \ - FIFO_REC_LOOP_REC_PTR->recordSize * sizeof(NvU32); - -#define FIFO_REC_LOOP_END \ - _nextPtr = DEM_FIFO_PTR(FIFO_REC_LOOP_ITERATOR + FIFO_REC_LOOP_REC_SIZE); \ - } \ -} - -static void _smbpbiDemInit(nvswitch_device *device, struct smbpbi *pSmbpbi, struct INFOROM_DEM_OBJECT_V1_00 *pFifo); -static void _nvswitch_smbpbi_dem_flush(nvswitch_device *device); - - NvlStatus nvswitch_smbpbi_init ( @@ -80,55 +39,36 @@ nvswitch_smbpbi_init ) { NV_STATUS status; - NvU64 dmaHandle; - void *cpuAddr; if (!device->pSoe) { return -NVL_ERR_INVALID_STATE; } - // Create DMA mapping for SMBPBI transactions - status = nvswitch_os_alloc_contig_memory(device->os_handle, &cpuAddr, - sizeof(SOE_SMBPBI_SHARED_SURFACE), - (device->dma_addr_width == 32)); - if (status != NVL_SUCCESS) - { - NVSWITCH_PRINT(device, ERROR, "Failed to allocate contig memory, rc:%d\n", - status); - return status; - } - - nvswitch_os_memset(cpuAddr, 0, sizeof(SOE_SMBPBI_SHARED_SURFACE)); - - status = nvswitch_os_map_dma_region(device->os_handle, cpuAddr, &dmaHandle, - sizeof(SOE_SMBPBI_SHARED_SURFACE), - NVSWITCH_DMA_DIR_BIDIRECTIONAL); - if (status != NVL_SUCCESS) - { - NVSWITCH_PRINT(device, ERROR, - "Failed to map dma region for SMBPBI shared surface, rc:%d\n", - status); - goto os_map_dma_region_fail; - } - device->pSmbpbi = nvswitch_os_malloc(sizeof(struct smbpbi)); if (!device->pSmbpbi) { status = -NVL_NO_MEM; goto smbpbi_init_fail; } + nvswitch_os_memset(device->pSmbpbi, 0, sizeof(struct smbpbi)); - device->pSmbpbi->sharedSurface = cpuAddr; - device->pSmbpbi->dmaHandle = dmaHandle; + status = device->hal.nvswitch_smbpbi_send_init_data(device); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "Failed to send SMBPBI init data, rc:%d\n", + status); + // Do not fail the init because of this. + } - return NVL_SUCCESS; + status = device->hal.nvswitch_smbpbi_alloc(device); smbpbi_init_fail: - nvswitch_os_unmap_dma_region(device->os_handle, cpuAddr, dmaHandle, - sizeof(SOE_SMBPBI_SHARED_SURFACE), NVSWITCH_DMA_DIR_BIDIRECTIONAL); -os_map_dma_region_fail: - nvswitch_os_free_contig_memory(device->os_handle, cpuAddr, sizeof(SOE_SMBPBI_SHARED_SURFACE)); + if (status != NVL_SUCCESS) + { + nvswitch_os_free(device->pSmbpbi); + } return status; } @@ -139,94 +79,24 @@ nvswitch_smbpbi_post_init nvswitch_device * device ) { - struct smbpbi *pSmbpbi = device->pSmbpbi; - FLCN *pFlcn; - NvU64 dmaHandle; - RM_FLCN_CMD_SOE cmd; - NVSWITCH_TIMEOUT timeout; - NvU32 cmdSeqDesc; - RM_SOE_SMBPBI_CMD_INIT *pInitCmd = &cmd.cmd.smbpbiCmd.init; - NvlStatus status; + NvlStatus status; - if (!device->pSmbpbi || !device->pInforom) + if (!device->pSmbpbi) { return -NVL_ERR_NOT_SUPPORTED; } - // Populate shared surface with static InfoROM data - nvswitch_inforom_read_static_data(device, device->pInforom, - &device->pSmbpbi->sharedSurface->inforomObjects); + status = device->hal.nvswitch_smbpbi_post_init_hal(device); - pFlcn = device->pSoe->pFlcn; - dmaHandle = pSmbpbi->dmaHandle; - - nvswitch_os_memset(&cmd, 0, sizeof(cmd)); - cmd.hdr.unitId = RM_SOE_UNIT_SMBPBI; - cmd.hdr.size = RM_SOE_CMD_SIZE(SMBPBI, INIT); - cmd.cmd.smbpbiCmd.cmdType = RM_SOE_SMBPBI_CMD_ID_INIT; - RM_FLCN_U64_PACK(&pInitCmd->dmaHandle, &dmaHandle); - - // - // Make the interval twice the heartbeat period to avoid - // skew between driver and soe threads - // - pInitCmd->driverPollingPeriodUs = (NVSWITCH_HEARTBEAT_INTERVAL_NS / 1000) * 2; - - nvswitch_timeout_create(NVSWITCH_INTERVAL_1SEC_IN_NS, &timeout); - status = flcnQueueCmdPostBlocking(device, pFlcn, - (PRM_FLCN_CMD)&cmd, - NULL, // pMsg - not used for now - NULL, // pPayload - not used for now - SOE_RM_CMDQ_LOG_ID, - &cmdSeqDesc, - &timeout); - if (status != NV_OK) + if (status == NVL_SUCCESS) { - NVSWITCH_PRINT(device, ERROR, "%s: SMBPBI Init command failed. rc:%d\n", - __FUNCTION__, status); - return status; + nvswitch_lib_smbpbi_log_sxid(device, NVSWITCH_ERR_NO_ERROR, + "NVSWITCH SMBPBI server is online."); + + NVSWITCH_PRINT(device, INFO, "%s: SMBPBI POST INIT completed\n", __FUNCTION__); } - nvswitch_lib_smbpbi_log_sxid(device, NVSWITCH_ERR_NO_ERROR, - "NVSWITCH SMBPBI server is online."); - - NVSWITCH_PRINT(device, INFO, "%s: SMBPBI POST INIT completed\n", __FUNCTION__); - - return NVL_SUCCESS; -} - -static void -_nvswitch_smbpbi_send_unload -( - nvswitch_device *device -) -{ - FLCN *pFlcn; - RM_FLCN_CMD_SOE cmd; - NVSWITCH_TIMEOUT timeout; - NvU32 cmdSeqDesc; - NvlStatus status; - - pFlcn = device->pSoe->pFlcn; - - nvswitch_os_memset(&cmd, 0, sizeof(cmd)); - cmd.hdr.unitId = RM_SOE_UNIT_SMBPBI; - cmd.hdr.size = RM_SOE_CMD_SIZE(SMBPBI, UNLOAD); - cmd.cmd.smbpbiCmd.cmdType = RM_SOE_SMBPBI_CMD_ID_UNLOAD; - - nvswitch_timeout_create(NVSWITCH_INTERVAL_1SEC_IN_NS, &timeout); - status = flcnQueueCmdPostBlocking(device, pFlcn, - (PRM_FLCN_CMD)&cmd, - NULL, // pMsg - not used for now - NULL, // pPayload - not used for now - SOE_RM_CMDQ_LOG_ID, - &cmdSeqDesc, - &timeout); - if (status != NV_OK) - { - NVSWITCH_PRINT(device, ERROR, "%s: SMBPBI unload command failed. rc:%d\n", - __FUNCTION__, status); - } + return status; } void @@ -237,8 +107,8 @@ nvswitch_smbpbi_unload { if (device->pSmbpbi) { - _nvswitch_smbpbi_send_unload(device); - _nvswitch_smbpbi_dem_flush(device); + device->hal.nvswitch_smbpbi_send_unload(device); + device->hal.nvswitch_smbpbi_dem_flush(device); } } @@ -250,13 +120,7 @@ nvswitch_smbpbi_destroy { if (device->pSmbpbi) { - nvswitch_os_unmap_dma_region(device->os_handle, - device->pSmbpbi->sharedSurface, - device->pSmbpbi->dmaHandle, - sizeof(SOE_SMBPBI_SHARED_SURFACE), - NVSWITCH_DMA_DIR_BIDIRECTIONAL); - nvswitch_os_free_contig_memory(device->os_handle, device->pSmbpbi->sharedSurface, - sizeof(SOE_SMBPBI_SHARED_SURFACE)); + device->hal.nvswitch_smbpbi_destroy_hal(device); nvswitch_os_free(device->pSmbpbi); device->pSmbpbi = NULL; } @@ -293,391 +157,6 @@ nvswitch_smbpbi_refresh_ecc_counts return NVL_SUCCESS; } -NvlStatus -nvswitch_inforom_dem_load -( - nvswitch_device *device -) -{ - NvlStatus status; - NvU8 version = 0; - NvU8 subversion = 0; - struct inforom *pInforom = device->pInforom; - NvU8 *pPackedObject = NULL; - struct INFOROM_DEM_OBJECT_V1_00 *pFifo; - - if ((pInforom == NULL) || (device->pSmbpbi == NULL) || - (device->pSmbpbi->sharedSurface == NULL)) - { - return -NVL_ERR_NOT_SUPPORTED; - } - - pFifo = GET_PFIFO_FROM_DEVICE(device); - - status = nvswitch_inforom_get_object_version_info(device, "DEM", &version, - &subversion); - if (status != NVL_SUCCESS) - { - NVSWITCH_PRINT(device, INFO, "no DEM object found, rc:%d\n", status); - goto nvswitch_inforom_dem_load_fail; - } - - if (!INFOROM_OBJECT_SUBVERSION_SUPPORTS_NVSWITCH(subversion)) - { - NVSWITCH_PRINT(device, WARN, "DEM v%u.%u not supported\n", - version, subversion); - status = -NVL_ERR_NOT_SUPPORTED; - goto nvswitch_inforom_dem_load_fail; - } - - NVSWITCH_PRINT(device, INFO, "DEM v%u.%u found\n", version, subversion); - - if (version != 1) - { - NVSWITCH_PRINT(device, WARN, "DEM v%u.%u not supported\n", - version, subversion); - status = -NVL_ERR_NOT_SUPPORTED; - goto nvswitch_inforom_dem_load_fail; - } - - pPackedObject = nvswitch_os_malloc(INFOROM_DEM_OBJECT_V1_00_PACKED_SIZE); - - if (pPackedObject == NULL) - { - status = -NVL_NO_MEM; - goto nvswitch_inforom_dem_load_fail; - } - - status = nvswitch_inforom_load_object(device, pInforom, "DEM", - INFOROM_DEM_OBJECT_V1_00_FMT, - pPackedObject, - pFifo); - if (status != NVL_SUCCESS) - { - NVSWITCH_PRINT(device, ERROR, "Failed to load DEM object, rc: %d\n", - status); - goto nvswitch_inforom_dem_load_fail; - } - -nvswitch_inforom_dem_load_fail: - - if (pPackedObject) - { - nvswitch_os_free(pPackedObject); - } - - // - // Mark the cached DEM as usable for Xid logging, even if we were - // unable to find it in the InfoROM image. - // - - device->pSmbpbi->sharedSurface->inforomObjects.DEM.bValid = NV_TRUE; - - _smbpbiDemInit(device, device->pSmbpbi, pFifo); - - return status; -} - -/*! - * Validate/Initialize the Driver Event Message (SXid) FIFO buffer - * - * @param[in] device device object pointer - * @param[in] pSmbpbi SMBPBI object pointer - * @param[in,out] pFifo DEM object pointer - * - * @return void - */ -static void -_smbpbiDemInit -( - nvswitch_device *device, - struct smbpbi *pSmbpbi, - struct INFOROM_DEM_OBJECT_V1_00 *pFifo -) -{ - NvU8 msgLeft; - unsigned recordsHeld = 0; - NvU16 FIFO_REC_LOOP_ITERATOR; - NvU16 bytesOccupied; - NvU16 bytesSeen; - NvBool status = NV_FALSE; - - // validate the FIFO buffer - - if ((DEM_FIFO_PTR(pFifo->writeOffset) != pFifo->writeOffset) || - (DEM_FIFO_PTR(pFifo->readOffset) != pFifo->readOffset) || - ((pFifo->writeOffset % sizeof(NvU32)) != 0) || - ((pFifo->readOffset % sizeof(NvU32)) != 0)) - { - goto smbpbiDemInit_exit; - } - - if (pFifo->writeOffset == pFifo->readOffset) - { - // The FIFO is empty - status = NV_TRUE; - goto smbpbiDemInit_exit; - } - - // - // This HAL extracts from a scratch register the count of DEM messages - // in the FIFO that has not yet been requested by the SMBPBI client. - // If the FIFO holds more messages than that, it means those in excess - // of this count have been delivered to the client by PreOS app. - // - if (device->hal.nvswitch_smbpbi_get_dem_num_messages(device, &msgLeft) != NVL_SUCCESS) - { - // assume the maximum - msgLeft = ~0; - } - - if (msgLeft == 0) - { - // Nothing of value in the FIFO. Lets reset it explicitly. - status = NV_TRUE; - pFifo->writeOffset = 0; - pFifo->readOffset = 0; - goto smbpbiDemInit_exit; - } - - // - // Count the messages in the FIFO, while also checking the structure - // for integrity. Reset the FIFO in case any corruption is found. - // - bytesOccupied = DEM_BYTES_OCCUPIED(pFifo); - - bytesSeen = 0; - FIFO_REC_LOOP_START(pFifo, bytesSeen < bytesOccupied) - if ((_recSize > DEM_RECORD_SIZE_MAX) || - (FIFO_REC_LOOP_REC_SIZE < DEM_RECORD_SIZE_MIN)) - { - goto smbpbiDemInit_exit; - } - - bytesSeen += FIFO_REC_LOOP_REC_SIZE; - ++recordsHeld; - FIFO_REC_LOOP_END - - if ((bytesSeen != bytesOccupied) || (msgLeft > recordsHeld)) - { - goto smbpbiDemInit_exit; - } - - // - // Advance the FIFO read ptr in order to remove those messages that - // have already been delivered to the client. - // - FIFO_REC_LOOP_START(pFifo, recordsHeld > msgLeft) - --recordsHeld; - FIFO_REC_LOOP_END - - pFifo->readOffset = FIFO_REC_LOOP_ITERATOR; - status = NV_TRUE; - -smbpbiDemInit_exit: - - if (!status) - { - // Reset the FIFO - pFifo->writeOffset = 0; - pFifo->readOffset = 0; - pFifo->seqNumber = 0; - } -} - -static void -_nvswitch_smbpbi_dem_flush(nvswitch_device *device) -{ - NvU8 *pPackedObject = NULL; - struct INFOROM_DEM_OBJECT_V1_00 *pFifo; - NvlStatus status = NVL_SUCCESS; - - pPackedObject = nvswitch_os_malloc(INFOROM_DEM_OBJECT_V1_00_PACKED_SIZE); - - if (pPackedObject == NULL) - { - status = -NVL_NO_MEM; - goto _nvswitch_smbpbi_dem_flush_exit; - } - - pFifo = GET_PFIFO_FROM_DEVICE(device); - - status = nvswitch_inforom_write_object(device, "DEM", - INFOROM_DEM_OBJECT_V1_00_FMT, - pFifo, - pPackedObject); - -_nvswitch_smbpbi_dem_flush_exit: - nvswitch_os_free(pPackedObject); - - if (status != NVL_SUCCESS) - { - NVSWITCH_PRINT(device, ERROR, "DEM object write failed, status=%d\n", - status); - } -} - -/*! - * A helper to create a new DEM FIFO record - * - * @param[in,out] pFifo DEM object pointer - * @param[in] num Xid number - * @param[in] osErrorString text message to store - * @param[in] msglen message size - * @param[out] pRecSize new record size in bytes - * - * @return ptr to the new record - * @return NULL if there's no room in the FIFO - * or dynamic allocation error - */ -static NV_MSGBOX_DEM_RECORD * -_makeNewRecord -( - INFOROM_DEM_OBJECT_V1_00 *pFifo, - NvU32 num, - NvU8 *osErrorString, - NvU32 msglen, - NvU32 *pRecSize -) -{ - NV_MSGBOX_DEM_RECORD *pNewRec; - - *pRecSize = NV_MIN(sizeof(NV_MSGBOX_DEM_RECORD) + msglen, - DEM_RECORD_SIZE_MAX); - - if ((*pRecSize > DEM_BYTES_AVAILABLE(pFifo)) || - ((pNewRec = nvswitch_os_malloc(*pRecSize)) == NULL)) - { - return NULL; - } - - // Fill the new record. - nvswitch_os_memset(pNewRec, 0, *pRecSize); - pNewRec->recordSize = NV_UNSIGNED_DIV_CEIL(*pRecSize, sizeof(NvU32)); - pNewRec->xidId = num; - pNewRec->seqNumber = pFifo->seqNumber++; - pNewRec->timeStamp = nvswitch_os_get_platform_time() / NVSWITCH_NSEC_PER_SEC; - - if (msglen > NV_MSGBOX_MAX_DRIVER_EVENT_MSG_TXT_SIZE) - { - // The text string is too long. Truncate and notify the client. - pNewRec->flags = FLD_SET_DRF(_MSGBOX, _DEM_RECORD_FLAGS, - _TRUNC, _SET, pNewRec->flags); - msglen = NV_MSGBOX_MAX_DRIVER_EVENT_MSG_TXT_SIZE - 1; - } - - nvswitch_os_memcpy(pNewRec->textMessage, osErrorString, msglen); - - return pNewRec; -} - -/*! - * A helper to add the new record to the DEM FIFO - * - * @param[in,out] pFifo DEM object pointer - * @param[in] pNewRec the new record - * @param[in] recSize new record size in bytes - * - * @return void - */ -static void -_addNewRecord -( - INFOROM_DEM_OBJECT_V1_00 *pFifo, - NV_MSGBOX_DEM_RECORD *pNewRec, - NvU32 recSize -) -{ - NvU16 rem; - NvU16 curPtr; - NvU16 copySz; - NvU8 *srcPtr; - - // Copy the new record into the FIFO, handling a possible wrap-around. - rem = recSize; - curPtr = pFifo->writeOffset; - srcPtr = (NvU8 *)pNewRec; - while (rem > 0) - { - copySz = NV_MIN(rem, DEM_FIFO_SIZE - curPtr); - nvswitch_os_memcpy(pFifo->fifoBuffer + curPtr, srcPtr, copySz); - rem -= copySz; - srcPtr += copySz; - curPtr = DEM_FIFO_PTR(curPtr + copySz); - } - - // Advance the FIFO write ptr. - pFifo->writeOffset = DEM_FIFO_PTR(pFifo->writeOffset + - (pNewRec->recordSize * sizeof(NvU32))); -} - -/*! - * Add a Driver Event Message (SXid) to the InfoROM DEM FIFO buffer - * - * @param[in] device device object pointer - * @param[in] num Xid number - * @param[in] msglen message size - * @param[in] osErrorString text message to store - * - * @return void - */ -void -nvswitch_smbpbi_log_message -( - nvswitch_device *device, - NvU32 num, - NvU32 msglen, - NvU8 *osErrorString -) -{ - INFOROM_DEM_OBJECT_V1_00 *pFifo; - NvU32 recSize; - NvU16 FIFO_REC_LOOP_ITERATOR; - NV_MSGBOX_DEM_RECORD *pNewRec; - - if ((device->pSmbpbi == NULL) || - (device->pSmbpbi->sharedSurface == NULL)) - { - return; - } - - pFifo = GET_PFIFO_FROM_DEVICE(device); - - pNewRec = _makeNewRecord(pFifo, num, osErrorString, msglen, &recSize); - - if (pNewRec != NULL) - { - _addNewRecord(pFifo, pNewRec, recSize); - nvswitch_os_free(pNewRec); - } - else - { - // - // We are unable to log this message. Mark the latest record - // with a flag telling the client that message(s) were dropped. - // - - NvU16 bytesOccupied = DEM_BYTES_OCCUPIED(pFifo); - NvU16 bytesSeen; - NV_MSGBOX_DEM_RECORD *pLastRec = NULL; - - // Find the newest record - bytesSeen = 0; - FIFO_REC_LOOP_START(pFifo, bytesSeen < bytesOccupied) - pLastRec = FIFO_REC_LOOP_REC_PTR; - bytesSeen += FIFO_REC_LOOP_REC_SIZE; - FIFO_REC_LOOP_END - - if (pLastRec != NULL) - { - pLastRec->flags = FLD_SET_DRF(_MSGBOX, _DEM_RECORD_FLAGS, - _OVFL, _SET, pLastRec->flags); - } - } - - return; -} - NvlStatus nvswitch_smbpbi_set_link_error_info ( diff --git a/src/common/nvswitch/kernel/soe/soe_call_hal_nvswitch.c b/src/common/nvswitch/kernel/soe/soe_call_hal_nvswitch.c index 516ce5c18..c0bdc531a 100644 --- a/src/common/nvswitch/kernel/soe/soe_call_hal_nvswitch.c +++ b/src/common/nvswitch/kernel/soe/soe_call_hal_nvswitch.c @@ -375,3 +375,20 @@ soeWaitForInitAck_HAL return pSoe->base.pHal->waitForInitAck(device, pSoe); } + +NvlStatus +soeI2CAccess_HAL +( + nvswitch_device *device, + NVSWITCH_CTRL_I2C_INDEXED_PARAMS *pParams +) +{ + PSOE pSoe = (PSOE)device->pSoe; + if (pSoe->base.pHal->i2cAccess == NULL) + { + NVSWITCH_ASSERT(0); + return 0; + } + + return pSoe->base.pHal->i2cAccess(device, pParams); +} diff --git a/src/common/nvswitch/kernel/soe/soe_nvswitch.c b/src/common/nvswitch/kernel/soe/soe_nvswitch.c index b83b76577..94dee820f 100644 --- a/src/common/nvswitch/kernel/soe/soe_nvswitch.c +++ b/src/common/nvswitch/kernel/soe/soe_nvswitch.c @@ -179,6 +179,10 @@ soeSetupHal { soeSetupHal_LR10(pSoe); } + else if (nvswitch_is_ls10_device_id(pci_device_id)) + { + soeSetupHal_LS10(pSoe); + } else { // we're on a device which doesn't support SOE diff --git a/src/common/nvswitch/kernel/spi_nvswitch.c b/src/common/nvswitch/kernel/spi_nvswitch.c index ac590c4aa..b50af8786 100644 --- a/src/common/nvswitch/kernel/spi_nvswitch.c +++ b/src/common/nvswitch/kernel/spi_nvswitch.c @@ -48,7 +48,7 @@ nvswitch_spi_init nvswitch_os_memset(&cmd, 0, sizeof(cmd)); cmd.hdr.unitId = RM_SOE_UNIT_SPI; - cmd.hdr.size = sizeof(cmd); + cmd.hdr.size = RM_FLCN_QUEUE_HDR_SIZE + sizeof(RM_SOE_SPI_CMD); cmd.cmd.spi.cmdType = RM_SOE_SPI_INIT; nvswitch_timeout_create(NVSWITCH_INTERVAL_1MSEC_IN_NS * 30, &timeout); diff --git a/src/common/sdk/nvidia/inc/Nvcm.h b/src/common/sdk/nvidia/inc/Nvcm.h index d0d942271..71dc8805e 100644 --- a/src/common/sdk/nvidia/inc/Nvcm.h +++ b/src/common/sdk/nvidia/inc/Nvcm.h @@ -45,14 +45,12 @@ extern "C" { #endif -#if !defined(XAPIGEN) /* avoid duplicate generated xapi fns */ #include "nvgputypes.h" #ifndef _H2INC #include "rmcd.h" #endif #include "nverror.h" -#endif /* !XAPIGEN */ #define NV_ROBUST_CHANNEL_ALLOCFAIL_CLIENT 0x00000001 #define NV_ROBUST_CHANNEL_ALLOCFAIL_DEVICE 0x00000002 diff --git a/src/common/sdk/nvidia/inc/alloc/alloc_channel.h b/src/common/sdk/nvidia/inc/alloc/alloc_channel.h new file mode 100644 index 000000000..4e9620466 --- /dev/null +++ b/src/common/sdk/nvidia/inc/alloc/alloc_channel.h @@ -0,0 +1,319 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: alloc/alloc_channel.finn +// + +#include "nvlimits.h" +#include "nvcfg_sdk.h" + +typedef struct NV_MEMORY_DESC_PARAMS { + NV_DECLARE_ALIGNED(NvU64 base, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NvU32 addressSpace; + NvU32 cacheAttrib; +} NV_MEMORY_DESC_PARAMS; + + +/* + * NV_CHANNEL_ALLOC_PARAMS.flags values. + * + * These flags may apply to all channel types: PIO, DMA, and GPFIFO. + * They are also designed so that zero is always the correct default. + * + * NVOS04_FLAGS_CHANNEL_TYPE: + * This flag specifies the type of channel to allocate. Legal values + * for this flag include: + * + * NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL: + * This flag specifies that a physical channel is to be allocated. + * + * NVOS04_FLAGS_CHANNEL_TYPE_VIRTUAL: + * OBSOLETE - NOT SUPPORTED + * + * NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL_FOR_VIRTUAL: + * OBSOLETE - NOT SUPPORTED + */ + +/* valid NVOS04_FLAGS_CHANNEL_TYPE values */ +#define NVOS04_FLAGS_CHANNEL_TYPE 1:0 +#define NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL 0x00000000 +#define NVOS04_FLAGS_CHANNEL_TYPE_VIRTUAL 0x00000001 // OBSOLETE +#define NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL_FOR_VIRTUAL 0x00000002 // OBSOLETE + +/* + * NVOS04_FLAGS_VPR: + * This flag specifies if channel is intended for work with + * Video Protected Regions (VPR) + * + * NVOS04_FLAGS_VPR_TRUE: + * The channel will only write to protected memory regions. + * + * NVOS04_FLAGS_VPR_FALSE: + * The channel will never read from protected memory regions. + */ +#define NVOS04_FLAGS_VPR 2:2 +#define NVOS04_FLAGS_VPR_FALSE 0x00000000 +#define NVOS04_FLAGS_VPR_TRUE 0x00000001 + + + +/* + * NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING: + * This flag specifies if the channel can skip refcounting of potentially + * accessed mappings on job kickoff. This flag is only meaningful for + * kernel drivers which perform refcounting of memory mappings. + * + * NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_FALSE: + * The channel cannot not skip refcounting of memory mappings + * + * NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_TRUE: + * The channel can skip refcounting of memory mappings + */ +#define NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING 3:3 +#define NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE: + * This flag specifies which "runqueue" the allocated channel will be + * executed on in a TSG. Channels on different runqueues within a TSG + * may be able to feed methods into the engine simultaneously. + * Non-default values are only supported on GP10x and later and only for + * channels within a TSG. + */ +#define NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE 4:4 +#define NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_DEFAULT 0x00000000 +#define NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_ONE 0x00000001 + +/* + * NVOS04_FLAGS_PRIVILEGED_CHANNEL: + * This flag tells RM whether to give the channel admin privilege. This + * flag will only take effect if the client is GSP-vGPU plugin. It is + * needed so that guest can update page tables in physical mode and do + * scrubbing. + */ +#define NVOS04_FLAGS_PRIVILEGED_CHANNEL 5:5 +#define NVOS04_FLAGS_PRIVILEGED_CHANNEL_FALSE 0x00000000 +#define NVOS04_FLAGS_PRIVILEGED_CHANNEL_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING: + * This flags tells RM not to schedule a newly created channel within a + * channel group immediately even if channel group is currently scheduled. + * Channel will not be scheduled until NVA06F_CTRL_GPFIFO_SCHEDULE is + * invoked. This is used eg. for CUDA which needs to do additional + * initialization before starting up a channel. + * Default is FALSE. + */ +#define NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING 6:6 +#define NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_FALSE 0x00000000 +#define NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_DENY_PHYSICAL_MODE_CE: + * This flag specifies whether or not to deny access to the physical + * mode of CopyEngine regardless of whether or not the client handle + * is admin. If set to true, this channel allocation will always result + * in an unprivileged channel. If set to false, the privilege of the channel + * will depend on the privilege level of the client handle. + * This is primarily meant for vGPU since all client handles + * granted to guests are admin. + */ +#define NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE 7:7 +#define NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_CHANNEL_USERD_INDEX_VALUE + * + * This flag specifies the channel offset in terms of within a page of + * USERD. For example, value 3 means the 4th channel within a USERD page. + * Given the USERD size is 512B, we will have 8 channels total, so 3 bits + * are reserved. + * + * When _USERD_INDEX_FIXED_TRUE is set but INDEX_PAGE_FIXED_FALSE is set, + * it will ask for a new USERD page. + * + */ +#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_VALUE 10:8 + +#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED 11:11 +#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_VALUE + * + * This flag specifies the channel offset in terms of USERD page. When + * this PAGE_FIXED_TRUE is set, the INDEX_FIXED_FALSE bit should also + * be set, otherwise INVALID_STATE will be returned. + * + * And the field _USERD_INDEX_VALUE will be used to request the specific + * offset within a USERD page. + */ + +#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_VALUE 20:12 + +#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED 21:21 +#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_DENY_AUTH_LEVEL_PRIV + * This flag specifies whether or not to deny access to the privileged + * host methods TLB_INVALIDATE and ACCESS_COUNTER_CLR + */ +#define NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV 22:22 +#define NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER + * + * This flag specifies scrubbing should be skipped for any internal + * allocations made for this channel from PMA using ctx buf pools. + * Only kernel clients are allowed to use this setting. + */ +#define NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER 23:23 +#define NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO + * + * This flag specifies that the client is expected to map USERD themselves + * and RM need not do so. + */ +#define NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO 24:24 +#define NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL + */ +#define NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL 25:25 +#define NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_FALSE 0x00000000 +#define NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT + * + * This flag specifies whether the channel calling context is from CPU + * VGPU plugin. + */ +#define NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT 26:26 +#define NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_TRUE 0x00000001 + + /* + * NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT + * + * This flag specifies the channel PBDMA ACQUIRE timeout option. + * _FALSE to disable it, _TRUE to enable it. + * When this flag is enabled, if a host semaphore acquire does not + * complete in about 2 sec, it will time out and trigger a RC error. + */ +#define NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT 27:27 +#define NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_FALSE 0x00000000 +#define NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_TRUE 0x00000001 + +/* + * NVOS04_FLAGS_GROUP_CHANNEL_THREAD: + * This flags specifies the thread id in which an allocated channel + * will be executed in a TSG. The relationship between the thread id + * in A TSG and respective definitions are implementation specific. + * Also, not all classes will be supported at thread > 0. + * This field cannot be used on non-TSG channels and must be set to + * the default value (0) in that case. If thread > 0 on a non-TSG + * channel, the allocation will fail + */ +#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD 29:28 +#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD_DEFAULT 0x00000000 +#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD_ONE 0x00000001 +#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD_TWO 0x00000002 + +#define NVOS04_FLAGS_MAP_CHANNEL 30:30 +#define NVOS04_FLAGS_MAP_CHANNEL_FALSE 0x00000000 +#define NVOS04_FLAGS_MAP_CHANNEL_TRUE 0x00000001 + +#define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC 31:31 +#define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_FALSE 0x00000000 +#define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_TRUE 0x00000001 + + + + +#define NV_CHANNEL_ALLOC_PARAMS_MESSAGE_ID (0x906fU) + +typedef struct NV_CHANNEL_ALLOC_PARAMS { + + NvHandle hObjectError; // error context DMA + NvHandle hObjectBuffer; // no longer used + NV_DECLARE_ALIGNED(NvU64 gpFifoOffset, 8); // offset to beginning of GP FIFO + NvU32 gpFifoEntries; // number of GP FIFO entries + + NvU32 flags; + + + NvHandle hContextShare; // context share handle + NvHandle hVASpace; // VASpace for the channel + + // handle to UserD memory object for channel, ignored if hUserdMemory[0]=0 + NvHandle hUserdMemory[NV_MAX_SUBDEVICES]; + + // offset to beginning of UserD within hUserdMemory[x] + NV_DECLARE_ALIGNED(NvU64 userdOffset[NV_MAX_SUBDEVICES], 8); + + // engine type(NV2080_ENGINE_TYPE_*) with which this channel is associated + NvU32 engineType; + // Channel identifier that is unique for the duration of a RM session + NvU32 cid; + // One-hot encoded bitmask to match SET_SUBDEVICE_MASK methods + NvU32 subDeviceId; + NvHandle hObjectEccError; // ECC error context DMA + + + + NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS instanceMem, 8); + NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS userdMem, 8); + NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS ramfcMem, 8); + NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS mthdbufMem, 8); + + NvHandle hPhysChannelGroup; // reserved + NvU32 internalFlags; // reserved + NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS errorNotifierMem, 8); // reserved + NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS eccErrorNotifierMem, 8); // reserved + NvU32 ProcessID; // reserved + NvU32 SubProcessID; // reserved +} NV_CHANNEL_ALLOC_PARAMS; + +typedef NV_CHANNEL_ALLOC_PARAMS NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS; + diff --git a/src/common/sdk/nvidia/inc/class/cl0000.h b/src/common/sdk/nvidia/inc/class/cl0000.h index 713eb7b84..e7fefba70 100644 --- a/src/common/sdk/nvidia/inc/class/cl0000.h +++ b/src/common/sdk/nvidia/inc/class/cl0000.h @@ -34,12 +34,12 @@ #include "cl0000_notification.h" /* object NV01_NULL_OBJECT */ -#define NV01_NULL_OBJECT (0x00000000) +#define NV01_NULL_OBJECT (0x0) /* finn: Evaluated from "NV0000_ALLOC_PARAMETERS_MESSAGE_ID" */ /* obsolete alises */ #define NV1_NULL_OBJECT NV01_NULL_OBJECT -#define NV01_ROOT (0x00000000) +#define NV01_ROOT (0x0U) /* finn: Evaluated from "NV0000_ALLOC_PARAMETERS_MESSAGE_ID" */ /* NvAlloc parameteters */ #define NV0000_ALLOC_PARAMETERS_MESSAGE_ID (0x0000U) diff --git a/src/common/sdk/nvidia/inc/class/cl0005.h b/src/common/sdk/nvidia/inc/class/cl0005.h index a963d15b6..2d04c34d7 100644 --- a/src/common/sdk/nvidia/inc/class/cl0005.h +++ b/src/common/sdk/nvidia/inc/class/cl0005.h @@ -32,7 +32,7 @@ #include "cl0005_notification.h" -#define NV01_EVENT (0x00000005) +#define NV01_EVENT (0x5U) /* finn: Evaluated from "NV0005_ALLOC_PARAMETERS_MESSAGE_ID" */ /* NvRmAlloc() parameters */ #define NV0005_ALLOC_PARAMETERS_MESSAGE_ID (0x0005U) diff --git a/src/common/sdk/nvidia/inc/class/cl000f.h b/src/common/sdk/nvidia/inc/class/cl000f.h index 961a619d2..7c0d96be3 100644 --- a/src/common/sdk/nvidia/inc/class/cl000f.h +++ b/src/common/sdk/nvidia/inc/class/cl000f.h @@ -30,7 +30,7 @@ // Source file: class/cl000f.finn // -#define FABRIC_MANAGER_SESSION (0x0000000F) +#define FABRIC_MANAGER_SESSION (0xfU) /* finn: Evaluated from "NV000F_ALLOCATION_PARAMETERS_MESSAGE_ID" */ #define NV000F_NOTIFIERS_FABRIC_EVENT (0) diff --git a/src/common/sdk/nvidia/inc/class/cl0060.h b/src/common/sdk/nvidia/inc/class/cl0060.h index bc1eb8e5b..80e377810 100644 --- a/src/common/sdk/nvidia/inc/class/cl0060.h +++ b/src/common/sdk/nvidia/inc/class/cl0060.h @@ -30,10 +30,8 @@ // Source file: class/cl0060.finn // -#define NV0060_SYNC_GPU_BOOST (0x00000060) +#define NV0060_SYNC_GPU_BOOST (0x60U) /* finn: Evaluated from "NV0060_ALLOC_PARAMETERS_MESSAGE_ID" */ -/*! - */ #define NV0060_ALLOC_PARAMETERS_MESSAGE_ID (0x0060U) typedef struct NV0060_ALLOC_PARAMETERS { diff --git a/src/common/sdk/nvidia/inc/class/cl0070.h b/src/common/sdk/nvidia/inc/class/cl0070.h index fd7fd70ac..c2a8f4ba7 100644 --- a/src/common/sdk/nvidia/inc/class/cl0070.h +++ b/src/common/sdk/nvidia/inc/class/cl0070.h @@ -29,8 +29,8 @@ // Source file: class/cl0070.finn // -#define NV01_MEMORY_VIRTUAL (0x00000070) -#define NV01_MEMORY_SYSTEM_DYNAMIC (0x00000070) +#define NV01_MEMORY_VIRTUAL (0x70U) /* finn: Evaluated from "NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_MESSAGE_ID" */ +#define NV01_MEMORY_SYSTEM_DYNAMIC (0x70U) /* finn: Evaluated from "NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_MESSAGE_ID" */ /* * NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS diff --git a/src/common/sdk/nvidia/inc/class/cl0080.h b/src/common/sdk/nvidia/inc/class/cl0080.h index e1f6a94c3..7f4bd59e6 100644 --- a/src/common/sdk/nvidia/inc/class/cl0080.h +++ b/src/common/sdk/nvidia/inc/class/cl0080.h @@ -33,7 +33,7 @@ #include "nvlimits.h" #include "cl0080_notification.h" -#define NV01_DEVICE_0 (0x00000080) +#define NV01_DEVICE_0 (0x80U) /* finn: Evaluated from "NV0080_ALLOC_PARAMETERS_MESSAGE_ID" */ /* NvAlloc parameteters */ #define NV0080_MAX_DEVICES NV_MAX_DEVICES diff --git a/src/common/sdk/nvidia/inc/class/cl0092.h b/src/common/sdk/nvidia/inc/class/cl0092.h index 8a9007070..327e0e47c 100644 --- a/src/common/sdk/nvidia/inc/class/cl0092.h +++ b/src/common/sdk/nvidia/inc/class/cl0092.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -20,10 +20,16 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef SDK_CL0092_H -#define SDK_CL0092_H +#pragma once -#include "nvtypes.h" +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl0092.finn +// + +#include "class/cl0092_callback.h" /* * This RgLineCallback class allows RM clients to register/unregister the RG line callback functions. @@ -50,19 +56,17 @@ * Pointer to the ctrl call param struct. */ -#define NV0092_RG_LINE_CALLBACK 0x0092 +#define NV0092_RG_LINE_CALLBACK (0x92U) /* finn: Evaluated from "NV0092_RG_LINE_CALLBACK_ALLOCATION_PARAMETERS_MESSAGE_ID" */ -typedef void (*NV0092_REGISTER_RG_LINE_CALLBACK_FN)(NvU32 rgIntrLine, void *param1, NvBool bIsIrqlIsr); +#define NV0092_RG_LINE_CALLBACK_ALLOCATION_PARAMETERS_MESSAGE_ID (0x0092U) -typedef struct -{ - NvU32 subDeviceInstance; - NvU32 head; - NvU32 rgLineNum; +typedef struct NV0092_RG_LINE_CALLBACK_ALLOCATION_PARAMETERS { + NvU32 subDeviceInstance; + NvU32 head; + NvU32 rgLineNum; - NV0092_REGISTER_RG_LINE_CALLBACK_FN pCallbkFn; + NV_DECLARE_ALIGNED(NvP64 pCallbkFn, 8); /* A function pointer of NV0092_REGISTER_RG_LINE_CALLBACK_FN */ - void *pCallbkParams; + NV_DECLARE_ALIGNED(NvP64 pCallbkParams, 8); /* The param1 in NV0092_REGISTER_RG_LINE_CALLBACK_FN */ } NV0092_RG_LINE_CALLBACK_ALLOCATION_PARAMETERS; -#endif // SDK_CL0092_H diff --git a/src/common/sdk/nvidia/inc/class/cl0092_callback.h b/src/common/sdk/nvidia/inc/class/cl0092_callback.h new file mode 100644 index 000000000..4cd86ad4a --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/cl0092_callback.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef SDK_CL0092_CALLBACK_H +#define SDK_CL0092_CALLBACK_H + +typedef void (*NV0092_REGISTER_RG_LINE_CALLBACK_FN)(NvU32 rgIntrLine, NvP64 param1, NvBool bIsIrqlIsr); + +#endif // SDK_CL0092_CALLBACK_H diff --git a/src/common/sdk/nvidia/inc/class/cl00c1.h b/src/common/sdk/nvidia/inc/class/cl00c1.h index 3e57495ba..73fea0564 100644 --- a/src/common/sdk/nvidia/inc/class/cl00c1.h +++ b/src/common/sdk/nvidia/inc/class/cl00c1.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -20,50 +20,46 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _cl00c1_h_ -#define _cl00c1_h_ +#pragma once -#ifdef __cplusplus -extern "C" { -#endif +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00c1.finn +// -#include "nvtypes.h" #include "nvlimits.h" - -#define NV_FB_SEGMENT (0x000000C1) +#define NV_FB_SEGMENT (0xc1U) /* finn: Evaluated from "NV_FB_SEGMENT_ALLOCATION_PARAMS_MESSAGE_ID" */ /* * NV_FB_SEGMENT_ALLOCATION_PARAMS - Allocation params to create FB segment through * NvRmAlloc. */ -typedef struct -{ - NvHandle hCtxDma; - NvU32 subDeviceIDMask NV_ALIGN_BYTES(8); - NvU64 dmaOffset NV_ALIGN_BYTES(8); - NvU64 VidOffset NV_ALIGN_BYTES(8); - NvU64 Offset NV_ALIGN_BYTES(8); // To be deprecated - NvU64 pOffset[NV_MAX_SUBDEVICES] NV_ALIGN_BYTES(8); - NvU64 Length NV_ALIGN_BYTES(8); - NvU64 ValidLength NV_ALIGN_BYTES(8); - NvP64 pPageArray NV_ALIGN_BYTES(8); - NvU32 startPageIndex; - NvHandle AllocHintHandle; - NvU32 Flags; - NvHandle hMemory; // Not used in NvRmAlloc path; only used in CTRL path - NvHandle hClient; // Not used in NvRmAlloc path; only used in CTRL path - NvHandle hDevice; // Not used in NvRmAlloc path; only used in CTRL path - NvP64 pCpuAddress NV_ALIGN_BYTES(8); // To be deprecated - NvP64 ppCpuAddress[NV_MAX_SUBDEVICES] NV_ALIGN_BYTES(8); - NvU64 GpuAddress NV_ALIGN_BYTES(8); // To be deprecated - NvU64 pGpuAddress[NV_MAX_SUBDEVICES] NV_ALIGN_BYTES(8); - NvHandle hAllocHintClient; - NvU32 kind; - NvU32 compTag; +#define NV_FB_SEGMENT_ALLOCATION_PARAMS_MESSAGE_ID (0x00C1U) + +typedef struct NV_FB_SEGMENT_ALLOCATION_PARAMS { + NvHandle hCtxDma; // unused + NvU32 subDeviceIDMask; + NV_DECLARE_ALIGNED(NvU64 dmaOffset, 8); // unused + NV_DECLARE_ALIGNED(NvU64 VidOffset, 8); + NV_DECLARE_ALIGNED(NvU64 Offset, 8); // To be deprecated + NV_DECLARE_ALIGNED(NvU64 pOffset[NV_MAX_SUBDEVICES], 8); + NV_DECLARE_ALIGNED(NvU64 Length, 8); + NV_DECLARE_ALIGNED(NvU64 ValidLength, 8); + NV_DECLARE_ALIGNED(NvP64 pPageArray, 8); + NvU32 startPageIndex; + NvHandle AllocHintHandle; + NvU32 Flags; + NvHandle hMemory; // Not used in NvRmAlloc path; only used in CTRL path + NvHandle hClient; // Not used in NvRmAlloc path; only used in CTRL path + NvHandle hDevice; // Not used in NvRmAlloc path; only used in CTRL path + NV_DECLARE_ALIGNED(NvP64 pCpuAddress, 8); // To be deprecated + NV_DECLARE_ALIGNED(NvP64 ppCpuAddress[NV_MAX_SUBDEVICES], 8); + NV_DECLARE_ALIGNED(NvU64 GpuAddress, 8); // To be deprecated + NV_DECLARE_ALIGNED(NvU64 pGpuAddress[NV_MAX_SUBDEVICES], 8); + NvHandle hAllocHintClient; + NvU32 kind; + NvU32 compTag; } NV_FB_SEGMENT_ALLOCATION_PARAMS; -#ifdef __cplusplus -}; /* extern "C" */ -#endif - -#endif /* _cl00c1_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/cl00c2.h b/src/common/sdk/nvidia/inc/class/cl00c2.h index 195971377..ef2d16823 100644 --- a/src/common/sdk/nvidia/inc/class/cl00c2.h +++ b/src/common/sdk/nvidia/inc/class/cl00c2.h @@ -29,7 +29,7 @@ // Source file: class/cl00c2.finn // -#define NV01_MEMORY_LOCAL_PHYSICAL (0x000000c2) +#define NV01_MEMORY_LOCAL_PHYSICAL (0xc2U) /* finn: Evaluated from "NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS_MESSAGE_ID" */ #define NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS_MESSAGE_ID (0x00c2U) diff --git a/src/common/sdk/nvidia/inc/class/cl00c3.h b/src/common/sdk/nvidia/inc/class/cl00c3.h index b9b31bc1f..298e582b8 100644 --- a/src/common/sdk/nvidia/inc/class/cl00c3.h +++ b/src/common/sdk/nvidia/inc/class/cl00c3.h @@ -29,7 +29,7 @@ // Source file: class/cl00c3.finn // -#define NV01_MEMORY_SYNCPOINT 0x00C3 +#define NV01_MEMORY_SYNCPOINT (0xc3U) /* finn: Evaluated from "NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS_MESSAGE_ID" */ /* * NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS - Allocation params to create syncpoint diff --git a/src/common/sdk/nvidia/inc/class/cl00db.h b/src/common/sdk/nvidia/inc/class/cl00db.h index a076cd9af..91791bdfb 100644 --- a/src/common/sdk/nvidia/inc/class/cl00db.h +++ b/src/common/sdk/nvidia/inc/class/cl00db.h @@ -31,7 +31,7 @@ // Source file: class/cl00db.finn // -#define NV40_DEBUG_BUFFER (0x000000db) +#define NV40_DEBUG_BUFFER (0xdbU) /* finn: Evaluated from "NV00DB_ALLOCATION_PARAMETERS_MESSAGE_ID" */ /* NvRmAlloc() parameters */ #define NV00DB_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00dbU) diff --git a/kernel-open/nvidia/nv-procfs-utils.c b/src/common/sdk/nvidia/inc/class/cl00de.h similarity index 66% rename from kernel-open/nvidia/nv-procfs-utils.c rename to src/common/sdk/nvidia/inc/class/cl00de.h index b9d8524ad..8c772ef51 100644 --- a/kernel-open/nvidia/nv-procfs-utils.c +++ b/src/common/sdk/nvidia/inc/class/cl00de.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,27 +21,30 @@ * DEALINGS IN THE SOFTWARE. */ -#if defined(CONFIG_PROC_FS) +#ifndef _cl00de_h_ +#define _cl00de_h_ -#include "nv-procfs-utils.h" - -void -nv_procfs_unregister_all(struct proc_dir_entry *entry, struct proc_dir_entry *delimiter) -{ -#if defined(NV_PROC_REMOVE_PRESENT) - proc_remove(entry); -#else - while (entry) - { - struct proc_dir_entry *next = entry->next; - if (entry->subdir) - nv_procfs_unregister_all(entry->subdir, delimiter); - remove_proc_entry(entry->name, entry->parent); - if (entry == delimiter) - break; - entry = next; - } -#endif -} +#ifdef __cplusplus +extern "C" { #endif +#define RM_USER_SHARED_DATA (0x000000de) + +typedef struct NV00DE_SHARED_DATA { + volatile NvU32 seq; + + NvU32 bar1Size; + NvU32 bar1AvailSize; + // New data members always add to bottom +} NV00DE_SHARED_DATA; + +typedef struct NV00DE_ALLOC_PARAMETERS { + // initialize to 0 + NvU32 reserved; +} NV00DE_ALLOC_PARAMETERS; + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl00de_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/cl00f3.h b/src/common/sdk/nvidia/inc/class/cl00f3.h index 1cb95c2f4..09647c32d 100644 --- a/src/common/sdk/nvidia/inc/class/cl00f3.h +++ b/src/common/sdk/nvidia/inc/class/cl00f3.h @@ -40,7 +40,7 @@ * other parameters are passed as Nv01MemoryFla structure. */ -#define NV01_MEMORY_FLA (0x000000f3) +#define NV01_MEMORY_FLA (0xf3U) /* finn: Evaluated from "NV_FLA_MEMORY_ALLOCATION_PARAMS_MESSAGE_ID" */ /* * Structure of NV_FLA_MEMORY_ALLOCATION_PARAMS diff --git a/src/common/sdk/nvidia/inc/class/cl00f8.h b/src/common/sdk/nvidia/inc/class/cl00f8.h index a3a6c4ce9..096c46c5b 100644 --- a/src/common/sdk/nvidia/inc/class/cl00f8.h +++ b/src/common/sdk/nvidia/inc/class/cl00f8.h @@ -36,7 +36,7 @@ * Class definition for allocating a contiguous or discontiguous FLA. */ -#define NV_MEMORY_FABRIC (0x000000f8) +#define NV_MEMORY_FABRIC (0xf8U) /* finn: Evaluated from "NV00F8_ALLOCATION_PARAMETERS_MESSAGE_ID" */ /* * alignment [IN] @@ -77,11 +77,13 @@ * Must be physical memory page size aligned. * * map.hVidMem [IN] - * Handle to the physical video memory. Must be passed when the sticky flag is set so that the - * FLA -> PA mapping can happen during object creation. - * Phys memory with 2MB pages is supported. - * Phys memory handle can be NV01_NULL_OBJECT if FLEXIBLE_FLA flag is passed. - * hVidMem should belong the same device and client which is allocating FLA. + * - Handle to the physical memory. + * - Must be passed so that the FLA -> GPA mapping can happen during object creation. + * - For sticky allocations, physical memory being mapped should be large enough + * (accounting map.offset) to cover the whole fabric object allocation size. + * - For flexible allocations, physical memory handle should be zero. + * - Phys memory with 2MB and 512MB pages is supported. + * - hVidMem should belong the same device and client which is allocating FLA. * * map.flags [IN] * Reserved for future use. diff --git a/src/common/sdk/nvidia/inc/class/cl00fd.h b/src/common/sdk/nvidia/inc/class/cl00fd.h new file mode 100644 index 000000000..5e80d463e --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/cl00fd.h @@ -0,0 +1,73 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * Class definition for allocating a contiguous or discontiguous Multicast FLA. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00fd.finn +// + +#define NV_MEMORY_MULTICAST_FABRIC (0xfdU) /* finn: Evaluated from "NV00FD_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +/* + * alignment [IN] + * Alignment for the allocation. + * Should be at least the requested page size. + * + * allocSize [IN] + * Size of the Multicast FLA VA. + * + * pageSize [IN] + * Requested page size. Can be any of the NV_MEMORY_MULTICAST_FABRIC_PAGE_SIZE_* + * + * allocFlags [IN] + * Reserved for future use + * Clients should pass 0 as of now. + * + * numGpus [IN] + * Number of unique GPUs to be attached. + * + * pOsEvent [IN] + * Optional OS event handle created with NvRmAllocOsEvent(). + */ + +#define NV_MEMORY_MULTICAST_FABRIC_PAGE_SIZE_512M 0x20000000 + +#define NV00FD_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00fdU) + +typedef struct NV00FD_ALLOCATION_PARAMETERS { + NV_DECLARE_ALIGNED(NvU64 alignment, 8); + NV_DECLARE_ALIGNED(NvU64 allocSize, 8); + NvU32 pageSize; + NvU32 allocFlags; + NvU32 numGpus; + NV_DECLARE_ALIGNED(NvP64 pOsEvent, 8); +} NV00FD_ALLOCATION_PARAMETERS; + diff --git a/src/common/sdk/nvidia/inc/class/cl00fe.h b/src/common/sdk/nvidia/inc/class/cl00fe.h new file mode 100644 index 000000000..464c1ec9a --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/cl00fe.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00fe.finn +// + +#define NV_MEMORY_MAPPER (0xfeU) /* finn: Evaluated from "NV_MEMORY_MAPPER_ALLOCATION_PARAMS_MESSAGE_ID" */ + +/* + * NV_MEMORY_MAPPER_ALLOCATION_PARAMS + * + * Allocation params for NV_MEMORY_MAPPER. + * This class provides paging operations channel interface to userspace clients. + */ +#define NV_MEMORY_MAPPER_ALLOCATION_PARAMS_MESSAGE_ID (0x00FEU) + +typedef struct NV_MEMORY_MAPPER_ALLOCATION_PARAMS { + NvBool unused; +} NV_MEMORY_MAPPER_ALLOCATION_PARAMS; + diff --git a/src/common/sdk/nvidia/inc/class/cl2080.h b/src/common/sdk/nvidia/inc/class/cl2080.h index 68eaabfc0..32b616f59 100644 --- a/src/common/sdk/nvidia/inc/class/cl2080.h +++ b/src/common/sdk/nvidia/inc/class/cl2080.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2002-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2002-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,472 +21,26 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _cl2080_h_ -#define _cl2080_h_ +#pragma once -#ifdef __cplusplus -extern "C" { -#endif +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl2080.finn +// -#include "nvtypes.h" #include "nvlimits.h" +#include "cl2080_notification.h" -#define NV20_SUBDEVICE_0 (0x00002080) - -/* event values */ -#define NV2080_NOTIFIERS_SW (0) -#define NV2080_NOTIFIERS_HOTPLUG (1) -#define NV2080_NOTIFIERS_POWER_CONNECTOR (2) -#define NV2080_NOTIFIERS_THERMAL_SW (3) -#define NV2080_NOTIFIERS_THERMAL_HW (4) -#define NV2080_NOTIFIERS_FULL_SCREEN_CHANGE (5) -#define NV2080_NOTIFIERS_EVENTBUFFER (6) -#define NV2080_NOTIFIERS_DP_IRQ (7) -#define NV2080_NOTIFIERS_GR_DEBUG_INTR (8) -#define NV2080_NOTIFIERS_PMU_EVENT (9) -#define NV2080_NOTIFIERS_PMU_COMMAND (10) -#define NV2080_NOTIFIERS_TIMER (11) -#define NV2080_NOTIFIERS_GRAPHICS (12) -#define NV2080_NOTIFIERS_PPP (13) -#define NV2080_NOTIFIERS_VLD (14) // also known as BSP -#define NV2080_NOTIFIERS_NVDEC0 NV2080_NOTIFIERS_VLD -#define NV2080_NOTIFIERS_NVDEC1 (15) -#define NV2080_NOTIFIERS_NVDEC2 (16) -#define NV2080_NOTIFIERS_NVDEC3 (17) -#define NV2080_NOTIFIERS_NVDEC4 (18) -#define NV2080_NOTIFIERS_NVDEC5 (19) -#define NV2080_NOTIFIERS_NVDEC6 (20) -#define NV2080_NOTIFIERS_NVDEC7 (21) -#define NV2080_NOTIFIERS_PDEC (22) // also known as VP -#define NV2080_NOTIFIERS_CE0 (23) -#define NV2080_NOTIFIERS_CE1 (24) -#define NV2080_NOTIFIERS_CE2 (25) -#define NV2080_NOTIFIERS_CE3 (26) -#define NV2080_NOTIFIERS_CE4 (27) -#define NV2080_NOTIFIERS_CE5 (28) -#define NV2080_NOTIFIERS_CE6 (29) -#define NV2080_NOTIFIERS_CE7 (30) -#define NV2080_NOTIFIERS_CE8 (31) -#define NV2080_NOTIFIERS_CE9 (32) -#define NV2080_NOTIFIERS_PSTATE_CHANGE (33) -#define NV2080_NOTIFIERS_HDCP_STATUS_CHANGE (34) -#define NV2080_NOTIFIERS_FIFO_EVENT_MTHD (35) -#define NV2080_NOTIFIERS_PRIV_RING_HANG (36) -#define NV2080_NOTIFIERS_RC_ERROR (37) -#define NV2080_NOTIFIERS_MSENC (38) -#define NV2080_NOTIFIERS_NVENC0 NV2080_NOTIFIERS_MSENC -#define NV2080_NOTIFIERS_NVENC1 (39) -#define NV2080_NOTIFIERS_NVENC2 (40) -#define NV2080_NOTIFIERS_UNUSED_0 (41) // Unused -#define NV2080_NOTIFIERS_ACPI_NOTIFY (42) -#define NV2080_NOTIFIERS_COOLER_DIAG_ZONE (43) -#define NV2080_NOTIFIERS_THERMAL_DIAG_ZONE (44) -#define NV2080_NOTIFIERS_AUDIO_HDCP_REQUEST (45) -#define NV2080_NOTIFIERS_WORKLOAD_MODULATION_CHANGE (46) -#define NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT (47) -#define NV2080_NOTIFIERS_GPIO_1_RISING_INTERRUPT (48) -#define NV2080_NOTIFIERS_GPIO_2_RISING_INTERRUPT (49) -#define NV2080_NOTIFIERS_GPIO_3_RISING_INTERRUPT (50) -#define NV2080_NOTIFIERS_GPIO_4_RISING_INTERRUPT (51) -#define NV2080_NOTIFIERS_GPIO_5_RISING_INTERRUPT (52) -#define NV2080_NOTIFIERS_GPIO_6_RISING_INTERRUPT (53) -#define NV2080_NOTIFIERS_GPIO_7_RISING_INTERRUPT (54) -#define NV2080_NOTIFIERS_GPIO_8_RISING_INTERRUPT (55) -#define NV2080_NOTIFIERS_GPIO_9_RISING_INTERRUPT (56) -#define NV2080_NOTIFIERS_GPIO_10_RISING_INTERRUPT (57) -#define NV2080_NOTIFIERS_GPIO_11_RISING_INTERRUPT (58) -#define NV2080_NOTIFIERS_GPIO_12_RISING_INTERRUPT (59) -#define NV2080_NOTIFIERS_GPIO_13_RISING_INTERRUPT (60) -#define NV2080_NOTIFIERS_GPIO_14_RISING_INTERRUPT (61) -#define NV2080_NOTIFIERS_GPIO_15_RISING_INTERRUPT (62) -#define NV2080_NOTIFIERS_GPIO_16_RISING_INTERRUPT (63) -#define NV2080_NOTIFIERS_GPIO_17_RISING_INTERRUPT (64) -#define NV2080_NOTIFIERS_GPIO_18_RISING_INTERRUPT (65) -#define NV2080_NOTIFIERS_GPIO_19_RISING_INTERRUPT (66) -#define NV2080_NOTIFIERS_GPIO_20_RISING_INTERRUPT (67) -#define NV2080_NOTIFIERS_GPIO_21_RISING_INTERRUPT (68) -#define NV2080_NOTIFIERS_GPIO_22_RISING_INTERRUPT (69) -#define NV2080_NOTIFIERS_GPIO_23_RISING_INTERRUPT (70) -#define NV2080_NOTIFIERS_GPIO_24_RISING_INTERRUPT (71) -#define NV2080_NOTIFIERS_GPIO_25_RISING_INTERRUPT (72) -#define NV2080_NOTIFIERS_GPIO_26_RISING_INTERRUPT (73) -#define NV2080_NOTIFIERS_GPIO_27_RISING_INTERRUPT (74) -#define NV2080_NOTIFIERS_GPIO_28_RISING_INTERRUPT (75) -#define NV2080_NOTIFIERS_GPIO_29_RISING_INTERRUPT (76) -#define NV2080_NOTIFIERS_GPIO_30_RISING_INTERRUPT (77) -#define NV2080_NOTIFIERS_GPIO_31_RISING_INTERRUPT (78) -#define NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT (79) -#define NV2080_NOTIFIERS_GPIO_1_FALLING_INTERRUPT (80) -#define NV2080_NOTIFIERS_GPIO_2_FALLING_INTERRUPT (81) -#define NV2080_NOTIFIERS_GPIO_3_FALLING_INTERRUPT (82) -#define NV2080_NOTIFIERS_GPIO_4_FALLING_INTERRUPT (83) -#define NV2080_NOTIFIERS_GPIO_5_FALLING_INTERRUPT (84) -#define NV2080_NOTIFIERS_GPIO_6_FALLING_INTERRUPT (85) -#define NV2080_NOTIFIERS_GPIO_7_FALLING_INTERRUPT (86) -#define NV2080_NOTIFIERS_GPIO_8_FALLING_INTERRUPT (87) -#define NV2080_NOTIFIERS_GPIO_9_FALLING_INTERRUPT (88) -#define NV2080_NOTIFIERS_GPIO_10_FALLING_INTERRUPT (89) -#define NV2080_NOTIFIERS_GPIO_11_FALLING_INTERRUPT (90) -#define NV2080_NOTIFIERS_GPIO_12_FALLING_INTERRUPT (91) -#define NV2080_NOTIFIERS_GPIO_13_FALLING_INTERRUPT (92) -#define NV2080_NOTIFIERS_GPIO_14_FALLING_INTERRUPT (93) -#define NV2080_NOTIFIERS_GPIO_15_FALLING_INTERRUPT (94) -#define NV2080_NOTIFIERS_GPIO_16_FALLING_INTERRUPT (95) -#define NV2080_NOTIFIERS_GPIO_17_FALLING_INTERRUPT (96) -#define NV2080_NOTIFIERS_GPIO_18_FALLING_INTERRUPT (97) -#define NV2080_NOTIFIERS_GPIO_19_FALLING_INTERRUPT (98) -#define NV2080_NOTIFIERS_GPIO_20_FALLING_INTERRUPT (99) -#define NV2080_NOTIFIERS_GPIO_21_FALLING_INTERRUPT (100) -#define NV2080_NOTIFIERS_GPIO_22_FALLING_INTERRUPT (101) -#define NV2080_NOTIFIERS_GPIO_23_FALLING_INTERRUPT (102) -#define NV2080_NOTIFIERS_GPIO_24_FALLING_INTERRUPT (103) -#define NV2080_NOTIFIERS_GPIO_25_FALLING_INTERRUPT (104) -#define NV2080_NOTIFIERS_GPIO_26_FALLING_INTERRUPT (105) -#define NV2080_NOTIFIERS_GPIO_27_FALLING_INTERRUPT (106) -#define NV2080_NOTIFIERS_GPIO_28_FALLING_INTERRUPT (107) -#define NV2080_NOTIFIERS_GPIO_29_FALLING_INTERRUPT (108) -#define NV2080_NOTIFIERS_GPIO_30_FALLING_INTERRUPT (109) -#define NV2080_NOTIFIERS_GPIO_31_FALLING_INTERRUPT (110) -#define NV2080_NOTIFIERS_ECC_SBE (111) -#define NV2080_NOTIFIERS_ECC_DBE (112) -#define NV2080_NOTIFIERS_STEREO_EMITTER_DETECTION (113) -#define NV2080_NOTIFIERS_GC5_GPU_READY (114) -#define NV2080_NOTIFIERS_SEC2 (115) -#define NV2080_NOTIFIERS_GC6_REFCOUNT_INC (116) -#define NV2080_NOTIFIERS_GC6_REFCOUNT_DEC (117) -#define NV2080_NOTIFIERS_POWER_EVENT (118) -#define NV2080_NOTIFIERS_CLOCKS_CHANGE (119) -#define NV2080_NOTIFIERS_HOTPLUG_PROCESSING_COMPLETE (120) -#define NV2080_NOTIFIERS_PHYSICAL_PAGE_FAULT (121) -#define NV2080_NOTIFIERS_RESERVED122 (122) -#define NV2080_NOTIFIERS_NVLINK_ERROR_FATAL (123) -#define NV2080_NOTIFIERS_PRIV_REG_ACCESS_FAULT (124) -#define NV2080_NOTIFIERS_NVLINK_ERROR_RECOVERY_REQUIRED (125) -#define NV2080_NOTIFIERS_NVJPG (126) -#define NV2080_NOTIFIERS_NVJPEG0 NV2080_NOTIFIERS_NVJPG -#define NV2080_NOTIFIERS_NVJPEG1 (127) -#define NV2080_NOTIFIERS_NVJPEG2 (128) -#define NV2080_NOTIFIERS_NVJPEG3 (129) -#define NV2080_NOTIFIERS_NVJPEG4 (130) -#define NV2080_NOTIFIERS_NVJPEG5 (131) -#define NV2080_NOTIFIERS_NVJPEG6 (132) -#define NV2080_NOTIFIERS_NVJPEG7 (133) -#define NV2080_NOTIFIERS_RUNLIST_AND_ENG_IDLE (134) -#define NV2080_NOTIFIERS_RUNLIST_ACQUIRE (135) -#define NV2080_NOTIFIERS_RUNLIST_ACQUIRE_AND_ENG_IDLE (136) -#define NV2080_NOTIFIERS_RUNLIST_IDLE (137) -#define NV2080_NOTIFIERS_TSG_PREEMPT_COMPLETE (138) -#define NV2080_NOTIFIERS_RUNLIST_PREEMPT_COMPLETE (139) -#define NV2080_NOTIFIERS_CTXSW_TIMEOUT (140) -#define NV2080_NOTIFIERS_INFOROM_ECC_OBJECT_UPDATED (141) -#define NV2080_NOTIFIERS_NVTELEMETRY_REPORT_EVENT (142) -#define NV2080_NOTIFIERS_DSTATE_XUSB_PPC (143) -#define NV2080_NOTIFIERS_FECS_CTX_SWITCH (144) -#define NV2080_NOTIFIERS_XUSB_PPC_CONNECTED (145) -#define NV2080_NOTIFIERS_GR0 NV2080_NOTIFIERS_GRAPHICS -#define NV2080_NOTIFIERS_GR1 (146) -#define NV2080_NOTIFIERS_GR2 (147) -#define NV2080_NOTIFIERS_GR3 (148) -#define NV2080_NOTIFIERS_GR4 (149) -#define NV2080_NOTIFIERS_GR5 (150) -#define NV2080_NOTIFIERS_GR6 (151) -#define NV2080_NOTIFIERS_GR7 (152) -#define NV2080_NOTIFIERS_OFA (153) -#define NV2080_NOTIFIERS_DSTATE_HDA (154) -#define NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL (155) -#define NV2080_NOTIFIERS_POISON_ERROR_FATAL (156) -#define NV2080_NOTIFIERS_UCODE_RESET (157) -#define NV2080_NOTIFIERS_PLATFORM_POWER_MODE_CHANGE (158) -#define NV2080_NOTIFIERS_SMC_CONFIG_UPDATE (159) -#define NV2080_NOTIFIERS_INFOROM_RRL_OBJECT_UPDATED (160) -#define NV2080_NOTIFIERS_INFOROM_PBL_OBJECT_UPDATED (161) -#define NV2080_NOTIFIERS_LPWR_DIFR_PREFETCH_REQUEST (162) -#define NV2080_NOTIFIERS_SEC_FAULT_ERROR (163) -#define NV2080_NOTIFIERS_POSSIBLE_ERROR (164) -#define NV2080_NOTIFIERS_MAXCOUNT (165) - -// Indexed GR notifier reference -#define NV2080_NOTIFIERS_GR(x) ((x == 0) ? (NV2080_NOTIFIERS_GR0) : (NV2080_NOTIFIERS_GR1 + (x-1))) -#define NV2080_NOTIFIER_TYPE_IS_GR(x) (((x) == NV2080_NOTIFIERS_GR0) || (((x) >= NV2080_NOTIFIERS_GR1) && ((x) <= NV2080_NOTIFIERS_GR7))) -// Indexed CE notifier reference -#define NV2080_NOTIFIERS_CE(x) (NV2080_NOTIFIERS_CE0 + (x)) -#define NV2080_NOTIFIER_TYPE_IS_CE(x) (((x) >= NV2080_NOTIFIERS_CE0) && ((x) <= NV2080_NOTIFIERS_CE9)) -// Indexed MSENC notifier reference -#define NV2080_NOTIFIERS_NVENC(x) (NV2080_NOTIFIERS_NVENC0 + (x)) -#define NV2080_NOTIFIER_TYPE_IS_NVENC(x) (((x) >= NV2080_NOTIFIERS_NVENC0) && ((x) <= NV2080_NOTIFIERS_NVENC2)) -// Indexed NVDEC notifier reference -#define NV2080_NOTIFIERS_NVDEC(x) (NV2080_NOTIFIERS_NVDEC0 + (x)) -#define NV2080_NOTIFIER_TYPE_IS_NVDEC(x) (((x) >= NV2080_NOTIFIERS_NVDEC0) && ((x) <= NV2080_NOTIFIERS_NVDEC7)) -// Indexed NVJPEG notifier reference -#define NV2080_NOTIFIERS_NVJPEG(x) (NV2080_NOTIFIERS_NVJPEG0 + (x)) -#define NV2080_NOTIFIER_TYPE_IS_NVJPEG(x) (((x) >= NV2080_NOTIFIERS_NVJPEG0) && ((x) <= NV2080_NOTIFIERS_NVJPEG7)) - -#define NV2080_NOTIFIERS_GPIO_RISING_INTERRUPT(pin) (NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT+(pin)) -#define NV2080_NOTIFIERS_GPIO_FALLING_INTERRUPT(pin) (NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT+(pin)) - -#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_IN_PROGRESS (0x8000) -#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_BAD_ARGUMENT (0x4000) -#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x2000) -#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x1000) -#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000) - -/* exported engine defines */ -#define NV2080_ENGINE_TYPE_NULL (0x00000000) -#define NV2080_ENGINE_TYPE_GRAPHICS (0x00000001) -#define NV2080_ENGINE_TYPE_GR0 NV2080_ENGINE_TYPE_GRAPHICS -#define NV2080_ENGINE_TYPE_GR1 (0x00000002) -#define NV2080_ENGINE_TYPE_GR2 (0x00000003) -#define NV2080_ENGINE_TYPE_GR3 (0x00000004) -#define NV2080_ENGINE_TYPE_GR4 (0x00000005) -#define NV2080_ENGINE_TYPE_GR5 (0x00000006) -#define NV2080_ENGINE_TYPE_GR6 (0x00000007) -#define NV2080_ENGINE_TYPE_GR7 (0x00000008) -#define NV2080_ENGINE_TYPE_COPY0 (0x00000009) -#define NV2080_ENGINE_TYPE_COPY1 (0x0000000a) -#define NV2080_ENGINE_TYPE_COPY2 (0x0000000b) -#define NV2080_ENGINE_TYPE_COPY3 (0x0000000c) -#define NV2080_ENGINE_TYPE_COPY4 (0x0000000d) -#define NV2080_ENGINE_TYPE_COPY5 (0x0000000e) -#define NV2080_ENGINE_TYPE_COPY6 (0x0000000f) -#define NV2080_ENGINE_TYPE_COPY7 (0x00000010) -#define NV2080_ENGINE_TYPE_COPY8 (0x00000011) -#define NV2080_ENGINE_TYPE_COPY9 (0x00000012) -#define NV2080_ENGINE_TYPE_BSP (0x00000013) -#define NV2080_ENGINE_TYPE_NVDEC0 NV2080_ENGINE_TYPE_BSP -#define NV2080_ENGINE_TYPE_NVDEC1 (0x00000014) -#define NV2080_ENGINE_TYPE_NVDEC2 (0x00000015) -#define NV2080_ENGINE_TYPE_NVDEC3 (0x00000016) -#define NV2080_ENGINE_TYPE_NVDEC4 (0x00000017) -#define NV2080_ENGINE_TYPE_NVDEC5 (0x00000018) -#define NV2080_ENGINE_TYPE_NVDEC6 (0x00000019) -#define NV2080_ENGINE_TYPE_NVDEC7 (0x0000001a) -#define NV2080_ENGINE_TYPE_MSENC (0x0000001b) -#define NV2080_ENGINE_TYPE_NVENC0 NV2080_ENGINE_TYPE_MSENC /* Mutually exclusive alias */ -#define NV2080_ENGINE_TYPE_NVENC1 (0x0000001c) -#define NV2080_ENGINE_TYPE_NVENC2 (0x0000001d) -#define NV2080_ENGINE_TYPE_VP (0x0000001e) -#define NV2080_ENGINE_TYPE_ME (0x0000001f) -#define NV2080_ENGINE_TYPE_PPP (0x00000020) -#define NV2080_ENGINE_TYPE_MPEG (0x00000021) -#define NV2080_ENGINE_TYPE_SW (0x00000022) -#define NV2080_ENGINE_TYPE_CIPHER (0x00000023) -#define NV2080_ENGINE_TYPE_TSEC NV2080_ENGINE_TYPE_CIPHER -#define NV2080_ENGINE_TYPE_VIC (0x00000024) -#define NV2080_ENGINE_TYPE_MP (0x00000025) -#define NV2080_ENGINE_TYPE_SEC2 (0x00000026) -#define NV2080_ENGINE_TYPE_HOST (0x00000027) -#define NV2080_ENGINE_TYPE_DPU (0x00000028) -#define NV2080_ENGINE_TYPE_PMU (0x00000029) -#define NV2080_ENGINE_TYPE_FBFLCN (0x0000002a) -#define NV2080_ENGINE_TYPE_NVJPG (0x0000002b) -#define NV2080_ENGINE_TYPE_NVJPEG0 NV2080_ENGINE_TYPE_NVJPG -#define NV2080_ENGINE_TYPE_NVJPEG1 (0x0000002c) -#define NV2080_ENGINE_TYPE_NVJPEG2 (0x0000002d) -#define NV2080_ENGINE_TYPE_NVJPEG3 (0x0000002e) -#define NV2080_ENGINE_TYPE_NVJPEG4 (0x0000002f) -#define NV2080_ENGINE_TYPE_NVJPEG5 (0x00000030) -#define NV2080_ENGINE_TYPE_NVJPEG6 (0x00000031) -#define NV2080_ENGINE_TYPE_NVJPEG7 (0x00000032) -#define NV2080_ENGINE_TYPE_OFA (0x00000033) -#define NV2080_ENGINE_TYPE_LAST (0x00000034) -#define NV2080_ENGINE_TYPE_ALLENGINES (0xffffffff) - -#define NV2080_ENGINE_TYPE_COPY_SIZE 10 -#define NV2080_ENGINE_TYPE_NVENC_SIZE 3 -#define NV2080_ENGINE_TYPE_NVJPEG_SIZE 8 -#define NV2080_ENGINE_TYPE_NVDEC_SIZE 8 -#define NV2080_ENGINE_TYPE_GR_SIZE 8 - -// Indexed engines -#define NV2080_ENGINE_TYPE_COPY(i) (NV2080_ENGINE_TYPE_COPY0+(i)) -#define NV2080_ENGINE_TYPE_IS_COPY(i) (((i) >= NV2080_ENGINE_TYPE_COPY0) && ((i) < NV2080_ENGINE_TYPE_COPY(NV2080_ENGINE_TYPE_COPY_SIZE))) -#define NV2080_ENGINE_TYPE_COPY_IDX(i) ((i) - NV2080_ENGINE_TYPE_COPY0) - -#define NV2080_ENGINE_TYPE_NVENC(i) (NV2080_ENGINE_TYPE_NVENC0+(i)) -#define NV2080_ENGINE_TYPE_IS_NVENC(i) (((i) >= NV2080_ENGINE_TYPE_NVENC0) && ((i) < NV2080_ENGINE_TYPE_NVENC(NV2080_ENGINE_TYPE_NVENC_SIZE))) -#define NV2080_ENGINE_TYPE_NVENC_IDX(i) ((i) - NV2080_ENGINE_TYPE_NVENC0) - -#define NV2080_ENGINE_TYPE_NVDEC(i) (NV2080_ENGINE_TYPE_NVDEC0+(i)) -#define NV2080_ENGINE_TYPE_IS_NVDEC(i) (((i) >= NV2080_ENGINE_TYPE_NVDEC0) && ((i) < NV2080_ENGINE_TYPE_NVDEC(NV2080_ENGINE_TYPE_NVDEC_SIZE))) -#define NV2080_ENGINE_TYPE_NVDEC_IDX(i) ((i) - NV2080_ENGINE_TYPE_NVDEC0) - -#define NV2080_ENGINE_TYPE_NVJPEG(i) (NV2080_ENGINE_TYPE_NVJPEG0+(i)) -#define NV2080_ENGINE_TYPE_IS_NVJPEG(i) (((i) >= NV2080_ENGINE_TYPE_NVJPEG0) && ((i) < NV2080_ENGINE_TYPE_NVJPEG(NV2080_ENGINE_TYPE_NVJPEG_SIZE))) -#define NV2080_ENGINE_TYPE_NVJPEG_IDX(i) ((i) - NV2080_ENGINE_TYPE_NVJPEG0) - -#define NV2080_ENGINE_TYPE_GR(i) (NV2080_ENGINE_TYPE_GR0 + (i)) -#define NV2080_ENGINE_TYPE_IS_GR(i) (((i) >= NV2080_ENGINE_TYPE_GR0) && ((i) < NV2080_ENGINE_TYPE_GR(NV2080_ENGINE_TYPE_GR_SIZE))) -#define NV2080_ENGINE_TYPE_GR_IDX(i) ((i) - NV2080_ENGINE_TYPE_GR0) - -#define NV2080_ENGINE_TYPE_IS_VALID(i) (((i) > (NV2080_ENGINE_TYPE_NULL)) && ((i) < (NV2080_ENGINE_TYPE_LAST))) - -/* exported client defines */ -#define NV2080_CLIENT_TYPE_TEX (0x00000001) -#define NV2080_CLIENT_TYPE_COLOR (0x00000002) -#define NV2080_CLIENT_TYPE_DEPTH (0x00000003) -#define NV2080_CLIENT_TYPE_DA (0x00000004) -#define NV2080_CLIENT_TYPE_FE (0x00000005) -#define NV2080_CLIENT_TYPE_SCC (0x00000006) -#define NV2080_CLIENT_TYPE_WID (0x00000007) -#define NV2080_CLIENT_TYPE_MSVLD (0x00000008) -#define NV2080_CLIENT_TYPE_MSPDEC (0x00000009) -#define NV2080_CLIENT_TYPE_MSPPP (0x0000000a) -#define NV2080_CLIENT_TYPE_VIC (0x0000000b) -#define NV2080_CLIENT_TYPE_ALLCLIENTS (0xffffffff) - -/* GC5 Gpu Ready event defines */ -#define NV2080_GC5_EXIT_COMPLETE (0x00000001) -#define NV2080_GC5_ENTRY_ABORTED (0x00000002) - -/* Platform Power Mode event defines */ -#define NV2080_PLATFORM_POWER_MODE_CHANGE_COMPLETION (0x00000000) -#define NV2080_PLATFORM_POWER_MODE_CHANGE_ACPI_NOTIFICATION (0x00000001) - -/* NvNotification[] fields and values */ -#define NV2080_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) -/* pio method data structure */ -typedef volatile struct _cl2080_tag0 { - NvV32 Reserved00[0x7c0]; -} Nv2080Typedef, Nv20Subdevice0; -#define NV2080_TYPEDEF Nv20Subdevice0 +#define NV20_SUBDEVICE_0 (0x2080U) /* finn: Evaluated from "NV2080_ALLOC_PARAMETERS_MESSAGE_ID" */ /* NvAlloc parameteters */ -#define NV2080_MAX_SUBDEVICES NV_MAX_SUBDEVICES -typedef struct { - NvU32 subDeviceId; +#define NV2080_MAX_SUBDEVICES NV_MAX_SUBDEVICES + +#define NV2080_ALLOC_PARAMETERS_MESSAGE_ID (0x2080U) + +typedef struct NV2080_ALLOC_PARAMETERS { + NvU32 subDeviceId; } NV2080_ALLOC_PARAMETERS; -/* HDCP Status change notification information */ -typedef struct Nv2080HdcpStatusChangeNotificationRec { - NvU32 displayId; - NvU32 hdcpStatusChangeNotif; -} Nv2080HdcpStatusChangeNotification; - -/* Pstate change notification information */ -typedef struct Nv2080PStateChangeNotificationRec { - struct { - NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/ - } timeStamp; /* -0007*/ - NvU32 NewPstate; -} Nv2080PStateChangeNotification; - -/* Clocks change notification information */ -typedef struct Nv2080ClocksChangeNotificationRec { - struct { - NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/ - } timeStamp; /* -0007*/ -} Nv2080ClocksChangeNotification; - -/* WorkLoad Modulation state change notification information*/ -typedef struct Nv2080WorkloadModulationChangeNotificationRec { - struct { - NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/ - } timeStamp; /* -0007*/ - NvBool WorkloadModulationEnabled; -} Nv2080WorkloadModulationChangeNotification; - -/* Hotplug notification information */ -typedef struct { - NvU32 plugDisplayMask; - NvU32 unplugDisplayMask; -} Nv2080HotplugNotification; - -/* Power state changing notification information */ -typedef struct { - NvBool bSwitchToAC; - NvBool bGPUCapabilityChanged; - NvU32 displayMaskAffected; -} Nv2080PowerEventNotification; - -/* DP IRQ notification information */ -typedef struct Nv2080DpIrqNotificationRec { - NvU32 displayId; -} Nv2080DpIrqNotification; - -/* XUSB/PPC D-State change notification information */ -typedef struct Nv2080DstateXusbPpcNotificationRec { - NvU32 dstateXusb; - NvU32 dstatePpc; -} Nv2080DstateXusbPpcNotification; - -/* XUSB/PPC Connection status notification information */ -typedef struct Nv2080XusbPpcConnectStateNotificationRec { - NvBool bConnected; -} Nv2080XusbPpcConnectStateNotification; - -/* ACPI event notification information */ -typedef struct Nv2080ACPIEvent { - NvU32 event; -} Nv2080ACPIEvent; - -/* Cooler Zone notification information */ -typedef struct _NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC { - NvU32 currentZone; -} NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC; - -/* Thermal Zone notification information */ -typedef struct _NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC { - NvU32 currentZone; -} NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC; - -/* HDCP ref count change notification information */ -typedef struct Nv2080AudioHdcpRequestRec { - NvU32 displayId; - NvU32 requestedState; -} Nv2080AudioHdcpRequest; - -/* Gpu ready event information */ -typedef struct Nv2080GC5GpuReadyParams { - NvU32 event; - NvU32 sciIntr0; - NvU32 sciIntr1; -} Nv2080GC5GpuReadyParams; - -/* Priv reg access fault notification information */ -typedef struct { - NvU32 errAddr; -} Nv2080PrivRegAccessFaultNotification; - -/* HDA D-State change notification information - * See @HDACODEC_DSTATE for definitions - */ -typedef struct Nv2080DstateHdaCodecNotificationRec { - NvU32 dstateHdaCodec; -} Nv2080DstateHdaCodecNotification; - -/* - * Platform Power Mode event information - */ -typedef struct _NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS { - NvU8 platformPowerModeIndex; - NvU8 platformPowerModeMask; - NvU8 eventReason; -} NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS; - -#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_INDEX 7:0 -#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_MASK 15:8 -#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_REASON 23:16 - -/* - * ENGINE_INFO_TYPE_NV2080 of the engine for which the QOS interrupt has been raised - */ -typedef struct { - NvU32 engineType; -} Nv2080QosIntrNotification; - -typedef struct { - NvU64 physAddress NV_ALIGN_BYTES(8); -} Nv2080EccDbeNotification; - -/* - * LPWR DIFR Prefetch Request - Size of L2 Cache - */ -typedef struct { - NvU32 l2CacheSize; -} Nv2080LpwrDifrPrefetchNotification; - -#ifdef __cplusplus -}; /* extern "C" */ -#endif - -#endif /* _cl2080_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/cl2080_notification.h b/src/common/sdk/nvidia/inc/class/cl2080_notification.h new file mode 100644 index 000000000..1879905f2 --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/cl2080_notification.h @@ -0,0 +1,497 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl2080_notification_h_ +#define _cl2080_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* event values */ +#define NV2080_NOTIFIERS_SW (0) +#define NV2080_NOTIFIERS_HOTPLUG (1) +#define NV2080_NOTIFIERS_POWER_CONNECTOR (2) +#define NV2080_NOTIFIERS_THERMAL_SW (3) +#define NV2080_NOTIFIERS_THERMAL_HW (4) +#define NV2080_NOTIFIERS_FULL_SCREEN_CHANGE (5) +#define NV2080_NOTIFIERS_EVENTBUFFER (6) +#define NV2080_NOTIFIERS_DP_IRQ (7) +#define NV2080_NOTIFIERS_GR_DEBUG_INTR (8) +#define NV2080_NOTIFIERS_PMU_EVENT (9) +#define NV2080_NOTIFIERS_PMU_COMMAND (10) +#define NV2080_NOTIFIERS_TIMER (11) +#define NV2080_NOTIFIERS_GRAPHICS (12) +#define NV2080_NOTIFIERS_PPP (13) +#define NV2080_NOTIFIERS_VLD (14) // also known as BSP +#define NV2080_NOTIFIERS_NVDEC0 NV2080_NOTIFIERS_VLD +#define NV2080_NOTIFIERS_NVDEC1 (15) +#define NV2080_NOTIFIERS_NVDEC2 (16) +#define NV2080_NOTIFIERS_NVDEC3 (17) +#define NV2080_NOTIFIERS_NVDEC4 (18) +#define NV2080_NOTIFIERS_NVDEC5 (19) +#define NV2080_NOTIFIERS_NVDEC6 (20) +#define NV2080_NOTIFIERS_NVDEC7 (21) +#define NV2080_NOTIFIERS_PDEC (22) // also known as VP +#define NV2080_NOTIFIERS_CE0 (23) +#define NV2080_NOTIFIERS_CE1 (24) +#define NV2080_NOTIFIERS_CE2 (25) +#define NV2080_NOTIFIERS_CE3 (26) +#define NV2080_NOTIFIERS_CE4 (27) +#define NV2080_NOTIFIERS_CE5 (28) +#define NV2080_NOTIFIERS_CE6 (29) +#define NV2080_NOTIFIERS_CE7 (30) +#define NV2080_NOTIFIERS_CE8 (31) +#define NV2080_NOTIFIERS_CE9 (32) +#define NV2080_NOTIFIERS_PSTATE_CHANGE (33) +#define NV2080_NOTIFIERS_HDCP_STATUS_CHANGE (34) +#define NV2080_NOTIFIERS_FIFO_EVENT_MTHD (35) +#define NV2080_NOTIFIERS_PRIV_RING_HANG (36) +#define NV2080_NOTIFIERS_RC_ERROR (37) +#define NV2080_NOTIFIERS_MSENC (38) +#define NV2080_NOTIFIERS_NVENC0 NV2080_NOTIFIERS_MSENC +#define NV2080_NOTIFIERS_NVENC1 (39) +#define NV2080_NOTIFIERS_NVENC2 (40) +#define NV2080_NOTIFIERS_UNUSED_0 (41) // Unused +#define NV2080_NOTIFIERS_ACPI_NOTIFY (42) +#define NV2080_NOTIFIERS_COOLER_DIAG_ZONE (43) +#define NV2080_NOTIFIERS_THERMAL_DIAG_ZONE (44) +#define NV2080_NOTIFIERS_AUDIO_HDCP_REQUEST (45) +#define NV2080_NOTIFIERS_WORKLOAD_MODULATION_CHANGE (46) +#define NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT (47) +#define NV2080_NOTIFIERS_GPIO_1_RISING_INTERRUPT (48) +#define NV2080_NOTIFIERS_GPIO_2_RISING_INTERRUPT (49) +#define NV2080_NOTIFIERS_GPIO_3_RISING_INTERRUPT (50) +#define NV2080_NOTIFIERS_GPIO_4_RISING_INTERRUPT (51) +#define NV2080_NOTIFIERS_GPIO_5_RISING_INTERRUPT (52) +#define NV2080_NOTIFIERS_GPIO_6_RISING_INTERRUPT (53) +#define NV2080_NOTIFIERS_GPIO_7_RISING_INTERRUPT (54) +#define NV2080_NOTIFIERS_GPIO_8_RISING_INTERRUPT (55) +#define NV2080_NOTIFIERS_GPIO_9_RISING_INTERRUPT (56) +#define NV2080_NOTIFIERS_GPIO_10_RISING_INTERRUPT (57) +#define NV2080_NOTIFIERS_GPIO_11_RISING_INTERRUPT (58) +#define NV2080_NOTIFIERS_GPIO_12_RISING_INTERRUPT (59) +#define NV2080_NOTIFIERS_GPIO_13_RISING_INTERRUPT (60) +#define NV2080_NOTIFIERS_GPIO_14_RISING_INTERRUPT (61) +#define NV2080_NOTIFIERS_GPIO_15_RISING_INTERRUPT (62) +#define NV2080_NOTIFIERS_GPIO_16_RISING_INTERRUPT (63) +#define NV2080_NOTIFIERS_GPIO_17_RISING_INTERRUPT (64) +#define NV2080_NOTIFIERS_GPIO_18_RISING_INTERRUPT (65) +#define NV2080_NOTIFIERS_GPIO_19_RISING_INTERRUPT (66) +#define NV2080_NOTIFIERS_GPIO_20_RISING_INTERRUPT (67) +#define NV2080_NOTIFIERS_GPIO_21_RISING_INTERRUPT (68) +#define NV2080_NOTIFIERS_GPIO_22_RISING_INTERRUPT (69) +#define NV2080_NOTIFIERS_GPIO_23_RISING_INTERRUPT (70) +#define NV2080_NOTIFIERS_GPIO_24_RISING_INTERRUPT (71) +#define NV2080_NOTIFIERS_GPIO_25_RISING_INTERRUPT (72) +#define NV2080_NOTIFIERS_GPIO_26_RISING_INTERRUPT (73) +#define NV2080_NOTIFIERS_GPIO_27_RISING_INTERRUPT (74) +#define NV2080_NOTIFIERS_GPIO_28_RISING_INTERRUPT (75) +#define NV2080_NOTIFIERS_GPIO_29_RISING_INTERRUPT (76) +#define NV2080_NOTIFIERS_GPIO_30_RISING_INTERRUPT (77) +#define NV2080_NOTIFIERS_GPIO_31_RISING_INTERRUPT (78) +#define NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT (79) +#define NV2080_NOTIFIERS_GPIO_1_FALLING_INTERRUPT (80) +#define NV2080_NOTIFIERS_GPIO_2_FALLING_INTERRUPT (81) +#define NV2080_NOTIFIERS_GPIO_3_FALLING_INTERRUPT (82) +#define NV2080_NOTIFIERS_GPIO_4_FALLING_INTERRUPT (83) +#define NV2080_NOTIFIERS_GPIO_5_FALLING_INTERRUPT (84) +#define NV2080_NOTIFIERS_GPIO_6_FALLING_INTERRUPT (85) +#define NV2080_NOTIFIERS_GPIO_7_FALLING_INTERRUPT (86) +#define NV2080_NOTIFIERS_GPIO_8_FALLING_INTERRUPT (87) +#define NV2080_NOTIFIERS_GPIO_9_FALLING_INTERRUPT (88) +#define NV2080_NOTIFIERS_GPIO_10_FALLING_INTERRUPT (89) +#define NV2080_NOTIFIERS_GPIO_11_FALLING_INTERRUPT (90) +#define NV2080_NOTIFIERS_GPIO_12_FALLING_INTERRUPT (91) +#define NV2080_NOTIFIERS_GPIO_13_FALLING_INTERRUPT (92) +#define NV2080_NOTIFIERS_GPIO_14_FALLING_INTERRUPT (93) +#define NV2080_NOTIFIERS_GPIO_15_FALLING_INTERRUPT (94) +#define NV2080_NOTIFIERS_GPIO_16_FALLING_INTERRUPT (95) +#define NV2080_NOTIFIERS_GPIO_17_FALLING_INTERRUPT (96) +#define NV2080_NOTIFIERS_GPIO_18_FALLING_INTERRUPT (97) +#define NV2080_NOTIFIERS_GPIO_19_FALLING_INTERRUPT (98) +#define NV2080_NOTIFIERS_GPIO_20_FALLING_INTERRUPT (99) +#define NV2080_NOTIFIERS_GPIO_21_FALLING_INTERRUPT (100) +#define NV2080_NOTIFIERS_GPIO_22_FALLING_INTERRUPT (101) +#define NV2080_NOTIFIERS_GPIO_23_FALLING_INTERRUPT (102) +#define NV2080_NOTIFIERS_GPIO_24_FALLING_INTERRUPT (103) +#define NV2080_NOTIFIERS_GPIO_25_FALLING_INTERRUPT (104) +#define NV2080_NOTIFIERS_GPIO_26_FALLING_INTERRUPT (105) +#define NV2080_NOTIFIERS_GPIO_27_FALLING_INTERRUPT (106) +#define NV2080_NOTIFIERS_GPIO_28_FALLING_INTERRUPT (107) +#define NV2080_NOTIFIERS_GPIO_29_FALLING_INTERRUPT (108) +#define NV2080_NOTIFIERS_GPIO_30_FALLING_INTERRUPT (109) +#define NV2080_NOTIFIERS_GPIO_31_FALLING_INTERRUPT (110) +#define NV2080_NOTIFIERS_ECC_SBE (111) +#define NV2080_NOTIFIERS_ECC_DBE (112) +#define NV2080_NOTIFIERS_STEREO_EMITTER_DETECTION (113) +#define NV2080_NOTIFIERS_GC5_GPU_READY (114) +#define NV2080_NOTIFIERS_SEC2 (115) +#define NV2080_NOTIFIERS_GC6_REFCOUNT_INC (116) +#define NV2080_NOTIFIERS_GC6_REFCOUNT_DEC (117) +#define NV2080_NOTIFIERS_POWER_EVENT (118) +#define NV2080_NOTIFIERS_CLOCKS_CHANGE (119) +#define NV2080_NOTIFIERS_HOTPLUG_PROCESSING_COMPLETE (120) +#define NV2080_NOTIFIERS_PHYSICAL_PAGE_FAULT (121) +#define NV2080_NOTIFIERS_RESERVED122 (122) +#define NV2080_NOTIFIERS_NVLINK_ERROR_FATAL (123) +#define NV2080_NOTIFIERS_PRIV_REG_ACCESS_FAULT (124) +#define NV2080_NOTIFIERS_NVLINK_ERROR_RECOVERY_REQUIRED (125) +#define NV2080_NOTIFIERS_NVJPG (126) +#define NV2080_NOTIFIERS_NVJPEG0 NV2080_NOTIFIERS_NVJPG +#define NV2080_NOTIFIERS_NVJPEG1 (127) +#define NV2080_NOTIFIERS_NVJPEG2 (128) +#define NV2080_NOTIFIERS_NVJPEG3 (129) +#define NV2080_NOTIFIERS_NVJPEG4 (130) +#define NV2080_NOTIFIERS_NVJPEG5 (131) +#define NV2080_NOTIFIERS_NVJPEG6 (132) +#define NV2080_NOTIFIERS_NVJPEG7 (133) +#define NV2080_NOTIFIERS_RUNLIST_AND_ENG_IDLE (134) +#define NV2080_NOTIFIERS_RUNLIST_ACQUIRE (135) +#define NV2080_NOTIFIERS_RUNLIST_ACQUIRE_AND_ENG_IDLE (136) +#define NV2080_NOTIFIERS_RUNLIST_IDLE (137) +#define NV2080_NOTIFIERS_TSG_PREEMPT_COMPLETE (138) +#define NV2080_NOTIFIERS_RUNLIST_PREEMPT_COMPLETE (139) +#define NV2080_NOTIFIERS_CTXSW_TIMEOUT (140) +#define NV2080_NOTIFIERS_INFOROM_ECC_OBJECT_UPDATED (141) +#define NV2080_NOTIFIERS_NVTELEMETRY_REPORT_EVENT (142) +#define NV2080_NOTIFIERS_DSTATE_XUSB_PPC (143) +#define NV2080_NOTIFIERS_FECS_CTX_SWITCH (144) +#define NV2080_NOTIFIERS_XUSB_PPC_CONNECTED (145) +#define NV2080_NOTIFIERS_GR0 NV2080_NOTIFIERS_GRAPHICS +#define NV2080_NOTIFIERS_GR1 (146) +#define NV2080_NOTIFIERS_GR2 (147) +#define NV2080_NOTIFIERS_GR3 (148) +#define NV2080_NOTIFIERS_GR4 (149) +#define NV2080_NOTIFIERS_GR5 (150) +#define NV2080_NOTIFIERS_GR6 (151) +#define NV2080_NOTIFIERS_GR7 (152) +#define NV2080_NOTIFIERS_OFA (153) +#define NV2080_NOTIFIERS_DSTATE_HDA (154) +#define NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL (155) +#define NV2080_NOTIFIERS_POISON_ERROR_FATAL (156) +#define NV2080_NOTIFIERS_UCODE_RESET (157) +#define NV2080_NOTIFIERS_PLATFORM_POWER_MODE_CHANGE (158) +#define NV2080_NOTIFIERS_SMC_CONFIG_UPDATE (159) +#define NV2080_NOTIFIERS_INFOROM_RRL_OBJECT_UPDATED (160) +#define NV2080_NOTIFIERS_INFOROM_PBL_OBJECT_UPDATED (161) +#define NV2080_NOTIFIERS_LPWR_DIFR_PREFETCH_REQUEST (162) +#define NV2080_NOTIFIERS_SEC_FAULT_ERROR (163) +#define NV2080_NOTIFIERS_POSSIBLE_ERROR (164) +#define NV2080_NOTIFIERS_NVLINK_INFO_LINK_UP (165) +#define NV2080_NOTIFIERS_NVLINK_INFO_LINK_DOWN (176) +#define NV2080_NOTIFIERS_MAXCOUNT (177) + +// Indexed GR notifier reference +#define NV2080_NOTIFIERS_GR(x) ((x == 0) ? (NV2080_NOTIFIERS_GR0) : (NV2080_NOTIFIERS_GR1 + (x - 1))) +#define NV2080_NOTIFIERS_GR_IDX(x) ((x) - NV2080_NOTIFIERS_GR0) +#define NV2080_NOTIFIER_TYPE_IS_GR(x) (((x) == NV2080_NOTIFIERS_GR0) || (((x) >= NV2080_NOTIFIERS_GR1) && ((x) <= NV2080_NOTIFIERS_GR7))) + +#define NV2080_NOTIFIERS_CE(x) (NV2080_NOTIFIERS_CE0 + (x)) +#define NV2080_NOTIFIERS_CE_IDX(x) ((x) - NV2080_NOTIFIERS_CE0) +#define NV2080_NOTIFIER_TYPE_IS_CE(x) (((x) >= NV2080_NOTIFIERS_CE0) && ((x) <= NV2080_NOTIFIERS_CE9)) + +// Indexed MSENC notifier reference +#define NV2080_NOTIFIERS_NVENC(x) (NV2080_NOTIFIERS_NVENC0 + (x)) +#define NV2080_NOTIFIERS_NVENC_IDX(x) ((x) - NV2080_NOTIFIERS_NVENC0) +#define NV2080_NOTIFIER_TYPE_IS_NVENC(x) (((x) >= NV2080_NOTIFIERS_NVENC0) && ((x) <= NV2080_NOTIFIERS_NVENC2)) +// Indexed NVDEC notifier reference +#define NV2080_NOTIFIERS_NVDEC(x) (NV2080_NOTIFIERS_NVDEC0 + (x)) +#define NV2080_NOTIFIERS_NVDEC_IDX(x) ((x) - NV2080_NOTIFIERS_NVDEC0) +#define NV2080_NOTIFIER_TYPE_IS_NVDEC(x) (((x) >= NV2080_NOTIFIERS_NVDEC0) && ((x) <= NV2080_NOTIFIERS_NVDEC7)) +// Indexed NVJPEG notifier reference +#define NV2080_NOTIFIERS_NVJPEG(x) (NV2080_NOTIFIERS_NVJPEG0 + (x)) +#define NV2080_NOTIFIERS_NVJPEG_IDX(x) ((x) - NV2080_NOTIFIERS_NVJPEG0) +#define NV2080_NOTIFIER_TYPE_IS_NVJPEG(x) (((x) >= NV2080_NOTIFIERS_NVJPEG0) && ((x) <= NV2080_NOTIFIERS_NVJPEG7)) + +#define NV2080_NOTIFIERS_GPIO_RISING_INTERRUPT(pin) (NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT + (pin)) +#define NV2080_NOTIFIERS_GPIO_FALLING_INTERRUPT(pin) (NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT + (pin)) + +#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_IN_PROGRESS (0x8000) +#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_BAD_ARGUMENT (0x4000) +#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x2000) +#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x1000) +#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000) + +/* exported engine defines */ +#define NV2080_ENGINE_TYPE_NULL (0x00000000) +#define NV2080_ENGINE_TYPE_GRAPHICS (0x00000001) +#define NV2080_ENGINE_TYPE_GR0 NV2080_ENGINE_TYPE_GRAPHICS +#define NV2080_ENGINE_TYPE_GR1 (0x00000002) +#define NV2080_ENGINE_TYPE_GR2 (0x00000003) +#define NV2080_ENGINE_TYPE_GR3 (0x00000004) +#define NV2080_ENGINE_TYPE_GR4 (0x00000005) +#define NV2080_ENGINE_TYPE_GR5 (0x00000006) +#define NV2080_ENGINE_TYPE_GR6 (0x00000007) +#define NV2080_ENGINE_TYPE_GR7 (0x00000008) +#define NV2080_ENGINE_TYPE_COPY0 (0x00000009) +#define NV2080_ENGINE_TYPE_COPY1 (0x0000000a) +#define NV2080_ENGINE_TYPE_COPY2 (0x0000000b) +#define NV2080_ENGINE_TYPE_COPY3 (0x0000000c) +#define NV2080_ENGINE_TYPE_COPY4 (0x0000000d) +#define NV2080_ENGINE_TYPE_COPY5 (0x0000000e) +#define NV2080_ENGINE_TYPE_COPY6 (0x0000000f) +#define NV2080_ENGINE_TYPE_COPY7 (0x00000010) +#define NV2080_ENGINE_TYPE_COPY8 (0x00000011) +#define NV2080_ENGINE_TYPE_COPY9 (0x00000012) +#define NV2080_ENGINE_TYPE_BSP (0x00000013) +#define NV2080_ENGINE_TYPE_NVDEC0 NV2080_ENGINE_TYPE_BSP +#define NV2080_ENGINE_TYPE_NVDEC1 (0x00000014) +#define NV2080_ENGINE_TYPE_NVDEC2 (0x00000015) +#define NV2080_ENGINE_TYPE_NVDEC3 (0x00000016) +#define NV2080_ENGINE_TYPE_NVDEC4 (0x00000017) +#define NV2080_ENGINE_TYPE_NVDEC5 (0x00000018) +#define NV2080_ENGINE_TYPE_NVDEC6 (0x00000019) +#define NV2080_ENGINE_TYPE_NVDEC7 (0x0000001a) +#define NV2080_ENGINE_TYPE_MSENC (0x0000001b) +#define NV2080_ENGINE_TYPE_NVENC0 NV2080_ENGINE_TYPE_MSENC /* Mutually exclusive alias */ +#define NV2080_ENGINE_TYPE_NVENC1 (0x0000001c) +#define NV2080_ENGINE_TYPE_NVENC2 (0x0000001d) +#define NV2080_ENGINE_TYPE_VP (0x0000001e) +#define NV2080_ENGINE_TYPE_ME (0x0000001f) +#define NV2080_ENGINE_TYPE_PPP (0x00000020) +#define NV2080_ENGINE_TYPE_MPEG (0x00000021) +#define NV2080_ENGINE_TYPE_SW (0x00000022) +#define NV2080_ENGINE_TYPE_CIPHER (0x00000023) +#define NV2080_ENGINE_TYPE_TSEC NV2080_ENGINE_TYPE_CIPHER +#define NV2080_ENGINE_TYPE_VIC (0x00000024) +#define NV2080_ENGINE_TYPE_MP (0x00000025) +#define NV2080_ENGINE_TYPE_SEC2 (0x00000026) +#define NV2080_ENGINE_TYPE_HOST (0x00000027) +#define NV2080_ENGINE_TYPE_DPU (0x00000028) +#define NV2080_ENGINE_TYPE_PMU (0x00000029) +#define NV2080_ENGINE_TYPE_FBFLCN (0x0000002a) +#define NV2080_ENGINE_TYPE_NVJPG (0x0000002b) +#define NV2080_ENGINE_TYPE_NVJPEG0 NV2080_ENGINE_TYPE_NVJPG +#define NV2080_ENGINE_TYPE_NVJPEG1 (0x0000002c) +#define NV2080_ENGINE_TYPE_NVJPEG2 (0x0000002d) +#define NV2080_ENGINE_TYPE_NVJPEG3 (0x0000002e) +#define NV2080_ENGINE_TYPE_NVJPEG4 (0x0000002f) +#define NV2080_ENGINE_TYPE_NVJPEG5 (0x00000030) +#define NV2080_ENGINE_TYPE_NVJPEG6 (0x00000031) +#define NV2080_ENGINE_TYPE_NVJPEG7 (0x00000032) +#define NV2080_ENGINE_TYPE_OFA (0x00000033) +#define NV2080_ENGINE_TYPE_LAST (0x0000003e) +#define NV2080_ENGINE_TYPE_ALLENGINES (0xffffffff) + +#define NV2080_ENGINE_TYPE_COPY_SIZE 10 +#define NV2080_ENGINE_TYPE_NVENC_SIZE 3 +#define NV2080_ENGINE_TYPE_NVJPEG_SIZE 8 +#define NV2080_ENGINE_TYPE_NVDEC_SIZE 8 +#define NV2080_ENGINE_TYPE_GR_SIZE 8 + +// Indexed engines +#define NV2080_ENGINE_TYPE_COPY(i) (NV2080_ENGINE_TYPE_COPY0+(i)) +#define NV2080_ENGINE_TYPE_IS_COPY(i) (((i) >= NV2080_ENGINE_TYPE_COPY0) && ((i) <= NV2080_ENGINE_TYPE_COPY9)) +#define NV2080_ENGINE_TYPE_COPY_IDX(i) ((i) - NV2080_ENGINE_TYPE_COPY0) + +#define NV2080_ENGINE_TYPE_NVENC(i) (NV2080_ENGINE_TYPE_NVENC0+(i)) +#define NV2080_ENGINE_TYPE_IS_NVENC(i) (((i) >= NV2080_ENGINE_TYPE_NVENC0) && ((i) < NV2080_ENGINE_TYPE_NVENC(NV2080_ENGINE_TYPE_NVENC_SIZE))) +#define NV2080_ENGINE_TYPE_NVENC_IDX(i) ((i) - NV2080_ENGINE_TYPE_NVENC0) + +#define NV2080_ENGINE_TYPE_NVDEC(i) (NV2080_ENGINE_TYPE_NVDEC0+(i)) +#define NV2080_ENGINE_TYPE_IS_NVDEC(i) (((i) >= NV2080_ENGINE_TYPE_NVDEC0) && ((i) < NV2080_ENGINE_TYPE_NVDEC(NV2080_ENGINE_TYPE_NVDEC_SIZE))) +#define NV2080_ENGINE_TYPE_NVDEC_IDX(i) ((i) - NV2080_ENGINE_TYPE_NVDEC0) + +#define NV2080_ENGINE_TYPE_NVJPEG(i) (NV2080_ENGINE_TYPE_NVJPEG0+(i)) +#define NV2080_ENGINE_TYPE_IS_NVJPEG(i) (((i) >= NV2080_ENGINE_TYPE_NVJPEG0) && ((i) < NV2080_ENGINE_TYPE_NVJPEG(NV2080_ENGINE_TYPE_NVJPEG_SIZE))) +#define NV2080_ENGINE_TYPE_NVJPEG_IDX(i) ((i) - NV2080_ENGINE_TYPE_NVJPEG0) + +#define NV2080_ENGINE_TYPE_GR(i) (NV2080_ENGINE_TYPE_GR0 + (i)) +#define NV2080_ENGINE_TYPE_IS_GR(i) (((i) >= NV2080_ENGINE_TYPE_GR0) && ((i) < NV2080_ENGINE_TYPE_GR(NV2080_ENGINE_TYPE_GR_SIZE))) +#define NV2080_ENGINE_TYPE_GR_IDX(i) ((i) - NV2080_ENGINE_TYPE_GR0) + +#define NV2080_ENGINE_TYPE_IS_VALID(i) (((i) > (NV2080_ENGINE_TYPE_NULL)) && ((i) < (NV2080_ENGINE_TYPE_LAST))) + +/* exported client defines */ +#define NV2080_CLIENT_TYPE_TEX (0x00000001) +#define NV2080_CLIENT_TYPE_COLOR (0x00000002) +#define NV2080_CLIENT_TYPE_DEPTH (0x00000003) +#define NV2080_CLIENT_TYPE_DA (0x00000004) +#define NV2080_CLIENT_TYPE_FE (0x00000005) +#define NV2080_CLIENT_TYPE_SCC (0x00000006) +#define NV2080_CLIENT_TYPE_WID (0x00000007) +#define NV2080_CLIENT_TYPE_MSVLD (0x00000008) +#define NV2080_CLIENT_TYPE_MSPDEC (0x00000009) +#define NV2080_CLIENT_TYPE_MSPPP (0x0000000a) +#define NV2080_CLIENT_TYPE_VIC (0x0000000b) +#define NV2080_CLIENT_TYPE_ALLCLIENTS (0xffffffff) + +/* GC5 Gpu Ready event defines */ +#define NV2080_GC5_EXIT_COMPLETE (0x00000001) +#define NV2080_GC5_ENTRY_ABORTED (0x00000002) + +/* Platform Power Mode event defines */ +#define NV2080_PLATFORM_POWER_MODE_CHANGE_COMPLETION (0x00000000) +#define NV2080_PLATFORM_POWER_MODE_CHANGE_ACPI_NOTIFICATION (0x00000001) + +/* NvNotification[] fields and values */ +#define NV2080_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000) +/* pio method data structure */ +typedef volatile struct _cl2080_tag0 { + NvV32 Reserved00[0x7c0]; +} Nv2080Typedef, Nv20Subdevice0; +#define NV2080_TYPEDEF Nv20Subdevice0 + +/* HDCP Status change notification information */ +typedef struct Nv2080HdcpStatusChangeNotificationRec { + NvU32 displayId; + NvU32 hdcpStatusChangeNotif; +} Nv2080HdcpStatusChangeNotification; + +/* Pstate change notification information */ +typedef struct Nv2080PStateChangeNotificationRec { + struct { + NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/ + } timeStamp; /* -0007*/ + NvU32 NewPstate; +} Nv2080PStateChangeNotification; + +/* Clocks change notification information */ +typedef struct Nv2080ClocksChangeNotificationRec { + struct { + NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/ + } timeStamp; /* -0007*/ +} Nv2080ClocksChangeNotification; + +/* WorkLoad Modulation state change notification information*/ +typedef struct Nv2080WorkloadModulationChangeNotificationRec { + struct { + NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/ + } timeStamp; /* -0007*/ + NvBool WorkloadModulationEnabled; +} Nv2080WorkloadModulationChangeNotification; + +/* Hotplug notification information */ +typedef struct { + NvU32 plugDisplayMask; + NvU32 unplugDisplayMask; +} Nv2080HotplugNotification; + +/* Power state changing notification information */ +typedef struct { + NvBool bSwitchToAC; + NvBool bGPUCapabilityChanged; + NvU32 displayMaskAffected; +} Nv2080PowerEventNotification; + +/* DP IRQ notification information */ +typedef struct Nv2080DpIrqNotificationRec { + NvU32 displayId; +} Nv2080DpIrqNotification; + +/* XUSB/PPC D-State change notification information */ +typedef struct Nv2080DstateXusbPpcNotificationRec { + NvU32 dstateXusb; + NvU32 dstatePpc; +} Nv2080DstateXusbPpcNotification; + +/* XUSB/PPC Connection status notification information */ +typedef struct Nv2080XusbPpcConnectStateNotificationRec { + NvBool bConnected; +} Nv2080XusbPpcConnectStateNotification; + +/* ACPI event notification information */ +typedef struct Nv2080ACPIEvent { + NvU32 event; +} Nv2080ACPIEvent; + +/* Cooler Zone notification information */ +typedef struct _NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC { + NvU32 currentZone; +} NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC; + +/* Thermal Zone notification information */ +typedef struct _NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC { + NvU32 currentZone; +} NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC; + +/* HDCP ref count change notification information */ +typedef struct Nv2080AudioHdcpRequestRec { + NvU32 displayId; + NvU32 requestedState; +} Nv2080AudioHdcpRequest; + +/* Gpu ready event information */ +typedef struct Nv2080GC5GpuReadyParams { + NvU32 event; + NvU32 sciIntr0; + NvU32 sciIntr1; +} Nv2080GC5GpuReadyParams; + +/* Priv reg access fault notification information */ +typedef struct { + NvU32 errAddr; +} Nv2080PrivRegAccessFaultNotification; + +/* HDA D-State change notification information + * See @HDACODEC_DSTATE for definitions + */ +typedef struct Nv2080DstateHdaCodecNotificationRec { + NvU32 dstateHdaCodec; +} Nv2080DstateHdaCodecNotification; + +/* + * Platform Power Mode event information + */ +typedef struct _NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS { + NvU8 platformPowerModeIndex; + NvU8 platformPowerModeMask; + NvU8 eventReason; +} NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS; + +#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_INDEX 7:0 +#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_MASK 15:8 +#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_REASON 23:16 + +/* + * ENGINE_INFO_TYPE_NV2080 of the engine for which the QOS interrupt has been raised + */ +typedef struct { + NvU32 engineType; +} Nv2080QosIntrNotification; + +typedef struct { + NvU64 physAddress NV_ALIGN_BYTES(8); +} Nv2080EccDbeNotification; + +/* + * LPWR DIFR Prefetch Request - Size of L2 Cache + */ +typedef struct { + NvU32 l2CacheSize; +} Nv2080LpwrDifrPrefetchNotification; + +/* + * Nvlink Link status change Notification + */ +typedef struct { + NvU32 GpuId; + NvU32 linkId; +} Nv2080NvlinkLnkChangeNotification; + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl2080_notification_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/cl2081.h b/src/common/sdk/nvidia/inc/class/cl2081.h index e1301bd01..05341cac1 100644 --- a/src/common/sdk/nvidia/inc/class/cl2081.h +++ b/src/common/sdk/nvidia/inc/class/cl2081.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -20,24 +20,21 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ - -#ifndef _cl2081_h_ -#define _cl2081_h_ -#ifdef __cplusplus -extern "C" { -#endif +#pragma once -#include "nvtypes.h" +#include -#define NV2081_BINAPI (0x00002081) +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl2081.finn +// -typedef struct{ - NvU32 reserved; -}NV2081_ALLOC_PARAMETERS; +#define NV2081_BINAPI (0x2081U) /* finn: Evaluated from "NV2081_ALLOC_PARAMETERS_MESSAGE_ID" */ -#ifdef __cplusplus -}; /* extern "C" */ -#endif +#define NV2081_ALLOC_PARAMETERS_MESSAGE_ID (0x2081U) + +typedef struct NV2081_ALLOC_PARAMETERS { + NvU32 reserved; +} NV2081_ALLOC_PARAMETERS; -#endif diff --git a/src/common/sdk/nvidia/inc/class/cl2082.h b/src/common/sdk/nvidia/inc/class/cl2082.h index 8beda618e..0a721f57d 100644 --- a/src/common/sdk/nvidia/inc/class/cl2082.h +++ b/src/common/sdk/nvidia/inc/class/cl2082.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,23 +21,20 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _cl2082_h_ -#define _cl2082_h_ +#pragma once -#ifdef __cplusplus -extern "C" { -#endif +#include -#include "nvtypes.h" +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl2082.finn +// -#define NV2082_BINAPI_PRIVILEGED (0x00002082) +#define NV2082_BINAPI_PRIVILEGED (0x2082U) /* finn: Evaluated from "NV2082_ALLOC_PARAMETERS_MESSAGE_ID" */ -typedef struct{ - NvU32 reserved; -}NV2082_ALLOC_PARAMETERS; +#define NV2082_ALLOC_PARAMETERS_MESSAGE_ID (0x2082U) -#ifdef __cplusplus -}; /* extern "C" */ -#endif +typedef struct NV2082_ALLOC_PARAMETERS { + NvU32 reserved; +} NV2082_ALLOC_PARAMETERS; -#endif diff --git a/src/common/sdk/nvidia/inc/class/cl30f1.h b/src/common/sdk/nvidia/inc/class/cl30f1.h index 2a8e3c97f..b7edbd2ea 100644 --- a/src/common/sdk/nvidia/inc/class/cl30f1.h +++ b/src/common/sdk/nvidia/inc/class/cl30f1.h @@ -33,7 +33,7 @@ #include "cl30f1_notification.h" /* class NV30_GSYNC */ -#define NV30_GSYNC (0x000030F1) +#define NV30_GSYNC (0x30f1U) /* finn: Evaluated from "NV30F1_ALLOC_PARAMETERS_MESSAGE_ID" */ #define NV30F1_GSYNC_CONNECTOR_ONE (0) #define NV30F1_GSYNC_CONNECTOR_TWO (1) diff --git a/src/common/sdk/nvidia/inc/class/cl503b.h b/src/common/sdk/nvidia/inc/class/cl503b.h index 5f63be473..b372f7802 100644 --- a/src/common/sdk/nvidia/inc/class/cl503b.h +++ b/src/common/sdk/nvidia/inc/class/cl503b.h @@ -31,7 +31,7 @@ // Source file: class/cl503b.finn // -#define NV50_P2P (0x0000503b) +#define NV50_P2P (0x503bU) /* finn: Evaluated from "NV503B_ALLOC_PARAMETERS_MESSAGE_ID" */ #define NV503B_FLAGS_P2P_TYPE 0:0 #define NV503B_FLAGS_P2P_TYPE_GPA 0 diff --git a/src/common/sdk/nvidia/inc/class/cl503c.h b/src/common/sdk/nvidia/inc/class/cl503c.h index 9b9bd3e19..7f2896092 100644 --- a/src/common/sdk/nvidia/inc/class/cl503c.h +++ b/src/common/sdk/nvidia/inc/class/cl503c.h @@ -31,7 +31,7 @@ // Source file: class/cl503c.finn // -#define NV50_THIRD_PARTY_P2P (0x0000503c) +#define NV50_THIRD_PARTY_P2P (0x503cU) /* finn: Evaluated from "NV503C_ALLOC_PARAMETERS_MESSAGE_ID" */ /* NvRmAlloc parameters */ #define NV503C_ALLOC_PARAMETERS_MESSAGE_ID (0x503cU) diff --git a/src/common/sdk/nvidia/inc/class/cl5070.h b/src/common/sdk/nvidia/inc/class/cl5070.h index d8a7f2d25..6a265519d 100644 --- a/src/common/sdk/nvidia/inc/class/cl5070.h +++ b/src/common/sdk/nvidia/inc/class/cl5070.h @@ -1,5 +1,6 @@ /* - * Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -31,7 +32,7 @@ #include "cl5070_notification.h" -#define NV50_DISPLAY (0x00005070) +#define NV50_DISPLAY (0x5070U) /* finn: Evaluated from "NV5070_ALLOCATION_PARAMETERS_MESSAGE_ID" */ #define NV5070_ALLOCATION_PARAMETERS_MESSAGE_ID (0x5070U) diff --git a/src/common/sdk/nvidia/inc/class/cl5070_notification.h b/src/common/sdk/nvidia/inc/class/cl5070_notification.h index fd0628aa1..a23107d0e 100644 --- a/src/common/sdk/nvidia/inc/class/cl5070_notification.h +++ b/src/common/sdk/nvidia/inc/class/cl5070_notification.h @@ -1,5 +1,6 @@ /* - * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), diff --git a/src/common/sdk/nvidia/inc/class/cl5080.h b/src/common/sdk/nvidia/inc/class/cl5080.h index c9c8caaa1..cf059456b 100644 --- a/src/common/sdk/nvidia/inc/class/cl5080.h +++ b/src/common/sdk/nvidia/inc/class/cl5080.h @@ -32,7 +32,7 @@ #include "cl5080_notification.h" -#define NV50_DEFERRED_API_CLASS (0x00005080) +#define NV50_DEFERRED_API_CLASS (0x5080U) /* finn: Evaluated from "NV5080_ALLOC_PARAMS_MESSAGE_ID" */ /* NvRmAlloc parameters */ #define NV5080_ALLOC_PARAMS_MESSAGE_ID (0x5080U) diff --git a/src/common/sdk/nvidia/inc/class/cl83de.h b/src/common/sdk/nvidia/inc/class/cl83de.h index 62c507c0d..df67debea 100644 --- a/src/common/sdk/nvidia/inc/class/cl83de.h +++ b/src/common/sdk/nvidia/inc/class/cl83de.h @@ -30,7 +30,7 @@ // Source file: class/cl83de.finn // -#define GT200_DEBUGGER (0x000083de) +#define GT200_DEBUGGER (0x83deU) /* finn: Evaluated from "NV83DE_ALLOC_PARAMETERS_MESSAGE_ID" */ /* * Creating the GT200_DEBUGGER object: @@ -53,3 +53,4 @@ typedef struct NV83DE_ALLOC_PARAMETERS { NvHandle hAppClient; NvHandle hClass3dObject; } NV83DE_ALLOC_PARAMETERS; + diff --git a/src/common/sdk/nvidia/inc/class/cl84a0.h b/src/common/sdk/nvidia/inc/class/cl84a0.h index 599a47b06..1ee51ad76 100644 --- a/src/common/sdk/nvidia/inc/class/cl84a0.h +++ b/src/common/sdk/nvidia/inc/class/cl84a0.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2001-2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,14 +21,16 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _cl84A0_h_ -#define _cl84A0_h_ +#pragma once -#ifdef __cplusplus -extern "C" { -#endif +#include -#include "nvtypes.h" +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl84a0.finn +// + +#include "cl84a0_deprecated.h" /* * Class definitions for creating a memory descriptor from a list of page numbers @@ -40,14 +42,14 @@ extern "C" { */ /* List of system memory physical page numbers */ -#define NV01_MEMORY_LIST_SYSTEM (0x00000081) +#define NV01_MEMORY_LIST_SYSTEM (0x00000081) /* List of frame buffer physical page numbers */ -#define NV01_MEMORY_LIST_FBMEM (0x00000082) +#define NV01_MEMORY_LIST_FBMEM (0x00000082) /* List of page numbers relative to the start of the specified object */ -#define NV01_MEMORY_LIST_OBJECT (0x00000083) +#define NV01_MEMORY_LIST_OBJECT (0x00000083) /* - * List structure of NV01_MEMORY_LIST_* classes + * List structure of NV01_MEMORY_LIST_* classes * * The pageNumber array is variable in length, with pageCount elements, * so the allocated size of the structure must reflect that. @@ -56,103 +58,53 @@ extern "C" { * NV01_MEMORY_LIST_OBJECT when the underlying object is * FBMEM (must be zero for other cases) * - * Nv01MemoryList is deprecated. NV_MEMORY_LIST_ALLOCATION_PARAMS should be used - * instead. - */ -typedef struct Nv01MemoryListRec { - NvHandle hClient; /* client to which object belongs - * (may differ from client creating the mapping). - * May be NV01_NULL_OBJECT, in which case client - * handle is used */ - NvHandle hParent; /* device with which object is associated. - * Must be NV01_NULL_OBJECT if hClient is NV01_NULL_OBJECT. - * Must not be NV01_NULL_OBJECT if hClient is - * not NV01_NULL_OBJECT. */ - NvHandle hObject; /* object to which pages are relative - * (NV01_NULL_OBJECT for NV01_MEMORY_LIST_SYSTEM - * and NV01_MEMORY_LIST_FBMEM) */ - NvHandle hHwResClient;/* client associated with the backdoor vnc surface*/ - NvHandle hHwResDevice;/* device associated to the bacdoor vnc surface*/ - NvHandle hHwResHandle;/* handle to hardware resources allocated to - * backdoor vnc surface*/ - NvU32 pteAdjust; /* offset of data in first page */ - NvU32 type; /* FBMEM: NVOS32_TYPE_* */ - NvU32 flags; /* FBMEM: NVOS32_ALLOC_FLAGS_* */ - NvU32 attr; /* FBMEM: NVOS32_ATTR_* */ - NvU32 attr2; /* FBMEM: NVOS32_ATTR2_* */ - NvU32 height; /* FBMEM: height in pixels */ - NvU32 width; /* FBMEM: width in pixels */ - NvU32 format; /* FBMEM: memory kind */ - NvU32 comprcovg; /* FBMEM: compression coverage */ - NvU32 zcullcovg; /* FBMEM: Z-cull coverage */ - NvU32 pageCount; /* count of elements in pageNumber array */ - NvU32 heapOwner; /* heap owner information from client */ - NvU32 reserved_1; /* reserved: must be 0 */ - NvU64 NV_DECLARE_ALIGNED(guestId,8); - /* ID of the guest VM. e.g., domain ID in case of Xen */ - NvU64 NV_DECLARE_ALIGNED(rangeBegin,8); - /* preferred VA range start address */ - NvU64 NV_DECLARE_ALIGNED(rangeEnd,8); - /* preferred VA range end address */ - NvU32 pitch; - NvU32 ctagOffset; - NvU64 size; - NvU64 align; - NvU64 pageNumber[1]; /* variable length array of page numbers */ -} Nv01MemoryList; - -/* * NV_MEMORY_LIST_ALLOCATION_PARAMS - Allocation params to create memory list * through NvRmAlloc. */ -typedef struct -{ - NvHandle hClient; /* client to which object belongs - * (may differ from client creating the mapping). - * May be NV01_NULL_OBJECT, in which case client - * handle is used */ - NvHandle hParent; /* device with which object is associated. - * Must be NV01_NULL_OBJECT if hClient is NV01_NULL_OBJECT. - * Must not be NV01_NULL_OBJECT if hClient is - * not NV01_NULL_OBJECT. */ - NvHandle hObject; /* object to which pages are relative - * (NV01_NULL_OBJECT for NV01_MEMORY_LIST_SYSTEM - * and NV01_MEMORY_LIST_FBMEM) */ - NvHandle hHwResClient;/* client associated with the backdoor vnc surface*/ - NvHandle hHwResDevice;/* device associated to the bacdoor vnc surface*/ - NvHandle hHwResHandle;/* handle to hardware resources allocated to - * backdoor vnc surface*/ - NvU32 pteAdjust; /* offset of data in first page */ - NvU32 reserved_0; /* reserved: must be 0 */ - NvU32 type; /* FBMEM: NVOS32_TYPE_* */ - NvU32 flags; /* FBMEM: NVOS32_ALLOC_FLAGS_* */ - NvU32 attr; /* FBMEM: NVOS32_ATTR_* */ - NvU32 attr2; /* FBMEM: NVOS32_ATTR2_* */ - NvU32 height; /* FBMEM: height in pixels */ - NvU32 width; /* FBMEM: width in pixels */ - NvU32 format; /* FBMEM: memory kind */ - NvU32 comprcovg; /* FBMEM: compression coverage */ - NvU32 zcullcovg; /* FBMEM: Z-cull coverage */ - NvU32 pageCount; /* count of elements in pageNumber array */ - NvU32 heapOwner; /* heap owner information from client */ +#define NV_MEMORY_LIST_ALLOCATION_PARAMS_MESSAGE_ID (0x84a0U) - NvU64 NV_DECLARE_ALIGNED(guestId,8); - /* ID of the guest VM. e.g., domain ID in case of Xen */ - NvU64 NV_DECLARE_ALIGNED(rangeBegin,8); - /* preferred VA range start address */ - NvU64 NV_DECLARE_ALIGNED(rangeEnd,8); - /* preferred VA range end address */ - NvU32 pitch; - NvU32 ctagOffset; - NvU64 size; - NvU64 align; - NvP64 pageNumberList NV_ALIGN_BYTES(8); - NvU64 limit NV_ALIGN_BYTES(8); - NvU32 flagsOs02; +typedef struct NV_MEMORY_LIST_ALLOCATION_PARAMS { + NvHandle hClient; /* client to which object belongs + * (may differ from client creating the mapping). + * May be NV01_NULL_OBJECT, in which case client + * handle is used */ + NvHandle hParent; /* device with which object is associated. + * Must be NV01_NULL_OBJECT if hClient is NV01_NULL_OBJECT. + * Must not be NV01_NULL_OBJECT if hClient is + * not NV01_NULL_OBJECT. */ + NvHandle hObject; /* object to which pages are relative + * (NV01_NULL_OBJECT for NV01_MEMORY_LIST_SYSTEM + * and NV01_MEMORY_LIST_FBMEM) */ + NvHandle hHwResClient; /* client associated with the backdoor vnc surface*/ + NvHandle hHwResDevice; /* device associated to the bacdoor vnc surface*/ + NvHandle hHwResHandle; /* handle to hardware resources allocated to + * backdoor vnc surface*/ + NvU32 pteAdjust; /* offset of data in first page */ + NvU32 reserved_0; /* reserved: must be 0 */ + NvU32 type; /* FBMEM: NVOS32_TYPE_* */ + NvU32 flags; /* FBMEM: NVOS32_ALLOC_FLAGS_* */ + NvU32 attr; /* FBMEM: NVOS32_ATTR_* */ + NvU32 attr2; /* FBMEM: NVOS32_ATTR2_* */ + NvU32 height; /* FBMEM: height in pixels */ + NvU32 width; /* FBMEM: width in pixels */ + NvU32 format; /* FBMEM: memory kind */ + NvU32 comprcovg; /* FBMEM: compression coverage */ + NvU32 zcullcovg; /* FBMEM: Z-cull coverage */ + NvU32 pageCount; /* count of elements in pageNumber array */ + NvU32 heapOwner; /* heap owner information from client */ + + NV_DECLARE_ALIGNED(NvU64 guestId, 8); + /* ID of the guest VM. e.g., domain ID in case of Xen */ + NV_DECLARE_ALIGNED(NvU64 rangeBegin, 8); + /* preferred VA range start address */ + NV_DECLARE_ALIGNED(NvU64 rangeEnd, 8); + /* preferred VA range end address */ + NvU32 pitch; + NvU32 ctagOffset; + NV_DECLARE_ALIGNED(NvU64 size, 8); + NV_DECLARE_ALIGNED(NvU64 align, 8); + NV_DECLARE_ALIGNED(NvP64 pageNumberList, 8); + NV_DECLARE_ALIGNED(NvU64 limit, 8); + NvU32 flagsOs02; } NV_MEMORY_LIST_ALLOCATION_PARAMS; -#ifdef __cplusplus -}; /* extern "C" */ -#endif - -#endif /* _cl84A0_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/cl84a0_deprecated.h b/src/common/sdk/nvidia/inc/class/cl84a0_deprecated.h new file mode 100644 index 000000000..f1e7f0c57 --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/cl84a0_deprecated.h @@ -0,0 +1,90 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl84a0_deprecated_h_ +#define _cl84a0_deprecated_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * List structure of NV01_MEMORY_LIST_* classes + * + * The pageNumber array is variable in length, with pageCount elements, + * so the allocated size of the structure must reflect that. + * + * FBMEM items apply only to NV01_MEMORY_LIST_FBMEM and to + * NV01_MEMORY_LIST_OBJECT when the underlying object is + * FBMEM (must be zero for other cases) + * + * Nv01MemoryList is deprecated. NV_MEMORY_LIST_ALLOCATION_PARAMS should be used + * instead. + */ +typedef struct Nv01MemoryListRec { + NvHandle hClient; /* client to which object belongs + * (may differ from client creating the mapping). + * May be NV01_NULL_OBJECT, in which case client + * handle is used */ + NvHandle hParent; /* device with which object is associated. + * Must be NV01_NULL_OBJECT if hClient is NV01_NULL_OBJECT. + * Must not be NV01_NULL_OBJECT if hClient is + * not NV01_NULL_OBJECT. */ + NvHandle hObject; /* object to which pages are relative + * (NV01_NULL_OBJECT for NV01_MEMORY_LIST_SYSTEM + * and NV01_MEMORY_LIST_FBMEM) */ + NvHandle hHwResClient;/* client associated with the backdoor vnc surface*/ + NvHandle hHwResDevice;/* device associated to the bacdoor vnc surface*/ + NvHandle hHwResHandle;/* handle to hardware resources allocated to + * backdoor vnc surface*/ + NvU32 pteAdjust; /* offset of data in first page */ + NvU32 type; /* FBMEM: NVOS32_TYPE_* */ + NvU32 flags; /* FBMEM: NVOS32_ALLOC_FLAGS_* */ + NvU32 attr; /* FBMEM: NVOS32_ATTR_* */ + NvU32 attr2; /* FBMEM: NVOS32_ATTR2_* */ + NvU32 height; /* FBMEM: height in pixels */ + NvU32 width; /* FBMEM: width in pixels */ + NvU32 format; /* FBMEM: memory kind */ + NvU32 comprcovg; /* FBMEM: compression coverage */ + NvU32 zcullcovg; /* FBMEM: Z-cull coverage */ + NvU32 pageCount; /* count of elements in pageNumber array */ + NvU32 heapOwner; /* heap owner information from client */ + NvU32 reserved_1; /* reserved: must be 0 */ + NvU64 NV_DECLARE_ALIGNED(guestId,8); + /* ID of the guest VM. e.g., domain ID in case of Xen */ + NvU64 NV_DECLARE_ALIGNED(rangeBegin,8); + /* preferred VA range start address */ + NvU64 NV_DECLARE_ALIGNED(rangeEnd,8); + /* preferred VA range end address */ + NvU32 pitch; + NvU32 ctagOffset; + NvU64 size; + NvU64 align; + NvU64 pageNumber[1]; /* variable length array of page numbers */ +} Nv01MemoryList; + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cl84a0_deprecated_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/cl9010.h b/src/common/sdk/nvidia/inc/class/cl9010.h index 1ec334b6b..722277b89 100644 --- a/src/common/sdk/nvidia/inc/class/cl9010.h +++ b/src/common/sdk/nvidia/inc/class/cl9010.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -19,21 +19,27 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ -#ifndef SDK_CL9010_H -#define SDK_CL9010_H -#include "nvtypes.h" +#pragma once -#define NV9010_VBLANK_CALLBACK 0x9010 +#include -typedef void (*OSVBLANKCALLBACKPROC)(void * pParm1, void * pParm2); +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl9010.finn +// -typedef struct -{ - OSVBLANKCALLBACKPROC pProc; // Routine to call at vblank time - NvV32 LogicalHead; // Logical Head - void *pParm1; // pParm1 - void *pParm2; // pParm2 +#include "class/cl9010_callback.h" + +#define NV9010_VBLANK_CALLBACK (0x9010U) /* finn: Evaluated from "NV_VBLANK_CALLBACK_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV_VBLANK_CALLBACK_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9010U) + +typedef struct NV_VBLANK_CALLBACK_ALLOCATION_PARAMETERS { + NV_DECLARE_ALIGNED(NvP64 pProc, 8); // Routine to call at vblank time + // A function pointer of OSVBLANKCALLBACKPROC + NvV32 LogicalHead; // Logical Head + NV_DECLARE_ALIGNED(NvP64 pParm1, 8); // pParm1 + NV_DECLARE_ALIGNED(NvP64 pParm2, 8); // pParm2 } NV_VBLANK_CALLBACK_ALLOCATION_PARAMETERS; -#endif // SDK_CL9010_H diff --git a/src/common/sdk/nvidia/inc/class/cl9010_callback.h b/src/common/sdk/nvidia/inc/class/cl9010_callback.h new file mode 100644 index 000000000..1945b686b --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/cl9010_callback.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef SDK_CL9010_CALLBACK_H +#define SDK_CL9010_CALLBACK_H + +typedef void (*OSVBLANKCALLBACKPROC)(NvP64 pParm1, NvP64 pParm2); + +#endif // SDK_CL9010_CALLBACK_H diff --git a/src/common/sdk/nvidia/inc/class/cl9072.h b/src/common/sdk/nvidia/inc/class/cl9072.h index fe3d91b86..61e134abb 100644 --- a/src/common/sdk/nvidia/inc/class/cl9072.h +++ b/src/common/sdk/nvidia/inc/class/cl9072.h @@ -32,7 +32,7 @@ #include "cl9072_notification.h" -#define GF100_DISP_SW 0x00009072 +#define GF100_DISP_SW (0x9072U) /* finn: Evaluated from "NV9072_ALLOCATION_PARAMETERS_MESSAGE_ID" */ #define NV9072_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9072U) diff --git a/src/common/sdk/nvidia/inc/class/cl9097.h b/src/common/sdk/nvidia/inc/class/cl9097.h new file mode 100644 index 000000000..8bc77927c --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/cl9097.h @@ -0,0 +1,3815 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_fermi_a_h_ +#define _cl_fermi_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../class/bin/sw_header.pl fermi_a */ + +#include "nvtypes.h" + +#define FERMI_A 0x9097 + +#define NV9097_SET_OBJECT 0x0000 +#define NV9097_SET_OBJECT_CLASS_ID 15:0 +#define NV9097_SET_OBJECT_ENGINE_ID 20:16 + +#define NV9097_NO_OPERATION 0x0100 +#define NV9097_NO_OPERATION_V 31:0 + +#define NV9097_SET_NOTIFY_A 0x0104 +#define NV9097_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NV9097_SET_NOTIFY_B 0x0108 +#define NV9097_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NV9097_NOTIFY 0x010c +#define NV9097_NOTIFY_TYPE 31:0 +#define NV9097_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NV9097_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NV9097_WAIT_FOR_IDLE 0x0110 +#define NV9097_WAIT_FOR_IDLE_V 31:0 + +#define NV9097_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NV9097_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NV9097_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NV9097_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NV9097_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NV9097_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NV9097_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NV9097_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NV9097_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NV9097_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NV9097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NV9097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NV9097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NV9097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NV9097_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NV9097_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NV9097_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NV9097_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NV9097_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NV9097_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NV9097_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NV9097_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NV9097_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NV9097_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NV9097_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NV9097_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NV9097_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NV9097_SEND_GO_IDLE 0x013c +#define NV9097_SEND_GO_IDLE_V 31:0 + +#define NV9097_PM_TRIGGER 0x0140 +#define NV9097_PM_TRIGGER_V 31:0 + +#define NV9097_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NV9097_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NV9097_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NV9097_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NV9097_RUN_DS_NOW 0x0200 +#define NV9097_RUN_DS_NOW_V 31:0 + +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NV9097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NV9097_SET_RASTER_PIPE_SYNC_CONTROL 0x0208 +#define NV9097_SET_RASTER_PIPE_SYNC_CONTROL_PRIM_AREA_THRESHOLD 21:0 +#define NV9097_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE 24:24 +#define NV9097_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE_FALSE 0x00000000 +#define NV9097_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NV9097_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NV9097_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NV9097_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NV9097_SET_API_MANDATED_EARLY_Z 0x0210 +#define NV9097_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NV9097_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NV9097_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_GS_DM_FIFO 0x0214 +#define NV9097_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NV9097_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NV9097_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NV9097_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NV9097_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NV9097_INVALIDATE_SHADER_CACHES 0x021c +#define NV9097_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NV9097_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NV9097_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NV9097_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NV9097_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NV9097_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NV9097_INVALIDATE_SHADER_CACHES_UNIFORM 8:8 +#define NV9097_INVALIDATE_SHADER_CACHES_UNIFORM_FALSE 0x00000000 +#define NV9097_INVALIDATE_SHADER_CACHES_UNIFORM_TRUE 0x00000001 +#define NV9097_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NV9097_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NV9097_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NV9097_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NV9097_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NV9097_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NV9097_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NV9097_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NV9097_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NV9097_SET_VAB_VERTEX3F(i) (0x0220+(i)*4) +#define NV9097_SET_VAB_VERTEX3F_V 31:0 + +#define NV9097_SET_VAB_VERTEX4F(i) (0x0230+(i)*4) +#define NV9097_SET_VAB_VERTEX4F_V 31:0 + +#define NV9097_SET_VAB_NORMAL3F(i) (0x0240+(i)*4) +#define NV9097_SET_VAB_NORMAL3F_V 31:0 + +#define NV9097_SET_VAB_COLOR3F(i) (0x0250+(i)*4) +#define NV9097_SET_VAB_COLOR3F_V 31:0 + +#define NV9097_SET_VAB_COLOR4F(i) (0x0260+(i)*4) +#define NV9097_SET_VAB_COLOR4F_V 31:0 + +#define NV9097_SET_VAB_COLOR4UB(i) (0x0270+(i)*4) +#define NV9097_SET_VAB_COLOR4UB_V 31:0 + +#define NV9097_SET_VAB_TEX_COORD1F(i) (0x0280+(i)*4) +#define NV9097_SET_VAB_TEX_COORD1F_V 31:0 + +#define NV9097_SET_VAB_TEX_COORD2F(i) (0x0290+(i)*4) +#define NV9097_SET_VAB_TEX_COORD2F_V 31:0 + +#define NV9097_SET_VAB_TEX_COORD3F(i) (0x02a0+(i)*4) +#define NV9097_SET_VAB_TEX_COORD3F_V 31:0 + +#define NV9097_SET_VAB_TEX_COORD4F(i) (0x02b0+(i)*4) +#define NV9097_SET_VAB_TEX_COORD4F_V 31:0 + +#define NV9097_SET_GA_TO_VA_MAPPING_MODE 0x02c4 +#define NV9097_SET_GA_TO_VA_MAPPING_MODE_V 0:0 +#define NV9097_SET_GA_TO_VA_MAPPING_MODE_V_DISABLE 0x00000000 +#define NV9097_SET_GA_TO_VA_MAPPING_MODE_V_ENABLE 0x00000001 + +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY 0x02c8 +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY_VIRTUAL_ADDRESS_UPPER 7:0 +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY_GENERIC_ADDRESS_UPPER 23:16 +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE 30:30 +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE_FALSE 0x00000000 +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE_TRUE 0x00000001 +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE 31:31 +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE_FALSE 0x00000000 +#define NV9097_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_TASK_CIRCULAR_BUFFER_THROTTLE 0x02cc +#define NV9097_SET_TASK_CIRCULAR_BUFFER_THROTTLE_TASK_COUNT 21:0 + +#define NV9097_SET_PRIM_CIRCULAR_BUFFER_THROTTLE 0x02d0 +#define NV9097_SET_PRIM_CIRCULAR_BUFFER_THROTTLE_PRIM_AREA 21:0 + +#define NV9097_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NV9097_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NV9097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NV9097_SET_RASTER_BOUNDING_BOX 0x02ec +#define NV9097_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NV9097_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NV9097_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NV9097_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NV9097_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NV9097_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NV9097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NV9097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NV9097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NV9097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NV9097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NV9097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NV9097_DRAW_ZERO_INDEX 0x0304 +#define NV9097_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NV9097_SET_L1_CONFIGURATION 0x0308 +#define NV9097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NV9097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NV9097_SET_RENDER_ENABLE_CONTROL 0x030c +#define NV9097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NV9097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NV9097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NV9097_X_X_X_SET_CT_ENABLE 0x0310 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET0 0:0 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET0_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET0_TRUE 0x00000001 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET1 1:1 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET1_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET1_TRUE 0x00000001 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET2 2:2 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET2_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET2_TRUE 0x00000001 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET3 3:3 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET3_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET3_TRUE 0x00000001 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET4 4:4 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET4_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET4_TRUE 0x00000001 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET5 5:5 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET5_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET5_TRUE 0x00000001 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET6 6:6 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET6_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET6_TRUE 0x00000001 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET7 7:7 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET7_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CT_ENABLE_TARGET7_TRUE 0x00000001 + +#define NV9097_SET_IEEE_CLEAN_UPDATE 0x0314 +#define NV9097_SET_IEEE_CLEAN_UPDATE_ENABLE 0:0 +#define NV9097_SET_IEEE_CLEAN_UPDATE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_IEEE_CLEAN_UPDATE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_SNAP_GRID_LINE 0x0318 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NV9097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NV9097_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NV9097_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NV9097_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NV9097_SET_SNAP_GRID_NON_LINE 0x031c +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NV9097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NV9097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NV9097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NV9097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NV9097_SET_TESSELLATION_PARAMETERS 0x0320 +#define NV9097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NV9097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NV9097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NV9097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NV9097_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NV9097_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NV9097_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NV9097_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NV9097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NV9097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NV9097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NV9097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NV9097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NV9097_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NV9097_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NV9097_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NV9097_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NV9097_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NV9097_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NV9097_SET_TESSELLATION_LOD_V1 0x0330 +#define NV9097_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NV9097_SET_TG_LOD_INTERIOR_U 0x0334 +#define NV9097_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NV9097_SET_TG_LOD_INTERIOR_V 0x0338 +#define NV9097_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NV9097_RESERVED_TG07 0x033c +#define NV9097_RESERVED_TG07_V 0:0 + +#define NV9097_RESERVED_TG08 0x0340 +#define NV9097_RESERVED_TG08_V 0:0 + +#define NV9097_RESERVED_TG09 0x0344 +#define NV9097_RESERVED_TG09_V 0:0 + +#define NV9097_RESERVED_TG10 0x0348 +#define NV9097_RESERVED_TG10_V 0:0 + +#define NV9097_RESERVED_TG11 0x034c +#define NV9097_RESERVED_TG11_V 0:0 + +#define NV9097_RESERVED_TG12 0x0350 +#define NV9097_RESERVED_TG12_V 0:0 + +#define NV9097_RESERVED_TG13 0x0354 +#define NV9097_RESERVED_TG13_V 0:0 + +#define NV9097_RESERVED_TG14 0x0358 +#define NV9097_RESERVED_TG14_V 0:0 + +#define NV9097_RESERVED_TG15 0x035c +#define NV9097_RESERVED_TG15_V 0:0 + +#define NV9097_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NV9097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NV9097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NV9097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NV9097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NV9097_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NV9097_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NV9097_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NV9097_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NV9097_SET_RASTER_ENABLE 0x037c +#define NV9097_SET_RASTER_ENABLE_V 0:0 +#define NV9097_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NV9097_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NV9097_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NV9097_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NV9097_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NV9097_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NV9097_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NV9097_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NV9097_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NV9097_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NV9097_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NV9097_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NV9097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NV9097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NV9097_SET_VAB_DATA_TYPELESS(i) (0x0400+(i)*4) +#define NV9097_SET_VAB_DATA_TYPELESS_V 31:0 + +#define NV9097_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NV9097_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NV9097_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NV9097_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NV9097_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NV9097_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NV9097_SET_RASTER_INPUT 0x0740 +#define NV9097_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NV9097_SET_STREAM_OUTPUT 0x0744 +#define NV9097_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NV9097_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NV9097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NV9097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_ALPHA_FRACTION 0x074c +#define NV9097_SET_ALPHA_FRACTION_V 7:0 + +#define NV9097_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NV9097_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NV9097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NV9097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NV9097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 + +#define NV9097_SET_MAX_TI_WARPS_PER_BATCH 0x075c +#define NV9097_SET_MAX_TI_WARPS_PER_BATCH_V 5:0 + +#define NV9097_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NV9097_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NV9097_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NV9097_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NV9097_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NV9097_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NV9097_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NV9097_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NV9097_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NV9097_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NV9097_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NV9097_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NV9097_SET_VAB_VERTEX2F(i) (0x07b0+(i)*4) +#define NV9097_SET_VAB_VERTEX2F_V 31:0 + +#define NV9097_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NV9097_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NV9097_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NV9097_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NV9097_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NV9097_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NV9097_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NV9097_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NV9097_SET_CULL_BEFORE_FETCH 0x07dc +#define NV9097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NV9097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NV9097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NV9097_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NV9097_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NV9097_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NV9097_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NV9097_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NV9097_SET_ZCULL_STORAGE_A 0x07e8 +#define NV9097_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NV9097_SET_ZCULL_STORAGE_B 0x07ec +#define NV9097_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NV9097_SET_ZCULL_STORAGE_C 0x07f0 +#define NV9097_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NV9097_SET_ZCULL_STORAGE_D 0x07f4 +#define NV9097_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NV9097_SET_ZT_READ_ONLY 0x07f8 +#define NV9097_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NV9097_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NV9097_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NV9097_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NV9097_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NV9097_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NV9097_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NV9097_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NV9097_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NV9097_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NV9097_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NV9097_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NV9097_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NV9097_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NV9097_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NV9097_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NV9097_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NV9097_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NV9097_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NV9097_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NV9097_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NV9097_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NV9097_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NV9097_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NV9097_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 + +#define NV9097_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NV9097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NV9097_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NV9097_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NV9097_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NV9097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NV9097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NV9097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NV9097_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NV9097_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NV9097_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NV9097_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NV9097_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NV9097_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NV9097_SET_COLOR_TARGET_MARK(j) (0x0824+(j)*64) +#define NV9097_SET_COLOR_TARGET_MARK_IEEE_CLEAN 0:0 +#define NV9097_SET_COLOR_TARGET_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NV9097_SET_COLOR_TARGET_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NV9097_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NV9097_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NV9097_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NV9097_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NV9097_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NV9097_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NV9097_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NV9097_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NV9097_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NV9097_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NV9097_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NV9097_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NV9097_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NV9097_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NV9097_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NV9097_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NV9097_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NV9097_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NV9097_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NV9097_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NV9097_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NV9097_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NV9097_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NV9097_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NV9097_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NV9097_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NV9097_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NV9097_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NV9097_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NV9097_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NV9097_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NV9097_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NV9097_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NV9097_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NV9097_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NV9097_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NV9097_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NV9097_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NV9097_SET_STATISTICS_COUNTER 0x0d68 +#define NV9097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NV9097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NV9097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NV9097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NV9097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NV9097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NV9097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NV9097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NV9097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NV9097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NV9097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NV9097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NV9097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NV9097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NV9097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NV9097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NV9097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NV9097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NV9097_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NV9097_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NV9097_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NV9097_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NV9097_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NV9097_SET_VERTEX_ARRAY_START 0x0d74 +#define NV9097_SET_VERTEX_ARRAY_START_V 31:0 + +#define NV9097_DRAW_VERTEX_ARRAY 0x0d78 +#define NV9097_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NV9097_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NV9097_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NV9097_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NV9097_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NV9097_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NV9097_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NV9097_SET_Z_CLEAR_VALUE 0x0d90 +#define NV9097_SET_Z_CLEAR_VALUE_V 31:0 + +#define NV9097_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NV9097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NV9097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NV9097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NV9097_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NV9097_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NV9097_SET_FRONT_POLYGON_MODE 0x0dac +#define NV9097_SET_FRONT_POLYGON_MODE_V 31:0 +#define NV9097_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NV9097_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NV9097_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NV9097_SET_BACK_POLYGON_MODE 0x0db0 +#define NV9097_SET_BACK_POLYGON_MODE_V 31:0 +#define NV9097_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NV9097_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NV9097_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NV9097_SET_POLY_SMOOTH 0x0db4 +#define NV9097_SET_POLY_SMOOTH_ENABLE 0:0 +#define NV9097_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NV9097_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_ZT_MARK 0x0db8 +#define NV9097_SET_ZT_MARK_IEEE_CLEAN 0:0 +#define NV9097_SET_ZT_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NV9097_SET_ZT_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NV9097_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NV9097_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NV9097_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NV9097_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NV9097_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NV9097_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NV9097_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NV9097_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NV9097_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NV9097_SET_POLY_OFFSET_POINT 0x0dc0 +#define NV9097_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NV9097_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_POLY_OFFSET_LINE 0x0dc4 +#define NV9097_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NV9097_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_POLY_OFFSET_FILL 0x0dc8 +#define NV9097_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NV9097_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NV9097_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_PATCH 0x0dcc +#define NV9097_SET_PATCH_SIZE 7:0 + +#define NV9097_SET_ZCULL_CRITERION 0x0dd8 +#define NV9097_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NV9097_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NV9097_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NV9097_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NV9097_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NV9097_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NV9097_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NV9097_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NV9097_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NV9097_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NV9097_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NV9097_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NV9097_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NV9097_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NV9097_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NV9097_SET_ZCULL_CRITERION_SREF 23:16 +#define NV9097_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NV9097_X_X_X_SET_DA_ATTRIBUTE_CACHE_LINE 0x0ddc +#define NV9097_X_X_X_SET_DA_ATTRIBUTE_CACHE_LINE_V 1:0 +#define NV9097_X_X_X_SET_DA_ATTRIBUTE_CACHE_LINE_V_SIZE128 0x00000000 +#define NV9097_X_X_X_SET_DA_ATTRIBUTE_CACHE_LINE_V_SIZE64 0x00000001 +#define NV9097_X_X_X_SET_DA_ATTRIBUTE_CACHE_LINE_V_SIZE32 0x00000002 + +#define NV9097_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NV9097_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NV9097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NV9097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NV9097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NV9097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_DRAW_INLINE_VERTEX_VAB_UPDATE 0x0dec +#define NV9097_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE 0:0 +#define NV9097_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE_TRUE 0x00000001 + +#define NV9097_X_X_X_SET_REDUCE_COLOR 0x0df4 +#define NV9097_X_X_X_SET_REDUCE_COLOR_U8_THRESHOLD 7:0 +#define NV9097_X_X_X_SET_REDUCE_COLOR_FP16_THRESHOLD 23:8 + +#define NV9097_SET_WINDOW_OFFSET_X 0x0df8 +#define NV9097_SET_WINDOW_OFFSET_X_V 16:0 + +#define NV9097_SET_WINDOW_OFFSET_Y 0x0dfc +#define NV9097_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NV9097_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NV9097_SET_SCISSOR_ENABLE_V 0:0 +#define NV9097_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NV9097_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NV9097_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NV9097_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NV9097_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NV9097_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NV9097_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NV9097_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NV9097_SET_VAB_NORMAL3S(i) (0x0f00+(i)*4) +#define NV9097_SET_VAB_NORMAL3S_V 31:0 + +#define NV9097_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NV9097_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NV9097_SET_BACK_STENCIL_MASK 0x0f58 +#define NV9097_SET_BACK_STENCIL_MASK_V 7:0 + +#define NV9097_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NV9097_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NV9097_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NV9097_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NV9097_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NV9097_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NV9097_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NV9097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NV9097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NV9097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NV9097_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NV9097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NV9097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NV9097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NV9097_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NV9097_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NV9097_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NV9097_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NV9097_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NV9097_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NV9097_SET_CT_MRT_ENABLE 0x0fac +#define NV9097_SET_CT_MRT_ENABLE_V 0:0 +#define NV9097_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NV9097_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NV9097_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NV9097_SET_NONMULTISAMPLED_Z_V 0:0 +#define NV9097_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NV9097_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NV9097_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NV9097_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NV9097_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NV9097_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NV9097_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NV9097_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NV9097_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NV9097_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NV9097_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NV9097_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NV9097_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_BLEND_OPT_CONTROL 0x0fdc +#define NV9097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NV9097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NV9097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NV9097_SET_ZT_A 0x0fe0 +#define NV9097_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_ZT_B 0x0fe4 +#define NV9097_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_ZT_FORMAT 0x0fe8 +#define NV9097_SET_ZT_FORMAT_V 4:0 +#define NV9097_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NV9097_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NV9097_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NV9097_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NV9097_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NV9097_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NV9097_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NV9097_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NV9097_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NV9097_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NV9097_SET_ZT_BLOCK_SIZE 0x0fec +#define NV9097_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NV9097_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NV9097_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NV9097_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV9097_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV9097_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV9097_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV9097_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV9097_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NV9097_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NV9097_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NV9097_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NV9097_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NV9097_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NV9097_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NV9097_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NV9097_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NV9097_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NV9097_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NV9097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NV9097_SET_FORCE_ONE_TEXTURE_UNIT 0x1004 +#define NV9097_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE 0:0 +#define NV9097_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NV9097_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NV9097_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NV9097_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NV9097_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NV9097_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NV9097_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NV9097_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NV9097_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NV9097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NV9097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NV9097_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NV9097_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NV9097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NV9097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_SPARE_NOOP00 0x1040 +#define NV9097_SET_SPARE_NOOP00_V 31:0 + +#define NV9097_SET_SPARE_NOOP01 0x1044 +#define NV9097_SET_SPARE_NOOP01_V 31:0 + +#define NV9097_SET_SPARE_NOOP02 0x1048 +#define NV9097_SET_SPARE_NOOP02_V 31:0 + +#define NV9097_SET_SPARE_NOOP03 0x104c +#define NV9097_SET_SPARE_NOOP03_V 31:0 + +#define NV9097_SET_SPARE_NOOP04 0x1050 +#define NV9097_SET_SPARE_NOOP04_V 31:0 + +#define NV9097_SET_SPARE_NOOP05 0x1054 +#define NV9097_SET_SPARE_NOOP05_V 31:0 + +#define NV9097_SET_SPARE_NOOP06 0x1058 +#define NV9097_SET_SPARE_NOOP06_V 31:0 + +#define NV9097_SET_SPARE_NOOP07 0x105c +#define NV9097_SET_SPARE_NOOP07_V 31:0 + +#define NV9097_SET_SPARE_NOOP08 0x1060 +#define NV9097_SET_SPARE_NOOP08_V 31:0 + +#define NV9097_SET_SPARE_NOOP09 0x1064 +#define NV9097_SET_SPARE_NOOP09_V 31:0 + +#define NV9097_SET_SPARE_NOOP10 0x1068 +#define NV9097_SET_SPARE_NOOP10_V 31:0 + +#define NV9097_SET_SPARE_NOOP11 0x106c +#define NV9097_SET_SPARE_NOOP11_V 31:0 + +#define NV9097_SET_SPARE_NOOP12 0x1070 +#define NV9097_SET_SPARE_NOOP12_V 31:0 + +#define NV9097_SET_SPARE_NOOP13 0x1074 +#define NV9097_SET_SPARE_NOOP13_V 31:0 + +#define NV9097_SET_SPARE_NOOP14 0x1078 +#define NV9097_SET_SPARE_NOOP14_V 31:0 + +#define NV9097_SET_SPARE_NOOP15 0x107c +#define NV9097_SET_SPARE_NOOP15_V 31:0 + +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NV9097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NV9097_UNBIND_ALL 0x10f4 +#define NV9097_UNBIND_ALL_TEXTURE_HEADERS 0:0 +#define NV9097_UNBIND_ALL_TEXTURE_HEADERS_FALSE 0x00000000 +#define NV9097_UNBIND_ALL_TEXTURE_HEADERS_TRUE 0x00000001 +#define NV9097_UNBIND_ALL_TEXTURE_SAMPLERS 4:4 +#define NV9097_UNBIND_ALL_TEXTURE_SAMPLERS_FALSE 0x00000000 +#define NV9097_UNBIND_ALL_TEXTURE_SAMPLERS_TRUE 0x00000001 +#define NV9097_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NV9097_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NV9097_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NV9097_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NV9097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NV9097_NO_OPERATION_DATA_HI 0x110c +#define NV9097_NO_OPERATION_DATA_HI_V 31:0 + +#define NV9097_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NV9097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NV9097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NV9097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NV9097_PM_TRIGGER_END 0x1114 +#define NV9097_PM_TRIGGER_END_V 31:0 + +#define NV9097_SET_VERTEX_ID_BASE 0x1118 +#define NV9097_SET_VERTEX_ID_BASE_V 31:0 + +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NV9097_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NV9097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NV9097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NV9097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NV9097_FLUSH_PENDING_WRITES 0x1144 +#define NV9097_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NV9097_SET_VAB_DATA_CONTROL 0x114c +#define NV9097_SET_VAB_DATA_CONTROL_VAB_INDEX 7:0 +#define NV9097_SET_VAB_DATA_CONTROL_COMPONENT_COUNT 10:8 +#define NV9097_SET_VAB_DATA_CONTROL_COMPONENT_BYTE_WIDTH 14:12 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT 18:16 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT_NUM_SNORM 0x00000001 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT_NUM_UNORM 0x00000002 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT_NUM_SINT 0x00000003 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT_NUM_UINT 0x00000004 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT_NUM_USCALED 0x00000005 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT_NUM_SSCALED 0x00000006 +#define NV9097_SET_VAB_DATA_CONTROL_FORMAT_NUM_FLOAT 0x00000007 + +#define NV9097_SET_VAB_DATA(i) (0x1150+(i)*4) +#define NV9097_SET_VAB_DATA_V 31:0 + +#define NV9097_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NV9097_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NV9097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NV9097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NV9097_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NV9097_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NV9097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NV9097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NV9097_SET_CT_SELECT 0x121c +#define NV9097_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NV9097_SET_CT_SELECT_TARGET0 6:4 +#define NV9097_SET_CT_SELECT_TARGET1 9:7 +#define NV9097_SET_CT_SELECT_TARGET2 12:10 +#define NV9097_SET_CT_SELECT_TARGET3 15:13 +#define NV9097_SET_CT_SELECT_TARGET4 18:16 +#define NV9097_SET_CT_SELECT_TARGET5 21:19 +#define NV9097_SET_CT_SELECT_TARGET6 24:22 +#define NV9097_SET_CT_SELECT_TARGET7 27:25 + +#define NV9097_SET_COMPRESSION_THRESHOLD 0x1220 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NV9097_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NV9097_SET_ZT_SIZE_A 0x1228 +#define NV9097_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NV9097_SET_ZT_SIZE_B 0x122c +#define NV9097_SET_ZT_SIZE_B_HEIGHT 16:0 + +#define NV9097_SET_ZT_SIZE_C 0x1230 +#define NV9097_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NV9097_SET_ZT_SIZE_C_CONTROL 16:16 +#define NV9097_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NV9097_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NV9097_SET_SAMPLER_BINDING 0x1234 +#define NV9097_SET_SAMPLER_BINDING_V 0:0 +#define NV9097_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NV9097_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NV9097_DRAW_AUTO 0x123c +#define NV9097_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NV9097_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NV9097_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 9:0 + +#define NV9097_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NV9097_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NV9097_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NV9097_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NV9097_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NV9097_SET_SHADER_SCHEDULING 0x12ac +#define NV9097_SET_SHADER_SCHEDULING_MODE 0:0 +#define NV9097_SET_SHADER_SCHEDULING_MODE_OLDEST_THREAD_FIRST 0x00000000 +#define NV9097_SET_SHADER_SCHEDULING_MODE_ROUND_ROBIN 0x00000001 + +#define NV9097_CLEAR_ZCULL_REGION 0x12c8 +#define NV9097_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NV9097_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NV9097_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NV9097_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NV9097_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NV9097_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NV9097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NV9097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NV9097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NV9097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NV9097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NV9097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NV9097_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NV9097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NV9097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NV9097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NV9097_SET_DEPTH_TEST 0x12cc +#define NV9097_SET_DEPTH_TEST_ENABLE 0:0 +#define NV9097_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NV9097_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_FILL_MODE 0x12d0 +#define NV9097_SET_FILL_MODE_V 31:0 +#define NV9097_SET_FILL_MODE_V_POINT 0x00000001 +#define NV9097_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NV9097_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NV9097_SET_SHADE_MODE 0x12d4 +#define NV9097_SET_SHADE_MODE_V 31:0 +#define NV9097_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NV9097_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NV9097_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NV9097_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NV9097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NV9097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NV9097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NV9097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NV9097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NV9097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NV9097_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NV9097_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NV9097_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NV9097_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_DEPTH_WRITE 0x12e8 +#define NV9097_SET_DEPTH_WRITE_ENABLE 0:0 +#define NV9097_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_ALPHA_TEST 0x12ec +#define NV9097_SET_ALPHA_TEST_ENABLE 0:0 +#define NV9097_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NV9097_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NV9097_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NV9097_DRAW_INLINE_INDEX4X8 0x1304 +#define NV9097_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NV9097_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NV9097_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NV9097_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NV9097_D3D_SET_CULL_MODE 0x1308 +#define NV9097_D3D_SET_CULL_MODE_V 31:0 +#define NV9097_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NV9097_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NV9097_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NV9097_SET_DEPTH_FUNC 0x130c +#define NV9097_SET_DEPTH_FUNC_V 31:0 +#define NV9097_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NV9097_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NV9097_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NV9097_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NV9097_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NV9097_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NV9097_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NV9097_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NV9097_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NV9097_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NV9097_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NV9097_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NV9097_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NV9097_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NV9097_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NV9097_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NV9097_SET_ALPHA_REF 0x1310 +#define NV9097_SET_ALPHA_REF_V 31:0 + +#define NV9097_SET_ALPHA_FUNC 0x1314 +#define NV9097_SET_ALPHA_FUNC_V 31:0 +#define NV9097_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NV9097_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NV9097_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NV9097_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NV9097_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NV9097_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NV9097_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NV9097_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NV9097_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NV9097_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NV9097_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NV9097_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NV9097_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NV9097_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NV9097_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NV9097_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NV9097_SET_DRAW_AUTO_STRIDE 0x1318 +#define NV9097_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NV9097_SET_BLEND_CONST_RED 0x131c +#define NV9097_SET_BLEND_CONST_RED_V 31:0 + +#define NV9097_SET_BLEND_CONST_GREEN 0x1320 +#define NV9097_SET_BLEND_CONST_GREEN_V 31:0 + +#define NV9097_SET_BLEND_CONST_BLUE 0x1324 +#define NV9097_SET_BLEND_CONST_BLUE_V 31:0 + +#define NV9097_SET_BLEND_CONST_ALPHA 0x1328 +#define NV9097_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NV9097_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NV9097_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NV9097_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NV9097_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NV9097_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS 2:1 +#define NV9097_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_ONLY 0x00000000 + +#define NV9097_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NV9097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NV9097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NV9097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_BLEND_COLOR_OP 0x1340 +#define NV9097_SET_BLEND_COLOR_OP_V 31:0 +#define NV9097_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NV9097_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NV9097_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NV9097_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NV9097_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NV9097_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NV9097_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NV9097_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NV9097_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NV9097_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NV9097_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NV9097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NV9097_SET_BLEND_ALPHA_OP 0x134c +#define NV9097_SET_BLEND_ALPHA_OP_V 31:0 +#define NV9097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NV9097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NV9097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NV9097_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NV9097_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NV9097_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NV9097_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NV9097_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NV9097_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NV9097_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NV9097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NV9097_SET_GLOBAL_COLOR_KEY 0x1354 +#define NV9097_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NV9097_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NV9097_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NV9097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NV9097_SET_SINGLE_ROP_CONTROL 0x135c +#define NV9097_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NV9097_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NV9097_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_BLEND(i) (0x1360+(i)*4) +#define NV9097_SET_BLEND_ENABLE 0:0 +#define NV9097_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NV9097_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_STENCIL_TEST 0x1380 +#define NV9097_SET_STENCIL_TEST_ENABLE 0:0 +#define NV9097_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NV9097_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_STENCIL_OP_FAIL 0x1384 +#define NV9097_SET_STENCIL_OP_FAIL_V 31:0 +#define NV9097_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NV9097_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NV9097_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NV9097_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NV9097_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NV9097_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NV9097_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NV9097_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NV9097_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NV9097_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NV9097_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NV9097_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NV9097_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NV9097_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NV9097_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NV9097_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NV9097_SET_STENCIL_OP_ZFAIL 0x1388 +#define NV9097_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NV9097_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NV9097_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NV9097_SET_STENCIL_OP_ZPASS 0x138c +#define NV9097_SET_STENCIL_OP_ZPASS_V 31:0 +#define NV9097_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NV9097_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NV9097_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NV9097_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NV9097_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NV9097_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NV9097_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NV9097_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NV9097_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NV9097_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NV9097_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NV9097_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NV9097_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NV9097_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NV9097_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NV9097_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NV9097_SET_STENCIL_FUNC 0x1390 +#define NV9097_SET_STENCIL_FUNC_V 31:0 +#define NV9097_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NV9097_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NV9097_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NV9097_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NV9097_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NV9097_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NV9097_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NV9097_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NV9097_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NV9097_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NV9097_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NV9097_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NV9097_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NV9097_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NV9097_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NV9097_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NV9097_SET_STENCIL_FUNC_REF 0x1394 +#define NV9097_SET_STENCIL_FUNC_REF_V 7:0 + +#define NV9097_SET_STENCIL_FUNC_MASK 0x1398 +#define NV9097_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NV9097_SET_STENCIL_MASK 0x139c +#define NV9097_SET_STENCIL_MASK_V 7:0 + +#define NV9097_SET_DRAW_AUTO_START 0x13a4 +#define NV9097_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NV9097_SET_PS_SATURATE 0x13a8 +#define NV9097_SET_PS_SATURATE_OUTPUT0 0:0 +#define NV9097_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NV9097_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NV9097_SET_PS_SATURATE_OUTPUT1 4:4 +#define NV9097_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NV9097_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NV9097_SET_PS_SATURATE_OUTPUT2 8:8 +#define NV9097_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NV9097_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NV9097_SET_PS_SATURATE_OUTPUT3 12:12 +#define NV9097_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NV9097_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NV9097_SET_PS_SATURATE_OUTPUT4 16:16 +#define NV9097_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NV9097_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NV9097_SET_PS_SATURATE_OUTPUT5 20:20 +#define NV9097_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NV9097_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NV9097_SET_PS_SATURATE_OUTPUT6 24:24 +#define NV9097_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NV9097_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NV9097_SET_PS_SATURATE_OUTPUT7 28:28 +#define NV9097_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NV9097_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 + +#define NV9097_SET_WINDOW_ORIGIN 0x13ac +#define NV9097_SET_WINDOW_ORIGIN_MODE 0:0 +#define NV9097_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NV9097_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NV9097_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NV9097_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NV9097_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NV9097_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NV9097_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NV9097_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NV9097_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NV9097_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NV9097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NV9097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_ALPHA_HYSTERESIS 0x1420 +#define NV9097_SET_ALPHA_HYSTERESIS_ROUNDS_OF_ALPHA 7:0 + +#define NV9097_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NV9097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NV9097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NV9097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NV9097_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NV9097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NV9097_INVALIDATE_DA_DMA_CACHE 0x142c +#define NV9097_INVALIDATE_DA_DMA_CACHE_V 0:0 + +#define NV9097_X_X_X_SET_REDUCE_DST_COLOR 0x1430 +#define NV9097_X_X_X_SET_REDUCE_DST_COLOR_UNORM_ENABLE 4:4 +#define NV9097_X_X_X_SET_REDUCE_DST_COLOR_UNORM_ENABLE_FALSE 0x00000000 +#define NV9097_X_X_X_SET_REDUCE_DST_COLOR_UNORM_ENABLE_TRUE 0x00000001 +#define NV9097_X_X_X_SET_REDUCE_DST_COLOR_SRGB_ENABLE 8:8 +#define NV9097_X_X_X_SET_REDUCE_DST_COLOR_SRGB_ENABLE_FALSE 0x00000000 +#define NV9097_X_X_X_SET_REDUCE_DST_COLOR_SRGB_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NV9097_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NV9097_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NV9097_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NV9097_X_X_X_SET_CLEAR_CONTROL 0x143c +#define NV9097_X_X_X_SET_CLEAR_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NV9097_X_X_X_SET_CLEAR_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CLEAR_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NV9097_X_X_X_SET_CLEAR_CONTROL_USE_CLEAR_RECT 4:4 +#define NV9097_X_X_X_SET_CLEAR_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NV9097_X_X_X_SET_CLEAR_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 + +#define NV9097_SET_PS_WARP_WATERMARKS 0x1450 +#define NV9097_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NV9097_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NV9097_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NV9097_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NV9097_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NV9097_STORE_ZCULL 0x1464 +#define NV9097_STORE_ZCULL_V 0:0 + +#define NV9097_LOAD_ZCULL 0x1500 +#define NV9097_LOAD_ZCULL_V 0:0 + +#define NV9097_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NV9097_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NV9097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NV9097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NV9097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NV9097_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NV9097_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NV9097_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NV9097_SET_USER_CLIP_ENABLE 0x1510 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NV9097_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NV9097_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NV9097_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NV9097_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_POINT_SIZE 0x1518 +#define NV9097_SET_POINT_SIZE_V 31:0 + +#define NV9097_SET_ZCULL_STATS 0x151c +#define NV9097_SET_ZCULL_STATS_ENABLE 0:0 +#define NV9097_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_POINT_SPRITE 0x1520 +#define NV9097_SET_POINT_SPRITE_ENABLE 0:0 +#define NV9097_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_SHADER_EXCEPTIONS 0x1528 +#define NV9097_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NV9097_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NV9097_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NV9097_CLEAR_REPORT_VALUE 0x1530 +#define NV9097_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NV9097_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NV9097_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NV9097_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NV9097_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NV9097_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NV9097_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NV9097_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 + +#define NV9097_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NV9097_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NV9097_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NV9097_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NV9097_SET_ZT_SELECT 0x1538 +#define NV9097_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NV9097_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NV9097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NV9097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NV9097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NV9097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NV9097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NV9097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NV9097_SET_RENDER_ENABLE_A 0x1550 +#define NV9097_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_RENDER_ENABLE_B 0x1554 +#define NV9097_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_RENDER_ENABLE_C 0x1558 +#define NV9097_SET_RENDER_ENABLE_C_MODE 2:0 +#define NV9097_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NV9097_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NV9097_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NV9097_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NV9097_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NV9097_SET_TEX_SAMPLER_POOL_A 0x155c +#define NV9097_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NV9097_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NV9097_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NV9097_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NV9097_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NV9097_SET_ANTI_ALIASED_LINE 0x1570 +#define NV9097_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NV9097_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_TEX_HEADER_POOL_A 0x1574 +#define NV9097_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_TEX_HEADER_POOL_B 0x1578 +#define NV9097_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_TEX_HEADER_POOL_C 0x157c +#define NV9097_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NV9097_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NV9097_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NV9097_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NV9097_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NV9097_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NV9097_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NV9097_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NV9097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NV9097_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NV9097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NV9097_SET_BACK_STENCIL_FUNC 0x15a4 +#define NV9097_SET_BACK_STENCIL_FUNC_V 31:0 +#define NV9097_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NV9097_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NV9097_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NV9097_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NV9097_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NV9097_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NV9097_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NV9097_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NV9097_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NV9097_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NV9097_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NV9097_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NV9097_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NV9097_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NV9097_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NV9097_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NV9097_SET_SRGB_WRITE 0x15b8 +#define NV9097_SET_SRGB_WRITE_ENABLE 0:0 +#define NV9097_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_DEPTH_BIAS 0x15bc +#define NV9097_SET_DEPTH_BIAS_V 31:0 + +#define NV9097_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NV9097_SET_ZCULL_REGION_FORMAT_TYPE 1:0 +#define NV9097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NV9097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NV9097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NV9097_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 + +#define NV9097_SET_RT_LAYER 0x15cc +#define NV9097_SET_RT_LAYER_V 15:0 +#define NV9097_SET_RT_LAYER_CONTROL 16:16 +#define NV9097_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NV9097_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NV9097_SET_ANTI_ALIAS 0x15d0 +#define NV9097_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NV9097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NV9097_SET_EDGE_FLAG 0x15e4 +#define NV9097_SET_EDGE_FLAG_V 0:0 +#define NV9097_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NV9097_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NV9097_DRAW_INLINE_INDEX 0x15e8 +#define NV9097_DRAW_INLINE_INDEX_V 31:0 + +#define NV9097_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NV9097_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NV9097_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NV9097_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NV9097_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NV9097_DRAW_INLINE_INDEX2X16 0x15f0 +#define NV9097_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NV9097_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NV9097_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NV9097_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NV9097_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NV9097_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NV9097_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NV9097_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NV9097_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NV9097_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NV9097_SET_POINT_SPRITE_SELECT 0x1604 +#define NV9097_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NV9097_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NV9097_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NV9097_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NV9097_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NV9097_SET_PROGRAM_REGION_A 0x1608 +#define NV9097_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NV9097_SET_PROGRAM_REGION_B 0x160c +#define NV9097_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NV9097_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NV9097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NV9097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NV9097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NV9097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NV9097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NV9097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NV9097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NV9097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NV9097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NV9097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NV9097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NV9097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NV9097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NV9097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NV9097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NV9097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NV9097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NV9097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NV9097_END 0x1614 +#define NV9097_END_V 0:0 + +#define NV9097_BEGIN 0x1618 +#define NV9097_BEGIN_OP 15:0 +#define NV9097_BEGIN_OP_POINTS 0x00000000 +#define NV9097_BEGIN_OP_LINES 0x00000001 +#define NV9097_BEGIN_OP_LINE_LOOP 0x00000002 +#define NV9097_BEGIN_OP_LINE_STRIP 0x00000003 +#define NV9097_BEGIN_OP_TRIANGLES 0x00000004 +#define NV9097_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NV9097_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NV9097_BEGIN_OP_QUADS 0x00000007 +#define NV9097_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NV9097_BEGIN_OP_POLYGON 0x00000009 +#define NV9097_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NV9097_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NV9097_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_BEGIN_OP_PATCH 0x0000000E +#define NV9097_BEGIN_PRIMITIVE_ID 24:24 +#define NV9097_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NV9097_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NV9097_BEGIN_INSTANCE_ID 27:26 +#define NV9097_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NV9097_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NV9097_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NV9097_BEGIN_SPLIT_MODE 30:29 +#define NV9097_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NV9097_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NV9097_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NV9097_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 + +#define NV9097_SET_VERTEX_ID_COPY 0x161c +#define NV9097_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NV9097_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NV9097_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NV9097_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NV9097_ADD_TO_PRIMITIVE_ID 0x1620 +#define NV9097_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NV9097_LOAD_PRIMITIVE_ID 0x1624 +#define NV9097_LOAD_PRIMITIVE_ID_V 31:0 + +#define NV9097_SET_SHADER_BASED_CULL 0x162c +#define NV9097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NV9097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NV9097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NV9097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NV9097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NV9097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_SHADER_ISA_VERSION 0x1634 +#define NV9097_SET_SHADER_ISA_VERSION_MINOR_SUB 7:0 +#define NV9097_SET_SHADER_ISA_VERSION_MINOR 15:8 +#define NV9097_SET_SHADER_ISA_VERSION_MAJOR 23:16 + +#define NV9097_SET_FERMI_CLASS_VERSION 0x1638 +#define NV9097_SET_FERMI_CLASS_VERSION_CURRENT 15:0 +#define NV9097_SET_FERMI_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NV9097_SET_VAB_PAGE 0x163c +#define NV9097_SET_VAB_PAGE_READ_SELECT 0:0 +#define NV9097_SET_VAB_PAGE_READ_SELECT_PAGES_0_AND_1 0x00000000 +#define NV9097_SET_VAB_PAGE_READ_SELECT_PAGES_0_AND_2 0x00000001 + +#define NV9097_DRAW_INLINE_VERTEX 0x1640 +#define NV9097_DRAW_INLINE_VERTEX_V 31:0 + +#define NV9097_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NV9097_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NV9097_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NV9097_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NV9097_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NV9097_SET_DA_OUTPUT 0x164c +#define NV9097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NV9097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NV9097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NV9097_SET_ANTI_ALIASED_POINT 0x1658 +#define NV9097_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NV9097_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_POINT_CENTER_MODE 0x165c +#define NV9097_SET_POINT_CENTER_MODE_V 31:0 +#define NV9097_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NV9097_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NV9097_SET_CUBEMAP_INTER_FACE_FILTERING 0x1664 +#define NV9097_SET_CUBEMAP_INTER_FACE_FILTERING_MODE 2:1 +#define NV9097_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_USE_WRAP 0x00000000 +#define NV9097_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_OVERRIDE_WRAP 0x00000001 +#define NV9097_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_SPAN_SEAM 0x00000002 +#define NV9097_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_CROSS_SEAM 0x00000003 + +#define NV9097_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NV9097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NV9097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NV9097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NV9097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NV9097_SET_LINE_STIPPLE 0x166c +#define NV9097_SET_LINE_STIPPLE_ENABLE 0:0 +#define NV9097_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NV9097_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NV9097_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NV9097_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NV9097_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NV9097_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NV9097_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NV9097_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NV9097_SET_PROVOKING_VERTEX 0x1684 +#define NV9097_SET_PROVOKING_VERTEX_V 0:0 +#define NV9097_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NV9097_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NV9097_SET_TWO_SIDED_LIGHT 0x1688 +#define NV9097_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NV9097_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_POLYGON_STIPPLE 0x168c +#define NV9097_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NV9097_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_SHADER_CONTROL 0x1690 +#define NV9097_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NV9097_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NV9097_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NV9097_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO 16:16 +#define NV9097_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NV9097_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NV9097_LAUNCH_VERTEX 0x169c +#define NV9097_LAUNCH_VERTEX_V 0:0 + +#define NV9097_CHECK_FERMI_CLASS_VERSION 0x16a0 +#define NV9097_CHECK_FERMI_CLASS_VERSION_CURRENT 15:0 +#define NV9097_CHECK_FERMI_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NV9097_SET_SPH_VERSION 0x16a4 +#define NV9097_SET_SPH_VERSION_CURRENT 15:0 +#define NV9097_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NV9097_CHECK_SPH_VERSION 0x16a8 +#define NV9097_CHECK_SPH_VERSION_CURRENT 15:0 +#define NV9097_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NV9097_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NV9097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NV9097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NV9097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NV9097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NV9097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NV9097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NV9097_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NV9097_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NV9097_SET_AAM_VERSION 0x1790 +#define NV9097_SET_AAM_VERSION_CURRENT 15:0 +#define NV9097_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NV9097_CHECK_AAM_VERSION 0x1794 +#define NV9097_CHECK_AAM_VERSION_CURRENT 15:0 +#define NV9097_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NV9097_SET_ZT_LAYER 0x179c +#define NV9097_SET_ZT_LAYER_OFFSET 15:0 + +#define NV9097_SET_VAB_MEMORY_AREA_A 0x17bc +#define NV9097_SET_VAB_MEMORY_AREA_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_VAB_MEMORY_AREA_B 0x17c0 +#define NV9097_SET_VAB_MEMORY_AREA_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_VAB_MEMORY_AREA_C 0x17c4 +#define NV9097_SET_VAB_MEMORY_AREA_C_SIZE 1:0 +#define NV9097_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_64K 0x00000001 +#define NV9097_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_128K 0x00000002 +#define NV9097_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_256K 0x00000003 + +#define NV9097_SET_INDEX_BUFFER_A 0x17c8 +#define NV9097_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NV9097_SET_INDEX_BUFFER_B 0x17cc +#define NV9097_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NV9097_SET_INDEX_BUFFER_C 0x17d0 +#define NV9097_SET_INDEX_BUFFER_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NV9097_SET_INDEX_BUFFER_D 0x17d4 +#define NV9097_SET_INDEX_BUFFER_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NV9097_SET_INDEX_BUFFER_E 0x17d8 +#define NV9097_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NV9097_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NV9097_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NV9097_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NV9097_SET_INDEX_BUFFER_F 0x17dc +#define NV9097_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NV9097_DRAW_INDEX_BUFFER 0x17e0 +#define NV9097_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NV9097_SET_DEPTH_BIAS_CLAMP 0x187c +#define NV9097_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NV9097_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NV9097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NV9097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NV9097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NV9097_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NV9097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NV9097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NV9097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NV9097_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NV9097_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NV9097_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NV9097_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NV9097_OGL_SET_CULL 0x1918 +#define NV9097_OGL_SET_CULL_ENABLE 0:0 +#define NV9097_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NV9097_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NV9097_OGL_SET_FRONT_FACE 0x191c +#define NV9097_OGL_SET_FRONT_FACE_V 31:0 +#define NV9097_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NV9097_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NV9097_OGL_SET_CULL_FACE 0x1920 +#define NV9097_OGL_SET_CULL_FACE_V 31:0 +#define NV9097_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NV9097_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NV9097_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NV9097_SET_VIEWPORT_PIXEL 0x1924 +#define NV9097_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NV9097_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NV9097_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NV9097_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NV9097_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NV9097_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NV9097_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NV9097_INVALIDATE_CONSTANT_BUFFER_CACHE 0x1930 +#define NV9097_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2 0:0 +#define NV9097_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_FALSE 0x00000000 +#define NV9097_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_TRUE 0x00000001 + +#define NV9097_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NV9097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NV9097_SET_USER_CLIP_OP 0x1940 +#define NV9097_SET_USER_CLIP_OP_PLANE0 0:0 +#define NV9097_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NV9097_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NV9097_SET_USER_CLIP_OP_PLANE1 4:4 +#define NV9097_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NV9097_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NV9097_SET_USER_CLIP_OP_PLANE2 8:8 +#define NV9097_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NV9097_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NV9097_SET_USER_CLIP_OP_PLANE3 12:12 +#define NV9097_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NV9097_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NV9097_SET_USER_CLIP_OP_PLANE4 16:16 +#define NV9097_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NV9097_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NV9097_SET_USER_CLIP_OP_PLANE5 20:20 +#define NV9097_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NV9097_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NV9097_SET_USER_CLIP_OP_PLANE6 24:24 +#define NV9097_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NV9097_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NV9097_SET_USER_CLIP_OP_PLANE7 28:28 +#define NV9097_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NV9097_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NV9097_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NV9097_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NV9097_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NV9097_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NV9097_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NV9097_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NV9097_SET_WINDOW_CLIP_ENABLE 0x194c +#define NV9097_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NV9097_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NV9097_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NV9097_SET_WINDOW_CLIP_TYPE 0x1950 +#define NV9097_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NV9097_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NV9097_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NV9097_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NV9097_INVALIDATE_ZCULL 0x1958 +#define NV9097_INVALIDATE_ZCULL_V 31:0 +#define NV9097_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NV9097_SET_ZCULL 0x1968 +#define NV9097_SET_ZCULL_Z_ENABLE 0:0 +#define NV9097_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NV9097_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NV9097_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_ZCULL_BOUNDS 0x196c +#define NV9097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NV9097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NV9097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NV9097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NV9097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NV9097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NV9097_ZCULL_SYNC 0x1978 +#define NV9097_ZCULL_SYNC_V 31:0 + +#define NV9097_SET_CLIP_ID_TEST 0x197c +#define NV9097_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NV9097_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NV9097_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NV9097_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NV9097_SET_CLIP_ID 0x1984 +#define NV9097_SET_CLIP_ID_V 31:0 + +#define NV9097_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NV9097_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NV9097_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NV9097_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NV9097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NV9097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NV9097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NV9097_SET_LOGIC_OP 0x19c4 +#define NV9097_SET_LOGIC_OP_ENABLE 0:0 +#define NV9097_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NV9097_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_LOGIC_OP_FUNC 0x19c8 +#define NV9097_SET_LOGIC_OP_FUNC_V 31:0 +#define NV9097_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NV9097_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NV9097_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NV9097_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NV9097_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NV9097_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NV9097_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NV9097_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NV9097_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NV9097_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NV9097_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NV9097_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NV9097_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NV9097_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NV9097_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NV9097_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NV9097_SET_Z_COMPRESSION 0x19cc +#define NV9097_SET_Z_COMPRESSION_ENABLE 0:0 +#define NV9097_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NV9097_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NV9097_CLEAR_SURFACE 0x19d0 +#define NV9097_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NV9097_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NV9097_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NV9097_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NV9097_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NV9097_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NV9097_CLEAR_SURFACE_R_ENABLE 2:2 +#define NV9097_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NV9097_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NV9097_CLEAR_SURFACE_G_ENABLE 3:3 +#define NV9097_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NV9097_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NV9097_CLEAR_SURFACE_B_ENABLE 4:4 +#define NV9097_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NV9097_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NV9097_CLEAR_SURFACE_A_ENABLE 5:5 +#define NV9097_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NV9097_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NV9097_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NV9097_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NV9097_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NV9097_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NV9097_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NV9097_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NV9097_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NV9097_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NV9097_SET_CT_WRITE_R_ENABLE 0:0 +#define NV9097_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NV9097_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NV9097_SET_CT_WRITE_G_ENABLE 4:4 +#define NV9097_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NV9097_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NV9097_SET_CT_WRITE_B_ENABLE 8:8 +#define NV9097_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NV9097_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NV9097_SET_CT_WRITE_A_ENABLE 12:12 +#define NV9097_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NV9097_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NV9097_PIPE_NOP 0x1a2c +#define NV9097_PIPE_NOP_V 31:0 + +#define NV9097_SET_SPARE00 0x1a30 +#define NV9097_SET_SPARE00_V 31:0 + +#define NV9097_SET_SPARE01 0x1a34 +#define NV9097_SET_SPARE01_V 31:0 + +#define NV9097_SET_SPARE02 0x1a38 +#define NV9097_SET_SPARE02_V 31:0 + +#define NV9097_SET_SPARE03 0x1a3c +#define NV9097_SET_SPARE03_V 31:0 + +#define NV9097_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NV9097_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NV9097_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NV9097_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NV9097_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NV9097_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NV9097_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NV9097_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NV9097_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NV9097_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NV9097_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NV9097_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NV9097_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NV9097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NV9097_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NV9097_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NV9097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NV9097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NV9097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NV9097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NV9097_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NV9097_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NV9097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NV9097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NV9097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 + +#define NV9097_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NV9097_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NV9097_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NV9097_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NV9097_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NV9097_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NV9097_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NV9097_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NV9097_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NV9097_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NV9097_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NV9097_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NV9097_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NV9097_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NV9097_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NV9097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NV9097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NV9097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NV9097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NV9097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NV9097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NV9097_SET_VERTEX_STREAM_LIMIT_A_A(j) (0x1f00+(j)*8) +#define NV9097_SET_VERTEX_STREAM_LIMIT_A_A_UPPER 7:0 + +#define NV9097_SET_VERTEX_STREAM_LIMIT_A_B(j) (0x1f04+(j)*8) +#define NV9097_SET_VERTEX_STREAM_LIMIT_A_B_LOWER 31:0 + +#define NV9097_SET_VERTEX_STREAM_LIMIT_B_A(j) (0x1f80+(j)*8) +#define NV9097_SET_VERTEX_STREAM_LIMIT_B_A_UPPER 7:0 + +#define NV9097_SET_VERTEX_STREAM_LIMIT_B_B(j) (0x1f84+(j)*8) +#define NV9097_SET_VERTEX_STREAM_LIMIT_B_B_LOWER 31:0 + +#define NV9097_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NV9097_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NV9097_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NV9097_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NV9097_SET_PIPELINE_SHADER_TYPE 7:4 +#define NV9097_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NV9097_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NV9097_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NV9097_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NV9097_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NV9097_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NV9097_SET_PIPELINE_PROGRAM(j) (0x2004+(j)*64) +#define NV9097_SET_PIPELINE_PROGRAM_OFFSET 31:0 + +#define NV9097_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NV9097_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NV9097_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NV9097_SET_PIPELINE_REGISTER_COUNT_V 7:0 + +#define NV9097_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NV9097_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NV9097_SET_PIPELINE_RESERVED_B(j) (0x2014+(j)*64) +#define NV9097_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NV9097_SET_PIPELINE_RESERVED_C(j) (0x2018+(j)*64) +#define NV9097_SET_PIPELINE_RESERVED_C_V 0:0 + +#define NV9097_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NV9097_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NV9097_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NV9097_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NV9097_SET_BINDING_CONTROL_TEXTURE(j) (0x2200+(j)*16) +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS 3:0 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__1 0x00000000 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__2 0x00000001 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__4 0x00000002 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__8 0x00000003 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__16 0x00000004 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS 7:4 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__1 0x00000000 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__2 0x00000001 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__4 0x00000002 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__8 0x00000003 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__16 0x00000004 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__32 0x00000005 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__64 0x00000006 +#define NV9097_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__128 0x00000007 + +#define NV9097_SET_BINDING_CONTROL_RESERVED_A(j) (0x2204+(j)*16) +#define NV9097_SET_BINDING_CONTROL_RESERVED_A_V 0:0 + +#define NV9097_SET_BINDING_CONTROL_RESERVED_B(j) (0x2208+(j)*16) +#define NV9097_SET_BINDING_CONTROL_RESERVED_B_V 0:0 + +#define NV9097_SET_FALCON00 0x2300 +#define NV9097_SET_FALCON00_V 31:0 + +#define NV9097_SET_FALCON01 0x2304 +#define NV9097_SET_FALCON01_V 31:0 + +#define NV9097_SET_FALCON02 0x2308 +#define NV9097_SET_FALCON02_V 31:0 + +#define NV9097_SET_FALCON03 0x230c +#define NV9097_SET_FALCON03_V 31:0 + +#define NV9097_SET_FALCON04 0x2310 +#define NV9097_SET_FALCON04_V 31:0 + +#define NV9097_SET_FALCON05 0x2314 +#define NV9097_SET_FALCON05_V 31:0 + +#define NV9097_SET_FALCON06 0x2318 +#define NV9097_SET_FALCON06_V 31:0 + +#define NV9097_SET_FALCON07 0x231c +#define NV9097_SET_FALCON07_V 31:0 + +#define NV9097_SET_FALCON08 0x2320 +#define NV9097_SET_FALCON08_V 31:0 + +#define NV9097_SET_FALCON09 0x2324 +#define NV9097_SET_FALCON09_V 31:0 + +#define NV9097_SET_FALCON10 0x2328 +#define NV9097_SET_FALCON10_V 31:0 + +#define NV9097_SET_FALCON11 0x232c +#define NV9097_SET_FALCON11_V 31:0 + +#define NV9097_SET_FALCON12 0x2330 +#define NV9097_SET_FALCON12_V 31:0 + +#define NV9097_SET_FALCON13 0x2334 +#define NV9097_SET_FALCON13_V 31:0 + +#define NV9097_SET_FALCON14 0x2338 +#define NV9097_SET_FALCON14_V 31:0 + +#define NV9097_SET_FALCON15 0x233c +#define NV9097_SET_FALCON15_V 31:0 + +#define NV9097_SET_FALCON16 0x2340 +#define NV9097_SET_FALCON16_V 31:0 + +#define NV9097_SET_FALCON17 0x2344 +#define NV9097_SET_FALCON17_V 31:0 + +#define NV9097_SET_FALCON18 0x2348 +#define NV9097_SET_FALCON18_V 31:0 + +#define NV9097_SET_FALCON19 0x234c +#define NV9097_SET_FALCON19_V 31:0 + +#define NV9097_SET_FALCON20 0x2350 +#define NV9097_SET_FALCON20_V 31:0 + +#define NV9097_SET_FALCON21 0x2354 +#define NV9097_SET_FALCON21_V 31:0 + +#define NV9097_SET_FALCON22 0x2358 +#define NV9097_SET_FALCON22_V 31:0 + +#define NV9097_SET_FALCON23 0x235c +#define NV9097_SET_FALCON23_V 31:0 + +#define NV9097_SET_FALCON24 0x2360 +#define NV9097_SET_FALCON24_V 31:0 + +#define NV9097_SET_FALCON25 0x2364 +#define NV9097_SET_FALCON25_V 31:0 + +#define NV9097_SET_FALCON26 0x2368 +#define NV9097_SET_FALCON26_V 31:0 + +#define NV9097_SET_FALCON27 0x236c +#define NV9097_SET_FALCON27_V 31:0 + +#define NV9097_SET_FALCON28 0x2370 +#define NV9097_SET_FALCON28_V 31:0 + +#define NV9097_SET_FALCON29 0x2374 +#define NV9097_SET_FALCON29_V 31:0 + +#define NV9097_SET_FALCON30 0x2378 +#define NV9097_SET_FALCON30_V 31:0 + +#define NV9097_SET_FALCON31 0x237c +#define NV9097_SET_FALCON31_V 31:0 + +#define NV9097_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NV9097_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NV9097_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NV9097_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NV9097_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NV9097_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NV9097_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NV9097_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NV9097_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NV9097_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NV9097_BIND_GROUP_TEXTURE_SAMPLER(j) (0x2400+(j)*32) +#define NV9097_BIND_GROUP_TEXTURE_SAMPLER_VALID 0:0 +#define NV9097_BIND_GROUP_TEXTURE_SAMPLER_VALID_FALSE 0x00000000 +#define NV9097_BIND_GROUP_TEXTURE_SAMPLER_VALID_TRUE 0x00000001 +#define NV9097_BIND_GROUP_TEXTURE_SAMPLER_SAMPLER_SLOT 11:4 +#define NV9097_BIND_GROUP_TEXTURE_SAMPLER_INDEX 24:12 + +#define NV9097_BIND_GROUP_TEXTURE_HEADER(j) (0x2404+(j)*32) +#define NV9097_BIND_GROUP_TEXTURE_HEADER_VALID 0:0 +#define NV9097_BIND_GROUP_TEXTURE_HEADER_VALID_FALSE 0x00000000 +#define NV9097_BIND_GROUP_TEXTURE_HEADER_VALID_TRUE 0x00000001 +#define NV9097_BIND_GROUP_TEXTURE_HEADER_TEXTURE_SLOT 8:1 +#define NV9097_BIND_GROUP_TEXTURE_HEADER_INDEX 30:9 + +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_SAMPLER(j) (0x2408+(j)*32) +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_SAMPLER_VALID 0:0 +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_SAMPLER_VALID_FALSE 0x00000000 +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_SAMPLER_VALID_TRUE 0x00000001 +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_SAMPLER_SAMPLER_SLOT 11:4 +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_SAMPLER_INDEX 24:12 + +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_HEADER(j) (0x240c+(j)*32) +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_HEADER_VALID 0:0 +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_HEADER_VALID_FALSE 0x00000000 +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_HEADER_VALID_TRUE 0x00000001 +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_HEADER_TEXTURE_SLOT 8:1 +#define NV9097_BIND_GROUP_EXTRA_TEXTURE_HEADER_INDEX 30:9 + +#define NV9097_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NV9097_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NV9097_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NV9097_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NV9097_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NV9097_RESERVED_GROUP_B_RESERVED_A(j) (0x2500+(j)*32) +#define NV9097_RESERVED_GROUP_B_RESERVED_A_V 0:0 + +#define NV9097_RESERVED_GROUP_B_RESERVED_B(j) (0x2504+(j)*32) +#define NV9097_RESERVED_GROUP_B_RESERVED_B_V 0:0 + +#define NV9097_RESERVED_GROUP_B_RESERVED_C(j) (0x2508+(j)*32) +#define NV9097_RESERVED_GROUP_B_RESERVED_C_V 0:0 + +#define NV9097_RESERVED_GROUP_B_RESERVED_D(j) (0x250c+(j)*32) +#define NV9097_RESERVED_GROUP_B_RESERVED_D_V 0:0 + +#define NV9097_RESERVED_GROUP_B_RESERVED_E(j) (0x2510+(j)*32) +#define NV9097_RESERVED_GROUP_B_RESERVED_E_V 0:0 + +#define NV9097_SET_COLOR_CLAMP 0x2600 +#define NV9097_SET_COLOR_CLAMP_ENABLE 0:0 +#define NV9097_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NV9097_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NV9097_SET_SU_LD_ST_TARGET_A(j) (0x2700+(j)*32) +#define NV9097_SET_SU_LD_ST_TARGET_A_OFFSET_UPPER 7:0 + +#define NV9097_SET_SU_LD_ST_TARGET_B(j) (0x2704+(j)*32) +#define NV9097_SET_SU_LD_ST_TARGET_B_OFFSET_LOWER 31:0 + +#define NV9097_SET_SU_LD_ST_TARGET_C(j) (0x2708+(j)*32) +#define NV9097_SET_SU_LD_ST_TARGET_C_WIDTH 31:0 + +#define NV9097_SET_SU_LD_ST_TARGET_D(j) (0x270c+(j)*32) +#define NV9097_SET_SU_LD_ST_TARGET_D_HEIGHT 16:0 +#define NV9097_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY 20:20 +#define NV9097_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY_BLOCKLINEAR 0x00000000 +#define NV9097_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY_PITCH 0x00000001 + +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT(j) (0x2710+(j)*32) +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_TYPE 0:0 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_TYPE_COLOR 0x00000000 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_TYPE_ZETA 0x00000001 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR 11:4 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_DISABLED 0x00000000 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32_BF32_AF32 0x000000C0 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32_BS32_AS32 0x000000C1 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32_BU32_AU32 0x000000C2 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32_BF32_X32 0x000000C3 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32_BS32_X32 0x000000C4 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32_BU32_X32 0x000000C5 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_G16_B16_A16 0x000000C6 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16_GN16_BN16_AN16 0x000000C7 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16_GS16_BS16_AS16 0x000000C8 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16_GU16_BU16_AU16 0x000000C9 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16_BF16_AF16 0x000000CA +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32 0x000000CB +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32 0x000000CC +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32 0x000000CD +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16_BF16_X16 0x000000CE +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8R8G8B8 0x000000CF +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8RL8GL8BL8 0x000000D0 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A2B10G10R10 0x000000D1 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AU2BU10GU10RU10 0x000000D2 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8B8G8R8 0x000000D5 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8BL8GL8RL8 0x000000D6 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AN8BN8GN8RN8 0x000000D7 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AS8BS8GS8RS8 0x000000D8 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AU8BU8GU8RU8 0x000000D9 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_G16 0x000000DA +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16_GN16 0x000000DB +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16_GS16 0x000000DC +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16_GU16 0x000000DD +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16 0x000000DE +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A2R10G10B10 0x000000DF +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_BF10GF11RF11 0x000000E0 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32 0x000000E3 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32 0x000000E4 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32 0x000000E5 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8R8G8B8 0x000000E6 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8RL8GL8BL8 0x000000E7 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R5G6B5 0x000000E8 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A1R5G5B5 0x000000E9 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_G8R8 0x000000EA +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GN8RN8 0x000000EB +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GS8RS8 0x000000EC +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GU8RU8 0x000000ED +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16 0x000000EE +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16 0x000000EF +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16 0x000000F0 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16 0x000000F1 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16 0x000000F2 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R8 0x000000F3 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN8 0x000000F4 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS8 0x000000F5 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU8 0x000000F6 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8 0x000000F7 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X1R5G5B5 0x000000F8 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8B8G8R8 0x000000F9 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8BL8GL8RL8 0x000000FA +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_Z1R5G5B5 0x000000FB +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_O1R5G5B5 0x000000FC +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_Z8R8G8B8 0x000000FD +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_O8R8G8B8 0x000000FE +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R32 0x000000FF +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A16 0x00000040 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AF16 0x00000041 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AF32 0x00000042 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8R8 0x00000043 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_A16 0x00000044 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_AF16 0x00000045 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_AF32 0x00000046 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA 16:12 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_Z16 0x00000013 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_Z24S8 0x00000014 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_X8Z24 0x00000015 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_S8Z24 0x00000016 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_V8Z24 0x00000018 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32 0x0000000A +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X24S8 0x00000019 +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_X8Z24_X16V8S8 0x0000001D +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X16V8X8 0x0000001E +#define NV9097_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X16V8S8 0x0000001F + +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE(j) (0x2714+(j)*32) +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_WIDTH 3:0 +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT 7:4 +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV9097_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 + +#define NV9097_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NV9097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NV9097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NV9097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NV9097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 2:0 +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 6:4 +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 10:8 +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 14:12 +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 18:16 +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 22:20 +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 26:24 +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 30:28 + +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NV9097_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NV9097_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NV9097_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NV9097_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NV9097_CALL_MME_MACRO_V 31:0 + +#define NV9097_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NV9097_CALL_MME_DATA_V 31:0 + +#endif /* _cl_fermi_a_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/cl90cd.h b/src/common/sdk/nvidia/inc/class/cl90cd.h index 2b8c2e5e7..6c626a6ea 100644 --- a/src/common/sdk/nvidia/inc/class/cl90cd.h +++ b/src/common/sdk/nvidia/inc/class/cl90cd.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,158 +21,158 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _cl90cd_h_ -#define _cl90cd_h_ +/* + * NV_EVENT_BUFFER + * An event buffer is shared between user (RO) and kernel(RW). + * It holds debug/profile event data provided by the kernel. + * + */ +#pragma once -#ifdef __cplusplus -extern "C" { -#endif +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl90cd.finn +// + +#define NV_EVENT_BUFFER (0x90cdU) /* finn: Evaluated from "NV_EVENT_BUFFER_ALLOC_PARAMETERS_MESSAGE_ID" */ /* -* NV_EVENT_BUFFER -* An event buffer is shared between user (RO) and kernel(RW). -* It holds debug/profile event data provided by the kernel. -* -*/ -#define NV_EVENT_BUFFER (0x000090CD) - -/* -* NV_EVENT_BUFFER_HEADER -* This structure holds the get and put values used to index/consume event buffer. -* Along with other RO data shared with the user. -* -* recordGet/Put: These "pointers" work in the traditional sense: -* - when GET==PUT, the fifo is empty -* - when GET==PUT+1, the fifo is full -* This implies a full fifo always has one "wasted" element. -* -* recordCount: This is the total number of records added to the buffer by the kernel -* This information is filled out when the buffer is setup to keep newest records. -* recordCount = number of records currently in the buffer + overflow count. -* -* recordDropcount: This is the number of event records that are dropped because the -* buffer is full. -* This information is filled out when event buffer is setup to keep oldest records. -* -* vardataDropcount: Event buffer provides a dual stream of data, where the record can contain -* an optional offset to a variable length data buffer. -* This is the number of variable data records that are dropped because the -* buffer is full. -* This information is filled out when event buffer is setup to keep oldest records. -*/ -typedef struct -{ - NvU32 recordGet; - NvU32 recordPut; - NvU64 recordCount; - NvU64 recordDropcount; - NvU64 vardataDropcount; + * NV_EVENT_BUFFER_HEADER + * This structure holds the get and put values used to index/consume event buffer. + * Along with other RO data shared with the user. + * + * recordGet/Put: These "pointers" work in the traditional sense: + * - when GET==PUT, the fifo is empty + * - when GET==PUT+1, the fifo is full + * This implies a full fifo always has one "wasted" element. + * + * recordCount: This is the total number of records added to the buffer by the kernel + * This information is filled out when the buffer is setup to keep newest records. + * recordCount = number of records currently in the buffer + overflow count. + * + * recordDropcount: This is the number of event records that are dropped because the + * buffer is full. + * This information is filled out when event buffer is setup to keep oldest records. + * + * vardataDropcount: Event buffer provides a dual stream of data, where the record can contain + * an optional offset to a variable length data buffer. + * This is the number of variable data records that are dropped because the + * buffer is full. + * This information is filled out when event buffer is setup to keep oldest records. + */ +typedef struct NV_EVENT_BUFFER_HEADER { + NvU32 recordGet; + NvU32 recordPut; + NV_DECLARE_ALIGNED(NvU64 recordCount, 8); + NV_DECLARE_ALIGNED(NvU64 recordDropcount, 8); + NV_DECLARE_ALIGNED(NvU64 vardataDropcount, 8); } NV_EVENT_BUFFER_HEADER; /* -* NV_EVENT_BUFFER_RECORD_HEADER -* This is the header added to each event record. -* This helps identify the event type and variable length data is associated with it. -*/ -typedef struct -{ - NvU16 type; - NvU16 subtype; - NvU32 varData; // [31: 5] = (varDataOffset >> 5); 0 < vardataOffset <= vardataBufferSize - // [ 4: 1] = reserved for future use - // [ 0: 0] = isVardataStartOffsetZero + * NV_EVENT_BUFFER_RECORD_HEADER + * This is the header added to each event record. + * This helps identify the event type and variable length data is associated with it. + */ +typedef struct NV_EVENT_BUFFER_RECORD_HEADER { + NvU16 type; + NvU16 subtype; + NvU32 varData; // [31: 5] = (varDataOffset >> 5); 0 < vardataOffset <= vardataBufferSize + // [ 4: 1] = reserved for future use + // [ 0: 0] = isVardataStartOffsetZero } NV_EVENT_BUFFER_RECORD_HEADER; /* -* NV_EVENT_BUFFER_RECORD -* This structure defines a generic event record. -* The size of this record is fixed for a given event buffer. -* It is configured by the user during allocation. -*/ -typedef struct -{ + * NV_EVENT_BUFFER_RECORD + * This structure defines a generic event record. + * The size of this record is fixed for a given event buffer. + * It is configured by the user during allocation. + */ +typedef struct NV_EVENT_BUFFER_RECORD { NV_EVENT_BUFFER_RECORD_HEADER recordHeader; - NvU64 inlinePayload[1] NV_ALIGN_BYTES(8); // 1st element of the payload/data + NV_DECLARE_ALIGNED(NvU64 inlinePayload[1], 8); // 1st element of the payload/data // Do not add more elements here, inlinePayload can contain more than one elements } NV_EVENT_BUFFER_RECORD; -#define NV_EVENT_VARDATA_GRANULARITY 32 -#define NV_EVENT_VARDATA_OFFSET_MASK (~(NV_EVENT_VARDATA_GRANULARITY - 1)) -#define NV_EVENT_VARDATA_START_OFFSET_ZERO 0x01 +#define NV_EVENT_VARDATA_GRANULARITY 32 +#define NV_EVENT_VARDATA_OFFSET_MASK (~(NV_EVENT_VARDATA_GRANULARITY - 1)) +#define NV_EVENT_VARDATA_START_OFFSET_ZERO 0x01 /* -* NV_EVENT_BUFFER_ALLOC_PARAMETERS -* -* bufferHeader [OUT] -* This is the user VA offset pointing to the base of NV_EVENT_BUFFER_HEADER. -* -* recordBuffer [OUT] -* This is the user VA offset pointing to the base of the event record buffer. -* This buffer will contain NV_EVENT_BUFFER_RECORDs added by the kernel. -* -* recordSize [IN] -* This is the size of NV_EVENT_BUFFER_RECORD used by this buffer -* -* recordCount [IN] -* This is the number of records that recordBuffer can hold. -* -* vardataBuffer [OUT] -* This is the user VA offset pointing to the base of the variable data buffer. -* -* vardataBufferSize [IN] -* Size of the variable data buffer in bytes. -* -* recordsFreeThreshold [IN] -* This is the notification threshold for the event record buffer. -* This felid specifies the number of records that the buffer can -* still hold before it gets full. -* -* vardataFreeThreshold [IN] -* This is the notification threshold for the vardata buffer. -* This felid specifies the number of bytes that the buffer can -* still hold before it gets full. -* -* notificationHandle [IN] -* When recordsFreeThreshold or vardataFreeThreshold is met, kernel will notify -* user on this handle. If notificationHandle = NULL, event notification -* is disabled. This is an OS specific notification handle. -* It is a Windows event handle or a fd pointer on Linux. -* -* hSubDevice [IN] -* An event buffer can either hold sub-device related events or system events. -* This handle specifies the sub-device to associate this buffer with. -* If this parameter is NULL, then the buffer is tied to the client instead. -* -* flags [IN] -* Set to 0 by default. -* This field can hold any future flags to configure the buffer if needed. -* -* hBufferHeader [IN] -* The backing memory object for the buffer header. Must be a NV01_MEMORY_DEVICELESS object. -* On Windows platforms, a buffer will be internally generated if hBufferHeader is 0. -* -* hRecordBuffer [IN] -* The backing memory object for the record buffer. Must be a NV01_MEMORY_DEVICELESS object. -* On Windows platforms, a buffer will be internally generated if hRecordBuffer is 0. -* -* hVardataBuffer [IN] -* The backing memory object for the vardata buffer. Must be a NV01_MEMORY_DEVICELESS object. -* On Windows platforms, a buffer will be internally generated if hVardataBuffer is 0. -* -*/ -typedef struct -{ - NvP64 bufferHeader NV_ALIGN_BYTES(8); - NvP64 recordBuffer NV_ALIGN_BYTES(8); - NvU32 recordSize; - NvU32 recordCount; - NvP64 vardataBuffer NV_ALIGN_BYTES(8); - NvU32 vardataBufferSize; - NvU32 recordsFreeThreshold; - NvU64 notificationHandle NV_ALIGN_BYTES(8); - NvU32 vardataFreeThreshold; + * NV_EVENT_BUFFER_ALLOC_PARAMETERS + * + * bufferHeader [OUT] + * This is the user VA offset pointing to the base of NV_EVENT_BUFFER_HEADER. + * + * recordBuffer [OUT] + * This is the user VA offset pointing to the base of the event record buffer. + * This buffer will contain NV_EVENT_BUFFER_RECORDs added by the kernel. + * + * recordSize [IN] + * This is the size of NV_EVENT_BUFFER_RECORD used by this buffer + * + * recordCount [IN] + * This is the number of records that recordBuffer can hold. + * + * vardataBuffer [OUT] + * This is the user VA offset pointing to the base of the variable data buffer. + * + * vardataBufferSize [IN] + * Size of the variable data buffer in bytes. + * + * recordsFreeThreshold [IN] + * This is the notification threshold for the event record buffer. + * This felid specifies the number of records that the buffer can + * still hold before it gets full. + * + * vardataFreeThreshold [IN] + * This is the notification threshold for the vardata buffer. + * This felid specifies the number of bytes that the buffer can + * still hold before it gets full. + * + * notificationHandle [IN] + * When recordsFreeThreshold or vardataFreeThreshold is met, kernel will notify + * user on this handle. If notificationHandle = NULL, event notification + * is disabled. This is an OS specific notification handle. + * It is a Windows event handle or a fd pointer on Linux. + * + * hSubDevice [IN] + * An event buffer can either hold sub-device related events or system events. + * This handle specifies the sub-device to associate this buffer with. + * If this parameter is NULL, then the buffer is tied to the client instead. + * + * flags [IN] + * Set to 0 by default. + * This field can hold any future flags to configure the buffer if needed. + * + * hBufferHeader [IN] + * The backing memory object for the buffer header. Must be a NV01_MEMORY_DEVICELESS object. + * On Windows platforms, a buffer will be internally generated if hBufferHeader is 0. + * + * hRecordBuffer [IN] + * The backing memory object for the record buffer. Must be a NV01_MEMORY_DEVICELESS object. + * On Windows platforms, a buffer will be internally generated if hRecordBuffer is 0. + * + * hVardataBuffer [IN] + * The backing memory object for the vardata buffer. Must be a NV01_MEMORY_DEVICELESS object. + * On Windows platforms, a buffer will be internally generated if hVardataBuffer is 0. + * + */ +#define NV_EVENT_BUFFER_ALLOC_PARAMETERS_MESSAGE_ID (0x90cdU) + +typedef struct NV_EVENT_BUFFER_ALLOC_PARAMETERS { + NV_DECLARE_ALIGNED(NvP64 bufferHeader, 8); + NV_DECLARE_ALIGNED(NvP64 recordBuffer, 8); + NvU32 recordSize; + NvU32 recordCount; + NV_DECLARE_ALIGNED(NvP64 vardataBuffer, 8); + NvU32 vardataBufferSize; + NvU32 recordsFreeThreshold; + NV_DECLARE_ALIGNED(NvU64 notificationHandle, 8); + NvU32 vardataFreeThreshold; NvHandle hSubDevice; - NvU32 flags; + NvU32 flags; NvHandle hBufferHeader; NvHandle hRecordBuffer; @@ -180,65 +180,58 @@ typedef struct } NV_EVENT_BUFFER_ALLOC_PARAMETERS; /* -* NV_EVENT_BUFFER_BIND -* This class is used to allocate an Event Type object bound to a given event buffer. -* This allocation call associates an event type with an event buffer. -* Multiple event types can be associated with the same buffer as long as they belong to -* the same category i.e. either sub-device or system. -* When event buffer is enabled, if an event bound to this buffer occurs, -* some relevant data gets added to it. -* cl2080.h has a list of sub-device events that can be associated with a buffer -* cl0000.h has a list of system events that can be associated with a buffer -* These defines are also used in class NV01_EVENT_OS_EVENT (0x79) to get event notification -* and class NV01_EVENT_KERNEL_CALLBACK_EX (0x7E) to get kernel callbacks. -* This class extends that support to additionally get relevant data in an event buffer -* -*/ -#define NV_EVENT_BUFFER_BIND (0x0000007F) + * NV_EVENT_BUFFER_BIND + * This class is used to allocate an Event Type object bound to a given event buffer. + * This allocation call associates an event type with an event buffer. + * Multiple event types can be associated with the same buffer as long as they belong to + * the same category i.e. either sub-device or system. + * When event buffer is enabled, if an event bound to this buffer occurs, + * some relevant data gets added to it. + * cl2080.h has a list of sub-device events that can be associated with a buffer + * cl0000.h has a list of system events that can be associated with a buffer + * These defines are also used in class NV01_EVENT_OS_EVENT (0x79) to get event notification + * and class NV01_EVENT_KERNEL_CALLBACK_EX (0x7E) to get kernel callbacks. + * This class extends that support to additionally get relevant data in an event buffer + * + */ +#define NV_EVENT_BUFFER_BIND (0x0000007F) /* -* NV_EVENT_BUFFER_BIND_PARAMETERS -* -* bufferHandle [IN] -* Event buffer handle used to bind the given event type -* -* eventType [IN] -* This is one of the eventTypeIDs from cl2080.h/cl000.h -* e.g. NV2080_NOTIFIERS_PSTATE_CHANGE -* -* eventSubtype [IN] -* Event subtype for a given type of event. -* This field is optional depending on if an eventtype has a subtype. -* -* hClientTarget [IN] -* Handle of the target client whose events are to be bound to the given buffer -* e.g. context switch events can be tracked for a given client. -* This field is optional depending on the event type. -* e.g. pstate change events are per gpu but do not depend on a client. -* -* hSrcResource [IN] -* source resource handle for the event type -* e.g. channel handle: RC/context switch can be tracked for a given channel -* This field is optional depending on the event type. -* e.g. pstate change events are per gpu and cannot be sub-categorized -* -* KernelCallbackdata [IN] -* This field is reserved for KERNEL ONLY clients. -* -*/ -typedef struct -{ + * NV_EVENT_BUFFER_BIND_PARAMETERS + * + * bufferHandle [IN] + * Event buffer handle used to bind the given event type + * + * eventType [IN] + * This is one of the eventTypeIDs from cl2080.h/cl000.h + * e.g. NV2080_NOTIFIERS_PSTATE_CHANGE + * + * eventSubtype [IN] + * Event subtype for a given type of event. + * This field is optional depending on if an eventtype has a subtype. + * + * hClientTarget [IN] + * Handle of the target client whose events are to be bound to the given buffer + * e.g. context switch events can be tracked for a given client. + * This field is optional depending on the event type. + * e.g. pstate change events are per gpu but do not depend on a client. + * + * hSrcResource [IN] + * source resource handle for the event type + * e.g. channel handle: RC/context switch can be tracked for a given channel + * This field is optional depending on the event type. + * e.g. pstate change events are per gpu and cannot be sub-categorized + * + * KernelCallbackdata [IN] + * This field is reserved for KERNEL ONLY clients. + * + */ +typedef struct NV_EVENT_BUFFER_BIND_PARAMETERS { NvHandle bufferHandle; - NvU16 eventType; - NvU16 eventSubtype; + NvU16 eventType; + NvU16 eventSubtype; NvHandle hClientTarget; NvHandle hSrcResource; - NvP64 KernelCallbackdata NV_ALIGN_BYTES(8); + NV_DECLARE_ALIGNED(NvP64 KernelCallbackdata, 8); } NV_EVENT_BUFFER_BIND_PARAMETERS; -#ifdef __cplusplus -}; /* extern "C" */ -#endif - -#endif // _cl90cd_h_ - diff --git a/src/common/sdk/nvidia/inc/class/cl9170.h b/src/common/sdk/nvidia/inc/class/cl9170.h index 9f774a611..478125f28 100644 --- a/src/common/sdk/nvidia/inc/class/cl9170.h +++ b/src/common/sdk/nvidia/inc/class/cl9170.h @@ -29,7 +29,7 @@ // Source file: class/cl9170.finn // -#define NV9170_DISPLAY (0x00009170) +#define NV9170_DISPLAY (0x9170U) /* finn: Evaluated from "NV9170_ALLOCATION_PARAMETERS_MESSAGE_ID" */ #define NV9170_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9170U) diff --git a/src/common/sdk/nvidia/inc/class/cl9270.h b/src/common/sdk/nvidia/inc/class/cl9270.h index c6ce40b30..de3f49894 100644 --- a/src/common/sdk/nvidia/inc/class/cl9270.h +++ b/src/common/sdk/nvidia/inc/class/cl9270.h @@ -29,7 +29,7 @@ // Source file: class/cl9270.finn // -#define NV9270_DISPLAY (0x00009270) +#define NV9270_DISPLAY (0x9270U) /* finn: Evaluated from "NV9270_ALLOCATION_PARAMETERS_MESSAGE_ID" */ #define NV9270_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9270U) diff --git a/src/common/sdk/nvidia/inc/class/cl9470.h b/src/common/sdk/nvidia/inc/class/cl9470.h index f7b1519ea..faacb955d 100644 --- a/src/common/sdk/nvidia/inc/class/cl9470.h +++ b/src/common/sdk/nvidia/inc/class/cl9470.h @@ -29,7 +29,7 @@ // Source file: class/cl9470.finn // -#define NV9470_DISPLAY (0x00009470) +#define NV9470_DISPLAY (0x9470U) /* finn: Evaluated from "NV9470_ALLOCATION_PARAMETERS_MESSAGE_ID" */ #define NV9470_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9470U) diff --git a/src/common/sdk/nvidia/inc/class/cl9570.h b/src/common/sdk/nvidia/inc/class/cl9570.h index 8f8876383..00e6d7fcd 100644 --- a/src/common/sdk/nvidia/inc/class/cl9570.h +++ b/src/common/sdk/nvidia/inc/class/cl9570.h @@ -29,7 +29,7 @@ // Source file: class/cl9570.finn // -#define NV9570_DISPLAY (0x00009570) +#define NV9570_DISPLAY (0x9570U) /* finn: Evaluated from "NV9570_ALLOCATION_PARAMETERS_MESSAGE_ID" */ #define NV9570_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9570U) diff --git a/src/common/sdk/nvidia/inc/class/cl9770.h b/src/common/sdk/nvidia/inc/class/cl9770.h index 87dccee58..914838fc4 100644 --- a/src/common/sdk/nvidia/inc/class/cl9770.h +++ b/src/common/sdk/nvidia/inc/class/cl9770.h @@ -29,7 +29,7 @@ // Source file: class/cl9770.finn // -#define NV9770_DISPLAY (0x00009770) +#define NV9770_DISPLAY (0x9770U) /* finn: Evaluated from "NV9770_ALLOCATION_PARAMETERS_MESSAGE_ID" */ #define NV9770_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9770U) diff --git a/src/common/sdk/nvidia/inc/class/cl9870.h b/src/common/sdk/nvidia/inc/class/cl9870.h index 2307a6b3b..44b76598f 100644 --- a/src/common/sdk/nvidia/inc/class/cl9870.h +++ b/src/common/sdk/nvidia/inc/class/cl9870.h @@ -29,7 +29,7 @@ // Source file: class/cl9870.finn // -#define NV9870_DISPLAY (0x00009870) +#define NV9870_DISPLAY (0x9870U) /* finn: Evaluated from "NV9870_ALLOCATION_PARAMETERS_MESSAGE_ID" */ #define NV9870_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9870U) diff --git a/src/common/sdk/nvidia/inc/class/cla06fsubch.h b/src/common/sdk/nvidia/inc/class/cla06fsubch.h index c65d6c107..330a68174 100644 --- a/src/common/sdk/nvidia/inc/class/cla06fsubch.h +++ b/src/common/sdk/nvidia/inc/class/cla06fsubch.h @@ -25,6 +25,9 @@ #define _cla06fsubch_h_ #define NVA06F_SUBCHANNEL_2D 3 +#define NVA06F_SUBCHANNEL_3D 0 +#define NVA06F_SUBCHANNEL_COMPUTE 1 #define NVA06F_SUBCHANNEL_COPY_ENGINE 4 +#define NVA06F_SUBCHANNEL_I2M 2 #endif // _cla06fsubch_h_ diff --git a/src/common/sdk/nvidia/inc/class/cla081.h b/src/common/sdk/nvidia/inc/class/cla081.h new file mode 100644 index 000000000..d17271a30 --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/cla081.h @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cla081_h_ +#define _cla081_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVA081_VGPU_CONFIG (0x0000a081) + +/*event values*/ +#define NVA081_NOTIFIERS_EVENT_VGPU_GUEST_CREATED (0) +#define NVA081_NOTIFIERS_EVENT_VGPU_GUEST_INITIALISING (1) +#define NVA081_NOTIFIERS_EVENT_VGPU_GUEST_DESTROYED (2) +#define NVA081_NOTIFIERS_MAXCOUNT (5) + + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cla081_h diff --git a/src/common/sdk/nvidia/inc/class/cla084.h b/src/common/sdk/nvidia/inc/class/cla084.h new file mode 100644 index 000000000..a224c6df1 --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/cla084.h @@ -0,0 +1,77 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cla084.finn +// + +#include "nv_vgpu_types.h" +#include "cla084_notification.h" + +#define NVA084_KERNEL_HOST_VGPU_DEVICE (0xa084U) /* finn: Evaluated from "NVA084_ALLOC_PARAMETERS_MESSAGE_ID" */ + +#define NVA084_MAX_VMMU_SEGMENTS 384 + +/* + * NVA084_ALLOC_PARAMETERS + * + * This structure represents vGPU host device KERNEL object allocation parameters. + * dbdf -> domain (31:16), bus (15:8), device (7:3), function (2:0) + * gfid -> Used only when SRIOV is enabled otherwise set to 0. + * swizzId [IN/OUT] -> Used only when MIG mode is enabled otherwise set + * to NV2080_CTRL_GPU_PARTITION_ID_INVALID. + * numChannels -> Used only when SRIOV is enabled. Must be a power of 2. + * bDisableDefaultSmcExecPartRestore - If set to true, SMC default execution partition + * save/restore will not be done in host-RM + * vgpuDeviceInstanceId -> Specifies the vGPU device instance per VM to be used + * for supporting multiple vGPUs per VM. + * numGuestFbHandles -> number of guest memory handles + * guestFbHandleList -> handle list to guest memory + * hPluginHeapMemory -> plugin heap memory handle + * bDeviceProfilingEnabled -> If set to true, profiling is allowed + */ +#define NVA084_ALLOC_PARAMETERS_MESSAGE_ID (0xa084U) + +typedef struct NVA084_ALLOC_PARAMETERS { + NvU32 dbdf; + NvU32 gfid; + NvU32 swizzId; + NvU32 vgpuType; + NvU32 vmPid; + NvU32 numChannels; + NvU32 numPluginChannels; + VM_ID_TYPE vmIdType; + NV_DECLARE_ALIGNED(VM_ID guestVmId, 8); + NvBool bDisableDefaultSmcExecPartRestore; + NvU32 vgpuDeviceInstanceId; + NvU32 numGuestFbHandles; + NvHandle guestFbHandleList[NVA084_MAX_VMMU_SEGMENTS]; + NvHandle hPluginHeapMemory; + NV_DECLARE_ALIGNED(NvU64 ctrlBuffOffset, 8); + NvBool bDeviceProfilingEnabled; +} NVA084_ALLOC_PARAMETERS; diff --git a/src/common/sdk/nvidia/inc/class/cla084_notification.h b/src/common/sdk/nvidia/inc/class/cla084_notification.h new file mode 100644 index 000000000..da2ec5b5f --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/cla084_notification.h @@ -0,0 +1,53 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cla084_notification_h_ +#define _cla084_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +// +// @todo: We will define the actual event values later based on the use case. +// These event values are only for Test purpose. +// +/* event values */ +#define NVA084_NOTIFIERS_EVENT_VGPU_PLUGIN_TASK_BOOTLOADED (0) +#define NVA084_NOTIFIERS_EVENT_VGPU_PLUGIN_TASK_UNLOADED (1) +#define NVA084_NOTIFIERS_EVENT_VGPU_PLUGIN_TASK_CRASHED (2) +#define NVA084_NOTIFIERS_EVENT_GUEST_DRIVER_LOADED (3) +#define NVA084_NOTIFIERS_EVENT_GUEST_DRIVER_UNLOADED (4) +#define NVA084_NOTIFIERS_MAXCOUNT (5) + +#define NVA084_NOTIFICATION_STATUS_IN_PROGRESS (0x8000) +#define NVA084_NOTIFICATION_STATUS_BAD_ARGUMENT (0x4000) +#define NVA084_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x2000) +#define NVA084_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x1000) +#define NVA084_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cla084_notification_h_ diff --git a/src/common/sdk/nvidia/inc/class/cla097.h b/src/common/sdk/nvidia/inc/class/cla097.h index 2ed72052e..9ebbcfda5 100644 --- a/src/common/sdk/nvidia/inc/class/cla097.h +++ b/src/common/sdk/nvidia/inc/class/cla097.h @@ -1,29 +1,3817 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. -#ifndef _cla097_h_ -#define _cla097_h_ + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_kepler_a_h_ +#define _cl_kepler_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../class/bin/sw_header.pl kepler_a */ + +#include "nvtypes.h" #define KEPLER_A 0xA097 -#endif // _cla097_h_ +#define NVA097_SET_OBJECT 0x0000 +#define NVA097_SET_OBJECT_CLASS_ID 15:0 +#define NVA097_SET_OBJECT_ENGINE_ID 20:16 + +#define NVA097_NO_OPERATION 0x0100 +#define NVA097_NO_OPERATION_V 31:0 + +#define NVA097_SET_NOTIFY_A 0x0104 +#define NVA097_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVA097_SET_NOTIFY_B 0x0108 +#define NVA097_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVA097_NOTIFY 0x010c +#define NVA097_NOTIFY_TYPE 31:0 +#define NVA097_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVA097_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVA097_WAIT_FOR_IDLE 0x0110 +#define NVA097_WAIT_FOR_IDLE_V 31:0 + +#define NVA097_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVA097_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVA097_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVA097_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVA097_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVA097_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVA097_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVA097_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVA097_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVA097_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVA097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVA097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVA097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVA097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVA097_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVA097_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVA097_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVA097_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVA097_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVA097_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVA097_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVA097_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVA097_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA097_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA097_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA097_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA097_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA097_SEND_GO_IDLE 0x013c +#define NVA097_SEND_GO_IDLE_V 31:0 + +#define NVA097_PM_TRIGGER 0x0140 +#define NVA097_PM_TRIGGER_V 31:0 + +#define NVA097_PM_TRIGGER_WFI 0x0144 +#define NVA097_PM_TRIGGER_WFI_V 31:0 + +#define NVA097_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVA097_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVA097_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVA097_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVA097_LINE_LENGTH_IN 0x0180 +#define NVA097_LINE_LENGTH_IN_VALUE 31:0 + +#define NVA097_LINE_COUNT 0x0184 +#define NVA097_LINE_COUNT_VALUE 31:0 + +#define NVA097_OFFSET_OUT_UPPER 0x0188 +#define NVA097_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVA097_OFFSET_OUT 0x018c +#define NVA097_OFFSET_OUT_VALUE 31:0 + +#define NVA097_PITCH_OUT 0x0190 +#define NVA097_PITCH_OUT_VALUE 31:0 + +#define NVA097_SET_DST_BLOCK_SIZE 0x0194 +#define NVA097_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVA097_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA097_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVA097_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA097_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA097_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA097_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA097_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA097_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA097_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVA097_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVA097_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVA097_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVA097_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVA097_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVA097_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVA097_SET_DST_WIDTH 0x0198 +#define NVA097_SET_DST_WIDTH_V 31:0 + +#define NVA097_SET_DST_HEIGHT 0x019c +#define NVA097_SET_DST_HEIGHT_V 31:0 + +#define NVA097_SET_DST_DEPTH 0x01a0 +#define NVA097_SET_DST_DEPTH_V 31:0 + +#define NVA097_SET_DST_LAYER 0x01a4 +#define NVA097_SET_DST_LAYER_V 31:0 + +#define NVA097_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVA097_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVA097_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVA097_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVA097_LAUNCH_DMA 0x01b0 +#define NVA097_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVA097_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVA097_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVA097_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVA097_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVA097_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVA097_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVA097_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVA097_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVA097_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVA097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVA097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVA097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVA097_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVA097_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA097_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA097_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVA097_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA097_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA097_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA097_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVA097_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA097_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVA097_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVA097_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA097_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVA097_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA097_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA097_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVA097_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVA097_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVA097_LOAD_INLINE_DATA 0x01b4 +#define NVA097_LOAD_INLINE_DATA_V 31:0 + +#define NVA097_SET_I2M_SEMAPHORE_A 0x01dc +#define NVA097_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVA097_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVA097_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA097_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVA097_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVA097_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVA097_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVA097_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVA097_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVA097_SET_I2M_SPARE_NOOP03 0x01fc +#define NVA097_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVA097_RUN_DS_NOW 0x0200 +#define NVA097_RUN_DS_NOW_V 31:0 + +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVA097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVA097_SET_RASTER_PIPE_SYNC_CONTROL 0x0208 +#define NVA097_SET_RASTER_PIPE_SYNC_CONTROL_PRIM_AREA_THRESHOLD 21:0 +#define NVA097_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE 24:24 +#define NVA097_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE_FALSE 0x00000000 +#define NVA097_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVA097_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVA097_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVA097_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVA097_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVA097_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVA097_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVA097_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_GS_DM_FIFO 0x0214 +#define NVA097_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVA097_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVA097_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVA097_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVA097_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA097_INVALIDATE_SHADER_CACHES 0x021c +#define NVA097_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVA097_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVA097_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVA097_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVA097_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVA097_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVA097_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVA097_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVA097_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVA097_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVA097_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVA097_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVA097_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVA097_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVA097_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVA097_SET_VAB_VERTEX3F(i) (0x0220+(i)*4) +#define NVA097_SET_VAB_VERTEX3F_V 31:0 + +#define NVA097_SET_VAB_VERTEX4F(i) (0x0230+(i)*4) +#define NVA097_SET_VAB_VERTEX4F_V 31:0 + +#define NVA097_SET_VAB_NORMAL3F(i) (0x0240+(i)*4) +#define NVA097_SET_VAB_NORMAL3F_V 31:0 + +#define NVA097_SET_VAB_COLOR3F(i) (0x0250+(i)*4) +#define NVA097_SET_VAB_COLOR3F_V 31:0 + +#define NVA097_SET_VAB_COLOR4F(i) (0x0260+(i)*4) +#define NVA097_SET_VAB_COLOR4F_V 31:0 + +#define NVA097_SET_VAB_COLOR4UB(i) (0x0270+(i)*4) +#define NVA097_SET_VAB_COLOR4UB_V 31:0 + +#define NVA097_SET_VAB_TEX_COORD1F(i) (0x0280+(i)*4) +#define NVA097_SET_VAB_TEX_COORD1F_V 31:0 + +#define NVA097_SET_VAB_TEX_COORD2F(i) (0x0290+(i)*4) +#define NVA097_SET_VAB_TEX_COORD2F_V 31:0 + +#define NVA097_SET_VAB_TEX_COORD3F(i) (0x02a0+(i)*4) +#define NVA097_SET_VAB_TEX_COORD3F_V 31:0 + +#define NVA097_SET_VAB_TEX_COORD4F(i) (0x02b0+(i)*4) +#define NVA097_SET_VAB_TEX_COORD4F_V 31:0 + +#define NVA097_SET_TASK_CIRCULAR_BUFFER_THROTTLE 0x02cc +#define NVA097_SET_TASK_CIRCULAR_BUFFER_THROTTLE_TASK_COUNT 21:0 + +#define NVA097_SET_PRIM_CIRCULAR_BUFFER_THROTTLE 0x02d0 +#define NVA097_SET_PRIM_CIRCULAR_BUFFER_THROTTLE_PRIM_AREA 21:0 + +#define NVA097_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVA097_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVA097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVA097_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVA097_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 9:0 + +#define NVA097_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVA097_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVA097_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVA097_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVA097_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVA097_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVA097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVA097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVA097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVA097_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVA097_SET_ZCULL_SUBREGION 0x02e8 +#define NVA097_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVA097_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVA097_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVA097_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVA097_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVA097_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVA097_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVA097_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVA097_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVA097_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVA097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVA097_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVA097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVA097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVA097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVA097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVA097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVA097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVA097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVA097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVA097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVA097_DRAW_ZERO_INDEX 0x0304 +#define NVA097_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVA097_SET_L1_CONFIGURATION 0x0308 +#define NVA097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVA097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVA097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVA097_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVA097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVA097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVA097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVA097_SET_SPA_VERSION 0x0310 +#define NVA097_SET_SPA_VERSION_MINOR 7:0 +#define NVA097_SET_SPA_VERSION_MAJOR 15:8 + +#define NVA097_SET_IEEE_CLEAN_UPDATE 0x0314 +#define NVA097_SET_IEEE_CLEAN_UPDATE_ENABLE 0:0 +#define NVA097_SET_IEEE_CLEAN_UPDATE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_IEEE_CLEAN_UPDATE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_SNAP_GRID_LINE 0x0318 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVA097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVA097_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVA097_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVA097_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVA097_SET_SNAP_GRID_NON_LINE 0x031c +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVA097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVA097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVA097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVA097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVA097_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVA097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVA097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVA097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVA097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVA097_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVA097_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVA097_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVA097_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVA097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVA097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVA097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVA097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVA097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVA097_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVA097_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVA097_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVA097_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVA097_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVA097_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVA097_SET_TESSELLATION_LOD_V1 0x0330 +#define NVA097_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVA097_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVA097_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVA097_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVA097_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVA097_RESERVED_TG07 0x033c +#define NVA097_RESERVED_TG07_V 0:0 + +#define NVA097_RESERVED_TG08 0x0340 +#define NVA097_RESERVED_TG08_V 0:0 + +#define NVA097_RESERVED_TG09 0x0344 +#define NVA097_RESERVED_TG09_V 0:0 + +#define NVA097_RESERVED_TG10 0x0348 +#define NVA097_RESERVED_TG10_V 0:0 + +#define NVA097_RESERVED_TG11 0x034c +#define NVA097_RESERVED_TG11_V 0:0 + +#define NVA097_RESERVED_TG12 0x0350 +#define NVA097_RESERVED_TG12_V 0:0 + +#define NVA097_RESERVED_TG13 0x0354 +#define NVA097_RESERVED_TG13_V 0:0 + +#define NVA097_RESERVED_TG14 0x0358 +#define NVA097_RESERVED_TG14_V 0:0 + +#define NVA097_RESERVED_TG15 0x035c +#define NVA097_RESERVED_TG15_V 0:0 + +#define NVA097_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVA097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVA097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVA097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVA097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVA097_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVA097_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVA097_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVA097_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVA097_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVA097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVA097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVA097_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVA097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVA097_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVA097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVA097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVA097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVA097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVA097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVA097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVA097_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVA097_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVA097_SET_RASTER_ENABLE 0x037c +#define NVA097_SET_RASTER_ENABLE_V 0:0 +#define NVA097_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVA097_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVA097_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVA097_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVA097_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVA097_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVA097_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVA097_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVA097_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVA097_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVA097_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVA097_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVA097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVA097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVA097_SET_VAB_DATA_TYPELESS(i) (0x0400+(i)*4) +#define NVA097_SET_VAB_DATA_TYPELESS_V 31:0 + +#define NVA097_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVA097_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVA097_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVA097_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVA097_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVA097_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVA097_SET_RASTER_INPUT 0x0740 +#define NVA097_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVA097_SET_STREAM_OUTPUT 0x0744 +#define NVA097_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVA097_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVA097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVA097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_ALPHA_FRACTION 0x074c +#define NVA097_SET_ALPHA_FRACTION_V 7:0 + +#define NVA097_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVA097_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVA097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVA097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVA097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 + +#define NVA097_SET_MAX_TI_WARPS_PER_BATCH 0x075c +#define NVA097_SET_MAX_TI_WARPS_PER_BATCH_V 5:0 + +#define NVA097_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVA097_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVA097_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVA097_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVA097_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVA097_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVA097_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVA097_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVA097_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVA097_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVA097_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVA097_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVA097_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVA097_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVA097_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVA097_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVA097_SET_ISBE_SAVE_RESTORE_PROGRAM 0x07ac +#define NVA097_SET_ISBE_SAVE_RESTORE_PROGRAM_OFFSET 31:0 + +#define NVA097_SET_VAB_VERTEX2F(i) (0x07b0+(i)*4) +#define NVA097_SET_VAB_VERTEX2F_V 31:0 + +#define NVA097_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVA097_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVA097_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVA097_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVA097_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVA097_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVA097_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVA097_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVA097_SET_CULL_BEFORE_FETCH 0x07dc +#define NVA097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVA097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVA097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVA097_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVA097_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVA097_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVA097_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVA097_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVA097_SET_ZCULL_STORAGE_A 0x07e8 +#define NVA097_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVA097_SET_ZCULL_STORAGE_B 0x07ec +#define NVA097_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVA097_SET_ZCULL_STORAGE_C 0x07f0 +#define NVA097_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVA097_SET_ZCULL_STORAGE_D 0x07f4 +#define NVA097_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVA097_SET_ZT_READ_ONLY 0x07f8 +#define NVA097_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVA097_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVA097_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVA097_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVA097_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVA097_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVA097_SET_TEXTURE_INSTRUCTION_OPERAND 0x07fc +#define NVA097_SET_TEXTURE_INSTRUCTION_OPERAND_ORDERING 0:0 +#define NVA097_SET_TEXTURE_INSTRUCTION_OPERAND_ORDERING_FERMI_ORDER 0x00000000 +#define NVA097_SET_TEXTURE_INSTRUCTION_OPERAND_ORDERING_KEPLER_ORDER 0x00000001 + +#define NVA097_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVA097_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVA097_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVA097_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVA097_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVA097_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVA097_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVA097_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVA097_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVA097_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVA097_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVA097_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVA097_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVA097_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVA097_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVA097_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVA097_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVA097_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVA097_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVA097_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVA097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVA097_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVA097_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVA097_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVA097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVA097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVA097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVA097_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVA097_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVA097_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVA097_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVA097_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVA097_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVA097_SET_COLOR_TARGET_MARK(j) (0x0824+(j)*64) +#define NVA097_SET_COLOR_TARGET_MARK_IEEE_CLEAN 0:0 +#define NVA097_SET_COLOR_TARGET_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVA097_SET_COLOR_TARGET_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVA097_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVA097_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVA097_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVA097_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVA097_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVA097_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVA097_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVA097_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVA097_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVA097_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVA097_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVA097_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVA097_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVA097_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVA097_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVA097_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVA097_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVA097_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVA097_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVA097_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVA097_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVA097_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVA097_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVA097_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVA097_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVA097_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVA097_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVA097_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVA097_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVA097_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVA097_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVA097_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVA097_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVA097_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVA097_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVA097_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVA097_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVA097_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVA097_SET_STATISTICS_COUNTER 0x0d68 +#define NVA097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVA097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVA097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVA097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVA097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVA097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVA097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVA097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVA097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVA097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVA097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVA097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVA097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVA097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVA097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVA097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVA097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVA097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVA097_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVA097_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVA097_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVA097_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVA097_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVA097_SET_VERTEX_ARRAY_START 0x0d74 +#define NVA097_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVA097_DRAW_VERTEX_ARRAY 0x0d78 +#define NVA097_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVA097_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVA097_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVA097_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVA097_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVA097_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVA097_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVA097_SET_Z_CLEAR_VALUE 0x0d90 +#define NVA097_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVA097_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVA097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVA097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVA097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVA097_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVA097_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVA097_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVA097_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVA097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVA097_SET_FRONT_POLYGON_MODE 0x0dac +#define NVA097_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVA097_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVA097_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVA097_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVA097_SET_BACK_POLYGON_MODE 0x0db0 +#define NVA097_SET_BACK_POLYGON_MODE_V 31:0 +#define NVA097_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVA097_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVA097_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVA097_SET_POLY_SMOOTH 0x0db4 +#define NVA097_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVA097_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVA097_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_ZT_MARK 0x0db8 +#define NVA097_SET_ZT_MARK_IEEE_CLEAN 0:0 +#define NVA097_SET_ZT_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVA097_SET_ZT_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVA097_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVA097_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVA097_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVA097_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVA097_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVA097_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVA097_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVA097_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVA097_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVA097_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVA097_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVA097_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVA097_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVA097_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVA097_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVA097_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVA097_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_PATCH 0x0dcc +#define NVA097_SET_PATCH_SIZE 7:0 + +#define NVA097_SET_ZCULL_CRITERION 0x0dd8 +#define NVA097_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVA097_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVA097_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVA097_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVA097_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVA097_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVA097_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVA097_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVA097_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVA097_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVA097_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVA097_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVA097_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVA097_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVA097_SET_ZCULL_CRITERION_SREF 23:16 +#define NVA097_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVA097_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVA097_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVA097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVA097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVA097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVA097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_DRAW_INLINE_VERTEX_VAB_UPDATE 0x0dec +#define NVA097_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE 0:0 +#define NVA097_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_WINDOW_OFFSET_X 0x0df8 +#define NVA097_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVA097_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVA097_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVA097_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVA097_SET_SCISSOR_ENABLE_V 0:0 +#define NVA097_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVA097_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVA097_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVA097_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVA097_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVA097_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVA097_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVA097_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVA097_SET_VAB_NORMAL3S(i) (0x0f00+(i)*4) +#define NVA097_SET_VAB_NORMAL3S_V 31:0 + +#define NVA097_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVA097_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVA097_SET_BACK_STENCIL_MASK 0x0f58 +#define NVA097_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVA097_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVA097_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVA097_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVA097_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVA097_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVA097_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVA097_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVA097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVA097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVA097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVA097_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVA097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVA097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVA097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVA097_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVA097_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVA097_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVA097_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVA097_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVA097_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVA097_SET_CT_MRT_ENABLE 0x0fac +#define NVA097_SET_CT_MRT_ENABLE_V 0:0 +#define NVA097_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVA097_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVA097_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVA097_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVA097_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVA097_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVA097_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVA097_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVA097_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVA097_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVA097_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVA097_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVA097_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVA097_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVA097_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVA097_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVA097_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVA097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVA097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVA097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVA097_SET_ZT_A 0x0fe0 +#define NVA097_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_ZT_B 0x0fe4 +#define NVA097_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_ZT_FORMAT 0x0fe8 +#define NVA097_SET_ZT_FORMAT_V 4:0 +#define NVA097_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVA097_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVA097_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVA097_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVA097_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVA097_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVA097_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVA097_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVA097_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVA097_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVA097_SET_ZT_BLOCK_SIZE 0x0fec +#define NVA097_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVA097_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA097_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVA097_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA097_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA097_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA097_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA097_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA097_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA097_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVA097_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVA097_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVA097_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVA097_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVA097_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVA097_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVA097_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVA097_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVA097_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVA097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA097_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVA097_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVA097_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVA097_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVA097_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVA097_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVA097_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVA097_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVA097_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVA097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVA097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVA097_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVA097_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVA097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVA097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_SPARE_NOOP00 0x1040 +#define NVA097_SET_SPARE_NOOP00_V 31:0 + +#define NVA097_SET_SPARE_NOOP01 0x1044 +#define NVA097_SET_SPARE_NOOP01_V 31:0 + +#define NVA097_SET_SPARE_NOOP02 0x1048 +#define NVA097_SET_SPARE_NOOP02_V 31:0 + +#define NVA097_SET_SPARE_NOOP03 0x104c +#define NVA097_SET_SPARE_NOOP03_V 31:0 + +#define NVA097_SET_SPARE_NOOP04 0x1050 +#define NVA097_SET_SPARE_NOOP04_V 31:0 + +#define NVA097_SET_SPARE_NOOP05 0x1054 +#define NVA097_SET_SPARE_NOOP05_V 31:0 + +#define NVA097_SET_SPARE_NOOP06 0x1058 +#define NVA097_SET_SPARE_NOOP06_V 31:0 + +#define NVA097_SET_SPARE_NOOP07 0x105c +#define NVA097_SET_SPARE_NOOP07_V 31:0 + +#define NVA097_SET_SPARE_NOOP08 0x1060 +#define NVA097_SET_SPARE_NOOP08_V 31:0 + +#define NVA097_SET_SPARE_NOOP09 0x1064 +#define NVA097_SET_SPARE_NOOP09_V 31:0 + +#define NVA097_SET_SPARE_NOOP10 0x1068 +#define NVA097_SET_SPARE_NOOP10_V 31:0 + +#define NVA097_SET_SPARE_NOOP11 0x106c +#define NVA097_SET_SPARE_NOOP11_V 31:0 + +#define NVA097_SET_SPARE_NOOP12 0x1070 +#define NVA097_SET_SPARE_NOOP12_V 31:0 + +#define NVA097_SET_SPARE_NOOP13 0x1074 +#define NVA097_SET_SPARE_NOOP13_V 31:0 + +#define NVA097_SET_SPARE_NOOP14 0x1078 +#define NVA097_SET_SPARE_NOOP14_V 31:0 + +#define NVA097_SET_SPARE_NOOP15 0x107c +#define NVA097_SET_SPARE_NOOP15_V 31:0 + +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVA097_UNBIND_ALL 0x10f4 +#define NVA097_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVA097_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVA097_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVA097_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVA097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA097_NO_OPERATION_DATA_HI 0x110c +#define NVA097_NO_OPERATION_DATA_HI_V 31:0 + +#define NVA097_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVA097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVA097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVA097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVA097_PM_TRIGGER_END 0x1114 +#define NVA097_PM_TRIGGER_END_V 31:0 + +#define NVA097_SET_VERTEX_ID_BASE 0x1118 +#define NVA097_SET_VERTEX_ID_BASE_V 31:0 + +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVA097_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVA097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVA097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVA097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVA097_FLUSH_PENDING_WRITES 0x1144 +#define NVA097_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVA097_SET_VAB_DATA_CONTROL 0x114c +#define NVA097_SET_VAB_DATA_CONTROL_VAB_INDEX 7:0 +#define NVA097_SET_VAB_DATA_CONTROL_COMPONENT_COUNT 10:8 +#define NVA097_SET_VAB_DATA_CONTROL_COMPONENT_BYTE_WIDTH 14:12 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT 18:16 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT_NUM_SNORM 0x00000001 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT_NUM_UNORM 0x00000002 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT_NUM_SINT 0x00000003 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT_NUM_UINT 0x00000004 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT_NUM_USCALED 0x00000005 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT_NUM_SSCALED 0x00000006 +#define NVA097_SET_VAB_DATA_CONTROL_FORMAT_NUM_FLOAT 0x00000007 + +#define NVA097_SET_VAB_DATA(i) (0x1150+(i)*4) +#define NVA097_SET_VAB_DATA_V 31:0 + +#define NVA097_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVA097_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVA097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVA097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVA097_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVA097_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVA097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVA097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVA097_SET_CT_SELECT 0x121c +#define NVA097_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVA097_SET_CT_SELECT_TARGET0 6:4 +#define NVA097_SET_CT_SELECT_TARGET1 9:7 +#define NVA097_SET_CT_SELECT_TARGET2 12:10 +#define NVA097_SET_CT_SELECT_TARGET3 15:13 +#define NVA097_SET_CT_SELECT_TARGET4 18:16 +#define NVA097_SET_CT_SELECT_TARGET5 21:19 +#define NVA097_SET_CT_SELECT_TARGET6 24:22 +#define NVA097_SET_CT_SELECT_TARGET7 27:25 + +#define NVA097_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVA097_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVA097_SET_ZT_SIZE_A 0x1228 +#define NVA097_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVA097_SET_ZT_SIZE_B 0x122c +#define NVA097_SET_ZT_SIZE_B_HEIGHT 16:0 + +#define NVA097_SET_ZT_SIZE_C 0x1230 +#define NVA097_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVA097_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVA097_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVA097_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVA097_SET_SAMPLER_BINDING 0x1234 +#define NVA097_SET_SAMPLER_BINDING_V 0:0 +#define NVA097_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVA097_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVA097_DRAW_AUTO 0x123c +#define NVA097_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVA097_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVA097_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 9:0 + +#define NVA097_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVA097_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVA097_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA097_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVA097_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVA097_SET_SHADER_SCHEDULING 0x12ac +#define NVA097_SET_SHADER_SCHEDULING_MODE 0:0 +#define NVA097_SET_SHADER_SCHEDULING_MODE_OLDEST_THREAD_FIRST 0x00000000 +#define NVA097_SET_SHADER_SCHEDULING_MODE_ROUND_ROBIN 0x00000001 + +#define NVA097_CLEAR_ZCULL_REGION 0x12c8 +#define NVA097_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVA097_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVA097_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVA097_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVA097_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVA097_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVA097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVA097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVA097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVA097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVA097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVA097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVA097_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVA097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVA097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVA097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVA097_SET_DEPTH_TEST 0x12cc +#define NVA097_SET_DEPTH_TEST_ENABLE 0:0 +#define NVA097_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVA097_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_FILL_MODE 0x12d0 +#define NVA097_SET_FILL_MODE_V 31:0 +#define NVA097_SET_FILL_MODE_V_POINT 0x00000001 +#define NVA097_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVA097_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVA097_SET_SHADE_MODE 0x12d4 +#define NVA097_SET_SHADE_MODE_V 31:0 +#define NVA097_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVA097_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVA097_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVA097_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVA097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVA097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVA097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVA097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVA097_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVA097_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVA097_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVA097_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_DEPTH_WRITE 0x12e8 +#define NVA097_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVA097_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_ALPHA_TEST 0x12ec +#define NVA097_SET_ALPHA_TEST_ENABLE 0:0 +#define NVA097_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVA097_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVA097_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVA097_DRAW_INLINE_INDEX4X8 0x1304 +#define NVA097_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVA097_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVA097_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVA097_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVA097_D3D_SET_CULL_MODE 0x1308 +#define NVA097_D3D_SET_CULL_MODE_V 31:0 +#define NVA097_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVA097_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVA097_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVA097_SET_DEPTH_FUNC 0x130c +#define NVA097_SET_DEPTH_FUNC_V 31:0 +#define NVA097_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVA097_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVA097_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVA097_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVA097_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVA097_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVA097_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVA097_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVA097_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVA097_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVA097_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVA097_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVA097_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVA097_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVA097_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVA097_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVA097_SET_ALPHA_REF 0x1310 +#define NVA097_SET_ALPHA_REF_V 31:0 + +#define NVA097_SET_ALPHA_FUNC 0x1314 +#define NVA097_SET_ALPHA_FUNC_V 31:0 +#define NVA097_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVA097_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVA097_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVA097_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVA097_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVA097_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVA097_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVA097_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVA097_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVA097_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVA097_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVA097_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVA097_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVA097_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVA097_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVA097_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVA097_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVA097_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVA097_SET_BLEND_CONST_RED 0x131c +#define NVA097_SET_BLEND_CONST_RED_V 31:0 + +#define NVA097_SET_BLEND_CONST_GREEN 0x1320 +#define NVA097_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVA097_SET_BLEND_CONST_BLUE 0x1324 +#define NVA097_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVA097_SET_BLEND_CONST_ALPHA 0x1328 +#define NVA097_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVA097_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVA097_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVA097_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVA097_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVA097_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVA097_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVA097_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVA097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVA097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVA097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_BLEND_COLOR_OP 0x1340 +#define NVA097_SET_BLEND_COLOR_OP_V 31:0 +#define NVA097_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVA097_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVA097_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVA097_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVA097_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVA097_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVA097_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVA097_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVA097_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVA097_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA097_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA097_SET_BLEND_ALPHA_OP 0x134c +#define NVA097_SET_BLEND_ALPHA_OP_V 31:0 +#define NVA097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVA097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVA097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVA097_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVA097_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVA097_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVA097_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVA097_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVA097_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVA097_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA097_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVA097_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVA097_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVA097_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA097_SET_SINGLE_ROP_CONTROL 0x135c +#define NVA097_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVA097_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVA097_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_BLEND(i) (0x1360+(i)*4) +#define NVA097_SET_BLEND_ENABLE 0:0 +#define NVA097_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVA097_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_STENCIL_TEST 0x1380 +#define NVA097_SET_STENCIL_TEST_ENABLE 0:0 +#define NVA097_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVA097_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_STENCIL_OP_FAIL 0x1384 +#define NVA097_SET_STENCIL_OP_FAIL_V 31:0 +#define NVA097_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVA097_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVA097_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVA097_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVA097_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVA097_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVA097_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVA097_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVA097_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVA097_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVA097_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVA097_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVA097_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVA097_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVA097_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVA097_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVA097_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVA097_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVA097_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVA097_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVA097_SET_STENCIL_OP_ZPASS 0x138c +#define NVA097_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVA097_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVA097_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVA097_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVA097_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVA097_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVA097_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVA097_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVA097_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVA097_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVA097_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVA097_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVA097_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVA097_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVA097_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVA097_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVA097_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVA097_SET_STENCIL_FUNC 0x1390 +#define NVA097_SET_STENCIL_FUNC_V 31:0 +#define NVA097_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVA097_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVA097_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVA097_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVA097_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVA097_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVA097_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVA097_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVA097_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVA097_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVA097_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVA097_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVA097_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVA097_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVA097_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVA097_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVA097_SET_STENCIL_FUNC_REF 0x1394 +#define NVA097_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVA097_SET_STENCIL_FUNC_MASK 0x1398 +#define NVA097_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVA097_SET_STENCIL_MASK 0x139c +#define NVA097_SET_STENCIL_MASK_V 7:0 + +#define NVA097_SET_DRAW_AUTO_START 0x13a4 +#define NVA097_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVA097_SET_PS_SATURATE 0x13a8 +#define NVA097_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVA097_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVA097_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVA097_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVA097_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVA097_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVA097_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVA097_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVA097_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVA097_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVA097_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVA097_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVA097_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVA097_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVA097_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVA097_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVA097_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVA097_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVA097_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVA097_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVA097_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVA097_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVA097_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVA097_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 + +#define NVA097_SET_WINDOW_ORIGIN 0x13ac +#define NVA097_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVA097_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVA097_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVA097_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVA097_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVA097_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVA097_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVA097_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVA097_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVA097_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVA097_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVA097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVA097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_ALPHA_HYSTERESIS 0x1420 +#define NVA097_SET_ALPHA_HYSTERESIS_ROUNDS_OF_ALPHA 7:0 + +#define NVA097_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVA097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVA097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA097_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVA097_INVALIDATE_DA_DMA_CACHE 0x142c +#define NVA097_INVALIDATE_DA_DMA_CACHE_V 0:0 + +#define NVA097_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVA097_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVA097_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVA097_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVA097_SET_PS_WARP_WATERMARKS 0x1450 +#define NVA097_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVA097_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVA097_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVA097_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVA097_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVA097_STORE_ZCULL 0x1464 +#define NVA097_STORE_ZCULL_V 0:0 + +#define NVA097_LOAD_ZCULL 0x1500 +#define NVA097_LOAD_ZCULL_V 0:0 + +#define NVA097_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVA097_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVA097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVA097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVA097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVA097_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVA097_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVA097_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVA097_SET_USER_CLIP_ENABLE 0x1510 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVA097_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVA097_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVA097_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVA097_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_POINT_SIZE 0x1518 +#define NVA097_SET_POINT_SIZE_V 31:0 + +#define NVA097_SET_ZCULL_STATS 0x151c +#define NVA097_SET_ZCULL_STATS_ENABLE 0:0 +#define NVA097_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_POINT_SPRITE 0x1520 +#define NVA097_SET_POINT_SPRITE_ENABLE 0:0 +#define NVA097_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_SHADER_EXCEPTIONS 0x1528 +#define NVA097_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVA097_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVA097_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVA097_CLEAR_REPORT_VALUE 0x1530 +#define NVA097_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVA097_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVA097_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVA097_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVA097_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVA097_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVA097_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVA097_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 + +#define NVA097_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVA097_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVA097_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVA097_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVA097_SET_ZT_SELECT 0x1538 +#define NVA097_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVA097_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVA097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVA097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVA097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVA097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVA097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVA097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVA097_SET_RENDER_ENABLE_A 0x1550 +#define NVA097_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_RENDER_ENABLE_B 0x1554 +#define NVA097_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_RENDER_ENABLE_C 0x1558 +#define NVA097_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVA097_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA097_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA097_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA097_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA097_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA097_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVA097_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVA097_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVA097_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVA097_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVA097_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVA097_SET_ANTI_ALIASED_LINE 0x1570 +#define NVA097_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVA097_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_TEX_HEADER_POOL_A 0x1574 +#define NVA097_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_TEX_HEADER_POOL_B 0x1578 +#define NVA097_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_TEX_HEADER_POOL_C 0x157c +#define NVA097_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVA097_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVA097_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVA097_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVA097_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVA097_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVA097_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVA097_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVA097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVA097_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVA097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVA097_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVA097_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVA097_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVA097_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVA097_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVA097_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVA097_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVA097_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVA097_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVA097_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVA097_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVA097_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVA097_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVA097_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVA097_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVA097_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVA097_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVA097_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVA097_SET_SRGB_WRITE 0x15b8 +#define NVA097_SET_SRGB_WRITE_ENABLE 0:0 +#define NVA097_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_DEPTH_BIAS 0x15bc +#define NVA097_SET_DEPTH_BIAS_V 31:0 + +#define NVA097_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVA097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVA097_SET_RT_LAYER 0x15cc +#define NVA097_SET_RT_LAYER_V 15:0 +#define NVA097_SET_RT_LAYER_CONTROL 16:16 +#define NVA097_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVA097_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVA097_SET_ANTI_ALIAS 0x15d0 +#define NVA097_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVA097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVA097_SET_EDGE_FLAG 0x15e4 +#define NVA097_SET_EDGE_FLAG_V 0:0 +#define NVA097_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVA097_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVA097_DRAW_INLINE_INDEX 0x15e8 +#define NVA097_DRAW_INLINE_INDEX_V 31:0 + +#define NVA097_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVA097_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVA097_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVA097_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVA097_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVA097_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVA097_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVA097_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVA097_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVA097_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVA097_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVA097_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVA097_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVA097_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVA097_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVA097_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVA097_SET_POINT_SPRITE_SELECT 0x1604 +#define NVA097_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVA097_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVA097_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVA097_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVA097_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVA097_SET_PROGRAM_REGION_A 0x1608 +#define NVA097_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVA097_SET_PROGRAM_REGION_B 0x160c +#define NVA097_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVA097_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVA097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVA097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVA097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVA097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVA097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVA097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVA097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVA097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVA097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVA097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVA097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVA097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVA097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVA097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVA097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVA097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVA097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVA097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVA097_END 0x1614 +#define NVA097_END_V 0:0 + +#define NVA097_BEGIN 0x1618 +#define NVA097_BEGIN_OP 15:0 +#define NVA097_BEGIN_OP_POINTS 0x00000000 +#define NVA097_BEGIN_OP_LINES 0x00000001 +#define NVA097_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVA097_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVA097_BEGIN_OP_TRIANGLES 0x00000004 +#define NVA097_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVA097_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVA097_BEGIN_OP_QUADS 0x00000007 +#define NVA097_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVA097_BEGIN_OP_POLYGON 0x00000009 +#define NVA097_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVA097_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVA097_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_BEGIN_OP_PATCH 0x0000000E +#define NVA097_BEGIN_PRIMITIVE_ID 24:24 +#define NVA097_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVA097_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVA097_BEGIN_INSTANCE_ID 27:26 +#define NVA097_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVA097_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVA097_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVA097_BEGIN_SPLIT_MODE 30:29 +#define NVA097_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVA097_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVA097_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVA097_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 + +#define NVA097_SET_VERTEX_ID_COPY 0x161c +#define NVA097_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVA097_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVA097_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVA097_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVA097_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVA097_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVA097_LOAD_PRIMITIVE_ID 0x1624 +#define NVA097_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVA097_SET_SHADER_BASED_CULL 0x162c +#define NVA097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVA097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVA097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVA097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVA097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVA097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_CLASS_VERSION 0x1638 +#define NVA097_SET_CLASS_VERSION_CURRENT 15:0 +#define NVA097_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA097_SET_VAB_PAGE 0x163c +#define NVA097_SET_VAB_PAGE_READ_SELECT 0:0 +#define NVA097_SET_VAB_PAGE_READ_SELECT_PAGES_0_AND_1 0x00000000 +#define NVA097_SET_VAB_PAGE_READ_SELECT_PAGES_0_AND_2 0x00000001 + +#define NVA097_DRAW_INLINE_VERTEX 0x1640 +#define NVA097_DRAW_INLINE_VERTEX_V 31:0 + +#define NVA097_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVA097_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVA097_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVA097_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVA097_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVA097_SET_DA_OUTPUT 0x164c +#define NVA097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVA097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVA097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVA097_SET_ANTI_ALIASED_POINT 0x1658 +#define NVA097_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVA097_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_POINT_CENTER_MODE 0x165c +#define NVA097_SET_POINT_CENTER_MODE_V 31:0 +#define NVA097_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVA097_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVA097_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVA097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVA097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVA097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVA097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVA097_SET_LINE_STIPPLE 0x166c +#define NVA097_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVA097_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVA097_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVA097_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVA097_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVA097_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVA097_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVA097_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVA097_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVA097_SET_PROVOKING_VERTEX 0x1684 +#define NVA097_SET_PROVOKING_VERTEX_V 0:0 +#define NVA097_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVA097_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVA097_SET_TWO_SIDED_LIGHT 0x1688 +#define NVA097_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVA097_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_POLYGON_STIPPLE 0x168c +#define NVA097_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVA097_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_SHADER_CONTROL 0x1690 +#define NVA097_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVA097_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVA097_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVA097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVA097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVA097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVA097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVA097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVA097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVA097_LAUNCH_VERTEX 0x169c +#define NVA097_LAUNCH_VERTEX_V 0:0 + +#define NVA097_CHECK_CLASS_VERSION 0x16a0 +#define NVA097_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVA097_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA097_SET_SPH_VERSION 0x16a4 +#define NVA097_SET_SPH_VERSION_CURRENT 15:0 +#define NVA097_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA097_CHECK_SPH_VERSION 0x16a8 +#define NVA097_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVA097_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA097_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVA097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVA097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVA097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVA097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVA097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVA097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVA097_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVA097_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVA097_SET_AAM_VERSION 0x1790 +#define NVA097_SET_AAM_VERSION_CURRENT 15:0 +#define NVA097_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA097_CHECK_AAM_VERSION 0x1794 +#define NVA097_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVA097_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA097_SET_ZT_LAYER 0x179c +#define NVA097_SET_ZT_LAYER_OFFSET 15:0 + +#define NVA097_SET_VAB_MEMORY_AREA_A 0x17bc +#define NVA097_SET_VAB_MEMORY_AREA_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_VAB_MEMORY_AREA_B 0x17c0 +#define NVA097_SET_VAB_MEMORY_AREA_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_VAB_MEMORY_AREA_C 0x17c4 +#define NVA097_SET_VAB_MEMORY_AREA_C_SIZE 1:0 +#define NVA097_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_64K 0x00000001 +#define NVA097_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_128K 0x00000002 +#define NVA097_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_256K 0x00000003 + +#define NVA097_SET_INDEX_BUFFER_A 0x17c8 +#define NVA097_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVA097_SET_INDEX_BUFFER_B 0x17cc +#define NVA097_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVA097_SET_INDEX_BUFFER_C 0x17d0 +#define NVA097_SET_INDEX_BUFFER_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVA097_SET_INDEX_BUFFER_D 0x17d4 +#define NVA097_SET_INDEX_BUFFER_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVA097_SET_INDEX_BUFFER_E 0x17d8 +#define NVA097_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVA097_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVA097_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVA097_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVA097_SET_INDEX_BUFFER_F 0x17dc +#define NVA097_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVA097_DRAW_INDEX_BUFFER 0x17e0 +#define NVA097_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVA097_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVA097_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVA097_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVA097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVA097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVA097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVA097_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVA097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVA097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVA097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVA097_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVA097_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVA097_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVA097_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVA097_OGL_SET_CULL 0x1918 +#define NVA097_OGL_SET_CULL_ENABLE 0:0 +#define NVA097_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVA097_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVA097_OGL_SET_FRONT_FACE 0x191c +#define NVA097_OGL_SET_FRONT_FACE_V 31:0 +#define NVA097_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVA097_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVA097_OGL_SET_CULL_FACE 0x1920 +#define NVA097_OGL_SET_CULL_FACE_V 31:0 +#define NVA097_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVA097_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVA097_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVA097_SET_VIEWPORT_PIXEL 0x1924 +#define NVA097_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVA097_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVA097_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVA097_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVA097_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVA097_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVA097_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVA097_INVALIDATE_CONSTANT_BUFFER_CACHE 0x1930 +#define NVA097_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2 0:0 +#define NVA097_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_FALSE 0x00000000 +#define NVA097_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_TRUE 0x00000001 + +#define NVA097_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVA097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVA097_SET_USER_CLIP_OP 0x1940 +#define NVA097_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVA097_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVA097_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVA097_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVA097_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVA097_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVA097_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVA097_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVA097_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVA097_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVA097_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVA097_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVA097_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVA097_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVA097_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVA097_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVA097_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVA097_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVA097_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVA097_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVA097_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVA097_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVA097_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVA097_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVA097_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVA097_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVA097_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVA097_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVA097_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVA097_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVA097_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVA097_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVA097_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVA097_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVA097_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVA097_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVA097_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVA097_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVA097_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVA097_INVALIDATE_ZCULL 0x1958 +#define NVA097_INVALIDATE_ZCULL_V 31:0 +#define NVA097_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVA097_SET_ZCULL 0x1968 +#define NVA097_SET_ZCULL_Z_ENABLE 0:0 +#define NVA097_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVA097_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVA097_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_ZCULL_BOUNDS 0x196c +#define NVA097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVA097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVA097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVA097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVA097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVA097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVA097_ZCULL_SYNC 0x1978 +#define NVA097_ZCULL_SYNC_V 31:0 + +#define NVA097_SET_CLIP_ID_TEST 0x197c +#define NVA097_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVA097_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVA097_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVA097_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVA097_SET_CLIP_ID 0x1984 +#define NVA097_SET_CLIP_ID_V 31:0 + +#define NVA097_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVA097_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVA097_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVA097_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVA097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVA097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVA097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVA097_SET_LOGIC_OP 0x19c4 +#define NVA097_SET_LOGIC_OP_ENABLE 0:0 +#define NVA097_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVA097_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_LOGIC_OP_FUNC 0x19c8 +#define NVA097_SET_LOGIC_OP_FUNC_V 31:0 +#define NVA097_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVA097_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVA097_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVA097_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVA097_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVA097_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVA097_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVA097_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVA097_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVA097_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVA097_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVA097_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVA097_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVA097_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVA097_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVA097_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVA097_SET_Z_COMPRESSION 0x19cc +#define NVA097_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVA097_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVA097_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVA097_CLEAR_SURFACE 0x19d0 +#define NVA097_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVA097_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVA097_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVA097_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVA097_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVA097_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVA097_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVA097_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVA097_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVA097_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVA097_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVA097_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVA097_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVA097_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVA097_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVA097_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVA097_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVA097_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVA097_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVA097_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVA097_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVA097_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVA097_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVA097_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVA097_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVA097_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVA097_SET_CT_WRITE_R_ENABLE 0:0 +#define NVA097_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVA097_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVA097_SET_CT_WRITE_G_ENABLE 4:4 +#define NVA097_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVA097_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVA097_SET_CT_WRITE_B_ENABLE 8:8 +#define NVA097_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVA097_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVA097_SET_CT_WRITE_A_ENABLE 12:12 +#define NVA097_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVA097_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVA097_PIPE_NOP 0x1a2c +#define NVA097_PIPE_NOP_V 31:0 + +#define NVA097_SET_SPARE00 0x1a30 +#define NVA097_SET_SPARE00_V 31:0 + +#define NVA097_SET_SPARE01 0x1a34 +#define NVA097_SET_SPARE01_V 31:0 + +#define NVA097_SET_SPARE02 0x1a38 +#define NVA097_SET_SPARE02_V 31:0 + +#define NVA097_SET_SPARE03 0x1a3c +#define NVA097_SET_SPARE03_V 31:0 + +#define NVA097_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVA097_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVA097_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVA097_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA097_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVA097_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVA097_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVA097_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVA097_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVA097_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVA097_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVA097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVA097_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVA097_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVA097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVA097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVA097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVA097_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVA097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVA097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVA097_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVA097_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVA097_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVA097_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVA097_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVA097_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVA097_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVA097_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVA097_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVA097_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVA097_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVA097_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVA097_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVA097_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVA097_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVA097_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVA097_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVA097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVA097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVA097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVA097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA097_SET_VERTEX_STREAM_LIMIT_A_A(j) (0x1f00+(j)*8) +#define NVA097_SET_VERTEX_STREAM_LIMIT_A_A_UPPER 7:0 + +#define NVA097_SET_VERTEX_STREAM_LIMIT_A_B(j) (0x1f04+(j)*8) +#define NVA097_SET_VERTEX_STREAM_LIMIT_A_B_LOWER 31:0 + +#define NVA097_SET_VERTEX_STREAM_LIMIT_B_A(j) (0x1f80+(j)*8) +#define NVA097_SET_VERTEX_STREAM_LIMIT_B_A_UPPER 7:0 + +#define NVA097_SET_VERTEX_STREAM_LIMIT_B_B(j) (0x1f84+(j)*8) +#define NVA097_SET_VERTEX_STREAM_LIMIT_B_B_LOWER 31:0 + +#define NVA097_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVA097_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVA097_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVA097_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVA097_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVA097_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVA097_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVA097_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVA097_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVA097_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVA097_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVA097_SET_PIPELINE_PROGRAM(j) (0x2004+(j)*64) +#define NVA097_SET_PIPELINE_PROGRAM_OFFSET 31:0 + +#define NVA097_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVA097_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVA097_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVA097_SET_PIPELINE_REGISTER_COUNT_V 7:0 + +#define NVA097_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVA097_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVA097_SET_PIPELINE_RESERVED_B(j) (0x2014+(j)*64) +#define NVA097_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVA097_SET_PIPELINE_RESERVED_C(j) (0x2018+(j)*64) +#define NVA097_SET_PIPELINE_RESERVED_C_V 0:0 + +#define NVA097_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVA097_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVA097_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVA097_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVA097_SET_FALCON00 0x2300 +#define NVA097_SET_FALCON00_V 31:0 + +#define NVA097_SET_FALCON01 0x2304 +#define NVA097_SET_FALCON01_V 31:0 + +#define NVA097_SET_FALCON02 0x2308 +#define NVA097_SET_FALCON02_V 31:0 + +#define NVA097_SET_FALCON03 0x230c +#define NVA097_SET_FALCON03_V 31:0 + +#define NVA097_SET_FALCON04 0x2310 +#define NVA097_SET_FALCON04_V 31:0 + +#define NVA097_SET_FALCON05 0x2314 +#define NVA097_SET_FALCON05_V 31:0 + +#define NVA097_SET_FALCON06 0x2318 +#define NVA097_SET_FALCON06_V 31:0 + +#define NVA097_SET_FALCON07 0x231c +#define NVA097_SET_FALCON07_V 31:0 + +#define NVA097_SET_FALCON08 0x2320 +#define NVA097_SET_FALCON08_V 31:0 + +#define NVA097_SET_FALCON09 0x2324 +#define NVA097_SET_FALCON09_V 31:0 + +#define NVA097_SET_FALCON10 0x2328 +#define NVA097_SET_FALCON10_V 31:0 + +#define NVA097_SET_FALCON11 0x232c +#define NVA097_SET_FALCON11_V 31:0 + +#define NVA097_SET_FALCON12 0x2330 +#define NVA097_SET_FALCON12_V 31:0 + +#define NVA097_SET_FALCON13 0x2334 +#define NVA097_SET_FALCON13_V 31:0 + +#define NVA097_SET_FALCON14 0x2338 +#define NVA097_SET_FALCON14_V 31:0 + +#define NVA097_SET_FALCON15 0x233c +#define NVA097_SET_FALCON15_V 31:0 + +#define NVA097_SET_FALCON16 0x2340 +#define NVA097_SET_FALCON16_V 31:0 + +#define NVA097_SET_FALCON17 0x2344 +#define NVA097_SET_FALCON17_V 31:0 + +#define NVA097_SET_FALCON18 0x2348 +#define NVA097_SET_FALCON18_V 31:0 + +#define NVA097_SET_FALCON19 0x234c +#define NVA097_SET_FALCON19_V 31:0 + +#define NVA097_SET_FALCON20 0x2350 +#define NVA097_SET_FALCON20_V 31:0 + +#define NVA097_SET_FALCON21 0x2354 +#define NVA097_SET_FALCON21_V 31:0 + +#define NVA097_SET_FALCON22 0x2358 +#define NVA097_SET_FALCON22_V 31:0 + +#define NVA097_SET_FALCON23 0x235c +#define NVA097_SET_FALCON23_V 31:0 + +#define NVA097_SET_FALCON24 0x2360 +#define NVA097_SET_FALCON24_V 31:0 + +#define NVA097_SET_FALCON25 0x2364 +#define NVA097_SET_FALCON25_V 31:0 + +#define NVA097_SET_FALCON26 0x2368 +#define NVA097_SET_FALCON26_V 31:0 + +#define NVA097_SET_FALCON27 0x236c +#define NVA097_SET_FALCON27_V 31:0 + +#define NVA097_SET_FALCON28 0x2370 +#define NVA097_SET_FALCON28_V 31:0 + +#define NVA097_SET_FALCON29 0x2374 +#define NVA097_SET_FALCON29_V 31:0 + +#define NVA097_SET_FALCON30 0x2378 +#define NVA097_SET_FALCON30_V 31:0 + +#define NVA097_SET_FALCON31 0x237c +#define NVA097_SET_FALCON31_V 31:0 + +#define NVA097_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVA097_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVA097_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVA097_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVA097_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVA097_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVA097_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVA097_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVA097_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVA097_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVA097_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVA097_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVA097_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVA097_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVA097_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVA097_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVA097_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVA097_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVA097_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVA097_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVA097_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVA097_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVA097_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVA097_SET_COLOR_CLAMP 0x2600 +#define NVA097_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVA097_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVA097_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVA097_NOOP_X_X_X_SET_VALVE 0x2604 +#define NVA097_NOOP_X_X_X_SET_VALVE_HIGHER_PRIORITY 0:0 +#define NVA097_NOOP_X_X_X_SET_VALVE_HIGHER_PRIORITY_COMPUTE 0x00000000 +#define NVA097_NOOP_X_X_X_SET_VALVE_HIGHER_PRIORITY_GRAPHICS 0x00000001 + +#define NVA097_SET_BINDLESS_TEXTURE 0x2608 +#define NVA097_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 4:0 + +#define NVA097_SET_TRAP_HANDLER 0x260c +#define NVA097_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVA097_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVA097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVA097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVA097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVA097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVA097_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVA097_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVA097_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVA097_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVA097_CALL_MME_MACRO_V 31:0 + +#define NVA097_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVA097_CALL_MME_DATA_V 31:0 + +#endif /* _cl_kepler_a_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/cla197.h b/src/common/sdk/nvidia/inc/class/cla197.h index 8e4edbebd..deae603a7 100644 --- a/src/common/sdk/nvidia/inc/class/cla197.h +++ b/src/common/sdk/nvidia/inc/class/cla197.h @@ -1,29 +1,3826 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. -#ifndef _cla197_h_ -#define _cla197_h_ + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_kepler_b_h_ +#define _cl_kepler_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../class/bin/sw_header.pl kepler_b */ + +#include "nvtypes.h" #define KEPLER_B 0xA197 -#endif // _cla197_h_ +#define NVA197_SET_OBJECT 0x0000 +#define NVA197_SET_OBJECT_CLASS_ID 15:0 +#define NVA197_SET_OBJECT_ENGINE_ID 20:16 + +#define NVA197_NO_OPERATION 0x0100 +#define NVA197_NO_OPERATION_V 31:0 + +#define NVA197_SET_NOTIFY_A 0x0104 +#define NVA197_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVA197_SET_NOTIFY_B 0x0108 +#define NVA197_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVA197_NOTIFY 0x010c +#define NVA197_NOTIFY_TYPE 31:0 +#define NVA197_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVA197_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVA197_WAIT_FOR_IDLE 0x0110 +#define NVA197_WAIT_FOR_IDLE_V 31:0 + +#define NVA197_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVA197_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVA197_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVA197_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVA197_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVA197_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVA197_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVA197_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVA197_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVA197_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVA197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVA197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVA197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVA197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVA197_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVA197_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVA197_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVA197_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVA197_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVA197_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVA197_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVA197_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVA197_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA197_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA197_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA197_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA197_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA197_SEND_GO_IDLE 0x013c +#define NVA197_SEND_GO_IDLE_V 31:0 + +#define NVA197_PM_TRIGGER 0x0140 +#define NVA197_PM_TRIGGER_V 31:0 + +#define NVA197_PM_TRIGGER_WFI 0x0144 +#define NVA197_PM_TRIGGER_WFI_V 31:0 + +#define NVA197_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVA197_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVA197_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVA197_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVA197_LINE_LENGTH_IN 0x0180 +#define NVA197_LINE_LENGTH_IN_VALUE 31:0 + +#define NVA197_LINE_COUNT 0x0184 +#define NVA197_LINE_COUNT_VALUE 31:0 + +#define NVA197_OFFSET_OUT_UPPER 0x0188 +#define NVA197_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVA197_OFFSET_OUT 0x018c +#define NVA197_OFFSET_OUT_VALUE 31:0 + +#define NVA197_PITCH_OUT 0x0190 +#define NVA197_PITCH_OUT_VALUE 31:0 + +#define NVA197_SET_DST_BLOCK_SIZE 0x0194 +#define NVA197_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVA197_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA197_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVA197_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA197_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA197_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA197_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA197_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA197_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA197_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVA197_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVA197_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVA197_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVA197_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVA197_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVA197_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVA197_SET_DST_WIDTH 0x0198 +#define NVA197_SET_DST_WIDTH_V 31:0 + +#define NVA197_SET_DST_HEIGHT 0x019c +#define NVA197_SET_DST_HEIGHT_V 31:0 + +#define NVA197_SET_DST_DEPTH 0x01a0 +#define NVA197_SET_DST_DEPTH_V 31:0 + +#define NVA197_SET_DST_LAYER 0x01a4 +#define NVA197_SET_DST_LAYER_V 31:0 + +#define NVA197_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVA197_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVA197_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVA197_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVA197_LAUNCH_DMA 0x01b0 +#define NVA197_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVA197_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVA197_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVA197_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVA197_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVA197_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVA197_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVA197_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVA197_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVA197_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVA197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVA197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVA197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVA197_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVA197_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA197_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA197_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVA197_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA197_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA197_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA197_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVA197_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA197_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVA197_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVA197_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA197_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVA197_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA197_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA197_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVA197_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVA197_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVA197_LOAD_INLINE_DATA 0x01b4 +#define NVA197_LOAD_INLINE_DATA_V 31:0 + +#define NVA197_SET_I2M_SEMAPHORE_A 0x01dc +#define NVA197_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVA197_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVA197_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA197_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVA197_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVA197_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVA197_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVA197_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVA197_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVA197_SET_I2M_SPARE_NOOP03 0x01fc +#define NVA197_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVA197_RUN_DS_NOW 0x0200 +#define NVA197_RUN_DS_NOW_V 31:0 + +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVA197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVA197_SET_RASTER_PIPE_SYNC_CONTROL 0x0208 +#define NVA197_SET_RASTER_PIPE_SYNC_CONTROL_PRIM_AREA_THRESHOLD 21:0 +#define NVA197_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE 24:24 +#define NVA197_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE_FALSE 0x00000000 +#define NVA197_SET_RASTER_PIPE_SYNC_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVA197_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVA197_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVA197_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVA197_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVA197_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVA197_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVA197_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_GS_DM_FIFO 0x0214 +#define NVA197_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVA197_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVA197_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVA197_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVA197_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA197_INVALIDATE_SHADER_CACHES 0x021c +#define NVA197_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVA197_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVA197_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVA197_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVA197_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVA197_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVA197_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVA197_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVA197_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVA197_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVA197_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVA197_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVA197_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVA197_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVA197_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVA197_SET_VAB_VERTEX3F(i) (0x0220+(i)*4) +#define NVA197_SET_VAB_VERTEX3F_V 31:0 + +#define NVA197_SET_VAB_VERTEX4F(i) (0x0230+(i)*4) +#define NVA197_SET_VAB_VERTEX4F_V 31:0 + +#define NVA197_SET_VAB_NORMAL3F(i) (0x0240+(i)*4) +#define NVA197_SET_VAB_NORMAL3F_V 31:0 + +#define NVA197_SET_VAB_COLOR3F(i) (0x0250+(i)*4) +#define NVA197_SET_VAB_COLOR3F_V 31:0 + +#define NVA197_SET_VAB_COLOR4F(i) (0x0260+(i)*4) +#define NVA197_SET_VAB_COLOR4F_V 31:0 + +#define NVA197_SET_VAB_COLOR4UB(i) (0x0270+(i)*4) +#define NVA197_SET_VAB_COLOR4UB_V 31:0 + +#define NVA197_SET_VAB_TEX_COORD1F(i) (0x0280+(i)*4) +#define NVA197_SET_VAB_TEX_COORD1F_V 31:0 + +#define NVA197_SET_VAB_TEX_COORD2F(i) (0x0290+(i)*4) +#define NVA197_SET_VAB_TEX_COORD2F_V 31:0 + +#define NVA197_SET_VAB_TEX_COORD3F(i) (0x02a0+(i)*4) +#define NVA197_SET_VAB_TEX_COORD3F_V 31:0 + +#define NVA197_SET_VAB_TEX_COORD4F(i) (0x02b0+(i)*4) +#define NVA197_SET_VAB_TEX_COORD4F_V 31:0 + +#define NVA197_SET_GLOBAL_LOAD_VIA_TEXTURE 0x02c4 +#define NVA197_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE 0:0 +#define NVA197_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE_TRUE 0x00000001 +#define NVA197_SET_GLOBAL_LOAD_VIA_TEXTURE_HEADER_INDEX 23:4 + +#define NVA197_SET_TASK_CIRCULAR_BUFFER_THROTTLE 0x02cc +#define NVA197_SET_TASK_CIRCULAR_BUFFER_THROTTLE_TASK_COUNT 21:0 + +#define NVA197_SET_PRIM_CIRCULAR_BUFFER_THROTTLE 0x02d0 +#define NVA197_SET_PRIM_CIRCULAR_BUFFER_THROTTLE_PRIM_AREA 21:0 + +#define NVA197_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVA197_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVA197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVA197_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVA197_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 9:0 + +#define NVA197_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVA197_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVA197_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVA197_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVA197_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVA197_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVA197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVA197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVA197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVA197_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVA197_SET_ZCULL_SUBREGION 0x02e8 +#define NVA197_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVA197_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVA197_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVA197_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVA197_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVA197_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVA197_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVA197_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVA197_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVA197_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVA197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVA197_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVA197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVA197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVA197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVA197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVA197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVA197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVA197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVA197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVA197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVA197_DRAW_ZERO_INDEX 0x0304 +#define NVA197_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVA197_SET_L1_CONFIGURATION 0x0308 +#define NVA197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVA197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVA197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVA197_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVA197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVA197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVA197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVA197_SET_SPA_VERSION 0x0310 +#define NVA197_SET_SPA_VERSION_MINOR 7:0 +#define NVA197_SET_SPA_VERSION_MAJOR 15:8 + +#define NVA197_SET_IEEE_CLEAN_UPDATE 0x0314 +#define NVA197_SET_IEEE_CLEAN_UPDATE_ENABLE 0:0 +#define NVA197_SET_IEEE_CLEAN_UPDATE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_IEEE_CLEAN_UPDATE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_SNAP_GRID_LINE 0x0318 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVA197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVA197_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVA197_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVA197_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVA197_SET_SNAP_GRID_NON_LINE 0x031c +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVA197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVA197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVA197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVA197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVA197_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVA197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVA197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVA197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVA197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVA197_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVA197_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVA197_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVA197_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVA197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVA197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVA197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVA197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVA197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVA197_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVA197_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVA197_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVA197_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVA197_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVA197_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVA197_SET_TESSELLATION_LOD_V1 0x0330 +#define NVA197_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVA197_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVA197_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVA197_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVA197_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVA197_RESERVED_TG07 0x033c +#define NVA197_RESERVED_TG07_V 0:0 + +#define NVA197_RESERVED_TG08 0x0340 +#define NVA197_RESERVED_TG08_V 0:0 + +#define NVA197_RESERVED_TG09 0x0344 +#define NVA197_RESERVED_TG09_V 0:0 + +#define NVA197_RESERVED_TG10 0x0348 +#define NVA197_RESERVED_TG10_V 0:0 + +#define NVA197_RESERVED_TG11 0x034c +#define NVA197_RESERVED_TG11_V 0:0 + +#define NVA197_RESERVED_TG12 0x0350 +#define NVA197_RESERVED_TG12_V 0:0 + +#define NVA197_RESERVED_TG13 0x0354 +#define NVA197_RESERVED_TG13_V 0:0 + +#define NVA197_RESERVED_TG14 0x0358 +#define NVA197_RESERVED_TG14_V 0:0 + +#define NVA197_RESERVED_TG15 0x035c +#define NVA197_RESERVED_TG15_V 0:0 + +#define NVA197_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVA197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVA197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVA197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVA197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVA197_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVA197_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVA197_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVA197_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVA197_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVA197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVA197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVA197_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVA197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVA197_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVA197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVA197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVA197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVA197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVA197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVA197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVA197_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVA197_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVA197_SET_RASTER_ENABLE 0x037c +#define NVA197_SET_RASTER_ENABLE_V 0:0 +#define NVA197_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVA197_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVA197_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVA197_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVA197_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVA197_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVA197_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVA197_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVA197_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVA197_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVA197_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVA197_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVA197_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVA197_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVA197_SET_VAB_DATA_TYPELESS(i) (0x0400+(i)*4) +#define NVA197_SET_VAB_DATA_TYPELESS_V 31:0 + +#define NVA197_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVA197_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVA197_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVA197_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVA197_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVA197_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVA197_SET_RASTER_INPUT 0x0740 +#define NVA197_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVA197_SET_STREAM_OUTPUT 0x0744 +#define NVA197_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVA197_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVA197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVA197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_ALPHA_FRACTION 0x074c +#define NVA197_SET_ALPHA_FRACTION_V 7:0 + +#define NVA197_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVA197_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVA197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVA197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVA197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 + +#define NVA197_SET_MAX_TI_WARPS_PER_BATCH 0x075c +#define NVA197_SET_MAX_TI_WARPS_PER_BATCH_V 5:0 + +#define NVA197_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVA197_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVA197_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVA197_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVA197_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVA197_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVA197_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVA197_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVA197_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVA197_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVA197_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVA197_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVA197_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVA197_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVA197_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVA197_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVA197_SET_ISBE_SAVE_RESTORE_PROGRAM 0x07ac +#define NVA197_SET_ISBE_SAVE_RESTORE_PROGRAM_OFFSET 31:0 + +#define NVA197_SET_VAB_VERTEX2F(i) (0x07b0+(i)*4) +#define NVA197_SET_VAB_VERTEX2F_V 31:0 + +#define NVA197_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVA197_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVA197_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVA197_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVA197_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVA197_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVA197_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVA197_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVA197_SET_CULL_BEFORE_FETCH 0x07dc +#define NVA197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVA197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVA197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVA197_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVA197_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVA197_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVA197_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVA197_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVA197_SET_ZCULL_STORAGE_A 0x07e8 +#define NVA197_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVA197_SET_ZCULL_STORAGE_B 0x07ec +#define NVA197_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVA197_SET_ZCULL_STORAGE_C 0x07f0 +#define NVA197_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVA197_SET_ZCULL_STORAGE_D 0x07f4 +#define NVA197_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVA197_SET_ZT_READ_ONLY 0x07f8 +#define NVA197_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVA197_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVA197_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVA197_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVA197_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVA197_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVA197_SET_TEXTURE_INSTRUCTION_OPERAND 0x07fc +#define NVA197_SET_TEXTURE_INSTRUCTION_OPERAND_ORDERING 0:0 +#define NVA197_SET_TEXTURE_INSTRUCTION_OPERAND_ORDERING_FERMI_ORDER 0x00000000 +#define NVA197_SET_TEXTURE_INSTRUCTION_OPERAND_ORDERING_KEPLER_ORDER 0x00000001 + +#define NVA197_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVA197_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVA197_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVA197_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVA197_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVA197_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVA197_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVA197_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVA197_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVA197_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVA197_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVA197_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVA197_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVA197_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVA197_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVA197_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVA197_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVA197_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVA197_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVA197_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVA197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVA197_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVA197_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVA197_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVA197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVA197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVA197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVA197_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVA197_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVA197_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVA197_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVA197_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVA197_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVA197_SET_COLOR_TARGET_MARK(j) (0x0824+(j)*64) +#define NVA197_SET_COLOR_TARGET_MARK_IEEE_CLEAN 0:0 +#define NVA197_SET_COLOR_TARGET_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVA197_SET_COLOR_TARGET_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVA197_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVA197_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVA197_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVA197_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVA197_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVA197_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVA197_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVA197_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVA197_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVA197_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVA197_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVA197_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVA197_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVA197_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVA197_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVA197_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVA197_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVA197_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVA197_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVA197_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVA197_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVA197_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVA197_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVA197_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVA197_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVA197_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVA197_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVA197_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVA197_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVA197_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVA197_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVA197_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVA197_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVA197_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVA197_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVA197_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVA197_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVA197_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVA197_SET_STATISTICS_COUNTER 0x0d68 +#define NVA197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVA197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVA197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVA197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVA197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVA197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVA197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVA197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVA197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVA197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVA197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVA197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVA197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVA197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVA197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVA197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVA197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVA197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVA197_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVA197_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVA197_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVA197_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVA197_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVA197_SET_VERTEX_ARRAY_START 0x0d74 +#define NVA197_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVA197_DRAW_VERTEX_ARRAY 0x0d78 +#define NVA197_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVA197_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVA197_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVA197_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVA197_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVA197_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVA197_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVA197_SET_Z_CLEAR_VALUE 0x0d90 +#define NVA197_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVA197_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVA197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVA197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVA197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVA197_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVA197_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVA197_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVA197_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVA197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVA197_SET_FRONT_POLYGON_MODE 0x0dac +#define NVA197_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVA197_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVA197_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVA197_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVA197_SET_BACK_POLYGON_MODE 0x0db0 +#define NVA197_SET_BACK_POLYGON_MODE_V 31:0 +#define NVA197_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVA197_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVA197_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVA197_SET_POLY_SMOOTH 0x0db4 +#define NVA197_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVA197_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVA197_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_ZT_MARK 0x0db8 +#define NVA197_SET_ZT_MARK_IEEE_CLEAN 0:0 +#define NVA197_SET_ZT_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVA197_SET_ZT_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVA197_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVA197_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVA197_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVA197_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVA197_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVA197_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVA197_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVA197_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVA197_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVA197_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVA197_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVA197_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVA197_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVA197_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVA197_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVA197_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVA197_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_PATCH 0x0dcc +#define NVA197_SET_PATCH_SIZE 7:0 + +#define NVA197_SET_ZCULL_CRITERION 0x0dd8 +#define NVA197_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVA197_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVA197_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVA197_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVA197_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVA197_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVA197_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVA197_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVA197_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVA197_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVA197_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVA197_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVA197_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVA197_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVA197_SET_ZCULL_CRITERION_SREF 23:16 +#define NVA197_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVA197_SET_SM_QUADRANT_SELECTION_CONTROL 0x0ddc +#define NVA197_SET_SM_QUADRANT_SELECTION_CONTROL_MAX_PIXEL_WARPS 7:0 + +#define NVA197_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVA197_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVA197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVA197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVA197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVA197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_DRAW_INLINE_VERTEX_VAB_UPDATE 0x0dec +#define NVA197_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE 0:0 +#define NVA197_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_DRAW_INLINE_VERTEX_VAB_UPDATE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_WINDOW_OFFSET_X 0x0df8 +#define NVA197_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVA197_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVA197_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVA197_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVA197_SET_SCISSOR_ENABLE_V 0:0 +#define NVA197_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVA197_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVA197_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVA197_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVA197_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVA197_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVA197_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVA197_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVA197_SET_VAB_NORMAL3S(i) (0x0f00+(i)*4) +#define NVA197_SET_VAB_NORMAL3S_V 31:0 + +#define NVA197_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVA197_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVA197_SET_BACK_STENCIL_MASK 0x0f58 +#define NVA197_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVA197_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVA197_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVA197_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVA197_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVA197_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVA197_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVA197_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVA197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVA197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVA197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVA197_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVA197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVA197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVA197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVA197_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVA197_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVA197_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVA197_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVA197_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVA197_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVA197_SET_CT_MRT_ENABLE 0x0fac +#define NVA197_SET_CT_MRT_ENABLE_V 0:0 +#define NVA197_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVA197_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVA197_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVA197_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVA197_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVA197_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVA197_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVA197_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVA197_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVA197_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVA197_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVA197_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVA197_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVA197_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVA197_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVA197_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVA197_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVA197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVA197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVA197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVA197_SET_ZT_A 0x0fe0 +#define NVA197_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_ZT_B 0x0fe4 +#define NVA197_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_ZT_FORMAT 0x0fe8 +#define NVA197_SET_ZT_FORMAT_V 4:0 +#define NVA197_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVA197_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVA197_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVA197_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVA197_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVA197_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVA197_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVA197_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVA197_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVA197_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVA197_SET_ZT_BLOCK_SIZE 0x0fec +#define NVA197_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVA197_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA197_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVA197_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA197_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA197_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA197_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA197_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA197_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA197_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVA197_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVA197_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVA197_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVA197_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVA197_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVA197_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVA197_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVA197_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVA197_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVA197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA197_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVA197_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVA197_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVA197_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVA197_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVA197_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVA197_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVA197_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVA197_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVA197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVA197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVA197_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVA197_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVA197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVA197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_SPARE_NOOP00 0x1040 +#define NVA197_SET_SPARE_NOOP00_V 31:0 + +#define NVA197_SET_SPARE_NOOP01 0x1044 +#define NVA197_SET_SPARE_NOOP01_V 31:0 + +#define NVA197_SET_SPARE_NOOP02 0x1048 +#define NVA197_SET_SPARE_NOOP02_V 31:0 + +#define NVA197_SET_SPARE_NOOP03 0x104c +#define NVA197_SET_SPARE_NOOP03_V 31:0 + +#define NVA197_SET_SPARE_NOOP04 0x1050 +#define NVA197_SET_SPARE_NOOP04_V 31:0 + +#define NVA197_SET_SPARE_NOOP05 0x1054 +#define NVA197_SET_SPARE_NOOP05_V 31:0 + +#define NVA197_SET_SPARE_NOOP06 0x1058 +#define NVA197_SET_SPARE_NOOP06_V 31:0 + +#define NVA197_SET_SPARE_NOOP07 0x105c +#define NVA197_SET_SPARE_NOOP07_V 31:0 + +#define NVA197_SET_SPARE_NOOP08 0x1060 +#define NVA197_SET_SPARE_NOOP08_V 31:0 + +#define NVA197_SET_SPARE_NOOP09 0x1064 +#define NVA197_SET_SPARE_NOOP09_V 31:0 + +#define NVA197_SET_SPARE_NOOP10 0x1068 +#define NVA197_SET_SPARE_NOOP10_V 31:0 + +#define NVA197_SET_SPARE_NOOP11 0x106c +#define NVA197_SET_SPARE_NOOP11_V 31:0 + +#define NVA197_SET_SPARE_NOOP12 0x1070 +#define NVA197_SET_SPARE_NOOP12_V 31:0 + +#define NVA197_SET_SPARE_NOOP13 0x1074 +#define NVA197_SET_SPARE_NOOP13_V 31:0 + +#define NVA197_SET_SPARE_NOOP14 0x1078 +#define NVA197_SET_SPARE_NOOP14_V 31:0 + +#define NVA197_SET_SPARE_NOOP15 0x107c +#define NVA197_SET_SPARE_NOOP15_V 31:0 + +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVA197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVA197_UNBIND_ALL 0x10f4 +#define NVA197_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVA197_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVA197_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVA197_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVA197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA197_NO_OPERATION_DATA_HI 0x110c +#define NVA197_NO_OPERATION_DATA_HI_V 31:0 + +#define NVA197_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVA197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVA197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVA197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVA197_PM_TRIGGER_END 0x1114 +#define NVA197_PM_TRIGGER_END_V 31:0 + +#define NVA197_SET_VERTEX_ID_BASE 0x1118 +#define NVA197_SET_VERTEX_ID_BASE_V 31:0 + +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVA197_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVA197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVA197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVA197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVA197_FLUSH_PENDING_WRITES 0x1144 +#define NVA197_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVA197_SET_VAB_DATA_CONTROL 0x114c +#define NVA197_SET_VAB_DATA_CONTROL_VAB_INDEX 7:0 +#define NVA197_SET_VAB_DATA_CONTROL_COMPONENT_COUNT 10:8 +#define NVA197_SET_VAB_DATA_CONTROL_COMPONENT_BYTE_WIDTH 14:12 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT 18:16 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT_NUM_SNORM 0x00000001 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT_NUM_UNORM 0x00000002 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT_NUM_SINT 0x00000003 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT_NUM_UINT 0x00000004 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT_NUM_USCALED 0x00000005 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT_NUM_SSCALED 0x00000006 +#define NVA197_SET_VAB_DATA_CONTROL_FORMAT_NUM_FLOAT 0x00000007 + +#define NVA197_SET_VAB_DATA(i) (0x1150+(i)*4) +#define NVA197_SET_VAB_DATA_V 31:0 + +#define NVA197_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVA197_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVA197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVA197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVA197_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVA197_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVA197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVA197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVA197_SET_CT_SELECT 0x121c +#define NVA197_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVA197_SET_CT_SELECT_TARGET0 6:4 +#define NVA197_SET_CT_SELECT_TARGET1 9:7 +#define NVA197_SET_CT_SELECT_TARGET2 12:10 +#define NVA197_SET_CT_SELECT_TARGET3 15:13 +#define NVA197_SET_CT_SELECT_TARGET4 18:16 +#define NVA197_SET_CT_SELECT_TARGET5 21:19 +#define NVA197_SET_CT_SELECT_TARGET6 24:22 +#define NVA197_SET_CT_SELECT_TARGET7 27:25 + +#define NVA197_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVA197_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVA197_SET_ZT_SIZE_A 0x1228 +#define NVA197_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVA197_SET_ZT_SIZE_B 0x122c +#define NVA197_SET_ZT_SIZE_B_HEIGHT 16:0 + +#define NVA197_SET_ZT_SIZE_C 0x1230 +#define NVA197_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVA197_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVA197_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVA197_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVA197_SET_SAMPLER_BINDING 0x1234 +#define NVA197_SET_SAMPLER_BINDING_V 0:0 +#define NVA197_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVA197_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVA197_DRAW_AUTO 0x123c +#define NVA197_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVA197_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVA197_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 9:0 + +#define NVA197_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVA197_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVA197_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA197_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVA197_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVA197_SET_SHADER_SCHEDULING 0x12ac +#define NVA197_SET_SHADER_SCHEDULING_MODE 0:0 +#define NVA197_SET_SHADER_SCHEDULING_MODE_OLDEST_THREAD_FIRST 0x00000000 +#define NVA197_SET_SHADER_SCHEDULING_MODE_ROUND_ROBIN 0x00000001 + +#define NVA197_CLEAR_ZCULL_REGION 0x12c8 +#define NVA197_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVA197_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVA197_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVA197_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVA197_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVA197_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVA197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVA197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVA197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVA197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVA197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVA197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVA197_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVA197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVA197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVA197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVA197_SET_DEPTH_TEST 0x12cc +#define NVA197_SET_DEPTH_TEST_ENABLE 0:0 +#define NVA197_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVA197_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_FILL_MODE 0x12d0 +#define NVA197_SET_FILL_MODE_V 31:0 +#define NVA197_SET_FILL_MODE_V_POINT 0x00000001 +#define NVA197_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVA197_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVA197_SET_SHADE_MODE 0x12d4 +#define NVA197_SET_SHADE_MODE_V 31:0 +#define NVA197_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVA197_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVA197_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVA197_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVA197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVA197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVA197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVA197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVA197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVA197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVA197_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVA197_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVA197_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVA197_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_DEPTH_WRITE 0x12e8 +#define NVA197_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVA197_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_ALPHA_TEST 0x12ec +#define NVA197_SET_ALPHA_TEST_ENABLE 0:0 +#define NVA197_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVA197_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVA197_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVA197_DRAW_INLINE_INDEX4X8 0x1304 +#define NVA197_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVA197_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVA197_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVA197_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVA197_D3D_SET_CULL_MODE 0x1308 +#define NVA197_D3D_SET_CULL_MODE_V 31:0 +#define NVA197_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVA197_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVA197_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVA197_SET_DEPTH_FUNC 0x130c +#define NVA197_SET_DEPTH_FUNC_V 31:0 +#define NVA197_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVA197_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVA197_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVA197_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVA197_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVA197_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVA197_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVA197_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVA197_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVA197_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVA197_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVA197_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVA197_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVA197_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVA197_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVA197_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVA197_SET_ALPHA_REF 0x1310 +#define NVA197_SET_ALPHA_REF_V 31:0 + +#define NVA197_SET_ALPHA_FUNC 0x1314 +#define NVA197_SET_ALPHA_FUNC_V 31:0 +#define NVA197_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVA197_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVA197_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVA197_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVA197_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVA197_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVA197_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVA197_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVA197_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVA197_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVA197_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVA197_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVA197_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVA197_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVA197_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVA197_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVA197_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVA197_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVA197_SET_BLEND_CONST_RED 0x131c +#define NVA197_SET_BLEND_CONST_RED_V 31:0 + +#define NVA197_SET_BLEND_CONST_GREEN 0x1320 +#define NVA197_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVA197_SET_BLEND_CONST_BLUE 0x1324 +#define NVA197_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVA197_SET_BLEND_CONST_ALPHA 0x1328 +#define NVA197_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVA197_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVA197_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVA197_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVA197_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVA197_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVA197_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVA197_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVA197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVA197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVA197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_BLEND_COLOR_OP 0x1340 +#define NVA197_SET_BLEND_COLOR_OP_V 31:0 +#define NVA197_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVA197_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVA197_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVA197_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVA197_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVA197_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVA197_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVA197_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVA197_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVA197_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA197_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA197_SET_BLEND_ALPHA_OP 0x134c +#define NVA197_SET_BLEND_ALPHA_OP_V 31:0 +#define NVA197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVA197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVA197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVA197_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVA197_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVA197_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVA197_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVA197_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVA197_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVA197_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA197_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVA197_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVA197_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVA197_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA197_SET_SINGLE_ROP_CONTROL 0x135c +#define NVA197_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVA197_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVA197_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_BLEND(i) (0x1360+(i)*4) +#define NVA197_SET_BLEND_ENABLE 0:0 +#define NVA197_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVA197_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_STENCIL_TEST 0x1380 +#define NVA197_SET_STENCIL_TEST_ENABLE 0:0 +#define NVA197_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVA197_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_STENCIL_OP_FAIL 0x1384 +#define NVA197_SET_STENCIL_OP_FAIL_V 31:0 +#define NVA197_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVA197_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVA197_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVA197_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVA197_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVA197_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVA197_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVA197_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVA197_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVA197_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVA197_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVA197_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVA197_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVA197_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVA197_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVA197_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVA197_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVA197_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVA197_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVA197_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVA197_SET_STENCIL_OP_ZPASS 0x138c +#define NVA197_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVA197_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVA197_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVA197_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVA197_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVA197_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVA197_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVA197_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVA197_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVA197_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVA197_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVA197_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVA197_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVA197_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVA197_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVA197_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVA197_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVA197_SET_STENCIL_FUNC 0x1390 +#define NVA197_SET_STENCIL_FUNC_V 31:0 +#define NVA197_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVA197_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVA197_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVA197_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVA197_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVA197_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVA197_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVA197_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVA197_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVA197_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVA197_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVA197_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVA197_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVA197_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVA197_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVA197_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVA197_SET_STENCIL_FUNC_REF 0x1394 +#define NVA197_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVA197_SET_STENCIL_FUNC_MASK 0x1398 +#define NVA197_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVA197_SET_STENCIL_MASK 0x139c +#define NVA197_SET_STENCIL_MASK_V 7:0 + +#define NVA197_SET_DRAW_AUTO_START 0x13a4 +#define NVA197_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVA197_SET_PS_SATURATE 0x13a8 +#define NVA197_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVA197_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVA197_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVA197_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVA197_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVA197_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVA197_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVA197_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVA197_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVA197_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVA197_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVA197_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVA197_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVA197_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVA197_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVA197_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVA197_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVA197_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVA197_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVA197_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVA197_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVA197_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVA197_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVA197_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 + +#define NVA197_SET_WINDOW_ORIGIN 0x13ac +#define NVA197_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVA197_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVA197_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVA197_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVA197_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVA197_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVA197_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVA197_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVA197_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVA197_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVA197_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVA197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVA197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_ALPHA_HYSTERESIS 0x1420 +#define NVA197_SET_ALPHA_HYSTERESIS_ROUNDS_OF_ALPHA 7:0 + +#define NVA197_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVA197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVA197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA197_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVA197_INVALIDATE_DA_DMA_CACHE 0x142c +#define NVA197_INVALIDATE_DA_DMA_CACHE_V 0:0 + +#define NVA197_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVA197_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVA197_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVA197_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVA197_SET_PS_WARP_WATERMARKS 0x1450 +#define NVA197_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVA197_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVA197_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVA197_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVA197_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVA197_STORE_ZCULL 0x1464 +#define NVA197_STORE_ZCULL_V 0:0 + +#define NVA197_LOAD_ZCULL 0x1500 +#define NVA197_LOAD_ZCULL_V 0:0 + +#define NVA197_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVA197_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVA197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVA197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVA197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVA197_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVA197_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVA197_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVA197_SET_USER_CLIP_ENABLE 0x1510 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVA197_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVA197_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVA197_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVA197_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_POINT_SIZE 0x1518 +#define NVA197_SET_POINT_SIZE_V 31:0 + +#define NVA197_SET_ZCULL_STATS 0x151c +#define NVA197_SET_ZCULL_STATS_ENABLE 0:0 +#define NVA197_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_POINT_SPRITE 0x1520 +#define NVA197_SET_POINT_SPRITE_ENABLE 0:0 +#define NVA197_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_SHADER_EXCEPTIONS 0x1528 +#define NVA197_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVA197_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVA197_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVA197_CLEAR_REPORT_VALUE 0x1530 +#define NVA197_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVA197_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVA197_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVA197_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVA197_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVA197_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVA197_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVA197_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 + +#define NVA197_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVA197_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVA197_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVA197_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVA197_SET_ZT_SELECT 0x1538 +#define NVA197_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVA197_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVA197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVA197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVA197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVA197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVA197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVA197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVA197_SET_RENDER_ENABLE_A 0x1550 +#define NVA197_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_RENDER_ENABLE_B 0x1554 +#define NVA197_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_RENDER_ENABLE_C 0x1558 +#define NVA197_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVA197_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA197_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA197_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA197_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA197_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA197_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVA197_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVA197_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVA197_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVA197_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVA197_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVA197_SET_ANTI_ALIASED_LINE 0x1570 +#define NVA197_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVA197_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_TEX_HEADER_POOL_A 0x1574 +#define NVA197_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_TEX_HEADER_POOL_B 0x1578 +#define NVA197_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_TEX_HEADER_POOL_C 0x157c +#define NVA197_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVA197_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVA197_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVA197_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVA197_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVA197_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVA197_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVA197_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVA197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVA197_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVA197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVA197_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVA197_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVA197_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVA197_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVA197_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVA197_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVA197_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVA197_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVA197_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVA197_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVA197_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVA197_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVA197_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVA197_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVA197_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVA197_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVA197_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVA197_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVA197_SET_SRGB_WRITE 0x15b8 +#define NVA197_SET_SRGB_WRITE_ENABLE 0:0 +#define NVA197_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_DEPTH_BIAS 0x15bc +#define NVA197_SET_DEPTH_BIAS_V 31:0 + +#define NVA197_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVA197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVA197_SET_RT_LAYER 0x15cc +#define NVA197_SET_RT_LAYER_V 15:0 +#define NVA197_SET_RT_LAYER_CONTROL 16:16 +#define NVA197_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVA197_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVA197_SET_ANTI_ALIAS 0x15d0 +#define NVA197_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVA197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVA197_SET_EDGE_FLAG 0x15e4 +#define NVA197_SET_EDGE_FLAG_V 0:0 +#define NVA197_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVA197_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVA197_DRAW_INLINE_INDEX 0x15e8 +#define NVA197_DRAW_INLINE_INDEX_V 31:0 + +#define NVA197_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVA197_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVA197_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVA197_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVA197_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVA197_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVA197_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVA197_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVA197_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVA197_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVA197_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVA197_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVA197_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVA197_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVA197_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVA197_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVA197_SET_POINT_SPRITE_SELECT 0x1604 +#define NVA197_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVA197_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVA197_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVA197_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVA197_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVA197_SET_PROGRAM_REGION_A 0x1608 +#define NVA197_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVA197_SET_PROGRAM_REGION_B 0x160c +#define NVA197_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVA197_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVA197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVA197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVA197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVA197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVA197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVA197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVA197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVA197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVA197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVA197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVA197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVA197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVA197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVA197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVA197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVA197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVA197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVA197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVA197_END 0x1614 +#define NVA197_END_V 0:0 + +#define NVA197_BEGIN 0x1618 +#define NVA197_BEGIN_OP 15:0 +#define NVA197_BEGIN_OP_POINTS 0x00000000 +#define NVA197_BEGIN_OP_LINES 0x00000001 +#define NVA197_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVA197_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVA197_BEGIN_OP_TRIANGLES 0x00000004 +#define NVA197_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVA197_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVA197_BEGIN_OP_QUADS 0x00000007 +#define NVA197_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVA197_BEGIN_OP_POLYGON 0x00000009 +#define NVA197_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVA197_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVA197_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_BEGIN_OP_PATCH 0x0000000E +#define NVA197_BEGIN_PRIMITIVE_ID 24:24 +#define NVA197_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVA197_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVA197_BEGIN_INSTANCE_ID 27:26 +#define NVA197_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVA197_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVA197_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVA197_BEGIN_SPLIT_MODE 30:29 +#define NVA197_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVA197_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVA197_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVA197_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 + +#define NVA197_SET_VERTEX_ID_COPY 0x161c +#define NVA197_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVA197_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVA197_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVA197_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVA197_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVA197_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVA197_LOAD_PRIMITIVE_ID 0x1624 +#define NVA197_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVA197_SET_SHADER_BASED_CULL 0x162c +#define NVA197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVA197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVA197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVA197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVA197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVA197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_CLASS_VERSION 0x1638 +#define NVA197_SET_CLASS_VERSION_CURRENT 15:0 +#define NVA197_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA197_SET_VAB_PAGE 0x163c +#define NVA197_SET_VAB_PAGE_READ_SELECT 0:0 +#define NVA197_SET_VAB_PAGE_READ_SELECT_PAGES_0_AND_1 0x00000000 +#define NVA197_SET_VAB_PAGE_READ_SELECT_PAGES_0_AND_2 0x00000001 + +#define NVA197_DRAW_INLINE_VERTEX 0x1640 +#define NVA197_DRAW_INLINE_VERTEX_V 31:0 + +#define NVA197_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVA197_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVA197_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVA197_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVA197_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVA197_SET_DA_OUTPUT 0x164c +#define NVA197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVA197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVA197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVA197_SET_ANTI_ALIASED_POINT 0x1658 +#define NVA197_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVA197_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_POINT_CENTER_MODE 0x165c +#define NVA197_SET_POINT_CENTER_MODE_V 31:0 +#define NVA197_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVA197_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVA197_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVA197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVA197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVA197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVA197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVA197_SET_LINE_STIPPLE 0x166c +#define NVA197_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVA197_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVA197_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVA197_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVA197_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVA197_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVA197_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVA197_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVA197_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVA197_SET_PROVOKING_VERTEX 0x1684 +#define NVA197_SET_PROVOKING_VERTEX_V 0:0 +#define NVA197_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVA197_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVA197_SET_TWO_SIDED_LIGHT 0x1688 +#define NVA197_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVA197_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_POLYGON_STIPPLE 0x168c +#define NVA197_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVA197_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_SHADER_CONTROL 0x1690 +#define NVA197_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVA197_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVA197_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVA197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVA197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVA197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVA197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVA197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVA197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVA197_LAUNCH_VERTEX 0x169c +#define NVA197_LAUNCH_VERTEX_V 0:0 + +#define NVA197_CHECK_CLASS_VERSION 0x16a0 +#define NVA197_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVA197_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA197_SET_SPH_VERSION 0x16a4 +#define NVA197_SET_SPH_VERSION_CURRENT 15:0 +#define NVA197_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA197_CHECK_SPH_VERSION 0x16a8 +#define NVA197_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVA197_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA197_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVA197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVA197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVA197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVA197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVA197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVA197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVA197_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVA197_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVA197_SET_AAM_VERSION 0x1790 +#define NVA197_SET_AAM_VERSION_CURRENT 15:0 +#define NVA197_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA197_CHECK_AAM_VERSION 0x1794 +#define NVA197_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVA197_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA197_SET_ZT_LAYER 0x179c +#define NVA197_SET_ZT_LAYER_OFFSET 15:0 + +#define NVA197_SET_VAB_MEMORY_AREA_A 0x17bc +#define NVA197_SET_VAB_MEMORY_AREA_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_VAB_MEMORY_AREA_B 0x17c0 +#define NVA197_SET_VAB_MEMORY_AREA_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_VAB_MEMORY_AREA_C 0x17c4 +#define NVA197_SET_VAB_MEMORY_AREA_C_SIZE 1:0 +#define NVA197_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_64K 0x00000001 +#define NVA197_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_128K 0x00000002 +#define NVA197_SET_VAB_MEMORY_AREA_C_SIZE_BYTES_256K 0x00000003 + +#define NVA197_SET_INDEX_BUFFER_A 0x17c8 +#define NVA197_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVA197_SET_INDEX_BUFFER_B 0x17cc +#define NVA197_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVA197_SET_INDEX_BUFFER_C 0x17d0 +#define NVA197_SET_INDEX_BUFFER_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVA197_SET_INDEX_BUFFER_D 0x17d4 +#define NVA197_SET_INDEX_BUFFER_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVA197_SET_INDEX_BUFFER_E 0x17d8 +#define NVA197_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVA197_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVA197_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVA197_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVA197_SET_INDEX_BUFFER_F 0x17dc +#define NVA197_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVA197_DRAW_INDEX_BUFFER 0x17e0 +#define NVA197_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVA197_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVA197_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVA197_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVA197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVA197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVA197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVA197_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVA197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVA197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVA197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVA197_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVA197_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVA197_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVA197_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVA197_OGL_SET_CULL 0x1918 +#define NVA197_OGL_SET_CULL_ENABLE 0:0 +#define NVA197_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVA197_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVA197_OGL_SET_FRONT_FACE 0x191c +#define NVA197_OGL_SET_FRONT_FACE_V 31:0 +#define NVA197_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVA197_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVA197_OGL_SET_CULL_FACE 0x1920 +#define NVA197_OGL_SET_CULL_FACE_V 31:0 +#define NVA197_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVA197_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVA197_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVA197_SET_VIEWPORT_PIXEL 0x1924 +#define NVA197_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVA197_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVA197_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVA197_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVA197_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVA197_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVA197_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVA197_INVALIDATE_CONSTANT_BUFFER_CACHE 0x1930 +#define NVA197_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2 0:0 +#define NVA197_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_FALSE 0x00000000 +#define NVA197_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_TRUE 0x00000001 + +#define NVA197_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVA197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVA197_SET_USER_CLIP_OP 0x1940 +#define NVA197_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVA197_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVA197_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVA197_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVA197_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVA197_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVA197_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVA197_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVA197_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVA197_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVA197_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVA197_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVA197_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVA197_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVA197_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVA197_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVA197_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVA197_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVA197_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVA197_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVA197_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVA197_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVA197_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVA197_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVA197_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVA197_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVA197_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVA197_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVA197_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVA197_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVA197_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVA197_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVA197_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVA197_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVA197_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVA197_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVA197_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVA197_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVA197_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVA197_INVALIDATE_ZCULL 0x1958 +#define NVA197_INVALIDATE_ZCULL_V 31:0 +#define NVA197_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVA197_SET_ZCULL 0x1968 +#define NVA197_SET_ZCULL_Z_ENABLE 0:0 +#define NVA197_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVA197_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVA197_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_ZCULL_BOUNDS 0x196c +#define NVA197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVA197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVA197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVA197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVA197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVA197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVA197_ZCULL_SYNC 0x1978 +#define NVA197_ZCULL_SYNC_V 31:0 + +#define NVA197_SET_CLIP_ID_TEST 0x197c +#define NVA197_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVA197_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVA197_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVA197_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVA197_SET_CLIP_ID 0x1984 +#define NVA197_SET_CLIP_ID_V 31:0 + +#define NVA197_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVA197_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVA197_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVA197_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVA197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVA197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVA197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVA197_SET_LOGIC_OP 0x19c4 +#define NVA197_SET_LOGIC_OP_ENABLE 0:0 +#define NVA197_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVA197_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_LOGIC_OP_FUNC 0x19c8 +#define NVA197_SET_LOGIC_OP_FUNC_V 31:0 +#define NVA197_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVA197_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVA197_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVA197_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVA197_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVA197_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVA197_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVA197_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVA197_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVA197_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVA197_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVA197_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVA197_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVA197_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVA197_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVA197_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVA197_SET_Z_COMPRESSION 0x19cc +#define NVA197_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVA197_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVA197_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVA197_CLEAR_SURFACE 0x19d0 +#define NVA197_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVA197_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVA197_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVA197_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVA197_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVA197_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVA197_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVA197_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVA197_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVA197_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVA197_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVA197_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVA197_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVA197_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVA197_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVA197_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVA197_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVA197_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVA197_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVA197_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVA197_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVA197_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVA197_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVA197_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVA197_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVA197_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVA197_SET_CT_WRITE_R_ENABLE 0:0 +#define NVA197_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVA197_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVA197_SET_CT_WRITE_G_ENABLE 4:4 +#define NVA197_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVA197_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVA197_SET_CT_WRITE_B_ENABLE 8:8 +#define NVA197_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVA197_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVA197_SET_CT_WRITE_A_ENABLE 12:12 +#define NVA197_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVA197_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVA197_PIPE_NOP 0x1a2c +#define NVA197_PIPE_NOP_V 31:0 + +#define NVA197_SET_SPARE00 0x1a30 +#define NVA197_SET_SPARE00_V 31:0 + +#define NVA197_SET_SPARE01 0x1a34 +#define NVA197_SET_SPARE01_V 31:0 + +#define NVA197_SET_SPARE02 0x1a38 +#define NVA197_SET_SPARE02_V 31:0 + +#define NVA197_SET_SPARE03 0x1a3c +#define NVA197_SET_SPARE03_V 31:0 + +#define NVA197_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVA197_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVA197_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVA197_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA197_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVA197_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVA197_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVA197_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVA197_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVA197_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVA197_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVA197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVA197_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVA197_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVA197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVA197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVA197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVA197_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVA197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVA197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVA197_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVA197_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVA197_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVA197_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVA197_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVA197_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVA197_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVA197_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVA197_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVA197_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVA197_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVA197_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVA197_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVA197_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVA197_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVA197_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVA197_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVA197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVA197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVA197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVA197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVA197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVA197_SET_VERTEX_STREAM_LIMIT_A_A(j) (0x1f00+(j)*8) +#define NVA197_SET_VERTEX_STREAM_LIMIT_A_A_UPPER 7:0 + +#define NVA197_SET_VERTEX_STREAM_LIMIT_A_B(j) (0x1f04+(j)*8) +#define NVA197_SET_VERTEX_STREAM_LIMIT_A_B_LOWER 31:0 + +#define NVA197_SET_VERTEX_STREAM_LIMIT_B_A(j) (0x1f80+(j)*8) +#define NVA197_SET_VERTEX_STREAM_LIMIT_B_A_UPPER 7:0 + +#define NVA197_SET_VERTEX_STREAM_LIMIT_B_B(j) (0x1f84+(j)*8) +#define NVA197_SET_VERTEX_STREAM_LIMIT_B_B_LOWER 31:0 + +#define NVA197_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVA197_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVA197_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVA197_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVA197_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVA197_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVA197_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVA197_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVA197_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVA197_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVA197_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVA197_SET_PIPELINE_PROGRAM(j) (0x2004+(j)*64) +#define NVA197_SET_PIPELINE_PROGRAM_OFFSET 31:0 + +#define NVA197_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVA197_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVA197_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVA197_SET_PIPELINE_REGISTER_COUNT_V 7:0 + +#define NVA197_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVA197_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVA197_SET_PIPELINE_RESERVED_B(j) (0x2014+(j)*64) +#define NVA197_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVA197_SET_PIPELINE_RESERVED_C(j) (0x2018+(j)*64) +#define NVA197_SET_PIPELINE_RESERVED_C_V 0:0 + +#define NVA197_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVA197_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVA197_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVA197_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVA197_SET_FALCON00 0x2300 +#define NVA197_SET_FALCON00_V 31:0 + +#define NVA197_SET_FALCON01 0x2304 +#define NVA197_SET_FALCON01_V 31:0 + +#define NVA197_SET_FALCON02 0x2308 +#define NVA197_SET_FALCON02_V 31:0 + +#define NVA197_SET_FALCON03 0x230c +#define NVA197_SET_FALCON03_V 31:0 + +#define NVA197_SET_FALCON04 0x2310 +#define NVA197_SET_FALCON04_V 31:0 + +#define NVA197_SET_FALCON05 0x2314 +#define NVA197_SET_FALCON05_V 31:0 + +#define NVA197_SET_FALCON06 0x2318 +#define NVA197_SET_FALCON06_V 31:0 + +#define NVA197_SET_FALCON07 0x231c +#define NVA197_SET_FALCON07_V 31:0 + +#define NVA197_SET_FALCON08 0x2320 +#define NVA197_SET_FALCON08_V 31:0 + +#define NVA197_SET_FALCON09 0x2324 +#define NVA197_SET_FALCON09_V 31:0 + +#define NVA197_SET_FALCON10 0x2328 +#define NVA197_SET_FALCON10_V 31:0 + +#define NVA197_SET_FALCON11 0x232c +#define NVA197_SET_FALCON11_V 31:0 + +#define NVA197_SET_FALCON12 0x2330 +#define NVA197_SET_FALCON12_V 31:0 + +#define NVA197_SET_FALCON13 0x2334 +#define NVA197_SET_FALCON13_V 31:0 + +#define NVA197_SET_FALCON14 0x2338 +#define NVA197_SET_FALCON14_V 31:0 + +#define NVA197_SET_FALCON15 0x233c +#define NVA197_SET_FALCON15_V 31:0 + +#define NVA197_SET_FALCON16 0x2340 +#define NVA197_SET_FALCON16_V 31:0 + +#define NVA197_SET_FALCON17 0x2344 +#define NVA197_SET_FALCON17_V 31:0 + +#define NVA197_SET_FALCON18 0x2348 +#define NVA197_SET_FALCON18_V 31:0 + +#define NVA197_SET_FALCON19 0x234c +#define NVA197_SET_FALCON19_V 31:0 + +#define NVA197_SET_FALCON20 0x2350 +#define NVA197_SET_FALCON20_V 31:0 + +#define NVA197_SET_FALCON21 0x2354 +#define NVA197_SET_FALCON21_V 31:0 + +#define NVA197_SET_FALCON22 0x2358 +#define NVA197_SET_FALCON22_V 31:0 + +#define NVA197_SET_FALCON23 0x235c +#define NVA197_SET_FALCON23_V 31:0 + +#define NVA197_SET_FALCON24 0x2360 +#define NVA197_SET_FALCON24_V 31:0 + +#define NVA197_SET_FALCON25 0x2364 +#define NVA197_SET_FALCON25_V 31:0 + +#define NVA197_SET_FALCON26 0x2368 +#define NVA197_SET_FALCON26_V 31:0 + +#define NVA197_SET_FALCON27 0x236c +#define NVA197_SET_FALCON27_V 31:0 + +#define NVA197_SET_FALCON28 0x2370 +#define NVA197_SET_FALCON28_V 31:0 + +#define NVA197_SET_FALCON29 0x2374 +#define NVA197_SET_FALCON29_V 31:0 + +#define NVA197_SET_FALCON30 0x2378 +#define NVA197_SET_FALCON30_V 31:0 + +#define NVA197_SET_FALCON31 0x237c +#define NVA197_SET_FALCON31_V 31:0 + +#define NVA197_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVA197_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVA197_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVA197_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVA197_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVA197_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVA197_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVA197_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVA197_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVA197_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVA197_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVA197_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVA197_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVA197_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVA197_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVA197_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVA197_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVA197_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVA197_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVA197_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVA197_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVA197_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVA197_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVA197_SET_COLOR_CLAMP 0x2600 +#define NVA197_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVA197_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVA197_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVA197_NOOP_X_X_X_SET_VALVE 0x2604 +#define NVA197_NOOP_X_X_X_SET_VALVE_HIGHER_PRIORITY 0:0 +#define NVA197_NOOP_X_X_X_SET_VALVE_HIGHER_PRIORITY_COMPUTE 0x00000000 +#define NVA197_NOOP_X_X_X_SET_VALVE_HIGHER_PRIORITY_GRAPHICS 0x00000001 + +#define NVA197_SET_BINDLESS_TEXTURE 0x2608 +#define NVA197_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 4:0 + +#define NVA197_SET_TRAP_HANDLER 0x260c +#define NVA197_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVA197_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVA197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVA197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVA197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVA197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVA197_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVA197_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVA197_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVA197_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVA197_CALL_MME_MACRO_V 31:0 + +#define NVA197_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVA197_CALL_MME_DATA_V 31:0 + +#endif /* _cl_kepler_b_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/cla26f.h b/src/common/sdk/nvidia/inc/class/cla26f.h new file mode 100644 index 000000000..807c5cf1c --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/cla26f.h @@ -0,0 +1,254 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cla26f_h_ +#define _cla26f_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvtypes.h" + +/* class KEPLER_CHANNEL_GPFIFO */ +/* + * Documentation for KEPLER_CHANNEL_GPFIFO can be found in dev_pbdma.ref, + * chapter "User Control Registers". It is documented as device NV_UDMA. + * The GPFIFO format itself is also documented in dev_pbdma.ref, + * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, + * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. + * + */ +#define KEPLER_CHANNEL_GPFIFO_C (0x0000A26F) + +/* pio method data structure */ +typedef volatile struct _cla26f_tag0 { + NvV32 Reserved00[0x7c0]; +} NvA26FTypedef, KEPLER_ChannelGPFifoC; +#define NVA26F_TYPEDEF KEPLER_CHANNELChannelGPFifo +/* dma flow control data structure */ +typedef volatile struct _cla26f_tag1 { + NvU32 Ignored00[0x010]; /* 0000-003f*/ + NvU32 Put; /* put offset, read/write 0040-0043*/ + NvU32 Get; /* get offset, read only 0044-0047*/ + NvU32 Reference; /* reference value, read only 0048-004b*/ + NvU32 PutHi; /* high order put offset bits 004c-004f*/ + NvU32 Ignored01[0x002]; /* 0050-0057*/ + NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ + NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ + NvU32 GetHi; /* high order get offset bits 0060-0063*/ + NvU32 Ignored02[0x007]; /* 0064-007f*/ + NvU32 Ignored03; /* used to be engine yield 0080-0083*/ + NvU32 Ignored04[0x001]; /* 0084-0087*/ + NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ + NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ + NvU32 Ignored05[0x5c]; +} NvA26FControl, KeplerCControlGPFifo; +/* fields and values */ +#define NVA26F_NUMBER_OF_SUBCHANNELS (8) +#define NVA26F_SET_OBJECT (0x00000000) +#define NVA26F_SET_OBJECT_NVCLASS 15:0 +#define NVA26F_SET_OBJECT_ENGINE 20:16 +#define NVA26F_SET_OBJECT_ENGINE_SW 0x0000001f +#define NVA26F_ILLEGAL (0x00000004) +#define NVA26F_ILLEGAL_HANDLE 31:0 +#define NVA26F_NOP (0x00000008) +#define NVA26F_NOP_HANDLE 31:0 +#define NVA26F_SEMAPHOREA (0x00000010) +#define NVA26F_SEMAPHOREA_OFFSET_UPPER 7:0 +#define NVA26F_SEMAPHOREB (0x00000014) +#define NVA26F_SEMAPHOREB_OFFSET_LOWER 31:2 +#define NVA26F_SEMAPHOREC (0x00000018) +#define NVA26F_SEMAPHOREC_PAYLOAD 31:0 +#define NVA26F_SEMAPHORED (0x0000001C) +#define NVA26F_SEMAPHORED_OPERATION 3:0 +#define NVA26F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 +#define NVA26F_SEMAPHORED_OPERATION_RELEASE 0x00000002 +#define NVA26F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NVA26F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 +#define NVA26F_SEMAPHORED_ACQUIRE_SWITCH 12:12 +#define NVA26F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 +#define NVA26F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 +#define NVA26F_SEMAPHORED_RELEASE_WFI 20:20 +#define NVA26F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 +#define NVA26F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 +#define NVA26F_SEMAPHORED_RELEASE_SIZE 24:24 +#define NVA26F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 +#define NVA26F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 +#define NVA26F_NON_STALL_INTERRUPT (0x00000020) +#define NVA26F_NON_STALL_INTERRUPT_HANDLE 31:0 +#define NVA26F_FB_FLUSH (0x00000024) +#define NVA26F_FB_FLUSH_HANDLE 31:0 +#define NVA26F_MEM_OP_A (0x00000028) +#define NVA26F_MEM_OP_A_OPERAND_LOW 31:2 +#define NVA26F_MEM_OP_A_TLB_INVALIDATE_ADDR 29:2 +#define NVA26F_MEM_OP_A_TLB_INVALIDATE_TARGET 31:30 +#define NVA26F_MEM_OP_A_TLB_INVALIDATE_TARGET_VID_MEM 0x00000000 +#define NVA26F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_COHERENT 0x00000002 +#define NVA26F_MEM_OP_A_TLB_INVALIDATE_TARGET_SYS_MEM_NONCOHERENT 0x00000003 +#define NVA26F_MEM_OP_B (0x0000002c) +#define NVA26F_MEM_OP_B_OPERAND_HIGH 7:0 +#define NVA26F_MEM_OP_B_OPERATION 31:27 +#define NVA26F_MEM_OP_B_OPERATION_SYSMEMBAR_FLUSH 0x00000005 +#define NVA26F_MEM_OP_B_OPERATION_MMU_TLB_INVALIDATE 0x00000009 +#define NVA26F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e +#define NVA26F_MEM_OP_B_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f +#define NVA26F_MEM_OP_B_OPERATION_L2_FLUSH_DIRTY 0x00000010 +#define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB 0:0 +#define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ONE 0x00000000 +#define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_PDB_ALL 0x00000001 +#define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC 1:1 +#define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_ENABLE 0x00000000 +#define NVA26F_MEM_OP_B_MMU_TLB_INVALIDATE_GPC_DISABLE 0x00000001 +#define NVA26F_SET_REFERENCE (0x00000050) +#define NVA26F_SET_REFERENCE_COUNT 31:0 +#define NVA26F_SYNCPOINTA (0x00000070) +#define NVA26F_SYNCPOINTA_PAYLOAD 31:0 +#define NVA26F_SYNCPOINTB (0x00000074) +#define NVA26F_SYNCPOINTB_OPERATION 1:0 +#define NVA26F_SYNCPOINTB_OPERATION_WAIT 0x00000000 +#define NVA26F_SYNCPOINTB_OPERATION_INCR 0x00000001 +#define NVA26F_SYNCPOINTB_OPERATION_BASE_ADD 0x00000002 +#define NVA26F_SYNCPOINTB_OPERATION_BASE_WRITE 0x00000003 +#define NVA26F_SYNCPOINTB_WAIT_SWITCH 4:4 +#define NVA26F_SYNCPOINTB_WAIT_SWITCH_DIS 0x00000000 +#define NVA26F_SYNCPOINTB_WAIT_SWITCH_EN 0x00000001 +#define NVA26F_SYNCPOINTB_BASE 5:5 +#define NVA26F_SYNCPOINTB_BASE_DIS 0x00000000 +#define NVA26F_SYNCPOINTB_BASE_EN 0x00000001 +#define NVA26F_SYNCPOINTB_SYNCPT_INDEX 15:8 +#define NVA26F_SYNCPOINTB_BASE_INDEX 25:20 +#define NVA26F_WFI (0x00000078) +#define NVA26F_WFI_HANDLE 31:0 +#define NVA26F_CRC_CHECK (0x0000007c) +#define NVA26F_CRC_CHECK_VALUE 31:0 +#define NVA26F_YIELD (0x00000080) +#define NVA26F_YIELD_OP 1:0 +#define NVA26F_YIELD_OP_NOP 0x00000000 + +/* GPFIFO entry format */ +#define NVA26F_GP_ENTRY__SIZE 8 +#define NVA26F_GP_ENTRY0_FETCH 0:0 +#define NVA26F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVA26F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NVA26F_GP_ENTRY0_GET 31:2 +#define NVA26F_GP_ENTRY0_OPERAND 31:0 +#define NVA26F_GP_ENTRY1_GET_HI 7:0 +#define NVA26F_GP_ENTRY1_PRIV 8:8 +#define NVA26F_GP_ENTRY1_PRIV_USER 0x00000000 +#define NVA26F_GP_ENTRY1_PRIV_KERNEL 0x00000001 +#define NVA26F_GP_ENTRY1_LEVEL 9:9 +#define NVA26F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NVA26F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NVA26F_GP_ENTRY1_LENGTH 30:10 +#define NVA26F_GP_ENTRY1_SYNC 31:31 +#define NVA26F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVA26F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVA26F_GP_ENTRY1_OPCODE 7:0 +#define NVA26F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVA26F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVA26F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVA26F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 + +/* dma method formats */ +#define NVA26F_DMA_METHOD_ADDRESS_OLD 12:2 +#define NVA26F_DMA_METHOD_ADDRESS 11:0 +#define NVA26F_DMA_SUBDEVICE_MASK 15:4 +#define NVA26F_DMA_METHOD_SUBCHANNEL 15:13 +#define NVA26F_DMA_TERT_OP 17:16 +#define NVA26F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NVA26F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NVA26F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NVA26F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NVA26F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NVA26F_DMA_METHOD_COUNT_OLD 28:18 +#define NVA26F_DMA_METHOD_COUNT 28:16 +#define NVA26F_DMA_IMMD_DATA 28:16 +#define NVA26F_DMA_SEC_OP 31:29 +#define NVA26F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NVA26F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NVA26F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NVA26F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) +#define NVA26F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NVA26F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NVA26F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NVA26F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) +/* dma incrementing method format */ +#define NVA26F_DMA_INCR_ADDRESS 11:0 +#define NVA26F_DMA_INCR_SUBCHANNEL 15:13 +#define NVA26F_DMA_INCR_COUNT 28:16 +#define NVA26F_DMA_INCR_OPCODE 31:29 +#define NVA26F_DMA_INCR_OPCODE_VALUE (0x00000001) +#define NVA26F_DMA_INCR_DATA 31:0 +/* dma non-incrementing method format */ +#define NVA26F_DMA_NONINCR_ADDRESS 11:0 +#define NVA26F_DMA_NONINCR_SUBCHANNEL 15:13 +#define NVA26F_DMA_NONINCR_COUNT 28:16 +#define NVA26F_DMA_NONINCR_OPCODE 31:29 +#define NVA26F_DMA_NONINCR_OPCODE_VALUE (0x00000003) +#define NVA26F_DMA_NONINCR_DATA 31:0 +/* dma increment-once method format */ +#define NVA26F_DMA_ONEINCR_ADDRESS 11:0 +#define NVA26F_DMA_ONEINCR_SUBCHANNEL 15:13 +#define NVA26F_DMA_ONEINCR_COUNT 28:16 +#define NVA26F_DMA_ONEINCR_OPCODE 31:29 +#define NVA26F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) +#define NVA26F_DMA_ONEINCR_DATA 31:0 +/* dma no-operation format */ +#define NVA26F_DMA_NOP (0x00000000) +/* dma immediate-data format */ +#define NVA26F_DMA_IMMD_ADDRESS 11:0 +#define NVA26F_DMA_IMMD_SUBCHANNEL 15:13 +#define NVA26F_DMA_IMMD_DATA 28:16 +#define NVA26F_DMA_IMMD_OPCODE 31:29 +#define NVA26F_DMA_IMMD_OPCODE_VALUE (0x00000004) +/* dma set sub-device mask format */ +#define NVA26F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 +#define NVA26F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 +#define NVA26F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) +/* dma store sub-device mask format */ +#define NVA26F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 +#define NVA26F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVA26F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) +/* dma use sub-device mask format */ +#define NVA26F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 +#define NVA26F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) +/* dma end-segment format */ +#define NVA26F_DMA_ENDSEG_OPCODE 31:29 +#define NVA26F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) +/* dma legacy incrementing/non-incrementing formats */ +#define NVA26F_DMA_ADDRESS 12:2 +#define NVA26F_DMA_SUBCH 15:13 +#define NVA26F_DMA_OPCODE3 17:16 +#define NVA26F_DMA_OPCODE3_NONE (0x00000000) +#define NVA26F_DMA_COUNT 28:18 +#define NVA26F_DMA_OPCODE 31:29 +#define NVA26F_DMA_OPCODE_METHOD (0x00000000) +#define NVA26F_DMA_OPCODE_NONINC_METHOD (0x00000002) +#define NVA26F_DMA_DATA 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _cla26f_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/clb069sw.h b/src/common/sdk/nvidia/inc/class/clb069sw.h index 621d214f9..840ac79e5 100644 --- a/src/common/sdk/nvidia/inc/class/clb069sw.h +++ b/src/common/sdk/nvidia/inc/class/clb069sw.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2008-2013 NVIDIA Corporation + Copyright (c) 2008-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -21,26 +21,18 @@ *******************************************************************************/ -#include "nvtypes.h" +#pragma once -#ifndef _clb069_sw_h_ -#define _clb069_sw_h_ +#include -#ifdef __cplusplus -extern "C" { -#endif +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clb069sw.finn +// -/* This file is *not* auto-generated. */ - - -typedef struct -{ - NvU32 flags; // set to 0 +#define NVB069_ALLOCATION_PARAMETERS_MESSAGE_ID (0xb069U) +typedef struct NVB069_ALLOCATION_PARAMETERS { + NvU32 flags; // set to 0 } NVB069_ALLOCATION_PARAMETERS; - -#ifdef __cplusplus -}; /* extern "C" */ -#endif -#endif // _clb096_sw_h diff --git a/src/common/sdk/nvidia/inc/class/clb097.h b/src/common/sdk/nvidia/inc/class/clb097.h index 31dc488a2..52ee31060 100644 --- a/src/common/sdk/nvidia/inc/class/clb097.h +++ b/src/common/sdk/nvidia/inc/class/clb097.h @@ -1,29 +1,3966 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. -#ifndef _clb097_h_ -#define _clb097_h_ + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_maxwell_a_h_ +#define _cl_maxwell_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl maxwell_a */ + +#include "nvtypes.h" #define MAXWELL_A 0xB097 -#endif // _clb097_h_ +#define NVB097_SET_OBJECT 0x0000 +#define NVB097_SET_OBJECT_CLASS_ID 15:0 +#define NVB097_SET_OBJECT_ENGINE_ID 20:16 + +#define NVB097_NO_OPERATION 0x0100 +#define NVB097_NO_OPERATION_V 31:0 + +#define NVB097_SET_NOTIFY_A 0x0104 +#define NVB097_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVB097_SET_NOTIFY_B 0x0108 +#define NVB097_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVB097_NOTIFY 0x010c +#define NVB097_NOTIFY_TYPE 31:0 +#define NVB097_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVB097_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVB097_WAIT_FOR_IDLE 0x0110 +#define NVB097_WAIT_FOR_IDLE_V 31:0 + +#define NVB097_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVB097_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVB097_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVB097_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVB097_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVB097_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVB097_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVB097_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVB097_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVB097_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVB097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVB097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVB097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVB097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVB097_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVB097_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVB097_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVB097_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVB097_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVB097_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVB097_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVB097_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVB097_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB097_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB097_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB097_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB097_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB097_SEND_GO_IDLE 0x013c +#define NVB097_SEND_GO_IDLE_V 31:0 + +#define NVB097_PM_TRIGGER 0x0140 +#define NVB097_PM_TRIGGER_V 31:0 + +#define NVB097_PM_TRIGGER_WFI 0x0144 +#define NVB097_PM_TRIGGER_WFI_V 31:0 + +#define NVB097_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVB097_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVB097_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVB097_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVB097_LINE_LENGTH_IN 0x0180 +#define NVB097_LINE_LENGTH_IN_VALUE 31:0 + +#define NVB097_LINE_COUNT 0x0184 +#define NVB097_LINE_COUNT_VALUE 31:0 + +#define NVB097_OFFSET_OUT_UPPER 0x0188 +#define NVB097_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVB097_OFFSET_OUT 0x018c +#define NVB097_OFFSET_OUT_VALUE 31:0 + +#define NVB097_PITCH_OUT 0x0190 +#define NVB097_PITCH_OUT_VALUE 31:0 + +#define NVB097_SET_DST_BLOCK_SIZE 0x0194 +#define NVB097_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVB097_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB097_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVB097_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB097_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB097_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB097_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB097_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB097_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB097_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVB097_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVB097_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVB097_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVB097_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB097_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB097_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVB097_SET_DST_WIDTH 0x0198 +#define NVB097_SET_DST_WIDTH_V 31:0 + +#define NVB097_SET_DST_HEIGHT 0x019c +#define NVB097_SET_DST_HEIGHT_V 31:0 + +#define NVB097_SET_DST_DEPTH 0x01a0 +#define NVB097_SET_DST_DEPTH_V 31:0 + +#define NVB097_SET_DST_LAYER 0x01a4 +#define NVB097_SET_DST_LAYER_V 31:0 + +#define NVB097_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVB097_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVB097_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVB097_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVB097_LAUNCH_DMA 0x01b0 +#define NVB097_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVB097_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB097_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB097_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVB097_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVB097_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVB097_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVB097_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVB097_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVB097_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVB097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVB097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVB097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVB097_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVB097_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB097_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB097_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVB097_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB097_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB097_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB097_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVB097_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB097_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVB097_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVB097_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB097_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVB097_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB097_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB097_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVB097_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVB097_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVB097_LOAD_INLINE_DATA 0x01b4 +#define NVB097_LOAD_INLINE_DATA_V 31:0 + +#define NVB097_SET_I2M_SEMAPHORE_A 0x01dc +#define NVB097_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVB097_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVB097_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB097_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVB097_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVB097_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVB097_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVB097_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVB097_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVB097_SET_I2M_SPARE_NOOP03 0x01fc +#define NVB097_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVB097_RUN_DS_NOW 0x0200 +#define NVB097_RUN_DS_NOW_V 31:0 + +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVB097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVB097_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVB097_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVB097_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVB097_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVB097_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVB097_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVB097_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVB097_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_GS_DM_FIFO 0x0214 +#define NVB097_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVB097_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVB097_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVB097_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVB097_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB097_INVALIDATE_SHADER_CACHES 0x021c +#define NVB097_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVB097_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVB097_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVB097_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVB097_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVB097_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVB097_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVB097_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVB097_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVB097_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVB097_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVB097_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVB097_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVB097_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVB097_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVB097_INCREMENT_SYNC_POINT 0x02c8 +#define NVB097_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVB097_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVB097_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVB097_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVB097_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVB097_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVB097_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVB097_SET_PRIM_CIRCULAR_BUFFER_THROTTLE 0x02d0 +#define NVB097_SET_PRIM_CIRCULAR_BUFFER_THROTTLE_PRIM_AREA 21:0 + +#define NVB097_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVB097_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVB097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVB097_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVB097_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVB097_DECOMPRESS_SURFACE 0x02e0 +#define NVB097_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVB097_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVB097_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVB097_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVB097_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVB097_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVB097_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVB097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVB097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVB097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVB097_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVB097_SET_ZCULL_SUBREGION 0x02e8 +#define NVB097_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVB097_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVB097_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVB097_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVB097_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVB097_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVB097_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVB097_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVB097_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVB097_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVB097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVB097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVB097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVB097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVB097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVB097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVB097_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVB097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVB097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVB097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVB097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVB097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVB097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVB097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVB097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVB097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVB097_DRAW_ZERO_INDEX 0x0304 +#define NVB097_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVB097_SET_L1_CONFIGURATION 0x0308 +#define NVB097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVB097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVB097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVB097_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVB097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVB097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVB097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVB097_SET_SPA_VERSION 0x0310 +#define NVB097_SET_SPA_VERSION_MINOR 7:0 +#define NVB097_SET_SPA_VERSION_MAJOR 15:8 + +#define NVB097_SET_IEEE_CLEAN_UPDATE 0x0314 +#define NVB097_SET_IEEE_CLEAN_UPDATE_ENABLE 0:0 +#define NVB097_SET_IEEE_CLEAN_UPDATE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_IEEE_CLEAN_UPDATE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_SNAP_GRID_LINE 0x0318 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVB097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVB097_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVB097_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVB097_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVB097_SET_SNAP_GRID_NON_LINE 0x031c +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVB097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVB097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVB097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVB097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVB097_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVB097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVB097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVB097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVB097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVB097_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVB097_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVB097_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVB097_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVB097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVB097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVB097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVB097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVB097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVB097_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVB097_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVB097_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVB097_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVB097_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVB097_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVB097_SET_TESSELLATION_LOD_V1 0x0330 +#define NVB097_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVB097_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVB097_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVB097_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVB097_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVB097_RESERVED_TG07 0x033c +#define NVB097_RESERVED_TG07_V 0:0 + +#define NVB097_RESERVED_TG08 0x0340 +#define NVB097_RESERVED_TG08_V 0:0 + +#define NVB097_RESERVED_TG09 0x0344 +#define NVB097_RESERVED_TG09_V 0:0 + +#define NVB097_RESERVED_TG10 0x0348 +#define NVB097_RESERVED_TG10_V 0:0 + +#define NVB097_RESERVED_TG11 0x034c +#define NVB097_RESERVED_TG11_V 0:0 + +#define NVB097_RESERVED_TG12 0x0350 +#define NVB097_RESERVED_TG12_V 0:0 + +#define NVB097_RESERVED_TG13 0x0354 +#define NVB097_RESERVED_TG13_V 0:0 + +#define NVB097_RESERVED_TG14 0x0358 +#define NVB097_RESERVED_TG14_V 0:0 + +#define NVB097_RESERVED_TG15 0x035c +#define NVB097_RESERVED_TG15_V 0:0 + +#define NVB097_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVB097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVB097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVB097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVB097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVB097_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVB097_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVB097_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVB097_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVB097_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVB097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVB097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVB097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVB097_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVB097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVB097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVB097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVB097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVB097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVB097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVB097_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVB097_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVB097_SET_RASTER_ENABLE 0x037c +#define NVB097_SET_RASTER_ENABLE_V 0:0 +#define NVB097_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVB097_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVB097_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVB097_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVB097_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVB097_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVB097_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVB097_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVB097_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVB097_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVB097_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVB097_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVB097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVB097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVB097_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVB097_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVB097_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVB097_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVB097_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVB097_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVB097_SET_RASTER_INPUT 0x0740 +#define NVB097_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVB097_SET_STREAM_OUTPUT 0x0744 +#define NVB097_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVB097_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVB097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVB097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_ALPHA_FRACTION 0x074c +#define NVB097_SET_ALPHA_FRACTION_V 7:0 + +#define NVB097_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVB097_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVB097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVB097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVB097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 + +#define NVB097_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVB097_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVB097_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVB097_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVB097_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVB097_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVB097_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVB097_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVB097_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVB097_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVB097_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVB097_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVB097_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVB097_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVB097_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVB097_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVB097_SET_ISBE_SAVE_RESTORE_PROGRAM 0x07ac +#define NVB097_SET_ISBE_SAVE_RESTORE_PROGRAM_OFFSET 31:0 + +#define NVB097_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVB097_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVB097_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVB097_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVB097_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVB097_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVB097_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVB097_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVB097_SET_CULL_BEFORE_FETCH 0x07dc +#define NVB097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVB097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVB097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVB097_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVB097_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVB097_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVB097_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVB097_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVB097_SET_ZCULL_STORAGE_A 0x07e8 +#define NVB097_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVB097_SET_ZCULL_STORAGE_B 0x07ec +#define NVB097_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVB097_SET_ZCULL_STORAGE_C 0x07f0 +#define NVB097_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVB097_SET_ZCULL_STORAGE_D 0x07f4 +#define NVB097_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVB097_SET_ZT_READ_ONLY 0x07f8 +#define NVB097_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVB097_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVB097_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVB097_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVB097_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVB097_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVB097_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVB097_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVB097_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVB097_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVB097_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVB097_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVB097_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVB097_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVB097_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVB097_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVB097_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVB097_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVB097_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVB097_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVB097_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVB097_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVB097_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVB097_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVB097_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVB097_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVB097_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVB097_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB097_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVB097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVB097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVB097_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVB097_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVB097_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVB097_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVB097_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVB097_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVB097_SET_COLOR_TARGET_MARK(j) (0x0824+(j)*64) +#define NVB097_SET_COLOR_TARGET_MARK_IEEE_CLEAN 0:0 +#define NVB097_SET_COLOR_TARGET_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVB097_SET_COLOR_TARGET_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVB097_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVB097_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVB097_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVB097_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVB097_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVB097_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVB097_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVB097_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVB097_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVB097_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVB097_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVB097_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVB097_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVB097_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVB097_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVB097_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVB097_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVB097_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVB097_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVB097_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVB097_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVB097_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVB097_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVB097_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVB097_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVB097_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVB097_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVB097_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVB097_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVB097_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVB097_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVB097_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVB097_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVB097_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVB097_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVB097_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVB097_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVB097_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVB097_SET_STATISTICS_COUNTER 0x0d68 +#define NVB097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVB097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVB097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVB097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVB097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVB097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVB097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVB097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVB097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVB097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVB097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVB097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVB097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVB097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVB097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVB097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVB097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVB097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVB097_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVB097_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVB097_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVB097_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVB097_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVB097_SET_VERTEX_ARRAY_START 0x0d74 +#define NVB097_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVB097_DRAW_VERTEX_ARRAY 0x0d78 +#define NVB097_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVB097_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVB097_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVB097_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVB097_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVB097_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVB097_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVB097_SET_Z_CLEAR_VALUE 0x0d90 +#define NVB097_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVB097_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVB097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVB097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVB097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVB097_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVB097_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVB097_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVB097_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVB097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVB097_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVB097_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVB097_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVB097_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVB097_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVB097_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVB097_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVB097_SET_FRONT_POLYGON_MODE 0x0dac +#define NVB097_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVB097_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVB097_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVB097_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVB097_SET_BACK_POLYGON_MODE 0x0db0 +#define NVB097_SET_BACK_POLYGON_MODE_V 31:0 +#define NVB097_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVB097_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVB097_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVB097_SET_POLY_SMOOTH 0x0db4 +#define NVB097_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVB097_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVB097_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_ZT_MARK 0x0db8 +#define NVB097_SET_ZT_MARK_IEEE_CLEAN 0:0 +#define NVB097_SET_ZT_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVB097_SET_ZT_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVB097_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVB097_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVB097_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVB097_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVB097_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVB097_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVB097_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVB097_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVB097_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVB097_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVB097_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVB097_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVB097_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVB097_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVB097_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVB097_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVB097_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_PATCH 0x0dcc +#define NVB097_SET_PATCH_SIZE 7:0 + +#define NVB097_SET_ITERATED_BLEND 0x0dd0 +#define NVB097_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVB097_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVB097_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVB097_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVB097_SET_ZCULL_CRITERION 0x0dd8 +#define NVB097_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVB097_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVB097_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVB097_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVB097_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVB097_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVB097_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVB097_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVB097_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVB097_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVB097_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVB097_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVB097_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVB097_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVB097_SET_ZCULL_CRITERION_SREF 23:16 +#define NVB097_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVB097_PIXEL_SHADER_BARRIER 0x0de0 +#define NVB097_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVB097_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVB097_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVB097_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVB097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVB097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVB097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVB097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVB097_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVB097_SET_WINDOW_OFFSET_X 0x0df8 +#define NVB097_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVB097_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVB097_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVB097_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVB097_SET_SCISSOR_ENABLE_V 0:0 +#define NVB097_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVB097_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVB097_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVB097_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVB097_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVB097_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVB097_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVB097_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVB097_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0f10 +#define NVB097_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVB097_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVB097_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVB097_SET_VPC_PERF_KNOB 0x0f14 +#define NVB097_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVB097_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVB097_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVB097_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVB097_PM_LOCAL_TRIGGER 0x0f18 +#define NVB097_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVB097_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVB097_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVB097_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVB097_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVB097_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVB097_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVB097_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVB097_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVB097_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVB097_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVB097_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVB097_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVB097_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVB097_SET_BACK_STENCIL_MASK 0x0f58 +#define NVB097_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVB097_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVB097_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVB097_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVB097_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVB097_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVB097_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVB097_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVB097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVB097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVB097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVB097_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVB097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVB097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVB097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVB097_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVB097_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVB097_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVB097_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVB097_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVB097_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVB097_SET_CT_MRT_ENABLE 0x0fac +#define NVB097_SET_CT_MRT_ENABLE_V 0:0 +#define NVB097_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVB097_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVB097_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVB097_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVB097_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVB097_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVB097_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVB097_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVB097_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVB097_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVB097_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVB097_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVB097_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVB097_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVB097_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVB097_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVB097_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVB097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVB097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVB097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVB097_SET_ZT_A 0x0fe0 +#define NVB097_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_ZT_B 0x0fe4 +#define NVB097_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_ZT_FORMAT 0x0fe8 +#define NVB097_SET_ZT_FORMAT_V 4:0 +#define NVB097_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVB097_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVB097_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVB097_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVB097_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVB097_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVB097_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVB097_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVB097_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVB097_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVB097_SET_ZT_BLOCK_SIZE 0x0fec +#define NVB097_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVB097_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB097_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVB097_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB097_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB097_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB097_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB097_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB097_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB097_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVB097_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVB097_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVB097_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVB097_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVB097_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVB097_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVB097_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVB097_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVB097_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVB097_SET_TILED_CACHE_BUNDLE_CONTROL 0x0ffc +#define NVB097_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT 0:0 +#define NVB097_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT_FALSE 0x00000000 +#define NVB097_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT_TRUE 0x00000001 + +#define NVB097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB097_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVB097_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVB097_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVB097_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVB097_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVB097_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVB097_SET_RESERVED_SW_METHOD00 0x1014 +#define NVB097_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVB097_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVB097_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVB097_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVB097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVB097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVB097_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVB097_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVB097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVB097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_RESERVED_SW_METHOD01 0x1028 +#define NVB097_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD02 0x102c +#define NVB097_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVB097_SET_SPARE_NOOP01 0x1044 +#define NVB097_SET_SPARE_NOOP01_V 31:0 + +#define NVB097_SET_SPARE_NOOP02 0x1048 +#define NVB097_SET_SPARE_NOOP02_V 31:0 + +#define NVB097_SET_SPARE_NOOP03 0x104c +#define NVB097_SET_SPARE_NOOP03_V 31:0 + +#define NVB097_SET_SPARE_NOOP04 0x1050 +#define NVB097_SET_SPARE_NOOP04_V 31:0 + +#define NVB097_SET_SPARE_NOOP05 0x1054 +#define NVB097_SET_SPARE_NOOP05_V 31:0 + +#define NVB097_SET_SPARE_NOOP06 0x1058 +#define NVB097_SET_SPARE_NOOP06_V 31:0 + +#define NVB097_SET_SPARE_NOOP07 0x105c +#define NVB097_SET_SPARE_NOOP07_V 31:0 + +#define NVB097_SET_SPARE_NOOP08 0x1060 +#define NVB097_SET_SPARE_NOOP08_V 31:0 + +#define NVB097_SET_SPARE_NOOP09 0x1064 +#define NVB097_SET_SPARE_NOOP09_V 31:0 + +#define NVB097_SET_SPARE_NOOP10 0x1068 +#define NVB097_SET_SPARE_NOOP10_V 31:0 + +#define NVB097_SET_SPARE_NOOP11 0x106c +#define NVB097_SET_SPARE_NOOP11_V 31:0 + +#define NVB097_SET_SPARE_NOOP12 0x1070 +#define NVB097_SET_SPARE_NOOP12_V 31:0 + +#define NVB097_SET_SPARE_NOOP13 0x1074 +#define NVB097_SET_SPARE_NOOP13_V 31:0 + +#define NVB097_SET_SPARE_NOOP14 0x1078 +#define NVB097_SET_SPARE_NOOP14_V 31:0 + +#define NVB097_SET_SPARE_NOOP15 0x107c +#define NVB097_SET_SPARE_NOOP15_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVB097_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVB097_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVB097_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD06 0x10bc +#define NVB097_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVB097_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVB097_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVB097_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVB097_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVB097_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVB097_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVB097_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD13 0x10dc +#define NVB097_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVB097_UNBIND_ALL 0x10f4 +#define NVB097_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVB097_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVB097_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVB097_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVB097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB097_SET_RESERVED_SW_METHOD14 0x1100 +#define NVB097_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVB097_SET_RESERVED_SW_METHOD15 0x1104 +#define NVB097_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVB097_NO_OPERATION_DATA_HI 0x110c +#define NVB097_NO_OPERATION_DATA_HI_V 31:0 + +#define NVB097_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVB097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVB097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVB097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVB097_PM_TRIGGER_END 0x1114 +#define NVB097_PM_TRIGGER_END_V 31:0 + +#define NVB097_SET_VERTEX_ID_BASE 0x1118 +#define NVB097_SET_VERTEX_ID_BASE_V 31:0 + +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVB097_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVB097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVB097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVB097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVB097_FLUSH_PENDING_WRITES 0x1144 +#define NVB097_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVB097_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVB097_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVB097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVB097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVB097_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVB097_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVB097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVB097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVB097_SET_CT_SELECT 0x121c +#define NVB097_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVB097_SET_CT_SELECT_TARGET0 6:4 +#define NVB097_SET_CT_SELECT_TARGET1 9:7 +#define NVB097_SET_CT_SELECT_TARGET2 12:10 +#define NVB097_SET_CT_SELECT_TARGET3 15:13 +#define NVB097_SET_CT_SELECT_TARGET4 18:16 +#define NVB097_SET_CT_SELECT_TARGET5 21:19 +#define NVB097_SET_CT_SELECT_TARGET6 24:22 +#define NVB097_SET_CT_SELECT_TARGET7 27:25 + +#define NVB097_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVB097_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVB097_SET_ZT_SIZE_A 0x1228 +#define NVB097_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVB097_SET_ZT_SIZE_B 0x122c +#define NVB097_SET_ZT_SIZE_B_HEIGHT 16:0 + +#define NVB097_SET_ZT_SIZE_C 0x1230 +#define NVB097_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVB097_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVB097_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVB097_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVB097_SET_SAMPLER_BINDING 0x1234 +#define NVB097_SET_SAMPLER_BINDING_V 0:0 +#define NVB097_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVB097_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVB097_DRAW_AUTO 0x123c +#define NVB097_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVB097_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVB097_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVB097_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVB097_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVB097_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB097_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVB097_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVB097_CLEAR_ZCULL_REGION 0x12c8 +#define NVB097_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVB097_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVB097_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVB097_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVB097_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVB097_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVB097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVB097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVB097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVB097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVB097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVB097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVB097_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVB097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVB097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVB097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVB097_SET_DEPTH_TEST 0x12cc +#define NVB097_SET_DEPTH_TEST_ENABLE 0:0 +#define NVB097_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVB097_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_FILL_MODE 0x12d0 +#define NVB097_SET_FILL_MODE_V 31:0 +#define NVB097_SET_FILL_MODE_V_POINT 0x00000001 +#define NVB097_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVB097_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVB097_SET_SHADE_MODE 0x12d4 +#define NVB097_SET_SHADE_MODE_V 31:0 +#define NVB097_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVB097_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVB097_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVB097_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVB097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVB097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVB097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVB097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVB097_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVB097_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVB097_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVB097_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_DEPTH_WRITE 0x12e8 +#define NVB097_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVB097_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_ALPHA_TEST 0x12ec +#define NVB097_SET_ALPHA_TEST_ENABLE 0:0 +#define NVB097_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVB097_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVB097_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVB097_DRAW_INLINE_INDEX4X8 0x1304 +#define NVB097_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVB097_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVB097_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVB097_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVB097_D3D_SET_CULL_MODE 0x1308 +#define NVB097_D3D_SET_CULL_MODE_V 31:0 +#define NVB097_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVB097_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVB097_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVB097_SET_DEPTH_FUNC 0x130c +#define NVB097_SET_DEPTH_FUNC_V 31:0 +#define NVB097_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVB097_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVB097_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVB097_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVB097_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVB097_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVB097_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVB097_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVB097_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVB097_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVB097_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVB097_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVB097_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVB097_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVB097_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVB097_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVB097_SET_ALPHA_REF 0x1310 +#define NVB097_SET_ALPHA_REF_V 31:0 + +#define NVB097_SET_ALPHA_FUNC 0x1314 +#define NVB097_SET_ALPHA_FUNC_V 31:0 +#define NVB097_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVB097_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVB097_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVB097_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVB097_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVB097_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVB097_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVB097_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVB097_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVB097_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVB097_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVB097_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVB097_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVB097_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVB097_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVB097_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVB097_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVB097_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVB097_SET_BLEND_CONST_RED 0x131c +#define NVB097_SET_BLEND_CONST_RED_V 31:0 + +#define NVB097_SET_BLEND_CONST_GREEN 0x1320 +#define NVB097_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVB097_SET_BLEND_CONST_BLUE 0x1324 +#define NVB097_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVB097_SET_BLEND_CONST_ALPHA 0x1328 +#define NVB097_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVB097_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVB097_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVB097_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVB097_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVB097_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVB097_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVB097_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVB097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVB097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVB097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_BLEND_COLOR_OP 0x1340 +#define NVB097_SET_BLEND_COLOR_OP_V 31:0 +#define NVB097_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVB097_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVB097_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVB097_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVB097_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVB097_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVB097_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVB097_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVB097_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVB097_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB097_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB097_SET_BLEND_ALPHA_OP 0x134c +#define NVB097_SET_BLEND_ALPHA_OP_V 31:0 +#define NVB097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVB097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVB097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVB097_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVB097_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVB097_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVB097_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVB097_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVB097_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVB097_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB097_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVB097_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVB097_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVB097_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB097_SET_SINGLE_ROP_CONTROL 0x135c +#define NVB097_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVB097_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVB097_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_BLEND(i) (0x1360+(i)*4) +#define NVB097_SET_BLEND_ENABLE 0:0 +#define NVB097_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVB097_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_STENCIL_TEST 0x1380 +#define NVB097_SET_STENCIL_TEST_ENABLE 0:0 +#define NVB097_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVB097_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_STENCIL_OP_FAIL 0x1384 +#define NVB097_SET_STENCIL_OP_FAIL_V 31:0 +#define NVB097_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVB097_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVB097_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVB097_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVB097_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVB097_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVB097_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVB097_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVB097_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVB097_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVB097_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVB097_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVB097_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVB097_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVB097_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVB097_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVB097_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVB097_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVB097_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVB097_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVB097_SET_STENCIL_OP_ZPASS 0x138c +#define NVB097_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVB097_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVB097_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVB097_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVB097_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVB097_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVB097_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVB097_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVB097_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVB097_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVB097_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVB097_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVB097_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVB097_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVB097_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVB097_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVB097_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVB097_SET_STENCIL_FUNC 0x1390 +#define NVB097_SET_STENCIL_FUNC_V 31:0 +#define NVB097_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVB097_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVB097_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVB097_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVB097_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVB097_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVB097_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVB097_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVB097_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVB097_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVB097_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVB097_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVB097_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVB097_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVB097_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVB097_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVB097_SET_STENCIL_FUNC_REF 0x1394 +#define NVB097_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVB097_SET_STENCIL_FUNC_MASK 0x1398 +#define NVB097_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVB097_SET_STENCIL_MASK 0x139c +#define NVB097_SET_STENCIL_MASK_V 7:0 + +#define NVB097_SET_DRAW_AUTO_START 0x13a4 +#define NVB097_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVB097_SET_PS_SATURATE 0x13a8 +#define NVB097_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVB097_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVB097_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB097_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVB097_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVB097_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB097_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVB097_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVB097_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB097_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVB097_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVB097_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB097_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVB097_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVB097_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB097_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVB097_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVB097_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB097_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVB097_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVB097_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB097_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVB097_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVB097_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB097_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVB097_SET_WINDOW_ORIGIN 0x13ac +#define NVB097_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVB097_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVB097_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVB097_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVB097_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVB097_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVB097_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVB097_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVB097_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVB097_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVB097_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVB097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVB097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_ALPHA_HYSTERESIS 0x1420 +#define NVB097_SET_ALPHA_HYSTERESIS_ROUNDS_OF_ALPHA 7:0 + +#define NVB097_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVB097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVB097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB097_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVB097_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVB097_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVB097_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVB097_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVB097_SET_PS_WARP_WATERMARKS 0x1450 +#define NVB097_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVB097_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVB097_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVB097_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVB097_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVB097_STORE_ZCULL 0x1464 +#define NVB097_STORE_ZCULL_V 0:0 + +#define NVB097_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVB097_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVB097_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVB097_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVB097_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVB097_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVB097_LOAD_ZCULL 0x1500 +#define NVB097_LOAD_ZCULL_V 0:0 + +#define NVB097_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVB097_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVB097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVB097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVB097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVB097_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVB097_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVB097_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVB097_SET_USER_CLIP_ENABLE 0x1510 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVB097_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVB097_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVB097_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVB097_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_POINT_SIZE 0x1518 +#define NVB097_SET_POINT_SIZE_V 31:0 + +#define NVB097_SET_ZCULL_STATS 0x151c +#define NVB097_SET_ZCULL_STATS_ENABLE 0:0 +#define NVB097_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_POINT_SPRITE 0x1520 +#define NVB097_SET_POINT_SPRITE_ENABLE 0:0 +#define NVB097_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_SHADER_EXCEPTIONS 0x1528 +#define NVB097_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVB097_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVB097_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVB097_CLEAR_REPORT_VALUE 0x1530 +#define NVB097_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVB097_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVB097_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVB097_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVB097_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVB097_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVB097_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVB097_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 + +#define NVB097_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVB097_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVB097_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVB097_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVB097_SET_ZT_SELECT 0x1538 +#define NVB097_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVB097_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVB097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVB097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVB097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVB097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVB097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVB097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVB097_SET_RENDER_ENABLE_A 0x1550 +#define NVB097_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_RENDER_ENABLE_B 0x1554 +#define NVB097_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_RENDER_ENABLE_C 0x1558 +#define NVB097_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVB097_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB097_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB097_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB097_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB097_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB097_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVB097_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVB097_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVB097_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVB097_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVB097_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVB097_SET_ANTI_ALIASED_LINE 0x1570 +#define NVB097_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVB097_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_TEX_HEADER_POOL_A 0x1574 +#define NVB097_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_TEX_HEADER_POOL_B 0x1578 +#define NVB097_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_TEX_HEADER_POOL_C 0x157c +#define NVB097_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVB097_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVB097_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVB097_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVB097_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVB097_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVB097_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVB097_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVB097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVB097_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVB097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVB097_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVB097_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVB097_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVB097_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVB097_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVB097_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVB097_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVB097_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVB097_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVB097_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVB097_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVB097_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVB097_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVB097_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVB097_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVB097_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVB097_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVB097_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVB097_SET_SRGB_WRITE 0x15b8 +#define NVB097_SET_SRGB_WRITE_ENABLE 0:0 +#define NVB097_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_DEPTH_BIAS 0x15bc +#define NVB097_SET_DEPTH_BIAS_V 31:0 + +#define NVB097_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVB097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVB097_SET_RT_LAYER 0x15cc +#define NVB097_SET_RT_LAYER_V 15:0 +#define NVB097_SET_RT_LAYER_CONTROL 16:16 +#define NVB097_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVB097_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVB097_SET_ANTI_ALIAS 0x15d0 +#define NVB097_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVB097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVB097_SET_EDGE_FLAG 0x15e4 +#define NVB097_SET_EDGE_FLAG_V 0:0 +#define NVB097_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVB097_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVB097_DRAW_INLINE_INDEX 0x15e8 +#define NVB097_DRAW_INLINE_INDEX_V 31:0 + +#define NVB097_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVB097_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVB097_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVB097_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVB097_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVB097_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVB097_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVB097_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVB097_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVB097_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVB097_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVB097_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVB097_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVB097_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVB097_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVB097_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVB097_SET_POINT_SPRITE_SELECT 0x1604 +#define NVB097_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVB097_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVB097_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVB097_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVB097_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVB097_SET_PROGRAM_REGION_A 0x1608 +#define NVB097_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVB097_SET_PROGRAM_REGION_B 0x160c +#define NVB097_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVB097_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVB097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVB097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVB097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVB097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVB097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVB097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVB097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVB097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVB097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVB097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVB097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVB097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVB097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVB097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVB097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVB097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVB097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVB097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVB097_END 0x1614 +#define NVB097_END_V 0:0 + +#define NVB097_BEGIN 0x1618 +#define NVB097_BEGIN_OP 15:0 +#define NVB097_BEGIN_OP_POINTS 0x00000000 +#define NVB097_BEGIN_OP_LINES 0x00000001 +#define NVB097_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVB097_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVB097_BEGIN_OP_TRIANGLES 0x00000004 +#define NVB097_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVB097_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVB097_BEGIN_OP_QUADS 0x00000007 +#define NVB097_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVB097_BEGIN_OP_POLYGON 0x00000009 +#define NVB097_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVB097_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVB097_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_BEGIN_OP_PATCH 0x0000000E +#define NVB097_BEGIN_PRIMITIVE_ID 24:24 +#define NVB097_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVB097_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVB097_BEGIN_INSTANCE_ID 27:26 +#define NVB097_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVB097_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVB097_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVB097_BEGIN_SPLIT_MODE 30:29 +#define NVB097_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVB097_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVB097_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVB097_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 + +#define NVB097_SET_VERTEX_ID_COPY 0x161c +#define NVB097_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVB097_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVB097_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVB097_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVB097_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVB097_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVB097_LOAD_PRIMITIVE_ID 0x1624 +#define NVB097_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVB097_SET_SHADER_BASED_CULL 0x162c +#define NVB097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVB097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVB097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVB097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVB097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVB097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_CLASS_VERSION 0x1638 +#define NVB097_SET_CLASS_VERSION_CURRENT 15:0 +#define NVB097_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB097_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVB097_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVB097_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVB097_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVB097_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVB097_SET_DA_OUTPUT 0x164c +#define NVB097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVB097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVB097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVB097_SET_ANTI_ALIASED_POINT 0x1658 +#define NVB097_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVB097_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_POINT_CENTER_MODE 0x165c +#define NVB097_SET_POINT_CENTER_MODE_V 31:0 +#define NVB097_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVB097_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVB097_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVB097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVB097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVB097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVB097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVB097_SET_LINE_STIPPLE 0x166c +#define NVB097_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVB097_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVB097_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVB097_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVB097_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVB097_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVB097_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVB097_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVB097_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVB097_SET_PROVOKING_VERTEX 0x1684 +#define NVB097_SET_PROVOKING_VERTEX_V 0:0 +#define NVB097_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVB097_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVB097_SET_TWO_SIDED_LIGHT 0x1688 +#define NVB097_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVB097_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_POLYGON_STIPPLE 0x168c +#define NVB097_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVB097_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_SHADER_CONTROL 0x1690 +#define NVB097_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVB097_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVB097_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVB097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVB097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVB097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVB097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVB097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVB097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVB097_CHECK_CLASS_VERSION 0x16a0 +#define NVB097_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVB097_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB097_SET_SPH_VERSION 0x16a4 +#define NVB097_SET_SPH_VERSION_CURRENT 15:0 +#define NVB097_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB097_CHECK_SPH_VERSION 0x16a8 +#define NVB097_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVB097_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB097_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVB097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVB097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVB097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVB097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVB097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVB097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVB097_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVB097_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVB097_SET_AAM_VERSION 0x1790 +#define NVB097_SET_AAM_VERSION_CURRENT 15:0 +#define NVB097_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB097_CHECK_AAM_VERSION 0x1794 +#define NVB097_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVB097_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB097_SET_ZT_LAYER 0x179c +#define NVB097_SET_ZT_LAYER_OFFSET 15:0 + +#define NVB097_SET_INDEX_BUFFER_A 0x17c8 +#define NVB097_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVB097_SET_INDEX_BUFFER_B 0x17cc +#define NVB097_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVB097_SET_INDEX_BUFFER_C 0x17d0 +#define NVB097_SET_INDEX_BUFFER_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVB097_SET_INDEX_BUFFER_D 0x17d4 +#define NVB097_SET_INDEX_BUFFER_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVB097_SET_INDEX_BUFFER_E 0x17d8 +#define NVB097_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVB097_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVB097_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVB097_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVB097_SET_INDEX_BUFFER_F 0x17dc +#define NVB097_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVB097_DRAW_INDEX_BUFFER 0x17e0 +#define NVB097_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVB097_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVB097_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVB097_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVB097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVB097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVB097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVB097_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVB097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVB097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVB097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVB097_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVB097_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVB097_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVB097_OGL_SET_CULL 0x1918 +#define NVB097_OGL_SET_CULL_ENABLE 0:0 +#define NVB097_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVB097_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVB097_OGL_SET_FRONT_FACE 0x191c +#define NVB097_OGL_SET_FRONT_FACE_V 31:0 +#define NVB097_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVB097_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVB097_OGL_SET_CULL_FACE 0x1920 +#define NVB097_OGL_SET_CULL_FACE_V 31:0 +#define NVB097_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVB097_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVB097_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVB097_SET_VIEWPORT_PIXEL 0x1924 +#define NVB097_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVB097_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVB097_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVB097_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVB097_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVB097_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVB097_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVB097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVB097_SET_USER_CLIP_OP 0x1940 +#define NVB097_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVB097_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVB097_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVB097_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVB097_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVB097_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVB097_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVB097_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVB097_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVB097_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVB097_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVB097_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVB097_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVB097_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVB097_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVB097_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVB097_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVB097_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVB097_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVB097_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVB097_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVB097_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVB097_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVB097_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVB097_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVB097_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVB097_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVB097_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVB097_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVB097_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVB097_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVB097_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVB097_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVB097_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVB097_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVB097_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVB097_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVB097_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVB097_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVB097_INVALIDATE_ZCULL 0x1958 +#define NVB097_INVALIDATE_ZCULL_V 31:0 +#define NVB097_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVB097_SET_ZCULL 0x1968 +#define NVB097_SET_ZCULL_Z_ENABLE 0:0 +#define NVB097_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVB097_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_ZCULL_BOUNDS 0x196c +#define NVB097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVB097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVB097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVB097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVB097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVB097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVB097_ZCULL_SYNC 0x1978 +#define NVB097_ZCULL_SYNC_V 31:0 + +#define NVB097_SET_CLIP_ID_TEST 0x197c +#define NVB097_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVB097_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVB097_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVB097_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVB097_SET_CLIP_ID 0x1984 +#define NVB097_SET_CLIP_ID_V 31:0 + +#define NVB097_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVB097_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVB097_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVB097_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVB097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVB097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVB097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVB097_SET_LOGIC_OP 0x19c4 +#define NVB097_SET_LOGIC_OP_ENABLE 0:0 +#define NVB097_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVB097_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_LOGIC_OP_FUNC 0x19c8 +#define NVB097_SET_LOGIC_OP_FUNC_V 31:0 +#define NVB097_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVB097_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVB097_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVB097_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVB097_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVB097_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVB097_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVB097_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVB097_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVB097_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVB097_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVB097_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVB097_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVB097_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVB097_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVB097_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVB097_SET_Z_COMPRESSION 0x19cc +#define NVB097_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVB097_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVB097_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVB097_CLEAR_SURFACE 0x19d0 +#define NVB097_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVB097_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVB097_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVB097_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVB097_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVB097_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVB097_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVB097_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVB097_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVB097_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVB097_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVB097_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVB097_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVB097_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVB097_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVB097_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVB097_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVB097_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVB097_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVB097_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVB097_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVB097_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVB097_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVB097_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVB097_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVB097_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVB097_SET_CT_WRITE_R_ENABLE 0:0 +#define NVB097_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVB097_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVB097_SET_CT_WRITE_G_ENABLE 4:4 +#define NVB097_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVB097_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVB097_SET_CT_WRITE_B_ENABLE 8:8 +#define NVB097_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVB097_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVB097_SET_CT_WRITE_A_ENABLE 12:12 +#define NVB097_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVB097_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVB097_PIPE_NOP 0x1a2c +#define NVB097_PIPE_NOP_V 31:0 + +#define NVB097_SET_SPARE00 0x1a30 +#define NVB097_SET_SPARE00_V 31:0 + +#define NVB097_SET_SPARE01 0x1a34 +#define NVB097_SET_SPARE01_V 31:0 + +#define NVB097_SET_SPARE02 0x1a38 +#define NVB097_SET_SPARE02_V 31:0 + +#define NVB097_SET_SPARE03 0x1a3c +#define NVB097_SET_SPARE03_V 31:0 + +#define NVB097_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVB097_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVB097_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVB097_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB097_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVB097_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVB097_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVB097_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVB097_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVB097_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVB097_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVB097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVB097_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVB097_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVB097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVB097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVB097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVB097_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVB097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVB097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVB097_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVB097_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVB097_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVB097_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVB097_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVB097_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVB097_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVB097_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVB097_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVB097_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVB097_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVB097_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVB097_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVB097_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVB097_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVB097_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVB097_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVB097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVB097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVB097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVB097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB097_SET_VERTEX_STREAM_LIMIT_A_A(j) (0x1f00+(j)*8) +#define NVB097_SET_VERTEX_STREAM_LIMIT_A_A_UPPER 7:0 + +#define NVB097_SET_VERTEX_STREAM_LIMIT_A_B(j) (0x1f04+(j)*8) +#define NVB097_SET_VERTEX_STREAM_LIMIT_A_B_LOWER 31:0 + +#define NVB097_SET_VERTEX_STREAM_LIMIT_B_A(j) (0x1f80+(j)*8) +#define NVB097_SET_VERTEX_STREAM_LIMIT_B_A_UPPER 7:0 + +#define NVB097_SET_VERTEX_STREAM_LIMIT_B_B(j) (0x1f84+(j)*8) +#define NVB097_SET_VERTEX_STREAM_LIMIT_B_B_LOWER 31:0 + +#define NVB097_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVB097_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVB097_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVB097_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVB097_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVB097_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVB097_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVB097_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVB097_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVB097_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVB097_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVB097_SET_PIPELINE_PROGRAM(j) (0x2004+(j)*64) +#define NVB097_SET_PIPELINE_PROGRAM_OFFSET 31:0 + +#define NVB097_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVB097_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVB097_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVB097_SET_PIPELINE_REGISTER_COUNT_V 7:0 + +#define NVB097_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVB097_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVB097_SET_PIPELINE_RESERVED_B(j) (0x2014+(j)*64) +#define NVB097_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVB097_SET_PIPELINE_RESERVED_C(j) (0x2018+(j)*64) +#define NVB097_SET_PIPELINE_RESERVED_C_V 0:0 + +#define NVB097_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVB097_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVB097_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVB097_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVB097_SET_FALCON00 0x2300 +#define NVB097_SET_FALCON00_V 31:0 + +#define NVB097_SET_FALCON01 0x2304 +#define NVB097_SET_FALCON01_V 31:0 + +#define NVB097_SET_FALCON02 0x2308 +#define NVB097_SET_FALCON02_V 31:0 + +#define NVB097_SET_FALCON03 0x230c +#define NVB097_SET_FALCON03_V 31:0 + +#define NVB097_SET_FALCON04 0x2310 +#define NVB097_SET_FALCON04_V 31:0 + +#define NVB097_SET_FALCON05 0x2314 +#define NVB097_SET_FALCON05_V 31:0 + +#define NVB097_SET_FALCON06 0x2318 +#define NVB097_SET_FALCON06_V 31:0 + +#define NVB097_SET_FALCON07 0x231c +#define NVB097_SET_FALCON07_V 31:0 + +#define NVB097_SET_FALCON08 0x2320 +#define NVB097_SET_FALCON08_V 31:0 + +#define NVB097_SET_FALCON09 0x2324 +#define NVB097_SET_FALCON09_V 31:0 + +#define NVB097_SET_FALCON10 0x2328 +#define NVB097_SET_FALCON10_V 31:0 + +#define NVB097_SET_FALCON11 0x232c +#define NVB097_SET_FALCON11_V 31:0 + +#define NVB097_SET_FALCON12 0x2330 +#define NVB097_SET_FALCON12_V 31:0 + +#define NVB097_SET_FALCON13 0x2334 +#define NVB097_SET_FALCON13_V 31:0 + +#define NVB097_SET_FALCON14 0x2338 +#define NVB097_SET_FALCON14_V 31:0 + +#define NVB097_SET_FALCON15 0x233c +#define NVB097_SET_FALCON15_V 31:0 + +#define NVB097_SET_FALCON16 0x2340 +#define NVB097_SET_FALCON16_V 31:0 + +#define NVB097_SET_FALCON17 0x2344 +#define NVB097_SET_FALCON17_V 31:0 + +#define NVB097_SET_FALCON18 0x2348 +#define NVB097_SET_FALCON18_V 31:0 + +#define NVB097_SET_FALCON19 0x234c +#define NVB097_SET_FALCON19_V 31:0 + +#define NVB097_SET_FALCON20 0x2350 +#define NVB097_SET_FALCON20_V 31:0 + +#define NVB097_SET_FALCON21 0x2354 +#define NVB097_SET_FALCON21_V 31:0 + +#define NVB097_SET_FALCON22 0x2358 +#define NVB097_SET_FALCON22_V 31:0 + +#define NVB097_SET_FALCON23 0x235c +#define NVB097_SET_FALCON23_V 31:0 + +#define NVB097_SET_FALCON24 0x2360 +#define NVB097_SET_FALCON24_V 31:0 + +#define NVB097_SET_FALCON25 0x2364 +#define NVB097_SET_FALCON25_V 31:0 + +#define NVB097_SET_FALCON26 0x2368 +#define NVB097_SET_FALCON26_V 31:0 + +#define NVB097_SET_FALCON27 0x236c +#define NVB097_SET_FALCON27_V 31:0 + +#define NVB097_SET_FALCON28 0x2370 +#define NVB097_SET_FALCON28_V 31:0 + +#define NVB097_SET_FALCON29 0x2374 +#define NVB097_SET_FALCON29_V 31:0 + +#define NVB097_SET_FALCON30 0x2378 +#define NVB097_SET_FALCON30_V 31:0 + +#define NVB097_SET_FALCON31 0x237c +#define NVB097_SET_FALCON31_V 31:0 + +#define NVB097_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVB097_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVB097_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVB097_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVB097_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVB097_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVB097_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVB097_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVB097_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVB097_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVB097_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVB097_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVB097_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVB097_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVB097_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVB097_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVB097_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVB097_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVB097_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVB097_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVB097_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVB097_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVB097_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVB097_SET_COLOR_CLAMP 0x2600 +#define NVB097_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVB097_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVB097_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVB097_SET_BINDLESS_TEXTURE 0x2608 +#define NVB097_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 4:0 + +#define NVB097_SET_TRAP_HANDLER 0x260c +#define NVB097_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVB097_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVB097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVB097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVB097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVB097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVB097_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVB097_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVB097_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB097_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVB097_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB097_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVB097_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVB097_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVB097_CALL_MME_MACRO_V 31:0 + +#define NVB097_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVB097_CALL_MME_DATA_V 31:0 + +#endif /* _cl_maxwell_a_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/clb097tex.h b/src/common/sdk/nvidia/inc/class/clb097tex.h new file mode 100644 index 000000000..e5543e339 --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/clb097tex.h @@ -0,0 +1,2050 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2010 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLB097TEX_H__ +#define __CLB097TEX_H__ + +/* +** Texture Header State + */ + +#define NVB097_TEXHEAD0_COMPONENT_SIZES 5:0 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_R32_G32_B32_A32 0x00000001 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_R32_G32_B32 0x00000002 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_R16_G16_B16_A16 0x00000003 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_R32_G32 0x00000004 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_R32_B24G8 0x00000005 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_X8B8G8R8 0x00000007 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_A8B8G8R8 0x00000008 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_A2B10G10R10 0x00000009 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_R16_G16 0x0000000c +#define NVB097_TEXHEAD0_COMPONENT_SIZES_G8R24 0x0000000d +#define NVB097_TEXHEAD0_COMPONENT_SIZES_G24R8 0x0000000e +#define NVB097_TEXHEAD0_COMPONENT_SIZES_R32 0x0000000f +#define NVB097_TEXHEAD0_COMPONENT_SIZES_A4B4G4R4 0x00000012 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_A5B5G5R1 0x00000013 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_A1B5G5R5 0x00000014 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_B5G6R5 0x00000015 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_B6G5R5 0x00000016 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_G8R8 0x00000018 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_R16 0x0000001b +#define NVB097_TEXHEAD0_COMPONENT_SIZES_Y8_VIDEO 0x0000001c +#define NVB097_TEXHEAD0_COMPONENT_SIZES_R8 0x0000001d +#define NVB097_TEXHEAD0_COMPONENT_SIZES_G4R4 0x0000001e +#define NVB097_TEXHEAD0_COMPONENT_SIZES_R1 0x0000001f +#define NVB097_TEXHEAD0_COMPONENT_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_BF10GF11RF11 0x00000021 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_G8B8G8R8 0x00000022 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_B8G8R8G8 0x00000023 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_DXT1 0x00000024 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_DXT23 0x00000025 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_DXT45 0x00000026 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_DXN1 0x00000027 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_DXN2 0x00000028 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_BC6H_SF16 0x00000010 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_BC6H_UF16 0x00000011 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_BC7U 0x00000017 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ETC2_RGB 0x00000006 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ETC2_RGBA 0x0000000b +#define NVB097_TEXHEAD0_COMPONENT_SIZES_EAC 0x00000019 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_EACX2 0x0000001a +#define NVB097_TEXHEAD0_COMPONENT_SIZES_Z24S8 0x00000029 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_X8Z24 0x0000002a +#define NVB097_TEXHEAD0_COMPONENT_SIZES_S8Z24 0x0000002b +#define NVB097_TEXHEAD0_COMPONENT_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVB097_TEXHEAD0_COMPONENT_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVB097_TEXHEAD0_COMPONENT_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ZF32 0x0000002f +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ZF32_X24S8 0x00000030 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVB097_TEXHEAD0_COMPONENT_SIZES_Z16 0x0000003a +#define NVB097_TEXHEAD0_COMPONENT_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVB097_TEXHEAD0_COMPONENT_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVB097_TEXHEAD0_COMPONENT_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVB097_TEXHEAD0_COMPONENT_SIZES_CS_BITFIELD_SIZE 0x0000003f +#define NVB097_TEXHEAD0_R_DATA_TYPE 8:6 +#define NVB097_TEXHEAD0_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD0_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD0_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD0_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD0_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD0_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD0_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD0_G_DATA_TYPE 11:9 +#define NVB097_TEXHEAD0_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD0_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD0_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD0_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD0_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD0_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD0_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD0_B_DATA_TYPE 14:12 +#define NVB097_TEXHEAD0_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD0_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD0_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD0_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD0_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD0_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD0_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD0_A_DATA_TYPE 17:15 +#define NVB097_TEXHEAD0_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD0_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD0_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD0_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD0_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD0_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD0_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD0_X_SOURCE 20:18 +#define NVB097_TEXHEAD0_X_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD0_X_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD0_X_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD0_X_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD0_X_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD0_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD0_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD0_Y_SOURCE 23:21 +#define NVB097_TEXHEAD0_Y_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD0_Y_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD0_Y_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD0_Y_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD0_Y_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD0_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD0_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD0_Z_SOURCE 26:24 +#define NVB097_TEXHEAD0_Z_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD0_Z_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD0_Z_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD0_Z_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD0_Z_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD0_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD0_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD0_W_SOURCE 29:27 +#define NVB097_TEXHEAD0_W_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD0_W_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD0_W_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD0_W_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD0_W_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD0_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD0_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD0_PACK_COMPONENTS 30:30 +#define NVB097_TEXHEAD0_USE_COMPONENT_SIZES_EXTENDED 31:31 +#define NVB097_TEXHEAD1_OFFSET_LOWER 31:0 +#define NVB097_TEXHEAD2_OFFSET_UPPER 7:0 +#define NVB097_TEXHEAD2_ANISO_SPREAD_MAX_LOG2_L_S_B 9:8 +#define NVB097_TEXHEAD2_S_R_G_B_CONVERSION 10:10 +#define NVB097_TEXHEAD2_ANISO_SPREAD_MAX_LOG2_M_S_B 11:11 +#define NVB097_TEXHEAD2_LOD_ANISO_QUALITY2 12:12 +#define NVB097_TEXHEAD2_COLOR_KEY_OP 13:13 +#define NVB097_TEXHEAD2_TEXTURE_TYPE 17:14 +#define NVB097_TEXHEAD2_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVB097_TEXHEAD2_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVB097_TEXHEAD2_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVB097_TEXHEAD2_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVB097_TEXHEAD2_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVB097_TEXHEAD2_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVB097_TEXHEAD2_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVB097_TEXHEAD2_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVB097_TEXHEAD2_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVB097_TEXHEAD2_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVB097_TEXHEAD2_MEMORY_LAYOUT 18:18 +#define NVB097_TEXHEAD2_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB097_TEXHEAD2_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_WIDTH 21:19 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_HEIGHT 24:22 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_DEPTH 27:25 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEAD2_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEAD2_SECTOR_PROMOTION 29:28 +#define NVB097_TEXHEAD2_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVB097_TEXHEAD2_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVB097_TEXHEAD2_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVB097_TEXHEAD2_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVB097_TEXHEAD2_BORDER_SOURCE 30:30 +#define NVB097_TEXHEAD2_BORDER_SOURCE_BORDER_TEXTURE 0x00000000 +#define NVB097_TEXHEAD2_BORDER_SOURCE_BORDER_COLOR 0x00000001 +#define NVB097_TEXHEAD2_NORMALIZED_COORDS 31:31 +#define NVB097_TEXHEAD3_PITCH 19:0 +#define NVB097_TEXHEAD3_LOD_ANISO_QUALITY 20:20 +#define NVB097_TEXHEAD3_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEAD3_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEAD3_LOD_ISO_QUALITY 21:21 +#define NVB097_TEXHEAD3_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEAD3_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEAD3_ANISO_COARSE_SPREAD_MODIFIER 23:22 +#define NVB097_TEXHEAD3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEAD3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEAD3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEAD3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEAD3_ANISO_SPREAD_SCALE 28:24 +#define NVB097_TEXHEAD3_USE_HEADER_OPT_CONTROL 29:29 +#define NVB097_TEXHEAD3_RESERVED3A 30:30 +#define NVB097_TEXHEAD3_RESERVED3B 31:31 +#define NVB097_TEXHEAD4_WIDTH 29:0 +#define NVB097_TEXHEAD4_DEPTH_TEXTURE 30:30 +#define NVB097_TEXHEAD4_USE_TEXTURE_HEADER_VERSION2 31:31 +#define NVB097_TEXHEAD5_HEIGHT 15:0 +#define NVB097_TEXHEAD5_DEPTH 27:16 +#define NVB097_TEXHEAD5_MAX_MIP_LEVEL 31:28 +#define NVB097_TEXHEAD6_TRILIN_OPT 4:0 +#define NVB097_TEXHEAD6_MIP_LOD_BIAS 17:5 +#define NVB097_TEXHEAD6_RESERVED6A 18:18 +#define NVB097_TEXHEAD6_ANISO_BIAS 22:19 +#define NVB097_TEXHEAD6_ANISO_FINE_SPREAD_FUNC 24:23 +#define NVB097_TEXHEAD6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEAD6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEAD6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEAD6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEAD6_ANISO_COARSE_SPREAD_FUNC 26:25 +#define NVB097_TEXHEAD6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEAD6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEAD6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEAD6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEAD6_MAX_ANISOTROPY 29:27 +#define NVB097_TEXHEAD6_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVB097_TEXHEAD6_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVB097_TEXHEAD6_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVB097_TEXHEAD6_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVB097_TEXHEAD6_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVB097_TEXHEAD6_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVB097_TEXHEAD6_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVB097_TEXHEAD6_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVB097_TEXHEAD6_ANISO_FINE_SPREAD_MODIFIER 31:30 +#define NVB097_TEXHEAD6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEAD6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEAD6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEAD6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEAD7_COLOR_KEY_VALUE 31:0 + + +/* +** Texture Header State Blocklinear + */ + +#define NVB097_TEXHEAD_BL_COMPONENTS MW(6:0) +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_R32 0x0000000f +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_R16 0x0000001b +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_R8 0x0000001d +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_R1 0x0000001f +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_EAC 0x00000019 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_Z16 0x0000003a +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVB097_TEXHEAD_BL_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVB097_TEXHEAD_BL_R_DATA_TYPE MW(9:7) +#define NVB097_TEXHEAD_BL_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_BL_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_BL_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_BL_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_BL_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_BL_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_BL_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BL_G_DATA_TYPE MW(12:10) +#define NVB097_TEXHEAD_BL_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_BL_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_BL_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_BL_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_BL_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_BL_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_BL_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BL_B_DATA_TYPE MW(15:13) +#define NVB097_TEXHEAD_BL_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_BL_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_BL_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_BL_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_BL_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_BL_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_BL_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BL_A_DATA_TYPE MW(18:16) +#define NVB097_TEXHEAD_BL_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_BL_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_BL_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_BL_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_BL_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_BL_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_BL_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BL_X_SOURCE MW(21:19) +#define NVB097_TEXHEAD_BL_X_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_BL_X_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_BL_X_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_BL_X_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_BL_X_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_BL_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_BL_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BL_Y_SOURCE MW(24:22) +#define NVB097_TEXHEAD_BL_Y_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_BL_Y_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_BL_Y_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_BL_Y_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_BL_Y_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_BL_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_BL_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BL_Z_SOURCE MW(27:25) +#define NVB097_TEXHEAD_BL_Z_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_BL_Z_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_BL_Z_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_BL_Z_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_BL_Z_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_BL_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_BL_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BL_W_SOURCE MW(30:28) +#define NVB097_TEXHEAD_BL_W_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_BL_W_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_BL_W_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_BL_W_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_BL_W_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_BL_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_BL_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BL_PACK_COMPONENTS MW(31:31) +#define NVB097_TEXHEAD_BL_RESERVED1Y MW(36:32) +#define NVB097_TEXHEAD_BL_GOB_DEPTH_OFFSET MW(38:37) +#define NVB097_TEXHEAD_BL_RESERVED1X MW(40:39) +#define NVB097_TEXHEAD_BL_ADDRESS_BITS31TO9 MW(63:41) +#define NVB097_TEXHEAD_BL_ADDRESS_BITS47TO32 MW(79:64) +#define NVB097_TEXHEAD_BL_RESERVED_ADDRESS MW(84:80) +#define NVB097_TEXHEAD_BL_HEADER_VERSION MW(87:85) +#define NVB097_TEXHEAD_BL_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVB097_TEXHEAD_BL_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVB097_TEXHEAD_BL_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVB097_TEXHEAD_BL_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVB097_TEXHEAD_BL_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVB097_TEXHEAD_BL_RESERVED_HEADER_VERSION MW(88:88) +#define NVB097_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVB097_TEXHEAD_BL_RESERVED2A MW(95:93) +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_WIDTH MW(98:96) +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT MW(101:99) +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH MW(104:102) +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEAD_BL_SPARSE_ENABLE MW(105:105) +#define NVB097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS MW(108:106) +#define NVB097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_ONE_GOB 0x00000000 +#define NVB097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_TWO_GOBS 0x00000001 +#define NVB097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEAD_BL_GOB3D MW(109:109) +#define NVB097_TEXHEAD_BL_USE_ARRAY_TILE_ALIGNMENT MW(110:110) +#define NVB097_TEXHEAD_BL_RESERVED3Z MW(111:111) +#define NVB097_TEXHEAD_BL_LOD_ANISO_QUALITY2 MW(112:112) +#define NVB097_TEXHEAD_BL_LOD_ANISO_QUALITY MW(113:113) +#define NVB097_TEXHEAD_BL_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEAD_BL_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEAD_BL_LOD_ISO_QUALITY MW(114:114) +#define NVB097_TEXHEAD_BL_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEAD_BL_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVB097_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEAD_BL_ANISO_SPREAD_SCALE MW(121:117) +#define NVB097_TEXHEAD_BL_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVB097_TEXHEAD_BL_DEPTH_TEXTURE MW(123:123) +#define NVB097_TEXHEAD_BL_MAX_MIP_LEVEL MW(127:124) +#define NVB097_TEXHEAD_BL_WIDTH_MINUS_ONE MW(143:128) +#define NVB097_TEXHEAD_BL_RESERVED4A MW(146:144) +#define NVB097_TEXHEAD_BL_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVB097_TEXHEAD_BL_S_R_G_B_CONVERSION MW(150:150) +#define NVB097_TEXHEAD_BL_TEXTURE_TYPE MW(154:151) +#define NVB097_TEXHEAD_BL_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVB097_TEXHEAD_BL_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVB097_TEXHEAD_BL_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVB097_TEXHEAD_BL_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVB097_TEXHEAD_BL_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVB097_TEXHEAD_BL_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVB097_TEXHEAD_BL_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVB097_TEXHEAD_BL_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVB097_TEXHEAD_BL_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVB097_TEXHEAD_BL_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVB097_TEXHEAD_BL_SECTOR_PROMOTION MW(156:155) +#define NVB097_TEXHEAD_BL_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVB097_TEXHEAD_BL_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVB097_TEXHEAD_BL_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVB097_TEXHEAD_BL_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVB097_TEXHEAD_BL_BORDER_SIZE MW(159:157) +#define NVB097_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVB097_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVB097_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVB097_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVB097_TEXHEAD_BL_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVB097_TEXHEAD_BL_HEIGHT_MINUS_ONE MW(175:160) +#define NVB097_TEXHEAD_BL_DEPTH_MINUS_ONE MW(189:176) +#define NVB097_TEXHEAD_BL_RESERVED5A MW(190:190) +#define NVB097_TEXHEAD_BL_NORMALIZED_COORDS MW(191:191) +#define NVB097_TEXHEAD_BL_RESERVED6Y MW(192:192) +#define NVB097_TEXHEAD_BL_TRILIN_OPT MW(197:193) +#define NVB097_TEXHEAD_BL_MIP_LOD_BIAS MW(210:198) +#define NVB097_TEXHEAD_BL_ANISO_BIAS MW(214:211) +#define NVB097_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVB097_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVB097_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEAD_BL_MAX_ANISOTROPY MW(221:219) +#define NVB097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVB097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVB097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVB097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVB097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVB097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVB097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVB097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVB097_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVB097_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEAD_BL_RES_VIEW_MIN_MIP_LEVEL MW(227:224) +#define NVB097_TEXHEAD_BL_RES_VIEW_MAX_MIP_LEVEL MW(231:228) +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT MW(235:232) +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X1_CENTER 0x0000000c +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2_CENTER 0x0000000d +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_CENTER 0x0000000e +#define NVB097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X4_REGULAR 0x0000000f +#define NVB097_TEXHEAD_BL_MIN_LOD_CLAMP MW(247:236) +#define NVB097_TEXHEAD_BL_RESERVED7Y MW(255:248) + + +/* +** Texture Header State Blocklinear Color Key + */ + +#define NVB097_TEXHEAD_BLCK_COMPONENTS MW(6:0) +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_R32 0x0000000f +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_R16 0x0000001b +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_R8 0x0000001d +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_R1 0x0000001f +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_EAC 0x00000019 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_Z16 0x0000003a +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVB097_TEXHEAD_BLCK_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVB097_TEXHEAD_BLCK_R_DATA_TYPE MW(9:7) +#define NVB097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BLCK_G_DATA_TYPE MW(12:10) +#define NVB097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BLCK_B_DATA_TYPE MW(15:13) +#define NVB097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BLCK_A_DATA_TYPE MW(18:16) +#define NVB097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BLCK_X_SOURCE MW(21:19) +#define NVB097_TEXHEAD_BLCK_X_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_BLCK_X_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_BLCK_X_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_BLCK_X_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_BLCK_X_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_BLCK_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_BLCK_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BLCK_Y_SOURCE MW(24:22) +#define NVB097_TEXHEAD_BLCK_Y_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_BLCK_Y_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_BLCK_Y_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_BLCK_Y_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_BLCK_Y_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_BLCK_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_BLCK_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BLCK_Z_SOURCE MW(27:25) +#define NVB097_TEXHEAD_BLCK_Z_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_BLCK_Z_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_BLCK_Z_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_BLCK_Z_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_BLCK_Z_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_BLCK_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_BLCK_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BLCK_W_SOURCE MW(30:28) +#define NVB097_TEXHEAD_BLCK_W_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_BLCK_W_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_BLCK_W_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_BLCK_W_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_BLCK_W_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_BLCK_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_BLCK_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_BLCK_PACK_COMPONENTS MW(31:31) +#define NVB097_TEXHEAD_BLCK_RESERVED1Y MW(36:32) +#define NVB097_TEXHEAD_BLCK_GOB_DEPTH_OFFSET MW(38:37) +#define NVB097_TEXHEAD_BLCK_RESERVED1X MW(40:39) +#define NVB097_TEXHEAD_BLCK_ADDRESS_BITS31TO9 MW(63:41) +#define NVB097_TEXHEAD_BLCK_ADDRESS_BITS47TO32 MW(79:64) +#define NVB097_TEXHEAD_BLCK_RESERVED_ADDRESS MW(84:80) +#define NVB097_TEXHEAD_BLCK_HEADER_VERSION MW(87:85) +#define NVB097_TEXHEAD_BLCK_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVB097_TEXHEAD_BLCK_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVB097_TEXHEAD_BLCK_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVB097_TEXHEAD_BLCK_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVB097_TEXHEAD_BLCK_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVB097_TEXHEAD_BLCK_RESERVED_HEADER_VERSION MW(88:88) +#define NVB097_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVB097_TEXHEAD_BLCK_RESERVED2A MW(95:93) +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_WIDTH MW(98:96) +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT MW(101:99) +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH MW(104:102) +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEAD_BLCK_SPARSE_ENABLE MW(105:105) +#define NVB097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS MW(108:106) +#define NVB097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_ONE_GOB 0x00000000 +#define NVB097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_TWO_GOBS 0x00000001 +#define NVB097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEAD_BLCK_GOB3D MW(109:109) +#define NVB097_TEXHEAD_BLCK_USE_ARRAY_TILE_ALIGNMENT MW(110:110) +#define NVB097_TEXHEAD_BLCK_RESERVED3Z MW(111:111) +#define NVB097_TEXHEAD_BLCK_LOD_ANISO_QUALITY2 MW(112:112) +#define NVB097_TEXHEAD_BLCK_LOD_ANISO_QUALITY MW(113:113) +#define NVB097_TEXHEAD_BLCK_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEAD_BLCK_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEAD_BLCK_LOD_ISO_QUALITY MW(114:114) +#define NVB097_TEXHEAD_BLCK_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEAD_BLCK_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVB097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEAD_BLCK_ANISO_SPREAD_SCALE MW(121:117) +#define NVB097_TEXHEAD_BLCK_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVB097_TEXHEAD_BLCK_DEPTH_TEXTURE MW(123:123) +#define NVB097_TEXHEAD_BLCK_MAX_MIP_LEVEL MW(127:124) +#define NVB097_TEXHEAD_BLCK_WIDTH_MINUS_ONE MW(143:128) +#define NVB097_TEXHEAD_BLCK_RESERVED4A MW(146:144) +#define NVB097_TEXHEAD_BLCK_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVB097_TEXHEAD_BLCK_S_R_G_B_CONVERSION MW(150:150) +#define NVB097_TEXHEAD_BLCK_TEXTURE_TYPE MW(154:151) +#define NVB097_TEXHEAD_BLCK_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVB097_TEXHEAD_BLCK_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVB097_TEXHEAD_BLCK_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVB097_TEXHEAD_BLCK_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVB097_TEXHEAD_BLCK_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVB097_TEXHEAD_BLCK_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVB097_TEXHEAD_BLCK_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVB097_TEXHEAD_BLCK_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVB097_TEXHEAD_BLCK_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVB097_TEXHEAD_BLCK_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVB097_TEXHEAD_BLCK_SECTOR_PROMOTION MW(156:155) +#define NVB097_TEXHEAD_BLCK_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVB097_TEXHEAD_BLCK_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVB097_TEXHEAD_BLCK_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVB097_TEXHEAD_BLCK_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVB097_TEXHEAD_BLCK_BORDER_SIZE MW(159:157) +#define NVB097_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVB097_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVB097_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVB097_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVB097_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVB097_TEXHEAD_BLCK_HEIGHT_MINUS_ONE MW(175:160) +#define NVB097_TEXHEAD_BLCK_DEPTH_MINUS_ONE MW(189:176) +#define NVB097_TEXHEAD_BLCK_RESERVED5A MW(190:190) +#define NVB097_TEXHEAD_BLCK_NORMALIZED_COORDS MW(191:191) +#define NVB097_TEXHEAD_BLCK_COLOR_KEY_OP MW(192:192) +#define NVB097_TEXHEAD_BLCK_TRILIN_OPT MW(197:193) +#define NVB097_TEXHEAD_BLCK_MIP_LOD_BIAS MW(210:198) +#define NVB097_TEXHEAD_BLCK_ANISO_BIAS MW(214:211) +#define NVB097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVB097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVB097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEAD_BLCK_MAX_ANISOTROPY MW(221:219) +#define NVB097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVB097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVB097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVB097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVB097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVB097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVB097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVB097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVB097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVB097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEAD_BLCK_COLOR_KEY_VALUE MW(255:224) + + +/* +** Texture Header State One-D Buffer + */ + +#define NVB097_TEXHEAD_1D_COMPONENTS MW(6:0) +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_R32 0x0000000f +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_R16 0x0000001b +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_R8 0x0000001d +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_R1 0x0000001f +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_EAC 0x00000019 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_Z16 0x0000003a +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVB097_TEXHEAD_1D_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVB097_TEXHEAD_1D_R_DATA_TYPE MW(9:7) +#define NVB097_TEXHEAD_1D_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_1D_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_1D_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_1D_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_1D_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_1D_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_1D_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_1D_G_DATA_TYPE MW(12:10) +#define NVB097_TEXHEAD_1D_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_1D_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_1D_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_1D_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_1D_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_1D_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_1D_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_1D_B_DATA_TYPE MW(15:13) +#define NVB097_TEXHEAD_1D_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_1D_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_1D_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_1D_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_1D_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_1D_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_1D_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_1D_A_DATA_TYPE MW(18:16) +#define NVB097_TEXHEAD_1D_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_1D_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_1D_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_1D_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_1D_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_1D_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_1D_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_1D_X_SOURCE MW(21:19) +#define NVB097_TEXHEAD_1D_X_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_1D_X_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_1D_X_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_1D_X_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_1D_X_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_1D_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_1D_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_1D_Y_SOURCE MW(24:22) +#define NVB097_TEXHEAD_1D_Y_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_1D_Y_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_1D_Y_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_1D_Y_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_1D_Y_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_1D_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_1D_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_1D_Z_SOURCE MW(27:25) +#define NVB097_TEXHEAD_1D_Z_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_1D_Z_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_1D_Z_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_1D_Z_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_1D_Z_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_1D_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_1D_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_1D_W_SOURCE MW(30:28) +#define NVB097_TEXHEAD_1D_W_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_1D_W_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_1D_W_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_1D_W_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_1D_W_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_1D_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_1D_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_1D_PACK_COMPONENTS MW(31:31) +#define NVB097_TEXHEAD_1D_ADDRESS_BITS31TO0 MW(63:32) +#define NVB097_TEXHEAD_1D_ADDRESS_BITS47TO32 MW(79:64) +#define NVB097_TEXHEAD_1D_RESERVED_ADDRESS MW(84:80) +#define NVB097_TEXHEAD_1D_HEADER_VERSION MW(87:85) +#define NVB097_TEXHEAD_1D_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVB097_TEXHEAD_1D_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVB097_TEXHEAD_1D_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVB097_TEXHEAD_1D_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVB097_TEXHEAD_1D_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVB097_TEXHEAD_1D_RESERVED_HEADER_VERSION MW(88:88) +#define NVB097_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVB097_TEXHEAD_1D_RESERVED2A MW(95:93) +#define NVB097_TEXHEAD_1D_WIDTH_MINUS_ONE_BITS31TO16 MW(111:96) +#define NVB097_TEXHEAD_1D_RESERVED3X MW(127:112) +#define NVB097_TEXHEAD_1D_WIDTH_MINUS_ONE_BITS15TO0 MW(143:128) +#define NVB097_TEXHEAD_1D_RESERVED4A MW(146:144) +#define NVB097_TEXHEAD_1D_RESERVED4X MW(149:147) +#define NVB097_TEXHEAD_1D_S_R_G_B_CONVERSION MW(150:150) +#define NVB097_TEXHEAD_1D_TEXTURE_TYPE MW(154:151) +#define NVB097_TEXHEAD_1D_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVB097_TEXHEAD_1D_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVB097_TEXHEAD_1D_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVB097_TEXHEAD_1D_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVB097_TEXHEAD_1D_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVB097_TEXHEAD_1D_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVB097_TEXHEAD_1D_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVB097_TEXHEAD_1D_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVB097_TEXHEAD_1D_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVB097_TEXHEAD_1D_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVB097_TEXHEAD_1D_SECTOR_PROMOTION MW(156:155) +#define NVB097_TEXHEAD_1D_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVB097_TEXHEAD_1D_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVB097_TEXHEAD_1D_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVB097_TEXHEAD_1D_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVB097_TEXHEAD_1D_RESERVED4Y MW(159:157) +#define NVB097_TEXHEAD_1D_RESERVED5X MW(189:160) +#define NVB097_TEXHEAD_1D_RESERVED5A MW(190:190) +#define NVB097_TEXHEAD_1D_RESERVED5Y MW(191:191) +#define NVB097_TEXHEAD_1D_RESERVED6X MW(223:192) +#define NVB097_TEXHEAD_1D_RESERVED7X MW(255:224) + + +/* +** Texture Header State Pitch + */ + +#define NVB097_TEXHEAD_PITCH_COMPONENTS MW(6:0) +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_R32 0x0000000f +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_R16 0x0000001b +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_R8 0x0000001d +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_R1 0x0000001f +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_EAC 0x00000019 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_Z16 0x0000003a +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVB097_TEXHEAD_PITCH_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVB097_TEXHEAD_PITCH_R_DATA_TYPE MW(9:7) +#define NVB097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCH_G_DATA_TYPE MW(12:10) +#define NVB097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCH_B_DATA_TYPE MW(15:13) +#define NVB097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCH_A_DATA_TYPE MW(18:16) +#define NVB097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCH_X_SOURCE MW(21:19) +#define NVB097_TEXHEAD_PITCH_X_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_PITCH_X_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_PITCH_X_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_PITCH_X_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_PITCH_X_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_PITCH_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_PITCH_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCH_Y_SOURCE MW(24:22) +#define NVB097_TEXHEAD_PITCH_Y_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_PITCH_Y_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_PITCH_Y_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_PITCH_Y_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_PITCH_Y_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_PITCH_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_PITCH_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCH_Z_SOURCE MW(27:25) +#define NVB097_TEXHEAD_PITCH_Z_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_PITCH_Z_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_PITCH_Z_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_PITCH_Z_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_PITCH_Z_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_PITCH_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_PITCH_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCH_W_SOURCE MW(30:28) +#define NVB097_TEXHEAD_PITCH_W_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_PITCH_W_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_PITCH_W_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_PITCH_W_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_PITCH_W_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_PITCH_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_PITCH_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCH_PACK_COMPONENTS MW(31:31) +#define NVB097_TEXHEAD_PITCH_RESERVED1A MW(36:32) +#define NVB097_TEXHEAD_PITCH_ADDRESS_BITS31TO5 MW(63:37) +#define NVB097_TEXHEAD_PITCH_ADDRESS_BITS47TO32 MW(79:64) +#define NVB097_TEXHEAD_PITCH_RESERVED_ADDRESS MW(84:80) +#define NVB097_TEXHEAD_PITCH_HEADER_VERSION MW(87:85) +#define NVB097_TEXHEAD_PITCH_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVB097_TEXHEAD_PITCH_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVB097_TEXHEAD_PITCH_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVB097_TEXHEAD_PITCH_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVB097_TEXHEAD_PITCH_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVB097_TEXHEAD_PITCH_RESERVED_HEADER_VERSION MW(88:88) +#define NVB097_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVB097_TEXHEAD_PITCH_RESERVED2A MW(95:93) +#define NVB097_TEXHEAD_PITCH_PITCH_BITS20TO5 MW(111:96) +#define NVB097_TEXHEAD_PITCH_LOD_ANISO_QUALITY2 MW(112:112) +#define NVB097_TEXHEAD_PITCH_LOD_ANISO_QUALITY MW(113:113) +#define NVB097_TEXHEAD_PITCH_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEAD_PITCH_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEAD_PITCH_LOD_ISO_QUALITY MW(114:114) +#define NVB097_TEXHEAD_PITCH_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEAD_PITCH_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVB097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEAD_PITCH_ANISO_SPREAD_SCALE MW(121:117) +#define NVB097_TEXHEAD_PITCH_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVB097_TEXHEAD_PITCH_DEPTH_TEXTURE MW(123:123) +#define NVB097_TEXHEAD_PITCH_MAX_MIP_LEVEL MW(127:124) +#define NVB097_TEXHEAD_PITCH_WIDTH_MINUS_ONE MW(143:128) +#define NVB097_TEXHEAD_PITCH_RESERVED4A MW(146:144) +#define NVB097_TEXHEAD_PITCH_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVB097_TEXHEAD_PITCH_S_R_G_B_CONVERSION MW(150:150) +#define NVB097_TEXHEAD_PITCH_TEXTURE_TYPE MW(154:151) +#define NVB097_TEXHEAD_PITCH_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVB097_TEXHEAD_PITCH_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVB097_TEXHEAD_PITCH_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVB097_TEXHEAD_PITCH_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVB097_TEXHEAD_PITCH_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVB097_TEXHEAD_PITCH_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVB097_TEXHEAD_PITCH_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVB097_TEXHEAD_PITCH_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVB097_TEXHEAD_PITCH_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVB097_TEXHEAD_PITCH_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVB097_TEXHEAD_PITCH_SECTOR_PROMOTION MW(156:155) +#define NVB097_TEXHEAD_PITCH_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVB097_TEXHEAD_PITCH_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVB097_TEXHEAD_PITCH_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVB097_TEXHEAD_PITCH_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVB097_TEXHEAD_PITCH_BORDER_SIZE MW(159:157) +#define NVB097_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVB097_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVB097_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVB097_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVB097_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVB097_TEXHEAD_PITCH_HEIGHT_MINUS_ONE MW(175:160) +#define NVB097_TEXHEAD_PITCH_DEPTH_MINUS_ONE MW(189:176) +#define NVB097_TEXHEAD_PITCH_RESERVED5A MW(190:190) +#define NVB097_TEXHEAD_PITCH_NORMALIZED_COORDS MW(191:191) +#define NVB097_TEXHEAD_PITCH_RESERVED6Y MW(192:192) +#define NVB097_TEXHEAD_PITCH_TRILIN_OPT MW(197:193) +#define NVB097_TEXHEAD_PITCH_MIP_LOD_BIAS MW(210:198) +#define NVB097_TEXHEAD_PITCH_ANISO_BIAS MW(214:211) +#define NVB097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVB097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVB097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEAD_PITCH_MAX_ANISOTROPY MW(221:219) +#define NVB097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVB097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVB097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVB097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVB097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVB097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVB097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVB097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVB097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVB097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEAD_PITCH_RES_VIEW_MIN_MIP_LEVEL MW(227:224) +#define NVB097_TEXHEAD_PITCH_RES_VIEW_MAX_MIP_LEVEL MW(231:228) +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT MW(235:232) +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X1_CENTER 0x0000000c +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2_CENTER 0x0000000d +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_CENTER 0x0000000e +#define NVB097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X4_REGULAR 0x0000000f +#define NVB097_TEXHEAD_PITCH_MIN_LOD_CLAMP MW(247:236) +#define NVB097_TEXHEAD_PITCH_RESERVED7Y MW(255:248) + + +/* +** Texture Header State Pitch Color Key + */ + +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS MW(6:0) +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32 0x0000000f +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R16 0x0000001b +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R8 0x0000001d +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R1 0x0000001f +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_EAC 0x00000019 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_Z16 0x0000003a +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVB097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVB097_TEXHEAD_PITCHCK_R_DATA_TYPE MW(9:7) +#define NVB097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_G_DATA_TYPE MW(12:10) +#define NVB097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_B_DATA_TYPE MW(15:13) +#define NVB097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_A_DATA_TYPE MW(18:16) +#define NVB097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_X_SOURCE MW(21:19) +#define NVB097_TEXHEAD_PITCHCK_X_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_X_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_X_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_X_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_X_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_PITCHCK_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_PITCHCK_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_Y_SOURCE MW(24:22) +#define NVB097_TEXHEAD_PITCHCK_Y_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_Y_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_Y_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_Y_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_Y_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_PITCHCK_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_PITCHCK_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_Z_SOURCE MW(27:25) +#define NVB097_TEXHEAD_PITCHCK_Z_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_Z_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_Z_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_Z_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_Z_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_PITCHCK_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_PITCHCK_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_W_SOURCE MW(30:28) +#define NVB097_TEXHEAD_PITCHCK_W_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_W_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_W_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_W_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_W_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEAD_PITCHCK_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEAD_PITCHCK_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_PACK_COMPONENTS MW(31:31) +#define NVB097_TEXHEAD_PITCHCK_RESERVED1A MW(36:32) +#define NVB097_TEXHEAD_PITCHCK_ADDRESS_BITS31TO5 MW(63:37) +#define NVB097_TEXHEAD_PITCHCK_ADDRESS_BITS47TO32 MW(79:64) +#define NVB097_TEXHEAD_PITCHCK_RESERVED_ADDRESS MW(84:80) +#define NVB097_TEXHEAD_PITCHCK_HEADER_VERSION MW(87:85) +#define NVB097_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_RESERVED_HEADER_VERSION MW(88:88) +#define NVB097_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVB097_TEXHEAD_PITCHCK_RESERVED2A MW(95:93) +#define NVB097_TEXHEAD_PITCHCK_PITCH_BITS20TO5 MW(111:96) +#define NVB097_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY2 MW(112:112) +#define NVB097_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY MW(113:113) +#define NVB097_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_LOD_ISO_QUALITY MW(114:114) +#define NVB097_TEXHEAD_PITCHCK_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVB097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_ANISO_SPREAD_SCALE MW(121:117) +#define NVB097_TEXHEAD_PITCHCK_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVB097_TEXHEAD_PITCHCK_DEPTH_TEXTURE MW(123:123) +#define NVB097_TEXHEAD_PITCHCK_MAX_MIP_LEVEL MW(127:124) +#define NVB097_TEXHEAD_PITCHCK_WIDTH_MINUS_ONE MW(143:128) +#define NVB097_TEXHEAD_PITCHCK_RESERVED4A MW(146:144) +#define NVB097_TEXHEAD_PITCHCK_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVB097_TEXHEAD_PITCHCK_S_R_G_B_CONVERSION MW(150:150) +#define NVB097_TEXHEAD_PITCHCK_TEXTURE_TYPE MW(154:151) +#define NVB097_TEXHEAD_PITCHCK_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVB097_TEXHEAD_PITCHCK_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVB097_TEXHEAD_PITCHCK_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVB097_TEXHEAD_PITCHCK_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVB097_TEXHEAD_PITCHCK_SECTOR_PROMOTION MW(156:155) +#define NVB097_TEXHEAD_PITCHCK_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_BORDER_SIZE MW(159:157) +#define NVB097_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_HEIGHT_MINUS_ONE MW(175:160) +#define NVB097_TEXHEAD_PITCHCK_DEPTH_MINUS_ONE MW(189:176) +#define NVB097_TEXHEAD_PITCHCK_RESERVED5A MW(190:190) +#define NVB097_TEXHEAD_PITCHCK_NORMALIZED_COORDS MW(191:191) +#define NVB097_TEXHEAD_PITCHCK_COLOR_KEY_OP MW(192:192) +#define NVB097_TEXHEAD_PITCHCK_TRILIN_OPT MW(197:193) +#define NVB097_TEXHEAD_PITCHCK_MIP_LOD_BIAS MW(210:198) +#define NVB097_TEXHEAD_PITCHCK_ANISO_BIAS MW(214:211) +#define NVB097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVB097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVB097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_MAX_ANISOTROPY MW(221:219) +#define NVB097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVB097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVB097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVB097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVB097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVB097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEAD_PITCHCK_COLOR_KEY_VALUE MW(255:224) + + +/* +** Texture Header State, Version 2 + */ + +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES 5:0 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_R32_G32_B32_A32 0x00000001 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_R32_G32_B32 0x00000002 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_R16_G16_B16_A16 0x00000003 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_R32_G32 0x00000004 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_R32_B24G8 0x00000005 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_X8B8G8R8 0x00000007 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_A8B8G8R8 0x00000008 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_A2B10G10R10 0x00000009 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_R16_G16 0x0000000c +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_G8R24 0x0000000d +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_G24R8 0x0000000e +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_R32 0x0000000f +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_A4B4G4R4 0x00000012 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_A5B5G5R1 0x00000013 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_A1B5G5R5 0x00000014 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_B5G6R5 0x00000015 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_B6G5R5 0x00000016 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_G8R8 0x00000018 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_R16 0x0000001b +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_Y8_VIDEO 0x0000001c +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_R8 0x0000001d +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_G4R4 0x0000001e +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_R1 0x0000001f +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_BF10GF11RF11 0x00000021 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_G8B8G8R8 0x00000022 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_B8G8R8G8 0x00000023 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_DXT1 0x00000024 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_DXT23 0x00000025 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_DXT45 0x00000026 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_DXN1 0x00000027 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_DXN2 0x00000028 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_BC6H_SF16 0x00000010 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_BC6H_UF16 0x00000011 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_BC7U 0x00000017 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ETC2_RGB 0x00000006 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ETC2_RGBA 0x0000000b +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_EAC 0x00000019 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_EACX2 0x0000001a +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_Z24S8 0x00000029 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_X8Z24 0x0000002a +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_S8Z24 0x0000002b +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ZF32 0x0000002f +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ZF32_X24S8 0x00000030 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_Z16 0x0000003a +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVB097_TEXHEADV2_0_COMPONENT_SIZES_CS_BITFIELD_SIZE 0x0000003f +#define NVB097_TEXHEADV2_0_R_DATA_TYPE 8:6 +#define NVB097_TEXHEADV2_0_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEADV2_0_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEADV2_0_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEADV2_0_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEADV2_0_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEADV2_0_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEADV2_0_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEADV2_0_G_DATA_TYPE 11:9 +#define NVB097_TEXHEADV2_0_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEADV2_0_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEADV2_0_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEADV2_0_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEADV2_0_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEADV2_0_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEADV2_0_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEADV2_0_B_DATA_TYPE 14:12 +#define NVB097_TEXHEADV2_0_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEADV2_0_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEADV2_0_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEADV2_0_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEADV2_0_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEADV2_0_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEADV2_0_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEADV2_0_A_DATA_TYPE 17:15 +#define NVB097_TEXHEADV2_0_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEADV2_0_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEADV2_0_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEADV2_0_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEADV2_0_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEADV2_0_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEADV2_0_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEADV2_0_X_SOURCE 20:18 +#define NVB097_TEXHEADV2_0_X_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEADV2_0_X_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEADV2_0_X_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEADV2_0_X_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEADV2_0_X_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEADV2_0_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEADV2_0_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEADV2_0_Y_SOURCE 23:21 +#define NVB097_TEXHEADV2_0_Y_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEADV2_0_Y_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEADV2_0_Y_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEADV2_0_Y_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEADV2_0_Y_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEADV2_0_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEADV2_0_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEADV2_0_Z_SOURCE 26:24 +#define NVB097_TEXHEADV2_0_Z_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEADV2_0_Z_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEADV2_0_Z_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEADV2_0_Z_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEADV2_0_Z_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEADV2_0_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEADV2_0_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEADV2_0_W_SOURCE 29:27 +#define NVB097_TEXHEADV2_0_W_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEADV2_0_W_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEADV2_0_W_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEADV2_0_W_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEADV2_0_W_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEADV2_0_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEADV2_0_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEADV2_0_PACK_COMPONENTS 30:30 +#define NVB097_TEXHEADV2_0_USE_COMPONENT_SIZES_EXTENDED 31:31 +#define NVB097_TEXHEADV2_1_OFFSET_LOWER 31:0 +#define NVB097_TEXHEADV2_2_OFFSET_UPPER 7:0 +#define NVB097_TEXHEADV2_2_ANISO_SPREAD_MAX_LOG2_L_S_B 9:8 +#define NVB097_TEXHEADV2_2_S_R_G_B_CONVERSION 10:10 +#define NVB097_TEXHEADV2_2_ANISO_SPREAD_MAX_LOG2_M_S_B 11:11 +#define NVB097_TEXHEADV2_2_LOD_ANISO_QUALITY2 12:12 +#define NVB097_TEXHEADV2_2_COLOR_KEY_OP 13:13 +#define NVB097_TEXHEADV2_2_TEXTURE_TYPE 17:14 +#define NVB097_TEXHEADV2_2_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVB097_TEXHEADV2_2_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVB097_TEXHEADV2_2_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVB097_TEXHEADV2_2_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVB097_TEXHEADV2_2_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVB097_TEXHEADV2_2_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVB097_TEXHEADV2_2_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVB097_TEXHEADV2_2_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVB097_TEXHEADV2_2_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVB097_TEXHEADV2_2_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVB097_TEXHEADV2_2_MEMORY_LAYOUT 18:18 +#define NVB097_TEXHEADV2_2_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB097_TEXHEADV2_2_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_WIDTH 21:19 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_HEIGHT 24:22 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_DEPTH 27:25 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEADV2_2_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEADV2_2_SECTOR_PROMOTION 29:28 +#define NVB097_TEXHEADV2_2_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVB097_TEXHEADV2_2_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVB097_TEXHEADV2_2_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVB097_TEXHEADV2_2_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVB097_TEXHEADV2_2_BORDER_SOURCE 30:30 +#define NVB097_TEXHEADV2_2_BORDER_SOURCE_BORDER_TEXTURE 0x00000000 +#define NVB097_TEXHEADV2_2_BORDER_SOURCE_BORDER_COLOR 0x00000001 +#define NVB097_TEXHEADV2_2_NORMALIZED_COORDS 31:31 +#define NVB097_TEXHEADV2_3_PITCH 19:0 +#define NVB097_TEXHEADV2_3_LOD_ANISO_QUALITY 20:20 +#define NVB097_TEXHEADV2_3_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEADV2_3_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEADV2_3_LOD_ISO_QUALITY 21:21 +#define NVB097_TEXHEADV2_3_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEADV2_3_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEADV2_3_ANISO_COARSE_SPREAD_MODIFIER 23:22 +#define NVB097_TEXHEADV2_3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEADV2_3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEADV2_3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEADV2_3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEADV2_3_ANISO_SPREAD_SCALE 28:24 +#define NVB097_TEXHEADV2_3_USE_HEADER_OPT_CONTROL 29:29 +#define NVB097_TEXHEADV2_3_RESERVED3A 30:30 +#define NVB097_TEXHEADV2_3_RESERVED3B 31:31 +#define NVB097_TEXHEADV2_4_WIDTH 29:0 +#define NVB097_TEXHEADV2_4_DEPTH_TEXTURE 30:30 +#define NVB097_TEXHEADV2_4_USE_TEXTURE_HEADER_VERSION2 31:31 +#define NVB097_TEXHEADV2_5_HEIGHT 15:0 +#define NVB097_TEXHEADV2_5_DEPTH 27:16 +#define NVB097_TEXHEADV2_5_MAX_MIP_LEVEL 31:28 +#define NVB097_TEXHEADV2_6_TRILIN_OPT 4:0 +#define NVB097_TEXHEADV2_6_MIP_LOD_BIAS 17:5 +#define NVB097_TEXHEADV2_6_RESERVED6A 18:18 +#define NVB097_TEXHEADV2_6_ANISO_BIAS 22:19 +#define NVB097_TEXHEADV2_6_ANISO_FINE_SPREAD_FUNC 24:23 +#define NVB097_TEXHEADV2_6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEADV2_6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEADV2_6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEADV2_6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEADV2_6_ANISO_COARSE_SPREAD_FUNC 26:25 +#define NVB097_TEXHEADV2_6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEADV2_6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEADV2_6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEADV2_6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEADV2_6_MAX_ANISOTROPY 29:27 +#define NVB097_TEXHEADV2_6_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVB097_TEXHEADV2_6_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVB097_TEXHEADV2_6_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVB097_TEXHEADV2_6_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVB097_TEXHEADV2_6_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVB097_TEXHEADV2_6_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVB097_TEXHEADV2_6_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVB097_TEXHEADV2_6_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVB097_TEXHEADV2_6_ANISO_FINE_SPREAD_MODIFIER 31:30 +#define NVB097_TEXHEADV2_6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEADV2_6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEADV2_6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEADV2_6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEADV2_7_RES_VIEW_MIN_MIP_LEVEL 3:0 +#define NVB097_TEXHEADV2_7_RES_VIEW_MAX_MIP_LEVEL 7:4 +#define NVB097_TEXHEADV2_7_HEIGHT_MSB 8:8 +#define NVB097_TEXHEADV2_7_HEIGHT_MSB_RESERVED 11:9 +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT 15:12 +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_2X1_CENTER 0x0000000c +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_2X2_CENTER 0x0000000d +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_4X2_CENTER 0x0000000e +#define NVB097_TEXHEADV2_7_MULTI_SAMPLE_COUNT_MODE_4X4_REGULAR 0x0000000f +#define NVB097_TEXHEADV2_7_MIN_LOD_CLAMP 27:16 +#define NVB097_TEXHEADV2_7_DEPTH_MSB 30:28 +#define NVB097_TEXHEADV2_7_RESERVED7A 31:31 + + +/* +** Texture Header State, Version 3 + */ + +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES 5:0 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_4X4 0x00000000 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_5X4 0x00000010 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_5X5 0x00000001 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_6X5 0x00000011 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_6X6 0x00000002 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_8X5 0x00000015 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_8X6 0x00000012 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_8X8 0x00000004 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_10X5 0x00000016 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_10X6 0x00000017 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_10X8 0x00000013 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_10X10 0x00000005 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_12X10 0x00000014 +#define NVB097_TEXHEADV3_0_COMPONENT_SIZES_ASTC_2D_12X12 0x00000006 +#define NVB097_TEXHEADV3_0_R_DATA_TYPE 8:6 +#define NVB097_TEXHEADV3_0_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEADV3_0_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEADV3_0_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEADV3_0_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEADV3_0_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEADV3_0_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEADV3_0_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEADV3_0_G_DATA_TYPE 11:9 +#define NVB097_TEXHEADV3_0_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEADV3_0_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEADV3_0_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEADV3_0_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEADV3_0_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEADV3_0_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEADV3_0_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEADV3_0_B_DATA_TYPE 14:12 +#define NVB097_TEXHEADV3_0_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEADV3_0_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEADV3_0_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEADV3_0_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEADV3_0_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEADV3_0_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEADV3_0_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEADV3_0_A_DATA_TYPE 17:15 +#define NVB097_TEXHEADV3_0_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVB097_TEXHEADV3_0_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVB097_TEXHEADV3_0_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVB097_TEXHEADV3_0_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVB097_TEXHEADV3_0_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVB097_TEXHEADV3_0_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVB097_TEXHEADV3_0_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVB097_TEXHEADV3_0_X_SOURCE 20:18 +#define NVB097_TEXHEADV3_0_X_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEADV3_0_X_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEADV3_0_X_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEADV3_0_X_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEADV3_0_X_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEADV3_0_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEADV3_0_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEADV3_0_Y_SOURCE 23:21 +#define NVB097_TEXHEADV3_0_Y_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEADV3_0_Y_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEADV3_0_Y_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEADV3_0_Y_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEADV3_0_Y_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEADV3_0_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEADV3_0_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEADV3_0_Z_SOURCE 26:24 +#define NVB097_TEXHEADV3_0_Z_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEADV3_0_Z_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEADV3_0_Z_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEADV3_0_Z_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEADV3_0_Z_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEADV3_0_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEADV3_0_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEADV3_0_W_SOURCE 29:27 +#define NVB097_TEXHEADV3_0_W_SOURCE_IN_ZERO 0x00000000 +#define NVB097_TEXHEADV3_0_W_SOURCE_IN_R 0x00000002 +#define NVB097_TEXHEADV3_0_W_SOURCE_IN_G 0x00000003 +#define NVB097_TEXHEADV3_0_W_SOURCE_IN_B 0x00000004 +#define NVB097_TEXHEADV3_0_W_SOURCE_IN_A 0x00000005 +#define NVB097_TEXHEADV3_0_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVB097_TEXHEADV3_0_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVB097_TEXHEADV3_0_PACK_COMPONENTS 30:30 +#define NVB097_TEXHEADV3_0_USE_COMPONENT_SIZES_EXTENDED 31:31 +#define NVB097_TEXHEADV3_1_OFFSET_LOWER 31:0 +#define NVB097_TEXHEADV3_2_OFFSET_UPPER 7:0 +#define NVB097_TEXHEADV3_2_ANISO_SPREAD_MAX_LOG2_L_S_B 9:8 +#define NVB097_TEXHEADV3_2_S_R_G_B_CONVERSION 10:10 +#define NVB097_TEXHEADV3_2_ANISO_SPREAD_MAX_LOG2_M_S_B 11:11 +#define NVB097_TEXHEADV3_2_LOD_ANISO_QUALITY2 12:12 +#define NVB097_TEXHEADV3_2_COLOR_KEY_OP 13:13 +#define NVB097_TEXHEADV3_2_TEXTURE_TYPE 17:14 +#define NVB097_TEXHEADV3_2_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVB097_TEXHEADV3_2_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVB097_TEXHEADV3_2_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVB097_TEXHEADV3_2_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVB097_TEXHEADV3_2_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVB097_TEXHEADV3_2_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVB097_TEXHEADV3_2_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVB097_TEXHEADV3_2_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVB097_TEXHEADV3_2_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVB097_TEXHEADV3_2_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVB097_TEXHEADV3_2_MEMORY_LAYOUT 18:18 +#define NVB097_TEXHEADV3_2_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB097_TEXHEADV3_2_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_WIDTH 21:19 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_HEIGHT 24:22 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_DEPTH 27:25 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB097_TEXHEADV3_2_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVB097_TEXHEADV3_2_SECTOR_PROMOTION 29:28 +#define NVB097_TEXHEADV3_2_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVB097_TEXHEADV3_2_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVB097_TEXHEADV3_2_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVB097_TEXHEADV3_2_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVB097_TEXHEADV3_2_BORDER_SOURCE 30:30 +#define NVB097_TEXHEADV3_2_BORDER_SOURCE_BORDER_TEXTURE 0x00000000 +#define NVB097_TEXHEADV3_2_BORDER_SOURCE_BORDER_COLOR 0x00000001 +#define NVB097_TEXHEADV3_2_NORMALIZED_COORDS 31:31 +#define NVB097_TEXHEADV3_3_PITCH 19:0 +#define NVB097_TEXHEADV3_3_LOD_ANISO_QUALITY 20:20 +#define NVB097_TEXHEADV3_3_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEADV3_3_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEADV3_3_LOD_ISO_QUALITY 21:21 +#define NVB097_TEXHEADV3_3_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVB097_TEXHEADV3_3_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVB097_TEXHEADV3_3_ANISO_COARSE_SPREAD_MODIFIER 23:22 +#define NVB097_TEXHEADV3_3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEADV3_3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEADV3_3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEADV3_3_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEADV3_3_ANISO_SPREAD_SCALE 28:24 +#define NVB097_TEXHEADV3_3_USE_HEADER_OPT_CONTROL 29:29 +#define NVB097_TEXHEADV3_3_RESERVED3A 30:30 +#define NVB097_TEXHEADV3_3_RESERVED3B 31:31 +#define NVB097_TEXHEADV3_4_WIDTH 29:0 +#define NVB097_TEXHEADV3_4_DEPTH_TEXTURE 30:30 +#define NVB097_TEXHEADV3_4_USE_TEXTURE_HEADER_VERSION2 31:31 +#define NVB097_TEXHEADV3_5_HEIGHT 15:0 +#define NVB097_TEXHEADV3_5_DEPTH 27:16 +#define NVB097_TEXHEADV3_5_MAX_MIP_LEVEL 31:28 +#define NVB097_TEXHEADV3_6_TRILIN_OPT 4:0 +#define NVB097_TEXHEADV3_6_MIP_LOD_BIAS 17:5 +#define NVB097_TEXHEADV3_6_RESERVED6A 18:18 +#define NVB097_TEXHEADV3_6_ANISO_BIAS 22:19 +#define NVB097_TEXHEADV3_6_ANISO_FINE_SPREAD_FUNC 24:23 +#define NVB097_TEXHEADV3_6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEADV3_6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEADV3_6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEADV3_6_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEADV3_6_ANISO_COARSE_SPREAD_FUNC 26:25 +#define NVB097_TEXHEADV3_6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVB097_TEXHEADV3_6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVB097_TEXHEADV3_6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVB097_TEXHEADV3_6_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVB097_TEXHEADV3_6_MAX_ANISOTROPY 29:27 +#define NVB097_TEXHEADV3_6_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVB097_TEXHEADV3_6_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVB097_TEXHEADV3_6_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVB097_TEXHEADV3_6_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVB097_TEXHEADV3_6_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVB097_TEXHEADV3_6_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVB097_TEXHEADV3_6_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVB097_TEXHEADV3_6_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVB097_TEXHEADV3_6_ANISO_FINE_SPREAD_MODIFIER 31:30 +#define NVB097_TEXHEADV3_6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVB097_TEXHEADV3_6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVB097_TEXHEADV3_6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVB097_TEXHEADV3_6_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVB097_TEXHEADV3_7_RES_VIEW_MIN_MIP_LEVEL 3:0 +#define NVB097_TEXHEADV3_7_RES_VIEW_MAX_MIP_LEVEL 7:4 +#define NVB097_TEXHEADV3_7_HEIGHT_MSB 8:8 +#define NVB097_TEXHEADV3_7_HEIGHT_MSB_RESERVED 11:9 +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT 15:12 +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_2X1_CENTER 0x0000000c +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_2X2_CENTER 0x0000000d +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_4X2_CENTER 0x0000000e +#define NVB097_TEXHEADV3_7_MULTI_SAMPLE_COUNT_MODE_4X4_REGULAR 0x0000000f +#define NVB097_TEXHEADV3_7_MIN_LOD_CLAMP 27:16 +#define NVB097_TEXHEADV3_7_DEPTH_MSB 30:28 +#define NVB097_TEXHEADV3_7_RESERVED7A 31:31 + + +/* +** Texture Sampler State + */ + +#define NVB097_TEXSAMP0_ADDRESS_U 2:0 +#define NVB097_TEXSAMP0_ADDRESS_U_WRAP 0x00000000 +#define NVB097_TEXSAMP0_ADDRESS_U_MIRROR 0x00000001 +#define NVB097_TEXSAMP0_ADDRESS_U_CLAMP_TO_EDGE 0x00000002 +#define NVB097_TEXSAMP0_ADDRESS_U_BORDER 0x00000003 +#define NVB097_TEXSAMP0_ADDRESS_U_CLAMP_OGL 0x00000004 +#define NVB097_TEXSAMP0_ADDRESS_U_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005 +#define NVB097_TEXSAMP0_ADDRESS_U_MIRROR_ONCE_BORDER 0x00000006 +#define NVB097_TEXSAMP0_ADDRESS_U_MIRROR_ONCE_CLAMP_OGL 0x00000007 +#define NVB097_TEXSAMP0_ADDRESS_V 5:3 +#define NVB097_TEXSAMP0_ADDRESS_V_WRAP 0x00000000 +#define NVB097_TEXSAMP0_ADDRESS_V_MIRROR 0x00000001 +#define NVB097_TEXSAMP0_ADDRESS_V_CLAMP_TO_EDGE 0x00000002 +#define NVB097_TEXSAMP0_ADDRESS_V_BORDER 0x00000003 +#define NVB097_TEXSAMP0_ADDRESS_V_CLAMP_OGL 0x00000004 +#define NVB097_TEXSAMP0_ADDRESS_V_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005 +#define NVB097_TEXSAMP0_ADDRESS_V_MIRROR_ONCE_BORDER 0x00000006 +#define NVB097_TEXSAMP0_ADDRESS_V_MIRROR_ONCE_CLAMP_OGL 0x00000007 +#define NVB097_TEXSAMP0_ADDRESS_P 8:6 +#define NVB097_TEXSAMP0_ADDRESS_P_WRAP 0x00000000 +#define NVB097_TEXSAMP0_ADDRESS_P_MIRROR 0x00000001 +#define NVB097_TEXSAMP0_ADDRESS_P_CLAMP_TO_EDGE 0x00000002 +#define NVB097_TEXSAMP0_ADDRESS_P_BORDER 0x00000003 +#define NVB097_TEXSAMP0_ADDRESS_P_CLAMP_OGL 0x00000004 +#define NVB097_TEXSAMP0_ADDRESS_P_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005 +#define NVB097_TEXSAMP0_ADDRESS_P_MIRROR_ONCE_BORDER 0x00000006 +#define NVB097_TEXSAMP0_ADDRESS_P_MIRROR_ONCE_CLAMP_OGL 0x00000007 +#define NVB097_TEXSAMP0_DEPTH_COMPARE 9:9 +#define NVB097_TEXSAMP0_DEPTH_COMPARE_FUNC 12:10 +#define NVB097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_NEVER 0x00000000 +#define NVB097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_LESS 0x00000001 +#define NVB097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_EQUAL 0x00000002 +#define NVB097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_LEQUAL 0x00000003 +#define NVB097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_GREATER 0x00000004 +#define NVB097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_NOTEQUAL 0x00000005 +#define NVB097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_GEQUAL 0x00000006 +#define NVB097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_ALWAYS 0x00000007 +#define NVB097_TEXSAMP0_S_R_G_B_CONVERSION 13:13 +#define NVB097_TEXSAMP0_RESERVED0A 16:14 +#define NVB097_TEXSAMP0_RESERVED0B 19:17 +#define NVB097_TEXSAMP0_MAX_ANISOTROPY 22:20 +#define NVB097_TEXSAMP0_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVB097_TEXSAMP0_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVB097_TEXSAMP0_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVB097_TEXSAMP0_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVB097_TEXSAMP0_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVB097_TEXSAMP0_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVB097_TEXSAMP0_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVB097_TEXSAMP0_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVB097_TEXSAMP1_MAG_FILTER 2:0 +#define NVB097_TEXSAMP1_MAG_FILTER_MAG_POINT 0x00000001 +#define NVB097_TEXSAMP1_MAG_FILTER_MAG_LINEAR 0x00000002 +#define NVB097_TEXSAMP1_MAG_FILTER_VCAA_4_TAP 0x00000003 +#define NVB097_TEXSAMP1_MAG_FILTER_VCAA_8_TAP 0x00000004 +#define NVB097_TEXSAMP1_MIN_LOD_CLAMP_BEHAVIOR_FOR_NEAREST_MIP 3:3 +#define NVB097_TEXSAMP1_MIN_LOD_CLAMP_BEHAVIOR_FOR_NEAREST_MIP_INTEGER_AND_FRACTION 0x00000000 +#define NVB097_TEXSAMP1_MIN_LOD_CLAMP_BEHAVIOR_FOR_NEAREST_MIP_INTEGER_ONLY 0x00000001 +#define NVB097_TEXSAMP1_MIN_FILTER 5:4 +#define NVB097_TEXSAMP1_MIN_FILTER_MIN_POINT 0x00000001 +#define NVB097_TEXSAMP1_MIN_FILTER_MIN_LINEAR 0x00000002 +#define NVB097_TEXSAMP1_MIN_FILTER_MIN_ANISO 0x00000003 +#define NVB097_TEXSAMP1_MIP_FILTER 7:6 +#define NVB097_TEXSAMP1_MIP_FILTER_MIP_NONE 0x00000001 +#define NVB097_TEXSAMP1_MIP_FILTER_MIP_POINT 0x00000002 +#define NVB097_TEXSAMP1_MIP_FILTER_MIP_LINEAR 0x00000003 +#define NVB097_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING 9:8 +#define NVB097_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_USE_WRAP 0x00000000 +#define NVB097_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_OVERRIDE_WRAP 0x00000001 +#define NVB097_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_AUTO_SPAN_SEAM 0x00000002 +#define NVB097_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_AUTO_CROSS_SEAM 0x00000003 +#define NVB097_TEXSAMP1_MIP_LOD_BIAS 24:12 +#define NVB097_TEXSAMP1_FLOAT_COORD_NORMALIZATION 25:25 +#define NVB097_TEXSAMP1_FLOAT_COORD_NORMALIZATION_USE_HEADER_SETTING 0x00000000 +#define NVB097_TEXSAMP1_FLOAT_COORD_NORMALIZATION_FORCE_UNNORMALIZED_COORDS 0x00000001 +#define NVB097_TEXSAMP1_TRILIN_OPT 30:26 +#define NVB097_TEXSAMP2_MIN_LOD_CLAMP 11:0 +#define NVB097_TEXSAMP2_MAX_LOD_CLAMP 23:12 +#define NVB097_TEXSAMP2_S_R_G_B_BORDER_COLOR_R 31:24 +#define NVB097_TEXSAMP3_RESERVED12 11:0 +#define NVB097_TEXSAMP3_S_R_G_B_BORDER_COLOR_G 19:12 +#define NVB097_TEXSAMP3_S_R_G_B_BORDER_COLOR_B 27:20 +#define NVB097_TEXSAMP4_BORDER_COLOR_R 31:0 +#define NVB097_TEXSAMP5_BORDER_COLOR_G 31:0 +#define NVB097_TEXSAMP6_BORDER_COLOR_B 31:0 +#define NVB097_TEXSAMP7_BORDER_COLOR_A 31:0 + + + +#endif // #ifndef __CLB097TEX_H__ diff --git a/src/common/sdk/nvidia/inc/class/clb0b5sw.h b/src/common/sdk/nvidia/inc/class/clb0b5sw.h index f0e0d315a..ff1893168 100644 --- a/src/common/sdk/nvidia/inc/class/clb0b5sw.h +++ b/src/common/sdk/nvidia/inc/class/clb0b5sw.h @@ -21,38 +21,34 @@ * DEALINGS IN THE SOFTWARE. */ -#include "nvtypes.h" +#pragma once -#ifndef _clb0b5sw_h_ -#define _clb0b5sw_h_ +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clb0b5sw.finn +// -#ifdef __cplusplus -extern "C" { -#endif -/* This file is *not* auto-generated. */ // // Using VERSION_0 will cause the API to interpret // engineType as a CE engine instance. This allows // for backward compatibility with 85B5sw and 90B5sw. // -#define NVB0B5_ALLOCATION_PARAMETERS_VERSION_0 0 +#define NVB0B5_ALLOCATION_PARAMETERS_VERSION_0 0 // // Using VERSION_1 will cause the API to interpret // engineType as an NV2080_ENGINE_TYPE ordinal. // -#define NVB0B5_ALLOCATION_PARAMETERS_VERSION_1 1 +#define NVB0B5_ALLOCATION_PARAMETERS_VERSION_1 1 -typedef struct -{ - NvU32 version; - NvU32 engineType; +#define NVB0B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0xb0b5U) + +typedef struct NVB0B5_ALLOCATION_PARAMETERS { + NvU32 version; + NvU32 engineType; } NVB0B5_ALLOCATION_PARAMETERS; -#ifdef __cplusplus -}; /* extern "C" */ -#endif -#endif // _clb0b5sw_h_ - diff --git a/src/common/sdk/nvidia/inc/class/clb197.h b/src/common/sdk/nvidia/inc/class/clb197.h index 77d77352c..f8c976c93 100644 --- a/src/common/sdk/nvidia/inc/class/clb197.h +++ b/src/common/sdk/nvidia/inc/class/clb197.h @@ -1,29 +1,4160 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. -#ifndef _clb197_h_ -#define _clb197_h_ + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_maxwell_b_h_ +#define _cl_maxwell_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl maxwell_b */ + +#include "nvtypes.h" #define MAXWELL_B 0xB197 -#endif // _clb197_h_ +#define NVB197_SET_OBJECT 0x0000 +#define NVB197_SET_OBJECT_CLASS_ID 15:0 +#define NVB197_SET_OBJECT_ENGINE_ID 20:16 + +#define NVB197_NO_OPERATION 0x0100 +#define NVB197_NO_OPERATION_V 31:0 + +#define NVB197_SET_NOTIFY_A 0x0104 +#define NVB197_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVB197_SET_NOTIFY_B 0x0108 +#define NVB197_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVB197_NOTIFY 0x010c +#define NVB197_NOTIFY_TYPE 31:0 +#define NVB197_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVB197_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVB197_WAIT_FOR_IDLE 0x0110 +#define NVB197_WAIT_FOR_IDLE_V 31:0 + +#define NVB197_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVB197_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVB197_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVB197_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVB197_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVB197_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVB197_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVB197_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVB197_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVB197_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVB197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVB197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVB197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVB197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVB197_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVB197_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVB197_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVB197_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVB197_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVB197_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVB197_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVB197_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVB197_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB197_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB197_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB197_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB197_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB197_SEND_GO_IDLE 0x013c +#define NVB197_SEND_GO_IDLE_V 31:0 + +#define NVB197_PM_TRIGGER 0x0140 +#define NVB197_PM_TRIGGER_V 31:0 + +#define NVB197_PM_TRIGGER_WFI 0x0144 +#define NVB197_PM_TRIGGER_WFI_V 31:0 + +#define NVB197_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVB197_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVB197_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVB197_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVB197_LINE_LENGTH_IN 0x0180 +#define NVB197_LINE_LENGTH_IN_VALUE 31:0 + +#define NVB197_LINE_COUNT 0x0184 +#define NVB197_LINE_COUNT_VALUE 31:0 + +#define NVB197_OFFSET_OUT_UPPER 0x0188 +#define NVB197_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVB197_OFFSET_OUT 0x018c +#define NVB197_OFFSET_OUT_VALUE 31:0 + +#define NVB197_PITCH_OUT 0x0190 +#define NVB197_PITCH_OUT_VALUE 31:0 + +#define NVB197_SET_DST_BLOCK_SIZE 0x0194 +#define NVB197_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVB197_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB197_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVB197_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB197_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB197_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB197_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB197_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB197_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB197_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVB197_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVB197_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVB197_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVB197_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB197_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB197_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVB197_SET_DST_WIDTH 0x0198 +#define NVB197_SET_DST_WIDTH_V 31:0 + +#define NVB197_SET_DST_HEIGHT 0x019c +#define NVB197_SET_DST_HEIGHT_V 31:0 + +#define NVB197_SET_DST_DEPTH 0x01a0 +#define NVB197_SET_DST_DEPTH_V 31:0 + +#define NVB197_SET_DST_LAYER 0x01a4 +#define NVB197_SET_DST_LAYER_V 31:0 + +#define NVB197_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVB197_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVB197_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVB197_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVB197_LAUNCH_DMA 0x01b0 +#define NVB197_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVB197_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB197_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB197_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVB197_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVB197_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVB197_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVB197_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVB197_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVB197_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVB197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVB197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVB197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVB197_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVB197_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB197_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB197_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVB197_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB197_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB197_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB197_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVB197_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB197_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVB197_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVB197_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB197_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVB197_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB197_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB197_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVB197_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVB197_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVB197_LOAD_INLINE_DATA 0x01b4 +#define NVB197_LOAD_INLINE_DATA_V 31:0 + +#define NVB197_SET_I2M_SEMAPHORE_A 0x01dc +#define NVB197_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVB197_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVB197_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB197_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVB197_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVB197_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVB197_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVB197_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVB197_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVB197_SET_I2M_SPARE_NOOP03 0x01fc +#define NVB197_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVB197_RUN_DS_NOW 0x0200 +#define NVB197_RUN_DS_NOW_V 31:0 + +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVB197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVB197_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVB197_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVB197_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVB197_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVB197_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVB197_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVB197_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVB197_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_GS_DM_FIFO 0x0214 +#define NVB197_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVB197_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVB197_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVB197_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVB197_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB197_INVALIDATE_SHADER_CACHES 0x021c +#define NVB197_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVB197_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVB197_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVB197_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVB197_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVB197_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVB197_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVB197_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVB197_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVB197_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVB197_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVB197_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVB197_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVB197_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVB197_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVB197_INCREMENT_SYNC_POINT 0x02c8 +#define NVB197_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVB197_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVB197_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVB197_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVB197_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVB197_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVB197_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVB197_SET_PRIM_CIRCULAR_BUFFER_THROTTLE 0x02d0 +#define NVB197_SET_PRIM_CIRCULAR_BUFFER_THROTTLE_PRIM_AREA 21:0 + +#define NVB197_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVB197_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVB197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVB197_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVB197_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVB197_DECOMPRESS_SURFACE 0x02e0 +#define NVB197_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVB197_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVB197_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVB197_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVB197_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVB197_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVB197_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVB197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVB197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVB197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVB197_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVB197_SET_ZCULL_SUBREGION 0x02e8 +#define NVB197_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVB197_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVB197_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVB197_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVB197_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVB197_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVB197_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVB197_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVB197_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVB197_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVB197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVB197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVB197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVB197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVB197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVB197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVB197_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVB197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVB197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVB197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVB197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVB197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVB197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVB197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVB197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVB197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVB197_DRAW_ZERO_INDEX 0x0304 +#define NVB197_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVB197_SET_L1_CONFIGURATION 0x0308 +#define NVB197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVB197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVB197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVB197_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVB197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVB197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVB197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVB197_SET_SPA_VERSION 0x0310 +#define NVB197_SET_SPA_VERSION_MINOR 7:0 +#define NVB197_SET_SPA_VERSION_MAJOR 15:8 + +#define NVB197_SET_IEEE_CLEAN_UPDATE 0x0314 +#define NVB197_SET_IEEE_CLEAN_UPDATE_ENABLE 0:0 +#define NVB197_SET_IEEE_CLEAN_UPDATE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_IEEE_CLEAN_UPDATE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_SNAP_GRID_LINE 0x0318 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVB197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVB197_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVB197_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVB197_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVB197_SET_SNAP_GRID_NON_LINE 0x031c +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVB197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVB197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVB197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVB197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVB197_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVB197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVB197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVB197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVB197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVB197_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVB197_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVB197_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVB197_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVB197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVB197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVB197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVB197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVB197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVB197_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVB197_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVB197_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVB197_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVB197_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVB197_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVB197_SET_TESSELLATION_LOD_V1 0x0330 +#define NVB197_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVB197_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVB197_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVB197_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVB197_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVB197_RESERVED_TG07 0x033c +#define NVB197_RESERVED_TG07_V 0:0 + +#define NVB197_RESERVED_TG08 0x0340 +#define NVB197_RESERVED_TG08_V 0:0 + +#define NVB197_RESERVED_TG09 0x0344 +#define NVB197_RESERVED_TG09_V 0:0 + +#define NVB197_RESERVED_TG10 0x0348 +#define NVB197_RESERVED_TG10_V 0:0 + +#define NVB197_RESERVED_TG11 0x034c +#define NVB197_RESERVED_TG11_V 0:0 + +#define NVB197_RESERVED_TG12 0x0350 +#define NVB197_RESERVED_TG12_V 0:0 + +#define NVB197_RESERVED_TG13 0x0354 +#define NVB197_RESERVED_TG13_V 0:0 + +#define NVB197_RESERVED_TG14 0x0358 +#define NVB197_RESERVED_TG14_V 0:0 + +#define NVB197_RESERVED_TG15 0x035c +#define NVB197_RESERVED_TG15_V 0:0 + +#define NVB197_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVB197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVB197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVB197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVB197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVB197_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVB197_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVB197_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVB197_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVB197_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVB197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVB197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVB197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVB197_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVB197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVB197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVB197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVB197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVB197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVB197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVB197_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVB197_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVB197_SET_RASTER_ENABLE 0x037c +#define NVB197_SET_RASTER_ENABLE_V 0:0 +#define NVB197_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVB197_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVB197_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVB197_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVB197_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVB197_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVB197_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVB197_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVB197_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVB197_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVB197_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVB197_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVB197_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVB197_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVB197_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVB197_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVB197_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVB197_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVB197_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVB197_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVB197_SET_RASTER_INPUT 0x0740 +#define NVB197_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVB197_SET_STREAM_OUTPUT 0x0744 +#define NVB197_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVB197_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVB197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVB197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_ALPHA_FRACTION 0x074c +#define NVB197_SET_ALPHA_FRACTION_V 7:0 + +#define NVB197_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVB197_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVB197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVB197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVB197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVB197_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVB197_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVB197_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVB197_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVB197_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVB197_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVB197_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVB197_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVB197_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVB197_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVB197_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVB197_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVB197_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVB197_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVB197_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVB197_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVB197_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVB197_SET_ISBE_SAVE_RESTORE_PROGRAM 0x07ac +#define NVB197_SET_ISBE_SAVE_RESTORE_PROGRAM_OFFSET 31:0 + +#define NVB197_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVB197_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVB197_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVB197_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVB197_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVB197_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVB197_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVB197_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVB197_SET_CULL_BEFORE_FETCH 0x07dc +#define NVB197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVB197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVB197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVB197_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVB197_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVB197_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVB197_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVB197_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVB197_SET_ZCULL_STORAGE_A 0x07e8 +#define NVB197_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVB197_SET_ZCULL_STORAGE_B 0x07ec +#define NVB197_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVB197_SET_ZCULL_STORAGE_C 0x07f0 +#define NVB197_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVB197_SET_ZCULL_STORAGE_D 0x07f4 +#define NVB197_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVB197_SET_ZT_READ_ONLY 0x07f8 +#define NVB197_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVB197_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVB197_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVB197_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVB197_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVB197_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVB197_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVB197_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVB197_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVB197_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVB197_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVB197_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVB197_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVB197_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVB197_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVB197_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVB197_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVB197_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVB197_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVB197_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVB197_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVB197_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVB197_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVB197_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVB197_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVB197_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVB197_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVB197_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB197_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVB197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVB197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVB197_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVB197_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVB197_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVB197_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVB197_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVB197_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVB197_SET_COLOR_TARGET_MARK(j) (0x0824+(j)*64) +#define NVB197_SET_COLOR_TARGET_MARK_IEEE_CLEAN 0:0 +#define NVB197_SET_COLOR_TARGET_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVB197_SET_COLOR_TARGET_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVB197_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVB197_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVB197_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVB197_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVB197_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVB197_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVB197_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVB197_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVB197_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVB197_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVB197_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVB197_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVB197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVB197_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVB197_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVB197_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVB197_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVB197_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVB197_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVB197_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVB197_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVB197_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVB197_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVB197_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVB197_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVB197_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVB197_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVB197_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVB197_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVB197_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVB197_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVB197_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVB197_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVB197_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVB197_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVB197_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVB197_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVB197_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVB197_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVB197_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVB197_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVB197_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVB197_SET_STATISTICS_COUNTER 0x0d68 +#define NVB197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVB197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVB197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVB197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVB197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVB197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVB197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVB197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVB197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVB197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVB197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVB197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVB197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVB197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVB197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVB197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVB197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVB197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVB197_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVB197_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVB197_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVB197_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVB197_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVB197_SET_VERTEX_ARRAY_START 0x0d74 +#define NVB197_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVB197_DRAW_VERTEX_ARRAY 0x0d78 +#define NVB197_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVB197_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVB197_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVB197_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVB197_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVB197_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVB197_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVB197_SET_Z_CLEAR_VALUE 0x0d90 +#define NVB197_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVB197_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVB197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVB197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVB197_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVB197_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVB197_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVB197_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVB197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVB197_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVB197_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVB197_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVB197_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVB197_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVB197_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVB197_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVB197_SET_FRONT_POLYGON_MODE 0x0dac +#define NVB197_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVB197_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVB197_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVB197_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVB197_SET_BACK_POLYGON_MODE 0x0db0 +#define NVB197_SET_BACK_POLYGON_MODE_V 31:0 +#define NVB197_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVB197_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVB197_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVB197_SET_POLY_SMOOTH 0x0db4 +#define NVB197_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVB197_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVB197_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_ZT_MARK 0x0db8 +#define NVB197_SET_ZT_MARK_IEEE_CLEAN 0:0 +#define NVB197_SET_ZT_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVB197_SET_ZT_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVB197_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVB197_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVB197_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVB197_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVB197_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVB197_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVB197_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVB197_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVB197_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVB197_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVB197_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVB197_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVB197_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVB197_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVB197_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVB197_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVB197_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_PATCH 0x0dcc +#define NVB197_SET_PATCH_SIZE 7:0 + +#define NVB197_SET_ITERATED_BLEND 0x0dd0 +#define NVB197_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVB197_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVB197_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVB197_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVB197_SET_ZCULL_CRITERION 0x0dd8 +#define NVB197_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVB197_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVB197_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVB197_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVB197_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVB197_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVB197_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVB197_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVB197_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVB197_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVB197_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVB197_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVB197_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVB197_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVB197_SET_ZCULL_CRITERION_SREF 23:16 +#define NVB197_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVB197_PIXEL_SHADER_BARRIER 0x0de0 +#define NVB197_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVB197_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVB197_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVB197_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVB197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVB197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVB197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVB197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVB197_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVB197_SET_WINDOW_OFFSET_X 0x0df8 +#define NVB197_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVB197_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVB197_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVB197_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVB197_SET_SCISSOR_ENABLE_V 0:0 +#define NVB197_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVB197_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVB197_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVB197_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVB197_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVB197_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVB197_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVB197_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVB197_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0f10 +#define NVB197_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVB197_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVB197_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVB197_SET_VPC_PERF_KNOB 0x0f14 +#define NVB197_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVB197_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVB197_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVB197_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVB197_PM_LOCAL_TRIGGER 0x0f18 +#define NVB197_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVB197_SET_POST_Z_PS_IMASK 0x0f1c +#define NVB197_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVB197_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVB197_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVB197_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVB197_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVB197_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVB197_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVB197_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVB197_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVB197_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVB197_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVB197_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVB197_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVB197_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVB197_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVB197_SET_BACK_STENCIL_MASK 0x0f58 +#define NVB197_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVB197_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVB197_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVB197_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVB197_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVB197_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVB197_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVB197_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVB197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVB197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVB197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVB197_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVB197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVB197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVB197_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVB197_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVB197_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVB197_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVB197_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVB197_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVB197_SET_SAMPLE_MASK 0x0fa4 +#define NVB197_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVB197_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVB197_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVB197_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVB197_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVB197_SET_CT_MRT_ENABLE 0x0fac +#define NVB197_SET_CT_MRT_ENABLE_V 0:0 +#define NVB197_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVB197_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVB197_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVB197_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVB197_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVB197_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVB197_SET_TIR 0x0fb4 +#define NVB197_SET_TIR_MODE 1:0 +#define NVB197_SET_TIR_MODE_DISABLED 0x00000000 +#define NVB197_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVB197_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVB197_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVB197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVB197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVB197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVB197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVB197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVB197_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVB197_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVB197_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVB197_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVB197_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVB197_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVB197_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVB197_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVB197_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVB197_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVB197_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_TIR_MODULATION 0x0fd4 +#define NVB197_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVB197_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVB197_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVB197_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVB197_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVB197_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVB197_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVB197_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVB197_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVB197_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVB197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVB197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVB197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVB197_SET_ZT_A 0x0fe0 +#define NVB197_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_ZT_B 0x0fe4 +#define NVB197_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_ZT_FORMAT 0x0fe8 +#define NVB197_SET_ZT_FORMAT_V 4:0 +#define NVB197_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVB197_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVB197_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVB197_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVB197_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVB197_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVB197_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVB197_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVB197_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVB197_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVB197_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVB197_SET_ZT_BLOCK_SIZE 0x0fec +#define NVB197_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVB197_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB197_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVB197_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB197_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB197_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB197_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB197_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB197_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB197_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVB197_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVB197_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVB197_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVB197_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVB197_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVB197_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVB197_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVB197_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVB197_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVB197_SET_TILED_CACHE_BUNDLE_CONTROL 0x0ffc +#define NVB197_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT 0:0 +#define NVB197_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT_FALSE 0x00000000 +#define NVB197_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT_TRUE 0x00000001 + +#define NVB197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB197_SET_VIEWPORT_MULTICAST 0x1004 +#define NVB197_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVB197_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVB197_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVB197_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVB197_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVB197_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVB197_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVB197_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVB197_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVB197_SET_RESERVED_SW_METHOD00 0x1014 +#define NVB197_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVB197_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVB197_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVB197_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVB197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVB197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVB197_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVB197_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVB197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVB197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_RESERVED_SW_METHOD01 0x1028 +#define NVB197_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD02 0x102c +#define NVB197_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVB197_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVB197_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVB197_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVB197_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVB197_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVB197_SET_SPARE_NOOP01 0x1044 +#define NVB197_SET_SPARE_NOOP01_V 31:0 + +#define NVB197_SET_SPARE_NOOP02 0x1048 +#define NVB197_SET_SPARE_NOOP02_V 31:0 + +#define NVB197_SET_SPARE_NOOP03 0x104c +#define NVB197_SET_SPARE_NOOP03_V 31:0 + +#define NVB197_SET_SPARE_NOOP04 0x1050 +#define NVB197_SET_SPARE_NOOP04_V 31:0 + +#define NVB197_SET_SPARE_NOOP05 0x1054 +#define NVB197_SET_SPARE_NOOP05_V 31:0 + +#define NVB197_SET_SPARE_NOOP06 0x1058 +#define NVB197_SET_SPARE_NOOP06_V 31:0 + +#define NVB197_SET_SPARE_NOOP07 0x105c +#define NVB197_SET_SPARE_NOOP07_V 31:0 + +#define NVB197_SET_SPARE_NOOP08 0x1060 +#define NVB197_SET_SPARE_NOOP08_V 31:0 + +#define NVB197_SET_SPARE_NOOP09 0x1064 +#define NVB197_SET_SPARE_NOOP09_V 31:0 + +#define NVB197_SET_SPARE_NOOP10 0x1068 +#define NVB197_SET_SPARE_NOOP10_V 31:0 + +#define NVB197_SET_SPARE_NOOP11 0x106c +#define NVB197_SET_SPARE_NOOP11_V 31:0 + +#define NVB197_SET_SPARE_NOOP12 0x1070 +#define NVB197_SET_SPARE_NOOP12_V 31:0 + +#define NVB197_SET_SPARE_NOOP13 0x1074 +#define NVB197_SET_SPARE_NOOP13_V 31:0 + +#define NVB197_SET_SPARE_NOOP14 0x1078 +#define NVB197_SET_SPARE_NOOP14_V 31:0 + +#define NVB197_SET_SPARE_NOOP15 0x107c +#define NVB197_SET_SPARE_NOOP15_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVB197_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVB197_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVB197_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD06 0x10bc +#define NVB197_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVB197_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVB197_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVB197_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVB197_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVB197_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVB197_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVB197_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD13 0x10dc +#define NVB197_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVB197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVB197_UNBIND_ALL 0x10f4 +#define NVB197_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVB197_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVB197_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVB197_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVB197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB197_SET_RESERVED_SW_METHOD14 0x1100 +#define NVB197_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVB197_SET_RESERVED_SW_METHOD15 0x1104 +#define NVB197_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVB197_NO_OPERATION_DATA_HI 0x110c +#define NVB197_NO_OPERATION_DATA_HI_V 31:0 + +#define NVB197_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVB197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVB197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVB197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVB197_PM_TRIGGER_END 0x1114 +#define NVB197_PM_TRIGGER_END_V 31:0 + +#define NVB197_SET_VERTEX_ID_BASE 0x1118 +#define NVB197_SET_VERTEX_ID_BASE_V 31:0 + +#define NVB197_SET_STENCIL_COMPRESSION 0x111c +#define NVB197_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVB197_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVB197_SET_TIR_CONTROL 0x1130 +#define NVB197_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVB197_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVB197_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVB197_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVB197_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVB197_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVB197_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVB197_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVB197_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 + +#define NVB197_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVB197_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVB197_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVB197_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVB197_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVB197_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVB197_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVB197_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVB197_SET_FILL_VIA_TRIANGLE 0x113c +#define NVB197_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVB197_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVB197_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVB197_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVB197_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVB197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVB197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVB197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVB197_FLUSH_PENDING_WRITES 0x1144 +#define NVB197_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVB197_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVB197_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVB197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVB197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVB197_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVB197_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVB197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVB197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVB197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVB197_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVB197_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVB197_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVB197_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVB197_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVB197_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVB197_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVB197_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVB197_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVB197_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVB197_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVB197_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVB197_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVB197_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVB197_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVB197_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVB197_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVB197_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_ZT_SPARSE 0x1208 +#define NVB197_SET_ZT_SPARSE_ENABLE 0:0 +#define NVB197_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVB197_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVB197_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVB197_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVB197_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVB197_SET_CT_SELECT 0x121c +#define NVB197_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVB197_SET_CT_SELECT_TARGET0 6:4 +#define NVB197_SET_CT_SELECT_TARGET1 9:7 +#define NVB197_SET_CT_SELECT_TARGET2 12:10 +#define NVB197_SET_CT_SELECT_TARGET3 15:13 +#define NVB197_SET_CT_SELECT_TARGET4 18:16 +#define NVB197_SET_CT_SELECT_TARGET5 21:19 +#define NVB197_SET_CT_SELECT_TARGET6 24:22 +#define NVB197_SET_CT_SELECT_TARGET7 27:25 + +#define NVB197_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVB197_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVB197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVB197_SET_ZT_SIZE_A 0x1228 +#define NVB197_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVB197_SET_ZT_SIZE_B 0x122c +#define NVB197_SET_ZT_SIZE_B_HEIGHT 16:0 + +#define NVB197_SET_ZT_SIZE_C 0x1230 +#define NVB197_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVB197_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVB197_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVB197_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVB197_SET_SAMPLER_BINDING 0x1234 +#define NVB197_SET_SAMPLER_BINDING_V 0:0 +#define NVB197_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVB197_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVB197_DRAW_AUTO 0x123c +#define NVB197_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVB197_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVB197_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVB197_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVB197_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVB197_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVB197_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVB197_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVB197_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVB197_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVB197_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB197_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVB197_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVB197_CLEAR_ZCULL_REGION 0x12c8 +#define NVB197_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVB197_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVB197_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVB197_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVB197_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVB197_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVB197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVB197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVB197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVB197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVB197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVB197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVB197_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVB197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVB197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVB197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVB197_SET_DEPTH_TEST 0x12cc +#define NVB197_SET_DEPTH_TEST_ENABLE 0:0 +#define NVB197_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVB197_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_FILL_MODE 0x12d0 +#define NVB197_SET_FILL_MODE_V 31:0 +#define NVB197_SET_FILL_MODE_V_POINT 0x00000001 +#define NVB197_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVB197_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVB197_SET_SHADE_MODE 0x12d4 +#define NVB197_SET_SHADE_MODE_V 31:0 +#define NVB197_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVB197_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVB197_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVB197_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVB197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVB197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVB197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVB197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVB197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVB197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVB197_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVB197_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVB197_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVB197_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_DEPTH_WRITE 0x12e8 +#define NVB197_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVB197_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_ALPHA_TEST 0x12ec +#define NVB197_SET_ALPHA_TEST_ENABLE 0:0 +#define NVB197_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVB197_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVB197_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVB197_DRAW_INLINE_INDEX4X8 0x1304 +#define NVB197_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVB197_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVB197_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVB197_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVB197_D3D_SET_CULL_MODE 0x1308 +#define NVB197_D3D_SET_CULL_MODE_V 31:0 +#define NVB197_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVB197_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVB197_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVB197_SET_DEPTH_FUNC 0x130c +#define NVB197_SET_DEPTH_FUNC_V 31:0 +#define NVB197_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVB197_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVB197_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVB197_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVB197_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVB197_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVB197_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVB197_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVB197_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVB197_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVB197_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVB197_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVB197_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVB197_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVB197_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVB197_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVB197_SET_ALPHA_REF 0x1310 +#define NVB197_SET_ALPHA_REF_V 31:0 + +#define NVB197_SET_ALPHA_FUNC 0x1314 +#define NVB197_SET_ALPHA_FUNC_V 31:0 +#define NVB197_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVB197_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVB197_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVB197_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVB197_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVB197_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVB197_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVB197_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVB197_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVB197_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVB197_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVB197_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVB197_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVB197_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVB197_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVB197_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVB197_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVB197_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVB197_SET_BLEND_CONST_RED 0x131c +#define NVB197_SET_BLEND_CONST_RED_V 31:0 + +#define NVB197_SET_BLEND_CONST_GREEN 0x1320 +#define NVB197_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVB197_SET_BLEND_CONST_BLUE 0x1324 +#define NVB197_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVB197_SET_BLEND_CONST_ALPHA 0x1328 +#define NVB197_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVB197_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVB197_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVB197_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVB197_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVB197_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVB197_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVB197_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVB197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVB197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVB197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_BLEND_COLOR_OP 0x1340 +#define NVB197_SET_BLEND_COLOR_OP_V 31:0 +#define NVB197_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVB197_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVB197_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVB197_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVB197_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVB197_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVB197_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVB197_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVB197_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVB197_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB197_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB197_SET_BLEND_ALPHA_OP 0x134c +#define NVB197_SET_BLEND_ALPHA_OP_V 31:0 +#define NVB197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVB197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVB197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVB197_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVB197_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVB197_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVB197_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVB197_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVB197_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVB197_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB197_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVB197_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVB197_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVB197_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB197_SET_SINGLE_ROP_CONTROL 0x135c +#define NVB197_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVB197_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_BLEND(i) (0x1360+(i)*4) +#define NVB197_SET_BLEND_ENABLE 0:0 +#define NVB197_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVB197_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_STENCIL_TEST 0x1380 +#define NVB197_SET_STENCIL_TEST_ENABLE 0:0 +#define NVB197_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVB197_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_STENCIL_OP_FAIL 0x1384 +#define NVB197_SET_STENCIL_OP_FAIL_V 31:0 +#define NVB197_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVB197_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVB197_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVB197_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVB197_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVB197_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVB197_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVB197_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVB197_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVB197_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVB197_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVB197_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVB197_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVB197_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVB197_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVB197_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVB197_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVB197_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVB197_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVB197_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVB197_SET_STENCIL_OP_ZPASS 0x138c +#define NVB197_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVB197_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVB197_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVB197_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVB197_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVB197_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVB197_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVB197_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVB197_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVB197_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVB197_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVB197_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVB197_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVB197_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVB197_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVB197_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVB197_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVB197_SET_STENCIL_FUNC 0x1390 +#define NVB197_SET_STENCIL_FUNC_V 31:0 +#define NVB197_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVB197_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVB197_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVB197_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVB197_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVB197_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVB197_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVB197_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVB197_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVB197_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVB197_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVB197_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVB197_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVB197_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVB197_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVB197_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVB197_SET_STENCIL_FUNC_REF 0x1394 +#define NVB197_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVB197_SET_STENCIL_FUNC_MASK 0x1398 +#define NVB197_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVB197_SET_STENCIL_MASK 0x139c +#define NVB197_SET_STENCIL_MASK_V 7:0 + +#define NVB197_SET_DRAW_AUTO_START 0x13a4 +#define NVB197_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVB197_SET_PS_SATURATE 0x13a8 +#define NVB197_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVB197_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVB197_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB197_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVB197_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVB197_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB197_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVB197_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVB197_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB197_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVB197_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVB197_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB197_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVB197_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVB197_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB197_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVB197_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVB197_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB197_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVB197_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVB197_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVB197_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVB197_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVB197_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVB197_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVB197_SET_WINDOW_ORIGIN 0x13ac +#define NVB197_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVB197_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVB197_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVB197_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVB197_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVB197_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVB197_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVB197_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVB197_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVB197_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVB197_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVB197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVB197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_ALPHA_HYSTERESIS 0x1420 +#define NVB197_SET_ALPHA_HYSTERESIS_ROUNDS_OF_ALPHA 7:0 + +#define NVB197_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVB197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVB197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB197_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVB197_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVB197_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVB197_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVB197_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVB197_SET_PS_WARP_WATERMARKS 0x1450 +#define NVB197_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVB197_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVB197_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVB197_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVB197_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVB197_STORE_ZCULL 0x1464 +#define NVB197_STORE_ZCULL_V 0:0 + +#define NVB197_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVB197_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVB197_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVB197_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVB197_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVB197_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVB197_LOAD_ZCULL 0x1500 +#define NVB197_LOAD_ZCULL_V 0:0 + +#define NVB197_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVB197_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVB197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVB197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVB197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVB197_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVB197_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVB197_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVB197_SET_USER_CLIP_ENABLE 0x1510 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVB197_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVB197_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVB197_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVB197_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_POINT_SIZE 0x1518 +#define NVB197_SET_POINT_SIZE_V 31:0 + +#define NVB197_SET_ZCULL_STATS 0x151c +#define NVB197_SET_ZCULL_STATS_ENABLE 0:0 +#define NVB197_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_POINT_SPRITE 0x1520 +#define NVB197_SET_POINT_SPRITE_ENABLE 0:0 +#define NVB197_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_SHADER_EXCEPTIONS 0x1528 +#define NVB197_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVB197_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVB197_CLEAR_REPORT_VALUE 0x1530 +#define NVB197_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVB197_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVB197_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVB197_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVB197_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVB197_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVB197_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVB197_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 + +#define NVB197_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVB197_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVB197_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVB197_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVB197_SET_ZT_SELECT 0x1538 +#define NVB197_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVB197_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVB197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVB197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVB197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVB197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVB197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVB197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVB197_SET_RENDER_ENABLE_A 0x1550 +#define NVB197_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_RENDER_ENABLE_B 0x1554 +#define NVB197_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_RENDER_ENABLE_C 0x1558 +#define NVB197_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVB197_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB197_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB197_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB197_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB197_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB197_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVB197_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVB197_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVB197_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVB197_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVB197_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVB197_SET_ANTI_ALIASED_LINE 0x1570 +#define NVB197_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVB197_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_TEX_HEADER_POOL_A 0x1574 +#define NVB197_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_TEX_HEADER_POOL_B 0x1578 +#define NVB197_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_TEX_HEADER_POOL_C 0x157c +#define NVB197_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVB197_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVB197_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVB197_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVB197_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVB197_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVB197_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVB197_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVB197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVB197_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVB197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVB197_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVB197_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVB197_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVB197_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVB197_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVB197_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVB197_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVB197_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVB197_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVB197_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVB197_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVB197_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVB197_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVB197_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVB197_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVB197_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVB197_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVB197_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVB197_SET_SRGB_WRITE 0x15b8 +#define NVB197_SET_SRGB_WRITE_ENABLE 0:0 +#define NVB197_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_DEPTH_BIAS 0x15bc +#define NVB197_SET_DEPTH_BIAS_V 31:0 + +#define NVB197_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVB197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVB197_SET_RT_LAYER 0x15cc +#define NVB197_SET_RT_LAYER_V 15:0 +#define NVB197_SET_RT_LAYER_CONTROL 16:16 +#define NVB197_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVB197_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVB197_SET_ANTI_ALIAS 0x15d0 +#define NVB197_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVB197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVB197_SET_EDGE_FLAG 0x15e4 +#define NVB197_SET_EDGE_FLAG_V 0:0 +#define NVB197_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVB197_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVB197_DRAW_INLINE_INDEX 0x15e8 +#define NVB197_DRAW_INLINE_INDEX_V 31:0 + +#define NVB197_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVB197_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVB197_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVB197_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVB197_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVB197_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVB197_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVB197_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVB197_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVB197_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVB197_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVB197_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVB197_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVB197_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVB197_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVB197_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVB197_SET_POINT_SPRITE_SELECT 0x1604 +#define NVB197_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVB197_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVB197_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVB197_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVB197_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVB197_SET_PROGRAM_REGION_A 0x1608 +#define NVB197_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVB197_SET_PROGRAM_REGION_B 0x160c +#define NVB197_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVB197_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVB197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVB197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVB197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVB197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVB197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVB197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVB197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVB197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVB197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVB197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVB197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVB197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVB197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVB197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVB197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVB197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVB197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVB197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVB197_END 0x1614 +#define NVB197_END_V 0:0 + +#define NVB197_BEGIN 0x1618 +#define NVB197_BEGIN_OP 15:0 +#define NVB197_BEGIN_OP_POINTS 0x00000000 +#define NVB197_BEGIN_OP_LINES 0x00000001 +#define NVB197_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVB197_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVB197_BEGIN_OP_TRIANGLES 0x00000004 +#define NVB197_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVB197_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVB197_BEGIN_OP_QUADS 0x00000007 +#define NVB197_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVB197_BEGIN_OP_POLYGON 0x00000009 +#define NVB197_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVB197_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVB197_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_BEGIN_OP_PATCH 0x0000000E +#define NVB197_BEGIN_PRIMITIVE_ID 24:24 +#define NVB197_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVB197_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVB197_BEGIN_INSTANCE_ID 27:26 +#define NVB197_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVB197_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVB197_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVB197_BEGIN_SPLIT_MODE 30:29 +#define NVB197_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVB197_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVB197_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVB197_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 + +#define NVB197_SET_VERTEX_ID_COPY 0x161c +#define NVB197_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVB197_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVB197_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVB197_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVB197_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVB197_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVB197_LOAD_PRIMITIVE_ID 0x1624 +#define NVB197_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVB197_SET_SHADER_BASED_CULL 0x162c +#define NVB197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVB197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVB197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVB197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVB197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_CLASS_VERSION 0x1638 +#define NVB197_SET_CLASS_VERSION_CURRENT 15:0 +#define NVB197_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB197_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVB197_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVB197_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVB197_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVB197_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVB197_SET_DA_OUTPUT 0x164c +#define NVB197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVB197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVB197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVB197_SET_ANTI_ALIASED_POINT 0x1658 +#define NVB197_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVB197_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_POINT_CENTER_MODE 0x165c +#define NVB197_SET_POINT_CENTER_MODE_V 31:0 +#define NVB197_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVB197_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVB197_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVB197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVB197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVB197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVB197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVB197_SET_LINE_STIPPLE 0x166c +#define NVB197_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVB197_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVB197_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVB197_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVB197_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVB197_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVB197_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVB197_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVB197_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVB197_SET_PROVOKING_VERTEX 0x1684 +#define NVB197_SET_PROVOKING_VERTEX_V 0:0 +#define NVB197_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVB197_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVB197_SET_TWO_SIDED_LIGHT 0x1688 +#define NVB197_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVB197_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_POLYGON_STIPPLE 0x168c +#define NVB197_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVB197_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_SHADER_CONTROL 0x1690 +#define NVB197_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVB197_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVB197_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVB197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVB197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVB197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVB197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVB197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVB197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVB197_CHECK_CLASS_VERSION 0x16a0 +#define NVB197_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVB197_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB197_SET_SPH_VERSION 0x16a4 +#define NVB197_SET_SPH_VERSION_CURRENT 15:0 +#define NVB197_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB197_CHECK_SPH_VERSION 0x16a8 +#define NVB197_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVB197_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB197_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVB197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVB197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVB197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVB197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVB197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVB197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVB197_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVB197_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVB197_SET_AAM_VERSION 0x1790 +#define NVB197_SET_AAM_VERSION_CURRENT 15:0 +#define NVB197_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB197_CHECK_AAM_VERSION 0x1794 +#define NVB197_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVB197_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB197_SET_ZT_LAYER 0x179c +#define NVB197_SET_ZT_LAYER_OFFSET 15:0 + +#define NVB197_SET_INDEX_BUFFER_A 0x17c8 +#define NVB197_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVB197_SET_INDEX_BUFFER_B 0x17cc +#define NVB197_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVB197_SET_INDEX_BUFFER_C 0x17d0 +#define NVB197_SET_INDEX_BUFFER_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVB197_SET_INDEX_BUFFER_D 0x17d4 +#define NVB197_SET_INDEX_BUFFER_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVB197_SET_INDEX_BUFFER_E 0x17d8 +#define NVB197_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVB197_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVB197_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVB197_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVB197_SET_INDEX_BUFFER_F 0x17dc +#define NVB197_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVB197_DRAW_INDEX_BUFFER 0x17e0 +#define NVB197_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVB197_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVB197_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVB197_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVB197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVB197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVB197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVB197_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVB197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVB197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVB197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVB197_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVB197_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVB197_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVB197_OGL_SET_CULL 0x1918 +#define NVB197_OGL_SET_CULL_ENABLE 0:0 +#define NVB197_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVB197_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVB197_OGL_SET_FRONT_FACE 0x191c +#define NVB197_OGL_SET_FRONT_FACE_V 31:0 +#define NVB197_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVB197_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVB197_OGL_SET_CULL_FACE 0x1920 +#define NVB197_OGL_SET_CULL_FACE_V 31:0 +#define NVB197_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVB197_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVB197_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVB197_SET_VIEWPORT_PIXEL 0x1924 +#define NVB197_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVB197_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVB197_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVB197_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVB197_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVB197_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVB197_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVB197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVB197_SET_USER_CLIP_OP 0x1940 +#define NVB197_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVB197_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVB197_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVB197_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVB197_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVB197_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVB197_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVB197_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVB197_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVB197_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVB197_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVB197_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVB197_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVB197_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVB197_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVB197_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVB197_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVB197_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVB197_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVB197_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVB197_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVB197_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVB197_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVB197_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVB197_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVB197_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVB197_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVB197_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVB197_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVB197_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVB197_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVB197_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVB197_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVB197_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVB197_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVB197_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVB197_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVB197_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVB197_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVB197_INVALIDATE_ZCULL 0x1958 +#define NVB197_INVALIDATE_ZCULL_V 31:0 +#define NVB197_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVB197_SET_ZCULL 0x1968 +#define NVB197_SET_ZCULL_Z_ENABLE 0:0 +#define NVB197_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVB197_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_ZCULL_BOUNDS 0x196c +#define NVB197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVB197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVB197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVB197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVB197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVB197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVB197_ZCULL_SYNC 0x1978 +#define NVB197_ZCULL_SYNC_V 31:0 + +#define NVB197_SET_CLIP_ID_TEST 0x197c +#define NVB197_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVB197_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVB197_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVB197_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVB197_SET_CLIP_ID 0x1984 +#define NVB197_SET_CLIP_ID_V 31:0 + +#define NVB197_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVB197_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVB197_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVB197_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVB197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVB197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVB197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVB197_SET_LOGIC_OP 0x19c4 +#define NVB197_SET_LOGIC_OP_ENABLE 0:0 +#define NVB197_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVB197_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_LOGIC_OP_FUNC 0x19c8 +#define NVB197_SET_LOGIC_OP_FUNC_V 31:0 +#define NVB197_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVB197_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVB197_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVB197_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVB197_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVB197_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVB197_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVB197_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVB197_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVB197_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVB197_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVB197_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVB197_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVB197_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVB197_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVB197_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVB197_SET_Z_COMPRESSION 0x19cc +#define NVB197_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVB197_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVB197_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVB197_CLEAR_SURFACE 0x19d0 +#define NVB197_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVB197_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVB197_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVB197_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVB197_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVB197_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVB197_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVB197_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVB197_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVB197_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVB197_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVB197_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVB197_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVB197_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVB197_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVB197_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVB197_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVB197_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVB197_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVB197_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVB197_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVB197_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVB197_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVB197_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVB197_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVB197_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVB197_SET_CT_WRITE_R_ENABLE 0:0 +#define NVB197_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVB197_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVB197_SET_CT_WRITE_G_ENABLE 4:4 +#define NVB197_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVB197_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVB197_SET_CT_WRITE_B_ENABLE 8:8 +#define NVB197_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVB197_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVB197_SET_CT_WRITE_A_ENABLE 12:12 +#define NVB197_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVB197_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVB197_PIPE_NOP 0x1a2c +#define NVB197_PIPE_NOP_V 31:0 + +#define NVB197_SET_SPARE00 0x1a30 +#define NVB197_SET_SPARE00_V 31:0 + +#define NVB197_SET_SPARE01 0x1a34 +#define NVB197_SET_SPARE01_V 31:0 + +#define NVB197_SET_SPARE02 0x1a38 +#define NVB197_SET_SPARE02_V 31:0 + +#define NVB197_SET_SPARE03 0x1a3c +#define NVB197_SET_SPARE03_V 31:0 + +#define NVB197_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVB197_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVB197_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVB197_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB197_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVB197_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVB197_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVB197_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVB197_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVB197_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVB197_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVB197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVB197_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVB197_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVB197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVB197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVB197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVB197_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVB197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVB197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVB197_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVB197_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVB197_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVB197_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVB197_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVB197_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVB197_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVB197_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVB197_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVB197_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVB197_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVB197_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVB197_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVB197_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVB197_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVB197_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVB197_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVB197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVB197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVB197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVB197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVB197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVB197_SET_VERTEX_STREAM_LIMIT_A_A(j) (0x1f00+(j)*8) +#define NVB197_SET_VERTEX_STREAM_LIMIT_A_A_UPPER 7:0 + +#define NVB197_SET_VERTEX_STREAM_LIMIT_A_B(j) (0x1f04+(j)*8) +#define NVB197_SET_VERTEX_STREAM_LIMIT_A_B_LOWER 31:0 + +#define NVB197_SET_VERTEX_STREAM_LIMIT_B_A(j) (0x1f80+(j)*8) +#define NVB197_SET_VERTEX_STREAM_LIMIT_B_A_UPPER 7:0 + +#define NVB197_SET_VERTEX_STREAM_LIMIT_B_B(j) (0x1f84+(j)*8) +#define NVB197_SET_VERTEX_STREAM_LIMIT_B_B_LOWER 31:0 + +#define NVB197_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVB197_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVB197_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVB197_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVB197_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVB197_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVB197_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVB197_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVB197_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVB197_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVB197_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVB197_SET_PIPELINE_PROGRAM(j) (0x2004+(j)*64) +#define NVB197_SET_PIPELINE_PROGRAM_OFFSET 31:0 + +#define NVB197_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVB197_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVB197_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVB197_SET_PIPELINE_REGISTER_COUNT_V 7:0 + +#define NVB197_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVB197_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVB197_SET_PIPELINE_RESERVED_B(j) (0x2014+(j)*64) +#define NVB197_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVB197_SET_PIPELINE_RESERVED_C(j) (0x2018+(j)*64) +#define NVB197_SET_PIPELINE_RESERVED_C_V 0:0 + +#define NVB197_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVB197_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVB197_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVB197_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVB197_SET_FALCON00 0x2300 +#define NVB197_SET_FALCON00_V 31:0 + +#define NVB197_SET_FALCON01 0x2304 +#define NVB197_SET_FALCON01_V 31:0 + +#define NVB197_SET_FALCON02 0x2308 +#define NVB197_SET_FALCON02_V 31:0 + +#define NVB197_SET_FALCON03 0x230c +#define NVB197_SET_FALCON03_V 31:0 + +#define NVB197_SET_FALCON04 0x2310 +#define NVB197_SET_FALCON04_V 31:0 + +#define NVB197_SET_FALCON05 0x2314 +#define NVB197_SET_FALCON05_V 31:0 + +#define NVB197_SET_FALCON06 0x2318 +#define NVB197_SET_FALCON06_V 31:0 + +#define NVB197_SET_FALCON07 0x231c +#define NVB197_SET_FALCON07_V 31:0 + +#define NVB197_SET_FALCON08 0x2320 +#define NVB197_SET_FALCON08_V 31:0 + +#define NVB197_SET_FALCON09 0x2324 +#define NVB197_SET_FALCON09_V 31:0 + +#define NVB197_SET_FALCON10 0x2328 +#define NVB197_SET_FALCON10_V 31:0 + +#define NVB197_SET_FALCON11 0x232c +#define NVB197_SET_FALCON11_V 31:0 + +#define NVB197_SET_FALCON12 0x2330 +#define NVB197_SET_FALCON12_V 31:0 + +#define NVB197_SET_FALCON13 0x2334 +#define NVB197_SET_FALCON13_V 31:0 + +#define NVB197_SET_FALCON14 0x2338 +#define NVB197_SET_FALCON14_V 31:0 + +#define NVB197_SET_FALCON15 0x233c +#define NVB197_SET_FALCON15_V 31:0 + +#define NVB197_SET_FALCON16 0x2340 +#define NVB197_SET_FALCON16_V 31:0 + +#define NVB197_SET_FALCON17 0x2344 +#define NVB197_SET_FALCON17_V 31:0 + +#define NVB197_SET_FALCON18 0x2348 +#define NVB197_SET_FALCON18_V 31:0 + +#define NVB197_SET_FALCON19 0x234c +#define NVB197_SET_FALCON19_V 31:0 + +#define NVB197_SET_FALCON20 0x2350 +#define NVB197_SET_FALCON20_V 31:0 + +#define NVB197_SET_FALCON21 0x2354 +#define NVB197_SET_FALCON21_V 31:0 + +#define NVB197_SET_FALCON22 0x2358 +#define NVB197_SET_FALCON22_V 31:0 + +#define NVB197_SET_FALCON23 0x235c +#define NVB197_SET_FALCON23_V 31:0 + +#define NVB197_SET_FALCON24 0x2360 +#define NVB197_SET_FALCON24_V 31:0 + +#define NVB197_SET_FALCON25 0x2364 +#define NVB197_SET_FALCON25_V 31:0 + +#define NVB197_SET_FALCON26 0x2368 +#define NVB197_SET_FALCON26_V 31:0 + +#define NVB197_SET_FALCON27 0x236c +#define NVB197_SET_FALCON27_V 31:0 + +#define NVB197_SET_FALCON28 0x2370 +#define NVB197_SET_FALCON28_V 31:0 + +#define NVB197_SET_FALCON29 0x2374 +#define NVB197_SET_FALCON29_V 31:0 + +#define NVB197_SET_FALCON30 0x2378 +#define NVB197_SET_FALCON30_V 31:0 + +#define NVB197_SET_FALCON31 0x237c +#define NVB197_SET_FALCON31_V 31:0 + +#define NVB197_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVB197_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVB197_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVB197_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVB197_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVB197_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVB197_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVB197_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVB197_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVB197_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVB197_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVB197_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVB197_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVB197_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVB197_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVB197_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVB197_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVB197_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVB197_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVB197_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVB197_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVB197_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVB197_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVB197_SET_COLOR_CLAMP 0x2600 +#define NVB197_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVB197_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVB197_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVB197_SET_BINDLESS_TEXTURE 0x2608 +#define NVB197_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 4:0 + +#define NVB197_SET_TRAP_HANDLER 0x260c +#define NVB197_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVB197_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVB197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVB197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVB197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVB197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVB197_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVB197_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVB197_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB197_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVB197_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB197_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVB197_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVB197_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVB197_CALL_MME_MACRO_V 31:0 + +#define NVB197_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVB197_CALL_MME_DATA_V 31:0 + +#endif /* _cl_maxwell_b_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/clb2cc.h b/src/common/sdk/nvidia/inc/class/clb2cc.h index 142ac762b..e539404fe 100644 --- a/src/common/sdk/nvidia/inc/class/clb2cc.h +++ b/src/common/sdk/nvidia/inc/class/clb2cc.h @@ -21,22 +21,26 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _clb2cc_h_ -#define _clb2cc_h_ +#pragma once -#ifdef __cplusplus -extern "C" { -#endif +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clb2cc.finn +// #include "clb0cc.h" -#define MAXWELL_PROFILER_DEVICE (0x0000B2CC) +#define MAXWELL_PROFILER_DEVICE (0xb2ccU) /* finn: Evaluated from "NVB2CC_ALLOC_PARAMETERS_MESSAGE_ID" */ /* * Creating the MAXWELL_PROFILER_DEVICE object: * - The profiler object is instantiated as a child of subdevice. */ -typedef struct { +#define NVB2CC_ALLOC_PARAMETERS_MESSAGE_ID (0xb2ccU) + +typedef struct NVB2CC_ALLOC_PARAMETERS { /* * This parameter specifies the handle of the client that owns the context * specified by hContextTarget. This can set it to 0 where a context @@ -54,8 +58,3 @@ typedef struct { NvHandle hContextTarget; } NVB2CC_ALLOC_PARAMETERS; -#ifdef __cplusplus -}; /* extern "C" */ -#endif - -#endif /* _clb2cc_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/clc097.h b/src/common/sdk/nvidia/inc/class/clc097.h index 6d1e31b4d..129056b4c 100644 --- a/src/common/sdk/nvidia/inc/class/clc097.h +++ b/src/common/sdk/nvidia/inc/class/clc097.h @@ -1,29 +1,4191 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. -#ifndef _clc097_h_ -#define _clc097_h_ + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_pascal_a_h_ +#define _cl_pascal_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl pascal_a */ + +#include "nvtypes.h" #define PASCAL_A 0xC097 -#endif // _clc097_h_ +#define NVC097_SET_OBJECT 0x0000 +#define NVC097_SET_OBJECT_CLASS_ID 15:0 +#define NVC097_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC097_NO_OPERATION 0x0100 +#define NVC097_NO_OPERATION_V 31:0 + +#define NVC097_SET_NOTIFY_A 0x0104 +#define NVC097_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC097_SET_NOTIFY_B 0x0108 +#define NVC097_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC097_NOTIFY 0x010c +#define NVC097_NOTIFY_TYPE 31:0 +#define NVC097_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC097_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC097_WAIT_FOR_IDLE 0x0110 +#define NVC097_WAIT_FOR_IDLE_V 31:0 + +#define NVC097_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVC097_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVC097_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVC097_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVC097_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVC097_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVC097_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVC097_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVC097_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVC097_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVC097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVC097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVC097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVC097_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVC097_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVC097_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVC097_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVC097_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVC097_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC097_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC097_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC097_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC097_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC097_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC097_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC097_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC097_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC097_SEND_GO_IDLE 0x013c +#define NVC097_SEND_GO_IDLE_V 31:0 + +#define NVC097_PM_TRIGGER 0x0140 +#define NVC097_PM_TRIGGER_V 31:0 + +#define NVC097_PM_TRIGGER_WFI 0x0144 +#define NVC097_PM_TRIGGER_WFI_V 31:0 + +#define NVC097_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC097_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC097_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC097_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC097_LINE_LENGTH_IN 0x0180 +#define NVC097_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC097_LINE_COUNT 0x0184 +#define NVC097_LINE_COUNT_VALUE 31:0 + +#define NVC097_OFFSET_OUT_UPPER 0x0188 +#define NVC097_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVC097_OFFSET_OUT 0x018c +#define NVC097_OFFSET_OUT_VALUE 31:0 + +#define NVC097_PITCH_OUT 0x0190 +#define NVC097_PITCH_OUT_VALUE 31:0 + +#define NVC097_SET_DST_BLOCK_SIZE 0x0194 +#define NVC097_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC097_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC097_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC097_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC097_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC097_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC097_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC097_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC097_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC097_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC097_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC097_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC097_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC097_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC097_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC097_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC097_SET_DST_WIDTH 0x0198 +#define NVC097_SET_DST_WIDTH_V 31:0 + +#define NVC097_SET_DST_HEIGHT 0x019c +#define NVC097_SET_DST_HEIGHT_V 31:0 + +#define NVC097_SET_DST_DEPTH 0x01a0 +#define NVC097_SET_DST_DEPTH_V 31:0 + +#define NVC097_SET_DST_LAYER 0x01a4 +#define NVC097_SET_DST_LAYER_V 31:0 + +#define NVC097_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC097_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC097_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC097_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC097_LAUNCH_DMA 0x01b0 +#define NVC097_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC097_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC097_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC097_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC097_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC097_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC097_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC097_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC097_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC097_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC097_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC097_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC097_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC097_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC097_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC097_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC097_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC097_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC097_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC097_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC097_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC097_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC097_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC097_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC097_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC097_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC097_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC097_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC097_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC097_LOAD_INLINE_DATA 0x01b4 +#define NVC097_LOAD_INLINE_DATA_V 31:0 + +#define NVC097_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC097_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC097_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC097_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC097_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC097_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC097_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC097_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC097_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC097_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC097_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC097_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC097_RUN_DS_NOW 0x0200 +#define NVC097_RUN_DS_NOW_V 31:0 + +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVC097_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVC097_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVC097_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVC097_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVC097_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVC097_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVC097_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVC097_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVC097_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_GS_DM_FIFO 0x0214 +#define NVC097_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVC097_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVC097_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVC097_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVC097_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC097_INVALIDATE_SHADER_CACHES 0x021c +#define NVC097_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC097_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC097_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC097_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC097_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC097_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC097_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC097_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC097_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC097_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC097_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC097_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC097_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC097_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC097_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC097_INCREMENT_SYNC_POINT 0x02c8 +#define NVC097_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVC097_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVC097_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVC097_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVC097_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVC097_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVC097_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVC097_SET_PRIM_CIRCULAR_BUFFER_THROTTLE 0x02d0 +#define NVC097_SET_PRIM_CIRCULAR_BUFFER_THROTTLE_PRIM_AREA 21:0 + +#define NVC097_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVC097_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVC097_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 21:0 + +#define NVC097_DECOMPRESS_SURFACE 0x02e0 +#define NVC097_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVC097_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVC097_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVC097_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVC097_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVC097_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVC097_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVC097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVC097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVC097_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVC097_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVC097_SET_ZCULL_SUBREGION 0x02e8 +#define NVC097_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVC097_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVC097_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVC097_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVC097_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVC097_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVC097_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVC097_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVC097_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVC097_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVC097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVC097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVC097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVC097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVC097_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVC097_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVC097_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVC097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVC097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVC097_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVC097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVC097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVC097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVC097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVC097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC097_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVC097_DRAW_ZERO_INDEX 0x0304 +#define NVC097_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVC097_SET_L1_CONFIGURATION 0x0308 +#define NVC097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVC097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC097_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVC097_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVC097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVC097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVC097_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVC097_SET_SPA_VERSION 0x0310 +#define NVC097_SET_SPA_VERSION_MINOR 7:0 +#define NVC097_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC097_SET_IEEE_CLEAN_UPDATE 0x0314 +#define NVC097_SET_IEEE_CLEAN_UPDATE_ENABLE 0:0 +#define NVC097_SET_IEEE_CLEAN_UPDATE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_IEEE_CLEAN_UPDATE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_SNAP_GRID_LINE 0x0318 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC097_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC097_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVC097_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC097_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC097_SET_SNAP_GRID_NON_LINE 0x031c +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC097_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVC097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC097_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC097_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVC097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVC097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVC097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVC097_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVC097_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVC097_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVC097_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVC097_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVC097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVC097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVC097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVC097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVC097_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVC097_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVC097_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVC097_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVC097_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVC097_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVC097_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVC097_SET_TESSELLATION_LOD_V1 0x0330 +#define NVC097_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVC097_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVC097_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVC097_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVC097_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVC097_RESERVED_TG07 0x033c +#define NVC097_RESERVED_TG07_V 0:0 + +#define NVC097_RESERVED_TG08 0x0340 +#define NVC097_RESERVED_TG08_V 0:0 + +#define NVC097_RESERVED_TG09 0x0344 +#define NVC097_RESERVED_TG09_V 0:0 + +#define NVC097_RESERVED_TG10 0x0348 +#define NVC097_RESERVED_TG10_V 0:0 + +#define NVC097_RESERVED_TG11 0x034c +#define NVC097_RESERVED_TG11_V 0:0 + +#define NVC097_RESERVED_TG12 0x0350 +#define NVC097_RESERVED_TG12_V 0:0 + +#define NVC097_RESERVED_TG13 0x0354 +#define NVC097_RESERVED_TG13_V 0:0 + +#define NVC097_RESERVED_TG14 0x0358 +#define NVC097_RESERVED_TG14_V 0:0 + +#define NVC097_RESERVED_TG15 0x035c +#define NVC097_RESERVED_TG15_V 0:0 + +#define NVC097_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVC097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVC097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVC097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVC097_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVC097_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVC097_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVC097_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVC097_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVC097_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVC097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVC097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVC097_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVC097_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVC097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVC097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVC097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC097_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVC097_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVC097_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVC097_SET_RASTER_ENABLE 0x037c +#define NVC097_SET_RASTER_ENABLE_V 0:0 +#define NVC097_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVC097_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVC097_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVC097_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVC097_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVC097_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVC097_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVC097_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVC097_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVC097_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVC097_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVC097_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVC097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVC097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVC097_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVC097_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVC097_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVC097_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVC097_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVC097_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVC097_SET_RASTER_INPUT 0x0740 +#define NVC097_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVC097_SET_STREAM_OUTPUT 0x0744 +#define NVC097_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVC097_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVC097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVC097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_ALPHA_FRACTION 0x074c +#define NVC097_SET_ALPHA_FRACTION_V 7:0 + +#define NVC097_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVC097_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVC097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVC097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVC097_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVC097_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVC097_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC097_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC097_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC097_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVC097_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC097_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC097_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVC097_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVC097_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVC097_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVC097_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVC097_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVC097_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVC097_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC097_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVC097_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC097_SET_ISBE_SAVE_RESTORE_PROGRAM 0x07ac +#define NVC097_SET_ISBE_SAVE_RESTORE_PROGRAM_OFFSET 31:0 + +#define NVC097_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVC097_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVC097_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVC097_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVC097_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVC097_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVC097_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVC097_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVC097_SET_CULL_BEFORE_FETCH 0x07dc +#define NVC097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVC097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVC097_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVC097_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVC097_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVC097_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVC097_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVC097_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVC097_SET_ZCULL_STORAGE_A 0x07e8 +#define NVC097_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVC097_SET_ZCULL_STORAGE_B 0x07ec +#define NVC097_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVC097_SET_ZCULL_STORAGE_C 0x07f0 +#define NVC097_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC097_SET_ZCULL_STORAGE_D 0x07f4 +#define NVC097_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC097_SET_ZT_READ_ONLY 0x07f8 +#define NVC097_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVC097_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVC097_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVC097_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVC097_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVC097_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVC097_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVC097_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVC097_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVC097_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVC097_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVC097_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVC097_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVC097_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVC097_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVC097_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVC097_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVC097_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVC097_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVC097_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVC097_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVC097_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVC097_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVC097_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVC097_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVC097_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC097_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC097_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVC097_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC097_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVC097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC097_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVC097_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVC097_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVC097_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVC097_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVC097_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVC097_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVC097_SET_COLOR_TARGET_MARK(j) (0x0824+(j)*64) +#define NVC097_SET_COLOR_TARGET_MARK_IEEE_CLEAN 0:0 +#define NVC097_SET_COLOR_TARGET_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVC097_SET_COLOR_TARGET_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVC097_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVC097_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVC097_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVC097_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVC097_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVC097_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVC097_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVC097_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVC097_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVC097_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVC097_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVC097_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVC097_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVC097_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVC097_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVC097_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVC097_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVC097_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVC097_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC097_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVC097_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVC097_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC097_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVC097_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVC097_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVC097_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVC097_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVC097_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVC097_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVC097_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVC097_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVC097_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVC097_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVC097_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVC097_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVC097_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVC097_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVC097_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVC097_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVC097_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC097_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVC097_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVC097_SET_STATISTICS_COUNTER 0x0d68 +#define NVC097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVC097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVC097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVC097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVC097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVC097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVC097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVC097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVC097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVC097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVC097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVC097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVC097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVC097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVC097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVC097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVC097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVC097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVC097_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC097_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC097_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVC097_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC097_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC097_SET_VERTEX_ARRAY_START 0x0d74 +#define NVC097_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVC097_DRAW_VERTEX_ARRAY 0x0d78 +#define NVC097_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVC097_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVC097_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVC097_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVC097_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVC097_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVC097_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVC097_SET_Z_CLEAR_VALUE 0x0d90 +#define NVC097_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVC097_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC097_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVC097_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVC097_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVC097_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC097_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC097_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVC097_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVC097_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVC097_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVC097_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVC097_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVC097_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVC097_SET_FRONT_POLYGON_MODE 0x0dac +#define NVC097_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVC097_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC097_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC097_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC097_SET_BACK_POLYGON_MODE 0x0db0 +#define NVC097_SET_BACK_POLYGON_MODE_V 31:0 +#define NVC097_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC097_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC097_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC097_SET_POLY_SMOOTH 0x0db4 +#define NVC097_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVC097_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVC097_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_ZT_MARK 0x0db8 +#define NVC097_SET_ZT_MARK_IEEE_CLEAN 0:0 +#define NVC097_SET_ZT_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVC097_SET_ZT_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVC097_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVC097_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVC097_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVC097_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVC097_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVC097_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVC097_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVC097_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVC097_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVC097_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVC097_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVC097_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVC097_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVC097_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVC097_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVC097_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVC097_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_PATCH 0x0dcc +#define NVC097_SET_PATCH_SIZE 7:0 + +#define NVC097_SET_ITERATED_BLEND 0x0dd0 +#define NVC097_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVC097_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVC097_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVC097_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVC097_SET_ZCULL_CRITERION 0x0dd8 +#define NVC097_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVC097_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVC097_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVC097_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVC097_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVC097_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVC097_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVC097_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVC097_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVC097_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVC097_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVC097_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVC097_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVC097_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVC097_SET_ZCULL_CRITERION_SREF 23:16 +#define NVC097_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVC097_PIXEL_SHADER_BARRIER 0x0de0 +#define NVC097_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVC097_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVC097_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC097_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVC097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVC097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVC097_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVC097_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVC097_SET_WINDOW_OFFSET_X 0x0df8 +#define NVC097_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVC097_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVC097_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVC097_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVC097_SET_SCISSOR_ENABLE_V 0:0 +#define NVC097_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVC097_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVC097_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVC097_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVC097_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVC097_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVC097_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVC097_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVC097_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0f10 +#define NVC097_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVC097_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVC097_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVC097_SET_VPC_PERF_KNOB 0x0f14 +#define NVC097_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVC097_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVC097_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVC097_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVC097_PM_LOCAL_TRIGGER 0x0f18 +#define NVC097_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVC097_SET_POST_Z_PS_IMASK 0x0f1c +#define NVC097_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVC097_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVC097_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVC097_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVC097_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVC097_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVC097_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVC097_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVC097_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVC097_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVC097_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVC097_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVC097_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVC097_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVC097_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVC097_SET_BACK_STENCIL_MASK 0x0f58 +#define NVC097_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVC097_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVC097_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVC097_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVC097_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVC097_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVC097_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVC097_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVC097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVC097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVC097_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVC097_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVC097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVC097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVC097_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVC097_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVC097_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVC097_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVC097_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVC097_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVC097_SET_SAMPLE_MASK 0x0fa4 +#define NVC097_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVC097_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVC097_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVC097_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVC097_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVC097_SET_CT_MRT_ENABLE 0x0fac +#define NVC097_SET_CT_MRT_ENABLE_V 0:0 +#define NVC097_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVC097_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVC097_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVC097_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVC097_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVC097_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVC097_SET_TIR 0x0fb4 +#define NVC097_SET_TIR_MODE 1:0 +#define NVC097_SET_TIR_MODE_DISABLED 0x00000000 +#define NVC097_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVC097_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVC097_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVC097_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVC097_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVC097_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC097_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC097_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVC097_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVC097_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVC097_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVC097_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVC097_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVC097_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVC097_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVC097_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVC097_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVC097_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVC097_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_TIR_MODULATION 0x0fd4 +#define NVC097_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVC097_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVC097_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVC097_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVC097_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVC097_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVC097_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVC097_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVC097_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVC097_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVC097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVC097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVC097_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVC097_SET_ZT_A 0x0fe0 +#define NVC097_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_ZT_B 0x0fe4 +#define NVC097_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_ZT_FORMAT 0x0fe8 +#define NVC097_SET_ZT_FORMAT_V 4:0 +#define NVC097_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVC097_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVC097_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVC097_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVC097_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVC097_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVC097_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVC097_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVC097_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVC097_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVC097_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVC097_SET_ZT_BLOCK_SIZE 0x0fec +#define NVC097_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVC097_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC097_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVC097_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC097_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC097_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC097_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC097_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC097_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC097_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVC097_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC097_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVC097_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVC097_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVC097_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVC097_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC097_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVC097_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVC097_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC097_SET_TILED_CACHE_BUNDLE_CONTROL 0x0ffc +#define NVC097_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT 0:0 +#define NVC097_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT_FALSE 0x00000000 +#define NVC097_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT_TRUE 0x00000001 + +#define NVC097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC097_SET_VIEWPORT_MULTICAST 0x1004 +#define NVC097_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVC097_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVC097_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVC097_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVC097_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVC097_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVC097_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC097_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVC097_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVC097_SET_RESERVED_SW_METHOD00 0x1014 +#define NVC097_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC097_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVC097_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC097_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVC097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVC097_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC097_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVC097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_RESERVED_SW_METHOD01 0x1028 +#define NVC097_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD02 0x102c +#define NVC097_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC097_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVC097_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVC097_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVC097_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVC097_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVC097_SET_SPARE_NOOP01 0x1044 +#define NVC097_SET_SPARE_NOOP01_V 31:0 + +#define NVC097_SET_SPARE_NOOP02 0x1048 +#define NVC097_SET_SPARE_NOOP02_V 31:0 + +#define NVC097_SET_SPARE_NOOP03 0x104c +#define NVC097_SET_SPARE_NOOP03_V 31:0 + +#define NVC097_SET_SPARE_NOOP04 0x1050 +#define NVC097_SET_SPARE_NOOP04_V 31:0 + +#define NVC097_SET_SPARE_NOOP05 0x1054 +#define NVC097_SET_SPARE_NOOP05_V 31:0 + +#define NVC097_SET_SPARE_NOOP06 0x1058 +#define NVC097_SET_SPARE_NOOP06_V 31:0 + +#define NVC097_SET_SPARE_NOOP07 0x105c +#define NVC097_SET_SPARE_NOOP07_V 31:0 + +#define NVC097_SET_SPARE_NOOP08 0x1060 +#define NVC097_SET_SPARE_NOOP08_V 31:0 + +#define NVC097_SET_SPARE_NOOP09 0x1064 +#define NVC097_SET_SPARE_NOOP09_V 31:0 + +#define NVC097_SET_SPARE_NOOP10 0x1068 +#define NVC097_SET_SPARE_NOOP10_V 31:0 + +#define NVC097_SET_SPARE_NOOP11 0x106c +#define NVC097_SET_SPARE_NOOP11_V 31:0 + +#define NVC097_SET_SPARE_NOOP12 0x1070 +#define NVC097_SET_SPARE_NOOP12_V 31:0 + +#define NVC097_SET_SPARE_NOOP13 0x1074 +#define NVC097_SET_SPARE_NOOP13_V 31:0 + +#define NVC097_SET_SPARE_NOOP14 0x1078 +#define NVC097_SET_SPARE_NOOP14_V 31:0 + +#define NVC097_SET_SPARE_NOOP15 0x107c +#define NVC097_SET_SPARE_NOOP15_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVC097_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVC097_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVC097_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD06 0x10bc +#define NVC097_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVC097_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVC097_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVC097_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVC097_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVC097_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVC097_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVC097_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD13 0x10dc +#define NVC097_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC097_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVC097_UNBIND_ALL 0x10f4 +#define NVC097_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVC097_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVC097_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVC097_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVC097_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC097_SET_RESERVED_SW_METHOD14 0x1100 +#define NVC097_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC097_SET_RESERVED_SW_METHOD15 0x1104 +#define NVC097_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC097_NO_OPERATION_DATA_HI 0x110c +#define NVC097_NO_OPERATION_DATA_HI_V 31:0 + +#define NVC097_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVC097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVC097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVC097_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVC097_PM_TRIGGER_END 0x1114 +#define NVC097_PM_TRIGGER_END_V 31:0 + +#define NVC097_SET_VERTEX_ID_BASE 0x1118 +#define NVC097_SET_VERTEX_ID_BASE_V 31:0 + +#define NVC097_SET_STENCIL_COMPRESSION 0x111c +#define NVC097_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVC097_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC097_SET_TIR_CONTROL 0x1130 +#define NVC097_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVC097_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC097_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC097_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVC097_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC097_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC097_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVC097_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVC097_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 + +#define NVC097_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVC097_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVC097_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVC097_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVC097_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVC097_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVC097_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVC097_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVC097_SET_FILL_VIA_TRIANGLE 0x113c +#define NVC097_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVC097_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVC097_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVC097_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVC097_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVC097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVC097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVC097_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVC097_FLUSH_PENDING_WRITES 0x1144 +#define NVC097_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVC097_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVC097_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC097_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC097_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC097_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVC097_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC097_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC097_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVC097_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVC097_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVC097_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVC097_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVC097_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVC097_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVC097_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVC097_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVC097_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVC097_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVC097_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVC097_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVC097_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVC097_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVC097_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC097_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC097_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVC097_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC097_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_SCREEN_STATE_MASK 0x1204 +#define NVC097_SET_SCREEN_STATE_MASK_MASK 3:0 + +#define NVC097_SET_ZT_SPARSE 0x1208 +#define NVC097_SET_ZT_SPARSE_ENABLE 0:0 +#define NVC097_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVC097_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVC097_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVC097_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVC097_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC097_SET_CT_SELECT 0x121c +#define NVC097_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVC097_SET_CT_SELECT_TARGET0 6:4 +#define NVC097_SET_CT_SELECT_TARGET1 9:7 +#define NVC097_SET_CT_SELECT_TARGET2 12:10 +#define NVC097_SET_CT_SELECT_TARGET3 15:13 +#define NVC097_SET_CT_SELECT_TARGET4 18:16 +#define NVC097_SET_CT_SELECT_TARGET5 21:19 +#define NVC097_SET_CT_SELECT_TARGET6 24:22 +#define NVC097_SET_CT_SELECT_TARGET7 27:25 + +#define NVC097_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVC097_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVC097_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVC097_SET_ZT_SIZE_A 0x1228 +#define NVC097_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVC097_SET_ZT_SIZE_B 0x122c +#define NVC097_SET_ZT_SIZE_B_HEIGHT 17:0 + +#define NVC097_SET_ZT_SIZE_C 0x1230 +#define NVC097_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVC097_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVC097_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC097_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVC097_SET_SAMPLER_BINDING 0x1234 +#define NVC097_SET_SAMPLER_BINDING_V 0:0 +#define NVC097_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVC097_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVC097_DRAW_AUTO 0x123c +#define NVC097_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVC097_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVC097_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVC097_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVC097_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVC097_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVC097_SET_BACK_END_COPY_A 0x1264 +#define NVC097_SET_BACK_END_COPY_A_DWORDS 7:0 +#define NVC097_SET_BACK_END_COPY_A_SATURATE32_ENABLE 8:8 +#define NVC097_SET_BACK_END_COPY_A_SATURATE32_ENABLE_FALSE 0x00000000 +#define NVC097_SET_BACK_END_COPY_A_SATURATE32_ENABLE_TRUE 0x00000001 +#define NVC097_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE 12:12 +#define NVC097_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_FALSE 0x00000000 +#define NVC097_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_BACK_END_COPY_B 0x1268 +#define NVC097_SET_BACK_END_COPY_B_SRC_ADDRESS_UPPER 7:0 + +#define NVC097_SET_BACK_END_COPY_C 0x126c +#define NVC097_SET_BACK_END_COPY_C_SRC_ADDRESS_LOWER 31:0 + +#define NVC097_SET_BACK_END_COPY_D 0x1270 +#define NVC097_SET_BACK_END_COPY_D_DEST_ADDRESS_UPPER 7:0 + +#define NVC097_SET_BACK_END_COPY_E 0x1274 +#define NVC097_SET_BACK_END_COPY_E_DEST_ADDRESS_LOWER 31:0 + +#define NVC097_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVC097_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 21:0 + +#define NVC097_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVC097_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVC097_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC097_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVC097_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVC097_CLEAR_ZCULL_REGION 0x12c8 +#define NVC097_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVC097_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVC097_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVC097_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVC097_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC097_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVC097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC097_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVC097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVC097_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVC097_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVC097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVC097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVC097_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVC097_SET_DEPTH_TEST 0x12cc +#define NVC097_SET_DEPTH_TEST_ENABLE 0:0 +#define NVC097_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVC097_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_FILL_MODE 0x12d0 +#define NVC097_SET_FILL_MODE_V 31:0 +#define NVC097_SET_FILL_MODE_V_POINT 0x00000001 +#define NVC097_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVC097_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVC097_SET_SHADE_MODE 0x12d4 +#define NVC097_SET_SHADE_MODE_V 31:0 +#define NVC097_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVC097_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVC097_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVC097_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC097_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVC097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVC097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVC097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVC097_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVC097_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVC097_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVC097_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVC097_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_DEPTH_WRITE 0x12e8 +#define NVC097_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVC097_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_ALPHA_TEST 0x12ec +#define NVC097_SET_ALPHA_TEST_ENABLE 0:0 +#define NVC097_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVC097_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVC097_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVC097_DRAW_INLINE_INDEX4X8 0x1304 +#define NVC097_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVC097_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVC097_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVC097_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVC097_D3D_SET_CULL_MODE 0x1308 +#define NVC097_D3D_SET_CULL_MODE_V 31:0 +#define NVC097_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVC097_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVC097_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVC097_SET_DEPTH_FUNC 0x130c +#define NVC097_SET_DEPTH_FUNC_V 31:0 +#define NVC097_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVC097_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVC097_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC097_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC097_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVC097_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC097_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC097_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC097_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVC097_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVC097_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC097_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC097_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVC097_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC097_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC097_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC097_SET_ALPHA_REF 0x1310 +#define NVC097_SET_ALPHA_REF_V 31:0 + +#define NVC097_SET_ALPHA_FUNC 0x1314 +#define NVC097_SET_ALPHA_FUNC_V 31:0 +#define NVC097_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVC097_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVC097_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC097_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC097_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVC097_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC097_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC097_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC097_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVC097_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVC097_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC097_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC097_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVC097_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC097_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC097_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC097_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVC097_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVC097_SET_BLEND_CONST_RED 0x131c +#define NVC097_SET_BLEND_CONST_RED_V 31:0 + +#define NVC097_SET_BLEND_CONST_GREEN 0x1320 +#define NVC097_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVC097_SET_BLEND_CONST_BLUE 0x1324 +#define NVC097_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVC097_SET_BLEND_CONST_ALPHA 0x1328 +#define NVC097_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVC097_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC097_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC097_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC097_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC097_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC097_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC097_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVC097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC097_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_BLEND_COLOR_OP 0x1340 +#define NVC097_SET_BLEND_COLOR_OP_V 31:0 +#define NVC097_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC097_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC097_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC097_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC097_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC097_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC097_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC097_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC097_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC097_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC097_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC097_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC097_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC097_SET_BLEND_ALPHA_OP 0x134c +#define NVC097_SET_BLEND_ALPHA_OP_V 31:0 +#define NVC097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC097_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC097_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC097_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC097_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC097_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC097_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC097_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC097_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC097_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC097_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVC097_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVC097_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVC097_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC097_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC097_SET_SINGLE_ROP_CONTROL 0x135c +#define NVC097_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVC097_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_BLEND(i) (0x1360+(i)*4) +#define NVC097_SET_BLEND_ENABLE 0:0 +#define NVC097_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVC097_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_STENCIL_TEST 0x1380 +#define NVC097_SET_STENCIL_TEST_ENABLE 0:0 +#define NVC097_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC097_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_STENCIL_OP_FAIL 0x1384 +#define NVC097_SET_STENCIL_OP_FAIL_V 31:0 +#define NVC097_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC097_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC097_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC097_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC097_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC097_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC097_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC097_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC097_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC097_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC097_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC097_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC097_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC097_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC097_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC097_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC097_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVC097_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC097_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC097_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC097_SET_STENCIL_OP_ZPASS 0x138c +#define NVC097_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVC097_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC097_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC097_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC097_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC097_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC097_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC097_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC097_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC097_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC097_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC097_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC097_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC097_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC097_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC097_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC097_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC097_SET_STENCIL_FUNC 0x1390 +#define NVC097_SET_STENCIL_FUNC_V 31:0 +#define NVC097_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC097_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC097_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC097_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC097_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC097_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC097_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC097_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC097_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC097_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC097_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC097_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC097_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC097_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC097_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC097_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC097_SET_STENCIL_FUNC_REF 0x1394 +#define NVC097_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVC097_SET_STENCIL_FUNC_MASK 0x1398 +#define NVC097_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVC097_SET_STENCIL_MASK 0x139c +#define NVC097_SET_STENCIL_MASK_V 7:0 + +#define NVC097_SET_DRAW_AUTO_START 0x13a4 +#define NVC097_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVC097_SET_PS_SATURATE 0x13a8 +#define NVC097_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVC097_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVC097_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC097_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVC097_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVC097_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC097_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVC097_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVC097_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC097_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVC097_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVC097_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC097_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVC097_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVC097_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC097_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVC097_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVC097_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC097_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVC097_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVC097_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC097_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVC097_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVC097_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC097_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVC097_SET_WINDOW_ORIGIN 0x13ac +#define NVC097_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVC097_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVC097_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVC097_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVC097_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVC097_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVC097_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVC097_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC097_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVC097_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC097_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVC097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVC097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_ALPHA_HYSTERESIS 0x1420 +#define NVC097_SET_ALPHA_HYSTERESIS_ROUNDS_OF_ALPHA 7:0 + +#define NVC097_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC097_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC097_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC097_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC097_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVC097_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVC097_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVC097_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVC097_SET_PS_WARP_WATERMARKS 0x1450 +#define NVC097_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVC097_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVC097_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVC097_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVC097_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC097_STORE_ZCULL 0x1464 +#define NVC097_STORE_ZCULL_V 0:0 + +#define NVC097_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVC097_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVC097_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVC097_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVC097_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVC097_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVC097_LOAD_ZCULL 0x1500 +#define NVC097_LOAD_ZCULL_V 0:0 + +#define NVC097_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVC097_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVC097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVC097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC097_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC097_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVC097_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC097_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC097_SET_USER_CLIP_ENABLE 0x1510 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVC097_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVC097_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVC097_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVC097_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_POINT_SIZE 0x1518 +#define NVC097_SET_POINT_SIZE_V 31:0 + +#define NVC097_SET_ZCULL_STATS 0x151c +#define NVC097_SET_ZCULL_STATS_ENABLE 0:0 +#define NVC097_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_POINT_SPRITE 0x1520 +#define NVC097_SET_POINT_SPRITE_ENABLE 0:0 +#define NVC097_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC097_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC097_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC097_CLEAR_REPORT_VALUE 0x1530 +#define NVC097_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVC097_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVC097_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVC097_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVC097_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVC097_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVC097_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVC097_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 + +#define NVC097_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVC097_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVC097_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVC097_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVC097_SET_ZT_SELECT 0x1538 +#define NVC097_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVC097_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVC097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVC097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVC097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVC097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVC097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVC097_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVC097_SET_RENDER_ENABLE_A 0x1550 +#define NVC097_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_RENDER_ENABLE_B 0x1554 +#define NVC097_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_RENDER_ENABLE_C 0x1558 +#define NVC097_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC097_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC097_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC097_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC097_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC097_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC097_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC097_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC097_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC097_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC097_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVC097_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVC097_SET_ANTI_ALIASED_LINE 0x1570 +#define NVC097_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVC097_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC097_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC097_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_TEX_HEADER_POOL_C 0x157c +#define NVC097_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC097_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVC097_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVC097_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVC097_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVC097_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC097_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC097_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC097_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC097_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC097_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC097_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVC097_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVC097_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC097_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC097_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC097_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC097_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC097_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC097_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC097_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC097_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC097_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC097_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC097_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC097_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC097_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC097_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC097_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC097_SET_SRGB_WRITE 0x15b8 +#define NVC097_SET_SRGB_WRITE_ENABLE 0:0 +#define NVC097_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_DEPTH_BIAS 0x15bc +#define NVC097_SET_DEPTH_BIAS_V 31:0 + +#define NVC097_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVC097_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVC097_SET_RT_LAYER 0x15cc +#define NVC097_SET_RT_LAYER_V 15:0 +#define NVC097_SET_RT_LAYER_CONTROL 16:16 +#define NVC097_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVC097_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVC097_SET_ANTI_ALIAS 0x15d0 +#define NVC097_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVC097_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVC097_SET_EDGE_FLAG 0x15e4 +#define NVC097_SET_EDGE_FLAG_V 0:0 +#define NVC097_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVC097_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVC097_DRAW_INLINE_INDEX 0x15e8 +#define NVC097_DRAW_INLINE_INDEX_V 31:0 + +#define NVC097_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVC097_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVC097_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVC097_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVC097_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVC097_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVC097_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVC097_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVC097_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVC097_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVC097_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVC097_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVC097_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVC097_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVC097_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVC097_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVC097_SET_POINT_SPRITE_SELECT 0x1604 +#define NVC097_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVC097_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVC097_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVC097_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVC097_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVC097_SET_PROGRAM_REGION_A 0x1608 +#define NVC097_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVC097_SET_PROGRAM_REGION_B 0x160c +#define NVC097_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVC097_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVC097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVC097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVC097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVC097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVC097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVC097_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVC097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVC097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVC097_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVC097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVC097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVC097_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVC097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVC097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVC097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVC097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVC097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVC097_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVC097_END 0x1614 +#define NVC097_END_V 0:0 + +#define NVC097_BEGIN 0x1618 +#define NVC097_BEGIN_OP 15:0 +#define NVC097_BEGIN_OP_POINTS 0x00000000 +#define NVC097_BEGIN_OP_LINES 0x00000001 +#define NVC097_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVC097_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVC097_BEGIN_OP_TRIANGLES 0x00000004 +#define NVC097_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVC097_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVC097_BEGIN_OP_QUADS 0x00000007 +#define NVC097_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVC097_BEGIN_OP_POLYGON 0x00000009 +#define NVC097_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVC097_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVC097_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_BEGIN_OP_PATCH 0x0000000E +#define NVC097_BEGIN_PRIMITIVE_ID 24:24 +#define NVC097_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC097_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC097_BEGIN_INSTANCE_ID 27:26 +#define NVC097_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVC097_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC097_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC097_BEGIN_SPLIT_MODE 30:29 +#define NVC097_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC097_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC097_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC097_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 + +#define NVC097_SET_VERTEX_ID_COPY 0x161c +#define NVC097_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVC097_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVC097_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVC097_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVC097_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVC097_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVC097_LOAD_PRIMITIVE_ID 0x1624 +#define NVC097_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVC097_SET_SHADER_BASED_CULL 0x162c +#define NVC097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVC097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVC097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVC097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVC097_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_CLASS_VERSION 0x1638 +#define NVC097_SET_CLASS_VERSION_CURRENT 15:0 +#define NVC097_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC097_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVC097_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVC097_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVC097_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVC097_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVC097_SET_DA_OUTPUT 0x164c +#define NVC097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVC097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVC097_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVC097_SET_ANTI_ALIASED_POINT 0x1658 +#define NVC097_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVC097_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_POINT_CENTER_MODE 0x165c +#define NVC097_SET_POINT_CENTER_MODE_V 31:0 +#define NVC097_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVC097_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVC097_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVC097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVC097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVC097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVC097_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVC097_SET_LINE_STIPPLE 0x166c +#define NVC097_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVC097_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVC097_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVC097_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVC097_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVC097_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVC097_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVC097_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVC097_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVC097_SET_PROVOKING_VERTEX 0x1684 +#define NVC097_SET_PROVOKING_VERTEX_V 0:0 +#define NVC097_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVC097_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVC097_SET_TWO_SIDED_LIGHT 0x1688 +#define NVC097_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVC097_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_POLYGON_STIPPLE 0x168c +#define NVC097_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVC097_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_SHADER_CONTROL 0x1690 +#define NVC097_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVC097_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVC097_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVC097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVC097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC097_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVC097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC097_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVC097_CHECK_CLASS_VERSION 0x16a0 +#define NVC097_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVC097_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC097_SET_SPH_VERSION 0x16a4 +#define NVC097_SET_SPH_VERSION_CURRENT 15:0 +#define NVC097_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC097_CHECK_SPH_VERSION 0x16a8 +#define NVC097_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVC097_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC097_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVC097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVC097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVC097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVC097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVC097_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVC097_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVC097_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVC097_SET_AAM_VERSION 0x1790 +#define NVC097_SET_AAM_VERSION_CURRENT 15:0 +#define NVC097_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC097_CHECK_AAM_VERSION 0x1794 +#define NVC097_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVC097_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC097_SET_ZT_LAYER 0x179c +#define NVC097_SET_ZT_LAYER_OFFSET 15:0 + +#define NVC097_SET_INDEX_BUFFER_A 0x17c8 +#define NVC097_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVC097_SET_INDEX_BUFFER_B 0x17cc +#define NVC097_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVC097_SET_INDEX_BUFFER_C 0x17d0 +#define NVC097_SET_INDEX_BUFFER_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC097_SET_INDEX_BUFFER_D 0x17d4 +#define NVC097_SET_INDEX_BUFFER_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC097_SET_INDEX_BUFFER_E 0x17d8 +#define NVC097_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVC097_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVC097_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVC097_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVC097_SET_INDEX_BUFFER_F 0x17dc +#define NVC097_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVC097_DRAW_INDEX_BUFFER 0x17e0 +#define NVC097_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC097_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVC097_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVC097_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVC097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVC097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVC097_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVC097_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVC097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVC097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVC097_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVC097_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVC097_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVC097_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVC097_OGL_SET_CULL 0x1918 +#define NVC097_OGL_SET_CULL_ENABLE 0:0 +#define NVC097_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVC097_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVC097_OGL_SET_FRONT_FACE 0x191c +#define NVC097_OGL_SET_FRONT_FACE_V 31:0 +#define NVC097_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVC097_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVC097_OGL_SET_CULL_FACE 0x1920 +#define NVC097_OGL_SET_CULL_FACE_V 31:0 +#define NVC097_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVC097_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVC097_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVC097_SET_VIEWPORT_PIXEL 0x1924 +#define NVC097_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVC097_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVC097_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVC097_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVC097_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVC097_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVC097_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVC097_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVC097_SET_USER_CLIP_OP 0x1940 +#define NVC097_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVC097_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVC097_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVC097_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVC097_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVC097_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVC097_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVC097_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVC097_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVC097_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVC097_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVC097_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVC097_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVC097_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVC097_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVC097_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVC097_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVC097_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVC097_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVC097_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVC097_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVC097_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVC097_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVC097_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVC097_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC097_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC097_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC097_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC097_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC097_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVC097_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVC097_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVC097_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVC097_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVC097_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVC097_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVC097_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVC097_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVC097_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVC097_INVALIDATE_ZCULL 0x1958 +#define NVC097_INVALIDATE_ZCULL_V 31:0 +#define NVC097_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVC097_SET_ZCULL 0x1968 +#define NVC097_SET_ZCULL_Z_ENABLE 0:0 +#define NVC097_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVC097_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_ZCULL_BOUNDS 0x196c +#define NVC097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVC097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVC097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVC097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC097_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVC097_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVC097_ZCULL_SYNC 0x1978 +#define NVC097_ZCULL_SYNC_V 31:0 + +#define NVC097_SET_CLIP_ID_TEST 0x197c +#define NVC097_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVC097_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVC097_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVC097_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVC097_SET_CLIP_ID 0x1984 +#define NVC097_SET_CLIP_ID_V 31:0 + +#define NVC097_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVC097_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVC097_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVC097_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVC097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVC097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVC097_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVC097_SET_LOGIC_OP 0x19c4 +#define NVC097_SET_LOGIC_OP_ENABLE 0:0 +#define NVC097_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVC097_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_LOGIC_OP_FUNC 0x19c8 +#define NVC097_SET_LOGIC_OP_FUNC_V 31:0 +#define NVC097_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVC097_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVC097_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVC097_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVC097_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVC097_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVC097_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVC097_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVC097_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVC097_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVC097_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVC097_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVC097_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVC097_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVC097_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVC097_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVC097_SET_Z_COMPRESSION 0x19cc +#define NVC097_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVC097_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC097_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC097_CLEAR_SURFACE 0x19d0 +#define NVC097_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVC097_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC097_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC097_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVC097_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC097_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC097_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVC097_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVC097_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVC097_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVC097_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVC097_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVC097_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVC097_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVC097_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVC097_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVC097_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVC097_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVC097_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVC097_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVC097_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVC097_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVC097_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVC097_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVC097_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC097_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVC097_SET_CT_WRITE_R_ENABLE 0:0 +#define NVC097_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVC097_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVC097_SET_CT_WRITE_G_ENABLE 4:4 +#define NVC097_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVC097_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVC097_SET_CT_WRITE_B_ENABLE 8:8 +#define NVC097_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVC097_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVC097_SET_CT_WRITE_A_ENABLE 12:12 +#define NVC097_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVC097_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVC097_PIPE_NOP 0x1a2c +#define NVC097_PIPE_NOP_V 31:0 + +#define NVC097_SET_SPARE00 0x1a30 +#define NVC097_SET_SPARE00_V 31:0 + +#define NVC097_SET_SPARE01 0x1a34 +#define NVC097_SET_SPARE01_V 31:0 + +#define NVC097_SET_SPARE02 0x1a38 +#define NVC097_SET_SPARE02_V 31:0 + +#define NVC097_SET_SPARE03 0x1a3c +#define NVC097_SET_SPARE03_V 31:0 + +#define NVC097_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC097_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC097_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC097_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC097_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC097_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC097_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVC097_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC097_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVC097_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVC097_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC097_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC097_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVC097_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVC097_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVC097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC097_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVC097_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVC097_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVC097_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVC097_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVC097_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVC097_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVC097_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVC097_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVC097_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVC097_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVC097_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC097_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVC097_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC097_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVC097_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC097_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVC097_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVC097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVC097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC097_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC097_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC097_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC097_SET_VERTEX_STREAM_LIMIT_A_A(j) (0x1f00+(j)*8) +#define NVC097_SET_VERTEX_STREAM_LIMIT_A_A_UPPER 7:0 + +#define NVC097_SET_VERTEX_STREAM_LIMIT_A_B(j) (0x1f04+(j)*8) +#define NVC097_SET_VERTEX_STREAM_LIMIT_A_B_LOWER 31:0 + +#define NVC097_SET_VERTEX_STREAM_LIMIT_B_A(j) (0x1f80+(j)*8) +#define NVC097_SET_VERTEX_STREAM_LIMIT_B_A_UPPER 7:0 + +#define NVC097_SET_VERTEX_STREAM_LIMIT_B_B(j) (0x1f84+(j)*8) +#define NVC097_SET_VERTEX_STREAM_LIMIT_B_B_LOWER 31:0 + +#define NVC097_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVC097_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVC097_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVC097_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVC097_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVC097_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVC097_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVC097_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVC097_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVC097_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVC097_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVC097_SET_PIPELINE_PROGRAM(j) (0x2004+(j)*64) +#define NVC097_SET_PIPELINE_PROGRAM_OFFSET 31:0 + +#define NVC097_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVC097_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVC097_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVC097_SET_PIPELINE_REGISTER_COUNT_V 7:0 + +#define NVC097_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVC097_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVC097_SET_PIPELINE_RESERVED_B(j) (0x2014+(j)*64) +#define NVC097_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVC097_SET_PIPELINE_RESERVED_C(j) (0x2018+(j)*64) +#define NVC097_SET_PIPELINE_RESERVED_C_V 0:0 + +#define NVC097_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVC097_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVC097_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVC097_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVC097_SET_FALCON00 0x2300 +#define NVC097_SET_FALCON00_V 31:0 + +#define NVC097_SET_FALCON01 0x2304 +#define NVC097_SET_FALCON01_V 31:0 + +#define NVC097_SET_FALCON02 0x2308 +#define NVC097_SET_FALCON02_V 31:0 + +#define NVC097_SET_FALCON03 0x230c +#define NVC097_SET_FALCON03_V 31:0 + +#define NVC097_SET_FALCON04 0x2310 +#define NVC097_SET_FALCON04_V 31:0 + +#define NVC097_SET_FALCON05 0x2314 +#define NVC097_SET_FALCON05_V 31:0 + +#define NVC097_SET_FALCON06 0x2318 +#define NVC097_SET_FALCON06_V 31:0 + +#define NVC097_SET_FALCON07 0x231c +#define NVC097_SET_FALCON07_V 31:0 + +#define NVC097_SET_FALCON08 0x2320 +#define NVC097_SET_FALCON08_V 31:0 + +#define NVC097_SET_FALCON09 0x2324 +#define NVC097_SET_FALCON09_V 31:0 + +#define NVC097_SET_FALCON10 0x2328 +#define NVC097_SET_FALCON10_V 31:0 + +#define NVC097_SET_FALCON11 0x232c +#define NVC097_SET_FALCON11_V 31:0 + +#define NVC097_SET_FALCON12 0x2330 +#define NVC097_SET_FALCON12_V 31:0 + +#define NVC097_SET_FALCON13 0x2334 +#define NVC097_SET_FALCON13_V 31:0 + +#define NVC097_SET_FALCON14 0x2338 +#define NVC097_SET_FALCON14_V 31:0 + +#define NVC097_SET_FALCON15 0x233c +#define NVC097_SET_FALCON15_V 31:0 + +#define NVC097_SET_FALCON16 0x2340 +#define NVC097_SET_FALCON16_V 31:0 + +#define NVC097_SET_FALCON17 0x2344 +#define NVC097_SET_FALCON17_V 31:0 + +#define NVC097_SET_FALCON18 0x2348 +#define NVC097_SET_FALCON18_V 31:0 + +#define NVC097_SET_FALCON19 0x234c +#define NVC097_SET_FALCON19_V 31:0 + +#define NVC097_SET_FALCON20 0x2350 +#define NVC097_SET_FALCON20_V 31:0 + +#define NVC097_SET_FALCON21 0x2354 +#define NVC097_SET_FALCON21_V 31:0 + +#define NVC097_SET_FALCON22 0x2358 +#define NVC097_SET_FALCON22_V 31:0 + +#define NVC097_SET_FALCON23 0x235c +#define NVC097_SET_FALCON23_V 31:0 + +#define NVC097_SET_FALCON24 0x2360 +#define NVC097_SET_FALCON24_V 31:0 + +#define NVC097_SET_FALCON25 0x2364 +#define NVC097_SET_FALCON25_V 31:0 + +#define NVC097_SET_FALCON26 0x2368 +#define NVC097_SET_FALCON26_V 31:0 + +#define NVC097_SET_FALCON27 0x236c +#define NVC097_SET_FALCON27_V 31:0 + +#define NVC097_SET_FALCON28 0x2370 +#define NVC097_SET_FALCON28_V 31:0 + +#define NVC097_SET_FALCON29 0x2374 +#define NVC097_SET_FALCON29_V 31:0 + +#define NVC097_SET_FALCON30 0x2378 +#define NVC097_SET_FALCON30_V 31:0 + +#define NVC097_SET_FALCON31 0x237c +#define NVC097_SET_FALCON31_V 31:0 + +#define NVC097_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVC097_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVC097_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVC097_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVC097_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVC097_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVC097_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVC097_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVC097_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVC097_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVC097_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVC097_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVC097_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVC097_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVC097_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVC097_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVC097_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVC097_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVC097_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVC097_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVC097_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC097_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC097_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVC097_SET_COLOR_CLAMP 0x2600 +#define NVC097_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVC097_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVC097_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVC097_SET_BINDLESS_TEXTURE 0x2608 +#define NVC097_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 4:0 + +#define NVC097_SET_TRAP_HANDLER 0x260c +#define NVC097_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVC097_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVC097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVC097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVC097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVC097_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC097_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC097_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC097_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC097_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC097_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC097_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC097_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVC097_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVC097_CALL_MME_MACRO_V 31:0 + +#define NVC097_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVC097_CALL_MME_DATA_V 31:0 + +#endif /* _cl_pascal_a_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/clc097tex.h b/src/common/sdk/nvidia/inc/class/clc097tex.h new file mode 100644 index 000000000..7c5a822e6 --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/clc097tex.h @@ -0,0 +1,1353 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2010 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLC097TEX_H__ +#define __CLC097TEX_H__ + +/* +** Texture Header State Blocklinear + */ + +#define NVC097_TEXHEAD_BL_COMPONENTS MW(6:0) +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_R32 0x0000000f +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_R16 0x0000001b +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_R8 0x0000001d +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_R1 0x0000001f +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_EAC 0x00000019 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_Z16 0x0000003a +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVC097_TEXHEAD_BL_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVC097_TEXHEAD_BL_R_DATA_TYPE MW(9:7) +#define NVC097_TEXHEAD_BL_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_BL_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_BL_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_BL_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_BL_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_BL_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_BL_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BL_G_DATA_TYPE MW(12:10) +#define NVC097_TEXHEAD_BL_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_BL_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_BL_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_BL_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_BL_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_BL_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_BL_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BL_B_DATA_TYPE MW(15:13) +#define NVC097_TEXHEAD_BL_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_BL_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_BL_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_BL_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_BL_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_BL_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_BL_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BL_A_DATA_TYPE MW(18:16) +#define NVC097_TEXHEAD_BL_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_BL_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_BL_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_BL_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_BL_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_BL_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_BL_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BL_X_SOURCE MW(21:19) +#define NVC097_TEXHEAD_BL_X_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_BL_X_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_BL_X_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_BL_X_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_BL_X_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_BL_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_BL_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BL_Y_SOURCE MW(24:22) +#define NVC097_TEXHEAD_BL_Y_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_BL_Y_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_BL_Y_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_BL_Y_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_BL_Y_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_BL_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_BL_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BL_Z_SOURCE MW(27:25) +#define NVC097_TEXHEAD_BL_Z_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_BL_Z_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_BL_Z_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_BL_Z_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_BL_Z_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_BL_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_BL_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BL_W_SOURCE MW(30:28) +#define NVC097_TEXHEAD_BL_W_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_BL_W_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_BL_W_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_BL_W_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_BL_W_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_BL_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_BL_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BL_PACK_COMPONENTS MW(31:31) +#define NVC097_TEXHEAD_BL_RESERVED1Y MW(36:32) +#define NVC097_TEXHEAD_BL_GOB_DEPTH_OFFSET MW(38:37) +#define NVC097_TEXHEAD_BL_RESERVED1X MW(40:39) +#define NVC097_TEXHEAD_BL_ADDRESS_BITS31TO9 MW(63:41) +#define NVC097_TEXHEAD_BL_ADDRESS_BITS48TO32 MW(80:64) +#define NVC097_TEXHEAD_BL_RESERVED_ADDRESS MW(84:81) +#define NVC097_TEXHEAD_BL_HEADER_VERSION MW(87:85) +#define NVC097_TEXHEAD_BL_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVC097_TEXHEAD_BL_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVC097_TEXHEAD_BL_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVC097_TEXHEAD_BL_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVC097_TEXHEAD_BL_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVC097_TEXHEAD_BL_RESERVED_HEADER_VERSION MW(88:88) +#define NVC097_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVC097_TEXHEAD_BL_RESERVED2A MW(95:93) +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_WIDTH MW(98:96) +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT MW(101:99) +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH MW(104:102) +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC097_TEXHEAD_BL_RESERVED3Y MW(105:105) +#define NVC097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS MW(108:106) +#define NVC097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_ONE_GOB 0x00000000 +#define NVC097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_TWO_GOBS 0x00000001 +#define NVC097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_FOUR_GOBS 0x00000002 +#define NVC097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_EIGHT_GOBS 0x00000003 +#define NVC097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_SIXTEEN_GOBS 0x00000004 +#define NVC097_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_THIRTYTWO_GOBS 0x00000005 +#define NVC097_TEXHEAD_BL_GOB3D MW(109:109) +#define NVC097_TEXHEAD_BL_RESERVED3Z MW(111:110) +#define NVC097_TEXHEAD_BL_LOD_ANISO_QUALITY2 MW(112:112) +#define NVC097_TEXHEAD_BL_LOD_ANISO_QUALITY MW(113:113) +#define NVC097_TEXHEAD_BL_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVC097_TEXHEAD_BL_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVC097_TEXHEAD_BL_LOD_ISO_QUALITY MW(114:114) +#define NVC097_TEXHEAD_BL_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVC097_TEXHEAD_BL_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVC097_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVC097_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVC097_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVC097_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVC097_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVC097_TEXHEAD_BL_ANISO_SPREAD_SCALE MW(121:117) +#define NVC097_TEXHEAD_BL_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVC097_TEXHEAD_BL_DEPTH_TEXTURE MW(123:123) +#define NVC097_TEXHEAD_BL_MAX_MIP_LEVEL MW(127:124) +#define NVC097_TEXHEAD_BL_WIDTH_MINUS_ONE MW(144:128) +#define NVC097_TEXHEAD_BL_DEPTH_MINUS_ONE_BIT14 MW(145:145) +#define NVC097_TEXHEAD_BL_HEIGHT_MINUS_ONE_BIT16 MW(146:146) +#define NVC097_TEXHEAD_BL_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVC097_TEXHEAD_BL_S_R_G_B_CONVERSION MW(150:150) +#define NVC097_TEXHEAD_BL_TEXTURE_TYPE MW(154:151) +#define NVC097_TEXHEAD_BL_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVC097_TEXHEAD_BL_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVC097_TEXHEAD_BL_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVC097_TEXHEAD_BL_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVC097_TEXHEAD_BL_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVC097_TEXHEAD_BL_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVC097_TEXHEAD_BL_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVC097_TEXHEAD_BL_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVC097_TEXHEAD_BL_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVC097_TEXHEAD_BL_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVC097_TEXHEAD_BL_SECTOR_PROMOTION MW(156:155) +#define NVC097_TEXHEAD_BL_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVC097_TEXHEAD_BL_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVC097_TEXHEAD_BL_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVC097_TEXHEAD_BL_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVC097_TEXHEAD_BL_BORDER_SIZE MW(159:157) +#define NVC097_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVC097_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVC097_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVC097_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVC097_TEXHEAD_BL_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVC097_TEXHEAD_BL_HEIGHT_MINUS_ONE MW(175:160) +#define NVC097_TEXHEAD_BL_DEPTH_MINUS_ONE MW(189:176) +#define NVC097_TEXHEAD_BL_RESERVED5A MW(190:190) +#define NVC097_TEXHEAD_BL_NORMALIZED_COORDS MW(191:191) +#define NVC097_TEXHEAD_BL_RESERVED6Y MW(192:192) +#define NVC097_TEXHEAD_BL_TRILIN_OPT MW(197:193) +#define NVC097_TEXHEAD_BL_MIP_LOD_BIAS MW(210:198) +#define NVC097_TEXHEAD_BL_ANISO_BIAS MW(214:211) +#define NVC097_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVC097_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVC097_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVC097_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVC097_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVC097_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVC097_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVC097_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVC097_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVC097_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVC097_TEXHEAD_BL_MAX_ANISOTROPY MW(221:219) +#define NVC097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVC097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVC097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVC097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVC097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVC097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVC097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVC097_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVC097_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVC097_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVC097_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVC097_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVC097_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVC097_TEXHEAD_BL_RES_VIEW_MIN_MIP_LEVEL MW(227:224) +#define NVC097_TEXHEAD_BL_RES_VIEW_MAX_MIP_LEVEL MW(231:228) +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT MW(235:232) +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVC097_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVC097_TEXHEAD_BL_MIN_LOD_CLAMP MW(247:236) +#define NVC097_TEXHEAD_BL_RESERVED7Y MW(255:248) + + +/* +** Texture Header State Blocklinear Color Key + */ + +#define NVC097_TEXHEAD_BLCK_COMPONENTS MW(6:0) +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_R32 0x0000000f +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_R16 0x0000001b +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_R8 0x0000001d +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_R1 0x0000001f +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_EAC 0x00000019 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_Z16 0x0000003a +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVC097_TEXHEAD_BLCK_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVC097_TEXHEAD_BLCK_R_DATA_TYPE MW(9:7) +#define NVC097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_BLCK_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BLCK_G_DATA_TYPE MW(12:10) +#define NVC097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_BLCK_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BLCK_B_DATA_TYPE MW(15:13) +#define NVC097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_BLCK_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BLCK_A_DATA_TYPE MW(18:16) +#define NVC097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_BLCK_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BLCK_X_SOURCE MW(21:19) +#define NVC097_TEXHEAD_BLCK_X_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_BLCK_X_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_BLCK_X_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_BLCK_X_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_BLCK_X_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_BLCK_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_BLCK_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BLCK_Y_SOURCE MW(24:22) +#define NVC097_TEXHEAD_BLCK_Y_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_BLCK_Y_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_BLCK_Y_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_BLCK_Y_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_BLCK_Y_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_BLCK_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_BLCK_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BLCK_Z_SOURCE MW(27:25) +#define NVC097_TEXHEAD_BLCK_Z_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_BLCK_Z_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_BLCK_Z_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_BLCK_Z_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_BLCK_Z_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_BLCK_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_BLCK_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BLCK_W_SOURCE MW(30:28) +#define NVC097_TEXHEAD_BLCK_W_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_BLCK_W_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_BLCK_W_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_BLCK_W_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_BLCK_W_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_BLCK_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_BLCK_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_BLCK_PACK_COMPONENTS MW(31:31) +#define NVC097_TEXHEAD_BLCK_RESERVED1Y MW(36:32) +#define NVC097_TEXHEAD_BLCK_GOB_DEPTH_OFFSET MW(38:37) +#define NVC097_TEXHEAD_BLCK_RESERVED1X MW(40:39) +#define NVC097_TEXHEAD_BLCK_ADDRESS_BITS31TO9 MW(63:41) +#define NVC097_TEXHEAD_BLCK_ADDRESS_BITS48TO32 MW(80:64) +#define NVC097_TEXHEAD_BLCK_RESERVED_ADDRESS MW(84:81) +#define NVC097_TEXHEAD_BLCK_HEADER_VERSION MW(87:85) +#define NVC097_TEXHEAD_BLCK_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVC097_TEXHEAD_BLCK_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVC097_TEXHEAD_BLCK_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVC097_TEXHEAD_BLCK_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVC097_TEXHEAD_BLCK_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVC097_TEXHEAD_BLCK_RESERVED_HEADER_VERSION MW(88:88) +#define NVC097_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVC097_TEXHEAD_BLCK_RESERVED2A MW(95:93) +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_WIDTH MW(98:96) +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT MW(101:99) +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH MW(104:102) +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC097_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC097_TEXHEAD_BLCK_RESERVED3Y MW(105:105) +#define NVC097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS MW(108:106) +#define NVC097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_ONE_GOB 0x00000000 +#define NVC097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_TWO_GOBS 0x00000001 +#define NVC097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_FOUR_GOBS 0x00000002 +#define NVC097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_EIGHT_GOBS 0x00000003 +#define NVC097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_SIXTEEN_GOBS 0x00000004 +#define NVC097_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_THIRTYTWO_GOBS 0x00000005 +#define NVC097_TEXHEAD_BLCK_GOB3D MW(109:109) +#define NVC097_TEXHEAD_BLCK_RESERVED3Z MW(111:110) +#define NVC097_TEXHEAD_BLCK_LOD_ANISO_QUALITY2 MW(112:112) +#define NVC097_TEXHEAD_BLCK_LOD_ANISO_QUALITY MW(113:113) +#define NVC097_TEXHEAD_BLCK_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVC097_TEXHEAD_BLCK_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVC097_TEXHEAD_BLCK_LOD_ISO_QUALITY MW(114:114) +#define NVC097_TEXHEAD_BLCK_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVC097_TEXHEAD_BLCK_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVC097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVC097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVC097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVC097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVC097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVC097_TEXHEAD_BLCK_ANISO_SPREAD_SCALE MW(121:117) +#define NVC097_TEXHEAD_BLCK_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVC097_TEXHEAD_BLCK_DEPTH_TEXTURE MW(123:123) +#define NVC097_TEXHEAD_BLCK_MAX_MIP_LEVEL MW(127:124) +#define NVC097_TEXHEAD_BLCK_WIDTH_MINUS_ONE MW(144:128) +#define NVC097_TEXHEAD_BLCK_DEPTH_MINUS_ONE_BIT14 MW(145:145) +#define NVC097_TEXHEAD_BLCK_HEIGHT_MINUS_ONE_BIT16 MW(146:146) +#define NVC097_TEXHEAD_BLCK_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVC097_TEXHEAD_BLCK_S_R_G_B_CONVERSION MW(150:150) +#define NVC097_TEXHEAD_BLCK_TEXTURE_TYPE MW(154:151) +#define NVC097_TEXHEAD_BLCK_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVC097_TEXHEAD_BLCK_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVC097_TEXHEAD_BLCK_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVC097_TEXHEAD_BLCK_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVC097_TEXHEAD_BLCK_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVC097_TEXHEAD_BLCK_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVC097_TEXHEAD_BLCK_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVC097_TEXHEAD_BLCK_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVC097_TEXHEAD_BLCK_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVC097_TEXHEAD_BLCK_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVC097_TEXHEAD_BLCK_SECTOR_PROMOTION MW(156:155) +#define NVC097_TEXHEAD_BLCK_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVC097_TEXHEAD_BLCK_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVC097_TEXHEAD_BLCK_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVC097_TEXHEAD_BLCK_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVC097_TEXHEAD_BLCK_BORDER_SIZE MW(159:157) +#define NVC097_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVC097_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVC097_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVC097_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVC097_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVC097_TEXHEAD_BLCK_HEIGHT_MINUS_ONE MW(175:160) +#define NVC097_TEXHEAD_BLCK_DEPTH_MINUS_ONE MW(189:176) +#define NVC097_TEXHEAD_BLCK_RESERVED5A MW(190:190) +#define NVC097_TEXHEAD_BLCK_NORMALIZED_COORDS MW(191:191) +#define NVC097_TEXHEAD_BLCK_COLOR_KEY_OP MW(192:192) +#define NVC097_TEXHEAD_BLCK_TRILIN_OPT MW(197:193) +#define NVC097_TEXHEAD_BLCK_MIP_LOD_BIAS MW(210:198) +#define NVC097_TEXHEAD_BLCK_ANISO_BIAS MW(214:211) +#define NVC097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVC097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVC097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVC097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVC097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVC097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVC097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVC097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVC097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVC097_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVC097_TEXHEAD_BLCK_MAX_ANISOTROPY MW(221:219) +#define NVC097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVC097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVC097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVC097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVC097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVC097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVC097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVC097_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVC097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVC097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVC097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVC097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVC097_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVC097_TEXHEAD_BLCK_COLOR_KEY_VALUE MW(255:224) + + +/* +** Texture Header State One-D Buffer + */ + +#define NVC097_TEXHEAD_1D_COMPONENTS MW(6:0) +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_R32 0x0000000f +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_R16 0x0000001b +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_R8 0x0000001d +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_R1 0x0000001f +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_EAC 0x00000019 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_Z16 0x0000003a +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVC097_TEXHEAD_1D_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVC097_TEXHEAD_1D_R_DATA_TYPE MW(9:7) +#define NVC097_TEXHEAD_1D_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_1D_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_1D_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_1D_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_1D_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_1D_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_1D_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_1D_G_DATA_TYPE MW(12:10) +#define NVC097_TEXHEAD_1D_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_1D_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_1D_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_1D_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_1D_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_1D_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_1D_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_1D_B_DATA_TYPE MW(15:13) +#define NVC097_TEXHEAD_1D_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_1D_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_1D_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_1D_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_1D_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_1D_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_1D_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_1D_A_DATA_TYPE MW(18:16) +#define NVC097_TEXHEAD_1D_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_1D_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_1D_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_1D_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_1D_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_1D_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_1D_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_1D_X_SOURCE MW(21:19) +#define NVC097_TEXHEAD_1D_X_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_1D_X_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_1D_X_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_1D_X_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_1D_X_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_1D_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_1D_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_1D_Y_SOURCE MW(24:22) +#define NVC097_TEXHEAD_1D_Y_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_1D_Y_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_1D_Y_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_1D_Y_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_1D_Y_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_1D_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_1D_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_1D_Z_SOURCE MW(27:25) +#define NVC097_TEXHEAD_1D_Z_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_1D_Z_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_1D_Z_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_1D_Z_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_1D_Z_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_1D_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_1D_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_1D_W_SOURCE MW(30:28) +#define NVC097_TEXHEAD_1D_W_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_1D_W_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_1D_W_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_1D_W_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_1D_W_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_1D_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_1D_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_1D_PACK_COMPONENTS MW(31:31) +#define NVC097_TEXHEAD_1D_ADDRESS_BITS31TO0 MW(63:32) +#define NVC097_TEXHEAD_1D_ADDRESS_BITS48TO32 MW(80:64) +#define NVC097_TEXHEAD_1D_RESERVED_ADDRESS MW(84:81) +#define NVC097_TEXHEAD_1D_HEADER_VERSION MW(87:85) +#define NVC097_TEXHEAD_1D_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVC097_TEXHEAD_1D_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVC097_TEXHEAD_1D_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVC097_TEXHEAD_1D_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVC097_TEXHEAD_1D_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVC097_TEXHEAD_1D_RESERVED_HEADER_VERSION MW(88:88) +#define NVC097_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVC097_TEXHEAD_1D_RESERVED2A MW(95:93) +#define NVC097_TEXHEAD_1D_WIDTH_MINUS_ONE_BITS31TO16 MW(111:96) +#define NVC097_TEXHEAD_1D_RESERVED3X MW(127:112) +#define NVC097_TEXHEAD_1D_WIDTH_MINUS_ONE_BITS15TO0 MW(143:128) +#define NVC097_TEXHEAD_1D_RESERVED4X MW(149:144) +#define NVC097_TEXHEAD_1D_S_R_G_B_CONVERSION MW(150:150) +#define NVC097_TEXHEAD_1D_TEXTURE_TYPE MW(154:151) +#define NVC097_TEXHEAD_1D_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVC097_TEXHEAD_1D_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVC097_TEXHEAD_1D_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVC097_TEXHEAD_1D_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVC097_TEXHEAD_1D_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVC097_TEXHEAD_1D_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVC097_TEXHEAD_1D_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVC097_TEXHEAD_1D_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVC097_TEXHEAD_1D_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVC097_TEXHEAD_1D_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVC097_TEXHEAD_1D_SECTOR_PROMOTION MW(156:155) +#define NVC097_TEXHEAD_1D_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVC097_TEXHEAD_1D_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVC097_TEXHEAD_1D_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVC097_TEXHEAD_1D_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVC097_TEXHEAD_1D_RESERVED4Y MW(159:157) +#define NVC097_TEXHEAD_1D_RESERVED5X MW(189:160) +#define NVC097_TEXHEAD_1D_RESERVED5A MW(190:190) +#define NVC097_TEXHEAD_1D_RESERVED5Y MW(191:191) +#define NVC097_TEXHEAD_1D_RESERVED6X MW(223:192) +#define NVC097_TEXHEAD_1D_RESERVED7X MW(255:224) + + +/* +** Texture Header State Pitch + */ + +#define NVC097_TEXHEAD_PITCH_COMPONENTS MW(6:0) +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_R32 0x0000000f +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_R16 0x0000001b +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_R8 0x0000001d +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_R1 0x0000001f +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_EAC 0x00000019 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_Z16 0x0000003a +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVC097_TEXHEAD_PITCH_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVC097_TEXHEAD_PITCH_R_DATA_TYPE MW(9:7) +#define NVC097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_PITCH_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCH_G_DATA_TYPE MW(12:10) +#define NVC097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_PITCH_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCH_B_DATA_TYPE MW(15:13) +#define NVC097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_PITCH_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCH_A_DATA_TYPE MW(18:16) +#define NVC097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_PITCH_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCH_X_SOURCE MW(21:19) +#define NVC097_TEXHEAD_PITCH_X_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_PITCH_X_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_PITCH_X_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_PITCH_X_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_PITCH_X_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_PITCH_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_PITCH_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCH_Y_SOURCE MW(24:22) +#define NVC097_TEXHEAD_PITCH_Y_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_PITCH_Y_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_PITCH_Y_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_PITCH_Y_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_PITCH_Y_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_PITCH_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_PITCH_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCH_Z_SOURCE MW(27:25) +#define NVC097_TEXHEAD_PITCH_Z_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_PITCH_Z_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_PITCH_Z_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_PITCH_Z_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_PITCH_Z_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_PITCH_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_PITCH_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCH_W_SOURCE MW(30:28) +#define NVC097_TEXHEAD_PITCH_W_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_PITCH_W_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_PITCH_W_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_PITCH_W_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_PITCH_W_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_PITCH_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_PITCH_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCH_PACK_COMPONENTS MW(31:31) +#define NVC097_TEXHEAD_PITCH_RESERVED1A MW(36:32) +#define NVC097_TEXHEAD_PITCH_ADDRESS_BITS31TO5 MW(63:37) +#define NVC097_TEXHEAD_PITCH_ADDRESS_BITS48TO32 MW(80:64) +#define NVC097_TEXHEAD_PITCH_RESERVED_ADDRESS MW(84:81) +#define NVC097_TEXHEAD_PITCH_HEADER_VERSION MW(87:85) +#define NVC097_TEXHEAD_PITCH_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVC097_TEXHEAD_PITCH_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVC097_TEXHEAD_PITCH_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVC097_TEXHEAD_PITCH_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVC097_TEXHEAD_PITCH_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVC097_TEXHEAD_PITCH_RESERVED_HEADER_VERSION MW(88:88) +#define NVC097_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVC097_TEXHEAD_PITCH_RESERVED2A MW(95:93) +#define NVC097_TEXHEAD_PITCH_PITCH_BITS20TO5 MW(111:96) +#define NVC097_TEXHEAD_PITCH_LOD_ANISO_QUALITY2 MW(112:112) +#define NVC097_TEXHEAD_PITCH_LOD_ANISO_QUALITY MW(113:113) +#define NVC097_TEXHEAD_PITCH_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVC097_TEXHEAD_PITCH_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVC097_TEXHEAD_PITCH_LOD_ISO_QUALITY MW(114:114) +#define NVC097_TEXHEAD_PITCH_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVC097_TEXHEAD_PITCH_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVC097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVC097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVC097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVC097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVC097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVC097_TEXHEAD_PITCH_ANISO_SPREAD_SCALE MW(121:117) +#define NVC097_TEXHEAD_PITCH_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVC097_TEXHEAD_PITCH_DEPTH_TEXTURE MW(123:123) +#define NVC097_TEXHEAD_PITCH_MAX_MIP_LEVEL MW(127:124) +#define NVC097_TEXHEAD_PITCH_WIDTH_MINUS_ONE MW(144:128) +#define NVC097_TEXHEAD_PITCH_PITCH_BIT21 MW(145:145) +#define NVC097_TEXHEAD_PITCH_HEIGHT_MINUS_ONE_BIT16 MW(146:146) +#define NVC097_TEXHEAD_PITCH_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVC097_TEXHEAD_PITCH_S_R_G_B_CONVERSION MW(150:150) +#define NVC097_TEXHEAD_PITCH_TEXTURE_TYPE MW(154:151) +#define NVC097_TEXHEAD_PITCH_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVC097_TEXHEAD_PITCH_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVC097_TEXHEAD_PITCH_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVC097_TEXHEAD_PITCH_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVC097_TEXHEAD_PITCH_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVC097_TEXHEAD_PITCH_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVC097_TEXHEAD_PITCH_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVC097_TEXHEAD_PITCH_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVC097_TEXHEAD_PITCH_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVC097_TEXHEAD_PITCH_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVC097_TEXHEAD_PITCH_SECTOR_PROMOTION MW(156:155) +#define NVC097_TEXHEAD_PITCH_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVC097_TEXHEAD_PITCH_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVC097_TEXHEAD_PITCH_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVC097_TEXHEAD_PITCH_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVC097_TEXHEAD_PITCH_BORDER_SIZE MW(159:157) +#define NVC097_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVC097_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVC097_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVC097_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVC097_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVC097_TEXHEAD_PITCH_HEIGHT_MINUS_ONE MW(175:160) +#define NVC097_TEXHEAD_PITCH_DEPTH_MINUS_ONE MW(189:176) +#define NVC097_TEXHEAD_PITCH_RESERVED5A MW(190:190) +#define NVC097_TEXHEAD_PITCH_NORMALIZED_COORDS MW(191:191) +#define NVC097_TEXHEAD_PITCH_RESERVED6Y MW(192:192) +#define NVC097_TEXHEAD_PITCH_TRILIN_OPT MW(197:193) +#define NVC097_TEXHEAD_PITCH_MIP_LOD_BIAS MW(210:198) +#define NVC097_TEXHEAD_PITCH_ANISO_BIAS MW(214:211) +#define NVC097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVC097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVC097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVC097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVC097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVC097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVC097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVC097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVC097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVC097_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVC097_TEXHEAD_PITCH_MAX_ANISOTROPY MW(221:219) +#define NVC097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVC097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVC097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVC097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVC097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVC097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVC097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVC097_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVC097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVC097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVC097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVC097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVC097_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVC097_TEXHEAD_PITCH_RES_VIEW_MIN_MIP_LEVEL MW(227:224) +#define NVC097_TEXHEAD_PITCH_RES_VIEW_MAX_MIP_LEVEL MW(231:228) +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT MW(235:232) +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVC097_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVC097_TEXHEAD_PITCH_MIN_LOD_CLAMP MW(247:236) +#define NVC097_TEXHEAD_PITCH_RESERVED7Y MW(255:248) + + +/* +** Texture Header State Pitch Color Key + */ + +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS MW(6:0) +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32 0x0000000f +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R16 0x0000001b +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R8 0x0000001d +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R1 0x0000001f +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_EAC 0x00000019 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_Z16 0x0000003a +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVC097_TEXHEAD_PITCHCK_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVC097_TEXHEAD_PITCHCK_R_DATA_TYPE MW(9:7) +#define NVC097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_G_DATA_TYPE MW(12:10) +#define NVC097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_B_DATA_TYPE MW(15:13) +#define NVC097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_A_DATA_TYPE MW(18:16) +#define NVC097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVC097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVC097_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_X_SOURCE MW(21:19) +#define NVC097_TEXHEAD_PITCHCK_X_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_X_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_X_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_X_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_X_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_PITCHCK_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_PITCHCK_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_Y_SOURCE MW(24:22) +#define NVC097_TEXHEAD_PITCHCK_Y_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_Y_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_Y_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_Y_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_Y_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_PITCHCK_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_PITCHCK_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_Z_SOURCE MW(27:25) +#define NVC097_TEXHEAD_PITCHCK_Z_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_Z_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_Z_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_Z_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_Z_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_PITCHCK_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_PITCHCK_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_W_SOURCE MW(30:28) +#define NVC097_TEXHEAD_PITCHCK_W_SOURCE_IN_ZERO 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_W_SOURCE_IN_R 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_W_SOURCE_IN_G 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_W_SOURCE_IN_B 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_W_SOURCE_IN_A 0x00000005 +#define NVC097_TEXHEAD_PITCHCK_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVC097_TEXHEAD_PITCHCK_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_PACK_COMPONENTS MW(31:31) +#define NVC097_TEXHEAD_PITCHCK_RESERVED1A MW(36:32) +#define NVC097_TEXHEAD_PITCHCK_ADDRESS_BITS31TO5 MW(63:37) +#define NVC097_TEXHEAD_PITCHCK_ADDRESS_BITS48TO32 MW(80:64) +#define NVC097_TEXHEAD_PITCHCK_RESERVED_ADDRESS MW(84:81) +#define NVC097_TEXHEAD_PITCHCK_HEADER_VERSION MW(87:85) +#define NVC097_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_RESERVED_HEADER_VERSION MW(88:88) +#define NVC097_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVC097_TEXHEAD_PITCHCK_RESERVED2A MW(95:93) +#define NVC097_TEXHEAD_PITCHCK_PITCH_BITS20TO5 MW(111:96) +#define NVC097_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY2 MW(112:112) +#define NVC097_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY MW(113:113) +#define NVC097_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_LOD_ISO_QUALITY MW(114:114) +#define NVC097_TEXHEAD_PITCHCK_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVC097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_ANISO_SPREAD_SCALE MW(121:117) +#define NVC097_TEXHEAD_PITCHCK_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVC097_TEXHEAD_PITCHCK_DEPTH_TEXTURE MW(123:123) +#define NVC097_TEXHEAD_PITCHCK_MAX_MIP_LEVEL MW(127:124) +#define NVC097_TEXHEAD_PITCHCK_WIDTH_MINUS_ONE MW(144:128) +#define NVC097_TEXHEAD_PITCHCK_PITCH_BIT21 MW(145:145) +#define NVC097_TEXHEAD_PITCHCK_HEIGHT_MINUS_ONE_BIT16 MW(146:146) +#define NVC097_TEXHEAD_PITCHCK_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVC097_TEXHEAD_PITCHCK_S_R_G_B_CONVERSION MW(150:150) +#define NVC097_TEXHEAD_PITCHCK_TEXTURE_TYPE MW(154:151) +#define NVC097_TEXHEAD_PITCHCK_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVC097_TEXHEAD_PITCHCK_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVC097_TEXHEAD_PITCHCK_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVC097_TEXHEAD_PITCHCK_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVC097_TEXHEAD_PITCHCK_SECTOR_PROMOTION MW(156:155) +#define NVC097_TEXHEAD_PITCHCK_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_BORDER_SIZE MW(159:157) +#define NVC097_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_HEIGHT_MINUS_ONE MW(175:160) +#define NVC097_TEXHEAD_PITCHCK_DEPTH_MINUS_ONE MW(189:176) +#define NVC097_TEXHEAD_PITCHCK_RESERVED5A MW(190:190) +#define NVC097_TEXHEAD_PITCHCK_NORMALIZED_COORDS MW(191:191) +#define NVC097_TEXHEAD_PITCHCK_COLOR_KEY_OP MW(192:192) +#define NVC097_TEXHEAD_PITCHCK_TRILIN_OPT MW(197:193) +#define NVC097_TEXHEAD_PITCHCK_MIP_LOD_BIAS MW(210:198) +#define NVC097_TEXHEAD_PITCHCK_ANISO_BIAS MW(214:211) +#define NVC097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVC097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVC097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_MAX_ANISOTROPY MW(221:219) +#define NVC097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVC097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVC097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVC097_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVC097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVC097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVC097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVC097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVC097_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVC097_TEXHEAD_PITCHCK_COLOR_KEY_VALUE MW(255:224) + + +/* +** Texture Sampler State + */ + +#define NVC097_TEXSAMP0_ADDRESS_U 2:0 +#define NVC097_TEXSAMP0_ADDRESS_U_WRAP 0x00000000 +#define NVC097_TEXSAMP0_ADDRESS_U_MIRROR 0x00000001 +#define NVC097_TEXSAMP0_ADDRESS_U_CLAMP_TO_EDGE 0x00000002 +#define NVC097_TEXSAMP0_ADDRESS_U_BORDER 0x00000003 +#define NVC097_TEXSAMP0_ADDRESS_U_CLAMP_OGL 0x00000004 +#define NVC097_TEXSAMP0_ADDRESS_U_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005 +#define NVC097_TEXSAMP0_ADDRESS_U_MIRROR_ONCE_BORDER 0x00000006 +#define NVC097_TEXSAMP0_ADDRESS_U_MIRROR_ONCE_CLAMP_OGL 0x00000007 +#define NVC097_TEXSAMP0_ADDRESS_V 5:3 +#define NVC097_TEXSAMP0_ADDRESS_V_WRAP 0x00000000 +#define NVC097_TEXSAMP0_ADDRESS_V_MIRROR 0x00000001 +#define NVC097_TEXSAMP0_ADDRESS_V_CLAMP_TO_EDGE 0x00000002 +#define NVC097_TEXSAMP0_ADDRESS_V_BORDER 0x00000003 +#define NVC097_TEXSAMP0_ADDRESS_V_CLAMP_OGL 0x00000004 +#define NVC097_TEXSAMP0_ADDRESS_V_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005 +#define NVC097_TEXSAMP0_ADDRESS_V_MIRROR_ONCE_BORDER 0x00000006 +#define NVC097_TEXSAMP0_ADDRESS_V_MIRROR_ONCE_CLAMP_OGL 0x00000007 +#define NVC097_TEXSAMP0_ADDRESS_P 8:6 +#define NVC097_TEXSAMP0_ADDRESS_P_WRAP 0x00000000 +#define NVC097_TEXSAMP0_ADDRESS_P_MIRROR 0x00000001 +#define NVC097_TEXSAMP0_ADDRESS_P_CLAMP_TO_EDGE 0x00000002 +#define NVC097_TEXSAMP0_ADDRESS_P_BORDER 0x00000003 +#define NVC097_TEXSAMP0_ADDRESS_P_CLAMP_OGL 0x00000004 +#define NVC097_TEXSAMP0_ADDRESS_P_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005 +#define NVC097_TEXSAMP0_ADDRESS_P_MIRROR_ONCE_BORDER 0x00000006 +#define NVC097_TEXSAMP0_ADDRESS_P_MIRROR_ONCE_CLAMP_OGL 0x00000007 +#define NVC097_TEXSAMP0_DEPTH_COMPARE 9:9 +#define NVC097_TEXSAMP0_DEPTH_COMPARE_FUNC 12:10 +#define NVC097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_NEVER 0x00000000 +#define NVC097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_LESS 0x00000001 +#define NVC097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_EQUAL 0x00000002 +#define NVC097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_LEQUAL 0x00000003 +#define NVC097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_GREATER 0x00000004 +#define NVC097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_NOTEQUAL 0x00000005 +#define NVC097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_GEQUAL 0x00000006 +#define NVC097_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_ALWAYS 0x00000007 +#define NVC097_TEXSAMP0_S_R_G_B_CONVERSION 13:13 +#define NVC097_TEXSAMP0_RESERVED0A 16:14 +#define NVC097_TEXSAMP0_RESERVED0B 19:17 +#define NVC097_TEXSAMP0_MAX_ANISOTROPY 22:20 +#define NVC097_TEXSAMP0_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVC097_TEXSAMP0_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVC097_TEXSAMP0_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVC097_TEXSAMP0_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVC097_TEXSAMP0_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVC097_TEXSAMP0_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVC097_TEXSAMP0_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVC097_TEXSAMP0_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVC097_TEXSAMP1_MAG_FILTER 2:0 +#define NVC097_TEXSAMP1_MAG_FILTER_MAG_POINT 0x00000001 +#define NVC097_TEXSAMP1_MAG_FILTER_MAG_LINEAR 0x00000002 +#define NVC097_TEXSAMP1_MAG_FILTER_VCAA_4_TAP 0x00000003 +#define NVC097_TEXSAMP1_MAG_FILTER_VCAA_8_TAP 0x00000004 +#define NVC097_TEXSAMP1_MIN_LOD_CLAMP_BEHAVIOR_FOR_NEAREST_MIP 3:3 +#define NVC097_TEXSAMP1_MIN_LOD_CLAMP_BEHAVIOR_FOR_NEAREST_MIP_INTEGER_AND_FRACTION 0x00000000 +#define NVC097_TEXSAMP1_MIN_LOD_CLAMP_BEHAVIOR_FOR_NEAREST_MIP_INTEGER_ONLY 0x00000001 +#define NVC097_TEXSAMP1_MIN_FILTER 5:4 +#define NVC097_TEXSAMP1_MIN_FILTER_MIN_POINT 0x00000001 +#define NVC097_TEXSAMP1_MIN_FILTER_MIN_LINEAR 0x00000002 +#define NVC097_TEXSAMP1_MIN_FILTER_MIN_ANISO 0x00000003 +#define NVC097_TEXSAMP1_MIP_FILTER 7:6 +#define NVC097_TEXSAMP1_MIP_FILTER_MIP_NONE 0x00000001 +#define NVC097_TEXSAMP1_MIP_FILTER_MIP_POINT 0x00000002 +#define NVC097_TEXSAMP1_MIP_FILTER_MIP_LINEAR 0x00000003 +#define NVC097_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING 9:8 +#define NVC097_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_USE_WRAP 0x00000000 +#define NVC097_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_OVERRIDE_WRAP 0x00000001 +#define NVC097_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_AUTO_SPAN_SEAM 0x00000002 +#define NVC097_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_AUTO_CROSS_SEAM 0x00000003 +#define NVC097_TEXSAMP1_REDUCTION_FILTER 11:10 +#define NVC097_TEXSAMP1_REDUCTION_FILTER_RED_NONE 0x00000000 +#define NVC097_TEXSAMP1_REDUCTION_FILTER_RED_MINIMUM 0x00000001 +#define NVC097_TEXSAMP1_REDUCTION_FILTER_RED_MAXIMUM 0x00000002 +#define NVC097_TEXSAMP1_MIP_LOD_BIAS 24:12 +#define NVC097_TEXSAMP1_FLOAT_COORD_NORMALIZATION 25:25 +#define NVC097_TEXSAMP1_FLOAT_COORD_NORMALIZATION_USE_HEADER_SETTING 0x00000000 +#define NVC097_TEXSAMP1_FLOAT_COORD_NORMALIZATION_FORCE_UNNORMALIZED_COORDS 0x00000001 +#define NVC097_TEXSAMP1_TRILIN_OPT 30:26 +#define NVC097_TEXSAMP2_MIN_LOD_CLAMP 11:0 +#define NVC097_TEXSAMP2_MAX_LOD_CLAMP 23:12 +#define NVC097_TEXSAMP2_S_R_G_B_BORDER_COLOR_R 31:24 +#define NVC097_TEXSAMP3_RESERVED12 11:0 +#define NVC097_TEXSAMP3_S_R_G_B_BORDER_COLOR_G 19:12 +#define NVC097_TEXSAMP3_S_R_G_B_BORDER_COLOR_B 27:20 +#define NVC097_TEXSAMP4_BORDER_COLOR_R 31:0 +#define NVC097_TEXSAMP5_BORDER_COLOR_G 31:0 +#define NVC097_TEXSAMP6_BORDER_COLOR_B 31:0 +#define NVC097_TEXSAMP7_BORDER_COLOR_A 31:0 + + + +#endif // #ifndef __CLC097TEX_H__ diff --git a/src/common/sdk/nvidia/inc/class/clc0b5sw.h b/src/common/sdk/nvidia/inc/class/clc0b5sw.h index c2e45466e..dc5bc4133 100644 --- a/src/common/sdk/nvidia/inc/class/clc0b5sw.h +++ b/src/common/sdk/nvidia/inc/class/clc0b5sw.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,38 +21,34 @@ * DEALINGS IN THE SOFTWARE. */ -#include "nvtypes.h" +#pragma once -#ifndef _clc0b5sw_h_ -#define _clc0b5sw_h_ +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc0b5sw.finn +// -#ifdef __cplusplus -extern "C" { -#endif -/* This file is *not* auto-generated. */ // // Using VERSION_0 will cause the API to interpret // engineType as a CE engine instance. This allows // for backward compatibility with 85B5sw and 90B5sw. // -#define NVC0B5_ALLOCATION_PARAMETERS_VERSION_0 0 +#define NVC0B5_ALLOCATION_PARAMETERS_VERSION_0 0 // // Using VERSION_1 will cause the API to interpret // engineType as an NV2080_ENGINE_TYPE ordinal. // -#define NVC0B5_ALLOCATION_PARAMETERS_VERSION_1 1 +#define NVC0B5_ALLOCATION_PARAMETERS_VERSION_1 1 -typedef struct -{ - NvU32 version; - NvU32 engineType; +#define NVC0B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc0b5U) + +typedef struct NVC0B5_ALLOCATION_PARAMETERS { + NvU32 version; + NvU32 engineType; } NVC0B5_ALLOCATION_PARAMETERS; -#ifdef __cplusplus -}; /* extern "C" */ -#endif -#endif // _clc0b5sw_h_ - diff --git a/src/common/sdk/nvidia/inc/class/clc197.h b/src/common/sdk/nvidia/inc/class/clc197.h index 0c8cce115..b03d73525 100644 --- a/src/common/sdk/nvidia/inc/class/clc197.h +++ b/src/common/sdk/nvidia/inc/class/clc197.h @@ -1,29 +1,4242 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. -#ifndef _clc197_h_ -#define _clc197_h_ + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_pascal_b_h_ +#define _cl_pascal_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl pascal_b */ + +#include "nvtypes.h" #define PASCAL_B 0xC197 -#endif // _clc197_h_ +#define NVC197_SET_OBJECT 0x0000 +#define NVC197_SET_OBJECT_CLASS_ID 15:0 +#define NVC197_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC197_NO_OPERATION 0x0100 +#define NVC197_NO_OPERATION_V 31:0 + +#define NVC197_SET_NOTIFY_A 0x0104 +#define NVC197_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC197_SET_NOTIFY_B 0x0108 +#define NVC197_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC197_NOTIFY 0x010c +#define NVC197_NOTIFY_TYPE 31:0 +#define NVC197_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC197_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC197_WAIT_FOR_IDLE 0x0110 +#define NVC197_WAIT_FOR_IDLE_V 31:0 + +#define NVC197_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVC197_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVC197_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVC197_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVC197_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVC197_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVC197_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVC197_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVC197_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVC197_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVC197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVC197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVC197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVC197_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVC197_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVC197_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVC197_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVC197_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVC197_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC197_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC197_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC197_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC197_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC197_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC197_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC197_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC197_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC197_SEND_GO_IDLE 0x013c +#define NVC197_SEND_GO_IDLE_V 31:0 + +#define NVC197_PM_TRIGGER 0x0140 +#define NVC197_PM_TRIGGER_V 31:0 + +#define NVC197_PM_TRIGGER_WFI 0x0144 +#define NVC197_PM_TRIGGER_WFI_V 31:0 + +#define NVC197_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC197_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC197_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC197_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC197_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC197_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC197_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC197_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC197_LINE_LENGTH_IN 0x0180 +#define NVC197_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC197_LINE_COUNT 0x0184 +#define NVC197_LINE_COUNT_VALUE 31:0 + +#define NVC197_OFFSET_OUT_UPPER 0x0188 +#define NVC197_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVC197_OFFSET_OUT 0x018c +#define NVC197_OFFSET_OUT_VALUE 31:0 + +#define NVC197_PITCH_OUT 0x0190 +#define NVC197_PITCH_OUT_VALUE 31:0 + +#define NVC197_SET_DST_BLOCK_SIZE 0x0194 +#define NVC197_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC197_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC197_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC197_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC197_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC197_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC197_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC197_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC197_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC197_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC197_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC197_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC197_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC197_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC197_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC197_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC197_SET_DST_WIDTH 0x0198 +#define NVC197_SET_DST_WIDTH_V 31:0 + +#define NVC197_SET_DST_HEIGHT 0x019c +#define NVC197_SET_DST_HEIGHT_V 31:0 + +#define NVC197_SET_DST_DEPTH 0x01a0 +#define NVC197_SET_DST_DEPTH_V 31:0 + +#define NVC197_SET_DST_LAYER 0x01a4 +#define NVC197_SET_DST_LAYER_V 31:0 + +#define NVC197_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC197_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC197_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC197_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC197_LAUNCH_DMA 0x01b0 +#define NVC197_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC197_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC197_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC197_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC197_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC197_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC197_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC197_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC197_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC197_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC197_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC197_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC197_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC197_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC197_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC197_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC197_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC197_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC197_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC197_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC197_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC197_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC197_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC197_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC197_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC197_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC197_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC197_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC197_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC197_LOAD_INLINE_DATA 0x01b4 +#define NVC197_LOAD_INLINE_DATA_V 31:0 + +#define NVC197_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC197_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC197_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC197_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC197_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC197_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC197_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC197_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC197_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC197_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC197_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC197_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC197_RUN_DS_NOW 0x0200 +#define NVC197_RUN_DS_NOW_V 31:0 + +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVC197_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVC197_SET_GS_MODE 0x0208 +#define NVC197_SET_GS_MODE_TYPE 0:0 +#define NVC197_SET_GS_MODE_TYPE_ANY 0x00000000 +#define NVC197_SET_GS_MODE_TYPE_FAST_GS 0x00000001 + +#define NVC197_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVC197_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVC197_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVC197_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVC197_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVC197_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVC197_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVC197_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_GS_DM_FIFO 0x0214 +#define NVC197_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVC197_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVC197_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVC197_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVC197_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC197_INVALIDATE_SHADER_CACHES 0x021c +#define NVC197_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC197_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC197_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC197_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC197_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC197_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC197_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC197_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC197_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC197_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC197_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC197_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC197_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC197_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC197_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC197_SET_INSTANCE_COUNT 0x0220 +#define NVC197_SET_INSTANCE_COUNT_V 31:0 + +#define NVC197_SET_POSITION_W_SCALED_OFFSET_ENABLE 0x0224 +#define NVC197_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE 0:0 +#define NVC197_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_GO_IDLE_TIMEOUT 0x022c +#define NVC197_SET_GO_IDLE_TIMEOUT_V 31:0 + +#define NVC197_INCREMENT_SYNC_POINT 0x02c8 +#define NVC197_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVC197_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVC197_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVC197_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVC197_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVC197_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVC197_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVC197_SET_PRIM_CIRCULAR_BUFFER_THROTTLE 0x02d0 +#define NVC197_SET_PRIM_CIRCULAR_BUFFER_THROTTLE_PRIM_AREA 21:0 + +#define NVC197_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVC197_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVC197_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC197_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVC197_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVC197_DECOMPRESS_SURFACE 0x02e0 +#define NVC197_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVC197_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVC197_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVC197_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVC197_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVC197_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVC197_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVC197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVC197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVC197_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVC197_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVC197_SET_ZCULL_SUBREGION 0x02e8 +#define NVC197_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVC197_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVC197_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVC197_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVC197_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVC197_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVC197_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVC197_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVC197_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVC197_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVC197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVC197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVC197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVC197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVC197_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVC197_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVC197_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVC197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVC197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVC197_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVC197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVC197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVC197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVC197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVC197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC197_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVC197_DRAW_ZERO_INDEX 0x0304 +#define NVC197_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVC197_SET_L1_CONFIGURATION 0x0308 +#define NVC197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVC197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC197_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVC197_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVC197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVC197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVC197_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVC197_SET_SPA_VERSION 0x0310 +#define NVC197_SET_SPA_VERSION_MINOR 7:0 +#define NVC197_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC197_SET_IEEE_CLEAN_UPDATE 0x0314 +#define NVC197_SET_IEEE_CLEAN_UPDATE_ENABLE 0:0 +#define NVC197_SET_IEEE_CLEAN_UPDATE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_IEEE_CLEAN_UPDATE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_SNAP_GRID_LINE 0x0318 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC197_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC197_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVC197_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC197_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC197_SET_SNAP_GRID_NON_LINE 0x031c +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC197_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVC197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC197_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC197_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVC197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVC197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVC197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVC197_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVC197_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVC197_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVC197_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVC197_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVC197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVC197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVC197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVC197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVC197_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVC197_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVC197_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVC197_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVC197_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVC197_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVC197_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVC197_SET_TESSELLATION_LOD_V1 0x0330 +#define NVC197_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVC197_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVC197_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVC197_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVC197_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVC197_RESERVED_TG07 0x033c +#define NVC197_RESERVED_TG07_V 0:0 + +#define NVC197_RESERVED_TG08 0x0340 +#define NVC197_RESERVED_TG08_V 0:0 + +#define NVC197_RESERVED_TG09 0x0344 +#define NVC197_RESERVED_TG09_V 0:0 + +#define NVC197_RESERVED_TG10 0x0348 +#define NVC197_RESERVED_TG10_V 0:0 + +#define NVC197_RESERVED_TG11 0x034c +#define NVC197_RESERVED_TG11_V 0:0 + +#define NVC197_RESERVED_TG12 0x0350 +#define NVC197_RESERVED_TG12_V 0:0 + +#define NVC197_RESERVED_TG13 0x0354 +#define NVC197_RESERVED_TG13_V 0:0 + +#define NVC197_RESERVED_TG14 0x0358 +#define NVC197_RESERVED_TG14_V 0:0 + +#define NVC197_RESERVED_TG15 0x035c +#define NVC197_RESERVED_TG15_V 0:0 + +#define NVC197_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVC197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVC197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVC197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVC197_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVC197_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVC197_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVC197_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVC197_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVC197_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVC197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVC197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVC197_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE 8:8 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE 9:9 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC197_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVC197_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVC197_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVC197_SET_RASTER_ENABLE 0x037c +#define NVC197_SET_RASTER_ENABLE_V 0:0 +#define NVC197_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVC197_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVC197_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVC197_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVC197_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVC197_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVC197_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVC197_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVC197_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVC197_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVC197_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVC197_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVC197_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVC197_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVC197_SET_POSITION_W_SCALED_OFFSET_SCALE_A(j) (0x0400+(j)*16) +#define NVC197_SET_POSITION_W_SCALED_OFFSET_SCALE_A_V 31:0 + +#define NVC197_SET_POSITION_W_SCALED_OFFSET_SCALE_B(j) (0x0404+(j)*16) +#define NVC197_SET_POSITION_W_SCALED_OFFSET_SCALE_B_V 31:0 + +#define NVC197_SET_POSITION_W_SCALED_OFFSET_RESERVED_A(j) (0x0408+(j)*16) +#define NVC197_SET_POSITION_W_SCALED_OFFSET_RESERVED_A_V 31:0 + +#define NVC197_SET_POSITION_W_SCALED_OFFSET_RESERVED_B(j) (0x040c+(j)*16) +#define NVC197_SET_POSITION_W_SCALED_OFFSET_RESERVED_B_V 31:0 + +#define NVC197_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVC197_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVC197_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVC197_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVC197_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVC197_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVC197_SET_RASTER_INPUT 0x0740 +#define NVC197_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVC197_SET_STREAM_OUTPUT 0x0744 +#define NVC197_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVC197_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVC197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVC197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_ALPHA_FRACTION 0x074c +#define NVC197_SET_ALPHA_FRACTION_V 7:0 + +#define NVC197_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVC197_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVC197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVC197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVC197_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVC197_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVC197_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC197_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC197_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC197_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVC197_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC197_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC197_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVC197_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVC197_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVC197_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVC197_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVC197_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVC197_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVC197_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC197_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVC197_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC197_SET_ISBE_SAVE_RESTORE_PROGRAM 0x07ac +#define NVC197_SET_ISBE_SAVE_RESTORE_PROGRAM_OFFSET 31:0 + +#define NVC197_SET_STENCIL_ZERO_BANDWIDTH_CLEAR 0x07b0 +#define NVC197_SET_STENCIL_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC197_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVC197_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVC197_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVC197_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVC197_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVC197_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVC197_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVC197_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVC197_SET_CULL_BEFORE_FETCH 0x07dc +#define NVC197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVC197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVC197_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVC197_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVC197_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVC197_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVC197_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVC197_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVC197_SET_ZCULL_STORAGE_A 0x07e8 +#define NVC197_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVC197_SET_ZCULL_STORAGE_B 0x07ec +#define NVC197_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVC197_SET_ZCULL_STORAGE_C 0x07f0 +#define NVC197_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC197_SET_ZCULL_STORAGE_D 0x07f4 +#define NVC197_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC197_SET_ZT_READ_ONLY 0x07f8 +#define NVC197_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVC197_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVC197_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVC197_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVC197_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVC197_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVC197_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVC197_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVC197_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVC197_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVC197_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVC197_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVC197_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVC197_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVC197_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVC197_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVC197_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVC197_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVC197_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVC197_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVC197_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVC197_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVC197_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVC197_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVC197_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVC197_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC197_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC197_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVC197_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC197_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVC197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC197_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVC197_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVC197_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVC197_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVC197_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVC197_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVC197_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVC197_SET_COLOR_TARGET_MARK(j) (0x0824+(j)*64) +#define NVC197_SET_COLOR_TARGET_MARK_IEEE_CLEAN 0:0 +#define NVC197_SET_COLOR_TARGET_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVC197_SET_COLOR_TARGET_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVC197_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVC197_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVC197_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVC197_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVC197_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVC197_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVC197_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVC197_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVC197_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVC197_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVC197_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVC197_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVC197_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVC197_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVC197_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVC197_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVC197_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVC197_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVC197_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC197_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVC197_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVC197_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC197_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVC197_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVC197_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVC197_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVC197_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVC197_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVC197_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVC197_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVC197_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVC197_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVC197_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVC197_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVC197_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVC197_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVC197_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVC197_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVC197_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVC197_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC197_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVC197_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVC197_SET_STATISTICS_COUNTER 0x0d68 +#define NVC197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVC197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVC197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVC197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVC197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVC197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVC197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVC197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVC197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVC197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVC197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVC197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVC197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVC197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVC197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVC197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVC197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 +#define NVC197_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE 16:16 +#define NVC197_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVC197_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC197_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC197_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVC197_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC197_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC197_SET_VERTEX_ARRAY_START 0x0d74 +#define NVC197_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVC197_DRAW_VERTEX_ARRAY 0x0d78 +#define NVC197_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVC197_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVC197_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVC197_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVC197_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVC197_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVC197_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVC197_SET_Z_CLEAR_VALUE 0x0d90 +#define NVC197_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVC197_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC197_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVC197_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVC197_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVC197_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC197_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC197_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVC197_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVC197_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVC197_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVC197_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVC197_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVC197_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVC197_SET_FRONT_POLYGON_MODE 0x0dac +#define NVC197_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVC197_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC197_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC197_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC197_SET_BACK_POLYGON_MODE 0x0db0 +#define NVC197_SET_BACK_POLYGON_MODE_V 31:0 +#define NVC197_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC197_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC197_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC197_SET_POLY_SMOOTH 0x0db4 +#define NVC197_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVC197_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVC197_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_ZT_MARK 0x0db8 +#define NVC197_SET_ZT_MARK_IEEE_CLEAN 0:0 +#define NVC197_SET_ZT_MARK_IEEE_CLEAN_FALSE 0x00000000 +#define NVC197_SET_ZT_MARK_IEEE_CLEAN_TRUE 0x00000001 + +#define NVC197_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVC197_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVC197_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVC197_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVC197_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVC197_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVC197_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVC197_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVC197_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVC197_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVC197_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVC197_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVC197_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVC197_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVC197_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVC197_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVC197_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_PATCH 0x0dcc +#define NVC197_SET_PATCH_SIZE 7:0 + +#define NVC197_SET_ITERATED_BLEND 0x0dd0 +#define NVC197_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVC197_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVC197_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVC197_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVC197_SET_ZCULL_CRITERION 0x0dd8 +#define NVC197_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVC197_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVC197_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVC197_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVC197_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVC197_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVC197_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVC197_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVC197_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVC197_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVC197_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVC197_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVC197_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVC197_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVC197_SET_ZCULL_CRITERION_SREF 23:16 +#define NVC197_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVC197_PIXEL_SHADER_BARRIER 0x0de0 +#define NVC197_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVC197_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVC197_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC197_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVC197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVC197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVC197_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVC197_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVC197_SET_WINDOW_OFFSET_X 0x0df8 +#define NVC197_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVC197_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVC197_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVC197_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVC197_SET_SCISSOR_ENABLE_V 0:0 +#define NVC197_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVC197_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVC197_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVC197_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVC197_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVC197_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVC197_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVC197_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVC197_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0f10 +#define NVC197_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVC197_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVC197_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVC197_SET_VPC_PERF_KNOB 0x0f14 +#define NVC197_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVC197_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVC197_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVC197_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVC197_PM_LOCAL_TRIGGER 0x0f18 +#define NVC197_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVC197_SET_POST_Z_PS_IMASK 0x0f1c +#define NVC197_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVC197_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVC197_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVC197_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVC197_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVC197_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVC197_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVC197_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVC197_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVC197_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVC197_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVC197_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVC197_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVC197_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVC197_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVC197_SET_BACK_STENCIL_MASK 0x0f58 +#define NVC197_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVC197_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVC197_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVC197_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVC197_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVC197_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVC197_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVC197_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVC197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVC197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVC197_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVC197_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVC197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVC197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVC197_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVC197_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVC197_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVC197_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVC197_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVC197_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVC197_SET_SAMPLE_MASK 0x0fa4 +#define NVC197_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVC197_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVC197_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVC197_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVC197_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVC197_SET_CT_MRT_ENABLE 0x0fac +#define NVC197_SET_CT_MRT_ENABLE_V 0:0 +#define NVC197_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVC197_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVC197_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVC197_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVC197_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVC197_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVC197_SET_TIR 0x0fb4 +#define NVC197_SET_TIR_MODE 1:0 +#define NVC197_SET_TIR_MODE_DISABLED 0x00000000 +#define NVC197_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVC197_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVC197_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVC197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVC197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVC197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC197_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVC197_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVC197_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVC197_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVC197_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVC197_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVC197_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVC197_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVC197_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVC197_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVC197_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVC197_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_TIR_MODULATION 0x0fd4 +#define NVC197_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVC197_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVC197_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVC197_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVC197_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVC197_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVC197_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVC197_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVC197_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVC197_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVC197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVC197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVC197_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVC197_SET_ZT_A 0x0fe0 +#define NVC197_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_ZT_B 0x0fe4 +#define NVC197_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_ZT_FORMAT 0x0fe8 +#define NVC197_SET_ZT_FORMAT_V 4:0 +#define NVC197_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVC197_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVC197_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVC197_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVC197_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVC197_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVC197_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVC197_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVC197_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVC197_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVC197_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVC197_SET_ZT_BLOCK_SIZE 0x0fec +#define NVC197_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVC197_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC197_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVC197_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC197_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC197_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC197_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC197_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC197_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC197_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVC197_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC197_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVC197_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVC197_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVC197_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVC197_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC197_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVC197_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVC197_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC197_SET_TILED_CACHE_BUNDLE_CONTROL 0x0ffc +#define NVC197_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT 0:0 +#define NVC197_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT_FALSE 0x00000000 +#define NVC197_SET_TILED_CACHE_BUNDLE_CONTROL_TREAT_HEAVYWEIGHT_AS_LIGHTWEIGHT_TRUE 0x00000001 + +#define NVC197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC197_SET_VIEWPORT_MULTICAST 0x1004 +#define NVC197_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVC197_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVC197_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVC197_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVC197_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVC197_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVC197_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC197_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVC197_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVC197_SET_RESERVED_SW_METHOD00 0x1014 +#define NVC197_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC197_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVC197_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC197_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVC197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVC197_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC197_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVC197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_RESERVED_SW_METHOD01 0x1028 +#define NVC197_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD02 0x102c +#define NVC197_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC197_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVC197_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVC197_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVC197_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVC197_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVC197_SET_SPARE_NOOP01 0x1044 +#define NVC197_SET_SPARE_NOOP01_V 31:0 + +#define NVC197_SET_SPARE_NOOP02 0x1048 +#define NVC197_SET_SPARE_NOOP02_V 31:0 + +#define NVC197_SET_SPARE_NOOP03 0x104c +#define NVC197_SET_SPARE_NOOP03_V 31:0 + +#define NVC197_SET_SPARE_NOOP04 0x1050 +#define NVC197_SET_SPARE_NOOP04_V 31:0 + +#define NVC197_SET_SPARE_NOOP05 0x1054 +#define NVC197_SET_SPARE_NOOP05_V 31:0 + +#define NVC197_SET_SPARE_NOOP06 0x1058 +#define NVC197_SET_SPARE_NOOP06_V 31:0 + +#define NVC197_SET_SPARE_NOOP07 0x105c +#define NVC197_SET_SPARE_NOOP07_V 31:0 + +#define NVC197_SET_SPARE_NOOP08 0x1060 +#define NVC197_SET_SPARE_NOOP08_V 31:0 + +#define NVC197_SET_SPARE_NOOP09 0x1064 +#define NVC197_SET_SPARE_NOOP09_V 31:0 + +#define NVC197_SET_SPARE_NOOP10 0x1068 +#define NVC197_SET_SPARE_NOOP10_V 31:0 + +#define NVC197_SET_SPARE_NOOP11 0x106c +#define NVC197_SET_SPARE_NOOP11_V 31:0 + +#define NVC197_SET_SPARE_NOOP12 0x1070 +#define NVC197_SET_SPARE_NOOP12_V 31:0 + +#define NVC197_SET_SPARE_NOOP13 0x1074 +#define NVC197_SET_SPARE_NOOP13_V 31:0 + +#define NVC197_SET_SPARE_NOOP14 0x1078 +#define NVC197_SET_SPARE_NOOP14_V 31:0 + +#define NVC197_SET_SPARE_NOOP15 0x107c +#define NVC197_SET_SPARE_NOOP15_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVC197_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVC197_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVC197_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD06 0x10bc +#define NVC197_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVC197_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVC197_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVC197_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVC197_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVC197_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVC197_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVC197_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD13 0x10dc +#define NVC197_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC197_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVC197_UNBIND_ALL 0x10f4 +#define NVC197_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVC197_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVC197_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVC197_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVC197_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC197_SET_RESERVED_SW_METHOD14 0x1100 +#define NVC197_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC197_SET_RESERVED_SW_METHOD15 0x1104 +#define NVC197_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC197_NO_OPERATION_DATA_HI 0x110c +#define NVC197_NO_OPERATION_DATA_HI_V 31:0 + +#define NVC197_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVC197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVC197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVC197_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVC197_PM_TRIGGER_END 0x1114 +#define NVC197_PM_TRIGGER_END_V 31:0 + +#define NVC197_SET_VERTEX_ID_BASE 0x1118 +#define NVC197_SET_VERTEX_ID_BASE_V 31:0 + +#define NVC197_SET_STENCIL_COMPRESSION 0x111c +#define NVC197_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVC197_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC197_SET_TIR_CONTROL 0x1130 +#define NVC197_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVC197_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC197_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC197_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVC197_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC197_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC197_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVC197_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVC197_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 + +#define NVC197_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVC197_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVC197_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVC197_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVC197_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVC197_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVC197_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVC197_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVC197_SET_FILL_VIA_TRIANGLE 0x113c +#define NVC197_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVC197_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVC197_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVC197_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVC197_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVC197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVC197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVC197_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVC197_FLUSH_PENDING_WRITES 0x1144 +#define NVC197_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVC197_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVC197_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC197_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC197_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC197_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVC197_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC197_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC197_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVC197_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVC197_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVC197_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVC197_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVC197_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVC197_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVC197_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVC197_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVC197_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVC197_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVC197_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVC197_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVC197_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVC197_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVC197_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC197_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC197_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVC197_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC197_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_SCREEN_STATE_MASK 0x1204 +#define NVC197_SET_SCREEN_STATE_MASK_MASK 3:0 + +#define NVC197_SET_ZT_SPARSE 0x1208 +#define NVC197_SET_ZT_SPARSE_ENABLE 0:0 +#define NVC197_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVC197_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVC197_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVC197_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVC197_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC197_SET_CT_SELECT 0x121c +#define NVC197_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVC197_SET_CT_SELECT_TARGET0 6:4 +#define NVC197_SET_CT_SELECT_TARGET1 9:7 +#define NVC197_SET_CT_SELECT_TARGET2 12:10 +#define NVC197_SET_CT_SELECT_TARGET3 15:13 +#define NVC197_SET_CT_SELECT_TARGET4 18:16 +#define NVC197_SET_CT_SELECT_TARGET5 21:19 +#define NVC197_SET_CT_SELECT_TARGET6 24:22 +#define NVC197_SET_CT_SELECT_TARGET7 27:25 + +#define NVC197_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVC197_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVC197_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVC197_SET_ZT_SIZE_A 0x1228 +#define NVC197_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVC197_SET_ZT_SIZE_B 0x122c +#define NVC197_SET_ZT_SIZE_B_HEIGHT 17:0 + +#define NVC197_SET_ZT_SIZE_C 0x1230 +#define NVC197_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVC197_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVC197_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC197_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVC197_SET_SAMPLER_BINDING 0x1234 +#define NVC197_SET_SAMPLER_BINDING_V 0:0 +#define NVC197_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVC197_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVC197_DRAW_AUTO 0x123c +#define NVC197_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVC197_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVC197_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVC197_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVC197_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVC197_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVC197_SET_BACK_END_COPY_A 0x1264 +#define NVC197_SET_BACK_END_COPY_A_DWORDS 7:0 +#define NVC197_SET_BACK_END_COPY_A_SATURATE32_ENABLE 8:8 +#define NVC197_SET_BACK_END_COPY_A_SATURATE32_ENABLE_FALSE 0x00000000 +#define NVC197_SET_BACK_END_COPY_A_SATURATE32_ENABLE_TRUE 0x00000001 +#define NVC197_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE 12:12 +#define NVC197_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_FALSE 0x00000000 +#define NVC197_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_BACK_END_COPY_B 0x1268 +#define NVC197_SET_BACK_END_COPY_B_SRC_ADDRESS_UPPER 7:0 + +#define NVC197_SET_BACK_END_COPY_C 0x126c +#define NVC197_SET_BACK_END_COPY_C_SRC_ADDRESS_LOWER 31:0 + +#define NVC197_SET_BACK_END_COPY_D 0x1270 +#define NVC197_SET_BACK_END_COPY_D_DEST_ADDRESS_UPPER 7:0 + +#define NVC197_SET_BACK_END_COPY_E 0x1274 +#define NVC197_SET_BACK_END_COPY_E_DEST_ADDRESS_LOWER 31:0 + +#define NVC197_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVC197_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 19:0 + +#define NVC197_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVC197_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVC197_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC197_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVC197_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVC197_CLEAR_ZCULL_REGION 0x12c8 +#define NVC197_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVC197_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVC197_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVC197_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVC197_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC197_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVC197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC197_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVC197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVC197_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVC197_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVC197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVC197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVC197_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVC197_SET_DEPTH_TEST 0x12cc +#define NVC197_SET_DEPTH_TEST_ENABLE 0:0 +#define NVC197_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVC197_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_FILL_MODE 0x12d0 +#define NVC197_SET_FILL_MODE_V 31:0 +#define NVC197_SET_FILL_MODE_V_POINT 0x00000001 +#define NVC197_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVC197_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVC197_SET_SHADE_MODE 0x12d4 +#define NVC197_SET_SHADE_MODE_V 31:0 +#define NVC197_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVC197_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVC197_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVC197_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC197_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVC197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVC197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVC197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVC197_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVC197_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVC197_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVC197_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVC197_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_DEPTH_WRITE 0x12e8 +#define NVC197_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVC197_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_ALPHA_TEST 0x12ec +#define NVC197_SET_ALPHA_TEST_ENABLE 0:0 +#define NVC197_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVC197_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVC197_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVC197_DRAW_INLINE_INDEX4X8 0x1304 +#define NVC197_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVC197_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVC197_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVC197_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVC197_D3D_SET_CULL_MODE 0x1308 +#define NVC197_D3D_SET_CULL_MODE_V 31:0 +#define NVC197_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVC197_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVC197_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVC197_SET_DEPTH_FUNC 0x130c +#define NVC197_SET_DEPTH_FUNC_V 31:0 +#define NVC197_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVC197_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVC197_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC197_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC197_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVC197_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC197_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC197_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC197_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVC197_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVC197_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC197_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC197_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVC197_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC197_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC197_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC197_SET_ALPHA_REF 0x1310 +#define NVC197_SET_ALPHA_REF_V 31:0 + +#define NVC197_SET_ALPHA_FUNC 0x1314 +#define NVC197_SET_ALPHA_FUNC_V 31:0 +#define NVC197_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVC197_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVC197_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC197_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC197_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVC197_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC197_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC197_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC197_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVC197_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVC197_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC197_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC197_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVC197_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC197_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC197_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC197_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVC197_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVC197_SET_BLEND_CONST_RED 0x131c +#define NVC197_SET_BLEND_CONST_RED_V 31:0 + +#define NVC197_SET_BLEND_CONST_GREEN 0x1320 +#define NVC197_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVC197_SET_BLEND_CONST_BLUE 0x1324 +#define NVC197_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVC197_SET_BLEND_CONST_ALPHA 0x1328 +#define NVC197_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVC197_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC197_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC197_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC197_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC197_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC197_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC197_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVC197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC197_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_BLEND_COLOR_OP 0x1340 +#define NVC197_SET_BLEND_COLOR_OP_V 31:0 +#define NVC197_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC197_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC197_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC197_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC197_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC197_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC197_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC197_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC197_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC197_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC197_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC197_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC197_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC197_SET_BLEND_ALPHA_OP 0x134c +#define NVC197_SET_BLEND_ALPHA_OP_V 31:0 +#define NVC197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC197_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC197_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC197_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC197_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC197_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC197_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC197_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC197_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC197_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC197_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVC197_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVC197_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVC197_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC197_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC197_SET_SINGLE_ROP_CONTROL 0x135c +#define NVC197_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVC197_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_BLEND(i) (0x1360+(i)*4) +#define NVC197_SET_BLEND_ENABLE 0:0 +#define NVC197_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVC197_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_STENCIL_TEST 0x1380 +#define NVC197_SET_STENCIL_TEST_ENABLE 0:0 +#define NVC197_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC197_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_STENCIL_OP_FAIL 0x1384 +#define NVC197_SET_STENCIL_OP_FAIL_V 31:0 +#define NVC197_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC197_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC197_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC197_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC197_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC197_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC197_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC197_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC197_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC197_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC197_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC197_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC197_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC197_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC197_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC197_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC197_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVC197_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC197_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC197_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC197_SET_STENCIL_OP_ZPASS 0x138c +#define NVC197_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVC197_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC197_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC197_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC197_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC197_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC197_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC197_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC197_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC197_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC197_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC197_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC197_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC197_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC197_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC197_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC197_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC197_SET_STENCIL_FUNC 0x1390 +#define NVC197_SET_STENCIL_FUNC_V 31:0 +#define NVC197_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC197_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC197_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC197_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC197_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC197_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC197_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC197_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC197_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC197_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC197_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC197_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC197_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC197_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC197_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC197_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC197_SET_STENCIL_FUNC_REF 0x1394 +#define NVC197_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVC197_SET_STENCIL_FUNC_MASK 0x1398 +#define NVC197_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVC197_SET_STENCIL_MASK 0x139c +#define NVC197_SET_STENCIL_MASK_V 7:0 + +#define NVC197_SET_DRAW_AUTO_START 0x13a4 +#define NVC197_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVC197_SET_PS_SATURATE 0x13a8 +#define NVC197_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVC197_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVC197_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC197_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVC197_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVC197_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC197_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVC197_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVC197_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC197_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVC197_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVC197_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC197_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVC197_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVC197_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC197_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVC197_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVC197_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC197_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVC197_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVC197_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC197_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVC197_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVC197_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC197_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVC197_SET_WINDOW_ORIGIN 0x13ac +#define NVC197_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVC197_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVC197_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVC197_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVC197_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVC197_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVC197_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVC197_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC197_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVC197_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC197_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVC197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVC197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_ALPHA_HYSTERESIS 0x1420 +#define NVC197_SET_ALPHA_HYSTERESIS_ROUNDS_OF_ALPHA 7:0 + +#define NVC197_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC197_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC197_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC197_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC197_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVC197_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVC197_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVC197_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVC197_SET_PS_WARP_WATERMARKS 0x1450 +#define NVC197_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVC197_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVC197_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVC197_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVC197_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC197_STORE_ZCULL 0x1464 +#define NVC197_STORE_ZCULL_V 0:0 + +#define NVC197_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVC197_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVC197_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVC197_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVC197_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVC197_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVC197_LOAD_ZCULL 0x1500 +#define NVC197_LOAD_ZCULL_V 0:0 + +#define NVC197_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVC197_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVC197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVC197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC197_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC197_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVC197_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC197_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC197_SET_USER_CLIP_ENABLE 0x1510 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVC197_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVC197_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVC197_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVC197_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_POINT_SIZE 0x1518 +#define NVC197_SET_POINT_SIZE_V 31:0 + +#define NVC197_SET_ZCULL_STATS 0x151c +#define NVC197_SET_ZCULL_STATS_ENABLE 0:0 +#define NVC197_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_POINT_SPRITE 0x1520 +#define NVC197_SET_POINT_SPRITE_ENABLE 0:0 +#define NVC197_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC197_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC197_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC197_CLEAR_REPORT_VALUE 0x1530 +#define NVC197_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVC197_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVC197_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVC197_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVC197_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVC197_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVC197_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC197_CLEAR_REPORT_VALUE_TYPE_SCG_CLOCKS 0x00000009 + +#define NVC197_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVC197_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVC197_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVC197_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVC197_SET_ZT_SELECT 0x1538 +#define NVC197_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVC197_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVC197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVC197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVC197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVC197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVC197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVC197_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVC197_SET_RENDER_ENABLE_A 0x1550 +#define NVC197_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_RENDER_ENABLE_B 0x1554 +#define NVC197_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_RENDER_ENABLE_C 0x1558 +#define NVC197_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC197_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC197_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC197_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC197_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC197_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC197_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC197_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC197_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC197_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC197_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVC197_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVC197_SET_ANTI_ALIASED_LINE 0x1570 +#define NVC197_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVC197_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC197_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC197_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_TEX_HEADER_POOL_C 0x157c +#define NVC197_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC197_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVC197_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVC197_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVC197_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVC197_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC197_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC197_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC197_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC197_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC197_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC197_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVC197_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVC197_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC197_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC197_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC197_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC197_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC197_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC197_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC197_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC197_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC197_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC197_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC197_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC197_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC197_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC197_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC197_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC197_SET_SRGB_WRITE 0x15b8 +#define NVC197_SET_SRGB_WRITE_ENABLE 0:0 +#define NVC197_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_DEPTH_BIAS 0x15bc +#define NVC197_SET_DEPTH_BIAS_V 31:0 + +#define NVC197_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVC197_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVC197_SET_RT_LAYER 0x15cc +#define NVC197_SET_RT_LAYER_V 15:0 +#define NVC197_SET_RT_LAYER_CONTROL 16:16 +#define NVC197_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVC197_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVC197_SET_ANTI_ALIAS 0x15d0 +#define NVC197_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVC197_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVC197_SET_EDGE_FLAG 0x15e4 +#define NVC197_SET_EDGE_FLAG_V 0:0 +#define NVC197_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVC197_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVC197_DRAW_INLINE_INDEX 0x15e8 +#define NVC197_DRAW_INLINE_INDEX_V 31:0 + +#define NVC197_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVC197_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVC197_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVC197_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVC197_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVC197_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVC197_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVC197_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVC197_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVC197_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVC197_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVC197_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVC197_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVC197_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVC197_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVC197_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVC197_SET_POINT_SPRITE_SELECT 0x1604 +#define NVC197_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVC197_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVC197_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVC197_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVC197_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVC197_SET_PROGRAM_REGION_A 0x1608 +#define NVC197_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVC197_SET_PROGRAM_REGION_B 0x160c +#define NVC197_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVC197_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVC197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVC197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVC197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVC197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVC197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVC197_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVC197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVC197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVC197_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVC197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVC197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVC197_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVC197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVC197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVC197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVC197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVC197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVC197_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVC197_END 0x1614 +#define NVC197_END_V 0:0 + +#define NVC197_BEGIN 0x1618 +#define NVC197_BEGIN_OP 15:0 +#define NVC197_BEGIN_OP_POINTS 0x00000000 +#define NVC197_BEGIN_OP_LINES 0x00000001 +#define NVC197_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVC197_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVC197_BEGIN_OP_TRIANGLES 0x00000004 +#define NVC197_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVC197_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVC197_BEGIN_OP_QUADS 0x00000007 +#define NVC197_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVC197_BEGIN_OP_POLYGON 0x00000009 +#define NVC197_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVC197_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVC197_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_BEGIN_OP_PATCH 0x0000000E +#define NVC197_BEGIN_PRIMITIVE_ID 24:24 +#define NVC197_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC197_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC197_BEGIN_INSTANCE_ID 27:26 +#define NVC197_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVC197_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC197_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC197_BEGIN_SPLIT_MODE 30:29 +#define NVC197_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC197_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC197_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC197_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC197_BEGIN_INSTANCE_ITERATE_ENABLE 31:31 +#define NVC197_BEGIN_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC197_BEGIN_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_VERTEX_ID_COPY 0x161c +#define NVC197_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVC197_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVC197_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVC197_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVC197_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVC197_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVC197_LOAD_PRIMITIVE_ID 0x1624 +#define NVC197_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVC197_SET_SHADER_BASED_CULL 0x162c +#define NVC197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVC197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVC197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVC197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVC197_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_CLASS_VERSION 0x1638 +#define NVC197_SET_CLASS_VERSION_CURRENT 15:0 +#define NVC197_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC197_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVC197_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVC197_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVC197_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVC197_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVC197_SET_DA_OUTPUT 0x164c +#define NVC197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVC197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVC197_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVC197_SET_ANTI_ALIASED_POINT 0x1658 +#define NVC197_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVC197_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_POINT_CENTER_MODE 0x165c +#define NVC197_SET_POINT_CENTER_MODE_V 31:0 +#define NVC197_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVC197_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVC197_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVC197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVC197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVC197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVC197_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVC197_SET_LINE_STIPPLE 0x166c +#define NVC197_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVC197_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVC197_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVC197_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVC197_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVC197_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVC197_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVC197_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVC197_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVC197_SET_PROVOKING_VERTEX 0x1684 +#define NVC197_SET_PROVOKING_VERTEX_V 0:0 +#define NVC197_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVC197_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVC197_SET_TWO_SIDED_LIGHT 0x1688 +#define NVC197_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVC197_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_POLYGON_STIPPLE 0x168c +#define NVC197_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVC197_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_SHADER_CONTROL 0x1690 +#define NVC197_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVC197_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVC197_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVC197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVC197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC197_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVC197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC197_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVC197_CHECK_CLASS_VERSION 0x16a0 +#define NVC197_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVC197_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC197_SET_SPH_VERSION 0x16a4 +#define NVC197_SET_SPH_VERSION_CURRENT 15:0 +#define NVC197_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC197_CHECK_SPH_VERSION 0x16a8 +#define NVC197_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVC197_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC197_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVC197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVC197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVC197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVC197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVC197_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVC197_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVC197_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVC197_SET_AAM_VERSION 0x1790 +#define NVC197_SET_AAM_VERSION_CURRENT 15:0 +#define NVC197_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC197_CHECK_AAM_VERSION 0x1794 +#define NVC197_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVC197_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC197_SET_ZT_LAYER 0x179c +#define NVC197_SET_ZT_LAYER_OFFSET 15:0 + +#define NVC197_SET_INDEX_BUFFER_A 0x17c8 +#define NVC197_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVC197_SET_INDEX_BUFFER_B 0x17cc +#define NVC197_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVC197_SET_INDEX_BUFFER_C 0x17d0 +#define NVC197_SET_INDEX_BUFFER_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC197_SET_INDEX_BUFFER_D 0x17d4 +#define NVC197_SET_INDEX_BUFFER_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC197_SET_INDEX_BUFFER_E 0x17d8 +#define NVC197_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVC197_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVC197_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVC197_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVC197_SET_INDEX_BUFFER_F 0x17dc +#define NVC197_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVC197_DRAW_INDEX_BUFFER 0x17e0 +#define NVC197_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC197_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVC197_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVC197_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVC197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVC197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVC197_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVC197_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVC197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVC197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVC197_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVC197_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVC197_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVC197_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVC197_OGL_SET_CULL 0x1918 +#define NVC197_OGL_SET_CULL_ENABLE 0:0 +#define NVC197_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVC197_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVC197_OGL_SET_FRONT_FACE 0x191c +#define NVC197_OGL_SET_FRONT_FACE_V 31:0 +#define NVC197_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVC197_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVC197_OGL_SET_CULL_FACE 0x1920 +#define NVC197_OGL_SET_CULL_FACE_V 31:0 +#define NVC197_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVC197_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVC197_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVC197_SET_VIEWPORT_PIXEL 0x1924 +#define NVC197_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVC197_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVC197_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVC197_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVC197_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVC197_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVC197_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVC197_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVC197_SET_USER_CLIP_OP 0x1940 +#define NVC197_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVC197_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVC197_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVC197_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVC197_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVC197_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVC197_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVC197_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVC197_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVC197_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVC197_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVC197_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVC197_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVC197_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVC197_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVC197_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVC197_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVC197_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVC197_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVC197_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVC197_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVC197_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVC197_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVC197_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVC197_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC197_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC197_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC197_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC197_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC197_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVC197_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVC197_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVC197_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVC197_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVC197_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVC197_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVC197_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVC197_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVC197_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVC197_INVALIDATE_ZCULL 0x1958 +#define NVC197_INVALIDATE_ZCULL_V 31:0 +#define NVC197_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVC197_SET_ZCULL 0x1968 +#define NVC197_SET_ZCULL_Z_ENABLE 0:0 +#define NVC197_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVC197_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_ZCULL_BOUNDS 0x196c +#define NVC197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVC197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVC197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVC197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC197_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVC197_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVC197_ZCULL_SYNC 0x1978 +#define NVC197_ZCULL_SYNC_V 31:0 + +#define NVC197_SET_CLIP_ID_TEST 0x197c +#define NVC197_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVC197_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVC197_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVC197_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVC197_SET_CLIP_ID 0x1984 +#define NVC197_SET_CLIP_ID_V 31:0 + +#define NVC197_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVC197_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVC197_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVC197_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVC197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVC197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVC197_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVC197_SET_LOGIC_OP 0x19c4 +#define NVC197_SET_LOGIC_OP_ENABLE 0:0 +#define NVC197_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVC197_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_LOGIC_OP_FUNC 0x19c8 +#define NVC197_SET_LOGIC_OP_FUNC_V 31:0 +#define NVC197_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVC197_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVC197_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVC197_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVC197_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVC197_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVC197_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVC197_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVC197_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVC197_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVC197_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVC197_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVC197_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVC197_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVC197_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVC197_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVC197_SET_Z_COMPRESSION 0x19cc +#define NVC197_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVC197_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC197_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC197_CLEAR_SURFACE 0x19d0 +#define NVC197_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVC197_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC197_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC197_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVC197_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC197_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC197_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVC197_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVC197_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVC197_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVC197_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVC197_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVC197_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVC197_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVC197_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVC197_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVC197_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVC197_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVC197_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVC197_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVC197_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVC197_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVC197_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVC197_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVC197_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC197_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVC197_SET_CT_WRITE_R_ENABLE 0:0 +#define NVC197_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVC197_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVC197_SET_CT_WRITE_G_ENABLE 4:4 +#define NVC197_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVC197_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVC197_SET_CT_WRITE_B_ENABLE 8:8 +#define NVC197_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVC197_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVC197_SET_CT_WRITE_A_ENABLE 12:12 +#define NVC197_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVC197_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVC197_PIPE_NOP 0x1a2c +#define NVC197_PIPE_NOP_V 31:0 + +#define NVC197_SET_SPARE00 0x1a30 +#define NVC197_SET_SPARE00_V 31:0 + +#define NVC197_SET_SPARE01 0x1a34 +#define NVC197_SET_SPARE01_V 31:0 + +#define NVC197_SET_SPARE02 0x1a38 +#define NVC197_SET_SPARE02_V 31:0 + +#define NVC197_SET_SPARE03 0x1a3c +#define NVC197_SET_SPARE03_V 31:0 + +#define NVC197_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC197_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC197_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC197_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC197_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC197_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC197_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVC197_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC197_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVC197_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVC197_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC197_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC197_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVC197_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_SCG_CLOCKS 0x00000008 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVC197_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVC197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC197_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVC197_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVC197_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVC197_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVC197_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVC197_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVC197_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVC197_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVC197_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVC197_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVC197_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVC197_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC197_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVC197_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC197_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVC197_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC197_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVC197_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVC197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVC197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC197_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC197_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC197_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC197_SET_VERTEX_STREAM_LIMIT_A_A(j) (0x1f00+(j)*8) +#define NVC197_SET_VERTEX_STREAM_LIMIT_A_A_UPPER 7:0 + +#define NVC197_SET_VERTEX_STREAM_LIMIT_A_B(j) (0x1f04+(j)*8) +#define NVC197_SET_VERTEX_STREAM_LIMIT_A_B_LOWER 31:0 + +#define NVC197_SET_VERTEX_STREAM_LIMIT_B_A(j) (0x1f80+(j)*8) +#define NVC197_SET_VERTEX_STREAM_LIMIT_B_A_UPPER 7:0 + +#define NVC197_SET_VERTEX_STREAM_LIMIT_B_B(j) (0x1f84+(j)*8) +#define NVC197_SET_VERTEX_STREAM_LIMIT_B_B_LOWER 31:0 + +#define NVC197_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVC197_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVC197_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVC197_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVC197_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVC197_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVC197_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVC197_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVC197_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVC197_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVC197_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVC197_SET_PIPELINE_PROGRAM(j) (0x2004+(j)*64) +#define NVC197_SET_PIPELINE_PROGRAM_OFFSET 31:0 + +#define NVC197_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVC197_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVC197_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVC197_SET_PIPELINE_REGISTER_COUNT_V 7:0 + +#define NVC197_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVC197_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVC197_SET_PIPELINE_RESERVED_B(j) (0x2014+(j)*64) +#define NVC197_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVC197_SET_PIPELINE_RESERVED_C(j) (0x2018+(j)*64) +#define NVC197_SET_PIPELINE_RESERVED_C_V 0:0 + +#define NVC197_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVC197_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVC197_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVC197_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVC197_SET_FALCON00 0x2300 +#define NVC197_SET_FALCON00_V 31:0 + +#define NVC197_SET_FALCON01 0x2304 +#define NVC197_SET_FALCON01_V 31:0 + +#define NVC197_SET_FALCON02 0x2308 +#define NVC197_SET_FALCON02_V 31:0 + +#define NVC197_SET_FALCON03 0x230c +#define NVC197_SET_FALCON03_V 31:0 + +#define NVC197_SET_FALCON04 0x2310 +#define NVC197_SET_FALCON04_V 31:0 + +#define NVC197_SET_FALCON05 0x2314 +#define NVC197_SET_FALCON05_V 31:0 + +#define NVC197_SET_FALCON06 0x2318 +#define NVC197_SET_FALCON06_V 31:0 + +#define NVC197_SET_FALCON07 0x231c +#define NVC197_SET_FALCON07_V 31:0 + +#define NVC197_SET_FALCON08 0x2320 +#define NVC197_SET_FALCON08_V 31:0 + +#define NVC197_SET_FALCON09 0x2324 +#define NVC197_SET_FALCON09_V 31:0 + +#define NVC197_SET_FALCON10 0x2328 +#define NVC197_SET_FALCON10_V 31:0 + +#define NVC197_SET_FALCON11 0x232c +#define NVC197_SET_FALCON11_V 31:0 + +#define NVC197_SET_FALCON12 0x2330 +#define NVC197_SET_FALCON12_V 31:0 + +#define NVC197_SET_FALCON13 0x2334 +#define NVC197_SET_FALCON13_V 31:0 + +#define NVC197_SET_FALCON14 0x2338 +#define NVC197_SET_FALCON14_V 31:0 + +#define NVC197_SET_FALCON15 0x233c +#define NVC197_SET_FALCON15_V 31:0 + +#define NVC197_SET_FALCON16 0x2340 +#define NVC197_SET_FALCON16_V 31:0 + +#define NVC197_SET_FALCON17 0x2344 +#define NVC197_SET_FALCON17_V 31:0 + +#define NVC197_SET_FALCON18 0x2348 +#define NVC197_SET_FALCON18_V 31:0 + +#define NVC197_SET_FALCON19 0x234c +#define NVC197_SET_FALCON19_V 31:0 + +#define NVC197_SET_FALCON20 0x2350 +#define NVC197_SET_FALCON20_V 31:0 + +#define NVC197_SET_FALCON21 0x2354 +#define NVC197_SET_FALCON21_V 31:0 + +#define NVC197_SET_FALCON22 0x2358 +#define NVC197_SET_FALCON22_V 31:0 + +#define NVC197_SET_FALCON23 0x235c +#define NVC197_SET_FALCON23_V 31:0 + +#define NVC197_SET_FALCON24 0x2360 +#define NVC197_SET_FALCON24_V 31:0 + +#define NVC197_SET_FALCON25 0x2364 +#define NVC197_SET_FALCON25_V 31:0 + +#define NVC197_SET_FALCON26 0x2368 +#define NVC197_SET_FALCON26_V 31:0 + +#define NVC197_SET_FALCON27 0x236c +#define NVC197_SET_FALCON27_V 31:0 + +#define NVC197_SET_FALCON28 0x2370 +#define NVC197_SET_FALCON28_V 31:0 + +#define NVC197_SET_FALCON29 0x2374 +#define NVC197_SET_FALCON29_V 31:0 + +#define NVC197_SET_FALCON30 0x2378 +#define NVC197_SET_FALCON30_V 31:0 + +#define NVC197_SET_FALCON31 0x237c +#define NVC197_SET_FALCON31_V 31:0 + +#define NVC197_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVC197_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVC197_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVC197_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVC197_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVC197_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVC197_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVC197_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVC197_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVC197_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVC197_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVC197_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVC197_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVC197_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVC197_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVC197_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVC197_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVC197_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVC197_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVC197_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVC197_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC197_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC197_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVC197_SET_COLOR_CLAMP 0x2600 +#define NVC197_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVC197_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVC197_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVC197_SET_BINDLESS_TEXTURE 0x2608 +#define NVC197_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 4:0 + +#define NVC197_SET_TRAP_HANDLER 0x260c +#define NVC197_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVC197_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVC197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVC197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVC197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVC197_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC197_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC197_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC197_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC197_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC197_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC197_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC197_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVC197_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVC197_CALL_MME_MACRO_V 31:0 + +#define NVC197_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVC197_CALL_MME_DATA_V 31:0 + +#endif /* _cl_pascal_b_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/clc1b5sw.h b/src/common/sdk/nvidia/inc/class/clc1b5sw.h index 213119ec8..27af6f205 100644 --- a/src/common/sdk/nvidia/inc/class/clc1b5sw.h +++ b/src/common/sdk/nvidia/inc/class/clc1b5sw.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2016-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,38 +21,34 @@ * DEALINGS IN THE SOFTWARE. */ -#include "nvtypes.h" +#pragma once -#ifndef _clc1b5sw_h_ -#define _clc1b5sw_h_ +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc1b5sw.finn +// -#ifdef __cplusplus -extern "C" { -#endif -/* This file is *not* auto-generated. */ // // Using VERSION_0 will cause the API to interpret // engineType as a CE engine instance. This allows // for backward compatibility with 85B5sw and 90B5sw. // -#define NVC1B5_ALLOCATION_PARAMETERS_VERSION_0 0 +#define NVC1B5_ALLOCATION_PARAMETERS_VERSION_0 0 // // Using VERSION_1 will cause the API to interpret // engineType as an NV2080_ENGINE_TYPE ordinal. // -#define NVC1B5_ALLOCATION_PARAMETERS_VERSION_1 1 +#define NVC1B5_ALLOCATION_PARAMETERS_VERSION_1 1 -typedef struct -{ - NvU32 version; - NvU32 engineType; +#define NVC1B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc1b5U) + +typedef struct NVC1B5_ALLOCATION_PARAMETERS { + NvU32 version; + NvU32 engineType; } NVC1B5_ALLOCATION_PARAMETERS; -#ifdef __cplusplus -}; /* extern "C" */ -#endif -#endif // _clc1b5sw_h_ - diff --git a/src/common/sdk/nvidia/inc/class/clc370.h b/src/common/sdk/nvidia/inc/class/clc370.h index 075f0815e..4f6bf4b44 100644 --- a/src/common/sdk/nvidia/inc/class/clc370.h +++ b/src/common/sdk/nvidia/inc/class/clc370.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -20,36 +20,24 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _clc370_h_ -#define _clc370_h_ +#pragma once -#ifdef __cplusplus -extern "C" { -#endif +#include -#include "nvtypes.h" +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc370.finn +// -#include "class/cl5070.h" +#include "clc370_notification.h" -#define NVC370_DISPLAY (0x0000C370) +#define NVC370_DISPLAY (0xc370U) /* finn: Evaluated from "NVC370_ALLOCATION_PARAMETERS_MESSAGE_ID" */ -/* event values */ -#define NVC370_NOTIFIERS_SW NV5070_NOTIFIERS_SW -#define NVC370_NOTIFIERS_BEGIN NV5070_NOTIFIERS_MAXCOUNT -#define NVC370_NOTIFIERS_VPR NVC370_NOTIFIERS_BEGIN + (0) -#define NVC370_NOTIFIERS_RG_SEM_NOTIFICATION NVC370_NOTIFIERS_VPR + (1) -#define NVC370_NOTIFIERS_WIN_SEM_NOTIFICATION NVC370_NOTIFIERS_RG_SEM_NOTIFICATION + (1) -#define NVC370_NOTIFIERS_MAXCOUNT NVC370_NOTIFIERS_WIN_SEM_NOTIFICATION + (1) +#define NVC370_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc370U) -typedef struct -{ - NvU32 numHeads; // Number of HEADs in this chip/display - NvU32 numSors; // Number of SORs in this chip/display - NvU32 numPiors; // Number of PIORs in this chip/display +typedef struct NVC370_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numPiors; // Number of PIORs in this chip/display } NVC370_ALLOCATION_PARAMETERS; -#ifdef __cplusplus -}; /* extern "C" */ -#endif - -#endif /* _clc370_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/clc370_notification.h b/src/common/sdk/nvidia/inc/class/clc370_notification.h new file mode 100644 index 000000000..e0c886731 --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/clc370_notification.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clc370_notification_h_ +#define _clc370_notification_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "class/cl5070.h" + +/* event values */ +#define NVC370_NOTIFIERS_SW NV5070_NOTIFIERS_SW +#define NVC370_NOTIFIERS_BEGIN NV5070_NOTIFIERS_MAXCOUNT +#define NVC370_NOTIFIERS_VPR NVC370_NOTIFIERS_BEGIN + (0) +#define NVC370_NOTIFIERS_RG_SEM_NOTIFICATION NVC370_NOTIFIERS_VPR + (1) +#define NVC370_NOTIFIERS_WIN_SEM_NOTIFICATION NVC370_NOTIFIERS_RG_SEM_NOTIFICATION + (1) +#define NVC370_NOTIFIERS_MAXCOUNT NVC370_NOTIFIERS_WIN_SEM_NOTIFICATION + (1) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif + +#endif /* _clc370_notification_h_ */ + diff --git a/src/common/sdk/nvidia/inc/class/clc397.h b/src/common/sdk/nvidia/inc/class/clc397.h index 2345ee662..2122c75ca 100644 --- a/src/common/sdk/nvidia/inc/class/clc397.h +++ b/src/common/sdk/nvidia/inc/class/clc397.h @@ -1,29 +1,4219 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. -#ifndef _clc397_h_ -#define _clc397_h_ + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_volta_a_h_ +#define _cl_volta_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl volta_a */ + +#include "nvtypes.h" #define VOLTA_A 0xC397 -#endif // _clc397_h_ +#define NVC397_SET_OBJECT 0x0000 +#define NVC397_SET_OBJECT_CLASS_ID 15:0 +#define NVC397_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC397_NO_OPERATION 0x0100 +#define NVC397_NO_OPERATION_V 31:0 + +#define NVC397_SET_NOTIFY_A 0x0104 +#define NVC397_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC397_SET_NOTIFY_B 0x0108 +#define NVC397_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC397_NOTIFY 0x010c +#define NVC397_NOTIFY_TYPE 31:0 +#define NVC397_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC397_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC397_WAIT_FOR_IDLE 0x0110 +#define NVC397_WAIT_FOR_IDLE_V 31:0 + +#define NVC397_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVC397_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVC397_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVC397_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVC397_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVC397_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVC397_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVC397_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVC397_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVC397_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVC397_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVC397_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVC397_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVC397_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVC397_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVC397_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVC397_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVC397_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVC397_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC397_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC397_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC397_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC397_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC397_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC397_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC397_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC397_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC397_SEND_GO_IDLE 0x013c +#define NVC397_SEND_GO_IDLE_V 31:0 + +#define NVC397_PM_TRIGGER 0x0140 +#define NVC397_PM_TRIGGER_V 31:0 + +#define NVC397_PM_TRIGGER_WFI 0x0144 +#define NVC397_PM_TRIGGER_WFI_V 31:0 + +#define NVC397_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC397_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC397_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC397_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC397_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC397_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC397_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC397_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC397_LINE_LENGTH_IN 0x0180 +#define NVC397_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC397_LINE_COUNT 0x0184 +#define NVC397_LINE_COUNT_VALUE 31:0 + +#define NVC397_OFFSET_OUT_UPPER 0x0188 +#define NVC397_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVC397_OFFSET_OUT 0x018c +#define NVC397_OFFSET_OUT_VALUE 31:0 + +#define NVC397_PITCH_OUT 0x0190 +#define NVC397_PITCH_OUT_VALUE 31:0 + +#define NVC397_SET_DST_BLOCK_SIZE 0x0194 +#define NVC397_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC397_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC397_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC397_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC397_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC397_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC397_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC397_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC397_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC397_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC397_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC397_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC397_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC397_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC397_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC397_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC397_SET_DST_WIDTH 0x0198 +#define NVC397_SET_DST_WIDTH_V 31:0 + +#define NVC397_SET_DST_HEIGHT 0x019c +#define NVC397_SET_DST_HEIGHT_V 31:0 + +#define NVC397_SET_DST_DEPTH 0x01a0 +#define NVC397_SET_DST_DEPTH_V 31:0 + +#define NVC397_SET_DST_LAYER 0x01a4 +#define NVC397_SET_DST_LAYER_V 31:0 + +#define NVC397_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC397_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC397_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC397_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC397_LAUNCH_DMA 0x01b0 +#define NVC397_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC397_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC397_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC397_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC397_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC397_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC397_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC397_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC397_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC397_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC397_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC397_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC397_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC397_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC397_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC397_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC397_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC397_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC397_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC397_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC397_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC397_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC397_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC397_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC397_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC397_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC397_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC397_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC397_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC397_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC397_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC397_LOAD_INLINE_DATA 0x01b4 +#define NVC397_LOAD_INLINE_DATA_V 31:0 + +#define NVC397_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC397_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC397_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC397_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC397_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC397_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC397_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC397_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC397_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC397_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC397_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC397_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC397_RUN_DS_NOW 0x0200 +#define NVC397_RUN_DS_NOW_V 31:0 + +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVC397_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVC397_SET_GS_MODE 0x0208 +#define NVC397_SET_GS_MODE_TYPE 0:0 +#define NVC397_SET_GS_MODE_TYPE_ANY 0x00000000 +#define NVC397_SET_GS_MODE_TYPE_FAST_GS 0x00000001 + +#define NVC397_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVC397_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVC397_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVC397_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVC397_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVC397_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVC397_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVC397_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_GS_DM_FIFO 0x0214 +#define NVC397_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVC397_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVC397_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVC397_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVC397_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC397_INVALIDATE_SHADER_CACHES 0x021c +#define NVC397_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC397_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC397_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC397_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC397_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC397_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC397_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC397_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC397_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC397_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC397_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC397_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC397_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC397_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC397_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC397_SET_INSTANCE_COUNT 0x0220 +#define NVC397_SET_INSTANCE_COUNT_V 31:0 + +#define NVC397_SET_POSITION_W_SCALED_OFFSET_ENABLE 0x0224 +#define NVC397_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE 0:0 +#define NVC397_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_GO_IDLE_TIMEOUT 0x022c +#define NVC397_SET_GO_IDLE_TIMEOUT_V 31:0 + +#define NVC397_SET_MME_VERSION 0x0234 +#define NVC397_SET_MME_VERSION_MAJOR 7:0 + +#define NVC397_INCREMENT_SYNC_POINT 0x02c8 +#define NVC397_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVC397_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVC397_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVC397_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVC397_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVC397_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVC397_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVC397_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVC397_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVC397_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVC397_DECOMPRESS_SURFACE 0x02e0 +#define NVC397_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVC397_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVC397_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVC397_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVC397_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVC397_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVC397_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVC397_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVC397_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVC397_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVC397_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVC397_SET_ZCULL_SUBREGION 0x02e8 +#define NVC397_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVC397_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVC397_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVC397_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVC397_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVC397_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVC397_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVC397_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVC397_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVC397_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVC397_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVC397_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVC397_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVC397_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVC397_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVC397_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVC397_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVC397_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVC397_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVC397_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVC397_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVC397_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVC397_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVC397_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVC397_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC397_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVC397_DRAW_ZERO_INDEX 0x0304 +#define NVC397_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVC397_SET_L1_CONFIGURATION 0x0308 +#define NVC397_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVC397_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC397_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVC397_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVC397_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVC397_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVC397_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVC397_SET_SPA_VERSION 0x0310 +#define NVC397_SET_SPA_VERSION_MINOR 7:0 +#define NVC397_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC397_SET_SNAP_GRID_LINE 0x0318 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC397_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC397_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVC397_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC397_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC397_SET_SNAP_GRID_NON_LINE 0x031c +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC397_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC397_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVC397_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC397_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC397_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVC397_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVC397_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVC397_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVC397_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVC397_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVC397_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVC397_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVC397_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVC397_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVC397_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVC397_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVC397_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVC397_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVC397_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVC397_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVC397_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVC397_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVC397_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVC397_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVC397_SET_TESSELLATION_LOD_V1 0x0330 +#define NVC397_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVC397_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVC397_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVC397_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVC397_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVC397_RESERVED_TG07 0x033c +#define NVC397_RESERVED_TG07_V 0:0 + +#define NVC397_RESERVED_TG08 0x0340 +#define NVC397_RESERVED_TG08_V 0:0 + +#define NVC397_RESERVED_TG09 0x0344 +#define NVC397_RESERVED_TG09_V 0:0 + +#define NVC397_RESERVED_TG10 0x0348 +#define NVC397_RESERVED_TG10_V 0:0 + +#define NVC397_RESERVED_TG11 0x034c +#define NVC397_RESERVED_TG11_V 0:0 + +#define NVC397_RESERVED_TG12 0x0350 +#define NVC397_RESERVED_TG12_V 0:0 + +#define NVC397_RESERVED_TG13 0x0354 +#define NVC397_RESERVED_TG13_V 0:0 + +#define NVC397_RESERVED_TG14 0x0358 +#define NVC397_RESERVED_TG14_V 0:0 + +#define NVC397_RESERVED_TG15 0x035c +#define NVC397_RESERVED_TG15_V 0:0 + +#define NVC397_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVC397_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVC397_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVC397_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVC397_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVC397_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVC397_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVC397_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVC397_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVC397_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVC397_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVC397_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVC397_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE 8:8 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE 9:9 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC397_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVC397_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVC397_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVC397_SET_RASTER_ENABLE 0x037c +#define NVC397_SET_RASTER_ENABLE_V 0:0 +#define NVC397_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVC397_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVC397_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVC397_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVC397_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVC397_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVC397_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVC397_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVC397_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVC397_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVC397_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVC397_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVC397_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVC397_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVC397_SET_POSITION_W_SCALED_OFFSET_SCALE_A(j) (0x0400+(j)*16) +#define NVC397_SET_POSITION_W_SCALED_OFFSET_SCALE_A_V 31:0 + +#define NVC397_SET_POSITION_W_SCALED_OFFSET_SCALE_B(j) (0x0404+(j)*16) +#define NVC397_SET_POSITION_W_SCALED_OFFSET_SCALE_B_V 31:0 + +#define NVC397_SET_POSITION_W_SCALED_OFFSET_RESERVED_A(j) (0x0408+(j)*16) +#define NVC397_SET_POSITION_W_SCALED_OFFSET_RESERVED_A_V 31:0 + +#define NVC397_SET_POSITION_W_SCALED_OFFSET_RESERVED_B(j) (0x040c+(j)*16) +#define NVC397_SET_POSITION_W_SCALED_OFFSET_RESERVED_B_V 31:0 + +#define NVC397_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVC397_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVC397_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVC397_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVC397_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVC397_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVC397_SET_RASTER_INPUT 0x0740 +#define NVC397_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVC397_SET_STREAM_OUTPUT 0x0744 +#define NVC397_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVC397_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVC397_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVC397_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVC397_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVC397_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVC397_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVC397_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVC397_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVC397_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC397_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC397_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC397_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVC397_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC397_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC397_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVC397_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVC397_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVC397_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVC397_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVC397_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVC397_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVC397_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC397_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVC397_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC397_SET_STENCIL_ZERO_BANDWIDTH_CLEAR 0x07b0 +#define NVC397_SET_STENCIL_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC397_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVC397_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVC397_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVC397_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVC397_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVC397_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVC397_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVC397_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVC397_SET_CULL_BEFORE_FETCH 0x07dc +#define NVC397_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVC397_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVC397_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVC397_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVC397_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVC397_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVC397_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVC397_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVC397_SET_ZCULL_STORAGE_A 0x07e8 +#define NVC397_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVC397_SET_ZCULL_STORAGE_B 0x07ec +#define NVC397_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVC397_SET_ZCULL_STORAGE_C 0x07f0 +#define NVC397_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC397_SET_ZCULL_STORAGE_D 0x07f4 +#define NVC397_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC397_SET_ZT_READ_ONLY 0x07f8 +#define NVC397_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVC397_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVC397_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVC397_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVC397_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVC397_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVC397_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVC397_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVC397_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVC397_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVC397_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVC397_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVC397_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVC397_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVC397_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVC397_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVC397_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVC397_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVC397_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVC397_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVC397_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVC397_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVC397_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVC397_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVC397_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVC397_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC397_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC397_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVC397_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC397_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC397_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVC397_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC397_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVC397_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVC397_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVC397_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVC397_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVC397_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVC397_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVC397_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVC397_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVC397_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVC397_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVC397_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVC397_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVC397_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVC397_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVC397_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVC397_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVC397_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVC397_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVC397_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVC397_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVC397_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVC397_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVC397_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVC397_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVC397_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC397_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVC397_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVC397_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC397_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVC397_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVC397_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVC397_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVC397_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVC397_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVC397_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVC397_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVC397_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVC397_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVC397_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVC397_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVC397_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVC397_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVC397_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVC397_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVC397_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVC397_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC397_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVC397_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVC397_SET_STATISTICS_COUNTER 0x0d68 +#define NVC397_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVC397_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVC397_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVC397_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVC397_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVC397_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVC397_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVC397_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVC397_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVC397_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVC397_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVC397_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVC397_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVC397_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVC397_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVC397_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVC397_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 +#define NVC397_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE 16:16 +#define NVC397_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVC397_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC397_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC397_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVC397_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC397_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC397_SET_VERTEX_ARRAY_START 0x0d74 +#define NVC397_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVC397_DRAW_VERTEX_ARRAY 0x0d78 +#define NVC397_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVC397_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVC397_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVC397_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVC397_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVC397_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVC397_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVC397_SET_Z_CLEAR_VALUE 0x0d90 +#define NVC397_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVC397_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC397_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC397_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC397_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVC397_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVC397_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVC397_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC397_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC397_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVC397_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVC397_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVC397_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVC397_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVC397_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVC397_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVC397_SET_FRONT_POLYGON_MODE 0x0dac +#define NVC397_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVC397_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC397_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC397_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC397_SET_BACK_POLYGON_MODE 0x0db0 +#define NVC397_SET_BACK_POLYGON_MODE_V 31:0 +#define NVC397_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC397_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC397_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC397_SET_POLY_SMOOTH 0x0db4 +#define NVC397_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVC397_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVC397_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVC397_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVC397_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVC397_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVC397_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVC397_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVC397_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVC397_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVC397_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVC397_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVC397_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVC397_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVC397_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVC397_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVC397_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVC397_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVC397_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_PATCH 0x0dcc +#define NVC397_SET_PATCH_SIZE 7:0 + +#define NVC397_SET_ITERATED_BLEND 0x0dd0 +#define NVC397_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVC397_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVC397_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVC397_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVC397_SET_ZCULL_CRITERION 0x0dd8 +#define NVC397_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVC397_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVC397_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVC397_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVC397_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVC397_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVC397_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVC397_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVC397_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVC397_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVC397_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVC397_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVC397_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVC397_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVC397_SET_ZCULL_CRITERION_SREF 23:16 +#define NVC397_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVC397_PIXEL_SHADER_BARRIER 0x0de0 +#define NVC397_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVC397_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVC397_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC397_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC397_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVC397_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVC397_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVC397_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVC397_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVC397_SET_WINDOW_OFFSET_X 0x0df8 +#define NVC397_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVC397_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVC397_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVC397_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVC397_SET_SCISSOR_ENABLE_V 0:0 +#define NVC397_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVC397_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVC397_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVC397_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVC397_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVC397_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVC397_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVC397_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVC397_SET_VPC_PERF_KNOB 0x0f14 +#define NVC397_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVC397_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVC397_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVC397_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVC397_PM_LOCAL_TRIGGER 0x0f18 +#define NVC397_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVC397_SET_POST_Z_PS_IMASK 0x0f1c +#define NVC397_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVC397_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVC397_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVC397_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVC397_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVC397_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVC397_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVC397_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVC397_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVC397_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVC397_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVC397_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVC397_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVC397_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVC397_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVC397_SET_BACK_STENCIL_MASK 0x0f58 +#define NVC397_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVC397_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVC397_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVC397_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVC397_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVC397_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVC397_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVC397_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVC397_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVC397_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVC397_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVC397_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVC397_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVC397_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVC397_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVC397_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVC397_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVC397_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVC397_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVC397_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVC397_SET_SAMPLE_MASK 0x0fa4 +#define NVC397_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVC397_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVC397_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVC397_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVC397_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVC397_SET_CT_MRT_ENABLE 0x0fac +#define NVC397_SET_CT_MRT_ENABLE_V 0:0 +#define NVC397_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVC397_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVC397_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVC397_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVC397_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVC397_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVC397_SET_TIR 0x0fb4 +#define NVC397_SET_TIR_MODE 1:0 +#define NVC397_SET_TIR_MODE_DISABLED 0x00000000 +#define NVC397_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVC397_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVC397_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVC397_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVC397_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVC397_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC397_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC397_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVC397_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVC397_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVC397_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVC397_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVC397_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVC397_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVC397_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVC397_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVC397_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVC397_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVC397_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_TIR_MODULATION 0x0fd4 +#define NVC397_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVC397_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVC397_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVC397_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVC397_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVC397_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVC397_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVC397_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVC397_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVC397_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVC397_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVC397_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVC397_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVC397_SET_ZT_A 0x0fe0 +#define NVC397_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_ZT_B 0x0fe4 +#define NVC397_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_ZT_FORMAT 0x0fe8 +#define NVC397_SET_ZT_FORMAT_V 4:0 +#define NVC397_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVC397_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVC397_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVC397_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVC397_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVC397_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVC397_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVC397_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVC397_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVC397_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVC397_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVC397_SET_ZT_BLOCK_SIZE 0x0fec +#define NVC397_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVC397_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC397_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVC397_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC397_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC397_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC397_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC397_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC397_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC397_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVC397_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC397_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVC397_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVC397_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVC397_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVC397_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC397_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVC397_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVC397_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC397_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC397_SET_VIEWPORT_MULTICAST 0x1004 +#define NVC397_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVC397_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVC397_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVC397_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVC397_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVC397_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVC397_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC397_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVC397_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVC397_SET_RESERVED_SW_METHOD00 0x1014 +#define NVC397_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC397_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVC397_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC397_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVC397_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC397_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVC397_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC397_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVC397_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC397_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_RESERVED_SW_METHOD01 0x1028 +#define NVC397_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD02 0x102c +#define NVC397_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC397_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVC397_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVC397_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVC397_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVC397_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVC397_SET_SPARE_NOOP01 0x1044 +#define NVC397_SET_SPARE_NOOP01_V 31:0 + +#define NVC397_SET_SPARE_NOOP02 0x1048 +#define NVC397_SET_SPARE_NOOP02_V 31:0 + +#define NVC397_SET_SPARE_NOOP03 0x104c +#define NVC397_SET_SPARE_NOOP03_V 31:0 + +#define NVC397_SET_SPARE_NOOP04 0x1050 +#define NVC397_SET_SPARE_NOOP04_V 31:0 + +#define NVC397_SET_SPARE_NOOP05 0x1054 +#define NVC397_SET_SPARE_NOOP05_V 31:0 + +#define NVC397_SET_SPARE_NOOP06 0x1058 +#define NVC397_SET_SPARE_NOOP06_V 31:0 + +#define NVC397_SET_SPARE_NOOP07 0x105c +#define NVC397_SET_SPARE_NOOP07_V 31:0 + +#define NVC397_SET_SPARE_NOOP08 0x1060 +#define NVC397_SET_SPARE_NOOP08_V 31:0 + +#define NVC397_SET_SPARE_NOOP09 0x1064 +#define NVC397_SET_SPARE_NOOP09_V 31:0 + +#define NVC397_SET_SPARE_NOOP10 0x1068 +#define NVC397_SET_SPARE_NOOP10_V 31:0 + +#define NVC397_SET_SPARE_NOOP11 0x106c +#define NVC397_SET_SPARE_NOOP11_V 31:0 + +#define NVC397_SET_SPARE_NOOP12 0x1070 +#define NVC397_SET_SPARE_NOOP12_V 31:0 + +#define NVC397_SET_SPARE_NOOP13 0x1074 +#define NVC397_SET_SPARE_NOOP13_V 31:0 + +#define NVC397_SET_SPARE_NOOP14 0x1078 +#define NVC397_SET_SPARE_NOOP14_V 31:0 + +#define NVC397_SET_SPARE_NOOP15 0x107c +#define NVC397_SET_SPARE_NOOP15_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVC397_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVC397_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVC397_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD06 0x10bc +#define NVC397_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVC397_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVC397_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVC397_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVC397_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVC397_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVC397_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVC397_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD13 0x10dc +#define NVC397_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC397_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVC397_UNBIND_ALL 0x10f4 +#define NVC397_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVC397_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVC397_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVC397_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVC397_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC397_SET_RESERVED_SW_METHOD14 0x1100 +#define NVC397_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC397_SET_RESERVED_SW_METHOD15 0x1104 +#define NVC397_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC397_NO_OPERATION_DATA_HI 0x110c +#define NVC397_NO_OPERATION_DATA_HI_V 31:0 + +#define NVC397_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVC397_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVC397_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVC397_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVC397_PM_TRIGGER_END 0x1114 +#define NVC397_PM_TRIGGER_END_V 31:0 + +#define NVC397_SET_VERTEX_ID_BASE 0x1118 +#define NVC397_SET_VERTEX_ID_BASE_V 31:0 + +#define NVC397_SET_STENCIL_COMPRESSION 0x111c +#define NVC397_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVC397_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC397_SET_TIR_CONTROL 0x1130 +#define NVC397_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVC397_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC397_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC397_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVC397_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC397_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC397_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVC397_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVC397_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 + +#define NVC397_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVC397_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVC397_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVC397_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVC397_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVC397_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVC397_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVC397_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVC397_SET_FILL_VIA_TRIANGLE 0x113c +#define NVC397_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVC397_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVC397_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVC397_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVC397_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVC397_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVC397_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVC397_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVC397_FLUSH_PENDING_WRITES 0x1144 +#define NVC397_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVC397_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVC397_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC397_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC397_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC397_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVC397_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC397_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC397_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVC397_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVC397_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVC397_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVC397_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVC397_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVC397_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVC397_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVC397_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVC397_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVC397_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVC397_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVC397_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVC397_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVC397_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVC397_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC397_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC397_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVC397_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC397_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_SCREEN_STATE_MASK 0x1204 +#define NVC397_SET_SCREEN_STATE_MASK_MASK 3:0 + +#define NVC397_SET_ZT_SPARSE 0x1208 +#define NVC397_SET_ZT_SPARSE_ENABLE 0:0 +#define NVC397_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVC397_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVC397_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVC397_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVC397_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC397_SET_CT_SELECT 0x121c +#define NVC397_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVC397_SET_CT_SELECT_TARGET0 6:4 +#define NVC397_SET_CT_SELECT_TARGET1 9:7 +#define NVC397_SET_CT_SELECT_TARGET2 12:10 +#define NVC397_SET_CT_SELECT_TARGET3 15:13 +#define NVC397_SET_CT_SELECT_TARGET4 18:16 +#define NVC397_SET_CT_SELECT_TARGET5 21:19 +#define NVC397_SET_CT_SELECT_TARGET6 24:22 +#define NVC397_SET_CT_SELECT_TARGET7 27:25 + +#define NVC397_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVC397_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVC397_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVC397_SET_ZT_SIZE_A 0x1228 +#define NVC397_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVC397_SET_ZT_SIZE_B 0x122c +#define NVC397_SET_ZT_SIZE_B_HEIGHT 17:0 + +#define NVC397_SET_ZT_SIZE_C 0x1230 +#define NVC397_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVC397_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVC397_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC397_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVC397_SET_SAMPLER_BINDING 0x1234 +#define NVC397_SET_SAMPLER_BINDING_V 0:0 +#define NVC397_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVC397_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVC397_DRAW_AUTO 0x123c +#define NVC397_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVC397_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVC397_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVC397_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVC397_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVC397_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVC397_SET_BACK_END_COPY_A 0x1264 +#define NVC397_SET_BACK_END_COPY_A_DWORDS 7:0 +#define NVC397_SET_BACK_END_COPY_A_SATURATE32_ENABLE 8:8 +#define NVC397_SET_BACK_END_COPY_A_SATURATE32_ENABLE_FALSE 0x00000000 +#define NVC397_SET_BACK_END_COPY_A_SATURATE32_ENABLE_TRUE 0x00000001 +#define NVC397_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE 12:12 +#define NVC397_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_FALSE 0x00000000 +#define NVC397_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_BACK_END_COPY_B 0x1268 +#define NVC397_SET_BACK_END_COPY_B_SRC_ADDRESS_UPPER 7:0 + +#define NVC397_SET_BACK_END_COPY_C 0x126c +#define NVC397_SET_BACK_END_COPY_C_SRC_ADDRESS_LOWER 31:0 + +#define NVC397_SET_BACK_END_COPY_D 0x1270 +#define NVC397_SET_BACK_END_COPY_D_DEST_ADDRESS_UPPER 7:0 + +#define NVC397_SET_BACK_END_COPY_E 0x1274 +#define NVC397_SET_BACK_END_COPY_E_DEST_ADDRESS_LOWER 31:0 + +#define NVC397_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVC397_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 19:0 + +#define NVC397_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVC397_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVC397_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC397_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVC397_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVC397_CLEAR_ZCULL_REGION 0x12c8 +#define NVC397_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVC397_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVC397_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVC397_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVC397_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC397_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC397_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVC397_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC397_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC397_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVC397_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVC397_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVC397_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVC397_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVC397_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVC397_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVC397_SET_DEPTH_TEST 0x12cc +#define NVC397_SET_DEPTH_TEST_ENABLE 0:0 +#define NVC397_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVC397_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_FILL_MODE 0x12d0 +#define NVC397_SET_FILL_MODE_V 31:0 +#define NVC397_SET_FILL_MODE_V_POINT 0x00000001 +#define NVC397_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVC397_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVC397_SET_SHADE_MODE 0x12d4 +#define NVC397_SET_SHADE_MODE_V 31:0 +#define NVC397_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVC397_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVC397_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVC397_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC397_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC397_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVC397_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVC397_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVC397_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVC397_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVC397_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVC397_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVC397_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVC397_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_DEPTH_WRITE 0x12e8 +#define NVC397_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVC397_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_ALPHA_TEST 0x12ec +#define NVC397_SET_ALPHA_TEST_ENABLE 0:0 +#define NVC397_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVC397_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVC397_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVC397_DRAW_INLINE_INDEX4X8 0x1304 +#define NVC397_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVC397_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVC397_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVC397_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVC397_D3D_SET_CULL_MODE 0x1308 +#define NVC397_D3D_SET_CULL_MODE_V 31:0 +#define NVC397_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVC397_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVC397_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVC397_SET_DEPTH_FUNC 0x130c +#define NVC397_SET_DEPTH_FUNC_V 31:0 +#define NVC397_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVC397_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVC397_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC397_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC397_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVC397_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC397_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC397_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC397_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVC397_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVC397_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC397_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC397_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVC397_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC397_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC397_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC397_SET_ALPHA_REF 0x1310 +#define NVC397_SET_ALPHA_REF_V 31:0 + +#define NVC397_SET_ALPHA_FUNC 0x1314 +#define NVC397_SET_ALPHA_FUNC_V 31:0 +#define NVC397_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVC397_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVC397_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC397_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC397_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVC397_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC397_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC397_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC397_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVC397_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVC397_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC397_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC397_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVC397_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC397_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC397_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC397_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVC397_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVC397_SET_BLEND_CONST_RED 0x131c +#define NVC397_SET_BLEND_CONST_RED_V 31:0 + +#define NVC397_SET_BLEND_CONST_GREEN 0x1320 +#define NVC397_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVC397_SET_BLEND_CONST_BLUE 0x1324 +#define NVC397_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVC397_SET_BLEND_CONST_ALPHA 0x1328 +#define NVC397_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVC397_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC397_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC397_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC397_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC397_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC397_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC397_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVC397_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC397_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC397_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_BLEND_COLOR_OP 0x1340 +#define NVC397_SET_BLEND_COLOR_OP_V 31:0 +#define NVC397_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC397_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC397_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC397_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC397_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC397_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC397_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC397_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC397_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC397_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC397_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC397_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC397_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC397_SET_BLEND_ALPHA_OP 0x134c +#define NVC397_SET_BLEND_ALPHA_OP_V 31:0 +#define NVC397_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC397_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC397_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC397_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC397_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC397_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC397_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC397_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC397_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC397_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC397_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC397_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVC397_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVC397_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVC397_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC397_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC397_SET_SINGLE_ROP_CONTROL 0x135c +#define NVC397_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVC397_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_BLEND(i) (0x1360+(i)*4) +#define NVC397_SET_BLEND_ENABLE 0:0 +#define NVC397_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVC397_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_STENCIL_TEST 0x1380 +#define NVC397_SET_STENCIL_TEST_ENABLE 0:0 +#define NVC397_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC397_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_STENCIL_OP_FAIL 0x1384 +#define NVC397_SET_STENCIL_OP_FAIL_V 31:0 +#define NVC397_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC397_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC397_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC397_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC397_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC397_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC397_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC397_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC397_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC397_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC397_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC397_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC397_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC397_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC397_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC397_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC397_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVC397_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC397_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC397_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC397_SET_STENCIL_OP_ZPASS 0x138c +#define NVC397_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVC397_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC397_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC397_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC397_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC397_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC397_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC397_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC397_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC397_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC397_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC397_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC397_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC397_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC397_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC397_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC397_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC397_SET_STENCIL_FUNC 0x1390 +#define NVC397_SET_STENCIL_FUNC_V 31:0 +#define NVC397_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC397_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC397_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC397_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC397_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC397_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC397_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC397_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC397_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC397_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC397_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC397_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC397_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC397_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC397_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC397_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC397_SET_STENCIL_FUNC_REF 0x1394 +#define NVC397_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVC397_SET_STENCIL_FUNC_MASK 0x1398 +#define NVC397_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVC397_SET_STENCIL_MASK 0x139c +#define NVC397_SET_STENCIL_MASK_V 7:0 + +#define NVC397_SET_DRAW_AUTO_START 0x13a4 +#define NVC397_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVC397_SET_PS_SATURATE 0x13a8 +#define NVC397_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVC397_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVC397_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC397_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVC397_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVC397_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC397_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVC397_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVC397_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC397_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVC397_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVC397_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC397_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVC397_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVC397_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC397_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVC397_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVC397_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC397_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVC397_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVC397_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC397_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVC397_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVC397_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC397_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVC397_SET_WINDOW_ORIGIN 0x13ac +#define NVC397_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVC397_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVC397_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVC397_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVC397_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVC397_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVC397_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVC397_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC397_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVC397_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC397_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVC397_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVC397_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVC397_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC397_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC397_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC397_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC397_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC397_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC397_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVC397_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVC397_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVC397_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVC397_SET_PS_WARP_WATERMARKS 0x1450 +#define NVC397_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVC397_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVC397_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVC397_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVC397_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC397_STORE_ZCULL 0x1464 +#define NVC397_STORE_ZCULL_V 0:0 + +#define NVC397_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVC397_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVC397_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVC397_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVC397_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVC397_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVC397_LOAD_ZCULL 0x1500 +#define NVC397_LOAD_ZCULL_V 0:0 + +#define NVC397_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVC397_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVC397_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVC397_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC397_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC397_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVC397_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC397_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC397_SET_USER_CLIP_ENABLE 0x1510 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVC397_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVC397_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVC397_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVC397_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_POINT_SIZE 0x1518 +#define NVC397_SET_POINT_SIZE_V 31:0 + +#define NVC397_SET_ZCULL_STATS 0x151c +#define NVC397_SET_ZCULL_STATS_ENABLE 0:0 +#define NVC397_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_POINT_SPRITE 0x1520 +#define NVC397_SET_POINT_SPRITE_ENABLE 0:0 +#define NVC397_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC397_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC397_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC397_CLEAR_REPORT_VALUE 0x1530 +#define NVC397_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVC397_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVC397_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVC397_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVC397_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVC397_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVC397_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC397_CLEAR_REPORT_VALUE_TYPE_SCG_CLOCKS 0x00000009 + +#define NVC397_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVC397_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVC397_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVC397_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVC397_SET_ZT_SELECT 0x1538 +#define NVC397_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVC397_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVC397_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVC397_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVC397_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVC397_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVC397_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVC397_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVC397_SET_RENDER_ENABLE_A 0x1550 +#define NVC397_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_RENDER_ENABLE_B 0x1554 +#define NVC397_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_RENDER_ENABLE_C 0x1558 +#define NVC397_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC397_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC397_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC397_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC397_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC397_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC397_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC397_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC397_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC397_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC397_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVC397_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVC397_SET_ANTI_ALIASED_LINE 0x1570 +#define NVC397_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVC397_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC397_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC397_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_TEX_HEADER_POOL_C 0x157c +#define NVC397_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC397_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVC397_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVC397_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVC397_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVC397_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC397_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC397_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC397_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC397_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC397_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC397_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVC397_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVC397_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC397_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC397_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC397_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC397_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC397_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC397_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC397_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC397_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC397_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC397_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC397_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC397_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC397_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC397_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC397_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC397_SET_SRGB_WRITE 0x15b8 +#define NVC397_SET_SRGB_WRITE_ENABLE 0:0 +#define NVC397_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_DEPTH_BIAS 0x15bc +#define NVC397_SET_DEPTH_BIAS_V 31:0 + +#define NVC397_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVC397_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVC397_SET_RT_LAYER 0x15cc +#define NVC397_SET_RT_LAYER_V 15:0 +#define NVC397_SET_RT_LAYER_CONTROL 16:16 +#define NVC397_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVC397_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVC397_SET_ANTI_ALIAS 0x15d0 +#define NVC397_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVC397_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVC397_SET_EDGE_FLAG 0x15e4 +#define NVC397_SET_EDGE_FLAG_V 0:0 +#define NVC397_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVC397_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVC397_DRAW_INLINE_INDEX 0x15e8 +#define NVC397_DRAW_INLINE_INDEX_V 31:0 + +#define NVC397_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVC397_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVC397_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVC397_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVC397_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVC397_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVC397_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVC397_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVC397_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVC397_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVC397_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVC397_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVC397_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVC397_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVC397_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVC397_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVC397_SET_POINT_SPRITE_SELECT 0x1604 +#define NVC397_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVC397_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVC397_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVC397_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVC397_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVC397_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVC397_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVC397_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVC397_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVC397_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVC397_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVC397_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVC397_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVC397_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVC397_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVC397_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVC397_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVC397_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVC397_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVC397_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVC397_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVC397_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVC397_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVC397_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVC397_END 0x1614 +#define NVC397_END_V 0:0 + +#define NVC397_BEGIN 0x1618 +#define NVC397_BEGIN_OP 15:0 +#define NVC397_BEGIN_OP_POINTS 0x00000000 +#define NVC397_BEGIN_OP_LINES 0x00000001 +#define NVC397_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVC397_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVC397_BEGIN_OP_TRIANGLES 0x00000004 +#define NVC397_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVC397_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVC397_BEGIN_OP_QUADS 0x00000007 +#define NVC397_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVC397_BEGIN_OP_POLYGON 0x00000009 +#define NVC397_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVC397_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVC397_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_BEGIN_OP_PATCH 0x0000000E +#define NVC397_BEGIN_PRIMITIVE_ID 24:24 +#define NVC397_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC397_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC397_BEGIN_INSTANCE_ID 27:26 +#define NVC397_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVC397_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC397_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC397_BEGIN_SPLIT_MODE 30:29 +#define NVC397_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC397_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC397_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC397_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC397_BEGIN_INSTANCE_ITERATE_ENABLE 31:31 +#define NVC397_BEGIN_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC397_BEGIN_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_VERTEX_ID_COPY 0x161c +#define NVC397_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVC397_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVC397_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVC397_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVC397_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVC397_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVC397_LOAD_PRIMITIVE_ID 0x1624 +#define NVC397_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVC397_SET_SHADER_BASED_CULL 0x162c +#define NVC397_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVC397_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVC397_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVC397_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVC397_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_CLASS_VERSION 0x1638 +#define NVC397_SET_CLASS_VERSION_CURRENT 15:0 +#define NVC397_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC397_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVC397_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVC397_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVC397_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVC397_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVC397_SET_DA_OUTPUT 0x164c +#define NVC397_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVC397_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVC397_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVC397_SET_ANTI_ALIASED_POINT 0x1658 +#define NVC397_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVC397_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_POINT_CENTER_MODE 0x165c +#define NVC397_SET_POINT_CENTER_MODE_V 31:0 +#define NVC397_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVC397_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVC397_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVC397_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVC397_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVC397_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVC397_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVC397_SET_LINE_STIPPLE 0x166c +#define NVC397_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVC397_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVC397_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVC397_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVC397_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVC397_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVC397_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVC397_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVC397_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVC397_SET_PROVOKING_VERTEX 0x1684 +#define NVC397_SET_PROVOKING_VERTEX_V 0:0 +#define NVC397_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVC397_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVC397_SET_TWO_SIDED_LIGHT 0x1688 +#define NVC397_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVC397_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_POLYGON_STIPPLE 0x168c +#define NVC397_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVC397_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_SHADER_CONTROL 0x1690 +#define NVC397_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVC397_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVC397_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVC397_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVC397_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC397_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC397_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVC397_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC397_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVC397_CHECK_CLASS_VERSION 0x16a0 +#define NVC397_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVC397_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC397_SET_SPH_VERSION 0x16a4 +#define NVC397_SET_SPH_VERSION_CURRENT 15:0 +#define NVC397_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC397_CHECK_SPH_VERSION 0x16a8 +#define NVC397_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVC397_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC397_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVC397_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVC397_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC397_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVC397_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVC397_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVC397_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVC397_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVC397_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVC397_SET_AAM_VERSION 0x1790 +#define NVC397_SET_AAM_VERSION_CURRENT 15:0 +#define NVC397_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC397_CHECK_AAM_VERSION 0x1794 +#define NVC397_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVC397_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC397_SET_ZT_LAYER 0x179c +#define NVC397_SET_ZT_LAYER_OFFSET 15:0 + +#define NVC397_SET_INDEX_BUFFER_A 0x17c8 +#define NVC397_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVC397_SET_INDEX_BUFFER_B 0x17cc +#define NVC397_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVC397_SET_INDEX_BUFFER_C 0x17d0 +#define NVC397_SET_INDEX_BUFFER_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC397_SET_INDEX_BUFFER_D 0x17d4 +#define NVC397_SET_INDEX_BUFFER_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC397_SET_INDEX_BUFFER_E 0x17d8 +#define NVC397_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVC397_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVC397_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVC397_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVC397_SET_INDEX_BUFFER_F 0x17dc +#define NVC397_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVC397_DRAW_INDEX_BUFFER 0x17e0 +#define NVC397_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC397_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVC397_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVC397_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVC397_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVC397_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVC397_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVC397_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVC397_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVC397_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVC397_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVC397_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVC397_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVC397_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVC397_OGL_SET_CULL 0x1918 +#define NVC397_OGL_SET_CULL_ENABLE 0:0 +#define NVC397_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVC397_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVC397_OGL_SET_FRONT_FACE 0x191c +#define NVC397_OGL_SET_FRONT_FACE_V 31:0 +#define NVC397_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVC397_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVC397_OGL_SET_CULL_FACE 0x1920 +#define NVC397_OGL_SET_CULL_FACE_V 31:0 +#define NVC397_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVC397_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVC397_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVC397_SET_VIEWPORT_PIXEL 0x1924 +#define NVC397_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVC397_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVC397_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVC397_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVC397_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVC397_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVC397_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE 17:16 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_USE_FIELD_MIN_Z_ZERO_MAX_Z_ONE 0x00000000 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MIN_Z_MAX_Z 0x00000001 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_ZERO_ONE 0x00000002 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MINUS_INF_PLUS_INF 0x00000003 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVC397_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVC397_SET_USER_CLIP_OP 0x1940 +#define NVC397_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVC397_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVC397_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVC397_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVC397_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVC397_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVC397_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVC397_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVC397_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVC397_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVC397_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVC397_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVC397_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVC397_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVC397_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVC397_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVC397_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVC397_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVC397_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVC397_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVC397_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVC397_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVC397_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVC397_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVC397_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC397_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC397_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC397_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC397_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC397_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVC397_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVC397_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVC397_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVC397_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVC397_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVC397_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVC397_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVC397_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVC397_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVC397_INVALIDATE_ZCULL 0x1958 +#define NVC397_INVALIDATE_ZCULL_V 31:0 +#define NVC397_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVC397_SET_ZCULL 0x1968 +#define NVC397_SET_ZCULL_Z_ENABLE 0:0 +#define NVC397_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVC397_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_ZCULL_BOUNDS 0x196c +#define NVC397_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVC397_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVC397_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVC397_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC397_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVC397_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVC397_ZCULL_SYNC 0x1978 +#define NVC397_ZCULL_SYNC_V 31:0 + +#define NVC397_SET_CLIP_ID_TEST 0x197c +#define NVC397_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVC397_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVC397_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVC397_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVC397_SET_CLIP_ID 0x1984 +#define NVC397_SET_CLIP_ID_V 31:0 + +#define NVC397_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVC397_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVC397_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVC397_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVC397_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVC397_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVC397_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVC397_SET_LOGIC_OP 0x19c4 +#define NVC397_SET_LOGIC_OP_ENABLE 0:0 +#define NVC397_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVC397_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_LOGIC_OP_FUNC 0x19c8 +#define NVC397_SET_LOGIC_OP_FUNC_V 31:0 +#define NVC397_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVC397_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVC397_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVC397_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVC397_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVC397_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVC397_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVC397_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVC397_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVC397_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVC397_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVC397_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVC397_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVC397_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVC397_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVC397_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVC397_SET_Z_COMPRESSION 0x19cc +#define NVC397_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVC397_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC397_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC397_CLEAR_SURFACE 0x19d0 +#define NVC397_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVC397_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC397_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC397_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVC397_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC397_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC397_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVC397_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVC397_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVC397_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVC397_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVC397_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVC397_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVC397_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVC397_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVC397_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVC397_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVC397_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVC397_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVC397_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVC397_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVC397_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVC397_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVC397_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVC397_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC397_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVC397_SET_CT_WRITE_R_ENABLE 0:0 +#define NVC397_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVC397_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVC397_SET_CT_WRITE_G_ENABLE 4:4 +#define NVC397_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVC397_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVC397_SET_CT_WRITE_B_ENABLE 8:8 +#define NVC397_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVC397_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVC397_SET_CT_WRITE_A_ENABLE 12:12 +#define NVC397_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVC397_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVC397_PIPE_NOP 0x1a2c +#define NVC397_PIPE_NOP_V 31:0 + +#define NVC397_SET_SPARE00 0x1a30 +#define NVC397_SET_SPARE00_V 31:0 + +#define NVC397_SET_SPARE01 0x1a34 +#define NVC397_SET_SPARE01_V 31:0 + +#define NVC397_SET_SPARE02 0x1a38 +#define NVC397_SET_SPARE02_V 31:0 + +#define NVC397_SET_SPARE03 0x1a3c +#define NVC397_SET_SPARE03_V 31:0 + +#define NVC397_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC397_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC397_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC397_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC397_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC397_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC397_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVC397_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC397_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVC397_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVC397_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC397_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC397_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVC397_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC397_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_SCG_CLOCKS 0x00000008 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC397_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC397_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVC397_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVC397_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC397_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC397_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVC397_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVC397_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVC397_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVC397_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVC397_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVC397_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVC397_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVC397_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVC397_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVC397_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVC397_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC397_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVC397_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC397_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVC397_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC397_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVC397_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVC397_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVC397_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC397_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC397_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC397_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC397_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC397_SET_VERTEX_STREAM_LIMIT_A_A(j) (0x1f00+(j)*8) +#define NVC397_SET_VERTEX_STREAM_LIMIT_A_A_UPPER 7:0 + +#define NVC397_SET_VERTEX_STREAM_LIMIT_A_B(j) (0x1f04+(j)*8) +#define NVC397_SET_VERTEX_STREAM_LIMIT_A_B_LOWER 31:0 + +#define NVC397_SET_VERTEX_STREAM_LIMIT_B_A(j) (0x1f80+(j)*8) +#define NVC397_SET_VERTEX_STREAM_LIMIT_B_A_UPPER 7:0 + +#define NVC397_SET_VERTEX_STREAM_LIMIT_B_B(j) (0x1f84+(j)*8) +#define NVC397_SET_VERTEX_STREAM_LIMIT_B_B_LOWER 31:0 + +#define NVC397_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVC397_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVC397_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVC397_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVC397_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVC397_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVC397_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVC397_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVC397_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVC397_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVC397_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVC397_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVC397_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVC397_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVC397_SET_PIPELINE_REGISTER_COUNT_V 8:0 + +#define NVC397_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVC397_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVC397_SET_PIPELINE_PROGRAM_ADDRESS_A(j) (0x2014+(j)*64) +#define NVC397_SET_PIPELINE_PROGRAM_ADDRESS_A_UPPER 7:0 + +#define NVC397_SET_PIPELINE_PROGRAM_ADDRESS_B(j) (0x2018+(j)*64) +#define NVC397_SET_PIPELINE_PROGRAM_ADDRESS_B_LOWER 31:0 + +#define NVC397_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVC397_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVC397_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVC397_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVC397_SET_FALCON00 0x2300 +#define NVC397_SET_FALCON00_V 31:0 + +#define NVC397_SET_FALCON01 0x2304 +#define NVC397_SET_FALCON01_V 31:0 + +#define NVC397_SET_FALCON02 0x2308 +#define NVC397_SET_FALCON02_V 31:0 + +#define NVC397_SET_FALCON03 0x230c +#define NVC397_SET_FALCON03_V 31:0 + +#define NVC397_SET_FALCON04 0x2310 +#define NVC397_SET_FALCON04_V 31:0 + +#define NVC397_SET_FALCON05 0x2314 +#define NVC397_SET_FALCON05_V 31:0 + +#define NVC397_SET_FALCON06 0x2318 +#define NVC397_SET_FALCON06_V 31:0 + +#define NVC397_SET_FALCON07 0x231c +#define NVC397_SET_FALCON07_V 31:0 + +#define NVC397_SET_FALCON08 0x2320 +#define NVC397_SET_FALCON08_V 31:0 + +#define NVC397_SET_FALCON09 0x2324 +#define NVC397_SET_FALCON09_V 31:0 + +#define NVC397_SET_FALCON10 0x2328 +#define NVC397_SET_FALCON10_V 31:0 + +#define NVC397_SET_FALCON11 0x232c +#define NVC397_SET_FALCON11_V 31:0 + +#define NVC397_SET_FALCON12 0x2330 +#define NVC397_SET_FALCON12_V 31:0 + +#define NVC397_SET_FALCON13 0x2334 +#define NVC397_SET_FALCON13_V 31:0 + +#define NVC397_SET_FALCON14 0x2338 +#define NVC397_SET_FALCON14_V 31:0 + +#define NVC397_SET_FALCON15 0x233c +#define NVC397_SET_FALCON15_V 31:0 + +#define NVC397_SET_FALCON16 0x2340 +#define NVC397_SET_FALCON16_V 31:0 + +#define NVC397_SET_FALCON17 0x2344 +#define NVC397_SET_FALCON17_V 31:0 + +#define NVC397_SET_FALCON18 0x2348 +#define NVC397_SET_FALCON18_V 31:0 + +#define NVC397_SET_FALCON19 0x234c +#define NVC397_SET_FALCON19_V 31:0 + +#define NVC397_SET_FALCON20 0x2350 +#define NVC397_SET_FALCON20_V 31:0 + +#define NVC397_SET_FALCON21 0x2354 +#define NVC397_SET_FALCON21_V 31:0 + +#define NVC397_SET_FALCON22 0x2358 +#define NVC397_SET_FALCON22_V 31:0 + +#define NVC397_SET_FALCON23 0x235c +#define NVC397_SET_FALCON23_V 31:0 + +#define NVC397_SET_FALCON24 0x2360 +#define NVC397_SET_FALCON24_V 31:0 + +#define NVC397_SET_FALCON25 0x2364 +#define NVC397_SET_FALCON25_V 31:0 + +#define NVC397_SET_FALCON26 0x2368 +#define NVC397_SET_FALCON26_V 31:0 + +#define NVC397_SET_FALCON27 0x236c +#define NVC397_SET_FALCON27_V 31:0 + +#define NVC397_SET_FALCON28 0x2370 +#define NVC397_SET_FALCON28_V 31:0 + +#define NVC397_SET_FALCON29 0x2374 +#define NVC397_SET_FALCON29_V 31:0 + +#define NVC397_SET_FALCON30 0x2378 +#define NVC397_SET_FALCON30_V 31:0 + +#define NVC397_SET_FALCON31 0x237c +#define NVC397_SET_FALCON31_V 31:0 + +#define NVC397_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVC397_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVC397_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVC397_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVC397_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVC397_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVC397_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVC397_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVC397_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVC397_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVC397_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVC397_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVC397_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVC397_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVC397_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVC397_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVC397_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVC397_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVC397_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVC397_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVC397_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC397_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC397_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVC397_SET_TRAP_HANDLER_A 0x25f8 +#define NVC397_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC397_SET_TRAP_HANDLER_B 0x25fc +#define NVC397_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC397_SET_COLOR_CLAMP 0x2600 +#define NVC397_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVC397_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVC397_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVC397_SET_BINDLESS_TEXTURE 0x2608 +#define NVC397_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 4:0 + +#define NVC397_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVC397_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVC397_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVC397_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVC397_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVC397_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC397_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC397_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC397_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC397_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC397_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC397_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC397_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC397_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC397_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC397_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC397_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC397_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC397_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC397_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVC397_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVC397_CALL_MME_MACRO_V 31:0 + +#define NVC397_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVC397_CALL_MME_DATA_V 31:0 + +#endif /* _cl_volta_a_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/clc3b5sw.h b/src/common/sdk/nvidia/inc/class/clc3b5sw.h index 2c1055c9d..b91398493 100644 --- a/src/common/sdk/nvidia/inc/class/clc3b5sw.h +++ b/src/common/sdk/nvidia/inc/class/clc3b5sw.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2016-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,38 +21,34 @@ * DEALINGS IN THE SOFTWARE. */ -#include "nvtypes.h" +#pragma once -#ifndef _clc3b5sw_h_ -#define _clc3b5sw_h_ +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc3b5sw.finn +// -#ifdef __cplusplus -extern "C" { -#endif -/* This file is *not* auto-generated. */ // // Using VERSION_0 will cause the API to interpret // engineType as a CE engine instance. This allows // for backward compatibility with 85B5sw and 90B5sw. // -#define NVC3B5_ALLOCATION_PARAMETERS_VERSION_0 0 +#define NVC3B5_ALLOCATION_PARAMETERS_VERSION_0 0 // // Using VERSION_1 will cause the API to interpret // engineType as an NV2080_ENGINE_TYPE ordinal. // -#define NVC3B5_ALLOCATION_PARAMETERS_VERSION_1 1 +#define NVC3B5_ALLOCATION_PARAMETERS_VERSION_1 1 -typedef struct -{ - NvU32 version; - NvU32 engineType; +#define NVC3B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc3b5U) + +typedef struct NVC3B5_ALLOCATION_PARAMETERS { + NvU32 version; + NvU32 engineType; } NVC3B5_ALLOCATION_PARAMETERS; -#ifdef __cplusplus -}; /* extern "C" */ -#endif -#endif // _clc3b5sw_h_ - diff --git a/src/common/sdk/nvidia/inc/class/clc570.h b/src/common/sdk/nvidia/inc/class/clc570.h index 12d200f47..0e562ab30 100644 --- a/src/common/sdk/nvidia/inc/class/clc570.h +++ b/src/common/sdk/nvidia/inc/class/clc570.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -20,28 +20,22 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _clc570_h_ -#define _clc570_h_ +#pragma once -#ifdef __cplusplus -extern "C" { -#endif +#include -#include "nvtypes.h" +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc570.finn +// -#include "class/cl5070.h" +#define NVC570_DISPLAY (0xc570U) /* finn: Evaluated from "NVC570_ALLOCATION_PARAMETERS_MESSAGE_ID" */ -#define NVC570_DISPLAY (0x0000C570) +#define NVC570_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc570U) -typedef struct -{ - NvU32 numHeads; // Number of HEADs in this chip/display - NvU32 numSors; // Number of SORs in this chip/display - NvU32 numPiors; // Number of PIORs in this chip/display +typedef struct NVC570_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numPiors; // Number of PIORs in this chip/display } NVC570_ALLOCATION_PARAMETERS; -#ifdef __cplusplus -}; /* extern "C" */ -#endif - -#endif /* _clc570_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/clc574.h b/src/common/sdk/nvidia/inc/class/clc574.h index 6df8d0320..4587c7add 100644 --- a/src/common/sdk/nvidia/inc/class/clc574.h +++ b/src/common/sdk/nvidia/inc/class/clc574.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,25 +21,21 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _clc574_h_ -#define _clc574_h_ +#pragma once -#ifdef __cplusplus -extern "C" { -#endif +#include -#include "nvtypes.h" +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc574.finn +// -#define UVM_CHANNEL_RETAINER (0x0000C574) +#define UVM_CHANNEL_RETAINER (0xc574U) /* finn: Evaluated from "NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_MESSAGE_ID" */ -typedef struct -{ +#define NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_MESSAGE_ID (0xc574U) + +typedef struct NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS { NvHandle hClient; NvHandle hChannel; -}NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS; +} NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS; -#ifdef __cplusplus -}; /* extern "C" */ -#endif - -#endif /* _clc574_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/clc58b.h b/src/common/sdk/nvidia/inc/class/clc58b.h index abeefa790..7dba2c63e 100644 --- a/src/common/sdk/nvidia/inc/class/clc58b.h +++ b/src/common/sdk/nvidia/inc/class/clc58b.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,16 +21,18 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _clc58b_h_ -#define _clc58b_h_ +#pragma once -#ifdef __cplusplus -extern "C" { -#endif +#include -#define TURING_VMMU_A (0x0000c58b) +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc58b.finn +// -/** +#define TURING_VMMU_A (0xc58bU) /* finn: Evaluated from "TURING_VMMU_A_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +/* * @brief NvAlloc parameters for TuringVmmuA class * * This class represents mapping between guest physical and system physical. @@ -38,17 +40,11 @@ extern "C" { * * gfid [in] * GFID of VF - **/ + */ -typedef struct -{ +#define TURING_VMMU_A_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc58bU) + +typedef struct TURING_VMMU_A_ALLOCATION_PARAMETERS { NvHandle hHostVgpuDevice; } TURING_VMMU_A_ALLOCATION_PARAMETERS; - -#ifdef __cplusplus -}; /* extern "C" */ -#endif - -#endif // _clc58b_h - diff --git a/src/common/sdk/nvidia/inc/class/clc597.h b/src/common/sdk/nvidia/inc/class/clc597.h index 988e3c069..711dae101 100644 --- a/src/common/sdk/nvidia/inc/class/clc597.h +++ b/src/common/sdk/nvidia/inc/class/clc597.h @@ -1,29 +1,4352 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. -#ifndef _clc597_h_ -#define _clc597_h_ + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_turing_a_h_ +#define _cl_turing_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl turing_a */ + +#include "nvtypes.h" #define TURING_A 0xC597 -#endif // _clc597_h_ +#define NVC597_SET_OBJECT 0x0000 +#define NVC597_SET_OBJECT_CLASS_ID 15:0 +#define NVC597_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC597_NO_OPERATION 0x0100 +#define NVC597_NO_OPERATION_V 31:0 + +#define NVC597_SET_NOTIFY_A 0x0104 +#define NVC597_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC597_SET_NOTIFY_B 0x0108 +#define NVC597_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC597_NOTIFY 0x010c +#define NVC597_NOTIFY_TYPE 31:0 +#define NVC597_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC597_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC597_WAIT_FOR_IDLE 0x0110 +#define NVC597_WAIT_FOR_IDLE_V 31:0 + +#define NVC597_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVC597_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVC597_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVC597_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVC597_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVC597_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVC597_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVC597_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVC597_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVC597_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVC597_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVC597_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVC597_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVC597_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVC597_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVC597_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVC597_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVC597_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVC597_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC597_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC597_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC597_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC597_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC597_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC597_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC597_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC597_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC597_SEND_GO_IDLE 0x013c +#define NVC597_SEND_GO_IDLE_V 31:0 + +#define NVC597_PM_TRIGGER 0x0140 +#define NVC597_PM_TRIGGER_V 31:0 + +#define NVC597_PM_TRIGGER_WFI 0x0144 +#define NVC597_PM_TRIGGER_WFI_V 31:0 + +#define NVC597_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC597_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC597_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC597_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC597_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC597_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC597_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC597_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC597_LINE_LENGTH_IN 0x0180 +#define NVC597_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC597_LINE_COUNT 0x0184 +#define NVC597_LINE_COUNT_VALUE 31:0 + +#define NVC597_OFFSET_OUT_UPPER 0x0188 +#define NVC597_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVC597_OFFSET_OUT 0x018c +#define NVC597_OFFSET_OUT_VALUE 31:0 + +#define NVC597_PITCH_OUT 0x0190 +#define NVC597_PITCH_OUT_VALUE 31:0 + +#define NVC597_SET_DST_BLOCK_SIZE 0x0194 +#define NVC597_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC597_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC597_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC597_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC597_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC597_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC597_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC597_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC597_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC597_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC597_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC597_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC597_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC597_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC597_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC597_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC597_SET_DST_WIDTH 0x0198 +#define NVC597_SET_DST_WIDTH_V 31:0 + +#define NVC597_SET_DST_HEIGHT 0x019c +#define NVC597_SET_DST_HEIGHT_V 31:0 + +#define NVC597_SET_DST_DEPTH 0x01a0 +#define NVC597_SET_DST_DEPTH_V 31:0 + +#define NVC597_SET_DST_LAYER 0x01a4 +#define NVC597_SET_DST_LAYER_V 31:0 + +#define NVC597_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC597_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC597_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC597_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC597_LAUNCH_DMA 0x01b0 +#define NVC597_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC597_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC597_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC597_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC597_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC597_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC597_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC597_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC597_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC597_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC597_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC597_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC597_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC597_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC597_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC597_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC597_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC597_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC597_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC597_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC597_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC597_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC597_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC597_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC597_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC597_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC597_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC597_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC597_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC597_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC597_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC597_LOAD_INLINE_DATA 0x01b4 +#define NVC597_LOAD_INLINE_DATA_V 31:0 + +#define NVC597_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC597_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC597_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC597_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC597_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC597_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC597_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC597_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC597_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC597_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC597_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC597_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC597_RUN_DS_NOW 0x0200 +#define NVC597_RUN_DS_NOW_V 31:0 + +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVC597_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVC597_SET_GS_MODE 0x0208 +#define NVC597_SET_GS_MODE_TYPE 0:0 +#define NVC597_SET_GS_MODE_TYPE_ANY 0x00000000 +#define NVC597_SET_GS_MODE_TYPE_FAST_GS 0x00000001 + +#define NVC597_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVC597_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVC597_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVC597_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVC597_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVC597_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVC597_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVC597_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_GS_DM_FIFO 0x0214 +#define NVC597_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVC597_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVC597_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVC597_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVC597_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC597_INVALIDATE_SHADER_CACHES 0x021c +#define NVC597_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC597_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC597_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC597_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC597_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC597_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC597_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC597_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC597_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC597_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC597_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC597_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC597_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC597_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC597_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC597_SET_INSTANCE_COUNT 0x0220 +#define NVC597_SET_INSTANCE_COUNT_V 31:0 + +#define NVC597_SET_POSITION_W_SCALED_OFFSET_ENABLE 0x0224 +#define NVC597_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE 0:0 +#define NVC597_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_GO_IDLE_TIMEOUT 0x022c +#define NVC597_SET_GO_IDLE_TIMEOUT_V 31:0 + +#define NVC597_SET_MME_VERSION 0x0234 +#define NVC597_SET_MME_VERSION_MAJOR 7:0 + +#define NVC597_SET_INDEX_BUFFER_SIZE_A 0x0238 +#define NVC597_SET_INDEX_BUFFER_SIZE_A_UPPER 7:0 + +#define NVC597_SET_INDEX_BUFFER_SIZE_B 0x023c +#define NVC597_SET_INDEX_BUFFER_SIZE_B_LOWER 31:0 + +#define NVC597_SET_ROOT_TABLE_VISIBILITY(i) (0x0240+(i)*4) +#define NVC597_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP0_ENABLE 1:0 +#define NVC597_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP1_ENABLE 5:4 +#define NVC597_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP2_ENABLE 9:8 +#define NVC597_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP3_ENABLE 13:12 +#define NVC597_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP4_ENABLE 17:16 + +#define NVC597_SET_DRAW_CONTROL_A 0x0260 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY 3:0 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_POINTS 0x00000000 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_LINES 0x00000001 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_QUADS 0x00000007 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_SET_DRAW_CONTROL_A_TOPOLOGY_PATCH 0x0000000E +#define NVC597_SET_DRAW_CONTROL_A_PRIMITIVE_ID 4:4 +#define NVC597_SET_DRAW_CONTROL_A_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC597_SET_DRAW_CONTROL_A_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC597_SET_DRAW_CONTROL_A_INSTANCE_ID 6:5 +#define NVC597_SET_DRAW_CONTROL_A_INSTANCE_ID_FIRST 0x00000000 +#define NVC597_SET_DRAW_CONTROL_A_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC597_SET_DRAW_CONTROL_A_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC597_SET_DRAW_CONTROL_A_SPLIT_MODE 8:7 +#define NVC597_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC597_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC597_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC597_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC597_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE 9:9 +#define NVC597_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 +#define NVC597_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX 10:10 +#define NVC597_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_FALSE 0x00000000 +#define NVC597_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_TRUE 0x00000001 +#define NVC597_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX 11:11 +#define NVC597_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_FALSE 0x00000000 +#define NVC597_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_TRUE 0x00000001 + +#define NVC597_SET_DRAW_CONTROL_B 0x0264 +#define NVC597_SET_DRAW_CONTROL_B_INSTANCE_COUNT 31:0 + +#define NVC597_DRAW_INDEX_BUFFER_BEGIN_END_A 0x0268 +#define NVC597_DRAW_INDEX_BUFFER_BEGIN_END_A_FIRST 31:0 + +#define NVC597_DRAW_INDEX_BUFFER_BEGIN_END_B 0x026c +#define NVC597_DRAW_INDEX_BUFFER_BEGIN_END_B_COUNT 31:0 + +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_A 0x0270 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_A_START 31:0 + +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_B 0x0274 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_B_COUNT 31:0 + +#define NVC597_INVALIDATE_RASTER_CACHE_NO_WFI 0x027c +#define NVC597_INVALIDATE_RASTER_CACHE_NO_WFI_V 0:0 + +#define NVC597_SET_COLOR_RENDER_TO_ZETA_SURFACE 0x02b8 +#define NVC597_SET_COLOR_RENDER_TO_ZETA_SURFACE_V 0:0 +#define NVC597_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_FALSE 0x00000000 +#define NVC597_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_TRUE 0x00000001 + +#define NVC597_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION 0x02bc +#define NVC597_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V 0:0 +#define NVC597_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_FALSE 0x00000000 +#define NVC597_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_TRUE 0x00000001 + +#define NVC597_INCREMENT_SYNC_POINT 0x02c8 +#define NVC597_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVC597_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVC597_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVC597_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVC597_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVC597_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVC597_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVC597_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVC597_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVC597_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC597_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVC597_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVC597_DECOMPRESS_SURFACE 0x02e0 +#define NVC597_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVC597_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVC597_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVC597_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVC597_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVC597_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVC597_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVC597_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVC597_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVC597_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVC597_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVC597_SET_ZCULL_SUBREGION 0x02e8 +#define NVC597_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVC597_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVC597_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVC597_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVC597_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVC597_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVC597_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVC597_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVC597_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVC597_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVC597_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVC597_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVC597_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVC597_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVC597_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVC597_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVC597_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVC597_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVC597_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVC597_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVC597_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVC597_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVC597_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVC597_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVC597_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC597_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVC597_DRAW_ZERO_INDEX 0x0304 +#define NVC597_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVC597_SET_L1_CONFIGURATION 0x0308 +#define NVC597_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVC597_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC597_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVC597_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVC597_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVC597_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVC597_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVC597_SET_SPA_VERSION 0x0310 +#define NVC597_SET_SPA_VERSION_MINOR 7:0 +#define NVC597_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC597_SET_TIMESLICE_BATCH_LIMIT 0x0314 +#define NVC597_SET_TIMESLICE_BATCH_LIMIT_BATCH_LIMIT 15:0 + +#define NVC597_SET_SNAP_GRID_LINE 0x0318 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC597_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC597_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVC597_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC597_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC597_SET_SNAP_GRID_NON_LINE 0x031c +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC597_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC597_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVC597_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC597_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC597_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVC597_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVC597_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVC597_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVC597_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVC597_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVC597_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVC597_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVC597_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVC597_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVC597_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVC597_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVC597_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVC597_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVC597_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVC597_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVC597_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVC597_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVC597_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVC597_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVC597_SET_TESSELLATION_LOD_V1 0x0330 +#define NVC597_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVC597_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVC597_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVC597_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVC597_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVC597_RESERVED_TG07 0x033c +#define NVC597_RESERVED_TG07_V 0:0 + +#define NVC597_RESERVED_TG08 0x0340 +#define NVC597_RESERVED_TG08_V 0:0 + +#define NVC597_RESERVED_TG09 0x0344 +#define NVC597_RESERVED_TG09_V 0:0 + +#define NVC597_RESERVED_TG10 0x0348 +#define NVC597_RESERVED_TG10_V 0:0 + +#define NVC597_RESERVED_TG11 0x034c +#define NVC597_RESERVED_TG11_V 0:0 + +#define NVC597_RESERVED_TG12 0x0350 +#define NVC597_RESERVED_TG12_V 0:0 + +#define NVC597_RESERVED_TG13 0x0354 +#define NVC597_RESERVED_TG13_V 0:0 + +#define NVC597_RESERVED_TG14 0x0358 +#define NVC597_RESERVED_TG14_V 0:0 + +#define NVC597_RESERVED_TG15 0x035c +#define NVC597_RESERVED_TG15_V 0:0 + +#define NVC597_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVC597_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVC597_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVC597_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVC597_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVC597_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVC597_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVC597_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVC597_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVC597_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVC597_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVC597_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVC597_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE 8:8 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE 9:9 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC597_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVC597_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVC597_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVC597_SET_RASTER_ENABLE 0x037c +#define NVC597_SET_RASTER_ENABLE_V 0:0 +#define NVC597_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVC597_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVC597_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVC597_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVC597_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVC597_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVC597_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVC597_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVC597_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVC597_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVC597_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVC597_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVC597_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVC597_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVC597_SET_POSITION_W_SCALED_OFFSET_SCALE_A(j) (0x0400+(j)*16) +#define NVC597_SET_POSITION_W_SCALED_OFFSET_SCALE_A_V 31:0 + +#define NVC597_SET_POSITION_W_SCALED_OFFSET_SCALE_B(j) (0x0404+(j)*16) +#define NVC597_SET_POSITION_W_SCALED_OFFSET_SCALE_B_V 31:0 + +#define NVC597_SET_POSITION_W_SCALED_OFFSET_RESERVED_A(j) (0x0408+(j)*16) +#define NVC597_SET_POSITION_W_SCALED_OFFSET_RESERVED_A_V 31:0 + +#define NVC597_SET_POSITION_W_SCALED_OFFSET_RESERVED_B(j) (0x040c+(j)*16) +#define NVC597_SET_POSITION_W_SCALED_OFFSET_RESERVED_B_V 31:0 + +#define NVC597_SET_ROOT_TABLE_SELECTOR 0x0504 +#define NVC597_SET_ROOT_TABLE_SELECTOR_ROOT_TABLE 2:0 +#define NVC597_SET_ROOT_TABLE_SELECTOR_OFFSET 15:8 + +#define NVC597_LOAD_ROOT_TABLE 0x0508 +#define NVC597_LOAD_ROOT_TABLE_V 31:0 + +#define NVC597_SET_MME_MEM_ADDRESS_A 0x0550 +#define NVC597_SET_MME_MEM_ADDRESS_A_UPPER 7:0 + +#define NVC597_SET_MME_MEM_ADDRESS_B 0x0554 +#define NVC597_SET_MME_MEM_ADDRESS_B_LOWER 31:0 + +#define NVC597_SET_MME_DATA_RAM_ADDRESS 0x0558 +#define NVC597_SET_MME_DATA_RAM_ADDRESS_WORD 31:0 + +#define NVC597_MME_DMA_READ 0x055c +#define NVC597_MME_DMA_READ_LENGTH 31:0 + +#define NVC597_MME_DMA_READ_FIFOED 0x0560 +#define NVC597_MME_DMA_READ_FIFOED_LENGTH 31:0 + +#define NVC597_MME_DMA_WRITE 0x0564 +#define NVC597_MME_DMA_WRITE_LENGTH 31:0 + +#define NVC597_MME_DMA_REDUCTION 0x0568 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP 2:0 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP_RED_INC 0x00000003 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP_RED_AND 0x00000005 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP_RED_OR 0x00000006 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_FORMAT 5:4 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_SIZE 8:8 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_SIZE_FOUR_BYTES 0x00000000 +#define NVC597_MME_DMA_REDUCTION_REDUCTION_SIZE_EIGHT_BYTES 0x00000001 + +#define NVC597_MME_DMA_SYSMEMBAR 0x056c +#define NVC597_MME_DMA_SYSMEMBAR_V 0:0 + +#define NVC597_MME_DMA_SYNC 0x0570 +#define NVC597_MME_DMA_SYNC_VALUE 31:0 + +#define NVC597_SET_MME_DATA_FIFO_CONFIG 0x0574 +#define NVC597_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE 2:0 +#define NVC597_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_0KB 0x00000000 +#define NVC597_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_4KB 0x00000001 +#define NVC597_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_8KB 0x00000002 +#define NVC597_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_12KB 0x00000003 +#define NVC597_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_16KB 0x00000004 + +#define NVC597_SET_VERTEX_STREAM_SIZE_A(j) (0x0600+(j)*8) +#define NVC597_SET_VERTEX_STREAM_SIZE_A_UPPER 7:0 + +#define NVC597_SET_VERTEX_STREAM_SIZE_B(j) (0x0604+(j)*8) +#define NVC597_SET_VERTEX_STREAM_SIZE_B_LOWER 31:0 + +#define NVC597_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVC597_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVC597_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVC597_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVC597_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVC597_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVC597_SET_RASTER_INPUT 0x0740 +#define NVC597_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVC597_SET_STREAM_OUTPUT 0x0744 +#define NVC597_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVC597_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVC597_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVC597_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVC597_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVC597_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVC597_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVC597_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVC597_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVC597_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC597_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC597_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC597_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVC597_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC597_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC597_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVC597_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVC597_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVC597_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVC597_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVC597_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVC597_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVC597_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC597_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVC597_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC597_SET_STENCIL_ZERO_BANDWIDTH_CLEAR 0x07b0 +#define NVC597_SET_STENCIL_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC597_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVC597_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVC597_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVC597_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVC597_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVC597_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVC597_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVC597_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVC597_SET_CULL_BEFORE_FETCH 0x07dc +#define NVC597_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVC597_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVC597_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVC597_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVC597_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVC597_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVC597_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVC597_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVC597_SET_ZCULL_STORAGE_A 0x07e8 +#define NVC597_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVC597_SET_ZCULL_STORAGE_B 0x07ec +#define NVC597_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVC597_SET_ZCULL_STORAGE_C 0x07f0 +#define NVC597_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC597_SET_ZCULL_STORAGE_D 0x07f4 +#define NVC597_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC597_SET_ZT_READ_ONLY 0x07f8 +#define NVC597_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVC597_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVC597_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVC597_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVC597_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVC597_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVC597_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVC597_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVC597_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVC597_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVC597_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVC597_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVC597_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVC597_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVC597_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVC597_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVC597_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVC597_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVC597_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVC597_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVC597_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVC597_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVC597_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVC597_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVC597_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVC597_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC597_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC597_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVC597_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC597_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC597_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVC597_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC597_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVC597_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVC597_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVC597_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVC597_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVC597_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVC597_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVC597_SET_COLOR_TARGET_RESERVED_A(j) (0x0824+(j)*64) +#define NVC597_SET_COLOR_TARGET_RESERVED_A_V 0:0 + +#define NVC597_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVC597_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVC597_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVC597_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVC597_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVC597_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVC597_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVC597_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVC597_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVC597_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVC597_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVC597_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVC597_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVC597_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVC597_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVC597_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVC597_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVC597_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVC597_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC597_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVC597_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVC597_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC597_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVC597_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVC597_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVC597_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVC597_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVC597_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVC597_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVC597_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVC597_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVC597_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVC597_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVC597_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVC597_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVC597_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVC597_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVC597_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVC597_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVC597_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC597_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVC597_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVC597_SET_STATISTICS_COUNTER 0x0d68 +#define NVC597_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVC597_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVC597_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVC597_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVC597_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVC597_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVC597_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVC597_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVC597_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVC597_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVC597_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVC597_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVC597_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVC597_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVC597_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVC597_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVC597_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 +#define NVC597_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE 16:16 +#define NVC597_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVC597_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC597_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC597_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVC597_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC597_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC597_SET_VERTEX_ARRAY_START 0x0d74 +#define NVC597_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVC597_DRAW_VERTEX_ARRAY 0x0d78 +#define NVC597_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVC597_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVC597_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVC597_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVC597_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVC597_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVC597_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVC597_SET_Z_CLEAR_VALUE 0x0d90 +#define NVC597_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVC597_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC597_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC597_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC597_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVC597_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVC597_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVC597_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC597_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC597_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVC597_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVC597_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVC597_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVC597_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVC597_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVC597_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVC597_SET_FRONT_POLYGON_MODE 0x0dac +#define NVC597_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVC597_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC597_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC597_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC597_SET_BACK_POLYGON_MODE 0x0db0 +#define NVC597_SET_BACK_POLYGON_MODE_V 31:0 +#define NVC597_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC597_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC597_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC597_SET_POLY_SMOOTH 0x0db4 +#define NVC597_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVC597_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVC597_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVC597_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVC597_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVC597_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVC597_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVC597_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVC597_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVC597_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVC597_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVC597_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVC597_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVC597_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVC597_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVC597_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVC597_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVC597_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVC597_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_PATCH 0x0dcc +#define NVC597_SET_PATCH_SIZE 7:0 + +#define NVC597_SET_ITERATED_BLEND 0x0dd0 +#define NVC597_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVC597_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVC597_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVC597_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVC597_SET_ZCULL_CRITERION 0x0dd8 +#define NVC597_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVC597_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVC597_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVC597_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVC597_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVC597_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVC597_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVC597_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVC597_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVC597_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVC597_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVC597_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVC597_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVC597_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVC597_SET_ZCULL_CRITERION_SREF 23:16 +#define NVC597_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVC597_PIXEL_SHADER_BARRIER 0x0de0 +#define NVC597_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVC597_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVC597_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC597_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC597_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVC597_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVC597_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVC597_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVC597_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVC597_SET_WINDOW_OFFSET_X 0x0df8 +#define NVC597_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVC597_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVC597_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVC597_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVC597_SET_SCISSOR_ENABLE_V 0:0 +#define NVC597_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVC597_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVC597_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVC597_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVC597_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVC597_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVC597_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVC597_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVC597_SET_VPC_PERF_KNOB 0x0f14 +#define NVC597_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVC597_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVC597_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVC597_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVC597_PM_LOCAL_TRIGGER 0x0f18 +#define NVC597_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVC597_SET_POST_Z_PS_IMASK 0x0f1c +#define NVC597_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVC597_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVC597_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVC597_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVC597_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVC597_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVC597_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVC597_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVC597_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVC597_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVC597_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVC597_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVC597_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVC597_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVC597_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVC597_SET_BACK_STENCIL_MASK 0x0f58 +#define NVC597_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVC597_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVC597_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVC597_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVC597_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVC597_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVC597_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVC597_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVC597_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVC597_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVC597_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVC597_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVC597_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVC597_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVC597_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVC597_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVC597_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVC597_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVC597_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVC597_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVC597_SET_SAMPLE_MASK 0x0fa4 +#define NVC597_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVC597_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVC597_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVC597_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVC597_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVC597_SET_CT_MRT_ENABLE 0x0fac +#define NVC597_SET_CT_MRT_ENABLE_V 0:0 +#define NVC597_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVC597_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVC597_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVC597_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVC597_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVC597_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVC597_SET_TIR 0x0fb4 +#define NVC597_SET_TIR_MODE 1:0 +#define NVC597_SET_TIR_MODE_DISABLED 0x00000000 +#define NVC597_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVC597_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVC597_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVC597_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVC597_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVC597_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC597_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC597_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVC597_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVC597_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVC597_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVC597_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVC597_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVC597_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVC597_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVC597_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVC597_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVC597_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVC597_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_TIR_MODULATION 0x0fd4 +#define NVC597_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVC597_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVC597_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVC597_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVC597_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVC597_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVC597_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVC597_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVC597_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVC597_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVC597_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVC597_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVC597_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVC597_SET_ZT_A 0x0fe0 +#define NVC597_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_ZT_B 0x0fe4 +#define NVC597_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_ZT_FORMAT 0x0fe8 +#define NVC597_SET_ZT_FORMAT_V 4:0 +#define NVC597_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVC597_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVC597_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVC597_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVC597_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVC597_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVC597_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVC597_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVC597_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVC597_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVC597_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVC597_SET_ZT_BLOCK_SIZE 0x0fec +#define NVC597_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVC597_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC597_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVC597_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC597_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC597_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC597_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC597_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC597_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC597_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVC597_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC597_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVC597_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVC597_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVC597_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVC597_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC597_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVC597_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVC597_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC597_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC597_SET_VIEWPORT_MULTICAST 0x1004 +#define NVC597_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVC597_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVC597_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVC597_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVC597_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVC597_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVC597_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC597_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVC597_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVC597_SET_RESERVED_SW_METHOD00 0x1014 +#define NVC597_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC597_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVC597_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC597_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVC597_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC597_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVC597_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC597_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVC597_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC597_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_RESERVED_SW_METHOD01 0x1028 +#define NVC597_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD02 0x102c +#define NVC597_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC597_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVC597_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVC597_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVC597_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVC597_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVC597_SET_SPARE_NOOP01 0x1044 +#define NVC597_SET_SPARE_NOOP01_V 31:0 + +#define NVC597_SET_SPARE_NOOP02 0x1048 +#define NVC597_SET_SPARE_NOOP02_V 31:0 + +#define NVC597_SET_SPARE_NOOP03 0x104c +#define NVC597_SET_SPARE_NOOP03_V 31:0 + +#define NVC597_SET_SPARE_NOOP04 0x1050 +#define NVC597_SET_SPARE_NOOP04_V 31:0 + +#define NVC597_SET_SPARE_NOOP05 0x1054 +#define NVC597_SET_SPARE_NOOP05_V 31:0 + +#define NVC597_SET_SPARE_NOOP06 0x1058 +#define NVC597_SET_SPARE_NOOP06_V 31:0 + +#define NVC597_SET_SPARE_NOOP07 0x105c +#define NVC597_SET_SPARE_NOOP07_V 31:0 + +#define NVC597_SET_SPARE_NOOP08 0x1060 +#define NVC597_SET_SPARE_NOOP08_V 31:0 + +#define NVC597_SET_SPARE_NOOP09 0x1064 +#define NVC597_SET_SPARE_NOOP09_V 31:0 + +#define NVC597_SET_SPARE_NOOP10 0x1068 +#define NVC597_SET_SPARE_NOOP10_V 31:0 + +#define NVC597_SET_SPARE_NOOP11 0x106c +#define NVC597_SET_SPARE_NOOP11_V 31:0 + +#define NVC597_SET_SPARE_NOOP12 0x1070 +#define NVC597_SET_SPARE_NOOP12_V 31:0 + +#define NVC597_SET_SPARE_NOOP13 0x1074 +#define NVC597_SET_SPARE_NOOP13_V 31:0 + +#define NVC597_SET_SPARE_NOOP14 0x1078 +#define NVC597_SET_SPARE_NOOP14_V 31:0 + +#define NVC597_SET_SPARE_NOOP15 0x107c +#define NVC597_SET_SPARE_NOOP15_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVC597_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVC597_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVC597_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD06 0x10bc +#define NVC597_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVC597_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVC597_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVC597_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVC597_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVC597_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVC597_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVC597_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD13 0x10dc +#define NVC597_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC597_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVC597_UNBIND_ALL 0x10f4 +#define NVC597_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVC597_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVC597_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVC597_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVC597_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC597_SET_RESERVED_SW_METHOD14 0x1100 +#define NVC597_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC597_SET_RESERVED_SW_METHOD15 0x1104 +#define NVC597_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC597_NO_OPERATION_DATA_HI 0x110c +#define NVC597_NO_OPERATION_DATA_HI_V 31:0 + +#define NVC597_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVC597_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVC597_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVC597_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVC597_PM_TRIGGER_END 0x1114 +#define NVC597_PM_TRIGGER_END_V 31:0 + +#define NVC597_SET_VERTEX_ID_BASE 0x1118 +#define NVC597_SET_VERTEX_ID_BASE_V 31:0 + +#define NVC597_SET_STENCIL_COMPRESSION 0x111c +#define NVC597_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVC597_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC597_SET_TIR_CONTROL 0x1130 +#define NVC597_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVC597_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC597_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC597_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVC597_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC597_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC597_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVC597_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVC597_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 + +#define NVC597_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVC597_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVC597_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVC597_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVC597_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVC597_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVC597_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVC597_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVC597_SET_FILL_VIA_TRIANGLE 0x113c +#define NVC597_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVC597_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVC597_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVC597_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVC597_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVC597_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVC597_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVC597_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVC597_FLUSH_PENDING_WRITES 0x1144 +#define NVC597_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVC597_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVC597_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC597_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC597_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC597_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVC597_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC597_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC597_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVC597_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVC597_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVC597_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVC597_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVC597_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVC597_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVC597_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVC597_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVC597_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVC597_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVC597_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVC597_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVC597_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVC597_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVC597_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC597_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC597_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVC597_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC597_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_SCREEN_STATE_MASK 0x1204 +#define NVC597_SET_SCREEN_STATE_MASK_MASK 3:0 + +#define NVC597_SET_ZT_SPARSE 0x1208 +#define NVC597_SET_ZT_SPARSE_ENABLE 0:0 +#define NVC597_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVC597_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVC597_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC597_SET_CT_SELECT 0x121c +#define NVC597_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVC597_SET_CT_SELECT_TARGET0 6:4 +#define NVC597_SET_CT_SELECT_TARGET1 9:7 +#define NVC597_SET_CT_SELECT_TARGET2 12:10 +#define NVC597_SET_CT_SELECT_TARGET3 15:13 +#define NVC597_SET_CT_SELECT_TARGET4 18:16 +#define NVC597_SET_CT_SELECT_TARGET5 21:19 +#define NVC597_SET_CT_SELECT_TARGET6 24:22 +#define NVC597_SET_CT_SELECT_TARGET7 27:25 + +#define NVC597_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVC597_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVC597_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVC597_SET_ZT_SIZE_A 0x1228 +#define NVC597_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVC597_SET_ZT_SIZE_B 0x122c +#define NVC597_SET_ZT_SIZE_B_HEIGHT 17:0 + +#define NVC597_SET_ZT_SIZE_C 0x1230 +#define NVC597_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVC597_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVC597_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC597_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVC597_SET_SAMPLER_BINDING 0x1234 +#define NVC597_SET_SAMPLER_BINDING_V 0:0 +#define NVC597_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVC597_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVC597_DRAW_AUTO 0x123c +#define NVC597_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVC597_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVC597_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVC597_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVC597_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVC597_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVC597_SET_BACK_END_COPY_A 0x1264 +#define NVC597_SET_BACK_END_COPY_A_DWORDS 7:0 +#define NVC597_SET_BACK_END_COPY_A_SATURATE32_ENABLE 8:8 +#define NVC597_SET_BACK_END_COPY_A_SATURATE32_ENABLE_FALSE 0x00000000 +#define NVC597_SET_BACK_END_COPY_A_SATURATE32_ENABLE_TRUE 0x00000001 +#define NVC597_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE 12:12 +#define NVC597_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_FALSE 0x00000000 +#define NVC597_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_BACK_END_COPY_B 0x1268 +#define NVC597_SET_BACK_END_COPY_B_SRC_ADDRESS_UPPER 7:0 + +#define NVC597_SET_BACK_END_COPY_C 0x126c +#define NVC597_SET_BACK_END_COPY_C_SRC_ADDRESS_LOWER 31:0 + +#define NVC597_SET_BACK_END_COPY_D 0x1270 +#define NVC597_SET_BACK_END_COPY_D_DEST_ADDRESS_UPPER 7:0 + +#define NVC597_SET_BACK_END_COPY_E 0x1274 +#define NVC597_SET_BACK_END_COPY_E_DEST_ADDRESS_LOWER 31:0 + +#define NVC597_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVC597_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 19:0 + +#define NVC597_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVC597_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVC597_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC597_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVC597_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVC597_CLEAR_ZCULL_REGION 0x12c8 +#define NVC597_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVC597_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVC597_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVC597_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVC597_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC597_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC597_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVC597_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC597_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC597_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVC597_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVC597_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVC597_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVC597_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVC597_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVC597_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVC597_SET_DEPTH_TEST 0x12cc +#define NVC597_SET_DEPTH_TEST_ENABLE 0:0 +#define NVC597_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVC597_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_FILL_MODE 0x12d0 +#define NVC597_SET_FILL_MODE_V 31:0 +#define NVC597_SET_FILL_MODE_V_POINT 0x00000001 +#define NVC597_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVC597_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVC597_SET_SHADE_MODE 0x12d4 +#define NVC597_SET_SHADE_MODE_V 31:0 +#define NVC597_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVC597_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVC597_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVC597_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC597_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC597_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVC597_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVC597_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVC597_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVC597_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVC597_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVC597_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVC597_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVC597_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_DEPTH_WRITE 0x12e8 +#define NVC597_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVC597_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_ALPHA_TEST 0x12ec +#define NVC597_SET_ALPHA_TEST_ENABLE 0:0 +#define NVC597_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVC597_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVC597_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVC597_DRAW_INLINE_INDEX4X8 0x1304 +#define NVC597_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVC597_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVC597_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVC597_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVC597_D3D_SET_CULL_MODE 0x1308 +#define NVC597_D3D_SET_CULL_MODE_V 31:0 +#define NVC597_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVC597_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVC597_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVC597_SET_DEPTH_FUNC 0x130c +#define NVC597_SET_DEPTH_FUNC_V 31:0 +#define NVC597_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVC597_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVC597_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC597_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC597_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVC597_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC597_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC597_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC597_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVC597_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVC597_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC597_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC597_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVC597_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC597_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC597_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC597_SET_ALPHA_REF 0x1310 +#define NVC597_SET_ALPHA_REF_V 31:0 + +#define NVC597_SET_ALPHA_FUNC 0x1314 +#define NVC597_SET_ALPHA_FUNC_V 31:0 +#define NVC597_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVC597_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVC597_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC597_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC597_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVC597_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC597_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC597_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC597_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVC597_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVC597_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC597_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC597_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVC597_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC597_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC597_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC597_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVC597_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVC597_SET_BLEND_CONST_RED 0x131c +#define NVC597_SET_BLEND_CONST_RED_V 31:0 + +#define NVC597_SET_BLEND_CONST_GREEN 0x1320 +#define NVC597_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVC597_SET_BLEND_CONST_BLUE 0x1324 +#define NVC597_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVC597_SET_BLEND_CONST_ALPHA 0x1328 +#define NVC597_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVC597_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC597_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC597_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC597_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC597_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC597_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC597_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVC597_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC597_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC597_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_BLEND_COLOR_OP 0x1340 +#define NVC597_SET_BLEND_COLOR_OP_V 31:0 +#define NVC597_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC597_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC597_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC597_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC597_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC597_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC597_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC597_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC597_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC597_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC597_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC597_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC597_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC597_SET_BLEND_ALPHA_OP 0x134c +#define NVC597_SET_BLEND_ALPHA_OP_V 31:0 +#define NVC597_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC597_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC597_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC597_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC597_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC597_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC597_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC597_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC597_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC597_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC597_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC597_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVC597_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVC597_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVC597_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC597_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC597_SET_SINGLE_ROP_CONTROL 0x135c +#define NVC597_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVC597_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_BLEND(i) (0x1360+(i)*4) +#define NVC597_SET_BLEND_ENABLE 0:0 +#define NVC597_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVC597_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_STENCIL_TEST 0x1380 +#define NVC597_SET_STENCIL_TEST_ENABLE 0:0 +#define NVC597_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC597_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_STENCIL_OP_FAIL 0x1384 +#define NVC597_SET_STENCIL_OP_FAIL_V 31:0 +#define NVC597_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC597_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC597_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC597_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC597_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC597_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC597_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC597_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC597_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC597_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC597_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC597_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC597_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC597_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC597_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC597_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC597_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVC597_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC597_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC597_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC597_SET_STENCIL_OP_ZPASS 0x138c +#define NVC597_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVC597_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC597_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC597_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC597_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC597_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC597_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC597_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC597_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC597_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC597_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC597_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC597_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC597_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC597_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC597_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC597_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC597_SET_STENCIL_FUNC 0x1390 +#define NVC597_SET_STENCIL_FUNC_V 31:0 +#define NVC597_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC597_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC597_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC597_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC597_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC597_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC597_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC597_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC597_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC597_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC597_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC597_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC597_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC597_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC597_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC597_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC597_SET_STENCIL_FUNC_REF 0x1394 +#define NVC597_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVC597_SET_STENCIL_FUNC_MASK 0x1398 +#define NVC597_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVC597_SET_STENCIL_MASK 0x139c +#define NVC597_SET_STENCIL_MASK_V 7:0 + +#define NVC597_SET_DRAW_AUTO_START 0x13a4 +#define NVC597_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVC597_SET_PS_SATURATE 0x13a8 +#define NVC597_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVC597_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVC597_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC597_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVC597_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVC597_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC597_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVC597_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVC597_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC597_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVC597_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVC597_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC597_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVC597_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVC597_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC597_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVC597_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVC597_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC597_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVC597_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVC597_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC597_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVC597_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVC597_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC597_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVC597_SET_WINDOW_ORIGIN 0x13ac +#define NVC597_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVC597_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVC597_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVC597_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVC597_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVC597_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVC597_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVC597_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC597_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVC597_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC597_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVC597_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVC597_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVC597_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC597_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC597_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC597_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC597_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC597_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC597_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVC597_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVC597_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVC597_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVC597_SET_PS_WARP_WATERMARKS 0x1450 +#define NVC597_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVC597_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVC597_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVC597_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVC597_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC597_STORE_ZCULL 0x1464 +#define NVC597_STORE_ZCULL_V 0:0 + +#define NVC597_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVC597_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVC597_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVC597_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVC597_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVC597_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVC597_LOAD_ZCULL 0x1500 +#define NVC597_LOAD_ZCULL_V 0:0 + +#define NVC597_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVC597_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVC597_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVC597_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC597_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC597_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVC597_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC597_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC597_SET_USER_CLIP_ENABLE 0x1510 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVC597_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVC597_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVC597_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVC597_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_POINT_SIZE 0x1518 +#define NVC597_SET_POINT_SIZE_V 31:0 + +#define NVC597_SET_ZCULL_STATS 0x151c +#define NVC597_SET_ZCULL_STATS_ENABLE 0:0 +#define NVC597_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_POINT_SPRITE 0x1520 +#define NVC597_SET_POINT_SPRITE_ENABLE 0:0 +#define NVC597_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC597_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC597_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC597_CLEAR_REPORT_VALUE 0x1530 +#define NVC597_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVC597_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVC597_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVC597_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVC597_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVC597_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVC597_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC597_CLEAR_REPORT_VALUE_TYPE_SCG_CLOCKS 0x00000009 + +#define NVC597_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVC597_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVC597_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVC597_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVC597_SET_ZT_SELECT 0x1538 +#define NVC597_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVC597_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVC597_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVC597_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVC597_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVC597_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVC597_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVC597_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVC597_SET_RENDER_ENABLE_A 0x1550 +#define NVC597_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_RENDER_ENABLE_B 0x1554 +#define NVC597_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_RENDER_ENABLE_C 0x1558 +#define NVC597_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC597_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC597_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC597_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC597_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC597_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC597_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC597_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC597_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC597_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC597_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVC597_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVC597_SET_ANTI_ALIASED_LINE 0x1570 +#define NVC597_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVC597_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC597_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC597_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_TEX_HEADER_POOL_C 0x157c +#define NVC597_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC597_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVC597_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVC597_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVC597_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVC597_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC597_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC597_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC597_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC597_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC597_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC597_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVC597_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVC597_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC597_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC597_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC597_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC597_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC597_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC597_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC597_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC597_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC597_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC597_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC597_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC597_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC597_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC597_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC597_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC597_SET_SRGB_WRITE 0x15b8 +#define NVC597_SET_SRGB_WRITE_ENABLE 0:0 +#define NVC597_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_DEPTH_BIAS 0x15bc +#define NVC597_SET_DEPTH_BIAS_V 31:0 + +#define NVC597_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVC597_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVC597_SET_RT_LAYER 0x15cc +#define NVC597_SET_RT_LAYER_V 15:0 +#define NVC597_SET_RT_LAYER_CONTROL 16:16 +#define NVC597_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVC597_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVC597_SET_ANTI_ALIAS 0x15d0 +#define NVC597_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVC597_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVC597_SET_EDGE_FLAG 0x15e4 +#define NVC597_SET_EDGE_FLAG_V 0:0 +#define NVC597_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVC597_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVC597_DRAW_INLINE_INDEX 0x15e8 +#define NVC597_DRAW_INLINE_INDEX_V 31:0 + +#define NVC597_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVC597_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVC597_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVC597_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVC597_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVC597_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVC597_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVC597_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVC597_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVC597_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVC597_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVC597_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVC597_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVC597_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVC597_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVC597_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVC597_SET_POINT_SPRITE_SELECT 0x1604 +#define NVC597_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVC597_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVC597_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVC597_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVC597_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVC597_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVC597_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVC597_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVC597_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVC597_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVC597_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVC597_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVC597_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVC597_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVC597_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVC597_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVC597_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVC597_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVC597_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVC597_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVC597_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVC597_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVC597_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVC597_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVC597_END 0x1614 +#define NVC597_END_V 0:0 + +#define NVC597_BEGIN 0x1618 +#define NVC597_BEGIN_OP 15:0 +#define NVC597_BEGIN_OP_POINTS 0x00000000 +#define NVC597_BEGIN_OP_LINES 0x00000001 +#define NVC597_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVC597_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVC597_BEGIN_OP_TRIANGLES 0x00000004 +#define NVC597_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVC597_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVC597_BEGIN_OP_QUADS 0x00000007 +#define NVC597_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVC597_BEGIN_OP_POLYGON 0x00000009 +#define NVC597_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVC597_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVC597_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_BEGIN_OP_PATCH 0x0000000E +#define NVC597_BEGIN_PRIMITIVE_ID 24:24 +#define NVC597_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC597_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC597_BEGIN_INSTANCE_ID 27:26 +#define NVC597_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVC597_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC597_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC597_BEGIN_SPLIT_MODE 30:29 +#define NVC597_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC597_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC597_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC597_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC597_BEGIN_INSTANCE_ITERATE_ENABLE 31:31 +#define NVC597_BEGIN_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC597_BEGIN_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_VERTEX_ID_COPY 0x161c +#define NVC597_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVC597_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVC597_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVC597_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVC597_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVC597_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVC597_LOAD_PRIMITIVE_ID 0x1624 +#define NVC597_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVC597_SET_SHADER_BASED_CULL 0x162c +#define NVC597_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVC597_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVC597_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVC597_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVC597_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_CLASS_VERSION 0x1638 +#define NVC597_SET_CLASS_VERSION_CURRENT 15:0 +#define NVC597_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC597_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVC597_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVC597_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVC597_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVC597_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVC597_SET_DA_OUTPUT 0x164c +#define NVC597_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVC597_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVC597_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVC597_SET_ANTI_ALIASED_POINT 0x1658 +#define NVC597_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVC597_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_POINT_CENTER_MODE 0x165c +#define NVC597_SET_POINT_CENTER_MODE_V 31:0 +#define NVC597_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVC597_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVC597_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVC597_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVC597_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVC597_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVC597_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVC597_SET_LINE_STIPPLE 0x166c +#define NVC597_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVC597_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVC597_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVC597_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVC597_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVC597_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVC597_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVC597_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVC597_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVC597_SET_PROVOKING_VERTEX 0x1684 +#define NVC597_SET_PROVOKING_VERTEX_V 0:0 +#define NVC597_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVC597_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVC597_SET_TWO_SIDED_LIGHT 0x1688 +#define NVC597_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVC597_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_POLYGON_STIPPLE 0x168c +#define NVC597_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVC597_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_SHADER_CONTROL 0x1690 +#define NVC597_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVC597_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVC597_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVC597_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVC597_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC597_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC597_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVC597_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC597_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVC597_CHECK_CLASS_VERSION 0x16a0 +#define NVC597_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVC597_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC597_SET_SPH_VERSION 0x16a4 +#define NVC597_SET_SPH_VERSION_CURRENT 15:0 +#define NVC597_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC597_CHECK_SPH_VERSION 0x16a8 +#define NVC597_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVC597_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC597_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVC597_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVC597_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC597_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVC597_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVC597_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVC597_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVC597_SET_SCG_GRAPHICS_PRIORITY 0x16bc +#define NVC597_SET_SCG_GRAPHICS_PRIORITY_PRIORITY 5:0 + +#define NVC597_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS(i) (0x16c0+(i)*4) +#define NVC597_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS_V 31:0 + +#define NVC597_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVC597_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVC597_SET_AAM_VERSION 0x1790 +#define NVC597_SET_AAM_VERSION_CURRENT 15:0 +#define NVC597_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC597_CHECK_AAM_VERSION 0x1794 +#define NVC597_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVC597_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC597_SET_ZT_LAYER 0x179c +#define NVC597_SET_ZT_LAYER_OFFSET 15:0 + +#define NVC597_SET_INDEX_BUFFER_A 0x17c8 +#define NVC597_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVC597_SET_INDEX_BUFFER_B 0x17cc +#define NVC597_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVC597_SET_INDEX_BUFFER_E 0x17d8 +#define NVC597_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVC597_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVC597_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVC597_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVC597_SET_INDEX_BUFFER_F 0x17dc +#define NVC597_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVC597_DRAW_INDEX_BUFFER 0x17e0 +#define NVC597_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC597_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVC597_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVC597_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVC597_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVC597_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVC597_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVC597_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVC597_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVC597_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVC597_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVC597_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVC597_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVC597_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVC597_OGL_SET_CULL 0x1918 +#define NVC597_OGL_SET_CULL_ENABLE 0:0 +#define NVC597_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVC597_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVC597_OGL_SET_FRONT_FACE 0x191c +#define NVC597_OGL_SET_FRONT_FACE_V 31:0 +#define NVC597_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVC597_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVC597_OGL_SET_CULL_FACE 0x1920 +#define NVC597_OGL_SET_CULL_FACE_V 31:0 +#define NVC597_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVC597_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVC597_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVC597_SET_VIEWPORT_PIXEL 0x1924 +#define NVC597_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVC597_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVC597_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVC597_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVC597_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVC597_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVC597_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE 17:16 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_USE_FIELD_MIN_Z_ZERO_MAX_Z_ONE 0x00000000 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MIN_Z_MAX_Z 0x00000001 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_ZERO_ONE 0x00000002 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MINUS_INF_PLUS_INF 0x00000003 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVC597_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVC597_SET_USER_CLIP_OP 0x1940 +#define NVC597_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVC597_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVC597_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVC597_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVC597_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVC597_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVC597_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVC597_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVC597_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVC597_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVC597_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVC597_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVC597_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVC597_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVC597_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVC597_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVC597_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVC597_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVC597_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVC597_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVC597_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVC597_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVC597_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVC597_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVC597_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC597_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC597_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC597_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC597_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC597_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVC597_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVC597_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVC597_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVC597_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVC597_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVC597_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVC597_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVC597_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVC597_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVC597_INVALIDATE_ZCULL 0x1958 +#define NVC597_INVALIDATE_ZCULL_V 31:0 +#define NVC597_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVC597_SET_ZCULL 0x1968 +#define NVC597_SET_ZCULL_Z_ENABLE 0:0 +#define NVC597_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVC597_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_ZCULL_BOUNDS 0x196c +#define NVC597_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVC597_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVC597_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVC597_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC597_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVC597_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVC597_ZCULL_SYNC 0x1978 +#define NVC597_ZCULL_SYNC_V 31:0 + +#define NVC597_SET_CLIP_ID_TEST 0x197c +#define NVC597_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVC597_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVC597_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVC597_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVC597_SET_CLIP_ID 0x1984 +#define NVC597_SET_CLIP_ID_V 31:0 + +#define NVC597_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVC597_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVC597_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVC597_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVC597_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVC597_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVC597_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVC597_SET_LOGIC_OP 0x19c4 +#define NVC597_SET_LOGIC_OP_ENABLE 0:0 +#define NVC597_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVC597_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_LOGIC_OP_FUNC 0x19c8 +#define NVC597_SET_LOGIC_OP_FUNC_V 31:0 +#define NVC597_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVC597_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVC597_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVC597_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVC597_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVC597_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVC597_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVC597_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVC597_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVC597_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVC597_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVC597_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVC597_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVC597_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVC597_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVC597_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVC597_SET_Z_COMPRESSION 0x19cc +#define NVC597_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVC597_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC597_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC597_CLEAR_SURFACE 0x19d0 +#define NVC597_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVC597_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC597_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC597_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVC597_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC597_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC597_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVC597_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVC597_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVC597_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVC597_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVC597_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVC597_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVC597_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVC597_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVC597_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVC597_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVC597_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVC597_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVC597_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVC597_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVC597_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVC597_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVC597_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVC597_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC597_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVC597_SET_CT_WRITE_R_ENABLE 0:0 +#define NVC597_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVC597_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVC597_SET_CT_WRITE_G_ENABLE 4:4 +#define NVC597_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVC597_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVC597_SET_CT_WRITE_B_ENABLE 8:8 +#define NVC597_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVC597_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVC597_SET_CT_WRITE_A_ENABLE 12:12 +#define NVC597_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVC597_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVC597_PIPE_NOP 0x1a2c +#define NVC597_PIPE_NOP_V 31:0 + +#define NVC597_SET_SPARE00 0x1a30 +#define NVC597_SET_SPARE00_V 31:0 + +#define NVC597_SET_SPARE01 0x1a34 +#define NVC597_SET_SPARE01_V 31:0 + +#define NVC597_SET_SPARE02 0x1a38 +#define NVC597_SET_SPARE02_V 31:0 + +#define NVC597_SET_SPARE03 0x1a3c +#define NVC597_SET_SPARE03_V 31:0 + +#define NVC597_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC597_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC597_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC597_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC597_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC597_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC597_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVC597_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC597_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVC597_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVC597_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC597_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC597_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVC597_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC597_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_SCG_CLOCKS 0x00000008 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC597_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC597_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVC597_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVC597_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC597_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC597_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVC597_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVC597_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVC597_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVC597_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVC597_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVC597_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVC597_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVC597_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVC597_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVC597_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVC597_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVC597_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVC597_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC597_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVC597_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC597_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVC597_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC597_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVC597_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVC597_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVC597_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC597_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC597_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC597_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC597_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC597_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVC597_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVC597_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVC597_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVC597_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVC597_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVC597_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVC597_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVC597_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVC597_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVC597_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVC597_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVC597_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVC597_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVC597_SET_PIPELINE_REGISTER_COUNT_V 8:0 + +#define NVC597_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVC597_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVC597_SET_PIPELINE_PROGRAM_ADDRESS_A(j) (0x2014+(j)*64) +#define NVC597_SET_PIPELINE_PROGRAM_ADDRESS_A_UPPER 7:0 + +#define NVC597_SET_PIPELINE_PROGRAM_ADDRESS_B(j) (0x2018+(j)*64) +#define NVC597_SET_PIPELINE_PROGRAM_ADDRESS_B_LOWER 31:0 + +#define NVC597_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVC597_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVC597_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVC597_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVC597_SET_FALCON00 0x2300 +#define NVC597_SET_FALCON00_V 31:0 + +#define NVC597_SET_FALCON01 0x2304 +#define NVC597_SET_FALCON01_V 31:0 + +#define NVC597_SET_FALCON02 0x2308 +#define NVC597_SET_FALCON02_V 31:0 + +#define NVC597_SET_FALCON03 0x230c +#define NVC597_SET_FALCON03_V 31:0 + +#define NVC597_SET_FALCON04 0x2310 +#define NVC597_SET_FALCON04_V 31:0 + +#define NVC597_SET_FALCON05 0x2314 +#define NVC597_SET_FALCON05_V 31:0 + +#define NVC597_SET_FALCON06 0x2318 +#define NVC597_SET_FALCON06_V 31:0 + +#define NVC597_SET_FALCON07 0x231c +#define NVC597_SET_FALCON07_V 31:0 + +#define NVC597_SET_FALCON08 0x2320 +#define NVC597_SET_FALCON08_V 31:0 + +#define NVC597_SET_FALCON09 0x2324 +#define NVC597_SET_FALCON09_V 31:0 + +#define NVC597_SET_FALCON10 0x2328 +#define NVC597_SET_FALCON10_V 31:0 + +#define NVC597_SET_FALCON11 0x232c +#define NVC597_SET_FALCON11_V 31:0 + +#define NVC597_SET_FALCON12 0x2330 +#define NVC597_SET_FALCON12_V 31:0 + +#define NVC597_SET_FALCON13 0x2334 +#define NVC597_SET_FALCON13_V 31:0 + +#define NVC597_SET_FALCON14 0x2338 +#define NVC597_SET_FALCON14_V 31:0 + +#define NVC597_SET_FALCON15 0x233c +#define NVC597_SET_FALCON15_V 31:0 + +#define NVC597_SET_FALCON16 0x2340 +#define NVC597_SET_FALCON16_V 31:0 + +#define NVC597_SET_FALCON17 0x2344 +#define NVC597_SET_FALCON17_V 31:0 + +#define NVC597_SET_FALCON18 0x2348 +#define NVC597_SET_FALCON18_V 31:0 + +#define NVC597_SET_FALCON19 0x234c +#define NVC597_SET_FALCON19_V 31:0 + +#define NVC597_SET_FALCON20 0x2350 +#define NVC597_SET_FALCON20_V 31:0 + +#define NVC597_SET_FALCON21 0x2354 +#define NVC597_SET_FALCON21_V 31:0 + +#define NVC597_SET_FALCON22 0x2358 +#define NVC597_SET_FALCON22_V 31:0 + +#define NVC597_SET_FALCON23 0x235c +#define NVC597_SET_FALCON23_V 31:0 + +#define NVC597_SET_FALCON24 0x2360 +#define NVC597_SET_FALCON24_V 31:0 + +#define NVC597_SET_FALCON25 0x2364 +#define NVC597_SET_FALCON25_V 31:0 + +#define NVC597_SET_FALCON26 0x2368 +#define NVC597_SET_FALCON26_V 31:0 + +#define NVC597_SET_FALCON27 0x236c +#define NVC597_SET_FALCON27_V 31:0 + +#define NVC597_SET_FALCON28 0x2370 +#define NVC597_SET_FALCON28_V 31:0 + +#define NVC597_SET_FALCON29 0x2374 +#define NVC597_SET_FALCON29_V 31:0 + +#define NVC597_SET_FALCON30 0x2378 +#define NVC597_SET_FALCON30_V 31:0 + +#define NVC597_SET_FALCON31 0x237c +#define NVC597_SET_FALCON31_V 31:0 + +#define NVC597_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVC597_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVC597_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVC597_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVC597_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVC597_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVC597_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVC597_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVC597_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVC597_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVC597_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVC597_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVC597_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVC597_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVC597_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVC597_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVC597_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVC597_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVC597_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVC597_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVC597_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC597_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC597_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVC597_SET_TRAP_HANDLER_A 0x25f8 +#define NVC597_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC597_SET_TRAP_HANDLER_B 0x25fc +#define NVC597_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC597_SET_COLOR_CLAMP 0x2600 +#define NVC597_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVC597_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVC597_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVC597_SET_BINDLESS_TEXTURE 0x2608 +#define NVC597_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 4:0 + +#define NVC597_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVC597_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVC597_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVC597_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVC597_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVC597_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC597_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC597_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC597_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC597_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC597_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC597_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC597_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC597_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC597_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC597_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC597_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC597_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC597_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC597_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVC597_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVC597_CALL_MME_MACRO_V 31:0 + +#define NVC597_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVC597_CALL_MME_DATA_V 31:0 + +#endif /* _cl_turing_a_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/clc5b5sw.h b/src/common/sdk/nvidia/inc/class/clc5b5sw.h index 4adc5a308..0295824e6 100644 --- a/src/common/sdk/nvidia/inc/class/clc5b5sw.h +++ b/src/common/sdk/nvidia/inc/class/clc5b5sw.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,38 +21,34 @@ * DEALINGS IN THE SOFTWARE. */ -#include "nvtypes.h" +#pragma once -#ifndef _clc5b5sw_h_ -#define _clc5b5sw_h_ +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc5b5sw.finn +// -#ifdef __cplusplus -extern "C" { -#endif -/* This file is *not* auto-generated. */ // // Using VERSION_0 will cause the API to interpret // engineType as a CE engine instance. This allows // for backward compatibility with 85B5sw and 90B5sw. // -#define NVC5B5_ALLOCATION_PARAMETERS_VERSION_0 0 +#define NVC5B5_ALLOCATION_PARAMETERS_VERSION_0 0 // // Using VERSION_1 will cause the API to interpret // engineType as an NV2080_ENGINE_TYPE ordinal. // -#define NVC5B5_ALLOCATION_PARAMETERS_VERSION_1 1 +#define NVC5B5_ALLOCATION_PARAMETERS_VERSION_1 1 -typedef struct -{ - NvU32 version; - NvU32 engineType; +#define NVC5B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc5b5U) + +typedef struct NVC5B5_ALLOCATION_PARAMETERS { + NvU32 version; + NvU32 engineType; } NVC5B5_ALLOCATION_PARAMETERS; -#ifdef __cplusplus -}; /* extern "C" */ -#endif -#endif // _clc5b5sw_h_ - diff --git a/src/common/sdk/nvidia/inc/class/clc637.h b/src/common/sdk/nvidia/inc/class/clc637.h index 6d5572dbf..65bed2662 100644 --- a/src/common/sdk/nvidia/inc/class/clc637.h +++ b/src/common/sdk/nvidia/inc/class/clc637.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,16 +21,16 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _clc637_h_ -#define _clc637_h_ +#pragma once -#ifdef __cplusplus -extern "C" { -#endif +#include -#include "nvtypes.h" +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc637.finn +// -#define AMPERE_SMC_PARTITION_REF (0x0000c637) +#define AMPERE_SMC_PARTITION_REF (0xc637U) /* finn: Evaluated from "NVC637_ALLOCATION_PARAMETERS_MESSAGE_ID" */ // // This swizzId can be used by root clients like tools for device level @@ -42,10 +42,12 @@ extern "C" { // TODO: Deprecate NVC637_DEVICE_LEVEL_SWIZZID once all the clients are moved to // NVC637_DEVICE_PROFILING_SWIZZID // -#define NVC637_DEVICE_LEVEL_SWIZZID NVC637_DEVICE_PROFILING_SWIZZID +#define NVC637_DEVICE_LEVEL_SWIZZID NVC637_DEVICE_PROFILING_SWIZZID /* NvRmAlloc parameters */ -typedef struct { +#define NVC637_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc637U) + +typedef struct NVC637_ALLOCATION_PARAMETERS { // // capDescriptor is a file descriptor for unix RM clients, but a void // pointer for windows RM clients. @@ -58,9 +60,3 @@ typedef struct { NvU32 swizzId; } NVC637_ALLOCATION_PARAMETERS; -#ifdef __cplusplus -}; /* extern "C" */ -#endif - -#endif /* _clc637_h_ */ - diff --git a/src/common/sdk/nvidia/inc/class/clc638.h b/src/common/sdk/nvidia/inc/class/clc638.h index 1bc65f423..73b3fda33 100644 --- a/src/common/sdk/nvidia/inc/class/clc638.h +++ b/src/common/sdk/nvidia/inc/class/clc638.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,20 +21,21 @@ * DEALINGS IN THE SOFTWARE. */ +#pragma once -#ifndef _clc638_h_ -#define _clc638_h_ +#include -#ifdef __cplusplus -extern "C" { -#endif +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc638.finn +// -#include "nvtypes.h" - -#define AMPERE_SMC_EXEC_PARTITION_REF (0x0000c638) +#define AMPERE_SMC_EXEC_PARTITION_REF (0xc638U) /* finn: Evaluated from "NVC638_ALLOCATION_PARAMETERS_MESSAGE_ID" */ /* NvRmAlloc parameters */ -typedef struct { +#define NVC638_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc638U) + +typedef struct NVC638_ALLOCATION_PARAMETERS { // // capDescriptor is a file descriptor for unix RM clients, but a void // pointer for windows RM clients. @@ -47,9 +48,3 @@ typedef struct { NvU32 execPartitionId; } NVC638_ALLOCATION_PARAMETERS; -#ifdef __cplusplus -}; /* extern "C" */ -#endif - -#endif /* _clc638_h_ */ - diff --git a/src/common/sdk/nvidia/inc/class/clc639.h b/src/common/sdk/nvidia/inc/class/clc639.h index 239f1b795..d589de7f6 100644 --- a/src/common/sdk/nvidia/inc/class/clc639.h +++ b/src/common/sdk/nvidia/inc/class/clc639.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,20 +21,21 @@ * DEALINGS IN THE SOFTWARE. */ +#pragma once -#ifndef _clc639_h_ -#define _clc639_h_ +#include -#ifdef __cplusplus -extern "C" { -#endif +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc639.finn +// -#include "nvtypes.h" - -#define AMPERE_SMC_CONFIG_SESSION (0x0000c639) +#define AMPERE_SMC_CONFIG_SESSION (0xc639U) /* finn: Evaluated from "NVC639_ALLOCATION_PARAMETERS_MESSAGE_ID" */ /* NvRmAlloc parameters */ -typedef struct { +#define NVC639_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc639U) + +typedef struct NVC639_ALLOCATION_PARAMETERS { // // capDescriptor is a file descriptor for unix RM clients, but a void // pointer for windows RM clients. @@ -45,8 +46,3 @@ typedef struct { NV_DECLARE_ALIGNED(NvU64 capDescriptor, 8); } NVC639_ALLOCATION_PARAMETERS; -#ifdef __cplusplus -}; /* extern "C" */ -#endif - -#endif /* _clc639_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/clc640.h b/src/common/sdk/nvidia/inc/class/clc640.h index 8f1fff3cf..214a45cab 100644 --- a/src/common/sdk/nvidia/inc/class/clc640.h +++ b/src/common/sdk/nvidia/inc/class/clc640.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,20 +21,21 @@ * DEALINGS IN THE SOFTWARE. */ +#pragma once -#ifndef _clc640_h_ -#define _clc640_h_ +#include -#ifdef __cplusplus -extern "C" { -#endif +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc640.finn +// -#include "nvtypes.h" - -#define AMPERE_SMC_MONITOR_SESSION (0x0000c640) +#define AMPERE_SMC_MONITOR_SESSION (0xc640U) /* finn: Evaluated from "NVC640_ALLOCATION_PARAMETERS_MESSAGE_ID" */ /* NvRmAlloc parameters */ -typedef struct { +#define NVC640_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc640U) + +typedef struct NVC640_ALLOCATION_PARAMETERS { // // capDescriptor is a file descriptor for unix RM clients, but a void // pointer for windows RM clients. @@ -45,8 +46,3 @@ typedef struct { NV_DECLARE_ALIGNED(NvU64 capDescriptor, 8); } NVC640_ALLOCATION_PARAMETERS; -#ifdef __cplusplus -}; /* extern "C" */ -#endif - -#endif /* _clc640_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/clc670.h b/src/common/sdk/nvidia/inc/class/clc670.h index e981a30a0..e46194d6d 100644 --- a/src/common/sdk/nvidia/inc/class/clc670.h +++ b/src/common/sdk/nvidia/inc/class/clc670.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -20,26 +20,22 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _clc670_h_ -#define _clc670_h_ +#pragma once -#ifdef __cplusplus -extern "C" { -#endif +#include -#include "nvtypes.h" +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc670.finn +// -#define NVC670_DISPLAY (0x0000C670) +#define NVC670_DISPLAY (0xc670U) /* finn: Evaluated from "NVC670_ALLOCATION_PARAMETERS_MESSAGE_ID" */ -typedef struct -{ - NvU32 numHeads; // Number of HEADs in this chip/display - NvU32 numSors; // Number of SORs in this chip/display - NvU32 numDsis; // Number of DSIs in this chip/display +#define NVC670_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc670U) + +typedef struct NVC670_ALLOCATION_PARAMETERS { + NvU32 numHeads; // Number of HEADs in this chip/display + NvU32 numSors; // Number of SORs in this chip/display + NvU32 numDsis; // Number of DSIs in this chip/display } NVC670_ALLOCATION_PARAMETERS; -#ifdef __cplusplus -}; /* extern "C" */ -#endif - -#endif /* _clc670_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/clc697.h b/src/common/sdk/nvidia/inc/class/clc697.h index 550ebcae0..a8b447e65 100644 --- a/src/common/sdk/nvidia/inc/class/clc697.h +++ b/src/common/sdk/nvidia/inc/class/clc697.h @@ -1,29 +1,4352 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. -#ifndef _clc697_h_ -#define _clc697_h_ + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_ampere_a_h_ +#define _cl_ampere_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl ampere_a */ + +#include "nvtypes.h" #define AMPERE_A 0xC697 -#endif // _clc697_h_ +#define NVC697_SET_OBJECT 0x0000 +#define NVC697_SET_OBJECT_CLASS_ID 15:0 +#define NVC697_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC697_NO_OPERATION 0x0100 +#define NVC697_NO_OPERATION_V 31:0 + +#define NVC697_SET_NOTIFY_A 0x0104 +#define NVC697_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC697_SET_NOTIFY_B 0x0108 +#define NVC697_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC697_NOTIFY 0x010c +#define NVC697_NOTIFY_TYPE 31:0 +#define NVC697_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC697_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC697_WAIT_FOR_IDLE 0x0110 +#define NVC697_WAIT_FOR_IDLE_V 31:0 + +#define NVC697_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVC697_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVC697_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVC697_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVC697_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVC697_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVC697_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVC697_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVC697_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVC697_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVC697_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVC697_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVC697_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVC697_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVC697_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVC697_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVC697_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVC697_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVC697_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC697_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC697_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC697_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC697_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC697_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC697_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC697_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC697_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC697_SEND_GO_IDLE 0x013c +#define NVC697_SEND_GO_IDLE_V 31:0 + +#define NVC697_PM_TRIGGER 0x0140 +#define NVC697_PM_TRIGGER_V 31:0 + +#define NVC697_PM_TRIGGER_WFI 0x0144 +#define NVC697_PM_TRIGGER_WFI_V 31:0 + +#define NVC697_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC697_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC697_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC697_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC697_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC697_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC697_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC697_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC697_LINE_LENGTH_IN 0x0180 +#define NVC697_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC697_LINE_COUNT 0x0184 +#define NVC697_LINE_COUNT_VALUE 31:0 + +#define NVC697_OFFSET_OUT_UPPER 0x0188 +#define NVC697_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVC697_OFFSET_OUT 0x018c +#define NVC697_OFFSET_OUT_VALUE 31:0 + +#define NVC697_PITCH_OUT 0x0190 +#define NVC697_PITCH_OUT_VALUE 31:0 + +#define NVC697_SET_DST_BLOCK_SIZE 0x0194 +#define NVC697_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC697_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC697_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC697_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC697_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC697_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC697_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC697_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC697_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC697_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC697_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC697_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC697_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC697_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC697_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC697_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC697_SET_DST_WIDTH 0x0198 +#define NVC697_SET_DST_WIDTH_V 31:0 + +#define NVC697_SET_DST_HEIGHT 0x019c +#define NVC697_SET_DST_HEIGHT_V 31:0 + +#define NVC697_SET_DST_DEPTH 0x01a0 +#define NVC697_SET_DST_DEPTH_V 31:0 + +#define NVC697_SET_DST_LAYER 0x01a4 +#define NVC697_SET_DST_LAYER_V 31:0 + +#define NVC697_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC697_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC697_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC697_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC697_LAUNCH_DMA 0x01b0 +#define NVC697_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC697_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC697_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC697_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC697_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC697_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC697_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC697_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC697_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC697_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC697_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC697_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC697_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC697_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC697_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC697_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC697_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC697_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC697_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC697_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC697_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC697_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC697_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC697_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC697_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC697_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC697_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC697_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC697_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC697_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC697_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC697_LOAD_INLINE_DATA 0x01b4 +#define NVC697_LOAD_INLINE_DATA_V 31:0 + +#define NVC697_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC697_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC697_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC697_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC697_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC697_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC697_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC697_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC697_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC697_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC697_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC697_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC697_RUN_DS_NOW 0x0200 +#define NVC697_RUN_DS_NOW_V 31:0 + +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVC697_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVC697_SET_GS_MODE 0x0208 +#define NVC697_SET_GS_MODE_TYPE 0:0 +#define NVC697_SET_GS_MODE_TYPE_ANY 0x00000000 +#define NVC697_SET_GS_MODE_TYPE_FAST_GS 0x00000001 + +#define NVC697_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVC697_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVC697_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVC697_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVC697_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVC697_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVC697_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVC697_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_GS_DM_FIFO 0x0214 +#define NVC697_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVC697_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVC697_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVC697_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVC697_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC697_INVALIDATE_SHADER_CACHES 0x021c +#define NVC697_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC697_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC697_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC697_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC697_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC697_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC697_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC697_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC697_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC697_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC697_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC697_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC697_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC697_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC697_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC697_SET_INSTANCE_COUNT 0x0220 +#define NVC697_SET_INSTANCE_COUNT_V 31:0 + +#define NVC697_SET_POSITION_W_SCALED_OFFSET_ENABLE 0x0224 +#define NVC697_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE 0:0 +#define NVC697_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_GO_IDLE_TIMEOUT 0x022c +#define NVC697_SET_GO_IDLE_TIMEOUT_V 31:0 + +#define NVC697_SET_MME_VERSION 0x0234 +#define NVC697_SET_MME_VERSION_MAJOR 7:0 + +#define NVC697_SET_INDEX_BUFFER_SIZE_A 0x0238 +#define NVC697_SET_INDEX_BUFFER_SIZE_A_UPPER 7:0 + +#define NVC697_SET_INDEX_BUFFER_SIZE_B 0x023c +#define NVC697_SET_INDEX_BUFFER_SIZE_B_LOWER 31:0 + +#define NVC697_SET_ROOT_TABLE_VISIBILITY(i) (0x0240+(i)*4) +#define NVC697_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP0_ENABLE 1:0 +#define NVC697_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP1_ENABLE 5:4 +#define NVC697_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP2_ENABLE 9:8 +#define NVC697_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP3_ENABLE 13:12 +#define NVC697_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP4_ENABLE 17:16 + +#define NVC697_SET_DRAW_CONTROL_A 0x0260 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY 3:0 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_POINTS 0x00000000 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_LINES 0x00000001 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_QUADS 0x00000007 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_SET_DRAW_CONTROL_A_TOPOLOGY_PATCH 0x0000000E +#define NVC697_SET_DRAW_CONTROL_A_PRIMITIVE_ID 4:4 +#define NVC697_SET_DRAW_CONTROL_A_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC697_SET_DRAW_CONTROL_A_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC697_SET_DRAW_CONTROL_A_INSTANCE_ID 6:5 +#define NVC697_SET_DRAW_CONTROL_A_INSTANCE_ID_FIRST 0x00000000 +#define NVC697_SET_DRAW_CONTROL_A_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC697_SET_DRAW_CONTROL_A_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC697_SET_DRAW_CONTROL_A_SPLIT_MODE 8:7 +#define NVC697_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC697_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC697_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC697_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC697_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE 9:9 +#define NVC697_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 +#define NVC697_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX 10:10 +#define NVC697_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_FALSE 0x00000000 +#define NVC697_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_TRUE 0x00000001 +#define NVC697_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX 11:11 +#define NVC697_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_FALSE 0x00000000 +#define NVC697_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_TRUE 0x00000001 + +#define NVC697_SET_DRAW_CONTROL_B 0x0264 +#define NVC697_SET_DRAW_CONTROL_B_INSTANCE_COUNT 31:0 + +#define NVC697_DRAW_INDEX_BUFFER_BEGIN_END_A 0x0268 +#define NVC697_DRAW_INDEX_BUFFER_BEGIN_END_A_FIRST 31:0 + +#define NVC697_DRAW_INDEX_BUFFER_BEGIN_END_B 0x026c +#define NVC697_DRAW_INDEX_BUFFER_BEGIN_END_B_COUNT 31:0 + +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_A 0x0270 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_A_START 31:0 + +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_B 0x0274 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_B_COUNT 31:0 + +#define NVC697_INVALIDATE_RASTER_CACHE_NO_WFI 0x027c +#define NVC697_INVALIDATE_RASTER_CACHE_NO_WFI_V 0:0 + +#define NVC697_SET_COLOR_RENDER_TO_ZETA_SURFACE 0x02b8 +#define NVC697_SET_COLOR_RENDER_TO_ZETA_SURFACE_V 0:0 +#define NVC697_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_FALSE 0x00000000 +#define NVC697_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_TRUE 0x00000001 + +#define NVC697_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION 0x02bc +#define NVC697_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V 0:0 +#define NVC697_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_FALSE 0x00000000 +#define NVC697_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_TRUE 0x00000001 + +#define NVC697_INCREMENT_SYNC_POINT 0x02c8 +#define NVC697_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVC697_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVC697_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVC697_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVC697_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVC697_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVC697_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVC697_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVC697_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVC697_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC697_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVC697_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVC697_DECOMPRESS_SURFACE 0x02e0 +#define NVC697_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVC697_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVC697_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVC697_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVC697_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVC697_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVC697_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVC697_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVC697_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVC697_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVC697_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVC697_SET_ZCULL_SUBREGION 0x02e8 +#define NVC697_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVC697_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVC697_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVC697_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVC697_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVC697_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVC697_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVC697_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVC697_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVC697_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVC697_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVC697_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVC697_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVC697_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVC697_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVC697_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVC697_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVC697_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVC697_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVC697_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVC697_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVC697_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVC697_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVC697_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVC697_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC697_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVC697_DRAW_ZERO_INDEX 0x0304 +#define NVC697_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVC697_SET_L1_CONFIGURATION 0x0308 +#define NVC697_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVC697_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC697_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVC697_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVC697_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVC697_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVC697_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVC697_SET_SPA_VERSION 0x0310 +#define NVC697_SET_SPA_VERSION_MINOR 7:0 +#define NVC697_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC697_SET_TIMESLICE_BATCH_LIMIT 0x0314 +#define NVC697_SET_TIMESLICE_BATCH_LIMIT_BATCH_LIMIT 15:0 + +#define NVC697_SET_SNAP_GRID_LINE 0x0318 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC697_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC697_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVC697_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC697_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC697_SET_SNAP_GRID_NON_LINE 0x031c +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC697_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC697_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVC697_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC697_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC697_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVC697_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVC697_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVC697_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVC697_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVC697_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVC697_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVC697_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVC697_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVC697_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVC697_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVC697_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVC697_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVC697_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVC697_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVC697_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVC697_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVC697_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVC697_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVC697_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVC697_SET_TESSELLATION_LOD_V1 0x0330 +#define NVC697_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVC697_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVC697_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVC697_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVC697_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVC697_RESERVED_TG07 0x033c +#define NVC697_RESERVED_TG07_V 0:0 + +#define NVC697_RESERVED_TG08 0x0340 +#define NVC697_RESERVED_TG08_V 0:0 + +#define NVC697_RESERVED_TG09 0x0344 +#define NVC697_RESERVED_TG09_V 0:0 + +#define NVC697_RESERVED_TG10 0x0348 +#define NVC697_RESERVED_TG10_V 0:0 + +#define NVC697_RESERVED_TG11 0x034c +#define NVC697_RESERVED_TG11_V 0:0 + +#define NVC697_RESERVED_TG12 0x0350 +#define NVC697_RESERVED_TG12_V 0:0 + +#define NVC697_RESERVED_TG13 0x0354 +#define NVC697_RESERVED_TG13_V 0:0 + +#define NVC697_RESERVED_TG14 0x0358 +#define NVC697_RESERVED_TG14_V 0:0 + +#define NVC697_RESERVED_TG15 0x035c +#define NVC697_RESERVED_TG15_V 0:0 + +#define NVC697_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVC697_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVC697_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVC697_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVC697_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVC697_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVC697_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVC697_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVC697_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVC697_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVC697_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVC697_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVC697_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE 8:8 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE 9:9 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC697_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVC697_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVC697_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVC697_SET_RASTER_ENABLE 0x037c +#define NVC697_SET_RASTER_ENABLE_V 0:0 +#define NVC697_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVC697_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVC697_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVC697_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVC697_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVC697_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVC697_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVC697_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVC697_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVC697_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVC697_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVC697_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVC697_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVC697_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVC697_SET_POSITION_W_SCALED_OFFSET_SCALE_A(j) (0x0400+(j)*16) +#define NVC697_SET_POSITION_W_SCALED_OFFSET_SCALE_A_V 31:0 + +#define NVC697_SET_POSITION_W_SCALED_OFFSET_SCALE_B(j) (0x0404+(j)*16) +#define NVC697_SET_POSITION_W_SCALED_OFFSET_SCALE_B_V 31:0 + +#define NVC697_SET_POSITION_W_SCALED_OFFSET_RESERVED_A(j) (0x0408+(j)*16) +#define NVC697_SET_POSITION_W_SCALED_OFFSET_RESERVED_A_V 31:0 + +#define NVC697_SET_POSITION_W_SCALED_OFFSET_RESERVED_B(j) (0x040c+(j)*16) +#define NVC697_SET_POSITION_W_SCALED_OFFSET_RESERVED_B_V 31:0 + +#define NVC697_SET_ROOT_TABLE_SELECTOR 0x0504 +#define NVC697_SET_ROOT_TABLE_SELECTOR_ROOT_TABLE 2:0 +#define NVC697_SET_ROOT_TABLE_SELECTOR_OFFSET 15:8 + +#define NVC697_LOAD_ROOT_TABLE 0x0508 +#define NVC697_LOAD_ROOT_TABLE_V 31:0 + +#define NVC697_SET_MME_MEM_ADDRESS_A 0x0550 +#define NVC697_SET_MME_MEM_ADDRESS_A_UPPER 7:0 + +#define NVC697_SET_MME_MEM_ADDRESS_B 0x0554 +#define NVC697_SET_MME_MEM_ADDRESS_B_LOWER 31:0 + +#define NVC697_SET_MME_DATA_RAM_ADDRESS 0x0558 +#define NVC697_SET_MME_DATA_RAM_ADDRESS_WORD 31:0 + +#define NVC697_MME_DMA_READ 0x055c +#define NVC697_MME_DMA_READ_LENGTH 31:0 + +#define NVC697_MME_DMA_READ_FIFOED 0x0560 +#define NVC697_MME_DMA_READ_FIFOED_LENGTH 31:0 + +#define NVC697_MME_DMA_WRITE 0x0564 +#define NVC697_MME_DMA_WRITE_LENGTH 31:0 + +#define NVC697_MME_DMA_REDUCTION 0x0568 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP 2:0 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP_RED_INC 0x00000003 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP_RED_AND 0x00000005 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP_RED_OR 0x00000006 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_FORMAT 5:4 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_SIZE 8:8 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_SIZE_FOUR_BYTES 0x00000000 +#define NVC697_MME_DMA_REDUCTION_REDUCTION_SIZE_EIGHT_BYTES 0x00000001 + +#define NVC697_MME_DMA_SYSMEMBAR 0x056c +#define NVC697_MME_DMA_SYSMEMBAR_V 0:0 + +#define NVC697_MME_DMA_SYNC 0x0570 +#define NVC697_MME_DMA_SYNC_VALUE 31:0 + +#define NVC697_SET_MME_DATA_FIFO_CONFIG 0x0574 +#define NVC697_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE 2:0 +#define NVC697_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_0KB 0x00000000 +#define NVC697_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_4KB 0x00000001 +#define NVC697_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_8KB 0x00000002 +#define NVC697_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_12KB 0x00000003 +#define NVC697_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_16KB 0x00000004 + +#define NVC697_SET_VERTEX_STREAM_SIZE_A(j) (0x0600+(j)*8) +#define NVC697_SET_VERTEX_STREAM_SIZE_A_UPPER 7:0 + +#define NVC697_SET_VERTEX_STREAM_SIZE_B(j) (0x0604+(j)*8) +#define NVC697_SET_VERTEX_STREAM_SIZE_B_LOWER 31:0 + +#define NVC697_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVC697_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVC697_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVC697_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVC697_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVC697_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVC697_SET_RASTER_INPUT 0x0740 +#define NVC697_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVC697_SET_STREAM_OUTPUT 0x0744 +#define NVC697_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVC697_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVC697_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVC697_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVC697_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVC697_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVC697_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVC697_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVC697_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVC697_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC697_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC697_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC697_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVC697_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC697_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC697_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVC697_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVC697_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVC697_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVC697_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVC697_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVC697_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVC697_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC697_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVC697_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC697_SET_STENCIL_ZERO_BANDWIDTH_CLEAR 0x07b0 +#define NVC697_SET_STENCIL_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC697_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVC697_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVC697_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVC697_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVC697_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVC697_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVC697_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVC697_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVC697_SET_CULL_BEFORE_FETCH 0x07dc +#define NVC697_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVC697_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVC697_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVC697_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVC697_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVC697_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVC697_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVC697_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVC697_SET_ZCULL_STORAGE_A 0x07e8 +#define NVC697_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVC697_SET_ZCULL_STORAGE_B 0x07ec +#define NVC697_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVC697_SET_ZCULL_STORAGE_C 0x07f0 +#define NVC697_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC697_SET_ZCULL_STORAGE_D 0x07f4 +#define NVC697_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC697_SET_ZT_READ_ONLY 0x07f8 +#define NVC697_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVC697_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVC697_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVC697_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVC697_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVC697_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVC697_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVC697_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVC697_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVC697_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVC697_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVC697_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVC697_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVC697_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVC697_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVC697_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVC697_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVC697_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVC697_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVC697_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVC697_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVC697_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVC697_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVC697_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVC697_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVC697_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC697_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC697_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVC697_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC697_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC697_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVC697_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC697_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVC697_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVC697_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVC697_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVC697_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVC697_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVC697_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVC697_SET_COLOR_TARGET_RESERVED_A(j) (0x0824+(j)*64) +#define NVC697_SET_COLOR_TARGET_RESERVED_A_V 0:0 + +#define NVC697_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVC697_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVC697_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVC697_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVC697_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVC697_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVC697_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVC697_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVC697_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVC697_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVC697_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVC697_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVC697_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVC697_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVC697_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVC697_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVC697_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVC697_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVC697_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC697_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVC697_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVC697_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC697_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVC697_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVC697_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVC697_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVC697_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVC697_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVC697_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVC697_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVC697_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVC697_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVC697_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVC697_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVC697_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVC697_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVC697_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVC697_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVC697_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVC697_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC697_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVC697_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVC697_SET_STATISTICS_COUNTER 0x0d68 +#define NVC697_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVC697_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVC697_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVC697_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVC697_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVC697_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVC697_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVC697_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVC697_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVC697_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVC697_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVC697_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVC697_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVC697_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVC697_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVC697_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVC697_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 +#define NVC697_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE 16:16 +#define NVC697_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVC697_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC697_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC697_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVC697_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC697_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC697_SET_VERTEX_ARRAY_START 0x0d74 +#define NVC697_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVC697_DRAW_VERTEX_ARRAY 0x0d78 +#define NVC697_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVC697_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVC697_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVC697_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVC697_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVC697_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVC697_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVC697_SET_Z_CLEAR_VALUE 0x0d90 +#define NVC697_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVC697_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC697_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC697_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC697_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVC697_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVC697_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVC697_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC697_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC697_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVC697_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVC697_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVC697_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVC697_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVC697_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVC697_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVC697_SET_FRONT_POLYGON_MODE 0x0dac +#define NVC697_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVC697_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC697_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC697_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC697_SET_BACK_POLYGON_MODE 0x0db0 +#define NVC697_SET_BACK_POLYGON_MODE_V 31:0 +#define NVC697_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC697_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC697_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC697_SET_POLY_SMOOTH 0x0db4 +#define NVC697_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVC697_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVC697_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVC697_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVC697_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVC697_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVC697_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVC697_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVC697_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVC697_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVC697_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVC697_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVC697_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVC697_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVC697_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVC697_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVC697_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVC697_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVC697_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_PATCH 0x0dcc +#define NVC697_SET_PATCH_SIZE 7:0 + +#define NVC697_SET_ITERATED_BLEND 0x0dd0 +#define NVC697_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVC697_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVC697_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVC697_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVC697_SET_ZCULL_CRITERION 0x0dd8 +#define NVC697_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVC697_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVC697_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVC697_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVC697_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVC697_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVC697_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVC697_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVC697_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVC697_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVC697_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVC697_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVC697_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVC697_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVC697_SET_ZCULL_CRITERION_SREF 23:16 +#define NVC697_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVC697_PIXEL_SHADER_BARRIER 0x0de0 +#define NVC697_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVC697_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVC697_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC697_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC697_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVC697_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVC697_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVC697_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVC697_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVC697_SET_WINDOW_OFFSET_X 0x0df8 +#define NVC697_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVC697_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVC697_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVC697_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVC697_SET_SCISSOR_ENABLE_V 0:0 +#define NVC697_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVC697_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVC697_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVC697_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVC697_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVC697_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVC697_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVC697_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVC697_SET_VPC_PERF_KNOB 0x0f14 +#define NVC697_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVC697_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVC697_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVC697_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVC697_PM_LOCAL_TRIGGER 0x0f18 +#define NVC697_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVC697_SET_POST_Z_PS_IMASK 0x0f1c +#define NVC697_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVC697_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVC697_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVC697_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVC697_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVC697_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVC697_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVC697_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVC697_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVC697_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVC697_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVC697_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVC697_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVC697_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVC697_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVC697_SET_BACK_STENCIL_MASK 0x0f58 +#define NVC697_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVC697_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVC697_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVC697_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVC697_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVC697_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVC697_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVC697_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVC697_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVC697_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVC697_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVC697_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVC697_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVC697_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVC697_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVC697_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVC697_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVC697_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVC697_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVC697_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVC697_SET_SAMPLE_MASK 0x0fa4 +#define NVC697_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVC697_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVC697_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVC697_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVC697_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVC697_SET_CT_MRT_ENABLE 0x0fac +#define NVC697_SET_CT_MRT_ENABLE_V 0:0 +#define NVC697_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVC697_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVC697_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVC697_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVC697_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVC697_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVC697_SET_TIR 0x0fb4 +#define NVC697_SET_TIR_MODE 1:0 +#define NVC697_SET_TIR_MODE_DISABLED 0x00000000 +#define NVC697_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVC697_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVC697_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVC697_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVC697_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVC697_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC697_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC697_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVC697_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVC697_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVC697_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVC697_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVC697_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVC697_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVC697_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVC697_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVC697_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVC697_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVC697_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_TIR_MODULATION 0x0fd4 +#define NVC697_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVC697_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVC697_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVC697_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVC697_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVC697_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVC697_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVC697_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVC697_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVC697_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVC697_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVC697_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVC697_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVC697_SET_ZT_A 0x0fe0 +#define NVC697_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_ZT_B 0x0fe4 +#define NVC697_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_ZT_FORMAT 0x0fe8 +#define NVC697_SET_ZT_FORMAT_V 4:0 +#define NVC697_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVC697_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVC697_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVC697_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVC697_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVC697_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVC697_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVC697_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVC697_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVC697_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVC697_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVC697_SET_ZT_BLOCK_SIZE 0x0fec +#define NVC697_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVC697_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC697_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVC697_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC697_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC697_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC697_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC697_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC697_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC697_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVC697_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC697_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVC697_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVC697_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVC697_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVC697_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC697_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVC697_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVC697_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC697_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC697_SET_VIEWPORT_MULTICAST 0x1004 +#define NVC697_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVC697_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVC697_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVC697_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVC697_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVC697_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVC697_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC697_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVC697_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVC697_SET_RESERVED_SW_METHOD00 0x1014 +#define NVC697_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC697_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVC697_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC697_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVC697_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC697_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVC697_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC697_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVC697_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC697_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_RESERVED_SW_METHOD01 0x1028 +#define NVC697_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD02 0x102c +#define NVC697_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC697_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVC697_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVC697_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVC697_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVC697_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVC697_SET_SPARE_NOOP01 0x1044 +#define NVC697_SET_SPARE_NOOP01_V 31:0 + +#define NVC697_SET_SPARE_NOOP02 0x1048 +#define NVC697_SET_SPARE_NOOP02_V 31:0 + +#define NVC697_SET_SPARE_NOOP03 0x104c +#define NVC697_SET_SPARE_NOOP03_V 31:0 + +#define NVC697_SET_SPARE_NOOP04 0x1050 +#define NVC697_SET_SPARE_NOOP04_V 31:0 + +#define NVC697_SET_SPARE_NOOP05 0x1054 +#define NVC697_SET_SPARE_NOOP05_V 31:0 + +#define NVC697_SET_SPARE_NOOP06 0x1058 +#define NVC697_SET_SPARE_NOOP06_V 31:0 + +#define NVC697_SET_SPARE_NOOP07 0x105c +#define NVC697_SET_SPARE_NOOP07_V 31:0 + +#define NVC697_SET_SPARE_NOOP08 0x1060 +#define NVC697_SET_SPARE_NOOP08_V 31:0 + +#define NVC697_SET_SPARE_NOOP09 0x1064 +#define NVC697_SET_SPARE_NOOP09_V 31:0 + +#define NVC697_SET_SPARE_NOOP10 0x1068 +#define NVC697_SET_SPARE_NOOP10_V 31:0 + +#define NVC697_SET_SPARE_NOOP11 0x106c +#define NVC697_SET_SPARE_NOOP11_V 31:0 + +#define NVC697_SET_SPARE_NOOP12 0x1070 +#define NVC697_SET_SPARE_NOOP12_V 31:0 + +#define NVC697_SET_SPARE_NOOP13 0x1074 +#define NVC697_SET_SPARE_NOOP13_V 31:0 + +#define NVC697_SET_SPARE_NOOP14 0x1078 +#define NVC697_SET_SPARE_NOOP14_V 31:0 + +#define NVC697_SET_SPARE_NOOP15 0x107c +#define NVC697_SET_SPARE_NOOP15_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVC697_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVC697_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVC697_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD06 0x10bc +#define NVC697_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVC697_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVC697_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVC697_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVC697_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVC697_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVC697_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVC697_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD13 0x10dc +#define NVC697_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC697_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVC697_UNBIND_ALL 0x10f4 +#define NVC697_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVC697_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVC697_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVC697_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVC697_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC697_SET_RESERVED_SW_METHOD14 0x1100 +#define NVC697_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC697_SET_RESERVED_SW_METHOD15 0x1104 +#define NVC697_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC697_NO_OPERATION_DATA_HI 0x110c +#define NVC697_NO_OPERATION_DATA_HI_V 31:0 + +#define NVC697_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVC697_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVC697_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVC697_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVC697_PM_TRIGGER_END 0x1114 +#define NVC697_PM_TRIGGER_END_V 31:0 + +#define NVC697_SET_VERTEX_ID_BASE 0x1118 +#define NVC697_SET_VERTEX_ID_BASE_V 31:0 + +#define NVC697_SET_STENCIL_COMPRESSION 0x111c +#define NVC697_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVC697_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC697_SET_TIR_CONTROL 0x1130 +#define NVC697_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVC697_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC697_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC697_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVC697_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC697_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC697_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVC697_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVC697_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 + +#define NVC697_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVC697_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVC697_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVC697_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVC697_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVC697_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVC697_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVC697_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVC697_SET_FILL_VIA_TRIANGLE 0x113c +#define NVC697_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVC697_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVC697_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVC697_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVC697_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVC697_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVC697_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVC697_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVC697_FLUSH_PENDING_WRITES 0x1144 +#define NVC697_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVC697_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVC697_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC697_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC697_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC697_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVC697_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC697_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC697_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVC697_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVC697_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVC697_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVC697_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVC697_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVC697_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVC697_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVC697_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVC697_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVC697_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVC697_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVC697_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVC697_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVC697_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVC697_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC697_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC697_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVC697_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC697_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_SCREEN_STATE_MASK 0x1204 +#define NVC697_SET_SCREEN_STATE_MASK_MASK 3:0 + +#define NVC697_SET_ZT_SPARSE 0x1208 +#define NVC697_SET_ZT_SPARSE_ENABLE 0:0 +#define NVC697_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVC697_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVC697_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC697_SET_CT_SELECT 0x121c +#define NVC697_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVC697_SET_CT_SELECT_TARGET0 6:4 +#define NVC697_SET_CT_SELECT_TARGET1 9:7 +#define NVC697_SET_CT_SELECT_TARGET2 12:10 +#define NVC697_SET_CT_SELECT_TARGET3 15:13 +#define NVC697_SET_CT_SELECT_TARGET4 18:16 +#define NVC697_SET_CT_SELECT_TARGET5 21:19 +#define NVC697_SET_CT_SELECT_TARGET6 24:22 +#define NVC697_SET_CT_SELECT_TARGET7 27:25 + +#define NVC697_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVC697_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVC697_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVC697_SET_ZT_SIZE_A 0x1228 +#define NVC697_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVC697_SET_ZT_SIZE_B 0x122c +#define NVC697_SET_ZT_SIZE_B_HEIGHT 17:0 + +#define NVC697_SET_ZT_SIZE_C 0x1230 +#define NVC697_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVC697_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVC697_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC697_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVC697_SET_SAMPLER_BINDING 0x1234 +#define NVC697_SET_SAMPLER_BINDING_V 0:0 +#define NVC697_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVC697_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVC697_DRAW_AUTO 0x123c +#define NVC697_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVC697_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVC697_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVC697_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVC697_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVC697_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVC697_SET_BACK_END_COPY_A 0x1264 +#define NVC697_SET_BACK_END_COPY_A_DWORDS 7:0 +#define NVC697_SET_BACK_END_COPY_A_SATURATE32_ENABLE 8:8 +#define NVC697_SET_BACK_END_COPY_A_SATURATE32_ENABLE_FALSE 0x00000000 +#define NVC697_SET_BACK_END_COPY_A_SATURATE32_ENABLE_TRUE 0x00000001 +#define NVC697_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE 12:12 +#define NVC697_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_FALSE 0x00000000 +#define NVC697_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_BACK_END_COPY_B 0x1268 +#define NVC697_SET_BACK_END_COPY_B_SRC_ADDRESS_UPPER 7:0 + +#define NVC697_SET_BACK_END_COPY_C 0x126c +#define NVC697_SET_BACK_END_COPY_C_SRC_ADDRESS_LOWER 31:0 + +#define NVC697_SET_BACK_END_COPY_D 0x1270 +#define NVC697_SET_BACK_END_COPY_D_DEST_ADDRESS_UPPER 7:0 + +#define NVC697_SET_BACK_END_COPY_E 0x1274 +#define NVC697_SET_BACK_END_COPY_E_DEST_ADDRESS_LOWER 31:0 + +#define NVC697_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVC697_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 19:0 + +#define NVC697_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVC697_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVC697_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC697_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVC697_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVC697_CLEAR_ZCULL_REGION 0x12c8 +#define NVC697_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVC697_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVC697_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVC697_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVC697_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC697_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC697_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVC697_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC697_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC697_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVC697_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVC697_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVC697_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVC697_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVC697_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVC697_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVC697_SET_DEPTH_TEST 0x12cc +#define NVC697_SET_DEPTH_TEST_ENABLE 0:0 +#define NVC697_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVC697_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_FILL_MODE 0x12d0 +#define NVC697_SET_FILL_MODE_V 31:0 +#define NVC697_SET_FILL_MODE_V_POINT 0x00000001 +#define NVC697_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVC697_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVC697_SET_SHADE_MODE 0x12d4 +#define NVC697_SET_SHADE_MODE_V 31:0 +#define NVC697_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVC697_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVC697_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVC697_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC697_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC697_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVC697_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVC697_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVC697_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVC697_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVC697_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVC697_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVC697_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVC697_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_DEPTH_WRITE 0x12e8 +#define NVC697_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVC697_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_ALPHA_TEST 0x12ec +#define NVC697_SET_ALPHA_TEST_ENABLE 0:0 +#define NVC697_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVC697_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVC697_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVC697_DRAW_INLINE_INDEX4X8 0x1304 +#define NVC697_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVC697_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVC697_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVC697_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVC697_D3D_SET_CULL_MODE 0x1308 +#define NVC697_D3D_SET_CULL_MODE_V 31:0 +#define NVC697_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVC697_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVC697_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVC697_SET_DEPTH_FUNC 0x130c +#define NVC697_SET_DEPTH_FUNC_V 31:0 +#define NVC697_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVC697_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVC697_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC697_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC697_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVC697_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC697_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC697_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC697_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVC697_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVC697_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC697_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC697_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVC697_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC697_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC697_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC697_SET_ALPHA_REF 0x1310 +#define NVC697_SET_ALPHA_REF_V 31:0 + +#define NVC697_SET_ALPHA_FUNC 0x1314 +#define NVC697_SET_ALPHA_FUNC_V 31:0 +#define NVC697_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVC697_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVC697_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC697_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC697_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVC697_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC697_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC697_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC697_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVC697_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVC697_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC697_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC697_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVC697_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC697_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC697_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC697_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVC697_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVC697_SET_BLEND_CONST_RED 0x131c +#define NVC697_SET_BLEND_CONST_RED_V 31:0 + +#define NVC697_SET_BLEND_CONST_GREEN 0x1320 +#define NVC697_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVC697_SET_BLEND_CONST_BLUE 0x1324 +#define NVC697_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVC697_SET_BLEND_CONST_ALPHA 0x1328 +#define NVC697_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVC697_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC697_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC697_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC697_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC697_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC697_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC697_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVC697_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC697_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC697_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_BLEND_COLOR_OP 0x1340 +#define NVC697_SET_BLEND_COLOR_OP_V 31:0 +#define NVC697_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC697_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC697_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC697_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC697_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC697_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC697_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC697_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC697_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC697_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC697_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC697_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC697_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC697_SET_BLEND_ALPHA_OP 0x134c +#define NVC697_SET_BLEND_ALPHA_OP_V 31:0 +#define NVC697_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC697_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC697_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC697_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC697_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC697_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC697_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC697_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC697_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC697_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC697_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC697_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVC697_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVC697_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVC697_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC697_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC697_SET_SINGLE_ROP_CONTROL 0x135c +#define NVC697_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVC697_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_BLEND(i) (0x1360+(i)*4) +#define NVC697_SET_BLEND_ENABLE 0:0 +#define NVC697_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVC697_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_STENCIL_TEST 0x1380 +#define NVC697_SET_STENCIL_TEST_ENABLE 0:0 +#define NVC697_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC697_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_STENCIL_OP_FAIL 0x1384 +#define NVC697_SET_STENCIL_OP_FAIL_V 31:0 +#define NVC697_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC697_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC697_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC697_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC697_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC697_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC697_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC697_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC697_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC697_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC697_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC697_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC697_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC697_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC697_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC697_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC697_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVC697_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC697_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC697_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC697_SET_STENCIL_OP_ZPASS 0x138c +#define NVC697_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVC697_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC697_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC697_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC697_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC697_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC697_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC697_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC697_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC697_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC697_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC697_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC697_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC697_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC697_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC697_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC697_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC697_SET_STENCIL_FUNC 0x1390 +#define NVC697_SET_STENCIL_FUNC_V 31:0 +#define NVC697_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC697_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC697_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC697_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC697_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC697_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC697_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC697_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC697_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC697_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC697_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC697_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC697_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC697_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC697_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC697_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC697_SET_STENCIL_FUNC_REF 0x1394 +#define NVC697_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVC697_SET_STENCIL_FUNC_MASK 0x1398 +#define NVC697_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVC697_SET_STENCIL_MASK 0x139c +#define NVC697_SET_STENCIL_MASK_V 7:0 + +#define NVC697_SET_DRAW_AUTO_START 0x13a4 +#define NVC697_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVC697_SET_PS_SATURATE 0x13a8 +#define NVC697_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVC697_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVC697_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC697_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVC697_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVC697_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC697_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVC697_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVC697_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC697_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVC697_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVC697_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC697_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVC697_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVC697_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC697_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVC697_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVC697_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC697_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVC697_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVC697_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC697_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVC697_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVC697_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC697_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVC697_SET_WINDOW_ORIGIN 0x13ac +#define NVC697_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVC697_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVC697_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVC697_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVC697_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVC697_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVC697_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVC697_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC697_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVC697_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC697_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVC697_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVC697_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVC697_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC697_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC697_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC697_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC697_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC697_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC697_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVC697_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVC697_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVC697_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVC697_SET_PS_WARP_WATERMARKS 0x1450 +#define NVC697_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVC697_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVC697_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVC697_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVC697_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC697_STORE_ZCULL 0x1464 +#define NVC697_STORE_ZCULL_V 0:0 + +#define NVC697_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVC697_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVC697_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVC697_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVC697_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVC697_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVC697_LOAD_ZCULL 0x1500 +#define NVC697_LOAD_ZCULL_V 0:0 + +#define NVC697_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVC697_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVC697_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVC697_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC697_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC697_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVC697_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC697_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC697_SET_USER_CLIP_ENABLE 0x1510 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVC697_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVC697_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVC697_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVC697_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_POINT_SIZE 0x1518 +#define NVC697_SET_POINT_SIZE_V 31:0 + +#define NVC697_SET_ZCULL_STATS 0x151c +#define NVC697_SET_ZCULL_STATS_ENABLE 0:0 +#define NVC697_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_POINT_SPRITE 0x1520 +#define NVC697_SET_POINT_SPRITE_ENABLE 0:0 +#define NVC697_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC697_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC697_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC697_CLEAR_REPORT_VALUE 0x1530 +#define NVC697_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVC697_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVC697_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVC697_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVC697_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVC697_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVC697_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC697_CLEAR_REPORT_VALUE_TYPE_SCG_CLOCKS 0x00000009 + +#define NVC697_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVC697_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVC697_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVC697_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVC697_SET_ZT_SELECT 0x1538 +#define NVC697_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVC697_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVC697_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVC697_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVC697_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVC697_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVC697_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVC697_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVC697_SET_RENDER_ENABLE_A 0x1550 +#define NVC697_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_RENDER_ENABLE_B 0x1554 +#define NVC697_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_RENDER_ENABLE_C 0x1558 +#define NVC697_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC697_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC697_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC697_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC697_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC697_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC697_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC697_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC697_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC697_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC697_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVC697_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVC697_SET_ANTI_ALIASED_LINE 0x1570 +#define NVC697_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVC697_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC697_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC697_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_TEX_HEADER_POOL_C 0x157c +#define NVC697_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC697_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVC697_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVC697_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVC697_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVC697_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC697_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC697_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC697_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC697_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC697_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC697_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVC697_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVC697_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC697_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC697_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC697_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC697_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC697_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC697_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC697_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC697_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC697_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC697_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC697_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC697_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC697_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC697_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC697_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC697_SET_SRGB_WRITE 0x15b8 +#define NVC697_SET_SRGB_WRITE_ENABLE 0:0 +#define NVC697_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_DEPTH_BIAS 0x15bc +#define NVC697_SET_DEPTH_BIAS_V 31:0 + +#define NVC697_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVC697_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVC697_SET_RT_LAYER 0x15cc +#define NVC697_SET_RT_LAYER_V 15:0 +#define NVC697_SET_RT_LAYER_CONTROL 16:16 +#define NVC697_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVC697_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVC697_SET_ANTI_ALIAS 0x15d0 +#define NVC697_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVC697_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVC697_SET_EDGE_FLAG 0x15e4 +#define NVC697_SET_EDGE_FLAG_V 0:0 +#define NVC697_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVC697_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVC697_DRAW_INLINE_INDEX 0x15e8 +#define NVC697_DRAW_INLINE_INDEX_V 31:0 + +#define NVC697_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVC697_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVC697_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVC697_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVC697_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVC697_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVC697_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVC697_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVC697_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVC697_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVC697_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVC697_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVC697_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVC697_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVC697_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVC697_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVC697_SET_POINT_SPRITE_SELECT 0x1604 +#define NVC697_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVC697_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVC697_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVC697_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVC697_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVC697_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVC697_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVC697_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVC697_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVC697_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVC697_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVC697_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVC697_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVC697_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVC697_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVC697_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVC697_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVC697_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVC697_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVC697_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVC697_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVC697_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVC697_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVC697_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVC697_END 0x1614 +#define NVC697_END_V 0:0 + +#define NVC697_BEGIN 0x1618 +#define NVC697_BEGIN_OP 15:0 +#define NVC697_BEGIN_OP_POINTS 0x00000000 +#define NVC697_BEGIN_OP_LINES 0x00000001 +#define NVC697_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVC697_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVC697_BEGIN_OP_TRIANGLES 0x00000004 +#define NVC697_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVC697_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVC697_BEGIN_OP_QUADS 0x00000007 +#define NVC697_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVC697_BEGIN_OP_POLYGON 0x00000009 +#define NVC697_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVC697_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVC697_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_BEGIN_OP_PATCH 0x0000000E +#define NVC697_BEGIN_PRIMITIVE_ID 24:24 +#define NVC697_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC697_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC697_BEGIN_INSTANCE_ID 27:26 +#define NVC697_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVC697_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC697_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC697_BEGIN_SPLIT_MODE 30:29 +#define NVC697_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC697_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC697_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC697_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC697_BEGIN_INSTANCE_ITERATE_ENABLE 31:31 +#define NVC697_BEGIN_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC697_BEGIN_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_VERTEX_ID_COPY 0x161c +#define NVC697_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVC697_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVC697_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVC697_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVC697_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVC697_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVC697_LOAD_PRIMITIVE_ID 0x1624 +#define NVC697_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVC697_SET_SHADER_BASED_CULL 0x162c +#define NVC697_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVC697_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVC697_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVC697_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVC697_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_CLASS_VERSION 0x1638 +#define NVC697_SET_CLASS_VERSION_CURRENT 15:0 +#define NVC697_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC697_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVC697_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVC697_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVC697_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVC697_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVC697_SET_DA_OUTPUT 0x164c +#define NVC697_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVC697_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVC697_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVC697_SET_ANTI_ALIASED_POINT 0x1658 +#define NVC697_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVC697_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_POINT_CENTER_MODE 0x165c +#define NVC697_SET_POINT_CENTER_MODE_V 31:0 +#define NVC697_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVC697_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVC697_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVC697_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVC697_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVC697_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVC697_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVC697_SET_LINE_STIPPLE 0x166c +#define NVC697_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVC697_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVC697_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVC697_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVC697_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVC697_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVC697_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVC697_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVC697_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVC697_SET_PROVOKING_VERTEX 0x1684 +#define NVC697_SET_PROVOKING_VERTEX_V 0:0 +#define NVC697_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVC697_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVC697_SET_TWO_SIDED_LIGHT 0x1688 +#define NVC697_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVC697_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_POLYGON_STIPPLE 0x168c +#define NVC697_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVC697_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_SHADER_CONTROL 0x1690 +#define NVC697_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVC697_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVC697_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVC697_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVC697_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC697_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC697_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVC697_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC697_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVC697_CHECK_CLASS_VERSION 0x16a0 +#define NVC697_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVC697_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC697_SET_SPH_VERSION 0x16a4 +#define NVC697_SET_SPH_VERSION_CURRENT 15:0 +#define NVC697_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC697_CHECK_SPH_VERSION 0x16a8 +#define NVC697_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVC697_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC697_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVC697_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVC697_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC697_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVC697_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVC697_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVC697_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVC697_SET_SCG_GRAPHICS_PRIORITY 0x16bc +#define NVC697_SET_SCG_GRAPHICS_PRIORITY_PRIORITY 5:0 + +#define NVC697_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS(i) (0x16c0+(i)*4) +#define NVC697_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS_V 31:0 + +#define NVC697_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVC697_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVC697_SET_AAM_VERSION 0x1790 +#define NVC697_SET_AAM_VERSION_CURRENT 15:0 +#define NVC697_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC697_CHECK_AAM_VERSION 0x1794 +#define NVC697_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVC697_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC697_SET_ZT_LAYER 0x179c +#define NVC697_SET_ZT_LAYER_OFFSET 15:0 + +#define NVC697_SET_INDEX_BUFFER_A 0x17c8 +#define NVC697_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVC697_SET_INDEX_BUFFER_B 0x17cc +#define NVC697_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVC697_SET_INDEX_BUFFER_E 0x17d8 +#define NVC697_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVC697_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVC697_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVC697_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVC697_SET_INDEX_BUFFER_F 0x17dc +#define NVC697_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVC697_DRAW_INDEX_BUFFER 0x17e0 +#define NVC697_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC697_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVC697_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVC697_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVC697_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVC697_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVC697_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVC697_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVC697_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVC697_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVC697_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVC697_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVC697_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVC697_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVC697_OGL_SET_CULL 0x1918 +#define NVC697_OGL_SET_CULL_ENABLE 0:0 +#define NVC697_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVC697_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVC697_OGL_SET_FRONT_FACE 0x191c +#define NVC697_OGL_SET_FRONT_FACE_V 31:0 +#define NVC697_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVC697_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVC697_OGL_SET_CULL_FACE 0x1920 +#define NVC697_OGL_SET_CULL_FACE_V 31:0 +#define NVC697_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVC697_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVC697_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVC697_SET_VIEWPORT_PIXEL 0x1924 +#define NVC697_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVC697_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVC697_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVC697_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVC697_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVC697_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVC697_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE 17:16 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_USE_FIELD_MIN_Z_ZERO_MAX_Z_ONE 0x00000000 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MIN_Z_MAX_Z 0x00000001 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_ZERO_ONE 0x00000002 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MINUS_INF_PLUS_INF 0x00000003 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVC697_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVC697_SET_USER_CLIP_OP 0x1940 +#define NVC697_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVC697_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVC697_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVC697_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVC697_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVC697_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVC697_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVC697_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVC697_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVC697_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVC697_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVC697_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVC697_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVC697_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVC697_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVC697_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVC697_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVC697_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVC697_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVC697_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVC697_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVC697_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVC697_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVC697_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVC697_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC697_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC697_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC697_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC697_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC697_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVC697_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVC697_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVC697_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVC697_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVC697_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVC697_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVC697_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVC697_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVC697_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVC697_INVALIDATE_ZCULL 0x1958 +#define NVC697_INVALIDATE_ZCULL_V 31:0 +#define NVC697_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVC697_SET_ZCULL 0x1968 +#define NVC697_SET_ZCULL_Z_ENABLE 0:0 +#define NVC697_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVC697_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_ZCULL_BOUNDS 0x196c +#define NVC697_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVC697_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVC697_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVC697_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC697_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVC697_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVC697_ZCULL_SYNC 0x1978 +#define NVC697_ZCULL_SYNC_V 31:0 + +#define NVC697_SET_CLIP_ID_TEST 0x197c +#define NVC697_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVC697_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVC697_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVC697_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVC697_SET_CLIP_ID 0x1984 +#define NVC697_SET_CLIP_ID_V 31:0 + +#define NVC697_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVC697_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVC697_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVC697_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVC697_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVC697_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVC697_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVC697_SET_LOGIC_OP 0x19c4 +#define NVC697_SET_LOGIC_OP_ENABLE 0:0 +#define NVC697_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVC697_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_LOGIC_OP_FUNC 0x19c8 +#define NVC697_SET_LOGIC_OP_FUNC_V 31:0 +#define NVC697_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVC697_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVC697_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVC697_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVC697_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVC697_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVC697_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVC697_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVC697_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVC697_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVC697_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVC697_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVC697_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVC697_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVC697_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVC697_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVC697_SET_Z_COMPRESSION 0x19cc +#define NVC697_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVC697_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC697_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC697_CLEAR_SURFACE 0x19d0 +#define NVC697_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVC697_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC697_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC697_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVC697_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC697_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC697_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVC697_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVC697_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVC697_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVC697_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVC697_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVC697_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVC697_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVC697_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVC697_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVC697_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVC697_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVC697_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVC697_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVC697_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVC697_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVC697_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVC697_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVC697_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC697_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVC697_SET_CT_WRITE_R_ENABLE 0:0 +#define NVC697_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVC697_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVC697_SET_CT_WRITE_G_ENABLE 4:4 +#define NVC697_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVC697_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVC697_SET_CT_WRITE_B_ENABLE 8:8 +#define NVC697_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVC697_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVC697_SET_CT_WRITE_A_ENABLE 12:12 +#define NVC697_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVC697_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVC697_PIPE_NOP 0x1a2c +#define NVC697_PIPE_NOP_V 31:0 + +#define NVC697_SET_SPARE00 0x1a30 +#define NVC697_SET_SPARE00_V 31:0 + +#define NVC697_SET_SPARE01 0x1a34 +#define NVC697_SET_SPARE01_V 31:0 + +#define NVC697_SET_SPARE02 0x1a38 +#define NVC697_SET_SPARE02_V 31:0 + +#define NVC697_SET_SPARE03 0x1a3c +#define NVC697_SET_SPARE03_V 31:0 + +#define NVC697_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC697_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC697_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC697_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC697_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC697_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC697_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVC697_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC697_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVC697_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVC697_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC697_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC697_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVC697_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC697_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_SCG_CLOCKS 0x00000008 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC697_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC697_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVC697_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVC697_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC697_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC697_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVC697_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVC697_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVC697_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVC697_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVC697_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVC697_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVC697_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVC697_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVC697_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVC697_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVC697_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVC697_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVC697_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC697_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVC697_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC697_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVC697_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC697_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVC697_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVC697_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVC697_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC697_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC697_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC697_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC697_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC697_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVC697_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVC697_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVC697_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVC697_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVC697_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVC697_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVC697_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVC697_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVC697_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVC697_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVC697_SET_PIPELINE_RESERVED_B(j) (0x2004+(j)*64) +#define NVC697_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVC697_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVC697_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVC697_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVC697_SET_PIPELINE_REGISTER_COUNT_V 8:0 + +#define NVC697_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVC697_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVC697_SET_PIPELINE_PROGRAM_ADDRESS_A(j) (0x2014+(j)*64) +#define NVC697_SET_PIPELINE_PROGRAM_ADDRESS_A_UPPER 7:0 + +#define NVC697_SET_PIPELINE_PROGRAM_ADDRESS_B(j) (0x2018+(j)*64) +#define NVC697_SET_PIPELINE_PROGRAM_ADDRESS_B_LOWER 31:0 + +#define NVC697_SET_PIPELINE_RESERVED_D(j) (0x201c+(j)*64) +#define NVC697_SET_PIPELINE_RESERVED_D_V 0:0 + +#define NVC697_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVC697_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVC697_SET_FALCON00 0x2300 +#define NVC697_SET_FALCON00_V 31:0 + +#define NVC697_SET_FALCON01 0x2304 +#define NVC697_SET_FALCON01_V 31:0 + +#define NVC697_SET_FALCON02 0x2308 +#define NVC697_SET_FALCON02_V 31:0 + +#define NVC697_SET_FALCON03 0x230c +#define NVC697_SET_FALCON03_V 31:0 + +#define NVC697_SET_FALCON04 0x2310 +#define NVC697_SET_FALCON04_V 31:0 + +#define NVC697_SET_FALCON05 0x2314 +#define NVC697_SET_FALCON05_V 31:0 + +#define NVC697_SET_FALCON06 0x2318 +#define NVC697_SET_FALCON06_V 31:0 + +#define NVC697_SET_FALCON07 0x231c +#define NVC697_SET_FALCON07_V 31:0 + +#define NVC697_SET_FALCON08 0x2320 +#define NVC697_SET_FALCON08_V 31:0 + +#define NVC697_SET_FALCON09 0x2324 +#define NVC697_SET_FALCON09_V 31:0 + +#define NVC697_SET_FALCON10 0x2328 +#define NVC697_SET_FALCON10_V 31:0 + +#define NVC697_SET_FALCON11 0x232c +#define NVC697_SET_FALCON11_V 31:0 + +#define NVC697_SET_FALCON12 0x2330 +#define NVC697_SET_FALCON12_V 31:0 + +#define NVC697_SET_FALCON13 0x2334 +#define NVC697_SET_FALCON13_V 31:0 + +#define NVC697_SET_FALCON14 0x2338 +#define NVC697_SET_FALCON14_V 31:0 + +#define NVC697_SET_FALCON15 0x233c +#define NVC697_SET_FALCON15_V 31:0 + +#define NVC697_SET_FALCON16 0x2340 +#define NVC697_SET_FALCON16_V 31:0 + +#define NVC697_SET_FALCON17 0x2344 +#define NVC697_SET_FALCON17_V 31:0 + +#define NVC697_SET_FALCON18 0x2348 +#define NVC697_SET_FALCON18_V 31:0 + +#define NVC697_SET_FALCON19 0x234c +#define NVC697_SET_FALCON19_V 31:0 + +#define NVC697_SET_FALCON20 0x2350 +#define NVC697_SET_FALCON20_V 31:0 + +#define NVC697_SET_FALCON21 0x2354 +#define NVC697_SET_FALCON21_V 31:0 + +#define NVC697_SET_FALCON22 0x2358 +#define NVC697_SET_FALCON22_V 31:0 + +#define NVC697_SET_FALCON23 0x235c +#define NVC697_SET_FALCON23_V 31:0 + +#define NVC697_SET_FALCON24 0x2360 +#define NVC697_SET_FALCON24_V 31:0 + +#define NVC697_SET_FALCON25 0x2364 +#define NVC697_SET_FALCON25_V 31:0 + +#define NVC697_SET_FALCON26 0x2368 +#define NVC697_SET_FALCON26_V 31:0 + +#define NVC697_SET_FALCON27 0x236c +#define NVC697_SET_FALCON27_V 31:0 + +#define NVC697_SET_FALCON28 0x2370 +#define NVC697_SET_FALCON28_V 31:0 + +#define NVC697_SET_FALCON29 0x2374 +#define NVC697_SET_FALCON29_V 31:0 + +#define NVC697_SET_FALCON30 0x2378 +#define NVC697_SET_FALCON30_V 31:0 + +#define NVC697_SET_FALCON31 0x237c +#define NVC697_SET_FALCON31_V 31:0 + +#define NVC697_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVC697_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVC697_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVC697_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVC697_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVC697_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVC697_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVC697_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVC697_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVC697_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVC697_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVC697_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVC697_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVC697_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVC697_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVC697_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVC697_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVC697_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVC697_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVC697_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVC697_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC697_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC697_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVC697_SET_TRAP_HANDLER_A 0x25f8 +#define NVC697_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC697_SET_TRAP_HANDLER_B 0x25fc +#define NVC697_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC697_SET_COLOR_CLAMP 0x2600 +#define NVC697_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVC697_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVC697_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVC697_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVC697_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVC697_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVC697_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVC697_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVC697_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC697_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC697_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC697_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC697_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC697_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC697_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC697_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC697_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC697_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC697_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC697_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC697_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC697_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC697_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVC697_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVC697_CALL_MME_MACRO_V 31:0 + +#define NVC697_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVC697_CALL_MME_DATA_V 31:0 + +#endif /* _cl_ampere_a_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/clc6b5sw.h b/src/common/sdk/nvidia/inc/class/clc6b5sw.h index d9d15ea5e..7a928aa66 100644 --- a/src/common/sdk/nvidia/inc/class/clc6b5sw.h +++ b/src/common/sdk/nvidia/inc/class/clc6b5sw.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,38 +21,34 @@ * DEALINGS IN THE SOFTWARE. */ -#include "nvtypes.h" +#pragma once -#ifndef _clc6b5sw_h_ -#define _clc6b5sw_h_ +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc6b5sw.finn +// -#ifdef __cplusplus -extern "C" { -#endif -/* This file is *not* auto-generated. */ // // Using VERSION_0 will cause the API to interpret // engineType as a CE engine instance. This allows // for backward compatibility with 85B5sw and 90B5sw. // -#define NVC6B5_ALLOCATION_PARAMETERS_VERSION_0 0 +#define NVC6B5_ALLOCATION_PARAMETERS_VERSION_0 0 // // Using VERSION_1 will cause the API to interpret // engineType as an NV2080_ENGINE_TYPE ordinal. // -#define NVC6B5_ALLOCATION_PARAMETERS_VERSION_1 1 +#define NVC6B5_ALLOCATION_PARAMETERS_VERSION_1 1 -typedef struct -{ - NvU32 version; - NvU32 engineType; +#define NVC6B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc6b5U) + +typedef struct NVC6B5_ALLOCATION_PARAMETERS { + NvU32 version; + NvU32 engineType; } NVC6B5_ALLOCATION_PARAMETERS; -#ifdef __cplusplus -}; /* extern "C" */ -#endif -#endif // _clc5b5sw_h_ - diff --git a/src/common/sdk/nvidia/inc/class/clc770.h b/src/common/sdk/nvidia/inc/class/clc770.h index 940d7762c..4f6691680 100644 --- a/src/common/sdk/nvidia/inc/class/clc770.h +++ b/src/common/sdk/nvidia/inc/class/clc770.h @@ -20,19 +20,16 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _clc770_h_ -#define _clc770_h_ +#pragma once -#ifdef __cplusplus -extern "C" { -#endif +#include -#include "nvtypes.h" +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/clc770.finn +// + +#define NVC770_DISPLAY (0xc770U) /* finn: Evaluated from "NVC770_ALLOCATION_PARAMETERS_MESSAGE_ID" */ -#define NVC770_DISPLAY (0x0000C770) -#ifdef __cplusplus -}; /* extern "C" */ -#endif -#endif /* _clc770_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/clc77f.h b/src/common/sdk/nvidia/inc/class/clc77f.h new file mode 100644 index 000000000..3651a58a6 --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/clc77f.h @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clC77F_h_ +#define _clC77F_h_ + +// +// This class provides functional support of Display ANYChannel, Display Contextdmas bound to +// ANYChannel can be used on any other display window channels. +// +#define NVC77F_ANY_CHANNEL_DMA (0x0000C77F) + +#endif // _clC77F_h_ + diff --git a/src/common/sdk/nvidia/inc/class/clc797.h b/src/common/sdk/nvidia/inc/class/clc797.h index 251b6e1cc..dc4b6001c 100644 --- a/src/common/sdk/nvidia/inc/class/clc797.h +++ b/src/common/sdk/nvidia/inc/class/clc797.h @@ -1,29 +1,4481 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. -#ifndef _clc797_h_ -#define _clc797_h_ + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cl_ampere_b_h_ +#define _cl_ampere_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl ampere_b */ + +#include "nvtypes.h" #define AMPERE_B 0xC797 -#endif // _clc797_h_ +#define NVC797_SET_OBJECT 0x0000 +#define NVC797_SET_OBJECT_CLASS_ID 15:0 +#define NVC797_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC797_NO_OPERATION 0x0100 +#define NVC797_NO_OPERATION_V 31:0 + +#define NVC797_SET_NOTIFY_A 0x0104 +#define NVC797_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC797_SET_NOTIFY_B 0x0108 +#define NVC797_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC797_NOTIFY 0x010c +#define NVC797_NOTIFY_TYPE 31:0 +#define NVC797_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC797_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC797_WAIT_FOR_IDLE 0x0110 +#define NVC797_WAIT_FOR_IDLE_V 31:0 + +#define NVC797_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVC797_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVC797_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVC797_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVC797_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVC797_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVC797_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVC797_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVC797_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVC797_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVC797_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVC797_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVC797_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVC797_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVC797_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVC797_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVC797_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVC797_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVC797_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC797_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC797_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC797_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC797_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC797_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC797_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC797_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC797_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC797_SEND_GO_IDLE 0x013c +#define NVC797_SEND_GO_IDLE_V 31:0 + +#define NVC797_PM_TRIGGER 0x0140 +#define NVC797_PM_TRIGGER_V 31:0 + +#define NVC797_PM_TRIGGER_WFI 0x0144 +#define NVC797_PM_TRIGGER_WFI_V 31:0 + +#define NVC797_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC797_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC797_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC797_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC797_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC797_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC797_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC797_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC797_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER 0x0158 +#define NVC797_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER_PAYLOAD_LOWER 31:0 + +#define NVC797_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER 0x015c +#define NVC797_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD_UPPER 31:0 + +#define NVC797_SET_REPORT_SEMAPHORE_ADDRESS_LOWER 0x0160 +#define NVC797_SET_REPORT_SEMAPHORE_ADDRESS_LOWER_LOWER 31:0 + +#define NVC797_SET_REPORT_SEMAPHORE_ADDRESS_UPPER 0x0164 +#define NVC797_SET_REPORT_SEMAPHORE_ADDRESS_UPPER_UPPER 7:0 + +#define NVC797_REPORT_SEMAPHORE_EXECUTE 0x0168 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_OPERATION 1:0 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_OPERATION_RELEASE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_OPERATION_ACQUIRE 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_OPERATION_REPORT_ONLY 0x00000002 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_OPERATION_TRAP 0x00000003 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION 5:2 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC797_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE 6:6 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT 11:7 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_NONE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_SCG_CLOCKS 0x00000008 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS0 0x0000000A +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS1 0x0000000C +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS2 0x0000000E +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS3 0x00000010 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REPORT_TIMESTAMP 0x00000014 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE 14:13 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_SUB_REPORT 17:15 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE 19:19 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE 18:18 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE 20:20 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP 23:21 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_INC 0x00000003 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_AND 0x00000005 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_OR 0x00000006 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT 25:24 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64 27:27 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_FALSE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_TRUE 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE 29:28 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_NONE 0x00000000 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_UNCONDITIONAL 0x00000001 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL 0x00000002 +#define NVC797_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x00000003 + +#define NVC797_LINE_LENGTH_IN 0x0180 +#define NVC797_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC797_LINE_COUNT 0x0184 +#define NVC797_LINE_COUNT_VALUE 31:0 + +#define NVC797_OFFSET_OUT_UPPER 0x0188 +#define NVC797_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVC797_OFFSET_OUT 0x018c +#define NVC797_OFFSET_OUT_VALUE 31:0 + +#define NVC797_PITCH_OUT 0x0190 +#define NVC797_PITCH_OUT_VALUE 31:0 + +#define NVC797_SET_DST_BLOCK_SIZE 0x0194 +#define NVC797_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC797_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC797_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC797_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC797_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC797_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC797_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC797_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC797_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC797_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC797_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC797_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC797_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC797_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC797_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC797_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC797_SET_DST_WIDTH 0x0198 +#define NVC797_SET_DST_WIDTH_V 31:0 + +#define NVC797_SET_DST_HEIGHT 0x019c +#define NVC797_SET_DST_HEIGHT_V 31:0 + +#define NVC797_SET_DST_DEPTH 0x01a0 +#define NVC797_SET_DST_DEPTH_V 31:0 + +#define NVC797_SET_DST_LAYER 0x01a4 +#define NVC797_SET_DST_LAYER_V 31:0 + +#define NVC797_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC797_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC797_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC797_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC797_LAUNCH_DMA 0x01b0 +#define NVC797_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC797_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC797_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC797_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC797_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC797_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC797_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC797_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC797_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC797_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC797_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC797_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC797_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC797_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC797_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC797_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC797_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC797_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC797_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC797_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC797_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC797_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC797_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC797_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC797_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC797_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC797_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC797_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC797_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC797_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC797_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC797_LOAD_INLINE_DATA 0x01b4 +#define NVC797_LOAD_INLINE_DATA_V 31:0 + +#define NVC797_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC797_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC797_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC797_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC797_SET_MME_SWITCH_STATE 0x01ec +#define NVC797_SET_MME_SWITCH_STATE_VALID 0:0 +#define NVC797_SET_MME_SWITCH_STATE_VALID_FALSE 0x00000000 +#define NVC797_SET_MME_SWITCH_STATE_VALID_TRUE 0x00000001 +#define NVC797_SET_MME_SWITCH_STATE_SAVE_MACRO 11:4 +#define NVC797_SET_MME_SWITCH_STATE_RESTORE_MACRO 19:12 + +#define NVC797_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC797_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC797_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC797_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC797_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC797_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC797_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC797_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC797_RUN_DS_NOW 0x0200 +#define NVC797_RUN_DS_NOW_V 31:0 + +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVC797_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVC797_SET_GS_MODE 0x0208 +#define NVC797_SET_GS_MODE_TYPE 0:0 +#define NVC797_SET_GS_MODE_TYPE_ANY 0x00000000 +#define NVC797_SET_GS_MODE_TYPE_FAST_GS 0x00000001 + +#define NVC797_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVC797_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVC797_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVC797_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVC797_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVC797_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVC797_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVC797_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_GS_DM_FIFO 0x0214 +#define NVC797_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVC797_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVC797_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVC797_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVC797_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC797_INVALIDATE_SHADER_CACHES 0x021c +#define NVC797_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC797_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC797_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC797_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC797_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC797_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC797_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC797_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC797_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC797_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC797_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC797_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC797_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC797_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC797_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC797_SET_INSTANCE_COUNT 0x0220 +#define NVC797_SET_INSTANCE_COUNT_V 31:0 + +#define NVC797_SET_POSITION_W_SCALED_OFFSET_ENABLE 0x0224 +#define NVC797_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE 0:0 +#define NVC797_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_GO_IDLE_TIMEOUT 0x022c +#define NVC797_SET_GO_IDLE_TIMEOUT_V 31:0 + +#define NVC797_SET_MME_VERSION 0x0234 +#define NVC797_SET_MME_VERSION_MAJOR 7:0 + +#define NVC797_SET_INDEX_BUFFER_SIZE_A 0x0238 +#define NVC797_SET_INDEX_BUFFER_SIZE_A_UPPER 7:0 + +#define NVC797_SET_INDEX_BUFFER_SIZE_B 0x023c +#define NVC797_SET_INDEX_BUFFER_SIZE_B_LOWER 31:0 + +#define NVC797_SET_ROOT_TABLE_VISIBILITY(i) (0x0240+(i)*4) +#define NVC797_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP0_ENABLE 1:0 +#define NVC797_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP1_ENABLE 5:4 +#define NVC797_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP2_ENABLE 9:8 +#define NVC797_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP3_ENABLE 13:12 +#define NVC797_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP4_ENABLE 17:16 + +#define NVC797_SET_DRAW_CONTROL_A 0x0260 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY 3:0 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_POINTS 0x00000000 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_LINES 0x00000001 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_QUADS 0x00000007 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_SET_DRAW_CONTROL_A_TOPOLOGY_PATCH 0x0000000E +#define NVC797_SET_DRAW_CONTROL_A_PRIMITIVE_ID 4:4 +#define NVC797_SET_DRAW_CONTROL_A_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC797_SET_DRAW_CONTROL_A_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC797_SET_DRAW_CONTROL_A_INSTANCE_ID 6:5 +#define NVC797_SET_DRAW_CONTROL_A_INSTANCE_ID_FIRST 0x00000000 +#define NVC797_SET_DRAW_CONTROL_A_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC797_SET_DRAW_CONTROL_A_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC797_SET_DRAW_CONTROL_A_SPLIT_MODE 8:7 +#define NVC797_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC797_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC797_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC797_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC797_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE 9:9 +#define NVC797_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 +#define NVC797_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX 10:10 +#define NVC797_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_FALSE 0x00000000 +#define NVC797_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_TRUE 0x00000001 +#define NVC797_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX 11:11 +#define NVC797_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_FALSE 0x00000000 +#define NVC797_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_TRUE 0x00000001 + +#define NVC797_SET_DRAW_CONTROL_B 0x0264 +#define NVC797_SET_DRAW_CONTROL_B_INSTANCE_COUNT 31:0 + +#define NVC797_DRAW_INDEX_BUFFER_BEGIN_END_A 0x0268 +#define NVC797_DRAW_INDEX_BUFFER_BEGIN_END_A_FIRST 31:0 + +#define NVC797_DRAW_INDEX_BUFFER_BEGIN_END_B 0x026c +#define NVC797_DRAW_INDEX_BUFFER_BEGIN_END_B_COUNT 31:0 + +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_A 0x0270 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_A_START 31:0 + +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_B 0x0274 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_B_COUNT 31:0 + +#define NVC797_INVALIDATE_RASTER_CACHE_NO_WFI 0x027c +#define NVC797_INVALIDATE_RASTER_CACHE_NO_WFI_V 0:0 + +#define NVC797_SET_COLOR_RENDER_TO_ZETA_SURFACE 0x02b8 +#define NVC797_SET_COLOR_RENDER_TO_ZETA_SURFACE_V 0:0 +#define NVC797_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_FALSE 0x00000000 +#define NVC797_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_TRUE 0x00000001 + +#define NVC797_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION 0x02bc +#define NVC797_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V 0:0 +#define NVC797_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_FALSE 0x00000000 +#define NVC797_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_TRUE 0x00000001 + +#define NVC797_INCREMENT_SYNC_POINT 0x02c8 +#define NVC797_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVC797_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVC797_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVC797_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVC797_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVC797_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVC797_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVC797_SET_ROOT_TABLE_PREFETCH 0x02d0 +#define NVC797_SET_ROOT_TABLE_PREFETCH_STAGE_ENABLES 5:0 + +#define NVC797_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVC797_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVC797_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC797_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVC797_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVC797_DECOMPRESS_SURFACE 0x02e0 +#define NVC797_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVC797_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVC797_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVC797_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVC797_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVC797_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVC797_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVC797_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVC797_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVC797_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVC797_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVC797_SET_ZCULL_SUBREGION 0x02e8 +#define NVC797_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVC797_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVC797_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVC797_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVC797_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVC797_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVC797_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVC797_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVC797_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVC797_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVC797_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVC797_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVC797_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVC797_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVC797_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVC797_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVC797_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVC797_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVC797_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVC797_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVC797_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVC797_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVC797_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVC797_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVC797_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC797_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVC797_DRAW_ZERO_INDEX 0x0304 +#define NVC797_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVC797_SET_L1_CONFIGURATION 0x0308 +#define NVC797_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVC797_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC797_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVC797_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVC797_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVC797_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVC797_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVC797_SET_SPA_VERSION 0x0310 +#define NVC797_SET_SPA_VERSION_MINOR 7:0 +#define NVC797_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC797_SET_TIMESLICE_BATCH_LIMIT 0x0314 +#define NVC797_SET_TIMESLICE_BATCH_LIMIT_BATCH_LIMIT 15:0 + +#define NVC797_SET_SNAP_GRID_LINE 0x0318 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC797_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC797_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVC797_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC797_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC797_SET_SNAP_GRID_NON_LINE 0x031c +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC797_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC797_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVC797_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC797_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC797_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVC797_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVC797_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVC797_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVC797_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVC797_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVC797_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVC797_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVC797_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVC797_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVC797_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVC797_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVC797_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVC797_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVC797_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVC797_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVC797_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVC797_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVC797_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVC797_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVC797_SET_TESSELLATION_LOD_V1 0x0330 +#define NVC797_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVC797_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVC797_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVC797_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVC797_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVC797_RESERVED_TG07 0x033c +#define NVC797_RESERVED_TG07_V 0:0 + +#define NVC797_RESERVED_TG08 0x0340 +#define NVC797_RESERVED_TG08_V 0:0 + +#define NVC797_RESERVED_TG09 0x0344 +#define NVC797_RESERVED_TG09_V 0:0 + +#define NVC797_RESERVED_TG10 0x0348 +#define NVC797_RESERVED_TG10_V 0:0 + +#define NVC797_RESERVED_TG11 0x034c +#define NVC797_RESERVED_TG11_V 0:0 + +#define NVC797_RESERVED_TG12 0x0350 +#define NVC797_RESERVED_TG12_V 0:0 + +#define NVC797_RESERVED_TG13 0x0354 +#define NVC797_RESERVED_TG13_V 0:0 + +#define NVC797_RESERVED_TG14 0x0358 +#define NVC797_RESERVED_TG14_V 0:0 + +#define NVC797_RESERVED_TG15 0x035c +#define NVC797_RESERVED_TG15_V 0:0 + +#define NVC797_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVC797_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVC797_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVC797_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVC797_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVC797_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVC797_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVC797_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVC797_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVC797_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVC797_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVC797_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVC797_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE 8:8 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE 9:9 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC797_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVC797_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVC797_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVC797_SET_RASTER_ENABLE 0x037c +#define NVC797_SET_RASTER_ENABLE_V 0:0 +#define NVC797_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVC797_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVC797_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVC797_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVC797_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVC797_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVC797_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVC797_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVC797_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVC797_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVC797_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVC797_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVC797_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVC797_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVC797_SET_POSITION_W_SCALED_OFFSET_SCALE_A(j) (0x0400+(j)*16) +#define NVC797_SET_POSITION_W_SCALED_OFFSET_SCALE_A_V 31:0 + +#define NVC797_SET_POSITION_W_SCALED_OFFSET_SCALE_B(j) (0x0404+(j)*16) +#define NVC797_SET_POSITION_W_SCALED_OFFSET_SCALE_B_V 31:0 + +#define NVC797_SET_POSITION_W_SCALED_OFFSET_RESERVED_A(j) (0x0408+(j)*16) +#define NVC797_SET_POSITION_W_SCALED_OFFSET_RESERVED_A_V 31:0 + +#define NVC797_SET_POSITION_W_SCALED_OFFSET_RESERVED_B(j) (0x040c+(j)*16) +#define NVC797_SET_POSITION_W_SCALED_OFFSET_RESERVED_B_V 31:0 + +#define NVC797_SET_Z_ROP_SLICE_MAP 0x0500 +#define NVC797_SET_Z_ROP_SLICE_MAP_VIRTUAL_ADDRESS_MASK 31:0 + +#define NVC797_SET_ROOT_TABLE_SELECTOR 0x0504 +#define NVC797_SET_ROOT_TABLE_SELECTOR_ROOT_TABLE 2:0 +#define NVC797_SET_ROOT_TABLE_SELECTOR_OFFSET 15:8 + +#define NVC797_LOAD_ROOT_TABLE 0x0508 +#define NVC797_LOAD_ROOT_TABLE_V 31:0 + +#define NVC797_SET_MME_MEM_ADDRESS_A 0x0550 +#define NVC797_SET_MME_MEM_ADDRESS_A_UPPER 16:0 + +#define NVC797_SET_MME_MEM_ADDRESS_B 0x0554 +#define NVC797_SET_MME_MEM_ADDRESS_B_LOWER 31:0 + +#define NVC797_SET_MME_DATA_RAM_ADDRESS 0x0558 +#define NVC797_SET_MME_DATA_RAM_ADDRESS_WORD 31:0 + +#define NVC797_MME_DMA_READ 0x055c +#define NVC797_MME_DMA_READ_LENGTH 31:0 + +#define NVC797_MME_DMA_READ_FIFOED 0x0560 +#define NVC797_MME_DMA_READ_FIFOED_LENGTH 31:0 + +#define NVC797_MME_DMA_WRITE 0x0564 +#define NVC797_MME_DMA_WRITE_LENGTH 31:0 + +#define NVC797_MME_DMA_REDUCTION 0x0568 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP 2:0 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP_RED_INC 0x00000003 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP_RED_AND 0x00000005 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP_RED_OR 0x00000006 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_FORMAT 5:4 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_SIZE 8:8 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_SIZE_FOUR_BYTES 0x00000000 +#define NVC797_MME_DMA_REDUCTION_REDUCTION_SIZE_EIGHT_BYTES 0x00000001 + +#define NVC797_MME_DMA_SYSMEMBAR 0x056c +#define NVC797_MME_DMA_SYSMEMBAR_V 0:0 + +#define NVC797_MME_DMA_SYNC 0x0570 +#define NVC797_MME_DMA_SYNC_VALUE 31:0 + +#define NVC797_SET_MME_DATA_FIFO_CONFIG 0x0574 +#define NVC797_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE 2:0 +#define NVC797_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_0KB 0x00000000 +#define NVC797_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_4KB 0x00000001 +#define NVC797_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_8KB 0x00000002 +#define NVC797_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_12KB 0x00000003 +#define NVC797_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_16KB 0x00000004 + +#define NVC797_SET_VERTEX_STREAM_SIZE_A(j) (0x0600+(j)*8) +#define NVC797_SET_VERTEX_STREAM_SIZE_A_UPPER 7:0 + +#define NVC797_SET_VERTEX_STREAM_SIZE_B(j) (0x0604+(j)*8) +#define NVC797_SET_VERTEX_STREAM_SIZE_B_LOWER 31:0 + +#define NVC797_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVC797_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVC797_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVC797_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVC797_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVC797_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVC797_SET_RASTER_INPUT 0x0740 +#define NVC797_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVC797_SET_STREAM_OUTPUT 0x0744 +#define NVC797_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVC797_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVC797_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVC797_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVC797_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVC797_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVC797_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVC797_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVC797_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVC797_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC797_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC797_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC797_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVC797_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC797_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC797_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVC797_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVC797_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVC797_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVC797_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVC797_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVC797_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVC797_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC797_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVC797_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC797_SET_STENCIL_ZERO_BANDWIDTH_CLEAR 0x07b0 +#define NVC797_SET_STENCIL_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC797_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVC797_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVC797_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVC797_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVC797_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVC797_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVC797_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVC797_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVC797_SET_CULL_BEFORE_FETCH 0x07dc +#define NVC797_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVC797_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVC797_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVC797_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVC797_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVC797_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVC797_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVC797_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVC797_SET_ZCULL_STORAGE_A 0x07e8 +#define NVC797_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVC797_SET_ZCULL_STORAGE_B 0x07ec +#define NVC797_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVC797_SET_ZCULL_STORAGE_C 0x07f0 +#define NVC797_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC797_SET_ZCULL_STORAGE_D 0x07f4 +#define NVC797_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC797_SET_ZT_READ_ONLY 0x07f8 +#define NVC797_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVC797_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVC797_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVC797_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVC797_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVC797_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVC797_THROTTLE_SM 0x07fc +#define NVC797_THROTTLE_SM_MULTIPLY_ADD 0:0 +#define NVC797_THROTTLE_SM_MULTIPLY_ADD_FALSE 0x00000000 +#define NVC797_THROTTLE_SM_MULTIPLY_ADD_TRUE 0x00000001 + +#define NVC797_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVC797_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVC797_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVC797_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVC797_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVC797_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVC797_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVC797_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVC797_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVC797_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVC797_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVC797_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVC797_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVC797_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVC797_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVC797_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVC797_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVC797_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVC797_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVC797_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC797_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC797_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVC797_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC797_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC797_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVC797_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC797_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVC797_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVC797_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVC797_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVC797_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVC797_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVC797_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVC797_SET_COLOR_TARGET_C_ROP_SLICE_MAP(j) (0x0824+(j)*64) +#define NVC797_SET_COLOR_TARGET_C_ROP_SLICE_MAP_VIRTUAL_ADDRESS_MASK 31:0 + +#define NVC797_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVC797_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVC797_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVC797_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVC797_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVC797_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVC797_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVC797_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVC797_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVC797_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVC797_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVC797_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVC797_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVC797_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVC797_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVC797_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVC797_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVC797_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVC797_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC797_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVC797_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVC797_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC797_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVC797_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVC797_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVC797_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVC797_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVC797_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVC797_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVC797_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVC797_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVC797_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVC797_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVC797_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVC797_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVC797_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVC797_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVC797_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVC797_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVC797_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC797_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVC797_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVC797_SET_STATISTICS_COUNTER 0x0d68 +#define NVC797_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVC797_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVC797_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVC797_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVC797_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVC797_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVC797_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVC797_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVC797_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVC797_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVC797_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVC797_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVC797_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVC797_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVC797_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVC797_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVC797_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 +#define NVC797_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE 16:16 +#define NVC797_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVC797_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC797_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC797_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVC797_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC797_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC797_SET_VERTEX_ARRAY_START 0x0d74 +#define NVC797_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVC797_DRAW_VERTEX_ARRAY 0x0d78 +#define NVC797_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVC797_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVC797_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVC797_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVC797_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVC797_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVC797_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVC797_SET_Z_CLEAR_VALUE 0x0d90 +#define NVC797_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVC797_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC797_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC797_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC797_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVC797_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVC797_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVC797_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC797_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC797_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVC797_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVC797_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVC797_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVC797_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVC797_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVC797_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVC797_SET_FRONT_POLYGON_MODE 0x0dac +#define NVC797_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVC797_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC797_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC797_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC797_SET_BACK_POLYGON_MODE 0x0db0 +#define NVC797_SET_BACK_POLYGON_MODE_V 31:0 +#define NVC797_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC797_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC797_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC797_SET_POLY_SMOOTH 0x0db4 +#define NVC797_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVC797_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVC797_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVC797_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVC797_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVC797_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVC797_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVC797_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVC797_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVC797_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVC797_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVC797_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVC797_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVC797_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVC797_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVC797_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVC797_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVC797_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVC797_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_PATCH 0x0dcc +#define NVC797_SET_PATCH_SIZE 7:0 + +#define NVC797_SET_ITERATED_BLEND 0x0dd0 +#define NVC797_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVC797_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVC797_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVC797_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVC797_SET_ZCULL_CRITERION 0x0dd8 +#define NVC797_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVC797_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVC797_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVC797_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVC797_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVC797_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVC797_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVC797_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVC797_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVC797_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVC797_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVC797_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVC797_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVC797_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVC797_SET_ZCULL_CRITERION_SREF 23:16 +#define NVC797_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVC797_PIXEL_SHADER_BARRIER 0x0de0 +#define NVC797_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVC797_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVC797_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 +#define NVC797_PIXEL_SHADER_BARRIER_BARRIER_LOCATION 1:1 +#define NVC797_PIXEL_SHADER_BARRIER_BARRIER_LOCATION_BLOCK_BEFORE_PS 0x00000000 +#define NVC797_PIXEL_SHADER_BARRIER_BARRIER_LOCATION_BLOCK_BEFORE_PS_AND_ZTEST 0x00000001 + +#define NVC797_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC797_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC797_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVC797_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVC797_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVC797_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVC797_MME_DMA_WRITE_METHOD_BARRIER 0x0dec +#define NVC797_MME_DMA_WRITE_METHOD_BARRIER_V 0:0 + +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVC797_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVC797_SET_WINDOW_OFFSET_X 0x0df8 +#define NVC797_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVC797_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVC797_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVC797_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVC797_SET_SCISSOR_ENABLE_V 0:0 +#define NVC797_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVC797_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVC797_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVC797_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVC797_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVC797_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVC797_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVC797_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVC797_SET_VPC_PERF_KNOB 0x0f14 +#define NVC797_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVC797_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVC797_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVC797_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVC797_PM_LOCAL_TRIGGER 0x0f18 +#define NVC797_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVC797_SET_POST_Z_PS_IMASK 0x0f1c +#define NVC797_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVC797_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVC797_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVC797_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVC797_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVC797_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVC797_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVC797_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVC797_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVC797_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVC797_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVC797_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVC797_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVC797_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVC797_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVC797_SET_BACK_STENCIL_MASK 0x0f58 +#define NVC797_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVC797_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVC797_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVC797_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVC797_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVC797_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVC797_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVC797_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVC797_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVC797_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVC797_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVC797_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVC797_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVC797_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVC797_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVC797_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVC797_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVC797_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVC797_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVC797_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVC797_SET_SAMPLE_MASK 0x0fa4 +#define NVC797_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVC797_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVC797_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVC797_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVC797_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVC797_SET_CT_MRT_ENABLE 0x0fac +#define NVC797_SET_CT_MRT_ENABLE_V 0:0 +#define NVC797_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVC797_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVC797_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVC797_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVC797_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVC797_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVC797_SET_TIR 0x0fb4 +#define NVC797_SET_TIR_MODE 1:0 +#define NVC797_SET_TIR_MODE_DISABLED 0x00000000 +#define NVC797_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVC797_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVC797_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVC797_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVC797_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVC797_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC797_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC797_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVC797_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVC797_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVC797_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVC797_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVC797_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVC797_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVC797_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVC797_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVC797_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVC797_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVC797_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_TIR_MODULATION 0x0fd4 +#define NVC797_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVC797_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVC797_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVC797_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVC797_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVC797_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVC797_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVC797_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVC797_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVC797_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVC797_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVC797_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVC797_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVC797_SET_ZT_A 0x0fe0 +#define NVC797_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_ZT_B 0x0fe4 +#define NVC797_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_ZT_FORMAT 0x0fe8 +#define NVC797_SET_ZT_FORMAT_V 4:0 +#define NVC797_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVC797_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVC797_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVC797_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVC797_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVC797_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVC797_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVC797_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVC797_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVC797_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVC797_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVC797_SET_ZT_BLOCK_SIZE 0x0fec +#define NVC797_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVC797_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC797_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVC797_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC797_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC797_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC797_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC797_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC797_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC797_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVC797_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC797_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVC797_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVC797_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVC797_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVC797_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC797_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVC797_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVC797_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC797_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC797_SET_VIEWPORT_MULTICAST 0x1004 +#define NVC797_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVC797_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVC797_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVC797_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVC797_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVC797_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVC797_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC797_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVC797_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVC797_SET_RESERVED_SW_METHOD00 0x1014 +#define NVC797_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC797_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVC797_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC797_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVC797_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC797_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVC797_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC797_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVC797_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC797_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_RESERVED_SW_METHOD01 0x1028 +#define NVC797_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD02 0x102c +#define NVC797_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC797_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVC797_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVC797_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVC797_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVC797_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVC797_SET_SPARE_NOOP01 0x1044 +#define NVC797_SET_SPARE_NOOP01_V 31:0 + +#define NVC797_SET_SPARE_NOOP02 0x1048 +#define NVC797_SET_SPARE_NOOP02_V 31:0 + +#define NVC797_SET_SPARE_NOOP03 0x104c +#define NVC797_SET_SPARE_NOOP03_V 31:0 + +#define NVC797_SET_SPARE_NOOP04 0x1050 +#define NVC797_SET_SPARE_NOOP04_V 31:0 + +#define NVC797_SET_SPARE_NOOP05 0x1054 +#define NVC797_SET_SPARE_NOOP05_V 31:0 + +#define NVC797_SET_SPARE_NOOP06 0x1058 +#define NVC797_SET_SPARE_NOOP06_V 31:0 + +#define NVC797_SET_SPARE_NOOP07 0x105c +#define NVC797_SET_SPARE_NOOP07_V 31:0 + +#define NVC797_SET_SPARE_NOOP08 0x1060 +#define NVC797_SET_SPARE_NOOP08_V 31:0 + +#define NVC797_SET_SPARE_NOOP09 0x1064 +#define NVC797_SET_SPARE_NOOP09_V 31:0 + +#define NVC797_SET_SPARE_NOOP10 0x1068 +#define NVC797_SET_SPARE_NOOP10_V 31:0 + +#define NVC797_SET_SPARE_NOOP11 0x106c +#define NVC797_SET_SPARE_NOOP11_V 31:0 + +#define NVC797_SET_SPARE_NOOP12 0x1070 +#define NVC797_SET_SPARE_NOOP12_V 31:0 + +#define NVC797_SET_SPARE_NOOP13 0x1074 +#define NVC797_SET_SPARE_NOOP13_V 31:0 + +#define NVC797_SET_SPARE_NOOP14 0x1078 +#define NVC797_SET_SPARE_NOOP14_V 31:0 + +#define NVC797_SET_SPARE_NOOP15 0x107c +#define NVC797_SET_SPARE_NOOP15_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVC797_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVC797_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVC797_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD06 0x10bc +#define NVC797_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVC797_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVC797_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVC797_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVC797_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVC797_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVC797_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVC797_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD13 0x10dc +#define NVC797_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC797_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVC797_UNBIND_ALL 0x10f4 +#define NVC797_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVC797_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVC797_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVC797_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVC797_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC797_SET_RESERVED_SW_METHOD14 0x1100 +#define NVC797_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC797_SET_RESERVED_SW_METHOD15 0x1104 +#define NVC797_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC797_NO_OPERATION_DATA_HI 0x110c +#define NVC797_NO_OPERATION_DATA_HI_V 31:0 + +#define NVC797_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVC797_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVC797_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVC797_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVC797_PM_TRIGGER_END 0x1114 +#define NVC797_PM_TRIGGER_END_V 31:0 + +#define NVC797_SET_VERTEX_ID_BASE 0x1118 +#define NVC797_SET_VERTEX_ID_BASE_V 31:0 + +#define NVC797_SET_STENCIL_COMPRESSION 0x111c +#define NVC797_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVC797_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC797_SET_TIR_CONTROL 0x1130 +#define NVC797_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVC797_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC797_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC797_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVC797_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC797_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC797_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVC797_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVC797_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 +#define NVC797_SET_TIR_CONTROL_REDUCTION_MODE 2:2 +#define NVC797_SET_TIR_CONTROL_REDUCTION_MODE_AFFINITY_MAP 0x00000000 +#define NVC797_SET_TIR_CONTROL_REDUCTION_MODE_TRUNCATION 0x00000001 + +#define NVC797_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVC797_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVC797_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVC797_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVC797_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVC797_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVC797_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVC797_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVC797_SET_FILL_VIA_TRIANGLE 0x113c +#define NVC797_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVC797_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVC797_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVC797_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVC797_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVC797_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVC797_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVC797_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVC797_FLUSH_PENDING_WRITES 0x1144 +#define NVC797_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVC797_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVC797_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC797_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC797_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC797_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVC797_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC797_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC797_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVC797_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVC797_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVC797_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVC797_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVC797_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVC797_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVC797_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVC797_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVC797_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVC797_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVC797_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVC797_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVC797_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVC797_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVC797_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC797_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC797_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVC797_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC797_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_SCREEN_STATE_MASK 0x1204 +#define NVC797_SET_SCREEN_STATE_MASK_MASK 3:0 + +#define NVC797_SET_ZT_SPARSE 0x1208 +#define NVC797_SET_ZT_SPARSE_ENABLE 0:0 +#define NVC797_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVC797_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVC797_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC797_SET_CT_SELECT 0x121c +#define NVC797_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVC797_SET_CT_SELECT_TARGET0 6:4 +#define NVC797_SET_CT_SELECT_TARGET1 9:7 +#define NVC797_SET_CT_SELECT_TARGET2 12:10 +#define NVC797_SET_CT_SELECT_TARGET3 15:13 +#define NVC797_SET_CT_SELECT_TARGET4 18:16 +#define NVC797_SET_CT_SELECT_TARGET5 21:19 +#define NVC797_SET_CT_SELECT_TARGET6 24:22 +#define NVC797_SET_CT_SELECT_TARGET7 27:25 + +#define NVC797_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVC797_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVC797_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVC797_SET_ZT_SIZE_A 0x1228 +#define NVC797_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVC797_SET_ZT_SIZE_B 0x122c +#define NVC797_SET_ZT_SIZE_B_HEIGHT 17:0 + +#define NVC797_SET_ZT_SIZE_C 0x1230 +#define NVC797_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVC797_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVC797_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC797_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVC797_SET_SAMPLER_BINDING 0x1234 +#define NVC797_SET_SAMPLER_BINDING_V 0:0 +#define NVC797_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVC797_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVC797_DRAW_AUTO 0x123c +#define NVC797_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVC797_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVC797_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVC797_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVC797_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVC797_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVC797_SET_BACK_END_COPY_A 0x1264 +#define NVC797_SET_BACK_END_COPY_A_DWORDS 7:0 +#define NVC797_SET_BACK_END_COPY_A_SATURATE32_ENABLE 8:8 +#define NVC797_SET_BACK_END_COPY_A_SATURATE32_ENABLE_FALSE 0x00000000 +#define NVC797_SET_BACK_END_COPY_A_SATURATE32_ENABLE_TRUE 0x00000001 +#define NVC797_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE 12:12 +#define NVC797_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_FALSE 0x00000000 +#define NVC797_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_BACK_END_COPY_B 0x1268 +#define NVC797_SET_BACK_END_COPY_B_SRC_ADDRESS_UPPER 7:0 + +#define NVC797_SET_BACK_END_COPY_C 0x126c +#define NVC797_SET_BACK_END_COPY_C_SRC_ADDRESS_LOWER 31:0 + +#define NVC797_SET_BACK_END_COPY_D 0x1270 +#define NVC797_SET_BACK_END_COPY_D_DEST_ADDRESS_UPPER 7:0 + +#define NVC797_SET_BACK_END_COPY_E 0x1274 +#define NVC797_SET_BACK_END_COPY_E_DEST_ADDRESS_LOWER 31:0 + +#define NVC797_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVC797_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 19:0 + +#define NVC797_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVC797_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVC797_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC797_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVC797_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVC797_CLEAR_ZCULL_REGION 0x12c8 +#define NVC797_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVC797_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVC797_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVC797_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVC797_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC797_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC797_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVC797_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC797_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC797_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVC797_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVC797_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVC797_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVC797_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVC797_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVC797_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVC797_SET_DEPTH_TEST 0x12cc +#define NVC797_SET_DEPTH_TEST_ENABLE 0:0 +#define NVC797_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVC797_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_FILL_MODE 0x12d0 +#define NVC797_SET_FILL_MODE_V 31:0 +#define NVC797_SET_FILL_MODE_V_POINT 0x00000001 +#define NVC797_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVC797_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVC797_SET_SHADE_MODE 0x12d4 +#define NVC797_SET_SHADE_MODE_V 31:0 +#define NVC797_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVC797_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVC797_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVC797_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC797_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC797_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVC797_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVC797_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVC797_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVC797_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVC797_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVC797_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVC797_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVC797_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_DEPTH_WRITE 0x12e8 +#define NVC797_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVC797_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_ALPHA_TEST 0x12ec +#define NVC797_SET_ALPHA_TEST_ENABLE 0:0 +#define NVC797_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVC797_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVC797_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVC797_DRAW_INLINE_INDEX4X8 0x1304 +#define NVC797_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVC797_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVC797_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVC797_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVC797_D3D_SET_CULL_MODE 0x1308 +#define NVC797_D3D_SET_CULL_MODE_V 31:0 +#define NVC797_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVC797_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVC797_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVC797_SET_DEPTH_FUNC 0x130c +#define NVC797_SET_DEPTH_FUNC_V 31:0 +#define NVC797_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVC797_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVC797_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC797_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC797_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVC797_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC797_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC797_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC797_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVC797_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVC797_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC797_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC797_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVC797_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC797_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC797_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC797_SET_ALPHA_REF 0x1310 +#define NVC797_SET_ALPHA_REF_V 31:0 + +#define NVC797_SET_ALPHA_FUNC 0x1314 +#define NVC797_SET_ALPHA_FUNC_V 31:0 +#define NVC797_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVC797_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVC797_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC797_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC797_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVC797_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC797_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC797_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC797_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVC797_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVC797_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC797_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC797_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVC797_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC797_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC797_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC797_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVC797_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVC797_SET_BLEND_CONST_RED 0x131c +#define NVC797_SET_BLEND_CONST_RED_V 31:0 + +#define NVC797_SET_BLEND_CONST_GREEN 0x1320 +#define NVC797_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVC797_SET_BLEND_CONST_BLUE 0x1324 +#define NVC797_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVC797_SET_BLEND_CONST_ALPHA 0x1328 +#define NVC797_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVC797_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC797_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC797_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC797_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC797_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC797_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC797_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVC797_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC797_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC797_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_BLEND_COLOR_OP 0x1340 +#define NVC797_SET_BLEND_COLOR_OP_V 31:0 +#define NVC797_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC797_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC797_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC797_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC797_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC797_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC797_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC797_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC797_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC797_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC797_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC797_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC797_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC797_SET_BLEND_ALPHA_OP 0x134c +#define NVC797_SET_BLEND_ALPHA_OP_V 31:0 +#define NVC797_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC797_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC797_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC797_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC797_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC797_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC797_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC797_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC797_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC797_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC797_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC797_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVC797_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVC797_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVC797_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC797_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC797_SET_SINGLE_ROP_CONTROL 0x135c +#define NVC797_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVC797_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_BLEND(i) (0x1360+(i)*4) +#define NVC797_SET_BLEND_ENABLE 0:0 +#define NVC797_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVC797_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_STENCIL_TEST 0x1380 +#define NVC797_SET_STENCIL_TEST_ENABLE 0:0 +#define NVC797_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC797_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_STENCIL_OP_FAIL 0x1384 +#define NVC797_SET_STENCIL_OP_FAIL_V 31:0 +#define NVC797_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC797_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC797_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC797_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC797_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC797_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC797_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC797_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC797_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC797_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC797_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC797_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC797_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC797_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC797_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC797_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC797_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVC797_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC797_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC797_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC797_SET_STENCIL_OP_ZPASS 0x138c +#define NVC797_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVC797_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC797_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC797_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC797_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC797_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC797_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC797_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC797_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC797_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC797_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC797_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC797_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC797_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC797_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC797_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC797_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC797_SET_STENCIL_FUNC 0x1390 +#define NVC797_SET_STENCIL_FUNC_V 31:0 +#define NVC797_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC797_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC797_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC797_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC797_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC797_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC797_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC797_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC797_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC797_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC797_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC797_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC797_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC797_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC797_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC797_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC797_SET_STENCIL_FUNC_REF 0x1394 +#define NVC797_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVC797_SET_STENCIL_FUNC_MASK 0x1398 +#define NVC797_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVC797_SET_STENCIL_MASK 0x139c +#define NVC797_SET_STENCIL_MASK_V 7:0 + +#define NVC797_SET_DRAW_AUTO_START 0x13a4 +#define NVC797_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVC797_SET_PS_SATURATE 0x13a8 +#define NVC797_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVC797_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVC797_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC797_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVC797_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVC797_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC797_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVC797_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVC797_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC797_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVC797_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVC797_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC797_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVC797_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVC797_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC797_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVC797_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVC797_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC797_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVC797_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVC797_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC797_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVC797_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVC797_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC797_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVC797_SET_WINDOW_ORIGIN 0x13ac +#define NVC797_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVC797_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVC797_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVC797_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVC797_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVC797_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVC797_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVC797_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC797_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVC797_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC797_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVC797_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVC797_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVC797_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC797_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC797_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC797_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC797_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC797_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC797_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVC797_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVC797_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVC797_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVC797_SET_PS_WARP_WATERMARKS 0x1450 +#define NVC797_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVC797_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVC797_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVC797_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVC797_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC797_STORE_ZCULL 0x1464 +#define NVC797_STORE_ZCULL_V 0:0 + +#define NVC797_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVC797_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVC797_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVC797_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVC797_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVC797_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVC797_LOAD_ZCULL 0x1500 +#define NVC797_LOAD_ZCULL_V 0:0 + +#define NVC797_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVC797_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVC797_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVC797_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC797_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC797_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVC797_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC797_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC797_SET_USER_CLIP_ENABLE 0x1510 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVC797_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVC797_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVC797_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVC797_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_POINT_SIZE 0x1518 +#define NVC797_SET_POINT_SIZE_V 31:0 + +#define NVC797_SET_ZCULL_STATS 0x151c +#define NVC797_SET_ZCULL_STATS_ENABLE 0:0 +#define NVC797_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_POINT_SPRITE 0x1520 +#define NVC797_SET_POINT_SPRITE_ENABLE 0:0 +#define NVC797_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC797_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC797_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC797_CLEAR_REPORT_VALUE 0x1530 +#define NVC797_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVC797_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVC797_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVC797_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVC797_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVC797_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVC797_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC797_CLEAR_REPORT_VALUE_TYPE_SCG_CLOCKS 0x00000009 + +#define NVC797_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVC797_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVC797_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVC797_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVC797_SET_ZT_SELECT 0x1538 +#define NVC797_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVC797_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVC797_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVC797_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVC797_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVC797_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVC797_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVC797_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVC797_SET_RENDER_ENABLE_A 0x1550 +#define NVC797_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_RENDER_ENABLE_B 0x1554 +#define NVC797_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_RENDER_ENABLE_C 0x1558 +#define NVC797_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC797_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC797_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC797_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC797_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC797_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC797_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC797_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC797_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC797_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC797_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVC797_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVC797_SET_ANTI_ALIASED_LINE 0x1570 +#define NVC797_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVC797_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC797_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC797_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_TEX_HEADER_POOL_C 0x157c +#define NVC797_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC797_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVC797_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVC797_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVC797_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVC797_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC797_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC797_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC797_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC797_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC797_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC797_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVC797_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVC797_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC797_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC797_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC797_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC797_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC797_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC797_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC797_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC797_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC797_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC797_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC797_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC797_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC797_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC797_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC797_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC797_SET_SRGB_WRITE 0x15b8 +#define NVC797_SET_SRGB_WRITE_ENABLE 0:0 +#define NVC797_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_DEPTH_BIAS 0x15bc +#define NVC797_SET_DEPTH_BIAS_V 31:0 + +#define NVC797_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVC797_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVC797_SET_RT_LAYER 0x15cc +#define NVC797_SET_RT_LAYER_V 15:0 +#define NVC797_SET_RT_LAYER_CONTROL 16:16 +#define NVC797_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVC797_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVC797_SET_ANTI_ALIAS 0x15d0 +#define NVC797_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVC797_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVC797_SET_EDGE_FLAG 0x15e4 +#define NVC797_SET_EDGE_FLAG_V 0:0 +#define NVC797_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVC797_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVC797_DRAW_INLINE_INDEX 0x15e8 +#define NVC797_DRAW_INLINE_INDEX_V 31:0 + +#define NVC797_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVC797_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVC797_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVC797_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVC797_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVC797_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVC797_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVC797_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVC797_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVC797_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVC797_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVC797_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVC797_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVC797_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVC797_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVC797_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVC797_SET_POINT_SPRITE_SELECT 0x1604 +#define NVC797_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVC797_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVC797_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVC797_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVC797_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVC797_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVC797_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVC797_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVC797_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVC797_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVC797_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVC797_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVC797_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVC797_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVC797_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVC797_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVC797_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVC797_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVC797_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVC797_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVC797_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVC797_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVC797_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVC797_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVC797_END 0x1614 +#define NVC797_END_V 0:0 + +#define NVC797_BEGIN 0x1618 +#define NVC797_BEGIN_OP 15:0 +#define NVC797_BEGIN_OP_POINTS 0x00000000 +#define NVC797_BEGIN_OP_LINES 0x00000001 +#define NVC797_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVC797_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVC797_BEGIN_OP_TRIANGLES 0x00000004 +#define NVC797_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVC797_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVC797_BEGIN_OP_QUADS 0x00000007 +#define NVC797_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVC797_BEGIN_OP_POLYGON 0x00000009 +#define NVC797_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVC797_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVC797_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_BEGIN_OP_PATCH 0x0000000E +#define NVC797_BEGIN_PRIMITIVE_ID 24:24 +#define NVC797_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC797_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC797_BEGIN_INSTANCE_ID 27:26 +#define NVC797_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVC797_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC797_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC797_BEGIN_SPLIT_MODE 30:29 +#define NVC797_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC797_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC797_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC797_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC797_BEGIN_INSTANCE_ITERATE_ENABLE 31:31 +#define NVC797_BEGIN_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC797_BEGIN_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_VERTEX_ID_COPY 0x161c +#define NVC797_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVC797_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVC797_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVC797_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVC797_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVC797_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVC797_LOAD_PRIMITIVE_ID 0x1624 +#define NVC797_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVC797_SET_SHADER_BASED_CULL 0x162c +#define NVC797_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVC797_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVC797_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVC797_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVC797_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_CLASS_VERSION 0x1638 +#define NVC797_SET_CLASS_VERSION_CURRENT 15:0 +#define NVC797_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC797_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVC797_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVC797_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVC797_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVC797_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVC797_SET_DA_OUTPUT 0x164c +#define NVC797_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVC797_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVC797_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVC797_SET_ANTI_ALIASED_POINT 0x1658 +#define NVC797_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVC797_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_POINT_CENTER_MODE 0x165c +#define NVC797_SET_POINT_CENTER_MODE_V 31:0 +#define NVC797_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVC797_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVC797_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVC797_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVC797_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVC797_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVC797_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVC797_SET_LINE_STIPPLE 0x166c +#define NVC797_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVC797_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVC797_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVC797_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVC797_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVC797_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVC797_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVC797_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVC797_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVC797_SET_PROVOKING_VERTEX 0x1684 +#define NVC797_SET_PROVOKING_VERTEX_V 0:0 +#define NVC797_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVC797_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVC797_SET_TWO_SIDED_LIGHT 0x1688 +#define NVC797_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVC797_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_POLYGON_STIPPLE 0x168c +#define NVC797_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVC797_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_SHADER_CONTROL 0x1690 +#define NVC797_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVC797_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVC797_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVC797_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVC797_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC797_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC797_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVC797_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC797_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVC797_CHECK_CLASS_VERSION 0x16a0 +#define NVC797_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVC797_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC797_SET_SPH_VERSION 0x16a4 +#define NVC797_SET_SPH_VERSION_CURRENT 15:0 +#define NVC797_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC797_CHECK_SPH_VERSION 0x16a8 +#define NVC797_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVC797_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC797_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVC797_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVC797_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC797_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVC797_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVC797_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVC797_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVC797_SET_SCG_GRAPHICS_PRIORITY 0x16bc +#define NVC797_SET_SCG_GRAPHICS_PRIORITY_PRIORITY 5:0 + +#define NVC797_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS(i) (0x16c0+(i)*4) +#define NVC797_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS_V 31:0 + +#define NVC797_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVC797_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVC797_SET_AAM_VERSION 0x1790 +#define NVC797_SET_AAM_VERSION_CURRENT 15:0 +#define NVC797_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC797_CHECK_AAM_VERSION 0x1794 +#define NVC797_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVC797_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC797_SET_ZT_LAYER 0x179c +#define NVC797_SET_ZT_LAYER_OFFSET 15:0 + +#define NVC797_SET_INDEX_BUFFER_A 0x17c8 +#define NVC797_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVC797_SET_INDEX_BUFFER_B 0x17cc +#define NVC797_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVC797_SET_INDEX_BUFFER_E 0x17d8 +#define NVC797_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVC797_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVC797_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVC797_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVC797_SET_INDEX_BUFFER_F 0x17dc +#define NVC797_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVC797_DRAW_INDEX_BUFFER 0x17e0 +#define NVC797_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC797_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVC797_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVC797_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVC797_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVC797_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVC797_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVC797_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVC797_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVC797_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVC797_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVC797_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVC797_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVC797_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVC797_OGL_SET_CULL 0x1918 +#define NVC797_OGL_SET_CULL_ENABLE 0:0 +#define NVC797_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVC797_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVC797_OGL_SET_FRONT_FACE 0x191c +#define NVC797_OGL_SET_FRONT_FACE_V 31:0 +#define NVC797_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVC797_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVC797_OGL_SET_CULL_FACE 0x1920 +#define NVC797_OGL_SET_CULL_FACE_V 31:0 +#define NVC797_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVC797_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVC797_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVC797_SET_VIEWPORT_PIXEL 0x1924 +#define NVC797_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVC797_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVC797_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVC797_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVC797_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVC797_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVC797_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE 17:16 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_USE_FIELD_MIN_Z_ZERO_MAX_Z_ONE 0x00000000 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MIN_Z_MAX_Z 0x00000001 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_ZERO_ONE 0x00000002 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MINUS_INF_PLUS_INF 0x00000003 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVC797_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVC797_SET_USER_CLIP_OP 0x1940 +#define NVC797_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVC797_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVC797_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVC797_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVC797_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVC797_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVC797_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVC797_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVC797_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVC797_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVC797_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVC797_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVC797_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVC797_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVC797_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVC797_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVC797_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVC797_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVC797_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVC797_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVC797_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVC797_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVC797_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVC797_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVC797_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC797_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC797_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC797_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC797_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC797_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVC797_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVC797_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVC797_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVC797_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVC797_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVC797_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVC797_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVC797_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVC797_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVC797_INVALIDATE_ZCULL 0x1958 +#define NVC797_INVALIDATE_ZCULL_V 31:0 +#define NVC797_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVC797_SET_ZCULL 0x1968 +#define NVC797_SET_ZCULL_Z_ENABLE 0:0 +#define NVC797_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVC797_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_ZCULL_BOUNDS 0x196c +#define NVC797_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVC797_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVC797_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVC797_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC797_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVC797_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVC797_ZCULL_SYNC 0x1978 +#define NVC797_ZCULL_SYNC_V 31:0 + +#define NVC797_SET_CLIP_ID_TEST 0x197c +#define NVC797_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVC797_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVC797_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVC797_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVC797_SET_CLIP_ID 0x1984 +#define NVC797_SET_CLIP_ID_V 31:0 + +#define NVC797_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVC797_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVC797_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVC797_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVC797_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVC797_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVC797_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVC797_SET_LOGIC_OP 0x19c4 +#define NVC797_SET_LOGIC_OP_ENABLE 0:0 +#define NVC797_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVC797_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_LOGIC_OP_FUNC 0x19c8 +#define NVC797_SET_LOGIC_OP_FUNC_V 31:0 +#define NVC797_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVC797_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVC797_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVC797_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVC797_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVC797_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVC797_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVC797_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVC797_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVC797_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVC797_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVC797_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVC797_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVC797_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVC797_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVC797_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVC797_SET_Z_COMPRESSION 0x19cc +#define NVC797_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVC797_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC797_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC797_CLEAR_SURFACE 0x19d0 +#define NVC797_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVC797_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC797_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC797_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVC797_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC797_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC797_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVC797_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVC797_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVC797_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVC797_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVC797_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVC797_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVC797_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVC797_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVC797_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVC797_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVC797_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVC797_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVC797_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVC797_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVC797_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVC797_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVC797_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVC797_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC797_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVC797_SET_CT_WRITE_R_ENABLE 0:0 +#define NVC797_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVC797_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVC797_SET_CT_WRITE_G_ENABLE 4:4 +#define NVC797_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVC797_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVC797_SET_CT_WRITE_B_ENABLE 8:8 +#define NVC797_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVC797_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVC797_SET_CT_WRITE_A_ENABLE 12:12 +#define NVC797_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVC797_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVC797_PIPE_NOP 0x1a2c +#define NVC797_PIPE_NOP_V 31:0 + +#define NVC797_SET_SPARE00 0x1a30 +#define NVC797_SET_SPARE00_V 31:0 + +#define NVC797_SET_SPARE01 0x1a34 +#define NVC797_SET_SPARE01_V 31:0 + +#define NVC797_SET_SPARE02 0x1a38 +#define NVC797_SET_SPARE02_V 31:0 + +#define NVC797_SET_SPARE03 0x1a3c +#define NVC797_SET_SPARE03_V 31:0 + +#define NVC797_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC797_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC797_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC797_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC797_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC797_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC797_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVC797_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC797_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVC797_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVC797_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC797_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC797_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVC797_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC797_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_SCG_CLOCKS 0x00000008 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_TIMESTAMP 0x00000014 +#define NVC797_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC797_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVC797_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVC797_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC797_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC797_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVC797_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVC797_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVC797_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVC797_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVC797_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVC797_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVC797_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVC797_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVC797_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVC797_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVC797_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVC797_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVC797_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC797_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVC797_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC797_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVC797_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC797_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVC797_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVC797_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVC797_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC797_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC797_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC797_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC797_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC797_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVC797_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVC797_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVC797_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVC797_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVC797_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVC797_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVC797_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVC797_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVC797_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVC797_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVC797_SET_PIPELINE_RESERVED_B(j) (0x2004+(j)*64) +#define NVC797_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVC797_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVC797_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVC797_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVC797_SET_PIPELINE_REGISTER_COUNT_V 8:0 + +#define NVC797_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVC797_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVC797_SET_PIPELINE_PROGRAM_ADDRESS_A(j) (0x2014+(j)*64) +#define NVC797_SET_PIPELINE_PROGRAM_ADDRESS_A_UPPER 7:0 + +#define NVC797_SET_PIPELINE_PROGRAM_ADDRESS_B(j) (0x2018+(j)*64) +#define NVC797_SET_PIPELINE_PROGRAM_ADDRESS_B_LOWER 31:0 + +#define NVC797_SET_PIPELINE_PROGRAM_PREFETCH(j) (0x201c+(j)*64) +#define NVC797_SET_PIPELINE_PROGRAM_PREFETCH_SIZE_IN_BLOCKS 6:0 + +#define NVC797_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVC797_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVC797_SET_FALCON00 0x2300 +#define NVC797_SET_FALCON00_V 31:0 + +#define NVC797_SET_FALCON01 0x2304 +#define NVC797_SET_FALCON01_V 31:0 + +#define NVC797_SET_FALCON02 0x2308 +#define NVC797_SET_FALCON02_V 31:0 + +#define NVC797_SET_FALCON03 0x230c +#define NVC797_SET_FALCON03_V 31:0 + +#define NVC797_SET_FALCON04 0x2310 +#define NVC797_SET_FALCON04_V 31:0 + +#define NVC797_SET_FALCON05 0x2314 +#define NVC797_SET_FALCON05_V 31:0 + +#define NVC797_SET_FALCON06 0x2318 +#define NVC797_SET_FALCON06_V 31:0 + +#define NVC797_SET_FALCON07 0x231c +#define NVC797_SET_FALCON07_V 31:0 + +#define NVC797_SET_FALCON08 0x2320 +#define NVC797_SET_FALCON08_V 31:0 + +#define NVC797_SET_FALCON09 0x2324 +#define NVC797_SET_FALCON09_V 31:0 + +#define NVC797_SET_FALCON10 0x2328 +#define NVC797_SET_FALCON10_V 31:0 + +#define NVC797_SET_FALCON11 0x232c +#define NVC797_SET_FALCON11_V 31:0 + +#define NVC797_SET_FALCON12 0x2330 +#define NVC797_SET_FALCON12_V 31:0 + +#define NVC797_SET_FALCON13 0x2334 +#define NVC797_SET_FALCON13_V 31:0 + +#define NVC797_SET_FALCON14 0x2338 +#define NVC797_SET_FALCON14_V 31:0 + +#define NVC797_SET_FALCON15 0x233c +#define NVC797_SET_FALCON15_V 31:0 + +#define NVC797_SET_FALCON16 0x2340 +#define NVC797_SET_FALCON16_V 31:0 + +#define NVC797_SET_FALCON17 0x2344 +#define NVC797_SET_FALCON17_V 31:0 + +#define NVC797_SET_FALCON18 0x2348 +#define NVC797_SET_FALCON18_V 31:0 + +#define NVC797_SET_FALCON19 0x234c +#define NVC797_SET_FALCON19_V 31:0 + +#define NVC797_SET_FALCON20 0x2350 +#define NVC797_SET_FALCON20_V 31:0 + +#define NVC797_SET_FALCON21 0x2354 +#define NVC797_SET_FALCON21_V 31:0 + +#define NVC797_SET_FALCON22 0x2358 +#define NVC797_SET_FALCON22_V 31:0 + +#define NVC797_SET_FALCON23 0x235c +#define NVC797_SET_FALCON23_V 31:0 + +#define NVC797_SET_FALCON24 0x2360 +#define NVC797_SET_FALCON24_V 31:0 + +#define NVC797_SET_FALCON25 0x2364 +#define NVC797_SET_FALCON25_V 31:0 + +#define NVC797_SET_FALCON26 0x2368 +#define NVC797_SET_FALCON26_V 31:0 + +#define NVC797_SET_FALCON27 0x236c +#define NVC797_SET_FALCON27_V 31:0 + +#define NVC797_SET_FALCON28 0x2370 +#define NVC797_SET_FALCON28_V 31:0 + +#define NVC797_SET_FALCON29 0x2374 +#define NVC797_SET_FALCON29_V 31:0 + +#define NVC797_SET_FALCON30 0x2378 +#define NVC797_SET_FALCON30_V 31:0 + +#define NVC797_SET_FALCON31 0x237c +#define NVC797_SET_FALCON31_V 31:0 + +#define NVC797_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVC797_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVC797_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVC797_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVC797_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVC797_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVC797_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVC797_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVC797_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVC797_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVC797_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVC797_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVC797_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVC797_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVC797_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVC797_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVC797_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVC797_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVC797_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVC797_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVC797_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC797_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC797_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVC797_SET_TRAP_HANDLER_A 0x25f8 +#define NVC797_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC797_SET_TRAP_HANDLER_B 0x25fc +#define NVC797_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC797_SET_COLOR_CLAMP 0x2600 +#define NVC797_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVC797_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVC797_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVC797_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVC797_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVC797_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVC797_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVC797_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVC797_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC797_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC797_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC797_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC797_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC797_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC797_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC797_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC797_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC797_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC797_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC797_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC797_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC797_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC797_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVC797_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVC797_CALL_MME_MACRO_V 31:0 + +#define NVC797_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVC797_CALL_MME_DATA_V 31:0 + +#endif /* _cl_ampere_b_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/clc86f.h b/src/common/sdk/nvidia/inc/class/clc86f.h index 712466c2b..48154a3d0 100644 --- a/src/common/sdk/nvidia/inc/class/clc86f.h +++ b/src/common/sdk/nvidia/inc/class/clc86f.h @@ -57,4 +57,28 @@ typedef volatile struct Nvc86fControl_struct { #define NVC86F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000 #define NVC86F_SEM_EXECUTE_PAYLOAD_SIZE 24:24 #define NVC86F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000 + +/* GPFIFO entry format */ +#define NVC86F_GP_ENTRY__SIZE 8 +#define NVC86F_GP_ENTRY0_FETCH 0:0 +#define NVC86F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 +#define NVC86F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 +#define NVC86F_GP_ENTRY0_GET 31:2 +#define NVC86F_GP_ENTRY0_OPERAND 31:0 +#define NVC86F_GP_ENTRY0_PB_EXTENDED_BASE_OPERAND 24:8 +#define NVC86F_GP_ENTRY1_GET_HI 7:0 +#define NVC86F_GP_ENTRY1_LEVEL 9:9 +#define NVC86F_GP_ENTRY1_LEVEL_MAIN 0x00000000 +#define NVC86F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 +#define NVC86F_GP_ENTRY1_LENGTH 30:10 +#define NVC86F_GP_ENTRY1_SYNC 31:31 +#define NVC86F_GP_ENTRY1_SYNC_PROCEED 0x00000000 +#define NVC86F_GP_ENTRY1_SYNC_WAIT 0x00000001 +#define NVC86F_GP_ENTRY1_OPCODE 7:0 +#define NVC86F_GP_ENTRY1_OPCODE_NOP 0x00000000 +#define NVC86F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 +#define NVC86F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 +#define NVC86F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 +#define NVC86F_GP_ENTRY1_OPCODE_SET_PB_SEGMENT_EXTENDED_BASE 0x00000004 + #endif // __gh100_clc86f_h__ diff --git a/src/common/sdk/nvidia/inc/class/clc997.h b/src/common/sdk/nvidia/inc/class/clc997.h index 8aa2487a4..81607be8d 100644 --- a/src/common/sdk/nvidia/inc/class/clc997.h +++ b/src/common/sdk/nvidia/inc/class/clc997.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,9 +21,4461 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _clc997_h_ -#define _clc997_h_ +#ifndef _cl_ada_a_h_ +#define _cl_ada_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl ada_a */ + +#include "nvtypes.h" #define ADA_A 0xC997 -#endif +#define NVC997_SET_OBJECT 0x0000 +#define NVC997_SET_OBJECT_CLASS_ID 15:0 +#define NVC997_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC997_NO_OPERATION 0x0100 +#define NVC997_NO_OPERATION_V 31:0 + +#define NVC997_SET_NOTIFY_A 0x0104 +#define NVC997_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC997_SET_NOTIFY_B 0x0108 +#define NVC997_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC997_NOTIFY 0x010c +#define NVC997_NOTIFY_TYPE 31:0 +#define NVC997_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC997_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC997_WAIT_FOR_IDLE 0x0110 +#define NVC997_WAIT_FOR_IDLE_V 31:0 + +#define NVC997_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVC997_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVC997_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVC997_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVC997_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVC997_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVC997_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVC997_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVC997_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVC997_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVC997_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVC997_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVC997_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVC997_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVC997_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVC997_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVC997_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVC997_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVC997_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC997_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC997_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC997_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC997_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC997_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC997_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC997_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC997_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC997_SEND_GO_IDLE 0x013c +#define NVC997_SEND_GO_IDLE_V 31:0 + +#define NVC997_PM_TRIGGER 0x0140 +#define NVC997_PM_TRIGGER_V 31:0 + +#define NVC997_PM_TRIGGER_WFI 0x0144 +#define NVC997_PM_TRIGGER_WFI_V 31:0 + +#define NVC997_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC997_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC997_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC997_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC997_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC997_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC997_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC997_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC997_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER 0x0158 +#define NVC997_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER_PAYLOAD_LOWER 31:0 + +#define NVC997_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER 0x015c +#define NVC997_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD_UPPER 31:0 + +#define NVC997_SET_REPORT_SEMAPHORE_ADDRESS_LOWER 0x0160 +#define NVC997_SET_REPORT_SEMAPHORE_ADDRESS_LOWER_LOWER 31:0 + +#define NVC997_SET_REPORT_SEMAPHORE_ADDRESS_UPPER 0x0164 +#define NVC997_SET_REPORT_SEMAPHORE_ADDRESS_UPPER_UPPER 7:0 + +#define NVC997_REPORT_SEMAPHORE_EXECUTE 0x0168 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_OPERATION 1:0 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_OPERATION_RELEASE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_OPERATION_ACQUIRE 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_OPERATION_REPORT_ONLY 0x00000002 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_OPERATION_TRAP 0x00000003 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION 5:2 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC997_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE 6:6 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT 11:7 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_NONE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_SCG_CLOCKS 0x00000008 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS0 0x0000000A +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS1 0x0000000C +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS2 0x0000000E +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS3 0x00000010 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REPORT_TIMESTAMP 0x00000014 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE 14:13 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_SUB_REPORT 17:15 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE 19:19 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE 18:18 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE 20:20 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP 23:21 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_INC 0x00000003 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_AND 0x00000005 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_OR 0x00000006 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT 25:24 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64 27:27 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_FALSE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_TRUE 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE 29:28 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_NONE 0x00000000 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_UNCONDITIONAL 0x00000001 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL 0x00000002 +#define NVC997_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x00000003 + +#define NVC997_LINE_LENGTH_IN 0x0180 +#define NVC997_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC997_LINE_COUNT 0x0184 +#define NVC997_LINE_COUNT_VALUE 31:0 + +#define NVC997_OFFSET_OUT_UPPER 0x0188 +#define NVC997_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVC997_OFFSET_OUT 0x018c +#define NVC997_OFFSET_OUT_VALUE 31:0 + +#define NVC997_PITCH_OUT 0x0190 +#define NVC997_PITCH_OUT_VALUE 31:0 + +#define NVC997_SET_DST_BLOCK_SIZE 0x0194 +#define NVC997_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC997_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC997_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC997_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC997_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC997_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC997_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC997_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC997_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC997_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC997_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC997_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC997_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC997_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC997_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC997_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC997_SET_DST_WIDTH 0x0198 +#define NVC997_SET_DST_WIDTH_V 31:0 + +#define NVC997_SET_DST_HEIGHT 0x019c +#define NVC997_SET_DST_HEIGHT_V 31:0 + +#define NVC997_SET_DST_DEPTH 0x01a0 +#define NVC997_SET_DST_DEPTH_V 31:0 + +#define NVC997_SET_DST_LAYER 0x01a4 +#define NVC997_SET_DST_LAYER_V 31:0 + +#define NVC997_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC997_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC997_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC997_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC997_LAUNCH_DMA 0x01b0 +#define NVC997_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC997_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC997_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC997_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC997_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC997_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC997_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC997_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC997_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC997_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC997_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC997_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC997_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC997_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC997_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC997_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC997_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC997_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC997_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC997_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC997_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC997_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC997_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC997_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC997_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC997_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC997_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC997_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC997_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC997_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC997_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC997_LOAD_INLINE_DATA 0x01b4 +#define NVC997_LOAD_INLINE_DATA_V 31:0 + +#define NVC997_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC997_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC997_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC997_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC997_SET_MME_SWITCH_STATE 0x01ec +#define NVC997_SET_MME_SWITCH_STATE_VALID 0:0 +#define NVC997_SET_MME_SWITCH_STATE_VALID_FALSE 0x00000000 +#define NVC997_SET_MME_SWITCH_STATE_VALID_TRUE 0x00000001 +#define NVC997_SET_MME_SWITCH_STATE_SAVE_MACRO 11:4 +#define NVC997_SET_MME_SWITCH_STATE_RESTORE_MACRO 19:12 + +#define NVC997_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC997_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC997_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC997_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC997_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC997_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC997_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC997_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC997_RUN_DS_NOW 0x0200 +#define NVC997_RUN_DS_NOW_V 31:0 + +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVC997_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVC997_SET_GS_MODE 0x0208 +#define NVC997_SET_GS_MODE_TYPE 0:0 +#define NVC997_SET_GS_MODE_TYPE_ANY 0x00000000 +#define NVC997_SET_GS_MODE_TYPE_FAST_GS 0x00000001 + +#define NVC997_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVC997_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVC997_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVC997_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVC997_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVC997_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVC997_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVC997_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_GS_DM_FIFO 0x0214 +#define NVC997_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVC997_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVC997_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVC997_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVC997_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC997_INVALIDATE_SHADER_CACHES 0x021c +#define NVC997_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC997_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC997_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC997_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC997_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC997_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC997_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC997_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC997_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC997_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC997_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC997_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC997_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC997_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC997_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC997_SET_INSTANCE_COUNT 0x0220 +#define NVC997_SET_INSTANCE_COUNT_V 31:0 + +#define NVC997_SET_POSITION_W_SCALED_OFFSET_ENABLE 0x0224 +#define NVC997_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE 0:0 +#define NVC997_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_GO_IDLE_TIMEOUT 0x022c +#define NVC997_SET_GO_IDLE_TIMEOUT_V 31:0 + +#define NVC997_SET_MME_VERSION 0x0234 +#define NVC997_SET_MME_VERSION_MAJOR 7:0 + +#define NVC997_SET_INDEX_BUFFER_SIZE_A 0x0238 +#define NVC997_SET_INDEX_BUFFER_SIZE_A_UPPER 7:0 + +#define NVC997_SET_INDEX_BUFFER_SIZE_B 0x023c +#define NVC997_SET_INDEX_BUFFER_SIZE_B_LOWER 31:0 + +#define NVC997_SET_ROOT_TABLE_VISIBILITY(i) (0x0240+(i)*4) +#define NVC997_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP0_ENABLE 1:0 +#define NVC997_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP1_ENABLE 5:4 +#define NVC997_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP2_ENABLE 9:8 +#define NVC997_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP3_ENABLE 13:12 +#define NVC997_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP4_ENABLE 17:16 + +#define NVC997_SET_DRAW_CONTROL_A 0x0260 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY 3:0 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_POINTS 0x00000000 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_LINES 0x00000001 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_QUADS 0x00000007 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_SET_DRAW_CONTROL_A_TOPOLOGY_PATCH 0x0000000E +#define NVC997_SET_DRAW_CONTROL_A_PRIMITIVE_ID 4:4 +#define NVC997_SET_DRAW_CONTROL_A_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC997_SET_DRAW_CONTROL_A_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC997_SET_DRAW_CONTROL_A_INSTANCE_ID 6:5 +#define NVC997_SET_DRAW_CONTROL_A_INSTANCE_ID_FIRST 0x00000000 +#define NVC997_SET_DRAW_CONTROL_A_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC997_SET_DRAW_CONTROL_A_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC997_SET_DRAW_CONTROL_A_SPLIT_MODE 8:7 +#define NVC997_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC997_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC997_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC997_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC997_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE 9:9 +#define NVC997_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 +#define NVC997_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX 10:10 +#define NVC997_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_FALSE 0x00000000 +#define NVC997_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_TRUE 0x00000001 +#define NVC997_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX 11:11 +#define NVC997_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_FALSE 0x00000000 +#define NVC997_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_TRUE 0x00000001 + +#define NVC997_SET_DRAW_CONTROL_B 0x0264 +#define NVC997_SET_DRAW_CONTROL_B_INSTANCE_COUNT 31:0 + +#define NVC997_DRAW_INDEX_BUFFER_BEGIN_END_A 0x0268 +#define NVC997_DRAW_INDEX_BUFFER_BEGIN_END_A_FIRST 31:0 + +#define NVC997_DRAW_INDEX_BUFFER_BEGIN_END_B 0x026c +#define NVC997_DRAW_INDEX_BUFFER_BEGIN_END_B_COUNT 31:0 + +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_A 0x0270 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_A_START 31:0 + +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_B 0x0274 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_B_COUNT 31:0 + +#define NVC997_INVALIDATE_RASTER_CACHE_NO_WFI 0x027c +#define NVC997_INVALIDATE_RASTER_CACHE_NO_WFI_V 0:0 + +#define NVC997_SET_COLOR_RENDER_TO_ZETA_SURFACE 0x02b8 +#define NVC997_SET_COLOR_RENDER_TO_ZETA_SURFACE_V 0:0 +#define NVC997_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_FALSE 0x00000000 +#define NVC997_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_TRUE 0x00000001 + +#define NVC997_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION 0x02bc +#define NVC997_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V 0:0 +#define NVC997_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_FALSE 0x00000000 +#define NVC997_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_TRUE 0x00000001 + +#define NVC997_INCREMENT_SYNC_POINT 0x02c8 +#define NVC997_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVC997_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVC997_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVC997_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVC997_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVC997_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVC997_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVC997_SET_ROOT_TABLE_PREFETCH 0x02d0 +#define NVC997_SET_ROOT_TABLE_PREFETCH_STAGE_ENABLES 5:0 + +#define NVC997_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVC997_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVC997_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC997_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVC997_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVC997_DECOMPRESS_SURFACE 0x02e0 +#define NVC997_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVC997_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVC997_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVC997_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVC997_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVC997_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVC997_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVC997_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVC997_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVC997_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVC997_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVC997_SET_ZCULL_SUBREGION 0x02e8 +#define NVC997_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVC997_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVC997_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVC997_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVC997_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVC997_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVC997_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVC997_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVC997_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVC997_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVC997_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVC997_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVC997_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVC997_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVC997_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVC997_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVC997_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVC997_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVC997_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVC997_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVC997_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVC997_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVC997_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVC997_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVC997_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC997_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVC997_DRAW_ZERO_INDEX 0x0304 +#define NVC997_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVC997_SET_L1_CONFIGURATION 0x0308 +#define NVC997_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVC997_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC997_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVC997_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVC997_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVC997_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVC997_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVC997_SET_SPA_VERSION 0x0310 +#define NVC997_SET_SPA_VERSION_MINOR 7:0 +#define NVC997_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC997_SET_TIMESLICE_BATCH_LIMIT 0x0314 +#define NVC997_SET_TIMESLICE_BATCH_LIMIT_BATCH_LIMIT 15:0 + +#define NVC997_SET_SNAP_GRID_LINE 0x0318 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC997_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC997_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVC997_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC997_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC997_SET_SNAP_GRID_NON_LINE 0x031c +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVC997_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVC997_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVC997_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVC997_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVC997_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVC997_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVC997_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVC997_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVC997_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVC997_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVC997_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVC997_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVC997_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVC997_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVC997_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVC997_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVC997_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVC997_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVC997_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVC997_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVC997_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVC997_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVC997_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVC997_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVC997_SET_TESSELLATION_LOD_V1 0x0330 +#define NVC997_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVC997_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVC997_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVC997_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVC997_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVC997_RESERVED_TG07 0x033c +#define NVC997_RESERVED_TG07_V 0:0 + +#define NVC997_RESERVED_TG08 0x0340 +#define NVC997_RESERVED_TG08_V 0:0 + +#define NVC997_RESERVED_TG09 0x0344 +#define NVC997_RESERVED_TG09_V 0:0 + +#define NVC997_RESERVED_TG10 0x0348 +#define NVC997_RESERVED_TG10_V 0:0 + +#define NVC997_RESERVED_TG11 0x034c +#define NVC997_RESERVED_TG11_V 0:0 + +#define NVC997_RESERVED_TG12 0x0350 +#define NVC997_RESERVED_TG12_V 0:0 + +#define NVC997_RESERVED_TG13 0x0354 +#define NVC997_RESERVED_TG13_V 0:0 + +#define NVC997_RESERVED_TG14 0x0358 +#define NVC997_RESERVED_TG14_V 0:0 + +#define NVC997_RESERVED_TG15 0x035c +#define NVC997_RESERVED_TG15_V 0:0 + +#define NVC997_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVC997_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVC997_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVC997_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVC997_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVC997_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVC997_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVC997_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVC997_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVC997_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVC997_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVC997_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVC997_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE 8:8 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE 9:9 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVC997_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVC997_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVC997_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVC997_SET_RASTER_ENABLE 0x037c +#define NVC997_SET_RASTER_ENABLE_V 0:0 +#define NVC997_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVC997_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVC997_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVC997_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVC997_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVC997_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVC997_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVC997_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVC997_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVC997_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVC997_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVC997_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVC997_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVC997_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVC997_SET_POSITION_W_SCALED_OFFSET_SCALE_A(j) (0x0400+(j)*16) +#define NVC997_SET_POSITION_W_SCALED_OFFSET_SCALE_A_V 31:0 + +#define NVC997_SET_POSITION_W_SCALED_OFFSET_SCALE_B(j) (0x0404+(j)*16) +#define NVC997_SET_POSITION_W_SCALED_OFFSET_SCALE_B_V 31:0 + +#define NVC997_SET_POSITION_W_SCALED_OFFSET_RESERVED_A(j) (0x0408+(j)*16) +#define NVC997_SET_POSITION_W_SCALED_OFFSET_RESERVED_A_V 31:0 + +#define NVC997_SET_POSITION_W_SCALED_OFFSET_RESERVED_B(j) (0x040c+(j)*16) +#define NVC997_SET_POSITION_W_SCALED_OFFSET_RESERVED_B_V 31:0 + +#define NVC997_SET_Z_ROP_SLICE_MAP 0x0500 +#define NVC997_SET_Z_ROP_SLICE_MAP_VIRTUAL_ADDRESS_MASK 31:0 + +#define NVC997_SET_ROOT_TABLE_SELECTOR 0x0504 +#define NVC997_SET_ROOT_TABLE_SELECTOR_ROOT_TABLE 2:0 +#define NVC997_SET_ROOT_TABLE_SELECTOR_OFFSET 15:8 + +#define NVC997_LOAD_ROOT_TABLE 0x0508 +#define NVC997_LOAD_ROOT_TABLE_V 31:0 + +#define NVC997_SET_MME_MEM_ADDRESS_A 0x0550 +#define NVC997_SET_MME_MEM_ADDRESS_A_UPPER 16:0 + +#define NVC997_SET_MME_MEM_ADDRESS_B 0x0554 +#define NVC997_SET_MME_MEM_ADDRESS_B_LOWER 31:0 + +#define NVC997_SET_MME_DATA_RAM_ADDRESS 0x0558 +#define NVC997_SET_MME_DATA_RAM_ADDRESS_WORD 31:0 + +#define NVC997_MME_DMA_READ 0x055c +#define NVC997_MME_DMA_READ_LENGTH 31:0 + +#define NVC997_MME_DMA_READ_FIFOED 0x0560 +#define NVC997_MME_DMA_READ_FIFOED_LENGTH 31:0 + +#define NVC997_MME_DMA_WRITE 0x0564 +#define NVC997_MME_DMA_WRITE_LENGTH 31:0 + +#define NVC997_MME_DMA_REDUCTION 0x0568 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP 2:0 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP_RED_INC 0x00000003 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP_RED_AND 0x00000005 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP_RED_OR 0x00000006 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_FORMAT 5:4 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_SIZE 8:8 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_SIZE_FOUR_BYTES 0x00000000 +#define NVC997_MME_DMA_REDUCTION_REDUCTION_SIZE_EIGHT_BYTES 0x00000001 + +#define NVC997_MME_DMA_SYSMEMBAR 0x056c +#define NVC997_MME_DMA_SYSMEMBAR_V 0:0 + +#define NVC997_MME_DMA_SYNC 0x0570 +#define NVC997_MME_DMA_SYNC_VALUE 31:0 + +#define NVC997_SET_MME_DATA_FIFO_CONFIG 0x0574 +#define NVC997_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE 2:0 +#define NVC997_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_0KB 0x00000000 +#define NVC997_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_4KB 0x00000001 +#define NVC997_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_8KB 0x00000002 +#define NVC997_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_12KB 0x00000003 +#define NVC997_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_16KB 0x00000004 + +#define NVC997_SET_VERTEX_STREAM_SIZE_A(j) (0x0600+(j)*8) +#define NVC997_SET_VERTEX_STREAM_SIZE_A_UPPER 7:0 + +#define NVC997_SET_VERTEX_STREAM_SIZE_B(j) (0x0604+(j)*8) +#define NVC997_SET_VERTEX_STREAM_SIZE_B_LOWER 31:0 + +#define NVC997_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVC997_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVC997_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVC997_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVC997_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVC997_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVC997_SET_RASTER_INPUT 0x0740 +#define NVC997_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVC997_SET_STREAM_OUTPUT 0x0744 +#define NVC997_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVC997_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVC997_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVC997_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVC997_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVC997_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVC997_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVC997_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVC997_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVC997_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC997_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC997_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC997_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVC997_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC997_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC997_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVC997_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NVC997_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVC997_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVC997_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVC997_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVC997_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVC997_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC997_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVC997_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC997_SET_STENCIL_ZERO_BANDWIDTH_CLEAR 0x07b0 +#define NVC997_SET_STENCIL_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVC997_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVC997_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVC997_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVC997_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVC997_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVC997_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVC997_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVC997_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVC997_SET_CULL_BEFORE_FETCH 0x07dc +#define NVC997_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVC997_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVC997_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVC997_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVC997_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVC997_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVC997_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVC997_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVC997_SET_ZCULL_STORAGE_A 0x07e8 +#define NVC997_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVC997_SET_ZCULL_STORAGE_B 0x07ec +#define NVC997_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVC997_SET_ZCULL_STORAGE_C 0x07f0 +#define NVC997_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVC997_SET_ZCULL_STORAGE_D 0x07f4 +#define NVC997_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVC997_SET_ZT_READ_ONLY 0x07f8 +#define NVC997_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVC997_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVC997_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVC997_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVC997_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVC997_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVC997_THROTTLE_SM 0x07fc +#define NVC997_THROTTLE_SM_MULTIPLY_ADD 0:0 +#define NVC997_THROTTLE_SM_MULTIPLY_ADD_FALSE 0x00000000 +#define NVC997_THROTTLE_SM_MULTIPLY_ADD_TRUE 0x00000001 + +#define NVC997_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVC997_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVC997_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVC997_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVC997_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVC997_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVC997_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVC997_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVC997_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVC997_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVC997_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVC997_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVC997_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVC997_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVC997_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVC997_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVC997_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVC997_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVC997_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVC997_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC997_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVC997_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVC997_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC997_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC997_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVC997_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC997_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVC997_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVC997_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVC997_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVC997_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVC997_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVC997_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVC997_SET_COLOR_TARGET_C_ROP_SLICE_MAP(j) (0x0824+(j)*64) +#define NVC997_SET_COLOR_TARGET_C_ROP_SLICE_MAP_VIRTUAL_ADDRESS_MASK 31:0 + +#define NVC997_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVC997_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVC997_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVC997_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVC997_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVC997_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVC997_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVC997_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVC997_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVC997_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVC997_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVC997_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVC997_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVC997_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVC997_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVC997_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVC997_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVC997_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVC997_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC997_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVC997_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVC997_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC997_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVC997_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVC997_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVC997_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVC997_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVC997_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVC997_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVC997_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVC997_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVC997_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVC997_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVC997_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVC997_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVC997_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVC997_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVC997_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVC997_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVC997_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC997_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVC997_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVC997_SET_STATISTICS_COUNTER 0x0d68 +#define NVC997_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVC997_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVC997_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVC997_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVC997_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVC997_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVC997_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVC997_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVC997_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVC997_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVC997_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVC997_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVC997_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVC997_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVC997_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVC997_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVC997_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 +#define NVC997_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE 16:16 +#define NVC997_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVC997_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC997_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC997_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVC997_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC997_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC997_SET_VERTEX_ARRAY_START 0x0d74 +#define NVC997_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVC997_DRAW_VERTEX_ARRAY 0x0d78 +#define NVC997_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVC997_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVC997_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVC997_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVC997_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVC997_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVC997_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVC997_SET_Z_CLEAR_VALUE 0x0d90 +#define NVC997_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVC997_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC997_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC997_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC997_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVC997_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVC997_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVC997_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC997_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC997_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVC997_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVC997_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVC997_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVC997_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVC997_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVC997_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVC997_SET_FRONT_POLYGON_MODE 0x0dac +#define NVC997_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVC997_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC997_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC997_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC997_SET_BACK_POLYGON_MODE 0x0db0 +#define NVC997_SET_BACK_POLYGON_MODE_V 31:0 +#define NVC997_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVC997_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVC997_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVC997_SET_POLY_SMOOTH 0x0db4 +#define NVC997_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVC997_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVC997_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVC997_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVC997_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVC997_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVC997_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVC997_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVC997_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVC997_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVC997_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVC997_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVC997_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVC997_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVC997_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVC997_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVC997_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVC997_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVC997_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_PATCH 0x0dcc +#define NVC997_SET_PATCH_SIZE 7:0 + +#define NVC997_SET_ITERATED_BLEND 0x0dd0 +#define NVC997_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVC997_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVC997_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVC997_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVC997_SET_ZCULL_CRITERION 0x0dd8 +#define NVC997_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVC997_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVC997_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVC997_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVC997_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVC997_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVC997_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVC997_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVC997_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVC997_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVC997_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVC997_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVC997_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVC997_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVC997_SET_ZCULL_CRITERION_SREF 23:16 +#define NVC997_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVC997_PIXEL_SHADER_BARRIER 0x0de0 +#define NVC997_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVC997_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVC997_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 +#define NVC997_PIXEL_SHADER_BARRIER_BARRIER_LOCATION 1:1 +#define NVC997_PIXEL_SHADER_BARRIER_BARRIER_LOCATION_BLOCK_BEFORE_PS 0x00000000 +#define NVC997_PIXEL_SHADER_BARRIER_BARRIER_LOCATION_BLOCK_BEFORE_PS_AND_ZTEST 0x00000001 + +#define NVC997_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC997_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC997_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVC997_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVC997_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVC997_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVC997_MME_DMA_WRITE_METHOD_BARRIER 0x0dec +#define NVC997_MME_DMA_WRITE_METHOD_BARRIER_V 0:0 + +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVC997_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVC997_SET_WINDOW_OFFSET_X 0x0df8 +#define NVC997_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVC997_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVC997_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVC997_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVC997_SET_SCISSOR_ENABLE_V 0:0 +#define NVC997_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVC997_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVC997_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVC997_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVC997_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVC997_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVC997_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVC997_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVC997_SET_VPC_PERF_KNOB 0x0f14 +#define NVC997_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVC997_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVC997_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVC997_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVC997_PM_LOCAL_TRIGGER 0x0f18 +#define NVC997_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVC997_SET_POST_Z_PS_IMASK 0x0f1c +#define NVC997_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVC997_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVC997_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVC997_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVC997_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVC997_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVC997_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVC997_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVC997_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVC997_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVC997_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVC997_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVC997_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVC997_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVC997_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVC997_SET_BACK_STENCIL_MASK 0x0f58 +#define NVC997_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVC997_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVC997_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVC997_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVC997_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVC997_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVC997_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVC997_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVC997_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVC997_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVC997_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVC997_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVC997_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVC997_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVC997_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVC997_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVC997_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVC997_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVC997_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVC997_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVC997_SET_SAMPLE_MASK 0x0fa4 +#define NVC997_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVC997_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVC997_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVC997_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVC997_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVC997_SET_CT_MRT_ENABLE 0x0fac +#define NVC997_SET_CT_MRT_ENABLE_V 0:0 +#define NVC997_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVC997_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVC997_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVC997_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVC997_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVC997_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVC997_SET_TIR 0x0fb4 +#define NVC997_SET_TIR_MODE 1:0 +#define NVC997_SET_TIR_MODE_DISABLED 0x00000000 +#define NVC997_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVC997_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVC997_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVC997_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVC997_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVC997_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC997_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC997_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVC997_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVC997_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVC997_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVC997_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVC997_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVC997_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVC997_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVC997_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVC997_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVC997_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVC997_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_TIR_MODULATION 0x0fd4 +#define NVC997_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVC997_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVC997_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVC997_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVC997_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVC997_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVC997_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVC997_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVC997_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVC997_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVC997_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVC997_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVC997_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVC997_SET_ZT_A 0x0fe0 +#define NVC997_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_ZT_B 0x0fe4 +#define NVC997_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_ZT_FORMAT 0x0fe8 +#define NVC997_SET_ZT_FORMAT_V 4:0 +#define NVC997_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVC997_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVC997_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVC997_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVC997_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVC997_SET_ZT_FORMAT_V_V8Z24 0x00000018 +#define NVC997_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVC997_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 +#define NVC997_SET_ZT_FORMAT_V_X8Z24_X16V8S8 0x0000001D +#define NVC997_SET_ZT_FORMAT_V_ZF32_X16V8X8 0x0000001E +#define NVC997_SET_ZT_FORMAT_V_ZF32_X16V8S8 0x0000001F + +#define NVC997_SET_ZT_BLOCK_SIZE 0x0fec +#define NVC997_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVC997_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC997_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVC997_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC997_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC997_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC997_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC997_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC997_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC997_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVC997_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVC997_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVC997_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVC997_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVC997_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVC997_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVC997_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVC997_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVC997_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVC997_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC997_SET_VIEWPORT_MULTICAST 0x1004 +#define NVC997_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVC997_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVC997_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVC997_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVC997_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVC997_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVC997_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVC997_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVC997_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVC997_SET_RESERVED_SW_METHOD00 0x1014 +#define NVC997_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC997_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVC997_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC997_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVC997_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC997_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVC997_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVC997_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVC997_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVC997_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_RESERVED_SW_METHOD01 0x1028 +#define NVC997_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD02 0x102c +#define NVC997_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC997_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVC997_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVC997_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVC997_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVC997_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVC997_SET_SPARE_NOOP01 0x1044 +#define NVC997_SET_SPARE_NOOP01_V 31:0 + +#define NVC997_SET_SPARE_NOOP02 0x1048 +#define NVC997_SET_SPARE_NOOP02_V 31:0 + +#define NVC997_SET_SPARE_NOOP03 0x104c +#define NVC997_SET_SPARE_NOOP03_V 31:0 + +#define NVC997_SET_SPARE_NOOP04 0x1050 +#define NVC997_SET_SPARE_NOOP04_V 31:0 + +#define NVC997_SET_SPARE_NOOP05 0x1054 +#define NVC997_SET_SPARE_NOOP05_V 31:0 + +#define NVC997_SET_SPARE_NOOP06 0x1058 +#define NVC997_SET_SPARE_NOOP06_V 31:0 + +#define NVC997_SET_SPARE_NOOP07 0x105c +#define NVC997_SET_SPARE_NOOP07_V 31:0 + +#define NVC997_SET_SPARE_NOOP08 0x1060 +#define NVC997_SET_SPARE_NOOP08_V 31:0 + +#define NVC997_SET_SPARE_NOOP09 0x1064 +#define NVC997_SET_SPARE_NOOP09_V 31:0 + +#define NVC997_SET_SPARE_NOOP10 0x1068 +#define NVC997_SET_SPARE_NOOP10_V 31:0 + +#define NVC997_SET_SPARE_NOOP11 0x106c +#define NVC997_SET_SPARE_NOOP11_V 31:0 + +#define NVC997_SET_SPARE_NOOP12 0x1070 +#define NVC997_SET_SPARE_NOOP12_V 31:0 + +#define NVC997_SET_SPARE_NOOP13 0x1074 +#define NVC997_SET_SPARE_NOOP13_V 31:0 + +#define NVC997_SET_SPARE_NOOP14 0x1078 +#define NVC997_SET_SPARE_NOOP14_V 31:0 + +#define NVC997_SET_SPARE_NOOP15 0x107c +#define NVC997_SET_SPARE_NOOP15_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVC997_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVC997_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVC997_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD06 0x10bc +#define NVC997_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVC997_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVC997_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVC997_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVC997_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVC997_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVC997_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVC997_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD13 0x10dc +#define NVC997_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVC997_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVC997_UNBIND_ALL 0x10f4 +#define NVC997_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVC997_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVC997_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVC997_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVC997_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC997_SET_RESERVED_SW_METHOD14 0x1100 +#define NVC997_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC997_SET_RESERVED_SW_METHOD15 0x1104 +#define NVC997_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC997_NO_OPERATION_DATA_HI 0x110c +#define NVC997_NO_OPERATION_DATA_HI_V 31:0 + +#define NVC997_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVC997_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVC997_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVC997_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVC997_PM_TRIGGER_END 0x1114 +#define NVC997_PM_TRIGGER_END_V 31:0 + +#define NVC997_SET_VERTEX_ID_BASE 0x1118 +#define NVC997_SET_VERTEX_ID_BASE_V 31:0 + +#define NVC997_SET_STENCIL_COMPRESSION 0x111c +#define NVC997_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVC997_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVC997_SET_TIR_CONTROL 0x1130 +#define NVC997_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVC997_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC997_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC997_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVC997_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVC997_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVC997_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVC997_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVC997_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 +#define NVC997_SET_TIR_CONTROL_REDUCTION_MODE 2:2 +#define NVC997_SET_TIR_CONTROL_REDUCTION_MODE_AFFINITY_MAP 0x00000000 +#define NVC997_SET_TIR_CONTROL_REDUCTION_MODE_TRUNCATION 0x00000001 + +#define NVC997_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVC997_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVC997_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVC997_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVC997_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVC997_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVC997_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVC997_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVC997_SET_FILL_VIA_TRIANGLE 0x113c +#define NVC997_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVC997_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVC997_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVC997_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVC997_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVC997_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVC997_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVC997_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVC997_FLUSH_PENDING_WRITES 0x1144 +#define NVC997_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVC997_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVC997_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC997_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC997_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC997_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVC997_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVC997_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVC997_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVC997_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVC997_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVC997_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVC997_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVC997_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVC997_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVC997_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVC997_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVC997_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVC997_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVC997_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVC997_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVC997_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVC997_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVC997_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC997_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC997_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVC997_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC997_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_SCREEN_STATE_MASK 0x1204 +#define NVC997_SET_SCREEN_STATE_MASK_MASK 3:0 + +#define NVC997_SET_ZT_SPARSE 0x1208 +#define NVC997_SET_ZT_SPARSE_ENABLE 0:0 +#define NVC997_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVC997_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVC997_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC997_SET_CT_SELECT 0x121c +#define NVC997_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVC997_SET_CT_SELECT_TARGET0 6:4 +#define NVC997_SET_CT_SELECT_TARGET1 9:7 +#define NVC997_SET_CT_SELECT_TARGET2 12:10 +#define NVC997_SET_CT_SELECT_TARGET3 15:13 +#define NVC997_SET_CT_SELECT_TARGET4 18:16 +#define NVC997_SET_CT_SELECT_TARGET5 21:19 +#define NVC997_SET_CT_SELECT_TARGET6 24:22 +#define NVC997_SET_CT_SELECT_TARGET7 27:25 + +#define NVC997_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVC997_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVC997_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVC997_SET_ZT_SIZE_A 0x1228 +#define NVC997_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVC997_SET_ZT_SIZE_B 0x122c +#define NVC997_SET_ZT_SIZE_B_HEIGHT 17:0 + +#define NVC997_SET_ZT_SIZE_C 0x1230 +#define NVC997_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVC997_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVC997_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVC997_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVC997_SET_SAMPLER_BINDING 0x1234 +#define NVC997_SET_SAMPLER_BINDING_V 0:0 +#define NVC997_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVC997_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVC997_DRAW_AUTO 0x123c +#define NVC997_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVC997_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVC997_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVC997_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVC997_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVC997_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVC997_SET_BACK_END_COPY_A 0x1264 +#define NVC997_SET_BACK_END_COPY_A_DWORDS 7:0 +#define NVC997_SET_BACK_END_COPY_A_SATURATE32_ENABLE 8:8 +#define NVC997_SET_BACK_END_COPY_A_SATURATE32_ENABLE_FALSE 0x00000000 +#define NVC997_SET_BACK_END_COPY_A_SATURATE32_ENABLE_TRUE 0x00000001 +#define NVC997_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE 12:12 +#define NVC997_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_FALSE 0x00000000 +#define NVC997_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_BACK_END_COPY_B 0x1268 +#define NVC997_SET_BACK_END_COPY_B_SRC_ADDRESS_UPPER 7:0 + +#define NVC997_SET_BACK_END_COPY_C 0x126c +#define NVC997_SET_BACK_END_COPY_C_SRC_ADDRESS_LOWER 31:0 + +#define NVC997_SET_BACK_END_COPY_D 0x1270 +#define NVC997_SET_BACK_END_COPY_D_DEST_ADDRESS_UPPER 7:0 + +#define NVC997_SET_BACK_END_COPY_E 0x1274 +#define NVC997_SET_BACK_END_COPY_E_DEST_ADDRESS_LOWER 31:0 + +#define NVC997_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVC997_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 19:0 + +#define NVC997_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVC997_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVC997_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC997_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVC997_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVC997_CLEAR_ZCULL_REGION 0x12c8 +#define NVC997_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVC997_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVC997_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVC997_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVC997_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC997_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC997_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVC997_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVC997_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVC997_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVC997_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVC997_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVC997_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVC997_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVC997_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVC997_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVC997_SET_DEPTH_TEST 0x12cc +#define NVC997_SET_DEPTH_TEST_ENABLE 0:0 +#define NVC997_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVC997_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_FILL_MODE 0x12d0 +#define NVC997_SET_FILL_MODE_V 31:0 +#define NVC997_SET_FILL_MODE_V_POINT 0x00000001 +#define NVC997_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVC997_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVC997_SET_SHADE_MODE 0x12d4 +#define NVC997_SET_SHADE_MODE_V 31:0 +#define NVC997_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVC997_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVC997_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVC997_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVC997_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVC997_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVC997_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVC997_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVC997_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVC997_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVC997_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVC997_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVC997_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVC997_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_DEPTH_WRITE 0x12e8 +#define NVC997_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVC997_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_ALPHA_TEST 0x12ec +#define NVC997_SET_ALPHA_TEST_ENABLE 0:0 +#define NVC997_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVC997_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVC997_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVC997_DRAW_INLINE_INDEX4X8 0x1304 +#define NVC997_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVC997_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVC997_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVC997_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVC997_D3D_SET_CULL_MODE 0x1308 +#define NVC997_D3D_SET_CULL_MODE_V 31:0 +#define NVC997_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVC997_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVC997_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVC997_SET_DEPTH_FUNC 0x130c +#define NVC997_SET_DEPTH_FUNC_V 31:0 +#define NVC997_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVC997_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVC997_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC997_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC997_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVC997_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC997_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC997_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC997_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVC997_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVC997_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC997_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC997_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVC997_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC997_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC997_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC997_SET_ALPHA_REF 0x1310 +#define NVC997_SET_ALPHA_REF_V 31:0 + +#define NVC997_SET_ALPHA_FUNC 0x1314 +#define NVC997_SET_ALPHA_FUNC_V 31:0 +#define NVC997_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVC997_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVC997_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC997_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC997_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVC997_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC997_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC997_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC997_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVC997_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVC997_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC997_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC997_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVC997_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC997_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC997_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC997_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVC997_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVC997_SET_BLEND_CONST_RED 0x131c +#define NVC997_SET_BLEND_CONST_RED_V 31:0 + +#define NVC997_SET_BLEND_CONST_GREEN 0x1320 +#define NVC997_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVC997_SET_BLEND_CONST_BLUE 0x1324 +#define NVC997_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVC997_SET_BLEND_CONST_ALPHA 0x1328 +#define NVC997_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVC997_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC997_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC997_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC997_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC997_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC997_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC997_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVC997_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC997_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC997_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_BLEND_COLOR_OP 0x1340 +#define NVC997_SET_BLEND_COLOR_OP_V 31:0 +#define NVC997_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC997_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC997_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC997_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC997_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC997_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC997_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC997_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC997_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC997_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC997_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC997_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC997_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC997_SET_BLEND_ALPHA_OP 0x134c +#define NVC997_SET_BLEND_ALPHA_OP_V 31:0 +#define NVC997_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC997_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC997_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC997_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC997_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC997_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC997_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC997_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC997_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC997_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC997_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC997_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVC997_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVC997_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVC997_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC997_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC997_SET_SINGLE_ROP_CONTROL 0x135c +#define NVC997_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVC997_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_BLEND(i) (0x1360+(i)*4) +#define NVC997_SET_BLEND_ENABLE 0:0 +#define NVC997_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVC997_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_STENCIL_TEST 0x1380 +#define NVC997_SET_STENCIL_TEST_ENABLE 0:0 +#define NVC997_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC997_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_STENCIL_OP_FAIL 0x1384 +#define NVC997_SET_STENCIL_OP_FAIL_V 31:0 +#define NVC997_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC997_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC997_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC997_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC997_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC997_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC997_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC997_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC997_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC997_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC997_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC997_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC997_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC997_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC997_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC997_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC997_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVC997_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC997_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC997_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC997_SET_STENCIL_OP_ZPASS 0x138c +#define NVC997_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVC997_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC997_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC997_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC997_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC997_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC997_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC997_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC997_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC997_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC997_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC997_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC997_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC997_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC997_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC997_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC997_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC997_SET_STENCIL_FUNC 0x1390 +#define NVC997_SET_STENCIL_FUNC_V 31:0 +#define NVC997_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC997_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC997_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC997_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC997_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC997_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC997_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC997_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC997_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC997_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC997_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC997_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC997_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC997_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC997_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC997_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC997_SET_STENCIL_FUNC_REF 0x1394 +#define NVC997_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVC997_SET_STENCIL_FUNC_MASK 0x1398 +#define NVC997_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVC997_SET_STENCIL_MASK 0x139c +#define NVC997_SET_STENCIL_MASK_V 7:0 + +#define NVC997_SET_DRAW_AUTO_START 0x13a4 +#define NVC997_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVC997_SET_PS_SATURATE 0x13a8 +#define NVC997_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVC997_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVC997_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC997_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVC997_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVC997_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC997_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVC997_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVC997_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC997_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVC997_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVC997_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC997_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVC997_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVC997_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC997_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVC997_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVC997_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC997_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVC997_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVC997_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVC997_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVC997_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVC997_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVC997_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVC997_SET_WINDOW_ORIGIN 0x13ac +#define NVC997_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVC997_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVC997_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVC997_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVC997_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVC997_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVC997_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVC997_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC997_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVC997_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVC997_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVC997_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVC997_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVC997_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC997_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC997_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC997_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC997_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC997_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC997_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVC997_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVC997_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVC997_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVC997_SET_PS_WARP_WATERMARKS 0x1450 +#define NVC997_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVC997_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVC997_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVC997_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVC997_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVC997_STORE_ZCULL 0x1464 +#define NVC997_STORE_ZCULL_V 0:0 + +#define NVC997_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVC997_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVC997_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVC997_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVC997_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVC997_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVC997_LOAD_ZCULL 0x1500 +#define NVC997_LOAD_ZCULL_V 0:0 + +#define NVC997_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVC997_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVC997_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVC997_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVC997_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVC997_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVC997_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVC997_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVC997_SET_USER_CLIP_ENABLE 0x1510 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVC997_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVC997_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVC997_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVC997_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_POINT_SIZE 0x1518 +#define NVC997_SET_POINT_SIZE_V 31:0 + +#define NVC997_SET_ZCULL_STATS 0x151c +#define NVC997_SET_ZCULL_STATS_ENABLE 0:0 +#define NVC997_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_POINT_SPRITE 0x1520 +#define NVC997_SET_POINT_SPRITE_ENABLE 0:0 +#define NVC997_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC997_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC997_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC997_CLEAR_REPORT_VALUE 0x1530 +#define NVC997_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVC997_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVC997_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVC997_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVC997_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVC997_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVC997_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC997_CLEAR_REPORT_VALUE_TYPE_SCG_CLOCKS 0x00000009 + +#define NVC997_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVC997_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVC997_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVC997_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVC997_SET_ZT_SELECT 0x1538 +#define NVC997_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVC997_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVC997_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVC997_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVC997_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVC997_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVC997_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVC997_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVC997_SET_RENDER_ENABLE_A 0x1550 +#define NVC997_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_RENDER_ENABLE_B 0x1554 +#define NVC997_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_RENDER_ENABLE_C 0x1558 +#define NVC997_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC997_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC997_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC997_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC997_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC997_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC997_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC997_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC997_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC997_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC997_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVC997_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVC997_SET_ANTI_ALIASED_LINE 0x1570 +#define NVC997_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVC997_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC997_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC997_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_TEX_HEADER_POOL_C 0x157c +#define NVC997_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC997_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVC997_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVC997_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVC997_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVC997_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVC997_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVC997_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVC997_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVC997_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVC997_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVC997_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVC997_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVC997_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVC997_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVC997_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVC997_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVC997_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVC997_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVC997_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVC997_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVC997_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVC997_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVC997_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVC997_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVC997_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVC997_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVC997_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVC997_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVC997_SET_SRGB_WRITE 0x15b8 +#define NVC997_SET_SRGB_WRITE_ENABLE 0:0 +#define NVC997_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_DEPTH_BIAS 0x15bc +#define NVC997_SET_DEPTH_BIAS_V 31:0 + +#define NVC997_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVC997_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVC997_SET_RT_LAYER 0x15cc +#define NVC997_SET_RT_LAYER_V 15:0 +#define NVC997_SET_RT_LAYER_CONTROL 16:16 +#define NVC997_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVC997_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVC997_SET_ANTI_ALIAS 0x15d0 +#define NVC997_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVC997_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVC997_SET_EDGE_FLAG 0x15e4 +#define NVC997_SET_EDGE_FLAG_V 0:0 +#define NVC997_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVC997_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVC997_DRAW_INLINE_INDEX 0x15e8 +#define NVC997_DRAW_INLINE_INDEX_V 31:0 + +#define NVC997_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVC997_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVC997_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVC997_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVC997_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVC997_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVC997_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVC997_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVC997_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVC997_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVC997_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVC997_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVC997_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVC997_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVC997_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVC997_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVC997_SET_POINT_SPRITE_SELECT 0x1604 +#define NVC997_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVC997_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVC997_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVC997_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVC997_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVC997_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVC997_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVC997_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVC997_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVC997_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVC997_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVC997_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVC997_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVC997_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVC997_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVC997_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVC997_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVC997_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVC997_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVC997_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVC997_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVC997_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVC997_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVC997_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVC997_END 0x1614 +#define NVC997_END_V 0:0 + +#define NVC997_BEGIN 0x1618 +#define NVC997_BEGIN_OP 15:0 +#define NVC997_BEGIN_OP_POINTS 0x00000000 +#define NVC997_BEGIN_OP_LINES 0x00000001 +#define NVC997_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVC997_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVC997_BEGIN_OP_TRIANGLES 0x00000004 +#define NVC997_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVC997_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVC997_BEGIN_OP_QUADS 0x00000007 +#define NVC997_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVC997_BEGIN_OP_POLYGON 0x00000009 +#define NVC997_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVC997_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVC997_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_BEGIN_OP_PATCH 0x0000000E +#define NVC997_BEGIN_PRIMITIVE_ID 24:24 +#define NVC997_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVC997_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVC997_BEGIN_INSTANCE_ID 27:26 +#define NVC997_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVC997_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVC997_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVC997_BEGIN_SPLIT_MODE 30:29 +#define NVC997_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVC997_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVC997_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVC997_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVC997_BEGIN_INSTANCE_ITERATE_ENABLE 31:31 +#define NVC997_BEGIN_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVC997_BEGIN_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_VERTEX_ID_COPY 0x161c +#define NVC997_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVC997_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVC997_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVC997_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVC997_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVC997_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVC997_LOAD_PRIMITIVE_ID 0x1624 +#define NVC997_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVC997_SET_SHADER_BASED_CULL 0x162c +#define NVC997_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVC997_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVC997_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVC997_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVC997_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_CLASS_VERSION 0x1638 +#define NVC997_SET_CLASS_VERSION_CURRENT 15:0 +#define NVC997_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC997_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVC997_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVC997_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVC997_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVC997_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVC997_SET_DA_OUTPUT 0x164c +#define NVC997_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVC997_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVC997_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVC997_SET_ANTI_ALIASED_POINT 0x1658 +#define NVC997_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVC997_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_POINT_CENTER_MODE 0x165c +#define NVC997_SET_POINT_CENTER_MODE_V 31:0 +#define NVC997_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVC997_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVC997_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVC997_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVC997_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVC997_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVC997_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVC997_SET_LINE_STIPPLE 0x166c +#define NVC997_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVC997_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVC997_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVC997_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVC997_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVC997_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVC997_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVC997_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVC997_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVC997_SET_PROVOKING_VERTEX 0x1684 +#define NVC997_SET_PROVOKING_VERTEX_V 0:0 +#define NVC997_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVC997_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVC997_SET_TWO_SIDED_LIGHT 0x1688 +#define NVC997_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVC997_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_POLYGON_STIPPLE 0x168c +#define NVC997_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVC997_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_SHADER_CONTROL 0x1690 +#define NVC997_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVC997_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVC997_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVC997_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVC997_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC997_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC997_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVC997_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC997_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVC997_CHECK_CLASS_VERSION 0x16a0 +#define NVC997_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVC997_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC997_SET_SPH_VERSION 0x16a4 +#define NVC997_SET_SPH_VERSION_CURRENT 15:0 +#define NVC997_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC997_CHECK_SPH_VERSION 0x16a8 +#define NVC997_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVC997_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC997_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVC997_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVC997_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVC997_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVC997_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVC997_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVC997_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVC997_SET_SCG_GRAPHICS_PRIORITY 0x16bc +#define NVC997_SET_SCG_GRAPHICS_PRIORITY_PRIORITY 5:0 + +#define NVC997_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS(i) (0x16c0+(i)*4) +#define NVC997_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS_V 31:0 + +#define NVC997_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVC997_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVC997_SET_AAM_VERSION 0x1790 +#define NVC997_SET_AAM_VERSION_CURRENT 15:0 +#define NVC997_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC997_CHECK_AAM_VERSION 0x1794 +#define NVC997_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVC997_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC997_SET_ZT_LAYER 0x179c +#define NVC997_SET_ZT_LAYER_OFFSET 15:0 + +#define NVC997_SET_INDEX_BUFFER_A 0x17c8 +#define NVC997_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVC997_SET_INDEX_BUFFER_B 0x17cc +#define NVC997_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVC997_SET_INDEX_BUFFER_E 0x17d8 +#define NVC997_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVC997_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVC997_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVC997_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVC997_SET_INDEX_BUFFER_F 0x17dc +#define NVC997_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVC997_DRAW_INDEX_BUFFER 0x17e0 +#define NVC997_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVC997_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVC997_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVC997_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVC997_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVC997_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVC997_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVC997_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVC997_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVC997_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVC997_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVC997_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVC997_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVC997_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVC997_OGL_SET_CULL 0x1918 +#define NVC997_OGL_SET_CULL_ENABLE 0:0 +#define NVC997_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVC997_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVC997_OGL_SET_FRONT_FACE 0x191c +#define NVC997_OGL_SET_FRONT_FACE_V 31:0 +#define NVC997_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVC997_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVC997_OGL_SET_CULL_FACE 0x1920 +#define NVC997_OGL_SET_CULL_FACE_V 31:0 +#define NVC997_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVC997_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVC997_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVC997_SET_VIEWPORT_PIXEL 0x1924 +#define NVC997_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVC997_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVC997_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVC997_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVC997_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVC997_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVC997_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE 17:16 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_USE_FIELD_MIN_Z_ZERO_MAX_Z_ONE 0x00000000 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MIN_Z_MAX_Z 0x00000001 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_ZERO_ONE 0x00000002 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MINUS_INF_PLUS_INF 0x00000003 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVC997_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVC997_SET_USER_CLIP_OP 0x1940 +#define NVC997_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVC997_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVC997_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVC997_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVC997_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVC997_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVC997_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVC997_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVC997_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVC997_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVC997_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVC997_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVC997_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVC997_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVC997_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVC997_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVC997_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVC997_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVC997_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVC997_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVC997_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVC997_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVC997_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVC997_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVC997_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC997_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC997_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC997_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC997_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC997_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVC997_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVC997_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVC997_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVC997_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVC997_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVC997_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVC997_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVC997_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVC997_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVC997_INVALIDATE_ZCULL 0x1958 +#define NVC997_INVALIDATE_ZCULL_V 31:0 +#define NVC997_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVC997_SET_ZCULL 0x1968 +#define NVC997_SET_ZCULL_Z_ENABLE 0:0 +#define NVC997_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVC997_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_ZCULL_BOUNDS 0x196c +#define NVC997_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVC997_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVC997_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVC997_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVC997_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVC997_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVC997_ZCULL_SYNC 0x1978 +#define NVC997_ZCULL_SYNC_V 31:0 + +#define NVC997_SET_CLIP_ID_TEST 0x197c +#define NVC997_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVC997_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVC997_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVC997_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVC997_SET_CLIP_ID 0x1984 +#define NVC997_SET_CLIP_ID_V 31:0 + +#define NVC997_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVC997_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVC997_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVC997_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVC997_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVC997_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVC997_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVC997_SET_LOGIC_OP 0x19c4 +#define NVC997_SET_LOGIC_OP_ENABLE 0:0 +#define NVC997_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVC997_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_LOGIC_OP_FUNC 0x19c8 +#define NVC997_SET_LOGIC_OP_FUNC_V 31:0 +#define NVC997_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVC997_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVC997_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVC997_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVC997_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVC997_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVC997_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVC997_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVC997_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVC997_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVC997_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVC997_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVC997_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVC997_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVC997_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVC997_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVC997_SET_Z_COMPRESSION 0x19cc +#define NVC997_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVC997_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC997_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC997_CLEAR_SURFACE 0x19d0 +#define NVC997_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVC997_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVC997_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVC997_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVC997_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVC997_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVC997_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVC997_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVC997_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVC997_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVC997_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVC997_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVC997_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVC997_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVC997_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVC997_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVC997_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVC997_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVC997_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVC997_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVC997_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVC997_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVC997_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVC997_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVC997_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVC997_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVC997_SET_CT_WRITE_R_ENABLE 0:0 +#define NVC997_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVC997_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVC997_SET_CT_WRITE_G_ENABLE 4:4 +#define NVC997_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVC997_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVC997_SET_CT_WRITE_B_ENABLE 8:8 +#define NVC997_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVC997_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVC997_SET_CT_WRITE_A_ENABLE 12:12 +#define NVC997_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVC997_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVC997_PIPE_NOP 0x1a2c +#define NVC997_PIPE_NOP_V 31:0 + +#define NVC997_SET_SPARE00 0x1a30 +#define NVC997_SET_SPARE00_V 31:0 + +#define NVC997_SET_SPARE01 0x1a34 +#define NVC997_SET_SPARE01_V 31:0 + +#define NVC997_SET_SPARE02 0x1a38 +#define NVC997_SET_SPARE02_V 31:0 + +#define NVC997_SET_SPARE03 0x1a3c +#define NVC997_SET_SPARE03_V 31:0 + +#define NVC997_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC997_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC997_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC997_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC997_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC997_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC997_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVC997_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC997_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVC997_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVC997_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVC997_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVC997_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVC997_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC997_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_SCG_CLOCKS 0x00000008 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_TIMESTAMP 0x00000014 +#define NVC997_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC997_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVC997_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVC997_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC997_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC997_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVC997_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVC997_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVC997_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVC997_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVC997_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVC997_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVC997_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVC997_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVC997_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVC997_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVC997_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVC997_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVC997_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVC997_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVC997_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVC997_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVC997_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVC997_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVC997_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVC997_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVC997_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVC997_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVC997_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC997_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVC997_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVC997_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVC997_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVC997_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVC997_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVC997_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVC997_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVC997_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVC997_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVC997_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVC997_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVC997_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVC997_SET_PIPELINE_RESERVED_B(j) (0x2004+(j)*64) +#define NVC997_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVC997_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVC997_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVC997_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVC997_SET_PIPELINE_REGISTER_COUNT_V 8:0 + +#define NVC997_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVC997_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVC997_SET_PIPELINE_PROGRAM_ADDRESS_A(j) (0x2014+(j)*64) +#define NVC997_SET_PIPELINE_PROGRAM_ADDRESS_A_UPPER 7:0 + +#define NVC997_SET_PIPELINE_PROGRAM_ADDRESS_B(j) (0x2018+(j)*64) +#define NVC997_SET_PIPELINE_PROGRAM_ADDRESS_B_LOWER 31:0 + +#define NVC997_SET_PIPELINE_PROGRAM_PREFETCH(j) (0x201c+(j)*64) +#define NVC997_SET_PIPELINE_PROGRAM_PREFETCH_SIZE_IN_BLOCKS 6:0 + +#define NVC997_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVC997_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVC997_SET_FALCON00 0x2300 +#define NVC997_SET_FALCON00_V 31:0 + +#define NVC997_SET_FALCON01 0x2304 +#define NVC997_SET_FALCON01_V 31:0 + +#define NVC997_SET_FALCON02 0x2308 +#define NVC997_SET_FALCON02_V 31:0 + +#define NVC997_SET_FALCON03 0x230c +#define NVC997_SET_FALCON03_V 31:0 + +#define NVC997_SET_FALCON04 0x2310 +#define NVC997_SET_FALCON04_V 31:0 + +#define NVC997_SET_FALCON05 0x2314 +#define NVC997_SET_FALCON05_V 31:0 + +#define NVC997_SET_FALCON06 0x2318 +#define NVC997_SET_FALCON06_V 31:0 + +#define NVC997_SET_FALCON07 0x231c +#define NVC997_SET_FALCON07_V 31:0 + +#define NVC997_SET_FALCON08 0x2320 +#define NVC997_SET_FALCON08_V 31:0 + +#define NVC997_SET_FALCON09 0x2324 +#define NVC997_SET_FALCON09_V 31:0 + +#define NVC997_SET_FALCON10 0x2328 +#define NVC997_SET_FALCON10_V 31:0 + +#define NVC997_SET_FALCON11 0x232c +#define NVC997_SET_FALCON11_V 31:0 + +#define NVC997_SET_FALCON12 0x2330 +#define NVC997_SET_FALCON12_V 31:0 + +#define NVC997_SET_FALCON13 0x2334 +#define NVC997_SET_FALCON13_V 31:0 + +#define NVC997_SET_FALCON14 0x2338 +#define NVC997_SET_FALCON14_V 31:0 + +#define NVC997_SET_FALCON15 0x233c +#define NVC997_SET_FALCON15_V 31:0 + +#define NVC997_SET_FALCON16 0x2340 +#define NVC997_SET_FALCON16_V 31:0 + +#define NVC997_SET_FALCON17 0x2344 +#define NVC997_SET_FALCON17_V 31:0 + +#define NVC997_SET_FALCON18 0x2348 +#define NVC997_SET_FALCON18_V 31:0 + +#define NVC997_SET_FALCON19 0x234c +#define NVC997_SET_FALCON19_V 31:0 + +#define NVC997_SET_FALCON20 0x2350 +#define NVC997_SET_FALCON20_V 31:0 + +#define NVC997_SET_FALCON21 0x2354 +#define NVC997_SET_FALCON21_V 31:0 + +#define NVC997_SET_FALCON22 0x2358 +#define NVC997_SET_FALCON22_V 31:0 + +#define NVC997_SET_FALCON23 0x235c +#define NVC997_SET_FALCON23_V 31:0 + +#define NVC997_SET_FALCON24 0x2360 +#define NVC997_SET_FALCON24_V 31:0 + +#define NVC997_SET_FALCON25 0x2364 +#define NVC997_SET_FALCON25_V 31:0 + +#define NVC997_SET_FALCON26 0x2368 +#define NVC997_SET_FALCON26_V 31:0 + +#define NVC997_SET_FALCON27 0x236c +#define NVC997_SET_FALCON27_V 31:0 + +#define NVC997_SET_FALCON28 0x2370 +#define NVC997_SET_FALCON28_V 31:0 + +#define NVC997_SET_FALCON29 0x2374 +#define NVC997_SET_FALCON29_V 31:0 + +#define NVC997_SET_FALCON30 0x2378 +#define NVC997_SET_FALCON30_V 31:0 + +#define NVC997_SET_FALCON31 0x237c +#define NVC997_SET_FALCON31_V 31:0 + +#define NVC997_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVC997_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVC997_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVC997_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVC997_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVC997_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVC997_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVC997_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVC997_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVC997_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVC997_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVC997_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVC997_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVC997_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVC997_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVC997_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVC997_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVC997_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVC997_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVC997_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVC997_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC997_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC997_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVC997_SET_TRAP_HANDLER_A 0x25f8 +#define NVC997_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC997_SET_TRAP_HANDLER_B 0x25fc +#define NVC997_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC997_SET_COLOR_CLAMP 0x2600 +#define NVC997_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVC997_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVC997_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVC997_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVC997_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVC997_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVC997_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVC997_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVC997_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC997_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC997_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC997_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC997_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC997_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC997_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC997_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC997_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC997_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC997_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC997_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC997_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC997_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC997_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVC997_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVC997_CALL_MME_MACRO_V 31:0 + +#define NVC997_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVC997_CALL_MME_DATA_V 31:0 + +#endif /* _cl_ada_a_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/clcb97.h b/src/common/sdk/nvidia/inc/class/clcb97.h index 44bd064ff..7528a2d8e 100644 --- a/src/common/sdk/nvidia/inc/class/clcb97.h +++ b/src/common/sdk/nvidia/inc/class/clcb97.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,7 +21,4460 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef __gh100_clcb97_h__ -#define __gh100_clcb97_h__ +#ifndef _cl_hopper_a_h_ +#define _cl_hopper_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl hopper_a */ + +#include "nvtypes.h" + #define HOPPER_A 0xCB97 -#endif // __gh100_clcb97_h__ + +#define NVCB97_SET_OBJECT 0x0000 +#define NVCB97_SET_OBJECT_CLASS_ID 15:0 +#define NVCB97_SET_OBJECT_ENGINE_ID 20:16 + +#define NVCB97_NO_OPERATION 0x0100 +#define NVCB97_NO_OPERATION_V 31:0 + +#define NVCB97_SET_NOTIFY_A 0x0104 +#define NVCB97_SET_NOTIFY_A_ADDRESS_UPPER 24:0 + +#define NVCB97_SET_NOTIFY_B 0x0108 +#define NVCB97_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVCB97_NOTIFY 0x010c +#define NVCB97_NOTIFY_TYPE 31:0 +#define NVCB97_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVCB97_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVCB97_WAIT_FOR_IDLE 0x0110 +#define NVCB97_WAIT_FOR_IDLE_V 31:0 + +#define NVCB97_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NVCB97_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NVCB97_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NVCB97_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NVCB97_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NVCB97_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NVCB97_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NVCB97_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NVCB97_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NVCB97_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NVCB97_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NVCB97_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NVCB97_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NVCB97_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NVCB97_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER 0x0128 +#define NVCB97_PEER_SEMAPHORE_RELEASE_OFFSET_UPPER_V 7:0 + +#define NVCB97_PEER_SEMAPHORE_RELEASE_OFFSET 0x012c +#define NVCB97_PEER_SEMAPHORE_RELEASE_OFFSET_V 31:0 + +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVCB97_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVCB97_SEND_GO_IDLE 0x013c +#define NVCB97_SEND_GO_IDLE_V 31:0 + +#define NVCB97_PM_TRIGGER 0x0140 +#define NVCB97_PM_TRIGGER_V 31:0 + +#define NVCB97_PM_TRIGGER_WFI 0x0144 +#define NVCB97_PM_TRIGGER_WFI_V 31:0 + +#define NVCB97_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVCB97_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVCB97_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVCB97_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVCB97_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVCB97_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVCB97_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVCB97_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVCB97_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER 0x0158 +#define NVCB97_SET_REPORT_SEMAPHORE_PAYLOAD_LOWER_PAYLOAD_LOWER 31:0 + +#define NVCB97_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER 0x015c +#define NVCB97_SET_REPORT_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD_UPPER 31:0 + +#define NVCB97_SET_REPORT_SEMAPHORE_ADDRESS_LOWER 0x0160 +#define NVCB97_SET_REPORT_SEMAPHORE_ADDRESS_LOWER_LOWER 31:0 + +#define NVCB97_SET_REPORT_SEMAPHORE_ADDRESS_UPPER 0x0164 +#define NVCB97_SET_REPORT_SEMAPHORE_ADDRESS_UPPER_UPPER 24:0 + +#define NVCB97_REPORT_SEMAPHORE_EXECUTE 0x0168 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_OPERATION 1:0 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_OPERATION_RELEASE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_OPERATION_ACQUIRE 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_OPERATION_REPORT_ONLY 0x00000002 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_OPERATION_TRAP 0x00000003 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION 5:2 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_NONE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_VPC 0x00000004 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PIPELINE_LOCATION_ALL 0x0000000F +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE 6:6 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT 11:7 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_NONE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_VS_INVOCATIONS 0x00000005 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_TI_INVOCATIONS 0x0000001B +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_TS_INVOCATIONS 0x0000001D +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_GS_INVOCATIONS 0x00000007 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_SCG_CLOCKS 0x00000008 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS0 0x0000000A +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS1 0x0000000C +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS2 0x0000000E +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_ZCULL_STATS3 0x00000010 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_PS_INVOCATIONS 0x00000013 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REPORT_TIMESTAMP 0x00000014 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE 14:13 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_SUB_REPORT 17:15 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE 19:19 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_FALSE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_FLUSH_DISABLE_TRUE 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE 18:18 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE_FALSE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_ROP_FLUSH_DISABLE_TRUE 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE 20:20 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP 23:21 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_ADD 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MIN 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_MAX 0x00000002 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_INC 0x00000003 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_DEC 0x00000004 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_AND 0x00000005 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_OR 0x00000006 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_OP_RED_XOR 0x00000007 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT 25:24 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64 27:27 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_FALSE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_PAYLOAD_SIZE64_TRUE 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE 29:28 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_NONE 0x00000000 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_UNCONDITIONAL 0x00000001 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL 0x00000002 +#define NVCB97_REPORT_SEMAPHORE_EXECUTE_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x00000003 + +#define NVCB97_LINE_LENGTH_IN 0x0180 +#define NVCB97_LINE_LENGTH_IN_VALUE 31:0 + +#define NVCB97_LINE_COUNT 0x0184 +#define NVCB97_LINE_COUNT_VALUE 31:0 + +#define NVCB97_OFFSET_OUT_UPPER 0x0188 +#define NVCB97_OFFSET_OUT_UPPER_VALUE 24:0 + +#define NVCB97_OFFSET_OUT 0x018c +#define NVCB97_OFFSET_OUT_VALUE 31:0 + +#define NVCB97_PITCH_OUT 0x0190 +#define NVCB97_PITCH_OUT_VALUE 31:0 + +#define NVCB97_SET_DST_BLOCK_SIZE 0x0194 +#define NVCB97_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVCB97_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVCB97_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVCB97_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVCB97_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVCB97_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVCB97_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVCB97_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVCB97_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVCB97_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVCB97_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVCB97_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVCB97_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVCB97_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVCB97_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVCB97_SET_DST_WIDTH 0x0198 +#define NVCB97_SET_DST_WIDTH_V 31:0 + +#define NVCB97_SET_DST_HEIGHT 0x019c +#define NVCB97_SET_DST_HEIGHT_V 31:0 + +#define NVCB97_SET_DST_DEPTH 0x01a0 +#define NVCB97_SET_DST_DEPTH_V 31:0 + +#define NVCB97_SET_DST_LAYER 0x01a4 +#define NVCB97_SET_DST_LAYER_V 31:0 + +#define NVCB97_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVCB97_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVCB97_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVCB97_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVCB97_LAUNCH_DMA 0x01b0 +#define NVCB97_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVCB97_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVCB97_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVCB97_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVCB97_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVCB97_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVCB97_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVCB97_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVCB97_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVCB97_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVCB97_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVCB97_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVCB97_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVCB97_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVCB97_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVCB97_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVCB97_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVCB97_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVCB97_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVCB97_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVCB97_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVCB97_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVCB97_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVCB97_LOAD_INLINE_DATA 0x01b4 +#define NVCB97_LOAD_INLINE_DATA_V 31:0 + +#define NVCB97_SET_I2M_SEMAPHORE_A 0x01dc +#define NVCB97_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 24:0 + +#define NVCB97_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVCB97_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVCB97_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVCB97_SET_MME_SWITCH_STATE 0x01ec +#define NVCB97_SET_MME_SWITCH_STATE_VALID 0:0 +#define NVCB97_SET_MME_SWITCH_STATE_VALID_FALSE 0x00000000 +#define NVCB97_SET_MME_SWITCH_STATE_VALID_TRUE 0x00000001 +#define NVCB97_SET_MME_SWITCH_STATE_SAVE_MACRO 11:4 +#define NVCB97_SET_MME_SWITCH_STATE_RESTORE_MACRO 19:12 + +#define NVCB97_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVCB97_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVCB97_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVCB97_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVCB97_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVCB97_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVCB97_SET_I2M_SPARE_NOOP03 0x01fc +#define NVCB97_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVCB97_RUN_DS_NOW 0x0200 +#define NVCB97_RUN_DS_NOW_V 31:0 + +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS 0x0204 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD 4:0 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_INSTANTANEOUS 0x00000000 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16 0x00000001 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32 0x00000002 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__64 0x00000003 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__128 0x00000004 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__256 0x00000005 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__512 0x00000006 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1024 0x00000007 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2048 0x00000008 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4096 0x00000009 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__8192 0x0000000A +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__16384 0x0000000B +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__32768 0x0000000C +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__65536 0x0000000D +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__131072 0x0000000E +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__262144 0x0000000F +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__524288 0x00000010 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__1048576 0x00000011 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__2097152 0x00000012 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD__4194304 0x00000013 +#define NVCB97_SET_OPPORTUNISTIC_EARLY_Z_HYSTERESIS_ACCUMULATED_PRIM_AREA_THRESHOLD_LATEZ_ALWAYS 0x0000001F + +#define NVCB97_SET_GS_MODE 0x0208 +#define NVCB97_SET_GS_MODE_TYPE 0:0 +#define NVCB97_SET_GS_MODE_TYPE_ANY 0x00000000 +#define NVCB97_SET_GS_MODE_TYPE_FAST_GS 0x00000001 + +#define NVCB97_SET_ALIASED_LINE_WIDTH_ENABLE 0x020c +#define NVCB97_SET_ALIASED_LINE_WIDTH_ENABLE_V 0:0 +#define NVCB97_SET_ALIASED_LINE_WIDTH_ENABLE_V_FALSE 0x00000000 +#define NVCB97_SET_ALIASED_LINE_WIDTH_ENABLE_V_TRUE 0x00000001 + +#define NVCB97_SET_API_MANDATED_EARLY_Z 0x0210 +#define NVCB97_SET_API_MANDATED_EARLY_Z_ENABLE 0:0 +#define NVCB97_SET_API_MANDATED_EARLY_Z_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_API_MANDATED_EARLY_Z_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_GS_DM_FIFO 0x0214 +#define NVCB97_SET_GS_DM_FIFO_SIZE_RASTER_ON 12:0 +#define NVCB97_SET_GS_DM_FIFO_SIZE_RASTER_OFF 28:16 +#define NVCB97_SET_GS_DM_FIFO_SPILL_ENABLED 31:31 +#define NVCB97_SET_GS_DM_FIFO_SPILL_ENABLED_FALSE 0x00000000 +#define NVCB97_SET_GS_DM_FIFO_SPILL_ENABLED_TRUE 0x00000001 + +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS 0x0218 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY 5:4 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVCB97_INVALIDATE_SHADER_CACHES 0x021c +#define NVCB97_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVCB97_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVCB97_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVCB97_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVCB97_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVCB97_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVCB97_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVCB97_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVCB97_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVCB97_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVCB97_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVCB97_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVCB97_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVCB97_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVCB97_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVCB97_SET_INSTANCE_COUNT 0x0220 +#define NVCB97_SET_INSTANCE_COUNT_V 31:0 + +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_ENABLE 0x0224 +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE 0:0 +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_ENABLE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_GO_IDLE_TIMEOUT 0x022c +#define NVCB97_SET_GO_IDLE_TIMEOUT_V 31:0 + +#define NVCB97_SET_MME_VERSION 0x0234 +#define NVCB97_SET_MME_VERSION_MAJOR 7:0 + +#define NVCB97_SET_INDEX_BUFFER_SIZE_A 0x0238 +#define NVCB97_SET_INDEX_BUFFER_SIZE_A_UPPER 7:0 + +#define NVCB97_SET_INDEX_BUFFER_SIZE_B 0x023c +#define NVCB97_SET_INDEX_BUFFER_SIZE_B_LOWER 31:0 + +#define NVCB97_SET_ROOT_TABLE_VISIBILITY(i) (0x0240+(i)*4) +#define NVCB97_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP0_ENABLE 1:0 +#define NVCB97_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP1_ENABLE 5:4 +#define NVCB97_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP2_ENABLE 9:8 +#define NVCB97_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP3_ENABLE 13:12 +#define NVCB97_SET_ROOT_TABLE_VISIBILITY_BINDING_GROUP4_ENABLE 17:16 + +#define NVCB97_SET_DRAW_CONTROL_A 0x0260 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY 3:0 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_LINES 0x00000001 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_SET_DRAW_CONTROL_A_TOPOLOGY_PATCH 0x0000000E +#define NVCB97_SET_DRAW_CONTROL_A_PRIMITIVE_ID 4:4 +#define NVCB97_SET_DRAW_CONTROL_A_PRIMITIVE_ID_FIRST 0x00000000 +#define NVCB97_SET_DRAW_CONTROL_A_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVCB97_SET_DRAW_CONTROL_A_INSTANCE_ID 6:5 +#define NVCB97_SET_DRAW_CONTROL_A_INSTANCE_ID_FIRST 0x00000000 +#define NVCB97_SET_DRAW_CONTROL_A_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVCB97_SET_DRAW_CONTROL_A_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVCB97_SET_DRAW_CONTROL_A_SPLIT_MODE 8:7 +#define NVCB97_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVCB97_SET_DRAW_CONTROL_A_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVCB97_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVCB97_SET_DRAW_CONTROL_A_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVCB97_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE 9:9 +#define NVCB97_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_DRAW_CONTROL_A_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX 10:10 +#define NVCB97_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_FALSE 0x00000000 +#define NVCB97_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_VERTEX_INDEX_TRUE 0x00000001 +#define NVCB97_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX 11:11 +#define NVCB97_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_FALSE 0x00000000 +#define NVCB97_SET_DRAW_CONTROL_A_IGNORE_GLOBAL_BASE_INSTANCE_INDEX_TRUE 0x00000001 + +#define NVCB97_SET_DRAW_CONTROL_B 0x0264 +#define NVCB97_SET_DRAW_CONTROL_B_INSTANCE_COUNT 31:0 + +#define NVCB97_DRAW_INDEX_BUFFER_BEGIN_END_A 0x0268 +#define NVCB97_DRAW_INDEX_BUFFER_BEGIN_END_A_FIRST 31:0 + +#define NVCB97_DRAW_INDEX_BUFFER_BEGIN_END_B 0x026c +#define NVCB97_DRAW_INDEX_BUFFER_BEGIN_END_B_COUNT 31:0 + +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_A 0x0270 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_A_START 31:0 + +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_B 0x0274 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_B_COUNT 31:0 + +#define NVCB97_INVALIDATE_RASTER_CACHE_NO_WFI 0x027c +#define NVCB97_INVALIDATE_RASTER_CACHE_NO_WFI_V 0:0 + +#define NVCB97_SET_COLOR_RENDER_TO_ZETA_SURFACE 0x02b8 +#define NVCB97_SET_COLOR_RENDER_TO_ZETA_SURFACE_V 0:0 +#define NVCB97_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_FALSE 0x00000000 +#define NVCB97_SET_COLOR_RENDER_TO_ZETA_SURFACE_V_TRUE 0x00000001 + +#define NVCB97_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION 0x02bc +#define NVCB97_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V 0:0 +#define NVCB97_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_VISIBLE_PRIM_OPTIMIZATION_V_TRUE 0x00000001 + +#define NVCB97_INCREMENT_SYNC_POINT 0x02c8 +#define NVCB97_INCREMENT_SYNC_POINT_INDEX 11:0 +#define NVCB97_INCREMENT_SYNC_POINT_CLEAN_L2 16:16 +#define NVCB97_INCREMENT_SYNC_POINT_CLEAN_L2_FALSE 0x00000000 +#define NVCB97_INCREMENT_SYNC_POINT_CLEAN_L2_TRUE 0x00000001 +#define NVCB97_INCREMENT_SYNC_POINT_CONDITION 20:20 +#define NVCB97_INCREMENT_SYNC_POINT_CONDITION_STREAM_OUT_WRITES_DONE 0x00000000 +#define NVCB97_INCREMENT_SYNC_POINT_CONDITION_ROP_WRITES_DONE 0x00000001 + +#define NVCB97_SET_ROOT_TABLE_PREFETCH 0x02d0 +#define NVCB97_SET_ROOT_TABLE_PREFETCH_STAGE_ENABLES 5:0 + +#define NVCB97_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE 0x02d4 +#define NVCB97_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_V 0:0 + +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE 0x02d8 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH 3:0 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT 7:4 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH 11:8 +#define NVCB97_SET_SURFACE_CLIP_ID_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVCB97_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVCB97_SET_ALPHA_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 13:0 + +#define NVCB97_DECOMPRESS_SURFACE 0x02e0 +#define NVCB97_DECOMPRESS_SURFACE_MRT_SELECT 2:0 +#define NVCB97_DECOMPRESS_SURFACE_RT_ARRAY_INDEX 19:4 + +#define NVCB97_SET_ZCULL_ROP_BYPASS 0x02e4 +#define NVCB97_SET_ZCULL_ROP_BYPASS_ENABLE 0:0 +#define NVCB97_SET_ZCULL_ROP_BYPASS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_ROP_BYPASS_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_ROP_BYPASS_NO_STALL 4:4 +#define NVCB97_SET_ZCULL_ROP_BYPASS_NO_STALL_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_ROP_BYPASS_NO_STALL_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING 8:8 +#define NVCB97_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_ROP_BYPASS_CULL_EVERYTHING_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_ROP_BYPASS_THRESHOLD 15:12 + +#define NVCB97_SET_ZCULL_SUBREGION 0x02e8 +#define NVCB97_SET_ZCULL_SUBREGION_ENABLE 0:0 +#define NVCB97_SET_ZCULL_SUBREGION_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_SUBREGION_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_SUBREGION_NORMALIZED_ALIQUOTS 27:4 + +#define NVCB97_SET_RASTER_BOUNDING_BOX 0x02ec +#define NVCB97_SET_RASTER_BOUNDING_BOX_MODE 0:0 +#define NVCB97_SET_RASTER_BOUNDING_BOX_MODE_BOUNDING_BOX 0x00000000 +#define NVCB97_SET_RASTER_BOUNDING_BOX_MODE_FULL_VIEWPORT 0x00000001 +#define NVCB97_SET_RASTER_BOUNDING_BOX_PAD 11:4 + +#define NVCB97_PEER_SEMAPHORE_RELEASE 0x02f0 +#define NVCB97_PEER_SEMAPHORE_RELEASE_V 31:0 + +#define NVCB97_SET_ITERATED_BLEND_OPTIMIZATION 0x02f4 +#define NVCB97_SET_ITERATED_BLEND_OPTIMIZATION_NOOP 1:0 +#define NVCB97_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_NEVER 0x00000000 +#define NVCB97_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0000 0x00000001 +#define NVCB97_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_ALPHA_0 0x00000002 +#define NVCB97_SET_ITERATED_BLEND_OPTIMIZATION_NOOP_SOURCE_RGBA_0001 0x00000003 + +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION 0x02f8 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_SUBREGION_ID 7:0 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_ALIQUOTS 23:8 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT 27:24 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16X2_4X4 0x00000000 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X16_4X4 0x00000001 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X2 0x00000002 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_2X4 0x00000003 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X8_4X4 0x00000004 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_4X2 0x00000005 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_8X8_2X4 0x00000006 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_16X16_4X8 0x00000007 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_2X2 0x00000008 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_4X2 0x00000009 +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_16X8_2X4 0x0000000A +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_ZS_8X8_2X2 0x0000000B +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_Z_4X8_1X1 0x0000000C +#define NVCB97_SET_ZCULL_SUBREGION_ALLOCATION_FORMAT_NONE 0x0000000F + +#define NVCB97_ASSIGN_ZCULL_SUBREGIONS 0x02fc +#define NVCB97_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM 1:0 +#define NVCB97_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Static 0x00000000 +#define NVCB97_ASSIGN_ZCULL_SUBREGIONS_ALGORITHM_Adaptive 0x00000001 + +#define NVCB97_SET_PS_OUTPUT_SAMPLE_MASK_USAGE 0x0300 +#define NVCB97_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE 0:0 +#define NVCB97_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE 1:1 +#define NVCB97_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVCB97_SET_PS_OUTPUT_SAMPLE_MASK_USAGE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 + +#define NVCB97_DRAW_ZERO_INDEX 0x0304 +#define NVCB97_DRAW_ZERO_INDEX_COUNT 31:0 + +#define NVCB97_SET_L1_CONFIGURATION 0x0308 +#define NVCB97_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NVCB97_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVCB97_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NVCB97_SET_RENDER_ENABLE_CONTROL 0x030c +#define NVCB97_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NVCB97_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NVCB97_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NVCB97_SET_SPA_VERSION 0x0310 +#define NVCB97_SET_SPA_VERSION_MINOR 7:0 +#define NVCB97_SET_SPA_VERSION_MAJOR 15:8 + +#define NVCB97_SET_TIMESLICE_BATCH_LIMIT 0x0314 +#define NVCB97_SET_TIMESLICE_BATCH_LIMIT_BATCH_LIMIT 15:0 + +#define NVCB97_SET_SNAP_GRID_LINE 0x0318 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVCB97_SET_SNAP_GRID_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVCB97_SET_SNAP_GRID_LINE_ROUNDING_MODE 8:8 +#define NVCB97_SET_SNAP_GRID_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVCB97_SET_SNAP_GRID_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVCB97_SET_SNAP_GRID_NON_LINE 0x031c +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL 3:0 +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__2X2 0x00000001 +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__4X4 0x00000002 +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__8X8 0x00000003 +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__16X16 0x00000004 +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__32X32 0x00000005 +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__64X64 0x00000006 +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__128X128 0x00000007 +#define NVCB97_SET_SNAP_GRID_NON_LINE_LOCATIONS_PER_PIXEL__256X256 0x00000008 +#define NVCB97_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE 8:8 +#define NVCB97_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_RTNE 0x00000000 +#define NVCB97_SET_SNAP_GRID_NON_LINE_ROUNDING_MODE_TESLA 0x00000001 + +#define NVCB97_SET_TESSELLATION_PARAMETERS 0x0320 +#define NVCB97_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE 1:0 +#define NVCB97_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_ISOLINE 0x00000000 +#define NVCB97_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_TRIANGLE 0x00000001 +#define NVCB97_SET_TESSELLATION_PARAMETERS_DOMAIN_TYPE_QUAD 0x00000002 +#define NVCB97_SET_TESSELLATION_PARAMETERS_SPACING 5:4 +#define NVCB97_SET_TESSELLATION_PARAMETERS_SPACING_INTEGER 0x00000000 +#define NVCB97_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_ODD 0x00000001 +#define NVCB97_SET_TESSELLATION_PARAMETERS_SPACING_FRACTIONAL_EVEN 0x00000002 +#define NVCB97_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES 9:8 +#define NVCB97_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_POINTS 0x00000000 +#define NVCB97_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_LINES 0x00000001 +#define NVCB97_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CW 0x00000002 +#define NVCB97_SET_TESSELLATION_PARAMETERS_OUTPUT_PRIMITIVES_TRIANGLES_CCW 0x00000003 + +#define NVCB97_SET_TESSELLATION_LOD_U0_OR_DENSITY 0x0324 +#define NVCB97_SET_TESSELLATION_LOD_U0_OR_DENSITY_V 31:0 + +#define NVCB97_SET_TESSELLATION_LOD_V0_OR_DETAIL 0x0328 +#define NVCB97_SET_TESSELLATION_LOD_V0_OR_DETAIL_V 31:0 + +#define NVCB97_SET_TESSELLATION_LOD_U1_OR_W0 0x032c +#define NVCB97_SET_TESSELLATION_LOD_U1_OR_W0_V 31:0 + +#define NVCB97_SET_TESSELLATION_LOD_V1 0x0330 +#define NVCB97_SET_TESSELLATION_LOD_V1_V 31:0 + +#define NVCB97_SET_TG_LOD_INTERIOR_U 0x0334 +#define NVCB97_SET_TG_LOD_INTERIOR_U_V 31:0 + +#define NVCB97_SET_TG_LOD_INTERIOR_V 0x0338 +#define NVCB97_SET_TG_LOD_INTERIOR_V_V 31:0 + +#define NVCB97_RESERVED_TG07 0x033c +#define NVCB97_RESERVED_TG07_V 0:0 + +#define NVCB97_RESERVED_TG08 0x0340 +#define NVCB97_RESERVED_TG08_V 0:0 + +#define NVCB97_RESERVED_TG09 0x0344 +#define NVCB97_RESERVED_TG09_V 0:0 + +#define NVCB97_RESERVED_TG10 0x0348 +#define NVCB97_RESERVED_TG10_V 0:0 + +#define NVCB97_RESERVED_TG11 0x034c +#define NVCB97_RESERVED_TG11_V 0:0 + +#define NVCB97_RESERVED_TG12 0x0350 +#define NVCB97_RESERVED_TG12_V 0:0 + +#define NVCB97_RESERVED_TG13 0x0354 +#define NVCB97_RESERVED_TG13_V 0:0 + +#define NVCB97_RESERVED_TG14 0x0358 +#define NVCB97_RESERVED_TG14_V 0:0 + +#define NVCB97_RESERVED_TG15 0x035c +#define NVCB97_RESERVED_TG15_V 0:0 + +#define NVCB97_SET_SUBTILING_PERF_KNOB_A 0x0360 +#define NVCB97_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_REGISTER_FILE_PER_SUBTILE 7:0 +#define NVCB97_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_PIXEL_OUTPUT_BUFFER_PER_SUBTILE 15:8 +#define NVCB97_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_SPM_TRIANGLE_RAM_PER_SUBTILE 23:16 +#define NVCB97_SET_SUBTILING_PERF_KNOB_A_FRACTION_OF_MAX_QUADS_PER_SUBTILE 31:24 + +#define NVCB97_SET_SUBTILING_PERF_KNOB_B 0x0364 +#define NVCB97_SET_SUBTILING_PERF_KNOB_B_FRACTION_OF_MAX_PRIMITIVES_PER_SUBTILE 7:0 + +#define NVCB97_SET_SUBTILING_PERF_KNOB_C 0x0368 +#define NVCB97_SET_SUBTILING_PERF_KNOB_C_RESERVED 0:0 + +#define NVCB97_SET_ZCULL_SUBREGION_TO_REPORT 0x036c +#define NVCB97_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE 0:0 +#define NVCB97_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_SUBREGION_TO_REPORT_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_SUBREGION_TO_REPORT_SUBREGION_ID 11:4 + +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE 0x0370 +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE 0:0 +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE 6:4 +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST 0x00000000 +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_NO_ACCEPT 0x00000001 +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_DEPTH_TEST_LATE_Z 0x00000002 +#define NVCB97_SET_ZCULL_SUBREGION_REPORT_TYPE_TYPE_STENCIL_TEST 0x00000003 + +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD 0x0374 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE 0:0 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE 4:4 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_IN_TIMESLICED_MODE_TRUE 0x00000001 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE 8:8 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_FALSE 0x00000000 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_UNPARTITIONED_MODE_TRUE 0x00000001 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE 9:9 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_FALSE 0x00000000 +#define NVCB97_SET_BALANCED_PRIMITIVE_WORKLOAD_BY_PES_IN_TIMESLICED_MODE_TRUE 0x00000001 + +#define NVCB97_SET_MAX_PATCHES_PER_BATCH 0x0378 +#define NVCB97_SET_MAX_PATCHES_PER_BATCH_V 5:0 + +#define NVCB97_SET_RASTER_ENABLE 0x037c +#define NVCB97_SET_RASTER_ENABLE_V 0:0 +#define NVCB97_SET_RASTER_ENABLE_V_FALSE 0x00000000 +#define NVCB97_SET_RASTER_ENABLE_V_TRUE 0x00000001 + +#define NVCB97_SET_STREAM_OUT_BUFFER_ENABLE(j) (0x0380+(j)*32) +#define NVCB97_SET_STREAM_OUT_BUFFER_ENABLE_V 0:0 +#define NVCB97_SET_STREAM_OUT_BUFFER_ENABLE_V_FALSE 0x00000000 +#define NVCB97_SET_STREAM_OUT_BUFFER_ENABLE_V_TRUE 0x00000001 + +#define NVCB97_SET_STREAM_OUT_BUFFER_ADDRESS_A(j) (0x0384+(j)*32) +#define NVCB97_SET_STREAM_OUT_BUFFER_ADDRESS_A_UPPER 7:0 + +#define NVCB97_SET_STREAM_OUT_BUFFER_ADDRESS_B(j) (0x0388+(j)*32) +#define NVCB97_SET_STREAM_OUT_BUFFER_ADDRESS_B_LOWER 31:0 + +#define NVCB97_SET_STREAM_OUT_BUFFER_SIZE(j) (0x038c+(j)*32) +#define NVCB97_SET_STREAM_OUT_BUFFER_SIZE_BYTES 31:0 + +#define NVCB97_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(j) (0x0390+(j)*32) +#define NVCB97_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER_START_OFFSET 31:0 + +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_SCALE_A(j) (0x0400+(j)*16) +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_SCALE_A_V 31:0 + +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_SCALE_B(j) (0x0404+(j)*16) +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_SCALE_B_V 31:0 + +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_RESERVED_A(j) (0x0408+(j)*16) +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_RESERVED_A_V 31:0 + +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_RESERVED_B(j) (0x040c+(j)*16) +#define NVCB97_SET_POSITION_W_SCALED_OFFSET_RESERVED_B_V 31:0 + +#define NVCB97_SET_Z_ROP_SLICE_MAP 0x0500 +#define NVCB97_SET_Z_ROP_SLICE_MAP_VIRTUAL_ADDRESS_MASK 31:0 + +#define NVCB97_SET_ROOT_TABLE_SELECTOR 0x0504 +#define NVCB97_SET_ROOT_TABLE_SELECTOR_ROOT_TABLE 2:0 +#define NVCB97_SET_ROOT_TABLE_SELECTOR_OFFSET 15:8 + +#define NVCB97_LOAD_ROOT_TABLE 0x0508 +#define NVCB97_LOAD_ROOT_TABLE_V 31:0 + +#define NVCB97_SET_MME_MEM_ADDRESS_A 0x0550 +#define NVCB97_SET_MME_MEM_ADDRESS_A_UPPER 24:0 + +#define NVCB97_SET_MME_MEM_ADDRESS_B 0x0554 +#define NVCB97_SET_MME_MEM_ADDRESS_B_LOWER 31:0 + +#define NVCB97_SET_MME_DATA_RAM_ADDRESS 0x0558 +#define NVCB97_SET_MME_DATA_RAM_ADDRESS_WORD 31:0 + +#define NVCB97_MME_DMA_READ 0x055c +#define NVCB97_MME_DMA_READ_LENGTH 31:0 + +#define NVCB97_MME_DMA_READ_FIFOED 0x0560 +#define NVCB97_MME_DMA_READ_FIFOED_LENGTH 31:0 + +#define NVCB97_MME_DMA_WRITE 0x0564 +#define NVCB97_MME_DMA_WRITE_LENGTH 31:0 + +#define NVCB97_MME_DMA_REDUCTION 0x0568 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP 2:0 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP_RED_ADD 0x00000000 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP_RED_MIN 0x00000001 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP_RED_MAX 0x00000002 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP_RED_INC 0x00000003 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP_RED_DEC 0x00000004 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP_RED_AND 0x00000005 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP_RED_OR 0x00000006 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_OP_RED_XOR 0x00000007 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_FORMAT 5:4 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_FORMAT_UNSIGNED 0x00000000 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_FORMAT_SIGNED 0x00000001 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_SIZE 8:8 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_SIZE_FOUR_BYTES 0x00000000 +#define NVCB97_MME_DMA_REDUCTION_REDUCTION_SIZE_EIGHT_BYTES 0x00000001 + +#define NVCB97_MME_DMA_SYSMEMBAR 0x056c +#define NVCB97_MME_DMA_SYSMEMBAR_V 0:0 + +#define NVCB97_MME_DMA_SYNC 0x0570 +#define NVCB97_MME_DMA_SYNC_VALUE 31:0 + +#define NVCB97_SET_MME_DATA_FIFO_CONFIG 0x0574 +#define NVCB97_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE 2:0 +#define NVCB97_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_0KB 0x00000000 +#define NVCB97_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_4KB 0x00000001 +#define NVCB97_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_8KB 0x00000002 +#define NVCB97_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_12KB 0x00000003 +#define NVCB97_SET_MME_DATA_FIFO_CONFIG_FIFO_SIZE_SIZE_16KB 0x00000004 + +#define NVCB97_SET_VERTEX_STREAM_SIZE_A(j) (0x0600+(j)*8) +#define NVCB97_SET_VERTEX_STREAM_SIZE_A_UPPER 7:0 + +#define NVCB97_SET_VERTEX_STREAM_SIZE_B(j) (0x0604+(j)*8) +#define NVCB97_SET_VERTEX_STREAM_SIZE_B_LOWER 31:0 + +#define NVCB97_SET_STREAM_OUT_CONTROL_STREAM(j) (0x0700+(j)*16) +#define NVCB97_SET_STREAM_OUT_CONTROL_STREAM_SELECT 1:0 + +#define NVCB97_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT(j) (0x0704+(j)*16) +#define NVCB97_SET_STREAM_OUT_CONTROL_COMPONENT_COUNT_MAX 7:0 + +#define NVCB97_SET_STREAM_OUT_CONTROL_STRIDE(j) (0x0708+(j)*16) +#define NVCB97_SET_STREAM_OUT_CONTROL_STRIDE_BYTES 31:0 + +#define NVCB97_SET_RASTER_INPUT 0x0740 +#define NVCB97_SET_RASTER_INPUT_STREAM_SELECT 1:0 + +#define NVCB97_SET_STREAM_OUTPUT 0x0744 +#define NVCB97_SET_STREAM_OUTPUT_ENABLE 0:0 +#define NVCB97_SET_STREAM_OUTPUT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STREAM_OUTPUT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE 0x0748 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE 0:0 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_TOPOLOGY_CHANGE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_HYBRID_ANTI_ALIAS_CONTROL 0x0754 +#define NVCB97_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES 3:0 +#define NVCB97_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID 4:4 +#define NVCB97_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_FRAGMENT 0x00000000 +#define NVCB97_SET_HYBRID_ANTI_ALIAS_CONTROL_CENTROID_PER_PASS 0x00000001 +#define NVCB97_SET_HYBRID_ANTI_ALIAS_CONTROL_PASSES_EXTENDED 5:5 + +#define NVCB97_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVCB97_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVCB97_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVCB97_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVCB97_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVCB97_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVCB97_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NVCB97_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 6:0 + +#define NVCB97_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NVCB97_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NVCB97_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NVCB97_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NVCB97_SET_COLOR_ZERO_BANDWIDTH_CLEAR 0x07a4 +#define NVCB97_SET_COLOR_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVCB97_SET_Z_ZERO_BANDWIDTH_CLEAR 0x07a8 +#define NVCB97_SET_Z_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVCB97_SET_TEXTURE_HEADER_VERSION 0x07ac +#define NVCB97_SET_TEXTURE_HEADER_VERSION_MAJOR 7:0 + +#define NVCB97_SET_STENCIL_ZERO_BANDWIDTH_CLEAR 0x07b0 +#define NVCB97_SET_STENCIL_ZERO_BANDWIDTH_CLEAR_SLOT_DISABLE_MASK 14:0 + +#define NVCB97_SET_ZCULL_REGION_SIZE_A 0x07c0 +#define NVCB97_SET_ZCULL_REGION_SIZE_A_WIDTH 15:0 + +#define NVCB97_SET_ZCULL_REGION_SIZE_B 0x07c4 +#define NVCB97_SET_ZCULL_REGION_SIZE_B_HEIGHT 15:0 + +#define NVCB97_SET_ZCULL_REGION_SIZE_C 0x07c8 +#define NVCB97_SET_ZCULL_REGION_SIZE_C_DEPTH 15:0 + +#define NVCB97_SET_ZCULL_REGION_PIXEL_OFFSET_C 0x07cc +#define NVCB97_SET_ZCULL_REGION_PIXEL_OFFSET_C_DEPTH 15:0 + +#define NVCB97_SET_CULL_BEFORE_FETCH 0x07dc +#define NVCB97_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE 0:0 +#define NVCB97_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_FALSE 0x00000000 +#define NVCB97_SET_CULL_BEFORE_FETCH_FETCH_STREAMS_ONCE_TRUE 0x00000001 + +#define NVCB97_SET_ZCULL_REGION_LOCATION 0x07e0 +#define NVCB97_SET_ZCULL_REGION_LOCATION_START_ALIQUOT 15:0 +#define NVCB97_SET_ZCULL_REGION_LOCATION_ALIQUOT_COUNT 31:16 + +#define NVCB97_SET_ZCULL_REGION_ALIQUOTS 0x07e4 +#define NVCB97_SET_ZCULL_REGION_ALIQUOTS_PER_LAYER 15:0 + +#define NVCB97_SET_ZCULL_STORAGE_A 0x07e8 +#define NVCB97_SET_ZCULL_STORAGE_A_ADDRESS_UPPER 7:0 + +#define NVCB97_SET_ZCULL_STORAGE_B 0x07ec +#define NVCB97_SET_ZCULL_STORAGE_B_ADDRESS_LOWER 31:0 + +#define NVCB97_SET_ZCULL_STORAGE_C 0x07f0 +#define NVCB97_SET_ZCULL_STORAGE_C_LIMIT_ADDRESS_UPPER 7:0 + +#define NVCB97_SET_ZCULL_STORAGE_D 0x07f4 +#define NVCB97_SET_ZCULL_STORAGE_D_LIMIT_ADDRESS_LOWER 31:0 + +#define NVCB97_SET_ZT_READ_ONLY 0x07f8 +#define NVCB97_SET_ZT_READ_ONLY_ENABLE_Z 0:0 +#define NVCB97_SET_ZT_READ_ONLY_ENABLE_Z_FALSE 0x00000000 +#define NVCB97_SET_ZT_READ_ONLY_ENABLE_Z_TRUE 0x00000001 +#define NVCB97_SET_ZT_READ_ONLY_ENABLE_STENCIL 4:4 +#define NVCB97_SET_ZT_READ_ONLY_ENABLE_STENCIL_FALSE 0x00000000 +#define NVCB97_SET_ZT_READ_ONLY_ENABLE_STENCIL_TRUE 0x00000001 + +#define NVCB97_THROTTLE_SM 0x07fc +#define NVCB97_THROTTLE_SM_MULTIPLY_ADD 0:0 +#define NVCB97_THROTTLE_SM_MULTIPLY_ADD_FALSE 0x00000000 +#define NVCB97_THROTTLE_SM_MULTIPLY_ADD_TRUE 0x00000001 + +#define NVCB97_SET_COLOR_TARGET_A(j) (0x0800+(j)*64) +#define NVCB97_SET_COLOR_TARGET_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_COLOR_TARGET_B(j) (0x0804+(j)*64) +#define NVCB97_SET_COLOR_TARGET_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_COLOR_TARGET_WIDTH(j) (0x0808+(j)*64) +#define NVCB97_SET_COLOR_TARGET_WIDTH_V 27:0 + +#define NVCB97_SET_COLOR_TARGET_HEIGHT(j) (0x080c+(j)*64) +#define NVCB97_SET_COLOR_TARGET_HEIGHT_V 16:0 + +#define NVCB97_SET_COLOR_TARGET_FORMAT(j) (0x0810+(j)*64) +#define NVCB97_SET_COLOR_TARGET_FORMAT_V 7:0 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_DISABLED 0x00000000 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_AS32 0x000000C1 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_AU32 0x000000C2 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RS32_GS32_BS32_X32 0x000000C4 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RU32_GU32_BU32_X32 0x000000C5 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RS16_GS16_BS16_AS16 0x000000C8 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RU16_GU16_BU16_AU16 0x000000C9 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF32_GF32 0x000000CB +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RS32_GS32 0x000000CC +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RU32_GU32 0x000000CD +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A8R8G8B8 0x000000CF +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A2B10G10R10 0x000000D1 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_AU2BU10GU10RU10 0x000000D2 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A8B8G8R8 0x000000D5 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_AS8BS8GS8RS8 0x000000D8 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_AU8BU8GU8RU8 0x000000D9 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_R16_G16 0x000000DA +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RN16_GN16 0x000000DB +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RS16_GS16 0x000000DC +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RU16_GU16 0x000000DD +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF16_GF16 0x000000DE +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A2R10G10B10 0x000000DF +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RS32 0x000000E3 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RU32 0x000000E4 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF32 0x000000E5 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_X8R8G8B8 0x000000E6 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_R5G6B5 0x000000E8 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A1R5G5B5 0x000000E9 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_G8R8 0x000000EA +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_GN8RN8 0x000000EB +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_GS8RS8 0x000000EC +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_GU8RU8 0x000000ED +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_R16 0x000000EE +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RN16 0x000000EF +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RS16 0x000000F0 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RU16 0x000000F1 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF16 0x000000F2 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_R8 0x000000F3 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RN8 0x000000F4 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RS8 0x000000F5 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RU8 0x000000F6 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A8 0x000000F7 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_X1R5G5B5 0x000000F8 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_X8B8G8R8 0x000000F9 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_Z1R5G5B5 0x000000FB +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_O1R5G5B5 0x000000FC +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_Z8R8G8B8 0x000000FD +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_O8R8G8B8 0x000000FE +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_R32 0x000000FF +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A16 0x00000040 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_AF16 0x00000041 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_AF32 0x00000042 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_A8R8 0x00000043 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_R16_A16 0x00000044 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF16_AF16 0x00000045 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_RF32_AF32 0x00000046 +#define NVCB97_SET_COLOR_TARGET_FORMAT_V_B8G8R8A8 0x00000047 + +#define NVCB97_SET_COLOR_TARGET_MEMORY(j) (0x0814+(j)*64) +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH 3:0 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT 7:4 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH 11:8 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVCB97_SET_COLOR_TARGET_MEMORY_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_SET_COLOR_TARGET_MEMORY_LAYOUT 12:12 +#define NVCB97_SET_COLOR_TARGET_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVCB97_SET_COLOR_TARGET_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVCB97_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL 16:16 +#define NVCB97_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVCB97_SET_COLOR_TARGET_MEMORY_THIRD_DIMENSION_CONTROL_THIRD_DIMENSION_DEFINES_DEPTH_SIZE 0x00000001 + +#define NVCB97_SET_COLOR_TARGET_THIRD_DIMENSION(j) (0x0818+(j)*64) +#define NVCB97_SET_COLOR_TARGET_THIRD_DIMENSION_V 27:0 + +#define NVCB97_SET_COLOR_TARGET_ARRAY_PITCH(j) (0x081c+(j)*64) +#define NVCB97_SET_COLOR_TARGET_ARRAY_PITCH_V 31:0 + +#define NVCB97_SET_COLOR_TARGET_LAYER(j) (0x0820+(j)*64) +#define NVCB97_SET_COLOR_TARGET_LAYER_OFFSET 15:0 + +#define NVCB97_SET_COLOR_TARGET_C_ROP_SLICE_MAP(j) (0x0824+(j)*64) +#define NVCB97_SET_COLOR_TARGET_C_ROP_SLICE_MAP_VIRTUAL_ADDRESS_MASK 31:0 + +#define NVCB97_SET_VIEWPORT_SCALE_X(j) (0x0a00+(j)*32) +#define NVCB97_SET_VIEWPORT_SCALE_X_V 31:0 + +#define NVCB97_SET_VIEWPORT_SCALE_Y(j) (0x0a04+(j)*32) +#define NVCB97_SET_VIEWPORT_SCALE_Y_V 31:0 + +#define NVCB97_SET_VIEWPORT_SCALE_Z(j) (0x0a08+(j)*32) +#define NVCB97_SET_VIEWPORT_SCALE_Z_V 31:0 + +#define NVCB97_SET_VIEWPORT_OFFSET_X(j) (0x0a0c+(j)*32) +#define NVCB97_SET_VIEWPORT_OFFSET_X_V 31:0 + +#define NVCB97_SET_VIEWPORT_OFFSET_Y(j) (0x0a10+(j)*32) +#define NVCB97_SET_VIEWPORT_OFFSET_Y_V 31:0 + +#define NVCB97_SET_VIEWPORT_OFFSET_Z(j) (0x0a14+(j)*32) +#define NVCB97_SET_VIEWPORT_OFFSET_Z_V 31:0 + +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE(j) (0x0a18+(j)*32) +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X 2:0 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_X 0x00000000 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_X 0x00000001 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Y 0x00000002 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Y 0x00000003 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_Z 0x00000004 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_Z 0x00000005 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X_POS_W 0x00000006 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_X_NEG_W 0x00000007 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y 6:4 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_X 0x00000000 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_X 0x00000001 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Y 0x00000002 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Y 0x00000003 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_Z 0x00000004 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_Z 0x00000005 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_POS_W 0x00000006 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Y_NEG_W 0x00000007 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z 10:8 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_X 0x00000000 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_X 0x00000001 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Y 0x00000002 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Y 0x00000003 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_Z 0x00000004 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_Z 0x00000005 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_POS_W 0x00000006 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_Z_NEG_W 0x00000007 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W 14:12 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_X 0x00000000 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_X 0x00000001 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Y 0x00000002 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Y 0x00000003 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_Z 0x00000004 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_Z 0x00000005 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W_POS_W 0x00000006 +#define NVCB97_SET_VIEWPORT_COORDINATE_SWIZZLE_W_NEG_W 0x00000007 + +#define NVCB97_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION(j) (0x0a1c+(j)*32) +#define NVCB97_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_X_BITS 4:0 +#define NVCB97_SET_VIEWPORT_INCREASE_SNAP_GRID_PRECISION_Y_BITS 12:8 + +#define NVCB97_SET_VIEWPORT_CLIP_HORIZONTAL(j) (0x0c00+(j)*16) +#define NVCB97_SET_VIEWPORT_CLIP_HORIZONTAL_X0 15:0 +#define NVCB97_SET_VIEWPORT_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVCB97_SET_VIEWPORT_CLIP_VERTICAL(j) (0x0c04+(j)*16) +#define NVCB97_SET_VIEWPORT_CLIP_VERTICAL_Y0 15:0 +#define NVCB97_SET_VIEWPORT_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVCB97_SET_VIEWPORT_CLIP_MIN_Z(j) (0x0c08+(j)*16) +#define NVCB97_SET_VIEWPORT_CLIP_MIN_Z_V 31:0 + +#define NVCB97_SET_VIEWPORT_CLIP_MAX_Z(j) (0x0c0c+(j)*16) +#define NVCB97_SET_VIEWPORT_CLIP_MAX_Z_V 31:0 + +#define NVCB97_SET_WINDOW_CLIP_HORIZONTAL(j) (0x0d00+(j)*8) +#define NVCB97_SET_WINDOW_CLIP_HORIZONTAL_XMIN 15:0 +#define NVCB97_SET_WINDOW_CLIP_HORIZONTAL_XMAX 31:16 + +#define NVCB97_SET_WINDOW_CLIP_VERTICAL(j) (0x0d04+(j)*8) +#define NVCB97_SET_WINDOW_CLIP_VERTICAL_YMIN 15:0 +#define NVCB97_SET_WINDOW_CLIP_VERTICAL_YMAX 31:16 + +#define NVCB97_SET_CLIP_ID_EXTENT_X(j) (0x0d40+(j)*8) +#define NVCB97_SET_CLIP_ID_EXTENT_X_MINX 15:0 +#define NVCB97_SET_CLIP_ID_EXTENT_X_WIDTH 31:16 + +#define NVCB97_SET_CLIP_ID_EXTENT_Y(j) (0x0d44+(j)*8) +#define NVCB97_SET_CLIP_ID_EXTENT_Y_MINY 15:0 +#define NVCB97_SET_CLIP_ID_EXTENT_Y_HEIGHT 31:16 + +#define NVCB97_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK 0x0d60 +#define NVCB97_SET_MAX_STREAM_OUTPUT_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V 3:0 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__0 0x00000000 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__1 0x00000001 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__2 0x00000002 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__4 0x00000003 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__8 0x00000004 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__16 0x00000005 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__32 0x00000006 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__64 0x00000007 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V__128 0x00000008 +#define NVCB97_SET_API_VISIBLE_CALL_LIMIT_V_NO_CHECK 0x0000000F + +#define NVCB97_SET_STATISTICS_COUNTER 0x0d68 +#define NVCB97_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE 0:0 +#define NVCB97_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_DA_VERTICES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE 1:1 +#define NVCB97_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_DA_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE 2:2 +#define NVCB97_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_VS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE 3:3 +#define NVCB97_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_GS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE 4:4 +#define NVCB97_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_GS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE 5:5 +#define NVCB97_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE 6:6 +#define NVCB97_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_STREAMING_PRIMITIVES_NEEDED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE 7:7 +#define NVCB97_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_CLIPPER_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE 8:8 +#define NVCB97_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_CLIPPER_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE 9:9 +#define NVCB97_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_PS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE 11:11 +#define NVCB97_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_TI_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE 12:12 +#define NVCB97_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_TS_INVOCATIONS_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE 13:13 +#define NVCB97_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_TS_PRIMITIVES_GENERATED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE 14:14 +#define NVCB97_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_TOTAL_STREAMING_PRIMITIVES_NEEDED_SUCCEEDED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE 10:10 +#define NVCB97_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_VTG_PRIMITIVES_OUT_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE 15:15 +#define NVCB97_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_ALPHA_BETA_CLOCKS_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE 16:16 +#define NVCB97_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STATISTICS_COUNTER_SCG_CLOCKS_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_CLEAR_RECT_HORIZONTAL 0x0d6c +#define NVCB97_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVCB97_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVCB97_SET_CLEAR_RECT_VERTICAL 0x0d70 +#define NVCB97_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVCB97_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVCB97_SET_VERTEX_ARRAY_START 0x0d74 +#define NVCB97_SET_VERTEX_ARRAY_START_V 31:0 + +#define NVCB97_DRAW_VERTEX_ARRAY 0x0d78 +#define NVCB97_DRAW_VERTEX_ARRAY_COUNT 31:0 + +#define NVCB97_SET_VIEWPORT_Z_CLIP 0x0d7c +#define NVCB97_SET_VIEWPORT_Z_CLIP_RANGE 0:0 +#define NVCB97_SET_VIEWPORT_Z_CLIP_RANGE_NEGATIVE_W_TO_POSITIVE_W 0x00000000 +#define NVCB97_SET_VIEWPORT_Z_CLIP_RANGE_ZERO_TO_POSITIVE_W 0x00000001 + +#define NVCB97_SET_COLOR_CLEAR_VALUE(i) (0x0d80+(i)*4) +#define NVCB97_SET_COLOR_CLEAR_VALUE_V 31:0 + +#define NVCB97_SET_Z_CLEAR_VALUE 0x0d90 +#define NVCB97_SET_Z_CLEAR_VALUE_V 31:0 + +#define NVCB97_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVCB97_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVCB97_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVCB97_FORCE_TRANSITION_TO_BETA 0x0d98 +#define NVCB97_FORCE_TRANSITION_TO_BETA_V 0:0 + +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_ENABLE 0x0d9c +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V 0:0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_FALSE 0x00000000 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_ENABLE_V_TRUE 0x00000001 + +#define NVCB97_SET_STENCIL_CLEAR_VALUE 0x0da0 +#define NVCB97_SET_STENCIL_CLEAR_VALUE_V 7:0 + +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI 0x0da4 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVCB97_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVCB97_SET_ZCULL_SERIALIZATION 0x0da8 +#define NVCB97_SET_ZCULL_SERIALIZATION_ENABLE 0:0 +#define NVCB97_SET_ZCULL_SERIALIZATION_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_SERIALIZATION_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_SERIALIZATION_APPLIED 5:4 +#define NVCB97_SET_ZCULL_SERIALIZATION_APPLIED_ALWAYS 0x00000000 +#define NVCB97_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z 0x00000001 +#define NVCB97_SET_ZCULL_SERIALIZATION_APPLIED_OUT_OF_GAMUT_Z 0x00000002 +#define NVCB97_SET_ZCULL_SERIALIZATION_APPLIED_LATE_Z_OR_OUT_OF_GAMUT_Z 0x00000003 + +#define NVCB97_SET_FRONT_POLYGON_MODE 0x0dac +#define NVCB97_SET_FRONT_POLYGON_MODE_V 31:0 +#define NVCB97_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 +#define NVCB97_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 +#define NVCB97_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVCB97_SET_BACK_POLYGON_MODE 0x0db0 +#define NVCB97_SET_BACK_POLYGON_MODE_V 31:0 +#define NVCB97_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 +#define NVCB97_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 +#define NVCB97_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 + +#define NVCB97_SET_POLY_SMOOTH 0x0db4 +#define NVCB97_SET_POLY_SMOOTH_ENABLE 0:0 +#define NVCB97_SET_POLY_SMOOTH_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_POLY_SMOOTH_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_ZCULL_DIR_FORMAT 0x0dbc +#define NVCB97_SET_ZCULL_DIR_FORMAT_ZDIR 15:0 +#define NVCB97_SET_ZCULL_DIR_FORMAT_ZDIR_LESS 0x00000000 +#define NVCB97_SET_ZCULL_DIR_FORMAT_ZDIR_GREATER 0x00000001 +#define NVCB97_SET_ZCULL_DIR_FORMAT_ZFORMAT 31:16 +#define NVCB97_SET_ZCULL_DIR_FORMAT_ZFORMAT_MSB 0x00000000 +#define NVCB97_SET_ZCULL_DIR_FORMAT_ZFORMAT_FP 0x00000001 +#define NVCB97_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZTRICK 0x00000002 +#define NVCB97_SET_ZCULL_DIR_FORMAT_ZFORMAT_ZF32_1 0x00000003 + +#define NVCB97_SET_POLY_OFFSET_POINT 0x0dc0 +#define NVCB97_SET_POLY_OFFSET_POINT_ENABLE 0:0 +#define NVCB97_SET_POLY_OFFSET_POINT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_POLY_OFFSET_POINT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_POLY_OFFSET_LINE 0x0dc4 +#define NVCB97_SET_POLY_OFFSET_LINE_ENABLE 0:0 +#define NVCB97_SET_POLY_OFFSET_LINE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_POLY_OFFSET_LINE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_POLY_OFFSET_FILL 0x0dc8 +#define NVCB97_SET_POLY_OFFSET_FILL_ENABLE 0:0 +#define NVCB97_SET_POLY_OFFSET_FILL_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_POLY_OFFSET_FILL_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_PATCH 0x0dcc +#define NVCB97_SET_PATCH_SIZE 7:0 + +#define NVCB97_SET_ITERATED_BLEND 0x0dd0 +#define NVCB97_SET_ITERATED_BLEND_ENABLE 0:0 +#define NVCB97_SET_ITERATED_BLEND_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ITERATED_BLEND_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ITERATED_BLEND_ALPHA_ENABLE 1:1 +#define NVCB97_SET_ITERATED_BLEND_ALPHA_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ITERATED_BLEND_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_ITERATED_BLEND_PASS 0x0dd4 +#define NVCB97_SET_ITERATED_BLEND_PASS_COUNT 7:0 + +#define NVCB97_SET_ZCULL_CRITERION 0x0dd8 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC 7:0 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC_NEVER 0x00000000 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC_LESS 0x00000001 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC_EQUAL 0x00000002 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC_LEQUAL 0x00000003 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC_GREATER 0x00000004 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC_NOTEQUAL 0x00000005 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC_GEQUAL 0x00000006 +#define NVCB97_SET_ZCULL_CRITERION_SFUNC_ALWAYS 0x00000007 +#define NVCB97_SET_ZCULL_CRITERION_NO_INVALIDATE 8:8 +#define NVCB97_SET_ZCULL_CRITERION_NO_INVALIDATE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_CRITERION_NO_INVALIDATE_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_CRITERION_FORCE_MATCH 9:9 +#define NVCB97_SET_ZCULL_CRITERION_FORCE_MATCH_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_CRITERION_FORCE_MATCH_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_CRITERION_SREF 23:16 +#define NVCB97_SET_ZCULL_CRITERION_SMASK 31:24 + +#define NVCB97_PIXEL_SHADER_BARRIER 0x0de0 +#define NVCB97_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE 0:0 +#define NVCB97_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_FALSE 0x00000000 +#define NVCB97_PIXEL_SHADER_BARRIER_SYSMEMBAR_ENABLE_TRUE 0x00000001 +#define NVCB97_PIXEL_SHADER_BARRIER_BARRIER_LOCATION 1:1 +#define NVCB97_PIXEL_SHADER_BARRIER_BARRIER_LOCATION_BLOCK_BEFORE_PS 0x00000000 +#define NVCB97_PIXEL_SHADER_BARRIER_BARRIER_LOCATION_BLOCK_BEFORE_PS_AND_ZTEST 0x00000001 + +#define NVCB97_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVCB97_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVCB97_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY 0x0de8 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE 0:0 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_VERTEX_ARRAY_ENABLE_TRUE 0x00000001 + +#define NVCB97_MME_DMA_WRITE_METHOD_BARRIER 0x0dec +#define NVCB97_MME_DMA_WRITE_METHOD_BARRIER_V 0:0 + +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER 0x0df0 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_POINTER_V 7:0 + +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION 0x0df4 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC 2:0 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_FALSE 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_TRUE 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_EQ 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_NE 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LT 0x00000004 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_LE 0x00000005 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GT 0x00000006 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_TEST_CC_GE 0x00000007 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION 5:3 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD_PRODUCTS 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUB_PRODUCTS 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MIN 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_MAX 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_RCP 0x00000004 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_ADD 0x00000005 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERATION_SUBTRACT 0x00000006 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT 8:6 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT0 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT1 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT2 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT3 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT4 0x00000004 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT5 0x00000005 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT6 0x00000006 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_CONSTANT_INPUT_SELECT_CONSTANT7 0x00000007 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT 11:9 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_RGB 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_RGB 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_SRC_AAA 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_DEST_AAA 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP0_RGB 0x00000004 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP1_RGB 0x00000005 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_TEMP2_RGB 0x00000006 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_A_SELECT_PBR_RGB 0x00000007 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT 15:12 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_RGB 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_SRC_AAA 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_RGB 0x00000005 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_DEST_AAA 0x00000006 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP0_RGB 0x00000009 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP1_RGB 0x0000000A +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_TEMP2_RGB 0x0000000B +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_PBR_RGB 0x0000000C +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_CONSTANT_RGB 0x0000000D +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_B_SELECT_ZERO_A_TIMES_B 0x0000000E +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT 18:16 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_RGB 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_RGB 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_SRC_AAA 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_DEST_AAA 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP0_RGB 0x00000004 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP1_RGB 0x00000005 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_TEMP2_RGB 0x00000006 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_C_SELECT_PBR_RGB 0x00000007 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT 22:19 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_RGB 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_SRC_AAA 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_SRC_AAA 0x00000004 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_RGB 0x00000005 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_DEST_AAA 0x00000006 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ONE_MINUS_DEST_AAA 0x00000007 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP0_RGB 0x00000009 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP1_RGB 0x0000000A +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_TEMP2_RGB 0x0000000B +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_PBR_RGB 0x0000000C +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_CONSTANT_RGB 0x0000000D +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OPERAND_D_SELECT_ZERO_C_TIMES_D 0x0000000E +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE 25:23 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RGB 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GBR 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_RRR 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_GGG 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_BBB 0x00000004 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_SWIZZLE_R_TO_A 0x00000005 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK 27:26 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_RGB 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_R_ONLY 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_G_ONLY 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_OUTPUT_WRITE_MASK_B_ONLY 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT 29:28 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP0 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP1 0x00000001 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_TEMP2 0x00000002 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_PASS_OUTPUT_NONE 0x00000003 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC 31:31 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_FALSE 0x00000000 +#define NVCB97_LOAD_ITERATED_BLEND_INSTRUCTION_SET_CC_TRUE 0x00000001 + +#define NVCB97_SET_WINDOW_OFFSET_X 0x0df8 +#define NVCB97_SET_WINDOW_OFFSET_X_V 16:0 + +#define NVCB97_SET_WINDOW_OFFSET_Y 0x0dfc +#define NVCB97_SET_WINDOW_OFFSET_Y_V 17:0 + +#define NVCB97_SET_SCISSOR_ENABLE(j) (0x0e00+(j)*16) +#define NVCB97_SET_SCISSOR_ENABLE_V 0:0 +#define NVCB97_SET_SCISSOR_ENABLE_V_FALSE 0x00000000 +#define NVCB97_SET_SCISSOR_ENABLE_V_TRUE 0x00000001 + +#define NVCB97_SET_SCISSOR_HORIZONTAL(j) (0x0e04+(j)*16) +#define NVCB97_SET_SCISSOR_HORIZONTAL_XMIN 15:0 +#define NVCB97_SET_SCISSOR_HORIZONTAL_XMAX 31:16 + +#define NVCB97_SET_SCISSOR_VERTICAL(j) (0x0e08+(j)*16) +#define NVCB97_SET_SCISSOR_VERTICAL_YMIN 15:0 +#define NVCB97_SET_SCISSOR_VERTICAL_YMAX 31:16 + +#define NVCB97_SET_VPC_PERF_KNOB 0x0f14 +#define NVCB97_SET_VPC_PERF_KNOB_CULLED_SMALL_LINES 7:0 +#define NVCB97_SET_VPC_PERF_KNOB_CULLED_SMALL_TRIANGLES 15:8 +#define NVCB97_SET_VPC_PERF_KNOB_NONCULLED_LINES_AND_POINTS 23:16 +#define NVCB97_SET_VPC_PERF_KNOB_NONCULLED_TRIANGLES 31:24 + +#define NVCB97_PM_LOCAL_TRIGGER 0x0f18 +#define NVCB97_PM_LOCAL_TRIGGER_BOOKMARK 15:0 + +#define NVCB97_SET_POST_Z_PS_IMASK 0x0f1c +#define NVCB97_SET_POST_Z_PS_IMASK_ENABLE 0:0 +#define NVCB97_SET_POST_Z_PS_IMASK_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_POST_Z_PS_IMASK_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_CONSTANT_COLOR_RENDERING 0x0f40 +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_ENABLE 0:0 +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_RED 0x0f44 +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_RED_V 31:0 + +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_GREEN 0x0f48 +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_GREEN_V 31:0 + +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_BLUE 0x0f4c +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_BLUE_V 31:0 + +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_ALPHA 0x0f50 +#define NVCB97_SET_CONSTANT_COLOR_RENDERING_ALPHA_V 31:0 + +#define NVCB97_SET_BACK_STENCIL_FUNC_REF 0x0f54 +#define NVCB97_SET_BACK_STENCIL_FUNC_REF_V 7:0 + +#define NVCB97_SET_BACK_STENCIL_MASK 0x0f58 +#define NVCB97_SET_BACK_STENCIL_MASK_V 7:0 + +#define NVCB97_SET_BACK_STENCIL_FUNC_MASK 0x0f5c +#define NVCB97_SET_BACK_STENCIL_FUNC_MASK_V 7:0 + +#define NVCB97_SET_VERTEX_STREAM_SUBSTITUTE_A 0x0f84 +#define NVCB97_SET_VERTEX_STREAM_SUBSTITUTE_A_ADDRESS_UPPER 7:0 + +#define NVCB97_SET_VERTEX_STREAM_SUBSTITUTE_B 0x0f88 +#define NVCB97_SET_VERTEX_STREAM_SUBSTITUTE_B_ADDRESS_LOWER 31:0 + +#define NVCB97_SET_LINE_MODE_POLYGON_CLIP 0x0f8c +#define NVCB97_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE 0:0 +#define NVCB97_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DRAW_LINE 0x00000000 +#define NVCB97_SET_LINE_MODE_POLYGON_CLIP_GENERATED_EDGE_DO_NOT_DRAW_LINE 0x00000001 + +#define NVCB97_SET_SINGLE_CT_WRITE_CONTROL 0x0f90 +#define NVCB97_SET_SINGLE_CT_WRITE_CONTROL_ENABLE 0:0 +#define NVCB97_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SINGLE_CT_WRITE_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_VTG_WARP_WATERMARKS 0x0f98 +#define NVCB97_SET_VTG_WARP_WATERMARKS_LOW 15:0 +#define NVCB97_SET_VTG_WARP_WATERMARKS_HIGH 31:16 + +#define NVCB97_SET_DEPTH_BOUNDS_MIN 0x0f9c +#define NVCB97_SET_DEPTH_BOUNDS_MIN_V 31:0 + +#define NVCB97_SET_DEPTH_BOUNDS_MAX 0x0fa0 +#define NVCB97_SET_DEPTH_BOUNDS_MAX_V 31:0 + +#define NVCB97_SET_SAMPLE_MASK 0x0fa4 +#define NVCB97_SET_SAMPLE_MASK_RASTER_OUT_ENABLE 0:0 +#define NVCB97_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SAMPLE_MASK_RASTER_OUT_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE 4:4 +#define NVCB97_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SAMPLE_MASK_COLOR_TARGET_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_COLOR_TARGET_SAMPLE_MASK 0x0fa8 +#define NVCB97_SET_COLOR_TARGET_SAMPLE_MASK_V 15:0 + +#define NVCB97_SET_CT_MRT_ENABLE 0x0fac +#define NVCB97_SET_CT_MRT_ENABLE_V 0:0 +#define NVCB97_SET_CT_MRT_ENABLE_V_FALSE 0x00000000 +#define NVCB97_SET_CT_MRT_ENABLE_V_TRUE 0x00000001 + +#define NVCB97_SET_NONMULTISAMPLED_Z 0x0fb0 +#define NVCB97_SET_NONMULTISAMPLED_Z_V 0:0 +#define NVCB97_SET_NONMULTISAMPLED_Z_V_PER_SAMPLE 0x00000000 +#define NVCB97_SET_NONMULTISAMPLED_Z_V_AT_PIXEL_CENTER 0x00000001 + +#define NVCB97_SET_TIR 0x0fb4 +#define NVCB97_SET_TIR_MODE 1:0 +#define NVCB97_SET_TIR_MODE_DISABLED 0x00000000 +#define NVCB97_SET_TIR_MODE_RASTER_N_TARGET_M 0x00000001 + +#define NVCB97_SET_ANTI_ALIAS_RASTER 0x0fb8 +#define NVCB97_SET_ANTI_ALIAS_RASTER_SAMPLES 2:0 +#define NVCB97_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_1X1 0x00000000 +#define NVCB97_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X2 0x00000002 +#define NVCB97_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVCB97_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVCB97_SET_ANTI_ALIAS_RASTER_SAMPLES_MODE_4X4 0x00000006 + +#define NVCB97_SET_SAMPLE_MASK_X0_Y0 0x0fbc +#define NVCB97_SET_SAMPLE_MASK_X0_Y0_V 15:0 + +#define NVCB97_SET_SAMPLE_MASK_X1_Y0 0x0fc0 +#define NVCB97_SET_SAMPLE_MASK_X1_Y0_V 15:0 + +#define NVCB97_SET_SAMPLE_MASK_X0_Y1 0x0fc4 +#define NVCB97_SET_SAMPLE_MASK_X0_Y1_V 15:0 + +#define NVCB97_SET_SAMPLE_MASK_X1_Y1 0x0fc8 +#define NVCB97_SET_SAMPLE_MASK_X1_Y1_V 15:0 + +#define NVCB97_SET_SURFACE_CLIP_ID_MEMORY_A 0x0fcc +#define NVCB97_SET_SURFACE_CLIP_ID_MEMORY_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_SURFACE_CLIP_ID_MEMORY_B 0x0fd0 +#define NVCB97_SET_SURFACE_CLIP_ID_MEMORY_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_TIR_MODULATION 0x0fd4 +#define NVCB97_SET_TIR_MODULATION_COMPONENT_SELECT 1:0 +#define NVCB97_SET_TIR_MODULATION_COMPONENT_SELECT_NO_MODULATION 0x00000000 +#define NVCB97_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGB 0x00000001 +#define NVCB97_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_ALPHA_ONLY 0x00000002 +#define NVCB97_SET_TIR_MODULATION_COMPONENT_SELECT_MODULATE_RGBA 0x00000003 + +#define NVCB97_SET_TIR_MODULATION_FUNCTION 0x0fd8 +#define NVCB97_SET_TIR_MODULATION_FUNCTION_SELECT 0:0 +#define NVCB97_SET_TIR_MODULATION_FUNCTION_SELECT_LINEAR 0x00000000 +#define NVCB97_SET_TIR_MODULATION_FUNCTION_SELECT_TABLE 0x00000001 + +#define NVCB97_SET_BLEND_OPT_CONTROL 0x0fdc +#define NVCB97_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS 0:0 +#define NVCB97_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_FALSE 0x00000000 +#define NVCB97_SET_BLEND_OPT_CONTROL_ALLOW_FLOAT_PIXEL_KILLS_TRUE 0x00000001 + +#define NVCB97_SET_ZT_A 0x0fe0 +#define NVCB97_SET_ZT_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_ZT_B 0x0fe4 +#define NVCB97_SET_ZT_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_ZT_FORMAT 0x0fe8 +#define NVCB97_SET_ZT_FORMAT_V 4:0 +#define NVCB97_SET_ZT_FORMAT_V_Z16 0x00000013 +#define NVCB97_SET_ZT_FORMAT_V_Z24S8 0x00000014 +#define NVCB97_SET_ZT_FORMAT_V_X8Z24 0x00000015 +#define NVCB97_SET_ZT_FORMAT_V_S8Z24 0x00000016 +#define NVCB97_SET_ZT_FORMAT_V_S8 0x00000017 +#define NVCB97_SET_ZT_FORMAT_V_ZF32 0x0000000A +#define NVCB97_SET_ZT_FORMAT_V_ZF32_X24S8 0x00000019 + +#define NVCB97_SET_ZT_BLOCK_SIZE 0x0fec +#define NVCB97_SET_ZT_BLOCK_SIZE_WIDTH 3:0 +#define NVCB97_SET_ZT_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVCB97_SET_ZT_BLOCK_SIZE_HEIGHT 7:4 +#define NVCB97_SET_ZT_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVCB97_SET_ZT_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVCB97_SET_ZT_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVCB97_SET_ZT_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVCB97_SET_ZT_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVCB97_SET_ZT_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_SET_ZT_BLOCK_SIZE_DEPTH 11:8 +#define NVCB97_SET_ZT_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 + +#define NVCB97_SET_ZT_ARRAY_PITCH 0x0ff0 +#define NVCB97_SET_ZT_ARRAY_PITCH_V 31:0 + +#define NVCB97_SET_SURFACE_CLIP_HORIZONTAL 0x0ff4 +#define NVCB97_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 +#define NVCB97_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 + +#define NVCB97_SET_SURFACE_CLIP_VERTICAL 0x0ff8 +#define NVCB97_SET_SURFACE_CLIP_VERTICAL_Y 15:0 +#define NVCB97_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 + +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS 0x1000 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE 0:0 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_FALSE 0x00000000 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_SYSTEM_MEMORY_VOLATILE_TRUE 0x00000001 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY 5:4 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_VAF_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVCB97_SET_VIEWPORT_MULTICAST 0x1004 +#define NVCB97_SET_VIEWPORT_MULTICAST_ORDER 0:0 +#define NVCB97_SET_VIEWPORT_MULTICAST_ORDER_VIEWPORT_ORDER 0x00000000 +#define NVCB97_SET_VIEWPORT_MULTICAST_ORDER_PRIMITIVE_ORDER 0x00000001 + +#define NVCB97_SET_TESSELLATION_CUT_HEIGHT 0x1008 +#define NVCB97_SET_TESSELLATION_CUT_HEIGHT_V 4:0 + +#define NVCB97_SET_MAX_GS_INSTANCES_PER_TASK 0x100c +#define NVCB97_SET_MAX_GS_INSTANCES_PER_TASK_V 10:0 + +#define NVCB97_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK 0x1010 +#define NVCB97_SET_MAX_GS_OUTPUT_VERTICES_PER_TASK_V 15:0 + +#define NVCB97_SET_RESERVED_SW_METHOD00 0x1014 +#define NVCB97_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVCB97_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER 0x1018 +#define NVCB97_SET_GS_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVCB97_SET_BETA_CB_STORAGE_CONSTRAINT 0x101c +#define NVCB97_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVCB97_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_BETA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER 0x1020 +#define NVCB97_SET_TI_OUTPUT_CB_STORAGE_MULTIPLIER_V 9:0 + +#define NVCB97_SET_ALPHA_CB_STORAGE_CONSTRAINT 0x1024 +#define NVCB97_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE 0:0 +#define NVCB97_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ALPHA_CB_STORAGE_CONSTRAINT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_RESERVED_SW_METHOD01 0x1028 +#define NVCB97_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD02 0x102c +#define NVCB97_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVCB97_SET_TIR_MODULATION_COEFFICIENT_TABLE(i) (0x1030+(i)*4) +#define NVCB97_SET_TIR_MODULATION_COEFFICIENT_TABLE_V0 7:0 +#define NVCB97_SET_TIR_MODULATION_COEFFICIENT_TABLE_V1 15:8 +#define NVCB97_SET_TIR_MODULATION_COEFFICIENT_TABLE_V2 23:16 +#define NVCB97_SET_TIR_MODULATION_COEFFICIENT_TABLE_V3 31:24 + +#define NVCB97_SET_SPARE_NOOP01 0x1044 +#define NVCB97_SET_SPARE_NOOP01_V 31:0 + +#define NVCB97_SET_SPARE_NOOP02 0x1048 +#define NVCB97_SET_SPARE_NOOP02_V 31:0 + +#define NVCB97_SET_SPARE_NOOP03 0x104c +#define NVCB97_SET_SPARE_NOOP03_V 31:0 + +#define NVCB97_SET_SPARE_NOOP04 0x1050 +#define NVCB97_SET_SPARE_NOOP04_V 31:0 + +#define NVCB97_SET_SPARE_NOOP05 0x1054 +#define NVCB97_SET_SPARE_NOOP05_V 31:0 + +#define NVCB97_SET_SPARE_NOOP06 0x1058 +#define NVCB97_SET_SPARE_NOOP06_V 31:0 + +#define NVCB97_SET_SPARE_NOOP07 0x105c +#define NVCB97_SET_SPARE_NOOP07_V 31:0 + +#define NVCB97_SET_SPARE_NOOP08 0x1060 +#define NVCB97_SET_SPARE_NOOP08_V 31:0 + +#define NVCB97_SET_SPARE_NOOP09 0x1064 +#define NVCB97_SET_SPARE_NOOP09_V 31:0 + +#define NVCB97_SET_SPARE_NOOP10 0x1068 +#define NVCB97_SET_SPARE_NOOP10_V 31:0 + +#define NVCB97_SET_SPARE_NOOP11 0x106c +#define NVCB97_SET_SPARE_NOOP11_V 31:0 + +#define NVCB97_SET_SPARE_NOOP12 0x1070 +#define NVCB97_SET_SPARE_NOOP12_V 31:0 + +#define NVCB97_SET_SPARE_NOOP13 0x1074 +#define NVCB97_SET_SPARE_NOOP13_V 31:0 + +#define NVCB97_SET_SPARE_NOOP14 0x1078 +#define NVCB97_SET_SPARE_NOOP14_V 31:0 + +#define NVCB97_SET_SPARE_NOOP15 0x107c +#define NVCB97_SET_SPARE_NOOP15_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD03 0x10b0 +#define NVCB97_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD04 0x10b4 +#define NVCB97_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD05 0x10b8 +#define NVCB97_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD06 0x10bc +#define NVCB97_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD07 0x10c0 +#define NVCB97_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD08 0x10c4 +#define NVCB97_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD09 0x10c8 +#define NVCB97_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM8 0x10cc +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM8_ALL_COVERED 23:16 + +#define NVCB97_SET_RESERVED_SW_METHOD10 0x10d0 +#define NVCB97_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD11 0x10d4 +#define NVCB97_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD12 0x10d8 +#define NVCB97_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD13 0x10dc +#define NVCB97_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM10 0x10e0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM10_ALL_COVERED 23:16 + +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM16 0x10e4 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_UNORM16_ALL_COVERED 23:16 + +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_FP11 0x10e8 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED_ALL_HIT_ONCE 5:0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_FP11_ALL_COVERED 21:16 + +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_FP16 0x10ec +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_FP16_ALL_COVERED 23:16 + +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_SRGB8 0x10f0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED_ALL_HIT_ONCE 7:0 +#define NVCB97_SET_REDUCE_COLOR_THRESHOLDS_SRGB8_ALL_COVERED 23:16 + +#define NVCB97_UNBIND_ALL 0x10f4 +#define NVCB97_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NVCB97_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NVCB97_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NVCB97_SET_CLEAR_SURFACE_CONTROL 0x10f8 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK 0:0 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_FALSE 0x00000000 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_RESPECT_STENCIL_MASK_TRUE 0x00000001 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT 4:4 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0 8:8 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_FALSE 0x00000000 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_SCISSOR0_TRUE 0x00000001 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0 12:12 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_FALSE 0x00000000 +#define NVCB97_SET_CLEAR_SURFACE_CONTROL_USE_VIEWPORT_CLIP0_TRUE 0x00000001 + +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS 0x10fc +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVCB97_SET_RESERVED_SW_METHOD14 0x1100 +#define NVCB97_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVCB97_SET_RESERVED_SW_METHOD15 0x1104 +#define NVCB97_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVCB97_NO_OPERATION_DATA_HI 0x110c +#define NVCB97_NO_OPERATION_DATA_HI_V 31:0 + +#define NVCB97_SET_DEPTH_BIAS_CONTROL 0x1110 +#define NVCB97_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT 0:0 +#define NVCB97_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_FALSE 0x00000000 +#define NVCB97_SET_DEPTH_BIAS_CONTROL_DEPTH_FORMAT_DEPENDENT_TRUE 0x00000001 + +#define NVCB97_PM_TRIGGER_END 0x1114 +#define NVCB97_PM_TRIGGER_END_V 31:0 + +#define NVCB97_SET_VERTEX_ID_BASE 0x1118 +#define NVCB97_SET_VERTEX_ID_BASE_V 31:0 + +#define NVCB97_SET_STENCIL_COMPRESSION 0x111c +#define NVCB97_SET_STENCIL_COMPRESSION_ENABLE 0:0 +#define NVCB97_SET_STENCIL_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STENCIL_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(i) (0x1120+(i)*4) +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0 0:0 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1 1:1 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2 2:2 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3 3:3 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0 4:4 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1 5:5 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2 6:6 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3 7:7 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0 8:8 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1 9:9 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2 10:10 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3 11:11 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0 12:12 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1 13:13 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2 14:14 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3 15:15 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0 16:16 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1 17:17 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2 18:18 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3 19:19 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0 20:20 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1 21:21 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2 22:22 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3 23:23 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0 24:24 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1 25:25 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2 26:26 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3 27:27 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0 28:28 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1 29:29 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2 30:30 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3 31:31 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(i) (0x1128+(i)*4) +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0 0:0 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1 1:1 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2 2:2 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3 3:3 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE0_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0 4:4 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1 5:5 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2 6:6 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3 7:7 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE1_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0 8:8 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1 9:9 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2 10:10 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3 11:11 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE2_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0 12:12 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1 13:13 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2 14:14 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3 15:15 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE3_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0 16:16 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1 17:17 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2 18:18 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3 19:19 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE4_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0 20:20 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1 21:21 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2 22:22 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3 23:23 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE5_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0 24:24 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1 25:25 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2 26:26 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3 27:27 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE6_COMP3_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0 28:28 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP0_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1 29:29 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP1_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2 30:30 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP2_TRUE 0x00000001 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3 31:31 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B_ATTRIBUTE7_COMP3_TRUE 0x00000001 + +#define NVCB97_SET_TIR_CONTROL 0x1130 +#define NVCB97_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES 0:0 +#define NVCB97_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVCB97_SET_TIR_CONTROL_Z_PASS_PIXEL_COUNT_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVCB97_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES 4:4 +#define NVCB97_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_DISABLE 0x00000000 +#define NVCB97_SET_TIR_CONTROL_ALPHA_TO_COVERAGE_USE_RASTER_SAMPLES_ENABLE 0x00000001 +#define NVCB97_SET_TIR_CONTROL_REDUCE_COVERAGE 1:1 +#define NVCB97_SET_TIR_CONTROL_REDUCE_COVERAGE_DISABLE 0x00000000 +#define NVCB97_SET_TIR_CONTROL_REDUCE_COVERAGE_ENABLE 0x00000001 +#define NVCB97_SET_TIR_CONTROL_REDUCTION_MODE 2:2 +#define NVCB97_SET_TIR_CONTROL_REDUCTION_MODE_AFFINITY_MAP 0x00000000 +#define NVCB97_SET_TIR_CONTROL_REDUCTION_MODE_TRUNCATION 0x00000001 + +#define NVCB97_SET_MUTABLE_METHOD_CONTROL 0x1134 +#define NVCB97_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT 0:0 +#define NVCB97_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_FALSE 0x00000000 +#define NVCB97_SET_MUTABLE_METHOD_CONTROL_TREAT_MUTABLE_AS_HEAVYWEIGHT_TRUE 0x00000001 + +#define NVCB97_SET_POST_PS_INITIAL_COVERAGE 0x1138 +#define NVCB97_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE 0:0 +#define NVCB97_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_FALSE 0x00000000 +#define NVCB97_SET_POST_PS_INITIAL_COVERAGE_USE_PRE_PS_COVERAGE_TRUE 0x00000001 + +#define NVCB97_SET_FILL_VIA_TRIANGLE 0x113c +#define NVCB97_SET_FILL_VIA_TRIANGLE_MODE 1:0 +#define NVCB97_SET_FILL_VIA_TRIANGLE_MODE_DISABLED 0x00000000 +#define NVCB97_SET_FILL_VIA_TRIANGLE_MODE_FILL_ALL 0x00000001 +#define NVCB97_SET_FILL_VIA_TRIANGLE_MODE_FILL_BBOX 0x00000002 + +#define NVCB97_SET_BLEND_PER_FORMAT_ENABLE 0x1140 +#define NVCB97_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16 4:4 +#define NVCB97_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_FALSE 0x00000000 +#define NVCB97_SET_BLEND_PER_FORMAT_ENABLE_SNORM8_UNORM16_SNORM16_TRUE 0x00000001 + +#define NVCB97_FLUSH_PENDING_WRITES 0x1144 +#define NVCB97_FLUSH_PENDING_WRITES_SM_DOES_GLOBAL_STORE 0:0 + +#define NVCB97_SET_VERTEX_ATTRIBUTE_A(i) (0x1160+(i)*4) +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_STREAM 4:0 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_SOURCE 6:6 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_SOURCE_ACTIVE 0x00000000 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_SOURCE_INACTIVE 0x00000001 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_OFFSET 20:7 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS 26:21 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE 29:27 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B 31:31 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_FALSE 0x00000000 +#define NVCB97_SET_VERTEX_ATTRIBUTE_A_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVCB97_SET_VERTEX_ATTRIBUTE_B(i) (0x11a0+(i)*4) +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_STREAM 4:0 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_SOURCE 6:6 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_SOURCE_ACTIVE 0x00000000 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_SOURCE_INACTIVE 0x00000001 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_OFFSET 20:7 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS 26:21 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32_A32 0x00000001 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32_B32 0x00000002 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16_A16 0x00000003 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32_G32 0x00000004 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16_B16 0x00000005 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8B8G8R8 0x0000002F +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8_A8 0x0000000A +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_X8B8G8R8 0x00000033 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A2B10G10R10 0x00000030 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_B10G11R11 0x00000031 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16_G16 0x0000000F +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R32 0x00000012 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8_B8 0x00000013 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_G8R8 0x00000032 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8_G8 0x00000018 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R16 0x0000001B +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_R8 0x0000001D +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_COMPONENT_BIT_WIDTHS_A8 0x00000034 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE 29:27 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_UNUSED_ENUM_DO_NOT_USE_BECAUSE_IT_WILL_GO_AWAY 0x00000000 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SINT 0x00000003 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_UINT 0x00000004 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_USCALED 0x00000005 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_SSCALED 0x00000006 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_NUMERICAL_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B 31:31 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_FALSE 0x00000000 +#define NVCB97_SET_VERTEX_ATTRIBUTE_B_SWAP_R_AND_B_TRUE 0x00000001 + +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS(i) (0x11e0+(i)*4) +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X0 3:0 +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y0 7:4 +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X1 11:8 +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y1 15:12 +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X2 19:16 +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y2 23:20 +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS_X3 27:24 +#define NVCB97_SET_ANTI_ALIAS_SAMPLE_POSITIONS_Y3 31:28 + +#define NVCB97_SET_OFFSET_RENDER_TARGET_INDEX 0x11f0 +#define NVCB97_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX 0:0 +#define NVCB97_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_FALSE 0x00000000 +#define NVCB97_SET_OFFSET_RENDER_TARGET_INDEX_BY_VIEWPORT_INDEX_TRUE 0x00000001 + +#define NVCB97_FORCE_HEAVYWEIGHT_METHOD_SYNC 0x11f4 +#define NVCB97_FORCE_HEAVYWEIGHT_METHOD_SYNC_V 31:0 + +#define NVCB97_SET_COVERAGE_TO_COLOR 0x11f8 +#define NVCB97_SET_COVERAGE_TO_COLOR_ENABLE 0:0 +#define NVCB97_SET_COVERAGE_TO_COLOR_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_COVERAGE_TO_COLOR_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_COVERAGE_TO_COLOR_CT_SELECT 6:4 + +#define NVCB97_DECOMPRESS_ZETA_SURFACE 0x11fc +#define NVCB97_DECOMPRESS_ZETA_SURFACE_Z_ENABLE 0:0 +#define NVCB97_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVCB97_DECOMPRESS_ZETA_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVCB97_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE 4:4 +#define NVCB97_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVCB97_DECOMPRESS_ZETA_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_SCREEN_STATE_MASK 0x1204 +#define NVCB97_SET_SCREEN_STATE_MASK_MASK 3:0 + +#define NVCB97_SET_ZT_SPARSE 0x1208 +#define NVCB97_SET_ZT_SPARSE_ENABLE 0:0 +#define NVCB97_SET_ZT_SPARSE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZT_SPARSE_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ZT_SPARSE_UNMAPPED_COMPARE 1:1 +#define NVCB97_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_UNMAPPED_0 0x00000000 +#define NVCB97_SET_ZT_SPARSE_UNMAPPED_COMPARE_ZT_SPARSE_FAIL_ALWAYS 0x00000001 + +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST 0x1214 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_START_INDEX 15:0 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT 0x1218 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_START_INDEX 15:0 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_DRAW_VERTEX_ARRAY_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVCB97_SET_CT_SELECT 0x121c +#define NVCB97_SET_CT_SELECT_TARGET_COUNT 3:0 +#define NVCB97_SET_CT_SELECT_TARGET0 6:4 +#define NVCB97_SET_CT_SELECT_TARGET1 9:7 +#define NVCB97_SET_CT_SELECT_TARGET2 12:10 +#define NVCB97_SET_CT_SELECT_TARGET3 15:13 +#define NVCB97_SET_CT_SELECT_TARGET4 18:16 +#define NVCB97_SET_CT_SELECT_TARGET5 21:19 +#define NVCB97_SET_CT_SELECT_TARGET6 24:22 +#define NVCB97_SET_CT_SELECT_TARGET7 27:25 + +#define NVCB97_SET_COMPRESSION_THRESHOLD 0x1220 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES 3:0 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__0 0x00000000 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__1 0x00000001 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__2 0x00000002 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__4 0x00000003 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__8 0x00000004 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__16 0x00000005 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__32 0x00000006 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__64 0x00000007 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__128 0x00000008 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__256 0x00000009 +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__512 0x0000000A +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__1024 0x0000000B +#define NVCB97_SET_COMPRESSION_THRESHOLD_SAMPLES__2048 0x0000000C + +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL 0x1224 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE 1:0 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_NO_CONFLICT_DETECT 0x00000000 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_SAMPLE 0x00000001 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_MODE_CONFLICT_DETECT_PIXEL 0x00000002 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE 2:2 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_16X16 0x00000000 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_TILE_SIZE_TC_TILE_SIZE_8X8 0x00000001 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER 3:3 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_ORDERED 0x00000000 +#define NVCB97_SET_PIXEL_SHADER_INTERLOCK_CONTROL_TILE_COALESCER_FRAGMENT_ORDER_TC_FRAGMENT_UNORDERED 0x00000001 + +#define NVCB97_SET_ZT_SIZE_A 0x1228 +#define NVCB97_SET_ZT_SIZE_A_WIDTH 27:0 + +#define NVCB97_SET_ZT_SIZE_B 0x122c +#define NVCB97_SET_ZT_SIZE_B_HEIGHT 17:0 + +#define NVCB97_SET_ZT_SIZE_C 0x1230 +#define NVCB97_SET_ZT_SIZE_C_THIRD_DIMENSION 15:0 +#define NVCB97_SET_ZT_SIZE_C_CONTROL 16:16 +#define NVCB97_SET_ZT_SIZE_C_CONTROL_THIRD_DIMENSION_DEFINES_ARRAY_SIZE 0x00000000 +#define NVCB97_SET_ZT_SIZE_C_CONTROL_ARRAY_SIZE_IS_ONE 0x00000001 + +#define NVCB97_SET_SAMPLER_BINDING 0x1234 +#define NVCB97_SET_SAMPLER_BINDING_V 0:0 +#define NVCB97_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NVCB97_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NVCB97_DRAW_AUTO 0x123c +#define NVCB97_DRAW_AUTO_BYTE_COUNT 31:0 + +#define NVCB97_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK(i) (0x1240+(i)*4) +#define NVCB97_SET_POST_VTG_SHADER_ATTRIBUTE_SKIP_MASK_V 31:0 + +#define NVCB97_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE 0x1260 +#define NVCB97_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_INDEX 7:0 +#define NVCB97_SET_PIXEL_SHADER_TICKET_DISPENSER_VALUE_TICKET_DISPENSER_VALUE 23:8 + +#define NVCB97_SET_BACK_END_COPY_A 0x1264 +#define NVCB97_SET_BACK_END_COPY_A_DWORDS 7:0 +#define NVCB97_SET_BACK_END_COPY_A_SATURATE32_ENABLE 8:8 +#define NVCB97_SET_BACK_END_COPY_A_SATURATE32_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_BACK_END_COPY_A_SATURATE32_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE 12:12 +#define NVCB97_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_BACK_END_COPY_A_TIMESTAMP_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_BACK_END_COPY_B 0x1268 +#define NVCB97_SET_BACK_END_COPY_B_SRC_ADDRESS_UPPER 7:0 + +#define NVCB97_SET_BACK_END_COPY_C 0x126c +#define NVCB97_SET_BACK_END_COPY_C_SRC_ADDRESS_LOWER 31:0 + +#define NVCB97_SET_BACK_END_COPY_D 0x1270 +#define NVCB97_SET_BACK_END_COPY_D_DEST_ADDRESS_UPPER 7:0 + +#define NVCB97_SET_BACK_END_COPY_E 0x1274 +#define NVCB97_SET_BACK_END_COPY_E_DEST_ADDRESS_LOWER 31:0 + +#define NVCB97_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVCB97_SET_CIRCULAR_BUFFER_SIZE_CACHE_LINES_PER_SM 19:0 + +#define NVCB97_SET_VTG_REGISTER_WATERMARKS 0x1284 +#define NVCB97_SET_VTG_REGISTER_WATERMARKS_LOW 15:0 +#define NVCB97_SET_VTG_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS 0x1290 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY 5:4 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_READ_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVCB97_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE 0x12a4 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_INDEX_TOPOLOGY_CHANGE_V 31:0 + +#define NVCB97_CLEAR_ZCULL_REGION 0x12c8 +#define NVCB97_CLEAR_ZCULL_REGION_Z_ENABLE 0:0 +#define NVCB97_CLEAR_ZCULL_REGION_Z_ENABLE_FALSE 0x00000000 +#define NVCB97_CLEAR_ZCULL_REGION_Z_ENABLE_TRUE 0x00000001 +#define NVCB97_CLEAR_ZCULL_REGION_STENCIL_ENABLE 4:4 +#define NVCB97_CLEAR_ZCULL_REGION_STENCIL_ENABLE_FALSE 0x00000000 +#define NVCB97_CLEAR_ZCULL_REGION_STENCIL_ENABLE_TRUE 0x00000001 +#define NVCB97_CLEAR_ZCULL_REGION_USE_CLEAR_RECT 1:1 +#define NVCB97_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_FALSE 0x00000000 +#define NVCB97_CLEAR_ZCULL_REGION_USE_CLEAR_RECT_TRUE 0x00000001 +#define NVCB97_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX 2:2 +#define NVCB97_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_FALSE 0x00000000 +#define NVCB97_CLEAR_ZCULL_REGION_USE_RT_ARRAY_INDEX_TRUE 0x00000001 +#define NVCB97_CLEAR_ZCULL_REGION_RT_ARRAY_INDEX 20:5 +#define NVCB97_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE 3:3 +#define NVCB97_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_FALSE 0x00000000 +#define NVCB97_CLEAR_ZCULL_REGION_MAKE_CONSERVATIVE_TRUE 0x00000001 + +#define NVCB97_SET_DEPTH_TEST 0x12cc +#define NVCB97_SET_DEPTH_TEST_ENABLE 0:0 +#define NVCB97_SET_DEPTH_TEST_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_DEPTH_TEST_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_FILL_MODE 0x12d0 +#define NVCB97_SET_FILL_MODE_V 31:0 +#define NVCB97_SET_FILL_MODE_V_POINT 0x00000001 +#define NVCB97_SET_FILL_MODE_V_WIREFRAME 0x00000002 +#define NVCB97_SET_FILL_MODE_V_SOLID 0x00000003 + +#define NVCB97_SET_SHADE_MODE 0x12d4 +#define NVCB97_SET_SHADE_MODE_V 31:0 +#define NVCB97_SET_SHADE_MODE_V_FLAT 0x00000001 +#define NVCB97_SET_SHADE_MODE_V_GOURAUD 0x00000002 +#define NVCB97_SET_SHADE_MODE_V_OGL_FLAT 0x00001D00 +#define NVCB97_SET_SHADE_MODE_V_OGL_SMOOTH 0x00001D01 + +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS 0x12d8 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_NONINTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS 0x12dc +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY 5:4 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_FIRST 0x00000000 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_NORMAL 0x00000001 +#define NVCB97_SET_L2_CACHE_CONTROL_FOR_ROP_INTERLOCKED_WRITE_REQUESTS_POLICY_EVICT_LAST 0x00000002 + +#define NVCB97_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL 0x12e0 +#define NVCB97_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT 3:0 +#define NVCB97_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1 0x00000000 +#define NVCB97_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_2X2 0x00000001 +#define NVCB97_SET_ALPHA_TO_COVERAGE_DITHER_CONTROL_DITHER_FOOTPRINT_PIXELS_1X1_VIRTUAL_SAMPLES 0x00000002 + +#define NVCB97_SET_BLEND_STATE_PER_TARGET 0x12e4 +#define NVCB97_SET_BLEND_STATE_PER_TARGET_ENABLE 0:0 +#define NVCB97_SET_BLEND_STATE_PER_TARGET_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_BLEND_STATE_PER_TARGET_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_DEPTH_WRITE 0x12e8 +#define NVCB97_SET_DEPTH_WRITE_ENABLE 0:0 +#define NVCB97_SET_DEPTH_WRITE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_DEPTH_WRITE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_ALPHA_TEST 0x12ec +#define NVCB97_SET_ALPHA_TEST_ENABLE 0:0 +#define NVCB97_SET_ALPHA_TEST_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ALPHA_TEST_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_INLINE_INDEX4X8_ALIGN 0x1300 +#define NVCB97_SET_INLINE_INDEX4X8_ALIGN_COUNT 29:0 +#define NVCB97_SET_INLINE_INDEX4X8_ALIGN_START 31:30 + +#define NVCB97_DRAW_INLINE_INDEX4X8 0x1304 +#define NVCB97_DRAW_INLINE_INDEX4X8_INDEX0 7:0 +#define NVCB97_DRAW_INLINE_INDEX4X8_INDEX1 15:8 +#define NVCB97_DRAW_INLINE_INDEX4X8_INDEX2 23:16 +#define NVCB97_DRAW_INLINE_INDEX4X8_INDEX3 31:24 + +#define NVCB97_D3D_SET_CULL_MODE 0x1308 +#define NVCB97_D3D_SET_CULL_MODE_V 31:0 +#define NVCB97_D3D_SET_CULL_MODE_V_NONE 0x00000001 +#define NVCB97_D3D_SET_CULL_MODE_V_CW 0x00000002 +#define NVCB97_D3D_SET_CULL_MODE_V_CCW 0x00000003 + +#define NVCB97_SET_DEPTH_FUNC 0x130c +#define NVCB97_SET_DEPTH_FUNC_V 31:0 +#define NVCB97_SET_DEPTH_FUNC_V_OGL_NEVER 0x00000200 +#define NVCB97_SET_DEPTH_FUNC_V_OGL_LESS 0x00000201 +#define NVCB97_SET_DEPTH_FUNC_V_OGL_EQUAL 0x00000202 +#define NVCB97_SET_DEPTH_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVCB97_SET_DEPTH_FUNC_V_OGL_GREATER 0x00000204 +#define NVCB97_SET_DEPTH_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVCB97_SET_DEPTH_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVCB97_SET_DEPTH_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVCB97_SET_DEPTH_FUNC_V_D3D_NEVER 0x00000001 +#define NVCB97_SET_DEPTH_FUNC_V_D3D_LESS 0x00000002 +#define NVCB97_SET_DEPTH_FUNC_V_D3D_EQUAL 0x00000003 +#define NVCB97_SET_DEPTH_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVCB97_SET_DEPTH_FUNC_V_D3D_GREATER 0x00000005 +#define NVCB97_SET_DEPTH_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVCB97_SET_DEPTH_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVCB97_SET_DEPTH_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVCB97_SET_ALPHA_REF 0x1310 +#define NVCB97_SET_ALPHA_REF_V 31:0 + +#define NVCB97_SET_ALPHA_FUNC 0x1314 +#define NVCB97_SET_ALPHA_FUNC_V 31:0 +#define NVCB97_SET_ALPHA_FUNC_V_OGL_NEVER 0x00000200 +#define NVCB97_SET_ALPHA_FUNC_V_OGL_LESS 0x00000201 +#define NVCB97_SET_ALPHA_FUNC_V_OGL_EQUAL 0x00000202 +#define NVCB97_SET_ALPHA_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVCB97_SET_ALPHA_FUNC_V_OGL_GREATER 0x00000204 +#define NVCB97_SET_ALPHA_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVCB97_SET_ALPHA_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVCB97_SET_ALPHA_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVCB97_SET_ALPHA_FUNC_V_D3D_NEVER 0x00000001 +#define NVCB97_SET_ALPHA_FUNC_V_D3D_LESS 0x00000002 +#define NVCB97_SET_ALPHA_FUNC_V_D3D_EQUAL 0x00000003 +#define NVCB97_SET_ALPHA_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVCB97_SET_ALPHA_FUNC_V_D3D_GREATER 0x00000005 +#define NVCB97_SET_ALPHA_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVCB97_SET_ALPHA_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVCB97_SET_ALPHA_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVCB97_SET_DRAW_AUTO_STRIDE 0x1318 +#define NVCB97_SET_DRAW_AUTO_STRIDE_V 11:0 + +#define NVCB97_SET_BLEND_CONST_RED 0x131c +#define NVCB97_SET_BLEND_CONST_RED_V 31:0 + +#define NVCB97_SET_BLEND_CONST_GREEN 0x1320 +#define NVCB97_SET_BLEND_CONST_GREEN_V 31:0 + +#define NVCB97_SET_BLEND_CONST_BLUE 0x1324 +#define NVCB97_SET_BLEND_CONST_BLUE_V 31:0 + +#define NVCB97_SET_BLEND_CONST_ALPHA 0x1328 +#define NVCB97_SET_BLEND_CONST_ALPHA_V 31:0 + +#define NVCB97_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVCB97_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVCB97_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVCB97_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVCB97_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVCB97_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVCB97_SET_BLEND_SEPARATE_FOR_ALPHA 0x133c +#define NVCB97_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVCB97_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_BLEND_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_BLEND_COLOR_OP 0x1340 +#define NVCB97_SET_BLEND_COLOR_OP_V 31:0 +#define NVCB97_SET_BLEND_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVCB97_SET_BLEND_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVCB97_SET_BLEND_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVCB97_SET_BLEND_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVCB97_SET_BLEND_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVCB97_SET_BLEND_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVCB97_SET_BLEND_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVCB97_SET_BLEND_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVCB97_SET_BLEND_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVCB97_SET_BLEND_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF 0x1344 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V 31:0 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVCB97_SET_BLEND_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF 0x1348 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V 31:0 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVCB97_SET_BLEND_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVCB97_SET_BLEND_ALPHA_OP 0x134c +#define NVCB97_SET_BLEND_ALPHA_OP_V 31:0 +#define NVCB97_SET_BLEND_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVCB97_SET_BLEND_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVCB97_SET_BLEND_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVCB97_SET_BLEND_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVCB97_SET_BLEND_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVCB97_SET_BLEND_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVCB97_SET_BLEND_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVCB97_SET_BLEND_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVCB97_SET_BLEND_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVCB97_SET_BLEND_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF 0x1350 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V 31:0 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVCB97_SET_BLEND_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVCB97_SET_GLOBAL_COLOR_KEY 0x1354 +#define NVCB97_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NVCB97_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF 0x1358 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V 31:0 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVCB97_SET_BLEND_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVCB97_SET_SINGLE_ROP_CONTROL 0x135c +#define NVCB97_SET_SINGLE_ROP_CONTROL_ENABLE 0:0 +#define NVCB97_SET_SINGLE_ROP_CONTROL_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SINGLE_ROP_CONTROL_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_BLEND(i) (0x1360+(i)*4) +#define NVCB97_SET_BLEND_ENABLE 0:0 +#define NVCB97_SET_BLEND_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_BLEND_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_STENCIL_TEST 0x1380 +#define NVCB97_SET_STENCIL_TEST_ENABLE 0:0 +#define NVCB97_SET_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_STENCIL_OP_FAIL 0x1384 +#define NVCB97_SET_STENCIL_OP_FAIL_V 31:0 +#define NVCB97_SET_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVCB97_SET_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVCB97_SET_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVCB97_SET_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVCB97_SET_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVCB97_SET_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVCB97_SET_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVCB97_SET_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVCB97_SET_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVCB97_SET_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVCB97_SET_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVCB97_SET_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVCB97_SET_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVCB97_SET_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVCB97_SET_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVCB97_SET_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVCB97_SET_STENCIL_OP_ZFAIL 0x1388 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V 31:0 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVCB97_SET_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVCB97_SET_STENCIL_OP_ZPASS 0x138c +#define NVCB97_SET_STENCIL_OP_ZPASS_V 31:0 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVCB97_SET_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVCB97_SET_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVCB97_SET_STENCIL_FUNC 0x1390 +#define NVCB97_SET_STENCIL_FUNC_V 31:0 +#define NVCB97_SET_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVCB97_SET_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVCB97_SET_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVCB97_SET_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVCB97_SET_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVCB97_SET_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVCB97_SET_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVCB97_SET_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVCB97_SET_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVCB97_SET_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVCB97_SET_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVCB97_SET_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVCB97_SET_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVCB97_SET_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVCB97_SET_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVCB97_SET_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVCB97_SET_STENCIL_FUNC_REF 0x1394 +#define NVCB97_SET_STENCIL_FUNC_REF_V 7:0 + +#define NVCB97_SET_STENCIL_FUNC_MASK 0x1398 +#define NVCB97_SET_STENCIL_FUNC_MASK_V 7:0 + +#define NVCB97_SET_STENCIL_MASK 0x139c +#define NVCB97_SET_STENCIL_MASK_V 7:0 + +#define NVCB97_SET_DRAW_AUTO_START 0x13a4 +#define NVCB97_SET_DRAW_AUTO_START_BYTE_COUNT 31:0 + +#define NVCB97_SET_PS_SATURATE 0x13a8 +#define NVCB97_SET_PS_SATURATE_OUTPUT0 0:0 +#define NVCB97_SET_PS_SATURATE_OUTPUT0_FALSE 0x00000000 +#define NVCB97_SET_PS_SATURATE_OUTPUT0_TRUE 0x00000001 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE0 1:1 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE0_ZERO_TO_PLUS_ONE 0x00000000 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE0_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVCB97_SET_PS_SATURATE_OUTPUT1 4:4 +#define NVCB97_SET_PS_SATURATE_OUTPUT1_FALSE 0x00000000 +#define NVCB97_SET_PS_SATURATE_OUTPUT1_TRUE 0x00000001 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE1 5:5 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE1_ZERO_TO_PLUS_ONE 0x00000000 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE1_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVCB97_SET_PS_SATURATE_OUTPUT2 8:8 +#define NVCB97_SET_PS_SATURATE_OUTPUT2_FALSE 0x00000000 +#define NVCB97_SET_PS_SATURATE_OUTPUT2_TRUE 0x00000001 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE2 9:9 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE2_ZERO_TO_PLUS_ONE 0x00000000 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE2_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVCB97_SET_PS_SATURATE_OUTPUT3 12:12 +#define NVCB97_SET_PS_SATURATE_OUTPUT3_FALSE 0x00000000 +#define NVCB97_SET_PS_SATURATE_OUTPUT3_TRUE 0x00000001 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE3 13:13 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE3_ZERO_TO_PLUS_ONE 0x00000000 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE3_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVCB97_SET_PS_SATURATE_OUTPUT4 16:16 +#define NVCB97_SET_PS_SATURATE_OUTPUT4_FALSE 0x00000000 +#define NVCB97_SET_PS_SATURATE_OUTPUT4_TRUE 0x00000001 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE4 17:17 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE4_ZERO_TO_PLUS_ONE 0x00000000 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE4_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVCB97_SET_PS_SATURATE_OUTPUT5 20:20 +#define NVCB97_SET_PS_SATURATE_OUTPUT5_FALSE 0x00000000 +#define NVCB97_SET_PS_SATURATE_OUTPUT5_TRUE 0x00000001 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE5 21:21 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE5_ZERO_TO_PLUS_ONE 0x00000000 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE5_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVCB97_SET_PS_SATURATE_OUTPUT6 24:24 +#define NVCB97_SET_PS_SATURATE_OUTPUT6_FALSE 0x00000000 +#define NVCB97_SET_PS_SATURATE_OUTPUT6_TRUE 0x00000001 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE6 25:25 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE6_ZERO_TO_PLUS_ONE 0x00000000 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE6_MINUS_ONE_TO_PLUS_ONE 0x00000001 +#define NVCB97_SET_PS_SATURATE_OUTPUT7 28:28 +#define NVCB97_SET_PS_SATURATE_OUTPUT7_FALSE 0x00000000 +#define NVCB97_SET_PS_SATURATE_OUTPUT7_TRUE 0x00000001 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE7 29:29 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE7_ZERO_TO_PLUS_ONE 0x00000000 +#define NVCB97_SET_PS_SATURATE_CLAMP_RANGE7_MINUS_ONE_TO_PLUS_ONE 0x00000001 + +#define NVCB97_SET_WINDOW_ORIGIN 0x13ac +#define NVCB97_SET_WINDOW_ORIGIN_MODE 0:0 +#define NVCB97_SET_WINDOW_ORIGIN_MODE_UPPER_LEFT 0x00000000 +#define NVCB97_SET_WINDOW_ORIGIN_MODE_LOWER_LEFT 0x00000001 +#define NVCB97_SET_WINDOW_ORIGIN_FLIP_Y 4:4 +#define NVCB97_SET_WINDOW_ORIGIN_FLIP_Y_FALSE 0x00000000 +#define NVCB97_SET_WINDOW_ORIGIN_FLIP_Y_TRUE 0x00000001 + +#define NVCB97_SET_LINE_WIDTH_FLOAT 0x13b0 +#define NVCB97_SET_LINE_WIDTH_FLOAT_V 31:0 + +#define NVCB97_SET_ALIASED_LINE_WIDTH_FLOAT 0x13b4 +#define NVCB97_SET_ALIASED_LINE_WIDTH_FLOAT_V 31:0 + +#define NVCB97_SET_LINE_MULTISAMPLE_OVERRIDE 0x1418 +#define NVCB97_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE 0:0 +#define NVCB97_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_LINE_MULTISAMPLE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NVCB97_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVCB97_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVCB97_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVCB97_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVCB97_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x1428 +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVCB97_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVCB97_SET_GLOBAL_BASE_VERTEX_INDEX 0x1434 +#define NVCB97_SET_GLOBAL_BASE_VERTEX_INDEX_V 31:0 + +#define NVCB97_SET_GLOBAL_BASE_INSTANCE_INDEX 0x1438 +#define NVCB97_SET_GLOBAL_BASE_INSTANCE_INDEX_V 31:0 + +#define NVCB97_SET_PS_WARP_WATERMARKS 0x1450 +#define NVCB97_SET_PS_WARP_WATERMARKS_LOW 15:0 +#define NVCB97_SET_PS_WARP_WATERMARKS_HIGH 31:16 + +#define NVCB97_SET_PS_REGISTER_WATERMARKS 0x1454 +#define NVCB97_SET_PS_REGISTER_WATERMARKS_LOW 15:0 +#define NVCB97_SET_PS_REGISTER_WATERMARKS_HIGH 31:16 + +#define NVCB97_STORE_ZCULL 0x1464 +#define NVCB97_STORE_ZCULL_V 0:0 + +#define NVCB97_SET_ITERATED_BLEND_CONSTANT_RED(j) (0x1480+(j)*16) +#define NVCB97_SET_ITERATED_BLEND_CONSTANT_RED_V 15:0 + +#define NVCB97_SET_ITERATED_BLEND_CONSTANT_GREEN(j) (0x1484+(j)*16) +#define NVCB97_SET_ITERATED_BLEND_CONSTANT_GREEN_V 15:0 + +#define NVCB97_SET_ITERATED_BLEND_CONSTANT_BLUE(j) (0x1488+(j)*16) +#define NVCB97_SET_ITERATED_BLEND_CONSTANT_BLUE_V 15:0 + +#define NVCB97_LOAD_ZCULL 0x1500 +#define NVCB97_LOAD_ZCULL_V 0:0 + +#define NVCB97_SET_SURFACE_CLIP_ID_HEIGHT 0x1504 +#define NVCB97_SET_SURFACE_CLIP_ID_HEIGHT_V 31:0 + +#define NVCB97_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL 0x1508 +#define NVCB97_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMIN 15:0 +#define NVCB97_SET_CLIP_ID_CLEAR_RECT_HORIZONTAL_XMAX 31:16 + +#define NVCB97_SET_CLIP_ID_CLEAR_RECT_VERTICAL 0x150c +#define NVCB97_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMIN 15:0 +#define NVCB97_SET_CLIP_ID_CLEAR_RECT_VERTICAL_YMAX 31:16 + +#define NVCB97_SET_USER_CLIP_ENABLE 0x1510 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE0 0:0 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE0_FALSE 0x00000000 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE0_TRUE 0x00000001 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE1 1:1 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE1_FALSE 0x00000000 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE1_TRUE 0x00000001 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE2 2:2 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE2_FALSE 0x00000000 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE2_TRUE 0x00000001 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE3 3:3 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE3_FALSE 0x00000000 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE3_TRUE 0x00000001 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE4 4:4 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE4_FALSE 0x00000000 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE4_TRUE 0x00000001 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE5 5:5 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE5_FALSE 0x00000000 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE5_TRUE 0x00000001 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE6 6:6 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE6_FALSE 0x00000000 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE6_TRUE 0x00000001 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE7 7:7 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE7_FALSE 0x00000000 +#define NVCB97_SET_USER_CLIP_ENABLE_PLANE7_TRUE 0x00000001 + +#define NVCB97_SET_ZPASS_PIXEL_COUNT 0x1514 +#define NVCB97_SET_ZPASS_PIXEL_COUNT_ENABLE 0:0 +#define NVCB97_SET_ZPASS_PIXEL_COUNT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZPASS_PIXEL_COUNT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_POINT_SIZE 0x1518 +#define NVCB97_SET_POINT_SIZE_V 31:0 + +#define NVCB97_SET_ZCULL_STATS 0x151c +#define NVCB97_SET_ZCULL_STATS_ENABLE 0:0 +#define NVCB97_SET_ZCULL_STATS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_STATS_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_POINT_SPRITE 0x1520 +#define NVCB97_SET_POINT_SPRITE_ENABLE 0:0 +#define NVCB97_SET_POINT_SPRITE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_POINT_SPRITE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_SHADER_EXCEPTIONS 0x1528 +#define NVCB97_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVCB97_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVCB97_CLEAR_REPORT_VALUE 0x1530 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE 4:0 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_DA_VERTICES_GENERATED 0x00000012 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_DA_PRIMITIVES_GENERATED 0x00000013 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_VS_INVOCATIONS 0x00000015 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_TI_INVOCATIONS 0x00000016 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_TS_INVOCATIONS 0x00000017 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_TS_PRIMITIVES_GENERATED 0x00000018 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_GS_INVOCATIONS 0x0000001A +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_GS_PRIMITIVES_GENERATED 0x0000001B +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_VTG_PRIMITIVES_OUT 0x0000001F +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_SUCCEEDED 0x00000010 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_STREAMING_PRIMITIVES_NEEDED 0x00000011 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000003 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_CLIPPER_INVOCATIONS 0x0000001C +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_CLIPPER_PRIMITIVES_GENERATED 0x0000001D +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_ZCULL_STATS 0x00000002 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_PS_INVOCATIONS 0x0000001E +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_ALPHA_BETA_CLOCKS 0x00000004 +#define NVCB97_CLEAR_REPORT_VALUE_TYPE_SCG_CLOCKS 0x00000009 + +#define NVCB97_SET_ANTI_ALIAS_ENABLE 0x1534 +#define NVCB97_SET_ANTI_ALIAS_ENABLE_V 0:0 +#define NVCB97_SET_ANTI_ALIAS_ENABLE_V_FALSE 0x00000000 +#define NVCB97_SET_ANTI_ALIAS_ENABLE_V_TRUE 0x00000001 + +#define NVCB97_SET_ZT_SELECT 0x1538 +#define NVCB97_SET_ZT_SELECT_TARGET_COUNT 0:0 + +#define NVCB97_SET_ANTI_ALIAS_ALPHA_CONTROL 0x153c +#define NVCB97_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE 0:0 +#define NVCB97_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 +#define NVCB97_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 +#define NVCB97_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE 4:4 +#define NVCB97_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 +#define NVCB97_SET_ANTI_ALIAS_ALPHA_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 + +#define NVCB97_SET_RENDER_ENABLE_A 0x1550 +#define NVCB97_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_RENDER_ENABLE_B 0x1554 +#define NVCB97_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_RENDER_ENABLE_C 0x1558 +#define NVCB97_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVCB97_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVCB97_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVCB97_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVCB97_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVCB97_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVCB97_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVCB97_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVCB97_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVCB97_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVCB97_SET_SLOPE_SCALE_DEPTH_BIAS 0x156c +#define NVCB97_SET_SLOPE_SCALE_DEPTH_BIAS_V 31:0 + +#define NVCB97_SET_ANTI_ALIASED_LINE 0x1570 +#define NVCB97_SET_ANTI_ALIASED_LINE_ENABLE 0:0 +#define NVCB97_SET_ANTI_ALIASED_LINE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ANTI_ALIASED_LINE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_TEX_HEADER_POOL_A 0x1574 +#define NVCB97_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_TEX_HEADER_POOL_B 0x1578 +#define NVCB97_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_TEX_HEADER_POOL_C 0x157c +#define NVCB97_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVCB97_SET_ACTIVE_ZCULL_REGION 0x1590 +#define NVCB97_SET_ACTIVE_ZCULL_REGION_ID 5:0 + +#define NVCB97_SET_TWO_SIDED_STENCIL_TEST 0x1594 +#define NVCB97_SET_TWO_SIDED_STENCIL_TEST_ENABLE 0:0 +#define NVCB97_SET_TWO_SIDED_STENCIL_TEST_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_TWO_SIDED_STENCIL_TEST_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_BACK_STENCIL_OP_FAIL 0x1598 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V 31:0 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_OGL_KEEP 0x00001E00 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_OGL_ZERO 0x00000000 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_OGL_REPLACE 0x00001E01 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCRSAT 0x00001E02 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECRSAT 0x00001E03 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_OGL_INVERT 0x0000150A +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_OGL_INCR 0x00008507 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_OGL_DECR 0x00008508 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_D3D_KEEP 0x00000001 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_D3D_ZERO 0x00000002 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_D3D_REPLACE 0x00000003 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCRSAT 0x00000004 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECRSAT 0x00000005 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_D3D_INVERT 0x00000006 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_D3D_INCR 0x00000007 +#define NVCB97_SET_BACK_STENCIL_OP_FAIL_V_D3D_DECR 0x00000008 + +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL 0x159c +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V 31:0 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_KEEP 0x00001E00 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_ZERO 0x00000000 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_REPLACE 0x00001E01 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCRSAT 0x00001E02 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECRSAT 0x00001E03 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INVERT 0x0000150A +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_INCR 0x00008507 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_OGL_DECR 0x00008508 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_KEEP 0x00000001 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_ZERO 0x00000002 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_REPLACE 0x00000003 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCRSAT 0x00000004 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECRSAT 0x00000005 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INVERT 0x00000006 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_INCR 0x00000007 +#define NVCB97_SET_BACK_STENCIL_OP_ZFAIL_V_D3D_DECR 0x00000008 + +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS 0x15a0 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V 31:0 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_OGL_KEEP 0x00001E00 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_OGL_ZERO 0x00000000 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_OGL_REPLACE 0x00001E01 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCRSAT 0x00001E02 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECRSAT 0x00001E03 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INVERT 0x0000150A +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_OGL_INCR 0x00008507 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_OGL_DECR 0x00008508 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_D3D_KEEP 0x00000001 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_D3D_ZERO 0x00000002 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_D3D_REPLACE 0x00000003 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCRSAT 0x00000004 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECRSAT 0x00000005 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INVERT 0x00000006 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_D3D_INCR 0x00000007 +#define NVCB97_SET_BACK_STENCIL_OP_ZPASS_V_D3D_DECR 0x00000008 + +#define NVCB97_SET_BACK_STENCIL_FUNC 0x15a4 +#define NVCB97_SET_BACK_STENCIL_FUNC_V 31:0 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_OGL_NEVER 0x00000200 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_OGL_LESS 0x00000201 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_OGL_EQUAL 0x00000202 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_OGL_LEQUAL 0x00000203 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_OGL_GREATER 0x00000204 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_OGL_NOTEQUAL 0x00000205 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_OGL_GEQUAL 0x00000206 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_OGL_ALWAYS 0x00000207 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_D3D_NEVER 0x00000001 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_D3D_LESS 0x00000002 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_D3D_EQUAL 0x00000003 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_D3D_LESSEQUAL 0x00000004 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_D3D_GREATER 0x00000005 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_D3D_NOTEQUAL 0x00000006 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_D3D_GREATEREQUAL 0x00000007 +#define NVCB97_SET_BACK_STENCIL_FUNC_V_D3D_ALWAYS 0x00000008 + +#define NVCB97_SET_SRGB_WRITE 0x15b8 +#define NVCB97_SET_SRGB_WRITE_ENABLE 0:0 +#define NVCB97_SET_SRGB_WRITE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SRGB_WRITE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_DEPTH_BIAS 0x15bc +#define NVCB97_SET_DEPTH_BIAS_V 31:0 + +#define NVCB97_SET_ZCULL_REGION_FORMAT 0x15c8 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE 3:0 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X4 0x00000000 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_ZS_4X4 0x00000001 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X2 0x00000002 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_2X4 0x00000003 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X8_4X4 0x00000004 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_4X2 0x00000005 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_8X8_2X4 0x00000006 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_16X16_4X8 0x00000007 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_2X2 0x00000008 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_4X2 0x00000009 +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_ZS_16X8_2X4 0x0000000A +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_ZS_8X8_2X2 0x0000000B +#define NVCB97_SET_ZCULL_REGION_FORMAT_TYPE_Z_4X8_1X1 0x0000000C + +#define NVCB97_SET_RT_LAYER 0x15cc +#define NVCB97_SET_RT_LAYER_V 15:0 +#define NVCB97_SET_RT_LAYER_CONTROL 16:16 +#define NVCB97_SET_RT_LAYER_CONTROL_V_SELECTS_LAYER 0x00000000 +#define NVCB97_SET_RT_LAYER_CONTROL_GEOMETRY_SHADER_SELECTS_LAYER 0x00000001 + +#define NVCB97_SET_ANTI_ALIAS 0x15d0 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES 3:0 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_1X1 0x00000000 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_2X1 0x00000001 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_2X2 0x00000002 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_4X2 0x00000003 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_D3D 0x00000004 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_2X1_D3D 0x00000005 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_4X4 0x00000006 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_4 0x00000008 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12 0x00000009 +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_8 0x0000000A +#define NVCB97_SET_ANTI_ALIAS_SAMPLES_MODE_4X2_VC_24 0x0000000B + +#define NVCB97_SET_EDGE_FLAG 0x15e4 +#define NVCB97_SET_EDGE_FLAG_V 0:0 +#define NVCB97_SET_EDGE_FLAG_V_FALSE 0x00000000 +#define NVCB97_SET_EDGE_FLAG_V_TRUE 0x00000001 + +#define NVCB97_DRAW_INLINE_INDEX 0x15e8 +#define NVCB97_DRAW_INLINE_INDEX_V 31:0 + +#define NVCB97_SET_INLINE_INDEX2X16_ALIGN 0x15ec +#define NVCB97_SET_INLINE_INDEX2X16_ALIGN_COUNT 30:0 +#define NVCB97_SET_INLINE_INDEX2X16_ALIGN_START_ODD 31:31 +#define NVCB97_SET_INLINE_INDEX2X16_ALIGN_START_ODD_FALSE 0x00000000 +#define NVCB97_SET_INLINE_INDEX2X16_ALIGN_START_ODD_TRUE 0x00000001 + +#define NVCB97_DRAW_INLINE_INDEX2X16 0x15f0 +#define NVCB97_DRAW_INLINE_INDEX2X16_EVEN 15:0 +#define NVCB97_DRAW_INLINE_INDEX2X16_ODD 31:16 + +#define NVCB97_SET_VERTEX_GLOBAL_BASE_OFFSET_A 0x15f4 +#define NVCB97_SET_VERTEX_GLOBAL_BASE_OFFSET_A_UPPER 7:0 + +#define NVCB97_SET_VERTEX_GLOBAL_BASE_OFFSET_B 0x15f8 +#define NVCB97_SET_VERTEX_GLOBAL_BASE_OFFSET_B_LOWER 31:0 + +#define NVCB97_SET_ZCULL_REGION_PIXEL_OFFSET_A 0x15fc +#define NVCB97_SET_ZCULL_REGION_PIXEL_OFFSET_A_WIDTH 15:0 + +#define NVCB97_SET_ZCULL_REGION_PIXEL_OFFSET_B 0x1600 +#define NVCB97_SET_ZCULL_REGION_PIXEL_OFFSET_B_HEIGHT 15:0 + +#define NVCB97_SET_POINT_SPRITE_SELECT 0x1604 +#define NVCB97_SET_POINT_SPRITE_SELECT_RMODE 1:0 +#define NVCB97_SET_POINT_SPRITE_SELECT_RMODE_ZERO 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_RMODE_FROM_R 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_RMODE_FROM_S 0x00000002 +#define NVCB97_SET_POINT_SPRITE_SELECT_ORIGIN 2:2 +#define NVCB97_SET_POINT_SPRITE_SELECT_ORIGIN_BOTTOM 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_ORIGIN_TOP 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE0 3:3 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE0_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE0_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE1 4:4 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE1_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE1_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE2 5:5 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE2_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE2_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE3 6:6 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE3_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE3_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE4 7:7 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE4_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE4_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE5 8:8 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE5_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE5_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE6 9:9 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE6_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE6_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE7 10:10 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE7_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE7_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE8 11:11 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE8_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE8_GENERATE 0x00000001 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE9 12:12 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE9_PASSTHROUGH 0x00000000 +#define NVCB97_SET_POINT_SPRITE_SELECT_TEXTURE9_GENERATE 0x00000001 + +#define NVCB97_SET_ATTRIBUTE_DEFAULT 0x1610 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE 0:0 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_0001 0x00000000 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_DIFFUSE_VECTOR_1111 0x00000001 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR 1:1 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0000 0x00000000 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_COLOR_FRONT_SPECULAR_VECTOR_0001 0x00000001 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR 2:2 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0000 0x00000000 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_GENERIC_VECTOR_VECTOR_0001 0x00000001 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE 3:3 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0000 0x00000000 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_FIXED_FNC_TEXTURE_VECTOR_0001 0x00000001 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0 4:4 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_0001 0x00000000 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_DX9_COLOR0_VECTOR_1111 0x00000001 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15 5:5 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0000 0x00000000 +#define NVCB97_SET_ATTRIBUTE_DEFAULT_DX9_COLOR1_TO_COLOR15_VECTOR_0001 0x00000001 + +#define NVCB97_END 0x1614 +#define NVCB97_END_V 0:0 + +#define NVCB97_BEGIN 0x1618 +#define NVCB97_BEGIN_OP 15:0 +#define NVCB97_BEGIN_OP_POINTS 0x00000000 +#define NVCB97_BEGIN_OP_LINES 0x00000001 +#define NVCB97_BEGIN_OP_LINE_LOOP 0x00000002 +#define NVCB97_BEGIN_OP_LINE_STRIP 0x00000003 +#define NVCB97_BEGIN_OP_TRIANGLES 0x00000004 +#define NVCB97_BEGIN_OP_TRIANGLE_STRIP 0x00000005 +#define NVCB97_BEGIN_OP_TRIANGLE_FAN 0x00000006 +#define NVCB97_BEGIN_OP_QUADS 0x00000007 +#define NVCB97_BEGIN_OP_QUAD_STRIP 0x00000008 +#define NVCB97_BEGIN_OP_POLYGON 0x00000009 +#define NVCB97_BEGIN_OP_LINELIST_ADJCY 0x0000000A +#define NVCB97_BEGIN_OP_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_BEGIN_OP_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_BEGIN_OP_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_BEGIN_OP_PATCH 0x0000000E +#define NVCB97_BEGIN_PRIMITIVE_ID 24:24 +#define NVCB97_BEGIN_PRIMITIVE_ID_FIRST 0x00000000 +#define NVCB97_BEGIN_PRIMITIVE_ID_UNCHANGED 0x00000001 +#define NVCB97_BEGIN_INSTANCE_ID 27:26 +#define NVCB97_BEGIN_INSTANCE_ID_FIRST 0x00000000 +#define NVCB97_BEGIN_INSTANCE_ID_SUBSEQUENT 0x00000001 +#define NVCB97_BEGIN_INSTANCE_ID_UNCHANGED 0x00000002 +#define NVCB97_BEGIN_SPLIT_MODE 30:29 +#define NVCB97_BEGIN_SPLIT_MODE_NORMAL_BEGIN_NORMAL_END 0x00000000 +#define NVCB97_BEGIN_SPLIT_MODE_NORMAL_BEGIN_OPEN_END 0x00000001 +#define NVCB97_BEGIN_SPLIT_MODE_OPEN_BEGIN_OPEN_END 0x00000002 +#define NVCB97_BEGIN_SPLIT_MODE_OPEN_BEGIN_NORMAL_END 0x00000003 +#define NVCB97_BEGIN_INSTANCE_ITERATE_ENABLE 31:31 +#define NVCB97_BEGIN_INSTANCE_ITERATE_ENABLE_FALSE 0x00000000 +#define NVCB97_BEGIN_INSTANCE_ITERATE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_VERTEX_ID_COPY 0x161c +#define NVCB97_SET_VERTEX_ID_COPY_ENABLE 0:0 +#define NVCB97_SET_VERTEX_ID_COPY_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_VERTEX_ID_COPY_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_VERTEX_ID_COPY_ATTRIBUTE_SLOT 11:4 + +#define NVCB97_ADD_TO_PRIMITIVE_ID 0x1620 +#define NVCB97_ADD_TO_PRIMITIVE_ID_V 31:0 + +#define NVCB97_LOAD_PRIMITIVE_ID 0x1624 +#define NVCB97_LOAD_PRIMITIVE_ID_V 31:0 + +#define NVCB97_SET_SHADER_BASED_CULL 0x162c +#define NVCB97_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE 1:1 +#define NVCB97_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SHADER_BASED_CULL_BATCH_CULL_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE 0:0 +#define NVCB97_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_SHADER_BASED_CULL_BEFORE_FETCH_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_CLASS_VERSION 0x1638 +#define NVCB97_SET_CLASS_VERSION_CURRENT 15:0 +#define NVCB97_SET_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVCB97_SET_DA_PRIMITIVE_RESTART 0x1644 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_ENABLE 0:0 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_DA_PRIMITIVE_RESTART_INDEX 0x1648 +#define NVCB97_SET_DA_PRIMITIVE_RESTART_INDEX_V 31:0 + +#define NVCB97_SET_DA_OUTPUT 0x164c +#define NVCB97_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START 12:12 +#define NVCB97_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_FALSE 0x00000000 +#define NVCB97_SET_DA_OUTPUT_VERTEX_ID_USES_ARRAY_START_TRUE 0x00000001 + +#define NVCB97_SET_ANTI_ALIASED_POINT 0x1658 +#define NVCB97_SET_ANTI_ALIASED_POINT_ENABLE 0:0 +#define NVCB97_SET_ANTI_ALIASED_POINT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ANTI_ALIASED_POINT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_POINT_CENTER_MODE 0x165c +#define NVCB97_SET_POINT_CENTER_MODE_V 31:0 +#define NVCB97_SET_POINT_CENTER_MODE_V_OGL 0x00000000 +#define NVCB97_SET_POINT_CENTER_MODE_V_D3D 0x00000001 + +#define NVCB97_SET_LINE_SMOOTH_PARAMETERS 0x1668 +#define NVCB97_SET_LINE_SMOOTH_PARAMETERS_FALLOFF 31:0 +#define NVCB97_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_00 0x00000000 +#define NVCB97_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_33 0x00000001 +#define NVCB97_SET_LINE_SMOOTH_PARAMETERS_FALLOFF__1_60 0x00000002 + +#define NVCB97_SET_LINE_STIPPLE 0x166c +#define NVCB97_SET_LINE_STIPPLE_ENABLE 0:0 +#define NVCB97_SET_LINE_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_LINE_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_LINE_SMOOTH_EDGE_TABLE(i) (0x1670+(i)*4) +#define NVCB97_SET_LINE_SMOOTH_EDGE_TABLE_V0 7:0 +#define NVCB97_SET_LINE_SMOOTH_EDGE_TABLE_V1 15:8 +#define NVCB97_SET_LINE_SMOOTH_EDGE_TABLE_V2 23:16 +#define NVCB97_SET_LINE_SMOOTH_EDGE_TABLE_V3 31:24 + +#define NVCB97_SET_LINE_STIPPLE_PARAMETERS 0x1680 +#define NVCB97_SET_LINE_STIPPLE_PARAMETERS_FACTOR 7:0 +#define NVCB97_SET_LINE_STIPPLE_PARAMETERS_PATTERN 23:8 + +#define NVCB97_SET_PROVOKING_VERTEX 0x1684 +#define NVCB97_SET_PROVOKING_VERTEX_V 0:0 +#define NVCB97_SET_PROVOKING_VERTEX_V_FIRST 0x00000000 +#define NVCB97_SET_PROVOKING_VERTEX_V_LAST 0x00000001 + +#define NVCB97_SET_TWO_SIDED_LIGHT 0x1688 +#define NVCB97_SET_TWO_SIDED_LIGHT_ENABLE 0:0 +#define NVCB97_SET_TWO_SIDED_LIGHT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_TWO_SIDED_LIGHT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_POLYGON_STIPPLE 0x168c +#define NVCB97_SET_POLYGON_STIPPLE_ENABLE 0:0 +#define NVCB97_SET_POLYGON_STIPPLE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_POLYGON_STIPPLE_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_SHADER_CONTROL 0x1690 +#define NVCB97_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVCB97_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVCB97_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NVCB97_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NVCB97_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVCB97_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVCB97_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NVCB97_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVCB97_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NVCB97_CHECK_CLASS_VERSION 0x16a0 +#define NVCB97_CHECK_CLASS_VERSION_CURRENT 15:0 +#define NVCB97_CHECK_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVCB97_SET_SPH_VERSION 0x16a4 +#define NVCB97_SET_SPH_VERSION_CURRENT 15:0 +#define NVCB97_SET_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVCB97_CHECK_SPH_VERSION 0x16a8 +#define NVCB97_CHECK_SPH_VERSION_CURRENT 15:0 +#define NVCB97_CHECK_SPH_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVCB97_SET_ALPHA_TO_COVERAGE_OVERRIDE 0x16b4 +#define NVCB97_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE 0:0 +#define NVCB97_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_DISABLE 0x00000000 +#define NVCB97_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE 0x00000001 +#define NVCB97_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT 1:1 +#define NVCB97_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_DISABLE 0x00000000 +#define NVCB97_SET_ALPHA_TO_COVERAGE_OVERRIDE_QUALIFY_BY_PS_SAMPLE_MASK_OUTPUT_ENABLE 0x00000001 + +#define NVCB97_SET_SCG_GRAPHICS_PRIORITY 0x16bc +#define NVCB97_SET_SCG_GRAPHICS_PRIORITY_PRIORITY 5:0 + +#define NVCB97_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS(i) (0x16c0+(i)*4) +#define NVCB97_SET_SCG_GRAPHICS_SCHEDULING_PARAMETERS_V 31:0 + +#define NVCB97_SET_POLYGON_STIPPLE_PATTERN(i) (0x1700+(i)*4) +#define NVCB97_SET_POLYGON_STIPPLE_PATTERN_V 31:0 + +#define NVCB97_SET_AAM_VERSION 0x1790 +#define NVCB97_SET_AAM_VERSION_CURRENT 15:0 +#define NVCB97_SET_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVCB97_CHECK_AAM_VERSION 0x1794 +#define NVCB97_CHECK_AAM_VERSION_CURRENT 15:0 +#define NVCB97_CHECK_AAM_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVCB97_SET_ZT_LAYER 0x179c +#define NVCB97_SET_ZT_LAYER_OFFSET 15:0 + +#define NVCB97_SET_INDEX_BUFFER_A 0x17c8 +#define NVCB97_SET_INDEX_BUFFER_A_ADDRESS_UPPER 7:0 + +#define NVCB97_SET_INDEX_BUFFER_B 0x17cc +#define NVCB97_SET_INDEX_BUFFER_B_ADDRESS_LOWER 31:0 + +#define NVCB97_SET_INDEX_BUFFER_E 0x17d8 +#define NVCB97_SET_INDEX_BUFFER_E_INDEX_SIZE 1:0 +#define NVCB97_SET_INDEX_BUFFER_E_INDEX_SIZE_ONE_BYTE 0x00000000 +#define NVCB97_SET_INDEX_BUFFER_E_INDEX_SIZE_TWO_BYTES 0x00000001 +#define NVCB97_SET_INDEX_BUFFER_E_INDEX_SIZE_FOUR_BYTES 0x00000002 + +#define NVCB97_SET_INDEX_BUFFER_F 0x17dc +#define NVCB97_SET_INDEX_BUFFER_F_FIRST 31:0 + +#define NVCB97_DRAW_INDEX_BUFFER 0x17e0 +#define NVCB97_DRAW_INDEX_BUFFER_COUNT 31:0 + +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST 0x17e4 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST 0x17e8 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST 0x17ec +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_FIRST 15:0 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_COUNT 27:16 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY 31:28 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINES 0x00000001 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_FIRST_TOPOLOGY_PATCH 0x0000000E + +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f0 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_DRAW_INDEX_BUFFER32_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f4 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_DRAW_INDEX_BUFFER16_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT 0x17f8 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_FIRST 15:0 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_COUNT 27:16 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY 31:28 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POINTS 0x00000000 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINES 0x00000001 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_LOOP 0x00000002 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINE_STRIP 0x00000003 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLES 0x00000004 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_STRIP 0x00000005 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLE_FAN 0x00000006 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUADS 0x00000007 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_QUAD_STRIP 0x00000008 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_POLYGON 0x00000009 +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINELIST_ADJCY 0x0000000A +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_DRAW_INDEX_BUFFER8_BEGIN_END_INSTANCE_SUBSEQUENT_TOPOLOGY_PATCH 0x0000000E + +#define NVCB97_SET_DEPTH_BIAS_CLAMP 0x187c +#define NVCB97_SET_DEPTH_BIAS_CLAMP_V 31:0 + +#define NVCB97_SET_VERTEX_STREAM_INSTANCE_A(i) (0x1880+(i)*4) +#define NVCB97_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED 0:0 +#define NVCB97_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_FALSE 0x00000000 +#define NVCB97_SET_VERTEX_STREAM_INSTANCE_A_IS_INSTANCED_TRUE 0x00000001 + +#define NVCB97_SET_VERTEX_STREAM_INSTANCE_B(i) (0x18c0+(i)*4) +#define NVCB97_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED 0:0 +#define NVCB97_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_FALSE 0x00000000 +#define NVCB97_SET_VERTEX_STREAM_INSTANCE_B_IS_INSTANCED_TRUE 0x00000001 + +#define NVCB97_SET_ATTRIBUTE_POINT_SIZE 0x1910 +#define NVCB97_SET_ATTRIBUTE_POINT_SIZE_ENABLE 0:0 +#define NVCB97_SET_ATTRIBUTE_POINT_SIZE_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ATTRIBUTE_POINT_SIZE_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ATTRIBUTE_POINT_SIZE_SLOT 11:4 + +#define NVCB97_OGL_SET_CULL 0x1918 +#define NVCB97_OGL_SET_CULL_ENABLE 0:0 +#define NVCB97_OGL_SET_CULL_ENABLE_FALSE 0x00000000 +#define NVCB97_OGL_SET_CULL_ENABLE_TRUE 0x00000001 + +#define NVCB97_OGL_SET_FRONT_FACE 0x191c +#define NVCB97_OGL_SET_FRONT_FACE_V 31:0 +#define NVCB97_OGL_SET_FRONT_FACE_V_CW 0x00000900 +#define NVCB97_OGL_SET_FRONT_FACE_V_CCW 0x00000901 + +#define NVCB97_OGL_SET_CULL_FACE 0x1920 +#define NVCB97_OGL_SET_CULL_FACE_V 31:0 +#define NVCB97_OGL_SET_CULL_FACE_V_FRONT 0x00000404 +#define NVCB97_OGL_SET_CULL_FACE_V_BACK 0x00000405 +#define NVCB97_OGL_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 + +#define NVCB97_SET_VIEWPORT_PIXEL 0x1924 +#define NVCB97_SET_VIEWPORT_PIXEL_CENTER 0:0 +#define NVCB97_SET_VIEWPORT_PIXEL_CENTER_AT_HALF_INTEGERS 0x00000000 +#define NVCB97_SET_VIEWPORT_PIXEL_CENTER_AT_INTEGERS 0x00000001 + +#define NVCB97_SET_VIEWPORT_SCALE_OFFSET 0x192c +#define NVCB97_SET_VIEWPORT_SCALE_OFFSET_ENABLE 0:0 +#define NVCB97_SET_VIEWPORT_SCALE_OFFSET_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_VIEWPORT_SCALE_OFFSET_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL 0x193c +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE 0:0 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_FALSE 0x00000000 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_MIN_Z_ZERO_MAX_Z_ONE_TRUE 0x00000001 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE 17:16 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_USE_FIELD_MIN_Z_ZERO_MAX_Z_ONE 0x00000000 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MIN_Z_MAX_Z 0x00000001 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_ZERO_ONE 0x00000002 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_Z_CLIP_RANGE_MINUS_INF_PLUS_INF 0x00000003 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z 3:3 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLIP 0x00000000 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MIN_Z_CLAMP 0x00000001 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z 4:4 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLIP 0x00000000 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_PIXEL_MAX_Z_CLAMP 0x00000001 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND 7:7 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_256 0x00000000 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_SCALE_1 0x00000001 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND 10:10 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_256 0x00000000 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_LINE_POINT_CULL_GUARDBAND_SCALE_1 0x00000001 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP 13:11 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP 0x00000000 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_PASSTHRU 0x00000001 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XY_CLIP 0x00000002 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_XYZ_CLIP 0x00000003 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_CLIP_NO_Z_CULL 0x00000004 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_FRUSTUM_Z_CLIP 0x00000005 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_CLIP_WZERO_TRI_FILL_OR_CLIP 0x00000006 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z 2:1 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SAME_AS_XY_GUARDBAND 0x00000000 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_256 0x00000001 +#define NVCB97_SET_VIEWPORT_CLIP_CONTROL_GEOMETRY_GUARDBAND_Z_SCALE_1 0x00000002 + +#define NVCB97_SET_USER_CLIP_OP 0x1940 +#define NVCB97_SET_USER_CLIP_OP_PLANE0 0:0 +#define NVCB97_SET_USER_CLIP_OP_PLANE0_CLIP 0x00000000 +#define NVCB97_SET_USER_CLIP_OP_PLANE0_CULL 0x00000001 +#define NVCB97_SET_USER_CLIP_OP_PLANE1 4:4 +#define NVCB97_SET_USER_CLIP_OP_PLANE1_CLIP 0x00000000 +#define NVCB97_SET_USER_CLIP_OP_PLANE1_CULL 0x00000001 +#define NVCB97_SET_USER_CLIP_OP_PLANE2 8:8 +#define NVCB97_SET_USER_CLIP_OP_PLANE2_CLIP 0x00000000 +#define NVCB97_SET_USER_CLIP_OP_PLANE2_CULL 0x00000001 +#define NVCB97_SET_USER_CLIP_OP_PLANE3 12:12 +#define NVCB97_SET_USER_CLIP_OP_PLANE3_CLIP 0x00000000 +#define NVCB97_SET_USER_CLIP_OP_PLANE3_CULL 0x00000001 +#define NVCB97_SET_USER_CLIP_OP_PLANE4 16:16 +#define NVCB97_SET_USER_CLIP_OP_PLANE4_CLIP 0x00000000 +#define NVCB97_SET_USER_CLIP_OP_PLANE4_CULL 0x00000001 +#define NVCB97_SET_USER_CLIP_OP_PLANE5 20:20 +#define NVCB97_SET_USER_CLIP_OP_PLANE5_CLIP 0x00000000 +#define NVCB97_SET_USER_CLIP_OP_PLANE5_CULL 0x00000001 +#define NVCB97_SET_USER_CLIP_OP_PLANE6 24:24 +#define NVCB97_SET_USER_CLIP_OP_PLANE6_CLIP 0x00000000 +#define NVCB97_SET_USER_CLIP_OP_PLANE6_CULL 0x00000001 +#define NVCB97_SET_USER_CLIP_OP_PLANE7 28:28 +#define NVCB97_SET_USER_CLIP_OP_PLANE7_CLIP 0x00000000 +#define NVCB97_SET_USER_CLIP_OP_PLANE7_CULL 0x00000001 + +#define NVCB97_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVCB97_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVCB97_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVCB97_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVCB97_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_CONTROL 0x1948 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE 0:0 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_TOPOLOGY_IN_BEGIN_METHODS 0x00000000 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_CONTROL_OVERRIDE_USE_SEPARATE_TOPOLOGY_STATE 0x00000001 + +#define NVCB97_SET_WINDOW_CLIP_ENABLE 0x194c +#define NVCB97_SET_WINDOW_CLIP_ENABLE_V 0:0 +#define NVCB97_SET_WINDOW_CLIP_ENABLE_V_FALSE 0x00000000 +#define NVCB97_SET_WINDOW_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NVCB97_SET_WINDOW_CLIP_TYPE 0x1950 +#define NVCB97_SET_WINDOW_CLIP_TYPE_V 1:0 +#define NVCB97_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 +#define NVCB97_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 +#define NVCB97_SET_WINDOW_CLIP_TYPE_V_CLIPALL 0x00000002 + +#define NVCB97_INVALIDATE_ZCULL 0x1958 +#define NVCB97_INVALIDATE_ZCULL_V 31:0 +#define NVCB97_INVALIDATE_ZCULL_V_INVALIDATE 0x00000000 + +#define NVCB97_SET_ZCULL 0x1968 +#define NVCB97_SET_ZCULL_Z_ENABLE 0:0 +#define NVCB97_SET_ZCULL_Z_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_Z_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_STENCIL_ENABLE 4:4 +#define NVCB97_SET_ZCULL_STENCIL_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_STENCIL_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_ZCULL_BOUNDS 0x196c +#define NVCB97_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE 0:0 +#define NVCB97_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_BOUNDS_Z_MIN_UNBOUNDED_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE 4:4 +#define NVCB97_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_ZCULL_BOUNDS_Z_MAX_UNBOUNDED_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_PRIMITIVE_TOPOLOGY 0x1970 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V 15:0 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_POINTLIST 0x00000001 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LINELIST 0x00000002 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP 0x00000003 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST 0x00000004 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP 0x00000005 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LINELIST_ADJCY 0x0000000A +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LINESTRIP_ADJCY 0x0000000B +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLELIST_ADJCY 0x0000000C +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_TRIANGLESTRIP_ADJCY 0x0000000D +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_PATCHLIST 0x0000000E +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_POINTS 0x00001001 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST 0x00001002 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST 0x00001003 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST 0x0000100F +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINESTRIP 0x00001010 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINESTRIP 0x00001011 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLELIST 0x00001012 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLESTRIP 0x00001013 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLESTRIP 0x00001014 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN 0x00001015 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLEFAN 0x00001016 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_TRIANGLEFAN_IMM 0x00001017 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_LINELIST_IMM 0x00001018 +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDTRIANGLELIST2 0x0000101A +#define NVCB97_SET_PRIMITIVE_TOPOLOGY_V_LEGACY_INDEXEDLINELIST2 0x0000101B + +#define NVCB97_ZCULL_SYNC 0x1978 +#define NVCB97_ZCULL_SYNC_V 31:0 + +#define NVCB97_SET_CLIP_ID_TEST 0x197c +#define NVCB97_SET_CLIP_ID_TEST_ENABLE 0:0 +#define NVCB97_SET_CLIP_ID_TEST_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_CLIP_ID_TEST_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_SURFACE_CLIP_ID_WIDTH 0x1980 +#define NVCB97_SET_SURFACE_CLIP_ID_WIDTH_V 31:0 + +#define NVCB97_SET_CLIP_ID 0x1984 +#define NVCB97_SET_CLIP_ID_V 31:0 + +#define NVCB97_SET_DEPTH_BOUNDS_TEST 0x19bc +#define NVCB97_SET_DEPTH_BOUNDS_TEST_ENABLE 0:0 +#define NVCB97_SET_DEPTH_BOUNDS_TEST_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_DEPTH_BOUNDS_TEST_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_BLEND_FLOAT_OPTION 0x19c0 +#define NVCB97_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO 0:0 +#define NVCB97_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NVCB97_SET_BLEND_FLOAT_OPTION_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NVCB97_SET_LOGIC_OP 0x19c4 +#define NVCB97_SET_LOGIC_OP_ENABLE 0:0 +#define NVCB97_SET_LOGIC_OP_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_LOGIC_OP_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_LOGIC_OP_FUNC 0x19c8 +#define NVCB97_SET_LOGIC_OP_FUNC_V 31:0 +#define NVCB97_SET_LOGIC_OP_FUNC_V_CLEAR 0x00001500 +#define NVCB97_SET_LOGIC_OP_FUNC_V_AND 0x00001501 +#define NVCB97_SET_LOGIC_OP_FUNC_V_AND_REVERSE 0x00001502 +#define NVCB97_SET_LOGIC_OP_FUNC_V_COPY 0x00001503 +#define NVCB97_SET_LOGIC_OP_FUNC_V_AND_INVERTED 0x00001504 +#define NVCB97_SET_LOGIC_OP_FUNC_V_NOOP 0x00001505 +#define NVCB97_SET_LOGIC_OP_FUNC_V_XOR 0x00001506 +#define NVCB97_SET_LOGIC_OP_FUNC_V_OR 0x00001507 +#define NVCB97_SET_LOGIC_OP_FUNC_V_NOR 0x00001508 +#define NVCB97_SET_LOGIC_OP_FUNC_V_EQUIV 0x00001509 +#define NVCB97_SET_LOGIC_OP_FUNC_V_INVERT 0x0000150A +#define NVCB97_SET_LOGIC_OP_FUNC_V_OR_REVERSE 0x0000150B +#define NVCB97_SET_LOGIC_OP_FUNC_V_COPY_INVERTED 0x0000150C +#define NVCB97_SET_LOGIC_OP_FUNC_V_OR_INVERTED 0x0000150D +#define NVCB97_SET_LOGIC_OP_FUNC_V_NAND 0x0000150E +#define NVCB97_SET_LOGIC_OP_FUNC_V_SET 0x0000150F + +#define NVCB97_SET_Z_COMPRESSION 0x19cc +#define NVCB97_SET_Z_COMPRESSION_ENABLE 0:0 +#define NVCB97_SET_Z_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_Z_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVCB97_CLEAR_SURFACE 0x19d0 +#define NVCB97_CLEAR_SURFACE_Z_ENABLE 0:0 +#define NVCB97_CLEAR_SURFACE_Z_ENABLE_FALSE 0x00000000 +#define NVCB97_CLEAR_SURFACE_Z_ENABLE_TRUE 0x00000001 +#define NVCB97_CLEAR_SURFACE_STENCIL_ENABLE 1:1 +#define NVCB97_CLEAR_SURFACE_STENCIL_ENABLE_FALSE 0x00000000 +#define NVCB97_CLEAR_SURFACE_STENCIL_ENABLE_TRUE 0x00000001 +#define NVCB97_CLEAR_SURFACE_R_ENABLE 2:2 +#define NVCB97_CLEAR_SURFACE_R_ENABLE_FALSE 0x00000000 +#define NVCB97_CLEAR_SURFACE_R_ENABLE_TRUE 0x00000001 +#define NVCB97_CLEAR_SURFACE_G_ENABLE 3:3 +#define NVCB97_CLEAR_SURFACE_G_ENABLE_FALSE 0x00000000 +#define NVCB97_CLEAR_SURFACE_G_ENABLE_TRUE 0x00000001 +#define NVCB97_CLEAR_SURFACE_B_ENABLE 4:4 +#define NVCB97_CLEAR_SURFACE_B_ENABLE_FALSE 0x00000000 +#define NVCB97_CLEAR_SURFACE_B_ENABLE_TRUE 0x00000001 +#define NVCB97_CLEAR_SURFACE_A_ENABLE 5:5 +#define NVCB97_CLEAR_SURFACE_A_ENABLE_FALSE 0x00000000 +#define NVCB97_CLEAR_SURFACE_A_ENABLE_TRUE 0x00000001 +#define NVCB97_CLEAR_SURFACE_MRT_SELECT 9:6 +#define NVCB97_CLEAR_SURFACE_RT_ARRAY_INDEX 25:10 + +#define NVCB97_CLEAR_CLIP_ID_SURFACE 0x19d4 +#define NVCB97_CLEAR_CLIP_ID_SURFACE_V 31:0 + +#define NVCB97_SET_COLOR_COMPRESSION(i) (0x19e0+(i)*4) +#define NVCB97_SET_COLOR_COMPRESSION_ENABLE 0:0 +#define NVCB97_SET_COLOR_COMPRESSION_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_COLOR_COMPRESSION_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_CT_WRITE(i) (0x1a00+(i)*4) +#define NVCB97_SET_CT_WRITE_R_ENABLE 0:0 +#define NVCB97_SET_CT_WRITE_R_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_CT_WRITE_R_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_CT_WRITE_G_ENABLE 4:4 +#define NVCB97_SET_CT_WRITE_G_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_CT_WRITE_G_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_CT_WRITE_B_ENABLE 8:8 +#define NVCB97_SET_CT_WRITE_B_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_CT_WRITE_B_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_CT_WRITE_A_ENABLE 12:12 +#define NVCB97_SET_CT_WRITE_A_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_CT_WRITE_A_ENABLE_TRUE 0x00000001 + +#define NVCB97_PIPE_NOP 0x1a2c +#define NVCB97_PIPE_NOP_V 31:0 + +#define NVCB97_SET_SPARE00 0x1a30 +#define NVCB97_SET_SPARE00_V 31:0 + +#define NVCB97_SET_SPARE01 0x1a34 +#define NVCB97_SET_SPARE01_V 31:0 + +#define NVCB97_SET_SPARE02 0x1a38 +#define NVCB97_SET_SPARE02_V 31:0 + +#define NVCB97_SET_SPARE03 0x1a3c +#define NVCB97_SET_SPARE03_V 31:0 + +#define NVCB97_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVCB97_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 24:0 + +#define NVCB97_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVCB97_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVCB97_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVCB97_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVCB97_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVCB97_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_OPERATION_ACQUIRE 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_OPERATION_REPORT_ONLY 0x00000002 +#define NVCB97_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVCB97_SET_REPORT_SEMAPHORE_D_RELEASE 4:4 +#define NVCB97_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_READS_COMPLETE 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_RELEASE_AFTER_ALL_PRECEEDING_WRITES_COMPLETE 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_ACQUIRE 8:8 +#define NVCB97_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_WRITES_START 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_ACQUIRE_BEFORE_ANY_FOLLOWING_READS_START 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 15:12 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_NONE 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DATA_ASSEMBLER 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VERTEX_SHADER 0x00000002 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_INIT_SHADER 0x00000008 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_TESSELATION_SHADER 0x00000009 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_GEOMETRY_SHADER 0x00000006 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_STREAMING_OUTPUT 0x00000005 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_VPC 0x00000004 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ZCULL 0x00000007 +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_PIXEL_SHADER 0x0000000A +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_DEPTH_TEST 0x0000000C +#define NVCB97_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_ALL 0x0000000F +#define NVCB97_SET_REPORT_SEMAPHORE_D_COMPARISON 16:16 +#define NVCB97_SET_REPORT_SEMAPHORE_D_COMPARISON_EQ 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_COMPARISON_GE 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVCB97_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT 27:23 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_NONE 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_VS_INVOCATIONS 0x00000005 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_TI_INVOCATIONS 0x0000001B +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_TS_INVOCATIONS 0x0000001D +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_GS_INVOCATIONS 0x00000007 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_SCG_CLOCKS 0x00000008 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_TOTAL_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x0000001E +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MINUS_SUCCEEDED 0x00000006 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS0 0x0000000A +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS1 0x0000000C +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS2 0x0000000E +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_ZCULL_STATS3 0x00000010 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_PS_INVOCATIONS 0x00000013 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_TILED_ZPASS_PIXEL_CNT64 0x00000017 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_BOUNDING_RECTANGLE 0x0000001C +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_TIMESTAMP 0x00000014 +#define NVCB97_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVCB97_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_SUB_REPORT 7:5 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REPORT_DWORD_NUMBER 21:21 +#define NVCB97_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVCB97_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVCB97_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVCB97_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVCB97_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVCB97_SET_VERTEX_STREAM_A_FORMAT(j) (0x1c00+(j)*16) +#define NVCB97_SET_VERTEX_STREAM_A_FORMAT_STRIDE 11:0 +#define NVCB97_SET_VERTEX_STREAM_A_FORMAT_ENABLE 12:12 +#define NVCB97_SET_VERTEX_STREAM_A_FORMAT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_VERTEX_STREAM_A_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_VERTEX_STREAM_A_LOCATION_A(j) (0x1c04+(j)*16) +#define NVCB97_SET_VERTEX_STREAM_A_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_VERTEX_STREAM_A_LOCATION_B(j) (0x1c08+(j)*16) +#define NVCB97_SET_VERTEX_STREAM_A_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_VERTEX_STREAM_A_FREQUENCY(j) (0x1c0c+(j)*16) +#define NVCB97_SET_VERTEX_STREAM_A_FREQUENCY_V 31:0 + +#define NVCB97_SET_VERTEX_STREAM_B_FORMAT(j) (0x1d00+(j)*16) +#define NVCB97_SET_VERTEX_STREAM_B_FORMAT_STRIDE 11:0 +#define NVCB97_SET_VERTEX_STREAM_B_FORMAT_ENABLE 12:12 +#define NVCB97_SET_VERTEX_STREAM_B_FORMAT_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_VERTEX_STREAM_B_FORMAT_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_VERTEX_STREAM_B_LOCATION_A(j) (0x1d04+(j)*16) +#define NVCB97_SET_VERTEX_STREAM_B_LOCATION_A_OFFSET_UPPER 7:0 + +#define NVCB97_SET_VERTEX_STREAM_B_LOCATION_B(j) (0x1d08+(j)*16) +#define NVCB97_SET_VERTEX_STREAM_B_LOCATION_B_OFFSET_LOWER 31:0 + +#define NVCB97_SET_VERTEX_STREAM_B_FREQUENCY(j) (0x1d0c+(j)*16) +#define NVCB97_SET_VERTEX_STREAM_B_FREQUENCY_V 31:0 + +#define NVCB97_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA(j) (0x1e00+(j)*32) +#define NVCB97_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE 0:0 +#define NVCB97_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_BLEND_PER_TARGET_SEPARATE_FOR_ALPHA_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP(j) (0x1e04+(j)*32) +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V 31:0 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MIN 0x00008007 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_OGL_MAX 0x00008008 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_ADD 0x00000001 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_SUBTRACT 0x00000002 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MIN 0x00000004 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_OP_V_D3D_MAX 0x00000005 + +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF(j) (0x1e08+(j)*32) +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V 31:0 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF(j) (0x1e0c+(j)*32) +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V 31:0 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVCB97_SET_BLEND_PER_TARGET_COLOR_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP(j) (0x1e10+(j)*32) +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V 31:0 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_SUBTRACT 0x0000800A +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_REVERSE_SUBTRACT 0x0000800B +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_FUNC_ADD 0x00008006 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MIN 0x00008007 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_OGL_MAX 0x00008008 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_ADD 0x00000001 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_SUBTRACT 0x00000002 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_REVSUBTRACT 0x00000003 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MIN 0x00000004 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_OP_V_D3D_MAX 0x00000005 + +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF(j) (0x1e14+(j)*32) +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V 31:0 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ZERO 0x00004000 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE 0x00004001 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ZERO 0x00000001 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_ONE 0x00000002 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHSRCALPHA 0x0000000C +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BOTHINVSRCALPHA 0x0000000D +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_SOURCE_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF(j) (0x1e18+(j)*32) +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V 31:0 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ZERO 0x00004000 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE 0x00004001 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_COLOR 0x00004300 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_COLOR 0x00004301 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA 0x00004302 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_SRC_ALPHA 0x00004303 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_ALPHA 0x00004304 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_ALPHA 0x00004305 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_DST_COLOR 0x00004306 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_DST_COLOR 0x00004307 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC_ALPHA_SATURATE 0x00004308 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_COLOR 0x0000C001 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_COLOR 0x0000C002 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_CONSTANT_ALPHA 0x0000C003 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_ONE_MINUS_CONSTANT_ALPHA 0x0000C004 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1COLOR 0x0000C900 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1COLOR 0x0000C901 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_SRC1ALPHA 0x0000C902 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_OGL_INVSRC1ALPHA 0x0000C903 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ZERO 0x00000001 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_ONE 0x00000002 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCCOLOR 0x00000003 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCCOLOR 0x00000004 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHA 0x00000005 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRCALPHA 0x00000006 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTALPHA 0x00000007 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTALPHA 0x00000008 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_DESTCOLOR 0x00000009 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVDESTCOLOR 0x0000000A +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRCALPHASAT 0x0000000B +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_BLENDFACTOR 0x0000000E +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVBLENDFACTOR 0x0000000F +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1COLOR 0x00000010 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1COLOR 0x00000011 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_SRC1ALPHA 0x00000012 +#define NVCB97_SET_BLEND_PER_TARGET_ALPHA_DEST_COEFF_V_D3D_INVSRC1ALPHA 0x00000013 + +#define NVCB97_SET_PIPELINE_SHADER(j) (0x2000+(j)*64) +#define NVCB97_SET_PIPELINE_SHADER_ENABLE 0:0 +#define NVCB97_SET_PIPELINE_SHADER_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_PIPELINE_SHADER_ENABLE_TRUE 0x00000001 +#define NVCB97_SET_PIPELINE_SHADER_TYPE 7:4 +#define NVCB97_SET_PIPELINE_SHADER_TYPE_VERTEX_CULL_BEFORE_FETCH 0x00000000 +#define NVCB97_SET_PIPELINE_SHADER_TYPE_VERTEX 0x00000001 +#define NVCB97_SET_PIPELINE_SHADER_TYPE_TESSELLATION_INIT 0x00000002 +#define NVCB97_SET_PIPELINE_SHADER_TYPE_TESSELLATION 0x00000003 +#define NVCB97_SET_PIPELINE_SHADER_TYPE_GEOMETRY 0x00000004 +#define NVCB97_SET_PIPELINE_SHADER_TYPE_PIXEL 0x00000005 + +#define NVCB97_SET_PIPELINE_RESERVED_B(j) (0x2004+(j)*64) +#define NVCB97_SET_PIPELINE_RESERVED_B_V 0:0 + +#define NVCB97_SET_PIPELINE_RESERVED_A(j) (0x2008+(j)*64) +#define NVCB97_SET_PIPELINE_RESERVED_A_V 0:0 + +#define NVCB97_SET_PIPELINE_REGISTER_COUNT(j) (0x200c+(j)*64) +#define NVCB97_SET_PIPELINE_REGISTER_COUNT_V 8:0 + +#define NVCB97_SET_PIPELINE_BINDING(j) (0x2010+(j)*64) +#define NVCB97_SET_PIPELINE_BINDING_GROUP 2:0 + +#define NVCB97_SET_PIPELINE_PROGRAM_ADDRESS_A(j) (0x2014+(j)*64) +#define NVCB97_SET_PIPELINE_PROGRAM_ADDRESS_A_UPPER 7:0 + +#define NVCB97_SET_PIPELINE_PROGRAM_ADDRESS_B(j) (0x2018+(j)*64) +#define NVCB97_SET_PIPELINE_PROGRAM_ADDRESS_B_LOWER 31:0 + +#define NVCB97_SET_PIPELINE_PROGRAM_PREFETCH(j) (0x201c+(j)*64) +#define NVCB97_SET_PIPELINE_PROGRAM_PREFETCH_SIZE_IN_BLOCKS 6:0 + +#define NVCB97_SET_PIPELINE_RESERVED_E(j) (0x2020+(j)*64) +#define NVCB97_SET_PIPELINE_RESERVED_E_V 0:0 + +#define NVCB97_SET_FALCON00 0x2300 +#define NVCB97_SET_FALCON00_V 31:0 + +#define NVCB97_SET_FALCON01 0x2304 +#define NVCB97_SET_FALCON01_V 31:0 + +#define NVCB97_SET_FALCON02 0x2308 +#define NVCB97_SET_FALCON02_V 31:0 + +#define NVCB97_SET_FALCON03 0x230c +#define NVCB97_SET_FALCON03_V 31:0 + +#define NVCB97_SET_FALCON04 0x2310 +#define NVCB97_SET_FALCON04_V 31:0 + +#define NVCB97_SET_FALCON05 0x2314 +#define NVCB97_SET_FALCON05_V 31:0 + +#define NVCB97_SET_FALCON06 0x2318 +#define NVCB97_SET_FALCON06_V 31:0 + +#define NVCB97_SET_FALCON07 0x231c +#define NVCB97_SET_FALCON07_V 31:0 + +#define NVCB97_SET_FALCON08 0x2320 +#define NVCB97_SET_FALCON08_V 31:0 + +#define NVCB97_SET_FALCON09 0x2324 +#define NVCB97_SET_FALCON09_V 31:0 + +#define NVCB97_SET_FALCON10 0x2328 +#define NVCB97_SET_FALCON10_V 31:0 + +#define NVCB97_SET_FALCON11 0x232c +#define NVCB97_SET_FALCON11_V 31:0 + +#define NVCB97_SET_FALCON12 0x2330 +#define NVCB97_SET_FALCON12_V 31:0 + +#define NVCB97_SET_FALCON13 0x2334 +#define NVCB97_SET_FALCON13_V 31:0 + +#define NVCB97_SET_FALCON14 0x2338 +#define NVCB97_SET_FALCON14_V 31:0 + +#define NVCB97_SET_FALCON15 0x233c +#define NVCB97_SET_FALCON15_V 31:0 + +#define NVCB97_SET_FALCON16 0x2340 +#define NVCB97_SET_FALCON16_V 31:0 + +#define NVCB97_SET_FALCON17 0x2344 +#define NVCB97_SET_FALCON17_V 31:0 + +#define NVCB97_SET_FALCON18 0x2348 +#define NVCB97_SET_FALCON18_V 31:0 + +#define NVCB97_SET_FALCON19 0x234c +#define NVCB97_SET_FALCON19_V 31:0 + +#define NVCB97_SET_FALCON20 0x2350 +#define NVCB97_SET_FALCON20_V 31:0 + +#define NVCB97_SET_FALCON21 0x2354 +#define NVCB97_SET_FALCON21_V 31:0 + +#define NVCB97_SET_FALCON22 0x2358 +#define NVCB97_SET_FALCON22_V 31:0 + +#define NVCB97_SET_FALCON23 0x235c +#define NVCB97_SET_FALCON23_V 31:0 + +#define NVCB97_SET_FALCON24 0x2360 +#define NVCB97_SET_FALCON24_V 31:0 + +#define NVCB97_SET_FALCON25 0x2364 +#define NVCB97_SET_FALCON25_V 31:0 + +#define NVCB97_SET_FALCON26 0x2368 +#define NVCB97_SET_FALCON26_V 31:0 + +#define NVCB97_SET_FALCON27 0x236c +#define NVCB97_SET_FALCON27_V 31:0 + +#define NVCB97_SET_FALCON28 0x2370 +#define NVCB97_SET_FALCON28_V 31:0 + +#define NVCB97_SET_FALCON29 0x2374 +#define NVCB97_SET_FALCON29_V 31:0 + +#define NVCB97_SET_FALCON30 0x2378 +#define NVCB97_SET_FALCON30_V 31:0 + +#define NVCB97_SET_FALCON31 0x237c +#define NVCB97_SET_FALCON31_V 31:0 + +#define NVCB97_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NVCB97_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NVCB97_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NVCB97_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NVCB97_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NVCB97_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NVCB97_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NVCB97_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NVCB97_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NVCB97_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NVCB97_BIND_GROUP_RESERVED_A(j) (0x2400+(j)*32) +#define NVCB97_BIND_GROUP_RESERVED_A_V 0:0 + +#define NVCB97_BIND_GROUP_RESERVED_B(j) (0x2404+(j)*32) +#define NVCB97_BIND_GROUP_RESERVED_B_V 0:0 + +#define NVCB97_BIND_GROUP_RESERVED_C(j) (0x2408+(j)*32) +#define NVCB97_BIND_GROUP_RESERVED_C_V 0:0 + +#define NVCB97_BIND_GROUP_RESERVED_D(j) (0x240c+(j)*32) +#define NVCB97_BIND_GROUP_RESERVED_D_V 0:0 + +#define NVCB97_BIND_GROUP_CONSTANT_BUFFER(j) (0x2410+(j)*32) +#define NVCB97_BIND_GROUP_CONSTANT_BUFFER_VALID 0:0 +#define NVCB97_BIND_GROUP_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVCB97_BIND_GROUP_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVCB97_BIND_GROUP_CONSTANT_BUFFER_SHADER_SLOT 8:4 + +#define NVCB97_SET_TRAP_HANDLER_A 0x25f8 +#define NVCB97_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVCB97_SET_TRAP_HANDLER_B 0x25fc +#define NVCB97_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVCB97_SET_COLOR_CLAMP 0x2600 +#define NVCB97_SET_COLOR_CLAMP_ENABLE 0:0 +#define NVCB97_SET_COLOR_CLAMP_ENABLE_FALSE 0x00000000 +#define NVCB97_SET_COLOR_CLAMP_ENABLE_TRUE 0x00000001 + +#define NVCB97_SET_STREAM_OUT_LAYOUT_SELECT(i,j) (0x2800+(i)*128+(j)*4) +#define NVCB97_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER00 7:0 +#define NVCB97_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER01 15:8 +#define NVCB97_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER02 23:16 +#define NVCB97_SET_STREAM_OUT_LAYOUT_SELECT_ATTRIBUTE_NUMBER03 31:24 + +#define NVCB97_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVCB97_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVCB97_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVCB97_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVCB97_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVCB97_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVCB97_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVCB97_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVCB97_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVCB97_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVCB97_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVCB97_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVCB97_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVCB97_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVCB97_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NVCB97_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NVCB97_CALL_MME_MACRO_V 31:0 + +#define NVCB97_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NVCB97_CALL_MME_DATA_V 31:0 + +#endif /* _cl_hopper_a_h_ */ diff --git a/src/common/sdk/nvidia/inc/class/clcb97tex.h b/src/common/sdk/nvidia/inc/class/clcb97tex.h new file mode 100644 index 000000000..f9871b787 --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/clcb97tex.h @@ -0,0 +1,2437 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLCB97TEX_H__ +#define __CLCB97TEX_H__ + +/* +** Texture Header State Blocklinear + */ + +#define NVCB97_TEXHEAD_BL_COMPONENTS MW(6:0) +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_BL_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_BL_R_DATA_TYPE MW(9:7) +#define NVCB97_TEXHEAD_BL_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_BL_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_BL_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_BL_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_BL_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_BL_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_BL_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BL_G_DATA_TYPE MW(12:10) +#define NVCB97_TEXHEAD_BL_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_BL_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_BL_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_BL_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_BL_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_BL_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_BL_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BL_B_DATA_TYPE MW(15:13) +#define NVCB97_TEXHEAD_BL_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_BL_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_BL_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_BL_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_BL_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_BL_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_BL_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BL_A_DATA_TYPE MW(18:16) +#define NVCB97_TEXHEAD_BL_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_BL_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_BL_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_BL_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_BL_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_BL_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_BL_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BL_X_SOURCE MW(21:19) +#define NVCB97_TEXHEAD_BL_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_BL_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_BL_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_BL_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_BL_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_BL_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_BL_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BL_Y_SOURCE MW(24:22) +#define NVCB97_TEXHEAD_BL_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_BL_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_BL_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_BL_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_BL_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_BL_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_BL_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BL_Z_SOURCE MW(27:25) +#define NVCB97_TEXHEAD_BL_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_BL_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_BL_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_BL_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_BL_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_BL_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_BL_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BL_W_SOURCE MW(30:28) +#define NVCB97_TEXHEAD_BL_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_BL_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_BL_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_BL_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_BL_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_BL_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_BL_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BL_PACK_COMPONENTS MW(31:31) +#define NVCB97_TEXHEAD_BL_RESERVED1Y MW(36:32) +#define NVCB97_TEXHEAD_BL_GOB_DEPTH_OFFSET MW(38:37) +#define NVCB97_TEXHEAD_BL_RESERVED1X MW(40:39) +#define NVCB97_TEXHEAD_BL_ADDRESS_BITS31TO9 MW(63:41) +#define NVCB97_TEXHEAD_BL_ADDRESS_BITS48TO32 MW(80:64) +#define NVCB97_TEXHEAD_BL_RESERVED_ADDRESS MW(84:81) +#define NVCB97_TEXHEAD_BL_HEADER_VERSION MW(87:85) +#define NVCB97_TEXHEAD_BL_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVCB97_TEXHEAD_BL_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVCB97_TEXHEAD_BL_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVCB97_TEXHEAD_BL_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVCB97_TEXHEAD_BL_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVCB97_TEXHEAD_BL_RESERVED_HEADER_VERSION MW(88:88) +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_0 0x00000000 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_1 0x00000001 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_2 0x00000002 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_3 0x00000003 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_4 0x00000004 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_5 0x00000005 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_6 0x00000006 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_7 0x00000007 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_8 0x00000008 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_9 0x00000009 +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_10 0x0000000a +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_11 0x0000000b +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_12 0x0000000c +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_13 0x0000000d +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_14 0x0000000e +#define NVCB97_TEXHEAD_BL_RESOURCE_VIEW_COHERENCY_HASH_HASH_UNALIASED 0x0000000f +#define NVCB97_TEXHEAD_BL_RESERVED2A MW(95:93) +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_WIDTH MW(98:96) +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT MW(101:99) +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH MW(104:102) +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_BL_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_BL_RESERVED3Y MW(105:105) +#define NVCB97_TEXHEAD_BL_TILE_WIDTH_IN_GOBS MW(108:106) +#define NVCB97_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_BL_TILE_WIDTH_IN_GOBS_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_BL_GOB3D MW(109:109) +#define NVCB97_TEXHEAD_BL_RESERVED3Z MW(111:110) +#define NVCB97_TEXHEAD_BL_LOD_ANISO_QUALITY2 MW(112:112) +#define NVCB97_TEXHEAD_BL_LOD_ANISO_QUALITY MW(113:113) +#define NVCB97_TEXHEAD_BL_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_BL_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_BL_LOD_ISO_QUALITY MW(114:114) +#define NVCB97_TEXHEAD_BL_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_BL_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_BL_ANISO_SPREAD_SCALE MW(121:117) +#define NVCB97_TEXHEAD_BL_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVCB97_TEXHEAD_BL_DEPTH_TEXTURE MW(123:123) +#define NVCB97_TEXHEAD_BL_MAX_MIP_LEVEL MW(127:124) +#define NVCB97_TEXHEAD_BL_WIDTH_MINUS_ONE MW(144:128) +#define NVCB97_TEXHEAD_BL_DEPTH_MINUS_ONE_BIT14 MW(145:145) +#define NVCB97_TEXHEAD_BL_HEIGHT_MINUS_ONE_BIT16 MW(146:146) +#define NVCB97_TEXHEAD_BL_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVCB97_TEXHEAD_BL_S_R_G_B_CONVERSION MW(150:150) +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE MW(154:151) +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_BL_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_BL_SECTOR_PROMOTION MW(156:155) +#define NVCB97_TEXHEAD_BL_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_BL_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_BL_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_BL_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_BL_BORDER_SIZE MW(159:157) +#define NVCB97_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVCB97_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVCB97_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVCB97_TEXHEAD_BL_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVCB97_TEXHEAD_BL_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVCB97_TEXHEAD_BL_HEIGHT_MINUS_ONE MW(175:160) +#define NVCB97_TEXHEAD_BL_DEPTH_MINUS_ONE MW(189:176) +#define NVCB97_TEXHEAD_BL_RESERVED5A MW(190:190) +#define NVCB97_TEXHEAD_BL_NORMALIZED_COORDS MW(191:191) +#define NVCB97_TEXHEAD_BL_RESERVED6Y MW(192:192) +#define NVCB97_TEXHEAD_BL_TRILIN_OPT MW(197:193) +#define NVCB97_TEXHEAD_BL_MIP_LOD_BIAS MW(210:198) +#define NVCB97_TEXHEAD_BL_ANISO_BIAS MW(214:211) +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY MW(221:219) +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXHEAD_BL_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_BL_RES_VIEW_MIN_MIP_LEVEL MW(227:224) +#define NVCB97_TEXHEAD_BL_RES_VIEW_MAX_MIP_LEVEL MW(231:228) +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT MW(235:232) +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVCB97_TEXHEAD_BL_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVCB97_TEXHEAD_BL_MIN_LOD_CLAMP MW(247:236) +#define NVCB97_TEXHEAD_BL_RESERVED7Y MW(255:248) + + +/* +** Texture Header State Blocklinear Color Key + */ + +#define NVCB97_TEXHEAD_BLCK_COMPONENTS MW(6:0) +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_BLCK_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_BLCK_R_DATA_TYPE MW(9:7) +#define NVCB97_TEXHEAD_BLCK_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_BLCK_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_BLCK_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_BLCK_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_BLCK_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_BLCK_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_BLCK_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BLCK_G_DATA_TYPE MW(12:10) +#define NVCB97_TEXHEAD_BLCK_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_BLCK_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_BLCK_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_BLCK_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_BLCK_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_BLCK_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_BLCK_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BLCK_B_DATA_TYPE MW(15:13) +#define NVCB97_TEXHEAD_BLCK_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_BLCK_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_BLCK_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_BLCK_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_BLCK_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_BLCK_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_BLCK_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BLCK_A_DATA_TYPE MW(18:16) +#define NVCB97_TEXHEAD_BLCK_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_BLCK_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_BLCK_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_BLCK_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_BLCK_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_BLCK_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_BLCK_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BLCK_X_SOURCE MW(21:19) +#define NVCB97_TEXHEAD_BLCK_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_BLCK_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_BLCK_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_BLCK_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_BLCK_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_BLCK_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_BLCK_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BLCK_Y_SOURCE MW(24:22) +#define NVCB97_TEXHEAD_BLCK_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_BLCK_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_BLCK_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_BLCK_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_BLCK_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_BLCK_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_BLCK_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BLCK_Z_SOURCE MW(27:25) +#define NVCB97_TEXHEAD_BLCK_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_BLCK_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_BLCK_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_BLCK_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_BLCK_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_BLCK_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_BLCK_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BLCK_W_SOURCE MW(30:28) +#define NVCB97_TEXHEAD_BLCK_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_BLCK_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_BLCK_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_BLCK_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_BLCK_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_BLCK_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_BLCK_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_BLCK_PACK_COMPONENTS MW(31:31) +#define NVCB97_TEXHEAD_BLCK_RESERVED1Y MW(36:32) +#define NVCB97_TEXHEAD_BLCK_GOB_DEPTH_OFFSET MW(38:37) +#define NVCB97_TEXHEAD_BLCK_RESERVED1X MW(40:39) +#define NVCB97_TEXHEAD_BLCK_ADDRESS_BITS31TO9 MW(63:41) +#define NVCB97_TEXHEAD_BLCK_ADDRESS_BITS48TO32 MW(80:64) +#define NVCB97_TEXHEAD_BLCK_RESERVED_ADDRESS MW(84:81) +#define NVCB97_TEXHEAD_BLCK_HEADER_VERSION MW(87:85) +#define NVCB97_TEXHEAD_BLCK_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVCB97_TEXHEAD_BLCK_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVCB97_TEXHEAD_BLCK_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVCB97_TEXHEAD_BLCK_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVCB97_TEXHEAD_BLCK_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVCB97_TEXHEAD_BLCK_RESERVED_HEADER_VERSION MW(88:88) +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_0 0x00000000 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_1 0x00000001 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_2 0x00000002 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_3 0x00000003 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_4 0x00000004 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_5 0x00000005 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_6 0x00000006 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_7 0x00000007 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_8 0x00000008 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_9 0x00000009 +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_10 0x0000000a +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_11 0x0000000b +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_12 0x0000000c +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_13 0x0000000d +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_14 0x0000000e +#define NVCB97_TEXHEAD_BLCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_UNALIASED 0x0000000f +#define NVCB97_TEXHEAD_BLCK_RESERVED2A MW(95:93) +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_WIDTH MW(98:96) +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT MW(101:99) +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH MW(104:102) +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_BLCK_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_BLCK_RESERVED3Y MW(105:105) +#define NVCB97_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS MW(108:106) +#define NVCB97_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_BLCK_TILE_WIDTH_IN_GOBS_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_BLCK_GOB3D MW(109:109) +#define NVCB97_TEXHEAD_BLCK_RESERVED3Z MW(111:110) +#define NVCB97_TEXHEAD_BLCK_LOD_ANISO_QUALITY2 MW(112:112) +#define NVCB97_TEXHEAD_BLCK_LOD_ANISO_QUALITY MW(113:113) +#define NVCB97_TEXHEAD_BLCK_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_BLCK_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_BLCK_LOD_ISO_QUALITY MW(114:114) +#define NVCB97_TEXHEAD_BLCK_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_BLCK_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_BLCK_ANISO_SPREAD_SCALE MW(121:117) +#define NVCB97_TEXHEAD_BLCK_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVCB97_TEXHEAD_BLCK_DEPTH_TEXTURE MW(123:123) +#define NVCB97_TEXHEAD_BLCK_MAX_MIP_LEVEL MW(127:124) +#define NVCB97_TEXHEAD_BLCK_WIDTH_MINUS_ONE MW(144:128) +#define NVCB97_TEXHEAD_BLCK_DEPTH_MINUS_ONE_BIT14 MW(145:145) +#define NVCB97_TEXHEAD_BLCK_HEIGHT_MINUS_ONE_BIT16 MW(146:146) +#define NVCB97_TEXHEAD_BLCK_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVCB97_TEXHEAD_BLCK_S_R_G_B_CONVERSION MW(150:150) +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE MW(154:151) +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_BLCK_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_BLCK_SECTOR_PROMOTION MW(156:155) +#define NVCB97_TEXHEAD_BLCK_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_BLCK_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_BLCK_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_BLCK_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_BLCK_BORDER_SIZE MW(159:157) +#define NVCB97_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVCB97_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVCB97_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVCB97_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVCB97_TEXHEAD_BLCK_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVCB97_TEXHEAD_BLCK_HEIGHT_MINUS_ONE MW(175:160) +#define NVCB97_TEXHEAD_BLCK_DEPTH_MINUS_ONE MW(189:176) +#define NVCB97_TEXHEAD_BLCK_RESERVED5A MW(190:190) +#define NVCB97_TEXHEAD_BLCK_NORMALIZED_COORDS MW(191:191) +#define NVCB97_TEXHEAD_BLCK_COLOR_KEY_OP MW(192:192) +#define NVCB97_TEXHEAD_BLCK_TRILIN_OPT MW(197:193) +#define NVCB97_TEXHEAD_BLCK_MIP_LOD_BIAS MW(210:198) +#define NVCB97_TEXHEAD_BLCK_ANISO_BIAS MW(214:211) +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY MW(221:219) +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXHEAD_BLCK_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_BLCK_COLOR_KEY_VALUE MW(255:224) + + +/* +** Texture Header State One-D Buffer + */ + +#define NVCB97_TEXHEAD_1D_COMPONENTS MW(6:0) +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_1D_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_1D_R_DATA_TYPE MW(9:7) +#define NVCB97_TEXHEAD_1D_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_1D_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_1D_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_1D_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_1D_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_1D_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_1D_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_1D_G_DATA_TYPE MW(12:10) +#define NVCB97_TEXHEAD_1D_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_1D_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_1D_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_1D_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_1D_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_1D_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_1D_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_1D_B_DATA_TYPE MW(15:13) +#define NVCB97_TEXHEAD_1D_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_1D_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_1D_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_1D_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_1D_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_1D_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_1D_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_1D_A_DATA_TYPE MW(18:16) +#define NVCB97_TEXHEAD_1D_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_1D_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_1D_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_1D_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_1D_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_1D_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_1D_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_1D_X_SOURCE MW(21:19) +#define NVCB97_TEXHEAD_1D_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_1D_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_1D_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_1D_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_1D_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_1D_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_1D_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_1D_Y_SOURCE MW(24:22) +#define NVCB97_TEXHEAD_1D_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_1D_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_1D_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_1D_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_1D_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_1D_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_1D_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_1D_Z_SOURCE MW(27:25) +#define NVCB97_TEXHEAD_1D_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_1D_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_1D_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_1D_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_1D_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_1D_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_1D_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_1D_W_SOURCE MW(30:28) +#define NVCB97_TEXHEAD_1D_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_1D_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_1D_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_1D_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_1D_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_1D_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_1D_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_1D_PACK_COMPONENTS MW(31:31) +#define NVCB97_TEXHEAD_1D_ADDRESS_BITS31TO0 MW(63:32) +#define NVCB97_TEXHEAD_1D_ADDRESS_BITS48TO32 MW(80:64) +#define NVCB97_TEXHEAD_1D_RESERVED_ADDRESS MW(84:81) +#define NVCB97_TEXHEAD_1D_HEADER_VERSION MW(87:85) +#define NVCB97_TEXHEAD_1D_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVCB97_TEXHEAD_1D_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVCB97_TEXHEAD_1D_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVCB97_TEXHEAD_1D_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVCB97_TEXHEAD_1D_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVCB97_TEXHEAD_1D_RESERVED_HEADER_VERSION MW(88:88) +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_0 0x00000000 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_1 0x00000001 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_2 0x00000002 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_3 0x00000003 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_4 0x00000004 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_5 0x00000005 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_6 0x00000006 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_7 0x00000007 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_8 0x00000008 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_9 0x00000009 +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_10 0x0000000a +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_11 0x0000000b +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_12 0x0000000c +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_13 0x0000000d +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_14 0x0000000e +#define NVCB97_TEXHEAD_1D_RESOURCE_VIEW_COHERENCY_HASH_HASH_UNALIASED 0x0000000f +#define NVCB97_TEXHEAD_1D_RESERVED2A MW(95:93) +#define NVCB97_TEXHEAD_1D_WIDTH_MINUS_ONE_BITS31TO16 MW(111:96) +#define NVCB97_TEXHEAD_1D_RESERVED3X MW(127:112) +#define NVCB97_TEXHEAD_1D_WIDTH_MINUS_ONE_BITS15TO0 MW(143:128) +#define NVCB97_TEXHEAD_1D_RESERVED4X MW(149:144) +#define NVCB97_TEXHEAD_1D_S_R_G_B_CONVERSION MW(150:150) +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE MW(154:151) +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_1D_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_1D_SECTOR_PROMOTION MW(156:155) +#define NVCB97_TEXHEAD_1D_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_1D_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_1D_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_1D_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_1D_RESERVED4Y MW(159:157) +#define NVCB97_TEXHEAD_1D_RESERVED5X MW(189:160) +#define NVCB97_TEXHEAD_1D_RESERVED5A MW(190:190) +#define NVCB97_TEXHEAD_1D_RESERVED5Y MW(191:191) +#define NVCB97_TEXHEAD_1D_RESERVED6X MW(223:192) +#define NVCB97_TEXHEAD_1D_RESERVED7X MW(255:224) + + +/* +** Texture Header State Pitch + */ + +#define NVCB97_TEXHEAD_PITCH_COMPONENTS MW(6:0) +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_PITCH_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_PITCH_R_DATA_TYPE MW(9:7) +#define NVCB97_TEXHEAD_PITCH_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_PITCH_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_PITCH_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_PITCH_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_PITCH_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_PITCH_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_PITCH_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCH_G_DATA_TYPE MW(12:10) +#define NVCB97_TEXHEAD_PITCH_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_PITCH_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_PITCH_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_PITCH_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_PITCH_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_PITCH_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_PITCH_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCH_B_DATA_TYPE MW(15:13) +#define NVCB97_TEXHEAD_PITCH_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_PITCH_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_PITCH_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_PITCH_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_PITCH_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_PITCH_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_PITCH_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCH_A_DATA_TYPE MW(18:16) +#define NVCB97_TEXHEAD_PITCH_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_PITCH_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_PITCH_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_PITCH_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_PITCH_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_PITCH_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_PITCH_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCH_X_SOURCE MW(21:19) +#define NVCB97_TEXHEAD_PITCH_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_PITCH_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_PITCH_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_PITCH_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_PITCH_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_PITCH_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_PITCH_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCH_Y_SOURCE MW(24:22) +#define NVCB97_TEXHEAD_PITCH_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_PITCH_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_PITCH_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_PITCH_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_PITCH_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_PITCH_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_PITCH_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCH_Z_SOURCE MW(27:25) +#define NVCB97_TEXHEAD_PITCH_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_PITCH_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_PITCH_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_PITCH_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_PITCH_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_PITCH_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_PITCH_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCH_W_SOURCE MW(30:28) +#define NVCB97_TEXHEAD_PITCH_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_PITCH_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_PITCH_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_PITCH_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_PITCH_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_PITCH_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_PITCH_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCH_PACK_COMPONENTS MW(31:31) +#define NVCB97_TEXHEAD_PITCH_RESERVED1A MW(36:32) +#define NVCB97_TEXHEAD_PITCH_ADDRESS_BITS31TO5 MW(63:37) +#define NVCB97_TEXHEAD_PITCH_ADDRESS_BITS48TO32 MW(80:64) +#define NVCB97_TEXHEAD_PITCH_RESERVED_ADDRESS MW(84:81) +#define NVCB97_TEXHEAD_PITCH_HEADER_VERSION MW(87:85) +#define NVCB97_TEXHEAD_PITCH_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVCB97_TEXHEAD_PITCH_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVCB97_TEXHEAD_PITCH_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVCB97_TEXHEAD_PITCH_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVCB97_TEXHEAD_PITCH_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVCB97_TEXHEAD_PITCH_RESERVED_HEADER_VERSION MW(88:88) +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_0 0x00000000 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_1 0x00000001 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_2 0x00000002 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_3 0x00000003 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_4 0x00000004 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_5 0x00000005 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_6 0x00000006 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_7 0x00000007 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_8 0x00000008 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_9 0x00000009 +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_10 0x0000000a +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_11 0x0000000b +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_12 0x0000000c +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_13 0x0000000d +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_14 0x0000000e +#define NVCB97_TEXHEAD_PITCH_RESOURCE_VIEW_COHERENCY_HASH_HASH_UNALIASED 0x0000000f +#define NVCB97_TEXHEAD_PITCH_RESERVED2A MW(95:93) +#define NVCB97_TEXHEAD_PITCH_PITCH_BITS20TO5 MW(111:96) +#define NVCB97_TEXHEAD_PITCH_LOD_ANISO_QUALITY2 MW(112:112) +#define NVCB97_TEXHEAD_PITCH_LOD_ANISO_QUALITY MW(113:113) +#define NVCB97_TEXHEAD_PITCH_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_PITCH_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_PITCH_LOD_ISO_QUALITY MW(114:114) +#define NVCB97_TEXHEAD_PITCH_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_PITCH_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_PITCH_ANISO_SPREAD_SCALE MW(121:117) +#define NVCB97_TEXHEAD_PITCH_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVCB97_TEXHEAD_PITCH_DEPTH_TEXTURE MW(123:123) +#define NVCB97_TEXHEAD_PITCH_MAX_MIP_LEVEL MW(127:124) +#define NVCB97_TEXHEAD_PITCH_WIDTH_MINUS_ONE MW(144:128) +#define NVCB97_TEXHEAD_PITCH_PITCH_BIT21 MW(145:145) +#define NVCB97_TEXHEAD_PITCH_HEIGHT_MINUS_ONE_BIT16 MW(146:146) +#define NVCB97_TEXHEAD_PITCH_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVCB97_TEXHEAD_PITCH_S_R_G_B_CONVERSION MW(150:150) +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE MW(154:151) +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_PITCH_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_PITCH_SECTOR_PROMOTION MW(156:155) +#define NVCB97_TEXHEAD_PITCH_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_PITCH_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_PITCH_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_PITCH_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_PITCH_BORDER_SIZE MW(159:157) +#define NVCB97_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVCB97_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVCB97_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVCB97_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVCB97_TEXHEAD_PITCH_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVCB97_TEXHEAD_PITCH_HEIGHT_MINUS_ONE MW(175:160) +#define NVCB97_TEXHEAD_PITCH_DEPTH_MINUS_ONE MW(189:176) +#define NVCB97_TEXHEAD_PITCH_RESERVED5A MW(190:190) +#define NVCB97_TEXHEAD_PITCH_NORMALIZED_COORDS MW(191:191) +#define NVCB97_TEXHEAD_PITCH_RESERVED6Y MW(192:192) +#define NVCB97_TEXHEAD_PITCH_TRILIN_OPT MW(197:193) +#define NVCB97_TEXHEAD_PITCH_MIP_LOD_BIAS MW(210:198) +#define NVCB97_TEXHEAD_PITCH_ANISO_BIAS MW(214:211) +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY MW(221:219) +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXHEAD_PITCH_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_PITCH_RES_VIEW_MIN_MIP_LEVEL MW(227:224) +#define NVCB97_TEXHEAD_PITCH_RES_VIEW_MAX_MIP_LEVEL MW(231:228) +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT MW(235:232) +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVCB97_TEXHEAD_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVCB97_TEXHEAD_PITCH_MIN_LOD_CLAMP MW(247:236) +#define NVCB97_TEXHEAD_PITCH_RESERVED7Y MW(255:248) + + +/* +** Texture Header State Pitch Color Key + */ + +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS MW(6:0) +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_PITCHCK_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_PITCHCK_R_DATA_TYPE MW(9:7) +#define NVCB97_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_R_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_G_DATA_TYPE MW(12:10) +#define NVCB97_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_G_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_B_DATA_TYPE MW(15:13) +#define NVCB97_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_B_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_A_DATA_TYPE MW(18:16) +#define NVCB97_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_SNORM 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_UNORM 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_SINT 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_UINT 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_SNORM_FORCE_FP16 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_UNORM_FORCE_FP16 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_A_DATA_TYPE_NUM_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_X_SOURCE MW(21:19) +#define NVCB97_TEXHEAD_PITCHCK_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_Y_SOURCE MW(24:22) +#define NVCB97_TEXHEAD_PITCHCK_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_Z_SOURCE MW(27:25) +#define NVCB97_TEXHEAD_PITCHCK_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_W_SOURCE MW(30:28) +#define NVCB97_TEXHEAD_PITCHCK_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_PACK_COMPONENTS MW(31:31) +#define NVCB97_TEXHEAD_PITCHCK_RESERVED1A MW(36:32) +#define NVCB97_TEXHEAD_PITCHCK_ADDRESS_BITS31TO5 MW(63:37) +#define NVCB97_TEXHEAD_PITCHCK_ADDRESS_BITS48TO32 MW(80:64) +#define NVCB97_TEXHEAD_PITCHCK_RESERVED_ADDRESS MW(84:81) +#define NVCB97_TEXHEAD_PITCHCK_HEADER_VERSION MW(87:85) +#define NVCB97_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_ONE_D_BUFFER 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_PITCH_COLOR_KEY 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_PITCH 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_BLOCKLINEAR 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_RESERVED_HEADER_VERSION MW(88:88) +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH MW(92:89) +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_0 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_1 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_2 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_3 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_4 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_5 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_6 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_7 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_8 0x00000008 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_9 0x00000009 +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_10 0x0000000a +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_11 0x0000000b +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_12 0x0000000c +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_13 0x0000000d +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_ALIASED_14 0x0000000e +#define NVCB97_TEXHEAD_PITCHCK_RESOURCE_VIEW_COHERENCY_HASH_HASH_UNALIASED 0x0000000f +#define NVCB97_TEXHEAD_PITCHCK_RESERVED2A MW(95:93) +#define NVCB97_TEXHEAD_PITCHCK_PITCH_BITS20TO5 MW(111:96) +#define NVCB97_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY2 MW(112:112) +#define NVCB97_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY MW(113:113) +#define NVCB97_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_LOD_ISO_QUALITY MW(114:114) +#define NVCB97_TEXHEAD_PITCHCK_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER MW(116:115) +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_SPREAD_SCALE MW(121:117) +#define NVCB97_TEXHEAD_PITCHCK_USE_HEADER_OPT_CONTROL MW(122:122) +#define NVCB97_TEXHEAD_PITCHCK_DEPTH_TEXTURE MW(123:123) +#define NVCB97_TEXHEAD_PITCHCK_MAX_MIP_LEVEL MW(127:124) +#define NVCB97_TEXHEAD_PITCHCK_WIDTH_MINUS_ONE MW(144:128) +#define NVCB97_TEXHEAD_PITCHCK_PITCH_BIT21 MW(145:145) +#define NVCB97_TEXHEAD_PITCHCK_HEIGHT_MINUS_ONE_BIT16 MW(146:146) +#define NVCB97_TEXHEAD_PITCHCK_ANISO_SPREAD_MAX_LOG2 MW(149:147) +#define NVCB97_TEXHEAD_PITCHCK_S_R_G_B_CONVERSION MW(150:150) +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE MW(154:151) +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_PITCHCK_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_PITCHCK_SECTOR_PROMOTION MW(156:155) +#define NVCB97_TEXHEAD_PITCHCK_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_BORDER_SIZE MW(159:157) +#define NVCB97_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_ONE 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_TWO 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_FOUR 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SIZE_EIGHT 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_BORDER_SIZE_BORDER_SAMPLER_COLOR 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_HEIGHT_MINUS_ONE MW(175:160) +#define NVCB97_TEXHEAD_PITCHCK_DEPTH_MINUS_ONE MW(189:176) +#define NVCB97_TEXHEAD_PITCHCK_RESERVED5A MW(190:190) +#define NVCB97_TEXHEAD_PITCHCK_NORMALIZED_COORDS MW(191:191) +#define NVCB97_TEXHEAD_PITCHCK_COLOR_KEY_OP MW(192:192) +#define NVCB97_TEXHEAD_PITCHCK_TRILIN_OPT MW(197:193) +#define NVCB97_TEXHEAD_PITCHCK_MIP_LOD_BIAS MW(210:198) +#define NVCB97_TEXHEAD_PITCHCK_ANISO_BIAS MW(214:211) +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY MW(221:219) +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXHEAD_PITCHCK_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_PITCHCK_COLOR_KEY_VALUE MW(255:224) + + +/* +** Texture Header V2 Blocklinear + */ + +#define NVCB97_TEXHEAD_V2_BL_RESERVED0A MW(3:0) +#define NVCB97_TEXHEAD_V2_BL_GOB_DEPTH_OFFSET MW(8:4) +#define NVCB97_TEXHEAD_V2_BL_ADDRESS_BITS31TO9 MW(31:9) +#define NVCB97_TEXHEAD_V2_BL_ADDRESS_BITS56TO32 MW(56:32) +#define NVCB97_TEXHEAD_V2_BL_RESERVED1A MW(63:57) +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_WIDTH MW(66:64) +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_HEIGHT MW(69:67) +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_DEPTH MW(72:70) +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_RESERVED3Y MW(73:73) +#define NVCB97_TEXHEAD_V2_BL_TILE_WIDTH_IN_GOBS MW(76:74) +#define NVCB97_TEXHEAD_V2_BL_TILE_WIDTH_IN_GOBS_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_TILE_WIDTH_IN_GOBS_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_TILE_WIDTH_IN_GOBS_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_TILE_WIDTH_IN_GOBS_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_TILE_WIDTH_IN_GOBS_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_TILE_WIDTH_IN_GOBS_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_GOB3D MW(77:77) +#define NVCB97_TEXHEAD_V2_BL_RESERVED2Z MW(79:78) +#define NVCB97_TEXHEAD_V2_BL_LOD_ANISO_QUALITY2 MW(80:80) +#define NVCB97_TEXHEAD_V2_BL_LOD_ANISO_QUALITY MW(81:81) +#define NVCB97_TEXHEAD_V2_BL_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_LOD_ISO_QUALITY MW(82:82) +#define NVCB97_TEXHEAD_V2_BL_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_MODIFIER MW(84:83) +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_ANISO_SPREAD_SCALE MW(89:85) +#define NVCB97_TEXHEAD_V2_BL_USE_HEADER_OPT_CONTROL MW(90:90) +#define NVCB97_TEXHEAD_V2_BL_DEPTH_TEXTURE MW(91:91) +#define NVCB97_TEXHEAD_V2_BL_MAX_MIP_LEVEL MW(95:92) +#define NVCB97_TEXHEAD_V2_BL_X_SOURCE MW(98:96) +#define NVCB97_TEXHEAD_V2_BL_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_BL_Y_SOURCE MW(101:99) +#define NVCB97_TEXHEAD_V2_BL_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_BL_Z_SOURCE MW(104:102) +#define NVCB97_TEXHEAD_V2_BL_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_BL_W_SOURCE MW(107:105) +#define NVCB97_TEXHEAD_V2_BL_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE MW(111:108) +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_UNORM 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_SNORM 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_FLOAT 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_SGNRGB 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_SGNA 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_DSDT 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_UINT 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_SINT 0x00000007 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_ZS 0x00000008 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_SZ 0x00000009 +#define NVCB97_TEXHEAD_V2_BL_DATA_TYPE_TEX_DATA_TYPE_ZFS 0x0000000a +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS MW(118:112) +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_V2_BL_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_V2_BL_PACK_COMPONENTS MW(119:119) +#define NVCB97_TEXHEAD_V2_BL_RESERVED3A MW(123:120) +#define NVCB97_TEXHEAD_V2_BL_HEADER_VERSION MW(127:124) +#define NVCB97_TEXHEAD_V2_BL_HEADER_VERSION_SELECT_PITCH_COLOR_KEY_V2 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_HEADER_VERSION_SELECT_PITCH_V2 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_HEADER_VERSION_SELECT_BLOCKLINEAR_V2 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY_V2 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_HEADER_VERSION_SELECT_ONE_D_RAW_TYPED 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_HEADER_VERSION_SELECT_ONE_D_STRUCT_BUF 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_WIDTH_MINUS_ONE MW(144:128) +#define NVCB97_TEXHEAD_V2_BL_NORMALIZED_COORDS MW(145:145) +#define NVCB97_TEXHEAD_V2_BL_ANISO_SPREAD_MAX_LOG2 MW(148:146) +#define NVCB97_TEXHEAD_V2_BL_S_R_G_B_CONVERSION MW(149:149) +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE MW(153:150) +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_V2_BL_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_V2_BL_SECTOR_PROMOTION MW(155:154) +#define NVCB97_TEXHEAD_V2_BL_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_BORDER_SOURCE MW(156:156) +#define NVCB97_TEXHEAD_V2_BL_BORDER_SOURCE_BORDER_TEXTURE 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_BORDER_SOURCE_BORDER_COLOR 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_RESERVED4A MW(159:157) +#define NVCB97_TEXHEAD_V2_BL_HEIGHT_MINUS_ONE MW(176:160) +#define NVCB97_TEXHEAD_V2_BL_DEPTH_MINUS_ONE MW(191:177) +#define NVCB97_TEXHEAD_V2_BL_RESERVED6Y MW(192:192) +#define NVCB97_TEXHEAD_V2_BL_TRILIN_OPT MW(197:193) +#define NVCB97_TEXHEAD_V2_BL_MIP_LOD_BIAS MW(210:198) +#define NVCB97_TEXHEAD_V2_BL_ANISO_BIAS MW(214:211) +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY MW(221:219) +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_RES_VIEW_MIN_MIP_LEVEL MW(227:224) +#define NVCB97_TEXHEAD_V2_BL_RES_VIEW_MAX_MIP_LEVEL MW(231:228) +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT MW(235:232) +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVCB97_TEXHEAD_V2_BL_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVCB97_TEXHEAD_V2_BL_MIN_LOD_CLAMP MW(247:236) +#define NVCB97_TEXHEAD_V2_BL_RESERVED7Y MW(255:248) + + +/* +** Texture Header V2 Blocklinear Color Key + */ + +#define NVCB97_TEXHEAD_V2_BLCK_RESERVED0A MW(3:0) +#define NVCB97_TEXHEAD_V2_BLCK_GOB_DEPTH_OFFSET MW(8:4) +#define NVCB97_TEXHEAD_V2_BLCK_ADDRESS_BITS31TO9 MW(31:9) +#define NVCB97_TEXHEAD_V2_BLCK_ADDRESS_BITS56TO32 MW(56:32) +#define NVCB97_TEXHEAD_V2_BLCK_RESERVED1A MW(63:57) +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_WIDTH MW(66:64) +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_HEIGHT MW(69:67) +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_DEPTH MW(72:70) +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_DEPTH_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_DEPTH_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_DEPTH_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_DEPTH_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_GOBS_PER_BLOCK_DEPTH_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_RESERVED3Y MW(73:73) +#define NVCB97_TEXHEAD_V2_BLCK_TILE_WIDTH_IN_GOBS MW(76:74) +#define NVCB97_TEXHEAD_V2_BLCK_TILE_WIDTH_IN_GOBS_ONE_GOB 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_TILE_WIDTH_IN_GOBS_TWO_GOBS 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_TILE_WIDTH_IN_GOBS_FOUR_GOBS 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_TILE_WIDTH_IN_GOBS_EIGHT_GOBS 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_TILE_WIDTH_IN_GOBS_SIXTEEN_GOBS 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_TILE_WIDTH_IN_GOBS_THIRTYTWO_GOBS 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_GOB3D MW(77:77) +#define NVCB97_TEXHEAD_V2_BLCK_RESERVED2Z MW(79:78) +#define NVCB97_TEXHEAD_V2_BLCK_LOD_ANISO_QUALITY2 MW(80:80) +#define NVCB97_TEXHEAD_V2_BLCK_LOD_ANISO_QUALITY MW(81:81) +#define NVCB97_TEXHEAD_V2_BLCK_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_LOD_ISO_QUALITY MW(82:82) +#define NVCB97_TEXHEAD_V2_BLCK_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_MODIFIER MW(84:83) +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_SPREAD_SCALE MW(89:85) +#define NVCB97_TEXHEAD_V2_BLCK_USE_HEADER_OPT_CONTROL MW(90:90) +#define NVCB97_TEXHEAD_V2_BLCK_DEPTH_TEXTURE MW(91:91) +#define NVCB97_TEXHEAD_V2_BLCK_MAX_MIP_LEVEL MW(95:92) +#define NVCB97_TEXHEAD_V2_BLCK_X_SOURCE MW(98:96) +#define NVCB97_TEXHEAD_V2_BLCK_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_BLCK_Y_SOURCE MW(101:99) +#define NVCB97_TEXHEAD_V2_BLCK_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_BLCK_Z_SOURCE MW(104:102) +#define NVCB97_TEXHEAD_V2_BLCK_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_BLCK_W_SOURCE MW(107:105) +#define NVCB97_TEXHEAD_V2_BLCK_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE MW(111:108) +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_UNORM 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_SNORM 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_FLOAT 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_SGNRGB 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_SGNA 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_DSDT 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_UINT 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_SINT 0x00000007 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_ZS 0x00000008 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_SZ 0x00000009 +#define NVCB97_TEXHEAD_V2_BLCK_DATA_TYPE_TEX_DATA_TYPE_ZFS 0x0000000a +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS MW(118:112) +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_V2_BLCK_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_V2_BLCK_PACK_COMPONENTS MW(119:119) +#define NVCB97_TEXHEAD_V2_BLCK_RESERVED3A MW(123:120) +#define NVCB97_TEXHEAD_V2_BLCK_HEADER_VERSION MW(127:124) +#define NVCB97_TEXHEAD_V2_BLCK_HEADER_VERSION_SELECT_PITCH_COLOR_KEY_V2 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_HEADER_VERSION_SELECT_PITCH_V2 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_HEADER_VERSION_SELECT_BLOCKLINEAR_V2 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY_V2 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_HEADER_VERSION_SELECT_ONE_D_RAW_TYPED 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_HEADER_VERSION_SELECT_ONE_D_STRUCT_BUF 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_WIDTH_MINUS_ONE MW(144:128) +#define NVCB97_TEXHEAD_V2_BLCK_NORMALIZED_COORDS MW(145:145) +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_SPREAD_MAX_LOG2 MW(148:146) +#define NVCB97_TEXHEAD_V2_BLCK_S_R_G_B_CONVERSION MW(149:149) +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE MW(153:150) +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_V2_BLCK_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_V2_BLCK_SECTOR_PROMOTION MW(155:154) +#define NVCB97_TEXHEAD_V2_BLCK_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_BORDER_SOURCE MW(156:156) +#define NVCB97_TEXHEAD_V2_BLCK_BORDER_SOURCE_BORDER_TEXTURE 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_BORDER_SOURCE_BORDER_COLOR 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_RESERVED4A MW(159:157) +#define NVCB97_TEXHEAD_V2_BLCK_HEIGHT_MINUS_ONE MW(176:160) +#define NVCB97_TEXHEAD_V2_BLCK_DEPTH_MINUS_ONE MW(191:177) +#define NVCB97_TEXHEAD_V2_BLCK_COLOR_KEY_OP MW(192:192) +#define NVCB97_TEXHEAD_V2_BLCK_TRILIN_OPT MW(197:193) +#define NVCB97_TEXHEAD_V2_BLCK_MIP_LOD_BIAS MW(210:198) +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_BIAS MW(214:211) +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY MW(221:219) +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXHEAD_V2_BLCK_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_BLCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_V2_BLCK_COLOR_KEY_VALUE MW(255:224) + + +/* +** Texture Header V2 One-D Raw Typed + */ + +#define NVCB97_TEXHEAD_V2_1DRT_ADDRESS_BITS31TO0 MW(31:0) +#define NVCB97_TEXHEAD_V2_1DRT_ADDRESS_BITS63TO32 MW(63:32) +#define NVCB97_TEXHEAD_V2_1DRT_WIDTH_MINUS_ONE MW(95:64) +#define NVCB97_TEXHEAD_V2_1DRT_X_SOURCE MW(98:96) +#define NVCB97_TEXHEAD_V2_1DRT_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_1DRT_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_1DRT_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_1DRT_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_1DRT_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_1DRT_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_1DRT_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_1DRT_Y_SOURCE MW(101:99) +#define NVCB97_TEXHEAD_V2_1DRT_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_1DRT_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_1DRT_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_1DRT_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_1DRT_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_1DRT_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_1DRT_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_1DRT_Z_SOURCE MW(104:102) +#define NVCB97_TEXHEAD_V2_1DRT_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_1DRT_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_1DRT_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_1DRT_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_1DRT_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_1DRT_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_1DRT_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_1DRT_W_SOURCE MW(107:105) +#define NVCB97_TEXHEAD_V2_1DRT_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_1DRT_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_1DRT_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_1DRT_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_1DRT_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_1DRT_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_1DRT_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE MW(111:108) +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_UNORM 0x00000000 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_SNORM 0x00000001 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_FLOAT 0x00000002 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_SGNRGB 0x00000003 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_SGNA 0x00000004 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_DSDT 0x00000005 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_UINT 0x00000006 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_SINT 0x00000007 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_ZS 0x00000008 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_SZ 0x00000009 +#define NVCB97_TEXHEAD_V2_1DRT_DATA_TYPE_TEX_DATA_TYPE_ZFS 0x0000000a +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS MW(117:112) +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_INVALID 0x00000000 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_G8R24 0x0000000d +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_G24R8 0x0000000e +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R32 0x0000000f +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_G8R8 0x00000018 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R16 0x0000001b +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R8 0x0000001d +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_G4R4 0x0000001e +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_X8B8G8R8_SRGB 0x00000031 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_A8B8G8R8_SRGB 0x00000032 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_G8R8_SRGB 0x00000033 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZES_1D_R8_SRGB 0x00000034 +#define NVCB97_TEXHEAD_V2_1DRT_COMPONENTS_SIZESV2_CS_BITFIELD_SIZE 0x0000003f +#define NVCB97_TEXHEAD_V2_1DRT_SECTOR_PROMOTION MW(119:118) +#define NVCB97_TEXHEAD_V2_1DRT_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_V2_1DRT_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_V2_1DRT_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_V2_1DRT_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_V2_1DRT_RESERVED3A MW(123:120) +#define NVCB97_TEXHEAD_V2_1DRT_HEADER_VERSION MW(127:124) +#define NVCB97_TEXHEAD_V2_1DRT_HEADER_VERSION_SELECT_PITCH_COLOR_KEY_V2 0x00000001 +#define NVCB97_TEXHEAD_V2_1DRT_HEADER_VERSION_SELECT_PITCH_V2 0x00000002 +#define NVCB97_TEXHEAD_V2_1DRT_HEADER_VERSION_SELECT_BLOCKLINEAR_V2 0x00000003 +#define NVCB97_TEXHEAD_V2_1DRT_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY_V2 0x00000004 +#define NVCB97_TEXHEAD_V2_1DRT_HEADER_VERSION_SELECT_ONE_D_RAW_TYPED 0x00000005 +#define NVCB97_TEXHEAD_V2_1DRT_HEADER_VERSION_SELECT_ONE_D_STRUCT_BUF 0x00000006 +#define NVCB97_TEXHEAD_V2_1DRT_RESERVED4X MW(156:128) +#define NVCB97_TEXHEAD_V2_1DRT_RESERVED4A MW(159:157) +#define NVCB97_TEXHEAD_V2_1DRT_RESERVED5X MW(191:160) +#define NVCB97_TEXHEAD_V2_1DRT_RESERVED6X MW(223:192) +#define NVCB97_TEXHEAD_V2_1DRT_RESERVED7X MW(255:224) + + +/* +** Texture Header V2 One-D Structured Buffer + */ + +#define NVCB97_TEXHEAD_V2_1DSB_ADDRESS_BITS31TO0 MW(31:0) +#define NVCB97_TEXHEAD_V2_1DSB_ADDRESS_BITS63TO32 MW(63:32) +#define NVCB97_TEXHEAD_V2_1DSB_WIDTH_MINUS_ONE MW(95:64) +#define NVCB97_TEXHEAD_V2_1DSB_STRIDE MW(107:96) +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE MW(111:108) +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_UNORM 0x00000000 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_SNORM 0x00000001 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_FLOAT 0x00000002 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_SGNRGB 0x00000003 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_SGNA 0x00000004 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_DSDT 0x00000005 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_UINT 0x00000006 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_SINT 0x00000007 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_ZS 0x00000008 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_SZ 0x00000009 +#define NVCB97_TEXHEAD_V2_1DSB_DATA_TYPE_TEX_DATA_TYPE_ZFS 0x0000000a +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS MW(117:112) +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_INVALID 0x00000000 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_G8R24 0x0000000d +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_G24R8 0x0000000e +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R32 0x0000000f +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_G8R8 0x00000018 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R16 0x0000001b +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R8 0x0000001d +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_G4R4 0x0000001e +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_X8B8G8R8_SRGB 0x00000031 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_A8B8G8R8_SRGB 0x00000032 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_G8R8_SRGB 0x00000033 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZES_1D_R8_SRGB 0x00000034 +#define NVCB97_TEXHEAD_V2_1DSB_COMPONENTS_SIZESV2_CS_BITFIELD_SIZE 0x0000003f +#define NVCB97_TEXHEAD_V2_1DSB_SECTOR_PROMOTION MW(119:118) +#define NVCB97_TEXHEAD_V2_1DSB_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_V2_1DSB_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_V2_1DSB_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_V2_1DSB_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_V2_1DSB_RESERVED3A MW(123:120) +#define NVCB97_TEXHEAD_V2_1DSB_HEADER_VERSION MW(127:124) +#define NVCB97_TEXHEAD_V2_1DSB_HEADER_VERSION_SELECT_PITCH_COLOR_KEY_V2 0x00000001 +#define NVCB97_TEXHEAD_V2_1DSB_HEADER_VERSION_SELECT_PITCH_V2 0x00000002 +#define NVCB97_TEXHEAD_V2_1DSB_HEADER_VERSION_SELECT_BLOCKLINEAR_V2 0x00000003 +#define NVCB97_TEXHEAD_V2_1DSB_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY_V2 0x00000004 +#define NVCB97_TEXHEAD_V2_1DSB_HEADER_VERSION_SELECT_ONE_D_RAW_TYPED 0x00000005 +#define NVCB97_TEXHEAD_V2_1DSB_HEADER_VERSION_SELECT_ONE_D_STRUCT_BUF 0x00000006 +#define NVCB97_TEXHEAD_V2_1DSB_RESERVED4X MW(156:128) +#define NVCB97_TEXHEAD_V2_1DSB_RESERVED4A MW(159:157) +#define NVCB97_TEXHEAD_V2_1DSB_RESERVED5X MW(191:160) +#define NVCB97_TEXHEAD_V2_1DSB_RESERVED6X MW(223:192) +#define NVCB97_TEXHEAD_V2_1DSB_RESERVED7X MW(255:224) + + +/* +** Texture Header V2 Pitch + */ + +#define NVCB97_TEXHEAD_V2_PITCH_RESERVED0A MW(3:0) +#define NVCB97_TEXHEAD_V2_PITCH_RESERVED0X MW(4:4) +#define NVCB97_TEXHEAD_V2_PITCH_ADDRESS_BITS31TO5 MW(31:5) +#define NVCB97_TEXHEAD_V2_PITCH_ADDRESS_BITS56TO32 MW(56:32) +#define NVCB97_TEXHEAD_V2_PITCH_RESERVED1A MW(63:57) +#define NVCB97_TEXHEAD_V2_PITCH_PITCH_BITS21TO5 MW(80:64) +#define NVCB97_TEXHEAD_V2_PITCH_LOD_ANISO_QUALITY2 MW(81:81) +#define NVCB97_TEXHEAD_V2_PITCH_LOD_ANISO_QUALITY MW(82:82) +#define NVCB97_TEXHEAD_V2_PITCH_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_LOD_ISO_QUALITY MW(83:83) +#define NVCB97_TEXHEAD_V2_PITCH_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_MODIFIER MW(85:84) +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_SPREAD_SCALE MW(90:86) +#define NVCB97_TEXHEAD_V2_PITCH_DEPTH_TEXTURE MW(91:91) +#define NVCB97_TEXHEAD_V2_PITCH_MAX_MIP_LEVEL MW(95:92) +#define NVCB97_TEXHEAD_V2_PITCH_X_SOURCE MW(98:96) +#define NVCB97_TEXHEAD_V2_PITCH_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCH_Y_SOURCE MW(101:99) +#define NVCB97_TEXHEAD_V2_PITCH_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCH_Z_SOURCE MW(104:102) +#define NVCB97_TEXHEAD_V2_PITCH_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCH_W_SOURCE MW(107:105) +#define NVCB97_TEXHEAD_V2_PITCH_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE MW(111:108) +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_UNORM 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_SNORM 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_FLOAT 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_SGNRGB 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_SGNA 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_DSDT 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_UINT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_SINT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_ZS 0x00000008 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_SZ 0x00000009 +#define NVCB97_TEXHEAD_V2_PITCH_DATA_TYPE_TEX_DATA_TYPE_ZFS 0x0000000a +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS MW(118:112) +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_V2_PITCH_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_V2_PITCH_PACK_COMPONENTS MW(119:119) +#define NVCB97_TEXHEAD_V2_PITCH_RESERVED3A MW(123:120) +#define NVCB97_TEXHEAD_V2_PITCH_HEADER_VERSION MW(127:124) +#define NVCB97_TEXHEAD_V2_PITCH_HEADER_VERSION_SELECT_PITCH_COLOR_KEY_V2 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_HEADER_VERSION_SELECT_PITCH_V2 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_HEADER_VERSION_SELECT_BLOCKLINEAR_V2 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY_V2 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_HEADER_VERSION_SELECT_ONE_D_RAW_TYPED 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_HEADER_VERSION_SELECT_ONE_D_STRUCT_BUF 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_WIDTH_MINUS_ONE MW(144:128) +#define NVCB97_TEXHEAD_V2_PITCH_NORMALIZED_COORDS MW(145:145) +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_SPREAD_MAX_LOG2 MW(148:146) +#define NVCB97_TEXHEAD_V2_PITCH_S_R_G_B_CONVERSION MW(149:149) +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE MW(153:150) +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_V2_PITCH_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_V2_PITCH_SECTOR_PROMOTION MW(155:154) +#define NVCB97_TEXHEAD_V2_PITCH_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_BORDER_SOURCE MW(156:156) +#define NVCB97_TEXHEAD_V2_PITCH_BORDER_SOURCE_BORDER_TEXTURE 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_BORDER_SOURCE_BORDER_COLOR 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_RESERVED4A MW(159:157) +#define NVCB97_TEXHEAD_V2_PITCH_HEIGHT_MINUS_ONE MW(176:160) +#define NVCB97_TEXHEAD_V2_PITCH_RESERVED5Y MW(191:177) +#define NVCB97_TEXHEAD_V2_PITCH_RESERVED6Y MW(192:192) +#define NVCB97_TEXHEAD_V2_PITCH_TRILIN_OPT MW(197:193) +#define NVCB97_TEXHEAD_V2_PITCH_MIP_LOD_BIAS MW(210:198) +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_BIAS MW(214:211) +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY MW(221:219) +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_RES_VIEW_MIN_MIP_LEVEL MW(227:224) +#define NVCB97_TEXHEAD_V2_PITCH_RES_VIEW_MAX_MIP_LEVEL MW(231:228) +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT MW(235:232) +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_1X1 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_2X1 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_D3D 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_2X1_D3D 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_4X4 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2_VC_4 0x00000008 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_2X2_VC_12 0x00000009 +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_VC_8 0x0000000a +#define NVCB97_TEXHEAD_V2_PITCH_MULTI_SAMPLE_COUNT_MODE_4X2_VC_24 0x0000000b +#define NVCB97_TEXHEAD_V2_PITCH_MIN_LOD_CLAMP MW(247:236) +#define NVCB97_TEXHEAD_V2_PITCH_RESERVED7Y MW(255:248) + + +/* +** Texture Header V2 Pitch Color Key + */ + +#define NVCB97_TEXHEAD_V2_PITCHCK_RESERVED0A MW(3:0) +#define NVCB97_TEXHEAD_V2_PITCHCK_RESERVED0X MW(4:4) +#define NVCB97_TEXHEAD_V2_PITCHCK_ADDRESS_BITS31TO5 MW(31:5) +#define NVCB97_TEXHEAD_V2_PITCHCK_ADDRESS_BITS56TO32 MW(56:32) +#define NVCB97_TEXHEAD_V2_PITCHCK_RESERVED1A MW(63:57) +#define NVCB97_TEXHEAD_V2_PITCHCK_PITCH_BITS21TO5 MW(80:64) +#define NVCB97_TEXHEAD_V2_PITCHCK_LOD_ANISO_QUALITY2 MW(81:81) +#define NVCB97_TEXHEAD_V2_PITCHCK_LOD_ANISO_QUALITY MW(82:82) +#define NVCB97_TEXHEAD_V2_PITCHCK_LOD_ANISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_LOD_ANISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_LOD_ISO_QUALITY MW(83:83) +#define NVCB97_TEXHEAD_V2_PITCHCK_LOD_ISO_QUALITY_LOD_QUALITY_LOW 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_LOD_ISO_QUALITY_LOD_QUALITY_HIGH 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER MW(85:84) +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_SPREAD_SCALE MW(90:86) +#define NVCB97_TEXHEAD_V2_PITCHCK_DEPTH_TEXTURE MW(91:91) +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_MIP_LEVEL MW(95:92) +#define NVCB97_TEXHEAD_V2_PITCHCK_X_SOURCE MW(98:96) +#define NVCB97_TEXHEAD_V2_PITCHCK_X_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_X_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_X_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_X_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_X_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_X_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_X_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCHCK_Y_SOURCE MW(101:99) +#define NVCB97_TEXHEAD_V2_PITCHCK_Y_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_Y_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_Y_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_Y_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_Y_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_Y_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_Y_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCHCK_Z_SOURCE MW(104:102) +#define NVCB97_TEXHEAD_V2_PITCHCK_Z_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_Z_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_Z_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_Z_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_Z_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_Z_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_Z_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCHCK_W_SOURCE MW(107:105) +#define NVCB97_TEXHEAD_V2_PITCHCK_W_SOURCE_IN_ZERO 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_W_SOURCE_IN_R 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_W_SOURCE_IN_G 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_W_SOURCE_IN_B 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_W_SOURCE_IN_A 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_W_SOURCE_IN_ONE_INT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_W_SOURCE_IN_ONE_FLOAT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE MW(111:108) +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_UNORM 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_SNORM 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_FLOAT 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_SGNRGB 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_SGNA 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_DSDT 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_UINT 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_SINT 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_ZS 0x00000008 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_SZ 0x00000009 +#define NVCB97_TEXHEAD_V2_PITCHCK_DATA_TYPE_TEX_DATA_TYPE_ZFS 0x0000000a +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS MW(118:112) +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_INVALID 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R32_G32_B32 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R32_G32 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R32_B24G8 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_X8B8G8R8 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_A8B8G8R8 0x00000008 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_A2B10G10R10 0x00000009 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R16_G16 0x0000000c +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_G8R24 0x0000000d +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_G24R8 0x0000000e +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R32 0x0000000f +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_A4B4G4R4 0x00000012 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_A5B5G5R1 0x00000013 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_A1B5G5R5 0x00000014 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_B5G6R5 0x00000015 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_B6G5R5 0x00000016 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_G8R8 0x00000018 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R16 0x0000001b +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R8 0x0000001d +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_G4R4 0x0000001e +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_R1 0x0000001f +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_BF10GF11RF11 0x00000021 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_G8B8G8R8 0x00000022 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_B8G8R8G8 0x00000023 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_DXT1 0x00000024 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_DXT23 0x00000025 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_DXT45 0x00000026 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_DXN1 0x00000027 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_DXN2 0x00000028 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_BC6H_SF16 0x00000010 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_BC6H_UF16 0x00000011 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_BC7U 0x00000017 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ETC2_RGB 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_EAC 0x00000019 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_EACX2 0x0000001a +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_Z24S8 0x00000029 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_X8Z24 0x0000002a +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_S8Z24 0x0000002b +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ZF32 0x0000002f +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ZF32_X24S8 0x00000030 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_Z16 0x0000003a +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046 +#define NVCB97_TEXHEAD_V2_PITCHCK_COMPONENTS_SIZES_CS_BITFIELD_SIZE 0x0000007f +#define NVCB97_TEXHEAD_V2_PITCHCK_PACK_COMPONENTS MW(119:119) +#define NVCB97_TEXHEAD_V2_PITCHCK_RESERVED3A MW(123:120) +#define NVCB97_TEXHEAD_V2_PITCHCK_HEADER_VERSION MW(127:124) +#define NVCB97_TEXHEAD_V2_PITCHCK_HEADER_VERSION_SELECT_PITCH_COLOR_KEY_V2 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_HEADER_VERSION_SELECT_PITCH_V2 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_HEADER_VERSION_SELECT_BLOCKLINEAR_V2 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_HEADER_VERSION_SELECT_BLOCKLINEAR_COLOR_KEY_V2 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_HEADER_VERSION_SELECT_ONE_D_RAW_TYPED 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_HEADER_VERSION_SELECT_ONE_D_STRUCT_BUF 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_WIDTH_MINUS_ONE MW(144:128) +#define NVCB97_TEXHEAD_V2_PITCHCK_NORMALIZED_COORDS MW(145:145) +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_SPREAD_MAX_LOG2 MW(148:146) +#define NVCB97_TEXHEAD_V2_PITCHCK_S_R_G_B_CONVERSION MW(149:149) +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE MW(153:150) +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_ONE_D 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_TWO_D 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_THREE_D 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_CUBEMAP 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_ONE_D_ARRAY 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_TWO_D_ARRAY 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_ONE_D_BUFFER 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_CUBEMAP_ARRAY 0x00000008 +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_HTEX_TWOD 0x0000000a +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_HTEX_THREE_D 0x0000000b +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_HTEX_TWOD_ARRAY 0x0000000e +#define NVCB97_TEXHEAD_V2_PITCHCK_TEXTURE_TYPE_TT_BIT_FIELD_SIZE 0x0000000f +#define NVCB97_TEXHEAD_V2_PITCHCK_SECTOR_PROMOTION MW(155:154) +#define NVCB97_TEXHEAD_V2_PITCHCK_SECTOR_PROMOTION_NO_PROMOTION 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_SECTOR_PROMOTION_PROMOTE_TO_4 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_BORDER_SOURCE MW(156:156) +#define NVCB97_TEXHEAD_V2_PITCHCK_BORDER_SOURCE_BORDER_TEXTURE 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_BORDER_SOURCE_BORDER_COLOR 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_RESERVED4A MW(159:157) +#define NVCB97_TEXHEAD_V2_PITCHCK_HEIGHT_MINUS_ONE MW(176:160) +#define NVCB97_TEXHEAD_V2_PITCHCK_RESERVED5Y MW(191:177) +#define NVCB97_TEXHEAD_V2_PITCHCK_COLOR_KEY_OP MW(192:192) +#define NVCB97_TEXHEAD_V2_PITCHCK_TRILIN_OPT MW(197:193) +#define NVCB97_TEXHEAD_V2_PITCHCK_MIP_LOD_BIAS MW(210:198) +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_BIAS MW(214:211) +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_FUNC MW(216:215) +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_FUNC MW(218:217) +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_HALF 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_COARSE_SPREAD_FUNC_SPREAD_FUNC_MAX 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY MW(221:219) +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXHEAD_V2_PITCHCK_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_MODIFIER MW(223:222) +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_NONE 0x00000000 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_ONE 0x00000001 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_CONST_TWO 0x00000002 +#define NVCB97_TEXHEAD_V2_PITCHCK_ANISO_FINE_SPREAD_MODIFIER_SPREAD_MODIFIER_SQRT 0x00000003 +#define NVCB97_TEXHEAD_V2_PITCHCK_COLOR_KEY_VALUE MW(255:224) + + +/* +** Texture Sampler State + */ + +#define NVCB97_TEXSAMP0_ADDRESS_U 2:0 +#define NVCB97_TEXSAMP0_ADDRESS_U_WRAP 0x00000000 +#define NVCB97_TEXSAMP0_ADDRESS_U_MIRROR 0x00000001 +#define NVCB97_TEXSAMP0_ADDRESS_U_CLAMP_TO_EDGE 0x00000002 +#define NVCB97_TEXSAMP0_ADDRESS_U_BORDER 0x00000003 +#define NVCB97_TEXSAMP0_ADDRESS_U_CLAMP_OGL 0x00000004 +#define NVCB97_TEXSAMP0_ADDRESS_U_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005 +#define NVCB97_TEXSAMP0_ADDRESS_U_MIRROR_ONCE_BORDER 0x00000006 +#define NVCB97_TEXSAMP0_ADDRESS_U_MIRROR_ONCE_CLAMP_OGL 0x00000007 +#define NVCB97_TEXSAMP0_ADDRESS_V 5:3 +#define NVCB97_TEXSAMP0_ADDRESS_V_WRAP 0x00000000 +#define NVCB97_TEXSAMP0_ADDRESS_V_MIRROR 0x00000001 +#define NVCB97_TEXSAMP0_ADDRESS_V_CLAMP_TO_EDGE 0x00000002 +#define NVCB97_TEXSAMP0_ADDRESS_V_BORDER 0x00000003 +#define NVCB97_TEXSAMP0_ADDRESS_V_CLAMP_OGL 0x00000004 +#define NVCB97_TEXSAMP0_ADDRESS_V_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005 +#define NVCB97_TEXSAMP0_ADDRESS_V_MIRROR_ONCE_BORDER 0x00000006 +#define NVCB97_TEXSAMP0_ADDRESS_V_MIRROR_ONCE_CLAMP_OGL 0x00000007 +#define NVCB97_TEXSAMP0_ADDRESS_P 8:6 +#define NVCB97_TEXSAMP0_ADDRESS_P_WRAP 0x00000000 +#define NVCB97_TEXSAMP0_ADDRESS_P_MIRROR 0x00000001 +#define NVCB97_TEXSAMP0_ADDRESS_P_CLAMP_TO_EDGE 0x00000002 +#define NVCB97_TEXSAMP0_ADDRESS_P_BORDER 0x00000003 +#define NVCB97_TEXSAMP0_ADDRESS_P_CLAMP_OGL 0x00000004 +#define NVCB97_TEXSAMP0_ADDRESS_P_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005 +#define NVCB97_TEXSAMP0_ADDRESS_P_MIRROR_ONCE_BORDER 0x00000006 +#define NVCB97_TEXSAMP0_ADDRESS_P_MIRROR_ONCE_CLAMP_OGL 0x00000007 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE 9:9 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC 12:10 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_NEVER 0x00000000 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_LESS 0x00000001 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_EQUAL 0x00000002 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_LEQUAL 0x00000003 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_GREATER 0x00000004 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_NOTEQUAL 0x00000005 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_GEQUAL 0x00000006 +#define NVCB97_TEXSAMP0_DEPTH_COMPARE_FUNC_ZC_ALWAYS 0x00000007 +#define NVCB97_TEXSAMP0_S_R_G_B_CONVERSION 13:13 +#define NVCB97_TEXSAMP0_RESERVED0A 16:14 +#define NVCB97_TEXSAMP0_RESERVED0B 19:17 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY 22:20 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY_ANISO_1_TO_1 0x00000000 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY_ANISO_2_TO_1 0x00000001 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY_ANISO_4_TO_1 0x00000002 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY_ANISO_6_TO_1 0x00000003 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY_ANISO_8_TO_1 0x00000004 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY_ANISO_10_TO_1 0x00000005 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY_ANISO_12_TO_1 0x00000006 +#define NVCB97_TEXSAMP0_MAX_ANISOTROPY_ANISO_16_TO_1 0x00000007 +#define NVCB97_TEXSAMP0_FORCED_INVALID 31:31 +#define NVCB97_TEXSAMP1_MAG_FILTER 2:0 +#define NVCB97_TEXSAMP1_MAG_FILTER_MAG_POINT 0x00000001 +#define NVCB97_TEXSAMP1_MAG_FILTER_MAG_LINEAR 0x00000002 +#define NVCB97_TEXSAMP1_MAG_FILTER_VCAA_4_TAP 0x00000003 +#define NVCB97_TEXSAMP1_MAG_FILTER_VCAA_8_TAP 0x00000004 +#define NVCB97_TEXSAMP1_MIN_LOD_CLAMP_BEHAVIOR_FOR_NEAREST_MIP 3:3 +#define NVCB97_TEXSAMP1_MIN_LOD_CLAMP_BEHAVIOR_FOR_NEAREST_MIP_INTEGER_AND_FRACTION 0x00000000 +#define NVCB97_TEXSAMP1_MIN_LOD_CLAMP_BEHAVIOR_FOR_NEAREST_MIP_INTEGER_ONLY 0x00000001 +#define NVCB97_TEXSAMP1_MIN_FILTER 5:4 +#define NVCB97_TEXSAMP1_MIN_FILTER_MIN_POINT 0x00000001 +#define NVCB97_TEXSAMP1_MIN_FILTER_MIN_LINEAR 0x00000002 +#define NVCB97_TEXSAMP1_MIN_FILTER_MIN_ANISO 0x00000003 +#define NVCB97_TEXSAMP1_MIP_FILTER 7:6 +#define NVCB97_TEXSAMP1_MIP_FILTER_MIP_NONE 0x00000001 +#define NVCB97_TEXSAMP1_MIP_FILTER_MIP_POINT 0x00000002 +#define NVCB97_TEXSAMP1_MIP_FILTER_MIP_LINEAR 0x00000003 +#define NVCB97_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING 9:8 +#define NVCB97_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_USE_WRAP 0x00000000 +#define NVCB97_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_OVERRIDE_WRAP 0x00000001 +#define NVCB97_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_AUTO_SPAN_SEAM 0x00000002 +#define NVCB97_TEXSAMP1_CUBEMAP_INTERFACE_FILTERING_AUTO_CROSS_SEAM 0x00000003 +#define NVCB97_TEXSAMP1_REDUCTION_FILTER 11:10 +#define NVCB97_TEXSAMP1_REDUCTION_FILTER_RED_NONE 0x00000000 +#define NVCB97_TEXSAMP1_REDUCTION_FILTER_RED_MINIMUM 0x00000001 +#define NVCB97_TEXSAMP1_REDUCTION_FILTER_RED_MAXIMUM 0x00000002 +#define NVCB97_TEXSAMP1_MIP_LOD_BIAS 24:12 +#define NVCB97_TEXSAMP1_FLOAT_COORD_NORMALIZATION 25:25 +#define NVCB97_TEXSAMP1_FLOAT_COORD_NORMALIZATION_USE_HEADER_SETTING 0x00000000 +#define NVCB97_TEXSAMP1_FLOAT_COORD_NORMALIZATION_FORCE_UNNORMALIZED_COORDS 0x00000001 +#define NVCB97_TEXSAMP1_TRILIN_OPT 30:26 +#define NVCB97_TEXSAMP2_MIN_LOD_CLAMP 11:0 +#define NVCB97_TEXSAMP2_MAX_LOD_CLAMP 23:12 +#define NVCB97_TEXSAMP2_S_R_G_B_BORDER_COLOR_R 31:24 +#define NVCB97_TEXSAMP3_RESERVED12 11:0 +#define NVCB97_TEXSAMP3_S_R_G_B_BORDER_COLOR_G 19:12 +#define NVCB97_TEXSAMP3_S_R_G_B_BORDER_COLOR_B 27:20 +#define NVCB97_TEXSAMP4_BORDER_COLOR_R 31:0 +#define NVCB97_TEXSAMP5_BORDER_COLOR_G 31:0 +#define NVCB97_TEXSAMP6_BORDER_COLOR_B 31:0 +#define NVCB97_TEXSAMP7_BORDER_COLOR_A 31:0 + + + +#endif // #ifndef __CLCB97TEX_H__ diff --git a/src/common/sdk/nvidia/inc/cpuopsys.h b/src/common/sdk/nvidia/inc/cpuopsys.h index ee911b77f..230c7b521 100644 --- a/src/common/sdk/nvidia/inc/cpuopsys.h +++ b/src/common/sdk/nvidia/inc/cpuopsys.h @@ -239,7 +239,7 @@ #endif /* For verification-only features not intended to be included in normal drivers */ -#if (defined(NV_MODS) || defined(NV_GSP_MODS)) && defined(DEBUG) && !defined(DISABLE_VERIF_FEATURES) +#if defined(ENABLE_VERIF_FEATURES) #define NV_VERIF_FEATURES #endif @@ -269,12 +269,6 @@ #define NV_IS_MODS 0 -#if defined(NV_GSP_MODS) -#define NV_IS_GSP_MODS 1 -#else -#define NV_IS_GSP_MODS 0 -#endif - #define NVOS_IS_WINDOWS 0 #if defined(NV_WINDOWS_CE) #define NVOS_IS_WINDOWS_CE 1 diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h index 00de834ef..89e221966 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h @@ -42,7 +42,6 @@ #define NV0000_CTRL_EVENT (0x05) #define NV0000_CTRL_NVD (0x06) #define NV0000_CTRL_SWINSTR (0x07) -#define NV0000_CTRL_GSPC (0x08) #define NV0000_CTRL_PROC (0x09) #define NV0000_CTRL_SYNC_GPU_BOOST (0x0A) #define NV0000_CTRL_GPUACCT (0x0B) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h index 1c1d7903c..a05add663 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h @@ -63,18 +63,20 @@ typedef struct NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS { NvU32 addrSpaceType; /* [out] - Memory Address Space Type */ } NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS; -#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_INVALID 0x00000000 -#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_SYSMEM 0x00000001 -#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_VIDMEM 0x00000002 -#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_REGMEM 0x00000003 -#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC 0x00000004 +#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_INVALID 0x00000000 +#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_SYSMEM 0x00000001 +#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_VIDMEM 0x00000002 +#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_REGMEM 0x00000003 +#define NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC 0x00000004 + + /* * NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO * * This command may be used to query information on a handle */ -#define NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO (0xd02) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_CLIENT_GET_HANDLE_INFO (0xd02) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_MESSAGE_ID" */ #define NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS_MESSAGE_ID (0x2U) @@ -160,5 +162,22 @@ typedef struct NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS { RS_SHARE_POLICY sharePolicy; /* [in] - Share Policy to apply */ } NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS; +/* + * NV0000_CTRL_CMD_CLIENT_OBJECTS_ARE_DUPLICATES + * + * This command returns true if the objects are duplicates. + * + * Currently supported only for memory objects. + */ +#define NV0000_CTRL_CMD_CLIENT_OBJECTS_ARE_DUPLICATES (0xd07) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS { + NvHandle hObject1; /* [in] - Handle of object to be checked */ + NvHandle hObject2; /* [in] - Handle of object to be checked */ + NvBool bDuplicates; /* [out] - Returns true if duplicates */ +} NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS; + /* _ctrl0000client_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h index 76e5bf5a6..3ce0f06f3 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h @@ -56,10 +56,10 @@ * NV_ERR_INVALID_PARAM_STRUCT * NV_ERR_OPERATING_SYSTEM */ -#define NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS (0x201) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS (0x201U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID" */ -#define NV0000_CTRL_GPU_MAX_ATTACHED_GPUS 32 -#define NV0000_CTRL_GPU_INVALID_ID (0xffffffff) +#define NV0000_CTRL_GPU_MAX_ATTACHED_GPUS 32U +#define NV0000_CTRL_GPU_INVALID_ID (0xffffffffU) #define NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID (0x1U) @@ -70,9 +70,9 @@ typedef struct NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS { /* * Deprecated. Please use NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 instead. */ -#define NV0000_CTRL_CMD_GPU_GET_ID_INFO (0x202) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_GPU_GET_ID_INFO (0x202U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_PARAMS_MESSAGE_ID" */ -#define NV0000_CTRL_GPU_MAX_SZNAME 128 +#define NV0000_CTRL_GPU_MAX_SZNAME 128U #define NV0000_CTRL_NO_NUMA_NODE (-1) @@ -149,7 +149,7 @@ typedef struct NV0000_CTRL_GPU_GET_ID_INFO_PARAMS { -#define NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 (0x205) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 (0x205U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID" */ #define NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID (0x5U) @@ -167,25 +167,25 @@ typedef struct NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS { /* valid flags values */ #define NV0000_CTRL_GPU_ID_INFO_IN_USE 0:0 -#define NV0000_CTRL_GPU_ID_INFO_IN_USE_FALSE (0x00000000) -#define NV0000_CTRL_GPU_ID_INFO_IN_USE_TRUE (0x00000001) +#define NV0000_CTRL_GPU_ID_INFO_IN_USE_FALSE (0x00000000U) +#define NV0000_CTRL_GPU_ID_INFO_IN_USE_TRUE (0x00000001U) #define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE 1:1 -#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_FALSE (0x00000000) -#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_TRUE (0x00000001) +#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_FALSE (0x00000000U) +#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_TRUE (0x00000001U) #define NV0000_CTRL_GPU_ID_INFO_MOBILE 2:2 -#define NV0000_CTRL_GPU_ID_INFO_MOBILE_FALSE (0x00000000) -#define NV0000_CTRL_GPU_ID_INFO_MOBILE_TRUE (0x00000001) +#define NV0000_CTRL_GPU_ID_INFO_MOBILE_FALSE (0x00000000U) +#define NV0000_CTRL_GPU_ID_INFO_MOBILE_TRUE (0x00000001U) #define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER 3:3 -#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_FALSE (0x00000000) -#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_TRUE (0x00000001) +#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_FALSE (0x00000000U) +#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_TRUE (0x00000001U) #define NV0000_CTRL_GPU_ID_INFO_SOC 5:5 -#define NV0000_CTRL_GPU_ID_INFO_SOC_FALSE (0x00000000) -#define NV0000_CTRL_GPU_ID_INFO_SOC_TRUE (0x00000001) +#define NV0000_CTRL_GPU_ID_INFO_SOC_FALSE (0x00000000U) +#define NV0000_CTRL_GPU_ID_INFO_SOC_TRUE (0x00000001U) #define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED 6:6 -#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_FALSE (0x00000000) -#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_TRUE (0x00000001) +#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_FALSE (0x00000000U) +#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_TRUE (0x00000001U) /* * NV0000_CTRL_CMD_GPU_GET_INIT_STATUS @@ -213,7 +213,7 @@ typedef struct NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS { * NV_ERR_INVALID_ARGUMENT * NV_ERR_INVALID_STATE */ -#define NV0000_CTRL_CMD_GPU_GET_INIT_STATUS (0x203) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_GPU_GET_INIT_STATUS (0x203U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS_MESSAGE_ID" */ #define NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS_MESSAGE_ID (0x3U) @@ -240,7 +240,7 @@ typedef struct NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS { * NV_OK * NV_ERR_INVALID_PARAM_STRUCT */ -#define NV0000_CTRL_CMD_GPU_GET_DEVICE_IDS (0x204) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_GPU_GET_DEVICE_IDS (0x204U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS_MESSAGE_ID" */ #define NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS_MESSAGE_ID (0x4U) @@ -275,7 +275,7 @@ typedef struct NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS { * Possible status values returned are: * NV_OK */ -#define NV0000_CTRL_CMD_GPU_GET_PROBED_IDS (0x214) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_GPU_GET_PROBED_IDS (0x214U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS_MESSAGE_ID" */ #define NV0000_CTRL_GPU_MAX_PROBED_GPUS NV_MAX_DEVICES @@ -312,7 +312,7 @@ typedef struct NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS { * NV_ERR_NOT_SUPPORTED * NV_ERR_INVALID_ARGUMENT */ -#define NV0000_CTRL_CMD_GPU_GET_PCI_INFO (0x21b) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_GPU_GET_PCI_INFO (0x21bU) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID" */ #define NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID (0x1BU) @@ -371,9 +371,9 @@ typedef struct NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS { * NV_ERR_IRQ_EDGE_TRIGGERED * NV_ERR_IRQ_NOT_FIRING */ -#define NV0000_CTRL_CMD_GPU_ATTACH_IDS (0x215) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_ATTACH_IDS_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_GPU_ATTACH_IDS (0x215U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_ATTACH_IDS_PARAMS_MESSAGE_ID" */ -#define NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS (0x0000ffff) +#define NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS (0x0000ffffU) #define NV0000_CTRL_GPU_ATTACH_IDS_PARAMS_MESSAGE_ID (0x15U) @@ -424,9 +424,9 @@ typedef struct NV0000_CTRL_GPU_ATTACH_IDS_PARAMS { * NV_ERR_INVALID_PARAM_STRUCT * NV_ERR_INVALID_ARGUMENT */ -#define NV0000_CTRL_CMD_GPU_DETACH_IDS (0x216) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_DETACH_IDS_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_GPU_DETACH_IDS (0x216U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_DETACH_IDS_PARAMS_MESSAGE_ID" */ -#define NV0000_CTRL_GPU_DETACH_ALL_ATTACHED_IDS (0x0000ffff) +#define NV0000_CTRL_GPU_DETACH_ALL_ATTACHED_IDS (0x0000ffffU) #define NV0000_CTRL_GPU_DETACH_IDS_PARAMS_MESSAGE_ID (0x16U) @@ -455,7 +455,7 @@ typedef struct NV0000_CTRL_GPU_DETACH_IDS_PARAMS { * NV_ERR_INVALID_STATE * */ -#define NV0000_CTRL_CMD_GPU_GET_SVM_SIZE (0x240) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_GPU_GET_SVM_SIZE (0x240U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS_MESSAGE_ID" */ #define NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS_MESSAGE_ID (0x40U) @@ -504,10 +504,10 @@ typedef struct NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS { * NV_ERR_OBJECT_NOT_FOUND * */ -#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO (0x274) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO (0x274U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS_MESSAGE_ID" */ /* maximum possible number of bytes of GID information */ -#define NV0000_GPU_MAX_GID_LENGTH (0x00000100) +#define NV0000_GPU_MAX_GID_LENGTH (0x00000100U) #define NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS_MESSAGE_ID (0x74U) @@ -520,12 +520,12 @@ typedef struct NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS { } NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS; #define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT 1:0 -#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_ASCII (0x00000000) -#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_BINARY (0x00000002) +#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_ASCII (0x00000000U) +#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_BINARY (0x00000002U) #define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE 2:2 -#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA1 (0x00000000) -#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA256 (0x00000001) +#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA1 (0x00000000U) +#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA256 (0x00000001U) /* * NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID @@ -566,7 +566,7 @@ typedef struct NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS { * NV_ERR_OBJECT_NOT_FOUND * NV_ERR_OPERATING_SYSTEM */ -#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID (0x275) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID (0x275U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS_MESSAGE_ID" */ #define NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS_MESSAGE_ID (0x75U) @@ -579,13 +579,13 @@ typedef struct NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS { /* valid format values */ #define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT 1:0 -#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_ASCII (0x00000000) -#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_BINARY (0x00000002) +#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_ASCII (0x00000000U) +#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_BINARY (0x00000002U) /*valid type values*/ #define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE 2:2 -#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA1 (0x00000000) -#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA256 (0x00000001) +#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA1 (0x00000000U) +#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA256 (0x00000001U) @@ -630,15 +630,15 @@ typedef struct NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS { * NV_ERR_IN_USE */ -#define NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE (0x278) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE (0x278U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS_MESSAGE_ID" */ /* Possible values of newState */ -#define NV0000_CTRL_GPU_DRAIN_STATE_DISABLED (0x00000000) -#define NV0000_CTRL_GPU_DRAIN_STATE_ENABLED (0x00000001) +#define NV0000_CTRL_GPU_DRAIN_STATE_DISABLED (0x00000000U) +#define NV0000_CTRL_GPU_DRAIN_STATE_ENABLED (0x00000001U) /* Defined bits for the "flags" argument */ -#define NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE (0x00000001) -#define NV0000_CTRL_GPU_DRAIN_STATE_FLAG_LINK_DISABLE (0x00000002) +#define NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE (0x00000001U) +#define NV0000_CTRL_GPU_DRAIN_STATE_FLAG_LINK_DISABLE (0x00000002U) #define NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS_MESSAGE_ID (0x78U) @@ -678,7 +678,7 @@ typedef struct NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS { * NV_ERR_INVALID_ARGUMENT */ -#define NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE (0x279) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE (0x279U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS_MESSAGE_ID" */ #define NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS_MESSAGE_ID (0x79U) @@ -716,7 +716,7 @@ typedef struct NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS { * NV_ERR_NOT_SUPPORTED */ -#define NV0000_CTRL_CMD_GPU_DISCOVER (0x27a) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | 0x7A" */ +#define NV0000_CTRL_CMD_GPU_DISCOVER (0x27aU) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | 0x7A" */ typedef struct NV0000_CTRL_GPU_DISCOVER_PARAMS { NvU32 domain; @@ -740,7 +740,7 @@ typedef struct NV0000_CTRL_GPU_DISCOVER_PARAMS { * NV_OK * */ -#define NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE (0x27b) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE (0x27bU) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS_MESSAGE_ID" */ #define NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS_MESSAGE_ID (0x7BU) @@ -748,7 +748,7 @@ typedef struct NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS { NvU32 enableMask; } NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS; -#define NV0000_CTRL_GPU_FLAGS_MEMOP_ENABLE (0x00000001) +#define NV0000_CTRL_GPU_FLAGS_MEMOP_ENABLE (0x00000001U) @@ -770,7 +770,7 @@ typedef struct NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS { * NV_ERR_IN_USE * */ -#define NV0000_CTRL_CMD_GPU_DISABLE_NVLINK_INIT (0x281) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_GPU_DISABLE_NVLINK_INIT (0x281U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS_MESSAGE_ID" */ #define NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS_MESSAGE_ID (0x81U) @@ -781,16 +781,16 @@ typedef struct NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS { } NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS; -#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PARAM_DATA 0x00000175 -#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_IN 6 -#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_OUT 5 +#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PARAM_DATA 0x00000175U +#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_IN 6U +#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_OUT 5U /* * NV0000_CTRL_CMD_GPU_LEGACY_CONFIG * * Path to use legacy RM GetConfig/Set API. This API is being phased out. */ -#define NV0000_CTRL_CMD_GPU_LEGACY_CONFIG (0x282) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_GPU_LEGACY_CONFIG (0x282U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_MESSAGE_ID" */ #define NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_MESSAGE_ID (0x82U) @@ -801,9 +801,6 @@ typedef struct NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS { NvU32 dataType; /* [out] - data union type */ union { - struct { - NvV32 value; - } configGet; struct { NvU32 newValue; NvU32 oldValue; @@ -820,16 +817,15 @@ typedef struct NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS { } data; } NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS; -#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_GET (0x00000000) -#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET (0x00000001) -#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_GET_EX (0x00000002) -#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET_EX (0x00000003) -#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_RESERVED (0x00000004) +#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET (0x00000001U) +#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_GET_EX (0x00000002U) +#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET_EX (0x00000003U) +#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_RESERVED (0x00000004U) /* * NV0000_CTRL_CMD_IDLE_CHANNELS */ -#define NV0000_CTRL_CMD_IDLE_CHANNELS (0x283) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_IDLE_CHANNELS (0x283U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS_MESSAGE_ID" */ #define NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS_MESSAGE_ID (0x83U) @@ -847,5 +843,31 @@ typedef struct NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS { NvV32 timeout; } NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS; +#define NV0000_CTRL_GPU_IMAGE_TYPE_GSP (0x00000001U) +#define NV0000_CTRL_GPU_IMAGE_TYPE_GSP_LOG (0x00000002U) + +/* + * NV0000_CTRL_CMD_PUSH_GSP_UCODE + * + * This command is used to push the GSP ucode into RM. + * This function is used only on VMware + * + * Possible status values returned are: + * NV_OK The sent data is stored successfully + * NV_ERR_INVALID_ARGUMENT if the arguments are not proper + * NV_ERR_NO_MEMORY if memory allocation failed + * NV_ERR_NOT_SUPPORTED if function is invoked on non-GSP setup or any + * setup other than VMware host + * + */ +#define NV0000_CTRL_CMD_PUSH_GSP_UCODE (0x285) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS_MESSAGE_ID (0x85U) + +typedef struct NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS { + NvU8 image; + NV_DECLARE_ALIGNED(NvU64 totalSize, 8); + NV_DECLARE_ALIGNED(NvP64 pData, 8); +} NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS; /* _ctrl0000gpu_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h index 0c8cc540d..74b65c799 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h @@ -53,7 +53,7 @@ * NV_OK * NV_ERR_INVALID_STATE */ -#define NV0000_CTRL_CMD_SYSTEM_GET_FEATURES (0x1f0) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_SYSTEM_GET_FEATURES (0x1f0U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS_MESSAGE_ID" */ #define NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS_MESSAGE_ID (0xF0U) @@ -65,14 +65,14 @@ typedef struct NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS { /* Valid feature values */ #define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI 0:0 -#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_FALSE (0x00000000) -#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_TRUE (0x00000001) +#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_TRUE (0x00000001U) #define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI 1:1 -#define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI_FALSE (0x00000000) -#define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI_TRUE (0x00000001) +#define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI_TRUE (0x00000001U) #define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT 2:2 -#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_FALSE (0x00000000) -#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_TRUE (0x00000001) +#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_TRUE (0x00000001U) /* * NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION * @@ -103,7 +103,7 @@ typedef struct NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS { * NV_ERR_INVALID_PARAM_STRUCT */ -#define NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION (0x101) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION (0x101U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID" */ #define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID (0x1U) @@ -195,29 +195,32 @@ typedef struct NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS { * Vendor defined Model and Extended Model combined * stepping * Silicon stepping + * bSEVEnabled + * Secure Encrypted Virtualization enabled/disabled state * * Possible status values returned are: * NV_OK * NV_ERR_INVALID_PARAM_STRUCT */ -#define NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO (0x102) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO (0x102U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS_MESSAGE_ID" */ #define NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS_MESSAGE_ID (0x2U) typedef struct NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS { - NvU32 type; /* processor type */ - NvU32 capabilities; /* processor caps */ - NvU32 clock; /* processor speed (MHz) */ - NvU32 L1DataCacheSize; /* L1 dcache size (KB) */ - NvU32 L2DataCacheSize; /* L2 dcache size (KB) */ - NvU32 dataCacheLineSize; /* L1 dcache bytes/line */ - NvU32 numLogicalCpus; /* logial processor cnt */ - NvU32 numPhysicalCpus; /* physical processor cnt*/ - NvU8 name[52]; /* embedded cpu name */ - NvU32 family; /* Vendor defined Family and Extended Family combined */ - NvU32 model; /* Vendor defined Model and Extended Model combined */ - NvU8 stepping; /* Silicon stepping */ - NvU32 coresOnDie; /* cpu cores per die */ + NvU32 type; /* processor type */ + NvU32 capabilities; /* processor caps */ + NvU32 clock; /* processor speed (MHz) */ + NvU32 L1DataCacheSize; /* L1 dcache size (KB) */ + NvU32 L2DataCacheSize; /* L2 dcache size (KB) */ + NvU32 dataCacheLineSize; /* L1 dcache bytes/line */ + NvU32 numLogicalCpus; /* logial processor cnt */ + NvU32 numPhysicalCpus; /* physical processor cnt*/ + NvU8 name[52]; /* embedded cpu name */ + NvU32 family; /* Vendor defined Family and Extended Family combined */ + NvU32 model; /* Vendor defined Model and Extended Model combined */ + NvU8 stepping; /* Silicon stepping */ + NvU32 coresOnDie; /* cpu cores per die */ + NvBool bSEVEnabled; /* SEV enabled on cpu */ } NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS; // Macros for CPU family information @@ -242,83 +245,85 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS { #define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_MODEL 0x9 /* processor type values */ -#define NV0000_CTRL_SYSTEM_CPU_TYPE_UNKNOWN (0x00000000) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_UNKNOWN (0x00000000U) /* Intel types */ -#define NV0000_CTRL_SYSTEM_CPU_TYPE_P5 (0x00000001) -#define NV0000_CTRL_SYSTEM_CPU_TYPE_P55 (0x00000002) -#define NV0000_CTRL_SYSTEM_CPU_TYPE_P6 (0x00000003) -#define NV0000_CTRL_SYSTEM_CPU_TYPE_P2 (0x00000004) -#define NV0000_CTRL_SYSTEM_CPU_TYPE_P2XC (0x00000005) -#define NV0000_CTRL_SYSTEM_CPU_TYPE_CELA (0x00000006) -#define NV0000_CTRL_SYSTEM_CPU_TYPE_P3 (0x00000007) -#define NV0000_CTRL_SYSTEM_CPU_TYPE_P3_INTL2 (0x00000008) -#define NV0000_CTRL_SYSTEM_CPU_TYPE_P4 (0x00000009) -#define NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2 (0x00000010) -#define NV0000_CTRL_SYSTEM_CPU_TYPE_CELN_M16H (0x00000011) -#define NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2_EXTRM (0x00000012) -#define NV0000_CTRL_SYSTEM_CPU_TYPE_ATOM (0x00000013) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_P5 (0x00000001U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_P55 (0x00000002U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_P6 (0x00000003U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_P2 (0x00000004U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_P2XC (0x00000005U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_CELA (0x00000006U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_P3 (0x00000007U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_P3_INTL2 (0x00000008U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_P4 (0x00000009U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2 (0x00000010U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_CELN_M16H (0x00000011U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2_EXTRM (0x00000012U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_ATOM (0x00000013U) /* AMD types */ -#define NV0000_CTRL_SYSTEM_CPU_TYPE_K5 (0x00000030) -#define NV0000_CTRL_SYSTEM_CPU_TYPE_K6 (0x00000031) -#define NV0000_CTRL_SYSTEM_CPU_TYPE_K62 (0x00000032) -#define NV0000_CTRL_SYSTEM_CPU_TYPE_K63 (0x00000033) -#define NV0000_CTRL_SYSTEM_CPU_TYPE_K7 (0x00000034) -#define NV0000_CTRL_SYSTEM_CPU_TYPE_K8 (0x00000035) -#define NV0000_CTRL_SYSTEM_CPU_TYPE_K10 (0x00000036) -#define NV0000_CTRL_SYSTEM_CPU_TYPE_K11 (0x00000037) -#define NV0000_CTRL_SYSTEM_CPU_TYPE_RYZEN (0x00000038) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_K5 (0x00000030U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_K6 (0x00000031U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_K62 (0x00000032U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_K63 (0x00000033U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_K7 (0x00000034U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_K8 (0x00000035U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_K10 (0x00000036U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_K11 (0x00000037U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_RYZEN (0x00000038U) /* IDT/Centaur types */ -#define NV0000_CTRL_SYSTEM_CPU_TYPE_C6 (0x00000060) -#define NV0000_CTRL_SYSTEM_CPU_TYPE_C62 (0x00000061) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_C6 (0x00000060U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_C62 (0x00000061U) /* Cyrix types */ -#define NV0000_CTRL_SYSTEM_CPU_TYPE_GX (0x00000070) -#define NV0000_CTRL_SYSTEM_CPU_TYPE_M1 (0x00000071) -#define NV0000_CTRL_SYSTEM_CPU_TYPE_M2 (0x00000072) -#define NV0000_CTRL_SYSTEM_CPU_TYPE_MGX (0x00000073) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_GX (0x00000070U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_M1 (0x00000071U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_M2 (0x00000072U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_MGX (0x00000073U) /* Transmeta types */ -#define NV0000_CTRL_SYSTEM_CPU_TYPE_TM_CRUSOE (0x00000080) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_TM_CRUSOE (0x00000080U) /* IBM types */ -#define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC603 (0x00000090) -#define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC604 (0x00000091) -#define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC750 (0x00000092) -#define NV0000_CTRL_SYSTEM_CPU_TYPE_POWERN (0x00000093) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC603 (0x00000090U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC604 (0x00000091U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC750 (0x00000092U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_POWERN (0x00000093U) /* Unknown ARM architecture CPU type */ -#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_UNKNOWN (0xA0000000) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_UNKNOWN (0xA0000000U) /* ARM Ltd types */ -#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A9 (0xA0000009) -#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A15 (0xA000000F) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A9 (0xA0000009U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A15 (0xA000000FU) /* NVIDIA types */ -#define NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_1_0 (0xA0001000) -#define NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_2_0 (0xA0002000) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_1_0 (0xA0001000U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_2_0 (0xA0002000U) /* Generic types */ -#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC (0xA00FF000) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC (0xA00FF000U) + + /* processor capabilities */ -#define NV0000_CTRL_SYSTEM_CPU_CAP_MMX (0x00000001) -#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE (0x00000002) -#define NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW (0x00000004) -#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE2 (0x00000008) -#define NV0000_CTRL_SYSTEM_CPU_CAP_SFENCE (0x00000010) -#define NV0000_CTRL_SYSTEM_CPU_CAP_WRITE_COMBINING (0x00000020) -#define NV0000_CTRL_SYSTEM_CPU_CAP_ALTIVEC (0x00000040) -#define NV0000_CTRL_SYSTEM_CPU_CAP_PUT_NEEDS_IO (0x00000080) -#define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WC_WORKAROUND (0x00000100) -#define NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW_EXT (0x00000200) -#define NV0000_CTRL_SYSTEM_CPU_CAP_MMX_EXT (0x00000400) -#define NV0000_CTRL_SYSTEM_CPU_CAP_CMOV (0x00000800) -#define NV0000_CTRL_SYSTEM_CPU_CAP_CLFLUSH (0x00001000) -#define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_190854 (0x00002000) /* deprecated */ -#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE3 (0x00004000) -#define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_124888 (0x00008000) -#define NV0000_CTRL_SYSTEM_CPU_CAP_HT_CAPABLE (0x00010000) -#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE41 (0x00020000) -#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE42 (0x00040000) -#define NV0000_CTRL_SYSTEM_CPU_CAP_AVX (0x00080000) -#define NV0000_CTRL_SYSTEM_CPU_CAP_ERMS (0x00100000) +#define NV0000_CTRL_SYSTEM_CPU_CAP_MMX (0x00000001U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE (0x00000002U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW (0x00000004U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE2 (0x00000008U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_SFENCE (0x00000010U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_WRITE_COMBINING (0x00000020U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_ALTIVEC (0x00000040U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_PUT_NEEDS_IO (0x00000080U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WC_WORKAROUND (0x00000100U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW_EXT (0x00000200U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_MMX_EXT (0x00000400U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_CMOV (0x00000800U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_CLFLUSH (0x00001000U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_190854 (0x00002000U) /* deprecated */ +#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE3 (0x00004000U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_124888 (0x00008000U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_HT_CAPABLE (0x00010000U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE41 (0x00020000U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE42 (0x00040000U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_AVX (0x00080000U) +#define NV0000_CTRL_SYSTEM_CPU_CAP_ERMS (0x00100000U) /* feature mask (as opposed to bugs, requirements, etc.) */ -#define NV0000_CTRL_SYSTEM_CPU_CAP_FEATURE_MASK (0x1f5e7f) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_CPU_CAP_MMX | NV0000_CTRL_SYSTEM_CPU_CAP_SSE | NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW | NV0000_CTRL_SYSTEM_CPU_CAP_SSE2 | NV0000_CTRL_SYSTEM_CPU_CAP_SFENCE | NV0000_CTRL_SYSTEM_CPU_CAP_WRITE_COMBINING | NV0000_CTRL_SYSTEM_CPU_CAP_ALTIVEC | NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW_EXT | NV0000_CTRL_SYSTEM_CPU_CAP_MMX_EXT | NV0000_CTRL_SYSTEM_CPU_CAP_CMOV | NV0000_CTRL_SYSTEM_CPU_CAP_CLFLUSH | NV0000_CTRL_SYSTEM_CPU_CAP_SSE3 | NV0000_CTRL_SYSTEM_CPU_CAP_HT_CAPABLE | NV0000_CTRL_SYSTEM_CPU_CAP_SSE41 | NV0000_CTRL_SYSTEM_CPU_CAP_SSE42 | NV0000_CTRL_SYSTEM_CPU_CAP_AVX | NV0000_CTRL_SYSTEM_CPU_CAP_ERMS)" */ +#define NV0000_CTRL_SYSTEM_CPU_CAP_FEATURE_MASK (0x1f5e7fU) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_CPU_CAP_MMX | NV0000_CTRL_SYSTEM_CPU_CAP_SSE | NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW | NV0000_CTRL_SYSTEM_CPU_CAP_SSE2 | NV0000_CTRL_SYSTEM_CPU_CAP_SFENCE | NV0000_CTRL_SYSTEM_CPU_CAP_WRITE_COMBINING | NV0000_CTRL_SYSTEM_CPU_CAP_ALTIVEC | NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW_EXT | NV0000_CTRL_SYSTEM_CPU_CAP_MMX_EXT | NV0000_CTRL_SYSTEM_CPU_CAP_CMOV | NV0000_CTRL_SYSTEM_CPU_CAP_CLFLUSH | NV0000_CTRL_SYSTEM_CPU_CAP_SSE3 | NV0000_CTRL_SYSTEM_CPU_CAP_HT_CAPABLE | NV0000_CTRL_SYSTEM_CPU_CAP_SSE41 | NV0000_CTRL_SYSTEM_CPU_CAP_SSE42 | NV0000_CTRL_SYSTEM_CPU_CAP_AVX | NV0000_CTRL_SYSTEM_CPU_CAP_ERMS)" */ /* * NV0000_CTRL_CMD_SYSTEM_GET_CAPS @@ -342,7 +347,7 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS { * NV_ERR_INVALID_PARAM_STRUCT * NV_ERR_INVALID_ARGUMENT */ -#define NV0000_CTRL_CMD_SYSTEM_GET_CAPS (0x103) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x3" */ +#define NV0000_CTRL_CMD_SYSTEM_GET_CAPS (0x103U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x3" */ typedef struct NV0000_CTRL_SYSTEM_GET_CAPS_PARAMS { NvU32 capsTblSize; @@ -356,7 +361,7 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CAPS_PARAMS { #define NV0000_CTRL_SYSTEM_CAPS_POWER_SLI_SUPPORTED 0:0x01 /* size in bytes of system caps table */ -#define NV0000_CTRL_SYSTEM_CAPS_TBL_SIZE 1 +#define NV0000_CTRL_SYSTEM_CAPS_TBL_SIZE 1U /* * NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO @@ -414,13 +419,13 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CAPS_PARAMS { * NV_ERR_INVALID_ARGUMENT * NV_ERR_OPERATING_SYSTEM */ -#define NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO (0x104) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO (0x104U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID" */ /* maximum name string length */ -#define NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH (0x0000020) +#define NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH (0x0000020U) /* invalid id */ -#define NV0000_SYSTEM_CHIPSET_INVALID_ID (0xffff) +#define NV0000_SYSTEM_CHIPSET_INVALID_ID (0xffffU) #define NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID (0x4U) @@ -442,8 +447,8 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS { } NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS; #define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE 0:0 -#define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_NO (0x00000000) -#define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_YES (0x00000001) +#define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_NO (0x00000000U) +#define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_YES (0x00000001U) @@ -461,7 +466,7 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS { * NV_OK * NV_ERR_INVALID_PARAM_STRUCT */ -#define NV0000_CTRL_CMD_SYSTEM_SET_MEMORY_SIZE (0x107) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_SYSTEM_SET_MEMORY_SIZE (0x107U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS_MESSAGE_ID" */ #define NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS_MESSAGE_ID (0x7U) @@ -487,10 +492,10 @@ typedef struct NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS { * NV_ERR_INVALID_PARAM_STRUCT */ -#define NV0000_CTRL_CMD_SYSTEM_GET_CLASSLIST (0x108) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_SYSTEM_GET_CLASSLIST (0x108U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS_MESSAGE_ID" */ /* maximum number of classes returned in classes[] array */ -#define NV0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE (32) +#define NV0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE (32U) #define NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS_MESSAGE_ID (0x8U) @@ -525,7 +530,7 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS { * Sync this up (#defines) with one in nvapi.spec! * (NV_ACPI_EVENT_TYPE & NV_ACPI_EVENT_DATA) */ -#define NV0000_CTRL_CMD_SYSTEM_NOTIFY_EVENT (0x110) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_SYSTEM_NOTIFY_EVENT (0x110U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS_MESSAGE_ID" */ #define NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS_MESSAGE_ID (0x10U) @@ -536,35 +541,35 @@ typedef struct NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS { } NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS; /* valid eventType values */ -#define NV0000_CTRL_SYSTEM_EVENT_TYPE_LID_STATE (0x00000000) -#define NV0000_CTRL_SYSTEM_EVENT_TYPE_POWER_SOURCE (0x00000001) -#define NV0000_CTRL_SYSTEM_EVENT_TYPE_DOCK_STATE (0x00000002) -#define NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_LID (0x00000003) -#define NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_DOCK (0x00000004) +#define NV0000_CTRL_SYSTEM_EVENT_TYPE_LID_STATE (0x00000000U) +#define NV0000_CTRL_SYSTEM_EVENT_TYPE_POWER_SOURCE (0x00000001U) +#define NV0000_CTRL_SYSTEM_EVENT_TYPE_DOCK_STATE (0x00000002U) +#define NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_LID (0x00000003U) +#define NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_DOCK (0x00000004U) /* valid eventData values */ -#define NV0000_CTRL_SYSTEM_EVENT_DATA_LID_OPEN (0x00000000) -#define NV0000_CTRL_SYSTEM_EVENT_DATA_LID_CLOSED (0x00000001) -#define NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_BATTERY (0x00000000) -#define NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_AC (0x00000001) -#define NV0000_CTRL_SYSTEM_EVENT_DATA_UNDOCKED (0x00000000) -#define NV0000_CTRL_SYSTEM_EVENT_DATA_DOCKED (0x00000001) -#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DSM (0x00000000) -#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DCS (0x00000001) -#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_NVIF (0x00000002) -#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_ACPI (0x00000003) -#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_POLL (0x00000004) -#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_COUNT (0x5) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_POLL + 1)" */ -#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DSM (0x00000000) -#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DCS (0x00000001) -#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_NVIF (0x00000002) -#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_ACPI (0x00000003) -#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_POLL (0x00000004) -#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_COUNT (0x5) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_POLL + 1)" */ +#define NV0000_CTRL_SYSTEM_EVENT_DATA_LID_OPEN (0x00000000U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_LID_CLOSED (0x00000001U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_BATTERY (0x00000000U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_AC (0x00000001U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_UNDOCKED (0x00000000U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_DOCKED (0x00000001U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DSM (0x00000000U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DCS (0x00000001U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_NVIF (0x00000002U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_ACPI (0x00000003U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_POLL (0x00000004U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_COUNT (0x5U) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_POLL + 1)" */ +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DSM (0x00000000U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DCS (0x00000001U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_NVIF (0x00000002U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_ACPI (0x00000003U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_POLL (0x00000004U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_COUNT (0x5U) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_POLL + 1)" */ /* valid bEventDataForced values */ -#define NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_FALSE (0x00000000) -#define NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_TRUE (0x00000001) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_TRUE (0x00000001U) /* * NV000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE @@ -589,7 +594,7 @@ typedef struct NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS { * NV_ERR_INVALID_PARAM_STRUCT * NV_ERR_INVALID_ARGUMENT */ -#define NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE (0x111) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE (0x111U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS_MESSAGE_ID" */ #define NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS_MESSAGE_ID (0x11U) @@ -598,10 +603,10 @@ typedef struct NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS { } NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS; /* valid systemType values */ -#define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP (0x000000) -#define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_GENERIC (0x000001) -#define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_TOSHIBA (0x000002) -#define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_SOC (0x000003) +#define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP (0x000000U) +#define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_GENERIC (0x000001U) +#define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_TOSHIBA (0x000002U) +#define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_SOC (0x000003U) @@ -628,12 +633,12 @@ typedef struct NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS { * NV_ERR_INVALID_ARGUMENT * NV_ERR_NOT_SUPPORTED */ -#define NV0000_CTRL_CMD_SYSTEM_DEBUG_RMMSG_CTRL (0x121) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_SYSTEM_DEBUG_RMMSG_CTRL (0x121U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS_MESSAGE_ID" */ -#define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_SIZE 512 +#define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_SIZE 512U -#define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_GET (0x00000000) -#define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_SET (0x00000001) +#define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_GET (0x00000000U) +#define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_SET (0x00000001U) #define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS_MESSAGE_ID (0x21U) @@ -672,7 +677,7 @@ typedef struct NV0000_CTRL_SYSTEM_HWBC_INFO { NvU32 secondaryBus; } NV0000_CTRL_SYSTEM_HWBC_INFO; -#define NV0000_CTRL_SYSTEM_HWBC_INVALID_ID (0xFFFFFFFF) +#define NV0000_CTRL_SYSTEM_HWBC_INVALID_ID (0xFFFFFFFFU) /* * NV0000_CTRL_CMD_SYSTEM_GET_HWBC_INFO @@ -695,9 +700,9 @@ typedef struct NV0000_CTRL_SYSTEM_HWBC_INFO { * NV_OK * NV_ERR_INVALID_ARGUMENT */ -#define NV0000_CTRL_CMD_SYSTEM_GET_HWBC_INFO (0x124) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_SYSTEM_GET_HWBC_INFO (0x124U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS_MESSAGE_ID" */ -#define NV0000_CTRL_SYSTEM_MAX_HWBCS (0x00000080) +#define NV0000_CTRL_SYSTEM_MAX_HWBCS (0x00000080U) #define NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS_MESSAGE_ID (0x24U) @@ -705,12 +710,346 @@ typedef struct NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS { NV0000_CTRL_SYSTEM_HWBC_INFO hwbcInfo[NV0000_CTRL_SYSTEM_MAX_HWBCS]; } NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS; +/* + * NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL + * + * This command is used to control GPS functionality. It allows control of + * GPU Performance Scaling (GPS), changing its operational parameters and read + * most GPS dynamic parameters. + * + * command + * This parameter specifies the command to execute. Invalid commands + * result in the return of an NV_ERR_INVALID_ARGUMENT status. + * locale + * This parameter indicates the specific locale to which the command + * 'command' is to be applied. + * Supported range of CPU/GPU {i = 0, ..., 255} + * data + * This parameter contains a command-specific data payload. It can + * be used to input data as well as output data. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_COMMAND + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_DATA + * NV_ERR_INVALID_REQUEST + * NV_ERR_NOT_SUPPORTED + */ +#define NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL (0x122U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS_MESSAGE_ID (0x22U) + +typedef struct NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS { + NvU16 command; + NvU16 locale; + NvU32 data; +} NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS; + +/* + * Valid command values : + * + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_INIT + * Is used to check if GPS was correctly initialized. + * Possible return (OUT) values are: + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_NO + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_YES + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_EXEC + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_EXEC + * Are used to stop/start GPS functionality and to get current status. + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_STOP + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_START + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_ACTIONS + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_ACTIONS + * Are used to control execution of GPS actions and to get current status. + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_OFF + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_ON + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_LOGIC + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_LOGIC + * Are used to switch current GPS logic and to retrieve current logic. + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_OFF + * Will cause that all GPS actions will be NULL. + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_FUZZY + * Fuzzy logic will determine GPS actions based on current ruleset. + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_DETERMINISTIC + * Deterministic logic will define GPS actions based on current ruleset. + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PREFERENCE + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PREFERENCE + * Are used to set/retrieve system control preference. + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_CPU + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_GPU + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_BOTH + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_GPU2CPU_LIMIT + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_GPU2CPU_LIMIT + * Are used to set/retrieve GPU2CPU pstate limits. + * IN/OUT values are four bytes packed into a 32-bit data field. + * The CPU cap index for GPU pstate 0 is in the lowest byte, the CPU cap + * index for the GPU pstate 3 is in the highest byte, etc. One + * special value is to disable the override to the GPU2CPU map: + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PMU_GPS_STATE + * Is used to stop/start GPS PMU functionality. + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PMU_GPS_STATE + * Is used to get the current status of PMU GPS. + * NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_NO_MAP_OVERRIDE + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_MAX_POWER + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_MAX_POWER + * Are used to set/retrieve max power [mW] that system can provide. + * This is hardcoded GPS safety feature and logic/rules does not apply + * to this threshold. + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_COOLING_BUDGET + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_COOLING_BUDGET + * Are used to set/retrieve current system cooling budget [mW]. + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_INTEGRAL_PERIOD + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_INTEGRAL_PERIOD + * Are used to set/retrieve integration interval [sec]. + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_RULESET + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULESET + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULE_COUNT + * Are used to set/retrieve used ruleset [#]. Value is checked + * against MAX number of rules for currently used GPS logic. Also COUNT + * provides a way to find out how many rules exist for the current control + * system. + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_APP_BOOST + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_APP_BOOST + * Is used to set/get a delay relative to now during which to allow unbound + * CPU performance. Units are seconds. + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_PWR_SUPPLY_MODE + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_PWR_SUPPLY_MODE + * Is used to override/get the actual power supply mode (AC/Battery). + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_REAL + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_AC + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_BATT + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_VCT_SUPPORT_INFO + * Is used to get the Ventura system information for VCT tool + * Returned 32bit value should be treated as bitmask and decoded in + * following way: + * Encoding details are defined in objgps.h refer to + * NV_GPS_SYS_SUPPORT_INFO and corresponding bit defines. + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_SUPPORTED_FUNCTION + * Is used to get the supported sub-functions defined in SBIOS. Returned + * value is a bitmask where each bit corresponds to different function: + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SUPPORT + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURASTATUS + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPSS + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SETPPC + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPPC + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURACB + * NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SYSPARAMS + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_DELTA + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_FUTURE + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_LTMAVG + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTEGRAL + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_BURDEN + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTERMEDIATE + * Are used to retrieve appropriate power measurements and their derivatives + * in [mW] for required locale. _BURDEN is defined only for _LOCALE_SYSTEM. + * _INTERMEDIATE is not defined for _LOCALE_SYSTEM, and takes an In value as + * index. + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_SENSOR_PARAMETERS + * Is used to retrieve parameters when adjusting raw sensor power reading. + * The values may come from SBIOS, VBIOS, registry or driver default. + * Possible IN value is the index of interested parameter. + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_DELTA + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_FUTURE + * Are used to retrieve appropriate temperature measurements and their + * derivatives in [1/1000 Celsius]. + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_CAP + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MIN + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MAX + * Are used to retrieve CPU(x)/GPU(x) p-state or it's limits. + * Not applicable to _LOCALE_SYSTEM. + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_ACTION + * Is used to retrieve last GPS action for given domain. + * Not applicable to _LOCALE_SYSTEM. + * Possible return (OUT) values are: + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_TO_P0 + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_BY_1 + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DO_NOTHING + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_SET_CURRENT + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_1 + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_2 + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_LFM + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_SLFM + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_STATE + * Is used to set the power sensor simulator state. + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_STATE + * Is used to get the power simulator sensor simulator state. + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_DATA + * Is used to set power sensor simulator data + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_DATA + * Is used to get power sensor simulator data + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_INIT_USING_SBIOS_AND_ACK + * Is used to respond to the ACPI event triggered by SBIOS. RM will + * request value for budget and status, validate them, apply them + * and send ACK back to SBIOS. + * NV0000_CTRL_CMD_SYSTEM_GPS_DATA_PING_SBIOS_FOR_EVENT + * Is a test cmd that should notify SBIOS to send ACPI event requesting + * budget and status change. + */ +#define NV0000_CTRL_CMD_SYSTEM_GPS_INVALID (0xFFFFU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_INIT (0x0000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_EXEC (0x0001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_EXEC (0x0002U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_ACTIONS (0x0003U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_ACTIONS (0x0004U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_LOGIC (0x0005U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_LOGIC (0x0006U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PREFERENCE (0x0007U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PREFERENCE (0x0008U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_GPU2CPU_LIMIT (0x0009U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_GPU2CPU_LIMIT (0x000AU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_SET_PMU_GPS_STATE (0x000BU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_GET_PMU_GPS_STATE (0x000CU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_MAX_POWER (0x0100U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_MAX_POWER (0x0101U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_COOLING_BUDGET (0x0102U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_COOLING_BUDGET (0x0103U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_INTEGRAL_PERIOD (0x0104U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_INTEGRAL_PERIOD (0x0105U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_RULESET (0x0106U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULESET (0x0107U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_RULE_COUNT (0x0108U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_APP_BOOST (0x0109U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_APP_BOOST (0x010AU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_SET_PWR_SUPPLY_MODE (0x010BU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_PWR_SUPPLY_MODE (0x010CU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_VCT_SUPPORT_INFO (0x010DU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_GET_SUPPORTED_FUNCTIONS (0x010EU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER (0x0200U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_DELTA (0x0201U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_FUTURE (0x0202U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_LTMAVG (0x0203U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTEGRAL (0x0204U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_BURDEN (0x0205U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_INTERMEDIATE (0x0206U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_SENSOR_PARAMETERS (0x0210U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP (0x0220U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_DELTA (0x0221U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_TEMP_FUTURE (0x0222U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE (0x0240U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_CAP (0x0241U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MIN (0x0242U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_MAX (0x0243U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_ACTION (0x0244U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_PSTATE_SLFM_PRESENT (0x0245U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_STATE (0x0250U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_STATE (0x0251U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_SET_POWER_SIM_DATA (0x0252U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_GET_POWER_SIM_DATA (0x0253U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_INIT_USING_SBIOS_AND_ACK (0x0320U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_PING_SBIOS_FOR_EVENT (0x0321U) + +/* valid LOCALE values */ +#define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_INVALID (0xFFFFU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_SYSTEM (0x0000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_CPU(i) (0x0100+((i)%0x100)) +#define NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_GPU(i) (0x0200+((i)%0x100)) + +/* valid data values for enums */ +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INVALID (0x80000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_NO (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INIT_YES (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_STOP (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_EXEC_START (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_OFF (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_ACTIONS_ON (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_OFF (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_FUZZY (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_LOGIC_DETERMINISTIC (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_CPU (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_GPU (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PREFERENCE_BOTH (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_NO_MAP_OVERRIDE (0xFFFFFFFFU) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_OFF (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_PMU_GPS_STATE_ON (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_REAL (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_AC (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_PWR_SUPPLY_FAKE_BATT (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SUPPORT (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURASTATUS (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPSS (0x00000004U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SETPPC (0x00000008U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_GETPPC (0x00000010U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_VENTURACB (0x00000020U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_SYS_DEF_FUNC_SYSPARAMS (0x00000040U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_TO_P0 (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DEC_BY_1 (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_DO_NOTHING (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_SET_CURRENT (0x00000003U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_1 (0x00000004U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_BY_2 (0x00000005U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_LFM (0x00000006U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_ACTION_INC_TO_SLFM (0x00000007U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_NO (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_SLFM_PRESENT_YES (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_OFF (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_GPS_DATA_DEF_POWER_SIM_STATE_ON (0x00000001U) + +/* + * NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_CONTROL + * + * This command allows execution of multiple GpsControl commands within one + * RmControl call. For practical reasons # of commands is limited to 16. + * This command shares defines with NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL. + * + * cmdCount + * Number of commands that should be executed. + * Less or equal to NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX. + * + * succeeded + * Number of commands that were succesully executed. + * Less or equal to NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX. + * Failing commands return NV0000_CTRL_CMD_SYSTEM_GPS_CMD_DEF_INVALID + * in their data field. + * + * cmdData + * Array of commands with following structure: + * command + * This parameter specifies the command to execute. + * Invalid commands result in the return of an + * NV_ERR_INVALID_ARGUMENT status. + * locale + * This parameter indicates the specific locale to which + * the command 'command' is to be applied. + * Supported range of CPU/GPU {i = 0, ..., 255} + * data + * This parameter contains a command-specific data payload. + * It is used both to input data as well as to output data. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_NOT_SUPPORTED + */ +#define NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_CONTROL (0x123U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX (16U) +#define NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS_MESSAGE_ID (0x23U) + +typedef struct NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS { + NvU32 cmdCount; + NvU32 succeeded; + + struct { + NvU16 command; + NvU16 locale; + NvU32 data; + } cmdData[NV0000_CTRL_CMD_SYSTEM_GPS_BATCH_COMMAND_MAX]; +} NV0000_CTRL_SYSTEM_GPS_BATCH_CONTROL_PARAMS; /* * Deprecated. Please use NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 instead. */ -#define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS (0x127) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS (0x127U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_MESSAGE_ID" */ /* * NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED must remain equal to the square of @@ -719,23 +1058,23 @@ typedef struct NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS { * allowed for batched P2P caps queries provided by the RM control * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX. */ -#define NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS 32 -#define NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED 1024 -#define NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS 8 -#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER 0xffffffff +#define NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS 32U +#define NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED 1024U +#define NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS 8U +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER 0xffffffffU /* P2P capabilities status index values */ -#define NV0000_CTRL_P2P_CAPS_INDEX_READ 0 -#define NV0000_CTRL_P2P_CAPS_INDEX_WRITE 1 -#define NV0000_CTRL_P2P_CAPS_INDEX_NVLINK 2 -#define NV0000_CTRL_P2P_CAPS_INDEX_ATOMICS 3 -#define NV0000_CTRL_P2P_CAPS_INDEX_PROP 4 -#define NV0000_CTRL_P2P_CAPS_INDEX_LOOPBACK 5 -#define NV0000_CTRL_P2P_CAPS_INDEX_PCI 6 -#define NV0000_CTRL_P2P_CAPS_INDEX_C2C 7 -#define NV0000_CTRL_P2P_CAPS_INDEX_PCI_BAR1 8 +#define NV0000_CTRL_P2P_CAPS_INDEX_READ 0U +#define NV0000_CTRL_P2P_CAPS_INDEX_WRITE 1U +#define NV0000_CTRL_P2P_CAPS_INDEX_NVLINK 2U +#define NV0000_CTRL_P2P_CAPS_INDEX_ATOMICS 3U +#define NV0000_CTRL_P2P_CAPS_INDEX_PROP 4U +#define NV0000_CTRL_P2P_CAPS_INDEX_LOOPBACK 5U +#define NV0000_CTRL_P2P_CAPS_INDEX_PCI 6U +#define NV0000_CTRL_P2P_CAPS_INDEX_C2C 7U +#define NV0000_CTRL_P2P_CAPS_INDEX_PCI_BAR1 8U -#define NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE 9 +#define NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE 9U #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_MESSAGE_ID (0x27U) @@ -752,54 +1091,54 @@ typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS { /* valid p2pCaps values */ #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED 0:0 -#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_FALSE (0x00000000) -#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_TRUE (0x00000001) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_TRUE (0x00000001U) #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED 1:1 -#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_FALSE (0x00000000) -#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_TRUE (0x00000001) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_TRUE (0x00000001U) #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED 2:2 -#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_FALSE (0x00000000) -#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_TRUE (0x00000001) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_TRUE (0x00000001U) #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED 3:3 -#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_FALSE (0x00000000) -#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_TRUE (0x00000001) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_TRUE (0x00000001U) #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED 4:4 -#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_FALSE (0x00000000) -#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_TRUE (0x00000001) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_TRUE (0x00000001U) #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED 5:5 -#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_FALSE (0x00000000) -#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_TRUE (0x00000001) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_TRUE (0x00000001U) #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED 6:6 -#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_FALSE (0x00000000) -#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_TRUE (0x00000001) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_TRUE (0x00000001U) #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED 7:7 -#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_FALSE (0x00000000) -#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_TRUE (0x00000001) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_TRUE (0x00000001U) #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED 8:8 -#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_FALSE (0x00000000) -#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_TRUE (0x00000001) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_TRUE (0x00000001U) #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED 9:9 -#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_FALSE (0x00000000) -#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_TRUE (0x00000001) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_TRUE (0x00000001U) #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED 10:10 -#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_FALSE (0x00000000) -#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_TRUE (0x00000001) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_TRUE (0x00000001U) #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED 12:12 -#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_FALSE (0x00000000) -#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_TRUE (0x00000001) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_TRUE (0x00000001U) #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED 13:13 -#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_FALSE (0x00000000) -#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_TRUE (0x00000001) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_TRUE (0x00000001U) /* P2P status codes */ -#define NV0000_P2P_CAPS_STATUS_OK (0x00) -#define NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED (0x01) -#define NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED (0x02) -#define NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED (0x03) -#define NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY (0x04) -#define NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED (0x05) +#define NV0000_P2P_CAPS_STATUS_OK (0x00U) +#define NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED (0x01U) +#define NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED (0x02U) +#define NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED (0x03U) +#define NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY (0x04U) +#define NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED (0x05U) /* * NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 @@ -889,7 +1228,8 @@ typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS { */ -#define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 (0x12b) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 (0x12bU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_MESSAGE_ID" */ #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_MESSAGE_ID (0x2BU) @@ -1003,7 +1343,7 @@ typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS { -#define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX (0x13a) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX (0x13aU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_MESSAGE_ID" */ typedef NvU32 NV0000_CTRL_P2P_CAPS_MATRIX_ROW[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; #define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_MESSAGE_ID (0x3AU) @@ -1020,9 +1360,221 @@ typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS { NV0000_CTRL_P2P_CAPS_MATRIX_ROW b2aOptimalWriteCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; } NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS; +/* + * NV0000_CTRL_CMD_SYSTEM_GPS_CTRL + * + * This command is used to execute general GPS Functions, most dealing with + * calling SBIOS, or retrieving cached sensor and GPS state data. + * + * version + * This parameter specifies the version of the interface. Legal values + * for this parameter are 1. + * cmd + * This parameter specifies the GPS API to be invoked. + * Valid values for this parameter are: + * NV0000_CTRL_GPS_CMD_GET_THERM_LIMIT + * This command gets the temperature limit for thermal controller. When + * this command is specified the input parameter contains ???. + * NV0000_CTRL_GPS_CMD_SET_THERM_LIMIT + * This command set the temperature limit for thermal controller. When + * this command is specified the input parameter contains ???. + * input + * This parameter specifies the cmd-specific input value. + * result + * This parameter returns the cmd-specific output value. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_CTRL_CMD_SYSTEM_GPS_CTRL (0x12aU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS_MESSAGE_ID (0x2AU) + +typedef struct NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS { + NvU32 cmd; + NvS32 input[2]; + NvS32 result[4]; +} NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS; + +/* valid version values */ +#define NV0000_CTRL_GPS_PSHARE_PARAMS_PSP_CURRENT_VERSION (0x00010000U) + +/* valid cmd values */ +#define NV0000_CTRL_GPS_CMD_TYPE_GET_THERM_LIMIT (0x00000002U) +#define NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000U) +#define NV0000_CTRL_GPS_RESULT_THERMAL_LIMIT (0x00000000U) +#define NV0000_CTRL_GPS_RESULT_MIN_LIMIT (0x00000001U) +#define NV0000_CTRL_GPS_RESULT_MAX_LIMIT (0x00000002U) +#define NV0000_CTRL_GPS_RESULT_LIMIT_SOURCE (0x00000003U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_THERM_LIMIT (0x00000003U) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_INPUT_THERMAL_LIMIT (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA (0x00000004U) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DOWN_N_DELTA (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA (0x00000005U) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DOWN_N_DELTA (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA (0x00000006U) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_HOLD_DELTA (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA (0x00000007U) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_HOLD_DELTA (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA (0x00000008U) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_UP_DELTA (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA (0x00000009U) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_UP_DELTA (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA (0x0000000AU) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_ENGAGE_DELTA (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA (0x0000000BU) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_ENGAGE_DELTA (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000CU) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000DU) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_CTRL_STATUS (0x00000016U) +#define NV0000_CTRL_GPS_RESULT_TEMP_CTRL_STATUS (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_CTRL_STATUS (0x00000017U) +#define NV0000_CTRL_GPS_INPUT_TEMP_CTRL_STATUS (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM (0x00000018U) +#define NV0000_CTRL_GPS_RESULT_CPU_SET_UTIL_AVG_NUM (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM (0x00000019U) +#define NV0000_CTRL_GPS_INPUT_CPU_GET_UTIL_AVG_NUM (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_PERF_SENSOR (0x0000001AU) +// NV0000_CTRL_GPS_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_GPS_INPUT_NEXT_EXPECTED_POLL (0x00000001U) +#define NV0000_CTRL_GPS_RESULT_PERF_SENSOR_VALUE (0x00000000U) +#define NV0000_CTRL_GPS_RESULT_PERF_SENSOR_AVAILABLE (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_CALL_ACPI (0x0000001BU) +#define NV0000_CTRL_GPS_INPUT_ACPI_CMD (0x00000000U) +#define NV0000_CTRL_GPS_INPUT_ACPI_PARAM_IN (0x00000001U) +#define NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_1 (0x00000000U) +#define NV0000_CTRL_GPS_OUTPUT_ACPI_RESULT_2 (0x00000001U) +#define NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_STATUS (0x00000000U) +#define NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_VERSION (0x00000001U) +#define NV0000_CTRL_GPS_OUTPUT_ACPI_PSHAREPARAM_SZ (0x00000002U) +#define NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_SZ (0x00000000U) +#define NV0000_CTRL_GPS_OUTPUT_ACPI_PSS_COUNT (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_IGPU_TURBO (0x0000001CU) +#define NV0000_CTRL_GPS_INPUT_SET_IGPU_TURBO (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERIOD (0x00000026U) +#define NV0000_CTRL_GPS_INPUT_TEMP_PERIOD (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERIOD (0x00000027U) +#define NV0000_CTRL_GPS_RESULT_TEMP_PERIOD (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_NUDGE_FACTOR (0x00000028U) +#define NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_UP (0x00000000U) +#define NV0000_CTRL_GPS_INPUT_TEMP_NUDGE_DOWN (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_NUDGE_FACTOR (0x00000029U) +#define NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_UP (0x00000000U) +#define NV0000_CTRL_GPS_RESULT_TEMP_NUDGE_DOWN (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES (0x0000002AU) +#define NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) +#define NV0000_CTRL_GPS_INPUT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES (0x0000002BU) +#define NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) +#define NV0000_CTRL_GPS_RESULT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_TEMP_PERF_LIMITS (0x0000002CU) +#define NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_UPPER (0x00000000U) +#define NV0000_CTRL_GPS_INPUT_TEMP_PERF_LIMIT_LOWER (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_TEMP_PERF_LIMITS (0x0000002DU) +#define NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_UPPER (0x00000000U) +#define NV0000_CTRL_GPS_RESULT_TEMP_PERF_LIMIT_LOWER (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_PM1_AVAILABLE (0x0000002EU) +#define NV0000_CTRL_GPS_INPUT_PM1_AVAILABLE (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_PM1_AVAILABLE (0x0000002FU) +#define NV0000_CTRL_GPS_OUTPUT_PM1_AVAILABLE (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS (0x00000044U) +#define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) +#define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2 (0x00000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS (0x00000045U) +#define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT (0x00000046U) +#define NV0000_CTRL_GPS_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ (0000000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT (0x00000047U) +#define NV0000_CTRL_GPS_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ (0000000000U) + +#define NV0000_CTRL_GPS_CMD_TYPE_GET_PPM (0x00000048U) +#define NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_INDEX (0000000000U) +#define NV0000_CTRL_GPS_CMD_TYPE_GET_PPM_AVAILABLE_MASK (0000000001U) + +#define NV0000_CTRL_GPS_CMD_TYPE_SET_PPM (0x00000049U) +#define NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX (0000000000U) +#define NV0000_CTRL_GPS_CMD_TYPE_SET_PPM_INDEX_MAX (2U) + +#define NV0000_CTRL_GPS_PPM_INDEX 7:0 +#define NV0000_CTRL_GPS_PPM_INDEX_MAXPERF (0U) +#define NV0000_CTRL_GPS_PPM_INDEX_BALANCED (1U) +#define NV0000_CTRL_GPS_PPM_INDEX_QUIET (2U) +#define NV0000_CTRL_GPS_PPM_INDEX_INVALID (0xFFU) +#define NV0000_CTRL_GPS_PPM_MASK 15:8 +#define NV0000_CTRL_GPS_PPM_MASK_INVALID (0U) + +/* valid PS_STATUS result values */ +#define NV0000_CTRL_GPS_CMD_PS_STATUS_OFF (0U) +#define NV0000_CTRL_GPS_CMD_PS_STATUS_ON (1U) -#define GPS_MAX_COUNTERS_PER_BLOCK 32 +/* + * NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS + * + * This command allows privileged users to update the values of + * security settings governing RM behavior. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT, + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INSUFFICIENT_PERMISSIONS + * + * Please note: as implied above, administrator privileges are + * required to modify security settings. + */ +#define NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS (0x129U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x29" */ + +#define GPS_MAX_COUNTERS_PER_BLOCK 32U typedef struct NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS { NvU32 objHndl; NvU32 blockId; @@ -1032,11 +1584,251 @@ typedef struct NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS { NvU32 counterBlock[GPS_MAX_COUNTERS_PER_BLOCK]; } NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS; -#define NV0000_CTRL_CMD_SYSTEM_GPS_GET_PERF_SENSORS (0x12c) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x2C" */ +#define NV0000_CTRL_CMD_SYSTEM_GPS_GET_PERF_SENSORS (0x12cU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x2C" */ -#define NV0000_CTRL_CMD_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS (0x12e) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x2E" */ +#define NV0000_CTRL_CMD_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS (0x12eU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x2E" */ +/* + * NV0000_CTRL_CMD_SYSTEM_GPS_CALL_ACPI + * + * This command allows users to call GPS ACPI commands for testing purposes. + * + * cmd + * This parameter specifies the GPS ACPI command to execute. + * + * input + * This parameter specified the cmd-dependent input value. + * + * resultSz + * This parameter returns the size (in bytes) of the valid data + * returned in the result parameter. + * + * result + * This parameter returns the results of the specified cmd. + * The maximum size (in bytes) of this returned data will + * not exceed GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE + * + * GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE + * The size of buffer (result) in unit of NvU32. + * The smallest value is sizeof(PSS_ENTRY)*ACPI_PSS_ENTRY_MAX. + * Since the prior one is 24 bytes, and the later one is 48, + * this value cannot be smaller than 288. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT, + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INSUFFICIENT_PERMISSIONS + * + */ +#define GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE 288U +#define NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS_MESSAGE_ID (0x2DU) +typedef struct NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS { + NvU32 cmd; + NvU32 input; + NvU32 resultSz; + NvU32 result[GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE]; +} NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS; + +#define NV0000_CTRL_CMD_SYSTEM_GPS_CALL_ACPI (0x12dU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS_MESSAGE_ID" */ + +/* + * NV0000_CTRL_SYSTEM_PARAM_* + * + * The following is a list of system-level parameters (often sensors) that the + * driver can be made aware of. They are primarily intended to be used by system + * power-balancing algorithms that require system-wide visibility in order to + * function. The names and values used here are established and specified in + * several different NVIDIA documents that are made externally available. Thus, + * updates to this list must be made with great caution. The only permissible + * change is to append new parameters. Reordering is strictly prohibited. + * + * Brief Parameter Summary: + * TGPU - GPU temperature (NvTemp) + * PDTS - CPU package temperature (NvTemp) + * SFAN - System fan speed (% of maximum fan speed) + * SKNT - Skin temperature (NvTemp) + * CPUE - CPU energy counter (NvU32) + * TMP1 - Additional temperature sensor 1 (NvTemp) + * TMP2 - Additional temperature sensor 2 (NvTemp) + * CTGP - Mode 2 power limit offset (NvU32) + * PPMD - Power mode data (NvU32) + */ +#define NV0000_CTRL_SYSTEM_PARAM_TGPU (0x00000000U) +#define NV0000_CTRL_SYSTEM_PARAM_PDTS (0x00000001U) +#define NV0000_CTRL_SYSTEM_PARAM_SFAN (0x00000002U) +#define NV0000_CTRL_SYSTEM_PARAM_SKNT (0x00000003U) +#define NV0000_CTRL_SYSTEM_PARAM_CPUE (0x00000004U) +#define NV0000_CTRL_SYSTEM_PARAM_TMP1 (0x00000005U) +#define NV0000_CTRL_SYSTEM_PARAM_TMP2 (0x00000006U) +#define NV0000_CTRL_SYSTEM_PARAM_CTGP (0x00000007U) +#define NV0000_CTRL_SYSTEM_PARAM_PPMD (0x00000008U) +#define NV0000_CTRL_SYSTEM_PARAM_COUNT (0x00000009U) + +/* + * NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD + * + * This command is used to execute general ACPI methods. + * + * method + * This parameter identifies the MXM ACPI API to be invoked. + * Valid values for this parameter are: + * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS + * This value specifies that the DSM NVOP subfunction OPTIMUSCAPS + * API is to be invoked. + * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG + * This value specifies that the DSM NVOP subfunction OPTIMUSFLAG + * API is to be invoked. This API will set a Flag in sbios to Indicate + * that HD Audio Controller is disable/Enabled from GPU Config space. + * This flag will be used by sbios to restore Audio state after resuming + * from s3/s4. + * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_CAPS + * This value specifies that the DSM JT subfunction FUNC_CAPS is to + * to be invoked to get the SBIOS capabilities + * NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_PLATPOLICY + * This value specifies that the DSM JT subfunction FUNC_PLATPOLICY is + * to be invoked to set and get the various platform policies for JT. + * Refer to the JT spec in more detail on various policies. + * inData + * This parameter specifies the method-specific input buffer. Data is + * passed to the specified API using this buffer. + * inDataSize + * This parameter specifies the size of the inData buffer in bytes. + * outStatus + * This parameter returns the status code from the associated ACPI call. + * outData + * This parameter specifies the method-specific output buffer. Data + * is returned by the specified API using this buffer. + * outDataSize + * This parameter specifies the size of the outData buffer in bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD (0x130U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID (0x30U) + +typedef struct NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS { + NvU32 method; + NV_DECLARE_ALIGNED(NvP64 inData, 8); + NvU16 inDataSize; + NvU32 outStatus; + NV_DECLARE_ALIGNED(NvP64 outData, 8); + NvU16 outDataSize; +} NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS; + +/* valid method parameter values */ +#define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS (0x00000000U) +#define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG (0x00000001U) +#define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_CAPS (0x00000002U) +#define NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_PLATPOLICY (0x00000003U) +/* + * NV0000_CTRL_CMD_SYSTEM_ENABLE_ETW_EVENTS + * + * This command can be used to instruct the RM to enable/disable specific module + * of ETW events. + * + * moduleMask + * This parameter specifies the module of events we would like to + * enable/disable. + * + * Possible status values returned are: + * NV_OK + */ +#define NV0000_CTRL_CMD_SYSTEM_ENABLE_ETW_EVENTS (0x131U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS_MESSAGE_ID (0x31U) + +typedef struct NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS { + NvU32 moduleMask; +} NV0000_CTRL_SYSTEM_ENABLE_ETW_EVENTS_PARAMS; + +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ALL (0x00000001U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NOFREQ (0x00000002U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_FLUSH (0x00000004U) + +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PERF (0x00000010U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_ELPG (0x00000020U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVDPS (0x00000040U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_POWER (0x00000080U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_DISP (0x00000100U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RMAPI (0x00000200U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_INTR (0x00000400U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_LOCK (0x00000800U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_RCJOURNAL (0x00001000U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GENERIC (0x00002000U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_THERM (0x00004000U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_GPS (0x00008000U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PCIE (0x00010000U) +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_NVTELEMETRY (0x00020000U) + +/* + * NV0000_CTRL_CMD_SYSTEM_GPS_GET_FRM_DATA + * + * This command is used to read FRL data based on need. + * + * nextSampleNumber + * This parameter returns the counter of next sample which is being filled. + * samples + * This parameter returns the frame time, render time, target time, client ID + * with one reserve bit for future use. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0000_CTRL_CMD_SYSTEM_GPS_GET_FRM_DATA (0x12fU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE_SIZE 64U + +typedef struct NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE { + NvU16 frameTime; + NvU16 renderTime; + NvU16 targetTime; + NvU8 sleepTime; + NvU8 sampleNumber; +} NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE; + +#define NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS_MESSAGE_ID (0x2FU) + +typedef struct NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS { + NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE samples[NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE_SIZE]; + NvU8 nextSampleNumber; +} NV0000_CTRL_SYSTEM_GPS_GET_FRM_DATA_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_GPS_SET_FRM_DATA + * + * This command is used to write FRM data based on need. + * + * frameTime + * This parameter contains the frame time of current frame. + * renderTime + * This parameter contains the render time of current frame. + * targetTime + * This parameter contains the target time of current frame. + * sleepTime + * This parameter contains the sleep duration inserted by FRL for the latest frame. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0000_CTRL_CMD_SYSTEM_GPS_SET_FRM_DATA (0x132U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS_MESSAGE_ID (0x32U) + +typedef struct NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS { + NV0000_CTRL_SYSTEM_GPS_FRM_DATA_SAMPLE sampleData; +} NV0000_CTRL_SYSTEM_GPS_SET_FRM_DATA_PARAMS; /* * NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO @@ -1063,8 +1855,8 @@ typedef struct NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS { * NV_ERR_INVALID_PARAM_STRUCT */ -#define NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE 256 -#define NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO (0x133) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE 256U +#define NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO (0x133U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_MESSAGE_ID" */ #define NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_MESSAGE_ID (0x33U) @@ -1098,7 +1890,7 @@ typedef struct NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS { * NV_ERR_NOT_SUPPORTED */ -#define NV0000_CTRL_CMD_SYSTEM_GET_GPUS_POWER_STATUS (0x134) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_SYSTEM_GET_GPUS_POWER_STATUS (0x134U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS_MESSAGE_ID" */ #define NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS_MESSAGE_ID (0x34U) @@ -1109,8 +1901,8 @@ typedef struct NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS { } NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS; /* Valid gpuExternalPowerStatus values */ -#define NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_CONNECTED 0 -#define NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_NOT_CONNECTED 1 +#define NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_CONNECTED 0U +#define NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_NOT_CONNECTED 1U /* * NV0000_CTRL_CMD_SYSTEM_GET_PRIVILEGED_STATUS @@ -1133,7 +1925,7 @@ typedef struct NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS { */ -#define NV0000_CTRL_CMD_SYSTEM_GET_PRIVILEGED_STATUS (0x135) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_SYSTEM_GET_PRIVILEGED_STATUS (0x135U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS_MESSAGE_ID" */ #define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS_MESSAGE_ID (0x35U) @@ -1143,9 +1935,9 @@ typedef struct NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS { /* Valid privStatus values */ -#define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_USER_FLAG (0x00000001) -#define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_KERNEL_HANDLE_FLAG (0x00000002) -#define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_HANDLE_FLAG (0x00000004) +#define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_USER_FLAG (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_KERNEL_HANDLE_FLAG (0x00000002U) +#define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_HANDLE_FLAG (0x00000004U) /* * NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS @@ -1179,7 +1971,7 @@ typedef enum NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS { NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED = 4, } NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS; -#define NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS (0x136) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS (0x136U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS_MESSAGE_ID" */ #define NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS_MESSAGE_ID (0x36U) @@ -1187,7 +1979,63 @@ typedef struct NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS { NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS fabricStatus; } NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS; +/* + * NV0000_CTRL_VGPU_GET_VGPU_VERSION_INFO + * + * This command is used to query the range of VGX version supported. + * + * host_min_supported_version + * The minimum vGPU version supported by host driver + * host_max_supported_version + * The maximum vGPU version supported by host driver + * user_min_supported_version + * The minimum vGPU version set by user for vGPU support + * user_max_supported_version + * The maximum vGPU version set by user for vGPU support + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + */ +#define NV0000_CTRL_VGPU_GET_VGPU_VERSION (0x137U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS_MESSAGE_ID" */ +/* + * NV0000_CTRL_VGPU_GET_VGPU_VERSION + */ +#define NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS_MESSAGE_ID (0x37U) + +typedef struct NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS { + NvU32 host_min_supported_version; + NvU32 host_max_supported_version; + NvU32 user_min_supported_version; + NvU32 user_max_supported_version; +} NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS; + +/* + * NV0000_CTRL_VGPU_SET_VGPU_VERSION + * + * This command is used to query whether pGPU is live migration capable or not. + * + * min_version + * The minimum vGPU version to be supported being set + * max_version + * The maximum vGPU version to be supported being set + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + */ +#define NV0000_CTRL_VGPU_SET_VGPU_VERSION (0x138U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS_MESSAGE_ID" */ + +/* + * NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS + */ +#define NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS_MESSAGE_ID (0x38U) + +typedef struct NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS { + NvU32 min_version; + NvU32 max_version; +} NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS; /* * NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID @@ -1202,7 +2050,7 @@ typedef struct NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS { * Possible status values returned are: * NV_OK */ -#define NV0000_CTRL_CMD_SYSTEM_GET_RM_INSTANCE_ID (0x139) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_SYSTEM_GET_RM_INSTANCE_ID (0x139U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS_MESSAGE_ID" */ /* * NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS @@ -1213,7 +2061,81 @@ typedef struct NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS { NV_DECLARE_ALIGNED(NvU64 rm_instance_id, 8); } NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS; +/* + * NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO + * + * This API is used to get the TPP(total processing power) and + * the rated TGP(total GPU power) from SBIOS. + * + * NVPCF is an acronym for Nvidia Platform Controllers and Framework + * which implements platform level policies. NVPCF is implemented in + * a kernel driver on windows. It is implemented in a user mode app + * called nvidia-powerd on Linux. + * + * gpuId + * GPU ID + * tpp + * Total processing power including CPU and GPU + * ratedTgp + * Rated total GPU Power + * subFunc + * NVPCF subfunction id + * ctgpOffsetmW + * Configurable TGP offset, in mW + * targetTppOffsetmW + * TPP, as offset in mW. + * maxOutputOffsetmW + * Maximum allowed output, as offset in mW. + * minOutputOffsetmW; + * Minimum allowed output, as offset in mW. + * + * Valid subFunc ids for NVPCF 1x include : + * NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED + * NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_NOT_SUPPORTED + */ +#define NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO (0x13bU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID (0x3BU) + +typedef struct NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS { + NvU32 gpuId; + NvU32 tpp; + NvU32 ratedTgp; + NvU32 subFunc; + NvU32 ctgpOffsetmW; + NvU32 targetTppOffsetmW; + NvU32 maxOutputOffsetmW; + NvU32 minOutputOffsetmW; +} NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS; + +/* Valid NVPCF subfunction case */ +#define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED_CASE 0U +#define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_CASE 1U +#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED_CASE 2U +#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_CASE 3U + +/* Valid NVPCF subfunction ids */ +#define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED (0x00000000) +#define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS (0x00000002) + +/* + * Defines for get supported sub functions bit fields + */ +#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED 0:0 +#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_YES 1 +#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_NO 0 + +/*! + * Config DSM 2x version specific defines + */ +#define NVPCF0100_CTRL_CONFIG_DSM_2X_VERSION (0x00000200) +#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED (0x00000000) +#define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_PARAMS (0x00000002) /* * NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT @@ -1227,7 +2149,7 @@ typedef struct NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS { * Possible status values returned are: * NV_OK */ -#define NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT (0x13c) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT (0x13cU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID" */ #define NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID (0x3CU) @@ -1249,7 +2171,7 @@ typedef struct NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS { * across all clients. * */ -#define NV0000_CTRL_CMD_SYSTEM_GET_CLIENT_DATABASE_INFO (0x13d) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_SYSTEM_GET_CLIENT_DATABASE_INFO (0x13dU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS_MESSAGE_ID" */ #define NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS_MESSAGE_ID (0x3DU) @@ -1280,8 +2202,8 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS { * NV_OK */ -#define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE 256 -#define NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION_V2 (0x13e) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE 256U +#define NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION_V2 (0x13eU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS_MESSAGE_ID" */ #define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS_MESSAGE_ID (0x3EU) @@ -1293,4 +2215,701 @@ typedef struct NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS { NvU32 officialChangelistNumber; } NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS; +/* + * NV0000_CTRL_CMD_SYSTEM_RMCTRL_CACHE_MODE_CTRL + * + * This API is used to get/set RMCTRL cache mode + * + * cmd [IN] + * GET - Gets RMCTRL cache mode + * SET - Sets RMCTRL cache mode + * + * mode [IN/OUT] + * On GET, this field is the output of current RMCTRL cache mode + * On SET, this field indicates the mode to set RMCTRL cache to + * Valid values for this parameter are: + * NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE + * No get/set action to cache. + * NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_ENABLE + * Try to get from cache at the beginning of the control. + * Set cache after control finished if the control has not been cached. + * NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY + * Do not get from cache. Set cache when control call finished. + * When setting the cache, verify the value in the cache is the same + * with the current control value if the control is already cached. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0000_CTRL_CMD_SYSTEM_RMCTRL_CACHE_MODE_CTRL (0x13fU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS_MESSAGE_ID (0x3FU) + +typedef struct NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS { + NvU32 cmd; + NvU32 mode; +} NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS; + +#define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_GET (0x00000000U) +#define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_SET (0x00000001U) + +#define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE (0x00000000U) +#define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_ENABLE (0x00000001U) +#define NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY (0x00000002U) + +/* + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL + * + * This command is used to control PFM_REQ_HNDLR functionality. It allows control of + * GPU Performance Scaling (PFM_REQ_HNDLR), changing its operational parameters and read + * most PFM_REQ_HNDLR dynamic parameters. + * + * command + * This parameter specifies the command to execute. Invalid commands + * result in the return of an NV_ERR_INVALID_ARGUMENT status. + * locale + * This parameter indicates the specific locale to which the command + * 'command' is to be applied. +* Supported range of CPU/GPU {i = 0, ..., 255} + * data + * This parameter contains a command-specific data payload. It can + * be used to input data as well as output data. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_COMMAND + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_DATA + * NV_ERR_INVALID_REQUEST + * NV_ERR_NOT_SUPPORTED + */ +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL (0x140U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS_MESSAGE_ID (0x40U) + +typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS { + NvU16 command; + NvU16 locale; + NvU32 data; +} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS; + +/* + * Valid command values : + * + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_INIT + * Is used to check if PFM_REQ_HNDLR was correctly initialized. + * Possible return (OUT) values are: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_NO + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_YES + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_EXEC + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_EXEC + * Are used to stop/start PFM_REQ_HNDLR functionality and to get current status. + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_STOP + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_START + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_ACTIONS + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_ACTIONS + * Are used to control execution of PFM_REQ_HNDLR actions and to get current status. + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_OFF + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_ON + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_LOGIC + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_LOGIC + * Are used to switch current PFM_REQ_HNDLR logic and to retrieve current logic. + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_OFF + * Will cause that all PFM_REQ_HNDLR actions will be NULL. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_FUZZY + * Fuzzy logic will determine PFM_REQ_HNDLR actions based on current ruleset. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_DETERMINISTIC + * Deterministic logic will define PFM_REQ_HNDLR actions based on current ruleset. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PREFERENCE + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PREFERENCE + * Are used to set/retrieve system control preference. + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_CPU + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_GPU + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_BOTH + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_GPU2CPU_LIMIT + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_GPU2CPU_LIMIT + * Are used to set/retrieve GPU2CPU pstate limits. + * IN/OUT values are four bytes packed into a 32-bit data field. + * The CPU cap index for GPU pstate 0 is in the lowest byte, the CPU cap + * index for the GPU pstate 3 is in the highest byte, etc. One + * special value is to disable the override to the GPU2CPU map: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PMU_PFM_REQ_HNDLR_STATE + * Is used to stop/start PFM_REQ_HNDLR PMU functionality. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PMU_PFM_REQ_HNDLR_STATE + * Is used to get the current status of PMU PFM_REQ_HNDLR. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_NO_MAP_OVERRIDE + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_MAX_POWER + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_MAX_POWER + * Are used to set/retrieve max power [mW] that system can provide. + * This is hardcoded PFM_REQ_HNDLR safety feature and logic/rules does not apply + * to this threshold. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_COOLING_BUDGET + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_COOLING_BUDGET + * Are used to set/retrieve current system cooling budget [mW]. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_INTEGRAL_PERIOD + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_INTEGRAL_PERIOD + * Are used to set/retrieve integration interval [sec]. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_RULESET + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULESET + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULE_COUNT + * Are used to set/retrieve used ruleset [#]. Value is checked + * against MAX number of rules for currently used PFM_REQ_HNDLR logic. Also COUNT + * provides a way to find out how many rules exist for the current control + * system. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_APP_BOOST + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_APP_BOOST + * Is used to set/get a delay relative to now during which to allow unbound + * CPU performance. Units are seconds. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_PWR_SUPPLY_MODE + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_PWR_SUPPLY_MODE + * Is used to override/get the actual power supply mode (AC/Battery). + * Possible IN/OUT values are: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_REAL + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_AC + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_BATT + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_VCT_SUPPORT_INFO + * Is used to get the Ventura system information for VCT tool + * Returned 32bit value should be treated as bitmask and decoded in + * following way: + * Encoding details are defined in objPFM_REQ_HNDLR.h refer to + * NV_PFM_REQ_HNDLR_SYS_SUPPORT_INFO and corresponding bit defines. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_SUPPORTED_FUNCTION + * Is used to get the supported sub-functions defined in SBIOS. Returned + * value is a bitmask where each bit corresponds to different function: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SUPPORT + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURASTATUS + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPSS + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SETPPC + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPPC + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURACB + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SYSPARAMS + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_DELTA + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_FUTURE + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_LTMAVG + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTEGRAL + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_BURDEN + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTERMEDIATE + * Are used to retrieve appropriate power measurements and their derivatives + * in [mW] for required locale. _BURDEN is defined only for _LOCALE_SYSTEM. + * _INTERMEDIATE is not defined for _LOCALE_SYSTEM, and takes an In value as + * index. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_SENSOR_PARAMETERS + * Is used to retrieve parameters when adjusting raw sensor power reading. + * The values may come from SBIOS, VBIOS, registry or driver default. + * Possible IN value is the index of interested parameter. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_DELTA + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_FUTURE + * Are used to retrieve appropriate temperature measurements and their + * derivatives in [1/1000 Celsius]. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_CAP + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MIN + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MAX + * Are used to retrieve CPU(x)/GPU(x) p-state or it's limits. + * Not applicable to _LOCALE_SYSTEM. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_ACTION + * Is used to retrieve last PFM_REQ_HNDLR action for given domain. + * Not applicable to _LOCALE_SYSTEM. + * Possible return (OUT) values are: + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_TO_P0 + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_BY_1 + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DO_NOTHING + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_SET_CURRENT + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_1 + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_2 + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_LFM + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_SLFM + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_STATE + * Is used to set the power sensor simulator state. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_STATE + * Is used to get the power simulator sensor simulator state. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_DATA + * Is used to set power sensor simulator data + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_DATA + * Is used to get power sensor simulator data + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_INIT_USING_SBIOS_AND_ACK + * Is used to respond to the ACPI event triggered by SBIOS. RM will + * request value for budget and status, validate them, apply them + * and send ACK back to SBIOS. + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_PING_SBIOS_FOR_EVENT + * Is a test cmd that should notify SBIOS to send ACPI event requesting + * budget and status change. + */ +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_INVALID (0xFFFFU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_INIT (0x0000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_EXEC (0x0001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_EXEC (0x0002U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_ACTIONS (0x0003U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_ACTIONS (0x0004U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_LOGIC (0x0005U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_LOGIC (0x0006U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PREFERENCE (0x0007U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PREFERENCE (0x0008U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_GPU2CPU_LIMIT (0x0009U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_GPU2CPU_LIMIT (0x000AU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_SET_PMU_PFM_REQ_HNDLR_STATE (0x000BU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_GET_PMU_PFM_REQ_HNDLR_STATE (0x000CU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_MAX_POWER (0x0100U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_MAX_POWER (0x0101U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_COOLING_BUDGET (0x0102U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_COOLING_BUDGET (0x0103U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_INTEGRAL_PERIOD (0x0104U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_INTEGRAL_PERIOD (0x0105U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_RULESET (0x0106U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULESET (0x0107U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_RULE_COUNT (0x0108U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_APP_BOOST (0x0109U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_APP_BOOST (0x010AU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_SET_PWR_SUPPLY_MODE (0x010BU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_PWR_SUPPLY_MODE (0x010CU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_VCT_SUPPORT_INFO (0x010DU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_GET_SUPPORTED_FUNCTIONS (0x010EU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER (0x0200U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_DELTA (0x0201U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_FUTURE (0x0202U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_LTMAVG (0x0203U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTEGRAL (0x0204U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_BURDEN (0x0205U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_INTERMEDIATE (0x0206U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_SENSOR_PARAMETERS (0x0210U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP (0x0220U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_DELTA (0x0221U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_TEMP_FUTURE (0x0222U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE (0x0240U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_CAP (0x0241U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MIN (0x0242U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_MAX (0x0243U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_ACTION (0x0244U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_PSTATE_SLFM_PRESENT (0x0245U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_STATE (0x0250U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_STATE (0x0251U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_SET_POWER_SIM_DATA (0x0252U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_GET_POWER_SIM_DATA (0x0253U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_INIT_USING_SBIOS_AND_ACK (0x0320U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_PING_SBIOS_FOR_EVENT (0x0321U) + +/* valid LOCALE values */ +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_INVALID (0xFFFFU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_SYSTEM (0x0000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_CPU(i) (0x0100+((i)%0x100)) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_LOCALE_GPU(i) (0x0200+((i)%0x100)) + +/* valid data values for enums */ +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INVALID (0x80000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_NO (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INIT_YES (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_STOP (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_EXEC_START (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_OFF (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_ACTIONS_ON (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_OFF (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_FUZZY (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_LOGIC_DETERMINISTIC (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_CPU (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_GPU (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PREFERENCE_BOTH (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_NO_MAP_OVERRIDE (0xFFFFFFFFU) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_OFF (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_PMU_PFM_REQ_HNDLR_STATE_ON (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_REAL (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_AC (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_PWR_SUPPLY_FAKE_BATT (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SUPPORT (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURASTATUS (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPSS (0x00000004U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SETPPC (0x00000008U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_GETPPC (0x00000010U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_VENTURACB (0x00000020U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SYS_DEF_FUNC_SYSPARAMS (0x00000040U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_TO_P0 (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DEC_BY_1 (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_DO_NOTHING (0x00000002U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_SET_CURRENT (0x00000003U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_1 (0x00000004U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_BY_2 (0x00000005U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_LFM (0x00000006U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_ACTION_INC_TO_SLFM (0x00000007U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_NO (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_SLFM_PRESENT_YES (0x00000001U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_OFF (0x00000000U) +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_DATA_DEF_POWER_SIM_STATE_ON (0x00000001U) + +/* + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL + * + * This command allows execution of multiple PFM_REQ_HNDLRControl commands within one + * RmControl call. For practical reasons # of commands is limited to 16. + * This command shares defines with NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CONTROL. + * + * cmdCount + * Number of commands that should be executed. + * Less or equal to NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX. + * + * succeeded + * Number of commands that were succesully executed. + * Less or equal to NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX. + * Failing commands return NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CMD_DEF_INVALID + * in their data field. + * + * cmdData + * Array of commands with following structure: + * command + * This parameter specifies the command to execute. + * Invalid commands result in the return of an + * NV_ERR_INVALID_ARGUMENT status. + * locale + * This parameter indicates the specific locale to which + * the command 'command' is to be applied. + * Supported range of CPU/GPU {i = 0, ..., 255} + * data + * This parameter contains a command-specific data payload. + * It is used both to input data as well as to output data. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_NOT_SUPPORTED + */ +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL (0x141U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX (16U) +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS_MESSAGE_ID (0x41U) + +typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS { + NvU32 cmdCount; + NvU32 succeeded; + + struct { + NvU16 command; + NvU16 locale; + NvU32 data; + } cmdData[NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_BATCH_COMMAND_MAX]; +} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_BATCH_CONTROL_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CTRL + * + * This command is used to execute general PFM_REQ_HNDLR Functions, most dealing with + * calling SBIOS, or retrieving cached sensor and PFM_REQ_HNDLR state data. + * + * version + * This parameter specifies the version of the interface. Legal values + * for this parameter are 1. + * cmd + * This parameter specifies the PFM_REQ_HNDLR API to be invoked. + * Valid values for this parameter are: + * NV0000_CTRL_PFM_REQ_HNDLR_CMD_GET_THERM_LIMIT + * This command gets the temperature limit for thermal controller. When + * this command is specified the input parameter contains ???. + * NV0000_CTRL_PFM_REQ_HNDLR_CMD_SET_THERM_LIMIT + * This command set the temperature limit for thermal controller. When + * this command is specified the input parameter contains ???. + * input + * This parameter specifies the cmd-specific input value. + * result + * This parameter returns the cmd-specific output value. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CTRL (0x142U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS_MESSAGE_ID (0x42U) + +typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS { + NvU32 cmd; + NvS32 input[2]; + NvS32 result[4]; +} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS; + +/* valid version values */ +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_PSP_CURRENT_VERSION (0x00010000U) + +/* valid cmd values */ +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_THERM_LIMIT (0x00000002U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_THERMAL_LIMIT (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MIN_LIMIT (0x00000001U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_MAX_LIMIT (0x00000002U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_LIMIT_SOURCE (0x00000003U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_THERM_LIMIT (0x00000003U) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_THERMAL_LIMIT (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DOWN_N_DELTA (0x00000004U) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DOWN_N_DELTA (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DOWN_N_DELTA (0x00000005U) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DOWN_N_DELTA (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_HOLD_DELTA (0x00000006U) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_HOLD_DELTA (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_HOLD_DELTA (0x00000007U) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_HOLD_DELTA (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_UP_DELTA (0x00000008U) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_UP_DELTA (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_UP_DELTA (0x00000009U) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_UP_DELTA (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_ENGAGE_DELTA (0x0000000AU) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_ENGAGE_DELTA (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_ENGAGE_DELTA (0x0000000BU) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_ENGAGE_DELTA (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000CU) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_DISENGAGE_DELTA (0x0000000DU) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_DISENGAGE_DELTA (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_CTRL_STATUS (0x00000016U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_CTRL_STATUS (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_CTRL_STATUS (0x00000017U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_CTRL_STATUS (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_GET_UTIL_AVG_NUM (0x00000018U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_CPU_SET_UTIL_AVG_NUM (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_SET_UTIL_AVG_NUM (0x00000019U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_CPU_GET_UTIL_AVG_NUM (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PERF_SENSOR (0x0000001AU) +// NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SENSOR_INDEX (0x00000000) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_NEXT_EXPECTED_POLL (0x00000001U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_VALUE (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_PERF_SENSOR_AVAILABLE (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_CALL_ACPI (0x0000001BU) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_CMD (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_ACPI_PARAM_IN (0x00000001U) +#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_1 (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_RESULT_2 (0x00000001U) +#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_STATUS (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_VERSION (0x00000001U) +#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSHAREPARAM_SZ (0x00000002U) +#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_SZ (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_ACPI_PSS_COUNT (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_IGPU_TURBO (0x0000001CU) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_SET_IGPU_TURBO (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERIOD (0x00000026U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERIOD (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERIOD (0x00000027U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERIOD (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_NUDGE_FACTOR (0x00000028U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_UP (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_NUDGE_DOWN (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_NUDGE_FACTOR (0x00000029U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_UP (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_NUDGE_DOWN (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_THRESHOLD_SAMPLES (0x0000002AU) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_THRESHOLD_SAMPLES (0x0000002BU) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_HOLD (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_THRESHOLD_SAMPLE_STEP (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_TEMP_PERF_LIMITS (0x0000002CU) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_UPPER (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_TEMP_PERF_LIMIT_LOWER (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_TEMP_PERF_LIMITS (0x0000002DU) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_UPPER (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_RESULT_TEMP_PERF_LIMIT_LOWER (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PM1_AVAILABLE (0x0000002EU) +#define NV0000_CTRL_PFM_REQ_HNDLR_INPUT_PM1_AVAILABLE (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PM1_AVAILABLE (0x0000002FU) +#define NV0000_CTRL_PFM_REQ_HNDLR_OUTPUT_PM1_AVAILABLE (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS (0x00000044U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_PACKAGE_LIMITS_PL2 (0x00000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS (0x00000045U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_PACKAGE_LIMITS_PL1 (0x00000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT (0x00000046U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_CPU_FREQ_LIMIT_MHZ (0000000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT (0x00000047U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_CPU_FREQ_LIMIT_MHZ (0000000000U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM (0x00000048U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_INDEX (0000000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_GET_PPM_AVAILABLE_MASK (0000000001U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM (0x00000049U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX (0000000000U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_TYPE_SET_PPM_INDEX_MAX (2U) + +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX 7:0 +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_MAXPERF (0U) +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_BALANCED (1U) +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_QUIET (2U) +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_INDEX_INVALID (0xFFU) +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK 15:8 +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_MASK_INVALID (0U) + +/* valid PS_STATUS result values */ +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_OFF (0U) +#define NV0000_CTRL_PFM_REQ_HNDLR_CMD_PS_STATUS_ON (1U) + +#define PFM_REQ_HNDLR_MAX_COUNTERS_PER_BLOCK 32U +typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS { + NvU32 objHndl; + NvU32 blockId; + NvU32 nextExpectedSampleTimems; + NvU32 countersReq; + NvU32 countersReturned; + NvU32 counterBlock[PFM_REQ_HNDLR_MAX_COUNTERS_PER_BLOCK]; +} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS; + +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSORS (0x146U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x46" */ + +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_EXTENDED_PERF_SENSORS (0x147U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x47" */ + +/* + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI + * + * This command allows users to call PFM_REQ_HNDLR ACPI commands for testing purposes. + * + * cmd + * This parameter specifies the PFM_REQ_HNDLR ACPI command to execute. + * + * input + * This parameter specified the cmd-dependent input value. + * + * resultSz + * This parameter returns the size (in bytes) of the valid data + * returned in the result parameter. + * + * result + * This parameter returns the results of the specified cmd. + * The maximum size (in bytes) of this returned data will + * not exceed PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE + * + * PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE + * The size of buffer (result) in unit of NvU32. + * The smallest value is sizeof(PSS_ENTRY)*ACPI_PSS_ENTRY_MAX. + * Since the prior one is 24 bytes, and the later one is 48, + * this value cannot be smaller than 288. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT, + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INSUFFICIENT_PERMISSIONS + * + */ +#define PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE 288U +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_MESSAGE_ID (0x43U) + +typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS { + NvU32 cmd; + NvU32 input; + NvU32 resultSz; + NvU32 result[PFM_REQ_HNDLR_MAX_ACPI_OUTPUT_BUFFER_SIZE]; +} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS; + +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI (0x143U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_RMTRACE_MODULE_PFM_REQ_HNDLR (0x00008000U) + +/* + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA + * + * This command is used to read FRL data based on need. + * + * nextSampleNumber + * This parameter returns the counter of next sample which is being filled. + * samples + * This parameter returns the frame time, render time, target time, client ID + * with one reserve bit for future use. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA (0x144U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE 64U + +typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE { + NvU16 frameTime; + NvU16 renderTime; + NvU16 targetTime; + NvU8 sleepTime; + NvU8 sampleNumber; +} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE; + +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS_MESSAGE_ID (0x44U) + +typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS { + NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE samples[NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE_SIZE]; + NvU8 nextSampleNumber; +} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS; + +/* + * NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA + * + * This command is used to write FRM data based on need. + * + * frameTime + * This parameter contains the frame time of current frame. + * renderTime + * This parameter contains the render time of current frame. + * targetTime + * This parameter contains the target time of current frame. + * sleepTime + * This parameter contains the sleep duration inserted by FRL for the latest frame. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0000_CTRL_CMD_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA (0x145U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS_MESSAGE_ID (0x45U) + +typedef struct NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS { + NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_FRM_DATA_SAMPLE sampleData; +} NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_SET_FRM_DATA_PARAMS; + /* _ctrl0000system_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h index 3402552a2..d55703d65 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h @@ -222,6 +222,9 @@ typedef struct NV0000_CTRL_OS_GET_GPU_INFO_PARAMS { * deviceInstatnce * This parameter returns a deviceInstance on which the object is located. * + * NV_MAX_DEVICES is returned if the object is parented by a client instead + * of a device. + * * maxObjects * This parameter returns the maximum number of object handles that may be * contained in the file descriptor. @@ -416,6 +419,8 @@ typedef struct NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS { #define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_SYSMEM 2 #define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC 3 + + #define NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS_MESSAGE_ID (0xCU) typedef struct NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS { diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h index 817d1d559..671c1a32a 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2016-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -30,3 +30,49 @@ // Source file: ctrl/ctrl0000/ctrl0000vgpu.finn // +#include "ctrl/ctrl0000/ctrl0000base.h" + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrla081.h" +#include "class/cl0000.h" +#include "nv_vgpu_types.h" +/* + * NV0000_CTRL_CMD_VGPU_GET_START_DATA + * + * This command gets data associated with NV0000_NOTIFIERS_VGPU_MGR_START to + * start VGPU process. + * + * mdevUuid + * This parameter gives mdev device UUID for which nvidia-vgpu-mgr should + * init process. + * + * qemuPid + * This parameter specifies the QEMU process ID of the VM. + * + * gpuPciId + * This parameter provides gpuId of GPU on which vgpu device is created. + * + * configParams + * This parameter specifies the configuration parameters for vGPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_EVENT + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INVALID_CLIENT + * + */ +#define NV0000_CTRL_CMD_VGPU_GET_START_DATA (0xc01) /* finn: Evaluated from "(FINN_NV01_ROOT_VGPU_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_GET_START_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_VGPU_GET_START_DATA_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV0000_CTRL_VGPU_GET_START_DATA_PARAMS { + NvU8 mdevUuid[VM_UUID_SIZE]; + NvU8 configParams[1024]; + NvU32 qemuPid; + NvU32 gpuPciId; + NvU16 vgpuId; + NvU32 gpuPciBdf; +} NV0000_CTRL_VGPU_GET_START_DATA_PARAMS; + +/* _ctrl0000vgpu_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0041.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0041.h index 6ff491b89..322393d9b 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0041.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0041.h @@ -156,28 +156,6 @@ typedef struct NV0041_CTRL_GET_SURFACE_ZCULL_ID_PARAMS { NvU32 zcullId; } NV0041_CTRL_GET_SURFACE_ZCULL_ID_PARAMS; -/* - * NV0041_CTRL_CMD_GET_SURFACE_PARTITION_STRIDE - * - * This command returns the partition stride (in bytes) for real memory - * associated with the memory object. - * - * Possible status values returned are: - * NV_OK - * NVOS_STATUS_BAD_OBJECT_HANDLE - * NVOS_STATUS_BAD_OBJECT_PARENT - * NVOS_STATUS_NOT_SUPPORTED - * - */ -#define NV0041_CTRL_CMD_GET_SURFACE_PARTITION_STRIDE (0x410105) /* finn: Evaluated from "(FINN_NV01_ROOT_USER_MEMORY_INTERFACE_ID << 8) | NV0041_CTRL_GET_SURFACE_PARTITION_STRIDE_PARAMS_MESSAGE_ID" */ - -#define NV0041_CTRL_GET_SURFACE_PARTITION_STRIDE_PARAMS_MESSAGE_ID (0x5U) - -typedef struct NV0041_CTRL_GET_SURFACE_PARTITION_STRIDE_PARAMS { - NvU32 partitionStride; -} NV0041_CTRL_GET_SURFACE_PARTITION_STRIDE_PARAMS; - - // return values for 'tilingFormat' // XXX - the names for these are misleading diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h index b3b3eb207..347b478e7 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h @@ -1137,6 +1137,10 @@ typedef struct NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS { * Major version number of DSC decoder on Panel. * dscDecoderVersionMinor * Minor version number of DSC decoder on Panel. +* dscUseCustomPPS +* Flag to indicate if Panel uses custom PPS values which deviate from standard values. +* dscCustomPPSData +* 32 bytes of custom PPS data required by Panel. * dscEncoderCaps * Capabilities of DSC encoder in SoC. * @@ -1148,31 +1152,35 @@ typedef struct NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS { #define NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING (0x731166U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS_MESSAGE_ID" */ +#define NV0073_CTRL_CMD_DFP_DSI_CUSTOM_PPS_DATA_COUNT 32U + #define NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS_MESSAGE_ID (0x66U) typedef struct NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS { - NvU32 subDeviceInstance; - NvU32 displayId; - NvU32 hActive; - NvU32 vActive; - NvU32 hFrontPorch; - NvU32 vFrontPorch; - NvU32 hBackPorch; - NvU32 vBackPorch; - NvU32 hSyncWidth; - NvU32 vSyncWidth; - NvU32 bpp; - NvU32 refresh; - NvU32 pclkHz; - NvU32 numLanes; - NvU32 dscEnable; - NvU32 dscBpp; - NvU32 dscNumSlices; - NvU32 dscDualDsc; - NvU32 dscSliceHeight; - NvU32 dscBlockPrediction; - NvU32 dscDecoderVersionMajor; - NvU32 dscDecoderVersionMinor; + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 hActive; + NvU32 vActive; + NvU32 hFrontPorch; + NvU32 vFrontPorch; + NvU32 hBackPorch; + NvU32 vBackPorch; + NvU32 hSyncWidth; + NvU32 vSyncWidth; + NvU32 bpp; + NvU32 refresh; + NvU32 pclkHz; + NvU32 numLanes; + NvU32 dscEnable; + NvU32 dscBpp; + NvU32 dscNumSlices; + NvU32 dscDualDsc; + NvU32 dscSliceHeight; + NvU32 dscBlockPrediction; + NvU32 dscDecoderVersionMajor; + NvU32 dscDecoderVersionMinor; + NvBool dscUseCustomPPS; + NvU32 dscCustomPPSData[NV0073_CTRL_CMD_DFP_DSI_CUSTOM_PPS_DATA_COUNT]; struct { NvBool bDscSupported; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h index 57a7ca3e3..e593227b3 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -1738,8 +1738,8 @@ typedef struct NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS { * should be set to zero for default behavior. * sorIndex * Specifies the SOR index. - * bIsDp12Supported - * Returns NV_TRUE if DP1.2 is supported by the GPU else NV_FALSE + * dpVersionsSupported + * Specified the DP versions supported by the GPU * bIsMultistreamSupported * Returns NV_TRUE if MST is supported by the GPU else NV_FALSE * bIsSCEnabled @@ -1788,6 +1788,7 @@ typedef struct NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS { * NV_ERR_NOT_SUPPORTED * */ + #define NV0073_CTRL_CMD_DP_GET_CAPS (0x731369U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS_MESSAGE_ID" */ #define NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS_MESSAGE_ID (0x69U) @@ -1796,8 +1797,7 @@ typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS { NvU32 subDeviceInstance; NvU32 sorIndex; NvU32 maxLinkRate; - NvBool bIsDp12Supported; - NvBool bIsDp14Supported; + NvU32 dpVersionsSupported; NvBool bIsMultistreamSupported; NvBool bIsSCEnabled; NvBool bHasIncreasedWatermarkLimits; @@ -1818,6 +1818,15 @@ typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS { } DSC; } NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS; +#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2 0:0 +#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2_NO (0x00000000U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2_YES (0x00000001U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4 1:1 +#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4_NO (0x00000000U) +#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4_YES (0x00000001U) + + + #define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE 2:0 #define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_NONE (0x00000000U) #define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_1_62 (0x00000001U) @@ -2705,7 +2714,7 @@ typedef struct NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS { #define NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_SET_ENABLE_OD 0x00000003 /* - * NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2 + * NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES * * This command returns the following info * @@ -2755,5 +2764,4 @@ typedef struct NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS { NvBool bDebugValues; NV0073_CTRL_DP_MSA_PROPERTIES_VALUES featureDebugValues; } NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS; - /* _ctrl0073dp_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h index 2163c3197..74ace22cc 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -574,7 +574,48 @@ typedef struct NV0073_CTRL_SPECIFIC_ACPI_ID_MAPPING { NvU32 dodIndex; } NV0073_CTRL_SPECIFIC_ACPI_ID_MAPPING; +/* + * NV0073_CTRL_CMD_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT + * + * This call will return the Display Port Attachment value + * per displayID as defined by Nvidia that is directly + * associated with the ACPI 3.0 _DOD entry's Display Port + * Attachment field. This should help clients map the + * _DOD ACPI ID to each displayID. Note, that some systems + * do not have a standard in place for this field. On those + * systems, the RM will return NV_ERR_NOT_SUPPORTED. + * + * Note that this "Display Port" attachment field has nothing + * to do with DisplayPort/DP. It's an unfortunate name inside + * the ACPI 3.0 spec that coincides with the name of DisplayPort. + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_NOT_SUPPORTED + * +*/ +#define NV0073_CTRL_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT_PARAMS_MESSAGE_ID (0x85U) + +typedef struct NV0073_CTRL_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 dispPortAttachment; +} NV0073_CTRL_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT_PARAMS; + + +#define NV0073_CTRL_CMD_SPECIFIC_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT (0x730285U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT_PARAMS_MESSAGE_ID" */ + +// defines for dispPortAttachment +#define NV0073_DISPLAY_PORT_ATTACHMENT_ANALOG (0x00000000U) +#define NV0073_DISPLAY_PORT_ATTACHMENT_LVDS (0x00000001U) +#define NV0073_DISPLAY_PORT_ATTACHMENT_DP_A (0x00000002U) +#define NV0073_DISPLAY_PORT_ATTACHMENT_DP_B (0x00000003U) +#define NV0073_DISPLAY_PORT_ATTACHMENT_DP_C (0x00000004U) +#define NV0073_DISPLAY_PORT_ATTACHMENT_DP_D (0x00000005U) +#define NV0073_DISPLAY_PORT_ATTACHMENT_UNKNOWN (0xFFFFFFFFU) /* * NV0073_CTRL_CMD_SPECIFIC_SET_ACPI_ID_MAPPING @@ -1835,7 +1876,34 @@ typedef struct NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS { NvU8 writeBuffer[NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_BUF_LEN]; } NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS; -#define NV0073_CTRL_SPECIFIC_DISP_I2C_READ_MODE (0x00000001) -#define NV0073_CTRL_SPECIFIC_DISP_I2C_WRITE_MODE (0x00000000) +#define NV0073_CTRL_SPECIFIC_DISP_I2C_READ_MODE (0x00000001) +#define NV0073_CTRL_SPECIFIC_DISP_I2C_WRITE_MODE (0x00000000) + +/* + * NV0073_CTRL_CMD_GET_VALID_HEAD_WINDOW_ASSIGNMENT + * + * This command returns the valid window head assignment mask + * + * windowHeadMask [out] + * This out parameter is an array which holds the head mask for + * each window. The Nth element in the array would be a bitmask + * of which heads can possibly drive window N. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_GENERIC + */ +#define NV0073_CTRL_CMD_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT (0x7302ad) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_MAX_WINDOWS 32U +#define NV0073_CTRL_SPECIFIC_FLEXIBLE_HEAD_WINDOW_ASSIGNMENT (0xFFU) + +#define NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS_MESSAGE_ID (0xADU) + +typedef struct NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS { + NvU32 subDeviceInstance; + NvU8 windowHeadMask[NV0073_CTRL_SPECIFIC_MAX_WINDOWS]; +} NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS; /* _ctrl0073specific_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h index 5a54df7dc..d25501a34 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h @@ -603,6 +603,122 @@ typedef struct NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS { +/* + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP + * + * This structure defines the mapping between the RM's displayId and the + * defined ACPI IDs for each display. + * displayId + * This parameter is a handle to a single display output path from the + * GPU pins to the display connector. Each display ID is defined by one bit. + * A zero in this parameter indicates a skip entry. + * acpiId + * This parameter defines the corresponding ACPI ID of the displayId. + * flags + * This parameter specifies optional flags that describe the association + * between the display ID and the ACPI ID. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN + * This field describes where the ACPI was found. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_RM + * The ACPI ID was generated by RM code. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_DOD + * The ACPI ID was found via the ACPI _DOD call. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_CLIENT + * The ACPI ID was generated by RM Client and sent to RM. Note this + * must be set on a NV0073_CTRL_CMD_SYSTEM_SET_ACPI_ID_MAP call. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_UNDOCKED + * This flag explains that the ACPI ID is only valid when the system + * is undocked. If this flag is not set, the ACPI ID is valid always. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_DOCKED + * This flag explains that the ACPI ID is only valid when the system + * is docked. If this flag is not set, the ACPI ID is valid always. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_BIOS_DETECT + * This flag is set only if the _DOD returns that the device can be + * detected by the system BIOS. This flag is copied directly from + * the ACPI spec. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_NON_VGA_OUTPUT + * This flag is set only if the _DOD returns that the device is + * a non-VGA device whose power is related to the VGA device. + * i.e. TV tuner, DVD decoder, Video capture. This flag is copied + * directly from the ACPI spec. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_MULTIHEAD_ID + * This value is set only if the _DOD returns it. The number + * indicates the head output of a multi-head device. This has no + * relation to the term, Head, currently used in the RM today. + * This is strictly a copy of the value directly from the ACPI spec. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_SCHEME + * This flag is set only if the _DOD returns that the acpiID follows + * the ACPI 3.0 spec. This flag is copied directly from + * the ACPI spec. + * + */ + +typedef struct NV0073_CTRL_SYSTEM_ACPI_ID_MAP_PARAMS { + NvU32 displayId; + NvU32 acpiId; + NvU32 flags; +} NV0073_CTRL_SYSTEM_ACPI_ID_MAP_PARAMS; + +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN 1:0 +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_RM 0x00000000U +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_DOD 0x00000001U +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_ORIGIN_CLIENT 0x00000002U + +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_UNDOCKED 2:2 +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_UNDOCKED_FALSE 0x00000000U +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_UNDOCKED_TRUE 0x00000001U + +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_DOCKED 3:3 +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_DOCKED_FALSE 0x00000000U +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_SNAG_DOCKED_TRUE 0x00000001U + +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_BIOS_DETECT 16:16 +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_BIOS_DETECT_FALSE 0x00000000U +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_BIOS_DETECT_TRUE 0x00000001U + +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_NON_VGA_OUTPUT 17:17 +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_NON_VGA_OUTPUT_FALSE 0x00000000U +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_NON_VGA_OUTPUT_TRUE 0x00000001U + +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_MULTIHEAD_ID 20:18 + +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_SCHEME 31:31 +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_SCHEME_VENDOR 0x00000000U +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_DOD_SCHEME_30 0x00000001U + +#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS (16U) + +/* + * NV0073_CTRL_CMD_SYSTEM_GET_ACPI_ID_MAP + * + * This command retrieves the mapping between the RM's displayId and the + * defined ACPI IDs for each display. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and + * the total number of subdevices within the parent device. It should + * be set to zero for default behavior. + * NV0073_CTRL_SYSTEM_ACPI_ID_MAP_PARAMS + * An array of display ID to ACPI ids with flags for each description. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * Only returned if subdeviceInstance was not valid. + */ + +#define NV0073_CTRL_CMD_SYSTEM_GET_ACPI_ID_MAP (0x73015aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS_MESSAGE_ID" */ + + +#define NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS_MESSAGE_ID (0x5AU) + +typedef struct NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS { + NvU32 subDeviceInstance; + NV0073_CTRL_SYSTEM_ACPI_ID_MAP_PARAMS acpiIdMap[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS]; +} NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS; + /* * NV0073_CTRL_CMD_SYSTEM_GET_INTERNAL_DISPLAYS * @@ -670,6 +786,265 @@ typedef struct NV0073_CTRL_SYSTEM_GET_BOOT_DISPLAYS_PARAMS { +/* + * NV0073_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD + * + * This command is used to execute general MXM ACPI methods. + * + * method + * This parameter identifies the MXM ACPI API to be invoked. + * Valid values for this parameter are: + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMI + * This value specifies that the MXMI API is to invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMS + * This value specifies that the MXMS API is to invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMX + * This value specifies that the MXMX API is to invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUON + * This value specifies that the Hybrid GPU ON API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUOFF + * This value specifies that the Hybrid GPU OFF API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUSTA + * This value specifies that the Hybrid GPU STA API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXDS + * This value specifies that the Hybrid GPU MXDS API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NVHG_MXMX + * This value specifies that the Hybrid GPU MXMX API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOS + * This value specifies that the Hybrid GPU DOS API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_ROM + * This value specifies that the Hybrid GPU ROM API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOD + * This value specifies that the Hybrid GPU DOD API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_SUPPORT + * This value specifies that the Hybrid GPU DSM subfunction SUPPORT + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HYBRIDCAPS + * This value specifies that the Hybrid GPU DSM subfunction SUPPORT + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_POLICYSELECT + * This value specifies that the Hybrid GPU DSM subfunction POLICYSELECT + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_POWERCONTROL + * This value specifies that the Hybrid GPU DSM subfunction POWERCONTROL + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_PLATPOLICY + * This value specifies that the Hybrid GPU DSM subfunction PLATPOLICY + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_DISPLAYSTATUS + * This value specifies that the Hybrid GPU DSM subfunction DISPLAYSTATUS + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MDTL + * This value specifies that the Hybrid GPU DSM subfunction MDTL + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSMBLIST + * This value specifies that the Hybrid GPU DSM subfunction HCSMBLIST + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSMBADDR + * This value specifies that the Hybrid GPU DSM subfunction HCSMBADDR + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCREADBYTE + * This value specifies that the Hybrid GPU DSM subfunction HCREADBYTE + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSENDBYTE + * This value specifies that the Hybrid GPU DSM subfunction HCSENDBYTES + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCGETSTATUS + * This value specifies that the Hybrid GPU DSM subfunction HCGETSTATUS + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCTRIGDDC + * This value specifies that the Hybrid GPU DSM subfunction HCTRIGDDC + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCGETDDC + * This value specifies that the Hybrid GPU DSM subfunction HCGETDDC + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DCS + * This value specifies that the Hybrid GPU DCS API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXSS + * This value specifies that the DSM MXM subfunction MXSS + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXMI + * This value specifies that the DSM MXM subfunction MXMI + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXMS + * This value specifies that the DSM MXM subfunction MXMS + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXPP + * This value specifies that the DSM MXM subfunction MXPP + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXDP + * This value specifies that the DSM MXM subfunction MXDP + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MDTL + * This value specifies that the DSM MXM subfunction MDTL + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXCB + * This value specifies that the DSM MXM subfunction MXCB + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_REMAPFUNC + * This value specifies the DSM generic remapping should return function + * and subfunction when this API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_HYBRIDCAPS + * This value specifies that the generic DSM subfunction HYBRIDCAPS + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_POLICYSELECT + * This value specifies that the generic DSM subfunction POLICYSELECT + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_PLATPOLICY + * This value specifies that the generic DSM subfunction PLATPOLICY + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_DISPLAYSTATUS + * This value specifies that the generic DSM subfunction DISPLAYSTATUS + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_MDTL + * This value specifies that the generic DSM subfunction MDTL + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETOBJBYTYPE + * This value specifies that the generic DSM subfunction GETOBJBYTYPE + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETALLOBJS + * This value specifies that the generic DSM subfunction GETALLOBJS + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETEVENTLIST + * This value specifies that the generic DSM subfunction GETEVENTLIST + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETBACKLIGHT + * This value specifies that the generic DSM subfunction GETBACKLIGHT + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_TESTSUBFUNCENABLED + * This value specifies the testIfDsmSubFunctionEnabled test should + * be done for the func/subfunction when this API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_GETSUPPORTEDFUNC + * This value specifies the list of supported generic dsm functions + * should be returned. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS + * This value specifies that the DSM NVOP subfunction OPTIMUSCAPS + * API is to be invoked. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG + * This value specifies that the DSM NVOP subfunction OPTIMUSFLAG + * API is to be invoked. This API will set a Flag in sbios to Indicate + * that HD Audio Controller is disable/Enabled from GPU Config space. + * This flag will be used by sbios to restore Audio state after resuming + * from s3/s4. + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_WMMX_NVOP_GPUON + * This value specifies that the WMMX (WMI-ACPI) GPON methods has to be invoked + * this call should happen below DPC level from any client. + * inData + * This parameter specifies the method-specific input buffer. Data is + * passed to the specified API using this buffer. For display related + * APIs the associated display mask can be found at a byte offset within + * the inData buffer using the following method-specific values: + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMX_DISP_MASK_OFFSET + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXDS_DISP_MASK_OFFSET + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NVHG_MXMX_DISP_MASK_OFFSET + * NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOS_DISP_MASK_OFFSET + * inDataSize + * This parameter specifies the size of the inData buffer in bytes. + * outStatus + * This parameter returns the status code from the associated ACPI call. + * outData + * This parameter specifies the method-specific output buffer. Data + * is returned by the specified API using this buffer. + * outDataSize + * This parameter specifies the size of the outData buffer in bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV0073_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD (0x730168U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS_MESSAGE_ID (0x68U) + +typedef struct NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS { + NvU32 method; + NV_DECLARE_ALIGNED(NvP64 inData, 8); + NvU16 inDataSize; + NvU32 outStatus; + NV_DECLARE_ALIGNED(NvP64 outData, 8); + NvU16 outDataSize; +} NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS; + + +/* valid method parameter values */ +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMX (0x00000002U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMX_DISP_MASK_OFFSET (0x00000001U) + +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUON (0x00000003U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUOFF (0x00000004U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUSTA (0x00000005U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXDS (0x00000006U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NVHG_MXMX (0x00000007U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOS (0x00000008U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_ROM (0x00000009U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOD (0x0000000aU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_SUPPORT (0x0000000bU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HYBRIDCAPS (0x0000000cU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_POLICYSELECT (0x0000000dU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_POWERCONTROL (0x0000000eU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_PLATPOLICY (0x0000000fU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_DISPLAYSTATUS (0x00000010U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MDTL (0x00000011U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSMBLIST (0x00000012U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSMBADDR (0x00000013U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCREADBYTE (0x00000014U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSENDBYTE (0x00000015U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCGETSTATUS (0x00000016U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCTRIGDDC (0x00000017U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCGETDDC (0x00000018U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DCS (0x00000019U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXSS (0x0000001aU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXMI (0x0000001bU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXMS (0x0000001cU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXPP (0x0000001dU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXDP (0x0000001eU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MDTL (0x0000001fU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXCB (0x00000020U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_GETEVENTLIST (0x00000021U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETMEMTABLE (0x00000022U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETMEMCFG (0x00000023U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETOBJBYTYPE (0x00000024U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETALLOBJS (0x00000025U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_REMAPFUNC (0x00000026U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_DISPLAYSTATUS (0x0000002aU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_MDTL (0x0000002bU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETOBJBYTYPE (0x0000002cU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETALLOBJS (0x0000002dU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETEVENTLIST (0x0000002eU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETBACKLIGHT (0x0000002fU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_TESTSUBFUNCENABLED (0x00000030U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_GETSUPPORTEDFUNC (0x00000031U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS (0x00000032U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_WMMX_NVOP_GPUON (0x00000033U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG (0x00000034U) + + +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETCALLBACKS (0x00000036U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NBCI_SUPPORTFUNCS (0x00000037U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NBCI_PLATCAPS (0x00000038U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NBCI_PLATPOLICY (0x00000039U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_MSTL (0x0000003aU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVGPS_FUNC_SUPPORT (0x0000003bU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDS (0x0000003cU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDM (0x0000003dU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXID (0x0000003eU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_LRST (0x0000003fU) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DDC_EDID (0x00000040U) + +/* valid input buffer offset values */ +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXDS_DISP_MASK_OFFSET (0x00000004U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NVHG_MXMX_DISP_MASK_OFFSET (0x00000004U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOS_DISP_MASK_OFFSET (0x00000004U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDS_DISP_MASK_OFFSET (0x00000004U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDM_DISP_MASK_OFFSET (0x00000004U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXID_DISP_MASK_OFFSET (0x00000004U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_LRST_DISP_MASK_OFFSET (0x00000004U) +#define NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DDC_EDID_DISP_MASK_OFFSET (0x00000004U) + + + /* * NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_UNPLUG_STATE * @@ -1068,5 +1443,38 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT_PARAMS { NvBool bIsSidebandI2cSupported; } NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT_PARAMS; +/* + * NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT + * + * This command is used to query if SIDEBAND SR can be used with the + * given display device. If PSR API is supported on the system, + * then sideband SR support is set to false. + * + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation + * should be directed. + * displayId (in) + * This parameter inputs the displayId of the active display. A value + * of zero indicates no display is active. + * bIsSidebandSrSupported + * If it is true, it means that sideband is supported and not PSR API. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT (0x73019dU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS_MESSAGE_ID (0x9DU) + +typedef struct NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvBool bIsSidebandSrSupported; +} NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS; + /* _ctrl0073system_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h index cf2f90e3a..b209ca25f 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h @@ -696,7 +696,7 @@ typedef struct NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS { NvU32 flags; NV_DECLARE_ALIGNED(NV0080_CTRL_DMA_UPDATE_PDE_2_PAGE_TABLE_PARAMS ptParams[NV0080_CTRL_DMA_UPDATE_PDE_2_PT_IDX__SIZE], 8); NvHandle hVASpace; - NV_DECLARE_ALIGNED(NvP64 pPdeBuffer, 8); // NV_MMU_VER2_PDE__SIZE + NV_DECLARE_ALIGNED(NvP64 pPdeBuffer, 8); // NV_MMU_VER2_DUAL_PDE__SIZE NvU32 subDeviceId; // ID+1, 0 for BC } NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h index b7b13f8ca..823cc0c3a 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h @@ -192,7 +192,7 @@ typedef struct NV0080_CTRL_FIFO_CHANNEL { #define NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS_MESSAGE_ID (0x5U) typedef struct NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS { - NvU32 fifoStartChannelListSize; + NvU32 fifoStartChannelListCount; NvHandle channelHandle[8]; NV_DECLARE_ALIGNED(NvP64 fifoStartChannelList, 8); } NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h index 58f2953e7..5ce19e563 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h @@ -494,7 +494,7 @@ typedef struct NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS { // Update this macro if new HW exceeds GPU Classlist MAX_SIZE -#define NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE 116 +#define NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE 160 #define NV0080_CTRL_CMD_GPU_GET_CLASSLIST_V2 (0x800292) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h index fe7c63a08..2592559fd 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h @@ -150,13 +150,14 @@ typedef struct NV0080_CTRL_GR_INFO { #define NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT (0x0000002E) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC (0x00000032) /* When adding a new INDEX, please update MAX_SIZE accordingly * NOTE: 0080 functionality is merged with 2080 functionality, so this max size * reflects that. */ -#define NV0080_CTRL_GR_INFO_INDEX_MAX (0x00000031) -#define NV0080_CTRL_GR_INFO_MAX_SIZE (0x32) /* finn: Evaluated from "(NV0080_CTRL_GR_INFO_INDEX_MAX + 1)" */ +#define NV0080_CTRL_GR_INFO_INDEX_MAX (0x00000032) +#define NV0080_CTRL_GR_INFO_MAX_SIZE (0x33) /* finn: Evaluated from "(NV0080_CTRL_GR_INFO_INDEX_MAX + 1)" */ /* * NV0080_CTRL_CMD_GR_GET_INFO diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h index c48b4125b..fbbdf7339 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -59,21 +59,10 @@ */ #define NV0080_CTRL_CMD_OS_UNIX_VT_SWITCH (0x801e01) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_OS_UNIX_INTERFACE_ID << 8) | NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS_MESSAGE_ID" */ -typedef struct NV0080_CTRL_OS_UNIX_VT_SWITCH_FB_INFO { - NvU32 subDeviceInstance; - - NvU16 width; - NvU16 height; - NvU16 depth; - NvU16 pitch; -} NV0080_CTRL_OS_UNIX_VT_SWITCH_FB_INFO; - #define NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS_MESSAGE_ID (0x1U) typedef struct NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS { - NvU32 cmd; /* in */ - - NV0080_CTRL_OS_UNIX_VT_SWITCH_FB_INFO fbInfo; /* out */ + NvU32 cmd; /* in */ } NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS; /* Called when the display driver needs RM to save the console data, diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h b/src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h index ceb6caf87..595b021a3 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h @@ -126,4 +126,93 @@ typedef struct NV00F8_CTRL_DESCRIBE_PARAMS { NvU32 numPfns; } NV00F8_CTRL_DESCRIBE_PARAMS; +/* + * hMemory [IN] + * Physical memory handle to be attached. + * + * offset [IN] + * Offset into the fabric object. + * Must be physical memory pagesize aligned (at least). + * + * mapOffSet [IN] + * Offset into the physical memory descriptor. + * Must be physical memory pagesize aligned. + * + * mapLength [IN] + * Length of physical memory handle to be mapped. + * Must be physical memory pagesize aligned and less than or equal to + * fabric alloc size. + */ +typedef struct NV00F8_CTRL_ATTACH_MEM_INFO { + NvHandle hMemory; + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NV_DECLARE_ALIGNED(NvU64 mapOffset, 8); + NV_DECLARE_ALIGNED(NvU64 mapLength, 8); +} NV00F8_CTRL_ATTACH_MEM_INFO; + +/* + * NV00F8_CTRL_CMD_ATTACH_MEM + * + * Attaches physical memory info to the fabric object. + * + * memInfos [IN] + * Memory infos to be attached. + * + * numMemInfos [IN] + * Number of memory infos to be attached. + * + * flags [IN] + * For future use only. Must be zero for now. + * + * numAttached [OUT] + * Successful attach count (returns a valid value on error too) + * + * Restrictions: + * a. Physical memory with 2MB pagesize is allowed + * b. Only vidmem physical memory handle can be attached + * c. Supported only for flexible fabric objects. + */ +#define NV00F8_CTRL_CMD_ATTACH_MEM (0xf80103) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_ATTACH_MEM_PARAMS_MESSAGE_ID" */ + +#define NV00F8_MAX_ATTACHABLE_MEM_INFOS 64 + +#define NV00F8_CTRL_ATTACH_MEM_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV00F8_CTRL_ATTACH_MEM_PARAMS { + NV_DECLARE_ALIGNED(NV00F8_CTRL_ATTACH_MEM_INFO memInfos[NV00F8_MAX_ATTACHABLE_MEM_INFOS], 8); + NvU16 numMemInfos; + NvU32 flags; + NvU16 numAttached; +} NV00F8_CTRL_ATTACH_MEM_PARAMS; + +/* + * NV00F8_CTRL_CMD_DETACH_MEM + * + * Detaches physical memory handle from the fabric object. + * + * offsets [IN] + * Offsets at which memory was attached. + * + * numOffsets [IN] + * Number of offsets to be detached. + * + * flags [IN] + * For future use only. Must be zero for now. + * + * numDetached [OUT] + * Successful detach count (returns a valid value on error too) + */ +#define NV00F8_CTRL_CMD_DETACH_MEM (0xf80104) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_DETACH_MEM_PARAMS_MESSAGE_ID" */ + +#define NV00F8_MAX_DETACHABLE_OFFSETS 64 + +#define NV00F8_CTRL_DETACH_MEM_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV00F8_CTRL_DETACH_MEM_PARAMS { + NV_DECLARE_ALIGNED(NvU64 offsets[NV00F8_MAX_DETACHABLE_OFFSETS], 8); + NvU16 numOffsets; + NvU32 flags; + NvU16 numDetached; +} NV00F8_CTRL_DETACH_MEM_PARAMS; + /* _ctrl00f8_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl00fd.h b/src/common/sdk/nvidia/inc/ctrl/ctrl00fd.h new file mode 100644 index 000000000..7ba86f861 --- /dev/null +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl00fd.h @@ -0,0 +1,160 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl00fd.finn +// + +#include "ctrl/ctrlxxxx.h" + +#define NV00FD_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x00fd, NV00FD_CTRL_##cat, idx) + +/* NV00FD command categories (6bits) */ +#define NV00FD_CTRL_RESERVED (0x00) +#define NV00FD_CTRL_MULTICAST_FABRIC (0x01) + +/* + * NV00FD_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV00FD_CTRL_CMD_NULL (0xfd0000) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NV00FD_CTRL_CMD_GET_INFO + * + * Queries multicast memory fabric allocation attributes. + * + * alignment [OUT] + * Alignment for the allocation. + * + * allocSize [OUT] + * Size of the allocation. + * + * pageSize [OUT] + * Page size of the allocation. + * + * numMaxGpus [OUT] + * Maximum number of attachable GPUs + * + * numAttachedGpus [OUT] + * Number of GPUs currently attached + * + */ +#define NV00FD_CTRL_CMD_GET_INFO (0xfd0101) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00FD_CTRL_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV00FD_CTRL_GET_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV00FD_CTRL_GET_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 alignment, 8); + NV_DECLARE_ALIGNED(NvU64 allocSize, 8); + NvU32 pageSize; + NvU32 numMaxGpus; + NvU32 numAttachedGpus; +} NV00FD_CTRL_GET_INFO_PARAMS; + +/* + * NV00FD_CTRL_CMD_ATTACH_MEM + * + * Attaches the physical memory handle and in turn the memory + * owner of the physical memory to the Multicast FLA object. + * + * hSubdevice [IN] + * Subdevice handle of the owner GPU + * + * hMemory [IN] + * Physical memory handle to be attached. + * + * offset [IN] + * Offset into the MCFLA object. (Must be zero for now, maybe used in future) + * Must be MCFLA pagesize aligned. + * + * mapOffSet [IN] + * Offset into the physical memory descriptor. + * Must be physical memory pagesize aligned. + * + * mapLength [IN] + * Length of physical memory handle to be mapped. + * Must be physical memory pagesize aligned and less than or equal to + * MCFLA alloc size + * + * flags [IN] + * For future use only. Must be zero for now. + * + * devDescriptor [IN] + * devDescriptor is a file descriptor for unix RM clients, but a void + * pointer for windows RM clients. It is transparent to RM clients i.e. RM's + * user-mode shim populates this field on behalf of clients. + * + * Restrictions: + * a. Memory belonging to only NVSwitch P2P supported GPUs + * which can do multicast can be attached + * b. Physical memory with 2MB pagesize is allowed + * c. Memory of an already attached GPU should not be attached + * d. Only vidmem physical memory handle can be attached + * + */ +#define NV00FD_CTRL_CMD_ATTACH_MEM (0xfd0102) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00FD_CTRL_ATTACH_MEM_PARAMS_MESSAGE_ID" */ + +#define NV00FD_CTRL_ATTACH_MEM_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV00FD_CTRL_ATTACH_MEM_PARAMS { + NvHandle hSubdevice; + NvHandle hMemory; + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NV_DECLARE_ALIGNED(NvU64 mapOffset, 8); + NV_DECLARE_ALIGNED(NvU64 mapLength, 8); + NvU32 flags; + NV_DECLARE_ALIGNED(NvU64 devDescriptor, 8); +} NV00FD_CTRL_ATTACH_MEM_PARAMS; + +/* + * NV00FD_CTRL_CMD_REGISTER_EVENT + * + * Allows clients to optionally register for events after the Multicast + * FLA object is duped under another client. + * + * pOsEvent [IN] + * OS event handle created with NvRmAllocOsEvent(). + * + */ +#define NV00FD_CTRL_CMD_REGISTER_EVENT (0xfd0103) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00FD_CTRL_REGISTER_EVENT_PARAMS_MESSAGE_ID" */ + +#define NV00FD_CTRL_REGISTER_EVENT_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV00FD_CTRL_REGISTER_EVENT_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pOsEvent, 8); +} NV00FD_CTRL_REGISTER_EVENT_PARAMS; + +/* _ctrl00fd_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl00fe.h b/src/common/sdk/nvidia/inc/ctrl/ctrl00fe.h new file mode 100644 index 000000000..2be1a0466 --- /dev/null +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl00fe.h @@ -0,0 +1,64 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl00fe.finn +// + +#define NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_FLAG_PAGE_KIND_SOURCE_ALLOCATION 0:0 +#define NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_FLAG_PAGE_KIND_SOURCE_ALLOCATION_PHYSICAL (0x00000000U) +#define NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_FLAG_PAGE_KIND_SOURCE_ALLOCATION_VIRTUAL (0x00000001U) + +typedef struct NV00FE_CTRL_PAGING_OPERATION { + NvHandle hVirtualMemory; + NV_DECLARE_ALIGNED(NvU64 virtualOffset, 8); + NvHandle hPhysicalMemory; + NV_DECLARE_ALIGNED(NvU64 physicalOffset, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NvU32 flags; +} NV00FE_CTRL_PAGING_OPERATION; + +/* + * NV00FE_CTRL_CMD_SUBMIT_PAGING_OPERATIONS + * + * Execute a list of paging operations + * Page size is determined by the virtual allocation + * Offsets/sizes must respect the page size + * + */ +#define NV00FE_CTRL_CMD_SUBMIT_PAGING_OPERATIONS (0xfe0002U) /* finn: Evaluated from "(FINN_NV_MEMORY_MAPPER_INTERFACE_ID << 8) | NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS_MESSAGE_ID" */ + +#define NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_MAX_COUNT (0x00010000U) + +#define NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS { + NvU32 pagingOpsCount; + NV_DECLARE_ALIGNED(NvP64 pagingOps, 8); +} NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS; + diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080.h index f7b7e6a1f..05f19cfcb 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080.h @@ -76,8 +76,7 @@ #include "ctrl2080/ctrl2080grmgr.h" #include "ctrl2080/ctrl2080ucodefuzzer.h" - - +#include "ctrl2080/ctrl2080vgpumgrinternal.h" #include "ctrl2080/ctrl2080hshub.h" /* include appropriate os-specific command header */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h index 9cbad13db..cf5835047 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h @@ -106,6 +106,243 @@ typedef struct NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS { NV2080_CTRL_BIOS_INFO biosInfoList[NV2080_CTRL_BIOS_INFO_MAX_SIZE]; } NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS; +/* + * NV2080_CTRL_BIOS_NBSI + * + * NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH + * This is the maximum length of a given registry string input (in characters). + * + * NV2080_CTRL_BIOS_NBSI_STRING_TYPE_ASCII + * This is a value indicating the format of a registry string is ascii. + * NV2080_CTRL_BIOS_NBSI_STRING_TYPE_UNICODE + * This is a value indicating the format of a registry string is unicode. + * NV2080_CTRL_BIOS_NBSI_STRING_TYPE_HASH + * This is a value indicating a registry string is actually a pre-hashed value. + * + * NV2080_CTRL_BIOS_NBSI_REG_STRING + * This is a structure used to store a registry string object. + * The members are as follows: + * + * size + * This is the size (in bytes) of the data contained in the string. If this + * is greater than the maximum registry string length, an error will be + * returned. + * type + * This is the type of data contained in the registry string. It can be either + * ascii, unicode or a pre-hashed value. + * value + * This is the value of the string. Depending on the type, a different object + * will be used to access the data. + */ +#define NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH (0x00000100) + +#define NV2080_CTRL_BIOS_NBSI_STRING_TYPE_ASCII (0x00000000) +#define NV2080_CTRL_BIOS_NBSI_STRING_TYPE_UNICODE (0x00000001) +#define NV2080_CTRL_BIOS_NBSI_STRING_TYPE_HASH (0x00000002) + +#define NV2080_CTRL_BIOS_NBSI_MODULE_ROOT (0x00000000) +#define NV2080_CTRL_BIOS_NBSI_MODULE_RM (0x00000001) +#define NV2080_CTRL_BIOS_NBSI_MODULE_DISPLAYDRIVER (0x00000002) +#define NV2080_CTRL_BIOS_NBSI_MODULE_VIDEO (0x00000003) +#define NV2080_CTRL_BIOS_NBSI_MODULE_CPL (0x00000004) +#define NV2080_CTRL_BIOS_NBSI_MODULE_D3D (0x00000005) +#define NV2080_CTRL_BIOS_NBSI_MODULE_OGL (0x00000006) +#define NV2080_CTRL_BIOS_NBSI_MODULE_PMU (0x00000007) +#define NV2080_CTRL_BIOS_NBSI_MODULE_MODE (0x00000008) +// this should equal the last NBSI_MODULE plus 1. +#define NV2080_CTRL_BIOS_NBSI_NUM_MODULES (0x00000009) + +// +// Never use this value! It's needed for DD/Video modules, but does not correspond +// to a valid NBSI hive! +// +#define NV2080_CTRL_BIOS_NBSI_MODULE_UNKNOWN (0x80000000) + +typedef struct NV2080_CTRL_BIOS_NBSI_REG_STRING { + NvU32 size; + NvU32 type; + + union { + NvU8 ascii[NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH]; + NvU16 unicode[NV2080_CTRL_BIOS_NBSI_MAX_REG_STRING_LENGTH]; + NvU16 hash; + } value; +} NV2080_CTRL_BIOS_NBSI_REG_STRING; + + +/* + * NV2080_CTRL_CMD_BIOS_GET_NBSI + * + * module + * This field specifies the given module per the MODULE_TYPES enum. + * path + * This field specifies the full path and registry node name for a + * given NBSI object. This is a maximum of 255 unicode characters, + * but may be provided as ascii or a pre-formed hash per the type + * member. The size (in bytes) of the given string/hash should be + * provided in the size member. + * + * NOTE: In the case of an incomplete path such as HKR, one may pass + * in simply the root node. E.g.: + * 1.) Normal case: HKLM\Path\Subpath + * 2.) Unknown case: HKR + * It is expected that all unknown/incomplete paths will be determined + * prior to NBSI programming! There is otherwise NO WAY to match + * the hash given by an incomplete path to that stored in NBSI! + * + * valueName + * This field specifies the registry name for a given NBSI object. + * This is a maximum of 255 unicode characters, but may be provided + * in ascii or a pre-formed hash per the type member. The size (in bytes) + * of the given string/hash should be provided in the size member. + * retBuf + * This field provides a pointer to a buffer into which the value + * retrieved from NBSI may be returned + * retSize + * This field is an input/output. It specifies the maximum size of the + * return buffer as an input, and the size of the returned data as an + * output. + * errorCode + * This field is a return value. It gives an error code representing + * failure to return a value (as opposed to failure of the call). + * This obeys the following: + * + * NV2080_CTRL_BIOS_GET_NBSI_SUCCESS + * The call has returned complete and valid data. + * NV2080_CTRL_BIOS_GET_NBSI_OVERRIDE + * The call returned complete and valid data which is expected to override + * any stored registry settings. + * NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE + * The call returned data, but the size of the return buffer was + * insufficient to contain it. The value returned in retSize represents + * the total size necessary (in bytes) to contain the data. + * if the size was non-0, the buffer is filled with the object contents up + * to that size. Can be used with retBufOffset to use multiple calls to get + * tables of very large size. + * NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND + * The call did not find a valid NBSI object for this key. This indicates + * NBSI has no opinion and, more importantly, any data returned is identical + * to data passed in. + * + * Possible return values are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_BIOS_GET_NBSI_SUCCESS (0x00000000) +#define NV2080_CTRL_BIOS_GET_NBSI_OVERRIDE (0x00000001) +#define NV2080_CTRL_BIOS_GET_NBSI_BAD_HASH (0xFFFFFFFA) +#define NV2080_CTRL_BIOS_GET_NBSI_APITEST_SUCCESS (0xFFFFFFFB) +#define NV2080_CTRL_BIOS_GET_NBSI_BAD_TABLE (0xFFFFFFFC) +#define NV2080_CTRL_BIOS_GET_NBSI_NO_TABLE (0xFFFFFFFD) +#define NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE (0xFFFFFFFE) +#define NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND (0xFFFFFFFF) + +#define NV2080_CTRL_CMD_BIOS_GET_NBSI (0x20800803) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_NBSI_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BIOS_GET_NBSI_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_BIOS_GET_NBSI_PARAMS { + NvU32 module; + NV2080_CTRL_BIOS_NBSI_REG_STRING path; + NV2080_CTRL_BIOS_NBSI_REG_STRING valueName; + NV_DECLARE_ALIGNED(NvP64 retBuf, 8); + NvU32 retSize; + NvU32 errorCode; +} NV2080_CTRL_BIOS_GET_NBSI_PARAMS; + +#define NV2080_CTRL_CMD_BIOS_GET_NBSI_V2 (0x2080080e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_BIOS_GET_NBSI_MAX_RET_SIZE (0x100) + +#define NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS { + NvU32 module; + NV2080_CTRL_BIOS_NBSI_REG_STRING path; + NV2080_CTRL_BIOS_NBSI_REG_STRING valueName; + NvU8 retBuf[NV2080_BIOS_GET_NBSI_MAX_RET_SIZE]; + NvU32 retSize; + NvU32 errorCode; +} NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS; + +/* + * NV2080_CTRL_CMD_BIOS_GET_NBSI_OBJ + * + * globType + * This field specifies the glob type wanted + * 0xffff: APItest... returns NV2080_CTRL_BIOS_GET_NBSI_APITEST_SUCCESS + * globIndex + * Index for globType desired + * 0 = best fit + * 1..255 = actual index + * globSource + * Index to nbsi directory sources used when getting entire directory + * 0 = registry + * 1 = VBIOS + * 2 = SBIOS + * 3 = ACPI + * retBufOffset + * When making multiple calls to get the object (if retSize is too small) + * offset into real object (0=start of object) + * retBuf + * This field provides a pointer to a buffer into which the object + * retrieved from NBSI may be returned + * retSize + * This field is an input/output. It specifies the maximum size of the + * return buffer as an input, and the size of the returned data as an + * output. + * totalObjSize + * This field is an output, where the total size of the object being + * retrieved is returned. + * errorCode + * This field is a return value. It gives an error code representing + * failure to return a value (as opposed to failure of the call). + * This obeys the following: + * + * NV2080_CTRL_BIOS_GET_NBSI_SUCCESS + * The call has returned complete and valid data. + * NV2080_CTRL_BIOS_GET_NBSI_OVERRIDE + * The call returned complete and valid data which is expected to override + * any stored registry settings. + * NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE + * The call returned data, but the size of the return buffer was + * insufficient to contain it. The value returned in retSize represents + * the total size necessary (in bytes) to contain the data. + * NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND + * The call did not find a valid NBSI object for this key. This indicates + * NBSI has no opinion and, more importantly, any data returned is identical + * to data passed in. + * + * Possible return values are: + * NV2080_CTRL_BIOS_GET_NBSI_SUCCESS + * NV2080_CTRL_BIOS_GET_NBSI_APITEST_NODIRACCESS + * NV2080_CTRL_BIOS_GET_NBSI_APITEST_SUCCESS + * NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE + * NV2080_CTRL_BIOS_GET_NBSI_BAD_TABLE + * NV2080_CTRL_BIOS_GET_NBSI_NO_TABLE + * NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND + */ +#define NV2080_CTRL_CMD_BIOS_GET_NBSI_OBJ (0x20800806) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS { + NvU16 globType; + NvU8 globIndex; + NvU16 globSource; + NvU32 retBufOffset; + NV_DECLARE_ALIGNED(NvP64 retBuf, 8); + NvU32 retSize; + NvU32 totalObjSize; + NvU32 errorCode; +} NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS; + +#define GLOB_TYPE_GET_NBSI_DIR 0xfffe +#define GLOB_TYPE_APITEST 0xffff +#define GLOB_TYPE_GET_NBSI_ACPI_RAW 0xfffd + /* diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h index 307b66f1f..eb8d97954 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h @@ -363,6 +363,7 @@ typedef struct NV2080_CTRL_BUS_INFO { #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_8000MBPS (0x00000003) #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_16000MBPS (0x00000004) #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_32000MBPS (0x00000005) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_64000MBPS (0x00000006) #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_WIDTH 9:4 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM 11:10 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_ASPM_NONE (0x00000000) @@ -374,18 +375,21 @@ typedef struct NV2080_CTRL_BUS_INFO { #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN3 (0x00000002) #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN4 (0x00000003) #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN5 (0x00000004) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GEN_GEN6 (0x00000005) #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL 19:16 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN1 (0x00000000) #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN2 (0x00000001) #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN3 (0x00000002) #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN4 (0x00000003) #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN5 (0x00000004) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_CURR_LEVEL_GEN6 (0x00000005) #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN 23:20 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN1 (0x00000000) #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN2 (0x00000001) #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN3 (0x00000002) #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN4 (0x00000003) #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN5 (0x00000004) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_GPU_GEN_GEN6 (0x00000005) #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES 24:24 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES_ENABLED (0x00000000) #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_SPEED_CHANGES_DISABLED (0x00000001) @@ -402,6 +406,7 @@ typedef struct NV2080_CTRL_BUS_INFO { #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_8000MBPS (0x00000003) #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_16000MBPS (0x00000004) #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_32000MBPS (0x00000005) +#define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_64000MBPS (0x00000006) #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH 25:20 #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_UNDEFINED (0x00000000) #define NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_WIDTH_X1 (0x00000001) @@ -708,6 +713,7 @@ typedef struct NV2080_CTRL_BUS_SET_PCIE_SPEED_PARAMS { #define NV2080_CTRL_BUS_SET_PCIE_SPEED_8000MBPS (0x00000003) #define NV2080_CTRL_BUS_SET_PCIE_SPEED_16000MBPS (0x00000004) #define NV2080_CTRL_BUS_SET_PCIE_SPEED_32000MBPS (0x00000005) +#define NV2080_CTRL_BUS_SET_PCIE_SPEED_64000MBPS (0x00000006) /* * NV2080_CTRL_CMD_BUS_SET_HWBC_UPSTREAM_PCIE_SPEED @@ -1492,3 +1498,91 @@ typedef struct NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS { } errCnts[NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES * NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE]; } NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING + * + * This command sets P2P mapping. + * + * connectionType[IN] + * Connection type, one of NV2080_CTRL_CMD_BUS_SET_P2P_MAPPINGS_CONNECTION + * peerId[IN] + * peerId of remote GPU from local GPU on which call is made. + * bSpaAccessOnly[IN] + * SPA access only. SPA addressing mode is supported when we support ATS. + * bUseUuid [in] + * Option only available for Guest RPCs and is not avaliable for external clients. + * Set to NV_TRUE to use remoteGpuUuid in lieu of remoteGpuId to identify target GPU. + * remoteGpuId[IN] + * GPU ID of remote GPU. + * remoteGpuUuid [in] + * Alternative to gpuId; used to identify target GPU for which caps are being queried. + * Option only available for Guest RPCs. + * If bUseUuid == NV_TRUE, gpuUuid is used in lieu of gpuId to identify target GPU. + * If bUseUuid == NV_FALSE, gpuUuid is ignored and gpuId is used by default. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING (0x2080182e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_INVALID 0 +#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_NVLINK 1 +#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_PCIE 2 +#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_PCIE_BAR1 3 +#define NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_C2C 4 + +#define NV2080_SET_P2P_MAPPING_UUID_LEN 16U + +#define NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_MESSAGE_ID (0x2EU) + +typedef struct NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS { + NvU32 connectionType; + NvU32 peerId; + NvBool bSpaAccessOnly; + NvBool bUseUuid; + NvU32 remoteGpuId; + NvU8 remoteGpuUuid[NV2080_SET_P2P_MAPPING_UUID_LEN]; +} NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS; + +/* + * NV2080_CTRL_CMD_BUS_UNSET_P2P_MAPPING + * + * This command unsets P2P mapping. + * + * connectionType[IN] + * Connection type, one of NV2080_CTRL_CMD_BUS_SET_P2P_MAPPINGS_CONNECTION + * peerId[IN] + * peerId of remote GPU from local GPU on which call is mad. + * bUseUuid [in] + * Option only available for Guest RPCs and is not avaliable for external clients. + * Set to NV_TRUE to use remoteGpuUuid in lieu of remoteGpuId to identify target GPU. + * remoteGpuId[IN] + * GPU ID of remote GPU. + * remoteGpuUuid [in] + * Alternative to gpuId; used to identify target GPU for which caps are being queried. + * Option only available for Guest RPCs. + * If bUseUuid == NV_TRUE, gpuUuid is used in lieu of gpuId to identify target GPU. + * If bUseUuid == NV_FALSE, gpuUuid is ignored and gpuId is used by default. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_BUS_UNSET_P2P_MAPPING (0x2080182f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_MESSAGE_ID (0x2FU) + +typedef struct NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS { + NvU32 connectionType; + NvU32 peerId; + NvBool bUseUuid; + NvU32 remoteGpuId; + NvU8 remoteGpuUuid[NV2080_SET_P2P_MAPPING_UUID_LEN]; +} NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS; + diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h index 179297e43..d2f5424a3 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h @@ -32,9 +32,10 @@ -/* NV20_SUBDEVICE_XX ce control commands and parameters */ +#include "nvcfg_sdk.h" -#include "ctrl2080common.h" + +/* NV20_SUBDEVICE_XX ce control commands and parameters */ /* * NV2080_CTRL_CMD_CE_GET_CAPS @@ -139,7 +140,7 @@ typedef struct NV2080_CTRL_CE_GET_CAPS_V2_PARAMS { /* * NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK * - * This command returns the mapping of PCE's for the given LCE + * This command returns the mapping of PCE's for the given LCE. * * ceEngineType * This parameter specifies the copy engine type @@ -153,6 +154,8 @@ typedef struct NV2080_CTRL_CE_GET_CAPS_V2_PARAMS { * NV_ERR_INVALID_ARGUMENT */ + + #define NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK (0x20802a02) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID (0x2U) @@ -198,13 +201,13 @@ typedef struct NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS { * * This command updates the PCE-LCE mappings * - * pPceLceMap [IN] + * pceLceMap [IN] * This parameter contains the array of PCE to LCE mappings. * The array is indexed by the PCE index, and contains the * LCE index that the PCE is assigned to. A unused PCE is * tagged with NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_INVALID_LCE. * - * pGrceConfig [IN] + * grceConfig [IN] * This parameter contains the array of GRCE configs. * 0xF -> GRCE does not share with any LCE * 0-MAX_LCE -> GRCE shares with the given LCE @@ -238,6 +241,18 @@ typedef struct NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS { #define NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_INVALID_LCE 0xf +/* + * NV2080_CTRL_CMD_CE_UPDATE_CLASS_DB + * + * This function triggers an update of the exported CE classes. CEs with + * no physical resources will not be exported. A record of these + * will be return in in the stubbedCeMask. + * + * An example if NV2080_ENGINE_TYPE_COPY4 is stubbed (1<<4) will be + * set in stubbedCeMask. + */ + + #define NV2080_CTRL_CMD_CE_UPDATE_CLASS_DB (0x20802a06) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID (0x6U) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h index 1ad616fff..e72e63c38 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h @@ -34,8 +34,6 @@ /* NV20_SUBDEVICE_XX dma control commands and parameters */ -#include "ctrl2080common.h" - /* * NV2080_CTRL_CMD_DMA_INVALIDATE_TLB * diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h index 411a59d89..7d0fabe24 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h @@ -34,7 +34,7 @@ -#define NV2080_CTRL_CMD_ECC_GET_CLIENT_EXPOSED_COUNTERS (0x20803400) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_ECC_GET_CLIENT_EXPOSED_COUNTERS (0x20803400U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS_MESSAGE_ID" */ /* * NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h index b25e3cd3f..a88332650 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h @@ -34,7 +34,6 @@ /* NV20_SUBDEVICE_XX fb control commands and parameters */ -#include "ctrl2080common.h" #include "nvlimits.h" /* @@ -274,114 +273,114 @@ typedef struct NV2080_CTRL_FB_INFO { } NV2080_CTRL_FB_INFO; /* valid fb info index values */ -#define NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_COUNT (0x00000000) // Deprecated -#define NV2080_CTRL_FB_INFO_INDEX_COMPRESSION_SIZE (0x00000001) -#define NV2080_CTRL_FB_INFO_INDEX_DRAM_PAGE_STRIDE (0x00000002) -#define NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_FREE_COUNT (0x00000003) -#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_COUNT (0x00000004) -#define NV2080_CTRL_FB_INFO_INDEX_BAR1_SIZE (0x00000005) -#define NV2080_CTRL_FB_INFO_INDEX_BANK_SWIZZLE_ALIGNMENT (0x00000006) -#define NV2080_CTRL_FB_INFO_INDEX_RAM_SIZE (0x00000007) -#define NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE (0x00000008) -#define NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE (0x00000009) -#define NV2080_CTRL_FB_INFO_INDEX_MAPPABLE_HEAP_SIZE (0x0000000A) -#define NV2080_CTRL_FB_INFO_INDEX_BUS_WIDTH (0x0000000B) -#define NV2080_CTRL_FB_INFO_INDEX_RAM_CFG (0x0000000C) -#define NV2080_CTRL_FB_INFO_INDEX_RAM_TYPE (0x0000000D) -#define NV2080_CTRL_FB_INFO_INDEX_BANK_COUNT (0x0000000E) -#define NV2080_CTRL_FB_INFO_INDEX_OVERLAY_OFFSET_ADJUSTMENT (0x0000000F) // Deprecated (index reused to return 0) -#define NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_SPACE_SIZE_KB (0x0000000F) // Deprecated (index reused to return 0) -#define NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_HEAP_SIZE_KB (0x0000000F) // Deprecated (index reused to return 0) -#define NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_MAPPBLE_SIZE_KB (0x0000000F) // Deprecated (index reused to return 0) -#define NV2080_CTRL_FB_INFO_INDEX_EFFECTIVE_BW (0x0000000F) // Deprecated (index reused to return 0) -#define NV2080_CTRL_FB_INFO_INDEX_FB_TAX_SIZE_KB (0x00000010) -#define NV2080_CTRL_FB_INFO_INDEX_HEAP_BASE_KB (0x00000011) -#define NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_SIZE_KB (0x00000012) -#define NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_BASE_KB (0x00000013) -#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK (0x00000014) -#define NV2080_CTRL_FB_INFO_INDEX_VISTA_RESERVED_HEAP_SIZE (0x00000015) -#define NV2080_CTRL_FB_INFO_INDEX_HEAP_FREE (0x00000016) -#define NV2080_CTRL_FB_INFO_INDEX_RAM_LOCATION (0x00000017) -#define NV2080_CTRL_FB_INFO_INDEX_FB_IS_BROKEN (0x00000018) -#define NV2080_CTRL_FB_INFO_INDEX_FBP_COUNT (0x00000019) -#define NV2080_CTRL_FB_INFO_INDEX_FBP_MASK (0x0000001A) -#define NV2080_CTRL_FB_INFO_INDEX_L2CACHE_SIZE (0x0000001B) -#define NV2080_CTRL_FB_INFO_INDEX_MEMORYINFO_VENDOR_ID (0x0000001C) -#define NV2080_CTRL_FB_INFO_INDEX_BAR1_AVAIL_SIZE (0x0000001D) -#define NV2080_CTRL_FB_INFO_INDEX_HEAP_START (0x0000001E) -#define NV2080_CTRL_FB_INFO_INDEX_BAR1_MAX_CONTIGUOUS_AVAIL_SIZE (0x0000001F) -#define NV2080_CTRL_FB_INFO_INDEX_USABLE_RAM_SIZE (0x00000020) -#define NV2080_CTRL_FB_INFO_INDEX_TRAINIG_2T (0x00000021) -#define NV2080_CTRL_FB_INFO_INDEX_LTC_COUNT (0x00000022) -#define NV2080_CTRL_FB_INFO_INDEX_LTS_COUNT (0x00000023) -#define NV2080_CTRL_FB_INFO_INDEX_L2CACHE_ONLY_MODE (0x00000024) -#define NV2080_CTRL_FB_INFO_INDEX_PSEUDO_CHANNEL_MODE (0x00000025) -#define NV2080_CTRL_FB_INFO_INDEX_SMOOTHDISP_RSVD_BAR1_SIZE (0x00000026) -#define NV2080_CTRL_FB_INFO_INDEX_HEAP_OFFLINE_SIZE (0x00000027) -#define NV2080_CTRL_FB_INFO_INDEX_1TO1_COMPTAG_ENABLED (0x00000028) -#define NV2080_CTRL_FB_INFO_INDEX_SUSPEND_RESUME_RSVD_SIZE (0x00000029) -#define NV2080_CTRL_FB_INFO_INDEX_ALLOW_PAGE_RETIREMENT (0x0000002A) -#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK (0x0000002B) -#define NV2080_CTRL_FB_INFO_POISON_FUSE_ENABLED (0x0000002C) -#define NV2080_CTRL_FB_INFO_FBPA_ECC_ENABLED (0x0000002D) -#define NV2080_CTRL_FB_INFO_DYNAMIC_PAGE_OFFLINING_ENABLED (0x0000002E) -#define NV2080_CTRL_FB_INFO_INDEX_FORCED_BAR1_64KB_MAPPING_ENABLED (0x0000002F) -#define NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_SIZE (0x00000030) -#define NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_ALIGNMENT (0x00000031) -#define NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_BAR1_MAX_OFFSET_64KB (0x00000032) -#define NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_TOTAL_KB (0x00000033) -#define NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_FREE_KB (0x00000034) -#define NV2080_CTRL_FB_INFO_INDEX_ECC_STATUS_SIZE (0x00000035) -#define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE (0x00000036) +#define NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_COUNT (0x00000000U) // Deprecated +#define NV2080_CTRL_FB_INFO_INDEX_COMPRESSION_SIZE (0x00000001U) +#define NV2080_CTRL_FB_INFO_INDEX_DRAM_PAGE_STRIDE (0x00000002U) +#define NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_FREE_COUNT (0x00000003U) +#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_COUNT (0x00000004U) +#define NV2080_CTRL_FB_INFO_INDEX_BAR1_SIZE (0x00000005U) +#define NV2080_CTRL_FB_INFO_INDEX_BANK_SWIZZLE_ALIGNMENT (0x00000006U) +#define NV2080_CTRL_FB_INFO_INDEX_RAM_SIZE (0x00000007U) +#define NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE (0x00000008U) +#define NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE (0x00000009U) +#define NV2080_CTRL_FB_INFO_INDEX_MAPPABLE_HEAP_SIZE (0x0000000AU) +#define NV2080_CTRL_FB_INFO_INDEX_BUS_WIDTH (0x0000000BU) +#define NV2080_CTRL_FB_INFO_INDEX_RAM_CFG (0x0000000CU) +#define NV2080_CTRL_FB_INFO_INDEX_RAM_TYPE (0x0000000DU) +#define NV2080_CTRL_FB_INFO_INDEX_BANK_COUNT (0x0000000EU) +#define NV2080_CTRL_FB_INFO_INDEX_OVERLAY_OFFSET_ADJUSTMENT (0x0000000FU) // Deprecated (index reused to return 0) +#define NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_SPACE_SIZE_KB (0x0000000FU) // Deprecated (index reused to return 0) +#define NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_HEAP_SIZE_KB (0x0000000FU) // Deprecated (index reused to return 0) +#define NV2080_CTRL_FB_INFO_INDEX_GPU_VADDR_MAPPBLE_SIZE_KB (0x0000000FU) // Deprecated (index reused to return 0) +#define NV2080_CTRL_FB_INFO_INDEX_EFFECTIVE_BW (0x0000000FU) // Deprecated (index reused to return 0) +#define NV2080_CTRL_FB_INFO_INDEX_FB_TAX_SIZE_KB (0x00000010U) +#define NV2080_CTRL_FB_INFO_INDEX_HEAP_BASE_KB (0x00000011U) +#define NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_SIZE_KB (0x00000012U) +#define NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_BASE_KB (0x00000013U) +#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK (0x00000014U) +#define NV2080_CTRL_FB_INFO_INDEX_VISTA_RESERVED_HEAP_SIZE (0x00000015U) +#define NV2080_CTRL_FB_INFO_INDEX_HEAP_FREE (0x00000016U) +#define NV2080_CTRL_FB_INFO_INDEX_RAM_LOCATION (0x00000017U) +#define NV2080_CTRL_FB_INFO_INDEX_FB_IS_BROKEN (0x00000018U) +#define NV2080_CTRL_FB_INFO_INDEX_FBP_COUNT (0x00000019U) +#define NV2080_CTRL_FB_INFO_INDEX_FBP_MASK (0x0000001AU) +#define NV2080_CTRL_FB_INFO_INDEX_L2CACHE_SIZE (0x0000001BU) +#define NV2080_CTRL_FB_INFO_INDEX_MEMORYINFO_VENDOR_ID (0x0000001CU) +#define NV2080_CTRL_FB_INFO_INDEX_BAR1_AVAIL_SIZE (0x0000001DU) +#define NV2080_CTRL_FB_INFO_INDEX_HEAP_START (0x0000001EU) +#define NV2080_CTRL_FB_INFO_INDEX_BAR1_MAX_CONTIGUOUS_AVAIL_SIZE (0x0000001FU) +#define NV2080_CTRL_FB_INFO_INDEX_USABLE_RAM_SIZE (0x00000020U) +#define NV2080_CTRL_FB_INFO_INDEX_TRAINIG_2T (0x00000021U) +#define NV2080_CTRL_FB_INFO_INDEX_LTC_COUNT (0x00000022U) +#define NV2080_CTRL_FB_INFO_INDEX_LTS_COUNT (0x00000023U) +#define NV2080_CTRL_FB_INFO_INDEX_L2CACHE_ONLY_MODE (0x00000024U) +#define NV2080_CTRL_FB_INFO_INDEX_PSEUDO_CHANNEL_MODE (0x00000025U) +#define NV2080_CTRL_FB_INFO_INDEX_SMOOTHDISP_RSVD_BAR1_SIZE (0x00000026U) +#define NV2080_CTRL_FB_INFO_INDEX_HEAP_OFFLINE_SIZE (0x00000027U) +#define NV2080_CTRL_FB_INFO_INDEX_1TO1_COMPTAG_ENABLED (0x00000028U) +#define NV2080_CTRL_FB_INFO_INDEX_SUSPEND_RESUME_RSVD_SIZE (0x00000029U) +#define NV2080_CTRL_FB_INFO_INDEX_ALLOW_PAGE_RETIREMENT (0x0000002AU) +#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK (0x0000002BU) +#define NV2080_CTRL_FB_INFO_POISON_FUSE_ENABLED (0x0000002CU) +#define NV2080_CTRL_FB_INFO_FBPA_ECC_ENABLED (0x0000002DU) +#define NV2080_CTRL_FB_INFO_DYNAMIC_PAGE_OFFLINING_ENABLED (0x0000002EU) +#define NV2080_CTRL_FB_INFO_INDEX_FORCED_BAR1_64KB_MAPPING_ENABLED (0x0000002FU) +#define NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_SIZE (0x00000030U) +#define NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_ALIGNMENT (0x00000031U) +#define NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_BAR1_MAX_OFFSET_64KB (0x00000032U) +#define NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_TOTAL_KB (0x00000033U) +#define NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_FREE_KB (0x00000034U) +#define NV2080_CTRL_FB_INFO_INDEX_ECC_STATUS_SIZE (0x00000035U) +#define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE (0x00000036U) -#define NV2080_CTRL_FB_INFO_INDEX_MAX (0x35) /* finn: Evaluated from "(NV2080_CTRL_FB_INFO_MAX_LIST_SIZE - 1)" */ +#define NV2080_CTRL_FB_INFO_INDEX_MAX (0x35U) /* finn: Evaluated from "(NV2080_CTRL_FB_INFO_MAX_LIST_SIZE - 1)" */ /* valid fb RAM type values */ -#define NV2080_CTRL_FB_INFO_RAM_TYPE_UNKNOWN (0x00000000) -#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDRAM (0x00000001) -#define NV2080_CTRL_FB_INFO_RAM_TYPE_DDR1 (0x00000002) /* SDDR and GDDR (aka DDR1 and GDDR1) */ -#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR2 (0x00000003) /* SDDR2 Used on NV43 and later */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_UNKNOWN (0x00000000U) +#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDRAM (0x00000001U) +#define NV2080_CTRL_FB_INFO_RAM_TYPE_DDR1 (0x00000002U) /* SDDR and GDDR (aka DDR1 and GDDR1) */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR2 (0x00000003U) /* SDDR2 Used on NV43 and later */ #define NV2080_CTRL_FB_INFO_RAM_TYPE_DDR2 NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR2 /* Deprecated alias */ -#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR2 (0x00000004) /* GDDR2 Used on NV30 and some NV36 */ -#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR3 (0x00000005) /* GDDR3 Used on NV40 and later */ -#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR4 (0x00000006) /* GDDR4 Used on G80 and later (deprecated) */ -#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR3 (0x00000007) /* SDDR3 Used on G9x and later */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR2 (0x00000004U) /* GDDR2 Used on NV30 and some NV36 */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR3 (0x00000005U) /* GDDR3 Used on NV40 and later */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR4 (0x00000006U) /* GDDR4 Used on G80 and later (deprecated) */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR3 (0x00000007U) /* SDDR3 Used on G9x and later */ #define NV2080_CTRL_FB_INFO_RAM_TYPE_DDR3 NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR3 /* Deprecated alias */ -#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5 (0x00000008) /* GDDR5 Used on GT21x and later */ -#define NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR2 (0x00000009) /* LPDDR (Low Power SDDR) used on T2x and later. */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5 (0x00000008U) /* GDDR5 Used on GT21x and later */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR2 (0x00000009U) /* LPDDR (Low Power SDDR) used on T2x and later. */ -#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR4 (0x0000000C) /* SDDR4 Used on Maxwell and later */ -#define NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR4 (0x0000000D) /* LPDDR (Low Power SDDR) used on T21x and later.*/ -#define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM1 (0x0000000E) /* HBM1 (High Bandwidth Memory) used on GP100 */ -#define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM2 (0x0000000F) /* HBM2 (High Bandwidth Memory-pseudo channel) */ -#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5X (0x00000010) /* GDDR5X Used on GP10x */ -#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6 (0x00000011) /* GDDR6 Used on TU10x */ -#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6X (0x00000012) /* GDDR6X Used on GA10x */ -#define NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR5 (0x00000013) /* LPDDR (Low Power SDDR) used on T23x and later.*/ -#define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM3 (0x00000014) /* HBM3 (High Bandwidth Memory) v3 */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_SDDR4 (0x0000000CU) /* SDDR4 Used on Maxwell and later */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR4 (0x0000000DU) /* LPDDR (Low Power SDDR) used on T21x and later.*/ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM1 (0x0000000EU) /* HBM1 (High Bandwidth Memory) used on GP100 */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM2 (0x0000000FU) /* HBM2 (High Bandwidth Memory-pseudo channel) */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR5X (0x00000010U) /* GDDR5X Used on GP10x */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6 (0x00000011U) /* GDDR6 Used on TU10x */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR6X (0x00000012U) /* GDDR6X Used on GA10x */ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR5 (0x00000013U) /* LPDDR (Low Power SDDR) used on T23x and later.*/ +#define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM3 (0x00000014U) /* HBM3 (High Bandwidth Memory) v3 */ /* valid RAM LOCATION types */ -#define NV2080_CTRL_FB_INFO_RAM_LOCATION_GPU_DEDICATED (0x00000000) -#define NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_SHARED (0x00000001) -#define NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_DEDICATED (0x00000002) +#define NV2080_CTRL_FB_INFO_RAM_LOCATION_GPU_DEDICATED (0x00000000U) +#define NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_SHARED (0x00000001U) +#define NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_DEDICATED (0x00000002U) /* valid Memory Vendor ID values */ -#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_SAMSUNG (0x00000001) -#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_QIMONDA (0x00000002) -#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ELPIDA (0x00000003) -#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ETRON (0x00000004) -#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_NANYA (0x00000005) -#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_HYNIX (0x00000006) -#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MOSEL (0x00000007) -#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_WINBOND (0x00000008) -#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ESMT (0x00000009) -#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MICRON (0x0000000F) -#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_UNKNOWN (0xFFFFFFFF) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_SAMSUNG (0x00000001U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_QIMONDA (0x00000002U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ELPIDA (0x00000003U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ETRON (0x00000004U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_NANYA (0x00000005U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_HYNIX (0x00000006U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MOSEL (0x00000007U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_WINBOND (0x00000008U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_ESMT (0x00000009U) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_MICRON (0x0000000FU) +#define NV2080_CTRL_FB_INFO_MEMORYINFO_VENDOR_ID_UNKNOWN (0xFFFFFFFFU) -#define NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_UNSUPPORTED (0x00000000) -#define NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_DISABLED (0x00000001) -#define NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_ENABLED (0x00000002) +#define NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_UNSUPPORTED (0x00000000U) +#define NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_DISABLED (0x00000001U) +#define NV2080_CTRL_FB_INFO_PSEUDO_CHANNEL_MODE_ENABLED (0x00000002U) /** * NV2080_CTRL_CMD_FB_GET_INFO @@ -405,7 +404,7 @@ typedef struct NV2080_CTRL_FB_INFO { * NV_ERR_INVALID_ARGUMENT * NV_ERR_OPERATING_SYSTEM */ -#define NV2080_CTRL_CMD_FB_GET_INFO (0x20801301) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_INFO_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_GET_INFO (0x20801301U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_INFO_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_FB_GET_INFO_PARAMS_MESSAGE_ID (0x1U) @@ -414,7 +413,7 @@ typedef struct NV2080_CTRL_FB_GET_INFO_PARAMS { NV_DECLARE_ALIGNED(NvP64 fbInfoList, 8); } NV2080_CTRL_FB_GET_INFO_PARAMS; -#define NV2080_CTRL_CMD_FB_GET_INFO_V2 (0x20801303) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_INFO_V2_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_GET_INFO_V2 (0x20801303U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_INFO_V2_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_FB_GET_INFO_V2_PARAMS_MESSAGE_ID (0x3U) @@ -437,7 +436,7 @@ typedef struct NV2080_CTRL_FB_GET_INFO_V2_PARAMS { * Note that both parameters will contain zero if there is no system tile * address space. */ -#define NV2080_CTRL_CMD_FB_GET_TILE_ADDRESS_INFO (0x20801302) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2" */ +#define NV2080_CTRL_CMD_FB_GET_TILE_ADDRESS_INFO (0x20801302U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2" */ typedef struct NV2080_CTRL_FB_GET_SYSTEM_TILE_ADDRESS_SPACE_INFO { NV_DECLARE_ALIGNED(NvU64 StartAddr, 8); @@ -463,7 +462,7 @@ typedef struct NV2080_CTRL_FB_GET_SYSTEM_TILE_ADDRESS_SPACE_INFO { * NV_ERR_NOT_SUPPORTED * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_CMD_FB_GET_BAR1_OFFSET (0x20801310) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_GET_BAR1_OFFSET (0x20801310U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS_MESSAGE_ID (0x10U) @@ -490,7 +489,7 @@ typedef struct NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS { * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_FB_GET_CARVEOUT_ADDRESS_INFO (0x2080130b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_SYSTEM_CARVEOUT_ADDRESS_SPACE_INFO_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_GET_CARVEOUT_ADDRESS_INFO (0x2080130bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_SYSTEM_CARVEOUT_ADDRESS_SPACE_INFO_MESSAGE_ID" */ #define NV2080_CTRL_FB_GET_SYSTEM_CARVEOUT_ADDRESS_SPACE_INFO_MESSAGE_ID (0xBU) @@ -527,7 +526,7 @@ typedef struct NV2080_CTRL_FB_GET_SYSTEM_CARVEOUT_ADDRESS_SPACE_INFO { * NVOS_STATUS_NOT_SUPPORTED * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_CMD_FB_GET_CALIBRATION_LOCK_FAILED (0x2080130c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_GET_CALIBRATION_LOCK_FAILED (0x2080130cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS_MESSAGE_ID (0xCU) @@ -541,8 +540,8 @@ typedef struct NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS { } NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS; /* valid flags parameter values */ -#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_NONE (0x00000000) -#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_RESET (0x00000001) +#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_NONE (0x00000000U) +#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_RESET (0x00000001U) /* * NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_ALLOWED @@ -574,7 +573,7 @@ typedef struct NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS { * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_ALLOWED (0x2080130d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0xD" */ // Deprecated, removed form RM +#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_ALLOWED (0x2080130dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0xD" */ // Deprecated, removed form RM typedef struct NV2080_CTRL_FB_SET_SCANOUT_COMPACTION_ALLOWED_PARAMS { NvU32 allowCompaction; @@ -582,12 +581,12 @@ typedef struct NV2080_CTRL_FB_SET_SCANOUT_COMPACTION_ALLOWED_PARAMS { } NV2080_CTRL_FB_SET_SCANOUT_COMPACTION_ALLOWED_PARAMS; /* valid allowCompaction values */ -#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_ALLOW (0x00000001) -#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_DISALLOW (0x00000000) +#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_ALLOW (0x00000001U) +#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_DISALLOW (0x00000000U) /* valid immediate values */ -#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_IMMEDIATE (000000001) -#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_NOT_IMMEDIATE (000000000) +#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_IMMEDIATE (000000001U) +#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_NOT_IMMEDIATE (000000000U) /* * NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE @@ -632,9 +631,9 @@ typedef struct NV2080_CTRL_FB_SET_SCANOUT_COMPACTION_ALLOWED_PARAMS { * supports it. Use this call if you want to flush a single allocation and * you have a memory object describing the physical memory. */ -#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE (0x2080130e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE (0x2080130eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES 500 +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES 500U #define NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID (0xEU) @@ -648,21 +647,21 @@ typedef struct NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS { /* valid fields and values for flags */ #define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE 1:0 -#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_VIDEO_MEMORY (0x00000000) -#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_SYSTEM_MEMORY (0x00000001) -#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_PEER_MEMORY (0x00000002) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_VIDEO_MEMORY (0x00000000U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_SYSTEM_MEMORY (0x00000001U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_APERTURE_PEER_MEMORY (0x00000002U) #define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK 2:2 -#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_NO (0x00000000) -#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_YES (0x00000001) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_NO (0x00000000U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_WRITE_BACK_YES (0x00000001U) #define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE 3:3 -#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_NO (0x00000000) -#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_YES (0x00000001) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_NO (0x00000000U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_INVALIDATE_YES (0x00000001U) #define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE 4:4 -#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE_ADDRESS_ARRAY (0x00000000) -#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE_FULL_CACHE (0x00000001) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE_ADDRESS_ARRAY (0x00000000U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FLUSH_MODE_FULL_CACHE (0x00000001U) #define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH 5:5 -#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_NO (0x00000000) -#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_YES (0x00000001) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_NO (0x00000000U) +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_FLAGS_FB_FLUSH_YES (0x00000001U) /* * NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY (deprecated; use NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2 instead) @@ -687,11 +686,11 @@ typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS { /* valid values for allocPolicy */ #define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS 0:0 -#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS_NO (0x00000000) -#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS_YES (0x00000001) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS_NO (0x00000000U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS_YES (0x00000001U) #define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES 1:1 -#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES_NO (0x00000000) -#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES_YES (0x00000001) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES_NO (0x00000000U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES_YES (0x00000001U) /* @@ -708,7 +707,7 @@ typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS { * NV_ERR_NOT_SUPPORTED * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY (0x2080130f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0xF" */ +#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY (0x2080130fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0xF" */ /* * NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAM @@ -736,7 +735,7 @@ typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS { * * Specifies the maximum number of allocation policy entries allowed */ -#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY_SIZE 11 +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY_SIZE 11U typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_ENTRY { NvU32 client; @@ -750,17 +749,17 @@ typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS { /* valid values for allocPolicy */ #define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS 0:0 -#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_DISABLE (0x00000000) -#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_ENABLE (0x00000001) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_DISABLE (0x00000000U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_ENABLE (0x00000001U) #define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_ALLOW 1:1 -#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_ALLOW_NO (0x00000000) -#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_ALLOW_YES (0x00000001) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_ALLOW_NO (0x00000000U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_READS_ALLOW_YES (0x00000001U) #define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES 2:2 -#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_DISABLE (0x00000000) -#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_ENABLE (0x00000001) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_DISABLE (0x00000000U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_ENABLE (0x00000001U) #define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_ALLOW 3:3 -#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_ALLOW_NO (0x00000000) -#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_ALLOW_YES (0x00000001) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_ALLOW_NO (0x00000000U) +#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_WRITES_ALLOW_YES (0x00000001U) /* @@ -774,7 +773,7 @@ typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS { * NV_ERR_NOT_SUPPORTED * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY_V2 (0x20801318) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x18" */ +#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY_V2 (0x20801318U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x18" */ /* * NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY (deprecated; use NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2 instead) @@ -787,7 +786,7 @@ typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS { * NV_ERR_NOT_SUPPORTED * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY (0x20801312) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x12" */ +#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY (0x20801312U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x12" */ /* * NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2 @@ -800,7 +799,7 @@ typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS { * NV_ERR_NOT_SUPPORTED * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2 (0x20801319) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x19" */ +#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2 (0x20801319U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x19" */ /* @@ -876,7 +875,7 @@ typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS { * NV_OK * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_CMD_FB_IS_KIND (0x20801313) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_IS_KIND (0x20801313U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID (0x13U) @@ -887,15 +886,15 @@ typedef struct NV2080_CTRL_FB_IS_KIND_PARAMS { } NV2080_CTRL_FB_IS_KIND_PARAMS; /* valid values for operation */ -#define NV2080_CTRL_FB_IS_KIND_OPERATION_SUPPORTED (0x00000000) -#define NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE (0x00000001) -#define NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_1 (0x00000002) -#define NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_2 (0x00000003) -#define NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_4 (0x00000004) -#define NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC (0x00000005) -#define NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_1 (0x00000006) -#define NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_2 (0x00000007) -#define NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_4 (0x00000008) +#define NV2080_CTRL_FB_IS_KIND_OPERATION_SUPPORTED (0x00000000U) +#define NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE (0x00000001U) +#define NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_1 (0x00000002U) +#define NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_2 (0x00000003U) +#define NV2080_CTRL_FB_IS_KIND_OPERATION_COMPRESSIBLE_4 (0x00000004U) +#define NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC (0x00000005U) +#define NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_1 (0x00000006U) +#define NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_2 (0x00000007U) +#define NV2080_CTRL_FB_IS_KIND_OPERATION_ZBC_ALLOWS_4 (0x00000008U) /** * NV2080_CTRL_CMD_FB_GET_GPU_CACHE_INFO @@ -927,7 +926,7 @@ typedef struct NV2080_CTRL_FB_IS_KIND_PARAMS { * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_INFO (0x20801315) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_INFO (0x20801315U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS_MESSAGE_ID (0x15U) @@ -939,19 +938,19 @@ typedef struct NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS { } NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS; /* valid values for powerState */ -#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE_ENABLED (0x00000000) -#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE_DISABLED (0x00000001) +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE_ENABLED (0x00000000U) +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE_DISABLED (0x00000001U) /* valid values for writeMode */ -#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE_WRITETHROUGH (0x00000000) -#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE_WRITEBACK (0x00000001) +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE_WRITETHROUGH (0x00000000U) +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE_WRITEBACK (0x00000001U) /* valid values for bypassMode */ -#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE_DISABLED (0x00000000) -#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE_ENABLED (0x00000001) +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE_DISABLED (0x00000000U) +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE_ENABLED (0x00000001U) /* valid values for rcmState */ -#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_FULL (0x00000000) -#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_TRANSITIONING (0x00000001) -#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_REDUCED (0x00000002) -#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_ZERO_CACHE (0x00000003) +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_FULL (0x00000000U) +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_TRANSITIONING (0x00000001U) +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_REDUCED (0x00000002U) +#define NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_ZERO_CACHE (0x00000003U) /* * NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY @@ -979,10 +978,10 @@ typedef struct NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_PARAMS { } NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_PARAMS; /* valid values for promotionPolicy */ -#define NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_NONE (0x00000000) -#define NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_QUARTER (0x00000001) -#define NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_HALF (0x00000002) -#define NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_FULL (0x00000003) +#define NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_NONE (0x00000000U) +#define NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_QUARTER (0x00000001U) +#define NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_HALF (0x00000002U) +#define NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_FULL (0x00000003U) /* @@ -996,7 +995,7 @@ typedef struct NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_PARAMS { * NV_ERR_NOT_SUPPORTED * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_PROMOTION_POLICY (0x20801316) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x16" */ // Deprecated, removed form RM +#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_PROMOTION_POLICY (0x20801316U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x16" */ // Deprecated, removed form RM /* @@ -1010,7 +1009,7 @@ typedef struct NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_PARAMS { * NV_ERR_NOT_SUPPORTED * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_PROMOTION_POLICY (0x20801317) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x17" */ // Deprecated, removed form RM +#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_PROMOTION_POLICY (0x20801317U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x17" */ // Deprecated, removed form RM /* * NV2080_CTRL_FB_CMD_GET_FB_REGION_INFO @@ -1054,9 +1053,9 @@ typedef struct NV2080_CTRL_FB_GPU_CACHE_PROMOTION_POLICY_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO (0x20801320) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO (0x20801320U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES 17 +#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES 17U typedef NvBool NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG[NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES]; @@ -1071,7 +1070,7 @@ typedef struct NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO { NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG blackList; } NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO; -#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES 16 +#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES 16U #define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_MESSAGE_ID (0x20U) @@ -1109,13 +1108,13 @@ typedef struct NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS { * NV_ERR_NOT_SUPPORTED * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_CMD_FB_OFFLINE_PAGES (0x20801321) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_OFFLINE_PAGES (0x20801321U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES (0x00000040) +#define NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES (0x00000040U) #define NV2080_CTRL_FB_OFFLINED_PAGES_INVALID_ADDRESS (0xffffffffffffffffULL) -#define NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_4K (0x00000000) -#define NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_64K (0x00000001) -#define NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_128K (0x00000002) +#define NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_4K (0x00000000U) +#define NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_64K (0x00000001U) +#define NV2080_CTRL_FB_OFFLINED_PAGES_PAGE_SIZE_128K (0x00000002U) /* * NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO @@ -1161,17 +1160,17 @@ typedef struct NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO { } NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO; /* valid values for source */ -#define NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_MULTIPLE_SBE (0x00000002) -#define NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_DBE (0x00000004) +#define NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_MULTIPLE_SBE (0x00000002U) +#define NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_DBE (0x00000004U) /* valid values for status */ -#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_OK (0x00000000) -#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_PENDING_RETIREMENT (0x00000001) -#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_BLACKLISTING_FAILED (0x00000002) -#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_TABLE_FULL (0x00000003) -#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_INTERNAL_ERROR (0x00000004) +#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_OK (0x00000000U) +#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_PENDING_RETIREMENT (0x00000001U) +#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_BLACKLISTING_FAILED (0x00000002U) +#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_TABLE_FULL (0x00000003U) +#define NV2080_CTRL_FB_OFFLINED_PAGES_STATUS_INTERNAL_ERROR (0x00000004U) /* deprecated */ #define NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_MULTIPLE_SBE NV2080_CTRL_FB_OFFLINED_PAGES_SOURCE_DPR_MULTIPLE_SBE @@ -1222,14 +1221,14 @@ typedef struct NV2080_CTRL_FB_OFFLINE_PAGES_PARAMS { -#define NV2080_CTRL_CMD_FB_GET_OFFLINED_PAGES (0x20801322) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_GET_OFFLINED_PAGES (0x20801322U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE 0:0 -#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE_FALSE 0 -#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE_TRUE 1 +#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE_FALSE 0U +#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_SBE_TRUE 1U #define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE 1:1 -#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE_FALSE 0 -#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE_TRUE 1 +#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE_FALSE 0U +#define NV2080_CTRL_FB_GET_OFFLINED_PAGES_RETIREMENT_PENDING_DBE_TRUE 1U @@ -1280,13 +1279,13 @@ typedef struct NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_FB_QUERY_ACR_REGION (0x20801325) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_QUERY_ACR_REGION (0x20801325U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS_MESSAGE_ID" */ // // We can create an ACR region by using RMCreateAcrRegion[1|2] regkey or mods -acr[1|2]_size // Client ID for such region is 2 in RM. // -#define NV2080_CTRL_CMD_FB_ACR_CLIENT_ID 2 +#define NV2080_CTRL_CMD_FB_ACR_CLIENT_ID 2U typedef enum NV2080_CTRL_CMD_FB_ACR_QUERY_TYPE { NV2080_CTRL_CMD_FB_ACR_QUERY_GET_CLIENT_REGION_STATUS = 0, @@ -1360,7 +1359,7 @@ typedef struct NV2080_CTRL_CMD_FB_QUERY_ACR_REGION_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_FB_CLEAR_OFFLINED_PAGES (0x20801326) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_CLEAR_OFFLINED_PAGES (0x20801326U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS_MESSAGE_ID (0x26U) @@ -1385,7 +1384,7 @@ typedef struct NV2080_CTRL_FB_CLEAR_OFFLINED_PAGES_PARAMS { * Possible status values returned are: * NV_OK NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO (0x20801327) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO (0x20801327U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS_MESSAGE_ID (0x27U) @@ -1414,7 +1413,7 @@ typedef struct NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_INFO_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_FB_GET_LTC_INFO_FOR_FBP (0x20801328) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_GET_LTC_INFO_FOR_FBP (0x20801328U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_MESSAGE_ID (0x28U) @@ -1459,7 +1458,7 @@ typedef struct NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT (0x20801329) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x29" */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT (0x20801329U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x29" */ typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS { NvU32 CBCBaseAddress; @@ -1496,7 +1495,7 @@ typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_CONTEXT_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTEDD */ -#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS (0x2080132a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2A" */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS (0x2080132aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2A" */ typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS { NV_DECLARE_ALIGNED(NvU32 *fcbits, 8); @@ -1531,7 +1530,7 @@ typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITS_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS (0x2080132b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2B" */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS (0x2080132bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2B" */ typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS { NvU32 fcbits; @@ -1563,7 +1562,7 @@ typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITS_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB (0x2080132c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2C" */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB (0x2080132cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2C" */ typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS { NV_DECLARE_ALIGNED(NvU64 SrcDataPhysicalStart, 8); @@ -1593,7 +1592,7 @@ typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPBITS64KB_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB (0x2080132d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2D" */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB (0x2080132dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2D" */ typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS { NV_DECLARE_ALIGNED(NvU64 DstDataPhysicalStart, 8); @@ -1634,7 +1633,7 @@ typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITSPS (0x2080132e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2E" */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITSPS (0x2080132eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2E" */ typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITSPS_PARAMS { NV_DECLARE_ALIGNED(NvU32 *fcbits, 8); @@ -1680,7 +1679,7 @@ typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITSPS_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITSPS (0x2080132f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2F" */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITSPS (0x2080132fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2F" */ typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITSPS_PARAMS { NvU32 fcbits; @@ -1714,7 +1713,7 @@ typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITSPS_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPCACHELINEPS (0x20801330) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x30" */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPCACHELINEPS (0x20801330U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x30" */ typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPCACHELINEPS_PARAMS { NV_DECLARE_ALIGNED(NvU32 *compCacheLine, 8); @@ -1742,7 +1741,7 @@ typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPCACHELINEPS_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPCACHELINEPS (0x20801331) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x31" */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPCACHELINEPS (0x20801331U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x31" */ typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPCACHELINEPS_PARAMS { NV_DECLARE_ALIGNED(NvU32 *compCacheLine, 8); @@ -1768,7 +1767,7 @@ typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPCACHELINEPS_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPCACHELINE_BOUNDS (0x20801332) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x32" */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPCACHELINE_BOUNDS (0x20801332U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x32" */ typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPCACHELINE_BOUNDS_PARAMS { NV_DECLARE_ALIGNED(NvU64 *minCPUAddress, 8); @@ -1799,7 +1798,7 @@ typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPCACHELINE_BOUNDS_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_PART_SLICE_OFFSET (0x20801333) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x33" */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_PART_SLICE_OFFSET (0x20801333U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x33" */ typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_PART_SLICE_OFFSET_PARAMS { NV_DECLARE_ALIGNED(NvU64 *part, 8); @@ -1828,7 +1827,7 @@ typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_PART_SLICE_OFFSET_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_FB_COMPBITCOPY_ALLOC_AND_INIT_DERIVEDPARAMS (0x20801334) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x34" */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_ALLOC_AND_INIT_DERIVEDPARAMS (0x20801334U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x34" */ typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_ALLOC_AND_INIT_DERIVEDPARAMS_PARAMS { NV_DECLARE_ALIGNED(NvP64 derivedParams, 8); @@ -1849,7 +1848,7 @@ typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_ALLOC_AND_INIT_DERIVEDPARAMS_PARAM * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1 (0x20801335) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x35" */ +#define NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1 (0x20801335U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x35" */ typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS { NvBool bForceBar1; @@ -1874,7 +1873,7 @@ typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1_PARAMS { * @CbcSwizzleParamsV1. However, the caller is responsible for making sure * all parameters are filled in before using it. */ -#define NV2080_CTRL_CMD_FB_GET_AMAP_CONF (0x20801336) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_GET_AMAP_CONF (0x20801336U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS_MESSAGE_ID (0x36U) @@ -1897,7 +1896,7 @@ typedef struct NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS { * Possible status values returned are: * NV_OK NV_ERR_NOT_SUPPORTED NV_ERR_INVALID_ARGUMENT NV_ERR_TIMEOUT */ -#define NV2080_CTRL_CMD_FB_CBC_OP (0x20801337) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_CBC_OP_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_CBC_OP (0x20801337U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_CBC_OP_PARAMS_MESSAGE_ID" */ /*! * Permitted CBC Operations @@ -1933,13 +1932,13 @@ typedef struct NV2080_CTRL_CMD_FB_CBC_OP_PARAMS { * NV_ERR_OUT_OF_RANGE * NV_ERR_INVALID_PARAMETER */ -#define NV2080_CTRL_CMD_FB_GET_CTAGS_FOR_CBC_EVICTION (0x20801338) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_GET_CTAGS_FOR_CBC_EVICTION (0x20801338U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS_MESSAGE_ID" */ /*! * Max size of @ref NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS::pCompTags * Arbitrary, but sufficiently large number. Should be checked against CBC size. */ -#define NV2080_MAX_CTAGS_FOR_CBC_EVICTION 0x7F +#define NV2080_MAX_CTAGS_FOR_CBC_EVICTION 0x7FU #define NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS_MESSAGE_ID (0x38U) @@ -1978,7 +1977,7 @@ typedef struct NV2080_CTRL_FB_GET_CTAGS_FOR_CBC_EVICTION_PARAMS { * NV_ERR_INVALID_STATE */ -#define NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE (0x20801339) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE (0x20801339U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS_MESSAGE_ID (0x39U) @@ -2005,7 +2004,7 @@ typedef struct NV2080_CTRL_CMD_FB_ALLOC_COMP_RESOURCE_PARAMS { * NV_ERR_INVALID_STATE */ -#define NV2080_CTRL_CMD_FB_FREE_TILE (0x2080133a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_FREE_TILE (0x2080133aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS_MESSAGE_ID (0x3AU) @@ -2039,7 +2038,7 @@ typedef struct NV2080_CTRL_CMD_FB_FREE_TILE_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_FB_SETUP_VPR_REGION (0x2080133b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_SETUP_VPR_REGION (0x2080133bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS_MESSAGE_ID" */ typedef enum NV2080_CTRL_CMD_FB_VPR_REQUEST_TYPE { NV2080_CTRL_CMD_FB_SET_VPR = 0, @@ -2087,7 +2086,7 @@ typedef struct NV2080_CTRL_CMD_FB_SETUP_VPR_REGION_PARAMS *PNV2080_CTRL_CMD_FB_S * Possible status values returned are: * NV_OK */ -#define NV2080_CTRL_CMD_FB_GET_CLI_MANAGED_OFFLINED_PAGES (0x2080133c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_GET_CLI_MANAGED_OFFLINED_PAGES (0x2080133cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS_MESSAGE_ID (0x3CU) @@ -2138,7 +2137,7 @@ typedef struct NV2080_CTRL_FB_GET_CLI_MANAGED_OFFLINED_PAGES_PARAMS { * NV_OK */ -#define NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO (0x2080133d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO (0x2080133dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS_MESSAGE_ID (0x3DU) @@ -2168,7 +2167,7 @@ typedef struct NV2080_CTRL_CMD_FB_GET_COMPBITCOPY_CONSTRUCT_INFO_PARAMS { * NV_OK * Any error code */ -#define NV2080_CTRL_CMD_FB_SET_RRD (0x2080133e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_RRD_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_SET_RRD (0x2080133eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_RRD_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_FB_SET_RRD_RESET_VALUE (~((NvU32)0)) #define NV2080_CTRL_FB_SET_RRD_PARAMS_MESSAGE_ID (0x3EU) @@ -2186,7 +2185,7 @@ typedef struct NV2080_CTRL_FB_SET_RRD_PARAMS { typedef struct NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS { NvU8 limit; } NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS; -#define NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE (0xff) +#define NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE (0xffU) /* * NV2080_CTRL_CMD_FB_SET_READ_LIMIT @@ -2200,7 +2199,7 @@ typedef struct NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS { * NV_OK * Any error code */ -#define NV2080_CTRL_CMD_FB_SET_READ_LIMIT (0x2080133f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_SET_READ_LIMIT (0x2080133fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_FB_SET_READ_LIMIT_RESET_VALUE NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE #define NV2080_CTRL_FB_SET_READ_LIMIT_PARAMS_MESSAGE_ID (0x3FU) @@ -2219,7 +2218,7 @@ typedef NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS NV2080_CTRL_FB_SET_READ_LIMIT * NV_OK * Any error code */ -#define NV2080_CTRL_CMD_FB_SET_WRITE_LIMIT (0x20801340) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_SET_WRITE_LIMIT (0x20801340U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_FB_SET_WRITE_LIMIT_RESET_VALUE NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_RESET_VALUE #define NV2080_CTRL_FB_SET_WRITE_LIMIT_PARAMS_MESSAGE_ID (0x40U) @@ -2238,7 +2237,7 @@ typedef NV2080_CTRL_FB_SET_READ_WRITE_LIMIT_PARAMS NV2080_CTRL_FB_SET_WRITE_LIMI * NV_OK * Any error code */ -#define NV2080_CTRL_CMD_FB_PATCH_PBR_FOR_MINING (0x20801341) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_PATCH_PBR_FOR_MINING (0x20801341U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS_MESSAGE_ID (0x41U) @@ -2251,9 +2250,9 @@ typedef struct NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS { * * Get memory alignment. Replacement for NVOS32_FUNCTION_GET_MEM_ALIGNMENT */ -#define NV2080_CTRL_CMD_FB_GET_MEM_ALIGNMENT (0x20801342) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_GET_MEM_ALIGNMENT (0x20801342U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_FB_GET_MEM_ALIGNMENT_MAX_BANKS (4) +#define NV2080_CTRL_FB_GET_MEM_ALIGNMENT_MAX_BANKS (4U) #define NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS_MESSAGE_ID (0x42U) typedef struct NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS { @@ -2289,7 +2288,7 @@ typedef struct NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS { * NV_OK NV_ERR_NOT_SUPPORTED * */ -#define NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR (0x20801343) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR (0x20801343U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS_MESSAGE_ID (0x43U) @@ -2302,8 +2301,8 @@ typedef struct NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS { } NV2080_CTRL_CMD_FB_GET_CBC_BASE_ADDR_PARAMS; #define NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING 0:0 -#define NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_FALSE 0 -#define NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_TRUE 1 +#define NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_FALSE 0U +#define NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_TRUE 1U @@ -2319,10 +2318,10 @@ typedef struct NV2080_CTRL_FB_REMAP_ENTRY { /* valid values for source */ -#define NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_SBE_FIELD (0x00000002) -#define NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_DBE_FIELD (0x00000003) +#define NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_SBE_FIELD (0x00000002U) +#define NV2080_CTRL_FB_REMAPPED_ROW_SOURCE_DBE_FIELD (0x00000003U) -#define NV2080_CTRL_FB_REMAPPED_ROWS_MAX_ROWS (0x00000200) +#define NV2080_CTRL_FB_REMAPPED_ROWS_MAX_ROWS (0x00000200U) /* * NV2080_CTRL_CMD_FB_GET_REMAPPED_ROWS @@ -2346,15 +2345,15 @@ typedef struct NV2080_CTRL_FB_REMAP_ENTRY { * NV_ERR_OBJECT_NOT_FOUND * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_FB_GET_REMAPPED_ROWS (0x20801344) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_GET_REMAPPED_ROWS (0x20801344U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING \ NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING #define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING_FALSE NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_FALSE #define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_PENDING_TRUE NV2080_CTRL_FB_REMAP_ENTRY_FLAGS_PENDING_TRUE #define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE 1:1 -#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE_FALSE 0 -#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE_TRUE 1 +#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE_FALSE 0U +#define NV2080_CTRL_FB_GET_REMAPPED_ROWS_FLAGS_FAILURE_TRUE 1U #define NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS_MESSAGE_ID (0x44U) @@ -2365,7 +2364,7 @@ typedef struct NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS { } NV2080_CTRL_FB_GET_REMAPPED_ROWS_PARAMS; // Max size of the queryParams in Bytes, so that the NV2080_CTRL_FB_FS_INFO_QUERY struct is still 32B -#define NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE 24 +#define NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE 24U /*! * Structure holding the out params for NV2080_CTRL_FB_FS_INFO_INVALID_QUERY. @@ -2579,19 +2578,19 @@ typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS { } NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS; // Possible values for queryType -#define NV2080_CTRL_FB_FS_INFO_INVALID_QUERY 0x0 -#define NV2080_CTRL_FB_FS_INFO_FBP_MASK 0x1 -#define NV2080_CTRL_FB_FS_INFO_LTC_MASK 0x2 -#define NV2080_CTRL_FB_FS_INFO_LTS_MASK 0x3 -#define NV2080_CTRL_FB_FS_INFO_FBPA_MASK 0x4 -#define NV2080_CTRL_FB_FS_INFO_ROP_MASK 0x5 -#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK 0x6 -#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK 0x7 -#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK 0x8 -#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK 0x9 -#define NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK 0xA -#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK 0xB -#define NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP 0xC +#define NV2080_CTRL_FB_FS_INFO_INVALID_QUERY 0x0U +#define NV2080_CTRL_FB_FS_INFO_FBP_MASK 0x1U +#define NV2080_CTRL_FB_FS_INFO_LTC_MASK 0x2U +#define NV2080_CTRL_FB_FS_INFO_LTS_MASK 0x3U +#define NV2080_CTRL_FB_FS_INFO_FBPA_MASK 0x4U +#define NV2080_CTRL_FB_FS_INFO_ROP_MASK 0x5U +#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK 0x6U +#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK 0x7U +#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK 0x8U +#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK 0x9U +#define NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK 0xAU +#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK 0xBU +#define NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP 0xCU typedef struct NV2080_CTRL_FB_FS_INFO_QUERY { NvU16 queryType; @@ -2615,7 +2614,7 @@ typedef struct NV2080_CTRL_FB_FS_INFO_QUERY { } NV2080_CTRL_FB_FS_INFO_QUERY; // Max number of queries that can be batched in a single call to NV2080_CTRL_CMD_FB_GET_FS_INFO -#define NV2080_CTRL_FB_FS_INFO_MAX_QUERIES 96 +#define NV2080_CTRL_FB_FS_INFO_MAX_QUERIES 96U #define NV2080_CTRL_FB_GET_FS_INFO_PARAMS_MESSAGE_ID (0x46U) @@ -2641,13 +2640,13 @@ typedef struct NV2080_CTRL_FB_GET_FS_INFO_PARAMS { * NV_ERR_INVALID_ARGUMENT * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_FB_GET_FS_INFO (0x20801346) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_FS_INFO_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_GET_FS_INFO (0x20801346U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_FS_INFO_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_FB_HISTOGRAM_IDX_NO_REMAPPED_ROWS (0x0) -#define NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAPPED_ROW (0x1) -#define NV2080_CTRL_FB_HISTOGRAM_IDX_MIXED_REMAPPED_REMAINING_ROWS (0x2) -#define NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAINING_ROW (0x3) -#define NV2080_CTRL_FB_HISTOGRAM_IDX_MAX_REMAPPED_ROWS (0x4) +#define NV2080_CTRL_FB_HISTOGRAM_IDX_NO_REMAPPED_ROWS (0x0U) +#define NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAPPED_ROW (0x1U) +#define NV2080_CTRL_FB_HISTOGRAM_IDX_MIXED_REMAPPED_REMAINING_ROWS (0x2U) +#define NV2080_CTRL_FB_HISTOGRAM_IDX_SINGLE_REMAINING_ROW (0x3U) +#define NV2080_CTRL_FB_HISTOGRAM_IDX_MAX_REMAPPED_ROWS (0x4U) #define NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS_MESSAGE_ID (0x47U) @@ -2680,7 +2679,7 @@ typedef struct NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_FB_GET_ROW_REMAPPER_HISTOGRAM (0x20801347) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_GET_ROW_REMAPPER_HISTOGRAM (0x20801347U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS_MESSAGE_ID" */ /* * NV2080_CTRL_CMD_FB_GET_DYNAMICALLY_BLACKLISTED_PAGES @@ -2707,16 +2706,16 @@ typedef struct NV2080_CTRL_FB_GET_ROW_REMAPPER_HISTOGRAM_PARAMS { * Possible status values returned are: * NV_OK */ -#define NV2080_CTRL_CMD_FB_GET_DYNAMIC_OFFLINED_PAGES (0x20801348) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_GET_DYNAMIC_OFFLINED_PAGES (0x20801348U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS_MESSAGE_ID" */ /* Maximum pages that can be dynamically blacklisted */ -#define NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_PAGES 512 +#define NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_PAGES 512U /* * Maximum entries that can be sent in a single pass of * NV2080_CTRL_CMD_FB_GET_DYNAMIC_OFFLINED_PAGES */ -#define NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES 64 +#define NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES 64U /** * NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO @@ -2747,8 +2746,8 @@ typedef struct NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS { /* valid values for source */ -#define NV2080_CTRL_FB_DYNAMIC_BLACKLISTED_PAGES_SOURCE_INVALID (0x00000000) -#define NV2080_CTRL_FB_DYNAMIC_BLACKLISTED_PAGES_SOURCE_DPR_DBE (0x00000001) +#define NV2080_CTRL_FB_DYNAMIC_BLACKLISTED_PAGES_SOURCE_INVALID (0x00000000U) +#define NV2080_CTRL_FB_DYNAMIC_BLACKLISTED_PAGES_SOURCE_DPR_DBE (0x00000001U) /* * NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO @@ -2794,7 +2793,7 @@ typedef struct NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS { * reached or client is out of memory. */ -#define NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO (0x20801349) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO (0x20801349U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS_MESSAGE_ID" */ /* * These work with the FLD_SET_REF_NUM and FLD_TEST_REF macros and describe the 'flags' member @@ -2803,18 +2802,18 @@ typedef struct NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS { // Address space of the allocation #define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE 4:0 -#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE_SYSMEM 0 -#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE_VIDMEM 1 +#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE_SYSMEM 0U +#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_TYPE_VIDMEM 1U // Whether the allocation is shared #define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED 5:5 -#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED_FALSE 0 -#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED_TRUE 1 +#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED_FALSE 0U +#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_SHARED_TRUE 1U // Whether this client owns this allocation #define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER 6:6 -#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER_FALSE 0 -#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER_TRUE 1 +#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER_FALSE 0U +#define NV2080_CTRL_CMD_FB_ALLOCATION_FLAGS_OWNER_TRUE 1U typedef struct NV2080_CTRL_CMD_FB_ALLOCATION_INFO { NvU32 client; /* [OUT] Identifies the client that made or shares the allocation (index into pClientInfo)*/ @@ -2853,7 +2852,7 @@ typedef struct NV2080_CTRL_CMD_FB_GET_CLIENT_ALLOCATION_INFO_PARAMS { * NV_ERR_INVALID_STATE * */ -#define NV2080_CTRL_CMD_FB_UPDATE_NUMA_STATUS (0x20801350) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_UPDATE_NUMA_STATUS (0x20801350U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS_MESSAGE_ID (0x50U) @@ -2890,9 +2889,9 @@ typedef struct NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS { * NV_OK * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_CMD_FB_GET_NUMA_INFO (0x20801351) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_GET_NUMA_INFO (0x20801351U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_FB_NUMA_INFO_MAX_OFFLINE_ADDRESSES 64 +#define NV2080_CTRL_FB_NUMA_INFO_MAX_OFFLINE_ADDRESSES 64U #define NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS_MESSAGE_ID (0x51U) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h index b7dcf078b..b8341aa47 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h @@ -474,7 +474,7 @@ typedef struct NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS { * NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE * * This command retrieves entries from the SW encoded GPU device info table - * from Host RM. + * from Host RM. * * Parameters: * @@ -517,7 +517,7 @@ typedef struct NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS { * pbdmaFaultIds * List of pbdma fault ids associated with engine * numPbdmas - * Number of pbdmas + * Number of pbdmas * engineName * Name of the engine */ @@ -643,8 +643,8 @@ typedef struct NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS { * description for more details. * - NV2080_CTRL_FIFO_RUNLIST_SCHED_POLICY_CHANNEL_INTERLEAVED_WDDM * This scheduling policy will make channels to be scheduled according - * to their interleave level per WDDM policy. - * See NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL description for more details. + * to their interleave level per WDDM policy. + * See NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL description for more details. * * Possible status values returned are: * NV_OK @@ -734,10 +734,10 @@ typedef struct NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS { * * When a VF subcontext is marked as a zombie, host RM points its PDB to a dummy * page allocated by guest RM in GPA space. This command provides the parameters - * of the guest RMs memory descriptor to be able to create a corresponding + * of the guest RMs memory descriptor to be able to create a corresponding * memory descriptor on the host RM. Host RM uses this to program the PDB of a * zombie subcontext. - * + * * Parameters: * Input parameters to describe the memory descriptor * [in] base @@ -756,4 +756,36 @@ typedef struct NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS { NvU32 cacheAttrib; } NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS; +/* + * NV2080_CTRL_CMD_FIFO_GET_ALLOCATED_CHANNELS + * + * Get's a bitmask of allocated channels. No guarantees are made about + * synchronization. A channel returned as allocated by this ctrl cmd might have + * already been destructed. + * + * Parameters: + * [in] runlistId + * [in,out] bitMask A 1 bit indicates that a channel with this index/id is + * allocated. This field is a multiple of 32 bits and each 32 + * bit group must be accessed as a platform 32 bit int to + * correctly map channel IDs. + * + */ +#define NV2080_CTRL_CMD_FIFO_GET_ALLOCATED_CHANNELS (0x20801119) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS_MESSAGE_ID" */ + +/* + * The maximum number than can be returned by + * NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS + */ +#define NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_MAX_CHANNELS 4096 + +#define NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS_MESSAGE_ID (0x19U) + +typedef struct NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS { + NvU32 runlistId; + NvU32 bitMask[NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_MAX_CHANNELS / 32]; +} NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS; + + + /* _ctrl2080fifo_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fla.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fla.h index 7040d33f4..3fe89b949 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fla.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fla.h @@ -34,8 +34,6 @@ /* NV20_SUBDEVICE_XX FLA control commands and parameters */ -#include "ctrl2080common.h" - /* * NV2080_CTRL_CMD_FLA_RANGE * diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h index 37810dcf1..474f91622 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h @@ -80,22 +80,44 @@ typedef struct NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS { * @defgroup NVOS_INST_EVT Instrumentation event types. * @{ */ + +//! Reserved for uStreamer internal use. #define NV2080_CTRL_FLCN_NVOS_INST_EVT_RSVD_DO_NOT_USE 0x00U + +//! RTOS CTXSW includes next taskID and number of ODP for previous task. #define NV2080_CTRL_FLCN_NVOS_INST_EVT_CTXSW_END 0x01U + +//! Begin of a HW IRQ. #define NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_BEGIN 0x02U + +//! End of a HW IRQ, before stack pinning etc is performed. #define NV2080_CTRL_FLCN_NVOS_INST_EVT_HW_IRQ_END 0x03U + +//! RTOS Timer tick slip. (Only for # tick processed > 1). #define NV2080_CTRL_FLCN_NVOS_INST_EVT_TIMER_TICK 0x04U + +//! Task start processing an event, includes taskId, eventType and unitId (optional). #define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_BEGIN 0x05U + +//! Task finished processing an event, incldues taskId. #define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_END 0x06U + +//! Latency for inserting response into RM queue. #define NV2080_CTRL_FLCN_NVOS_INST_EVT_RM_QUEUE_LATENCY 0x07U + +//! Special / multi-purpose event, see field definition below. #define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_SPECIAL_EVENT 0x08U -#define NV2080_CTRL_FLCN_NVOS_INST_EVT_DMA_BEGIN 0x09U + +//! Unused, recycle +#define NV2080_CTRL_FLCN_NVOS_INST_EVT_UNUSED_0 0x09U + #define NV2080_CTRL_FLCN_NVOS_INST_EVT_DMA_END 0x0AU //! Begin/end for arbitrary block of code. The payload contains a sub-ID for each location profiled. #define NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_BEGIN 0x0BU #define NV2080_CTRL_FLCN_NVOS_INST_EVT_GENERIC_END 0x0CU +//! Queueing time for the most recent event. #define NV2080_CTRL_FLCN_NVOS_INST_EVT_TASK_EVENT_LATENCY 0x0DU /*!@}*/ @@ -191,6 +213,7 @@ typedef struct NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS { #define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_BEGIN_EVENT_TYPE 23:16 #define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_TASK_ID 7:0 +#define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_CALLBACK_ID 15:8 #define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_RPC_FUNC 15:8 #define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_RPC_FUNC_BOBJ_CMD_BASE 0xF0 #define NV2080_CTRL_FLCN_USTREAMER_EVENT_TAIL_PAYLOADCOMPACT_TASK_EVENT_END_CLASS_ID 23:16 diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h index f87471dd9..82dcb30f0 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h @@ -33,6 +33,22 @@ #include "ctrl/ctrl2080/ctrl2080gr.h" #include "ctrl/ctrl0000/ctrl0000system.h" #include "nvcfg_sdk.h" +#include "nvstatus.h" + +#define NV_GRID_LICENSE_INFO_MAX_LENGTH (128) + +/* License info strings for vGPU products */ +#define NV_GRID_LICENSE_FEATURE_VPC_EDITION "GRID-Virtual-PC,2.0;Quadro-Virtual-DWS,5.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0" +#define NV_GRID_LICENSE_FEATURE_VAPPS_EDITION "GRID-Virtual-Apps,3.0" +#define NV_GRID_LICENSE_FEATURE_VIRTUAL_WORKSTATION_EDITION "Quadro-Virtual-DWS,5.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0" +#define NV_GRID_LICENSE_FEATURE_GAMING_EDITION "GRID-vGaming,8.0" +#define NV_GRID_LICENSE_FEATURE_COMPUTE_EDITION "NVIDIA-vComputeServer,9.0;Quadro-Virtual-DWS,5.0" + +#define NV_GRID_LICENSED_PRODUCT_VWS "NVIDIA RTX Virtual Workstation" +#define NV_GRID_LICENSED_PRODUCT_GAMING "NVIDIA Cloud Gaming" +#define NV_GRID_LICENSED_PRODUCT_VPC "NVIDIA Virtual PC" +#define NV_GRID_LICENSED_PRODUCT_VAPPS "NVIDIA Virtual Applications" +#define NV_GRID_LICENSED_PRODUCT_COMPUTE "NVIDIA Virtual Compute Server" @@ -40,8 +56,8 @@ /* Valid feature values */ #define NV2080_CTRL_GPU_GET_FEATURES_CLK_ARCH_DOMAINS 0:0 -#define NV2080_CTRL_GPU_GET_FEATURES_CLK_ARCH_DOMAINS_FALSE (0x00000000) -#define NV2080_CTRL_GPU_GET_FEATURES_CLK_ARCH_DOMAINS_TRUE (0x00000001) +#define NV2080_CTRL_GPU_GET_FEATURES_CLK_ARCH_DOMAINS_FALSE (0x00000000U) +#define NV2080_CTRL_GPU_GET_FEATURES_CLK_ARCH_DOMAINS_TRUE (0x00000001U) @@ -54,144 +70,144 @@ typedef struct NV2080_CTRL_GPU_INFO { -#define NV2080_CTRL_GPU_INFO_INDEX_MINOR_REVISION_EXT (0x00000004) +#define NV2080_CTRL_GPU_INFO_INDEX_MINOR_REVISION_EXT (0x00000004U) -#define NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV0 (0x00000012) -#define NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV1 (0x00000013) +#define NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV0 (0x00000012U) +#define NV2080_CTRL_GPU_INFO_INDEX_NETLIST_REV1 (0x00000013U) -#define NV2080_CTRL_GPU_INFO_INDEX_SYSMEM_ACCESS (0x0000001f) +#define NV2080_CTRL_GPU_INFO_INDEX_SYSMEM_ACCESS (0x0000001fU) -#define NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD (0x00000022) +#define NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD (0x00000022U) -#define NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE (0x00000025) -#define NV2080_CTRL_GPU_INFO_INDEX_IBMNPU_RELAXED_ORDERING (0x00000026) -#define NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED (0x00000027) -#define NV2080_CTRL_GPU_INFO_INDEX_NVSWITCH_PROXY_DETECTED (0x00000028) -#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT (0x00000029) -#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SMC_MODE (0x0000002a) -#define NV2080_CTRL_GPU_INFO_INDEX_SPLIT_VAS_MGMT_SERVER_CLIENT_RM (0x0000002b) -#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SM_VERSION (0x0000002c) -#define NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY (0x0000002d) +#define NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE (0x00000025U) +#define NV2080_CTRL_GPU_INFO_INDEX_IBMNPU_RELAXED_ORDERING (0x00000026U) +#define NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED (0x00000027U) +#define NV2080_CTRL_GPU_INFO_INDEX_NVSWITCH_PROXY_DETECTED (0x00000028U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT (0x00000029U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SMC_MODE (0x0000002aU) +#define NV2080_CTRL_GPU_INFO_INDEX_SPLIT_VAS_MGMT_SERVER_CLIENT_RM (0x0000002bU) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SM_VERSION (0x0000002cU) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY (0x0000002dU) -#define NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM (0x0000002f) -#define NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY (0x00000030) -#define NV2080_CTRL_GPU_INFO_INDEX_NVENC_STATS_REPORTING_STATE (0x00000031) +#define NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM (0x0000002fU) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY (0x00000030U) +#define NV2080_CTRL_GPU_INFO_INDEX_NVENC_STATS_REPORTING_STATE (0x00000031U) -#define NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED (0x00000033) -#define NV2080_CTRL_GPU_INFO_INDEX_DISPLAY_ENABLED (0x00000034) -#define NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED (0x00000035) -#define NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY (0x00000036) -#define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY (0x00000037) +#define NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED (0x00000033U) +#define NV2080_CTRL_GPU_INFO_INDEX_DISPLAY_ENABLED (0x00000034U) +#define NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED (0x00000035U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY (0x00000036U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY (0x00000037U) -#define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU (0x0000003c) -#define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY (0x0000003d) -#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x0000003e) +#define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU (0x0000003cU) +#define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY (0x0000003dU) +#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x0000003eU) /* valid minor revision extended values */ -#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_NONE (0x00000000) -#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_P (0x00000001) -#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_V (0x00000002) -#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_PV (0x00000003) +#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_NONE (0x00000000U) +#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_P (0x00000001U) +#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_V (0x00000002U) +#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_PV (0x00000003U) /* valid system memory access capability values */ -#define NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_NO (0x00000000) -#define NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_YES (0x00000001) +#define NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_SYSMEM_ACCESS_YES (0x00000001U) /* valid gemini board values */ -#define NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_NO (0x00000000) -#define NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_YES (0x00000001) +#define NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GEMINI_BOARD_YES (0x00000001U) /* valid surprise removal values */ -#define NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_NO (0x00000000) -#define NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_YES (0x00000001) +#define NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_YES (0x00000001U) /* valid relaxed ordering values */ -#define NV2080_CTRL_GPU_INFO_IBMNPU_RELAXED_ORDERING_DISABLED (0x00000000) -#define NV2080_CTRL_GPU_INFO_IBMNPU_RELAXED_ORDERING_ENABLED (0x00000001) -#define NV2080_CTRL_GPU_INFO_IBMNPU_RELAXED_ORDERING_UNSUPPORTED (0xFFFFFFFF) +#define NV2080_CTRL_GPU_INFO_IBMNPU_RELAXED_ORDERING_DISABLED (0x00000000U) +#define NV2080_CTRL_GPU_INFO_IBMNPU_RELAXED_ORDERING_ENABLED (0x00000001U) +#define NV2080_CTRL_GPU_INFO_IBMNPU_RELAXED_ORDERING_UNSUPPORTED (0xFFFFFFFFU) /* valid poison fuse capability values */ -#define NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_NO (0x00000000) -#define NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_YES (0x00000001) +#define NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_YES (0x00000001U) /* valid nvswitch proxy detected values */ -#define NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_NO (0x00000000) -#define NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_YES (0x00000001) +#define NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_NVSWITCH_PROXY_DETECTED_YES (0x00000001U) /* valid NVSR GPU support info values */ -#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_NO (0x00000000) -#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_YES (0x00000001) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT_YES (0x00000001U) /* valid SMC mode values */ -#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_UNSUPPORTED (0x00000000) -#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLED (0x00000001) -#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLED (0x00000002) -#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLE_PENDING (0x00000003) -#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLE_PENDING (0x00000004) +#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_UNSUPPORTED (0x00000000U) +#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLED (0x00000001U) +#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLED (0x00000002U) +#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLE_PENDING (0x00000003U) +#define NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLE_PENDING (0x00000004U) /* valid split VAS mode values */ -#define NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_NO (0x00000000) -#define NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_YES (0x00000001) +#define NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_SPLIT_VAS_MGMT_SERVER_CLIENT_RM_YES (0x00000001U) /* valid grid capability values */ -#define NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_NO (0x00000000) -#define NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_YES (0x00000001) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_FLA_CAPABILITY_YES (0x00000001U) /* valid per runlist channel ram capability values */ -#define NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_DISABLED (0x00000000) -#define NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_ENABLED (0x00000001) +#define NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_DISABLED (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_PER_RUNLIST_CHANNEL_RAM_ENABLED (0x00000001U) /* valid ATS capability values */ -#define NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_NO (0x00000000) -#define NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_YES (0x00000001) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_ATS_CAPABILITY_YES (0x00000001U) /* valid Nvenc Session Stats reporting state values */ -#define NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_DISABLED (0x00000000) -#define NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_ENABLED (0x00000001) -#define NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_NOT_SUPPORTED (0x00000002) +#define NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_DISABLED (0x00000000U) +#define NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_ENABLED (0x00000001U) +#define NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_NOT_SUPPORTED (0x00000002U) /* valid 4K PAGE isolation requirement values */ -#define NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED_NO (0x00000000) -#define NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED_YES (0x00000001) +#define NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED_YES (0x00000001U) /* valid display enabled values */ -#define NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_NO (0x00000000) -#define NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_YES (0x00000001) +#define NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_YES (0x00000001U) /* valid mobile config enabled values */ -#define NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_NO (0x00000000) -#define NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_YES (0x00000001) +#define NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED_YES (0x00000001U) /* valid profiling capability values */ -#define NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_DISABLED (0x00000000) -#define NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_ENABLED (0x00000001) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_DISABLED (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_ENABLED (0x00000001U) /* valid debugging capability values */ -#define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_DISABLED (0x00000000) -#define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_ENABLED (0x00000001) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_DISABLED (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_ENABLED (0x00000001U) /* valid CMP (Crypto Mining Processor) SKU values */ -#define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_NO (0x00000000) -#define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_YES (0x00000001) +#define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_YES (0x00000001U) /* valid dma-buf suport values */ -#define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_NO (0x00000000) -#define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_YES (0x00000001) +#define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_NO (0x00000000U) +#define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_YES (0x00000001U) /* * NV2080_CTRL_CMD_GPU_GET_INFO @@ -216,7 +232,7 @@ typedef struct NV2080_CTRL_GPU_INFO { * NV_ERR_NOT_SUPPORTED * NV_ERR_OPERATING_SYSTEM */ -#define NV2080_CTRL_CMD_GPU_GET_INFO (0x20800101) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFO_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_INFO (0x20800101U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFO_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_GET_INFO_PARAMS_MESSAGE_ID (0x1U) @@ -225,7 +241,7 @@ typedef struct NV2080_CTRL_GPU_GET_INFO_PARAMS { NV_DECLARE_ALIGNED(NvP64 gpuInfoList, 8); } NV2080_CTRL_GPU_GET_INFO_PARAMS; -#define NV2080_CTRL_CMD_GPU_GET_INFO_V2 (0x20800102) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x2" */ +#define NV2080_CTRL_CMD_GPU_GET_INFO_V2 (0x20800102U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x2" */ typedef struct NV2080_CTRL_GPU_GET_INFO_V2_PARAMS { NvU32 gpuInfoListSize; @@ -256,17 +272,17 @@ typedef struct NV2080_CTRL_GPU_GET_INFO_V2_PARAMS { * NV_ERR_INVALID_ARGUMENT * NV_ERR_OPERATING_SYSTEM */ -#define NV2080_CTRL_CMD_GPU_GET_NAME_STRING (0x20800110) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_NAME_STRING (0x20800110U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_MESSAGE_ID" */ -#define NV2080_GPU_MAX_NAME_STRING_LENGTH (0x0000040) +#define NV2080_GPU_MAX_NAME_STRING_LENGTH (0x0000040U) // This field is deprecated - 'gpuNameStringFlags' is now a simple scalar. // Field maintained (and extended from 0:0) for compile-time compatibility. #define NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE 31:0 /* valid gpu name string flags */ -#define NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_ASCII (0x00000000) -#define NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_UNICODE (0x00000001) +#define NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_ASCII (0x00000000U) +#define NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_UNICODE (0x00000001U) #define NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS_MESSAGE_ID (0x10U) @@ -294,7 +310,7 @@ typedef struct NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS { * NV_ERR_INVALID_ARGUMENT * NV_ERR_OPERATING_SYSTEM */ -#define NV2080_CTRL_CMD_GPU_GET_SHORT_NAME_STRING (0x20800111) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_SHORT_NAME_STRING (0x20800111U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS_MESSAGE_ID (0x11U) @@ -324,7 +340,7 @@ typedef struct NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS { * NV_OK * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_CMD_GPU_SET_POWER (0x20800112) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_POWER_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_SET_POWER (0x20800112U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_POWER_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_SET_POWER_PARAMS_MESSAGE_ID (0x12U) @@ -336,6 +352,13 @@ typedef struct NV2080_CTRL_GPU_SET_POWER_PARAMS { +#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_0 (0x00000000U) +#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_1 (0x00000001U) +#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_2 (0x00000002U) +#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_3 (0x00000003U) +#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_4 (0x00000004U) +#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_7 (0x00000007U) + /* * NV2080_CTRL_CMD_GPU_GET_SDM * @@ -350,7 +373,7 @@ typedef struct NV2080_CTRL_GPU_SET_POWER_PARAMS { * NV_OK * NV_ERR_INVALID_PARAM_STRUCT */ -#define NV2080_CTRL_CMD_GPU_GET_SDM (0x20800118) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_SDM_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_SDM (0x20800118U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_SDM_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_GET_SDM_PARAMS_MESSAGE_ID (0x18U) @@ -376,7 +399,7 @@ typedef struct NV2080_CTRL_GPU_GET_SDM_PARAMS { * NV_ERR_INVALID_DATA * NV_ERR_INVALID_PARAM_STRUCT */ -#define NV2080_CTRL_CMD_GPU_SET_SDM (0x20800120) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_SDM_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_SET_SDM (0x20800120U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_SDM_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_SET_SDM_PARAMS_MESSAGE_ID (0x20U) @@ -397,7 +420,7 @@ typedef struct NV2080_CTRL_GPU_SET_SDM_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO (0x20800119) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO (0x20800119U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS_MESSAGE_ID (0x19U) @@ -405,17 +428,17 @@ typedef struct NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS { NvU32 type; } NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS; -#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_NONE (0x00000000) -#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_MODS_AMODEL (0x00000001) -#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_LIVE_AMODEL (0x00000002) -#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_FMODEL (0x00000003) -#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_RTL (0x00000004) -#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU (0x00000005) -#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU_LOW_POWER (0x00000006) -#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA (0x00000007) -#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_RTL (0x00000008) -#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_FMODEL (0x00000009) -#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_UNKNOWN (0xFFFFFFFF) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_NONE (0x00000000U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_MODS_AMODEL (0x00000001U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_LIVE_AMODEL (0x00000002U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_FMODEL (0x00000003U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_RTL (0x00000004U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU (0x00000005U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_EMU_LOW_POWER (0x00000006U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA (0x00000007U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_RTL (0x00000008U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_DFPGA_FMODEL (0x00000009U) +#define NV2080_CTRL_GPU_GET_SIMULATION_INFO_TYPE_UNKNOWN (0xFFFFFFFFU) /* * NV2080_CTRL_GPU_REG_OP @@ -590,32 +613,32 @@ typedef struct NV2080_CTRL_GPU_REG_OP { } NV2080_CTRL_GPU_REG_OP; /* valid regOp values */ -#define NV2080_CTRL_GPU_REG_OP_READ_32 (0x00000000) -#define NV2080_CTRL_GPU_REG_OP_WRITE_32 (0x00000001) -#define NV2080_CTRL_GPU_REG_OP_READ_64 (0x00000002) -#define NV2080_CTRL_GPU_REG_OP_WRITE_64 (0x00000003) -#define NV2080_CTRL_GPU_REG_OP_READ_08 (0x00000004) -#define NV2080_CTRL_GPU_REG_OP_WRITE_08 (0x00000005) +#define NV2080_CTRL_GPU_REG_OP_READ_32 (0x00000000U) +#define NV2080_CTRL_GPU_REG_OP_WRITE_32 (0x00000001U) +#define NV2080_CTRL_GPU_REG_OP_READ_64 (0x00000002U) +#define NV2080_CTRL_GPU_REG_OP_WRITE_64 (0x00000003U) +#define NV2080_CTRL_GPU_REG_OP_READ_08 (0x00000004U) +#define NV2080_CTRL_GPU_REG_OP_WRITE_08 (0x00000005U) /* valid regType values */ -#define NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL (0x00000000) -#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX (0x00000001) -#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC (0x00000002) -#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_SM (0x00000004) -#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_CROP (0x00000008) -#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_ZROP (0x00000010) -#define NV2080_CTRL_GPU_REG_OP_TYPE_FB (0x00000020) -#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_QUAD (0x00000040) -#define NV2080_CTRL_GPU_REG_OP_TYPE_DEVICE (0x00000080) +#define NV2080_CTRL_GPU_REG_OP_TYPE_GLOBAL (0x00000000U) +#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX (0x00000001U) +#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_TPC (0x00000002U) +#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_SM (0x00000004U) +#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_CROP (0x00000008U) +#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_ZROP (0x00000010U) +#define NV2080_CTRL_GPU_REG_OP_TYPE_FB (0x00000020U) +#define NV2080_CTRL_GPU_REG_OP_TYPE_GR_CTX_QUAD (0x00000040U) +#define NV2080_CTRL_GPU_REG_OP_TYPE_DEVICE (0x00000080U) /* valid regStatus values (note: NvU8 ie, 1 byte) */ -#define NV2080_CTRL_GPU_REG_OP_STATUS_SUCCESS (0x00) -#define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OP (0x01) -#define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_TYPE (0x02) -#define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OFFSET (0x04) -#define NV2080_CTRL_GPU_REG_OP_STATUS_UNSUPPORTED_OP (0x08) -#define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_MASK (0x10) -#define NV2080_CTRL_GPU_REG_OP_STATUS_NOACCESS (0x20) +#define NV2080_CTRL_GPU_REG_OP_STATUS_SUCCESS (0x00U) +#define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OP (0x01U) +#define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_TYPE (0x02U) +#define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_OFFSET (0x04U) +#define NV2080_CTRL_GPU_REG_OP_STATUS_UNSUPPORTED_OP (0x08U) +#define NV2080_CTRL_GPU_REG_OP_STATUS_INVALID_MASK (0x10U) +#define NV2080_CTRL_GPU_REG_OP_STATUS_NOACCESS (0x20U) /* * NV2080_CTRL_CMD_GPU_EXEC_REG_OPS @@ -664,7 +687,7 @@ typedef struct NV2080_CTRL_GPU_REG_OP { * NV_ERR_INVALID_ARGUMENT * NV_ERR_INVALID_PARAM_STRUCT */ -#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS (0x20800122) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x22" */ +#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS (0x20800122U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x22" */ typedef struct NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS { NvHandle hClientTarget; @@ -693,7 +716,7 @@ typedef struct NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS { * Possible status values returned are: * NV_OK */ -#define NV2080_CTRL_CMD_GPU_GET_ENGINES (0x20800123) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINES_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_ENGINES (0x20800123U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINES_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_GET_ENGINES_PARAMS_MESSAGE_ID (0x23U) @@ -702,10 +725,10 @@ typedef struct NV2080_CTRL_GPU_GET_ENGINES_PARAMS { NV_DECLARE_ALIGNED(NvP64 engineList, 8); } NV2080_CTRL_GPU_GET_ENGINES_PARAMS; -#define NV2080_CTRL_CMD_GPU_GET_ENGINES_V2 (0x20800170) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_ENGINES_V2 (0x20800170U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID" */ /* Must match NV2080_ENGINE_TYPE_LAST from cl2080.h */ -#define NV2080_GPU_MAX_ENGINES_LIST_SIZE 0x34 +#define NV2080_GPU_MAX_ENGINES_LIST_SIZE 0x3EU #define NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID (0x70U) @@ -737,7 +760,7 @@ typedef struct NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS { * NV_ERR_INVALID_ARGUMENT * NV_ERR_INVALID_PARAM_STRUCT */ -#define NV2080_CTRL_CMD_GPU_GET_ENGINE_CLASSLIST (0x20800124) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_ENGINE_CLASSLIST (0x20800124U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS_MESSAGE_ID (0x24U) @@ -777,7 +800,7 @@ typedef struct NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS { * NV_ERR_INVALID_ARGUMENT * NV_ERR_INVALID_PARAM_STRUCT */ -#define NV2080_CTRL_CMD_GPU_GET_ENGINE_FAULT_INFO (0x20800125) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_ENGINE_FAULT_INFO (0x20800125U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS_MESSAGE_ID (0x25U) @@ -808,12 +831,12 @@ typedef struct NV2080_CTRL_GPU_GET_ENGINE_FAULT_INFO_PARAMS { * Possible status values returned are: * NV_OK */ -#define NV2080_CTRL_CMD_GPU_QUERY_MODE (0x20800128) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_MODE_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_QUERY_MODE (0x20800128U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_MODE_PARAMS_MESSAGE_ID" */ /* valid mode parameter values */ -#define NV2080_CTRL_GPU_QUERY_MODE_UNKNOWN_MODE (0x00000000) -#define NV2080_CTRL_GPU_QUERY_MODE_GRAPHICS_MODE (0x00000001) -#define NV2080_CTRL_GPU_QUERY_MODE_COMPUTE_MODE (0x00000002) +#define NV2080_CTRL_GPU_QUERY_MODE_UNKNOWN_MODE (0x00000000U) +#define NV2080_CTRL_GPU_QUERY_MODE_GRAPHICS_MODE (0x00000001U) +#define NV2080_CTRL_GPU_QUERY_MODE_COMPUTE_MODE (0x00000002U) #define NV2080_CTRL_GPU_QUERY_MODE_PARAMS_MESSAGE_ID (0x28U) @@ -859,21 +882,21 @@ typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY { NvU8 bNonmapped; } NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY; -#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_MAIN 0 -#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PM 1 -#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PATCH 2 -#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_BUFFER_BUNDLE_CB 3 -#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PAGEPOOL 4 -#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_ATTRIBUTE_CB 5 -#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_RTV_CB_GLOBAL 6 -#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_POOL 7 -#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_CTRL_BLK 8 -#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_FECS_EVENT 9 -#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PRIV_ACCESS_MAP 10 -#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_UNRESTRICTED_PRIV_ACCESS_MAP 11 -#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GLOBAL_PRIV_ACCESS_MAP 12 +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_MAIN 0U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PM 1U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PATCH 2U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_BUFFER_BUNDLE_CB 3U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PAGEPOOL 4U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_ATTRIBUTE_CB 5U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_RTV_CB_GLOBAL 6U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_POOL 7U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_CTRL_BLK 8U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_FECS_EVENT 9U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PRIV_ACCESS_MAP 10U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_UNRESTRICTED_PRIV_ACCESS_MAP 11U +#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GLOBAL_PRIV_ACCESS_MAP 12U -#define NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES 16 +#define NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES 16U /* * NV2080_CTRL_CMD_GPU_PROMOTE_CTX @@ -911,7 +934,7 @@ typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY { * NV_ERR_INVALID_DEVICE - The Class/Device is not yet ready to provide this info. * NV_ERR_INVALID_ARGUMENT - Bad/Unknown Class ID specified. */ -#define NV2080_CTRL_CMD_GPU_PROMOTE_CTX (0x2080012b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_PROMOTE_CTX (0x2080012bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_MESSAGE_ID (0x2BU) @@ -952,7 +975,7 @@ typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS *PNV2080_CTRL_GPU_PROMOTE_CTX_ * NV_ERR_INVALID_DEVICE - The Class/Device is not yet ready to provide this info. * NV_ERR_INVALID_ARGUMENT - Bad/Unknown Class ID specified. */ -#define NV2080_CTRL_CMD_GPU_EVICT_CTX (0x2080012c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EVICT_CTX_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_EVICT_CTX (0x2080012cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EVICT_CTX_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_EVICT_CTX_PARAMS_MESSAGE_ID (0x2CU) @@ -1003,7 +1026,7 @@ typedef struct NV2080_CTRL_GPU_EVICT_CTX_PARAMS *PNV2080_CTRL_GPU_EVICT_CTX_PARA * NV_ERR_INVALID_DEVICE - The Class/Device is not yet ready to provide this info. * NV_ERR_INVALID_ARGUMENT - Bad/Unknown Class ID specified. */ -#define NV2080_CTRL_CMD_GPU_INITIALIZE_CTX (0x2080012d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_INITIALIZE_CTX (0x2080012dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_MESSAGE_ID (0x2DU) @@ -1023,13 +1046,13 @@ typedef struct NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS { typedef struct NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS *PNV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS; #define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE 1:0 -#define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_VIDMEM (0x00000000) -#define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_COH_SYS (0x00000001) -#define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_NCOH_SYS (0x00000002) +#define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_VIDMEM (0x00000000U) +#define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_COH_SYS (0x00000001U) +#define NV2080_CTRL_GPU_INITIALIZE_CTX_APERTURE_NCOH_SYS (0x00000002U) #define NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE 2:2 -#define NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_YES (0x00000000) -#define NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_NO (0x00000001) +#define NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_YES (0x00000000U) +#define NV2080_CTRL_GPU_INITIALIZE_CTX_GPU_CACHEABLE_NO (0x00000001U) /* * NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX - Tells RM Whether this Ctx buffer needs to @@ -1040,15 +1063,15 @@ typedef struct NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS *PNV2080_CTRL_GPU_INITIALIZ */ #define NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX 3:3 -#define NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_NO (0x00000000) -#define NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_YES (0x00000001) +#define NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_NO (0x00000000U) +#define NV2080_CTRL_GPU_INITIALIZE_CTX_PRESERVE_CTX_YES (0x00000001U) /* * NV2080_CTRL_CMD_CPU_QUERY_ECC_INTR * Queries the top level ECC PMC PRI register * TODO remove these parameters, tracked in bug #1975721 */ -#define NV2080_CTRL_CMD_GPU_QUERY_ECC_INTR (0x2080012e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x2E" */ +#define NV2080_CTRL_CMD_GPU_QUERY_ECC_INTR (0x2080012eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x2E" */ typedef struct NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS { NvU32 eccIntrStatus; @@ -1075,21 +1098,21 @@ typedef struct NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS { -#define NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS (0x2080012f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS (0x2080012fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_GPU_ECC_UNIT_COUNT (0x00000018) +#define NV2080_CTRL_GPU_ECC_UNIT_COUNT (0x00000018U) // Deprecated do not use #define NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE 0:0 -#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_FILTERED (0x00000000) -#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_RAW (0x00000001) +#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_FILTERED (0x00000000U) +#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_FLAGS_TYPE_RAW (0x00000001U) -#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_FALSE 0 -#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_TRUE 1 -#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_INDETERMINATE 2 +#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_FALSE 0U +#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_TRUE 1U +#define NV2080_CTRL_GPU_QUERY_ECC_STATUS_UNC_ERR_INDETERMINATE 2U /* * NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS @@ -1229,13 +1252,13 @@ typedef struct NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS { * NV_ERR_INSUFFICIENT_PERMISSIONS (if the user is not the Administrator or superuser) * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_GPU_SET_COMPUTE_MODE_RULES (0x20800130) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_SET_COMPUTE_MODE_RULES (0x20800130U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID" */ /* valid rules parameter values */ -#define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_NONE (0x00000000) -#define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE (0x00000001) -#define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_COMPUTE_PROHIBITED (0x00000002) -#define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE_PROCESS (0x00000003) +#define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_NONE (0x00000000U) +#define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE (0x00000001U) +#define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_COMPUTE_PROHIBITED (0x00000002U) +#define NV2080_CTRL_GPU_COMPUTE_MODE_RULES_EXCLUSIVE_COMPUTE_PROCESS (0x00000003U) #define NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID (0x30U) @@ -1259,7 +1282,7 @@ typedef struct NV2080_CTRL_GPU_SET_COMPUTE_MODE_RULES_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_GPU_QUERY_COMPUTE_MODE_RULES (0x20800131) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_QUERY_COMPUTE_MODE_RULES (0x20800131U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS_MESSAGE_ID (0x31U) @@ -1289,10 +1312,10 @@ typedef struct NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS { * NV_ERR_NOT_SUPPORTED * NV_ERR_INVALID_STATE */ -#define NV2080_CTRL_CMD_GPU_QUERY_ECC_CONFIGURATION (0x20800133) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_QUERY_ECC_CONFIGURATION (0x20800133U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLED (0x00000000) -#define NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLED (0x00000001) +#define NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLED (0x00000000U) +#define NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLED (0x00000001U) #define NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS_MESSAGE_ID (0x33U) @@ -1318,10 +1341,10 @@ typedef struct NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS { * NV_ERR_INVALID_ARGUMENT * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_GPU_SET_ECC_CONFIGURATION (0x20800134) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_SET_ECC_CONFIGURATION (0x20800134U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLE (0x00000000) -#define NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLE (0x00000001) +#define NV2080_CTRL_GPU_ECC_CONFIGURATION_DISABLE (0x00000000U) +#define NV2080_CTRL_GPU_ECC_CONFIGURATION_ENABLE (0x00000001U) #define NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS_MESSAGE_ID (0x34U) @@ -1351,15 +1374,15 @@ typedef struct NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS { * NV_ERR_INVALID_ARGUMENT * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_GPU_RESET_ECC_ERROR_STATUS (0x20800136) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_RESET_ECC_ERROR_STATUS (0x20800136U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_GPU_ECC_ERROR_STATUS_NONE (0x00000000) -#define NV2080_CTRL_GPU_ECC_ERROR_STATUS_VOLATILE (0x00000001) -#define NV2080_CTRL_GPU_ECC_ERROR_STATUS_AGGREGATE (0x00000002) +#define NV2080_CTRL_GPU_ECC_ERROR_STATUS_NONE (0x00000000U) +#define NV2080_CTRL_GPU_ECC_ERROR_STATUS_VOLATILE (0x00000001U) +#define NV2080_CTRL_GPU_ECC_ERROR_STATUS_AGGREGATE (0x00000002U) #define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE 0:0 -#define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_FALSE 0 -#define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_TRUE 1 +#define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_FALSE 0U +#define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_FLAGS_FORCE_PURGE_TRUE 1U #define NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS_MESSAGE_ID (0x36U) @@ -1382,7 +1405,7 @@ typedef struct NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS { * NV_ERR_NOT_SUPPORTED * NV_ERR_INVALID_PARAM_STRUCT */ -#define NV2080_CTRL_CMD_GPU_GET_FERMI_GPC_INFO (0x20800137) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_FERMI_GPC_INFO (0x20800137U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS_MESSAGE_ID (0x37U) @@ -1410,7 +1433,7 @@ typedef struct NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS { * NV_ERR_NOT_SUPPORTED * NV_ERR_INVALID_PARAM_STRUCT */ -#define NV2080_CTRL_CMD_GPU_GET_FERMI_TPC_INFO (0x20800138) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_FERMI_TPC_INFO (0x20800138U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS_MESSAGE_ID (0x38U) @@ -1443,7 +1466,7 @@ typedef struct NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS { * NV2080_CTRL_CMD_GR_GET_ZCULL_MASK * */ -#define NV2080_CTRL_CMD_GPU_GET_FERMI_ZCULL_INFO (0x20800139) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_FERMI_ZCULL_INFO (0x20800139U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS_MESSAGE_ID (0x39U) @@ -1497,13 +1520,13 @@ typedef struct NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO (0x2080013f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO (0x2080013fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS_MESSAGE_ID" */ -#define NV2080_GPU_MAX_MARKETING_NAME_LENGTH (0x00000018) -#define NV2080_GPU_MAX_SERIAL_NUMBER_LENGTH (0x00000010) -#define NV2080_GPU_MAX_MEMORY_PART_ID_LENGTH (0x00000014) -#define NV2080_GPU_MAX_MEMORY_DATE_CODE_LENGTH (0x00000006) -#define NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH (0x00000014) +#define NV2080_GPU_MAX_MARKETING_NAME_LENGTH (0x00000018U) +#define NV2080_GPU_MAX_SERIAL_NUMBER_LENGTH (0x00000010U) +#define NV2080_GPU_MAX_MEMORY_PART_ID_LENGTH (0x00000014U) +#define NV2080_GPU_MAX_MEMORY_DATE_CODE_LENGTH (0x00000006U) +#define NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH (0x00000014U) #define NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS_MESSAGE_ID (0x3FU) @@ -1534,7 +1557,7 @@ typedef struct NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_GPU_GET_ID (0x20800142) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ID_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_ID (0x20800142U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ID_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_GET_ID_PARAMS_MESSAGE_ID (0x42U) @@ -1562,7 +1585,7 @@ typedef struct NV2080_CTRL_GPU_GET_ID_PARAMS { * NV_ERR_INVALID_ARGUMENT * */ -#define NV2080_CTRL_CMD_GPU_SET_GPU_DEBUG_MODE (0x20800143) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_SET_GPU_DEBUG_MODE (0x20800143U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID (0x43U) @@ -1570,8 +1593,8 @@ typedef struct NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS { NvU32 mode; } NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS; -#define NV2080_CTRL_GPU_DEBUG_MODE_ENABLED (0x00000001) -#define NV2080_CTRL_GPU_DEBUG_MODE_DISABLED (0x00000002) +#define NV2080_CTRL_GPU_DEBUG_MODE_ENABLED (0x00000001U) +#define NV2080_CTRL_GPU_DEBUG_MODE_DISABLED (0x00000002U) /* * NV2080_CTRL_CMD_GPU_GET_GPU_DEBUG_MODE @@ -1592,7 +1615,7 @@ typedef struct NV2080_CTRL_GPU_SET_GPU_DEBUG_MODE_PARAMS { * NV_ERR_INVALID_ARGUMENT * */ -#define NV2080_CTRL_CMD_GPU_GET_GPU_DEBUG_MODE (0x20800144) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_GPU_DEBUG_MODE (0x20800144U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS_MESSAGE_ID (0x44U) @@ -1641,10 +1664,10 @@ typedef struct NV2080_CTRL_GPU_GET_GPU_DEBUG_MODE_PARAMS { * NV_ERR_INVALID_PARAM_STRUCT */ -#define NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST (0x20800147) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST (0x20800147U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS_MESSAGE_ID" */ /* this macro specifies the maximum number of partner entries */ -#define NV2080_CTRL_GPU_MAX_ENGINE_PARTNERS (0x00000020) +#define NV2080_CTRL_GPU_MAX_ENGINE_PARTNERS (0x00000020U) #define NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS_MESSAGE_ID (0x47U) @@ -1696,10 +1719,13 @@ typedef struct NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS { * NV_ERR_NOT_SUPPORTED * NV_ERR_INVALID_STATE */ -#define NV2080_CTRL_CMD_GPU_GET_GID_INFO (0x2080014a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_GID_INFO (0x2080014aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_MESSAGE_ID" */ /* maximum possible number of bytes of GID information returned */ -#define NV2080_GPU_MAX_GID_LENGTH (0x000000100) +#define NV2080_GPU_MAX_GID_LENGTH (0x000000100ULL) + +/* maximum possible number of bytes of GID information returned if given the BINARY and SHA1 flags */ +#define NV2080_GPU_MAX_SHA1_BINARY_GID_LENGTH (0x000000010ULL) #define NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_MESSAGE_ID (0x4AU) @@ -1712,11 +1738,11 @@ typedef struct NV2080_CTRL_GPU_GET_GID_INFO_PARAMS { /* valid flags values */ #define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT 1:0 -#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_ASCII (0x00000000) -#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_BINARY (0x00000002) +#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_ASCII (0x00000000U) +#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_BINARY (0x00000002U) #define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_TYPE 2:2 -#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_TYPE_SHA1 (0x00000000) +#define NV2080_GPU_CMD_GPU_GET_GID_FLAGS_TYPE_SHA1 (0x00000000U) /* * NV2080_CTRL_CMD_GPU_GET_INFOROM_OBJECT_VERSION @@ -1743,9 +1769,9 @@ typedef struct NV2080_CTRL_GPU_GET_GID_INFO_PARAMS { * NV_ERR_NOT_SUPPORTED * */ -#define NV2080_CTRL_CMD_GPU_GET_INFOROM_OBJECT_VERSION (0x2080014b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_INFOROM_OBJECT_VERSION (0x2080014bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_GPU_INFOROM_OBJ_TYPE_LEN 3 +#define NV2080_CTRL_GPU_INFOROM_OBJ_TYPE_LEN 3U #define NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS_MESSAGE_ID (0x4BU) @@ -1767,7 +1793,7 @@ typedef struct NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS { * Possible status return values are: * NV_OK */ -#define NV2080_CTRL_CMD_SET_GPU_OPTIMUS_INFO (0x2080014c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_SET_GPU_OPTIMUS_INFO (0x2080014cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS_MESSAGE_ID (0x4CU) @@ -1794,7 +1820,7 @@ typedef struct NV2080_CTRL_GPU_OPTIMUS_INFO_PARAMS { * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_GPU_GET_IP_VERSION (0x2080014d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_IP_VERSION (0x2080014dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS_MESSAGE_ID (0x4DU) @@ -1803,11 +1829,11 @@ typedef struct NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS { NvU32 ipVersion; } NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS; -#define NV2080_CTRL_GPU_GET_IP_VERSION_DISPLAY (0x00000001) -#define NV2080_CTRL_GPU_GET_IP_VERSION_HDACODEC (0x00000002) -#define NV2080_CTRL_GPU_GET_IP_VERSION_PMGR (0x00000003) -#define NV2080_CTRL_GPU_GET_IP_VERSION_PPWR_PMU (0x00000004) -#define NV2080_CTRL_GPU_GET_IP_VERSION_DISP_FALCON (0x00000005) +#define NV2080_CTRL_GPU_GET_IP_VERSION_DISPLAY (0x00000001U) +#define NV2080_CTRL_GPU_GET_IP_VERSION_HDACODEC (0x00000002U) +#define NV2080_CTRL_GPU_GET_IP_VERSION_PMGR (0x00000003U) +#define NV2080_CTRL_GPU_GET_IP_VERSION_PPWR_PMU (0x00000004U) +#define NV2080_CTRL_GPU_GET_IP_VERSION_DISP_FALCON (0x00000005U) @@ -1821,9 +1847,9 @@ typedef struct NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_GPU_ILLUM_ATTRIB_LOGO_BRIGHTNESS 0 -#define NV2080_CTRL_GPU_ILLUM_ATTRIB_SLI_BRIGHTNESS 1 -#define NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT (0x20800153) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_GPU_ILLUM_ATTRIB_LOGO_BRIGHTNESS 0U +#define NV2080_CTRL_GPU_ILLUM_ATTRIB_SLI_BRIGHTNESS 1U +#define NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT (0x20800153U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS_MESSAGE_ID (0x53U) @@ -1841,7 +1867,7 @@ typedef struct NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_GPU_GET_ILLUM (0x20800154) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x54" */ +#define NV2080_CTRL_CMD_GPU_GET_ILLUM (0x20800154U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x54" */ typedef struct NV2080_CTRL_CMD_GPU_ILLUM_PARAMS { NvU32 attribute; @@ -1857,7 +1883,7 @@ typedef struct NV2080_CTRL_CMD_GPU_ILLUM_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_GPU_SET_ILLUM (0x20800155) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x55" */ +#define NV2080_CTRL_CMD_GPU_SET_ILLUM (0x20800155U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x55" */ /* * NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION @@ -1876,9 +1902,9 @@ typedef struct NV2080_CTRL_CMD_GPU_ILLUM_PARAMS { * NV_ERR_NOT_SUPPORTED * NV_ERR_INVALID_DATA */ -#define NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION (0x20800156) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION (0x20800156U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_GPU_INFOROM_IMAGE_VERSION_LEN 16 +#define NV2080_CTRL_GPU_INFOROM_IMAGE_VERSION_LEN 16U #define NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS_MESSAGE_ID (0x56U) @@ -1895,7 +1921,7 @@ typedef struct NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_GPU_QUERY_INFOROM_ECC_SUPPORT (0x20800157) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x57" */ +#define NV2080_CTRL_CMD_GPU_QUERY_INFOROM_ECC_SUPPORT (0x20800157U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x57" */ /* * NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION @@ -1947,9 +1973,9 @@ typedef struct NV2080_CTRL_GPU_PHYSICAL_BRIDGE_VERSION_PARAMS { * NV_ERR_INVALID_ARGUMENT * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO (0x2080015a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO (0x2080015aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_MAX_PHYSICAL_BRIDGE (100) +#define NV2080_CTRL_MAX_PHYSICAL_BRIDGE (100U) #define NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS_MESSAGE_ID (0x5AU) typedef struct NV2080_CTRL_GPU_GET_PHYSICAL_BRIDGE_VERSION_INFO_PARAMS { @@ -2021,7 +2047,7 @@ typedef struct NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS { * NV_ERR_INVALID_ARGUMENT * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU (0x2080015b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU (0x2080015bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS_MESSAGE_ID (0x5BU) @@ -2059,7 +2085,7 @@ typedef struct NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS { * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_GPU_QUERY_SCRUBBER_STATUS (0x2080015f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_QUERY_SCRUBBER_STATUS (0x2080015fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS_MESSAGE_ID (0x5FU) @@ -2071,8 +2097,8 @@ typedef struct NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS { } NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS; /* valid values for scrubber status */ -#define NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_RUNNING (0x00000000) -#define NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_IDLE (0x00000001) +#define NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_RUNNING (0x00000000U) +#define NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_IDLE (0x00000001U) /* * NV2080_CTRL_CMD_GPU_GET_VPR_CAPS @@ -2092,7 +2118,7 @@ typedef struct NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS { * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_GPU_GET_VPR_CAPS (0x20800160) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_VPR_CAPS (0x20800160U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS_MESSAGE_ID (0x60U) @@ -2111,7 +2137,7 @@ typedef struct NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS { * Possible status values returned are: * NVOS_STATUS_SUCCESS */ -#define NV2080_CTRL_CMD_GPU_HANDLE_GPU_SR (0x20800167) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x67" */ +#define NV2080_CTRL_CMD_GPU_HANDLE_GPU_SR (0x20800167U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x67" */ /* @@ -2145,9 +2171,9 @@ typedef struct NV2080_CTRL_GPU_GET_VPR_CAPS_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_GPU_GET_PES_INFO (0x20800168) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PES_INFO_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_PES_INFO (0x20800168U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PES_INFO_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_CMD_GPU_GET_PES_INFO_MAX_TPC_PER_GPC_COUNT 10 +#define NV2080_CTRL_CMD_GPU_GET_PES_INFO_MAX_TPC_PER_GPC_COUNT 10U #define NV2080_CTRL_GPU_GET_PES_INFO_PARAMS_MESSAGE_ID (0x68U) @@ -2175,9 +2201,9 @@ typedef struct NV2080_CTRL_GPU_GET_PES_INFO_PARAMS { * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_GPU_GET_OEM_INFO (0x20800169) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_OEM_INFO (0x20800169U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS_MESSAGE_ID" */ -#define NV2080_GPU_MAX_OEM_INFO_LENGTH (0x000001F8) +#define NV2080_GPU_MAX_OEM_INFO_LENGTH (0x000001F8U) #define NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS_MESSAGE_ID (0x69U) @@ -2193,7 +2219,7 @@ typedef struct NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS { * NV_OK * NV_ERR_NOT_READY */ -#define NV2080_CTRL_CMD_GPU_PROCESS_POST_GC6_EXIT_TASKS (0x2080016a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x6A" */ +#define NV2080_CTRL_CMD_GPU_PROCESS_POST_GC6_EXIT_TASKS (0x2080016aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x6A" */ /* * NV2080_CTRL_CMD_GPU_GET_VPR_INFO @@ -2227,7 +2253,7 @@ typedef struct NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_GPU_GET_VPR_INFO (0x2080016b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_VPR_INFO (0x2080016bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS_MESSAGE_ID" */ typedef enum NV2080_CTRL_VPR_INFO_QUERY_TYPE { @@ -2266,7 +2292,7 @@ typedef struct NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS { * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_CMD_GPU_GET_ENCODER_CAPACITY (0x2080016c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_ENCODER_CAPACITY (0x2080016cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS_MESSAGE_ID" */ typedef enum NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE { NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264 = 0, @@ -2299,7 +2325,7 @@ typedef struct NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS { * NV_OK * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS (0x2080016d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS (0x2080016dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS_MESSAGE_ID (0x6DU) @@ -2309,7 +2335,7 @@ typedef struct NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS { NvU32 averageEncodeLatency; } NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS; -#define NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES 0x200 // 512 entries. +#define NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES 0x200U // 512 entries. /* * NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO @@ -2359,7 +2385,7 @@ typedef struct NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS { NV_DECLARE_ALIGNED(NvP64 sessionInfoTbl, 8); } NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS; -#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO (0x2080016e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO (0x2080016eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS_MESSAGE_ID" */ /* * NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR @@ -2394,7 +2420,7 @@ typedef struct NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS { NV_DECLARE_ALIGNED(NvU64 fabricBaseAddr, 8); } NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS; -#define NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR (0x2080016f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR (0x2080016fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID" */ /* * NV2080_CTRL_CMD_GPU_VIRTUAL_INTERRUPT @@ -2416,7 +2442,7 @@ typedef struct NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS { NvU32 handle; } NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS; -#define NV2080_CTRL_CMD_GPU_VIRTUAL_INTERRUPT (0x20800172) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_VIRTUAL_INTERRUPT (0x20800172U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_VIRTUAL_INTERRUPT_PARAMS_MESSAGE_ID" */ /* * NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS @@ -2446,7 +2472,7 @@ typedef struct NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS { NvU32 ppcData; } NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS; -#define NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS (0x20800173) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS (0x20800173U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_QUERY_FUNCTION_STATUS_PARAMS_MESSAGE_ID" */ /* * NV2080_CTRL_GPU_PARTITION_SPAN @@ -2522,42 +2548,36 @@ typedef struct NV2080_CTRL_GPU_SET_PARTITION_INFO { } NV2080_CTRL_GPU_SET_PARTITION_INFO; #define PARTITIONID_INVALID NV2080_CTRL_GPU_PARTITION_ID_INVALID -#define NV2080_CTRL_GPU_PARTITION_ID_INVALID 0xFFFFFFFF -#define NV2080_CTRL_GPU_MAX_PARTITIONS 0x00000008 -#define NV2080_CTRL_GPU_MAX_PARTITION_IDS 0x00000009 -#define NV2080_CTRL_GPU_MAX_SMC_IDS 0x00000008 -#define NV2080_CTRL_GPU_MAX_GPC_PER_SMC 0x0000000c -#define NV2080_CTRL_GPU_MAX_CE_PER_SMC 0x00000008 +#define NV2080_CTRL_GPU_PARTITION_ID_INVALID 0xFFFFFFFFU +#define NV2080_CTRL_GPU_MAX_PARTITIONS 0x00000008U +#define NV2080_CTRL_GPU_MAX_PARTITION_IDS 0x00000009U +#define NV2080_CTRL_GPU_MAX_SMC_IDS 0x00000008U +#define NV2080_CTRL_GPU_MAX_GPC_PER_SMC 0x0000000cU +#define NV2080_CTRL_GPU_MAX_CE_PER_SMC 0x00000008U #define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE 1:0 -#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL 0x00000000 -#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_HALF 0x00000001 -#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_QUARTER 0x00000002 -#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_EIGHTH 0x00000003 -#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE__SIZE 4 +#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL 0x00000000U +#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_HALF 0x00000001U +#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_QUARTER 0x00000002U +#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_EIGHTH 0x00000003U +#define NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE__SIZE 4U #define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE 4:2 -#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL 0x00000000 -#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF 0x00000001 -#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF 0x00000002 -#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER 0x00000003 -#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_QUARTER 0x00000004 -#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH 0x00000005 -#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE 6 -#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE 7:5 -#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_FULL 0x00000001 -#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_HALF 0x00000002 -#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_MINI_HALF 0x00000003 -#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_QUARTER 0x00000004 -#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_EIGHTH 0x00000005 -#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_NONE 0x00000000 -#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE__SIZE 6 -#define NV2080_CTRL_GPU_PARTITION_MAX_TYPES 8 +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL 0x00000000U +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF 0x00000001U +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF 0x00000002U +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER 0x00000003U +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_QUARTER 0x00000004U +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH 0x00000005U +#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE 6U + + +#define NV2080_CTRL_GPU_PARTITION_MAX_TYPES 8U #define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA 30:30 -#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_DISABLE 0 -#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_ENABLE 1 +#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_DISABLE 0U +#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_ENABLE 1U #define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN 31:31 -#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_DISABLE 0 -#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_ENABLE 1 +#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_DISABLE 0U +#define NV2080_CTRL_GPU_PARTITION_FLAG_PLACE_AT_SPAN_ENABLE 1U // TODO XXX Bug 2657907 Remove these once clients update #define NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _FULL) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _FULL)) @@ -2573,7 +2593,7 @@ typedef struct NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS { NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_SET_PARTITION_INFO partitionInfo[NV2080_CTRL_GPU_MAX_PARTITIONS], 8); } NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS; -#define NV2080_CTRL_CMD_GPU_SET_PARTITIONS (0x20800174) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_SET_PARTITIONS (0x20800174U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS_MESSAGE_ID" */ /* * NV2080_CTRL_GPU_GET_PARTITION_INFO @@ -2649,6 +2669,9 @@ typedef struct NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS { * - NV_TRUE if partition had poison error which requires drain and reset * else NV_FALSE. * + * validCTSIdMask[OUT] + * - Mask of CTS IDs usable by this partition, not reflecting current allocations + * * Possible status values returned are: * NV_OK * NV_ERR_INVALID_ARGUMENT @@ -2677,6 +2700,7 @@ typedef struct NV2080_CTRL_GPU_GET_PARTITION_INFO { NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN span, 8); NvBool bValid; NvBool bPartitionError; + NV_DECLARE_ALIGNED(NvU64 validCTSIdMask, 8); } NV2080_CTRL_GPU_GET_PARTITION_INFO; /* @@ -2702,7 +2726,7 @@ typedef struct NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS { NvBool bGetAllPartitionInfo; } NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS; -#define NV2080_CTRL_CMD_GPU_GET_PARTITIONS (0x20800175) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_PARTITIONS (0x20800175U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS_MESSAGE_ID" */ /* * NV2080_CTRL_GPU_CONFIGURE_PARTITION @@ -2741,7 +2765,7 @@ typedef struct NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS { * NV_ERR_NOT_SUPPORTED * NV_ERR_STATE_IN_USE */ -#define NV2080_CTRL_CMD_GPU_CONFIGURE_PARTITION (0x20800176) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_CONFIGURE_PARTITION (0x20800176U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS_MESSAGE_ID (0x76U) @@ -2759,7 +2783,7 @@ typedef struct NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS { * This struct represents a GMMU fault packet. * */ -#define NV2080_CTRL_GPU_FAULT_PACKET_SIZE 32 +#define NV2080_CTRL_GPU_FAULT_PACKET_SIZE 32U typedef struct NV2080_CTRL_GPU_FAULT_PACKET { NvU8 data[NV2080_CTRL_GPU_FAULT_PACKET_SIZE]; } NV2080_CTRL_GPU_FAULT_PACKET; @@ -2777,7 +2801,7 @@ typedef struct NV2080_CTRL_GPU_FAULT_PACKET { * NV_OK * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_CMD_GPU_REPORT_NON_REPLAYABLE_FAULT (0x20800177) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_REPORT_NON_REPLAYABLE_FAULT (0x20800177U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS_MESSAGE_ID (0x77U) @@ -2795,7 +2819,7 @@ typedef struct NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS { * See confluence page "vGPU UMED Security" for details. * */ -#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_VGPU (0x20800178) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x78" */ +#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_VGPU (0x20800178U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x78" */ /* * NV2080_CTRL_CMD_GPU_GET_ENGINE_RUNLIST_PRI_BASE @@ -2819,7 +2843,7 @@ typedef struct NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS { * NV_ERR_INVALID_ARGUMENT * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_GPU_GET_ENGINE_RUNLIST_PRI_BASE (0x20800179) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_ENGINE_RUNLIST_PRI_BASE (0x20800179U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS_MESSAGE_ID (0x79U) @@ -2828,8 +2852,8 @@ typedef struct NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS { NvU32 runlistPriBase[NV2080_GPU_MAX_ENGINES_LIST_SIZE]; } NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS; -#define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_NULL (0xFFFFFFFF) -#define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_ERROR (0xFFFFFFFB) +#define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_NULL (0xFFFFFFFFU) +#define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_ERROR (0xFFFFFFFBU) /* * NV2080_CTRL_CMD_GPU_GET_HW_ENGINE_ID @@ -2853,7 +2877,7 @@ typedef struct NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS { * NV_ERR_INVALID_ARGUMENT * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_GPU_GET_HW_ENGINE_ID (0x2080017a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_HW_ENGINE_ID (0x2080017aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS_MESSAGE_ID (0x7AU) @@ -2862,8 +2886,8 @@ typedef struct NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS { NvU32 hwEngineID[NV2080_GPU_MAX_ENGINES_LIST_SIZE]; } NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS; -#define NV2080_CTRL_GPU_GET_HW_ENGINE_ID_NULL (0xFFFFFFFF) -#define NV2080_CTRL_GPU_GET_HW_ENGINE_ID_ERROR (0xFFFFFFFB) +#define NV2080_CTRL_GPU_GET_HW_ENGINE_ID_NULL (0xFFFFFFFFU) +#define NV2080_CTRL_GPU_GET_HW_ENGINE_ID_ERROR (0xFFFFFFFBU) /* * NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS @@ -2884,7 +2908,7 @@ typedef struct NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS { * NV_OK * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS (0x2080017b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS (0x2080017bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS_MESSAGE_ID (0x7BU) @@ -2929,11 +2953,11 @@ typedef struct NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS { * Average frame capture latency in microseconds. */ -#define NV2080_CTRL_NVFBC_SESSION_FLAG_DIFFMAP_ENABLED 0x00000001 -#define NV2080_CTRL_NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED 0x00000002 -#define NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_NO_WAIT 0x00000004 -#define NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_INFINITE 0x00000008 -#define NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_TIMEOUT 0x00000010 +#define NV2080_CTRL_NVFBC_SESSION_FLAG_DIFFMAP_ENABLED 0x00000001U +#define NV2080_CTRL_NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED 0x00000002U +#define NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_NO_WAIT 0x00000004U +#define NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_INFINITE 0x00000008U +#define NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_TIMEOUT 0x00000010U typedef struct NV2080_CTRL_NVFBC_SW_SESSION_INFO { NvU32 processId; @@ -2973,7 +2997,7 @@ typedef struct NV2080_CTRL_NVFBC_SW_SESSION_INFO { * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_GPU_NVFBC_MAX_SESSION_COUNT 256 +#define NV2080_GPU_NVFBC_MAX_SESSION_COUNT 256U #define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS_MESSAGE_ID (0x7CU) @@ -2982,7 +3006,7 @@ typedef struct NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS { NV2080_CTRL_NVFBC_SW_SESSION_INFO sessionInfoTbl[NV2080_GPU_NVFBC_MAX_SESSION_COUNT]; } NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS; -#define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO (0x2080017c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO (0x2080017cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS_MESSAGE_ID" */ @@ -2999,7 +3023,7 @@ typedef struct NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_GPU_GET_VMMU_SEGMENT_SIZE (0x2080017e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_VMMU_SEGMENT_SIZE (0x2080017eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS_MESSAGE_ID (0x7EU) @@ -3007,11 +3031,11 @@ typedef struct NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS { NV_DECLARE_ALIGNED(NvU64 vmmuSegmentSize, 8); } NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS; -#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_32MB 0x02000000 -#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_64MB 0x04000000 -#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_128MB 0x08000000 -#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_256MB 0x10000000 -#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_512MB 0x20000000 +#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_32MB 0x02000000U +#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_64MB 0x04000000U +#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_128MB 0x08000000U +#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_256MB 0x10000000U +#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_512MB 0x20000000U @@ -3059,7 +3083,7 @@ typedef struct NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS { * NV_ERR_INVALID_ARGUMENT * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_GPU_GET_PARTITION_CAPACITY (0x20800181) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_PARTITION_CAPACITY (0x20800181U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS_MESSAGE_ID (0x81U) @@ -3098,7 +3122,7 @@ typedef struct NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS { * NV_ERR_NOT_SUPPORTED * NV_ERR_OPERATING_SYSTEM */ -#define NV2080_CTRL_CMD_GPU_GET_CACHED_INFO (0x20800182) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x82" */ +#define NV2080_CTRL_CMD_GPU_GET_CACHED_INFO (0x20800182U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x82" */ typedef struct NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS { NvU32 gpuInfoListSize; @@ -3155,12 +3179,12 @@ typedef struct NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS { * NV_ERR_INVALID_ARGUMENT * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_GPU_SET_PARTITIONING_MODE (0x20800183) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_SET_PARTITIONING_MODE (0x20800183U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING 1:0 -#define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_LEGACY 0 -#define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_MAX_PERF 1 -#define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_FAST_RECONFIG 2 +#define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_LEGACY 0U +#define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_MAX_PERF 1U +#define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_FAST_RECONFIG 2U #define NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID (0x83U) @@ -3258,7 +3282,7 @@ typedef struct NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS { NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO partitionDescs[NV2080_CTRL_GPU_PARTITION_MAX_TYPES], 8); } NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS; -#define NV2080_CTRL_CMD_GPU_DESCRIBE_PARTITIONS (0x20800185) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_DESCRIBE_PARTITIONS (0x20800185U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS_MESSAGE_ID" */ @@ -3276,7 +3300,7 @@ typedef struct NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_GPU_GET_MAX_SUPPORTED_PAGE_SIZE (0x20800188) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_MAX_SUPPORTED_PAGE_SIZE (0x20800188U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS_MESSAGE_ID (0x88U) @@ -3308,7 +3332,7 @@ typedef struct NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS { NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); } NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS; -#define NV2080_CTRL_CMD_GPU_GET_NUM_MMUS_PER_GPC (0x2080018a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_NUM_MMUS_PER_GPC (0x2080018aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NUM_MMUS_PER_GPC_PARAMS_MESSAGE_ID" */ /* * NV2080_CTRL_CMD_GPU_GET_ACTIVE_PARTITION_IDS @@ -3334,7 +3358,7 @@ typedef struct NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS { NvU32 partitionCount; } NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS; -#define NV2080_CTRL_CMD_GPU_GET_ACTIVE_PARTITION_IDS (0x2080018b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_ACTIVE_PARTITION_IDS (0x2080018bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS_MESSAGE_ID" */ @@ -3367,10 +3391,10 @@ typedef struct NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS { * NV_ERR_INVALID_PARAM_STRUCT * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_CMD_GPU_GET_PIDS (0x2080018d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PIDS_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_PIDS (0x2080018dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PIDS_PARAMS_MESSAGE_ID" */ /* max size of pidTable */ -#define NV2080_CTRL_GPU_GET_PIDS_MAX_COUNT 950 +#define NV2080_CTRL_GPU_GET_PIDS_MAX_COUNT 950U #define NV2080_CTRL_GPU_GET_PIDS_PARAMS_MESSAGE_ID (0x8DU) @@ -3386,8 +3410,8 @@ typedef struct NV2080_CTRL_GPU_GET_PIDS_PARAMS { * PIDs with or without GPU contexts. For any other class id, PIDs only with GPU * contexts are returned. */ -#define NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_CLASS (0x00000000) -#define NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_VGPU_GUEST (0x00000001) +#define NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_CLASS (0x00000000U) +#define NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_VGPU_GUEST (0x00000001U) /* * NV2080_CTRL_SMC_SUBSCRIPTION_INFO @@ -3436,7 +3460,7 @@ typedef struct NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA { NV_DECLARE_ALIGNED(NvU64 protectedMemSharedDuped, 8); } NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA; -#define NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE (0x00000000) +#define NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE (0x00000000U) #define NV2080_CTRL_GPU_PID_INFO_INDEX_MAX NV2080_CTRL_GPU_PID_INFO_INDEX_VIDEO_MEMORY_USAGE @@ -3509,10 +3533,10 @@ typedef struct NV2080_CTRL_GPU_PID_INFO { * NV_ERR_INVALID_PARAM_STRUCT * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_CMD_GPU_GET_PID_INFO (0x2080018e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PID_INFO_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_PID_INFO (0x2080018eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_PID_INFO_PARAMS_MESSAGE_ID" */ /* max size of pidInfoList */ -#define NV2080_CTRL_GPU_GET_PID_INFO_MAX_COUNT 200 +#define NV2080_CTRL_GPU_GET_PID_INFO_MAX_COUNT 200U #define NV2080_CTRL_GPU_GET_PID_INFO_PARAMS_MESSAGE_ID (0x8EU) @@ -3522,6 +3546,36 @@ typedef struct NV2080_CTRL_GPU_GET_PID_INFO_PARAMS { } NV2080_CTRL_GPU_GET_PID_INFO_PARAMS; + +/*! + * NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT + * + * @brief Handle VF PRI faults + * + * faultType + * BAR1, BAR2, PHYSICAL or UNBOUND_INSTANCE + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * + */ + +#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT (0x20800192U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_INVALID 0U +#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR1 1U +#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR2 2U +#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_PHYSICAL 3U +#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_UNBOUND_INSTANCE 4U + +#define NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_MESSAGE_ID (0x92U) + +typedef struct NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS { + NvU32 faultType; +} NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS; + + /*! * Compute policy types to be specified by callers to set a config. * @@ -3530,8 +3584,8 @@ typedef struct NV2080_CTRL_GPU_GET_PID_INFO_PARAMS { * Check @ref NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_DATA_TIMESLICE for * permissible timeslice values. */ -#define NV2080_CTRL_GPU_COMPUTE_POLICY_TIMESLICE 0 -#define NV2080_CTRL_GPU_COMPUTE_POLICY_MAX 1 +#define NV2080_CTRL_GPU_COMPUTE_POLICY_TIMESLICE 0U +#define NV2080_CTRL_GPU_COMPUTE_POLICY_MAX 1U /*! * Enum consisting of permissible timeslice options that can configured @@ -3576,7 +3630,7 @@ typedef struct NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS { * NV_ERR_INVALID_ARGUMENT * NV_ERR_OBJECT_NOT_FOUND */ -#define NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG (0x20800195) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG (0x20800195U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID" */ /*! * This define limits the max number of policy configs that can be handled by @@ -3585,7 +3639,7 @@ typedef struct NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS { * @note Needs to be in sync (greater or equal) to NV2080_CTRL_GPU_COMPUTE_POLICY_MAX. */ -#define NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_LIST_MAX 32 +#define NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_LIST_MAX 32U #define NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS_MESSAGE_ID (0x95U) @@ -3599,6 +3653,72 @@ typedef struct NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS { NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG configList[NV2080_CTRL_GPU_COMPUTE_POLICY_CONFIG_LIST_MAX]; } NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS; +/* + * NV2080_CTRL_CMD_GPU_GET_GFID + * + * This command returns the GFID (GPU Function ID) for a given SR-IOV + * Virtual Function (VF) of the physical GPU. + * + * domain [IN] + * This field specifies the respective domain of the PCI device. + * bus [IN] + * This field specifies the bus id for a given VF. + * device [IN] + * This field specifies the device id for a given VF. + * func [IN] + * This field specifies the function id for a given VF. + * gfid[OUT] + * - This field returns GFID for a given VF BDF. + * gfidMask[OUT] + * - This field returns GFID mask value. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ + +#define NV2080_CTRL_CMD_GPU_GET_GFID (0x20800196U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_GFID_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_GFID_PARAMS_MESSAGE_ID (0x96U) + +typedef struct NV2080_CTRL_GPU_GET_GFID_PARAMS { + NvU32 domain; + NvU8 bus; + NvU8 device; + NvU8 func; + NvU32 gfid; + NvU32 gfidMask; +} NV2080_CTRL_GPU_GET_GFID_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY + * + * This command informs the GPU driver that the GPU partition associated with + * a given GFID has been activated or will be deactivated. + * + * gfid[IN] + * - The GPU function identifier for a given VF BDF + * bEnable [IN] + * - Set to NV_TRUE if the GPU partition has been activated. + * - Set to NV_FALSE if the GPU partition will be deactivated. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_OPERATING_SYSTEM + */ + +#define NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY (0x20800197U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS_MESSAGE_ID (0x97U) + +typedef struct NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS { + NvU32 gfid; + NvBool bEnable; +} NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS; /*! * NV2080_CTRL_CMD_GPU_VALIDATE_MEM_MAP_REQUEST @@ -3616,7 +3736,7 @@ typedef struct NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS { * NV_ERR_PROTECTION_FAULT * */ -#define NV2080_CTRL_CMD_GPU_VALIDATE_MEM_MAP_REQUEST (0x20800198) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_VALIDATE_MEM_MAP_REQUEST (0x20800198U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS_MESSAGE_ID (0x98U) @@ -3649,9 +3769,9 @@ typedef struct NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS { * Possible status values returned are: * NV_OK */ -#define NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES (0x2080019b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES (0x2080019bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS 0x90 +#define NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS 0xA0U #define NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID (0x9BU) @@ -3679,7 +3799,7 @@ typedef struct NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS { * Possible status values returned are: * NV_OK */ -#define NV2080_CTRL_CMD_GPU_GET_ID_NAME_MAPPING (0x2080019c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_ID_NAME_MAPPING (0x2080019cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS_MESSAGE_ID (0x9CU) @@ -3704,10 +3824,10 @@ typedef struct NV2080_CTRL_GPU_GET_ID_NAME_MAPPING_PARAMS { * NV_ERR_INVALID_ARGUMENT * NV_ERR_INVALID_PARAM_STRUCT */ -#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_NOPTRS (0x2080019d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_NOPTRS (0x2080019dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS_MESSAGE_ID" */ /* setting this to 100 keeps it right below 4k in size */ -#define NV2080_CTRL_REG_OPS_ARRAY_MAX 100 +#define NV2080_CTRL_REG_OPS_ARRAY_MAX 100U #define NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS_MESSAGE_ID (0x9DU) typedef struct NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS { @@ -3733,6 +3853,12 @@ typedef struct NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS { * the GPU ID of an attached GPU. * If bAllCaps == NV_FALSE, this parameter is an in parameter and the requester * should set it to the ID of the GPU that needs to be queried from. + * [in] gpuUuid + * Alternative to gpuId; used to identify target GPU for which caps are being queried. + * Option only available for Guest RPCs. + * If bUseUuid == NV_TRUE, gpuUuid is used in lieu of gpuId to identify target GPU. + * If bUseUuid == NV_FALSE, gpuUuid is ignored and gpuId is used by default. + * If bAllCaps == NV_TRUE, gpuUuid is ignored. * [out] p2pCaps * Peer to peer capabilities discovered between the GPUs. * See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values. @@ -3747,8 +3873,11 @@ typedef struct NV2080_CTRL_GPU_EXEC_REG_OPS_NOPTRS_PARAMS { * Bus peer ID. For an invalid or a non-existent peer this field * has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER. */ +#define NV2080_GET_P2P_CAPS_UUID_LEN 16U + typedef struct NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO { NvU32 gpuId; + NvU8 gpuUuid[NV2080_GET_P2P_CAPS_UUID_LEN]; NvU32 p2pCaps; NvU32 p2pOptimalReadCEs; NvU32 p2pOptimalWriteCEs; @@ -3767,6 +3896,10 @@ typedef struct NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO { * Set to NV_TRUE to query the capabilities for all the attached GPUs. * Set to NV_FALSE and specify peerGpuCount and peerGpuCaps[].gpuId * to retrieve the capabilities only for the specified GPUs. + * [in] bUseUuid + * Option only available for Guest RPCs. + * Set to NV_TRUE to use gpuUuid in lieu of gpuId to identify target GPU. + * If bAllCaps == NV_TRUE, bUseUuid is ignored. * [in/out] peerGpuCount * The number of the peerGpuCaps entries. * If bAllCaps == NV_TRUE, this parameter is an out parameter and equals to @@ -3782,12 +3915,13 @@ typedef struct NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO { * NV_ERR_INVALID_ARGUMENT - Invalid peerGpuCount * NV_ERR_OBJECT_NOT_FOUND - Invalid peerGpuCaps[].gpuId */ -#define NV2080_CTRL_CMD_GET_P2P_CAPS (0x208001a0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GET_P2P_CAPS_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GET_P2P_CAPS (0x208001a0U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GET_P2P_CAPS_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GET_P2P_CAPS_PARAMS_MESSAGE_ID (0xA0U) typedef struct NV2080_CTRL_GET_P2P_CAPS_PARAMS { NvBool bAllCaps; + NvBool bUseUuid; NvU32 peerGpuCount; NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO peerGpuCaps[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; } NV2080_CTRL_GET_P2P_CAPS_PARAMS; @@ -3840,6 +3974,144 @@ typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS { NV2080_CTRL_GPU_COMPUTE_PROFILE profiles[NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE]; } NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS; -#define NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILES (0x208001a2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILES (0x208001a2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_GPU_FABRIC_PROBE_STATE_UNSUPPORTED 0U +#define NV2080_CTRL_GPU_FABRIC_PROBE_STATE_NOT_STARTED 1U +#define NV2080_CTRL_GPU_FABRIC_PROBE_STATE_IN_PROGRESS 2U +#define NV2080_CTRL_GPU_FABRIC_PROBE_STATE_COMPLETE 3U + +#define NV2080_GPU_FABRIC_CLUSTER_UUID_LEN 16U + +#define NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_SUPPORTED NVBIT64(0) + +/*! + * NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS + * + * This structure provides the GPU<-->FM probe state info on NVSwitch based + * systems + * + * state[OUT] + * - Current state of GPU<-->FM probe req/rsp + * Following values can be returned + * _UNSUPPORTED - system does not support this feature + * _NOT_STARTED - probe request is not yet sent to the FM + * _IN_PROGRESS - probe response is not yet received + * _COMPLETE - probe response is received + * When state is NV2080_CTRL_GPU_FABRIC_PROBE_STATE_COMPLETE + * status has to be checked for probe response success/failure + * status[OUT] + * - Inband Probe response status + * A GPU which returns NV_OK status upon receiving the probe response + * can participate in P2P + * clusterUuid[OUT] + * - Uuid of the cluster to which this node belongs + * fabricPartitionId[OUT] + * - Fabric partition Id + * fabricCaps[OUT] + * - Summary of fabric capabilities received from probe resp + * Possible values are + * NV2080_CTRL_GPU_FABRIC_PROBE_CAP_* + */ +#define NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xA3U) + +typedef struct NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS { + NvU8 state; + NV_STATUS status; + NvU8 clusterUuid[NV2080_GPU_FABRIC_CLUSTER_UUID_LEN]; + NvU16 fabricPartitionId; + NV_DECLARE_ALIGNED(NvU64 fabricCaps, 8); +} NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS; + +#define NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO (0x208001a3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS + * + * This command retrieves and constructs the GPU partnumber from the VBIOS. + * + * The following data are currently supported: + * + * pciDevId + * The PCI device ID + * + * chipSku + * The chip SKU information + * + * chipMajor + * The chip major number + * + * chipMinor + * The chip minor number + * + */ +#define NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS (0x208001a4U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS_MESSAGE_ID" */ + +/* + * The string format for a GPU part number + * The GPU part number is formatted with 4 hexadecimal digits for the PCI device ID, the chip SKU string, + * the chip major number, and then the chip minor number. + * Ordering of the fields for the string format must be synced with the NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS + * struct fields. + */ +#define GPU_PART_NUMBER_FMT "%04X-%s-%X%X" + +/* The maximum length for the chip sku */ +#define NV2080_MAX_CHIP_SKU_LENGTH 0x00000004U + +#define NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS_MESSAGE_ID (0xA4U) + +typedef struct NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS { + NvU32 pciDevId; + NvU8 chipSku[NV2080_MAX_CHIP_SKU_LENGTH]; + NvU32 chipMajor; + NvU32 chipMinor; +} NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS; + +/* + * NV2080_CTRL_CMD_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP + * + * This command returns the host hardware defined engine ID of the specified engine(s). + * + * swizzId[IN] + * - HW Partition ID associated with the requested partition. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP (0x208001a5U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS_MESSAGE_ID (0xA5U) + +typedef struct NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS { + NvU32 swizzId; +} NV2080_CTRL_GPU_MOVE_RUNLISTS_ALLOCATION_TO_SUBHEAP_PARAMS; + +#define NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS (0x208001a6U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS_GSP (0x208001a7U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS_VGPU (0x208001a8U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS_MESSAGE_ID" */ + +/* setting this to 100 keeps it right below 4k in size */ +#define NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX 50U +typedef struct NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS { + NvHandle hClientTarget; + NvHandle hChannelTarget; + NvU32 bNonTransactional; + NvU32 regOpCount; + NvU32 smIds[NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX]; + NV2080_CTRL_GPU_REG_OP regOps[NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX]; + NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8); +} NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS; + +#define NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_MESSAGE_ID (0xA6U) + +typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS; +#define NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS_MESSAGE_ID (0xA7U) + +typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS_GSP_PARAMS; +#define NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS_MESSAGE_ID (0xA8U) + +typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS; /* _ctrl2080gpu_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h index c7fb06425..dde6eed98 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h @@ -33,6 +33,8 @@ #include "ctrl/ctrl2080/ctrl2080base.h" #include "ctrl/ctrl0080/ctrl0080gr.h" /* 2080 is partially derivative of 0080 */ +#include "nvcfg_sdk.h" + /* * NV2080_CTRL_GR_ROUTE_INFO * @@ -250,6 +252,7 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO; #define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SINGLETON_GPCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SINGLETON_GPCS #define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS #define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC /* When adding a new INDEX, please update INDEX_MAX and MAX_SIZE accordingly * NOTE: 0080 functionality is merged with 2080 functionality, so this max size @@ -297,6 +300,8 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO; #define NV2080_CTRL_GR_INFO_SM_VERSION_8_09 (0x00000809U) #define NV2080_CTRL_GR_INFO_SM_VERSION_9_00 (0x00000900U) + + /* compatibility SM versions to match the official names in the ISA (e.g., SM5.2) */ #define NV2080_CTRL_GR_INFO_SM_VERSION_5_2 (NV2080_CTRL_GR_INFO_SM_VERSION_5_02) #define NV2080_CTRL_GR_INFO_SM_VERSION_5_3 (NV2080_CTRL_GR_INFO_SM_VERSION_5_03) @@ -314,6 +319,7 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO; #define NV2080_CTRL_GR_INFO_SM_VERSION_9_0 (NV2080_CTRL_GR_INFO_SM_VERSION_9_00) + /** * NV2080_CTRL_CMD_GR_GET_INFO * diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080illum.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080illum.h index 73db05198..54a762ab5 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080illum.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080illum.h @@ -28,3 +28,4 @@ // Source file: ctrl/ctrl2080/ctrl2080illum.finn // + diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h index a92da4d0d..5307f5d05 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h @@ -39,6 +39,9 @@ #include "ctrl/ctrl0080/ctrl0080bsp.h" /* NV0080_CTRL_BSP_CAPS_TBL_SIZE */ #include "ctrl/ctrl2080/ctrl2080fifo.h" /* NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO */ #include "ctrl/ctrl0000/ctrl0000system.h" +#include "ctrl/ctrl90f1.h" +#include "ctrl/ctrl30f1.h" + /*! * NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO * @@ -54,6 +57,9 @@ * bFbRemapperEnabled * Display IP v02_01 and later. * Indicates that the display remapper HW exists and is enabled. + * numHeads + * Display IP v02_01 and later. + * Provides the number of heads HW support. */ #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO (0x20800a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */ @@ -64,6 +70,10 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS { NvU32 feHwSysCap; NvU32 windowPresentMask; NvBool bFbRemapperEnabled; + NvU32 numHeads; + NvBool bPrimaryVga; + NvU32 i2cPort; + NvU32 internalDispActiveMask; } NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS; @@ -674,6 +684,7 @@ typedef struct NV2080_CTRL_INTERNAL_DEVICE_INFO { NvU32 isEngine; NvU32 rlEngId; NvU32 runlistPriBase; + NvU32 groupId; } NV2080_CTRL_INTERNAL_DEVICE_INFO; #define NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES 88 @@ -886,6 +897,9 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS { * * nvOfaCount [OUT] * # NVOFA engines + * + * validCTSIdMask [OUT] + * # mask of CTS IDs which can be assigned under this profile */ #define NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES 20 @@ -905,6 +919,7 @@ typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO { NvU32 nvDecCount; NvU32 nvJpgCount; NvU32 nvOfaCount; + NV_DECLARE_ALIGNED(NvU64 validCTSIdMask, 8); } NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO; /*! @@ -919,8 +934,8 @@ typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO { * Supported profiles. */ typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS { - NvU32 count; - NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO table[NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES]; + NvU32 count; + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO table[NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES], 8); } NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS; /*! @@ -1010,42 +1025,6 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS { TEGRA_IMP_IMPORT_DATA tegraImpImportData; } NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS; -/*! - * NV2080_CTRL_CMD_INTERNAL_BUS_BIND_LOCAL_GFID_FOR_P2P - * - * Binds local GFID for SR-IOV P2P requests - * - * localGfid [IN] - * GFID to bind in the P2P source GPU - * - * peerId [IN] - * Peer ID of the P2P destination GPU - */ -#define NV2080_CTRL_CMD_INTERNAL_BUS_BIND_LOCAL_GFID_FOR_P2P (0x20800a55) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BUS_BIND_LOCAL_GFID_FOR_P2P_PARAMS_MESSAGE_ID" */ - -#define NV2080_CTRL_INTERNAL_BUS_BIND_LOCAL_GFID_FOR_P2P_PARAMS_MESSAGE_ID (0x55U) - -typedef struct NV2080_CTRL_INTERNAL_BUS_BIND_LOCAL_GFID_FOR_P2P_PARAMS { - NvU32 localGfid; - NvU32 peerId; -} NV2080_CTRL_INTERNAL_BUS_BIND_LOCAL_GFID_FOR_P2P_PARAMS; - -/*! - * NV2080_CTRL_CMD_INTERNAL_BUS_BIND_REMOTE_GFID_FOR_P2P - * - * Binds remote GFID for SR-IOV P2P requests - * - * remoteGfid [IN] - * GFID to bind in the P2P destination GPU - */ -#define NV2080_CTRL_CMD_INTERNAL_BUS_BIND_REMOTE_GFID_FOR_P2P (0x20800a56) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BUS_BIND_REMOTE_GFID_FOR_P2P_PARAMS_MESSAGE_ID" */ - -#define NV2080_CTRL_INTERNAL_BUS_BIND_REMOTE_GFID_FOR_P2P_PARAMS_MESSAGE_ID (0x56U) - -typedef struct NV2080_CTRL_INTERNAL_BUS_BIND_REMOTE_GFID_FOR_P2P_PARAMS { - NvU32 remoteGfid; -} NV2080_CTRL_INTERNAL_BUS_BIND_REMOTE_GFID_FOR_P2P_PARAMS; - /*! * NV2080_CTRL_CMD_INTERNAL_BUS_FLUSH_WITH_SYSMEMBAR * @@ -1526,19 +1505,29 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS * * Invoke RC recovery after watchdog timeout is hit. */ -#define NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT (0x20800a6a) /* finn: Evaluated from "((FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6a)" */ +#define NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT (0x20800a6a) /* finn: Evaluated from "((FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6a)" */ /* ! * This command disables cuda limit activation at teardown of the client. */ -#define NV2080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_DISABLE (0x20800a7a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7A" */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_DISABLE (0x20800a7a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7A" */ /* * This command is cleaning up OPTP when a client is found to have * been terminated unexpectedly. */ -#define NV2080_CTRL_CMD_INTERNAL_PERF_OPTP_CLI_CLEAR (0x20800a7c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7C" */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_OPTP_CLI_CLEAR (0x20800a7c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7C" */ +/* ! + * This command is used to get the current AUX power state of the sub-device. + */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_GET_AUX_POWER_STATE (0x20800a81) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS_MESSAGE_ID (0x81U) + +typedef struct NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS { + NvU32 powerState; +} NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS; /*! * This command can be used to boost P-State up one level or to the highest for a limited @@ -1559,7 +1548,7 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS * NV_ERR_INVALID_PARAM_STRUCT * NV_ERR_INVALID_ARGUMENT */ -#define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_2X (0x20800a9a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_2X (0x20800a9a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X_MESSAGE_ID" */ #define NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X_MESSAGE_ID (0x9AU) @@ -1719,6 +1708,23 @@ typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PAR NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferPteArray[NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES], 8); } NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS; +/* + * NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER + * + * Pin PDEs for Global VA range on the server RM and then mirror the client's page + * directory/tables in the server. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER (0x20800a9f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS_MESSAGE_ID (0x9FU) + +typedef struct NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS { + NV_DECLARE_ALIGNED(NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS PdeCopyParams, 8); +} NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS; + /* * NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER * @@ -1798,7 +1804,7 @@ typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X { * Retrieves skyline information about the GPU. Params are sized to currently known max * values, but will need to be modified in the future should that change. */ -#define NV2080_CTRL_CMD_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO (0x208038a2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GRMGR_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO (0x20800aa2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_SKYLINES 8 #define NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS 8 @@ -2209,7 +2215,99 @@ typedef struct NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS { * Possible status values returned are: * NV_OK */ -#define NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP (0x20800ab4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xB4" */ +#define NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP (0x20800ab4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS_MESSAGE_ID (0xB4U) + +typedef struct NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS { + NvBool bDevShrBuf; + NvBool bMigShrBuf; +} NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS; + +/*! + * NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO + * + * [in] gpuId + * GPU ID. + * [in] gpuInstance + * GPU instance. + * [in] p2pCaps + * Peer to peer capabilities discovered between the GPUs. + * See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values. + * [in] p2pOptimalReadCEs + * Mask of CEs to use for p2p reads over Nvlink. + * [in] p2pOptimalWriteCEs + * Mask of CEs to use for p2p writes over Nvlink. + * [in] p2pCapsStatus + * Status of all supported p2p capabilities. + * See NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 for the list of valid values. + * [in] busPeerId + * Bus peer ID. For an invalid or a non-existent peer this field + * has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER. + */ +typedef struct NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO { + NvU32 gpuId; + NvU32 gpuInstance; + NvU32 p2pCaps; + NvU32 p2pOptimalReadCEs; + NvU32 p2pOptimalWriteCEs; + NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE]; + NvU32 busPeerId; +} NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO; + +/*! + * NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS + * + * An internal call to propagate the peer to peer capabilities of peer GPUs + * to the Physical RM. These capabilities are to be consumed by the vGPU GSP plugin. + * This control is used to both add and and update the peer to peer capabilities. + * The existing GPU entries will be updated and those which don't exist will be added. + * Use NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS to remove the added entries. + * + * [in] peerGpuCount + * The number of the peerGpuInfos entries. + * [in] peerGpuInfos + * The array of NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS entries, describing + * the peer to peer capabilities of the specified GPUs. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT - Invalid peerGpuCount + * NV_ERR_INSUFFICIENT_RESOURCES - Total GPU count exceeds the maximum value + */ +#define NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS (0x20800ab5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS_MESSAGE_ID (0xB5U) + +typedef struct NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS { + NvU32 peerGpuCount; + NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO peerGpuInfos[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; +} NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS + * + * An internal call to remove the cached peer to peer capabilities of peer GPUs + * from the Physical RM. + * + * [in] peerGpuIdCount + * The number of the peerGpuIds entries. + * [in] peerGpuIds + * The array of GPU IDs, specifying the GPU for which the entries need to be removed. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT - Invalid peerGpuIdCount + * NV_ERR_OBJECT_NOT_FOUND - Invalid peerGpuIds[] entry + */ +#define NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS (0x20800ab6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS_MESSAGE_ID (0xB6U) + +typedef struct NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS { + NvU32 peerGpuIdCount; + NvU32 peerGpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; +} NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS; @@ -2261,13 +2359,63 @@ typedef struct NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS { */ #define NV2080_CTRL_CMD_INTERNAL_BIF_SET_PCIE_RO (0x20800ab9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS_MESSAGE_ID (0xb9U) +#define NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS_MESSAGE_ID (0xB9U) typedef struct NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS { // Enable/disable PCIe relaxed ordering NvBool enableRo; } NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS; +/* + * NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE + * + * An internal call to invoke the sequence VGA register reads & writes to + * perform save and restore of VGA + * + * [in] saveOrRestore + * To indicate whether save or restore needs to be performed. + * [in] useVbios + * Primary VGA indication from OS. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE (0x20800a76) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS_MESSAGE_ID (0x76U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS { + + NvBool bSaveOrRestore; + NvBool bUseVbios; +} NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE + * + * To perform restore operation from saved fonts. + * + * [in] saveOrRestore + * To indicate whether save or restore needs to be performed. + * [in] useVbios + * Primary VGA indication from OS. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE (0x20800a77) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS_MESSAGE_ID (0x77U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS { + + NvBool bWriteCr; +} NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS; + /*! * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES @@ -2300,6 +2448,7 @@ typedef struct NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE { NvU32 gpcCount; NvU32 veidCount; NvU32 smCount; + NvU32 physicalSlots; } NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE; /*! @@ -2313,7 +2462,7 @@ typedef struct NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE { * profiles[OUT] * - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles */ -#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xbbU) +#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xBBU) typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS { NvU32 profileCount; @@ -2322,6 +2471,310 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS { +/* + * NV2080_CTRL_CMD_INTERNAL_CCU_SET_STREAM_STATE + * + * This command sets the ccu stream to enable/disable state. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_CCU_SET_STREAM_STATE (0x20800abd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS_MESSAGE_ID (0xBDU) + +typedef struct NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS { + NvBool bStreamState; +} NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GSYNC_ATTACH_AND_INIT + * + * Attach GPU to the external device. + * + * [in] bExtDevFound + * To enable GPIO interrupts. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_GSYNC_ATTACH_AND_INIT (0x20800abe) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS_MESSAGE_ID (0xBEU) + +typedef struct NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS { + NvBool bExtDevFound; +} NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS + * + * Optimize the Gsync timing parameters + * + * [in] timingParameters + * Timing parameters passed by client. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS (0x20800abf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS_MESSAGE_ID (0xBFU) + +typedef struct NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS { + NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS timingParameters; +} NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_DISPLAY_IDS + * + * Get displayIDs supported by the display. + * + * [out] displayIds + * Associated display ID with head. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_DISPLAY_IDS (0x20800ac0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS_MESSAGE_ID" */ + +#define NV2080_MAX_NUM_HEADS 4 + +#define NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS_MESSAGE_ID (0xC0U) + +typedef struct NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS { + NvU32 displayIds[NV2080_MAX_NUM_HEADS]; +} NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_STREO_SYNC + * + * Set the Stereo sync for Gsync + * + * [in] slave + * Slave GPU head status. + * [in] localSlave + * Slave GPU head status but are not coupled. + * [in] master + * Master GPU head status. + * [in] regstatus + * Register status of status1 register. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_STREO_SYNC (0x20800ac1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS_MESSAGE_ID (0xC1U) + +typedef struct NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS { + NvU32 slave[NV2080_MAX_NUM_HEADS]; + NvU32 localSlave[NV2080_MAX_NUM_HEADS]; + NvU32 master[NV2080_MAX_NUM_HEADS]; + NvU32 regStatus; +} NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES + * + * Get vertical active lines for given head. + * + * [in] head + * For the headIdx which we need active. + * [out] vActiveLines + * Vertical active lines. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES (0x20800ac4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS_MESSAGE_ID (0xC4U) + +typedef struct NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS { + NvU32 headIdx; + NvU32 vActiveLines; +} NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GSYNC_IS_DISPLAYID_VALID + * + * Verifies if this displayId is valid. + * + * [in] displays + * Displays given by the client + * + * [out] displayId + * DisplayId for the given display + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_GSYNC_IS_DISPLAYID_VALID (0x20800ac9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS_MESSAGE_ID (0xC9U) + +typedef struct NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS { + NvU32 displays; + NvU32 displayId; +} NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC + * + * Disable the raster sync gpio on the other P2060 GPU + * that's connected to master over Video bridge. + * + * [in] bEnableMaster + * If it is master gpu. + * + * [out] bRasterSyncGpioSaved + * If raster sync GPIO direction is saved or not. + * + * [in/out] bRasterSyncGpioDirection + * During save it gets the direction. + * In restores it sets the direction. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC (0x20800aca) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS_MESSAGE_ID (0xCAU) + +typedef struct NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS { + NvBool bEnableMaster; + NvBool bRasterSyncGpioSaved; + NvU32 bRasterSyncGpioDirection; +} NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_FBSR_INIT + * + * Initialize FBSR on GSP to prepare for suspend-resume + * + * [in] fbsrType + * Fbsr object type + * [in] numRegions + * Number of regions that GSP should allocate records for + * [in] hClient + * Handle to client of SYSMEM memlist object + * [in] hSysMem + * Handle to SYSMEM memlist object + * [in] gspFbAllocsSysOffset + * Offset in SYSMEM for GSP's FB Allocations + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_FBSR_INIT (0x20800ac2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID (0xC2U) + +typedef struct NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS { + NvU32 fbsrType; + NvU32 numRegions; + NvHandle hClient; + NvHandle hSysMem; + NV_DECLARE_ALIGNED(NvU64 gspFbAllocsSysOffset, 8); +} NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_FBSR_SEND_REGION_INFO + * + * Send info of FB region that will be saved/restored by GSP on suspend-resume + * + * [in] fbsrType + * Fbsr object type + * [in] hClient + * Handle to client of FBMEM memlist object + * [in] hVidMem + * Handle to FBMEM memlist object + * [in] vidOffset + * Offset in FBMEM region to save/restore + * [in] sysOffset + * Offset in SYSMEM region to save to/restore from + * [in] size + * Size of region being saved/restored + */ +#define NV2080_CTRL_CMD_INTERNAL_FBSR_SEND_REGION_INFO (0x20800ac3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS_MESSAGE_ID (0xC3U) + +typedef struct NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS { + NvU32 fbsrType; + NvHandle hClient; + NvHandle hVidMem; + NV_DECLARE_ALIGNED(NvU64 vidOffset, 8); + NV_DECLARE_ALIGNED(NvU64 sysOffset, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); +} NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB + * + * This command is used to get the amount of host reserved FB + * + * hostReservedFb [OUT] + * Amount of FB reserved for the host + * vgpuTypeId [IN] + * The Type ID for VGPU profile + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB (0x20800ac5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS_MESSAGE_ID (0xC5U) + +typedef struct NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS { + NV_DECLARE_ALIGNED(NvU64 hostReservedFb, 8); + NvU32 vgpuTypeId; +} NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD + * + * This command initiates brightc module state load. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD (0x20800ac6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_ACPI_DSM_READ_SIZE (0x1000) /* finn: Evaluated from "(4 * 1024)" */ + +#define NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS_MESSAGE_ID (0xC6U) + +typedef struct NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS { + NvU32 status; + NvU16 backLightDataSize; + NvU8 backLightData[NV2080_CTRL_ACPI_DSM_READ_SIZE]; +} NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS; + /* * NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL * @@ -2329,14 +2782,12 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS { * * [Out] numActiveLinksPerIoctrl */ -#define NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID (0xD8U) +#define NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID (0xC7U) typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS { NvU32 numActiveLinksPerIoctrl; } NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS; - -#define NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL (0x20800ad8U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID" */ - +#define NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL (0x20800ac7U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID" */ /* * NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL * @@ -2344,13 +2795,126 @@ typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS * * [Out] numLinksPerIoctrl */ -#define NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID (0xD9U) +#define NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID (0xC8U) typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS { NvU32 numLinksPerIoctrl; } NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS; +#define NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL (0x20800ac8U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL (0x20800ad9U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS_MESSAGE_ID" */ +/*! + * NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE + * + * Update the system control capability + * + * bIsSysCtrlSupported [IN] + If the system control is supported + * bIsPlatformLegacy [OUT] + If the platform is legacy + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE (0x20800acb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS_MESSAGE_ID (0xCBU) + +typedef struct NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS { + NvBool bIsSysCtrlSupported; + NvBool bIsPlatformLegacy; +} NV2080_CTRL_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE_PARAMS; + +/*! + * Macros for PFM_REQ_HNDLR_STATE_SYNC data types. + */ +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_PMGR 0x00U +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_THERM 0x01U +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_SMBPBI 0x02U + +/*! + * Structure representing static data for a PFM_REQ_HNDLR_STATE_SYNC_SMBPBI. + */ +typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI { + /*! + * PFM sensor ID + */ + NvU32 sensorId; + + /*! + * PFM sensor limit value if required + */ + NvU32 limit; +} NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI; + +/*! + * Structure of static information describing PFM_REQ_HNDLR_STATE_SYNC data types. + */ +typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA { + /*! + * @ref NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_ + */ + NvU8 type; + + /*! + * Type-specific information. + */ + union { + NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI smbpbi; + } data; +} NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA; + +/*! + * Macros for PFM_REQ_HNDLR_STATE_SYNC flags for specific operation. + */ +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_PMGR_LOAD 0x00U +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_THERM_INIT 0x01U +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_CLEAR 0x02U +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_SMBPBI_OP_SET 0x03U + +/*! + * Structure of static information describing PFM_REQ_HNDLR_STATE_SYNC params. + */ +typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS { + /*! + * @ref NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_FLAGS_ + */ + NvU8 flags; + + /*! + * Type-specific information. + */ + NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA syncData; +} NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC + * + * State sync with platform req handler and SMBPBI + * + * flags [IN] + * Flags that needs sync operation between physical and kernel + * + * syncData [IN] + * Sync payload data + * + */ +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC (0x20800acc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xCC" */ + +/*! + * NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC + * + * State sync with platform req handler and SMBPBI + * + * flags [IN] + * Flags that needs sync operation between physical and kernel + * + * syncData [IN] + * Sync payload data + * + */ +#define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC (0x20800acd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xCD" */ /*! * NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE @@ -2358,7 +2922,7 @@ typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS * Query Coherent FB Aperture Size. * */ -#define NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE (0x20800ada) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE (0x20800ada) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID (0xDAU) @@ -2367,4 +2931,246 @@ typedef struct NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS { NV_DECLARE_ALIGNED(NvU64 coherentFbApertureSize, 8); } NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS; + +/*! + * Macros for NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE flag + */ +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_FORCED_OFF_STATUS 0x00U +#define NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_GET_PM1_STATUS 0x01U + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE + * + * Queries PM1 Forced off / PM1 Available status + * + * flag [IN] + * Fetch PM1 Forced off / PM1 Available status based on value. + * bStatus [OUT] + * PM1 Forced off / PM1 Available is true or false. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_ARGUMETS + */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE (0x20800ace) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS_MESSAGE_ID (0xCEU) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS { + /*! + * Fetch PM1 Forced off / PM1 Available status based on value. + */ + NvU8 flag; + + /*! + * PM1 Forced off / PM1 Available status + */ + NvBool bStatus; +} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_PM1_STATE_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE + * + * Set PM1 state to enabled / disabled (boost clocks). + * + * bEnable [IN] + * NV_TRUE means enable PM1, NV_FALSE means disable. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE (0x20800acf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS_MESSAGE_ID (0xCFU) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS { + + /*! + * NV_TRUE means enable PM1, NV_FALSE means disable. + */ + NvBool bEnable; +} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT + * + * Updates EDPpeak Limit of GPU + * + * bEnable [IN] + * Enable or Reset the settings + * + * Possible status values returned are: + * NV_OK + * NV_ERR_GENERIC + * NV_ERR_NOT_SUPPORTED + * NV_ERR_NOT_READY + */ + +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT (0x20800ad0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS_MESSAGE_ID (0xD0U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS { + NvBool bEnable; +} NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT + * + * Updates Target Temperature of GPU + * + * targetTemp [IN] + * Target Temperature Set from SBIOS + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT (0x20800ad1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS_MESSAGE_ID (0xD1U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS { + NvS32 targetTemp; +} NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_UPDATE_TGPU_LIMIT_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE + * + * Enable / disable CTGP MODE + * + * bEnable [IN] + * Enable or Reset the settings + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE (0x20800ad2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS_MESSAGE_ID (0xD2U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS { + NvBool bEnable; +} NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TGP_MODE_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2 + * + * Configuration of the turbo v2 parameters for NVPCF-Turbo arb control + * + * ctgpOffsetmW [IN] + * TGP MODE Offset in mW + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2 (0x20800ad3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS_MESSAGE_ID (0xD3U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS { + NvU32 ctgpOffsetmW; +} NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_CONFIGURE_TURBO_V2_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO + * + * Query VPstatese info. Get VPS PS2.0 support / get highest VP State Idx and requested VP State Idx + * + * bVpsPs20Supported [OUT] + * Reflects Vpstates PS20 support + * vPstateIdxHighest [OUT} + * Reflects Highest VPstate Idx + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO (0x20800ad4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS_MESSAGE_ID (0xD4U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS { + /*! + * Reflects Vpstates PS20 support + */ + NvBool bVpsPs20Supported; + + /*! + * Get highest VPState Idx from VBIOS + */ + NvU32 vPstateIdxHighest; +} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_INFO_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING + * + * Get vPstate mapping for requested pStateIdx + * + * pStateIdx [IN] + * Requested PState Idx + * vPstateIdx [OUT} + * Mapped VPstate Idx + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING (0x20800ad5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS_MESSAGE_ID (0xD5U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS { + /*! + * Requested PState Idx + */ + NvU32 pStateIdx; + + /*! + * Mapped VPstate Idx + */ + NvU32 vPstateIdxMapping; +} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_GET_VPSTATE_MAPPING_PARAMS; + +/*! + * NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE + * + * Set requested VPstate + * + * vPstateIdx [IN] + * VPstate Idx to be set + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE (0x20800ad6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS_MESSAGE_ID (0xD6U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS { + + /*! + * NV_TRUE means enable PM1, NV_FALSE means disable. + */ + NvU32 vPstateIdx; +} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS; + +/* + * This command unsets Dynamic Boost limit when nvidia-powerd is terminated unexpectedly. + */ +#define NV2080_CTRL_CMD_INTERNAL_PMGR_UNSET_DYNAMIC_BOOST_LIMIT (0x20800a7b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7B" */ + /* ctrl2080internal_h */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080lpwr.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080lpwr.h index 068d4f2f8..9a121f97f 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080lpwr.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080lpwr.h @@ -23,6 +23,8 @@ #pragma once +#include + // // This file was generated with FINN, an NVIDIA coding tool. // Source file: ctrl/ctrl2080/ctrl2080lpwr.finn @@ -30,5 +32,69 @@ +/*! + * NV2080_CTRL_CMD_LPWR_DIFR_CTRL + * + * This command is used to control the DIFR + * feature behavior. + * + */ +#define NV2080_CTRL_CMD_LPWR_DIFR_CTRL (0x20802801) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_LPWR_INTERFACE_ID << 8) | NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS_MESSAGE_ID" */ + +/*! + * @brief Various Values for control + */ +// Disable the DIFR +#define NV2080_CTRL_LPWR_DIFR_CTRL_DISABLE (0x00000001) +// Enable the DIFR +#define NV2080_CTRL_LPWR_DIFR_CTRL_ENABLE (0x00000002) + +// Support status for DIFR +#define NV2080_CTRL_LPWR_DIFR_CTRL_SUPPORT_STATUS (0x00000003) + +/*! + * Structure containing DIFR control call Parameters + */ +#define NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS { + NvU32 ctrlParamVal; +} NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS; + +// Values for the SUPPORT Control Status +#define NV2080_CTRL_LPWR_DIFR_SUPPORTED (0x00000001) +#define NV2080_CTRL_LPWR_DIFR_NOT_SUPPORTED (0x00000002) + +/*! + * NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE + * + * This control call is used to send the prefetch response + * + */ +#define NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE (0x20802802) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_LPWR_INTERFACE_ID << 8) | NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS_MESSAGE_ID" */ + +/*! + * @brief Various Values of Reponses for Prefetch Status + */ + +// Prefetch is successfull. +#define NV2080_CTRL_LPWR_DIFR_PREFETCH_SUCCESS (0x00000001) +// OS Filps are enabled, so prefetch can not be done. +#define NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_OS_FLIPS_ENABLED (0x00000002) +// Current Display surface can not fit in L2 +#define NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_INSUFFICIENT_L2_SIZE (0x00000003) +// Fatal and un recoverable Error +#define NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_CE_HW_ERROR (0x00000004) + +/*! + * Structure containing DIFR prefetch response control call Parameters + */ +#define NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS { + NvU32 responseVal; +} NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS; + + // _ctrl2080lpwr_h_ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h index 23cce95d5..82504293b 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -134,6 +134,7 @@ typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS { #define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_0 (0x00000005U) #define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1 (0x00000006U) #define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0 (0x00000007U) + #define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_INVALID (0x00000000U) #define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_1_0 (0x00000001U) #define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_0 (0x00000002U) @@ -142,6 +143,7 @@ typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS { #define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_1 (0x00000006U) #define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_4_0 (0x00000007U) + /* * NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS * @@ -491,12 +493,40 @@ typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS { * Returns the NVLIPT_LNK Log En Mask 0 * Used in Ampere and later * + * NVLIPTLnkCtrlLinkStateRequest + * Returns the NVLIPT_LNK Control Link State Request value + * Used in Ampere and later + * * DLSpeedStatusTx * Returns the NVLINK DL speed status for sublink Tx * * DLSpeedStatusRx * Returns the NVLINK DL speed status for sublink Rx * + * NVLDLRxSlsmErrCntl + * Returns the NVLDL_RXSLSM_ERR_CNTL value + * Used in Hopper and later + * + * NVLDLTopLinkState + * Returns the NVLDL_TOP_LINK_STATE value + * Used in Hopper and later + * + * NVLDLTopIntr + * Returns the NVLDL_TOP_INTR value + * Used in Hopper and later + * + * DLStatMN00 + * Returns the DLSTAT MN00 Code and subcode + * Used in Hopper and later + * + * DLStatUC01 + * Returns the DLSTAT UC01 value + * Used in Hopper and later + * + * MinionNvlinkLinkIntr + * Returns the MINION_NVLINK_LINK_INTR code and subcode + * Used in Hopper and later + * * bExcessErrorDL * Returns true for excessive error rate interrupt from DL */ @@ -519,8 +549,15 @@ typedef struct NV2080_CTRL_NVLINK_ERR_INFO { NvU32 MIFRxErrStatus0; NvU32 NVLIPTLnkErrStatus0; NvU32 NVLIPTLnkErrLogEn0; + NvU32 NVLIPTLnkCtrlLinkStateRequest; NvU32 DLSpeedStatusTx; NvU32 DLSpeedStatusRx; + NvU32 NVLDLRxSlsmErrCntl; + NvU32 NVLDLTopLinkState; + NvU32 NVLDLTopIntr; + NvU32 DLStatMN00; + NvU32 DLStatUC01; + NvU32 MinionNvlinkLinkIntr; NvBool bExcessErrorDL; } NV2080_CTRL_NVLINK_ERR_INFO; @@ -601,6 +638,11 @@ typedef struct NV2080_CTRL_NVLINK_COMMON_ERR_INFO { #define NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_SAFE (0x00000006U) #define NV2080_CTRL_NVLINK_SL1_SLSM_STATUS_RX_PRIMARY_STATE_OFF (0x00000007U) +/* Flags to query different debug registers */ +#define NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_DEFAULT (0x0U) +#define NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_INTR_STATUS (0x1U) +#define NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_ALI_STATUS (0x2U) + #define NV2080_CTRL_NVLINK_MAX_IOCTRLS 3U /* * NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS @@ -616,6 +658,12 @@ typedef struct NV2080_CTRL_NVLINK_COMMON_ERR_INFO { * * commonErrInfo * Returns the error information common to each IOCTRL + * + * ErrInfoFlags + * Input for determining which values to query. Possible values: + * NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_INTR_STATUS + * NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_ALI_STATUS + * */ #define NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS_MESSAGE_ID (0x3U) @@ -624,6 +672,7 @@ typedef struct NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS { NV2080_CTRL_NVLINK_ERR_INFO linkErrInfo[NV2080_CTRL_NVLINK_MAX_LINKS]; NvU32 ioctrlMask; NV2080_CTRL_NVLINK_COMMON_ERR_INFO commonErrInfo[NV2080_CTRL_NVLINK_MAX_IOCTRLS]; + NvU8 ErrInfoFlags; } NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS; /* @@ -1340,100 +1389,8 @@ typedef struct NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS { NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_TYPE errorType; } NV2080_CTRL_NVLINK_INJECT_TLC_ERROR_PARAMS; -/* - * NV2080_CTRL_CMD_NVLINK_CHECK_BRIDGE - * - * This command returns the presence and data fields of an NVLink Bridge EEPROM. - * - * [in] linkId - * The NVLink ID to check for a bridge EEPROM - * [out] bPresent - * NV_TRUE if the EEPROM chip is detected. - * [out] bValid - * NV_TRUE if the the data read passes validity checks. If so, the following - * fields are populated. - * [out] firmwareVersion - * The firmware version formatted as PPPP.SSSS.BB, e.g. 4931.0200.01.01, - * padded with one or more 0x00 - * [out] bridgeVendor - * The bridge vendor name, padded with one or more 0x00 - * [out] boardPartNumber - * The board part number, formatted as CCC-FPPPP-SSSS-RRR - * (e.g. 699-24931-0200-000), padded with one or more 0x00 - * [out] boardRevision - * The board revision, e.g. A00, padded with one or more 0x00 - * [out] configuration - * Bridge form factor (2-way/3-way/4-way). - * See NV2080_CTRL_NVLINK_BRIDGE_CONFIGURATION_* - * [out] spacing - * # of slots spacing identifier. See NV2080_CTRL_NVLINK_BRIDGE_SPACING_* - * [out] interconnectType - * Type of interconnect. See NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_TYPE_* - * [out] interconnectWidth - * Width of interconnect NVHS lanes. - * See NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_WIDTH_* - * [out] maximumLandDataRate - * Maximum data transfer rate in T/s, as an IEEE-754 32-bit float - * [out] featureIllumination - * Illumination feature supported. - * See NV2080_CTRL_NVLINK_BRIDGE_ILLUMINATION_FEATURE_* - * [out] businessUnit - * Business unit identifier. - */ -#define NV2080_CTRL_CMD_NVLINK_CHECK_BRIDGE (0x20803010U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_CHECK_BRIDGE_PARAMS_MESSAGE_ID" */ - -// ASCII bytes plus space for null terminator -#define NV2080_CTRL_NVLINK_BRIDGE_FIRMWARE_VERSION_LENGTH (0x11U) /* finn: Evaluated from "(16 + 1)" */ -#define NV2080_CTRL_NVLINK_BRIDGE_VENDOR_LENGTH (0x15U) /* finn: Evaluated from "(20 + 1)" */ -#define NV2080_CTRL_NVLINK_BRIDGE_BOARD_PART_NUMBER_LENGTH (0x15U) /* finn: Evaluated from "(20 + 1)" */ -#define NV2080_CTRL_NVLINK_BRIDGE_BOARD_REVISION_LENGTH (0x4U) /* finn: Evaluated from "(3 + 1)" */ - - - -#define NV2080_CTRL_NVLINK_BRIDGE_CONFIGURATION_UNDEFINED (0x00U) -#define NV2080_CTRL_NVLINK_BRIDGE_CONFIGURATION_2_WAY (0x02U) -#define NV2080_CTRL_NVLINK_BRIDGE_CONFIGURATION_3_WAY (0x03U) -#define NV2080_CTRL_NVLINK_BRIDGE_CONFIGURATION_4_WAY (0x04U) - -#define NV2080_CTRL_NVLINK_BRIDGE_SPACING_UNDEFINED (0x00U) -#define NV2080_CTRL_NVLINK_BRIDGE_SPACING_2_SLOT (0x02U) -#define NV2080_CTRL_NVLINK_BRIDGE_SPACING_3_SLOT (0x03U) -#define NV2080_CTRL_NVLINK_BRIDGE_SPACING_4_SLOT (0x04U) - -#define NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_TYPE_UNDEFINED (0x00U) -#define NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_TYPE_NVLINK_2 (0x02U) -#define NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_TYPE_NVLINK_3 (0x03U) - -#define NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_WIDTH_UNDEFINED (0x00U) -#define NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_WIDTH_4_LANES (0x02U) -#define NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_WIDTH_8_LANES (0x03U) -#define NV2080_CTRL_NVLINK_BRIDGE_INTERCONNECT_WIDTH_16_LANES (0x04U) - -#define NV2080_CTRL_NVLINK_BRIDGE_ILLUMINATION_FEATURE_NONE (0x00U) -#define NV2080_CTRL_NVLINK_BRIDGE_ILLUMINATION_FEATURE_SINGLE_COLOR (0x01U) -#define NV2080_CTRL_NVLINK_BRIDGE_ILLUMINATION_FEATURE_RGB (0x02U) - -#define NV2080_CTRL_NVLINK_CHECK_BRIDGE_PARAMS_MESSAGE_ID (0x10U) - -typedef struct NV2080_CTRL_NVLINK_CHECK_BRIDGE_PARAMS { - NvU32 linkId; - NvBool bPresent; - NvBool bValid; - char firmwareVersion[NV2080_CTRL_NVLINK_BRIDGE_FIRMWARE_VERSION_LENGTH]; - char bridgeVendor[NV2080_CTRL_NVLINK_BRIDGE_VENDOR_LENGTH]; - char boardPartNumber[NV2080_CTRL_NVLINK_BRIDGE_BOARD_PART_NUMBER_LENGTH]; - char boardRevision[NV2080_CTRL_NVLINK_BRIDGE_BOARD_REVISION_LENGTH]; - NvU8 businessUnit; - NvU8 configuration; - NvU8 spacing; - NvU8 interconnectType; - NvU8 interconnectWidth; - NvF32 maximumLaneDataRate; - NvU8 featureIllumination; -} NV2080_CTRL_NVLINK_CHECK_BRIDGE_PARAMS; - /* * NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES * @@ -2309,10 +2266,17 @@ typedef struct NV2080_CTRL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS { #define NV2080_CTRL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS_MESSAGE_ID (0x25U) typedef struct NV2080_CTRL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS { - NvU32 linkId; - NvBool bConnected; NV_DECLARE_ALIGNED(NvU64 remoteDeviceType, 8); + NV_DECLARE_ALIGNED(NvU64 remoteChipSid, 8); + NvU32 linkId; + NvU32 laneRxdetStatusMask; NvU32 remoteLinkNumber; + NvU32 remotePciDeviceId; + NvU32 remoteDomain; + NvU8 remoteBus; + NvU8 remoteDevice; + NvU8 remoteFunction; + NvBool bConnected; } NV2080_CTRL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS; #define NV2080_CTRL_CMD_NVLINK_UPDATE_LINK_CONNECTION (0x20803025U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS_MESSAGE_ID" */ @@ -2883,6 +2847,81 @@ typedef struct NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS { NvU32 params; } NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS; -#define NV2080_CTRL_CMD_NVLINK_EOM_CONTROL (0x2080303c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_NVLINK_EOM_CONTROL (0x2080303c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID" */ + +/*! + * Inband Recieved Data + */ +#define NV2080_CTRL_NVLINK_INBAND_MAX_MSG_SIZE 4096 +#define NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_MESSAGE_ID (0x3dU) + +typedef struct NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS { + NvU8 data[NV2080_CTRL_NVLINK_INBAND_MAX_MSG_SIZE]; + NvU32 dataSize; +} NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS; + +#define NV2080_CTRL_NVLINK_L1_THRESHOLD_SET (0x00000000U) +#define NV2080_CTRL_NVLINK_L1_THRESHOLD_GET (0x00000001U) + +/* + * NV2080_CTRL_CMD_NVLINK_L1_THRESHOLD + * + * This command is used to get/set the L1 threshold value + * + * [in] flag + * Whether to set or get the L1 threshold value + * + * [in/out] l1Threshold + * Used to set or get the L1 threshold value + * + */ +#define NV2080_CTRL_NVLINK_L1_THRESHOLD_PARAMS_MESSAGE_ID (0x3eU) + +typedef struct NV2080_CTRL_NVLINK_L1_THRESHOLD_PARAMS { + NvU32 flag; + NvU32 l1Threshold; +} NV2080_CTRL_NVLINK_L1_THRESHOLD_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_L1_THRESHOLD (0x2080303eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_L1_THRESHOLD_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_INBAND_SEND_DATA + * + * RPC for sending Inband data + * + * [In] data[] + * data to be sent over inband + * [In] dataSize + * Size of valid data in data array + */ +#define NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS_MESSAGE_ID (0x3fU) + +typedef struct NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS { + NvU8 buffer[NV2080_CTRL_NVLINK_INBAND_MAX_MSG_SIZE]; + NvU32 dataSize; +} NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_INBAND_SEND_DATA (0x2080303fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_NVLINK_IS_GPU_DEGRADED + * + * RPC for Getting GPU degraded status upon link error + * + * [In] linkId + * Id of the link on which error occured + * [In] bIsGpuDegraded + * Boolean to track corresponding GPU is degraded or not + */ +#define NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_MESSAGE_ID (0x40U) + +typedef struct NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS { + NvU32 linkId; + NvBool bIsGpuDegraded; +} NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_IS_GPU_DEGRADED (0x20803040U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_MESSAGE_ID" */ + /* _ctrl2080nvlink_h_ */ + diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h index e5dbf055c..b12521dfd 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h @@ -72,7 +72,6 @@ * NV_ERR_INVALID_ARGUMENT */ - #define NV2080_CTRL_PERF_BOOST_FLAGS_CMD 1:0 #define NV2080_CTRL_PERF_BOOST_FLAGS_CMD_CLEAR (0x00000000) #define NV2080_CTRL_PERF_BOOST_FLAGS_CMD_BOOST_1LEVEL (0x00000001) @@ -86,6 +85,10 @@ #define NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_NO (0x00000000) #define NV2080_CTRL_PERF_BOOST_FLAGS_ASYNC_YES (0x00000001) +#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY 6:6 +#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY_DEFAULT (0x00000000) +#define NV2080_CTRL_PERF_BOOST_FLAGS_CUDA_PRIORITY_HIGH (0x00000001) + #define NV2080_CTRL_PERF_BOOST_DURATION_MAX 3600 //The duration can be specified up to 1 hour #define NV2080_CTRL_PERF_BOOST_DURATION_INFINITE 0xffffffff // If set this way, the boost will last until cleared. @@ -124,6 +127,76 @@ typedef struct NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS { NvBool bAcquire; } NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS; +/* + * NV2080_CTRL_PERF_POWERSTATE + * + * This structure describes power state information. + * + * powerState + * This parameter specifies the type of power source. + * Legal values for this parameter include: + * NV2080_CTRL_PERF_POWER_SOURCE_AC + * This values indicates that the power state is AC. + * NV2080_CTRL_PERF_POWER_SOURCE_BATTERY + * This values indicates that the power state is battery. + */ +#define NV2080_CTRL_PERF_POWER_SOURCE_AC (0x00000000) +#define NV2080_CTRL_PERF_POWER_SOURCE_BATTERY (0x00000001) + +typedef struct NV2080_CTRL_PERF_POWERSTATE_PARAMS { + NvU32 powerState; +} NV2080_CTRL_PERF_POWERSTATE_PARAMS; + +/* + * NV2080_CTRL_CMD_PERF_SET_POWERSTATE + * + * This command can be used to set the perf power state as AC or battery. + * + * powerStateInfo + * This parameter specifies the power source type to set. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_PERF_SET_POWERSTATE (0x2080205b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS_MESSAGE_ID (0x5BU) + +typedef struct NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS { + NV2080_CTRL_PERF_POWERSTATE_PARAMS powerStateInfo; +} NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS; + +/* + * NV2080_CTRL_CMD_PERF_SET_AUX_POWER_STATE + * + * This command allows the forcing of a performance level based on auxiliary + * power-states. + * + * powerState + * This parameter specifies the target auxiliary Power state. Legal aux + * power-states for this parameter are defined by the + * NV2080_CTRL_PERF_AUX_POWER_STATE_P* definitions that follow. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_PERF_SET_AUX_POWER_STATE (0x20802092) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS_MESSAGE_ID (0x92U) + +typedef struct NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS { + NvU32 powerState; +} NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS; + +#define NV2080_CTRL_PERF_AUX_POWER_STATE_P0 (0x00000000) +#define NV2080_CTRL_PERF_AUX_POWER_STATE_P1 (0x00000001) +#define NV2080_CTRL_PERF_AUX_POWER_STATE_P2 (0x00000002) +#define NV2080_CTRL_PERF_AUX_POWER_STATE_P3 (0x00000003) +#define NV2080_CTRL_PERF_AUX_POWER_STATE_P4 (0x00000004) +#define NV2080_CTRL_PERF_AUX_POWER_STATE_COUNT (0x00000005) + /*! * Enumeration of the RATED_TDP arbitration clients which make requests to force * enable/disable VF points above the RATED_TDP point. @@ -376,7 +449,7 @@ typedef NV2080_CTRL_GPUMON_SAMPLES NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMP /*! * Number of GPU monitoring sample in their respective buffers. */ -#define NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL 100 +#define NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL 72 #define NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_BUFFER_SIZE \ NV_SIZEOF32(NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE) * \ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmgr.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmgr.h index abbc4cf38..fa476b5dc 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmgr.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmgr.h @@ -30,3 +30,38 @@ // Source file: ctrl/ctrl2080/ctrl2080pmgr.finn // + + +#define NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_SUPPORTED 0U +#define NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_SUPPORTED 1U +#define NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_APPLICABLE 2U + +/*! + * NV2080_CTRL_PMGR_MODULE_INFO_PARAMS + * + * This provides information about different module properties + * + * moduleId[OUT] + * - This is a static HW identifier that is unique for each module on a given baseboard. + * For non-baseboard products this would always be 0. + * nvswitchSupport[OUT] + * - NVSwitch present or not. Possible values are + * NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_SUPPORTED + * NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_SUPPORTED + * NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_APPLICABLE + */ +#define NV2080_CTRL_PMGR_MODULE_INFO_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_PMGR_MODULE_INFO_PARAMS { + NvU32 moduleId; + NvU8 nvswitchSupport; +} NV2080_CTRL_PMGR_MODULE_INFO_PARAMS; + +/*! + * NV2080_CTRL_CMD_PMGR_GET_MODULE_INFO + * + * Control call to query the subdevice module INFO. + * + */ +#define NV2080_CTRL_CMD_PMGR_GET_MODULE_INFO (0x20802609) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PMGR_INTERFACE_ID << 8) | NV2080_CTRL_PMGR_MODULE_INFO_PARAMS_MESSAGE_ID" */ + diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h index 93b1113e1..e4995b8a6 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h new file mode 100644 index 000000000..2da2c8025 --- /dev/null +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h @@ -0,0 +1,407 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl2080/ctrl2080vgpumgrinternal.finn +// + +#include "ctrl/ctrl2080/ctrl2080base.h" +#include "ctrl/ctrla081.h" + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK + * + * This command is used to bootload GSP VGPU plugin task. + * Can be called only with SR-IOV and with VGPU_GSP_PLUGIN_OFFLOAD feature. + * + * dbdf - domain (31:16), bus (15:8), device (7:3), function (2:0) + * gfid - Gfid + * vgpuType - The Type ID for VGPU profile + * vmPid - Plugin process ID of vGPU guest instance + * swizzId - SwizzId + * numChannels - Number of channels + * numPluginChannels - Number of plugin channels + * bDisableSmcPartitionRestore - If set to true, SMC default execution partition + * save/restore will not be done in host-RM + * guestFbPhysAddrList - list of VMMU segment aligned physical address of guest FB memory + * guestFbLengthList - list of guest FB memory length in bytes + * pluginHeapMemoryPhysAddr - plugin heap memory offset + * pluginHeapMemoryLength - plugin heap memory length in bytes + * bDeviceProfilingEnabled - If set to true, profiling is allowed + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK (0x20804001) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_MAX_VMMU_SEGMENTS 384 + +/* Must match NV2080_ENGINE_TYPE_LAST from cl2080.h */ +#define NV2080_GPU_MAX_ENGINES 0x3e + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS { + NvU32 dbdf; + NvU32 gfid; + NvU32 vgpuType; + NvU32 vmPid; + NvU32 swizzId; + NvU32 numChannels; + NvU32 numPluginChannels; + NvU32 chidOffset[NV2080_GPU_MAX_ENGINES]; + NvBool bDisableDefaultSmcExecPartRestore; + NvU32 numGuestFbSegments; + NV_DECLARE_ALIGNED(NvU64 guestFbPhysAddrList[NV2080_CTRL_MAX_VMMU_SEGMENTS], 8); + NV_DECLARE_ALIGNED(NvU64 guestFbLengthList[NV2080_CTRL_MAX_VMMU_SEGMENTS], 8); + NV_DECLARE_ALIGNED(NvU64 pluginHeapMemoryPhysAddr, 8); + NV_DECLARE_ALIGNED(NvU64 pluginHeapMemoryLength, 8); + NV_DECLARE_ALIGNED(NvU64 ctrlBuffOffset, 8); + NvBool bDeviceProfilingEnabled; +} NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK + * + * This command is used to shutdown GSP VGPU plugin task. + * Can be called only with SR-IOV and with VGPU_GSP_PLUGIN_OFFLOAD feature. + * + * gfid - Gfid + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK (0x20804002) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS { + NvU32 gfid; +} NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE + * + * This command is used to add a new vGPU config to the pGPU in physical RM. + * Unlike NVA081_CTRL_CMD_VGPU_CONFIG_SET_INFO, it does no validation + * and is only to be used internally. + * + * discardVgpuTypes [IN] + * This parameter specifies if existing vGPU configuration should be + * discarded for given pGPU + * + * vgpuInfoCount [IN] + * This parameter specifies the number of entries of virtual GPU type +* information + * + * vgpuInfo [IN] + * This parameter specifies virtual GPU type information + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE (0x20804003) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS { + NvBool discardVgpuTypes; + NvU32 vgpuInfoCount; + NV_DECLARE_ALIGNED(NVA081_CTRL_VGPU_INFO vgpuInfo[NVA081_MAX_VGPU_TYPES_PER_PGPU], 8); +} NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS; + +/* + * NV2080_GUEST_VM_INFO + * + * This structure represents vGPU guest's (VM's) information + * + * vmPid [OUT] + * This param specifies the vGPU plugin process ID + * guestOs [OUT] + * This param specifies the vGPU guest OS type + * migrationProhibited [OUT] + * This flag indicates whether migration is prohibited for VM or not + * guestNegotiatedVgpuVersion [OUT] + * This param specifies the vGPU version of guest driver after negotiation + * frameRateLimit [OUT] + * This param specifies the current value of FRL set for guest + * licensed [OUT] + * This param specifies whether the VM is Unlicensed/Licensed + * licenseState [OUT] + * This param specifies the current state of the GRID license state machine + * licenseExpiryTimestamp [OUT] + * License expiry time in seconds since UNIX epoch + * licenseExpiryStatus [OUT] + * License expiry status + * guestDriverVersion [OUT] + * This param specifies the driver version of the driver installed on the VM + * guestDriverBranch [OUT] + * This param specifies the driver branch of the driver installed on the VM + * guestVmInfoState [OUT] + * This param stores the current state of guest dependent fields + * + */ +typedef struct NV2080_GUEST_VM_INFO { + NvU32 vmPid; + NvU32 guestOs; + NvU32 migrationProhibited; + NvU32 guestNegotiatedVgpuVersion; + NvU32 frameRateLimit; + NvBool licensed; + NvU32 licenseState; + NvU32 licenseExpiryTimestamp; + NvU8 licenseExpiryStatus; + NvU8 guestDriverVersion[NVA081_VGPU_STRING_BUFFER_SIZE]; + NvU8 guestDriverBranch[NVA081_VGPU_STRING_BUFFER_SIZE]; + GUEST_VM_INFO_STATE guestVmInfoState; +} NV2080_GUEST_VM_INFO; + +/* + * NV2080_GUEST_VGPU_DEVICE + * + * This structure represents host vgpu device's (assigned to VM) information + * + * gfid [OUT] + * This parameter specifies the gfid of vGPU assigned to VM. + * vgpuPciId [OUT] + * This parameter specifies vGPU PCI ID + * vgpuDeviceInstanceId [OUT] + * This paramter specifies the vGPU device instance per VM to be used for supporting + * multiple vGPUs per VM. + * fbUsed [OUT] + * This parameter specifies FB usage in bytes + * eccState [OUT] + * This parameter specifies the ECC state of the virtual GPU. + * One of NVA081_CTRL_ECC_STATE_xxx values. + * bDriverLoaded [OUT] + * This parameter specifies whether driver is loaded on this particular vGPU. + * + */ +typedef struct NV2080_HOST_VGPU_DEVICE { + NvU32 gfid; + NV_DECLARE_ALIGNED(NvU64 vgpuPciId, 8); + NvU32 vgpuDeviceInstanceId; + NV_DECLARE_ALIGNED(NvU64 fbUsed, 8); + NvU32 encoderCapacity; + NvU32 eccState; + NvBool bDriverLoaded; +} NV2080_HOST_VGPU_DEVICE; + +/* + * NV2080_VGPU_GUEST + * + * This structure represents a vGPU guest + * + */ +typedef struct NV2080_VGPU_GUEST { + NV2080_GUEST_VM_INFO guestVmInfo; + NV_DECLARE_ALIGNED(NV2080_HOST_VGPU_DEVICE vgpuDevice, 8); +} NV2080_VGPU_GUEST; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU + * + * This command enumerates list of vGPU guest instances per pGpu + * + * numVgpu [OUT] + * This parameter specifies the number of virtual GPUs created on this physical GPU + * + * vgpuGuest [OUT] + * This parameter specifies an array containing guest vgpu's information for + * all vGPUs created on this physical GPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU (0x20804004) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS { + NvU32 numVgpu; + NV_DECLARE_ALIGNED(NV2080_VGPU_GUEST vgpuGuest[NVA081_MAX_VGPU_PER_PGPU], 8); +} NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO + * + * This command is used clear guest vm info. It should be used when + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE + * is called with NVA081_NOTIFIERS_EVENT_VGPU_GUEST_DESTROYED state. + * + * gfid [IN] + * This parameter specifies the gfid of vGPU assigned to VM. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO (0x20804005) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS { + NvU32 gfid; +} NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE + * + * This command is used to get the FB usage of all vGPU instances running on a GPU. + * + * vgpuCount [OUT] + * This field specifies the number of vGPU devices for which FB usage is returned. + * vgpuFbUsage [OUT] + * This is an array of type NV2080_VGPU_FB_USAGE, which contains a list of vGPU gfid + * and their corresponding FB usage in bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE (0x20804006) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID" */ + +typedef struct NV2080_VGPU_FB_USAGE { + NvU32 gfid; + NV_DECLARE_ALIGNED(NvU64 fbUsed, 8); +} NV2080_VGPU_FB_USAGE; + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS { + NvU32 vgpuCount; + NV_DECLARE_ALIGNED(NV2080_VGPU_FB_USAGE vgpuFbUsage[NVA081_MAX_VGPU_PER_PGPU], 8); +} NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY + * + * This command is used to set vGPU instance's (represented by gfid) encoder Capacity. + * + * gfid [IN] + * This parameter specifies the gfid of vGPU assigned to VM. + * encoderCapacity [IN] + * Encoder capacity value from 0 to 100. Value of 0x00 indicates encoder performance + * may be minimal for this GPU and software should fall back to CPU-based encode. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY (0x20804007) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS { + NvU32 gfid; + NvU32 encoderCapacity; +} NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP + * + * This command is used to cleanup all the GSP VGPU plugin task allocated resources after its shutdown. + * Can be called only with SR-IOV and with VGPU_GSP_PLUGIN_OFFLOAD feature. + * + * gfid [IN] + * This parameter specifies the gfid of vGPU assigned to VM. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP (0x20804008) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS { + NvU32 gfid; +} NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS; + +#define NV2080_CTRL_MAX_NVU32_TO_CONVERTED_STR_LEN 8 +#define NV2080_CTRL_MAX_GPC_COUNT 32 + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING + * + * Reroutes kvgpumgrGetPgpuFSEncoding to vgpuMgrGetPgpuFSEncoding. + * + * pgpuString [OUT] + * Resulting PGPU string + * pgpuStringSize + * PGPU string size + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING (0x20804009) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS { + NvU8 pgpuString[NVA081_PGPU_METADATA_STRING_SIZE]; + NvU32 pgpuStringSize; +} NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT + * + * Reroutes kvgpumgrCheckPgpuMigrationSupport to vgpuMgrCheckPgpuMigrationSupport. + * + * bIsMigrationSupported [OUT] + * Resulting status of the migration support + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT (0x2080400a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS { + NvBool bIsMigrationSupported; +} NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS; + +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG + * + * Sets vgpu manager parameters. This control is used after GSP initialization. + * + * bSupportHeterogeneousTimeSlicedVgpuTypes [IN] + * Enable/disable heterogeneous time-sliced vgpu types + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG (0x2080400b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS { + NvBool bSupportHeterogeneousTimeSlicedVgpuTypes; +} NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS; + +/* _ctrl2080vgpumgrinternal_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffb.h b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffb.h index b024c6a49..ec1691612 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffb.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffb.h @@ -344,6 +344,9 @@ typedef struct NV208F_CTRL_CMD_FB_ECC_GET_FORWARD_MAP_ADDRESS_PARAMS { * * address * The physical DRAM address to be targeted by the kill pointer + * + * bProdInjection + * Whether the kill pointer is set through the production injection flow or not */ #define NV208F_CTRL_CMD_FB_ECC_SET_KILL_PTR (0x208f050e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_ECC_SET_KILL_PTR_PARAMS_MESSAGE_ID" */ @@ -358,6 +361,7 @@ typedef enum NV208F_CTRL_FB_ERROR_TYPE { typedef struct NV208F_CTRL_FB_ECC_SET_KILL_PTR_PARAMS { NV208F_CTRL_FB_ERROR_TYPE errorType; NV_DECLARE_ALIGNED(NvU64 address, 8); + NvBool bProdInjection; } NV208F_CTRL_FB_ECC_SET_KILL_PTR_PARAMS; @@ -583,4 +587,25 @@ typedef struct NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS { NvU32 sourceMask; } NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS; +/* + * NV208F_CTRL_CMD_FB_GET_FLOORSWEPT_FBPA_MASK + * + * This command calculates the floorswept fbpa mask by taking 1/2 HBM + * floorsweeping into account + * + * fbpaMask + * This value of the mask. + * + * Possbile status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NV208F_CTRL_CMD_FB_GET_FLOORSWEPT_FBPA_MASK (0x208f0516) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_GET_FLOORSWEPT_FBPA_MASK_PARAMS_MESSAGE_ID" */ + +#define NV208F_CTRL_FB_GET_FLOORSWEPT_FBPA_MASK_PARAMS_MESSAGE_ID (0x16U) + +typedef struct NV208F_CTRL_FB_GET_FLOORSWEPT_FBPA_MASK_PARAMS { + NvU32 fbpaMask; +} NV208F_CTRL_FB_GET_FLOORSWEPT_FBPA_MASK_PARAMS; + /* _ctrl208ffb_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgpu.h b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgpu.h index 3dc607e56..d473f1137 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgpu.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgpu.h @@ -82,7 +82,7 @@ typedef struct NV208F_CTRL_GPU_RAM_SVOP_VALUES_PARAMS { * NV_ERR_INVALID_ARGUMENT */ -#define NV208F_CTRL_CMD_GPU_SET_RAM_SVOP_VALUES (0x208f1102) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID << 8) | 0x2" */ +#define NV208F_CTRL_CMD_GPU_SET_RAM_SVOP_VALUES (0x208f1102) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GPU_INTERFACE_ID << 8) | 0x2" */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h index 77aeb17dd..2b298e6fb 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h @@ -41,10 +41,10 @@ * Parameters: * * location - * Only used for HSHUB. + * Only used for HSHUBMMU. * * sublocation - * Only used for HSHUB. + * Only used for HSHUBMMU. * * unit * Specifies the MMU HW unit where the injection will occur. @@ -93,7 +93,7 @@ typedef struct NV208F_CTRL_MMU_ECC_INJECT_ERROR_PARAMS { * NV_ERR_NOT_SUPPORTED otherwise * */ -#define NV208F_CTRL_CMD_MMU_ECC_INJECTION_SUPPORTED (0x208f0b02) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_MMU_INTERFACE_ID << 8) | NV208F_CTRL_MMU_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID" */ +#define NV208F_CTRL_CMD_MMU_ECC_INJECTION_SUPPORTED (0x208f0b02) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_MMU_INTERFACE_ID << 8) | NV208F_CTRL_MMU_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070rg.h b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070rg.h index f5dacc305..64269d8c1 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070rg.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070rg.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -88,8 +88,19 @@ typedef struct NV5070_CTRL_CMD_GET_RG_STATUS_PARAMS { * _SET_RG_: Whether to enable or disable RG underflow reporting. * _GET_RG_: Whether or not RG underflow reporting is enabled. * underflow - * _SET_RG_: Clear underflow (TRUE) or leave it alone (FALSE). - * _GET_RG_: RG underflow underflowed (TRUE) or not underflowed (FALSE). + * _SET_RG_: Clear underflow (CLEAR_UNDERFLOW_YES) or leave it alone + * (CLEAR_UNDERFLOW_NO). + * Note: The GET_RG function automatically clears the underflow. + * It is recommended that GET_RG be used to clear any initial + * underflows, and that the "underflow" field be set to + * CLEAR_UNDERFLOW_NO in any SET_RG calls. This field may be + * deprecated in the future, for SET_RG calls. + * _GET_RG_: UNDERFLOWED_YES if an RG underflow occurred since the most + * recent prior call to to NV5070_CTRL_CMD_GET_RG_STATUS. + * epfifoUnderflow + * _SET_RG_: Not used. + * _GET_RG_: EPFIFO_UNDERFLOWED_YES if an EPFIFO underflow occurred since + * the most recent prior call to NV5070_CTRL_CMD_GET_RG_STATUS. * mode * _SET_RG_: What mode to use when underflow occurs. This is * independent from enable field. This is always active. @@ -100,19 +111,22 @@ typedef struct NV5070_CTRL_CMD_UNDERFLOW_PARAMS { NvU32 head; NvU32 enable; NvU32 underflow; + NvU32 epfifoUnderflow; NvU32 mode; } NV5070_CTRL_CMD_UNDERFLOW_PARAMS; -#define NV5070_CTRL_CMD_UNDERFLOW_PROP_ENABLED_NO (0x00000000) -#define NV5070_CTRL_CMD_UNDERFLOW_PROP_ENABLED_YES (0x00000001) -#define NV5070_CTRL_CMD_UNDERFLOW_PROP_UNDERFLOWED_NO (0x00000000) -#define NV5070_CTRL_CMD_UNDERFLOW_PROP_UNDERFLOWED_YES (0x00000001) -#define NV5070_CTRL_CMD_UNDERFLOW_PROP_MODE_REPEAT (0x00000000) -#define NV5070_CTRL_CMD_UNDERFLOW_PROP_MODE_RED (0x00000001) -#define NV5070_CTRL_CMD_UNDERFLOW_PROP_ENABLE_NO (0x00000000) -#define NV5070_CTRL_CMD_UNDERFLOW_PROP_ENABLE_YES (0x00000001) -#define NV5070_CTRL_CMD_UNDERFLOW_PROP_CLEAR_UNDERFLOW_NO (0x00000000) -#define NV5070_CTRL_CMD_UNDERFLOW_PROP_CLEAR_UNDERFLOW_YES (0x00000001) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_ENABLED_NO (0x00000000) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_ENABLED_YES (0x00000001) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_UNDERFLOWED_NO (0x00000000) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_UNDERFLOWED_YES (0x00000001) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_EPFIFO_UNDERFLOWED_NO (0x00000000) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_EPFIFO_UNDERFLOWED_YES (0x00000001) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_MODE_REPEAT (0x00000000) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_MODE_RED (0x00000001) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_ENABLE_NO (0x00000000) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_ENABLE_YES (0x00000001) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_CLEAR_UNDERFLOW_NO (0x00000000) +#define NV5070_CTRL_CMD_UNDERFLOW_PROP_CLEAR_UNDERFLOW_YES (0x00000001) /* * NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP @@ -129,7 +143,7 @@ typedef struct NV5070_CTRL_CMD_UNDERFLOW_PARAMS { * NV_ERR_INVALID_ARGUMENT * NV_ERR_GENERIC */ -#define NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP (0x50700203) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP_PARAMS_MESSAGE_ID" */ +#define NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP (0x50700203) /* finn: Evaluated from "(FINN_NV50_DISPLAY_RG_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP_PARAMS_MESSAGE_ID" */ #define NV5070_CTRL_CMD_GET_RG_UNDERFLOW_PROP_PARAMS_MESSAGE_ID (0x3U) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl83de/ctrl83dedebug.h b/src/common/sdk/nvidia/inc/ctrl/ctrl83de/ctrl83dedebug.h index 746fc0698..c4c36b0ca 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl83de/ctrl83dedebug.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl83de/ctrl83dedebug.h @@ -1068,5 +1068,39 @@ typedef struct NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS { NV_DECLARE_ALIGNED(NV83DE_CTRL_DEBUG_ACCESS_MEMORY_ENTRY entries[MAX_ACCESS_MEMORY_OPS], 8); } NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS; +/* + * NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY + * + * faultAddress (OUT) + * Faulting address + * faultType (OUT) + * Type of MMU fault + * accessType (OUT) + * Type of access that caused this fault + */ +#define NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_MAX_ENTRIES 4 +typedef struct NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY { + NV_DECLARE_ALIGNED(NvU64 faultAddress, 8); + NvU32 faultType; + NvU32 accessType; +} NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY; + +/* + * NV83DE_CTRL_CMD_DEBUG_READ_MMU_FAULT_INFO + * + * mmuFaultInfoList (OUT) + * Entries of MMU faults recorded for the attached context. The cached data is only cleared via LRU policy when new MMU faults arrive so repeat data may be returned by this command. + * count (OUT) + * Number of MMU fault entries contain valid data. + */ +#define NV83DE_CTRL_CMD_DEBUG_READ_MMU_FAULT_INFO (0x83de0328) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS_MESSAGE_ID" */ + +#define NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS_MESSAGE_ID (0x28U) + +typedef struct NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS { + NV_DECLARE_ALIGNED(NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY mmuFaultInfoList[NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_MAX_ENTRIES], 8); + NvU32 count; +} NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS; + /* _ctrl83dedebug_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl90f1.h b/src/common/sdk/nvidia/inc/ctrl/ctrl90f1.h index d63ae9db7..20d94dd1e 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl90f1.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl90f1.h @@ -33,19 +33,19 @@ #include "ctrl/ctrlxxxx.h" #include "mmu_fmt_types.h" -#define GMMU_FMT_MAX_LEVELS 6 +#define GMMU_FMT_MAX_LEVELS 6U /* Fermi+ GPU VASpace control commands and parameters */ #define NV90F1_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x90F1, NV90F1_CTRL_##cat, idx) /* Command categories (6bits) */ -#define NV90F1_CTRL_RESERVED (0x00) -#define NV90F1_CTRL_VASPACE (0x01) +#define NV90F1_CTRL_RESERVED (0x00U) +#define NV90F1_CTRL_VASPACE (0x01U) /*! * Does nothing. */ -#define NV90F1_CTRL_CMD_NULL (0x90f10000) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_RESERVED_INTERFACE_ID << 8) | 0x0" */ +#define NV90F1_CTRL_CMD_NULL (0x90f10000U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_RESERVED_INTERFACE_ID << 8) | 0x0" */ @@ -54,7 +54,7 @@ /*! * Get VAS GPU MMU format. */ -#define NV90F1_CTRL_CMD_VASPACE_GET_GMMU_FORMAT (0x90f10101) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS_MESSAGE_ID" */ +#define NV90F1_CTRL_CMD_VASPACE_GET_GMMU_FORMAT (0x90f10101U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS_MESSAGE_ID" */ #define NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS_MESSAGE_ID (0x1U) @@ -81,7 +81,7 @@ typedef struct NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS { /*! * Get VAS page level information. */ -#define NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO (0x90f10102) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | 0x2" */ +#define NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO (0x90f10102U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | 0x2" */ typedef struct NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS { /*! @@ -151,7 +151,7 @@ typedef struct NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS { * A particular VA range and level (page size) combination may only be * locked down once at a given time, but each level is independent. */ -#define NV90F1_CTRL_CMD_VASPACE_RESERVE_ENTRIES (0x90f10103) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_MESSAGE_ID" */ +#define NV90F1_CTRL_CMD_VASPACE_RESERVE_ENTRIES (0x90f10103U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_MESSAGE_ID" */ #define NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_MESSAGE_ID (0x3U) @@ -192,7 +192,7 @@ typedef struct NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS { * a given level of the MMU format that has been reserved through a call to * @ref NV90F1_CTRL_CMD_VASPACE_RESERVE_ENTRIES. Also referred to as "unlock". */ -#define NV90F1_CTRL_CMD_VASPACE_RELEASE_ENTRIES (0x90f10104) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS_MESSAGE_ID" */ +#define NV90F1_CTRL_CMD_VASPACE_RELEASE_ENTRIES (0x90f10104U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS_MESSAGE_ID" */ #define NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS_MESSAGE_ID (0x4U) @@ -232,7 +232,7 @@ typedef struct NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS { * Get VAS page level information without kernel priviledge. This will internally call * NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO. */ -#define NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO_VERIF (0x90f10105) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | 0x5" */ +#define NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO_VERIF (0x90f10105U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | 0x5" */ /*! * Pin PDEs for a given VA range on the server RM and then mirror the client's page @@ -240,7 +240,7 @@ typedef struct NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS { * * @ref */ -#define NV90F1_CTRL_CMD_VASPACE_COPY_SERVER_RESERVED_PDES (0x90f10106) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_MESSAGE_ID" */ +#define NV90F1_CTRL_CMD_VASPACE_COPY_SERVER_RESERVED_PDES (0x90f10106U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_MESSAGE_ID" */ #define NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_MESSAGE_ID (0x6U) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla080.h b/src/common/sdk/nvidia/inc/ctrl/ctrla080.h new file mode 100644 index 000000000..ead7f53dc --- /dev/null +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla080.h @@ -0,0 +1,652 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla080.finn +// + + + + + +/* + * NVA080_CTRL_CMD_VGPU_DISPLAY_SET_SURFACE_PROPERTIES + * + * This command sets primary surface properties on a virtual GPU in displayless mode + * + * Parameters: + * headIndex + * This parameter specifies the head for which surface properties are + * + * isPrimary + * This parameter indicates whether surface information is for primary surface. set to 1 if its a primary surface. + * + * hMemory + * Memory handle containing the surface (only for RM-managed heaps) + * + * offset + * Offset from base of allocation (hMemory for RM-managed heaps; physical + * memory otherwise) + * + * surfaceType + * This parameter indicates whether surface type is block linear or pitch + * + * surfaceBlockHeight + * This parameter indicates block height for the surface + * + * surfacePitch + * This parameter indicates pitch value for the surface + * + * surfaceFormat + * This parameter indicates surface format (A8R8G8B8/A1R5G5B5) + * + * surfaceWidth + * This parameter indicates width value for the surface + * + * surfaceHeight + * This parameter indicates height value for the surface + * + * surfaceSize + * This parameter indicates size of the surface + * + * surfaceKind + * This parameter indicates surface kind (only for externally-managed + * heaps) + * + * rectX [unused] + * This parameter indicates X coordinate of the region to be displayed + * + * rectY [unused] + * This parameter indicates Y coordinate of the region to be displayed + * + * rectWidth + * This parameter indicates width of the region to be displayed + * + * rectHeight + * This parameter indicates height of the region to be displayed + * + * hHwResDevice + * This parameter indicates the device associated with surface + * + * hHwResHandle + * This parameter indicates the handle to hardware resources allocated to surface + * + * effectiveFbPageSize + * This parameter indicates the actual page size used by KMD for the surface + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NVOS_STATUS_NOT_SUPPORTED + */ + +#define NVA080_CTRL_CMD_VGPU_DISPLAY_SET_SURFACE_PROPERTIES (0xa0800103) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MESSAGE_ID" */ + +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MESSAGE_ID (0x3U) + +typedef struct NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES { + NvU32 headIndex; + NvU32 isPrimary; + NvU32 hMemory; + NvU32 offset; + NvU32 surfaceType; + NvU32 surfaceBlockHeight; + NvU32 surfacePitch; + NvU32 surfaceFormat; + NvU32 surfaceWidth; + NvU32 surfaceHeight; + NvU32 rectX; + NvU32 rectY; + NvU32 rectWidth; + NvU32 rectHeight; + NvU32 surfaceSize; + NvU32 surfaceKind; + NvU32 hHwResDevice; + NvU32 hHwResHandle; + NvU32 effectiveFbPageSize; +} NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES; + +/* valid surfaceType values */ +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MEMORY_LAYOUT 0:0 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_MEMORY_LAYOUT_PITCH 0x00000001 +/* valid surfaceBlockHeight values */ +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_ONE_GOB 0x00000000 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_TWO_GOBS 0x00000001 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_BLOCK_HEIGHT_THIRTYTWO_GOBS 0x00000005 +/* valid surfaceFormat values */ +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_I8 0x0000001E +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_RF16_GF16_BF16_AF16 0x000000CA +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_A8R8G8B8 0x000000CF +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_A2B10G10R10 0x000000D1 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_X2BL10GL10RL10_XRBIAS 0x00000022 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_A8B8G8R8 0x000000D5 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_R5G6B5 0x000000E8 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_A1R5G5B5 0x000000E9 +#define NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_FORMAT_R16_G16_B16_A16 0x000000C6 + +/* + * NVA080_CTRL_CMD_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS + * + * This command clears surface information related to head. + * It should be called while shutting down head in displayless mode on virtual GPU + * + * Parameters: + * headIndex + * This parameter specifies the head for which cleanup is requested. + * + * blankingEnabled + * This parameter must be set to 1 to enable blanking. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NVOS_STATUS_NOT_SUPPORTED + */ +#define NVA080_CTRL_CMD_VGPU_DISPLAY_CLEANUP_SURFACE (0xa0800104) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_MESSAGE_ID" */ + +#define NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS { + NvU32 headIndex; + NvU32 blankingEnabled; +} NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS; + +/* + * NVA080_CTRL_CMD_VGPU_DISPLAY_GET_POINTER_ADDRESS + * + * This command returns CPU virtual address of the mouse pointer mapping for VGPU. + * The address returned by this command is the pointer address for the head 0. + * VGPU_POINTER_OFFSET_HEAD(i) should be added to this address to get the address of head i. + * VGPU mouse pointer is a 32 bit value, X location of the mouse pointer is stored in + * 15:0 and Y location is stored in 31:16 bits. X location value of the mouse pointer is + * negative if bit 15 is set. Similarly, Y location value is negative if bit 31 is set. + * + * Parameters: + * pPointerAddress + * CPU virtual address of the mouse pointer mapping for VGPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NVOS_STATUS_NOT_SUPPORTED + */ + +#define NVA080_CTRL_CMD_VGPU_DISPLAY_GET_POINTER_ADDRESS (0xa0800105) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_DISPLAY_GET_POINTER_ADDRESS_PARAMS_MESSAGE_ID" */ + +#define NVA080_CTRL_VGPU_DISPLAY_GET_POINTER_ADDRESS_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NVA080_CTRL_VGPU_DISPLAY_GET_POINTER_ADDRESS_PARAMS { + NV_DECLARE_ALIGNED(NvP64 pPointerAddress, 8); +} NVA080_CTRL_VGPU_DISPLAY_GET_POINTER_ADDRESS_PARAMS; + +#define VGPU_POINTER_OFFSET_HEAD0_VALUE 0x00000000 +#define VGPU_POINTER_OFFSET_HEAD0_FLAG 0x00000004 +#define VGPU_POINTER_OFFSET_HEAD1_VALUE 0x00000008 +#define VGPU_POINTER_OFFSET_HEAD1_FLAG 0x0000000c +#define VGPU_POINTER_OFFSET_HEAD2_VALUE 0x00000010 +#define VGPU_POINTER_OFFSET_HEAD2_FLAG 0x00000014 +#define VGPU_POINTER_OFFSET_HEAD3_VALUE 0x00000018 +#define VGPU_POINTER_OFFSET_HEAD3_FLAG 0x0000001c +#define VGPU_POINTER_OFFSET_HEAD_VALUE(i) (i * 8) +#define VGPU_POINTER_OFFSET_HEAD_FLAG(i) (4 + i * 8) +#define VGPU_POINTER_OFFSET_HEAD_SIZE 4 + +/* + * NVA080_CTRL_CMD_GET_MAPPABLE_VIDEO_SIZE + * + * This command returns mappable video size to be used by each VM. + * + * Parameters: + * mappableVideoSize + * This parameter returns mappable video size in bytes. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NVOS_STATUS_NOT_SUPPORTED + */ + + +#define NV_VGPU_POINTER_X_LOCATION 15:0 +#define NV_VGPU_POINTER_Y_LOCATION 31:16 +#define NVA080_CTRL_CMD_GET_MAPPABLE_VIDEO_SIZE (0xa0800201) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS_MESSAGE_ID" */ + +#define NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 mappableVideoSize, 8); +} NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS; + +/* + * NVA080_CTRL_CMD_MAP_SEMA_MEM + * + * This command returns GPU VA for the channel with 'hCtxDma' handle + * where per VM semaphore memory is mapped which is used for tracking + * non-stall interrupt of each VM. + * + * Parameters: + * hClient [in] + * This parameter specifies the handle to the NV01_ROOT object of + * the client. This object should be the parent of the object + * specified by hDevice. + * hDevice [in] + * This parameter specifies the handle of the NV01_DEVICE object + * representing the desired GPU. + * hMemory [in] + * This parameter specifies the handle for semaphore memory + * hCtxDma [in] + * This parameter specifies the handle of the NV01_CONTEXT_DMA + * object through which bufferId is written in semaphore memory for + * non-stall interrupt tracking. + * semaAddress [out] + * This parameter returns the GPU virtual address of the semaphore + * memory. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_INVALID_DATA + * NV_ERR_INVALID_CLIENT + * NV_ERR_INVALID_OBJECT_HANDLE + * + */ + +#define NVA080_CTRL_CMD_MAP_SEMA_MEM (0xa0800202) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | 0x2" */ + +typedef struct NVA080_CTRL_MAP_SEMA_MEM_PARAMS { + NvHandle hClient; + NvHandle hDevice; + NvHandle hMemory; + NvHandle hCtxDma; + NV_DECLARE_ALIGNED(NvU64 semaAddress, 8); +} NVA080_CTRL_MAP_SEMA_MEM_PARAMS; + +/* + * NVA080_CTRL_CMD_UNMAP_SEMA_MEM + * + * This command unmaps per VM semaphore memory from GPU VA space, mapped by + * NVA080_CTRL_CMD_MAP_SEMA_MEM command. + * + * Parameters: + * Same as NVA080_CTRL_MAP_SEMA_MEM_PARAMS, except semaAddress is input + * parameter here. + * + * Possible status values returned are: + * NV_OK + * NVOS_STATUS_INVALID_DATA + * NV_ERR_INVALID_CLIENT + * NV_ERR_INVALID_OBJECT_HANDLE + * + */ + +#define NVA080_CTRL_CMD_UNMAP_SEMA_MEM (0xa0800203) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | 0x3" */ + +/*! + * NVA080_CTRL_CMD_SET_FB_USAGE + * + * This command sets the current framebuffer usage value in the plugin. + * + * Parameters: + * fbUsed [in] + * This parameter holds the current FB usage value in bytes. + * + * Possible status values returned are: + * NV_OK + */ +#define NVA080_CTRL_CMD_SET_FB_USAGE (0xa0800204) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_SET_FB_USAGE_PARAMS_MESSAGE_ID" */ + +#define NVA080_CTRL_SET_FB_USAGE_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVA080_CTRL_SET_FB_USAGE_PARAMS { + NV_DECLARE_ALIGNED(NvU64 fbUsed, 8); +} NVA080_CTRL_SET_FB_USAGE_PARAMS; + +/*! +* NVA080_CTRL_CMD_MAP_PER_ENGINE_SEMA_MEM +* +* This command allocates the per engine vGPU semaphore memory and map it to +* GPU/CPU VA. +* +* Calculate engine's semaphore GPU VA = +* semaAddress + semaStride * NV2080_ENGINE_TYPE_ of that engine +* +* Parameters: +* hClient [in] +* This parameter specifies the handle to the NV01_ROOT object of +* the client. This object should be the parent of the object +* specified by hDevice. +* hDevice [in] +* This parameter specifies the handle of the NV01_DEVICE object +* representing the desired GPU. +* hMemory [in] +* This parameter specifies the handle for semaphore memory +* hCtxDma [in] +* This parameter specifies the handle of the NV01_CONTEXT_DMA +* object through which bufferId is written in semaphore memory for +* non-stall interrupt tracking. +* semaAddress [out] +* This parameter returns the GPU VA of the per engine semaphore memory. +* semaStride [out] +* This parameter specifies the stride of each engine's semaphore offset within this memory. +* +* Possible status values returned are: +* NV_OK +*/ + +#define NVA080_CTRL_CMD_MAP_PER_ENGINE_SEMA_MEM (0xa0800205) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID" */ + +#define NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS { + NvU32 hClient; + NvU32 hDevice; + NvHandle hMemory; + NvU32 hCtxDma; + NV_DECLARE_ALIGNED(NvU64 semaAddress, 8); + NvU32 semaStride; +} NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS; + +/*! +* NVA080_CTRL_CMD_UNMAP_PER_ENGINE_SEMA_MEM +* +* This command unmaps and frees the per engine vGPU semaphore memory. +* +* Parameters: +* Same as NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS, except semaAddress is input +* parameter here. +* +* Possible status values returned are: +* NV_OK +*/ + +#define NVA080_CTRL_CMD_UNMAP_PER_ENGINE_SEMA_MEM (0xa0800206) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_UNMAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID" */ + +#define NVA080_CTRL_UNMAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID (0x6U) + +typedef NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS NVA080_CTRL_UNMAP_PER_ENGINE_SEMA_MEM_PARAMS; + +/* + * NVA080_CTRL_CMD_UPDATE_SYSMEM_BITMAP + * + * This command provides the guest RM with PFN information, so that it can + * update the shared memory with the plugin, which keeps track of guest sysmem. + * + * Parameters: + * destPhysAddr + * Start address of the segment to be tracked + * + * pageCount + * Number of pages in the segment + * + * pageSize + * Size of pages in the segment + * + * isValid: + * TRUE : Set bits corresponding to PFNs in bitmap and increase segment refcount + * FALSE: Decrease segment refcount and then unset bits if refcount is 0 + * + * pfnList + * List of PFNs in the segment + * + * flags + * FLAGS_DST_PHYS_ADDR_BAR1_OFFSET + * Flag set to TRUE if pteMem is CPU VA pointing to BAR1 and + * dstPhysAddr contains BAR1 offset. + * + * Possible status values returned are: + * NVOS_STATUS_SUCCESS + */ + +#define NVA080_CTRL_CMD_UPDATE_SYSMEM_BITMAP (0xa0800207) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_MESSAGE_ID" */ + +#define NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_FLAGS_DST_PHYS_ADDR_BAR1_OFFSET 0:0 +#define NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_FLAGS_DST_PHYS_ADDR_BAR1_OFFSET_FALSE (0x00000000) +#define NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_FLAGS_DST_PHYS_ADDR_BAR1_OFFSET_TRUE (0x00000001) + +#define NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS { + NV_DECLARE_ALIGNED(NvU64 destPhysAddr, 8); + NvU32 pageCount; + NvU32 pageSize; + NvBool isValid; + NV_DECLARE_ALIGNED(NvP64 pfnList, 8); + NvU32 flags; +} NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS; + +/* + * Blit semaphore offset location + */ +#define VGPU_BLIT_RESTORE_SEMA_MEM_OFFSET 0x200 +#define VGPU_BLIT_RESTORE_SEMA_MEM_ADDR(addr) (((NvU64)addr) + VGPU_BLIT_RESTORE_SEMA_MEM_OFFSET) + +#define VGPU_BLIT_SEMA_MEM_OFFSET 0x400 +#define VGPU_BLIT_SEMA_MEM_ADDR(addr) (((NvU64)addr) + VGPU_BLIT_SEMA_MEM_OFFSET) + +#define VGPU_FBMEMCE_PUSH_SEMA_MEM_OFFSET 0x800 +#define VGPU_FBMEMCE_PUSH_SEMA_MEM_ADDR(addr) (((NvU64)addr) + VGPU_FBMEMCE_PUSH_SEMA_MEM_OFFSET) + +#define VGPU_FBMEMCE_SEMA_MEM_OFFSET 0x810 +#define VGPU_FBMEMCE_SEMA_MEM_ADDR(addr) (((NvU64)addr) + VGPU_FBMEMCE_SEMA_MEM_OFFSET) + +#define VGPU_FBMEMCE_PIPELINED_SEMA_MEM_LOWER_OFFSET 0x820 +#define VGPU_FBMEMCE_PIPELINED_SEMA_MEM_LOWER_ADDR(addr) (((NvU64)addr) + VGPU_FBMEMCE_PIPELINED_SEMA_MEM_LOWER_OFFSET) + +#define VGPU_FBMEMCE_PIPELINED_SEMA_MEM_UPPER_OFFSET 0x824 + +/* + * NVA080_CTRL_CMD_VGPU_GET_CONFIG + * + * This command returns VGPU configuration information for the associated GPU. + * + * Parameters: + * frameRateLimiter + * This parameter returns value of frame rate limiter + * swVSyncEnabled + * This parameter returns value of SW VSync flag (zero for disabled, + * non-zero for enabled) + * cudaEnabled + * This parameter returns whether CUDA is enabled or not + * pluginPteBlitEnabled + * This parameter returns whether to use plugin pte blit path + * disableWddm1xPreemption + * This parameter returns whether to disable WDDM 1.x Preemption or not + * debugBuffer + * This parameter specifies a pointer to memory which is filled with + * debugging information. + * debugBufferSize + * This parameter specifies the size of the debugging buffer in bytes. + * guestFbOffset + * This parameter returns FB offset start address for VM + * mappableCpuHostAperture + * This parameter returns mappable CPU host aperture size + * linuxInterruptOptimization + * This parameter returns whether stall interrupts are enabled/disabled for + * Linux VM + * vgpuDeviceCapsBits + * This parameter specifies CAP bits to ON/OFF features from guest OS. + * CAPS_SW_VSYNC_ENABLED + * cap bit to indicate if SW VSync flag enabled/disabled. + * Please note, currently, guest doesn't honour this bit. + * CAPS_CUDA_ENABLED + * cap bit to indicate if CUDA enabled/disabled. + * Please note, currently, guest doesn't honour this bit. + * CAPS_WDDM1_PREEMPTION_DISABLED + * cap bit to indicate if WDDM 1.x Preemption disabled/enabled. + * Please note, currently, guest doesn't honour this bit. + * CAPS_LINUX_INTERRUPT_OPTIMIZATION_ENABLED + * cap bit to indicate if stall interrupts are enabled/disabled for + * Linux VM. Please note, currently, guest doesn't honour this bit. + * CAPS_PTE_BLIT_ENABLED + * cap bit to indicate if PTE blit is enabled/disabled. + * Please note, currently, guest doesn't honour this bit. + * CAPS_PDE_BLIT_ENABLED + * cap bit to indicate if PDE blit is enabled/disabled. + * CAPS_GET_PDE_INFO_CTRL_DISABLED + * cap bit to indicate if GET_PDE_INFO RM Ctrl is disabled/enabled. + * CAPS_GUEST_FB_OFFSET_DISABLED + * cap bit to indicate if FB Offset is exposed to guest or not. + * If set, FB Offset is not exposed to guest. + * CAPS_CILP_DISABLED_ON_WDDM + * cap bit to indicate if CILP on WDDM disabled/enabled. + * CAPS_UPDATE_DOORBELL_TOKEN_ENABLED + * cap bit to indicate if guest needs to use doorbell token value updated + * dynamically by host after migration. + * CAPS_SRIOV_ENABLED + * Cap bit to indicate if the vGPU is running in SRIOV mode or not. + * CAPS_GUEST_MANAGED_VA_ENABLED + * Cap bit to indicate if the Guest is managing the VA. + * CAPS_VGPU_1TO1_COMPTAG_ENABLED + * Cap bit to indicate if the 1to1 comptag enabled. This is always TRUE + * when SR-IOV is enabled. + * CAPS_MBP_ENABLED + * Cap bit to indicate if the Mid Buffer Preemption enabled. + * CAPS_ASYNC_MBP_ENABLED + * Cap bit to indicate if the asynchronus Mid buffer Preemption enabled. + * CAPS_TLB_INVALIDATE_ENABLED + * Cap bit to indicate if the vGPU supports TLB Invalidation operation or not. + * CAPS_PTE_BLIT_FOR_BAR1_PT_UPDATE_ENABLED + * Cap bit to indicate if the vGPU supports PTE blit for page table updates using BAR1 + * CAPS_SRIOV_HEAVY_ENABLED + * Cap bit to indicate if vGPU is running in SRIOV Heavy mode or not. + * When set true SRIOV Heavy is enabled. + * When set false and CAPS_SRIOV_ENABLED is set true, SRIOV Standard is enabled. + * CAPS_TIMESLICE_OVERRIDE_ENABLED + * Cap bit to indicate whether TSG timeslice override is enabled or not. + * When set true, TSG timeslice override is enabled. + * When false, TSG timeslice override is disabled. + * uvmEnabledFeatures + * This parameter returns mask of UVM enabled features on vGPU. It comprises of + * UVM managed APIs and replayable faults that are enabled or disabled based on + * vGPU version. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define VGPU_FBMEMCE_PIPELINED_SEMA_MEM_UPPER_ADDR(addr) (((NvU64)addr) + VGPU_FBMEMCE_PIPELINED_SEMA_MEM_UPPER_OFFSET) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG (0xa0800301) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_OTHERS_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_MESSAGE_ID" */ + +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SW_VSYNC_ENABLED 0:0 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SW_VSYNC_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SW_VSYNC_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CUDA_ENABLED 1:1 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CUDA_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CUDA_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_WDDM1_PREEMPTION_DISABLED 2:2 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_WDDM1_PREEMPTION_DISABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_WDDM1_PREEMPTION_DISABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_LINUX_INTERRUPT_OPTIMIZATION_ENABLED 3:3 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_LINUX_INTERRUPT_OPTIMIZATION_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_LINUX_INTERRUPT_OPTIMIZATION_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_ENABLED 4:4 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PDE_BLIT_ENABLED 5:5 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PDE_BLIT_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PDE_BLIT_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GET_PDE_INFO_CTRL_DISABLED 6:6 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GET_PDE_INFO_CTRL_DISABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GET_PDE_INFO_CTRL_DISABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_FB_OFFSET_DISABLED 7:7 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_FB_OFFSET_DISABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_FB_OFFSET_DISABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CILP_DISABLED_ON_WDDM 8:8 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CILP_DISABLED_ON_WDDM_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CILP_DISABLED_ON_WDDM_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_SEMAPHORE_DISABLED 9:9 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_SEMAPHORE_DISABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_SEMAPHORE_DISABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_UPDATE_DOORBELL_TOKEN_ENABLED 10:10 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_UPDATE_DOORBELL_TOKEN_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_UPDATE_DOORBELL_TOKEN_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_ENABLED 11:11 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_MANAGED_VA_ENABLED 12:12 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_MANAGED_VA_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_MANAGED_VA_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_1TO1_COMPTAG_ENABLED 13:13 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_1TO1_COMPTAG_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VGPU_1TO1_COMPTAG_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_MBP_ENABLED 14:14 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_MBP_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_MBP_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_ASYNC_MBP_ENABLED 15:15 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_ASYNC_MBP_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_ASYNC_MBP_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TLB_INVALIDATE_ENABLED 16:16 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TLB_INVALIDATE_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TLB_INVALIDATE_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_FOR_BAR1_PT_UPDATE_ENABLED 17:17 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_FOR_BAR1_PT_UPDATE_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_PTE_BLIT_FOR_BAR1_PT_UPDATE_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GPU_DIRECT_RDMA_ENABLED 18:18 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GPU_DIRECT_RDMA_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GPU_DIRECT_RDMA_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_HEAVY_ENABLED 19:19 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_HEAVY_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SRIOV_HEAVY_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TIMESLICE_OVERRIDE_ENABLED 20:20 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TIMESLICE_OVERRIDE_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TIMESLICE_OVERRIDE_ENABLED_TRUE (0x00000001) + +/* UVM supported features */ +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_REPLAYABLE_FAULTS_ENABLED 0:0 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_REPLAYABLE_FAULTS_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_REPLAYABLE_FAULTS_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_API_ENABLED 1:1 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_API_ENABLED_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_API_ENABLED_TRUE (0x00000001) + +#define NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVA080_CTRL_VGPU_GET_CONFIG_PARAMS { + NvU32 frameRateLimiter; + NvU32 swVSyncEnabled; + NvU32 cudaEnabled; + NvU32 pluginPteBlitEnabled; + NvU32 disableWddm1xPreemption; + NvU32 debugBufferSize; + NV_DECLARE_ALIGNED(NvP64 debugBuffer, 8); + NV_DECLARE_ALIGNED(NvU64 guestFbOffset, 8); + NV_DECLARE_ALIGNED(NvU64 mappableCpuHostAperture, 8); + NvU32 linuxInterruptOptimization; + NvU32 vgpuDeviceCapsBits; + NvU32 maxPixels; + NvU32 uvmEnabledFeatures; +} NVA080_CTRL_VGPU_GET_CONFIG_PARAMS; + + + +/* _ctrla080_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla081.h b/src/common/sdk/nvidia/inc/ctrl/ctrla081.h new file mode 100644 index 000000000..35876db4f --- /dev/null +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla081.h @@ -0,0 +1,716 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla081.finn +// + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl2080/ctrl2080gpu.h" +#include "nv_vgpu_types.h" +/* NVA081_VGPU_CONFIG control commands and parameters */ + +#define NVA081_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xA081, NVA081_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NVA081_CTRL_RESERVED (0x00) +#define NVA081_CTRL_VGPU_CONFIG (0x01) + +#define NVA081_CTRL_VGPU_CONFIG_INVALID_TYPE 0x00 +#define NVA081_MAX_VGPU_TYPES_PER_PGPU 0x40 +#define NVA081_MAX_VGPU_PER_PGPU 32 +#define NVA081_VM_UUID_SIZE 16 +#define NVA081_VGPU_STRING_BUFFER_SIZE 32 +#define NVA081_VGPU_SIGNATURE_SIZE 128 +#define NVA081_VM_NAME_SIZE 128 +#define NVA081_PCI_CONFIG_SPACE_SIZE 0x100 +#define NVA081_PGPU_METADATA_STRING_SIZE 256 +#define NVA081_EXTRA_PARAMETERS_SIZE 1024 + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_SET_INFO + * + * This command sets the vGPU config information in RM + * + * Parameters: + * + * discardVgpuTypes [IN] + * This parameter specifies if existing vGPU configuration should be + * discarded for given pGPU + * + * vgpuInfo [IN] + * This parameter specifies virtual GPU type information + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_SET_INFO (0xa0810101) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS_MESSAGE_ID" */ + +/* + * NVA081_CTRL_VGPU_CONFIG_INFO + * + * This structure represents the per vGPU information + * + */ +typedef struct NVA081_CTRL_VGPU_INFO { + // This structure should be in sync with NVA082_CTRL_CMD_HOST_VGPU_DEVICE_GET_VGPU_TYPE_INFO_PARAMS + NvU32 vgpuType; + NvU8 vgpuName[NVA081_VGPU_STRING_BUFFER_SIZE]; + NvU8 vgpuClass[NVA081_VGPU_STRING_BUFFER_SIZE]; + NvU8 vgpuSignature[NVA081_VGPU_SIGNATURE_SIZE]; + NvU8 license[NV_GRID_LICENSE_INFO_MAX_LENGTH]; + NvU32 maxInstance; + NvU32 numHeads; + NvU32 maxResolutionX; + NvU32 maxResolutionY; + NvU32 maxPixels; + NvU32 frlConfig; + NvU32 cudaEnabled; + NvU32 eccSupported; + NvU32 gpuInstanceSize; + NvU32 multiVgpuSupported; + NV_DECLARE_ALIGNED(NvU64 vdevId, 8); + NV_DECLARE_ALIGNED(NvU64 pdevId, 8); + NV_DECLARE_ALIGNED(NvU64 profileSize, 8); + NV_DECLARE_ALIGNED(NvU64 fbLength, 8); + NV_DECLARE_ALIGNED(NvU64 gspHeapSize, 8); + NV_DECLARE_ALIGNED(NvU64 fbReservation, 8); + NV_DECLARE_ALIGNED(NvU64 mappableVideoSize, 8); + NvU32 encoderCapacity; + NV_DECLARE_ALIGNED(NvU64 bar1Length, 8); + NvU32 frlEnable; + NvU8 adapterName[NV2080_GPU_MAX_NAME_STRING_LENGTH]; + NvU16 adapterName_Unicode[NV2080_GPU_MAX_NAME_STRING_LENGTH]; + NvU8 shortGpuNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH]; + NvU8 licensedProductName[NV_GRID_LICENSE_INFO_MAX_LENGTH]; + NvU32 vgpuExtraParams[NVA081_EXTRA_PARAMETERS_SIZE]; + NvU32 ftraceEnable; + NvU32 gpuDirectSupported; + NvU32 nvlinkP2PSupported; + NvU32 multiVgpuExclusive; + NvU32 exclusiveType; + NvU32 exclusiveSize; + // used only by NVML + NvU32 gpuInstanceProfileId; +} NVA081_CTRL_VGPU_INFO; + +/* + * NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS + * + * This structure represents the vGPU configuration information + * + */ +#define NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS { + NvBool discardVgpuTypes; + NV_DECLARE_ALIGNED(NVA081_CTRL_VGPU_INFO vgpuInfo, 8); + NvU32 vgpuConfigState; +} NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS; + +/* VGPU Config state values */ +#define NVA081_CTRL_VGPU_CONFIG_STATE_UNINITIALIZED 0 +#define NVA081_CTRL_VGPU_CONFIG_STATE_IN_PROGRESS 1 +#define NVA081_CTRL_VGPU_CONFIG_STATE_READY 2 + +/* + * NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU + * + * This command enumerates list of vGPU guest instances per pGpu + * + * Parameters: + * + * vgpuType [OUT] + * This parameter specifies the virtual GPU type for this physical GPU + * + * numVgpu [OUT] + * This parameter specifies the number of virtual GPUs created on this physical GPU + * + * guestInstanceInfo [OUT] + * This parameter specifies an array containing guest instance's information for + * all instances created on this physical GPU + * + * guestVgpuInfo [OUT] + * This parameter specifies an array containing guest vgpu's information for + * all vGPUs created on this physical GPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU (0xa0810102) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID" */ + +/* + * NVA081_GUEST_VM_INFO + * + * This structure represents vGPU guest's (VM's) information + * + * vmPid [OUT] + * This param specifies the vGPU plugin process ID + * vmIdType [OUT] + * This param specifies the VM ID type, i.e. DOMAIN_ID or UUID + * guestOs [OUT] + * This param specifies the vGPU guest OS type + * migrationProhibited [OUT] + * This flag indicates whether migration is prohibited for VM or not + * guestNegotiatedVgpuVersion [OUT] + * This param specifies the vGPU version of guest driver after negotiation + * frameRateLimit [OUT] + * This param specifies the current value of FRL set for guest + * licensed [OUT] + * This param specifies whether the VM is Unlicensed/Licensed + * licenseState [OUT] + * This param specifies the current state of the GRID license state machine + * licenseExpiryTimestamp [OUT] + * License expiry time in seconds since UNIX epoch + * licenseExpiryStatus [OUT] + * License expiry status + * guestDriverVersion [OUT] + * This param specifies the driver version of the driver installed on the VM + * guestDriverBranch [OUT] + * This param specifies the driver branch of the driver installed on the VM + * vmName [OUT] + * This param stores the name assigned to VM (KVM only) + * guestVmInfoState [OUT] + * This param stores the current state of guest dependent fields + * + */ +typedef struct NVA081_GUEST_VM_INFO { + NvU32 vmPid; + VM_ID_TYPE vmIdType; + NvU32 guestOs; + NvU32 migrationProhibited; + NvU32 guestNegotiatedVgpuVersion; + NvU32 frameRateLimit; + NvBool licensed; + NvU32 licenseState; + NvU32 licenseExpiryTimestamp; + NvU8 licenseExpiryStatus; + NV_DECLARE_ALIGNED(VM_ID guestVmId, 8); + NvU8 guestDriverVersion[NVA081_VGPU_STRING_BUFFER_SIZE]; + NvU8 guestDriverBranch[NVA081_VGPU_STRING_BUFFER_SIZE]; + NvU8 vmName[NVA081_VM_NAME_SIZE]; + GUEST_VM_INFO_STATE guestVmInfoState; +} NVA081_GUEST_VM_INFO; + +/* + * NVA081_GUEST_VGPU_DEVICE + * + * This structure represents host vgpu device's (assigned to VM) information + * + * eccState [OUT] + * This parameter specifies the ECC state of the virtual GPU. + * One of NVA081_CTRL_ECC_STATE_xxx values. + * bDriverLoaded [OUT] + * This parameter specifies whether driver is loaded on this particular vGPU. + * swizzId [OUT] + * This param specifies the GPU Instance ID or Swizz ID + * + */ +typedef struct NVA081_HOST_VGPU_DEVICE { + NvU32 vgpuType; + NvU32 vgpuDeviceInstanceId; + NV_DECLARE_ALIGNED(NvU64 vgpuPciId, 8); + NvU8 vgpuUuid[VM_UUID_SIZE]; + NvU8 mdevUuid[VM_UUID_SIZE]; + NvU32 encoderCapacity; + NV_DECLARE_ALIGNED(NvU64 fbUsed, 8); + NvU32 eccState; + NvBool bDriverLoaded; + NvU32 swizzId; +} NVA081_HOST_VGPU_DEVICE; + +/* ECC state values */ +#define NVA081_CTRL_ECC_STATE_UNKNOWN 0 +#define NVA081_CTRL_ECC_STATE_NOT_SUPPORTED 1 +#define NVA081_CTRL_ECC_STATE_DISABLED 2 +#define NVA081_CTRL_ECC_STATE_ENABLED 3 + +/* + * NVA081_VGPU_GUEST + * + * This structure represents a vGPU guest + * + */ +typedef struct NVA081_VGPU_GUEST { + NV_DECLARE_ALIGNED(NVA081_GUEST_VM_INFO guestVmInfo, 8); + NV_DECLARE_ALIGNED(NVA081_HOST_VGPU_DEVICE vgpuDevice, 8); +} NVA081_VGPU_GUEST; + +/* + * NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS + * + * This structure represents the information of vGPU guest instances per pGpu + * + */ +#define NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS { + NvU32 vgpuType; + NvU32 numVgpu; + NV_DECLARE_ALIGNED(NVA081_VGPU_GUEST vgpuGuest[NVA081_MAX_VGPU_PER_PGPU], 8); +} NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_VGPU_TYPE_INFO + * + * This command fetches vGPU type info from RM. + * + * Parameters: + * + * vgpuType [IN] + * This parameter specifies the virtual GPU type for which vGPU info should be returned. + * + * vgpuTypeInfo [OUT] + * This parameter returns NVA081_CTRL_VGPU_INFO data for the vGPU type specified by vgpuType. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + */ + +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_VGPU_TYPE_INFO (0xa0810103) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS_MESSAGE_ID" */ + +/* + * NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS + * + */ +#define NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS { + NvU32 vgpuType; + NV_DECLARE_ALIGNED(NVA081_CTRL_VGPU_INFO vgpuTypeInfo, 8); +} NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS; + +/* + * NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS + * This structure represents supported/creatable vGPU types on a pGPU + */ +typedef struct NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS { + /* + * [OUT] vGPU config state on a pGPU + */ + NvU32 vgpuConfigState; + + /* + * [OUT] Count of supported/creatable vGPU types on a pGPU + */ + NvU32 numVgpuTypes; + + /* + * [OUT] - Array of vGPU type ids supported/creatable on a pGPU + */ + NvU32 vgpuTypes[NVA081_MAX_VGPU_TYPES_PER_PGPU]; +} NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS; + + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_SUPPORTED_VGPU_TYPES + * + * This command fetches count and list of vGPU types supported on a pGpu from RM + * + * Parameters: + * + * numVgpuTypes [OUT] + * This parameter returns the number of vGPU types supported on this pGPU + * + * vgpuTypes [OUT] + * This parameter returns list of supported vGPUs types on this pGPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + */ + +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_SUPPORTED_VGPU_TYPES (0xa0810104) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | 0x4" */ + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES + * + * This command fetches count and list of vGPU types creatable on a pGpu from RM + * + * Parameters: + * + * numVgpuTypes [OUT] + * This parameter returns the number of vGPU types creatable on this pGPU + * + * vgpuTypes [OUT] + * This parameter returns list of creatable vGPUs types on this pGPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + */ + +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_CREATABLE_VGPU_TYPES (0xa0810105) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | 0x5" */ + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_EVENT_SET_NOTIFICATION + * + * This command sets event notification state for the associated subdevice/pGPU. + * This command requires that an instance of NV01_EVENT has been previously + * bound to the associated subdevice object. + * + * event + * This parameter specifies the type of event to which the specified + * action is to be applied. This parameter must specify a valid + * NVA081_NOTIFIERS value (see cla081.h for more details) and should + * not exceed one less NVA081_NOTIFIERS_MAXCOUNT. + * action + * This parameter specifies the desired event notification action. + * Valid notification actions include: + * NVA081_CTRL_SET_EVENT_NOTIFICATION_DISABLE + * This action disables event notification for the specified + * event for the associated subdevice object. + * NVA081_CTRL_SET_EVENT_NOTIFICATION_SINGLE + * This action enables single-shot event notification for the + * specified event for the associated subdevice object. + * NVA081_CTRL_SET_EVENT_NOTIFICATION_REPEAT + * This action enables repeated event notification for the specified + * event for the associated system controller object. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_STATE + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_EVENT_SET_NOTIFICATION (0xa0810106) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS { + NvU32 event; + NvU32 action; +} NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS; + + +/* valid event action values */ +#define NVA081_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000) +#define NVA081_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001) +#define NVA081_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002) + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_NOTIFY_START + * + * This command notifies the nvidia-vgpu-vfio module with start status. + * It notifies whether start has been successful or not. + * + * mdevUuid + * This parameter specifies the uuid of the mdev device for which start has + * been called. + * vmUuid + * The UUID of VM for which vGPU has been created. + * vmName + * The name of VM for which vGPU has been created. + * returnStatus + * This parameter species whether the vGPU plugin is initialized or not. + * it specifies the error code in case plugin initialization has failed + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_NOTIFY_START (0xa0810107) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS_MESSAGE_ID" */ + +/* + * NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS + * This structure represents information of plugin init status. + */ +#define NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS { + NvU8 mdevUuid[VM_UUID_SIZE]; + NvU8 vmUuid[VM_UUID_SIZE]; + NvU8 vmName[NVA081_VM_NAME_SIZE]; + NvU32 returnStatus; +} NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_MDEV_REGISTER + * + * This command register the GPU to Linux kernel's mdev module for vGPU on KVM. + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_MDEV_REGISTER (0xa0810109) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | 0x9" */ + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_SET_VGPU_INSTANCE_ENCODER_CAPACITY + * + * This command is used to set vGPU instance's (represented by vgpuUuid) encoder Capacity. + * + * vgpuUuid + * This parameter specifies the uuid of vGPU assigned to VM. + * encoderCapacity + * Encoder capacity value from 0 to 100. Value of 0x00 indicates encoder performance + * may be minimal for this GPU and software should fall back to CPU-based encode. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVA081_CTRL_CMD_VGPU_CONFIG_SET_VGPU_INSTANCE_ENCODER_CAPACITY (0xa0810110) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS_MESSAGE_ID" */ + +/* + * NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS + * + * This structure represents encoder capacity for vgpu instance. + */ +#define NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS_MESSAGE_ID (0x10U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS { + NvU8 vgpuUuid[VM_UUID_SIZE]; + NvU32 encoderCapacity; +} NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_VGPU_FB_USAGE + * + * This command is used to get the FB usage of all vGPU instances running on a GPU. + * + * vgpuCount + * This field specifies the number of vGPU devices for which FB usage is returned. + * vgpuFbUsage + * This is an array of type NVA081_VGPU_FB_USAGE, which contains a list of vGPUs + * and their corresponding FB usage in bytes; + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_VGPU_FB_USAGE (0xa0810111) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID" */ + +typedef struct NVA081_VGPU_FB_USAGE { + NvU8 vgpuUuid[VM_UUID_SIZE]; + NV_DECLARE_ALIGNED(NvU64 fbUsed, 8); +} NVA081_VGPU_FB_USAGE; + +/* + * NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS + * + * This structure represents the FB usage information of vGPU instances running on a GPU. + */ +#define NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS_MESSAGE_ID (0x11U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS { + NvU32 vgpuCount; + NV_DECLARE_ALIGNED(NVA081_VGPU_FB_USAGE vgpuFbUsage[NVA081_MAX_VGPU_PER_PGPU], 8); +} NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP + * + * This command is used to query whether pGPU is live migration capable or not. + * + * bMigrationCap + * Set to NV_TRUE if pGPU is migration capable. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_REQUEST + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP (0xa0810112) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS_MESSAGE_ID" */ + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS_MESSAGE_ID (0x12U) + +typedef struct NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS { + NvBool bMigrationCap; +} NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_HOST_FB_RESERVATION + * + * This command is used to get the host FB requirements + * + * hostReservedFb [OUT] + * Amount of FB reserved for the host + * eccAndPrReservedFb [OUT] + * Amount of FB reserved for the ecc and page retirement + * totalReservedFb [OUT] + * Total FB reservation + * vgpuTypeId [IN] + * The Type ID for VGPU profile + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_HOST_FB_RESERVATION (0xa0810113) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_HOST_FB_RESERVATION_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_GET_HOST_FB_RESERVATION_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_GET_HOST_FB_RESERVATION_PARAMS { + NV_DECLARE_ALIGNED(NvU64 hostReservedFb, 8); + NV_DECLARE_ALIGNED(NvU64 eccAndPrReservedFb, 8); + NV_DECLARE_ALIGNED(NvU64 totalReservedFb, 8); + NvU32 vgpuTypeId; +} NVA081_CTRL_VGPU_CONFIG_GET_HOST_FB_RESERVATION_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_PGPU_METADATA_STRING + * + * This command is used to get the pGpu metadata string. + * + * pGpuString + * String holding pGpu Metadata + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_INVALID_STATE + * NV_ERR_INSUFFICIENT_RESOURCES + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_PGPU_METADATA_STRING (0xa0810114) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_PGPU_METADATA_STRING_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_GET_PGPU_METADATA_STRING_PARAMS_MESSAGE_ID (0x14U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_GET_PGPU_METADATA_STRING_PARAMS { + NvU8 pGpuString[NVA081_PGPU_METADATA_STRING_SIZE]; +} NVA081_CTRL_VGPU_CONFIG_GET_PGPU_METADATA_STRING_PARAMS; + +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT (0xa0810115) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT_PARAMS_MESSAGE_ID (0x15U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT_PARAMS { + NvBool doorbellEmulationEnabled; +} NVA081_CTRL_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_FREE_SWIZZID + * + * This command is used to get free swizzid from RM + * + * gpuPciId [IN] + * This param specifies the PCI device ID of VF on which VM is running + * + * vgpuTypeId [IN] + * This param specifies the Type ID for VGPU profile + * + * swizzId [OUT] + * This param specifies the GPU Instance ID or Swizz ID + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_FREE_SWIZZID (0xa0810116) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_FREE_SWIZZID_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_GET_FREE_SWIZZID_PARAMS_MESSAGE_ID (0x16U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_GET_FREE_SWIZZID_PARAMS { + NvU32 gpuPciId; + NvU32 vgpuTypeId; + NvU32 swizzId; +} NVA081_CTRL_VGPU_CONFIG_GET_FREE_SWIZZID_PARAMS; + +/* + * NVA081_CTRL_CMD_PGPU_GET_MULTI_VGPU_SUPPORT_INFO + * + * This command is used to get multi vGPU related info for the physical GPU. + * + * fractionalmultiVgpuSupported [OUT] + * This param specifies whether fractional multi-vGPU is supported + * + * heterogeneousTimesliceProfilesSupported [OUT] + * This param specifies whether concurrent execution of timesliced vGPU profiles of differing types is supported + * + * heterogeneousTimesliceSizesSupported [OUT] + * This param specifies whether concurrent execution of timesliced vGPU profiles of differing framebuffer sizes is supported + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVA081_CTRL_CMD_PGPU_GET_MULTI_VGPU_SUPPORT_INFO (0xa0810117) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS_MESSAGE_ID (0x17U) + +typedef struct NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS { + NvU32 fractionalmultiVgpuSupported; + NvU32 heterogeneousTimesliceProfilesSupported; + NvU32 heterogeneousTimesliceSizesSupported; +} NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS; + +/* + * NVA081_CTRL_CMD_GET_VGPU_DRIVER_CAPS + * + * This command is used to get vGPU driver capabilities. + * + * heterogeneousMultiVgpuSupported [OUT] + * This param specifies whether heterogeneous multi-vGPU is supported + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVA081_CTRL_CMD_GET_VGPU_DRIVER_CAPS (0xa0810118) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS { + NvU32 heterogeneousMultiVgpuSupported; +} NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_SET_PGPU_INFO + * + * This command is to set pgpu info + * + * fractionalMultiVgpu [IN] + * This param specifies the fractional multivgpu is enabled or disabled on GPU + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + */ + +#define NVA081_CTRL_CMD_VGPU_CONFIG_SET_PGPU_INFO (0xa0810119) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS_MESSAGE_ID (0x19U) + +typedef struct NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS { + NvU32 fractionalMultiVgpu; +} NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS; + +/* _ctrlA081vgpuconfig_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla083.h b/src/common/sdk/nvidia/inc/ctrl/ctrla083.h deleted file mode 100644 index 855ebd41f..000000000 --- a/src/common/sdk/nvidia/inc/ctrl/ctrla083.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2015-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#pragma once - -#include - -// -// This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrla083.finn -// - -#include "ctrl/ctrlxxxx.h" -/* NVA083_GRID_DISPLAYLESS control commands and parameters */ - -#define NVA083_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xA083, NVA083_CTRL_##cat, idx) - -/* Command categories (6bits) */ -#define NVA083_CTRL_RESERVED (0x00) -#define NVA083_CTRL_VIRTUAL_DISPLAY (0x01) - -/* - * NVA083_CTRL_CMD_NULL - * - * This command does nothing. - * This command does not take any parameters. - * - * Possible status values returned are: - * NV_OK - */ - -#define NVA083_CTRL_CMD_NULL (0xa0830000) /* finn: Evaluated from "(FINN_NVA083_GRID_DISPLAYLESS_RESERVED_INTERFACE_ID << 8) | 0x0" */ - -#define NVA083_CTRL_CMD_VIRTUAL_DISPLAY_GET_NUM_HEADS (0xa0830101) /* finn: Evaluated from "(FINN_NVA083_GRID_DISPLAYLESS_VIRTUAL_DISPLAY_INTERFACE_ID << 8) | NVA083_CTRL_VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS_MESSAGE_ID" */ - -#define NVA083_CTRL_VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS_MESSAGE_ID (0x1U) - -typedef struct NVA083_CTRL_VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS { - NvU32 numHeads; - NvU32 maxNumHeads; -} NVA083_CTRL_VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS; - -/* - * NVA083_CTRL_CMD_VIRTUAL_DISPLAY_GET_MAX_RESOLUTION - * - * This command returns the maximum resolution supported on a GPU with - * Displayless path enabled OR on a virtual GPU. - * - * headIndex - * This parameter specifies the head for which the maximum resolution is to be - * retrieved. - * - * maxHResolution - * This parameter returns the maximum horizontal resolution. - * - * maxVResolution - * This parameter returns the maximum vertical resolution. - * - * Possible status values returned are: - * NV_OK - * NV_ERR_INVALID_ARGUMENT - */ - -#define NVA083_CTRL_CMD_VIRTUAL_DISPLAY_GET_MAX_RESOLUTION (0xa0830102) /* finn: Evaluated from "(FINN_NVA083_GRID_DISPLAYLESS_VIRTUAL_DISPLAY_INTERFACE_ID << 8) | NVA083_CTRL_VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS_MESSAGE_ID" */ - -#define NVA083_CTRL_VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS_MESSAGE_ID (0x2U) - -typedef struct NVA083_CTRL_VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS { - NvU32 headIndex; - NvU32 maxHResolution; - NvU32 maxVResolution; -} NVA083_CTRL_VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS; - - - -#define NVA083_CTRL_CMD_VIRTUAL_DISPLAY_GET_MAX_PIXELS (0xa0830106) /* finn: Evaluated from "(FINN_NVA083_GRID_DISPLAYLESS_VIRTUAL_DISPLAY_INTERFACE_ID << 8) | NVA083_CTRL_VIRTUAL_DISPLAY_GET_MAX_PIXELS_PARAMS_MESSAGE_ID" */ - -#define NVA083_CTRL_VIRTUAL_DISPLAY_GET_MAX_PIXELS_PARAMS_MESSAGE_ID (0x6U) - -typedef struct NVA083_CTRL_VIRTUAL_DISPLAY_GET_MAX_PIXELS_PARAMS { - NV_DECLARE_ALIGNED(NvU64 maxPixels, 8); -} NVA083_CTRL_VIRTUAL_DISPLAY_GET_MAX_PIXELS_PARAMS; - -/* _ctrla083_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla084.h b/src/common/sdk/nvidia/inc/ctrl/ctrla084.h new file mode 100644 index 000000000..f5a514684 --- /dev/null +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla084.h @@ -0,0 +1,302 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla084.finn +// + +#include "nv_vgpu_types.h" +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl2080/ctrl2080gpu.h" // NV2080_GPU_MAX_GID_LENGTH +#include "ctrl/ctrl2080/ctrl2080fb.h" // NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES + +/* NVA084_KERNEL_HOST_VGPU_DEVICE control commands and parameters */ +#define NVA084_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xA084U, NVA084_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NVA084_CTRL_RESERVED (0x00) +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE (0x01) + +/* + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO + * + * This command sets the guest vgpu device's information + * + * Parameter: + * + * vgpuUuid [IN] + * This parameter specifies the universaly unique identifier of the guest vGPU device + * + * vgpuDeviceInstanceId [IN] + * This parameter specifies the vGPU device instance + * + * Possible status values returned are: + * NV_OK + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO (0xa0840101) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS { + NvU8 vgpuUuid[NV2080_GPU_MAX_GID_LENGTH]; + NvU32 vgpuDeviceInstanceId; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS; + +/* NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE + * + * This command triggers the notifier for vGPU guest. + * + * Parameters: + * + * vmLifeCycleState[IN] + * The life cycle event of the vGPU guest. This can be: + * NVA081_NOTIFIERS_EVENT_VGPU_GUEST_DESTROYED + * NVA081_NOTIFIERS_EVENT_VGPU_GUEST_CREATED + * + * Possible status values returned are: + * NV_OK + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE (0xa0840102) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE_PARAMS { + NvU32 vmLifeCycleState; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE_PARAMS; + +/* + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO + * + * This command is used to copy offlined page mapping info from plugin to host vgpu device + * + * guestFbSegmentPageSize [in] + * Guest FB segment page size + * + * offlinedPageCount [in] + * Offlined page count in the guest FB range + * + * gpa [in] + * This array represents guest page address list of offlined page + * + * hMemory [in] + * This array represents memory handle list of good page + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO (0xa0840103) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO_PARAMS { + NvU32 guestFbSegmentPageSize; + NvU32 offlinedPageCount; + NV_DECLARE_ALIGNED(NvU64 gpa[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES], 8); + NvHandle hMemory[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES]; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO_PARAMS; + +/* + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS + * + * Config space access for the virtual function + * + * Parameters: + * + * offset [IN] + * Offset within the config space + * + * numBytes [IN] + * Number of bytes to be read/written: 1/2/4 + * + * accessType [IN] + * To indicate whether it is a read operation or a write operation + * + * value [INOUT] + * Value to be read or written + * + * Possible status values returned are: + * NV_OK + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS (0xa0840104) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_VF_CONFIG_SPACE_ACCESS_TYPE_READ 0x1 +#define NVA084_CTRL_VF_CONFIG_SPACE_ACCESS_TYPE_WRITE 0x2 + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS_PARAMS_MESSAGE_ID (0x4U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS_PARAMS { + NvU16 offset; + NvU8 numBytes; + NvU8 accessType; + NvU32 value; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS_PARAMS; + +/* + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF + * + * This command is used to create a bind-point on a host system + * for the collection of guest VM FECS events + * + * hEventBufferClient[IN] + * The client of the event buffer to bind to + * + * hEventBufferSubdevice[IN] + * The subdevice of the event buffer to bind to + * + * hEventBuffer[IN] + * The event buffer to bind to + * + * reasonCode[OUT] + * The reason for failure (if any); see NV2080_CTRL_GR_FECS_BIND_EVTBUF_REASON_CODE + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF (0xa0840105) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF_PARAMS_MESSAGE_ID (0x5U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF_PARAMS { + NvHandle hEventBufferClient; + NvHandle hEventBufferSubdevice; + NvHandle hEventBuffer; + NvU32 reasonCode; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF_PARAMS; + +/* + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL + * + * The command will trigger the specified interrupt on the host from CPU Plugin. + * + * handle[IN] + * - An opaque handle that will be passed in along with the interrupt + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL (0xa0840106) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL_PARAMS { + NvU32 handle; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL_PARAMS; + +/* valid action values */ +#define NVA084_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000) +#define NVA084_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001) +#define NVA084_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002) + +/* + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION + * + * This command sets event notification state for the associated host vgpu device. + * This command requires that an instance of NV01_EVENT has been previously + * bound to the associated host vgpu device object. + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION (0xa0840107) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION_PARAMS { + // + // @todo: We will define the actual event values later based on the use case. + // These event values are only for Test purpose. + // + NvU32 event; + NvU32 action; + NvBool bNotifyState; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION_PARAMS; + +/* NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE + * + * This command is used to set SRIOV state parameters in RM. + * + * Parameters: + * + * numPluginChannels [IN] + * Number of channels required by plugin + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE (0xa0840108) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_MAX_PLUGIN_CHANNELS 5 + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS { + NvU32 numPluginChannels; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS; + +/* NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID + * + * This command is used to set/unset VM ID parameters in host vgpu device in RM. + * + * Parameters: + * + * action + * This parameter specifies the desired set guest id action. + * Valid set guest id actions include: + * NVA084_CTRL_HOST_VGPU_DEVICE_KERNEL_SET_GUEST_ID_ACTION_SET + * This action sets the VM ID information in host vgpu device. + * NVA084_CTRL_HOST_VGPU_DEVICE_KERNEL_SET_GUEST_ID_ACTION_UNSET + * This action unsets the VM ID information in host vgpu device. + * vmPid [IN] + * VM process ID + * vmIdType[IN] + * VM ID type whether it's UUID or DOMAIN_ID + * guestVmId[IN] + * VM ID + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID (0xa0840109) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS { + NvU8 action; + NvU32 vmPid; + VM_ID_TYPE vmIdType; + NV_DECLARE_ALIGNED(VM_ID guestVmId, 8); +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS; + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_ACTION_SET (0x00000000) +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_ACTION_UNSET (0x00000001) + +/* _ctrla084_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h b/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h index b472e6b7f..d456c63c1 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h @@ -387,7 +387,7 @@ typedef struct NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS { * if programming fails, it will reset credits to 0 for all the chiplets. * */ -#define NVB0CC_CTRL_CMD_SET_HS_CREDITS (0xb0cc010e) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0xE" */ +#define NVB0CC_CTRL_CMD_SET_HS_CREDITS (0xb0cc010e) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_MESSAGE_ID" */ typedef enum NVB0CC_CHIPLET_TYPE { NVB0CC_CHIPLET_TYPE_INVALID = 0, @@ -440,6 +440,8 @@ typedef struct NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS { #define NVB0CC_MAX_CREDIT_INFO_ENTRIES (63) +#define NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_MESSAGE_ID (0xEU) + typedef struct NVB0CC_CTRL_SET_HS_CREDITS_PARAMS { /*! * [in] The PMA Channel Index associated with a given PMA stream. diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h index 0ceda2368..743663c24 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h @@ -149,6 +149,10 @@ * This parameter specifies if the head operates in 2Head1Or mode. * Refer to NVD_2_Heads_Driving_1_OR_Functional_Description.docx for more details. * + * head.bGetOSLDOutput + * This parameter specifies if the client requires output for the OSLD + * (One Shot Mode with Stall Lock Disabled) mode along with legacy outputs. + * * head.bDisableMidFrameAndDWCFWatermark * WAR for bug 200508242. * In linux it is possible that there will be no fullscreen window visible @@ -269,8 +273,17 @@ * * Outputs: * bIsPossible - * This output tells if the specified mode can be supported. + * This output tells if the specified mode can be supported. To know if + * the mode is possible with OSLD, the bIsOSLDPossible result must + * be checked. * + * bIsOSLDPossible + * This output is returned for each head and suggests to the clients + * if the mode will be possible or not on that head when OSLD is enabled. + * The output is only valid if bGetOSLDOutput is set in the head input. + * Note that with OSLD output, RM will also return the legacy output + * values. + * * minImpVPState * minImpVPState returns the minimum v-pstate at which the mode is possible * (assuming bIsPossible is TRUE). This output is valid only on dGPU, and @@ -317,6 +330,25 @@ * support the mode. This output is valid only on Tegra, and only if * NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE was set in the * "options" field. + * + * vblankIncreaseInLinesForOSLDMode + * vblankIncreaseInLinesForOSLDMode returns the amount, in lines, by + * which vblank needs to be extended to achieve optimized MSCG when OSLD + * Mode is enabled (assuming bIsPossible is TRUE). Features like Panel + * Replay and Panel Self Refresh enable OSLD mode. This value is 0 if + * the vblank is large enough to accommodate spool up and MSCG latencies. + * This output is valid only if + * NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE was set in the + * "options" field and bGetOSLDOutput was specified in the head input. + * + * wakeUpRgLineForOSLDMode + * wakeUpRgLineForOSLDMode returns the rg line in the vblank region at which + * the clients will be required to send a timestamped update to achieve + * optimized MSCG when OSLD Mode is enabled (assuming bIsPossible is + * is TRUE). Features like Panel Replay and Panel Self Refresh enable + * OSLD mode. This output is valid only if + * NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE was set in the + * "options" field and bGetOSLDOutput was specified in the head input. * * worstCaseMargin * worstCaseMargin returns the ratio of available bandwidth to required @@ -410,6 +442,8 @@ typedef struct NVC372_CTRL_IMP_HEAD { NvBool bIs2Head1Or; + NvBool bGetOSLDOutput; + NvBool bDisableMidFrameAndDWCFWatermark; } NVC372_CTRL_IMP_HEAD; typedef struct NVC372_CTRL_IMP_HEAD *PNVC372_CTRL_IMP_HEAD; @@ -452,6 +486,8 @@ typedef struct NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS { NvBool bIsPossible; + NvBool bIsOSLDPossible[NVC372_CTRL_MAX_POSSIBLE_HEADS]; + NvU32 minImpVPState; NvU32 minPState; @@ -462,6 +498,10 @@ typedef struct NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS { NvU32 minRequiredHubclkKHz; + NvU32 vblankIncreaseInLinesForOSLDMode[NVC372_CTRL_MAX_POSSIBLE_HEADS]; + + NvU32 wakeUpRgLineForOSLDMode[NVC372_CTRL_MAX_POSSIBLE_HEADS]; + NvU32 worstCaseMargin; NvU32 dispClkKHz; @@ -500,10 +540,11 @@ typedef struct NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS *PNVC372_CTRL_IS_MODE_POSSIBL #define NVC372_CTRL_IMP_INSUFFICIENT_BANDWIDTH 5 #define NVC372_CTRL_IMP_DISPCLK_TOO_LOW 6 #define NVC372_CTRL_IMP_ELV_START_TOO_HIGH 7 -#define NVC372_CTRL_IMP_INSUFFICIENT_THREAD_GROUPS 8 -#define NVC372_CTRL_IMP_INVALID_PARAMETER 9 -#define NVC372_CTRL_IMP_UNRECOGNIZED_FORMAT 10 -#define NVC372_CTRL_IMP_UNSPECIFIED 11 +#define NVC372_CTRL_IMP_OSLD_ELV_START_TOO_HIGH 8 +#define NVC372_CTRL_IMP_INSUFFICIENT_THREAD_GROUPS 9 +#define NVC372_CTRL_IMP_INVALID_PARAMETER 10 +#define NVC372_CTRL_IMP_UNRECOGNIZED_FORMAT 11 +#define NVC372_CTRL_IMP_UNSPECIFIED 12 /* * The calculated margin is multiplied by a constant, so that it can be diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc637.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc637.h index ce4db0bb9..155d639ce 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc637.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc637.h @@ -85,6 +85,16 @@ * * veidStartOffset[OUT] * - VEID start offset within GPU partition + * + * smCount[IN/OUT] + * - Number of active SMs in this partition + * + * spanStart[IN/OUT] + * - First slot in the span for an execution partition placement + * + * computeSize[IN/OUT] + * - Flag corresponding to the compute profile used + * */ typedef struct NVC637_CTRL_EXEC_PARTITIONS_INFO { NvU32 gpcCount; @@ -97,6 +107,9 @@ typedef struct NVC637_CTRL_EXEC_PARTITIONS_INFO { NvU32 ofaCount; NvU32 sharedEngFlag; NvU32 veidStartOffset; + NvU32 smCount; + NvU32 spanStart; + NvU32 computeSize; } NVC637_CTRL_EXEC_PARTITIONS_INFO; #define NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG 31:0 @@ -128,6 +141,12 @@ typedef struct NVC637_CTRL_EXEC_PARTITIONS_INFO { * when vgpu plugin implements virtualized execution partition ID support. * (bug 2938187) * + * REQUEST_AT_SPAN + * - If set, RM will try to assign execution partition resources at the specified span. + * This flag currently is only useful for chips in which CTS IDs are mandatory in RM, + * as it allows the requester to position compute instances without using RM best fit + * allocation. + * * execPartCount[IN] * - Number of execution partitions requested * @@ -145,8 +164,9 @@ typedef struct NVC637_CTRL_EXEC_PARTITIONS_INFO { #define NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_WITH_PART_ID 0:0 #define NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_WITH_PART_ID_FALSE (0x00000000) #define NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_WITH_PART_ID_TRUE (0x00000001) - - +#define NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_AT_SPAN 1:1 +#define NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_AT_SPAN_FALSE (0x00000000) +#define NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_AT_SPAN_TRUE (0x00000001) #define NVC637_CTRL_CMD_EXEC_PARTITIONS_CREATE (0xc6370101) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_MESSAGE_ID" */ @@ -284,6 +304,9 @@ typedef struct NVC637_CTRL_EXEC_PARTITIONS_EXPORTED_INFO { NvU32 gpcMask; NvU32 veidOffset; NvU32 veidCount; + NvU32 smCount; + NvU32 spanStart; + NvU32 computeSize; } NVC637_CTRL_EXEC_PARTITIONS_EXPORTED_INFO; typedef struct NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS { @@ -291,4 +314,79 @@ typedef struct NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS { NV_DECLARE_ALIGNED(NVC637_CTRL_EXEC_PARTITIONS_EXPORTED_INFO info, 8); } NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS; +/* + * NVC637_CTRL_EXEC_PARTITION_PARTITION_SPAN + * + * This struct represents the span of a compute instance, which represents the + * resource slots a given partition occupies (or may occupy) within a fixed range which + * is defined per-chip. A partition containing more resources will cover more + * resource slots and therefore cover a larger span. + * + * lo + * - The starting unit of this span, inclusive + * + * hi + * - The ending unit of this span, inclusive + * + */ +typedef struct NVC637_CTRL_EXEC_PARTITION_PARTITION_SPAN { + NV_DECLARE_ALIGNED(NvU64 lo, 8); + NV_DECLARE_ALIGNED(NvU64 hi, 8); +} NVC637_CTRL_EXEC_PARTITION_PARTITION_SPAN; + +/* + * NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY + * + * This command returns the count of compute instances which can be created + * of the given commpute profile size (represented by the computeSize field + * within a profile) which can be requested via NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILES + * Note that this API does not "reserve" any partitions, and there is no + * guarantee that the reported count of available partitions of a given size + * will remain consistent following creation of partitions of different size + * through NV2080_CTRL_GPU_SET_PARTITIONS. + * Note that this API is unsupported if SMC is feature-disabled. + * Note that the caller of this CTRL must be subscribed to a valid GPU instance + * + * computeSize[IN] + * - Partition flag indicating size of requested profile + * + * profileCount[OUT] + * - Available number of profiles of the given size which can currently be created. + * + * availableSpans[OUT] + * - For each profile able to be created of the specified size, the span + * it could occupy. + * + * availableSpansCount[OUT] + * - Number of valid entries in availableSpans. + * + * totalProfileCount[OUT] + * - Total number of profiles of the given size which can be created. + * + * totalSpans[OUT] + * - List of spans which can possibly be occupied by profiles of the + * given type. + * + * totalSpansCount[OUT] + * - Number of valid entries in totalSpans. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NVC637_CTRL_CMD_EXEC_PARTITIONS_GET_PROFILE_CAPACITY (0xc63701a9U) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY_PARAMS_MESSAGE_ID" */ + +#define NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY_PARAMS_MESSAGE_ID (0xA9U) + +typedef struct NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY_PARAMS { + NvU32 computeSize; + NvU32 profileCount; + NV_DECLARE_ALIGNED(NVC637_CTRL_EXEC_PARTITION_PARTITION_SPAN availableSpans[NVC637_CTRL_MAX_EXEC_PARTITIONS], 8); + NvU32 availableSpansCount; + NvU32 totalProfileCount; + NV_DECLARE_ALIGNED(NVC637_CTRL_EXEC_PARTITION_PARTITION_SPAN totalSpans[NVC637_CTRL_MAX_EXEC_PARTITIONS], 8); + NvU32 totalSpansCount; +} NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY_PARAMS; + // _ctrlc637_h_ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlcbca.h b/src/common/sdk/nvidia/inc/ctrl/ctrlcbca.h index 026ad394e..1e47decf9 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlcbca.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlcbca.h @@ -82,7 +82,39 @@ typedef struct NV_COUNTER_COLLECTION_UNIT_SUBSCRIBE_PARAMS { * NV_ERR_INVALID_ARGUMENT */ -#define NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_UNSUBSCRIBE (0xcbca0102) /* finn: Evaluated from "(FINN_NV_COUNTER_COLLECTION_UNIT_CCU_INTERFACE_ID << 8) | 0x2" */ +#define NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_UNSUBSCRIBE (0xcbca0102) /* finn: Evaluated from "(FINN_NV_COUNTER_COLLECTION_UNIT_CCU_INTERFACE_ID << 8) | 0x2" */ + +/* + * NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_SET_STREAM_STATE + * + * This command is used to set the counter collection unit stream state + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_SET_STREAM_STATE (0xcbca0103) /* finn: Evaluated from "(FINN_NV_COUNTER_COLLECTION_UNIT_CCU_INTERFACE_ID << 8) | NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS_MESSAGE_ID" */ + +#define NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS { + NvBool bStreamState; +} NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS; + +/* + * NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_GET_STREAM_STATE + * + * This command is used to get the counter collection unit stream state + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV_COUNTER_COLLECTION_UNIT_CTRL_CMD_GET_STREAM_STATE (0xcbca0104) /* finn: Evaluated from "(FINN_NV_COUNTER_COLLECTION_UNIT_CCU_INTERFACE_ID << 8) | 0x4" */ /* _ctrlcbca_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlxxxx.h b/src/common/sdk/nvidia/inc/ctrl/ctrlxxxx.h index 7a5eaad23..efe0c589d 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlxxxx.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlxxxx.h @@ -34,11 +34,11 @@ /* definitions shared by all CTRL interfaces */ -/* Basic command format: -* cmd_class [31:16], +/* Basic command format: +* cmd_class [31:16], * cmd_reserved [15:15], * cmd_reserved [14:14], -* cmd_category [13:8], +* cmd_category [13:8], * cmd_index [7:0] */ diff --git a/src/common/sdk/nvidia/inc/finn_rm_api.h b/src/common/sdk/nvidia/inc/finn_rm_api.h index 77fbdd11e..0722dd9a0 100644 --- a/src/common/sdk/nvidia/inc/finn_rm_api.h +++ b/src/common/sdk/nvidia/inc/finn_rm_api.h @@ -40,7 +40,7 @@ * FINN compiler version */ #define FINN_VERSION_MAJOR 1 -#define FINN_VERSION_MINOR 13 +#define FINN_VERSION_MINOR 14 #define FINN_VERSION_PATCH 0 typedef struct FINN_RM_API @@ -172,7 +172,6 @@ typedef FINN_RM_API FINN_NV01_ROOT_EVENT; typedef FINN_RM_API FINN_NV01_ROOT_GPU; #define FINN_NV01_ROOT_GPUACCT_INTERFACE_ID (0xbU) typedef FINN_RM_API FINN_NV01_ROOT_GPUACCT; - #define FINN_NV01_ROOT_GSYNC_INTERFACE_ID (0x3U) typedef FINN_RM_API FINN_NV01_ROOT_GSYNC; #define FINN_NV01_ROOT_NVD_INTERFACE_ID (0x6U) @@ -186,7 +185,8 @@ typedef FINN_RM_API FINN_NV01_ROOT_SYNC_GPU_BOOST; typedef FINN_RM_API FINN_NV01_ROOT_SYSTEM; #define FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID (0x3dU) typedef FINN_RM_API FINN_NV01_ROOT_OS_UNIX; - +#define FINN_NV01_ROOT_VGPU_INTERFACE_ID (0xcU) +typedef FINN_RM_API FINN_NV01_ROOT_VGPU; #define FINN_NV01_ROOT_OS_WINDOWS_INTERFACE_ID (0x3fU) typedef FINN_RM_API FINN_NV01_ROOT_OS_WINDOWS; #define FINN_NV01_CONTEXT_DMA_RESERVED_INTERFACE_ID (0x200U) @@ -267,6 +267,8 @@ typedef FINN_RM_API FINN_NV01_DEVICE_0_OS_UNIX; #define FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID (0x9001U) typedef FINN_RM_API FINN_NV0090_KERNEL_GRAPHICS_CONTEXT; +#define FINN_IMEX_SESSION_INTERFACE_ID (0xf100U) +typedef FINN_RM_API FINN_IMEX_SESSION; #define FINN_NV01_MEMORY_FABRIC_EXPORT_RESERVED_INTERFACE_ID (0xf400U) typedef FINN_RM_API FINN_NV01_MEMORY_FABRIC_EXPORT_RESERVED; #define FINN_NV01_MEMORY_FABRIC_EXPORT_EXPORT_INTERFACE_ID (0xf401U) @@ -275,6 +277,10 @@ typedef FINN_RM_API FINN_NV01_MEMORY_FABRIC_EXPORT_EXPORT; typedef FINN_RM_API FINN_NV01_MEMORY_FABRIC_IMPORT_RESERVED; #define FINN_NV01_MEMORY_FABRIC_IMPORT_IMPORT_INTERFACE_ID (0xf501U) typedef FINN_RM_API FINN_NV01_MEMORY_FABRIC_IMPORT_IMPORT; +#define FINN_NV_MEMORY_FABRIC_EXPORT_RESERVED_INTERFACE_ID (0xf700U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_EXPORT_RESERVED; +#define FINN_NV_MEMORY_FABRIC_EXPORT_INTERFACE_ID (0xf701U) +typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_EXPORT; #define FINN_NV_MEMORY_FABRIC_RESERVED_INTERFACE_ID (0xf800U) typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_RESERVED; #define FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID (0xf801U) @@ -291,6 +297,12 @@ typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_EXPORTED_REF_EXPORT_REF; typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORTED_REF_RESERVED; #define FINN_NV_MEMORY_FABRIC_IMPORTED_REF_IMPORT_REF_INTERFACE_ID (0xfb01U) typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORTED_REF_IMPORT_REF; +#define FINN_NV_MEMORY_MULTICAST_FABRIC_RESERVED_INTERFACE_ID (0xfd00U) +typedef FINN_RM_API FINN_NV_MEMORY_MULTICAST_FABRIC_RESERVED; +#define FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID (0xfd01U) +typedef FINN_RM_API FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC; +#define FINN_NV_MEMORY_MAPPER_INTERFACE_ID (0x00FE00U) +typedef FINN_RM_API FINN_NV_MEMORY_MAPPER; #define FINN_NV20_SUBDEVICE_0_RESERVED_INTERFACE_ID (0x208000U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_RESERVED; @@ -341,6 +353,8 @@ typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_GSP; typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_HSHUB; #define FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID (0x208006U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_I2C; +#define FINN_NV20_SUBDEVICE_0_PMGR_INTERFACE_ID (0x208026U) +typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_PMGR; #define FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID (0x20800aU) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_INTERNAL; @@ -355,6 +369,7 @@ typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_NVD; #define FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID (0x208030U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_NVLINK; + #define FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID (0x208020U) typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_PERF; @@ -542,13 +557,15 @@ typedef FINN_RM_API FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY; typedef FINN_RM_API FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY; #define FINN_KEPLER_DEVICE_VGPU_VGPU_OTHERS_INTERFACE_ID (0xa08003U) typedef FINN_RM_API FINN_KEPLER_DEVICE_VGPU_VGPU_OTHERS; +#define FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID (0xa08101U) +typedef FINN_RM_API FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG; #define FINN_NVA083_GRID_DISPLAYLESS_RESERVED_INTERFACE_ID (0xa08300U) typedef FINN_RM_API FINN_NVA083_GRID_DISPLAYLESS_RESERVED; #define FINN_NVA083_GRID_DISPLAYLESS_VIRTUAL_DISPLAY_INTERFACE_ID (0xa08301U) typedef FINN_RM_API FINN_NVA083_GRID_DISPLAYLESS_VIRTUAL_DISPLAY; -#define FINN_NVA084_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_KERNEL_INTERFACE_ID (0xa08401U) -typedef FINN_RM_API FINN_NVA084_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_KERNEL; +#define FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID (0xa08401U) +typedef FINN_RM_API FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE; #define FINN_NVENC_SW_SESSION_NVENC_SW_SESSION_INTERFACE_ID (0xa0bc01U) typedef FINN_RM_API FINN_NVENC_SW_SESSION_NVENC_SW_SESSION; #define FINN_NVFBC_SW_SESSION_NVFBC_SW_SESSION_INTERFACE_ID (0xa0bd01U) diff --git a/src/common/sdk/nvidia/inc/mmu_fmt_types.h b/src/common/sdk/nvidia/inc/mmu_fmt_types.h index 5a81c3d67..ecbe2aaeb 100644 --- a/src/common/sdk/nvidia/inc/mmu_fmt_types.h +++ b/src/common/sdk/nvidia/inc/mmu_fmt_types.h @@ -97,6 +97,13 @@ typedef struct MMU_FMT_LEVEL { */ NvU8 numSubLevels; + /*! + * Information tag used to decode internal level naming. + * Used for verif. + * */ + NvU32 pageLevelIdTag; + + /*! * Array of sub-level formats of length numSubLevels. * @@ -129,3 +136,16 @@ typedef struct MMU_FMT_LEVEL { * simplify SW handling, encouraging loops over "dual copy-paste." */ #define MMU_FMT_MAX_SUB_LEVELS 2 + +/*! + * Valid values for the pageLevelIdTag field. + * These values are used to identify the internal naming of the page level. + * Used for verif purposes. + */ +#define MMU_FMT_PT_SURF_ID_PD0 0 +#define MMU_FMT_PT_SURF_ID_PD1 1 +#define MMU_FMT_PT_SURF_ID_PD2 2 +#define MMU_FMT_PT_SURF_ID_PD3 3 +#define MMU_FMT_PT_SURF_ID_PD4 4 +#define MMU_FMT_PT_SURF_ID_PT_4K 5 +#define MMU_FMT_PT_SURF_ID_PT_BIG 6 diff --git a/src/common/sdk/nvidia/inc/nv-hypervisor.h b/src/common/sdk/nvidia/inc/nv-hypervisor.h index ddc6a9134..6ee37f76c 100644 --- a/src/common/sdk/nvidia/inc/nv-hypervisor.h +++ b/src/common/sdk/nvidia/inc/nv-hypervisor.h @@ -27,15 +27,13 @@ #include // Enums for supported hypervisor types. -// New hypervisor type should be added before OS_HYPERVISOR_CUSTOM_FORCED +// New hypervisor type should be added before OS_HYPERVISOR_UNKNOWN typedef enum _HYPERVISOR_TYPE { OS_HYPERVISOR_XEN = 0, OS_HYPERVISOR_VMWARE, OS_HYPERVISOR_HYPERV, OS_HYPERVISOR_KVM, - OS_HYPERVISOR_PARALLELS, - OS_HYPERVISOR_CUSTOM_FORCED, OS_HYPERVISOR_UNKNOWN } HYPERVISOR_TYPE; diff --git a/src/common/sdk/nvidia/inc/nv_vgpu_types.h b/src/common/sdk/nvidia/inc/nv_vgpu_types.h index 388625a52..fae998595 100644 --- a/src/common/sdk/nvidia/inc/nv_vgpu_types.h +++ b/src/common/sdk/nvidia/inc/nv_vgpu_types.h @@ -39,8 +39,8 @@ /* ! XAPIGEN */ #define VM_UUID_SIZE 16 -#define INVALID_VGPU_DEV_INST 0xFFFFFFFF -#define MAX_VGPU_DEVICES_PER_VM 16 +#define INVALID_VGPU_DEV_INST 0xFFFFFFFFU +#define MAX_VGPU_DEVICES_PER_VM 16U /* This enum represents the current state of guest dependent fields */ typedef enum GUEST_VM_INFO_STATE { diff --git a/src/common/sdk/nvidia/inc/nverror.h b/src/common/sdk/nvidia/inc/nverror.h index bce7bea45..1e3a9ac87 100644 --- a/src/common/sdk/nvidia/inc/nverror.h +++ b/src/common/sdk/nvidia/inc/nverror.h @@ -32,9 +32,12 @@ * ******************************************************************************/ +#include "nvcfg_sdk.h" + #define ROBUST_CHANNEL_GR_EXCEPTION (13) #define ROBUST_CHANNEL_GR_ERROR_SW_NOTIFY (13) #define ROBUST_CHANNEL_FAKE_ERROR (14) +#define ROBUST_CHANNEL_VBLANK_CALLBACK_TIMEOUT (16) #define ROBUST_CHANNEL_DISP_MISSED_NOTIFIER (19) #define ROBUST_CHANNEL_MPEG_ERROR_SW_METHOD (20) #define ROBUST_CHANNEL_ME_ERROR_SW_METHOD (21) @@ -96,6 +99,16 @@ #define INFOROM_ERASE_LIMIT_EXCEEDED (93) #define ROBUST_CHANNEL_CONTAINED_ERROR (94) #define ROBUST_CHANNEL_UNCONTAINED_ERROR (95) +#define ROBUST_CHANNEL_NVDEC5_ERROR (96) +#define ROBUST_CHANNEL_NVDEC6_ERROR (97) +#define ROBUST_CHANNEL_NVDEC7_ERROR (98) +#define ROBUST_CHANNEL_NVJPG1_ERROR (99) +#define ROBUST_CHANNEL_NVJPG2_ERROR (100) +#define ROBUST_CHANNEL_NVJPG3_ERROR (101) +#define ROBUST_CHANNEL_NVJPG4_ERROR (102) +#define ROBUST_CHANNEL_NVJPG5_ERROR (103) +#define ROBUST_CHANNEL_NVJPG6_ERROR (104) +#define ROBUST_CHANNEL_NVJPG7_ERROR (105) #define SEC_FAULT_ERROR (110) #define GSP_RPC_TIMEOUT (119) #define GSP_ERROR (120) @@ -104,55 +117,65 @@ #define SPI_PMU_RPC_WRITE_FAIL (123) #define SPI_PMU_RPC_ERASE_FAIL (124) #define INFOROM_FS_ERROR (125) -#define ROBUST_CHANNEL_LAST_ERROR (INFOROM_FS_ERROR) +#define ALI_TRAINING_FAIL (136) +#define ROBUST_CHANNEL_LAST_ERROR (ALI_TRAINING_FAIL) + // Indexed CE reference #define ROBUST_CHANNEL_CE_ERROR(x) \ - (x < 3 ? ROBUST_CHANNEL_CE0_ERROR + (x) : \ - ((x < 6) ? (ROBUST_CHANNEL_CE3_ERROR + (x - 3)) : \ - ((x < 9) ? (ROBUST_CHANNEL_CE6_ERROR + (x - 6)) : \ - ROBUST_CHANNEL_CE9_ERROR))) + ((x < 3) ? \ + (ROBUST_CHANNEL_CE0_ERROR + (x)) : \ + ((x < 6) ? \ + (ROBUST_CHANNEL_CE3_ERROR + (x - 3)) : \ + ((x < 9) ? \ + (ROBUST_CHANNEL_CE6_ERROR + (x - 6)) : \ + (ROBUST_CHANNEL_CE9_ERROR)))) -#define ROBUST_CHANNEL_IS_CE_ERROR(x) \ - ((x == ROBUST_CHANNEL_CE0_ERROR) || (x == ROBUST_CHANNEL_CE1_ERROR) || \ - (x == ROBUST_CHANNEL_CE2_ERROR) || (x == ROBUST_CHANNEL_CE3_ERROR) || \ - (x == ROBUST_CHANNEL_CE4_ERROR) || (x == ROBUST_CHANNEL_CE5_ERROR) || \ - (x == ROBUST_CHANNEL_CE6_ERROR) || (x == ROBUST_CHANNEL_CE7_ERROR) || \ +#define ROBUST_CHANNEL_IS_CE_ERROR(x) \ + ((x == ROBUST_CHANNEL_CE0_ERROR) || (x == ROBUST_CHANNEL_CE1_ERROR) || \ + (x == ROBUST_CHANNEL_CE2_ERROR) || (x == ROBUST_CHANNEL_CE3_ERROR) || \ + (x == ROBUST_CHANNEL_CE4_ERROR) || (x == ROBUST_CHANNEL_CE5_ERROR) || \ + (x == ROBUST_CHANNEL_CE6_ERROR) || (x == ROBUST_CHANNEL_CE7_ERROR) || \ (x == ROBUST_CHANNEL_CE8_ERROR) || (x == ROBUST_CHANNEL_CE9_ERROR)) -#define ROBUST_CHANNEL_CE_ERROR_IDX(x) \ - (((x >= ROBUST_CHANNEL_CE0_ERROR) && (x <= ROBUST_CHANNEL_CE2_ERROR)) ? \ - (x - ROBUST_CHANNEL_CE0_ERROR) : \ - (((x >= ROBUST_CHANNEL_CE3_ERROR) && \ - (x <= ROBUST_CHANNEL_CE5_ERROR)) ? \ - (x - ROBUST_CHANNEL_CE3_ERROR) : \ - (((x >= ROBUST_CHANNEL_CE6_ERROR) && \ - (x <= ROBUST_CHANNEL_CE8_ERROR)) ? \ - (x - ROBUST_CHANNEL_CE6_ERROR) : \ - (x - ROBUST_CHANNEL_CE9_ERROR)))) +#define ROBUST_CHANNEL_CE_ERROR_IDX(x) \ + (((x >= ROBUST_CHANNEL_CE0_ERROR) && (x <= ROBUST_CHANNEL_CE2_ERROR)) ? \ + (x - ROBUST_CHANNEL_CE0_ERROR) : \ + (((x >= ROBUST_CHANNEL_CE3_ERROR) && (x <= ROBUST_CHANNEL_CE5_ERROR)) ? \ + (x - ROBUST_CHANNEL_CE3_ERROR + 3) : \ + (((x >= ROBUST_CHANNEL_CE6_ERROR) && (x <= ROBUST_CHANNEL_CE8_ERROR)) ? \ + (x - ROBUST_CHANNEL_CE6_ERROR + 6) : \ + (x - ROBUST_CHANNEL_CE9_ERROR + 9)))) // Indexed NVDEC reference -#define ROBUST_CHANNEL_NVDEC_ERROR(x) \ - ((x == 0) ? \ - (ROBUST_CHANNEL_NVDEC0_ERROR) : \ - (((x >= 1) && (x <= 2)) ? (ROBUST_CHANNEL_NVDEC1_ERROR + x - 1) : \ - (ROBUST_CHANNEL_NVDEC3_ERROR + x - 3))) +#define ROBUST_CHANNEL_NVDEC_ERROR(x) \ + ((x < 1) ? \ + (ROBUST_CHANNEL_NVDEC0_ERROR) : \ + ((x < 3) ? \ + (ROBUST_CHANNEL_NVDEC1_ERROR + (x - 1)) : \ + ((x < 5) ? \ + (ROBUST_CHANNEL_NVDEC3_ERROR + (x - 3)): \ + (ROBUST_CHANNEL_NVDEC5_ERROR + (x - 5))))) #define ROBUST_CHANNEL_IS_NVDEC_ERROR(x) \ ((x == ROBUST_CHANNEL_NVDEC0_ERROR) || \ (x == ROBUST_CHANNEL_NVDEC1_ERROR) || \ (x == ROBUST_CHANNEL_NVDEC2_ERROR) || \ (x == ROBUST_CHANNEL_NVDEC3_ERROR) || \ - (x == ROBUST_CHANNEL_NVDEC4_ERROR)) + (x == ROBUST_CHANNEL_NVDEC4_ERROR) || \ + (x == ROBUST_CHANNEL_NVDEC5_ERROR) || \ + (x == ROBUST_CHANNEL_NVDEC6_ERROR) || \ + (x == ROBUST_CHANNEL_NVDEC7_ERROR)) -#define ROBUST_CHANNEL_NVDEC_ERROR_IDX(x) \ - (((x == ROBUST_CHANNEL_NVDEC0_ERROR)) ? \ - (x - ROBUST_CHANNEL_NVDEC0_ERROR) : \ - (((x >= ROBUST_CHANNEL_NVDEC1_ERROR) && \ - (x <= ROBUST_CHANNEL_NVDEC2_ERROR)) ? \ - (x - ROBUST_CHANNEL_NVDEC1_ERROR + 1) : \ - (x - ROBUST_CHANNEL_NVDEC3_ERROR + 3))) +#define ROBUST_CHANNEL_NVDEC_ERROR_IDX(x) \ + ((x == ROBUST_CHANNEL_NVDEC0_ERROR) ? \ + (x - ROBUST_CHANNEL_NVDEC0_ERROR) : \ + (((x >= ROBUST_CHANNEL_NVDEC1_ERROR) && (x <= ROBUST_CHANNEL_NVDEC2_ERROR)) ? \ + (x - ROBUST_CHANNEL_NVDEC1_ERROR + 1) : \ + (((x >= ROBUST_CHANNEL_NVDEC3_ERROR) && (x <= ROBUST_CHANNEL_NVDEC4_ERROR)) ? \ + (x - ROBUST_CHANNEL_NVDEC3_ERROR + 3) : \ + (x - ROBUST_CHANNEL_NVDEC5_ERROR + 5)))) // Indexed NVENC reference #define ROBUST_CHANNEL_NVENC_ERROR(x) \ @@ -177,105 +200,4 @@ #define ROBUST_CHANNEL_ERROR_RECOVERY_LEVEL_NON_FATAL (1) #define ROBUST_CHANNEL_ERROR_RECOVERY_LEVEL_FATAL (2) -#define ROBUST_CHANNEL_ERROR_STR_PUBLIC_PUBLISHED \ - {"Unknown Error", \ - "DMA Engine Error (FIFO Error 1)", \ - "DMA Engine Error (FIFO Error 2)", \ - "DMA Engine Error (FIFO Error 3)", \ - "DMA Engine Error (FIFO Error 4)", \ - "DMA Engine Error (FIFO Error 5)", \ - "DMA Engine Error (FIFO Error 6)", \ - "DMA Engine Error (FIFO Error 7)", \ - "DMA Engine Error (FIFO Error 8)", \ - "Graphics Engine Error (GR Error 1)", \ - "Graphics Engine Error (GR Error 2)", \ - "Graphics Engine Error (GR Error 3)", \ - "Graphics Engine Error (GR Error 4)", \ - "Graphics Engine Error (GR Exception Error)",\ - "Fake Error", \ - "Display Engine Error (CRTC Error 1)", \ - "Display Engine Error (CRTC Error 2)", \ - "Display Engine Error (CRTC Error 3)", \ - "Bus Interface Error (BIF Error)", \ - "Client Reported Error", \ - "Video Engine Error (MPEG Error)", \ - "Video Engine Error (ME Error)", \ - "Video Engine Error (VP Error 1)", \ - "Error Reporting Enabled", \ - "Graphics Engine Error (GR Error 6)", \ - "Graphics Engine Error (GR Error 7)", \ - "DMA Engine Error (FIFO Error 9)", \ - "Video Engine Error (VP Error 2)", \ - "Video Engine Error (VP2 Error)", \ - "Video Engine Error (BSP Error)", \ - "Access Violation Error (MMU Error 1)", \ - "Access Violation Error (MMU Error 2)", \ - "DMA Engine Error (PBDMA Error)", \ - "Security Engine Error (SEC Error)", \ - "Video Engine Error (MSVLD Error)", \ - "Video Engine Error (MSPDEC Error)", \ - "Video Engine Error (MSPPP Error)", \ - "Graphics Engine Error (FECS Error 1)", \ - "Graphics Engine Error (FECS Error 2)", \ - "DMA Engine Error (CE Error 1)", \ - "DMA Engine Error (CE Error 2)", \ - "DMA Engine Error (CE Error 3)", \ - "Video Engine Error (VIC Error)", \ - "Verification Error", \ - "Access Violation Error (MMU Error 3)", \ - "Operating System Error (OS Error 1)", \ - "Operating System Error (OS Error 2)", \ - "Video Engine Error (MSENC/NVENC0 Error)",\ - "ECC Error (DBE Error)", \ - "Power State Locked", \ - "Power State Event (RC Error)", \ - "Power State Event (Stress Test Error)", \ - "Power State Event (Thermal Event 1)", \ - "Power State Event (Thermal Event 2)", \ - "Power State Event (Power Event)", \ - "Power State Event (Thermal Event 3)", \ - "Display Engine Error (EVO Error)", \ - "FB Interface Error (FBPA Error 1)", \ - "FB Interface Error (FBPA Error 2)", \ - "PMU error", \ - "SEC2 error", \ - "PMU Breakpoint (non-fatal)", \ - "PMU Halt Error", \ - "INFOROM Page Retirement Event", \ - "INFOROM Page Retirement Failure", \ - "Video Engine Error (NVENC1 Error)", \ - "Graphics Engine Error (FECS Error 3)", \ - "Graphics Engine Error (FECS Error 4)", \ - "Video Engine Error (NVDEC0 Error)", \ - "Graphics Engine Error (GR Class Error)",\ - "DMA Engine Error (CE Error 4)", \ - "DMA Engine Error (CE Error 5)", \ - "DMA Engine Error (CE Error 6)", \ - "Video Engine Error (NVENC2 Error)", \ - "NVLink Error", \ - "DMA Engine Error (CE Error 6)", \ - "DMA Engine Error (CE Error 7)", \ - "DMA Engine Error (CE Error 8)", \ - "vGPU device cannot be started", \ - "GPU has fallen off the bus", \ - "DMA Engine Error (Pushbuffer CRC mismatch)",\ - "VGA Subsystem Error", \ - "Video JPEG Engine Error (NVJPG Error)", \ - "Video Engine Error (NVDEC1 Error)", \ - "Video Engine Error (NVDEC2 Error)", \ - "DMA Engine Error (CE Error 9)", \ - "Video OFA Engine Error (OFA0 Error)", \ - "NvTelemetry Driver Reoprt", \ - "Video Engine Error (NVDEC3 Error)", \ - "Video Engine Error (NVDEC4 Error)", \ - "FB Interface Error (FBPA Error 3)", \ - "Reserved Xid", \ - "Excessive SBE interrupts", \ - "INFOROM Erase Limit Exceeded", \ - "Contained error", \ - "Uncontained error" - -#define ROBUST_CHANNEL_ERROR_STR_PUBLIC \ - ROBUST_CHANNEL_ERROR_STR_PUBLIC_PUBLISHED} - #endif // NVERROR_H diff --git a/src/common/sdk/nvidia/inc/nvgputypes.h b/src/common/sdk/nvidia/inc/nvgputypes.h index 59ba45b3d..d01841467 100644 --- a/src/common/sdk/nvidia/inc/nvgputypes.h +++ b/src/common/sdk/nvidia/inc/nvgputypes.h @@ -150,9 +150,7 @@ typedef struct NvSyncPointFenceRec { |* *| \***************************************************************************/ -#if !defined(XAPIGEN) /* NvOffset is XAPIGEN builtin type, so skip typedef */ typedef NvU64 NvOffset; /* GPU address */ -#endif #define NvOffset_HI32(n) ((NvU32)(((NvU64)(n)) >> 32)) #define NvOffset_LO32(n) ((NvU32)((NvU64)(n))) diff --git a/src/common/sdk/nvidia/inc/nvmisc.h b/src/common/sdk/nvidia/inc/nvmisc.h index 210e23798..fa33a9ffd 100644 --- a/src/common/sdk/nvidia/inc/nvmisc.h +++ b/src/common/sdk/nvidia/inc/nvmisc.h @@ -234,12 +234,14 @@ extern "C" { #define DRF_EXTENT(drf) (drf##_HIGH_FIELD) #define DRF_SHIFT(drf) ((drf##_LOW_FIELD) % 32U) #define DRF_SHIFT_RT(drf) ((drf##_HIGH_FIELD) % 32U) +#define DRF_SIZE(drf) ((drf##_HIGH_FIELD)-(drf##_LOW_FIELD)+1U) #define DRF_MASK(drf) (0xFFFFFFFFU >> (31U - ((drf##_HIGH_FIELD) % 32U) + ((drf##_LOW_FIELD) % 32U))) #else #define DRF_BASE(drf) (NV_FALSE?drf) // much better #define DRF_EXTENT(drf) (NV_TRUE?drf) // much better #define DRF_SHIFT(drf) (((NvU32)DRF_BASE(drf)) % 32U) #define DRF_SHIFT_RT(drf) (((NvU32)DRF_EXTENT(drf)) % 32U) +#define DRF_SIZE(drf) (DRF_EXTENT(drf)-DRF_BASE(drf)+1U) #define DRF_MASK(drf) (0xFFFFFFFFU>>(31U - DRF_SHIFT_RT(drf) + DRF_SHIFT(drf))) #endif #define DRF_DEF(d,r,f,c) (((NvU32)(NV ## d ## r ## f ## c))<>(31-((DRF_ISBIT(1,drf)) % 32)+((DRF_ISBIT(0,drf)) % 32))) #define DRF_DEF(d,r,f,c) ((NV ## d ## r ## f ## c)<>DRF_SHIFT(NV ## d ## r ## f))&DRF_MASK(NV ## d ## r ## f)) #endif @@ -907,6 +909,16 @@ static NV_FORCEINLINE void *NV_NVUPTR_TO_PTR(NvUPtr address) return uAddr.p; } +// Get bit at pos (k) from x +#define NV_BIT_GET(k, x) (((x) >> (k)) & 1) +// Get bit at pos (n) from (hi) if >= 64, otherwise from (lo). This is paired with NV_BIT_SET_128 which sets the bit. +#define NV_BIT_GET_128(n, lo, hi) (((n) < 64) ? NV_BIT_GET((n), (lo)) : NV_BIT_GET((n) - 64, (hi))) +// +// Set the bit at pos (b) for U64 which is < 128. Since the (b) can be >= 64, we need 2 U64 to store this. +// Use (lo) if (b) is less than 64, and (hi) if >= 64. +// +#define NV_BIT_SET_128(b, lo, hi) { nvAssert( (b) < 128 ); if ( (b) < 64 ) (lo) |= NVBIT64(b); else (hi) |= NVBIT64( b & 0x3F ); } + #ifdef __cplusplus } #endif //__cplusplus diff --git a/src/common/sdk/nvidia/inc/nvos.h b/src/common/sdk/nvidia/inc/nvos.h index 99a4eb896..4fb187071 100644 --- a/src/common/sdk/nvidia/inc/nvos.h +++ b/src/common/sdk/nvidia/inc/nvos.h @@ -42,6 +42,10 @@ extern "C" { #include "rs_access.h" #include "nvcfg_sdk.h" + +// Temporary include. Please include this directly instead of nvos.h +#include "alloc/alloc_channel.h" + /* local defines here */ #define FILE_DEVICE_NV 0x00008000 #define NV_IOCTL_FCT_BASE 0x00000800 @@ -160,7 +164,7 @@ typedef struct } NVOS00_PARAMETERS; /* valid hClass values. */ -#define NV01_ROOT (0x00000000) +#define NV01_ROOT (0x0U) // // Redefining it here to maintain consistency with current code // This is also defined in class cl0001.h @@ -443,6 +447,9 @@ typedef struct NvV32 status; } NVOS21_PARAMETERS; +#define NVOS64_FLAGS_NONE (0x00000000) +#define NVOS64_FLAGS_FINN_SERIALIZED (0x00000001) + /* New struct with rights requested */ typedef struct { @@ -452,6 +459,7 @@ typedef struct NvV32 hClass; // [in] class num of new object NvP64 pAllocParms NV_ALIGN_BYTES(8); // [IN] class-specific alloc parameters NvP64 pRightsRequested NV_ALIGN_BYTES(8); // [IN] RS_ACCESS_MASK to request rights, or NULL + NvU32 flags; // [IN] flags for FINN serialization NvV32 status; // [OUT] status } NVOS64_PARAMETERS; @@ -1847,23 +1855,6 @@ typedef struct NvU32 flags; } NVOS34_PARAMETERS; -/* function OS37 */ -#define NV04_UPDATE_CONTEXT_DMA (0x00000025) - -/* parameters */ -typedef struct -{ - NvHandle hClient; - NvHandle hDevice; - NvHandle hDma; - NvHandle hDmaPteArray; // ctx dma for pte's - NvV32 dmaFirstPage; // first page in "real" context dma to update - NvV32 pteArrayOffset; // first pte to use from input pte array - NvV32 pteCount; // count of PTE entries to update - NvHandle hResourceHandle; // bind data handle - NvV32 status; -} NVOS37_PARAMETERS; - /* function OS38 */ #define NV04_ACCESS_REGISTRY (0x00000026) @@ -2118,9 +2109,6 @@ typedef struct #define NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC 29:29 #define NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_FALSE (0x00000000) #define NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_TRUE (0x00000001) -#define NVOS46_FLAGS_DR_SURF 30:30 -#define NVOS46_FLAGS_DR_SURF_FALSE (0x00000000) -#define NVOS46_FLAGS_DR_SURF_TRUE (0x00000001) // // This flag must be used with caution. Improper use can leave stale entries in the TLB, // and allow access to memory no longer owned by the RM client or cause page faults. @@ -2185,6 +2173,7 @@ typedef struct #define NVOS54_FLAGS_NONE (0x00000000) #define NVOS54_FLAGS_IRQL_RAISED (0x00000001) #define NVOS54_FLAGS_LOCK_BYPASS (0x00000002) +#define NVOS54_FLAGS_FINN_SERIALIZED (0x00000004) /* parameters */ typedef struct @@ -2403,7 +2392,7 @@ typedef struct { // // Indicates this device is being created by guest and requires a -// HostVgpuDeviceKernel creation in client. +// KernelHostVgpuDeviceApi creation in client. // #define NV_DEVICE_ALLOCATION_FLAGS_HOST_VGPU_DEVICE (0x00002000) @@ -2414,269 +2403,16 @@ typedef struct { // #define NV_DEVICE_ALLOCATION_FLAGS_PLUGIN_CONTEXT (0x00004000) +// +// For clients using unlinked SLI to catch allocations attempts on secondary GPUs +// not accompanied by a fixed offset. +// +#define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_REQUIRE_FIXED_OFFSET (0x00008000) + #define NV_DEVICE_ALLOCATION_VAMODE_OPTIONAL_MULTIPLE_VASPACES (0x00000000) #define NV_DEVICE_ALLOCATION_VAMODE_SINGLE_VASPACE (0x00000001) #define NV_DEVICE_ALLOCATION_VAMODE_MULTIPLE_VASPACES (0x00000002) -/* - * NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS.flags values. - * - * These flags may apply to all channel types: PIO, DMA, and GPFIFO. - * They are also designed so that zero is always the correct default. - * - * NVOS04_FLAGS_CHANNEL_TYPE: - * This flag specifies the type of channel to allocate. Legal values - * for this flag include: - * - * NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL: - * This flag specifies that a physical channel is to be allocated. - * - * NVOS04_FLAGS_CHANNEL_TYPE_VIRTUAL: - * OBSOLETE - NOT SUPPORTED - * - * NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL_FOR_VIRTUAL: - * OBSOLETE - NOT SUPPORTED - */ - -/* valid NVOS04_FLAGS_CHANNEL_TYPE values */ -#define NVOS04_FLAGS_CHANNEL_TYPE 1:0 -#define NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL 0x00000000 -#define NVOS04_FLAGS_CHANNEL_TYPE_VIRTUAL 0x00000001 // OBSOLETE -#define NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL_FOR_VIRTUAL 0x00000002 // OBSOLETE - -/* - * NVOS04_FLAGS_VPR: - * This flag specifies if channel is intended for work with - * Video Protected Regions (VPR) - * - * NVOS04_FLAGS_VPR_TRUE: - * The channel will only write to protected memory regions. - * - * NVOS04_FLAGS_VPR_FALSE: - * The channel will never read from protected memory regions. - */ -#define NVOS04_FLAGS_VPR 2:2 -#define NVOS04_FLAGS_VPR_FALSE 0x00000000 -#define NVOS04_FLAGS_VPR_TRUE 0x00000001 - -/* - * NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING: - * This flag specifies if the channel can skip refcounting of potentially - * accessed mappings on job kickoff. This flag is only meaningful for - * kernel drivers which perform refcounting of memory mappings. - * - * NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_FALSE: - * The channel cannot not skip refcounting of memory mappings - * - * NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_TRUE: - * The channel can skip refcounting of memory mappings - */ -#define NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING 3:3 -#define NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_FALSE 0x00000000 -#define NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_TRUE 0x00000001 - -/* - * NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE: - * This flag specifies which "runqueue" the allocated channel will be - * executed on in a TSG. Channels on different runqueues within a TSG - * may be able to feed methods into the engine simultaneously. - * Non-default values are only supported on GP10x and later and only for - * channels within a TSG. - */ -#define NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE 4:4 -#define NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_DEFAULT 0x00000000 -#define NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_ONE 0x00000001 - -/* - * NVOS04_FLAGS_PRIVILEGED_CHANNEL: - * This flag tells RM whether to give the channel admin privilege. This - * flag will only take effect if the client is GSP-vGPU plugin. It is - * needed so that guest can update page tables in physical mode and do - * scrubbing. - */ -#define NVOS04_FLAGS_PRIVILEGED_CHANNEL 5:5 -#define NVOS04_FLAGS_PRIVILEGED_CHANNEL_FALSE 0x00000000 -#define NVOS04_FLAGS_PRIVILEGED_CHANNEL_TRUE 0x00000001 - -/* - * NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING: - * This flags tells RM not to schedule a newly created channel within a - * channel group immediately even if channel group is currently scheduled. - * Channel will not be scheduled until NVA06F_CTRL_GPFIFO_SCHEDULE is - * invoked. This is used eg. for CUDA which needs to do additional - * initialization before starting up a channel. - * Default is FALSE. - */ -#define NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING 6:6 -#define NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_FALSE 0x00000000 -#define NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_TRUE 0x00000001 - -/* - * NVOS04_FLAGS_DENY_PHYSICAL_MODE_CE: - * This flag specifies whether or not to deny access to the physical - * mode of CopyEngine regardless of whether or not the client handle - * is admin. If set to true, this channel allocation will always result - * in an unprivileged channel. If set to false, the privilege of the channel - * will depend on the privilege level of the client handle. - * This is primarily meant for vGPU since all client handles - * granted to guests are admin. - */ -#define NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE 7:7 -#define NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_FALSE 0x00000000 -#define NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_TRUE 0x00000001 - -/* - * NVOS04_FLAGS_CHANNEL_USERD_INDEX_VALUE - * - * This flag specifies the channel offset in terms of within a page of - * USERD. For example, value 3 means the 4th channel within a USERD page. - * Given the USERD size is 512B, we will have 8 channels total, so 3 bits - * are reserved. - * - * When _USERD_INDEX_FIXED_TRUE is set but INDEX_PAGE_FIXED_FALSE is set, - * it will ask for a new USERD page. - * - */ -#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_VALUE 10:8 - -#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED 11:11 -#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_FALSE 0x00000000 -#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_TRUE 0x00000001 - -/* - * NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_VALUE - * - * This flag specifies the channel offset in terms of USERD page. When - * this PAGE_FIXED_TRUE is set, the INDEX_FIXED_FALSE bit should also - * be set, otherwise INVALID_STATE will be returned. - * - * And the field _USERD_INDEX_VALUE will be used to request the specific - * offset within a USERD page. - */ - -#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_VALUE 20:12 - -#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED 21:21 -#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_FALSE 0x00000000 -#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_TRUE 0x00000001 - -/* - * NVOS04_FLAGS_DENY_AUTH_LEVEL_PRIV - * This flag specifies whether or not to deny access to the privileged - * host methods TLB_INVALIDATE and ACCESS_COUNTER_CLR - */ -#define NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV 22:22 -#define NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_FALSE 0x00000000 -#define NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_TRUE 0x00000001 - -/* - * NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER - * - * This flag specifies scrubbing should be skipped for any internal - * allocations made for this channel from PMA using ctx buf pools. - * Only kernel clients are allowed to use this setting. - */ -#define NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER 23:23 -#define NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_FALSE 0x00000000 -#define NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_TRUE 0x00000001 - -/* - * NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO - * - * This flag specifies that the client is expected to map USERD themselves - * and RM need not do so. - */ -#define NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO 24:24 -#define NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_FALSE 0x00000000 -#define NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_TRUE 0x00000001 - -/* - * NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL - */ -#define NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL 25:25 -#define NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_FALSE 0x00000000 -#define NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_TRUE 0x00000001 - -/* - * NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT - * - * This flag specifies whether the channel calling context is from CPU - * VGPU plugin. - */ -#define NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT 26:26 -#define NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_FALSE 0x00000000 -#define NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_TRUE 0x00000001 - - /* - * NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT - * - * This flag specifies the channel PBDMA ACQUIRE timeout option. - * _FALSE to disable it, _TRUE to enable it. - * When this flag is enabled, if a host semaphore acquire does not - * complete in about 2 sec, it will time out and trigger a RC error. - */ -#define NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT 27:27 -#define NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_FALSE 0x00000000 -#define NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_TRUE 0x00000001 - -/* - * NVOS04_FLAGS_GROUP_CHANNEL_THREAD: - * This flags specifies the thread id in which an allocated channel - * will be executed in a TSG. The relationship between the thread id - * in A TSG and respective definitions are implementation specific. - * Also, not all classes will be supported at thread > 0. - * This field cannot be used on non-TSG channels and must be set to - * the default value (0) in that case. If thread > 0 on a non-TSG - * channel, the allocation will fail - */ -#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD 29:28 -#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD_DEFAULT 0x00000000 -#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD_ONE 0x00000001 -#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD_TWO 0x00000002 - -#define NVOS04_FLAGS_MAP_CHANNEL 30:30 -#define NVOS04_FLAGS_MAP_CHANNEL_FALSE 0x00000000 -#define NVOS04_FLAGS_MAP_CHANNEL_TRUE 0x00000001 - -#define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC 31:31 -#define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_FALSE 0x00000000 -#define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_TRUE 0x00000001 - -typedef struct -{ - NvU64 base NV_ALIGN_BYTES(8); - NvU64 size NV_ALIGN_BYTES(8); - NvU32 addressSpace; - NvU32 cacheAttrib; -} NV_MEMORY_DESC_PARAMS; - -typedef struct -{ - NvHandle hObjectError; // error context DMA - NvHandle hObjectBuffer; // no longer used - NvU64 gpFifoOffset NV_ALIGN_BYTES(8); // offset to beginning of GP FIFO - NvU32 gpFifoEntries; // number of GP FIFO entries - NvU32 flags; - NvHandle hContextShare; // context share handle - NvHandle hVASpace; // VASpace for the channel - NvHandle hUserdMemory[NVOS_MAX_SUBDEVICES]; // handle to UserD memory object for channel, ignored if hUserdMemory[0]=0 - NvU64 userdOffset[NVOS_MAX_SUBDEVICES] NV_ALIGN_BYTES(8); // offset to beginning of UserD within hUserdMemory[x] - NvU32 engineType; // engine type(NV2080_ENGINE_TYPE_*) with which this channel is associated - NvU32 cid; // Channel identifier that is unique for the duration of a RM session - NvU32 subDeviceId; // One-hot encoded bitmask to match SET_SUBDEVICE_MASK methods - NvHandle hObjectEccError; // ECC error context DMA - NV_MEMORY_DESC_PARAMS instanceMem; - NV_MEMORY_DESC_PARAMS userdMem; - NV_MEMORY_DESC_PARAMS ramfcMem; - NV_MEMORY_DESC_PARAMS mthdbufMem; - - NvHandle hPhysChannelGroup; // reserved - NvU32 internalFlags; // reserved - NV_MEMORY_DESC_PARAMS errorNotifierMem; // reserved - NV_MEMORY_DESC_PARAMS eccErrorNotifierMem; // reserved - NvU32 ProcessID; // reserved - NvU32 SubProcessID; // reserved -} NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS; #define NV_CHANNELGPFIFO_NOTIFICATION_TYPE_ERROR 0x00000000 #define NV_CHANNELGPFIFO_NOTIFICATION_TYPE_WORK_SUBMIT_TOKEN 0x00000001 @@ -2686,18 +2422,6 @@ typedef struct #define NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS_TRUE 0x1 #define NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS_FALSE 0x0 -typedef struct -{ - NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS gpfifoAllocationParams; - NvHandle hKernelChannel; -} NV_PHYSICALCHANNEL_ALLOC_PARAMS; - -typedef struct -{ - NvHandle hRunlistBase; // Handle to physmem runlist base - NvU32 engineID; // Engine associated with the runlist -} NV_CHANNELRUNLIST_ALLOCATION_PARAMETERS; - typedef struct { NvV32 channelInstance; // One of the n channel instances of a given channel type. @@ -2837,53 +2561,6 @@ typedef struct NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of OFA? } NV_OFA_ALLOCATION_PARAMETERS; -#define NV04_BIND_ARBITRARY_CONTEXT_DMA (0x00000039) - -/* parameters */ - -#define NV04_GET_MEMORY_INFO (0x0000003A) - -typedef struct -{ - NvHandle hClient; // [IN] client handle - NvHandle hDevice; // [IN] device handle for mapping - NvHandle hMemory; // [IN] memory handle for mapping - NvU64 offset NV_ALIGN_BYTES(8); // [IN] offset of region - NvU64 physAddr NV_ALIGN_BYTES(8); // [OUT] Physical Addr - NvV32 status; // [OUT] status -} NVOS58_PARAMETERS; - -/* function OS59 */ -#define NV04_MAP_MEMORY_DMA_OFFSET (0x0000003B) - -/* parameters */ -typedef struct -{ - NvHandle hClient; // [IN] client handle - NvHandle hDevice; // [IN] device handle for mapping - NvHandle hDma; // [IN] dma handle for mapping - NvU32 dmaFirstPage; // [IN] numPages - NvU32 numPages; // [IN] numPages - NvV32 flags; // [IN] flags - NvU64 offset NV_ALIGN_BYTES(8); // [IN] Dma Offset - NvHandle hDmaPteArray; // ctx dma for pte's - NvV32 status; // [OUT] status -} NVOS59_PARAMETERS; - -/* function OS60 */ -#define NV04_UNMAP_MEMORY_DMA_OFFSET (0x0000003C) -/* parameters */ -typedef struct -{ - NvHandle hClient; // [IN] client handle - NvHandle hDevice; // [IN] device handle for mapping - NvHandle hDma; // [IN] dma handle for mapping - NvU32 numPages; // [IN] numPages - NvU64 dmaOffset NV_ALIGN_BYTES(8); // [IN] dmaOffset - NvV32 status; // [OUT] status -} NVOS60_PARAMETERS; - - #define NV04_ADD_VBLANK_CALLBACK (0x0000003D) #include "class/cl9010.h" // for OSVBLANKCALLBACKPROC @@ -3041,6 +2718,7 @@ typedef struct #define NV_VASPACE_ALLOCATION_FLAGS_IS_FLA BIT(9) #define NV_VASPACE_ALLOCATION_FLAGS_SKIP_SCRUB_MEMPOOL BIT(10) #define NV_VASPACE_ALLOCATION_FLAGS_OPTIMIZE_PTETABLE_MEMPOOL_USAGE BIT(11) +#define NV_VASPACE_ALLOCATION_FLAGS_REQUIRE_FIXED_OFFSET BIT(12) #define NV_VASPACE_ALLOCATION_INDEX_GPU_NEW 0x00 // +#include + +/* + * This header file defines static inline functions to manage 3D class + * color targets. + */ + +static inline void nv3dSelectColorTarget( + Nv3dChannelPtr p3dChannel, + NvU8 colorTargetIndex) +{ + NvPushChannelPtr p = p3dChannel->pPushChannel; + + nvPushImmedVal(p, NVA06F_SUBCHANNEL_3D, NV9097_SET_CT_SELECT, + NV3D_V(9097, SET_CT_SELECT, TARGET_COUNT, 1) | + NV3D_V(9097, SET_CT_SELECT, TARGET0, colorTargetIndex) | + NV3D_V(9097, SET_CT_SELECT, TARGET1, 0) | + NV3D_V(9097, SET_CT_SELECT, TARGET2, 0) | + NV3D_V(9097, SET_CT_SELECT, TARGET3, 0) | + NV3D_V(9097, SET_CT_SELECT, TARGET4, 0) | + NV3D_V(9097, SET_CT_SELECT, TARGET5, 0) | + NV3D_V(9097, SET_CT_SELECT, TARGET6, 0) | + NV3D_V(9097, SET_CT_SELECT, TARGET7, 0)); +} + +static inline void nv3dSetColorTarget( + Nv3dChannelPtr p3dChannel, + NvU8 colorTargetIndex, + NvU32 surfaceFormat, + NvU64 surfaceGpuAddress, + NvBool blockLinear, + Nv3dBlockLinearLog2GobsPerBlock gobsPerBlock, + NvU32 surfaceWidth, + NvU32 surfaceHeight) +{ + NvPushChannelPtr p = p3dChannel->pPushChannel; + + const NvU32 memoryInfo = + blockLinear ? + (NV3D_V(9097, SET_COLOR_TARGET_MEMORY, BLOCK_WIDTH, gobsPerBlock.x) | + NV3D_V(9097, SET_COLOR_TARGET_MEMORY, BLOCK_HEIGHT, gobsPerBlock.y) | + NV3D_V(9097, SET_COLOR_TARGET_MEMORY, BLOCK_DEPTH, gobsPerBlock.z) | + NV3D_C(9097, SET_COLOR_TARGET_MEMORY, LAYOUT, BLOCKLINEAR)) : + NV3D_C(9097, SET_COLOR_TARGET_MEMORY, LAYOUT, PITCH); + + if (surfaceFormat == NV9097_SET_COLOR_TARGET_FORMAT_V_DISABLED) { + // Disable this color target. + nvPushImmedVal(p, NVA06F_SUBCHANNEL_3D, + NV9097_SET_COLOR_TARGET_FORMAT(colorTargetIndex), + NV9097_SET_COLOR_TARGET_FORMAT_V_DISABLED); + return; + } + + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, + NV9097_SET_COLOR_TARGET_A(colorTargetIndex), 6); + + nvPushSetMethodDataU64(p, surfaceGpuAddress); + nvPushSetMethodData(p, surfaceWidth); + nvPushSetMethodData(p, surfaceHeight); + nvPushSetMethodData(p, surfaceFormat); + nvPushSetMethodData(p, memoryInfo); +} + +#endif /* __NVIDIA_3D_COLOR_TARGETS_H__ */ diff --git a/src/common/unix/nvidia-3d/interface/nvidia-3d-constant-buffers.h b/src/common/unix/nvidia-3d/interface/nvidia-3d-constant-buffers.h new file mode 100644 index 000000000..3587f7a27 --- /dev/null +++ b/src/common/unix/nvidia-3d/interface/nvidia-3d-constant-buffers.h @@ -0,0 +1,196 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVIDIA_3D_CONSTANT_BUFFERS_H__ +#define __NVIDIA_3D_CONSTANT_BUFFERS_H__ + +#include "nvidia-3d.h" + +#include +#include + +/* + * This header file defines static inline functions to manage 3D class + * constant buffers. + */ + + +static inline void nv3dSelectCbAddress( + Nv3dChannelRec *p3dChannel, + NvU64 offset, + NvU32 size) +{ + NvPushChannelPtr p = p3dChannel->pPushChannel; + + nvAssert(size > 0); + nvAssert(NV_IS_ALIGNED(size, NV3D_MIN_CONSTBUF_ALIGNMENT)); + nvAssert(size <= 65536); + nvAssert(NV_IS_ALIGNED(offset, NV3D_MIN_CONSTBUF_ALIGNMENT)); + + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, + NV9097_SET_CONSTANT_BUFFER_SELECTOR_A, 3); + nvPushSetMethodData(p, size); + nvPushSetMethodDataU64(p, offset); +} + +/*! + * Select a constant buffer for binding or updating. + */ +static inline void nv3dSelectCb( + Nv3dChannelRec *p3dChannel, + int constantBufferIndex) +{ + const NvU64 gpuAddress = + nv3dGetConstantBufferGpuAddress(p3dChannel, constantBufferIndex); + + nv3dSelectCbAddress(p3dChannel, gpuAddress, NV3D_CONSTANT_BUFFER_SIZE); +} + +/*! + * Bind the selected Cb to a given slot (or invalidate that slot). + */ +static inline void nv3dBindCb( + Nv3dChannelRec *p3dChannel, + int bindGroup, // XXX TODO: this type should be NVShaderBindGroup + int slot, + NvBool valid) +{ + NvPushChannelPtr p = p3dChannel->pPushChannel; + + ASSERT_DRF_NUM(9097, _BIND_GROUP_CONSTANT_BUFFER, _SHADER_SLOT, slot); + + nvPushImmedVal(p, NVA06F_SUBCHANNEL_3D, + NV9097_BIND_GROUP_CONSTANT_BUFFER(bindGroup), + NV3D_V(9097, BIND_GROUP_CONSTANT_BUFFER, VALID, !!valid) | + NV3D_V(9097, BIND_GROUP_CONSTANT_BUFFER, SHADER_SLOT, slot)); +} + +/*! + * Push *only the header* to tell the GPU to "load" constants from the + * pushbuffer. + * + * \param[in] p3dChannel The nvidia-3d channel. + * \param[in] offset The offset in bytes of the start of the + * updates. + * \param[in] dwords Count of dwords to be loaded (after the + * header). + * + * \return An NvPushChannelUnion pointing immediately after the + * header, with enough contiguous space to copy 'dwords' of + * data. + */ +static inline NvPushChannelUnion *nv3dLoadConstantsHeader( + Nv3dChannelRec *p3dChannel, + NvU32 offset, + size_t dwords) +{ + NvPushChannelPtr p = p3dChannel->pPushChannel; + NvPushChannelUnion *buffer; + + nvAssert((dwords + 1) <= nvPushMaxMethodCount(p)); + + nvPushMethodOneIncr(p, NVA06F_SUBCHANNEL_3D, + NV9097_LOAD_CONSTANT_BUFFER_OFFSET, dwords + 1); + nvPushSetMethodData(p, offset); + + buffer = p->main.buffer; + p->main.buffer += dwords; + + return buffer; +} + +/*! + * Load an array of bytes into a constant buffer at a specified location. + * + * The count must be a multiple of 4 bytes. + * + * \param[in] p3dChannel The nvidia-3d channel. + * \param[in] offset The offset in bytes of the start of the + * updates. + * \param[in] bytes Count of bytes to write. Must be a + * multiple of 4. + * \param[in] values Data to be written. + */ +static inline void nv3dLoadConstants( + Nv3dChannelRec *p3dChannel, + NvU32 offset, + size_t bytes, + const void *values) +{ + const size_t dwords = bytes / 4; + NvPushChannelUnion *buffer; + + nvAssert((bytes & 3) == 0); + + buffer = nv3dLoadConstantsHeader(p3dChannel, offset, dwords); + + nvDmaMoveDWORDS(buffer, values, dwords); +} + +/*! + * Set the current constant buffer's current byte offset, for use with + * nv3dPushConstants(). + */ +static inline void nv3dSetConstantBufferOffset( + Nv3dChannelRec *p3dChannel, + NvU32 offset) +{ + NvPushChannelPtr p = p3dChannel->pPushChannel; + + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, + NV9097_LOAD_CONSTANT_BUFFER_OFFSET, 1); + nvPushSetMethodData(p, offset); +} + +// Load an array of dwords into a constant buffer at the current location. This +// also advances the constant buffer load offset, so that multiple calls to +// nv3dPushConstants will write to sequential memory addresses. +static inline void nv3dPushConstants( + Nv3dChannelRec *p3dChannel, + size_t bytes, + const void *values) +{ + NvPushChannelPtr p = p3dChannel->pPushChannel; + const size_t dwords = bytes / 4; + nvAssert((bytes & 3) == 0); + nvAssert(dwords <= nvPushMaxMethodCount(p)); + + nvPushMethodNoIncr(p, NVA06F_SUBCHANNEL_3D, + NV9097_LOAD_CONSTANT_BUFFER(0), dwords); + nvPushInlineData(p, values, dwords); +} + +static inline void nv3dLoadSingleConstant( + Nv3dChannelRec *p3dChannel, + NvU32 offset, + NvU32 value) +{ + NvPushChannelPtr p = p3dChannel->pPushChannel; + + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, + NV9097_LOAD_CONSTANT_BUFFER_OFFSET, 2); + nvPushSetMethodData(p, offset); + nvPushSetMethodData(p, value); +} + +#endif /* __NVIDIA_3D_CONSTANT_BUFFERS_H__ */ diff --git a/src/common/unix/nvidia-3d/interface/nvidia-3d-imports.h b/src/common/unix/nvidia-3d/interface/nvidia-3d-imports.h new file mode 100644 index 000000000..839a2da59 --- /dev/null +++ b/src/common/unix/nvidia-3d/interface/nvidia-3d-imports.h @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * nvidia-3d-imports.h declares functions with nvidia-3d host drivers must + * provide. + */ + +#ifndef __NVIDIA_3D_IMPORTS_H__ +#define __NVIDIA_3D_IMPORTS_H__ + +#include /* size_t */ + +void *nv3dImportAlloc(size_t size); +void nv3dImportFree(void *ptr); +int nv3dImportMemCmp(const void *a, const void *b, size_t size); +void nv3dImportMemSet(void *s, int c, size_t size); +void nv3dImportMemCpy(void *dest, const void *src, size_t size); +void nv3dImportMemMove(void *dest, const void *src, size_t size); + +#endif /* __NVIDIA_3D_IMPORTS_H__ */ diff --git a/src/common/unix/nvidia-3d/interface/nvidia-3d-shader-constants.h b/src/common/unix/nvidia-3d/interface/nvidia-3d-shader-constants.h new file mode 100644 index 000000000..b6e210c50 --- /dev/null +++ b/src/common/unix/nvidia-3d/interface/nvidia-3d-shader-constants.h @@ -0,0 +1,53 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _NVIDIA_3D_SHADER_CONSTANTS_H_ +#define _NVIDIA_3D_SHADER_CONSTANTS_H_ + +#if defined(NV3D_BUILD_AS_GLSL) + + #define NV3D_CB_SLOT_FIRST_USER_BINDABLE 0 + +#else + + /* Shaders always use this slot for compiler-emitted constants. This + * assumption is verified at ucode build time. */ + #define NV3D_CB_SLOT_COMPILER 1 + + /* Offset between GLSL slot 0 and hardware slot */ + #define NV3D_CB_SLOT_FIRST_USER_BINDABLE 3 + +#endif + +/* This slot is used for most uniforms/constants defined in each shader */ +#define NV3D_CB_SLOT_MISC1 (NV3D_CB_SLOT_FIRST_USER_BINDABLE + 0) + +/* When needed (Kepler+), shaders always use this constant slot for bindless + * texture handles. */ +#define NV3D_CB_SLOT_BINDLESS_TEXTURE (NV3D_CB_SLOT_FIRST_USER_BINDABLE + 1) + + +/* Matches __GL_PGM_UNUSED_TEXTURE_UNIT */ +#define NV3D_TEX_BINDING_UNUSED 255 + +#endif /* _NVIDIA_3D_SHADER_CONSTANTS_H_ */ diff --git a/src/common/unix/nvidia-3d/interface/nvidia-3d-shaders.h b/src/common/unix/nvidia-3d/interface/nvidia-3d-shaders.h new file mode 100644 index 000000000..3e8c75a9d --- /dev/null +++ b/src/common/unix/nvidia-3d/interface/nvidia-3d-shaders.h @@ -0,0 +1,69 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2010-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVIDIA_3D_SHADERS_H__ +#define __NVIDIA_3D_SHADERS_H__ + +#include +#include + +// These are used in the "shader type" field below +#define NV3D_SHADER_TYPE_VERTEX NV9097_SET_PIPELINE_SHADER_TYPE_VERTEX +#define NV3D_SHADER_TYPE_PIXEL NV9097_SET_PIPELINE_SHADER_TYPE_PIXEL + +typedef enum { + NV3D_HW_SHADER_STAGE_VERTEX_A = 0, + NV3D_HW_SHADER_STAGE_VERTEX_B, + NV3D_HW_SHADER_STAGE_TESS_CONTROL, + NV3D_HW_SHADER_STAGE_TESS_EVAL, + NV3D_HW_SHADER_STAGE_GEOMETRY, + NV3D_HW_SHADER_STAGE_PIXEL, + NV3D_HW_SHADER_STAGE_COUNT, +} __attribute__ ((__packed__)) Nv3dShaderStage; + +typedef enum { + NV3D_HW_BIND_GROUP_VERTEX = 0, + NV3D_HW_BIND_GROUP_TESS_CONTROL, + NV3D_HW_BIND_GROUP_TESS_EVAL, + NV3D_HW_BIND_GROUP_GEOMETRY, + NV3D_HW_BIND_GROUP_FRAGMENT, + NV3D_HW_BIND_GROUP_LAST = NV3D_HW_BIND_GROUP_FRAGMENT +} __attribute__ ((__packed__)) Nv3dShaderBindGroup; + +typedef struct _nv_program_info { + NvU32 offset; // Start offset relative to program heap + NvU8 registerCount; // From '#.MAX_REG n'+1 + NvU8 type; // Shader type + NvS8 constIndex; // Index into the compiler-generated constant buffer table + + Nv3dShaderStage stage; // Pipeline stage + Nv3dShaderBindGroup bindGroup; // NV3D_HW_BIND_GROUP +} Nv3dProgramInfo; + +typedef struct _nv_shader_const_buf_info { + const NvU32 *data; + NvU32 offset; + NvU32 size; +} Nv3dShaderConstBufInfo; + +#endif // __NVIDIA_3D_SHADERS_H__ diff --git a/src/common/unix/nvidia-3d/interface/nvidia-3d-types.h b/src/common/unix/nvidia-3d/interface/nvidia-3d-types.h new file mode 100644 index 000000000..aa89838a6 --- /dev/null +++ b/src/common/unix/nvidia-3d/interface/nvidia-3d-types.h @@ -0,0 +1,478 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVIDIA_3D_TYPES_H__ +#define __NVIDIA_3D_TYPES_H__ + + +#include "nvtypes.h" +#include "nvlimits.h" +#include "nvidia-push-methods.h" + +#include "nvidia-3d-shaders.h" + +enum Nv3dBlendOperation { + NV3D_BLEND_OP_CLEAR, + NV3D_BLEND_OP_SRC, + NV3D_BLEND_OP_DST, + NV3D_BLEND_OP_OVER, + NV3D_BLEND_OP_OVER_REVERSE, + NV3D_BLEND_OP_IN, + NV3D_BLEND_OP_IN_REVERSE, + NV3D_BLEND_OP_OUT, + NV3D_BLEND_OP_OUT_REVERSE, + NV3D_BLEND_OP_ATOP, + NV3D_BLEND_OP_ATOP_REVERSE, + NV3D_BLEND_OP_XOR, + NV3D_BLEND_OP_ADD, + NV3D_BLEND_OP_SATURATE, +}; + +// We use two vertex streams: one for static attributes (values that are the +// same for all vertices) and one for dynamic attributes. +enum Nv3dVertexAttributeStreamType { + NV3D_VERTEX_ATTRIBUTE_STREAM_FIRST = 0, + NV3D_VERTEX_ATTRIBUTE_STREAM_STATIC = 0, + NV3D_VERTEX_ATTRIBUTE_STREAM_DYNAMIC = 1, + NV3D_VERTEX_ATTRIBUTE_STREAM_COUNT, +} __attribute__ ((__packed__)); + +/* The data type of a vertex attribute. */ +/* Names of enum Nv3dVertexAttributeDataType members follow + * "NV3D_VERTEX_ATTRIBUTE_DATA_TYPE_{N_elements}_{element_size}_{NUMERICAL_TYPE}" convention + * where {NUMERICAL_TYPE} gives information about NV9097_SET_VERTEX_ATTRIBUTE_A_NUMERICAL_TYPE + */ +enum Nv3dVertexAttributeDataType { + NV3D_VERTEX_ATTRIBUTE_DATA_TYPE_2_32_FLOAT, /* two floats */ + NV3D_VERTEX_ATTRIBUTE_DATA_TYPE_4_32_FLOAT, /* four floats */ + NV3D_VERTEX_ATTRIBUTE_DATA_TYPE_4_16_UNORM, /* four unsigned shorts mapped to floats: [0,65535] => [0.0f,1.0f] */ + NV3D_VERTEX_ATTRIBUTE_DATA_TYPE_4_8_UNORM, /* four unsigned bytes mapped to floats: [0,255] => [0.0f,1.0f] */ + NV3D_VERTEX_ATTRIBUTE_DATA_TYPE_2_16_SSCALED,/* two shorts mapped to floats: [-32768,32767] => [-32768.0f,32767.0f] */ +} __attribute__ ((__packed__)); + +/* The possible vertex attributes. */ +enum Nv3dVertexAttributeType { + NV3D_VERTEX_ATTRIBUTE_POSITION = 0, + NV3D_VERTEX_ATTRIBUTE_VERTEX_WEIGHT = 1, + NV3D_VERTEX_ATTRIBUTE_NORMAL = 2, + NV3D_VERTEX_ATTRIBUTE_COLOR = 3, + NV3D_VERTEX_ATTRIBUTE_SECONDARY_COLOR = 4, + NV3D_VERTEX_ATTRIBUTE_FOG_COORD = 5, + NV3D_VERTEX_ATTRIBUTE_POINT_SIZE = 6, + NV3D_VERTEX_ATTRIBUTE_MATRIX_INDEX = 7, + NV3D_VERTEX_ATTRIBUTE_TEXCOORD0 = 8, + NV3D_VERTEX_ATTRIBUTE_TEXCOORD1 = 9, + NV3D_VERTEX_ATTRIBUTE_TEXCOORD2 = 10, + NV3D_VERTEX_ATTRIBUTE_TEXCOORD3 = 11, + /* + * The _END enum value is used as a sentinel to terminate arrays of + * Nv3dVertexAttributeInfoRec (see Nv3dVertexAttributeInfoRec, below). + */ + NV3D_VERTEX_ATTRIBUTE_END = 255, +} __attribute__ ((__packed__)); + +/* + * Nv3dVertexAttributeInfoRec stores the triplet attribute, stream type, and + * data type. Arrays of Nv3dVertexAttributeInfoRec are used to describe vertex + * attribute configurations to FermiSetupVertexArrays(). + * + * The NV3D_ATTRIB_ENTRY() and NV3D_ATTRIB_END macros can be used to make + * Nv3dVertexAttributeInfoRec assignment more succinct. E.g., + * + * Nv3dVertexAttributeInfoRec attribs[] = { + * NV3D_ATTRIB_ENTRY(COLOR, STATIC, 4UB), + * NV3D_ATTRIB_END, + * }; + */ +typedef struct _Nv3dVertexAttributeInfoRec { + enum Nv3dVertexAttributeType attributeType; + enum Nv3dVertexAttributeStreamType streamType; + enum Nv3dVertexAttributeDataType dataType; +} Nv3dVertexAttributeInfoRec; + +#define NV3D_ATTRIB_TYPE_ENTRY(_i, _streamType, _dataType) \ + (Nv3dVertexAttributeInfoRec) \ + { .attributeType = _i, \ + .streamType = NV3D_VERTEX_ATTRIBUTE_STREAM_##_streamType, \ + .dataType = NV3D_VERTEX_ATTRIBUTE_DATA_TYPE_##_dataType } + +#define NV3D_ATTRIB_ENTRY(_attribType, _streamType, _dataType) \ + NV3D_ATTRIB_TYPE_ENTRY(NV3D_VERTEX_ATTRIBUTE_##_attribType, _streamType, _dataType) + +#define NV3D_ATTRIB_END \ + (Nv3dVertexAttributeInfoRec) \ + { .attributeType = NV3D_VERTEX_ATTRIBUTE_END } + +/* + * When built into kernel code, define Nv3dFloat to be an NvU32: it is the same + * size as a float, but the caller is responsible for storing float bit patterns + * to Nv3dFloat. + */ +ct_assert(sizeof(float) == sizeof(NvU32)); +#if NV_PUSH_ALLOW_FLOAT +typedef float Nv3dFloat; +#else +typedef NvU32 Nv3dFloat; +#endif + +static inline void nv3dPushFloat(NvPushChannelPtr p, const Nv3dFloat data) +{ +#if NV_PUSH_ALLOW_FLOAT + nvPushSetMethodDataF(p, data); +#else + nvPushSetMethodData(p, data); +#endif +} + +/* + * Vertex attribute data types. Each of these types represents a different way + * of specifying vertex attribute data. + */ +typedef struct __attribute__((packed)) { + Nv3dFloat x, y; +} Nv3dVertexAttrib2F; + +typedef struct __attribute__((packed)) { + NvU32 x, y; +} Nv3dVertexAttrib2U; + +typedef struct __attribute__((packed)) { + NvS32 x, y; +} Nv3dVertexAttrib2S; + +typedef struct __attribute__((packed)) { + Nv3dFloat x, y, z; +} Nv3dVertexAttrib3F; + +typedef struct __attribute__((packed)) { + NvU32 x, y, z; +} Nv3dVertexAttrib3U; + +typedef struct __attribute__((packed)) { + Nv3dFloat x, y, z, w; +} Nv3dVertexAttrib4F; + +typedef struct __attribute__((packed)) { + NvU16 x, y, z, w; +} Nv3dVertexAttrib4US; + +typedef struct __attribute__((packed)) { + NvU8 x, y, z, w; +} Nv3dVertexAttrib4UB; + +typedef struct { + NvU32 xyzw; +} Nv3dVertexAttrib4UBPacked; + +typedef struct __attribute__((packed)) { + NvU32 xy; +} Nv3dVertexAttrib2SPacked; + +// List of component sizes used for the internal representation of a +// texture header +enum Nv3dTexHeaderComponentSizes { + NV3D_TEXHEAD_A8B8G8R8, + NV3D_TEXHEAD_A2B10G10R10, + NV3D_TEXHEAD_B5G6R5, + NV3D_TEXHEAD_A1B5G5R5, + NV3D_TEXHEAD_R8, + NV3D_TEXHEAD_R32, + NV3D_TEXHEAD_R16, + NV3D_TEXHEAD_G8R8, + NV3D_TEXHEAD_R16G16B16A16, + NV3D_TEXHEAD_R32G32B32A32, + NV3D_TEXHEAD_Y8_VIDEO +}; + +// List of component sources used for the internal representation of a +// texture header +enum Nv3dTexHeaderSource { + NV3D_TEXHEAD_IN_A, + NV3D_TEXHEAD_IN_R, + NV3D_TEXHEAD_IN_G, + NV3D_TEXHEAD_IN_B, + NV3D_TEXHEAD_IN_ZERO, + NV3D_TEXHEAD_IN_ONE_FLOAT +}; + +// List of component data types used for the internal representation of +// a texture header +enum Nv3dTexHeaderDataType { + NV3D_TEXHEAD_NUM_UNORM, + NV3D_TEXHEAD_NUM_UINT, + NV3D_TEXHEAD_NUM_FLOAT, + NV3D_TEXHEAD_NUM_SNORM, + NV3D_TEXHEAD_NUM_SINT +}; + +enum Nv3dTexHeaderRepeatType { + NV3D_TEXHEAD_REPEAT_TYPE_NONE, + NV3D_TEXHEAD_REPEAT_TYPE_NORMAL, + NV3D_TEXHEAD_REPEAT_TYPE_PAD, + NV3D_TEXHEAD_REPEAT_TYPE_REFLECT +}; + +enum Nv3dTextureFilterType{ + NV3D_TEXHEAD_FILTER_TYPE_NEAREST, + NV3D_TEXHEAD_FILTER_TYPE_LINEAR, + NV3D_TEXHEAD_FILTER_TYPE_ANISO_2X, + NV3D_TEXHEAD_FILTER_TYPE_ANISO_4X, + NV3D_TEXHEAD_FILTER_TYPE_ANISO_8X, + NV3D_TEXHEAD_FILTER_TYPE_ANISO_16X +}; + +enum Nv3dTexType { + NV3D_TEX_TYPE_ONE_D, + NV3D_TEX_TYPE_ONE_D_BUFFER, + NV3D_TEX_TYPE_TWO_D_PITCH, + NV3D_TEX_TYPE_TWO_D_BLOCKLINEAR, +}; + +typedef struct { + NvU32 x; + NvU32 y; + NvU32 z; +} Nv3dBlockLinearLog2GobsPerBlock; + +// Intermediate representation of a texture header +typedef struct { + NvBool error; + + enum Nv3dTexHeaderComponentSizes sizes; + + // Currently, we always use the same data type for all components. + enum Nv3dTexHeaderDataType dataType; + + struct { + enum Nv3dTexHeaderSource x; + enum Nv3dTexHeaderSource y; + enum Nv3dTexHeaderSource z; + enum Nv3dTexHeaderSource w; + } source; + + enum Nv3dTexType texType; + + NvU64 offset; + NvBool normalizedCoords; + enum Nv3dTexHeaderRepeatType repeatType; + enum Nv3dTextureFilterType filtering; + int pitch; + int width; + int height; + + Nv3dBlockLinearLog2GobsPerBlock log2GobsPerBlock; +} Nv3dRenderTexInfo; + +typedef NvU32 Nv3dTexSampler[8]; +typedef NvU32 Nv3dTexHeader[8]; + +// HW representation of a texture header +typedef struct { + Nv3dTexSampler samp; + Nv3dTexHeader head; +} Nv3dTexture; + +#define NV3D_CONSTANT_BUFFER_SIZE (4096 * 4) + +#define NV3D_TEXTURE_INDEX_INVALID (-1) + +#define NV3D_VERTEX_ATTRIBUTE_STREAM_SIZE (64 * 1024) + +/* + * The constant buffer alignment constraints, specifically for the methods: + * + * NV*97_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE + * NV*97_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER + * + * have evolved over GPU architectures: + * + * kepler maxwell pascal volta turing + * SIZE 256 16 16 16 16 + * ADDRESS 256 256 256 256 64 + * + * But, using an alignment of 256 all the time is simpler. + */ +#define NV3D_MIN_CONSTBUF_ALIGNMENT 256 + +/* + * 3D engine pitch alignment requirements for texture surface. + */ +#define NV3D_TEXTURE_PITCH_ALIGNMENT 256 + +typedef struct _Nv3dStreamSurfaceRec { + NvU64 gpuAddress; + NvU64 size; +} Nv3dStreamSurfaceRec; + +typedef struct _Nv3dVertexAttributeStreamRec { + // Current GPU address within the stream. + NvU64 current; + // Terminating GPU address within the stream. + NvU64 end; + // Number of bytes per vertex. + NvU32 stride; + // Index of the next vertex to be launched. + int nextLaunch; +} Nv3dVertexAttributeStreamRec; + +typedef struct _Nv3dHal Nv3dHal; + +typedef struct _Nv3dDeviceCapsRec { + NvU32 hasSetBindlessTexture :1; /* Supports SetBindlessTexture method */ + NvU32 hasProgramRegion :1; + + NvU32 maxDim; /* + * Maximum width or height of the + * texture surface in pixels. + */ +} Nv3dDeviceCapsRec, *Nv3dDeviceCapsPtr; + +typedef struct _Nv3dDeviceSpaVersionRec { + NvU16 major; + NvU16 minor; +} Nv3dDeviceSpaVersionRec; + +/* + * Enum for each compiled shader version. + */ +enum Nv3dShaderArch { + NV3D_SHADER_ARCH_MAXWELL, + NV3D_SHADER_ARCH_PASCAL, + NV3D_SHADER_ARCH_VOLTA, + NV3D_SHADER_ARCH_TURING, + NV3D_SHADER_ARCH_AMPERE, + NV3D_SHADER_ARCH_HOPPER, + NV3D_SHADER_ARCH_COUNT, +}; + +typedef struct _Nv3dDeviceRec { + + NvPushDevicePtr pPushDevice; + Nv3dDeviceCapsRec caps; + NvU32 classNumber; + enum Nv3dShaderArch shaderArch; + + Nv3dDeviceSpaVersionRec spaVersion; + + NvU32 maxThreadsPerWarp; + NvU32 maxWarps; + + const Nv3dHal *hal; + +} Nv3dDeviceRec, *Nv3dDevicePtr; + +typedef struct _Nv3dChannelProgramsRec { + /* + * An array of program descriptors, and the number of elements + * in the array. + */ + size_t num; + const Nv3dProgramInfo *info; + + size_t maxLocalBytes; + size_t maxStackBytes; + + /* + * The shader program code segment. + * + * The size is in bytes. + */ + struct { + size_t decompressedSize; + const unsigned char *compressedStart; + const unsigned char *compressedEnd; + } code; + + /* + * The constant buffers generated by the compiler for use with the above + * code segment. + * + * 'size' is the total size of the surface to allocate, in bytes. + * 'sizeAlign' is the minimum alignment required by the hardware for each + * particular constant buffer. (Although we may only have + * N bytes of data to upload for each constant buffer, that + * size should be padded out with zeroes to a multiple of this + * value.) + * 'count' is the number of entries in the 'info' array. + * 'info' is a pointer to an array of Nv3dShaderConstBufInfo entries. + */ + struct { + size_t size; + NvU32 sizeAlign; + NvU32 count; + const Nv3dShaderConstBufInfo *info; + } constants; +} Nv3dChannelProgramsRec; + +typedef struct _Nv3dChannelRec { + + Nv3dDevicePtr p3dDevice; + NvPushChannelPtr pPushChannel; + + NvU32 handle[NV_MAX_SUBDEVICES]; + NvU16 numTextures; + NvU16 numTextureBindings; + + Nv3dVertexAttributeStreamRec + vertexStreams[NV3D_VERTEX_ATTRIBUTE_STREAM_COUNT]; + + /* + * Begin / end state. ~0 if outside begin/end, or NV9097_BEGIN_OP_* if + * inside. + */ + NvU32 currentPrimitiveMode; + + Nv3dChannelProgramsRec programs; + int currentProgramIndex[NV3D_HW_SHADER_STAGE_COUNT]; + NvU64 programLocalMemorySize; + + NvBool hasFrameBoundaries; + + struct { + NvU32 handle[NV_MAX_SUBDEVICES]; + NvU64 gpuAddress; + NvU64 programOffset; + NvU64 programConstantsOffset; + NvU64 programLocalMemoryOffset; + NvU64 textureOffset; + NvU64 bindlessTextureConstantBufferOffset; + NvU64 constantBufferOffset; + NvU64 vertexStreamOffset[NV3D_VERTEX_ATTRIBUTE_STREAM_COUNT]; + NvU64 totalSize; + } surface; + +} Nv3dChannelRec, *Nv3dChannelPtr; + +typedef struct { + Nv3dFloat red; + Nv3dFloat green; + Nv3dFloat blue; + Nv3dFloat alpha; +} Nv3dColor; + +typedef struct { + NvU32 blendFactorSrc; /* NV9097_SET_BLEND_COLOR/ALPHA_SOURCE_COEFF_ */ + NvU32 blendFactorDst; /* NV9097_SET_BLEND_COLOR/ALPHA_DEST_COEFF_ */ + NvU32 blendEquation; /* NV9097_SET_BLEND_COLOR/ALPHA_OP_ */ +} Nv3dBlendState; +#endif /* __NVIDIA_3D_TYPES_H__ */ diff --git a/src/common/unix/nvidia-3d/interface/nvidia-3d-utils.h b/src/common/unix/nvidia-3d/interface/nvidia-3d-utils.h new file mode 100644 index 000000000..6b9599404 --- /dev/null +++ b/src/common/unix/nvidia-3d/interface/nvidia-3d-utils.h @@ -0,0 +1,104 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVIDIA_3D_UTILS_H__ +#define __NVIDIA_3D_UTILS_H__ + +#include "nvidia-3d.h" + +#include +#include + +static inline void nv3dSetSurfaceClip( + Nv3dChannelRec *p3dChannel, + NvS16 x, + NvS16 y, + NvU16 w, + NvU16 h) +{ + NvPushChannelPtr p = p3dChannel->pPushChannel; + + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, + NV9097_SET_SURFACE_CLIP_HORIZONTAL, 2); + nvPushSetMethodData(p, + NV3D_V(9097, SET_SURFACE_CLIP_HORIZONTAL, X, x) | + NV3D_V(9097, SET_SURFACE_CLIP_HORIZONTAL, WIDTH, w)); + nvPushSetMethodData(p, + NV3D_V(9097, SET_SURFACE_CLIP_VERTICAL, Y, y) | + NV3D_V(9097, SET_SURFACE_CLIP_VERTICAL, HEIGHT, h)); +} + +static inline void nv3dClearSurface( + Nv3dChannelRec *p3dChannel, + const NvU32 clearColor[4], + NvU16 x, + NvU16 y, + NvU16 w, + NvU16 h) +{ + NvPushChannelPtr p = p3dChannel->pPushChannel; + + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, NV9097_SET_COLOR_CLEAR_VALUE(0), 4); + nvPushSetMethodData(p, clearColor[0]); + nvPushSetMethodData(p, clearColor[1]); + nvPushSetMethodData(p, clearColor[2]); + nvPushSetMethodData(p, clearColor[3]); + + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, NV9097_SET_CLEAR_RECT_HORIZONTAL, 2); + nvPushSetMethodData(p, + NV3D_V(9097, SET_CLEAR_RECT_HORIZONTAL, XMIN, x) | + NV3D_V(9097, SET_CLEAR_RECT_HORIZONTAL, XMAX, x + w)); + nvPushSetMethodData(p, + NV3D_V(9097, SET_CLEAR_RECT_VERTICAL, YMIN, y) | + NV3D_V(9097, SET_CLEAR_RECT_VERTICAL, YMAX, y + h)); + nvPushImmedVal(p, NVA06F_SUBCHANNEL_3D, NV9097_CLEAR_SURFACE, + NV3D_C(9097, CLEAR_SURFACE, R_ENABLE, TRUE) | + NV3D_C(9097, CLEAR_SURFACE, G_ENABLE, TRUE) | + NV3D_C(9097, CLEAR_SURFACE, B_ENABLE, TRUE) | + NV3D_C(9097, CLEAR_SURFACE, A_ENABLE, TRUE)); +} + +static inline void nv3dVasBegin( + Nv3dChannelRec *p3dChannel, + NvU32 mode) +{ + NvPushChannelPtr p = p3dChannel->pPushChannel; + + nvAssert(p3dChannel->currentPrimitiveMode == ~0); + + p3dChannel->currentPrimitiveMode = mode; + nvPushImmedVal(p, NVA06F_SUBCHANNEL_3D, NV9097_BEGIN, mode); +} + +static inline void nv3dVasEnd( + Nv3dChannelRec *p3dChannel) +{ + NvPushChannelPtr p = p3dChannel->pPushChannel; + + nvAssert(p3dChannel->currentPrimitiveMode != ~0); + + p3dChannel->currentPrimitiveMode = ~0; + nvPushImmedVal(p, NVA06F_SUBCHANNEL_3D, NV9097_END, 0); +} + +#endif /* __NVIDIA_3D_UTILS_H__ */ diff --git a/src/common/unix/nvidia-3d/interface/nvidia-3d.h b/src/common/unix/nvidia-3d/interface/nvidia-3d.h new file mode 100644 index 000000000..cdac1653d --- /dev/null +++ b/src/common/unix/nvidia-3d/interface/nvidia-3d.h @@ -0,0 +1,296 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * The nvidia-3d library provides utility code for programming a 3D + * object. + */ + +#ifndef __NVIDIA_3D_H__ +#define __NVIDIA_3D_H__ + +#include "nvtypes.h" +#include "nvmisc.h" /* DRF_DEF, et al */ +#include "nvlimits.h" /* NV_MAX_SUBDEVICES */ + +#include "nvidia-push-types.h" +#include "nvidia-3d-types.h" + +#define NV3D_C(d, r, f, c) DRF_DEF( d, _ ## r, _ ## f, _ ## c) +#define NV3D_V(d, r, f, v) DRF_NUM( d, _ ## r, _ ## f, (NvU32)(v) ) + +/* + * Allocate and free an Nv3dDeviceRec + */ +typedef struct _Nv3dAllocDeviceParams { + NvPushDevicePtr pPushDevice; +} Nv3dAllocDeviceParams; + +NvBool nv3dAllocDevice( + const Nv3dAllocDeviceParams *pParams, + Nv3dDevicePtr p3dDevice); + +void nv3dFreeDevice( + Nv3dDevicePtr p3dDevice); + +/* + * Allocate and free an Nv3dChannelRec data structure. + * + * Note that all pointers provided in this parameter structure are + * cached in the Nv3dChannelRec. They must remain valid from + * nv3dAllocChannelState() until the corresponding + * nv3dFreeChannelState() call. + */ +typedef struct _Nv3dAllocChannelStateParams { + /* + * The Nv3dDeviceRec to use with this channel. + */ + Nv3dDevicePtr p3dDevice; + + /* + * The number of texture headers/samplers nvidia-3d should + * allocate. + */ + NvU16 numTextures; + + /* + * The number of general purpose constant buffers nvidia-3d should + * allocate. + */ + NvU16 numConstantBuffers; + + /* + * The number of texture bindings. + */ + NvU16 numTextureBindings; + + /* + * Whether the host driver renders in terms of frames, or, like the X + * driver, renders directly to the front buffer. On >= Pascal, the pipe + * needs to be explicitly flushed at the end of a frame. + */ + NvBool hasFrameBoundaries; + +} Nv3dAllocChannelStateParams; + +NvBool nv3dAllocChannelState( + const Nv3dAllocChannelStateParams *pParams, + Nv3dChannelPtr p3dChannel); + +void nv3dFreeChannelState( + Nv3dChannelPtr p3dChannel); + + +/* + * Allocate and free the RM object for an Nv3dChannelRec. + */ +typedef struct _Nv3dAllocChannelObjectParams { + NvPushChannelPtr pPushChannel; + NvU32 handle[NV_MAX_SUBDEVICES]; +} Nv3dAllocChannelObjectParams; + +NvBool nv3dAllocChannelObject( + const Nv3dAllocChannelObjectParams *pParams, + Nv3dChannelPtr p3dChannel); + +void nv3dFreeChannelObject( + Nv3dChannelPtr p3dChannel); + + +/* + * Allocate and free the surface needed by the Nv3dChannelRec. + */ +NvBool nv3dAllocChannelSurface(Nv3dChannelPtr p3dChannel); + +void nv3dFreeChannelSurface(Nv3dChannelPtr p3dChannel); + + +/* + * Once the Nv3dChannelRec is allocated, and the objects and surface + * for it are allocated, nv3dInitChannel() is used to initialize the + * graphics engine and make it ready to use. + */ +NvBool nv3dInitChannel(Nv3dChannelPtr p3dChannel); + + +/* + * Return the offset or GPU address of the specified item within the + * Nv3dChannelRec's surface. + */ + +static inline NvU64 nv3dGetTextureOffset( + const Nv3dChannelRec *p3dChannel, + NvU32 textureIndex) +{ + const NvU64 offset = p3dChannel->surface.textureOffset; + + return offset + (sizeof(Nv3dTexture) * textureIndex); +} + +static inline NvU64 nv3dGetTextureGpuAddress( + const Nv3dChannelRec *p3dChannel, + NvU32 textureIndex) +{ + return p3dChannel->surface.gpuAddress + + nv3dGetTextureOffset(p3dChannel, textureIndex); +} + +static inline NvU64 nv3dGetConstantBufferOffset( + const Nv3dChannelRec *p3dChannel, + NvU32 constantBufferIndex) +{ + const NvU64 offset = p3dChannel->surface.constantBufferOffset; + + return offset + (NV3D_CONSTANT_BUFFER_SIZE * constantBufferIndex); +} + +static inline NvU64 nv3dGetConstantBufferGpuAddress( + const Nv3dChannelRec *p3dChannel, + NvU32 constantBufferIndex) +{ + return p3dChannel->surface.gpuAddress + + nv3dGetConstantBufferOffset(p3dChannel, constantBufferIndex); +} + +static inline NvU64 nv3dGetProgramOffset( + const Nv3dChannelRec *p3dChannel) +{ + return p3dChannel->surface.programOffset; +} + +static inline NvU64 nv3dGetProgramGpuAddress( + const Nv3dChannelRec *p3dChannel) +{ + return p3dChannel->surface.gpuAddress + nv3dGetProgramOffset(p3dChannel); +} + +static inline NvU64 nv3dGetProgramConstantsOffset( + const Nv3dChannelRec *p3dChannel) +{ + return p3dChannel->surface.programConstantsOffset; +} + +static inline NvU64 nv3dGetProgramConstantsGpuAddress( + const Nv3dChannelRec *p3dChannel) +{ + return p3dChannel->surface.gpuAddress + + nv3dGetProgramConstantsOffset(p3dChannel); +} + +static inline NvU64 nv3dGetProgramLocalMemoryOffset( + const Nv3dChannelRec *p3dChannel) +{ + return p3dChannel->surface.programLocalMemoryOffset; +} + +static inline NvU64 nv3dGetProgramLocalMemoryGpuAddress( + const Nv3dChannelRec *p3dChannel) +{ + return p3dChannel->surface.gpuAddress + + nv3dGetProgramLocalMemoryOffset(p3dChannel); +} + +static inline NvU64 nv3dGetBindlessTextureConstantBufferOffset( + const Nv3dChannelRec *p3dChannel) +{ + return p3dChannel->surface.bindlessTextureConstantBufferOffset; +} + +static inline NvU64 nv3dGetBindlessTextureConstantBufferGpuAddress( + const Nv3dChannelRec *p3dChannel) +{ + return p3dChannel->surface.gpuAddress + + nv3dGetBindlessTextureConstantBufferOffset(p3dChannel); +} + +static inline NvU64 nv3dGetVertexAttributestreamOffset( + const Nv3dChannelRec *p3dChannel, + enum Nv3dVertexAttributeStreamType stream) +{ + return p3dChannel->surface.vertexStreamOffset[stream]; +} + +static inline NvU64 nv3dGetVertexAttributestreamGpuAddress( + const Nv3dChannelRec *p3dChannel, + enum Nv3dVertexAttributeStreamType stream) +{ + return p3dChannel->surface.gpuAddress + + nv3dGetVertexAttributestreamOffset(p3dChannel, stream); +} + +void nv3dUploadDataInline( + Nv3dChannelRec *p3dChannel, + NvU64 gpuBaseAddress, + size_t offset, + const void *data, + size_t bytes); + +void nv3dClearProgramCache( + Nv3dChannelRec *p3dChannel); + +void nv3dLoadProgram( + Nv3dChannelRec *p3dChannel, + int programIndex); + +void nv3dLoadTextures( + Nv3dChannelRec *p3dChannel, + int firstTextureIndex, + const Nv3dRenderTexInfo *texInfo, + int numTexures); + +void nv3dBindTextures( + Nv3dChannelPtr p3dChannel, + int programIndex, + const int *textureBindingIndices); + +void nv3dSetBlendColorCoefficients( + Nv3dChannelPtr p3dChannel, + enum Nv3dBlendOperation op, + NvBool forceNoDstAlphaBits, + NvBool dualSourceBlending); + +void nv3dSetBlend( + Nv3dChannelPtr p3dChannel, + const Nv3dBlendState *blendStateColor, + const Nv3dBlendState *blendStateAlpha, + const Nv3dColor *blendColor); + +int nv3dVasSetup( + Nv3dChannelRec *p3dChannel, + const Nv3dVertexAttributeInfoRec *attribs, + const Nv3dStreamSurfaceRec *pSurf); + +void nv3dVasSelectCbForVertexData( + Nv3dChannelRec *p3dChannel); + +void nv3dVasDrawInlineVerts( + Nv3dChannelRec *p3dChannel, + const void *data, + int numVerts); + +NvBool nv3dVasMakeRoom( + Nv3dChannelRec *p3dChannel, + NvU32 pendingVerts, + NvU32 moreVerts); + +#endif /* __NVIDIA_3D_H__ */ diff --git a/src/common/unix/nvidia-3d/src/nvidia-3d-core.c b/src/common/unix/nvidia-3d/src/nvidia-3d-core.c new file mode 100644 index 000000000..f99428128 --- /dev/null +++ b/src/common/unix/nvidia-3d/src/nvidia-3d-core.c @@ -0,0 +1,162 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvidia-3d.h" +#include "nvidia-3d-types-priv.h" +#include "nvos.h" +#include "nvidia-3d-fermi.h" +#include "nvidia-3d-kepler.h" +#include "nvidia-push-utils.h" + +NvBool nv3dAllocChannelObject( + const Nv3dAllocChannelObjectParams *pParams, + Nv3dChannelPtr p3dChannel) +{ + NvPushChannelPtr pPushChannel = pParams->pPushChannel; + NvPushDevicePtr pPushDevice = pPushChannel->pDevice; + const NvU32 classNumber = p3dChannel->p3dDevice->classNumber; + int sd; + + /* + * nv3dAllocChannel() should have been called to assign p3dDevice. + */ + nvAssert(p3dChannel->p3dDevice != NULL); + nvAssert(p3dChannel->p3dDevice->pPushDevice == + pParams->pPushChannel->pDevice); + + for (sd = 0; + sd < ARRAY_LEN(pPushChannel->channelHandle) && + pPushChannel->channelHandle[sd] != 0; + sd++) { + + if (nvPushIsAModel(pPushDevice)) { + nvAssert(sd == 0); + } else { + const NvPushImports *pImports = pPushDevice->pImports; + nvAssert(pParams->handle[sd] != 0); + NvU32 ret = pImports->rmApiAlloc(pPushDevice, + pPushChannel->channelHandle[sd], + pParams->handle[sd], + classNumber, + NULL); + if (ret != NVOS_STATUS_SUCCESS) { + return FALSE; + } + } + + p3dChannel->handle[sd] = pParams->handle[sd]; + } + + p3dChannel->pPushChannel = pPushChannel; + + return TRUE; +} + +void nv3dFreeChannelObject(Nv3dChannelPtr p3dChannel) +{ + int sd; + + p3dChannel->pPushChannel = NULL; + + // No need to actually free the object here. It gets destroyed during + // channel teardown. + for (sd = 0; sd < ARRAY_LEN(p3dChannel->handle); sd++) { + p3dChannel->handle[sd] = 0; + } +} + +void nv3dUploadDataInline( + Nv3dChannelRec *p3dChannel, + NvU64 gpuBaseAddress, + size_t offset, + const void *data, + size_t bytes) +{ + const Nv3dHal *pHal = p3dChannel->p3dDevice->hal; + + pHal->uploadDataInline(p3dChannel, gpuBaseAddress, offset, data, bytes); +} + +void nv3dClearProgramCache(Nv3dChannelRec *p3dChannel) +{ + Nv3dShaderStage stage; + + for (stage = 0; + stage < ARRAY_LEN(p3dChannel->currentProgramIndex); + stage++) { + p3dChannel->currentProgramIndex[stage] = -1; + } +} + +void nv3dLoadTextures( + Nv3dChannelRec *p3dChannel, + int firstTex, + const Nv3dRenderTexInfo *texInfo, + int numTex) +{ + /* Limit number of texture/samplers on the stack to 4 (256 bytes) */ +#define MAX_TEX_CHUNK 4 + Nv3dTexture textures[MAX_TEX_CHUNK]; + const Nv3dHal *pHal = p3dChannel->p3dDevice->hal; + const NvU64 gpuBaseAddress = nv3dGetTextureGpuAddress(p3dChannel, 0); + + nvAssert(numTex >= 1); + + // Invalidate the texture/sampler caches. This will cause a wait for idle + // if there's rendering still in progress. This is necessary in case the + // texture parameters we're about to overwrite are in use. + _nv3dInvalidateTexturesFermi(p3dChannel); + + while (numTex) { + const NvU32 chunkNumTex = NV_MIN(numTex, MAX_TEX_CHUNK); + const size_t startOffset = sizeof(Nv3dTexture) * firstTex; + const size_t bytes = sizeof(Nv3dTexture) * chunkNumTex; + int i; + + NVMISC_MEMSET(textures, 0, sizeof(textures)); + + nvAssert(firstTex + numTex <= p3dChannel->numTextures); + + // Write texture header to HW format + for (i = 0; i < chunkNumTex; i++) { + pHal->assignNv3dTexture(texInfo[i], &textures[i]); + } + + nv3dUploadDataInline(p3dChannel, gpuBaseAddress, startOffset, + textures, bytes); + + numTex -= chunkNumTex; + firstTex += chunkNumTex; + texInfo += chunkNumTex; + } +} + +void nv3dBindTextures( + Nv3dChannelPtr p3dChannel, + int programIndex, + const int *textureBindingIndices) +{ + nvAssert(programIndex < p3dChannel->programs.num); + + _nv3dBindTexturesKepler(p3dChannel, programIndex, textureBindingIndices); +} diff --git a/src/common/unix/nvidia-3d/src/nvidia-3d-fermi.c b/src/common/unix/nvidia-3d/src/nvidia-3d-fermi.c new file mode 100644 index 000000000..6d42f6913 --- /dev/null +++ b/src/common/unix/nvidia-3d/src/nvidia-3d-fermi.c @@ -0,0 +1,557 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvidia-3d-types-priv.h" +#include "nvidia-3d-fermi.h" +#include "nvidia-3d.h" +#include "nvidia-3d-imports.h" +#include "nvidia-3d-constant-buffers.h" +#include "nvidia-3d-shader-constants.h" +#include "nvidia-3d-vertex-arrays.h" +#include "nvidia-push-utils.h" /* nvPushSetObject */ + +#include +#include + +#include + +#if NV_PUSH_ALLOW_FLOAT + #define NV3D_FLOAT_ONE (1.00f) +#else + #define NV3D_FLOAT_ONE 0x3F800000 /* 1.00f */ +#endif + +static void *DecompressUsingXz( + const Nv3dChannelRec *p3dChannel, + const void *compressedData, + size_t compressedSize, + size_t decompressedSize) +{ + NvPushDevicePtr pPushDevice = p3dChannel->p3dDevice->pPushDevice; + const NvPushImports *pImports = pPushDevice->pImports; + void *decompressedData = nv3dImportAlloc(decompressedSize); + struct xz_dec *xzState; + enum xz_ret ret; + + struct xz_buf xzBuf = { + .in = compressedData, + .in_pos = 0, + .in_size = compressedSize, + .out = decompressedData, + .out_pos = 0, + .out_size = decompressedSize, + }; + + if (decompressedData == NULL) { + return NULL; + } + + xz_crc32_init(); + + xzState = xz_dec_init(XZ_SINGLE, 0); + + if (xzState == NULL) { + pImports->logError(pPushDevice, + "Failed to initialize xz decompression."); + goto fail; + } + + ret = xz_dec_run(xzState, &xzBuf); + + xz_dec_end(xzState); + + if (ret != XZ_STREAM_END) { + pImports->logError(pPushDevice, "Failed to decompress xz data."); + goto fail; + } + + return decompressedData; + +fail: + nv3dImportFree(decompressedData); + return NULL; +} + +static void *DecompressPrograms(const Nv3dChannelRec *p3dChannel) +{ + const Nv3dChannelProgramsRec *pPrograms = &p3dChannel->programs; + const size_t compressedSize = + pPrograms->code.compressedEnd - pPrograms->code.compressedStart; + + nvAssert(pPrograms->code.compressedEnd > pPrograms->code.compressedStart); + + return DecompressUsingXz(p3dChannel, + pPrograms->code.compressedStart, + compressedSize, + pPrograms->code.decompressedSize); +} + +/* + * This function attempts to upload the precompiled shaders to the GPU through + * a temporary CPU mapping. + * Failure of this function is not fatal -- we can fall back to uploading + * through the pushbuffer. + */ +static NvBool UploadPrograms(Nv3dChannelPtr p3dChannel, const void *programCode) +{ + NvPushDevicePtr pPushDevice = p3dChannel->p3dDevice->pPushDevice; + const NvPushImports *pImports = pPushDevice->pImports; + const size_t size = p3dChannel->programs.code.decompressedSize; + NvU32 sd; + + for (sd = 0; sd < pPushDevice->numSubDevices; sd++) { + NvU32 status; + void *ptr; + const NvU32 hMemory = pPushDevice->clientSli ? + p3dChannel->surface.handle[sd] : + p3dChannel->surface.handle[0]; + + status = pImports->rmApiMapMemory(pPushDevice, + pPushDevice->subDevice[sd].handle, + hMemory, + p3dChannel->surface.programOffset, + size, + &ptr, + 0); + if (status != NVOS_STATUS_SUCCESS) { + return FALSE; + } + + nvAssert((size % 4) == 0); + nvDmaMoveDWORDS(ptr, programCode, size / 4); + + status = pImports->rmApiUnmapMemory(pPushDevice, + pPushDevice->subDevice[sd].handle, + hMemory, + ptr, + 0); + nvAssert(status == NVOS_STATUS_SUCCESS); + } + + return TRUE; +} + +NvBool nv3dInitChannel(Nv3dChannelPtr p3dChannel) +{ + NvPushChannelPtr p = p3dChannel->pPushChannel; + const Nv3dDeviceCapsRec *pCaps = &p3dChannel->p3dDevice->caps; + const Nv3dHal *pHal = p3dChannel->p3dDevice->hal; + const NvU64 tex0GpuAddress = nv3dGetTextureGpuAddress(p3dChannel, 0); + NvU64 gpuAddress; + NvU32 i; + void *programCode = DecompressPrograms(p3dChannel); + + if (programCode == NULL) { + return FALSE; + } + + /* + * nv3dAllocChannel() should have been called to assign p3dDevice. + */ + nvAssert(p3dChannel->p3dDevice != NULL); + + /* + * nv3dAllocChannelObject() should have been called to assign + * pPushChannel. + */ + nvAssert(p3dChannel->pPushChannel != NULL); + + /* + * nv3dAllocChannelSurface() should have been called to allocate + * the surface. + */ + nvAssert(p3dChannel->surface.handle[0] != 0); + + nv3dClearProgramCache(p3dChannel); + + p3dChannel->currentPrimitiveMode = ~0; + + nvPushSetObject(p, NVA06F_SUBCHANNEL_3D, p3dChannel->handle); + + // Ct[0]'s format defaults to A8R8G8B8, rather than DISABLED. + nvPushImmedVal(p, NVA06F_SUBCHANNEL_3D, + NV9097_SET_COLOR_TARGET_FORMAT(0), + NV3D_C(9097, SET_COLOR_TARGET_FORMAT, V, DISABLED)); + + nvPushImmedVal(p, NVA06F_SUBCHANNEL_3D, + NV9097_SET_ZT_SELECT, + NV3D_V(9097, SET_ZT_SELECT, TARGET_COUNT, 0)); + + // Set a substitute stream address. This is used when the Vertex Attribute + // Fetch unit tries to fetch outside the bounds of an enabled stream, which + // should never happen. However, AModel always fetches this value + // regardless of whether it actually needs it, so it causes MMU errors if + // it's not set. + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, + NV9097_SET_VERTEX_STREAM_SUBSTITUTE_A, 2); + nvPushSetMethodDataU64(p, p3dChannel->surface.gpuAddress); + + if (p3dChannel->programLocalMemorySize) { + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, + NV9097_SET_SHADER_LOCAL_MEMORY_A, 4); + // ADDRESS_{UPPER,LOWER} + nvPushSetMethodDataU64(p, + nv3dGetProgramLocalMemoryGpuAddress(p3dChannel)); + // SIZE_{UPPER,LOWER} + nvPushSetMethodDataU64(p, p3dChannel->programLocalMemorySize); + } + + // Point rasterization. + nvPushImmed(p, NVA06F_SUBCHANNEL_3D, + NV9097_SET_POINT_CENTER_MODE, OGL); + + // SPA Control. + nvPushImmed(p, NVA06F_SUBCHANNEL_3D, + NV9097_SET_SAMPLER_BINDING, VIA_HEADER_BINDING); + + // Viewport parameters. + nvPushImmedVal(p, NVA06F_SUBCHANNEL_3D, NV9097_SET_VIEWPORT_SCALE_OFFSET, + NV3D_C(9097, SET_VIEWPORT_SCALE_OFFSET, ENABLE, FALSE)); + + // Viewport clip. There are 16 viewports + for (i = 0; i < 16; i++) { + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, + NV9097_SET_VIEWPORT_CLIP_HORIZONTAL(i), 2); + nvPushSetMethodData(p, pCaps->maxDim << 16); + nvPushSetMethodData(p, pCaps->maxDim << 16); + } + + nvPushImmed(p, NVA06F_SUBCHANNEL_3D, NV9097_SET_PROVOKING_VERTEX, LAST); + + // Use one rop state for all targets + nvPushImmedVal(p, NVA06F_SUBCHANNEL_3D, NV9097_SET_SINGLE_ROP_CONTROL, + NV3D_C(9097, SET_SINGLE_ROP_CONTROL, ENABLE, TRUE)); + nvPushImmedVal(p, NVA06F_SUBCHANNEL_3D, NV9097_SET_SINGLE_CT_WRITE_CONTROL, + NV3D_C(9097, SET_SINGLE_CT_WRITE_CONTROL, ENABLE, TRUE)); + + // Set up blending: enable Ct[0]. It's disabled by default for the rest. + nvPushImmedVal(p, NVA06F_SUBCHANNEL_3D, NV9097_SET_BLEND(0), + NV3D_C(9097, SET_BLEND, ENABLE, TRUE)); + + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, NV9097_SET_BLEND_CONST_ALPHA, 1); + nv3dPushFloat(p, NV3D_FLOAT_ONE); + + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, + NV9097_SET_BLEND_SEPARATE_FOR_ALPHA, 2); + nvPushSetMethodData(p, + NV3D_C(9097, SET_BLEND_SEPARATE_FOR_ALPHA, ENABLE, FALSE)); + nvPushSetMethodData(p, + NV3D_C(9097, SET_BLEND_COLOR_OP, V, OGL_FUNC_ADD)); + + // Upload the pixel shaders. First, attempt to upload through a CPU + // mapping (which is generally faster); if that fails (e.g., because there + // is no space in BAR1 for the mapping), then fall back to uploading inline + // through the pushbuffer. + if (!UploadPrograms(p3dChannel, programCode)) { + pHal->uploadDataInline(p3dChannel, + nv3dGetProgramGpuAddress(p3dChannel), + 0, + programCode, + p3dChannel->programs.code.decompressedSize); + } + + nv3dImportFree(programCode); + programCode = NULL; + + for (i = 0; i < p3dChannel->programs.constants.count; i++) { + const Nv3dShaderConstBufInfo *pInfo = + &p3dChannel->programs.constants.info[i]; + + pHal->uploadDataInline(p3dChannel, + nv3dGetProgramConstantsGpuAddress(p3dChannel), + pInfo->offset, + pInfo->data, + pInfo->size); + } + + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, NV9097_INVALIDATE_SHADER_CACHES, 1); + nvPushSetMethodData(p, + DRF_DEF(9097, _INVALIDATE_SHADER_CACHES, _INSTRUCTION, _TRUE) | + DRF_DEF(9097, _INVALIDATE_SHADER_CACHES, _CONSTANT, _TRUE)); + + if (pCaps->hasProgramRegion) { + gpuAddress = nv3dGetProgramGpuAddress(p3dChannel); + + nvAssert((gpuAddress & 255) == 0); + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, NV9097_SET_PROGRAM_REGION_A, 2); + nvPushSetMethodDataU64(p, gpuAddress); + } + + // Initialize the texture header and sampler area. + // + // To update these things, we upload data through the pushbuffer. The + // upload has an alignment twice the size of a texture header/sampler, so we + // interleave the two. Texture samplers come first. Thus, "texture sampler + // 2i+1" is actually texture header 2i. This allows us to use a single + // upload to update a single texture sampler/header pair if we so desire. + gpuAddress = tex0GpuAddress + offsetof(Nv3dTexture, samp); + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, NV9097_SET_TEX_SAMPLER_POOL_A, 3); + nvPushSetMethodDataU64(p, gpuAddress); + nvPushSetMethodData(p, 0); // Max index. 0 because we use VIA_HEADER mode. + + gpuAddress = tex0GpuAddress + offsetof(Nv3dTexture, head); + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, NV9097_SET_TEX_HEADER_POOL_A, 3); + nvPushSetMethodDataU64(p, gpuAddress); + nvPushSetMethodData(p, 2 * (NV_MAX(p3dChannel->numTextures, 1) - 1)); // Max index + + nvPushImmedVal(p, NVA06F_SUBCHANNEL_3D, NV9097_SET_WINDOW_ORIGIN, + NV3D_C(9097, SET_WINDOW_ORIGIN, MODE, UPPER_LEFT) | + NV3D_C(9097, SET_WINDOW_ORIGIN, FLIP_Y, TRUE)); + + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, NV9097_SET_ZCULL_BOUNDS, 1); + nvPushSetMethodData(p, + NV3D_C(9097, SET_ZCULL_BOUNDS, Z_MIN_UNBOUNDED_ENABLE, FALSE) | + NV3D_C(9097, SET_ZCULL_BOUNDS, Z_MAX_UNBOUNDED_ENABLE, FALSE)); + + pHal->setSpaVersion(p3dChannel); + + pHal->initChannel(p3dChannel); + + _nv3dInitializeStreams(p3dChannel); + + return TRUE; +} + +void nv3dLoadProgram( + Nv3dChannelRec *p3dChannel, + int programIndex) +{ + const Nv3dHal *pHal = p3dChannel->p3dDevice->hal; + const Nv3dProgramInfo *pgm = &p3dChannel->programs.info[programIndex]; + NvPushChannelPtr p = p3dChannel->pPushChannel; + + nvAssert(programIndex < p3dChannel->programs.num); + nvAssert(programIndex >= 0); + nvAssert(pgm->stage < ARRAY_LEN(p3dChannel->currentProgramIndex)); + nvAssert(pgm->bindGroup <= NV3D_HW_BIND_GROUP_LAST); + + if (p3dChannel->currentProgramIndex[pgm->stage] == programIndex) { + return; + } + + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, + NV9097_SET_PIPELINE_SHADER(pgm->stage), 1); + nvPushSetMethodData(p, + NV3D_C(9097, SET_PIPELINE_SHADER, ENABLE, TRUE) | + NV3D_V(9097, SET_PIPELINE_SHADER, TYPE, pgm->type)); + + pHal->setProgramOffset(p3dChannel, pgm->stage, pgm->offset); + + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, + NV9097_SET_PIPELINE_REGISTER_COUNT(pgm->stage), 2); + nvPushSetMethodData(p, pgm->registerCount); + nvPushSetMethodData(p, pgm->bindGroup); + + // Bind or invalidate the compiler-generated constant buffer slot, which the + // compiler always puts in NV3D_CB_SLOT_COMPILER. + if (pgm->constIndex == -1) { + nv3dBindCb(p3dChannel, pgm->bindGroup, + NV3D_CB_SLOT_COMPILER, FALSE); + } else if (p3dChannel->programs.constants.size > 0) { + const Nv3dShaderConstBufInfo *pInfo = + &p3dChannel->programs.constants.info[pgm->constIndex]; + const NvU64 gpuAddress = + nv3dGetProgramConstantsGpuAddress(p3dChannel) + pInfo->offset; + const NvU32 paddedSize = + NV_ALIGN_UP(pInfo->size, p3dChannel->programs.constants.sizeAlign); + + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, + NV9097_SET_CONSTANT_BUFFER_SELECTOR_A, 3); + nvPushSetMethodData(p, paddedSize); + nvPushSetMethodDataU64(p, gpuAddress); + nv3dBindCb(p3dChannel, pgm->bindGroup, NV3D_CB_SLOT_COMPILER, TRUE); + } + + p3dChannel->currentProgramIndex[pgm->stage] = programIndex; +} + +void _nv3dSetProgramOffsetFermi( + Nv3dChannelRec *p3dChannel, + NvU32 stage, + NvU32 offset) +{ + NvPushChannelPtr p = p3dChannel->pPushChannel; + + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, + NV9097_SET_PIPELINE_PROGRAM(stage), 1); + nvPushSetMethodData(p, offset); +} + +void _nv3dInvalidateTexturesFermi( + Nv3dChannelRec *p3dChannel) +{ + NvPushChannelPtr p = p3dChannel->pPushChannel; + + nvPushImmedVal(p, NVA06F_SUBCHANNEL_3D, + NV9097_INVALIDATE_SAMPLER_CACHE, + NV3D_C(9097, INVALIDATE_SAMPLER_CACHE, LINES, ALL)); + nvPushImmedVal(p, NVA06F_SUBCHANNEL_3D, + NV9097_INVALIDATE_TEXTURE_HEADER_CACHE, + NV3D_C(9097, INVALIDATE_TEXTURE_HEADER_CACHE, LINES, ALL)); +} + +void nv3dSetBlendColorCoefficients( + Nv3dChannelPtr p3dChannel, + enum Nv3dBlendOperation op, + NvBool forceNoDstAlphaBits, + NvBool dualSourceBlending) +{ +#define SFACTOR(factor) (NV9097_SET_BLEND_COLOR_SOURCE_COEFF_V_OGL_##factor) +#define DFACTOR(factor) (NV9097_SET_BLEND_COLOR_DEST_COEFF_V_OGL_##factor) +#define OP(op) (NV3D_BLEND_OP_##op) + + static const struct { + NvU32 sfactor; + NvU32 dfactor; + } BlendOps[] = { + [OP(CLEAR)] = {SFACTOR(ZERO), DFACTOR(ZERO)}, + [OP(SRC)] = {SFACTOR(ONE), DFACTOR(ZERO)}, + [OP(DST)] = {SFACTOR(ZERO), DFACTOR(ONE)}, + [OP(OVER)] = {SFACTOR(ONE), DFACTOR(ONE_MINUS_SRC_ALPHA)}, + [OP(OVER_REVERSE)] = {SFACTOR(ONE_MINUS_DST_ALPHA), DFACTOR(ONE)}, + [OP(IN)] = {SFACTOR(DST_ALPHA), DFACTOR(ZERO)}, + [OP(IN_REVERSE)] = {SFACTOR(ZERO), DFACTOR(SRC_ALPHA)}, + [OP(OUT)] = {SFACTOR(ONE_MINUS_DST_ALPHA), DFACTOR(ZERO)}, + [OP(OUT_REVERSE)] = {SFACTOR(ZERO), DFACTOR(ONE_MINUS_SRC_ALPHA)}, + [OP(ATOP)] = {SFACTOR(DST_ALPHA), DFACTOR(ONE_MINUS_SRC_ALPHA)}, + [OP(ATOP_REVERSE)] = {SFACTOR(ONE_MINUS_DST_ALPHA), DFACTOR(SRC_ALPHA)}, + [OP(XOR)] = {SFACTOR(ONE_MINUS_DST_ALPHA), DFACTOR(ONE_MINUS_SRC_ALPHA)}, + [OP(ADD)] = {SFACTOR(ONE), DFACTOR(ONE)}, + [OP(SATURATE)] = {SFACTOR(SRC_ALPHA_SATURATE), DFACTOR(ONE)} + }; + + NvU32 sfactor, dfactor; + + nvAssert(op < ARRAY_LEN(BlendOps)); + + sfactor = BlendOps[op].sfactor; + dfactor = BlendOps[op].dfactor; + + // if we're rendering to a picture that has an XRGB format that HW doesn't + // support, feed in the 1.0 constant DstAlpha value + if (forceNoDstAlphaBits) { + switch (sfactor) { + case SFACTOR(DST_ALPHA): + sfactor = SFACTOR(CONSTANT_ALPHA); + break; + case SFACTOR(ONE_MINUS_DST_ALPHA): + sfactor = SFACTOR(ONE_MINUS_CONSTANT_ALPHA); + break; + default: + break; + } + } + + // If dual-source blending is enabled, swap the dfactor for one that uses + // the second source color. + if (dualSourceBlending) { + switch (dfactor) { + case DFACTOR(SRC_ALPHA): + case DFACTOR(SRC_COLOR): + dfactor = DFACTOR(SRC1COLOR); + break; + case DFACTOR(ONE_MINUS_SRC_ALPHA): + case DFACTOR(ONE_MINUS_SRC_COLOR): + dfactor = DFACTOR(INVSRC1COLOR); + break; + default: + break; + } + } + + Nv3dBlendState nv3dBlendStateColor = { }; + + nv3dBlendStateColor.blendEquation = NV3D_C(9097, SET_BLEND_COLOR_OP, V, OGL_FUNC_ADD); + nv3dBlendStateColor.blendFactorSrc = sfactor; + nv3dBlendStateColor.blendFactorDst = dfactor; + + nv3dSetBlend(p3dChannel, &nv3dBlendStateColor, NULL, NULL); +} + +void nv3dSetBlend( + Nv3dChannelPtr p3dChannel, + const Nv3dBlendState *blendStateColor, + const Nv3dBlendState *blendStateAlpha, + const Nv3dColor *blendColor) +{ + NvPushChannelPtr p = p3dChannel->pPushChannel; + + const Nv3dColor defaultColor = { + NV3D_FLOAT_ONE, + NV3D_FLOAT_ONE, + NV3D_FLOAT_ONE, + NV3D_FLOAT_ONE + }; + + if (blendColor == NULL) { + blendColor = &defaultColor; + } + + if (blendStateColor == NULL && blendStateAlpha == NULL) { + nvPushImmedVal(p, NVA06F_SUBCHANNEL_3D, NV9097_SET_BLEND(0), + NV3D_C(9097, SET_BLEND, ENABLE, FALSE)); + return; + } + + if (blendStateColor != NULL) { + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, NV9097_SET_BLEND_COLOR_OP, 3); + nvPushSetMethodData(p, blendStateColor->blendEquation); + nvPushSetMethodData(p, blendStateColor->blendFactorSrc); + nvPushSetMethodData(p, blendStateColor->blendFactorDst); + } + + if (blendStateAlpha != NULL) { + nvPushImmedVal(p, NVA06F_SUBCHANNEL_3D, NV9097_SET_BLEND_SEPARATE_FOR_ALPHA, + NV3D_C(9097, SET_BLEND_SEPARATE_FOR_ALPHA, ENABLE, TRUE)); + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, NV9097_SET_BLEND_ALPHA_OP, 2); + nvPushSetMethodData(p, blendStateAlpha->blendEquation); + nvPushSetMethodData(p, blendStateAlpha->blendFactorSrc); + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, NV9097_SET_BLEND_ALPHA_DEST_COEFF, 1); + nvPushSetMethodData(p, blendStateAlpha->blendFactorDst); + } else { + nvPushImmedVal(p, NVA06F_SUBCHANNEL_3D, NV9097_SET_BLEND_SEPARATE_FOR_ALPHA, + NV3D_C(9097, SET_BLEND_SEPARATE_FOR_ALPHA, ENABLE, FALSE)); + } + + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, NV9097_SET_BLEND_CONST_RED, 4); + nv3dPushFloat(p, blendColor->red); + nv3dPushFloat(p, blendColor->green); + nv3dPushFloat(p, blendColor->blue); + nv3dPushFloat(p, blendColor->alpha); + + nvPushImmedVal(p, NVA06F_SUBCHANNEL_3D, NV9097_SET_BLEND(0), + NV3D_C(9097, SET_BLEND, ENABLE, TRUE)); + +} + +void _nv3dSetVertexStreamEndFermi( + Nv3dChannelPtr p3dChannel, + enum Nv3dVertexAttributeStreamType stream, + const Nv3dVertexAttributeStreamRec *pStream) +{ + NvPushChannelPtr p = p3dChannel->pPushChannel; + + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, + NV9097_SET_VERTEX_STREAM_LIMIT_A_A(stream), 2); + nvPushSetMethodDataU64(p, pStream->end - 1); +} diff --git a/src/common/unix/nvidia-3d/src/nvidia-3d-hopper.c b/src/common/unix/nvidia-3d/src/nvidia-3d-hopper.c new file mode 100644 index 000000000..9d233a2e4 --- /dev/null +++ b/src/common/unix/nvidia-3d/src/nvidia-3d-hopper.c @@ -0,0 +1,384 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvidia-3d-turing.h" +#include "nvidia-3d-hopper.h" +#include "nvidia-3d.h" + +#include +#include +#include + +void _nv3dInitChannelHopper(Nv3dChannelRec *p3dChannel) +{ + NvPushChannelPtr p = p3dChannel->pPushChannel; + + _nv3dInitChannelTuring(p3dChannel); + + // Select texture header major version 1 for the new Hopper format. + nvPushImmedVal(p, NVA06F_SUBCHANNEL_3D, NVCB97_SET_TEXTURE_HEADER_VERSION, 1); +} + +void _nv3dAssignNv3dTextureHopper( + Nv3dRenderTexInfo info, + Nv3dTexture *tex) +{ + nvAssert(!info.error); + + switch (info.sizes) { + case NV3D_TEXHEAD_A8B8G8R8: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _COMPONENTS, + _SIZES_A8B8G8R8, tex->head); + break; + case NV3D_TEXHEAD_A2B10G10R10: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _COMPONENTS, + _SIZES_A2B10G10R10, tex->head); + break; + case NV3D_TEXHEAD_B5G6R5: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _COMPONENTS, + _SIZES_B5G6R5, tex->head); + break; + case NV3D_TEXHEAD_A1B5G5R5: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _COMPONENTS, + _SIZES_A1B5G5R5, tex->head); + break; + case NV3D_TEXHEAD_R8: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _COMPONENTS, + _SIZES_R8, tex->head); + break; + case NV3D_TEXHEAD_R32: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _COMPONENTS, + _SIZES_R32, tex->head); + break; + case NV3D_TEXHEAD_R16: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _COMPONENTS, + _SIZES_R16, tex->head); + break; + case NV3D_TEXHEAD_G8R8: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _COMPONENTS, + _SIZES_G8R8, tex->head); + break; + case NV3D_TEXHEAD_R16G16B16A16: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _COMPONENTS, + _SIZES_R16_G16_B16_A16, tex->head); + break; + case NV3D_TEXHEAD_R32G32B32A32: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _COMPONENTS, + _SIZES_R32_G32_B32_A32, tex->head); + break; + case NV3D_TEXHEAD_Y8_VIDEO: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _COMPONENTS, + _SIZES_Y8_VIDEO, tex->head); + break; + default: + nvAssert(!"Unrecognized component sizes"); + } + + switch (info.dataType) { + case NV3D_TEXHEAD_NUM_UNORM: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _DATA_TYPE, + _TEX_DATA_TYPE_UNORM, tex->head); + break; + case NV3D_TEXHEAD_NUM_UINT: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _DATA_TYPE, + _TEX_DATA_TYPE_UINT, tex->head); + break; + case NV3D_TEXHEAD_NUM_FLOAT: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _DATA_TYPE, + _TEX_DATA_TYPE_FLOAT, tex->head); + break; + case NV3D_TEXHEAD_NUM_SNORM: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _DATA_TYPE, + _TEX_DATA_TYPE_FLOAT, tex->head); + break; + case NV3D_TEXHEAD_NUM_SINT: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _DATA_TYPE, + _TEX_DATA_TYPE_SINT, tex->head); + break; + } + + switch (info.source.x) { + case NV3D_TEXHEAD_IN_A: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _X_SOURCE, + _IN_A, tex->head); + break; + case NV3D_TEXHEAD_IN_R: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _X_SOURCE, + _IN_R, tex->head); + break; + case NV3D_TEXHEAD_IN_G: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _X_SOURCE, + _IN_G, tex->head); + break; + case NV3D_TEXHEAD_IN_B: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _X_SOURCE, + _IN_B, tex->head); + break; + case NV3D_TEXHEAD_IN_ZERO: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _X_SOURCE, + _IN_ZERO, tex->head); + break; + case NV3D_TEXHEAD_IN_ONE_FLOAT: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _X_SOURCE, + _IN_ONE_FLOAT, tex->head); + break; + } + + switch (info.source.y) { + case NV3D_TEXHEAD_IN_A: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _Y_SOURCE, + _IN_A, tex->head); + break; + case NV3D_TEXHEAD_IN_R: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _Y_SOURCE, + _IN_R, tex->head); + break; + case NV3D_TEXHEAD_IN_G: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _Y_SOURCE, + _IN_G, tex->head); + break; + case NV3D_TEXHEAD_IN_B: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _Y_SOURCE, + _IN_B, tex->head); + break; + case NV3D_TEXHEAD_IN_ZERO: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _Y_SOURCE, + _IN_ZERO, tex->head); + break; + case NV3D_TEXHEAD_IN_ONE_FLOAT: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _Y_SOURCE, + _IN_ONE_FLOAT, tex->head); + break; + } + + switch (info.source.z) { + case NV3D_TEXHEAD_IN_A: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _Z_SOURCE, + _IN_A, tex->head); + break; + case NV3D_TEXHEAD_IN_R: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _Z_SOURCE, + _IN_R, tex->head); + break; + case NV3D_TEXHEAD_IN_G: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _Z_SOURCE, + _IN_G, tex->head); + break; + case NV3D_TEXHEAD_IN_B: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _Z_SOURCE, + _IN_B, tex->head); + break; + case NV3D_TEXHEAD_IN_ZERO: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _Z_SOURCE, + _IN_ZERO, tex->head); + break; + case NV3D_TEXHEAD_IN_ONE_FLOAT: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _Z_SOURCE, + _IN_ONE_FLOAT, tex->head); + break; + } + + switch (info.source.w) { + case NV3D_TEXHEAD_IN_A: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _W_SOURCE, + _IN_A, tex->head); + break; + case NV3D_TEXHEAD_IN_R: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _W_SOURCE, + _IN_R, tex->head); + break; + case NV3D_TEXHEAD_IN_G: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _W_SOURCE, + _IN_G, tex->head); + break; + case NV3D_TEXHEAD_IN_B: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _W_SOURCE, + _IN_B, tex->head); + break; + case NV3D_TEXHEAD_IN_ZERO: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _W_SOURCE, + _IN_ZERO, tex->head); + break; + case NV3D_TEXHEAD_IN_ONE_FLOAT: + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _W_SOURCE, + _IN_ONE_FLOAT, tex->head); + break; + } + + // Default to edge clamping. Our GPU seems to support wrapping + // even with non-normalized coordinates. + tex->samp[0] = + NV3D_C(CB97, TEXSAMP0, ADDRESS_U, CLAMP_TO_EDGE) | + NV3D_C(CB97, TEXSAMP0, ADDRESS_V, CLAMP_TO_EDGE) | + NV3D_C(CB97, TEXSAMP0, ADDRESS_P, CLAMP_TO_EDGE); + + if (info.texType == NV3D_TEX_TYPE_ONE_D_BUFFER) { + FLD_SET_DRF_NUM_MW(CB97, _TEXHEAD_V2_1DRT, _ADDRESS_BITS31TO0, + NvU64_LO32(info.offset), tex->head); + + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_1DRT, _HEADER_VERSION, + _SELECT_ONE_D_RAW_TYPED, tex->head); + FLD_SET_DRF_NUM_MW(CB97_, TEXHEAD_V2_1DRT, _ADDRESS_BITS63TO32, + NvU64_HI32(info.offset), tex->head); + + FLD_SET_DRF_NUM_MW(CB97, _TEXHEAD_V2_1DRT, _WIDTH_MINUS_ONE, + info.width - 1, tex->head); + } else if (info.texType == NV3D_TEX_TYPE_TWO_D_PITCH) { + FLD_SET_DRF_NUM_MW(CB97, _TEXHEAD_V2_PITCH, _ADDRESS_BITS31TO5, + info.offset >> 5, tex->head); + + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_PITCH, _HEADER_VERSION, + _SELECT_PITCH_V2, tex->head); + FLD_SET_DRF_NUM_MW(CB97, _TEXHEAD_V2_PITCH, _ADDRESS_BITS56TO32, + NvU64_HI32(info.offset), tex->head); + + FLD_SET_DRF_NUM_MW(CB97, _TEXHEAD_V2_PITCH, _PITCH_BITS21TO5, + NvU32_LO16(info.pitch >> 5), tex->head); + + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_PITCH, _TEXTURE_TYPE, + _TWO_D_NO_MIPMAP, tex->head); + FLD_SET_DRF_NUM_MW(CB97, _TEXHEAD_V2_PITCH, _WIDTH_MINUS_ONE, + info.width - 1, tex->head); + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_PITCH, _BORDER_SOURCE, + _BORDER_COLOR, tex->head); + + FLD_SET_DRF_NUM_MW(CB97, _TEXHEAD_V2_PITCH, _HEIGHT_MINUS_ONE, + info.height - 1, tex->head); + FLD_SET_DRF_NUM_MW(CB97, _TEXHEAD_V2_PITCH, _NORMALIZED_COORDS, + info.normalizedCoords, tex->head); + } else { + if (info.texType == NV3D_TEX_TYPE_ONE_D) { + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _TEXTURE_TYPE, + _ONE_D, tex->head); + } else if (info.texType == NV3D_TEX_TYPE_TWO_D_BLOCKLINEAR) { + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _TEXTURE_TYPE, + _TWO_D_NO_MIPMAP, tex->head); + } + FLD_SET_DRF_NUM_MW(CB97, _TEXHEAD_V2_BL, _ADDRESS_BITS31TO9, + info.offset >> 9, tex->head); + + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _HEADER_VERSION, + _SELECT_BLOCKLINEAR_V2, tex->head); + FLD_SET_DRF_NUM_MW(CB97, _TEXHEAD_V2_BL, _ADDRESS_BITS56TO32, + NvU64_HI32(info.offset), tex->head); + + FLD_SET_DRF_NUM_MW(CB97, _TEXHEAD_V2_BL, _GOBS_PER_BLOCK_WIDTH, + info.log2GobsPerBlock.x, tex->head); + FLD_SET_DRF_NUM_MW(CB97, _TEXHEAD_V2_BL, _GOBS_PER_BLOCK_HEIGHT, + info.log2GobsPerBlock.y, tex->head); + FLD_SET_DRF_NUM_MW(CB97, _TEXHEAD_V2_BL, _GOBS_PER_BLOCK_DEPTH, + info.log2GobsPerBlock.z, tex->head); + + FLD_SET_DRF_NUM_MW(CB97, _TEXHEAD_V2_BL, _WIDTH_MINUS_ONE, + info.width - 1, tex->head); + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _BORDER_SOURCE, + _BORDER_COLOR, tex->head); + + FLD_SET_DRF_NUM_MW(CB97, _TEXHEAD_V2_BL, _HEIGHT_MINUS_ONE, + info.height - 1, tex->head); + FLD_SET_DRF_NUM_MW(CB97, _TEXHEAD_V2_BL, _DEPTH_MINUS_ONE, + 0, tex->head); + FLD_SET_DRF_NUM_MW(CB97, _TEXHEAD_V2_BL, _NORMALIZED_COORDS, + info.normalizedCoords, tex->head); + } + + switch (info.repeatType) { + case NV3D_TEXHEAD_REPEAT_TYPE_NORMAL: + tex->samp[0] = NV3D_C(CB97, TEXSAMP0, ADDRESS_U, WRAP) | + NV3D_C(CB97, TEXSAMP0, ADDRESS_V, WRAP); + break; + case NV3D_TEXHEAD_REPEAT_TYPE_PAD: + tex->samp[0] = NV3D_C(CB97, TEXSAMP0, ADDRESS_U, CLAMP_TO_EDGE) | + NV3D_C(CB97, TEXSAMP0, ADDRESS_V, CLAMP_TO_EDGE); + break; + case NV3D_TEXHEAD_REPEAT_TYPE_REFLECT: + tex->samp[0] = NV3D_C(CB97, TEXSAMP0, ADDRESS_U, MIRROR) | + NV3D_C(CB97, TEXSAMP0, ADDRESS_V, MIRROR); + break; + case NV3D_TEXHEAD_REPEAT_TYPE_NONE: + tex->samp[0] = NV3D_C(CB97, TEXSAMP0, ADDRESS_U, BORDER) | + NV3D_C(CB97, TEXSAMP0, ADDRESS_V, BORDER); + break; + } + + switch (info.filtering) { + case NV3D_TEXHEAD_FILTER_TYPE_NEAREST: + tex->samp[1] = NV3D_C(CB97, TEXSAMP1, MAG_FILTER, MAG_POINT) | + NV3D_C(CB97, TEXSAMP1, MIN_FILTER, MIN_POINT) | + NV3D_C(CB97, TEXSAMP1, MIP_FILTER, MIP_NONE); + break; + + case NV3D_TEXHEAD_FILTER_TYPE_LINEAR: + tex->samp[1] = NV3D_C(CB97, TEXSAMP1, MAG_FILTER, MAG_LINEAR) | + NV3D_C(CB97, TEXSAMP1, MIN_FILTER, MIN_LINEAR) | + NV3D_C(CB97, TEXSAMP1, MIP_FILTER, MIP_NONE); + break; + + case NV3D_TEXHEAD_FILTER_TYPE_ANISO_2X: + tex->samp[0] |= NV3D_C(CB97, TEXSAMP0, MAX_ANISOTROPY, ANISO_2_TO_1); + tex->samp[1] = NV3D_C(CB97, TEXSAMP1, MAG_FILTER, MAG_LINEAR) | + NV3D_C(CB97, TEXSAMP1, MIN_FILTER, MIN_ANISO) | + NV3D_C(CB97, TEXSAMP1, MIP_FILTER, MIP_NONE); + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _MAX_ANISOTROPY, + _ANISO_2_TO_1, tex->head); + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _ANISO_FINE_SPREAD_MODIFIER, + _SPREAD_MODIFIER_CONST_TWO, tex->head); + + break; + + case NV3D_TEXHEAD_FILTER_TYPE_ANISO_4X: + tex->samp[0] |= NV3D_C(CB97, TEXSAMP0, MAX_ANISOTROPY, ANISO_4_TO_1); + tex->samp[1] = NV3D_C(CB97, TEXSAMP1, MAG_FILTER, MAG_LINEAR) | + NV3D_C(CB97, TEXSAMP1, MIN_FILTER, MIN_ANISO) | + NV3D_C(CB97, TEXSAMP1, MIP_FILTER, MIP_NONE); + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _MAX_ANISOTROPY, + _ANISO_4_TO_1, tex->head); + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _ANISO_FINE_SPREAD_MODIFIER, + _SPREAD_MODIFIER_CONST_TWO, tex->head); + break; + + case NV3D_TEXHEAD_FILTER_TYPE_ANISO_8X: + tex->samp[0] |= NV3D_C(CB97, TEXSAMP0, MAX_ANISOTROPY, ANISO_8_TO_1); + tex->samp[1] = NV3D_C(CB97, TEXSAMP1, MAG_FILTER, MAG_LINEAR) | + NV3D_C(CB97, TEXSAMP1, MIN_FILTER, MIN_ANISO) | + NV3D_C(CB97, TEXSAMP1, MIP_FILTER, MIP_NONE); + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _MAX_ANISOTROPY, + _ANISO_8_TO_1, tex->head); + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _ANISO_FINE_SPREAD_MODIFIER, + _SPREAD_MODIFIER_CONST_TWO, tex->head); + + break; + + case NV3D_TEXHEAD_FILTER_TYPE_ANISO_16X: + tex->samp[0] |= NV3D_C(CB97, TEXSAMP0, MAX_ANISOTROPY, ANISO_16_TO_1); + tex->samp[1] = NV3D_C(CB97, TEXSAMP1, MAG_FILTER, MAG_LINEAR) | + NV3D_C(CB97, TEXSAMP1, MIN_FILTER, MIN_ANISO) | + NV3D_C(CB97, TEXSAMP1, MIP_FILTER, MIP_NONE); + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _MAX_ANISOTROPY, + _ANISO_16_TO_1, tex->head); + FLD_SET_DRF_DEF_MW(CB97, _TEXHEAD_V2_BL, _ANISO_FINE_SPREAD_MODIFIER, + _SPREAD_MODIFIER_CONST_TWO, tex->head); + break; + + } +} diff --git a/src/common/unix/nvidia-3d/src/nvidia-3d-init.c b/src/common/unix/nvidia-3d/src/nvidia-3d-init.c new file mode 100644 index 000000000..2ea47dee8 --- /dev/null +++ b/src/common/unix/nvidia-3d/src/nvidia-3d-init.c @@ -0,0 +1,504 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2005-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + + +#include "nvidia-3d.h" +#include "nvidia-3d-surface.h" +#include "nvidia-3d-types-priv.h" + +#include "nvidia-3d-fermi.h" +#include "nvidia-3d-kepler.h" +#include "nvidia-3d-maxwell.h" +#include "nvidia-3d-pascal.h" +#include "nvidia-3d-volta.h" +#include "nvidia-3d-turing.h" +#include "nvidia-3d-hopper.h" + +#include "nvidia-push-init.h" // nvPushGetSupportedClassIndex() +#include "nvidia-push-utils.h" // nvPushIsAmodel() + +#include // HOPPER_A +#include // ADA_A +#include // AMPERE_B +#include // AMPERE_A +#include // TURING_A +#include // VOLTA_A +#include // PASCAL_B +#include // PASCAL_A +#include // MAXWELL_B +#include // MAXWELL_A + +#include +#include + +#include "g_maxwell_shader_info.h" +#include "g_pascal_shader_info.h" +#include "g_volta_shader_info.h" +#include "g_turing_shader_info.h" +#include "g_ampere_shader_info.h" +#include "g_hopper_shader_info.h" + +#define _NV3D_CHANNEL_PROGRAMS_ENTRY(_archLower, _archCamel, _archUpper) \ + [NV3D_SHADER_ARCH_ ## _archUpper ] = { \ + .num = NUM_PROGRAMS, \ + .info = _archCamel ## ProgramInfo, \ + .maxLocalBytes = _archCamel ## ShaderMaxLocalBytes, \ + .maxStackBytes = _archCamel ## ShaderMaxStackBytes, \ + .code.decompressedSize = _archCamel ## ProgramHeapSize, \ + .code.compressedStart = \ + ({ extern const unsigned char \ + _binary_ ## _archLower ## _shaders_xz_start[]; \ + _binary_ ## _archLower ## _shaders_xz_start; }), \ + .code.compressedEnd = \ + ({ extern const unsigned char \ + _binary_ ## _archLower ## _shaders_xz_end[]; \ + _binary_ ## _archLower ## _shaders_xz_end; }), \ + .constants.info = _archCamel ## ConstBufInfo, \ + .constants.count = \ + (NvU32)ARRAY_LEN(_archCamel ## ConstBufInfo), \ + .constants.size = _archCamel ## ConstBufSize, \ + .constants.sizeAlign = _archCamel ## ConstBufSizeAlign, \ + } + +static Nv3dChannelProgramsRec PickProgramsRec( + const Nv3dDeviceRec *p3dDevice) +{ + const Nv3dChannelProgramsRec programsTable[NV3D_SHADER_ARCH_COUNT] = { + + _NV3D_CHANNEL_PROGRAMS_ENTRY(maxwell, Maxwell, MAXWELL), + _NV3D_CHANNEL_PROGRAMS_ENTRY(pascal, Pascal, PASCAL), + _NV3D_CHANNEL_PROGRAMS_ENTRY(volta, Volta, VOLTA), + _NV3D_CHANNEL_PROGRAMS_ENTRY(turing, Turing, TURING), + _NV3D_CHANNEL_PROGRAMS_ENTRY(ampere, Ampere, AMPERE), + _NV3D_CHANNEL_PROGRAMS_ENTRY(hopper, Hopper, HOPPER), + }; + + return programsTable[p3dDevice->shaderArch]; +} + +#undef _NV3D_CHANNEL_PROGRAMS_ENTRY + + +static NvBool QueryThreadsAndWarpsOneSd( + Nv3dDevicePtr p3dDevice, + NvU32 sd, + NvU32 *pMaxWarps, + NvU32 *pThreadsPerWarp) +{ + NvPushDevicePtr pPushDevice = p3dDevice->pPushDevice; + const NvPushImports *pImports = pPushDevice->pImports; + NvU32 ret; + + NV2080_CTRL_GR_GET_INFO_PARAMS grInfoParams = { 0 }; + struct { + NV2080_CTRL_GR_INFO numSMs; + NV2080_CTRL_GR_INFO maxWarpsPerSM; + NV2080_CTRL_GR_INFO threadsPerWarp; + } grInfo; + + NVMISC_MEMSET(&grInfo, 0, sizeof(grInfo)); + + grInfo.numSMs.index = + NV2080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR; + grInfo.maxWarpsPerSM.index = + NV2080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM; + grInfo.threadsPerWarp.index = + NV2080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP; + + grInfoParams.grInfoListSize = + sizeof(grInfo) / sizeof(NV2080_CTRL_GR_INFO); + + grInfoParams.grInfoList = NV_PTR_TO_NvP64(&grInfo); + + ret = pImports->rmApiControl(pPushDevice, + pPushDevice->subDevice[sd].handle, + NV2080_CTRL_CMD_GR_GET_INFO, + &grInfoParams, + sizeof(grInfoParams)); + + if (ret != NVOS_STATUS_SUCCESS) { + return FALSE; + } + + *pMaxWarps = grInfo.numSMs.data * grInfo.maxWarpsPerSM.data; + *pThreadsPerWarp = grInfo.threadsPerWarp.data; + + return TRUE; +} + +static NvBool GetMaxThreadsAndWarps(Nv3dDevicePtr p3dDevice) +{ + NvU32 sd; + + p3dDevice->maxThreadsPerWarp = 0; + p3dDevice->maxWarps = 0; + + for (sd = 0; sd < p3dDevice->pPushDevice->numSubDevices; sd++) { + + NvU32 maxWarps, threadsPerWarp; + + if (!QueryThreadsAndWarpsOneSd(p3dDevice, sd, + &maxWarps, &threadsPerWarp)) { + return FALSE; + } + + p3dDevice->maxThreadsPerWarp = + NV_MAX(p3dDevice->maxThreadsPerWarp, threadsPerWarp); + + p3dDevice->maxWarps = NV_MAX(p3dDevice->maxWarps, maxWarps); + } + + return TRUE; +} + +/*! + * Get the SM version reported by resman. + * + * \params pPushDevice The nvidia-push device corresponding to the GPU. + * + * \return The SM version of this device. + */ +static NvU32 GetSmVersion( + NvPushDevicePtr pPushDevice) +{ + NvU32 sd, smVersion = NV2080_CTRL_GR_INFO_SM_VERSION_NONE; + + if (nvPushIsAModel(pPushDevice)) { + /* + * On amodel resman cannot tell us the SM version, so we pick + * the SM version based on NVAModelConfig. + */ + static const NvU32 table[] = { + [NV_AMODEL_MAXWELL] = NV2080_CTRL_GR_INFO_SM_VERSION_5_0, + [NV_AMODEL_PASCAL] = NV2080_CTRL_GR_INFO_SM_VERSION_6_0, + [NV_AMODEL_VOLTA] = NV2080_CTRL_GR_INFO_SM_VERSION_7_0, + [NV_AMODEL_TURING] = NV2080_CTRL_GR_INFO_SM_VERSION_7_5, + [NV_AMODEL_AMPERE] = NV2080_CTRL_GR_INFO_SM_VERSION_8_2, + [NV_AMODEL_ADA] = NV2080_CTRL_GR_INFO_SM_VERSION_8_9, + [NV_AMODEL_HOPPER] = NV2080_CTRL_GR_INFO_SM_VERSION_9_0, + }; + + if (pPushDevice->amodelConfig >= ARRAY_LEN(table)) { + return NV2080_CTRL_GR_INFO_SM_VERSION_NONE; + } + + return table[pPushDevice->amodelConfig]; + } + + /* + * Query the SM version from resman. This query is per-subDevice, + * but we use SM version per-device, so assert that the SM version + * matches across subDevices. + */ + for (sd = 0; sd < pPushDevice->numSubDevices; sd++) { + + const NvPushImports *pImports = pPushDevice->pImports; + NV2080_CTRL_GR_GET_INFO_PARAMS params = { }; + NV2080_CTRL_GR_INFO smVersionParams = { }; + NvU32 ret; + + smVersionParams.index = NV2080_CTRL_GR_INFO_INDEX_SM_VERSION; + params.grInfoListSize = 1; + params.grInfoList = NV_PTR_TO_NvP64(&smVersionParams); + + ret = pImports->rmApiControl(pPushDevice, + pPushDevice->subDevice[sd].handle, + NV2080_CTRL_CMD_GR_GET_INFO, + ¶ms, + sizeof(params)); + + if (ret != NVOS_STATUS_SUCCESS) { + return NV2080_CTRL_GR_INFO_SM_VERSION_NONE; + } + + if (sd == 0) { + smVersion = smVersionParams.data; + } else { + nvAssert(smVersion == smVersionParams.data); + } + } + + return smVersion; +} + +/*! + * Get the SPA version to use with the 3D Class. + * + * Note that resman only reports the SM version (the "hardware + * revision"), not the SPA version (the ISA version). So we use a + * table to map from SM version to SPA version. + * + * \params pPushDevice The nvidia-push device corresponding to the GPU. + * \params pSpaVersion The spaVersion to assign. + * + * \return TRUE if the SPA version could be assigned. + */ +static NvBool GetSpaVersion( + NvPushDevicePtr pPushDevice, + Nv3dDeviceSpaVersionRec *pSpaVersion) +{ + static const struct { + NvU32 smVersion; + Nv3dDeviceSpaVersionRec spaVersion; + } table[] = { + /* Maxwell */ + { NV2080_CTRL_GR_INFO_SM_VERSION_5_0, { 5,0 } }, + { NV2080_CTRL_GR_INFO_SM_VERSION_5_2, { 5,2 } }, + { NV2080_CTRL_GR_INFO_SM_VERSION_5_3, { 5,3 } }, + + /* Pascal */ + { NV2080_CTRL_GR_INFO_SM_VERSION_6_0, { 5,5 } }, + { NV2080_CTRL_GR_INFO_SM_VERSION_6_1, { 5,5 } }, + { NV2080_CTRL_GR_INFO_SM_VERSION_6_2, { 5,6 } }, + + /* Volta */ + { NV2080_CTRL_GR_INFO_SM_VERSION_7_0, { 7,0 } }, + { NV2080_CTRL_GR_INFO_SM_VERSION_7_2, { 7,2 } }, + + /* Turing */ + { NV2080_CTRL_GR_INFO_SM_VERSION_7_3, { 7,3 } }, + { NV2080_CTRL_GR_INFO_SM_VERSION_7_5, { 7,5 } }, + + /* Ampere */ + { NV2080_CTRL_GR_INFO_SM_VERSION_8_2, { 8,2 } }, + { NV2080_CTRL_GR_INFO_SM_VERSION_8_6, { 8,6 } }, + { NV2080_CTRL_GR_INFO_SM_VERSION_8_7, { 8,6 } }, + { NV2080_CTRL_GR_INFO_SM_VERSION_8_8, { 8,6 } }, + /* Ada */ + { NV2080_CTRL_GR_INFO_SM_VERSION_8_9, { 8,9 } }, + /* Hopper */ + { NV2080_CTRL_GR_INFO_SM_VERSION_9_0, { 9,0 } }, + }; + + const NvU32 smVersion = GetSmVersion(pPushDevice); + NvU32 i; + + for (i = 0; i < ARRAY_LEN(table); i++) { + if (table[i].smVersion == smVersion) { + *pSpaVersion = table[i].spaVersion; + return TRUE; + } + } + + return FALSE; +} + +static const Nv3dHal _nv3dHalMaxwell = { + _nv3dSetSpaVersionKepler, /* setSpaVersion */ + _nv3dInitChannelMaxwell, /* initChannel */ + _nv3dUploadDataInlineKepler, /* uploadDataInline */ + _nv3dSetProgramOffsetFermi, /* setProgramOffset */ + _nv3dAssignNv3dTextureMaxwell, /* assignNv3dTexture */ + _nv3dSetVertexStreamEndFermi, /* setVertexStreamEnd */ +}; + +static const Nv3dHal _nv3dHalPascal = { + _nv3dSetSpaVersionKepler, /* setSpaVersion */ + _nv3dInitChannelPascal, /* initChannel */ + _nv3dUploadDataInlineKepler, /* uploadDataInline */ + _nv3dSetProgramOffsetFermi, /* setProgramOffset */ + _nv3dAssignNv3dTexturePascal, /* assignNv3dTexture */ + _nv3dSetVertexStreamEndFermi, /* setVertexStreamEnd */ +}; + +static const Nv3dHal _nv3dHalVolta = { + _nv3dSetSpaVersionKepler, /* setSpaVersion */ + _nv3dInitChannelPascal, /* initChannel */ + _nv3dUploadDataInlineKepler, /* uploadDataInline */ + _nv3dSetProgramOffsetVolta, /* setProgramOffset */ + _nv3dAssignNv3dTexturePascal, /* assignNv3dTexture */ + _nv3dSetVertexStreamEndFermi, /* setVertexStreamEnd */ +}; + +static const Nv3dHal _nv3dHalTuring = { + _nv3dSetSpaVersionKepler, /* setSpaVersion */ + _nv3dInitChannelTuring, /* initChannel */ + _nv3dUploadDataInlineKepler, /* uploadDataInline */ + _nv3dSetProgramOffsetVolta, /* setProgramOffset */ + _nv3dAssignNv3dTexturePascal, /* assignNv3dTexture */ + _nv3dSetVertexStreamEndTuring, /* setVertexStreamEnd */ +}; + +static const Nv3dHal _nv3dHalAmpere = { + _nv3dSetSpaVersionKepler, /* setSpaVersion */ + _nv3dInitChannelTuring, /* initChannel */ + _nv3dUploadDataInlineKepler, /* uploadDataInline */ + _nv3dSetProgramOffsetVolta, /* setProgramOffset */ + _nv3dAssignNv3dTexturePascal, /* assignNv3dTexture */ + _nv3dSetVertexStreamEndTuring, /* setVertexStreamEnd */ +}; + +static const Nv3dHal _nv3dHalHopper = { + _nv3dSetSpaVersionKepler, /* setSpaVersion */ + _nv3dInitChannelHopper, /* initChannel */ + _nv3dUploadDataInlineKepler, /* uploadDataInline */ + _nv3dSetProgramOffsetVolta, /* setProgramOffset */ + _nv3dAssignNv3dTextureHopper, /* assignNv3dTexture */ + _nv3dSetVertexStreamEndTuring, /* setVertexStreamEnd */ +}; + +NvBool nv3dAllocDevice( + const Nv3dAllocDeviceParams *pParams, + Nv3dDevicePtr p3dDevice) +{ + static const struct { + NvPushSupportedClass base; + const Nv3dDeviceCapsRec caps; + const Nv3dHal *hal; + enum Nv3dShaderArch shaderArch; + } table[] = { + +#define ENTRY(_classNumber, \ + _arch, \ + _amodelArch, \ + _hasSetBindlessTexture, \ + _hasProgramRegion, \ + _maxDim, \ + _hal) \ + { \ + .base.classNumber = _classNumber, \ + .base.amodelConfig = NV_AMODEL_ ## _amodelArch, \ + .caps.hasSetBindlessTexture = _hasSetBindlessTexture, \ + .caps.hasProgramRegion = _hasProgramRegion, \ + .caps.maxDim = _maxDim, \ + .hal = &_nv3dHal ## _hal, \ + .shaderArch = NV3D_SHADER_ARCH_ ## _arch,\ + } + + /* + * hal--------------------------------------------------+ + * maxDim----------------------------------------+ | + * hasProgramRegion---------------------------+ | | + * hasSetBindlessTexture-------------------+ | | | + * amodel arch----------------+ | | | | + * shader arch---+ | | | | | + * classNumber | | | | | | + * | | | | | | | + */ + ENTRY(HOPPER_A, HOPPER, HOPPER, 0, 0, 32768, Hopper), + ENTRY(ADA_A, AMPERE, ADA, 0, 0, 32768, Ampere), + ENTRY(AMPERE_B, AMPERE, AMPERE, 0, 0, 32768, Ampere), + ENTRY(AMPERE_A, AMPERE, AMPERE, 0, 0, 32768, Ampere), + ENTRY(TURING_A, TURING, TURING, 0, 0, 32768, Turing), + ENTRY(VOLTA_A, VOLTA, VOLTA, 0, 0, 32768, Volta), + ENTRY(PASCAL_B, PASCAL, PASCAL, 1, 1, 32768, Pascal), + ENTRY(PASCAL_A, PASCAL, PASCAL, 1, 1, 32768, Pascal), + ENTRY(MAXWELL_B, MAXWELL, MAXWELL, 1, 1, 16384, Maxwell), + ENTRY(MAXWELL_A, MAXWELL, MAXWELL, 1, 1, 16384, Maxwell), + }; + + int i; + + NVMISC_MEMSET(p3dDevice, 0, sizeof(*p3dDevice)); + + /* find the first supported 3D HAL */ + + i = nvPushGetSupportedClassIndex(pParams->pPushDevice, + table, + sizeof(table[0]), + ARRAY_LEN(table)); + if (i == -1) { + goto fail; + } + + if (!GetSpaVersion(pParams->pPushDevice, &p3dDevice->spaVersion)) { + goto fail; + } + + p3dDevice->pPushDevice = pParams->pPushDevice; + p3dDevice->caps = table[i].caps; + p3dDevice->classNumber = table[i].base.classNumber; + p3dDevice->hal = table[i].hal; + p3dDevice->shaderArch = table[i].shaderArch; + + if (!GetMaxThreadsAndWarps(p3dDevice)) { + goto fail; + } + + return TRUE; + +fail: + nv3dFreeDevice(p3dDevice); + return FALSE; +} + +void nv3dFreeDevice(Nv3dDevicePtr p3dDevice) +{ + /* + * So far, there is nothing to free: Nv3dDevicePtr only stores + * queried information. + */ + NVMISC_MEMSET(p3dDevice, 0, sizeof(*p3dDevice)); +} + +static NvU64 ComputeProgramLocalMemorySize( + const Nv3dChannelRec *p3dChannel) +{ + const Nv3dDeviceRec *p3dDevice = p3dChannel->p3dDevice; + + // LocalMemorySizePerSM needs to be a multiple of 512 + // Note that maxLocalBytes and/or maxStackBytes might be zero. + const NvU64 defaultSizePerWarp = + NV_ALIGN_UP(p3dChannel->programs.maxLocalBytes * + p3dDevice->maxThreadsPerWarp + + p3dChannel->programs.maxStackBytes, 512); + + // shader local memory lower bits must be a multiple of 128kB + return NV_ALIGN_UP(defaultSizePerWarp * p3dDevice->maxWarps, 128*1024); +} + +NvBool nv3dAllocChannelState( + const Nv3dAllocChannelStateParams *pParams, + Nv3dChannelPtr p3dChannel) +{ + NVMISC_MEMSET(p3dChannel, 0, sizeof(*p3dChannel)); + + p3dChannel->p3dDevice = pParams->p3dDevice; + + p3dChannel->numTextures = pParams->numTextures; + p3dChannel->numTextureBindings = pParams->numTextureBindings; + + p3dChannel->hasFrameBoundaries = pParams->hasFrameBoundaries; + + p3dChannel->programs = PickProgramsRec(pParams->p3dDevice); + + p3dChannel->programLocalMemorySize = + ComputeProgramLocalMemorySize(p3dChannel); + + _nv3dAssignSurfaceOffsets(pParams, p3dChannel); + + return TRUE; +} + +void nv3dFreeChannelState(Nv3dChannelPtr p3dChannel) +{ + int sd; + for (sd = 0; sd < NV_MAX_SUBDEVICES; sd++) { + nvAssert(p3dChannel->surface.handle[sd] == 0); + } + nvAssert(p3dChannel->pPushChannel == NULL); + + NVMISC_MEMSET(p3dChannel, 0, sizeof(*p3dChannel)); +} + diff --git a/src/common/unix/nvidia-3d/src/nvidia-3d-kepler.c b/src/common/unix/nvidia-3d/src/nvidia-3d-kepler.c new file mode 100644 index 000000000..0dec5f43f --- /dev/null +++ b/src/common/unix/nvidia-3d/src/nvidia-3d-kepler.c @@ -0,0 +1,154 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvidia-3d-kepler.h" +#include "nvidia-3d.h" +#include "nvidia-3d-constant-buffers.h" +#include "nvidia-3d-shader-constants.h" + +#include +#include + +void _nv3dSetSpaVersionKepler(Nv3dChannelRec *p3dChannel) +{ + NvPushChannelPtr pPushChannel = p3dChannel->pPushChannel; + const NvU16 major = p3dChannel->p3dDevice->spaVersion.major; + const NvU16 minor = p3dChannel->p3dDevice->spaVersion.minor; + + // Tell AModel or fmodel what shader model version to use. This has no + // effect on real hardware. The SM version (the "hardware revision" of the + // SM block) does not always match the SPA version (the ISA version). + nvPushMethod(pPushChannel, NVA06F_SUBCHANNEL_3D, + NVA097_SET_SPA_VERSION, 1); + nvPushSetMethodData(pPushChannel, + NV3D_V(A097, SET_SPA_VERSION, MAJOR, major) | + NV3D_V(A097, SET_SPA_VERSION, MINOR, minor)); +} + +void _nv3dInitChannelKepler(Nv3dChannelRec *p3dChannel) +{ + NvPushChannelPtr p = p3dChannel->pPushChannel; + + // Configure constant buffer slot NV3D_CB_SLOT_BINDLESS_TEXTURE as the + // place the texture binding table is stored. This is obsolete on Volta and + // later, so don't run it there. + if (p3dChannel->p3dDevice->caps.hasSetBindlessTexture) { + nvPushImmedVal(p, NVA06F_SUBCHANNEL_3D, + NVA097_SET_BINDLESS_TEXTURE, + NV3D_V(A097, SET_BINDLESS_TEXTURE, CONSTANT_BUFFER_SLOT_SELECT, + NV3D_CB_SLOT_BINDLESS_TEXTURE)); + } + + // Disable shader exceptions. This matches OpenGL driver behavior. + nvPushImmedVal(p, NVA06F_SUBCHANNEL_3D, + NV9097_SET_SHADER_EXCEPTIONS, + NV3D_C(9097, SET_SHADER_EXCEPTIONS, ENABLE, FALSE)); +} + +/*! + * Upload data using the INLINE_TO_MEMORY methods embedded in the KEPLER_A + * class. + * + * The number of dwords pushed inline is limited by nvPushMaxMethodCount(). + * Push the data in multiple chunks, if necessary. + */ +void _nv3dUploadDataInlineKepler( + Nv3dChannelRec *p3dChannel, + NvU64 gpuBaseAddress, + size_t offset, + const void *data, + size_t bytes) +{ + NvPushChannelPtr p = p3dChannel->pPushChannel; + /* + * Below we use '1 + dwordsThisChunk' as the method count, so subtract one + * when computing chunkSizeDwords. + */ + const NvU32 chunkSizeDwords = nvPushMaxMethodCount(p) - 1; + const NvU32 chunkSize = chunkSizeDwords * 4; /* in bytes */ + size_t bytesSoFar; + + // Only allow uploading complete dwords. + nvAssert((bytes & 3) == 0); + + for (bytesSoFar = 0; bytesSoFar < bytes; bytesSoFar += chunkSize) { + + const NvU32 bytesThisChunk = NV_MIN(bytes - bytesSoFar, chunkSize); + const NvU32 dwordsThisChunk = bytesThisChunk / 4; + + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, NVA097_LINE_LENGTH_IN, 5); + nvPushSetMethodData(p, bytesThisChunk); + nvPushSetMethodData(p, 1); // NVA097_LINE_COUNT + nvPushSetMethodDataU64(p, gpuBaseAddress + offset + bytesSoFar); + nvPushSetMethodData(p, bytesThisChunk); // NVA097_PITCH_OUT + + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, NVA097_SET_DST_WIDTH, 2); + nvPushSetMethodData(p, bytesThisChunk); + nvPushSetMethodData(p, 1); // NVA097_SET_DST_HEIGHT + + nvPushMethodOneIncr(p, NVA06F_SUBCHANNEL_3D, NVA097_LAUNCH_DMA, + 1 + dwordsThisChunk); + nvPushSetMethodData(p, + NV3D_C(A097, LAUNCH_DMA, DST_MEMORY_LAYOUT, PITCH) | + // Disable flush -- As long as only 3D requires the data uploaded, + // we don't need to incur the performance penalty of a sys-membar. + NV3D_C(A097, LAUNCH_DMA, COMPLETION_TYPE, FLUSH_DISABLE) | + NV3D_C(A097, LAUNCH_DMA, INTERRUPT_TYPE, NONE) | + NV3D_C(A097, LAUNCH_DMA, SYSMEMBAR_DISABLE, TRUE)); + nvPushInlineData(p, (const NvU8 *)data + bytesSoFar, dwordsThisChunk); + } +} + +void _nv3dBindTexturesKepler( + Nv3dChannelPtr p3dChannel, + int programIndex, + const int *textureBindingIndices) +{ + const NvU16 numTextureBindings = p3dChannel->numTextureBindings; + NvPushChannelUnion *remappedBinding = NULL; + NvU8 slot; + const NvU64 gpuAddress = + nv3dGetBindlessTextureConstantBufferGpuAddress(p3dChannel); + + nv3dSelectCbAddress(p3dChannel, gpuAddress, NV3D_CONSTANT_BUFFER_SIZE); + nv3dBindCb(p3dChannel, NV3D_HW_BIND_GROUP_FRAGMENT, + NV3D_CB_SLOT_BINDLESS_TEXTURE, TRUE); + /* + * Set up the header in the pushbuffer for the LOAD_CONSTANTS method. The + * below loop will write the data to upload directly into the pushbuffer. + */ + remappedBinding = nv3dLoadConstantsHeader(p3dChannel, 0, + numTextureBindings); + + for (slot = 0; slot < numTextureBindings; slot++) { + int tex = textureBindingIndices[slot]; + + /* + * Bindless texture packed pointers. Technically, these consist of + * a header at bits 19:0 and a sampler in 32:20, but we don't need + * to set a separate header because we enabled + * SET_SAMPLER_BINDING_VIA_HEADER_BINDING. + */ + remappedBinding[slot].u = tex * 2; + } +} diff --git a/src/common/unix/nvidia-3d/src/nvidia-3d-maxwell.c b/src/common/unix/nvidia-3d/src/nvidia-3d-maxwell.c new file mode 100644 index 000000000..295f827c3 --- /dev/null +++ b/src/common/unix/nvidia-3d/src/nvidia-3d-maxwell.c @@ -0,0 +1,435 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvidia-3d-maxwell.h" +#include "nvidia-3d-kepler.h" +#include "nvidia-3d.h" + +#include "class/clb097.h" +#include "class/clb097tex.h" +#include + +void _nv3dInitChannelMaxwell(Nv3dChannelRec *p3dChannel) +{ + NvPushChannelPtr p = p3dChannel->pPushChannel; + const Nv3dDeviceRec *p3dDevice = p3dChannel->p3dDevice; + + _nv3dInitChannelKepler(p3dChannel); + + if (p3dDevice->classNumber == MAXWELL_A) { + /* + * Use Maxwell texture header format. + * + * maxwell.mfs says: + * NOTE: this method is required to be sent in GM10x. It is ignored + * and treated as a NOP in GM20x. + * + * And on later chips, it is removed and causes exceptions. So we only + * send this on GM10x (class MAXWELL_A). + */ + nvPushImmed(p, NVA06F_SUBCHANNEL_3D, + NVB097_SET_SELECT_MAXWELL_TEXTURE_HEADERS, TRUE); + } +} + +void _nv3dAssignNv3dTextureMaxwell( + Nv3dRenderTexInfo info, + Nv3dTexture *tex) +{ + NvU32 hi_offset = NvU32_LO16(info.offset >> 32); + + nvAssert(!info.error); + + switch (info.sizes) { + case NV3D_TEXHEAD_A8B8G8R8: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _COMPONENTS, + _SIZES_A8B8G8R8, tex->head); + break; + case NV3D_TEXHEAD_A2B10G10R10: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _COMPONENTS, + _SIZES_A2B10G10R10, tex->head); + break; + case NV3D_TEXHEAD_B5G6R5: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _COMPONENTS, + _SIZES_B5G6R5, tex->head); + break; + case NV3D_TEXHEAD_A1B5G5R5: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _COMPONENTS, + _SIZES_A1B5G5R5, tex->head); + break; + case NV3D_TEXHEAD_R8: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _COMPONENTS, + _SIZES_R8, tex->head); + break; + case NV3D_TEXHEAD_R32: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _COMPONENTS, + _SIZES_R32, tex->head); + break; + case NV3D_TEXHEAD_R16: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _COMPONENTS, + _SIZES_R16, tex->head); + break; + case NV3D_TEXHEAD_G8R8: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _COMPONENTS, + _SIZES_G8R8, tex->head); + break; + case NV3D_TEXHEAD_R16G16B16A16: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _COMPONENTS, + _SIZES_R16_G16_B16_A16, tex->head); + break; + case NV3D_TEXHEAD_R32G32B32A32: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _COMPONENTS, + _SIZES_R32_G32_B32_A32, tex->head); + break; + case NV3D_TEXHEAD_Y8_VIDEO: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _COMPONENTS, + _SIZES_Y8_VIDEO, tex->head); + break; + default: + nvAssert(!"Unrecognized component sizes"); + } + + switch (info.dataType) { + case NV3D_TEXHEAD_NUM_UNORM: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _R_DATA_TYPE, + _NUM_UNORM, tex->head); + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _G_DATA_TYPE, + _NUM_UNORM, tex->head); + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _B_DATA_TYPE, + _NUM_UNORM, tex->head); + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _A_DATA_TYPE, + _NUM_UNORM, tex->head); + break; + case NV3D_TEXHEAD_NUM_UINT: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _R_DATA_TYPE, + _NUM_UINT, tex->head); + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _G_DATA_TYPE, + _NUM_UINT, tex->head); + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _B_DATA_TYPE, + _NUM_UINT, tex->head); + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _A_DATA_TYPE, + _NUM_UINT, tex->head); + break; + case NV3D_TEXHEAD_NUM_FLOAT: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _R_DATA_TYPE, + _NUM_FLOAT, tex->head); + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _G_DATA_TYPE, + _NUM_FLOAT, tex->head); + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _B_DATA_TYPE, + _NUM_FLOAT, tex->head); + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _A_DATA_TYPE, + _NUM_FLOAT, tex->head); + break; + case NV3D_TEXHEAD_NUM_SNORM: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _R_DATA_TYPE, + _NUM_FLOAT, tex->head); + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _G_DATA_TYPE, + _NUM_FLOAT, tex->head); + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _B_DATA_TYPE, + _NUM_FLOAT, tex->head); + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _A_DATA_TYPE, + _NUM_FLOAT, tex->head); + break; + case NV3D_TEXHEAD_NUM_SINT: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _R_DATA_TYPE, + _NUM_SINT, tex->head); + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _G_DATA_TYPE, + _NUM_SINT, tex->head); + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _B_DATA_TYPE, + _NUM_SINT, tex->head); + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _A_DATA_TYPE, + _NUM_SINT, tex->head); + break; + } + + switch (info.source.x) { + case NV3D_TEXHEAD_IN_A: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _X_SOURCE, + _IN_A, tex->head); + break; + case NV3D_TEXHEAD_IN_R: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _X_SOURCE, + _IN_R, tex->head); + break; + case NV3D_TEXHEAD_IN_G: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _X_SOURCE, + _IN_G, tex->head); + break; + case NV3D_TEXHEAD_IN_B: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _X_SOURCE, + _IN_B, tex->head); + break; + case NV3D_TEXHEAD_IN_ZERO: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _X_SOURCE, + _IN_ZERO, tex->head); + break; + case NV3D_TEXHEAD_IN_ONE_FLOAT: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _X_SOURCE, + _IN_ONE_FLOAT, tex->head); + break; + } + + switch (info.source.y) { + case NV3D_TEXHEAD_IN_A: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _Y_SOURCE, + _IN_A, tex->head); + break; + case NV3D_TEXHEAD_IN_R: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _Y_SOURCE, + _IN_R, tex->head); + break; + case NV3D_TEXHEAD_IN_G: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _Y_SOURCE, + _IN_G, tex->head); + break; + case NV3D_TEXHEAD_IN_B: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _Y_SOURCE, + _IN_B, tex->head); + break; + case NV3D_TEXHEAD_IN_ZERO: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _Y_SOURCE, + _IN_ZERO, tex->head); + break; + case NV3D_TEXHEAD_IN_ONE_FLOAT: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _Y_SOURCE, + _IN_ONE_FLOAT, tex->head); + break; + } + + switch (info.source.z) { + case NV3D_TEXHEAD_IN_A: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _Z_SOURCE, + _IN_A, tex->head); + break; + case NV3D_TEXHEAD_IN_R: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _Z_SOURCE, + _IN_R, tex->head); + break; + case NV3D_TEXHEAD_IN_G: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _Z_SOURCE, + _IN_G, tex->head); + break; + case NV3D_TEXHEAD_IN_B: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _Z_SOURCE, + _IN_B, tex->head); + break; + case NV3D_TEXHEAD_IN_ZERO: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _Z_SOURCE, + _IN_ZERO, tex->head); + break; + case NV3D_TEXHEAD_IN_ONE_FLOAT: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _Z_SOURCE, + _IN_ONE_FLOAT, tex->head); + break; + } + + switch (info.source.w) { + case NV3D_TEXHEAD_IN_A: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _W_SOURCE, + _IN_A, tex->head); + break; + case NV3D_TEXHEAD_IN_R: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _W_SOURCE, + _IN_R, tex->head); + break; + case NV3D_TEXHEAD_IN_G: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _W_SOURCE, + _IN_G, tex->head); + break; + case NV3D_TEXHEAD_IN_B: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _W_SOURCE, + _IN_B, tex->head); + break; + case NV3D_TEXHEAD_IN_ZERO: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _W_SOURCE, + _IN_ZERO, tex->head); + break; + case NV3D_TEXHEAD_IN_ONE_FLOAT: + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _W_SOURCE, + _IN_ONE_FLOAT, tex->head); + break; + } + + // Default to edge clamping. Our GPU seems to support wrapping + // even with non-normalized coordinates. + tex->samp[0] = + NV3D_C(B097, TEXSAMP0, ADDRESS_U, CLAMP_TO_EDGE) | + NV3D_C(B097, TEXSAMP0, ADDRESS_V, CLAMP_TO_EDGE) | + NV3D_C(B097, TEXSAMP0, ADDRESS_P, CLAMP_TO_EDGE); + + if (info.texType == NV3D_TEX_TYPE_ONE_D_BUFFER) { + FLD_SET_DRF_NUM_MW(B097, _TEXHEAD_1D, _ADDRESS_BITS31TO0, + NvU64_LO32(info.offset), tex->head); + + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_1D, _HEADER_VERSION, + _SELECT_ONE_D_BUFFER, tex->head); + FLD_SET_DRF_NUM_MW(B097_, TEXHEAD_1D_, ADDRESS_BITS47TO32, + hi_offset, tex->head); + + FLD_SET_DRF_NUM_MW(B097, _TEXHEAD_1D, _WIDTH_MINUS_ONE_BITS31TO16, + NvU32_HI16(info.width - 1), tex->head); + + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_1D, _TEXTURE_TYPE, + _ONE_D_BUFFER, tex->head); + FLD_SET_DRF_NUM_MW(B097, _TEXHEAD_1D, _WIDTH_MINUS_ONE_BITS15TO0, + NvU32_LO16(info.width - 1), tex->head); + } else if (info.texType == NV3D_TEX_TYPE_TWO_D_PITCH) { + FLD_SET_DRF_NUM_MW(B097, _TEXHEAD_PITCH, _ADDRESS_BITS31TO5, + (NvU32)((info.offset >> 5) & 0x7ffffff), tex->head); + + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_PITCH, _HEADER_VERSION, + _SELECT_PITCH, tex->head); + FLD_SET_DRF_NUM_MW(B097, _TEXHEAD_PITCH, _ADDRESS_BITS47TO32, + hi_offset, tex->head); + + FLD_SET_DRF_NUM_MW(B097, _TEXHEAD_PITCH, _PITCH_BITS20TO5, + NvU32_LO16(info.pitch >> 5), tex->head); + + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_PITCH, _TEXTURE_TYPE, + _TWO_D_NO_MIPMAP, tex->head); + FLD_SET_DRF_NUM_MW(B097, _TEXHEAD_PITCH, _WIDTH_MINUS_ONE, + info.width - 1, tex->head); + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_PITCH, _BORDER_SIZE, + _BORDER_SAMPLER_COLOR, tex->head); + + FLD_SET_DRF_NUM_MW(B097, _TEXHEAD_PITCH, _HEIGHT_MINUS_ONE, + info.height - 1, tex->head); + FLD_SET_DRF_NUM_MW(B097, _TEXHEAD_PITCH, _DEPTH_MINUS_ONE, + 0, tex->head); + FLD_SET_DRF_NUM_MW(B097, _TEXHEAD_PITCH, _NORMALIZED_COORDS, + info.normalizedCoords, tex->head); + } else { + if (info.texType == NV3D_TEX_TYPE_ONE_D) { + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _TEXTURE_TYPE, + _ONE_D, tex->head); + } else if (info.texType == NV3D_TEX_TYPE_TWO_D_BLOCKLINEAR) { + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _TEXTURE_TYPE, + _TWO_D_NO_MIPMAP, tex->head); + } + FLD_SET_DRF_NUM_MW(B097, _TEXHEAD_BL, _ADDRESS_BITS31TO9, + (info.offset >> 9) & 0x7fffff, tex->head); + + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _HEADER_VERSION, + _SELECT_BLOCKLINEAR, tex->head); + FLD_SET_DRF_NUM_MW(B097, _TEXHEAD_BL, _ADDRESS_BITS47TO32, + hi_offset, tex->head); + + FLD_SET_DRF_NUM_MW(B097, _TEXHEAD_BL, _GOBS_PER_BLOCK_WIDTH, + info.log2GobsPerBlock.x, tex->head); + FLD_SET_DRF_NUM_MW(B097, _TEXHEAD_BL, _GOBS_PER_BLOCK_HEIGHT, + info.log2GobsPerBlock.y, tex->head); + FLD_SET_DRF_NUM_MW(B097, _TEXHEAD_BL, _GOBS_PER_BLOCK_DEPTH, + info.log2GobsPerBlock.z, tex->head); + FLD_SET_DRF_NUM_MW(B097, _TEXHEAD_BL, _WIDTH_MINUS_ONE, + info.width - 1, tex->head); + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _BORDER_SIZE, + _BORDER_SAMPLER_COLOR, tex->head); + + FLD_SET_DRF_NUM_MW(B097, _TEXHEAD_BL, _HEIGHT_MINUS_ONE, + info.height - 1, tex->head); + FLD_SET_DRF_NUM_MW(B097, _TEXHEAD_BL, _DEPTH_MINUS_ONE, + 0, tex->head); + FLD_SET_DRF_NUM_MW(B097, _TEXHEAD_BL, _NORMALIZED_COORDS, + info.normalizedCoords, tex->head); + } + + switch (info.repeatType) { + case NV3D_TEXHEAD_REPEAT_TYPE_NORMAL: + tex->samp[0] = NV3D_C(B097, TEXSAMP0, ADDRESS_U, WRAP) | + NV3D_C(B097, TEXSAMP0, ADDRESS_V, WRAP); + break; + case NV3D_TEXHEAD_REPEAT_TYPE_PAD: + tex->samp[0] = NV3D_C(B097, TEXSAMP0, ADDRESS_U, CLAMP_TO_EDGE) | + NV3D_C(B097, TEXSAMP0, ADDRESS_V, CLAMP_TO_EDGE); + break; + case NV3D_TEXHEAD_REPEAT_TYPE_REFLECT: + tex->samp[0] = NV3D_C(B097, TEXSAMP0, ADDRESS_U, MIRROR) | + NV3D_C(B097, TEXSAMP0, ADDRESS_V, MIRROR); + break; + case NV3D_TEXHEAD_REPEAT_TYPE_NONE: + tex->samp[0] = NV3D_C(B097, TEXSAMP0, ADDRESS_U, BORDER) | + NV3D_C(B097, TEXSAMP0, ADDRESS_V, BORDER); + break; + } + + switch (info.filtering) { + case NV3D_TEXHEAD_FILTER_TYPE_NEAREST: + tex->samp[1] = NV3D_C(B097, TEXSAMP1, MAG_FILTER, MAG_POINT) | + NV3D_C(B097, TEXSAMP1, MIN_FILTER, MIN_POINT) | + NV3D_C(B097, TEXSAMP1, MIP_FILTER, MIP_NONE); + break; + + case NV3D_TEXHEAD_FILTER_TYPE_LINEAR: + tex->samp[1] = NV3D_C(B097, TEXSAMP1, MAG_FILTER, MAG_LINEAR) | + NV3D_C(B097, TEXSAMP1, MIN_FILTER, MIN_LINEAR) | + NV3D_C(B097, TEXSAMP1, MIP_FILTER, MIP_NONE); + break; + + case NV3D_TEXHEAD_FILTER_TYPE_ANISO_2X: + tex->samp[0] |= NV3D_C(B097, TEXSAMP0, MAX_ANISOTROPY, ANISO_2_TO_1); + tex->samp[1] = NV3D_C(B097, TEXSAMP1, MAG_FILTER, MAG_LINEAR) | + NV3D_C(B097, TEXSAMP1, MIN_FILTER, MIN_ANISO) | + NV3D_C(B097, TEXSAMP1, MIP_FILTER, MIP_NONE); + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _MAX_ANISOTROPY, + _ANISO_2_TO_1, tex->head); + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _ANISO_FINE_SPREAD_MODIFIER, + _SPREAD_MODIFIER_CONST_TWO, tex->head); + + break; + + case NV3D_TEXHEAD_FILTER_TYPE_ANISO_4X: + tex->samp[0] |= NV3D_C(B097, TEXSAMP0, MAX_ANISOTROPY, ANISO_4_TO_1); + tex->samp[1] = NV3D_C(B097, TEXSAMP1, MAG_FILTER, MAG_LINEAR) | + NV3D_C(B097, TEXSAMP1, MIN_FILTER, MIN_ANISO) | + NV3D_C(B097, TEXSAMP1, MIP_FILTER, MIP_NONE); + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _MAX_ANISOTROPY, + _ANISO_4_TO_1, tex->head); + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _ANISO_FINE_SPREAD_MODIFIER, + _SPREAD_MODIFIER_CONST_TWO, tex->head); + break; + + case NV3D_TEXHEAD_FILTER_TYPE_ANISO_8X: + tex->samp[0] |= NV3D_C(B097, TEXSAMP0, MAX_ANISOTROPY, ANISO_8_TO_1); + tex->samp[1] = NV3D_C(B097, TEXSAMP1, MAG_FILTER, MAG_LINEAR) | + NV3D_C(B097, TEXSAMP1, MIN_FILTER, MIN_ANISO) | + NV3D_C(B097, TEXSAMP1, MIP_FILTER, MIP_NONE); + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _MAX_ANISOTROPY, + _ANISO_8_TO_1, tex->head); + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _ANISO_FINE_SPREAD_MODIFIER, + _SPREAD_MODIFIER_CONST_TWO, tex->head); + + break; + + case NV3D_TEXHEAD_FILTER_TYPE_ANISO_16X: + tex->samp[0] |= NV3D_C(B097, TEXSAMP0, MAX_ANISOTROPY, ANISO_16_TO_1); + tex->samp[1] = NV3D_C(B097, TEXSAMP1, MAG_FILTER, MAG_LINEAR) | + NV3D_C(B097, TEXSAMP1, MIN_FILTER, MIN_ANISO) | + NV3D_C(B097, TEXSAMP1, MIP_FILTER, MIP_NONE); + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _MAX_ANISOTROPY, + _ANISO_16_TO_1, tex->head); + FLD_SET_DRF_DEF_MW(B097, _TEXHEAD_BL, _ANISO_FINE_SPREAD_MODIFIER, + _SPREAD_MODIFIER_CONST_TWO, tex->head); + break; + + } +} diff --git a/src/common/unix/nvidia-3d/src/nvidia-3d-pascal.c b/src/common/unix/nvidia-3d/src/nvidia-3d-pascal.c new file mode 100644 index 000000000..fe7ae447c --- /dev/null +++ b/src/common/unix/nvidia-3d/src/nvidia-3d-pascal.c @@ -0,0 +1,431 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvidia-3d-pascal.h" +#include "nvidia-3d-maxwell.h" +#include "nvidia-3d.h" + +#include "class/clc197.h" /* NVC197_SET_GO_IDLE_TIMEOUT */ +#include "class/clc097tex.h" +#include + +void _nv3dInitChannelPascal(Nv3dChannelRec *p3dChannel) +{ + NvPushChannelPtr p = p3dChannel->pPushChannel; + + _nv3dInitChannelMaxwell(p3dChannel); + + if (!p3dChannel->hasFrameBoundaries) { + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, NVC197_SET_GO_IDLE_TIMEOUT, 1); + nvPushSetMethodData(p, 0x800); + } +} + +void _nv3dAssignNv3dTexturePascal( + Nv3dRenderTexInfo info, + Nv3dTexture *tex) +{ + nvAssert(!info.error); + + switch (info.sizes) { + case NV3D_TEXHEAD_A8B8G8R8: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _COMPONENTS, + _SIZES_A8B8G8R8, tex->head); + break; + case NV3D_TEXHEAD_A2B10G10R10: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _COMPONENTS, + _SIZES_A2B10G10R10, tex->head); + break; + case NV3D_TEXHEAD_B5G6R5: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _COMPONENTS, + _SIZES_B5G6R5, tex->head); + break; + case NV3D_TEXHEAD_A1B5G5R5: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _COMPONENTS, + _SIZES_A1B5G5R5, tex->head); + break; + case NV3D_TEXHEAD_R8: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _COMPONENTS, + _SIZES_R8, tex->head); + break; + case NV3D_TEXHEAD_R32: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _COMPONENTS, + _SIZES_R32, tex->head); + break; + case NV3D_TEXHEAD_R16: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _COMPONENTS, + _SIZES_R16, tex->head); + break; + case NV3D_TEXHEAD_G8R8: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _COMPONENTS, + _SIZES_G8R8, tex->head); + break; + case NV3D_TEXHEAD_R16G16B16A16: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _COMPONENTS, + _SIZES_R16_G16_B16_A16, tex->head); + break; + case NV3D_TEXHEAD_R32G32B32A32: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _COMPONENTS, + _SIZES_R32_G32_B32_A32, tex->head); + break; + case NV3D_TEXHEAD_Y8_VIDEO: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _COMPONENTS, + _SIZES_Y8_VIDEO, tex->head); + break; + default: + nvAssert(!"Unrecognized component sizes"); + } + + switch (info.dataType) { + case NV3D_TEXHEAD_NUM_UNORM: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _R_DATA_TYPE, + _NUM_UNORM, tex->head); + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _G_DATA_TYPE, + _NUM_UNORM, tex->head); + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _B_DATA_TYPE, + _NUM_UNORM, tex->head); + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _A_DATA_TYPE, + _NUM_UNORM, tex->head); + break; + case NV3D_TEXHEAD_NUM_UINT: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _R_DATA_TYPE, + _NUM_UINT, tex->head); + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _G_DATA_TYPE, + _NUM_UINT, tex->head); + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _B_DATA_TYPE, + _NUM_UINT, tex->head); + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _A_DATA_TYPE, + _NUM_UINT, tex->head); + break; + case NV3D_TEXHEAD_NUM_FLOAT: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _R_DATA_TYPE, + _NUM_FLOAT, tex->head); + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _G_DATA_TYPE, + _NUM_FLOAT, tex->head); + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _B_DATA_TYPE, + _NUM_FLOAT, tex->head); + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _A_DATA_TYPE, + _NUM_FLOAT, tex->head); + break; + case NV3D_TEXHEAD_NUM_SNORM: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _R_DATA_TYPE, + _NUM_FLOAT, tex->head); + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _G_DATA_TYPE, + _NUM_FLOAT, tex->head); + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _B_DATA_TYPE, + _NUM_FLOAT, tex->head); + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _A_DATA_TYPE, + _NUM_FLOAT, tex->head); + break; + case NV3D_TEXHEAD_NUM_SINT: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _R_DATA_TYPE, + _NUM_SINT, tex->head); + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _G_DATA_TYPE, + _NUM_SINT, tex->head); + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _B_DATA_TYPE, + _NUM_SINT, tex->head); + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _A_DATA_TYPE, + _NUM_SINT, tex->head); + break; + } + + switch (info.source.x) { + case NV3D_TEXHEAD_IN_A: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _X_SOURCE, + _IN_A, tex->head); + break; + case NV3D_TEXHEAD_IN_R: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _X_SOURCE, + _IN_R, tex->head); + break; + case NV3D_TEXHEAD_IN_G: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _X_SOURCE, + _IN_G, tex->head); + break; + case NV3D_TEXHEAD_IN_B: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _X_SOURCE, + _IN_B, tex->head); + break; + case NV3D_TEXHEAD_IN_ZERO: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _X_SOURCE, + _IN_ZERO, tex->head); + break; + case NV3D_TEXHEAD_IN_ONE_FLOAT: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _X_SOURCE, + _IN_ONE_FLOAT, tex->head); + break; + } + + switch (info.source.y) { + case NV3D_TEXHEAD_IN_A: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _Y_SOURCE, + _IN_A, tex->head); + break; + case NV3D_TEXHEAD_IN_R: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _Y_SOURCE, + _IN_R, tex->head); + break; + case NV3D_TEXHEAD_IN_G: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _Y_SOURCE, + _IN_G, tex->head); + break; + case NV3D_TEXHEAD_IN_B: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _Y_SOURCE, + _IN_B, tex->head); + break; + case NV3D_TEXHEAD_IN_ZERO: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _Y_SOURCE, + _IN_ZERO, tex->head); + break; + case NV3D_TEXHEAD_IN_ONE_FLOAT: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _Y_SOURCE, + _IN_ONE_FLOAT, tex->head); + break; + } + + switch (info.source.z) { + case NV3D_TEXHEAD_IN_A: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _Z_SOURCE, + _IN_A, tex->head); + break; + case NV3D_TEXHEAD_IN_R: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _Z_SOURCE, + _IN_R, tex->head); + break; + case NV3D_TEXHEAD_IN_G: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _Z_SOURCE, + _IN_G, tex->head); + break; + case NV3D_TEXHEAD_IN_B: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _Z_SOURCE, + _IN_B, tex->head); + break; + case NV3D_TEXHEAD_IN_ZERO: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _Z_SOURCE, + _IN_ZERO, tex->head); + break; + case NV3D_TEXHEAD_IN_ONE_FLOAT: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _Z_SOURCE, + _IN_ONE_FLOAT, tex->head); + break; + } + + switch (info.source.w) { + case NV3D_TEXHEAD_IN_A: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _W_SOURCE, + _IN_A, tex->head); + break; + case NV3D_TEXHEAD_IN_R: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _W_SOURCE, + _IN_R, tex->head); + break; + case NV3D_TEXHEAD_IN_G: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _W_SOURCE, + _IN_G, tex->head); + break; + case NV3D_TEXHEAD_IN_B: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _W_SOURCE, + _IN_B, tex->head); + break; + case NV3D_TEXHEAD_IN_ZERO: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _W_SOURCE, + _IN_ZERO, tex->head); + break; + case NV3D_TEXHEAD_IN_ONE_FLOAT: + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _W_SOURCE, + _IN_ONE_FLOAT, tex->head); + break; + } + + // Default to edge clamping. Our GPU seems to support wrapping + // even with non-normalized coordinates. + tex->samp[0] = + NV3D_C(C097, TEXSAMP0, ADDRESS_U, CLAMP_TO_EDGE) | + NV3D_C(C097, TEXSAMP0, ADDRESS_V, CLAMP_TO_EDGE) | + NV3D_C(C097, TEXSAMP0, ADDRESS_P, CLAMP_TO_EDGE); + + if (info.texType == NV3D_TEX_TYPE_ONE_D_BUFFER) { + FLD_SET_DRF_NUM_MW(C097, _TEXHEAD_1D, _ADDRESS_BITS31TO0, + NvU64_LO32(info.offset), tex->head); + + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_1D, _HEADER_VERSION, + _SELECT_ONE_D_BUFFER, tex->head); + FLD_SET_DRF_NUM_MW(C097_, TEXHEAD_1D_, ADDRESS_BITS48TO32, + NvU64_HI32(info.offset), tex->head); + + FLD_SET_DRF_NUM_MW(C097, _TEXHEAD_1D, _WIDTH_MINUS_ONE_BITS31TO16, + NvU32_HI16(info.width - 1), tex->head); + + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_1D, _TEXTURE_TYPE, + _ONE_D_BUFFER, tex->head); + FLD_SET_DRF_NUM_MW(C097, _TEXHEAD_1D, _WIDTH_MINUS_ONE_BITS15TO0, + NvU32_LO16(info.width - 1), tex->head); + } else if (info.texType == NV3D_TEX_TYPE_TWO_D_PITCH) { + FLD_SET_DRF_NUM_MW(C097, _TEXHEAD_PITCH, _ADDRESS_BITS31TO5, + info.offset >> 5, tex->head); + + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_PITCH, _HEADER_VERSION, + _SELECT_PITCH, tex->head); + FLD_SET_DRF_NUM_MW(C097, _TEXHEAD_PITCH, _ADDRESS_BITS48TO32, + NvU64_HI32(info.offset), tex->head); + + FLD_SET_DRF_NUM_MW(C097, _TEXHEAD_PITCH, _PITCH_BITS20TO5, + NvU32_LO16(info.pitch >> 5), tex->head); + FLD_SET_DRF_NUM_MW(C097, _TEXHEAD_PITCH, _PITCH_BIT21, + info.pitch >> 21, tex->head); + + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_PITCH, _TEXTURE_TYPE, + _TWO_D_NO_MIPMAP, tex->head); + FLD_SET_DRF_NUM_MW(C097, _TEXHEAD_PITCH, _WIDTH_MINUS_ONE, + info.width - 1, tex->head); + FLD_SET_DRF_NUM_MW(C097, _TEXHEAD_PITCH, _HEIGHT_MINUS_ONE_BIT16, + (info.height - 1) >> 16, tex->head); + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_PITCH, _BORDER_SIZE, + _BORDER_SAMPLER_COLOR, tex->head); + + FLD_SET_DRF_NUM_MW(C097, _TEXHEAD_PITCH, _HEIGHT_MINUS_ONE, + info.height - 1, tex->head); + FLD_SET_DRF_NUM_MW(C097, _TEXHEAD_PITCH, _DEPTH_MINUS_ONE, + 0, tex->head); + FLD_SET_DRF_NUM_MW(C097, _TEXHEAD_PITCH, _NORMALIZED_COORDS, + info.normalizedCoords, tex->head); + } else { + if (info.texType == NV3D_TEX_TYPE_ONE_D) { + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _TEXTURE_TYPE, + _ONE_D, tex->head); + } else if (info.texType == NV3D_TEX_TYPE_TWO_D_BLOCKLINEAR) { + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _TEXTURE_TYPE, + _TWO_D_NO_MIPMAP, tex->head); + } + FLD_SET_DRF_NUM_MW(C097, _TEXHEAD_BL, _ADDRESS_BITS31TO9, + info.offset >> 9, tex->head); + + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _HEADER_VERSION, + _SELECT_BLOCKLINEAR, tex->head); + FLD_SET_DRF_NUM_MW(C097, _TEXHEAD_BL, _ADDRESS_BITS48TO32, + NvU64_HI32(info.offset), tex->head); + + FLD_SET_DRF_NUM_MW(C097, _TEXHEAD_BL, _GOBS_PER_BLOCK_WIDTH, + info.log2GobsPerBlock.x, tex->head); + FLD_SET_DRF_NUM_MW(C097, _TEXHEAD_BL, _GOBS_PER_BLOCK_HEIGHT, + info.log2GobsPerBlock.y, tex->head); + FLD_SET_DRF_NUM_MW(C097, _TEXHEAD_BL, _GOBS_PER_BLOCK_DEPTH, + info.log2GobsPerBlock.z, tex->head); + + FLD_SET_DRF_NUM_MW(C097, _TEXHEAD_BL, _WIDTH_MINUS_ONE, + info.width - 1, tex->head); + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _BORDER_SIZE, + _BORDER_SAMPLER_COLOR, tex->head); + + FLD_SET_DRF_NUM_MW(C097, _TEXHEAD_BL, _HEIGHT_MINUS_ONE, + info.height - 1, tex->head); + FLD_SET_DRF_NUM_MW(C097, _TEXHEAD_BL, _HEIGHT_MINUS_ONE_BIT16, + (info.height - 1) >> 16, tex->head); + FLD_SET_DRF_NUM_MW(C097, _TEXHEAD_BL, _DEPTH_MINUS_ONE, + 0, tex->head); + FLD_SET_DRF_NUM_MW(C097, _TEXHEAD_BL, _DEPTH_MINUS_ONE_BIT14, + 0, tex->head); + FLD_SET_DRF_NUM_MW(C097, _TEXHEAD_BL, _NORMALIZED_COORDS, + info.normalizedCoords, tex->head); + } + + switch (info.repeatType) { + case NV3D_TEXHEAD_REPEAT_TYPE_NORMAL: + tex->samp[0] = NV3D_C(C097, TEXSAMP0, ADDRESS_U, WRAP) | + NV3D_C(C097, TEXSAMP0, ADDRESS_V, WRAP); + break; + case NV3D_TEXHEAD_REPEAT_TYPE_PAD: + tex->samp[0] = NV3D_C(C097, TEXSAMP0, ADDRESS_U, CLAMP_TO_EDGE) | + NV3D_C(C097, TEXSAMP0, ADDRESS_V, CLAMP_TO_EDGE); + break; + case NV3D_TEXHEAD_REPEAT_TYPE_REFLECT: + tex->samp[0] = NV3D_C(C097, TEXSAMP0, ADDRESS_U, MIRROR) | + NV3D_C(C097, TEXSAMP0, ADDRESS_V, MIRROR); + break; + case NV3D_TEXHEAD_REPEAT_TYPE_NONE: + tex->samp[0] = NV3D_C(C097, TEXSAMP0, ADDRESS_U, BORDER) | + NV3D_C(C097, TEXSAMP0, ADDRESS_V, BORDER); + break; + } + + switch (info.filtering) { + case NV3D_TEXHEAD_FILTER_TYPE_NEAREST: + tex->samp[1] = NV3D_C(C097, TEXSAMP1, MAG_FILTER, MAG_POINT) | + NV3D_C(C097, TEXSAMP1, MIN_FILTER, MIN_POINT) | + NV3D_C(C097, TEXSAMP1, MIP_FILTER, MIP_NONE); + break; + + case NV3D_TEXHEAD_FILTER_TYPE_LINEAR: + tex->samp[1] = NV3D_C(C097, TEXSAMP1, MAG_FILTER, MAG_LINEAR) | + NV3D_C(C097, TEXSAMP1, MIN_FILTER, MIN_LINEAR) | + NV3D_C(C097, TEXSAMP1, MIP_FILTER, MIP_NONE); + break; + + case NV3D_TEXHEAD_FILTER_TYPE_ANISO_2X: + tex->samp[0] |= NV3D_C(C097, TEXSAMP0, MAX_ANISOTROPY, ANISO_2_TO_1); + tex->samp[1] = NV3D_C(C097, TEXSAMP1, MAG_FILTER, MAG_LINEAR) | + NV3D_C(C097, TEXSAMP1, MIN_FILTER, MIN_ANISO) | + NV3D_C(C097, TEXSAMP1, MIP_FILTER, MIP_NONE); + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _MAX_ANISOTROPY, + _ANISO_2_TO_1, tex->head); + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _ANISO_FINE_SPREAD_MODIFIER, + _SPREAD_MODIFIER_CONST_TWO, tex->head); + + break; + + case NV3D_TEXHEAD_FILTER_TYPE_ANISO_4X: + tex->samp[0] |= NV3D_C(C097, TEXSAMP0, MAX_ANISOTROPY, ANISO_4_TO_1); + tex->samp[1] = NV3D_C(C097, TEXSAMP1, MAG_FILTER, MAG_LINEAR) | + NV3D_C(C097, TEXSAMP1, MIN_FILTER, MIN_ANISO) | + NV3D_C(C097, TEXSAMP1, MIP_FILTER, MIP_NONE); + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _MAX_ANISOTROPY, + _ANISO_4_TO_1, tex->head); + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _ANISO_FINE_SPREAD_MODIFIER, + _SPREAD_MODIFIER_CONST_TWO, tex->head); + break; + + case NV3D_TEXHEAD_FILTER_TYPE_ANISO_8X: + tex->samp[0] |= NV3D_C(C097, TEXSAMP0, MAX_ANISOTROPY, ANISO_8_TO_1); + tex->samp[1] = NV3D_C(C097, TEXSAMP1, MAG_FILTER, MAG_LINEAR) | + NV3D_C(C097, TEXSAMP1, MIN_FILTER, MIN_ANISO) | + NV3D_C(C097, TEXSAMP1, MIP_FILTER, MIP_NONE); + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _MAX_ANISOTROPY, + _ANISO_8_TO_1, tex->head); + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _ANISO_FINE_SPREAD_MODIFIER, + _SPREAD_MODIFIER_CONST_TWO, tex->head); + + break; + + case NV3D_TEXHEAD_FILTER_TYPE_ANISO_16X: + tex->samp[0] |= NV3D_C(C097, TEXSAMP0, MAX_ANISOTROPY, ANISO_16_TO_1); + tex->samp[1] = NV3D_C(C097, TEXSAMP1, MAG_FILTER, MAG_LINEAR) | + NV3D_C(C097, TEXSAMP1, MIN_FILTER, MIN_ANISO) | + NV3D_C(C097, TEXSAMP1, MIP_FILTER, MIP_NONE); + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _MAX_ANISOTROPY, + _ANISO_16_TO_1, tex->head); + FLD_SET_DRF_DEF_MW(C097, _TEXHEAD_BL, _ANISO_FINE_SPREAD_MODIFIER, + _SPREAD_MODIFIER_CONST_TWO, tex->head); + break; + + } +} diff --git a/src/common/unix/nvidia-3d/src/nvidia-3d-surface.c b/src/common/unix/nvidia-3d/src/nvidia-3d-surface.c new file mode 100644 index 000000000..da82945ac --- /dev/null +++ b/src/common/unix/nvidia-3d/src/nvidia-3d-surface.c @@ -0,0 +1,291 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvidia-3d.h" +#include "nvidia-3d-surface.h" +#include "nvidia-push-utils.h" /* nvPushIsAmodel() */ + +#include + +static void FreeSurface( + Nv3dChannelRec *p3dChannel) +{ + NvPushDevicePtr pPushDevice = p3dChannel->p3dDevice->pPushDevice; + int sd; + + for (sd = ARRAY_LEN(pPushDevice->subDevice) - 1; + sd >= 0; + sd--) { + if (p3dChannel->surface.handle[sd]) { + NvU32 ret = pPushDevice->pImports->rmApiFree( + pPushDevice, + pPushDevice->subDevice[sd].deviceHandle, + p3dChannel->surface.handle[sd]); + nvAssert(ret == NVOS_STATUS_SUCCESS); + (void)ret; + p3dChannel->surface.handle[sd] = 0; + } + } +} + +static NvBool AllocSurface( + Nv3dChannelRec *p3dChannel, + NvU64 size) +{ + NvPushDevicePtr pPushDevice = p3dChannel->p3dDevice->pPushDevice; + const NvPushImports *pImports = pPushDevice->pImports; + int sd; + + for (sd = 0; + sd < ARRAY_LEN(pPushDevice->subDevice) && + pPushDevice->subDevice[sd].deviceHandle != 0; + sd++) { + + NVOS32_PARAMETERS params = { + .hRoot = pPushDevice->clientHandle, + .hObjectParent = pPushDevice->subDevice[sd].deviceHandle, + .function = NVOS32_FUNCTION_ALLOC_SIZE, + .data.AllocSize.owner = pPushDevice->clientHandle, + .data.AllocSize.type = NVOS32_TYPE_SHADER_PROGRAM, + .data.AllocSize.size = size, + .data.AllocSize.attr = + DRF_DEF(OS32, _ATTR, _LOCATION, _VIDMEM) | + DRF_DEF(OS32, _ATTR, _PHYSICALITY, _ALLOW_NONCONTIGUOUS) | + DRF_DEF(OS32, _ATTR, _COHERENCY, _WRITE_COMBINE), + .data.AllocSize.attr2 = + DRF_DEF(OS32, _ATTR2, _GPU_CACHEABLE, _YES), + .data.AllocSize.flags = 0, + .data.AllocSize.alignment = 4096, + }; + + NvU32 ret = pImports->rmApiVidHeapControl(pPushDevice, ¶ms); + + if (ret != NVOS_STATUS_SUCCESS) { + FreeSurface(p3dChannel); + return FALSE; + } + + p3dChannel->surface.handle[sd] = params.data.AllocSize.hMemory; + } + + return TRUE; +} + +static void UnmapSurface( + const Nv3dChannelRec *p3dChannel, + NvU64 gpuAddress) +{ + NvPushDevicePtr pPushDevice = p3dChannel->p3dDevice->pPushDevice; + const NvPushImports *pImports = pPushDevice->pImports; + int sd; + + for (sd = ARRAY_LEN(p3dChannel->surface.handle) - 1; sd >= 0; sd--) { + if (p3dChannel->surface.handle[sd]) { + NvU32 ret = pImports->rmApiUnmapMemoryDma( + pPushDevice, + pPushDevice->subDevice[sd].deviceHandle, + pPushDevice->subDevice[sd].gpuVASpaceCtxDma, + p3dChannel->surface.handle[sd], + 0, + gpuAddress); + nvAssert(ret == NVOS_STATUS_SUCCESS); + (void)ret; + } + } +} + +static NvU64 MapSurface( + const Nv3dChannelRec *p3dChannel, + NvU64 size) +{ + NvPushDevicePtr pPushDevice = p3dChannel->p3dDevice->pPushDevice; + const NvPushImports *pImports = pPushDevice->pImports; + NvU64 gpuAddress = 0; + int sd; + + for (sd = 0; + sd < ARRAY_LEN(p3dChannel->surface.handle) && + p3dChannel->surface.handle[sd] != 0; + sd++) { + NvU32 flags = DRF_DEF(OS46, _FLAGS, _CACHE_SNOOP, _ENABLE); + NvU64 thisGpuAddress; + + if (sd == 0) { + /* For the first device, RM assigns a virtual address. */ + thisGpuAddress = 0; + } else { + /* For subsequent devices, use the same virtual address. */ + flags = FLD_SET_DRF(OS46, _FLAGS, _DMA_OFFSET_FIXED, _TRUE, flags); + nvAssert(gpuAddress != 0); + thisGpuAddress = gpuAddress; + } + + NvU32 ret = pImports->rmApiMapMemoryDma(pPushDevice, + pPushDevice->subDevice[sd].deviceHandle, + pPushDevice->subDevice[sd].gpuVASpaceCtxDma, + p3dChannel->surface.handle[sd], + 0, + size, + flags, + &thisGpuAddress); + if (ret != NVOS_STATUS_SUCCESS) { + if (sd != 0) { + /* Clean up earlier successful mappings */ + UnmapSurface(p3dChannel, gpuAddress); + } + return 0; + } + + if (sd == 0) { + gpuAddress = thisGpuAddress; + } else { + nvAssert(gpuAddress == thisGpuAddress); + } + } + + return gpuAddress; +} + +NvBool nv3dAllocChannelSurface(Nv3dChannelPtr p3dChannel) +{ + const NvU64 size = p3dChannel->surface.totalSize; + NvU64 gpuAddress; + + if (!AllocSurface(p3dChannel, size)) { + return FALSE; + } + + gpuAddress = MapSurface(p3dChannel, size); + + if (gpuAddress == 0) { + FreeSurface(p3dChannel); + return FALSE; + } + + p3dChannel->surface.gpuAddress = gpuAddress; + + return TRUE; +} + +void nv3dFreeChannelSurface(Nv3dChannelPtr p3dChannel) +{ + + if (p3dChannel->surface.gpuAddress != 0) { + /* + * If the surface is mapped into our channel, we need to ensure + * that any methods in the channel that might reference the + * gpuAddress have idled before we unmap the address. + */ + nvPushIdleChannel(p3dChannel->pPushChannel); + + UnmapSurface(p3dChannel, + p3dChannel->surface.gpuAddress); + p3dChannel->surface.gpuAddress = 0; + } + + FreeSurface(p3dChannel); +} + +/* + * The Nv3dChannelRec's surface contains: + * + * programLocalMemory + * programCode + * programConstants + * Nv3dTexture[numTextures] + * bindlessTextureConstantBuffer (optionally) + * Nv3dConstantBuffer[numConstantBuffers] + * vertexStreams + * + * Where all items are aligned to NV3D_TEXTURE_PITCH_ALIGNMENT. + * + * Compute all the offsets into the surface, and the total surface + * size. + * + * XXX TODO: use correct alignment for all items, rather than + * NV3D_TEXTURE_PITCH_ALIGNMENT. + */ +void _nv3dAssignSurfaceOffsets( + const Nv3dAllocChannelStateParams *pParams, + Nv3dChannelPtr p3dChannel) +{ + const NvU32 programPrefetchPadding = 2048; + + NvU64 offset = 0; + enum Nv3dVertexAttributeStreamType stream; + + /* + * Program local memory requires at least 4k alignment. So, place + * it at the start of the surface. + */ + p3dChannel->surface.programLocalMemoryOffset = offset; + + offset += p3dChannel->programLocalMemorySize; + offset = NV_ALIGN_UP(offset, NV3D_TEXTURE_PITCH_ALIGNMENT); + + p3dChannel->surface.programOffset = offset; + + offset += p3dChannel->programs.code.decompressedSize; + offset = NV_ALIGN_UP(offset, NV3D_TEXTURE_PITCH_ALIGNMENT); + + p3dChannel->surface.programConstantsOffset = offset; + + offset += p3dChannel->programs.constants.size; + offset = NV_ALIGN_UP(offset, NV3D_TEXTURE_PITCH_ALIGNMENT); + + p3dChannel->surface.textureOffset = offset; + + offset += (sizeof(Nv3dTexture) * pParams->numTextures); + offset = NV_ALIGN_UP(offset, NV3D_TEXTURE_PITCH_ALIGNMENT); + + p3dChannel->surface.bindlessTextureConstantBufferOffset = offset; + offset += NV3D_CONSTANT_BUFFER_SIZE; + offset = NV_ALIGN_UP(offset, NV3D_TEXTURE_PITCH_ALIGNMENT); + + p3dChannel->surface.constantBufferOffset = offset; + + offset += (NV3D_CONSTANT_BUFFER_SIZE * pParams->numConstantBuffers); + offset = NV_ALIGN_UP(offset, NV3D_TEXTURE_PITCH_ALIGNMENT); + + /* + * TODO: not all nvidia-3d host drivers will require the vertex stream + * memory; maybe host drivers should opt in? + */ + for (stream = NV3D_VERTEX_ATTRIBUTE_STREAM_FIRST; + stream < NV3D_VERTEX_ATTRIBUTE_STREAM_COUNT; + stream++) { + + p3dChannel->surface.vertexStreamOffset[stream] = offset; + + offset += NV3D_VERTEX_ATTRIBUTE_STREAM_SIZE; + offset = NV_ALIGN_UP(offset, NV3D_TEXTURE_PITCH_ALIGNMENT); + } + + /* + * Make sure the total surface size is large enough to cover any + * potential prefetch region. + */ + p3dChannel->surface.totalSize = + NV_MAX(p3dChannel->surface.programOffset + programPrefetchPadding, + offset); +} diff --git a/src/common/unix/nvidia-3d/src/nvidia-3d-turing.c b/src/common/unix/nvidia-3d/src/nvidia-3d-turing.c new file mode 100644 index 000000000..71c3938a3 --- /dev/null +++ b/src/common/unix/nvidia-3d/src/nvidia-3d-turing.c @@ -0,0 +1,56 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvidia-3d-turing.h" +#include "nvidia-3d-pascal.h" +#include "nvidia-3d.h" + +#include "class/clc597.h" +#include + +void _nv3dInitChannelTuring(Nv3dChannelRec *p3dChannel) +{ + NvPushChannelPtr p = p3dChannel->pPushChannel; + + _nv3dInitChannelPascal(p3dChannel); + + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, NVC597_SET_SPH_VERSION, 2); + nvPushSetMethodData(p, + NV3D_V(C597, SET_SPH_VERSION, CURRENT, 4) | + NV3D_V(C597, SET_SPH_VERSION, OLDEST_SUPPORTED, 4)); + nvPushSetMethodData(p, + NV3D_V(C597, CHECK_SPH_VERSION, CURRENT, 4) | + NV3D_V(C597, CHECK_SPH_VERSION, OLDEST_SUPPORTED, 4)); +} + +void _nv3dSetVertexStreamEndTuring( + Nv3dChannelPtr p3dChannel, + enum Nv3dVertexAttributeStreamType stream, + const Nv3dVertexAttributeStreamRec *pStream) +{ + NvPushChannelPtr p = p3dChannel->pPushChannel; + + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, + NVC597_SET_VERTEX_STREAM_SIZE_A(stream), 2); + nvPushSetMethodDataU64(p, pStream->end - pStream->current); +} diff --git a/src/common/unix/nvidia-3d/src/nvidia-3d-vertex-arrays.c b/src/common/unix/nvidia-3d/src/nvidia-3d-vertex-arrays.c new file mode 100644 index 000000000..4a6991156 --- /dev/null +++ b/src/common/unix/nvidia-3d/src/nvidia-3d-vertex-arrays.c @@ -0,0 +1,531 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvidia-3d.h" +#include "nvidia-3d-vertex-arrays.h" +#include "nvidia-3d-types-priv.h" +#include "nvidia-3d-constant-buffers.h" +#include "nvidia-3d-utils.h" + +#include +#include + +static void InitializeStreamFromSurf( + const Nv3dStreamSurfaceRec *pSurf, + Nv3dVertexAttributeStreamRec *pStream) +{ + pStream->current = pSurf->gpuAddress; + pStream->end = pSurf->gpuAddress + pSurf->size; + pStream->stride = 0; + pStream->nextLaunch = 0; +} + +static void InitializeStream( + Nv3dChannelRec *p3dChannel, + enum Nv3dVertexAttributeStreamType stream, + Nv3dVertexAttributeStreamRec *pStream) +{ + const Nv3dStreamSurfaceRec tmpSurf = { + .gpuAddress = + nv3dGetVertexAttributestreamGpuAddress(p3dChannel, stream), + .size = NV3D_VERTEX_ATTRIBUTE_STREAM_SIZE, + }; + InitializeStreamFromSurf(&tmpSurf, pStream); +} + +void _nv3dInitializeStreams( + Nv3dChannelRec *p3dChannel) +{ + enum Nv3dVertexAttributeStreamType stream; + NvPushChannelPtr p = p3dChannel->pPushChannel; + + // Disable vertex attribute vectors 16 through 31 (scalars 64 through 127). + // We don't use them. + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, + NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_B(0), 2); + nvPushSetMethodData(p, ~0); + nvPushSetMethodData(p, ~0); + + for (stream = NV3D_VERTEX_ATTRIBUTE_STREAM_FIRST; + stream < NV3D_VERTEX_ATTRIBUTE_STREAM_COUNT; + stream++) { + + Nv3dVertexAttributeStreamRec *pStream = + &p3dChannel->vertexStreams[stream]; + + InitializeStream(p3dChannel, stream, pStream); + } +} + +static void AdvanceStream( + Nv3dVertexAttributeStreamRec *pStream) +{ + pStream->current += pStream->stride * pStream->nextLaunch; + nvAssert(pStream->current <= pStream->end); + pStream->nextLaunch = 0; +} + +/*! + * Configure a vertex attribute stream to fetch from a surface. + * + * \param[in] p3dChannel The channel + * \param[in] stream The vertex attribute stream + * \param[in] pStream The vertex attribute stream tracking structure + */ +static void +SetVertexStreamSurface( + Nv3dChannelRec *p3dChannel, + enum Nv3dVertexAttributeStreamType stream, + const Nv3dVertexAttributeStreamRec *pStream) +{ + const Nv3dHal *pHal = p3dChannel->p3dDevice->hal; + NvPushChannelPtr p = p3dChannel->pPushChannel; + + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, + NV9097_SET_VERTEX_STREAM_A_FORMAT(stream), 3); + nvPushSetMethodData(p, + NV3D_V(9097, SET_VERTEX_STREAM_A_FORMAT, STRIDE, pStream->stride) | + NV3D_C(9097, SET_VERTEX_STREAM_A_FORMAT, ENABLE, TRUE)); + nvPushSetMethodDataU64(p, pStream->current); + + pHal->setVertexStreamEnd(p3dChannel, stream, pStream); +} + +/*! + * Reset a vertex attribute stream to the specified offset, while leaving its + * stride and limit alone. + */ +static void +SetVertexStreamOffset( + Nv3dChannelRec *p3dChannel, + enum Nv3dVertexAttributeStreamType stream, + NvU64 offset) +{ + const Nv3dHal *pHal = p3dChannel->p3dDevice->hal; + NvPushChannelPtr p = p3dChannel->pPushChannel; + Nv3dVertexAttributeStreamRec *pStream = &p3dChannel->vertexStreams[stream]; + + pStream->current = offset; + pStream->nextLaunch = 0; + + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, + NV9097_SET_VERTEX_STREAM_A_LOCATION_A(stream), 2); + nvPushSetMethodDataU64(p, offset); + + pHal->setVertexStreamEnd(p3dChannel, stream, pStream); +} + +/*! + * Point the constant buffer selector at the next location for data in the + * given stream. + */ +static void SelectCbForStream( + Nv3dChannelRec *p3dChannel, + enum Nv3dVertexAttributeStreamType stream) +{ + Nv3dVertexAttributeStreamRec *pStream = &p3dChannel->vertexStreams[stream]; + const NvU64 gpuAddress = + nv3dGetVertexAttributestreamGpuAddress(p3dChannel, stream); + int startOffset = pStream->current + pStream->stride * pStream->nextLaunch - + gpuAddress; + + nv3dSelectCbAddress(p3dChannel, gpuAddress, + NV3D_VERTEX_ATTRIBUTE_STREAM_SIZE); + nv3dSetConstantBufferOffset(p3dChannel, startOffset); +} + +/*! + * Configure the DA and VAF to fetch from vertex attribute streams. + * + * This function configures the Data Assembler (DA) and Vertex Attribute Fetch + * (VAF) units to fetch vertex attributes from pSurf using a format configured + * by the 'attribs' array. + * + * It configures two streams: NV3D_VERTEX_ATTRIBUTE_STREAM_STATIC and + * NV3D_VERTEX_ATTRIBUTE_STREAM_DYNAMIC. The static stream contains attributes + * that are the same across all vertices. The dynamic stream contains + * attributes that are different for each vertex. The static stream sources + * from the next available location in the static vertex data surface and uses a + * stride of 0, so that all vertices in an array fetch the same values for those + * attributes. Then, it configures the dynamic stream to fetch starting at + * offset 0 of pSurf, unless pSurf is NULL in which case it starts at the + * appropriate offset in the dynamic vertex data surface. + * + * The 'attribs' array stores Nv3dVertexAttributeInfoRecs, terminated with an + * element where attributeType is NV3D_VERTEX_ATTRIBUTE_END. Each element + * contains: + * + * (a) An enum Nv3dVertexAttributeType indicating which vertex attribute this + * array element describes. + * + * (b) An enum Nv3dVertexAttributeDataType indicating the data type to use for + * the attribute. + * + * (c) An enum Nv3dVertexAttributeStreamType indicating which stream should use + * the attribute. + * + * If any attributes are enabled as static, this function selects the static + * stream surface as the current constant buffer. The caller should push the + * appropriate vertex data. + * + * Note that if you launch rendering using vertex attributes from a surface, you + * must wait for idle before changing those attributes later. Otherwise, the + * VAF unit may fetch the new data instead of the old data, causing corruption. + * + * \param[in] p3dChannel The 3d channel to program + * \param[in] attribs Description of vertex attributes (see above) + * \param[in] pSurf Surface that dynamic attributes will be fetched from + * + * \return The size in bytes of the static attribute data + */ +int nv3dVasSetup( + Nv3dChannelRec *p3dChannel, + const Nv3dVertexAttributeInfoRec *attribs, + const Nv3dStreamSurfaceRec *pSurf) +{ + /* This table is indexed by enum Nv3dVertexAttributeDataType. */ + static const struct { + NvU32 size; + NvU32 setVertexAttributeA; + } attribTypeTable[] = { + + [NV3D_VERTEX_ATTRIBUTE_DATA_TYPE_2_32_FLOAT] = { + sizeof(float) * 2, + NV3D_C(9097, SET_VERTEX_ATTRIBUTE_A, + COMPONENT_BIT_WIDTHS, R32_G32) | + NV3D_C(9097, SET_VERTEX_ATTRIBUTE_A, NUMERICAL_TYPE, NUM_FLOAT), + }, + + [NV3D_VERTEX_ATTRIBUTE_DATA_TYPE_4_32_FLOAT] = { + sizeof(float) * 4, + NV3D_C(9097, SET_VERTEX_ATTRIBUTE_A, + COMPONENT_BIT_WIDTHS, R32_G32_B32_A32) | + NV3D_C(9097, SET_VERTEX_ATTRIBUTE_A, NUMERICAL_TYPE, NUM_FLOAT), + }, + + [NV3D_VERTEX_ATTRIBUTE_DATA_TYPE_4_16_UNORM] = { + sizeof(NvU16) * 4, + NV3D_C(9097, SET_VERTEX_ATTRIBUTE_A, + COMPONENT_BIT_WIDTHS, R16_G16_B16_A16) | + NV3D_C(9097, SET_VERTEX_ATTRIBUTE_A, NUMERICAL_TYPE, NUM_UNORM), + }, + + [NV3D_VERTEX_ATTRIBUTE_DATA_TYPE_4_8_UNORM] = { + sizeof(NvU8) * 4, + NV3D_C(9097, SET_VERTEX_ATTRIBUTE_A, + COMPONENT_BIT_WIDTHS, A8B8G8R8) | + NV3D_C(9097, SET_VERTEX_ATTRIBUTE_A, NUMERICAL_TYPE, NUM_UNORM), + }, + + [NV3D_VERTEX_ATTRIBUTE_DATA_TYPE_2_16_SSCALED] = { + sizeof(NvU32), + NV3D_C(9097, SET_VERTEX_ATTRIBUTE_A, + COMPONENT_BIT_WIDTHS, R16_G16) | + NV3D_C(9097, SET_VERTEX_ATTRIBUTE_A, NUMERICAL_TYPE, NUM_SSCALED), + }, + + }; + + NvPushChannelPtr p = p3dChannel->pPushChannel; + Nv3dVertexAttributeStreamRec *pStatic = + &p3dChannel->vertexStreams[NV3D_VERTEX_ATTRIBUTE_STREAM_STATIC]; + Nv3dVertexAttributeStreamRec *pDynamic = + &p3dChannel->vertexStreams[NV3D_VERTEX_ATTRIBUTE_STREAM_DYNAMIC]; + int staticOffset = 0, dynamicOffset = 0; + Nv3dVertexAttributeStreamRec tmpStreamRec; + NvU32 stride = 0; + NvU64 daEnableMask = 0, daSkipMask; + NvBool hasStaticAttribs = FALSE; + NvBool hasPositionAttrib = FALSE; + int i; + + // POSITION must be specified and must be a dynamic attribute. + for (i = 0; attribs[i].attributeType != NV3D_VERTEX_ATTRIBUTE_END; i++) { + if (attribs[i].attributeType != NV3D_VERTEX_ATTRIBUTE_POSITION) { + continue; + } + hasPositionAttrib = TRUE; + nvAssert(attribs[i].streamType == NV3D_VERTEX_ATTRIBUTE_STREAM_DYNAMIC); + } + if (!hasPositionAttrib) { + nvAssert(!"POSITION vertex attribute not specified."); + } + + // Configure the DA output skip mask so that it only fetches attributes for + // enabled streams. + for (i = 0; attribs[i].attributeType != NV3D_VERTEX_ATTRIBUTE_END; i++) { + const enum Nv3dVertexAttributeType attrib = attribs[i].attributeType; + // Always enable all four components of the value. This causes the + // DA to generate default values if there are not enough components + // in the pulled vertex data. This sets W=1 if W is missing. + // + // Otherwise, the value would come from the default the hardware + // generates as input to the vertex shader when that attribute is + // skipped in the DA, which is specified in the .mfs file as, "a + // default value is inserted". + // + // Note all attribute values are expected to be less than 16 (i.e., fit + // in MASK_A; attributes 16 through 31 would go in MASK_B). + nvAssert(attrib < 16); + daEnableMask |= 0xfULL << (4 * attrib); + } + daSkipMask = ~daEnableMask; + + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, + NV9097_SET_DA_OUTPUT_ATTRIBUTE_SKIP_MASK_A(0), 2); + nvPushSetMethodData(p, NvU64_LO32(daSkipMask)); + nvPushSetMethodData(p, NvU64_HI32(daSkipMask)); + + // Configure the attributes to fetch from the streams. + for (i = 0; attribs[i].attributeType != NV3D_VERTEX_ATTRIBUTE_END; i++) { + + const enum Nv3dVertexAttributeType attrib = attribs[i].attributeType; + const enum Nv3dVertexAttributeDataType dataType = attribs[i].dataType; + const enum Nv3dVertexAttributeStreamType stream = attribs[i].streamType; + const NvU32 size = attribTypeTable[dataType].size; + const NvU32 setVertexAttributeA = + attribTypeTable[dataType].setVertexAttributeA; + + int offset; + + if (stream == NV3D_VERTEX_ATTRIBUTE_STREAM_STATIC) { + offset = staticOffset; + staticOffset += size; + hasStaticAttribs = TRUE; + } else { + nvAssert(stream == NV3D_VERTEX_ATTRIBUTE_STREAM_DYNAMIC); + offset = dynamicOffset; + dynamicOffset += size; + stride += size; + } + + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, + NV9097_SET_VERTEX_ATTRIBUTE_A(attrib), 1); + nvPushSetMethodData(p, + NV3D_V(9097, SET_VERTEX_ATTRIBUTE_A, STREAM, stream) | + NV3D_C(9097, SET_VERTEX_ATTRIBUTE_A, SOURCE, ACTIVE) | + NV3D_V(9097, SET_VERTEX_ATTRIBUTE_A, OFFSET, offset) | + setVertexAttributeA); + } + + + // Advance the stream past any attribs used previously. + AdvanceStream(pStatic); + // Although we may have set a non-zero stride on a previous call to this + // function (mostly so the bookkeeping above works out), as far as the GPU + // is concerned we should program a stride of 0. + pStatic->stride = 0; + + // See if we need to wrap the static stream. + if (pStatic->current + staticOffset >= pStatic->end) { + nvPushImmedVal(p, NVA06F_SUBCHANNEL_3D, NV9097_WAIT_FOR_IDLE, 0); + + // Reset both the static and dynamic streams, since we know the GPU is + // done reading from both. + InitializeStream(p3dChannel, + NV3D_VERTEX_ATTRIBUTE_STREAM_STATIC, pStatic); + InitializeStream(p3dChannel, + NV3D_VERTEX_ATTRIBUTE_STREAM_DYNAMIC, pDynamic); + } else if (!pSurf) { + // Advance the dynamic stream past any attribs used previously (unless + // we just reset the stream). + AdvanceStream(pDynamic); + } + + /* override dynamic stream with pSurf */ + if (pSurf) { + pDynamic = &tmpStreamRec; + InitializeStreamFromSurf(pSurf, pDynamic); + } + + // Configure the streams. A stride of 0 makes it read the same attribute + // each time. + nvAssert(pStatic->stride == 0); + SetVertexStreamSurface(p3dChannel, + NV3D_VERTEX_ATTRIBUTE_STREAM_STATIC, + pStatic); + nvAssert(stride != 0); + pDynamic->stride = stride; + SetVertexStreamSurface(p3dChannel, + NV3D_VERTEX_ATTRIBUTE_STREAM_DYNAMIC, + pDynamic); + + // If there are static attributes, set up the constant buffer selector. + if (hasStaticAttribs) { + SelectCbForStream(p3dChannel, NV3D_VERTEX_ATTRIBUTE_STREAM_STATIC); + + // Override the static stream's "stride" so that the next time this + // function is called it will set staticStartOffset to right after the + // static data here. + pStatic->stride = staticOffset; + pStatic->nextLaunch = 1; + } + + return staticOffset; +} + +/*! + * Check if uploading the specified number of vertices will write past the end + * of the given vertex stream. + */ +static NvBool WillVertexDataWrap( + Nv3dVertexAttributeStreamRec *pStream, + int n) +{ + // >= here is intentional: It's illegal to set the constant buffer selector + // past the end of the constant buffer, which could happen if the last + // primitive drawn exactly fills the dynamic data stream and another + // primitive is drawn. Then the next call to nv3dVasSelectCbForVertexData() + // would cause a channel error. + // + // Instead of trying to detect that case there, just disallow completely + // filling the stream so it wraps slightly earlier. + return pStream->current + pStream->stride * (pStream->nextLaunch + n) >= + pStream->end; +} + +/*! + * Launch vertices and update tracked vertex array state. + */ +static void DrawVertexArray(Nv3dChannelRec *p3dChannel, int numVerts) +{ + NvPushChannelPtr p = p3dChannel->pPushChannel; + Nv3dVertexAttributeStreamRec *pDynamic = + &p3dChannel->vertexStreams[NV3D_VERTEX_ATTRIBUTE_STREAM_DYNAMIC]; + + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, NV9097_SET_VERTEX_ARRAY_START, 2); + nvPushSetMethodData(p, pDynamic->nextLaunch); + nvPushSetMethodData(p, numVerts); // NV9097_DRAW_VERTEX_ARRAY + + pDynamic->nextLaunch += numVerts; +} + +/*! + * Reset both the static and dynamic vertex array streams to the base of the + * corresponding surfaces. + */ +static void WrapVertexStreams(Nv3dChannelRec *p3dChannel) +{ + NvPushChannelPtr p = p3dChannel->pPushChannel; + Nv3dVertexAttributeStreamRec *pStatic = + &p3dChannel->vertexStreams[NV3D_VERTEX_ATTRIBUTE_STREAM_STATIC]; + const NvU64 gpuAddress = + nv3dGetVertexAttributestreamGpuAddress(p3dChannel, + NV3D_VERTEX_ATTRIBUTE_STREAM_DYNAMIC); + const NvU32 primMode = p3dChannel->currentPrimitiveMode; + + // Set the software tracking for the static stream so it starts over at the + // beginning next time nv3dVasSetup() is called, but leave the hardware + // configured to read the data that's already there, in case vertices + // submitted later still need it. + pStatic->current = pStatic->end; + pStatic->nextLaunch = 0; + + // The hardware can't handle changing the vertex stream offset inside a + // BEGIN / END block, so temporarily end now. + nv3dVasEnd(p3dChannel); + + // Wrap the dynamic vertex stream. + nvPushImmedVal(p, NVA06F_SUBCHANNEL_3D, NV9097_WAIT_FOR_IDLE, 0); + SetVertexStreamOffset(p3dChannel, NV3D_VERTEX_ATTRIBUTE_STREAM_DYNAMIC, + gpuAddress); + + nv3dVasBegin(p3dChannel, primMode); +} + +/*! + * Point the constant buffer selector at the next location for vertex data in + * the dynamic data surface. + */ +void nv3dVasSelectCbForVertexData(Nv3dChannelRec *p3dChannel) +{ + SelectCbForStream(p3dChannel, NV3D_VERTEX_ATTRIBUTE_STREAM_DYNAMIC); +} + +/*! + * Upload and draw vertices using the dynamic vertex data surface + * + * This function uploads data to the dynamic vertex attribute stream surface + * using inline constant buffer updates starting at the next free space in that + * surface, and then launches rendering. The number of vertices rendered is + * specified by 'numVerts'. + * + * Static data should have already been written to the static vertex attribute + * stream surface by the caller. + * + * If not enough space is available in the dynamic data surface, this function + * waits for idle before wrapping to the beginning of the surface to avoid + * conflicting with earlier rendering that might be in flight. + * + * It is up to the caller to send BEGIN and END methods around calls to this + * function. + * + * \param[in] p3dChannel The channel + * \param[in] data Data to upload + * \param[in] numVerts Number of vertices rendered + */ +void nv3dVasDrawInlineVerts( + Nv3dChannelRec *p3dChannel, + const void *data, + int numVerts) +{ + if (data != NULL) { + Nv3dVertexAttributeStreamRec *pDynamic = + &p3dChannel->vertexStreams[NV3D_VERTEX_ATTRIBUTE_STREAM_DYNAMIC]; + + // See if we need to wrap the dynamic stream. + if (WillVertexDataWrap(pDynamic, numVerts)) { + WrapVertexStreams(p3dChannel); + } + + nv3dVasSelectCbForVertexData(p3dChannel); + nv3dPushConstants(p3dChannel, pDynamic->stride * numVerts, data); + } + + DrawVertexArray(p3dChannel, numVerts); +} + +NvBool nv3dVasMakeRoom( + Nv3dChannelRec *p3dChannel, + NvU32 pendingVerts, + NvU32 moreVerts) +{ + Nv3dVertexAttributeStreamRec *pDynamic = + &p3dChannel->vertexStreams[NV3D_VERTEX_ATTRIBUTE_STREAM_DYNAMIC]; + + const NvBool wrap = WillVertexDataWrap(pDynamic, pendingVerts + moreVerts); + + // If pendingVerts + moreVerts would exceed the dynamic vertex array buffer, + // flush it now and start over at the beginning. + if (wrap) { + DrawVertexArray(p3dChannel, pendingVerts); + WrapVertexStreams(p3dChannel); + + // Reset the constant buffer update pointer to the beginning of the + // dynamic vertex data buffer. + nv3dSetConstantBufferOffset(p3dChannel, 0); + } + + return wrap; +} + diff --git a/src/common/unix/nvidia-3d/src/nvidia-3d-volta.c b/src/common/unix/nvidia-3d/src/nvidia-3d-volta.c new file mode 100644 index 000000000..4eb1106f9 --- /dev/null +++ b/src/common/unix/nvidia-3d/src/nvidia-3d-volta.c @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvidia-3d-volta.h" +#include "nvidia-3d.h" + +#include "class/clc397.h" +#include + +void _nv3dSetProgramOffsetVolta( + Nv3dChannelRec *p3dChannel, + NvU32 stage, + NvU32 offset) +{ + NvPushChannelPtr p = p3dChannel->pPushChannel; + const NvU64 gpuAddress = nv3dGetProgramGpuAddress(p3dChannel) + offset; + + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, + NVC397_SET_PIPELINE_PROGRAM_ADDRESS_A(stage), 2); + nvPushSetMethodDataU64(p, gpuAddress); +} diff --git a/src/common/unix/nvidia-headsurface/nvidia-headsurface-constants.h b/src/common/unix/nvidia-headsurface/nvidia-headsurface-constants.h new file mode 100644 index 000000000..48fd49a2d --- /dev/null +++ b/src/common/unix/nvidia-headsurface/nvidia-headsurface-constants.h @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _NVIDIA_HEADSURFACE_CONSTANTS_H_ +#define _NVIDIA_HEADSURFACE_CONSTANTS_H_ + +/* Possible values for NvHsFragmentUniforms::resamplingMethod */ +#define NVIDIA_HEADSURFACE_RESAMPLING_METHOD_BICUBIC_TRIANGULAR 1 +#define NVIDIA_HEADSURFACE_RESAMPLING_METHOD_BICUBIC_BELL_SHAPED 2 +#define NVIDIA_HEADSURFACE_RESAMPLING_METHOD_BICUBIC_BSPLINE 3 +#define NVIDIA_HEADSURFACE_RESAMPLING_METHOD_BICUBIC_ADAPTIVE_TRIANGULAR 4 +#define NVIDIA_HEADSURFACE_RESAMPLING_METHOD_BICUBIC_ADAPTIVE_BELL_SHAPED 5 +#define NVIDIA_HEADSURFACE_RESAMPLING_METHOD_BICUBIC_ADAPTIVE_BSPLINE 6 + +/* Uniform sampler binding indices */ +#define NVIDIA_HEADSURFACE_UNIFORM_SAMPLER_BINDING_PRIMARY_TEX 0 +#define NVIDIA_HEADSURFACE_UNIFORM_SAMPLER_BINDING_CURSOR_TEX 1 +#define NVIDIA_HEADSURFACE_UNIFORM_SAMPLER_BINDING_BLEND_TEX 2 +#define NVIDIA_HEADSURFACE_UNIFORM_SAMPLER_BINDING_OFFSET_TEX 3 +#define NVIDIA_HEADSURFACE_UNIFORM_SAMPLER_BINDING_OVERLAY_TEX 4 +#define NVIDIA_HEADSURFACE_UNIFORM_SAMPLER_BINDING_LUT_TEX 5 +#define NVIDIA_HEADSURFACE_UNIFORM_SAMPLER_BINDING_NUM 6 + +#endif /* _NVIDIA_HEADSURFACE_CONSTANTS_H_ */ diff --git a/src/common/unix/nvidia-headsurface/nvidia-headsurface-types.h b/src/common/unix/nvidia-headsurface/nvidia-headsurface-types.h new file mode 100644 index 000000000..1e643d244 --- /dev/null +++ b/src/common/unix/nvidia-headsurface/nvidia-headsurface-types.h @@ -0,0 +1,67 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVIDIA_HEADSURFACE_TYPES_H__ +#define __NVIDIA_HEADSURFACE_TYPES_H__ + +#include "nvtypes.h" +#include "nvidia-3d-types.h" + +typedef struct _NvHsVertexUniforms { + Nv3dVertexAttrib2U vertexScale; + Nv3dVertexAttrib2U primaryTextureScale; + Nv3dVertexAttrib2U primaryTextureBias; + Nv3dVertexAttrib2S cursorPosition; +} __attribute__((packed)) NvHsVertexUniforms; + +typedef struct _NvHsFragmentUniforms { // Byte offsets + Nv3dVertexAttrib2U vertexScale; // 0 + Nv3dVertexAttrib3U numLutEntries NV_ALIGN_BYTES(16); // 16 + Nv3dVertexAttrib2U primaryTextureBias NV_ALIGN_BYTES(8); // 32 + Nv3dVertexAttrib2S cursorPosition; // 40 + // Although this is really a 3x3 matrix, GLSL std140 uniform block + // layout says that the column stride is equal to a vec4. + Nv3dFloat transform[3][4]; // 48 + Nv3dVertexAttrib2F pixelShiftOffset; // 96 + Nv3dVertexAttrib3F luminanceCoefficient NV_ALIGN_BYTES(16); // 112 + Nv3dVertexAttrib2F chromaCoefficient NV_ALIGN_BYTES(8); // 128 + Nv3dFloat luminanceScale; // 136 + Nv3dFloat luminanceBlackLevel; // 140 + Nv3dFloat chrominanceScale; // 144 + Nv3dFloat chrominanceBlackLevel; // 148 + NvU32 useSatHue; // 152 + Nv3dFloat satCos; // 156 + int resamplingMethod; // 160 +} __attribute__((packed)) NvHsFragmentUniforms; + +/* + * The static warp mesh consists of four vertices, each vertex has six + * components: (XY, UVRQ). + */ +typedef struct { + struct { + Nv3dFloat x, y, u, v, r, q; + } vertex[4]; +} NvHsStaticWarpMesh; + +#endif /* __NVIDIA_HEADSURFACE_TYPES_H__ */ diff --git a/src/common/unix/nvidia-push/include/nvidia-push-priv-imports.h b/src/common/unix/nvidia-push/include/nvidia-push-priv-imports.h new file mode 100644 index 000000000..587c75309 --- /dev/null +++ b/src/common/unix/nvidia-push/include/nvidia-push-priv-imports.h @@ -0,0 +1,203 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#if !defined(__NVIDIA_PUSH_PRIV_IMPORTS_H__) +#define __NVIDIA_PUSH_PRIV_IMPORTS_H__ + +#include "nvidia-push-types.h" + +static inline NvU32 nvPushImportRmApiControl( + NvPushDevicePtr pDevice, + NvU32 hObject, + NvU32 cmd, + void *pParams, + NvU32 paramsSize) +{ + return pDevice->pImports->rmApiControl(pDevice, hObject, cmd, + pParams, paramsSize); +} + +static inline NvU32 nvPushImportRmApiAlloc( + NvPushDevicePtr pDevice, + NvU32 hParent, + NvU32 hObject, + NvU32 hClass, + void *pAllocParams) +{ + + return pDevice->pImports->rmApiAlloc(pDevice, hParent, hObject, hClass, + pAllocParams); +} + +static inline NvU32 nvPushImportRmApiFree( + NvPushDevicePtr pDevice, + NvU32 hParent, + NvU32 hObject) +{ + return pDevice->pImports->rmApiFree(pDevice, hParent, hObject); +} + +static inline NvU32 nvPushImportRmApiMapMemoryDma( + NvPushDevicePtr pDevice, + NvU32 hDevice, + NvU32 hDma, + NvU32 hMemory, + NvU64 offset, + NvU64 length, + NvU32 flags, + NvU64 *pDmaOffset) +{ + return pDevice->pImports->rmApiMapMemoryDma(pDevice, + hDevice, + hDma, + hMemory, + offset, + length, + flags, + pDmaOffset); +} + +static inline NvU32 nvPushImportRmApiUnmapMemoryDma( + NvPushDevicePtr pDevice, + NvU32 hDevice, + NvU32 hDma, + NvU32 hMemory, + NvU32 flags, + NvU64 dmaOffset) +{ + return pDevice->pImports->rmApiUnmapMemoryDma(pDevice, + hDevice, + hDma, + hMemory, + flags, + dmaOffset); + +} + +static inline NvU32 nvPushImportRmApiAllocMemory64( + NvPushDevicePtr pDevice, + NvU32 hParent, + NvU32 hMemory, + NvU32 hClass, + NvU32 flags, + void **ppAddress, + NvU64 *pLimit) +{ + return pDevice->pImports->rmApiAllocMemory64(pDevice, + hParent, + hMemory, + hClass, + flags, + ppAddress, + pLimit); +} + +static inline NvU32 nvPushImportRmApiVidHeapControl( + NvPushDevicePtr pDevice, + void *pVidHeapControlParms) +{ + return pDevice->pImports->rmApiVidHeapControl(pDevice, + pVidHeapControlParms); +} + +static inline NvU32 nvPushImportRmApiMapMemory( + NvPushDevicePtr pDevice, + NvU32 hDevice, + NvU32 hMemory, + NvU64 offset, + NvU64 length, + void **ppLinearAddress, + NvU32 flags) +{ + return pDevice->pImports->rmApiMapMemory(pDevice, + hDevice, + hMemory, + offset, + length, + ppLinearAddress, + flags); +} + +static inline NvU32 nvPushImportRmApiUnmapMemory( + NvPushDevicePtr pDevice, + NvU32 hDevice, + NvU32 hMemory, + void *pLinearAddress, + NvU32 flags) +{ + return pDevice->pImports->rmApiUnmapMemory(pDevice, + hDevice, + hMemory, + pLinearAddress, + flags); +} + +static inline NvU64 nvPushImportGetMilliSeconds( + NvPushDevicePtr pDevice) +{ + return pDevice->pImports->getMilliSeconds(pDevice); +} + +static inline void nvPushImportYield( + NvPushDevicePtr pDevice) +{ + pDevice->pImports->yield(pDevice); +} + +static inline NvBool nvPushImportWaitForEvent( + NvPushDevicePtr pDevice, + NvPushImportEvent *pEvent, + NvU64 timeout) +{ + return pDevice->pImports->waitForEvent(pDevice, pEvent, timeout); +} + +static inline void nvPushImportEmptyEventFifo( + NvPushDevicePtr pDevice, + NvPushImportEvent *pEvent) +{ + pDevice->pImports->emptyEventFifo(pDevice, pEvent); +} + +static inline void nvPushImportChannelErrorOccurred( + NvPushChannelPtr pChannel, + NvU32 channelErrCode) +{ + pChannel->pDevice->pImports->channelErrorOccurred(pChannel, channelErrCode); +} + +static inline void nvPushImportPushbufferWrapped( + NvPushChannelPtr pChannel) +{ + pChannel->pDevice->pImports->pushbufferWrapped(pChannel); +} + +#define nvPushImportLogError(_pDevice, ...) \ + (_pDevice)->pImports->logError((_pDevice), __VA_ARGS__) + +#if defined(DEBUG) +#define nvPushImportLogNvDiss(_pChannel, ...) \ + (_pChannel)->pDevice->pImports->logNvDiss((_pChannel), __VA_ARGS__) +#endif /* DEBUG */ + +#endif /* __NVIDIA_PUSH_PRIV_IMPORTS_H__ */ diff --git a/src/common/unix/nvidia-push/include/nvidia-push-priv.h b/src/common/unix/nvidia-push/include/nvidia-push-priv.h new file mode 100644 index 000000000..db76c0295 --- /dev/null +++ b/src/common/unix/nvidia-push/include/nvidia-push-priv.h @@ -0,0 +1,122 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVIDIA_PUSH_PRIV_H__ +#define __NVIDIA_PUSH_PRIV_H__ + +#include "nvmisc.h" // NV_ALIGN_UP +#include "class/cla16f.h" // NVA16F_GP_ENTRY__SIZE + +/* + * Push buffer constants + * "The pushbuffer" consists of several regions packed into a single memory + * allocation. In order, they are: + * 1. The "main" pushbuffer. Most of the driver pushes methods here; + * 2. GPFIFO entries; + * 3. The "progress tracker" pushbuffer. This is used by the DMA kickoff code + * as a reserved area to put semaphore release methods, which we use to + * track HOST's progress fetching the pushbuffer. We also use this to + * workaround hardware bug 1667921. + */ + +/* Offset of the GPFIFO entries: entry (2) above. */ +static inline NvU32 __nvPushGpFifoOffset(const NvPushChannelRec *pChannel) +{ + nvAssert(pChannel->main.sizeInBytes != 0); + return NV_ALIGN_UP(pChannel->main.sizeInBytes, NVA16F_GP_ENTRY__SIZE); +} + +/* + * We need to align each set of methods in the progress tracker pushbuffer to + * 128 bytes so that we avoid HW bug 1667921 (on chips that are affected). + * This is used for both the start of the GPFIFO segment _and_ the size (for + * each GPFIFO entry). + */ +#define NV_ALIGN_LBDAT_EXTRA_BUG 128 +/* + * Offset of the progress tracker pushbuffer: entry (3) above. + * + * Note that we always use the appropriate alignment to WAR the LBDAT_EXTRA bug + * for the offset. Although this is only necessary on some chips, it's simpler + * to always use this alignment. + */ +static inline NvU32 __nvPushProgressTrackerOffset( + const NvPushChannelRec *pChannel) +{ + const NvU32 gpFifoOffset = __nvPushGpFifoOffset(pChannel); + const NvU32 gpFifoLength = + pChannel->numGpFifoEntries * NVA16F_GP_ENTRY__SIZE; + + nvAssert(gpFifoLength != 0); + + return NV_ALIGN_UP(gpFifoOffset + gpFifoLength, NV_ALIGN_LBDAT_EXTRA_BUG); +} + +/* We always write two GPFIFO entries: one for the main pushbuffer, and one + * for the progress tracker pushbuffer. */ +#define NV_PUSH_NUM_GPFIFO_ENTRIES_PER_KICKOFF 2 + +/* + * Encoding for the progress tracker semaphore payload. + * _GET stores dwords, rather than bytes. + * _GP_GET stores the number of "pairs" of gpFifo entries. + */ +#define NV_PUSH_PROGRESS_TRACKER_SEMAPHORE_GET 17:0 +#define NV_PUSH_PROGRESS_TRACKER_SEMAPHORE_GP_GET 31:18 + +/* + * The number of 0080 RM devices for the given NvPushDevice. + * This is 1 for RM SLI and numSubDevices for client SLI. + */ +static inline int +__nvPushGetNumDevices(const NvPushDeviceRec *pDevice) +{ + if (pDevice->clientSli) { + return pDevice->numSubDevices; + } + return 1; +} + +/* + * The 0080 RM device index for the given subdevice index. + * This is 0 for RM SLI, and the subdevice index for client SLI. + */ +static inline int +__nvPushGetDeviceIndex(const NvPushDeviceRec *pDevice, int sd) +{ + if (pDevice->clientSli) { + return sd; + } + return 0; +} + +NvU32 __nvPushProgressTrackerEntrySize(const NvPushDeviceRec *pDevice); + +NvBool __nvPushTestPushBuffer(NvPushChannelPtr p); + +NvBool __nvPushGetHal( + const NvPushAllocDeviceParams *pParams, + NvU32 channelClass, + NvPushHal *pHal); + +#endif /* __NVIDIA_PUSH_PRIV_H__ */ diff --git a/src/common/unix/nvidia-push/interface/nvidia-push-init.h b/src/common/unix/nvidia-push/interface/nvidia-push-init.h new file mode 100644 index 000000000..7dd062025 --- /dev/null +++ b/src/common/unix/nvidia-push/interface/nvidia-push-init.h @@ -0,0 +1,259 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * This file contains nvidia-push device and channel setup structures and + * functions. + */ + +#ifndef __NVIDIA_PUSH_INIT_H__ +#define __NVIDIA_PUSH_INIT_H__ + + +#include "nvidia-push-types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * Return the index of the first class table element supported on this device. + * + * pClassTable is an array where each element corresponds to a class + * the caller supports. The first field in the array element should + * be an NvPushSupportedClass struct. There may be additional fields + * in the array element that are specific to the caller. The + * classTableStride argument indicates the size in bytes of one array + * element, such that nvPushGetSupportedClassIndex() can step from one + * array element to the next by adding classTableStride. + * + * nvPushGetSupportedClassIndex() will query the list of classes + * supported by this device, and return the index of the first + * pClassTable array element that is supported by the device. -1 is + * returned if there is no match. + * + * \param pDevice The nvidia-push device whose class list to consider. + * \param pClassTable The table of classes supported. + * \param classTableStride The size in bytes of one table element. + * \param classTableLength The number of table elements. + * + * \return The index of the first table element that matches, or -1. + */ + +typedef struct _NvPushSupportedClass { + NvU32 classNumber; + NVAModelConfig amodelConfig; +} NvPushSupportedClass; + +int nvPushGetSupportedClassIndex( + NvPushDevicePtr pDevice, + const void *pClassTable, + size_t classTableStride, + size_t classTableLength); + +/* + * Parameter structure populated by the host driver when requesting an + * NvPushDeviceRec. + */ +typedef struct _NvPushAllocDeviceParams { + + /* Pointer to host device, filled by host driver as needed */ + void *hostDevice; + + const NvPushImports *pImports; + + /* The host driver's RMAPI client (NV0000) handle. */ + NvU32 clientHandle; + + /* TRUE iff this device is in client-side SLI mode. */ + NvBool clientSli; + + /* The number of subDevices allocated by the host driver. */ + NvU32 numSubDevices; + + struct { + /* The host driver's RMAPI device (NV0080) handles */ + NvU32 deviceHandle; + /* The host driver's RMAPI subDevice (NV2080) handles. */ + NvU32 handle; + /* FERMI_VASPACE_A object in which channels on this device should be + * mapped. */ + NvU32 gpuVASpaceObject; + /* ctxDma handle to be used with MapMemoryDma. */ + NvU32 gpuVASpace; + } subDevice[NV_MAX_SUBDEVICES]; + + struct { + /* + * The Amodel configuration requested by the host driver. + */ + NVAModelConfig config; + } amodel; + + /* Whether channels on this device will be used to program Tegra. */ + NvBool isTegra; + + /* + * Pool of RMAPI object handles. The host driver should populate + * all of the elements in this array before calling + * nvPushAllocDevice(), and release all of these handles if + * nvPushAllocDevice() fails, or after calling nvPushFreeDevice(). + * + * The number of possible handles is: + * + * hUserMode (per-sd) + */ +#define NV_PUSH_DEVICE_HANDLE_POOL_NUM \ + (NV_MAX_SUBDEVICES) + + NvU32 handlePool[NV_PUSH_DEVICE_HANDLE_POOL_NUM]; + + NvU32 numClasses; + const NvU32 *supportedClasses; + +} NvPushAllocDeviceParams; + +NvBool nvPushAllocDevice( + const NvPushAllocDeviceParams *pParams, + NvPushDevicePtr pDevice); + +void nvPushFreeDevice( + NvPushDevicePtr pDevice); + + +/* + * Parameter structure populated by the host driver when requesting an + * NvPushChannelRec. + */ +typedef struct _NvPushAllocChannelParams { + + /* NV2080_ENGINE_TYPE_ */ + NvU32 engineType; + + /* + * Whether to log the pushbuffer in nvdiss format, by calling + * nvPushImportLogNvDiss(). + */ + NvBool logNvDiss; + + /* + * Normally, the pushbuffer utility library will time out when + * waiting for things (space in the pushbuffer, waiting for + * notifiers, etc). When the channel is created with + * noTimeout=TRUE, the channel will wait indefinitely for these + * things. + */ + NvBool noTimeout; + + /* + * Normally, the pushbuffer utility library checks for channel + * errors and reports them to the host driver by calling + * nvPushImportChannelErrorOccurred(). Host drivers can set + * ignoreChannelErrors=TRUE to disable this check. + */ + NvBool ignoreChannelErrors; + + /* + * DIFR stands for Display Idle Frame Refresh in which a CE is used to + * prefetch framebuffer pixels into the GPU's L2 cache. The prefetch + * operation requires the channel to be specifically configured for DIFR + * prefetching. This flag indicates if this channel is intended to be + * used for just that. + */ + NvBool difrPrefetch; + + /* + * Host drivers should specify how many notifiers they want. The + * pushbuffer utility library will allocate memory to hold this + * many notifiers on each subDevice, plus an error notifier. + * + * The 'notifierIndex' argument to, e.g., nvPushGetNotifierCpuAddress() + * should be in the range [0,numNotifiers). + */ + NvU8 numNotifiers; + + /* + * The size of the "main" pushbuffer in bytes. Note this does not + * include space for gpfifo entries or progress tracking: + * nvidia-push will implicitly pad the total pushbuffer for those + * items. + */ + NvU32 pushBufferSizeInBytes; + + /* + * Pool of RMAPI object handles. The host driver should populate + * all of the elements in this array before calling + * nvPushAllocChannel(), and release all of these handles if + * nvPushAllocChannel() fails, or after calling nvPushFreeChannel(). + * + * The number of possible handles is: + * + * progressSemaphore hMemory (per-sd) + + * pushbufferHandle (per-device) + + * pushbufferVAHandle (per-sd) + + * userD.hMemory (per-sd) + + * channelHandle (per-sd) + + * notifier memoryHandle (per-device) + + * error notifier ctxDma (per-device) + */ +#define NV_PUSH_CHANNEL_HANDLE_POOL_NUM \ + (NV_MAX_SUBDEVICES + \ + 1 + \ + NV_MAX_SUBDEVICES + \ + NV_MAX_SUBDEVICES + \ + NV_MAX_SUBDEVICES + \ + 1 + \ + 1) + + NvU32 handlePool[NV_PUSH_CHANNEL_HANDLE_POOL_NUM]; + + /* + * A pointer to an NvPushDeviceRec, initialized with + * nvPushAllocDevice(). One or more NvPushChannelRecs may share + * the same NvPushDevicePtr. + * + * This pDevice should be kept allocated until all + * NvPushChannelRecs using it have been freed. + */ + NvPushDevicePtr pDevice; + +} NvPushAllocChannelParams; + +NvBool nvPushAllocChannel( + const NvPushAllocChannelParams *pParams, + NvPushChannelPtr buffer); + +void nvPushFreeChannel( + NvPushChannelPtr buffer); + + +void nvPushInitWaitForNotifier( + NvPushChannelPtr pChannel, + NvU32 notifierIndex, + NvU32 subdeviceMask); + +#ifdef __cplusplus +}; +#endif + +#endif /*__NVIDIA_PUSH_INIT_H__ */ diff --git a/src/common/unix/nvidia-push/interface/nvidia-push-methods.h b/src/common/unix/nvidia-push/interface/nvidia-push-methods.h new file mode 100644 index 000000000..bdbc558e7 --- /dev/null +++ b/src/common/unix/nvidia-push/interface/nvidia-push-methods.h @@ -0,0 +1,247 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * This file contains macros and inline functions used to actually program + * methods. + */ + +#ifndef __NVIDIA_PUSH_METHODS_H__ +#define __NVIDIA_PUSH_METHODS_H__ + +#include "nvidia-push-types.h" + +#include "class/cla16f.h" + +#ifdef __cplusplus +extern "C" { +#endif + +static inline void __nvPushSetMethodDataSegment(NvPushChannelSegmentPtr s, const NvU32 data) +{ + s->buffer->u = data; + s->buffer++; +} + +static inline void nvPushSetMethodData(NvPushChannelPtr p, const NvU32 data) +{ + __nvPushSetMethodDataSegment(&p->main, data); +} + +#if NV_PUSH_ALLOW_FLOAT +static inline void __nvPushSetMethodDataSegmentF(NvPushChannelSegmentPtr s, const float data) +{ + s->buffer->f = data; + s->buffer++; +} + +static inline void nvPushSetMethodDataF(NvPushChannelPtr p, const float data) +{ + __nvPushSetMethodDataSegmentF(&p->main, data); +} +#endif + +static inline void __nvPushSetMethodDataSegmentU64(NvPushChannelSegmentPtr s, const NvU64 data) +{ + __nvPushSetMethodDataSegment(s, NvU64_HI32(data)); + __nvPushSetMethodDataSegment(s, NvU64_LO32(data)); +} + +static inline void nvPushSetMethodDataU64(NvPushChannelPtr p, const NvU64 data) +{ + __nvPushSetMethodDataSegmentU64(&p->main, data); +} + +void __nvPushMoveDWORDS(NvU32* dst, const NvU32* src, int dwords); + +static inline void +nvDmaMoveDWORDS(NvPushChannelUnion *dst, const NvU32* src, int dwords) +{ + // The 'dst' argument is an array of NvPushChannelUnion; it is safe + // to treat this as an array of NvU32, as long as NvU32 and + // NvPushChannelUnion are the same size. + ct_assert(sizeof(NvU32) == sizeof(NvPushChannelUnion)); + __nvPushMoveDWORDS((NvU32 *)dst, src, dwords); +} + +static inline void nvPushInlineData(NvPushChannelPtr p, const void *data, + size_t dwords) +{ + nvDmaMoveDWORDS(p->main.buffer, (const NvU32 *)data, dwords); + p->main.buffer += dwords; +} + +/*! + * Return the maximum method count: the maximum number of dwords that can be + * specified in the nvPushMethod() family of macros. + */ +static inline NvU32 nvPushMaxMethodCount(const NvPushChannelRec *p) +{ + /* + * The number of methods that can be specified in one NVA16F_DMA_METHOD + * header is limited by the bit field size of NVA16F_DMA_METHOD_COUNT: 28:16 + * (i.e., maximum representable value 8191). + */ + const NvU32 maxFromMethodCountMask = DRF_MASK(NVA16F_DMA_METHOD_COUNT); + + /* + * Further, the method count must be smaller than half the total pushbuffer + * size minus one, to correctly distinguish empty and full pushbuffers. See + * nvPushHeader() for details. + */ + const NvU32 pushBufferSizeInBytes = p->main.sizeInBytes; + const NvU32 pushBufferSizeInDWords = pushBufferSizeInBytes / 4; + const NvU32 pushBufferHalfSizeInDWords = pushBufferSizeInDWords / 2; + + /* + * Subtract two from pushBufferHalfSizeInDWords: + * + * -1 to distinguish pushbuffer empty from full (see above). + * + * -1 to be smaller than, rather than equal to, the above constraints. + */ + const NvU32 maxFromPushBufferSize = pushBufferHalfSizeInDWords - 2; + + return NV_MIN(maxFromMethodCountMask, maxFromPushBufferSize); +} + +// These macros verify that the values used in the methods fits +// into the defined ranges. +#define ASSERT_DRF_DEF(d, r, f, n) \ + nvAssert(!(~DRF_MASK(NV ## d ## r ## f) & (NV ## d ## r ## f ## n))) +#define ASSERT_DRF_NUM(d, r, f, n) \ + nvAssert(!(~DRF_MASK(NV ## d ## r ## f) & (n))) + +#if defined(DEBUG) +#include "class/clc36f.h" /* VOLTA_CHANNEL_GPFIFO_A */ + +/* + * When pushing GPFIFO methods (NVA16F_SEMAPHORE[ABCD]), all four + * methods must be pushed together. If the four methods are not + * pushed together, nvidia-push might wrap, injecting its progress + * tracking semaphore release methods in the middle, and perturb the + * NVA16F_SEMAPHOREA_OFFSET_UPPER and NVA16F_SEMAPHOREB_OFFSET_LOWER + * channel state. + * + * Return whether the methods described by the arguments include some, + * but not all, of A, B, C, and D. I.e., if the range starts at B, C, + * or D, or if the range ends at A, B, or C. + * + * Perform a similar check for Volta+ semaphore methods + * NVC36F_SEM_ADDR_LO..NVC36F_SEM_EXECUTE. Note that we always check for both + * sets of methods, regardless of the GPU we're actually running on. This is + * okay since: + * a) the NVC36F_SEM_ADDR_LO..NVC36F_SEM_EXECUTE method offsets were not used + * for anything from (a16f..c36f]. + * b) the SEMAPHORE[ABCD] methods still exist on the newer classes (they + * haven't been reused for anything else) + */ +static inline NvBool __nvPushStartSplitsSemaphore( + NvU32 method, + NvU32 count, + NvU32 secOp) +{ + ct_assert(NVA16F_SEMAPHOREA < NVA16F_SEMAPHORED); + ct_assert(NVC36F_SEM_ADDR_LO < NVC36F_SEM_EXECUTE); + + /* + * compute start and end as inclusive; if not incrementing, we + * assume end==start + */ + const NvU32 start = method; + const NvU32 end = (secOp == NVA16F_DMA_SEC_OP_INC_METHOD) ? + (method + ((count - 1) * 4)) : method; + + return ((start > NVA16F_SEMAPHOREA) && (start <= NVA16F_SEMAPHORED)) || + ((end >= NVA16F_SEMAPHOREA) && (end < NVA16F_SEMAPHORED)) || + ((start > NVC36F_SEM_ADDR_LO) && (start <= NVC36F_SEM_EXECUTE)) || + ((end >= NVC36F_SEM_ADDR_LO) && (end < NVC36F_SEM_EXECUTE)); +} +#endif /* DEBUG */ + +/* + * Note that _count+1 must be less than half the total pushbuffer size. This is + * required by GPFIFO because we can't reliably tell when we can write all the + * way to the end of the pushbuffer if we wrap (see bug 232454). This + * assumption ensures that there will be enough space once GET reaches PUT. + */ +#define nvPushHeader(_push_buffer, _segment, _count, _header) do { \ + NvPushChannelSegmentPtr _pSegment = &(_push_buffer)->_segment; \ + nvAssert(((_count)+1) < ((_pSegment)->sizeInBytes / 8)); \ + if ((_pSegment)->freeDwords < ((_count)+1)) \ + __nvPushMakeRoom((_push_buffer), (_count) + 1); \ + __nvPushSetMethodDataSegment((_pSegment), (_header)); \ + (_pSegment)->freeDwords -= ((_count)+1); \ +} while(0) + +#define __nvPushStart(_push_buffer, _segment, _subch, _offset, _count, _opcode) \ +{ \ + nvAssert(!__nvPushStartSplitsSemaphore( \ + (_offset), \ + (_count), \ + NVA16F_DMA_SEC_OP ## _opcode)); \ + ASSERT_DRF_DEF(A16F, _DMA, _SEC_OP, _opcode); \ + ASSERT_DRF_NUM(A16F, _DMA, _METHOD_COUNT, _count); \ + ASSERT_DRF_NUM(A16F, _DMA, _METHOD_SUBCHANNEL, _subch); \ + ASSERT_DRF_NUM(A16F, _DMA, _METHOD_ADDRESS, (_offset) >> 2); \ + nvPushHeader((_push_buffer), _segment, (_count), \ + DRF_DEF(A16F, _DMA, _SEC_OP, _opcode) | \ + DRF_NUM(A16F, _DMA, _METHOD_COUNT, _count) | \ + DRF_NUM(A16F, _DMA, _METHOD_SUBCHANNEL, _subch) | \ + DRF_NUM(A16F, _DMA, _METHOD_ADDRESS, (_offset) >> 2)); \ +} + +// The GPU can encode a 13-bit constant method/data pair in a single DWORD. +#define nvPushImmedValSegment(_push_buffer, _segment, _subch, _offset, _data) { \ + ASSERT_DRF_NUM(A16F, _DMA, _IMMD_DATA, _data); \ + ASSERT_DRF_NUM(A16F, _DMA, _METHOD_SUBCHANNEL, _subch); \ + ASSERT_DRF_NUM(A16F, _DMA, _METHOD_ADDRESS, (_offset) >> 2); \ + if ((_push_buffer)->_segment.freeDwords < 1) \ + __nvPushMakeRoom((_push_buffer), 1); \ + __nvPushSetMethodDataSegment(&(_push_buffer)->_segment, \ + DRF_DEF(A16F, _DMA, _SEC_OP, _IMMD_DATA_METHOD) | \ + DRF_NUM(A16F, _DMA, _IMMD_DATA, _data) | \ + DRF_NUM(A16F, _DMA, _METHOD_SUBCHANNEL, _subch) | \ + DRF_NUM(A16F, _DMA, _METHOD_ADDRESS, (_offset) >> 2)); \ + (_push_buffer)->_segment.freeDwords--; \ +} + +#define nvPushImmedVal(_push_buffer, _subch, _offset, _data) \ + nvPushImmedValSegment(_push_buffer, main, _subch, _offset, _data) + +#define nvPushImmed(_push_buffer, _subch, _offset, _val) \ + nvPushImmedVal(_push_buffer, _subch, _offset, _offset##_V_##_val) + +// Method headers. +#define nvPushMethod(_push_buffer, _subch, _offset, _count) \ + __nvPushStart(_push_buffer, main, _subch, _offset, _count, _INC_METHOD) +#define nvPushMethodNoIncr(_push_buffer, _subch, _offset, _count) \ + __nvPushStart(_push_buffer, main, _subch, _offset, _count, _NON_INC_METHOD) +#define nvPushMethodOneIncr(_push_buffer, _subch, _offset, _count) \ + __nvPushStart(_push_buffer, main, _subch, _offset, _count, _ONE_INC) + +#ifdef __cplusplus +}; +#endif + +#endif /* __NVIDIA_PUSH_METHODS_H__ */ diff --git a/src/common/unix/nvidia-push/interface/nvidia-push-types.h b/src/common/unix/nvidia-push/interface/nvidia-push-types.h new file mode 100644 index 000000000..4772ee11d --- /dev/null +++ b/src/common/unix/nvidia-push/interface/nvidia-push-types.h @@ -0,0 +1,281 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * This file contains core definitions (structures and enums) for use in the + * rest of the nvidia-push code. + */ + +#ifndef __NVIDIA_PUSH_TYPES_H__ +#define __NVIDIA_PUSH_TYPES_H__ + +#include /* size_t */ + + + +#include "nvtypes.h" +#include "nvlimits.h" +#include "nvmisc.h" +#include "nvgputypes.h" /* NvNotificationRec */ +#include "nv_common_utils.h" /* TRUE/FALSE */ +#include "nvctassert.h" +#include "nv_assert.h" /* nvAssert() */ +#include "nv_amodel_enum.h" /* NVAModelConfig */ +#include "nvos.h" /* NV_CHANNELGPFIFO_NOTIFICATION_* */ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV_PUSH_NOTIFIER_SHORT_TIMEOUT 3000 /* in milliseconds (ie: 3 seconds) */ +#define NV_PUSH_NOTIFIER_LONG_TIMEOUT 10000 /* in milliseconds (ie: 10 seconds) */ + +# define NV_PUSH_PRINTF_FORMAT_ARGUMENT +# define NV_PUSH_PRINTF_ATTRIBUTES(_fmt,_var) \ + __attribute__((format (printf, _fmt, _var))) + + +#if defined(NV_PUSH_IN_KERNEL) +# define NV_PUSH_ALLOW_FLOAT 0 +#else +# define NV_PUSH_ALLOW_FLOAT 1 +#endif + +typedef union _NvPushChannelUnion +{ + NvU32 u; +#if NV_PUSH_ALLOW_FLOAT + float f; +#endif +} NvPushChannelUnion; + +typedef struct _NvPushChannelRec NvPushChannelRec; +typedef struct _NvPushChannelRec *NvPushChannelPtr; + +typedef struct _nv_push_hal { + void (*kickoff)(struct _NvPushChannelRec*, NvU32 oldGpPut, NvU32 newGpPut); + void (*releaseTimelineSemaphore)(NvPushChannelPtr, void *cpuAddress, NvU64 gpuAddress, NvU64 val); + void (*acquireTimelineSemaphore)(NvPushChannelPtr, NvU64 gpuAddress, NvU64 val); + struct { + /* Requires USERD memory to be specified at channel allocation */ + NvU32 clientAllocatesUserD :1; + + /* On Tegra, we currently need to allocate double the requested GPFIFO + * entries */ + NvU32 allocateDoubleSizeGpFifo :1; + + /* Use Volta+ semaphore methods */ + NvU32 voltaSemMethods :1; + + NvU32 extendedBase :1; + } caps; +} NvPushHal; + +typedef struct _NvPushDeviceRec { + + void *hostDevice; /* Provided by the host driver */ + + NvBool hostLBoverflowBug1667921 : 1; + NvBool clientSli : 1; /* Provided by the host driver */ + + NvU32 clientHandle; /* Provided by the host driver */ + NvU32 numSubDevices; /* Provided by the host driver */ + + NvU32 numClasses; /* Provided by the host driver */ + const NvU32 *supportedClasses;/* Provided by the host driver */ + + struct { + NvU32 handle; /* Provided by the host driver */ + NvU32 deviceHandle; /* Provided by the host driver */ + NvU32 gpuVASpaceObject;/* Provided by the host driver */ + NvU32 gpuVASpaceCtxDma;/* Provided by the host driver */ + NvU32 hUserMode; /* VOLTA_USERMODE_A object */ + void *pUserMode; /* VOLTA_USERMODE_A mapping */ + } subDevice[NV_MAX_SUBDEVICES]; + + NvU32 gpfifoClass; + size_t userDSize; + + NVAModelConfig amodelConfig; + + NvPushHal hal; + const struct _NvPushImports *pImports; + +} NvPushDeviceRec, *NvPushDevicePtr; + + +typedef struct _NvPushChannelSegmentRec +{ + NvU32 freeDwords; // free space (in dwords) + NvU32 sizeInBytes; // Push buffer size (in bytes) + NvU32 putOffset; // Offset of last kickoff + NvPushChannelUnion *base; // Push buffer start pointer + NvPushChannelUnion *buffer; // Push buffer current pointer + NvU64 gpuMapOffset; +} NvPushChannelSegmentRec, *NvPushChannelSegmentPtr; + +struct _NvPushChannelRec +{ + NvBool initialized : 1; + NvBool logNvDiss : 1; + NvBool noTimeout : 1; + NvBool ignoreChannelErrors : 1; + NvBool channelErrorOccurred : 1; + + NvU32 channelHandle[NV_MAX_SUBDEVICES]; + NvU32 pushbufferHandle; + NvU32 pushbufferVAHandle[NV_MAX_SUBDEVICES]; + NvPushChannelSegmentRec main; + + void *control[NV_MAX_SUBDEVICES]; + NvU32 numGpFifoEntries; + NvU32 *gpfifo; // GPFIFO entries + NvU32 gpPutOffset; // GPFIFO entries last kicked off offset + NvU32 currentSubDevMask; + + NvPushChannelSegmentRec progressTracker; + struct { + NvU32 handle[NV_MAX_SUBDEVICES]; + void *ptr[NV_MAX_SUBDEVICES]; + NvU64 gpuVA; + } progressSemaphore; + + struct { + NvU32 hMemory; + } userD[NV_MAX_SUBDEVICES]; + + struct { + NvU8 num; + NvU32 memoryHandle; + NvNotification *cpuAddress; + NvU64 gpuAddress; + NvU32 errorCtxDma; + } notifiers; + + NvPushDeviceRec *pDevice; +}; + +/* Opaque type, only used by pointer within the push buffer utility library. */ +typedef struct _NvPushImportEvent NvPushImportEvent; + +/* Table of function pointers to be provided by the nvidia-push host driver. */ +typedef struct _NvPushImports { + + NvU32 (*rmApiControl) (NvPushDevicePtr pDevice, + NvU32 hObject, + NvU32 cmd, + void *pParams, + NvU32 paramsSize); + + NvU32 (*rmApiAlloc) (NvPushDevicePtr pDevice, + NvU32 hParent, + NvU32 hObject, + NvU32 hClass, + void *pAllocParams); + + NvU32 (*rmApiFree) (NvPushDevicePtr pDevice, + NvU32 hParent, + NvU32 hObject); + + NvU32 (*rmApiMapMemoryDma) (NvPushDevicePtr pDevice, + NvU32 hDevice, + NvU32 hDma, + NvU32 hMemory, + NvU64 offset, + NvU64 length, + NvU32 flags, + NvU64 *pDmaOffset); + + NvU32 (*rmApiUnmapMemoryDma) (NvPushDevicePtr pDevice, + NvU32 hDevice, + NvU32 hDma, + NvU32 hMemory, + NvU32 flags, + NvU64 dmaOffset); + + NvU32 (*rmApiAllocMemory64) (NvPushDevicePtr pDevice, + NvU32 hParent, + NvU32 hMemory, + NvU32 hClass, + NvU32 flags, + void **ppAddress, + NvU64 *pLimit); + + NvU32 (*rmApiVidHeapControl) (NvPushDevicePtr pDevice, + void *pVidHeapControlParms); + + NvU32 (*rmApiMapMemory) (NvPushDevicePtr pDevice, + NvU32 hDevice, + NvU32 hMemory, + NvU64 offset, + NvU64 length, + void **ppLinearAddress, + NvU32 flags); + + NvU32 (*rmApiUnmapMemory) (NvPushDevicePtr pDevice, + NvU32 hDevice, + NvU32 hMemory, + void *pLinearAddress, + NvU32 flags); + + NvU64 (*getMilliSeconds) (NvPushDevicePtr pDevice); + + void (*yield) (NvPushDevicePtr pDevice); + + NvBool (*waitForEvent) (NvPushDevicePtr pDevice, + NvPushImportEvent *pEvent, + NvU64 timeout); + + void (*emptyEventFifo) (NvPushDevicePtr pDevice, + NvPushImportEvent *pEvent); + + void (*channelErrorOccurred) (NvPushChannelPtr pChannel, NvU32 channelErrCode); + + void (*pushbufferWrapped) (NvPushChannelPtr pChannel); + + void (*logError) (NvPushDevicePtr pDevice, + NV_PUSH_PRINTF_FORMAT_ARGUMENT const char *fmt, ...) + NV_PUSH_PRINTF_ATTRIBUTES(2,3); + + /* + * The logNvDiss() import, in DEBUG builds, logs strings to be + * parsed by nvdiss. Note that multiple nvPushImportLogNvDiss() + * calls may be used to build one line of output (so, respect the + * newlines provided in the strings). + */ +#if defined(DEBUG) + void (*logNvDiss) (NvPushChannelPtr pChannel, + NV_PUSH_PRINTF_FORMAT_ARGUMENT const char *fmt, ...) + NV_PUSH_PRINTF_ATTRIBUTES(2,3); +#endif + +} NvPushImports; + + +void __nvPushMakeRoom(NvPushChannelPtr, NvU32 count); + +#ifdef __cplusplus +}; +#endif + +#endif /* __NVIDIA_PUSH_TYPES_H__ */ diff --git a/src/common/unix/nvidia-push/interface/nvidia-push-utils.h b/src/common/unix/nvidia-push/interface/nvidia-push-utils.h new file mode 100644 index 000000000..7dfa8e208 --- /dev/null +++ b/src/common/unix/nvidia-push/interface/nvidia-push-utils.h @@ -0,0 +1,180 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* This file contains push buffer utility functions and declarations */ + +#ifndef __NVIDIA_PUSH_UTILS_H__ +#define __NVIDIA_PUSH_UTILS_H__ + +#include "nvidia-push-types.h" +#include "nvlimits.h" + +#include "class/cla16f.h" + +#ifdef __cplusplus +extern "C" { +#endif + +static inline NvBool nvPushIsAModel(const NvPushDeviceRec *pDevice) +{ + return FALSE; +} + + +/* declare prototypes: */ +NvBool nvPushCheckChannelError(NvPushChannelPtr pChannel); +void nvPushKickoff(NvPushChannelPtr); +NvBool nvPushIdleChannelTest(NvPushChannelPtr pChannel, NvU32 timeoutMSec); +NvBool nvPushIdleChannel(NvPushChannelPtr); + +void nvPushWaitForNotifier( + NvPushChannelPtr pChannel, + NvU32 notifierIndex, + NvU32 subdeviceMask, + NvBool yield, + NvPushImportEvent *pEvent, + int id); + +void nvPushReleaseTimelineSemaphore( + NvPushChannelPtr p, + void *cpuAddress, + NvU64 gpuAddress, + NvU64 val); + +void nvPushAcquireTimelineSemaphore( + NvPushChannelPtr p, + NvU64 gpuAddress, + NvU64 val); + +NvBool nvPushDecodeMethod(NvU32 header, NvU32 *count); +void nvPushSetObject(NvPushChannelPtr p, NvU32 subch, NvU32 object[NV_MAX_SUBDEVICES]); +void nvPushSetSubdeviceMask(NvPushChannelPtr p, NvU32 mask); +void __nvPushMakeRoom(NvPushChannelPtr, NvU32 count); + +#define NV_PUSH_SUBDEVICE_MASK_PRIMARY 0x00000001 +#define NV_PUSH_SUBDEVICE_MASK_ALL DRF_MASK(NVA16F_DMA_SET_SUBDEVICE_MASK_VALUE) + +/* + * Evaluates to TRUE if the two subDevMasks are equivalent for the given SLI + * device + */ +static inline NvBool nvPushSubDeviceMaskEquiv( + const NvPushDeviceRec *pDevice, + NvU32 maskA, + NvU32 maskB) +{ + const NvU32 allSubDevices = (1 << pDevice->numSubDevices) - 1; + + return (maskA & allSubDevices) == (maskB & allSubDevices); +} + +/* Evaluates to TRUE if subDevMask will write to all of the GPUs */ +static inline NvBool nvPushSubDeviceMaskAllActive( + const NvPushDeviceRec *pDevice, + NvU32 subDevMask) +{ + return nvPushSubDeviceMaskEquiv(pDevice, subDevMask, + NV_PUSH_SUBDEVICE_MASK_ALL); +} + +#define NV_PUSH_NOTIFIER_INTERNAL_BIT 0x80 +ct_assert(NV_PUSH_NOTIFIER_INTERNAL_BIT >= + NV_CHANNELGPFIFO_NOTIFICATION_TYPE__SIZE_1); +#define NV_PUSH_ERROR_NOTIFIER_INDEX \ + (NV_PUSH_NOTIFIER_INTERNAL_BIT | \ + NV_CHANNELGPFIFO_NOTIFICATION_TYPE_ERROR) +#define NV_PUSH_TOKEN_NOTIFIER_INDEX \ + (NV_PUSH_NOTIFIER_INTERNAL_BIT | \ + NV_CHANNELGPFIFO_NOTIFICATION_TYPE_WORK_SUBMIT_TOKEN) + +/* + * Notifiers for use by nvidia-push, not exposed to clients: + * NV_CHANNELGPFIFO_NOTIFICATION_TYPE__SIZE_1: defined by RM + * NV_MAX_SUBDEVICES: one for each subdevice to track work submission token + */ +#define NV_PUSH_NUM_INTERNAL_NOTIFIERS \ + (NV_CHANNELGPFIFO_NOTIFICATION_TYPE__SIZE_1 + NV_MAX_SUBDEVICES) + +static inline NvU32 __nvPushGetNotifierRawIndex( + const NvPushDeviceRec *pDevice, + NvU32 notifierIndex, + NvU32 sd) +{ + if (notifierIndex & NV_PUSH_NOTIFIER_INTERNAL_BIT) { + return notifierIndex & ~NV_PUSH_NOTIFIER_INTERNAL_BIT; + } else { + return (notifierIndex * pDevice->numSubDevices) + sd + + NV_PUSH_NUM_INTERNAL_NOTIFIERS; + } +} + +static inline NvNotification *nvPushGetNotifierCpuAddress( + const NvPushChannelRec *pChannel, + NvU32 notifierIndex, + NvU32 sd) +{ + const NvU32 rawIndex = + __nvPushGetNotifierRawIndex(pChannel->pDevice, notifierIndex, sd); + + return &pChannel->notifiers.cpuAddress[rawIndex]; +} + +static inline NvU64 nvPushGetNotifierGpuAddress( + const NvPushChannelRec *pChannel, + NvU32 notifierIndex, + NvU32 sd) +{ + const NvU32 rawIndex = + __nvPushGetNotifierRawIndex(pChannel->pDevice, notifierIndex, sd); + const size_t offset = rawIndex * sizeof(NvNotification); + + return pChannel->notifiers.gpuAddress + offset; +} + + +extern NvU32 nvPushReadGetOffset(NvPushChannelPtr push_buffer, NvBool minimum); + + +/*! + * Make room in the pushbuffer, checking for errors. + * + * If a channel error occurred, channelErrorOccurred is set to TRUE. + * nvPushCheckForRoomAndErrors() is designed to be called just before a + * nvPushMethod() with the same size. + */ +static inline void nvPushCheckForRoomAndErrors( + NvPushChannelPtr pChannel, + NvU32 count) +{ + pChannel->channelErrorOccurred = FALSE; + + if (pChannel->main.freeDwords < (count + 1)) { + __nvPushMakeRoom(pChannel, count + 1); + } +} + +#ifdef __cplusplus +}; +#endif + +#endif /* __NVIDIA_PUSH_UTILS_H__ */ diff --git a/src/common/unix/nvidia-push/src/nvidia-push-init.c b/src/common/unix/nvidia-push/src/nvidia-push-init.c new file mode 100644 index 000000000..3262815d8 --- /dev/null +++ b/src/common/unix/nvidia-push/src/nvidia-push-init.c @@ -0,0 +1,1531 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + + +#include "nvidia-push-init.h" +#include "nvidia-push-utils.h" +#include "nvidia-push-priv.h" +#include "nvidia-push-priv-imports.h" + +#include "nvos.h" + +#include "nv_assert.h" + +#include "alloc/alloc_channel.h" +#include "class/cl0002.h" // NV01_CONTEXT_DMA +#include "class/cl003e.h" // NV01_MEMORY_SYSTEM +#include "class/cl0040.h" // NV01_MEMORY_LOCAL_USER + +#include "class/cla16f.h" // KEPLER_CHANNEL_GPFIFO_B +#include "class/cla26f.h" // KEPLER_CHANNEL_GPFIFO_C +#include "class/clb06f.h" // MAXWELL_CHANNEL_GPFIFO_A +#include "class/clc06f.h" // PASCAL_CHANNEL_GPFIFO_A +#include "class/clc36f.h" // VOLTA_CHANNEL_GPFIFO_A +#include "class/clc46f.h" // TURING_CHANNEL_GPFIFO_A +#include "class/cl50a0.h" // NV50_MEMORY_VIRTUAL +#include "class/clc56f.h" // AMPERE_CHANNEL_GPFIFO_A +#include "class/clc86f.h" // HOPPER_CHANNEL_GPFIFO_A +#include "class/clc361.h" // VOLTA_USERMODE_A +#include "class/clc661.h" // HOPPER_USERMODE_A + +#include "ctrl/ctrl0080/ctrl0080fifo.h" // NV0080_CTRL_CMD_FIFO_GET_CAPS_V2 +#include "ctrl/ctrl2080/ctrl2080bus.h" // NV2080_CTRL_CMD_BUS_GET_INFO +#include "ctrl/ctrla06f.h" // KEPLER_CHANNEL_GPFIFO_A +#include "ctrl/ctrlc36f.h" // VOLTA_CHANNEL_GPFIFO_A + +static NvU32 GetHandle( + const NvU32 *pHandlePool, + NvU8 handlePoolSize, + NvU64 *pUsedHandleBitmask) +{ + NvU8 i; + const NvU64 usedHandleBitmask = *pUsedHandleBitmask; + + /* + * We assume there are less than 64 handles in the pool. If the + * pool is larger than that, we'll need a fancier bitmask. + */ + nvAssert(handlePoolSize < (sizeof(NvU64) * 8)); + + for (i = 0; i < handlePoolSize; i++) { + if ((usedHandleBitmask & NVBIT64(i)) == 0) { + *pUsedHandleBitmask |= NVBIT64(i); + return pHandlePool[i]; + } + } + + nvAssert(!"Exhausted handlePool!"); + + return 0; +} + +static NvU32 GetChannelHandle( + const NvPushAllocChannelParams *pParams, + NvU64 *pUsedHandleBitmask) +{ + return GetHandle(pParams->handlePool, + ARRAY_LEN(pParams->handlePool), + pUsedHandleBitmask); +} + +static NvU32 GetDeviceHandle( + const NvPushAllocDeviceParams *pParams, + NvU64 *pUsedHandleBitmask) +{ + return GetHandle(pParams->handlePool, + ARRAY_LEN(pParams->handlePool), + pUsedHandleBitmask); +} + +static void FreeSemaSurface(NvPushChannelPtr p) +{ + NvPushDevicePtr pDevice = p->pDevice; + NvU32 *handle = p->progressSemaphore.handle; + void **ptr = p->progressSemaphore.ptr; + NvU32 status; + int sd; + + if (p->progressSemaphore.gpuVA) { + for (sd = pDevice->numSubDevices - 1; sd >= 0; sd--) { + const int deviceIndex = __nvPushGetDeviceIndex(pDevice, sd); + status = nvPushImportRmApiUnmapMemoryDma( + pDevice, + pDevice->subDevice[sd].handle, + pDevice->subDevice[deviceIndex].gpuVASpaceCtxDma, + handle[sd], + 0, + p->progressSemaphore.gpuVA); + if (status != NVOS_STATUS_SUCCESS) { + nvAssert(!"Failed to unmap progressSemaphore"); + } + } + p->progressSemaphore.gpuVA = 0; + } + + for (sd = pDevice->numSubDevices - 1; sd >= 0; sd--) { + const int deviceIndex = __nvPushGetDeviceIndex(pDevice, sd); + if (!handle[sd]) { + continue; + } + status = nvPushImportRmApiFree( + pDevice, + pDevice->subDevice[deviceIndex].deviceHandle, + handle[sd]); + if (status != NVOS_STATUS_SUCCESS) { + nvAssert(!"Failed to free progressSemaphore"); + } + handle[sd] = 0; + + /* Freeing this memory automatically unmaps it. */ + ptr[sd] = NULL; + } +} + +static NvBool AllocSemaSurface( + NvPushChannelPtr p, + const NvPushAllocChannelParams *pParams, + NvBool coherent, + NvU64 *pUsedHandleBitmask) +{ + NvPushDevicePtr pDevice = p->pDevice; + NvU32 *handle = p->progressSemaphore.handle; + void **ptr = p->progressSemaphore.ptr; + NvU32 status; + const NvU64 size = 4096; + unsigned int sd; + + /* 1. Allocate sysmem surface(s) to back the semaphore, get CPU mapping */ + for (sd = 0; sd < pDevice->numSubDevices; sd++) { + const int deviceIndex = __nvPushGetDeviceIndex(pDevice, sd); + NvU64 limit = size - 1; + const NvU32 flags = DRF_DEF(OS02, _FLAGS, _PHYSICALITY, _NONCONTIGUOUS) | + (coherent ? DRF_DEF(OS02, _FLAGS, _COHERENCY, _CACHED) : + DRF_DEF(OS02, _FLAGS, _COHERENCY, _UNCACHED)); + + handle[sd] = GetChannelHandle(pParams, pUsedHandleBitmask); + + status = nvPushImportRmApiAllocMemory64(pDevice, + pDevice->subDevice[deviceIndex].deviceHandle, + handle[sd], + NV01_MEMORY_SYSTEM, + flags, + &ptr[sd], + &limit); + + if (status != NVOS_STATUS_SUCCESS) { + handle[sd] = 0; + nvAssert(!"Failed to allocate FIFO semaphore surface"); + goto fail; + } + } + + /* 2. Map the surface(s) into the GPU(s) */ + for (sd = 0; sd < pDevice->numSubDevices; sd++) { + NvU32 flags = DRF_DEF(OS46, _FLAGS, _ACCESS, _READ_WRITE) | + DRF_DEF(OS46, _FLAGS, _PAGE_SIZE, _4KB) | + (coherent ? DRF_DEF(OS46, _FLAGS, _CACHE_SNOOP, _ENABLE) : + DRF_DEF(OS46, _FLAGS, _CACHE_SNOOP, _DISABLE)); + const int deviceIndex = __nvPushGetDeviceIndex(pDevice, sd); + + /* + * Note that this mapping is somewhat special because we use a + * different surface for each subdevice, but want to map at the same + * virtual address on all subdevices. + */ + if (sd == 0) { + /* + * Create a new virtual mapping. + * + * The MapMemoryDma call will assign to + * 'p->progressSemaphore.gpuVA'. + * + * In !clientSli, this creates a broadcast mapping that we override + * with the _DMA_UNICAST_REUSE_ALLOC flag below. + * In clientSli, each mapping is already unicast. + * + * In both cases, the DMA_OFFSET_FIXED flag ensures the VA matches + * between all subdevices. + */ + p->progressSemaphore.gpuVA = 0; + flags = FLD_SET_DRF(OS46, _FLAGS, _DMA_OFFSET_FIXED, _FALSE, flags); + } else { + /* + * The MapMemoryDma call will read from + * 'p->progressSemaphore.gpuVA'. + */ + nvAssert(p->progressSemaphore.gpuVA != 0); + if (!pDevice->clientSli) { + flags = FLD_SET_DRF(OS46, _FLAGS, _DMA_UNICAST_REUSE_ALLOC, _TRUE, flags); + } + flags = FLD_SET_DRF(OS46, _FLAGS, _DMA_OFFSET_FIXED, _TRUE, flags); + } + + status = nvPushImportRmApiMapMemoryDma(pDevice, + pDevice->subDevice[sd].handle, + pDevice->subDevice[deviceIndex].gpuVASpaceCtxDma, + handle[sd], + 0, + size, + flags, + &p->progressSemaphore.gpuVA); + if (status != NVOS_STATUS_SUCCESS) { + nvAssert(!"Failed to map FIFO semaphore surface"); + goto fail; + } + } + + return TRUE; +fail: + FreeSemaSurface(p); + return FALSE; +} + +/* + * The size of the "progress tracker" portion of the pushbuffer. + * + * We use one set of progress tracker methods for every two GPFIFO entries (one + * GPFIFO entry is for the main pushbuffer, the other is for the progress + * tracker methods). + */ +static inline NvU32 ProgressTrackerBufferSize(NvPushChannelPtr buffer) +{ + return __nvPushProgressTrackerEntrySize(buffer->pDevice) * + (buffer->numGpFifoEntries / 2); +} + +/* + * The size of the pushbuffer allocation, including all segments and GPFIFO + * entries. + */ +static inline NvU32 CalculateGPBufferSize(NvPushChannelPtr buffer) +{ + return __nvPushProgressTrackerOffset(buffer) + + ProgressTrackerBufferSize(buffer); +} + +/*! + * Set up an NvPushChannelSegmentRec's initial state based on the provided data + * + * \param segment Pointer to segment structure to initialize + * \param ptr CPU mapping to the base of the segment. + * \param gpuOffset GPU mapping of the base of the segment. + * \param size Size of the segment, in bytes. + */ +static void InitDmaSegment(NvPushChannelSegmentPtr segment, + void *ptr, + NvU64 gpuOffset, + NvU32 size) +{ + segment->base = (NvPushChannelUnion *)ptr; + segment->buffer = (NvPushChannelUnion *)ptr; + segment->sizeInBytes = size; + segment->freeDwords = size >> 2; + segment->gpuMapOffset = gpuOffset; + segment->putOffset = 0; +} + +/*! + * Set up the work submit token. RM will write this into the "error context + * DMA" at the offset we request. + */ +static NvBool RequestChidToken(NvPushChannelPtr p) +{ + NvPushDevicePtr pDevice = p->pDevice; + int deviceIndex; + + for (deviceIndex = 0; + deviceIndex < __nvPushGetNumDevices(pDevice); + deviceIndex++) { + + NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS notifParams = { 0 }; + NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS tokenParams = { 0 }; + NvU32 status; + + notifParams.index = NV_CHANNELGPFIFO_NOTIFICATION_TYPE__SIZE_1 + deviceIndex; + + status = nvPushImportRmApiControl(pDevice, + p->channelHandle[deviceIndex], + NVC36F_CTRL_CMD_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX, + ¬ifParams, + sizeof(notifParams)); + if (status != NVOS_STATUS_SUCCESS) { + return FALSE; + } + + /* + * Request the channel's "work submit token". This isn't actually used for + * anything but RM needs it to be called after the channel has been allocated, + * for reasons. + */ + status = nvPushImportRmApiControl(pDevice, + p->channelHandle[deviceIndex], + NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN, + &tokenParams, + sizeof(tokenParams)); + if (status != NVOS_STATUS_SUCCESS) { + return FALSE; + } + } + return TRUE; +} + +static NvBool BindAndScheduleChannel(NvPushDevicePtr pDevice, + NvU32 channelHandle, + NvU32 engineType) +{ + NVA06F_CTRL_BIND_PARAMS bindParams = { 0 }; + NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS scheduleParams = { 0 }; + NvBool ret; + + bindParams.engineType = engineType; + ret = nvPushImportRmApiControl(pDevice, + channelHandle, + NVA06F_CTRL_CMD_BIND, + &bindParams, + sizeof(bindParams)); + + if (ret != NVOS_STATUS_SUCCESS) { + nvPushImportLogError(pDevice, "Failed to bind the channel"); + return FALSE; + } + + scheduleParams.bEnable = NV_TRUE; + ret = nvPushImportRmApiControl(pDevice, + channelHandle, + NVA06F_CTRL_CMD_GPFIFO_SCHEDULE, + &scheduleParams, + sizeof(scheduleParams)); + + if (ret != NVOS_STATUS_SUCCESS) { + nvPushImportLogError(pDevice, + "Failed to schedule the channel"); + return FALSE; + } + + return TRUE; +} + +static NvBool AllocChannelObject( + NvPushChannelPtr buffer, + const NvPushAllocChannelParams *pParams, + NvU64 *pUsedHandleBitmask, + NvU64 gpuAddress) +{ + NvPushDevicePtr pDevice = buffer->pDevice; + NV_CHANNEL_ALLOC_PARAMS params = { 0 }; + unsigned int sd; + NvU32 userdMapHandle[NV_MAX_SUBDEVICES]; + NvU32 ret; + const NvU64 gpFifoOffset = gpuAddress + __nvPushGpFifoOffset(buffer); + int deviceIndex; + + for (deviceIndex = 0; + deviceIndex < __nvPushGetNumDevices(pDevice); + deviceIndex++) { + buffer->channelHandle[deviceIndex] = GetChannelHandle(pParams, pUsedHandleBitmask); + nvAssert(buffer->notifiers.errorCtxDma != 0); + + /* Open the DMA channel by allocating the CHANNEL_GPFIFO object */ + params.hObjectError = buffer->notifiers.errorCtxDma; + if (pDevice->subDevice[deviceIndex].gpuVASpaceObject != 0) { + params.hVASpace = pDevice->subDevice[deviceIndex].gpuVASpaceObject; + } else { + params.hObjectBuffer = pDevice->subDevice[deviceIndex].gpuVASpaceCtxDma; + } + // Offset is relative to the ctx dma + params.gpFifoOffset = gpFifoOffset; + + if (pDevice->hal.caps.allocateDoubleSizeGpFifo) { + // On Tegra, we have to allocate twice the GPFIFO size. This is because + // the kernel will add its own entries (max 2) for the kickoff for the + // pre-sync and post-sync fences. This means the max kickoff size is not + // actually buffer->numGpFifoEntries - 1, it's + // most likely buffer->numGpFifoEntries - 3. + // + // TODO: Tell the users the actual max kickoff size to avoid this + // WAR. NvRmTegraChannelGetMaxKickoffGpfifoCount() retrieves this piece + // of info on Tegra. Bug 2404063. + params.gpFifoEntries = buffer->numGpFifoEntries * 2; + } else { + params.gpFifoEntries = buffer->numGpFifoEntries; + } + + params.flags = 0; + if (pParams->difrPrefetch) { + params.flags |= DRF_DEF(OS04, + _FLAGS, + _SET_EVICT_LAST_CE_PREFETCH_CHANNEL, + _TRUE); + } + + if (pDevice->hal.caps.clientAllocatesUserD) { + if (pDevice->clientSli) { + params.hUserdMemory[0] = buffer->userD[deviceIndex].hMemory; + params.userdOffset[0] = 0; + } else { + for (sd = 0; sd < pDevice->numSubDevices; sd++) { + params.hUserdMemory[sd] = buffer->userD[0].hMemory; + params.userdOffset[sd] = 0; + } + } + userdMapHandle[deviceIndex] = buffer->userD[deviceIndex].hMemory; + } else { + userdMapHandle[deviceIndex] = buffer->channelHandle[deviceIndex]; + } + params.engineType = pParams->engineType; + if (pDevice->clientSli) { + params.subDeviceId = (1 << deviceIndex); + } + + if ((ret = nvPushImportRmApiAlloc(pDevice, + pDevice->subDevice[deviceIndex].deviceHandle, + buffer->channelHandle[deviceIndex], + pDevice->gpfifoClass, + ¶ms)) != NVOS_STATUS_SUCCESS) + { + nvPushImportLogError(pDevice, + "Push buffer object allocation failed: 0x%x (%s)", + ret, nvstatusToString(ret)); + buffer->channelHandle[deviceIndex] = 0; + return FALSE; + } + + if (!BindAndScheduleChannel(pDevice, + buffer->channelHandle[deviceIndex], + pParams->engineType)) { + return FALSE; + } + } + + for (sd = 0; sd < pDevice->numSubDevices; sd++) { + void *pUserD; + + deviceIndex = __nvPushGetDeviceIndex(pDevice, sd); + + // Map the DMA controls for each subdevice. + ret = nvPushImportRmApiMapMemory(pDevice, + pDevice->subDevice[sd].handle, + userdMapHandle[deviceIndex], + 0, + pDevice->userDSize, + &pUserD, + 0); + if (ret != NVOS_STATUS_SUCCESS) { + nvPushImportLogError(pDevice, + "Push buffer mapping failed: 0x%x (%s)", + ret, nvstatusToString(ret)); + return FALSE; + } + + buffer->control[sd] = pUserD; + } + + return TRUE; +} + +/* + * It might be nice to suballocate these rather + * than create a separate RM allocation for each channel. + */ +static NvBool nvDmaAllocUserD( + NvPushChannelPtr p, + const NvPushAllocChannelParams *pParams, + NvU64 *pUsedHandleBitmask) +{ + NvPushDevicePtr pDevice = p->pDevice; + int deviceIndex; + + if (!pDevice->hal.caps.clientAllocatesUserD) { + return TRUE; + } + + for (deviceIndex = 0; + deviceIndex < __nvPushGetNumDevices(pDevice); + deviceIndex++) { + NV_MEMORY_ALLOCATION_PARAMS memAllocParams = { 0 }; + const NvU32 attr = + DRF_DEF(OS32, _ATTR, _LOCATION, _VIDMEM) | + DRF_DEF(OS32, _ATTR, _PAGE_SIZE, _4KB) | + DRF_DEF(OS32, _ATTR, _COHERENCY, _UNCACHED); + const NvU32 flags = + NVOS32_ALLOC_FLAGS_ALIGNMENT_FORCE | + NVOS32_ALLOC_FLAGS_PERSISTENT_VIDMEM; + NvU32 ret; + + NvU32 hMemory = GetChannelHandle(pParams, pUsedHandleBitmask); + + memAllocParams.owner = pDevice->clientHandle; + memAllocParams.type = NVOS32_TYPE_DMA; + memAllocParams.size = pDevice->userDSize; + memAllocParams.attr = attr; + memAllocParams.flags = flags; + memAllocParams.alignment = pDevice->userDSize; + + ret = nvPushImportRmApiAlloc(pDevice, + pDevice->subDevice[deviceIndex].deviceHandle, + hMemory, + NV01_MEMORY_LOCAL_USER, + &memAllocParams); + if (ret != NV_OK) { + return FALSE; + } + + p->userD[deviceIndex].hMemory = hMemory; + } + + return TRUE; +} + +int nvPushGetSupportedClassIndex( + NvPushDevicePtr pDevice, + const void *pClassTable, + size_t classTableStride, + size_t classTableLength) +{ + unsigned int i, j; + + for (i = 0; i < classTableLength; i++) { + + const NvU8 *bytes = (const NvU8 *)pClassTable; + const size_t byteOffset = i * classTableStride; + const NvPushSupportedClass *pClass = + (const NvPushSupportedClass *) (bytes + byteOffset); + + if (nvPushIsAModel(pDevice)) { + if (pDevice->amodelConfig == pClass->amodelConfig) { + return i; + } + continue; + } + + for (j = 0; j < pDevice->numClasses; j++) { + if (pClass->classNumber == pDevice->supportedClasses[j]) { + return i; + } + } + } + return -1; +} + +static NvBool GetChannelClassAndUserDSize( + NvPushDevicePtr pDevice, + const NvPushAllocDeviceParams *pParams) +{ + const struct { + NvPushSupportedClass base; + size_t gpFifoSize; + } gpFifoDmaClasses[] = { + { + { HOPPER_CHANNEL_GPFIFO_A, + NV_AMODEL_HOPPER }, + sizeof(HopperAControlGPFifo) + }, + { + { AMPERE_CHANNEL_GPFIFO_A, + NV_AMODEL_ADA }, + sizeof(AmpereAControlGPFifo) + }, + { + { AMPERE_CHANNEL_GPFIFO_A, + NV_AMODEL_AMPERE }, + sizeof(AmpereAControlGPFifo) + }, + { + { TURING_CHANNEL_GPFIFO_A, + NV_AMODEL_TURING }, + sizeof(TuringAControlGPFifo) + }, + { + { VOLTA_CHANNEL_GPFIFO_A, + NV_AMODEL_VOLTA }, + sizeof(VoltaAControlGPFifo) + }, + { + { PASCAL_CHANNEL_GPFIFO_A, + NV_AMODEL_PASCAL }, + sizeof(PascalAControlGPFifo) + }, + { + { MAXWELL_CHANNEL_GPFIFO_A, + NV_AMODEL_MAXWELL }, + sizeof(MaxwellAControlGPFifo) + }, + { + { KEPLER_CHANNEL_GPFIFO_C, + NV_AMODEL_KEPLER_SM35 }, + sizeof(KeplerCControlGPFifo) + }, + { + { KEPLER_CHANNEL_GPFIFO_B, + NV_AMODEL_KEPLER }, + sizeof(KeplerBControlGPFifo) + }, + + }; + + int i; + + i = nvPushGetSupportedClassIndex(pDevice, gpFifoDmaClasses, + sizeof(gpFifoDmaClasses[0]), + ARRAY_LEN(gpFifoDmaClasses)); + if (i == -1) { + return FALSE; + } + + pDevice->gpfifoClass = gpFifoDmaClasses[i].base.classNumber; + pDevice->userDSize = gpFifoDmaClasses[i].gpFifoSize; + return TRUE; +} + +/* + * Query GPU<->CPU coherency. In particular, *pCoherent is set to TRUE when + * the GPU is capable of accessing CPU-cached system memory coherently with + * respect to CPU accesses. + * + * For surfaces with CPU read/write or CPU read-mostly such as notifiers: + * If *pCoherent is TRUE: + * - create CPU mappings with COHERENCY_WRITE_BACK + * - create GPU mappings with CACHE_SNOOP_ENABLE + * If *pCoherent is FALSE: + * - create CPU mappings with COHERENCY_UNCACHED + * - create GPU mappings with CACHE_SNOOP_DISABLE + * + * (CPU write-mostly surfaces such as the pushbuffer always use WRITE_COMBINED + * memory.) + * + * Note we only query on the first subdevice and assume the other subdevices + * are the same. + */ +static NvBool GetCoherenceFlags( + NvPushChannelPtr pChannel, + NvBool *pCoherent) +{ + NvPushDevicePtr pDevice = pChannel->pDevice; + NV2080_CTRL_BUS_GET_INFO_PARAMS busInfo = { 0 }; + struct { + NV2080_CTRL_BUS_INFO coherentFlags; + } busInfoList; + + NvU32 ret; + + NVMISC_MEMSET(&busInfoList, 0, sizeof(busInfoList)); + busInfoList.coherentFlags.index = + NV2080_CTRL_BUS_INFO_INDEX_COHERENT_DMA_FLAGS; + + busInfo.busInfoListSize = sizeof(busInfoList) / + sizeof(NV2080_CTRL_BUS_INFO); + busInfo.busInfoList = NV_PTR_TO_NvP64(&busInfoList); + + ret = nvPushImportRmApiControl(pDevice, + pDevice->subDevice[0].handle, + NV2080_CTRL_CMD_BUS_GET_INFO, + &busInfo, sizeof(busInfo)); + + if (ret != NVOS_STATUS_SUCCESS) { + return FALSE; + } + + *pCoherent = + FLD_TEST_DRF(2080_CTRL_BUS_INFO, _COHERENT_DMA_FLAGS, _GPUGART, _TRUE, + busInfoList.coherentFlags.data); + return TRUE; +} + +static NvBool TryAllocAndMapPushbuffer( + NvPushChannelPtr pChannel, + const NvU32 allocFlags, + const NvU32 mapFlags, + const NvU32 limit, + void **pCpuAddress, + NvU64 *pGpuAddress) +{ + NvU32 ret; + NvU64 localLimit; + NvU64 size = limit + 1; + void *cpuAddress = NULL; + NvU64 gpuAddress = 0; + NvPushDevicePtr pDevice = pChannel->pDevice; + int deviceIndex; + NvBool vaAlloc[NV_MAX_SUBDEVICES] = { 0 }; + NvBool vaMap[NV_MAX_SUBDEVICES] = { 0 }; + NvBool surfaceAlloc = FALSE; + + for (deviceIndex = 0; + deviceIndex < __nvPushGetNumDevices(pDevice); + deviceIndex++) { + NV_MEMORY_ALLOCATION_PARAMS vaParams = { 0 }; + + vaParams.owner = 0x70757368; + vaParams.type = NVOS32_TYPE_DMA; + vaParams.flags = + NVOS32_ALLOC_FLAGS_MEMORY_HANDLE_PROVIDED | + NVOS32_ALLOC_FLAGS_VIRTUAL; + vaParams.size = size; + vaParams.hVASpace = pDevice->subDevice[deviceIndex].gpuVASpaceObject; + + if (deviceIndex == 0) { + /* For the first device, RM assigns a virtual address. */ + if (pChannel->pDevice->hal.caps.extendedBase) { + /* + * Force the virtual mapping to be naturally aligned. + * This ensures that the allocation cannot cross a 40-bit + * boundary, so we can initialize the higher bits of the VA + * with the PB_EXTENDED_BASE_OPERAND GPFIFO command once at + * init time and not worry about it being able to change + * between any two GPFIFO entries. + */ + vaParams.flags |= NVOS32_ALLOC_FLAGS_ALIGNMENT_FORCE; + vaParams.alignment = size; + ROUNDUP_POW2_U64(vaParams.alignment); + } + } else { + /* For subsequent devices, use the same virtual address. */ + vaParams.flags |= NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE; + nvAssert(gpuAddress != 0); + vaParams.offset = gpuAddress; + } + + ret = nvPushImportRmApiAlloc( + pDevice, + pDevice->subDevice[deviceIndex].deviceHandle, + pChannel->pushbufferVAHandle[deviceIndex], + NV50_MEMORY_VIRTUAL, + &vaParams); + + if (ret != NVOS_STATUS_SUCCESS) { + goto fail; + } + vaAlloc[deviceIndex] = TRUE; + + if (deviceIndex == 0) { + gpuAddress = vaParams.offset; + nvAssert(vaParams.size >= size); + /* The VA allocation may have been bloated to a larger size, to + * align with the page size. Adjust to ensure that we allocate a + * surface of at least that size, or else attempts to map it will + * fail. */ + size = vaParams.size; + } else { + nvAssert(gpuAddress == vaParams.offset); + nvAssert(vaParams.size == size); + } + } + + /* Allocate a single surface in system memory for the pushbuffer. */ + localLimit = size - 1; + ret = nvPushImportRmApiAllocMemory64( + pDevice, + pDevice->subDevice[0].deviceHandle, + pChannel->pushbufferHandle, + NV01_MEMORY_SYSTEM, + allocFlags, + &cpuAddress, + &localLimit); + + if (ret != NVOS_STATUS_SUCCESS) { + goto fail; + } + nvAssert(localLimit + 1 >= size); + surfaceAlloc = TRUE; + + for (deviceIndex = 0; + deviceIndex < __nvPushGetNumDevices(pDevice); + deviceIndex++) { + NvU64 mapOffset = 0; + + ret = nvPushImportRmApiMapMemoryDma( + pDevice, + pDevice->subDevice[deviceIndex].deviceHandle, + pChannel->pushbufferVAHandle[deviceIndex], + pChannel->pushbufferHandle, + 0, + size, + mapFlags, + &mapOffset); + + if (ret != NVOS_STATUS_SUCCESS) { + goto fail; + } + vaMap[deviceIndex] = TRUE; + /* mapMemoryDma takes in a relative offset but assigns an absolute VA */ + nvAssert(mapOffset == gpuAddress); + } + + /* success */ + *pCpuAddress = cpuAddress; + *pGpuAddress = gpuAddress; + return TRUE; + +fail: + for (deviceIndex = __nvPushGetNumDevices(pDevice) - 1; + deviceIndex >= 0; + deviceIndex--) { + if (vaMap[deviceIndex]) { + ret = nvPushImportRmApiUnmapMemoryDma(pDevice, + pDevice->subDevice[deviceIndex].deviceHandle, + pChannel->pushbufferVAHandle[deviceIndex], + pChannel->pushbufferHandle, + 0, + gpuAddress); + nvAssert(ret == NVOS_STATUS_SUCCESS); + vaMap[deviceIndex] = FALSE; + } + if (vaAlloc[deviceIndex]) { + ret = nvPushImportRmApiFree(pDevice, + pDevice->subDevice[deviceIndex].deviceHandle, + pChannel->pushbufferVAHandle[deviceIndex]); + nvAssert(ret == NVOS_STATUS_SUCCESS); + vaAlloc[deviceIndex] = FALSE; + } + }; + + if (surfaceAlloc) { + ret = nvPushImportRmApiFree(pDevice, + pDevice->subDevice[0].deviceHandle, + pChannel->pushbufferHandle); + nvAssert(ret == NVOS_STATUS_SUCCESS); + } + + return FALSE; +} + +static NvBool AllocPushbuffer( + NvPushChannelPtr pChannel, + const NvPushAllocChannelParams *pParams, + NvU64 *pUsedHandleBitmask, + void **pCpuAddress, + NvU64 *pGpuAddress) +{ + const NvU32 size = CalculateGPBufferSize(pChannel); + NvU32 limit = size - 1; + int deviceIndex; + + pChannel->pushbufferHandle = GetChannelHandle(pParams, pUsedHandleBitmask); + for (deviceIndex = 0; + deviceIndex < __nvPushGetNumDevices(pChannel->pDevice); + deviceIndex++) { + pChannel->pushbufferVAHandle[deviceIndex] = + GetChannelHandle(pParams, pUsedHandleBitmask); + } + + if (TryAllocAndMapPushbuffer( + pChannel, + DRF_DEF(OS02, _FLAGS, _PHYSICALITY, _NONCONTIGUOUS) | + DRF_DEF(OS02, _FLAGS, _COHERENCY, _WRITE_COMBINE), + DRF_DEF(OS46, _FLAGS, _CACHE_SNOOP, _DISABLE), + limit, + pCpuAddress, + pGpuAddress)) { + return TRUE; + } + + pChannel->pushbufferHandle = 0; + NVMISC_MEMSET(pChannel->pushbufferVAHandle, 0, sizeof(pChannel->pushbufferVAHandle)); + return FALSE; +} + +/*! + * Free resources allocated in AllocUserMode(). + */ +static void FreeUserMode( + NvPushDevicePtr pDevice) +{ + NvU32 sd; + + for (sd = 0; sd < pDevice->numSubDevices; sd++) { + + if (pDevice->subDevice[sd].pUserMode != NULL) { + nvPushImportRmApiUnmapMemory( + pDevice, + pDevice->subDevice[sd].handle, + pDevice->subDevice[sd].hUserMode, + pDevice->subDevice[sd].pUserMode, + 0 /* flags */); + pDevice->subDevice[sd].pUserMode = NULL; + } + + if (pDevice->subDevice[sd].hUserMode != 0) { + nvPushImportRmApiFree( + pDevice, + pDevice->subDevice[sd].handle, + pDevice->subDevice[sd].hUserMode); + pDevice->subDevice[sd].hUserMode = 0; + } + } +} + +/*! + * Allocate and map the "usermode" object on each subdevice, supported on GV100 + * and up. This mapping exposes registers considered safe for userspace to + * access directly. Most importantly, it contains the "doorbell" register + * which we use to notify HOST that we've updated GP_PUT so that it will fetch + * work for the channel. + */ +static NvBool AllocUserMode( + NvPushDevicePtr pDevice, + const NvPushAllocDeviceParams *pParams, + NvU64 *pUsedHandleBitmask) +{ + unsigned int sd; + + static const NvPushSupportedClass userModeClasses[] = { + { HOPPER_USERMODE_A, + NV_AMODEL_HOPPER }, + { VOLTA_USERMODE_A, + NV_AMODEL_VOLTA }, + }; + int i; + + if (!pDevice->hal.caps.clientAllocatesUserD) { + return TRUE; + } + + i = nvPushGetSupportedClassIndex(pDevice, userModeClasses, + sizeof(userModeClasses[0]), + ARRAY_LEN(userModeClasses)); + if (i == -1) { + return FALSE; + } + + for (sd = 0; sd < pDevice->numSubDevices; sd++) { + NvU32 ret; + void *allocParams = NULL; + + NV_HOPPER_USERMODE_A_PARAMS hopperParams = { 0 }; + if (userModeClasses[i].classNumber != VOLTA_USERMODE_A) { + allocParams = &hopperParams; + // The BAR1 mapping is used for (faster and more efficient) writes + // to perform work submission, but can't be used for reads. + // If we ever want to read from the USERMODE region (e.g., to read + // PTIMER) then we need a second mapping. + hopperParams.bBar1Mapping = NV_TRUE; + } + + pDevice->subDevice[sd].hUserMode = + GetDeviceHandle(pParams, pUsedHandleBitmask); + + ret = nvPushImportRmApiAlloc( + pDevice, + pDevice->subDevice[sd].handle, + pDevice->subDevice[sd].hUserMode, + userModeClasses[i].classNumber, + allocParams); + + if (ret != NVOS_STATUS_SUCCESS) { + pDevice->subDevice[sd].hUserMode = 0; + goto fail; + } + + ret = nvPushImportRmApiMapMemory( + pDevice, + pDevice->subDevice[sd].handle, + pDevice->subDevice[sd].hUserMode, + 0, /* offset */ + NVC361_NV_USERMODE__SIZE, + &pDevice->subDevice[sd].pUserMode, + 0 /* flags */); + + if (ret != NVOS_STATUS_SUCCESS) { + goto fail; + } + } + + return TRUE; + +fail: + FreeUserMode(pDevice); + return FALSE; +} + +static void CheckCaps(NvPushDevicePtr pDevice) +{ + int deviceIndex; + + pDevice->hostLBoverflowBug1667921 = FALSE; + + for (deviceIndex = 0; + deviceIndex < __nvPushGetNumDevices(pDevice); + deviceIndex++) { + NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS fifoCapsParams = { 0 }; + NvU32 ret; + + ret = nvPushImportRmApiControl(pDevice, + pDevice->subDevice[deviceIndex].deviceHandle, + NV0080_CTRL_CMD_FIFO_GET_CAPS_V2, + &fifoCapsParams, + sizeof(fifoCapsParams)); + if (ret != NVOS_STATUS_SUCCESS) { + nvAssert(!"Failed to determine chip fifo capabilities"); + return; + } + + pDevice->hostLBoverflowBug1667921 |= + !!NV0080_CTRL_FIFO_GET_CAP(fifoCapsParams.capsTbl, + NV0080_CTRL_FIFO_CAPS_HAS_HOST_LB_OVERFLOW_BUG_1667921); + } +} + + +static void FreeNotifiers( + NvPushChannelPtr pChannel) +{ + NvPushDevicePtr pDevice = pChannel->pDevice; + + if (pChannel->notifiers.errorCtxDma != 0) { + nvPushImportRmApiFree(pDevice, + pDevice->clientHandle, + pChannel->notifiers.errorCtxDma); + pChannel->notifiers.errorCtxDma = 0; + + } + + if (pChannel->notifiers.gpuAddress != 0) { + int deviceIndex; + for (deviceIndex = __nvPushGetNumDevices(pDevice) - 1; + deviceIndex >= 0; + deviceIndex--) { + nvPushImportRmApiUnmapMemoryDma(pDevice, + pDevice->subDevice[deviceIndex].deviceHandle, + pDevice->subDevice[deviceIndex].gpuVASpaceCtxDma, + pChannel->notifiers.memoryHandle, + 0, + pChannel->notifiers.gpuAddress); + } + pChannel->notifiers.gpuAddress = 0; + } + + if (pChannel->notifiers.memoryHandle != 0) { + nvPushImportRmApiFree(pDevice, + pDevice->subDevice[0].deviceHandle, + pChannel->notifiers.memoryHandle); + pChannel->notifiers.memoryHandle = 0; + } +} + +/* + * Allocate enough notifier memory to store: + * - numNotifiers host driver requested NvNotifications, per subDevice + * - NV_PUSH_NUM_INTERNAL_NOTIFIERS NvNotifications, per channel + */ +static NvBool AllocNotifiers( + NvPushChannelPtr pChannel, + const NvPushAllocChannelParams *pParams, + NvBool coherent, + NvU64 *pUsedHandleBitmask) +{ + NvPushDevicePtr pDevice = pChannel->pDevice; + const NvU32 size = + (((pParams->numNotifiers * pDevice->numSubDevices) + + NV_PUSH_NUM_INTERNAL_NOTIFIERS) * + sizeof(NvNotification)); + NV_CONTEXT_DMA_ALLOCATION_PARAMS ctxdmaParams = { 0 }; + + NvU64 limit = size - 1; + int deviceIndex; + NvU32 ret; + NvU32 allocFlags, gpuMapFlags; + + /* + * The host-driver specified number of notifiers must not collide + * with the reserved bit we use to indicate internal notifiers. + */ + if (pParams->numNotifiers & NV_PUSH_NOTIFIER_INTERNAL_BIT) { + return FALSE; + } + + pChannel->notifiers.num = pParams->numNotifiers; + pChannel->notifiers.memoryHandle = + GetChannelHandle(pParams, pUsedHandleBitmask); + + allocFlags = DRF_DEF(OS02,_FLAGS,_PHYSICALITY,_NONCONTIGUOUS), + gpuMapFlags = 0; + if (coherent) { + allocFlags = FLD_SET_DRF(OS02, _FLAGS, _COHERENCY, _WRITE_BACK, allocFlags); + gpuMapFlags = FLD_SET_DRF(OS46, _FLAGS, _CACHE_SNOOP, _ENABLE, gpuMapFlags); + } else { + allocFlags = FLD_SET_DRF(OS02, _FLAGS, _COHERENCY, _UNCACHED, allocFlags); + gpuMapFlags = FLD_SET_DRF(OS46, _FLAGS, _CACHE_SNOOP, _DISABLE, gpuMapFlags); + } + + ret = nvPushImportRmApiAllocMemory64( + pDevice, + pDevice->subDevice[0].deviceHandle, + pChannel->notifiers.memoryHandle, + NV01_MEMORY_SYSTEM, + allocFlags, + (void **)&pChannel->notifiers.cpuAddress, + &limit); + + if (ret != NVOS_STATUS_SUCCESS) { + pChannel->notifiers.memoryHandle = 0; + goto fail; + } + + /* Map the memory into the GPU's VA space. */ + + for (deviceIndex = 0; + deviceIndex < __nvPushGetNumDevices(pDevice); + deviceIndex++) { + NvU32 mapFlags = gpuMapFlags; + NvU64 gpuAddress; + if (deviceIndex == 0) { + /* For the first device, RM assigns a virtual address. */ + gpuAddress = 0; + } else { + /* For subsequent devices, use the same virtual address. */ + mapFlags = FLD_SET_DRF(OS46, _FLAGS, _DMA_OFFSET_FIXED, _TRUE, + mapFlags); + gpuAddress = pChannel->notifiers.gpuAddress; + nvAssert(gpuAddress != 0); + } + ret = nvPushImportRmApiMapMemoryDma( + pDevice, + pDevice->subDevice[deviceIndex].deviceHandle, + pDevice->subDevice[deviceIndex].gpuVASpaceCtxDma, + pChannel->notifiers.memoryHandle, + 0, /* offset */ + size, + mapFlags, + &gpuAddress); + + if (ret != NVOS_STATUS_SUCCESS) { + goto fail; + } + + if (deviceIndex == 0) { + pChannel->notifiers.gpuAddress = gpuAddress; + } else { + nvAssert(pChannel->notifiers.gpuAddress == gpuAddress); + } + } + + /* Create the internal notifier ctxDma. */ + + pChannel->notifiers.errorCtxDma = + GetChannelHandle(pParams, pUsedHandleBitmask); + + ctxdmaParams.hMemory = pChannel->notifiers.memoryHandle; + ctxdmaParams.flags = DRF_DEF(OS03, _FLAGS, _MAPPING, _KERNEL) | + DRF_DEF(OS03, _FLAGS, _HASH_TABLE, _DISABLE); + /* the internal notifiers are at the start of the memory */ + ctxdmaParams.offset = 0; + ctxdmaParams.limit = (NV_PUSH_NUM_INTERNAL_NOTIFIERS * + sizeof(NvNotification)) - 1; + + ret = nvPushImportRmApiAlloc(pDevice, + pDevice->subDevice[0].deviceHandle, + pChannel->notifiers.errorCtxDma, + NV01_CONTEXT_DMA, + &ctxdmaParams); + + if (ret != NVOS_STATUS_SUCCESS) { + pChannel->notifiers.errorCtxDma = 0; + goto fail; + } + + /* + * Initialize the error notifier; note that there is only one + * error notifier shared by all subdevices, so we specify master as the + * subDeviceMask. + */ + nvPushInitWaitForNotifier(pChannel, + NV_PUSH_ERROR_NOTIFIER_INDEX, + NV_PUSH_SUBDEVICE_MASK_PRIMARY); + + return TRUE; + +fail: + FreeNotifiers(pChannel); + return FALSE; +} + +static NvU32 GetExtendedBase(NvU64 offset) +{ + return NvU64_HI32(offset) >> 8; +} + +static void InitGpFifoExtendedBase( + NvPushChannelPtr pChannel) +{ + const NvU64 pbBase = pChannel->main.gpuMapOffset; + const NvU32 extendedBase = GetExtendedBase(pbBase); + NvU32 *gpPointer = &(pChannel->gpfifo[pChannel->gpPutOffset*2]); + NvU32 i; + + if (!pChannel->pDevice->hal.caps.extendedBase) { + nvAssert(extendedBase == 0); + return; + } + + /* + * Because of the natural VA alignment specified when allocating the + * pushbuffer, all parts of the pushbuffer surface should be in the same + * 40-bit region. + */ + nvAssert(GetExtendedBase(pChannel->main.gpuMapOffset) == + GetExtendedBase(pChannel->progressTracker.gpuMapOffset)); + nvAssert(GetExtendedBase(pChannel->main.gpuMapOffset + + pChannel->main.sizeInBytes - 1) == + GetExtendedBase(pChannel->main.gpuMapOffset)); + nvAssert(GetExtendedBase(pChannel->progressTracker.gpuMapOffset + + pChannel->progressTracker.sizeInBytes - 1) == + GetExtendedBase(pChannel->progressTracker.gpuMapOffset)); + + /* Set the "extended base" for all subsequent methods */ + gpPointer[0] = DRF_NUM(C86F, _GP_ENTRY0, _PB_EXTENDED_BASE_OPERAND, extendedBase); + gpPointer[1] = DRF_DEF(C86F, _GP_ENTRY1, _OPCODE, _SET_PB_SEGMENT_EXTENDED_BASE); + gpPointer += 2; + + /* Pad out with NOP GPFIFO methods so everything remains aligned. */ + for (i = 1; i < NV_PUSH_NUM_GPFIFO_ENTRIES_PER_KICKOFF; i++) { + gpPointer[0] = 0; + gpPointer[1] = DRF_DEF(C86F, _GP_ENTRY1, _OPCODE, _NOP); + gpPointer += 2; + } + + pChannel->gpPutOffset += NV_PUSH_NUM_GPFIFO_ENTRIES_PER_KICKOFF; + +} + +NvBool nvPushAllocChannel( + const NvPushAllocChannelParams *pParams, + NvPushChannelPtr buffer) +{ + NvPushDevicePtr pDevice; + void *cpuAddress = NULL; + NvU64 gpuAddress = 0; + NvU64 usedHandleBitmask = 0; + NvBool coherent = FALSE; + + NVMISC_MEMSET(buffer, 0, sizeof(*buffer)); + + pDevice = pParams->pDevice; + + buffer->pDevice = pDevice; + buffer->logNvDiss = pParams->logNvDiss; + buffer->noTimeout = pParams->noTimeout; + buffer->ignoreChannelErrors = pParams->ignoreChannelErrors; + + buffer->currentSubDevMask = NV_PUSH_SUBDEVICE_MASK_ALL; + + /* + * Assign main.sizeInBytes early, because the rest of + * initialization relies on knowing the main pushbuffer size. + * Note this must fit in NV_PUSH_PROGRESS_TRACKER_SEMAPHORE_GET, + * which stores dwords. + */ + nvAssert((DRF_MASK(NV_PUSH_PROGRESS_TRACKER_SEMAPHORE_GET) * 4) > + pParams->pushBufferSizeInBytes); + buffer->main.sizeInBytes = pParams->pushBufferSizeInBytes; + + /* + * Compute numGpFifoEntries. There are several constraints: + * + * - We make numGpFifoEntries 1/64th the size of the main + * pushbuffer. The maximum pushbuffer size is 1048572, and we + * consume 2 gpFifo entries per kickoff. This works out to be + * 128 bytes of pushbuffer (32 dwords) per kickoff, before we + * are gpFifo-limited. + * + * - Per dev_pbdma.ref, "The number of GP entries in the circular + * buffer is always a power of 2." So, round up to the next + * power of two. + * + * - Because we consume 2 gpFifo entries per kickoff + * (NV_PUSH_NUM_GPFIFO_ENTRIES_PER_KICKOFF), we also align to a + * multiple of 2. This should be guaranteed by the power of 2 + * check. + * + * - numGpFifoEntries must fit in + * NV_PUSH_PROGRESS_TRACKER_SEMAPHORE_GP_GET so that the + * progress tracker semaphore releases can report the consumed + * gpFifo entry. The distribution of bits in + * NV_PUSH_PROGRESS_TRACKER_SEMAPHORE should ensure this is + * satisfied. + */ + + buffer->numGpFifoEntries = pParams->pushBufferSizeInBytes / 64; + + buffer->numGpFifoEntries = nvNextPow2_U32(buffer->numGpFifoEntries); + + nvAssert((buffer->numGpFifoEntries % + NV_PUSH_NUM_GPFIFO_ENTRIES_PER_KICKOFF) == 0); + + nvAssert((DRF_MASK(NV_PUSH_PROGRESS_TRACKER_SEMAPHORE_GP_GET) * 2) > + buffer->numGpFifoEntries); + + if (!GetCoherenceFlags(buffer, &coherent)) { + goto failed; + } + + if (!AllocNotifiers(buffer, pParams, coherent, &usedHandleBitmask)) { + nvPushImportLogError(pDevice, + "Failed to allocate notification memory."); + goto failed; + } + + /* Only allocate memory for one pushbuffer. All subdevices will share */ + if (!AllocPushbuffer(buffer, + pParams, + &usedHandleBitmask, + &cpuAddress, + &gpuAddress)) { + nvPushImportLogError(pDevice, + "Push buffer DMA allocation failed"); + goto failed; + } + + /* First the "main" pushbuffer */ + InitDmaSegment(&buffer->main, + cpuAddress, + gpuAddress, + pParams->pushBufferSizeInBytes); + /* Next the GPFIFO */ + buffer->gpfifo = + (NvU32 *)((char *)cpuAddress + __nvPushGpFifoOffset(buffer)); + buffer->gpPutOffset = 0; + /* Next the "progressTracker" */ + InitDmaSegment(&buffer->progressTracker, + (char *)cpuAddress + __nvPushProgressTrackerOffset(buffer), + gpuAddress + __nvPushProgressTrackerOffset(buffer), + ProgressTrackerBufferSize(buffer)); + + if (!nvDmaAllocUserD(buffer, pParams, &usedHandleBitmask)) { + goto failed; + } + + if (!AllocChannelObject(buffer, pParams, + &usedHandleBitmask, gpuAddress)) { + goto failed; + } + + if (pDevice->hal.caps.clientAllocatesUserD && + !RequestChidToken(buffer)) { + goto failed; + } + + if (!AllocSemaSurface(buffer, pParams, coherent, &usedHandleBitmask)) { + goto failed; + } + +#if defined(DEBUG) + if (buffer->logNvDiss) { + nvPushImportLogNvDiss(buffer, "nvdiss: encoding 2\n"); + } +#endif /* DEBUG */ + + InitGpFifoExtendedBase(buffer); + + if (!__nvPushTestPushBuffer(buffer)) { + goto failed; + } + + buffer->initialized = TRUE; + + return TRUE; + +failed: + nvPushFreeChannel(buffer); + return FALSE; +} + +/*! + * Free resources allocated by AllocChannel(). + */ +void nvPushFreeChannel(NvPushChannelPtr buffer) +{ + NvPushDevicePtr pDevice = buffer->pDevice; + unsigned int sd; + int deviceIndex; + + if (pDevice == NULL) { + goto done; + } + + /* Unmap pushbuffer DMA controls */ + for (sd = 0; sd < pDevice->numSubDevices; sd++) { + NvU32 userdMapHandle; + + deviceIndex = __nvPushGetDeviceIndex(pDevice, sd); + if (pDevice->hal.caps.clientAllocatesUserD) { + userdMapHandle = buffer->userD[deviceIndex].hMemory; + } else { + userdMapHandle = buffer->channelHandle[deviceIndex]; + } + + if (buffer->control[sd]) { + nvPushImportRmApiUnmapMemory(pDevice, + pDevice->subDevice[sd].handle, + userdMapHandle, + buffer->control[sd], + 0); + buffer->control[sd] = NULL; + } + } + + for (deviceIndex = __nvPushGetNumDevices(pDevice) - 1; + deviceIndex >= 0; + deviceIndex--) { + if (buffer->channelHandle[deviceIndex] != 0) { + nvPushImportRmApiFree(pDevice, + pDevice->subDevice[deviceIndex].deviceHandle, + buffer->channelHandle[deviceIndex]); + buffer->channelHandle[deviceIndex] = 0; + } + + if (buffer->userD[deviceIndex].hMemory != 0) { + nvPushImportRmApiFree(pDevice, + pDevice->subDevice[deviceIndex].deviceHandle, + buffer->userD[deviceIndex].hMemory); + buffer->userD[deviceIndex].hMemory = 0; + } + + if (buffer->pushbufferVAHandle[deviceIndex] != 0) { + nvPushImportRmApiFree(pDevice, + pDevice->subDevice[deviceIndex].deviceHandle, + buffer->pushbufferVAHandle[deviceIndex]); + buffer->pushbufferVAHandle[deviceIndex] = 0; + } + } + + if (buffer->pushbufferHandle != 0) { + nvPushImportRmApiFree(pDevice, + pDevice->subDevice[0].deviceHandle, + buffer->pushbufferHandle); + buffer->pushbufferHandle = 0; + } + + FreeNotifiers(buffer); + + FreeSemaSurface(buffer); + +done: + NVMISC_MEMSET(buffer, 0, sizeof(*buffer)); +} + +NvBool nvPushAllocDevice( + const NvPushAllocDeviceParams *pParams, + NvPushDevicePtr pDevice) +{ + unsigned int sd; + NvU64 usedHandleBitmask = 0; + + NVMISC_MEMSET(pDevice, 0, sizeof(*pDevice)); + + pDevice->hostDevice = pParams->hostDevice; + pDevice->pImports = pParams->pImports; + pDevice->numSubDevices = pParams->numSubDevices; + pDevice->clientSli = pParams->clientSli; + pDevice->clientHandle = pParams->clientHandle; + + pDevice->numClasses = pParams->numClasses; + pDevice->supportedClasses = pParams->supportedClasses; + + for (sd = 0; sd < pParams->numSubDevices; sd++) { + pDevice->subDevice[sd].handle = pParams->subDevice[sd].handle; + pDevice->subDevice[sd].deviceHandle = pParams->subDevice[sd].deviceHandle; + pDevice->subDevice[sd].gpuVASpaceObject = pParams->subDevice[sd].gpuVASpaceObject; + pDevice->subDevice[sd].gpuVASpaceCtxDma = pParams->subDevice[sd].gpuVASpace; + } + + if (pParams->amodel.config != NV_AMODEL_NONE) { + nvAssert(!"Ignoring AModel configuration on non-XAMODEL build"); + } + pDevice->amodelConfig = pParams->amodel.config; + + CheckCaps(pDevice); + + if (!GetChannelClassAndUserDSize(pDevice, pParams)) { + nvPushImportLogError(pDevice, + "No supported command buffer format found"); + goto fail; + } + + if (!__nvPushGetHal(pParams, pDevice->gpfifoClass, &pDevice->hal)) { + nvPushImportLogError(pDevice, "No push buffer implementation found."); + goto fail; + } + + if (!AllocUserMode(pDevice, pParams, &usedHandleBitmask)) { + nvPushImportLogError(pDevice, + "Unable to allocate push buffer controls."); + goto fail; + } + + + return TRUE; + +fail: + nvPushFreeDevice(pDevice); + + return FALSE; +} + +void nvPushFreeDevice( + NvPushDevicePtr pDevice) +{ + FreeUserMode(pDevice); + + NVMISC_MEMSET(pDevice, 0, sizeof(*pDevice)); +} diff --git a/src/common/unix/nvidia-push/src/nvidia-push.c b/src/common/unix/nvidia-push/src/nvidia-push.c new file mode 100644 index 000000000..ae1931005 --- /dev/null +++ b/src/common/unix/nvidia-push/src/nvidia-push.c @@ -0,0 +1,1173 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + + + +#include "nvidia-push-init.h" +#include "nvidia-push-methods.h" +#include "nvidia-push-utils.h" +#include "nvidia-push-priv.h" +#include "nvidia-push-priv-imports.h" + +#include "nvos.h" +#include "nv_assert.h" +#include "nvSemaphoreCommon.h" + +#include "class/cl2080.h" // NV2080_SUBDEVICE_NOTIFICATION_STATUS_DONE_SUCCESS + +#include "class/cla16f.h" // KEPLER_CHANNEL_GPFIFO_B +#include "class/cla26f.h" // KEPLER_CHANNEL_GPFIFO_C +#include "class/clb06f.h" // MAXWELL_CHANNEL_GPFIFO_A +#include "class/clc06f.h" // PASCAL_CHANNEL_GPFIFO_A +#include "class/clc36f.h" // VOLTA_CHANNEL_GPFIFO_A +#include "class/clc46f.h" // TURING_CHANNEL_GPFIFO_A +#include "class/clc56f.h" // AMPERE_CHANNEL_GPFIFO_A +#include "class/clc86f.h" // HOPPER_CHANNEL_GPFIFO_A +#include "class/clc361.h" // VOLTA_USERMODE_A +#include "ctrl/ctrl906f.h" // NV906F_CTRL_GET_CLASS_ENGINEID + +/* + * This low-level macro pushes SetSubDevice methods. Most of the driver should + * use the higher-level NV_DMA_SET_SUBDEVICE_MASK macro. + */ +#define SetSubDeviceMask(_push_buffer, _segment, _mask) \ + do { \ + ASSERT_DRF_NUM(A16F, _DMA, _SET_SUBDEVICE_MASK_VALUE, _mask); \ + nvPushHeader(_push_buffer, _segment, 0, \ + DRF_DEF(A16F, _DMA, _SEC_OP, _GRP0_USE_TERT) | \ + DRF_DEF(A16F, _DMA, _TERT_OP, _GRP0_SET_SUB_DEV_MASK) | \ + DRF_NUM(A16F, _DMA, _SET_SUBDEVICE_MASK_VALUE, _mask)); \ + } while(0) + +/*! + * Check for a channel error on pChannel. + * + * Check the channel's error notifier to determine if a channel error + * occurred. If an error occurred, call the host driver's + * nvPushImportChannelErrorOccurred() implementation, which may take + * steps to recover from the error. + * + * \param[in] pChannel The GPU channel. + * + * \return Return TRUE if a channel error occurred, FALSE otherwise. + */ +NvBool nvPushCheckChannelError(NvPushChannelPtr pChannel) +{ + unsigned short status; + NvNotification *pNotifier; + + if (pChannel->ignoreChannelErrors) { + return FALSE; + } + + pNotifier = + nvPushGetNotifierCpuAddress(pChannel, NV_PUSH_ERROR_NOTIFIER_INDEX, 0); + + status = pNotifier->status; + + if (status == 0xFFFF) { + nvPushImportChannelErrorOccurred(pChannel, pNotifier->info32); + pChannel->channelErrorOccurred = TRUE; + return TRUE; + } + + return FALSE; +} + + +/* + * This function dumps the pushbuffer. The output format is compatible with + * nvdiss. + */ +static void DumpPB(NvPushChannelPtr pChannel) +{ +#if defined(DEBUG) + const NvPushChannelSegmentRec *segment = &pChannel->main; + const int columns = 8; + const NvPushChannelUnion *base = segment->base; + const NvPushChannelUnion *b = + (NvPushChannelUnion *)((char *)segment->base + segment->putOffset); + const NvPushChannelUnion *end = segment->buffer; + NvU32 i; + + if (!pChannel->logNvDiss) { + return; + } + + nvPushImportLogNvDiss(pChannel, + "***************** Push Buffer Contents: ********************\n"); + + for (i = 0; b && b != end; b++, i++) { + if ((i % columns) == 0) { + nvPushImportLogNvDiss(pChannel, "%06" NvUPtr_fmtx ":", + (NvUPtr)((b - base) * 4)); + } + + nvPushImportLogNvDiss(pChannel, " %08X", b->u); + + if ((i % columns) == (columns - 1) || (b + 1) == end) { + nvPushImportLogNvDiss(pChannel, "\n"); + } + } + + nvPushImportLogNvDiss(pChannel, + "***************** End Push Buffer Contents: ****************\n"); + nvPushImportLogNvDiss(pChannel, + "************************************************************\n"); +#endif /* DEBUG */ +} + +static NvU32 ReadProgressTrackerSemaphore(NvPushChannelPtr p, int sd) +{ + volatile NvU32 *ptr = (volatile NvU32 *)p->progressSemaphore.ptr[sd]; + return *ptr; +} + +static NvU32 GpFifoReadGet(NvPushChannelPtr p, int sd) +{ + const NvU32 current = ReadProgressTrackerSemaphore(p, sd); + const NvU32 getDwords = + DRF_VAL(_PUSH_PROGRESS_TRACKER, _SEMAPHORE, _GET, current); + return getDwords * 4; /* return get in bytes */ +} + +static NvU32 GpFifoReadGpGet(NvPushChannelPtr p, int sd) +{ + const NvU32 current = ReadProgressTrackerSemaphore(p, sd); + const NvU32 gpGetPairs = + DRF_VAL(_PUSH_PROGRESS_TRACKER, _SEMAPHORE, _GP_GET, current); + /* return gpGet in gpFifo indices, not pairs of indices */ + return gpGetPairs * 2; +} + +/* Read GPGET for all devices and return the minimum */ +static NvU32 ReadGpGetOffset(NvPushChannelPtr push_buffer) +{ + unsigned int i; + NvU32 bestGet = 0; + NvS32 distanceToPut, maxDistanceToPut = 0; + const NvPushDeviceRec *pDevice = push_buffer->pDevice; + + if (pDevice->numSubDevices <= 1) { + bestGet = GpFifoReadGpGet(push_buffer, 0); + } else { + for (i = 0; i < pDevice->numSubDevices; i++) { + NvU32 get = GpFifoReadGpGet(push_buffer, i); + + /* Compute distance to put, accounting for wraps */ + distanceToPut = push_buffer->gpPutOffset - get; + if (distanceToPut < 0) { + distanceToPut += push_buffer->numGpFifoEntries; + } + + nvAssert(distanceToPut >= 0); + + /* Track the maximum distance to put and the corresponding get. */ + if (distanceToPut >= maxDistanceToPut) { + maxDistanceToPut = distanceToPut; + bestGet = get; + } + } + } + + /* We should never see an odd index, since we always kick off two entries + * at a time. */ + nvAssert((bestGet & 1) == 0); + + return bestGet; +} + +static void FillGpEntry(NvPushChannelSegmentPtr segment, NvU32 putOffset, + NvU32 *gpEntry0, NvU32 *gpEntry1) +{ + const NvU32 length = putOffset - segment->putOffset; + const NvU64 base = segment->gpuMapOffset + segment->putOffset; + *gpEntry0 = + DRF_NUM(A16F, _GP_ENTRY0, _GET, NvU64_LO32(base) >> 2); + *gpEntry1 = + DRF_NUM(A16F, _GP_ENTRY1, _GET_HI, NvU64_HI32(base)) | + DRF_NUM(A16F, _GP_ENTRY1, _LENGTH, length >> 2); + + ASSERT_DRF_NUM(A16F, _GP_ENTRY1, _LENGTH, length >> 2); + nvAssert(segment->putOffset + length <= segment->sizeInBytes); + nvAssert(!(segment->putOffset & 0x3)); + nvAssert(!(length & 0x3)); + nvAssert(length != 0); +} + +/*! + * Calculate the amount of space that we need for each kickoff in the progress + * tracker pushbuffer. + */ +NvU32 __nvPushProgressTrackerEntrySize(const NvPushDeviceRec *pDevice) +{ + NvU32 dwords, size; + + /* + * The minimum number of methods we need is 4 for pre-Volta (SemaphoreA-D), + * and 5 for Volta+ (SemAddrHi/Lo, SemPayloadHi/Lo, SemExecute). + * The pushbuffer encoding consists of one 32-bit header plus one 32-bit + * data entry for each method. + */ + dwords = 1; + + if (pDevice->hal.caps.voltaSemMethods) { + dwords += 5; + } else { + dwords += 4; + } + + /* + * If SLI is enabled, we may need to ensure that the semaphore is written + * on all subdevices. This requires two extra dwords: SET_SUBDEVICE_MASK + * to a broadcast state, and a second SET_SUBDEVICE_MASK to restore the old + * state. + */ + if (pDevice->numSubDevices > 1) { + dwords += 2; + } + + size = dwords * sizeof(NvU32); + + /* + * If the GPU is affected by hardware bug 1667921, then we pad this out to + * NV_ALIGN_LBDAT_EXTRA_BUG. (The workaround requires that each entry be a + * multiple of this size.) + */ + nvAssert(size <= NV_ALIGN_LBDAT_EXTRA_BUG); + return pDevice->hostLBoverflowBug1667921 ? NV_ALIGN_LBDAT_EXTRA_BUG : size; +} + +/*! + * This function emits methods into the progress tracker pushbuffer region that + * will cause host to release a semaphore with payload 'putOffset', then writes + * a GPFIFO entry to 'gpPointer' that will make host fetch those methods. + * + * Normally, for progress tracking purposes, we only need to know if + * host has read the method, in which case _RELEASE_WFI=DIS is sufficient + * below. But, when we need to know if the channel is really idle, host + * must send WAIT_FOR_IDLE to the downstream engine (_RELEASE_WFI=EN). + * Use 'progressTrackerWFI' to control this behavior. + */ +static void InsertProgressTracker(NvPushChannelPtr p, NvU32 putOffset, + NvU32 gpPutOffset, NvU32 *gpPointer, + NvBool progressTrackerWFI) +{ + const NvPushDeviceRec *pDevice = p->pDevice; + NvPushChannelSegmentPtr segment = &p->progressTracker; + + /* + * The progress tracker pushbuffer segment is sized such that we have + * just enough space to write the methods we need to for every (two) + * entries in the GPFIFO. + * + * We directly calculate the location to begin writing methods from the + * size of a single entry and gpPutOffset (divided by two because we only + * write one progress tracker entry for every two GPFIFO entries). + */ + const NvU32 entrySize = __nvPushProgressTrackerEntrySize(pDevice); + const NvU32 entry = gpPutOffset >> 1; + const NvU32 entryOffset = entrySize * entry; + const NvU32 putOffsetDwords = putOffset / 4; + const NvU32 payload = + DRF_NUM(_PUSH_PROGRESS_TRACKER, _SEMAPHORE, _GET, putOffsetDwords) | + DRF_NUM(_PUSH_PROGRESS_TRACKER, _SEMAPHORE, _GP_GET, gpPutOffset / 2); + + NvU32 restoreSDM = NV_PUSH_SUBDEVICE_MASK_ALL; + + /* + * PROGRESS_TRACKER_SEMAPHORE_GET above stores dwords, so + * putOffset had better be a multiple of four. + */ + nvAssert((putOffset % 4) == 0); + + /* + * PROGRESS_TRACKER_SEMAPHORE_GP_GET above stores pairs of gpFifo + * entries, so gpPutOffset had better be even. + */ + nvAssert((gpPutOffset % 2) == 0); + + segment->freeDwords = entrySize / sizeof(NvU32); + segment->putOffset = entryOffset; + segment->buffer = (NvPushChannelUnion *)((char *)segment->base + entryOffset); + + /* + * __nvPushProgressTrackerEntrySize() contains a calculation of how many + * methods we need. This must be kept up-to-date with the actual methods + * pushed below. + */ + if (!nvPushSubDeviceMaskEquiv(pDevice, p->currentSubDevMask, + NV_PUSH_SUBDEVICE_MASK_ALL)) { + restoreSDM = p->currentSubDevMask; + SetSubDeviceMask(p, progressTracker, NV_PUSH_SUBDEVICE_MASK_ALL); + } + if (pDevice->hal.caps.voltaSemMethods) { + const NvU32 semaphoreOperation = + DRF_DEF(C36F, _SEM_EXECUTE, _OPERATION, _RELEASE) | + DRF_DEF(C36F, _SEM_EXECUTE, _PAYLOAD_SIZE, _32BIT) | + DRF_DEF(C36F, _SEM_EXECUTE, _RELEASE_TIMESTAMP, _DIS) | + (progressTrackerWFI ? + DRF_DEF(C36F, _SEM_EXECUTE, _RELEASE_WFI, _EN) : + DRF_DEF(C36F, _SEM_EXECUTE, _RELEASE_WFI, _DIS)); + + __nvPushStart(p, progressTracker, 0, NVC36F_SEM_ADDR_LO, 5, _INC_METHOD); + /* + * NVC36F_SEM_ADDR_{LO,HI} is backwards from most 64-bit + * addresses spread over two methods, so we cannot use + * __nvPushSetMethodDataSegmentU64(). + */ + __nvPushSetMethodDataSegment(segment, NvU64_LO32(p->progressSemaphore.gpuVA)); + __nvPushSetMethodDataSegment(segment, NvU64_HI32(p->progressSemaphore.gpuVA)); + __nvPushSetMethodDataSegment(segment, payload); + __nvPushSetMethodDataSegment(segment, 0); + __nvPushSetMethodDataSegment(segment, semaphoreOperation); + } else { + const NvU32 semaphoreOperation = + DRF_DEF(A16F, _SEMAPHORED, _OPERATION, _RELEASE) | + DRF_DEF(A16F, _SEMAPHORED, _RELEASE_SIZE, _4BYTE) | + (progressTrackerWFI ? + DRF_DEF(A16F, _SEMAPHORED, _RELEASE_WFI, _EN) : + DRF_DEF(A16F, _SEMAPHORED, _RELEASE_WFI, _DIS)); + + __nvPushStart(p, progressTracker, 0, NVA16F_SEMAPHOREA, 4, _INC_METHOD); + __nvPushSetMethodDataSegmentU64(segment, p->progressSemaphore.gpuVA); + __nvPushSetMethodDataSegment(segment, payload); + __nvPushSetMethodDataSegment(segment, semaphoreOperation); + } + + if (restoreSDM != NV_PUSH_SUBDEVICE_MASK_ALL) { + SetSubDeviceMask(p, progressTracker, restoreSDM); + } + + if (pDevice->hostLBoverflowBug1667921) { + /* The workaround for bug 1667921 dictates that we must kick off a + * GPFIFO segment of an exact size. Pad out with NOPs. */ + while (segment->freeDwords) { + nvPushImmedValSegment(p, progressTracker, 0, NVA16F_NOP, 0); + } + } + + FillGpEntry(segment, + (NvU32)((char *)segment->buffer - (char *)segment->base), + &gpPointer[0], &gpPointer[1]); +} + +#if defined(NVCPU_X86) || defined(NVCPU_X86_64) +#define NV_CPU_MEMFENCE() __asm__ __volatile__ ("sfence" : : : "memory") +#elif NVCPU_IS_FAMILY_ARM +#define NV_CPU_MEMFENCE() __asm__ __volatile__ ("dsb sy\n\t" : : : "memory"); +#elif NVCPU_IS_PPC64LE +#define NV_CPU_MEMFENCE() __asm__ __volatile__ ("lwsync\n\t" : : : "memory") +#else +#define NV_CPU_MEMFENCE() /* nothing */ +#endif + +static NvBool nvWriteGpEntry( + NvPushChannelPtr push_buffer, + NvU32 putOffset, + NvBool progressTrackerWFI) +{ + NvU32 gpEntry0, gpEntry1; + + NvU32 nextGpPut; + NvU32 *gpPointer; + const NvU32 entriesNeeded = NV_PUSH_NUM_GPFIFO_ENTRIES_PER_KICKOFF; + NvPushDevicePtr pDevice = push_buffer->pDevice; + + FillGpEntry(&push_buffer->main, putOffset, &gpEntry0, &gpEntry1); + + nextGpPut = (push_buffer->gpPutOffset + entriesNeeded) & + (push_buffer->numGpFifoEntries - 1); + gpPointer = &(push_buffer->gpfifo[push_buffer->gpPutOffset*2]); + + nvAssert((nextGpPut % 2) == 0); + + // Wait for a free entry in the buffer + while (nextGpPut == ReadGpGetOffset(push_buffer)) { + if (nvPushCheckChannelError(push_buffer)) { + nvAssert(!"A channel error occurred in nvWriteGpEntry()"); + return FALSE; + } + } + gpPointer[0] = gpEntry0; + gpPointer[1] = gpEntry1; + gpPointer += 2; + + InsertProgressTracker(push_buffer, putOffset, + push_buffer->gpPutOffset, gpPointer, + progressTrackerWFI); + + /* Make sure all CPU writes to writecombined memory get flushed */ + NV_CPU_MEMFENCE(); + + pDevice->hal.kickoff(push_buffer, push_buffer->gpPutOffset, nextGpPut); + + push_buffer->gpPutOffset = nextGpPut; + + return TRUE; +} + +static void Kickoff(NvPushChannelPtr p, NvBool progressTrackerWFI) +{ + NvU32 putOffset; + + if (!p) { + return; + } + + putOffset = (NvU32)((char *)p->main.buffer - (char *)p->main.base); + + if (p->main.putOffset == putOffset) { + return; + } + + DumpPB(p); + + if (nvWriteGpEntry(p, putOffset, progressTrackerWFI)) { + // Change putOffset only if nvWriteGpEntry succeeds. + // If it fails, it means we went through channel recovery and the + // recovery process changed putOffset. + p->main.putOffset = putOffset; + } +} + +void nvPushKickoff(NvPushChannelPtr p) +{ + Kickoff(p, FALSE /* progressTrackerWFI */); +} + +/*! + * Write GP_PUT to USERD. On GPUs where HOST snoops USERD, this is all we need + * to do to kick off the channel. + */ +static void UserDKickoff(NvPushChannelPtr push_buffer, + NvU32 oldGpPut, NvU32 newGpPut) +{ + /* Kick off all push buffers */ + unsigned int sd; + + for (sd = 0; sd < push_buffer->pDevice->numSubDevices; sd++) { + KeplerBControlGPFifo *pUserd = + (KeplerBControlGPFifo *)push_buffer->control[sd]; + pUserd->GPPut = newGpPut; + } +} + +/*! + * Kick off a channel on GPUs where HOST does not snoop USERD. + * + * This is implemented in two steps: + * 1. Write GP_PUT to USERD; + * 2. Write the channel's token to HOST's doorbell register. + */ +static void DoorbellKickoff(NvPushChannelPtr pChannel, + NvU32 oldGpPut, NvU32 newGpPut) +{ + const NvPushDeviceRec *pDevice = pChannel->pDevice; + NvU32 sd; + + /* First update GPPUT in USERD. */ + UserDKickoff(pChannel, oldGpPut, newGpPut); + +#if NVCPU_IS_PPC64LE + __asm__ __volatile__ ("sync\n\t" : : : "memory"); +#elif NVCPU_IS_FAMILY_ARM + __asm__ __volatile__ ("dsb sy\n\t" : : : "memory"); +#endif + + /* Then ring the doorbells so HOST knows to check for the updated GPPUT. */ + for (sd = 0; sd < pDevice->numSubDevices; sd++) { + volatile NvU32 *doorbell; + NvU8 *pUserMode = (NvU8 *)pDevice->subDevice[sd].pUserMode; + NvU32 notifIndex; + NvNotification *pTokenNotifier = NULL; + + if (pDevice->clientSli) { + notifIndex = NV_CHANNELGPFIFO_NOTIFICATION_TYPE__SIZE_1 + sd; + } else { + /* RM doesn't maintain a separate token for each subdevice. */ + notifIndex = NV_CHANNELGPFIFO_NOTIFICATION_TYPE__SIZE_1; + } + notifIndex |= NV_PUSH_NOTIFIER_INTERNAL_BIT; + + /* The final parameter 'sd' in nvPushGetNotifierCpuAddress is unused + * for internal notifiers. */ + pTokenNotifier = + nvPushGetNotifierCpuAddress(pChannel, notifIndex, 0); + + nvAssert(pUserMode != NULL); + + doorbell = (volatile NvU32 *)(pUserMode + + NVC361_NOTIFY_CHANNEL_PENDING); + *doorbell = pTokenNotifier->info32; + } +} + +/* Read GET for all devices and return the minimum or maximum*/ +NvU32 nvPushReadGetOffset(NvPushChannelPtr push_buffer, NvBool minimum) +{ + unsigned int i; + NvU32 get, bestGet = 0; + const NvPushDeviceRec *pDevice = push_buffer->pDevice; + NvS32 distanceToPut, minmaxDistanceToPut = + minimum ? 0 : push_buffer->main.sizeInBytes; + + if (pDevice->numSubDevices <= 1) { + return GpFifoReadGet(push_buffer, 0); + } + + for (i = 0; i < pDevice->numSubDevices; i++) { + get = GpFifoReadGet(push_buffer, i); + + /* Compute distance to put, accounting for wraps */ + distanceToPut = push_buffer->main.putOffset - get; + if (distanceToPut < 0) { + distanceToPut += push_buffer->main.sizeInBytes; + } + + /* Accumulate the maximum distance to put and the corresponding get. */ + if ((minimum && (distanceToPut >= minmaxDistanceToPut)) || + (!minimum && (distanceToPut <= minmaxDistanceToPut))) { + minmaxDistanceToPut = distanceToPut; + bestGet = get; + } + } + return bestGet; +} + +static void WriteGetOffset(NvPushChannelPtr p, NvU32 value) +{ + NvPushDeviceRec *pDevice = p->pDevice; + unsigned int sd; + + for (sd = 0; sd < pDevice->numSubDevices; sd++) { + volatile NvU32 *ptr = (volatile NvU32 *)(p->progressSemaphore.ptr[sd]); + *ptr = value; + } + + NV_CPU_MEMFENCE(); +} + +static NvBool IdleChannel(NvPushChannelPtr p, NvBool progressTrackerWFI, + NvU32 timeoutMSec) +{ + NvU64 baseTime, currentTime; + + /* + * Write a channel NOP, kick off the pushbuffer, and wait for the + * pushbuffer to drain. It is important for the NOP to be written + * here: this ensures the kickoff won't be optimized away, as it + * otherwise would if the host driver called: + * + * nvPushKickoff(pChannel); + * nvPushIdleChannel(pChannel); + * + * The path nvPushIdleChannel() => IdleChannel() => Kickoff() will + * issue a WFI, which is important to ensure the channel is really + * idle. + */ + nvPushHeader(p, main, 0, NVA16F_DMA_NOP); + + Kickoff(p, progressTrackerWFI); + + for (baseTime = currentTime = nvPushImportGetMilliSeconds(p->pDevice); + TRUE; currentTime = nvPushImportGetMilliSeconds(p->pDevice)) { + + nvAssert(p->main.putOffset != 0); + + if (nvPushReadGetOffset(p, TRUE) == p->main.putOffset) { + return TRUE; + } + + if (currentTime > (baseTime + timeoutMSec) && + !p->noTimeout) { + return FALSE; + } + } +} + +/* + * Idle channel with the requested timeout, but don't print an error when it + * times out. This should be used for verifying expected timeouts on + * idlechannels in testing. + */ +NvBool nvPushIdleChannelTest(NvPushChannelPtr pChannel, NvU32 timeoutMSec) +{ + return IdleChannel(pChannel, TRUE /* progressTrackerWFI */, timeoutMSec); +} + +NvBool nvPushIdleChannel(NvPushChannelPtr pChannel) +{ + NvBool ret; + + ret = IdleChannel(pChannel, TRUE /* progressTrackerWFI */, + NV_PUSH_NOTIFIER_SHORT_TIMEOUT); + + if (!ret) { + nvPushImportLogError(pChannel->pDevice, "Failed to idle DMA."); + } + + return ret; +} + +NvBool __nvPushTestPushBuffer(NvPushChannelPtr p) +{ + NvBool ret; + + /* + * Immediately after allocating the pushbuffer, push a channel NOP and + * babysit the channel until it's consumed as a quick sanity check. + */ + WriteGetOffset(p, 0); + + ret = IdleChannel(p, FALSE /* progressTrackerWFI */, + NV_PUSH_NOTIFIER_SHORT_TIMEOUT); + + if (!ret) { + nvPushImportLogError(p->pDevice, "Failed to initialize DMA."); + } + + return ret; +} + +void __nvPushMakeRoom(NvPushChannelPtr push_buffer, NvU32 count) +{ + NvU32 getOffset; + NvU32 putOffset; + NvBool fenceToEnd = FALSE; + + putOffset = (NvU32) ((char *)push_buffer->main.buffer - + (char *)push_buffer->main.base); + + nvAssert(putOffset <= push_buffer->main.sizeInBytes); + nvAssert((count << 2) <= push_buffer->main.sizeInBytes); + + if (putOffset != push_buffer->main.putOffset) { + nvPushKickoff(push_buffer); + } + nvAssert(putOffset == push_buffer->main.putOffset); + + while (count >= push_buffer->main.freeDwords) { + if (nvPushCheckChannelError(push_buffer)) { + nvAssert(!"A channel error occurred in __nvPushMakeRoom()"); + // Unlike with non-gpfifo channels, RC recovery can't reset GET to + // 0 so we need to continue as if we just started waiting for space. + return __nvPushMakeRoom(push_buffer, count); + } + + getOffset = nvPushReadGetOffset(push_buffer, TRUE); + nvAssert(getOffset <= push_buffer->main.sizeInBytes); + + if (getOffset > putOffset) { + // We previously wrapped. The space between PUT and GET is + // available. + push_buffer->main.freeDwords = ((getOffset - putOffset) >> 2) - 1; + + // TODO: If still not enough room, call DelayRegisterReadsCaller + // here. + } else if(!fenceToEnd) { + // GET wrapped, so we can write all the way to the end of the + // pushbuffer. + fenceToEnd = TRUE; + push_buffer->main.freeDwords = + (push_buffer->main.sizeInBytes - putOffset) >> 2; + } else { + // getOffset is behind putOffset and there wasn't enough space + // between putOffset and the end of the pushbuffer. Wrap to the + // beginning and wait for GET to advance far enough. + + nvAssert((putOffset >> 2) > count); + + // Record where the last method was written so that RC recovery can + // know where to wrap. + nvPushImportPushbufferWrapped(push_buffer); + + // We can't write putOffset to 0 while getOffset is 0 + // otherwise we could fool ourselves into thinking a full + // pushbuffer is empty + if (getOffset) { + // XXX NOTE: While it would be nice to be able to decide that we + // can write to the whole pushbuffer when getOffset == putOffset, we + // can fall into the trap of writing the same amount of data to the + // pushbuffer twice and not being able to tell whether GET has + // wrapped all the way around, or hasn't moved at all. + + push_buffer->main.putOffset = 0; + push_buffer->main.buffer = push_buffer->main.base; + push_buffer->main.freeDwords = (getOffset >> 2) - 1; + } + } + + if (nvPushCheckChannelError(push_buffer)) { + nvAssert(!"A channel error was recovered when waiting for room in push buffer"); + return __nvPushMakeRoom(push_buffer, count); + } + } + +#if defined(DEBUG) + { + const NvU32 freeBytes = push_buffer->main.freeDwords * 4; + const NvU8 *curPtr = + ((NvU8 *)push_buffer->main.buffer) + freeBytes; + const NvU8 *endPtr = + ((NvU8 *)push_buffer->main.base) + push_buffer->main.sizeInBytes; + + nvAssert(freeBytes <= push_buffer->main.sizeInBytes); + nvAssert(curPtr <= endPtr); + } +#endif /* DEBUG */ +} + +/* + * This function intializes a notifier to IN_PROGRESS on all subdevices. + */ +void nvPushInitWaitForNotifier( + NvPushChannelPtr pChannel, + NvU32 notifierIndex, + NvU32 subdeviceMask) +{ + unsigned int sd; + + for (sd = 0; sd < pChannel->pDevice->numSubDevices; sd++) { + + NvNotification *pNotifier; + + if (!(subdeviceMask & (1 << sd))) { + continue; + + } + + pNotifier = nvPushGetNotifierCpuAddress(pChannel, notifierIndex, sd); + pNotifier->status = NV2080_SUBDEVICE_NOTIFICATION_STATUS_IN_PROGRESS; + } +} + +/* + * This function waits for a notifier. It does the following: + * + * - has a short and long timeout + * + * - if the short timeout was exceeded then check if PUT == GET. If PUT + * == GET then it is almost certain that the notifier really should + * have been delivered and something is wrong. We should just stop + * waiting for the notifier. + * + * - if the short timeout was exceeded and PUT != GET then trying + * rewriting PUT in hopes of getting the hardware back on track. + * (note: this doesn't actually do anything on GPFIFO channels) + * + * - if the PUT != GET and the long timeout is exceeded the chip must + * be hung or our channel encountered an error. + * + * - For either timeout, in a debug build print a diagnostic message + * to indicate what went wrong. + * + * This function always prints out a terse message so that we can + * diagnose problems from the field. In debug builds we print out + * additional information. + */ + +void nvPushWaitForNotifier( + NvPushChannelPtr p, + NvU32 notifyIndex, + NvU32 subdeviceMask, + NvBool yield, + NvPushImportEvent *pEvent, + int id) +{ + NvU64 newtime, short_timeout_value = 0, long_timeout_value = 0; + NvBool short_timeout, long_timeout, shortTimeOutDone = FALSE; + NvU32 getOffset; + unsigned int sd; + NvNotification * pNotify; + int timeout = 0; + NvBool must_wait_for_event = (pEvent != NULL); + NvPushDevicePtr pDevice = p->pDevice; + + for (sd = 0; sd < pDevice->numSubDevices; sd++) { + if (!(subdeviceMask & (1 << sd))) + continue; + + pNotify = nvPushGetNotifierCpuAddress(p, notifyIndex, sd); + + // Give a chance not to enter the while loop if notifier is + // already ready. + while ((must_wait_for_event) || + (pNotify->status != NV2080_SUBDEVICE_NOTIFICATION_STATUS_DONE_SUCCESS)) { + + newtime = nvPushImportGetMilliSeconds(pDevice); + + if (!short_timeout_value) { + short_timeout_value = newtime + NV_PUSH_NOTIFIER_SHORT_TIMEOUT; + long_timeout_value = newtime + NV_PUSH_NOTIFIER_LONG_TIMEOUT; + } + + if (must_wait_for_event && pEvent) { + if (timeout == 0) { + timeout = NV_PUSH_NOTIFIER_SHORT_TIMEOUT; + } else { + timeout = NV_PUSH_NOTIFIER_LONG_TIMEOUT-NV_PUSH_NOTIFIER_SHORT_TIMEOUT; + must_wait_for_event = FALSE; + } + + if (nvPushImportWaitForEvent(pDevice, pEvent, timeout)) { + // At this point we won't wait for OS events + // anymore, but still for the notifier. + must_wait_for_event = FALSE; + continue; + } + // We timed out or an error occurred + } + + short_timeout = (newtime > short_timeout_value); + long_timeout = (newtime > long_timeout_value); + + if (p->noTimeout) { + short_timeout = FALSE; + long_timeout = FALSE; + } + + if (nvPushCheckChannelError(p)) { + nvAssert(!"A channel error was recovered when waiting for a notifier; returning"); + return; + } + + if (short_timeout || long_timeout) { + + getOffset = GpFifoReadGet(p, sd); + if (p->main.putOffset == getOffset) { + + /* + * If PUT == GET then it is almost certain that the + * notifier really should have been delivered and + * something is wrong. We should just stop waiting for + * the notifier. + */ + + nvPushImportLogError(pDevice, + "WAIT (0, %d, 0x%04x, 0x%08x, 0x%08x)", + id, pNotify->status, getOffset, p->main.putOffset); + nvAssert(!"PUT == GET, but notifier has not completed; returning!"); + + /* Set status to done in case it is read */ + pNotify->status = NV2080_SUBDEVICE_NOTIFICATION_STATUS_DONE_SUCCESS; + + continue; + } + + if (long_timeout) { + + nvPushImportLogError(pDevice, + "WAIT (1, %d, 0x%04x, 0x%08x, 0x%08x)", + id, pNotify->status, getOffset, p->main.putOffset); + nvAssert(!"Long timeout exceeded; PUT != GET; returning!"); + + /* Set status to done in case it is read */ + pNotify->status = NV2080_SUBDEVICE_NOTIFICATION_STATUS_DONE_SUCCESS; + + return; + } + + if (!shortTimeOutDone) { + nvPushImportLogError(pDevice, + "WAIT (2, %d, 0x%04x, 0x%08x, 0x%08x)", + id, pNotify->status, getOffset, p->main.putOffset); + nvAssert(!"Short timeout exceeded; PUT != GET"); + + /* Once is enough */ + shortTimeOutDone = TRUE; + } + } + + /* optionally yield */ + if (!pEvent && yield) { + nvPushImportYield(pDevice); + } + } + } + + if (pEvent) { + /* Empty the event FIFO */ + nvPushImportEmptyEventFifo(pDevice, pEvent); + } +} + +// Decode a method header, returning the method count. Return FALSE if the +// value is not recognizable as a method header. +NvBool nvPushDecodeMethod(NvU32 header, NvU32 *count) +{ + switch (DRF_VAL(A16F, _DMA, _SEC_OP, header)) { + case NVA16F_DMA_SEC_OP_IMMD_DATA_METHOD: + *count = 0; + return TRUE; + case NVA16F_DMA_SEC_OP_INC_METHOD: + case NVA16F_DMA_SEC_OP_NON_INC_METHOD: + case NVA16F_DMA_SEC_OP_ONE_INC: + *count = DRF_VAL(A16F, _DMA, _METHOD_COUNT, header); + return TRUE; + default: + // Not a recognized method header! + return FALSE; + } +} + +static NvU32 GetSetObjectHandle(NvPushChannelPtr pChannel, NvU32 handle, + int deviceIndex) +{ + NvPushDevicePtr pDevice = pChannel->pDevice; + NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS params = { 0 }; + NvU32 ret; + + // AModel has a bug where it requires an object handle instead of a class + // and engine ID. + if (nvPushIsAModel(pDevice)) { + return handle; + } + + // Query RM for the class and engine ID of this handle. + params.hObject = handle; + ret = nvPushImportRmApiControl(pDevice, + pChannel->channelHandle[deviceIndex], + NV906F_CTRL_GET_CLASS_ENGINEID, + ¶ms, sizeof(params)); + + if (ret != NVOS_STATUS_SUCCESS) { + nvPushImportLogError(pDevice, "Failed to query object info."); + return 0; + } + +#if defined(DEBUG) + // Print debug spew mapping the SetObject ID to a class number for + // nvdiss + if (params.classID && pChannel->logNvDiss) { + nvPushImportLogNvDiss(pChannel, + "SetObjectId: class 0x%x, objectID 0x%x\n", + params.classID, params.classEngineID); + } +#endif /* DEBUG */ + + return params.classEngineID; +} + +// Issue a SET_OBJECT method on the specified subchannel. +void nvPushSetObject(NvPushChannelPtr p, NvU32 subch, NvU32 object[NV_MAX_SUBDEVICES]) +{ + const NvPushDeviceRec *pDevice = p->pDevice; + const NvU32 oldSubDevMask = p->currentSubDevMask; + int deviceIndex; + + for (deviceIndex = 0; + deviceIndex < __nvPushGetNumDevices(pDevice); + deviceIndex++) { + if (pDevice->clientSli) { + const NvU32 thisSDM = 1 << deviceIndex; + if ((thisSDM & oldSubDevMask) == 0) { + continue; + } + nvPushSetSubdeviceMask(p, thisSDM); + } + nvPushMethod(p, subch, NVA16F_SET_OBJECT, 1); + nvPushSetMethodData(p, + GetSetObjectHandle(p, object[deviceIndex], deviceIndex)); + } + nvPushSetSubdeviceMask(p, oldSubDevMask); +} + +void nvPushSetSubdeviceMask(NvPushChannelPtr p, NvU32 mask) +{ + if (nvPushSubDeviceMaskEquiv(p->pDevice, p->currentSubDevMask, mask)) { + return; + } + p->currentSubDevMask = mask; + + SetSubDeviceMask(p, main, mask); +} + +static void KeplerReleaseTimelineSemaphore( + NvPushChannelPtr p, + void *cpuAddress, + NvU64 gpuAddress, + NvU64 val) +{ + NvReportSemaphore32 *report = (NvReportSemaphore32 *)cpuAddress; + + // Must be done before submitting the semaphore release to ensure the maximum + // known-submitted value is never less than the semaphore's current value. + NvTimeSemFermiSetMaxSubmitted(report, val); + + nvPushMethod(p, 0, NVA16F_SEMAPHOREA, 4); + nvPushSetMethodDataU64(p, gpuAddress); // NVA16F_SEMAPHOREB + nvPushSetMethodData(p, val); // NVA16F_SEMAPHOREC + nvPushSetMethodData(p, // NVA16F_SEMAPHORED + DRF_DEF(A16F, _SEMAPHORED, _OPERATION, _RELEASE) | + DRF_DEF(A16F, _SEMAPHORED, _RELEASE_SIZE, _4BYTE)); + + nvPushMethod(p, 0, NVA16F_NON_STALL_INTERRUPT, 1); + nvPushSetMethodData(p, 0); +} + +static void KeplerAcquireTimelineSemaphore( + NvPushChannelPtr p, + NvU64 gpuAddress, + NvU64 val) +{ + nvPushMethod(p, 0, NVA16F_SEMAPHOREA, 4); + nvPushSetMethodDataU64(p, gpuAddress); // NVA16F_SEMAPHOREB + nvPushSetMethodData(p, val); // NVA16F_SEMAPHOREC + nvPushSetMethodData(p, // NVA16F_SEMAPHORED + DRF_DEF(A16F, _SEMAPHORED, _ACQUIRE_SWITCH, _ENABLED) | + DRF_DEF(A16F, _SEMAPHORED, _OPERATION, _ACQ_GEQ)); +} + +static void VoltaReleaseTimelineSemaphore( + NvPushChannelPtr p, + void *cpuAddress, + NvU64 gpuAddress, + NvU64 val) +{ + nvPushMethod(p, 0, NVC36F_SEM_ADDR_LO, 5); + nvPushSetMethodData(p, NvU64_LO32(gpuAddress)); + nvPushSetMethodData(p, NvU64_HI32(gpuAddress)); // NVC36F_SEM_ADDR_HI + nvPushSetMethodData(p, NvU64_LO32(val)); // NVC36F_SEM_PAYLOAD_LO + nvPushSetMethodData(p, NvU64_HI32(val)); // NVC36F_SEM_PAYLOAD_HI + nvPushSetMethodData(p, // NVC36F_SEM_EXECUTE + DRF_DEF(C36F, _SEM_EXECUTE, _OPERATION, _RELEASE) | + DRF_DEF(C36F, _SEM_EXECUTE, _RELEASE_WFI, _EN) | + DRF_DEF(C36F, _SEM_EXECUTE, _PAYLOAD_SIZE, _64BIT) | + DRF_DEF(C36F, _SEM_EXECUTE, _RELEASE_TIMESTAMP, _EN)); + + nvPushMethod(p, 0, NVC36F_NON_STALL_INTERRUPT, 1); + nvPushSetMethodData(p, 0); +} + +static void VoltaAcquireTimelineSemaphore( + NvPushChannelPtr p, + NvU64 gpuAddress, + NvU64 val) +{ + nvPushMethod(p, 0, NVC36F_SEM_ADDR_LO, 5); + nvPushSetMethodData(p, NvU64_LO32(gpuAddress)); + nvPushSetMethodData(p, NvU64_HI32(gpuAddress)); // NVC36F_SEM_ADDR_HI + nvPushSetMethodData(p, NvU64_LO32(val)); // NVC36F_SEM_PAYLOAD_LO + nvPushSetMethodData(p, NvU64_HI32(val)); // NVC36F_SEM_PAYLOAD_HI + nvPushSetMethodData(p, // NVC36F_SEM_EXECUTE + DRF_DEF(C36F, _SEM_EXECUTE, _OPERATION, _ACQ_STRICT_GEQ) | + DRF_DEF(C36F, _SEM_EXECUTE, _ACQUIRE_SWITCH_TSG, _EN) | + DRF_DEF(C36F, _SEM_EXECUTE, _PAYLOAD_SIZE, _64BIT)); +} + +void nvPushReleaseTimelineSemaphore( + NvPushChannelPtr p, + void *cpuAddress, + NvU64 gpuAddress, + NvU64 val) +{ + NvPushDevicePtr pDevice = p->pDevice; + pDevice->hal.releaseTimelineSemaphore(p, cpuAddress, gpuAddress, val); +} + +void nvPushAcquireTimelineSemaphore( + NvPushChannelPtr p, + NvU64 gpuAddress, + NvU64 val) +{ + NvPushDevicePtr pDevice = p->pDevice; + pDevice->hal.acquireTimelineSemaphore(p, gpuAddress, val); +} + +NvBool __nvPushGetHal( + const NvPushAllocDeviceParams *pParams, + NvU32 channelClass, + NvPushHal *pHal) +{ + switch (channelClass) { + case HOPPER_CHANNEL_GPFIFO_A: + pHal->caps.extendedBase = TRUE; + // otherwise backwards compatible with the Volta DMA HAL + // fall through +#if defined(__GNUC__) && __GNUC__ >= 7 + // GCC apparently doesn't think the comment above is sufficient to + // quiet -Wimplicit-fallthrough, when there are preprocessor + // directives between it and the next case. + // This attribute is only supported on gcc 7 and later. + __attribute__ ((fallthrough)); +#endif + case AMPERE_CHANNEL_GPFIFO_A: + // backwards compatible with the Volta DMA HAL + // fall through + case TURING_CHANNEL_GPFIFO_A: + // backwards compatible with the Volta DMA HAL + // fall through + case VOLTA_CHANNEL_GPFIFO_A: + pHal->kickoff = DoorbellKickoff; + pHal->caps.clientAllocatesUserD = TRUE; + pHal->caps.allocateDoubleSizeGpFifo = FALSE; + pHal->caps.voltaSemMethods = TRUE; + pHal->releaseTimelineSemaphore = VoltaReleaseTimelineSemaphore; + pHal->acquireTimelineSemaphore = VoltaAcquireTimelineSemaphore; + break; + case PASCAL_CHANNEL_GPFIFO_A: + // backwards compatible with the Kepler DMA HAL + // fall through + case MAXWELL_CHANNEL_GPFIFO_A: + // backwards compatible with the Kepler DMA HAL + // fall through + case KEPLER_CHANNEL_GPFIFO_B: + pHal->kickoff = UserDKickoff; + pHal->caps.clientAllocatesUserD = FALSE; + pHal->caps.allocateDoubleSizeGpFifo = FALSE; + pHal->releaseTimelineSemaphore = KeplerReleaseTimelineSemaphore; + pHal->acquireTimelineSemaphore = KeplerAcquireTimelineSemaphore; + break; + default: + nvAssert(!"There's no DMA HAL for this channel class"); + } + + if (pParams->amodel.config != NV_AMODEL_NONE) { + pHal->kickoff = NULL; + } else if (pParams->isTegra) { + pHal->kickoff = NULL; + } + + return !!(pHal->kickoff); +} + +void __nvPushMoveDWORDS(NvU32* dst, const NvU32* src, int dwords) +{ + while (dwords & ~0x03) { + *dst = *src; + *(dst + 1) = *(src + 1); + *(dst + 2) = *(src + 2); + *(dst + 3) = *(src + 3); + src += 4; + dst += 4; + dwords -= 4; + } + if (!dwords) return; + *dst = *src; + if (dwords == 1) return; + *(dst + 1) = *(src + 1); + if (dwords == 2) return; + *(dst + 2) = *(src + 2); +} diff --git a/src/common/unix/xzminidec/interface/xz.h b/src/common/unix/xzminidec/interface/xz.h new file mode 100644 index 000000000..aa583627e --- /dev/null +++ b/src/common/unix/xzminidec/interface/xz.h @@ -0,0 +1,285 @@ +/* + * XZ decompressor + * + * Authors: Lasse Collin + * Igor Pavlov + * + * This file has been put into the public domain. + * You can do whatever you want with this file. + */ + +#ifndef XZ_H +#define XZ_H + +/* Get the definition of size_t. */ +#if defined(__KERNEL__) +# include +#else +# include +#endif + +/* Get the definition of uint32_t and friends. */ +#if defined(NV_XZ_USE_NVTYPES) +# include + typedef NvU8 uint8_t; + typedef NvU16 uint16_t; + typedef NvU32 uint32_t; + typedef NvU64 uint64_t; +#elif defined(__KERNEL__) +# include +#else +# include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* In Linux, this is used to make extern functions static when needed. */ +#ifndef XZ_EXTERN +# define XZ_EXTERN extern +#endif + +/** + * enum xz_mode - Operation mode + * + * @XZ_SINGLE: Single-call mode. This uses less RAM than + * than multi-call modes, because the LZMA2 + * dictionary doesn't need to be allocated as + * part of the decoder state. All required data + * structures are allocated at initialization, + * so xz_dec_run() cannot return XZ_MEM_ERROR. + * @XZ_PREALLOC: Multi-call mode with preallocated LZMA2 + * dictionary buffer. All data structures are + * allocated at initialization, so xz_dec_run() + * cannot return XZ_MEM_ERROR. + * @XZ_DYNALLOC: Multi-call mode. The LZMA2 dictionary is + * allocated once the required size has been + * parsed from the stream headers. If the + * allocation fails, xz_dec_run() will return + * XZ_MEM_ERROR. + * + * It is possible to enable support only for a subset of the above + * modes at compile time by defining XZ_DEC_SINGLE, XZ_DEC_PREALLOC, + * or XZ_DEC_DYNALLOC. The xz_dec kernel module is always compiled + * with support for all operation modes, but the preboot code may + * be built with fewer features to minimize code size. + */ +enum xz_mode { + XZ_SINGLE, + XZ_PREALLOC, + XZ_DYNALLOC +}; + +/** + * enum xz_ret - Return codes + * @XZ_OK: Everything is OK so far. More input or more + * output space is required to continue. This + * return code is possible only in multi-call mode + * (XZ_PREALLOC or XZ_DYNALLOC). + * @XZ_STREAM_END: Operation finished successfully. + * @XZ_UNSUPPORTED_CHECK: Integrity check type is not supported. Decoding + * is still possible in multi-call mode by simply + * calling xz_dec_run() again. + * Note that this return value is used only if + * XZ_DEC_ANY_CHECK was defined at build time, + * which is not used in the kernel. Unsupported + * check types return XZ_OPTIONS_ERROR if + * XZ_DEC_ANY_CHECK was not defined at build time. + * @XZ_MEM_ERROR: Allocating memory failed. This return code is + * possible only if the decoder was initialized + * with XZ_DYNALLOC. The amount of memory that was + * tried to be allocated was no more than the + * dict_max argument given to xz_dec_init(). + * @XZ_MEMLIMIT_ERROR: A bigger LZMA2 dictionary would be needed than + * allowed by the dict_max argument given to + * xz_dec_init(). This return value is possible + * only in multi-call mode (XZ_PREALLOC or + * XZ_DYNALLOC); the single-call mode (XZ_SINGLE) + * ignores the dict_max argument. + * @XZ_FORMAT_ERROR: File format was not recognized (wrong magic + * bytes). + * @XZ_OPTIONS_ERROR: This implementation doesn't support the requested + * compression options. In the decoder this means + * that the header CRC32 matches, but the header + * itself specifies something that we don't support. + * @XZ_DATA_ERROR: Compressed data is corrupt. + * @XZ_BUF_ERROR: Cannot make any progress. Details are slightly + * different between multi-call and single-call + * mode; more information below. + * + * In multi-call mode, XZ_BUF_ERROR is returned when two consecutive calls + * to XZ code cannot consume any input and cannot produce any new output. + * This happens when there is no new input available, or the output buffer + * is full while at least one output byte is still pending. Assuming your + * code is not buggy, you can get this error only when decoding a compressed + * stream that is truncated or otherwise corrupt. + * + * In single-call mode, XZ_BUF_ERROR is returned only when the output buffer + * is too small or the compressed input is corrupt in a way that makes the + * decoder produce more output than the caller expected. When it is + * (relatively) clear that the compressed input is truncated, XZ_DATA_ERROR + * is used instead of XZ_BUF_ERROR. + */ +enum xz_ret { + XZ_OK, + XZ_STREAM_END, + XZ_UNSUPPORTED_CHECK, + XZ_MEM_ERROR, + XZ_MEMLIMIT_ERROR, + XZ_FORMAT_ERROR, + XZ_OPTIONS_ERROR, + XZ_DATA_ERROR, + XZ_BUF_ERROR +}; + +/** + * struct xz_buf - Passing input and output buffers to XZ code + * @in: Beginning of the input buffer. This may be NULL if and only + * if in_pos is equal to in_size. + * @in_pos: Current position in the input buffer. This must not exceed + * in_size. + * @in_size: Size of the input buffer + * @out: Beginning of the output buffer. This may be NULL if and only + * if out_pos is equal to out_size. + * @out_pos: Current position in the output buffer. This must not exceed + * out_size. + * @out_size: Size of the output buffer + * + * Only the contents of the output buffer from out[out_pos] onward, and + * the variables in_pos and out_pos are modified by the XZ code. + */ +struct xz_buf { + const uint8_t *in; + size_t in_pos; + size_t in_size; + + uint8_t *out; + size_t out_pos; + size_t out_size; +}; + +/** + * struct xz_dec - Opaque type to hold the XZ decoder state + */ +struct xz_dec; + +/** + * xz_dec_init() - Allocate and initialize a XZ decoder state + * @mode: Operation mode + * @dict_max: Maximum size of the LZMA2 dictionary (history buffer) for + * multi-call decoding. This is ignored in single-call mode + * (mode == XZ_SINGLE). LZMA2 dictionary is always 2^n bytes + * or 2^n + 2^(n-1) bytes (the latter sizes are less common + * in practice), so other values for dict_max don't make sense. + * In the kernel, dictionary sizes of 64 KiB, 128 KiB, 256 KiB, + * 512 KiB, and 1 MiB are probably the only reasonable values, + * except for kernel and initramfs images where a bigger + * dictionary can be fine and useful. + * + * Single-call mode (XZ_SINGLE): xz_dec_run() decodes the whole stream at + * once. The caller must provide enough output space or the decoding will + * fail. The output space is used as the dictionary buffer, which is why + * there is no need to allocate the dictionary as part of the decoder's + * internal state. + * + * Because the output buffer is used as the workspace, streams encoded using + * a big dictionary are not a problem in single-call mode. It is enough that + * the output buffer is big enough to hold the actual uncompressed data; it + * can be smaller than the dictionary size stored in the stream headers. + * + * Multi-call mode with preallocated dictionary (XZ_PREALLOC): dict_max bytes + * of memory is preallocated for the LZMA2 dictionary. This way there is no + * risk that xz_dec_run() could run out of memory, since xz_dec_run() will + * never allocate any memory. Instead, if the preallocated dictionary is too + * small for decoding the given input stream, xz_dec_run() will return + * XZ_MEMLIMIT_ERROR. Thus, it is important to know what kind of data will be + * decoded to avoid allocating excessive amount of memory for the dictionary. + * + * Multi-call mode with dynamically allocated dictionary (XZ_DYNALLOC): + * dict_max specifies the maximum allowed dictionary size that xz_dec_run() + * may allocate once it has parsed the dictionary size from the stream + * headers. This way excessive allocations can be avoided while still + * limiting the maximum memory usage to a sane value to prevent running the + * system out of memory when decompressing streams from untrusted sources. + * + * On success, xz_dec_init() returns a pointer to struct xz_dec, which is + * ready to be used with xz_dec_run(). If memory allocation fails, + * xz_dec_init() returns NULL. + */ +XZ_EXTERN struct xz_dec *xz_dec_init(enum xz_mode mode, uint32_t dict_max); + +/** + * xz_dec_run() - Run the XZ decoder + * @s: Decoder state allocated using xz_dec_init() + * @b: Input and output buffers + * + * The possible return values depend on build options and operation mode. + * See enum xz_ret for details. + * + * Note that if an error occurs in single-call mode (return value is not + * XZ_STREAM_END), b->in_pos and b->out_pos are not modified and the + * contents of the output buffer from b->out[b->out_pos] onward are + * undefined. This is true even after XZ_BUF_ERROR, because with some filter + * chains, there may be a second pass over the output buffer, and this pass + * cannot be properly done if the output buffer is truncated. Thus, you + * cannot give the single-call decoder a too small buffer and then expect to + * get that amount valid data from the beginning of the stream. You must use + * the multi-call decoder if you don't want to uncompress the whole stream. + */ +XZ_EXTERN enum xz_ret xz_dec_run(struct xz_dec *s, struct xz_buf *b); + +/** + * xz_dec_reset() - Reset an already allocated decoder state + * @s: Decoder state allocated using xz_dec_init() + * + * This function can be used to reset the multi-call decoder state without + * freeing and reallocating memory with xz_dec_end() and xz_dec_init(). + * + * In single-call mode, xz_dec_reset() is always called in the beginning of + * xz_dec_run(). Thus, explicit call to xz_dec_reset() is useful only in + * multi-call mode. + */ +XZ_EXTERN void xz_dec_reset(struct xz_dec *s); + +/** + * xz_dec_end() - Free the memory allocated for the decoder state + * @s: Decoder state allocated using xz_dec_init(). If s is NULL, + * this function does nothing. + */ +XZ_EXTERN void xz_dec_end(struct xz_dec *s); + +/* + * Standalone build (userspace build or in-kernel build for boot time use) + * needs a CRC32 implementation. For normal in-kernel use, kernel's own + * CRC32 module is used instead, and users of this module don't need to + * care about the functions below. + */ +#ifndef XZ_INTERNAL_CRC32 +# ifdef __KERNEL__ +# define XZ_INTERNAL_CRC32 0 +# else +# define XZ_INTERNAL_CRC32 1 +# endif +#endif + +#if XZ_INTERNAL_CRC32 +/* + * This must be called before any other xz_* function to initialize + * the CRC32 lookup table. + */ +XZ_EXTERN void xz_crc32_init(void); + +/* + * Update CRC32 value using the polynomial from IEEE-802.3. To start a new + * calculation, the third argument must be zero. To continue the calculation, + * the previously returned value is passed as the third argument. + */ +XZ_EXTERN uint32_t xz_crc32(const uint8_t *buf, size_t size, uint32_t crc); +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/common/unix/xzminidec/src/xz_config.h b/src/common/unix/xzminidec/src/xz_config.h new file mode 100644 index 000000000..a552b4a0c --- /dev/null +++ b/src/common/unix/xzminidec/src/xz_config.h @@ -0,0 +1,113 @@ +/* + * Private includes and definitions for userspace use of XZ Embedded + * + * Author: Lasse Collin + * + * This file has been put into the public domain. + * You can do whatever you want with this file. + */ + +#ifndef XZ_CONFIG_H +#define XZ_CONFIG_H + +/* Uncomment as needed to enable BCJ filter decoders. */ +/* #define XZ_DEC_X86 */ +/* #define XZ_DEC_POWERPC */ +/* #define XZ_DEC_IA64 */ +/* #define XZ_DEC_ARM */ +/* #define XZ_DEC_ARMTHUMB */ +/* #define XZ_DEC_SPARC */ + +#include + +#include "xz.h" + +#if defined(NV_XZ_CUSTOM_MEM_HOOKS) +# include "nv_xz_mem_hooks.h" +#else +# include +# include +# define kmalloc(size, flags) malloc(size) +# define kfree(ptr) free(ptr) +# define vmalloc(size) malloc(size) +# define vfree(ptr) free(ptr) + +# define memeq(a, b, size) (memcmp(a, b, size) == 0) +# define memzero(buf, size) memset(buf, 0, size) +#endif /* defined(NV_XZ_CUSTOM_MEM_HOOKS) */ + +#ifndef min +# define min(x, y) ((x) < (y) ? (x) : (y)) +#endif +#define min_t(type, x, y) min(x, y) + +/* + * Some functions have been marked with __always_inline to keep the + * performance reasonable even when the compiler is optimizing for + * small code size. You may be able to save a few bytes by #defining + * __always_inline to plain inline, but don't complain if the code + * becomes slow. + * + * NOTE: System headers on GNU/Linux may #define this macro already, + * so if you want to change it, you need to #undef it first. + */ +#ifndef __always_inline +# ifdef __GNUC__ +# define __always_inline \ + inline __attribute__((__always_inline__)) +# else +# define __always_inline inline +# endif +#endif + +/* Inline functions to access unaligned unsigned 32-bit integers */ +#ifndef get_unaligned_le32 +static inline uint32_t get_unaligned_le32(const uint8_t *buf) +{ + return (uint32_t)buf[0] + | ((uint32_t)buf[1] << 8) + | ((uint32_t)buf[2] << 16) + | ((uint32_t)buf[3] << 24); +} +#endif + +#ifndef get_unaligned_be32 +static inline uint32_t get_unaligned_be32(const uint8_t *buf) +{ + return (uint32_t)(buf[0] << 24) + | ((uint32_t)buf[1] << 16) + | ((uint32_t)buf[2] << 8) + | (uint32_t)buf[3]; +} +#endif + +#ifndef put_unaligned_le32 +static inline void put_unaligned_le32(uint32_t val, uint8_t *buf) +{ + buf[0] = (uint8_t)val; + buf[1] = (uint8_t)(val >> 8); + buf[2] = (uint8_t)(val >> 16); + buf[3] = (uint8_t)(val >> 24); +} +#endif + +#ifndef put_unaligned_be32 +static inline void put_unaligned_be32(uint32_t val, uint8_t *buf) +{ + buf[0] = (uint8_t)(val >> 24); + buf[1] = (uint8_t)(val >> 16); + buf[2] = (uint8_t)(val >> 8); + buf[3] = (uint8_t)val; +} +#endif + +/* + * Use get_unaligned_le32() also for aligned access for simplicity. On + * little endian systems, #define get_le32(ptr) (*(const uint32_t *)(ptr)) + * could save a few bytes in code size. + */ +#ifndef get_le32 +# define get_le32 get_unaligned_le32 +#endif + +#endif diff --git a/src/common/unix/xzminidec/src/xz_crc32.c b/src/common/unix/xzminidec/src/xz_crc32.c new file mode 100644 index 000000000..34532d14f --- /dev/null +++ b/src/common/unix/xzminidec/src/xz_crc32.c @@ -0,0 +1,59 @@ +/* + * CRC32 using the polynomial from IEEE-802.3 + * + * Authors: Lasse Collin + * Igor Pavlov + * + * This file has been put into the public domain. + * You can do whatever you want with this file. + */ + +/* + * This is not the fastest implementation, but it is pretty compact. + * The fastest versions of xz_crc32() on modern CPUs without hardware + * accelerated CRC instruction are 3-5 times as fast as this version, + * but they are bigger and use more memory for the lookup table. + */ + +#include "xz_private.h" + +/* + * STATIC_RW_DATA is used in the pre-boot environment on some architectures. + * See for details. + */ +#ifndef STATIC_RW_DATA +# define STATIC_RW_DATA static +#endif + +STATIC_RW_DATA uint32_t xz_crc32_table[256]; + +XZ_EXTERN void xz_crc32_init(void) +{ + const uint32_t poly = 0xEDB88320; + + uint32_t i; + uint32_t j; + uint32_t r; + + for (i = 0; i < 256; ++i) { + r = i; + for (j = 0; j < 8; ++j) + r = (r >> 1) ^ (poly & ~((r & 1) - 1)); + + xz_crc32_table[i] = r; + } + + return; +} + +XZ_EXTERN uint32_t xz_crc32(const uint8_t *buf, size_t size, uint32_t crc) +{ + crc = ~crc; + + while (size != 0) { + crc = xz_crc32_table[*buf++ ^ (crc & 0xFF)] ^ (crc >> 8); + --size; + } + + return ~crc; +} diff --git a/src/common/unix/xzminidec/src/xz_dec_bcj.c b/src/common/unix/xzminidec/src/xz_dec_bcj.c new file mode 100644 index 000000000..a768e6d28 --- /dev/null +++ b/src/common/unix/xzminidec/src/xz_dec_bcj.c @@ -0,0 +1,574 @@ +/* + * Branch/Call/Jump (BCJ) filter decoders + * + * Authors: Lasse Collin + * Igor Pavlov + * + * This file has been put into the public domain. + * You can do whatever you want with this file. + */ + +#include "xz_private.h" + +/* + * The rest of the file is inside this ifdef. It makes things a little more + * convenient when building without support for any BCJ filters. + */ +#ifdef XZ_DEC_BCJ + +struct xz_dec_bcj { + /* Type of the BCJ filter being used */ + enum { + BCJ_X86 = 4, /* x86 or x86-64 */ + BCJ_POWERPC = 5, /* Big endian only */ + BCJ_IA64 = 6, /* Big or little endian */ + BCJ_ARM = 7, /* Little endian only */ + BCJ_ARMTHUMB = 8, /* Little endian only */ + BCJ_SPARC = 9 /* Big or little endian */ + } type; + + /* + * Return value of the next filter in the chain. We need to preserve + * this information across calls, because we must not call the next + * filter anymore once it has returned XZ_STREAM_END. + */ + enum xz_ret ret; + + /* True if we are operating in single-call mode. */ + bool single_call; + + /* + * Absolute position relative to the beginning of the uncompressed + * data (in a single .xz Block). We care only about the lowest 32 + * bits so this doesn't need to be uint64_t even with big files. + */ + uint32_t pos; + + /* x86 filter state */ + uint32_t x86_prev_mask; + + /* Temporary space to hold the variables from struct xz_buf */ + uint8_t *out; + size_t out_pos; + size_t out_size; + + struct { + /* Amount of already filtered data in the beginning of buf */ + size_t filtered; + + /* Total amount of data currently stored in buf */ + size_t size; + + /* + * Buffer to hold a mix of filtered and unfiltered data. This + * needs to be big enough to hold Alignment + 2 * Look-ahead: + * + * Type Alignment Look-ahead + * x86 1 4 + * PowerPC 4 0 + * IA-64 16 0 + * ARM 4 0 + * ARM-Thumb 2 2 + * SPARC 4 0 + */ + uint8_t buf[16]; + } temp; +}; + +#ifdef XZ_DEC_X86 +/* + * This is used to test the most significant byte of a memory address + * in an x86 instruction. + */ +static inline int bcj_x86_test_msbyte(uint8_t b) +{ + return b == 0x00 || b == 0xFF; +} + +static size_t bcj_x86(struct xz_dec_bcj *s, uint8_t *buf, size_t size) +{ + static const bool mask_to_allowed_status[8] + = { true, true, true, false, true, false, false, false }; + + static const uint8_t mask_to_bit_num[8] = { 0, 1, 2, 2, 3, 3, 3, 3 }; + + size_t i; + size_t prev_pos = (size_t)-1; + uint32_t prev_mask = s->x86_prev_mask; + uint32_t src; + uint32_t dest; + uint32_t j; + uint8_t b; + + if (size <= 4) + return 0; + + size -= 4; + for (i = 0; i < size; ++i) { + if ((buf[i] & 0xFE) != 0xE8) + continue; + + prev_pos = i - prev_pos; + if (prev_pos > 3) { + prev_mask = 0; + } else { + prev_mask = (prev_mask << (prev_pos - 1)) & 7; + if (prev_mask != 0) { + b = buf[i + 4 - mask_to_bit_num[prev_mask]]; + if (!mask_to_allowed_status[prev_mask] + || bcj_x86_test_msbyte(b)) { + prev_pos = i; + prev_mask = (prev_mask << 1) | 1; + continue; + } + } + } + + prev_pos = i; + + if (bcj_x86_test_msbyte(buf[i + 4])) { + src = get_unaligned_le32(buf + i + 1); + while (true) { + dest = src - (s->pos + (uint32_t)i + 5); + if (prev_mask == 0) + break; + + j = mask_to_bit_num[prev_mask] * 8; + b = (uint8_t)(dest >> (24 - j)); + if (!bcj_x86_test_msbyte(b)) + break; + + src = dest ^ (((uint32_t)1 << (32 - j)) - 1); + } + + dest &= 0x01FFFFFF; + dest |= (uint32_t)0 - (dest & 0x01000000); + put_unaligned_le32(dest, buf + i + 1); + i += 4; + } else { + prev_mask = (prev_mask << 1) | 1; + } + } + + prev_pos = i - prev_pos; + s->x86_prev_mask = prev_pos > 3 ? 0 : prev_mask << (prev_pos - 1); + return i; +} +#endif + +#ifdef XZ_DEC_POWERPC +static size_t bcj_powerpc(struct xz_dec_bcj *s, uint8_t *buf, size_t size) +{ + size_t i; + uint32_t instr; + + for (i = 0; i + 4 <= size; i += 4) { + instr = get_unaligned_be32(buf + i); + if ((instr & 0xFC000003) == 0x48000001) { + instr &= 0x03FFFFFC; + instr -= s->pos + (uint32_t)i; + instr &= 0x03FFFFFC; + instr |= 0x48000001; + put_unaligned_be32(instr, buf + i); + } + } + + return i; +} +#endif + +#ifdef XZ_DEC_IA64 +static size_t bcj_ia64(struct xz_dec_bcj *s, uint8_t *buf, size_t size) +{ + static const uint8_t branch_table[32] = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 4, 4, 6, 6, 0, 0, 7, 7, + 4, 4, 0, 0, 4, 4, 0, 0 + }; + + /* + * The local variables take a little bit stack space, but it's less + * than what LZMA2 decoder takes, so it doesn't make sense to reduce + * stack usage here without doing that for the LZMA2 decoder too. + */ + + /* Loop counters */ + size_t i; + size_t j; + + /* Instruction slot (0, 1, or 2) in the 128-bit instruction word */ + uint32_t slot; + + /* Bitwise offset of the instruction indicated by slot */ + uint32_t bit_pos; + + /* bit_pos split into byte and bit parts */ + uint32_t byte_pos; + uint32_t bit_res; + + /* Address part of an instruction */ + uint32_t addr; + + /* Mask used to detect which instructions to convert */ + uint32_t mask; + + /* 41-bit instruction stored somewhere in the lowest 48 bits */ + uint64_t instr; + + /* Instruction normalized with bit_res for easier manipulation */ + uint64_t norm; + + for (i = 0; i + 16 <= size; i += 16) { + mask = branch_table[buf[i] & 0x1F]; + for (slot = 0, bit_pos = 5; slot < 3; ++slot, bit_pos += 41) { + if (((mask >> slot) & 1) == 0) + continue; + + byte_pos = bit_pos >> 3; + bit_res = bit_pos & 7; + instr = 0; + for (j = 0; j < 6; ++j) + instr |= (uint64_t)(buf[i + j + byte_pos]) + << (8 * j); + + norm = instr >> bit_res; + + if (((norm >> 37) & 0x0F) == 0x05 + && ((norm >> 9) & 0x07) == 0) { + addr = (norm >> 13) & 0x0FFFFF; + addr |= ((uint32_t)(norm >> 36) & 1) << 20; + addr <<= 4; + addr -= s->pos + (uint32_t)i; + addr >>= 4; + + norm &= ~((uint64_t)0x8FFFFF << 13); + norm |= (uint64_t)(addr & 0x0FFFFF) << 13; + norm |= (uint64_t)(addr & 0x100000) + << (36 - 20); + + instr &= (1 << bit_res) - 1; + instr |= norm << bit_res; + + for (j = 0; j < 6; j++) + buf[i + j + byte_pos] + = (uint8_t)(instr >> (8 * j)); + } + } + } + + return i; +} +#endif + +#ifdef XZ_DEC_ARM +static size_t bcj_arm(struct xz_dec_bcj *s, uint8_t *buf, size_t size) +{ + size_t i; + uint32_t addr; + + for (i = 0; i + 4 <= size; i += 4) { + if (buf[i + 3] == 0xEB) { + addr = (uint32_t)buf[i] | ((uint32_t)buf[i + 1] << 8) + | ((uint32_t)buf[i + 2] << 16); + addr <<= 2; + addr -= s->pos + (uint32_t)i + 8; + addr >>= 2; + buf[i] = (uint8_t)addr; + buf[i + 1] = (uint8_t)(addr >> 8); + buf[i + 2] = (uint8_t)(addr >> 16); + } + } + + return i; +} +#endif + +#ifdef XZ_DEC_ARMTHUMB +static size_t bcj_armthumb(struct xz_dec_bcj *s, uint8_t *buf, size_t size) +{ + size_t i; + uint32_t addr; + + for (i = 0; i + 4 <= size; i += 2) { + if ((buf[i + 1] & 0xF8) == 0xF0 + && (buf[i + 3] & 0xF8) == 0xF8) { + addr = (((uint32_t)buf[i + 1] & 0x07) << 19) + | ((uint32_t)buf[i] << 11) + | (((uint32_t)buf[i + 3] & 0x07) << 8) + | (uint32_t)buf[i + 2]; + addr <<= 1; + addr -= s->pos + (uint32_t)i + 4; + addr >>= 1; + buf[i + 1] = (uint8_t)(0xF0 | ((addr >> 19) & 0x07)); + buf[i] = (uint8_t)(addr >> 11); + buf[i + 3] = (uint8_t)(0xF8 | ((addr >> 8) & 0x07)); + buf[i + 2] = (uint8_t)addr; + i += 2; + } + } + + return i; +} +#endif + +#ifdef XZ_DEC_SPARC +static size_t bcj_sparc(struct xz_dec_bcj *s, uint8_t *buf, size_t size) +{ + size_t i; + uint32_t instr; + + for (i = 0; i + 4 <= size; i += 4) { + instr = get_unaligned_be32(buf + i); + if ((instr >> 22) == 0x100 || (instr >> 22) == 0x1FF) { + instr <<= 2; + instr -= s->pos + (uint32_t)i; + instr >>= 2; + instr = ((uint32_t)0x40000000 - (instr & 0x400000)) + | 0x40000000 | (instr & 0x3FFFFF); + put_unaligned_be32(instr, buf + i); + } + } + + return i; +} +#endif + +/* + * Apply the selected BCJ filter. Update *pos and s->pos to match the amount + * of data that got filtered. + * + * NOTE: This is implemented as a switch statement to avoid using function + * pointers, which could be problematic in the kernel boot code, which must + * avoid pointers to static data (at least on x86). + */ +static void bcj_apply(struct xz_dec_bcj *s, + uint8_t *buf, size_t *pos, size_t size) +{ + size_t filtered; + + buf += *pos; + size -= *pos; + + switch (s->type) { +#ifdef XZ_DEC_X86 + case BCJ_X86: + filtered = bcj_x86(s, buf, size); + break; +#endif +#ifdef XZ_DEC_POWERPC + case BCJ_POWERPC: + filtered = bcj_powerpc(s, buf, size); + break; +#endif +#ifdef XZ_DEC_IA64 + case BCJ_IA64: + filtered = bcj_ia64(s, buf, size); + break; +#endif +#ifdef XZ_DEC_ARM + case BCJ_ARM: + filtered = bcj_arm(s, buf, size); + break; +#endif +#ifdef XZ_DEC_ARMTHUMB + case BCJ_ARMTHUMB: + filtered = bcj_armthumb(s, buf, size); + break; +#endif +#ifdef XZ_DEC_SPARC + case BCJ_SPARC: + filtered = bcj_sparc(s, buf, size); + break; +#endif + default: + /* Never reached but silence compiler warnings. */ + filtered = 0; + break; + } + + *pos += filtered; + s->pos += filtered; +} + +/* + * Flush pending filtered data from temp to the output buffer. + * Move the remaining mixture of possibly filtered and unfiltered + * data to the beginning of temp. + */ +static void bcj_flush(struct xz_dec_bcj *s, struct xz_buf *b) +{ + size_t copy_size; + + copy_size = min_t(size_t, s->temp.filtered, b->out_size - b->out_pos); + memcpy(b->out + b->out_pos, s->temp.buf, copy_size); + b->out_pos += copy_size; + + s->temp.filtered -= copy_size; + s->temp.size -= copy_size; + memmove(s->temp.buf, s->temp.buf + copy_size, s->temp.size); +} + +/* + * The BCJ filter functions are primitive in sense that they process the + * data in chunks of 1-16 bytes. To hide this issue, this function does + * some buffering. + */ +XZ_EXTERN enum xz_ret xz_dec_bcj_run(struct xz_dec_bcj *s, + struct xz_dec_lzma2 *lzma2, + struct xz_buf *b) +{ + size_t out_start; + + /* + * Flush pending already filtered data to the output buffer. Return + * immediatelly if we couldn't flush everything, or if the next + * filter in the chain had already returned XZ_STREAM_END. + */ + if (s->temp.filtered > 0) { + bcj_flush(s, b); + if (s->temp.filtered > 0) + return XZ_OK; + + if (s->ret == XZ_STREAM_END) + return XZ_STREAM_END; + } + + /* + * If we have more output space than what is currently pending in + * temp, copy the unfiltered data from temp to the output buffer + * and try to fill the output buffer by decoding more data from the + * next filter in the chain. Apply the BCJ filter on the new data + * in the output buffer. If everything cannot be filtered, copy it + * to temp and rewind the output buffer position accordingly. + * + * This needs to be always run when temp.size == 0 to handle a special + * case where the output buffer is full and the next filter has no + * more output coming but hasn't returned XZ_STREAM_END yet. + */ + if (s->temp.size < b->out_size - b->out_pos || s->temp.size == 0) { + out_start = b->out_pos; + memcpy(b->out + b->out_pos, s->temp.buf, s->temp.size); + b->out_pos += s->temp.size; + + s->ret = xz_dec_lzma2_run(lzma2, b); + if (s->ret != XZ_STREAM_END + && (s->ret != XZ_OK || s->single_call)) + return s->ret; + + bcj_apply(s, b->out, &out_start, b->out_pos); + + /* + * As an exception, if the next filter returned XZ_STREAM_END, + * we can do that too, since the last few bytes that remain + * unfiltered are meant to remain unfiltered. + */ + if (s->ret == XZ_STREAM_END) + return XZ_STREAM_END; + + s->temp.size = b->out_pos - out_start; + b->out_pos -= s->temp.size; + memcpy(s->temp.buf, b->out + b->out_pos, s->temp.size); + + /* + * If there wasn't enough input to the next filter to fill + * the output buffer with unfiltered data, there's no point + * to try decoding more data to temp. + */ + if (b->out_pos + s->temp.size < b->out_size) + return XZ_OK; + } + + /* + * We have unfiltered data in temp. If the output buffer isn't full + * yet, try to fill the temp buffer by decoding more data from the + * next filter. Apply the BCJ filter on temp. Then we hopefully can + * fill the actual output buffer by copying filtered data from temp. + * A mix of filtered and unfiltered data may be left in temp; it will + * be taken care on the next call to this function. + */ + if (b->out_pos < b->out_size) { + /* Make b->out{,_pos,_size} temporarily point to s->temp. */ + s->out = b->out; + s->out_pos = b->out_pos; + s->out_size = b->out_size; + b->out = s->temp.buf; + b->out_pos = s->temp.size; + b->out_size = sizeof(s->temp.buf); + + s->ret = xz_dec_lzma2_run(lzma2, b); + + s->temp.size = b->out_pos; + b->out = s->out; + b->out_pos = s->out_pos; + b->out_size = s->out_size; + + if (s->ret != XZ_OK && s->ret != XZ_STREAM_END) + return s->ret; + + bcj_apply(s, s->temp.buf, &s->temp.filtered, s->temp.size); + + /* + * If the next filter returned XZ_STREAM_END, we mark that + * everything is filtered, since the last unfiltered bytes + * of the stream are meant to be left as is. + */ + if (s->ret == XZ_STREAM_END) + s->temp.filtered = s->temp.size; + + bcj_flush(s, b); + if (s->temp.filtered > 0) + return XZ_OK; + } + + return s->ret; +} + +XZ_EXTERN struct xz_dec_bcj *xz_dec_bcj_create(bool single_call) +{ + struct xz_dec_bcj *s = kmalloc(sizeof(*s), GFP_KERNEL); + if (s != NULL) + s->single_call = single_call; + + return s; +} + +XZ_EXTERN enum xz_ret xz_dec_bcj_reset(struct xz_dec_bcj *s, uint8_t id) +{ + switch (id) { +#ifdef XZ_DEC_X86 + case BCJ_X86: +#endif +#ifdef XZ_DEC_POWERPC + case BCJ_POWERPC: +#endif +#ifdef XZ_DEC_IA64 + case BCJ_IA64: +#endif +#ifdef XZ_DEC_ARM + case BCJ_ARM: +#endif +#ifdef XZ_DEC_ARMTHUMB + case BCJ_ARMTHUMB: +#endif +#ifdef XZ_DEC_SPARC + case BCJ_SPARC: +#endif + break; + + default: + /* Unsupported Filter ID */ + return XZ_OPTIONS_ERROR; + } + + s->type = id; + s->ret = XZ_OK; + s->pos = 0; + s->x86_prev_mask = 0; + s->temp.filtered = 0; + s->temp.size = 0; + + return XZ_OK; +} + +#endif diff --git a/src/common/unix/xzminidec/src/xz_dec_lzma2.c b/src/common/unix/xzminidec/src/xz_dec_lzma2.c new file mode 100644 index 000000000..70309066c --- /dev/null +++ b/src/common/unix/xzminidec/src/xz_dec_lzma2.c @@ -0,0 +1,1173 @@ +/* + * LZMA2 decoder + * + * Authors: Lasse Collin + * Igor Pavlov + * + * This file has been put into the public domain. + * You can do whatever you want with this file. + */ + +#include "xz_private.h" +#include "xz_lzma2.h" + +/* + * Range decoder initialization eats the first five bytes of each LZMA chunk. + */ +#define RC_INIT_BYTES 5 + +/* + * Minimum number of usable input buffer to safely decode one LZMA symbol. + * The worst case is that we decode 22 bits using probabilities and 26 + * direct bits. This may decode at maximum of 20 bytes of input. However, + * lzma_main() does an extra normalization before returning, thus we + * need to put 21 here. + */ +#define LZMA_IN_REQUIRED 21 + +/* + * Dictionary (history buffer) + * + * These are always true: + * start <= pos <= full <= end + * pos <= limit <= end + * + * In multi-call mode, also these are true: + * end == size + * size <= size_max + * allocated <= size + * + * Most of these variables are size_t to support single-call mode, + * in which the dictionary variables address the actual output + * buffer directly. + */ +struct dictionary { + /* Beginning of the history buffer */ + uint8_t *buf; + + /* Old position in buf (before decoding more data) */ + size_t start; + + /* Position in buf */ + size_t pos; + + /* + * How full dictionary is. This is used to detect corrupt input that + * would read beyond the beginning of the uncompressed stream. + */ + size_t full; + + /* Write limit; we don't write to buf[limit] or later bytes. */ + size_t limit; + + /* + * End of the dictionary buffer. In multi-call mode, this is + * the same as the dictionary size. In single-call mode, this + * indicates the size of the output buffer. + */ + size_t end; + + /* + * Size of the dictionary as specified in Block Header. This is used + * together with "full" to detect corrupt input that would make us + * read beyond the beginning of the uncompressed stream. + */ + uint32_t size; + + /* + * Maximum allowed dictionary size in multi-call mode. + * This is ignored in single-call mode. + */ + uint32_t size_max; + + /* + * Amount of memory currently allocated for the dictionary. + * This is used only with XZ_DYNALLOC. (With XZ_PREALLOC, + * size_max is always the same as the allocated size.) + */ + uint32_t allocated; + + /* Operation mode */ + enum xz_mode mode; +}; + +/* Range decoder */ +struct rc_dec { + uint32_t range; + uint32_t code; + + /* + * Number of initializing bytes remaining to be read + * by rc_read_init(). + */ + uint32_t init_bytes_left; + + /* + * Buffer from which we read our input. It can be either + * temp.buf or the caller-provided input buffer. + */ + const uint8_t *in; + size_t in_pos; + size_t in_limit; +}; + +/* Probabilities for a length decoder. */ +struct lzma_len_dec { + /* Probability of match length being at least 10 */ + uint16_t choice; + + /* Probability of match length being at least 18 */ + uint16_t choice2; + + /* Probabilities for match lengths 2-9 */ + uint16_t low[POS_STATES_MAX][LEN_LOW_SYMBOLS]; + + /* Probabilities for match lengths 10-17 */ + uint16_t mid[POS_STATES_MAX][LEN_MID_SYMBOLS]; + + /* Probabilities for match lengths 18-273 */ + uint16_t high[LEN_HIGH_SYMBOLS]; +}; + +struct lzma_dec { + /* Distances of latest four matches */ + uint32_t rep0; + uint32_t rep1; + uint32_t rep2; + uint32_t rep3; + + /* Types of the most recently seen LZMA symbols */ + enum lzma_state state; + + /* + * Length of a match. This is updated so that dict_repeat can + * be called again to finish repeating the whole match. + */ + uint32_t len; + + /* + * LZMA properties or related bit masks (number of literal + * context bits, a mask dervied from the number of literal + * position bits, and a mask dervied from the number + * position bits) + */ + uint32_t lc; + uint32_t literal_pos_mask; /* (1 << lp) - 1 */ + uint32_t pos_mask; /* (1 << pb) - 1 */ + + /* If 1, it's a match. Otherwise it's a single 8-bit literal. */ + uint16_t is_match[STATES][POS_STATES_MAX]; + + /* If 1, it's a repeated match. The distance is one of rep0 .. rep3. */ + uint16_t is_rep[STATES]; + + /* + * If 0, distance of a repeated match is rep0. + * Otherwise check is_rep1. + */ + uint16_t is_rep0[STATES]; + + /* + * If 0, distance of a repeated match is rep1. + * Otherwise check is_rep2. + */ + uint16_t is_rep1[STATES]; + + /* If 0, distance of a repeated match is rep2. Otherwise it is rep3. */ + uint16_t is_rep2[STATES]; + + /* + * If 1, the repeated match has length of one byte. Otherwise + * the length is decoded from rep_len_decoder. + */ + uint16_t is_rep0_long[STATES][POS_STATES_MAX]; + + /* + * Probability tree for the highest two bits of the match + * distance. There is a separate probability tree for match + * lengths of 2 (i.e. MATCH_LEN_MIN), 3, 4, and [5, 273]. + */ + uint16_t dist_slot[DIST_STATES][DIST_SLOTS]; + + /* + * Probility trees for additional bits for match distance + * when the distance is in the range [4, 127]. + */ + uint16_t dist_special[FULL_DISTANCES - DIST_MODEL_END]; + + /* + * Probability tree for the lowest four bits of a match + * distance that is equal to or greater than 128. + */ + uint16_t dist_align[ALIGN_SIZE]; + + /* Length of a normal match */ + struct lzma_len_dec match_len_dec; + + /* Length of a repeated match */ + struct lzma_len_dec rep_len_dec; + + /* Probabilities of literals */ + uint16_t literal[LITERAL_CODERS_MAX][LITERAL_CODER_SIZE]; +}; + +struct lzma2_dec { + /* Position in xz_dec_lzma2_run(). */ + enum lzma2_seq { + SEQ_CONTROL, + SEQ_UNCOMPRESSED_1, + SEQ_UNCOMPRESSED_2, + SEQ_COMPRESSED_0, + SEQ_COMPRESSED_1, + SEQ_PROPERTIES, + SEQ_LZMA_PREPARE, + SEQ_LZMA_RUN, + SEQ_COPY + } sequence; + + /* Next position after decoding the compressed size of the chunk. */ + enum lzma2_seq next_sequence; + + /* Uncompressed size of LZMA chunk (2 MiB at maximum) */ + uint32_t uncompressed; + + /* + * Compressed size of LZMA chunk or compressed/uncompressed + * size of uncompressed chunk (64 KiB at maximum) + */ + uint32_t compressed; + + /* + * True if dictionary reset is needed. This is false before + * the first chunk (LZMA or uncompressed). + */ + bool need_dict_reset; + + /* + * True if new LZMA properties are needed. This is false + * before the first LZMA chunk. + */ + bool need_props; +}; + +struct xz_dec_lzma2 { + /* + * The order below is important on x86 to reduce code size and + * it shouldn't hurt on other platforms. Everything up to and + * including lzma.pos_mask are in the first 128 bytes on x86-32, + * which allows using smaller instructions to access those + * variables. On x86-64, fewer variables fit into the first 128 + * bytes, but this is still the best order without sacrificing + * the readability by splitting the structures. + */ + struct rc_dec rc; + struct dictionary dict; + struct lzma2_dec lzma2; + struct lzma_dec lzma; + + /* + * Temporary buffer which holds small number of input bytes between + * decoder calls. See lzma2_lzma() for details. + */ + struct { + uint32_t size; + uint8_t buf[3 * LZMA_IN_REQUIRED]; + } temp; +}; + +/************** + * Dictionary * + **************/ + +/* + * Reset the dictionary state. When in single-call mode, set up the beginning + * of the dictionary to point to the actual output buffer. + */ +static void dict_reset(struct dictionary *dict, struct xz_buf *b) +{ + if (DEC_IS_SINGLE(dict->mode)) { + dict->buf = b->out + b->out_pos; + dict->end = b->out_size - b->out_pos; + } + + dict->start = 0; + dict->pos = 0; + dict->limit = 0; + dict->full = 0; +} + +/* Set dictionary write limit */ +static void dict_limit(struct dictionary *dict, size_t out_max) +{ + if (dict->end - dict->pos <= out_max) + dict->limit = dict->end; + else + dict->limit = dict->pos + out_max; +} + +/* Return true if at least one byte can be written into the dictionary. */ +static inline bool dict_has_space(const struct dictionary *dict) +{ + return dict->pos < dict->limit; +} + +/* + * Get a byte from the dictionary at the given distance. The distance is + * assumed to valid, or as a special case, zero when the dictionary is + * still empty. This special case is needed for single-call decoding to + * avoid writing a '\0' to the end of the destination buffer. + */ +static inline uint32_t dict_get(const struct dictionary *dict, uint32_t dist) +{ + size_t offset = dict->pos - dist - 1; + + if (dist >= dict->pos) + offset += dict->end; + + return dict->full > 0 ? dict->buf[offset] : 0; +} + +/* + * Put one byte into the dictionary. It is assumed that there is space for it. + */ +static inline void dict_put(struct dictionary *dict, uint8_t byte) +{ + dict->buf[dict->pos++] = byte; + + if (dict->full < dict->pos) + dict->full = dict->pos; +} + +/* + * Repeat given number of bytes from the given distance. If the distance is + * invalid, false is returned. On success, true is returned and *len is + * updated to indicate how many bytes were left to be repeated. + */ +static bool dict_repeat(struct dictionary *dict, uint32_t *len, uint32_t dist) +{ + size_t back; + uint32_t left; + + if (dist >= dict->full || dist >= dict->size) + return false; + + left = min_t(size_t, dict->limit - dict->pos, *len); + *len -= left; + + back = dict->pos - dist - 1; + if (dist >= dict->pos) + back += dict->end; + + do { + dict->buf[dict->pos++] = dict->buf[back++]; + if (back == dict->end) + back = 0; + } while (--left > 0); + + if (dict->full < dict->pos) + dict->full = dict->pos; + + return true; +} + +/* Copy uncompressed data as is from input to dictionary and output buffers. */ +static void dict_uncompressed(struct dictionary *dict, struct xz_buf *b, + uint32_t *left) +{ + size_t copy_size; + + while (*left > 0 && b->in_pos < b->in_size + && b->out_pos < b->out_size) { + copy_size = min(b->in_size - b->in_pos, + b->out_size - b->out_pos); + if (copy_size > dict->end - dict->pos) + copy_size = dict->end - dict->pos; + if (copy_size > *left) + copy_size = *left; + + *left -= copy_size; + + memcpy(dict->buf + dict->pos, b->in + b->in_pos, copy_size); + dict->pos += copy_size; + + if (dict->full < dict->pos) + dict->full = dict->pos; + + if (DEC_IS_MULTI(dict->mode)) { + if (dict->pos == dict->end) + dict->pos = 0; + + memcpy(b->out + b->out_pos, b->in + b->in_pos, + copy_size); + } + + dict->start = dict->pos; + + b->out_pos += copy_size; + b->in_pos += copy_size; + } +} + +/* + * Flush pending data from dictionary to b->out. It is assumed that there is + * enough space in b->out. This is guaranteed because caller uses dict_limit() + * before decoding data into the dictionary. + */ +static uint32_t dict_flush(struct dictionary *dict, struct xz_buf *b) +{ + size_t copy_size = dict->pos - dict->start; + + if (DEC_IS_MULTI(dict->mode)) { + if (dict->pos == dict->end) + dict->pos = 0; + + memcpy(b->out + b->out_pos, dict->buf + dict->start, + copy_size); + } + + dict->start = dict->pos; + b->out_pos += copy_size; + return copy_size; +} + +/***************** + * Range decoder * + *****************/ + +/* Reset the range decoder. */ +static void rc_reset(struct rc_dec *rc) +{ + rc->range = (uint32_t)-1; + rc->code = 0; + rc->init_bytes_left = RC_INIT_BYTES; +} + +/* + * Read the first five initial bytes into rc->code if they haven't been + * read already. (Yes, the first byte gets completely ignored.) + */ +static bool rc_read_init(struct rc_dec *rc, struct xz_buf *b) +{ + while (rc->init_bytes_left > 0) { + if (b->in_pos == b->in_size) + return false; + + rc->code = (rc->code << 8) + b->in[b->in_pos++]; + --rc->init_bytes_left; + } + + return true; +} + +/* Return true if there may not be enough input for the next decoding loop. */ +static inline bool rc_limit_exceeded(const struct rc_dec *rc) +{ + return rc->in_pos > rc->in_limit; +} + +/* + * Return true if it is possible (from point of view of range decoder) that + * we have reached the end of the LZMA chunk. + */ +static inline bool rc_is_finished(const struct rc_dec *rc) +{ + return rc->code == 0; +} + +/* Read the next input byte if needed. */ +static inline __always_inline void rc_normalize(struct rc_dec *rc) +{ + if (rc->range < RC_TOP_VALUE) { + rc->range <<= RC_SHIFT_BITS; + rc->code = (rc->code << RC_SHIFT_BITS) + rc->in[rc->in_pos++]; + } +} + +/* + * Decode one bit. In some versions, this function has been splitted in three + * functions so that the compiler is supposed to be able to more easily avoid + * an extra branch. In this particular version of the LZMA decoder, this + * doesn't seem to be a good idea (tested with GCC 3.3.6, 3.4.6, and 4.3.3 + * on x86). Using a non-splitted version results in nicer looking code too. + * + * NOTE: This must return an int. Do not make it return a bool or the speed + * of the code generated by GCC 3.x decreases 10-15 %. (GCC 4.3 doesn't care, + * and it generates 10-20 % faster code than GCC 3.x from this file anyway.) + */ +static inline __always_inline int rc_bit(struct rc_dec *rc, uint16_t *prob) +{ + uint32_t bound; + int bit; + + rc_normalize(rc); + bound = (rc->range >> RC_BIT_MODEL_TOTAL_BITS) * *prob; + if (rc->code < bound) { + rc->range = bound; + *prob += (RC_BIT_MODEL_TOTAL - *prob) >> RC_MOVE_BITS; + bit = 0; + } else { + rc->range -= bound; + rc->code -= bound; + *prob -= *prob >> RC_MOVE_BITS; + bit = 1; + } + + return bit; +} + +/* Decode a bittree starting from the most significant bit. */ +static inline __always_inline uint32_t rc_bittree(struct rc_dec *rc, + uint16_t *probs, uint32_t limit) +{ + uint32_t symbol = 1; + + do { + if (rc_bit(rc, &probs[symbol])) + symbol = (symbol << 1) + 1; + else + symbol <<= 1; + } while (symbol < limit); + + return symbol; +} + +/* Decode a bittree starting from the least significant bit. */ +static inline __always_inline void rc_bittree_reverse(struct rc_dec *rc, + uint16_t *probs, + uint32_t *dest, uint32_t limit) +{ + uint32_t symbol = 1; + uint32_t i = 0; + + do { + if (rc_bit(rc, &probs[symbol])) { + symbol = (symbol << 1) + 1; + *dest += 1 << i; + } else { + symbol <<= 1; + } + } while (++i < limit); +} + +/* Decode direct bits (fixed fifty-fifty probability) */ +static inline void rc_direct(struct rc_dec *rc, uint32_t *dest, uint32_t limit) +{ + uint32_t mask; + + do { + rc_normalize(rc); + rc->range >>= 1; + rc->code -= rc->range; + mask = (uint32_t)0 - (rc->code >> 31); + rc->code += rc->range & mask; + *dest = (*dest << 1) + (mask + 1); + } while (--limit > 0); +} + +/******** + * LZMA * + ********/ + +/* Get pointer to literal coder probability array. */ +static uint16_t *lzma_literal_probs(struct xz_dec_lzma2 *s) +{ + uint32_t prev_byte = dict_get(&s->dict, 0); + uint32_t low = prev_byte >> (8 - s->lzma.lc); + uint32_t high = (s->dict.pos & s->lzma.literal_pos_mask) << s->lzma.lc; + return s->lzma.literal[low + high]; +} + +/* Decode a literal (one 8-bit byte) */ +static void lzma_literal(struct xz_dec_lzma2 *s) +{ + uint16_t *probs; + uint32_t symbol; + uint32_t match_byte; + uint32_t match_bit; + uint32_t offset; + uint32_t i; + + probs = lzma_literal_probs(s); + + if (lzma_state_is_literal(s->lzma.state)) { + symbol = rc_bittree(&s->rc, probs, 0x100); + } else { + symbol = 1; + match_byte = dict_get(&s->dict, s->lzma.rep0) << 1; + offset = 0x100; + + do { + match_bit = match_byte & offset; + match_byte <<= 1; + i = offset + match_bit + symbol; + + if (rc_bit(&s->rc, &probs[i])) { + symbol = (symbol << 1) + 1; + offset &= match_bit; + } else { + symbol <<= 1; + offset &= ~match_bit; + } + } while (symbol < 0x100); + } + + dict_put(&s->dict, (uint8_t)symbol); + lzma_state_literal(&s->lzma.state); +} + +/* Decode the length of the match into s->lzma.len. */ +static void lzma_len(struct xz_dec_lzma2 *s, struct lzma_len_dec *l, + uint32_t pos_state) +{ + uint16_t *probs; + uint32_t limit; + + if (!rc_bit(&s->rc, &l->choice)) { + probs = l->low[pos_state]; + limit = LEN_LOW_SYMBOLS; + s->lzma.len = MATCH_LEN_MIN; + } else { + if (!rc_bit(&s->rc, &l->choice2)) { + probs = l->mid[pos_state]; + limit = LEN_MID_SYMBOLS; + s->lzma.len = MATCH_LEN_MIN + LEN_LOW_SYMBOLS; + } else { + probs = l->high; + limit = LEN_HIGH_SYMBOLS; + s->lzma.len = MATCH_LEN_MIN + LEN_LOW_SYMBOLS + + LEN_MID_SYMBOLS; + } + } + + s->lzma.len += rc_bittree(&s->rc, probs, limit) - limit; +} + +/* Decode a match. The distance will be stored in s->lzma.rep0. */ +static void lzma_match(struct xz_dec_lzma2 *s, uint32_t pos_state) +{ + uint16_t *probs; + uint32_t dist_slot; + uint32_t limit; + + lzma_state_match(&s->lzma.state); + + s->lzma.rep3 = s->lzma.rep2; + s->lzma.rep2 = s->lzma.rep1; + s->lzma.rep1 = s->lzma.rep0; + + lzma_len(s, &s->lzma.match_len_dec, pos_state); + + probs = s->lzma.dist_slot[lzma_get_dist_state(s->lzma.len)]; + dist_slot = rc_bittree(&s->rc, probs, DIST_SLOTS) - DIST_SLOTS; + + if (dist_slot < DIST_MODEL_START) { + s->lzma.rep0 = dist_slot; + } else { + limit = (dist_slot >> 1) - 1; + s->lzma.rep0 = 2 + (dist_slot & 1); + + if (dist_slot < DIST_MODEL_END) { + s->lzma.rep0 <<= limit; + probs = s->lzma.dist_special + s->lzma.rep0 + - dist_slot - 1; + rc_bittree_reverse(&s->rc, probs, + &s->lzma.rep0, limit); + } else { + rc_direct(&s->rc, &s->lzma.rep0, limit - ALIGN_BITS); + s->lzma.rep0 <<= ALIGN_BITS; + rc_bittree_reverse(&s->rc, s->lzma.dist_align, + &s->lzma.rep0, ALIGN_BITS); + } + } +} + +/* + * Decode a repeated match. The distance is one of the four most recently + * seen matches. The distance will be stored in s->lzma.rep0. + */ +static void lzma_rep_match(struct xz_dec_lzma2 *s, uint32_t pos_state) +{ + uint32_t tmp; + + if (!rc_bit(&s->rc, &s->lzma.is_rep0[s->lzma.state])) { + if (!rc_bit(&s->rc, &s->lzma.is_rep0_long[ + s->lzma.state][pos_state])) { + lzma_state_short_rep(&s->lzma.state); + s->lzma.len = 1; + return; + } + } else { + if (!rc_bit(&s->rc, &s->lzma.is_rep1[s->lzma.state])) { + tmp = s->lzma.rep1; + } else { + if (!rc_bit(&s->rc, &s->lzma.is_rep2[s->lzma.state])) { + tmp = s->lzma.rep2; + } else { + tmp = s->lzma.rep3; + s->lzma.rep3 = s->lzma.rep2; + } + + s->lzma.rep2 = s->lzma.rep1; + } + + s->lzma.rep1 = s->lzma.rep0; + s->lzma.rep0 = tmp; + } + + lzma_state_long_rep(&s->lzma.state); + lzma_len(s, &s->lzma.rep_len_dec, pos_state); +} + +/* LZMA decoder core */ +static bool lzma_main(struct xz_dec_lzma2 *s) +{ + uint32_t pos_state; + + /* + * If the dictionary was reached during the previous call, try to + * finish the possibly pending repeat in the dictionary. + */ + if (dict_has_space(&s->dict) && s->lzma.len > 0) + dict_repeat(&s->dict, &s->lzma.len, s->lzma.rep0); + + /* + * Decode more LZMA symbols. One iteration may consume up to + * LZMA_IN_REQUIRED - 1 bytes. + */ + while (dict_has_space(&s->dict) && !rc_limit_exceeded(&s->rc)) { + pos_state = s->dict.pos & s->lzma.pos_mask; + + if (!rc_bit(&s->rc, &s->lzma.is_match[ + s->lzma.state][pos_state])) { + lzma_literal(s); + } else { + if (rc_bit(&s->rc, &s->lzma.is_rep[s->lzma.state])) + lzma_rep_match(s, pos_state); + else + lzma_match(s, pos_state); + + if (!dict_repeat(&s->dict, &s->lzma.len, s->lzma.rep0)) + return false; + } + } + + /* + * Having the range decoder always normalized when we are outside + * this function makes it easier to correctly handle end of the chunk. + */ + rc_normalize(&s->rc); + + return true; +} + +/* + * Reset the LZMA decoder and range decoder state. Dictionary is nore reset + * here, because LZMA state may be reset without resetting the dictionary. + */ +static void lzma_reset(struct xz_dec_lzma2 *s) +{ + uint16_t *probs; + size_t i; + + s->lzma.state = STATE_LIT_LIT; + s->lzma.rep0 = 0; + s->lzma.rep1 = 0; + s->lzma.rep2 = 0; + s->lzma.rep3 = 0; + + /* + * All probabilities are initialized to the same value. This hack + * makes the code smaller by avoiding a separate loop for each + * probability array. + * + * This could be optimized so that only that part of literal + * probabilities that are actually required. In the common case + * we would write 12 KiB less. + */ + probs = s->lzma.is_match[0]; + for (i = 0; i < PROBS_TOTAL; ++i) + probs[i] = RC_BIT_MODEL_TOTAL / 2; + + rc_reset(&s->rc); +} + +/* + * Decode and validate LZMA properties (lc/lp/pb) and calculate the bit masks + * from the decoded lp and pb values. On success, the LZMA decoder state is + * reset and true is returned. + */ +static bool lzma_props(struct xz_dec_lzma2 *s, uint8_t props) +{ + if (props > (4 * 5 + 4) * 9 + 8) + return false; + + s->lzma.pos_mask = 0; + while (props >= 9 * 5) { + props -= 9 * 5; + ++s->lzma.pos_mask; + } + + s->lzma.pos_mask = (1 << s->lzma.pos_mask) - 1; + + s->lzma.literal_pos_mask = 0; + while (props >= 9) { + props -= 9; + ++s->lzma.literal_pos_mask; + } + + s->lzma.lc = props; + + if (s->lzma.lc + s->lzma.literal_pos_mask > 4) + return false; + + s->lzma.literal_pos_mask = (1 << s->lzma.literal_pos_mask) - 1; + + lzma_reset(s); + + return true; +} + +/********* + * LZMA2 * + *********/ + +/* + * The LZMA decoder assumes that if the input limit (s->rc.in_limit) hasn't + * been exceeded, it is safe to read up to LZMA_IN_REQUIRED bytes. This + * wrapper function takes care of making the LZMA decoder's assumption safe. + * + * As long as there is plenty of input left to be decoded in the current LZMA + * chunk, we decode directly from the caller-supplied input buffer until + * there's LZMA_IN_REQUIRED bytes left. Those remaining bytes are copied into + * s->temp.buf, which (hopefully) gets filled on the next call to this + * function. We decode a few bytes from the temporary buffer so that we can + * continue decoding from the caller-supplied input buffer again. + */ +static bool lzma2_lzma(struct xz_dec_lzma2 *s, struct xz_buf *b) +{ + size_t in_avail; + uint32_t tmp; + + in_avail = b->in_size - b->in_pos; + if (s->temp.size > 0 || s->lzma2.compressed == 0) { + tmp = 2 * LZMA_IN_REQUIRED - s->temp.size; + if (tmp > s->lzma2.compressed - s->temp.size) + tmp = s->lzma2.compressed - s->temp.size; + if (tmp > in_avail) + tmp = in_avail; + + memcpy(s->temp.buf + s->temp.size, b->in + b->in_pos, tmp); + + if (s->temp.size + tmp == s->lzma2.compressed) { + memzero(s->temp.buf + s->temp.size + tmp, + sizeof(s->temp.buf) + - s->temp.size - tmp); + s->rc.in_limit = s->temp.size + tmp; + } else if (s->temp.size + tmp < LZMA_IN_REQUIRED) { + s->temp.size += tmp; + b->in_pos += tmp; + return true; + } else { + s->rc.in_limit = s->temp.size + tmp - LZMA_IN_REQUIRED; + } + + s->rc.in = s->temp.buf; + s->rc.in_pos = 0; + + if (!lzma_main(s) || s->rc.in_pos > s->temp.size + tmp) + return false; + + s->lzma2.compressed -= s->rc.in_pos; + + if (s->rc.in_pos < s->temp.size) { + s->temp.size -= s->rc.in_pos; + memmove(s->temp.buf, s->temp.buf + s->rc.in_pos, + s->temp.size); + return true; + } + + b->in_pos += s->rc.in_pos - s->temp.size; + s->temp.size = 0; + } + + in_avail = b->in_size - b->in_pos; + if (in_avail >= LZMA_IN_REQUIRED) { + s->rc.in = b->in; + s->rc.in_pos = b->in_pos; + + if (in_avail >= s->lzma2.compressed + LZMA_IN_REQUIRED) + s->rc.in_limit = b->in_pos + s->lzma2.compressed; + else + s->rc.in_limit = b->in_size - LZMA_IN_REQUIRED; + + if (!lzma_main(s)) + return false; + + in_avail = s->rc.in_pos - b->in_pos; + if (in_avail > s->lzma2.compressed) + return false; + + s->lzma2.compressed -= in_avail; + b->in_pos = s->rc.in_pos; + } + + in_avail = b->in_size - b->in_pos; + if (in_avail < LZMA_IN_REQUIRED) { + if (in_avail > s->lzma2.compressed) + in_avail = s->lzma2.compressed; + + memcpy(s->temp.buf, b->in + b->in_pos, in_avail); + s->temp.size = in_avail; + b->in_pos += in_avail; + } + + return true; +} + +/* + * Take care of the LZMA2 control layer, and forward the job of actual LZMA + * decoding or copying of uncompressed chunks to other functions. + */ +XZ_EXTERN enum xz_ret xz_dec_lzma2_run(struct xz_dec_lzma2 *s, + struct xz_buf *b) +{ + uint32_t tmp; + + while (b->in_pos < b->in_size || s->lzma2.sequence == SEQ_LZMA_RUN) { + switch (s->lzma2.sequence) { + case SEQ_CONTROL: + /* + * LZMA2 control byte + * + * Exact values: + * 0x00 End marker + * 0x01 Dictionary reset followed by + * an uncompressed chunk + * 0x02 Uncompressed chunk (no dictionary reset) + * + * Highest three bits (s->control & 0xE0): + * 0xE0 Dictionary reset, new properties and state + * reset, followed by LZMA compressed chunk + * 0xC0 New properties and state reset, followed + * by LZMA compressed chunk (no dictionary + * reset) + * 0xA0 State reset using old properties, + * followed by LZMA compressed chunk (no + * dictionary reset) + * 0x80 LZMA chunk (no dictionary or state reset) + * + * For LZMA compressed chunks, the lowest five bits + * (s->control & 1F) are the highest bits of the + * uncompressed size (bits 16-20). + * + * A new LZMA2 stream must begin with a dictionary + * reset. The first LZMA chunk must set new + * properties and reset the LZMA state. + * + * Values that don't match anything described above + * are invalid and we return XZ_DATA_ERROR. + */ + tmp = b->in[b->in_pos++]; + + if (tmp == 0x00) + return XZ_STREAM_END; + + if (tmp >= 0xE0 || tmp == 0x01) { + s->lzma2.need_props = true; + s->lzma2.need_dict_reset = false; + dict_reset(&s->dict, b); + } else if (s->lzma2.need_dict_reset) { + return XZ_DATA_ERROR; + } + + if (tmp >= 0x80) { + s->lzma2.uncompressed = (tmp & 0x1F) << 16; + s->lzma2.sequence = SEQ_UNCOMPRESSED_1; + + if (tmp >= 0xC0) { + /* + * When there are new properties, + * state reset is done at + * SEQ_PROPERTIES. + */ + s->lzma2.need_props = false; + s->lzma2.next_sequence + = SEQ_PROPERTIES; + + } else if (s->lzma2.need_props) { + return XZ_DATA_ERROR; + + } else { + s->lzma2.next_sequence + = SEQ_LZMA_PREPARE; + if (tmp >= 0xA0) + lzma_reset(s); + } + } else { + if (tmp > 0x02) + return XZ_DATA_ERROR; + + s->lzma2.sequence = SEQ_COMPRESSED_0; + s->lzma2.next_sequence = SEQ_COPY; + } + + break; + + case SEQ_UNCOMPRESSED_1: + s->lzma2.uncompressed + += (uint32_t)b->in[b->in_pos++] << 8; + s->lzma2.sequence = SEQ_UNCOMPRESSED_2; + break; + + case SEQ_UNCOMPRESSED_2: + s->lzma2.uncompressed + += (uint32_t)b->in[b->in_pos++] + 1; + s->lzma2.sequence = SEQ_COMPRESSED_0; + break; + + case SEQ_COMPRESSED_0: + s->lzma2.compressed + = (uint32_t)b->in[b->in_pos++] << 8; + s->lzma2.sequence = SEQ_COMPRESSED_1; + break; + + case SEQ_COMPRESSED_1: + s->lzma2.compressed + += (uint32_t)b->in[b->in_pos++] + 1; + s->lzma2.sequence = s->lzma2.next_sequence; + break; + + case SEQ_PROPERTIES: + if (!lzma_props(s, b->in[b->in_pos++])) + return XZ_DATA_ERROR; + + s->lzma2.sequence = SEQ_LZMA_PREPARE; + + /* fallthrough */ + case SEQ_LZMA_PREPARE: + if (s->lzma2.compressed < RC_INIT_BYTES) + return XZ_DATA_ERROR; + + if (!rc_read_init(&s->rc, b)) + return XZ_OK; + + s->lzma2.compressed -= RC_INIT_BYTES; + s->lzma2.sequence = SEQ_LZMA_RUN; + + /* fallthrough */ + case SEQ_LZMA_RUN: + /* + * Set dictionary limit to indicate how much we want + * to be encoded at maximum. Decode new data into the + * dictionary. Flush the new data from dictionary to + * b->out. Check if we finished decoding this chunk. + * In case the dictionary got full but we didn't fill + * the output buffer yet, we may run this loop + * multiple times without changing s->lzma2.sequence. + */ + dict_limit(&s->dict, min_t(size_t, + b->out_size - b->out_pos, + s->lzma2.uncompressed)); + if (!lzma2_lzma(s, b)) + return XZ_DATA_ERROR; + + s->lzma2.uncompressed -= dict_flush(&s->dict, b); + + if (s->lzma2.uncompressed == 0) { + if (s->lzma2.compressed > 0 || s->lzma.len > 0 + || !rc_is_finished(&s->rc)) + return XZ_DATA_ERROR; + + rc_reset(&s->rc); + s->lzma2.sequence = SEQ_CONTROL; + + } else if (b->out_pos == b->out_size + || (b->in_pos == b->in_size + && s->temp.size + < s->lzma2.compressed)) { + return XZ_OK; + } + + break; + + case SEQ_COPY: + dict_uncompressed(&s->dict, b, &s->lzma2.compressed); + if (s->lzma2.compressed > 0) + return XZ_OK; + + s->lzma2.sequence = SEQ_CONTROL; + break; + } + } + + return XZ_OK; +} + +XZ_EXTERN struct xz_dec_lzma2 *xz_dec_lzma2_create(enum xz_mode mode, + uint32_t dict_max) +{ + struct xz_dec_lzma2 *s = kmalloc(sizeof(*s), GFP_KERNEL); + if (s == NULL) + return NULL; + + s->dict.mode = mode; + s->dict.size_max = dict_max; + + if (DEC_IS_PREALLOC(mode)) { + s->dict.buf = vmalloc(dict_max); + if (s->dict.buf == NULL) { + kfree(s); + return NULL; + } + } else if (DEC_IS_DYNALLOC(mode)) { + s->dict.buf = NULL; + s->dict.allocated = 0; + } + + return s; +} + +XZ_EXTERN enum xz_ret xz_dec_lzma2_reset(struct xz_dec_lzma2 *s, uint8_t props) +{ + /* This limits dictionary size to 3 GiB to keep parsing simpler. */ + if (props > 39) + return XZ_OPTIONS_ERROR; + + s->dict.size = 2 + (props & 1); + s->dict.size <<= (props >> 1) + 11; + + if (DEC_IS_MULTI(s->dict.mode)) { + if (s->dict.size > s->dict.size_max) + return XZ_MEMLIMIT_ERROR; + + s->dict.end = s->dict.size; + + if (DEC_IS_DYNALLOC(s->dict.mode)) { + if (s->dict.allocated < s->dict.size) { + vfree(s->dict.buf); + s->dict.buf = vmalloc(s->dict.size); + if (s->dict.buf == NULL) { + s->dict.allocated = 0; + return XZ_MEM_ERROR; + } + } + } + } + + s->lzma.len = 0; + + s->lzma2.sequence = SEQ_CONTROL; + s->lzma2.need_dict_reset = true; + + s->temp.size = 0; + + return XZ_OK; +} + +XZ_EXTERN void xz_dec_lzma2_end(struct xz_dec_lzma2 *s) +{ + if (DEC_IS_MULTI(s->dict.mode)) + vfree(s->dict.buf); + + kfree(s); +} diff --git a/src/common/unix/xzminidec/src/xz_dec_stream.c b/src/common/unix/xzminidec/src/xz_dec_stream.c new file mode 100644 index 000000000..6ba94eb65 --- /dev/null +++ b/src/common/unix/xzminidec/src/xz_dec_stream.c @@ -0,0 +1,829 @@ +/* + * .xz Stream decoder + * + * Author: Lasse Collin + * + * This file has been put into the public domain. + * You can do whatever you want with this file. + */ + +#include "xz_private.h" +#include "xz_stream.h" + +/* Hash used to validate the Index field */ +struct xz_dec_hash { + vli_type unpadded; + vli_type uncompressed; + uint32_t crc32; +}; + +struct xz_dec { + /* Position in dec_main() */ + enum { + SEQ_STREAM_HEADER, + SEQ_BLOCK_START, + SEQ_BLOCK_HEADER, + SEQ_BLOCK_UNCOMPRESS, + SEQ_BLOCK_PADDING, + SEQ_BLOCK_CHECK, + SEQ_INDEX, + SEQ_INDEX_PADDING, + SEQ_INDEX_CRC32, + SEQ_STREAM_FOOTER + } sequence; + + /* Position in variable-length integers and Check fields */ + uint32_t pos; + + /* Variable-length integer decoded by dec_vli() */ + vli_type vli; + + /* Saved in_pos and out_pos */ + size_t in_start; + size_t out_start; + + /* CRC32 value in Block or Index */ + uint32_t crc32; + + /* Type of the integrity check calculated from uncompressed data */ + enum xz_check check_type; + + /* Operation mode */ + enum xz_mode mode; + + /* + * True if the next call to xz_dec_run() is allowed to return + * XZ_BUF_ERROR. + */ + bool allow_buf_error; + + /* Information stored in Block Header */ + struct { + /* + * Value stored in the Compressed Size field, or + * VLI_UNKNOWN if Compressed Size is not present. + */ + vli_type compressed; + + /* + * Value stored in the Uncompressed Size field, or + * VLI_UNKNOWN if Uncompressed Size is not present. + */ + vli_type uncompressed; + + /* Size of the Block Header field */ + uint32_t size; + } block_header; + + /* Information collected when decoding Blocks */ + struct { + /* Observed compressed size of the current Block */ + vli_type compressed; + + /* Observed uncompressed size of the current Block */ + vli_type uncompressed; + + /* Number of Blocks decoded so far */ + vli_type count; + + /* + * Hash calculated from the Block sizes. This is used to + * validate the Index field. + */ + struct xz_dec_hash hash; + } block; + + /* Variables needed when verifying the Index field */ + struct { + /* Position in dec_index() */ + enum { + SEQ_INDEX_COUNT, + SEQ_INDEX_UNPADDED, + SEQ_INDEX_UNCOMPRESSED + } sequence; + + /* Size of the Index in bytes */ + vli_type size; + + /* Number of Records (matches block.count in valid files) */ + vli_type count; + + /* + * Hash calculated from the Records (matches block.hash in + * valid files). + */ + struct xz_dec_hash hash; + } index; + + /* + * Temporary buffer needed to hold Stream Header, Block Header, + * and Stream Footer. The Block Header is the biggest (1 KiB) + * so we reserve space according to that. buf[] has to be aligned + * to a multiple of four bytes; the size_t variables before it + * should guarantee this. + */ + struct { + size_t pos; + size_t size; + uint8_t buf[1024]; + } temp; + + struct xz_dec_lzma2 *lzma2; + +#ifdef XZ_DEC_BCJ + struct xz_dec_bcj *bcj; + bool bcj_active; +#endif +}; + +#ifdef XZ_DEC_ANY_CHECK +/* Sizes of the Check field with different Check IDs */ +static const uint8_t check_sizes[16] = { + 0, + 4, 4, 4, + 8, 8, 8, + 16, 16, 16, + 32, 32, 32, + 64, 64, 64 +}; +#endif + +/* + * Fill s->temp by copying data starting from b->in[b->in_pos]. Caller + * must have set s->temp.pos to indicate how much data we are supposed + * to copy into s->temp.buf. Return true once s->temp.pos has reached + * s->temp.size. + */ +static bool fill_temp(struct xz_dec *s, struct xz_buf *b) +{ + size_t copy_size = min_t(size_t, + b->in_size - b->in_pos, s->temp.size - s->temp.pos); + + memcpy(s->temp.buf + s->temp.pos, b->in + b->in_pos, copy_size); + b->in_pos += copy_size; + s->temp.pos += copy_size; + + if (s->temp.pos == s->temp.size) { + s->temp.pos = 0; + return true; + } + + return false; +} + +/* Decode a variable-length integer (little-endian base-128 encoding) */ +static enum xz_ret dec_vli(struct xz_dec *s, const uint8_t *in, + size_t *in_pos, size_t in_size) +{ + uint8_t byte; + + if (s->pos == 0) + s->vli = 0; + + while (*in_pos < in_size) { + byte = in[*in_pos]; + ++*in_pos; + + s->vli |= (vli_type)(byte & 0x7F) << s->pos; + + if ((byte & 0x80) == 0) { + /* Don't allow non-minimal encodings. */ + if (byte == 0 && s->pos != 0) + return XZ_DATA_ERROR; + + s->pos = 0; + return XZ_STREAM_END; + } + + s->pos += 7; + if (s->pos == 7 * VLI_BYTES_MAX) + return XZ_DATA_ERROR; + } + + return XZ_OK; +} + +/* + * Decode the Compressed Data field from a Block. Update and validate + * the observed compressed and uncompressed sizes of the Block so that + * they don't exceed the values possibly stored in the Block Header + * (validation assumes that no integer overflow occurs, since vli_type + * is normally uint64_t). Update the CRC32 if presence of the CRC32 + * field was indicated in Stream Header. + * + * Once the decoding is finished, validate that the observed sizes match + * the sizes possibly stored in the Block Header. Update the hash and + * Block count, which are later used to validate the Index field. + */ +static enum xz_ret dec_block(struct xz_dec *s, struct xz_buf *b) +{ + enum xz_ret ret; + + s->in_start = b->in_pos; + s->out_start = b->out_pos; + +#ifdef XZ_DEC_BCJ + if (s->bcj_active) + ret = xz_dec_bcj_run(s->bcj, s->lzma2, b); + else +#endif + ret = xz_dec_lzma2_run(s->lzma2, b); + + s->block.compressed += b->in_pos - s->in_start; + s->block.uncompressed += b->out_pos - s->out_start; + + /* + * There is no need to separately check for VLI_UNKNOWN, since + * the observed sizes are always smaller than VLI_UNKNOWN. + */ + if (s->block.compressed > s->block_header.compressed + || s->block.uncompressed + > s->block_header.uncompressed) + return XZ_DATA_ERROR; + + if (s->check_type == XZ_CHECK_CRC32) + s->crc32 = xz_crc32(b->out + s->out_start, + b->out_pos - s->out_start, s->crc32); + + if (ret == XZ_STREAM_END) { + if (s->block_header.compressed != VLI_UNKNOWN + && s->block_header.compressed + != s->block.compressed) + return XZ_DATA_ERROR; + + if (s->block_header.uncompressed != VLI_UNKNOWN + && s->block_header.uncompressed + != s->block.uncompressed) + return XZ_DATA_ERROR; + + s->block.hash.unpadded += s->block_header.size + + s->block.compressed; + +#ifdef XZ_DEC_ANY_CHECK + s->block.hash.unpadded += check_sizes[s->check_type]; +#else + if (s->check_type == XZ_CHECK_CRC32) + s->block.hash.unpadded += 4; +#endif + + s->block.hash.uncompressed += s->block.uncompressed; + s->block.hash.crc32 = xz_crc32( + (const uint8_t *)&s->block.hash, + sizeof(s->block.hash), s->block.hash.crc32); + + ++s->block.count; + } + + return ret; +} + +/* Update the Index size and the CRC32 value. */ +static void index_update(struct xz_dec *s, const struct xz_buf *b) +{ + size_t in_used = b->in_pos - s->in_start; + s->index.size += in_used; + s->crc32 = xz_crc32(b->in + s->in_start, in_used, s->crc32); +} + +/* + * Decode the Number of Records, Unpadded Size, and Uncompressed Size + * fields from the Index field. That is, Index Padding and CRC32 are not + * decoded by this function. + * + * This can return XZ_OK (more input needed), XZ_STREAM_END (everything + * successfully decoded), or XZ_DATA_ERROR (input is corrupt). + */ +static enum xz_ret dec_index(struct xz_dec *s, struct xz_buf *b) +{ + enum xz_ret ret; + + do { + ret = dec_vli(s, b->in, &b->in_pos, b->in_size); + if (ret != XZ_STREAM_END) { + index_update(s, b); + return ret; + } + + switch (s->index.sequence) { + case SEQ_INDEX_COUNT: + s->index.count = s->vli; + + /* + * Validate that the Number of Records field + * indicates the same number of Records as + * there were Blocks in the Stream. + */ + if (s->index.count != s->block.count) + return XZ_DATA_ERROR; + + s->index.sequence = SEQ_INDEX_UNPADDED; + break; + + case SEQ_INDEX_UNPADDED: + s->index.hash.unpadded += s->vli; + s->index.sequence = SEQ_INDEX_UNCOMPRESSED; + break; + + case SEQ_INDEX_UNCOMPRESSED: + s->index.hash.uncompressed += s->vli; + s->index.hash.crc32 = xz_crc32( + (const uint8_t *)&s->index.hash, + sizeof(s->index.hash), + s->index.hash.crc32); + --s->index.count; + s->index.sequence = SEQ_INDEX_UNPADDED; + break; + } + } while (s->index.count > 0); + + return XZ_STREAM_END; +} + +/* + * Validate that the next four input bytes match the value of s->crc32. + * s->pos must be zero when starting to validate the first byte. + */ +static enum xz_ret crc32_validate(struct xz_dec *s, struct xz_buf *b) +{ + do { + if (b->in_pos == b->in_size) + return XZ_OK; + + if (((s->crc32 >> s->pos) & 0xFF) != b->in[b->in_pos++]) + return XZ_DATA_ERROR; + + s->pos += 8; + + } while (s->pos < 32); + + s->crc32 = 0; + s->pos = 0; + + return XZ_STREAM_END; +} + +#ifdef XZ_DEC_ANY_CHECK +/* + * Skip over the Check field when the Check ID is not supported. + * Returns true once the whole Check field has been skipped over. + */ +static bool check_skip(struct xz_dec *s, struct xz_buf *b) +{ + while (s->pos < check_sizes[s->check_type]) { + if (b->in_pos == b->in_size) + return false; + + ++b->in_pos; + ++s->pos; + } + + s->pos = 0; + + return true; +} +#endif + +/* Decode the Stream Header field (the first 12 bytes of the .xz Stream). */ +static enum xz_ret dec_stream_header(struct xz_dec *s) +{ + if (!memeq(s->temp.buf, HEADER_MAGIC, HEADER_MAGIC_SIZE)) + return XZ_FORMAT_ERROR; + + if (xz_crc32(s->temp.buf + HEADER_MAGIC_SIZE, 2, 0) + != get_le32(s->temp.buf + HEADER_MAGIC_SIZE + 2)) + return XZ_DATA_ERROR; + + if (s->temp.buf[HEADER_MAGIC_SIZE] != 0) + return XZ_OPTIONS_ERROR; + + /* + * Of integrity checks, we support only none (Check ID = 0) and + * CRC32 (Check ID = 1). However, if XZ_DEC_ANY_CHECK is defined, + * we will accept other check types too, but then the check won't + * be verified and a warning (XZ_UNSUPPORTED_CHECK) will be given. + */ + s->check_type = s->temp.buf[HEADER_MAGIC_SIZE + 1]; + +#ifdef XZ_DEC_ANY_CHECK + if (s->check_type > XZ_CHECK_MAX) + return XZ_OPTIONS_ERROR; + + if (s->check_type > XZ_CHECK_CRC32) + return XZ_UNSUPPORTED_CHECK; +#else + if (s->check_type > XZ_CHECK_CRC32) + return XZ_OPTIONS_ERROR; +#endif + + return XZ_OK; +} + +/* Decode the Stream Footer field (the last 12 bytes of the .xz Stream) */ +static enum xz_ret dec_stream_footer(struct xz_dec *s) +{ + if (!memeq(s->temp.buf + 10, FOOTER_MAGIC, FOOTER_MAGIC_SIZE)) + return XZ_DATA_ERROR; + + if (xz_crc32(s->temp.buf + 4, 6, 0) != get_le32(s->temp.buf)) + return XZ_DATA_ERROR; + + /* + * Validate Backward Size. Note that we never added the size of the + * Index CRC32 field to s->index.size, thus we use s->index.size / 4 + * instead of s->index.size / 4 - 1. + */ + if ((s->index.size >> 2) != get_le32(s->temp.buf + 4)) + return XZ_DATA_ERROR; + + if (s->temp.buf[8] != 0 || s->temp.buf[9] != s->check_type) + return XZ_DATA_ERROR; + + /* + * Use XZ_STREAM_END instead of XZ_OK to be more convenient + * for the caller. + */ + return XZ_STREAM_END; +} + +/* Decode the Block Header and initialize the filter chain. */ +static enum xz_ret dec_block_header(struct xz_dec *s) +{ + enum xz_ret ret; + + /* + * Validate the CRC32. We know that the temp buffer is at least + * eight bytes so this is safe. + */ + s->temp.size -= 4; + if (xz_crc32(s->temp.buf, s->temp.size, 0) + != get_le32(s->temp.buf + s->temp.size)) + return XZ_DATA_ERROR; + + s->temp.pos = 2; + + /* + * Catch unsupported Block Flags. We support only one or two filters + * in the chain, so we catch that with the same test. + */ +#ifdef XZ_DEC_BCJ + if (s->temp.buf[1] & 0x3E) +#else + if (s->temp.buf[1] & 0x3F) +#endif + return XZ_OPTIONS_ERROR; + + /* Compressed Size */ + if (s->temp.buf[1] & 0x40) { + if (dec_vli(s, s->temp.buf, &s->temp.pos, s->temp.size) + != XZ_STREAM_END) + return XZ_DATA_ERROR; + + s->block_header.compressed = s->vli; + } else { + s->block_header.compressed = VLI_UNKNOWN; + } + + /* Uncompressed Size */ + if (s->temp.buf[1] & 0x80) { + if (dec_vli(s, s->temp.buf, &s->temp.pos, s->temp.size) + != XZ_STREAM_END) + return XZ_DATA_ERROR; + + s->block_header.uncompressed = s->vli; + } else { + s->block_header.uncompressed = VLI_UNKNOWN; + } + +#ifdef XZ_DEC_BCJ + /* If there are two filters, the first one must be a BCJ filter. */ + s->bcj_active = s->temp.buf[1] & 0x01; + if (s->bcj_active) { + if (s->temp.size - s->temp.pos < 2) + return XZ_OPTIONS_ERROR; + + ret = xz_dec_bcj_reset(s->bcj, s->temp.buf[s->temp.pos++]); + if (ret != XZ_OK) + return ret; + + /* + * We don't support custom start offset, + * so Size of Properties must be zero. + */ + if (s->temp.buf[s->temp.pos++] != 0x00) + return XZ_OPTIONS_ERROR; + } +#endif + + /* Valid Filter Flags always take at least two bytes. */ + if (s->temp.size - s->temp.pos < 2) + return XZ_DATA_ERROR; + + /* Filter ID = LZMA2 */ + if (s->temp.buf[s->temp.pos++] != 0x21) + return XZ_OPTIONS_ERROR; + + /* Size of Properties = 1-byte Filter Properties */ + if (s->temp.buf[s->temp.pos++] != 0x01) + return XZ_OPTIONS_ERROR; + + /* Filter Properties contains LZMA2 dictionary size. */ + if (s->temp.size - s->temp.pos < 1) + return XZ_DATA_ERROR; + + ret = xz_dec_lzma2_reset(s->lzma2, s->temp.buf[s->temp.pos++]); + if (ret != XZ_OK) + return ret; + + /* The rest must be Header Padding. */ + while (s->temp.pos < s->temp.size) + if (s->temp.buf[s->temp.pos++] != 0x00) + return XZ_OPTIONS_ERROR; + + s->temp.pos = 0; + s->block.compressed = 0; + s->block.uncompressed = 0; + + return XZ_OK; +} + +static enum xz_ret dec_main(struct xz_dec *s, struct xz_buf *b) +{ + enum xz_ret ret; + + /* + * Store the start position for the case when we are in the middle + * of the Index field. + */ + s->in_start = b->in_pos; + + while (true) { + switch (s->sequence) { + case SEQ_STREAM_HEADER: + /* + * Stream Header is copied to s->temp, and then + * decoded from there. This way if the caller + * gives us only little input at a time, we can + * still keep the Stream Header decoding code + * simple. Similar approach is used in many places + * in this file. + */ + if (!fill_temp(s, b)) + return XZ_OK; + + /* + * If dec_stream_header() returns + * XZ_UNSUPPORTED_CHECK, it is still possible + * to continue decoding if working in multi-call + * mode. Thus, update s->sequence before calling + * dec_stream_header(). + */ + s->sequence = SEQ_BLOCK_START; + + ret = dec_stream_header(s); + if (ret != XZ_OK) + return ret; + + /* fallthrough */ + case SEQ_BLOCK_START: + /* We need one byte of input to continue. */ + if (b->in_pos == b->in_size) + return XZ_OK; + + /* See if this is the beginning of the Index field. */ + if (b->in[b->in_pos] == 0) { + s->in_start = b->in_pos++; + s->sequence = SEQ_INDEX; + break; + } + + /* + * Calculate the size of the Block Header and + * prepare to decode it. + */ + s->block_header.size + = ((uint32_t)b->in[b->in_pos] + 1) * 4; + + s->temp.size = s->block_header.size; + s->temp.pos = 0; + s->sequence = SEQ_BLOCK_HEADER; + + /* fallthrough */ + case SEQ_BLOCK_HEADER: + if (!fill_temp(s, b)) + return XZ_OK; + + ret = dec_block_header(s); + if (ret != XZ_OK) + return ret; + + s->sequence = SEQ_BLOCK_UNCOMPRESS; + + /* fallthrough */ + case SEQ_BLOCK_UNCOMPRESS: + ret = dec_block(s, b); + if (ret != XZ_STREAM_END) + return ret; + + s->sequence = SEQ_BLOCK_PADDING; + + /* fallthrough */ + case SEQ_BLOCK_PADDING: + /* + * Size of Compressed Data + Block Padding + * must be a multiple of four. We don't need + * s->block.compressed for anything else + * anymore, so we use it here to test the size + * of the Block Padding field. + */ + while (s->block.compressed & 3) { + if (b->in_pos == b->in_size) + return XZ_OK; + + if (b->in[b->in_pos++] != 0) + return XZ_DATA_ERROR; + + ++s->block.compressed; + } + + s->sequence = SEQ_BLOCK_CHECK; + + /* fallthrough */ + case SEQ_BLOCK_CHECK: + if (s->check_type == XZ_CHECK_CRC32) { + ret = crc32_validate(s, b); + if (ret != XZ_STREAM_END) + return ret; + } +#ifdef XZ_DEC_ANY_CHECK + else if (!check_skip(s, b)) { + return XZ_OK; + } +#endif + + s->sequence = SEQ_BLOCK_START; + break; + + case SEQ_INDEX: + ret = dec_index(s, b); + if (ret != XZ_STREAM_END) + return ret; + + s->sequence = SEQ_INDEX_PADDING; + + /* fallthrough */ + case SEQ_INDEX_PADDING: + while ((s->index.size + (b->in_pos - s->in_start)) + & 3) { + if (b->in_pos == b->in_size) { + index_update(s, b); + return XZ_OK; + } + + if (b->in[b->in_pos++] != 0) + return XZ_DATA_ERROR; + } + + /* Finish the CRC32 value and Index size. */ + index_update(s, b); + + /* Compare the hashes to validate the Index field. */ + if (!memeq(&s->block.hash, &s->index.hash, + sizeof(s->block.hash))) + return XZ_DATA_ERROR; + + s->sequence = SEQ_INDEX_CRC32; + + /* fallthrough */ + case SEQ_INDEX_CRC32: + ret = crc32_validate(s, b); + if (ret != XZ_STREAM_END) + return ret; + + s->temp.size = STREAM_HEADER_SIZE; + s->sequence = SEQ_STREAM_FOOTER; + + /* fallthrough */ + case SEQ_STREAM_FOOTER: + if (!fill_temp(s, b)) + return XZ_OK; + + return dec_stream_footer(s); + } + } + + /* Never reached */ +} + +/* + * xz_dec_run() is a wrapper for dec_main() to handle some special cases in + * multi-call and single-call decoding. + * + * In multi-call mode, we must return XZ_BUF_ERROR when it seems clear that we + * are not going to make any progress anymore. This is to prevent the caller + * from calling us infinitely when the input file is truncated or otherwise + * corrupt. Since zlib-style API allows that the caller fills the input buffer + * only when the decoder doesn't produce any new output, we have to be careful + * to avoid returning XZ_BUF_ERROR too easily: XZ_BUF_ERROR is returned only + * after the second consecutive call to xz_dec_run() that makes no progress. + * + * In single-call mode, if we couldn't decode everything and no error + * occurred, either the input is truncated or the output buffer is too small. + * Since we know that the last input byte never produces any output, we know + * that if all the input was consumed and decoding wasn't finished, the file + * must be corrupt. Otherwise the output buffer has to be too small or the + * file is corrupt in a way that decoding it produces too big output. + * + * If single-call decoding fails, we reset b->in_pos and b->out_pos back to + * their original values. This is because with some filter chains there won't + * be any valid uncompressed data in the output buffer unless the decoding + * actually succeeds (that's the price to pay of using the output buffer as + * the workspace). + */ +XZ_EXTERN enum xz_ret xz_dec_run(struct xz_dec *s, struct xz_buf *b) +{ + size_t in_start; + size_t out_start; + enum xz_ret ret; + + if (DEC_IS_SINGLE(s->mode)) + xz_dec_reset(s); + + in_start = b->in_pos; + out_start = b->out_pos; + ret = dec_main(s, b); + + if (DEC_IS_SINGLE(s->mode)) { + if (ret == XZ_OK) + ret = b->in_pos == b->in_size + ? XZ_DATA_ERROR : XZ_BUF_ERROR; + + if (ret != XZ_STREAM_END) { + b->in_pos = in_start; + b->out_pos = out_start; + } + + } else if (ret == XZ_OK && in_start == b->in_pos + && out_start == b->out_pos) { + if (s->allow_buf_error) + ret = XZ_BUF_ERROR; + + s->allow_buf_error = true; + } else { + s->allow_buf_error = false; + } + + return ret; +} + +XZ_EXTERN struct xz_dec *xz_dec_init(enum xz_mode mode, uint32_t dict_max) +{ + struct xz_dec *s = kmalloc(sizeof(*s), GFP_KERNEL); + if (s == NULL) + return NULL; + + s->mode = mode; + +#ifdef XZ_DEC_BCJ + s->bcj = xz_dec_bcj_create(DEC_IS_SINGLE(mode)); + if (s->bcj == NULL) + goto error_bcj; +#endif + + s->lzma2 = xz_dec_lzma2_create(mode, dict_max); + if (s->lzma2 == NULL) + goto error_lzma2; + + xz_dec_reset(s); + return s; + +error_lzma2: +#ifdef XZ_DEC_BCJ + xz_dec_bcj_end(s->bcj); +error_bcj: +#endif + kfree(s); + return NULL; +} + +XZ_EXTERN void xz_dec_reset(struct xz_dec *s) +{ + s->sequence = SEQ_STREAM_HEADER; + s->allow_buf_error = false; + s->pos = 0; + s->crc32 = 0; + memzero(&s->block, sizeof(s->block)); + memzero(&s->index, sizeof(s->index)); + s->temp.pos = 0; + s->temp.size = STREAM_HEADER_SIZE; +} + +XZ_EXTERN void xz_dec_end(struct xz_dec *s) +{ + if (s != NULL) { + xz_dec_lzma2_end(s->lzma2); +#ifdef XZ_DEC_BCJ + xz_dec_bcj_end(s->bcj); +#endif + kfree(s); + } +} diff --git a/src/common/unix/xzminidec/src/xz_lzma2.h b/src/common/unix/xzminidec/src/xz_lzma2.h new file mode 100644 index 000000000..071d67bee --- /dev/null +++ b/src/common/unix/xzminidec/src/xz_lzma2.h @@ -0,0 +1,204 @@ +/* + * LZMA2 definitions + * + * Authors: Lasse Collin + * Igor Pavlov + * + * This file has been put into the public domain. + * You can do whatever you want with this file. + */ + +#ifndef XZ_LZMA2_H +#define XZ_LZMA2_H + +/* Range coder constants */ +#define RC_SHIFT_BITS 8 +#define RC_TOP_BITS 24 +#define RC_TOP_VALUE (1 << RC_TOP_BITS) +#define RC_BIT_MODEL_TOTAL_BITS 11 +#define RC_BIT_MODEL_TOTAL (1 << RC_BIT_MODEL_TOTAL_BITS) +#define RC_MOVE_BITS 5 + +/* + * Maximum number of position states. A position state is the lowest pb + * number of bits of the current uncompressed offset. In some places there + * are different sets of probabilities for different position states. + */ +#define POS_STATES_MAX (1 << 4) + +/* + * This enum is used to track which LZMA symbols have occurred most recently + * and in which order. This information is used to predict the next symbol. + * + * Symbols: + * - Literal: One 8-bit byte + * - Match: Repeat a chunk of data at some distance + * - Long repeat: Multi-byte match at a recently seen distance + * - Short repeat: One-byte repeat at a recently seen distance + * + * The symbol names are in from STATE_oldest_older_previous. REP means + * either short or long repeated match, and NONLIT means any non-literal. + */ +enum lzma_state { + STATE_LIT_LIT, + STATE_MATCH_LIT_LIT, + STATE_REP_LIT_LIT, + STATE_SHORTREP_LIT_LIT, + STATE_MATCH_LIT, + STATE_REP_LIT, + STATE_SHORTREP_LIT, + STATE_LIT_MATCH, + STATE_LIT_LONGREP, + STATE_LIT_SHORTREP, + STATE_NONLIT_MATCH, + STATE_NONLIT_REP +}; + +/* Total number of states */ +#define STATES 12 + +/* The lowest 7 states indicate that the previous state was a literal. */ +#define LIT_STATES 7 + +/* Indicate that the latest symbol was a literal. */ +static inline void lzma_state_literal(enum lzma_state *state) +{ + if (*state <= STATE_SHORTREP_LIT_LIT) + *state = STATE_LIT_LIT; + else if (*state <= STATE_LIT_SHORTREP) + *state -= 3; + else + *state -= 6; +} + +/* Indicate that the latest symbol was a match. */ +static inline void lzma_state_match(enum lzma_state *state) +{ + *state = *state < LIT_STATES ? STATE_LIT_MATCH : STATE_NONLIT_MATCH; +} + +/* Indicate that the latest state was a long repeated match. */ +static inline void lzma_state_long_rep(enum lzma_state *state) +{ + *state = *state < LIT_STATES ? STATE_LIT_LONGREP : STATE_NONLIT_REP; +} + +/* Indicate that the latest symbol was a short match. */ +static inline void lzma_state_short_rep(enum lzma_state *state) +{ + *state = *state < LIT_STATES ? STATE_LIT_SHORTREP : STATE_NONLIT_REP; +} + +/* Test if the previous symbol was a literal. */ +static inline bool lzma_state_is_literal(enum lzma_state state) +{ + return state < LIT_STATES; +} + +/* Each literal coder is divided in three sections: + * - 0x001-0x0FF: Without match byte + * - 0x101-0x1FF: With match byte; match bit is 0 + * - 0x201-0x2FF: With match byte; match bit is 1 + * + * Match byte is used when the previous LZMA symbol was something else than + * a literal (that is, it was some kind of match). + */ +#define LITERAL_CODER_SIZE 0x300 + +/* Maximum number of literal coders */ +#define LITERAL_CODERS_MAX (1 << 4) + +/* Minimum length of a match is two bytes. */ +#define MATCH_LEN_MIN 2 + +/* Match length is encoded with 4, 5, or 10 bits. + * + * Length Bits + * 2-9 4 = Choice=0 + 3 bits + * 10-17 5 = Choice=1 + Choice2=0 + 3 bits + * 18-273 10 = Choice=1 + Choice2=1 + 8 bits + */ +#define LEN_LOW_BITS 3 +#define LEN_LOW_SYMBOLS (1 << LEN_LOW_BITS) +#define LEN_MID_BITS 3 +#define LEN_MID_SYMBOLS (1 << LEN_MID_BITS) +#define LEN_HIGH_BITS 8 +#define LEN_HIGH_SYMBOLS (1 << LEN_HIGH_BITS) +#define LEN_SYMBOLS (LEN_LOW_SYMBOLS + LEN_MID_SYMBOLS + LEN_HIGH_SYMBOLS) + +/* + * Maximum length of a match is 273 which is a result of the encoding + * described above. + */ +#define MATCH_LEN_MAX (MATCH_LEN_MIN + LEN_SYMBOLS - 1) + +/* + * Different sets of probabilities are used for match distances that have + * very short match length: Lengths of 2, 3, and 4 bytes have a separate + * set of probabilities for each length. The matches with longer length + * use a shared set of probabilities. + */ +#define DIST_STATES 4 + +/* + * Get the index of the appropriate probability array for decoding + * the distance slot. + */ +static inline uint32_t lzma_get_dist_state(uint32_t len) +{ + return len < DIST_STATES + MATCH_LEN_MIN + ? len - MATCH_LEN_MIN : DIST_STATES - 1; +} + +/* + * The highest two bits of a 32-bit match distance are encoded using six bits. + * This six-bit value is called a distance slot. This way encoding a 32-bit + * value takes 6-36 bits, larger values taking more bits. + */ +#define DIST_SLOT_BITS 6 +#define DIST_SLOTS (1 << DIST_SLOT_BITS) + +/* Match distances up to 127 are fully encoded using probabilities. Since + * the highest two bits (distance slot) are always encoded using six bits, + * the distances 0-3 don't need any additional bits to encode, since the + * distance slot itself is the same as the actual distance. DIST_MODEL_START + * indicates the first distance slot where at least one additional bit is + * needed. + */ +#define DIST_MODEL_START 4 + +/* + * Match distances greater than 127 are encoded in three pieces: + * - distance slot: the highest two bits + * - direct bits: 2-26 bits below the highest two bits + * - alignment bits: four lowest bits + * + * Direct bits don't use any probabilities. + * + * The distance slot value of 14 is for distances 128-191. + */ +#define DIST_MODEL_END 14 + +/* Distance slots that indicate a distance <= 127. */ +#define FULL_DISTANCES_BITS (DIST_MODEL_END / 2) +#define FULL_DISTANCES (1 << FULL_DISTANCES_BITS) + +/* + * For match distances greater than 127, only the highest two bits and the + * lowest four bits (alignment) is encoded using probabilities. + */ +#define ALIGN_BITS 4 +#define ALIGN_SIZE (1 << ALIGN_BITS) +#define ALIGN_MASK (ALIGN_SIZE - 1) + +/* Total number of all probability variables */ +#define PROBS_TOTAL (1846 + LITERAL_CODERS_MAX * LITERAL_CODER_SIZE) + +/* + * LZMA remembers the four most recent match distances. Reusing these + * distances tends to take less space than re-encoding the actual + * distance value. + */ +#define REPS 4 + +#endif diff --git a/src/common/unix/xzminidec/src/xz_private.h b/src/common/unix/xzminidec/src/xz_private.h new file mode 100644 index 000000000..482b90f36 --- /dev/null +++ b/src/common/unix/xzminidec/src/xz_private.h @@ -0,0 +1,156 @@ +/* + * Private includes and definitions + * + * Author: Lasse Collin + * + * This file has been put into the public domain. + * You can do whatever you want with this file. + */ + +#ifndef XZ_PRIVATE_H +#define XZ_PRIVATE_H + +#ifdef __KERNEL__ +# include +# include +# include + /* XZ_PREBOOT may be defined only via decompress_unxz.c. */ +# ifndef XZ_PREBOOT +# include +# include +# include +# ifdef CONFIG_XZ_DEC_X86 +# define XZ_DEC_X86 +# endif +# ifdef CONFIG_XZ_DEC_POWERPC +# define XZ_DEC_POWERPC +# endif +# ifdef CONFIG_XZ_DEC_IA64 +# define XZ_DEC_IA64 +# endif +# ifdef CONFIG_XZ_DEC_ARM +# define XZ_DEC_ARM +# endif +# ifdef CONFIG_XZ_DEC_ARMTHUMB +# define XZ_DEC_ARMTHUMB +# endif +# ifdef CONFIG_XZ_DEC_SPARC +# define XZ_DEC_SPARC +# endif +# define memeq(a, b, size) (memcmp(a, b, size) == 0) +# define memzero(buf, size) memset(buf, 0, size) +# endif +# define get_le32(p) le32_to_cpup((const uint32_t *)(p)) +#else + /* + * For userspace builds, use a separate header to define the required + * macros and functions. This makes it easier to adapt the code into + * different environments and avoids clutter in the Linux kernel tree. + */ +# include "xz_config.h" +#endif + +/* If no specific decoding mode is requested, enable support for all modes. */ +#if !defined(XZ_DEC_SINGLE) && !defined(XZ_DEC_PREALLOC) \ + && !defined(XZ_DEC_DYNALLOC) +# define XZ_DEC_SINGLE +# define XZ_DEC_PREALLOC +# define XZ_DEC_DYNALLOC +#endif + +/* + * The DEC_IS_foo(mode) macros are used in "if" statements. If only some + * of the supported modes are enabled, these macros will evaluate to true or + * false at compile time and thus allow the compiler to omit unneeded code. + */ +#ifdef XZ_DEC_SINGLE +# define DEC_IS_SINGLE(mode) ((mode) == XZ_SINGLE) +#else +# define DEC_IS_SINGLE(mode) (false) +#endif + +#ifdef XZ_DEC_PREALLOC +# define DEC_IS_PREALLOC(mode) ((mode) == XZ_PREALLOC) +#else +# define DEC_IS_PREALLOC(mode) (false) +#endif + +#ifdef XZ_DEC_DYNALLOC +# define DEC_IS_DYNALLOC(mode) ((mode) == XZ_DYNALLOC) +#else +# define DEC_IS_DYNALLOC(mode) (false) +#endif + +#if !defined(XZ_DEC_SINGLE) +# define DEC_IS_MULTI(mode) (true) +#elif defined(XZ_DEC_PREALLOC) || defined(XZ_DEC_DYNALLOC) +# define DEC_IS_MULTI(mode) ((mode) != XZ_SINGLE) +#else +# define DEC_IS_MULTI(mode) (false) +#endif + +/* + * If any of the BCJ filter decoders are wanted, define XZ_DEC_BCJ. + * XZ_DEC_BCJ is used to enable generic support for BCJ decoders. + */ +#ifndef XZ_DEC_BCJ +# if defined(XZ_DEC_X86) || defined(XZ_DEC_POWERPC) \ + || defined(XZ_DEC_IA64) || defined(XZ_DEC_ARM) \ + || defined(XZ_DEC_ARM) || defined(XZ_DEC_ARMTHUMB) \ + || defined(XZ_DEC_SPARC) +# define XZ_DEC_BCJ +# endif +#endif + +/* + * Allocate memory for LZMA2 decoder. xz_dec_lzma2_reset() must be used + * before calling xz_dec_lzma2_run(). + */ +XZ_EXTERN struct xz_dec_lzma2 *xz_dec_lzma2_create(enum xz_mode mode, + uint32_t dict_max); + +/* + * Decode the LZMA2 properties (one byte) and reset the decoder. Return + * XZ_OK on success, XZ_MEMLIMIT_ERROR if the preallocated dictionary is not + * big enough, and XZ_OPTIONS_ERROR if props indicates something that this + * decoder doesn't support. + */ +XZ_EXTERN enum xz_ret xz_dec_lzma2_reset(struct xz_dec_lzma2 *s, + uint8_t props); + +/* Decode raw LZMA2 stream from b->in to b->out. */ +XZ_EXTERN enum xz_ret xz_dec_lzma2_run(struct xz_dec_lzma2 *s, + struct xz_buf *b); + +/* Free the memory allocated for the LZMA2 decoder. */ +XZ_EXTERN void xz_dec_lzma2_end(struct xz_dec_lzma2 *s); + +#ifdef XZ_DEC_BCJ +/* + * Allocate memory for BCJ decoders. xz_dec_bcj_reset() must be used before + * calling xz_dec_bcj_run(). + */ +XZ_EXTERN struct xz_dec_bcj *xz_dec_bcj_create(bool single_call); + +/* + * Decode the Filter ID of a BCJ filter. This implementation doesn't + * support custom start offsets, so no decoding of Filter Properties + * is needed. Returns XZ_OK if the given Filter ID is supported. + * Otherwise XZ_OPTIONS_ERROR is returned. + */ +XZ_EXTERN enum xz_ret xz_dec_bcj_reset(struct xz_dec_bcj *s, uint8_t id); + +/* + * Decode raw BCJ + LZMA2 stream. This must be used only if there actually is + * a BCJ filter in the chain. If the chain has only LZMA2, xz_dec_lzma2_run() + * must be called directly. + */ +XZ_EXTERN enum xz_ret xz_dec_bcj_run(struct xz_dec_bcj *s, + struct xz_dec_lzma2 *lzma2, + struct xz_buf *b); + +/* Free the memory allocated for the BCJ filters. */ +#define xz_dec_bcj_end(s) kfree(s) +#endif + +#endif diff --git a/src/common/unix/xzminidec/src/xz_stream.h b/src/common/unix/xzminidec/src/xz_stream.h new file mode 100644 index 000000000..66cb5a705 --- /dev/null +++ b/src/common/unix/xzminidec/src/xz_stream.h @@ -0,0 +1,62 @@ +/* + * Definitions for handling the .xz file format + * + * Author: Lasse Collin + * + * This file has been put into the public domain. + * You can do whatever you want with this file. + */ + +#ifndef XZ_STREAM_H +#define XZ_STREAM_H + +#if defined(__KERNEL__) && !XZ_INTERNAL_CRC32 +# include +# undef crc32 +# define xz_crc32(buf, size, crc) \ + (~crc32_le(~(uint32_t)(crc), buf, size)) +#endif + +/* + * See the .xz file format specification at + * http://tukaani.org/xz/xz-file-format.txt + * to understand the container format. + */ + +#define STREAM_HEADER_SIZE 12 + +#define HEADER_MAGIC "\3757zXZ" +#define HEADER_MAGIC_SIZE 6 + +#define FOOTER_MAGIC "YZ" +#define FOOTER_MAGIC_SIZE 2 + +/* + * Variable-length integer can hold a 63-bit unsigned integer or a special + * value indicating that the value is unknown. + * + * Experimental: vli_type can be defined to uint32_t to save a few bytes + * in code size (no effect on speed). Doing so limits the uncompressed and + * compressed size of the file to less than 256 MiB and may also weaken + * error detection slightly. + */ +typedef uint64_t vli_type; + +#define VLI_MAX ((vli_type)-1 / 2) +#define VLI_UNKNOWN ((vli_type)-1) + +/* Maximum encoded size of a VLI */ +#define VLI_BYTES_MAX (sizeof(vli_type) * 8 / 7) + +/* Integrity Check types */ +enum xz_check { + XZ_CHECK_NONE = 0, + XZ_CHECK_CRC32 = 1, + XZ_CHECK_CRC64 = 4, + XZ_CHECK_SHA256 = 10 +}; + +/* Maximum possible Check ID */ +#define XZ_CHECK_MAX 15 + +#endif diff --git a/src/common/uproc/os/libos-v2.0.0/debug/lines.h b/src/common/uproc/os/common/include/libdwarf.h similarity index 63% rename from src/common/uproc/os/libos-v2.0.0/debug/lines.h rename to src/common/uproc/os/common/include/libdwarf.h index 0aabcb59e..0656b22ea 100644 --- a/src/common/uproc/os/libos-v2.0.0/debug/lines.h +++ b/src/common/uproc/os/common/include/libdwarf.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,20 +21,14 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef LINES_H_ -#define LINES_H_ +#ifndef __LINES_H__ +#define __LINES_H__ +#include "libelf.h" +#ifdef __cplusplus +extern "C" { +#endif -#include "elf.h" - -typedef struct -{ - NvU64 address; - NvU32 length; - NvU32 arangeUnit; - const NvU8 *lineUnitBuffer; - NvU32 lineUnitSize; - -} ARangeTupple; +#include "libos_status.h" typedef struct { @@ -42,21 +36,21 @@ typedef struct NvU8 *debugARangesStart, *debugARangesEnd; NvU8 *symtabStart, *symtabEnd; NvU8 *strtabStart, *strtabEnd; - ARangeTupple *arangeTable; + struct DwarfARangeTuple *arangeTable; NvU32 nARangeEntries; -} libosDebugResolver; +} LibosDebugResolver; -void libosDebugResolverConstruct(libosDebugResolver *pThis, elf64_header *elf); -void libosDebugResolverDestroy(libosDebugResolver *pThis); +LibosStatus LibosDebugResolverConstruct(LibosDebugResolver *pThis, LibosElfImage * image); +void LibosDebugResolverDestroy(LibosDebugResolver *pThis); // @note Optimized for single lookup (no search structures are created) -NvBool libosDebugResolveSymbolToVA(libosDebugResolver *pThis, const char *symbol, NvU64 *address); -NvBool libosDebugResolveSymbolToName( - libosDebugResolver *pThis, NvU64 symbolAddress, const char **name, NvU64 *offset); -NvBool libosDwarfResolveLine( - libosDebugResolver *pThis, NvU64 address, const char **directory, const char **filename, +NvBool LibosDebugResolveSymbolToVA(LibosDebugResolver *pThis, const char *symbol, NvU64 *address); +NvBool LibosDebugResolveSymbolToName(LibosDebugResolver *pThis, NvU64 symbolAddress, const char **name, NvU64 *offset); +NvBool LibosDwarfResolveLine(LibosDebugResolver *pThis, NvU64 address, const char **directory, const char **filename, NvU64 *outputLine, NvU64 *outputColumn, NvU64 *matchedAddress); -NvBool libosDebugGetSymbolRange( - libosDebugResolver *pThis, NvU64 symbolAddress, NvU64 *symStart, NvU64 *symEnd); +NvBool LibosDebugGetSymbolRange(LibosDebugResolver *pThis, NvU64 symbolAddress, NvU64 *symStart, NvU64 *symEnd); +#ifdef __cplusplus +} +#endif #endif diff --git a/src/common/uproc/os/common/include/libelf.h b/src/common/uproc/os/common/include/libelf.h new file mode 100644 index 000000000..fa547b17f --- /dev/null +++ b/src/common/uproc/os/common/include/libelf.h @@ -0,0 +1,141 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef LIBELF_H_ +#define LIBELF_H_ +#include +#ifdef __cplusplus +extern "C" { +#endif + +#include "libos_status.h" + +// Structures for Loader +typedef struct +{ + NvU8 ident[16]; + NvU16 type; + NvU16 machine; + NvU32 version; + NvU64 entry; + NvU64 phoff; + NvU64 shoff; + NvU32 flags; + NvU16 ehsize; + NvU16 phentsize; + NvU16 phnum; + NvU16 shentsize; + NvU16 shnum; + NvU16 shstrndx; +} LibosElf64Header; + +typedef struct +{ + NvU32 type; + NvU32 flags; + NvU64 offset; + NvU64 vaddr; + NvU64 paddr; + NvU64 filesz; + NvU64 memsz; + NvU64 align; +} LibosElf64ProgramHeader; + +#define PF_X 1 +#define PF_W 2 +#define PF_R 4 + +#define PT_LOAD 1 +#define PT_NOTE 4 +#define PT_PHDR 6 +#define PT_SHLIB 5 +#define PT_DYNAMIC 2 +// Structures for finding Symbols +typedef struct +{ + NvU32 name; + NvU32 type; + NvU64 flags; + NvU64 addr; + NvU64 offset; + NvU64 size; + NvU32 link; + NvU32 info; + NvU64 addralign; + NvU64 entsize; +} LibosElf64SectionHeader; + +#define SHT_NOBITS 8 +#define SHT_PROGBITS 1 + +typedef struct +{ + NvU32 name; + NvU8 info; + NvU8 other; + NvU16 shndx; + NvU64 value; + NvU64 size; +} LibosElf64Symbol; + +typedef struct { + NvS64 tag; + NvU64 ptr; +} LibosElf64Dynamic; + +typedef struct LibosElfImage{ + LibosElf64Header * elf; + NvU64 size; + void * (*map)(struct LibosElfImage *image, NvU64 offset, NvU64 size); +} LibosElfImage; + +LibosStatus LibosElfImageConstruct(LibosElfImage * image, void * elf, NvU64 size); + +// Program headers +LibosElf64ProgramHeader * LibosElfProgramHeaderForRange(LibosElfImage * image, NvU64 va, NvU64 vaLastByte); +LibosElf64ProgramHeader * LibosElfProgramHeaderNext(LibosElfImage * image, LibosElf64ProgramHeader * previous); + +// Section headers +LibosElf64SectionHeader * LibosElfFindSectionByName(LibosElfImage * image, const char *targetName); +LibosStatus LibosElfMapSection(LibosElfImage * image, LibosElf64SectionHeader * shdr, NvU8 ** start, NvU8 ** end); +LibosElf64SectionHeader * LibosElfFindSectionByAddress(LibosElfImage * image, NvU64 address); +LibosElf64SectionHeader * LibosElfSectionHeaderNext(LibosElfImage * image, LibosElf64SectionHeader * previous); + +// Dynamic linker +LibosElf64ProgramHeader * LibosElfHeaderDynamic(LibosElfImage * image); +LibosElf64Dynamic * LibosElfDynamicEntryNext(LibosElfImage * image, LibosElf64ProgramHeader * dynamicTableHeader, LibosElf64Dynamic * previous); + +// VA based access +void * LibosElfMapVirtual(LibosElfImage * image, NvU64 address, NvU64 size); +const char * LibosElfMapVirtualString(LibosElfImage * image, NvU64 address, NvBool checkShdrs); + +// Libos Tiny entry +NvBool LibosTinyElfGetBootEntry(LibosElfImage * image, NvU64 * physicalEntry); + +NvBool LibosElfCommitData(LibosElfImage * image, NvU64 commitVirtualAddress, NvU64 commitSize); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/common/uproc/os/libos-v2.0.0/debug/logdecode.h b/src/common/uproc/os/common/include/liblogdecode.h similarity index 83% rename from src/common/uproc/os/libos-v2.0.0/debug/logdecode.h rename to src/common/uproc/os/common/include/liblogdecode.h index 51f3b8123..7346c6c3e 100644 --- a/src/common/uproc/os/libos-v2.0.0/debug/logdecode.h +++ b/src/common/uproc/os/common/include/liblogdecode.h @@ -50,7 +50,7 @@ extern "C" { #if LIBOS_LOG_DECODE_ENABLE # include "../include/libos_log.h" -# include "lines.h" +# include "libdwarf.h" #endif // Forward declarations. @@ -67,13 +67,14 @@ typedef struct LIBOS_LOG_DECODE_LOG LIBOS_LOG_DECODE_LOG; typedef struct { NV_DECLARE_ALIGNED(LIBOS_LOG_DECODE_LOG *log, 8); + NV_DECLARE_ALIGNED(LIBOS_LOG_DECODE_LOG *logSymbolResolver, 8); NV_DECLARE_ALIGNED(libosLogMetadata *meta, 8); NV_DECLARE_ALIGNED(NvU64 timeStamp, 8); NvU64 args[LIBOS_LOG_MAX_ARGS]; } LIBOS_LOG_DECODE_RECORD; // Size of LIBOS_LOG_DECODE_RECORD without args, in number of NvU64 entries. -# define LIBOS_LOG_DECODE_RECORD_BASE 3 +# define LIBOS_LOG_DECODE_RECORD_BASE 4 // Ensure that the size matches up (no padding in the struct) ct_assert((LIBOS_LOG_DECODE_RECORD_BASE * sizeof(NvU64)) == (sizeof(LIBOS_LOG_DECODE_RECORD) - sizeof(((LIBOS_LOG_DECODE_RECORD*)NULL)->args))); @@ -83,6 +84,8 @@ ct_assert((LIBOS_LOG_DECODE_RECORD_BASE * sizeof(NvU64)) == (sizeof(LIBOS_LOG_DE #define TASK_NAME_MAX_LENGTH (8) #define SOURCE_NAME_MAX_LENGTH (4) +#define ELF_SECTION_NAME_MAX (32) // In bytes + // NvLog buffer typedef struct { @@ -102,7 +105,8 @@ struct LIBOS_LOG_DECODE_LOG NvU64 putCopy; // End pointer for this batch. NvU64 putIter; // Iterator for this batch. NvU32 gpuInstance; // GPU that this log is associated with. - char taskPrefix[TASK_NAME_MAX_LENGTH]; // Prefix string printed before each line. + char taskPrefix[TASK_NAME_MAX_LENGTH]; // Prefix string printed before each line. + char elfSectionName[ELF_SECTION_NAME_MAX]; // Task section name in container logging ELF serving as ID. #if LIBOS_LOG_TO_NVLOG NvU32 hNvLogNoWrap; // No wrap buffer captures first records. @@ -114,6 +118,9 @@ struct LIBOS_LOG_DECODE_LOG #endif #if LIBOS_LOG_DECODE_ENABLE + LibosElf64Header *elf; + LibosElfImage elfImage; + LibosDebugResolver resolver; LIBOS_LOG_DECODE_RECORD record; #endif }; @@ -126,8 +133,7 @@ typedef struct LIBOS_LOG_DECODE_LOG log[LIBOS_LOG_MAX_LOGS]; #if LIBOS_LOG_DECODE_ENABLE - elf64_header *elf; - libosDebugResolver resolver; + NvBool bIsDecodable; // True if a logging ELF is provided, False on NULL NvU64 *scratchBuffer; // Sorted by timestamp. NvU64 scratchBufferSize; // Sum of logBufferSize. char *curLineBufPtr; // Current position in lineBuffer. @@ -156,19 +162,21 @@ void libosLogCreate(LIBOS_LOG_DECODE *logDecode); void libosLogCreateEx(LIBOS_LOG_DECODE *logDecode, const char *pSourceName); #endif -void libosLogAddLogEx(LIBOS_LOG_DECODE *logDecode, void *buffer, NvU64 bufferSize, NvU32 gpuInstance, NvU32 gpuArch, NvU32 gpuImpl, const char *name); -void libosLogAddLog(LIBOS_LOG_DECODE *logDecode, void *buffer, NvU64 bufferSize, NvU32 gpuInstance, const char *name); +void libosLogAddLogEx(LIBOS_LOG_DECODE *logDecode, void *buffer, NvU64 bufferSize, NvU32 gpuInstance, NvU32 gpuArch, NvU32 gpuImpl, const char *name, const char *elfSectionName); +void libosLogAddLog(LIBOS_LOG_DECODE *logDecode, void *buffer, NvU64 bufferSize, NvU32 gpuInstance, const char *name, const char *elfSectionName); #if LIBOS_LOG_DECODE_ENABLE -void libosLogInit(LIBOS_LOG_DECODE *logDecode, elf64_header *elf); +void libosLogInit(LIBOS_LOG_DECODE *logDecode, LibosElf64Header *elf, NvU64 elfSize); void libosLogInitEx( - LIBOS_LOG_DECODE *logDecode, elf64_header *elf, NvBool bSynchronousBuffer, NvBool bPtrSymbolResolve); + LIBOS_LOG_DECODE *logDecode, LibosElf64Header *elf, NvBool bSynchronousBuffer, NvBool bPtrSymbolResolve, NvU64 elfSize); #else -void libosLogInit(LIBOS_LOG_DECODE *logDecode, void *elf); +void libosLogInit(LIBOS_LOG_DECODE *logDecode, void *elf, NvU64 elfSize); void libosLogInitEx( - LIBOS_LOG_DECODE *logDecode, void *elf, NvBool bSynchronousBuffer, NvBool bPtrSymbolResolve); + LIBOS_LOG_DECODE *logDecode, void *elf, NvBool bSynchronousBuffer, NvBool bPtrSymbolResolve, NvU64 elfSize); #endif // LIBOS_LOG_DECODE_ENABLE +void libosLogSymbolicateAddress(LIBOS_LOG_DECODE *logDecode, char *decodedLine, NvLength decodedLineSize, NvUPtr addr); + void libosLogDestroy(LIBOS_LOG_DECODE *logDecode); void libosExtractLogs(LIBOS_LOG_DECODE *logDecode, NvBool bSyncNvLog); diff --git a/src/common/uproc/os/libos-v2.0.0/include/libos_init_args.h b/src/common/uproc/os/common/include/libos_init_args.h similarity index 100% rename from src/common/uproc/os/libos-v2.0.0/include/libos_init_args.h rename to src/common/uproc/os/common/include/libos_init_args.h diff --git a/src/common/uproc/os/libos-v2.0.0/include/libos_log.h b/src/common/uproc/os/common/include/libos_log.h similarity index 68% rename from src/common/uproc/os/libos-v2.0.0/include/libos_log.h rename to src/common/uproc/os/common/include/libos_log.h index 890161fcf..7aad0ea40 100644 --- a/src/common/uproc/os/libos-v2.0.0/include/libos_log.h +++ b/src/common/uproc/os/common/include/libos_log.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -25,6 +25,8 @@ #define LIBOS_LOGGER_H_ #include "nvtypes.h" +#include +#include "libos_printf_arg.h" /** * @brief The log metadata structures and format strings are stripped @@ -41,6 +43,21 @@ typedef struct NvU8 printLevel; } libosLogMetadata; +/** + * @brief The log metadata structure extended for accomodating remote + * task's symbol resolution. + * It contains a flag 'version_extended', containing its high bit + * set so that this extended struct can be differentiated from + * the original struct. + * + */ +typedef struct +{ + NV_DECLARE_ALIGNED(NvU64 versionExtended, 8); + NV_DECLARE_ALIGNED(const char *elfSectionName, 8); + libosLogMetadata meta; +} libosLogMetadata_extended; + /*! * Count arguments * @@ -63,7 +80,39 @@ typedef struct * Cast remaining log arguments to integers for storage * */ -#define LIBOS_LOG_BUILD_ARG(a) (NvU64)(a), +static inline LibosPrintfArgument LibosPrintfArgumentU64(NvU64 i) { + LibosPrintfArgument r; + r.i = i; + return r; +} + +static inline LibosPrintfArgument LibosPrintfArgumentS64(NvS64 i) { + LibosPrintfArgument r; + r.i = (NvU64)i; + return r; +} + +#if !defined(NVRM) && !defined(PMU_RTOS) && LIBOS_CONFIG_FLOAT + static inline LibosPrintfArgument LibosPrintfArgumentFloat(float f) { + LibosPrintfArgument r; + r.f = f; + return r; + } + static inline LibosPrintfArgument LibosPrintfArgumentDouble(double f) { + LibosPrintfArgument r; + r.f = f; + return r; + } + +# define LIBOS_LOG_BUILD_ARG(a) _Generic((a), \ + float: LibosPrintfArgumentFloat(a), \ + double: LibosPrintfArgumentDouble(a), \ + default : LibosPrintfArgumentU64((NvU64)a)), + +#else +# define LIBOS_LOG_BUILD_ARG(a) (NvU64)(a), +#endif + #define LIBOS_LOG_BUILD_1(fmt) #define LIBOS_LOG_BUILD_2(fmt, b) LIBOS_LOG_BUILD_ARG(b) #define LIBOS_LOG_BUILD_3(fmt, b, c) LIBOS_LOG_BUILD_ARG(b) LIBOS_LOG_BUILD_ARG(c) @@ -139,10 +188,40 @@ typedef struct LIBOS_LOG_BUILD_APPLY( \ LIBOS_MACRO_PASTE_EVAL(LIBOS_LOG_BUILD_, LIBOS_MACRO_GET_COUNT(__VA_ARGS__)), __VA_ARGS__) -#define LOG_LEVEL_INFO 0 -#define LOG_LEVEL_ERROR 1 +#define LOG_LEVEL_INFO 0 +#define LOG_LEVEL_WARNING 1 +#define LOG_LEVEL_ERROR 2 -# define LIBOS_SECTION_LOGGING __attribute__((section(".logging"))) +#define LIBOS_SECTION_LOGGING __attribute__((section(".logging"))) + +// The compiler used for Windows doesn't have access to the format attribute +__attribute__((format(printf, 1, 2))) +static inline void gccFakePrintf(const char *pFmt, ...) +{ + (void)pFmt; +} + +void LibosLogTokens(const libosLogMetadata * metadata, const LibosPrintfArgument * tokens, NvU64 count); + +/*! + * Cast remaining log arguments to integers for storage + * + */ +#define LibosLog(level, ...) \ + do \ + { \ + gccFakePrintf(__VA_ARGS__); \ + static const LIBOS_SECTION_LOGGING char libos_pvt_format[] = {LIBOS_MACRO_FIRST(__VA_ARGS__)}; \ + static const LIBOS_SECTION_LOGGING char libos_pvt_file[] = {__FILE__}; \ + static const LIBOS_SECTION_LOGGING libosLogMetadata libos_pvt_meta = { \ + .filename = &libos_pvt_file[0], \ + .format = &libos_pvt_format[0], \ + .lineNumber = __LINE__, \ + .argumentCount = LIBOS_MACRO_GET_COUNT(__VA_ARGS__) - 1, \ + .printLevel = level}; \ + const LibosPrintfArgument tokens[] = { APPLY_REMAINDER(__VA_ARGS__) }; \ + LibosLogTokens(&libos_pvt_meta, &tokens[0], sizeof(tokens) / sizeof(*tokens)); \ + } while (0) #ifdef LIBOS_LOGGING_METADATA_SPLIT /*! @@ -192,4 +271,29 @@ typedef struct dispatcher(sizeof(tokens) / sizeof(*tokens), &tokens[0]); \ } while (0) +/*! + * Cast remaining log arguments to integers for storage + * This macro is used when logging for other task's address + */ +#define LIBOS_LOG_ADDRESS(dispatcher, taskElfSectionName, level, ...) \ + do \ + { \ + static const LIBOS_SECTION_LOGGING_CONST char libos_pvt_format[] = {LIBOS_MACRO_FIRST(__VA_ARGS__)}; \ + static const LIBOS_SECTION_LOGGING_CONST char libos_pvt_file[] = {__FILE__}; \ + static const LIBOS_SECTION_LOGGING_CONST char libos_pvt_elf_name[] = {taskElfSectionName}; \ + LIBOS_LOGGING_AUX_METADATA_DUMP; \ + const libosLogMetadata libos_pvt_meta = { \ + .filename = &libos_pvt_file[0], \ + .format = &libos_pvt_format[0], \ + .lineNumber = __LINE__, \ + .argumentCount = LIBOS_MACRO_GET_COUNT(__VA_ARGS__) - 1, \ + .printLevel = level}; \ + static const LIBOS_SECTION_LOGGING_METADATA libosLogMetadata_extended libos_pvt_meta_ex = { \ + .versionExtended = 0x8000000000000000ULL, \ + .elfSectionName = &libos_pvt_elf_name[0], \ + .meta = libos_pvt_meta}; \ + const NvU64 tokens[] = {APPLY_REMAINDER(__VA_ARGS__)(NvU64) & libos_pvt_meta_ex}; \ + dispatcher(sizeof(tokens) / sizeof(*tokens), &tokens[0]); \ + } while (0) + #endif diff --git a/src/nvidia/src/libraries/nvport/sync/inc/sync_rwlock_def.h b/src/common/uproc/os/common/include/libos_printf_arg.h similarity index 73% rename from src/nvidia/src/libraries/nvport/sync/inc/sync_rwlock_def.h rename to src/common/uproc/os/common/include/libos_printf_arg.h index 5f956f02e..49aeb10c6 100644 --- a/src/nvidia/src/libraries/nvport/sync/inc/sync_rwlock_def.h +++ b/src/common/uproc/os/common/include/libos_printf_arg.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -20,22 +20,22 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ +#ifndef LIBOS_PRINTF_ARG_H_ +#define LIBOS_PRINTF_ARG_H_ -/** - * @file - * @brief SYNC custom rwlock struct implementations - * - */ - -#ifndef _NVPORT_SYNC_RWLOCK_DEF_H_ -#define _NVPORT_SYNC_RWLOCK_DEF_H_ - -struct PORT_RWLOCK -{ - PORT_SEMAPHORE *pSemRead; - PORT_SEMAPHORE *pSemWrite; - volatile NvS32 numReaders; - PORT_MEM_ALLOCATOR *pAllocator; -}; - +#include "nvtypes.h" +#if !defined(NVRM) && !defined(PMU_RTOS) && !defined(NVSYM_STANDALONE) +#include "libos-config.h" #endif + +typedef union +{ + NvU64 i; +#if !defined(NVRM) && !defined(PMU_RTOS) && LIBOS_CONFIG_FLOAT + long double f; +#endif + void *p; +} LibosPrintfArgument; + +#endif //LIBOS_PRINTF_ARG_H_ + diff --git a/src/common/uproc/os/common/include/libos_status.h b/src/common/uproc/os/common/include/libos_status.h new file mode 100644 index 000000000..36fe31bd7 --- /dev/null +++ b/src/common/uproc/os/common/include/libos_status.h @@ -0,0 +1,59 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef LIBOS_STATUS_H +#define LIBOS_STATUS_H + +/** + * @brief Status codes for Libos kernel syscalls and standard daemons. + * + */ +// __packed__ forces this enum to use a minimal underlying type to represent this enum +// It is required for LibOS 3.x syscalls, otherwise it wouldn't fit into registers +// Note: Windows does not support this feature +typedef enum +__attribute__ ((__packed__)) +{ + LibosOk = 0u, + + LibosErrorArgument = 1u, + LibosErrorAccess = 2u, + LibosErrorTimeout = 3u, + LibosErrorIncomplete = 4u, + LibosErrorFailed = 5u, + LibosErrorOutOfMemory= 6u, + LibosErrorSpoofed = 7u, + LibosErrorPortLost = 8u, + LibosErrorShuttleReset = 10u, + LibosErrorExhaustedHandles = 9u, + LibosErrorNotDeviceMapped = 11u +} LibosStatus; + +#define LIBOS_OK LibosOk + +#define LIBOS_ERROR_INVALID_ARGUMENT LibosErrorArgument +#define LIBOS_ERROR_INVALID_ACCESS LibosErrorAccess +#define LIBOS_ERROR_TIMEOUT LibosErrorTimeout +#define LIBOS_ERROR_INCOMPLETE LibosErrorIncomplete +#define LIBOS_ERROR_OPERATION_FAILED LibosErrorFailed + +#endif diff --git a/src/common/uproc/os/libos-v2.0.0/debug/elf.c b/src/common/uproc/os/libos-v2.0.0/debug/elf.c deleted file mode 100644 index 451053c84..000000000 --- a/src/common/uproc/os/libos-v2.0.0/debug/elf.c +++ /dev/null @@ -1,187 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifdef NVRM - -# include -# define memcpy(d, s, l) portMemCopy(d, l, s, l) -# define strcmp(str1, str2) portStringCompare(str1, str2, 0x1000) - -#else // NVRM - -# include -# include -# include - -#endif // NVRM - -#include "elf.h" -#include "nvtypes.h" - -/** - * - * @brief Find the start and end of the ELF section in memory - * from the section name. - * - * @param[in] elf - * @param[in] sectionName - * The section to find such as .text or .data - * @param[out] start, end - * The start and end of the section in the loaded ELF file - * e.g validPtr >= start && validPtr < end - * @param[out] va_baase - * The virtual address this section is loaded at - */ -NvBool -libosElfFindSectionByName(elf64_header *elf, const char *targetName, NvU8 **start, NvU8 **end, NvU64 *va_base) -{ - elf64_shdr *shdr = (elf64_shdr *)(((char *)elf) + elf->shoff); - const char *string_base = ((char *)elf) + shdr[elf->shstrndx].offset; - NvU32 i; - - for (i = 0; i < elf->shnum; i++, shdr++) - { - const char *name = string_base + shdr->name; - if (strcmp(name, targetName) == 0) - { - *start = (NvU8 *)elf + shdr->offset; - *end = (NvU8 *)elf + shdr->offset + shdr->size; - *va_base = shdr->addr; - return NV_TRUE; - } - } - - return NV_FALSE; -} - -/** - * - * @brief Find the start and end of the ELF section in memory - * from the section name. - * - * @param[in] elf - * @param[in] sectionName - * The section to find such as .text or .data - * @param[out] start, end - * The start and end of the section in the loaded ELF file - * e.g validPtr >= start && validPtr < end - * @param[out] va_base - * The virtual address this section is loaded at - */ -NvBool -libosElfFindSectionByAddress(elf64_header *elf, NvU64 address, NvU8 **start, NvU8 **end, NvU64 *va_base) -{ - elf64_shdr *shdr = (elf64_shdr *)(((char *)elf) + elf->shoff); - NvU32 i; - - for (i = 0; i < elf->shnum; i++, shdr++) - { - if (address >= shdr->addr && address < (shdr->addr + shdr->size)) - { - *start = (NvU8 *)elf + shdr->offset; - *end = (NvU8 *)elf + shdr->offset + shdr->size; - *va_base = shdr->addr; - return NV_TRUE; - } - } - - return NV_FALSE; -} - -/** - * - * @brief Reads an arbitrary sized block of memory by loaded VA through - * the ELF. This can be used to read data from the perspective - * of a processor who has loaded the ELF. - * - * @param[in] elf - * @param[in] address - * The absolute virtual address to read - * @param[out] size - * The number of bytes that must be valid. - * @returns - * The pointer to the data in question, or NULL if the operation failed) - */ -void *libosElfReadVirtual(elf64_header *elf, NvU64 address, NvU64 size) -{ - NvU8 *start, *end; - NvU64 va_base; - NvU64 section_offset; - NvU64 section_offset_tail; - - // @todo This really should be using the PHDR as theoretically section headers - // might be stripped - if (!libosElfFindSectionByAddress(elf, address, &start, &end, &va_base)) - return 0; - - section_offset = address - va_base; - - // Compute section offset (overflow check) - section_offset_tail = section_offset + size; - if (section_offset_tail < section_offset) - return 0; - - // Bounds check the tail - if (section_offset_tail > (NvLength)(end - start)) - return 0; - - return (address - va_base) + start; -} - -/** - * - * @brief Reads an arbitrary length string by loaded VA through - * the ELF. This can be used to read data from the perspective - * of a processor who has loaded the ELF. - * - * @param[in] elf - * @param[in] address - * The absolute virtual address to read - * @returns - * The pointer to the data in question, or NULL if the operation failed) - * Ensures that all bytes of the string lie within the ELF same section. - */ -const char *libosElfReadStringVirtual(elf64_header *elf, NvU64 address) -{ - NvU8 *start, *end; - NvU64 base; - NvU8 *region; - NvU8 *i; - - // @todo This really should be using the PHDR as theoretically section headers - // might be stripped - if (!libosElfFindSectionByAddress(elf, address, &start, &end, &base)) - return 0; - - region = (address - base) + start; - i = region; - - while (i >= start && i < end) - { - if (!*i) - return (const char *)region; - i++; - } - - return 0; -} diff --git a/src/common/uproc/os/libos-v2.0.0/debug/elf.h b/src/common/uproc/os/libos-v2.0.0/debug/elf.h deleted file mode 100644 index 58261c5a8..000000000 --- a/src/common/uproc/os/libos-v2.0.0/debug/elf.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2017-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef GSP_ELF_H_ -#define GSP_ELF_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -// Structures for Loader -typedef struct -{ - NvU8 ident[16]; - NvU16 type; - NvU16 machine; - NvU32 version; - NvU64 entry; - NvU64 phoff; - NvU64 shoff; - NvU32 flags; - NvU16 ehsize; - NvU16 phentsize; - NvU16 phnum; - NvU16 shentsize; - NvU16 shnum; - NvU16 shstrndx; -} elf64_header; - -typedef struct -{ - NvU32 type; - NvU32 flags; - NvU64 offset; - NvU64 vaddr; - NvU64 paddr; - NvU64 filesz; - NvU64 memsz; - NvU64 align; -} elf64_phdr; - -#define PF_X 1 -#define PF_W 2 -#define PF_R 4 - -#define PT_LOAD 1 - -// Structures for finding Symbols -typedef struct -{ - NvU32 name; - NvU32 type; - NvU64 flags; - NvU64 addr; - NvU64 offset; - NvU64 size; - NvU32 link; - NvU32 info; - NvU64 addralign; - NvU64 entsize; -} elf64_shdr; - -typedef struct -{ - NvU32 name; - NvU8 info; - NvU8 other; - NvU16 shndx; - NvU64 value; - NvU64 size; -} elf64_sym; - -// Core ELF API -NvBool libosElfFindSectionByName( - elf64_header *elf, const char *sectionName, NvU8 **start, NvU8 **end, NvU64 *va_base); -NvBool -libosElfFindSectionByAddress(elf64_header *elf, NvU64 address, NvU8 **start, NvU8 **end, NvU64 *va_base); -void *libosElfReadVirtual(elf64_header *elf, NvU64 address, NvU64 size); -const char *libosElfReadStringVirtual(elf64_header *elf, NvU64 address); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/src/common/uproc/os/libos-v2.0.0/debug/lines.c b/src/common/uproc/os/libos-v3.1.0/lib/libdwarf.c similarity index 85% rename from src/common/uproc/os/libos-v2.0.0/debug/lines.c rename to src/common/uproc/os/libos-v3.1.0/lib/libdwarf.c index 9f1fd2aff..4845ff1f9 100644 --- a/src/common/uproc/os/libos-v2.0.0/debug/lines.c +++ b/src/common/uproc/os/libos-v3.1.0/lib/libdwarf.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -34,8 +34,6 @@ # include # include -# define portMemCopy(d, l, s, m) memcpy(d, s, l) -# define portMemSet(d, v, l) memset(d, v, l) # define portStringCompare(str1, str2, l) strcmp(str1, str2) # define portMemAllocNonPaged(l) malloc(l); # define portMemFree(p) free(p); @@ -43,7 +41,7 @@ #endif // NVRM #include "nvtypes.h" -#include "lines.h" +#include "libdwarf.h" typedef struct { @@ -52,9 +50,27 @@ typedef struct NvU64 size; } DwarfStream; -static void libosDwarfBuildTables(libosDebugResolver *pThis); -static void dwarfBuildARangeTable(libosDebugResolver *pThis); -static void dwarfSetARangeTableLineUnit(libosDebugResolver *pThis, DwarfStream unit, NvU64 address); +typedef struct DwarfARangeTuple +{ + NvU64 address; + NvU32 length; + NvU32 arangeUnit; + const NvU8 *lineUnitBuffer; + NvU32 lineUnitSize; +} DwarfARangeTuple; + +void constructDwarfARangeTuple(DwarfARangeTuple * pThis) +{ + pThis->address = 0; + pThis->length = 0; + pThis->arangeUnit = 0; + pThis->lineUnitBuffer = 0; + pThis->lineUnitSize = 0; +} + +static void libosDwarfBuildTables(LibosDebugResolver *pThis); +static void dwarfBuildARangeTable(LibosDebugResolver *pThis); +static void dwarfSetARangeTableLineUnit(LibosDebugResolver *pThis, DwarfStream unit, NvU64 address); // https://www.dwarfstd.org/doc/dwarf-2.0.0.pdf @@ -89,23 +105,36 @@ enum * @brief Creates a resolver object for a given ELF. * No resources or memory are retained by this call. * - * @param[in] elf + * @param[in] image * An elf containing .debug_line and or .symtab data * @param[in] pThis * An uninitialized resolver object. */ -void libosDebugResolverConstruct(libosDebugResolver *pThis, elf64_header *elf) +LibosStatus LibosDebugResolverConstruct(LibosDebugResolver *pThis, LibosElfImage * image) { - NvU64 vabase; - libosElfFindSectionByName(elf, ".debug_line", &pThis->debugLineStart, &pThis->debugLineEnd, &vabase); - libosElfFindSectionByName( - elf, ".debug_aranges", &pThis->debugARangesStart, &pThis->debugARangesEnd, &vabase); - libosElfFindSectionByName(elf, ".symtab", &pThis->symtabStart, &pThis->symtabEnd, &vabase); - libosElfFindSectionByName(elf, ".strtab", &pThis->strtabStart, &pThis->strtabEnd, &vabase); + + LibosElf64SectionHeader * debugLine = LibosElfFindSectionByName(image, ".debug_line"); + if (!debugLine || LibosOk != LibosElfMapSection(image, debugLine, &pThis->debugLineStart, &pThis->debugLineEnd)) + pThis->debugLineStart = pThis->debugLineEnd = 0; + + LibosElf64SectionHeader * debugARanges = LibosElfFindSectionByName(image, ".debug_aranges"); + if (!debugARanges || LibosOk != LibosElfMapSection(image, debugARanges, &pThis->debugARangesStart, &pThis->debugARangesEnd)) + pThis->debugARangesStart = pThis->debugARangesEnd = 0; + + LibosElf64SectionHeader * debugSymTab = LibosElfFindSectionByName(image, ".symtab"); + if (!debugSymTab || LibosOk != LibosElfMapSection(image, debugSymTab, &pThis->symtabStart, &pThis->symtabEnd)) + pThis->symtabStart = pThis->symtabEnd = 0; + + LibosElf64SectionHeader * debugStrTab = LibosElfFindSectionByName(image, ".strtab"); + if (!debugStrTab || LibosOk != LibosElfMapSection(image, debugStrTab, &pThis->strtabStart, &pThis->strtabEnd)) + pThis->strtabStart = pThis->strtabEnd = 0; + libosDwarfBuildTables(pThis); + + return LibosOk; } -void libosDebugResolverDestroy(libosDebugResolver *pThis) +void LibosDebugResolverDestroy(LibosDebugResolver *pThis) { if (pThis->arangeTable != NULL) { @@ -125,11 +154,11 @@ void libosDebugResolverDestroy(libosDebugResolver *pThis) * @param[out] address * The virtual address for the given symbol.\ */ -NvBool libosDebugResolveSymbolToVA(libosDebugResolver *pThis, const char *symbolName, NvU64 *address) +NvBool LibosDebugResolveSymbolToVA(LibosDebugResolver *pThis, const char *symbolName, NvU64 *address) { - elf64_sym *i = (elf64_sym *)pThis->symtabStart; + LibosElf64Symbol *i = (LibosElf64Symbol *)pThis->symtabStart; - NvU64 count = (pThis->symtabEnd - pThis->symtabStart) / sizeof(elf64_sym); + NvU64 count = (pThis->symtabEnd - pThis->symtabStart) / sizeof(LibosElf64Symbol); while (count--) { if (i->name != 0) @@ -161,24 +190,27 @@ NvBool libosDebugResolveSymbolToVA(libosDebugResolver *pThis, const char *symbol * @param[out] name * The symbol name containing or matching the search address */ -NvBool libosDebugResolveSymbolToName( - libosDebugResolver *pThis, NvU64 symbolAddress, const char **name, NvU64 *offset) +NvBool LibosDebugResolveSymbolToName( + LibosDebugResolver *pThis, NvU64 symbolAddress, const char **name, NvU64 *offset) { - elf64_sym *i = (elf64_sym *)pThis->symtabStart; - NvU64 count = (pThis->symtabEnd - pThis->symtabStart) / sizeof(elf64_sym); + LibosElf64Symbol *i = (LibosElf64Symbol *)pThis->symtabStart; + NvU64 count = (pThis->symtabEnd - pThis->symtabStart) / sizeof(LibosElf64Symbol); while (count--) { - if (symbolAddress == i->value || (symbolAddress >= i->value && symbolAddress < i->value + i->size)) + if (i->name && (symbolAddress == i->value || (symbolAddress >= i->value && symbolAddress < i->value + i->size))) { - if (i->name) - *name = i->name + (const char *)pThis->strtabStart; - else - *name = ""; + *name = i->name + (const char *)pThis->strtabStart; *offset = symbolAddress - i->value; - return NV_TRUE; + + // Return now if this was a non-empty label (e.g. we're contained within it) + if (i->size) + return NV_TRUE; } i++; } + // We hit an empty label, good enough + if (*name) + return NV_TRUE; return NV_FALSE; } @@ -199,11 +231,11 @@ NvBool libosDebugResolveSymbolToName( * @param[out] symEnd * One past the last address covered by the symbol. */ -NvBool libosDebugGetSymbolRange( - libosDebugResolver *pThis, NvU64 symbolAddress, NvU64 *symStart, NvU64 *symEnd) +NvBool LibosDebugGetSymbolRange( + LibosDebugResolver *pThis, NvU64 symbolAddress, NvU64 *symStart, NvU64 *symEnd) { - elf64_sym *i = (elf64_sym *)pThis->symtabStart; - elf64_sym *symtabEnd = (elf64_sym *)pThis->symtabEnd; + LibosElf64Symbol *i = (LibosElf64Symbol *)pThis->symtabStart; + LibosElf64Symbol *symtabEnd = (LibosElf64Symbol *)pThis->symtabEnd; for (; i < symtabEnd; i++) { @@ -221,9 +253,11 @@ NvBool libosDebugGetSymbolRange( static NvBool libosDwarfReadRaw(DwarfStream *stream, void *buffer, NvU64 size) { NvU64 newOffset = stream->offset + size; + NvU32 i; if (newOffset > stream->size) return NV_FALSE; - portMemCopy(buffer, (size_t)size, stream->buffer + stream->offset, size); + for (i = 0; i < size; i++) + ((NvU8*)buffer)[i] = stream->buffer[stream->offset+i]; stream->offset = newOffset; return NV_TRUE; } @@ -321,6 +355,7 @@ static NvBool dwarfReadFilename(DwarfStream *names, const char **directory, cons return NV_TRUE; } + /** * * @brief DWARF-2 Virtual machine interpreter for debug data @@ -346,7 +381,7 @@ static NvBool dwarfReadFilename(DwarfStream *names, const char **directory, cons * Set to true when building the aranges index table. */ static NvBool dwarfParseUnitLines( - libosDebugResolver *pThis, DwarfStream unit, NvU64 pc, const char **directory, const char **filename, + LibosDebugResolver *pThis, DwarfStream unit, NvU64 pc, const char **directory, const char **filename, NvU64 *outputLine, NvU64 *outputColumn, NvU64 *matchedAddress, NvBool bBuildTable) { NvU16 version; @@ -354,38 +389,28 @@ static NvBool dwarfParseUnitLines( DwarfStream saveUnit = unit; - NvU64 headerOffset; - NvU8 minimumInstructionLength, defaultIsStmt, lineRange, opcodeBase; - NvS8 line_base; - NvU64 i; - - DwarfStream names; - - // Initial state of virtual machine - NvU64 previousAddress = 0, previousLine = 0, previousColumn = 0, previousFile = 0; - NvU64 address = 0, file = 1, line = 1, column = 0; - NvU8 isStmt; - //NvBool basicBlock = NV_FALSE - NvBool postEmitResetState = NV_FALSE; - //NvBool prologueEnd = NV_FALSE; - //NvBool epilogueBegin = NV_FALSE; - NvBool postEmitResetStateIsStmt = NV_FALSE; - //NvBool endSequence = NV_FALSE; - NvU8 opcode; - if (!DWARF_READ(&unit, &version) || version > 2 || !DWARF_READ(&unit, &prologueLength)) { return NV_FALSE; } - headerOffset = unit.offset; + NvU64 headerOffset = unit.offset; + NvU8 minimumInstructionLength, defaultIsStmt, lineRange, opcodeBase; + NvS8 line_base; if (!DWARF_READ(&unit, &minimumInstructionLength) || !DWARF_READ(&unit, &defaultIsStmt) || !DWARF_READ(&unit, &line_base) || !DWARF_READ(&unit, &lineRange) || !DWARF_READ(&unit, &opcodeBase)) { return NV_FALSE; } + if (lineRange == 0) + { + // @TODO: TEMP_HACK: FIXME. + return NV_FALSE; + } + // Skip over the opcode lengths + NvU64 i; for (i = 1; i < opcodeBase; i++) { NvU64 dummy; @@ -396,7 +421,7 @@ static NvBool dwarfParseUnitLines( } // Names section starts here inside after the prologue - names = unit; + DwarfStream names = unit; // Skip prologue unit.offset = headerOffset; @@ -407,16 +432,25 @@ static NvBool dwarfParseUnitLines( } unit.offset += prologueLength; - isStmt = defaultIsStmt; + // Initial state of virtuall machine + NvU64 previousAddress = 0, previousLine = 0, previousColumn = 0, previousFile = 0; + NvU64 address = 0, file = 1, line = 1, column = 0; + NvU8 isStmt = defaultIsStmt; + //NvBool basicBlock = NV_FALSE + NvBool postEmitResetState = NV_FALSE; + //NvBool prologueEnd = NV_FALSE; + //NvBool epilogueBegin = NV_FALSE; + NvBool postEmitResetStateIsStmt = NV_FALSE; + //NvBool endSequence = NV_FALSE; // Run the line number information program for this unit + NvU8 opcode; while (NV_TRUE) { - NvBool emit_row = NV_FALSE; - //NvU64 offset = unit.offset; if (!DWARF_READ(&unit, &opcode)) break; + NvBool emit_row = NV_FALSE; //NvBool reset_basic_block = NV_FALSE; // 6.2.5.1 Special Opcodes @@ -482,9 +516,9 @@ static NvBool dwarfParseUnitLines( case DW_LNE_define_file: { const char *fname = ""; - NvU64 dir, time, size; libosDwarfExtractString(&unit, &fname); //printf(" [0x%08x] Define file: %s\n", fname, offset); + NvU64 dir, time, size; dwarfReadUleb128(&unit, &dir); dwarfReadUleb128(&unit, &time); dwarfReadUleb128(&unit, &size); @@ -626,6 +660,7 @@ static NvBool dwarfParseUnitLines( //if (reset_basic_block) // basicBlock = NV_FALSE; } + return NV_FALSE; } @@ -646,11 +681,11 @@ static NvBool dwarfParseUnitLines( * @param[in] matchedAddress * Returns the virtual address to the start of the matched line/col. */ -NvBool libosDwarfResolveLine( - libosDebugResolver *pThis, NvU64 address, const char **directory, const char **filename, +NvBool LibosDwarfResolveLine( + LibosDebugResolver *pThis, NvU64 address, const char **directory, const char **filename, NvU64 *outputLine, NvU64 *outputColumn, NvU64 *matchedAddress) { - ARangeTupple *pFoundARange = NULL; + DwarfARangeTuple *pFoundARange = NULL; DwarfStream unit; NvU32 i; @@ -692,30 +727,29 @@ NvBool libosDwarfResolveLine( * @param[in/out] pThis * An initialized resolver object. */ -static void libosDwarfBuildTables(libosDebugResolver *pThis) +static void libosDwarfBuildTables(LibosDebugResolver *pThis) { - NvU32 tableSize; - DwarfStream debugLines; - DwarfStream unit; - NvU32 currentUnit = 1; - NvU32 unitSize; - pThis->arangeTable = NULL; pThis->nARangeEntries = 0; // Run through the .debug_aranges elf section to get a count of consolidated ranges. dwarfBuildARangeTable(pThis); - tableSize = (pThis->nARangeEntries + 1) * sizeof(ARangeTupple); + NvU32 tableSize = (pThis->nARangeEntries + 1) * sizeof(DwarfARangeTuple); + NvU32 i; // Allocate the table. pThis->arangeTable = portMemAllocNonPaged(tableSize); - portMemSet(pThis->arangeTable, 0, tableSize); + for (i = 0; i < pThis->nARangeEntries + 1; i++) + constructDwarfARangeTuple(&pThis->arangeTable[i]); // Run through the .debug_aranges elf section again to populate the table. dwarfBuildARangeTable(pThis); - debugLines.buffer = pThis->debugLineStart; debugLines.offset = 0; debugLines.size = pThis->debugLineEnd - pThis->debugLineStart; + DwarfStream debugLines = {pThis->debugLineStart, 0, pThis->debugLineEnd - pThis->debugLineStart}; + DwarfStream unit; + NvU32 currentUnit = 1; + NvU32 unitSize; // Run through the .debug_line elf section to match units to the arange table. for (currentUnit = 1;; currentUnit++) @@ -747,7 +781,7 @@ static void libosDwarfBuildTables(libosDebugResolver *pThis) * @param[in/out] pThis * An initialized resolver object. */ -static void dwarfBuildARangeTable(libosDebugResolver *pThis) +static void dwarfBuildARangeTable(LibosDebugResolver *pThis) { DwarfStream debugARanges = { pThis->debugARangesStart, 0, pThis->debugARangesEnd - pThis->debugARangesStart}; @@ -763,10 +797,6 @@ static void dwarfBuildARangeTable(libosDebugResolver *pThis) NvU8 addressSize = 0xff; NvU8 selectorSize = 0xff; - NvU32 nUnitTupples; - NvU64 combAddress = 0; - NvU64 combLength = 0; - if (!DWARF_READ(&debugARanges, &unit_size) || unit_size >= 0xfffffff0) { break; @@ -792,6 +822,10 @@ static void dwarfBuildARangeTable(libosDebugResolver *pThis) // Pad to natural alignment unit.offset = (unit.offset + 15) & ~15; + NvU32 nUnitTupples; + NvU64 combAddress = 0; + NvU64 combLength = 0; + for (nUnitTupples = 0;; nUnitTupples++) { NvU64 address; @@ -814,9 +848,9 @@ static void dwarfBuildARangeTable(libosDebugResolver *pThis) if (pThis->arangeTable != NULL && nARangeEntries < pThis->nARangeEntries) { // Table has been allocated -- fill it in. - ARangeTupple *pEntry = &pThis->arangeTable[nARangeEntries]; + DwarfARangeTuple *pEntry = &pThis->arangeTable[nARangeEntries]; pEntry->address = combAddress; - pEntry->length = (NvU32)combLength; + pEntry->length = combLength; pEntry->arangeUnit = nUnit; } nARangeEntries++; @@ -846,7 +880,7 @@ static void dwarfBuildARangeTable(libosDebugResolver *pThis) * @param[in] address * Any virtual address contained in teh above .debug_lines unit. */ -static void dwarfSetARangeTableLineUnit(libosDebugResolver *pThis, DwarfStream unit, NvU64 address) +static void dwarfSetARangeTableLineUnit(LibosDebugResolver *pThis, DwarfStream unit, NvU64 address) { NvU32 foundUnit = 0; NvU32 i; @@ -880,6 +914,6 @@ static void dwarfSetARangeTableLineUnit(libosDebugResolver *pThis, DwarfStream u for (; (foundUnit == pThis->arangeTable[i].arangeUnit); i++) { pThis->arangeTable[i].lineUnitBuffer = unit.buffer; - pThis->arangeTable[i].lineUnitSize = (NvU32)unit.size; + pThis->arangeTable[i].lineUnitSize = unit.size; } } diff --git a/src/common/uproc/os/libos-v3.1.0/lib/libelf.c b/src/common/uproc/os/libos-v3.1.0/lib/libelf.c new file mode 100644 index 000000000..cba09ed6e --- /dev/null +++ b/src/common/uproc/os/libos-v3.1.0/lib/libelf.c @@ -0,0 +1,489 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifdef NVRM +# include +# define strcmp(str1, str2) portStringCompare(str1, str2, 0x1000) +# define strncmp(str1, str2, size) portStringCompare(str1, str2, size) +#else // NVRM +# include +# include +# include +#endif // NVRM + +#include "libelf.h" +#include + +static void * elfSimpleAccess(LibosElfImage * image, NvU64 offset, NvU64 size) +{ + if ((offset + size) <= image->size) + return (NvU8 *)image->elf + offset; + return 0; +} + +/** + * + * @brief Initialize an elf image to point to an unloaded elf. + * + * @param[in] image + * The image structure to initialize with the provided elf. + * @param[in] elf + * @param[in] size + */ +LibosStatus LibosElfImageConstruct(LibosElfImage * image, void * elf, NvU64 size) +{ + if (size < sizeof(LibosElf64Header)) + return LibosErrorIncomplete; + + +#ifdef LIBOS_TOOL_BAKE + image->elf = malloc(size); + memcpy(image->elf, elf, size); +#else + image->elf = (LibosElf64Header *) elf; +#endif + + image->size = size; + image->map = elfSimpleAccess; + + return LibosOk; +} + +/** + * + * @brief Returns the offset from the start of the ELF corresponding + * to the entry point. + * + * The ELF should be copied directly into memory without modification. + * The packaged LIBOS elf contains a self bootstrapping ELF loader. + * + * During boot: + * - PHDRs are copied into memory descriptors + * - Copy on write sections are duplicated (into additional heap above) + * + * @param[in] elf + * @returns false if not a recognized LIBOS ELF. + */ +NvBool LibosTinyElfGetBootEntry(LibosElfImage * image, NvU64 * physicalEntry) +{ + NvU64 entryVa = image->elf->entry; + + // Find the phdr containing the entry point + LibosElf64ProgramHeader * phdr = LibosElfProgramHeaderForRange(image, entryVa, entryVa); + if (phdr) + { + *physicalEntry = phdr->paddr + entryVa - phdr->vaddr; + return NV_TRUE; + } + + return NV_FALSE; +} + +/** + * + * @brief Iterates Program Headers + * + * Program headers are loadable regions of the ELF. + * Each header may contain any number of sections. + * + * @param[in] image + * @param[in] previous + * Previous returned program header. Pass null to get first header. + */ +LibosElf64ProgramHeader * LibosElfProgramHeaderNext(LibosElfImage * image, LibosElf64ProgramHeader * previous) +{ + LibosElf64ProgramHeader * phdrTable = (LibosElf64ProgramHeader *) image->map(image, image->elf->phoff, sizeof(LibosElf64ProgramHeader) * image->elf->phnum); + LibosElf64ProgramHeader * phdrTableEnd = phdrTable + image->elf->phnum; + + LibosElf64ProgramHeader * next; + if (!previous) + next = phdrTable; + else + next = previous + 1; + + if (next == phdrTableEnd) + return 0; + + return next; +} + +/** + * + * @brief Iterates Sections + * + * + * @param[in] image + * @param[in] previous + * Previous returned section header. Pass null to get first header. + */ +LibosElf64SectionHeader * LibosElfSectionHeaderNext(LibosElfImage * image, LibosElf64SectionHeader * previous) +{ + LibosElf64SectionHeader * shdrTable = (LibosElf64SectionHeader *) image->map(image, image->elf->shoff, sizeof(LibosElf64SectionHeader) * image->elf->shnum); + LibosElf64SectionHeader * shdrTableEnd = shdrTable + image->elf->shnum; + + LibosElf64SectionHeader * next; + if (!previous) + next = shdrTable; + else + next = previous + 1; + + if (next == shdrTableEnd) + return 0; + + return next; +} + + +/** + * + * @brief Locates the dynamic loader section + * + * This section contains dependency information, import/export symbols, + * and relocations. + * + * @param[in] image + * @param[in] previous + * Previous returned section header. Pass null to get first header. + */ +LibosElf64ProgramHeader * LibosElfHeaderDynamic(LibosElfImage * image) +{ + LibosElf64ProgramHeader * phdr; + for (phdr = LibosElfProgramHeaderNext(image, 0); phdr; phdr = LibosElfProgramHeaderNext(image, phdr)) + if (phdr->type == PT_DYNAMIC) + return phdr; + return 0; +} + +/** + * + * @brief Iterates resources in dynamic loader section + * + * LibosElf64Dynamic::tag must contain + * DT_HASH + * DT_STRTAB + * DT_SYMTAB + * DT_RELA + * DT_RELASZ + * DT_RELAENT + * DT_STRSZ + * DT_SYMENT + * DT_REL + * DT_RELSZ + * DT_RELENT + * It may also contain + * DT_NEEDED - List of dynamic libraries this image depends on + * ptr is an offset in DT_STRTAB table for image name + * + * @param[in] dynamicTableHeader + * @see LibosElfHeaderDynamic + * @param[in] previous + * Previous returned dynamic table entry. Pass null to get first entry. + */ +LibosElf64Dynamic * LibosElfDynamicEntryNext(LibosElfImage * image, LibosElf64ProgramHeader * dynamicTableHeader, LibosElf64Dynamic * previous) +{ + LibosElf64Dynamic * dynamicTable = (LibosElf64Dynamic *) image->map(image, dynamicTableHeader->offset, dynamicTableHeader->filesz); + LibosElf64Dynamic * dynamicTableEnd = dynamicTable + (dynamicTableHeader->filesz / sizeof(LibosElf64Dynamic)); + + LibosElf64Dynamic * next; + if (!previous) + next = dynamicTable; + else + next = previous + 1; + + if (previous == dynamicTableEnd) + return 0; + + return next; +} + +/** + * + * @brief Locates the program header containing this region of virtual addresses. + * + * @param[in] image + * @param[in] va + * @param[in] vaLastByte + * The program header must contain all bytes in the range [va, vaLastByte] inclusive. + */ +LibosElf64ProgramHeader * LibosElfProgramHeaderForRange(LibosElfImage * image, NvU64 va, NvU64 vaLastByte) +{ + LibosElf64ProgramHeader * phdr; + for (phdr = LibosElfProgramHeaderNext(image, 0); + phdr; + phdr = LibosElfProgramHeaderNext(image, phdr)) + { + // Is this memory region within this PHDR? + if (va >= phdr->vaddr && (vaLastByte - phdr->vaddr) < phdr->memsz) + return phdr; + } + + return 0; +} + +/** + * + * @brief Find the start and end of the ELF section in memory + * from the section name. + * + * @param[in] image + * @param[in] sectionName + * The section to find such as .text or .data + * @param[out] start, end + * The start and end of the section in the loaded ELF file + * e.g validPtr >= start && validPtr < end + */ +LibosElf64SectionHeader * LibosElfFindSectionByName(LibosElfImage * image, const char *targetName) +{ + // @todo: Enumerate, and introduce function for kth section header + LibosElf64SectionHeader * shdr = (LibosElf64SectionHeader *) image->map(image, image->elf->shoff, image->elf->shnum * sizeof(LibosElf64SectionHeader)); + NvU32 i; + + if (!shdr || image->elf->shstrndx >= image->elf->shnum) + return 0; + + const char *shstr = (const char *) image->map(image, shdr[image->elf->shstrndx].offset, shdr[image->elf->shstrndx].size); + size_t shstrSize = shdr[image->elf->shstrndx].size; + + for (i = 0; i < image->elf->shnum; i++, shdr++) + { + if (shdr->name >= shstrSize) + return 0; + + const char *name = shstr + shdr->name; + + if (strncmp(name, targetName, shstrSize - shdr->name) == 0) + { + return shdr; + } + } + + return 0; +} + +/** + * + * @brief Find the start and end of the loaded section. + * + * @returns + * LibosErrorIncomplete if there are no bits assigned to the section + * @param[in] image + * @param[in] shdr + * The section header to find the start and end of. + * @param[out] start, end + * The start and end of the section in the loaded ELF file + * e.g validPtr >= start && validPtr < end + */ +LibosStatus LibosElfMapSection(LibosElfImage * image, LibosElf64SectionHeader * shdr, NvU8 ** start, NvU8 ** end) +{ + NvU8 * mapping; + + if (shdr->type == SHT_NOBITS) + // Try mapping through the PHDR as a last ditch approach + mapping = (NvU8 *) LibosElfMapVirtual(image, shdr->addr, shdr->size); + else + mapping = (NvU8 *) image->map(image, shdr->offset, shdr->size); + *start = mapping; + *end = mapping + shdr->size; + + return LibosOk; +} + +/** + * + * @brief Find the start and end of the ELF section in memory + * from the section name. + * + * @param[in] image + * @param[in] address + * Query the section containing the requested byte + */ +LibosElf64SectionHeader * LibosElfFindSectionByAddress(LibosElfImage * image, NvU64 address) +{ + LibosElf64SectionHeader * shdr; + for (shdr = LibosElfSectionHeaderNext(image, 0); shdr; shdr = LibosElfSectionHeaderNext(image, shdr)) + if (address >= shdr->addr && address < (shdr->addr + shdr->size)) + return shdr; + + return 0; +} + +/** + * + * @brief Reads an arbitrary sized block of memory by loaded VA through + * the ELF. This can be used to read data from the perspective + * of a processor who has loaded the ELF. + * + * @param[in] image + * @param[in] address + * The absolute virtual address to read + * @param[out] size + * The number of bytes that must be valid. + * @returns + * The pointer to the data in question, or NULL if the operation failed) + */ +void *LibosElfMapVirtual(LibosElfImage * image, NvU64 address, NvU64 size) +{ + LibosElf64ProgramHeader * phdr = LibosElfProgramHeaderForRange(image, address, address + size - 1); + + if (phdr != NULL) + return image->map(image, address - phdr->vaddr + phdr->offset, size); + + LibosElf64SectionHeader *shdr = LibosElfFindSectionByAddress(image, address); + + if (shdr != NULL) + { + NvU64 section_end = shdr->offset + shdr->size; + NvU64 section_offset = address - shdr->addr; + + // Compute section offset (overflow check) + NvU64 section_offset_tail = section_offset + size; + if (section_offset_tail < section_offset) + return NULL; + + // Bounds check the tail + if (section_offset_tail > (NvLength)(section_end - shdr->offset)) + return NULL; + + return image->map(image, address - shdr->addr + shdr->offset, size); + } + + return NULL; +} + +/** + * + * @brief Reads an arbitrary length string by loaded VA through + * the ELF. This can be used to read data from the perspective + * of a processor who has loaded the ELF. + * + * @param[in] image + * @param[in] address + * The virtual address of the string constant. + * @returns + * The string constant. Returns null if the string isn't entirely contained + * in the image. + */ +const char *LibosElfMapVirtualString(LibosElfImage * image, NvU64 address, NvBool checkShdrs) +{ + NvU64 stringOffset = 0; + const char * string = NULL; + + do + { + // Ensure the entire string is in the same PHDR + LibosElf64ProgramHeader * phdr = LibosElfProgramHeaderForRange(image, address, address + stringOffset); + + if (phdr == NULL && checkShdrs) + { + LibosElf64SectionHeader * shdr = LibosElfFindSectionByAddress(image, address); + + if (shdr == NULL) + return NULL; + + string = (const char *) image->map(image, shdr->offset + (address - shdr->addr), stringOffset+1); + } + else if (phdr) + { + // Update the mapping + string = (const char *) image->map(image, phdr->offset + (address - phdr->vaddr), stringOffset+1); + } + + if (!string) + return NULL; + + stringOffset++; + } while (string[stringOffset]); + + return string; +} + +#ifdef LIBOS_TOOL_BAKE + +NvBool LibosElfCommitData(LibosElfImage *elf, NvU64 commitVirtualAddress, NvU64 commitSize) + +{ + if (!commitSize) + return NV_FALSE; + + // Ensure the commit size doesn't wrap + NvU64 lastByte; + if (__builtin_add_overflow(commitVirtualAddress, commitSize - 1, &lastByte)) + return NV_FALSE; + + // Ensure that the commit region doesn't partially overlap any sections + for (LibosElf64SectionHeader * psec = LibosElfSectionHeaderNext(elf, 0); psec; psec = LibosElfSectionHeaderNext(elf, psec)) + if (lastByte >= psec->addr && (lastByte - psec->addr) < psec->size) + lastByte = psec->addr + psec->size - 1; + + // Find the containing PHDR + LibosElf64ProgramHeader * phdr = LibosElfProgramHeaderForRange(elf, commitVirtualAddress, lastByte); + + // Is the area already committed? + if (lastByte < (phdr->vaddr + phdr->filesz)) + return NV_TRUE; + + // Find insertion point in the ELF image + NvU64 insertionOffset = phdr->offset + phdr->filesz; + NvU64 insertionCount = (lastByte + 1) - (phdr->vaddr + phdr->filesz); + + // Update the file backed size + phdr->filesz = lastByte - phdr->vaddr + 1; + + // Update all PHDR offsets + for (LibosElf64ProgramHeader * phdr = LibosElfProgramHeaderNext(elf, 0); phdr; phdr = LibosElfProgramHeaderNext(elf, phdr)) + if (phdr->offset > insertionOffset) + phdr->offset += insertionCount; + + // Update all section offsets + for (LibosElf64SectionHeader * psec = LibosElfSectionHeaderNext(elf, 0); psec; psec = LibosElfSectionHeaderNext(elf, psec)) + { + if (psec->offset > insertionOffset) + psec->offset += insertionCount; + + // Did we just commit a section? Convert from nobits to progbits + if (psec->addr >= phdr->vaddr && (psec->addr+psec->size) <= (phdr->vaddr + phdr->filesz)) + if (psec->type == SHT_NOBITS) { + // @todo: Set the offset field + psec->type = SHT_PROGBITS; + } + } + + if (elf->elf->phoff > insertionOffset) + elf->elf->phoff += insertionCount; + + if (elf->elf->shoff > insertionOffset) + elf->elf->shoff += insertionCount; + + // Reallocate the file and create the hole + elf->elf = realloc(elf->elf, elf->size + insertionCount); + memmove(((NvU8*)elf->elf) + insertionOffset + insertionCount, ((NvU8*)elf->elf) + insertionOffset, elf->size - insertionOffset); + + // Zero the hole + memset(((NvU8*)elf->elf) + insertionOffset, 0, insertionCount); + + elf->size += insertionCount; + + return NV_TRUE; +} + +#endif diff --git a/src/common/uproc/os/libos-v2.0.0/debug/logdecode.c b/src/common/uproc/os/libos-v3.1.0/lib/liblogdecode.c similarity index 86% rename from src/common/uproc/os/libos-v2.0.0/debug/logdecode.c rename to src/common/uproc/os/libos-v3.1.0/lib/liblogdecode.c index 09f5b3f5c..e4213392b 100644 --- a/src/common/uproc/os/libos-v2.0.0/debug/logdecode.c +++ b/src/common/uproc/os/libos-v3.1.0/lib/liblogdecode.c @@ -42,6 +42,7 @@ # define portStringCopy(d, ld, s, ls) strncpy(d, s, ld) # define portStringLength(s) strlen(s) # define portStringLengthSafe(s, l) strlen(s) +# define portStringCompare(s1, s2, l) strncmp(s1, s2, l) # define portMemCopy(d, ld, s, ls) memcpy(d, s, ld) # define portMemSet(d, v, l) memset(d, v, l) @@ -66,7 +67,7 @@ int logPrintf(const char *, ...); // Forward declaration. TODO: allow libos code #endif // NVRM #include "nvtypes.h" -#include "logdecode.h" +#include "liblogdecode.h" #if LIBOS_LOG_DECODE_ENABLE @@ -272,6 +273,21 @@ static void states_init(void) } } +/** + * @brief Find the Log buffer corresponding to the elf section name given. + */ +static LIBOS_LOG_DECODE_LOG *_findLogBufferFromSectionName(LIBOS_LOG_DECODE *logDecode, const char *elfSectionName) +{ + NvU32 i; + for (i = 0; i < logDecode->numLogBuffers; ++i) + { + LIBOS_LOG_DECODE_LOG *pLog = &logDecode->log[i]; + if (portStringCompare(pLog->elfSectionName, elfSectionName, sizeof(pLog->elfSectionName)) == 0) + return pLog; + } + return NULL; +} + /** * * @brief Print out the line buffer and reset the current line buffer pointer. @@ -317,23 +333,23 @@ static void emit_string(const char *s, int l, LIBOS_LOG_DECODE *logDecode) } } -static void s_getSymbolDataStr(LIBOS_LOG_DECODE *logDecode, char *decodedLine, NvLength decodedLineSize, NvUPtr addr) +static void s_getSymbolDataStr(LibosDebugResolver *resolver, char *decodedLine, NvLength decodedLineSize, NvUPtr addr) { const char *directory; const char *filename; - const char *name; - NvU64 offset; + const char *name = NULL; + NvU64 offset = 0; NvU64 outputLine; NvU64 outputColumn; NvU64 matchedAddress; - if (!libosDebugResolveSymbolToName(&logDecode->resolver, addr, &name, &offset)) + if (!LibosDebugResolveSymbolToName(resolver, addr, &name, &offset)) { name = 0; } decodedLine[decodedLineSize - 1U] = '\0'; - if (libosDwarfResolveLine( - &logDecode->resolver, addr, &directory, &filename, &outputLine, &outputColumn, + if (LibosDwarfResolveLine( + resolver, addr, &directory, &filename, &outputLine, &outputColumn, &matchedAddress)) { if (name) @@ -347,12 +363,17 @@ static void s_getSymbolDataStr(LIBOS_LOG_DECODE *logDecode, char *decodedLine, N snprintf(decodedLine, decodedLineSize - 1, "??? (%s:%lld)", filename, outputLine); } } - else + else if (name) { snprintf(decodedLine, decodedLineSize - 1, "%s+%lld", name, offset); } } +void libosLogSymbolicateAddress(LIBOS_LOG_DECODE *logDecode, char *decodedLine, NvLength decodedLineSize, NvUPtr addr) +{ + s_getSymbolDataStr(&logDecode->log[0].resolver, decodedLine, decodedLineSize, addr); +} + /** * * @brief Pad a field with ' ' or '0'. @@ -696,7 +717,7 @@ static int libos_printf_a( { static char symDecodedLine[SYM_DECODED_LINE_MAX_SIZE]; - s_getSymbolDataStr(logDecode, symDecodedLine, sizeof(symDecodedLine), (NvUPtr)arg.i); + s_getSymbolDataStr(&pRec->logSymbolResolver->resolver, symDecodedLine, sizeof(symDecodedLine), (NvUPtr)arg.i); // Set common vars a = &symDecodedLine[0]; @@ -704,7 +725,7 @@ static int libos_printf_a( } goto print_string; case 's': - a = (char *)libosElfReadStringVirtual(logDecode->elf, (NvUPtr)arg.p); + a = (char *)LibosElfMapVirtualString(&pRec->log->elfImage, (NvUPtr)arg.p, NV_FALSE); if (!a) a = (char *)"(bad-pointer)"; print_string: @@ -748,7 +769,7 @@ static int libos_printf_a( symDecodedLine[prefixLen++] = '<'; #endif // NVWATCH - s_getSymbolDataStr(logDecode, symDecodedLine + prefixLen, sizeof(symDecodedLine) - prefixLen, (NvUPtr)arg.i); + s_getSymbolDataStr(&pRec->log->resolver, symDecodedLine + prefixLen, sizeof(symDecodedLine) - prefixLen, (NvUPtr)arg.i); symDecodedLineLen = portStringLength(symDecodedLine); symDecodedLineLen = MIN(symDecodedLineLen, sizeof(symDecodedLine) - 1); // just in case @@ -811,12 +832,12 @@ static void libosPrintLogRecords(LIBOS_LOG_DECODE *logDecode, NvU64 *scratchBuff } // Locate format string - format = libosElfReadStringVirtual(logDecode->elf, (NvU64)(NvUPtr)pRec->meta->format); + format = LibosElfMapVirtualString(&pRec->log->elfImage, (NvU64)(NvUPtr)pRec->meta->format, NV_TRUE); if (!format) break; // Locate filename - filename = libosElfReadStringVirtual(logDecode->elf, (NvU64)(NvUPtr)pRec->meta->filename); + filename = LibosElfMapVirtualString(&pRec->log->elfImage, (NvU64)(NvUPtr)pRec->meta->filename, NV_TRUE); if (!filename || !filename[0]) filename = "unknown"; @@ -839,6 +860,41 @@ static void libosPrintLogRecords(LIBOS_LOG_DECODE *logDecode, NvU64 *scratchBuff } } +/** + * @brief Fetch the correct metadata from the given index in the physical buffer. + * Initialize elfSectionName appropriately in case extended version of metadata is found. + */ +static libosLogMetadata *_getLoggingMetadata(LIBOS_LOG_DECODE_LOG *pLog, NvU64 idx, const char **elfSectionName) +{ + libosLogMetadata *meta = NULL; + libosLogMetadata_extended *metaEx = NULL; + const char *filename = NULL; + *elfSectionName = NULL; + + meta = (libosLogMetadata *) LibosElfMapVirtual(&pLog->elfImage, pLog->physicLogBuffer[idx], sizeof(libosLogMetadata)); + if (meta == NULL) + return NULL; + + // Try to fetch filename to check if we received an extended metadata + filename = LibosElfMapVirtualString(&pLog->elfImage, (NvU64)(NvUPtr)meta->filename, NV_TRUE); + if ((filename == NULL) && ((NvU64) meta->filename == 0x8000000000000000ULL)) + { + // Filename wasn't mapped correctly. That means this is an extended metadata. + metaEx = (libosLogMetadata_extended *) LibosElfMapVirtual(&pLog->elfImage, pLog->physicLogBuffer[idx], sizeof(libosLogMetadata_extended)); + if (metaEx == NULL) + return NULL; + meta = &metaEx->meta; + + // Fetch the remote task's elf section name string. + if (metaEx->elfSectionName != NULL) + { + *elfSectionName = LibosElfMapVirtualString(&pLog->elfImage, (NvU64)(NvUPtr)metaEx->elfSectionName, NV_TRUE); + } + } + + return meta; +} + # define LIBOS_LOG_TIMESTAMP_END 0 # define LIBOS_LOG_TIMESTAMP_MAX NV_U64_MAX @@ -868,12 +924,18 @@ static void libosExtractLog_ReadRecord(LIBOS_LOG_DECODE *logDecode, LIBOS_LOG_DE NvU64 i = pLog->putIter; NvU64 argCount; NvU64 j; + const char *elfSectionName; if (pLog->putIter == pLog->previousPut) { pLog->record.timeStamp = LIBOS_LOG_TIMESTAMP_END; return; } + if (pLog->elf == NULL) // Can't decode if task ELF isn't initialized + { + pLog->record.timeStamp = LIBOS_LOG_TIMESTAMP_END; + return; + } // If we wrapped, adjust local copy of previousPut. if (previousPut + log_entries < pLog->putCopy) @@ -899,8 +961,7 @@ static void libosExtractLog_ReadRecord(LIBOS_LOG_DECODE *logDecode, LIBOS_LOG_DE if (i < previousPut + 1) goto buffer_wrapped; - pLog->record.meta = (libosLogMetadata *)libosElfReadVirtual( - logDecode->elf, pLog->physicLogBuffer[1 + (--i % log_entries)], sizeof(libosLogMetadata)); + pLog->record.meta = _getLoggingMetadata(pLog, 1 + (--i % log_entries), &elfSectionName); // Sanity check meta data. if (pLog->record.meta == NULL || pLog->record.meta->argumentCount > LIBOS_LOG_MAX_ARGS) @@ -911,6 +972,20 @@ static void libosExtractLog_ReadRecord(LIBOS_LOG_DECODE *logDecode, LIBOS_LOG_DE goto error_ret; } + pLog->record.logSymbolResolver = pLog; + if (elfSectionName != NULL) + { + // This log is in the context of another task. + LIBOS_LOG_DECODE_LOG *pLogSymbolResolver; + + // Initialize the correct Log Buffer that will be used to resolve symbols + pLogSymbolResolver = _findLogBufferFromSectionName(logDecode, elfSectionName); + if ((pLogSymbolResolver != NULL) && (pLogSymbolResolver->elf != NULL)) + { + pLog->record.logSymbolResolver = pLogSymbolResolver; // Valid log buffer found + } + } + argCount = pLog->record.meta->argumentCount; // Check whether record goes past previous put (buffer wrapped). @@ -968,17 +1043,6 @@ static void libosExtractLogs_decode(LIBOS_LOG_DECODE *logDecode) pLog->putCopy = pLog->physicLogBuffer[0]; pLog->putIter = pLog->putCopy; - if (pLog->putIter < pLog->previousPut) - { - printf( - "**** %s-%s buffer put counter reset unexpectedly (cur=0x%llx, prev=0x%llx). Entries possibly lost. ****\n", - logDecode->sourceName, pLog->taskPrefix, pLog->putIter, pLog->previousPut); -#ifdef PORT_ASSERT - PORT_ASSERT(pLog->putIter >= pLog->previousPut); -#endif - pLog->previousPut = pLog->putIter; - } - libosExtractLog_ReadRecord(logDecode, pLog); } @@ -1233,7 +1297,7 @@ void libosLogCreateEx(LIBOS_LOG_DECODE *logDecode, const char *pSourceName) } #endif -void libosLogAddLogEx(LIBOS_LOG_DECODE *logDecode, void *buffer, NvU64 bufferSize, NvU32 gpuInstance, NvU32 gpuArch, NvU32 gpuImpl, const char *name) +void libosLogAddLogEx(LIBOS_LOG_DECODE *logDecode, void *buffer, NvU64 bufferSize, NvU32 gpuInstance, NvU32 gpuArch, NvU32 gpuImpl, const char *name, const char *elfSectionName) { NvU32 i; LIBOS_LOG_DECODE_LOG *pLog; @@ -1257,6 +1321,10 @@ void libosLogAddLogEx(LIBOS_LOG_DECODE *logDecode, void *buffer, NvU64 bufferSiz if (name) portStringCopy(pLog->taskPrefix, sizeof(pLog->taskPrefix), name, sizeof(pLog->taskPrefix)); + if (elfSectionName) + portStringCopy(pLog->elfSectionName, sizeof(pLog->elfSectionName), elfSectionName, sizeof(pLog->elfSectionName)); + else + portStringCopy(pLog->elfSectionName, sizeof(pLog->elfSectionName), "default", sizeof(pLog->elfSectionName)); #if LIBOS_LOG_TO_NVLOG NV_STATUS status; @@ -1353,18 +1421,40 @@ void libosLogAddLogEx(LIBOS_LOG_DECODE *logDecode, void *buffer, NvU64 bufferSiz #endif // LIBOS_LOG_TO_NVLOG } -void libosLogAddLog(LIBOS_LOG_DECODE *logDecode, void *buffer, NvU64 bufferSize, NvU32 gpuInstance, const char *name) +void libosLogAddLog(LIBOS_LOG_DECODE *logDecode, void *buffer, NvU64 bufferSize, NvU32 gpuInstance, const char *name, const char *elfSectionName) { // Use defaults for gpuArch and gpuImpl - libosLogAddLogEx(logDecode, buffer, bufferSize, gpuInstance, 0, 0, name); + libosLogAddLogEx(logDecode, buffer, bufferSize, gpuInstance, 0, 0, name, elfSectionName); } #if LIBOS_LOG_DECODE_ENABLE -void libosLogInit(LIBOS_LOG_DECODE *logDecode, elf64_header *elf) +static NvBool _checkIsElfContainer(LibosElfImage *image) +{ + // Container ELF will contain a section denoting that it is a container! + if (LibosElfFindSectionByName(image, ".fwIsContainerElf") == NULL) + return NV_FALSE; + + return NV_TRUE; +} + +void _libosLogInitLogBuffer(LIBOS_LOG_DECODE_LOG *pLog, LibosElf64Header *elf, NvU64 elfSize) +{ + pLog->elf = elf; + + if (elf != NULL) + { + LibosElfImageConstruct(&pLog->elfImage, elf, elfSize); + LibosDebugResolverConstruct(&pLog->resolver, &pLog->elfImage); + } +} + +void libosLogInit(LIBOS_LOG_DECODE *logDecode, LibosElf64Header *elf, NvU64 elfSize) { NvU64 scratchBufferSize = 0; NvU64 i; + NvBool bIsContainer; + LibosElfImage image; // // The scratch buffer holds the sorted records in flight from all logs. @@ -1392,36 +1482,71 @@ void libosLogInit(LIBOS_LOG_DECODE *logDecode, elf64_header *elf) // The scratch buffer is sized to handle worst-case overhead scratchBufferSize = (scratchBufferSize * LIBOS_LOG_DECODE_RECORD_BASE) / minLogBufferEntryLength; - - logDecode->elf = elf; logDecode->scratchBuffer = portMemAllocNonPaged(scratchBufferSize); logDecode->scratchBufferSize = scratchBufferSize; logDecode->curLineBufPtr = logDecode->lineBuffer; - if (elf != NULL) + if (elf == NULL) { - libosDebugResolverConstruct(&logDecode->resolver, elf); + logDecode->bIsDecodable = NV_FALSE; + return; + } + + // Set up log decoder + if (LibosElfImageConstruct(&image, elf, elfSize) == LibosOk) + { + logDecode->bIsDecodable = NV_TRUE; + } + else + { + logDecode->bIsDecodable = NV_FALSE; + return; + } + bIsContainer = _checkIsElfContainer(&image); + + // Set up individual log buffers + for (i = 0; i < logDecode->numLogBuffers; i++) + { + if (bIsContainer) + { + LibosElf64SectionHeader *sectionHdr; + NvU8 *sectionData = NULL, *sectionDataEnd; + NvU64 sectionSize = 0; + + // Initialize each log buffer with its own task's logging ELF + sectionHdr = LibosElfFindSectionByName(&image, (const char *) logDecode->log[i].elfSectionName); + if (sectionHdr != NULL) { + LibosElfMapSection(&image, sectionHdr, §ionData, §ionDataEnd); + sectionSize = sectionHdr->size; + } + _libosLogInitLogBuffer(&logDecode->log[i], (LibosElf64Header *) sectionData, sectionSize); + } + else + { + // If it isn't a container, all buffers are initialized with the common logging elf + _libosLogInitLogBuffer(&logDecode->log[i], elf, elfSize); + } } } void libosLogInitEx( - LIBOS_LOG_DECODE *logDecode, elf64_header *elf, NvBool bSynchronousBuffer, NvBool bPtrSymbolResolve) + LIBOS_LOG_DECODE *logDecode, LibosElf64Header *elf, NvBool bSynchronousBuffer, NvBool bPtrSymbolResolve, NvU64 elfSize) { // Set extended config logDecode->bSynchronousBuffer = bSynchronousBuffer; logDecode->bPtrSymbolResolve = bPtrSymbolResolve; // Complete init - libosLogInit(logDecode, elf); + libosLogInit(logDecode, elf, elfSize); } #else // LIBOS_LOG_DECODE_ENABLE -void libosLogInit(LIBOS_LOG_DECODE *logDecode, void *elf) {} +void libosLogInit(LIBOS_LOG_DECODE *logDecode, void *elf, NvU64 elfSize) {} void libosLogInitEx( LIBOS_LOG_DECODE *logDecode, void *elf, - NvBool bSynchronousBuffer, NvBool bPtrSymbolResolve) + NvBool bSynchronousBuffer, NvBool bPtrSymbolResolve, NvU64 elfSize) { // No extended config to set when decode is disabled } @@ -1451,7 +1576,12 @@ void libosLogDestroy(LIBOS_LOG_DECODE *logDecode) #endif // LIBOS_LOG_TO_NVLOG #if LIBOS_LOG_DECODE_ENABLE - libosDebugResolverDestroy(&logDecode->resolver); + NvU64 j; + for (j = 0; j < logDecode->numLogBuffers; j++) + { + LIBOS_LOG_DECODE_LOG *pLog = &logDecode->log[j]; + LibosDebugResolverDestroy(&pLog->resolver); + } if (logDecode->scratchBuffer) { @@ -1464,7 +1594,7 @@ void libosLogDestroy(LIBOS_LOG_DECODE *logDecode) void libosExtractLogs(LIBOS_LOG_DECODE *logDecode, NvBool bSyncNvLog) { #if LIBOS_LOG_DECODE_ENABLE - if (logDecode->elf != NULL) + if (logDecode->bIsDecodable) libosExtractLogs_decode(logDecode); #endif diff --git a/src/nvidia-modeset/Makefile b/src/nvidia-modeset/Makefile index 965e647b9..9ef3c62e9 100644 --- a/src/nvidia-modeset/Makefile +++ b/src/nvidia-modeset/Makefile @@ -9,6 +9,13 @@ include ../../utils.mk include srcs.mk +############################################################################## +# Helper functions to determine the compiler type +############################################################################## +GET_COMPILER_TYPE = \ + $(shell $(VERSION_MK_DIR)/nv-compiler.sh type $(1)) +############################################################################## + # The source files for nv-modeset-kernel.o are all SRCS and SRCS_CXX defined in # srcs.mk, and the NVIDIA ID string ALL_SRCS = $(SRCS) $(SRCS_CXX) @@ -16,9 +23,12 @@ ALL_SRCS += $(NVIDSTRING) SRC_COMMON = ../common +CONDITIONAL_CFLAGS := + CFLAGS += -include $(SRC_COMMON)/sdk/nvidia/inc/cpuopsys.h CFLAGS += -I $(SRC_COMMON)/sdk/nvidia/inc +CFLAGS += -I $(SRC_COMMON)/sdk/nvidia/inc/hw CFLAGS += -I $(SRC_COMMON)/shared/inc CFLAGS += -I $(SRC_COMMON)/inc CFLAGS += -I $(SRC_COMMON)/softfloat/nvidia @@ -96,10 +106,40 @@ CFLAGS += -ffunction-sections CFLAGS += -fdata-sections CFLAGS += -ffreestanding -CONDITIONAL_CFLAGS := $(call TEST_CC_ARG, -fcf-protection=none) CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -Wformat-overflow=2) CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -Wformat-truncation=1) + ifeq ($(TARGET_ARCH),x86_64) + COMPILER_TYPE := $(call GET_COMPILER_TYPE, $(CC)) + ENDBR_SUPPORTED := $(call AS_HAS_INSTR, endbr64) + + FCF_SUPPORTED = + + # + # GCC flags -fcf-protection=branch and -mindirect-branch=extern-thunk can + # be used together after GCC version 9.4.0. See + # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93654 for details. + # Check if GCC version is appropriate. + # + ifeq ($(COMPILER_TYPE),gcc) + FCF_SUPPORTED := \ + $(shell $(VERSION_MK_DIR)/nv-compiler.sh version_is_at_least $(CC) 90400) + endif + + # + # Clang version 14.0.0 is required for -fcf-protection=branch to work + # correctly. See commit + # https://github.com/llvm/llvm-project/commit/dfcf69770bc522b9e411c66454934a37c1f35332 + # + ifeq ($(COMPILER_TYPE),clang) + FCF_SUPPORTED := \ + $(shell $(VERSION_MK_DIR)/nv-compiler.sh version_is_at_least $(CC) 140000) + endif + + ifeq ($(FCF_SUPPORTED)-$(ENDBR_SUPPORTED),1-1) + CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -fcf-protection=branch) + endif + CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -fno-jump-tables) CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -mindirect-branch=thunk-extern) CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -mindirect-branch-register) endif @@ -119,7 +159,38 @@ CXX_ONLY_CFLAGS += -fcheck-new SHADER_OBJS = - CFLAGS += -DNVKMS_INCLUDE_HEADSURFACE=0 + CFLAGS += -DNVKMS_INCLUDE_HEADSURFACE=1 + + CFLAGS += -I $(SRC_COMMON)/unix/nvidia-3d/interface + CFLAGS += -I $(SRC_COMMON)/unix/nvidia-push/interface + CFLAGS += -I $(SRC_COMMON)/unix/nvidia-3d/include + CFLAGS += -I $(SRC_COMMON)/unix/nvidia-push/include + CFLAGS += -I $(SRC_COMMON)/unix/xzminidec/interface + CFLAGS += -I $(SRC_COMMON)/unix/nvidia-headsurface + CFLAGS += -I src/shaders + + CFLAGS += -DNV_PUSH_IN_KERNEL + CFLAGS += -DNV_XZ_CUSTOM_MEM_HOOKS + CFLAGS += -DNV_XZ_USE_NVTYPES + CFLAGS += -DXZ_DEC_SINGLE + + # Compress the shaders and embed in ELF object files. + define COMPRESS_SHADERS + $$(OUTPUTDIR)/$(1)_shaders.xz: src/shaders/g_$(1)_shaders + @$(MKDIR) $$(OUTPUTDIR) + $$(call quiet_cmd,XZ) -ce -C none < $$^ > $$@ + + $$(eval $$(call READ_ONLY_OBJECT_FROM_FILE_RULE,$$(OUTPUTDIR)/$(1)_shaders.xz)) + + SHADER_OBJS += $$(OUTPUTDIR)/$(1)_shaders.xz.o + endef + + $(eval $(call COMPRESS_SHADERS,maxwell)) + $(eval $(call COMPRESS_SHADERS,pascal)) + $(eval $(call COMPRESS_SHADERS,volta)) + $(eval $(call COMPRESS_SHADERS,turing)) + $(eval $(call COMPRESS_SHADERS,ampere)) + $(eval $(call COMPRESS_SHADERS,hopper)) OBJS = $(call BUILD_OBJECT_LIST,$(ALL_SRCS)) OBJS += $(SHADER_OBJS) @@ -134,11 +205,12 @@ $(foreach src, $(ALL_SRCS), $(eval $(call DEFINE_OBJECT_RULE,TARGET,$(src)))) NV_MODESET_KERNEL_O = $(OUTPUTDIR)/nv-modeset-kernel.o -.PNONY: all clean +.PHONY: all all: $(NV_MODESET_KERNEL_O) $(NV_MODESET_KERNEL_O): $(OBJS) $(call quiet_cmd,LD) -r -o $(NV_MODESET_KERNEL_O) $(OBJS) +.PHONY: clean clean: $(RM) -rf $(OUTPUTDIR) diff --git a/src/nvidia-modeset/include/nvkms-difr.h b/src/nvidia-modeset/include/nvkms-difr.h new file mode 100644 index 000000000..f00e8969d --- /dev/null +++ b/src/nvidia-modeset/include/nvkms-difr.h @@ -0,0 +1,45 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __NVKMS_DIFR_H__ +#define __NVKMS_DIFR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nvkms-types.h" + +NVDIFRStateEvoPtr nvDIFRAllocate(NVDevEvoPtr pDevEvo); +void nvDIFRFree(NVDIFRStateEvoPtr pDifr); + +void nvDIFRNotifyFlip(NVDIFRStateEvoPtr pDifr); +NvU32 nvDIFRPrefetchSurfaces(NVDIFRStateEvoPtr pDifr, + size_t l2CacheSize); +NvBool nvDIFRSendPrefetchResponse(NVDIFRStateEvoPtr pDifr, + NvU32 responseStatus); + +#ifdef __cplusplus +}; +#endif + +#endif /* __NVKMS_DIFR_H__ */ diff --git a/src/nvidia-modeset/include/nvkms-dma.h b/src/nvidia-modeset/include/nvkms-dma.h index b1802301b..6e6f6c39d 100644 --- a/src/nvidia-modeset/include/nvkms-dma.h +++ b/src/nvidia-modeset/include/nvkms-dma.h @@ -283,4 +283,7 @@ static inline NvBool nvIsUpdateStateEmpty(const NVDevEvoRec *pDevEvo, return TRUE; } +NvBool nvEvoPollForEmptyChannel(NVEvoChannelPtr pChannel, NvU32 sd, + NvU64 *pStartTime, const NvU32 timeout); + #endif /* __NVKMS_DMA_H__ */ diff --git a/src/nvidia-modeset/include/nvkms-dpy.h b/src/nvidia-modeset/include/nvkms-dpy.h index 2b1e2acf1..376237937 100644 --- a/src/nvidia-modeset/include/nvkms-dpy.h +++ b/src/nvidia-modeset/include/nvkms-dpy.h @@ -39,7 +39,7 @@ NVDpyEvoPtr nvAllocDpyEvo(NVDispEvoPtr pDispEvo, void nvFreeDpyEvo(NVDispEvoPtr pDispEvo, NVDpyEvoPtr pDpyEvo); NVConnectorEvoPtr nvGetConnectorFromDisp(NVDispEvoPtr pDispEvo, NVDpyId dpyId); -void nvUpdateInfoFrames(const NVDispEvoRec *pDispEvo, const NvU32 head); +void nvUpdateInfoFrames(NVDpyEvoRec *pDpyEvo); NvBool nvDpyRequiresDualLinkEvo(const NVDpyEvoRec *pDpyEvo, const NVHwModeTimingsEvo *pTimings); diff --git a/src/nvidia-modeset/include/nvkms-evo.h b/src/nvidia-modeset/include/nvkms-evo.h index 4f6a73255..4ce68b712 100644 --- a/src/nvidia-modeset/include/nvkms-evo.h +++ b/src/nvidia-modeset/include/nvkms-evo.h @@ -63,8 +63,6 @@ nvConstructNvModeTimingsFromHwModeTimings(const NVHwModeTimingsEvo *pTimings, NvModeTimingsPtr pModeTimings); void nvEvoSetTimings(NVDispEvoPtr pDispEvo, const NvU32 head, NVEvoUpdateState *updateState); -NvBool nvGetDfpProtocol(const NVDpyEvoRec *pDpyEvo, - NVHwModeTimingsEvoPtr pTimings); void nvInitScalingUsageBounds(const NVDevEvoRec *pDevEvo, struct NvKmsScalingUsageBounds *pScaling); NvBool nvComputeScalingUsageBounds(const NVEvoScalerCaps *pScalerCaps, @@ -84,8 +82,9 @@ NvBool nvValidateHwModeTimingsViewPort(const NVDevEvoRec *pDevEvo, NVEvoInfoStringPtr pInfoString); void nvAssignDefaultUsageBounds(const NVDispEvoRec *pDispEvo, NVHwModeViewPortEvo *pViewPort); -struct NvKmsUsageBounds nvUnionUsageBounds(const struct NvKmsUsageBounds *a, - const struct NvKmsUsageBounds *b); +void nvUnionUsageBounds(const struct NvKmsUsageBounds *a, + const struct NvKmsUsageBounds *b, + struct NvKmsUsageBounds *ret); NvBool UsageBoundsEqual(const struct NvKmsUsageBounds *a, const struct NvKmsUsageBounds *b); NvU64 nvEvoGetFormatsWithEqualOrLowerUsageBound( @@ -112,11 +111,16 @@ void nvEnableMidFrameAndDWCFWatermark(NVDevEvoPtr pDevEvo, void nvEvoHeadSetControlOR(NVDispEvoPtr pDispEvo, const NvU32 head, NVEvoUpdateState *pUpdateState); +void nvChooseDitheringEvo( + const NVConnectorEvoRec *pConnectorEvo, + const enum nvKmsPixelDepth pixelDepth, + const NVDpyAttributeRequestedDitheringConfig *pReqDithering, + NVDpyAttributeCurrentDitheringConfig *pCurrDithering); + void nvSetDitheringEvo( - NVDispEvoPtr pDispEvo, const NvU32 head, - enum NvKmsDpyAttributeRequestedDitheringValue configState, - const enum NvKmsDpyAttributeRequestedDitheringDepthValue configDepth, - const enum NvKmsDpyAttributeRequestedDitheringModeValue configMode, + NVDispEvoPtr pDispEvo, + const NvU32 head, + const NVDpyAttributeCurrentDitheringConfig *pCurrDithering, NVEvoUpdateState *pUpdateState); NvBool nvEnableFrameLockEvo(NVDispEvoPtr pDispEvo); @@ -128,6 +132,7 @@ NvBool nvAllowFlipLockEvo(NVDispEvoPtr pDispEvo, NvS64 value); NvBool nvSetStereoEvo(const NVDispEvoRec *pDispEvo, const NvU32 head, NvBool enable); NvBool nvGetStereoEvo(const NVDispEvoRec *pDispEvo, const NvU32 head); +struct NvKmsCompositionParams nvDefaultCursorCompositionParams(const NVDevEvoRec *pDevEvo); NvBool nvAllocCoreChannelEvo(NVDevEvoPtr pDevEvo); void nvFreeCoreChannelEvo(NVDevEvoPtr pDevEvo); @@ -162,7 +167,8 @@ NvBool nvConstructHwModeTimingsImpCheckEvo( NvBool nvDowngradeHwModeTimingsDpPixelDepthEvo( NVHwModeTimingsEvoPtr pTimings, - const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace); + const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, + const enum NvKmsDpyAttributeColorRangeValue colorRange); NvBool nvDPValidateModeEvo(NVDpyEvoPtr pDpyEvo, NVHwModeTimingsEvoPtr pTimings, @@ -213,7 +219,9 @@ NvBool nvValidateSetLutCommonParams( const struct NvKmsSetLutCommonParams *pParams); void nvChooseCurrentColorSpaceAndRangeEvo( - const NVHwModeTimingsEvo *pTimings, + enum nvKmsPixelDepth pixelDepth, + enum NvYuv420Mode yuv420Mode, + enum NvKmsOutputTf tf, const enum NvKmsDpyAttributeRequestedColorSpaceValue requestedColorSpace, const enum NvKmsDpyAttributeColorRangeValue requestedColorRange, enum NvKmsDpyAttributeCurrentColorSpaceValue *pCurrentColorSpace, @@ -226,12 +234,6 @@ void nvUpdateCurrentHardwareColorSpaceAndRangeEvo( const enum NvKmsDpyAttributeColorRangeValue colorRange, NVEvoUpdateState *pUpdateState); -void nvSetColorSpaceAndRangeEvo( - NVDispEvoPtr pDispEvo, const NvU32 head, - const enum NvKmsDpyAttributeRequestedColorSpaceValue requestedColorSpace, - const enum NvKmsDpyAttributeColorRangeValue requestedColorRange, - NVEvoUpdateState *pUpdateState); - NvBool nvAssignSOREvo(NVConnectorEvoPtr pConnectorEvo, NvU32 sorExcludeMask); void nvRestoreSORAssigmentsEvo(NVDevEvoRec *pDevEvo); @@ -292,6 +294,19 @@ void nvDPSerializerPostSetMode(NVDispEvoPtr pDispEvo, NvBool nvFramelockSetControlUnsyncEvo(NVDispEvoPtr pDispEvo, const NvU32 headMask, NvBool server); +NvBool nvIsHDRCapableHead(NVDispEvoPtr pDispEvo, + NvU32 apiHead); + +NvU32 nvGetHDRSrcMaxLum(const NVFlipChannelEvoHwState *pHwState); + +NvBool nvNeedsTmoLut(NVDevEvoPtr pDevEvo, + NVEvoChannelPtr pChannel, + const NVFlipChannelEvoHwState *pHwState, + NvU32 srcMaxLum, + NvU32 targetMaxCLL); + +NvBool nvIsCscMatrixIdentity(const struct NvKmsCscMatrix *matrix); + #ifdef __cplusplus }; #endif diff --git a/src/nvidia-modeset/include/nvkms-flip-workarea.h b/src/nvidia-modeset/include/nvkms-flip-workarea.h index a2bb25b82..7d1b2d0c8 100644 --- a/src/nvidia-modeset/include/nvkms-flip-workarea.h +++ b/src/nvidia-modeset/include/nvkms-flip-workarea.h @@ -41,9 +41,6 @@ struct NvKmsFlipWorkArea { NVFlipEvoHwState newState; NVFlipEvoHwState oldState; - - NvU32 oldAccelerators; - NvBool accelerated; } head[NVKMS_MAX_HEADS_PER_DISP]; } sd[NVKMS_MAX_SUBDEVICES]; }; diff --git a/src/nvidia-modeset/include/nvkms-flip.h b/src/nvidia-modeset/include/nvkms-flip.h index e02f7f69d..1fb3686a7 100644 --- a/src/nvidia-modeset/include/nvkms-flip.h +++ b/src/nvidia-modeset/include/nvkms-flip.h @@ -36,6 +36,20 @@ void nvInitFlipEvoHwState( const NvU32 head, NVFlipEvoHwState *pFlipState); +NvBool nvAssignSurfaceArray( + const NVDevEvoRec *pDevEvo, + const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, + const NvKmsSurfaceHandle surfaceHandles[NVKMS_MAX_EYES], + const NvBool isUsedByCursorChannel, + const NvBool isUsedByLayerChannel, + NVSurfaceEvoPtr pSurfaceEvos[NVKMS_MAX_EYES]); + +NvBool +nvAssignCursorSurface(const struct NvKmsPerOpenDev *pOpenDev, + const NVDevEvoRec *pDevEvo, + const struct NvKmsSetCursorImageCommonParams *pImgParams, + NVSurfaceEvoPtr *pSurfaceEvo); + NvBool nvUpdateFlipEvoHwState( const struct NvKmsPerOpenDev *pOpenDev, const NVDevEvoRec *pDevEvo, @@ -43,8 +57,13 @@ NvBool nvUpdateFlipEvoHwState( const NvU32 head, const struct NvKmsFlipCommonParams *pParams, NVFlipEvoHwState *pFlipState, - NvBool allowVrr, - const struct NvKmsUsageBounds *pPossibleUsage); + NvBool allowVrr); + +void +nvOverrideScalingUsageBounds(const NVDevEvoRec *pDevEvo, + NvU32 head, + NVFlipEvoHwState *pFlipState, + const struct NvKmsUsageBounds *pPossibleUsage); NvBool nvValidateFlipEvoHwState( const NVDevEvoRec *pDevEvo, @@ -70,12 +89,6 @@ void nvFlipEvoOneHead( void nvEvoCancelPostFlipIMPTimer( NVDevEvoPtr pDevEvo); -NvBool nvHandleSyncptRegistration( - NVDevEvoRec *pDevEvo, - NvU32 head, - const struct NvKmsFlipCommonParams *pParams, - NVFlipEvoHwState *pFlipState); - void nvFillPostSyncptReplyOneChannel( NVEvoChannel *pChannel, enum NvKmsSyncptType postType, @@ -89,4 +102,19 @@ NvBool nvFlipEvo(NVDevEvoPtr pDevEvo, NvBool skipUpdate, NvBool allowFlipLock); +void nvApiHeadGetLayerSurfaceArray(const NVDispEvoRec *pDispEvo, + const NvU32 apiHead, + const NvU32 layer, + NVSurfaceEvoPtr pSurfaceEvos[NVKMS_MAX_EYES]); + +void nvApiHeadGetCursorInfo(const NVDispEvoRec *pDispEvo, + const NvU32 apiHead, + NVSurfaceEvoPtr *ppSurfaceEvo, + NvS16 *x, NvS16 *y); + +void nvApiHeadSetViewportPointIn(const NVDispEvoRec *pDispEvo, + const NvU32 apiHead, + const NvU16 x, + const NvU16 y); + #endif /* __NVKMS_FLIP_H__ */ diff --git a/src/nvidia-modeset/include/nvkms-hdmi.h b/src/nvidia-modeset/include/nvkms-hdmi.h index 69f6cd958..93341ecd3 100644 --- a/src/nvidia-modeset/include/nvkms-hdmi.h +++ b/src/nvidia-modeset/include/nvkms-hdmi.h @@ -33,8 +33,7 @@ extern "C" { void nvUpdateHdmiInfoFrames(const NVDispEvoRec *pDispEvo, const NvU32 head, const NVAttributesSetEvoRec *pAttributesSet, - const NvBool hdTimings, - const NVT_VIDEO_INFOFRAME_CTRL *pCtrl, + const NVDispHeadInfoFrameStateEvoRec *pInfoFrameState, NVDpyEvoRec *pDpyEvo); void nvDpyUpdateHdmiPreModesetEvo(NVDpyEvoPtr pDpyEvo); diff --git a/src/nvidia-modeset/include/nvkms-headsurface-3d.h b/src/nvidia-modeset/include/nvkms-headsurface-3d.h new file mode 100644 index 000000000..fe00775d5 --- /dev/null +++ b/src/nvidia-modeset/include/nvkms-headsurface-3d.h @@ -0,0 +1,70 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVKMS_HEADSURFACE_3D_H__ +#define __NVKMS_HEADSURFACE_3D_H__ + +#include "nvkms-types.h" +#include "nvkms-headsurface.h" +#include "nvkms-headsurface-priv.h" +#include "nvkms-headsurface-config.h" + +NvBool nvHs3dAllocDevice(NVHsDeviceEvoPtr pHsDevice); + +void nvHs3dFreeDevice(NVHsDeviceEvoPtr pHsDevice); + +NvBool nvHs3dAllocChannel(NVHsChannelEvoPtr pHsChannel); + +void nvHs3dFreeChannel(NVHsChannelEvoPtr pHsChannel); + +void nvHs3dClearSurface( + NVHsChannelEvoPtr pHsChannel, + const NVHsSurfaceRec *pHsSurface, + const struct NvKmsRect surfaceRect, + NvBool yuv420); + +void nvHs3dSetConfig(NVHsChannelEvoPtr pHsChannel); + +NvBool nvHs3dRenderFrame( + NVHsChannelEvoPtr pHsChannel, + const NvHsNextFrameRequestType requestType, + const NvBool honorSwapGroupClipList, + const NvU8 dstEye, + const NvU8 dstBufferIndex, + const enum NvKmsPixelShiftMode pixelShift, + const struct NvKmsRect destRect, + const NVSurfaceEvoRec *pSurfaceEvo[NVKMS_MAX_LAYERS_PER_HEAD]); + +void nvHs3dReleaseSemaphore( + NVHsChannelEvoPtr pHsChannel, + const NVSurfaceEvoRec *pSurfaceEvo, + const enum NvKmsNIsoFormat nIsoFormat, + const NvU16 offsetInWords, + const NvU32 payload, + const NvBool allPreceedingReads); + +NvU32 nvHs3dLastRenderedOffset(NVHsChannelEvoPtr pHsChannel); + +void nvHs3dPushPendingViewportFlip(NVHsChannelEvoPtr pHsChannel); + +#endif /* __NVKMS_HEADSURFACE_3D_H__ */ diff --git a/src/nvidia-modeset/include/nvkms-headsurface-config.h b/src/nvidia-modeset/include/nvkms-headsurface-config.h new file mode 100644 index 000000000..9f1e167ee --- /dev/null +++ b/src/nvidia-modeset/include/nvkms-headsurface-config.h @@ -0,0 +1,239 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVKMS_HEADSURFACE_CONFIG_H__ +#define __NVKMS_HEADSURFACE_CONFIG_H__ + +#include "nvkms-types.h" +#include "nvkms-modeset-types.h" /* NVProposedModeSetHwState */ +#include "nvkms-softfloat.h" /* NvKmsMatrixF32 */ +#include "nvidia-headsurface-types.h" /* NvHsStaticWarpMesh */ +#include "g_shader_names.h" /* ProgramName */ + +typedef enum { + /* + * The head config does not need headSurface; there would be + * nothing headSurface could do to make the configuration + * achievable. + */ + NVKMS_HEAD_SURFACE_CONFIG_STATE_NO_HEAD_SURFACE, + + /* + * The head config might be achievable in hardware, but + * headSurface might help if we fail to program it in hardware. + */ + NVKMS_HEAD_SURFACE_CONFIG_STATE_MAYBE_HEAD_SURFACE, + + /* + * HeadSurface is needed, but display hardware should still be used for + * ViewPortOut positioning within Raster. I.e., from a display hardware + * standpoint, ViewPortIn == ViewPortOut, but ViewPortOut!=Raster. + */ + NVKMS_HEAD_SURFACE_CONFIG_STATE_PARTIAL_HEAD_SURFACE, + + /* + * HeadSurface is needed, and should also be used for ViewPortOut + * scaling. I.e., from a display hardware standpoint, ViewPortIn + * == ViewPortOut, and ViewPortOut == Raster. + */ + NVKMS_HEAD_SURFACE_CONFIG_STATE_FULL_HEAD_SURFACE, +} NVHsConfigState; + +/* + * Configuration state to be used by NVHsChannelEvoRec. + */ +typedef struct { + + NVHsConfigState state; + + /* + * Which eyes are required by this headSurface configuration. Valid + * combinations are: + * + * NVBIT(NVKMS_LEFT), or + * NVBIT(NVKMS_LEFT) | NVBIT(NVKMS_RIGHT) + */ + NvU8 eyeMask; + + /* + * The dimensions of headSurface frames. This is only assigned if ::state + * is PARTIAL_HEAD_SURFACE or FULL_HEAD_SURFACE. + * + * If state is PARTIAL_HEAD_SURFACE, then frameSize will be the size of the + * display engine's viewPortOut. Any difference between the + * client-requested viewPortOut and the active raster region will be + * resolved by the display engine. Also, NVHsChannelConfig::viewPortOut + * will equal frameSize. + * + * If state is FULL_HEAD_SURFACE, then frameSize will be the same size as + * the display engine's active raster region. Any difference between the + * client-requested viewPortOut and the active raster region will be + * resolved by headSurface. NVHsChannelConfig::viewPortOut might be smaller + * than frameSize. + */ + struct NvKmsSize frameSize; + + /* + * The size of the surface for headSurface. + * + * Normally, ::surfaceSize will be equal to ::frameSize. However, when + * SwapGroup is enabled, surfaceSize is bloated to twice ::frameSize. + * + * Note that the actual vidmem surface might be allocated larger than + * surfaceSize: the video memory allocation is the maximum of the + * surfaceSize for this head across all subdevices. + */ + struct NvKmsSize surfaceSize; + + /* + * When SwapGroup is enabled, we need a staging surface to perform + * screen-aligned 2d blits to assemble frames of SwapGroup and non-SwapGroup + * content, prior to applying headSurface transformations. + * + * When SwapGroup is not enabled ::stagingSurfaceSize will be zero size. + */ + struct NvKmsSize stagingSurfaceSize; + + /* The region within the headSurface surfaces, where the image should be + rendered. */ + struct NvKmsRect viewPortOut; + + /* The region headSurface will read from. */ + struct NvKmsRect viewPortIn; + + NvBool hs10bpcHint; + NvBool yuv420; + NvBool blendAfterWarp; + + enum NvKmsPixelShiftMode pixelShift; + enum NvKmsResamplingMethod resamplingMethod; + struct NvKmsMatrixF32 transform; + NvHsStaticWarpMesh staticWarpMesh; + + /* + * Note that any NVSurfaceEvoPtr's stored here require special attention + * for reference counting. See, e.g., HsConfigUpdateSurfaceRefCount(). + */ + + NVSurfaceEvoPtr pBlendTexSurface; + NVSurfaceEvoPtr pOffsetTexSurface; + + struct { + NVSurfaceEvoPtr pSurface; + NvU32 vertexCount; + enum NvKmsWarpMeshDataType dataType; + } warpMesh; + + NVFlipCursorEvoHwState cursor; + + /* XXX NVKMS HEADSURFACE TODO: plumb through dvc */ + NvS32 dvc; + + NvBool neededForModeset; + NvBool neededForSwapGroup; + +} NVHsChannelConfig; + +typedef struct { + + NVHsChannelEvoPtr pHsChannel; + NvBool channelReused; + + NVHsChannelConfig channelConfig; + + /* The initial surfaces to read from when initializing headSurface. */ + struct { + NVSurfaceEvoPtr pSurfaceEvo[NVKMS_MAX_EYES]; + } layer[NVKMS_MAX_LAYERS_PER_HEAD]; +} NVHsConfigOneHead; + +typedef struct { + /* State that is per-disp, per-api-head. */ + NVHsConfigOneHead apiHead[NVKMS_MAX_SUBDEVICES][NVKMS_MAX_HEADS_PER_DISP]; + + /* State that is per-head, but spans subdevices. */ + NVHsStateOneHeadAllDisps apiHeadAllDisps[NVKMS_MAX_HEADS_PER_DISP]; + + /* + * Whether apiHeadAllDisps[]::surface[] were reused from the current + * configuration. + * + * surfacesReused[] is indexed by the api heads. + */ + NvBool surfacesReused[NVKMS_MAX_HEADS_PER_DISP]; + + /* + * Whether the modeset asked to apply the requested configuration, or only + * test if the requested configuration is valid. I.e., + * NvKmsSetModeParams::request::commit. + */ + NvBool commit; + +} NVHsConfig; + +NvBool nvHsConfigInitModeset( + NVDevEvoRec *pDevEvo, + const struct NvKmsSetModeRequest *pRequest, + struct NvKmsSetModeReply *pReply, + const struct NvKmsPerOpenDev *pOpenDev, + NVHsConfig *pHsConfig); + +void nvHsConfigInitSwapGroup( + const NVDevEvoRec *pDevEvo, + const NVSwapGroupRec *pSwapGroup, + const NvBool neededForSwapGroup, + NVHsConfig *pHsConfig); + +NvBool nvHsConfigDowngrade( + NVDevEvoRec *pDevEvo, + const struct NvKmsSetModeRequest *pRequest, + NVHsConfig *pHsConfig); + +NvBool nvHsConfigAllocResources( + NVDevEvoRec *pDevEvo, + NVHsConfig *pHsConfig); + +void nvHsConfigFreeResources( + NVDevEvoRec *pDevEvo, + NVHsConfig *pHsConfig); + +void nvHsConfigStop( + NVDevEvoPtr pDevEvo, + const NVHsConfig *pHsConfig); + +void nvHsConfigStart( + NVDevEvoPtr pDevEvo, + NVHsConfig *pHsConfig); + +NvBool nvHsConfigPatchSetModeRequest(const NVDevEvoRec *pDevEvo, + const NVHsConfig *pHsConfig, + struct NvKmsPerOpenDev *pOpenDev, + struct NvKmsSetModeRequest *pRequest, + NvU32 patchedHeadsMask[NVKMS_MAX_SUBDEVICES]); +void +nvHsConfigClearPatchedSetModeRequest(const NVDevEvoRec *pDevEvo, + struct NvKmsPerOpenDev *pOpenDev, + struct NvKmsSetModeRequest *pRequest, + const NvU32 patchedHeadsMask[NVKMS_MAX_SUBDEVICES]); + +#endif /* __NVKMS_HEADSURFACE_CONFIG_H__ */ diff --git a/src/nvidia-modeset/include/nvkms-headsurface-ioctl.h b/src/nvidia-modeset/include/nvkms-headsurface-ioctl.h new file mode 100644 index 000000000..10e977ad9 --- /dev/null +++ b/src/nvidia-modeset/include/nvkms-headsurface-ioctl.h @@ -0,0 +1,48 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVKMS_HEADSURFACE_IOCTL_H__ +#define __NVKMS_HEADSURFACE_IOCTL_H__ + +#include "nvkms-types.h" +#include "nvkms-api.h" + +NvBool nvHsIoctlMoveCursor( + NVDispEvoPtr pDispEvo, + NvU32 head, + const struct NvKmsMoveCursorCommonParams *pParams); + +NvBool nvHsIoctlSetCursorImage( + NVDispEvoPtr pDispEvo, + const struct NvKmsPerOpenDev *pOpenDevice, + const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, + NvU32 head, + const struct NvKmsSetCursorImageCommonParams *pParams); + +NvBool nvHsIoctlFlip( + NVDevEvoPtr pDevEvo, + const struct NvKmsPerOpenDev *pOpenDev, + const struct NvKmsFlipRequest *pRequest, + struct NvKmsFlipReply *pReply); + +#endif /* __NVKMS_HEADSURFACE_IOCTL_H__ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gspc.h b/src/nvidia-modeset/include/nvkms-headsurface-matrix.h similarity index 74% rename from src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gspc.h rename to src/nvidia-modeset/include/nvkms-headsurface-matrix.h index 419d00649..7f8dddc59 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gspc.h +++ b/src/nvidia-modeset/include/nvkms-headsurface-matrix.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2005-2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,12 +21,13 @@ * DEALINGS IN THE SOFTWARE. */ -#pragma once +#ifndef __NVKMS_HEADSURFACE_MATRIX_H__ +#define __NVKMS_HEADSURFACE_MATRIX_H__ -#include +#include "nvkms-headsurface-config.h" -// -// This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl0000/ctrl0000gspc.finn -// +NvBool nvHsAssignTransformMatrix( + NVHsChannelConfig *pChannelConfig, + const struct NvKmsSetModeHeadSurfaceParams *p); +#endif /* __NVKMS_HEADSURFACE_MATRIX_H__ */ diff --git a/src/nvidia-modeset/include/nvkms-headsurface-priv.h b/src/nvidia-modeset/include/nvkms-headsurface-priv.h new file mode 100644 index 000000000..ca4a61a60 --- /dev/null +++ b/src/nvidia-modeset/include/nvkms-headsurface-priv.h @@ -0,0 +1,530 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVKMS_HEADSURFACE_PRIV_H__ +#define __NVKMS_HEADSURFACE_PRIV_H__ + +#include "nvkms-types.h" +#include "nvkms-headsurface.h" +#include "nvkms-headsurface-config.h" +#include "nvkms-surface.h" +#include "nvkms-utils.h" + +#include "nvidia-push-init.h" +#include "nvidia-3d.h" + +#include "nv_list.h" + +/* + * This header file defines structures shared by the nvkms-headsurface*.c source + * files. To the rest of nvkms, these structures should be opaque. + */ + +#define NVKMS_HEAD_SURFACE_MAX_NOTIFIERS_PER_HEAD 4 +#define NVKMS_HEAD_SURFACE_MAX_NOTIFIER_SIZE 16 +#define NVKMS_HEAD_SURFACE_NOTIFIER_BYTES_PER_HEAD \ + (NVKMS_HEAD_SURFACE_MAX_NOTIFIERS_PER_HEAD * \ + NVKMS_HEAD_SURFACE_MAX_NOTIFIER_SIZE) + +#define NVKMS_HEAD_SURFACE_MAX_FRAME_SEMAPHORES 2 + +#define NVKMS_HEAD_SURFACE_SEMAPHORE_BYTES_PER_HEAD \ + (sizeof(NvGpuSemaphore) * NVKMS_HEAD_SURFACE_MAX_FRAME_SEMAPHORES) + +#define NVKMS_HEAD_SURFACE_FRAME_SEMAPHORE_DISPLAYABLE 0xFFFFFFFF +#define NVKMS_HEAD_SURFACE_FRAME_SEMAPHORE_RENDERABLE 0x11111111 + +/* + * XXX NVKMS HEADSURFACE TODO: HeadSurface uses both notifiers and semaphores + * for synchronization: + * + * - Notifiers to ensure the CPU waits until after the previous frame's flip + * completes before starting the next frame. + * + * - Semaphores to ensure the flip to the next frame is not started until the + * rendering for the next frame completes. + * + * We should simplify things by using semaphores for both. + */ +typedef struct _NVHsNotifiersOneSdRec { + NvU8 notifier + [NVKMS_MAX_HEADS_PER_DISP][NVKMS_HEAD_SURFACE_NOTIFIER_BYTES_PER_HEAD]; + NvU8 semaphore + [NVKMS_MAX_HEADS_PER_DISP][NVKMS_HEAD_SURFACE_SEMAPHORE_BYTES_PER_HEAD]; +} NVHsNotifiersOneSdRec; + +#define NVKMS_HEAD_SURFACE_NOTIFIERS_SIZE_IN_BYTES 4096 + +ct_assert(NVKMS_HEAD_SURFACE_NOTIFIERS_SIZE_IN_BYTES >= + sizeof(NVHsNotifiersOneSdRec)); + +typedef struct _NVHsNotifiersRec { + + NvU32 rmHandle; + NvKmsSurfaceHandle nvKmsHandle; + const NVSurfaceEvoRec *pSurfaceEvo; + + struct { + NVHsNotifiersOneSdRec *ptr; + struct { + NvU8 nextSlot; + } apiHead[NVKMS_MAX_HEADS_PER_DISP]; + } sd[NVKMS_MAX_SUBDEVICES]; + + enum NvKmsNIsoFormat nIsoFormat; + +} NVHsNotifiersRec; + +typedef struct _NVHsSurfaceRec { + + NvKmsSurfaceHandle nvKmsHandle; + NvU32 rmHandle; + + Nv3dBlockLinearLog2GobsPerBlock gobsPerBlock; + + const NVSurfaceEvoRec *pSurfaceEvo; + +} NVHsSurfaceRec; + +typedef struct _NVHsDeviceEvoRec { + + NVDevEvoRec *pDevEvo; + + NvU32 gpuVASpace; + + struct { + Nv3dDeviceRec device; + } nv3d; + + NVHsNotifiersRec notifiers; + +} NVHsDeviceEvoRec; + +enum NVHsChannelTexInfoEnum { + NVKMS_HEADSURFACE_TEXINFO_SRC = 0, + /* XXX NVKMS HEADSURFACE TODO: enable all the below */ + NVKMS_HEADSURFACE_TEXINFO_CURSOR = 1, + NVKMS_HEADSURFACE_TEXINFO_BLEND = 2, + NVKMS_HEADSURFACE_TEXINFO_OFFSET = 3, + NVKMS_HEADSURFACE_TEXINFO_OVERLAY = 4, + /* NVKMS_HEADSURFACE_TEXINFO_LUT = 5, */ + NVKMS_HEADSURFACE_TEXINFO_NUM, +}; + +typedef struct _NVHsChannelStatisticsOneEyeRec { + /* Running total of the number of frames rendered by headSurface. */ + NvU64 nFrames; + + /* Running total of the GPU time spent rendering, in nanoseconds. */ + NvU64 gpuTimeSpent; + + /* We compute the FPS for 5 second periods. */ + struct { + /* + * Running total of the number of frames rendered by headSurface; reset + * every 5 seconds. + */ + NvU64 nFrames; + /* + * The time, in nanoseconds, when this FPS period started, so we know + * when the 5 second period is done. + */ + NvU64 startTime; + /* + * Most recently computed FPS for the last 5 second period. + */ + NvU64 framesPerMs; + } fps; +} NVHsChannelStatisticsOneEyeRec; + +typedef struct _NVHsChannelFlipQueueEntry { + NVListRec flipQueueEntry; + NVFlipChannelEvoHwState hwState; +} NVHsChannelFlipQueueEntry; + +typedef struct _NVHsChannelEvoRec { + + NVDispEvoRec *pDispEvo; + + NvU32 apiHead; + + struct { + NvPushChannelRec channel; + NvU32 handlePool[NV_PUSH_CHANNEL_HANDLE_POOL_NUM]; + } nvPush; + + struct { + NvU32 handle; + Nv3dChannelRec channel; + Nv3dRenderTexInfo texInfo[NVKMS_HEADSURFACE_TEXINFO_NUM]; + } nv3d; + + struct { + NvU32 handle; + } nv2d; + + /* + * NvKmsFlipParams is too large to declare on the stack. We preallocate it + * here so that we don't have to allocate and free it on every headSurface + * flip. + */ + struct NvKmsFlipParams scratchParams; + + /* + * The index into NVDevEvoRec::apiHeadSurfaceAllDisps[apiHead]::surface[] to use + * for the next frame of headSurface. + */ + NvU8 nextIndex; + + /* + * When neededForSwapGroup is true, frames of headSurface are rendered to + * alternating offsets within double-sized headSurface surfaces. nextOffset + * is either 0 or 1, to select the offset of the next headSurface frame. + */ + NvU8 nextOffset; + + /* + * HeadSurface flips are semaphore interlocked with headSurface rendering. + * We need to use a different semaphore offset for subsequent flips. + * frameSemaphoreIndex is used to alternate between + * NVKMS_HEAD_SURFACE_MAX_FRAME_SEMAPHORES offsets. + */ + NvU8 frameSemaphoreIndex; + + NVHsChannelConfig config; + + NVVBlankCallbackPtr vBlankCallback; + + /* + * NVHsChannelEvoRec keeps a list of flip queue entries, and the "current" + * entry. NVHsChannelFlipQueueEntry is a single entry in the flip queue. + * + * Each entry describes a validated flip request. When NVKMS is called to + * build the next frame of headSurface, it inspects if the next entry in the + * queue is ready to flip (e.g., any semaphore acquires have been + * satisfied). If the next flip queue entry is ready, we use it to replace + * the current entry. Otherwise, we continue to use the existing current + * entry. + * + * Surfaces within an NVHsChannelFlipQueueEntry have their reference counts: + * + * - incremented when the NVHsChannelFlipQueueEntry is added to the flip + * queue. + * + * - decremented when the NVHsChannelFlipQueueEntry is removed from current + * (i.e., when we do the equivalent of "flip away"). + * + * To simulate EVO/NVDisplay semaphore behavior, if an + * NVHsChannelFlipQueueEntry specifies a semaphore: + * + * - We wait for the semaphore's acquire value to be reached before + * promoting the entry from the flip queue to current. + * + * - We write the semaphore's release value when the + * NVHsChannelFlipQueueEntry is removed from current (i.e., when we do the + * equivalent of "flip away"). + */ + + struct { + NVFlipChannelEvoHwState current; + NVListRec queue; + } flipQueue[NVKMS_MAX_LAYERS_PER_HEAD]; + + /* + * This cached main layer surface needed when the main layer transitioning + * out of headSurface due to exiting a swapgroup. I.e. in this path: + * nvHsConfigStop() => HsConfigRestoreMainLayerSurface() + */ + struct { + NVSurfaceEvoPtr pSurfaceEvo[NVKMS_MAX_EYES]; + } flipQueueMainLayerState; + + NvU64 lastCallbackUSec; + + /* + * For NVKMS headsurface swap groups, at some point after the flip has been + * issued, NVKMS needs to check the notifier associated with that flip to + * see if the flip has been completed and release the deferred request + * fifo entry associated with that flip. This bool reflects whether that + * check is done during the headsurface vblank interrupt callback or later + * during the RG line 1 interrupt callback. + */ + NvBool usingRgIntrForSwapGroups; + + /* + * Handle to the RG line interrupt callback object. This is needed to + * enabled and disable the RG interrupt callback. + */ + NvU32 rgIntrCallbackObjectHandle; + +#if NVKMS_PROCFS_ENABLE + + /* + * We track statistics differently for SwapGroup and non-SwapGroup + * headSurface; abstract the grouping into "slots". For non-SwapGroup there + * is only one rendered frame (one "slot"). For SwapGroup, there are three + * different rendered frames (so three "slots"). + */ +#define NVKMS_HEADSURFACE_STATS_MAX_SLOTS 3 + +#define NVKMS_HEADSURFACE_STATS_SEMAPHORE_BEFORE 0 +#define NVKMS_HEADSURFACE_STATS_SEMAPHORE_AFTER 1 + + /* + * One semaphore before the frame, and one semaphore after the frame. + */ +#define NVKMS_HEAD_SURFACE_STATS_SEMAPHORE_STAGE_COUNT 2 + + /* + * We need semaphores for each stereo eye for each "slot". + */ +#define NVKMS_HEADSURFACE_STATS_MAX_SEMAPHORES \ + (NVKMS_HEAD_SURFACE_STATS_SEMAPHORE_STAGE_COUNT * \ + NVKMS_MAX_EYES * \ + NVKMS_HEADSURFACE_STATS_MAX_SLOTS) + + struct { + + NVHsChannelStatisticsOneEyeRec + perEye[NVKMS_MAX_EYES][NVKMS_HEADSURFACE_STATS_MAX_SLOTS]; + + /* How often we were called back before the previous frame was done. */ + NvU64 nPreviousFrameNotDone; + + /* How often we did not update HS backbuffer with non-sg content. */ + NvU64 nOmittedNonSgHsUpdates; + + /* How often did we have fullscreen swapgroup, and didn't. */ + NvU64 nFullscreenSgFrames; + NvU64 nNonFullscreenSgFrames; + + /* + * Statistics on which Display Memory Interface (DMI) scanline we are on + * when headSurface is called. + * + * pHistogram is a dynamically allocated array of counts. The array has + * vVisible + 1 elements (the +1 is because the hardware-reported + * scanline values are in the inclusive range [0,vVisible]). Each + * element contains how many times we've been called back while on that + * scanline. + * + * When in the blanking region, there isn't a DMI scanline. We + * increment n{,Not}InBlankingPeriod to keep track of how often we are + * called back while in the blanking region. + */ + struct { + NvU64 *pHistogram; /* array with vVisible elements */ + NvU16 vVisible; + NvU64 nInBlankingPeriod; + NvU64 nNotInBlankingPeriod; + } scanLine; + + } statistics; +#else +#define NVKMS_HEADSURFACE_STATS_MAX_SEMAPHORES 0 +#endif /* NVKMS_PROCFS_ENABLE */ + + /* + * We need one semaphore for the non-stall interrupt following rendering to + * the next viewport offset with swapgroups enabled. + */ +#define NVKMS_HEADSURFACE_VIEWPORT_OFFSET_SEMAPHORE_INDEX \ + NVKMS_HEADSURFACE_STATS_MAX_SEMAPHORES + +#define NVKMS_HEADSURFACE_MAX_SEMAPHORES \ + (NVKMS_HEADSURFACE_VIEWPORT_OFFSET_SEMAPHORE_INDEX + 1) + + /* + * Whether this channel has kicked off rendering to a new viewport offset + * for non-swapgroup content updates, but hasn't yet kicked off the + * viewport flip to the new offset. Used to prevent rendering a new + * frame if rendering the previous frame took longer than a full frame of + * scanout. + */ + NvBool viewportFlipPending; + + /* + * Recorded timestamp of the last headsurface flip. Used for deciding if + * certain blits to the headsurface can be omitted. + */ + NvU64 lastHsClientFlipTimeUs; + + /* + * If this channel has kicked off a real flip while swapgroups were active, + * mark this channel as using real flips instead of blits for swapgroups, + * don't fast forward through headsurface flips (since every flip needs to + * be kicked off with every swapgroup ready event), and skip the part of + * the RG interrupt that would update non-swapgroup content. + */ + NvBool swapGroupFlipping; + +} NVHsChannelEvoRec; + +static inline NvU8 Hs3dStatisticsGetSlot( + const NVHsChannelEvoRec *pHsChannel, + const NvHsNextFrameRequestType requestType, + const NvU8 dstBufferIndex, + const NvBool honorSwapGroupClipList) +{ + if (pHsChannel->config.neededForSwapGroup) { + switch (requestType) { + case NV_HS_NEXT_FRAME_REQUEST_TYPE_FIRST_FRAME: + /* + * SwapGroup FIRST_FRAME will render to pHsChannel->nextIndex with + * honorSwapGroupClipList==false. + */ + nvAssert(dstBufferIndex < 2); + return dstBufferIndex; + case NV_HS_NEXT_FRAME_REQUEST_TYPE_VBLANK: + /* + * SwapGroup VBLANK fully populates the nextIndex buffer + * (honorSwapGroupClipList==false), and only populates the + * non-swapgroup regions of the current index. + */ + return honorSwapGroupClipList ? 0 : 1; + case NV_HS_NEXT_FRAME_REQUEST_TYPE_SWAP_GROUP_READY: + return 2; + } + } + + return 0; /* non-SwapGroup always only uses slot 0 */ +} + +/*! + * Get the offset, in words, of the frame semaphore within NVHsNotifiersOneSdRec + * that corresponds to (head, frameSemaphoreIndex). + */ +static inline NvU16 HsGetFrameSemaphoreOffsetInWords( + const NVHsChannelEvoRec *pHsChannel) +{ + const NvU16 semBase = + offsetof(NVHsNotifiersOneSdRec, semaphore[pHsChannel->apiHead]); + const NvU16 semOffset = sizeof(NvGpuSemaphore) * + pHsChannel->frameSemaphoreIndex; + + const NvU16 offsetInBytes = semBase + semOffset; + + /* + * NVHsNotifiersOneSdRec::semaphore should be word-aligned, and + * sizeof(NvGpuSemaphore) is a multiple of words, so the offset to any + * NvGpuSemaphore within the array should be word-aligned. + */ + nvAssert((offsetInBytes % 4) == 0); + + return offsetInBytes / 4; +} + +static inline void HsIncrementFrameSemaphoreIndex( + NVHsChannelEvoRec *pHsChannel) +{ + pHsChannel->frameSemaphoreIndex++; + pHsChannel->frameSemaphoreIndex %= NVKMS_HEAD_SURFACE_MAX_FRAME_SEMAPHORES; +} + +static inline NvU8 HsGetPreviousOffset( + const NVHsChannelEvoRec *pHsChannel) +{ + nvAssert(pHsChannel->config.neededForSwapGroup); + + nvAssert(pHsChannel->config.surfaceSize.height == + (pHsChannel->config.frameSize.height * 2)); + + return A_minus_b_with_wrap_U8(pHsChannel->nextOffset, 1, + NVKMS_HEAD_SURFACE_MAX_BUFFERS); +} + +static inline void HsIncrementNextOffset( + const NVHsDeviceEvoRec *pHsDevice, + NVHsChannelEvoRec *pHsChannel) +{ + nvAssert(pHsChannel->config.neededForSwapGroup); + + nvAssert(pHsChannel->config.surfaceSize.height == + (pHsChannel->config.frameSize.height * 2)); + + pHsChannel->nextOffset++; + pHsChannel->nextOffset %= 2; +} + +static inline void HsIncrementNextIndex( + const NVHsDeviceEvoRec *pHsDevice, + NVHsChannelEvoRec *pHsChannel) +{ + const NVDevEvoRec *pDevEvo = pHsDevice->pDevEvo; + const NvU32 surfaceCount = + pDevEvo->apiHeadSurfaceAllDisps[pHsChannel->apiHead].surfaceCount; + + nvAssert(surfaceCount > 0); + + pHsChannel->nextIndex++; + pHsChannel->nextIndex %= surfaceCount; +} + +static inline void HsChangeSurfaceFlipRefCount( + NVSurfaceEvoPtr pSurfaceEvo, + NvBool increase) +{ + if (pSurfaceEvo != NULL) { + if (increase) { + nvEvoIncrementSurfaceRefCnts(pSurfaceEvo); + } else { + nvEvoDecrementSurfaceRefCnts(pSurfaceEvo); + } + } +} + +/*! + * Get the last NVFlipChannelEvoHwState entry in the pHsChannel's flip queue for + * the specified layer. + * + * If the flip queue is empty, return the 'current' entry. Otherwise, return + * the most recently queued entry. + * + * This function cannot fail. + */ +static inline const NVFlipChannelEvoHwState *HsGetLastFlipQueueEntry( + const NVHsChannelEvoRec *pHsChannel, + const NvU8 layer) +{ + const NVListRec *pFlipQueue = &pHsChannel->flipQueue[layer].queue; + const NVHsChannelFlipQueueEntry *pEntry; + + /* + * XXX NVKMS HEADSURFACE TODO: use nvListIsEmpty() once bugfix_main is + * updated to make nvListIsEmpty()'s argument const; see changelist + * 23614050. + * + * if (nvListIsEmpty(pFlipQueue)) { + */ + if (pFlipQueue->next == pFlipQueue) { + return &pHsChannel->flipQueue[layer].current; + } + + pEntry = nvListLastEntry(pFlipQueue, + NVHsChannelFlipQueueEntry, + flipQueueEntry); + + return &pEntry->hwState; +} + +#endif /* __NVKMS_HEADSURFACE_PRIV_H__ */ diff --git a/src/nvidia-modeset/include/nvkms-headsurface-swapgroup.h b/src/nvidia-modeset/include/nvkms-headsurface-swapgroup.h new file mode 100644 index 000000000..d86c7e3f5 --- /dev/null +++ b/src/nvidia-modeset/include/nvkms-headsurface-swapgroup.h @@ -0,0 +1,89 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVKMS_HEADSURFACE_SWAPGROUP_H__ +#define __NVKMS_HEADSURFACE_SWAPGROUP_H__ + +#include "nvkms-types.h" + +NvBool nvHsSwapGroupIsHeadSurfaceNeeded( + const NVDispEvoRec *pDispEvo, + const NvU32 apiHead); + +void nvHsSwapGroupRelease( + NVDevEvoPtr pDevEvo, + NVSwapGroupRec *pSwapGroup); + +NVSwapGroupRec* nvHsAllocSwapGroup( + NVDevEvoPtr pDevEvo, + const struct NvKmsAllocSwapGroupRequest *pRequest); + +NVSwapGroupRec *nvHsGetSwapGroupStruct( + const NVEvoApiHandlesRec *pEvoApiHandles, + NvKmsSwapGroupHandle handle); + +NVSwapGroupRec *nvHsGetSwapGroup( + const NVEvoApiHandlesRec *pEvoApiHandles, + NvKmsSwapGroupHandle handle); + +void nvHsDecrementSwapGroupRefCnt(NVSwapGroupPtr pSwapGroup); + +NvBool nvHsIncrementSwapGroupRefCnt(NVSwapGroupPtr pSwapGroup); + +void nvHsFreeSwapGroup( + NVDevEvoPtr pDevEvo, + NVSwapGroupRec *pSwapGroup); + +typedef struct _NVHsJoinSwapGroupWorkArea { + NVDevEvoPtr pDevEvo; + NVSwapGroupRec *pSwapGroup; + NVDeferredRequestFifoRec *pDeferredRequestFifo; + struct NvKmsPerOpen *pEventOpenFd; + NvBool enabledHeadSurface; +} NVHsJoinSwapGroupWorkArea; + +NvBool nvHsJoinSwapGroup( + NVHsJoinSwapGroupWorkArea *joinSwapGroupWorkArea, + NvU32 numHandles, + NvBool pendingJoin); + +void nvHsLeaveSwapGroup( + NVDevEvoPtr pDevEvo, + NVDeferredRequestFifoRec *pDeferredRequestFifo, + NvBool teardown); + +NvBool nvHsSetSwapGroupClipList( + NVDevEvoPtr pDevEvo, + NVSwapGroupRec *pSwapGroup, + const NvU16 nClips, + struct NvKmsRect *pClipList); + +void nvHsSwapGroupReady( + NVDevEvoPtr pDevEvo, + NVDeferredRequestFifoRec *pDeferredRequestFifo, + const NvU32 request); + +NvBool nvHsSwapGroupGetPerEyeStereo( + const NVSwapGroupRec *pSwapGroup); + +#endif /* __NVKMS_HEADSURFACE_SWAPGROUP_H__ */ diff --git a/src/nvidia-modeset/include/nvkms-headsurface.h b/src/nvidia-modeset/include/nvkms-headsurface.h new file mode 100644 index 000000000..0e7a05b75 --- /dev/null +++ b/src/nvidia-modeset/include/nvkms-headsurface.h @@ -0,0 +1,126 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVKMS_HEADSURFACE_H__ +#define __NVKMS_HEADSURFACE_H__ + +#include "nvkms-types.h" + +NvU64 nvHsMapSurfaceToDevice( + const NVDevEvoRec *pDevEvo, + const NvU32 rmHandle, + const NvU64 sizeInBytes, + enum NvHsMapPermissions hsMapPermissions); + +void nvHsUnmapSurfaceFromDevice( + const NVDevEvoRec *pDevEvo, + const NvU32 rmHandle, + const NvU64 gpuAddress); + +NVHsSurfacePtr nvHsAllocSurface( + NVDevEvoRec *pDevEvo, + const NvBool requireCtxDma, + const enum NvKmsSurfaceMemoryFormat format, + const NvU32 widthInPixels, + const NvU32 heightInPixels); + +void nvHsFreeSurface( + NVDevEvoRec *pDevEvo, + NVHsSurfacePtr pHsSurface); + +NvBool nvHsAllocDevice( + NVDevEvoRec *pDevEvo, + const struct NvKmsAllocDeviceRequest *pRequest); + +void nvHsFreeDevice(NVDevEvoRec *pDevEvo); + +NVHsChannelEvoPtr nvHsAllocChannel(NVDispEvoRec *pDispEvo, NvU32 apiHead); + +void nvHsFreeChannel(NVHsChannelEvoPtr pHsChannel); + +void nvHsPushFlipQueueEntry( + NVHsChannelEvoPtr pHsChannel, + const NvU8 layer, + const NVFlipChannelEvoHwState *pHwState); + +void nvHsDrainFlipQueue( + NVHsChannelEvoPtr pHsChannel); + +NvBool nvHsIdleFlipQueue( + NVHsChannelEvoPtr pHsChannel, + NvBool force); + +void nvHsInitNotifiers( + NVHsDeviceEvoPtr pHsDevice, + NVHsChannelEvoPtr pHsChannel); + +void nvHsFlip( + NVHsDeviceEvoPtr pHsDevice, + NVHsChannelEvoPtr pHsChannel, + const NvU8 eyeMask, + const NvBool perEyeStereoFlip, + const NvU8 currentIndex, + const NVHsStateOneHeadAllDisps *pHsOneHeadAllDisps, + const NvBool isFirstFlip, + const NvBool allowFlipLock); + +typedef enum { + NV_HS_NEXT_FRAME_REQUEST_TYPE_FIRST_FRAME, + NV_HS_NEXT_FRAME_REQUEST_TYPE_VBLANK, + NV_HS_NEXT_FRAME_REQUEST_TYPE_SWAP_GROUP_READY, +} NvHsNextFrameRequestType; + +void nvHsNextFrame( + NVHsDeviceEvoPtr pHsDevice, + NVHsChannelEvoPtr pHsChannel, + const NvHsNextFrameRequestType requestType); + +void nvHsAddVBlankCallback(NVHsChannelEvoPtr pHsChannel); + +void nvHsRemoveVBlankCallback(NVHsChannelEvoPtr pHsChannel); + +void nvHsAddRgLine1Callback(NVHsChannelEvoPtr pHsChannel); + +void nvHsRemoveRgLine1Callback(NVHsChannelEvoPtr pHsChannel); + +void nvHsAllocStatistics( + NVHsChannelEvoPtr pHsChannel); + +void nvHsFreeStatistics( + NVHsChannelEvoPtr pHsChannel); + +void nvHsProcessPendingViewportFlips(NVDevEvoPtr pDevEvo); + +NVSurfaceEvoRec *nvHsGetNvKmsSurface(const NVDevEvoRec *pDevEvo, + NvKmsSurfaceHandle surfaceHandle, + const NvBool requireCtxDma); + +#if NVKMS_PROCFS_ENABLE +void nvHsProcFs( + NVEvoInfoStringRec *pInfoString, + NVDevEvoRec *pDevEvo, + NvU32 dispIndex, + NvU32 head); +#endif + +#endif /* __NVKMS_HEADSURFACE_H__ */ diff --git a/src/nvidia-modeset/include/nvkms-lut.h b/src/nvidia-modeset/include/nvkms-lut.h index a9462ce4b..5500e0127 100644 --- a/src/nvidia-modeset/include/nvkms-lut.h +++ b/src/nvidia-modeset/include/nvkms-lut.h @@ -30,6 +30,16 @@ extern "C" { #include "nvkms-types.h" +NvBool nvSetTmoLutSurfacesEvo(NVDevEvoPtr pDevEvo, + NVFlipEvoHwState *pFlipState, + NvU32 head); +void nvRefTmoLutSurfacesEvo(NVDevEvoPtr pDevEvo, + NVFlipEvoHwState *pFlipState, + NvU32 head); +void nvUnrefTmoLutSurfacesEvo(NVDevEvoPtr pDevEvo, + NVFlipEvoHwState *pFlipState, + NvU32 head); + NvBool nvAllocLutSurfacesEvo(NVDevEvoPtr pDevEvo); void nvFreeLutSurfacesEvo(NVDevEvoPtr pDevEvo); diff --git a/src/nvidia-modeset/include/nvkms-modepool.h b/src/nvidia-modeset/include/nvkms-modepool.h index 3ac3e3e9e..f3ce047f3 100644 --- a/src/nvidia-modeset/include/nvkms-modepool.h +++ b/src/nvidia-modeset/include/nvkms-modepool.h @@ -49,7 +49,8 @@ NvBool nvValidateModeForModeset(NVDpyEvoRec *pDpyEvo, const struct NvKmsMode *pKmsMode, const struct NvKmsSize *pViewPortSizeIn, const struct NvKmsRect *pViewPortOut, - NVHwModeTimingsEvo *pTimingsEvo); + NVHwModeTimingsEvo *pTimingsEvo, + NVT_VIDEO_INFOFRAME_CTRL *pInfoFrameCtrl); const NVT_TIMING *nvFindEdidNVT_TIMING( const NVDpyEvoRec *pDpyEvo, diff --git a/src/nvidia-modeset/include/nvkms-modeset-types.h b/src/nvidia-modeset/include/nvkms-modeset-types.h index 5054c654b..cdee15e29 100644 --- a/src/nvidia-modeset/include/nvkms-modeset-types.h +++ b/src/nvidia-modeset/include/nvkms-modeset-types.h @@ -44,6 +44,8 @@ typedef struct { NvU32 vrrOverrideMinRefreshRate; NVDPLibModesetStatePtr pDpLibModesetState; NVDispHeadAudioStateEvoRec audio; + NVDispHeadInfoFrameStateEvoRec infoFrame; + enum NvKmsOutputTf tf; } NVProposedModeSetHwStateOneHead; typedef struct { diff --git a/src/nvidia-modeset/include/nvkms-modeset-workarea.h b/src/nvidia-modeset/include/nvkms-modeset-workarea.h index 9890b8725..da492dd33 100644 --- a/src/nvidia-modeset/include/nvkms-modeset-workarea.h +++ b/src/nvidia-modeset/include/nvkms-modeset-workarea.h @@ -24,6 +24,8 @@ #ifndef __NVKMS_MODESET_WORKAREA_H__ #define __NVKMS_MODESET_WORKAREA_H__ +#include "nvkms-headsurface-config.h" + typedef struct { struct { struct { @@ -38,6 +40,7 @@ typedef struct { NvU32 assignedSorMask; } sd[NVKMS_MAX_SUBDEVICES]; + NVHsConfig hsConfig; NVEvoUpdateState earlyUpdateState; NVEvoModesetUpdateState modesetUpdateState; diff --git a/src/nvidia-modeset/include/nvkms-modeset.h b/src/nvidia-modeset/include/nvkms-modeset.h index 9540058a3..f3abffbb5 100644 --- a/src/nvidia-modeset/include/nvkms-modeset.h +++ b/src/nvidia-modeset/include/nvkms-modeset.h @@ -25,13 +25,24 @@ #define __NVKMS_MODESET_H__ #include "nvkms-types.h" +#include "class/cl0092_callback.h" #ifdef __cplusplus extern "C" { #endif +NvBool +nvGetHwModeTimings(const NVDispEvoRec *pDispEvo, + const struct NvKmsSetModeOneHeadRequest *pRequestHead, + NVHwModeTimingsEvo *pTimings, + NVT_VIDEO_INFOFRAME_CTRL *pInfoFrameCtrl); + +NvBool nvGetAllowHeadSurfaceInNvKms(const NVDevEvoRec *pDevEvo, + const struct NvKmsPerOpenDev *pOpenDev, + const struct NvKmsSetModeRequest *pRequest); + NvBool nvSetDispModeEvo(NVDevEvoPtr pDevEvo, - const struct NvKmsPerOpenDev *pOpenDev, + struct NvKmsPerOpenDev *pOpenDev, const struct NvKmsSetModeRequest *pRequest, struct NvKmsSetModeReply *pReply, NvBool bypassComposition, @@ -51,6 +62,21 @@ void nvUnregisterVBlankCallback(NVDispEvoPtr pDispEvo, NvU32 head, NVVBlankCallbackPtr pCallback); +NVVBlankCallbackPtr +nvApiHeadRegisterVBlankCallback(NVDispEvoPtr pDispEvo, + const NvU32 apiHead, + NVVBlankCallbackProc pCallback, + void *pUserData); + +void nvApiHeadUnregisterVBlankCallback(NVDispEvoPtr pDispEvo, + const NvU32 apiHead, + NVVBlankCallbackPtr pCallback); + +NvU32 +nvApiHeadAddRgLine1Callback(const NVDispEvoRec *pDispEvo, + const NvU32 apiHead, + NV0092_REGISTER_RG_LINE_CALLBACK_FN pCallback); + #ifdef __cplusplus }; #endif diff --git a/src/nvidia-modeset/include/nvkms-prealloc-types.h b/src/nvidia-modeset/include/nvkms-prealloc-types.h index 947a2a55d..0756a440e 100644 --- a/src/nvidia-modeset/include/nvkms-prealloc-types.h +++ b/src/nvidia-modeset/include/nvkms-prealloc-types.h @@ -33,6 +33,8 @@ enum NVPreallocType { PREALLOC_TYPE_MODE_SET_WORK_AREA, PREALLOC_TYPE_FLIP_WORK_AREA, PREALLOC_TYPE_PROPOSED_MODESET_HW_STATE, + PREALLOC_TYPE_HS_PATCHED_MODESET_REQUEST, + PREALLOC_TYPE_HS_INIT_CONFIG_HW_TIMINGS, PREALLOC_TYPE_VALIDATE_PROPOSED_MODESET_HW_STATE, PREALLOC_TYPE_VALIDATE_MODE_HW_MODE_TIMINGS, PREALLOC_TYPE_MAX diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080common.h b/src/nvidia-modeset/include/nvkms-push.h similarity index 80% rename from src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080common.h rename to src/nvidia-modeset/include/nvkms-push.h index 4857c3eb7..8ad6d4a89 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080common.h +++ b/src/nvidia-modeset/include/nvkms-push.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2001-2004 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -20,15 +20,12 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ +#ifndef __NVKMS_PUSH_H__ +#define __NVKMS_PUSH_H__ -#pragma once +#include "nvkms-types.h" -// -// This file was generated with FINN, an NVIDIA coding tool. -// Source file: ctrl/ctrl2080/ctrl2080common.finn -// +NvBool nvAllocNvPushDevice(NVDevEvoPtr pDevEvo); +void nvFreeNvPushDevice(NVDevEvoPtr pDevEvo); - - - -#define NV2080_CTRL_CMD_MAX_HEADS 2 +#endif diff --git a/src/nvidia-modeset/include/nvkms-rm.h b/src/nvidia-modeset/include/nvkms-rm.h index a0e2e901c..3755d60e6 100644 --- a/src/nvidia-modeset/include/nvkms-rm.h +++ b/src/nvidia-modeset/include/nvkms-rm.h @@ -110,6 +110,8 @@ NvBool nvRmEvoMapVideoMemory(NVDevEvoPtr pDevEvo, NvBool nvRmAllocDeviceEvo(NVDevEvoPtr pDevEvo, const struct NvKmsAllocDeviceRequest *pRequest); void nvRmFreeDeviceEvo(NVDevEvoPtr pDevEvo); +NvBool nvRmRegisterDIFREventHandler(NVDevEvoPtr pDevEvo); +void nvRmUnregisterDIFREventHandler(NVDevEvoPtr pDevEvo); NvBool nvRmIsPossibleToActivateDpyIdList(NVDispEvoPtr pDispEvo, const NVDpyIdList dpyIdList); NvBool nvRmVTSwitch(NVDevEvoPtr pDevEvo, NvU32 cmd); diff --git a/src/nvidia-modeset/include/nvkms-stereo.h b/src/nvidia-modeset/include/nvkms-stereo.h new file mode 100644 index 000000000..245c2b89c --- /dev/null +++ b/src/nvidia-modeset/include/nvkms-stereo.h @@ -0,0 +1,43 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVKMS_STEREO_H__ +#define __NVKMS_STEREO_H__ + +#include "nvkms-types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +NvBool nvSetStereo(const NVDispEvoRec *pDispEvo, + const NvU32 apiHead, + NvBool enable); + +NvBool nvGetStereo(const NVDispEvoRec *pDispEvo, const NvU32 apiHead); + +#ifdef __cplusplus +}; +#endif + +#endif /* __NVKMS_STEREO_H__ */ diff --git a/src/nvidia-modeset/include/nvkms-surface.h b/src/nvidia-modeset/include/nvkms-surface.h index 89dd4e5e7..0a05242cd 100644 --- a/src/nvidia-modeset/include/nvkms-surface.h +++ b/src/nvidia-modeset/include/nvkms-surface.h @@ -55,7 +55,8 @@ NVSurfaceEvoPtr nvEvoGetSurfaceFromHandle( const NVDevEvoRec *pDevEvo, const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, const NvKmsSurfaceHandle surfaceHandle, - const NVEvoChannelMask channelMask); + const NvBool isUsedByCursorChannel, + const NvBool isUsedByLayerChannel); NVSurfaceEvoPtr nvEvoGetSurfaceFromHandleNoCtxDmaOk( const NVDevEvoRec *pDevEvo, diff --git a/src/nvidia-modeset/include/nvkms-types.h b/src/nvidia-modeset/include/nvkms-types.h index 1d8c6c468..7ab209e4d 100644 --- a/src/nvidia-modeset/include/nvkms-types.h +++ b/src/nvidia-modeset/include/nvkms-types.h @@ -53,6 +53,8 @@ extern "C" { #include "nvmisc.h" +#include "nvidia-push-init.h" + #include "timing/nvtiming.h" #include "timing/nvt_dsc_pps.h" #include "hdmipacket/nvhdmi_frlInterface.h" // HDMI_{SRC,SINK}_CAPS @@ -100,6 +102,9 @@ extern "C" { #define NVKMS_BLOCK_LINEAR_LOG_GOB_WIDTH 6U /* 64 bytes (2^6) */ #define NVKMS_BLOCK_LINEAR_GOB_WIDTH ((NvU32)1 << NVKMS_BLOCK_LINEAR_LOG_GOB_WIDTH) +#define NVKMS_BLOCK_LINEAR_LOG_GOB_HEIGHT 3U /* 8 rows (2^3) */ +#define NVKMS_BLOCK_LINEAR_GOB_HEIGHT ((NvU32)1 << NVKMS_BLOCK_LINEAR_LOG_GOB_HEIGHT) + #define NV_INVALID_OR 0xFFFFFFFF #define NVKMS_RM_HEAP_ID 0xDCBA @@ -120,6 +125,7 @@ extern "C" { typedef struct _NVEvoApiHandlesRec *NVEvoApiHandlesPtr; typedef struct _NVEvoSubDeviceRec *NVSubDeviceEvoPtr; typedef struct _NVEvoDevRec *NVDevEvoPtr; +typedef struct _NVDIFRStateEvoRec *NVDIFRStateEvoPtr; typedef struct _NVDmaBufferEvoRec *NVDmaBufferEvoPtr; typedef struct _NVEvoChannel *NVEvoChannelPtr; typedef struct _NVEvoHeadControl *NVEvoHeadControlPtr; @@ -277,6 +283,7 @@ typedef struct { NvBool csc0MatricesPresent; NvBool cscLUTsPresent; NvBool csc1MatricesPresent; + NvBool tmoPresent; NVEvoScalerCaps scalerCaps; } NVEvoWindowCaps; #define NV_EVO_NUM_WINDOW_CAPS 32 @@ -474,6 +481,12 @@ typedef struct _NVEvoChannel { NVEvoChannelCaps caps; NVEvoSyncpt postSyncpt; + + struct { + NvBool enabled; + NvU32 srcMaxLum; + NvU32 targetMaxLums[NVKMS_MAX_SUBDEVICES]; + } tmoParams; } NVEvoChannel; typedef enum { @@ -551,8 +564,10 @@ typedef struct { NvU32 releaseValue; } semaphores; struct { - NvU32 preCtxDma; + NvBool isPreSyncptSpecified; + NvU32 preSyncpt; NvU32 preValue; + NvU32 postCtxDma; NvU32 postValue; } syncpts; @@ -600,6 +615,33 @@ typedef struct { struct NvKmsRRParams rrParams; struct NvKmsCompositionParams composition; + + NVFlipLutHwState tmoLut; + struct { + struct NvKmsHDRStaticMetadata val; + NvBool enabled; + } hdrStaticMetadata; + + enum NvKmsInputColorSpace colorspace; + + struct { + NvBool specified; + + /* + * Maximum vertical downscale factor (scaled by 1024) + * + * For example, if the downscale factor is 1.5, then maxVDownscaleFactor + * would be 1.5 x 1024 = 1536. + */ + NvU16 vertical; + + /* + * Maximum horizontal downscale factor (scaled by 1024) + * + * See the example above for vertical. + */ + NvU16 horizontal; + } maxDownscaleFactors; } NVFlipChannelEvoHwState; typedef struct { @@ -608,16 +650,29 @@ typedef struct { NVFlipChannelEvoHwState layer[NVKMS_MAX_LAYERS_PER_HEAD]; struct NvKmsUsageBounds usage; NvBool disableMidFrameAndDWCFWatermark; + enum NvKmsOutputTf tf; + + NvBool skipLayerPendingFlips[NVKMS_MAX_LAYERS_PER_HEAD]; + struct { - NvBool viewPortPointIn : 1; - NvBool cursorSurface : 1; - NvBool cursorPosition : 1; + NvBool viewPortPointIn : 1; + NvBool cursorSurface : 1; + NvBool cursorPosition : 1; + NvBool tf : 1; + NvBool hdrStaticMetadata : 1; NvBool layerPosition[NVKMS_MAX_LAYERS_PER_HEAD]; + NvBool layerSyncObjects[NVKMS_MAX_LAYERS_PER_HEAD]; NvBool layer[NVKMS_MAX_LAYERS_PER_HEAD]; } dirty; } NVFlipEvoHwState; +enum NvKmsHDROutputState { + NVKMS_HDR_OUTPUT_STATE_SDR = 0, + NVKMS_HDR_OUTPUT_STATE_HDR = 1, + NVKMS_HDR_OUTPUT_STATE_TRANSITIONING_TO_SDR = 2, +}; + /*! * State requested through the NVKMS API. This may differ from * the current hardware state (e.g., if the head has been @@ -770,7 +825,6 @@ typedef struct { typedef struct { NvBool supportsDP13 :1; - NvBool supportsInbandStereoSignaling :1; NvBool supportsHDMI20 :1; NvBool inputLutAppliesToBase :1; NvU8 validNIsoFormatMask; @@ -826,6 +880,12 @@ typedef struct _NVEvoSubDeviceRec { } NVEvoSubDeviceRec; +enum NvKmsLUTState { + NvKmsLUTStateUninitialized = 0, + NvKmsLUTStateIdentity = 1, + NvKmsLUTStatePQ = 2, +}; + /* Device-specific EVO state (subdevice- and channel-independent) */ typedef struct _NVEvoDevRec { @@ -842,6 +902,11 @@ typedef struct _NVEvoDevRec { NvU32 deviceHandle; struct NvKmsPerOpenDev *pNvKmsOpenDev; + struct { + NvPushDeviceRec device; + NvU32 handlePool[NV_PUSH_DEVICE_HANDLE_POOL_NUM]; + } nvPush; + /* SLI Info */ struct { NvBool mosaic; @@ -861,19 +926,18 @@ typedef struct _NVEvoDevRec { NvU32 displayHandle; + /*! + * lastModesettingClient points to the pOpenDev of the client that + * performed the last modeset. + */ + const struct NvKmsPerOpenDev *lastModesettingClient; + /*! * modesetOwner points to the pOpenDev of the client that called * NVKMS_IOCTL_GRAB_OWNERSHIP. */ const struct NvKmsPerOpenDev *modesetOwner; - /*! - * The first modeset after a modeset ownership transition should not inherit - * state from the previous modeset that we don't want inherited: LUTs or - * heads not specified in the new modeset request. - */ - NvBool modesetOwnerChanged; - /*! * NVEvoDevRec::numSubDevices is the number of GPUs in the SLI * device. This is the number of NVEvoSubDevPtrs in @@ -928,6 +992,7 @@ typedef struct _NVEvoDevRec { NVEvoCapsRec caps; NVEvoCoreChannelDmaRec coreChannelDma; + NvU32 nvkmsGpuVASpace; NvBool mobile : 1; NvBool usesTegraDevice : 1; @@ -998,8 +1063,6 @@ typedef struct _NVEvoDevRec { */ NvBool isHeadSurfaceSupported : 1; - NvU32 validResamplingMethodMask; - nvkms_timer_handle_t *postFlipIMPTimer; nvkms_timer_handle_t *consoleRestoreTimer; @@ -1060,7 +1123,7 @@ typedef struct _NVEvoDevRec { NVHsDeviceEvoPtr pHsDevice; /* The current headSurface configuration. */ - NVHsStateOneHeadAllDisps headSurfaceAllDisps[NVKMS_MAX_HEADS_PER_DISP]; + NVHsStateOneHeadAllDisps apiHeadSurfaceAllDisps[NVKMS_MAX_HEADS_PER_DISP]; struct NVDevPreallocRec prealloc; @@ -1092,12 +1155,26 @@ typedef struct _NVEvoDevRec { } disp[NVKMS_MAX_SUBDEVICES]; } head[NVKMS_MAX_HEADS_PER_DISP]; NVLutSurfaceEvoPtr defaultLut; + enum NvKmsLUTState defaultBaseLUTState[NVKMS_MAX_SUBDEVICES]; + enum NvKmsLUTState defaultOutputLUTState[NVKMS_MAX_SUBDEVICES]; } lut; /*! stores pre-syncpts */ NVEvoSyncpt *preSyncptTable; NvBool *pAllSyncptUsedInCurrentFlip; + /* DIFR prefetch event handling. */ + NVOS10_EVENT_KERNEL_CALLBACK_EX difrPrefetchCallback; + NvU32 difrPrefetchEventHandler; + + /* DIFR runtime state. */ + NVDIFRStateEvoPtr pDifrState; + + NvU32 numApiHeads; + + struct { + NvU32 numLayers; + } apiHead[NVKMS_MAX_HEADS_PER_DISP]; } NVDevEvoRec; /* @@ -1244,8 +1321,6 @@ typedef struct _NVHwModeTimingsEvo { NVHwModeViewPortEvo viewPort; - NVT_VIDEO_INFOFRAME_CTRL infoFrameCtrl; - struct { enum NvKmsStereoMode mode; NvBool isAegis; @@ -1456,6 +1531,12 @@ static inline NvU32 nvEvoConnectorGetPrimaryOr( BIT_IDX_32(LOWESTBIT(pConnectorEvo->or.mask))); } +typedef struct _NVDpyAttributeCurrentDitheringConfigRec { + NvBool enabled; + enum NvKmsDpyAttributeCurrentDitheringDepthValue depth; + enum NvKmsDpyAttributeCurrentDitheringModeValue mode; +} NVDpyAttributeCurrentDitheringConfig; + typedef struct __NVAttributesSetEvoRec { #define NV_EVO_DVC_MIN (-1024) @@ -1472,7 +1553,7 @@ typedef struct __NVAttributesSetEvoRec { * * Since YUV444 mode only allows limited color range, changes to the * current color space may trigger changes to the current color - * range (see nvSetColorSpaceAndRangeEvo()). + * range (see nvChooseCurrentColorSpaceAndRangeEvo()). * * For SW YUV420 mode, these values are ignored in * HEAD_SET_PROCAMP and applied in the headSurface composite shader. @@ -1480,11 +1561,7 @@ typedef struct __NVAttributesSetEvoRec { enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace; enum NvKmsDpyAttributeColorRangeValue colorRange; - struct { - NvBool enabled; - enum NvKmsDpyAttributeCurrentDitheringDepthValue depth; - enum NvKmsDpyAttributeCurrentDitheringModeValue mode; - } dithering; + NVDpyAttributeCurrentDitheringConfig dithering; #define NV_EVO_IMAGE_SHARPENING_MIN 0 #define NV_EVO_IMAGE_SHARPENING_MAX 255 @@ -1531,13 +1608,16 @@ typedef struct _NVDispHeadAudioStateEvoRec { NvBool enabled : 1; } NVDispHeadAudioStateEvoRec; +typedef struct _NVDispHeadInfoFrameStateEvoRec { + NVT_VIDEO_INFOFRAME_CTRL ctrl; + NvBool hdTimings; +} NVDispHeadInfoFrameStateEvoRec; + /* * This structure stores information about the active per-head display state. */ typedef struct _NVDispHeadStateEvoRec { - NVAttributesSetEvoRec attributes; - /*! Cached, to preserve across modesets. */ struct NvKmsModeValidationParams modeValidationParams; @@ -1555,7 +1635,6 @@ typedef struct _NVDispHeadStateEvoRec { * This is intended to be used by console restore to avoid bug 2168873. */ NvBool bypassComposition : 1; - NvBool hs10bpcHint : 1; struct { NVT_COLOR_FORMAT colorFormat; @@ -1576,7 +1655,6 @@ typedef struct _NVDispHeadStateEvoRec { NVHwModeTimingsEvo timings; NVConnectorEvoRec *pConnectorEvo; /* NULL if the head is not active */ - NVDpyIdList activeDpys; /* empty if the head is not active */ /* * Each head can have up to NVKMS_MAX_VBLANK_SYNC_OBJECTS_PER_HEAD @@ -1592,8 +1670,49 @@ typedef struct _NVDispHeadStateEvoRec { NvU32 rmVBlankCallbackHandle; NVListRec vblankCallbackList; + + enum NvKmsOutputTf tf; + + struct { + enum NvKmsHDROutputState outputState; + struct NvKmsHDRStaticMetadata staticMetadata; + nvkms_timer_handle_t *sdrTransitionTimer; + } hdr; + + /* + * The api head can be mapped onto the N harware heads, a frame presented + * by the api head gets split horizontally into N tiles, 'tilePosition' + * describe the tile presented by this hardware head. + */ + NvU8 tilePosition; } NVDispHeadStateEvoRec; +typedef struct _NVDispApiHeadStateEvoRec { + /* + * The mask of hardware heads mapped onto this api head, + * set to zero if the api head is not active. + */ + NvU32 hwHeadsMask; + + NVDpyIdList activeDpys; /* Empty if the head is not active */ + NVAttributesSetEvoRec attributes; + + /* + * Hardware timings which are split across hardware heads. + * + * XXX[2Heads1OR] The api-head state does not require to track full + * hardware timings. Replace 'timings' by minimal per api-head hardware + * timings information used in code. + */ + NVHwModeTimingsEvo timings; + + struct NvKmsPoint viewPortPointIn; + + NVDispHeadInfoFrameStateEvoRec infoFrame; + + NvBool hs10bpcHint : 1; +} NVDispApiHeadStateEvoRec; + typedef struct _NVDispEvoRec { NvU8 gpuLogIndex; NVDevEvoPtr pDevEvo; @@ -1603,6 +1722,7 @@ typedef struct _NVDispEvoRec { NVOS10_EVENT_KERNEL_CALLBACK_EX rmDPIRQCallback; NVDispHeadStateEvoRec headState[NVKMS_MAX_HEADS_PER_DISP]; + NVDispApiHeadStateEvoRec apiHeadState[NVKMS_MAX_HEADS_PER_DISP]; NVDpyIdList vbiosDpyConfig[NVKMS_MAX_HEADS_PER_DISP]; @@ -1664,8 +1784,10 @@ typedef struct _NVDispEvoRec { } framelock; + /* NVDevEvoRec::pHsChannel[] is indexed by the api heads */ NVHsChannelEvoPtr pHsChannel[NVKMS_MAX_HEADS_PER_DISP]; + /* NVDevEvoRec::pSwapGroup[] is indexed by the api heads */ NVSwapGroupPtr pSwapGroup[NVKMS_MAX_HEADS_PER_DISP]; /*! @@ -1696,6 +1818,34 @@ static inline NvU32 nvHardwareHeadToApiHead(const NvU32 head) return head; } + +static inline NvU32 GetNextHwHead(NvU32 hwHeadsMask, const NvU32 prevHwHead) +{ + if ((hwHeadsMask == 0x0) || + ((prevHwHead != NV_INVALID_HEAD) && + ((hwHeadsMask &= ~((1 << (prevHwHead + 1)) -1 )) == 0x0))) { + return NV_INVALID_HEAD; + } + return BIT_IDX_32(LOWESTBIT(hwHeadsMask)); +} + +#define FOR_EACH_EVO_HW_HEAD_IN_MASK(__hwHeadsMask, __hwHead) \ + for ((__hwHead) = GetNextHwHead((__hwHeadsMask), NV_INVALID_HEAD); \ + (__hwHead) != NV_INVALID_HEAD; \ + (__hwHead) = GetNextHwHead((__hwHeadsMask), (__hwHead))) + +#define FOR_EACH_EVO_HW_HEAD(__pDispEvo, __apiHead, __hwHead) \ + FOR_EACH_EVO_HW_HEAD_IN_MASK((__pDispEvo)->apiHeadState[(__apiHead)].hwHeadsMask, \ + (__hwHead)) + +static inline NvU32 nvGetPrimaryHwHead(const NVDispEvoRec *pDispEvo, + const NvU32 apiHead) +{ + return (apiHead != NV_INVALID_HEAD) ? + GetNextHwHead(pDispEvo->apiHeadState[apiHead].hwHeadsMask, + NV_INVALID_HEAD) : NV_INVALID_HEAD; +} + typedef enum { NV_EVO_PASSIVE_DP_DONGLE_UNUSED, NV_EVO_PASSIVE_DP_DONGLE_DP2DVI, @@ -1726,6 +1876,12 @@ typedef struct _NVVBlankCallbackRec { void *pUserData; } NVVBlankCallbackRec; +typedef struct _NVDpyAttributeRequestedDitheringConfigRec { + enum NvKmsDpyAttributeRequestedDitheringValue state; + enum NvKmsDpyAttributeRequestedDitheringDepthValue depth; + enum NvKmsDpyAttributeRequestedDitheringModeValue mode; +} NVDpyAttributeRequestedDitheringConfig; + typedef struct _NVDpyEvoRec { NVListRec dpyListEntry; NVDpyId id; @@ -1757,11 +1913,7 @@ typedef struct _NVDpyEvoRec { NVEdidRec edid; NVParsedEdidEvoRec parsedEdid; - struct { - enum NvKmsDpyAttributeRequestedDitheringValue state; - enum NvKmsDpyAttributeRequestedDitheringDepthValue depth; - enum NvKmsDpyAttributeRequestedDitheringModeValue mode; - } requestedDithering; + NVDpyAttributeRequestedDitheringConfig requestedDithering; enum NvKmsDpyAttributeRequestedColorSpaceValue requestedColorSpace; enum NvKmsDpyAttributeColorRangeValue requestedColorRange; @@ -1783,6 +1935,15 @@ typedef struct _NVDpyEvoRec { NvU8 buffer[NVKMS_GUID_SIZE]; char str[NVKMS_GUID_STRING_SIZE]; } guid; + + /* + * When the DP serializer is in MST mode, this field is used to uniquely + * identify each MST DPY that's connected to the DP serializer. + * + * This field is only valid for DP serializer DPYs, and pDpLibDevice + * must be NULL in this case. + */ + NvU8 serializerStreamIndex; } dp; struct { @@ -1975,6 +2136,13 @@ static inline NvBool nvHeadIsActive(const NVDispEvoRec *pDispEvo, (pDispEvo->headState[head].pConnectorEvo != NULL); } +static inline NvBool nvApiHeadIsActive(const NVDispEvoRec *pDispEvo, + const NvU32 apiHead) +{ + return (apiHead < ARRAY_LEN(pDispEvo->apiHeadState)) && + (!nvDpyIdListIsEmpty(pDispEvo->apiHeadState[apiHead].activeDpys)); +} + /*! * Return the mask of active heads on this pDispEvo. */ @@ -2015,13 +2183,14 @@ static inline NvBool nvAllHeadsInactive(const NVDevEvoRec *pDevEvo) static inline NVDpyIdList nvActiveDpysOnDispEvo(const NVDispEvoRec *pDispEvo) { NVDpyIdList dpyIdList = nvEmptyDpyIdList(); - NvU32 head; + NvU32 apiHead; - for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { - const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + for (apiHead = 0; apiHead < NVKMS_MAX_HEADS_PER_DISP; apiHead++) { + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; dpyIdList = nvAddDpyIdListToDpyIdList(dpyIdList, - pHeadState->activeDpys); + pApiHeadState->activeDpys); } return dpyIdList; @@ -2062,6 +2231,8 @@ typedef struct _NVLutSurfaceEvo { NvU32 dispCtxDma; + NvU32 allocRefCnt; /* Only used for dynamically allocated LUTs */ + void *subDeviceAddress[NVKMS_MAX_SUBDEVICES]; } NVLutSurfaceEvoRec; @@ -2152,6 +2323,7 @@ enum NvHsMapPermissions { #define NVKMS_SURFACE_MEMORY_FORMATS_RGB_PACKED8BPP ( \ NVBIT64(NvKmsSurfaceMemoryFormatRF16GF16BF16AF16) | \ + NVBIT64(NvKmsSurfaceMemoryFormatRF16GF16BF16XF16) | \ NVBIT64(NvKmsSurfaceMemoryFormatR16G16B16A16)) #define NVKMS_SURFACE_MEMORY_FORMATS_YUV_PACKED422 ( \ @@ -2228,6 +2400,12 @@ struct _NVSurfaceEvoRec { NvU32 log2GobsPerBlockY; + /* + * GPU virtual address of the surface, in NVKMS's VA space for use by + * headSurface. + */ + NvU64 gpuAddress; + /* * HeadSurface needs a CPU mapping of surfaces containing semaphores. */ @@ -2555,11 +2733,15 @@ typedef const struct _nv_evo_hal { void (*AccelerateChannel)(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel, const NvU32 sd, + const NvBool trashPendingMethods, + const NvBool unblockMethodsInExecutation, NvU32 *pOldAccelerators); void (*ResetChannelAccelerators)(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel, const NvU32 sd, + const NvBool trashPendingMethods, + const NvBool unblockMethodsInExecutation, NvU32 oldAccelerators); NvBool (*AllocRmCtrlObject) (NVDevEvoPtr); @@ -2637,6 +2819,7 @@ typedef const struct _nv_evo_hal { NvU32 supportedDitheringModes; size_t impStructSize; NVEvoScalerTaps minScalerTaps; + NvU64 xEmulatedSurfaceMemoryFormats; } caps; } NVEvoHAL, *NVEvoHALPtr; diff --git a/src/nvidia-modeset/include/nvkms-vrr.h b/src/nvidia-modeset/include/nvkms-vrr.h index 91c375a8c..f90ee0301 100644 --- a/src/nvidia-modeset/include/nvkms-vrr.h +++ b/src/nvidia-modeset/include/nvkms-vrr.h @@ -41,8 +41,8 @@ void nvSetVrrActive(NVDevEvoPtr pDevEvo, NvBool active); void nvApplyVrrBaseFlipOverrides(const NVDispEvoRec *pDispEvo, NvU32 head, const NVFlipChannelEvoHwState *pOld, NVFlipChannelEvoHwState *pNew); -void nvSetNextVrrFlipTypeAndIndex(NVDevEvoPtr pDevEvo, - struct NvKmsFlipReply *reply); +enum NvKmsVrrFlipType nvGetActiveVrrType(const NVDevEvoRec *pDevEvo); +NvS32 nvIncVrrSemaphoreIndex(NVDevEvoPtr pDevEvo); void nvTriggerVrrUnstallMoveCursor(NVDispEvoPtr pDispEvo); void nvTriggerVrrUnstallSetCursorImage(NVDispEvoPtr pDispEvo, NvBool ctxDmaChanged); diff --git a/src/nvidia-modeset/interface/nvkms-api-types.h b/src/nvidia-modeset/interface/nvkms-api-types.h index 0f59c8304..7131b32b8 100644 --- a/src/nvidia-modeset/interface/nvkms-api-types.h +++ b/src/nvidia-modeset/interface/nvkms-api-types.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -29,6 +29,7 @@ #include #define NVKMS_MAX_SUBDEVICES NV_MAX_SUBDEVICES +#define NVKMS_MAX_HEADS_PER_DISP NV_MAX_HEADS #define NVKMS_LEFT 0 #define NVKMS_RIGHT 1 @@ -530,4 +531,78 @@ typedef struct { NvBool noncoherent; } NvKmsDispIOCoherencyModes; +enum NvKmsInputColorSpace { + /* Unknown colorspace; no de-gamma will be applied */ + NVKMS_INPUT_COLORSPACE_NONE = 0, + + /* Linear, Rec.709 [-0.5, 7.5) */ + NVKMS_INPUT_COLORSPACE_SCRGB_LINEAR = 1, + + /* PQ, Rec.2020 unity */ + NVKMS_INPUT_COLORSPACE_BT2100_PQ = 2, +}; + +enum NvKmsOutputTf { + /* + * NVKMS itself won't apply any OETF (clients are still + * free to provide a custom OLUT) + */ + NVKMS_OUTPUT_TF_NONE = 0, + NVKMS_OUTPUT_TF_TRADITIONAL_GAMMA_SDR = 1, + NVKMS_OUTPUT_TF_PQ = 2, +}; + +/*! + * HDR Static Metadata Type1 Descriptor as per CEA-861.3 spec. + * This is expected to match exactly with the spec. + */ +struct NvKmsHDRStaticMetadata { + /*! + * Color primaries of the data. + * These are coded as unsigned 16-bit values in units of 0.00002, + * where 0x0000 represents zero and 0xC350 represents 1.0000. + */ + struct { + NvU16 x, y; + } displayPrimaries[3]; + + /*! + * White point of colorspace data. + * These are coded as unsigned 16-bit values in units of 0.00002, + * where 0x0000 represents zero and 0xC350 represents 1.0000. + */ + struct { + NvU16 x, y; + } whitePoint; + + /** + * Maximum mastering display luminance. + * This value is coded as an unsigned 16-bit value in units of 1 cd/m2, + * where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2. + */ + NvU16 maxDisplayMasteringLuminance; + + /*! + * Minimum mastering display luminance. + * This value is coded as an unsigned 16-bit value in units of + * 0.0001 cd/m2, where 0x0001 represents 0.0001 cd/m2 and 0xFFFF + * represents 6.5535 cd/m2. + */ + NvU16 minDisplayMasteringLuminance; + + /*! + * Maximum content light level. + * This value is coded as an unsigned 16-bit value in units of 1 cd/m2, + * where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2. + */ + NvU16 maxCLL; + + /*! + * Maximum frame-average light level. + * This value is coded as an unsigned 16-bit value in units of 1 cd/m2, + * where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2. + */ + NvU16 maxFALL; +}; + #endif /* NVKMS_API_TYPES_H */ diff --git a/src/nvidia-modeset/interface/nvkms-api.h b/src/nvidia-modeset/interface/nvkms-api.h index f7bc6842f..1682ace4c 100644 --- a/src/nvidia-modeset/interface/nvkms-api.h +++ b/src/nvidia-modeset/interface/nvkms-api.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -54,12 +54,8 @@ * device: multiple devices may have disps with the same dispHandle * value. * - * A disp contains one or more subdevices, as reported by - * NvKmsQueryDispReply::subDeviceMask. A disp will only have - * multiple subdevices in cases where the device only has a single - * disp. Any subdevice specified in - * NvKmsQueryDispReply::subDeviceMask will also be in - * NvKmsAllocDeviceReply::subDeviceMask. + * A disp represents one subdevice; disp index N corresponds to subdevice + * index N. * * - A connector, which represents an electrical connection to the * GPU. E.g., a physical DVI-I connector has two NVKMS connector @@ -270,12 +266,12 @@ enum NvKmsIoctlCommand { NVKMS_IOCTL_EXPORT_VRR_SEMAPHORE_SURFACE, NVKMS_IOCTL_ENABLE_VBLANK_SYNC_OBJECT, NVKMS_IOCTL_DISABLE_VBLANK_SYNC_OBJECT, + NVKMS_IOCTL_NOTIFY_VBLANK, }; #define NVKMS_NVIDIA_DRIVER_VERSION_STRING_LENGTH 32 #define NVKMS_MAX_CONNECTORS_PER_DISP 16 -#define NVKMS_MAX_HEADS_PER_DISP 4 #define NVKMS_MAX_GPUS_PER_FRAMELOCK 4 #define NVKMS_MAX_DEVICE_REGISTRY_KEYS 16 #define NVKMS_MAX_DEVICE_REGISTRY_KEYNAME_LEN 32 @@ -700,73 +696,6 @@ struct NvKmsChannelSyncObjects { } u; }; -enum NvKmsOutputTf { - /* - * NVKMS itself won't apply any OETF (clients are still - * free to provide a custom OLUT) - */ - NVKMS_OUTPUT_TF_NONE = 0, - NVKMS_OUTPUT_TF_PQ = 1, -}; - -/*! - * HDR Static Metadata Type1 Descriptor as per CEA-861.3 spec. - * This is expected to match exactly with the spec. - */ -struct NvKmsHDRStaticMetadata { - /*! - * Color primaries of the data. - * These are coded as unsigned 16-bit values in units of 0.00002, - * where 0x0000 represents zero and 0xC350 represents 1.0000. - */ - struct { - NvU16 x, y; - } displayPrimaries[3]; - - /*! - * White point of colorspace data. - * These are coded as unsigned 16-bit values in units of 0.00002, - * where 0x0000 represents zero and 0xC350 represents 1.0000. - */ - struct { - NvU16 x, y; - } whitePoint; - - /** - * Maximum mastering display luminance. - * This value is coded as an unsigned 16-bit value in units of 1 cd/m2, - * where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2. - */ - NvU16 maxDisplayMasteringLuminance; - - /*! - * Minimum mastering display luminance. - * This value is coded as an unsigned 16-bit value in units of - * 0.0001 cd/m2, where 0x0001 represents 0.0001 cd/m2 and 0xFFFF - * represents 6.5535 cd/m2. - */ - NvU16 minDisplayMasteringLuminance; - - /*! - * Maximum content light level. - * This value is coded as an unsigned 16-bit value in units of 1 cd/m2, - * where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2. - */ - NvU16 maxCLL; - - /*! - * Maximum frame-average light level. - * This value is coded as an unsigned 16-bit value in units of 1 cd/m2, - * where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2. - */ - NvU16 maxFALL; -}; - -enum NvKmsInputColorSpace { - /* Unknown colorspace; no de-gamma will be applied */ - NVKMS_SURFACE_COLORSPACE_NONE = 0, -}; - /*! * Description of how to flip on a single head. * @@ -980,6 +909,7 @@ struct NvKmsFlipCommonParams { struct NvKmsHDRStaticMetadata staticMetadata; } hdr; + /* This field has no effect right now. */ struct { enum NvKmsInputColorSpace val; NvBool specified; @@ -1117,7 +1047,6 @@ struct NvKmsAllocDeviceReply { * IMPLEMENTATION NOTE: this is the portion of DispHalRec::caps * that can vary between EVO classes. */ - NvBool supportsInbandStereoSignaling; NvBool requiresVrrSemaphores; NvBool inputLutAppliesToBase; @@ -1128,8 +1057,7 @@ struct NvKmsAllocDeviceReply { NvBool supportsSwapGroups; /*! - * Whether the NVKMS SwapGroup implementation supports Warp and Blend on - * this device. + * Whether NVKMS supports Warp and Blend on this device. */ NvBool supportsWarpAndBlend; @@ -1166,15 +1094,6 @@ struct NvKmsAllocDeviceReply { */ NvU8 validNIsoFormatMask; - /*! - * Which NvKmsResamplingMethod enum values are supported by the NVKMS - * device. - * - * Iff a particular enum NvKmsResamplingMethod 'value' is supported, then (1 - * << value) will be set in validResamplingMethodMask. - */ - NvU32 validResamplingMethodMask; - NvU32 surfaceAlignment; NvU32 maxWidthInBytes; NvU32 maxWidthInPixels; @@ -1216,6 +1135,12 @@ struct NvKmsAllocDeviceReply { NvKmsDispIOCoherencyModes isoIOCoherencyModes; NvKmsDispIOCoherencyModes nisoIOCoherencyModes; + /*! + * 'displayIsGpuL2Coherent' indicates whether display is coherent with + * GPU's L2 cache. + */ + NvBool displayIsGpuL2Coherent; + /*! * 'supportsSyncpts' indicates whether NVKMS supports the use of syncpts * for synchronization. @@ -1290,15 +1215,6 @@ struct NvKmsQueryDispRequest { }; struct NvKmsQueryDispReply { - /*! - * The instance of the subdevice that owns this disp. - * NVBIT(displayOwner) will be present in subDeviceMask. - */ - NvU32 displayOwner; - - /*! A bitmask of the device's subdevices used by this disp. */ - NvU32 subDeviceMask; - /*! The possible dpys for this disp, excluding any dynamic dpys. */ NVDpyIdList validDpys; @@ -2000,7 +1916,6 @@ enum NvKmsSetModeOneHeadStatus { NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_PERMISSIONS = 7, NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_HEAD_SURFACE = 8, NVKMS_SET_MODE_ONE_HEAD_STATUS_UNSUPPORTED_HEAD_SURFACE_COMBO = 9, - NVKMS_SET_MODE_ONE_HEAD_STATUS_UNSUPPORTED_HEAD_SURFACE_FEATURE = 10, }; struct NvKmsSetModeOneHeadReply { @@ -2220,8 +2135,7 @@ struct NvKmsFlipRequest { NvKmsDeviceHandle deviceHandle; /* - * sd[n] corresponds to bit N in NvKmsQueryDispReply::subDeviceMask and - * NvKmsAllocDeviceReply::subDeviceMask. + * sd[n] corresponds to bit N in NvKmsAllocDeviceReply::subDeviceMask. */ struct NvKmsFlipRequestOneSubDevice sd[NVKMS_MAX_SUBDEVICES]; @@ -2275,8 +2189,7 @@ struct NvKmsFlipReply { enum NvKmsVrrFlipType vrrFlipType; /*! - * sd[n] corresponds to bit N in NvKmsQueryDispReply::subDeviceMask and - * NvKmsAllocDeviceReply::subDeviceMask. + * sd[n] corresponds to bit N in NvKmsAllocDeviceReply::subDeviceMask. */ struct NvKmsFlipReplyOneSubDevice sd[NVKMS_MAX_SUBDEVICES]; }; @@ -2690,6 +2603,7 @@ enum NvKmsDpyAttributeCurrentColorSpaceValue { NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422 = 1, NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444 = 2, NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420 = 3, + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_BT2020RGB = 4, }; /*! Values for the NV_KMS_DPY_ATTRIBUTE_DIGITAL_SIGNAL attribute. */ @@ -4069,4 +3983,32 @@ struct NvKmsDisableVblankSyncObjectParams { struct NvKmsDisableVblankSyncObjectReply reply; /*! out */ }; +/*! + * NVKMS_IOCTL_NOTIFY_VBLANK: + * + * Register a unicast event fd to be notified when the next vblank event occurs + * on the specified head. This is a one-shot notification, and in order to be + * notified of subsequent vblank events the caller must clear and re-register + * the unicast event fd. + */ + +struct NvKmsNotifyVblankRequest { + NvKmsDeviceHandle deviceHandle; + NvKmsDispHandle dispHandle; + NvU32 head; + + struct { + int fd; + } unicastEvent; +}; + +struct NvKmsNotifyVblankReply { + NvU32 padding; +}; + +struct NvKmsNotifyVblankParams { + struct NvKmsNotifyVblankRequest request; /*! in */ + struct NvKmsNotifyVblankReply reply; /*! out */ +}; + #endif /* NVKMS_API_H */ diff --git a/src/nvidia-modeset/interface/nvkms-format.h b/src/nvidia-modeset/interface/nvkms-format.h index d1483f875..88b26b3d4 100644 --- a/src/nvidia-modeset/interface/nvkms-format.h +++ b/src/nvidia-modeset/interface/nvkms-format.h @@ -86,8 +86,9 @@ enum NvKmsSurfaceMemoryFormat { NvKmsSurfaceMemoryFormatY12___V12U12_N420 = 32, NvKmsSurfaceMemoryFormatY8___U8___V8_N444 = 33, NvKmsSurfaceMemoryFormatY8___U8___V8_N420 = 34, + NvKmsSurfaceMemoryFormatRF16GF16BF16XF16 = 35, NvKmsSurfaceMemoryFormatMin = NvKmsSurfaceMemoryFormatI8, - NvKmsSurfaceMemoryFormatMax = NvKmsSurfaceMemoryFormatY8___U8___V8_N420, + NvKmsSurfaceMemoryFormatMax = NvKmsSurfaceMemoryFormatRF16GF16BF16XF16, }; typedef struct NvKmsSurfaceMemoryFormatInfo { diff --git a/src/nvidia-modeset/kapi/include/nvkms-kapi-internal.h b/src/nvidia-modeset/kapi/include/nvkms-kapi-internal.h index dbaab771b..a0ba45899 100644 --- a/src/nvidia-modeset/kapi/include/nvkms-kapi-internal.h +++ b/src/nvidia-modeset/kapi/include/nvkms-kapi-internal.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -81,9 +81,11 @@ struct NvKmsKapiDevice { NvU32 maxCursorSizeInPixels; NvU8 genericPageKind; + NvBool requiresVrrSemaphores; } caps; NvU64 supportedSurfaceMemoryFormats[NVKMS_KAPI_LAYER_MAX]; + NvBool supportsHDR[NVKMS_KAPI_LAYER_MAX]; NvU32 numHeads; NvU32 numLayers[NVKMS_KAPI_MAX_HEADS]; diff --git a/src/nvidia-modeset/kapi/interface/nvkms-kapi.h b/src/nvidia-modeset/kapi/interface/nvkms-kapi.h index a63d8dfdf..0ae71e170 100644 --- a/src/nvidia-modeset/kapi/interface/nvkms-kapi.h +++ b/src/nvidia-modeset/kapi/interface/nvkms-kapi.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -149,6 +149,7 @@ struct NvKmsKapiDeviceResourcesInfo { } caps; NvU64 supportedSurfaceMemoryFormats[NVKMS_KAPI_LAYER_MAX]; + NvBool supportsHDR[NVKMS_KAPI_LAYER_MAX]; }; #define NVKMS_KAPI_LAYER_MASK(layerType) (1 << (layerType)) @@ -218,6 +219,11 @@ struct NvKmsKapiLayerConfig { struct NvKmsRRParams rrParams; struct NvKmsKapiSyncpt syncptParams; + struct NvKmsHDRStaticMetadata hdrMetadata; + NvBool hdrMetadataSpecified; + + enum NvKmsOutputTf tf; + NvU8 minPresentInterval; NvBool tearing; @@ -226,6 +232,8 @@ struct NvKmsKapiLayerConfig { NvS16 dstX, dstY; NvU16 dstWidth, dstHeight; + + enum NvKmsInputColorSpace inputColorSpace; }; struct NvKmsKapiLayerRequestedConfig { @@ -277,6 +285,8 @@ struct NvKmsKapiHeadModeSetConfig { NvKmsKapiDisplay displays[NVKMS_KAPI_MAX_CLONE_DISPLAYS]; struct NvKmsKapiDisplayMode mode; + + NvBool vrrEnabled; }; struct NvKmsKapiHeadRequestedConfig { @@ -368,6 +378,9 @@ struct NvKmsKapiDynamicDisplayParams { /* [OUT] Connection status */ NvU32 connected; + /* [OUT] VRR status */ + NvBool vrrSupported; + /* [IN/OUT] EDID of connected monitor/ Input to override EDID */ struct { NvU16 bufferSize; @@ -484,6 +497,38 @@ struct NvKmsKapiFunctionsTable { */ void (*releaseOwnership)(struct NvKmsKapiDevice *device); + /*! + * Grant modeset permissions for a display to fd. Only one (dispIndex, head, + * display) is currently supported. + * + * \param [in] fd fd from opening /dev/nvidia-modeset. + * + * \param [in] device A device returned by allocateDevice(). + * + * \param [in] head head of display. + * + * \param [in] display The display to grant. + * + * \return NV_TRUE on success, NV_FALSE on failure. + */ + NvBool (*grantPermissions) + ( + NvS32 fd, + struct NvKmsKapiDevice *device, + NvU32 head, + NvKmsKapiDisplay display + ); + + /*! + * Revoke modeset permissions previously granted. This currently applies for all + * previous grant requests for this device. + * + * \param [in] device A device returned by allocateDevice(). + * + * \return NV_TRUE on success, NV_FALSE on failure. + */ + NvBool (*revokePermissions)(struct NvKmsKapiDevice *device); + /*! * Registers for notification, via * NvKmsKapiAllocateDeviceParams::eventCallback, of the events specified diff --git a/src/nvidia-modeset/kapi/src/nvkms-kapi.c b/src/nvidia-modeset/kapi/src/nvkms-kapi.c index 688e72538..8f3a63de3 100644 --- a/src/nvidia-modeset/kapi/src/nvkms-kapi.c +++ b/src/nvidia-modeset/kapi/src/nvkms-kapi.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,6 +27,7 @@ #include "nvkms-api.h" #include "nvkms-rmapi.h" +#include "nvkms-vrr.h" #include "nvkms-kapi.h" #include "nvkms-kapi-private.h" @@ -352,6 +353,7 @@ static NvBool KmsAllocateDevice(struct NvKmsKapiDevice *device) device->caps.maxHeightInPixels = paramsAlloc->reply.maxHeightInPixels; device->caps.maxCursorSizeInPixels = paramsAlloc->reply.maxCursorSize; device->caps.genericPageKind = paramsAlloc->reply.genericPageKind; + device->caps.requiresVrrSemaphores = paramsAlloc->reply.requiresVrrSemaphores; /* XXX Add LUT support */ @@ -367,6 +369,7 @@ static NvBool KmsAllocateDevice(struct NvKmsKapiDevice *device) for (layer = 0; layer < NVKMS_KAPI_LAYER_MAX; layer++) { device->supportedSurfaceMemoryFormats[layer] = paramsAlloc->reply.layerCaps[layer].supportedSurfaceMemoryFormats; + device->supportsHDR[layer] = paramsAlloc->reply.layerCaps[layer].supportsHDR; } if (paramsAlloc->reply.validNIsoFormatMask & @@ -815,6 +818,59 @@ static void ReleaseOwnership(struct NvKmsKapiDevice *device) ¶msRelease, sizeof(paramsRelease)); } +static NvBool GrantPermissions +( + NvS32 fd, + struct NvKmsKapiDevice *device, + NvU32 head, + NvKmsKapiDisplay display +) +{ + struct NvKmsGrantPermissionsParams paramsGrant = { }; + struct NvKmsPermissions *perm = ¶msGrant.request.permissions; + NvU32 dispIdx = device->dispIdx; + + if (dispIdx >= ARRAY_LEN(perm->modeset.disp) || + head >= ARRAY_LEN(perm->modeset.disp[0].head) || device == NULL) { + return NV_FALSE; + } + + if (device->hKmsDevice == 0x0) { + return NV_TRUE; + } + + perm->type = NV_KMS_PERMISSIONS_TYPE_MODESET; + perm->modeset.disp[dispIdx].head[head].dpyIdList = + nvAddDpyIdToEmptyDpyIdList(nvNvU32ToDpyId(display)); + + paramsGrant.request.fd = fd; + paramsGrant.request.deviceHandle = device->hKmsDevice; + + return nvkms_ioctl_from_kapi(device->pKmsOpen, + NVKMS_IOCTL_GRANT_PERMISSIONS, ¶msGrant, + sizeof(paramsGrant)); +} + +static NvBool RevokePermissions(struct NvKmsKapiDevice *device) +{ + struct NvKmsRevokePermissionsParams paramsRevoke = { }; + + if (device == NULL) { + return NV_FALSE; + } + + if (device->hKmsDevice == 0x0) { + return NV_TRUE; + } + + paramsRevoke.request.deviceHandle = device->hKmsDevice; + paramsRevoke.request.permissionsTypeBitmask = NVBIT(NV_KMS_PERMISSIONS_TYPE_MODESET); + + return nvkms_ioctl_from_kapi(device->pKmsOpen, + NVKMS_IOCTL_REVOKE_PERMISSIONS, ¶msRevoke, + sizeof(paramsRevoke)); +} + static NvBool DeclareEventInterest ( const struct NvKmsKapiDevice *device, @@ -931,6 +987,13 @@ static NvBool GetDeviceResourcesInfo nvkms_memcpy(info->supportedSurfaceMemoryFormats, device->supportedSurfaceMemoryFormats, sizeof(device->supportedSurfaceMemoryFormats)); + + ct_assert(sizeof(info->supportsHDR) == + sizeof(device->supportsHDR)); + + nvkms_memcpy(info->supportsHDR, + device->supportsHDR, + sizeof(device->supportsHDR)); done: return status; @@ -1145,6 +1208,8 @@ static NvBool GetDynamicDisplayInfo( params->connected = pParamsDpyDynamic->reply.connected; if (pParamsDpyDynamic->reply.connected && !params->overrideEdid) { + NvBool vrrSupported = + (pParamsDpyDynamic->reply.vrrType != NVKMS_DPY_VRR_TYPE_NONE) ? NV_TRUE : NV_FALSE; nvkms_memcpy( params->edid.buffer, @@ -1152,6 +1217,7 @@ static NvBool GetDynamicDisplayInfo( sizeof(params->edid.buffer)); params->edid.bufferSize = pParamsDpyDynamic->reply.edid.bufferSize; + params->vrrSupported = (vrrSupported && !device->caps.requiresVrrSemaphores) ? NV_TRUE : NV_FALSE; } done: @@ -2277,6 +2343,21 @@ static NvBool AssignSyncObjectConfig( return NV_TRUE; } +static void AssignHDRMetadataConfig( + const struct NvKmsKapiLayerConfig *layerConfig, + const NvU32 layer, + struct NvKmsFlipCommonParams *params) +{ + if (layerConfig->hdrMetadataSpecified) { + params->layer[layer].hdr.enabled = TRUE; + params->layer[layer].hdr.specified = TRUE; + params->layer[layer].hdr.staticMetadata = layerConfig->hdrMetadata; + } else { + params->layer[layer].hdr.enabled = FALSE; + params->layer[layer].hdr.specified = TRUE; + } +} + static void NvKmsKapiCursorConfigToKms( const struct NvKmsKapiCursorRequestedConfig *requestedConfig, struct NvKmsFlipCommonParams *params, @@ -2358,6 +2439,11 @@ static NvBool NvKmsKapiOverlayLayerConfigToKms( params->layer[layer].outputPosition.specified = NV_TRUE; } + params->layer[layer].colorspace.val = layerConfig->inputColorSpace; + params->layer[layer].colorspace.specified = TRUE; + + AssignHDRMetadataConfig(layerConfig, layer, params); + if (commit) { NvU32 nextIndex = NVKMS_KAPI_INC_NOTIFIER_INDEX( device->layerState[head][layer]. @@ -2454,6 +2540,11 @@ static NvBool NvKmsKapiPrimaryLayerConfigToKms( changed = TRUE; } + params->layer[NVKMS_MAIN_LAYER].colorspace.val = layerConfig->inputColorSpace; + params->layer[NVKMS_MAIN_LAYER].colorspace.specified = TRUE; + + AssignHDRMetadataConfig(layerConfig, NVKMS_MAIN_LAYER, params); + if (commit && changed) { NvU32 nextIndex = NVKMS_KAPI_INC_NOTIFIER_INDEX( device->layerState[head][NVKMS_MAIN_LAYER]. @@ -2527,6 +2618,38 @@ static NvBool NvKmsKapiLayerConfigToKms( bFromKmsSetMode); } +static NvBool GetOutputTransferFunction( + const struct NvKmsKapiHeadRequestedConfig *headRequestedConfig, + enum NvKmsOutputTf *tf) +{ + NvBool found = NV_FALSE; + NvU32 layer; + + *tf = NVKMS_OUTPUT_TF_NONE; + + for (layer = 0; + layer < ARRAY_LEN(headRequestedConfig->layerRequestedConfig); + layer++) { + const struct NvKmsKapiLayerRequestedConfig *layerRequestedConfig = + &headRequestedConfig->layerRequestedConfig[layer]; + const struct NvKmsKapiLayerConfig *layerConfig = + &layerRequestedConfig->config; + + if (layerConfig->hdrMetadataSpecified) { + if (!found) { + *tf = layerConfig->tf; + found = NV_TRUE; + } else if (*tf != layerConfig->tf) { + nvKmsKapiLogDebug( + "Output transfer function should be the same for all layers on a head"); + return NV_FALSE; + } + } + } + + return NV_TRUE; +} + /* * Helper function to convert NvKmsKapiRequestedModeSetConfig * to NvKmsSetModeParams. @@ -2554,6 +2677,7 @@ static NvBool NvKmsKapiRequestedModeSetConfigToKms( const struct NvKmsKapiHeadModeSetConfig *headModeSetConfig = &headRequestedConfig->modeSetConfig; struct NvKmsSetModeOneHeadRequest *paramsHead; + enum NvKmsOutputTf tf; NvU32 layer; NvU32 i; @@ -2605,10 +2729,25 @@ static NvBool NvKmsKapiRequestedModeSetConfigToKms( } } + if (!GetOutputTransferFunction(headRequestedConfig, &tf)) { + return NV_FALSE; + } + + paramsHead->flip.tf.val = tf; + paramsHead->flip.tf.specified = NV_TRUE; + paramsHead->viewPortSizeIn.width = headModeSetConfig->mode.timings.hVisible; paramsHead->viewPortSizeIn.height = headModeSetConfig->mode.timings.vVisible; + + if (device->caps.requiresVrrSemaphores) { + paramsHead->allowGsync = NV_FALSE; + paramsHead->allowAdaptiveSync = NVKMS_ALLOW_ADAPTIVE_SYNC_DISABLED; + } else { + paramsHead->allowGsync = NV_TRUE; + paramsHead->allowAdaptiveSync = NVKMS_ALLOW_ADAPTIVE_SYNC_ALL; + } } return NV_TRUE; @@ -2722,6 +2861,7 @@ static NvBool KmsFlip( params->request.deviceHandle = device->hKmsDevice; params->request.commit = commit; + params->request.allowVrr = NV_FALSE; for (i = 0; i < ARRAY_LEN(params->request.sd); i++) { struct NvKmsFlipRequestOneSubDevice *sdParams = ¶ms->request.sd[i]; @@ -2738,6 +2878,7 @@ static NvBool KmsFlip( &requestedConfig->headRequestedConfig[head]; const struct NvKmsKapiHeadModeSetConfig *headModeSetConfig = &headRequestedConfig->modeSetConfig; + enum NvKmsOutputTf tf; struct NvKmsFlipCommonParams *flipParams = &sdParams->head[head]; @@ -2775,6 +2916,18 @@ static NvBool KmsFlip( bChanged = NV_TRUE; } + + status = GetOutputTransferFunction(headRequestedConfig, &tf); + if (status != NV_TRUE) { + goto done; + } + + flipParams->tf.val = tf; + flipParams->tf.specified = NV_TRUE; + + if (headModeSetConfig->vrrEnabled) { + params->request.allowVrr = NV_TRUE; + } } } @@ -3064,6 +3217,9 @@ NvBool nvKmsKapiGetFunctionsTableInternal funcsTable->grabOwnership = GrabOwnership; funcsTable->releaseOwnership = ReleaseOwnership; + funcsTable->grantPermissions = GrantPermissions; + funcsTable->revokePermissions = RevokePermissions; + funcsTable->declareEventInterest = DeclareEventInterest; funcsTable->getDeviceResourcesInfo = GetDeviceResourcesInfo; diff --git a/src/nvidia-modeset/lib/nvkms-format.c b/src/nvidia-modeset/lib/nvkms-format.c index 55901cf82..cb8c8fd1a 100644 --- a/src/nvidia-modeset/lib/nvkms-format.c +++ b/src/nvidia-modeset/lib/nvkms-format.c @@ -83,6 +83,7 @@ static const NvKmsSurfaceMemoryFormatInfo nvKmsSurfaceMemoryFormatInfo[] = { RGB_ENTRY(A8B8G8R8, 32, 4), RGB_ENTRY(X8B8G8R8, 24, 4), RGB_ENTRY(RF16GF16BF16AF16, 64, 8), + RGB_ENTRY(RF16GF16BF16XF16, 64, 8), RGB_ENTRY(R16G16B16A16, 64, 8), RGB_ENTRY(RF32GF32BF32AF32, 128, 16), YUV_ENTRY(Y8_U8__Y8_V8_N422, 16, 1, 8, 8, 2, 1), diff --git a/src/nvidia-modeset/src/dp/nvdp-connector.cpp b/src/nvidia-modeset/src/dp/nvdp-connector.cpp index 47917361e..ef6a55e80 100644 --- a/src/nvidia-modeset/src/dp/nvdp-connector.cpp +++ b/src/nvidia-modeset/src/dp/nvdp-connector.cpp @@ -333,6 +333,7 @@ static void InitDpModesetParams( pParams->colorFormat = dpColorFormat_YCbCr422; break; case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB: + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_BT2020RGB: pParams->colorFormat = dpColorFormat_RGB; break; } diff --git a/src/nvidia-modeset/src/dp/nvdp-evo-interface.cpp b/src/nvidia-modeset/src/dp/nvdp-evo-interface.cpp index 70dda08fc..74e89b8cb 100644 --- a/src/nvidia-modeset/src/dp/nvdp-evo-interface.cpp +++ b/src/nvidia-modeset/src/dp/nvdp-evo-interface.cpp @@ -85,6 +85,15 @@ NvU32 EvoInterface::getRegkeyValue(const char *key) bool EvoInterface::isInbandStereoSignalingSupported() { + NVDispEvoPtr pDispEvo = pConnectorEvo->pDispEvo; + NVDpyEvoPtr pDpyEvo; + + FOR_ALL_EVO_DPYS(pDpyEvo, pDispEvo->validDisplays, pDispEvo) { + if ((pDpyEvo->pConnectorEvo == pConnectorEvo) && + pDpyEvo->dp.inbandStereoSignaling) { + return TRUE; + } + } return FALSE; } diff --git a/src/nvidia-modeset/src/nvkms-attributes.c b/src/nvidia-modeset/src/nvkms-attributes.c index f39305f4c..666fd9df8 100644 --- a/src/nvidia-modeset/src/nvkms-attributes.c +++ b/src/nvidia-modeset/src/nvkms-attributes.c @@ -30,6 +30,7 @@ #include "nvkms-rm.h" #include "nvkms-rmapi.h" #include "nvos.h" +#include "nvkms-stereo.h" #include // NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_* @@ -154,14 +155,15 @@ static NvBool GetScanLine(const NVDpyEvoRec *pDpyEvo, NvS64 *pScanLine) NV0073_CTRL_SYSTEM_GET_SCANLINE_PARAMS params = { 0 }; NVDispEvoPtr pDispEvo = pDpyEvo->pDispEvo; NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; - NvU32 ret; - /* XXX[2Heads1OR] Get scanline of the primary hardware head. */ - const NvU32 head = pDpyEvo->apiHead; + NvU32 head, ret; - if (head == NV_INVALID_HEAD) { + if (pDpyEvo->apiHead == NV_INVALID_HEAD) { return FALSE; } + head = nvGetPrimaryHwHead(pDispEvo, pDpyEvo->apiHead); + nvAssert(head != NV_INVALID_HEAD); + params.subDeviceInstance = pDispEvo->displayOwner; params.head = head; @@ -205,18 +207,39 @@ static NvBool DitherConfigurationAllowed(const NVDpyEvoRec *pDpyEvo) static void SetDitheringCommon(NVDpyEvoPtr pDpyEvo) { NVEvoUpdateState updateState = { }; + const NVConnectorEvoRec *pConnectorEvo = pDpyEvo->pConnectorEvo; + NVDispEvoRec *pDispEvo = pConnectorEvo->pDispEvo; + NVDispApiHeadStateEvoRec *pApiHeadState; + enum nvKmsPixelDepth pixelDepth; + NvU32 head; if (pDpyEvo->apiHead == NV_INVALID_HEAD) { return; } + pApiHeadState = &pDispEvo->apiHeadState[pDpyEvo->apiHead]; - /* XXX[2Heads1OR] Broadcast dithering to the hardware heads. */ - nvSetDitheringEvo(pDpyEvo->pDispEvo, - pDpyEvo->apiHead, - pDpyEvo->requestedDithering.state, - pDpyEvo->requestedDithering.depth, - pDpyEvo->requestedDithering.mode, - &updateState); + nvAssert((pApiHeadState->hwHeadsMask) != 0x0 && + (nvDpyIdIsInDpyIdList(pDpyEvo->id, pApiHeadState->activeDpys))); + + head = nvGetPrimaryHwHead(pDispEvo, pDpyEvo->apiHead); + pixelDepth = pDispEvo->headState[head].timings.pixelDepth; +#if defined(DEBUG) + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + nvAssert(pixelDepth == pDispEvo->headState[head].timings.pixelDepth); + } +#endif + + nvChooseDitheringEvo(pConnectorEvo, + pixelDepth, + &pDpyEvo->requestedDithering, + &pApiHeadState->attributes.dithering); + + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + nvSetDitheringEvo(pDispEvo, + head, + &pApiHeadState->attributes.dithering, + &updateState); + } nvEvoUpdateAndKickOff(pDpyEvo->pDispEvo, FALSE, &updateState, TRUE /* releaseElv */); @@ -428,22 +451,29 @@ static NvBool SetDigitalVibrance(NVDpyEvoRec *pDpyEvo, NvS64 dvc) { NVEvoUpdateState updateState = { }; NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo; + NVDispApiHeadStateEvoRec *pApiHeadState; + NvU32 head; - if (!DigitalVibranceAvailable(pDpyEvo)) { + if ((pDpyEvo->apiHead == NV_INVALID_HEAD) || + !DigitalVibranceAvailable(pDpyEvo)) { return FALSE; } + pApiHeadState = &pDispEvo->apiHeadState[pDpyEvo->apiHead]; + + nvAssert((pApiHeadState->hwHeadsMask) != 0x0 && + (nvDpyIdIsInDpyIdList(pDpyEvo->id, pApiHeadState->activeDpys))); dvc = NV_MAX(dvc, NV_EVO_DVC_MIN); dvc = NV_MIN(dvc, NV_EVO_DVC_MAX); - /* XXX[2Heads1OR] Broadcast vibrance setting to the hardware heads. */ - nvSetDVCEvo(pDpyEvo->pDispEvo, - pDpyEvo->apiHead, dvc, &updateState); + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + nvSetDVCEvo(pDispEvo, head, dvc, &updateState); + } nvEvoUpdateAndKickOff(pDpyEvo->pDispEvo, FALSE, &updateState, TRUE /* releaseElv */); - pDispEvo->headState[pDpyEvo->apiHead].attributes.dvc = dvc; + pApiHeadState->attributes.dvc = dvc; return TRUE; } @@ -495,23 +525,29 @@ static NvBool SetImageSharpening(NVDpyEvoRec *pDpyEvo, NvS64 imageSharpening) { NVEvoUpdateState updateState = { }; NVDispEvoPtr pDispEvo = pDpyEvo->pDispEvo; + NVDispApiHeadStateEvoRec *pApiHeadState; + NvU32 head; - if (!ImageSharpeningAvailable(pDpyEvo)) { + if ((pDpyEvo->apiHead == NV_INVALID_HEAD) || + !ImageSharpeningAvailable(pDpyEvo)) { return FALSE; } + pApiHeadState = &pDispEvo->apiHeadState[pDpyEvo->apiHead]; + + nvAssert((pApiHeadState->hwHeadsMask) != 0x0 && + (nvDpyIdIsInDpyIdList(pDpyEvo->id, pApiHeadState->activeDpys))); imageSharpening = NV_MAX(imageSharpening, NV_EVO_IMAGE_SHARPENING_MIN); imageSharpening = NV_MIN(imageSharpening, NV_EVO_IMAGE_SHARPENING_MAX); - /* XXX[2Heads1OR] Broadcast image sharpening setting to the hardware heads */ - nvSetImageSharpeningEvo(pDispEvo, - pDpyEvo->apiHead, imageSharpening, &updateState); + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + nvSetImageSharpeningEvo(pDispEvo, head, imageSharpening, &updateState); + } nvEvoUpdateAndKickOff(pDispEvo, FALSE, &updateState, TRUE /* releaseElv */); - pDispEvo->headState[pDpyEvo->apiHead].attributes.imageSharpening.value = - imageSharpening; + pApiHeadState->attributes.imageSharpening.value = imageSharpening; return TRUE; } @@ -578,29 +614,58 @@ static NvBool ColorSpaceAndRangeAvailable(const NVDpyEvoRec *pDpyEvo) static void DpyPostColorSpaceOrRangeSetEvo(NVDpyEvoPtr pDpyEvo) { NVEvoUpdateState updateState = { }; + NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo; + NVDispApiHeadStateEvoRec *pApiHeadState; + enum nvKmsPixelDepth pixelDepth; + enum NvYuv420Mode yuv420Mode; + enum NvKmsOutputTf tf; + NvU32 head; if (pDpyEvo->apiHead == NV_INVALID_HEAD) { return; } + pApiHeadState = &pDispEvo->apiHeadState[pDpyEvo->apiHead]; + + nvAssert((pApiHeadState->hwHeadsMask) != 0x0 && + (nvDpyIdIsInDpyIdList(pDpyEvo->id, pApiHeadState->activeDpys))); + + head = nvGetPrimaryHwHead(pDispEvo, pDpyEvo->apiHead); + pixelDepth = pDispEvo->headState[head].timings.pixelDepth; + yuv420Mode = pDispEvo->headState[head].timings.yuv420Mode; + tf = pDispEvo->headState[head].tf; +#if defined(DEBUG) + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + nvAssert(pixelDepth == pDispEvo->headState[head].timings.pixelDepth); + nvAssert(yuv420Mode == pDispEvo->headState[head].timings.yuv420Mode); + } +#endif - /* XXX[2Heads1OR] Broadcast color space settings to the hardware heads. */ /* - * Recompute the current ColorSpace and ColorRange, given updated requested - * values, and program any changes in EVO hardware. + * Choose current colorSpace and colorRange based on the current mode + * timings and the requested color space and range. */ - nvSetColorSpaceAndRangeEvo( - pDpyEvo->pDispEvo, - pDpyEvo->apiHead, - pDpyEvo->requestedColorSpace, - pDpyEvo->requestedColorRange, - &updateState); + nvChooseCurrentColorSpaceAndRangeEvo(pixelDepth, + yuv420Mode, + tf, + pDpyEvo->requestedColorSpace, + pDpyEvo->requestedColorRange, + &pApiHeadState->attributes.colorSpace, + &pApiHeadState->attributes.colorRange); + + /* Update hardware's current colorSpace and colorRange */ + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + nvUpdateCurrentHardwareColorSpaceAndRangeEvo(pDispEvo, + head, + pApiHeadState->attributes.colorSpace, + pApiHeadState->attributes.colorRange, + &updateState); + } /* Update InfoFrames as needed. */ - nvUpdateInfoFrames(pDpyEvo->pDispEvo, pDpyEvo->apiHead); + nvUpdateInfoFrames(pDpyEvo); // Kick off - nvEvoUpdateAndKickOff(pDpyEvo->pDispEvo, FALSE, &updateState, - TRUE /* releaseElv */); + nvEvoUpdateAndKickOff(pDispEvo, FALSE, &updateState, TRUE /* releaseElv */); // XXX DisplayPort sets color format. } @@ -809,22 +874,22 @@ static NvBool GetDigitalLinkType(const NVDpyEvoRec *pDpyEvo, NvS64 *pValue) if (nvConnectorUsesDPLib(pDpyEvo->pConnectorEvo)) { *pValue = nvRMLaneCountToNvKms(pDpyEvo->dp.laneCount); } else { - const NVHwModeTimingsEvo *pTimings; + enum nvKmsTimingsProtocol protocol; const NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo; - /* - * XXX[2Heads1OR] Track DIGITAL_LINK_TYPE as per head - * attributes set which get mirrored into NVDpyEvoRec::attributes - * after modeset. - */ - const NvU32 head = pDpyEvo->apiHead; + NvU32 head = nvGetPrimaryHwHead(pDispEvo, pDpyEvo->apiHead); - if (head == NV_INVALID_HEAD) { - return FALSE; + nvAssert(head != NV_INVALID_HEAD); + protocol = pDispEvo->headState[head].timings.protocol; +#if defined(DEBUG) + { + NvU32 h; + FOR_EACH_EVO_HW_HEAD(pDispEvo, pDpyEvo->apiHead, h) { + nvAssert(protocol == pDispEvo->headState[h].timings.protocol); + } } +#endif - pTimings = &pDispEvo->headState[head].timings; - - *pValue = nvDpyRequiresDualLinkEvo(pDpyEvo, pTimings) ? + *pValue = (protocol == NVKMS_PROTOCOL_SOR_DUAL_TMDS) ? NV_KMS_DPY_ATTRIBUTE_DIGITAL_LINK_TYPE_DUAL : NV_KMS_DPY_ATTRIBUTE_DIGITAL_LINK_TYPE_SINGLE; } @@ -976,8 +1041,7 @@ static NvBool SetStereoEvo(NVDpyEvoPtr pDpyEvo, NvS64 value) return FALSE; } - /* XXX[2Heads1OR] Broadcast the stereo setting to the hardware heads. */ - return nvSetStereoEvo(pDpyEvo->pDispEvo, pDpyEvo->apiHead, enable); + return nvSetStereo(pDpyEvo->pDispEvo, pDpyEvo->apiHead, enable); } static NvBool GetStereoEvo(const NVDpyEvoRec *pDpyEvo, NvS64 *pValue) @@ -986,8 +1050,7 @@ static NvBool GetStereoEvo(const NVDpyEvoRec *pDpyEvo, NvS64 *pValue) return FALSE; } - /* XXX[2Heads1OR] Loop over hardware heads to determine stereo status. */ - *pValue = !!nvGetStereoEvo(pDpyEvo->pDispEvo, pDpyEvo->apiHead); + *pValue = !!nvGetStereo(pDpyEvo->pDispEvo, pDpyEvo->apiHead); return TRUE; } @@ -1211,19 +1274,15 @@ NvBool nvSetDpyAttributeEvo(NVDpyEvoPtr pDpyEvo, if (pDpyEvo->apiHead != NV_INVALID_HEAD) { NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo; + NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[pDpyEvo->apiHead]; NVDpyEvoRec *pClonedDpyEvo; /* * The current attributes state should be consistent across all cloned * dpys. - * - * XXX[2Heads1OR] Optimize this loop in follow on code change when - * apiHead -> pDpyEvo mapping will get implemented. */ - FOR_ALL_EVO_DPYS(pClonedDpyEvo, pDispEvo->validDisplays, pDispEvo) { - if (pClonedDpyEvo->apiHead != pDpyEvo->apiHead) { - continue; - } + FOR_ALL_EVO_DPYS(pClonedDpyEvo, pApiHeadState->activeDpys, pDispEvo) { nvDpyUpdateCurrentAttributes(pClonedDpyEvo); } } else { diff --git a/src/nvidia-modeset/src/nvkms-console-restore.c b/src/nvidia-modeset/src/nvkms-console-restore.c index 28e52d977..e49a1db9b 100644 --- a/src/nvidia-modeset/src/nvkms-console-restore.c +++ b/src/nvidia-modeset/src/nvkms-console-restore.c @@ -150,6 +150,15 @@ static void FlipBaseToNull(NVDevEvoPtr pDevEvo) pRequestHead->layer[layer].compositionParams.specified = TRUE; pRequestHead->layer[layer].completionNotifier.specified = TRUE; pRequestHead->layer[layer].syncObjects.specified = TRUE; + + // Disable HDR + pRequestHead->tf.val = NVKMS_OUTPUT_TF_NONE; + pRequestHead->tf.specified = TRUE; + pRequestHead->layer[layer].hdr.enabled = FALSE; + pRequestHead->layer[layer].hdr.specified = TRUE; + pRequestHead->layer[layer].colorspace.val = + NVKMS_INPUT_COLORSPACE_NONE; + pRequestHead->layer[layer].colorspace.specified = TRUE; } pRequest->commit = TRUE; diff --git a/src/nvidia-modeset/src/nvkms-cursor.c b/src/nvidia-modeset/src/nvkms-cursor.c index e5a5928d7..30467d681 100644 --- a/src/nvidia-modeset/src/nvkms-cursor.c +++ b/src/nvidia-modeset/src/nvkms-cursor.c @@ -74,7 +74,8 @@ NvBool nvGetCursorImageSurfaces( nvEvoGetSurfaceFromHandle(pDevEvo, pOpenDevSurfaceHandles, pParams->surfaceHandle[eye], - NV_EVO_CHANNEL_MASK_CURSOR_ALL); + TRUE /* isUsedByCursorChannel */, + FALSE /* isUsedByLayerChannel */); if ((pSurfaceEvo == NULL) || (pSurfaceEvo->isoType != NVKMS_MEMORY_ISO)) { return FALSE; @@ -160,12 +161,8 @@ FlipCursorImage(NVDispEvoPtr pDispEvo, pFlipRequest = &pFlipParams->request; - pFlipRequest->sd[sd].head[head] = (struct NvKmsFlipCommonParams) { - .cursor = { - .image = *pImageParams, - .imageSpecified = TRUE, - }, - }; + pFlipRequest->sd[sd].head[head].cursor.image = *pImageParams; + pFlipRequest->sd[sd].head[head].cursor.imageSpecified = TRUE; pFlipRequest->sd[sd].requestedHeadsBitMask = NVBIT(head); diff --git a/src/nvidia-modeset/src/nvkms-difr.c b/src/nvidia-modeset/src/nvkms-difr.c new file mode 100644 index 000000000..216c05b38 --- /dev/null +++ b/src/nvidia-modeset/src/nvkms-difr.c @@ -0,0 +1,725 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * DIFR stands for Display Idle Frame Refresh which is a low-power feature + * for display that allows scanning out frames from L2 cache. The actual GPU + * memory can be gated off while the display outputs are served off the + * cache. + * + * DIFR is defined in three operational layers 1, 2, and 3 and operates in + * terms of entering and exiting these layers in order. + * + * Layer 1 has to deem it's possible to enter DIFR until layer 2 and 3 can + * start considering. Any layer seeing conditions that prevent entering DIFR + * mode can abort the attempt to enter. But, finally, if all layers agree + * the hardware will switch to low-power mode, turn off GPU memory, and + * start serving pixels off the cache. + * + * Managing some high-level state to help the hardware transition from one + * layer to another is implemented in NVKMS and RM. Simplified, NVKMS + * handles assistance for layer 1 and RM for layer 2. + * + * Much of the layer 1 or NVKMS DIFR specific code is collected into this + * file, centered around an object called NVDIFRStateEvo. + * + * The role of NVKMS is to listen for DIFR prefetch events (which originate + * from h/w and get dispatched by RM), prefetch framebuffer pixels into L2 + * cache, and report back to h/w (via RM). NVKMS will also disable DIFR each + * time there's an explicitly known display update (such as a flip) and + * re-enable it once enough idle time has passed. + * + * The rest of NVKMS will call entrypoints in this file to inform the DIFR + * implementation here about changes in relevant state. + * + * For each DevEvo object nvkms-evo.c will call + * nvDIFRAllocate()/nvDIFRFree() here to also create a corresponding DIFR + * state object. The DIFR state will contain everything needed to implement + * prefetching such as channel and copy engine allocation. + * + * If DIFR state was successfully allocated, nvkms-rm.c will create an event + * listener for DIFR prefetch events which will call back to + * nvDIFRPrefetchSurfaces() here in order to do prefetching. This means + * going through each active head and issuing a special CE copy, for all + * layers of the surface, to populate the L2 cache with framebuffer pixel + * data. + * + * After all prefetches are complete, RM needs to know about the completion + * status. This is implemented in nvDIFRSendPrefetchResponse(), again called + * by nvkms-rm.c. + * + * NVKMS must also temporarily disable DIFR in hardware if it knows about + * upcoming updates to the framebuffer and then re-enable DIFR when the + * screen becomes idle again. For this, nvFlipEvoOneHead() will call us back + * via nvDIFRNotifyFlip() when a new flip is happening. We will call RM to + * disable DIFR, then set up a timer into the future and when it triggers we + * will re-enable DIFR again. But if nvFlipEvoOneHead() notifies us about + * another upcoming frame, we'll just replace the old timer with a new one. + * Thus, the timer will eventually wake us after notifications of new frames + * cease to come in. + * + * The DIFR hardware will automatically detect activity in graphics/copy + * engines and will not try to enter the low-power mode if there is any. So + * this is something NVKMS doesn't have to worry about. + * + * Userspace can also flag surfaces as non-cacheable which makes us abort + * any prefetches if those surfaces are currently displayed on any active + * heads. For now, CPU mapped surfaces are flagged as such because neither + * NVKMS nor the hardware can observe CPU writes into a surface. + */ + + + +#include "nvkms-difr.h" +#include "nvkms-push.h" +#include "nvkms-rm.h" +#include "nvkms-rmapi.h" +#include "nvkms-utils.h" + +#include "nvidia-push-init.h" +#include "nvidia-push-methods.h" +#include "nvidia-push-types.h" +#include "nvidia-push-types.h" +#include "nvidia-push-utils.h" + +#include +#include +#include +#include +#include +#include +#include +#include + +#define PREFETCH_DONE_VALUE 0x00000fed + +/* How long to wait after last flip until re-enabling DIFR. */ +#define DIFR_IDLE_WAIT_PERIOD_US 500000 + +/* How long to wait for prefetch dma completion. */ +#define DIFR_PREFETCH_WAIT_PERIOD_US 10000 /* 10ms */ + +/* + * DIFR runtime state + */ +typedef struct _NVDIFRStateEvoRec { + NVDevEvoPtr pDevEvo; + NvU32 copyEngineType; + + /* + * This is kept in sync with whether DIFR is explicitly disabled in + * hardware. + */ + NvBool hwDisabled; + NvU64 lastFlipTime; + nvkms_timer_handle_t *idleTimer; + + /* Pushbuffer for DIFR prefetches. */ + NvPushChannelRec prefetchPushChannel; + NvU32 pushChannelHandlePool[NV_PUSH_CHANNEL_HANDLE_POOL_NUM]; + + /* Copy engine instance for DIFR prefetches. */ + NvU32 prefetchEngine; + + /* For tracking which surfaces have been prefetched already. */ + NvU32 prefetchPass; +} NVDIFRStateEvoRec; + +static NvBool AllocDIFRPushChannel(NVDIFRStateEvoPtr pDifr); +static void FreeDIFRPushChannel(NVDIFRStateEvoPtr pDifr); +static NvBool AllocDIFRCopyEngine(NVDIFRStateEvoPtr pDifr); +static void FreeDIFRCopyEngine(NVDIFRStateEvoPtr pDifr); +static NvU32 PrefetchSingleSurface(NVDIFRStateEvoPtr pDifr, + NVSurfaceEvoPtr pSurfaceEvo, + size_t *remainingCache); + +static NvBool SetDisabledState(NVDIFRStateEvoPtr pDifr, + NvBool shouldDisable); +static NvBool IsCECompatibleWithDIFR(NVDevEvoPtr pDevEvo, + NvU32 instance); +static void EnsureIdleTimer(NVDIFRStateEvoPtr pDifr); +static void IdleTimerProc(void *dataPtr, NvU32 dataU32); + +/* + * Public entry points. + */ + +NVDIFRStateEvoPtr nvDIFRAllocate(NVDevEvoPtr pDevEvo) +{ + NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS params = { 0 }; + NVDIFRStateEvoPtr pDifr; + NvU32 ret; + + /* DIFR not supported/implemented on RM SLI */ + if (pDevEvo->numSubDevices > 1) { + return NULL; + } + + params.ctrlParamVal = NV2080_CTRL_LPWR_DIFR_CTRL_SUPPORT_STATUS; + ret = nvRmApiControl(nvEvoGlobal.clientHandle, + pDevEvo->pSubDevices[0]->handle, + NV2080_CTRL_CMD_LPWR_DIFR_CTRL, + ¶ms, + sizeof(params)); + + if (ret != NV_OK) { + nvEvoLogDev(pDevEvo, + EVO_LOG_WARN, + "unable to query whether display caching is supported"); + return NULL; + } + + if (params.ctrlParamVal != NV2080_CTRL_LPWR_DIFR_SUPPORTED) { + return NULL; + } + + pDifr = nvCalloc(sizeof(*pDifr), 1); + if (!pDifr) { + return NULL; + } + + pDifr->pDevEvo = pDevEvo; + + if (!AllocDIFRPushChannel(pDifr) || + !AllocDIFRCopyEngine(pDifr)) { + nvDIFRFree(pDifr); + + return NULL; + } + + return pDifr; +} + +void nvDIFRFree(NVDIFRStateEvoPtr pDifr) +{ + nvAssert(pDifr); + + /* Cancel pending idle timer. */ + nvkms_free_timer(pDifr->idleTimer); + + /* Leave DIFR enabled (default state). */ + SetDisabledState(pDifr, FALSE); + + /* Free resources. */ + FreeDIFRCopyEngine(pDifr); + FreeDIFRPushChannel(pDifr); + + nvFree(pDifr); +} + +/* + * Notify of a new or upcoming flip. This will disable DIFR for a brief + * period in anticipation of further flips. + */ +void nvDIFRNotifyFlip(NVDIFRStateEvoPtr pDifr) +{ + pDifr->lastFlipTime = nvkms_get_usec(); + + /* A flip is coming: signal RM to disable DIFR if we haven't already. */ + if (SetDisabledState(pDifr, TRUE)) { + /* Check back after a while and re-enable if idle again. */ + EnsureIdleTimer(pDifr); + } +} + +NvU32 nvDIFRPrefetchSurfaces(NVDIFRStateEvoPtr pDifr, size_t l2CacheSize) +{ + NVDevEvoPtr pDevEvo = pDifr->pDevEvo; + NVEvoSubDevPtr pSubDev; + NVEvoSubDevHeadStatePtr pHeadState; + NVSurfaceEvoPtr pSurface; + size_t cacheRemaining = l2CacheSize; + NvU32 layer; + NvU32 head; + NvU32 eye; + NvU32 status; + + /* If DIFR is disabled it's because we know we were or will be flipping. */ + if (pDifr->hwDisabled) { + return NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_OS_FLIPS_ENABLED; + } + + status = NV2080_CTRL_LPWR_DIFR_PREFETCH_SUCCESS; + + pSubDev = &pDevEvo->gpus[0]; + + /* Get new prefetch pass counter for this iteration. */ + pDifr->prefetchPass++; + + for (head = 0; head < pDevEvo->numHeads; head++) { + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + for (eye = 0; eye < NVKMS_MAX_EYES; eye++) { + NvU32 prefetchStatus; + + pHeadState = &pSubDev->headState[head]; + pSurface = pHeadState->layer[layer].pSurfaceEvo[eye]; + + if (!pSurface) { + continue; + } + + if (pSurface->noDisplayCaching) { + status = + NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_OS_FLIPS_ENABLED; + break; + } + + /* + * If we see the same pSurface twice (UBB, multi-head X + * screens, etc) we only ever want to prefetch it once + * within a single nvDIFRPrefetchSurfaces() call. + */ + if (pSurface->difrLastPrefetchPass == pDifr->prefetchPass) { + continue; + } + + pSurface->difrLastPrefetchPass = pDifr->prefetchPass; + prefetchStatus = PrefetchSingleSurface(pDevEvo->pDifrState, + pSurface, + &cacheRemaining); + if (prefetchStatus != NV2080_CTRL_LPWR_DIFR_PREFETCH_SUCCESS) { + status = prefetchStatus; + break; + } + } + } + } + + return status; +} + +NvBool nvDIFRSendPrefetchResponse(NVDIFRStateEvoPtr pDifr, NvU32 responseStatus) +{ + NVDevEvoPtr pDevEvo = pDifr->pDevEvo; + NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS params = { 0 }; + + params.responseVal = responseStatus; + + return (nvRmApiControl(nvEvoGlobal.clientHandle, + pDevEvo->pSubDevices[0]->handle, + NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE, + ¶ms, + sizeof(params)) + == NV_OK); +} + +/* + * Local helper functions. + */ +static NvBool AllocDIFRPushChannel(NVDIFRStateEvoPtr pDifr) +{ + NVDevEvoPtr pDevEvo = pDifr->pDevEvo; + NvPushAllocChannelParams params = { 0 }; + NvU32 i; + + pDifr->copyEngineType = NV2080_ENGINE_TYPE_NULL; + + for (i = 0; i < NV2080_ENGINE_TYPE_COPY_SIZE; i++) { + if (IsCECompatibleWithDIFR(pDevEvo, i)) { + pDifr->copyEngineType = NV2080_ENGINE_TYPE_COPY(i); + break; + } + } + + if (pDifr->copyEngineType == NV2080_ENGINE_TYPE_NULL) { + return FALSE; + } + + params.engineType = pDifr->copyEngineType; + params.pDevice = &pDifr->pDevEvo->nvPush.device; + params.difrPrefetch = TRUE; + params.logNvDiss = FALSE; + params.noTimeout = FALSE; + params.ignoreChannelErrors = FALSE; + params.numNotifiers = 1; + params.pushBufferSizeInBytes = 1024; + + ct_assert(sizeof(params.handlePool) == sizeof(pDifr->pushChannelHandlePool)); + + for (i = 0; i < ARRAY_LEN(pDifr->pushChannelHandlePool); i++) { + pDifr->pushChannelHandlePool[i] = + nvGenerateUnixRmHandle(&pDevEvo->handleAllocator); + + params.handlePool[i] = pDifr->pushChannelHandlePool[i]; + } + + if (!nvPushAllocChannel(¶ms, &pDifr->prefetchPushChannel)) { + return FALSE; + } + + return TRUE; +} + +static void FreeDIFRPushChannel(NVDIFRStateEvoPtr pDifr) +{ + NVDevEvoPtr pDevEvo = pDifr->pDevEvo; + NvU32 i; + + nvPushFreeChannel(&pDifr->prefetchPushChannel); + + for (i = 0; i < ARRAY_LEN(pDifr->pushChannelHandlePool); i++) { + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, + pDifr->pushChannelHandlePool[i]); + pDifr->pushChannelHandlePool[i] = 0; + } +} + +static NvBool AllocDIFRCopyEngine(NVDIFRStateEvoPtr pDifr) +{ + NVB0B5_ALLOCATION_PARAMETERS allocParams = { 0 }; + NVDevEvoPtr pDevEvo = pDifr->pDevEvo; + NvU32 ret; + + /* + * We will only be called if NV2080_CTRL_CMD_LPWR_DIFR_CTRL says DIFR is + * supported in which case we assume the chip supports this CE class. + */ + nvAssert(nvRmEvoClassListCheck(pDevEvo, AMPERE_DMA_COPY_B)); + + pDifr->prefetchEngine = nvGenerateUnixRmHandle(&pDevEvo->handleAllocator); + if (pDifr->prefetchEngine == 0) { + return NV_FALSE; + } + + allocParams.version = NVB0B5_ALLOCATION_PARAMETERS_VERSION_1; + allocParams.engineType = pDifr->copyEngineType; + + ret = nvRmApiAlloc(nvEvoGlobal.clientHandle, + pDifr->prefetchPushChannel.channelHandle[0], + pDifr->prefetchEngine, + AMPERE_DMA_COPY_B, + &allocParams); + if (ret != NVOS_STATUS_SUCCESS) { + return NV_FALSE; + } + + return NV_TRUE; +} + +static void FreeDIFRCopyEngine(NVDIFRStateEvoPtr pDifr) +{ + if (pDifr->prefetchEngine != 0) { + nvRmApiFree(nvEvoGlobal.clientHandle, + pDifr->pDevEvo->pSubDevices[0]->handle, + pDifr->prefetchEngine); + } + + nvFreeUnixRmHandle(&pDifr->pDevEvo->handleAllocator, + pDifr->prefetchEngine); +} + +static NvU32 PrefetchSingleSurface(NVDIFRStateEvoPtr pDifr, + NVSurfaceEvoPtr pSurfaceEvo, + size_t *cacheRemaining) +{ + NvPushChannelPtr p = &pDifr->prefetchPushChannel; + NvU64 semaphoreGPUAddress = nvPushGetNotifierGpuAddress(p, 0, 0); + NvGpuSemaphore *semaphore = (NvGpuSemaphore *) + nvPushGetNotifierCpuAddress(p, 0, 0); + const NvKmsSurfaceMemoryFormatInfo *finfo = + nvKmsGetSurfaceMemoryFormatInfo(pSurfaceEvo->format); + NvU32 componentSizes; + NvU32 pitch; + NvU32 line_length_in; + NvU32 line_count; + size_t surfaceSize; + NvU64 starttime; + NvU64 endtime; + + /* + * Tell SET_REMAP_COMPONENTS the byte-size of a pixel in terms of color + * component size and count. It doesn't matter which actual combinations we + * choose as long as size*count will be equal to bytesPerPixel. This is + * because we won't be doing any actual remapping per se: we will just + * effectively tell the prefetch operation to fetch the correct amount of + * bytes for each pixel. + */ + switch (finfo->rgb.bytesPerPixel) { +#define COMPONENTS(size, num) \ + (DRF_DEF(A0B5, _SET_REMAP_COMPONENTS, _COMPONENT_SIZE, size) | \ + DRF_DEF(A0B5, _SET_REMAP_COMPONENTS, _NUM_SRC_COMPONENTS, num) | \ + DRF_DEF(A0B5, _SET_REMAP_COMPONENTS, _NUM_DST_COMPONENTS, num)) + + case 1: componentSizes = COMPONENTS(_ONE, _ONE); break; + case 2: componentSizes = COMPONENTS(_ONE, _TWO); break; + case 3: componentSizes = COMPONENTS(_ONE, _THREE); break; + case 4: componentSizes = COMPONENTS(_ONE, _FOUR); break; + case 6: componentSizes = COMPONENTS(_TWO, _THREE); break; + case 8: componentSizes = COMPONENTS(_TWO, _FOUR); break; + case 12: componentSizes = COMPONENTS(_FOUR, _THREE); break; + case 16: componentSizes = COMPONENTS(_FOUR, _FOUR); break; + default: componentSizes = 0; break; +#undef COMPONENTS + } + + /* + * TODO: For now, we don't prefetch multiplane surfaces. In order to do so + * we'd need to loop over all valid planes of the pSurfaceEvo and issue a + * prefetch for each plane. + */ + if (finfo->numPlanes > 1) { + /* + * Regardless of its wording, this is the proper failure code to send + * upstream. This lets the RM disable DIFR until the next modeset. + */ + return NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_INSUFFICIENT_L2_SIZE; + } + + /* + * Compute some dimensional values to obtain correct blob size for + * prefetching. + */ + pitch = pSurfaceEvo->planes[0].pitch; + line_length_in = pSurfaceEvo->widthInPixels; + line_count = pSurfaceEvo->heightInPixels; + + if (pSurfaceEvo->layout == NvKmsSurfaceMemoryLayoutBlockLinear) { + pitch *= NVKMS_BLOCK_LINEAR_GOB_WIDTH; + } + + surfaceSize = pitch * line_count; + + /* + * Greedy strategy: assume all surfaces will fit in the supplied L2 size but + * the first one that doesn't will cause the prefetch request to fail. If we + * run out of cache then DIFR will disable itself until the next modeset. + */ + if (*cacheRemaining < surfaceSize) { + return NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_INSUFFICIENT_L2_SIZE; + } + + /* + * TODO: we should probably round up to the nearest cacheline size or maybe + * up to pSurfaceEvo->planes[0].rmObjectSizeInBytes, if greater? + * + * Using the total size of the surface pixel data (in bytes) seems to work + * but surface allocations can be larger than that and I'm not sure if DIFR + * needs only surfaceSize bytes in the cache or if the h/w will end up + * reading some non-visible alignment/padding areas as well. + */ + *cacheRemaining -= surfaceSize; + + /* + * Push buffer DMA copy and semaphore programming. + */ + nvPushSetObject(p, NVA06F_SUBCHANNEL_COPY_ENGINE, &pDifr->prefetchEngine); + nvPushMethod(p, NVA06F_SUBCHANNEL_COPY_ENGINE, + NVA0B5_SET_REMAP_COMPONENTS, 1); + nvPushSetMethodData(p, + componentSizes | + DRF_DEF(A0B5, _SET_REMAP_COMPONENTS, _DST_X, _CONST_A) | + DRF_DEF(A0B5, _SET_REMAP_COMPONENTS, _DST_Y, _CONST_A) | + DRF_DEF(A0B5, _SET_REMAP_COMPONENTS, _DST_Z, _CONST_A) | + DRF_DEF(A0B5, _SET_REMAP_COMPONENTS, _DST_W, _CONST_A)); + nvPushImmedVal(p, NVA06F_SUBCHANNEL_COPY_ENGINE, + NVA0B5_SET_REMAP_CONST_A, 0); + nvPushMethod(p, NVA06F_SUBCHANNEL_COPY_ENGINE, NVA0B5_OFFSET_IN_UPPER, 2); + nvPushSetMethodDataU64(p, pSurfaceEvo->gpuAddress); + nvPushMethod(p, NVA06F_SUBCHANNEL_COPY_ENGINE, NVA0B5_OFFSET_OUT_UPPER, 2); + nvPushSetMethodDataU64(p, pSurfaceEvo->gpuAddress); + nvPushMethod(p, NVA06F_SUBCHANNEL_COPY_ENGINE, NVA0B5_PITCH_IN, 1); + nvPushSetMethodData(p, pitch); + nvPushMethod(p, NVA06F_SUBCHANNEL_COPY_ENGINE, NVA0B5_PITCH_OUT, 1); + nvPushSetMethodData(p, pitch); + + nvPushMethod(p, NVA06F_SUBCHANNEL_COPY_ENGINE, NVA0B5_LINE_LENGTH_IN, 1); + nvPushSetMethodData(p, line_length_in); + nvPushMethod(p, NVA06F_SUBCHANNEL_COPY_ENGINE, NVA0B5_LINE_COUNT, 1); + nvPushSetMethodData(p, line_count); + + nvPushMethod(p, NVA06F_SUBCHANNEL_COPY_ENGINE, NVA0B5_LAUNCH_DMA, 1); + nvPushSetMethodData + (p, + DRF_DEF(A0B5, _LAUNCH_DMA, _DATA_TRANSFER_TYPE, _PIPELINED) | + DRF_DEF(A0B5, _LAUNCH_DMA, _FLUSH_ENABLE, _TRUE) | + DRF_DEF(A0B5, _LAUNCH_DMA, _SEMAPHORE_TYPE, _NONE) | + DRF_DEF(A0B5, _LAUNCH_DMA, _INTERRUPT_TYPE, _NONE) | + DRF_DEF(A0B5, _LAUNCH_DMA, _REMAP_ENABLE, _TRUE) | + DRF_DEF(A0B5, _LAUNCH_DMA, _SRC_MEMORY_LAYOUT, _PITCH) | + DRF_DEF(A0B5, _LAUNCH_DMA, _DST_MEMORY_LAYOUT, _PITCH) | + DRF_DEF(A0B5, _LAUNCH_DMA, _MULTI_LINE_ENABLE, _TRUE) | + DRF_DEF(A0B5, _LAUNCH_DMA, _SRC_TYPE, _VIRTUAL) | + DRF_DEF(A0B5, _LAUNCH_DMA, _DST_TYPE, _VIRTUAL)); + + /* + * Reset semaphore value. A memory barrier will be issued by nvidia-push so + * we don't need one here. + */ + semaphore->data[0] = 0; + + /* Program a semaphore release after prefetch DMA copy. */ + nvPushMethod(p, 0, NVA06F_SEMAPHOREA, 4); + nvPushSetMethodDataU64(p, semaphoreGPUAddress); + nvPushSetMethodData(p, PREFETCH_DONE_VALUE); + nvPushSetMethodData(p, + DRF_DEF(A06F, _SEMAPHORED, _OPERATION, _RELEASE) | + DRF_DEF(A06F, _SEMAPHORED, _RELEASE_WFI, _EN) | + DRF_DEF(A06F, _SEMAPHORED, _RELEASE_SIZE, _4BYTE)); + nvPushKickoff(p); + + /* + * Errors and prefetch faults are handled as follows. If prefetch + * succeeds the semaphore release will trigger and we will exit upon + * seeing PREFETCH_DONE_VALUE in the memory location. Upon failure we + * will end up timing out, signal RM of the CE fault and DIFR will + * remain disabled until next driver load. + * + * Currently the total launch-to-end effective (with scheduling) + * prefetch rate on silicon seems to be around 15k pixels per + * microsecond, empirically. Thus, the time will range from a couple of + * hundred microseconds for a very small panel to slightly less than 2 + * milliseconds for a single 4k display. We'll wait for 100us at a time + * and expect a realistic completion within few milliseconds at most. + */ + starttime = nvkms_get_usec(); + do { + endtime = nvkms_get_usec(); + + if (semaphore->data[0] == PREFETCH_DONE_VALUE) { + return NV2080_CTRL_LPWR_DIFR_PREFETCH_SUCCESS; + } + + nvkms_usleep(100); + } while (endtime - starttime < DIFR_PREFETCH_WAIT_PERIOD_US); /* 10ms */ + + return NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_CE_HW_ERROR; +} + +/* + * Set DIFR disabled state in H/W. Return true if state was changed and it + * was successfully signalled downstream. + */ +static NvBool SetDisabledState(NVDIFRStateEvoPtr pDifr, + NvBool shouldDisable) +{ + NVDevEvoPtr pDevEvo = pDifr->pDevEvo; + NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS params = { 0 }; + NvU32 ret; + + if (shouldDisable == pDifr->hwDisabled) { + return TRUE; + } + + params.ctrlParamVal = shouldDisable + ? NV2080_CTRL_LPWR_DIFR_CTRL_DISABLE + : NV2080_CTRL_LPWR_DIFR_CTRL_ENABLE; + + ret = nvRmApiControl(nvEvoGlobal.clientHandle, + pDevEvo->pSubDevices[0]->handle, + NV2080_CTRL_CMD_LPWR_DIFR_CTRL, + ¶ms, + sizeof(params)); + + if (ret != NV_OK) { + return FALSE; + } + + pDifr->hwDisabled = shouldDisable; + + return TRUE; +} + +static NvBool IsCECompatibleWithDIFR(NVDevEvoPtr pDevEvo, NvU32 instance) +{ + NV2080_CTRL_CE_GET_CAPS_V2_PARAMS params; + NvU32 ret; + + nvkms_memset(¶ms, 0, sizeof(params)); + params.ceEngineType = NV2080_ENGINE_TYPE_COPY(instance); + + ret = nvRmApiControl(nvEvoGlobal.clientHandle, + pDevEvo->pSubDevices[0]->handle, + NV2080_CTRL_CMD_CE_GET_CAPS_V2, + ¶ms, + sizeof(params)); + + if (ret != NVOS_STATUS_SUCCESS) { + return FALSE; + } + + ct_assert(sizeof(params.capsTbl) == NV2080_CTRL_CE_CAPS_TBL_SIZE); + + /* Current criteria: DIFR prefetches can't use graphics CEs. */ + if (NV2080_CTRL_CE_GET_CAP(params.capsTbl, NV2080_CTRL_CE_CAPS_CE_GRCE)) { + return FALSE; + } + + return TRUE; +} + +/* + * Make sure we have a pending idle timer to check back on idleness. + */ +static void EnsureIdleTimer(NVDIFRStateEvoPtr pDifr) +{ + if (!pDifr->idleTimer) { + /* Wait 100x longer in emulation. */ + NvU64 idlePeriod = + DIFR_IDLE_WAIT_PERIOD_US * + (nvIsEmulationEvo(pDifr->pDevEvo) ? 100 : 1); + + pDifr->idleTimer = + nvkms_alloc_timer(IdleTimerProc, pDifr, 0, idlePeriod); + } +} + +/* + * An idle timer should always remain pending after a flip until further + * flips cease and DIFR can be re-enabled. + * + * Currently we'll try to re-enable DIFR after a constant period of idleness + * since the last flip but this could resonate badly with a client that's + * rendering at the same pace. + * + * To avoid churn we could track the time DIFR actually did remain enabled. + * If the enabled-period is relatively short against the disabled-period, we + * should bump the timeout to re-enable so that we won't be retrying all the + * time. Conversely, we should reset the bumped timeout after we actually + * managed to sleep long enough with DIFR enabled. + * + * Note: There's the question of whether we should apply slight hysteresis + * within NVKMS regarding enabling/disabling DIFR. The hardware itself does + * some churn-limiting and practical observations show that it seems to work + * sufficiently and I've not observed rapid, repeating prefetch requests. + * Keeping this note here in case this matter needs to be revisited later. + */ +static void IdleTimerProc(void *dataPtr, NvU32 dataU32) +{ + NVDIFRStateEvoPtr pDifr = (NVDIFRStateEvoPtr)dataPtr; + NvU64 now = nvkms_get_usec(); + NvU64 idlePeriod = + DIFR_IDLE_WAIT_PERIOD_US * + (nvIsEmulationEvo(pDifr->pDevEvo) ? 100 : 1); + + /* First free the timer that triggered us. */ + nvkms_free_timer(pDifr->idleTimer); + pDifr->idleTimer = NULL; + + if (now - pDifr->lastFlipTime >= idlePeriod) { + /* Enough time has passed with no new flips, enable DIFR. */ + SetDisabledState(pDifr, FALSE); + } else { + /* New flips have happened since the original, reset idle timer. */ + EnsureIdleTimer(pDifr); + } +} diff --git a/src/nvidia-modeset/src/nvkms-dma.c b/src/nvidia-modeset/src/nvkms-dma.c index c6a3c1f14..efa9e24ae 100644 --- a/src/nvidia-modeset/src/nvkms-dma.c +++ b/src/nvidia-modeset/src/nvkms-dma.c @@ -157,6 +157,26 @@ static NvU32 EvoReadGetOffset(NVDmaBufferEvoPtr push_buffer, NvBool minimum) return bestGet; } +NvBool nvEvoPollForEmptyChannel(NVEvoChannelPtr pChannel, NvU32 sd, + NvU64 *pStartTime, const NvU32 timeout) +{ + NVDmaBufferEvoPtr push_buffer = &pChannel->pb; + + do { + if (EvoCoreReadGet(push_buffer, sd) == push_buffer->put_offset) { + break; + } + + if (nvExceedsTimeoutUSec(pStartTime, timeout)) { + return FALSE; + } + + nvkms_yield(); + } while (TRUE); + + return TRUE; +} + void nvEvoMakeRoom(NVEvoChannelPtr pChannel, NvU32 count) { NVDmaBufferEvoPtr push_buffer = &pChannel->pb; diff --git a/src/nvidia-modeset/src/nvkms-dpy.c b/src/nvidia-modeset/src/nvkms-dpy.c index a41263c5d..b5a71ae6a 100644 --- a/src/nvidia-modeset/src/nvkms-dpy.c +++ b/src/nvidia-modeset/src/nvkms-dpy.c @@ -42,6 +42,9 @@ #include "nvos.h" #include "timing/dpsdp.h" +#include "displayport/displayport.h" + +#include // NV0073_CTRL_DFP_FLAGS_* #include // NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_* #define TMDS_SINGLE_LINK_PCLK_MAX 165000 @@ -118,10 +121,7 @@ static NvBool DpyConnectEvo( ReadAndApplyEdidEvo(pDpyEvo, pParams); } - if (pDpyEvo->apiHead != NV_INVALID_HEAD) { - /* XXX[2Heads1OR] Info frames should get programmed onky for the primary head. */ - nvUpdateInfoFrames(pDpyEvo->pDispEvo, pDpyEvo->apiHead); - } + nvUpdateInfoFrames(pDpyEvo); return TRUE; } @@ -467,23 +467,50 @@ static NvBool ReadDPSerializerTimings( NVT_TIMING *pTimings, NvU8 *pBpc) { - /* - * TODO Add RM control call that will return the fixed timings - * and bpc that can be used with a given display. - */ - pTimings->HVisible = 1920; - pTimings->VVisible = 1080; - pTimings->HFrontPorch = 88; - pTimings->VFrontPorch = 4; - pTimings->HSyncWidth = 44; - pTimings->VSyncWidth = 5; - pTimings->HTotal = 2200; - pTimings->VTotal = 1125; - pTimings->HSyncPol = 0; - pTimings->VSyncPol = 0; - pTimings->interlaced = 0; - pTimings->pclk = 14850; - pTimings->etc.rrx1k = 60000; + NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS timingParams = { }; + NVDispEvoPtr pDispEvo = pDpyEvo->pDispEvo; + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NvU32 ret; + + timingParams.subDeviceInstance = pDispEvo->displayOwner; + timingParams.displayId = nvDpyIdToNvU32(pDpyEvo->pConnectorEvo->displayId); + timingParams.stream = pDpyEvo->dp.serializerStreamIndex; + + ret = nvRmApiControl(nvEvoGlobal.clientHandle, + pDevEvo->displayCommonHandle, + NV0073_CTRL_CMD_DFP_GET_FIXED_MODE_TIMING, + &timingParams, sizeof(timingParams)); + if (ret != NVOS_STATUS_SUCCESS) { + nvEvoLogDisp(pDispEvo, EVO_LOG_WARN, + "Unable to read fixed mode timings for display device %s", + pDpyEvo->name); + return FALSE; + } + + if (!timingParams.valid) { + nvEvoLogDisp(pDispEvo, EVO_LOG_WARN, + "Fixed mode timings are invalid for display device %s", + pDpyEvo->name); + return FALSE; + } + + nvkms_memset(pTimings, 0, sizeof(NVT_TIMING)); + + pTimings->HVisible = timingParams.hActive; + pTimings->HFrontPorch = timingParams.hFrontPorch; + pTimings->HSyncWidth = timingParams.hSyncWidth; + pTimings->HTotal = timingParams.hActive + timingParams.hFrontPorch + + timingParams.hSyncWidth + timingParams.hBackPorch; + + pTimings->VVisible = timingParams.vActive; + pTimings->VFrontPorch = timingParams.vFrontPorch; + pTimings->VSyncWidth = timingParams.vSyncWidth; + pTimings->VTotal = timingParams.vActive + timingParams.vFrontPorch + + timingParams.vSyncWidth + timingParams.vBackPorch; + + pTimings->pclk = timingParams.pclkKHz / 10; + pTimings->etc.rrx1k = timingParams.rrx1k; + *pBpc = 0; return TRUE; @@ -2305,11 +2332,105 @@ NVConnectorEvoPtr nvGetConnectorFromDisp(NVDispEvoPtr pDispEvo, NVDpyId dpyId) return NULL; } +static const NVT_HDR_INFOFRAME_PAYLOAD NV_SDR_PAYLOAD = +{ + .eotf = NVT_CEA861_HDR_INFOFRAME_EOTF_SDR_GAMMA, + .static_metadata_desc_id = NVT_CEA861_STATIC_METADATA_SM0 + // type1 is empty - no metadata +}; + +static void UpdateDpHDRInfoFrame(const NVDispEvoRec *pDispEvo, const NvU32 head) +{ + NvU32 ret; + const NVDispHeadStateEvoRec *pHeadState = + &pDispEvo->headState[head]; + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + + NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS params = { + .subDeviceInstance = pDispEvo->displayOwner, + .displayId = pHeadState->activeRmId + }; + + // DPSDP_DESCRIPTOR has a (dataSize, hb, db) layout, while + // NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS.aPacket needs to contain + // (hb, db) without dataSize, so this makes sdp->hb align with aPacket. + DPSDP_DESCRIPTOR *sdp = + (DPSDP_DESCRIPTOR *)(params.aPacket - + offsetof(DPSDP_DESCRIPTOR, hb)); + + nvAssert((void *)&sdp->hb == (void *)params.aPacket); + + sdp->hb.hb0 = 0; + sdp->hb.hb1 = dp_pktType_DynamicRangeMasteringInfoFrame; + sdp->hb.hb2 = DP_INFOFRAME_SDP_V1_3_NON_AUDIO_SIZE - 1; + sdp->hb.hb3 = DP_INFOFRAME_SDP_V1_3_VERSION << + DP_INFOFRAME_SDP_V1_3_HB3_VERSION_SHIFT; + + sdp->db.db0 = NVT_VIDEO_INFOFRAME_VERSION_1; + sdp->db.db1 = sizeof(NVT_HDR_INFOFRAME) - sizeof(NVT_INFOFRAME_HEADER); + + nvAssert((sizeof(sdp->db) - 2) >= sizeof(NVT_HDR_INFOFRAME_PAYLOAD)); + + if (pHeadState->hdr.outputState == NVKMS_HDR_OUTPUT_STATE_HDR) { + NVT_HDR_INFOFRAME_PAYLOAD *payload = + (NVT_HDR_INFOFRAME_PAYLOAD *) &sdp->db.db2; + + // XXX HDR TODO: Support EOTFs other than PQ. + nvAssert(pHeadState->tf == NVKMS_OUTPUT_TF_PQ); + payload->eotf = NVT_CEA861_HDR_INFOFRAME_EOTF_ST2084; + + payload->static_metadata_desc_id = NVT_CEA861_STATIC_METADATA_SM0; + + // payload->type1 = static metadata + nvAssert(sizeof(NVT_HDR_INFOFRAME_MASTERING_DATA) == + (sizeof(struct NvKmsHDRStaticMetadata))); + nvkms_memcpy(&payload->type1, + &pHeadState->hdr.staticMetadata, + sizeof(NVT_HDR_INFOFRAME_MASTERING_DATA)); + + params.transmitControl = + DRF_DEF(0073_CTRL_SPECIFIC, _SET_OD_PACKET_TRANSMIT_CONTROL, _SINGLE_FRAME, _DISABLE); + } else if (pHeadState->hdr.outputState == + NVKMS_HDR_OUTPUT_STATE_TRANSITIONING_TO_SDR) { + nvkms_memcpy(&sdp->db.db2, &NV_SDR_PAYLOAD, sizeof(NVT_HDR_INFOFRAME_PAYLOAD)); + + params.transmitControl = + DRF_DEF(0073_CTRL_SPECIFIC, _SET_OD_PACKET_TRANSMIT_CONTROL, _SINGLE_FRAME, _DISABLE); + } else { + nvAssert(pHeadState->hdr.outputState == NVKMS_HDR_OUTPUT_STATE_SDR); + + nvkms_memcpy(&sdp->db.db2, &NV_SDR_PAYLOAD, sizeof(NVT_HDR_INFOFRAME_PAYLOAD)); + + params.transmitControl = + DRF_DEF(0073_CTRL_SPECIFIC, _SET_OD_PACKET_TRANSMIT_CONTROL, _SINGLE_FRAME, _ENABLE); + } + + params.transmitControl |= + DRF_DEF(0073_CTRL_SPECIFIC, _SET_OD_PACKET_TRANSMIT_CONTROL, _OTHER_FRAME, _DISABLE) | + DRF_DEF(0073_CTRL_SPECIFIC, _SET_OD_PACKET_TRANSMIT_CONTROL, _ENABLE, _YES) | + DRF_DEF(0073_CTRL_SPECIFIC, _SET_OD_PACKET_TRANSMIT_CONTROL, _GEN_INFOFRAME_MODE, _INFOFRAME1) | + DRF_DEF(0073_CTRL_SPECIFIC, _SET_OD_PACKET_TRANSMIT_CONTROL, _ON_HBLANK, _DISABLE); + + params.packetSize = sizeof(sdp->hb) + sizeof(NVT_HDR_INFOFRAME); + + ret = nvRmApiControl(nvEvoGlobal.clientHandle, + pDevEvo->displayCommonHandle, + NV0073_CTRL_CMD_SPECIFIC_SET_OD_PACKET, + ¶ms, + sizeof(params)); + + if (ret != NVOS_STATUS_SUCCESS) { + nvAssert(!"NV0073_CTRL_CMD_SPECIFIC_SET_OD_PACKET failed"); + } +} + /* * Construct the DP 1.3 YUV420 infoframe, and toggle it on or off based on * whether or not YUV420 mode is in use. */ -static void UpdateDpInfoFrames(const NVDispEvoRec *pDispEvo, const NvU32 head) +static void UpdateDpYUV420InfoFrame(const NVDispEvoRec *pDispEvo, + const NvU32 head, + const NVAttributesSetEvoRec *pAttributesSet) { const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; @@ -2321,7 +2442,7 @@ static void UpdateDpInfoFrames(const NVDispEvoRec *pDispEvo, const NvU32 head) params.subDeviceInstance = pDispEvo->displayOwner; params.displayId = pHeadState->activeRmId; - if (pHeadState->attributes.colorSpace == + if (pAttributesSet->colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420) { // DPSDP_DP_VSC_SDP_DESCRIPTOR has a (dataSize, hb, db) layout, while @@ -2358,7 +2479,7 @@ static void UpdateDpInfoFrames(const NVDispEvoRec *pDispEvo, const NvU32 head) break; } - switch (pHeadState->attributes.colorRange) { + switch (pAttributesSet->colorRange) { case NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_FULL: sdp->db.dynamicRange = SDP_VSC_DYNAMIC_RANGE_VESA; break; @@ -2393,25 +2514,40 @@ static void UpdateDpInfoFrames(const NVDispEvoRec *pDispEvo, const NvU32 head) } } -void nvUpdateInfoFrames(const NVDispEvoRec *pDispEvo, const NvU32 head) +static void UpdateDpInfoFrames(const NVDispEvoRec *pDispEvo, + const NvU32 head, + const NVAttributesSetEvoRec *pAttributesSet) { - const NVDispHeadStateEvoRec *pHeadState = - &pDispEvo->headState[head]; - NVDpyEvoRec *pDpyEvo = - nvGetOneArbitraryDpyEvo(pHeadState->activeDpys, pDispEvo); + UpdateDpHDRInfoFrame(pDispEvo, head); - if (pDpyEvo == NULL) { + UpdateDpYUV420InfoFrame(pDispEvo, head, pAttributesSet); +} + +void nvUpdateInfoFrames(NVDpyEvoRec *pDpyEvo) +{ + const NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo; + const NVDispApiHeadStateEvoRec *pApiHeadState; + NvU32 head; + + if (pDpyEvo->apiHead == NV_INVALID_HEAD) { return; } + pApiHeadState = &pDispEvo->apiHeadState[pDpyEvo->apiHead]; + + nvAssert((pApiHeadState->hwHeadsMask) != 0x0 && + (nvDpyIdIsInDpyIdList(pDpyEvo->id, pApiHeadState->activeDpys))); + + head = nvGetPrimaryHwHead(pDispEvo, pDpyEvo->apiHead); + + nvAssert(head != NV_INVALID_HEAD); if (nvConnectorUsesDPLib(pDpyEvo->pConnectorEvo)) { - UpdateDpInfoFrames(pDispEvo, head); + UpdateDpInfoFrames(pDispEvo, head, &pApiHeadState->attributes); } else { nvUpdateHdmiInfoFrames(pDispEvo, head, - &pHeadState->attributes, - nvEvoIsHDQualityVideoTimings(&pHeadState->timings), - &pHeadState->timings.infoFrameCtrl, + &pApiHeadState->attributes, + &pApiHeadState->infoFrame, pDpyEvo); } } @@ -2719,9 +2855,8 @@ void nvDpyUpdateCurrentAttributes(NVDpyEvoRec *pDpyEvo) NVAttributesSetEvoRec newAttributes = pDpyEvo->currentAttributes; if (pDpyEvo->apiHead != NV_INVALID_HEAD) { - /* XXX[2Heads1OR] attributes should get stored in the api-head state. */ newAttributes = - pDpyEvo->pDispEvo->headState[pDpyEvo->apiHead].attributes; + pDpyEvo->pDispEvo->apiHeadState[pDpyEvo->apiHead].attributes; } else { newAttributes.dithering.enabled = FALSE; newAttributes.dithering.depth = NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_DEPTH_NONE; diff --git a/src/nvidia-modeset/src/nvkms-evo.c b/src/nvidia-modeset/src/nvkms-evo.c index 97cdf9243..6ecf91187 100644 --- a/src/nvidia-modeset/src/nvkms-evo.c +++ b/src/nvidia-modeset/src/nvkms-evo.c @@ -42,6 +42,8 @@ #include "nvkms-prealloc.h" #include "nvkms-rmapi.h" #include "nvkms-surface.h" +#include "nvkms-headsurface.h" +#include "nvkms-difr.h" #include "nvkms-vrr.h" #include "nvkms-ioctl.h" @@ -195,8 +197,9 @@ static void BlankHeadEvo(NVDispEvoPtr pDispEvo, const NvU32 head, { NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; - struct NvKmsCompositionParams emptyCursorCompParams = { }; - + struct NvKmsCompositionParams emptyCursorCompParams = + nvDefaultCursorCompositionParams(pDevEvo); + /* * If core channel surface is supported, ->SetSurface() * disables Lut along with core channel surface. Otherwise need to disable @@ -1645,9 +1648,18 @@ void nvEnableMidFrameAndDWCFWatermark(NVDevEvoPtr pDevEvo, * This needs to be called during a modeset when YUV420 mode may have been * enabled or disabled, as well as when the requested color space or range have * changed. + * + * RGB/YUV would be selected for DFP, only RGB would be selected for CRT and + * only YUV would be selected for TV. + * + * If SW YUV420 mode is enabled, EVO HW is programmed with default (RGB color + * space, FULL color range) values, and the real values are used in a + * headSurface composite shader. */ void nvChooseCurrentColorSpaceAndRangeEvo( - const NVHwModeTimingsEvo *pTimings, + enum nvKmsPixelDepth pixelDepth, + enum NvYuv420Mode yuv420Mode, + enum NvKmsOutputTf tf, const enum NvKmsDpyAttributeRequestedColorSpaceValue requestedColorSpace, const enum NvKmsDpyAttributeColorRangeValue requestedColorRange, enum NvKmsDpyAttributeCurrentColorSpaceValue *pCurrentColorSpace, @@ -1659,16 +1671,23 @@ void nvChooseCurrentColorSpaceAndRangeEvo( NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_FULL; /* At depth 18 only RGB and full range are allowed */ - if (pTimings && pTimings->pixelDepth == NVKMS_PIXEL_DEPTH_18_444) { + if (pixelDepth == NVKMS_PIXEL_DEPTH_18_444) { goto done; } /* * If the current mode timing requires YUV420 compression, we override the * requested color space with YUV420. + * + * If the head is currently in PQ output mode, we override the requested + * color space with BT2020. */ - if (pTimings && (pTimings->yuv420Mode != NV_YUV420_MODE_NONE)) { + if (yuv420Mode != NV_YUV420_MODE_NONE) { newColorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420; + } else if (tf == NVKMS_OUTPUT_TF_PQ) { + // XXX HDR TODO: Handle other transfer functions + // XXX HDR TODO: Handle YUV + newColorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_BT2020RGB; } else { /* * Note this is an assignment between different enum types. Checking the @@ -1690,10 +1709,11 @@ void nvChooseCurrentColorSpaceAndRangeEvo( } } - /* Only limited color range is allowed in YUV colorimetry. */ + /* Only limited color range is allowed in YUV and BT2020 colorimetry. */ if ((newColorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444) || (newColorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422) || - (newColorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420)) { + (newColorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420) || + (newColorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_BT2020RGB)) { newColorRange = NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_LIMITED; } else { newColorRange = requestedColorRange; @@ -1734,6 +1754,7 @@ void nvUpdateCurrentHardwareColorSpaceAndRangeEvo( // Set color format switch (colorSpace) { case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB: + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_BT2020RGB: pHeadState->procAmp.colorFormat = NVT_COLOR_FORMAT_RGB; break; case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444: @@ -1756,6 +1777,9 @@ void nvUpdateCurrentHardwareColorSpaceAndRangeEvo( case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB: pHeadState->procAmp.colorimetry = NVT_COLORIMETRY_RGB; break; + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_BT2020RGB: + pHeadState->procAmp.colorimetry = NVT_COLORIMETRY_BT2020RGB; + break; case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444: case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422: case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420: @@ -1824,45 +1848,6 @@ void nvUpdateCurrentHardwareColorSpaceAndRangeEvo( nvPopEvoSubDevMask(pDevEvo); } -/*! - * nvSetColorSpaceAndRangeEvo() - Select the colorimetry and color range - * values and program into EVO HW based on the currently selected - * color space and color range values and DISPLAY_DEVICE_TYPE. - * - * RGB/YUV would be selected for DFP, only RGB would be selected for CRT and - * only YUV would be selected for TV. - * - * If SW YUV420 mode is enabled, EVO HW is programmed with default (RGB color - * space, FULL color range) values, and the real values are used in a - * headSurface composite shader. - */ -void nvSetColorSpaceAndRangeEvo( - NVDispEvoPtr pDispEvo, const NvU32 head, - const enum NvKmsDpyAttributeRequestedColorSpaceValue requestedColorSpace, - const enum NvKmsDpyAttributeColorRangeValue requestedColorRange, - NVEvoUpdateState *pUpdateState) -{ - NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; - NVHwModeTimingsEvo *pTimings = &pHeadState->timings; - - /* - * Choose current colorSpace and colorRange based on the current mode - * timings and the requested color space and range. - */ - nvChooseCurrentColorSpaceAndRangeEvo(pTimings, - requestedColorSpace, - requestedColorRange, - &pHeadState->attributes.colorSpace, - &pHeadState->attributes.colorRange); - - /* Update hardware's current colorSpace and colorRange */ - nvUpdateCurrentHardwareColorSpaceAndRangeEvo(pDispEvo, - head, - pHeadState->attributes.colorSpace, - pHeadState->attributes.colorRange, - pUpdateState); -} - void nvEvoHeadSetControlOR(NVDispEvoPtr pDispEvo, const NvU32 head, NVEvoUpdateState *pUpdateState) { @@ -1896,69 +1881,72 @@ void nvEvoHeadSetControlOR(NVDispEvoPtr pDispEvo, nvPopEvoSubDevMask(pDevEvo); } +static const struct { + NvU32 algo; + enum NvKmsDpyAttributeCurrentDitheringModeValue nvKmsDitherMode; +} ditherModeTable[] = { + { NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_DYNAMIC_2X2, + NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_MODE_DYNAMIC_2X2 }, + { NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_STATIC_2X2, + NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_MODE_STATIC_2X2 }, + { NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_TEMPORAL, + NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_MODE_TEMPORAL }, + { NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_UNKNOWN, + NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_MODE_NONE } +}; + +static const struct { + NvU32 type; + enum NvKmsDpyAttributeCurrentDitheringDepthValue nvKmsDitherDepth; +} ditherDepthTable[] = { + { NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_6_BITS, + NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_DEPTH_6_BITS }, + { NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_8_BITS, + NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_DEPTH_8_BITS }, + { NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_OFF, + NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_DEPTH_NONE } +}; + /*! - * Set dithering based on the values in input config and + * Choose dithering based on the requested dithering config * NVConnectorEvo::or::dither. */ -void nvSetDitheringEvo( - NVDispEvoPtr pDispEvo, const NvU32 head, - enum NvKmsDpyAttributeRequestedDitheringValue configState, - const enum NvKmsDpyAttributeRequestedDitheringDepthValue configDepth, - const enum NvKmsDpyAttributeRequestedDitheringModeValue configMode, - NVEvoUpdateState *pUpdateState) +void nvChooseDitheringEvo( + const NVConnectorEvoRec *pConnectorEvo, + const enum nvKmsPixelDepth pixelDepth, + const NVDpyAttributeRequestedDitheringConfig *pReqDithering, + NVDpyAttributeCurrentDitheringConfig *pCurrDithering) { - static const struct { - NvU32 algo; - enum NvKmsDpyAttributeCurrentDitheringModeValue nvKmsDitherMode; - } ditherModeTable[] = { - { NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_DYNAMIC_2X2, - NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_MODE_DYNAMIC_2X2 }, - { NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_STATIC_2X2, - NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_MODE_STATIC_2X2 }, - { NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_TEMPORAL, - NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_MODE_TEMPORAL }, - { NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_UNKNOWN, - NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_MODE_NONE } + NvU32 i; + NVDpyAttributeCurrentDitheringConfig currDithering = { + .enabled = FALSE, + .mode = NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_MODE_NONE, + .depth = NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_DEPTH_NONE, }; - static const struct { - NvU32 type; - enum NvKmsDpyAttributeCurrentDitheringDepthValue nvKmsDitherDepth; - } ditherDepthTable[] = { - { NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_6_BITS, - NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_DEPTH_6_BITS }, - { NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_8_BITS, - NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_DEPTH_8_BITS }, - { NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_OFF, - NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_DEPTH_NONE } - }; - int i; - NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; - NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; - NvBool enabled = FALSE; - NvU32 algo = NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_UNKNOWN; - NvU32 type = NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_OFF; - const NVConnectorEvoRec *pConnectorEvo = pHeadState->pConnectorEvo; - if (pConnectorEvo != NULL) { - type = pConnectorEvo->or.ditherType; - algo = pConnectorEvo->or.ditherAlgo; - } - enabled = (type != NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_OFF); + currDithering.enabled = (pConnectorEvo->or.ditherType != + NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_OFF); - /* - * Make sure algo is a recognizable value that we will be able to program - * in hardware. - */ - if (algo == NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_UNKNOWN) { - algo = NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_DYNAMIC_2X2; + for (i = 0; i < ARRAY_LEN(ditherDepthTable); i++) { + if (ditherDepthTable[i].type == pConnectorEvo->or.ditherType) { + currDithering.depth = ditherDepthTable[i].nvKmsDitherDepth; + break; + } } - switch (configState) { + for (i = 0; i < ARRAY_LEN(ditherModeTable); i++) { + if (ditherModeTable[i].algo == pConnectorEvo->or.ditherAlgo) { + currDithering.mode = ditherModeTable[i].nvKmsDitherMode; + break; + } + } + + switch (pReqDithering->state) { case NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_ENABLED: - enabled = TRUE; + currDithering.enabled = TRUE; break; case NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_DISABLED: - enabled = FALSE; + currDithering.enabled = FALSE; break; default: nvAssert(!"Unknown Dithering configuration"); @@ -1971,12 +1959,14 @@ void nvSetDitheringEvo( break; } - switch (configDepth) { + switch (pReqDithering->depth) { case NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_DEPTH_6_BITS: - type = NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_6_BITS; + currDithering.depth = + NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_DEPTH_6_BITS; break; case NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_DEPTH_8_BITS: - type = NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_8_BITS; + currDithering.depth = + NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_DEPTH_8_BITS; break; default: nvAssert(!"Unknown Dithering Depth"); @@ -1990,15 +1980,16 @@ void nvSetDitheringEvo( } - if (pConnectorEvo != NULL && nvConnectorUsesDPLib(pConnectorEvo) && - configState != NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_DISABLED) { + if (nvConnectorUsesDPLib(pConnectorEvo) && + (pReqDithering->state != + NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_DISABLED)) { NvU32 lutBits = 11; /* If we are using DisplayPort panel with bandwidth constraints * which lowers the color depth, consider that while applying * dithering effects. */ - NvU32 dpBits = nvPixelDepthToBitsPerComponent(pHeadState->timings.pixelDepth); + NvU32 dpBits = nvPixelDepthToBitsPerComponent(pixelDepth); if (dpBits == 0) { nvAssert(!"Unknown dpBits"); dpBits = 8; @@ -2011,31 +2002,38 @@ void nvSetDitheringEvo( * * XXX TODO: nvdisplay can dither to 10 bpc. */ - if (dpBits <= 8 && lutBits > dpBits) { - if (configState == NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_AUTO) { - enabled = TRUE; + if ((dpBits <= 8) && (lutBits > dpBits)) { + if (pReqDithering->state == + NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_AUTO) { + currDithering.enabled = TRUE; } } - if (configDepth == NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_DEPTH_AUTO) { + if (pReqDithering->depth == + NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_DEPTH_AUTO) { if (dpBits <= 6) { - type = NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_6_BITS; + currDithering.depth = + NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_DEPTH_6_BITS; } else if (dpBits <= 8) { - type = NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_8_BITS; + currDithering.depth = + NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_DEPTH_8_BITS; } } } - if (enabled) { - switch (configMode) { + if (currDithering.enabled) { + switch (pReqDithering->mode) { case NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_MODE_TEMPORAL: - algo = NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_TEMPORAL; + currDithering.mode = + NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_MODE_TEMPORAL; break; case NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_MODE_DYNAMIC_2X2: - algo = NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_DYNAMIC_2X2; + currDithering.mode = + NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_MODE_DYNAMIC_2X2; break; case NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_MODE_STATIC_2X2: - algo = NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_STATIC_2X2; + currDithering.mode = + NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_MODE_STATIC_2X2; break; default: nvAssert(!"Unknown Dithering Mode"); @@ -2048,35 +2046,53 @@ void nvSetDitheringEvo( break; } } else { - algo = NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_UNKNOWN; - type = NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_OFF; + currDithering.depth = NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_DEPTH_NONE; + currDithering.mode = NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_MODE_NONE; + } + + *pCurrDithering = currDithering; +} + +void nvSetDitheringEvo( + NVDispEvoPtr pDispEvo, + const NvU32 head, + const NVDpyAttributeCurrentDitheringConfig *pCurrDithering, + NVEvoUpdateState *pUpdateState) +{ + NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + NvU32 i; + NvU32 algo = NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_UNKNOWN; + NvU32 type = NV0073_CTRL_SPECIFIC_OR_DITHER_TYPE_OFF; + NvU32 enabled = pCurrDithering->enabled; + + for (i = 0; i < ARRAY_LEN(ditherModeTable); i++) { + if (ditherModeTable[i].nvKmsDitherMode == pCurrDithering->mode) { + algo = ditherModeTable[i].algo; + break; + } + } + nvAssert(i < ARRAY_LEN(ditherModeTable)); + + for (i = 0; i < ARRAY_LEN(ditherDepthTable); i++) { + if (ditherDepthTable[i].nvKmsDitherDepth == pCurrDithering->depth) { + type = ditherDepthTable[i].type; + break; + } + } + nvAssert(i < ARRAY_LEN(ditherDepthTable)); + + /* + * Make sure algo is a recognizable value that we will be able to program + * in hardware. + */ + if (algo == NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_UNKNOWN) { + algo = NV0073_CTRL_SPECIFIC_OR_DITHER_ALGO_DYNAMIC_2X2; } nvPushEvoSubDevMaskDisp(pDispEvo); - - pDevEvo->hal->SetDither(pDispEvo, head, enabled, type, algo, pUpdateState); - + pDevEvo->hal->SetDither(pDispEvo, head, enabled, type, algo, + pUpdateState); nvPopEvoSubDevMask(pDevEvo); - - pHeadState->attributes.dithering.enabled = enabled; - - for (i = 0; i < ARRAY_LEN(ditherDepthTable); i++) { - if (type == ditherDepthTable[i].type) { - pHeadState->attributes.dithering.depth = - ditherDepthTable[i].nvKmsDitherDepth; - break; - } - } - nvAssert(i < ARRAY_LEN(ditherModeTable)); - - for (i = 0; i < ARRAY_LEN(ditherModeTable); i++) { - if (algo == ditherModeTable[i].algo) { - pHeadState->attributes.dithering.mode = - ditherModeTable[i].nvKmsDitherMode; - break; - } - } - nvAssert(i < ARRAY_LEN(ditherModeTable)); } /* @@ -3500,12 +3516,35 @@ static NvBool AllocEvoSubDevs(NVDevEvoPtr pDevEvo) for (i = 0; i < ARRAY_LEN(pSdHeadState->layer); i++) { pSdHeadState->layer[i].cscMatrix = NVKMS_IDENTITY_CSC_MATRIX; } + + pSdHeadState->cursor.cursorCompParams = + nvDefaultCursorCompositionParams(pDevEvo); } } return TRUE; } + +// Replace default cursor composition params when zeroed-out values are unsupported. +struct NvKmsCompositionParams nvDefaultCursorCompositionParams(const NVDevEvoRec *pDevEvo) +{ + const struct NvKmsCompositionCapabilities *pCaps = + &pDevEvo->caps.cursorCompositionCaps; + const NvU32 supportedBlendMode = + pCaps->colorKeySelect[NVKMS_COMPOSITION_COLOR_KEY_SELECT_DISABLE].supportedBlendModes[1]; + + struct NvKmsCompositionParams params = { }; + + if ((supportedBlendMode & NVBIT(NVKMS_COMPOSITION_BLENDING_MODE_OPAQUE)) != 0x0) { + params.blendingMode[1] = NVKMS_COMPOSITION_BLENDING_MODE_OPAQUE; + } else { + params.blendingMode[1] = NVKMS_COMPOSITION_BLENDING_MODE_PREMULT_ALPHA; + } + + return params; +} + static NvBool ValidateConnectorTypes(const NVDevEvoRec *pDevEvo) { const NVDispEvoRec *pDispEvo; @@ -3529,6 +3568,51 @@ static NvBool ValidateConnectorTypes(const NVDevEvoRec *pDevEvo) return TRUE; } +static void InitApiHeadState(NVDevEvoRec *pDevEvo) +{ + NVDispEvoRec *pDispEvo; + NvU32 dispIndex; + NvU32 head; + + nvAssert(pDevEvo->numApiHeads == pDevEvo->numHeads); + + for (head = 0; head < pDevEvo->numHeads; head++) { + NvU32 apiHead = nvHardwareHeadToApiHead(head); + pDevEvo->apiHead[apiHead].numLayers = + pDevEvo->head[head].numLayers; + } + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + for (head = 0; head < pDevEvo->numHeads; head++) { + NvU32 apiHead = nvHardwareHeadToApiHead(head); + + pDispEvo->apiHeadState[apiHead].hwHeadsMask = NVBIT(head); + pDispEvo->apiHeadState[apiHead].attributes = + NV_EVO_DEFAULT_ATTRIBUTES_SET; + + if (pDispEvo->headState[head].pConnectorEvo != NULL) { + const NVConnectorEvoRec *pConnectorEvo = + pDispEvo->headState[head].pConnectorEvo; + + /* + * Use the pDpyEvo for the connector, since we may not have one + * for display id if it's a dynamic one. + */ + NVDpyEvoRec *pDpyEvo = nvGetDpyEvoFromDispEvo(pDispEvo, + pConnectorEvo->displayId); + + nvAssert(pDpyEvo->apiHead == NV_INVALID_HEAD); + + pDpyEvo->apiHead = apiHead; + pDispEvo->apiHeadState[apiHead].activeDpys = + nvAddDpyIdToEmptyDpyIdList(pConnectorEvo->displayId); + } else { + pDispEvo->apiHeadState[apiHead].activeDpys = nvEmptyDpyIdList(); + } + } + } +} + /*! * Allocate the EVO core channel. * @@ -3543,6 +3627,8 @@ NvBool nvAllocCoreChannelEvo(NVDevEvoPtr pDevEvo) NvU32 dispIndex; NvU32 head; + nvAssert(pDevEvo->lastModesettingClient == NULL); + /* Do nothing if the display was already allocated */ if (pDevEvo->displayHandle != 0) { return TRUE; @@ -3706,6 +3792,8 @@ NvBool nvAllocCoreChannelEvo(NVDevEvoPtr pDevEvo) } } + InitApiHeadState(pDevEvo); + return TRUE; failed: @@ -3914,6 +4002,18 @@ void nvRestoreSORAssigmentsEvo(NVDevEvoRec *pDevEvo) } } +static void ClearApiHeadState(NVDevEvoRec *pDevEvo) +{ + NvU32 dispIndex; + NVDispEvoRec *pDispEvo; + + nvkms_memset(pDevEvo->apiHead, 0, sizeof(pDevEvo->apiHead)); + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + nvkms_memset(pDispEvo->apiHeadState, 0, sizeof(pDispEvo->apiHeadState)); + } +} + /*! * Free the EVO core channel. * @@ -3925,6 +4025,8 @@ void nvFreeCoreChannelEvo(NVDevEvoPtr pDevEvo) NvU32 dispIndex; NvU32 head; + ClearApiHeadState(pDevEvo); + nvEvoCancelPostFlipIMPTimer(pDevEvo); nvCancelVrrFrameReleaseTimers(pDevEvo); @@ -3986,6 +4088,8 @@ void nvFreeCoreChannelEvo(NVDevEvoPtr pDevEvo) nvFree(pDevEvo->gpus); pDevEvo->gpus = NULL; + + pDevEvo->lastModesettingClient = NULL; } @@ -4850,8 +4954,7 @@ void nvAssignDefaultUsageBounds(const NVDispEvoRec *pDispEvo, pDevEvo->caps.layerCaps[i].supportedSurfaceMemoryFormats; nvInitScalingUsageBounds(pDevEvo, pScaling); - /* Scaling is not currently supported for the main layer. Bug 3488083 */ - if (i != NVKMS_MAIN_LAYER && pDevEvo->hal->GetWindowScalingCaps) { + if (pDevEvo->hal->GetWindowScalingCaps) { const NVEvoScalerCaps *pScalerCaps = pDevEvo->hal->GetWindowScalingCaps(pDevEvo); int j; @@ -4995,12 +5098,12 @@ ConstructHwModeTimingsViewPort(const NVDispEvoRec *pDispEvo, /* - * nvGetDfpProtocol()- determine the protocol to use on the given pDpy + * GetDfpProtocol()- determine the protocol to use on the given pDpy * with the given pTimings; assigns pTimings->protocol. */ -NvBool nvGetDfpProtocol(const NVDpyEvoRec *pDpyEvo, - NVHwModeTimingsEvoPtr pTimings) +static NvBool GetDfpProtocol(const NVDpyEvoRec *pDpyEvo, + NVHwModeTimingsEvoPtr pTimings) { NVConnectorEvoPtr pConnectorEvo = pDpyEvo->pConnectorEvo; const NvU32 rmProtocol = pConnectorEvo->or.protocol; @@ -5139,7 +5242,7 @@ static NvBool ConstructHwModeTimingsEvoDfp(const NVDpyEvoRec *pDpyEvo, return FALSE; } - ret = nvGetDfpProtocol(pDpyEvo, pTimings); + ret = GetDfpProtocol(pDpyEvo, pTimings); if (!ret) { return FALSE; @@ -5158,7 +5261,8 @@ static NvBool ConstructHwModeTimingsEvoDfp(const NVDpyEvoRec *pDpyEvo, NvBool nvDowngradeHwModeTimingsDpPixelDepthEvo( NVHwModeTimingsEvoPtr pTimings, - const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace) + const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, + const enum NvKmsDpyAttributeColorRangeValue colorRange) { /* * In YUV420, HW is programmed with RGB color space and full color range. @@ -5178,6 +5282,11 @@ NvBool nvDowngradeHwModeTimingsDpPixelDepthEvo( return FALSE; case NVKMS_PIXEL_DEPTH_24_444: + /* At depth 18 only RGB and full range are allowed */ + if ((colorSpace != NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB) || + (colorRange != NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_FULL)) { + return FALSE; + } pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_18_444; break; case NVKMS_PIXEL_DEPTH_30_444: @@ -5205,6 +5314,10 @@ NvBool nvDPValidateModeEvo(NVDpyEvoPtr pDpyEvo, (pTimings->yuv420Mode != NV_YUV420_MODE_NONE) ? NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420 : NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB; + const enum NvKmsDpyAttributeColorRangeValue colorRange = + (colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB) ? + NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_FULL : + NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_LIMITED; /* Only do this for DP devices. */ if (!nvConnectorUsesDPLib(pConnectorEvo)) { @@ -5226,7 +5339,8 @@ NvBool nvDPValidateModeEvo(NVDpyEvoPtr pDpyEvo, tryAgain: if (!nvDPValidateModeForDpyEvo(pDpyEvo, colorSpace, pParams, pTimings)) { - if (nvDowngradeHwModeTimingsDpPixelDepthEvo(pTimings, colorSpace)) { + if (nvDowngradeHwModeTimingsDpPixelDepthEvo(pTimings, + colorSpace, colorRange)) { goto tryAgain; } /* @@ -5329,14 +5443,6 @@ NvBool nvConstructHwModeTimingsEvo(const NVDpyEvoRec *pDpyEvo, } } - /* - * Clear the NVT_VIDEO_INFOFRAME_CTRL; it will be populated when - * considering EDID modes for the modepool, and used when sending - * the infoframe to an HDMI monitor. - */ - nvkms_memset(&pTimings->infoFrameCtrl, - NVT_INFOFRAME_CTRL_DONTCARE, sizeof(pTimings->infoFrameCtrl)); - pTimings->stereo.mode = pParams->stereoMode; pTimings->stereo.isAegis = pDpyEvo->stereo3DVision.isAegis; @@ -6729,6 +6835,12 @@ NvBool nvFreeDevEvo(NVDevEvoPtr pDevEvo) return FALSE; } + if (pDevEvo->pDifrState) { + nvRmUnregisterDIFREventHandler(pDevEvo); + nvDIFRFree(pDevEvo->pDifrState); + pDevEvo->pDifrState = NULL; + } + if (pDevEvo->pNvKmsOpenDev != NULL) { /* * DP-MST allows to attach more than one heads/stream to single DP @@ -6747,6 +6859,8 @@ NvBool nvFreeDevEvo(NVDevEvoPtr pDevEvo) nvTeardownHdmiLibrary(pDevEvo); + nvHsFreeDevice(pDevEvo); + nvFreePerOpenDev(nvEvoGlobal.nvKmsPerOpen, pDevEvo->pNvKmsOpenDev); nvFreeFrameLocksEvo(pDevEvo); @@ -6772,6 +6886,11 @@ NvBool nvFreeDevEvo(NVDevEvoPtr pDevEvo) return TRUE; } +static void AssignNumberOfApiHeads(NVDevEvoRec *pDevEvo) +{ + pDevEvo->numApiHeads = pDevEvo->numHeads; +} + NVDevEvoPtr nvAllocDevEvo(const struct NvKmsAllocDeviceRequest *pRequest, enum NvKmsAllocDeviceStatus *pStatus) { @@ -6858,6 +6977,8 @@ NVDevEvoPtr nvAllocDevEvo(const struct NvKmsAllocDeviceRequest *pRequest, goto done; } + AssignNumberOfApiHeads(pDevEvo); + if (!nvAllocCoreChannelEvo(pDevEvo)) { status = NVKMS_ALLOC_DEVICE_STATUS_CORE_CHANNEL_ALLOC_FAILED; goto done; @@ -6887,6 +7008,11 @@ NVDevEvoPtr nvAllocDevEvo(const struct NvKmsAllocDeviceRequest *pRequest, goto done; } + if (!nvHsAllocDevice(pDevEvo, pRequest)) { + status = NVKMS_ALLOC_DEVICE_STATUS_FATAL_ERROR; + goto done; + } + if (!nvInitHdmiLibrary(pDevEvo)) { status = NVKMS_ALLOC_DEVICE_STATUS_FATAL_ERROR; goto done; @@ -6896,6 +7022,18 @@ NVDevEvoPtr nvAllocDevEvo(const struct NvKmsAllocDeviceRequest *pRequest, status = NVKMS_ALLOC_DEVICE_STATUS_SUCCESS; + /* + * We can't allocate DIFR state if h/w doesn't support it. Only register + * event handlers with DIFR state. + */ + pDevEvo->pDifrState = nvDIFRAllocate(pDevEvo); + if (pDevEvo->pDifrState) { + if (!nvRmRegisterDIFREventHandler(pDevEvo)) { + nvDIFRFree(pDevEvo->pDifrState); + pDevEvo->pDifrState = NULL; + } + } + /* fall through */ done: @@ -7357,3 +7495,138 @@ void nvDPSerializerPostSetMode(NVDispEvoPtr pDispEvo, NV_FALSE /* reTrain */); } } + +NvBool nvIsHDRCapableHead(NVDispEvoPtr pDispEvo, + NvU32 apiHead) +{ + const NVDpyEvoRec *pDpyEvo; + NvU32 primaryHwHead = nvGetPrimaryHwHead(pDispEvo, apiHead); + NvU32 activeDpyCount = 0; + + if (primaryHwHead != NV_INVALID_HEAD) { + const NVDispHeadStateEvoRec *pHeadState = + &pDispEvo->headState[primaryHwHead]; + const NVConnectorEvoRec *pConnectorEvo = pHeadState->pConnectorEvo; + + if (pConnectorEvo == NULL) { + return FALSE; + } + + // XXX HDR TODO: Currently only DP is supported, not HDMI. + if (!nvConnectorUsesDPLib(pConnectorEvo)) { + return FALSE; + } + } else { + return FALSE; + } + + FOR_ALL_EVO_DPYS(pDpyEvo, + pDispEvo->apiHeadState[apiHead].activeDpys, + pDispEvo) { + const NVT_EDID_INFO *pInfo = &pDpyEvo->parsedEdid.info; + const NVT_HDR_STATIC_METADATA *pHdrInfo = + &pInfo->hdr_static_metadata_info; + + if (!pDpyEvo->parsedEdid.valid) { + return FALSE; + } + + // Sink should support ST2084 EOTF. + if (!pHdrInfo->supported_eotf.smpte_st_2084_eotf) { + return FALSE; + } + + /* + * Sink should support static metadata type1. Nvtiming sets + * static_metadata_type to 1 if the sink supports static metadata type1. + */ + if (pHdrInfo->static_metadata_type != 1) { + return FALSE; + } + + activeDpyCount++; + } + + return (activeDpyCount > 0); +} + +NvU32 nvGetHDRSrcMaxLum(const NVFlipChannelEvoHwState *pHwState) +{ + if (!pHwState->hdrStaticMetadata.enabled) { + return 0; + } + + if (pHwState->hdrStaticMetadata.val.maxCLL > 0) { + return pHwState->hdrStaticMetadata.val.maxCLL; + } + + return pHwState->hdrStaticMetadata.val.maxDisplayMasteringLuminance; +} + +NvBool nvNeedsTmoLut(NVDevEvoPtr pDevEvo, + NVEvoChannelPtr pChannel, + const NVFlipChannelEvoHwState *pHwState, + NvU32 srcMaxLum, + NvU32 targetMaxCLL) +{ + const NvU32 win = NV_EVO_CHANNEL_MASK_WINDOW_NUMBER(pChannel->channelMask); + const NvU32 head = pDevEvo->headForWindow[win]; + const NvU32 sdMask = nvPeekEvoSubDevMask(pDevEvo); + const NvU32 sd = (sdMask == 0) ? 0 : __builtin_ffs(sdMask) - 1; + const NVDispHeadStateEvoRec *pHeadState = + &pDevEvo->pDispEvo[sd]->headState[head]; +#if defined(DEBUG) + const NVEvoWindowCaps *pWinCaps = + &pDevEvo->gpus[sd].capabilities.window[pChannel->instance]; +#endif + + // Don't tone map if flipped to NULL. + if (!pHwState->pSurfaceEvo[NVKMS_LEFT]) { + return FALSE; + } + + // Don't tone map if layer doesn't have static metadata. + // XXX HDR TODO: Support tone mapping SDR surfaces to HDR + if (!pHwState->hdrStaticMetadata.enabled) { + return FALSE; + } + + // Don't tone map if output isn't HDR. + // XXX HDR TODO: Support tone mapping HDR surfaces to SDR + if (pHeadState->hdr.outputState != NVKMS_HDR_OUTPUT_STATE_HDR) { + return FALSE; + } + + // Don't tone map if TMO not present, implied by NVKMS_HDR_OUTPUT_STATE_HDR. + nvAssert(pWinCaps->tmoPresent); + + // Don't tone map if source or target max luminance is unspecified. + if ((srcMaxLum == 0) || (targetMaxCLL == 0)) { + return FALSE; + } + + // Don't tone map unless source max luminance exceeds target by 10%. + if (srcMaxLum <= ((targetMaxCLL * 110) / 100)) { + return FALSE; + } + + return TRUE; +} + +NvBool nvIsCscMatrixIdentity(const struct NvKmsCscMatrix *matrix) +{ + const struct NvKmsCscMatrix identity = NVKMS_IDENTITY_CSC_MATRIX; + + int y; + for (y = 0; y < 3; y++) { + int x; + + for (x = 0; x < 4; x++) { + if (matrix->m[y][x] != identity.m[y][x]) { + return FALSE; + } + } + } + + return TRUE; +} diff --git a/src/nvidia-modeset/src/nvkms-evo2.c b/src/nvidia-modeset/src/nvkms-evo2.c index b19d49601..e5f63e421 100644 --- a/src/nvidia-modeset/src/nvkms-evo2.c +++ b/src/nvidia-modeset/src/nvkms-evo2.c @@ -226,6 +226,7 @@ static NvU32 EvoOverlayFormatFromKmsFormat91(enum NvKmsSurfaceMemoryFormat forma case NvKmsSurfaceMemoryFormatX2B10G10R10: return NV917E_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10; case NvKmsSurfaceMemoryFormatRF16GF16BF16AF16: + case NvKmsSurfaceMemoryFormatRF16GF16BF16XF16: return NV917E_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16; case NvKmsSurfaceMemoryFormatR16G16B16A16: return NV917E_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16; @@ -1264,6 +1265,7 @@ static NvU32 nvHwFormatFromKmsFormat90( case NvKmsSurfaceMemoryFormatX2B10G10R10: return NV917D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10; case NvKmsSurfaceMemoryFormatRF16GF16BF16AF16: + case NvKmsSurfaceMemoryFormatRF16GF16BF16XF16: return NV917D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16; case NvKmsSurfaceMemoryFormatR16G16B16A16: return NV917D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16; @@ -2171,6 +2173,7 @@ static void EvoPackColorKey91(enum NvKmsSurfaceMemoryFormat format, break; case NvKmsSurfaceMemoryFormatI8: case NvKmsSurfaceMemoryFormatRF16GF16BF16AF16: + case NvKmsSurfaceMemoryFormatRF16GF16BF16XF16: case NvKmsSurfaceMemoryFormatR16G16B16A16: case NvKmsSurfaceMemoryFormatRF32GF32BF32AF32: case NvKmsSurfaceMemoryFormatY8_U8__Y8_V8_N422: @@ -3738,14 +3741,27 @@ static NvBool SetAccelerators( static void EvoAccelerateChannel91(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel, const NvU32 sd, + const NvBool trashPendingMethods, + const NvBool unblockMethodsInExecutation, NvU32 *pOldAccelerators) { + NvU32 accelMask = 0x0; + + if (trashPendingMethods) { + accelMask |= NV5070_CTRL_ACCL_TRASH_ONLY; + } + /* Start with a conservative set of accelerators; may need to add more * later. */ - const NvU32 accelMask = - NV5070_CTRL_ACCL_IGNORE_PI | - NV5070_CTRL_ACCL_SKIP_SEMA | - NV5070_CTRL_ACCL_IGNORE_FLIPLOCK; + if (unblockMethodsInExecutation) { + accelMask |= NV5070_CTRL_ACCL_IGNORE_PI | + NV5070_CTRL_ACCL_SKIP_SEMA | + NV5070_CTRL_ACCL_IGNORE_FLIPLOCK; + } + + if (accelMask == 0x0) { + return; + } *pOldAccelerators = GetAccelerators(pDevEvo, pChannel, sd); @@ -3758,14 +3774,27 @@ static void EvoAccelerateChannel91(NVDevEvoPtr pDevEvo, static void EvoResetChannelAccelerators91(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel, const NvU32 sd, + const NvBool trashPendingMethods, + const NvBool unblockMethodsInExecutation, NvU32 oldAccelerators) { + NvU32 accelMask = 0x0; + + if (trashPendingMethods) { + accelMask |= NV5070_CTRL_ACCL_TRASH_ONLY; + } + /* Start with a conservative set of accelerators; may need to add more * later. */ - const NvU32 accelMask = - NV5070_CTRL_ACCL_IGNORE_PI | - NV5070_CTRL_ACCL_SKIP_SEMA | - NV5070_CTRL_ACCL_IGNORE_FLIPLOCK; + if (unblockMethodsInExecutation) { + accelMask |= NV5070_CTRL_ACCL_IGNORE_PI | + NV5070_CTRL_ACCL_SKIP_SEMA | + NV5070_CTRL_ACCL_IGNORE_FLIPLOCK; + } + + if (accelMask == 0x0) { + return; + } /* Accelerate window channel. */ if (!SetAccelerators(pDevEvo, pChannel, sd, oldAccelerators, accelMask)) { @@ -3846,5 +3875,6 @@ NVEvoHAL nvEvo94 = { NV_EVO2_SUPPORTED_DITHERING_MODES, /* supportedDitheringModes */ sizeof(NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS), /* impStructSize */ NV_EVO_SCALER_1TAP, /* minScalerTaps */ + 0, /* xEmulatedSurfaceMemoryFormats */ }, }; diff --git a/src/nvidia-modeset/src/nvkms-evo3.c b/src/nvidia-modeset/src/nvkms-evo3.c index 7786b0e7b..335d5d3a9 100644 --- a/src/nvidia-modeset/src/nvkms-evo3.c +++ b/src/nvidia-modeset/src/nvkms-evo3.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2010-2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -36,6 +36,7 @@ #include "nvkms-modeset-types.h" #include "nvkms-prealloc.h" #include "nv-float.h" +#include "nvkms-dpy.h" #include @@ -58,6 +59,16 @@ #include #include +#define NV_EVO3_X_EMULATED_SURFACE_MEMORY_FORMATS_C3 \ + (NVBIT64(NvKmsSurfaceMemoryFormatRF16GF16BF16XF16)) + +#define NV_EVO3_X_EMULATED_SURFACE_MEMORY_FORMATS_C5 \ + (NVBIT64(NvKmsSurfaceMemoryFormatRF16GF16BF16XF16)) + +#define NV_EVO3_X_EMULATED_SURFACE_MEMORY_FORMATS_C6 \ + (NVBIT64(NvKmsSurfaceMemoryFormatRF16GF16BF16XF16) | \ + NVBIT64(NvKmsSurfaceMemoryFormatX2B10G10R10)) + /** Number of CRCs supported by hardware on NVC37D hardware (SF/SOR, Comp, RG) */ #define NV_EVO3_NUM_CRC_FIELDS 3 @@ -77,13 +88,27 @@ static void UpdateCompositionC3(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel, const struct NvKmsCompositionParams *pCompParams, - NVEvoUpdateState *updateState); + NVEvoUpdateState *updateState, + enum NvKmsSurfaceMemoryFormat format); static void UpdateCompositionC5(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel, const struct NvKmsCompositionParams *pCompParams, NVEvoUpdateState *updateState, - NvBool bypassComposition); + NvBool bypassComposition, + enum NvKmsSurfaceMemoryFormat format); + +static void +EvoSetupIdentityOutputLutC5(NVEvoLutDataRec *pData, + enum NvKmsLUTState *lutState, + NvU32 *lutSize, + NvBool *isLutModeVss); + +static void +EvoSetupIdentityBaseLutC5(NVEvoLutDataRec *pData, + enum NvKmsLUTState *lutState, + NvU32 *lutSize, + NvBool *isLutModeVss); ct_assert(NV_EVO_LOCK_PIN_0 > NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1); @@ -120,7 +145,7 @@ ct_assert((NVKMS_MAX_EYES * NVKMS_MAX_PLANES_PER_SURFACE) == 6); #define NV_EVO3_DEFAULT_WINDOW_USAGE_BOUNDS_C5 \ (DRF_DEF(C57D, _WINDOW_SET_WINDOW_USAGE_BOUNDS, _ILUT_ALLOWED, _TRUE) | \ - DRF_DEF(C57D, _WINDOW_SET_WINDOW_USAGE_BOUNDS, _TMO_LUT_ALLOWED, _FALSE)) + DRF_DEF(C57D, _WINDOW_SET_WINDOW_USAGE_BOUNDS, _TMO_LUT_ALLOWED, _TRUE)) static inline NvU8 EyeAndPlaneToCtxDmaIdx(const NvU8 eye, const NvU8 plane) { @@ -303,6 +328,16 @@ static void InitTaps5ScalerCoefficientsC5(NVDevEvoPtr pDevEvo, } } +/* + * This is a 3x4 matrix with S5.14 coefficients (truncated from S5.16 + * SW-specified values). + */ +static const struct NvKmsCscMatrix Rec2020RGBToLMS = {{ + { 0x697c, 0x8620, 0x1064, 0 }, + { 0x2aa8, 0xb86c, 0x1ce8, 0 }, + { 0x62c, 0x1354, 0xe684, 0 }, +}}; + /* * This is a 3x4 matrix with S5.14 coefficients (truncated from S5.16 * SW-specified values). @@ -414,6 +449,33 @@ static const NvU16 EotfPQ512Entries[] = { 0x55B4, 0x55C1, 0x55CF, 0x5607, 0x5641, 0x567E, 0x56BC, 0x56FE, 0x5741, 0x5788, 0x57D1, }; +#define TMO_LUT_NUM_SEGMENTS 64 +#define TMO_LUT_SEG_SIZE_LOG2 4 +#define TMO_LUT_NUM_ENTRIES 1024 + +struct TmoLutSettings +{ + NvU32 satMode; + NvU32 lowIntensityZoneEnd; + NvU32 lowIntensityValueLinWeight; + NvU32 lowIntensityValueNonLinWeight; + NvU32 lowIntensityValueThreshold; + + NvU32 medIntensityZoneStart; + NvU32 medIntensityZoneEnd; + NvU32 medIntensityValueLinWeight; + NvU32 medIntensityValueNonLinWeight; + NvU32 medIntensityValueThreshold; + + NvU32 highIntensityZoneStart; + NvU32 highIntensityValueLinWeight; + NvU32 highIntensityValueNonLinWeight; + NvU32 highIntensityValueThreshold; +}; + +// Default Rec.2020 weights, no color correction. +static const struct TmoLutSettings TMO_LUT_SETTINGS_REC2020 = { 2, 1280, 256, 256, 255, 4960, 4961, 256, 256, 255, 10640, 256, 256, 255 }; + static void InitCsc0LUT(NVEvoChannelPtr pChannel, const NvU32 *pSegmentSizes, NvU32 numSegmentSizes, const NvU16 *pLUTEntries, NvU32 numEntries) @@ -458,6 +520,7 @@ static void InitCsc1LUT(NVEvoChannelPtr pChannel, static void ConfigureCsc0C5(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel, + enum NvKmsInputColorSpace colorspace, NvBool enable) { NVEvoWindowCaps *pWinCaps = @@ -471,7 +534,11 @@ static void ConfigureCsc0C5(NVDevEvoPtr pDevEvo, } if (enable) { - matrix = Rec709RGBToLMS; + if (colorspace == NVKMS_INPUT_COLORSPACE_BT2100_PQ) { + matrix = Rec2020RGBToLMS; + } else { + matrix = Rec709RGBToLMS; + } lutData |= DRF_DEF(C57E, _SET_CSC0LUT_CONTROL, _INTERPOLATE, _ENABLE) | DRF_DEF(C57E, _SET_CSC0LUT_CONTROL, _MIRROR, _DISABLE) | @@ -505,6 +572,310 @@ static void ConfigureCsc0C5(NVDevEvoPtr pDevEvo, nvDmaSetEvoMethodData(pChannel, csc01Data); } +static inline float64_t maxF(float64_t a, float64_t b) +{ + return f64_lt(a, b) ? b : a; +} + +static inline float64_t clampF(float64_t value, float64_t min, float64_t max) +{ + value = maxF(value, min); + value = f64_lt(max, value) ? max : value; + return value; +} + +static float64_t PQEotf(float64_t colorValue, NvBool inverse) +{ + const float64_t zero = {0x0000000000000000}; // 0.0 + const float64_t one = {0x3FF0000000000000}; // 1.0 + const float64_t m1 = {0x3FC463FFFFFFB9A2}; // 0.1593017578125 + const float64_t m2 = {0x4053B60000000000}; // 78.84375 + const float64_t c1 = {0x3FEAC00000000000}; // 0.8359375 + const float64_t c2 = {0x4032DA0000000000}; // 18.8515625 + const float64_t c3 = {0x4032B00000000000}; // 18.6875 + + const float64_t invm1 = {0x40191C0D56E72ABA}; // 1/m1 = 6.27739463602 + const float64_t invm2 = {0x3F89F9B585D7C997}; // 1/m2 = 0.01268331351 + + if (inverse) { + // Convert from linear to PQ-encoded values. + float64_t L = clampF(colorValue, zero, one); + float64_t powLm1 = nvKmsPow(L, m1); + float64_t N = nvKmsPow(f64_div(f64_add(c1, f64_mul(c2, powLm1)), + f64_add(one, f64_mul(c3, powLm1))), m2); + + return clampF(N, zero, one); + } else { + // Convert from PQ-encoded values to linear values. + float64_t N = clampF(colorValue, zero, one); + float64_t powNinvM2 = nvKmsPow(N, invm2); + float64_t L = nvKmsPow(f64_div(maxF(f64_sub(powNinvM2, c1), zero), + f64_sub(c2, f64_mul(c3, powNinvM2))), + invm1); + + return clampF(L, zero, one); + } +} + +// Hermite spline +static float64_t P(float64_t B, float64_t KS, float64_t maxLum) +{ + const float64_t one = {0x3FF0000000000000}; // 1.0 + const float64_t two = {0x4000000000000000}; // 2.0 + const float64_t negtwo = {0xC000000000000000}; // -2.0 + const float64_t three = {0x4008000000000000}; // 3.0 + + float64_t t = f64_div(f64_sub(B, KS), f64_sub(one, KS)); + float64_t t2 = f64_mul(t, t); + float64_t t3 = f64_mul(t2, t); + + return + f64_add(f64_add( + f64_mul(f64_add(f64_sub(f64_mul(two, t3), f64_mul(three, t2)), one), KS), + f64_mul(f64_add(f64_sub(t3, f64_mul(two, t2)), t), f64_sub(one, KS))), + f64_mul(f64_add(f64_mul(negtwo, t3), f64_mul(three, t2)), maxLum)); +} + +/* + * PQ tone mapping operator with no remapping of blacks or "toe" section of + * curve. Messing with nonlinearity and remapping in the SDR portion of the + * curve results in bad looking PC desktop and game content. + * + * XXX HDR TODO: Remap blacks and implement toe section for video content? + */ +static NvU16 TmoLutEntry(NvU32 i, NvU32 targetMaxLum, NvU32 srcMaxLum) +{ + const float64_t zero = {0x0000000000000000}; // 0.0 + const float64_t half = {0x3FE0000000000000}; // 0.5 + const float64_t one = {0x3FF0000000000000}; // 1.0 + const float64_t oneHalf = {0x3FF8000000000000}; // 1.5 + const float64_t tenThousand = {0x40C3880000000000}; // 10000.0 + const float64_t maxIntensity = {0x40CFFF8000000000}; // 16383.0 + + float64_t outputF; + float64_t inputF = + f64_div(ui32_to_f64(i), ui32_to_f64(TMO_LUT_NUM_ENTRIES - 1)); + + float64_t targetMaxLumF = ui32_to_f64(targetMaxLum); + float64_t srcMaxLumF = ui32_to_f64(srcMaxLum); + + // Normalize luminance to 10,000 nits + float64_t Lw = f64_div(srcMaxLumF, tenThousand); + float64_t Lmax = f64_div(targetMaxLumF, tenThousand); + + float64_t maxLumRatio; + float64_t KS; + float64_t E1; + float64_t E2; + + nvAssert(srcMaxLum >= targetMaxLum); + + Lw = PQEotf(Lw, TRUE); + Lmax = PQEotf(Lmax, TRUE); + + maxLumRatio = f64_div(Lmax, Lw); + + KS = f64_sub(f64_mul(oneHalf, maxLumRatio), half); + + E1 = f64_div(inputF, Lw); + + if (f64_lt(E1, KS) || f64_eq(KS, one)) { + E2 = E1; + } else { + E2 = P(E1, KS, maxLumRatio); + } + + outputF = clampF(f64_mul(E2, Lw), zero, Lmax); + + return (NvU16) f64_to_ui32(clampF(f64_mul(outputF, maxIntensity), + zero, maxIntensity), + softfloat_round_near_even, FALSE) << 2; +} + +static void InitializeTmoLut(const NVEvoChannelPtr pChannel, + NVLutSurfaceEvoPtr pLutSurfaceEvo, + NvU32 sd) +{ + NVEvoLutDataRec *pData = pLutSurfaceEvo->subDeviceAddress[sd]; + NvU64 vssHead = 0; + NvU32 lutEntryCounter = 0, i; + + // VSS Header + for (lutEntryCounter = 0; lutEntryCounter < NV_LUT_VSS_HEADER_SIZE; lutEntryCounter++) { + vssHead = 0; + for (i = 0; ((i < 16) && (((lutEntryCounter * 16) + i) < TMO_LUT_NUM_SEGMENTS)); i++) { + NvU64 temp = TMO_LUT_SEG_SIZE_LOG2; + vssHead |= temp << (i * 3); + } + nvkms_memcpy(&(pData->base[lutEntryCounter]), &vssHead, sizeof(NVEvoLutEntryRec)); + } + + for (i = 0; i < TMO_LUT_NUM_ENTRIES; i++) { + pData->base[i + NV_LUT_VSS_HEADER_SIZE].Red = + pData->base[i + NV_LUT_VSS_HEADER_SIZE].Green = + pData->base[i + NV_LUT_VSS_HEADER_SIZE].Blue = + TmoLutEntry(i, + pChannel->tmoParams.targetMaxLums[sd], + pChannel->tmoParams.srcMaxLum); + } + + // Copy the last entry for interpolation + pData->base[TMO_LUT_NUM_ENTRIES + NV_LUT_VSS_HEADER_SIZE].Red = + pData->base[TMO_LUT_NUM_ENTRIES + NV_LUT_VSS_HEADER_SIZE - 1].Red; + pData->base[TMO_LUT_NUM_ENTRIES + NV_LUT_VSS_HEADER_SIZE].Blue = + pData->base[TMO_LUT_NUM_ENTRIES + NV_LUT_VSS_HEADER_SIZE - 1].Blue; + pData->base[TMO_LUT_NUM_ENTRIES + NV_LUT_VSS_HEADER_SIZE].Green = + pData->base[TMO_LUT_NUM_ENTRIES + NV_LUT_VSS_HEADER_SIZE - 1].Green; +} + +static NvBool UpdateTmoParams(NVEvoChannelPtr pChannel, + NvBool enabled, + NvU32 srcMaxLum, + const NvU32 targetMaxLums[NVKMS_MAX_SUBDEVICES]) +{ + NvU16 sd; + NvBool dirty = FALSE; + + if (pChannel->tmoParams.enabled != enabled) { + pChannel->tmoParams.enabled = enabled; + dirty = TRUE; + } + + if (pChannel->tmoParams.srcMaxLum != srcMaxLum) { + pChannel->tmoParams.srcMaxLum = srcMaxLum; + dirty = TRUE; + } + + for (sd = 0; sd < NVKMS_MAX_SUBDEVICES; sd++) { + if (pChannel->tmoParams.targetMaxLums[sd] != targetMaxLums[sd]) { + pChannel->tmoParams.targetMaxLums[sd] = targetMaxLums[sd]; + dirty = TRUE; + } + } + + return dirty; +} + +static void ConfigureTmoLut(NVDevEvoPtr pDevEvo, + const NVFlipChannelEvoHwState *pHwState, + NVEvoChannelPtr pChannel) +{ + NvU16 sd; + const NvU32 win = NV_EVO_CHANNEL_MASK_WINDOW_NUMBER(pChannel->channelMask); + const NvU32 head = pDevEvo->headForWindow[win]; + NvU32 ctxDma; + const NvU32 offset = offsetof(NVEvoLutDataRec, base); + const struct TmoLutSettings *tmoLutSettings; + const NvU32 srcMaxLum = nvGetHDRSrcMaxLum(pHwState); + + NvBool needsTmoLut = FALSE; + NvU32 targetMaxLums[NVKMS_MAX_SUBDEVICES] = {0}; + for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { + const NVDispHeadStateEvoRec *pHeadState = + &pDevEvo->pDispEvo[sd]->headState[head]; + + targetMaxLums[sd] = pHeadState->hdr.staticMetadata.maxCLL; + + // If any head needs tone mapping, enable TMO for channel + if (nvNeedsTmoLut(pDevEvo, pChannel, pHwState, + srcMaxLum, targetMaxLums[sd])) { + needsTmoLut = TRUE; + } + } + + if (!UpdateTmoParams(pChannel, needsTmoLut, srcMaxLum, targetMaxLums)) { + // No change in parameters, no need to reconfigure. + return; + } + + if (!pChannel->tmoParams.enabled) { + nvDmaSetStartEvoMethod(pChannel, NVC57E_SET_CONTEXT_DMA_TMO_LUT, 1); + nvDmaSetEvoMethodData(pChannel, + DRF_NUM(C57E, _SET_CONTEXT_DMA_TMO_LUT, _HANDLE, 0)); + + return; + } + + // Initialize TMO LUT on all subdevices + for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { + nvAssert(pHwState->tmoLut.pLutSurfaceEvo != NULL); + InitializeTmoLut(pChannel, pHwState->tmoLut.pLutSurfaceEvo, sd); + } + + // Program TMO LUT + + // XXX HDR TODO: Support other transfer functions + tmoLutSettings = &TMO_LUT_SETTINGS_REC2020; + + ctxDma = pHwState->tmoLut.pLutSurfaceEvo->dispCtxDma; + + nvDmaSetStartEvoMethod(pChannel, NVC57E_SET_TMO_CONTROL, 1); + nvDmaSetEvoMethodData(pChannel, + DRF_NUM(C57E, _SET_TMO_CONTROL, _SIZE, + NV_LUT_VSS_HEADER_SIZE + TMO_LUT_NUM_ENTRIES + 1) | + DRF_DEF(C57E, _SET_TMO_CONTROL, _INTERPOLATE, _ENABLE) | + DRF_NUM(C57E, _SET_TMO_CONTROL, _SAT_MODE, tmoLutSettings->satMode)); + + nvDmaSetStartEvoMethod(pChannel, NVC57E_SET_OFFSET_TMO_LUT, 1); + nvDmaSetEvoMethodData(pChannel, + DRF_NUM(C57E, _SET_OFFSET_TMO_LUT, _ORIGIN, offset >> 8)); + + nvDmaSetStartEvoMethod(pChannel, NVC57E_SET_CONTEXT_DMA_TMO_LUT, 1); + nvDmaSetEvoMethodData(pChannel, + DRF_NUM(C57E, _SET_CONTEXT_DMA_TMO_LUT, _HANDLE, ctxDma)); + + + // Low Intensity + + nvDmaSetStartEvoMethod(pChannel, NVC57E_SET_TMO_LOW_INTENSITY_ZONE, 1); + nvDmaSetEvoMethodData(pChannel, + DRF_NUM(C57E, _SET_TMO_LOW_INTENSITY_ZONE, _END, + tmoLutSettings->lowIntensityZoneEnd)); + + nvDmaSetStartEvoMethod(pChannel, NVC57E_SET_TMO_LOW_INTENSITY_VALUE, 1); + nvDmaSetEvoMethodData(pChannel, + DRF_NUM(C57E, _SET_TMO_LOW_INTENSITY_VALUE, _LIN_WEIGHT, + tmoLutSettings->lowIntensityValueLinWeight) | + DRF_NUM(C57E, _SET_TMO_LOW_INTENSITY_VALUE, _NON_LIN_WEIGHT, + tmoLutSettings->lowIntensityValueNonLinWeight) | + DRF_NUM(C57E, _SET_TMO_LOW_INTENSITY_VALUE, _THRESHOLD, + tmoLutSettings->lowIntensityValueThreshold)); + + // Medium Intensity + + nvDmaSetStartEvoMethod(pChannel, NVC57E_SET_TMO_MEDIUM_INTENSITY_ZONE, 1); + nvDmaSetEvoMethodData(pChannel, + DRF_NUM(C57E, _SET_TMO_MEDIUM_INTENSITY_ZONE, _START, + tmoLutSettings->medIntensityZoneStart) | + DRF_NUM(C57E, _SET_TMO_MEDIUM_INTENSITY_ZONE, _END, + tmoLutSettings->medIntensityZoneEnd)); + + nvDmaSetStartEvoMethod(pChannel, NVC57E_SET_TMO_MEDIUM_INTENSITY_VALUE, 1); + nvDmaSetEvoMethodData(pChannel, + DRF_NUM(C57E, _SET_TMO_MEDIUM_INTENSITY_VALUE, _LIN_WEIGHT, + tmoLutSettings->medIntensityValueLinWeight) | + DRF_NUM(C57E, _SET_TMO_MEDIUM_INTENSITY_VALUE, _NON_LIN_WEIGHT, + tmoLutSettings->medIntensityValueNonLinWeight) | + DRF_NUM(C57E, _SET_TMO_MEDIUM_INTENSITY_VALUE, _THRESHOLD, + tmoLutSettings->medIntensityValueThreshold)); + + // High Intensity + + nvDmaSetStartEvoMethod(pChannel, NVC57E_SET_TMO_HIGH_INTENSITY_ZONE, 1); + nvDmaSetEvoMethodData(pChannel, + DRF_NUM(C57E, _SET_TMO_HIGH_INTENSITY_ZONE, _START, + tmoLutSettings->highIntensityZoneStart)); + + nvDmaSetStartEvoMethod(pChannel, NVC57E_SET_TMO_HIGH_INTENSITY_VALUE, 1); + nvDmaSetEvoMethodData(pChannel, + DRF_NUM(C57E, _SET_TMO_HIGH_INTENSITY_VALUE, _LIN_WEIGHT, + tmoLutSettings->highIntensityValueLinWeight) | + DRF_NUM(C57E, _SET_TMO_HIGH_INTENSITY_VALUE, _NON_LIN_WEIGHT, + tmoLutSettings->highIntensityValueNonLinWeight) | + DRF_NUM(C57E, _SET_TMO_HIGH_INTENSITY_VALUE, _THRESHOLD, + tmoLutSettings->highIntensityValueThreshold)); +} + static void ConfigureCsc1C5(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel, NvBool enable) @@ -524,7 +895,7 @@ static void ConfigureCsc1C5(NVDevEvoPtr pDevEvo, if (enable) { const NvU32 sdMask = nvPeekEvoSubDevMask(pDevEvo); const NvU32 sd = (sdMask == 0) ? 0 : __builtin_ffs(sdMask) - 1; - NVDispHeadStateEvoRec *pHeadState; + const NVDispHeadStateEvoRec *pHeadState; /* * All callers of this path should push a single sd on the stack, @@ -534,8 +905,9 @@ static void ConfigureCsc1C5(NVDevEvoPtr pDevEvo, pHeadState = &pDevEvo->pDispEvo[sd]->headState[head]; - if ((pHeadState->procAmp.colorimetry == NVT_COLORIMETRY_BT2020RGB) || - (pHeadState->procAmp.colorimetry == NVT_COLORIMETRY_BT2020YCC)) { + if (pHeadState->hdr.outputState == NVKMS_HDR_OUTPUT_STATE_HDR) { + // XXX HDR TODO: Support other transfer functions + nvAssert(pHeadState->tf == NVKMS_OUTPUT_TF_PQ); matrix = LMSToRec2020RGB; } else { matrix = LMSToRec709RGB; @@ -709,24 +1081,17 @@ static void EvoInitDefaultLutC5(NVDevEvoPtr pDevEvo) nvAssert(pLut); for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { + NvU32 lutSize; + NvBool isLutModeVss; NVEvoLutDataRec *pData = pLut->subDeviceAddress[sd]; - NvU16 i; - ct_assert(NV_NUM_EVO_LUT_ENTRIES == 1025); - for (i = 0; i < 1024; i++) { - // nvdisplay 3 uses FP16 entries in the ILUT. - pData->base[NV_LUT_VSS_HEADER_SIZE + i].Red = - pData->base[NV_LUT_VSS_HEADER_SIZE + i].Green = - pData->base[NV_LUT_VSS_HEADER_SIZE + i].Blue = nvUnorm10ToFp16(i).v; + EvoSetupIdentityBaseLutC5(pData, + &pDevEvo->lut.defaultBaseLUTState[sd], + &lutSize, &isLutModeVss); - // nvdisplay 3 uses 16-bit fixed-point entries in the OLUT. - pData->output[NV_LUT_VSS_HEADER_SIZE + i].Red = - pData->output[NV_LUT_VSS_HEADER_SIZE + i].Green = - pData->output[NV_LUT_VSS_HEADER_SIZE + i].Blue = (i << (16 - 10)); - } - - pData->base[NV_LUT_VSS_HEADER_SIZE + 1024] = pData->base[NV_LUT_VSS_HEADER_SIZE + 1023]; - pData->output[NV_LUT_VSS_HEADER_SIZE + 1024] = pData->output[NV_LUT_VSS_HEADER_SIZE + 1023]; + EvoSetupIdentityOutputLutC5(pData, + &pDevEvo->lut.defaultOutputLUTState[sd], + &lutSize, &isLutModeVss); } } @@ -1311,6 +1676,7 @@ static void EvoSetOCsc0C5(NVDispEvoPtr pDispEvo, const NvU32 head) nvAssert(!"Unexpected colorimetry"); /* fallthrough */ case NVT_COLORIMETRY_RGB: + case NVT_COLORIMETRY_BT2020RGB: /* fallthrough; for RGB output, perform saturation adjustment in YUV709 */ case NVT_COLORIMETRY_YUV_709: CrYCbtoRGBMatrix = NvKmsMatrixToNvKmsMatrixF32(CrYCb709toRGBMatrix); @@ -1327,9 +1693,16 @@ static void EvoSetOCsc0C5(NVDispEvoPtr pDispEvo, const NvU32 head) ocsc0Matrix = nvMultiply3x4Matrix(&CrYCbtoRGBMatrix, &ocsc0Matrix); if (nvkms_output_rounding_fix()) { - ocsc0Matrix.m[0][3] = f32_add(ocsc0Matrix.m[0][3], inv2048F32); - ocsc0Matrix.m[1][3] = f32_add(ocsc0Matrix.m[1][3], inv2048F32); - ocsc0Matrix.m[2][3] = f32_add(ocsc0Matrix.m[2][3], inv2048F32); + /* + * XXX Only apply WAR for bug 2267663 for linear output TFs. Non-linear + * TFs could amplify the 1/2048 factor to the point of being + * perceptible. + */ + if (pHeadState->tf == NVKMS_OUTPUT_TF_NONE) { + ocsc0Matrix.m[0][3] = f32_add(ocsc0Matrix.m[0][3], inv2048F32); + ocsc0Matrix.m[1][3] = f32_add(ocsc0Matrix.m[1][3], inv2048F32); + ocsc0Matrix.m[2][3] = f32_add(ocsc0Matrix.m[2][3], inv2048F32); + } } nvDmaSetStartEvoMethod(pChannel, NVC57D_HEAD_SET_OCSC0COEFFICIENT_C00(head), 12); @@ -1358,12 +1731,15 @@ static void EvoSetProcAmpC5(NVDispEvoPtr pDispEvo, const NvU32 head, NvU32 dynRange, chromaLpf, chromaDownV; NvU32 colorimetry; + NVT_COLORIMETRY nvtColorimetry = pHeadState->procAmp.colorimetry; + NVT_COLOR_RANGE nvtColorRange = pHeadState->procAmp.colorRange; + /* These methods should only apply to a single pDpyEvo */ nvAssert(pDevEvo->subDevMaskStackDepth > 0); nvUpdateUpdateState(pDevEvo, updateState, pChannel); - switch (pHeadState->procAmp.colorimetry) { + switch (nvtColorimetry) { default: nvAssert(!"Unrecognized colorimetry"); // fall through @@ -1383,10 +1759,10 @@ static void EvoSetProcAmpC5(NVDispEvoPtr pDispEvo, const NvU32 head, break; } - if (pHeadState->procAmp.colorRange == NVT_COLOR_RANGE_FULL) { + if (nvtColorRange == NVT_COLOR_RANGE_FULL) { dynRange = DRF_DEF(C57D, _HEAD_SET_PROCAMP, _DYNAMIC_RANGE, _VESA); } else { - nvAssert(pHeadState->procAmp.colorRange == NVT_COLOR_RANGE_LIMITED); + nvAssert(nvtColorRange == NVT_COLOR_RANGE_LIMITED); dynRange = DRF_DEF(C57D, _HEAD_SET_PROCAMP, _DYNAMIC_RANGE, _CEA); } @@ -2672,10 +3048,10 @@ static void AssignPerWindowImpParams(NVC372_CTRL_IMP_WINDOW *pImpWindow, pImpWindow->inputScalerVerticalTaps = NVEvoScalerTapsToNum(pScaling->vTaps); - /* Assume we need a full 1025-entry window (input) LUT and no tone-mapping + /* Assume we need a full 1025-entry window (input) and tone-mapping * output (TMO) LUT. */ pImpWindow->lut = NVC372_CTRL_IMP_LUT_USAGE_1025; - pImpWindow->tmoLut = NVC372_CTRL_IMP_LUT_USAGE_NONE; + pImpWindow->tmoLut = NVC372_CTRL_IMP_LUT_USAGE_1025; } static void @@ -2789,24 +3165,6 @@ EvoFlipC3(NVDevEvoPtr pDevEvo, NVEvoUpdateState *updateState, NvBool bypassComposition); -static NvBool IsCscMatrixIdentity(const struct NvKmsCscMatrix *matrix) -{ - const struct NvKmsCscMatrix identity = NVKMS_IDENTITY_CSC_MATRIX; - - int y; - for (y = 0; y < 3; y++) { - int x; - - for (x = 0; x < 4; x++) { - if (matrix->m[y][x] != identity.m[y][x]) { - return FALSE; - } - } - } - - return TRUE; -} - /* * Returns TRUE iff the CSC should be enabled (i.e., the matrix is not the * identity matrix). @@ -2817,7 +3175,7 @@ static NvBool SetCscMatrixC3(NVEvoChannelPtr pChannel, NvU32 method = NVC37E_SET_CSC_RED2RED; int y; - if (IsCscMatrixIdentity(matrix)) { + if (nvIsCscMatrixIdentity(matrix)) { return FALSE; } @@ -2848,7 +3206,7 @@ static void SetCscMatrixC5Wrapper(NVEvoChannelPtr pChannel, { int y; - if (IsCscMatrixIdentity(matrix)) { + if (nvIsCscMatrixIdentity(matrix)) { nvDmaSetStartEvoMethod(pChannel, controlMethod, 1); nvDmaSetEvoMethodData(pChannel, disableMethodData); return; @@ -3040,7 +3398,12 @@ EvoProgramSemaphore6(NVDevEvoPtr pDevEvo, /*! Program Acq-only semaphore */ hCtxDma = offset = acqMode = relMode = value = 0; if (pHwState->syncObject.usingSyncpt) { - hCtxDma = pHwState->syncObject.u.syncpts.preCtxDma; + if (pHwState->syncObject.u.syncpts.isPreSyncptSpecified) { + NvU32 id = pHwState->syncObject.u.syncpts.preSyncpt; + hCtxDma = pDevEvo->preSyncptTable[id].hCtxDma; + } else { + hCtxDma = 0; + } offset = 0; acqMode = DRF_DEF(C67E, _SET_ACQ_SEMAPHORE_CONTROL, _ACQ_MODE, _CGEQ); value = pHwState->syncObject.u.syncpts.preValue; @@ -3380,6 +3743,7 @@ static NvBool IsSurfaceFormatUVSwapped( case NvKmsSurfaceMemoryFormatA2B10G10R10: case NvKmsSurfaceMemoryFormatX2B10G10R10: case NvKmsSurfaceMemoryFormatRF16GF16BF16AF16: + case NvKmsSurfaceMemoryFormatRF16GF16BF16XF16: case NvKmsSurfaceMemoryFormatR16G16B16A16: case NvKmsSurfaceMemoryFormatRF32GF32BF32AF32: return FALSE; @@ -3410,15 +3774,19 @@ static NvU32 nvHwFormatFromKmsFormatC3( case NvKmsSurfaceMemoryFormatR5G6B5: return NVC37E_SET_PARAMS_FORMAT_R5G6B5; case NvKmsSurfaceMemoryFormatA8R8G8B8: - case NvKmsSurfaceMemoryFormatX8R8G8B8: return NVC37E_SET_PARAMS_FORMAT_A8R8G8B8; + case NvKmsSurfaceMemoryFormatX8R8G8B8: + return NVC37E_SET_PARAMS_FORMAT_X8R8G8B8; case NvKmsSurfaceMemoryFormatA8B8G8R8: - case NvKmsSurfaceMemoryFormatX8B8G8R8: return NVC37E_SET_PARAMS_FORMAT_A8B8G8R8; + case NvKmsSurfaceMemoryFormatX8B8G8R8: + return NVC37E_SET_PARAMS_FORMAT_X8B8G8R8; case NvKmsSurfaceMemoryFormatA2B10G10R10: - case NvKmsSurfaceMemoryFormatX2B10G10R10: return NVC37E_SET_PARAMS_FORMAT_A2B10G10R10; + case NvKmsSurfaceMemoryFormatX2B10G10R10: + return NVC37E_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS; case NvKmsSurfaceMemoryFormatRF16GF16BF16AF16: + case NvKmsSurfaceMemoryFormatRF16GF16BF16XF16: return NVC37E_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16; case NvKmsSurfaceMemoryFormatR16G16B16A16: return NVC37E_SET_PARAMS_FORMAT_R16_G16_B16_A16; @@ -3505,6 +3873,7 @@ static NvU32 nvHwFormatFromKmsFormatC5( case NvKmsSurfaceMemoryFormatA2B10G10R10: case NvKmsSurfaceMemoryFormatX2B10G10R10: case NvKmsSurfaceMemoryFormatRF16GF16BF16AF16: + case NvKmsSurfaceMemoryFormatRF16GF16BF16XF16: case NvKmsSurfaceMemoryFormatR16G16B16A16: case NvKmsSurfaceMemoryFormatRF32GF32BF32AF32: return nvHwFormatFromKmsFormatC3(format); @@ -3527,6 +3896,8 @@ static NvU32 nvHwFormatFromKmsFormatC6( return NVC67E_SET_PARAMS_FORMAT_Y8___U8___V8_N444; case NvKmsSurfaceMemoryFormatY8___U8___V8_N420: return NVC67E_SET_PARAMS_FORMAT_Y8___U8___V8_N420; + case NvKmsSurfaceMemoryFormatX2B10G10R10: + return NVC67E_SET_PARAMS_FORMAT_A2B10G10R10; case NvKmsSurfaceMemoryFormatY8_U8__Y8_V8_N422: case NvKmsSurfaceMemoryFormatU8_Y8__V8_Y8_N422: case NvKmsSurfaceMemoryFormatY8___U8V8_N444: @@ -3556,8 +3927,8 @@ static NvU32 nvHwFormatFromKmsFormatC6( case NvKmsSurfaceMemoryFormatA8B8G8R8: case NvKmsSurfaceMemoryFormatX8B8G8R8: case NvKmsSurfaceMemoryFormatA2B10G10R10: - case NvKmsSurfaceMemoryFormatX2B10G10R10: case NvKmsSurfaceMemoryFormatRF16GF16BF16AF16: + case NvKmsSurfaceMemoryFormatRF16GF16BF16XF16: case NvKmsSurfaceMemoryFormatR16G16B16A16: case NvKmsSurfaceMemoryFormatRF32GF32BF32AF32: return nvHwFormatFromKmsFormatC5(format); @@ -3690,7 +4061,90 @@ EvoFlipC3(NVDevEvoPtr pDevEvo, } UpdateCompositionC3(pDevEvo, pChannel, - &pHwState->composition, updateState); + &pHwState->composition, updateState, + format); +} + +static void EvoSetupPQEotfBaseLutC5(NVEvoLutDataRec *pData, + enum NvKmsLUTState *lutState, + NvU32 *lutSize, + NvBool *isLutModeVss) +{ + NvU32 lutDataStartingIndex = NV_LUT_VSS_HEADER_SIZE; + NvU32 numEotfPQ512Entries = ARRAY_LEN(EotfPQ512Entries); + NvU32 eotfTableIdx; + NvU64 vssHead = 0; + NvU32 lutEntryCounter = 0, i; + + // Skip LUT data init if already done + if (*lutState == NvKmsLUTStatePQ) { + goto skipInit; + } + + // VSS Header + for (lutEntryCounter = 0; lutEntryCounter < NV_LUT_VSS_HEADER_SIZE; lutEntryCounter++) { + vssHead = 0; + for (i = 0; ((i < 16) && (((lutEntryCounter * 16) + i) < ARRAY_LEN(EotfPQ512SegSizesLog2))); i++) { + NvU64 temp = EotfPQ512SegSizesLog2[(lutEntryCounter * 16) + i]; + temp = temp << (i * 3); + vssHead |= temp; + } + nvkms_memcpy(&(pData->base[lutEntryCounter]), &vssHead, sizeof(NVEvoLutEntryRec)); + } + + for (eotfTableIdx = 0; eotfTableIdx < numEotfPQ512Entries; eotfTableIdx++) { + /* + * Values are in range [0.0, 125.0], will be scaled back by OLUT. + * XXX HDR TODO: Divide by 125.0 if output mode is not HDR? + */ + pData->base[eotfTableIdx + lutDataStartingIndex].Red = + pData->base[eotfTableIdx + lutDataStartingIndex].Green = + pData->base[eotfTableIdx + lutDataStartingIndex].Blue = + EotfPQ512Entries[eotfTableIdx]; + } + + // Copy the last entry for interpolation + pData->base[numEotfPQ512Entries + lutDataStartingIndex].Red = + pData->base[numEotfPQ512Entries + lutDataStartingIndex - 1].Red; + pData->base[numEotfPQ512Entries + lutDataStartingIndex].Green = + pData->base[numEotfPQ512Entries + lutDataStartingIndex - 1].Green; + pData->base[numEotfPQ512Entries + lutDataStartingIndex].Blue = + pData->base[numEotfPQ512Entries + lutDataStartingIndex - 1].Blue; + +skipInit: + *lutState = NvKmsLUTStatePQ; + *lutSize = NV_LUT_VSS_HEADER_SIZE + numEotfPQ512Entries + 1; + *isLutModeVss = TRUE; +} + +static void +EvoSetupIdentityBaseLutC5(NVEvoLutDataRec *pData, + enum NvKmsLUTState *lutState, + NvU32 *lutSize, + NvBool *isLutModeVss) +{ + int i; + + // Skip LUT data init if already done + if (*lutState == NvKmsLUTStateIdentity) { + goto skipInit; + } + + ct_assert(NV_NUM_EVO_LUT_ENTRIES == 1025); + + // nvdisplay 3 uses FP16 entries in the ILUT. + for (i = 0; i < 1024; i++) { + pData->base[NV_LUT_VSS_HEADER_SIZE + i].Red = + pData->base[NV_LUT_VSS_HEADER_SIZE + i].Green = + pData->base[NV_LUT_VSS_HEADER_SIZE + i].Blue = nvUnorm10ToFp16(i).v; + } + pData->base[NV_LUT_VSS_HEADER_SIZE + 1024] = + pData->base[NV_LUT_VSS_HEADER_SIZE + 1023]; + +skipInit: + *lutState = NvKmsLUTStateIdentity; + *lutSize = NV_LUT_VSS_HEADER_SIZE + NV_NUM_EVO_LUT_ENTRIES; + *isLutModeVss = FALSE; } static void @@ -3704,10 +4158,25 @@ EvoFlipC5Common(NVDevEvoPtr pDevEvo, NvBool swapUV; NvU32 hTaps, vTaps; NvBool scaling = FALSE; - NVLutSurfaceEvoPtr pLutSurfaceEvo = - EvoGetLutSurface3(pDevEvo, pChannel, pHwState); + NVLutSurfaceEvoPtr pLutSurfaceEvo = NULL; + NvU32 lutSize = NV_NUM_EVO_LUT_ENTRIES; + NvBool isLutModeVss = FALSE; + + NvU32 win = NV_EVO_CHANNEL_MASK_WINDOW_NUMBER(pChannel->channelMask); + NvU32 head = pDevEvo->headForWindow[win]; + + const NvU32 sdMask = nvPeekEvoSubDevMask(pDevEvo); + const NvU32 sd = (sdMask == 0) ? 0 : __builtin_ffs(sdMask) - 1; + const NVDispHeadStateEvoRec *pHeadState = &pDevEvo->pDispEvo[sd]->headState[head]; + + // XXX HDR TODO: Handle other colorspaces + // XXX HDR TODO: Enable custom input LUTs with HDR + if (pHwState->colorspace != NVKMS_INPUT_COLORSPACE_BT2100_PQ) { + pLutSurfaceEvo = EvoGetLutSurface3(pDevEvo, pChannel, pHwState); + } if (!EvoFlipC3Common(pDevEvo, pChannel, pHwState, updateState)) { + ConfigureTmoLut(pDevEvo, pHwState, pChannel); return; } @@ -3748,17 +4217,19 @@ EvoFlipC5Common(NVDevEvoPtr pDevEvo, nvAssert(!(scaling && bypassComposition)); /* - * If scaling, enable the CSC0 and CSC1 pipelines so that we can scale in - * the non-linear ICtCp domain. + * If scaling or tonemapping, we must enable the CSC0 and CSC1 pipelines. * - * If no scaling, just use CSC11 to convert from the input gamut to the - * output (panel) gamut, and disable everything else. + * If no scaling or tonemapping, just use CSC11 to convert from the input + * gamut to the output (panel) gamut, and disable everything else. */ - if (scaling) { - ConfigureCsc0C5(pDevEvo, pChannel, TRUE); + if (scaling || + nvNeedsTmoLut(pDevEvo, pChannel, pHwState, + nvGetHDRSrcMaxLum(pHwState), + pHeadState->hdr.staticMetadata.maxCLL)) { + ConfigureCsc0C5(pDevEvo, pChannel, pHwState->colorspace, TRUE); ConfigureCsc1C5(pDevEvo, pChannel, TRUE); } else { - ConfigureCsc0C5(pDevEvo, pChannel, FALSE); + ConfigureCsc0C5(pDevEvo, pChannel, pHwState->colorspace, FALSE); ConfigureCsc1C5(pDevEvo, pChannel, FALSE); SetCsc11MatrixC5(pChannel, &pHwState->cscMatrix); @@ -3766,10 +4237,37 @@ EvoFlipC5Common(NVDevEvoPtr pDevEvo, // In nvdisplay 3, an ILUT is required to convert the input surface to FP16, // unless the surface being displayed is already FP16 to begin with. - if (format == NvKmsSurfaceMemoryFormatRF16GF16BF16AF16 || bypassComposition) { + if ((format == NvKmsSurfaceMemoryFormatRF16GF16BF16AF16) || + (format == NvKmsSurfaceMemoryFormatRF16GF16BF16XF16) || bypassComposition) { + nvAssert((pHwState->colorspace == NVKMS_INPUT_COLORSPACE_SCRGB_LINEAR) || + (pHwState->colorspace == NVKMS_INPUT_COLORSPACE_NONE)); pLutSurfaceEvo = NULL; } else if (!pLutSurfaceEvo) { + NVEvoLutDataRec *pData = NULL; + pLutSurfaceEvo = pDevEvo->lut.defaultLut; + pData = pLutSurfaceEvo->subDeviceAddress[sd]; + + nvAssert(pData); + + switch (pHwState->colorspace) { + case NVKMS_INPUT_COLORSPACE_BT2100_PQ: + EvoSetupPQEotfBaseLutC5(pData, + &pDevEvo->lut.defaultBaseLUTState[sd], + &lutSize, &isLutModeVss); + break; + case NVKMS_INPUT_COLORSPACE_NONE: + EvoSetupIdentityBaseLutC5(pData, + &pDevEvo->lut.defaultBaseLUTState[sd], + &lutSize, &isLutModeVss); + break; + default: // XXX HDR TODO: Handle other colorspaces + nvAssert(FALSE); + EvoSetupIdentityBaseLutC5(pData, + &pDevEvo->lut.defaultBaseLUTState[sd], + &lutSize, &isLutModeVss); + break; + } } if (pLutSurfaceEvo) { @@ -3778,11 +4276,12 @@ EvoFlipC5Common(NVDevEvoPtr pDevEvo, nvDmaSetStartEvoMethod(pChannel, NVC57E_SET_ILUT_CONTROL, 1); nvDmaSetEvoMethodData(pChannel, - DRF_DEF(C57E, _SET_ILUT_CONTROL, _INTERPOLATE, _DISABLE) | + (isLutModeVss ? DRF_DEF(C57E, _SET_ILUT_CONTROL, _INTERPOLATE, _ENABLE) : + DRF_DEF(C57E, _SET_ILUT_CONTROL, _INTERPOLATE, _DISABLE)) | DRF_DEF(C57E, _SET_ILUT_CONTROL, _MIRROR, _DISABLE) | - DRF_DEF(C57E, _SET_ILUT_CONTROL, _MODE, _DIRECT10) | - DRF_NUM(C57E, _SET_ILUT_CONTROL, _SIZE, NV_LUT_VSS_HEADER_SIZE + - NV_NUM_EVO_LUT_ENTRIES)); + (isLutModeVss ? DRF_DEF(C57E, _SET_ILUT_CONTROL, _MODE, _SEGMENTED) : + DRF_DEF(C57E, _SET_ILUT_CONTROL, _MODE, _DIRECT10)) | + DRF_NUM(C57E, _SET_ILUT_CONTROL, _SIZE, lutSize)); nvDmaSetStartEvoMethod(pChannel, NVC57E_SET_OFFSET_ILUT, 1); nvDmaSetEvoMethodData(pChannel, @@ -3796,9 +4295,12 @@ EvoFlipC5Common(NVDevEvoPtr pDevEvo, nvDmaSetEvoMethodData(pChannel, 0); } + ConfigureTmoLut(pDevEvo, pHwState, pChannel); + UpdateCompositionC5(pDevEvo, pChannel, &pHwState->composition, updateState, - bypassComposition); + bypassComposition, + format); } static void @@ -3981,7 +4483,8 @@ static void UpdateCompositionC3(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel, const struct NvKmsCompositionParams *pCompParams, - NVEvoUpdateState *updateState) + NVEvoUpdateState *updateState, + enum NvKmsSurfaceMemoryFormat format) { NvU32 colorKeySelect; NvU32 compositionFactorSelect = 0; @@ -4099,6 +4602,32 @@ UpdateCompositionC3(NVDevEvoPtr pDevEvo, nvAssert(!"Invalid blend mode"); return; } + + /* Override the composition factors for X channel emulated surface format. */ + if (NvKmsIsCompositionModeUseAlpha(pCompParams->blendingMode[match]) && + ((pDevEvo->hal->caps.xEmulatedSurfaceMemoryFormats & NVBIT64(format)) != 0U)) { + if (match == 1) { + /* Clear the previously selected composition factors for match pixels. */ + compositionFactorSelect &= ~(DRF_MASK(NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT) << + DRF_SHIFT(NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT)); + compositionFactorSelect &= ~(DRF_MASK(NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT) << + DRF_SHIFT(NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT)); + + compositionFactorSelect |= + DRF_DEF(C37E, _SET_COMPOSITION_FACTOR_SELECT, _SRC_COLOR_FACTOR_MATCH_SELECT, _K1) | + DRF_DEF(C37E, _SET_COMPOSITION_FACTOR_SELECT, _DST_COLOR_FACTOR_MATCH_SELECT, _NEG_K1); + } else { + /* Clear the previously selected composition factors for no-match pixels. */ + compositionFactorSelect &= ~(DRF_MASK(NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT) << + DRF_SHIFT(NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT)); + compositionFactorSelect &= ~(DRF_MASK(NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT) << + DRF_SHIFT(NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT)); + + compositionFactorSelect |= + DRF_DEF(C37E, _SET_COMPOSITION_FACTOR_SELECT, _SRC_COLOR_FACTOR_NO_MATCH_SELECT, _K1) | + DRF_DEF(C37E, _SET_COMPOSITION_FACTOR_SELECT, _DST_COLOR_FACTOR_NO_MATCH_SELECT, _NEG_K1); + } + } } UpdateComposition(pDevEvo, @@ -4127,12 +4656,14 @@ UpdateCompositionC5(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel, const struct NvKmsCompositionParams *pCompParams, NVEvoUpdateState *updateState, - NvBool bypassComposition) + NvBool bypassComposition, + enum NvKmsSurfaceMemoryFormat format) { if (bypassComposition) { EvoBypassCompositionC5(pDevEvo, pChannel, updateState); } else { - UpdateCompositionC3(pDevEvo, pChannel, pCompParams, updateState); + UpdateCompositionC3(pDevEvo, pChannel, pCompParams, + updateState, format); } } @@ -4369,6 +4900,99 @@ static void EvoSetLUTContextDmaC3(const NVDispEvoRec *pDispEvo, nvPopEvoSubDevMask(pDevEvo); } +static void EvoSetupPQOetfOutputLutC5(NVEvoLutDataRec *pData, + enum NvKmsLUTState *lutState, + NvU32 *lutSize, + NvBool *isLutModeVss) +{ + NvU32 lutDataStartingIndex = NV_LUT_VSS_HEADER_SIZE; + NvU32 numOetfPQ512Entries = ARRAY_LEN(OetfPQ512Entries); + NvU32 oetfTableIdx; + NvU64 vssHead = 0; + NvU32 lutEntryCounter = 0, i; + + // Skip LUT data init if already done + if (*lutState == NvKmsLUTStatePQ) { + goto skipInit; + } + + // VSS Header + for (lutEntryCounter = 0; lutEntryCounter < NV_LUT_VSS_HEADER_SIZE; lutEntryCounter++) { + vssHead = 0; + for (i = 0; ((i < 16) && (((lutEntryCounter * 16) + i) < ARRAY_LEN(OetfPQ512SegSizesLog2))); i++) { + NvU64 temp = OetfPQ512SegSizesLog2[(lutEntryCounter * 16) + i]; + temp = temp << (i * 3); + vssHead |= temp; + } + nvkms_memcpy(&(pData->output[lutEntryCounter]), &vssHead, sizeof(NVEvoLutEntryRec)); + } + + for (oetfTableIdx = 0; oetfTableIdx < numOetfPQ512Entries; oetfTableIdx++) { + pData->output[oetfTableIdx + lutDataStartingIndex].Red = + pData->output[oetfTableIdx + lutDataStartingIndex].Green = + pData->output[oetfTableIdx + lutDataStartingIndex].Blue = + OetfPQ512Entries[oetfTableIdx]; + } + + // Copy the last entry for interpolation + pData->output[numOetfPQ512Entries + lutDataStartingIndex].Red = + pData->output[numOetfPQ512Entries + lutDataStartingIndex - 1].Red; + pData->output[numOetfPQ512Entries + lutDataStartingIndex].Green = + pData->output[numOetfPQ512Entries + lutDataStartingIndex - 1].Green; + pData->output[numOetfPQ512Entries + lutDataStartingIndex].Blue = + pData->output[numOetfPQ512Entries + lutDataStartingIndex - 1].Blue; + +skipInit: + *lutState = NvKmsLUTStatePQ; + *lutSize = numOetfPQ512Entries + 1; + *isLutModeVss = TRUE; +} + +static void EvoSetupIdentityOutputLutC5(NVEvoLutDataRec *pData, + enum NvKmsLUTState *lutState, + NvU32 *lutSize, + NvBool *isLutModeVss) +{ + NvU32 i; + + // Skip LUT data init if already done + if (*lutState == NvKmsLUTStateIdentity) { + goto skipInit; + } + + ct_assert(NV_NUM_EVO_LUT_ENTRIES == 1025); + + // nvdisplay 3 uses 16-bit fixed-point entries in the OLUT. + for (i = 0; i < 1024; i++) { + pData->output[NV_LUT_VSS_HEADER_SIZE + i].Red = + pData->output[NV_LUT_VSS_HEADER_SIZE + i].Green = + pData->output[NV_LUT_VSS_HEADER_SIZE + i].Blue = (i << (16 - 10)); + } + pData->output[NV_LUT_VSS_HEADER_SIZE + 1024] = + pData->output[NV_LUT_VSS_HEADER_SIZE + 1023]; + +skipInit: + *lutState = NvKmsLUTStateIdentity; + *lutSize = 1025; + *isLutModeVss = FALSE; +} + +static void SetupHDROutputLUT(NVDevEvoPtr pDevEvo, + const NVDispHeadStateEvoRec *pHeadState, + NvU32 sd, + enum NvKmsLUTState *lutState, + NvU32 *lutSize, + NvBool *isLutModeVss) +{ + NVLutSurfaceEvoPtr pLut = pDevEvo->lut.defaultLut; + NVEvoLutDataRec *pData = pLut->subDeviceAddress[sd]; + + // XXX HDR TODO: Support other transfer functions + nvAssert(pHeadState->tf == NVKMS_OUTPUT_TF_PQ); + + EvoSetupPQOetfOutputLutC5(pData, lutState, lutSize, isLutModeVss); +} + static void EvoSetLUTContextDmaC5(const NVDispEvoRec *pDispEvo, const int head, NVLutSurfaceEvoPtr pLutSurfEvo, @@ -4381,6 +5005,16 @@ static void EvoSetLUTContextDmaC5(const NVDispEvoRec *pDispEvo, NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; NVEvoChannelPtr pChannel = pDevEvo->core; NvU64 offset; + NvU32 sd, lutSize = NV_NUM_EVO_LUT_ENTRIES; + NvBool isLutModeVss = FALSE; + const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + NvBool disableOcsc0 = FALSE; + NvU32 fpNormScale = 0xFFFFFFFF; + + // XXX HDR TODO: Enable custom output LUTs with HDR + if (pHeadState->hdr.outputState == NVKMS_HDR_OUTPUT_STATE_HDR) { + enableOutputLut = FALSE; + } nvAssert(ctxdma || (!enableBaseLut && !enableOutputLut)); @@ -4393,6 +5027,48 @@ static void EvoSetLUTContextDmaC5(const NVDispEvoRec *pDispEvo, updateState, bypassComposition); + /* Set the ctxdma for the output LUT */ + + if (bypassComposition) { + ctxdma = 0; + + /* if we're not enabling the OLUT, OCSC0 also needs to be disabled */ + disableOcsc0 = TRUE; + } else if (!enableOutputLut) { + /* Use the default OLUT if the client didn't provide one */ + ctxdma = pDevEvo->lut.defaultLut->dispCtxDma; + + // Setup default OLUT + for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { + if (pHeadState->hdr.outputState == NVKMS_HDR_OUTPUT_STATE_HDR) { + SetupHDROutputLUT(pDevEvo, pHeadState, sd, + &pDevEvo->lut.defaultOutputLUTState[sd], + &lutSize, &isLutModeVss); + + disableOcsc0 = TRUE; + + /* + * Scale from [0.0, 125.0] to [0.0, 1.0] + * XXX HDR TODO: Assumes input is in this range, SDR is not. + */ + fpNormScale = 0xFFFFFFFF / 125; + } else { + NVLutSurfaceEvoPtr pLut = pDevEvo->lut.defaultLut; + NVEvoLutDataRec *pData = pLut->subDeviceAddress[sd]; + + EvoSetupIdentityOutputLutC5( + pData, + &pDevEvo->lut.defaultOutputLUTState[sd], + &lutSize, &isLutModeVss); + } + } + } + + if (disableOcsc0) { + nvDmaSetStartEvoMethod(pChannel, NVC57D_HEAD_SET_OCSC0CONTROL(head), 1); + nvDmaSetEvoMethodData(pChannel, DRF_DEF(C57D, _HEAD_SET_OCSC0CONTROL, _ENABLE, _DISABLE)); + } + /* Program the output LUT */ offset = offsetof(NVEvoLutDataRec, output); @@ -4400,39 +5076,27 @@ static void EvoSetLUTContextDmaC5(const NVDispEvoRec *pDispEvo, nvDmaSetStartEvoMethod(pChannel, NVC57D_HEAD_SET_OLUT_CONTROL(head), 1); nvDmaSetEvoMethodData(pChannel, - (!nvkms_output_rounding_fix() ? + ((isLutModeVss || !nvkms_output_rounding_fix()) ? DRF_DEF(C57D, _HEAD_SET_OLUT_CONTROL, _INTERPOLATE, _ENABLE) : DRF_DEF(C57D, _HEAD_SET_OLUT_CONTROL, _INTERPOLATE, _DISABLE)) | DRF_DEF(C57D, _HEAD_SET_OLUT_CONTROL, _MIRROR, _DISABLE) | - DRF_DEF(C57D, _HEAD_SET_OLUT_CONTROL, _MODE, _DIRECT10) | + (isLutModeVss ? DRF_DEF(C57D, _HEAD_SET_OLUT_CONTROL, _MODE, _SEGMENTED) : + DRF_DEF(C57D, _HEAD_SET_OLUT_CONTROL, _MODE, _DIRECT10)) | DRF_NUM(C57D, _HEAD_SET_OLUT_CONTROL, _SIZE, NV_LUT_VSS_HEADER_SIZE + - NV_NUM_EVO_LUT_ENTRIES)); + lutSize)); nvDmaSetStartEvoMethod(pChannel, NVC57D_HEAD_SET_OFFSET_OLUT(head), 1); nvDmaSetEvoMethodData(pChannel, DRF_NUM(C57D, _HEAD_SET_OFFSET_OLUT, _ORIGIN, offset >> 8)); nvDmaSetStartEvoMethod(pChannel, NVC57D_HEAD_SET_OLUT_FP_NORM_SCALE(head), 1); - nvDmaSetEvoMethodData(pChannel, 0xffffffff); - - /* Set the ctxdma for the output LUT */ - - if (bypassComposition) { - ctxdma = 0; - - /* if we're not enabling the OLUT, OCSC0 also needs to be disabled */ - nvDmaSetStartEvoMethod(pChannel, NVC57D_HEAD_SET_OCSC0CONTROL(head), 1); - nvDmaSetEvoMethodData(pChannel, DRF_DEF(C57D, _HEAD_SET_OCSC0CONTROL, _ENABLE, _DISABLE)); - } else if (!enableOutputLut) { - /* Use the default OLUT if the client didn't provide one */ - ctxdma = pDevEvo->lut.defaultLut->dispCtxDma; - } + nvDmaSetEvoMethodData(pChannel, fpNormScale); nvDmaSetStartEvoMethod(pChannel, NVC57D_HEAD_SET_CONTEXT_DMA_OLUT(head), 1); nvDmaSetEvoMethodData(pChannel, DRF_NUM(C57D, _HEAD_SET_CONTEXT_DMA_OLUT, _HANDLE, ctxdma)); - if (!bypassComposition) { + if (!disableOcsc0) { /* only enable OCSC0 after enabling the OLUT */ nvDmaSetStartEvoMethod(pChannel, NVC57D_HEAD_SET_OCSC0CONTROL(head), 1); nvDmaSetEvoMethodData(pChannel, DRF_DEF(C57D, _HEAD_SET_OCSC0CONTROL, _ENABLE, _ENABLE)); @@ -4693,27 +5357,6 @@ static void EvoParsePrecompScalerCaps5(NVEvoCapabilitiesPtr pEvoCaps, NVEvoScalerTapsCaps *pTapsCaps; NvU32 capA = ReadCapReg(pCaps, NVC573_PRECOMP_WIN_PIPE_HDR_CAPA(i)); NvU32 capD, capF; - NvBool csc00Present = FALSE, csc01Present = FALSE; - NvBool csc0LUTPresent = FALSE, csc1LUTPresent = FALSE; - NvBool csc10Present = FALSE, csc11Present = FALSE; - - csc00Present = FLD_TEST_DRF(C573, _PRECOMP_WIN_PIPE_HDR_CAPA, - _CSC00_PRESENT, _TRUE, capA); - csc01Present = FLD_TEST_DRF(C573, _PRECOMP_WIN_PIPE_HDR_CAPA, - _CSC01_PRESENT, _TRUE, capA); - pWinCaps->csc0MatricesPresent = (csc00Present && csc01Present); - - csc0LUTPresent = FLD_TEST_DRF(C573, _PRECOMP_WIN_PIPE_HDR_CAPA, - _CSC0LUT_PRESENT, _TRUE, capA); - csc1LUTPresent = FLD_TEST_DRF(C573, _PRECOMP_WIN_PIPE_HDR_CAPA, - _CSC1LUT_PRESENT, _TRUE, capA); - pWinCaps->cscLUTsPresent = (csc0LUTPresent && csc1LUTPresent); - - csc10Present = FLD_TEST_DRF(C573, _PRECOMP_WIN_PIPE_HDR_CAPA, - _CSC10_PRESENT, _TRUE, capA); - csc11Present = FLD_TEST_DRF(C573, _PRECOMP_WIN_PIPE_HDR_CAPA, - _CSC11_PRESENT, _TRUE, capA); - pWinCaps->csc1MatricesPresent = (csc10Present && csc11Present); pScalerCaps->present = FLD_TEST_DRF(C573, _PRECOMP_WIN_PIPE_HDR_CAPA, _SCLR_PRESENT, @@ -4824,6 +5467,37 @@ static void EvoParseCapabilityNotifierC5C6Common(NVEvoCapabilitiesPtr pEvoCaps, } } + for (i = 0; i < NVC573_SYS_CAPB_WINDOW_EXISTS__SIZE_1; i++) { + NVEvoWindowCaps *pWinCaps = &pEvoCaps->window[i]; + NvU32 capA = ReadCapReg(pCaps, NVC573_PRECOMP_WIN_PIPE_HDR_CAPA(i)); + + pWinCaps->tmoPresent = FLD_TEST_DRF(C573, _PRECOMP_WIN_PIPE_HDR_CAPA, + _TMO_PRESENT, _TRUE, capA); + + pWinCaps->csc0MatricesPresent = + FLD_TEST_DRF(C573, _PRECOMP_WIN_PIPE_HDR_CAPA, + _CSC00_PRESENT, _TRUE, capA) && + FLD_TEST_DRF(C573, _PRECOMP_WIN_PIPE_HDR_CAPA, + _CSC01_PRESENT, _TRUE, capA); + + pWinCaps->csc1MatricesPresent = + (FLD_TEST_DRF(C573, _PRECOMP_WIN_PIPE_HDR_CAPA, + _CSC10_PRESENT, _TRUE, capA) && + FLD_TEST_DRF(C573, _PRECOMP_WIN_PIPE_HDR_CAPA, + _CSC11_PRESENT, _TRUE, capA)); + + pWinCaps->cscLUTsPresent = + FLD_TEST_DRF(C573, _PRECOMP_WIN_PIPE_HDR_CAPA, + _CSC0LUT_PRESENT, _TRUE, capA) && + FLD_TEST_DRF(C573, _PRECOMP_WIN_PIPE_HDR_CAPA, + _CSC1LUT_PRESENT, _TRUE, capA); + + nvAssert(!pWinCaps->tmoPresent || + (pWinCaps->csc0MatricesPresent && + pWinCaps->csc1MatricesPresent && + pWinCaps->cscLUTsPresent)); + } + /* * To keep the design simple, NVKMS will expose support for precomp scaling * iff postcomp scaling isn't supported. This means that on chips which have @@ -4926,6 +5600,46 @@ static NvU32 UsableWindowCount(const NVEvoCapabilities *pEvoCaps) typedef typeof(EvoParseCapabilityNotifierC3) parse_caps_t; typedef typeof(nvHwFormatFromKmsFormatC3) get_hw_fmt_t; +static void SetHDRLayerCaps(NVDevEvoPtr pDevEvo) +{ + NVEvoSubDevPtr pEvoSubDev = &pDevEvo->gpus[0]; + NVEvoCapabilitiesPtr pEvoCaps = &pEvoSubDev->capabilities; + NvU32 win; +#if defined(DEBUG) + NvBool hdrLayerCapSet[NVKMS_MAX_LAYERS_PER_HEAD] = {FALSE}; +#endif + NvU32 numLayers[NVKMS_MAX_HEADS_PER_DISP] = {0}; + + /* + * XXX HDR: This assumes the window => layer mapping from + * nvAllocCoreChannelEvo(). + * + * TODO: Rework API to explicitly factor in window => layer mapping. + */ + for (win = 0; win < pDevEvo->numWindows; win++) { + NVEvoWindowCaps *pWinCaps = &pEvoCaps->window[win]; + const NvU32 head = pDevEvo->headForWindow[win]; + + /* + * XXX HDR: layerCaps assumes that every head has layers with the + * same capabilities. + * + * TODO: Rework API for per-head layerCaps if this assert trips. + */ + nvAssert(!hdrLayerCapSet[numLayers[head]] || + (pDevEvo->caps.layerCaps[numLayers[head]].supportsHDR == + pWinCaps->tmoPresent)); + + pDevEvo->caps.layerCaps[numLayers[head]].supportsHDR = pWinCaps->tmoPresent; + +#if defined(DEBUG) + hdrLayerCapSet[numLayers[head]] = TRUE; +#endif + + numLayers[head]++; + } +} + static NvBool EvoGetCapabilities3(NVDevEvoPtr pDevEvo, parse_caps_t *pParse, get_hw_fmt_t *pGetHwFmt, @@ -4945,7 +5659,6 @@ static NvBool EvoGetCapabilities3(NVDevEvoPtr pDevEvo, enum NvKmsRotation curRotation; NvBool reflectionX; NvBool reflectionY; - NvU32 win; NvU8 layer; /* With nvdisplay, capabilities are exposed in a separate object. */ @@ -5022,30 +5735,7 @@ static NvBool EvoGetCapabilities3(NVDevEvoPtr pDevEvo, pEvoSubDev->capabilities.misc.supportsHVFlip; } - /* - * On Volta, only WINDOWs (2N) and (2N + 1) can be attached to HEAD N. - * This is a HW restriction that's documented in the MFS. - * However, starting Turing, display HW supports flexible window - * mapping, which means that SW can freely attach any window to any - * head. - * - * On Orin VDK R4, for example, there's currently one usable head - * (HEAD 0), and 8 total usable windows (WINDOWs 0-7). - * This configuration is currently causing issues since this function - * assumes that the available number of heads and windows strictly - * abides by the fixed mapping enforced on Volta. - * - * This window mapping init sequence will eventually be updated to - * support flexible window mapping. But, until that happens, there - * should at least be a sanity check to make sure that the head that the - * current window maps to - per the Volta restriction - is actually - * available. - */ - - for (win = 0; win < pDevEvo->numWindows; win++) { - pDevEvo->headForWindow[win] = NVC37D_WINDOW_MAPPED_TO_HEAD(win); - nvAssert(pDevEvo->headForWindow[win] < pDevEvo->numHeads); - } + SetHDRLayerCaps(pDevEvo); for (i = NvKmsSurfaceMemoryFormatMin; i <= NvKmsSurfaceMemoryFormatMax; @@ -5937,13 +6627,27 @@ static NvBool SetAccelerators( static void EvoAccelerateChannelC3(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel, const NvU32 sd, + const NvBool trashPendingMethods, + const NvBool unblockMethodsInExecutation, NvU32 *pOldAccelerators) { + NvU32 accelMask = 0x0; + + if (trashPendingMethods) { + accelMask |= NVC370_CTRL_ACCL_TRASH_ONLY; + } + /* Start with a conservative set of accelerators; may need to add more * later. */ - const NvU32 accelMask = - NVC370_CTRL_ACCL_IGNORE_PI | - NVC370_CTRL_ACCL_SKIP_SEMA; + if (unblockMethodsInExecutation) { + accelMask |= NVC370_CTRL_ACCL_IGNORE_PI | + NVC370_CTRL_ACCL_SKIP_SEMA | + NVC370_CTRL_ACCL_IGNORE_FLIPLOCK; + } + + if (accelMask == 0x0) { + return; + } *pOldAccelerators = GetAccelerators(pDevEvo, pChannel, sd); @@ -5956,13 +6660,27 @@ static void EvoAccelerateChannelC3(NVDevEvoPtr pDevEvo, static void EvoResetChannelAcceleratorsC3(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel, const NvU32 sd, + const NvBool trashPendingMethods, + const NvBool unblockMethodsInExecutation, NvU32 oldAccelerators) { + NvU32 accelMask = 0x0; + + if (trashPendingMethods) { + accelMask |= NVC370_CTRL_ACCL_TRASH_ONLY; + } + /* Start with a conservative set of accelerators; may need to add more * later. */ - const NvU32 accelMask = - NVC370_CTRL_ACCL_IGNORE_PI | - NVC370_CTRL_ACCL_SKIP_SEMA; + if (unblockMethodsInExecutation) { + accelMask |= NVC370_CTRL_ACCL_IGNORE_PI | + NVC370_CTRL_ACCL_SKIP_SEMA | + NVC370_CTRL_ACCL_IGNORE_FLIPLOCK; + } + + if (accelMask == 0x0) { + return; + } /* Accelerate window channel. */ if (!SetAccelerators(pDevEvo, pChannel, sd, oldAccelerators, accelMask)) { @@ -6737,7 +7455,7 @@ static NvBool EvoComputeWindowScalingTapsC5(const NVDevEvoRec *pDevEvo, */ if ((pHwState->sizeIn.width != pHwState->sizeOut.width) || (pHwState->sizeIn.height != pHwState->sizeOut.height)) { - if (!IsCscMatrixIdentity(&pHwState->cscMatrix)) { + if (!nvIsCscMatrixIdentity(&pHwState->cscMatrix)) { return FALSE; } } @@ -6833,6 +7551,7 @@ NVEvoHAL nvEvoC3 = { NV_EVO3_SUPPORTED_DITHERING_MODES, /* supportedDitheringModes */ sizeof(NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS), /* impStructSize */ NV_EVO_SCALER_2TAPS, /* minScalerTaps */ + NV_EVO3_X_EMULATED_SURFACE_MEMORY_FORMATS_C3, /* xEmulatedSurfaceMemoryFormats */ }, }; @@ -6909,6 +7628,7 @@ NVEvoHAL nvEvoC5 = { NV_EVO3_SUPPORTED_DITHERING_MODES, /* supportedDitheringModes */ sizeof(NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS), /* impStructSize */ NV_EVO_SCALER_2TAPS, /* minScalerTaps */ + NV_EVO3_X_EMULATED_SURFACE_MEMORY_FORMATS_C5, /* xEmulatedSurfaceMemoryFormats */ }, }; @@ -6985,5 +7705,6 @@ NVEvoHAL nvEvoC6 = { NV_EVO3_SUPPORTED_DITHERING_MODES, /* supportedDitheringModes */ sizeof(NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS), /* impStructSize */ NV_EVO_SCALER_2TAPS, /* minScalerTaps */ + NV_EVO3_X_EMULATED_SURFACE_MEMORY_FORMATS_C6, /* xEmulatedSurfaceMemoryFormats */ }, }; diff --git a/src/nvidia-modeset/src/nvkms-flip.c b/src/nvidia-modeset/src/nvkms-flip.c index 78abc04a5..14e38b078 100644 --- a/src/nvidia-modeset/src/nvkms-flip.c +++ b/src/nvidia-modeset/src/nvkms-flip.c @@ -32,9 +32,14 @@ #include "nvkms-vrr.h" #include "nvkms-cursor.h" #include "nvkms-types.h" +#include "nvkms-dpy.h" +#include "nvkms-lut.h" +#include "nvkms-softfloat.h" #include "nvkms-sync.h" +#include "nvkms-difr.h" + static void SchedulePostFlipIMPTimer(NVDevEvoPtr pDevEvo); // The EVO .mfs file defines the maximum minPresentInterval to be 8. @@ -54,11 +59,12 @@ static void SchedulePostFlipIMPTimer(NVDevEvoPtr pDevEvo); * \return Return TRUE if all surfaceHandles could be successfully * translated into pSurfaceEvos. Otherwise, return FALSE. */ -static NvBool AssignSurfaceArray( +NvBool nvAssignSurfaceArray( const NVDevEvoRec *pDevEvo, const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, const NvKmsSurfaceHandle surfaceHandles[NVKMS_MAX_EYES], - const NVEvoChannelMask channelMask, + const NvBool isUsedByCursorChannel, + const NvBool isUsedByLayerChannel, NVSurfaceEvoPtr pSurfaceEvos[NVKMS_MAX_EYES]) { NvU32 eye; @@ -71,7 +77,8 @@ static NvBool AssignSurfaceArray( nvEvoGetSurfaceFromHandle(pDevEvo, pOpenDevSurfaceHandles, surfaceHandles[eye], - channelMask); + isUsedByCursorChannel, + isUsedByLayerChannel); if ((pSurfaceEvos[eye] == NULL) || (pSurfaceEvos[eye]->isoType != NVKMS_MEMORY_ISO)) { return FALSE; @@ -117,7 +124,8 @@ static NvBool AssignNIsoEvoHwState( nvEvoGetSurfaceFromHandle(pDevEvo, pOpenDevSurfaceHandles, pParamsNIso->surfaceHandle, - pChannel->channelMask); + FALSE /* isUsedByCursorChannel */, + TRUE /* isUsedByLayerChannel */); if (pSurfaceEvo == NULL) { return FALSE; } @@ -313,19 +321,15 @@ static NvBool AssignSemaphoreEvoHwState( } static NvBool AssignPreSyncptEvoHwState( - NVDevEvoRec *pDevEvo, - NVEvoChannel *pChannel, + const NVDevEvoRec *pDevEvo, const struct NvKmsChannelSyncObjects *pChannelSyncObjects, NVFlipSyncObjectEvoHwState *pFlipSyncObject) { - NvBool ret, bFound = FALSE; + NvBool ret; NvU32 id = 0; - NvU32 hSyncptCtxDma, hSyncpt; NvU32 value; enum NvKmsSyncptType preType; - nvAssert(pDevEvo->pAllSyncptUsedInCurrentFlip != NULL); - nvAssert(pChannelSyncObjects->useSyncpt); preType = pChannelSyncObjects->u.syncpts.pre.type; @@ -353,56 +357,17 @@ static NvBool AssignPreSyncptEvoHwState( if (id >= NV_SYNCPT_GLOBAL_TABLE_LENGTH) { return FALSE; } - /*! use id value to check the global table */ - bFound = (pDevEvo->preSyncptTable[id].hCtxDma != 0); - if (bFound == FALSE) { - /*! Register - allocate and bind ctxdma to syncpt*/ - ret = nvRmEvoAllocAndBindSyncpt(pDevEvo, - pChannel, - id, - &hSyncpt, - &hSyncptCtxDma); - if (!ret) { - nvAssert(!"Failed to register pre-syncpt"); - return FALSE; - } - - /*! Fill the Entry in Global Table */ - pDevEvo->preSyncptTable[id].hCtxDma = hSyncptCtxDma; - pDevEvo->preSyncptTable[id].hSyncpt = hSyncpt; - pDevEvo->preSyncptTable[id].channelMask |= pChannel->channelMask; - pDevEvo->pAllSyncptUsedInCurrentFlip[id] = NV_TRUE; - pDevEvo->preSyncptTable[id].id = id; - } else { - /*! - * syncpt found, just bind the context dma of this syncpt - * to the window if it is not already. - */ - if ((pDevEvo->preSyncptTable[id].channelMask & - pChannel->channelMask) == 0) { - - ret = nvRmEvoBindDispContextDMA(pDevEvo, - pChannel, - pDevEvo->preSyncptTable[id].hCtxDma); - if (ret != NVOS_STATUS_SUCCESS) { - nvAssert(!"Failed to bind pre-syncpt with ctxdma"); - return ret; - } - pDevEvo->preSyncptTable[id].channelMask |= pChannel->channelMask; - pDevEvo->pAllSyncptUsedInCurrentFlip[id] = NV_TRUE; - /*! hSyncpt already allocated for id*/ - } - } /*! Fill pre-syncpt related information in hardware state */ - pFlipSyncObject->u.syncpts.preCtxDma = pDevEvo->preSyncptTable[id].hCtxDma; + pFlipSyncObject->u.syncpts.preSyncpt = id; pFlipSyncObject->u.syncpts.preValue = value; + pFlipSyncObject->u.syncpts.isPreSyncptSpecified = TRUE; pFlipSyncObject->usingSyncpt = TRUE; return TRUE; } static NvBool AssignPostSyncptEvoHwState( - NVDevEvoRec *pDevEvo, + const NVDevEvoRec *pDevEvo, NVEvoChannel *pChannel, const struct NvKmsChannelSyncObjects *pChannelSyncObjects, NVFlipSyncObjectEvoHwState *pFlipSyncObject) @@ -510,68 +475,102 @@ static void FillPostSyncptReply( } } -NvBool nvHandleSyncptRegistration( - NVDevEvoRec *pDevEvo, - NvU32 head, - const struct NvKmsFlipCommonParams *pParams, - NVFlipEvoHwState *pFlipState) +static NvBool GetPreSyncptCtxDma(NVDevEvoRec *pDevEvo, + NVEvoChannel *pChannel, const NvU32 id) { - NvBool ret = TRUE; - NvU32 layer; + NvU32 hSyncptCtxDma, hSyncpt; - if (!pDevEvo->supportsSyncpts) { - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - if (pParams->layer[layer].syncObjects.specified && - pParams->layer[layer].syncObjects.val.useSyncpt) { - return FALSE; - } + /*! use id value to check the global table */ + if (pDevEvo->preSyncptTable[id].hCtxDma == 0) { + /*! Register - allocate and bind ctxdma to syncpt*/ + if (!nvRmEvoAllocAndBindSyncpt(pDevEvo, + pChannel, + id, + &hSyncpt, + &hSyncptCtxDma)) { + nvAssert(!"Failed to register pre-syncpt"); + return FALSE; } - return TRUE; + /*! Fill the Entry in Global Table */ + pDevEvo->preSyncptTable[id].hCtxDma = hSyncptCtxDma; + pDevEvo->preSyncptTable[id].hSyncpt = hSyncpt; + pDevEvo->preSyncptTable[id].channelMask |= pChannel->channelMask; + pDevEvo->preSyncptTable[id].id = id; + } else { + /*! + * syncpt found, just bind the context dma of this syncpt + * to the window if it is not already. + */ + if ((pDevEvo->preSyncptTable[id].channelMask & + pChannel->channelMask) == 0) { + + NvU32 ret = + nvRmEvoBindDispContextDMA(pDevEvo, + pChannel, + pDevEvo->preSyncptTable[id].hCtxDma); + if (ret != NVOS_STATUS_SUCCESS) { + nvAssert(!"Failed to bind pre-syncpt with ctxdma"); + } + pDevEvo->preSyncptTable[id].channelMask |= pChannel->channelMask; + /*! hSyncpt already allocated for id*/ + } } + return TRUE; +} + +static NvBool RegisterPreSyncpt(NVDevEvoRec *pDevEvo, + struct NvKmsFlipWorkArea *pWorkArea) +{ + NvU32 sd; + NvU32 ret = TRUE; + const NVDispEvoRec *pDispEvo; + pDevEvo->pAllSyncptUsedInCurrentFlip = nvCalloc(1, sizeof(NvBool) * NV_SYNCPT_GLOBAL_TABLE_LENGTH); if (pDevEvo->pAllSyncptUsedInCurrentFlip == NULL) { - return FALSE; + ret = FALSE; + goto done; } - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - if (!pParams->layer[layer].syncObjects.specified || - !pParams->layer[layer].syncObjects.val.useSyncpt) { - continue; - } + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + NvU32 head; + for (head = 0; head < ARRAY_LEN(pWorkArea->sd[sd].head); head++) { + NVFlipEvoHwState *pFlipState = + &pWorkArea->sd[sd].head[head].newState; + NvU32 layer; - nvkms_memset(&pFlipState->layer[layer].syncObject, - 0, - sizeof(pFlipState->layer[layer].syncObject)); + for (layer = 0; layer < ARRAY_LEN(pFlipState->layer); layer++) { + NVFlipSyncObjectEvoHwState *pFlipSyncObject = + &pFlipState->layer[layer].syncObject; + NvU32 preSyncpt = pFlipSyncObject->u.syncpts.preSyncpt; - ret = AssignPreSyncptEvoHwState(pDevEvo, + if (!pFlipState->dirty.layerSyncObjects[layer] || + !pFlipSyncObject->usingSyncpt || + !pFlipSyncObject->u.syncpts.isPreSyncptSpecified) { + continue; + } + + if (!GetPreSyncptCtxDma(pDevEvo, pDevEvo->head[head].layer[layer], - &pParams->layer[layer].syncObjects.val, - &pFlipState->layer[layer].syncObject); - if (!ret) { - nvAssert(!"Failed to store hw state for layer pre-syncpt"); - goto done; - } + preSyncpt)) { + ret = FALSE; + goto done; + } - ret = AssignPostSyncptEvoHwState(pDevEvo, - pDevEvo->head[head].layer[layer], - &pParams->layer[layer].syncObjects.val, - &pFlipState->layer[layer].syncObject); - if (!ret) { - nvAssert(!"Failed to store hw state for layer post-syncpt"); - goto done; + pDevEvo->pAllSyncptUsedInCurrentFlip[preSyncpt] = NV_TRUE; + } } } done: nvFree(pDevEvo->pAllSyncptUsedInCurrentFlip); pDevEvo->pAllSyncptUsedInCurrentFlip = NULL; + return ret; } - void nvClearFlipEvoHwState( NVFlipEvoHwState *pFlipState) { @@ -593,7 +592,7 @@ void nvInitFlipEvoHwState( const NvU32 head, NVFlipEvoHwState *pFlipState) { - const NVDispEvoRec *pDispEvo = pDevEvo->gpus[sd].pDispEvo; + NVDispEvoRec *pDispEvo = pDevEvo->gpus[sd].pDispEvo; const NVEvoSubDevHeadStateRec *pSdHeadState; NvU32 i; @@ -641,7 +640,9 @@ static NvBool IsLayerDirty(const struct NvKmsFlipCommonParams *pParams, pParams->layer[layer].completionNotifier.specified || pParams->layer[layer].syncObjects.specified || pParams->layer[layer].compositionParams.specified || - pParams->layer[layer].csc.specified; + pParams->layer[layer].csc.specified || + pParams->layer[layer].hdr.specified || + pParams->layer[layer].colorspace.specified; } /*! @@ -857,8 +858,7 @@ static NvBool AssignUsageBounds( pLayerFlipState->pSurfaceEvo[NVKMS_LEFT]->format, pDevEvo->caps.layerCaps[i].supportedSurfaceMemoryFormats); - /* Scaling is not currently supported for the main layer. Bug 3488083 */ - if (i != NVKMS_MAIN_LAYER && pDevEvo->hal->GetWindowScalingCaps) { + if (pDevEvo->hal->GetWindowScalingCaps) { const NVEvoScalerCaps *pScalerCaps = pDevEvo->hal->GetWindowScalingCaps(pDevEvo); @@ -873,6 +873,24 @@ static NvBool AssignUsageBounds( return FALSE; } } + + if (pLayerFlipState->maxDownscaleFactors.specified) { + struct NvKmsScalingUsageBounds *pTargetScaling = + &pFlipState->usage.layer[i].scaling; + + if ((pLayerFlipState->maxDownscaleFactors.vertical < + pTargetScaling->maxVDownscaleFactor) || + (pLayerFlipState->maxDownscaleFactors.horizontal < + pTargetScaling->maxHDownscaleFactor)) { + return FALSE; + } + + pTargetScaling->maxVDownscaleFactor = + pLayerFlipState->maxDownscaleFactors.vertical; + pTargetScaling->maxHDownscaleFactor = + pLayerFlipState->maxDownscaleFactors.horizontal; + } + } else { pUsage->layer[i].usable = FALSE; pUsage->layer[i].supportedSurfaceMemoryFormats = 0; @@ -882,44 +900,31 @@ static NvBool AssignUsageBounds( return TRUE; } -static NvBool OverrideUsageBounds(const NVDevEvoRec *pDevEvo, - NVFlipEvoHwState *pFlipState, - const struct NvKmsFlipCommonParams *pParams, - NvU32 sd, - NvU32 head, - const struct NvKmsUsageBounds *pPossibleUsage) +void +nvOverrideScalingUsageBounds(const NVDevEvoRec *pDevEvo, + NvU32 head, + NVFlipEvoHwState *pFlipState, + const struct NvKmsUsageBounds *pPossibleUsage) { NvU32 i; for (i = 0; i < pDevEvo->head[head].numLayers; i++) { + const NVFlipChannelEvoHwState *pLayerFlipState = &pFlipState->layer[i]; const struct NvKmsScalingUsageBounds *pPossibleScaling = - &pPossibleUsage->layer[i].scaling; + &pPossibleUsage->layer[i].scaling; struct NvKmsScalingUsageBounds *pTargetScaling = - &pFlipState->usage.layer[i].scaling; - NvU16 possibleV = pPossibleScaling->maxVDownscaleFactor; - NvU16 possibleH = pPossibleScaling->maxHDownscaleFactor; - NvU16 targetV = pTargetScaling->maxVDownscaleFactor; - NvU16 targetH = pTargetScaling->maxHDownscaleFactor; + &pFlipState->usage.layer[i].scaling; if (!pFlipState->usage.layer[i].usable) { continue; } - if (pParams->layer[i].maxDownscaleFactors.specified) { - NvU16 requestedV = pParams->layer[i].maxDownscaleFactors.vertical; - NvU16 requestedH = pParams->layer[i].maxDownscaleFactors.horizontal; + if (!pLayerFlipState->maxDownscaleFactors.specified) { + const NvU16 possibleV = pPossibleScaling->maxVDownscaleFactor; + const NvU16 possibleH = pPossibleScaling->maxHDownscaleFactor; + NvU16 targetV = pTargetScaling->maxVDownscaleFactor; + NvU16 targetH = pTargetScaling->maxHDownscaleFactor; - if ((requestedV < targetV) || (requestedH < targetH)) { - return FALSE; - } - - if ((requestedV > possibleV) || (requestedH > possibleH)) { - return FALSE; - } - - pTargetScaling->maxVDownscaleFactor = requestedV; - pTargetScaling->maxHDownscaleFactor = requestedH; - } else { /* * Calculate max H/V downscale factor by quantizing the range. * @@ -960,8 +965,6 @@ static NvBool OverrideUsageBounds(const NVDevEvoRec *pDevEvo, pTargetScaling->vTaps = pPossibleScaling->vTaps; pTargetScaling->vUpscalingAllowed = pPossibleScaling->vUpscalingAllowed; } - - return TRUE; } static NvBool FlipTimeStampValidForChannel( @@ -1038,6 +1041,69 @@ static NvBool ValidatePerLayerCompParams( return TRUE; } +static NvBool UpdateFlipEvoHwStateTf( + const NVDevEvoRec *pDevEvo, + const struct NvKmsFlipCommonParams *pParams, + NVFlipEvoHwState *pFlipState, + const NvU32 sd, + const NvU32 head) +{ + if (!pParams->tf.specified) { + return TRUE; + } + + // If enabling HDR... + // XXX HDR TODO: Handle other transfer functions + if (pParams->tf.val == NVKMS_OUTPUT_TF_PQ) { + NVDispEvoPtr pDispEvo = pDevEvo->pDispEvo[sd]; + + // Cannot be an SLI configuration. + // XXX HDR TODO: Test SLI Mosaic + HDR and remove this check + if (pDevEvo->numSubDevices > 1) { + return FALSE; + } + + // Sink must support HDR. + if (!nvIsHDRCapableHead(pDispEvo, nvHardwareHeadToApiHead(head))) { + return FALSE; + } + } + + pFlipState->dirty.tf = TRUE; + pFlipState->tf = pParams->tf.val; + + return TRUE; +} + +static NvBool UpdateFlipEvoHwStateHDRStaticMetadata( + const NVDevEvoRec *pDevEvo, + const struct NvKmsFlipCommonParams *pParams, + NVFlipEvoHwState *pFlipState, + NVFlipChannelEvoHwState *pHwState, + const NvU32 head, + const NvU32 layer) +{ + if (pParams->layer[layer].hdr.specified) { + if (pParams->layer[layer].hdr.enabled) { + // Don't allow enabling HDR on a layer that doesn't support it. + if (!pDevEvo->caps.layerCaps[layer].supportsHDR) { + return FALSE; + } + + pHwState->hdrStaticMetadata.val = + pParams->layer[layer].hdr.staticMetadata; + } + pHwState->hdrStaticMetadata.enabled = pParams->layer[layer].hdr.enabled; + + // Only mark dirty if layer supports HDR, otherwise this is a no-op. + if (pDevEvo->caps.layerCaps[layer].supportsHDR) { + pFlipState->dirty.hdrStaticMetadata = TRUE; + } + } + + return TRUE; +} + static NvBool UpdateLayerFlipEvoHwStateCommon( const struct NvKmsPerOpenDev *pOpenDev, const NVDevEvoRec *pDevEvo, @@ -1054,11 +1120,12 @@ static NvBool UpdateLayerFlipEvoHwStateCommon( NvBool ret; if (pParams->layer[layer].surface.specified) { - ret = AssignSurfaceArray(pDevEvo, - pOpenDevSurfaceHandles, - pParams->layer[layer].surface.handle, - pChannel->channelMask, - pHwState->pSurfaceEvo); + ret = nvAssignSurfaceArray(pDevEvo, + pOpenDevSurfaceHandles, + pParams->layer[layer].surface.handle, + FALSE /* isUsedByCursorChannel */, + TRUE /* isUsedByLayerChannel */, + pHwState->pSurfaceEvo); if (!ret) { return FALSE; } @@ -1082,28 +1149,49 @@ static NvBool UpdateLayerFlipEvoHwStateCommon( } pHwState->timeStamp = pParams->layer[layer].timeStamp; - /*! - * The NVKMS_SYNCPT_TYPE* types are handled earlier in the flip path (in - * the function nvHandleSyncptRegistration) - */ - if (pParams->layer[layer].syncObjects.specified && - !pParams->layer[layer].syncObjects.val.useSyncpt) { - - if (pParams->layer[layer].syncObjects.val.u.semaphores.acquire.surface.surfaceHandle != 0 || - pParams->layer[layer].syncObjects.val.u.semaphores.release.surface.surfaceHandle != 0) { - if (pParams->layer[layer].skipPendingFlips) { - return FALSE; - } + if (pParams->layer[layer].syncObjects.specified) { + if (!pDevEvo->supportsSyncpts && + pParams->layer[layer].syncObjects.val.useSyncpt) { + return FALSE; } - ret = AssignSemaphoreEvoHwState(pDevEvo, - pOpenDevSurfaceHandles, - pChannel, - sd, - &pParams->layer[layer].syncObjects.val, - &pHwState->syncObject); - if (!ret) { - return FALSE; + nvkms_memset(&pFlipState->layer[layer].syncObject, + 0, + sizeof(pFlipState->layer[layer].syncObject)); + + if (pParams->layer[layer].syncObjects.val.useSyncpt) { + ret = AssignPreSyncptEvoHwState(pDevEvo, + &pParams->layer[layer].syncObjects.val, + &pHwState->syncObject); + if (!ret) { + return FALSE; + } + pFlipState->dirty.layerSyncObjects[layer] = TRUE; + + ret = AssignPostSyncptEvoHwState(pDevEvo, + pDevEvo->head[head].layer[layer], + &pParams->layer[layer].syncObjects.val, + &pHwState->syncObject); + if (!ret) { + return FALSE; + } + } else { + if (pParams->layer[layer].syncObjects.val.u.semaphores.acquire.surface.surfaceHandle != 0 || + pParams->layer[layer].syncObjects.val.u.semaphores.release.surface.surfaceHandle != 0) { + if (pParams->layer[layer].skipPendingFlips) { + return FALSE; + } + } + + ret = AssignSemaphoreEvoHwState(pDevEvo, + pOpenDevSurfaceHandles, + pChannel, + sd, + &pParams->layer[layer].syncObjects.val, + &pHwState->syncObject); + if (!ret) { + return FALSE; + } } } @@ -1183,6 +1271,17 @@ static NvBool UpdateLayerFlipEvoHwStateCommon( pParams->layer[layer].compositionParams.val; } + if (!UpdateFlipEvoHwStateHDRStaticMetadata( + pDevEvo, pParams, pFlipState, + pHwState, head, layer)) { + return FALSE; + } + + if (pParams->layer[layer].colorspace.specified) { + pHwState->colorspace = + pParams->layer[layer].colorspace.val; + } + if (pHwState->composition.depth == 0) { pHwState->composition.depth = NVKMS_MAX_LAYERS_PER_HEAD - layer; @@ -1214,6 +1313,18 @@ static NvBool UpdateLayerFlipEvoHwStateCommon( } } + if (pParams->layer[layer].maxDownscaleFactors.specified) { + pFlipState->layer[layer].maxDownscaleFactors.vertical = + pParams->layer[layer].maxDownscaleFactors.vertical; + pFlipState->layer[layer].maxDownscaleFactors.horizontal = + pParams->layer[layer].maxDownscaleFactors.horizontal; + pFlipState->layer[layer].maxDownscaleFactors.specified = TRUE; + } else { + pFlipState->layer[layer].maxDownscaleFactors.vertical = 0; + pFlipState->layer[layer].maxDownscaleFactors.horizontal = 0; + pFlipState->layer[layer].maxDownscaleFactors.specified = FALSE; + } + pFlipState->dirty.layer[layer] = TRUE; return TRUE; @@ -1281,6 +1392,45 @@ static NvBool UpdateMainLayerFlipEvoHwState( return FALSE; } + pFlipState->skipLayerPendingFlips[NVKMS_MAIN_LAYER] = + pParams->layer[NVKMS_MAIN_LAYER].skipPendingFlips; + + return TRUE; +} + +NvBool +nvAssignCursorSurface(const struct NvKmsPerOpenDev *pOpenDev, + const NVDevEvoRec *pDevEvo, + const struct NvKmsSetCursorImageCommonParams *pImgParams, + NVSurfaceEvoPtr *pSurfaceEvo) + +{ + const NVEvoApiHandlesRec *pOpenDevSurfaceHandles = + nvGetSurfaceHandlesFromOpenDevConst(pOpenDev); + NVSurfaceEvoPtr pSurfaceEvos[NVKMS_MAX_EYES] = { }; + + if (!nvGetCursorImageSurfaces(pDevEvo, + pOpenDevSurfaceHandles, + pImgParams, + pSurfaceEvos)) { + return FALSE; + } + + /* XXX NVKMS TODO: add support for stereo cursor */ + if (pSurfaceEvos[NVKMS_RIGHT] != NULL) { + return FALSE; + } + + if (pSurfaceEvos[NVKMS_LEFT] != NULL) { + if (!ValidatePerLayerCompParams(&pImgParams->cursorCompParams, + &pDevEvo->caps.cursorCompositionCaps, + pSurfaceEvos[NVKMS_LEFT])) { + return FALSE; + } + } + + *pSurfaceEvo = pSurfaceEvos[NVKMS_LEFT]; + return TRUE; } @@ -1290,33 +1440,13 @@ static NvBool UpdateCursorLayerFlipEvoHwState( const struct NvKmsFlipCommonParams *pParams, NVFlipEvoHwState *pFlipState) { - const NVEvoApiHandlesRec *pOpenDevSurfaceHandles = - nvGetSurfaceHandlesFromOpenDevConst(pOpenDev); - if (pParams->cursor.imageSpecified) { - NVSurfaceEvoPtr pSurfaceEvos[NVKMS_MAX_EYES] = { }; - - if (!nvGetCursorImageSurfaces(pDevEvo, - pOpenDevSurfaceHandles, - &pParams->cursor.image, - pSurfaceEvos)) { + if (!nvAssignCursorSurface(pOpenDev, pDevEvo, &pParams->cursor.image, + &pFlipState->cursor.pSurfaceEvo)) { return FALSE; } - /* XXX NVKMS TODO: add support for stereo cursor */ - if (pSurfaceEvos[NVKMS_RIGHT] != NULL) { - return FALSE; - } - - pFlipState->cursor.pSurfaceEvo = pSurfaceEvos[NVKMS_LEFT]; - if (pFlipState->cursor.pSurfaceEvo != NULL) { - if (!ValidatePerLayerCompParams(&pParams->cursor.image.cursorCompParams, - &pDevEvo->caps.cursorCompositionCaps, - pFlipState->cursor.pSurfaceEvo)) { - return FALSE; - } - pFlipState->cursor.cursorCompParams = pParams->cursor.image.cursorCompParams; } @@ -1412,8 +1542,7 @@ NvBool nvUpdateFlipEvoHwState( const NvU32 head, const struct NvKmsFlipCommonParams *pParams, NVFlipEvoHwState *pFlipState, - NvBool allowVrr, - const struct NvKmsUsageBounds *pPossibleUsage) + NvBool allowVrr) { NvU32 layer; @@ -1431,6 +1560,10 @@ NvBool nvUpdateFlipEvoHwState( return FALSE; } + if (!UpdateFlipEvoHwStateTf(pDevEvo, pParams, pFlipState, sd, head)) { + return FALSE; + } + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { if (layer == NVKMS_MAIN_LAYER) { if (!UpdateMainLayerFlipEvoHwState(pOpenDev, pDevEvo, sd, head, @@ -1450,12 +1583,6 @@ NvBool nvUpdateFlipEvoHwState( return FALSE; } - if (!OverrideUsageBounds(pDevEvo, pFlipState, pParams, sd, head, - pPossibleUsage)) { - return FALSE; - } - - /* * If there is active cursor/cropped-window(overlay) without full screen * window(base/core) then NVKMS is supposed to disable MidFrame/DWCF @@ -1643,8 +1770,6 @@ ValidateMainFlipChannelEvoHwState(const NVDevEvoRec *pDevEvo, static NvBool ValidateOverlayFlipChannelEvoHwState(const NVDevEvoRec *pDevEvo, - const NvU32 head, - const NvU32 layer, const NVFlipChannelEvoHwState *pHwState) { const NVSurfaceEvoRec *pSurfaceEvo = pHwState->pSurfaceEvo[NVKMS_LEFT]; @@ -1658,8 +1783,6 @@ ValidateOverlayFlipChannelEvoHwState(const NVDevEvoRec *pDevEvo, */ struct NvKmsRect sourceFetchRect = {0}; - nvAssert(layer != NVKMS_MAIN_LAYER); - if (!ValidateFlipChannelEvoHwState(pHwState)) { return FALSE; } @@ -1684,6 +1807,140 @@ ValidateOverlayFlipChannelEvoHwState(const NVDevEvoRec *pDevEvo, return TRUE; } +static NvBool +ValidateHDR(const NVDevEvoRec *pDevEvo, + const NvU32 head, + const NVFlipEvoHwState *pFlipState) +{ + NvU32 staticMetadataCount = 0; + NvU32 layerSupportedCount = 0; + + NvU32 layer; + + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + if (pDevEvo->caps.layerCaps[layer].supportsHDR) { + layerSupportedCount++; + } + + if (pFlipState->layer[layer].hdrStaticMetadata.enabled) { + staticMetadataCount++; + + /* + * If HDR static metadata is enabled, we may need TMO. CSC11 will be + * used by NVKMS to convert from linear FP16 LMS to linear FP16 RGB. + * As such, the user-supplied precomp CSC can't be programmed into + * CSC11 in this case. + */ + if (!nvIsCscMatrixIdentity(&pFlipState->layer[layer].cscMatrix)) { + return FALSE; + } + + // Already checked in UpdateFlipEvoHwStateHDRStaticMetadata() + nvAssert(pDevEvo->caps.layerCaps[layer].supportsHDR); + } + } + + // If enabling HDR... + // XXX HDR TODO: Handle other transfer functions + if (pFlipState->tf == NVKMS_OUTPUT_TF_PQ) { + // At least one layer must have static metadata. + if (staticMetadataCount == 0) { + return FALSE; + } + + // At least one layer must support HDR, implied above. + nvAssert(layerSupportedCount != 0); + } + + // Only one layer can specify HDR static metadata. + // XXX HDR TODO: Support multiple layers with HDR static metadata + if (staticMetadataCount > 1) { + return FALSE; + } + + return TRUE; +} + +static NvBool +ValidateColorspace(const NVDevEvoRec *pDevEvo, + const NvU32 head, + const NVFlipEvoHwState *pFlipState) +{ + NvU32 layer; + + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + if ((pFlipState->layer[layer].colorspace != + NVKMS_INPUT_COLORSPACE_NONE)) { + + NVSurfaceEvoPtr pSurfaceEvo = + pFlipState->layer[layer].pSurfaceEvo[NVKMS_LEFT]; + const NvKmsSurfaceMemoryFormatInfo *pFormatInfo = + (pSurfaceEvo != NULL) ? + nvKmsGetSurfaceMemoryFormatInfo(pSurfaceEvo->format) : NULL; + + // XXX HDR TODO: Support YUV. + if ((pFormatInfo == NULL) || pFormatInfo->isYUV) { + return FALSE; + } + + // FP16 is only for use with scRGB. + if ((pFlipState->layer[layer].colorspace != + NVKMS_INPUT_COLORSPACE_SCRGB_LINEAR) && + ((pSurfaceEvo->format == + NvKmsSurfaceMemoryFormatRF16GF16BF16AF16) || + (pSurfaceEvo->format == + NvKmsSurfaceMemoryFormatRF16GF16BF16XF16))) { + return FALSE; + } + + // scRGB is only compatible with FP16. + if ((pFlipState->layer[layer].colorspace == + NVKMS_INPUT_COLORSPACE_SCRGB_LINEAR) && + !((pSurfaceEvo->format == + NvKmsSurfaceMemoryFormatRF16GF16BF16AF16) || + (pSurfaceEvo->format == + NvKmsSurfaceMemoryFormatRF16GF16BF16XF16))) { + return FALSE; + } + } + } + + return TRUE; +} + +static NvU32 ValidateCompositionDepth(const NVFlipEvoHwState *pFlipState, + const NvU32 layer) +{ + NvU32 tmpLayer; + + if (pFlipState->layer[layer].pSurfaceEvo[NVKMS_LEFT] == NULL) { + return TRUE; + } + + /* Depth should be different for each of the layers owned by the head */ + for (tmpLayer = 0; tmpLayer < ARRAY_LEN(pFlipState->layer); tmpLayer++) { + if (pFlipState->layer[tmpLayer].pSurfaceEvo[NVKMS_LEFT] == NULL) { + continue; + } + + if ((tmpLayer != layer) && + (pFlipState->layer[tmpLayer].composition.depth == + pFlipState->layer[layer].composition.depth)) { + return FALSE; + } + } + + /* Depth of the main layer should be the greatest one */ + if (pFlipState->layer[NVKMS_MAIN_LAYER].pSurfaceEvo[NVKMS_LEFT] != NULL) { + if (pFlipState->layer[NVKMS_MAIN_LAYER].composition.depth < + pFlipState->layer[layer].composition.depth) { + return FALSE; + } + } + + return TRUE; +} + /*! * Perform validation of the the given NVFlipEvoHwState. */ @@ -1696,29 +1953,8 @@ NvBool nvValidateFlipEvoHwState( NvU32 layer; for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - - if (pFlipState->layer[layer].pSurfaceEvo[NVKMS_LEFT] != NULL) { - NvU32 tmpLayer; - - /* Depth should be different for each of the layers owned by the head */ - for (tmpLayer = 0; tmpLayer < pDevEvo->head[head].numLayers; tmpLayer++) { - if (pFlipState->layer[tmpLayer].pSurfaceEvo[NVKMS_LEFT] == NULL) { - continue; - } - - if ((tmpLayer != layer) && - (pFlipState->layer[tmpLayer].composition.depth == - pFlipState->layer[layer].composition.depth)) { - return FALSE; - } - } - - /* Depth of the main layer should be the greatest one */ - if ((pFlipState->layer[NVKMS_MAIN_LAYER].pSurfaceEvo[NVKMS_LEFT] != NULL) && - (pFlipState->layer[layer].composition.depth > - pFlipState->layer[NVKMS_MAIN_LAYER].composition.depth)) { - return FALSE; - } + if (!ValidateCompositionDepth(pFlipState, layer)) { + return FALSE; } if (layer == NVKMS_MAIN_LAYER) { @@ -1728,18 +1964,38 @@ NvBool nvValidateFlipEvoHwState( pFlipState->viewPortPointIn)) { return FALSE; } - continue; - } + } else { + const NVFlipChannelEvoHwState *pMainLayerState = + &pFlipState->layer[NVKMS_MAIN_LAYER]; - if (pFlipState->dirty.layer[layer] && - !ValidateOverlayFlipChannelEvoHwState(pDevEvo, - head, - layer, - &pFlipState->layer[layer])) { - return FALSE; + /* + * No overlay layer should be enabled if the main + * layer is disabled. + */ + if ((pMainLayerState->pSurfaceEvo[NVKMS_LEFT] == NULL) && + (pFlipState->layer[layer].pSurfaceEvo[NVKMS_LEFT] != NULL)) { + return FALSE; + } + + if (!pFlipState->dirty.layer[layer]) { + continue; + } + + if (!ValidateOverlayFlipChannelEvoHwState(pDevEvo, + &pFlipState->layer[layer])) { + return FALSE; + } } } + if (!ValidateHDR(pDevEvo, head, pFlipState)) { + return FALSE; + } + + if (!ValidateColorspace(pDevEvo, head, pFlipState)) { + return FALSE; + } + /* XXX NVKMS TODO: validate cursor x,y against current viewport in? */ return ValidateUsageBounds(pDevEvo, @@ -1748,50 +2004,6 @@ NvBool nvValidateFlipEvoHwState( &pTimings->viewPort.possibleUsage); } - -/*! - * Validate overlay should be enabled only with valid core scanout surface. - */ -static NvBool ValidatePerDispState( - const NVDevEvoRec *pDevEvo, - const struct NvKmsFlipWorkArea *pWorkArea) -{ - const NVDispEvoRec *pDispEvo; - NvU32 sd; - - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - NvU32 head; - - for (head = 0; head < pDevEvo->numHeads; head++) { - const NVEvoSubDevHeadStateRec *pSdHeadState = - &pDevEvo->gpus[pDispEvo->displayOwner].headState[head]; - const NVSurfaceEvoRec *pMainScanoutSurface = - pSdHeadState->layer[NVKMS_MAIN_LAYER].pSurfaceEvo[NVKMS_LEFT]; - const NVFlipEvoHwState *pFlipState = - &pWorkArea->sd[sd].head[head].newState; - NvU32 layer; - - if (pFlipState->dirty.layer[NVKMS_MAIN_LAYER]) { - pMainScanoutSurface = - pFlipState->layer[NVKMS_MAIN_LAYER].pSurfaceEvo[NVKMS_LEFT]; - } - - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - if (layer == NVKMS_MAIN_LAYER) { - continue; - } - - if (pFlipState->layer[layer].pSurfaceEvo[NVKMS_LEFT] != NULL && - pMainScanoutSurface == NULL) { - return FALSE; - } - } - } - } - - return TRUE; -} - /* * Record in the updateState that the given channel needs interlocked * window immediate updates. @@ -1830,6 +2042,189 @@ static void UpdateUpdateFlipLockState(NVDevEvoPtr pDevEvo, } } +static void CancelSDRTransitionTimer(NVDispHeadStateEvoRec *pHeadState) +{ + nvkms_free_timer(pHeadState->hdr.sdrTransitionTimer); + pHeadState->hdr.sdrTransitionTimer = NULL; +} + +static void SDRTransition(void *dataPtr, NvU32 head) +{ + NVDispHeadStateEvoRec *pHeadState = dataPtr; + + nvAssert(pHeadState->hdr.outputState == + NVKMS_HDR_OUTPUT_STATE_TRANSITIONING_TO_SDR); + pHeadState->hdr.outputState = NVKMS_HDR_OUTPUT_STATE_SDR; + + if (pHeadState->pConnectorEvo) { + NVConnectorEvoPtr pConnectorEvo = pHeadState->pConnectorEvo; + NVDispEvoPtr pDispEvo = pConnectorEvo->pDispEvo; + NvU32 apiHead = nvHardwareHeadToApiHead(head); + NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[apiHead]; + NVDpyEvoPtr pDpyEvo = + nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo); + + nvUpdateInfoFrames(pDpyEvo); + } + + CancelSDRTransitionTimer(pHeadState); +} + +static void ScheduleSDRTransitionTimer(NVDispHeadStateEvoRec *pHeadState, + const NvU32 head) +{ + nvAssert(!pHeadState->hdr.sdrTransitionTimer); + + pHeadState->hdr.sdrTransitionTimer = + nvkms_alloc_timer(SDRTransition, + pHeadState, + head, + 2000000 /* 2 seconds */); +} + +// Adjust from EDID-encoded maxCLL/maxFALL to actual values in units of 1 cd/m2 +static inline NvU32 MaxCvToVal(NvU32 cv) +{ + // 50*2^(cv/32) + return f64_to_ui32( + f64_mul(ui32_to_f64(50), + nvKmsPow(ui32_to_f64(2), + f64_div(ui32_to_f64(cv), + ui32_to_f64(32)))), softfloat_round_near_even, FALSE); +} + +// Adjust from EDID-encoded minCLL to actual value in units of 0.0001 cd/m2 +static inline NvU32 MinCvToVal(NvU32 cv, NvU32 maxCLL) +{ + // 10,000 * (minCLL = (maxCLL * ((cv/255)^2 / 100))) + return f64_to_ui32( + f64_mul(ui32_to_f64(10000), + f64_mul(ui32_to_f64(maxCLL), + f64_div(nvKmsPow(f64_div(ui32_to_f64(cv), + ui32_to_f64(255)), + ui32_to_f64(2)), + ui32_to_f64(100)))), + softfloat_round_near_even, FALSE); +} + +static void UpdateHDR(NVDevEvoPtr pDevEvo, + const NVFlipEvoHwState *pFlipState, + const NvU32 sd, + const NvU32 head, + NVEvoUpdateState *updateState) +{ + NVDispEvoPtr pDispEvo = pDevEvo->gpus[sd].pDispEvo; + NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + NvU32 apiHead = nvHardwareHeadToApiHead(head); + NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[apiHead]; + NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo); + NvBool dirty = FALSE; + + if (pFlipState->dirty.tf) { + // XXX HDR TODO: Handle other transfer functions + if (pFlipState->tf == NVKMS_OUTPUT_TF_PQ) { + pHeadState->hdr.outputState = NVKMS_HDR_OUTPUT_STATE_HDR; + + CancelSDRTransitionTimer(pHeadState); + } else if (pHeadState->hdr.outputState == NVKMS_HDR_OUTPUT_STATE_HDR) { + pHeadState->hdr.outputState = + NVKMS_HDR_OUTPUT_STATE_TRANSITIONING_TO_SDR; + + ScheduleSDRTransitionTimer(pHeadState, head); + } + pHeadState->tf = pFlipState->tf; + + nvChooseCurrentColorSpaceAndRangeEvo( + pHeadState->timings.pixelDepth, + pHeadState->timings.yuv420Mode, + pHeadState->tf, + pDpyEvo->requestedColorSpace, + pDpyEvo->requestedColorRange, + &pApiHeadState->attributes.colorSpace, + &pApiHeadState->attributes.colorRange); + + /* Update hardware's current colorSpace and colorRange */ + nvUpdateCurrentHardwareColorSpaceAndRangeEvo( + pDispEvo, + head, + pApiHeadState->attributes.colorSpace, + pApiHeadState->attributes.colorRange, + updateState); + + dirty = TRUE; + } + + if (pFlipState->dirty.hdrStaticMetadata) { + NvU32 layer; + NvBool found = FALSE; + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + // Populate head with updated static metadata. + if (pFlipState->layer[layer].hdrStaticMetadata.enabled) { + const NVT_EDID_INFO *pInfo = &pDpyEvo->parsedEdid.info; + const NVT_HDR_STATIC_METADATA *pHdrInfo = + &pInfo->hdr_static_metadata_info; + + NvU32 targetMaxCLL = MaxCvToVal(pHdrInfo->max_cll); + + // Send this layer's metadata to the display. + pHeadState->hdr.staticMetadata = + pFlipState->layer[layer].hdrStaticMetadata.val; + + /* + * Prepare for tone mapping. If we expect to tone map and the + * EDID has valid lum values, mirror EDID lum values to prevent + * redundant tone mapping by the display. We will tone map to + * the specified maxCLL. + */ + if (nvNeedsTmoLut(pDevEvo, pDevEvo->head[head].layer[layer], + &pFlipState->layer[layer], + nvGetHDRSrcMaxLum( + &pFlipState->layer[layer]), + targetMaxCLL)) { + NvU32 targetMaxFALL = MaxCvToVal(pHdrInfo->max_fall); + if ((targetMaxCLL > 0) && + (targetMaxCLL <= 10000) && + (targetMaxCLL >= targetMaxFALL)) { + + NvU32 targetMinCLL = MinCvToVal(pHdrInfo->min_cll, + targetMaxCLL); + + pHeadState->hdr.staticMetadata. + maxDisplayMasteringLuminance = targetMaxCLL; + pHeadState->hdr.staticMetadata. + minDisplayMasteringLuminance = targetMinCLL; + pHeadState->hdr.staticMetadata.maxCLL = targetMaxCLL; + pHeadState->hdr.staticMetadata.maxFALL = targetMaxFALL; + } + } + + /* + * Only one layer can currently specify static metadata, + * verified by ValidateHDR(). + * + * XXX HDR TODO: Combine metadata from multiple layers. + */ + nvAssert(!found); + found = TRUE; + } + } + if (!found) { + nvkms_memset(&pHeadState->hdr.staticMetadata, 0, + sizeof(struct NvKmsHDRStaticMetadata)); + } + + dirty = TRUE; + } + + if (dirty) { + // Update OCSC / OLUT + nvEvoUpdateCurrentPalette(pDispEvo, head, FALSE); + + nvUpdateInfoFrames(pDpyEvo); + } +} + /*! * Program a flip on all requested layers on the specified head. * @@ -1848,6 +2243,8 @@ void nvFlipEvoOneHead( NvBool allowFlipLock, NVEvoUpdateState *updateState) { + NVDispEvoRec *pDispEvo = pDevEvo->gpus[sd].pDispEvo; + const NvU32 apiHead = nvHardwareHeadToApiHead(head); const NvU32 subDeviceMask = NVBIT(sd); const NVDispHeadStateEvoRec *pHeadState = &pDevEvo->gpus[sd].pDispEvo->headState[head]; @@ -1910,6 +2307,8 @@ void nvFlipEvoOneHead( pFlipState->cursor.y); } + UpdateHDR(pDevEvo, pFlipState, sd, head, updateState); + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { if (!pFlipState->dirty.layer[layer]) { continue; @@ -1934,6 +2333,11 @@ void nvFlipEvoOneHead( nvPushEvoSubDevMask(pDevEvo, subDeviceMask); + /* Inform DIFR about the upcoming flip. */ + if (pDevEvo->pDifrState) { + nvDIFRNotifyFlip(pDevEvo->pDifrState); + } + pDevEvo->hal->Flip(pDevEvo, pDevEvo->head[head].layer[layer], &pFlipState->layer[layer], @@ -1950,6 +2354,9 @@ void nvFlipEvoOneHead( pSdHeadState->targetDisableMidFrameAndDWCFWatermark = pFlipState->disableMidFrameAndDWCFWatermark; + + pDispEvo->apiHeadState[apiHead].viewPortPointIn = + pSdHeadState->viewPortPointIn; } static void ChangeSurfaceFlipRefCount( @@ -2021,31 +2428,30 @@ static void UnionScalingUsageBounds( ret->vUpscalingAllowed = a->vUpscalingAllowed || b->vUpscalingAllowed; } -struct NvKmsUsageBounds nvUnionUsageBounds( - const struct NvKmsUsageBounds *a, - const struct NvKmsUsageBounds *b) +void nvUnionUsageBounds(const struct NvKmsUsageBounds *a, + const struct NvKmsUsageBounds *b, + struct NvKmsUsageBounds *ret) { - struct NvKmsUsageBounds ret; NvU32 i; + nvkms_memset(ret, 0, sizeof(*ret)); + for (i = 0; i < ARRAY_LEN(a->layer); i++) { nvAssert(a->layer[i].usable == !!a->layer[i].supportedSurfaceMemoryFormats); nvAssert(b->layer[i].usable == !!b->layer[i].supportedSurfaceMemoryFormats); - ret.layer[i].usable = a->layer[i].usable || b->layer[i].usable; + ret->layer[i].usable = a->layer[i].usable || b->layer[i].usable; - ret.layer[i].supportedSurfaceMemoryFormats = + ret->layer[i].supportedSurfaceMemoryFormats = a->layer[i].supportedSurfaceMemoryFormats | b->layer[i].supportedSurfaceMemoryFormats; UnionScalingUsageBounds(&a->layer[i].scaling, &b->layer[i].scaling, - &ret.layer[i].scaling); + &ret->layer[i].scaling); } - - return ret; } NvBool UsageBoundsEqual( @@ -2120,10 +2526,9 @@ static NvBool AllocatePreFlipBandwidth(NVDevEvoPtr pDevEvo, timingsParams[head].activeRmId = pHeadState->activeRmId; timingsParams[head].pTimings = &pHeadState->timings; - currentAndNew[head] = nvUnionUsageBounds(pCurrent, pNew); - guaranteedAndCurrent[head] = nvUnionUsageBounds( - &pHeadState->timings.viewPort.guaranteedUsage, - pCurrent); + nvUnionUsageBounds(pCurrent, pNew, ¤tAndNew[head]); + nvUnionUsageBounds(&pHeadState->timings.viewPort.guaranteedUsage, + pCurrent, &guaranteedAndCurrent[head]); if (!ValidateUsageBounds(pDevEvo, head, @@ -2132,8 +2537,8 @@ static NvBool AllocatePreFlipBandwidth(NVDevEvoPtr pDevEvo, recheckIMP = TRUE; } - guaranteedAndCurrent[head] = - nvUnionUsageBounds(&guaranteedAndCurrent[head], pNew); + nvUnionUsageBounds(&guaranteedAndCurrent[head], pNew, + &guaranteedAndCurrent[head]); timingsParams[head].pUsage = &guaranteedAndCurrent[head]; } @@ -2208,8 +2613,7 @@ static NvBool PrepareToDoPreFlipIMP(NVDevEvoPtr pDevEvo, NvU32 layer; - *pPreFlipUsage = nvUnionUsageBounds(pNewUsage, - pCurrentUsage); + nvUnionUsageBounds(pNewUsage, pCurrentUsage, pPreFlipUsage); if (pDevEvo->hal->caps.supportsNonInterlockedUsageBoundsUpdate) { /* @@ -2351,7 +2755,7 @@ static void LowerDispBandwidth(void *dataPtr, NvU32 dataU32) timingsParams[head].activeRmId = pHeadState->activeRmId; timingsParams[head].pTimings = &pHeadState->timings; - guaranteedAndCurrent[head] = nvUnionUsageBounds(pGuaranteed, pCurrent); + nvUnionUsageBounds(pGuaranteed, pCurrent, &guaranteedAndCurrent[head]); timingsParams[head].pUsage = &guaranteedAndCurrent[head]; } @@ -2571,6 +2975,147 @@ static void SchedulePostFlipIMP(NVDevEvoPtr pDevEvo) } } +static NvBool GetAllowVrr(const NVDevEvoRec *pDevEvo, + const struct NvKmsFlipRequest *request, + NvBool *pApplyAllowVrr) +{ + NvU32 sd; + const NVDispEvoRec *pDispEvo; + NvU32 requestedHeadCount, activeHeadCount, dirtyMainLayerCount; + NvBool allowVrr = request->allowVrr; + + *pApplyAllowVrr = FALSE; + + /*! + * Count active and requested heads so we can make a decision about VRR + * and register syncpts if specified. + */ + requestedHeadCount = activeHeadCount = dirtyMainLayerCount = 0; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + NvU32 head; + const struct NvKmsFlipRequestOneSubDevice *pRequestOneSubDevice = + &request->sd[sd]; + + for (head = 0; head < ARRAY_LEN(pRequestOneSubDevice->head); head++) { + if (nvHeadIsActive(pDispEvo, head)) { + activeHeadCount++; + } + + if ((NVBIT(head) & + pRequestOneSubDevice->requestedHeadsBitMask) != 0x0) { + requestedHeadCount++; + + if (IsLayerDirty(&pRequestOneSubDevice->head[head], + NVKMS_MAIN_LAYER)) { + dirtyMainLayerCount++; + } + } + } + } + + /* + * Deactivate VRR if only a subset of the heads are requested or + * only a subset of the heads are being flipped. + */ + if ((activeHeadCount != requestedHeadCount) || + (activeHeadCount != dirtyMainLayerCount)) { + allowVrr = FALSE; + } + + /* + * Apply NvKmsFlipRequest::allowVrr + * only if at least one main layer is became dirty. + */ + if (dirtyMainLayerCount > 0) { + *pApplyAllowVrr = TRUE; + } + + return allowVrr; +} + +static void SkipLayerPendingFlips(NVDevEvoRec *pDevEvo, + const NvBool trashPendingMethods, + const NvBool unblockMethodsInExecutation, + struct NvKmsFlipWorkArea *pWorkArea) +{ + NvU64 startTime = 0; + const NvU32 timeout = 2000000; /* 2 seconds */ + struct { + struct { + struct { + NvU32 oldAccelMask; + } head[NVKMS_MAX_HEADS_PER_DISP]; + } sd[NVKMS_MAX_SUBDEVICES]; + } accelState = { }; + NvU32 sd, head; + + for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { + if (!pWorkArea->sd[sd].changed) { + continue; + } + + for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { + const NVFlipEvoHwState *pFlipState = + &pWorkArea->sd[sd].head[head].newState; + + if (!pFlipState->skipLayerPendingFlips[NVKMS_MAIN_LAYER]|| + !pFlipState->dirty.layer[NVKMS_MAIN_LAYER]) { + continue; + } + + pDevEvo->hal->AccelerateChannel( + pDevEvo, + pDevEvo->head[head].layer[NVKMS_MAIN_LAYER], + sd, + trashPendingMethods, + unblockMethodsInExecutation, + &accelState.sd[sd].head[head].oldAccelMask); + } + } + + for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { + if (!pWorkArea->sd[sd].changed) { + continue; + } + + for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { + const NVFlipEvoHwState *pFlipState = + &pWorkArea->sd[sd].head[head].newState; + + if (!pFlipState->skipLayerPendingFlips[NVKMS_MAIN_LAYER] || + !pFlipState->dirty.layer[NVKMS_MAIN_LAYER]) { + continue; + } + + if (unblockMethodsInExecutation) { + if (!nvEvoPollForNoMethodPending(pDevEvo, + sd, + pDevEvo->head[head].layer[NVKMS_MAIN_LAYER], + &startTime, + timeout)) { + nvAssert(!"Failed to idle the main layer channel"); + } + } else { + if (!nvEvoPollForEmptyChannel(pDevEvo->head[head].layer[NVKMS_MAIN_LAYER], + sd, + &startTime, + timeout)) { + nvAssert(!"Failed to empty the main layer channel"); + } + } + + pDevEvo->hal->ResetChannelAccelerators( + pDevEvo, + pDevEvo->head[head].layer[NVKMS_MAIN_LAYER], + sd, + trashPendingMethods, + unblockMethodsInExecutation, + accelState.sd[sd].head[head].oldAccelMask); + } + } +} + /*! * Program a flip on all requested layers on all requested heads on * all requested disps in NvKmsFlipRequest. @@ -2597,12 +3142,15 @@ NvBool nvFlipEvo(NVDevEvoPtr pDevEvo, NvBool skipUpdate, NvBool allowFlipLock) { + enum NvKmsVrrFlipType vrrFlipType = NV_KMS_VRR_FLIP_NON_VRR; + NvS32 vrrSemaphoreIndex = -1; NvU32 head, sd; - NvU32 requestedHeadCount, activeHeadCount, dirtyBaseChannelCount; + NvBool applyAllowVrr = FALSE; NvBool ret = FALSE; NvBool changed = FALSE; - NvBool allowVrr = request->allowVrr; NVDispEvoPtr pDispEvo; + const NvBool allowVrr = + GetAllowVrr(pDevEvo, request, &applyAllowVrr); struct NvKmsFlipWorkArea *pWorkArea = nvPreallocGet(pDevEvo, PREALLOC_TYPE_FLIP_WORK_AREA, sizeof(*pWorkArea)); @@ -2638,46 +3186,6 @@ NvBool nvFlipEvo(NVDevEvoPtr pDevEvo, } } - - /*! - * Count active and requested heads so we can make a decision about VRR - * and register syncpts if specified. - */ - requestedHeadCount = activeHeadCount = dirtyBaseChannelCount = 0; - - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - - const struct NvKmsFlipRequestOneSubDevice *pRequestOneSubDevice = - &request->sd[sd]; - - for (head = 0; head < ARRAY_LEN(pRequestOneSubDevice->head); head++) { - const NvBool headActive = nvHeadIsActive(pDispEvo, head); - - if (headActive) { - activeHeadCount++; - } - - if (NVBIT(head) & pRequestOneSubDevice->requestedHeadsBitMask) { - requestedHeadCount++; - } - - if (headActive) { - if (!nvHandleSyncptRegistration( - pDevEvo, - head, - &pRequestOneSubDevice->head[head], - &pWorkArea->sd[sd].head[head].newState)) { - goto done; - } - } - } - } - - /* Deactivate VRR if only a subset of the heads are requested */ - if (requestedHeadCount != activeHeadCount) { - allowVrr = FALSE; - } - /* Validate the flip parameters and update the work area. */ FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { @@ -2686,6 +3194,7 @@ NvBool nvFlipEvo(NVDevEvoPtr pDevEvo, for (head = 0; head < ARRAY_LEN(pRequestOneSubDevice->head); head++) { const NVDispHeadStateEvoRec *pHeadState; + const struct NvKmsUsageBounds *pPossibleUsage; const NvBool headActive = nvHeadIsActive(pDispEvo, head); if (!(NVBIT(head) & pRequestOneSubDevice->requestedHeadsBitMask)) { @@ -2697,6 +3206,7 @@ NvBool nvFlipEvo(NVDevEvoPtr pDevEvo, } pHeadState = &pDispEvo->headState[head]; + pPossibleUsage = &pHeadState->timings.viewPort.possibleUsage; if (!nvUpdateFlipEvoHwState( pOpenDev, @@ -2705,14 +3215,14 @@ NvBool nvFlipEvo(NVDevEvoPtr pDevEvo, head, &pRequestOneSubDevice->head[head], &pWorkArea->sd[sd].head[head].newState, - allowVrr, - &pHeadState->timings.viewPort.possibleUsage)) { + allowVrr)) { goto done; } - if (pWorkArea->sd[sd].head[head].newState.dirty.layer[NVKMS_MAIN_LAYER]) { - dirtyBaseChannelCount++; - } + nvOverrideScalingUsageBounds(pDevEvo, + head, + &pWorkArea->sd[sd].head[head].newState, + pPossibleUsage); if (!nvValidateFlipEvoHwState( pDevEvo, @@ -2722,20 +3232,17 @@ NvBool nvFlipEvo(NVDevEvoPtr pDevEvo, goto done; } + if (!nvSetTmoLutSurfacesEvo(pDevEvo, + &pWorkArea->sd[sd].head[head].newState, + head)) { + goto done; + } + pWorkArea->sd[sd].changed = TRUE; changed = TRUE; } } - /* Deactivate VRR if only a subset of the heads are being flipped */ - if (dirtyBaseChannelCount != activeHeadCount) { - allowVrr = FALSE; - } - - if (!ValidatePerDispState(pDevEvo, pWorkArea)) { - goto done; - } - /* If nothing changed, fail. */ if (!changed) { @@ -2752,6 +3259,10 @@ NvBool nvFlipEvo(NVDevEvoPtr pDevEvo, goto done; } + if (!RegisterPreSyncpt(pDevEvo, pWorkArea)) { + goto done; + } + if (!PrepareToDoPreFlipIMP(pDevEvo, pWorkArea)) { goto done; } @@ -2778,20 +3289,28 @@ NvBool nvFlipEvo(NVDevEvoPtr pDevEvo, head, &pWorkArea->sd[sd].head[head].newState, NV_TRUE); + + nvRefTmoLutSurfacesEvo( + pDevEvo, + &pWorkArea->sd[sd].head[head].newState, + head); } } PreFlipIMP(pDevEvo, pWorkArea); - /* Apply NvKmsFlipRequest::allowVrr only if a base channel has become dirty */ - if (dirtyBaseChannelCount > 0) { + if (!skipUpdate) { + /* Trash flips pending in channel which are not yet in execution */ + SkipLayerPendingFlips(pDevEvo, TRUE /* trashPendingMethods */, + FALSE /* unblockMethodsInExecutation */, + pWorkArea); + } + + if (applyAllowVrr) { nvSetVrrActive(pDevEvo, allowVrr); } for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { - const struct NvKmsFlipRequestOneSubDevice *pRequestOneSubDevice = - &request->sd[sd]; - NVEvoUpdateState updateState = { }; if (!pWorkArea->sd[sd].changed) { @@ -2801,22 +3320,6 @@ NvBool nvFlipEvo(NVDevEvoPtr pDevEvo, pDispEvo = pDevEvo->gpus[sd].pDispEvo; for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { - const NVFlipEvoHwState *pFlipState = - &pWorkArea->sd[sd].head[head].newState; - const struct NvKmsFlipCommonParams *pParams = - &pRequestOneSubDevice->head[head]; - - if (pParams->layer[NVKMS_MAIN_LAYER].skipPendingFlips && - pFlipState->dirty.layer[NVKMS_MAIN_LAYER] && - !skipUpdate) { - pDevEvo->hal->AccelerateChannel( - pDevEvo, - pDevEvo->head[head].layer[NVKMS_MAIN_LAYER], - sd, - &pWorkArea->sd[sd].head[head].oldAccelerators); - pWorkArea->sd[sd].head[head].accelerated = TRUE; - } - nvFlipEvoOneHead(pDevEvo, sd, head, &pWorkArea->sd[sd].head[head].newState, allowFlipLock, @@ -2834,6 +3337,11 @@ NvBool nvFlipEvo(NVDevEvoPtr pDevEvo, head, &pWorkArea->sd[sd].head[head].oldState, NV_FALSE); + + nvUnrefTmoLutSurfacesEvo( + pDevEvo, + &pWorkArea->sd[sd].head[head].oldState, + head); } FillPostSyncptReply(pDevEvo, @@ -2844,43 +3352,25 @@ NvBool nvFlipEvo(NVDevEvoPtr pDevEvo, } - { - NvU64 startTime = 0; - const NvU32 timeout = 2000000; /* 2 seconds */ - - for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { - if (!pWorkArea->sd[sd].changed) { - continue; - } - - for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { - if (!pWorkArea->sd[sd].head[head].accelerated) { - continue; - } - - if (!nvEvoPollForNoMethodPending(pDevEvo, - sd, - pDevEvo->head[head].layer[NVKMS_MAIN_LAYER], - &startTime, - timeout)) { - nvAssert(!"Timed out while idling base channel"); - } - - pDevEvo->hal->ResetChannelAccelerators( - pDevEvo, - pDevEvo->head[head].layer[NVKMS_MAIN_LAYER], - sd, - pWorkArea->sd[sd].head[head].oldAccelerators); - } - } + if (!skipUpdate) { + /* Unblock flips which are stuck in execution */ + SkipLayerPendingFlips(pDevEvo, FALSE /* trashPendingMethods */, + TRUE /* unblockMethodsInExecutation */, + pWorkArea); } - if (dirtyBaseChannelCount > 0) { - nvSetNextVrrFlipTypeAndIndex(pDevEvo, reply); + if (applyAllowVrr) { + vrrFlipType = nvGetActiveVrrType(pDevEvo); + vrrSemaphoreIndex = nvIncVrrSemaphoreIndex(pDevEvo); } else { // TODO Schedule vrr unstall; per-disp/per-device? } + if (reply != NULL) { + reply->vrrFlipType = vrrFlipType; + reply->vrrSemaphoreIndex = vrrSemaphoreIndex; + } + if (!skipUpdate) { // Note that usage bounds are not lowered here, because the flip // queued by this function may not occur until later. Instead, schedule @@ -2898,3 +3388,112 @@ done: return ret; } + +void nvApiHeadGetLayerSurfaceArray(const NVDispEvoRec *pDispEvo, + const NvU32 apiHead, + const NvU32 layer, + NVSurfaceEvoPtr pSurfaceEvos[NVKMS_MAX_EYES]) +{ + + const NvU32 sd = pDispEvo->displayOwner; + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + NvU32 head, headCount; + + nvAssert(apiHead != NV_INVALID_HEAD); + + headCount = 0; + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + const NVEvoSubDevHeadStateRec *pSdHeadState = + &pDispEvo->pDevEvo->gpus[sd].headState[head]; + NvU8 eye; + + if (headCount == 0) { + for (eye = NVKMS_LEFT; eye < NVKMS_MAX_EYES; eye++) { + pSurfaceEvos[eye] = + pSdHeadState->layer[layer].pSurfaceEvo[eye]; + } + } else { + for (eye = NVKMS_LEFT; eye < NVKMS_MAX_EYES; eye++) { + nvAssert(pSurfaceEvos[eye] == + pSdHeadState->layer[layer].pSurfaceEvo[eye]); + } + } + + headCount++; + } +} + +void nvApiHeadGetCursorInfo(const NVDispEvoRec *pDispEvo, + const NvU32 apiHead, + NVSurfaceEvoPtr *ppSurfaceEvo, + NvS16 *x, NvS16 *y) +{ + + const NvU32 sd = pDispEvo->displayOwner; + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + NvU32 head, headCount; + + nvAssert(apiHead != NV_INVALID_HEAD); + + headCount = 0; + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + const NVEvoSubDevHeadStateRec *pSdHeadState = + &pDispEvo->pDevEvo->gpus[sd].headState[head]; + + if (headCount == 0) { + *ppSurfaceEvo = pSdHeadState->cursor.pSurfaceEvo; + *x = pSdHeadState->cursor.x; + *y = pSdHeadState->cursor.y; + } else { + nvAssert(*ppSurfaceEvo == pSdHeadState->cursor.pSurfaceEvo); + nvAssert(*x == pSdHeadState->cursor.x); + nvAssert(*y == pSdHeadState->cursor.y); + } + + headCount++; + } +} + +void nvApiHeadSetViewportPointIn(const NVDispEvoRec *pDispEvo, + const NvU32 apiHead, + const NvU16 x, + const NvU16 y) +{ + NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + NVEvoUpdateState updateState = { }; + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + NvU16 hwViewportInWidth; + NvU32 head, headCount; + + nvAssert(apiHead != NV_INVALID_HEAD); + + headCount = 0; + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + const NVDispHeadStateEvoRec *pHeadState = + &pDispEvo->headState[head]; + const NVHwModeTimingsEvo *pTimings = + &pHeadState->timings; + + if (headCount == 0) { + hwViewportInWidth = pTimings->viewPort.in.width; + } else { + nvAssert(hwViewportInWidth == pTimings->viewPort.in.width); + } + + nvPushEvoSubDevMaskDisp(pDispEvo); + pDevEvo->hal->SetViewportPointIn(pDevEvo, head, + x + (hwViewportInWidth * pHeadState->tilePosition), y, + &updateState); + nvPopEvoSubDevMask(pDevEvo); + + headCount++; + } + + if (headCount != 0) { + nvEvoUpdateAndKickOff(pDispEvo, FALSE /* sync */, &updateState, + TRUE /* releaseElv */); + } +} diff --git a/src/nvidia-modeset/src/nvkms-hal.c b/src/nvidia-modeset/src/nvkms-hal.c index 6eb3acab5..1d8177068 100644 --- a/src/nvidia-modeset/src/nvkms-hal.c +++ b/src/nvidia-modeset/src/nvkms-hal.c @@ -58,7 +58,6 @@ enum NvKmsAllocDeviceStatus nvAssignEvoCaps(NVDevEvoPtr pDevEvo) { #define ENTRY(_classPrefix, \ _pEvoHal, \ - _supportsInbandStereoSignaling, \ _supportsDP13, \ _supportsHDMI20, \ _inputLutAppliesToBase, \ @@ -82,8 +81,6 @@ enum NvKmsAllocDeviceStatus nvAssignEvoCaps(NVDevEvoPtr pDevEvo) }, \ .evoCaps = { \ .supportsDP13 = _supportsDP13, \ - .supportsInbandStereoSignaling = \ - _supportsInbandStereoSignaling, \ .supportsHDMI20 = _supportsHDMI20, \ .validNIsoFormatMask = _validNIsoFormatMask, \ .inputLutAppliesToBase = _inputLutAppliesToBase, \ @@ -176,24 +173,23 @@ enum NvKmsAllocDeviceStatus nvAssignEvoCaps(NVDevEvoPtr pDevEvo) const NVEvoCapsRec evoCaps; } dispTable[] = { /* - * genericPageKind------------------------+ - * inputLutAppliesToBase ------------+ | - * supportsHDMI20 ----------------+ | | - * supportsDP13 ---------------+ | | | - * inbandStereoSignaling----+ | | | | - * pEvoHal --------------+ | | | | | - * windowClassPrefix | | | | | | - * classPrefix | | | | | | | - * | | | | | | | | + * genericPageKind---------------------+ + * inputLutAppliesToBase ---------+ | + * supportsHDMI20 -------------+ | | + * supportsDP13 ------------+ | | | + * pEvoHal --------------+ | | | | + * windowClassPrefix | | | | | + * classPrefix | | | | | | + * | | | | | | | */ - ENTRY_NVD(C7, C6, &nvEvoC6, 1, 1, 1, 0, TURING_GENERIC_KIND), - ENTRY_NVD(C6, C6, &nvEvoC6, 1, 1, 1, 0, TURING_GENERIC_KIND), - ENTRY_NVD(C5, C5, &nvEvoC5, 1, 1, 1, 0, TURING_GENERIC_KIND), - ENTRY_NVD(C3, C3, &nvEvoC3, 1, 1, 1, 0, FERMI_GENERIC_KIND), - ENTRY_EVO(98, &nvEvo94, 1, 1, 1, 1, FERMI_GENERIC_KIND), - ENTRY_EVO(97, &nvEvo94, 1, 1, 1, 1, FERMI_GENERIC_KIND), - ENTRY_EVO(95, &nvEvo94, 1, 0, 1, 1, FERMI_GENERIC_KIND), - ENTRY_EVO(94, &nvEvo94, 1, 0, 0, 1, FERMI_GENERIC_KIND), + ENTRY_NVD(C7, C6, &nvEvoC6, 1, 1, 0, TURING_GENERIC_KIND), + ENTRY_NVD(C6, C6, &nvEvoC6, 1, 1, 0, TURING_GENERIC_KIND), + ENTRY_NVD(C5, C5, &nvEvoC5, 1, 1, 0, TURING_GENERIC_KIND), + ENTRY_NVD(C3, C3, &nvEvoC3, 1, 1, 0, FERMI_GENERIC_KIND), + ENTRY_EVO(98, &nvEvo94, 1, 1, 1, FERMI_GENERIC_KIND), + ENTRY_EVO(97, &nvEvo94, 1, 1, 1, FERMI_GENERIC_KIND), + ENTRY_EVO(95, &nvEvo94, 0, 1, 1, FERMI_GENERIC_KIND), + ENTRY_EVO(94, &nvEvo94, 0, 0, 1, FERMI_GENERIC_KIND), }; int i; diff --git a/src/nvidia-modeset/src/nvkms-hdmi.c b/src/nvidia-modeset/src/nvkms-hdmi.c index c4c375b29..34f91eaa7 100644 --- a/src/nvidia-modeset/src/nvkms-hdmi.c +++ b/src/nvidia-modeset/src/nvkms-hdmi.c @@ -71,6 +71,7 @@ static void CalculateVideoInfoFrameColorFormat( // sets video infoframe colorspace (RGB/YUV). switch (pAttributesSet->colorSpace) { case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB: + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_BT2020RGB: pCtrl->color_space = NVT_VIDEO_INFOFRAME_BYTE1_Y1Y0_RGB; break; case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422: @@ -92,6 +93,9 @@ static void CalculateVideoInfoFrameColorFormat( case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB: pCtrl->colorimetry = NVT_COLORIMETRY_RGB; break; + case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_BT2020RGB: + pCtrl->colorimetry = NVT_COLORIMETRY_BT2020RGB; + break; case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422: case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444: if (hdTimings) { @@ -123,9 +127,13 @@ static void CalculateVideoInfoFrameColorFormat( break; } - // Only limited color range is allowed with YUV444 or YUV422 color spaces + /* + * Only limited color range is allowed with YUV444, YUV422 color spaces, or + * BT2020 colorimetry. + */ nvAssert(!(((pCtrl->color_space == NVT_VIDEO_INFOFRAME_BYTE1_Y1Y0_YCbCr422) || - (pCtrl->color_space == NVT_VIDEO_INFOFRAME_BYTE1_Y1Y0_YCbCr444)) && + (pCtrl->color_space == NVT_VIDEO_INFOFRAME_BYTE1_Y1Y0_YCbCr444) || + (pCtrl->colorimetry == NVT_COLORIMETRY_BT2020RGB)) && (pCtrl->rgb_quantization_range != NVT_VIDEO_INFOFRAME_BYTE3_Q1Q0_LIMITED_RANGE))); } @@ -434,11 +442,11 @@ static void SendInfoFrame(const NVDispEvoRec *pDispEvo, static void SendVideoInfoFrame(const NVDispEvoRec *pDispEvo, const NvU32 head, const NVAttributesSetEvoRec *pAttributesSet, - const NvBool hdTimings, - const NVT_VIDEO_INFOFRAME_CTRL *pCtrl, + const NVDispHeadInfoFrameStateEvoRec *pInfoFrameState, NVT_EDID_INFO *pEdidInfo) { - NVT_VIDEO_INFOFRAME_CTRL videoCtrl = *pCtrl; + NvBool hdTimings = pInfoFrameState->hdTimings; + NVT_VIDEO_INFOFRAME_CTRL videoCtrl = pInfoFrameState->ctrl; NVT_VIDEO_INFOFRAME VideoInfoFrame; NVT_STATUS status; @@ -519,8 +527,7 @@ SendHDMI3DVendorSpecificInfoFrame(const NVDispEvoRec *pDispEvo, void nvUpdateHdmiInfoFrames(const NVDispEvoRec *pDispEvo, const NvU32 head, const NVAttributesSetEvoRec *pAttributesSet, - const NvBool hdTimings, - const NVT_VIDEO_INFOFRAME_CTRL *pCtrl, + const NVDispHeadInfoFrameStateEvoRec *pInfoFrameState, NVDpyEvoRec *pDpyEvo) { if (!nvDpyIsHdmiEvo(pDpyEvo)) { @@ -537,8 +544,7 @@ void nvUpdateHdmiInfoFrames(const NVDispEvoRec *pDispEvo, SendVideoInfoFrame(pDispEvo, head, pAttributesSet, - hdTimings, - pCtrl, + pInfoFrameState, &pDpyEvo->parsedEdid.info); SendHDMI3DVendorSpecificInfoFrame(pDispEvo, diff --git a/src/nvidia-modeset/src/nvkms-headsurface-3d.c b/src/nvidia-modeset/src/nvkms-headsurface-3d.c new file mode 100644 index 000000000..6e6ee0a73 --- /dev/null +++ b/src/nvidia-modeset/src/nvkms-headsurface-3d.c @@ -0,0 +1,2062 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvkms-types.h" +#include "nvkms-headsurface-3d.h" +#include "nvkms-headsurface-priv.h" +#include "nvkms-rmapi.h" +#include "nvkms-utils.h" /* nvVEvoLog() */ +#include "nvkms-sync.h" /* nvKmsSemaphorePayloadOffset() */ +#include "nvkms-rm.h" /* nvRmEvoClassListCheck() */ + +#include "nvidia-push-methods.h" /* nvPushMethod(), nvPushSet*() */ +#include "nvidia-push-utils.h" /* nvPushKickoff(), nvPushGetNotifierCpuAddress() */ +#include "nvkms-push.h" + +#include "nv_list.h" /* nv_container_of */ + +#include "nvidia-3d-color-targets.h" /* nv3dSelectColorTarget() */ +#include "nvidia-3d-utils.h" /* nv3dSetSurfaceClip() */ +#include "nvidia-3d-constant-buffers.h" /* nv3dSelectCb() */ +#include "nvidia-3d-shader-constants.h" /* NV3D_CB_SLOT_MISC1 */ + +#include "nvidia-3d-imports.h" + +#include "g_nvidia-headsurface-shader-info.h" /* nvHeadSurfaceShaderInfo[] */ +#include "nvidia-headsurface-types.h" + +#include "nvkms-softfloat.h" + +#include "nvidia-headsurface-constants.h" + +#include + +#include /* NV20_SUBDEVICE_0 */ +#include /* FERMI_TWOD_A */ +#include /* KEPLER_CHANNEL_GPFIFO_A */ + +/* + * Define constant buffer indices used by headSurface. + */ +typedef enum { + NVKMS_HEADSURFACE_CONSTANT_BUFFER_FRAGMENT_PROGRAM, + NVKMS_HEADSURFACE_CONSTANT_BUFFER_VERTEX_PROGRAM, + NVKMS_HEADSURFACE_CONSTANT_BUFFER_STATIC_WARP_MESH, + NVKMS_HEADSURFACE_CONSTANT_BUFFER_COUNT, +} NvHs3dConstantBufferIndex; + + +void *nv3dImportAlloc(size_t size) +{ + return nvAlloc(size); +} + +void nv3dImportFree(void *ptr) +{ + nvFree(ptr); +} + +int nv3dImportMemCmp(const void *a, const void *b, size_t size) +{ + return nvkms_memcmp(a, b, size); +} + +void nv3dImportMemSet(void *s, int c, size_t size) +{ + nvkms_memset(s, c, size); +} + +void nv3dImportMemCpy(void *dest, const void *src, size_t size) +{ + nvkms_memcpy(dest, src, size); +} + +void nv3dImportMemMove(void *dest, const void *src, size_t size) +{ + nvkms_memmove(dest, src, size); +} + +NvBool nvHs3dAllocDevice(NVHsDeviceEvoRec *pHsDevice) +{ + Nv3dAllocDeviceParams params = { }; + + params.pPushDevice = &pHsDevice->pDevEvo->nvPush.device; + + if (!nv3dAllocDevice(¶ms, &pHsDevice->nv3d.device)) { + goto fail; + } + + return TRUE; + +fail: + nvHs3dFreeDevice(pHsDevice); + return FALSE; +} + +void nvHs3dFreeDevice(NVHsDeviceEvoRec *pHsDevice) +{ + if (pHsDevice == NULL) { + return; + } + + nv3dFreeDevice(&pHsDevice->nv3d.device); +} + +static void FreeNvPushChannel(NVHsChannelEvoRec *pHsChannel) +{ + const NVDispEvoRec *pDispEvo; + NVDevEvoPtr pDevEvo; + NvU32 h; + + if ((pHsChannel == NULL) || (pHsChannel->pDispEvo == NULL)) { + return; + } + + pDispEvo = pHsChannel->pDispEvo; + pDevEvo = pDispEvo->pDevEvo; + + nvPushFreeChannel(&pHsChannel->nvPush.channel); + + for (h = 0; h < ARRAY_LEN(pHsChannel->nvPush.handlePool); h++) { + if (pHsChannel->nvPush.handlePool[h] != 0) { + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, + pHsChannel->nvPush.handlePool[h]); + pHsChannel->nvPush.handlePool[h] = 0; + } + } +} + +static NvBool AllocNvPushChannel(NVHsChannelEvoRec *pHsChannel) +{ + NVDevEvoPtr pDevEvo = pHsChannel->pDispEvo->pDevEvo; + NvPushAllocChannelParams params = { }; + NvU32 h; + + params.engineType = NV2080_ENGINE_TYPE_GRAPHICS; + params.logNvDiss = FALSE; + params.noTimeout = FALSE; + params.ignoreChannelErrors = FALSE; + params.numNotifiers = NVKMS_HEADSURFACE_MAX_SEMAPHORES; + + /* + * XXX NVKMS HEADSURFACE TODO: Pushbuffer memory can be used faster than + * it's drained in complex headsurface swapgroup configurations, since + * there's no throttling on viewportin flips being scheduled in response to + * a vblank callback before previous rendering has completed. + * + * This size was raised from 8k to 128k to WAR the issue, and a proper fix + * will be added in bug 2397492, after which this limit can be lowered + * again. + * + * Throttling is now implemented using the RG line 1 interrupt headsurface + * rendering mechanism, so this limit can be lowered once the old + * vblank-triggered viewport flipping mechanism is removed. + */ + params.pushBufferSizeInBytes = 128 * 1024; /* arbitrary */ + + ct_assert(sizeof(params.handlePool) == + sizeof(pHsChannel->nvPush.handlePool)); + + for (h = 0; h < ARRAY_LEN(pHsChannel->nvPush.handlePool); h++) { + pHsChannel->nvPush.handlePool[h] = + nvGenerateUnixRmHandle(&pDevEvo->handleAllocator); + params.handlePool[h] = pHsChannel->nvPush.handlePool[h]; + } + + params.pDevice = &pDevEvo->nvPush.device; + + if (!nvPushAllocChannel(¶ms, &pHsChannel->nvPush.channel)) { + FreeNvPushChannel(pHsChannel); + return FALSE; + } + + return TRUE; +} + +static void FreeNv3dChannel(NVHsChannelEvoRec *pHsChannel) +{ + const NVDispEvoRec *pDispEvo; + NVDevEvoPtr pDevEvo; + + if ((pHsChannel == NULL) || (pHsChannel->pDispEvo == NULL)) { + return; + } + + pDispEvo = pHsChannel->pDispEvo; + pDevEvo = pDispEvo->pDevEvo; + + nv3dFreeChannelSurface(&pHsChannel->nv3d.channel); + nv3dFreeChannelObject(&pHsChannel->nv3d.channel); + nv3dFreeChannelState(&pHsChannel->nv3d.channel); + + if (pHsChannel->nv3d.handle != 0) { + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, + pHsChannel->nv3d.handle); + pHsChannel->nv3d.handle = 0; + } +} + + +static NvBool AllocNv3dChannel(NVHsChannelEvoRec *pHsChannel) +{ + NVDevEvoPtr pDevEvo = pHsChannel->pDispEvo->pDevEvo; + Nv3dAllocChannelStateParams stateParams = { }; + Nv3dAllocChannelObjectParams objectParams = { }; + + stateParams.p3dDevice = &pDevEvo->pHsDevice->nv3d.device; + stateParams.numTextures = NVKMS_HEADSURFACE_TEXINFO_NUM; + stateParams.numConstantBuffers = NVKMS_HEADSURFACE_CONSTANT_BUFFER_COUNT; + stateParams.numTextureBindings = + NVIDIA_HEADSURFACE_UNIFORM_SAMPLER_BINDING_NUM; + + /* + * XXX NVKMS HEADSURFACE TODO: set hasFrameBoundaries to TRUE, but how to + * trigger a frame boundary? + */ + stateParams.hasFrameBoundaries = FALSE; + + if (!nv3dAllocChannelState(&stateParams, &pHsChannel->nv3d.channel)) { + goto fail; + } + + pHsChannel->nv3d.handle = nvGenerateUnixRmHandle(&pDevEvo->handleAllocator); + + objectParams.pPushChannel = &pHsChannel->nvPush.channel; + objectParams.handle[0] = pHsChannel->nv3d.handle; + + if (!nv3dAllocChannelObject(&objectParams, &pHsChannel->nv3d.channel)) { + goto fail; + } + + if (!nv3dAllocChannelSurface(&pHsChannel->nv3d.channel)) { + goto fail; + } + + return TRUE; + +fail: + FreeNv3dChannel(pHsChannel); + return FALSE; +} + +static void FreeNv2dChannel(NVHsChannelEvoRec *pHsChannel) +{ + const NVDispEvoRec *pDispEvo; + NVDevEvoPtr pDevEvo; + + if ((pHsChannel == NULL) || (pHsChannel->pDispEvo == NULL)) { + return; + } + + pDispEvo = pHsChannel->pDispEvo; + pDevEvo = pDispEvo->pDevEvo; + + if (pHsChannel->nv2d.handle != 0) { + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, + pHsChannel->nv2d.handle); + pHsChannel->nv2d.handle = 0; + } +} + +static NvBool AllocNv2dChannel(NVHsChannelEvoRec *pHsChannel) +{ + NVDevEvoPtr pDevEvo = pHsChannel->pDispEvo->pDevEvo; + NvU32 ret; + + if (!nvRmEvoClassListCheck(pDevEvo, FERMI_TWOD_A)) { + goto fail; + } + + pHsChannel->nv2d.handle = nvGenerateUnixRmHandle(&pDevEvo->handleAllocator); + + ret = nvRmApiAlloc(nvEvoGlobal.clientHandle, + pHsChannel->nvPush.channel.channelHandle[0], + pHsChannel->nv2d.handle, + FERMI_TWOD_A, + NULL); + + if (ret != NVOS_STATUS_SUCCESS) { + goto fail; + } + + return TRUE; + +fail: + FreeNv2dChannel(pHsChannel); + return FALSE; +} + +NvBool nvHs3dAllocChannel(NVHsChannelEvoPtr pHsChannel) +{ + const NvU32 dispSdMask = NVBIT(pHsChannel->pDispEvo->displayOwner); + NvPushChannelPtr p = &pHsChannel->nvPush.channel; + + if (!AllocNvPushChannel(pHsChannel)) { + goto fail; + } + + if (!AllocNv3dChannel(pHsChannel)) { + goto fail; + } + + if (!AllocNv2dChannel(pHsChannel)) { + goto fail; + } + + p = &pHsChannel->nvPush.channel; + + /* + * pHsChannel will only be used on this pDispEvo; set the channel's + * subdevice mask to this pDispEvo's subdevice mask. + */ + nvPushSetSubdeviceMask(p, dispSdMask); + + if (!nv3dInitChannel(&pHsChannel->nv3d.channel)) { + goto fail; + } + + nvPushKickoff(p); + + return TRUE; + +fail: + nvHs3dFreeChannel(pHsChannel); + return FALSE; +} + +void nvHs3dFreeChannel(NVHsChannelEvoPtr pHsChannel) +{ + if (pHsChannel == NULL) { + return; + } + + FreeNv2dChannel(pHsChannel); + + FreeNv3dChannel(pHsChannel); + + FreeNvPushChannel(pHsChannel); +} + +/*! + * HsSurfaceFormatTable[] defines a mapping between NvKmsSurfaceMemoryFormat + * enum values, NV902D_SET_SRC_FORMAT values, NV9097_SET_COLOR_TARGET_FORMAT + * values and various nvidia-3d values needed to assign an Nv3dRenderTexInfo + * structure. + */ +static const struct { + NvU32 cl902d; + NvU32 cl9097; + enum Nv3dTexHeaderComponentSizes sizes; + enum Nv3dTexHeaderDataType dataType; + struct { + enum Nv3dTexHeaderSource x; + enum Nv3dTexHeaderSource y; + enum Nv3dTexHeaderSource z; + enum Nv3dTexHeaderSource w; + } source; +} HsSurfaceFormatTable[] = { + +#define ENTRY(_nvKmsFmt, _cl902d, _cl9097, _nv3dSizes, _nv3dDataType, _x, _y, _z, _w) \ + \ + [NvKmsSurfaceMemoryFormat ## _nvKmsFmt] = { \ + .cl902d = NV902D_SET_SRC_FORMAT_V_ ## _cl902d, \ + .cl9097 = NV9097_SET_COLOR_TARGET_FORMAT_V_ ## _cl9097, \ + .sizes = NV3D_TEXHEAD_ ## _nv3dSizes, \ + .dataType = NV3D_TEXHEAD_NUM_ ## _nv3dDataType, \ + .source.x = NV3D_TEXHEAD_IN_ ## _x, \ + .source.y = NV3D_TEXHEAD_IN_ ## _y, \ + .source.z = NV3D_TEXHEAD_IN_ ## _z, \ + .source.w = NV3D_TEXHEAD_IN_ ## _w, \ + } + + ENTRY(I8, Y8, R8, R8, UINT, R, R, R, R), + ENTRY(A1R5G5B5, A1R5G5B5, A1R5G5B5, A1B5G5R5, UNORM, B, G, R, A), + ENTRY(X1R5G5B5, X1R5G5B5, X1R5G5B5, A1B5G5R5, UNORM, B, G, R, ONE_FLOAT), + ENTRY(R5G6B5, R5G6B5, R5G6B5, B5G6R5, UNORM, B, G, R, ONE_FLOAT), + ENTRY(A8R8G8B8, A8R8G8B8, A8R8G8B8, A8B8G8R8, UNORM, B, G, R, A), + ENTRY(X8R8G8B8, X8R8G8B8, X8R8G8B8, A8B8G8R8, UNORM, B, G, R, ONE_FLOAT), + ENTRY(A2B10G10R10, A2B10G10R10, A2B10G10R10, A2B10G10R10, UNORM, R, G, B, A), + ENTRY(X2B10G10R10, A2B10G10R10, A2B10G10R10, A2B10G10R10, UNORM, R, G, B, ONE_FLOAT), + ENTRY(A8B8G8R8, A8B8G8R8, A8B8G8R8, A8B8G8R8, UNORM, R, G, B, A), + ENTRY(X8B8G8R8, X8B8G8R8, X8B8G8R8, A8B8G8R8, UNORM, R, G, B, ONE_FLOAT), + ENTRY(R16G16B16A16, R16_G16_B16_A16, R16_G16_B16_A16, R16G16B16A16, UNORM, R, G, B, A), + ENTRY(RF32GF32BF32AF32, RF32_GF32_BF32_AF32, RF32_GF32_BF32_AF32, R32G32B32A32, FLOAT, R, G, B, A), + +#undef ENTRY + +}; + +/*! + * Return the NV9097_SET_COLOR_TARGET_FORMAT that corresponds to the provided + * NvKmsSurfaceMemoryFormat. + */ +static NvU32 HsGetColorTargetFormat(enum NvKmsSurfaceMemoryFormat format) +{ + nvAssert(format < ARRAY_LEN(HsSurfaceFormatTable)); + + return HsSurfaceFormatTable[format].cl9097; +} + +/*! + * Given NvKmsSurfaceMemoryFormat, assign Nv3dRenderTexInfo fields: + * + * Nv3dRenderTexInfo::sizes + * Nv3dRenderTexInfo::dataType + * Nv3dRenderTexInfo::source + */ +static void AssignRenderTexInfoSizesDataTypeSource( + enum NvKmsSurfaceMemoryFormat format, + Nv3dRenderTexInfo *pTexInfo) +{ + nvAssert(format < ARRAY_LEN(HsSurfaceFormatTable)); + + pTexInfo->sizes = HsSurfaceFormatTable[format].sizes; + pTexInfo->dataType = HsSurfaceFormatTable[format].dataType; + pTexInfo->source.x = HsSurfaceFormatTable[format].source.x; + pTexInfo->source.y = HsSurfaceFormatTable[format].source.y; + pTexInfo->source.z = HsSurfaceFormatTable[format].source.z; + pTexInfo->source.w = HsSurfaceFormatTable[format].source.w; +} + +/*! + * Return the NV902D_SET_SRC_FORMAT that corresponds to the provided + * NvKmsSurfaceMemoryFormat. + */ +static NvU32 HsGet2dFormat(enum NvKmsSurfaceMemoryFormat format) +{ + nvAssert(format < ARRAY_LEN(HsSurfaceFormatTable)); + + return HsSurfaceFormatTable[format].cl902d; +} + +/*! + * Assign the Nv3dRenderTexInfo, given an NVSurfaceEvoRec. + */ +static void AssignRenderTexInfo( + const NVSurfaceEvoRec *pSurface, + const NvBool normalizedCoords, + const NvBool filtering, + Nv3dRenderTexInfo *pTexInfo) +{ + nvkms_memset(pTexInfo, 0, sizeof(*pTexInfo)); + + if (pSurface == NULL) { + return; + } + + AssignRenderTexInfoSizesDataTypeSource(pSurface->format, pTexInfo); + + if (pSurface->layout == NvKmsSurfaceMemoryLayoutBlockLinear) { + pTexInfo->texType = NV3D_TEX_TYPE_TWO_D_BLOCKLINEAR; + } else { + pTexInfo->texType = NV3D_TEX_TYPE_TWO_D_PITCH; + } + + pTexInfo->offset = pSurface->gpuAddress; + + pTexInfo->normalizedCoords = normalizedCoords; + pTexInfo->repeatType = NV3D_TEXHEAD_REPEAT_TYPE_NONE; + + pTexInfo->filtering = filtering; + pTexInfo->pitch = pSurface->planes[0].pitch; + pTexInfo->width = pSurface->widthInPixels; + pTexInfo->height = pSurface->heightInPixels; + + + /* + * When NVKMS clients register surfaces, they only specify log2GobsPerBlockY + * (not X or Z). This should be okay for now: + * + * X is never non-zero: on >= FERMI the only valid GOBS_PER_BLOCK_WIDTH is + * ONE_GOB: + * + * cl9097tex.h: + * #define NV9097_TEXHEAD2_GOBS_PER_BLOCK_WIDTH 21:19 + * #define NV9097_TEXHEAD2_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 + * + * clc097tex.h: + * #define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_WIDTH MW(98:96) + * #define NVC097_TEXHEAD_BL_GOBS_PER_BLOCK_WIDTH_ONE_GOB 0x00000000 + * + * Z would only be non-zero for a surface with three dimensions. + */ + + pTexInfo->log2GobsPerBlock.x = 0; + pTexInfo->log2GobsPerBlock.y = pSurface->log2GobsPerBlockY; + pTexInfo->log2GobsPerBlock.z = 0; +} + +static void HsGetYuv420Black( + const enum NvKmsSurfaceMemoryFormat format, + NvU32 color[4]) +{ + switch(format) { + case NvKmsSurfaceMemoryFormatI8: + nvAssert(!"headSurface cannot render to an I8 surface"); + break; + case NvKmsSurfaceMemoryFormatA1R5G5B5: + case NvKmsSurfaceMemoryFormatX1R5G5B5: + color[0] = 0x3d042108; /* 1/31 in 5bpc ==> 0.032258f */ + color[1] = 0x3d042108; /* 1/31 in 5bpc ==> 0.032258f */ + color[2] = 0x3ef7bdef; /* 15/31 in 5bpc ==> 0.483871f */ + break; + case NvKmsSurfaceMemoryFormatR5G6B5: + color[0] = 0x3d042108; /* 1/31 in 5bpc ==> 0.032258f */ + color[1] = 0x3d430c31; /* 3/63 in 6bpc ==> 0.047619f */ + color[2] = 0x3ef7bdef; /* 15/31 in 5bpc ==> 0.483871f */ + break; + case NvKmsSurfaceMemoryFormatA8R8G8B8: + case NvKmsSurfaceMemoryFormatX8R8G8B8: + case NvKmsSurfaceMemoryFormatA8B8G8R8: + case NvKmsSurfaceMemoryFormatX8B8G8R8: + color[0] = 0x3d70f0f1; /* 15/255 in 8bpc ==> 0.058824f */ + color[1] = 0x3d70f0f1; /* 15/255 in 8bpc ==> 0.058824f */ + color[2] = 0x3efefeff; /* 127/255 in 8bpc ==> 0.498039f */ + break; + case NvKmsSurfaceMemoryFormatA2B10G10R10: + case NvKmsSurfaceMemoryFormatX2B10G10R10: + color[0] = 0x3d7c3f10; /* 63/1023 in 10bpc ==> 0.061584f */ + color[1] = 0x3d7c3f10; /* 63/1023 in 10bpc ==> 0.061584f */ + color[2] = 0x3effbff0; /* 511/1023 in 10bpc ==> 0.499511f */ + break; + case NvKmsSurfaceMemoryFormatRF16GF16BF16AF16: + case NvKmsSurfaceMemoryFormatRF16GF16BF16XF16: + case NvKmsSurfaceMemoryFormatR16G16B16A16: + case NvKmsSurfaceMemoryFormatRF32GF32BF32AF32: + case NvKmsSurfaceMemoryFormatY8_U8__Y8_V8_N422: + case NvKmsSurfaceMemoryFormatU8_Y8__V8_Y8_N422: + case NvKmsSurfaceMemoryFormatY8___U8V8_N444: + case NvKmsSurfaceMemoryFormatY8___V8U8_N444: + case NvKmsSurfaceMemoryFormatY8___U8V8_N422: + case NvKmsSurfaceMemoryFormatY8___V8U8_N422: + case NvKmsSurfaceMemoryFormatY8___U8V8_N420: + case NvKmsSurfaceMemoryFormatY8___V8U8_N420: + case NvKmsSurfaceMemoryFormatY10___U10V10_N444: + case NvKmsSurfaceMemoryFormatY10___V10U10_N444: + case NvKmsSurfaceMemoryFormatY10___U10V10_N422: + case NvKmsSurfaceMemoryFormatY10___V10U10_N422: + case NvKmsSurfaceMemoryFormatY10___U10V10_N420: + case NvKmsSurfaceMemoryFormatY10___V10U10_N420: + case NvKmsSurfaceMemoryFormatY12___U12V12_N444: + case NvKmsSurfaceMemoryFormatY12___V12U12_N444: + case NvKmsSurfaceMemoryFormatY12___U12V12_N422: + case NvKmsSurfaceMemoryFormatY12___V12U12_N422: + case NvKmsSurfaceMemoryFormatY12___U12V12_N420: + case NvKmsSurfaceMemoryFormatY12___V12U12_N420: + case NvKmsSurfaceMemoryFormatY8___U8___V8_N444: + case NvKmsSurfaceMemoryFormatY8___U8___V8_N420: + nvAssert(!"HeadSurface doesn't render to these formats"); + break; + } + + color[3] = NV_FLOAT_ZERO; +} + +void nvHs3dClearSurface( + NVHsChannelEvoRec *pHsChannel, + const NVHsSurfaceRec *pHsSurface, + const struct NvKmsRect surfaceRect, + NvBool yuv420) +{ + NvPushChannelPtr p = &pHsChannel->nvPush.channel; + Nv3dChannelRec *p3d = &pHsChannel->nv3d.channel; + const NVSurfaceEvoRec *pSurfaceEvo = pHsSurface->pSurfaceEvo; + + const int ct = 0; + const NvBool blockLinear = TRUE; + const NvU32 surfaceFormat = HsGetColorTargetFormat(pSurfaceEvo->format); + const NvU16 x = surfaceRect.x; + const NvU16 y = surfaceRect.y; + const NvU16 w = surfaceRect.width; + const NvU16 h = surfaceRect.height; + + NvU32 clearColor[4] = { 0, 0, 0, 0 }; + + if (yuv420) { + HsGetYuv420Black(surfaceFormat, clearColor); + } + + nv3dSelectColorTarget(p3d, ct); + + nv3dSetColorTarget(p3d, + ct, + surfaceFormat, + pSurfaceEvo->gpuAddress, + blockLinear, + pHsSurface->gobsPerBlock, + pSurfaceEvo->widthInPixels, + pSurfaceEvo->heightInPixels); + + nv3dSetSurfaceClip(p3d, x, y, w, h); + nv3dSetBlendColorCoefficients(p3d, NV3D_BLEND_OP_SRC, FALSE, FALSE); + nv3dClearSurface(p3d, clearColor, x, y, w, h); + + nvPushKickoff(p); +} + +/*! + * The 3D engine can perform bilinear and nearest resampling as part of normal + * texture usage. But if a more complex resampling method is requested, then we + * will need to use an appropriate headSurface fragment program. + */ +static NvBool HsIsCustomSampling(enum NvKmsResamplingMethod resamplingMethod) +{ + return (resamplingMethod != NVKMS_RESAMPLING_METHOD_BILINEAR) && + (resamplingMethod != NVKMS_RESAMPLING_METHOD_NEAREST); +} + +/*! + * Return the headSurface fragment program that matches the configuration + * described by NVHsChannelConfig. + * + * \param[in] pChannelConfig The channel configuration. + */ +static ProgramName Hs3dGetFragmentProgram( + const NVHsChannelConfig *pChannelConfig, + const enum NvKmsPixelShiftMode pixelShift, + const NvBool overlay) +{ + const NvBool blend = pChannelConfig->pBlendTexSurface != NULL; + const NvBool offset = pChannelConfig->pOffsetTexSurface != NULL; + const NvBool blendAfterWarp = pChannelConfig->blendAfterWarp; + const NvBool yuv420 = pChannelConfig->yuv420; + const NvBool pixelShiftEnabled = pixelShift != NVKMS_PIXEL_SHIFT_NONE; + const NvBool customSampling = + HsIsCustomSampling(pChannelConfig->resamplingMethod); + const NvBool blendOffsetOrderMatters = (blend || offset); + + int i; + + for (i = 0; i < ARRAY_LEN(nvHeadSurfaceShaderInfo); i++) { + if ((nvHeadSurfaceShaderInfo[i].blend == blend) && + (nvHeadSurfaceShaderInfo[i].offset == offset) && + (nvHeadSurfaceShaderInfo[i].overlay == overlay) && + (nvHeadSurfaceShaderInfo[i].yuv420 == yuv420) && + (nvHeadSurfaceShaderInfo[i].pixelShift == pixelShiftEnabled) && + (nvHeadSurfaceShaderInfo[i].customSampling == customSampling) && + (!blendOffsetOrderMatters || + (nvHeadSurfaceShaderInfo[i].blendAfterWarp == blendAfterWarp))) { + + return PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT + i; + } + } + + nvAssert(!"Missing headSurface fragment program."); + + return PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT; +} + +/*! + * Given the rest of NVHsChannelConfig, return the srcFiltering configuration. + */ +static NvBool Hs3dGetSrcFiltering( + const NVHsChannelConfig *pChannelConfig, + const enum NvKmsPixelShiftMode pixelShift, + const NvBool overlay) +{ + if (overlay) { + return FALSE; + } + + if (pChannelConfig->yuv420) { + return FALSE; + } + + if (pixelShift != NVKMS_PIXEL_SHIFT_NONE) { + return FALSE; + } + + if (pChannelConfig->resamplingMethod == NVKMS_RESAMPLING_METHOD_NEAREST) { + return FALSE; + } + + return TRUE; +} + +/*! + * Load the warp mesh for this head. + */ +static void LoadStaticWarpMesh( + NVHsChannelEvoPtr pHsChannel) +{ + const NvHsStaticWarpMesh *swm = &pHsChannel->config.staticWarpMesh; + Nv3dChannelRec *p3d = &pHsChannel->nv3d.channel; + + /* We use a constant buffer slot to store the static warp mesh. */ + + ct_assert(sizeof(*swm) <= NV3D_CONSTANT_BUFFER_SIZE); + + nv3dSelectCb(p3d, NVKMS_HEADSURFACE_CONSTANT_BUFFER_STATIC_WARP_MESH); + + nv3dLoadConstants(p3d, 0, sizeof(*swm), swm); +} + +/*! + * Initialize the TWOD object in the channel. + */ +static void Hs3dSetup2d(NVHsChannelEvoPtr pHsChannel) +{ + NvPushChannelPtr p = &pHsChannel->nvPush.channel; + + nvAssert(!p->pDevice->clientSli || p->pDevice->numSubDevices == 1); + nvPushSetObject(p, NVA06F_SUBCHANNEL_2D, &pHsChannel->nv2d.handle); +} + +/*! + * Set up TWOD to read from the source surface. + */ +static void Hs3dSetup2dBlitSrc( + NVHsChannelEvoPtr pHsChannel, + const NVSurfaceEvoRec *pSrc) +{ + NvPushChannelPtr p = &pHsChannel->nvPush.channel; + const NvU32 colorFormat = HsGet2dFormat(pSrc->format); + + if (pSrc->layout == NvKmsSurfaceMemoryLayoutBlockLinear) { + nvPushMethod(p, NVA06F_SUBCHANNEL_2D, NV902D_SET_SRC_MEMORY_LAYOUT, 2); + nvPushSetMethodData(p, NV902D_SET_SRC_MEMORY_LAYOUT_V_BLOCKLINEAR); + /* NV902D_SET_SRC_BLOCK_SIZE */ + nvPushSetMethodData(p, + NV3D_V(902D, SET_SRC_BLOCK_SIZE, DEPTH, 0) | + NV3D_V(902D, SET_SRC_BLOCK_SIZE, HEIGHT, pSrc->log2GobsPerBlockY)); + } else { + nvPushImmed(p, NVA06F_SUBCHANNEL_2D, + NV902D_SET_SRC_MEMORY_LAYOUT, PITCH); + nvPushMethod(p, NVA06F_SUBCHANNEL_2D, NV902D_SET_SRC_PITCH, 1); + nvPushSetMethodData(p, pSrc->planes[0].pitch); + } + nvPushMethod(p, NVA06F_SUBCHANNEL_2D, NV902D_SET_SRC_WIDTH, 4); + nvPushSetMethodData(p, pSrc->widthInPixels); + /* NV902D_SET_SRC_HEIGHT */ + nvPushSetMethodData(p, pSrc->heightInPixels); + /* NV902D_SET_SRC_OFFSET */ + nvPushSetMethodDataU64(p, pSrc->gpuAddress); + + nvPushImmedVal(p, NVA06F_SUBCHANNEL_2D, NV902D_SET_SRC_FORMAT, colorFormat); +} + +/*! + * Set up TWOD to write to the destination surface. + */ +static void Hs3dSetup2dBlitDst( + NVHsChannelEvoPtr pHsChannel, + const NVHsSurfaceRec *pDst) +{ + NvPushChannelPtr p = &pHsChannel->nvPush.channel; + const NVSurfaceEvoRec *pSurfaceEvo = pDst->pSurfaceEvo; + const NvU32 colorFormat = HsGet2dFormat(pSurfaceEvo->format); + + /* NVHsSurfaceRec surfaces are always blockLinear. */ + nvAssert(pSurfaceEvo->layout == NvKmsSurfaceMemoryLayoutBlockLinear); + + nvPushMethod(p, NVA06F_SUBCHANNEL_2D, NV902D_SET_DST_MEMORY_LAYOUT, 2); + nvPushSetMethodData(p, NV902D_SET_DST_MEMORY_LAYOUT_V_BLOCKLINEAR); + + /* NV902D_SET_DST_BLOCK_SIZE */ + nvAssert(pDst->gobsPerBlock.x == 0); + nvPushSetMethodData(p, + NV3D_V(902D, SET_DST_BLOCK_SIZE, DEPTH, pDst->gobsPerBlock.z) | + NV3D_V(902D, SET_DST_BLOCK_SIZE, HEIGHT, pDst->gobsPerBlock.y)); + + nvPushMethod(p, NVA06F_SUBCHANNEL_2D, NV902D_SET_DST_WIDTH, 4); + nvPushSetMethodData(p, pSurfaceEvo->widthInPixels); + /* NV902D_SET_DST_HEIGHT */ + nvPushSetMethodData(p, pSurfaceEvo->heightInPixels); + /* NV902D_SET_DST_OFFSET */ + nvPushSetMethodDataU64(p, pSurfaceEvo->gpuAddress); + + nvPushImmedVal(p, NVA06F_SUBCHANNEL_2D, NV902D_SET_DST_FORMAT, colorFormat); +} + +/*! + * Prepare TWOD to perform blits between surfaces. + */ +static void Hs3dSetup2dBlit( + NVHsChannelEvoPtr pHsChannel, + const NVSurfaceEvoRec *pSrc, + const NVHsSurfaceRec *pDst) +{ + NvPushChannelPtr p = &pHsChannel->nvPush.channel; + + nvPushImmed(p, NVA06F_SUBCHANNEL_2D, NV902D_SET_OPERATION, SRCCOPY); + + Hs3dSetup2dBlitSrc(pHsChannel, pSrc); + Hs3dSetup2dBlitDst(pHsChannel, pDst); +} + +/*! + * Perform a blit, using TWOD, between the surfaces defined in the previous call + * to Hs3dSetup2dBlit(). This can be called multiple times per + * Hs3dSetup2dBlit(). + */ +static void Hs3d2dBlit( + NVHsChannelEvoPtr pHsChannel, + struct NvKmsPoint srcPoint, + struct NvKmsPoint dstPoint, + struct NvKmsSize size) +{ + NvPushChannelPtr p = &pHsChannel->nvPush.channel; + + nvPushMethod(p, NVA06F_SUBCHANNEL_2D, + NV902D_SET_PIXELS_FROM_MEMORY_DST_X0, 12); + nvPushSetMethodData(p, dstPoint.x); /* Destination X */ + /* NV902D_SET_PIXELS_FROM_MEMORY_DST_Y0 */ + nvPushSetMethodData(p, dstPoint.y); /* Destination Y */ + /* NV902D_SET_PIXELS_FROM_MEMORY_DST_WIDTH */ + nvPushSetMethodData(p, size.width); /* Blit Width */ + /* NV902D_SET_PIXELS_FROM_MEMORY_DST_HEIGHT */ + nvPushSetMethodData(p, size.height); /* Blit Height */ + /* NV902D_SET_PIXELS_FROM_MEMORY_DU_DX_FRAC */ + nvPushSetMethodData(p, 0x0); /* du/dx fraction */ + /* NV902D_SET_PIXELS_FROM_MEMORY_DU_DX_INT */ + nvPushSetMethodData(p, 0x1); /* du/dx int */ + /* NV902D_SET_PIXELS_FROM_MEMORY_DV_DY_FRAC */ + nvPushSetMethodData(p, 0x0); /* dv/dy fraction */ + /* NV902D_SET_PIXELS_FROM_MEMORY_DV_DY_INT */ + nvPushSetMethodData(p, 0x1); /* dv/dy int */ + /* NV902D_SET_PIXELS_FROM_MEMORY_SRC_X0_FRAC */ + nvPushSetMethodData(p, 0x0); /* Source X fraction */ + /* NV902D_SET_PIXELS_FROM_MEMORY_SRC_X0_INT */ + nvPushSetMethodData(p, srcPoint.x); /* Source X int */ + /* NV902D_SET_PIXELS_FROM_MEMORY_SRC_Y0_FRAC */ + nvPushSetMethodData(p, 0x0); /* Source Y fraction */ + /* NV902D_PIXELS_FROM_MEMORY_SRC_Y0_INT */ + nvPushSetMethodData(p, srcPoint.y); /* Source Y int */ +} + +/*! + * Initialize the pHsChannel for rendering. + * + * This should be called once, when the headSurface configuration is applied to + * the device. Here we do any work that is static for the given headSurface + * configuration. + * + * This function cannot fail. + * + * \param[in,out] pHsChannel The channel to update. + */ +void nvHs3dSetConfig(NVHsChannelEvoPtr pHsChannel) +{ + LoadStaticWarpMesh(pHsChannel); + + nvkms_memset(pHsChannel->nv3d.texInfo, 0, + sizeof(pHsChannel->nv3d.texInfo)); + + /* Set up sampler from blend surface. */ + + AssignRenderTexInfo( + pHsChannel->config.pBlendTexSurface, + TRUE /* normalizedCoords */, + TRUE /* filtering */, + &pHsChannel->nv3d.texInfo[NVKMS_HEADSURFACE_TEXINFO_BLEND]); + + /* Set up sampler from offset surface. */ + + AssignRenderTexInfo( + pHsChannel->config.pOffsetTexSurface, + TRUE /* normalizedCoords */, + TRUE /* filtering */, + &pHsChannel->nv3d.texInfo[NVKMS_HEADSURFACE_TEXINFO_OFFSET]); + + Hs3dSetup2d(pHsChannel); +} + +static NvU32 HsGetSatCos(NvS32 dvc) +{ + // Digital vibrance is between -1024 (NV_EVO_DVC_MIN) and 1023 + // (NV_EVO_DVC_MAX), normalized to 0.0f-2.0f for this shader, + // defaulting to 1.0f. This mimics nvSetDVCEvo(). + // (dvc + 1024) / 1024.0f + const NvU32 a = NV_MAX(dvc + 1024, 0); + const float32_t b = ui32_to_f32(a); + const float32_t c = ui32_to_f32(1024); + const float32_t d = f32_div(b, c); + + return F32viewAsNvU32(d); +} + +/*! + * Load the fragment program uniforms needed for the headSurface configuration. + */ +static void LoadFragmentProgramUniforms( + NVHsChannelEvoPtr pHsChannel, + const enum NvKmsPixelShiftMode pixelShift, + const NvBool overlay, + const struct NvKmsPoint viewPortPointIn) +{ + const NVHsChannelConfig *pChannelConfig = &pHsChannel->config; + const NvBool pixelShiftEnabled = pixelShift != NVKMS_PIXEL_SHIFT_NONE; + const NvBool customSampling = + HsIsCustomSampling(pChannelConfig->resamplingMethod); + + NvHsFragmentUniforms fragmentUniforms = { }; + + /* XXX NVKMS HEADSURFACE TODO: plumb colorRange */ + const enum NvKmsDpyAttributeColorRangeValue colorRange = + NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_FULL; + + const NvBool needsFragmentUniforms = + pChannelConfig->blendAfterWarp || + pChannelConfig->yuv420 || + overlay || + pixelShiftEnabled || + customSampling; + + if (!needsFragmentUniforms) { + return; + } + + if (customSampling) { + +#if defined(DEBUG) + /* + * The customSampling calculation above should ensure that + * pChannelConfig->resamplingMethod is one of the following values. And + * the enums and constants should be defined such that they have the + * same values. + */ + NvBool found = FALSE; + +#define CHECK(_x) \ + do { \ + ct_assert(NVKMS_RESAMPLING_METHOD_ ## _x == \ + NVIDIA_HEADSURFACE_RESAMPLING_METHOD_ ## _x); \ + if (pChannelConfig->resamplingMethod == \ + NVKMS_RESAMPLING_METHOD_ ## _x) { \ + found = TRUE; \ + } \ + } while (0) + + CHECK(BICUBIC_TRIANGULAR); + CHECK(BICUBIC_BELL_SHAPED); + CHECK(BICUBIC_BSPLINE); + CHECK(BICUBIC_ADAPTIVE_TRIANGULAR); + CHECK(BICUBIC_ADAPTIVE_BELL_SHAPED); + CHECK(BICUBIC_ADAPTIVE_BSPLINE); + +#undef CHECK + + nvAssert(found); +#endif /* DEBUG */ + + fragmentUniforms.resamplingMethod = pChannelConfig->resamplingMethod; + } + + if (pChannelConfig->blendAfterWarp) { + fragmentUniforms.vertexScale.x = pChannelConfig->viewPortOut.width; + fragmentUniforms.vertexScale.y = pChannelConfig->viewPortOut.height; + } + + // The following uniforms are all necessary for the LUT and colorRange + // to be applied in the headSurface shader for the overlay, YUV420, or + // pixelshift mode. + if (pChannelConfig->yuv420 || overlay || pixelShiftEnabled) { + + const int nPaletteEntries = 0; /* XXX NVKMS HEADSURFACE TODO */ + const int depth = 24; /* XXX NVKMS HEADSURFACE TODO */ + + fragmentUniforms.numLutEntries.x = nPaletteEntries; + fragmentUniforms.numLutEntries.y = nPaletteEntries; + fragmentUniforms.numLutEntries.z = nPaletteEntries; + + // In depth 16 (R5G6B5) the LUT has half as many entries for red + // and blue as it does for green. + if (depth == 16) { + nvAssert(fragmentUniforms.numLutEntries.x % 2 == 0); + fragmentUniforms.numLutEntries.x /= 2; + nvAssert(fragmentUniforms.numLutEntries.z % 2 == 0); + fragmentUniforms.numLutEntries.z /= 2; + } + } + + if (pChannelConfig->yuv420 || pixelShiftEnabled) { + int i, j; + + // primaryTextureBias is used in the fragment shader as well in + // YUV420/pixelshift modes in order to map YUV420/pixelshift + // transformed fragment coordinates to the viewport, since the + // vertex shader's transformation is skipped in YUV420/pixelshift + // modes. + + fragmentUniforms.primaryTextureBias.x = viewPortPointIn.x; + fragmentUniforms.primaryTextureBias.y = viewPortPointIn.y; + + fragmentUniforms.cursorPosition.x = pChannelConfig->cursor.x + + fragmentUniforms.primaryTextureBias.x; + fragmentUniforms.cursorPosition.y = pChannelConfig->cursor.y + + fragmentUniforms.primaryTextureBias.y; + + for (i = 0; i < 3; i++) { + for (j = 0; j < 3; j++) { + fragmentUniforms.transform[i][j] = + F32viewAsNvU32(pChannelConfig->transform.m[i][j]); + } + } + } + + // In pixelshift mode, a 2x width/height source surface is + // downsampled to the destination surface. This tells the shader + // whether to copy the upper left or bottom right pixels of each + // pixel quad for the destination surface. + if (pixelShift == NVKMS_PIXEL_SHIFT_4K_TOP_LEFT) { + fragmentUniforms.pixelShiftOffset.x = NV_FLOAT_NEG_QUARTER; + fragmentUniforms.pixelShiftOffset.y = NV_FLOAT_NEG_QUARTER; + } else if (pixelShift == NVKMS_PIXEL_SHIFT_4K_BOTTOM_RIGHT) { + fragmentUniforms.pixelShiftOffset.x = NV_FLOAT_QUARTER; + fragmentUniforms.pixelShiftOffset.y = NV_FLOAT_QUARTER; + } else { + // When we get here, we should only see pixelShift of 4k or none (not + // 8k): 8k should be translated into different 4k configs for each eye, + // higher in the call chain. + nvAssert(pixelShift == NVKMS_PIXEL_SHIFT_NONE); + } + + if (pChannelConfig->yuv420) { + // Since YUV 4:2:0 is only currently supported on 4K modes, hardcode + // the ITU-R BT.709 colorspace conversion matrix. + // The following 5 coefficients are copied from items 4.2 and 4.3 of + // Rec. ITU-R BT.709-5. + fragmentUniforms.luminanceCoefficient.x = 0x3e59b3d0; /* R : 0.2126f */ + fragmentUniforms.luminanceCoefficient.y = 0x3f371759; /* G : 0.7152f */ + fragmentUniforms.luminanceCoefficient.z = 0x3d93dd98; /* B : 0.0722f */ + fragmentUniforms.chromaCoefficient.x = 0x3f228f5c; /* Cr: 0.6350f */ + fragmentUniforms.chromaCoefficient.y = 0x3f09f55a; /* Cb: 0.5389f */ + + // Range compression is disabled in HW and applied manually in the + // shader for YUV420 mode. + if (colorRange == NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_FULL) { + fragmentUniforms.luminanceScale = NV_FLOAT_ONE; + fragmentUniforms.luminanceBlackLevel = NV_FLOAT_ZERO; + fragmentUniforms.chrominanceScale = NV_FLOAT_ONE; + } else if (colorRange == NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_LIMITED) { + // ITU-R BT.709 mandates a limited color range with the + // following 8bpc quantization values (section 6.10): + // + // Luminance black level 16 + // Luminance nominal range 16-235 (i.e., range of 219) + // Chrominance nominal range 16-240 (i.e., range of 224) + // + // Divide these values by 255.0f to normalize to the range 0.0f-1.0f + // for the yuv420 shader's color range quantization. + + // 219.0f / 255.0f == 0.858824f ==> 0x3f5bdbdc + fragmentUniforms.luminanceScale = 0x3f5bdbdc; + + // 16.0f / 255.0f == 0.062745f ==> 0x3d808081 + fragmentUniforms.luminanceBlackLevel = 0x3d808081; + + // 224.0f / 255.0f == 0.878431f ==> 0x3f60e0e1 + fragmentUniforms.chrominanceScale = 0x3f60e0e1; + } else { + nvAssert(!"Invalid color range"); + } + // Chrominance black level is 128 for both full and limited range. + // Divide by 255.0f to normalize to the range 0.0f-1.0f. + // 128.0f / 255.0f == 0.501961 ==> 0x3f008081 + fragmentUniforms.chrominanceBlackLevel = 0x3f008081; + + fragmentUniforms.satCos = HsGetSatCos(pChannelConfig->dvc); + + // Default digital vibrance is 1024, from an input dvc of 0. If + // dvc is not default, useSatHue tells the shader to use the + // modified satCos. + if (pChannelConfig->dvc != 0) { + fragmentUniforms.useSatHue = 1; + } + } + + nv3dSelectCb(&pHsChannel->nv3d.channel, + NVKMS_HEADSURFACE_CONSTANT_BUFFER_FRAGMENT_PROGRAM); + nv3dBindCb(&pHsChannel->nv3d.channel, NV3D_HW_BIND_GROUP_FRAGMENT, + NV3D_CB_SLOT_MISC1, TRUE); + nv3dLoadConstants(&pHsChannel->nv3d.channel, 0, + sizeof(fragmentUniforms), &fragmentUniforms); +} + +/*! + * Load the vertex program uniforms needed for the headSurface configuration. + */ +static void LoadVertexProgramUniforms( + NVHsChannelEvoPtr pHsChannel, + const struct NvKmsPoint viewPortPointIn) +{ + const NVHsChannelConfig *pChannelConfig = &pHsChannel->config; + Nv3dChannelRec *p3d = &pHsChannel->nv3d.channel; + NvHsVertexUniforms uniforms = { }; + + /* Scale incoming vertices by the output resolution. */ + uniforms.vertexScale.x = pChannelConfig->viewPortOut.width; + uniforms.vertexScale.y = pChannelConfig->viewPortOut.height; + + /* Map primary texture coordinates to the display viewport. */ + + uniforms.primaryTextureScale.x = pChannelConfig->viewPortIn.width; + uniforms.primaryTextureScale.y = pChannelConfig->viewPortIn.height; + + uniforms.primaryTextureBias.x = viewPortPointIn.x; + uniforms.primaryTextureBias.y = viewPortPointIn.y; + + uniforms.cursorPosition.x = pChannelConfig->cursor.x + + uniforms.primaryTextureBias.x; + uniforms.cursorPosition.y = pChannelConfig->cursor.y + + uniforms.primaryTextureBias.y; + + /* Bind the constant buffer. */ + nv3dSelectCb(p3d, NVKMS_HEADSURFACE_CONSTANT_BUFFER_VERTEX_PROGRAM); + nv3dBindCb(p3d, NV3D_HW_BIND_GROUP_VERTEX, NV3D_CB_SLOT_MISC1, TRUE); + + /* Upload the uniforms in it. */ + nv3dLoadConstants(p3d, 0, sizeof(uniforms), &uniforms); +} + +/*! + * Assign the 'textures' texture binding indices array. + * + * The array should have NVIDIA_HEADSURFACE_UNIFORM_SAMPLER_BINDING_NUM + * elements. + */ +static void AssignTextureBindingIndices( + const NVHsChannelEvoRec *pHsChannel, + const NVSurfaceEvoRec *pSurfaceEvo[NVKMS_MAX_LAYERS_PER_HEAD], + int *textures) +{ + const struct { + enum NVHsChannelTexInfoEnum texture; + const NVSurfaceEvoRec *pSurface; + } textureTable[NVIDIA_HEADSURFACE_UNIFORM_SAMPLER_BINDING_NUM] = { + +#define ENTRY(_binding, _texinfo, _surface) \ + [NVIDIA_HEADSURFACE_UNIFORM_SAMPLER_BINDING_ ## _binding ## _TEX] = { \ + .texture = NVKMS_HEADSURFACE_TEXINFO_ ## _texinfo, \ + .pSurface = _surface, \ + } + + ENTRY(PRIMARY, SRC, pSurfaceEvo[NVKMS_MAIN_LAYER]), + ENTRY(CURSOR, CURSOR, pHsChannel->config.cursor.pSurfaceEvo), + ENTRY(BLEND, BLEND, pHsChannel->config.pBlendTexSurface), + ENTRY(OFFSET, OFFSET, pHsChannel->config.pOffsetTexSurface), + ENTRY(OVERLAY, OVERLAY, pSurfaceEvo[NVKMS_OVERLAY_LAYER]), + +#undef ENTRY + }; + + NvU32 i; + + for (i = 0; i < ARRAY_LEN(textureTable); i++) { + if (textureTable[i].pSurface != NULL) { + textures[i] = textureTable[i].texture; + } else { + textures[i] = NV3D_TEXTURE_INDEX_INVALID; + } + } +} + +/*! + * Get the warp mesh data to use to draw headSurface. + * + * If the client specified a warpMesh surface, we use that. Otherwise, use the + * static warp mesh computed earlier. + */ +static void GetWarpMeshData( + const NVHsChannelEvoPtr pHsChannel, + Nv3dStreamSurfaceRec *pStreamSurf, + NvU32 *pOp, + NvU32 *pVertexCount) +{ + const NvU32 opTable[] = { + [NVKMS_WARP_MESH_DATA_TYPE_TRIANGLES_XYUVRQ] = + NV3D_C(9097, BEGIN, OP, TRIANGLES), + [NVKMS_WARP_MESH_DATA_TYPE_TRIANGLE_STRIP_XYUVRQ] = + NV3D_C(9097, BEGIN, OP, TRIANGLE_STRIP), + }; + + const NVSurfaceEvoRec *pSurface = pHsChannel->config.warpMesh.pSurface; + Nv3dChannelRec *p3d = &pHsChannel->nv3d.channel; + + enum NvKmsWarpMeshDataType dataType; + + nvkms_memset(pStreamSurf, 0, sizeof(*pStreamSurf)); + + if (pSurface != NULL) { + + pStreamSurf->gpuAddress = pSurface->gpuAddress; + pStreamSurf->size = pSurface->planes[0].rmObjectSizeInBytes; + dataType = pHsChannel->config.warpMesh.dataType; + *pVertexCount = pHsChannel->config.warpMesh.vertexCount; + + } else { + + pStreamSurf->gpuAddress = + nv3dGetConstantBufferGpuAddress(p3d, + NVKMS_HEADSURFACE_CONSTANT_BUFFER_STATIC_WARP_MESH); + pStreamSurf->size = NV3D_CONSTANT_BUFFER_SIZE; + dataType = NVKMS_WARP_MESH_DATA_TYPE_TRIANGLE_STRIP_XYUVRQ; + *pVertexCount = 4; + } + + nvAssert((dataType == NVKMS_WARP_MESH_DATA_TYPE_TRIANGLES_XYUVRQ) || + (dataType == NVKMS_WARP_MESH_DATA_TYPE_TRIANGLE_STRIP_XYUVRQ)); + + *pOp = opTable[dataType]; +} + +/*! + * Program the WindowOffset method. + */ +static void HsSetWindowOffset( + NVHsChannelEvoRec *pHsChannel, + NvS16 x, NvS16 y) +{ + NvPushChannelPtr p = &pHsChannel->nvPush.channel; + + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, NV9097_SET_WINDOW_OFFSET_X, 2); + nvPushSetMethodData(p, x); + nvPushSetMethodData(p, y); +} + +/*! + * Return a pointer to the semaphore structure for this headSurface channel and + * semaphore index. + * + * Note we abuse the nvidia-push library's notifier infrastructure as a + * convenient mechanism to allocate and map memory for us. NvNotification and + * NvGpuSemaphore structures are the same size, so this works out. + */ +static inline NvGpuSemaphore *Hs3dGetSemaphore( + const NVHsChannelEvoRec *pHsChannel, + NvU8 index) +{ + const NvPushChannelRec *pChannel = &pHsChannel->nvPush.channel; + const NvU32 sd = pHsChannel->pDispEvo->displayOwner; + + NvNotification *pNotifier = + nvPushGetNotifierCpuAddress(pChannel, index, sd); + + ct_assert(sizeof(NvNotification) == sizeof(NvGpuSemaphore)); + + return (NvGpuSemaphore *) pNotifier; +} + +#if NVKMS_PROCFS_ENABLE +/*! + * Get the semaphore index (e.g., to be passed into + * nvPushGetNotifierGpuAddress()) for an (eye, slot) pair. + */ +static inline NvU8 Hs3dGetStatisticsSemaphoreIndex(const NvU8 eye, + const NvU8 slot) +{ + nvAssert((eye == NVKMS_LEFT) || (eye == NVKMS_RIGHT)); + nvAssert(slot < NVKMS_HEADSURFACE_STATS_MAX_SLOTS); + + const NvU8 maxSemsPerEye = NVKMS_HEAD_SURFACE_STATS_SEMAPHORE_STAGE_COUNT; + const NvU8 maxSemsPerSlot = maxSemsPerEye * NVKMS_MAX_EYES; + + const NvU8 index = (eye * maxSemsPerEye) + (slot * maxSemsPerSlot); + + nvAssert(index < NVKMS_HEADSURFACE_STATS_MAX_SEMAPHORES); + + return index; +} + +/*! + * Return the 64-bit nanosecond timeStamp from the given NvGpuSemaphore. + */ +static inline NvU64 Hs3dGetSemaphoreTime(const NvGpuSemaphore *pSemaphore) +{ + const NvU64 low = pSemaphore->timeStamp.nanoseconds[0]; + const NvU64 high = pSemaphore->timeStamp.nanoseconds[1]; + + return (high << 32) | low; +} + +static void Hs3dStatisticsReleaseSemaphore( + NVHsChannelEvoPtr pHsChannel, + const NvU8 semIndex, + const NvU64 nFrames) +{ + NvPushChannelPtr p = &pHsChannel->nvPush.channel; + const NvU32 sd = pHsChannel->pDispEvo->displayOwner; + + const NvU64 gpuAddress = nvPushGetNotifierGpuAddress(p, semIndex, sd); + + /* + * Use the current frame number as the payload, so we can assert that we're + * inspecting the right, and correctly released, semaphores when computing + * deltaTime below. + */ + const NvU32 payload = NvU64_LO32(nFrames); + + const NvU32 operation = + NV3D_C(9097, SET_REPORT_SEMAPHORE_D, OPERATION, RELEASE) | + NV3D_C(9097, SET_REPORT_SEMAPHORE_D, RELEASE, + AFTER_ALL_PRECEEDING_WRITES_COMPLETE) | + NV3D_C(9097, SET_REPORT_SEMAPHORE_D, STRUCTURE_SIZE, FOUR_WORDS)| + NV3D_C(9097, SET_REPORT_SEMAPHORE_D, FLUSH_DISABLE, TRUE) | + NV3D_C(9097, SET_REPORT_SEMAPHORE_D, PIPELINE_LOCATION, ALL); + + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, NV9097_SET_REPORT_SEMAPHORE_A, 4); + nvPushSetMethodDataU64(p, gpuAddress); + nvPushSetMethodData(p, payload); + nvPushSetMethodData(p, operation); +} + +static void Hs3dStatisticsComputeFps( + NVHsChannelEvoPtr pHsChannel, + const NvU8 eye, + const NvU8 slot, + const NvU64 currentTime) +{ + NVHsChannelStatisticsOneEyeRec *pPerEye = + &pHsChannel->statistics.perEye[eye][slot]; + + NvU64 elapsedTime; + NvU32 elapsedTimeMs; + + if (pPerEye->fps.startTime == 0) { + pPerEye->fps.startTime = currentTime; + } + + pPerEye->fps.nFrames++; + + elapsedTime = currentTime - pPerEye->fps.startTime; + + /* + * To maintain precision without floating point math, convert + * the time from nanoseconds to milliseconds (divide by 1000000) + * and multiply nFrames by 1000000. This yields frames per + * milliseconds. + */ + elapsedTimeMs = (elapsedTime + 500000) / 1000000; + + if (elapsedTimeMs > 5000) { /* 5 seconds */ + + pPerEye->fps.framesPerMs = + (pPerEye->fps.nFrames * 1000000) / elapsedTimeMs; + + pPerEye->fps.nFrames = 0; + pPerEye->fps.startTime = currentTime; + } +} + +#endif /* NVKMS_PROCFS_ENABLE */ + +/*! + * Collect statistics on headSurface rendering. + * + * Hs3dStatisticsBefore() should be called before pushing the frame's rendering + * methods, and Hs3dStatisticsAfter() should be called after pushing the frame's + * rendering methods. Both times, we push methods to do a 3D engine semaphore + * release. + * + * Also, in the "Before" case, we look at the semaphores that were released + * during the previous frame (we assume that, by the time we are here for Frame + * N, the rendering and semaphore releases completed for Frame N-1), and compute + * the time between Frame N-1's "before" and "after" semaphore releases. + */ + + +static void Hs3dStatisticsBefore( + NVHsChannelEvoPtr pHsChannel, + const NvU8 eye, + const NvU8 slot) +{ +#if NVKMS_PROCFS_ENABLE + NVHsChannelStatisticsOneEyeRec *pPerEye = + &pHsChannel->statistics.perEye[eye][slot]; + + const NvU8 semIndex = Hs3dGetStatisticsSemaphoreIndex(eye, slot); + + if (pPerEye->nFrames == 0) { + goto done; + } + + /* Compute the statistics for the previous frame. */ + + const NvU32 prevPayload = NvU64_LO32(pPerEye->nFrames - 1); + + const NvU8 beforeIndex = + semIndex + NVKMS_HEADSURFACE_STATS_SEMAPHORE_BEFORE; + const NvU8 afterIndex = + semIndex + NVKMS_HEADSURFACE_STATS_SEMAPHORE_AFTER; + + NvGpuSemaphore *pBefore = Hs3dGetSemaphore(pHsChannel, beforeIndex); + NvGpuSemaphore *pAfter = Hs3dGetSemaphore(pHsChannel, afterIndex); + + const NvU64 beforeTime = Hs3dGetSemaphoreTime(pBefore); + const NvU64 afterTime = Hs3dGetSemaphoreTime(pAfter); + const NvU64 deltaTime = afterTime - beforeTime; + + /* + * The payload for the before and after semaphores should be the + * previous frame number unless (a) we're looking at the wrong + * semaphores or (b) the semaphores weren't released yet. + */ + nvAssert(pBefore->data[0] == prevPayload); + nvAssert(pAfter->data[0] == prevPayload); + (void)prevPayload; + + if (afterTime < beforeTime) { + nvEvoLogDispDebug(pHsChannel->pDispEvo, EVO_LOG_ERROR, + "Hs3dStatisticsBefore(): " + "afterTime (%" NvU64_fmtu " nsec) < " + "beforeTime (%" NvU64_fmtu " nsec)", + afterTime, beforeTime); + } + + pPerEye->gpuTimeSpent += deltaTime; + + /* + * Compute the frames per second of headSurface for this eye + slot, so that + * we can take advantage of the nanosecond time extracted above from the + * released semaphores. + */ + Hs3dStatisticsComputeFps(pHsChannel, eye, slot, beforeTime); + +done: + Hs3dStatisticsReleaseSemaphore( + pHsChannel, + semIndex + NVKMS_HEADSURFACE_STATS_SEMAPHORE_BEFORE, + pPerEye->nFrames); + +#endif /* NVKMS_PROCFS_ENABLE */ +} + +static void Hs3dStatisticsAfter( + NVHsChannelEvoPtr pHsChannel, + const NvU8 eye, + const NvU8 slot) +{ +#if NVKMS_PROCFS_ENABLE + NVHsChannelStatisticsOneEyeRec *pPerEye = + &pHsChannel->statistics.perEye[eye][slot]; + const NvU8 semIndex = Hs3dGetStatisticsSemaphoreIndex(eye, slot); + + Hs3dStatisticsReleaseSemaphore( + pHsChannel, + semIndex + NVKMS_HEADSURFACE_STATS_SEMAPHORE_AFTER, + pPerEye->nFrames); + + pPerEye->nFrames++; + +#endif /* NVKMS_PROCFS_ENABLE */ +} + +/*! + * Return the semaphore value showing the viewport offset for the most recently + * completed frame of non-swapgroup headsurface rendering. + */ +NvU32 nvHs3dLastRenderedOffset(NVHsChannelEvoPtr pHsChannel) +{ + const NvU8 semIndex = NVKMS_HEADSURFACE_VIEWPORT_OFFSET_SEMAPHORE_INDEX; + const NvGpuSemaphore *sema = Hs3dGetSemaphore(pHsChannel, semIndex); + + return sema->data[0]; +} + +/*! + * Push a semaphore write of the viewport offset used for the previous frame + * of non-swapgroup headsurface rendering to + * NVKMS_HEADSURFACE_VIEWPORT_OFFSET_SEMAPHORE_INDEX followed by a + * non-stall interrupt. + */ +void nvHs3dPushPendingViewportFlip(NVHsChannelEvoPtr pHsChannel) +{ + NvPushChannelPtr p = &pHsChannel->nvPush.channel; + const NvU32 sd = pHsChannel->pDispEvo->displayOwner; + const NvU8 semIndex = NVKMS_HEADSURFACE_VIEWPORT_OFFSET_SEMAPHORE_INDEX; + + const NvU64 gpuAddress = nvPushGetNotifierGpuAddress(p, semIndex, sd); + const NvU32 payload = pHsChannel->nextOffset; + const NvU32 semaphoreOperation = + DRF_DEF(A06F, _SEMAPHORED, _OPERATION, _RELEASE) | + DRF_DEF(A06F, _SEMAPHORED, _RELEASE_WFI, _DIS) | + DRF_DEF(A06F, _SEMAPHORED, _RELEASE_SIZE, _4BYTE); + + nvAssert(!pHsChannel->viewportFlipPending); + + pHsChannel->viewportFlipPending = TRUE; + + nvPushMethod(p, 0, NVA06F_SEMAPHOREA, 4); + nvPushSetMethodDataU64(p, gpuAddress); + nvPushSetMethodData(p, payload); + nvPushSetMethodData(p, semaphoreOperation); + + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, NVA06F_NON_STALL_INTERRUPT, 1); + nvPushSetMethodData(p, 0); + nvPushKickoff(p); + +} + +struct NvHs3dRenderFrameWorkArea { + + struct { + NvBool enabled; + NvBool honorSwapGroupClipList; + + struct { + const NVSurfaceEvoRec *pSurfaceEvo[NVKMS_MAX_LAYERS_PER_HEAD]; + } src; + + struct { + const NVHsSurfaceRec *pHsSurface; + } dst; + + } staging; + + struct { + + struct { + const NVSurfaceEvoRec *pSurfaceEvo[NVKMS_MAX_LAYERS_PER_HEAD]; + struct NvKmsPoint viewPortPointIn; + } src; + + struct { + const NVHsSurfaceRec *pHsSurface; + } dst; + + } threeD; +}; + +/*! + * Assign the NvHs3dRenderFrameWorkArea structure. + * + * Whether SwapGroup is enabled impacts the nvHs3dRenderFrame() pipeline. + */ +static NvBool Hs3dAssignRenderFrameWorkArea( + const NVHsChannelEvoRec *pHsChannel, + const NvBool honorSwapGroupClipList, + const NvU8 dstEye, + const NvU8 dstBufferIndex, + const NVSurfaceEvoRec *pSurfaceEvo[NVKMS_MAX_LAYERS_PER_HEAD], + struct NvHs3dRenderFrameWorkArea *pWorkArea) +{ + const NVDevEvoRec *pDevEvo = pHsChannel->pDispEvo->pDevEvo; + const NVHsStateOneHeadAllDisps *pHsOneHeadAllDisps = + &pDevEvo->apiHeadSurfaceAllDisps[pHsChannel->apiHead]; + + const NVHsSurfaceRec *pSurface; + const struct NvKmsPoint origin = { .x = 0, .y = 0}; + + NvU8 layer; + + nvkms_memset(pWorkArea, 0, sizeof(*pWorkArea)); + + nvAssert(dstEye < ARRAY_LEN(pHsOneHeadAllDisps->surfaces)); + nvAssert(dstBufferIndex < ARRAY_LEN(pHsOneHeadAllDisps->surfaces[dstEye])); + + pSurface = pHsOneHeadAllDisps->surfaces[dstEye][dstBufferIndex].pSurface; + + if (pSurface == NULL) { + return FALSE; + } + + /* Assign the src and dst of the operations needed by headSurface. */ + + /* + * We only need the staging buffer if there are both swapgroup and + * non-swapgroup content on the screen which we can see from the + * cliplist. + * + * NOTE: We probably should assert here that viewPortIn minus swapgroup + * clip list equals viewPortIn. The client already does the same, + * communicates that to NVKMS and that is cached in the + * swapGroupIsFullscreen flag. + */ + + const NVSwapGroupRec *pSwapGroup = + pHsChannel->pDispEvo->pSwapGroup[pHsChannel->apiHead]; + + if (pHsChannel->config.neededForSwapGroup && + pSwapGroup && + !pSwapGroup->swapGroupIsFullscreen) { + + const NVHsSurfaceRec *pStagingSurface = + pHsOneHeadAllDisps->surfaces[dstEye][dstBufferIndex].pStagingSurface; + nvAssert(pStagingSurface != NULL); + + /* + * The 'staging' operation uses the client-provided surfaces as src, and + * uses the staging surface as dst. + */ + + pWorkArea->staging.enabled = TRUE; + pWorkArea->staging.honorSwapGroupClipList = honorSwapGroupClipList; + + ct_assert(ARRAY_LEN(pWorkArea->staging.src.pSurfaceEvo) == + NVKMS_MAX_LAYERS_PER_HEAD); + + for (layer = 0; layer < NVKMS_MAX_LAYERS_PER_HEAD; layer++) { + pWorkArea->staging.src.pSurfaceEvo[layer] = pSurfaceEvo[layer]; + } + pWorkArea->staging.dst.pHsSurface = pStagingSurface; + + /* + * The 'threeD' operation uses the staging surface as src, and the + * headSurface surface as dst. + */ + + pWorkArea->threeD.src.pSurfaceEvo[NVKMS_MAIN_LAYER] = + pStagingSurface->pSurfaceEvo; + pWorkArea->threeD.src.viewPortPointIn = origin; + pWorkArea->threeD.dst.pHsSurface = pSurface; + + } else { + + /* Disable the 'staging' operation. */ + + pWorkArea->staging.enabled = FALSE; + + /* + * The 'threeD' operation uses client-provided surfaces as src, and the + * headSurface surface as dst. + */ + + ct_assert(ARRAY_LEN(pWorkArea->threeD.src.pSurfaceEvo) == + NVKMS_MAX_LAYERS_PER_HEAD); + + for (layer = 0; layer < NVKMS_MAX_LAYERS_PER_HEAD; layer++) { + pWorkArea->threeD.src.pSurfaceEvo[layer] = pSurfaceEvo[layer]; + } + pWorkArea->threeD.src.viewPortPointIn.x = pHsChannel->config.viewPortIn.x; + pWorkArea->threeD.src.viewPortPointIn.y = pHsChannel->config.viewPortIn.y; + + pWorkArea->threeD.dst.pHsSurface = pSurface; + } + + return TRUE; +} + +/*! + * Get the clip list for the SwapGroup associated with this pHsChannel. If + * there is no client-specified clip list, use the entire viewPortIn as the clip + * list. + * + * \param[in] pHsChannel The channel in use. + * \param[in] honorSwapGroupClipList + * Whether the returned clip list should honor + * the SwapGroup's current clip list. + * \param[out] pNClips The number of rects in the returned clip list. + * \param[out] ppClipList The returned clip list. + */ +static void Hs3dUpdateStagingSurfaceGetClipList( + const NVHsChannelEvoRec *pHsChannel, + const NvBool honorSwapGroupClipList, + NvU16 *pNClips, + const struct NvKmsRect **ppClipList) +{ + const NVDispEvoRec *pDispEvo = pHsChannel->pDispEvo; + const NVSwapGroupRec *pSwapGroup; + + nvAssert(pDispEvo != NULL); + + pSwapGroup = pDispEvo->pSwapGroup[pHsChannel->apiHead]; + + nvAssert(pSwapGroup != NULL); + + if (pSwapGroup->pClipList == NULL || + !honorSwapGroupClipList) { + + *pNClips = 1; + *ppClipList = &pHsChannel->config.viewPortIn; + } else { + *pNClips = pSwapGroup->nClips; + *ppClipList = pSwapGroup->pClipList; + } +} + +/*! + * Intersect two rects and return the resulting rect. + * + * To do this, convert from NvKmsRect {x,y,width,height} to {x0,x1,y0,y1}, and + * take the max of the x0 values and the min of the x1 values. E.g., + * + * Ax0 Ax1 + * +-----+ + * | Bx0 | Bx1 + * | +--+--+ + * | | | | + * +--+--+ | + * | | + * +-----+ + * . . + * . . + * Cx0 . = MAX(Ax0, Bx0) + * Cx1 = MIN(Ax1, Bx1) + * + * Note that the NvKmsRects are expected to describe regions within the NvU16 + * coordinate space. I.e., x1 = x + width should not overflow 16 bits. The + * headSurface ViewPortIn has this property, and nvHsSetSwapGroupClipList() + * guarantees this for the client-specified clip list. + * + * If intersection is empty, e.g., + * + * Ax0 Ax1 Bx0 Bx1 + * +----+ +----+ + * | | | | + * +----+ +----+ + * . . + * . . + * . Cx0 = MAX(Ax0, Bx0) + * Cx1 = MIN(Ax1, Bx1) + * + * return a rect with width=0, height=0. + */ +static struct NvKmsRect Hs3dIntersectRects( + const struct NvKmsRect rectA, + const struct NvKmsRect rectB) +{ + struct NvKmsRect rect = { }; + + const NvU16 Ax1 = rectA.x + rectA.width; + const NvU16 Ay1 = rectA.y + rectA.height; + + const NvU16 Bx1 = rectB.x + rectB.width; + const NvU16 By1 = rectB.y + rectB.height; + + const NvU16 Cx0 = NV_MAX(rectA.x, rectB.x); + const NvU16 Cy0 = NV_MAX(rectA.y, rectB.y); + + const NvU16 Cx1 = NV_MIN(Ax1, Bx1); + const NvU16 Cy1 = NV_MIN(Ay1, By1); + + nvAssert(!A_plus_B_greater_than_C_U16(rectA.x, rectA.width, NV_U16_MAX)); + nvAssert(!A_plus_B_greater_than_C_U16(rectA.y, rectA.height, NV_U16_MAX)); + + nvAssert(!A_plus_B_greater_than_C_U16(rectB.x, rectB.width, NV_U16_MAX)); + nvAssert(!A_plus_B_greater_than_C_U16(rectB.y, rectB.height, NV_U16_MAX)); + + if ((Cx0 >= Cx1) || (Cy0 >= Cy1)) { + /* Disjoint; return empty rect. */ + return rect; + } + + rect.x = Cx0; + rect.y = Cy0; + rect.width = Cx1 - Cx0; + rect.height = Cy1 - Cy0; + + return rect; +} + +/*! + * Compute the parameters to perform a (non-scaling) blit from client-specified + * input surface to the headSurface staging surface. + * + * \param[in] clipRect In source surface coordinate space. + * \param[in] viewPortIn In source surface coordinate space. + * \param[out] pSrcPoint In source surface coordinate space. + * \param[out] pDstPoint In dest surface coordinate space. + * \param[out] pSize Size of rect to blit. + * + * \return Return FALSE if clipRect and viewPortIn have an empty intersection. + * Otherwise, return TRUE and assign the [out] params. + */ +static NvBool Hs3dUpdateStagingSurfaceGetBlitParams( + const struct NvKmsRect clipRect, + const struct NvKmsRect viewPortIn, + struct NvKmsPoint *pSrcPoint, + struct NvKmsPoint *pDstPoint, + struct NvKmsSize *pSize) +{ + const struct NvKmsRect rect = Hs3dIntersectRects(clipRect, viewPortIn); + + if (rect.width == 0 || rect.height == 0) { + return FALSE; + } + + pSize->width = rect.width; + pSize->height = rect.height; + + pSrcPoint->x = rect.x; + pSrcPoint->y = rect.y; + + /* + * pDstPoint is in the staging surface, which is viewPortIn-sized; position + * pDstPoint relative to viewPortIn. + */ + + nvAssert(rect.x >= viewPortIn.x); + pDstPoint->x = rect.x - viewPortIn.x; + + nvAssert(rect.y >= viewPortIn.y); + pDstPoint->y = rect.y - viewPortIn.y; + + return TRUE; +} + +/*! + * If the staging surface is enabled, copy the content from the client-provided + * surfaces into the staging surface. + * + * \param[in,out] pHsChannel The channel to use for rendering. + * \param[in] pWorkArea The description of what surfaces to use for src + * and dst of the TWOD blits. + */ +static void Hs3dUpdateStagingSurface( + NVHsChannelEvoPtr pHsChannel, + const struct NvHs3dRenderFrameWorkArea *pWorkArea) +{ + NvU16 i, nClips = 0; + const struct NvKmsRect *pClipList = NULL; + + if (!pWorkArea->staging.enabled) { + return; + } + + nvAssert(pWorkArea->staging.dst.pHsSurface != NULL); + + if (pWorkArea->staging.src.pSurfaceEvo[NVKMS_MAIN_LAYER] == NULL) { + return; + } + + Hs3dUpdateStagingSurfaceGetClipList( + pHsChannel, + pWorkArea->staging.honorSwapGroupClipList, + &nClips, + &pClipList); + + Hs3dSetup2dBlit(pHsChannel, + pWorkArea->staging.src.pSurfaceEvo[NVKMS_MAIN_LAYER], + pWorkArea->staging.dst.pHsSurface); + + for (i = 0; i < nClips; i++) { + + struct NvKmsPoint srcPoint = { }; + struct NvKmsPoint dstPoint = { }; + struct NvKmsSize size = { }; + + if (!Hs3dUpdateStagingSurfaceGetBlitParams( + pClipList[i], pHsChannel->config.viewPortIn, + &srcPoint, &dstPoint, &size)) { + continue; + } + + Hs3d2dBlit(pHsChannel, srcPoint, dstPoint, size); + } +} + +/*! + * Render a headSurface frame. + * + * \param[in,out] pHsChannel The channel to use for rendering. + * \param[in] requestType The type of headSurface frame to render. + * \param[in] honorSwapGroupClipList + * Whether to clip the rendering against + * the SwapGroup's current clip list. + * \param[in] dstEye The NVKMS_{LEFT,RIGHT} to which we are + * rendering. + * \param[in] dstBufferIndex The index of the buffer to render into. + * \param[in] pixelShift The pixelShift configuration to use. + * \param[in] destRect The region of pDest to render into. + * \param[in] pSurfaceEvo The surfaces to read from. + * + * \return Return TRUE if there was a headSurface buffer to render into. + * Return FALSE if no headSurface buffer was present. + */ +NvBool nvHs3dRenderFrame( + NVHsChannelEvoPtr pHsChannel, + const NvHsNextFrameRequestType requestType, + const NvBool honorSwapGroupClipList, + const NvU8 dstEye, + const NvU8 dstBufferIndex, + const enum NvKmsPixelShiftMode pixelShift, + const struct NvKmsRect destRect, + const NVSurfaceEvoRec *pSurfaceEvo[NVKMS_MAX_LAYERS_PER_HEAD]) +{ + Nv3dChannelRec *p3d = &pHsChannel->nv3d.channel; + NvBool useOverlay; + const Nv3dVertexAttributeInfoRec attribs[] = { + NV3D_ATTRIB_ENTRY(POSITION, DYNAMIC, 2_32_FLOAT), + NV3D_ATTRIB_ENTRY(TEXCOORD0, DYNAMIC, 4_32_FLOAT), + NV3D_ATTRIB_END, + }; + + NvBool srcFiltering; + ProgramName fragmentProgram; + + Nv3dStreamSurfaceRec streamSurf; + NvPushChannelPtr p = &pHsChannel->nvPush.channel; + NvU32 op, vertexCount; + + int textures[NVIDIA_HEADSURFACE_UNIFORM_SAMPLER_BINDING_NUM] = { }; + + const NvU8 statisticsSlot = + Hs3dStatisticsGetSlot(pHsChannel, requestType, + dstBufferIndex, honorSwapGroupClipList); + + struct NvHs3dRenderFrameWorkArea workArea; + + if (!Hs3dAssignRenderFrameWorkArea(pHsChannel, + honorSwapGroupClipList, + dstEye, + dstBufferIndex, + pSurfaceEvo, &workArea)) { + return FALSE; + } + + useOverlay = (workArea.threeD.src.pSurfaceEvo[NVKMS_OVERLAY_LAYER] != NULL); + srcFiltering = + Hs3dGetSrcFiltering(&pHsChannel->config, pixelShift, useOverlay); + fragmentProgram = + Hs3dGetFragmentProgram(&pHsChannel->config, pixelShift, useOverlay); + + Hs3dStatisticsBefore(pHsChannel, dstEye, statisticsSlot); + + Hs3dUpdateStagingSurface(pHsChannel, &workArea); + + AssignTextureBindingIndices(pHsChannel, workArea.threeD.src.pSurfaceEvo, + textures); + + /* Set up sampler from source surfaces. */ + + AssignRenderTexInfo( + workArea.threeD.src.pSurfaceEvo[NVKMS_MAIN_LAYER], + FALSE /* normalizedCoords */, + srcFiltering, + &pHsChannel->nv3d.texInfo[NVKMS_HEADSURFACE_TEXINFO_SRC]); + + AssignRenderTexInfo( + pHsChannel->config.cursor.pSurfaceEvo, + FALSE /* normalizedCoords */, + srcFiltering, + &pHsChannel->nv3d.texInfo[NVKMS_HEADSURFACE_TEXINFO_CURSOR]); + + AssignRenderTexInfo( + workArea.threeD.src.pSurfaceEvo[NVKMS_OVERLAY_LAYER], + FALSE /* normalizedCoords */, + srcFiltering, + &pHsChannel->nv3d.texInfo[NVKMS_HEADSURFACE_TEXINFO_OVERLAY]); + + /* XXX NVKMS HEADSURFACE TODO: sampler from LUT */ + + /* Set up the source textures. */ + + nv3dLoadTextures(p3d, 0 /* first texture */, + pHsChannel->nv3d.texInfo, + ARRAY_LEN(pHsChannel->nv3d.texInfo)); + + nv3dBindTextures(p3d, fragmentProgram, textures); + + /* + * Set up the destination. + * + * Note: we rely on nvHs3dClearSurface() for setting up the color target and + * surface clip. + */ + nvHs3dClearSurface(pHsChannel, workArea.threeD.dst.pHsSurface, + destRect, pHsChannel->config.yuv420); + + HsSetWindowOffset(pHsChannel, destRect.x, destRect.y); + + /* Load the vertex shader. */ + nv3dLoadProgram(p3d, PROGRAM_NVIDIA_HEADSURFACE_VERTEX); + + /* Load the fragment shader. */ + nv3dLoadProgram(p3d, fragmentProgram); + + /* + * Load vertex and fragment program uniforms. + * + * XXX NVKMS HEADSURFACE TODO: the inputs that influence the program + * uniforms /could/ change from one frame to the next, but in the steady + * state they won't. Should we add tracking to only reload the program + * uniforms when their inputs change? + */ + + LoadFragmentProgramUniforms(pHsChannel, pixelShift, useOverlay, + workArea.threeD.src.viewPortPointIn); + + LoadVertexProgramUniforms(pHsChannel, workArea.threeD.src.viewPortPointIn); + + /* Get the mesh data to use for this frame. */ + + GetWarpMeshData(pHsChannel, &streamSurf, &op, &vertexCount); + + /* Draw the frame of headSurface using a vertex array. */ + + nv3dVasSetup(p3d, attribs, &streamSurf); + nv3dVasBegin(p3d, op); + + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, NV9097_SET_VERTEX_ARRAY_START, 2); + nvPushSetMethodData(p, 0); + nvPushSetMethodData(p, vertexCount); + + nv3dVasEnd(p3d); + + Hs3dStatisticsAfter(pHsChannel, dstEye, statisticsSlot); + + nvPushKickoff(p); + + return TRUE; +} + +/*! + * Use the graphics channel to release the described semaphore. + * + * \param[in,out] pHsChannel The channel to use for the release. + * \param[in] pSurfaceEvo The semaphore surface. + * \param[in] nIsoFormat The NISO format of the surface. + * \param[in] offsetInWords The offset to the semaphore within the surface. + * \param[in] payload The payload to write to the semaphore. + * \param[in] allPreceedingReads Whether to wait for preceding + * reads or writes. + */ +void nvHs3dReleaseSemaphore( + NVHsChannelEvoPtr pHsChannel, + const NVSurfaceEvoRec *pSurfaceEvo, + const enum NvKmsNIsoFormat nIsoFormat, + const NvU16 offsetInWords, + const NvU32 payload, + const NvBool allPreceedingReads) +{ + NvPushChannelPtr p = &pHsChannel->nvPush.channel; + + const NvU32 payloadByteOffsetInSemaphore = + nvKmsSemaphorePayloadOffset(nIsoFormat) * 4; + + const NvU64 gpuAddress = + pSurfaceEvo->gpuAddress + + (offsetInWords * 4) + + payloadByteOffsetInSemaphore; + + const NvU32 afterAllPreceedingReadsOrWrites = + allPreceedingReads ? + NV3D_C(9097, SET_REPORT_SEMAPHORE_D, RELEASE, + AFTER_ALL_PRECEEDING_READS_COMPLETE) : + NV3D_C(9097, SET_REPORT_SEMAPHORE_D, RELEASE, + AFTER_ALL_PRECEEDING_WRITES_COMPLETE); + + const NvU32 operation = + NV3D_C(9097, SET_REPORT_SEMAPHORE_D, OPERATION, RELEASE) | + NV3D_C(9097, SET_REPORT_SEMAPHORE_D, STRUCTURE_SIZE, ONE_WORD) | + NV3D_C(9097, SET_REPORT_SEMAPHORE_D, FLUSH_DISABLE, TRUE) | + NV3D_C(9097, SET_REPORT_SEMAPHORE_D, PIPELINE_LOCATION, ALL) | + afterAllPreceedingReadsOrWrites; + + nvPushMethod(p, NVA06F_SUBCHANNEL_3D, NV9097_SET_REPORT_SEMAPHORE_A, 4); + nvPushSetMethodDataU64(p, gpuAddress); + nvPushSetMethodData(p, payload); + nvPushSetMethodData(p, operation); + + nvPushKickoff(p); +} diff --git a/src/nvidia-modeset/src/nvkms-headsurface-config.c b/src/nvidia-modeset/src/nvkms-headsurface-config.c new file mode 100644 index 000000000..d2e7053e2 --- /dev/null +++ b/src/nvidia-modeset/src/nvkms-headsurface-config.c @@ -0,0 +1,2886 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvkms-headsurface.h" +#include "nvkms-headsurface-priv.h" +#include "nvkms-headsurface-config.h" +#include "nvkms-headsurface-3d.h" +#include "nvkms-headsurface-matrix.h" +#include "nvkms-headsurface-swapgroup.h" +#include "nvkms-flip.h" +#include "nvkms-utils.h" +#include "nvkms-surface.h" +#include "nvkms-private.h" +#include "nvkms-evo.h" +#include "nvkms-modeset.h" +#include "nvkms-prealloc.h" +#include "nvidia-push-utils.h" /* nvPushIdleChannel() */ + +/*! + * Use warp and blend if any of the warp and blend surfaces were specified. + */ +static NvBool UsesWarpAndBlend( + const struct NvKmsSetModeOneHeadRequest *pRequestHead) +{ + return pRequestHead->headSurface.warpMesh.surfaceHandle != 0 || + pRequestHead->headSurface.blendTexSurfaceHandle != 0 || + pRequestHead->headSurface.offsetTexSurfaceHandle != 0; +} + +/* + * If 3D space, the identity matrix would be + * + * 1 0 0 + * 0 1 0 + * 0 0 1 + * + * but for 2D homogeneous coordinate space, any matrix with: + * + * n 0 0 + * 0 n 0 + * 0 0 n + * + * is an identity matrix. + */ +static NvBool Is2dHomogeneousIdentity(const struct NvKmsMatrix *m) +{ + return m->m[0][1] == 0 && + m->m[0][2] == 0 && + m->m[1][0] == 0 && + m->m[1][2] == 0 && + m->m[2][0] == 0 && + m->m[2][1] == 0 && + m->m[0][0] == m->m[1][1] && + m->m[1][1] == m->m[2][2]; +} + +/* + * A scaling transform is any where: + * + * a 0 0 + * 0 b 0 + * 0 0 c + */ +static NvBool IsScalingTransform(const struct NvKmsMatrix *m) +{ + return m->m[0][1] == 0 && + m->m[0][2] == 0 && + m->m[1][0] == 0 && + m->m[1][2] == 0 && + m->m[2][0] == 0 && + m->m[2][1] == 0; +} + +static inline NvBool StateNeedsHeadSurface(const NVHsConfigState state) +{ + return state == NVKMS_HEAD_SURFACE_CONFIG_STATE_PARTIAL_HEAD_SURFACE || + state == NVKMS_HEAD_SURFACE_CONFIG_STATE_FULL_HEAD_SURFACE; +} + +static inline void CopyHsStateOneHeadAllDisps( + NVHsStateOneHeadAllDisps *pDst, + const NVHsStateOneHeadAllDisps *pSrc) +{ + nvkms_memcpy(pDst, pSrc, sizeof(NVHsStateOneHeadAllDisps)); +} + +static inline void MoveHsStateOneHeadAllDisps( + NVHsStateOneHeadAllDisps *pDst, + NVHsStateOneHeadAllDisps *pSrc) +{ + CopyHsStateOneHeadAllDisps(pDst, pSrc); + nvkms_memset(pSrc, 0, sizeof(NVHsStateOneHeadAllDisps)); +} + +/*! + * Free the surfaces tracked in pHsOneHeadAllDisps. + * + * surfacesReused indicates that the NVHsSurfaceRecs were reused from the + * current configuration, and therefore should not actually be freed. If + * surfacesReused is TRUE, update the pHsOneHeadAllDisps structure, but do not + * free the NVHsSurfaceRecs. + * + * \param[in] pDevEvo The device. + * \param[in] pHsOneHeadAllDisps The structure tracking the surfaces. + * \param[in] surfacesReused Whether the surface was reused. + */ +static void HsConfigFreeHeadSurfaceSurfaces( + NVDevEvoRec *pDevEvo, + NVHsStateOneHeadAllDisps *pHsOneHeadAllDisps, + NvBool surfacesReused) +{ + int eye, buf; + + for (buf = 0; buf < pHsOneHeadAllDisps->surfaceCount; buf++) { + + /* + * If we get here, we expect that the headSurface surfaces are still + * allocated. But depending on the configuration, we may only have left + * surfaces, not right surfaces, so only assert for the left eye. + */ + nvAssert(pHsOneHeadAllDisps->surfaces[NVKMS_LEFT][buf].pSurface != + NULL); + + for (eye = NVKMS_LEFT; eye < NVKMS_MAX_EYES; eye++) { + if (!surfacesReused) { + nvHsFreeSurface( + pDevEvo, + pHsOneHeadAllDisps->surfaces[eye][buf].pSurface); + nvHsFreeSurface( + pDevEvo, + pHsOneHeadAllDisps->surfaces[eye][buf].pStagingSurface); + } + pHsOneHeadAllDisps->surfaces[eye][buf].pSurface = NULL; + pHsOneHeadAllDisps->surfaces[eye][buf].pStagingSurface = NULL; + } + } + pHsOneHeadAllDisps->surfaceCount = 0; +} + + +/*! + * Update the NVHsChannelConfig's surfaceSize. + */ +static void HsConfigUpdateOneHeadSurfaceSize( + NVHsChannelConfig *pChannelConfig) +{ + pChannelConfig->surfaceSize = pChannelConfig->frameSize; + + pChannelConfig->stagingSurfaceSize.width = 0; + pChannelConfig->stagingSurfaceSize.height = 0; + + /* + * When SwapGroup is enabled, we double the size of the surface and allocate + * staging surfaces. + * + * Note we double the height, not the width, for better cache locality: + * frames of headSurface will be rendered to either the top of bottom half + * of the surface. + */ + if (pChannelConfig->neededForSwapGroup) { + pChannelConfig->surfaceSize.height *= 2; + + pChannelConfig->stagingSurfaceSize.width = + pChannelConfig->viewPortIn.width; + pChannelConfig->stagingSurfaceSize.height = + pChannelConfig->viewPortIn.height; + } +} + + +/*! + * Update NVHsConfigOneHead + * + * Given the modetimings and NvKmsSetModeHeadSurfaceParams, update the + * NVHsConfigOneHead. If state is PARTIAL or FULL, compute the needed size of + * the headSurface surfaces. + * + * \param[in] state To what extent, if any, headSurface should + * be used. + * \param[in] pTimings The modetimings in use on the head. + * \param[in] p The requested configuration from the client. + * \param[in,out] pChannelConfig The headSurface channel config for the head. + */ +static NvBool HsConfigUpdateOneHead( + const NVHsConfigState state, + const NVHwModeTimingsEvo *pTimings, + const struct NvKmsSetModeHeadSurfaceParams *p, + NVHsChannelConfig *pChannelConfig) +{ + struct NvKmsSize size = { 0 }; + struct NvKmsRect viewPortOut = { 0 }; + + if (state == NVKMS_HEAD_SURFACE_CONFIG_STATE_PARTIAL_HEAD_SURFACE) { + /* + * If PARTIAL, the viewPortOut and surface will have the same size, and + * the viewPortOut will be positioned at the origin of the surface. + * Note that for double scan modes, the headSurface viewPortOut height + * will _not_ be doubled (the line doubling will be done using display + * hardware). + */ + viewPortOut = nvEvoViewPortOutClientView(pTimings); + viewPortOut.x = 0; + viewPortOut.y = 0; + size.width = viewPortOut.width; + size.height = viewPortOut.height; + + /* SW yuv420 modes should always be forced to FULL_HEAD_SURFACE. */ + nvAssert(pTimings->yuv420Mode != NV_YUV420_MODE_SW); + + } else if (state == NVKMS_HEAD_SURFACE_CONFIG_STATE_FULL_HEAD_SURFACE) { + /* + * Note that for both double scan and SW yuv420 modes, the headSurface + * viewPortOut will be adjusted relative to viewPortIn. In both cases + * viewPortOut will match the modetimings and headSurface, not the + * display hardware, will perform the needed scaling/conversion from + * viewPortIn to viewPortOut. + */ + viewPortOut = nvEvoViewPortOutHwView(pTimings); + size.width = nvEvoVisibleWidth(pTimings); + size.height = nvEvoVisibleHeight(pTimings); + } + + /* viewPortOut must fit within frameSize */ + nvAssert((viewPortOut.x + viewPortOut.width) <= size.width); + nvAssert((viewPortOut.y + viewPortOut.height) <= size.height); + + pChannelConfig->state = state; + + pChannelConfig->frameSize = size; + pChannelConfig->viewPortOut = viewPortOut; + + HsConfigUpdateOneHeadSurfaceSize(pChannelConfig); + + if (StateNeedsHeadSurface(state)) { + return nvHsAssignTransformMatrix(pChannelConfig, p); + } + + return TRUE; +} + +static NvBool HsConfigInitModesetOneHeadWarpAndBlendSurface( + const NVDevEvoRec *pDevEvo, + const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, + const NvKmsSurfaceHandle handle, + NVSurfaceEvoPtr *ppSurface) +{ + if (handle == 0) { + *ppSurface = NULL; + return TRUE; + } + + *ppSurface = nvEvoGetSurfaceFromHandleNoCtxDmaOk(pDevEvo, + pOpenDevSurfaceHandles, + handle); + + return *ppSurface != NULL; +} + +/*! + * Initialize NVHsChannelConfig::warpMesh. + * + * If the client's request is invalid, return FALSE. + * Otherwise, assign NVHsChannelConfig::warpMesh appropriately and return TRUE. + * + * \param[in] pOpenDevSurfaceHandles The client's api handles structure. + * \param[in] p The client request structure. + * \param[out] pChannelConfig The channel configuration to be assigned. + */ +static NvBool HsConfigInitModesetWarpMesh( + const NVDevEvoRec *pDevEvo, + const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, + const struct NvKmsSetModeHeadSurfaceParams *p, + NVHsChannelConfig *pChannelConfig) +{ + const NvKmsSurfaceMemoryFormatInfo *pFormatInfo; + NVSurfaceEvoPtr pSurface; + NvU32 neededSize; + + if (p->warpMesh.surfaceHandle == 0) { + return TRUE; + } + + pSurface = nvEvoGetSurfaceFromHandleNoCtxDmaOk(pDevEvo, + pOpenDevSurfaceHandles, + p->warpMesh.surfaceHandle); + if (pSurface == NULL) { + return FALSE; + } + + switch (p->warpMesh.dataType) { + case NVKMS_WARP_MESH_DATA_TYPE_TRIANGLES_XYUVRQ: + if ((p->warpMesh.vertexCount % 3) != 0) { + return FALSE; + } + break; + case NVKMS_WARP_MESH_DATA_TYPE_TRIANGLE_STRIP_XYUVRQ: + break; + default: + return FALSE; + } + + if (p->warpMesh.vertexCount < 3) { + return FALSE; + } + + if (!NV_IS_ALIGNED(pSurface->widthInPixels, 1024)) { + return FALSE; + } + + pFormatInfo = nvKmsGetSurfaceMemoryFormatInfo(pSurface->format); + if (pFormatInfo->rgb.bytesPerPixel != 4) { + return FALSE; + } + + if (pSurface->layout != NvKmsSurfaceMemoryLayoutPitch) { + return FALSE; + } + + neededSize = p->warpMesh.vertexCount * sizeof(Nv3dFloat) * 6; + + if (neededSize > pSurface->planes[0].rmObjectSizeInBytes) { + return FALSE; + } + + pChannelConfig->warpMesh.pSurface = pSurface; + pChannelConfig->warpMesh.vertexCount = p->warpMesh.vertexCount; + pChannelConfig->warpMesh.dataType = p->warpMesh.dataType; + + return TRUE; +} + +/*! + * Initialize pHsConfigOneHead. + * + * This is called once by nvHsConfigInitModeset(), and therefore should only + * assign configuration parameters that do not change when NVHsConfigState + * changes. + * + * Configuration that changes based on NVHsConfigState should be handled by + * HsConfigUpdateOneHead(), so that it can be adjusted by nvHsConfigDowngrade() + * if necessary. + */ +static NvBool HsConfigInitModesetOneHead( + const NVDevEvoRec *pDevEvo, + NVHsConfigState state, + const NvU8 eyeMask, + const NvU32 apiHead, + const NvU32 dispIndex, + const NVHwModeTimingsEvo *pTimings, + const struct NvKmsSize *pViewPortSizeIn, + const struct NvKmsFlipCommonParams *pFlipParams, + const struct NvKmsSetModeHeadSurfaceParams *pHSParams, + const struct NvKmsPerOpenDev *pOpenDev, + NVHsConfigOneHead *pHsConfigOneHead) +{ + const NVEvoApiHandlesRec *pOpenDevSurfaceHandles = + nvGetSurfaceHandlesFromOpenDevConst(pOpenDev); + NVHsChannelConfig *pChannelConfig = &pHsConfigOneHead->channelConfig; + const NVDispEvoRec *pDispEvo = pDevEvo->pDispEvo[dispIndex]; + NvU32 layer; + + /* The passed-in state indicates whether modeset needs headSurface. */ + + pChannelConfig->neededForModeset = StateNeedsHeadSurface(state); + + /* + * If the current SwapGroup configuration needs headSurface, preserve that + * in pChannelConfig and override the state. Note we determine this by + * inspecting the SwapGroups on the device: it isn't sufficient to look at + * pDispEvo->pHsChannel[apiHead]->config.neededForSwapGroup because + * pDispEvo->pHsChannel[apiHead] will by NULL if the head was previously + * disabled and the new modeset is enabling the head. + */ + pChannelConfig->neededForSwapGroup = + nvHsSwapGroupIsHeadSurfaceNeeded(pDispEvo, apiHead); + + if (pDispEvo->pHsChannel[apiHead] != NULL) { + nvAssert(pDispEvo->pHsChannel[apiHead]->config.neededForSwapGroup == + pChannelConfig->neededForSwapGroup); + } + + /* + * If headSurface is needed for SwapGroup, make sure the state is at least + * PARTIAL. + */ + if (pChannelConfig->neededForSwapGroup && !StateNeedsHeadSurface(state)) { + state = NVKMS_HEAD_SURFACE_CONFIG_STATE_PARTIAL_HEAD_SURFACE; + } + + if (state == NVKMS_HEAD_SURFACE_CONFIG_STATE_NO_HEAD_SURFACE) { + nvkms_memset(pHsConfigOneHead, 0, sizeof(*pHsConfigOneHead)); + return TRUE; + } + + pChannelConfig->eyeMask = eyeMask; + + /* + * XXX NVKMS HEADSURFACE TODO: Update viewPortIn.[xy] for panning updates. + */ + if (pFlipParams->viewPortIn.specified) { + pChannelConfig->viewPortIn.x = pFlipParams->viewPortIn.point.x; + pChannelConfig->viewPortIn.y = pFlipParams->viewPortIn.point.y; + } else { + pChannelConfig->viewPortIn.x = 0; + pChannelConfig->viewPortIn.y = 0; + } + + pChannelConfig->viewPortIn.width = pViewPortSizeIn->width; + pChannelConfig->viewPortIn.height = pViewPortSizeIn->height; + + pChannelConfig->yuv420 = (pTimings->yuv420Mode == NV_YUV420_MODE_SW); + + pChannelConfig->blendAfterWarp = pHSParams->blendAfterWarp; + pChannelConfig->pixelShift = pHSParams->pixelShift; + pChannelConfig->resamplingMethod = pHSParams->resamplingMethod; + + if (!HsConfigInitModesetOneHeadWarpAndBlendSurface( + pDevEvo, + pOpenDevSurfaceHandles, + pHSParams->blendTexSurfaceHandle, + &pChannelConfig->pBlendTexSurface)) { + return FALSE; + } + + if (!HsConfigInitModesetOneHeadWarpAndBlendSurface( + pDevEvo, + pOpenDevSurfaceHandles, + pHSParams->offsetTexSurfaceHandle, + &pChannelConfig->pOffsetTexSurface)) { + return FALSE; + } + + if (!HsConfigInitModesetWarpMesh(pDevEvo, + pOpenDevSurfaceHandles, + pHSParams, + pChannelConfig)) { + return FALSE; + } + + /* + * Modeset does not inherit the old flip state, therefore + * make sure to clear the surfaces if the client hasn't specified + * new surfaces. + */ + for (layer = 0; layer < ARRAY_LEN(pFlipParams->layer); layer++) { + if (pFlipParams->layer[layer].surface.specified) { + NvBool ret = nvAssignSurfaceArray(pDevEvo, + pOpenDevSurfaceHandles, + pFlipParams->layer[layer].surface.handle, + FALSE /* isUsedByCursorChannel */, + TRUE /* isUsedByLayerChannel */, + pHsConfigOneHead->layer[layer].pSurfaceEvo); + if (!ret) { + return FALSE; + } + } else { + nvkms_memset(pHsConfigOneHead->layer[layer].pSurfaceEvo, + 0, + sizeof(pHsConfigOneHead->layer[layer].pSurfaceEvo)); + } + } + + /* XXX make cursor stereo-aware */ + if (pFlipParams->cursor.imageSpecified) { + if (!nvAssignCursorSurface(pOpenDev, pDevEvo, &pFlipParams->cursor.image, + &pChannelConfig->cursor.pSurfaceEvo)) { + return FALSE; + } + } else { + pChannelConfig->cursor.pSurfaceEvo = NULL; + } + + if (pFlipParams->cursor.positionSpecified) { + pChannelConfig->cursor.x = pFlipParams->cursor.position.x; + pChannelConfig->cursor.y = pFlipParams->cursor.position.y; + } else { + pChannelConfig->cursor.x = 0; + pChannelConfig->cursor.y = 0; + } + + { + const NVSurfaceEvoRec *pMainSurfaceEvo = + pHsConfigOneHead->layer[NVKMS_MAIN_LAYER].pSurfaceEvo[NVKMS_LEFT]; + + if ((pMainSurfaceEvo != NULL) && + ((pMainSurfaceEvo->format == + NvKmsSurfaceMemoryFormatA2B10G10R10) || + (pMainSurfaceEvo->format == + NvKmsSurfaceMemoryFormatX2B10G10R10))) { + pChannelConfig->hs10bpcHint = TRUE; + } else { + pChannelConfig->hs10bpcHint = FALSE; + } + } + + if (!HsConfigUpdateOneHead(state, pTimings, pHSParams, pChannelConfig)) { + return FALSE; + } + + return TRUE; +} + +/*! + * Validate the requested headSurface configuration. + * + * If the configuration is valid return TRUE. + * Otherwise, assign pReplyHead->status and return FALSE. + * + * The general rules for when to use which status: + * + * INVALID_HEAD_SURFACE is reported for bad API usage; e.g., things such as + * unrecognized enum values. + * + * UNSUPPORTED_HEAD_SURFACE_COMBO is reported when headSurface does not support + * the requested combination of feaures. + * + * UNSUPPORTED_HEAD_SURFACE_FEATURE is reported if the requested configuration + * is not supported on the current GPU (Quadro checks, and similar). + */ +static NvBool HsConfigValidate( + const NVDevEvoRec *pDevEvo, + const struct NvKmsSetModeOneHeadRequest *pRequestHead, + struct NvKmsSetModeOneHeadReply *pReplyHead) +{ + const NvModeTimings *pModeTimings = &pRequestHead->mode.timings; + const struct NvKmsSetModeHeadSurfaceParams *p = &pRequestHead->headSurface; + + /* + * Validate that the requested rotation is a recognized value. + */ + switch (p->rotation) { + case NVKMS_ROTATION_0: + case NVKMS_ROTATION_90: + case NVKMS_ROTATION_180: + case NVKMS_ROTATION_270: + break; + default: + goto failInvalid; + } + + /* + * Check warp&blend feature compatibility. + */ + if (UsesWarpAndBlend(pRequestHead)) { + if (pModeTimings->yuv420Mode == NV_YUV420_MODE_SW) { + goto failUnsupportedCombo; + } + } + + /* + * Validate that the requested pixelShift is a recognized value. + */ + switch (p->pixelShift) { + case NVKMS_PIXEL_SHIFT_NONE: + case NVKMS_PIXEL_SHIFT_4K_TOP_LEFT: + case NVKMS_PIXEL_SHIFT_4K_BOTTOM_RIGHT: + case NVKMS_PIXEL_SHIFT_8K: + break; + default: + goto failInvalid; + } + + /* + * Check pixelShift feature compatibility. + */ + if (p->pixelShift != NVKMS_PIXEL_SHIFT_NONE) { + if (UsesWarpAndBlend(pRequestHead)) { + goto failUnsupportedCombo; + } + + if (pModeTimings->yuv420Mode == NV_YUV420_MODE_SW) { + goto failUnsupportedCombo; + } + } + + + /* + * Validate that the requested resamplingMethod is a recognized value. + */ + + switch (p->resamplingMethod) { + case NVKMS_RESAMPLING_METHOD_BILINEAR: + case NVKMS_RESAMPLING_METHOD_BICUBIC_TRIANGULAR: + case NVKMS_RESAMPLING_METHOD_BICUBIC_BELL_SHAPED: + case NVKMS_RESAMPLING_METHOD_BICUBIC_BSPLINE: + case NVKMS_RESAMPLING_METHOD_BICUBIC_ADAPTIVE_TRIANGULAR: + case NVKMS_RESAMPLING_METHOD_BICUBIC_ADAPTIVE_BELL_SHAPED: + case NVKMS_RESAMPLING_METHOD_BICUBIC_ADAPTIVE_BSPLINE: + case NVKMS_RESAMPLING_METHOD_NEAREST: + break; + default: + goto failInvalid; + } + + /* + * Check resamplingMethod feature compatibility. + * + * The overlay, yuv420, and pixelShift headsurface shaders all texture + * from pixel centers, relying on non-filtered input, and perform + * bilinear filtering manually in the shader. Reject combinations + * of these modes with non-bilinear filtering modes. + */ + if (p->resamplingMethod != NVKMS_RESAMPLING_METHOD_BILINEAR) { + + if (p->pixelShift != NVKMS_PIXEL_SHIFT_NONE) { + goto failUnsupportedCombo; + } + + if (pModeTimings->yuv420Mode == NV_YUV420_MODE_SW) { + goto failUnsupportedCombo; + } + + if (p->fakeOverlay) { + goto failUnsupportedCombo; + } + } + + /* + * PixelShift8k hijacks stereo; prohibit PixelShift8k with real stereo. + */ + if ((pRequestHead->headSurface.pixelShift == NVKMS_PIXEL_SHIFT_8K) && + (pRequestHead->modeValidationParams.stereoMode != + NVKMS_STEREO_DISABLED)) { + goto failUnsupportedCombo; + } + + return TRUE; + +failInvalid: + + pReplyHead->status = NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_HEAD_SURFACE; + return FALSE; + +failUnsupportedCombo: + + pReplyHead->status = + NVKMS_SET_MODE_ONE_HEAD_STATUS_UNSUPPORTED_HEAD_SURFACE_COMBO; + return FALSE; +} + +/*! + * Copy the configuration described in an NVHsChannelEvoRec to an + * NVHsConfigOneHead. + * + * When changing the headSurface configuration, we build an NVHsConfig, which + * describes the headSurface configuration across all heads on the device. + * + * But, the requested configuration may only specify a subset of heads, and the + * rest of the heads are expected to preserve their current configuration. + * + * Use this function to copy the configuration of an existing NVHsChannelEvoRec + * to an NVHsConfigOneHead. + */ +static void HsConfigCopyHsChannelToHsConfig( + NVHsConfigOneHead *pHsConfigOneHead, + const NVHsChannelEvoRec *pHsChannel) +{ + NvU8 eye, layer; + + pHsConfigOneHead->channelConfig = pHsChannel->config; + + /* + * Initialize the surfaces to be used by pHsConfigOneHead. We use the + * surfaces most recently pushed on the flip queue. NVKMS should drain the + * current flip queue as part of applying a new headSurface configuration. + * If the flip queue is already drained, use the surfaces in the flipqueue's + * 'current', + * + * Note that we do not need to update any reference counts here: that is + * done when the hsConfig is applied to the device by nvHsConfigApply(). + * And, in that path refcnts are always incremented for the new surfaces + * before refcnts are decremented for the old surfaces. + */ + + /* both structures have the same number of layers */ + ct_assert(ARRAY_LEN(pHsConfigOneHead->layer) == + ARRAY_LEN(pHsChannel->flipQueue)); + + for (layer = 0; layer < ARRAY_LEN(pHsConfigOneHead->layer); layer++) { + + const NVFlipChannelEvoHwState *pHwState = + HsGetLastFlipQueueEntry(pHsChannel, layer); + + /* both structures have the same number of eyes */ + ct_assert(ARRAY_LEN(pHsConfigOneHead->layer[layer].pSurfaceEvo) == + ARRAY_LEN(pHwState->pSurfaceEvo)); + + for (eye = NVKMS_LEFT; eye < NVKMS_MAX_EYES; eye++) { + pHsConfigOneHead->layer[layer].pSurfaceEvo[eye] = + pHwState->pSurfaceEvo[eye]; + } + } +} + +/*! + * Return whether the NvKmsSetModeRequest requests a change on the disp+head. + */ +static NvBool HsConfigHeadRequested( + const struct NvKmsSetModeRequest *pRequest, + const NvU32 dispIndex, + const NvU32 apiHead) +{ + if ((pRequest->requestedDispsBitMask & NVBIT(dispIndex)) == 0) { + return FALSE; + } + + if ((pRequest->disp[dispIndex].requestedHeadsBitMask & NVBIT(apiHead)) == 0) { + return FALSE; + } + + return TRUE; +} + +/*! + * Get the initial NVHsConfig for the configuration. + * + * For each head that will be active, there are four possible states, + * described by NVHsConfigState. + * + * Construct an optimistic proposed headSurface configuration, + * setting the most hardware-dependent state per head. + * + * If the modeset fails with that configuration, the caller will "downgrade" the + * configuration via nvHsConfigDowngrade() and try again. + * + * \param[in] pDevEvo The device. + * \param[in] pRequest The requested configuration from the client. + * \param[out] pReply The modeset reply structure. + * \param[in] pOpenDev The per-open device data for the client. + * \param[out] pHsConfig The NVHsConfig to populate. + * + * Return FALSE if the requested configuration is not possible, and assign + * status fields in pReply as appropriate. + */ +NvBool nvHsConfigInitModeset( + NVDevEvoRec *pDevEvo, + const struct NvKmsSetModeRequest *pRequest, + struct NvKmsSetModeReply *pReply, + const struct NvKmsPerOpenDev *pOpenDev, + NVHsConfig *pHsConfig) +{ + NvU32 dispIndex, apiHead; + NVDispEvoPtr pDispEvo; + NvBool ret; + + nvkms_memset(pHsConfig, 0, sizeof(*pHsConfig)); + + /* + * Cache the 'commit' flag, to decide later whether to actually allocate + * resources for this pHsConfig. + */ + pHsConfig->commit = pRequest->commit; + + if (!nvGetAllowHeadSurfaceInNvKms(pDevEvo, pOpenDev, pRequest)) { + return TRUE; + } + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + const struct NvKmsSetModeOneHeadRequest *pRequestHead = + &pRequest->disp[dispIndex].head[apiHead]; + struct NvKmsSetModeOneHeadReply *pReplyHead = + &pReply->disp[dispIndex].head[apiHead]; + NVHwModeTimingsEvo *pTimings; + + NvU8 eyeMask = NVBIT(NVKMS_LEFT); + NVHsConfigState state = + NVKMS_HEAD_SURFACE_CONFIG_STATE_NO_HEAD_SURFACE; + + const NvBool is2dHomogeneousIdentity = + !pRequestHead->headSurface.transformSpecified || + Is2dHomogeneousIdentity(&pRequestHead->headSurface.transform); + + /* Skip this head if it is not specified in the request. */ + + if (!HsConfigHeadRequested(pRequest, dispIndex, apiHead)) { + + /* + * If the head is not specified in the new request, but + * currently has a headSurface configuration, propagate that + * configuration to the new pHsConfig. + */ + const NVHsChannelEvoRec *pHsChannel = + pDispEvo->pHsChannel[apiHead]; + + if (pHsChannel != NULL) { + HsConfigCopyHsChannelToHsConfig( + &pHsConfig->apiHead[dispIndex][apiHead], pHsChannel); + } + + continue; + } + + /* Skip this head if it is not driving any dpys. */ + + if (nvDpyIdListIsEmpty(pRequestHead->dpyIdList)) { + continue; + } + + if (!HsConfigValidate(pDevEvo, pRequestHead, pReplyHead)) { + return FALSE; + } + + pTimings = + nvPreallocGet(pDevEvo, PREALLOC_TYPE_HS_INIT_CONFIG_HW_TIMINGS, + sizeof(*pTimings)); + nvkms_memset(pTimings, 0, sizeof(*pTimings)); + + if (!nvGetHwModeTimings(pDispEvo, pRequestHead, pTimings, + NULL /* pInfoFrameCtrl */)) { + nvPreallocRelease(pDevEvo, PREALLOC_TYPE_HS_INIT_CONFIG_HW_TIMINGS); + return FALSE; + } + + if (pRequestHead->headSurface.pixelShift != + NVKMS_PIXEL_SHIFT_NONE) { + + if (pRequestHead->headSurface.pixelShift == + NVKMS_PIXEL_SHIFT_8K) { + eyeMask |= NVBIT(NVKMS_RIGHT); + } + + state = NVKMS_HEAD_SURFACE_CONFIG_STATE_FULL_HEAD_SURFACE; + goto done; + } + + /* + * If any of the stereo modes were requested, we'll need NVKMS_RIGHT + * surfaces if we enable headSurface. + */ + if (pRequestHead->modeValidationParams.stereoMode != + NVKMS_STEREO_DISABLED) { + eyeMask |= NVBIT(NVKMS_RIGHT); + } + + if (pTimings->yuv420Mode == NV_YUV420_MODE_SW) { + state = NVKMS_HEAD_SURFACE_CONFIG_STATE_FULL_HEAD_SURFACE; + goto done; + } + + /* + * XXX NVKMS HEADSURFACE TODO: should resamplingMethod only apply if + * there is viewport scaling? + */ + if (pRequestHead->headSurface.resamplingMethod != + NVKMS_RESAMPLING_METHOD_DEFAULT) { + state = NVKMS_HEAD_SURFACE_CONFIG_STATE_FULL_HEAD_SURFACE; + goto done; + } + + if (pRequestHead->headSurface.forceFullCompositionPipeline) { + state = NVKMS_HEAD_SURFACE_CONFIG_STATE_FULL_HEAD_SURFACE; + goto done; + } + + if (pRequestHead->headSurface.forceCompositionPipeline) { + state = NVKMS_HEAD_SURFACE_CONFIG_STATE_PARTIAL_HEAD_SURFACE; + goto done; + } + + /* + * If Warp & Blend is attempted, transforms are bypassed. We want + * headSurface buffers no matter what. + */ + if (UsesWarpAndBlend(pRequestHead)) { + state = NVKMS_HEAD_SURFACE_CONFIG_STATE_PARTIAL_HEAD_SURFACE; + goto done; + } + + if (pRequestHead->headSurface.fakeOverlay) { + state = NVKMS_HEAD_SURFACE_CONFIG_STATE_PARTIAL_HEAD_SURFACE; + goto done; + } + + if (pRequestHead->headSurface.rotation != NVKMS_ROTATION_0) { + state = NVKMS_HEAD_SURFACE_CONFIG_STATE_PARTIAL_HEAD_SURFACE; + goto done; + } + + if (pRequestHead->headSurface.reflectionX) { + state = NVKMS_HEAD_SURFACE_CONFIG_STATE_PARTIAL_HEAD_SURFACE; + goto done; + } + + if (pRequestHead->headSurface.reflectionY) { + state = NVKMS_HEAD_SURFACE_CONFIG_STATE_PARTIAL_HEAD_SURFACE; + goto done; + } + + if (is2dHomogeneousIdentity) { + const NvU16 hVisible = nvEvoVisibleWidth(pTimings); + const NvU16 vVisible = nvEvoVisibleHeight(pTimings); + + if (pTimings->viewPort.out.width != pTimings->viewPort.in.width || + pTimings->viewPort.out.height != pTimings->viewPort.in.height) { + /* + * If ViewPortIn is not the size of ViewPortOut, we might need + * headSurface to scale. + */ + state = NVKMS_HEAD_SURFACE_CONFIG_STATE_MAYBE_HEAD_SURFACE; + } else if ((pTimings->viewPort.out.xAdjust != 0) || + (pTimings->viewPort.out.yAdjust != 0) || + (pTimings->viewPort.out.width != hVisible) || + (pTimings->viewPort.out.height != vVisible)) { + /* + * If ViewPortOut is not the size of raster, we might need + * headSurface to position ViewPortOut. + */ + state = NVKMS_HEAD_SURFACE_CONFIG_STATE_MAYBE_HEAD_SURFACE; + + } else { + /* + * If this is an identity transform, ViewPortIn is the + * same as ViewPortOut, and ViewPortOut is the same as + * raster, we don't need headSurface. + */ + state = NVKMS_HEAD_SURFACE_CONFIG_STATE_NO_HEAD_SURFACE; + + } + goto done; + } + + /* + * A scaling transformation might be possible with display hardware. + */ + if (pRequestHead->headSurface.transformSpecified && + IsScalingTransform(&pRequestHead->headSurface.transform)) { + state = NVKMS_HEAD_SURFACE_CONFIG_STATE_MAYBE_HEAD_SURFACE; + goto done; + } + + /* + * Otherwise, the transformation is more complicated: fall back to + * headSurface. + */ + + state = NVKMS_HEAD_SURFACE_CONFIG_STATE_PARTIAL_HEAD_SURFACE; +done: + ret = HsConfigInitModesetOneHead(pDevEvo, + state, + eyeMask, + apiHead, + dispIndex, + pTimings, + &pRequestHead->viewPortSizeIn, + &pRequestHead->flip, + &pRequestHead->headSurface, + pOpenDev, + &pHsConfig->apiHead[dispIndex][apiHead]); + + nvPreallocRelease(pDevEvo, PREALLOC_TYPE_HS_INIT_CONFIG_HW_TIMINGS); + + if (!ret) { + pReplyHead->status = + NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_HEAD_SURFACE; + return FALSE; + } + } + } + + return TRUE; +} + + +/*! + * Initialize pHsConfigOneHead for SwapGroup. + * + * In the case that headSurface is not needed for modeset, but is needed for + * SwapGroup, initialize the given pHsConfigOneHead. + * + * This should parallel HsConfigInitModesetOneHead() + */ +static void HsConfigInitSwapGroupOneHead( + const NVDispEvoRec *pDispEvo, + const NvU32 apiHead, + NVHsConfigOneHead *pHsConfigOneHead) +{ + static const struct NvKmsSetModeHeadSurfaceParams + nullHeadSurfaceParams = { }; + + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + const NVHwModeTimingsEvo *pTimings = &pApiHeadState->timings; + const NVHsConfigState state = + NVKMS_HEAD_SURFACE_CONFIG_STATE_PARTIAL_HEAD_SURFACE; + NVHsChannelConfig *pChannelConfig = &pHsConfigOneHead->channelConfig; + NvU32 layer; + + pChannelConfig->eyeMask = NVBIT(NVKMS_LEFT); + + if (pTimings->stereo.mode != NVKMS_STEREO_DISABLED) { + pChannelConfig->eyeMask |= NVBIT(NVKMS_RIGHT); + } + + pChannelConfig->viewPortIn.x = pApiHeadState->viewPortPointIn.x; + pChannelConfig->viewPortIn.y = pApiHeadState->viewPortPointIn.y; + + pChannelConfig->viewPortIn.width = pTimings->viewPort.in.width; + pChannelConfig->viewPortIn.height = pTimings->viewPort.in.height; + + pChannelConfig->hs10bpcHint = pApiHeadState->hs10bpcHint; + + for (layer = 0; layer < pDevEvo->apiHead[apiHead].numLayers; layer++) { + nvApiHeadGetLayerSurfaceArray(pDispEvo, apiHead, layer, + pHsConfigOneHead->layer[layer].pSurfaceEvo); + } + + nvApiHeadGetCursorInfo(pDispEvo, apiHead, + &pChannelConfig->cursor.pSurfaceEvo, + &pChannelConfig->cursor.x, + &pChannelConfig->cursor.y); + + HsConfigUpdateOneHead(state, pTimings, + &nullHeadSurfaceParams, pChannelConfig); +} + + +/*! + * Initial NVHsConfig, applying neededForSwapGroup for the given pSwapGroup to + * the current headSurface configuration. + */ +void nvHsConfigInitSwapGroup( + const NVDevEvoRec *pDevEvo, + const NVSwapGroupRec *pSwapGroup, + const NvBool neededForSwapGroup, + NVHsConfig *pHsConfig) +{ + NvU32 dispIndex, apiHead; + NVDispEvoPtr pDispEvo; + + nvkms_memset(pHsConfig, 0, sizeof(*pHsConfig)); + + pHsConfig->commit = TRUE; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + + for (apiHead = 0; apiHead < pDevEvo->numHeads; apiHead++) { + NvBool neededForModeset = FALSE; + + const NVHsChannelEvoRec *pHsChannel = + pDispEvo->pHsChannel[apiHead]; + + NVHsConfigOneHead *pHsConfigOneHead = + &pHsConfig->apiHead[dispIndex][apiHead]; + NVHsChannelConfig *pChannelConfig = &pHsConfigOneHead->channelConfig; + + /* + * If (pDevEvo->modesetOwner == NULL) that means either the vbios + * console or the NVKMS console might be active, the console + * surface may not be set up to be the source of headSurface + * operations, and NVKMS may be unloaded, so we can't have the + * display rely on headSurface. + */ + if (pDevEvo->modesetOwner == NULL) { + continue; + } + + /* + * + * If (pDevEvo->modesetOwner != NULL) but + * (pDevEvo->lastModesettingClient != pDevEvo->modesetOwner) that + * means the modeset ownership is grabbed by the external client + * but it hasn't performed any modeset and the console is still + * active. + */ + if ((pDevEvo->modesetOwner != NULL) && + (pDevEvo->lastModesettingClient != pDevEvo->modesetOwner)) { + continue; + } + + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { + continue; + } + + /* + * If the head currently has a headSurface configuration, propagate + * that to the new pHsConfig. + */ + if (pHsChannel != NULL) { + HsConfigCopyHsChannelToHsConfig(pHsConfigOneHead, pHsChannel); + } + + /* If this head is not part of the SwapGroup, don't change it. */ + + if (pDispEvo->pSwapGroup[apiHead] != pSwapGroup) { + continue; + } + + neededForModeset = pHsConfigOneHead->channelConfig.neededForModeset; + + pChannelConfig->neededForSwapGroup = neededForSwapGroup; + + /* + * neededForModeset describes whether the current headSurface + * configuration is enabled due to the modeset. + * + * neededForSwapGroup describes whether the new headSurface + * configuration needs to be enabled due to enabling a SwapGroup. + * + * Update pHsConfigOneHead for the given combination of + * neededForModeset + neededForSwapGroup. + */ + + if (neededForModeset) { + + /* + * HeadSurface is already enabled (it is needed for modeset), + * and we are toggling the neededForSwapGroup field. + * + * We should already have a pHsChannel. + */ + nvAssert(pHsChannel != NULL); + + /* + * neededForSwapGroup impacts the computation of + * pChannelConfig->surfaceSize, so recompute that now. + */ + HsConfigUpdateOneHeadSurfaceSize(pChannelConfig); + + } else { + + if (neededForSwapGroup) { + + /* + * HeadSurface is not needed in the current configuration + * for modeset, but now it is needed for SwapGroup. + * + * We don't yet have a pHsChannel. + * + * We need to initialize pHsConfigOneHead, similar to what + * HsConfigInitModesetOneHead() does. + */ + nvAssert(pHsChannel == NULL); + + HsConfigInitSwapGroupOneHead(pDispEvo, apiHead, + pHsConfigOneHead); + + } else { + + /* + * We have headSurface currently enabled. However, it is + * not needed for modeset, and now it isn't needed for + * SwapGroup. + * + * Clear the pHsConfigOneHead. + */ + + nvAssert(pHsChannel != NULL); + + nvkms_memset(pHsConfigOneHead, 0, sizeof(*pHsConfigOneHead)); + } + } + } + } +} + + +/*! + * "Downgrade" the NVHsConfig. + * + * The caller unsuccessfully attempted a modeset with the given NVHsConfig, + * where the heads with state==MAYBE_HEAD_SURFACE used the display hardware + * instead of headSurface, and the heads with state==PARTIAL_HEAD_SURFACE used + * display hardware for ViewPortOut ==> Raster scaling. + * + * Demote one of the heads along the path MAYBE_HEAD_SURFACE -> + * PARTIAL_HEAD_SURFACE -> FULL_HEAD_SURFACE, so that the caller can try the + * modeset again. + * + * \param[in] pDevEvo The device. + * \param[in] pRequest The requested configuration from the client. + * \param[in,out] pHsConfig The NVHsConfig to downgrade. + * + * \return TRUE if a head could be downgraded. FALSE if there are no + * more heads to downgrade. + */ +NvBool nvHsConfigDowngrade( + NVDevEvoRec *pDevEvo, + const struct NvKmsSetModeRequest *pRequest, + NVHsConfig *pHsConfig) +{ + NvU32 dispIndex, apiHead, try; + NVDispEvoPtr pDispEvo; + + for (try = 0; try < 2; try++) { + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + const struct NvKmsSetModeOneHeadRequest *pRequestHead = + &pRequest->disp[dispIndex].head[apiHead]; + NVHsChannelConfig *pChannelConfig = + &pHsConfig->apiHead[dispIndex][apiHead].channelConfig; + + NVHsConfigState state = + NVKMS_HEAD_SURFACE_CONFIG_STATE_NO_HEAD_SURFACE; + + if (!HsConfigHeadRequested(pRequest, dispIndex, apiHead)) { + continue; + } + + /* Skip this head if it is not driving any dpys. */ + + if (nvDpyIdListIsEmpty(pRequestHead->dpyIdList)) { + continue; + } + + /* + * On the first try, downgrade from + * MAYBE_HEAD_SURFACE to PARTIAL_HEAD_SURFACE. + */ + if ((try == 0) && + (pChannelConfig->state == + NVKMS_HEAD_SURFACE_CONFIG_STATE_MAYBE_HEAD_SURFACE)) { + + state = NVKMS_HEAD_SURFACE_CONFIG_STATE_PARTIAL_HEAD_SURFACE; + } + + /* + * On the second try, downgrade from + * PARTIAL_HEAD_SURFACE to FULL_HEAD_SURFACE. + */ + if ((try == 1) && + (pChannelConfig->state == + NVKMS_HEAD_SURFACE_CONFIG_STATE_PARTIAL_HEAD_SURFACE)) { + + state = NVKMS_HEAD_SURFACE_CONFIG_STATE_FULL_HEAD_SURFACE; + } + + if (state != NVKMS_HEAD_SURFACE_CONFIG_STATE_NO_HEAD_SURFACE) { + NvU32 ret; + const struct NvKmsSetModeHeadSurfaceParams *p = + &pRequest->disp[dispIndex].head[apiHead].headSurface; + NVHwModeTimingsEvo *pTimings = + nvPreallocGet(pDevEvo, PREALLOC_TYPE_HS_INIT_CONFIG_HW_TIMINGS, + sizeof(*pTimings)); + nvkms_memset(pTimings, 0, sizeof(*pTimings)); + + if (!nvGetHwModeTimings(pDispEvo, pRequestHead, pTimings, + NULL /* pInfoFrameCtrl */)) { + nvPreallocRelease(pDevEvo, PREALLOC_TYPE_HS_INIT_CONFIG_HW_TIMINGS); + return FALSE; + } + + ret = HsConfigUpdateOneHead(state, + pTimings, + p, + pChannelConfig); + + nvPreallocRelease(pDevEvo, PREALLOC_TYPE_HS_INIT_CONFIG_HW_TIMINGS); + + return ret; + } + } + } + } + + return FALSE; +} + +/*! + * Return whether the given pDevEvoHsConfig satisfies the specified eyeMask. + */ +static NvBool HsConfigEyeMasksMatch( + const NVHsStateOneHeadAllDisps *pDevEvoHsConfig, + const NvU8 eyeMask) +{ + NvU8 eye, buf; + + for (eye = NVKMS_LEFT; eye < NVKMS_MAX_EYES; eye++) { + + if ((NVBIT(eye) & eyeMask) == 0) { + continue; + } + + for (buf = 0; buf < pDevEvoHsConfig->surfaceCount; buf++) { + if (pDevEvoHsConfig->surfaces[eye][buf].pSurface == NULL) { + return FALSE; + } + } + } + + return TRUE; +} + + +/*! + * Return an NvKmsSize that is the maximum of sizeA and sizeB in each dimension. + */ +static inline struct NvKmsSize HsConfigGetMaxNvKmsSize( + struct NvKmsSize sizeA, + struct NvKmsSize sizeB) +{ + struct NvKmsSize maxSize; + + maxSize.width = NV_MAX(sizeA.width, sizeB.width); + maxSize.height = NV_MAX(sizeA.height, sizeB.height); + + return maxSize; +} + +/*! + * Reconcile hs10bpcHint across multiple disps. + * + * If any disp is X2B10G10R10, use X2B10G10R10. Otherwise, use A8R8G8B8. + */ +static enum NvKmsSurfaceMemoryFormat HsConfigGetMaxFormat( + enum NvKmsSurfaceMemoryFormat prevFormat, + NvBool hs10bpcHint) +{ + /* + * prevFormat is initialized to 0; it should not collide with X2B10G10R10 or + * A8R8G8B8 + */ + ct_assert(NvKmsSurfaceMemoryFormatX2B10G10R10 != 0); + ct_assert(NvKmsSurfaceMemoryFormatA8R8G8B8 != 0); + + if (prevFormat == NvKmsSurfaceMemoryFormatX2B10G10R10) { + return prevFormat; + } + + return hs10bpcHint ? + NvKmsSurfaceMemoryFormatX2B10G10R10 : NvKmsSurfaceMemoryFormatA8R8G8B8; +} + +/*! + * Return whether sizeA is greater than or equal to sizeB in both dimensions. + */ +static inline NvBool HsConfigNvKmsSizeIsGreaterOrEqual( + struct NvKmsSize sizeA, + struct NvKmsSize sizeB) +{ + return (sizeA.width >= sizeB.width) && (sizeA.height >= sizeB.height); +} + + +typedef struct _NVHsConfigAllocResourcesWorkArea { + NvBool needsHeadSurface; + NvBool neededForSwapGroup; + NvU8 eyeMask; + struct NvKmsSize headSurfaceSize; + struct NvKmsSize headSurfaceStagingSize; + enum NvKmsSurfaceMemoryFormat format; +} NVHsConfigAllocResourcesWorkArea; + + +/*! + * Allocate an NVHsSurfaceRec and clear its memory on all subdevices. + * + * \return NULL if there was an allocation failure. Otherwise, return a + * pointer to the allocated NVHsSurfaceRec. + */ +static NVHsSurfacePtr HsConfigAllocSurfacesOneSurface( + NVDevEvoRec *pDevEvo, + const NVHsConfig *pHsConfig, + const NvU32 apiHead, + const NvBool displayHardwareAccess, + struct NvKmsSize surfaceSize, + const enum NvKmsSurfaceMemoryFormat format) +{ + NvU32 dispIndex; + NVDispEvoPtr pDispEvo; + NVHsSurfacePtr pSurface; + + pSurface = nvHsAllocSurface(pDevEvo, + displayHardwareAccess, + format, + surfaceSize.width, + surfaceSize.height); + if (pSurface == NULL) { + return NULL; + } + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + const NVHsConfigOneHead *pHsConfigOneHead = + &pHsConfig->apiHead[dispIndex][apiHead]; + NVHsChannelEvoRec *pHsChannel = pHsConfigOneHead->pHsChannel; + + if (pHsChannel != NULL) { + const struct NvKmsRect surfaceRect = { + .x = 0, + .y = 0, + .width = surfaceSize.width, + .height = surfaceSize.height, + }; + + nvHs3dClearSurface(pHsChannel, pSurface, surfaceRect, + pHsConfigOneHead->channelConfig.yuv420); + } + } + + return pSurface; +} + + +/*! + * Allocate all the surfaces need for one 'buf'. + * + * Only update pHsConfig if all allocations succeed. + * + * \return FALSE if there was an allocation failure. Otherwise, return TRUE + * and update pHsConfig to point at the new allocations. + */ +static NvBool HsConfigAllocSurfacesOneBuf( + NVDevEvoRec *pDevEvo, + NVHsConfig *pHsConfig, + const NvU32 apiHead, + const NvU8 buf, + const NVHsConfigAllocResourcesWorkArea *pWorkArea) +{ + NVHsSurfacePtr pSurface[NVKMS_MAX_EYES] = { }; + NVHsSurfacePtr pStagingSurface[NVKMS_MAX_EYES] = { }; + NvU8 eye; + + const NvBool needsStaging = + (pWorkArea->headSurfaceStagingSize.width != 0) && + (pWorkArea->headSurfaceStagingSize.height != 0); + + for (eye = NVKMS_LEFT; eye < NVKMS_MAX_EYES; eye++) { + + if ((NVBIT(eye) & pWorkArea->eyeMask) == 0) { + continue; + } + + pSurface[eye] = + HsConfigAllocSurfacesOneSurface(pDevEvo, + pHsConfig, + apiHead, + TRUE, /* requireCtxDma */ + pWorkArea->headSurfaceSize, + pWorkArea->format); + if (pSurface[eye] == NULL) { + goto fail; + } + + if (needsStaging) { + pStagingSurface[eye] = + HsConfigAllocSurfacesOneSurface( + pDevEvo, + pHsConfig, + apiHead, + FALSE, /* displayHardwareAccess */ + pWorkArea->headSurfaceStagingSize, + pWorkArea->format); + if (pStagingSurface[eye] == NULL) { + goto fail; + } + } + } + + /* All allocations succeeded, we can safely update pHsConfig. */ + + for (eye = NVKMS_LEFT; eye < NVKMS_MAX_EYES; eye++) { + pHsConfig->apiHeadAllDisps[apiHead].surfaces[eye][buf].pSurface = + pSurface[eye]; + pHsConfig->apiHeadAllDisps[apiHead].surfaces[eye][buf].pStagingSurface = + pStagingSurface[eye]; + } + + return TRUE; + +fail: + + /* Something failed; free everything. nvHsFreeSurface(NULL) is a noop. */ + + for (eye = NVKMS_LEFT; eye < NVKMS_MAX_EYES; eye++) { + nvHsFreeSurface(pDevEvo, pSurface[eye]); + nvHsFreeSurface(pDevEvo, pStagingSurface[eye]); + } + + return FALSE; +} + + +/*! + * Allocate all the surfaces needed for one head. + * + * \return FALSE if there was an irrecoverable allocation failure. Otherwise, + * return TRUE and update pHsConfig. + */ +static NvBool HsConfigAllocSurfacesOneHead( + NVDevEvoRec *pDevEvo, + NVHsConfig *pHsConfig, + const NvU32 apiHead, + const NVHsConfigAllocResourcesWorkArea *pWorkArea) +{ + NVHsStateOneHeadAllDisps *pHsOneHeadAllDisps = + &pHsConfig->apiHeadAllDisps[apiHead]; + NvU8 buf; + + pHsOneHeadAllDisps->surfaceCount = 0; + + for (buf = 0; buf < NVKMS_HEAD_SURFACE_MAX_BUFFERS; buf++) { + + /* + * HeadSurface normally double buffers its rendering and flipping + * (NVKMS_HEAD_SURFACE_MAX_BUFFERS == 2), but in most configurations it + * can function single-buffered if necessary (so only buf == 0 is + * "mustHave"). + * + * However, for SwapGroups, the two buffers are used differently, and we + * cannot really accommodate single-buffered use. So, both buffers are + * "mustHave" when neededForSwapGroup. + */ + const NvBool mustHave = (buf == 0) || pWorkArea->neededForSwapGroup; + + if (!HsConfigAllocSurfacesOneBuf(pDevEvo, + pHsConfig, + apiHead, + buf, + pWorkArea)) { + if (mustHave) { + nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, + "Failed to allocate memory for composition pipeline"); + HsConfigFreeHeadSurfaceSurfaces(pDevEvo, + pHsOneHeadAllDisps, + FALSE /* surfacesReused */); + return FALSE; + } else { + nvEvoLogDev(pDevEvo, EVO_LOG_WARN, + "Failed to allocate memory for composition pipeline; continuing with potential tearing."); + break; + } + } + + pHsOneHeadAllDisps->surfaceCount++; + } + + nvAssert(pHsOneHeadAllDisps->surfaceCount > 0); + + pHsOneHeadAllDisps->size = pWorkArea->headSurfaceSize; + pHsOneHeadAllDisps->stagingSize = pWorkArea->headSurfaceStagingSize; + + return TRUE; +} + + +/*! + * Allocate resources needed for the NVHsConfig. + * + * The headSurface configuration may need additional resources to be allocated. + * Determine what resources are needed, allocate them, and track them in the + * NVHsConfig. We do not know if this configuration will be usable by modeset, + * so we do not alter pDevEvo state in this function. + * + * This function could be called multiple times for the same NVHsConfig. If a + * modeset fails, the caller will call nvHsConfigFreeResources(), then + * nvHsConfigDowngrade(), and then call this again. + * + * \param[in] pDevEvo The device. + * \param[in,out] pHsConfig The NVHsConfig to allocate resources for. + * + * \return TRUE if needed resources were allocated. FALSE if resources + * could not be allocated. + */ +NvBool nvHsConfigAllocResources( + NVDevEvoRec *pDevEvo, + NVHsConfig *pHsConfig) +{ + NvU32 dispIndex, apiHead; + NVDispEvoPtr pDispEvo; + + NVHsConfigAllocResourcesWorkArea workArea[NVKMS_MAX_HEADS_PER_DISP] = { }; + + /* + * Handle SLI Mosaic: surface allocations are broadcast across + * subdevices, so compute the maximum surface sizes needed for + * each head on all subdevices. + */ + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + const NVHsChannelConfig *pChannelConfig = + &pHsConfig->apiHead[dispIndex][apiHead].channelConfig; + + /* Do we need headSurface on this head? */ + if (!StateNeedsHeadSurface(pChannelConfig->state)) { + continue; + } + + /* + * XXX NVKMS HEADSURFACE TODO: perform validation of headSurface + * here. + */ + + /* + * If the client allocated the device with no3d, but we need + * headSurface, fail. + */ + if (pDevEvo->pHsDevice == NULL) { + return FALSE; + } + + workArea[apiHead].needsHeadSurface = TRUE; + workArea[apiHead].eyeMask |= pChannelConfig->eyeMask; + + workArea[apiHead].neededForSwapGroup = + workArea[apiHead].neededForSwapGroup || + pChannelConfig->neededForSwapGroup; + + workArea[apiHead].headSurfaceSize = + HsConfigGetMaxNvKmsSize(workArea[apiHead].headSurfaceSize, + pChannelConfig->surfaceSize); + + workArea[apiHead].headSurfaceStagingSize = + HsConfigGetMaxNvKmsSize(workArea[apiHead].headSurfaceStagingSize, + pChannelConfig->stagingSurfaceSize); + workArea[apiHead].format = + HsConfigGetMaxFormat(workArea[apiHead].format, + pChannelConfig->hs10bpcHint); + } + } + + /* + * Return early without any resource allocation if this configuration is not + * going to be committed. + */ + if (!pHsConfig->commit) { + return TRUE; + } + + /* Allocate the 3d channel where necessary. */ + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + + for (apiHead = 0; apiHead < pDevEvo->numHeads; apiHead++) { + NVHsConfigOneHead *pHsConfigOneHead = + &pHsConfig->apiHead[dispIndex][apiHead]; + NVHsChannelConfig *pChannelConfig = + &pHsConfigOneHead->channelConfig; + + if (!StateNeedsHeadSurface(pChannelConfig->state)) { + continue; + } + + if (pDispEvo->pHsChannel[apiHead] != NULL) { + /* Reuse the existing headSurface channel, if it exists. */ + pHsConfigOneHead->pHsChannel = pDispEvo->pHsChannel[apiHead]; + pHsConfigOneHead->channelReused = TRUE; + } else { + /* Otherwise, allocate a new channel. */ + pHsConfigOneHead->channelReused = FALSE; + pHsConfigOneHead->pHsChannel = + nvHsAllocChannel(pDispEvo, apiHead); + + if (pHsConfigOneHead->pHsChannel == NULL) { + nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, + "Failed to allocate channel for composition pipeline"); + nvHsConfigFreeResources(pDevEvo, pHsConfig); + return FALSE; + } + } + } + } + + /* + * Assign NVHsConfig::apiHeadAllDisps[], and either reuse the existing surfaces + * (if they are large enough), or allocate new surfaces. + */ + for (apiHead = 0; apiHead < pDevEvo->numHeads; apiHead++) { + const NVHsStateOneHeadAllDisps *pDevEvoHsConfig = + &pDevEvo->apiHeadSurfaceAllDisps[apiHead]; + + /* There should not (yet?) be any surfaces allocated for this head */ + nvAssert(pHsConfig->apiHeadAllDisps[apiHead].surfaceCount == 0); + + if (!workArea[apiHead].needsHeadSurface) { + continue; + } + + /* + * If NVKMS already has sufficiently large surfaces for this head, reuse + * them instead of allocating new ones. + * + * XXX NVKMS HEADSURFACE TODO: when transitioning from a large mode to a + * small mode, this will keep the large mode's headSurface surfaces. + * Perhaps we should not reuse the existing surfaces if they are + * significantly larger than necessary. Or, perhaps we should do some + * sort of headSurface compaction after applying surfaces to the device? + * What if the current config is tearing (surfaceCount == 1), and we + * could upgrade to (surfaceCount == 2)? + * + * The same problem applies when transitioning from stereo to mono + * (we'll leave a right eye surface allocated but unused). + * + * The same problem applies when transitioning from a configuration that + * needs stagingSurfaces to a configuration that doesn't. + */ + if ((pDevEvoHsConfig->surfaceCount > 0) && + HsConfigNvKmsSizeIsGreaterOrEqual( + pDevEvoHsConfig->size, + workArea[apiHead].headSurfaceSize) && + HsConfigNvKmsSizeIsGreaterOrEqual( + pDevEvoHsConfig->stagingSize, + workArea[apiHead].headSurfaceStagingSize) && + HsConfigEyeMasksMatch(pDevEvoHsConfig, workArea[apiHead].eyeMask)) { + CopyHsStateOneHeadAllDisps(&pHsConfig->apiHeadAllDisps[apiHead], + pDevEvoHsConfig); + pHsConfig->surfacesReused[apiHead] = TRUE; + continue; + } + + /* Otherwise, allocate new surfaces. */ + + if (!HsConfigAllocSurfacesOneHead(pDevEvo, + pHsConfig, + apiHead, + &workArea[apiHead])) { + nvHsConfigFreeResources(pDevEvo, pHsConfig); + return FALSE; + } + + /* + * XXX NVKMS HEADSURFACE TODO: Populate the surface with the correct + * screen contents. + * + * It is unclear if that is desirable behavior: if we're reusing an + * existing headSurface surface, we shouldn't clobber existing content + * before we flip. + */ + } + + return TRUE; +} + +/*! + * Free resources allocated for NVHsConfig but not used by the current + * configuration. + * + * nvHsConfigAllocResources() allocates resources, after first attempting to + * reuse the current configuration's existing resources. Those will be + * propagated to the pDevEvo by nvHsConfigApply() if the modeset succeeds. + * + * However, if the modeset fails, this function needs to free everything + * allocated by nvHsConfigAllocResources(). + * + * \param[in] pDevEvo The device + * \param[in,out] pHsConfig The NVHsConfigRec whose resources should be freed. + */ +void nvHsConfigFreeResources( + NVDevEvoRec *pDevEvo, + NVHsConfig *pHsConfig) +{ + NvU32 dispIndex, apiHead; + NVDispEvoPtr pDispEvo; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + for (apiHead = 0; apiHead < pDevEvo->numHeads; apiHead++) { + NVHsConfigOneHead *pHsConfigOneHead = + &pHsConfig->apiHead[dispIndex][apiHead]; + + if (pHsConfigOneHead->pHsChannel == NULL) { + continue; + } + + if (!pHsConfigOneHead->channelReused) { + nvHsFreeChannel(pHsConfigOneHead->pHsChannel); + } + + pHsConfigOneHead->pHsChannel = NULL; + pHsConfigOneHead->channelReused = FALSE; + } + } + + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + HsConfigFreeHeadSurfaceSurfaces(pDevEvo, + &pHsConfig->apiHeadAllDisps[apiHead], + pHsConfig->surfacesReused[apiHead]); + pHsConfig->surfacesReused[apiHead] = FALSE; + } +} + +/*! + * Initialize each layer's flip queue. + */ +static void HsConfigInitFlipQueue( + NVHsChannelEvoPtr pHsChannel, + const NVHsConfigOneHead *pHsConfigOneHead) +{ + NvU8 layer, eye; + + /* + * Initialize flipQueueMainLayerState with the surfaces specified in the modeset + * request. + */ + for (eye = 0; eye < NVKMS_MAX_EYES; eye++) { + pHsChannel->flipQueueMainLayerState.pSurfaceEvo[eye] = + pHsConfigOneHead->layer[NVKMS_MAIN_LAYER].pSurfaceEvo[eye]; + } + + /* + * Push a single flip queue entry into each layer's flip queue, using the + * surfaces specified in the modeset request. Later, the nvHsNextFrame() => + * HsUpdateFlipQueueCurrent() call chain will pop the entry from the queue + * and put it in "current". + * + * This might seem a little indirect, but we do things this way so that we + * use common paths for reference count bookkeeping. + */ + for (layer = 0; layer < ARRAY_LEN(pHsConfigOneHead->layer); layer++) { + + NVFlipChannelEvoHwState hwState = { }; + + nvkms_memset(&pHsChannel->flipQueue[layer], 0, + sizeof(pHsChannel->flipQueue[layer])); + + nvListInit(&pHsChannel->flipQueue[layer].queue); + + for (eye = 0; eye < ARRAY_LEN(hwState.pSurfaceEvo); eye++) { + hwState.pSurfaceEvo[eye] = + pHsConfigOneHead->layer[layer].pSurfaceEvo[eye]; + } + + nvHsPushFlipQueueEntry(pHsChannel, layer, &hwState); + } +} + +static void HsConfigUpdateSurfaceRefCount( + const NVHsChannelConfig *pChannelConfig, + NvBool increase) +{ + HsChangeSurfaceFlipRefCount(pChannelConfig->warpMesh.pSurface, increase); + + HsChangeSurfaceFlipRefCount(pChannelConfig->pBlendTexSurface, increase); + + HsChangeSurfaceFlipRefCount(pChannelConfig->pOffsetTexSurface, increase); + + HsChangeSurfaceFlipRefCount(pChannelConfig->cursor.pSurfaceEvo, increase); +} + +/*! + * Check if flipLock should be allowed on this device. + * + * If any head has headSurface enabled, flipLock might interfere with per-head + * presentation, so prohibit flipLock. + */ +static NvBool HsConfigAllowFlipLock(const NVDevEvoRec *pDevEvo) +{ + NvU32 dispIndex, apiHead; + NVDispEvoPtr pDispEvo; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + if (pDispEvo->pHsChannel[apiHead] != NULL) { + return FALSE; + } + } + } + + return TRUE; +} + +static void HsMainLayerFlip( + NVHsChannelEvoPtr pHsChannel, + NvKmsSurfaceHandle surfaceHandle[NVKMS_MAX_EYES], + const struct NvKmsPoint viewPortPointIn, + const struct NvKmsSetCursorImageCommonParams cursorImage, + const struct NvKmsMoveCursorCommonParams cursorPosition) +{ + const NVDispEvoRec *pDispEvo = pHsChannel->pDispEvo; + NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + const NvU32 apiHead = pHsChannel->apiHead; + struct NvKmsFlipRequest *pRequest; + struct NvKmsFlipParams *pFlipParams; + const NvU32 sd = pDispEvo->displayOwner; + NvBool ret; + NvU8 eye; + struct NvKmsFlipCommonParams *pParamsOneHead; + + /* + * Use a preallocated NvKmsFlipRequest, so that we don't have to allocate + * memory here (and deal with allocation failure). + */ + pFlipParams = &pHsChannel->scratchParams; + + nvkms_memset(pFlipParams, 0, sizeof(*pFlipParams)); + + pRequest = &pFlipParams->request; + + pRequest->commit = NV_TRUE; + + pParamsOneHead = &pRequest->sd[sd].head[apiHead]; + + pParamsOneHead->layer[NVKMS_MAIN_LAYER].surface.specified = TRUE; + + for (eye = NVKMS_LEFT; eye < NVKMS_MAX_EYES; eye++) { + pParamsOneHead->layer[NVKMS_MAIN_LAYER].surface.handle[eye] = surfaceHandle[eye]; + } + + if (surfaceHandle[NVKMS_LEFT] != 0) { + NVEvoApiHandlesRec *pOpenDevSurfaceHandles = + nvGetSurfaceHandlesFromOpenDev(pDevEvo->pNvKmsOpenDev); + NVSurfaceEvoPtr pSurfaceEvo = + nvEvoGetPointerFromApiHandle(pOpenDevSurfaceHandles, surfaceHandle[NVKMS_LEFT]); + + pParamsOneHead->layer[NVKMS_MAIN_LAYER].sizeIn.specified = TRUE; + pParamsOneHead->layer[NVKMS_MAIN_LAYER].sizeIn.val.width = + pSurfaceEvo->widthInPixels; + pParamsOneHead->layer[NVKMS_MAIN_LAYER].sizeIn.val.height = + pSurfaceEvo->heightInPixels; + + pParamsOneHead->layer[NVKMS_MAIN_LAYER].sizeOut.specified = TRUE; + pParamsOneHead->layer[NVKMS_MAIN_LAYER].sizeOut.val = + pParamsOneHead->layer[NVKMS_MAIN_LAYER].sizeIn.val; + } + + /* clear completion notifier and sync objects */ + pParamsOneHead->layer[NVKMS_MAIN_LAYER].completionNotifier.specified = TRUE; + pParamsOneHead->layer[NVKMS_MAIN_LAYER].syncObjects.specified = TRUE; + + pParamsOneHead->viewPortIn.specified = TRUE; + pParamsOneHead->viewPortIn.point = viewPortPointIn; + + pParamsOneHead->cursor.image = cursorImage; + pParamsOneHead->cursor.imageSpecified = TRUE; + + pParamsOneHead->cursor.position = cursorPosition; + pParamsOneHead->cursor.positionSpecified = TRUE; + + pRequest->sd[sd].requestedHeadsBitMask = NVBIT(apiHead); + + ret = nvFlipEvo(pDevEvo, + pDevEvo->pNvKmsOpenDev, + pRequest, + &pFlipParams->reply, + FALSE /* skipUpdate */, + FALSE /* allowFlipLock */); + + if (!ret) { + nvAssert(!"headSurface main layer flip failed?"); + } +} + +/*! + * When disabling headSurface, restore the non-headSurface surface, if + * necessary. + * + * HeadSurface is disabled in two paths: as part of modeset, and as part of + * leaving a SwapGroup. In the modeset case, we do not need to do anything + * here: the modeset already specified the correct surface. + * + * But, in the case of disabling headSurface due to leaving a SwapGroup, we need + * to restore the client's non-headSurface surface(s) (i.e., the surfaces in + * flipQueueMainLayerState). So, we check for the case of transitioning from a + * configuration with: + * + * neededForModeset == FALSE + * neededForSwapGroup == TRUE + * + * to a configuration with: + * + * neededForModeset == FALSE + * neededForSwapGroup == FALSE + * + * To flip in that case, use HsMainLayerFlip() => nvFlipEvo(), which populates an + * NvKmsFlipRequest structure. This takes surface handles, so temporarily + * generate NvKmsSurfaceHandles in pNvKmsOpenDev's namespace. + */ +static void HsConfigRestoreMainLayerSurface( + NVDispEvoPtr pDispEvo, + NVHsChannelEvoPtr pHsChannelOld, + const NVHsChannelConfig *pHsChannelConfigNew) +{ + if (!pHsChannelOld->config.neededForModeset && + pHsChannelOld->config.neededForSwapGroup && + !pHsChannelConfigNew->neededForModeset && + !pHsChannelConfigNew->neededForSwapGroup) { + + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NVEvoApiHandlesRec *pNvKmsOpenDevSurfaceHandles = + nvGetSurfaceHandlesFromOpenDev(pDevEvo->pNvKmsOpenDev); + NVSurfaceEvoRec *pSurfaceEvo[NVKMS_MAX_EYES] = { }; + NvKmsSurfaceHandle surfaceHandle[NVKMS_MAX_EYES] = { }; + NvU8 eye; + + struct NvKmsSetCursorImageCommonParams cursorImage = { }; + + const struct NvKmsMoveCursorCommonParams cursorPosition = { + .x = pHsChannelOld->config.cursor.x, + .y = pHsChannelOld->config.cursor.y, + }; + + const struct NvKmsPoint viewPortPointIn = { + .x = pHsChannelOld->config.viewPortIn.x, + .y = pHsChannelOld->config.viewPortIn.y, + }; + + for (eye = NVKMS_LEFT; eye < NVKMS_MAX_EYES; eye++) { + + pSurfaceEvo[eye] = + pHsChannelOld->flipQueueMainLayerState.pSurfaceEvo[eye]; + + if (pSurfaceEvo[eye] == NULL) { + continue; + } + + surfaceHandle[eye] = + nvEvoCreateApiHandle(pNvKmsOpenDevSurfaceHandles, + pSurfaceEvo[eye]); + } + + if (pHsChannelOld->config.cursor.pSurfaceEvo != NULL) { + + cursorImage.surfaceHandle[NVKMS_LEFT] = + nvEvoCreateApiHandle(pNvKmsOpenDevSurfaceHandles, + pHsChannelOld->config.cursor.pSurfaceEvo); + cursorImage.cursorCompParams.colorKeySelect = + NVKMS_COMPOSITION_COLOR_KEY_SELECT_DISABLE; + cursorImage.cursorCompParams.blendingMode[1] = + NVKMS_COMPOSITION_BLENDING_MODE_PREMULT_ALPHA; + } + + HsMainLayerFlip( + pHsChannelOld, + surfaceHandle, + viewPortPointIn, + cursorImage, + cursorPosition); + + for (eye = NVKMS_LEFT; eye < NVKMS_MAX_EYES; eye++) { + + if (pSurfaceEvo[eye] == NULL) { + continue; + } + + nvEvoDestroyApiHandle(pNvKmsOpenDevSurfaceHandles, + surfaceHandle[eye]); + } + + if (cursorImage.surfaceHandle[NVKMS_LEFT] != 0) { + nvEvoDestroyApiHandle(pNvKmsOpenDevSurfaceHandles, + cursorImage.surfaceHandle[NVKMS_LEFT]); + } + } +} + + +/*! + * Wait for idle on a set of base channels. + * + * \param[in,out] pDevEvo The device. + * \param[in] idleChannelMaskPerSd The channel masks per subdevice that + * we should wait to be idle. + * \param[in] allowStopBase Whether we should stop base or just + * assert if the idle times out. + */ +static void HsConfigIdleBaseChannels( + NVDevEvoPtr pDevEvo, + const NVEvoChannelMask *idleChannelMaskPerSd, + NvBool allowStopBase) +{ + NvU64 startTime = 0; + NvBool allChannelsIdle = FALSE; + NVDispEvoPtr pDispEvo; + NvU32 dispIndex, head; + NVEvoChannelMask busyChannelMaskPerSd[NVKMS_MAX_SUBDEVICES] = { }; + + /* + * Wait up to 2 seconds for all channels to be idle, and gather a list of + * all busy channels. + */ + while (!allChannelsIdle) { + + const NvU32 timeout = 2000000; /* 2 seconds */ + NvBool anyChannelBusy = FALSE; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + for (head = 0; head < pDevEvo->numHeads; head++) { + NVEvoChannelPtr pMainLayerChannel = + pDevEvo->head[head].layer[NVKMS_MAIN_LAYER]; + if (idleChannelMaskPerSd[pDispEvo->displayOwner] & + pMainLayerChannel->channelMask) { + + NvBool isMethodPending = FALSE; + if (!pDevEvo->hal->IsChannelMethodPending( + pDevEvo, + pMainLayerChannel, + pDispEvo->displayOwner, + &isMethodPending) + || isMethodPending) { + + /* Mark this channel as busy. */ + busyChannelMaskPerSd[pDispEvo->displayOwner] |= + pMainLayerChannel->channelMask; + anyChannelBusy = TRUE; + } else { + /* + * Mark this channel as no longer busy, in case its + * flip completed while we were waiting on another + * channel. + */ + busyChannelMaskPerSd[pDispEvo->displayOwner] &= + ~pMainLayerChannel->channelMask; + } + } + } + } + + if (!anyChannelBusy) { + allChannelsIdle = TRUE; + break; + } + + /* Break out of the loop if we exceed the timeout. */ + if (nvExceedsTimeoutUSec(&startTime, timeout)) { + break; + } + + nvkms_yield(); + } + + if (!allChannelsIdle) { + /* + * At least one channel was still idle after the 2 second timeout + * above. + */ + if (!allowStopBase) { + /* + * The caller of this function expected this wait for idle not to + * time out. + */ + nvEvoLogDev(pDevEvo, EVO_LOG_WARN, + "Timeout while waiting for idle."); + } else { + /* + * Idle all base channels that were still busy when the wait above + * timed out. + */ + NVEvoIdleChannelState idleChannelState = { }; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + idleChannelState.subdev[pDispEvo->displayOwner].channelMask = + busyChannelMaskPerSd[pDispEvo->displayOwner]; + } + + pDevEvo->hal->ForceIdleSatelliteChannelIgnoreLock( + pDevEvo, &idleChannelState); + } + } +} + + +/*! + * Enable or disable fliplock on all channels using headsurface for swapgroups, + * waiting for idle if necessary. + */ +static void HsConfigUpdateFlipLockForSwapGroups(NVDevEvoPtr pDevEvo, + NvBool enable) +{ + NvU32 dispIndex, head; + NVDispEvoPtr pDispEvo; + NVEvoChannelMask flipLockToggleChannelMaskPerSd[NVKMS_MAX_SUBDEVICES] = { }; + + /* Determine which channels need to enable or disable fliplock. */ + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + + for (head = 0; head < pDevEvo->numHeads; head++) { + const NvU32 apiHead = nvHardwareHeadToApiHead(head); + NVHsChannelEvoPtr pHsChannel = pDispEvo->pHsChannel[apiHead]; + + if (pHsChannel == NULL) { + continue; + } + + NVEvoSubDevPtr pEvoSubDev = &pDevEvo->gpus[pDispEvo->displayOwner]; + NVEvoHeadControlPtr pHC = &pEvoSubDev->headControl[head]; + NVEvoChannelPtr pMainLayerChannel = + pDevEvo->head[head].layer[NVKMS_MAIN_LAYER]; + NvBool setFlipLock = FALSE; + + /* + * This function is called in two cases, when disabling fliplock for + * the pHsChannels in the previous config, and when enabling + * fliplock for the pHsChannels in the new config. In either case, + * if the old config wasn't using fliplock for swapgroups, or the + * new config won't be using fliplock for swapgroups, don't change + * the fliplock state here. + */ + if (!pHsChannel->config.neededForSwapGroup) { + continue; + } + + if (!enable && pHC->flipLock) { + /* + * This channel is currently using fliplock in the config that + * is being torn down; idle its base channel and disable + * fliplock. + */ + setFlipLock = TRUE; + } + + if (enable && ((pHC->serverLock != NV_EVO_NO_LOCK) || + (pHC->clientLock != NV_EVO_NO_LOCK))) { + /* + * This channel will be using fliplock for swap groups in the + * new config; idle its base channel and enable fliplock. + */ + + /* + * Override the prohibition of fliplock on pDispEvos with + * headsurface enabled (calculated earlier in + * HsConfigAllowFlipLock) to allow enabling fliplock for + * headSurface swapgroups. + */ + nvAllowFlipLockEvo(pDispEvo, TRUE /* allowFlipLock */); + + nvAssert(!HEAD_MASK_QUERY(pEvoSubDev->flipLockProhibitedHeadMask, + head)); + setFlipLock = TRUE; + } + + if (!setFlipLock) { + continue; + } + + flipLockToggleChannelMaskPerSd[pDispEvo->displayOwner] |= + pMainLayerChannel->channelMask; + } + } + + /* + * Wait for all base channels that are enabling/disabling fliplock to be + * idle. This shouldn't timeout if we're enabling fliplock while bringing + * up swapgroups on a new head. + */ + HsConfigIdleBaseChannels(pDevEvo, + flipLockToggleChannelMaskPerSd, + !enable /* allowStopBase */); + + /* Now that all channels are idle, update fliplock. */ + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + NVEvoUpdateState updateState = { }; + + if (!flipLockToggleChannelMaskPerSd[pDispEvo->displayOwner]) { + continue; + } + + for (head = 0; head < pDevEvo->numHeads; head++) { + NVEvoChannelPtr pMainLayerChannel = + pDevEvo->head[head].layer[NVKMS_MAIN_LAYER]; + if (flipLockToggleChannelMaskPerSd[pDispEvo->displayOwner] & + pMainLayerChannel->channelMask) { + + NvU32 setEnable = enable; + + if (!nvUpdateFlipLockEvoOneHead(pDispEvo, head, &setEnable, + TRUE /* set */, + NULL /* needsEarlyUpdate */, + &updateState)) { + nvEvoLogDev(pDevEvo, EVO_LOG_WARN, + "Failed to toggle fliplock for swapgroups."); + } + } + } + + nvEvoUpdateAndKickOff(pDispEvo, TRUE, &updateState, + TRUE /* releaseElv */); + } +} + +/*! + * Tear down all existing headSurface configs on the device, disabling + * fliplock, flipping base to NULL, restoring core surfaces, and releasing + * swapgroups if necessary. + * + * This function is not allowed to fail: it is called after we have committed to + * performing the modeset. + * + * \param[in,out] pDevEvo The device. + * \param[in] pHsConfig The NVHsConfig that will be applied later in this + * transition; this is used to decide whether to + * restore the non-headSurface surface when leaving + * a SwapGroup. + */ +void nvHsConfigStop( + NVDevEvoPtr pDevEvo, + const NVHsConfig *pHsConfig) +{ + NvU32 dispIndex, apiHead; + NVDispEvoPtr pDispEvo; + NVHsDeviceEvoPtr pHsDevice = pDevEvo->pHsDevice; + NVEvoChannelMask hsDisableChannelMaskPerSd[NVKMS_MAX_SUBDEVICES] = { }; + + /* + * We should only get here if this configuration is going to be committed. + */ + nvAssert(pHsConfig->commit); + + /* + * If fliplock was in use for headsurface swapgroups on any channel, wait + * for those channels to be idle, applying accelerators to ignore + * fliplock/interlock if necessary, and disable fliplock on those channels. + */ + HsConfigUpdateFlipLockForSwapGroups(pDevEvo, FALSE /* enable */); + + /* Flip all headSurface heads to NULL. */ + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + NvU32 head; + for (head = 0; head < pDevEvo->numHeads; head++) { + const NvU32 apiHead = nvHardwareHeadToApiHead(head); + NVHsChannelEvoPtr pHsChannel = pDispEvo->pHsChannel[apiHead]; + + if (pHsChannel != NULL) { + NVEvoChannelPtr pMainLayerChannel = + pDevEvo->head[head].layer[NVKMS_MAIN_LAYER]; + hsDisableChannelMaskPerSd[pDispEvo->displayOwner] |= + pMainLayerChannel->channelMask; + + if (pHsChannel->config.pixelShift == NVKMS_PIXEL_SHIFT_8K) { + nvSetStereoEvo(pDispEvo, head, FALSE); + } + + if (pHsChannel->config.neededForSwapGroup) { + pHsChannel->viewportFlipPending = FALSE; + nvHsRemoveRgLine1Callback(pHsChannel); + } + + nvHsRemoveVBlankCallback(pHsChannel); + nvHsFlip(pHsDevice, + pHsChannel, + 0 /* eyeMask: ignored when disabling */, + FALSE /* perEyeStereoFlip: ignored when disabling */, + 0 /* index: ignored when disabling */, + NULL /* NULL == disable */, + FALSE /* isFirstFlip */, + FALSE /* allowFlipLock */); + } + } + } + + /* + * Wait for base to be idle on all channels that previously had headSurface + * enabled in order to allow semaphore releases from previous headSurface + * flips to complete. This wait should not timeout, so if it does, just + * assert instead of forcing the channels idle. + */ + HsConfigIdleBaseChannels(pDevEvo, + hsDisableChannelMaskPerSd, + FALSE /* allowStopBase */); + + /* Update bookkeeping and restore the original surface in main layer. */ + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + NVHsChannelEvoPtr pHsChannel = pDispEvo->pHsChannel[apiHead]; + + if (pHsChannel != NULL) { + nvHsFreeStatistics(pHsChannel); + nvHsDrainFlipQueue(pHsChannel); + + HsConfigRestoreMainLayerSurface( + pDispEvo, + pHsChannel, + &pHsConfig->apiHead[dispIndex][apiHead].channelConfig); + } + } + } + + /* + * At this point any active swapgroups with pending flips have completed + * those flips (by force if necessary) and flipped back to core, so release + * any deferred request fifos that are waiting for that pending flip to + * complete. + */ + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + NVSwapGroupRec *pSwapGroup = pDispEvo->pSwapGroup[apiHead]; + if ((pSwapGroup != NULL) && + pSwapGroup->pendingFlip) { + nvHsSwapGroupRelease(pDevEvo, pSwapGroup); + } + } + } + + /* finally, make sure any remaining rendering commands have landed */ + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + NVHsChannelEvoPtr pHsChannel = pDispEvo->pHsChannel[apiHead]; + if (pHsChannel != NULL) { + nvPushIdleChannel(&pHsChannel->nvPush.channel); + } + } + } +} + +/*! + * Apply the new NVHsConfig to the device. + * + * As resources are propagated from pHsConfig to pDevEvo, remove them from + * pHsConfig, so that nvHsConfigFreeResources() can safely be called on the + * pHsConfig. + * + * This function is not allowed to fail: it is called after we have committed to + * performing the modeset. + * + * \param[in,out] pDevEvo The device. + * \param[in,out] pHsConfig The NVHsConfig to apply. + */ +void nvHsConfigStart( + NVDevEvoPtr pDevEvo, + NVHsConfig *pHsConfig) +{ + NvU32 dispIndex, head; + NVDispEvoPtr pDispEvo; + NVHsDeviceEvoPtr pHsDevice = pDevEvo->pHsDevice; + NvBool allowFlipLock; + + /* + * We should only get here if this configuration is going to be committed. + */ + nvAssert(pHsConfig->commit); + + /* Update channels. */ + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + + for (head = 0; head < pDevEvo->numHeads; head++) { + const NvU32 apiHead = nvHardwareHeadToApiHead(head); + NVHsConfigOneHead *pHsConfigOneHead = + &pHsConfig->apiHead[dispIndex][apiHead]; + + /* + * If we have a new configuration, increment its surface reference + * counts. + */ + if (pHsConfigOneHead->pHsChannel != NULL) { + HsConfigUpdateSurfaceRefCount( + &pHsConfigOneHead->channelConfig, + TRUE /* increase */); + } + + /* + * If we have an old configuration, decrement its surface reference + * counts. + */ + if (pDispEvo->pHsChannel[apiHead] != NULL) { + HsConfigUpdateSurfaceRefCount( + &pDispEvo->pHsChannel[apiHead]->config, + FALSE /* increase */); + } + + /* If there is no channel before or after, continue. */ + + if ((pDispEvo->pHsChannel[apiHead] == NULL) && + (pHsConfigOneHead->pHsChannel == NULL)) { + continue; + } + + /* If the channel is used before and after, continue. */ + + if ((pDispEvo->pHsChannel[apiHead] != NULL) && + (pHsConfigOneHead->pHsChannel != NULL)) { + nvAssert(pHsConfigOneHead->channelReused); + nvAssert(pDispEvo->pHsChannel[apiHead] == + pHsConfigOneHead->pHsChannel); + continue; + } + + /* Free any channels no longer needed. */ + + if ((pDispEvo->pHsChannel[apiHead] != NULL) && + (pHsConfigOneHead->pHsChannel == NULL)) { + nvHsFreeChannel(pDispEvo->pHsChannel[apiHead]); + pDispEvo->pHsChannel[apiHead] = NULL; + continue; + } + + /* + * Otherwise, propagate the channel configuration from pHsConfig to + * pDispEvo. + */ + nvAssert(pDispEvo->pHsChannel[apiHead] == NULL); + pDispEvo->pHsChannel[apiHead] = pHsConfigOneHead->pHsChannel; + pHsConfigOneHead->pHsChannel = NULL; + } + } + + /* Update surfaces. */ + + for (head = 0; head < pDevEvo->numHeads; head++) { + + const NvU32 apiHead = nvHardwareHeadToApiHead(head); + NVHsStateOneHeadAllDisps *pDevEvoHsConfig = + &pDevEvo->apiHeadSurfaceAllDisps[apiHead]; + NVHsStateOneHeadAllDisps *pHsOneHeadAllDisps = + &pHsConfig->apiHeadAllDisps[apiHead]; + + /* + * If the device is currently using headSurface on this head, but the + * new configuration is not, free the surfaces. + */ + if ((pDevEvoHsConfig->surfaceCount > 0) && + (pHsOneHeadAllDisps->surfaceCount == 0)) { + + HsConfigFreeHeadSurfaceSurfaces(pDevEvo, pDevEvoHsConfig, FALSE); + continue; + } + + /* + * If the device is currently not using headSurface on this head, but + * the new configuration is, propagate resources. + */ + if ((pDevEvoHsConfig->surfaceCount == 0) && + (pHsOneHeadAllDisps->surfaceCount > 0)) { + + MoveHsStateOneHeadAllDisps(pDevEvoHsConfig, pHsOneHeadAllDisps); + continue; + } + + /* + * If the device is currently using headSurface on this head, and the + * new configuration also is, reconcile the two. + */ + if ((pDevEvoHsConfig->surfaceCount > 0) && + (pHsOneHeadAllDisps->surfaceCount > 0)) { + + /* + * If the new configuration is reusing the device's surfaces, then + * this head is done. + */ + if (pHsConfig->surfacesReused[apiHead]) { + nvAssert(nvkms_memcmp(pDevEvoHsConfig, pHsOneHeadAllDisps, + sizeof(*pDevEvoHsConfig)) == 0); + continue; + } + + /* + * Otherwise, the new configuration had to allocate new surfaces. + * Free the old surfaces and replace them. + */ + HsConfigFreeHeadSurfaceSurfaces(pDevEvo, pDevEvoHsConfig, FALSE); + + MoveHsStateOneHeadAllDisps(pDevEvoHsConfig, pHsOneHeadAllDisps); + } + } + + /* + * Update the flip lock prohibit/allow state, based on whether heads will + * have headSurface enabled in the new configuration. This will allow + * headSurface flips to proceed independently of non-headSurface flips + * on configurations that would otherwise implicitly enable fliplock + * in FinishModesetOneTopology, which should allow the first flip to + * complete below. After that, fliplock may be enabled again for + * headSurface swapgroups if necessary. + */ + + allowFlipLock = HsConfigAllowFlipLock(pDevEvo); + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + nvAllowFlipLockEvo(pDispEvo, allowFlipLock); + } + + /* Enable headSurface for the new configuration. */ + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + + for (head = 0; head < pDevEvo->numHeads; head++) { + const NvU32 apiHead = nvHardwareHeadToApiHead(head); + NVHsChannelEvoPtr pHsChannel = pDispEvo->pHsChannel[apiHead]; + const NVHsConfigOneHead *pHsConfigOneHead = + &pHsConfig->apiHead[dispIndex][apiHead]; + + if (pHsChannel != NULL) { + + nvHsAddVBlankCallback(pHsChannel); + + nvHsAllocStatistics(pHsChannel); + + /* Apply the new configuration to pHsChannel. */ + + pHsChannel->config = pHsConfigOneHead->channelConfig; + + if (pHsChannel->config.neededForSwapGroup) { + nvHsAddRgLine1Callback(pHsChannel); + } + + /* + * nvHsConfigPatchSetModeRequest() used + * surfaces[eye][nextIndex].pSurface as the surface during + * modeset. Now that we know that the modeset succeeded, + * increment nextIndex. + */ + HsIncrementNextIndex(pHsDevice, pHsChannel); + + /* + * Reset nextOffset: non-SwapGroup configurations rely on + * nextOffset being 0 to avoid rendering and flipping to an + * invalid configuration within a headSurface surface, and + * SwapGroup configurations rely on nextOffset being 0 to avoid + * the combination of HsIncrementNextOffset below and the + * first flip to offset 0 in HsFlipHelper resulting in the + * active offset and next offset both being 0, which would cause + * a hang in HsServiceRGLineInterrupt. + */ + pHsChannel->nextOffset = 0; + + if (pHsChannel->config.neededForSwapGroup) { + HsIncrementNextOffset(pHsDevice, pHsChannel); + } + + /* Do the one-time set up of the channel. */ + + nvHs3dSetConfig(pHsChannel); + + /* Render the first frame. */ + + nvHsInitNotifiers(pHsDevice, pHsChannel); + HsConfigInitFlipQueue(pHsChannel, pHsConfigOneHead); + nvHsNextFrame(pHsDevice, pHsChannel, + NV_HS_NEXT_FRAME_REQUEST_TYPE_FIRST_FRAME); + + if (pHsChannel->config.pixelShift == NVKMS_PIXEL_SHIFT_8K) { + nvSetStereoEvo(pDispEvo, head, TRUE); + } + } + } + } + + /* + * If fliplock is necessary for headsurface swapgroups on any channel, + * wait for idle (which shouldn't timeout since fliplock was disabled + * above) and enable fliplock on those channels. + */ + HsConfigUpdateFlipLockForSwapGroups(pDevEvo, TRUE /* enable */); +} + +static void HsConfigPatchRequestedViewPortOneHead( + const NVDispEvoRec *pDispEvo, + struct NvKmsSetModeOneHeadRequest *pRequestHead, + const NVHsConfigOneHead *pHsConfigOneHead) +{ + const NVHsChannelConfig *pChannelConfig = &pHsConfigOneHead->channelConfig; + + nvAssert(StateNeedsHeadSurface(pChannelConfig->state)); + + /* + * Patch ViewPortIn: whenever using headSurface, the display + * hardware's ViewPortIn is the size of the headSurface frame. + */ + pRequestHead->viewPortSizeIn.width = pChannelConfig->frameSize.width; + pRequestHead->viewPortSizeIn.height = pChannelConfig->frameSize.height; + + /* + * Patch ViewPortOut: if PARTIAL, then headSurface uses the display hardware + * to do ViewPortIn => ViewPortOut scaling. In that case, we keep the + * client-requested ViewPortOut (i.e., change nothing here). But, if FULL, + * then we program the display hardware with a ViewPortOut the size of the + * visible region of the mode: the surface, ViewPortIn, ViewPortOut, and + * visible region are all the same size. + */ + if (pChannelConfig->state == + NVKMS_HEAD_SURFACE_CONFIG_STATE_FULL_HEAD_SURFACE) { + /* + * If ViewPortOut is not specified in the request, then the ViewPortOut + * will be programmed with the same size as the visible region of + * the mode. + */ + nvkms_memset(&pRequestHead->viewPortOut, + 0, sizeof(pRequestHead->viewPortOut)); + pRequestHead->viewPortOutSpecified = FALSE; + } +} + + +/*! + * Modify the NvKmsSetModeRequest with the desired NVHsConfig. + * + * After calling this function, a modeset will be attempted. If that modeset + * fails, then the previous NvKmsSetModeRequest will be restored, and the + * NVHsConfig will be downgraded, and the process will be tried again. + * + * This function is a noop if pHsConfig does not enable headSurface for any + * heads. + * + * \param[in] pDevEvo The device + * \param[in] pHsConfig The NVHsConfigRec to apply to pRequest. + * \param[in,out] pOpenDev The per-open device data for the modeset client. + * \param[in,out] pRequest The modeset request to be modified. + * \param[out] patchedApiHeadsMask[] The per sub-device mask of the api + * heads which are patched by this + * function. + * + * \return TRUE if pRequest could be modified as necessary. + * FALSE if an error occurred and the modeset should be aborted. + * The patchedApiHeadsMask[] output parameter is used by + * nvHsConfigClearPatchedSetModeReq() to free resources like + * surface handles before clearing the input modeset + * request. + */ +NvBool nvHsConfigPatchSetModeRequest(const NVDevEvoRec *pDevEvo, + const NVHsConfig *pHsConfig, + struct NvKmsPerOpenDev *pOpenDev, + struct NvKmsSetModeRequest *pRequest, + NvU32 patchedApiHeadsMask[NVKMS_MAX_SUBDEVICES]) +{ + NvU32 ret = TRUE; + NvU32 apiHead, sd, eye; + NVDispEvoPtr pDispEvo; + NVEvoApiHandlesRec *pOpenDevSurfaceHandles = + nvGetSurfaceHandlesFromOpenDev(pOpenDev); + + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + struct NvKmsSetModeOneDispRequest *pRequestDisp = + &pRequest->disp[sd]; + + patchedApiHeadsMask[sd] = 0x0; + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + const NVHsConfigOneHead *pHsConfigOneHead = + &pHsConfig->apiHead[sd][apiHead]; + const NVHsChannelConfig *pChannelConfig = + &pHsConfigOneHead->channelConfig; + + const NVHsChannelEvoRec *pHsChannel = pHsConfigOneHead->pHsChannel; + + struct NvKmsSetModeOneHeadRequest *pRequestHead = + &pRequestDisp->head[apiHead]; + + NvU32 layer; + + if (!HsConfigHeadRequested(pRequest, sd, apiHead)) { + continue; + } + + if (!StateNeedsHeadSurface(pChannelConfig->state)) { + continue; + } + + /* If this is a commit-ful modeset, we should have a channel. */ + if (pHsConfig->commit) { + nvAssert(pHsChannel != NULL); + } + + patchedApiHeadsMask[sd] |= NVBIT(apiHead); + + /* + * XXX NVKMS HEADSURFACE TODO: update the cursor configuration as + * necessary. + */ + + /* + * Construct a new NvKmsFlipCommonParams request reflecting + * pHsConfig. This is per-disp. + */ + nvkms_memset(&pRequestHead->flip, 0, sizeof(pRequestHead->flip)); + + pRequestHead->flip.viewPortIn.specified = TRUE; + pRequestHead->flip.viewPortIn.point.x = 0; + pRequestHead->flip.viewPortIn.point.y = 0; + + pRequestHead->flip.cursor.imageSpecified = TRUE; + pRequestHead->flip.cursor.positionSpecified = TRUE; + + for (layer = 0; layer < pDevEvo->apiHead[apiHead].numLayers; layer++) { + pRequestHead->flip.layer[layer].surface.specified = TRUE; + pRequestHead->flip.layer[layer].completionNotifier.specified = TRUE; + pRequestHead->flip.layer[layer].syncObjects.specified = TRUE; + pRequestHead->flip.layer[layer].compositionParams.specified = TRUE; + + if (layer != NVKMS_MAIN_LAYER) { + continue; + } + + pRequestHead->flip.layer[layer].csc.specified = TRUE; + pRequestHead->flip.layer[layer].csc.matrix = NVKMS_IDENTITY_CSC_MATRIX; + + for (eye = NVKMS_LEFT; eye < NVKMS_MAX_EYES; eye++) { + if ((NVBIT(eye) & pChannelConfig->eyeMask) == 0) { + continue; + } + + /* If this is a commit-ful modeset, we should have a surface. */ + if (pHsConfig->commit) { + NVHsSurfaceRec *pHsSurface = + pHsConfig->apiHeadAllDisps[apiHead]. + surfaces[eye][pHsChannel->nextIndex].pSurface; + nvAssert(pHsSurface != NULL); + + NVSurfaceEvoRec *pSurfaceEvo = + nvHsGetNvKmsSurface(pDevEvo, + pHsSurface->nvKmsHandle, + TRUE /* requireCtxDma */); + nvAssert(pSurfaceEvo != NULL); + + pRequestHead->flip.layer[layer].surface.handle[eye] = + nvEvoCreateApiHandle(pOpenDevSurfaceHandles, + pSurfaceEvo); + if (pRequestHead->flip.layer[layer].surface.handle[eye] != 0x0) { + nvEvoIncrementSurfaceStructRefCnt(pSurfaceEvo); + } else { + ret = FALSE; + } + } else { + pRequestHead->flip.layer[layer].surface.handle[eye] = 0; + } + } + + if (pRequestHead->flip.layer[layer].surface.handle[NVKMS_LEFT] != 0) { + const NVHsSurfaceRec *pHsSurface = + pHsConfig->apiHeadAllDisps[apiHead]. + surfaces[NVKMS_LEFT][pHsChannel->nextIndex].pSurface; + + pRequestHead->flip.layer[layer].sizeIn.specified = TRUE; + pRequestHead->flip.layer[layer].sizeIn.val.width = + pHsSurface->pSurfaceEvo->widthInPixels; + pRequestHead->flip.layer[layer].sizeIn.val.height = + pHsSurface->pSurfaceEvo->heightInPixels; + + pRequestHead->flip.layer[layer].sizeOut.specified = TRUE; + pRequestHead->flip.layer[layer].sizeOut.val = + pRequestHead->flip.layer[layer].sizeIn.val; + } + } + + HsConfigPatchRequestedViewPortOneHead(pDispEvo, pRequestHead, + pHsConfigOneHead); + } + } + + return ret; +} + +void +nvHsConfigClearPatchedSetModeRequest(const NVDevEvoRec *pDevEvo, + struct NvKmsPerOpenDev *pOpenDev, + struct NvKmsSetModeRequest *pRequest, + const NvU32 patchedApiHeadsMask[NVKMS_MAX_SUBDEVICES]) +{ + NvU32 sd; + NVDispEvoPtr pDispEvo; + NVEvoApiHandlesRec *pOpenDevSurfaceHandles = + nvGetSurfaceHandlesFromOpenDev(pOpenDev); + + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + NvU32 apiHead; + struct NvKmsSetModeOneDispRequest *pRequestDisp = + &pRequest->disp[sd]; + + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + struct NvKmsSetModeOneHeadRequest *pRequestHead = + &pRequestDisp->head[apiHead]; + NvU32 eye; + + if ((NVBIT(apiHead) & patchedApiHeadsMask[sd]) == 0x0) { + continue; + } + + + for (eye = NVKMS_LEFT; eye < NVKMS_MAX_EYES; eye++) { + const NvKmsSurfaceHandle surfaceHandle = + pRequestHead->flip.layer[NVKMS_MAIN_LAYER].surface.handle[eye]; + + if (surfaceHandle != 0x0) { + NVSurfaceEvoPtr pSurfaceEvo = + nvEvoGetPointerFromApiHandle(pOpenDevSurfaceHandles, + surfaceHandle); + nvEvoDestroyApiHandle(pOpenDevSurfaceHandles, surfaceHandle); + nvEvoDecrementSurfaceStructRefCnt(pSurfaceEvo); + } + } + } + } + + nvkms_memset(pRequest, 0, sizeof(*pRequest)); +} diff --git a/src/nvidia-modeset/src/nvkms-headsurface-ioctl.c b/src/nvidia-modeset/src/nvkms-headsurface-ioctl.c new file mode 100644 index 000000000..b6a65243b --- /dev/null +++ b/src/nvidia-modeset/src/nvkms-headsurface-ioctl.c @@ -0,0 +1,623 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvkms-types.h" +#include "nvkms-headsurface.h" +#include "nvkms-headsurface-ioctl.h" +#include "nvkms-headsurface-priv.h" +#include "nvkms-cursor.h" +#include "nvkms-utils.h" +#include "nvkms-flip.h" + +/* + * This source file contains functions that intercept portions of the NVKMS API. + * + * If the API request changes headSurface state, we update headSurface + * accordingly. If the API request does not touch headSurface-ful heads, we + * "call down" to the normal NVKMS implementation. + * + * Note that some NVKMS requests can touch multiple heads at once, where a + * subset of the heads are driven by headSurface. In those cases, we: + * + * - Identify if all requested heads are headSurface-less; if so, call down and + * return. + * + * - Validate the request for the headSurface-ful heads. + * + * - If there are both headSurface-less *and* headSurface-ful heads in the + * request, build a temporary request structure with the headSurface-ful heads + * removed. Call down with that temporary structure. + * + * - Apply the request to the headSurface-ful heads. + */ + +/*! + * Assign headSurface bitmasks. + * + * Given requestedHeadsBitMask and a disp, assign a head bitmasks of the + * headSurface-ful heads and headSurface-less heads. + * + * Fail if requestedHeadsBitMask contains invalid heads. + */ +static NvBool HsIoctlGetBitMasks( + const NVDispEvoRec *pDispEvo, + const NvU32 requestedHeadsBitMask, + NvU32 *pHsMask, + NvU32 *pNonHsMask) +{ + NvU32 hsMask = 0; + NvU32 nonHsMask = 0; + NvU32 head; + + if (nvHasBitAboveMax(requestedHeadsBitMask, pDispEvo->pDevEvo->numHeads)) { + return FALSE; + } + + FOR_EACH_INDEX_IN_MASK(32, head, requestedHeadsBitMask) { + const NvU32 apiHead = nvHardwareHeadToApiHead(head); + if (pDispEvo->pHsChannel[apiHead] == NULL) { + nonHsMask |= NVBIT(head); + } else { + hsMask |= NVBIT(head); + } + + } FOR_EACH_INDEX_IN_MASK_END; + + /* + * Each bit from the original mask should be in exactly one of hsMask or + * nonHsMask. + */ + nvAssert((hsMask | nonHsMask) == requestedHeadsBitMask); + nvAssert((hsMask & nonHsMask) == 0); + + *pHsMask = hsMask; + *pNonHsMask = nonHsMask; + + return TRUE; +} + +/*! + * Validate the NvKmsMoveCursorCommonParams for headSurface. + */ +static NvBool HsIoctlValidateMoveCursor( + const NVHsChannelEvoRec *pHsChannel, + const struct NvKmsMoveCursorCommonParams *pParams) +{ + /* XXX NVKMS HEADSURFACE TODO: validate x,y against headSurface config */ + + return TRUE; +} + +/*! + * Apply x,y to headSurface. + * + * This configuration should first be validated by HsIoctlValidateMoveCursor(). + * We cannot fail from here. + */ +static void HsIoctlMoveCursor( + NVHsChannelEvoRec *pHsChannel, + const NvS16 x, const NvS16 y) +{ + pHsChannel->config.cursor.x = x; + pHsChannel->config.cursor.y = y; + + /* + * XXX NVKMS HEADSURFACE TODO: record that this head is dirty, so + * headSurface knows it needs to rerender the frame. + */ +} + +/*! + * Update headSurface for NVKMS_IOCTL_MOVE_CURSOR. + */ +NvBool nvHsIoctlMoveCursor( + NVDispEvoPtr pDispEvo, + NvU32 head, + const struct NvKmsMoveCursorCommonParams *pParams) +{ + const NvU32 apiHead = nvHardwareHeadToApiHead(head); + NVHsChannelEvoRec *pHsChannel; + + if (apiHead > ARRAY_LEN(pDispEvo->pHsChannel)) { + return FALSE; + } + + pHsChannel = pDispEvo->pHsChannel[apiHead]; + + /* If headSurface is not used on this head, call down. */ + + if (pHsChannel == NULL) { + nvEvoMoveCursor(pDispEvo, head, pParams); + return TRUE; + } + + if (!HsIoctlValidateMoveCursor(pHsChannel, pParams)) { + return FALSE; + } + + HsIoctlMoveCursor(pHsChannel, pParams->x, pParams->y); + + return TRUE; +} + +/*! + * Validate the NvKmsSetCursorImageCommonParams for headSurface. + * + * If successfully validated, also assign ppSurfaceEvo. + */ +static NvBool HsIoctlValidateSetCursorImage( + const NVHsChannelEvoRec *pHsChannel, + const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, + const struct NvKmsSetCursorImageCommonParams *pParams, + NVSurfaceEvoRec **ppSurfaceEvo) +{ + NVSurfaceEvoPtr pSurfaceEvos[NVKMS_MAX_EYES]; + + if (!nvGetCursorImageSurfaces(pHsChannel->pDispEvo->pDevEvo, + pOpenDevSurfaceHandles, + pParams, + pSurfaceEvos)) { + return FALSE; + } + + /* XXX NVKMS HEADSURFACE TODO: make cursor stereo-aware. */ + + *ppSurfaceEvo = pSurfaceEvos[NVKMS_LEFT]; + + return TRUE; +} + +/*! + * Apply the cursor pSurfaceEvo to headSurface. + * + * This configuration should first be validated by + * HsIoctlValidateSetCursorImage(). We cannot fail from here. + */ +static void HsIoctlSetCursorImage( + NVHsChannelEvoRec *pHsChannel, + NVSurfaceEvoRec *pSurfaceEvo) +{ + /* + * Increment the refcnt of the new surface, and + * decrement the refcnt of the old surface. + * + * XXX NVKMS HEADSURFACE TODO: wait until graphics channel is done using old + * surface before decrementing its refcnt? + */ + + HsChangeSurfaceFlipRefCount( + pSurfaceEvo, TRUE /* increase */); + + HsChangeSurfaceFlipRefCount( + pHsChannel->config.cursor.pSurfaceEvo, FALSE /* increase */); + + pHsChannel->config.cursor.pSurfaceEvo = pSurfaceEvo; + + /* + * XXX NVKMS HEADSURFACE TODO: record that this head is dirty, so + * headSurface knows it needs to rerender the frame. + */ +} + +/*! + * Update headSurface for NVKMS_IOCTL_SET_CURSOR_IMAGE. + */ +NvBool nvHsIoctlSetCursorImage( + NVDispEvoPtr pDispEvo, + const struct NvKmsPerOpenDev *pOpenDevice, + const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, + NvU32 head, + const struct NvKmsSetCursorImageCommonParams *pParams) +{ + const NvU32 apiHead = nvHardwareHeadToApiHead(head); + NVHsChannelEvoRec *pHsChannel; + NVSurfaceEvoRec *pSurfaceEvo = NULL; + + if (apiHead > ARRAY_LEN(pDispEvo->pHsChannel)) { + return FALSE; + } + + pHsChannel = pDispEvo->pHsChannel[apiHead]; + + /* If headSurface is not used on this head, call down. */ + + if (pHsChannel == NULL) { + return nvSetCursorImage(pDispEvo, + pOpenDevice, + pOpenDevSurfaceHandles, + head, + pParams); + } + + if (!HsIoctlValidateSetCursorImage(pHsChannel, + pOpenDevSurfaceHandles, + pParams, + &pSurfaceEvo)) { + return FALSE; + } + + HsIoctlSetCursorImage(pHsChannel, pSurfaceEvo); + + return TRUE; +} + +/*! + * Apply NvKmsPoint to headSurface. + */ +static void HsIoctlPan( + NVHsChannelEvoRec *pHsChannel, + const struct NvKmsPoint *pViewPortPointIn) +{ + pHsChannel->config.viewPortIn.x = pViewPortPointIn->x; + pHsChannel->config.viewPortIn.y = pViewPortPointIn->y; + + /* + * XXX NVKMS HEADSURFACE TODO: record that this head is dirty, so + * headSurface knows it needs to rerender the frame. + */ +} + +/*! + * Create a copy of NvKmsFlipRequest with the headSurface-ful heads removed. + */ +static struct NvKmsFlipRequest *HsIoctlRemoveHsHeadsFromNvKmsFlipRequest( + NVDevEvoPtr pDevEvo, + const struct NvKmsFlipRequest *pRequestOriginal, + const NvU32 hsMask[NVKMS_MAX_SUBDEVICES]) +{ + NVDispEvoPtr pDispEvo; + NvU32 head, sd; + + struct NvKmsFlipRequest *pRequest = nvAlloc(sizeof(*pRequest)); + + if (pRequest == NULL) { + return FALSE; + } + + *pRequest = *pRequestOriginal; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + FOR_EACH_INDEX_IN_MASK(32, head, hsMask[sd]) { + + nvkms_memset(&pRequest->sd[sd].head[head], 0, + sizeof(pRequest->sd[sd].head[head])); + + pRequest->sd[sd].requestedHeadsBitMask &= ~NVBIT(head); + + } FOR_EACH_INDEX_IN_MASK_END; + } + + return pRequest; +} + +static void HsIoctlAssignSurfacesMaxEyes( + NVSurfaceEvoPtr pSurfaceEvoDst[], + NVSurfaceEvoRec *const pSurfaceEvoSrc[]) +{ + NvU8 eye; + + for (eye = NVKMS_LEFT; eye < NVKMS_MAX_EYES; eye++) { + pSurfaceEvoDst[eye] = pSurfaceEvoSrc[eye]; + } +} + +static NvBool HsIoctlFlipValidateOneHwState( + const NVFlipChannelEvoHwState *pHwState, + const NvU32 sd) +{ + /* HeadSurface does not support completion notifiers, yet. */ + + if ((pHwState->completionNotifier.surface.pSurfaceEvo != NULL) || + (pHwState->completionNotifier.awaken)) { + return FALSE; + } + + /* The semaphore surface must have a CPU mapping. */ + + if (!pHwState->syncObject.usingSyncpt) { + if (pHwState->syncObject.u.semaphores.acquireSurface.pSurfaceEvo != NULL) { + if (pHwState->syncObject.u.semaphores.acquireSurface.pSurfaceEvo->cpuAddress[sd] == NULL) { + return FALSE; + } + } + + if (pHwState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo != NULL) { + if (pHwState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo->cpuAddress[sd] == NULL) { + return FALSE; + } + } + } + + /* HeadSurface does not support timeStamp flips, yet. */ + + if (pHwState->timeStamp != 0) { + return FALSE; + } + + return TRUE; +} + +/*! + * Assign NVFlipEvoHwState. + * + * Return TRUE if the NVFlipEvoHwState could be assigned and is valid for use by + * headSurface. + */ +static NvBool HsIoctlFlipAssignHwStateOneHead( + NVHsChannelEvoRec *pHsChannel, + NVDevEvoPtr pDevEvo, + const NvU32 sd, + const NvU32 head, + const struct NvKmsPerOpenDev *pOpenDev, + const struct NvKmsFlipCommonParams *pRequestOneHead, + NVFlipEvoHwState *pFlipState) +{ + NvU32 layer; + const struct NvKmsUsageBounds *pPossibleUsage = + &pDevEvo->gpus[sd].pDispEvo->headState[head].timings.viewPort.possibleUsage; + + nvAssert(pHsChannel != NULL); + + /* Init pFlipState using current pHsChannel state. */ + + nvClearFlipEvoHwState(pFlipState); + + pFlipState->cursor = pHsChannel->config.cursor; + + pFlipState->viewPortPointIn.x = pHsChannel->config.viewPortIn.x; + pFlipState->viewPortPointIn.y = pHsChannel->config.viewPortIn.y; + + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + pFlipState->layer[layer] = *HsGetLastFlipQueueEntry(pHsChannel, layer); + } + + /* Apply pRequestOneHead to pFlipState. */ + + if (!nvUpdateFlipEvoHwState(pOpenDev, pDevEvo, sd, head, pRequestOneHead, + pFlipState, FALSE /* allowVrr */)) { + return FALSE; + } + + nvOverrideScalingUsageBounds(pDevEvo, head, pFlipState, pPossibleUsage); + + /* Validate that the requested changes can be performed by headSurface. */ + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + if (!pFlipState->dirty.layer[layer]) { + continue; + } + + if (!HsIoctlFlipValidateOneHwState(&pFlipState->layer[layer], sd)) { + return FALSE; + } + } + + return TRUE; +} + +/*! + * Update headSurface for NVKMS_IOCTL_FLIP. + * + * XXX NVKMS HEADSURFACE TODO: handle/validate the rest of the flip request + * structure. + */ +NvBool nvHsIoctlFlip( + NVDevEvoPtr pDevEvo, + const struct NvKmsPerOpenDev *pOpenDev, + const struct NvKmsFlipRequest *pRequest, + struct NvKmsFlipReply *pReply) +{ + NvU32 head, sd; + NVDispEvoPtr pDispEvo; + NvU32 nHsHeads = 0; + NvU32 nNonHsHeads = 0; + NvBool ret = FALSE; + + struct { + NvU32 hsMask[NVKMS_MAX_SUBDEVICES]; + NvU32 nonHsMask[NVKMS_MAX_SUBDEVICES]; + + NVFlipEvoHwState flipState + [NVKMS_MAX_SUBDEVICES][NVKMS_MAX_HEADS_PER_DISP]; + + } *pWorkArea = nvCalloc(1, sizeof(*pWorkArea)); + + if (pWorkArea == NULL) { + goto done; + } + + /* Take inventory of which heads are touched by the request. */ + + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + + if (!HsIoctlGetBitMasks(pDispEvo, + pRequest->sd[sd].requestedHeadsBitMask, + &pWorkArea->hsMask[sd], + &pWorkArea->nonHsMask[sd])) { + goto done; + } + + nHsHeads += nvPopCount32(pWorkArea->hsMask[sd]); + nNonHsHeads += nvPopCount32(pWorkArea->nonHsMask[sd]); + } + + /* + * Handle the common case: if there are no headSurface-ful heads touched by + * the request, call down and return. + */ + if (nHsHeads == 0) { + ret = nvFlipEvo(pDevEvo, + pOpenDev, + pRequest, + pReply, + FALSE /* skipUpdate */, + TRUE /* allowFlipLock */); + goto done; + } + + /* + * Assign and validate flipState for any headSurface heads in the + * request. + */ + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + FOR_EACH_INDEX_IN_MASK(32, head, pWorkArea->hsMask[sd]) { + const NvU32 apiHead = nvHardwareHeadToApiHead(head); + if (!HsIoctlFlipAssignHwStateOneHead( + pDispEvo->pHsChannel[apiHead], + pDevEvo, + sd, + head, + pOpenDev, + &pRequest->sd[sd].head[head], + &pWorkArea->flipState[sd][head])) { + goto done; + } + + } FOR_EACH_INDEX_IN_MASK_END; + } + + /* + * If we got this far, we know there are headSurface-ful heads. If there + * are also headSurface-less heads, build a new request structure with the + * headSurface-ful heads removed and call down. + */ + + if (nNonHsHeads != 0) { + + NvBool tmp; + struct NvKmsFlipRequest *pRequestLocal = + HsIoctlRemoveHsHeadsFromNvKmsFlipRequest( + pDevEvo, pRequest, pWorkArea->hsMask); + + if (pRequestLocal == NULL) { + goto done; + } + + tmp = nvFlipEvo(pDevEvo, + pOpenDev, + pRequestLocal, + pReply, + FALSE /* skipUpdate */, + TRUE /* allowFlipLock */); + + nvFree(pRequestLocal); + + if (!tmp) { + goto done; + } + } + + /* We cannot fail beyond this point. */ + + ret = TRUE; + + + /* If this is a validation-only request, we are done. */ + + if (!pRequest->commit) { + goto done; + } + + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + FOR_EACH_INDEX_IN_MASK(32, head, pWorkArea->hsMask[sd]) { + const NvU32 apiHead = nvHardwareHeadToApiHead(head); + NVHsChannelEvoRec *pHsChannel = pDispEvo->pHsChannel[apiHead]; + const struct NvKmsFlipCommonParams *pParams = + &pRequest->sd[sd].head[head]; + NVFlipEvoHwState *pFlipState = + &pWorkArea->flipState[sd][head]; + + if (!nvHeadIsActive(pDispEvo, head)) { + continue; + } + + if (pParams->layer[NVKMS_MAIN_LAYER].skipPendingFlips && + pFlipState->dirty.layer[NVKMS_MAIN_LAYER]) { + nvHsIdleFlipQueue(pHsChannel, TRUE /* force */); + } + } FOR_EACH_INDEX_IN_MASK_END; + } + + /* Finally, update the headSurface-ful heads in the request. */ + + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + FOR_EACH_INDEX_IN_MASK(32, head, pWorkArea->hsMask[sd]) { + const NvU32 apiHead = nvHardwareHeadToApiHead(head); + const NVFlipEvoHwState *pFlipState = + &pWorkArea->flipState[sd][head]; + + NVHsChannelEvoRec *pHsChannel = pDispEvo->pHsChannel[apiHead]; + NvU32 layer; + + nvAssert(pHsChannel != NULL); + + if (pFlipState->dirty.cursorPosition) { + HsIoctlMoveCursor( + pHsChannel, + pFlipState->cursor.x, + pFlipState->cursor.y); + } + + if (pFlipState->dirty.cursorSurface) { + HsIoctlSetCursorImage( + pHsChannel, + pFlipState->cursor.pSurfaceEvo); + } + + if (pFlipState->dirty.viewPortPointIn) { + HsIoctlPan(pHsChannel, &pFlipState->viewPortPointIn); + } + + /* + * XXX NVKMS HEADSURFACE TODO: Layers that are specified as part + * of the same NVKMS_IOCTL_FLIP request should be flipped + * atomically. But, layers that are specified separately should + * be allowed to flip separately. Update the headSurface flip + * queue handling to coordinate multi-layer atomic flips. + */ + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + if (!pFlipState->dirty.layer[layer]) { + continue; + } + + if (layer == NVKMS_MAIN_LAYER) { + HsIoctlAssignSurfacesMaxEyes( + pHsChannel->flipQueueMainLayerState.pSurfaceEvo, + pFlipState->layer[layer].pSurfaceEvo); + } + + nvHsPushFlipQueueEntry(pHsChannel, layer, &pFlipState->layer[layer]); + + if (pHsChannel->config.neededForSwapGroup) { + pHsChannel->swapGroupFlipping = NV_TRUE; + } + } + } FOR_EACH_INDEX_IN_MASK_END; + } + +done: + + nvFree(pWorkArea); + + return ret; +} + diff --git a/src/nvidia-modeset/src/nvkms-headsurface-matrix.c b/src/nvidia-modeset/src/nvkms-headsurface-matrix.c new file mode 100644 index 000000000..6ba69cdf2 --- /dev/null +++ b/src/nvidia-modeset/src/nvkms-headsurface-matrix.c @@ -0,0 +1,661 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include "nvkms-headsurface-matrix.h" +#include "nvkms-softfloat.h" +#include "nv-float.h" + +/*! + * Multiply the matrices 'l' and 'r', and return the result. + */ +static struct NvKmsMatrixF32 MultiplyMatrix( + const struct NvKmsMatrixF32 *l, + const struct NvKmsMatrixF32 *r) +{ + struct NvKmsMatrixF32 d = { }; + int dx, dy; + + for (dy = 0; dy < 3; dy++) { + for (dx = 0; dx < 3; dx++) { + float32_t v = NvU32viewAsF32(NV_FLOAT_ZERO); + int o; + for (o = 0; o < 3; o++) { + const float32_t a = f32_mul(l->m[dy][o], r->m[o][dx]); + v = f32_add(v, a); + } + d.m[dy][dx] = v; + } + } + + return d; +} + +/*! + * Generate a matrix that performs the translation described by tx in x and ty + * in y. + */ +static struct NvKmsMatrixF32 GenTranslationMatrix( + float32_t tx, + float32_t ty) +{ + struct NvKmsMatrixF32 ret = { }; + + ret.m[0][0] = NvU32viewAsF32(NV_FLOAT_ONE); + ret.m[0][1] = NvU32viewAsF32(NV_FLOAT_ZERO); + ret.m[0][2] = tx; + ret.m[1][0] = NvU32viewAsF32(NV_FLOAT_ZERO); + ret.m[1][1] = NvU32viewAsF32(NV_FLOAT_ONE); + ret.m[1][2] = ty; + ret.m[2][0] = NvU32viewAsF32(NV_FLOAT_ZERO); + ret.m[2][1] = NvU32viewAsF32(NV_FLOAT_ZERO); + ret.m[2][2] = NvU32viewAsF32(NV_FLOAT_ONE); + + return ret; +} + +/*! + * Generate a matrix that performs the scaling operation described by sx in x + * and sy in y. + */ +static struct NvKmsMatrixF32 GenScaleMatrix( + float32_t sx, + float32_t sy) +{ + struct NvKmsMatrixF32 ret = { }; + + ret.m[0][0] = sx; + ret.m[0][1] = NvU32viewAsF32(NV_FLOAT_ZERO); + ret.m[0][2] = NvU32viewAsF32(NV_FLOAT_ZERO); + ret.m[1][0] = NvU32viewAsF32(NV_FLOAT_ZERO); + ret.m[1][1] = sy; + ret.m[1][2] = NvU32viewAsF32(NV_FLOAT_ZERO); + ret.m[2][0] = NvU32viewAsF32(NV_FLOAT_ZERO); + ret.m[2][1] = NvU32viewAsF32(NV_FLOAT_ZERO); + ret.m[2][2] = NvU32viewAsF32(NV_FLOAT_ONE); + + return ret; +} + +/*! + * Generate a matrix that performs the rotation operation described by cosine + * 'c' and sine 's'. + */ +static struct NvKmsMatrixF32 GenRotationMatrix( + float32_t c, + float32_t s) +{ + struct NvKmsMatrixF32 ret = { }; + const float32_t negOneF32 = NvU32viewAsF32(NV_FLOAT_NEG_ONE); + + ret.m[0][0] = c; + ret.m[0][1] = f32_mul(s, negOneF32); + ret.m[0][2] = NvU32viewAsF32(NV_FLOAT_ZERO); + ret.m[1][0] = s; + ret.m[1][1] = c; + ret.m[1][2] = NvU32viewAsF32(NV_FLOAT_ZERO); + ret.m[2][0] = NvU32viewAsF32(NV_FLOAT_ZERO); + ret.m[2][1] = NvU32viewAsF32(NV_FLOAT_ZERO); + ret.m[2][2] = NvU32viewAsF32(NV_FLOAT_ONE); + + return ret; +} + +/*! + * Generate the identity matrix. + */ +static struct NvKmsMatrixF32 GenIdentityMatrix(void) +{ + return GenScaleMatrix(NvU32viewAsF32(NV_FLOAT_ONE), + NvU32viewAsF32(NV_FLOAT_ONE)); +} + +/*! + * Transform x,y,q with a 3x3 affine transformation matrix (row-major). + */ +static inline void TransformVertex( + const struct NvKmsMatrixF32 *mat, + float32_t *pX, + float32_t *pY, + float32_t *pQ) +{ + const float32_t x_in = *pX; + const float32_t y_in = *pY; + const float32_t oneF32 = NvU32viewAsF32(NV_FLOAT_ONE); + float32_t w, oneOverW, x, y; + + x = F32_AxB_plus_CxD_plus_E(x_in, mat->m[0][0], + y_in, mat->m[0][1], + mat->m[0][2]); + y = F32_AxB_plus_CxD_plus_E(x_in, mat->m[1][0], + y_in, mat->m[1][1], + mat->m[1][2]); + w = F32_AxB_plus_CxD_plus_E(x_in, mat->m[2][0], + y_in, mat->m[2][1], + mat->m[2][2]); + oneOverW = f32_div(oneF32, w); + + x = f32_mul(x, oneOverW); + y = f32_mul(y, oneOverW); + + *pX = x; + *pY = y; + *pQ = oneOverW; +} + +/*! + * Transform pRectIn by the matrix, returning the result in pRectOut. + * + * XXX If we knew the matrix would produce a screen-aligned rectangle, we + * wouldn't need to transform as many points. + * + * XXX We should probably compute the screen-aligned rect inscribed by the + * transformed points, rather than compute the bounding box. + */ +static struct NvKmsRect TransformRect( + const struct NvKmsRect *pRectIn, + const struct NvKmsMatrixF32 *transform) +{ + /* + * Get the four corners of pRectIn: + * + * 0 3 + * +----------+ + * | | + * +----------+ + * 1 2 + */ + struct NvKmsPoint p[4] = { + [0] = { + .x = pRectIn->x, + .y = pRectIn->y, + }, + [1] = { + .x = pRectIn->x, + .y = pRectIn->y + pRectIn->height, + }, + [2] = { + .x = pRectIn->x + pRectIn->width, + .y = pRectIn->y + pRectIn->height, + }, + [3] = { + .x = pRectIn->x + pRectIn->width, + .y = pRectIn->y, + }, + }; + + NvU8 i; + NvU16 minx, maxx, miny, maxy; + struct NvKmsRect rectOut = { }; + + /* Apply the matrix transform to each point. */ + + for (i = 0; i < 4; i++) { + + float32_t x = ui32_to_f32(p[i].x); + float32_t y = ui32_to_f32(p[i].y); + float32_t unused; + + TransformVertex(transform, &x, &y, &unused); + + p[i].x = F32toNvU16(x); + p[i].y = F32toNvU16(y); + } + + /* Compute the screen-aligned bounding box of the transformed points. */ + + minx = p[0].x; + maxx = p[0].x; + miny = p[0].y; + maxy = p[0].y; + + for (i = 1; i < 4; i++) { + minx = NV_MIN(minx, p[i].x); + maxx = NV_MAX(maxx, p[i].x); + miny = NV_MIN(miny, p[i].y); + maxy = NV_MAX(maxy, p[i].y); + } + + rectOut.x = minx; + rectOut.y = miny; + rectOut.width = maxx - minx; + rectOut.height = maxy - miny; + + return rectOut; +} + +/*! + * Apply the rotation described by 'rotation' and 'viewPortOut' to the + * transformation matrix. + * + * \param[in] viewPortOut The viewPortOut region. + * \param[in] transform The current transformation matrix. + * \param[in] rotation The requested screen-aligned rotation. + * + * \return The resulting transformation matrix. + */ +static struct NvKmsMatrixF32 ApplyRotationToMatrix( + const struct NvKmsRect *viewPortOut, + const struct NvKmsMatrixF32 *transform, + enum NvKmsRotation rotation) +{ + const float32_t zeroF32 = NvU32viewAsF32(NV_FLOAT_ZERO); + const float32_t oneF32 = NvU32viewAsF32(NV_FLOAT_ONE); + const float32_t negOneF32 = NvU32viewAsF32(NV_FLOAT_NEG_ONE); + + float32_t f_rot_cos, f_rot_sin, f_rot_dx, f_rot_dy; + float32_t width, height; + + struct NvKmsMatrixF32 m = *transform; + struct NvKmsMatrixF32 tmpMatrix; + + struct NvKmsRect transformedViewPortOut; + + if (rotation == NVKMS_ROTATION_0) { + return m; + } + + transformedViewPortOut = TransformRect(viewPortOut, transform); + + width = ui32_to_f32(transformedViewPortOut.width); + height = ui32_to_f32(transformedViewPortOut.height); + + switch (rotation) { + default: + case NVKMS_ROTATION_90: + f_rot_cos = zeroF32; f_rot_sin = oneF32; + f_rot_dx = height; f_rot_dy = zeroF32; + break; + case NVKMS_ROTATION_180: + f_rot_cos = negOneF32; f_rot_sin = zeroF32; + f_rot_dx = width; f_rot_dy = height; + break; + case NVKMS_ROTATION_270: + f_rot_cos = zeroF32; f_rot_sin = negOneF32; + f_rot_dx = zeroF32; f_rot_dy = width; + break; + } + + tmpMatrix = GenRotationMatrix(f_rot_cos, f_rot_sin); + m = MultiplyMatrix(&tmpMatrix, &m); + + tmpMatrix = GenTranslationMatrix(f_rot_dx, f_rot_dy); + m = MultiplyMatrix(&tmpMatrix, &m); + + return m; +} + +/*! + * Apply the reflection described by 'reflection[XY]', 'rotation' and + * 'viewPortOut' to the transformation matrix. + * + * \param[in] viewPortOut The viewPortOut region. + * \param[in] transform The current transformation matrix. + * \param[in] reflectionX Whether to reflect along the X axis. + * \param[in] reflectionY Whether to reflect along the Y axis. + * + * \return The resulting transformation matrix. + */ +static struct NvKmsMatrixF32 ApplyReflectionToMatrix( + const struct NvKmsRect *viewPortOut, + const struct NvKmsMatrixF32 *transform, + NvBool reflectionX, + NvBool reflectionY) +{ + const float32_t zeroF32 = NvU32viewAsF32(NV_FLOAT_ZERO); + const float32_t oneF32 = NvU32viewAsF32(NV_FLOAT_ONE); + const float32_t negOneF32 = NvU32viewAsF32(NV_FLOAT_NEG_ONE); + + float32_t f_scale_x, f_scale_y, f_scale_dx, f_scale_dy; + float32_t width, height; + + struct NvKmsMatrixF32 m = *transform; + struct NvKmsMatrixF32 tmpMatrix; + + struct NvKmsRect transformedViewPortOut; + + if (!reflectionX && !reflectionY) { + return m; + } + + transformedViewPortOut = TransformRect(viewPortOut, transform); + + width = ui32_to_f32(transformedViewPortOut.width); + height = ui32_to_f32(transformedViewPortOut.height); + + f_scale_x = oneF32; + f_scale_dx = zeroF32; + f_scale_y = oneF32; + f_scale_dy = zeroF32; + + if (reflectionX) { + f_scale_x = negOneF32; + f_scale_dx = width; + } + + if (reflectionY) { + f_scale_y = negOneF32; + f_scale_dy = height; + } + + tmpMatrix = GenScaleMatrix(f_scale_x, f_scale_y); + m = MultiplyMatrix(&tmpMatrix, &m); + + tmpMatrix = GenTranslationMatrix(f_scale_dx, f_scale_dy); + m = MultiplyMatrix(&tmpMatrix, &m); + + return m; +} + +/*! + * Apply the scaling described by 'viewPortIn' and 'viewPortOut' to the + * transformation matrix. + * + * \param[in] viewPortIn The viewPortIn region. + * \param[in] viewPortOut The viewPortOut region. + * \param[in] transform The current transformation matrix. + * + * \return The resulting transformation matrix. + */ +static struct NvKmsMatrixF32 ScaleMatrixForViewPorts( + const struct NvKmsRect *viewPortIn, + const struct NvKmsRect *viewPortOut, + const struct NvKmsMatrixF32 *transform) +{ + const struct NvKmsRect transformedViewPortOut = + TransformRect(viewPortOut, transform); + + const float32_t inWidth = ui32_to_f32(viewPortIn->width); + const float32_t inHeight = ui32_to_f32(viewPortIn->height); + const float32_t outWidth = ui32_to_f32(transformedViewPortOut.width); + const float32_t outHeight = ui32_to_f32(transformedViewPortOut.height); + + struct NvKmsMatrixF32 tmpMatrix; + + const float32_t sx = f32_div(inWidth, outWidth); + const float32_t sy = f32_div(inHeight, outHeight); + + tmpMatrix = GenScaleMatrix(sx, sy); + + return MultiplyMatrix(&tmpMatrix, transform); +} + +/*! + * Translate the matrix for the ViewPortOut position. + * + * When headSurface state == FULL, the headSurface surface is the size of the + * visible region of the mode and headSurface rendering simulates the + * client-requested viewPortOut. Translate the headSurface transformation + * matrix for the ViewPortOut position. + * + * \param[in] state The headSurface state; we only translate for FULL. + * \param[in] viewPortOut The viewPortOut region. + * \param[in] transform The current transformation matrix. + */ +static struct NvKmsMatrixF32 TranslateMatrixForViewPortOut( + const NVHsConfigState state, + const struct NvKmsRect *viewPortOut, + const struct NvKmsMatrixF32 *transform) +{ + if (state != NVKMS_HEAD_SURFACE_CONFIG_STATE_FULL_HEAD_SURFACE) { + return *transform; + } + + const struct NvKmsRect transformedViewPortOut = + TransformRect(viewPortOut, transform); + + const float32_t x = ui32_to_f32(transformedViewPortOut.x); + const float32_t y = ui32_to_f32(transformedViewPortOut.y); + const float32_t negX = f32_mul(x, NvU32viewAsF32(NV_FLOAT_NEG_ONE)); + const float32_t negY = f32_mul(y, NvU32viewAsF32(NV_FLOAT_NEG_ONE)); + + const struct NvKmsMatrixF32 translationMatrix = + GenTranslationMatrix(negX, negY); + + return MultiplyMatrix(&translationMatrix, transform); +} + +/*! + * For pixelShift modes, bloat by x2 (pixelShift takes a 2x2 quad of input + * pixels for each output pixel). + * + * \param[in] transform The current transformation matrix. + * \param[in] pixelShift The pixelShift mode requested. + */ +static struct NvKmsMatrixF32 TransformMatrixForPixelShift( + const struct NvKmsMatrixF32 *transform, + enum NvKmsPixelShiftMode pixelShift) +{ + const float32_t twoF32 = NvU32viewAsF32(NV_FLOAT_TWO); + const struct NvKmsMatrixF32 pixelShiftBloatTransform = + GenScaleMatrix(twoF32, twoF32); + struct NvKmsMatrixF32 m = *transform; + + if (pixelShift == NVKMS_PIXEL_SHIFT_NONE) { + return m; + } + + return MultiplyMatrix(&pixelShiftBloatTransform, &m); +} + +/*! + * Multiply the client-specified transform with the current transform. + * + * \param[in] transform The current transformation matrix. + * \param[in] p The client request parameter structure. + */ +static struct NvKmsMatrixF32 ApplyClientTransformToMatrix( + const struct NvKmsMatrixF32 *transform, + const struct NvKmsSetModeHeadSurfaceParams *p) +{ + const struct NvKmsMatrixF32 clientTransform = + NvKmsMatrixToNvKmsMatrixF32(p->transform); + + nvAssert(p->transformSpecified); + + return MultiplyMatrix(&clientTransform, transform); +} + +static NvBool InvertMatrix( + struct NvKmsMatrixF32 *dst, + const struct NvKmsMatrixF32 *src) +{ + float64_t det; + int i, j; + static int a[3] = { 2, 2, 1 }; + static int b[3] = { 1, 0, 0 }; + const float64_t zeroF64 = i32_to_f64(0); + const float64_t oneF64 = i32_to_f64(1); + + det = zeroF64; + for (i = 0; i < 3; i++) { + float64_t p; + const int ai = a[i]; + const int bi = b[i]; + + float32_t tmp = F32_AxB_minus_CxD(src->m[ai][2], src->m[bi][1], + src->m[ai][1], src->m[bi][2]); + tmp = f32_mul(src->m[i][0], tmp); + + p = f32_to_f64(tmp); + + if (i == 1) { + p = F64_negate(p); + } + + det = f64_add(det, p); + } + + if (f64_eq(det, zeroF64)) { + return FALSE; + } + + det = f64_div(oneF64, det); + + for (j = 0; j < 3; j++) { + for (i = 0; i < 3; i++) { + float64_t p; + const int ai = a[i]; + const int aj = a[j]; + const int bi = b[i]; + const int bj = b[j]; + + const float32_t tmp = + F32_AxB_minus_CxD(src->m[ai][aj], src->m[bi][bj], + src->m[ai][bj], src->m[bi][aj]); + p = f32_to_f64(tmp); + + if (((i + j) & 1) != 0) { + p = F64_negate(p); + } + + p = f64_mul(det, p); + + dst->m[j][i] = f64_to_f32(p); + } + } + + return TRUE; +} + +/*! + * Calculate a warp mesh for this head. + * + * This constructs a simple 4-vertex "mesh" that renders a single quad using a + * triangle strip. The vertices are transformed from the viewPortIn region + * using the inversed of the HS transform to normalized headSurface space. + */ +static NvBool AssignStaticWarpMesh( + NVHsChannelConfig *p) +{ + int i; + + NvHsStaticWarpMesh *swm = &p->staticWarpMesh; + + const float32_t viewPortInWidthF = ui32_to_f32(p->viewPortIn.width); + const float32_t viewPortInHeightF = ui32_to_f32(p->viewPortIn.height); + const float32_t viewPortOutWidthF = ui32_to_f32(p->viewPortOut.width); + const float32_t viewPortOutHeightF = ui32_to_f32(p->viewPortOut.height); + + struct NvKmsMatrixF32 invertedTransform; + + if (!InvertMatrix(&invertedTransform, &p->transform)) { + return FALSE; + } + + swm->vertex[0].x = swm->vertex[0].u = NV_FLOAT_ZERO; + swm->vertex[0].y = swm->vertex[0].v = NV_FLOAT_ZERO; + + swm->vertex[1].x = swm->vertex[1].u = NV_FLOAT_ZERO; + swm->vertex[1].y = swm->vertex[1].v = NV_FLOAT_ONE; + + swm->vertex[2].x = swm->vertex[2].u = NV_FLOAT_ONE; + swm->vertex[2].y = swm->vertex[2].v = NV_FLOAT_ZERO; + + swm->vertex[3].x = swm->vertex[3].u = NV_FLOAT_ONE; + swm->vertex[3].y = swm->vertex[3].v = NV_FLOAT_ONE; + + for (i = 0; i < 4; i++) { + + float32_t x = NvU32viewAsF32(swm->vertex[i].x); + float32_t y = NvU32viewAsF32(swm->vertex[i].y); + float32_t q; + + // Scale to input region + x = f32_mul(x, viewPortInWidthF); + y = f32_mul(y, viewPortInHeightF); + + // Transform + TransformVertex(&invertedTransform, &x, &y, &q); + + // Normalize to output region + x = f32_div(x, viewPortOutWidthF); + y = f32_div(y, viewPortOutHeightF); + + swm->vertex[i].x = F32viewAsNvU32(x); + swm->vertex[i].y = F32viewAsNvU32(y); + swm->vertex[i].q = F32viewAsNvU32(q); + } + + return TRUE; +} + +/*! + * Assign NVHsChannelConfig::transform and NVHsChannelConfig::staticWarpMesh, + * based on the current viewports described in NVHsChannelConfig, and various + * client-requested state in NvKmsSetModeHeadSurfaceParams. + * + * \param[in,out] pChannelConfig The headSurface channel config. + * \param[in] p The NVKMS client headSurface parameters. + * + * \return TRUE if the NVHsChannelConfig fields could be successfully assigned. + * Otherwise, FALSE. + */ +NvBool nvHsAssignTransformMatrix( + NVHsChannelConfig *pChannelConfig, + const struct NvKmsSetModeHeadSurfaceParams *p) +{ + struct NvKmsMatrixF32 transform = GenIdentityMatrix(); + + transform = TranslateMatrixForViewPortOut( + pChannelConfig->state, + &pChannelConfig->viewPortOut, + &transform); + + transform = TransformMatrixForPixelShift( + &transform, + p->pixelShift); + + transform = ApplyRotationToMatrix( + &pChannelConfig->viewPortOut, + &transform, + p->rotation); + + transform = ApplyReflectionToMatrix( + &pChannelConfig->viewPortOut, + &transform, + p->reflectionX, + p->reflectionY); + /* + * We treat client-specified transformation matrices and viewport scaling as + * mutually exclusive: when a client-specified transformation matrix is + * provided, the viewPortIn is already transformed by that matrix (the + * client needed to do that, in order to know the size of the surface). + * Calling ScaleMatrixForViewPorts() in the transformSpecified would + * effectively scale the viewPortIn a second time, which would be incorrect. + */ + if (p->transformSpecified) { + transform = ApplyClientTransformToMatrix( + &transform, p); + } else { + transform = ScaleMatrixForViewPorts( + &pChannelConfig->viewPortIn, + &pChannelConfig->viewPortOut, + &transform); + } + + pChannelConfig->transform = transform; + + return AssignStaticWarpMesh(pChannelConfig); +} + diff --git a/src/nvidia-modeset/src/nvkms-headsurface-swapgroup.c b/src/nvidia-modeset/src/nvkms-headsurface-swapgroup.c new file mode 100644 index 000000000..d216cdec7 --- /dev/null +++ b/src/nvidia-modeset/src/nvkms-headsurface-swapgroup.c @@ -0,0 +1,951 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvkms-headsurface-swapgroup.h" +#include "nvkms-headsurface-config.h" +#include "nvkms-headsurface.h" +#include "nvkms-utils.h" +#include "nvkms-private.h" + +/* + * When headSurface is used to implement a SwapGroup, there are several surfaces + * involved: + * + * +------+ + * | | Client Surface + * +------+ + * | | + * +---+ +---+ screen-aligned blits + * v v + * +------+ +------+ + * |(0) | |(1) | Staging Surfaces + * +------+ +------+ + * | | headSurface transformation + * v v + * +------+ +------+ + * |(0) | |(1) | + * |......| |......| Double-height headSurface surfaces. + * | | | | + * +------+ +------+ + * + * For each frame of headSurface: + * + * - All non-SwapGroup content from the Client Surface is copied to Staging + * Surface (0) (merging new non-SwapGroup content with old SwapGroup content). + * + * - All content is copied from the Client Surface to Staging Surface (1). + * + * - HeadSurface transformation (applying rotation, yuv420, etc) textures from + * Staging Surface (0) and renders to one half of double-height headSurface + * surface (0). + * + * - HeadSurface transformation (applying rotation, yuv420, etc) textures from + * Staging Surface (1) and renders to one half of double-height headSurface + * surface (1). + * + * - We use ViewPortIn to flip between halves of the double-height headSurface + * surfaces. + * + * - We use flip-locked flips to flip between the headSurface surfaces (0) and + * (1). + * + * For performance reasons the following optimizations are in place to + * reduce blitting overhead: + * + * - If Swapgroup content is full-screen we skip the Staging Surface + * entirely. There are no regions of Swapgroup and non-Swapgroup content + * that need to be glued together in the Staging Surface: we will only + * ever source updated content from the swapgroup client. We can also + * render transformed frames without the Staging Surface in this case. + * + * - With full-screen Swapgroup content we can also skip REQUEST_TYPE_VBLANK + * frames as there can't possibly be any non-Swapgroup content to be + * updated. We do have to keep rendering continuously though to update the + * mouse cursor, overlays, and other individual artifacts. We thus skip + * REQUEST_TYPE_VBLANK frames if the client keeps actively generating + * REQUEST_TYPE_SWAP_GROUP_READY frames. However, if the client pauses + * itself we fall back to rendering REQUEST_TYPE_VBLANK frames for cursor + * and other updates at vsync rate. + */ + +static void FlipSwapGroup( + NVDevEvoPtr pDevEvo, + NVSwapGroupRec *pSwapGroup); + +/*! + * Update whether this pSwapGroup needs headSurface. + * + * \param[in] pDevEvo The device the SwapGroup is on. + * \param[in] pSwapGroup The SwapGroup to update. + * \param[in] needed Whether headSurface is needed for this SwapGroup. + * + * The usage here is similar to what is done at modeset time: create an + * NVHsConfig and initialize it to describe the headSurface configuration + * required across the device. Allocate the resources for the NVHsConfig and + * apply them to the pDevEvo. + * + * \return Return whether the headSurface needed state could be successfully + * updated. + */ +static NvBool HsSwapGroupUpdateHeadSurfaceNeeded( + NVDevEvoPtr pDevEvo, + const NVSwapGroupRec *pSwapGroup, + const NvBool needed) +{ + NvBool ret = FALSE; + NVHsConfig *pHsConfig = nvCalloc(1, sizeof(*pHsConfig)); + + if (pHsConfig == NULL) { + goto done; + } + + nvHsConfigInitSwapGroup(pDevEvo, pSwapGroup, needed, pHsConfig); + + if (!nvHsConfigAllocResources(pDevEvo, pHsConfig)) { + goto done; + } + + /* + * XXX NVKMS HEADSURFACE TODO: validate the pHsConfig. If we fail + * validation, downgrade and try again. Repeat until we either pass + * validation or downgrading fails and we need to give up. + */ + + /* we cannot fail beyond this point */ + + nvHsConfigStop(pDevEvo, pHsConfig); + + nvHsConfigStart(pDevEvo, pHsConfig); + + nvHsConfigFreeResources(pDevEvo, pHsConfig); + + ret = TRUE; + +done: + nvFree(pHsConfig); + + return ret; +} + + +/*! + * Return whether there is a non-zero number of SwapGroup members for the + * specified device, disp, head. + */ +NvBool nvHsSwapGroupIsHeadSurfaceNeeded( + const NVDispEvoRec *pDispEvo, + const NvU32 apiHead) +{ + const NVSwapGroupRec *pSwapGroup = pDispEvo->pSwapGroup[apiHead]; + + if (pSwapGroup == NULL) { + return FALSE; + } + + return pSwapGroup->nMembers > 0; +} + + +/* + * We should only write to the NvKmsDeferredRequestFifo::semaphore[] element + * that the client requested. When the NVDeferredRequestFifoRec is not ready, + * store an invalid semaphore index value, so that bad indexing is obvious. + */ +#define INVALID_SEMAPHORE_INDEX 0xFFFFFFFF + + +/*! + * Return whether all current members of the SwapGroup are ready to swap. + */ +static NvBool SwapGroupIsReady(const NVSwapGroupRec *pSwapGroup) +{ + /* + * As an optimization, we maintain nMembers and nMembersReady so that we can + * quickly check if all members are ready. + * + * If a member joins while a swapgroup has a pending flip, it is put in a + * pendingJoined state, added to nMembersPendingJoined, and not counted + * here. + */ + NvBool ret = (pSwapGroup->nMembers - pSwapGroup->nMembersPendingJoined) == + pSwapGroup->nMembersReady; + + /* This should only be called if a swap group hasn't been zombified. */ + nvAssert(!pSwapGroup->zombie); + +#if defined(DEBUG) + /* + * Assert that bookkeeping matches between + * pDeferredRequestFifo->swapGroup.ready, + * pDeferredRequestFifo->swapGroup.pendingJoined, and nMembersReady. + */ + NvBool assertRet = TRUE; + + const NVDeferredRequestFifoRec *pDeferredRequestFifo; + + FOR_ALL_DEFERRED_REQUEST_FIFOS_IN_SWAP_GROUP(pSwapGroup, + pDeferredRequestFifo) { + + nvAssert(pDeferredRequestFifo->swapGroup.pSwapGroup == pSwapGroup); + if (!pDeferredRequestFifo->swapGroup.ready && + !pDeferredRequestFifo->swapGroup.pendingJoined) { + assertRet = FALSE; + break; + } + } + + nvAssert(assertRet == ret); +#endif + + return ret; +} + + +/*! + * Release the pDeferredRequestFifo member of the SwapGroup. + */ +static void ReleaseDeferredRequestFifo( + NVDeferredRequestFifoRec *pDeferredRequestFifo) +{ + const NvGpuSemaphore semReadyValue = { + .data[0] = NVKMS_DEFERRED_REQUEST_SEMAPHORE_VALUE_SWAP_GROUP_READY, + }; + + const NvU32 semIndex = pDeferredRequestFifo->swapGroup.semaphoreIndex; + struct NvKmsDeferredRequestFifo *pFifo = pDeferredRequestFifo->fifo; + NVSwapGroupRec *pSwapGroup = pDeferredRequestFifo->swapGroup.pSwapGroup; + + /* This should only be called if the member is ready. */ + nvAssert(pDeferredRequestFifo->swapGroup.ready); + + /* + * This shouldn't be called if a new member has joined and submitted + * swapready while the swap group had an outstanding flip (i.e. + * pendingJoined is true). In that case: + * + * - nvHsSwapGroupReady() will mark this member as pendingReady + * - When the flip completes, nvHsSwapGroupRelease will release all members + * that were present when the flip was kicked off, and promote + * pendingJoined/pendingReady members to joined/ready + * - When the original members submit another ready (nvHsSwapGroupReady), + * the last non-ready original member leaves (nvHsLeaveSwapGroup), or + * the last non-pendingReady member leaves between kicking off a flip + * and the first vblank after the flip completes (nvHsSwapGroupRelease), + * a new flip is kicked off. + */ + nvAssert(!pDeferredRequestFifo->swapGroup.pendingJoined && + !pDeferredRequestFifo->swapGroup.pendingReady); + + if (semIndex < ARRAY_LEN(pFifo->semaphore)) { + pFifo->semaphore[semIndex] = semReadyValue; + + nvSendUnicastEvent(pDeferredRequestFifo->swapGroup.pOpenUnicastEvent); + + } else { + + /* + * The semaphoreIndex is validated in nvHsSwapGroupReady() before + * assignment, so it should always be valid by the time we get here. + */ + nvAssert(!"Invalid semIndex"); + } + + pDeferredRequestFifo->swapGroup.ready = FALSE; + pDeferredRequestFifo->swapGroup.semaphoreIndex = INVALID_SEMAPHORE_INDEX; + + /* + * This may be called if a deferred request fifo entry is being processed + * after its associated swap group has been freed, in which case, + * pDeferredRequestFifo->swapGroup.pSwapGroup will be NULL. + */ + if (pSwapGroup) { + nvAssert(!pSwapGroup->zombie); + nvAssert(pSwapGroup->nMembersReady > 0); + pSwapGroup->nMembersReady--; + } +} + + +/*! + * Release all members of the SwapGroup. + */ +void nvHsSwapGroupRelease( + NVDevEvoPtr pDevEvo, + NVSwapGroupRec *pSwapGroup) +{ + NVDeferredRequestFifoRec *pDeferredRequestFifo; + NvBool readiedFifos = FALSE; + + /* This should only be called if a swap group hasn't been zombified. */ + nvAssert(!pSwapGroup->zombie); + + FOR_ALL_DEFERRED_REQUEST_FIFOS_IN_SWAP_GROUP(pSwapGroup, + pDeferredRequestFifo) { + if (!pDeferredRequestFifo->swapGroup.pendingJoined) { + ReleaseDeferredRequestFifo(pDeferredRequestFifo); + } + } + + nvAssert(pSwapGroup->nMembersReady == 0); + + pSwapGroup->pendingFlip = FALSE; + + /* + * If a new member joins or submits swap ready between FlipSwapGroup() + * and nvHsSwapGroupRelease, it enters the pendingJoined and pendingReady + * state to avoid changing swap group state while a flip is in flight. + * + * Now that the flip has completed, promote these members to fully joined/ + * fully ready. + */ + if (pSwapGroup->nMembersPendingJoined != 0) { + FOR_ALL_DEFERRED_REQUEST_FIFOS_IN_SWAP_GROUP(pSwapGroup, + pDeferredRequestFifo) { + if (pDeferredRequestFifo->swapGroup.pendingJoined) { + pDeferredRequestFifo->swapGroup.pendingJoined = FALSE; + nvAssert(pSwapGroup->nMembersPendingJoined > 0); + pSwapGroup->nMembersPendingJoined--; + } + + if (pDeferredRequestFifo->swapGroup.pendingReady) { + pDeferredRequestFifo->swapGroup.pendingReady = FALSE; + pDeferredRequestFifo->swapGroup.ready = TRUE; + pSwapGroup->nMembersReady++; + readiedFifos = TRUE; + } + } + + nvAssert(pSwapGroup->nMembersPendingJoined == 0); + } + + /* + * If any pending joined fifos submitted SWAP_READY while a flip was in + * flight, they were promoted from pending ready to ready above; if the + * fifos that were previously joined to the swap group left while their + * last flip was in flight, then we need to kick off a new flip for the + * previously pending ready fifos now. + */ + if (readiedFifos && SwapGroupIsReady(pSwapGroup)) { + FlipSwapGroup(pDevEvo, pSwapGroup); + } +} + + +/*! + * Enqueue a headSurface flip on all heads of the pSwapGroup. + * + * Now that the specified pSwapGroup is ready, call + * nvHsNextFrame(SWAP_GROUP_READY) for all active heads in the pSwapGroup. This + * will render a new frame of headSurface, including the now complete SwapGroup + * content, and kick off a flip to the new frame. The flip will only complete + * once the entire SwapBarrier is ready. + * + * Once headSurface sees that these flips completed, it will call + * nvHsSwapGroupRelease() to release all SwapGroup members. + */ +static void FlipSwapGroup( + NVDevEvoPtr pDevEvo, + NVSwapGroupRec *pSwapGroup) +{ + NVHsDeviceEvoPtr pHsDevice = pDevEvo->pHsDevice; + NVDispEvoPtr pDispEvo; + NvU32 dispIndex; + NvBool waitForFlip = FALSE; + + /* + * We should never kick off a new flip before the previous flip has + * completed and the swap group has been released. + */ + nvAssert(!pSwapGroup->pendingFlip); + + pSwapGroup->pendingFlip = TRUE; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + NvU32 apiHead; + for (apiHead = 0; apiHead < ARRAY_LEN(pDispEvo->pSwapGroup); apiHead++) { + if (pDispEvo->pSwapGroup[apiHead] == pSwapGroup) { + NVHsChannelEvoPtr pHsChannel = pDispEvo->pHsChannel[apiHead]; + + if (pHsChannel == NULL) { + continue; + } + + nvHsNextFrame(pHsDevice, pHsChannel, + NV_HS_NEXT_FRAME_REQUEST_TYPE_SWAP_GROUP_READY); + waitForFlip = TRUE; + } + } + } + + /* + * If there are no active heads in the pSwapGroup, then there are no flips + * to wait for: release the SwapGroup now. + */ + if (!waitForFlip) { + nvHsSwapGroupRelease(pDevEvo, pSwapGroup); + } +} + + +/*! + * Check that the NvKmsSwapGroupConfig is valid for the given pDevEvo. + */ +static NvBool HsSwapGroupValidateConfig( + const NVDevEvoRec *pDevEvo, + const struct NvKmsSwapGroupConfig *pConfig) +{ + const NvU32 validHeadMask = NVBIT(pDevEvo->numHeads) - 1; + NvU32 dispIndex; + + for (dispIndex = 0; dispIndex < ARRAY_LEN(pConfig->disp); dispIndex++) { + + if (pConfig->disp[dispIndex].headMask == 0) { + continue; + } + + /* Fail if the config describes disps not present on the pDevEvo. */ + + if (dispIndex >= pDevEvo->nDispEvo) { + return FALSE; + } + + /* Fail if the config describes heads not present on the disp. */ + + if ((pConfig->disp[dispIndex].headMask & ~validHeadMask) != 0) { + return FALSE; + } + } + + return TRUE; +} + +/*! + * Allocate a SwapGroup. + * + * This validates that the requested configuration is valid, and adds the + * SwapGroup to pDevEvo's list of SwapGroups. + */ +NVSwapGroupRec* nvHsAllocSwapGroup( + NVDevEvoPtr pDevEvo, + const struct NvKmsAllocSwapGroupRequest *pRequest) +{ + NVSwapGroupRec *pSwapGroup; + NVDispEvoPtr pDispEvo; + NvU32 dispIndex; + + if (!HsSwapGroupValidateConfig(pDevEvo, &pRequest->config)) { + return NULL; + } + + /* Are there heads requested that already belong to another SwapGroup? */ + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + NvU32 head; + FOR_ALL_HEADS(head, pRequest->config.disp[dispIndex].headMask) { + const NvU32 apiHead = nvHardwareHeadToApiHead(head); + if (pDispEvo->pSwapGroup[apiHead] != NULL) { + return NULL; + } + } + } + + pSwapGroup = nvCalloc(1, sizeof(*pSwapGroup)); + + if (pSwapGroup == NULL) { + return NULL; + } + + if (!nvHsIncrementSwapGroupRefCnt(pSwapGroup)) { + nvFree(pSwapGroup); + return NULL; + } + + nvListInit(&pSwapGroup->deferredRequestFifoList); + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + NvU32 head; + FOR_ALL_HEADS(head, pRequest->config.disp[dispIndex].headMask) { + const NvU32 apiHead = nvHardwareHeadToApiHead(head); + pDispEvo->pSwapGroup[apiHead] = pSwapGroup; + } + } + + return pSwapGroup; +} + + +/*! + * Returns a swap group with the given handle from the given set of swap group + * handles. + * + * Does not return NULL if pSwapGroup->zombie is TRUE; the only operation we + * want to perform on a swap group that has already been freed but hasn't lost + * all of its references yet is NVKMS_IOCTL_RELEASE_SWAP_GROUP; all other + * callers should use nvHsGetSwapGroup. + */ +NVSwapGroupRec *nvHsGetSwapGroupStruct( + const NVEvoApiHandlesRec *pEvoApiHandles, + NvKmsSwapGroupHandle handle) +{ + return nvEvoGetPointerFromApiHandle(pEvoApiHandles, handle); +} + + +/*! + * Returns a swap group with the given handle from the given set of swap group + * handles, or NULL if the swap group is in the "zombie" state. + * + * A swap group is in the "zombie" state if nvHsFreeSwapGroup() has removed it + * from pDevEvo->swapGroupList, removed its deferred request fifos from + * pSwapGroup->deferredRequestFifoList, and freed its clip list, but its + * reference count is nonzero; in that case, most operations on that swap group + * should call this function and behave as if that swap group no longer exists. + */ +NVSwapGroupRec *nvHsGetSwapGroup( + const NVEvoApiHandlesRec *pEvoApiHandles, + NvKmsSwapGroupHandle handle) +{ + NVSwapGroupRec *pSwapGroup = nvHsGetSwapGroupStruct(pEvoApiHandles, handle); + + if (pSwapGroup == NULL) { + return NULL; + } + + if (pSwapGroup->zombie) { + return NULL; + } + + return pSwapGroup; +} + + +/*! + * Increment the swap group's reference count, failing if refCnt is already + * NV_U64_MAX. + */ +NvBool nvHsIncrementSwapGroupRefCnt(NVSwapGroupPtr pSwapGroup) +{ + if (pSwapGroup->refCnt == NV_U64_MAX) { + return FALSE; + } + + pSwapGroup->refCnt++; + + return TRUE; +} + + +/*! + * Decrement the swap group's reference count, and free it if there are no more + * references to it. + */ +void nvHsDecrementSwapGroupRefCnt(NVSwapGroupPtr pSwapGroup) +{ + nvAssert(pSwapGroup->refCnt >= 1); + pSwapGroup->refCnt--; + + if (pSwapGroup->refCnt == 0) { + nvFree(pSwapGroup); + } +} + + +/*! + * Free the SwapGroup. + * + * - Make any NVDeferredRequestFifoRec members implicitly leave the SwapGroup. + * + * - Remove the SwapGroup from pDevEvo's list of SwapGroups. + * + * - Free the SwapGroup's pClipList + * + * - Mark the SwapGroup as a "zombie" and decrement its reference count. If + * this removes the last reference to the swap group, free it immediately. + * Otherwise, any remaining references to the swap group need to handle + * the "zombie" swap group correctly. + */ +void nvHsFreeSwapGroup( + NVDevEvoPtr pDevEvo, + NVSwapGroupRec *pSwapGroup) +{ + NVDeferredRequestFifoRec *pDeferredRequestFifo; + NVDeferredRequestFifoRec *pDeferredRequestFifoTmp; + NVDispEvoPtr pDispEvo; + NvU32 dispIndex; + + /* + * Be careful to use the "_safe" loop macro, because nvHsLeaveSwapGroup() + * will remove pDeferredRequestFifo from + * pSwapGroup->deferredRequestFifoList. + */ + nvListForEachEntry_safe(pDeferredRequestFifo, + pDeferredRequestFifoTmp, + &pSwapGroup->deferredRequestFifoList, + swapGroup.deferredRequestFifoListEntry) { + + nvHsLeaveSwapGroup(pDevEvo, pDeferredRequestFifo, TRUE /* teardown */); + } + + nvAssert(pSwapGroup->nMembers == 0); + nvAssert(pSwapGroup->nMembersReady == 0); + + /* + * XXX NVKMS HEADSURFACE TODO: Shutdown headSurface, if this SwapGroup was + * forcing headSurface on. + */ + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + NvU32 apiHead; + for (apiHead = 0; apiHead < ARRAY_LEN(pDispEvo->pSwapGroup); apiHead++) { + if (pDispEvo->pSwapGroup[apiHead] == pSwapGroup) { + pDispEvo->pSwapGroup[apiHead] = NULL; + } + } + } + + nvFree(pSwapGroup->pClipList); + pSwapGroup->pClipList = NULL; + + pSwapGroup->zombie = TRUE; + nvHsDecrementSwapGroupRefCnt(pSwapGroup); +} + + +/*! + * Given an array of {deferred request fifo, swapgroup} tuples, join each + * deferred request fifo to its corresponding swapgroup. If any join causes + * a headsurface transition which fails, clean up by undoing any headsurface + * transitions which succeeded. + */ +NvBool nvHsJoinSwapGroup( + NVHsJoinSwapGroupWorkArea *joinSwapGroupWorkArea, + NvU32 numHandles, + NvBool pendingJoin) +{ + NvU32 i; + + for (i = 0; i < numHandles; i++) { + NVDevEvoPtr pDevEvo = joinSwapGroupWorkArea[i].pDevEvo; + NVSwapGroupRec *pSwapGroup = joinSwapGroupWorkArea[i].pSwapGroup; + NVDeferredRequestFifoRec *pDeferredRequestFifo = + joinSwapGroupWorkArea[i].pDeferredRequestFifo; + + /* + * If we are transitioning from 0 to 1 nMembers, change the "needed" state + * of headSurface. + */ + if (pSwapGroup->nMembers == 0) { + /* + * pendingJoin should only be true if a client joins a + * pDeferredRequestFifo to a SwapGroup while a SwapGroup flip is + * pending on any SwapGroup that is being joined as part of this + * collective join; in that case, there must already be at least + * one fifo joined to each SwapGroup this client is joining, or we + * may do a headsurface transition with a SwapGroup flip pending. + */ + nvAssert(!pendingJoin); + + if (!HsSwapGroupUpdateHeadSurfaceNeeded(pDevEvo, pSwapGroup, TRUE)) { + goto fail; + } + + /* + * Keep track of all the swapgroups which have successfully caused + * a headsurface transition, so we can disable headsurface on them + * if we fail to enable headsurface on a subsequent entry. + */ + joinSwapGroupWorkArea[i].enabledHeadSurface = TRUE; + } + + /* This should only be called if a swap group hasn't been zombified. */ + nvAssert(!pSwapGroup->zombie); + + pSwapGroup->nMembers++; + + nvkms_memset(&pDeferredRequestFifo->swapGroup, 0, + sizeof(pDeferredRequestFifo->swapGroup)); + + if (pendingJoin) { + pDeferredRequestFifo->swapGroup.pendingJoined = TRUE; + pSwapGroup->nMembersPendingJoined++; + } + + pDeferredRequestFifo->swapGroup.pSwapGroup = pSwapGroup; + pDeferredRequestFifo->swapGroup.semaphoreIndex = INVALID_SEMAPHORE_INDEX; + + nvListAppend(&pDeferredRequestFifo->swapGroup.deferredRequestFifoListEntry, + &pSwapGroup->deferredRequestFifoList); + } + + return TRUE; + +fail: + /* + * Enabling headsurface for one of the swapgroups in this request failed; + * undo any successful headsurface enablements that happened earlier. + */ + for (i = 0; i < numHandles; i++) { + if (joinSwapGroupWorkArea[i].enabledHeadSurface) { + NVDevEvoPtr pDevEvo = joinSwapGroupWorkArea[i].pDevEvo; + NVSwapGroupRec *pSwapGroup = joinSwapGroupWorkArea[i].pSwapGroup; + if (!HsSwapGroupUpdateHeadSurfaceNeeded(pDevEvo, pSwapGroup, FALSE)) { + nvAssert(!"Failed nvHsJoinSwapGroup cleanup."); + } + } + } + + return FALSE; +} + + +/*! + * Remove the pDeferredRequestFifo from the SwapGroup. + */ +void nvHsLeaveSwapGroup( + NVDevEvoPtr pDevEvo, + NVDeferredRequestFifoRec *pDeferredRequestFifo, + NvBool teardown) +{ + NVSwapGroupRec *pSwapGroup = pDeferredRequestFifo->swapGroup.pSwapGroup; + NvBool removingReadyFifo = FALSE; + + if (pSwapGroup == NULL) { + return; + } + + /* This should only be called if a swap group hasn't been zombified. */ + nvAssert(!pSwapGroup->zombie); + + /* + * If the last member of the SwapGroup is leaving, change the "needed" state + * of headSurface. + */ + if (pSwapGroup->nMembers == 1) { + if (!HsSwapGroupUpdateHeadSurfaceNeeded(pDevEvo, pSwapGroup, FALSE)) { + nvAssert(!"Failed to transition out of headSurface"); + /* XXX NVKMS HEADSURFACE TODO: we need to do something here... */ + } + } + + nvListDel(&pDeferredRequestFifo->swapGroup.deferredRequestFifoListEntry); + pDeferredRequestFifo->swapGroup.pSwapGroup = NULL; + + nvRemoveUnicastEvent(pDeferredRequestFifo->swapGroup.pOpenUnicastEvent); + + if (pDeferredRequestFifo->swapGroup.ready) { + nvAssert(pSwapGroup->nMembersReady > 0); + removingReadyFifo = TRUE; + pSwapGroup->nMembersReady--; + } + + nvAssert(pSwapGroup->nMembers > 0); + pSwapGroup->nMembers--; + + /* + * Release the SwapGroup if this member was the only unready member of the + * SwapGroup. + * + * We only want to do this if we're not in the process of removing + * every member from the swap group (i.e. while the swap group is being + * freed), since this may trigger a flip depending on the order in which + * the deferred request fifos leave the swap group if some members are + * ready and some aren't. + * + * In addition, we only want to do this if the member we're removing was + * the last member preventing the SwapGroup from flipping; otherwise, we + * may kick off a redundant flip here if a member leaves between the swap + * group kicking off a flip and a subsequent vblank or headsurface + * transition releasing the swapgroup. + */ + if (!teardown && !removingReadyFifo && (pSwapGroup->nMembers != 0)) { + if (SwapGroupIsReady(pSwapGroup)) { + FlipSwapGroup(pDevEvo, pSwapGroup); + } + } +} + + +/*! + * Update the clip list of the SwapGroup. + * + * \param[in] pDevEvo The device the SwapGroup is on. + * \param[in] pSwapGroup The SwapGroup to modify. + * \param[in] nClips The number of NvKmsRects in pClipList. + * \param[in] pClipList The array of NvKmsRects. This is dynamically + * allocated by the caller. + * + * \return Return whether the clip list was updated. If this returns TRUE, + * then pSwapGroup takes responsibility for freeing pClipList (either + * when the next clip list update occurs, or when freeing the + * pSwapGroup). + */ +NvBool nvHsSetSwapGroupClipList( + NVDevEvoPtr pDevEvo, + NVSwapGroupRec *pSwapGroup, + const NvU16 nClips, + struct NvKmsRect *pClipList) +{ + NvU16 i; + + /* + * TODO: + * + * - If clip list is transitioning from empty to non-empty, allocate + * headSurface SwapGroup resources. + * + * - If clip list is transitioning from non-empty to empty, free headSurface + * SwapGroup resources. + */ + + /* Reject the clip list if any of rects overflow NvU16. */ + + for (i = 0; i < nClips; i++) { + + if (A_plus_B_greater_than_C_U16(pClipList[i].x, + pClipList[i].width, + NV_U16_MAX)) { + return FALSE; + } + + if (A_plus_B_greater_than_C_U16(pClipList[i].y, + pClipList[i].height, + NV_U16_MAX)) { + return FALSE; + } + } + + nvFree(pSwapGroup->pClipList); + + pSwapGroup->pClipList = pClipList; + pSwapGroup->nClips = nClips; + + /* The cliplists we receive here originate straight from + * UpdateSwapGroupClipList() in nvx_clip.c. The clips are exclusive in + * nature, i.e. they describe areas without swapgroup content. The + * cliplists come constructed depending on the screen content as + * follows: + * + * 1) No swapgroup content at all: NULL cliplist + * 2) Swapgroup and non-swapgroup content: cliplist contains regions + * covering all the non-swapgroup areas + * 3) Only swapgroup content: a cliplist of length 1 containing an empty + * clip region. This is what we detect and cache here. + */ + pSwapGroup->swapGroupIsFullscreen = (pSwapGroup->nClips == 1 && + pSwapGroup->pClipList[0].x == 0 && + pSwapGroup->pClipList[0].y == 0 && + pSwapGroup->pClipList[0].width == 0 && + pSwapGroup->pClipList[0].height == 0); + + return TRUE; +} + + +/*! + * Mark the pDeferredRequestFifo SwapGroup member as ready. + */ +void nvHsSwapGroupReady( + NVDevEvoPtr pDevEvo, + NVDeferredRequestFifoRec *pDeferredRequestFifo, + const NvU32 request) +{ + const NvU32 semaphoreIndex = + DRF_VAL(KMS, _DEFERRED_REQUEST, _SEMAPHORE_INDEX, request); + const NvU32 perEyeStereo = + DRF_VAL(KMS, _DEFERRED_REQUEST, + _SWAP_GROUP_READY_PER_EYE_STEREO, request); + + NVSwapGroupRec *pSwapGroup = pDeferredRequestFifo->swapGroup.pSwapGroup; + + if (semaphoreIndex >= NVKMS_MAX_DEFERRED_REQUESTS) { + return; + } + + /* + * Duplicate execution of a deferred request fifo entry likely indicates + * a poorly behaved client, so assert that this semaphore index hasn't + * transitioned yet. + */ + nvAssert(pDeferredRequestFifo->fifo->semaphore[semaphoreIndex].data[0] != + NVKMS_DEFERRED_REQUEST_SEMAPHORE_VALUE_SWAP_GROUP_READY); + + pDeferredRequestFifo->swapGroup.semaphoreIndex = semaphoreIndex; + + if (pDeferredRequestFifo->swapGroup.pendingJoined) { + /* + * This deferred request fifo joined and was marked ready between its + * swap group kicking off a flip and that flip completing. Mark it + * as pendingReady now, and it will be promoted to ready once the + * swap group is released. + */ + pDeferredRequestFifo->swapGroup.pendingReady = TRUE; + return; + } + + pDeferredRequestFifo->swapGroup.ready = TRUE; + pDeferredRequestFifo->swapGroup.perEyeStereo = + perEyeStereo == NVKMS_DEFERRED_REQUEST_SWAP_GROUP_READY_PER_EYE_STEREO_PER_EYE; + + /* + * This may be called if a deferred request fifo entry is being processed + * after its associated swap group has been freed, in which case, + * pDeferredRequestFifo->swapGroup.pSwapGroup will be NULL and we should + * release the deferred request fifo. + */ + if (pSwapGroup == NULL) { + ReleaseDeferredRequestFifo(pDeferredRequestFifo); + return; + } + + nvAssert(pSwapGroup->nMembersReady < NV_U32_MAX); + pSwapGroup->nMembersReady++; + nvAssert(pSwapGroup->nMembersReady <= pSwapGroup->nMembers); + + /* Kick off a SwapGroup flip when all members are ready. */ + if (SwapGroupIsReady(pSwapGroup)) { + FlipSwapGroup(pDevEvo, pSwapGroup); + } +} + +/*! + * Return the reconciled perEyeStereo setting across all deferred request fifos + * joined to this SwapGroup. + * + * If any deferred request fifo wants per-eye presentation (perEyeStereo == + * TRUE), return TRUE for the entire SwapGroup. Otherwise, return FALSE (i.e., + * per-pair presentation). + */ +NvBool nvHsSwapGroupGetPerEyeStereo( + const NVSwapGroupRec *pSwapGroup) +{ + const NVDeferredRequestFifoRec *pDeferredRequestFifo; + + FOR_ALL_DEFERRED_REQUEST_FIFOS_IN_SWAP_GROUP(pSwapGroup, + pDeferredRequestFifo) { + if (pDeferredRequestFifo->swapGroup.perEyeStereo) { + return TRUE; + } + } + + return FALSE; +} diff --git a/src/nvidia-modeset/src/nvkms-headsurface.c b/src/nvidia-modeset/src/nvkms-headsurface.c new file mode 100644 index 000000000..c64209f8b --- /dev/null +++ b/src/nvidia-modeset/src/nvkms-headsurface.c @@ -0,0 +1,2891 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvkms-types.h" +#include "nvkms-headsurface.h" +#include "nvkms-headsurface-3d.h" +#include "nvkms-headsurface-priv.h" +#include "nvkms-headsurface-swapgroup.h" +#include "nvkms-utils.h" +#include "nvkms-rmapi.h" +#include "nvkms-surface.h" +#include "nvkms-sync.h" +#include "nvkms-flip.h" +#include "nvkms-private.h" +#include "nvkms-evo.h" +#include "nvkms-dma.h" +#include "nvkms-modeset.h" +#include "nvkms-rm.h" + +#include /* NV01_MEMORY_LOCAL_USER */ + +static NvBool AllocNotifiers(NVHsDeviceEvoRec *pHsDevice); +static void FreeNotifiers(NVHsDeviceEvoRec *pHsDevice); +static void HsProcFsRecordFullscreenSgFrames(NVHsChannelEvoPtr pHsChannel, + NvBool isFullscreen); + +static NvU32 GetLog2GobsPerBlockY(NvU32 height) +{ + NvU32 log2GobsPerBlockY = 4; // 16 gobs/block + + const NvU64 heightAndOneHalf = (NvU64)height + ((NvU64)height/2ULL); + const NvU64 nvFermiBlockLinearGobHeight = NVKMS_BLOCK_LINEAR_GOB_HEIGHT; + + // If we're wasting too much memory, cap the block height + while ((log2GobsPerBlockY > 0U) && + (((nvFermiBlockLinearGobHeight * ((NvU64)1ULL << log2GobsPerBlockY))) > + heightAndOneHalf)) { + log2GobsPerBlockY--; + } + + // If there is more than one gob per block, + if (log2GobsPerBlockY > 0U) { + + // Proposed shrunk block size. + // compute a new proposedBlockSize, based on a gob size that is half + // of the current value (log2 - 1). the "if(log2 > 0)" above keeps this + // value always ">= 0". + NvU32 proposedBlockSize = + NVKMS_BLOCK_LINEAR_GOB_HEIGHT << (log2GobsPerBlockY - 1U); + + // While the proposedBlockSize is greater than the image size, + while (proposedBlockSize >= height) { + // It's safe to cut the gobs per block in half. + --log2GobsPerBlockY; + + // If we've hit 1 gob per block, stop. + if (log2GobsPerBlockY == 0U) { + break; + } + // Otherwise, divide the proposed block dimension/size by two. + proposedBlockSize /= 2U; + } + } + + return log2GobsPerBlockY; +} + +static void GetLog2GobsPerBlock( + NvU32 bytesPerPixel, + NvU32 widthInPixels, + NvU32 heightInPixels, + NvU32 *pLog2GobsPerBlockY, + NvU32 *pitchInBlocks, + NvU64 *sizeInBytes) +{ + NvU32 xAlign, yAlign, pitchInBytes, lines; + + NvU32 log2GobsPerBlockY = GetLog2GobsPerBlockY(heightInPixels); + + xAlign = NVKMS_BLOCK_LINEAR_GOB_WIDTH - 1; + yAlign = (NVKMS_BLOCK_LINEAR_GOB_HEIGHT << log2GobsPerBlockY) - 1; + + pitchInBytes = NV_ALIGN_UP(widthInPixels * bytesPerPixel, xAlign); + lines = NV_ALIGN_UP(heightInPixels, yAlign); + + *pLog2GobsPerBlockY = log2GobsPerBlockY; + *sizeInBytes = (NvU64)pitchInBytes * lines; + *pitchInBlocks = pitchInBytes / NVKMS_BLOCK_LINEAR_GOB_WIDTH; +} + +static NvU32 AllocSurfaceVidmem( + const NVDevEvoRec *pDevEvo, + NvU32 handle, + NvU64 sizeInBytes) +{ + NV_MEMORY_ALLOCATION_PARAMS memAllocParams = { }; + + memAllocParams.owner = NVKMS_RM_HEAP_ID; + memAllocParams.size = sizeInBytes; + memAllocParams.type = NVOS32_TYPE_IMAGE; + + memAllocParams.attr = DRF_DEF(OS32, _ATTR, _LOCATION, _VIDMEM) | + DRF_DEF(OS32, _ATTR, _PHYSICALITY, _CONTIGUOUS) | + DRF_DEF(OS32, _ATTR, _FORMAT, _BLOCK_LINEAR); + + memAllocParams.attr2 = DRF_DEF(OS32, _ATTR2, _GPU_CACHEABLE, _DEFAULT); + + memAllocParams.flags = NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_DOWN | + NVOS32_ALLOC_FLAGS_ALIGNMENT_FORCE; + + memAllocParams.alignment = NV_EVO_SURFACE_ALIGNMENT; + + return nvRmApiAlloc(nvEvoGlobal.clientHandle, + pDevEvo->deviceHandle, + handle, + NV01_MEMORY_LOCAL_USER, + &memAllocParams); +} + +NvU64 nvHsMapSurfaceToDevice( + const NVDevEvoRec *pDevEvo, + const NvU32 rmHandle, + const NvU64 sizeInBytes, + const enum NvHsMapPermissions hsMapPermissions) +{ + NvU32 ret; + NvU32 flags = DRF_DEF(OS46, _FLAGS, _CACHE_SNOOP, _ENABLE); + NvU64 gpuAddress = 0; + + /* pHsDevice could be NULL if we are in no3d mode. */ + + if (pDevEvo->pHsDevice == NULL) { + return gpuAddress; + } + + switch (hsMapPermissions) { + case NvHsMapPermissionsNone: + return gpuAddress; + case NvHsMapPermissionsReadWrite: + flags |= DRF_DEF(OS46, _FLAGS, _ACCESS, _READ_WRITE); + break; + case NvHsMapPermissionsReadOnly: + flags |= DRF_DEF(OS46, _FLAGS, _ACCESS, _READ_ONLY); + break; + } + + ret = nvRmApiMapMemoryDma(nvEvoGlobal.clientHandle, + pDevEvo->deviceHandle, + pDevEvo->nvkmsGpuVASpace, + rmHandle, + 0, /* offset */ + sizeInBytes, + flags, + &gpuAddress); + + if (ret == NVOS_STATUS_SUCCESS) { + return gpuAddress; + } else { + return NV_HS_BAD_GPU_ADDRESS; + } +} + +void nvHsUnmapSurfaceFromDevice( + const NVDevEvoRec *pDevEvo, + const NvU32 rmHandle, + const NvU64 gpuAddress) +{ + if ((gpuAddress == 0) || (gpuAddress == NV_HS_BAD_GPU_ADDRESS)) { + return; + } + + if (pDevEvo->pHsDevice == NULL) { + return; + } + + nvRmApiUnmapMemoryDma(nvEvoGlobal.clientHandle, + pDevEvo->deviceHandle, + pDevEvo->nvkmsGpuVASpace, + rmHandle, + 0, /* flags */ + gpuAddress); +} + +/*! + * Free an NVHsSurfaceRec, allocated by nvHsAllocSurface(). + * + * \param[in] pDevEvo The device. + * \param[in] pHsSurface The NVHsSurfaceRec to free. + */ +void nvHsFreeSurface( + NVDevEvoRec *pDevEvo, + NVHsSurfaceRec *pHsSurface) +{ + if (pHsSurface == NULL) { + return; + } + + if (pHsSurface->rmHandle != 0) { + nvRmApiFree(nvEvoGlobal.clientHandle, + pDevEvo->deviceHandle, + pHsSurface->rmHandle); + + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, pHsSurface->rmHandle); + pHsSurface->rmHandle = 0; + } + + if (pHsSurface->nvKmsHandle != 0) { + nvEvoUnregisterSurface(pDevEvo, + pDevEvo->pNvKmsOpenDev, + pHsSurface->nvKmsHandle, + FALSE /* skipUpdate */); + } + + nvFree(pHsSurface); +} + +NVSurfaceEvoRec *nvHsGetNvKmsSurface(const NVDevEvoRec *pDevEvo, + NvKmsSurfaceHandle surfaceHandle, + const NvBool requireCtxDma) +{ + const NVEvoApiHandlesRec *pNvKmsOpenDevSurfaceHandles; + NVSurfaceEvoRec *pKmsSurface; + + pNvKmsOpenDevSurfaceHandles = + nvGetSurfaceHandlesFromOpenDevConst(pDevEvo->pNvKmsOpenDev); + + nvAssert(pNvKmsOpenDevSurfaceHandles != NULL); + + pKmsSurface = + nvEvoGetSurfaceFromHandleNoCtxDmaOk(pDevEvo, + pNvKmsOpenDevSurfaceHandles, + surfaceHandle); + nvAssert(pKmsSurface != NULL); + nvAssert(pKmsSurface->requireCtxDma == requireCtxDma); + + return pKmsSurface; +} + +/*! + * Allocate an NVHsSurfaceRec, for use with headSurface. + * + * Video memory is allocated, mapped into the device's GPU virtual address + * space, and registered with NVKMS's pNvKmsOpenDev. + * + * Note the video memory is not cleared here, because the corresponding graphics + * channel may not be allocated, yet. + * + * \param[in] pDevEvo The device. + * \param[in] requireCtxDma Whether display hardware requires access. + * \param[in] format The format of the surface. + * \param[in] widthInPixels The width of the surface, in pixels. + * \param[in] heightInPixels The height of the surface, in pixels. + * + * \return On success, an allocate NVHsSurfaceRec structure is returned. + * On failure, NULL is returned. + */ +NVHsSurfaceRec *nvHsAllocSurface( + NVDevEvoRec *pDevEvo, + const NvBool requireCtxDma, + const enum NvKmsSurfaceMemoryFormat format, + const NvU32 widthInPixels, + const NvU32 heightInPixels) +{ + struct NvKmsRegisterSurfaceParams nvKmsParams = { }; + const NvKmsSurfaceMemoryFormatInfo *pFormatInfo = + nvKmsGetSurfaceMemoryFormatInfo(format); + NvU32 pitchInBlocks = 0; + NvU64 sizeInBytes = 0; + NvU32 log2GobsPerBlockY = 0; + NvU32 ret = 0; + NVHsSurfaceRec *pHsSurface = nvCalloc(1, sizeof(*pHsSurface)); + + if (pHsSurface == NULL) { + return NULL; + } + + GetLog2GobsPerBlock(pFormatInfo->rgb.bytesPerPixel, + widthInPixels, + heightInPixels, + &log2GobsPerBlockY, + &pitchInBlocks, + &sizeInBytes); + + sizeInBytes = NV_ALIGN_UP(sizeInBytes, NV_EVO_SURFACE_ALIGNMENT); + + pHsSurface->rmHandle = nvGenerateUnixRmHandle(&pDevEvo->handleAllocator); + + if (pHsSurface->rmHandle == 0) { + goto fail; + } + + ret = AllocSurfaceVidmem(pDevEvo, pHsSurface->rmHandle, sizeInBytes); + + if (ret != NVOS_STATUS_SUCCESS) { + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, pHsSurface->rmHandle); + pHsSurface->rmHandle = 0; + + goto fail; + } + + pHsSurface->gobsPerBlock.y = log2GobsPerBlockY; + + /* + * For blocklinear surfaces, the NVKMS pitch is in units of blocks, which + * matches what GetLog2GobsPerBlock() returned to us. + */ + nvKmsParams.request.useFd = FALSE; + nvKmsParams.request.rmClient = nvEvoGlobal.clientHandle; + nvKmsParams.request.widthInPixels = widthInPixels; + nvKmsParams.request.heightInPixels = heightInPixels; + nvKmsParams.request.layout = NvKmsSurfaceMemoryLayoutBlockLinear; + nvKmsParams.request.format = format; + nvKmsParams.request.noDisplayHardwareAccess = !requireCtxDma; + nvKmsParams.request.log2GobsPerBlockY = log2GobsPerBlockY; + + nvKmsParams.request.planes[0].u.rmObject = pHsSurface->rmHandle; + nvKmsParams.request.planes[0].pitch = pitchInBlocks; + nvKmsParams.request.planes[0].rmObjectSizeInBytes = sizeInBytes; + + nvEvoRegisterSurface(pDevEvo, pDevEvo->pNvKmsOpenDev, &nvKmsParams, + NvHsMapPermissionsReadWrite); + + if (nvKmsParams.reply.surfaceHandle == 0) { + goto fail; + } + + pHsSurface->nvKmsHandle = nvKmsParams.reply.surfaceHandle; + + pHsSurface->pSurfaceEvo = + nvHsGetNvKmsSurface(pDevEvo, pHsSurface->nvKmsHandle, requireCtxDma); + + if (pHsSurface->pSurfaceEvo == NULL) { + goto fail; + } + + return pHsSurface; + +fail: + nvHsFreeSurface(pDevEvo, pHsSurface); + + return NULL; +} + +NvBool nvHsAllocDevice( + NVDevEvoRec *pDevEvo, + const struct NvKmsAllocDeviceRequest *pRequest) +{ + NVHsDeviceEvoRec *pHsDevice; + + nvAssert(pDevEvo->pHsDevice == NULL); + + if (!pDevEvo->isHeadSurfaceSupported) { + return TRUE; + } + + if (pRequest->no3d) { + return TRUE; + } + + pHsDevice = nvCalloc(1, sizeof(*pHsDevice)); + + if (pHsDevice == NULL) { + goto fail; + } + + pDevEvo->pHsDevice = pHsDevice; + pHsDevice->pDevEvo = pDevEvo; + + nvAssert(pDevEvo->nvkmsGpuVASpace); + + if (!nvHs3dAllocDevice(pHsDevice)) { + goto fail; + } + + if (!AllocNotifiers(pHsDevice)) { + goto fail; + } + + return TRUE; + +fail: + nvHsFreeDevice(pDevEvo); + + return FALSE; +} + +void nvHsFreeDevice(NVDevEvoRec *pDevEvo) +{ + NVHsDeviceEvoRec *pHsDevice = pDevEvo->pHsDevice; + + if (pHsDevice == NULL) { + return; + } + + FreeNotifiers(pHsDevice); + + nvHs3dFreeDevice(pHsDevice); + + nvFree(pHsDevice); + + pDevEvo->pHsDevice = NULL; +} + +NVHsChannelEvoPtr nvHsAllocChannel(NVDispEvoRec *pDispEvo, NvU32 apiHead) +{ + NVHsChannelEvoRec *pHsChannel = nvCalloc(1, sizeof(*pHsChannel)); + + if (pHsChannel == NULL) { + goto fail; + } + + pHsChannel->pDispEvo = pDispEvo; + pHsChannel->apiHead = apiHead; + + if (!nvHs3dAllocChannel(pHsChannel)) { + goto fail; + } + + return pHsChannel; + +fail: + nvHsFreeChannel(pHsChannel); + + return NULL; +} + +void nvHsFreeChannel(NVHsChannelEvoPtr pHsChannel) +{ + if (pHsChannel == NULL) { + return; + } + + nvHs3dFreeChannel(pHsChannel); + + nvFree(pHsChannel); +} + +static NvU32 HsGetSemaphoreIndex( + const NVFlipNIsoSurfaceEvoHwState *pSemaSurface) +{ + const NvU32 offsetInBytes = pSemaSurface->offsetInWords * 4; + const enum NvKmsNIsoFormat format = pSemaSurface->format; + const NvU32 sizeOfSemaphore = nvKmsSizeOfSemaphore(format); + + /* + * The semaphore size must be greater than zero. Flip validation should + * prevent us from getting here with an invalid NvKmsNIsoFormat. + */ + nvAssert(sizeOfSemaphore > 0); + + /* The semaphore offset should be a multiple of the semaphore size. */ + nvAssert((offsetInBytes % sizeOfSemaphore) == 0); + + return offsetInBytes / sizeOfSemaphore; +} + +/*! + * Read the payload of the semaphore described in the pHwState. + */ +static NvU32 HsFlipQueueReadSemaphore( + const NVHsChannelEvoRec *pHsChannel, + const NVFlipNIsoSurfaceEvoHwState *pSemaSurface) +{ + const enum NvKmsNIsoFormat format = pSemaSurface->format; + const NvU32 semaphoreIndex = HsGetSemaphoreIndex(pSemaSurface); + const NvU32 sd = pHsChannel->pDispEvo->displayOwner; + const void *ptr; + struct nvKmsParsedSemaphore parsedSemaphore = { }; + + /* We should only get here if we have a valid semaphore surface. */ + nvAssert(pSemaSurface->pSurfaceEvo != NULL); + + ptr = pSemaSurface->pSurfaceEvo->cpuAddress[sd]; + + if (ptr == NULL) { + nvAssert(!"Semaphore surface without CPU mapping!"); + return 0; + } + + nvKmsParseSemaphore(format, semaphoreIndex, ptr, &parsedSemaphore); + + return parsedSemaphore.payload; +} + +/*! + * Return whether the specified pHwState is ready to flip. + */ +static NvBool HsFlipQueueEntryIsReady( + const NVHsChannelEvoRec *pHsChannel, + const NVFlipChannelEvoHwState *pHwState) +{ + const NVFlipNIsoSurfaceEvoHwState *pSemaSurface = + &pHwState->syncObject.u.semaphores.acquireSurface; + + if (pHwState->syncObject.usingSyncpt) { + return TRUE; + } + + /* + * If a semaphore surface was specified, check if the semaphore has reached + * the specified acquire value. + */ + if (pSemaSurface->pSurfaceEvo != NULL) { + const NvU32 semaphoreValue = + HsFlipQueueReadSemaphore(pHsChannel, pSemaSurface); + + if (pHsChannel->swapGroupFlipping) { + // With swap group flipping, the client semaphore should be + // written before the non-stall interrupt kicking off the flip. + nvAssert(semaphoreValue == pHwState->syncObject.u.semaphores.acquireValue); + } else { + if (semaphoreValue != pHwState->syncObject.u.semaphores.acquireValue) { + return FALSE; + } + } + } + + /* + * If a time stamp was specified for the flip, check if the time stamp has + * been satisfied. + * + * XXX NVKMS HEADSURFACE TODO: Implement time stamp flip check. + */ + + return TRUE; +} + +/*! + * Update the reference count of all the surfaces described in the pHwState. + */ +static void HsUpdateFlipQueueEntrySurfaceRefCount( + const NVFlipChannelEvoHwState *pHwState, + NvBool increase) +{ + HsChangeSurfaceFlipRefCount( + pHwState->pSurfaceEvo[NVKMS_LEFT], increase); + + HsChangeSurfaceFlipRefCount( + pHwState->pSurfaceEvo[NVKMS_RIGHT], increase); + + HsChangeSurfaceFlipRefCount( + pHwState->completionNotifier.surface.pSurfaceEvo, increase); + + if (!pHwState->syncObject.usingSyncpt) { + HsChangeSurfaceFlipRefCount( + pHwState->syncObject.u.semaphores.acquireSurface.pSurfaceEvo, increase); + + HsChangeSurfaceFlipRefCount( + pHwState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo, increase); + } +} + +/*! + * Update bookkeeping for "flipping away" from a pHwState. + */ +static void HsReleaseFlipQueueEntry( + NVDevEvoPtr pDevEvo, + NVHsChannelEvoPtr pHsChannel, + const NVFlipChannelEvoHwState *pHwState) +{ + /* + * If a semaphore surface was specified, we can now write its release value. + */ + if (!pHwState->syncObject.usingSyncpt && + pHwState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo != NULL) { + + /* + * XXX NVKMS HEADSURFACE TODO: write the timestamp in the EVO/NVDisplay + * semaphore structure, based on NvKmsNIsoFormat. The graphics channel + * doesn't support all the NvKmsNIsoFormats, so we would need to use a + * graphics channel semaphore release of STRUCTURE_SIZE = ONE_WORD with + * the timestamp as payload. It would be unfortunate to read ptimer + * registers in order to compute the payload value. + */ + + nvHs3dReleaseSemaphore(pHsChannel, + pHwState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo, + pHwState->syncObject.u.semaphores.releaseSurface.format, + pHwState->syncObject.u.semaphores.releaseSurface.offsetInWords, + pHwState->syncObject.u.semaphores.releaseValue, + TRUE /* allPreceedingReads */); + } + + /* + * HeadSurface no longer needs to read from the surfaces in pHwState; + * decrement their reference counts. + */ + HsUpdateFlipQueueEntrySurfaceRefCount(pHwState, FALSE); +} + +/*! + * "Fast forward" through flip queue entries that are ready. + * + * \param[in,out] pHsChannel The headSurface channel. + * \param[in] layer The layer of the flip queue. + * \param[in] honorIsReadyCriteria Honor the isReady check for + * flip queue entries. + * \param[in] honorMinPresentInterval Honor the minPresentInterval in + * flip queue entries. + */ +static void HsFastForwardFlipQueue( + NVHsChannelEvoPtr pHsChannel, + const NvU8 layer, + const NvBool honorIsReadyCriteria, + const NvBool honorMinPresentInterval) +{ + NVDevEvoPtr pDevEvo = pHsChannel->pDispEvo->pDevEvo; + NVListRec *pFlipQueue = &pHsChannel->flipQueue[layer].queue; + + /* + * For swapgroup flips, every flip kicked off by the client needs to result + * in a real flip in hardware, so we can't fast forward through flips here. + */ + if (pHsChannel->config.neededForSwapGroup) { + return; + } + + while (!nvListIsEmpty(pFlipQueue)) { + + NVHsChannelFlipQueueEntry *pEntry = + nvListFirstEntry(pFlipQueue, + NVHsChannelFlipQueueEntry, + flipQueueEntry); + /* + * Stop "fast forwarding" once we find a flip queue entry that is not + * ready: we must not release semaphores out of order, otherwise we + * could confuse client semaphore interlocking. + */ + if (honorIsReadyCriteria && + !HsFlipQueueEntryIsReady(pHsChannel, &pEntry->hwState)) { + break; + } + + /* + * Normally, we want to make sure that each MinPresentInterval > 0 flip + * is displayed for one frame, so we shouldn't fast forward past them. + */ + if (honorMinPresentInterval && + (pEntry->hwState.minPresentInterval != 0)) { + break; + } + + /* + * We are "flipping away" from the flip queue entry in current. Release + * it, and replace it with the entry in pEntry. + */ + + HsReleaseFlipQueueEntry(pDevEvo, pHsChannel, + &pHsChannel->flipQueue[layer].current); + + pHsChannel->flipQueue[layer].current = pEntry->hwState; + + nvListDel(&pEntry->flipQueueEntry); + nvFree(pEntry); + } +} + +/*! + * Push a new entry to the end of the headSurface channel's flip queue. + * + * \param[in,out] pHsChannel The headSurface channel. + * \param[in] layer The layer of the flip queue. + * \param[in] pHwState The hwState to be pushed on the flip queue. + */ +void nvHsPushFlipQueueEntry( + NVHsChannelEvoPtr pHsChannel, + const NvU8 layer, + const NVFlipChannelEvoHwState *pHwState) +{ + NVListRec *pFlipQueue = &pHsChannel->flipQueue[layer].queue; + NVHsChannelFlipQueueEntry *pEntry = nvCalloc(1, sizeof(*pEntry)); + + if (pEntry == NULL) { + /* + * XXX NVKMS HEADSURFACE TODO: we cannot fail at this point in the call + * chain (we've already committed to the flip). Move the nvCalloc() call + * earlier in the call chain to a point where we can fail. + */ + return; + } + + pEntry->hwState = *pHwState; + + /* Increment the ref counts on the surfaces in the flip queue entry. */ + + HsUpdateFlipQueueEntrySurfaceRefCount(&pEntry->hwState, TRUE); + + /* "Fast forward" through existing flip queue entries that are ready. */ + + HsFastForwardFlipQueue(pHsChannel, layer, + TRUE /* honorIsReadyCriteria */, + TRUE /* honorMinPresentInterval */); + + /* Append the new entry. */ + + nvListAppend(&pEntry->flipQueueEntry, pFlipQueue); +} + +/*! + * Remove the first entry in the flip queue and return it. + * + * If the first entry in the flipQueue is ready to be consumed by headSurface, + * remove it from the list and return it in the 'pHwState' argument. + * + * If this function returns TRUE, it is the caller's responsibility to + * eventually call + * + * HsUpdateFlipQueueEntrySurfaceRefCount(pHwState, FALSE) + * + * for the returned pHwState. + * + * \param[in,out] pHsChannel The headSurface channel. + * \param[in] layer The layer of the flip queue. + * \param[out] pHwState The hwState that was popped off the flip queue. + * + * \return Return TRUE if a flip queue entry was popped off the queue and + * copied into pHwState. + */ +static NvBool HsPopFlipQueueEntry( + NVHsChannelEvoPtr pHsChannel, + const NvU8 layer, + NVFlipChannelEvoHwState *pHwState) +{ + NVListRec *pFlipQueue = &pHsChannel->flipQueue[layer].queue; + NVHsChannelFlipQueueEntry *pEntry; + + if (nvListIsEmpty(pFlipQueue)) { + return FALSE; + } + + pEntry = nvListFirstEntry(pFlipQueue, + NVHsChannelFlipQueueEntry, + flipQueueEntry); + + if (!HsFlipQueueEntryIsReady(pHsChannel, &pEntry->hwState)) { + return FALSE; + } + + *pHwState = pEntry->hwState; + + nvListDel(&pEntry->flipQueueEntry); + nvFree(pEntry); + + return TRUE; +} + +/*! + * Update the current flip queue entry for a new headSurface frame. + * + * To build a new frame of headSurface, we look at the flip queue of each layer. + * If there is an entry available, we pop it off the queue and replace .current + * with the entry. + */ +static void HsUpdateFlipQueueCurrent( + NVHsChannelEvoPtr pHsChannel) +{ + NVDevEvoPtr pDevEvo = pHsChannel->pDispEvo->pDevEvo; + NvU8 layer; + + for (layer = 0; layer < ARRAY_LEN(pHsChannel->flipQueue); layer++) { + + NVFlipChannelEvoHwState newCurrent = { }; + + /* + * XXX NVKMS HEADSURFACE TODO: fast forward to the last ready flip queue + * entry. Share code with similar functionality in + * nvHsPushFlipQueueEntry(). + */ + + if (!HsPopFlipQueueEntry(pHsChannel, layer, &newCurrent)) { + continue; + } + + /* + * We have a new flip queue entry to place in current. Release the old + * current flip queue entry, and replace it with the popped entry. + */ + HsReleaseFlipQueueEntry(pDevEvo, pHsChannel, + &pHsChannel->flipQueue[layer].current); + + pHsChannel->flipQueue[layer].current = newCurrent; + } +} + +/*! + * Drain the flip queue on each layer of pHsChannel. + * + * In preparation to disable headSurface, release the flip queue entry in + * .current, as well as all entries in the queue. + */ +void nvHsDrainFlipQueue( + NVHsChannelEvoPtr pHsChannel) +{ + NVDevEvoPtr pDevEvo = pHsChannel->pDispEvo->pDevEvo; + NvU8 layer; + + for (layer = 0; layer < ARRAY_LEN(pHsChannel->flipQueue); layer++) { + NVListRec *pFlipQueue = &pHsChannel->flipQueue[layer].queue; + + HsReleaseFlipQueueEntry(pDevEvo, pHsChannel, + &pHsChannel->flipQueue[layer].current); + + nvkms_memset(&pHsChannel->flipQueue[layer].current, 0, + sizeof(pHsChannel->flipQueue[layer].current)); + + while (!nvListIsEmpty(pFlipQueue)) { + + NVHsChannelFlipQueueEntry *pEntry = + nvListFirstEntry(pFlipQueue, + NVHsChannelFlipQueueEntry, + flipQueueEntry); + + HsReleaseFlipQueueEntry(pDevEvo, pHsChannel, &pEntry->hwState); + + nvListDel(&pEntry->flipQueueEntry); + nvFree(pEntry); + } + } +} + +/*! + * Return whether all flip queues on this pHsChannel are idle. + * + * As a side effect, attempt to "fast forward" through flip queue entries, in an + * effort to make the flip queues idle. When fast forwarding, always ignore the + * client-requested minPresentInterval. Optionally (when force == TRUE), also + * ignore the "IsReady" check. + * + * This is intended to be used in two scenarios: + * + * - First, call nvHsIdleFlipQueue(force=FALSE) in a loop with all other heads + * we are trying to idle. This should allow semaphore interlocking to + * progress naturally. + * + * - If that loop times out, call nvHsIdleFlipQueue(force=TRUE), which will + * ignore the IsReady conditions and forcibly make the flip queues idle. + */ +NvBool nvHsIdleFlipQueue( + NVHsChannelEvoPtr pHsChannel, + NvBool force) +{ + const NvBool honorIsReadyCriteria = !force; + NvBool ret = TRUE; + NvU8 layer; + + for (layer = 0; layer < ARRAY_LEN(pHsChannel->flipQueue); layer++) { + + HsFastForwardFlipQueue(pHsChannel, layer, + honorIsReadyCriteria, + FALSE /* honorMinPresentInterval */); + + if (!nvListIsEmpty(&pHsChannel->flipQueue[layer].queue)) { + /* force should always result in an empty flip queue */ + nvAssert(!force); + ret = FALSE; + } + } + + return ret; +} + +/* + * We use notifiers to know when headSurface frames are presented, so that we + * don't render to the visible buffer. + */ + +static NvU32 AllocNotifierMemory( + const NVDevEvoRec *pDevEvo, + NvU32 handle) +{ + NV_MEMORY_ALLOCATION_PARAMS memAllocParams = { }; + + memAllocParams.owner = NVKMS_RM_HEAP_ID; + memAllocParams.size = NVKMS_HEAD_SURFACE_NOTIFIERS_SIZE_IN_BYTES; + memAllocParams.type = NVOS32_TYPE_DMA; + + memAllocParams.attr = DRF_DEF(OS32, _ATTR, _LOCATION, _VIDMEM) | + DRF_DEF(OS32, _ATTR, _PHYSICALITY, _CONTIGUOUS) | + DRF_DEF(OS32, _ATTR, _PAGE_SIZE, _4KB) | + DRF_DEF(OS32, _ATTR, _COHERENCY, _UNCACHED); + + memAllocParams.flags = NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_DOWN | + NVOS32_ALLOC_FLAGS_IGNORE_BANK_PLACEMENT | + NVOS32_ALLOC_FLAGS_FORCE_ALIGN_HOST_PAGE; + + memAllocParams.attr2 = DRF_DEF(OS32, _ATTR2, _ISO, _NO); + + return nvRmApiAlloc(nvEvoGlobal.clientHandle, + pDevEvo->deviceHandle, + handle, + NV01_MEMORY_LOCAL_USER, + &memAllocParams); +} + +static NvBool MapNotifiers(NVHsDeviceEvoRec *pHsDevice) +{ + NVDevEvoRec *pDevEvo = pHsDevice->pDevEvo; + NVHsNotifiersRec *pNotifiers = &pHsDevice->notifiers; + const NvU64 size = NVKMS_HEAD_SURFACE_NOTIFIERS_SIZE_IN_BYTES; + NvU32 sd, ret; + + for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { + ret = nvRmApiMapMemory(nvEvoGlobal.clientHandle, + pDevEvo->pSubDevices[sd]->handle, + pNotifiers->rmHandle, + 0, + size, + (void **)&pNotifiers->sd[sd].ptr, + 0); + if (ret != NVOS_STATUS_SUCCESS) { + return FALSE; + } + + /* + * Intentionally use NVMISC_MEMSET() rather than nvkms_memset(): some + * CPU architectures, notably ARM, may fault if streaming stores like in + * an optimized memset() implementation are used on a BAR1 mapping. + * NVMISC_MEMSET() is conveniently not optimized. + */ + NVMISC_MEMSET((void *)pNotifiers->sd[sd].ptr, 0, size); + } + + return TRUE; +} + +static void UnmapNotifiers(NVHsDeviceEvoRec *pHsDevice) +{ + NVDevEvoRec *pDevEvo = pHsDevice->pDevEvo; + NVHsNotifiersRec *pNotifiers = &pHsDevice->notifiers; + NvU32 sd; + + if (pNotifiers->rmHandle == 0) { + return; + } + + for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { + + if (pNotifiers->sd[sd].ptr == NULL) { + continue; + } + + nvRmApiUnmapMemory(nvEvoGlobal.clientHandle, + pDevEvo->pSubDevices[sd]->handle, + pNotifiers->rmHandle, + pNotifiers->sd[sd].ptr, + 0); + + pNotifiers->sd[sd].ptr = NULL; + } +} + +static NvBool RegisterNotifiersWithNvKms(NVHsDeviceEvoRec *pHsDevice) +{ + struct NvKmsRegisterSurfaceParams params = { }; + NVHsNotifiersRec *pNotifiers = &pHsDevice->notifiers; + NVDevEvoRec *pDevEvo = pHsDevice->pDevEvo; + const NvBool requireCtxDma = TRUE; + + params.request.useFd = FALSE; + params.request.rmClient = nvEvoGlobal.clientHandle; + + params.request.layout = NvKmsSurfaceMemoryLayoutPitch; + params.request.format = NvKmsSurfaceMemoryFormatI8; + + params.request.isoType = NVKMS_MEMORY_NISO; + + params.request.planes[0].u.rmObject = pNotifiers->rmHandle; + params.request.planes[0].pitch = NVKMS_HEAD_SURFACE_NOTIFIERS_SIZE_IN_BYTES; + params.request.planes[0].rmObjectSizeInBytes = + NVKMS_HEAD_SURFACE_NOTIFIERS_SIZE_IN_BYTES; + + nvEvoRegisterSurface(pDevEvo, pDevEvo->pNvKmsOpenDev, ¶ms, + NvHsMapPermissionsReadWrite); + + pHsDevice->notifiers.nvKmsHandle = params.reply.surfaceHandle; + + if (pHsDevice->notifiers.nvKmsHandle == 0) { + return FALSE; + } + + pHsDevice->notifiers.pSurfaceEvo = + nvHsGetNvKmsSurface(pDevEvo, + pHsDevice->notifiers.nvKmsHandle, + requireCtxDma); + + return (pHsDevice->notifiers.pSurfaceEvo != NULL); +} + +static void AssignNIsoFormat(NVHsDeviceEvoRec *pHsDevice) +{ + const NVDevEvoRec *pDevEvo = pHsDevice->pDevEvo; + + if (pDevEvo->caps.validNIsoFormatMask & + NVBIT(NVKMS_NISO_FORMAT_FOUR_WORD_NVDISPLAY)) { + /* If available, use the "nvdisplay" format. */ + pHsDevice->notifiers.nIsoFormat = NVKMS_NISO_FORMAT_FOUR_WORD_NVDISPLAY; + } else { + /* Otherwise, use the "legacy" format. */ + nvAssert((pDevEvo->caps.validNIsoFormatMask & + NVBIT(NVKMS_NISO_FORMAT_LEGACY)) != 0); + pHsDevice->notifiers.nIsoFormat = NVKMS_NISO_FORMAT_LEGACY; + } +} + +static NvBool AllocNotifiers(NVHsDeviceEvoRec *pHsDevice) +{ + NvU32 ret; + NVDevEvoRec *pDevEvo; + + pDevEvo = pHsDevice->pDevEvo; + + pHsDevice->notifiers.rmHandle = nvGenerateUnixRmHandle(&pDevEvo->handleAllocator); + + if (pHsDevice->notifiers.rmHandle == 0) { + goto fail; + } + + ret = AllocNotifierMemory(pHsDevice->pDevEvo, pHsDevice->notifiers.rmHandle); + + if (ret != NVOS_STATUS_SUCCESS) { + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, + pHsDevice->notifiers.rmHandle); + pHsDevice->notifiers.rmHandle = 0; + + goto fail; + } + + if (!MapNotifiers(pHsDevice)) { + goto fail; + } + + if (!RegisterNotifiersWithNvKms(pHsDevice)) { + goto fail; + } + + AssignNIsoFormat(pHsDevice); + + return TRUE; + +fail: + FreeNotifiers(pHsDevice); + + return FALSE; +} + +static void FreeNotifiers(NVHsDeviceEvoRec *pHsDevice) +{ + NVDevEvoRec *pDevEvo; + NVHsNotifiersRec *pNotifiers; + + if (pHsDevice == NULL) { + return; + } + + pDevEvo = pHsDevice->pDevEvo; + pNotifiers = &pHsDevice->notifiers; + + if (pNotifiers->nvKmsHandle != 0) { + nvEvoUnregisterSurface(pDevEvo, + pDevEvo->pNvKmsOpenDev, + pNotifiers->nvKmsHandle, + FALSE /* skipUpdate */); + pNotifiers->pSurfaceEvo = NULL; + } + + UnmapNotifiers(pHsDevice); + + if (pHsDevice->notifiers.rmHandle != 0) { + nvRmApiFree(nvEvoGlobal.clientHandle, + pDevEvo->deviceHandle, + pHsDevice->notifiers.rmHandle); + + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, + pHsDevice->notifiers.rmHandle); + pHsDevice->notifiers.rmHandle = 0; + } +} + +/*! + * Reset headSurface notifiers for this channel to NOT_BEGUN. + * + * By the time the modeset completes to transition into a new headSurface + * configuration, all headSurface flips from the previous completion should be + * completed. But, that would leave at least one notifier set to FINISHED. + * + * Initialize all notifiers for this channel to NOT_BEGUN, so that + * HsVBlankCallbackDeferredWork() does not interpret notifier state from the + * previous headSurface configuration as applying to the new headSurface + * configuration. + */ +static void HsInitNotifiers( + NVHsDeviceEvoRec *pHsDevice, + NVHsChannelEvoRec *pHsChannel) +{ + const NvU32 apiHead = pHsChannel->apiHead; + const NvU32 sd = pHsChannel->pDispEvo->displayOwner; + NVHsNotifiersRec *pHsNotifiers = &pHsDevice->notifiers; + NVHsNotifiersOneSdRec *pHsNotifiersOneSd = pHsNotifiers->sd[sd].ptr; + NvU8 slot, buffer; + + for (slot = 0; slot < NVKMS_HEAD_SURFACE_MAX_NOTIFIERS_PER_HEAD; slot++) { + nvKmsResetNotifier(pHsNotifiers->nIsoFormat, + FALSE /* overlay */, + slot, + pHsNotifiersOneSd->notifier[apiHead]); + } + + for (buffer = 0; buffer < NVKMS_HEAD_SURFACE_MAX_BUFFERS; buffer++) { + nvKmsResetSemaphore(pHsNotifiers->nIsoFormat, + buffer, pHsNotifiersOneSd->semaphore[apiHead], + NVKMS_HEAD_SURFACE_FRAME_SEMAPHORE_RENDERABLE); + } +} + +void nvHsInitNotifiers( + NVHsDeviceEvoRec *pHsDevice, + NVHsChannelEvoRec *pHsChannel) +{ + if (pHsChannel->config.neededForSwapGroup) { + /* + * XXX NVKMS HEADSURFACE TODO: initialize tracking for ViewPortIn + * flips. + */ + } else { + HsInitNotifiers(pHsDevice, pHsChannel); + } +} + +/*! + * For the given head and sd, prepare the next notifier: + * + * - Look up the next notifier to use. + * - Clear that notifier to STATUS_NOT_BEGUN. + * - Update the slot bookkeeping for the (head,sd) pair. + * - Return the dword offset of the notifier. + */ +static NvU16 PrepareNextNotifier( + NVHsNotifiersRec *pHsNotifiers, + NvU32 sd, + NvU32 apiHead) +{ + const NvU32 notifierSize = + nvKmsSizeOfNotifier(pHsNotifiers->nIsoFormat, FALSE /* overlay */); + + const NvU8 nextSlot = pHsNotifiers->sd[sd].apiHead[apiHead].nextSlot; + + NVHsNotifiersOneSdRec *pHsNotifiersOneSd = pHsNotifiers->sd[sd].ptr; + + const NvU8 *headBase = pHsNotifiersOneSd->notifier[apiHead]; + + const NvU8 offsetInBytes = + (headBase - ((const NvU8 *) pHsNotifiersOneSd)) + + (notifierSize * nextSlot); + + nvAssert(notifierSize <= NVKMS_HEAD_SURFACE_MAX_NOTIFIER_SIZE); + + nvKmsResetNotifier(pHsNotifiers->nIsoFormat, FALSE /* overlay */, + nextSlot, pHsNotifiersOneSd->notifier[apiHead]); + + pHsNotifiers->sd[sd].apiHead[apiHead].nextSlot = + (nextSlot + 1) % NVKMS_HEAD_SURFACE_MAX_NOTIFIERS_PER_HEAD; + + return offsetInBytes / 4; +} + +/*! + * Helper function for nvHsFlip(); populate NvKmsFlipRequest and call + * nvFlipEvo(). + * + * \param[in,out] pHsDevice The headSurface device. + * \param[in,out] pHsChannel The headSurface channel. + * \param[in] perEyeStereoFlip Whether to flip per-eye. + * \param[in] surfaceHandles The surfaces to flip to. + * \param[in] isFirstFlip Whether this is the first flip after + * enabling headsurface. + * \param[in] allowFlipLock Whether to allow fliplock for this flip. + */ +static void HsFlipHelper( + NVHsDeviceEvoRec *pHsDevice, + NVHsChannelEvoRec *pHsChannel, + const NvBool perEyeStereoFlip, + const NvKmsSurfaceHandle surfaceHandles[NVKMS_MAX_EYES], + const NvBool isFirstFlip, + const NvBool allowFlipLock) +{ + NVDevEvoRec *pDevEvo = pHsDevice->pDevEvo; + struct NvKmsFlipRequest *pRequest; + struct NvKmsFlipParams *pFlipParams; + struct NvKmsFlipCommonParams *pParamsOneHead; + NVHsNotifiersRec *pHsNotifiers = &pHsDevice->notifiers; + const NvU32 sd = pHsChannel->pDispEvo->displayOwner; + const NvU32 apiHead = pHsChannel->apiHead; + NvBool ret; + + /* + * Use a preallocated NvKmsFlipParams, so that we don't have to allocate + * memory here (and deal with allocation failure). + */ + pFlipParams = &pHsChannel->scratchParams; + + nvkms_memset(pFlipParams, 0, sizeof(*pFlipParams)); + + pRequest = &pFlipParams->request; + + pParamsOneHead = &pRequest->sd[sd].head[apiHead]; + + pRequest->commit = NV_TRUE; + + if (isFirstFlip) { + /* + * For the first flip after enabling headsurface + * (NV_HS_NEXT_FRAME_REQUEST_TYPE_FIRST_FRAME), the old viewport + * (saved in HsConfigInitSwapGroupOneHead or HsConfigInitModesetOneHead + * and restored in HsConfigRestoreMainLayerSurface) which may specify an + * offset within a multi-head surface needs to be overridden to the + * origin for the per-head headsurface surfaces. + */ + pParamsOneHead->viewPortIn.specified = TRUE; + pParamsOneHead->viewPortIn.point.x = 0; + pParamsOneHead->viewPortIn.point.y = 0; + + pParamsOneHead->cursor.imageSpecified = TRUE; + + pParamsOneHead->cursor.positionSpecified = TRUE; + } + + pParamsOneHead->layer[NVKMS_MAIN_LAYER].surface.handle[NVKMS_LEFT] = + surfaceHandles[NVKMS_LEFT]; + pParamsOneHead->layer[NVKMS_MAIN_LAYER].surface.handle[NVKMS_RIGHT] = + surfaceHandles[NVKMS_RIGHT]; + pParamsOneHead->layer[NVKMS_MAIN_LAYER].surface.specified = TRUE; + pParamsOneHead->layer[NVKMS_MAIN_LAYER].syncObjects.val.useSyncpt = FALSE; + pParamsOneHead->layer[NVKMS_MAIN_LAYER].syncObjects.specified = TRUE; + pParamsOneHead->layer[NVKMS_MAIN_LAYER].tearing = FALSE; + pParamsOneHead->layer[NVKMS_MAIN_LAYER].perEyeStereoFlip = perEyeStereoFlip; + pParamsOneHead->layer[NVKMS_MAIN_LAYER].minPresentInterval = 1; + pParamsOneHead->layer[NVKMS_MAIN_LAYER].csc.specified = TRUE; + + /* + * XXX NVKMS HEADSURFACE TODO: Work out in which cases we should use the + * head's current CSC. + */ + pParamsOneHead->layer[NVKMS_MAIN_LAYER].csc.matrix = NVKMS_IDENTITY_CSC_MATRIX; + + pParamsOneHead->layer[NVKMS_MAIN_LAYER].completionNotifier.specified = TRUE; + + pRequest->sd[sd].requestedHeadsBitMask = NVBIT(apiHead); + + if (surfaceHandles[NVKMS_LEFT] != 0) { + NVEvoApiHandlesRec *pOpenDevSurfaceHandles = + nvGetSurfaceHandlesFromOpenDev(pDevEvo->pNvKmsOpenDev); + NVSurfaceEvoPtr pSurfaceEvo = + nvEvoGetPointerFromApiHandle(pOpenDevSurfaceHandles, surfaceHandles[NVKMS_LEFT]); + struct NvKmsSemaphore *pSema; + + pParamsOneHead->layer[NVKMS_MAIN_LAYER].completionNotifier.val.surface.surfaceHandle = + pHsNotifiers->nvKmsHandle; + pParamsOneHead->layer[NVKMS_MAIN_LAYER].completionNotifier.val.surface.format = + pHsNotifiers->nIsoFormat; + pParamsOneHead->layer[NVKMS_MAIN_LAYER].completionNotifier.val.surface.offsetInWords = + PrepareNextNotifier(pHsNotifiers, sd, apiHead); + + pParamsOneHead->layer[NVKMS_MAIN_LAYER].syncObjects.val.useSyncpt = FALSE; + pParamsOneHead->layer[NVKMS_MAIN_LAYER].syncObjects.specified = TRUE; + + pSema = &pParamsOneHead->layer[NVKMS_MAIN_LAYER].syncObjects.val.u.semaphores.acquire; + pSema->surface.surfaceHandle = pHsNotifiers->nvKmsHandle; + pSema->surface.format = pHsNotifiers->nIsoFormat; + pSema->surface.offsetInWords = + HsGetFrameSemaphoreOffsetInWords(pHsChannel); + pSema->value = NVKMS_HEAD_SURFACE_FRAME_SEMAPHORE_DISPLAYABLE; + + pParamsOneHead->layer[NVKMS_MAIN_LAYER].syncObjects.val.u.semaphores.release = + pParamsOneHead->layer[NVKMS_MAIN_LAYER].syncObjects.val.u.semaphores.acquire; + + pParamsOneHead->layer[NVKMS_MAIN_LAYER].syncObjects.val.u.semaphores.release.value = + NVKMS_HEAD_SURFACE_FRAME_SEMAPHORE_RENDERABLE; + + pParamsOneHead->layer[NVKMS_MAIN_LAYER].sizeIn.specified = TRUE; + pParamsOneHead->layer[NVKMS_MAIN_LAYER].sizeIn.val.width = + pSurfaceEvo->widthInPixels; + pParamsOneHead->layer[NVKMS_MAIN_LAYER].sizeIn.val.height = + pSurfaceEvo->heightInPixels; + + pParamsOneHead->layer[NVKMS_MAIN_LAYER].sizeOut.specified = TRUE; + pParamsOneHead->layer[NVKMS_MAIN_LAYER].sizeOut.val = + pParamsOneHead->layer[NVKMS_MAIN_LAYER].sizeIn.val; + } + + ret = nvFlipEvo(pDevEvo, + pDevEvo->pNvKmsOpenDev, + pRequest, + &pFlipParams->reply, + FALSE /* skipUpdate */, + allowFlipLock); + + if (!ret) { + nvAssert(!"headSurface flip failed?"); + } +} + +/*! + * Flip to the headSurface buffer specified by index. + * + * If pHsOneHeadAllDisps == NULL, disable headSurface by flipping to NULL. + * + * \param[in,out] pHsDevice The headSurface device. + * \param[in,out] pHsChannel The headSurface channel. + * \param[in] eyeMask The mask of which eyes to flip. + * \param[in] perEyeStereoFlip Whether to flip per-eye. + * \param[in] index Which buffer to flip to. + * \param[in] pHsOneHeadAllDisps The headSurface config. + * \param[in] isFirstFlip Whether this is the first flip after + * enabling headsurface. + * \param[in] allowFlipLock Whether to allow fliplock for this flip. + */ +void nvHsFlip( + NVHsDeviceEvoRec *pHsDevice, + NVHsChannelEvoRec *pHsChannel, + const NvU8 eyeMask, + const NvBool perEyeStereoFlip, + const NvU8 index, + const NVHsStateOneHeadAllDisps *pHsOneHeadAllDisps, + const NvBool isFirstFlip, + const NvBool allowFlipLock) +{ + NvKmsSurfaceHandle surfaceHandles[NVKMS_MAX_EYES] = { 0, 0 }; + const NvBool enable = (pHsOneHeadAllDisps != NULL); + + if (enable) { + NvU8 eye; + + for (eye = NVKMS_LEFT; eye < NVKMS_MAX_EYES; eye++) { + + const NVHsSurfaceRec *pHsSurface = + pHsOneHeadAllDisps->surfaces[eye][index].pSurface; + + if ((eyeMask & NVBIT(eye)) == 0) { + continue; + } + + nvAssert(pHsSurface != NULL); + + surfaceHandles[eye] = pHsSurface->nvKmsHandle; + nvAssert(surfaceHandles[eye] != 0); + } + } + + HsFlipHelper(pHsDevice, + pHsChannel, + perEyeStereoFlip, + surfaceHandles, + isFirstFlip, + allowFlipLock); + + if (!enable) { + /* XXX NVKMS HEADSURFACE TODO: disable stereo toggling, if necessary. */ + } +} + +/*! + * "Flip" using the core channel's ViewPortIn. + */ +static void HsFlipViewPortIn(NVHsChannelEvoPtr pHsChannel, NvU16 x, NvU16 y) +{ + const NVDispEvoRec *pDispEvo = pHsChannel->pDispEvo; + + /* + * XXX NVKMS HEADSURFACE TODO: use the panning NVKMS API request, rather + * than call the low-level SetViewportPointIn() HAL proc. But, to do that, + * we would need to make the pan request much lighter weight, so that it is + * usable for our needs here. + */ + nvApiHeadSetViewportPointIn(pDispEvo, pHsChannel->apiHead, x, y); + + /* + * XXX NVKMS HEADSURFACE TODO: Add tracking so that IsPreviousFrameDone() + * can know if this update latched. + */ +} + +static void HsPickSrcEyeAndPixelShift( + const NVHsChannelEvoRec *pHsChannel, + const NvU8 dstEye, + NvU8 *pSrcEye, + enum NvKmsPixelShiftMode *pPixelShift) +{ + if (pHsChannel->config.pixelShift == NVKMS_PIXEL_SHIFT_8K) { + + if (dstEye == NVKMS_LEFT) { + *pSrcEye = NVKMS_LEFT; + *pPixelShift = NVKMS_PIXEL_SHIFT_4K_BOTTOM_RIGHT; + } + + if (dstEye == NVKMS_RIGHT) { + *pSrcEye = NVKMS_LEFT; + *pPixelShift = NVKMS_PIXEL_SHIFT_4K_TOP_LEFT; + } + } else { + *pSrcEye = dstEye; + *pPixelShift = pHsChannel->config.pixelShift; + } +} + +/*! + * Structure to drive the behavior of nvHsNextFrame(). + */ +struct NvHsNextFrameWorkArea { + + /* + * The range of surface indices to render to. Indices here are used as the + * 'index' in NVHsStateOneHeadAllDisps::surfaces[eye][index]::pSurface. + */ + NvU8 dstBufferIndexStart; + NvU8 dstBufferIndexEnd; + + /* Whether to flip to the surface indicated by pHsChannel->nextIndex. */ + NvBool doFlipToNextIndex; + + /* Whether to allow fliplock on the flip to the next surface. */ + NvBool allowFlipLock; + + /* Whether to flip to the destRect region of the surface.*/ + NvBool doFlipToDestRect; + + /* Whether to increment nextIndex and/or nextOffset. */ + NvBool doIncrementNextIndex; + NvBool doIncrementNextOffset; + + /* + * On which dstBuffer indices to honor the SwapGroup's exclusive + * clip list. + */ + NvU8 honorSwapGroupClipListBufferMask; + + /* The region within the surface to render into. */ + struct NvKmsRect destRect; + + /* + * If perEyeStereo::override == TRUE, use perEyeStereo::value to control the + * headSurface flip. + */ + struct { + NvBool override; + NvBool value; + } perEyeStereo; +}; + +/*! + * Assign an NvHsNextFrameWorkArea structure, to drive execution of + * nvHsNextFrame(). + */ +static struct NvHsNextFrameWorkArea HsAssignNextFrameWorkArea( + const NVHsChannelEvoRec *pHsChannel, + const NvHsNextFrameRequestType requestType) +{ + struct NvHsNextFrameWorkArea workArea = { }; + NvU8 destOffset; + + if ((requestType == NV_HS_NEXT_FRAME_REQUEST_TYPE_FIRST_FRAME) || + (requestType == NV_HS_NEXT_FRAME_REQUEST_TYPE_VBLANK)) { + + /* + * The swapgroup first frame renders and flips both core and base to + * the back index double height headsurface swapgroup surface, just + * like a non-swapgroup headsurface flip. + */ + if (requestType == NV_HS_NEXT_FRAME_REQUEST_TYPE_FIRST_FRAME || + !pHsChannel->config.neededForSwapGroup) { + + /* + * In the non-SwapGroup case, headSurface should: + * - only render to the 'nextIndex' surface, + * - flip to the nextIndex surface, + * - increment nextIndex. + */ + workArea.dstBufferIndexStart = pHsChannel->nextIndex; + workArea.dstBufferIndexEnd = pHsChannel->nextIndex; + + workArea.doFlipToNextIndex = TRUE; + workArea.allowFlipLock = FALSE; + workArea.doFlipToDestRect = FALSE; + + workArea.doIncrementNextIndex = TRUE; + workArea.doIncrementNextOffset = FALSE; + + } else { + + /* + * In the SwapGroup case, headSurface should: + * - render to both surfaces, + * - flip to the nextOffset, + * - increment nextOffset. + */ + workArea.dstBufferIndexStart = 0; + workArea.dstBufferIndexEnd = NVKMS_HEAD_SURFACE_MAX_BUFFERS - 1; + + workArea.doFlipToNextIndex = FALSE; + + workArea.allowFlipLock = FALSE; + workArea.doFlipToDestRect = TRUE; + + workArea.doIncrementNextIndex = FALSE; + workArea.doIncrementNextOffset = TRUE; + + /* + * For VBLANK-initiated frames of SwapGroup headSurface, we want the + * surface indicated by pHsChannel->nextIndex to contain the new + * SwapGroup content, and the non-nextIndex surface to contain the + * old SwapGroup content. + * + * Therefore, set the non-nextIndex bit(s) in + * honorSwapGroupClipListBufferMask, so that we leave the old + * SwapGroup content in that case. In all other cases, we will get + * the new SwapGroup content. + */ + workArea.honorSwapGroupClipListBufferMask = + ~NVBIT(pHsChannel->nextIndex); + } + + } else { + /* + * SWAP_GROUP_READY-initiated headSurface frames are special: we render + * a new frame to the nextIndex surface, using the previous destRect + * (i.e., the location that ViewPortIn will use at the next vblank). + * However, the flip may take indefinitely long to arrive: it will wait + * for the rest of the SwapBarrier. That is okay, because + * nvHsNextFrame(VBLANK) calls between now and the flip actually + * occurring will keep updating both surfaces, using ViewPortIn to + * "flip" to the new content. + * + * Therefore, we do _not_ increment nextIndex here. Instead, we update + * nextIndex when we find that the flip completed. Until then, we keep + * nextIndex the same, so that nvHsNextFrame(VBLANK) frames know which + * surface should receive the new SwapGroup content. + */ + + const NVSwapGroupRec *pSwapGroup = + pHsChannel->pDispEvo->pSwapGroup[pHsChannel->apiHead]; + + nvAssert(requestType == NV_HS_NEXT_FRAME_REQUEST_TYPE_SWAP_GROUP_READY); + nvAssert(pHsChannel->config.neededForSwapGroup); + + workArea.dstBufferIndexStart = pHsChannel->nextIndex; + workArea.dstBufferIndexEnd = pHsChannel->nextIndex; + + workArea.doFlipToNextIndex = TRUE; + workArea.allowFlipLock = TRUE; + workArea.doFlipToDestRect = FALSE; + + workArea.doIncrementNextIndex = FALSE; + workArea.doIncrementNextOffset = FALSE; + + workArea.perEyeStereo.override = TRUE; + workArea.perEyeStereo.value = + nvHsSwapGroupGetPerEyeStereo(pSwapGroup); + } + + /* + * Pick the rect within the destination surface that headSurface should + * render into. + * + * For normal (!neededForSwapGroup) use, this should be simply: + * { 0, 0, frameSize.width, frameSize.height } + * When SwapGroups are enabled, the headSurface is allocated at + * double height and we alternate between + * { 0, 0, frameSize.width, frameSize.height } + * { 0, frameSize.height, frameSize.width, frameSize.height } + * And use ViewPortIn to flip to the updated half. + * + * The 'nextOffset' field tracks which half headSurface should use for the + * next frame. + * + * The exception to the above is SWAP_GROUP_READY: in that case, we will + * flip between surfaces, but not change ViewPortIn, so we want to use the + * _previous_ nextOffset value. + */ + if (requestType == NV_HS_NEXT_FRAME_REQUEST_TYPE_SWAP_GROUP_READY) { + destOffset = HsGetPreviousOffset(pHsChannel); + } else { + destOffset = pHsChannel->nextOffset; + } + + workArea.destRect.x = 0; + workArea.destRect.y = pHsChannel->config.frameSize.height * + destOffset; + workArea.destRect.width = pHsChannel->config.frameSize.width; + workArea.destRect.height = pHsChannel->config.frameSize.height; + + return workArea; +} + +/*! + * Produce the next headSurface frame. + * + * Render the frame, flip to it, and update next{Index,Offset} bookkeeping + * as necessary. + * + * \param[in,out] pHsDevice The device to render on. + * \param[in,out] pHsChannel The channel to use for rendering. + * \param[in] requestType This indicates the type of frame behavior + * desired by the caller: when FIRST_FRAME, we need + * to populate the surface in the core channel on + * pre-NVDisplay. + */ +void nvHsNextFrame( + NVHsDeviceEvoPtr pHsDevice, + NVHsChannelEvoPtr pHsChannel, + const NvHsNextFrameRequestType requestType) +{ + const NVDevEvoRec *pDevEvo = pHsDevice->pDevEvo; + const NVHsStateOneHeadAllDisps *pHsOneHeadAllDisps = + &pDevEvo->apiHeadSurfaceAllDisps[pHsChannel->apiHead]; + NvBool perEyeStereoFlip = FALSE; + NvU8 dstEye; + NvU8 eyeMask = 0; + + struct NvHsNextFrameWorkArea workArea = + HsAssignNextFrameWorkArea(pHsChannel, requestType); + + HsUpdateFlipQueueCurrent(pHsChannel); + + for (dstEye = NVKMS_LEFT; dstEye < NVKMS_MAX_EYES; dstEye++) { + + const NVSurfaceEvoRec *pSurfaceEvo[NVKMS_MAX_LAYERS_PER_HEAD]; + NvBool surfacesPresent = FALSE; + NvU8 layer, srcEye = dstEye; + NvU8 dstBufferIndex; + enum NvKmsPixelShiftMode pixelShift = pHsChannel->config.pixelShift; + NvBool ret; + + HsPickSrcEyeAndPixelShift(pHsChannel, dstEye, &srcEye, &pixelShift); + + for (layer = 0; layer < ARRAY_LEN(pHsChannel->flipQueue); layer++) { + pSurfaceEvo[layer] = + pHsChannel->flipQueue[layer].current.pSurfaceEvo[srcEye]; + + surfacesPresent = surfacesPresent || (pSurfaceEvo[layer] != NULL); + + perEyeStereoFlip = perEyeStereoFlip || + pHsChannel->flipQueue[layer].current.perEyeStereoFlip; + } + + /* + * If there are no surfaces present for this srcEye, and the dstEye is + * not LEFT, don't render it. + * + * This condition is limited to LEFT because: + * - We need to perform _a_ flip even if no source surface is provided. + * - We don't want to perform more rendering than absolutely + * unnecessarily. + */ + if (!surfacesPresent && (dstEye != NVKMS_LEFT)) { + continue; + } + + for (dstBufferIndex = workArea.dstBufferIndexStart; + dstBufferIndex <= workArea.dstBufferIndexEnd; + dstBufferIndex++) { + + NvU8 thisEyeMask = 0; + const NvBool honorSwapGroupClipList = + !!(workArea.honorSwapGroupClipListBufferMask & + NVBIT(dstBufferIndex)); + + ret = nvHs3dRenderFrame(pHsChannel, + requestType, + honorSwapGroupClipList, + dstEye, + dstBufferIndex, + pixelShift, + workArea.destRect, + pSurfaceEvo); + /* + * Record which eyes we've rendered, so that we only flip those + * eyes. + * + * In the case that we're looping over multiple buffer indices, we + * should get the same result across buffers. + */ + if (ret) { + thisEyeMask = NVBIT(dstEye); + } + + if (dstBufferIndex != workArea.dstBufferIndexStart) { + nvAssert((eyeMask & NVBIT(dstEye)) == + (thisEyeMask & NVBIT(dstEye))); + } + + eyeMask |= thisEyeMask; + } + } + + if (workArea.doFlipToNextIndex) { + + if (workArea.perEyeStereo.override) { + perEyeStereoFlip = workArea.perEyeStereo.value; + } + + nvHs3dReleaseSemaphore( + pHsChannel, + pHsDevice->notifiers.pSurfaceEvo, + pHsDevice->notifiers.nIsoFormat, + HsGetFrameSemaphoreOffsetInWords(pHsChannel), + NVKMS_HEAD_SURFACE_FRAME_SEMAPHORE_DISPLAYABLE, + FALSE /* allPreceedingReads */); + + nvHsFlip( + pHsDevice, + pHsChannel, + eyeMask, + perEyeStereoFlip, + pHsChannel->nextIndex, + pHsOneHeadAllDisps, + requestType == NV_HS_NEXT_FRAME_REQUEST_TYPE_FIRST_FRAME, + workArea.allowFlipLock); + HsIncrementFrameSemaphoreIndex(pHsChannel); + + // Record fullscreen/non-fullscreen swapgroup flip counts + const NVSwapGroupRec *pSwapGroup = + pHsChannel->pDispEvo->pSwapGroup[pHsChannel->apiHead]; + + if (pSwapGroup) { + HsProcFsRecordFullscreenSgFrames(pHsChannel, + pSwapGroup->swapGroupIsFullscreen); + } + + // Record the time of the last flip originating from client update + if (requestType == NV_HS_NEXT_FRAME_REQUEST_TYPE_SWAP_GROUP_READY) { + pHsChannel->lastHsClientFlipTimeUs = nvkms_get_usec(); + } + } + + if (workArea.doFlipToDestRect) { + // Viewport fake flips are only used in swapgroup configurations. + nvAssert(pHsChannel->config.neededForSwapGroup); + + if (pHsChannel->usingRgIntrForSwapGroups) { + nvHs3dPushPendingViewportFlip(pHsChannel); + } else { + HsFlipViewPortIn(pHsChannel, + workArea.destRect.x, workArea.destRect.y); + } + } + + if (workArea.doIncrementNextIndex) { + HsIncrementNextIndex(pHsDevice, pHsChannel); + } + + if (workArea.doIncrementNextOffset) { + HsIncrementNextOffset(pHsDevice, pHsChannel); + } +} + +/*! + * In response to a non-stall interrupt, check if a headsurface channel has + * completed a frame of non-swapgroup headsurface rendering and kick off a + * viewport flip to the offset that was used for that rendering. + */ +void nvHsProcessPendingViewportFlips(NVDevEvoPtr pDevEvo) +{ + NVDispEvoPtr pDispEvo; + NvU32 dispIndex; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + NvU32 apiHead; + for (apiHead = 0; apiHead < NVKMS_MAX_HEADS_PER_DISP; apiHead++) { + NVHsChannelEvoPtr pHsChannel = pDispEvo->pHsChannel[apiHead]; + NvU32 lastRenderedOffset; + + if (pHsChannel == NULL) { + continue; + } + + lastRenderedOffset = nvHs3dLastRenderedOffset(pHsChannel); + + /* + * If this channel is marked as having kicked off a frame of + * rendering, and the semaphore write of the render offset to + * NVKMS_HEADSURFACE_VIEWPORT_OFFSET_SEMAPHORE_INDEX has completed, + * then this channel is ready to make a viewport flip to that + * offset. + */ + if (pHsChannel->viewportFlipPending && + (lastRenderedOffset == HsGetPreviousOffset(pHsChannel))) { + + HsFlipViewPortIn(pHsChannel, 0 /* x */, + lastRenderedOffset * + pHsChannel->config.frameSize.height); + pHsChannel->viewportFlipPending = FALSE; + } + } + } +} + +/*! + * Record the current scanline, for procfs statistics reporting. + */ +static void HsProcFsRecordScanline( + const NVDispEvoRec *pDispEvo, + const NvU32 head) +{ +#if NVKMS_PROCFS_ENABLE + const NvU32 apiHead = nvHardwareHeadToApiHead(head); + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + NVHsChannelEvoRec *pHsChannel = pDispEvo->pHsChannel[apiHead]; + NvU16 scanLine = 0; + NvBool inBlankingPeriod = FALSE; + + if (pHsChannel->statistics.scanLine.pHistogram == NULL) { + return; + } + + pDevEvo->hal->GetScanLine(pDispEvo, head, &scanLine, &inBlankingPeriod); + + if (inBlankingPeriod) { + pHsChannel->statistics.scanLine.nInBlankingPeriod++; + } else { + pHsChannel->statistics.scanLine.nNotInBlankingPeriod++; + + if (scanLine <= pHsChannel->statistics.scanLine.vVisible) { + pHsChannel->statistics.scanLine.pHistogram[scanLine]++; + } else { + nvEvoLogDispDebug(pDispEvo, EVO_LOG_ERROR, + "HsProcFsRecordScanline(): scanLine (%d) > vVisible (%d)", + scanLine, pHsChannel->statistics.scanLine.vVisible); + } + } +#endif /* NVKMS_PROCFS_ENABLE */ +} + +static void HsProcFsRecordPreviousFrameNotDone( + NVHsChannelEvoPtr pHsChannel) +{ +#if NVKMS_PROCFS_ENABLE + pHsChannel->statistics.nPreviousFrameNotDone++; +#endif +} + +static void HsProcFsRecordFullscreenSgFrames( + NVHsChannelEvoPtr pHsChannel, + NvBool isFullscreen) +{ +#if NVKMS_PROCFS_ENABLE + if (isFullscreen) { + pHsChannel->statistics.nFullscreenSgFrames++; + } else { + pHsChannel->statistics.nNonFullscreenSgFrames++; + } +#endif /* NVKMS_PROCFS_ENABLE */ +} + +static void HsProcFsRecordOmittedNonSgHsUpdate( + NVHsChannelEvoPtr pHsChannel) +{ +#if NVKMS_PROCFS_ENABLE + pHsChannel->statistics.nOmittedNonSgHsUpdates++; +#endif +} + +/*! + * Determine if we've flipped to the previous frame. + * + * When we program the flip method, we reset the notifier to NOT_BEGUN, and when + * EVO peforms the flip, it changes the notifier to BEGUN. + * + * Find the notifier slot for the previous frame, parse its notifier, and return + * whether it is BEGUN. + */ +static NvBool IsPreviousFlipDone(NVHsChannelEvoPtr pHsChannel) +{ + const NVDispEvoRec *pDispEvo = pHsChannel->pDispEvo; + const NvU32 apiHead = pHsChannel->apiHead; + const NvU32 sd = pDispEvo->displayOwner; + const NVHsDeviceEvoRec *pHsDevice = pDispEvo->pDevEvo->pHsDevice; + const NVHsNotifiersRec *pHsNotifiers = &pHsDevice->notifiers; + const NVHsNotifiersOneSdRec *pHsNotifiersOneSd = pHsNotifiers->sd[sd].ptr; + const NvU8 nextSlot = pHsNotifiers->sd[sd].apiHead[apiHead].nextSlot; + struct nvKmsParsedNotifier parsed = { }; + + const NvU8 prevSlot = + A_minus_b_with_wrap_U8(nextSlot, 1, + NVKMS_HEAD_SURFACE_MAX_NOTIFIERS_PER_HEAD); + + nvKmsParseNotifier(pHsNotifiers->nIsoFormat, FALSE /* overlay */, + prevSlot, pHsNotifiersOneSd->notifier[apiHead], &parsed); + + return parsed.status == NVKMS_NOTIFIER_STATUS_BEGUN; +} + +/*! + * Determine if we've flipped to the previous frame. + */ +static NvBool IsPreviousFrameDone(NVHsChannelEvoPtr pHsChannel) +{ + if (pHsChannel->config.neededForSwapGroup) { + /* + * XXX NVKMS HEADSURFACE TODO: Somehow determine if the previous + * ViewPortIn update for this head was latched. + */ + + /* + * XXX NVKMS HEADSURFACE TODO: In the absence of a mechanism to + * determine if ViewPortIn was latched, we would normally rely on this + * callback arriving once per vblank. Unfortunately, bug 2086726 can + * cause us to get called twice per vblank. WAR this for now by + * ignoring callbacks that arrive in a very small window of the previous + * callback. + * + * Throttling is now implemented using the RG line 1 interrupt + * headsurface rendering mechanism, so this limit can be lowered once + * the old vblank-triggered viewport flipping mechanism is removed. + */ + + const NvU64 oldUSec = pHsChannel->lastCallbackUSec; + const NvU64 newUSec = nvkms_get_usec(); + + /* + * This threshold is somewhat arbitrary. In bug 2086726, we see the + * callback get called from both the ISR and the bottom half, which are + * usually within ~200 usec of each other on an idle system. There + * shouldn't be a danger of mistaking legitimate periodic callbacks with + * this small threshold: 500 usec per refresh would require a 2000 Hz + * mode. + */ + const NvU64 thresholdUSec = 500; + + nvAssert(!pHsChannel->usingRgIntrForSwapGroups); + + if ((newUSec > oldUSec) && + (newUSec - oldUSec) < thresholdUSec) { + return FALSE; + } + + pHsChannel->lastCallbackUSec = newUSec; + + return TRUE; + } else { + return IsPreviousFlipDone(pHsChannel); + } +} + +/*! + * Check if all flips completed for this SwapGroup. If so, release the + * SwapGroup. + */ +static void HsCheckSwapGroupFlipDone( + NVDevEvoPtr pDevEvo, + NVSwapGroupRec *pSwapGroup) +{ + const NVHsDeviceEvoRec *pHsDevice = pDevEvo->pHsDevice; + NVDispEvoPtr pDispEvo; + NvU32 dispIndex; + + nvAssert(pSwapGroup != NULL); + + if (!pSwapGroup->pendingFlip) { + return; + } + + /* + * Check if all active heads in the SwapGroup have completed their flips. + * If any haven't, return early. + */ + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + NvU32 apiHead; + for (apiHead = 0; apiHead < ARRAY_LEN(pDispEvo->pSwapGroup); apiHead++) { + + if (pDispEvo->pSwapGroup[apiHead] == pSwapGroup) { + + NVHsChannelEvoPtr pHsChannel = pDispEvo->pHsChannel[apiHead]; + + if (pHsChannel == NULL) { + continue; + } + + nvAssert(pHsChannel->config.neededForSwapGroup); + + if (!IsPreviousFlipDone(pHsChannel)) { + return; + } + } + } + } + + /* + * The SwapGroup is ready: increment nextIndex for all active heads, so that + * subsequent frames of headSurface render to the next buffer. + */ + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + NvU32 apiHead; + for (apiHead = 0; apiHead < ARRAY_LEN(pDispEvo->pSwapGroup); apiHead++) { + + if (pDispEvo->pSwapGroup[apiHead] == pSwapGroup) { + + NVHsChannelEvoPtr pHsChannel = pDispEvo->pHsChannel[apiHead]; + + if (pHsChannel == NULL) { + continue; + } + + nvAssert(pHsChannel->config.neededForSwapGroup); + nvAssert(IsPreviousFlipDone(pHsChannel)); + + HsIncrementNextIndex(pHsDevice, pHsChannel); + } + } + } + + /* + * The SwapGroup is ready: release all SwapGroup members so that they can + * proceed. + */ + nvHsSwapGroupRelease(pDevEvo, pSwapGroup); +} + +/* + * Called from RG line interrupt handler to determine whether rendering a + * new frame could be skipped. + */ +static NvBool HsCanOmitNonSgHsUpdate(NVHsChannelEvoPtr pHsChannel) +{ + const NVSwapGroupRec *pHeadSwapGroup = + pHsChannel->pDispEvo->pSwapGroup[pHsChannel->apiHead]; + + /* + * In the case of a fullscreen swapgroup, we can generally omit updating + * the headsurface entirely upon vblank as long as the client is + * actively rendering. All the swapgroup content has already been + * updated to the headsurface backbuffer at the client's swapbuffers + * time and there's no need to update the backbuffer again on RG line 1 + * or vblank interrupt time. + * + * There is one exception to this. If the client isn't rendering + * actively then updates to the cursor (and possibly overlays, head + * config) still require rendering an updated frame to the backbuffer. + * Thus, we will simply limit this optimization for frames that come + * within one frame time after the last recorded flip. + */ + if (pHeadSwapGroup && + pHeadSwapGroup->swapGroupIsFullscreen) { + + NvU64 nowUs = nvkms_get_usec(); + NvU64 frameTimeUs = nvEvoFrametimeUsFromTimings( + &pHsChannel->pDispEvo->apiHeadState[pHsChannel->apiHead].timings); + + if (nowUs - pHsChannel->lastHsClientFlipTimeUs < frameTimeUs) { + return NV_TRUE; + } + } + + return NV_FALSE; +} + +/*! + * Receive RG line 1 callback, in process context with nvkms_lock held. + */ +static void HsServiceRGLineInterrupt(void *dataPtr, NvU32 dataU32) +{ + NVDispEvoRec *pDispEvo = (NVDispEvoRec *)dataPtr; + NvU32 head = dataU32; + const NvU32 apiHead = nvHardwareHeadToApiHead(head); + NVHsChannelEvoPtr pHsChannel = pDispEvo->pHsChannel[apiHead]; + + /* + * The pHsChannel may have been torn down between when the callback was + * generated and when this was called. Ignore spurious callbacks. + */ + if (pHsChannel == NULL) { + return; + } + + if (pHsChannel->config.neededForSwapGroup) { + /* + * Update the non-swapgroup content on the back half of both + * headsurface surfaces, and the swapgroup content on the back half of + * the back headsurface surface, and perform a viewportoffset flip to + * the back offset. + * + * Synchronization is achieved by the following mechanism: + * + * - Before rendering a new frame, check that we aren't still scanning + * out from that half of the surface. + * - After rendering a frame, push a semaphore write with the render + * offset and a non-stall interrupt. + * - In response to the non-stall interrupt, perform the viewport + * flip to the render offset. + */ + NvU32 activeViewportOffset = + pDispEvo->pDevEvo->hal->GetActiveViewportOffset(pDispEvo, head); + + nvAssert((activeViewportOffset == 0) || + (activeViewportOffset == pHsChannel->config.frameSize.height)); + + activeViewportOffset /= pHsChannel->config.frameSize.height; + + if (activeViewportOffset == HsGetPreviousOffset(pHsChannel)) { + /* + * The active viewport is the same as the last one we pushed, so + * it's safe to start rendering to pHsChannel->nextOffset; check if + * rendering from a previous interrupt hasn't completed yet. + */ + if (pHsChannel->viewportFlipPending) { + /* + * A non-stall interrupt hasn't been triggered since we kicked + * off the previous frame's rendering. + */ + HsProcFsRecordPreviousFrameNotDone(pHsChannel); + } else { + NVHsDeviceEvoRec *pHsDevice = pDispEvo->pDevEvo->pHsDevice; + + HsProcFsRecordScanline(pDispEvo, head); + + if (HsCanOmitNonSgHsUpdate(pHsChannel)) { + HsProcFsRecordOmittedNonSgHsUpdate(pHsChannel); + } else { + nvHsNextFrame(pHsDevice, pHsChannel, NV_HS_NEXT_FRAME_REQUEST_TYPE_VBLANK); + } + } + } else { + /* + * The viewport flip we pushed after the previous frame's rendering + * hasn't been applied in hardware yet. + */ + HsProcFsRecordPreviousFrameNotDone(pHsChannel); + } + + HsCheckSwapGroupFlipDone(pDispEvo->pDevEvo, pDispEvo->pSwapGroup[apiHead]); + } +} + +/*! + * Receive vblank callback, in process context with nvkms_lock held. + * + */ +static void HsVBlankCallback(NVDispEvoRec *pDispEvo, + const NvU32 head, + NVVBlankCallbackPtr pCallbackData) +{ + const NvU32 apiHead = nvHardwareHeadToApiHead(head); + NVHsChannelEvoPtr pHsChannel = pDispEvo->pHsChannel[apiHead]; + NVHsDeviceEvoRec *pHsDevice = pDispEvo->pDevEvo->pHsDevice; + + /* + * The pHsChannel may have been torn down between when the vblank was + * generated and when this was called. Ignore spurious callbacks. + */ + if (pHsChannel == NULL) { + return; + } + + if (!pHsChannel->usingRgIntrForSwapGroups && + pHsChannel->config.neededForSwapGroup) { + HsCheckSwapGroupFlipDone(pDispEvo->pDevEvo, pDispEvo->pSwapGroup[apiHead]); + } + + if (pHsChannel->usingRgIntrForSwapGroups && + pHsChannel->config.neededForSwapGroup) { + // The next frame will be rendered during the RG line 1 interrupt. + return; + } + + /* + * If we have not flipped to the previous buffer, yet, we should not render + * to the next buffer. Wait until the next vblank callback. + */ + if (!IsPreviousFrameDone(pHsChannel)) { + HsProcFsRecordPreviousFrameNotDone(pHsChannel); + return; + } + + HsProcFsRecordScanline(pDispEvo, head); + + /* + * XXX NVKMS HEADSURFACE TODO: evaluate whether there has been + * damage to the source buffer since the last headSurface frame. + * Only if so, perform the headSurface transformation and flip to + * the resulting headSurface buffer. + * + * For headSurface bringup purposes, just always flip to the next + * headSurface buffer. + */ + + /* + * When fullscreen swapgroup flipping, we don't need to update + * non-swapgroup content at vblank. + */ + if (!pHsChannel->swapGroupFlipping) { + nvHsNextFrame(pHsDevice, pHsChannel, + NV_HS_NEXT_FRAME_REQUEST_TYPE_VBLANK); + } +} + +/*! + * Receive RG line 1 interrupt notification from resman. + * + * This function is registered as the kernel callback function from resman when + * the RG line 1 interrupt is generated. + * + * This function is called within resman's context, so we schedule a zero timer + * callback to process the swapgroup check and release without holding the + * resman lock. + */ +static void HsRGLineInterruptCallback(NvU32 rgIntrLine, void *param1, + NvBool bIsIrqlIsr /* unused */) +{ + void *pDispEvoRefPtr = (void *)((NvUPtr)param1 & + ~(NVKMS_MAX_HEADS_PER_DISP-1)); + NvU32 head = (NvUPtr)param1 & (NVKMS_MAX_HEADS_PER_DISP-1); + (void) nvkms_alloc_timer_with_ref_ptr( + HsServiceRGLineInterrupt, /* callback */ + pDispEvoRefPtr, /* ref_ptr */ + head, /* dataU32 */ + 0); /* usec */ +} + +/*! + * Schedule vblank callbacks from resman on a specific head and subdevice. + */ +void nvHsAddVBlankCallback(NVHsChannelEvoPtr pHsChannel) +{ + NVDispEvoRec *pDispEvo = pHsChannel->pDispEvo; + + pHsChannel->vBlankCallback = + nvApiHeadRegisterVBlankCallback(pDispEvo, + pHsChannel->apiHead, + HsVBlankCallback, + NULL); +} + +/*! + * Add an RG line 1 callback to check the swapgroup flip notifier and release + * its associated deferred request fifo. + * + * This is done in an RG line 1 callback instead of the vblank callback to WAR + * an issue where certain mode timings cause the vblank callback to fire + * slightly before LOADV causes the notifier to transition from NOT_BEGUN + * to BEGUN, causing an extra frame of delay before the next vblank occurs and + * the deferred request fifo can be released. + */ +void nvHsAddRgLine1Callback(NVHsChannelEvoPtr pHsChannel) +{ + const NVDispEvoRec *pDispEvo = pHsChannel->pDispEvo; + NvBool found; + NvU32 val; + + /* + * Use the RG line 1 interrupt to check swapgroup completion by default, + * but allow setting NVKMS_DELAY_SWAPGROUP_CHECK=0 by regkey to revert to + * the old method of checking during vblank for debugging purposes. + */ + found = nvGetRegkeyValue(pDispEvo->pDevEvo, "NVKMS_DELAY_SWAPGROUP_CHECK", + &val); + + if (found && (val == 0)) { + return; + } + + pHsChannel->rgIntrCallbackObjectHandle = + nvApiHeadAddRgLine1Callback(pDispEvo, + pHsChannel->apiHead, + HsRGLineInterruptCallback); + + if (pHsChannel->rgIntrCallbackObjectHandle == 0) { + nvAssert(!"Failed to register headSurface RG line 1 interrupt"); + } else { + pHsChannel->usingRgIntrForSwapGroups = TRUE; + } +} + +/*! + * Cancel RG line 1 callbacks from resman on the specified head and subdevice. + * + * The same limitations regarding leftover vblank callbacks after vblank + * callbacks are disabled in nvHsRemoveVblankCallback apply to RG callbacks. + */ +void nvHsRemoveRgLine1Callback(NVHsChannelEvoPtr pHsChannel) +{ + const NVDispEvoRec *pDispEvo = pHsChannel->pDispEvo; + + if (pHsChannel->usingRgIntrForSwapGroups) { + nvRmRemoveRgLine1Callback(pDispEvo, + pHsChannel->rgIntrCallbackObjectHandle); + pHsChannel->rgIntrCallbackObjectHandle = 0; + } +} + +/*! + * Cancel vblank callbacks from resman on the specified head and subdevice. + * + * Note that there could currently be callbacks in flight. We should be + * prepared to handle a spurious callback after cancelling the callbacks here. + * + * XXX NVKMS HEADSURFACE TODO: It would be better to: + * + * (a) Remove the vblank callback before the modeset that disables headSurface. + * (b) Drain/cancel any in flight callbacks while holding the nvkms_lock. + * + * A mechanism like that should avoid spurious callbacks. + */ +void nvHsRemoveVBlankCallback(NVHsChannelEvoPtr pHsChannel) +{ + NVDispEvoRec *pDispEvo = pHsChannel->pDispEvo; + + nvApiHeadUnregisterVBlankCallback(pDispEvo, + pHsChannel->apiHead, + pHsChannel->vBlankCallback); + pHsChannel->vBlankCallback = NULL; +} + +void nvHsAllocStatistics( + NVHsChannelEvoRec *pHsChannel) +{ +#if NVKMS_PROCFS_ENABLE + const NVDispEvoRec *pDispEvo = pHsChannel->pDispEvo; + const NvU32 apiHead = pHsChannel->apiHead; + const NVHwModeTimingsEvo *pTimings = + &pDispEvo->apiHeadState[apiHead].timings; + NvU32 n; + + nvkms_memset(&pHsChannel->statistics, 0, sizeof(pHsChannel->statistics)); + + pHsChannel->statistics.scanLine.vVisible = nvEvoVisibleHeight(pTimings); + + n = pHsChannel->statistics.scanLine.vVisible + 1; + + pHsChannel->statistics.scanLine.pHistogram = nvCalloc(1, sizeof(NvU64) * n); +#endif /* NVKMS_PROCFS_ENABLE */ +} + +void nvHsFreeStatistics( + NVHsChannelEvoRec *pHsChannel) +{ +#if NVKMS_PROCFS_ENABLE + nvFree(pHsChannel->statistics.scanLine.pHistogram); + nvkms_memset(&pHsChannel->statistics, 0, sizeof(pHsChannel->statistics)); +#endif /* NVKMS_PROCFS_ENABLE */ +} + +#if NVKMS_PROCFS_ENABLE + +static const struct { + const char *before; + const char *after; +} HsProcFsIndentTable[] = { + [0] = { .before = "", .after = " " }, + [1] = { .before = " ", .after = " " }, + [2] = { .before = " ", .after = " " }, + [3] = { .before = " ", .after = " " }, + [5] = { .before = " ", .after = "" }, +}; + +static const char *HsProcFsIndentBefore(NvU8 indent) +{ + nvAssert(indent < ARRAY_LEN(HsProcFsIndentTable)); + + return HsProcFsIndentTable[indent].before; +} + +static const char *HsProcFsIndentAfter(NvU8 indent) +{ + nvAssert(indent < ARRAY_LEN(HsProcFsIndentTable)); + + return HsProcFsIndentTable[indent].after; +} + +static void HsProcFsGpuTime( + NVEvoInfoStringRec *pInfoString, + const NvU64 nFrames, + const NvU64 gpuTimeSpent, + const NvU8 indent) +{ + /* + * Use nFrames - 1 to compute averageGpuTimeNs: the nvHs3dRenderFrame() path + * increments nFrames at the end of rendering a frame, but it only updates + * gpuTimeSpent at the start of rendering the _next_ frame. I.e., + * gpuTimeSpent has time for nFrames - 1 frames. + */ + const NvU64 averageGpuTimeNs = + (nFrames <= 1) ? 0 : (gpuTimeSpent / (nFrames - 1)); + const NvU64 averageGpuTimeUs = (averageGpuTimeNs + 500) / 1000; + const NvU64 nFramesToReport = (nFrames <= 1) ? 0 : nFrames - 1; + + nvEvoLogInfoString( + pInfoString, " %savg GPU time / frame%s : " + "%" NvU64_fmtu ".%03" NvU64_fmtu " msec " + "(%" NvU64_fmtu " nsec / %" NvU64_fmtu " frames)", + HsProcFsIndentBefore(indent), + HsProcFsIndentAfter(indent), + averageGpuTimeUs / 1000, + averageGpuTimeUs % 1000, + gpuTimeSpent, + nFramesToReport); +} + +static void HsProcFsFrameStatisticsOneEye( + NVEvoInfoStringRec *pInfoString, + const NVHsChannelEvoRec *pHsChannel, + const NvU8 eye, + const NvU8 slot, + const NvU8 indent) +{ + const NVHsChannelStatisticsOneEyeRec *pPerEye = + &pHsChannel->statistics.perEye[eye][slot]; + + const NvU64 framesPerMs = pPerEye->fps.framesPerMs; + + nvEvoLogInfoString( + pInfoString, + " %snFrames%s : %" NvU64_fmtu, + HsProcFsIndentBefore(indent), + HsProcFsIndentAfter(indent), + pPerEye->nFrames); + + nvEvoLogInfoString( + pInfoString, " %sFPS (computed every 5s)%s: " + "%" NvU64_fmtu ".%03" NvU64_fmtu, + HsProcFsIndentBefore(indent), + HsProcFsIndentAfter(indent), + framesPerMs / 1000, + framesPerMs % 1000); + + HsProcFsGpuTime( + pInfoString, + pPerEye->nFrames, + pPerEye->gpuTimeSpent, + indent); +} + +static void HsProcFsFrameStatisticsOneSlot( + NVEvoInfoStringRec *pInfoString, + const NVHsChannelEvoRec *pHsChannel, + const NvU8 slot, + const NvU8 indent) +{ + const char *eyeLabel[] = { + [NVKMS_LEFT] = "Left Eye ", + [NVKMS_RIGHT] = "Right Eye", + }; + + const NvBool needEyeLabel = + pHsChannel->statistics.perEye[NVKMS_RIGHT][slot].nFrames != 0; + NvU8 eye; + + for (eye = NVKMS_LEFT; eye < NVKMS_MAX_EYES; eye++) { + + NvU8 localIndent = 0; + + if (pHsChannel->statistics.perEye[eye][slot].nFrames == 0) { + continue; + } + + if (needEyeLabel) { + nvEvoLogInfoString( + pInfoString, " %s%s%s :", + HsProcFsIndentBefore(indent), + eyeLabel[eye], + HsProcFsIndentAfter(indent)); + localIndent++; + } + + HsProcFsFrameStatisticsOneEye( + pInfoString, + pHsChannel, + eye, + slot, + indent + localIndent); + } +} + +static void HsProcFsFrameStatistics( + NVEvoInfoStringRec *pInfoString, + const NVHsChannelEvoRec *pHsChannel) +{ + NvU8 slot; + + if (pHsChannel->config.neededForSwapGroup) { + nvEvoLogInfoString(pInfoString, + " VBLANK frames :"); + + nvEvoLogInfoString(pInfoString, + " Old swapGroup content :"); + + slot = Hs3dStatisticsGetSlot( + pHsChannel, + NV_HS_NEXT_FRAME_REQUEST_TYPE_VBLANK, 0, + TRUE /* honorSwapGroupClipList */); + + HsProcFsFrameStatisticsOneSlot(pInfoString, pHsChannel, slot, 2); + + nvEvoLogInfoString(pInfoString, + " New swapGroup content :"); + + slot = Hs3dStatisticsGetSlot( + pHsChannel, + NV_HS_NEXT_FRAME_REQUEST_TYPE_VBLANK, 0, + FALSE /* honorSwapGroupClipList */); + + HsProcFsFrameStatisticsOneSlot(pInfoString, pHsChannel, slot, 2); + + nvEvoLogInfoString(pInfoString, + " SWAP_GROUP_READY frames :"); + + slot = Hs3dStatisticsGetSlot( + pHsChannel, + NV_HS_NEXT_FRAME_REQUEST_TYPE_SWAP_GROUP_READY, 0, + FALSE /* honorSwapGroupClipList */); + + HsProcFsFrameStatisticsOneSlot(pInfoString, pHsChannel, slot, 1); + + } else { + const NvU8 indent = 0; /* start with no indentation */ + + slot = Hs3dStatisticsGetSlot( + pHsChannel, + NV_HS_NEXT_FRAME_REQUEST_TYPE_VBLANK, 0, + FALSE); + + HsProcFsFrameStatisticsOneSlot(pInfoString, pHsChannel, slot, indent); + } +} + +static void HsProcFsScanLine( + NVEvoInfoStringRec *pInfoString, + const NVHsChannelEvoRec *pHsChannel) +{ + NvU16 i; + + nvEvoLogInfoString(pInfoString, + " scanLine information :"); + + nvEvoLogInfoString(pInfoString, + " nInBlankingPeriod : %" NvU64_fmtu, + pHsChannel->statistics.scanLine.nInBlankingPeriod); + nvEvoLogInfoString(pInfoString, + " nNotInBlankingPeriod : %" NvU64_fmtu, + pHsChannel->statistics.scanLine.nNotInBlankingPeriod); + nvEvoLogInfoString(pInfoString, + " vVisible : %d", + pHsChannel->statistics.scanLine.vVisible); + + if (pHsChannel->statistics.scanLine.pHistogram == NULL) { + + nvEvoLogInfoString(pInfoString, + " scanline histogram : failed allocation"); + } else { + + nvEvoLogInfoString(pInfoString, + " scanline histogram :"); + + for (i = 0; i <= pHsChannel->statistics.scanLine.vVisible; i++) { + + if (pHsChannel->statistics.scanLine.pHistogram[i] != 0) { + nvEvoLogInfoString(pInfoString, + " scanLine[%04d] : %" NvU64_fmtu, + i, pHsChannel->statistics.scanLine.pHistogram[i]); + } + } + } +} + +static void HsProcFsFlipQueueOneEntry( + NVEvoInfoStringRec *pInfoString, + const NVFlipChannelEvoHwState *pFlipState) +{ + /* + * Print the pointers by casting to NvUPtr and formatting with NvUPtr_fmtx, + * so that NULL is printed as "0x0", rather than "(null)". + */ + + nvEvoLogInfoString(pInfoString, + " pSurfaceEvo(L,R) : 0x%" NvUPtr_fmtx ", 0x%" NvUPtr_fmtx, + (NvUPtr)pFlipState->pSurfaceEvo[NVKMS_LEFT], + (NvUPtr)pFlipState->pSurfaceEvo[NVKMS_RIGHT]); + + if (!pFlipState->syncObject.usingSyncpt) { + nvEvoLogInfoString(pInfoString, + " semaphore : " + "acquire pSurfaceEvo: 0x%" NvUPtr_fmtx ", " + "release pSurfaceEvo: 0x%" NvUPtr_fmtx ", " + "acquire value: 0x%08x, " + "release value: 0x%08x", + (NvUPtr)pFlipState->syncObject.u.semaphores.acquireSurface.pSurfaceEvo, + (NvUPtr)pFlipState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo, + pFlipState->syncObject.u.semaphores.acquireValue, + pFlipState->syncObject.u.semaphores.releaseValue); + } +} + +static void HsProcFsFlipQueue( + NVEvoInfoStringRec *pInfoString, + const NVHsChannelEvoRec *pHsChannel) +{ + const NVHsChannelFlipQueueEntry *pEntry; + NvU8 layer; + + for (layer = 0; layer < ARRAY_LEN(pHsChannel->flipQueue); layer++) { + + const char *layerString[NVKMS_MAX_LAYERS_PER_HEAD] = { + [NVKMS_MAIN_LAYER] = "(main) ", + [NVKMS_OVERLAY_LAYER] = "(overlay)", + }; + + nvEvoLogInfoString(pInfoString, + " flipQueue%s :", layerString[layer]); + + nvEvoLogInfoString(pInfoString, + " current :"); + + HsProcFsFlipQueueOneEntry(pInfoString, + &pHsChannel->flipQueue[layer].current); + + nvListForEachEntry(pEntry, + &pHsChannel->flipQueue[layer].queue, + flipQueueEntry) { + + nvEvoLogInfoString(pInfoString, + " pending :"); + + HsProcFsFlipQueueOneEntry(pInfoString, &pEntry->hwState); + } + } +} + +static const char *HsGetEyeMaskString(const NvU8 eyeMask) +{ + if (eyeMask == NVBIT(NVKMS_LEFT)) { + return "L"; + } else { + nvAssert(eyeMask == (NVBIT(NVKMS_LEFT) | NVBIT(NVKMS_RIGHT))); + return "L|R"; + } +} + +static const char *HsGetPixelShiftString( + const enum NvKmsPixelShiftMode pixelShift) +{ + switch (pixelShift) { + case NVKMS_PIXEL_SHIFT_NONE: return "none"; + case NVKMS_PIXEL_SHIFT_4K_TOP_LEFT: return "4kTopLeft"; + case NVKMS_PIXEL_SHIFT_4K_BOTTOM_RIGHT: return "4kBottomRight"; + case NVKMS_PIXEL_SHIFT_8K: return "8k"; + } + + return "unknown"; +} + +static void HsProcFsTransform( + NVEvoInfoStringRec *pInfoString, + const NVHsChannelEvoRec *pHsChannel) +{ + nvEvoLogInfoString(pInfoString, + " transform matrix : " + "{ { 0x%08x, 0x%08x, 0x%08x },", + F32viewAsNvU32(pHsChannel->config.transform.m[0][0]), + F32viewAsNvU32(pHsChannel->config.transform.m[0][1]), + F32viewAsNvU32(pHsChannel->config.transform.m[0][2])); + + nvEvoLogInfoString(pInfoString, + " : " + " { 0x%08x, 0x%08x, 0x%08x },", + F32viewAsNvU32(pHsChannel->config.transform.m[1][0]), + F32viewAsNvU32(pHsChannel->config.transform.m[1][1]), + F32viewAsNvU32(pHsChannel->config.transform.m[1][2])); + + nvEvoLogInfoString(pInfoString, + " : " + " { 0x%08x, 0x%08x, 0x%08x } }", + F32viewAsNvU32(pHsChannel->config.transform.m[2][0]), + F32viewAsNvU32(pHsChannel->config.transform.m[2][1]), + F32viewAsNvU32(pHsChannel->config.transform.m[2][2])); +} + +static void HsProcFsStaticWarpMesh( + NVEvoInfoStringRec *pInfoString, + const NVHsChannelEvoRec *pHsChannel) +{ + nvEvoLogInfoString(pInfoString, + " staticWarpMesh : " + "{ { 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x },", + pHsChannel->config.staticWarpMesh.vertex[0].x, + pHsChannel->config.staticWarpMesh.vertex[0].y, + pHsChannel->config.staticWarpMesh.vertex[0].u, + pHsChannel->config.staticWarpMesh.vertex[0].v, + pHsChannel->config.staticWarpMesh.vertex[0].r, + pHsChannel->config.staticWarpMesh.vertex[0].q); + + nvEvoLogInfoString(pInfoString, + " : " + " { 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x },", + pHsChannel->config.staticWarpMesh.vertex[1].x, + pHsChannel->config.staticWarpMesh.vertex[1].y, + pHsChannel->config.staticWarpMesh.vertex[1].u, + pHsChannel->config.staticWarpMesh.vertex[1].v, + pHsChannel->config.staticWarpMesh.vertex[1].r, + pHsChannel->config.staticWarpMesh.vertex[1].q); + + nvEvoLogInfoString(pInfoString, + " : " + " { 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x },", + pHsChannel->config.staticWarpMesh.vertex[2].x, + pHsChannel->config.staticWarpMesh.vertex[2].y, + pHsChannel->config.staticWarpMesh.vertex[2].u, + pHsChannel->config.staticWarpMesh.vertex[2].v, + pHsChannel->config.staticWarpMesh.vertex[2].r, + pHsChannel->config.staticWarpMesh.vertex[2].q); + + nvEvoLogInfoString(pInfoString, + " : " + " { 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x } }", + pHsChannel->config.staticWarpMesh.vertex[3].x, + pHsChannel->config.staticWarpMesh.vertex[3].y, + pHsChannel->config.staticWarpMesh.vertex[3].u, + pHsChannel->config.staticWarpMesh.vertex[3].v, + pHsChannel->config.staticWarpMesh.vertex[3].r, + pHsChannel->config.staticWarpMesh.vertex[3].q); +} + +static const char *HsProcFsGetNeededForString( + const NVHsChannelEvoRec *pHsChannel) +{ + if (pHsChannel->config.neededForModeset && + pHsChannel->config.neededForSwapGroup) { + return "modeset, swapgroup"; + } + + if (pHsChannel->config.neededForModeset && + !pHsChannel->config.neededForSwapGroup) { + return "modeset"; + } + + if (!pHsChannel->config.neededForModeset && + pHsChannel->config.neededForSwapGroup) { + return "swapgroup"; + } + + return "unknown"; +} + +static void HsProcFsFrameSemaphores( + NVEvoInfoStringRec *pInfoString, + const NVHsChannelEvoRec *pHsChannel) +{ + const NVDispEvoRec *pDispEvo = pHsChannel->pDispEvo; + const NVHsDeviceEvoRec *pHsDevice = pDispEvo->pDevEvo->pHsDevice; + const NvU32 sd = pDispEvo->displayOwner; + const NVHsNotifiersOneSdRec *p = pHsDevice->notifiers.sd[sd].ptr; + const NvGpuSemaphore *pSema = + (const NvGpuSemaphore *)p->semaphore[pHsChannel->apiHead]; + + NvU8 buffer; + + for (buffer = 0; buffer < NVKMS_HEAD_SURFACE_MAX_BUFFERS; buffer++) { + nvEvoLogInfoString(pInfoString, + " frameSemaphore[%d] : 0x%0x", + buffer, + pSema[buffer].data[0]); + } +} + +void nvHsProcFs( + NVEvoInfoStringRec *pInfoString, + NVDevEvoRec *pDevEvo, + NvU32 dispIndex, + NvU32 head) +{ + NVDispEvoPtr pDispEvo = pDevEvo->pDispEvo[dispIndex]; + const NvU32 apiHead = nvHardwareHeadToApiHead(head); + const NVHsChannelEvoRec *pHsChannel = pDispEvo->pHsChannel[apiHead]; + const NVHsStateOneHeadAllDisps *pHsOneHeadAllDisps = + &pDevEvo->apiHeadSurfaceAllDisps[apiHead]; + + if (pHsChannel == NULL) { + nvEvoLogInfoString(pInfoString, + " headSurface[head:%02d] : disabled", head); + return; + } + + nvEvoLogInfoString(pInfoString, + " headSurface[head:%02d] : " + "enabled (needed for: %s)", + head, HsProcFsGetNeededForString(pHsChannel)); + + HsProcFsFrameStatistics(pInfoString, pHsChannel); + + nvEvoLogInfoString(pInfoString, + " nextIndex : %d", + pHsChannel->nextIndex); + + nvEvoLogInfoString(pInfoString, + " nextOffset : %d", + pHsChannel->nextOffset); + + nvEvoLogInfoString(pInfoString, + " nPreviousFrameNotDone : %" NvU64_fmtu, + pHsChannel->statistics.nPreviousFrameNotDone); + + nvEvoLogInfoString(pInfoString, + " nOmittedNonSgHsUpdates : %" NvU64_fmtu, + pHsChannel->statistics.nOmittedNonSgHsUpdates); + + nvEvoLogInfoString(pInfoString, + " nFullscreenSgFrames : %" NvU64_fmtu, + pHsChannel->statistics.nFullscreenSgFrames); + + nvEvoLogInfoString(pInfoString, + " nNonFullscreenSgFrames : %" NvU64_fmtu, + pHsChannel->statistics.nNonFullscreenSgFrames); + + nvEvoLogInfoString(pInfoString, + " viewPortIn : %d x %d +%d +%d", + pHsChannel->config.viewPortIn.width, + pHsChannel->config.viewPortIn.height, + pHsChannel->config.viewPortIn.x, + pHsChannel->config.viewPortIn.y); + + nvEvoLogInfoString(pInfoString, + " viewPortOut : %d x %d +%d +%d", + pHsChannel->config.viewPortOut.width, + pHsChannel->config.viewPortOut.height, + pHsChannel->config.viewPortOut.x, + pHsChannel->config.viewPortOut.y); + + nvEvoLogInfoString(pInfoString, + " frameSize : %d x %d", + pHsChannel->config.frameSize.width, + pHsChannel->config.frameSize.height); + + nvEvoLogInfoString(pInfoString, + " surfaceSize : %d x %d", + pHsChannel->config.surfaceSize.width, + pHsChannel->config.surfaceSize.height); + + nvEvoLogInfoString(pInfoString, + " stagingSurfaceSize : %d x %d", + pHsChannel->config.stagingSurfaceSize.width, + pHsChannel->config.stagingSurfaceSize.height); + + nvEvoLogInfoString(pInfoString, + " allDispsSurfaceSize : %d x %d", + pHsOneHeadAllDisps->size.width, + pHsOneHeadAllDisps->size.height); + + nvEvoLogInfoString(pInfoString, + " allDispsStagingSize : %d x %d", + pHsOneHeadAllDisps->stagingSize.width, + pHsOneHeadAllDisps->stagingSize.height); + + nvEvoLogInfoString(pInfoString, + " allDispsSurfaceCount : %d", + pHsOneHeadAllDisps->surfaceCount); + + nvEvoLogInfoString(pInfoString, + " eyeMask : %s", + HsGetEyeMaskString(pHsChannel->config.eyeMask)); + + nvEvoLogInfoString(pInfoString, + " pixelShift : %s", + HsGetPixelShiftString(pHsChannel->config.pixelShift)); + + HsProcFsTransform(pInfoString, pHsChannel); + + HsProcFsStaticWarpMesh(pInfoString, pHsChannel); + + HsProcFsFlipQueue(pInfoString, pHsChannel); + + HsProcFsFrameSemaphores(pInfoString, pHsChannel); + + HsProcFsScanLine(pInfoString, pHsChannel); +} +#endif /* NVKMS_PROCFS_ENABLE */ diff --git a/src/nvidia-modeset/src/nvkms-lut.c b/src/nvidia-modeset/src/nvkms-lut.c index 3e623a66d..fbe195ad0 100644 --- a/src/nvidia-modeset/src/nvkms-lut.c +++ b/src/nvidia-modeset/src/nvkms-lut.c @@ -288,10 +288,77 @@ static NVLutSurfaceEvoPtr AllocLutSurfaceEvo(NVDevEvoPtr pDevEvo) } } +NvBool nvSetTmoLutSurfacesEvo(NVDevEvoPtr pDevEvo, + NVFlipEvoHwState *pFlipState, + NvU32 head) +{ + NvU32 layer; + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + if (pFlipState->layer[layer].hdrStaticMetadata.enabled) { + if (!pFlipState->layer[layer].tmoLut.pLutSurfaceEvo) { + pFlipState->layer[layer].tmoLut.pLutSurfaceEvo = + AllocLutSurfaceEvo(pDevEvo); + if (!pFlipState->layer[layer].tmoLut.pLutSurfaceEvo) { + return FALSE; + } + + // Will be referenced via nvRefTmoLutSurfacesEvo() on new state + pFlipState->layer[layer].tmoLut.pLutSurfaceEvo->allocRefCnt = 0; + } + } else { + // Will be freed via nvUnrefTmoLutSurfacesEvo() on old state + pFlipState->layer[layer].tmoLut.pLutSurfaceEvo = NULL; + } + } + + return TRUE; +} + +void nvRefTmoLutSurfacesEvo(NVDevEvoPtr pDevEvo, + NVFlipEvoHwState *pFlipState, + NvU32 head) +{ + // Reference new state layers that have hdrStaticMetadata enabled. + NvU32 layer; + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + if (pFlipState->layer[layer].hdrStaticMetadata.enabled) { + nvAssert(pFlipState->layer[layer].tmoLut.pLutSurfaceEvo); + pFlipState->layer[layer].tmoLut.pLutSurfaceEvo->allocRefCnt++; + } + } +} + +void nvUnrefTmoLutSurfacesEvo(NVDevEvoPtr pDevEvo, + NVFlipEvoHwState *pFlipState, + NvU32 head) +{ + // Unref old state layers that had hdrStaticMetadata enabled. + NvU32 layer; + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + if (pFlipState->layer[layer].hdrStaticMetadata.enabled) { + nvAssert(pFlipState->layer[layer].tmoLut.pLutSurfaceEvo); + + if (pFlipState->layer[layer].tmoLut.pLutSurfaceEvo->allocRefCnt <= 1) { + // Wait for any outstanding LUT updates before freeing. + if (pDevEvo->core) { + nvRMSyncEvoChannel(pDevEvo, pDevEvo->core, __LINE__); + } + + FreeLutSurfaceEvo( + pFlipState->layer[layer].tmoLut.pLutSurfaceEvo); + + pFlipState->layer[layer].tmoLut.pLutSurfaceEvo = NULL; + } else { + pFlipState->layer[layer].tmoLut.pLutSurfaceEvo->allocRefCnt--; + } + } + } +} + NvBool nvAllocLutSurfacesEvo(NVDevEvoPtr pDevEvo) { NVDispEvoPtr pDispEvo; - NvU32 head, dispIndex, i; + NvU32 head, dispIndex, i, sd; for (head = 0; head < pDevEvo->numHeads; head++) { for (i = 0; i < ARRAY_LEN(pDevEvo->lut.head[head].LUT); i++) { @@ -318,6 +385,12 @@ NvBool nvAllocLutSurfacesEvo(NVDevEvoPtr pDevEvo) return FALSE; } + for (sd = 0; sd < NVKMS_MAX_SUBDEVICES; sd++) { + pDevEvo->lut.defaultBaseLUTState[sd] = + pDevEvo->lut.defaultOutputLUTState[sd] = + NvKmsLUTStateUninitialized; + } + pDevEvo->hal->InitDefaultLut(pDevEvo); } diff --git a/src/nvidia-modeset/src/nvkms-modepool.c b/src/nvidia-modeset/src/nvkms-modepool.c index 17e5a6e8c..136c6f605 100644 --- a/src/nvidia-modeset/src/nvkms-modepool.c +++ b/src/nvidia-modeset/src/nvkms-modepool.c @@ -1923,7 +1923,8 @@ NvBool nvValidateModeForModeset(NVDpyEvoRec *pDpyEvo, const struct NvKmsMode *pKmsMode, const struct NvKmsSize *pViewPortSizeIn, const struct NvKmsRect *pViewPortOut, - NVHwModeTimingsEvo *pTimingsEvo) + NVHwModeTimingsEvo *pTimingsEvo, + NVT_VIDEO_INFOFRAME_CTRL *pInfoFrameCtrl) { EvoValidateModeFlags flags; struct NvKmsMode kmsMode = *pKmsMode; @@ -1959,7 +1960,9 @@ NvBool nvValidateModeForModeset(NVDpyEvoRec *pDpyEvo, return FALSE; } - pTimingsEvo->infoFrameCtrl = infoFrameCtrl; + if (pInfoFrameCtrl != NULL) { + *pInfoFrameCtrl = infoFrameCtrl; + } return TRUE; } diff --git a/src/nvidia-modeset/src/nvkms-modeset.c b/src/nvidia-modeset/src/nvkms-modeset.c index 0ba1b8885..7dc1b4142 100644 --- a/src/nvidia-modeset/src/nvkms-modeset.c +++ b/src/nvidia-modeset/src/nvkms-modeset.c @@ -97,6 +97,56 @@ #include "nvkms-modeset-types.h" #include "nvkms-modeset-workarea.h" #include "nvkms-attributes.h" +#include "nvkms-headsurface-config.h" + +static void +ClearProposedModeSetHwState(const NVDevEvoRec *pDevEvo, + NVProposedModeSetHwState *pProposed, + const NvBool committed) +{ + const NVDispEvoRec *pDispEvo; + NvU32 dispIndex; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + NvU32 head; + + if (!committed) { + /* Free new allocated RM display IDs for changed heads */ + for (head = 0; head < pDevEvo->numHeads; head++) { + NVProposedModeSetHwStateOneHead *pProposedHead = + &pProposed->disp[dispIndex].head[head]; + + if (!pProposedHead->changed || + (pProposedHead->activeRmId == 0x0)) { + continue; + } + nvRmFreeDisplayId(pDispEvo, pProposedHead->activeRmId); + } + } + + for (head = 0; head < pDevEvo->numHeads; head++) { + NVProposedModeSetHwStateOneHead *pProposedHead = + &pProposed->disp[dispIndex].head[head]; + nvDPLibFreeModesetState(pProposedHead->pDpLibModesetState); + } + } + + nvkms_memset(pProposed, 0 , sizeof(*pProposed)); +} + +/* + * Inherit the previous modeset state as part of this modeset if: + * - The requesting client is not the internal NVKMS client (i.e., this is not + * a console restore modeset). + * - There is no modeset ownership change since the last modeset. + */ +static NvBool +InheritPreviousModesetState(const NVDevEvoRec *pDevEvo, + const struct NvKmsPerOpenDev *pCurrentModesetOpenDev) +{ + return (pCurrentModesetOpenDev != pDevEvo->pNvKmsOpenDev) && + (pCurrentModesetOpenDev == pDevEvo->lastModesettingClient); +} /*! * Get an allowFlipLockGroup value that is not yet used by pProposed. @@ -171,10 +221,11 @@ static NvU8 GetAvailableAllowFlipLockGroupValue( * \return Return TRUE if the requested mode is valid and pTimings * could be assigned. Otherwise, return FALSE. */ -static NvBool -GetHwModeTimings(const NVDispEvoRec *pDispEvo, - const struct NvKmsSetModeOneHeadRequest *pRequestHead, - NVHwModeTimingsEvo *pTimings) +NvBool +nvGetHwModeTimings(const NVDispEvoRec *pDispEvo, + const struct NvKmsSetModeOneHeadRequest *pRequestHead, + NVHwModeTimingsEvo *pTimings, + NVT_VIDEO_INFOFRAME_CTRL *pInfoFrameCtrl) { NVDpyEvoPtr pDpyEvo; @@ -194,44 +245,27 @@ GetHwModeTimings(const NVDispEvoRec *pDispEvo, &pRequestHead->viewPortSizeIn, pRequestHead->viewPortOutSpecified ? &pRequestHead->viewPortOut : NULL, - pTimings); + pTimings, + pInfoFrameCtrl); } -static NvBool ApplySyncptRegistration( - NVDevEvoRec *pDevEvo, - NvU32 head, - const struct NvKmsFlipCommonParams *pParams, - NVFlipEvoHwState *pFlipState) +static NvBool IsPreSyncptSpecified( + const NVDevEvoRec *pDevEvo, + const NvU32 head, + const struct NvKmsFlipCommonParams *pParams) { NvU32 layer; - if (!pDevEvo->supportsSyncpts) { - return TRUE; - } - - /*! - * Modeset path should not request pre-syncpt as it will - * not progress because this will update all of the Core and - * Window method state together, and wait for the Core - * completion notifier to signal. If any of the Window - * channels is waiting for a semaphore acquire, then this - * will stall the Core notifier as well since the Core and - * Window channels are interlocked. - */ for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { if (pParams->layer[layer].syncObjects.specified && pParams->layer[layer].syncObjects.val.useSyncpt && pParams->layer[layer].syncObjects.val.u.syncpts.pre.type != NVKMS_SYNCPT_TYPE_NONE) { - nvAssert(!"Failing as pre-syncpt requested in modeset!"); - return FALSE; + return TRUE; } } - return nvHandleSyncptRegistration(pDevEvo, - head, - pParams, - pFlipState); + return FALSE; } static NvBool @@ -273,7 +307,9 @@ GetColorSpaceAndColorRange( * Choose current colorSpace and colorRange based on the current mode * timings and the requested color space and range. */ - nvChooseCurrentColorSpaceAndRangeEvo(&pProposedHead->timings, + nvChooseCurrentColorSpaceAndRangeEvo(pProposedHead->timings.pixelDepth, + pProposedHead->timings.yuv420Mode, + pProposedHead->tf, requestedColorSpace, requestedColorRange, &pProposedHead->attributes.colorSpace, @@ -317,6 +353,22 @@ GetColorSpaceAndColorRange( return TRUE; } +/* + * Return whether headSurface is allowed. But, only honor the requestor's + * setting if they are the modeset owner. Otherwise, inherit the cached value + * in pDevEvo. + */ +NvBool nvGetAllowHeadSurfaceInNvKms(const NVDevEvoRec *pDevEvo, + const struct NvKmsPerOpenDev *pOpenDev, + const struct NvKmsSetModeRequest *pRequest) +{ + if (pOpenDev == pDevEvo->modesetOwner || pOpenDev == pDevEvo->pNvKmsOpenDev) { + return pRequest->allowHeadSurfaceInNvKms; + } + + return pDevEvo->allowHeadSurfaceInNvKms; +} + /*! * Assign the NVProposedModeSetHwState structure. * @@ -343,8 +395,7 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, const struct NvKmsPerOpenDev *pOpenDev, const struct NvKmsSetModeRequest *pRequest, struct NvKmsSetModeReply *pReply, - NVProposedModeSetHwState *pProposed, - NvBool modesetOwnerChanged) + NVProposedModeSetHwState *pProposed) { NvU32 sd; NVDispEvoPtr pDispEvo; @@ -360,6 +411,7 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, const NVDispHeadStateEvoRec *pHeadState; NVProposedModeSetHwStateOneHead *pProposedHead = &pProposed->disp[sd].head[head]; + const NvU32 apiHead = nvHardwareHeadToApiHead(head); /* * Case of invalid hardware head is handled inside @@ -375,26 +427,29 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, pHeadState = &pDispEvo->headState[head]; pProposedHead->timings = pHeadState->timings; - pProposedHead->dpyIdList = pHeadState->activeDpys; + pProposedHead->dpyIdList = + pDispEvo->apiHeadState[apiHead].activeDpys; pProposedHead->pConnectorEvo = pHeadState->pConnectorEvo; pProposedHead->activeRmId = pHeadState->activeRmId; pProposedHead->allowFlipLockGroup = pHeadState->allowFlipLockGroup; pProposedHead->modeValidationParams = pHeadState->modeValidationParams; - pProposedHead->attributes = pHeadState->attributes; + pProposedHead->attributes = + pDispEvo->apiHeadState[apiHead].attributes; pProposedHead->changed = FALSE; - pProposedHead->hs10bpcHint = pHeadState->hs10bpcHint; + pProposedHead->hs10bpcHint = + pDispEvo->apiHeadState[apiHead].hs10bpcHint; pProposedHead->audio = pHeadState->audio; + pProposedHead->infoFrame = + pDispEvo->apiHeadState[apiHead].infoFrame; + pProposedHead->tf = pHeadState->tf; } } /* Update pProposed with the requested changes from the client. */ - if (pOpenDev == pDevEvo->modesetOwner || pOpenDev == pDevEvo->pNvKmsOpenDev) { - pProposed->allowHeadSurfaceInNvKms = pRequest->allowHeadSurfaceInNvKms; - } else { - pProposed->allowHeadSurfaceInNvKms = pDevEvo->allowHeadSurfaceInNvKms; - } + pProposed->allowHeadSurfaceInNvKms = + nvGetAllowHeadSurfaceInNvKms(pDevEvo, pOpenDev, pRequest); FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { const struct NvKmsSetModeOneDispRequest *pRequestDisp = @@ -403,7 +458,7 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, NvU32 head; if ((pRequest->requestedDispsBitMask & (1 << sd)) == 0) { - if (modesetOwnerChanged) { + if (!InheritPreviousModesetState(pDevEvo, pOpenDev)) { shutDownAllHeads = TRUE; } else { continue; @@ -426,7 +481,7 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, if ((pRequestDisp->requestedHeadsBitMask & (1 << head)) == 0 || shutDownAllHeads) { - if (modesetOwnerChanged) { + if (!InheritPreviousModesetState(pDevEvo, pOpenDev)) { /* * If the modeset owner is changing, implicitly shut down * other heads not included in requestedHeadsBitMask. @@ -495,12 +550,15 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, * head so that if additional heads fail, we can report * more complete failure information to the client. */ - if (!GetHwModeTimings(pDispEvo, pRequestHead, &pProposedHead->timings)) { + if (!nvGetHwModeTimings(pDispEvo, pRequestHead, + &pProposedHead->timings, &pProposedHead->infoFrame.ctrl)) { pReply->disp[sd].head[head].status = NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_MODE; ret = FALSE; continue; } + pProposedHead->infoFrame.hdTimings = + nvEvoIsHDQualityVideoTimings(&pProposedHead->timings); pProposedHead->allowFlipLockGroup = 0; pProposedHead->modeValidationParams = @@ -543,12 +601,12 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, } /* - * modesetOwnerChanged implies that there was a modeset - * ownership change since the last modeset. If input/output lut not - * specified by the new modeset owner then keep them disabled by - * default. + * If InheritPreviousModesetState() returns FALSE, it implies that + * there was a modeset ownership change since the last modeset. If + * input/output lut not specified by the new modeset owner then + * keep them disabled by default. */ - if (modesetOwnerChanged) { + if (!InheritPreviousModesetState(pDevEvo, pOpenDev)) { pProposedHead->lut = pRequestHead->lut; if (!pRequestHead->lut.input.specified) { @@ -595,11 +653,20 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, } } - if (!ApplySyncptRegistration( + /*! + * Modeset path should not request pre-syncpt as it will + * not progress because this will update all of the Core and + * Window method state together, and wait for the Core + * completion notifier to signal. If any of the Window + * channels is waiting for a semaphore acquire, then this + * will stall the Core notifier as well since the Core and + * Window channels are interlocked. + */ + if (pDevEvo->supportsSyncpts && + IsPreSyncptSpecified( pDevEvo, head, - &pRequest->disp[sd].head[head].flip, - pFlip)) { + &pRequest->disp[sd].head[head].flip)) { pReply->disp[sd].head[head].status = NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_FLIP; ret = FALSE; @@ -611,8 +678,7 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, head, &pRequestHead->flip, pFlip, - FALSE /* allowVrr */, - &pProposedHead->timings.viewPort.possibleUsage)) { + FALSE /* allowVrr */)) { pReply->disp[sd].head[head].status = NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_FLIP; ret = FALSE; @@ -691,6 +757,11 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, } } + if (ret) { + } else { + ClearProposedModeSetHwState(pDevEvo, pProposed, FALSE /* committed */); + } + return ret; } @@ -802,9 +873,8 @@ ValidateProposedModeSetHwStateOneDispImp(NVDispEvoPtr pDispEvo, &pDevEvo->gpus[0].headState[head].preallocatedUsage; } - guaranteedAndProposed[head] = nvUnionUsageBounds( - &pProposedHead->timings.viewPort.guaranteedUsage, - pProposedUsage); + nvUnionUsageBounds(&pProposedHead->timings.viewPort.guaranteedUsage, + pProposedUsage, &guaranteedAndProposed[head]); timingsParams[head].pUsage = &guaranteedAndProposed[head]; } @@ -857,7 +927,8 @@ static NvBool DowngradeDpPixelDepth( if ((pProposedHead->pConnectorEvo == pConnectorEvo) && nvDowngradeHwModeTimingsDpPixelDepthEvo( pTimings, - pProposedHead->attributes.colorSpace)) { + pProposedHead->attributes.colorSpace, + pProposedHead->attributes.colorRange)) { return TRUE; } } @@ -1053,31 +1124,6 @@ ValidateProposedModeSetHwStateOneDisp( dpyIdList = nvAddDpyIdListToDpyIdList(dpyIdList, proposedDpyIdList); } - /* - * Check that the requested flipping state is valid. - */ - - for (head = 0; head < pDevEvo->numHeads; head++) { - - if (!pProposedDisp->head[head].changed) { - continue; - } - - if (nvDpyIdListIsEmpty(pProposedDisp->head[head].dpyIdList)) { - continue; - } - - if (!nvValidateFlipEvoHwState( - pDevEvo, - head, - &pProposedDisp->head[head].timings, - &pProposed->sd[pDispEvo->displayOwner].head[head].flip)) { - pReplyDisp->head[head].status = - NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_FLIP; - return FALSE; - } - } - /* * Check ViewPortIn dimensions and ensure valid h/vTaps can be assigned. */ @@ -1105,6 +1151,28 @@ ValidateProposedModeSetHwStateOneDisp( return FALSE; } + /* + * The pixelDepth value, which required to choose the dithering + * configuration, gets finalized as part of the DisplayPort bandwidth + * validation. + */ + for (head = 0; head < pDevEvo->numHeads; head++) { + NVProposedModeSetHwStateOneHead *pProposedHead = + &pProposedDisp->head[head]; + NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pProposedHead->dpyIdList, + pDispEvo); + + if (!pProposedHead->changed || (pDpyEvo == NULL)) { + continue; + } + + nvChooseDitheringEvo(pDpyEvo->pConnectorEvo, + pProposedHead->timings.pixelDepth, + &pDpyEvo->requestedDithering, + &pProposedHead->attributes.dithering); + } + /* * Check that the configuration passes IMP. */ @@ -1118,6 +1186,51 @@ ValidateProposedModeSetHwStateOneDisp( return TRUE; } +/*! + * Validate the proposed flip configuration on the specified sub device. + * + * \param[in] pDispEvo The disp to which pProposedDisp is to be applied. + * \param[in] pProposed The requested configuration. + * \param[out] pProposedSd The requested flip configuration. + * + * \return If pProposedDisp is valid, return TRUE. Otherwise, set the + * appropriate status fields in pReplyDisp to non-SUCCESS, + * and return FALSE. + */ +static NvBool +ValidateProposedFlipHwStateOneSubDev( + const NVDevEvoRec *pDevEvo, + const NVProposedModeSetHwStateOneDisp *pProposedDisp, + NVProposedModeSetHwStateOneSubDev *pProposedSd, + struct NvKmsSetModeOneDispReply *pReplyDisp) +{ + NvU32 head; + + for (head = 0; head < pDevEvo->numHeads; head++) { + if (!pProposedDisp->head[head].changed || + nvDpyIdListIsEmpty(pProposedDisp->head[head].dpyIdList)) { + continue; + } + + nvOverrideScalingUsageBounds( + pDevEvo, + head, + &pProposedSd->head[head].flip, + &pProposedDisp->head[head].timings.viewPort.possibleUsage); + + if (!nvValidateFlipEvoHwState(pDevEvo, + head, + &pProposedDisp->head[head].timings, + &pProposedSd->head[head].flip)) { + pReplyDisp->head[head].status = + NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_FLIP; + return FALSE; + } + } + + return TRUE; +} + /*! * Validate the proposed configuration. * @@ -1155,6 +1268,8 @@ ValidateProposedModeSetHwState(NVDevEvoPtr pDevEvo, NVProposedModeSetHwStateOneDisp *pProposedDisp = &pActual->disp[dispIndex]; + NVProposedModeSetHwStateOneSubDev *pProposedSd = + &pActual->sd[pDispEvo->displayOwner]; struct NvKmsSetModeOneDispReply *pReplyDisp; pReplyDisp = &pReply->disp[dispIndex]; @@ -1166,6 +1281,13 @@ ValidateProposedModeSetHwState(NVDevEvoPtr pDevEvo, pWorkArea)) { goto done; } + + if (!ValidateProposedFlipHwStateOneSubDev(pDevEvo, + pProposedDisp, + pProposedSd, + pReplyDisp)) { + goto done; + } } nvkms_memcpy(pProposed, pActual, sizeof(*pProposed)); @@ -1395,6 +1517,8 @@ ApplyProposedModeSetHwStateOneHeadShutDown( NVDispHeadStateEvoPtr pHeadState; NVDpyEvoPtr pDpyEvo; const NvU32 sd = pDispEvo->displayOwner; + NvU32 apiHead = nvHardwareHeadToApiHead(head); + NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[apiHead]; /* * If nothing changed about this head's configuration, then we @@ -1417,7 +1541,7 @@ ApplyProposedModeSetHwStateOneHeadShutDown( } pHeadState = &pDispEvo->headState[head]; - pDpyEvo = nvGetOneArbitraryDpyEvo(pHeadState->activeDpys, pDispEvo); + pDpyEvo = nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo); /* * Identify and disable any active core RG sync objects. @@ -1444,9 +1568,10 @@ ApplyProposedModeSetHwStateOneHeadShutDown( pWorkArea->sd[pDispEvo->displayOwner].changedDpyIdList = nvAddDpyIdListToDpyIdList( - pHeadState->activeDpys, + pApiHeadState->activeDpys, pWorkArea->sd[pDispEvo->displayOwner].changedDpyIdList); - pHeadState->activeDpys = nvEmptyDpyIdList(); + pApiHeadState->activeDpys = nvEmptyDpyIdList(); + nvkms_memset(&pApiHeadState->timings, 0, sizeof(pApiHeadState->timings)); pHeadState->pConnectorEvo = NULL; pHeadState->bypassComposition = FALSE; @@ -1467,6 +1592,9 @@ ApplyProposedModeSetHwStateOneHeadShutDown( nvkms_memset(&pDevEvo->gpus[sd].headState[head], 0, sizeof(pDevEvo->gpus[sd].headState[head])); + pDevEvo->gpus[sd].headState[head].cursor.cursorCompParams = + nvDefaultCursorCompositionParams(pDevEvo); + pDpyEvo->apiHead = NV_INVALID_HEAD; } @@ -1559,6 +1687,8 @@ ApplyProposedModeSetHwStateOneHeadPreUpdate( NVDispHeadStateEvoPtr pHeadState; NVDpyEvoPtr pDpyEvo = nvGetOneArbitraryDpyEvo(pProposedHead->dpyIdList, pDispEvo); + NvU32 apiHead = nvHardwareHeadToApiHead(head); + NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[apiHead]; /* * If nothing changed about this head's configuration, then there @@ -1584,7 +1714,7 @@ ApplyProposedModeSetHwStateOneHeadPreUpdate( return; } - pDpyEvo->apiHead = nvHardwareHeadToApiHead(head); + pDpyEvo->apiHead = apiHead; AssignSor(pWorkArea, pProposedHead->pConnectorEvo); @@ -1600,10 +1730,11 @@ ApplyProposedModeSetHwStateOneHeadPreUpdate( * Cache the list of active pDpys for this head, as well as the * mode timings. */ - pHeadState->activeDpys = pProposedHead->dpyIdList; + pApiHeadState->activeDpys = pProposedHead->dpyIdList; + pApiHeadState->timings = pProposedHead->timings; pWorkArea->sd[pDispEvo->displayOwner].changedDpyIdList = nvAddDpyIdListToDpyIdList( - pHeadState->activeDpys, + pApiHeadState->activeDpys, pWorkArea->sd[pDispEvo->displayOwner].changedDpyIdList); nvAssert(pDpyEvo->pConnectorEvo == pProposedHead->pConnectorEvo); @@ -1612,6 +1743,7 @@ ApplyProposedModeSetHwStateOneHeadPreUpdate( pHeadState->timings = pProposedHead->timings; pHeadState->audio = pProposedHead->audio; + pApiHeadState->infoFrame = pProposedHead->infoFrame; AssignProposedUsageOneHead(pDispEvo->pDevEvo, pProposed, head); @@ -1625,11 +1757,9 @@ ApplyProposedModeSetHwStateOneHeadPreUpdate( nvEvoSetTimings(pDispEvo, head, updateState); - // Set the dither type & mode - nvSetDitheringEvo(pDispEvo, head, - pDpyEvo->requestedDithering.state, - pDpyEvo->requestedDithering.depth, - pDpyEvo->requestedDithering.mode, + nvSetDitheringEvo(pDispEvo, + head, + &pProposedHead->attributes.dithering, updateState); nvEvoHeadSetControlOR(pDispEvo, head, updateState); @@ -1669,15 +1799,7 @@ ApplyProposedModeSetHwStateOneHeadPreUpdate( ReenableActiveCoreRGSyncObjects(pDispEvo->pDevEvo, pHeadState, head, updateState); - pHeadState->attributes.digitalSignal = - pProposedHead->attributes.digitalSignal; - pHeadState->attributes.dvc = pProposedHead->attributes.dvc; - pHeadState->attributes.imageSharpening.available = - pProposedHead->attributes.imageSharpening.available; - pHeadState->attributes.imageSharpening.value = - pProposedHead->attributes.imageSharpening.value; - pHeadState->attributes.colorSpace = pProposedHead->attributes.colorSpace; - pHeadState->attributes.colorRange = pProposedHead->attributes.colorRange; + pApiHeadState->attributes = pProposedHead->attributes; } @@ -1699,6 +1821,9 @@ ApplyProposedModeSetHwStateOneHeadPostUpdate(NVDispEvoPtr pDispEvo, *pProposedHead) { NVDispHeadStateEvoRec *pHeadState; + NVDpyEvoRec *pDpyEvo; + NvU32 apiHead = nvHardwareHeadToApiHead(head); + NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[apiHead]; /* * If nothing changed about this head's configuration, then there @@ -1718,11 +1843,15 @@ ApplyProposedModeSetHwStateOneHeadPostUpdate(NVDispEvoPtr pDispEvo, * if this head is left alone in the next NvKmsSetModeRequest. */ pHeadState = &pDispEvo->headState[head]; + + pDpyEvo = nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo); + nvAssert(pDpyEvo != NULL); + pHeadState->allowFlipLockGroup = pProposedHead->allowFlipLockGroup; pHeadState->modeValidationParams = pProposedHead->modeValidationParams; - pHeadState->hs10bpcHint = pProposedHead->hs10bpcHint; + pApiHeadState->hs10bpcHint = pProposedHead->hs10bpcHint; - nvUpdateInfoFrames(pDispEvo, head); + nvUpdateInfoFrames(pDpyEvo); /* Perform 3D vision authentication */ nv3DVisionAuthenticationEvo(pDispEvo, head); @@ -2340,6 +2469,7 @@ AssignReplySuccess(const NVDevEvoRec *pDevEvo, } for (head = 0; head < pDevEvo->numHeads; head++) { + const NvU32 apiHead = nvHardwareHeadToApiHead(head); const struct NvKmsSetModeOneHeadRequest *pRequestHead = &pRequestDisp->head[head]; struct NvKmsSetModeOneHeadReply *pReplyHead = @@ -2360,7 +2490,7 @@ AssignReplySuccess(const NVDevEvoRec *pDevEvo, pReplyHead->possibleUsage = pHeadState->timings.viewPort.possibleUsage; pReplyHead->guaranteedUsage = pHeadState->timings.viewPort.guaranteedUsage; pReplyHead->usingHeadSurface = - (pDispEvo->pHsChannel[head] != NULL); + (pDispEvo->pHsChannel[apiHead] != NULL); pReplyHead->vrrEnabled = (pDispEvo->headState[head].timings.vrr.type != NVKMS_DPY_VRR_TYPE_NONE); @@ -2431,18 +2561,95 @@ static NvBool IdleAllSatelliteChannels(NVDevEvoRec *pDevEvo) } /*! - * Helper function to validate the proposed mode + * Helper function to assign and validate the proposed mode */ static NvBool -IsProposedModeSetValid(NVDevEvoPtr pDevEvo, - struct NvKmsSetModeReply *pReply, - const struct NvKmsPerOpenDev *pOpenDev, - NVProposedModeSetHwState *pProposed, - const struct NvKmsSetModeRequest *pRequest, - NVModeSetWorkArea *pWorkArea) +AssignAndValidateProposedModeSet(NVDevEvoPtr pDevEvo, + struct NvKmsPerOpenDev *pOpenDev, + const struct NvKmsSetModeRequest *pRequest, + struct NvKmsSetModeReply *pReply, + NVProposedModeSetHwState *pProposed, + NVModeSetWorkArea *pWorkArea) { - return ValidateProposedModeSetHwState(pDevEvo, pProposed, pReply, - pWorkArea); + NvBool ret = FALSE; + struct NvKmsSetModeRequest *pPatchedRequest = nvPreallocGet(pDevEvo, + PREALLOC_TYPE_HS_PATCHED_MODESET_REQUEST, + sizeof(*pPatchedRequest)); + + /* clear pPatchedRequest */ + nvkms_memset(pPatchedRequest, 0, sizeof(*pPatchedRequest)); + + if (!nvHsConfigInitModeset(pDevEvo, pRequest, pReply, pOpenDev, + &pWorkArea->hsConfig)) { + goto done; + } + +tryHsAgain: + { + NvU32 patchedApiHeadsMask[NVKMS_MAX_SUBDEVICES] = { }; + + if (!nvHsConfigAllocResources(pDevEvo, &pWorkArea->hsConfig)) { + goto done; + } + + /* copy pRequest -> pPatchedRequest */ + *pPatchedRequest = *pRequest; + + /* modify pPatchedRequest for a headsurface config */ + if (!nvHsConfigPatchSetModeRequest(pDevEvo, &pWorkArea->hsConfig, + pOpenDev, pPatchedRequest, + patchedApiHeadsMask)) { + + nvHsConfigFreeResources(pDevEvo, &pWorkArea->hsConfig); + + goto done; + } + + /* assign pProposed from pPatchedRequest */ + if (!AssignProposedModeSetHwState(pDevEvo, pOpenDev, pPatchedRequest, + pReply, pProposed)) { + + nvHsConfigClearPatchedSetModeRequest(pDevEvo, + pOpenDev, + pPatchedRequest, + patchedApiHeadsMask); + nvHsConfigFreeResources(pDevEvo, &pWorkArea->hsConfig); + + goto done; + } + + /* validate pProposed */ + if (!ValidateProposedModeSetHwState(pDevEvo, pProposed, pReply, + pWorkArea)) { + + ClearProposedModeSetHwState(pDevEvo, pProposed, FALSE); + nvHsConfigClearPatchedSetModeRequest(pDevEvo, + pOpenDev, + pPatchedRequest, + patchedApiHeadsMask); + nvHsConfigFreeResources(pDevEvo, &pWorkArea->hsConfig); + + /* + * If the pProposed assigned from the patched modeset request + * failed validation, downgrade the headSurface configuration and + * try again. + */ + if (nvHsConfigDowngrade(pDevEvo, pRequest, &pWorkArea->hsConfig)) { + goto tryHsAgain; + } + goto done; + } + + nvHsConfigClearPatchedSetModeRequest(pDevEvo, pOpenDev, pPatchedRequest, + patchedApiHeadsMask); + ret = TRUE; + } + +done: + nvPreallocRelease(pDevEvo, + PREALLOC_TYPE_HS_PATCHED_MODESET_REQUEST); + + return ret; } /*! @@ -2469,7 +2676,7 @@ IsProposedModeSetValid(NVDevEvoPtr pDevEvo, * have been changed. */ NvBool nvSetDispModeEvo(NVDevEvoPtr pDevEvo, - const struct NvKmsPerOpenDev *pOpenDev, + struct NvKmsPerOpenDev *pOpenDev, const struct NvKmsSetModeRequest *pRequest, struct NvKmsSetModeReply *pReply, NvBool bypassComposition, @@ -2483,19 +2690,7 @@ NvBool nvSetDispModeEvo(NVDevEvoPtr pDevEvo, NVDispEvoPtr pDispEvo; NvU32 dispNeedsEarlyUpdate; NvBool updateCoreFirst = FALSE; - - /* - * We should shutdown unused heads and do not inherit the previous modeset - * state as part of this modeset if: - * - The requesting client is the internal NVKMS client (i.e., - * this is a console restore modeset), or - * - 'modesetOwnerChanged' is recorded in the device; - * i.e., there was a modeset ownership change since the last - * modeset. - */ - const NvBool modesetOwnerChanged = - (pOpenDev == pDevEvo->pNvKmsOpenDev) ? TRUE : - pDevEvo->modesetOwnerChanged; + NvBool committed = FALSE; NVModeSetWorkArea *pWorkArea = nvPreallocGet(pDevEvo, PREALLOC_TYPE_MODE_SET_WORK_AREA, @@ -2517,14 +2712,8 @@ NvBool nvSetDispModeEvo(NVDevEvoPtr pDevEvo, goto done; } - if (!AssignProposedModeSetHwState(pDevEvo, pOpenDev, - pRequest, pReply, pProposed, - modesetOwnerChanged)) { - goto done; - } - - if (!IsProposedModeSetValid(pDevEvo, pReply, pOpenDev, pProposed, - pRequest, pWorkArea)) { + if (!AssignAndValidateProposedModeSet(pDevEvo, pOpenDev, pRequest, pReply, + pProposed, pWorkArea)) { goto done; } @@ -2548,7 +2737,7 @@ NvBool nvSetDispModeEvo(NVDevEvoPtr pDevEvo, /* * Disable stereo pin during console restore or modeset owner changes. */ - if (modesetOwnerChanged) { + if (!InheritPreviousModesetState(pDevEvo, pOpenDev)) { NvU32 sd; FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { NvU32 head; @@ -2561,6 +2750,14 @@ NvBool nvSetDispModeEvo(NVDevEvoPtr pDevEvo, } } + /* + * Tear down any existing headSurface config, restoring the pre-headSurface + * config. This must be done before fliplock is potentially re-enabled + * during nvEvoLockStatePostModeset below. + */ + + nvHsConfigStop(pDevEvo, &pWorkArea->hsConfig); + nvEvoCancelPostFlipIMPTimer(pDevEvo); BeginEndModeset(pDevEvo, pProposed, BEGIN_MODESET); @@ -2615,23 +2812,19 @@ NvBool nvSetDispModeEvo(NVDevEvoPtr pDevEvo, nvEvoLockStatePostModeset(pDevEvo, doRasterLock); + /* + * The modeset was successful: if headSurface was used as part of this + * modeset, record that in the pDevEvo. + */ + nvHsConfigStart(pDevEvo, &pWorkArea->hsConfig); + BeginEndModeset(pDevEvo, pProposed, END_MODESET); AssignReplySuccess(pDevEvo, pRequest, pReply, pWorkArea); pDevEvo->skipConsoleRestore = FALSE; - /* - * If this was a pNvKmsOpenDev-initiated modeset, force the next modeset to - * shut down all unused heads and not to inherit any state from this - * modeset. That will prevent a regular client from inheriting - * pNvKmsOpenDev modeset state. - */ - pDevEvo->modesetOwnerChanged = - (pOpenDev == pDevEvo->pNvKmsOpenDev) ? TRUE : FALSE; - - /* fall through */ -done: + pDevEvo->lastModesettingClient = pOpenDev; FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { NvU32 head; @@ -2640,47 +2833,42 @@ done: * In case of successful commit, update current attribute values and * free old display IDs. */ - if (pRequest->commit && ret) { - NVDpyEvoRec *pDpyEvo; + NVDpyEvoRec *pDpyEvo; - FOR_ALL_EVO_DPYS(pDpyEvo, - pWorkArea->sd[dispIndex].changedDpyIdList, - pDispEvo) { - nvDpyUpdateCurrentAttributes(pDpyEvo); - } - - for (head = 0; head < pDevEvo->numHeads; head++) { - if (pWorkArea->sd[dispIndex].head[head].oldActiveRmId != 0x0) { - nvRmFreeDisplayId( - pDispEvo, - pWorkArea->sd[dispIndex].head[head].oldActiveRmId); - } - } - } else { - /* Otherwise, free new allocated RM display IDs for changed heads */ - for (head = 0; head < pDevEvo->numHeads; head++) { - NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposed->disp[dispIndex].head[head]; - - if (!pProposedHead->changed || pProposedHead->activeRmId == 0x0) { - continue; - } - nvRmFreeDisplayId(pDispEvo, pProposedHead->activeRmId); - } + FOR_ALL_EVO_DPYS(pDpyEvo, + pWorkArea->sd[dispIndex].changedDpyIdList, + pDispEvo) { + nvDpyUpdateCurrentAttributes(pDpyEvo); } for (head = 0; head < pDevEvo->numHeads; head++) { - NVProposedModeSetHwStateOneHead *pProposedHead = - &pProposed->disp[dispIndex].head[head]; - nvDPLibFreeModesetState(pProposedHead->pDpLibModesetState); + if (pWorkArea->sd[dispIndex].head[head].oldActiveRmId != 0x0) { + nvRmFreeDisplayId( + pDispEvo, + pWorkArea->sd[dispIndex].head[head].oldActiveRmId); + } } } + committed = TRUE; + + /* fall through */ +done: + ClearProposedModeSetHwState(pDevEvo, pProposed, committed); + /* If all heads are shut down, allow GC6. */ if (nvAllHeadsInactive(pDevEvo)) { nvRmSetGc6Allowed(pDevEvo, TRUE); } + /* + * nvHsConfigFreeResources() frees any headSurface resources no longer + * needed. On a successful modeset, nvHsConfigApply() will move resources + * from the hsConfig to the pDevEvo, and nvHsConfigFreeResources() will be a + * noop. + */ + nvHsConfigFreeResources(pDevEvo, &pWorkArea->hsConfig); + nvPreallocRelease(pDevEvo, PREALLOC_TYPE_MODE_SET_WORK_AREA); nvPreallocRelease(pDevEvo, PREALLOC_TYPE_PROPOSED_MODESET_HW_STATE); return ret; @@ -2727,6 +2915,25 @@ NVVBlankCallbackPtr nvRegisterVBlankCallback(NVDispEvoPtr pDispEvo, return pVBlankCallback; } +NVVBlankCallbackPtr +nvApiHeadRegisterVBlankCallback(NVDispEvoPtr pDispEvo, + const NvU32 apiHead, + NVVBlankCallbackProc pCallback, + void *pUserData) +{ + /* + * All the hardware heads mapped on the input api head should be + * rasterlocked, and should trigger vblank callback exactly at same time; + * therefore it is sufficient to register vblank callback only with the + * primary hardware head. + */ + const NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); + if (head == NV_INVALID_HEAD) { + return NULL; + } + return nvRegisterVBlankCallback(pDispEvo, head, pCallback, pUserData); +} + /*! * Un-register a vblank callback for a given head. * @@ -2751,6 +2958,17 @@ void nvUnregisterVBlankCallback(NVDispEvoPtr pDispEvo, } } +void nvApiHeadUnregisterVBlankCallback(NVDispEvoPtr pDispEvo, + const NvU32 apiHead, + NVVBlankCallbackPtr pCallback) +{ + const NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); + if (head == NV_INVALID_HEAD) { + return; + } + nvUnregisterVBlankCallback(pDispEvo, head, pCallback); +} + /*! * Perform a modeset that disables some or all heads. * @@ -2780,7 +2998,7 @@ void nvShutDownHeads(NVDevEvoPtr pDevEvo, NVShutDownHeadsTestFunc pTestFunc) for (head = 0; head < pDevEvo->numHeads; head++) { /* * XXX pTestFunc isn't honored by nvSetDispModeEvo()'s - * modesetOwnerChanged logic. + * InheritPreviousModesetState() logic. */ if (pTestFunc && !pTestFunc(pDispEvo, head)) { continue; @@ -2827,3 +3045,21 @@ void nvShutDownHeads(NVDevEvoPtr pDevEvo, NVShutDownHeadsTestFunc pTestFunc) nvAssertAllDpysAreInactive(pDevEvo); } } + +NvU32 +nvApiHeadAddRgLine1Callback(const NVDispEvoRec *pDispEvo, + const NvU32 apiHead, + NV0092_REGISTER_RG_LINE_CALLBACK_FN pCallback) +{ + /* + * All the hardware heads mapped on the input api head should be + * rasterlocked, and should trigger RgLine1 callback exactly at same time; + * therefore it is sufficient to register RgLine1 callback only with the + * primary hardware head. + */ + const NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); + if (head == NV_INVALID_HEAD) { + return FALSE; + } + return nvRmAddRgLine1Callback(pDispEvo, head, pCallback); +} diff --git a/src/nvidia-modeset/src/nvkms-pow.c b/src/nvidia-modeset/src/nvkms-pow.c new file mode 100644 index 000000000..6445f54ea --- /dev/null +++ b/src/nvidia-modeset/src/nvkms-pow.c @@ -0,0 +1,468 @@ +/* + * ==================================================== + * Copyright (C) 2004 by Sun Microsystems, Inc. All rights reserved. + * + * Permission to use, copy, modify, and distribute this + * software is freely granted, provided that this notice + * is preserved. + * ==================================================== + */ + +/* + * ==================================================== + * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved. + * + * Developed at SunSoft, a Sun Microsystems, Inc. business. + * Permission to use, copy, modify, and distribute this + * software is freely granted, provided that this notice + * is preserved. + * ==================================================== + */ + +/* + * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* Adapted from https://www.netlib.org/fdlibm/fdlibm.h 1.5 04/04/22 */ +/* Adapted from https://www.netlib.org/fdlibm/e_pow.c 1.5 04/04/22 SMI */ +/* Adapted from https://www.netlib.org/fdlibm/s_fabs.c 1.3 95/01/18 */ +/* Adapted from https://www.netlib.org/fdlibm/s_scalbn.c 1.3 95/01/18 */ +/* Adapted from https://www.netlib.org/fdlibm/s_copysign.c 1.3 95/01/18 */ + +#include "nvkms-softfloat.h" +#include "nv-float.h" + +static const float64_t +bp[] = {{0x3FF0000000000000}, {0x3FF8000000000000},}, // 1.0, 1.5 +dp_h[] = {{0x0000000000000000}, {0x3FE2B80340000000},}, // 5.84962487220764160156e-01 +dp_l[] = {{0x0000000000000000}, {0x3E4CFDEB43CFD006},}, // 1.35003920212974897128e-08 +nan = {0xFFF8000000000000}, // NaN +zero = {0x0000000000000000}, // 0.0 +quarter = {0x3FD0000000000000}, // 0.25 +third = {0x3FD5555555555555}, // 0.3333333333333333333333 +half = {0x3FE0000000000000}, // 0.5 +one = {0x3FF0000000000000}, // 1.0 +two = {0x4000000000000000}, // 2.0 +three = {0x4008000000000000}, // 3.0 +two53 = {0x4340000000000000}, // 9007199254740992.0 +two54 = {0x4350000000000000}, // 1.80143985094819840000e+16 +twom54 = {0x3C90000000000000}, // 5.55111512312578270212e-17 +huge = {0x7E37E43C8800759C}, // 1.0e300 +tiny = {0x01A56E1FC2F8F359}, // 1.0e-300 +/* poly coefs for (3/2)*(log(x)-2s-2/3*s**3 */ +L1 = {0x3FE3333333333303}, // 5.99999999999994648725e-01} +L2 = {0x3FDB6DB6DB6FABFF}, // 4.28571428578550184252e-01} +L3 = {0x3FD55555518F264D}, // 3.33333329818377432918e-01} +L4 = {0x3FD17460A91D4101}, // 2.72728123808534006489e-01} +L5 = {0x3FCD864A93C9DB65}, // 2.30660745775561754067e-01} +L6 = {0x3FCA7E284A454EEF}, // 2.06975017800338417784e-01} +P1 = {0x3FC555555555553E}, // 1.66666666666666019037e-01} +P2 = {0xBF66C16C16BEBD93}, // -2.77777777770155933842e-03} +P3 = {0x3F11566AAF25DE2C}, // 6.61375632143793436117e-05} +P4 = {0xBEBBBD41C5D26BF1}, // -1.65339022054652515390e-06} +P5 = {0x3E66376972BEA4D0}, // 4.13813679705723846039e-08} +lg2 = {0x3FE62E42FEFA39EF}, // 6.93147180559945286227e-01} +lg2_h = {0x3FE62E4300000000}, // 6.93147182464599609375e-01} +lg2_l = {0xBE205C610CA86C39}, // -1.90465429995776804525e-09} +ovt = {0x3C971547652B82FE}, // -(1024-log2(ovfl+.5ulp)), 8.0085662595372944372e-0017 +cp = {0x3FEEC709DC3A03FD}, // 2/(3ln2), 9.61796693925975554329e-01 +cp_h = {0x3FEEC709E0000000}, // (float)cp, 9.61796700954437255859e-01 +cp_l = {0xBE3E2FE0145B01F5}, // tail of cp_h, -7.02846165095275826516e-09 +ivln2 = {0x3FF71547652B82FE}, // 1/ln2, 1.44269504088896338700e+00 +ivln2_h = {0x3FF7154760000000}, // 24b 1/ln2, 1.44269502162933349609e+00 +ivln2_l = {0x3E54AE0BF85DDF44}; // 1/ln2 tail, 1.92596299112661746887e-08 + +// Little endian only +#define __HI(x) *(1+(int*)&x) +#define __LO(x) *(int*)&x +#define __HIp(x) *(1+(int*)x) +#define __LOp(x) *(int*)x + +/* + * F64_copysign(float64_t x, float64_t y) + * F64_copysign(x,y) returns a value with the magnitude of x and + * with the sign bit of y. + */ +static float64_t F64_copysign(float64_t x, float64_t y) +{ + __HI(x) = (__HI(x) & 0x7fffffff) | (__HI(y) & 0x80000000); + return x; +} + +/* + * F64_scalbn (float64_t x, int n) + * F64_scalbn(x,n) returns x* 2**n computed by exponent + * manipulation rather than by actually performing an + * exponentiation or a multiplication. + */ +static float64_t F64_scalbn(float64_t x, int n) +{ + int k,hx,lx; + hx = __HI(x); + lx = __LO(x); + + k = (hx & 0x7ff00000) >> 20; // extract exponent + if (k == 0) { // 0 or subnormal x + if ((lx | (hx & 0x7fffffff)) == 0) { + return x; // +-0 + } + x = f64_mul(x, two54); + hx = __HI(x); + k = ((hx & 0x7ff00000) >> 20) - 54; + if (n < -50000) { + return f64_mul(tiny, x); // underflow + } + } + if (k == 0x7ff) { + return f64_add(x, x); // NaN or Inf + } + k = k + n; + if (k > 0x7fe) { + return f64_mul(huge, F64_copysign(huge,x)); // overflow + } + if (k > 0) { // normal result + __HI(x) = (hx & 0x800fffff) | (k << 20); + return x; + } + if (k <= -54) { + if (n > 50000) { // in case integer overflow in n+k + return f64_mul(huge, F64_copysign(huge,x)); // overflow + } + } else { + return f64_mul(tiny, F64_copysign(tiny,x)); // underflow + } + k += 54; // subnormal result + __HI(x) = (hx & 0x800fffff) | (k << 20); + return f64_mul(x, twom54); +} + + +/* + * F64_fabs(x) returns the absolute value of x. + */ +static float64_t F64_fabs(float64_t x) +{ + __HI(x) &= 0x7fffffff; + return x; +} + +/* + * nvKmsPow(x,y) return x**y + * + * n + * Method: Let x = 2 * (1+f) + * 1. Compute and return log2(x) in two pieces: + * log2(x) = w1 + w2, + * where w1 has 53-24 = 29 bit trailing zeros. + * 2. Perform y*log2(x) = n+y' by simulating muti-precision + * arithmetic, where |y'|<=0.5. + * 3. Return x**y = 2**n*exp(y'*log2) + * + * Special cases: + * 1. (anything) ** 0 is 1 + * 2. (anything) ** 1 is itself + * 3. (anything) ** NAN is NAN + * 4. NAN ** (anything except 0) is NAN + * 5. +-(|x| > 1) ** +INF is +INF + * 6. +-(|x| > 1) ** -INF is +0 + * 7. +-(|x| < 1) ** +INF is +0 + * 8. +-(|x| < 1) ** -INF is +INF + * 9. +-1 ** +-INF is NAN + * 10. +0 ** (+anything except 0, NAN) is +0 + * 11. -0 ** (+anything except 0, NAN, odd integer) is +0 + * 12. +0 ** (-anything except 0, NAN) is +INF + * 13. -0 ** (-anything except 0, NAN, odd integer) is +INF + * 14. -0 ** (odd integer) = -( +0 ** (odd integer) ) + * 15. +INF ** (+anything except 0,NAN) is +INF + * 16. +INF ** (-anything except 0,NAN) is +0 + * 17. -INF ** (anything) = -0 ** (-anything) + * 18. (-anything) ** (integer) is (-1)**(integer)*(+anything**integer) + * 19. (-anything except 0 and inf) ** (non-integer) is NAN + * + * Accuracy: + * pow(x,y) returns x**y nearly rounded. In particular, pow(integer,integer) + * always returns the correct integer provided it is representable. + */ +float64_t nvKmsPow(float64_t x, float64_t y) +{ + float64_t z, ax, z_h, z_l, p_h, p_l; + float64_t y1, t1, t2, r, s, t, u, v, w; + int i, j, k, yisint, n; + int hx, hy, ix, iy; + unsigned lx, ly; + + hx = __HI(x); + lx = __LO(x); + + hy = __HI(y); + ly = __LO(y); + + ix = hx & 0x7fffffff; + iy = hy & 0x7fffffff; + + /* y==zero: x**0 = 1 */ + if ((iy | ly) == 0) { + return one; + } + + /* +-NaN return x+y */ + if ((ix > 0x7ff00000) || ((ix == 0x7ff00000) && (lx != 0)) || + (iy > 0x7ff00000) || ((iy == 0x7ff00000) && (ly != 0))) { + return f64_add(x, y); + } + + /* + * Determine if y is an odd int when x < 0: + * yisint = 0 ... y is not an integer + * yisint = 1 ... y is an odd int + * yisint = 2 ... y is an even int + */ + yisint = 0; + if (hx < 0) { + if (iy >= 0x43400000) { + yisint = 2; // even integer y + } else if (iy >= 0x3ff00000) { + k = (iy >> 20) - 0x3ff; // exponent + if (k > 20) { + j = ly >> (52 - k); + if ((j << (52 - k)) == ly) { + yisint = 2 - (j & 1); + } + } else if (ly == 0) { + j = iy >> (20 - k); + if ((j << (20 -k )) == iy) { + yisint = 2 - (j & 1); + } + } + } + } + + /* special value of y */ + if (ly == 0) { + if (iy == 0x7ff00000) { // y is +-inf + if (((ix - 0x3ff00000) | lx) == 0) { // inf**+-1 is NaN + return f64_sub(y, y); + } else if (ix >= 0x3ff00000) { // (|x|>1)**+-inf = inf,0 + return (hy >= 0) ? y: zero; + } else { // (|x|<1)**-,+inf = inf,0 + return (hy < 0) ? F64_negate(y): zero; + } + } + if (iy == 0x3ff00000) { // y is +-1 + if (hy < 0) { + return f64_div(one, x); + } else { + return x; + } + } + if (hy == 0x40000000) { // y is 2 + return f64_mul(x, x); + } + if (hy == 0x3fe00000) { // y is 0.5 + if (hx >= 0) { // x >= +0 + return f64_sqrt(x); + } + } + } + + ax = F64_fabs(x); + /* special value of x */ + if (lx == 0) { + // x is +-0,+-inf,+-1 + if ((ix == 0x7ff00000) || (ix == 0) || (ix == 0x3ff00000)) { + z = ax; + if (hy < 0) { + z = f64_div(one, z); // z = (1/|x|) + } + if (hx < 0) { + if (((ix - 0x3ff00000) | yisint) == 0) { // (-1)**non-int is NaN + z = nan; + } else if (yisint == 1) { // (x<0)**odd = -(|x|**odd) + z = F64_negate(z); + } + } + return z; + } + } + + n = (hx >> 31) + 1; + + /* (x<0)**(non-int) is NaN */ + if ((n | yisint) == 0) { + return nan; + } + + s = one; // s (sign of result -ve**odd) = -1 else = 1 + if ((n | (yisint - 1)) == 0) { + s = F64_negate(one); // (-ve)**(odd int) + } + + /* |y| is huge */ + if (iy > 0x41e00000) { // if |y| > 2**31 + if (iy > 0x43f00000){ // if |y| > 2**64, must o/uflow + if (ix <= 0x3fefffff) { + return (hy < 0) ? f64_mul(huge, huge) : f64_mul(tiny, tiny); + } + if (ix >= 0x3ff00000) { + return (hy > 0) ? f64_mul(huge, huge) : f64_mul(tiny, tiny); + } + } + /* over/underflow if x is not close to one */ + if (ix < 0x3fefffff) { + return (hy < 0) ? f64_mul(f64_mul(s, huge), huge) : + f64_mul(f64_mul(s, tiny), tiny); + } + if (ix > 0x3ff00000) { + return (hy > 0) ? f64_mul(f64_mul(s, huge), huge) : + f64_mul(f64_mul(s, tiny), tiny); + } + /* + * now |1-x| is tiny <= 2**-20, suffice to compute + * log(x) by x-x^2/2+x^3/3-x^4/4 + */ + t = f64_sub(ax, one); // t has 20 trailing zeros + w = f64_mul(f64_mul(t, t), f64_sub(half, f64_mul(t, f64_sub(third, f64_mul(t, quarter))))); + u = f64_mul(ivln2_h, t); // ivln2_h has 21 sig. bits + v = f64_sub(f64_mul(t, ivln2_l), f64_mul(w, ivln2)); + t1 = f64_add(u, v); + __LO(t1) = 0; + t2 = f64_sub(v, f64_sub(t1, u)); + } else { + float64_t ss, s2, s_h, s_l, t_h, t_l; + n = 0; + /* take care subnormal number */ + if (ix < 0x00100000) { + ax = f64_mul(ax, two53); + n -= 53; + ix = __HI(ax); + } + n += ((ix) >> 20) - 0x3ff; + j = ix & 0x000fffff; + /* determine interval */ + ix = j | 0x3ff00000; // normalize ix + if (j <= 0x3988E) { // |x|> 1) | 0x20000000) + 0x00080000 + (k << 18); + t_l = f64_sub(ax, f64_sub(t_h, bp[k])); + s_l = f64_mul(v, f64_sub(f64_sub(u, f64_mul(s_h, t_h)), f64_mul(s_h, t_l))); + /* compute log(ax) */ + s2 = f64_mul(ss, ss); + r = f64_mul(f64_mul(s2, s2),f64_add(L1, f64_mul(s2, f64_add(L2, f64_mul(s2, f64_add(L3, f64_mul(s2, f64_add(L4, f64_mul(s2, f64_add(L5, f64_mul(s2, L6))))))))))); + r = f64_add(r, f64_mul(s_l, f64_add(s_h, ss))); + s2 = f64_mul(s_h, s_h); + t_h = f64_add(f64_add(three, s2), r); + __LO(t_h) = 0; + t_l = f64_sub(r, (f64_sub(f64_sub(t_h, three), s2))); + /* u+v = ss*(1+...) */ + u = f64_mul(s_h, t_h); + v = f64_add(f64_mul(s_l, t_h), f64_mul(t_l, ss)); + /* 2/(3log2)*(ss+...) */ + p_h = f64_add(u, v); + __LO(p_h) = 0; + p_l = f64_sub(v, f64_sub(p_h, u)); + z_h = f64_mul(cp_h, p_h); // cp_h+cp_l = 2/(3*log2) + z_l = f64_add(f64_add(f64_mul(cp_l, p_h), f64_mul(p_l, cp)), dp_l[k]); + /* log2(ax) = (ss+..)*2/(3*log2) = n + dp_h + z_h + z_l */ + t = i32_to_f64(n); + t1 = f64_add(f64_add(f64_add(z_h, z_l), dp_h[k]), t); + __LO(t1) = 0; + t2 = f64_sub(z_l, f64_sub(f64_sub(f64_sub(t1, t), dp_h[k]), z_h)); + } + + /* split up y into y1+y2 and compute (y1+y2)*(t1+t2) */ + y1 = y; + __LO(y1) = 0; + p_l = f64_add(f64_mul(f64_sub(y, y1), t1), f64_mul(y, t2)); + p_h = f64_mul(y1, t1); + z = f64_add(p_l, p_h); + j = __HI(z); + i = __LO(z); + if (j >= 0x40900000) { // z >= 1024 + if (((j - 0x40900000) | i) != 0) { // if z > 1024 + return f64_mul(f64_mul(s, huge), huge); // overflow + } else { + if (f64_lt(f64_sub(z, p_h), f64_add(p_l, ovt))) { + return f64_mul(f64_mul(s, huge), huge); // overflow + } + } + } else if ((j & 0x7fffffff) >= 0x4090cc00) { // z <= -1075 + if (((j - 0xc090cc00) | i) != 0) { // z < -1075 + return f64_mul(f64_mul(s, tiny), tiny); // underflow + } else { + if (f64_le(p_l, f64_sub(z, p_h))) { + return f64_mul(f64_mul(s, tiny), tiny); // underflow + } + } + } + /* + * compute 2**(p_h+p_l) + */ + i = j & 0x7fffffff; + k = (i >> 20) - 0x3ff; + n = 0; + if (i > 0x3fe00000) { // if |z| > 0.5, set n = [z+0.5] + n = j + (0x00100000 >> (k + 1)); + k = ((n & 0x7fffffff) >> 20) - 0x3ff; // new k for n + t = zero; + __HI(t) = (n & ~(0x000fffff >> k)); + n = ((n & 0x000fffff) | 0x00100000) >> (20 - k); + if (j < 0) { + n = -n; + } + p_h = f64_sub(p_h, t); + } + t = f64_add(p_l, p_h); + __LO(t) = 0; + u = f64_mul(t, lg2_h); + v = f64_add(f64_mul(f64_sub(p_l, f64_sub(t, p_h)), lg2), f64_mul(t, lg2_l)); + z = f64_add(u, v); + w = f64_sub(v, f64_sub(z, u)); + t = f64_mul(z, z); + t1 = f64_sub(z, f64_mul(t, f64_add(P1, f64_mul(t, f64_add(P2, f64_mul(t, f64_add(P3, f64_mul(t, f64_add(P4, f64_mul(t, P5)))))))))); + r = f64_sub(f64_div(f64_mul(z, t1), f64_sub(t1, two)), f64_add(w, f64_mul(z, w))); + z = f64_sub(one, f64_sub(r, z)); + j = __HI(z); + j += (n << 20); + if ((j >> 20) <= 0) { + z = F64_scalbn(z,n); // subnormal output + } else { + __HI(z) += (n << 20); + } + return f64_mul(s, z); +} diff --git a/src/nvidia-modeset/src/nvkms-prealloc.c b/src/nvidia-modeset/src/nvkms-prealloc.c index 7d3a1f741..82160cadc 100644 --- a/src/nvidia-modeset/src/nvkms-prealloc.c +++ b/src/nvidia-modeset/src/nvkms-prealloc.c @@ -47,8 +47,11 @@ static size_t GetSizeForType(NVDevEvoPtr pDevEvo, enum NVPreallocType type) case PREALLOC_TYPE_PROPOSED_MODESET_HW_STATE: /* fallthrough */ case PREALLOC_TYPE_VALIDATE_PROPOSED_MODESET_HW_STATE: return sizeof(NVProposedModeSetHwState); - case PREALLOC_TYPE_VALIDATE_MODE_HW_MODE_TIMINGS: + case PREALLOC_TYPE_VALIDATE_MODE_HW_MODE_TIMINGS: /* fallthrough */ + case PREALLOC_TYPE_HS_INIT_CONFIG_HW_TIMINGS: return sizeof(NVHwModeTimingsEvo); + case PREALLOC_TYPE_HS_PATCHED_MODESET_REQUEST: + return sizeof(struct NvKmsSetModeRequest); case PREALLOC_TYPE_MAX: /* Not a real option, but added for -Wswitch-enum */ break; diff --git a/src/nvidia-modeset/src/nvkms-push.c b/src/nvidia-modeset/src/nvkms-push.c new file mode 100644 index 000000000..892fa2d7d --- /dev/null +++ b/src/nvidia-modeset/src/nvkms-push.c @@ -0,0 +1,309 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#include "nvkms-push.h" +#include "nvkms-rmapi.h" +#include "nvkms-utils.h" + +#include "nvidia-push-methods.h" +#include "nvidia-push-utils.h" + +/* + * Wrapper functions needed by nvidia-push. + */ +static NvU32 NvPushImportRmApiControl( + NvPushDevicePtr pDevice, + NvU32 hObject, + NvU32 cmd, + void *pParams, + NvU32 paramsSize) +{ + return nvRmApiControl( + nvEvoGlobal.clientHandle, + hObject, + cmd, + pParams, + paramsSize); +} + +static NvU32 NvPushImportRmApiAlloc( + NvPushDevicePtr pDevice, + NvU32 hParent, + NvU32 hObject, + NvU32 hClass, + void *pAllocParams) +{ + return nvRmApiAlloc( + nvEvoGlobal.clientHandle, + hParent, + hObject, + hClass, + pAllocParams); +} + +static NvU32 NvPushImportRmApiFree( + NvPushDevicePtr pDevice, + NvU32 hParent, + NvU32 hObject) +{ + return nvRmApiFree( + nvEvoGlobal.clientHandle, + hParent, + hObject); +} + +static NvU32 NvPushImportRmApiMapMemoryDma( + NvPushDevicePtr pDevice, + NvU32 hDevice, + NvU32 hDma, + NvU32 hMemory, + NvU64 offset, + NvU64 length, + NvU32 flags, + NvU64 *pDmaOffset) +{ + return nvRmApiMapMemoryDma( + nvEvoGlobal.clientHandle, + hDevice, + hDma, + hMemory, + offset, + length, + flags, + pDmaOffset); +} + +static NvU32 NvPushImportRmApiUnmapMemoryDma( + NvPushDevicePtr pDevice, + NvU32 hDevice, + NvU32 hDma, + NvU32 hMemory, + NvU32 flags, + NvU64 dmaOffset) +{ + return nvRmApiUnmapMemoryDma( + nvEvoGlobal.clientHandle, + hDevice, + hDma, + hMemory, + flags, + dmaOffset); +} + +static NvU32 NvPushImportRmApiAllocMemory64( + NvPushDevicePtr pDevice, + NvU32 hParent, + NvU32 hMemory, + NvU32 hClass, + NvU32 flags, + void **ppAddress, + NvU64 *pLimit) +{ + return nvRmApiAllocMemory64( + nvEvoGlobal.clientHandle, + hParent, + hMemory, + hClass, + flags, + ppAddress, + pLimit); +} + +static NvU32 NvPushImportRmApiVidHeapControl( + NvPushDevicePtr pDevice, + void *pVidHeapControlParms) +{ + return nvRmApiVidHeapControl(pVidHeapControlParms); +} + +static NvU32 NvPushImportRmApiMapMemory( + NvPushDevicePtr pDevice, + NvU32 hDevice, + NvU32 hMemory, + NvU64 offset, + NvU64 length, + void **ppLinearAddress, + NvU32 flags) +{ + return nvRmApiMapMemory( + nvEvoGlobal.clientHandle, + hDevice, + hMemory, + offset, + length, + ppLinearAddress, + flags); +} + +static NvU32 NvPushImportRmApiUnmapMemory( + NvPushDevicePtr pDevice, + NvU32 hDevice, + NvU32 hMemory, + void *pLinearAddress, + NvU32 flags) +{ + return nvRmApiUnmapMemory( + nvEvoGlobal.clientHandle, + hDevice, + hMemory, + pLinearAddress, + flags); +} + +static NvU64 NvPushImportGetMilliSeconds( + NvPushDevicePtr pDevice) +{ + return (nvkms_get_usec() + 500) / 1000; +} + +static void NvPushImportYield( + NvPushDevicePtr pDevice) +{ + nvkms_yield(); +} + +static NvBool NvPushImportWaitForEvent( + NvPushDevicePtr pDevice, + NvPushImportEvent *pEvent, + NvU64 timeout) +{ + return FALSE; +} + +static void NvPushImportEmptyEventFifo( + NvPushDevicePtr pDevice, + NvPushImportEvent *pEvent) +{ + return; +} + +static void NvPushImportChannelErrorOccurred( + NvPushChannelPtr pChannel, + NvU32 channelErrCode) +{ + /* XXX TODO: implement me */ +} + +static void NvPushImportPushbufferWrapped( + NvPushChannelPtr pChannel) +{ + /* XXX TODO: implement me */ +} + +static void NvPushImportLogError( + NvPushDevicePtr pDevice, + const char *fmt, ...) +{ + const NVDevEvoRec *pDevEvo = pDevice->hostDevice; + + nvAssert(pDevEvo); + + va_list ap; + va_start(ap, fmt); + nvVEvoLog(EVO_LOG_ERROR, pDevEvo->gpuLogIndex, fmt, ap); + va_end(ap); +} + +#if defined(DEBUG) +static void NvPushImportLogNvDiss( + NvPushChannelPtr pChannel, + const char *fmt, ...) +{ + /* XXX TODO: implement me */ +} +#endif /* DEBUG */ + +static const NvPushImports NvKmsNvPushImports = { + NvPushImportRmApiControl, /* rmApiControl */ + NvPushImportRmApiAlloc, /* rmApiAlloc */ + NvPushImportRmApiFree, /* rmApiFree */ + NvPushImportRmApiMapMemoryDma, /* rmApiMapMemoryDma */ + NvPushImportRmApiUnmapMemoryDma, /* rmApiUnmapMemoryDma */ + NvPushImportRmApiAllocMemory64, /* rmApiAllocMemory64 */ + NvPushImportRmApiVidHeapControl, /* rmApiVidHeapControl */ + NvPushImportRmApiMapMemory, /* rmApiMapMemory */ + NvPushImportRmApiUnmapMemory, /* rmApiUnmapMemory */ + NvPushImportGetMilliSeconds, /* getMilliSeconds */ + NvPushImportYield, /* yield */ + NvPushImportWaitForEvent, /* waitForEvent */ + NvPushImportEmptyEventFifo, /* emptyEventFifo */ + NvPushImportChannelErrorOccurred, /* channelErrorOccurred */ + NvPushImportPushbufferWrapped, /* pushbufferWrapped */ + NvPushImportLogError, /* logError */ +#if defined(DEBUG) + NvPushImportLogNvDiss, /* logNvDiss */ +#endif +}; + +NvBool nvAllocNvPushDevice(NVDevEvoPtr pDevEvo) +{ + NvPushAllocDeviceParams params = { }; + NvU32 sd, h; + + params.hostDevice = pDevEvo; + params.pImports = &NvKmsNvPushImports; + params.clientHandle = nvEvoGlobal.clientHandle; + params.subDevice[0].deviceHandle = pDevEvo->deviceHandle; + params.numSubDevices = pDevEvo->numSubDevices; + + params.numClasses = pDevEvo->numClasses; + params.supportedClasses = pDevEvo->supportedClasses; + + for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { + params.subDevice[sd].handle = pDevEvo->pSubDevices[sd]->handle; + } + + params.amodel.config = NV_AMODEL_NONE; + params.isTegra = FALSE; + params.subDevice[0].gpuVASpace = pDevEvo->nvkmsGpuVASpace; + + ct_assert(sizeof(params.handlePool) == + sizeof(pDevEvo->nvPush.handlePool)); + + for (h = 0; h < ARRAY_LEN(pDevEvo->nvPush.handlePool); h++) { + pDevEvo->nvPush.handlePool[h] = + nvGenerateUnixRmHandle(&pDevEvo->handleAllocator); + params.handlePool[h] = pDevEvo->nvPush.handlePool[h]; + } + + if (!nvPushAllocDevice(¶ms, &pDevEvo->nvPush.device)) { + nvFreeNvPushDevice(pDevEvo); + return FALSE; + } + + return TRUE; +} + +void nvFreeNvPushDevice(NVDevEvoPtr pDevEvo) +{ + NvU32 h; + + nvPushFreeDevice(&pDevEvo->nvPush.device); + + for (h = 0; h < ARRAY_LEN(pDevEvo->nvPush.handlePool); h++) { + if (pDevEvo->nvPush.handlePool[h] != 0) { + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, + pDevEvo->nvPush.handlePool[h]); + pDevEvo->nvPush.handlePool[h] = 0; + } + } +} diff --git a/src/nvidia-modeset/src/nvkms-rm.c b/src/nvidia-modeset/src/nvkms-rm.c index 206c90df3..90ee5ce6e 100644 --- a/src/nvidia-modeset/src/nvkms-rm.c +++ b/src/nvidia-modeset/src/nvkms-rm.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -40,9 +40,13 @@ #include "nvkms-surface.h" #include "nvkms-vrr.h" +#include "nvkms-push.h" +#include "nvkms-difr.h" + #include "class/cl0002.h" /* NV01_CONTEXT_DMA */ #include "class/cl0005.h" /* NV01_EVENT */ +#include // NV01_MEMORY_VIRTUAL #include /* NV04_DISPLAY_COMMON */ #include /* NV01_MEMORY_SYSTEM */ #include /* NV01_MEMORY_FRAMEBUFFER_CONSOLE */ @@ -64,7 +68,6 @@ #include "class/cl917e.h" /* NV917E_OVERLAY_CHANNEL_DMA */ #include /* NV0000_CTRL_GPU_* */ -#include /* NV0073_CTRL_SYSTEM_GET_VRR_CONFIG */ #include /* NV0002_CTRL_CMD_BIND_CONTEXTDMA */ #include /* NV0073_CTRL_CMD_DFP_GET_INFO */ #include /* NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID */ @@ -76,7 +79,6 @@ #include /* NV2080_CTRL_CMD_BIOS_GET_NBSI */ #include /* NV2080_CTRL_CMD_BUS_GET_INFO */ #include /* NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION */ -#include /* NV2080_CTRL_CMD_GPU_GET_SW_FEATURES */ #include /* NV2080_CTRL_CMD_TIMER_GET_TIME */ #include /* NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT */ #include /* NV5070_CTRL_CMD_SET_RMFREE_FLAGS */ @@ -90,6 +92,35 @@ static NvU32 GetLegacyConnectorType(NVDispEvoPtr pDispEvo, NVDpyId dpyId); static void RmFreeEvoChannel(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel); +static NvBool EngineListCheckOneSubdevice(const NVEvoSubDeviceRec *pSubDevice, + NvU32 engineType) +{ + const NvU32 *engines = pSubDevice->supportedEngines; + int i; + + for (i = 0; i < pSubDevice->numEngines; i++) { + if (engines[i] == engineType) { + return TRUE; + } + } + + return FALSE; +} + +static NvBool EngineListCheck(const NVDevEvoRec *pDevEvo, NvU32 engineType) +{ + int sd; + + for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { + if (!EngineListCheckOneSubdevice(pDevEvo->pSubDevices[sd], + engineType)) { + return FALSE; + } + } + + return TRUE; +} + static NvBool QueryGpuCapabilities(NVDevEvoPtr pDevEvo) { NvBool ctxDmaCoherentAllowedDev = FALSE; @@ -100,9 +131,24 @@ static NvBool QueryGpuCapabilities(NVDevEvoPtr pDevEvo) pDevEvo->isHeadSurfaceSupported = FALSE; - pDevEvo->validResamplingMethodMask = - NVBIT(NVKMS_RESAMPLING_METHOD_BILINEAR) | - NVBIT(NVKMS_RESAMPLING_METHOD_NEAREST); + if (EngineListCheck(pDevEvo, NV2080_ENGINE_TYPE_GRAPHICS)) { + NV0080_CTRL_GR_GET_CAPS_V2_PARAMS grCaps = { 0 }; + + ret = nvRmApiControl(nvEvoGlobal.clientHandle, + pDevEvo->deviceHandle, + NV0080_CTRL_CMD_GR_GET_CAPS_V2, + &grCaps, + sizeof(grCaps)); + + if (ret != NVOS_STATUS_SUCCESS) { + return FALSE; + } + + /* Assume headSurface is supported if there is a graphics engine + * and headSurface support is included in the NVKMS build. + */ + pDevEvo->isHeadSurfaceSupported = NVKMS_INCLUDE_HEADSURFACE; + } /* ctxDma{,Non}CoherentAllowed */ @@ -237,7 +283,10 @@ static void FreeDisplay(NVDispEvoPtr pDispEvo) } for (head = 0; head < ARRAY_LEN(pDispEvo->pSwapGroup); head++) { - nvAssert(pDispEvo->pSwapGroup[head] == NULL); +#if defined(DEBUG) + const NvU32 apiHead = nvHardwareHeadToApiHead(head); + nvAssert(pDispEvo->pSwapGroup[apiHead] == NULL); +#endif nvAssert(nvListIsEmpty(&pDispEvo->headState[head].vblankCallbackList)); } @@ -268,8 +317,6 @@ static inline NVDispEvoPtr AllocDisplay(NVDevEvoPtr pDevEvo) pDispEvo->framelock.currentServerHead = NV_INVALID_HEAD; for (head = 0; head < ARRAY_LEN(pDispEvo->headState); head++) { - pDispEvo->headState[head].activeDpys = nvEmptyDpyIdList(); - pDispEvo->headState[head].attributes = NV_EVO_DEFAULT_ATTRIBUTES_SET; nvListInit(&pDispEvo->headState[head].vblankCallbackList); } @@ -831,27 +878,45 @@ static NvBool AllocConnectors(NVDispEvoPtr pDispEvo) return FALSE; } +static NvBool IsFlexibleWindowMapping(NvU32 windowHeadMask) +{ + return (windowHeadMask == + NV0073_CTRL_SPECIFIC_FLEXIBLE_HEAD_WINDOW_ASSIGNMENT); +} /*! * Query the number of heads and save the result in pDevEvo->numHeads. + * Get window head assignment and save it in pDevEvo->headForWindow[win]. * * Query the number of heads on each pDisp of the pDev and limit to - * the minimum across all pDisps. Query the headMask on each pDisp - * and take the intersection across pDisps. Limit the number of heads - * to the number of bits in the headMask. + * the minimum across all pDisps. Query the headMask on each pDisp and + * take the intersection across pDisps. Query the window-head assignment + * and if it is fully flexible, assign WINDOWs (2N) and (2N + 1) to HEAD N. + * Otherwise, use the queried assignment. + * + * Limit the number of heads to the number of bits in the headMask. Ignore + * the heads which don't have any windows assigned to them and heads which + * create holes in the headMask. If a head which has assigned windows gets + * pruned out, assign NV_INVALID_HEAD to those windows. * * \param[in,out] pDev This is the device pointer; the pDisps within * it are used to query per-GPU information. * The result is written to pDevEvo->numHeads. * - * \return Return TRUE if numHeads could be correctly assigned; - * return FALSE if numHeads could not be queried. + * \return Return TRUE if numHeads are correctly queried and + * window-head assignment is done. + * Return FALSE if numHeads or window-head assignment + * could not be queried. */ -static NvBool ProbeHeadCount(NVDevEvoPtr pDevEvo) +static NvBool ProbeHeadCountAndWindowAssignment(NVDevEvoPtr pDevEvo) { NvU32 numHeads = 0, headMask = 0; + NvU32 headsWithWindowsMask = 0; int sd, head, numBits; NVDispEvoPtr pDispEvo; + NvBool first = TRUE; + NvBool isFlexibleWindowMapping = NV_TRUE; + NvU32 win; NvU32 ret; pDevEvo->numHeads = 0; @@ -860,6 +925,7 @@ static NvBool ProbeHeadCount(NVDevEvoPtr pDevEvo) NV0073_CTRL_SYSTEM_GET_NUM_HEADS_PARAMS numHeadsParams = { 0 }; NV0073_CTRL_SPECIFIC_GET_ALL_HEAD_MASK_PARAMS headMaskParams = { 0 }; + NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS winHeadAssignParams = { }; numHeadsParams.subDeviceInstance = sd; numHeadsParams.flags = 0; @@ -922,8 +988,82 @@ static NvBool ProbeHeadCount(NVDevEvoPtr pDevEvo) headMask = intersectedHeadMask; } } + + winHeadAssignParams.subDeviceInstance = sd; + ret = nvRmApiControl(nvEvoGlobal.clientHandle, + pDevEvo->displayCommonHandle, + NV0073_CTRL_CMD_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT, + &winHeadAssignParams, sizeof(winHeadAssignParams)); + + if (ret == NVOS_STATUS_SUCCESS) { + for (win = 0; win < NVKMS_MAX_WINDOWS_PER_DISP; win++) { + NvU32 windowHeadMask = winHeadAssignParams.windowHeadMask[win]; + + if ((win == 0) && first) { + isFlexibleWindowMapping = IsFlexibleWindowMapping(windowHeadMask); + } else if (isFlexibleWindowMapping) { + /* + * Currently, if one window is completely flexible, then all are. + * In case of fully flexible window mapping, if windowHeadMask is + * zero for a window, then that window is not present in HW. + */ + nvAssert(!windowHeadMask || (isFlexibleWindowMapping == + IsFlexibleWindowMapping(windowHeadMask))); + } + + /* + * For custom window mapping, if windowHeadMask is 0, then head + * is not assigned to this window. For flexible window mapping, + * if windowHeadMask is 0, then the window is not present in HW. + */ + if (windowHeadMask == 0) { + continue; + } + + if (isFlexibleWindowMapping) { + /* + * TODO: For now assign WINDOWs (2N) and (2N + 1) to HEAD N when + * completely flexible window assignment is specified by window + * head assignment mask. + */ + head = win >> 1; + windowHeadMask = NVBIT_TYPE(head, NvU8); + nvAssert(head < numHeads); + } else { + // We don't support same window assigned to multiple heads. + nvAssert(ONEBITSET(windowHeadMask)); + + head = BIT_IDX_32(windowHeadMask); + } + + if (first) { + pDevEvo->headForWindow[win] = head; + headsWithWindowsMask |= windowHeadMask; + } else { + nvAssert(pDevEvo->headForWindow[win] == head); + } + } + } else if (ret != NVOS_STATUS_ERROR_NOT_SUPPORTED) { + nvEvoLogDevDebug(pDevEvo, EVO_LOG_ERROR, + "Failed to get window-head assignment"); + return FALSE; + } else { + // Pre-Volta, we don't need to populate pDevEvo->headForWindow[] and + // each HW head has a window assigned. + headsWithWindowsMask = headMask; + } + + if (first) { + first = FALSE; + } } + /* Check whether heads which have windows assigned are actually present in HW */ + nvAssert(!(~headMask & headsWithWindowsMask)); + + /* Intersect heads present in HW with heads which have windows assigned */ + headMask &= headsWithWindowsMask; + /* clamp numHeads to the number of bits in headMask */ numBits = nvPopCount32(headMask); @@ -961,6 +1101,18 @@ static NvBool ProbeHeadCount(NVDevEvoPtr pDevEvo) pDevEvo->numHeads = numHeads; + /* + * If a head which has assigned windows gets pruned out, assign + * NV_INVALID_HEAD to those windows. + */ + for (win = 0; win < NVKMS_MAX_WINDOWS_PER_DISP; win++) { + if ((pDevEvo->headForWindow[win] == NV_INVALID_HEAD) || + (pDevEvo->headForWindow[win] < pDevEvo->numHeads)) { + continue; + } + pDevEvo->headForWindow[win] = NV_INVALID_HEAD; + } + return TRUE; } @@ -971,7 +1123,6 @@ static void MarkConnectorBootHeadActive(NVDispEvoPtr pDispEvo, NvU32 head) { NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; NVDpyId displayId, rootPortId; - NVDpyEvoPtr pDpyEvo; NVConnectorEvoPtr pConnectorEvo; NVDispHeadStateEvoPtr pHeadState; NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS params = { 0 }; @@ -1031,19 +1182,10 @@ static void MarkConnectorBootHeadActive(NVDispEvoPtr pDispEvo, NvU32 head) } nvAssert((pConnectorEvo->or.mask & NVBIT(params.index)) != 0x0); - // Use the pDpyEvo for the connector, since we may not have one for - // display id if it's a dynamic one. - pDpyEvo = nvGetDpyEvoFromDispEvo(pDispEvo, pConnectorEvo->displayId); - pHeadState = &pDispEvo->headState[head]; - nvAssert(pDpyEvo->apiHead == NV_INVALID_HEAD); nvAssert(!nvHeadIsActive(pDispEvo, head)); - pDpyEvo->apiHead = nvHardwareHeadToApiHead(head); - - pHeadState->activeDpys = - nvAddDpyIdToEmptyDpyIdList(pConnectorEvo->displayId); pHeadState->pConnectorEvo = pConnectorEvo; pHeadState->activeRmId = nvDpyIdToNvU32(displayId); @@ -1309,15 +1451,18 @@ static NvBool AllocDPSerializerDpys(NVConnectorEvoPtr pConnectorEvo) supportsMST = pConnectorEvo->dpSerializerCaps.supportsMST; numHeads = pConnectorEvo->pDispEvo->pDevEvo->numHeads; for (i = 0; i < numHeads && supportsMST; i++) { + NVDpyEvoPtr pDpyEvo = NULL; NvBool dynamicDpyCreated = FALSE; char address[5] = { }; nvkms_snprintf(address, sizeof(address), "0.%d", i + 1); - if ((nvGetDPMSTDpyEvo(pConnectorEvo, address, - &dynamicDpyCreated) == NULL) || - !dynamicDpyCreated) { + pDpyEvo = nvGetDPMSTDpyEvo(pConnectorEvo, address, + &dynamicDpyCreated); + if ((pDpyEvo == NULL) || !dynamicDpyCreated) { return FALSE; } + + pDpyEvo->dp.serializerStreamIndex = i; } return TRUE; @@ -1439,6 +1584,32 @@ static NvBool RegisterDispCallback(NVOS10_EVENT_KERNEL_CALLBACK_EX *cb, handle, func, event); } +static void +DifrPrefetchEventDeferredWork(void *dataPtr, NvU32 dataU32) +{ + NVDevEvoPtr pDevEvo = dataPtr; + size_t l2CacheSize = (size_t)dataU32; + NvU32 status; + + nvAssert(pDevEvo->pDifrState); + + status = nvDIFRPrefetchSurfaces(pDevEvo->pDifrState, l2CacheSize); + nvDIFRSendPrefetchResponse(pDevEvo->pDifrState, status); +} + +static void DifrPrefetchEvent(void *arg, void *pEventDataVoid, + NvU32 hEvent, NvU32 Data, NV_STATUS Status) +{ + Nv2080LpwrDifrPrefetchNotification *notif = + (Nv2080LpwrDifrPrefetchNotification *)pEventDataVoid; + + (void)nvkms_alloc_timer_with_ref_ptr( + DifrPrefetchEventDeferredWork, /* callback */ + arg, /* argument (this is a ref_ptr to a pDevEvo) */ + notif->l2CacheSize, /* dataU32 */ + 0); /* timeout: schedule the work immediately */ +} + enum NvKmsAllocDeviceStatus nvRmAllocDisplays(NVDevEvoPtr pDevEvo) { NVDispEvoPtr pDispEvo; @@ -1502,7 +1673,7 @@ enum NvKmsAllocDeviceStatus nvRmAllocDisplays(NVDevEvoPtr pDevEvo) goto fail; } - if (!ProbeHeadCount(pDevEvo)) { + if (!ProbeHeadCountAndWindowAssignment(pDevEvo)) { status = NVKMS_ALLOC_DEVICE_STATUS_NO_HARDWARE_AVAILABLE; goto fail; } @@ -1680,9 +1851,8 @@ void nvRmDestroyDisplays(NVDevEvoPtr pDevEvo) FreeDisplays(pDevEvo); - if (pDevEvo->supportsSyncpts) { - nvFree(pDevEvo->preSyncptTable); - } + nvFree(pDevEvo->preSyncptTable); + pDevEvo->preSyncptTable = NULL; if (pDevEvo->displayCommonHandle != 0) { ret = nvRmApiFree(nvEvoGlobal.clientHandle, @@ -3308,9 +3478,15 @@ static void FreeCoreRGSyncpts(NVDevEvoPtr pDevEvo) return; } + /* We can get here in teardown cases from alloc failures */ + if (pDevEvo->nDispEvo == 0) { + return; + } + /* If Syncpts are supported, we're on Orin, which only has one display. */ nvAssert(pDevEvo->nDispEvo == 1); pDispEvo = pDevEvo->pDispEvo[0]; + /* For each Head: */ for (int i = 0; i < pDevEvo->numHeads; i++) { /* Free all core RG syncpts. */ @@ -4232,6 +4408,46 @@ fail: return FALSE; } +static void FreeGpuVASpace(NVDevEvoPtr pDevEvo) +{ + if (pDevEvo->nvkmsGpuVASpace != 0) { + nvRmApiFree(nvEvoGlobal.clientHandle, + pDevEvo->deviceHandle, + pDevEvo->nvkmsGpuVASpace); + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, + pDevEvo->nvkmsGpuVASpace); + pDevEvo->nvkmsGpuVASpace = 0; + } +} + +static NvBool AllocGpuVASpace(NVDevEvoPtr pDevEvo) +{ + NvU32 ret; + NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS memoryVirtualParams = { }; + + pDevEvo->nvkmsGpuVASpace = + nvGenerateUnixRmHandle(&pDevEvo->handleAllocator); + + memoryVirtualParams.offset = 0; + memoryVirtualParams.limit = 0; // no limit on VA space + memoryVirtualParams.hVASpace = 0; // client's default VA space + + ret = nvRmApiAlloc(nvEvoGlobal.clientHandle, + pDevEvo->deviceHandle, + pDevEvo->nvkmsGpuVASpace, + NV01_MEMORY_VIRTUAL, + &memoryVirtualParams); + + if (ret != NVOS_STATUS_SUCCESS) { + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, + pDevEvo->nvkmsGpuVASpace); + pDevEvo->nvkmsGpuVASpace = 0; + return FALSE; + } + + return TRUE; +} + static void NonStallInterruptCallback( void *arg, void *pEventDataVoid, @@ -4441,6 +4657,14 @@ NvBool nvRmAllocDeviceEvo(NVDevEvoPtr pDevEvo, goto failure; } + if (!AllocGpuVASpace(pDevEvo)) { + goto failure; + } + + if (!nvAllocNvPushDevice(pDevEvo)) { + goto failure; + } + return TRUE; failure: @@ -4452,6 +4676,10 @@ void nvRmFreeDeviceEvo(NVDevEvoPtr pDevEvo) { NvU32 sd; + nvFreeNvPushDevice(pDevEvo); + + FreeGpuVASpace(pDevEvo); + UnregisterNonStallInterruptCallback(pDevEvo); nvFree(pDevEvo->supportedClasses); @@ -4478,6 +4706,78 @@ void nvRmFreeDeviceEvo(NVDevEvoPtr pDevEvo) CloseDevice(pDevEvo); } +/* + * Set up DIFR notifier listener to drive framebuffer prefetching once the + * h/w gets idle enough. + */ +NvBool nvRmRegisterDIFREventHandler(NVDevEvoPtr pDevEvo) +{ + pDevEvo->difrPrefetchEventHandler = + nvGenerateUnixRmHandle(&pDevEvo->handleAllocator); + + if (pDevEvo->difrPrefetchEventHandler != 0) { + NvBool registered; + + /* + * Allocate event callback. + */ + registered = nvRmRegisterCallback( + pDevEvo, + &pDevEvo->difrPrefetchCallback, + pDevEvo->ref_ptr, + pDevEvo->pSubDevices[0]->handle, + pDevEvo->difrPrefetchEventHandler, + DifrPrefetchEvent, + NV2080_NOTIFIERS_LPWR_DIFR_PREFETCH_REQUEST); + + /* + * Configure event notification. + */ + if (registered) { + NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS prefetchEventParams = { 0 }; + + prefetchEventParams.event = NV2080_NOTIFIERS_LPWR_DIFR_PREFETCH_REQUEST; + prefetchEventParams.action = NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT; + + if (nvRmApiControl(nvEvoGlobal.clientHandle, + pDevEvo->pSubDevices[0]->handle, + NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION, + &prefetchEventParams, + sizeof(prefetchEventParams)) + == NVOS_STATUS_SUCCESS) { + return TRUE; + + } + } + nvRmUnregisterDIFREventHandler(pDevEvo); + } + return FALSE; +} + +void nvRmUnregisterDIFREventHandler(NVDevEvoPtr pDevEvo) +{ + if (pDevEvo->difrPrefetchEventHandler != 0) { + NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS prefetchEventParams = { 0 }; + + prefetchEventParams.event = NV2080_NOTIFIERS_LPWR_DIFR_PREFETCH_REQUEST; + prefetchEventParams.action = NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE; + + nvRmApiControl(nvEvoGlobal.clientHandle, + pDevEvo->pSubDevices[0]->handle, + NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION, + &prefetchEventParams, + sizeof(prefetchEventParams)); + + nvRmApiFree(nvEvoGlobal.clientHandle, + pDevEvo->pSubDevices[0]->handle, + pDevEvo->difrPrefetchEventHandler); + + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, + pDevEvo->difrPrefetchEventHandler); + pDevEvo->difrPrefetchEventHandler = 0; + } +} + /*! * Determine whether all the dpys in the dpyIdList can be activated together. @@ -4701,12 +5001,166 @@ done: nvFreeUnixRmHandle(&pDevEvo->handleAllocator, hMemory); } -NvBool nvRmQueryDpAuxLog(NVDispEvoRec *pDispEvo, NvS64 *pValue) +static void LogAuxPacket(const NVDispEvoRec *pDispEvo, const DPAUXPACKET *pkt) { - *pValue = FALSE; - return TRUE; + const char *req, *rep; + char str[DP_MAX_MSG_SIZE * 3 + 1]; + char *p = str; + int i; + + switch (DRF_VAL(_DP, _AUXLOGGER, _REQUEST_TYPE, pkt->auxEvents)) { + case NV_DP_AUXLOGGER_REQUEST_TYPE_AUXWR: + req = "auxwr"; + break; + case NV_DP_AUXLOGGER_REQUEST_TYPE_AUXRD: + req = "auxrd"; + break; + case NV_DP_AUXLOGGER_REQUEST_TYPE_MOTWR: + // MOT is "middle of transaction", which is just another type of i2c + // access. + req = "motwr"; + break; + case NV_DP_AUXLOGGER_REQUEST_TYPE_I2CWR: + req = "i2cwr"; + break; + case NV_DP_AUXLOGGER_REQUEST_TYPE_MOTRD: + req = "motrd"; + break; + case NV_DP_AUXLOGGER_REQUEST_TYPE_I2CRD: + req = "i2crd"; + break; + default: + // Only log I2C and AUX transactions. + return; + } + + switch (DRF_VAL(_DP, _AUXLOGGER, _REPLY_TYPE, pkt->auxEvents)) { + case NV_DP_AUXLOGGER_REPLY_TYPE_NULL: + rep = "none"; + break; + case NV_DP_AUXLOGGER_REPLY_TYPE_SB_ACK: + rep = "sb_ack"; + break; + case NV_DP_AUXLOGGER_REPLY_TYPE_RETRY: + rep = "retry"; + break; + case NV_DP_AUXLOGGER_REPLY_TYPE_TIMEOUT: + rep = "timeout"; + break; + case NV_DP_AUXLOGGER_REPLY_TYPE_DEFER: + rep = "defer"; + break; + case NV_DP_AUXLOGGER_REPLY_TYPE_DEFER_TO: + rep = "defer_to"; + break; + case NV_DP_AUXLOGGER_REPLY_TYPE_ACK: + rep = "ack"; + break; + case NV_DP_AUXLOGGER_REPLY_TYPE_ERROR: + rep = "error"; + break; + default: + case NV_DP_AUXLOGGER_REPLY_TYPE_UNKNOWN: + rep = "unknown"; + break; + } + + for (i = 0; i < pkt->auxMessageReplySize; i++) { + p += nvkms_snprintf(p, str + sizeof(str) - p, "%02x ", + pkt->auxPacket[i]); + } + + nvAssert(p < str + sizeof(str)); + *p = '\0'; + + nvEvoLogDisp(pDispEvo, EVO_LOG_INFO, + "%04u: port %u @ 0x%05x: [%10u] %s %2u, [%10u] %-8s %s", + pkt->auxCount, pkt->auxOutPort, pkt->auxPortAddress, + pkt->auxRequestTimeStamp, req, + pkt->auxMessageReqSize, + pkt->auxReplyTimeStamp, rep, + str); } +/*! + * This "attribute" queries the RM DisplayPort AUX channel log and dumps it to + * the kernel log. It returns a value of TRUE if any RM AUX transactions were + * logged, and FALSE otherwise. + * + * This attribute is intended to be queried in a loop as long as it reads TRUE. + * + * \return TRUE if the query succeeded (even if no events were logged). + * \return FALSE if the query failed. + */ +NvBool nvRmQueryDpAuxLog(NVDispEvoRec *pDispEvo, NvS64 *pValue) +{ + NV0073_CTRL_CMD_DP_GET_AUXLOGGER_BUFFER_DATA_PARAMS *pParams = + nvCalloc(sizeof(*pParams), 1); + NvU32 status; + int i; + NvBool ret = FALSE; + + pDispEvo->dpAuxLoggingEnabled = TRUE; + *pValue = FALSE; + + if (!pParams) { + return FALSE; + } + + pParams->subDeviceInstance = pDispEvo->displayOwner; + pParams->dpAuxBufferReadSize = MAX_LOGS_PER_POLL; + + status = nvRmApiControl(nvEvoGlobal.clientHandle, + pDispEvo->pDevEvo->displayCommonHandle, + NV0073_CTRL_CMD_DP_GET_AUXLOGGER_BUFFER_DATA, + pParams, sizeof(*pParams)); + if (status != NVOS_STATUS_SUCCESS) { + goto done; + } + + nvAssert(pParams->dpNumMessagesRead <= MAX_LOGS_PER_POLL); + for (i = 0; i < pParams->dpNumMessagesRead; i++) { + const DPAUXPACKET *pkt = &pParams->dpAuxBuffer[i]; + + switch (DRF_VAL(_DP, _AUXLOGGER, _EVENT_TYPE, pkt->auxEvents)) { + case NV_DP_AUXLOGGER_EVENT_TYPE_AUX: + LogAuxPacket(pDispEvo, pkt); + break; + case NV_DP_AUXLOGGER_EVENT_TYPE_HOT_PLUG: + nvEvoLogDisp(pDispEvo, EVO_LOG_INFO, + "%04u: port %u [%10u] hotplug", + pkt->auxCount, pkt->auxOutPort, + pkt->auxRequestTimeStamp); + break; + case NV_DP_AUXLOGGER_EVENT_TYPE_HOT_UNPLUG: + nvEvoLogDisp(pDispEvo, EVO_LOG_INFO, + "%04u: port %u [%10u] unplug", + pkt->auxCount, pkt->auxOutPort, + pkt->auxRequestTimeStamp); + break; + case NV_DP_AUXLOGGER_EVENT_TYPE_IRQ: + nvEvoLogDisp(pDispEvo, EVO_LOG_INFO, + "%04u: port %u [%10u] irq", + pkt->auxCount, pkt->auxOutPort, + pkt->auxRequestTimeStamp); + break; + default: + nvEvoLogDisp(pDispEvo, EVO_LOG_INFO, + "%04u: port %u [%10u] unknown event", + pkt->auxCount, pkt->auxOutPort, + pkt->auxRequestTimeStamp); + break; + } + + *pValue = TRUE; + } + + ret = TRUE; + +done: + nvFree(pParams); + return ret; +} /*! * Return the GPU's current PTIMER, or 0 if the query fails. diff --git a/src/nvidia-modeset/src/nvkms-stereo.c b/src/nvidia-modeset/src/nvkms-stereo.c new file mode 100644 index 000000000..27cdd0a8c --- /dev/null +++ b/src/nvidia-modeset/src/nvkms-stereo.c @@ -0,0 +1,62 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvkms-evo.h" +#include "nvkms-stereo.h" + +NvBool nvSetStereo(const NVDispEvoRec *pDispEvo, + const NvU32 apiHead, + NvBool enable) +{ + NvU32 head; + NvU32 primaryHead = + nvGetPrimaryHwHead(pDispEvo, apiHead); + + if (primaryHead == NV_INVALID_HEAD) { + return FALSE; + } + + /* Only one head can drive stereo, make sure stereo is disabled + * on all the seconday hardware heads. */ + FOR_EACH_EVO_HW_HEAD(pDispEvo, apiHead, head) { + if (head == primaryHead) { + continue; + } + if(!nvSetStereoEvo(pDispEvo, head, FALSE)) { + nvAssert(!"Failed to disable stereo on secondary head"); + } + } + + return nvSetStereoEvo(pDispEvo, primaryHead, enable); +} + +NvBool nvGetStereo(const NVDispEvoRec *pDispEvo, const NvU32 apiHead) +{ + NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); + + if (head == NV_INVALID_HEAD) { + return FALSE; + } + + return nvGetStereoEvo(pDispEvo, head); +} diff --git a/src/nvidia-modeset/src/nvkms-surface.c b/src/nvidia-modeset/src/nvkms-surface.c index 95f353865..ce2f95a2c 100644 --- a/src/nvidia-modeset/src/nvkms-surface.c +++ b/src/nvidia-modeset/src/nvkms-surface.c @@ -27,6 +27,8 @@ #include "nvkms-utils.h" #include "nvkms-flip.h" #include "nvkms-private.h" +#include "nvkms-headsurface.h" +#include "nvkms-headsurface-swapgroup.h" #include "nvos.h" // NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_FROM_FD @@ -84,6 +86,9 @@ static void FreeSurfaceEvoRm(NVDevEvoPtr pDevEvo, NVSurfaceEvoPtr pSurfaceEvo) } } + nvHsUnmapSurfaceFromDevice(pDevEvo, + firstPlaneRmHandle, + pSurfaceEvo->gpuAddress); } FOR_ALL_VALID_PLANES(planeIndex, pSurfaceEvo) { @@ -506,6 +511,29 @@ void nvEvoRegisterSurface(NVDevEvoPtr pDevEvo, pSurfaceEvo->requireCtxDma = !pRequest->noDisplayHardwareAccess; pSurfaceEvo->noDisplayCaching = pRequest->noDisplayCaching; + /* + * Map the surface into the GPU's virtual address space, for use with + * headSurface. If the surface may be used for semaphores, headSurface will + * need to write to it through the graphics channel. Force a writable GPU + * mapping. + * + * Map the first plane of the surface only into the GPU's address space. + * We would have already rejected multi-planar semaphore requests earlier. + */ + if (nisoMemory) { + hsMapPermissions = NvHsMapPermissionsReadWrite; + } + + pSurfaceEvo->gpuAddress = nvHsMapSurfaceToDevice( + pDevEvo, + pSurfaceEvo->planes[0].rmHandle, + pRequest->planes[0].rmObjectSizeInBytes, + hsMapPermissions); + + if (pSurfaceEvo->gpuAddress == NV_HS_BAD_GPU_ADDRESS) { + goto fail; + } + /* * Map the first plane of the surface only into the CPU's address space. * This is the only valid plane since we would have already rejected @@ -1113,13 +1141,14 @@ static NVSurfaceEvoPtr GetSurfaceFromHandle( const NVDevEvoRec *pDevEvo, const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, const NvKmsSurfaceHandle surfaceHandle, - const NVEvoChannelMask channelMask, + const NvBool isUsedByCursorChannel, + const NvBool isUsedByLayerChannel, const NvBool requireCtxDma) { NVSurfaceEvoPtr pSurfaceEvo = nvEvoGetPointerFromApiHandle(pOpenDevSurfaceHandles, surfaceHandle); - nvAssert(requireCtxDma || !channelMask); + nvAssert(requireCtxDma || (!isUsedByCursorChannel && !isUsedByLayerChannel)); if (pSurfaceEvo == NULL) { return NULL; @@ -1134,8 +1163,7 @@ static NVSurfaceEvoPtr GetSurfaceFromHandle( } /* Validate that the surface can be used as a cursor image */ - if ((channelMask & - NV_EVO_CHANNEL_MASK_CURSOR_ALL) && + if (isUsedByCursorChannel && !pDevEvo->hal->ValidateCursorSurface(pDevEvo, pSurfaceEvo)) { return NULL; } @@ -1149,7 +1177,7 @@ static NVSurfaceEvoPtr GetSurfaceFromHandle( * know if nvEvoGetHeadSetStoragePitchValue() was protecting us from any * surface dimensions that could cause trouble for the 3d engine. */ - if ((channelMask & ~NV_EVO_CHANNEL_MASK_CURSOR_ALL) || !requireCtxDma) { + if (isUsedByLayerChannel || !requireCtxDma) { NvU8 planeIndex; FOR_ALL_VALID_PLANES(planeIndex, pSurfaceEvo) { @@ -1169,12 +1197,14 @@ NVSurfaceEvoPtr nvEvoGetSurfaceFromHandle( const NVDevEvoRec *pDevEvo, const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, const NvKmsSurfaceHandle surfaceHandle, - const NVEvoChannelMask channelMask) + const NvBool isUsedByCursorChannel, + const NvBool isUsedByLayerChannel) { return GetSurfaceFromHandle(pDevEvo, pOpenDevSurfaceHandles, surfaceHandle, - channelMask, + isUsedByCursorChannel, + isUsedByLayerChannel, TRUE /* requireCtxDma */); } @@ -1185,7 +1215,9 @@ NVSurfaceEvoPtr nvEvoGetSurfaceFromHandleNoCtxDmaOk( { return GetSurfaceFromHandle(pDevEvo, pOpenDevSurfaceHandles, - surfaceHandle, 0x0 /* channelMask */, + surfaceHandle, + FALSE /* isUsedByCursorChannel */, + FALSE /* isUsedByLayerChannel */, FALSE /* requireCtxDma */); } @@ -1247,6 +1279,8 @@ void nvEvoUnregisterDeferredRequestFifo( nvAssert(pDeferredRequestFifo->fifo != NULL); nvAssert(pDeferredRequestFifo->pSurfaceEvo != NULL); + nvHsLeaveSwapGroup(pDevEvo, pDeferredRequestFifo, FALSE /* teardown */); + nvRmApiUnmapMemory( nvEvoGlobal.clientHandle, pDevEvo->deviceHandle, diff --git a/src/nvidia-modeset/src/nvkms-vrr.c b/src/nvidia-modeset/src/nvkms-vrr.c index 72b12aa3d..5467876e5 100644 --- a/src/nvidia-modeset/src/nvkms-vrr.c +++ b/src/nvidia-modeset/src/nvkms-vrr.c @@ -155,11 +155,14 @@ void nvCancelVrrFrameReleaseTimers( return; } -void nvSetNextVrrFlipTypeAndIndex( - NVDevEvoPtr pDevEvo, - struct NvKmsFlipReply *reply) +enum NvKmsVrrFlipType nvGetActiveVrrType(const NVDevEvoRec *pDevEvo) { - return; + return NV_KMS_VRR_FLIP_NON_VRR; +} + +NvS32 nvIncVrrSemaphoreIndex(NVDevEvoPtr pDevEvo) +{ + return -1; } void nvTriggerVrrUnstallMoveCursor( diff --git a/src/nvidia-modeset/src/nvkms.c b/src/nvidia-modeset/src/nvkms.c index c3a4f96a8..a0d57dde7 100644 --- a/src/nvidia-modeset/src/nvkms.c +++ b/src/nvidia-modeset/src/nvkms.c @@ -40,8 +40,9 @@ #include "nvkms-surface.h" #include "nvkms-3dvision.h" #include "nvkms-ioctl.h" -#include "nvkms-cursor.h" /* nvSetCursorImage, nvEvoMoveCursor */ -#include "nvkms-flip.h" /* nvFlipEvo */ +#include "nvkms-headsurface.h" +#include "nvkms-headsurface-ioctl.h" +#include "nvkms-headsurface-swapgroup.h" #include "nvkms-vrr.h" #include "dp/nvdp-connector.h" @@ -115,6 +116,10 @@ enum NvKmsUnicastEventType { * NVKMS_IOCTL_JOIN_SWAP_GROUP */ NvKmsUnicastEventTypeDeferredRequest, + /* Used by: + * NVKMS_IOCTL_NOTIFY_VBLANK */ + NvKmsUnicastEventTypeVblankNotification, + /* Undefined, this indicates the unicast fd is available for use. */ NvKmsUnicastEventTypeUndefined, }; @@ -137,6 +142,7 @@ struct NvKmsPerOpenDisp { NVEvoApiHandlesRec connectorHandles; struct NvKmsPerOpenConnector connector[NVKMS_MAX_CONNECTORS_PER_DISP]; NVEvoApiHandlesRec vblankSyncObjectHandles[NVKMS_MAX_HEADS_PER_DISP]; + NVEvoApiHandlesRec vblankCallbackHandles[NVKMS_MAX_HEADS_PER_DISP]; }; struct NvKmsPerOpenDev { @@ -149,6 +155,7 @@ struct NvKmsPerOpenDev { struct NvKmsPerOpenDisp disp[NVKMS_MAX_SUBDEVICES]; NvBool isPrivileged; NVEvoApiHandlesRec deferredRequestFifoHandles; + NVEvoApiHandlesRec swapGroupHandles; }; struct NvKmsPerOpenEventListEntry { @@ -198,6 +205,12 @@ struct NvKmsPerOpen { struct { NVDeferredRequestFifoPtr pDeferredRequestFifo; } deferred; + + struct { + NvKmsGenericHandle hCallback; + struct NvKmsPerOpenDisp *pOpenDisp; + NvU32 head; + } vblankNotification; } e; } unicastEvent; }; @@ -656,6 +669,9 @@ static void ClearPerOpenDisp( struct NvKmsPerOpenConnector *pOpenConnector; NvKmsGenericHandle connector; + NVVBlankCallbackPtr pCallbackData; + NvKmsGenericHandle callback; + FreePerOpenFrameLock(pOpen, pOpenDisp); FOR_ALL_POINTERS_IN_EVO_API_HANDLES(&pOpenDisp->connectorHandles, @@ -668,6 +684,12 @@ static void ClearPerOpenDisp( for (NvU32 i = 0; i < NVKMS_MAX_HEADS_PER_DISP; i++) { nvEvoDestroyApiHandles(&pOpenDisp->vblankSyncObjectHandles[i]); + + FOR_ALL_POINTERS_IN_EVO_API_HANDLES(&pOpenDisp->vblankCallbackHandles[i], + pCallbackData, callback) { + nvRemoveUnicastEvent(pCallbackData->pUserData); + } + nvEvoDestroyApiHandles(&pOpenDisp->vblankCallbackHandles[i]); } nvEvoDestroyApiHandle(&pOpenDev->dispHandles, pOpenDisp->nvKmsApiHandle); @@ -733,6 +755,17 @@ static NvBool InitPerOpenDisp( } } + /* Initialize the vblankCallbackHandles for each head. + * + * The limit of VBLANK_SYNC_OBJECTS_PER_HEAD doesn't really apply here, but + * we need something. */ + for (NvU32 i = 0; i < NVKMS_MAX_HEADS_PER_DISP; i++) { + if (!nvEvoInitApiHandles(&pOpenDisp->vblankCallbackHandles[i], + NVKMS_MAX_VBLANK_SYNC_OBJECTS_PER_HEAD)) { + goto fail; + } + } + if (!AllocPerOpenFrameLock(pOpen, pOpenDisp)) { goto fail; } @@ -744,6 +777,28 @@ fail: return FALSE; } +/*! + * Free any SwapGroups tracked by this pOpenDev. + */ +static void FreeSwapGroups(struct NvKmsPerOpenDev *pOpenDev) +{ + NVSwapGroupRec *pSwapGroup; + NvKmsSwapGroupHandle handle; + NVDevEvoPtr pDevEvo = pOpenDev->pDevEvo; + + FOR_ALL_POINTERS_IN_EVO_API_HANDLES(&pOpenDev->swapGroupHandles, + pSwapGroup, + handle) { + nvEvoDestroyApiHandle(&pOpenDev->swapGroupHandles, handle); + + if (pDevEvo->modesetOwner == pOpenDev) { + nvHsFreeSwapGroup(pDevEvo, pSwapGroup); + } else { + nvHsDecrementSwapGroupRefCnt(pSwapGroup); + } + } +} + /*! * Check that the NvKmsPermissions make sense. */ @@ -884,8 +939,6 @@ static NvBool GrabModesetOwnership(struct NvKmsPerOpenDev *pOpenDev) AssignFullNvKmsFlipPermissions(pDevEvo, &pOpenDev->flipPermissions); AssignFullNvKmsModesetPermissions(pDevEvo, &pOpenDev->modesetPermissions); - pDevEvo->modesetOwnerChanged = TRUE; - return TRUE; } @@ -953,8 +1006,6 @@ static void ReallocCoreChannel(NVDevEvoRec *pDevEvo) static void RestoreConsole(NVDevEvoPtr pDevEvo) { - pDevEvo->modesetOwnerChanged = TRUE; - // Try to issue a modeset and flip to the framebuffer console surface. if (!nvEvoRestoreConsole(pDevEvo, TRUE /* allowMST */)) { // If that didn't work, free the core channel to trigger RM's console @@ -985,6 +1036,8 @@ static NvBool ReleaseModesetOwnership(struct NvKmsPerOpenDev *pOpenDev) return FALSE; } + FreeSwapGroups(pOpenDev); + pDevEvo->modesetOwner = NULL; pDevEvo->handleConsoleHotplugs = TRUE; @@ -1027,6 +1080,8 @@ void nvFreePerOpenDev(struct NvKmsPerOpen *pOpen, nvEvoDestroyApiHandles(&pOpenDev->deferredRequestFifoHandles); + nvEvoDestroyApiHandles(&pOpenDev->swapGroupHandles); + nvFree(pOpenDev); } @@ -1098,6 +1153,10 @@ struct NvKmsPerOpenDev *nvAllocPerOpenDev(struct NvKmsPerOpen *pOpen, goto fail; } + if (!nvEvoInitApiHandles(&pOpenDev->swapGroupHandles, 4)) { + goto fail; + } + return pOpenDev; fail: @@ -1165,6 +1224,30 @@ static NvBool AssignNvKmsPerOpenType(struct NvKmsPerOpen *pOpen, return TRUE; } +/*! + * Return whether the PerOpen can be used as a unicast event. + */ +static inline NvBool PerOpenIsValidForUnicastEvent( + const struct NvKmsPerOpen *pOpen) +{ + /* If the type is Undefined, it can be made a unicast event. */ + + if (pOpen->type == NvKmsPerOpenTypeUndefined) { + return TRUE; + } + + /* + * If the type is already UnicastEvent but there is no active user, it can + * be made a unicast event. + */ + if ((pOpen->type == NvKmsPerOpenTypeUnicastEvent) && + (pOpen->unicastEvent.type == NvKmsUnicastEventTypeUndefined)) { + return TRUE; + } + + return FALSE; +} + /*! * Allocate the specified device. */ @@ -1278,11 +1361,20 @@ static NvBool AllocDevice(struct NvKmsPerOpen *pOpen, pParams->reply.maxCursorSize = pDevEvo->cursorHal->caps.maxSize; + /* NVKMS swap groups and warp&blend depends on headSurface functionality. */ + pParams->reply.supportsSwapGroups = pDevEvo->isHeadSurfaceSupported; + pParams->reply.supportsWarpAndBlend = pDevEvo->isHeadSurfaceSupported; + pParams->reply.validLayerRRTransforms = pDevEvo->caps.validLayerRRTransforms; pParams->reply.isoIOCoherencyModes = pDevEvo->isoIOCoherencyModes; pParams->reply.nisoIOCoherencyModes = pDevEvo->nisoIOCoherencyModes; + /* + * TODO: Replace the isSOCDisplay check with an RM query. See Bug 3689635. + */ + pParams->reply.displayIsGpuL2Coherent = !pDevEvo->isSOCDisplay; + pParams->reply.supportsSyncpts = pDevEvo->supportsSyncpts; pParams->reply.supportsIndependentAcqRelSemaphore = @@ -1381,6 +1473,8 @@ static void FreeDeviceReference(struct NvKmsPerOpen *pOpen, /* Disable all client-owned vblank sync objects that still exist. */ DisableRemainingVblankSyncObjects(pOpen, pOpenDev); + FreeSwapGroups(pOpenDev); + UnregisterDeferredRequestFifos(pOpenDev); nvEvoFreeClientSurfaces(pOpenDev->pDevEvo, pOpenDev, @@ -1395,6 +1489,7 @@ static void FreeDeviceReference(struct NvKmsPerOpen *pOpen, ReleaseModesetOwnership(pOpenDev); nvAssert(pOpenDev->pDevEvo->modesetOwner != pOpenDev); + nvAssert(pOpenDev->pDevEvo->lastModesettingClient != pOpenDev); } nvFreePerOpenDev(pOpen, pOpenDev); @@ -1445,8 +1540,6 @@ static NvBool QueryDisp(struct NvKmsPerOpen *pOpen, pDispEvo = pOpenDisp->pDispEvo; - pParams->reply.displayOwner = pDispEvo->displayOwner; - pParams->reply.subDeviceMask = nvDispSubDevMaskEvo(pDispEvo); // Don't include dynamic displays in validDpys. The data returned here is // supposed to be static for the lifetime of the pDispEvo. pParams->reply.validDpys = @@ -1990,20 +2083,6 @@ static NvBool SetMode(struct NvKmsPerOpen *pOpen, TRUE /* doRasterLock */); } -static inline NvBool nvHsIoctlSetCursorImage( - NVDispEvoPtr pDispEvo, - const struct NvKmsPerOpenDev *pOpenDevice, - const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, - NvU32 head, - const struct NvKmsSetCursorImageCommonParams *pParams) -{ - return nvSetCursorImage(pDispEvo, - pOpenDevice, - pOpenDevSurfaceHandles, - head, - pParams); -} - /*! * Set the cursor image. */ @@ -2036,15 +2115,6 @@ static NvBool SetCursorImage(struct NvKmsPerOpen *pOpen, &pParams->request.common); } -static inline NvBool nvHsIoctlMoveCursor( - NVDispEvoPtr pDispEvo, - NvU32 head, - const struct NvKmsMoveCursorCommonParams *pParams) -{ - nvEvoMoveCursor(pDispEvo, head, pParams); - return TRUE; -} - /*! * Change the cursor position. */ @@ -2154,6 +2224,12 @@ static NvBool IdleBaseChannelCheckIdleOneHead( { NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + const NvU32 apiHead = nvHardwareHeadToApiHead(head); + NVHsChannelEvoPtr pHsChannel = pDispEvo->pHsChannel[apiHead]; + + if (pHsChannel != NULL) { + return nvHsIdleFlipQueue(pHsChannel, FALSE /* force */); + } else { NVEvoChannelPtr pMainLayerChannel = pDevEvo->head[head].layer[NVKMS_MAIN_LAYER]; @@ -2286,20 +2362,6 @@ static NvBool IdleBaseChannel(struct NvKmsPerOpen *pOpen, } -static inline NvBool nvHsIoctlFlip( - NVDevEvoPtr pDevEvo, - const struct NvKmsPerOpenDev *pOpenDev, - const struct NvKmsFlipRequest *pRequest, - struct NvKmsFlipReply *pReply) -{ - return nvFlipEvo(pOpenDev->pDevEvo, - pOpenDev, - pRequest, - pReply, - FALSE /* skipUpdate */, - TRUE /* allowFlipLock */); -} - /*! * Flip the specified head. */ @@ -2516,6 +2578,170 @@ static NvBool ReleaseSurface(struct NvKmsPerOpen *pOpen, void *pParamsVoid) } +/*! + * Associate a swap group with the NvKmsPerOpen specified by + * NvKmsGrantSwapGroupParams::request::fd. + */ +static NvBool GrantSwapGroup(struct NvKmsPerOpen *pOpen, void *pParamsVoid) +{ + struct NvKmsGrantSwapGroupParams *pParams = pParamsVoid; + struct NvKmsPerOpenDev *pOpenDev; + NVSwapGroupRec *pSwapGroup; + struct NvKmsPerOpen *pOpenFd; + + pOpenDev = GetPerOpenDev(pOpen, pParams->request.deviceHandle); + + if (pOpenDev == NULL) { + return FALSE; + } + + if (pOpenDev->pDevEvo->modesetOwner != pOpenDev) { + return FALSE; + } + + pSwapGroup = nvHsGetSwapGroup(&pOpenDev->swapGroupHandles, + pParams->request.swapGroupHandle); + + if (pSwapGroup == NULL) { + return FALSE; + } + + pOpenFd = nvkms_get_per_open_data(pParams->request.fd); + + if (pOpenFd == NULL) { + return FALSE; + } + + /* + * Increment the swap group refcnt while granting it so the SwapGroup + * won't be freed out from under the grant fd. To complement this, + * nvKmsClose() on NvKmsPerOpenTypeGrantSwapGroup calls + * DecrementSwapGroupRefCnt(). + */ + if (!nvHsIncrementSwapGroupRefCnt(pSwapGroup)) { + return FALSE; + } + + if (!AssignNvKmsPerOpenType( + pOpenFd, NvKmsPerOpenTypeGrantSwapGroup, FALSE)) { + nvHsDecrementSwapGroupRefCnt(pSwapGroup); + return FALSE; + } + + /* we must not fail beyond this point */ + + pOpenFd->grantSwapGroup.pSwapGroup = pSwapGroup; + + pOpenFd->grantSwapGroup.pDevEvo = pOpenDev->pDevEvo; + + return TRUE; +} + + +/*! + * Retrieve the swap group and device associated with + * NvKmsAcquireSwapGroupParams::request::fd, give the client an + * NvKmsSwapGroupHandle to the swap group, and increment the + * swap group's reference count. + */ +static NvBool AcquireSwapGroup(struct NvKmsPerOpen *pOpen, void *pParamsVoid) +{ + struct NvKmsAcquireSwapGroupParams *pParams = pParamsVoid; + struct NvKmsPerOpen *pOpenFd; + struct NvKmsPerOpenDev *pOpenDev; + NvKmsSwapGroupHandle swapGroupHandle = 0; + + pOpenFd = nvkms_get_per_open_data(pParams->request.fd); + + if (pOpenFd == NULL) { + return FALSE; + } + + if (pOpenFd->type != NvKmsPerOpenTypeGrantSwapGroup) { + return FALSE; + } + + /* + * pSwapGroup is only freed when its last reference goes away; if pOpenFd + * hasn't yet been closed, then its reference incremented in + * GrantSwapGroup() couldn't have been decremented in nvKmsClose() + */ + nvAssert(pOpenFd->grantSwapGroup.pSwapGroup != NULL); + nvAssert(pOpenFd->grantSwapGroup.pDevEvo != NULL); + + if (pOpenFd->grantSwapGroup.pSwapGroup->zombie) { + return FALSE; + } + + pOpenDev = DevEvoToOpenDev(pOpen, pOpenFd->grantSwapGroup.pDevEvo); + + if (pOpenDev == NULL) { + return FALSE; + } + + if (nvEvoApiHandlePointerIsPresent(&pOpenDev->swapGroupHandles, + pOpenFd->grantSwapGroup.pSwapGroup)) { + return FALSE; + } + + if (!nvHsIncrementSwapGroupRefCnt(pOpenFd->grantSwapGroup.pSwapGroup)) { + return FALSE; + } + + swapGroupHandle = + nvEvoCreateApiHandle(&pOpenDev->swapGroupHandles, + pOpenFd->grantSwapGroup.pSwapGroup); + + if (swapGroupHandle == 0) { + nvHsDecrementSwapGroupRefCnt(pOpenFd->grantSwapGroup.pSwapGroup); + return FALSE; + } + + /* we must not fail beyond this point */ + + pParams->reply.deviceHandle = pOpenDev->nvKmsApiHandle; + pParams->reply.swapGroupHandle = swapGroupHandle; + + return TRUE; +} + + +/*! + * Free this client's reference to the swap group. + * + * This is meant to be called by clients that have acquired the swap group + * handle through AcquireSwapGroup(). + */ +static NvBool ReleaseSwapGroup(struct NvKmsPerOpen *pOpen, void *pParamsVoid) +{ + struct NvKmsReleaseSwapGroupParams *pParams = pParamsVoid; + struct NvKmsPerOpenDev *pOpenDev; + NVSwapGroupRec *pSwapGroup; + NvKmsSwapGroupHandle handle = pParams->request.swapGroupHandle; + + pOpenDev = GetPerOpenDev(pOpen, pParams->request.deviceHandle); + + if (pOpenDev == NULL) { + return FALSE; + } + + /* + * This may operate on a swap group that has already been freed + * (pSwapGroup->zombie is TRUE). + */ + pSwapGroup = nvHsGetSwapGroupStruct(&pOpenDev->swapGroupHandles, + handle); + if (pSwapGroup == NULL) { + return FALSE; + } + + nvEvoDestroyApiHandle(&pOpenDev->swapGroupHandles, handle); + + nvHsDecrementSwapGroupRefCnt(pSwapGroup); + + return TRUE; +} + /*! * Change the value of the specified attribute. */ @@ -3137,6 +3363,394 @@ static NvBool QueryDpyCRC32(struct NvKmsPerOpen *pOpen, return TRUE; } +static NvBool AllocSwapGroup( + struct NvKmsPerOpen *pOpen, + void *pParamsVoid) +{ + struct NvKmsAllocSwapGroupParams *pParams = pParamsVoid; + struct NvKmsPerOpenDev *pOpenDev; + NVSwapGroupRec *pSwapGroup; + NvKmsSwapGroupHandle handle; + + pOpenDev = GetPerOpenDev(pOpen, pParams->request.deviceHandle); + + if (pOpenDev == NULL) { + return FALSE; + } + + if (pOpenDev->pDevEvo->modesetOwner != pOpenDev) { + return FALSE; + } + + pSwapGroup = nvHsAllocSwapGroup(pOpenDev->pDevEvo, &pParams->request); + + if (pSwapGroup == NULL) { + return FALSE; + } + + handle = nvEvoCreateApiHandle(&pOpenDev->swapGroupHandles, pSwapGroup); + + if (handle == 0) { + nvHsFreeSwapGroup(pOpenDev->pDevEvo, pSwapGroup); + return FALSE; + } + + pParams->reply.swapGroupHandle = handle; + + return TRUE; +} + +static NvBool FreeSwapGroup( + struct NvKmsPerOpen *pOpen, + void *pParamsVoid) +{ + struct NvKmsFreeSwapGroupParams *pParams = pParamsVoid; + struct NvKmsPerOpenDev *pOpenDev; + NVSwapGroupRec *pSwapGroup; + NvKmsSwapGroupHandle handle = pParams->request.swapGroupHandle; + + pOpenDev = GetPerOpenDev(pOpen, pParams->request.deviceHandle); + + if (pOpenDev == NULL) { + return FALSE; + } + + if (pOpenDev->pDevEvo->modesetOwner != pOpenDev) { + return FALSE; + } + + pSwapGroup = nvHsGetSwapGroup(&pOpenDev->swapGroupHandles, + handle); + if (pSwapGroup == NULL) { + return FALSE; + } + + nvEvoDestroyApiHandle(&pOpenDev->swapGroupHandles, handle); + + nvHsFreeSwapGroup(pOpenDev->pDevEvo, pSwapGroup); + + return TRUE; +} + +static NvBool JoinSwapGroup( + struct NvKmsPerOpen *pOpen, + void *pParamsVoid) +{ + struct NvKmsJoinSwapGroupParams *pParams = pParamsVoid; + const struct NvKmsJoinSwapGroupRequestOneMember *pMember = + pParams->request.member; + NvU32 i; + NvBool anySwapGroupsPending = FALSE; + NVHsJoinSwapGroupWorkArea *pJoinSwapGroupWorkArea; + + if ((pParams->request.numMembers == 0) || + (pParams->request.numMembers > + ARRAY_LEN(pParams->request.member))) { + return FALSE; + } + + pJoinSwapGroupWorkArea = nvCalloc(pParams->request.numMembers, + sizeof(NVHsJoinSwapGroupWorkArea)); + + if (!pJoinSwapGroupWorkArea) { + return FALSE; + } + + /* + * When a client is joining multiple swap groups simultaneously, all of its + * deferred request fifos must enter the pendingJoined state if any of the + * swap groups it's joining have pending flips. Otherwise, this sequence + * can lead to a deadlock: + * + * - Client 0 joins DRF 0 to SG 0, DRF 1 to SG 1, with SG 0 and SG 1 + * fliplocked + * - Client 0 submits DRF 0 ready, SG 0 flips, but the flip won't complete + * and [Client 0.DRF 0] won't be released until SG 1 flips due to + * fliplock + * - Client 1 joins DRF 0 to SG 0, DRF 1 to SG 1 + * - Client 0 submits DRF 1 ready, but SG 1 doesn't flip because + * [Client 1.DRF 0] has joined. + * + * With the pendingJoined behavior, this sequence works as follows: + * + * - Client 0 joins DRF 0 to SG 0, DRF 1 to SG 1, with SG 0 and SG 1 + * fliplocked + * - Client 0 submits DRF 0 ready, SG 0 flips, but the flip won't complete + * and [Client 0.DRF 0] won't be released until SG 1 flips due to + * fliplock + * - Client 1 joins DRF 0 to SG 0, DRF 1 to SG 1, but both enter the + * pendingJoined state because [Client 0.DRF 0] has a pending flip. + * - Client 0 submits DRF 1 ready, both swap groups flip, Client 0's + * DRFs are both released, and Client 1's DRFs both leave the + * pendingJoined state. + */ + for (i = 0; i < pParams->request.numMembers; i++) { + struct NvKmsPerOpenDev *pOpenDev; + NVSwapGroupRec *pSwapGroup; + NVDeferredRequestFifoRec *pDeferredRequestFifo; + struct NvKmsPerOpen *pEventOpenFd = NULL; + NvKmsDeviceHandle deviceHandle = pMember[i].deviceHandle; + NvKmsSwapGroupHandle swapGroupHandle = pMember[i].swapGroupHandle; + NvKmsDeferredRequestFifoHandle deferredRequestFifoHandle = + pMember[i].deferredRequestFifoHandle; + + pOpenDev = GetPerOpenDev(pOpen, deviceHandle); + + if (pOpenDev == NULL) { + goto fail; + } + + pSwapGroup = nvHsGetSwapGroup(&pOpenDev->swapGroupHandles, + swapGroupHandle); + + if (pSwapGroup == NULL) { + goto fail; + } + + if (pSwapGroup->pendingFlip) { + anySwapGroupsPending = TRUE; + } + + /* + * In addition to the check for pending swap groups above, validate + * the remainder of the request now. + */ + + /* + * Prevent pSwapGroup->nMembers from overflowing NV_U32_MAX. + * + * Ideally we would want to count how many members are being added to + * each swap group in the request, but as an optimization, just verify + * that the number of {fifo, swapgroup} tuples joining would not + * overflow any swapgroup even if every one was joining the same + * swapgroup. + */ + if (NV_U32_MAX - pSwapGroup->nMembers < pParams->request.numMembers) { + goto fail; + } + + pDeferredRequestFifo = + nvEvoGetPointerFromApiHandle( + &pOpenDev->deferredRequestFifoHandles, + deferredRequestFifoHandle); + + if (pDeferredRequestFifo == NULL) { + goto fail; + } + + /* + * If the pDeferredRequestFifo is already a member of a SwapGroup, then + * fail. + */ + if (pDeferredRequestFifo->swapGroup.pSwapGroup != NULL) { + goto fail; + } + + if (pMember[i].unicastEvent.specified) { + pEventOpenFd = nvkms_get_per_open_data(pMember[i].unicastEvent.fd); + + if (pEventOpenFd == NULL) { + goto fail; + } + + if (!PerOpenIsValidForUnicastEvent(pEventOpenFd)) { + goto fail; + } + } + + pJoinSwapGroupWorkArea[i].pDevEvo = pOpenDev->pDevEvo; + pJoinSwapGroupWorkArea[i].pSwapGroup = pSwapGroup; + pJoinSwapGroupWorkArea[i].pDeferredRequestFifo = pDeferredRequestFifo; + pJoinSwapGroupWorkArea[i].pEventOpenFd = pEventOpenFd; + pJoinSwapGroupWorkArea[i].enabledHeadSurface = FALSE; + } + + if (!nvHsJoinSwapGroup(pJoinSwapGroupWorkArea, + pParams->request.numMembers, + anySwapGroupsPending)) { + goto fail; + } + + /* Beyond this point, the function cannot fail. */ + + for (i = 0; i < pParams->request.numMembers; i++) { + struct NvKmsPerOpen *pEventOpenFd = + pJoinSwapGroupWorkArea[i].pEventOpenFd; + NVDeferredRequestFifoRec *pDeferredRequestFifo = + pJoinSwapGroupWorkArea[i].pDeferredRequestFifo; + + if (pEventOpenFd) { + pDeferredRequestFifo->swapGroup.pOpenUnicastEvent = pEventOpenFd; + + pEventOpenFd->unicastEvent.type = + NvKmsUnicastEventTypeDeferredRequest; + pEventOpenFd->unicastEvent.e.deferred.pDeferredRequestFifo = + pDeferredRequestFifo; + + pEventOpenFd->type = NvKmsPerOpenTypeUnicastEvent; + } + } + + nvFree(pJoinSwapGroupWorkArea); + return TRUE; + +fail: + nvFree(pJoinSwapGroupWorkArea); + return FALSE; +} + +static NvBool LeaveSwapGroup( + struct NvKmsPerOpen *pOpen, + void *pParamsVoid) +{ + struct NvKmsLeaveSwapGroupParams *pParams = pParamsVoid; + const struct NvKmsLeaveSwapGroupRequestOneMember *pMember = + pParams->request.member; + NvU32 i; + + if ((pParams->request.numMembers == 0) || + (pParams->request.numMembers > + ARRAY_LEN(pParams->request.member))) { + return FALSE; + } + + /* + * Validate all handles passed by the caller and fail if any are invalid. + */ + for (i = 0; i < pParams->request.numMembers; i++) { + struct NvKmsPerOpenDev *pOpenDev; + NVDeferredRequestFifoRec *pDeferredRequestFifo; + NvKmsDeviceHandle deviceHandle = + pMember[i].deviceHandle; + NvKmsDeferredRequestFifoHandle deferredRequestFifoHandle = + pMember[i].deferredRequestFifoHandle; + + pOpenDev = GetPerOpenDev(pOpen, deviceHandle); + + if (pOpenDev == NULL) { + return FALSE; + } + + pDeferredRequestFifo = + nvEvoGetPointerFromApiHandle( + &pOpenDev->deferredRequestFifoHandles, + deferredRequestFifoHandle); + + if (pDeferredRequestFifo == NULL) { + return FALSE; + } + + if (pDeferredRequestFifo->swapGroup.pSwapGroup == NULL) { + return FALSE; + } + } + + /* Beyond this point, the function cannot fail. */ + + for (i = 0; i < pParams->request.numMembers; i++) { + struct NvKmsPerOpenDev *pOpenDev; + NVDeferredRequestFifoRec *pDeferredRequestFifo; + NvKmsDeviceHandle deviceHandle = + pMember[i].deviceHandle; + NvKmsDeferredRequestFifoHandle deferredRequestFifoHandle = + pMember[i].deferredRequestFifoHandle; + + pOpenDev = GetPerOpenDev(pOpen, deviceHandle); + + pDeferredRequestFifo = + nvEvoGetPointerFromApiHandle( + &pOpenDev->deferredRequestFifoHandles, + deferredRequestFifoHandle); + + nvHsLeaveSwapGroup(pOpenDev->pDevEvo, pDeferredRequestFifo, + FALSE /* teardown */); + } + + return TRUE; +} + +static NvBool SetSwapGroupClipList( + struct NvKmsPerOpen *pOpen, + void *pParamsVoid) +{ + struct NvKmsSetSwapGroupClipListParams *pParams = pParamsVoid; + struct NvKmsPerOpenDev *pOpenDev; + NVSwapGroupRec *pSwapGroup; + struct NvKmsRect *pClipList; + NvBool ret; + + pOpenDev = GetPerOpenDev(pOpen, pParams->request.deviceHandle); + + if (pOpenDev == NULL) { + return FALSE; + } + + if (pOpenDev->pDevEvo->modesetOwner != pOpenDev) { + return FALSE; + } + + pSwapGroup = nvHsGetSwapGroup(&pOpenDev->swapGroupHandles, + pParams->request.swapGroupHandle); + + if (pSwapGroup == NULL) { + return FALSE; + } + + /* + * Create a copy of the passed-in pClipList, to be stored in pSwapGroup. + * Copy from the client using nvkms_copyin() or nvkms_memcpy(), depending on + * the clientType. + * + * We do not use the nvKmsIoctl() prepUser/doneUser infrastructure here + * because that would require creating two copies of pClipList in the + * user-space client case: one allocated in prepUser and freed in doneUser, + * and a second in nvHsSetSwapGroupClipList(). + */ + if (pParams->request.nClips == 0) { + pClipList = NULL; + } else { + const size_t len = sizeof(struct NvKmsRect) * pParams->request.nClips; + + if ((pParams->request.pClipList == 0) || + !nvKmsNvU64AddressIsSafe(pParams->request.pClipList)) { + return FALSE; + } + + pClipList = nvAlloc(len); + + if (pClipList == NULL) { + return FALSE; + } + + if (pOpen->clientType == NVKMS_CLIENT_USER_SPACE) { + int status = + nvkms_copyin(pClipList, pParams->request.pClipList, len); + + if (status != 0) { + nvFree(pClipList); + return FALSE; + } + } else { + const void *pKernelPointer = + nvKmsNvU64ToPointer(pParams->request.pClipList); + + nvkms_memcpy(pClipList, pKernelPointer, len); + } + } + + ret = nvHsSetSwapGroupClipList( + pOpenDev->pDevEvo, + pSwapGroup, + pParams->request.nClips, + pClipList); + + if (!ret) { + nvFree(pClipList); + } + + return ret; +} + static NvBool SwitchMux( struct NvKmsPerOpen *pOpen, void *pParamsVoid) @@ -3399,6 +4013,70 @@ static NvBool DisableVblankSyncObject( return TRUE; } +static void NotifyVblankCallback(NVDispEvoRec *pDispEvo, + const NvU32 head, + NVVBlankCallbackPtr pCallbackData) +{ + struct NvKmsPerOpen *pEventOpenFd = pCallbackData->pUserData; + + /* + * NOTIFY_VBLANK events are single-shot so notify the unicast FD, then + * immediately unregister the callback. The unregister step is done in + * nvRemoveUnicastEvent which resets the unicast event data. + */ + nvSendUnicastEvent(pEventOpenFd); + nvRemoveUnicastEvent(pEventOpenFd); +} + +static NvBool NotifyVblank( + struct NvKmsPerOpen *pOpen, + void *pParamsVoid) +{ + struct NvKmsNotifyVblankParams *pParams = pParamsVoid; + struct NvKmsPerOpen *pEventOpenFd = NULL; + NVVBlankCallbackPtr pCallbackData = NULL; + struct NvKmsPerOpenDisp* pOpenDisp = + GetPerOpenDisp(pOpen, pParams->request.deviceHandle, + pParams->request.dispHandle); + NvU32 head = pParams->request.head; + + pEventOpenFd = nvkms_get_per_open_data(pParams->request.unicastEvent.fd); + + if (pEventOpenFd == NULL) { + return NV_FALSE; + } + + if (!PerOpenIsValidForUnicastEvent(pEventOpenFd)) { + return NV_FALSE; + } + + pEventOpenFd->type = NvKmsPerOpenTypeUnicastEvent; + + pCallbackData = nvRegisterVBlankCallback(pOpenDisp->pDispEvo, + head, + NotifyVblankCallback, + pEventOpenFd); + if (pCallbackData == NULL) { + return NV_FALSE; + } + + pEventOpenFd->unicastEvent.type = NvKmsUnicastEventTypeVblankNotification; + pEventOpenFd->unicastEvent.e.vblankNotification.pOpenDisp = pOpenDisp; + pEventOpenFd->unicastEvent.e.vblankNotification.head = head; + pEventOpenFd->unicastEvent.e.vblankNotification.hCallback + = nvEvoCreateApiHandle(&pOpenDisp->vblankCallbackHandles[head], + pCallbackData); + + if (pEventOpenFd->unicastEvent.e.vblankNotification.hCallback == 0) { + nvUnregisterVBlankCallback(pOpenDisp->pDispEvo, + head, + pCallbackData); + return NV_FALSE; + } + + return NV_TRUE; +} + /*! * Perform the ioctl operation requested by the client. * @@ -3506,11 +4184,20 @@ NvBool nvKmsIoctl( RegisterDeferredRequestFifo), ENTRY(NVKMS_IOCTL_UNREGISTER_DEFERRED_REQUEST_FIFO, UnregisterDeferredRequestFifo), + ENTRY(NVKMS_IOCTL_ALLOC_SWAP_GROUP, AllocSwapGroup), + ENTRY(NVKMS_IOCTL_FREE_SWAP_GROUP, FreeSwapGroup), + ENTRY(NVKMS_IOCTL_JOIN_SWAP_GROUP, JoinSwapGroup), + ENTRY(NVKMS_IOCTL_LEAVE_SWAP_GROUP, LeaveSwapGroup), + ENTRY(NVKMS_IOCTL_SET_SWAP_GROUP_CLIP_LIST, SetSwapGroupClipList), + ENTRY(NVKMS_IOCTL_GRANT_SWAP_GROUP, GrantSwapGroup), + ENTRY(NVKMS_IOCTL_ACQUIRE_SWAP_GROUP, AcquireSwapGroup), + ENTRY(NVKMS_IOCTL_RELEASE_SWAP_GROUP, ReleaseSwapGroup), ENTRY(NVKMS_IOCTL_SWITCH_MUX, SwitchMux), ENTRY(NVKMS_IOCTL_GET_MUX_STATE, GetMuxState), ENTRY(NVKMS_IOCTL_EXPORT_VRR_SEMAPHORE_SURFACE, ExportVrrSemaphoreSurface), ENTRY(NVKMS_IOCTL_ENABLE_VBLANK_SYNC_OBJECT, EnableVblankSyncObject), ENTRY(NVKMS_IOCTL_DISABLE_VBLANK_SYNC_OBJECT, DisableVblankSyncObject), + ENTRY(NVKMS_IOCTL_NOTIFY_VBLANK, NotifyVblank), }; struct NvKmsPerOpen *pOpen = pOpenVoid; @@ -3648,6 +4335,7 @@ void nvKmsClose(void *pOpenVoid) if (pOpen->type == NvKmsPerOpenTypeGrantSwapGroup) { nvAssert(pOpen->grantSwapGroup.pSwapGroup != NULL); + nvHsDecrementSwapGroupRefCnt(pOpen->grantSwapGroup.pSwapGroup); } if (pOpen->type == NvKmsPerOpenTypeUnicastEvent) { @@ -3714,8 +4402,9 @@ static const char *ProcFsUnicastEventTypeString( enum NvKmsUnicastEventType type) { switch (type) { - case NvKmsUnicastEventTypeDeferredRequest: return "DeferredRequest"; - case NvKmsUnicastEventTypeUndefined: return "undefined"; + case NvKmsUnicastEventTypeDeferredRequest: return "DeferredRequest"; + case NvKmsUnicastEventTypeVblankNotification: return "VblankNotification"; + case NvKmsUnicastEventTypeUndefined: return "undefined"; } return "unknown"; @@ -3880,6 +4569,11 @@ ProcFsPrintClients( " pDeferredRequestFifo : %p", pOpen->unicastEvent.e.deferred.pDeferredRequestFifo); break; + case NvKmsUnicastEventTypeVblankNotification: + nvEvoLogInfoString(&infoString, + " head : %x", + pOpen->unicastEvent.e.vblankNotification.head); + break; default: break; } @@ -3969,6 +4663,9 @@ static void PrintSurface( " misc : " "log2GobsPerBlockY:%d", pSurfaceEvo->log2GobsPerBlockY); + nvEvoLogInfoString(pInfoString, + " gpuAddress : 0x%016" NvU64_fmtx, + pSurfaceEvo->gpuAddress); nvEvoLogInfoString(pInfoString, " memory : layout:%s format:%s", NvKmsSurfaceMemoryLayoutToString(pSurfaceEvo->layout), @@ -4051,6 +4748,44 @@ ProcFsPrintSurfaces( } } +static void +ProcFsPrintHeadSurface( + void *data, + char *buffer, + size_t size, + nvkms_procfs_out_string_func_t *outString) +{ + NVDevEvoPtr pDevEvo; + NVDispEvoPtr pDispEvo; + NvU32 dispIndex, head; + NVEvoInfoStringRec infoString; + + FOR_ALL_EVO_DEVS(pDevEvo) { + + nvInitInfoString(&infoString, buffer, size); + nvEvoLogInfoString(&infoString, + "pDevEvo (deviceId:%02d) : %p", + pDevEvo->deviceId, pDevEvo); + outString(data, buffer); + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + + nvInitInfoString(&infoString, buffer, size); + nvEvoLogInfoString(&infoString, + " pDispEvo (dispIndex:%02d) : %p", + dispIndex, pDispEvo); + outString(data, buffer); + + for (head = 0; head < pDevEvo->numHeads; head++) { + nvInitInfoString(&infoString, buffer, size); + nvHsProcFs(&infoString, pDevEvo, dispIndex, head); + nvEvoLogInfoString(&infoString, ""); + outString(data, buffer); + } + } + } +} + static const char *SwapGroupPerEyeStereoString(const NvU32 request) { const NvU32 value = @@ -4333,6 +5068,7 @@ void nvKmsGetProcFiles(const nvkms_procfs_file_t **ppProcFiles) static const nvkms_procfs_file_t procFiles[] = { { "clients", ProcFsPrintClients }, { "surfaces", ProcFsPrintSurfaces }, + { "headsurface", ProcFsPrintHeadSurface }, { "deferred-request-fifos", ProcFsPrintDeferredRequestFifos }, { "crcs", ProcFsPrintDpyCrcs }, { NULL, NULL }, @@ -4648,6 +5384,10 @@ void nvSendUnicastEvent(struct NvKmsPerOpen *pOpen) void nvRemoveUnicastEvent(struct NvKmsPerOpen *pOpen) { NVDeferredRequestFifoPtr pDeferredRequestFifo; + NvKmsGenericHandle callbackHandle; + NVVBlankCallbackPtr pCallbackData; + struct NvKmsPerOpenDisp *pOpenDisp; + NvU32 head; if (pOpen == NULL) { return; @@ -4664,6 +5404,31 @@ void nvRemoveUnicastEvent(struct NvKmsPerOpen *pOpen) pDeferredRequestFifo->swapGroup.pOpenUnicastEvent = NULL; pOpen->unicastEvent.e.deferred.pDeferredRequestFifo = NULL; break; + case NvKmsUnicastEventTypeVblankNotification: + /* grab fields from the unicast fd */ + callbackHandle = + pOpen->unicastEvent.e.vblankNotification.hCallback; + pOpenDisp = + pOpen->unicastEvent.e.vblankNotification.pOpenDisp; + head = pOpen->unicastEvent.e.vblankNotification.head; + + /* Unregister the vblank callback */ + pCallbackData = + nvEvoGetPointerFromApiHandle(&pOpenDisp->vblankCallbackHandles[head], + callbackHandle); + + nvUnregisterVBlankCallback(pOpenDisp->pDispEvo, + head, + pCallbackData); + + nvEvoDestroyApiHandle(&pOpenDisp->vblankCallbackHandles[head], + callbackHandle); + + /* invalidate the pOpen data */ + pOpen->unicastEvent.e.vblankNotification.hCallback = 0; + pOpen->unicastEvent.e.vblankNotification.pOpenDisp = NULL; + pOpen->unicastEvent.e.vblankNotification.head = NV_INVALID_HEAD; + break; default: nvAssert("Invalid Unicast Event Type!"); break; @@ -4946,6 +5711,13 @@ static void ServiceOneDeferredRequestFifo( case NVKMS_DEFERRED_REQUEST_OPCODE_NOP: break; + case NVKMS_DEFERRED_REQUEST_OPCODE_SWAP_GROUP_READY: + nvHsSwapGroupReady( + pDevEvo, + pDeferredRequestFifo, + request); + break; + default: nvAssert(!"Invalid NVKMS deferred request opcode"); break; @@ -4984,6 +5756,7 @@ void nvKmsServiceNonStallInterrupt(void *dataPtr, NvU32 dataU32) } } + nvHsProcessPendingViewportFlips(pDevEvo); } NvBool nvKmsGetBacklight(NvU32 display_id, void *drv_priv, NvU32 *brightness) diff --git a/src/nvidia-modeset/src/shaders/g_ampere_shader_info.h b/src/nvidia-modeset/src/shaders/g_ampere_shader_info.h new file mode 100644 index 000000000..fa9617b38 --- /dev/null +++ b/src/nvidia-modeset/src/shaders/g_ampere_shader_info.h @@ -0,0 +1,328 @@ +// Generated using 'Offline GLSL Shader Compiler Version 13.0.0.0.465.00.dev/gpu_drv/dev_a-14542' +// WARNING: This file is auto-generated! Do not hand-edit! +// Instead, edit the GLSL shaders and run 'unix-build nvmake @generate'. + +#include "nvidia-3d-shaders.h" +#include "g_shader_names.h" + +ct_assert(NUM_PROGRAMS == 34); +static const Nv3dProgramInfo AmpereProgramInfo[NUM_PROGRAMS] = { + // nvidia_headsurface_vertex + { .offset = 0x00000000, + .registerCount = 16, + .type = NV3D_SHADER_TYPE_VERTEX, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_VERTEX_B, + .bindGroup = NV3D_HW_BIND_GROUP_VERTEX, + }, + + // nvidia_headsurface_fragment + { .offset = 0x00000300, + .registerCount = 13, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_customSampling + { .offset = 0x00000580, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_overlay + { .offset = 0x00004680, + .registerCount = 32, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_overlay_customSampling + { .offset = 0x00005200, + .registerCount = 32, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset + { .offset = 0x00007d00, + .registerCount = 15, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_customSampling + { .offset = 0x00008000, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_swapped + { .offset = 0x0000c180, + .registerCount = 18, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_swapped_customSampling + { .offset = 0x0000c500, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_overlay + { .offset = 0x00010700, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_overlay_customSampling + { .offset = 0x00011300, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_overlay_swapped + { .offset = 0x00013f80, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_overlay_swapped_customSampling + { .offset = 0x00014b00, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend + { .offset = 0x00017780, + .registerCount = 15, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_customSampling + { .offset = 0x00017a80, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_swapped + { .offset = 0x0001bc00, + .registerCount = 20, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_swapped_customSampling + { .offset = 0x0001bf80, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_overlay + { .offset = 0x00020180, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_overlay_customSampling + { .offset = 0x00020d80, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_overlay_swapped + { .offset = 0x00023980, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_overlay_swapped_customSampling + { .offset = 0x00024500, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset + { .offset = 0x00027180, + .registerCount = 20, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_customSampling + { .offset = 0x00027500, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_swapped + { .offset = 0x0002b680, + .registerCount = 19, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_swapped_customSampling + { .offset = 0x0002ba00, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_overlay + { .offset = 0x0002fc00, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_overlay_customSampling + { .offset = 0x00030780, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_overlay_swapped + { .offset = 0x00033400, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_overlay_swapped_customSampling + { .offset = 0x00033f80, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_yuv420 + { .offset = 0x00036c00, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_yuv420_overlay + { .offset = 0x00038300, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_pixelShift + { .offset = 0x0003a480, + .registerCount = 32, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_overlay_pixelShift + { .offset = 0x0003ac80, + .registerCount = 32, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_reversePrime + { .offset = 0x0003b880, + .registerCount = 13, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + +}; + + +static const Nv3dShaderConstBufInfo AmpereConstBufInfo[] = { +}; + +static const size_t AmpereConstBufSize = 0; +static const NvU32 AmpereConstBufSizeAlign = 256; + +// Total shader code size: 238.75 KB +static const size_t AmpereProgramHeapSize = 244480; +static const size_t AmpereShaderMaxLocalBytes = 0; +static const size_t AmpereShaderMaxStackBytes = 0; diff --git a/src/nvidia-modeset/src/shaders/g_ampere_shaders b/src/nvidia-modeset/src/shaders/g_ampere_shaders new file mode 100644 index 000000000..2d26d21b6 Binary files /dev/null and b/src/nvidia-modeset/src/shaders/g_ampere_shaders differ diff --git a/src/nvidia-modeset/src/shaders/g_hopper_shader_info.h b/src/nvidia-modeset/src/shaders/g_hopper_shader_info.h new file mode 100644 index 000000000..dc1b16a7d --- /dev/null +++ b/src/nvidia-modeset/src/shaders/g_hopper_shader_info.h @@ -0,0 +1,328 @@ +// Generated using 'Offline GLSL Shader Compiler Version 13.0.0.0.465.00.dev/gpu_drv/dev_a-14542' +// WARNING: This file is auto-generated! Do not hand-edit! +// Instead, edit the GLSL shaders and run 'unix-build nvmake @generate'. + +#include "nvidia-3d-shaders.h" +#include "g_shader_names.h" + +ct_assert(NUM_PROGRAMS == 34); +static const Nv3dProgramInfo HopperProgramInfo[NUM_PROGRAMS] = { + // nvidia_headsurface_vertex + { .offset = 0x00000000, + .registerCount = 13, + .type = NV3D_SHADER_TYPE_VERTEX, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_VERTEX_B, + .bindGroup = NV3D_HW_BIND_GROUP_VERTEX, + }, + + // nvidia_headsurface_fragment + { .offset = 0x00000300, + .registerCount = 13, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_customSampling + { .offset = 0x00000580, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_overlay + { .offset = 0x00004680, + .registerCount = 32, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_overlay_customSampling + { .offset = 0x00005200, + .registerCount = 32, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset + { .offset = 0x00007d00, + .registerCount = 15, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_customSampling + { .offset = 0x00008000, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_swapped + { .offset = 0x0000c200, + .registerCount = 16, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_swapped_customSampling + { .offset = 0x0000c580, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_overlay + { .offset = 0x00010780, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_overlay_customSampling + { .offset = 0x00011380, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_overlay_swapped + { .offset = 0x00013f80, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_overlay_swapped_customSampling + { .offset = 0x00014b00, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend + { .offset = 0x00017780, + .registerCount = 15, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_customSampling + { .offset = 0x00017a80, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_swapped + { .offset = 0x0001bc00, + .registerCount = 18, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_swapped_customSampling + { .offset = 0x0001bf00, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_overlay + { .offset = 0x00020100, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_overlay_customSampling + { .offset = 0x00020d00, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_overlay_swapped + { .offset = 0x00023900, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_overlay_swapped_customSampling + { .offset = 0x00024480, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset + { .offset = 0x00027080, + .registerCount = 20, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_customSampling + { .offset = 0x00027400, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_swapped + { .offset = 0x0002b580, + .registerCount = 19, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_swapped_customSampling + { .offset = 0x0002b900, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_overlay + { .offset = 0x0002fb00, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_overlay_customSampling + { .offset = 0x00030680, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_overlay_swapped + { .offset = 0x00033300, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_overlay_swapped_customSampling + { .offset = 0x00033f00, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_yuv420 + { .offset = 0x00036b80, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_yuv420_overlay + { .offset = 0x00038200, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_pixelShift + { .offset = 0x0003a380, + .registerCount = 32, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_overlay_pixelShift + { .offset = 0x0003ab80, + .registerCount = 32, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_reversePrime + { .offset = 0x0003b780, + .registerCount = 13, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + +}; + + +static const Nv3dShaderConstBufInfo HopperConstBufInfo[] = { +}; + +static const size_t HopperConstBufSize = 0; +static const NvU32 HopperConstBufSizeAlign = 256; + +// Total shader code size: 238.5 KB +static const size_t HopperProgramHeapSize = 244224; +static const size_t HopperShaderMaxLocalBytes = 0; +static const size_t HopperShaderMaxStackBytes = 0; diff --git a/src/nvidia-modeset/src/shaders/g_hopper_shaders b/src/nvidia-modeset/src/shaders/g_hopper_shaders new file mode 100644 index 000000000..eb4e721e9 Binary files /dev/null and b/src/nvidia-modeset/src/shaders/g_hopper_shaders differ diff --git a/src/nvidia-modeset/src/shaders/g_maxwell_shader_info.h b/src/nvidia-modeset/src/shaders/g_maxwell_shader_info.h new file mode 100644 index 000000000..2f23ae7c2 --- /dev/null +++ b/src/nvidia-modeset/src/shaders/g_maxwell_shader_info.h @@ -0,0 +1,428 @@ +// Generated using 'Offline GLSL Shader Compiler Version 13.0.0.0.465.00.dev/gpu_drv/dev_a-14542' +// WARNING: This file is auto-generated! Do not hand-edit! +// Instead, edit the GLSL shaders and run 'unix-build nvmake @generate'. + +#include "nvidia-3d-shaders.h" +#include "g_shader_names.h" + +ct_assert(NUM_PROGRAMS == 34); +static const Nv3dProgramInfo MaxwellProgramInfo[NUM_PROGRAMS] = { + // nvidia_headsurface_vertex + { .offset = 0x00000030, + .registerCount = 11, + .type = NV3D_SHADER_TYPE_VERTEX, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_VERTEX_B, + .bindGroup = NV3D_HW_BIND_GROUP_VERTEX, + }, + + // nvidia_headsurface_fragment + { .offset = 0x000001f0, + .registerCount = 15, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_customSampling + { .offset = 0x00000370, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = 0, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_overlay + { .offset = 0x000030f0, + .registerCount = 38, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_overlay_customSampling + { .offset = 0x00003930, + .registerCount = 32, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = 1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset + { .offset = 0x000057f0, + .registerCount = 16, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_customSampling + { .offset = 0x000059b0, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = 2, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_swapped + { .offset = 0x000087b0, + .registerCount = 16, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_swapped_customSampling + { .offset = 0x000089b0, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = 3, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_overlay + { .offset = 0x0000b7f0, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_overlay_customSampling + { .offset = 0x0000c0b0, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = 1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_overlay_swapped + { .offset = 0x0000dfb0, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_overlay_swapped_customSampling + { .offset = 0x0000e7f0, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = 1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend + { .offset = 0x00010730, + .registerCount = 24, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_customSampling + { .offset = 0x000108f0, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = 2, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_swapped + { .offset = 0x000136b0, + .registerCount = 23, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_swapped_customSampling + { .offset = 0x000138b0, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = 3, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_overlay + { .offset = 0x000166b0, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_overlay_customSampling + { .offset = 0x00016f30, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = 1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_overlay_swapped + { .offset = 0x00018e30, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_overlay_swapped_customSampling + { .offset = 0x00019630, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = 1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset + { .offset = 0x0001b570, + .registerCount = 18, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_customSampling + { .offset = 0x0001b770, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = 4, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_swapped + { .offset = 0x0001e5b0, + .registerCount = 18, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_swapped_customSampling + { .offset = 0x0001e7f0, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = 5, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_overlay + { .offset = 0x00021670, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_overlay_customSampling + { .offset = 0x00021ef0, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = 6, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_overlay_swapped + { .offset = 0x00023ef0, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_overlay_swapped_customSampling + { .offset = 0x00024770, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = 6, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_yuv420 + { .offset = 0x000267b0, + .registerCount = 48, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_yuv420_overlay + { .offset = 0x00027730, + .registerCount = 45, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_pixelShift + { .offset = 0x00028f70, + .registerCount = 32, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_overlay_pixelShift + { .offset = 0x000294f0, + .registerCount = 38, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_reversePrime + { .offset = 0x00029db0, + .registerCount = 15, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + +}; + +static const NvU32 MaxwellConstantBuf0[] = { + 0x00000438, // 1.5134e-42 + 0x000007f0, // 2.84744e-42 + 0x00000d18, // 4.69715e-42 + 0x000012f8, // 6.80471e-42 + 0x00001478, // 7.3428e-42 + 0x00001630, // 7.95938e-42 + 0x00001a40, // 9.41673e-42 + 0x00001de0, // 1.07171e-41 + 0x000022e0, // 1.25108e-41 + 0x00002880, // 1.45287e-41 + 0x00002a00, // 1.50668e-41 + 0x00002bb8, // 1.56833e-41 + 0x3f400000, // 0.75 +}; +static const NvU32 MaxwellConstantBuf1[] = { + 0x000003d0, // 1.36767e-42 + 0x00000770, // 2.66807e-42 + 0x00000c58, // 4.4281e-42 + 0x00001240, // 6.54687e-42 + 0x000013c0, // 7.08497e-42 + 0x00001578, // 7.70154e-42 + 0x3f400000, // 0.75 +}; +static const NvU32 MaxwellConstantBuf2[] = { + 0x00000438, // 1.5134e-42 + 0x000007f0, // 2.84744e-42 + 0x00000d10, // 4.68594e-42 + 0x000012f8, // 6.80471e-42 + 0x00001478, // 7.3428e-42 + 0x00001630, // 7.95938e-42 + 0x00001a70, // 9.48399e-42 + 0x00001e10, // 1.07844e-41 + 0x00002310, // 1.25781e-41 + 0x000028b0, // 1.45959e-41 + 0x00002a30, // 1.5134e-41 + 0x00002be0, // 1.57394e-41 + 0x3f400000, // 0.75 +}; +static const NvU32 MaxwellConstantBuf3[] = { + 0x00000438, // 1.5134e-42 + 0x000007f0, // 2.84744e-42 + 0x00000d10, // 4.68594e-42 + 0x000012f8, // 6.80471e-42 + 0x00001478, // 7.3428e-42 + 0x00001630, // 7.95938e-42 + 0x00001ab0, // 9.57367e-42 + 0x00001e50, // 1.08741e-41 + 0x00002350, // 1.26677e-41 + 0x000028f0, // 1.46856e-41 + 0x00002a70, // 1.52237e-41 + 0x00002c20, // 1.58291e-41 + 0x3f400000, // 0.75 +}; +static const NvU32 MaxwellConstantBuf4[] = { + 0x00000440, // 1.52461e-42 + 0x000007f8, // 2.85865e-42 + 0x00000d18, // 4.69715e-42 + 0x00001300, // 6.81592e-42 + 0x00001480, // 7.35401e-42 + 0x00001638, // 7.97059e-42 + 0x00001a90, // 9.52883e-42 + 0x00001e30, // 1.08292e-41 + 0x00002330, // 1.26229e-41 + 0x000028d0, // 1.46408e-41 + 0x00002a50, // 1.51789e-41 + 0x00002c00, // 1.57842e-41 + 0x3f400000, // 0.75 +}; +static const NvU32 MaxwellConstantBuf5[] = { + 0x00000440, // 1.52461e-42 + 0x000007f8, // 2.85865e-42 + 0x00000d18, // 4.69715e-42 + 0x00001300, // 6.81592e-42 + 0x00001480, // 7.35401e-42 + 0x00001638, // 7.97059e-42 + 0x00001ad0, // 9.61851e-42 + 0x00001e70, // 1.09189e-41 + 0x00002370, // 1.27126e-41 + 0x00002910, // 1.47304e-41 + 0x00002a90, // 1.52685e-41 + 0x00002c40, // 1.58739e-41 + 0x3f400000, // 0.75 +}; +static const NvU32 MaxwellConstantBuf6[] = { + 0x000003f0, // 1.41251e-42 + 0x000007a0, // 2.73533e-42 + 0x00000ca0, // 4.529e-42 + 0x00001280, // 6.63655e-42 + 0x00001400, // 7.17465e-42 + 0x000015b8, // 7.79122e-42 + 0x3f400000, // 0.75 +}; + +static const Nv3dShaderConstBufInfo MaxwellConstBufInfo[] = { + { MaxwellConstantBuf0, 0, 52 }, + { MaxwellConstantBuf1, 256, 28 }, + { MaxwellConstantBuf2, 512, 52 }, + { MaxwellConstantBuf3, 768, 52 }, + { MaxwellConstantBuf4, 1024, 52 }, + { MaxwellConstantBuf5, 1280, 52 }, + { MaxwellConstantBuf6, 1536, 28 }, +}; + +static const size_t MaxwellConstBufSize = 1792; +static const NvU32 MaxwellConstBufSizeAlign = 256; + +// Total shader code size: 167.75 KB +static const size_t MaxwellProgramHeapSize = 171776; +static const size_t MaxwellShaderMaxLocalBytes = 0; +static const size_t MaxwellShaderMaxStackBytes = 96; diff --git a/src/nvidia-modeset/src/shaders/g_maxwell_shaders b/src/nvidia-modeset/src/shaders/g_maxwell_shaders new file mode 100644 index 000000000..8fd090a7d Binary files /dev/null and b/src/nvidia-modeset/src/shaders/g_maxwell_shaders differ diff --git a/src/nvidia-modeset/src/shaders/g_nvidia-headsurface-shader-info.h b/src/nvidia-modeset/src/shaders/g_nvidia-headsurface-shader-info.h new file mode 100644 index 000000000..05468fca6 --- /dev/null +++ b/src/nvidia-modeset/src/shaders/g_nvidia-headsurface-shader-info.h @@ -0,0 +1,341 @@ +static const struct NVHeadSurfaceShaderInfo { + NvBool yuv420 : 1; + NvBool blend : 1; + NvBool offset : 1; + NvBool blendAfterWarp : 1; + NvBool overlay : 1; + NvBool pixelShift : 1; + NvBool customSampling : 1; + NvBool reversePrime : 1; +} nvHeadSurfaceShaderInfo[] = { + { /* 0: nvidia_headsurface_fragment */ + .pixelShift = FALSE, + .yuv420 = FALSE, + .blend = FALSE, + .offset = FALSE, + .overlay = FALSE, + .blendAfterWarp = FALSE, + .customSampling = FALSE, + .reversePrime = FALSE, + }, + { /* 1: nvidia_headsurface_fragment_customSampling */ + .pixelShift = FALSE, + .yuv420 = FALSE, + .blend = FALSE, + .offset = FALSE, + .overlay = FALSE, + .blendAfterWarp = FALSE, + .customSampling = TRUE, + .reversePrime = FALSE, + }, + { /* 2: nvidia_headsurface_fragment_overlay */ + .pixelShift = FALSE, + .yuv420 = FALSE, + .blend = FALSE, + .offset = FALSE, + .overlay = TRUE, + .blendAfterWarp = FALSE, + .customSampling = FALSE, + .reversePrime = FALSE, + }, + { /* 3: nvidia_headsurface_fragment_overlay_customSampling */ + .pixelShift = FALSE, + .yuv420 = FALSE, + .blend = FALSE, + .offset = FALSE, + .overlay = TRUE, + .blendAfterWarp = FALSE, + .customSampling = TRUE, + .reversePrime = FALSE, + }, + { /* 4: nvidia_headsurface_fragment_offset */ + .pixelShift = FALSE, + .yuv420 = FALSE, + .blend = FALSE, + .offset = TRUE, + .overlay = FALSE, + .blendAfterWarp = FALSE, + .customSampling = FALSE, + .reversePrime = FALSE, + }, + { /* 5: nvidia_headsurface_fragment_offset_customSampling */ + .pixelShift = FALSE, + .yuv420 = FALSE, + .blend = FALSE, + .offset = TRUE, + .overlay = FALSE, + .blendAfterWarp = FALSE, + .customSampling = TRUE, + .reversePrime = FALSE, + }, + { /* 6: nvidia_headsurface_fragment_offset_swapped */ + .pixelShift = FALSE, + .yuv420 = FALSE, + .blend = FALSE, + .offset = TRUE, + .overlay = FALSE, + .blendAfterWarp = TRUE, + .customSampling = FALSE, + .reversePrime = FALSE, + }, + { /* 7: nvidia_headsurface_fragment_offset_swapped_customSampling */ + .pixelShift = FALSE, + .yuv420 = FALSE, + .blend = FALSE, + .offset = TRUE, + .overlay = FALSE, + .blendAfterWarp = TRUE, + .customSampling = TRUE, + .reversePrime = FALSE, + }, + { /* 8: nvidia_headsurface_fragment_offset_overlay */ + .pixelShift = FALSE, + .yuv420 = FALSE, + .blend = FALSE, + .offset = TRUE, + .overlay = TRUE, + .blendAfterWarp = FALSE, + .customSampling = FALSE, + .reversePrime = FALSE, + }, + { /* 9: nvidia_headsurface_fragment_offset_overlay_customSampling */ + .pixelShift = FALSE, + .yuv420 = FALSE, + .blend = FALSE, + .offset = TRUE, + .overlay = TRUE, + .blendAfterWarp = FALSE, + .customSampling = TRUE, + .reversePrime = FALSE, + }, + { /* 10: nvidia_headsurface_fragment_offset_overlay_swapped */ + .pixelShift = FALSE, + .yuv420 = FALSE, + .blend = FALSE, + .offset = TRUE, + .overlay = TRUE, + .blendAfterWarp = TRUE, + .customSampling = FALSE, + .reversePrime = FALSE, + }, + { /* 11: nvidia_headsurface_fragment_offset_overlay_swapped_customSampling */ + .pixelShift = FALSE, + .yuv420 = FALSE, + .blend = FALSE, + .offset = TRUE, + .overlay = TRUE, + .blendAfterWarp = TRUE, + .customSampling = TRUE, + .reversePrime = FALSE, + }, + { /* 12: nvidia_headsurface_fragment_blend */ + .pixelShift = FALSE, + .yuv420 = FALSE, + .blend = TRUE, + .offset = FALSE, + .overlay = FALSE, + .blendAfterWarp = FALSE, + .customSampling = FALSE, + .reversePrime = FALSE, + }, + { /* 13: nvidia_headsurface_fragment_blend_customSampling */ + .pixelShift = FALSE, + .yuv420 = FALSE, + .blend = TRUE, + .offset = FALSE, + .overlay = FALSE, + .blendAfterWarp = FALSE, + .customSampling = TRUE, + .reversePrime = FALSE, + }, + { /* 14: nvidia_headsurface_fragment_blend_swapped */ + .pixelShift = FALSE, + .yuv420 = FALSE, + .blend = TRUE, + .offset = FALSE, + .overlay = FALSE, + .blendAfterWarp = TRUE, + .customSampling = FALSE, + .reversePrime = FALSE, + }, + { /* 15: nvidia_headsurface_fragment_blend_swapped_customSampling */ + .pixelShift = FALSE, + .yuv420 = FALSE, + .blend = TRUE, + .offset = FALSE, + .overlay = FALSE, + .blendAfterWarp = TRUE, + .customSampling = TRUE, + .reversePrime = FALSE, + }, + { /* 16: nvidia_headsurface_fragment_blend_overlay */ + .pixelShift = FALSE, + .yuv420 = FALSE, + .blend = TRUE, + .offset = FALSE, + .overlay = TRUE, + .blendAfterWarp = FALSE, + .customSampling = FALSE, + .reversePrime = FALSE, + }, + { /* 17: nvidia_headsurface_fragment_blend_overlay_customSampling */ + .pixelShift = FALSE, + .yuv420 = FALSE, + .blend = TRUE, + .offset = FALSE, + .overlay = TRUE, + .blendAfterWarp = FALSE, + .customSampling = TRUE, + .reversePrime = FALSE, + }, + { /* 18: nvidia_headsurface_fragment_blend_overlay_swapped */ + .pixelShift = FALSE, + .yuv420 = FALSE, + .blend = TRUE, + .offset = FALSE, + .overlay = TRUE, + .blendAfterWarp = TRUE, + .customSampling = FALSE, + .reversePrime = FALSE, + }, + { /* 19: nvidia_headsurface_fragment_blend_overlay_swapped_customSampling */ + .pixelShift = FALSE, + .yuv420 = FALSE, + .blend = TRUE, + .offset = FALSE, + .overlay = TRUE, + .blendAfterWarp = TRUE, + .customSampling = TRUE, + .reversePrime = FALSE, + }, + { /* 20: nvidia_headsurface_fragment_blend_offset */ + .pixelShift = FALSE, + .yuv420 = FALSE, + .blend = TRUE, + .offset = TRUE, + .overlay = FALSE, + .blendAfterWarp = FALSE, + .customSampling = FALSE, + .reversePrime = FALSE, + }, + { /* 21: nvidia_headsurface_fragment_blend_offset_customSampling */ + .pixelShift = FALSE, + .yuv420 = FALSE, + .blend = TRUE, + .offset = TRUE, + .overlay = FALSE, + .blendAfterWarp = FALSE, + .customSampling = TRUE, + .reversePrime = FALSE, + }, + { /* 22: nvidia_headsurface_fragment_blend_offset_swapped */ + .pixelShift = FALSE, + .yuv420 = FALSE, + .blend = TRUE, + .offset = TRUE, + .overlay = FALSE, + .blendAfterWarp = TRUE, + .customSampling = FALSE, + .reversePrime = FALSE, + }, + { /* 23: nvidia_headsurface_fragment_blend_offset_swapped_customSampling */ + .pixelShift = FALSE, + .yuv420 = FALSE, + .blend = TRUE, + .offset = TRUE, + .overlay = FALSE, + .blendAfterWarp = TRUE, + .customSampling = TRUE, + .reversePrime = FALSE, + }, + { /* 24: nvidia_headsurface_fragment_blend_offset_overlay */ + .pixelShift = FALSE, + .yuv420 = FALSE, + .blend = TRUE, + .offset = TRUE, + .overlay = TRUE, + .blendAfterWarp = FALSE, + .customSampling = FALSE, + .reversePrime = FALSE, + }, + { /* 25: nvidia_headsurface_fragment_blend_offset_overlay_customSampling */ + .pixelShift = FALSE, + .yuv420 = FALSE, + .blend = TRUE, + .offset = TRUE, + .overlay = TRUE, + .blendAfterWarp = FALSE, + .customSampling = TRUE, + .reversePrime = FALSE, + }, + { /* 26: nvidia_headsurface_fragment_blend_offset_overlay_swapped */ + .pixelShift = FALSE, + .yuv420 = FALSE, + .blend = TRUE, + .offset = TRUE, + .overlay = TRUE, + .blendAfterWarp = TRUE, + .customSampling = FALSE, + .reversePrime = FALSE, + }, + { /* 27: nvidia_headsurface_fragment_blend_offset_overlay_swapped_customSampling */ + .pixelShift = FALSE, + .yuv420 = FALSE, + .blend = TRUE, + .offset = TRUE, + .overlay = TRUE, + .blendAfterWarp = TRUE, + .customSampling = TRUE, + .reversePrime = FALSE, + }, + { /* 28: nvidia_headsurface_fragment_yuv420 */ + .pixelShift = FALSE, + .yuv420 = TRUE, + .blend = FALSE, + .offset = FALSE, + .overlay = FALSE, + .blendAfterWarp = FALSE, + .customSampling = FALSE, + .reversePrime = FALSE, + }, + { /* 29: nvidia_headsurface_fragment_yuv420_overlay */ + .pixelShift = FALSE, + .yuv420 = TRUE, + .blend = FALSE, + .offset = FALSE, + .overlay = TRUE, + .blendAfterWarp = FALSE, + .customSampling = FALSE, + .reversePrime = FALSE, + }, + { /* 30: nvidia_headsurface_fragment_pixelShift */ + .pixelShift = TRUE, + .yuv420 = FALSE, + .blend = FALSE, + .offset = FALSE, + .overlay = FALSE, + .blendAfterWarp = FALSE, + .customSampling = FALSE, + .reversePrime = FALSE, + }, + { /* 31: nvidia_headsurface_fragment_overlay_pixelShift */ + .pixelShift = TRUE, + .yuv420 = FALSE, + .blend = FALSE, + .offset = FALSE, + .overlay = TRUE, + .blendAfterWarp = FALSE, + .customSampling = FALSE, + .reversePrime = FALSE, + }, + { /* 32: nvidia_headsurface_fragment_reversePrime */ + .pixelShift = FALSE, + .yuv420 = FALSE, + .blend = FALSE, + .offset = FALSE, + .overlay = FALSE, + .blendAfterWarp = FALSE, + .customSampling = FALSE, + .reversePrime = TRUE, + }, +}; diff --git a/src/nvidia-modeset/src/shaders/g_pascal_shader_info.h b/src/nvidia-modeset/src/shaders/g_pascal_shader_info.h new file mode 100644 index 000000000..3d62a718f --- /dev/null +++ b/src/nvidia-modeset/src/shaders/g_pascal_shader_info.h @@ -0,0 +1,428 @@ +// Generated using 'Offline GLSL Shader Compiler Version 13.0.0.0.465.00.dev/gpu_drv/dev_a-14542' +// WARNING: This file is auto-generated! Do not hand-edit! +// Instead, edit the GLSL shaders and run 'unix-build nvmake @generate'. + +#include "nvidia-3d-shaders.h" +#include "g_shader_names.h" + +ct_assert(NUM_PROGRAMS == 34); +static const Nv3dProgramInfo PascalProgramInfo[NUM_PROGRAMS] = { + // nvidia_headsurface_vertex + { .offset = 0x00000030, + .registerCount = 11, + .type = NV3D_SHADER_TYPE_VERTEX, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_VERTEX_B, + .bindGroup = NV3D_HW_BIND_GROUP_VERTEX, + }, + + // nvidia_headsurface_fragment + { .offset = 0x000001f0, + .registerCount = 15, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_customSampling + { .offset = 0x00000370, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = 0, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_overlay + { .offset = 0x000030f0, + .registerCount = 38, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_overlay_customSampling + { .offset = 0x00003930, + .registerCount = 32, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = 1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset + { .offset = 0x000057f0, + .registerCount = 16, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_customSampling + { .offset = 0x000059b0, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = 2, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_swapped + { .offset = 0x000087b0, + .registerCount = 16, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_swapped_customSampling + { .offset = 0x000089b0, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = 3, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_overlay + { .offset = 0x0000b7f0, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_overlay_customSampling + { .offset = 0x0000c0b0, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = 1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_overlay_swapped + { .offset = 0x0000dfb0, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_overlay_swapped_customSampling + { .offset = 0x0000e7f0, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = 1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend + { .offset = 0x00010730, + .registerCount = 24, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_customSampling + { .offset = 0x000108f0, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = 2, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_swapped + { .offset = 0x000136b0, + .registerCount = 23, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_swapped_customSampling + { .offset = 0x000138b0, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = 3, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_overlay + { .offset = 0x000166b0, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_overlay_customSampling + { .offset = 0x00016f30, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = 1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_overlay_swapped + { .offset = 0x00018e30, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_overlay_swapped_customSampling + { .offset = 0x00019630, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = 1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset + { .offset = 0x0001b570, + .registerCount = 18, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_customSampling + { .offset = 0x0001b770, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = 4, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_swapped + { .offset = 0x0001e5b0, + .registerCount = 18, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_swapped_customSampling + { .offset = 0x0001e7f0, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = 5, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_overlay + { .offset = 0x00021670, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_overlay_customSampling + { .offset = 0x00021ef0, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = 6, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_overlay_swapped + { .offset = 0x00023ef0, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_overlay_swapped_customSampling + { .offset = 0x00024770, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = 6, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_yuv420 + { .offset = 0x000267b0, + .registerCount = 48, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_yuv420_overlay + { .offset = 0x00027730, + .registerCount = 45, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_pixelShift + { .offset = 0x00028f70, + .registerCount = 32, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_overlay_pixelShift + { .offset = 0x000294f0, + .registerCount = 38, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_reversePrime + { .offset = 0x00029db0, + .registerCount = 15, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + +}; + +static const NvU32 PascalConstantBuf0[] = { + 0x00000438, // 1.5134e-42 + 0x000007f0, // 2.84744e-42 + 0x00000d18, // 4.69715e-42 + 0x000012f8, // 6.80471e-42 + 0x00001478, // 7.3428e-42 + 0x00001630, // 7.95938e-42 + 0x00001a40, // 9.41673e-42 + 0x00001de0, // 1.07171e-41 + 0x000022e0, // 1.25108e-41 + 0x00002880, // 1.45287e-41 + 0x00002a00, // 1.50668e-41 + 0x00002bb8, // 1.56833e-41 + 0x3f400000, // 0.75 +}; +static const NvU32 PascalConstantBuf1[] = { + 0x000003d0, // 1.36767e-42 + 0x00000770, // 2.66807e-42 + 0x00000c58, // 4.4281e-42 + 0x00001240, // 6.54687e-42 + 0x000013c0, // 7.08497e-42 + 0x00001578, // 7.70154e-42 + 0x3f400000, // 0.75 +}; +static const NvU32 PascalConstantBuf2[] = { + 0x00000438, // 1.5134e-42 + 0x000007f0, // 2.84744e-42 + 0x00000d10, // 4.68594e-42 + 0x000012f8, // 6.80471e-42 + 0x00001478, // 7.3428e-42 + 0x00001630, // 7.95938e-42 + 0x00001a70, // 9.48399e-42 + 0x00001e10, // 1.07844e-41 + 0x00002310, // 1.25781e-41 + 0x000028b0, // 1.45959e-41 + 0x00002a30, // 1.5134e-41 + 0x00002be0, // 1.57394e-41 + 0x3f400000, // 0.75 +}; +static const NvU32 PascalConstantBuf3[] = { + 0x00000438, // 1.5134e-42 + 0x000007f0, // 2.84744e-42 + 0x00000d10, // 4.68594e-42 + 0x000012f8, // 6.80471e-42 + 0x00001478, // 7.3428e-42 + 0x00001630, // 7.95938e-42 + 0x00001ab0, // 9.57367e-42 + 0x00001e50, // 1.08741e-41 + 0x00002350, // 1.26677e-41 + 0x000028f0, // 1.46856e-41 + 0x00002a70, // 1.52237e-41 + 0x00002c20, // 1.58291e-41 + 0x3f400000, // 0.75 +}; +static const NvU32 PascalConstantBuf4[] = { + 0x00000440, // 1.52461e-42 + 0x000007f8, // 2.85865e-42 + 0x00000d18, // 4.69715e-42 + 0x00001300, // 6.81592e-42 + 0x00001480, // 7.35401e-42 + 0x00001638, // 7.97059e-42 + 0x00001a90, // 9.52883e-42 + 0x00001e30, // 1.08292e-41 + 0x00002330, // 1.26229e-41 + 0x000028d0, // 1.46408e-41 + 0x00002a50, // 1.51789e-41 + 0x00002c00, // 1.57842e-41 + 0x3f400000, // 0.75 +}; +static const NvU32 PascalConstantBuf5[] = { + 0x00000440, // 1.52461e-42 + 0x000007f8, // 2.85865e-42 + 0x00000d18, // 4.69715e-42 + 0x00001300, // 6.81592e-42 + 0x00001480, // 7.35401e-42 + 0x00001638, // 7.97059e-42 + 0x00001ad0, // 9.61851e-42 + 0x00001e70, // 1.09189e-41 + 0x00002370, // 1.27126e-41 + 0x00002910, // 1.47304e-41 + 0x00002a90, // 1.52685e-41 + 0x00002c40, // 1.58739e-41 + 0x3f400000, // 0.75 +}; +static const NvU32 PascalConstantBuf6[] = { + 0x000003f0, // 1.41251e-42 + 0x000007a0, // 2.73533e-42 + 0x00000ca0, // 4.529e-42 + 0x00001280, // 6.63655e-42 + 0x00001400, // 7.17465e-42 + 0x000015b8, // 7.79122e-42 + 0x3f400000, // 0.75 +}; + +static const Nv3dShaderConstBufInfo PascalConstBufInfo[] = { + { PascalConstantBuf0, 0, 52 }, + { PascalConstantBuf1, 256, 28 }, + { PascalConstantBuf2, 512, 52 }, + { PascalConstantBuf3, 768, 52 }, + { PascalConstantBuf4, 1024, 52 }, + { PascalConstantBuf5, 1280, 52 }, + { PascalConstantBuf6, 1536, 28 }, +}; + +static const size_t PascalConstBufSize = 1792; +static const NvU32 PascalConstBufSizeAlign = 256; + +// Total shader code size: 167.75 KB +static const size_t PascalProgramHeapSize = 171776; +static const size_t PascalShaderMaxLocalBytes = 0; +static const size_t PascalShaderMaxStackBytes = 96; diff --git a/src/nvidia-modeset/src/shaders/g_pascal_shaders b/src/nvidia-modeset/src/shaders/g_pascal_shaders new file mode 100644 index 000000000..b32308032 Binary files /dev/null and b/src/nvidia-modeset/src/shaders/g_pascal_shaders differ diff --git a/src/nvidia-modeset/src/shaders/g_shader_names.h b/src/nvidia-modeset/src/shaders/g_shader_names.h new file mode 100644 index 000000000..fd5c97a6f --- /dev/null +++ b/src/nvidia-modeset/src/shaders/g_shader_names.h @@ -0,0 +1,46 @@ +// WARNING: This file is auto-generated! Do not hand-edit! +// Instead, edit the GLSL shaders and run 'unix-build nvmake @generate'. + +#ifndef __G_SHADER_NAMES_H__ +#define __G_SHADER_NAMES_H__ + +typedef enum { + PROGRAM_NVIDIA_HEADSURFACE_VERTEX, + PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT, + PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT_CUSTOMSAMPLING, + PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT_OVERLAY, + PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT_OVERLAY_CUSTOMSAMPLING, + PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT_OFFSET, + PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT_OFFSET_CUSTOMSAMPLING, + PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT_OFFSET_SWAPPED, + PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT_OFFSET_SWAPPED_CUSTOMSAMPLING, + PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT_OFFSET_OVERLAY, + PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT_OFFSET_OVERLAY_CUSTOMSAMPLING, + PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT_OFFSET_OVERLAY_SWAPPED, + PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT_OFFSET_OVERLAY_SWAPPED_CUSTOMSAMPLING, + PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT_BLEND, + PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT_BLEND_CUSTOMSAMPLING, + PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT_BLEND_SWAPPED, + PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT_BLEND_SWAPPED_CUSTOMSAMPLING, + PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT_BLEND_OVERLAY, + PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT_BLEND_OVERLAY_CUSTOMSAMPLING, + PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT_BLEND_OVERLAY_SWAPPED, + PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT_BLEND_OVERLAY_SWAPPED_CUSTOMSAMPLING, + PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT_BLEND_OFFSET, + PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT_BLEND_OFFSET_CUSTOMSAMPLING, + PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT_BLEND_OFFSET_SWAPPED, + PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT_BLEND_OFFSET_SWAPPED_CUSTOMSAMPLING, + PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT_BLEND_OFFSET_OVERLAY, + PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT_BLEND_OFFSET_OVERLAY_CUSTOMSAMPLING, + PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT_BLEND_OFFSET_OVERLAY_SWAPPED, + PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT_BLEND_OFFSET_OVERLAY_SWAPPED_CUSTOMSAMPLING, + PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT_YUV420, + PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT_YUV420_OVERLAY, + PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT_PIXELSHIFT, + PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT_OVERLAY_PIXELSHIFT, + PROGRAM_NVIDIA_HEADSURFACE_FRAGMENT_REVERSEPRIME, +} ProgramName; + +#define NUM_PROGRAMS 34 + +#endif // __G_SHADER_NAMES_H__ diff --git a/src/nvidia-modeset/src/shaders/g_turing_shader_info.h b/src/nvidia-modeset/src/shaders/g_turing_shader_info.h new file mode 100644 index 000000000..d8d7f57f9 --- /dev/null +++ b/src/nvidia-modeset/src/shaders/g_turing_shader_info.h @@ -0,0 +1,328 @@ +// Generated using 'Offline GLSL Shader Compiler Version 13.0.0.0.465.00.dev/gpu_drv/dev_a-14542' +// WARNING: This file is auto-generated! Do not hand-edit! +// Instead, edit the GLSL shaders and run 'unix-build nvmake @generate'. + +#include "nvidia-3d-shaders.h" +#include "g_shader_names.h" + +ct_assert(NUM_PROGRAMS == 34); +static const Nv3dProgramInfo TuringProgramInfo[NUM_PROGRAMS] = { + // nvidia_headsurface_vertex + { .offset = 0x00000000, + .registerCount = 16, + .type = NV3D_SHADER_TYPE_VERTEX, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_VERTEX_B, + .bindGroup = NV3D_HW_BIND_GROUP_VERTEX, + }, + + // nvidia_headsurface_fragment + { .offset = 0x00000280, + .registerCount = 13, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_customSampling + { .offset = 0x00000480, + .registerCount = 41, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_overlay + { .offset = 0x00004780, + .registerCount = 35, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_overlay_customSampling + { .offset = 0x00005280, + .registerCount = 35, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset + { .offset = 0x00007f00, + .registerCount = 15, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_customSampling + { .offset = 0x00008180, + .registerCount = 41, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_swapped + { .offset = 0x0000c500, + .registerCount = 18, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_swapped_customSampling + { .offset = 0x0000c800, + .registerCount = 41, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_overlay + { .offset = 0x00010b80, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_overlay_customSampling + { .offset = 0x00011700, + .registerCount = 38, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_overlay_swapped + { .offset = 0x00014400, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_overlay_swapped_customSampling + { .offset = 0x00014f80, + .registerCount = 38, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend + { .offset = 0x00017c80, + .registerCount = 15, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_customSampling + { .offset = 0x00017f00, + .registerCount = 41, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_swapped + { .offset = 0x0001c200, + .registerCount = 20, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_swapped_customSampling + { .offset = 0x0001c500, + .registerCount = 41, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_overlay + { .offset = 0x00020880, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_overlay_customSampling + { .offset = 0x00021400, + .registerCount = 38, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_overlay_swapped + { .offset = 0x00024100, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_overlay_swapped_customSampling + { .offset = 0x00024c00, + .registerCount = 38, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset + { .offset = 0x00027900, + .registerCount = 20, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_customSampling + { .offset = 0x00027c00, + .registerCount = 41, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_swapped + { .offset = 0x0002bf80, + .registerCount = 20, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_swapped_customSampling + { .offset = 0x0002c280, + .registerCount = 41, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_overlay + { .offset = 0x00030680, + .registerCount = 44, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_overlay_customSampling + { .offset = 0x00031200, + .registerCount = 43, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_overlay_swapped + { .offset = 0x00034000, + .registerCount = 45, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_overlay_swapped_customSampling + { .offset = 0x00034b80, + .registerCount = 45, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_yuv420 + { .offset = 0x00037980, + .registerCount = 59, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_yuv420_overlay + { .offset = 0x00038f00, + .registerCount = 56, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_pixelShift + { .offset = 0x0003b080, + .registerCount = 45, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_overlay_pixelShift + { .offset = 0x0003b800, + .registerCount = 35, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_reversePrime + { .offset = 0x0003c400, + .registerCount = 13, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + +}; + + +static const Nv3dShaderConstBufInfo TuringConstBufInfo[] = { +}; + +static const size_t TuringConstBufSize = 0; +static const NvU32 TuringConstBufSizeAlign = 256; + +// Total shader code size: 241.5 KB +static const size_t TuringProgramHeapSize = 247296; +static const size_t TuringShaderMaxLocalBytes = 0; +static const size_t TuringShaderMaxStackBytes = 0; diff --git a/src/nvidia-modeset/src/shaders/g_turing_shaders b/src/nvidia-modeset/src/shaders/g_turing_shaders new file mode 100644 index 000000000..3fa3ac0f6 Binary files /dev/null and b/src/nvidia-modeset/src/shaders/g_turing_shaders differ diff --git a/src/nvidia-modeset/src/shaders/g_volta_shader_info.h b/src/nvidia-modeset/src/shaders/g_volta_shader_info.h new file mode 100644 index 000000000..72132cedc --- /dev/null +++ b/src/nvidia-modeset/src/shaders/g_volta_shader_info.h @@ -0,0 +1,328 @@ +// Generated using 'Offline GLSL Shader Compiler Version 13.0.0.0.465.00.dev/gpu_drv/dev_a-14542' +// WARNING: This file is auto-generated! Do not hand-edit! +// Instead, edit the GLSL shaders and run 'unix-build nvmake @generate'. + +#include "nvidia-3d-shaders.h" +#include "g_shader_names.h" + +ct_assert(NUM_PROGRAMS == 34); +static const Nv3dProgramInfo VoltaProgramInfo[NUM_PROGRAMS] = { + // nvidia_headsurface_vertex + { .offset = 0x00000030, + .registerCount = 16, + .type = NV3D_SHADER_TYPE_VERTEX, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_VERTEX_B, + .bindGroup = NV3D_HW_BIND_GROUP_VERTEX, + }, + + // nvidia_headsurface_fragment + { .offset = 0x000002b0, + .registerCount = 13, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_customSampling + { .offset = 0x000004b0, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_overlay + { .offset = 0x000048b0, + .registerCount = 32, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_overlay_customSampling + { .offset = 0x000053b0, + .registerCount = 32, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset + { .offset = 0x00008030, + .registerCount = 15, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_customSampling + { .offset = 0x000082b0, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_swapped + { .offset = 0x0000c730, + .registerCount = 18, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_swapped_customSampling + { .offset = 0x0000ca30, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_overlay + { .offset = 0x00010eb0, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_overlay_customSampling + { .offset = 0x00011ab0, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_overlay_swapped + { .offset = 0x00014830, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_offset_overlay_swapped_customSampling + { .offset = 0x000153b0, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend + { .offset = 0x000181b0, + .registerCount = 15, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_customSampling + { .offset = 0x00018430, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_swapped + { .offset = 0x0001c830, + .registerCount = 20, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_swapped_customSampling + { .offset = 0x0001cb30, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_overlay + { .offset = 0x00020fb0, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_overlay_customSampling + { .offset = 0x00021b30, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_overlay_swapped + { .offset = 0x000248b0, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_overlay_swapped_customSampling + { .offset = 0x00025430, + .registerCount = 39, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset + { .offset = 0x000281b0, + .registerCount = 20, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_customSampling + { .offset = 0x000284b0, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_swapped + { .offset = 0x0002c9b0, + .registerCount = 19, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_swapped_customSampling + { .offset = 0x0002ccb0, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_overlay + { .offset = 0x000311b0, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_overlay_customSampling + { .offset = 0x00031d30, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_overlay_swapped + { .offset = 0x00034b30, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_blend_offset_overlay_swapped_customSampling + { .offset = 0x000356b0, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_yuv420 + { .offset = 0x000384b0, + .registerCount = 48, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_yuv420_overlay + { .offset = 0x00039ab0, + .registerCount = 40, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_pixelShift + { .offset = 0x0003bc30, + .registerCount = 32, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_overlay_pixelShift + { .offset = 0x0003c3b0, + .registerCount = 32, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + + // nvidia_headsurface_fragment_reversePrime + { .offset = 0x0003cfb0, + .registerCount = 13, + .type = NV3D_SHADER_TYPE_PIXEL, + .constIndex = -1, + .stage = NV3D_HW_SHADER_STAGE_PIXEL, + .bindGroup = NV3D_HW_BIND_GROUP_FRAGMENT, + }, + +}; + + +static const Nv3dShaderConstBufInfo VoltaConstBufInfo[] = { +}; + +static const size_t VoltaConstBufSize = 0; +static const NvU32 VoltaConstBufSizeAlign = 256; + +// Total shader code size: 244.375 KB +static const size_t VoltaProgramHeapSize = 250240; +static const size_t VoltaShaderMaxLocalBytes = 0; +static const size_t VoltaShaderMaxStackBytes = 0; diff --git a/src/nvidia-modeset/src/shaders/g_volta_shaders b/src/nvidia-modeset/src/shaders/g_volta_shaders new file mode 100644 index 000000000..633d21bf8 Binary files /dev/null and b/src/nvidia-modeset/src/shaders/g_volta_shaders differ diff --git a/src/nvidia-modeset/srcs.mk b/src/nvidia-modeset/srcs.mk index bb3a9df77..fbcca3ccc 100644 --- a/src/nvidia-modeset/srcs.mk +++ b/src/nvidia-modeset/srcs.mk @@ -140,6 +140,19 @@ SRCS += ../common/unix/common/utils/nv_memory_tracker.c SRCS += ../common/unix/common/utils/nv_mode_timings_utils.c SRCS += ../common/unix/common/utils/nv_vasprintf.c SRCS += ../common/unix/common/utils/unix_rm_handle.c +SRCS += ../common/unix/nvidia-3d/src/nvidia-3d-core.c +SRCS += ../common/unix/nvidia-3d/src/nvidia-3d-fermi.c +SRCS += ../common/unix/nvidia-3d/src/nvidia-3d-hopper.c +SRCS += ../common/unix/nvidia-3d/src/nvidia-3d-init.c +SRCS += ../common/unix/nvidia-3d/src/nvidia-3d-kepler.c +SRCS += ../common/unix/nvidia-3d/src/nvidia-3d-maxwell.c +SRCS += ../common/unix/nvidia-3d/src/nvidia-3d-pascal.c +SRCS += ../common/unix/nvidia-3d/src/nvidia-3d-surface.c +SRCS += ../common/unix/nvidia-3d/src/nvidia-3d-turing.c +SRCS += ../common/unix/nvidia-3d/src/nvidia-3d-vertex-arrays.c +SRCS += ../common/unix/nvidia-3d/src/nvidia-3d-volta.c +SRCS += ../common/unix/nvidia-push/src/nvidia-push-init.c +SRCS += ../common/unix/nvidia-push/src/nvidia-push.c SRCS += kapi/src/nvkms-kapi-channelevent.c SRCS += kapi/src/nvkms-kapi-notifiers.c SRCS += kapi/src/nvkms-kapi.c @@ -158,6 +171,7 @@ SRCS += src/nvkms-console-restore.c SRCS += src/nvkms-cursor.c SRCS += src/nvkms-cursor2.c SRCS += src/nvkms-cursor3.c +SRCS += src/nvkms-difr.c SRCS += src/nvkms-dma.c SRCS += src/nvkms-dpy.c SRCS += src/nvkms-event.c @@ -169,14 +183,27 @@ SRCS += src/nvkms-flip.c SRCS += src/nvkms-framelock.c SRCS += src/nvkms-hal.c SRCS += src/nvkms-hdmi.c +SRCS += src/nvkms-headsurface-3d.c +SRCS += src/nvkms-headsurface-config.c +SRCS += src/nvkms-headsurface-ioctl.c +SRCS += src/nvkms-headsurface-matrix.c +SRCS += src/nvkms-headsurface-swapgroup.c +SRCS += src/nvkms-headsurface.c SRCS += src/nvkms-hw-states.c SRCS += src/nvkms-lut.c SRCS += src/nvkms-modepool.c SRCS += src/nvkms-modeset.c +SRCS += src/nvkms-pow.c SRCS += src/nvkms-prealloc.c +SRCS += src/nvkms-push.c SRCS += src/nvkms-rm.c SRCS += src/nvkms-rmapi-dgpu.c +SRCS += src/nvkms-stereo.c SRCS += src/nvkms-surface.c SRCS += src/nvkms-utils.c SRCS += src/nvkms-vrr.c SRCS += src/nvkms.c +SRCS += ../common/unix/xzminidec/src/xz_crc32.c +SRCS += ../common/unix/xzminidec/src/xz_dec_bcj.c +SRCS += ../common/unix/xzminidec/src/xz_dec_lzma2.c +SRCS += ../common/unix/xzminidec/src/xz_dec_stream.c diff --git a/src/nvidia/Makefile b/src/nvidia/Makefile index 2a3773131..b7ca09b25 100644 --- a/src/nvidia/Makefile +++ b/src/nvidia/Makefile @@ -10,6 +10,13 @@ include ../../utils.mk include srcs.mk +############################################################################## +# Helper functions to determine the compiler type +############################################################################## +GET_COMPILER_TYPE = \ + $(shell $(VERSION_MK_DIR)/nv-compiler.sh type $(1)) +############################################################################## + # The source files for nv-kernel.o are all SRCS and SRCS_CXX defined in srcs.mk, # and the NVIDIA ID string ALL_SRCS = $(SRCS) $(SRCS_CXX) @@ -23,7 +30,9 @@ CFLAGS += -include $(SRC_COMMON)/sdk/nvidia/inc/cpuopsys.h CFLAGS += -I kernel/inc CFLAGS += -I interface CFLAGS += -I $(SRC_COMMON)/sdk/nvidia/inc +CFLAGS += -I $(SRC_COMMON)/sdk/nvidia/inc/hw CFLAGS += -I arch/nvalloc/common/inc +CFLAGS += -I arch/nvalloc/common/inc/gsp CFLAGS += -I arch/nvalloc/common/inc/deprecated CFLAGS += -I arch/nvalloc/unix/include CFLAGS += -I inc @@ -33,6 +42,7 @@ CFLAGS += -I $(SRC_COMMON)/shared/msgq/inc CFLAGS += -I $(SRC_COMMON)/inc CFLAGS += -I $(SRC_COMMON)/uproc/os/libos-v2.0.0/include +CFLAGS += -I $(SRC_COMMON)/uproc/os/common/include CFLAGS += -I $(SRC_COMMON)/uproc/os/libos-v2.0.0/debug CFLAGS += -I $(SRC_COMMON)/inc/swref CFLAGS += -I $(SRC_COMMON)/inc/swref/published @@ -43,6 +53,7 @@ CFLAGS += -I $(SRC_COMMON)/nvswitch/interface CFLAGS += -I $(SRC_COMMON)/nvswitch/common/inc/ CFLAGS += -I $(SRC_COMMON)/inc/displayport CFLAGS += -I $(SRC_COMMON)/nvlink/interface/ +CFLAGS += -I $(SRC_COMMON)/nvlink/inband/interface CFLAGS += -I src/mm/uvm/interface CFLAGS += -I inc/libraries CFLAGS += -I src/libraries @@ -120,9 +131,37 @@ CFLAGS += -fdata-sections NV_KERNEL_O_LDFLAGS += --gc-sections EXPORTS_LINK_COMMAND = exports_link_command.txt -CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -fcf-protection=none) - ifeq ($(TARGET_ARCH),x86_64) + COMPILER_TYPE := $(call GET_COMPILER_TYPE, $(CC)) + ENDBR_SUPPORTED := $(call AS_HAS_INSTR, endbr64) + + FCF_SUPPORTED = + + # + # GCC flags -fcf-protection=branch and -mindirect-branch=extern-thunk can + # be used together after GCC version 9.4.0. See + # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93654 for details. + # Check if GCC version is appropriate. + # + ifeq ($(COMPILER_TYPE),gcc) + FCF_SUPPORTED := \ + $(shell $(VERSION_MK_DIR)/nv-compiler.sh version_is_at_least $(CC) 90400) + endif + + # + # Clang version 14.0.0 is required for -fcf-protection=branch to work + # correctly. See commit + # https://github.com/llvm/llvm-project/commit/dfcf69770bc522b9e411c66454934a37c1f35332 + # + ifeq ($(COMPILER_TYPE),clang) + FCF_SUPPORTED := \ + $(shell $(VERSION_MK_DIR)/nv-compiler.sh version_is_at_least $(CC) 140000) + endif + + ifeq ($(FCF_SUPPORTED)-$(ENDBR_SUPPORTED),1-1) + CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -fcf-protection=branch) + endif + CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -fno-jump-tables) CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -mindirect-branch-register) CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -mindirect-branch=thunk-extern) endif @@ -144,7 +183,7 @@ $(foreach src, $(ALL_SRCS), $(eval $(call DEFINE_OBJECT_RULE,TARGET,$(src)))) NV_KERNEL_O = $(OUTPUTDIR)/nv-kernel.o -.PNONY: all clean +.PHONY: all all: $(NV_KERNEL_O) LINKER_SCRIPT = nv-kernel.ld @@ -159,5 +198,6 @@ $(NV_KERNEL_O): $(OBJS) $(EXPORTS_LINK_COMMAND) $(LINKER_SCRIPT) --localize-symbol=memcpy \ $@ +.PHONY: clean clean: $(RM) -rf $(OUTPUTDIR) diff --git a/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_emem_channels.h b/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_emem_channels.h new file mode 100644 index 000000000..c4b9949e2 --- /dev/null +++ b/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_emem_channels.h @@ -0,0 +1,47 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _FSP_EMEM_CHANNELS_H_ +#define _FSP_EMEM_CHANNELS_H_ + +// +// NVDM (NVIDIA Data Model) overlayed on MCTP (Management Component Transport +// Protocol) and sent over EMEM is the communication mechanism used between FSP +// management partition and CPU-RM/other uprocs. +// + +// RM uses channel 0 for FSP EMEM. +#define FSP_EMEM_CHANNEL_RM 0x0 + +// PMU/SOE use channel 4 for FSP EMEM. +#define FSP_EMEM_CHANNEL_PMU_SOE 0x4 +#define FSP_EMEM_CHANNEL_MAX 0x8 + +// EMEM channel 0 (RM) is allocated 1K bytes. +#define FSP_EMEM_CHANNEL_RM_SIZE 1024 + +// EMEM channel 4 (PMU/SOE) is allocated 1K bytes. +#define FSP_EMEM_CHANNEL_PMU_SOE_SIZE 1024 +#define FSP_EMEM_CHANNEL_PMU_SOE_OFFSET 4096 + +#endif // _FSP_EMEM_CHANNELS_H_ diff --git a/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_mctp_format.h b/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_mctp_format.h new file mode 100644 index 000000000..c087dc249 --- /dev/null +++ b/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_mctp_format.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _FSP_MCTP_FORMAT_H_ +#define _FSP_MCTP_FORMAT_H_ + +// +// NVDM (NVIDIA Data Model) overlayed on MCTP (Management Component Transport +// Protocol) and sent over EMEM is the communication mechanism used between FSP +// management partition and CPU-RM/other uprocs. +// + + +#define MCTP_HEADER_VERSION 3:0 +#define MCTP_HEADER_RSVD 7:4 + +#define MCTP_HEADER_DEID 15:8 +#define MCTP_HEADER_SEID 23:16 + +#define MCTP_HEADER_TAG 26:24 +#define MCTP_HEADER_TO 27:27 +#define MCTP_HEADER_SEQ 29:28 +#define MCTP_HEADER_EOM 30:30 +#define MCTP_HEADER_SOM 31:31 + +#define MCTP_MSG_HEADER_TYPE 6:0 +#define MCTP_MSG_HEADER_IC 7:7 + +#define MCTP_MSG_HEADER_VENDOR_ID 23:8 +#define MCTP_MSG_HEADER_NVDM_TYPE 31:24 + +#define MCTP_MSG_HEADER_TYPE_VENDOR_PCI 0x7e +#define MCTP_MSG_HEADER_VENDOR_ID_NV 0x10de + +#endif // _FSP_MCTP_FORMAT_H_ diff --git a/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_nvdm_format.h b/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_nvdm_format.h new file mode 100644 index 000000000..dc389f14d --- /dev/null +++ b/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_nvdm_format.h @@ -0,0 +1,43 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _FSP_NVDM_FORMAT_H_ +#define _FSP_NVDM_FORMAT_H_ + +#include "fsp/fsp_mctp_format.h" +#include "fsp/fsp_emem_channels.h" + +// +// NVDM (NVIDIA Data Model) overlayed on MCTP (Management Component Transport +// Protocol) and sent over EMEM is the communication mechanism used between FSP +// management partition and CPU-RM/other uprocs. +// + +#define NVDM_TYPE_HULK 0x11 +#define NVDM_TYPE_FIRMWARE_UPDATE 0x12 +#define NVDM_TYPE_COT 0x14 +#define NVDM_TYPE_FSP_RESPONSE 0x15 +#define NVDM_TYPE_INFOROM 0x17 +#define NVDM_TYPE_SMBPBI 0x18 + +#endif // _FSP_NVDM_FORMAT_H_ diff --git a/src/common/uproc/os/libos-v2.0.0/include/gsp_fw_wpr_meta.h b/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_wpr_meta.h similarity index 94% rename from src/common/uproc/os/libos-v2.0.0/include/gsp_fw_wpr_meta.h rename to src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_wpr_meta.h index 6aee28648..c056000d6 100644 --- a/src/common/uproc/os/libos-v2.0.0/include/gsp_fw_wpr_meta.h +++ b/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_wpr_meta.h @@ -21,11 +21,6 @@ * DEALINGS IN THE SOFTWARE. */ -// TODO: This file is is not libos specific, so it really does not belong under -// uproc/os/libos-v2.0.0. It is used by booter, bootloader, libos, GSP-RM, -// and kernel RM. An appropriate location might be uproc/common/inc, but -// that directory is not currently synced by DVS for driver builds. - #pragma once #ifndef GSP_FW_WPR_META_H_ @@ -138,9 +133,15 @@ typedef struct NvU16 partitionRpcRequestOffset; NvU16 partitionRpcReplyOffset; + // Code section and dataSection offset and size. + NvU32 elfCodeOffset; + NvU32 elfDataOffset; + NvU32 elfCodeSize; + NvU32 elfDataSize; + // Pad structure to exactly 256 bytes. Can replace padding with additional // fields without incrementing revision. Padding initialized to 0. - NvU32 padding[7]; + NvU32 padding[3]; // BL to use for verification (i.e. Booter says OK to boot) NvU64 verified; // 0x0 -> unverified, 0xa0a0a0a0a0a0a0a0 -> verified diff --git a/src/nvidia/arch/nvalloc/common/inc/gsp/gspifpub.h b/src/nvidia/arch/nvalloc/common/inc/gsp/gspifpub.h index eea7cfc2c..46733a60e 100644 --- a/src/nvidia/arch/nvalloc/common/inc/gsp/gspifpub.h +++ b/src/nvidia/arch/nvalloc/common/inc/gsp/gspifpub.h @@ -44,11 +44,11 @@ typedef enum { /*! * @brief GSP-CC Microcode Initialization Parameters */ -typedef struct GSP_CC_INIT_PARAMS +typedef struct GSP_FMC_INIT_PARAMS { // CC initialization "registry keys" NvU32 regkeys; -} GSP_CC_INIT_PARAMS; +} GSP_FMC_INIT_PARAMS; /*! * @brief GSP-ACR BOOT_GSP_RM Command Parameters @@ -68,6 +68,8 @@ typedef struct GSP_ACR_BOOT_GSP_RM_PARAMS NvU64 wprCarveoutOffset; // Size in bytes of the WPR containing GSP-RM NvU32 wprCarveoutSize; + // Whether to boot GSP-RM or GSP-Proxy through ACR + NvBool bIsGspRmBoot; } GSP_ACR_BOOT_GSP_RM_PARAMS; /*! @@ -84,11 +86,11 @@ typedef struct GSP_RM_PARAMS /*! * @brief GSP-CC Microcode Parameters for Boot Partitions */ -typedef struct GSP_CC_BOOT_PARAMS +typedef struct GSP_FMC_BOOT_PARAMS { - GSP_CC_INIT_PARAMS initParams; - GSP_ACR_BOOT_GSP_RM_PARAMS bootGspRmParams; - GSP_RM_PARAMS gspRmParams; -} GSP_CC_BOOT_PARAMS; + GSP_FMC_INIT_PARAMS initParams; + GSP_ACR_BOOT_GSP_RM_PARAMS bootGspRmParams; + GSP_RM_PARAMS gspRmParams; +} GSP_FMC_BOOT_PARAMS; #endif // GSPIFPUB_H diff --git a/src/nvidia/arch/nvalloc/common/inc/nv-firmware-chip-family-select.h b/src/nvidia/arch/nvalloc/common/inc/nv-firmware-chip-family-select.h new file mode 100644 index 000000000..068cc44d5 --- /dev/null +++ b/src/nvidia/arch/nvalloc/common/inc/nv-firmware-chip-family-select.h @@ -0,0 +1,62 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NV_FIRMWARE_CHIP_FAMILY_SELECT_H +#define NV_FIRMWARE_CHIP_FAMILY_SELECT_H + + + +#include +#include + +static inline nv_firmware_chip_family_t nv_firmware_get_chip_family( + NvU32 gpuArch, + NvU32 gpuImpl +) +{ + switch (gpuArch) + { + case GPU_ARCHITECTURE_TURING: + if (gpuImpl <= GPU_IMPLEMENTATION_TU106) + return NV_FIRMWARE_CHIP_FAMILY_TU10X; + else + return NV_FIRMWARE_CHIP_FAMILY_TU11X; + + case GPU_ARCHITECTURE_AMPERE: + if (gpuImpl == GPU_IMPLEMENTATION_GA100) + return NV_FIRMWARE_CHIP_FAMILY_GA100; + else + return NV_FIRMWARE_CHIP_FAMILY_GA10X; + + case GPU_ARCHITECTURE_ADA: + return NV_FIRMWARE_CHIP_FAMILY_AD10X; + + case GPU_ARCHITECTURE_HOPPER: + if (gpuImpl == GPU_IMPLEMENTATION_GH100) + return NV_FIRMWARE_CHIP_FAMILY_GH100; + } + + return NV_FIRMWARE_CHIP_FAMILY_NULL; +} + +#endif // NV_FIRMWARE_CHIP_FAMILY_SELECT_H diff --git a/src/nvidia/arch/nvalloc/common/inc/nv-firmware.h b/src/nvidia/arch/nvalloc/common/inc/nv-firmware.h new file mode 100644 index 000000000..3ddade5b7 --- /dev/null +++ b/src/nvidia/arch/nvalloc/common/inc/nv-firmware.h @@ -0,0 +1,132 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NV_FIRMWARE_H +#define NV_FIRMWARE_H + + + +#include +#include + +typedef enum +{ + NV_FIRMWARE_TYPE_GSP, + NV_FIRMWARE_TYPE_GSP_LOG +} nv_firmware_type_t; + +typedef enum +{ + NV_FIRMWARE_CHIP_FAMILY_NULL = 0, + NV_FIRMWARE_CHIP_FAMILY_TU10X = 1, + NV_FIRMWARE_CHIP_FAMILY_TU11X = 2, + NV_FIRMWARE_CHIP_FAMILY_GA100 = 3, + NV_FIRMWARE_CHIP_FAMILY_GA10X = 4, + NV_FIRMWARE_CHIP_FAMILY_AD10X = 5, + NV_FIRMWARE_CHIP_FAMILY_GH100 = 6, + NV_FIRMWARE_CHIP_FAMILY_END, +} nv_firmware_chip_family_t; + +static inline const char *nv_firmware_chip_family_to_string( + nv_firmware_chip_family_t fw_chip_family +) +{ + switch (fw_chip_family) { + case NV_FIRMWARE_CHIP_FAMILY_GH100: return "gh100"; + case NV_FIRMWARE_CHIP_FAMILY_AD10X: return "ad10x"; + case NV_FIRMWARE_CHIP_FAMILY_GA10X: return "ga10x"; + case NV_FIRMWARE_CHIP_FAMILY_GA100: return "ga100"; + case NV_FIRMWARE_CHIP_FAMILY_TU11X: return "tu11x"; + case NV_FIRMWARE_CHIP_FAMILY_TU10X: return "tu10x"; + + case NV_FIRMWARE_CHIP_FAMILY_END: // fall through + case NV_FIRMWARE_CHIP_FAMILY_NULL: + return NULL; + } + return NULL; +} + +// The includer (presumably nv.c) may optionally define +// NV_FIRMWARE_PATH_FOR_FILENAME(filename) +// to return a string "path" given a gsp_*.bin or gsp_log_*.bin filename. +// +// The function nv_firmware_path will then be available. +#if defined(NV_FIRMWARE_PATH_FOR_FILENAME) +static inline const char *nv_firmware_path( + nv_firmware_type_t fw_type, + nv_firmware_chip_family_t fw_chip_family +) +{ + if (fw_type == NV_FIRMWARE_TYPE_GSP) + { + switch (fw_chip_family) + { + case NV_FIRMWARE_CHIP_FAMILY_AD10X: + return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_ad10x.bin"); + + case NV_FIRMWARE_CHIP_FAMILY_GH100: // fall through + case NV_FIRMWARE_CHIP_FAMILY_GA100: // fall through + case NV_FIRMWARE_CHIP_FAMILY_GA10X: // fall through + case NV_FIRMWARE_CHIP_FAMILY_TU11X: // fall through + case NV_FIRMWARE_CHIP_FAMILY_TU10X: + return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_tu10x.bin"); + + case NV_FIRMWARE_CHIP_FAMILY_END: // fall through + case NV_FIRMWARE_CHIP_FAMILY_NULL: + return ""; + } + } + else if (fw_type == NV_FIRMWARE_TYPE_GSP_LOG) + { + switch (fw_chip_family) + { + case NV_FIRMWARE_CHIP_FAMILY_AD10X: + return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_log_ad10x.bin"); + + case NV_FIRMWARE_CHIP_FAMILY_GH100: // fall through + case NV_FIRMWARE_CHIP_FAMILY_GA100: // fall through + case NV_FIRMWARE_CHIP_FAMILY_GA10X: // fall through + case NV_FIRMWARE_CHIP_FAMILY_TU11X: // fall through + case NV_FIRMWARE_CHIP_FAMILY_TU10X: + return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_log_tu10x.bin"); + + case NV_FIRMWARE_CHIP_FAMILY_END: // fall through + case NV_FIRMWARE_CHIP_FAMILY_NULL: + return ""; + } + } + + return ""; +} +#endif // defined(NV_FIRMWARE_PATH_FOR_FILENAME) + +// The includer (presumably nv.c) may optionally define +// NV_FIRMWARE_DECLARE_GSP_FILENAME(filename) +// which will then be invoked (at the top-level) for each +// gsp_*.bin (but not gsp_log_*.bin) +#if defined(NV_FIRMWARE_DECLARE_GSP_FILENAME) +NV_FIRMWARE_DECLARE_GSP_FILENAME("gsp_ad10x.bin") +NV_FIRMWARE_DECLARE_GSP_FILENAME("gsp_tu10x.bin") +#endif // defined(NV_FIRMWARE_DECLARE_GSP_FILENAME) + +#endif // NV_FIRMWARE_DECLARE_GSP_FILENAME diff --git a/src/nvidia/arch/nvalloc/common/inc/nvcst.h b/src/nvidia/arch/nvalloc/common/inc/nvcst.h index 1e2942f0a..9a86d5e42 100644 --- a/src/nvidia/arch/nvalloc/common/inc/nvcst.h +++ b/src/nvidia/arch/nvalloc/common/inc/nvcst.h @@ -27,6 +27,7 @@ #include #include #include +#include #define CHIPSET_SETUP_FUNC(name) static NV_STATUS name(OBJCL *pCl); @@ -86,7 +87,6 @@ CHIPSET_SETUP_FUNC(Huawei_Kunpeng920_setupFunc) CHIPSET_SETUP_FUNC(Mellanox_BlueField_setupFunc) CHIPSET_SETUP_FUNC(Amazon_Gravitron2_setupFunc) CHIPSET_SETUP_FUNC(Fujitsu_A64FX_setupFunc) -CHIPSET_SETUP_FUNC(Phytium_FT2000_setupFunc) CHIPSET_SETUP_FUNC(Ampere_Altra_setupFunc) CHIPSET_SETUP_FUNC(Arm_NeoverseN1_setupFunc) CHIPSET_SETUP_FUNC(Nvidia_T210_setupFunc) @@ -154,6 +154,7 @@ CSINFO chipsetInfo[] = {PCI_VENDOR_ID_INTEL, 0xA14A, CS_INTEL_A145, "SkyLake C232", Intel_A145_setupFunc}, {PCI_VENDOR_ID_INTEL, 0xA14D, CS_INTEL_A145, "SkyLake-H", Intel_A145_setupFunc}, {PCI_VENDOR_ID_INTEL, 0xA244, CS_INTEL_A145, "SkyLake C620", Intel_A145_setupFunc}, + {PCI_VENDOR_ID_INTEL, 0xA1C8, CS_INTEL_A145, "SkyLake C620", Intel_A145_setupFunc}, {PCI_VENDOR_ID_INTEL, 0x8D47, CS_INTEL_8D47, "IntelX99", Intel_8D47_setupFunc}, {PCI_VENDOR_ID_INTEL, 0x8D44, CS_INTEL_8D47, "IntelC612", Intel_8D44_setupFunc}, {PCI_VENDOR_ID_INTEL, 0xA2C5, CS_INTEL_A2C5, "IntelZ270", Intel_A2C5_setupFunc}, @@ -239,12 +240,6 @@ CSINFO chipsetInfo[] = {PCI_VENDOR_ID_MELLANOX, 0xA2D5, CS_MELLANOX_BLUEFIELD2, "Mellanox BlueField 2 Crypto disabled", NULL}, {PCI_VENDOR_ID_AMAZON, 0x0200, CS_AMAZON_GRAVITRON2, "Amazon Gravitron2", Amazon_Gravitron2_setupFunc}, {PCI_VENDOR_ID_FUJITSU, 0x1952, CS_FUJITSU_A64FX, "Fujitsu A64FX", Fujitsu_A64FX_setupFunc}, - {PCI_VENDOR_ID_CADENCE, 0xDC01, CS_PHYTIUM_FT2000, "Phytium FT2000", Phytium_FT2000_setupFunc}, - {PCI_VENDOR_ID_CADENCE, 0xDC08, CS_PHYTIUM_FT2000, "Phytium FT2000", Phytium_FT2000_setupFunc}, - {PCI_VENDOR_ID_CADENCE, 0xDC16, CS_PHYTIUM_FT2000, "Phytium FT2000", Phytium_FT2000_setupFunc}, - {PCI_VENDOR_ID_CADENCE, 0xFC01, CS_PHYTIUM_FT2000, "Phytium FT2000", Phytium_FT2000_setupFunc}, - {PCI_VENDOR_ID_CADENCE, 0xFC08, CS_PHYTIUM_FT2000, "Phytium FT2000", Phytium_FT2000_setupFunc}, - {PCI_VENDOR_ID_CADENCE, 0xFC16, CS_PHYTIUM_FT2000, "Phytium FT2000", Phytium_FT2000_setupFunc}, {PCI_VENDOR_ID_CADENCE, 0xDC01, CS_PHYTIUM_S2500, "Phytium S2500", NULL}, {PCI_VENDOR_ID_CADENCE, 0xDC08, CS_PHYTIUM_S2500, "Phytium S2500", NULL}, {PCI_VENDOR_ID_CADENCE, 0xDC16, CS_PHYTIUM_S2500, "Phytium S2500", NULL}, @@ -335,18 +330,12 @@ ARMCSALLOWLISTINFO armChipsetAllowListInfo[] = {PCI_VENDOR_ID_MELLANOX, 0xA2D5, CS_MELLANOX_BLUEFIELD2},// Mellanox BlueField 2 Crypto disabled {PCI_VENDOR_ID_AMAZON, 0x0200, CS_AMAZON_GRAVITRON2}, // Amazon Gravitron2 {PCI_VENDOR_ID_FUJITSU, 0x1952, CS_FUJITSU_A64FX}, // Fujitsu A64FX - {PCI_VENDOR_ID_CADENCE, 0xDC01, CS_PHYTIUM_FT2000}, // Phytium FT2000 - {PCI_VENDOR_ID_CADENCE, 0xDC08, CS_PHYTIUM_FT2000}, // Phytium FT2000 - {PCI_VENDOR_ID_CADENCE, 0xDC16, CS_PHYTIUM_FT2000}, // Phytium FT2000 - {PCI_VENDOR_ID_CADENCE, 0xFC01, CS_PHYTIUM_FT2000}, // Phytium FT2000 - {PCI_VENDOR_ID_CADENCE, 0xFC08, CS_PHYTIUM_FT2000}, // Phytium FT2000 - {PCI_VENDOR_ID_CADENCE, 0xFC16, CS_PHYTIUM_FT2000}, // Phytium FT2000 {PCI_VENDOR_ID_CADENCE, 0xDC01, CS_PHYTIUM_S2500}, // Phytium S2500 {PCI_VENDOR_ID_CADENCE, 0xDC08, CS_PHYTIUM_S2500}, // Phytium S2500 {PCI_VENDOR_ID_CADENCE, 0xDC16, CS_PHYTIUM_S2500}, // Phytium S2500 {PCI_VENDOR_ID_CADENCE, 0xFC01, CS_PHYTIUM_S2500}, // Phytium S2500 {PCI_VENDOR_ID_CADENCE, 0xFC08, CS_PHYTIUM_S2500}, // Phytium S2500 - {PCI_VENDOR_ID_CADENCE, 0xDC16, CS_PHYTIUM_S2500}, // Phytium S2500 + {PCI_VENDOR_ID_CADENCE, 0xFC16, CS_PHYTIUM_S2500}, // Phytium S2500 {PCI_VENDOR_ID_AMPERE, 0xE000, CS_AMPERE_ALTRA}, // Ampere Altra {PCI_VENDOR_ID_AMPERE, 0xE00D, CS_AMPERE_ALTRA}, // Ampere Altra {PCI_VENDOR_ID_AMPERE, 0xE00E, CS_AMPERE_ALTRA}, // Ampere Altra diff --git a/src/nvidia/arch/nvalloc/common/inc/nvdevid.h b/src/nvidia/arch/nvalloc/common/inc/nvdevid.h index 41dcbf8ef..559bcb743 100644 --- a/src/nvidia/arch/nvalloc/common/inc/nvdevid.h +++ b/src/nvidia/arch/nvalloc/common/inc/nvdevid.h @@ -156,6 +156,7 @@ /////////////////////////////////////////////////////////////////////////////////////////// #define NV_PCI_DEVID_DEVICE_PG171_SKU200_PG179_SKU220 0x25B6 /* NVIDIA A16 / NVIDIA A2 */ +#define NV_PCI_DEVID_DEVICE_PG189_SKU600 0x1EBA /////////////////////////////////////////////////////////////////////////////////////////// // @@ -633,7 +634,6 @@ enum { , CS_MELLANOX_BLUEFIELD , CS_AMAZON_GRAVITRON2 , CS_FUJITSU_A64FX -, CS_PHYTIUM_FT2000 , CS_AMPERE_ALTRA , CS_ARM_NEOVERSEN1 , CS_MARVELL_OCTEON_CN96XX diff --git a/src/nvidia/arch/nvalloc/common/inc/nvpcie.h b/src/nvidia/arch/nvalloc/common/inc/nvpcie.h index 56ed38fc1..6b5c7ca75 100644 --- a/src/nvidia/arch/nvalloc/common/inc/nvpcie.h +++ b/src/nvidia/arch/nvalloc/common/inc/nvpcie.h @@ -58,26 +58,81 @@ #define PCI_MULTIFUNCTION 0x80 // From PCI Local Bus Specification, Revision 3.0 +// and PCI Express Base Specification 6.0 +// numbers in comments to right of values indicate +// the referenced section in the PCIE spec -#define CAP_ID_MASK 0xFF -#define CAP_ID_PMI 0x01 -#define CAP_ID_AGP 0x02 -#define CAP_ID_VPD 0x03 -#define CAP_ID_SLOT_ID 0x04 -#define CAP_ID_MSI 0x05 -#define CAP_ID_HOT_SWAP 0x06 -#define CAP_ID_PCI_X 0x07 -#define CAP_ID_HYPER_TRANSPORT 0x08 -#define CAP_ID_VENDOR_SPECIFIC 0x09 -#define CAP_ID_DEBUG_PORT 0x0A -#define CAP_ID_CRC 0x0B -#define CAP_ID_HOT_PLUG 0x0C -#define CAP_ID_SUBSYSTEM_ID 0x0D -#define CAP_ID_AGP8X 0x0E -#define CAP_ID_SECURE 0x0F -#define CAP_ID_PCI_EXPRESS 0x10 -#define CAP_ID_MSI_X 0x11 +#define CAP_ID_MASK 0xFF + +#define CAP_ID_NULL 0x00 // 7.9.28.1 +#define CAP_ID_PMI 0x01 // 7.5.2.1 +#define CAP_ID_AGP 0x02 +#define CAP_ID_VPD 0x03 // 7.9.18.1 +#define CAP_ID_SLOT_ID 0x04 +#define CAP_ID_MSI 0x05 // 7.7.1.1 +#define CAP_ID_HOT_SWAP 0x06 +#define CAP_ID_PCI_X 0x07 +#define CAP_ID_HYPER_TRANSPORT 0x08 +#define CAP_ID_VENDOR_SPECIFIC 0x09 +#define CAP_ID_DEBUG_PORT 0x0A +#define CAP_ID_CRC 0x0B +#define CAP_ID_HOT_PLUG 0x0C +#define CAP_ID_SUBSYSTEM_ID 0x0D // 7.9.23.1 +#define CAP_ID_AGP8X 0x0E +#define CAP_ID_SECURE 0x0F +#define CAP_ID_PCI_EXPRESS 0x10 // 7.5.3.1 +#define CAP_ID_MSI_X 0x11 // 7.7.2.1 +#define CAP_ID_ENHANCED_ALLOCATION 0x14 // 7.8.5.1 +#define CAP_ID_FPB 0x15 // 7.8.11.1 +#define CAP_ID_AF 0x13 // 7.9.21.1 + +// +// sizes for static PCI capabilities structure +// +#define CAP_NULL_SIZE 0x04 // 7.9.28 +#define CAP_PMI_SIZE 0x08 // 7.5.2 +#define CAP_VPD_SIZE 0x08 // 7.9.18 +#define CAP_PCI_X_SIZE 0x3C // 7.5.3 +#define CAP_PCI_EXPRESS_SIZE 0x3C // 7.5.3 +#define CAP_FPB_SIZE 0x08 // 7.8.11.1 +#define CAP_AF_SIZE 0x08 // 7.9.21 +#define CAP_SUBSYSTEM_ID_SIZE 0x08 // 7.9.23 + +// MSI capability size related fields +#define PCI_MSI_CONTROL 0x02 // 7.7.1.2 +#define PCI_MSI_CONTROL_64BIT_CAPABLE 7:7 +#define PCI_MSI_CONTROL_64BIT_CAPABLE_FALSE 0 +#define PCI_MSI_CONTROL_64BIT_CAPABLE_TRUE 1 +#define PCI_MSI_CONTROL_PVM_CAPABLE 8:8 +#define PCI_MSI_CONTROL_PVM_CAPABLE_FALSE 0 +#define PCI_MSI_CONTROL_PVM_CAPABLE_TRUE 1 +#define PCI_MSI_BASE_SIZE 0x0C // 7.7.1 +#define PCI_MSI_64BIT_ADDR_CAPABLE_ADJ_SIZE 0x04 // 7.7.1 +#define PCI_MSI_PVM_CAPABLE_ADJ_SIZE 0x08 // 7.7.1 + +// MSI-X capability size related fields +#define PCI_MSI_X_BASE_SIZE 0x0C // 7.7.2 +#define PCI_MSI_X_CONTROL 0x02 // 7.7.2.2 +#define PCI_MSI_X_CONTROL_TABLE_SIZE 10:0 +#define PCI_MSI_X_TABLE_OFFSET_BIR 0x04 // 7.7.2.3 +#define PCI_MSI_X_TABLE_OFFSET 31:3 +#define PCI_MSI_X_PBR_OFFSET_BIR 0x08 // 7.7.2.4 +#define PCI_MSI_X_PBR_OFFSET 31:3 +#define PCI_MSI_X_TABLE_ENTRY_SIZE 0x10 // 7.7.2 +#define PCI_MSI_X_PBR_ENTRY_SIZE 0x10 // 7.7.2 + +// Enhanced Allocation Capability size related fields +#define PCI_ENHANCED_ALLOCATION_FIRST_DW 0x00 // 7.8.5.1 +#define PCI_ENHANCED_ALLOCATION_FIRST_DW_NUM_ENTRIES 21:16 +#define PCI_ENHANCED_ALLOCATION_TYPE_0_BASE_SIZE 0x04 // 7.8.5.1 +#define PCI_ENHANCED_ALLOCATION_TYPE_1_BASE_SIZE 0x08 // 7.8.5.2 +#define PCI_ENHANCED_ALLOCATION_ENTRY_HEADER 0x00 // 7.8.5.3 +#define PCI_ENHANCED_ALLOCATION_ENTRY_HEADER_ENTRY_SIZE 2:0 + +// PCI Vendor Specific Capability size related fields +#define PCI_VENDOR_SPECIFIC_CAP_HEADER 0x00 // 7.9.4 +#define PCI_VENDOR_SPECIFIC_CAP_HEADER_LENGTH 23:16 // // Extended config space size is 4096 bytes. @@ -99,6 +154,8 @@ #define PCI_HEADER_TYPE0_CACHE_LINE_SIZE 0x0C #define PCI_HEADER_TYPE0_LATENCY_TIMER 0x0D #define PCI_HEADER_TYPE0_HEADER_TYPE 0x0E +#define PCI_HEADER_TYPE0_HEADER_TYPE_0 0 +#define PCI_HEADER_TYPE0_HEADER_TYPE_1 1 #define PCI_HEADER_TYPE0_BIST 0x0F #define PCI_HEADER_TYPE0_BAR0 0x10 #define PCI_HEADER_TYPE0_BAR1 0x14 @@ -229,14 +286,120 @@ #define PCIE_LINK_STATUS_2_DE_EMPHASIS 0:0 // PCIE De-Emphasis Level #define PCI_COMMON_SUBSYSTEM_VENDOR_ID 0x2c // PCI subsystem Vendor Id #define PCI_COMMON_SUBSYSTEM_ID 0x2e // PCI subsystem Id - +#define PCIE_CAPABILITY_BASE 0x100 // 1st PCIE capability. // PCI Express Capability ID in the enhanced configuration space -#define PCIE_CAP_ID_ERROR 0x1 // PCIE Advanced Error Reporting -#define PCIE_CAP_ID_VC 0x2 // PCIE Virtual Channel (VC) -#define PCIE_CAP_ID_SERIAL 0x3 // PCIE Device Serial Number -#define PCIE_CAP_ID_POWER 0x4 // PCIE Power Budgeting -#define PCIE_CAP_ID_L1_PM_SUBSTATES 0x1E // PCIE L1 PM Substates +#define PCIE_CAP_ID_NULL 0x00 // 7.9.28.1 +#define PCIE_CAP_ID_ERROR 0x01 // 7.8.4.1 +#define PCIE_CAP_ID_VC 0x02 // 7.9.1.1 +#define PCIE_CAP_ID_SERIAL 0x03 // 7.9.3.1 +#define PCIE_CAP_ID_POWER 0x04 // 7.8.1.1 +#define PCIE_CAP_ID_ROOT_COMPLEX 0x05 // 7.9.8.1 +#define PCIE_CAP_ID_ROOT_COMPLEX_INTERNAL_LINK_CTRL 0x06 // 7.9.9.1 +#define PCIE_CAP_ID_ROOT_COMPLEX_EVENT_COLLECTOR_ENDPOINT 0x07 // 7.9.10.1 +#define PCIE_CAP_ID_PCIE_CAP_ID_MFVC 0x08 // 7.9.2.1 +#define PCIE_CAP_ID_RCRB 0x0A // 7.9.7.1 +#define PCIE_CAP_ID_ACS 0x0D // 7.7.11.1 +#define PCIE_CAP_ID_ARI 0x0E // 7.8.8.1 +#define PCIE_CAP_ID_MULTICAST 0x12 // 7.9.11.1 +#define PCIE_CAP_ID_RESIZABLE_BAR 0x15 // 7.8.6.1 +#define PCIE_CAP_ID_DYNAMIC_POWER_ALLOCATION 0x16 // 7.9.12.1 +#define PCIE_CAP_ID_TPH 0x17 // 7.9.13.1 +#define PCIE_CAP_ID_LATENCY_TOLERANCE 0x18 // 7.8.2.1 +#define PCIE_CAP_ID_SECONDARY_PCIE_CAPABILITY 0x19 // 7.7.3.1 +#define PCIE_CAP_ID_PASID 0x1B // 7.8.9.1 +#define PCIE_CAP_ID_DPC 0x1D // 7.9.14.1 +#define PCIE_CAP_ID_L1_PM_SUBSTATES 0x1E // 7.8.3.1 +#define PCIE_CAP_ID_PTM 0x1F // 7.9.15.1 +#define PCIE_CAP_ID_FRS_QUEUING 0x21 // 7.8.10.1 +#define PCIE_CAP_ID_READINESS_TIME_REPORTING 0x22 // 7.9.16.1 +#define PCIE_CAP_ID_VENDOR_SPECIFIC 0x23 // 7.9.6.1 +#define PCIE_CAP_ID_VF_RESIZABLE_BAR 0x24 // 7.8.7.1 +#define PCIE_CAP_ID_DATA_LINK 0x25 // 7.7.4.1 +#define PCIE_CAP_ID_PHYSLAYER_16_GT 0x26 // 7.7.5.1 +#define PCIE_CAP_ID_LANE_MARGINING_AT_RECEVER 0x27 // 7.7.10.1 +#define PCIE_CAP_ID_HIERARCHY_ID 0x28 // 7.9.17.1 +#define PCIE_CAP_ID_NPEM 0x29 // 7.9.19.1 +#define PCIE_CAP_ID_PHYSLAYER_32_GT 0x2A // 7.7.6.1 +#define PCIE_CAP_ID_ALTERNATE_PROTOCOL 0x2B // 7.9.20.1 +#define PCIE_CAP_ID_SFI 0x2C // 7.9.22.1 +#define PCIE_CAP_ID_SHADOW_FUNCTIONS 0x2D // 7.9.25.1 +#define PCIE_CAP_ID_DATA_OBJECT_EXCHANGE 0x2E // 7.9.24.1 +#define PCIE_CAP_ID_DEVICE_3 0x2F // 7.7.9.1 +#define PCIE_CAP_ID_IDE 0x30 // 7.9.26.1 +#define PCIE_CAP_ID_PHYSLAYER_64_GT 0x31 // 7.7.7.1 +#define PCIE_CAP_ID_FLT_LOGGING 0x32 // 7.7.8.1 +#define PCIE_CAP_ID_FLIT_PERF_MEASURMENT 0x33 // 7.8.12.1 +#define PCIE_CAP_ID_FLIT_ERROR_INJECTION 0x34 // 7.8.13.1 + +// static sized structure sizes +#define PCIE_CAP_HEADER_SIZE 0x04 // 7.6.3 +#define PCIE_CAP_NULL_SIZE 0x04 // 7.9.28 +#define PCIE_CAP_ERROR_SIZE 0x48 // 7.8.4 +#define PCIE_CAP_POWER_SIZE 0x10 // 7.8.1 +#define PCIE_CAP_ROOT_COMPLEX_INTERNAL_LINK_CTRL_SIZE 0x0C // 7.9.9 +#define PCIE_CAP_ROOT_COMPLEX_EVENT_COLLECTOR_ENDPOINT_SIZE 0x0C // 7.9.10 +#define PCIE_CAP_SECONDARY_PCIE_SIZE 0x4C // 7.7.3.1 +#define PCIE_CAP_DATA_LINK_SIZE 0x0C // 7.7.4 +#define PCIE_CAP_PHYSLAYER_16_GT_SIZE 0x40 // 7.7.5 +#define PCIE_CAP_PHYSLAYER_32_GT_SIZE 0x40 // 7.7.6 +#define PCIE_CAP_PHYSLAYER_64_GT_SIZE 0x20 // 7.7.7 +#define PCIE_CAP_FLT_LOGGING_SIZE 0x3C // 7.7.8 +#define PCIE_CAP_DEVICE_3_SIZE 0x10 // 7.7.9 +#define PCIE_CAP_LANE_MARGINING_AT_RECEVER_SIZE 0x88 // 7.7.10 +#define PCIE_CAP_ACS_SIZE 0x10 // 7.7.11 +#define PCIE_CAP_LATENCY_TOLERANCE_SIZE 0x08 // 7.8.2 +#define PCIE_CAP_L1_PM_SUBSTATE_SIZE 0x14 // 7.8.3 +#define PCIE_CAP_RESIZABLE_BAR_SIZE 0x34 // 7.8.6 +#define PCIE_CAP_VF_RESIZABLE_BAR_SIZE 0x34 // 7.8.7 +#define PCIE_CAP_ARI_SIZE 0x08 // 7.8.8 +#define PCIE_CAP_PASID_SIZE 0x08 // 7.8.9 +#define PCIE_CAP_FRS_QUEUING_SIZE 0x10 // 7.8.10 +#define PCIE_CAP_FPB_SIZE 0x24 // 7.8.11 +#define PCIE_CAP_FLIT_PERF_MEASURMENT_SIZE 0x24 // 7.8.12 +#define PCIE_CAP_FLIT_ERROR_INJECTION_SIZE 0x24 // 7.8.13 +#define PCIE_CAP_DEV_SERIAL_SIZE 0x0C // 7.9.3 +#define PCIE_CAP_RCRB_SIZE 0x14 // 7.9.7 +#define PCIE_CAP_MULTICAST_SIZE 0x30 // 7.9.11 +#define PCIE_CAP_DYNAMIC_POWER_ALLOCATION_SIZE 0x30 // 7.9.12 +#define PCIE_CAP_DPC_SIZE 0x5C // 7.9.14 +#define PCIE_CAP_PTM_SIZE 0x0C // 7.9.15 +#define PCIE_CAP_READINESS_TIME_REPORTING_SIZE 0x0C // 7.9.16 +#define PCIE_CAP_HIERARCHY_ID_SIZE 0x0C // 7.9.17 +#define PCIE_CAP_NPEM_SIZE 0x10 // 7.9.19 +#define PCIE_CAP_ALTERNATE_PROTOCOL_SIZE 0x14 // 7.9.20 +#define PCIE_CAP_SFI_SIZE 0x14 // 7.9.22 +#define PCIE_CAP_DATA_OBJECT_EXCHANGE_SIZE 0x18 // 7.9.24 +#define PCIE_CAP_SHADOW_FUNCTIONS_SIZE 0x1C // 7.9.25 +#define PCIE_CAP_IDE_SIZE 0x34 // 7.9.26 + +// Virtual Channel Capability size related fields +#define PCIE_VC_REGISTER_1 0x04 // 7.9.1.2 +#define PCIE_VC_REGISTER_1_EXTENDED_VC_COUNT 2:0 +#define PCIE_VIRTUAL_CHANNELS_BASE_SIZE 0x18 // 7.9.1 +#define PCIE_VIRTUAL_CHANNELS_EXTENDED_VC_ENTRY_SIZE 0x10 // 7.9.1 + +// Multi Function Virtual Channel Capability size related fields +#define PCIE_MFVC_REGISTER_1 0x04 // 7.9.2.2 +#define PCIE_MFVC_REGISTER_1_EXTENDED_VC_COUNT 2:0 +#define PCIE_PCIE_CAP_ID_MFVC_BASE_SIZE 0x18 // 7.9.2 +#define PCIE_PCIE_CAP_ID_MFVC_EXTENDED_VC_ENTRY_SIZE 0x10 // 7.9.2 + +// Vendor Specific Capability size related fields +#define PCIE_VENDOR_SPECIFIC_HEADER_1 0x04 // 7.9.6.2 +#define PCIE_VENDOR_SPECIFIC_HEADER_1_LENGTH 31:20 + +// Root Complex Capability size related fields +#define PCIE_ROOT_COMPLEX_SELF_DESC_REGISTER 0x04 // 7.9.8.2 +#define PCIE_ROOT_COMPLEX_SELF_DESC_REGISTER_NUM_LINK_ENTRIES 15:8 +#define PCIE_ROOT_COMPLEX_BASE_SIZE 0x0C // 7.9.8 +#define PCIE_ROOT_COMPLEX_LINK_ENTRY_SIZE 0x10 // 7.9.8.3 + +// TPH capability size related fields +#define PCIE_TPH_REQUESTOR_REGISTER 0x04 // 7.9.13.2 +#define PCIE_TPH_REQUESTOR_REGISTER_ST_TABLE_SIZE 26:16 +#define PCIE_TPH_BASE_SIZE 0x0C // 7.9.13 +#define PCIE_TPH_ST_ENTRY_SIZE 0x02 // 7.9.13.4 // Intel CPU family. #define INTEL_CPU_FAMILY_06 0x06 @@ -249,6 +412,7 @@ #define INTEL_CPU_MODEL_2D 0x2d #define INTEL_CPU_MODEL_3A 0x3a #define INTEL_CPU_MODEL_3F 0x3f + // Symbolic defines for each possible virtual channel enum { @@ -263,6 +427,49 @@ enum RM_PCIE_VIRTUAL_CHANNEL_INVALID }; +// Diagnostic collection actions. +#define RM_PCIE_ACTION_NOP 0 +#define RM_PCIE_ACTION_COLLECT_CONFIG_SPACE 1 +#define RM_PCIE_ACTION_COLLECT_PCI_CAP_STRUCT 2 +#define RM_PCIE_ACTION_COLLECT_PCIE_CAP_STRUCT 3 +#define RM_PCIE_ACTION_COLLECT_ALL_PCI_CAPS 4 +#define RM_PCIE_ACTION_COLLECT_ALL_PCIE_CAPS 5 +#define RM_PCIE_ACTION_REPORT_PCI_CAPS_COUNT 6 +#define RM_PCIE_ACTION_REPORT_PCIE_CAPS_COUNT 7 +#define RM_PCIE_ACTION_EOS 0xff + + +// Diagnostic collection device Type ids +#define RM_PCIE_DEVICE_TYPE_NONE 0xff +#define RM_PCIE_DEVICE_TYPE_GPU 0 +#define RM_PCIE_DEVICE_TYPE_UPSTREAM_BRIDGE 1 +#define RM_PCIE_DEVICE_COUNT 2 + +// Diagnostic collection capability Type ids +#define RM_PCIE_DC_CAP_TYPE_NONE 0xff +#define RM_PCIE_DC_CAP_TYPE_PCI 0 +#define RM_PCIE_DC_CAP_TYPE_PCIE 1 +#define RM_PCIE_DC_CAP_TYPE_COUNT 2 + +typedef struct _def_bif_dc_diagnostic_collection_command +{ + NvU8 action; + NvU8 deviceType; + NvU16 locator; + NvU16 length; +} CL_PCIE_DC_DIAGNOSTIC_COLLECTION_ENTRY; + +typedef struct _def_cl_pcie_dc_capability_map_entry +{ + NvU16 id; + NvU16 blkOffset; +} CL_PCIE_DC_CAPABILITY_MAP_ENTRY; +typedef struct +{ + NvU16 count; + CL_PCIE_DC_CAPABILITY_MAP_ENTRY entries[PCI_MAX_CAPS]; +} CL_PCIE_DC_CAPABILITY_MAP; + struct OBJCL; // root port setup functions NV_STATUS Broadcom_HT2100_setupFunc(OBJGPU *, OBJCL*); @@ -287,6 +494,6 @@ NV_STATUS AMD_RP1630_setupFunc(OBJGPU *, OBJCL*); NV_STATUS AMD_RP1483_setupFunc(OBJGPU *, OBJCL*); // Determines if the GPU is in a multi-GPU board based on devid checks -NvBool gpuIsMultiGpuBoard(OBJGPU *, NvBool *, NvBool *); +NvBool gpuIsMultiGpuBoard(OBJGPU *, NvBool *); #endif // NVPCIE_H diff --git a/src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h b/src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h index 546e12e4f..e5b17a0ed 100644 --- a/src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h +++ b/src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h @@ -214,6 +214,8 @@ 0x0000000f #define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_POWER_HINT_GET \ 0x00000010 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_CONFIGURE_PROGRAMMABLE_EDPP \ + 0x00000011 #define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_POLL 0x000000ff @@ -310,6 +312,11 @@ #define NV_MSGBOX_CMD_ARG1_BUNDLE_REQUEST_COUNT 11:8 #define NV_MSGBOX_CMD_ARG1_BUNDLE_DISP_RULE_COUNT 15:12 + +#define NV_MSGBOX_CMD_ARG1_GET_DEM_OLDEST 0x00000000 +#define NV_MSGBOX_CMD_ARG1_GET_DEM_BY_SEQ_NUMBER 0x00000001 +#define NV_MSGBOX_CMD_ARG1_GET_DEM_BY_TIMESTAMP 0x00000002 + #define NV_MSGBOX_CMD_ARG1_ECC_V6_ERROR_TYPE 15:8 #define NV_MSGBOX_CMD_ARG1_ECC_V6_ERROR_TYPE_CORRECTABLE_ERROR 0 #define NV_MSGBOX_CMD_ARG1_ECC_V6_ERROR_TYPE_UNCORRECTABLE_ERROR 1 @@ -346,6 +353,16 @@ #define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVDEC_UTILIZATION 0x0000000E #define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVJPG_UTILIZATION 0x0000000F #define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVOFA_UTILIZATION 0x00000010 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_RAW_TX_BW_PER_LINK 0x00000011 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_DATA_TX_BW_PER_LINK 0x00000012 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_RAW_RX_BW_PER_LINK 0x00000013 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVLINK_DATA_RX_BW_PER_LINK 0x00000014 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVDEC_UTIL_PER_INSTANCE 0x00000015 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_NVJPG_UTIL_PER_INSTANCE 0x00000016 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_INTEGER_UTILIZATION 0x00000017 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_DMMA_UTILIZATION 0x00000018 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_HMMA_UTILIZATION 0x00000019 +#define NV_MSGBOX_CMD_ARG1_GPM_METRIC_IMMA_UTILIZATION 0x0000001A #define NV_MSGBOX_CMD_ARG1_DYN_SYS_INFO_DRIVER_VERSION_V1 0x00000000 @@ -440,8 +457,11 @@ (NV_MSGBOX_CMD_ARG2_GET_POWER_HINT_INFO_PROFILES_PAGE_3 + 1) // Arg2 for _GPU_PERFORMANCE_MONITORING -#define NV_MSGBOX_CMD_ARG2_GPM_PARTITION 23:16 #define NV_MSGBOX_CMD_ARG2_GPM_PARTITION_AGGREGATE 0x000000FF +#define NV_MSGBOX_CMD_ARG2_GPM_PARTITION_INDEX 21:16 +#define NV_MSGBOX_CMD_ARG2_GPM_CI_METRICS_REQUESTED 23:23 +#define NV_MSGBOX_CMD_ARG2_GPM_CI_METRICS_REQUESTED_YES 0x00000001 +#define NV_MSGBOX_CMD_ARG2_GPM_CI_METRICS_REQUESTED_NO 0x00000000 #define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER 23:16 #define NV_MSGBOX_CMD_ARG2_GPM_MULTIPLIER_1X 0x00000001 @@ -816,6 +836,12 @@ #define NV_MSGBOX_DATA_CAP_4_SET_DEVICE_DISABLE 7:7 #define NV_MSGBOX_DATA_CAP_4_SET_DEVICE_DISABLE_NOT_AVAILABLE 0x00000000 #define NV_MSGBOX_DATA_CAP_4_SET_DEVICE_DISABLE_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_SET_ECC_MODE 8:8 +#define NV_MSGBOX_DATA_CAP_4_SET_ECC_MODE_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_SET_ECC_MODE_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_SET_MIG_MODE 10:10 +#define NV_MSGBOX_DATA_CAP_4_SET_MIG_MODE_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_SET_MIG_MODE_AVAILABLE 0x00000001 #define NV_MSGBOX_DATA_CAP_4_FAN_CURVE_POINTS_GET_SET 11:11 #define NV_MSGBOX_DATA_CAP_4_FAN_CURVE_POINTS_GET_SET_NOT_AVAILABLE 0x00000000 #define NV_MSGBOX_DATA_CAP_4_FAN_CURVE_POINTS_GET_SET_AVAILABLE 0x00000001 @@ -828,6 +854,9 @@ #define NV_MSGBOX_DATA_CAP_4_GPU_PERFORMANCE_MONITORING 24:24 #define NV_MSGBOX_DATA_CAP_4_GPU_PERFORMANCE_MONITORING_NOT_AVAILABLE 0x00000000 #define NV_MSGBOX_DATA_CAP_4_GPU_PERFORMANCE_MONITORING_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_CONFIGURE_PROGRAMMABLE_EDPP 30:30 +#define NV_MSGBOX_DATA_CAP_4_CONFIGURE_PROGRAMMABLE_EDPP_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_CONFIGURE_PROGRAMMABLE_EDPP_AVAILABLE 0x00000001 /* ECC counters */ #define NV_MSGBOX_DATA_ECC_CNT_16BIT_DBE 31:16 @@ -1145,6 +1174,20 @@ #define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_2_REPLAY_ROLLOVER_COUNT 15:0 #define NV_MSGBOX_DATA_PCIE_LINK_INFO_PAGE_2_NAKS_RCVD_COUNT 31:16 +/* + * Input for NV_MSGBOX_CMD_OPCODE_GPU_PERFORMANCE_MONITORING. Value is valid + * only if Arg2 != GPM_PARTITION_AGGREGATE and Arg2.Bit7 == 1 + */ +#define NV_MSGBOX_DATA_GPM_COMPUTE_INSTANCE_INDEX 15:8 + +/* + * The following three fields correspond to the data which is interpreted + * differently depending on GPM Metric specified in Arg1. + */ +#define NV_MSGBOX_DATA_GPM_NVLINK_INDEX 7:0 +#define NV_MSGBOX_DATA_GPM_NVDEC_INSTANCE 7:0 +#define NV_MSGBOX_DATA_GPM_NVJPG_INSTANCE 7:0 + /* MSGBOX Extended Data Register */ #define NV_MSGBOX_EXT_DATA_REG 31:0 @@ -1265,16 +1308,22 @@ /* Event types */ typedef enum { - NV_MSGBOX_EVENT_TYPE_SERVER_RESTART = 0, + NV_MSGBOX_EVENT_TYPE_SERVER_RESTART_COLD = 0, NV_MSGBOX_EVENT_TYPE_GPU_RESET_REQUIRED, - NV_MSGBOX_EVENT_TYPE_DRIVER_ERROR_MESSAGE, + NV_MSGBOX_EVENT_TYPE_DRIVER_ERROR_MESSAGE_OLDEST, NV_MSGBOX_EVENT_TYPE_TGP_LIMIT_SET_SUCCESS, NV_MSGBOX_EVENT_TYPE_CLOCK_LIMIT_SET_SUCCESS, NV_MSGBOX_EVENT_TYPE_ECC_TOGGLE_SUCCESS, NV_MSGBOX_EVENT_TYPE_MIG_TOGGLE_SUCCESS, + NV_MSGBOX_EVENT_TYPE_SERVER_RESTART_WARM, + NV_MSGBOX_EVENT_TYPE_DRIVER_ERROR_MESSAGE_NEW, NV_MSGBOX_NUM_EVENTS, /* insert new event types before this line */ } NvMsgboxEventType; +/* Legacy event names for compatipility */ +#define NV_MSGBOX_EVENT_TYPE_SERVER_RESTART NV_MSGBOX_EVENT_TYPE_SERVER_RESTART_COLD +#define NV_MSGBOX_EVENT_TYPE_DRIVER_ERROR_MESSAGE NV_MSGBOX_EVENT_TYPE_DRIVER_ERROR_MESSAGE_OLDEST + /* Bit mask of all defined events */ #define NV_MSGBOX_EVENT_TYPE__ALL (NVBIT(NV_MSGBOX_NUM_EVENTS) - 1) @@ -2012,6 +2061,34 @@ typedef struct // new param starting from here. } NV_MSGBOX_POWER_HINT_PARAMS; +/*! + * This param is used for NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_CONFIGURE_PROGRAMMABLE_EDPP + */ +typedef struct +{ + /*! + * [out] Power Hint in mW + */ + NvU32 data; +} NV_MSGBOX_PROGRAMMABLE_EDPP_PARAMS; + +#define NV_MSGBOX_PROGRAMMABLE_EDPP_PARAMS_DATA 31:0 +#define NV_MSGBOX_PROGRAMMABLE_EDPP_PARAMS_DATA_OPERATION 1:0 +#define NV_MSGBOX_PROGRAMMABLE_EDPP_PARAMS_DATA_OPERATION_GET 0x0 +#define NV_MSGBOX_PROGRAMMABLE_EDPP_PARAMS_DATA_OPERATION_SET 0x1 +#define NV_MSGBOX_PROGRAMMABLE_EDPP_PARAMS_DATA_OPERATION_CLEAR 0x2 + +#define NV_MSGBOX_PROGRAMMABLE_EDPP_PARAMS_DATA_MODE 3:2 +#define NV_MSGBOX_PROGRAMMABLE_EDPP_PARAMS_DATA_MODE_PERSISTENT 0x0 +#define NV_MSGBOX_PROGRAMMABLE_EDPP_PARAMS_DATA_MODE_ONESHOT 0x1 + +#define NV_MSGBOX_PROGRAMMABLE_EDPP_PARAMS_DATA_LIMIT_CURRENT 10:4 +#define NV_MSGBOX_PROGRAMMABLE_EDPP_PARAMS_DATA_LIMIT_RATED 17:11 +#define NV_MSGBOX_PROGRAMMABLE_EDPP_PARAMS_DATA_LIMIT_MAXIMUM 24:18 +#define NV_MSGBOX_PROGRAMMABLE_EDPP_PARAMS_DATA_LIMIT_MINIMUM 31:25 + +#define NV_MSGBOX_PROGRAMMABLE_EDPP_PARAMS_LIMIT_NOT_SET 0x7F + /*! * @brief Union of all possible parameter struct. Used to determine the maximum * amount of space parameter blocks can take. @@ -2031,6 +2108,7 @@ typedef union { NV_MSGBOX_CLOCK_LIMIT_GET_PARAMS clockLimitGet; NV_MSGBOX_THERMAL_FAN_V3_FAN_CURVE_POINTS_PARAMS fanCurvePointsV3; NV_MSGBOX_POWER_HINT_PARAMS powerHintParams; + NV_MSGBOX_PROGRAMMABLE_EDPP_PARAMS programmableEdppParams; } NV_MSGBOX_ASYNC_REQ_PARAMS_UNION; #endif // !NV_MSGBOX_NO_PARAM_STRUCTS @@ -2446,15 +2524,15 @@ typedef union { ( \ NV_MSGBOX_CMD(_GPU_PERFORMANCE_MONITORING, 0, 0) | \ DRF_DEF(_MSGBOX, _CMD, _ARG1_GPM_ACTION, type) | \ - DRF_DEF(_MSGBOX, _CMD, _ARG1_GPM_METRIC, metric) | \ - DRF_DEF(_MSGBOX, _CMD, _ARG2_GPM_PARTITION, partition) \ + DRF_NUM(_MSGBOX, _CMD, _ARG1_GPM_METRIC, metric) | \ + DRF_NUM(_MSGBOX, _CMD, _ARG2_GPM_PARTITION, partition) \ ) -#define NV_MSGBOX_CMD_GPM_SET_INTERVAL(interval) \ +#define NV_MSGBOX_CMD_GPM_SET_MULTIPLIER(multiplier) \ ( \ NV_MSGBOX_CMD(_GPU_PERFORMANCE_MONITORING, 0, 0) | \ - DRF_DEF(_MSGBOX, _CMD, _ARG1_GPM_ACTION, _SET_INTERVAL) | \ - DRF_DEF(_MSGBOX, _CMD, _ARG1_GPM_INTERVAL, (interval)) \ + DRF_DEF(_MSGBOX, _CMD, _ARG1_GPM_ACTION, _SET_MULTIPLIER) | \ + DRF_NUM(_MSGBOX, _CMD, _ARG2_GPM_MULTIPLIER, (multiplier)) \ ) #define NV_MSGBOX_GET_CMD_OPCODE(cmd) DRF_VAL(_MSGBOX, _CMD, _OPCODE, (cmd)) diff --git a/src/nvidia/arch/nvalloc/common/inc/rmlsfm.h b/src/nvidia/arch/nvalloc/common/inc/rmlsfm.h index 62b9c44f4..2e712609b 100644 --- a/src/nvidia/arch/nvalloc/common/inc/rmlsfm.h +++ b/src/nvidia/arch/nvalloc/common/inc/rmlsfm.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2011-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2011-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -484,6 +484,11 @@ typedef struct _def_acr_reserved_dmem NvU32 reservedDmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)]; // Always first.. } ACR_RESERVED_DMEM, *PACR_RESERVED_DMEM; +typedef struct _def_booter_reserved_dmem +{ + NvU32 reservedDmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)]; // Always first.. +} BOOTER_RESERVED_DMEM; + #define NV_FLCN_ACR_DESC_FLAGS_SIG_VERIF 0:0 #define NV_FLCN_ACR_DESC_FLAGS_SIG_VERIF_DISABLE 0 #define NV_FLCN_ACR_DESC_FLAGS_SIG_VERIF_ENABLE 1 diff --git a/src/nvidia/arch/nvalloc/unix/include/nv-nb-regs.h b/src/nvidia/arch/nvalloc/unix/include/nv-nb-regs.h index 45f7d25be..6282b357e 100644 --- a/src/nvidia/arch/nvalloc/unix/include/nv-nb-regs.h +++ b/src/nvidia/arch/nvalloc/unix/include/nv-nb-regs.h @@ -24,6 +24,8 @@ #ifndef _NV_NB_REGS_H_ #define _NV_NB_REGS_H_ +#include "nvdevid.h" + typedef struct { NvU32 subsystem_vendor_id; diff --git a/src/nvidia/arch/nvalloc/unix/include/nv-priv.h b/src/nvidia/arch/nvalloc/unix/include/nv-priv.h index b091586c1..b605a73af 100644 --- a/src/nvidia/arch/nvalloc/unix/include/nv-priv.h +++ b/src/nvidia/arch/nvalloc/unix/include/nv-priv.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -28,6 +28,7 @@ #include #include #include +#include #include @@ -39,13 +40,16 @@ #define NV_PRIV_REG_RD16(b,o) ((b)->Reg016[(o)/2]) #define NV_PRIV_REG_RD32(b,o) ((b)->Reg032[(o)/4]) -#define NV_NUM_CR_REGS 0x99 - struct OBJGPU; - -#define NV_BIT_PLANE_SIZE 64 * 1024 -#define NV_NUM_VGA_BIT_PLANES 4 +typedef struct +{ + NvBool baseValid; + VGAADDRDESC base; + NvBool workspaceBaseValid; + VGAADDRDESC workspaceBase; + NvU32 vesaMode; +} nv_vga_t; /* * device state during Power Management @@ -113,12 +117,10 @@ typedef struct nv_i2c_adapter_entry_s #define NV_INIT_FLAG_GPU_STATE_LOAD 0x0008 #define NV_INIT_FLAG_FIFO_WATCHDOG 0x0010 #define NV_INIT_FLAG_CORE_LOGIC 0x0020 -#define NV_INIT_FLAG_HIRES 0x0040 -#define NV_INIT_FLAG_DISP_STATE_SAVED 0x0080 -#define NV_INIT_FLAG_GPUMGR_ATTACH 0x0100 -#define NV_INIT_FLAG_PUBLIC_I2C 0x0400 -#define NV_INIT_FLAG_SCALABILITY 0x0800 -#define NV_INIT_FLAG_DMA 0x1000 +#define NV_INIT_FLAG_GPUMGR_ATTACH 0x0040 +#define NV_INIT_FLAG_PUBLIC_I2C 0x0080 +#define NV_INIT_FLAG_SCALABILITY 0x0100 +#define NV_INIT_FLAG_DMA 0x0200 #define MAX_I2C_ADAPTERS NV402C_CTRL_NUM_I2C_PORTS @@ -298,6 +300,12 @@ typedef struct nv_dynamic_power_s */ NvBool b_fine_not_supported; + /* + * This flag is used to check if a workitem is queued for + * RmQueueIdleSustainedWorkitem(). + */ + NvBool b_idle_sustained_workitem_queued; + /* * Counter to track clients disallowing GCOFF. */ @@ -321,14 +329,10 @@ typedef struct NvU32 pmc_boot_0; + nv_vga_t vga; + nv_efi_t efi; - NvU8 scr_vga_active[OBJ_MAX_HEADS]; - NvU8 scr_dcb_index_lo[OBJ_MAX_HEADS]; - NvU8 scr_dcb_index_hi[OBJ_MAX_HEADS]; - - NvU8 font_bitplanes[NV_NUM_VGA_BIT_PLANES][NV_BIT_PLANE_SIZE]; - NvU32 flags; NvU32 status; diff --git a/src/nvidia/arch/nvalloc/unix/include/nv.h b/src/nvidia/arch/nvalloc/unix/include/nv.h index 8537ec962..20ce3e7d8 100644 --- a/src/nvidia/arch/nvalloc/unix/include/nv.h +++ b/src/nvidia/arch/nvalloc/unix/include/nv.h @@ -40,6 +40,7 @@ #include #include "nv_stdarg.h" #include +#include #include #include @@ -160,8 +161,14 @@ typedef enum _TEGRASOC_WHICH_CLK TEGRASOC_WHICH_CLK_MAUD, TEGRASOC_WHICH_CLK_AZA_2XBIT, TEGRASOC_WHICH_CLK_AZA_BIT, - TEGRA234_CLK_MIPI_CAL, - TEGRA234_CLK_UART_FST_MIPI_CAL, + TEGRASOC_WHICH_CLK_MIPI_CAL, + TEGRASOC_WHICH_CLK_UART_FST_MIPI_CAL, + TEGRASOC_WHICH_CLK_SOR0_DIV, + TEGRASOC_WHICH_CLK_DISP_ROOT, + TEGRASOC_WHICH_CLK_HUB_ROOT, + TEGRASOC_WHICH_CLK_PLLA_DISP, + TEGRASOC_WHICH_CLK_PLLA_DISPHUB, + TEGRASOC_WHICH_CLK_PLLA, TEGRASOC_WHICH_CLK_MAX, // TEGRASOC_WHICH_CLK_MAX is defined for boundary checks only. } TEGRASOC_WHICH_CLK; @@ -304,7 +311,7 @@ typedef struct nv_alloc_mapping_context_s { typedef enum { - NV_SOC_IRQ_DISPLAY_TYPE, + NV_SOC_IRQ_DISPLAY_TYPE = 0x1, NV_SOC_IRQ_DPAUX_TYPE, NV_SOC_IRQ_GPIO_TYPE, NV_SOC_IRQ_HDACODEC_TYPE, @@ -368,6 +375,7 @@ typedef struct nv_state_t nv_aperture_t *mipical_regs; nv_aperture_t *fb, ud; nv_aperture_t *simregs; + nv_aperture_t *emc_regs; NvU32 num_dpaux_instance; NvU32 interrupt_line; @@ -430,9 +438,6 @@ typedef struct nv_state_t /* Variable to force allocation of 32-bit addressable memory */ NvBool force_dma32_alloc; - /* Variable to track if device has entered dynamic power state */ - NvBool dynamic_power_entered; - /* PCI power state should be D0 during system suspend */ NvBool d0_state_in_suspend; @@ -465,6 +470,9 @@ typedef struct nv_state_t /* Check if NVPCF DSM function is implemented under NVPCF or GPU device scope */ NvBool nvpcf_dsm_in_gpu_scope; + /* Bool to check if the device received a shutdown notification */ + NvBool is_shutdown; + } nv_state_t; // These define need to be in sync with defines in system.h @@ -473,6 +481,10 @@ typedef struct nv_state_t #define OS_TYPE_SUNOS 0x3 #define OS_TYPE_VMWARE 0x4 +#define NVFP_TYPE_NONE 0x0 +#define NVFP_TYPE_REFCOUNTED 0x1 +#define NVFP_TYPE_REGISTERED 0x2 + struct nv_file_private_t { NvHandle *handles; @@ -482,6 +494,7 @@ struct nv_file_private_t nv_file_private_t *ctl_nvfp; void *ctl_nvfp_priv; + NvU32 register_or_refcount; }; // Forward define the gpu ops structures @@ -513,8 +526,9 @@ typedef struct UvmGpuChannelResourceBindParams_tag *nvgpuChannelResourceBindPar typedef struct UvmGpuPagingChannelAllocParams_tag nvgpuPagingChannelAllocParams_t; typedef struct UvmGpuPagingChannel_tag *nvgpuPagingChannelHandle_t; typedef struct UvmGpuPagingChannelInfo_tag *nvgpuPagingChannelInfo_t; -typedef NV_STATUS (*nvPmaEvictPagesCallback)(void *, NvU32, NvU64 *, NvU32, NvU64, NvU64); -typedef NV_STATUS (*nvPmaEvictRangeCallback)(void *, NvU64, NvU64); +typedef enum UvmPmaGpuMemoryType_tag nvgpuGpuMemoryType_t; +typedef NV_STATUS (*nvPmaEvictPagesCallback)(void *, NvU32, NvU64 *, NvU32, NvU64, NvU64, nvgpuGpuMemoryType_t); +typedef NV_STATUS (*nvPmaEvictRangeCallback)(void *, NvU64, NvU64, nvgpuGpuMemoryType_t); /* * flags @@ -566,12 +580,6 @@ typedef enum NV_POWER_STATE_RUNNING } nv_power_state_t; -typedef enum -{ - NV_FIRMWARE_GSP, - NV_FIRMWARE_GSP_LOG -} nv_firmware_t; - #define NV_PRIMARY_VGA(nv) ((nv)->primary_vga) #define NV_IS_CTL_DEVICE(nv) ((nv)->flags & NV_FLAG_CONTROL) @@ -587,12 +595,6 @@ typedef enum #define NV_SOC_IS_ISO_IOMMU_PRESENT(nv) \ ((nv)->iso_iommu_present) -/* - * NVIDIA ACPI event ID to be passed into the core NVIDIA driver for - * AC/DC event. - */ -#define NV_SYSTEM_ACPI_BATTERY_POWER_EVENT 0x8002 - /* * GPU add/remove events */ @@ -604,8 +606,6 @@ typedef enum * to core NVIDIA driver for ACPI events. */ #define NV_SYSTEM_ACPI_EVENT_VALUE_DISPLAY_SWITCH_DEFAULT 0 -#define NV_SYSTEM_ACPI_EVENT_VALUE_POWER_EVENT_AC 0 -#define NV_SYSTEM_ACPI_EVENT_VALUE_POWER_EVENT_BATTERY 1 #define NV_SYSTEM_ACPI_EVENT_VALUE_DOCK_EVENT_UNDOCKED 0 #define NV_SYSTEM_ACPI_EVENT_VALUE_DOCK_EVENT_DOCKED 1 @@ -616,14 +616,18 @@ typedef enum #define NV_EVAL_ACPI_METHOD_NVIF 0x01 #define NV_EVAL_ACPI_METHOD_WMMX 0x02 -#define NV_I2C_CMD_READ 1 -#define NV_I2C_CMD_WRITE 2 -#define NV_I2C_CMD_SMBUS_READ 3 -#define NV_I2C_CMD_SMBUS_WRITE 4 -#define NV_I2C_CMD_SMBUS_QUICK_WRITE 5 -#define NV_I2C_CMD_SMBUS_QUICK_READ 6 -#define NV_I2C_CMD_SMBUS_BLOCK_READ 7 -#define NV_I2C_CMD_SMBUS_BLOCK_WRITE 8 +typedef enum { + NV_I2C_CMD_READ = 1, + NV_I2C_CMD_WRITE, + NV_I2C_CMD_SMBUS_READ, + NV_I2C_CMD_SMBUS_WRITE, + NV_I2C_CMD_SMBUS_QUICK_WRITE, + NV_I2C_CMD_SMBUS_QUICK_READ, + NV_I2C_CMD_SMBUS_BLOCK_READ, + NV_I2C_CMD_SMBUS_BLOCK_WRITE, + NV_I2C_CMD_BLOCK_READ, + NV_I2C_CMD_BLOCK_WRITE +} nv_i2c_cmd_t; // Flags needed by OSAllocPagesNode #define NV_ALLOC_PAGES_NODE_NONE 0x0 @@ -636,27 +640,33 @@ typedef enum #define NV_GET_NV_STATE(pGpu) \ (nv_state_t *)((pGpu) ? (pGpu)->pOsGpuInfo : NULL) -#define IS_REG_OFFSET(nv, offset, length) \ - (((offset) >= (nv)->regs->cpu_address) && \ - (((offset) + ((length)-1)) <= \ - (nv)->regs->cpu_address + ((nv)->regs->size-1))) +static inline NvBool IS_REG_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length) +{ + return ((offset >= nv->regs->cpu_address) && + ((offset + (length - 1)) <= (nv->regs->cpu_address + (nv->regs->size - 1)))); +} -#define IS_FB_OFFSET(nv, offset, length) \ - (((nv)->fb) && ((offset) >= (nv)->fb->cpu_address) && \ - (((offset) + ((length)-1)) <= (nv)->fb->cpu_address + ((nv)->fb->size-1))) +static inline NvBool IS_FB_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length) +{ + return ((nv->fb) && (offset >= nv->fb->cpu_address) && + ((offset + (length - 1)) <= (nv->fb->cpu_address + (nv->fb->size - 1)))); +} -#define IS_UD_OFFSET(nv, offset, length) \ - (((nv)->ud.cpu_address != 0) && ((nv)->ud.size != 0) && \ - ((offset) >= (nv)->ud.cpu_address) && \ - (((offset) + ((length)-1)) <= (nv)->ud.cpu_address + ((nv)->ud.size-1))) +static inline NvBool IS_UD_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length) +{ + return ((nv->ud.cpu_address != 0) && (nv->ud.size != 0) && + (offset >= nv->ud.cpu_address) && + ((offset + (length - 1)) <= (nv->ud.cpu_address + (nv->ud.size - 1)))); +} -#define IS_IMEM_OFFSET(nv, offset, length) \ - (((nv)->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address != 0) && \ - ((nv)->bars[NV_GPU_BAR_INDEX_IMEM].size != 0) && \ - ((offset) >= (nv)->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address) && \ - (((offset) + ((length) - 1)) <= \ - (nv)->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + \ - ((nv)->bars[NV_GPU_BAR_INDEX_IMEM].size - 1))) +static inline NvBool IS_IMEM_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length) +{ + return ((nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address != 0) && + (nv->bars[NV_GPU_BAR_INDEX_IMEM].size != 0) && + (offset >= nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address) && + ((offset + (length - 1)) <= (nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + + (nv->bars[NV_GPU_BAR_INDEX_IMEM].size - 1)))); +} #define NV_RM_MAX_MSIX_LINES 8 @@ -787,7 +797,7 @@ NV_STATUS NV_API_CALL nv_pci_trigger_recovery (nv_state_t *); NvBool NV_API_CALL nv_requires_dma_remap (nv_state_t *); NvBool NV_API_CALL nv_is_rm_firmware_active(nv_state_t *); -const void*NV_API_CALL nv_get_firmware(nv_state_t *, nv_firmware_t, const void **, NvU32 *); +const void*NV_API_CALL nv_get_firmware(nv_state_t *, nv_firmware_type_t, nv_firmware_chip_family_t, const void **, NvU32 *); void NV_API_CALL nv_put_firmware(const void *); nv_file_private_t* NV_API_CALL nv_get_file_private(NvS32, NvBool, void **); @@ -828,6 +838,7 @@ NV_STATUS NV_API_CALL nv_acquire_fabric_mgmt_cap (int, int*); int NV_API_CALL nv_cap_drv_init(void); void NV_API_CALL nv_cap_drv_exit(void); NvBool NV_API_CALL nv_is_gpu_accessible(nv_state_t *); +NvBool NV_API_CALL nv_match_gpu_os_info(nv_state_t *, void *); NvU32 NV_API_CALL nv_get_os_type(void); @@ -916,11 +927,11 @@ NvBool NV_API_CALL rm_is_supported_pci_device(NvU8 pci_class, void NV_API_CALL rm_i2c_remove_adapters (nvidia_stack_t *, nv_state_t *); NvBool NV_API_CALL rm_i2c_is_smbus_capable (nvidia_stack_t *, nv_state_t *, void *); -NV_STATUS NV_API_CALL rm_i2c_transfer (nvidia_stack_t *, nv_state_t *, void *, NvU8, NvU8, NvU8, NvU32, NvU8 *); +NV_STATUS NV_API_CALL rm_i2c_transfer (nvidia_stack_t *, nv_state_t *, void *, nv_i2c_cmd_t, NvU8, NvU8, NvU32, NvU8 *); NV_STATUS NV_API_CALL rm_perform_version_check (nvidia_stack_t *, void *, NvU32); -NV_STATUS NV_API_CALL rm_system_event (nvidia_stack_t *, NvU32, NvU32); +void NV_API_CALL rm_power_source_change_event (nvidia_stack_t *, NvU32); void NV_API_CALL rm_disable_gpu_state_persistence (nvidia_stack_t *sp, nv_state_t *); NV_STATUS NV_API_CALL rm_p2p_init_mapping (nvidia_stack_t *, NvU64, NvU64 *, NvU64 *, NvU64 *, NvU64 *, NvU64, NvU64, NvU64, NvU64, void (*)(void *), void *); @@ -944,6 +955,7 @@ void NV_API_CALL rm_kernel_rmapi_op(nvidia_stack_t *sp, void *ops_cmd); NvBool NV_API_CALL rm_get_device_remove_flag(nvidia_stack_t *sp, NvU32 gpu_id); NV_STATUS NV_API_CALL rm_gpu_copy_mmu_faults(nvidia_stack_t *, nv_state_t *, NvU32 *); NV_STATUS NV_API_CALL rm_gpu_copy_mmu_faults_unlocked(nvidia_stack_t *, nv_state_t *, NvU32 *); +NV_STATUS NV_API_CALL rm_gpu_handle_mmu_faults(nvidia_stack_t *, nv_state_t *, NvU32 *); NvBool NV_API_CALL rm_gpu_need_4k_page_isolation(nv_state_t *); NvBool NV_API_CALL rm_is_chipset_io_coherent(nv_stack_t *); NvBool NV_API_CALL rm_init_event_locks(nvidia_stack_t *, nv_state_t *); @@ -969,12 +981,13 @@ const char* NV_API_CALL rm_get_dynamic_power_management_status(nvidia_stack_t *, const char* NV_API_CALL rm_get_gpu_gcx_support(nvidia_stack_t *, nv_state_t *, NvBool); void NV_API_CALL rm_acpi_notify(nvidia_stack_t *, nv_state_t *, NvU32); -NV_STATUS NV_API_CALL rm_get_clientnvpcf_power_limits(nvidia_stack_t *, nv_state_t *, NvU32 *, NvU32 *); + +NvBool NV_API_CALL rm_is_altstack_in_use(void); /* vGPU VFIO specific functions */ NV_STATUS NV_API_CALL nv_vgpu_create_request(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU32, NvU16 *, NvU32, NvBool *); NV_STATUS NV_API_CALL nv_vgpu_delete(nvidia_stack_t *, const NvU8 *, NvU16); -NV_STATUS NV_API_CALL nv_vgpu_get_type_ids(nvidia_stack_t *, nv_state_t *, NvU32 *, NvU32 **, NvBool); +NV_STATUS NV_API_CALL nv_vgpu_get_type_ids(nvidia_stack_t *, nv_state_t *, NvU32 *, NvU32 *, NvBool, NvU8, NvBool); NV_STATUS NV_API_CALL nv_vgpu_get_type_info(nvidia_stack_t *, nv_state_t *, NvU32, char *, int, NvU8); NV_STATUS NV_API_CALL nv_vgpu_get_bar_info(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU64 *, NvU32, void *); NV_STATUS NV_API_CALL nv_vgpu_start(nvidia_stack_t *, const NvU8 *, void *, NvS32 *, NvU8 *, NvU32); @@ -998,6 +1011,16 @@ static inline const NvU8 *nv_get_cached_uuid(nv_state_t *nv) return nv->nv_uuid_cache.valid ? nv->nv_uuid_cache.uuid : NULL; } +/* nano second resolution timer callback structure */ +typedef struct nv_nano_timer nv_nano_timer_t; + +/* nano timer functions */ +void NV_API_CALL nv_create_nano_timer(nv_state_t *, void *pTmrEvent, nv_nano_timer_t **); +void NV_API_CALL nv_start_nano_timer(nv_state_t *nv, nv_nano_timer_t *, NvU64 timens); +NV_STATUS NV_API_CALL rm_run_nano_timer_callback(nvidia_stack_t *, nv_state_t *, void *pTmrEvent); +void NV_API_CALL nv_cancel_nano_timer(nv_state_t *, nv_nano_timer_t *); +void NV_API_CALL nv_destroy_nano_timer(nv_state_t *nv, nv_nano_timer_t *); + #if defined(NVCPU_X86_64) static inline NvU64 nv_rdtsc(void) diff --git a/src/nvidia/arch/nvalloc/unix/include/os-interface.h b/src/nvidia/arch/nvalloc/unix/include/os-interface.h index 0aaf20521..9ebeeed83 100644 --- a/src/nvidia/arch/nvalloc/unix/include/os-interface.h +++ b/src/nvidia/arch/nvalloc/unix/include/os-interface.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -143,6 +143,14 @@ void NV_API_CALL os_free_semaphore (void *); NV_STATUS NV_API_CALL os_acquire_semaphore (void *); NV_STATUS NV_API_CALL os_cond_acquire_semaphore (void *); NV_STATUS NV_API_CALL os_release_semaphore (void *); +void* NV_API_CALL os_alloc_rwlock (void); +void NV_API_CALL os_free_rwlock (void *); +NV_STATUS NV_API_CALL os_acquire_rwlock_read (void *); +NV_STATUS NV_API_CALL os_acquire_rwlock_write (void *); +NV_STATUS NV_API_CALL os_cond_acquire_rwlock_read (void *); +NV_STATUS NV_API_CALL os_cond_acquire_rwlock_write(void *); +void NV_API_CALL os_release_rwlock_read (void *); +void NV_API_CALL os_release_rwlock_write (void *); NvBool NV_API_CALL os_semaphore_may_sleep (void); NV_STATUS NV_API_CALL os_get_version_info (os_version_info*); NvBool NV_API_CALL os_is_isr (void); diff --git a/src/nvidia/arch/nvalloc/unix/include/osapi.h b/src/nvidia/arch/nvalloc/unix/include/osapi.h index 484351ec8..7c71874e5 100644 --- a/src/nvidia/arch/nvalloc/unix/include/osapi.h +++ b/src/nvidia/arch/nvalloc/unix/include/osapi.h @@ -128,7 +128,7 @@ void RmI2cAddGpuPorts(nv_state_t *); NV_STATUS RmInitX86EmuState(OBJGPU *); void RmFreeX86EmuState(OBJGPU *); -NV_STATUS RmSystemEvent(nv_state_t *, NvU32, NvU32); +NV_STATUS RmPowerSourceChangeEvent(nv_state_t *, NvU32); const NvU8 *RmGetGpuUuidRaw(nv_state_t *); @@ -144,7 +144,7 @@ NV_STATUS rm_free_os_event (NvHandle, NvU32); NV_STATUS rm_get_event_data (nv_file_private_t *, NvP64, NvU32 *); void rm_client_free_os_events (NvHandle); -NV_STATUS rm_create_mmap_context (nv_state_t *, NvHandle, NvHandle, NvHandle, NvP64, NvU64, NvU64, NvU32, NvU32); +NV_STATUS rm_create_mmap_context (NvHandle, NvHandle, NvHandle, NvP64, NvU64, NvU64, NvU32, NvU32); NV_STATUS rm_update_device_mapping_info (NvHandle, NvHandle, NvHandle, void *, void *); NV_STATUS rm_access_registry (NvHandle, NvHandle, NvU32, NvP64, NvU32, NvP64, NvU32, NvP64, NvU32 *, NvU32 *, NvU32 *); diff --git a/src/nvidia/arch/nvalloc/unix/src/escape.c b/src/nvidia/arch/nvalloc/unix/src/escape.c index 585fe50f6..c7b451a46 100644 --- a/src/nvidia/arch/nvalloc/unix/src/escape.c +++ b/src/nvidia/arch/nvalloc/unix/src/escape.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -46,6 +46,8 @@ #include // NV01_MEMORY_SYSTEM #include // NV01_MEMORY_SYSTEM_OS_DESCRIPTOR +#include + #define NV_CTL_DEVICE_ONLY(nv) \ { \ if (((nv)->flags & NV_FLAG_CONTROL) == 0) \ @@ -64,6 +66,56 @@ } \ } +static NvBool RmIsDeviceRefNeeded(NVOS54_PARAMETERS *pApi) +{ + switch(pApi->cmd) + { + case NV00FD_CTRL_CMD_ATTACH_MEM: + return NV_TRUE; + default: + return NV_FALSE; + } +} + +static NV_STATUS RmGetDeviceFd(NVOS54_PARAMETERS *pApi, NvS32 *pFd) +{ + RMAPI_PARAM_COPY paramCopy; + void *pKernelParams; + NvU32 paramSize; + NV_STATUS status; + + *pFd = -1; + + switch(pApi->cmd) + { + case NV00FD_CTRL_CMD_ATTACH_MEM: + paramSize = sizeof(NV00FD_CTRL_ATTACH_MEM_PARAMS); + break; + default: + return NV_ERR_INVALID_ARGUMENT; + } + + RMAPI_PARAM_COPY_INIT(paramCopy, pKernelParams, pApi->params, paramSize, 1); + + status = rmapiParamsAcquire(¶mCopy, NV_TRUE); + if (status != NV_OK) + return status; + + switch(pApi->cmd) + { + case NV00FD_CTRL_CMD_ATTACH_MEM: + *pFd = (NvS32)((NV00FD_CTRL_ATTACH_MEM_PARAMS *)pKernelParams)->devDescriptor; + break; + default: + NV_ASSERT(0); + break; + } + + NV_ASSERT(rmapiParamsRelease(¶mCopy) == NV_OK); + + return status; +} + // Only return errors through pApi->status static void RmCreateOsDescriptor(NVOS32_PARAMETERS *pApi, API_SECURITY_INFO secInfo) { @@ -91,6 +143,7 @@ static void RmCreateOsDescriptor(NVOS32_PARAMETERS *pApi, API_SECURITY_INFO secI pageCount = (1 + ((allocSize - 1) / os_page_size)); writable = FLD_TEST_DRF(OS32, _ATTR2, _PROTECTION_USER, _READ_WRITE, pApi->data.AllocOsDesc.attr2); + flags = FLD_SET_DRF_NUM(_LOCK_USER_PAGES, _FLAGS, _WRITE, writable, flags); rmStatus = os_lock_user_pages(pDescriptor, pageCount, &pPageArray, flags); if (rmStatus == NV_OK) @@ -243,6 +296,7 @@ NV_STATUS RmIoctl( secInfo.privLevel = osIsAdministrator() ? RS_PRIV_LEVEL_USER_ROOT : RS_PRIV_LEVEL_USER; secInfo.paramLocation = PARAM_LOCATION_USER; secInfo.pProcessToken = NULL; + secInfo.gpuOsInfo = NULL; secInfo.clientOSInfo = nvfp->ctl_nvfp; if (secInfo.clientOSInfo == NULL) secInfo.clientOSInfo = nvfp; @@ -282,7 +336,7 @@ NV_STATUS RmIoctl( (!FLD_TEST_DRF(OS02, _FLAGS, _MAPPING, _NO_MAP, flags)) && (pParms->status == NV_OK)) { - if (rm_create_mmap_context(nv, pParms->hRoot, + if (rm_create_mmap_context(pParms->hRoot, pParms->hObjectParent, pParms->hObjectNew, pParms->pMemory, pParms->limit + 1, 0, NV_MEMORY_DEFAULT, @@ -464,7 +518,7 @@ NV_STATUS RmIoctl( if (pParms->status == NV_OK) { - pParms->status = rm_create_mmap_context(nv, pParms->hClient, + pParms->status = rm_create_mmap_context(pParms->hClient, pParms->hDevice, pParms->hMemory, pParms->pLinearAddress, pParms->length, pParms->offset, @@ -700,6 +754,9 @@ NV_STATUS RmIoctl( case NV_ESC_RM_CONTROL: { NVOS54_PARAMETERS *pApi = data; + void *priv = NULL; + nv_file_private_t *dev_nvfp = NULL; + NvS32 fd; NV_CTL_DEVICE_ONLY(nv); @@ -709,7 +766,51 @@ NV_STATUS RmIoctl( goto done; } + if (RmIsDeviceRefNeeded(pApi)) + { + rmStatus = RmGetDeviceFd(pApi, &fd); + if (rmStatus != NV_OK) + { + goto done; + } + + dev_nvfp = nv_get_file_private(fd, NV_FALSE, &priv); + if (dev_nvfp == NULL) + { + rmStatus = NV_ERR_INVALID_DEVICE; + goto done; + } + + // Check to avoid cyclic dependency with NV_ESC_REGISTER_FD + if (!portAtomicCompareAndSwapU32(&dev_nvfp->register_or_refcount, + NVFP_TYPE_REFCOUNTED, + NVFP_TYPE_NONE)) + { + // Is this already refcounted... + if (dev_nvfp->register_or_refcount != NVFP_TYPE_REFCOUNTED) + { + nv_put_file_private(priv); + rmStatus = NV_ERR_IN_USE; + goto done; + } + } + + secInfo.gpuOsInfo = priv; + } + Nv04ControlWithSecInfo(pApi, secInfo); + + if ((pApi->status != NV_OK) && (priv != NULL)) + { + // + // No need to reset `register_or_refcount` as it might be set + // for previous successful calls. We let it clear with FD close. + // + nv_put_file_private(priv); + + secInfo.gpuOsInfo = NULL; + } + break; } @@ -751,7 +852,7 @@ NV_STATUS RmIoctl( } // LOCK: acquire API lock - rmStatus = rmApiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI); + rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI); if (rmStatus != NV_OK) goto done; @@ -759,7 +860,7 @@ NV_STATUS RmIoctl( if (nvfp->ctl_nvfp != NULL) { // UNLOCK: release API lock - rmApiLockRelease(); + rmapiLockRelease(); rmStatus = NV_ERR_INVALID_STATE; goto done; } @@ -776,7 +877,7 @@ NV_STATUS RmIoctl( if (ctl_nvfp == NULL) { // UNLOCK: release API lock - rmApiLockRelease(); + rmapiLockRelease(); rmStatus = NV_ERR_INVALID_ARGUMENT; goto done; } @@ -787,11 +888,23 @@ NV_STATUS RmIoctl( { nv_put_file_private(priv); // UNLOCK: release API lock - rmApiLockRelease(); + rmapiLockRelease(); rmStatus = NV_ERR_INVALID_ARGUMENT; goto done; } + // Check to avoid cyclic dependency with device refcounting + if (!portAtomicCompareAndSwapU32(&nvfp->register_or_refcount, + NVFP_TYPE_REGISTERED, + NVFP_TYPE_NONE)) + { + nv_put_file_private(priv); + // UNLOCK: release API lock + rmapiLockRelease(); + rmStatus = NV_ERR_IN_USE; + goto done; + } + // // nvfp->ctl_nvfp is read outside the lock, so set it atomically. // Note that once set, this can never be removed until the fd @@ -803,7 +916,7 @@ NV_STATUS RmIoctl( nvfp->ctl_nvfp_priv = priv; // UNLOCK: release API lock - rmApiLockRelease(); + rmapiLockRelease(); // NOTE: nv_put_file_private(priv) is not called here. It MUST be // called during cleanup of this nvfp. diff --git a/src/nvidia/arch/nvalloc/unix/src/exports-stubs.c b/src/nvidia/arch/nvalloc/unix/src/exports-stubs.c index ef7008a4a..4dac378a6 100644 --- a/src/nvidia/arch/nvalloc/unix/src/exports-stubs.c +++ b/src/nvidia/arch/nvalloc/unix/src/exports-stubs.c @@ -207,16 +207,6 @@ os_unref_dynamic_power { } -NV_STATUS NV_API_CALL rm_get_clientnvpcf_power_limits( - nvidia_stack_t *sp, - nv_state_t *nv, - NvU32 *limitRated, - NvU32 *limitCurr -) -{ - return NV_ERR_NOT_SUPPORTED; -} - NV_STATUS deviceCtrlCmdOsUnixVTSwitch_IMPL ( @@ -235,24 +225,6 @@ NV_STATUS NV_API_CALL rm_save_low_res_mode( return NV_ERR_NOT_SUPPORTED; } -NV_STATUS NV_API_CALL rm_gpu_copy_mmu_faults( - nvidia_stack_t *sp, - nv_state_t *nv, - NvU32 *faultsCopied -) -{ - return NV_OK; -} - -NV_STATUS NV_API_CALL rm_gpu_copy_mmu_faults_unlocked( - nvidia_stack_t *sp, - nv_state_t *nv, - NvU32 *faultsCopied -) -{ - return NV_OK; -} - NV_STATUS RmInitX86EmuState(OBJGPU *pGpu) { return NV_OK; diff --git a/src/nvidia/arch/nvalloc/unix/src/os-hypervisor-stubs.c b/src/nvidia/arch/nvalloc/unix/src/os-hypervisor-stubs.c deleted file mode 100644 index da473ca29..000000000 --- a/src/nvidia/arch/nvalloc/unix/src/os-hypervisor-stubs.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "nvstatus.h" -#include "os/os.h" -#include "nv.h" -#include "nv-hypervisor.h" - -HYPERVISOR_TYPE NV_API_CALL nv_get_hypervisor_type(void) -{ - return OS_HYPERVISOR_UNKNOWN; -} - -NV_STATUS NV_API_CALL nv_vgpu_get_type_ids( - nvidia_stack_t *sp, - nv_state_t *pNv, - NvU32 *numVgpuTypes, - NvU32 **vgpuTypeIds, - NvBool isVirtfn -) -{ - return NV_ERR_NOT_SUPPORTED; -} - -NV_STATUS NV_API_CALL nv_vgpu_process_vf_info( - nvidia_stack_t *sp, - nv_state_t *pNv, - NvU8 cmd, - NvU32 domain, - NvU8 bus, - NvU8 slot, - NvU8 function, - NvBool isMdevAttached, - void *vf_pci_info -) -{ - return NV_ERR_NOT_SUPPORTED; -} - -NV_STATUS NV_API_CALL nv_vgpu_get_type_info( - nvidia_stack_t *sp, - nv_state_t *pNv, - NvU32 vgpuTypeId, - char *buffer, - int type_info, - NvU8 devfn -) -{ - return NV_ERR_NOT_SUPPORTED; -} - -NV_STATUS NV_API_CALL nv_vgpu_create_request( - nvidia_stack_t *sp, - nv_state_t *pNv, - const NvU8 *pMdevUuid, - NvU32 vgpuTypeId, - NvU16 *vgpuId, - NvU32 gpuPciBdf, - NvBool *is_driver_vm -) -{ - return NV_ERR_NOT_SUPPORTED; -} - -NV_STATUS NV_API_CALL nv_vgpu_update_request( - nvidia_stack_t *sp , - const NvU8 *pMdevUuid, - VGPU_DEVICE_STATE deviceState, - NvU64 *offsets, - NvU64 *sizes, - const char *configParams -) -{ - return NV_ERR_NOT_SUPPORTED; -} - -NV_STATUS NV_API_CALL nv_vgpu_get_sparse_mmap( - nvidia_stack_t *sp , - nv_state_t *pNv, - const NvU8 *pMdevUuid, - NvU64 **offsets, - NvU64 **sizes, - NvU32 *numAreas -) -{ - return NV_ERR_NOT_SUPPORTED; -} - -NV_STATUS NV_API_CALL nv_gpu_bind_event( - nvidia_stack_t *sp -) -{ - return NV_ERR_NOT_SUPPORTED; -} - -NV_STATUS NV_API_CALL nv_vgpu_start( - nvidia_stack_t *sp, - const NvU8 *pMdevUuid, - void *waitQueue, - NvS32 *returnStatus, - NvU8 *vmName, - NvU32 qemuPid -) -{ - return NV_ERR_NOT_SUPPORTED; -} - -NV_STATUS NV_API_CALL nv_vgpu_delete( - nvidia_stack_t *sp, - const NvU8 *pMdevUuid, - NvU16 vgpuId -) -{ - return NV_ERR_NOT_SUPPORTED; -} - -NV_STATUS NV_API_CALL nv_vgpu_get_bar_info( - nvidia_stack_t *sp, - nv_state_t *pNv, - const NvU8 *pMdevUuid, - NvU64 *size, - NvU32 regionIndex, - void *pVgpuVfioRef -) -{ - return NV_ERR_NOT_SUPPORTED; -} - -void initVGXSpecificRegistry(OBJGPU *pGpu) -{} - diff --git a/src/nvidia/arch/nvalloc/unix/src/os-hypervisor.c b/src/nvidia/arch/nvalloc/unix/src/os-hypervisor.c new file mode 100644 index 000000000..3982c35e8 --- /dev/null +++ b/src/nvidia/arch/nvalloc/unix/src/os-hypervisor.c @@ -0,0 +1,1023 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * + * @file os-hypervisor.c + * @brief OS specific Hypervisor interfaces for RM + * + */ + +#include "os/os.h" +#include "nv.h" +#include "nv-priv.h" +#include +#include +#include "core/thread_state.h" +#include "core/locks.h" +#include "virtualization/kernel_vgpu_mgr.h" +#include "kernel/gpu/mig_mgr/kernel_mig_manager.h" +#include "kernel/gpu/fifo/kernel_fifo.h" +#include "osapi.h" +#include "virtualization/kernel_hostvgpudeviceapi.h" +#include +#include "gpu/bif/kernel_bif.h" +#include "gpu/bus/kern_bus.h" +#include // NV_PMC_BOOT_1_VGPU +#include "nvdevid.h" + +#define NV_VFIO_PCI_BAR1_REGION_INDEX 1 +#define NV_VFIO_PCI_BAR2_REGION_INDEX 2 +#define NV_VFIO_PCI_BAR3_REGION_INDEX 3 + +static NV_STATUS nv_parse_config_params(const char *, const char *, const char, NvU32 *); + +void hypervisorSetHypervVgpuSupported_IMPL(POBJHYPERVISOR pHypervisor) +{ + pHypervisor->bIsHypervVgpuSupported = NV_TRUE; +} + +NvBool hypervisorIsVgxHyper_IMPL(void) +{ + return os_is_vgx_hyper(); +} + +NV_STATUS hypervisorInjectInterrupt_IMPL +( + POBJHYPERVISOR pHypervisor, + VGPU_NS_INTR *pVgpuNsIntr +) +{ + NV_STATUS status = NV_ERR_NOT_SUPPORTED; + + if (pVgpuNsIntr->pVgpuVfioRef) + status = osVgpuInjectInterrupt(pVgpuNsIntr->pVgpuVfioRef); + else + { + if (pVgpuNsIntr->guestMSIAddr && pVgpuNsIntr->guestMSIData) + { + status = os_inject_vgx_msi((NvU16)pVgpuNsIntr->guestDomainId, + pVgpuNsIntr->guestMSIAddr, + pVgpuNsIntr->guestMSIData); + } + } + + return status; +} + +HYPERVISOR_TYPE NV_API_CALL nv_get_hypervisor_type(void) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + POBJHYPERVISOR pHypervisor = SYS_GET_HYPERVISOR(pSys); + return hypervisorGetHypervisorType(pHypervisor); +} + +static NV_STATUS get_available_instances( + NvU32 *avail_instances, + nv_state_t *pNv, + VGPU_TYPE *vgpuTypeInfo, + NvU32 pgpuIndex, + NvU8 devfn +) +{ + NV_STATUS rmStatus = NV_OK; + OBJGPU *pGpu = NULL; + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys); + + *avail_instances = 0; + + pGpu = NV_GET_NV_PRIV_PGPU(pNv); + if (pGpu == NULL) + { + NV_PRINTF(LEVEL_ERROR, "%s GPU handle is not valid \n", __FUNCTION__); + rmStatus = NV_ERR_INVALID_STATE; + goto exit; + } + + /* TODO: Needs to have a proper fix this for DriverVM config */ + if (gpuIsSriovEnabled(pGpu) && + !(pHypervisor->getProperty(pHypervisor, PDB_PROP_HYPERVISOR_DRIVERVM_ENABLED))) + { + NvU8 fnId = devfn - pGpu->sriovState.firstVFOffset; + + if (fnId > 63) + { + NV_ASSERT(0); + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto exit; + } + + if (IS_MIG_ENABLED(pGpu)) + { + if (IS_MIG_IN_USE(pGpu)) { + NvU64 swizzIdInUseMask = 0; + NvU32 partitionFlag = PARTITIONID_INVALID; + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + NvU32 id; + + swizzIdInUseMask = kmigmgrGetSwizzIdInUseMask(pGpu, pKernelMIGManager); + + rmStatus = kvgpumgrGetPartitionFlag(vgpuTypeInfo->vgpuTypeId, + &partitionFlag); + if (rmStatus != NV_OK) + { + // Query for a non MIG vgpuType + NV_PRINTF(LEVEL_ERROR, "%s Query for a non MIG vGPU type \n", + __FUNCTION__); + rmStatus = NV_OK; + goto exit; + } + + // Determine valid swizzids not assigned to any vGPU device. + FOR_EACH_INDEX_IN_MASK(64, id, swizzIdInUseMask) + { + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance; + NvU64 mask = 0; + + rmStatus = kmigmgrGetGPUInstanceInfo(pGpu, pKernelMIGManager, + id, &pKernelMIGGpuInstance); + if (rmStatus != NV_OK) + { + // Didn't find requested GPU instance + NV_PRINTF(LEVEL_ERROR, + "No valid GPU instance with SwizzId - %d found\n", id); + goto exit; + } + + mask = NVBIT64(id); + + if (pKernelMIGGpuInstance->partitionFlag == partitionFlag) + { + // Validate that same ID is not already set and VF is available + if (!(mask & pKernelVgpuMgr->pgpuInfo[pgpuIndex].assignedSwizzIdMask) && + !(pKernelVgpuMgr->pgpuInfo[pgpuIndex].createdVfMask & NVBIT64(fnId))) + { + *avail_instances = 1; + break; + } + } + } + FOR_EACH_INDEX_IN_MASK_END; + } + } + else + { + if (pKernelVgpuMgr->pgpuInfo[pgpuIndex].numCreatedVgpu < vgpuTypeInfo->maxInstance) + { + if (vgpuTypeInfo->gpuInstanceSize) + { + // Query for a MIG vgpuType + NV_PRINTF(LEVEL_ERROR, "%s Query for a MIG vGPU type \n", + __FUNCTION__); + rmStatus = NV_OK; + goto exit; + } + + if (!(pKernelVgpuMgr->pgpuInfo[pgpuIndex].createdVfMask & NVBIT64(fnId))) + { + if (kvgpumgrCheckVgpuTypeCreatable(&pKernelVgpuMgr->pgpuInfo[pgpuIndex], vgpuTypeInfo) == NV_OK) + *avail_instances = 1; + } + } + } + } + else + { + if (kvgpumgrCheckVgpuTypeCreatable(&pKernelVgpuMgr->pgpuInfo[pgpuIndex], vgpuTypeInfo) == NV_OK) + *avail_instances = vgpuTypeInfo->maxInstance - pKernelVgpuMgr->pgpuInfo[pgpuIndex].numCreatedVgpu; + } + +exit: + return rmStatus; +} + +#define MAX_STR_LEN 256 +NV_STATUS NV_API_CALL nv_vgpu_get_type_info( + nvidia_stack_t *sp, + nv_state_t *pNv, + NvU32 vgpuTypeId, + char *buffer, + int type_info, + NvU8 devfn +) +{ + THREAD_STATE_NODE threadState; + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPU *pGpu = NULL; + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + NV_STATUS rmStatus = NV_OK; + VGPU_TYPE *vgpuTypeInfo; + NvU32 pgpuIndex, i, avail_instances = 0; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR)) == NV_OK) + { + pGpu = NV_GET_NV_PRIV_PGPU(pNv); + if (pGpu == NULL) + { + NV_PRINTF(LEVEL_ERROR, "%s GPU handle is not valid \n", __FUNCTION__); + rmStatus = NV_ERR_INVALID_STATE; + goto exit; + } + + if ((rmStatus = kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pNv->gpu_id, &pgpuIndex)) == + NV_OK) + { + for (i = 0; i < MAX_VGPU_TYPES_PER_PGPU; i++) + { + vgpuTypeInfo = pKernelVgpuMgr->pgpuInfo[pgpuIndex].vgpuTypes[i]; + if (vgpuTypeInfo == NULL) + break; + + if (vgpuTypeInfo->vgpuTypeId != vgpuTypeId) + continue; + + switch (type_info) + { + case VGPU_TYPE_NAME: + os_snprintf(buffer, VGPU_STRING_BUFFER_SIZE, "%s\n", + vgpuTypeInfo->vgpuName); + break; + case VGPU_TYPE_DESCRIPTION: + os_snprintf(buffer, MAX_STR_LEN, + "num_heads=%d, frl_config=%d, " + "framebuffer=%dM, max_resolution=%dx%d, max_instance=%d\n", + vgpuTypeInfo->numHeads, vgpuTypeInfo->frlConfig, + vgpuTypeInfo->profileSize >> 20, + vgpuTypeInfo->maxResolutionX, + vgpuTypeInfo->maxResolutionY, + vgpuTypeInfo->maxInstance); + break; + case VGPU_TYPE_INSTANCES: + rmStatus = get_available_instances(&avail_instances, pNv, + vgpuTypeInfo, + pgpuIndex, devfn); + if (rmStatus != NV_OK) + goto exit; + + os_snprintf(buffer, MAX_STR_LEN, "%d\n", avail_instances); + break; + default: + rmStatus = NV_ERR_INVALID_ARGUMENT; + } + break; + } + } + +exit: + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL nv_vgpu_get_type_ids( + nvidia_stack_t *sp, + nv_state_t *pNv, + NvU32 *numVgpuTypes, + NvU32 *vgpuTypeIds, + NvBool isVirtfn, + NvU8 devfn, + NvBool getCreatableTypes +) +{ + THREAD_STATE_NODE threadState; + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + NV_STATUS rmStatus = NV_OK; + NvU32 pgpuIndex, i, avail_instances = 0; + NvU32 numSupportedVgpuTypes = 0; + VGPU_TYPE *vgpuTypeInfo; + void *fp; + + if (!vgpuTypeIds || !numVgpuTypes) + return NV_ERR_INVALID_ARGUMENT; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR)) == NV_OK) + { + if ((rmStatus = kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pNv->gpu_id, &pgpuIndex)) == + NV_OK) + { + if (pKernelVgpuMgr->pgpuInfo[pgpuIndex].sriovEnabled && !isVirtfn) + { + *numVgpuTypes = 0; + } + else + { + numSupportedVgpuTypes = pKernelVgpuMgr->pgpuInfo[pgpuIndex].numVgpuTypes; + *numVgpuTypes = 0; + + for (i = 0; i < numSupportedVgpuTypes; i++) + { + vgpuTypeInfo = pKernelVgpuMgr->pgpuInfo[pgpuIndex].vgpuTypes[i]; + + if (!getCreatableTypes) + { + // Return all available types + vgpuTypeIds[*numVgpuTypes] = vgpuTypeInfo->vgpuTypeId; + (*numVgpuTypes)++; + continue; + } + + rmStatus = get_available_instances(&avail_instances, pNv, + vgpuTypeInfo, pgpuIndex, + devfn); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to get available instances for vGPU ID: %d, status: 0x%x\n", + vgpuTypeInfo->vgpuTypeId, rmStatus); + continue; + } + + if (avail_instances == 0) + continue; + + vgpuTypeIds[*numVgpuTypes] = vgpuTypeInfo->vgpuTypeId; + (*numVgpuTypes)++; + } + } + } + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL nv_vgpu_delete( + nvidia_stack_t *sp, + const NvU8 *pMdevUuid, + NvU16 vgpuId +) +{ + THREAD_STATE_NODE threadState; + void *fp = NULL; + NvU32 rmStatus = NV_OK; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR)) == NV_OK) + { + rmStatus = kvgpumgrDeleteRequestVgpu(pMdevUuid, vgpuId); + // UNLOCK: release API lock + rmapiLockRelease(); + } + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL nv_vgpu_process_vf_info( + nvidia_stack_t *sp, + nv_state_t *pNv, + NvU8 cmd, + NvU32 domain, + NvU8 bus, + NvU8 slot, + NvU8 function, + NvBool isMdevAttached, + void *vf_pci_info +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus = NV_OK; + void *fp = NULL; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR)) == NV_OK) + { + rmStatus = kvgpumgrProcessVfInfo(pNv->gpu_id, cmd, domain, bus, slot, function, isMdevAttached, (vgpu_vf_pci_info *) vf_pci_info); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL nv_vgpu_create_request( + nvidia_stack_t *sp, + nv_state_t *pNv, + const NvU8 *pMdevUuid, + NvU32 vgpuTypeId, + NvU16 *vgpuId, + NvU32 gpuPciBdf, + NvBool *is_driver_vm +) +{ + THREAD_STATE_NODE threadState; + OBJSYS *pSys = SYS_GET_INSTANCE(); + void *fp = NULL; + OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys); + NV_STATUS rmStatus = NV_OK; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR)) == NV_OK) + { + rmStatus = kvgpumgrCreateRequestVgpu(pNv->gpu_id, pMdevUuid, + vgpuTypeId, vgpuId, gpuPciBdf); + + *is_driver_vm = pHypervisor->getProperty(pHypervisor, PDB_PROP_HYPERVISOR_DRIVERVM_ENABLED); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL nv_vgpu_get_bar_info( + nvidia_stack_t *sp, + nv_state_t *pNv, + const NvU8 *pMdevUuid, + NvU64 *size, + NvU32 regionIndex, + void *pVgpuVfioRef +) +{ + REQUEST_VGPU_INFO_NODE *pRequestVgpu = NULL; + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus = NV_OK, status; + OBJGPU *pGpu = NULL; + KernelBus *pKernelBus; + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice; + void *fp = NULL; + NvU32 value = 0; + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr * pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_SILENT, rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR), exit); + + pGpu = NV_GET_NV_PRIV_PGPU(pNv); + if (pGpu == NULL) + { + NV_PRINTF(LEVEL_ERROR, "%s GPU handle is not valid \n", __FUNCTION__); + rmStatus = NV_ERR_INVALID_STATE; + goto release_lock; + } + pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + *size = kbusGetPciBarSize(pKernelBus, regionIndex); + + NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_SILENT, + kvgpumgrGetHostVgpuDeviceFromMdevUuid(pNv->gpu_id, + pMdevUuid, + &pKernelHostVgpuDevice), release_lock); + + pRequestVgpu = pKernelHostVgpuDevice->pRequestVgpuInfoNode; + if (pRequestVgpu == NULL) + { + rmStatus = NV_ERR_INVALID_POINTER; + goto release_lock; + } + + pKernelHostVgpuDevice->pVgpuVfioRef = pVgpuVfioRef; + + if (regionIndex == NV_VFIO_PCI_BAR1_REGION_INDEX) + { + VGPU_TYPE *vgpuTypeInfo; + NvU32 pgpuIndex = 0; + NvBool bOverrideBar1Size = NV_FALSE; + + // Read BAR1 length from vgpuTypeInfo + NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_SILENT, + kvgpumgrGetVgpuTypeInfo(pKernelHostVgpuDevice->vgpuType, &vgpuTypeInfo), release_lock); + + *size = vgpuTypeInfo->bar1Length << 20; + + NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_SILENT, + kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pNv->gpu_id, &pgpuIndex), release_lock); + + /* + * check for 'override_bar1_size' param in vgpuExtraParams list first, + * if param is missing there then check it in vgpu_params list + */ + status = nv_parse_config_params((const char*)vgpuTypeInfo->vgpuExtraParams, + "override_bar1_size", ';', &value); + + if (status == NV_OK && value) { + bOverrideBar1Size = NV_TRUE; + } else if (status == NV_ERR_OBJECT_NOT_FOUND) { + status = nv_parse_config_params(pRequestVgpu->configParams, + "override_bar1_size", ',', &value); + if (status == NV_OK && value) + bOverrideBar1Size = NV_TRUE; + } + if (bOverrideBar1Size) { + NvU64 bar1SizeInBytes, guestBar1; + NvU64 gpuBar1LowerLimit = 256 * 1024 * 1024; // bar1 lower limit for override_bar1_length parameter + + bar1SizeInBytes = kbusGetPciBarSize(pKernelBus, NV_VFIO_PCI_BAR1_REGION_INDEX); + if (pKernelVgpuMgr->pgpuInfo[pgpuIndex].sriovEnabled) + { + *size = pGpu->sriovState.vfBarSize[1]; + } + else if (bar1SizeInBytes > gpuBar1LowerLimit) + { + guestBar1 = bar1SizeInBytes / vgpuTypeInfo->maxInstance; + *size = nvPrevPow2_U64(guestBar1); + } + } + } + else if (regionIndex == NV_VFIO_PCI_BAR2_REGION_INDEX || + regionIndex == NV_VFIO_PCI_BAR3_REGION_INDEX) + { + status = nv_parse_config_params(pRequestVgpu->configParams, + "address64", ',', &value); + + if ((status != NV_OK) || ((status == NV_OK) && (value != 0))) + { + if (regionIndex == NV_VFIO_PCI_BAR2_REGION_INDEX) + *size = 0; + else if (regionIndex == NV_VFIO_PCI_BAR3_REGION_INDEX) + *size = kbusGetPciBarSize(pKernelBus, NV_VFIO_PCI_BAR2_REGION_INDEX); + } + } + +release_lock: + // UNLOCK: release API lock + rmapiLockRelease(); + +exit: + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS osVgpuVfioWake( + void *waitQueue +) +{ + vgpu_vfio_info vgpu_info; + + vgpu_info.waitQueue = waitQueue; + + return os_call_vgpu_vfio((void *) &vgpu_info, CMD_VGPU_VFIO_WAKE_WAIT_QUEUE); +} + +NV_STATUS NV_API_CALL nv_vgpu_start( + nvidia_stack_t *sp, + const NvU8 *pMdevUuid, + void *waitQueue, + NvS32 *returnStatus, + NvU8 *vmName, + NvU32 qemuPid +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus = NV_OK; + void *fp = NULL; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR)) == NV_OK) + { + rmStatus = kvgpumgrStart(pMdevUuid, waitQueue, returnStatus, + vmName, qemuPid); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +static NV_STATUS nv_parse_config_params( + const char *config_params, + const char *key, + const char delim, + NvU32 *config_value +) +{ + char *ptr, *configParams = rm_remove_spaces(config_params); + char *token, *value, *name; + NvU32 data; + NV_STATUS rmStatus = NV_ERR_OBJECT_NOT_FOUND; + + ptr = configParams; + while ((token = rm_string_token(&ptr, delim)) != NULL) + { + if (!(name = rm_string_token(&token, '=')) || !os_string_length(name)) + continue; + + if (!(value = rm_string_token(&token, '=')) || !os_string_length(value)) + continue; + + data = os_strtoul(value, NULL, 0); + + if (os_string_compare(name, key) == 0) + { + rmStatus = NV_OK; + *config_value = data; + } + } + + // Free the memory allocated by rm_remove_spaces() + os_free_mem(configParams); + + return rmStatus; +} + +NV_STATUS NV_API_CALL nv_vgpu_get_sparse_mmap( + nvidia_stack_t *sp , + nv_state_t *pNv, + const NvU8 *pMdevUuid, + NvU64 **offsets, + NvU64 **sizes, + NvU32 *numAreas +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus = NV_ERR_INVALID_STATE, status; + OBJGPU *pGpu = NULL; + POBJTMR pTmr = NULL; + KernelFifo *pKernelFifo = NULL; + void *fp = NULL; + REQUEST_VGPU_INFO_NODE *pRequestVgpu = NULL; + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice; + NvU32 bar0TmrMapSize = 0, bar0FifoMapSize = 0, value = 0; + NvU64 bar0TmrMapOffset = 0, bar0FifoMapOffset = 0; + NvU64 *vfRegionSizes = NULL; + NvU64 *vfRegionOffsets = NULL; + KernelBif *pKernelBif = NULL; + + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR)) == NV_OK) + { + pGpu = NV_GET_NV_PRIV_PGPU(pNv); + + if (pGpu == NULL) + { + rmStatus = NV_ERR_INVALID_STATE; + goto cleanup; + } + pTmr = GPU_GET_TIMER(pGpu); + pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + *numAreas = 0; + rmStatus = kvgpumgrGetHostVgpuDeviceFromMdevUuid(pNv->gpu_id, pMdevUuid, + &pKernelHostVgpuDevice); + if (rmStatus == NV_OK) + { + if (pKernelHostVgpuDevice->gfid != 0) + { + rmStatus = kbifGetNumVFSparseMmapRegions_HAL(pGpu, pKernelBif, pKernelHostVgpuDevice, numAreas); + if (rmStatus == NV_OK) + { + os_alloc_mem((void **)&vfRegionOffsets, sizeof(NvU64) * (*numAreas)); + os_alloc_mem((void **)&vfRegionSizes, sizeof (NvU64) * (*numAreas)); + if (vfRegionOffsets && vfRegionSizes) + { + rmStatus = kbifGetVFSparseMmapRegions_HAL(pGpu, pKernelBif, pKernelHostVgpuDevice, os_page_size, + vfRegionOffsets, vfRegionSizes); + if (rmStatus == NV_OK) + { + *offsets = vfRegionOffsets; + *sizes = vfRegionSizes; + } + } + else + { + if (vfRegionOffsets != NULL) + os_free_mem(vfRegionOffsets); + + if (vfRegionSizes != NULL) + os_free_mem(vfRegionSizes); + + rmStatus = NV_ERR_INSUFFICIENT_RESOURCES; + } + } + } + else + { + pRequestVgpu = pKernelHostVgpuDevice->pRequestVgpuInfoNode; + if (pRequestVgpu == NULL) + { + rmStatus = NV_ERR_INVALID_POINTER; + goto cleanup; + } + + status = nv_parse_config_params(pRequestVgpu->configParams, "direct_gpu_timer_access", ',', &value); + if ((status == NV_OK) && (value != 0)) + { + rmStatus = tmrGetTimerBar0MapInfo_HAL(pGpu, pTmr, + &bar0TmrMapOffset, + &bar0TmrMapSize); + if (rmStatus == NV_OK) + (*numAreas)++; + else + NV_PRINTF(LEVEL_ERROR, + "%s Failed to get NV_PTIMER region \n", + __FUNCTION__); + } + + value = 0; + { + status = kfifoGetUsermodeMapInfo_HAL(pGpu, pKernelFifo, + &bar0FifoMapOffset, + &bar0FifoMapSize); + if (status == NV_OK) + (*numAreas)++; + } + + if (*numAreas != 0) + { + NvU32 i = 0; + NvU64 *tmpOffset, *tmpSize; + os_alloc_mem((void **)offsets, sizeof(NvU64) * (*numAreas)); + os_alloc_mem((void **)sizes, sizeof (NvU64) * (*numAreas)); + + tmpOffset = *offsets; + tmpSize = *sizes; + + if (bar0TmrMapSize != 0) + { + tmpOffset[i] = bar0TmrMapOffset; + tmpSize[i] = bar0TmrMapSize; + i++; + } + + if (bar0FifoMapSize != 0) + { + tmpOffset[i] = bar0FifoMapOffset; + tmpSize[i] = bar0FifoMapSize; + } + } + } + } + +cleanup: + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL nv_vgpu_update_request( + nvidia_stack_t *sp , + const NvU8 *pMdevUuid, + VGPU_DEVICE_STATE deviceState, + NvU64 *offsets, + NvU64 *sizes, + const char *configParams +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus = NV_ERR_OBJECT_NOT_FOUND; + void *fp = NULL; + REQUEST_VGPU_INFO_NODE *pRequestVgpu = NULL; + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + if (offsets != NULL) + os_free_mem(offsets); + + if (sizes != NULL) + os_free_mem(sizes); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR)) == NV_OK) + { + for (pRequestVgpu = listHead(&pKernelVgpuMgr->listRequestVgpuHead); + pRequestVgpu != NULL; + pRequestVgpu = listNext(&pKernelVgpuMgr->listRequestVgpuHead, pRequestVgpu)) + { + if (portMemCmp(pRequestVgpu->mdevUuid, pMdevUuid, VGPU_UUID_SIZE) == 0) + { + + if (configParams != NULL) + portStringCopy(pRequestVgpu->configParams, + sizeof(pRequestVgpu->configParams), + configParams, (portStringLength(configParams) + 1)); + + pRequestVgpu->deviceState = deviceState; + rmStatus = NV_OK; + } + } + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS NV_API_CALL nv_gpu_bind_event( + nvidia_stack_t *sp +) +{ + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus = NV_OK; + void *fp = NULL; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + // LOCK: acquire API lock + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR)) == NV_OK) + { + CliAddSystemEvent(NV0000_NOTIFIERS_GPU_BIND_EVENT, 0); + + // UNLOCK: release API lock + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + +NV_STATUS osVgpuInjectInterrupt(void *vgpuVfioRef) +{ + vgpu_vfio_info vgpu_info; + + vgpu_info.vgpuVfioRef = vgpuVfioRef; + + return os_call_vgpu_vfio((void *) &vgpu_info, CMD_VGPU_VFIO_INJECT_INTERRUPT); +} + +NV_STATUS osVgpuRegisterMdev +( + OS_GPU_INFO *pOsGpuInfo +) +{ + NV_STATUS status = NV_OK; + vgpu_vfio_info vgpu_info; + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + KERNEL_PHYS_GPU_INFO *pPhysGpuInfo; + NvU32 pgpuIndex, i; + OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys); + + status = kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pOsGpuInfo->gpu_id, &pgpuIndex); + if (status != NV_OK) + return status; + + pPhysGpuInfo = &(pKernelVgpuMgr->pgpuInfo[pgpuIndex]); + + vgpu_info.numVgpuTypes = pKernelVgpuMgr->pgpuInfo[pgpuIndex].numVgpuTypes; + + status = os_alloc_mem((void **)&vgpu_info.vgpuTypeIds, + ((vgpu_info.numVgpuTypes) * sizeof(NvU32))); + if (status != NV_OK) + return status; + + vgpu_info.nv = pOsGpuInfo; + for (i = 0; i < pPhysGpuInfo->numVgpuTypes; i++) + { + vgpu_info.vgpuTypeIds[i] = pPhysGpuInfo->vgpuTypes[i]->vgpuTypeId; + } + + if ((!pPhysGpuInfo->sriovEnabled) || + (pHypervisor->getProperty(pHypervisor, PDB_PROP_HYPERVISOR_DRIVERVM_ENABLED))) + { + vgpu_info.is_virtfn = NV_FALSE; + status = os_call_vgpu_vfio((void *)&vgpu_info, CMD_VGPU_VFIO_REGISTER_MDEV); + } + else + { + for (i = 0; i < MAX_VF_COUNT_PER_GPU; i++) + { + if (pPhysGpuInfo->vfPciInfo[i].isNvidiaAttached) + { + vgpu_info.is_virtfn = NV_TRUE; + vgpu_info.domain = pPhysGpuInfo->vfPciInfo[i].domain; + vgpu_info.bus = pPhysGpuInfo->vfPciInfo[i].bus; + vgpu_info.slot = pPhysGpuInfo->vfPciInfo[i].slot; + vgpu_info.function = pPhysGpuInfo->vfPciInfo[i].function; + + status = os_call_vgpu_vfio((void *)&vgpu_info, CMD_VGPU_VFIO_REGISTER_MDEV); + if (status == NV_OK) + { + pPhysGpuInfo->vfPciInfo[i].isMdevAttached = NV_TRUE; + } + } + } + } + + os_free_mem(vgpu_info.vgpuTypeIds); + return status; +} + +NV_STATUS osIsVgpuVfioPresent(void) +{ + vgpu_vfio_info vgpu_info; + + return os_call_vgpu_vfio((void *) &vgpu_info, CMD_VGPU_VFIO_PRESENT); +} + +void initVGXSpecificRegistry(OBJGPU *pGpu) +{ + NvU32 data32; +#if !defined(NVCPU_X86_64) + osWriteRegistryDword(pGpu, NV_REG_STR_RM_BAR2_APERTURE_SIZE_MB, 4); +#endif + osWriteRegistryDword(pGpu, NV_REG_PROCESS_NONSTALL_INTR_IN_LOCKLESS_ISR, + NV_REG_PROCESS_NONSTALL_INTR_IN_LOCKLESS_ISR_ENABLE); + if ((osReadRegistryDword(pGpu, NV_REG_STR_RM_DUMP_NVLOG, &data32) != NV_OK)) + { + osWriteRegistryDword(pGpu, NV_REG_STR_RM_DUMP_NVLOG, + NV_REG_STR_RM_DUMP_NVLOG_ENABLE); + } + osWriteRegistryDword(pGpu, NV_REG_STR_RM_RC_WATCHDOG, + NV_REG_STR_RM_RC_WATCHDOG_DISABLE); + osWriteRegistryDword(pGpu, NV_REG_STR_CL_FORCE_P2P, + DRF_DEF(_REG_STR, _CL_FORCE_P2P, _READ, _DISABLE) | + DRF_DEF(_REG_STR, _CL_FORCE_P2P, _WRITE, _DISABLE)); +} + + +NV_STATUS rm_is_vgpu_supported_device( + OS_GPU_INFO *pOsGpuInfo, + NvU32 pmc_boot_1 +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + POBJHYPERVISOR pHypervisor = SYS_GET_HYPERVISOR(pSys); + NvBool is_sriov_enabled = FLD_TEST_DRF(_PMC, _BOOT_1, _VGPU, _VF, pmc_boot_1); + + // if not running in vGPU mode (guest VM) return NV_OK + if (!(pHypervisor && pHypervisor->bIsHVMGuest && + (FLD_TEST_DRF(_PMC, _BOOT_1, _VGPU, _PV, pmc_boot_1) || + is_sriov_enabled))) + { + return NV_OK; + } + + return NV_OK; +} diff --git a/src/nvidia/arch/nvalloc/unix/src/os.c b/src/nvidia/arch/nvalloc/unix/src/os.c index eae8c433c..53f46d1b3 100644 --- a/src/nvidia/arch/nvalloc/unix/src/os.c +++ b/src/nvidia/arch/nvalloc/unix/src/os.c @@ -59,6 +59,12 @@ #include "mem_mgr/mem.h" #include "gpu/mem_mgr/virt_mem_allocator_common.h" +#include +#include +#include "gps.h" +#include "jt.h" + + extern const char *ppOsBugCheckBugcodeStr[]; @@ -716,6 +722,7 @@ NvU32 osReleaseRmSema(void *pSema, OBJGPU *pDpcGpu) void osSpinLoop(void) { + // Enable this code to get debug prints from Libos. } NvU64 osGetMaxUserVa(void) @@ -931,6 +938,11 @@ NV_STATUS osAllocPagesInternal( nv->force_dma32_alloc = NV_FALSE; } + if (status != NV_OK) + { + return status; + } + // // If the OS layer doesn't think in RM page size, we need to inflate the // PTE array into RM pages. @@ -1597,6 +1609,7 @@ void osDevWriteReg032( { NvBool vgpuHandled = NV_FALSE; + vgpuDevWriteReg032(pGpu, thisAddress, thisValue, &vgpuHandled); if (vgpuHandled) { return; @@ -1656,6 +1669,7 @@ NvU32 osDevReadReg032( NvU32 retval = 0; NvBool vgpuHandled = NV_FALSE; + retval = vgpuDevReadReg032(pGpu, thisAddress, &vgpuHandled); if (vgpuHandled) { return retval; @@ -1782,6 +1796,16 @@ void osGetTimeoutParams(OBJGPU *pGpu, NvU32 *pTimeoutUs, NvU32 *pScale, NvU32 *p NV_ASSERT((NV_GPU_MODE_GRAPHICS_MODE == gpuMode) || (NV_GPU_MODE_COMPUTE_MODE == gpuMode)); + if (hypervisorIsVgxHyper()) + { + // + // 1.8 seconds is chosen because it is 90% of the overall hard limit of 2.0 + // seconds, imposed by WDDM driver rules. + // Currently primary use case of VGX is Windows, so setting 1.8 as default + // + *pTimeoutUs = 1.8 * 1000000; + } + else { switch (gpuMode) { @@ -1803,7 +1827,6 @@ void osGetTimeoutParams(OBJGPU *pGpu, NvU32 *pTimeoutUs, NvU32 *pScale, NvU32 *p { *pScale = 60; // 1s -> 1m } - return; } @@ -1940,22 +1963,28 @@ _initializeExportObjectFd NV_STATUS status; RsResourceRef *pResourceRef; Device *pDevice; + NvU32 deviceInstance = NV_MAX_DEVICES; if (nvfp->handles != NULL) { return NV_ERR_STATE_IN_USE; } - status = serverutilGetResourceRef(hClient, hDevice, &pResourceRef); - if (status != NV_OK) + if (hDevice != 0) { - return status; - } + status = serverutilGetResourceRef(hClient, hDevice, &pResourceRef); + if (status != NV_OK) + { + return status; + } - pDevice = dynamicCast(pResourceRef->pResource, Device); - if (pDevice == NULL) - { - return NV_ERR_INVALID_PARAMETER; + pDevice = dynamicCast(pResourceRef->pResource, Device); + if (pDevice == NULL) + { + return NV_ERR_INVALID_PARAMETER; + } + + deviceInstance = pDevice->deviceInst; } NV_ASSERT_OK_OR_RETURN(os_alloc_mem((void **)&nvfp->handles, @@ -1965,7 +1994,7 @@ _initializeExportObjectFd sizeof(nvfp->handles[0]) * maxObjects); nvfp->maxHandles = maxObjects; - nvfp->deviceInstance = pDevice->deviceInst; + nvfp->deviceInstance = deviceInstance; if (metadata != NULL) { @@ -2431,7 +2460,115 @@ NV_STATUS osCallACPI_DSM NvU16 *pSize ) { - return NV_ERR_NOT_SUPPORTED; + NV_STATUS status; + NvU8 *pAcpiDsmGuid = NULL; + NvU32 acpiDsmRev; + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NvU16 acpiDsmInArgSize = 4; + NvBool acpiNvpcfDsmFunction = NV_FALSE; + + // do any handling/remapping of guid needed. + status = checkDsmCall(pGpu, + (ACPI_DSM_FUNCTION *) &acpiDsmFunction, + &acpiDsmSubFunction, + pInOut, + pSize); + + // return if subfunction is not supported or we're returning cache data + if (status != NV_WARN_MORE_PROCESSING_REQUIRED) + { + return status; + } + + switch ((NvU32) acpiDsmFunction) + { + case ACPI_DSM_FUNCTION_NBSI: + pAcpiDsmGuid = (NvU8 *) &NBSI_DSM_GUID; + acpiDsmRev = NBSI_REVISION_ID; + break; + case ACPI_DSM_FUNCTION_NVHG: + pAcpiDsmGuid = (NvU8 *) &NVHG_DSM_GUID; + acpiDsmRev = NVHG_REVISION_ID; + break; + case ACPI_DSM_FUNCTION_MXM: + pAcpiDsmGuid = (NvU8 *) &DSM_MXM_GUID; + acpiDsmRev = ACPI_MXM_REVISION_ID; + break; + case ACPI_DSM_FUNCTION_NBCI: + pAcpiDsmGuid = (NvU8 *) &NBCI_DSM_GUID; + acpiDsmRev = NBCI_REVISION_ID; + break; + case ACPI_DSM_FUNCTION_NVOP: + pAcpiDsmGuid = (NvU8 *) &NVOP_DSM_GUID; + acpiDsmRev = NVOP_REVISION_ID; + break; + case ACPI_DSM_FUNCTION_PCFG: + pAcpiDsmGuid = (NvU8 *) &PCFG_DSM_GUID; + acpiDsmRev = PCFG_REVISION_ID; + break; + case ACPI_DSM_FUNCTION_PEX: + pAcpiDsmGuid = (NvU8 *) &PEX_DSM_GUID; + acpiDsmRev = PEX_REVISION_ID; + if (acpiDsmSubFunction == PEX_FUNC_SETLTRLATENCY) + { + acpiDsmInArgSize = (3 + *pSize); + } + break; + case (ACPI_DSM_FUNCTION_JT): + pAcpiDsmGuid = (NvU8 *) &JT_DSM_GUID; + acpiDsmRev = JT_REVISION_ID; + break; + case ACPI_DSM_FUNCTION_NVPCF: + { + pAcpiDsmGuid = (NvU8 *)&NVPCF_ACPI_DSM_GUID; + acpiDsmRev = NVPCF_ACPI_DSM_REVISION_ID; + acpiDsmInArgSize = (*pSize); + acpiNvpcfDsmFunction = NV_TRUE; + break; + } + case ACPI_DSM_FUNCTION_NVPCF_2X: + pAcpiDsmGuid = (NvU8 *)&NVPCF_ACPI_DSM_GUID; + acpiDsmRev = NVPCF_2X_ACPI_DSM_REVISION_ID; + acpiDsmInArgSize = (*pSize); + if (!nv->nvpcf_dsm_in_gpu_scope) + { + acpiNvpcfDsmFunction = NV_TRUE; + } + break; + + default: + return NV_ERR_NOT_SUPPORTED; + break; + } + + status = nv_acpi_dsm_method(nv, + pAcpiDsmGuid, + acpiDsmRev, + acpiNvpcfDsmFunction, + acpiDsmSubFunction, + pInOut, + acpiDsmInArgSize, + NULL, + pInOut, + pSize); + + if (status == NV_OK) + { + if (acpiDsmSubFunction == NV_ACPI_ALL_FUNC_SUPPORT) + { + // if handling get supported functions list... cache it for later calls + cacheDsmSupportedFunction(pGpu, acpiDsmFunction, acpiDsmSubFunction, pInOut, *pSize); + } + } + else if (nvp->b_mobile_config_enabled) + { + NV_PRINTF(LEVEL_ERROR, + "osCallACPI_DSM: Error during 0x%x DSM subfunction 0x%x! status=0x%x\n", + acpiDsmFunction, acpiDsmSubFunction, status); + } + + return status; } NV_STATUS osCallACPI_DOD @@ -4744,6 +4881,35 @@ osTegraSocGetImpImportData return NV_ERR_NOT_SUPPORTED; } +/*! + * @brief Tells BPMP whether or not RFL is valid + * + * Display HW generates an ok_to_switch signal which asserts when mempool + * occupancy is high enough to be able to turn off memory long enough to + * execute a dramclk frequency switch without underflowing display output. + * ok_to_switch drives the RFL ("request for latency") signal in the memory + * unit, and the switch sequencer waits for this signal to go active before + * starting a dramclk switch. However, if the signal is not valid (e.g., if + * display HW or SW has not been initialized yet), the switch sequencer ignores + * the signal. This API tells BPMP whether or not the signal is valid. + * + * @param[in] pOsGpuInfo Per GPU Linux state + * @param[in] bEnable True if RFL will be valid; false if invalid + * + * @returns NV_OK if successful, + * NV_ERR_NOT_SUPPORTED if the functionality is not available, or + * NV_ERR_GENERIC if some other kind of error occurred. + */ +NV_STATUS +osTegraSocEnableDisableRfl +( + OS_GPU_INFO *pOsGpuInfo, + NvBool bEnable +) +{ + return NV_ERR_NOT_SUPPORTED; +} + /*! * @brief Allocates a specified amount of ISO memory bandwidth for display * @@ -4793,7 +4959,8 @@ osCreateNanoTimer void **pTimer ) { - return NV_ERR_NOT_SUPPORTED; + nv_create_nano_timer(pOsGpuInfo, pTmrEvent, (nv_nano_timer_t **)pTimer); + return NV_OK; } /*! @@ -4811,7 +4978,8 @@ osStartNanoTimer NvU64 timeNs ) { - return NV_ERR_NOT_SUPPORTED; + nv_start_nano_timer(pOsGpuInfo, (nv_nano_timer_t *)pTimer, timeNs); + return NV_OK; } /*! @@ -4827,8 +4995,8 @@ osCancelNanoTimer void *pTimer ) { - return NV_ERR_NOT_SUPPORTED; - + nv_cancel_nano_timer(pOsGpuInfo, (nv_nano_timer_t *)pTimer); + return NV_OK; } /*! @@ -4845,7 +5013,8 @@ osDestroyNanoTimer void *pTimer ) { - return NV_ERR_NOT_SUPPORTED; + nv_destroy_nano_timer(pOsGpuInfo, (nv_nano_timer_t *)pTimer); + return NV_OK; } /*! @@ -5016,6 +5185,52 @@ osIsGpuAccessible return nv_is_gpu_accessible(NV_GET_NV_STATE(pGpu)); } +/*! + * @brief Check whether GPU has received a shutdown notification from the OS + */ +NvBool +osIsGpuShutdown +( + OBJGPU *pGpu +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + return nv ? nv->is_shutdown : NV_TRUE; +} + +/*! + * @brief Check GPU OS info matches + * + * @param[in] pGpu GPU object pointer + * + * @returns NVBool, Returns TRUE if matched. + */ +NvBool +osMatchGpuOsInfo +( + OBJGPU *pGpu, + void *pOsInfo +) +{ + return nv_match_gpu_os_info(NV_GET_NV_STATE(pGpu), pOsInfo); +} + +/*! + * @brief Release GPU OS info. + * + * @param[in] pOsInfo GPU OS info pointer + * + * @returns void + */ +void +osReleaseGpuOsInfo +( + void *pOsInfo +) +{ + nv_put_file_private(pOsInfo); +} + NvBool osDmabufIsSupported(void) { diff --git a/src/nvidia/arch/nvalloc/unix/src/osapi.c b/src/nvidia/arch/nvalloc/unix/src/osapi.c index e841c8436..9c90478d7 100644 --- a/src/nvidia/arch/nvalloc/unix/src/osapi.c +++ b/src/nvidia/arch/nvalloc/unix/src/osapi.c @@ -105,7 +105,7 @@ RM_API *RmUnixRmApiPrologue(nv_state_t *pNv, THREAD_STATE_NODE *pThreadNode, NvU { threadStateInit(pThreadNode, THREAD_STATE_FLAGS_NONE); - if ((rmApiLockAcquire(API_LOCK_FLAGS_NONE, module)) == NV_OK) + if ((rmapiLockAcquire(API_LOCK_FLAGS_NONE, module)) == NV_OK) { if ((pNv->rmapi.hClient != 0) && (os_ref_dynamic_power(pNv, NV_DYNAMIC_PM_FINE) == NV_OK)) @@ -113,7 +113,7 @@ RM_API *RmUnixRmApiPrologue(nv_state_t *pNv, THREAD_STATE_NODE *pThreadNode, NvU return rmapiGetInterface(RMAPI_API_LOCK_INTERNAL); } - rmApiLockRelease(); + rmapiLockRelease(); } threadStateFree(pThreadNode, THREAD_STATE_FLAGS_NONE); @@ -132,7 +132,7 @@ RM_API *RmUnixRmApiPrologue(nv_state_t *pNv, THREAD_STATE_NODE *pThreadNode, NvU void RmUnixRmApiEpilogue(nv_state_t *pNv, THREAD_STATE_NODE *pThreadNode) { os_unref_dynamic_power(pNv, NV_DYNAMIC_PM_FINE); - rmApiLockRelease(); + rmapiLockRelease(); threadStateFree(pThreadNode, THREAD_STATE_FLAGS_NONE); } @@ -209,9 +209,9 @@ const NvU8 * RmGetGpuUuidRaw( gidFlags = DRF_DEF(2080_GPU_CMD,_GPU_GET_GID_FLAGS,_TYPE,_SHA1) | DRF_DEF(2080_GPU_CMD,_GPU_GET_GID_FLAGS,_FORMAT,_BINARY); - if (!rmApiLockIsOwner()) + if (!rmapiLockIsOwner()) { - rmStatus = rmApiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_GPU); + rmStatus = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_GPU); if (rmStatus != NV_OK) { return NULL; @@ -224,7 +224,7 @@ const NvU8 * RmGetGpuUuidRaw( { if (isApiLockTaken == NV_TRUE) { - rmApiLockRelease(); + rmapiLockRelease(); } return NULL; @@ -233,7 +233,7 @@ const NvU8 * RmGetGpuUuidRaw( rmStatus = gpuGetGidInfo(pGpu, NULL, NULL, gidFlags); if (isApiLockTaken == NV_TRUE) { - rmApiLockRelease(); + rmapiLockRelease(); } if (rmStatus != NV_OK) @@ -780,10 +780,8 @@ static NV_STATUS RmAccessRegistry( RmStatus = NV_ERR_INVALID_STRING_LENGTH; goto done; } - // get access to client's parmStr RMAPI_PARAM_COPY_INIT(parmStrParamCopy, tmpParmStr, clientParmStrAddress, ParmStrLength, 1); - parmStrParamCopy.flags |= RMAPI_PARAM_COPY_FLAGS_ZERO_BUFFER; RmStatus = rmapiParamsAcquire(&parmStrParamCopy, NV_TRUE); if (RmStatus != NV_OK) { @@ -1100,66 +1098,55 @@ static NV_STATUS RmPerformVersionCheck( return NV_ERR_GENERIC; } -NV_STATUS RmSystemEvent( +// +// Check if the NVPCF _DSM functions are implemented under +// NVPCF scope or GPU device scope. +// As part of RM initialisation this function checks the +// support of NVPCF _DSM function implementation under +// NVPCF scope, in case that fails, clear the cached DSM +// support status and retry the NVPCF _DSM function under +// GPU scope. +// +static void RmCheckNvpcfDsmScope( + OBJGPU *pGpu +) +{ + NvU32 supportedFuncs; + NvU16 dsmDataSize = sizeof(supportedFuncs); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + ACPI_DSM_FUNCTION acpiDsmFunction = ACPI_DSM_FUNCTION_NVPCF_2X; + NvU32 acpiDsmSubFunction = NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED; + + nv->nvpcf_dsm_in_gpu_scope = NV_FALSE; + + if ((osCallACPI_DSM(pGpu, acpiDsmFunction, acpiDsmSubFunction, + &supportedFuncs, &dsmDataSize) != NV_OK) || + (FLD_TEST_DRF(PCF0100, _CTRL_CONFIG_DSM, + _FUNC_GET_SUPPORTED_IS_SUPPORTED, _NO, supportedFuncs)) || + (dsmDataSize != sizeof(supportedFuncs))) + { + nv->nvpcf_dsm_in_gpu_scope = NV_TRUE; + + // clear cached DSM function status + uncacheDsmFuncStatus(pGpu, acpiDsmFunction, acpiDsmSubFunction); + } +} + +NV_STATUS RmPowerSourceChangeEvent( nv_state_t *pNv, - NvU32 event_type, NvU32 event_val ) { - NV_STATUS rmStatus = NV_OK; - NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS params; + NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS params = {0}; RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); - switch (event_type) - { - case NV_SYSTEM_ACPI_BATTERY_POWER_EVENT: - { - Nv2080PowerEventNotification powerParams; - portMemSet(&powerParams, 0, sizeof(powerParams)); - powerParams.bSwitchToAC = NV_TRUE; - powerParams.bGPUCapabilityChanged = NV_FALSE; - powerParams.displayMaskAffected = 0; + params.powerStateInfo.powerState = event_val ? NV2080_CTRL_PERF_POWER_SOURCE_BATTERY : + NV2080_CTRL_PERF_POWER_SOURCE_AC; - params.eventType = NV0000_CTRL_SYSTEM_EVENT_TYPE_POWER_SOURCE; - if (event_val == NV_SYSTEM_ACPI_EVENT_VALUE_POWER_EVENT_BATTERY) - { - params.eventData = NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_BATTERY; - powerParams.bSwitchToAC = NV_FALSE; - } - else if (event_val == NV_SYSTEM_ACPI_EVENT_VALUE_POWER_EVENT_AC) - { - params.eventData = NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_AC; - powerParams.bSwitchToAC = NV_TRUE; - } - else - { - rmStatus = NV_ERR_INVALID_ARGUMENT; - } - if (rmStatus == NV_OK) - { - OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv); - - rmStatus = pRmApi->Control(pRmApi, - pNv->rmapi.hClient, - pNv->rmapi.hClient, - NV0000_CTRL_CMD_SYSTEM_NOTIFY_EVENT, - (void *)¶ms, - sizeof(NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS)); - - // - // TODO: bug 2812848 Investigate if we can use system event - // or if we can broadcast NV2080_NOTIFIERS_POWER_EVENT for all GPUs - // - gpuNotifySubDeviceEvent(pGpu, NV2080_NOTIFIERS_POWER_EVENT, - &powerParams, sizeof(powerParams), 0, 0); - } - break; - } - default: - rmStatus = NV_ERR_INVALID_ARGUMENT; - } - - return rmStatus; + return pRmApi->Control(pRmApi, pNv->rmapi.hClient, + pNv->rmapi.hSubDevice, + NV2080_CTRL_CMD_PERF_SET_POWERSTATE, + ¶ms, sizeof(params)); } /*! @@ -1175,6 +1162,51 @@ static void RmHandleDNotifierEvent( NvU32 event_type ) { + NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS params = { 0 }; + RM_API *pRmApi; + THREAD_STATE_NODE threadState; + NV_STATUS rmStatus = NV_OK; + + switch (event_type) + { + case ACPI_NOTIFY_POWER_LEVEL_D1: + params.powerState = NV2080_CTRL_PERF_AUX_POWER_STATE_P0; + break; + case ACPI_NOTIFY_POWER_LEVEL_D2: + params.powerState = NV2080_CTRL_PERF_AUX_POWER_STATE_P1; + break; + case ACPI_NOTIFY_POWER_LEVEL_D3: + params.powerState = NV2080_CTRL_PERF_AUX_POWER_STATE_P2; + break; + case ACPI_NOTIFY_POWER_LEVEL_D4: + params.powerState = NV2080_CTRL_PERF_AUX_POWER_STATE_P3; + break; + case ACPI_NOTIFY_POWER_LEVEL_D5: + params.powerState = NV2080_CTRL_PERF_AUX_POWER_STATE_P4; + break; + default: + return; + } + + pRmApi = RmUnixRmApiPrologue(pNv, &threadState, RM_LOCK_MODULES_ACPI); + if (pRmApi == NULL) + { + return; + } + + rmStatus = pRmApi->Control(pRmApi, pNv->rmapi.hClient, + pNv->rmapi.hSubDevice, + NV2080_CTRL_CMD_PERF_SET_AUX_POWER_STATE, + ¶ms, sizeof(params)); + + RmUnixRmApiEpilogue(pNv, &threadState); + + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "%s: Failed to handle ACPI D-Notifier event, status=0x%x\n", + __FUNCTION__, rmStatus); + } } static NV_STATUS @@ -1372,7 +1404,7 @@ NvBool NV_API_CALL rm_init_adapter( threadStateInit(&threadState, THREAD_STATE_FLAGS_DEVICE_INIT); // LOCK: acquire API lock - if (rmApiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_INIT) == NV_OK) + if (rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_INIT) == NV_OK) { if (!((gpumgrQueryGpuDrainState(pNv->gpu_id, &bEnabled, NULL) == NV_OK) && bEnabled)) @@ -1388,7 +1420,7 @@ NvBool NV_API_CALL rm_init_adapter( } // UNLOCK: release API lock - rmApiLockRelease(); + rmapiLockRelease(); } threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); @@ -1411,7 +1443,7 @@ void NV_API_CALL rm_disable_adapter( NV_ASSERT_OK(os_flush_work_queue(pNv->queue)); // LOCK: acquire API lock - if (rmApiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DESTROY) == NV_OK) + if (rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DESTROY) == NV_OK) { if (pNv->flags & NV_FLAG_PERSISTENT_SW_STATE) { @@ -1423,7 +1455,7 @@ void NV_API_CALL rm_disable_adapter( } // UNLOCK: release API lock - rmApiLockRelease(); + rmapiLockRelease(); } NV_ASSERT_OK(os_flush_work_queue(pNv->queue)); @@ -1443,12 +1475,12 @@ void NV_API_CALL rm_shutdown_adapter( threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); // LOCK: acquire API lock - if (rmApiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DESTROY) == NV_OK) + if (rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DESTROY) == NV_OK) { RmShutdownAdapter(pNv); // UNLOCK: release API lock - rmApiLockRelease(); + rmapiLockRelease(); } threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); @@ -1487,7 +1519,7 @@ NV_STATUS NV_API_CALL rm_acquire_api_lock( threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); // LOCK: acquire API lock - rmStatus = rmApiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI); + rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI); threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); NV_EXIT_RM_RUNTIME(sp,fp); @@ -1506,7 +1538,7 @@ NV_STATUS NV_API_CALL rm_release_api_lock( threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); // UNLOCK: release API lock - rmApiLockRelease(); + rmapiLockRelease(); threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); NV_EXIT_RM_RUNTIME(sp,fp); @@ -1972,7 +2004,6 @@ done: // TODO: Bug 1802250: [uvm8] Use an alt stack in all functions in unix/src/osapi.c NV_STATUS rm_create_mmap_context( - nv_state_t *pNv, NvHandle hClient, NvHandle hDevice, NvHandle hMemory, @@ -1985,7 +2016,7 @@ NV_STATUS rm_create_mmap_context( { NV_STATUS rmStatus = NV_OK; // LOCK: acquire API lock - if ((rmStatus = rmApiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_OSAPI)) == NV_OK) + if ((rmStatus = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_OSAPI)) == NV_OK) { RmClient *pClient; @@ -2008,7 +2039,7 @@ NV_STATUS rm_create_mmap_context( serverutilReleaseClient(LOCK_ACCESS_READ, pClient); // UNLOCK: release API lock - rmApiLockRelease(); + rmapiLockRelease(); } return rmStatus; @@ -2029,6 +2060,7 @@ static NV_STATUS RmGetAllocPrivate( PMEMORY_DESCRIPTOR pMemDesc; NvU32 pageOffset; NvU64 pageCount; + NvU64 endingOffset; RsResourceRef *pResourceRef; RmResource *pRmResource; void *pMemData; @@ -2040,7 +2072,7 @@ static NV_STATUS RmGetAllocPrivate( pageOffset = (offset & ~os_page_mask); offset &= os_page_mask; - NV_ASSERT_OR_RETURN(rmApiLockIsOwner(), NV_ERR_INVALID_LOCK_STATE); + NV_ASSERT_OR_RETURN(rmapiLockIsOwner(), NV_ERR_INVALID_LOCK_STATE); if (NV_OK != serverutilAcquireClient(hClient, LOCK_ACCESS_READ, &pClient)) return NV_ERR_INVALID_CLIENT; @@ -2089,8 +2121,9 @@ static NV_STATUS RmGetAllocPrivate( if (rmStatus != NV_OK) goto done; - pageCount = ((pageOffset + length) / os_page_size); - pageCount += (*pPageIndex + (((pageOffset + length) % os_page_size) ? 1 : 0)); + endingOffset = pageOffset + length; + pageCount = (endingOffset / os_page_size); + pageCount += (*pPageIndex + ((endingOffset % os_page_size) ? 1 : 0)); if (pageCount > NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount)) { @@ -2150,12 +2183,12 @@ NV_STATUS rm_get_adapter_status( NV_STATUS rmStatus = NV_ERR_OPERATING_SYSTEM; // LOCK: acquire API lock - if (rmApiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_OSAPI) == NV_OK) + if (rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_OSAPI) == NV_OK) { rmStatus = RmGetAdapterStatus(pNv, pStatus); // UNLOCK: release API lock - rmApiLockRelease(); + rmapiLockRelease(); } return rmStatus; @@ -2419,7 +2452,7 @@ void NV_API_CALL rm_cleanup_file_private( return; // LOCK: acquire API lock - if (rmApiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI) == NV_OK) + if (rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI) == NV_OK) { // Unref any object which was exported on this file. if (nvfp->handles != NULL) @@ -2444,7 +2477,7 @@ void NV_API_CALL rm_cleanup_file_private( RmFreeUnusedClients(pNv, nvfp); // UNLOCK: release API lock - rmApiLockRelease(); + rmapiLockRelease(); } rmapiEpilogue(pRmApi, &rmApiContext); @@ -2472,12 +2505,12 @@ void NV_API_CALL rm_unbind_lock( threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); // LOCK: acquire API lock - if (rmApiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI) == NV_OK) + if (rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI) == NV_OK) { RmUnbindLock(pNv); // UNLOCK: release API lock - rmApiLockRelease(); + rmapiLockRelease(); } threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); @@ -2493,12 +2526,12 @@ NV_STATUS rm_alloc_os_event( NV_STATUS RmStatus; // LOCK: acquire API lock - if ((RmStatus = rmApiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_EVENT)) == NV_OK) + if ((RmStatus = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_EVENT)) == NV_OK) { RmStatus = RmAllocOsEvent(hClient, nvfp, fd); // UNLOCK: release API lock - rmApiLockRelease(); + rmapiLockRelease(); } return RmStatus; @@ -2512,12 +2545,12 @@ NV_STATUS rm_free_os_event( NV_STATUS RmStatus; // LOCK: acquire API lock - if ((RmStatus = rmApiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_EVENT)) == NV_OK) + if ((RmStatus = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_EVENT)) == NV_OK) { RmStatus = RmFreeOsEvent(hClient, fd); // UNLOCK: release API lock - rmApiLockRelease(); + rmapiLockRelease(); } return RmStatus; @@ -2532,12 +2565,12 @@ NV_STATUS rm_get_event_data( NV_STATUS RmStatus; // LOCK: acquire API lock - if ((RmStatus = rmApiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_EVENT)) == NV_OK) + if ((RmStatus = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_EVENT)) == NV_OK) { RmStatus = RmGetEventData(nvfp, pEvent, MoreEvents, NV_TRUE); // UNLOCK: release API lock - rmApiLockRelease(); + rmapiLockRelease(); } return RmStatus; @@ -2569,7 +2602,7 @@ NV_STATUS NV_API_CALL rm_read_registry_dword( if (nv != NULL) { // LOCK: acquire API lock - if ((RmStatus = rmApiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_OSAPI)) != NV_OK) + if ((RmStatus = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_OSAPI)) != NV_OK) { NV_EXIT_RM_RUNTIME(sp,fp); return RmStatus; @@ -2586,7 +2619,7 @@ NV_STATUS NV_API_CALL rm_read_registry_dword( if (isApiLockTaken == NV_TRUE) { // UNLOCK: release API lock - rmApiLockRelease(); + rmapiLockRelease(); } NV_EXIT_RM_RUNTIME(sp,fp); @@ -2610,7 +2643,7 @@ NV_STATUS NV_API_CALL rm_write_registry_dword( if (nv != NULL) { // LOCK: acquire API lock - if ((RmStatus = rmApiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI)) != NV_OK) + if ((RmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI)) != NV_OK) { NV_EXIT_RM_RUNTIME(sp,fp); return RmStatus; @@ -2624,7 +2657,7 @@ NV_STATUS NV_API_CALL rm_write_registry_dword( if (isApiLockTaken == NV_TRUE) { // UNLOCK: release API lock - rmApiLockRelease(); + rmapiLockRelease(); } NV_EXIT_RM_RUNTIME(sp,fp); @@ -2649,7 +2682,7 @@ NV_STATUS NV_API_CALL rm_write_registry_binary( if (nv != NULL) { // LOCK: acquire API lock - if ((RmStatus = rmApiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI)) != NV_OK) + if ((RmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI)) != NV_OK) { NV_EXIT_RM_RUNTIME(sp,fp); return RmStatus; @@ -2663,7 +2696,7 @@ NV_STATUS NV_API_CALL rm_write_registry_binary( if (isApiLockTaken == NV_TRUE) { // UNLOCK: release API lock - rmApiLockRelease(); + rmapiLockRelease(); } NV_EXIT_RM_RUNTIME(sp,fp); @@ -2688,7 +2721,7 @@ NV_STATUS NV_API_CALL rm_write_registry_string( if (nv != NULL) { // LOCK: acquire API lock - if ((rmStatus = rmApiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI)) != NV_OK) + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI)) != NV_OK) { NV_EXIT_RM_RUNTIME(sp,fp); return rmStatus; @@ -2702,7 +2735,7 @@ NV_STATUS NV_API_CALL rm_write_registry_string( if (isApiLockTaken == NV_TRUE) { // UNLOCK: release API lock - rmApiLockRelease(); + rmapiLockRelease(); } NV_EXIT_RM_RUNTIME(sp,fp); @@ -2864,12 +2897,13 @@ static NV_STATUS RmRunNanoTimerCallback( OBJSYS *pSys = SYS_GET_INSTANCE(); POBJTMR pTmr = GPU_GET_TIMER(pGpu); THREAD_STATE_NODE threadState; - NV_STATUS status = NV_OK; - + NV_STATUS status = NV_OK; // LOCK: try to acquire GPUs lock - if ((status = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_COND_ACQUIRE, RM_LOCK_MODULES_TMR)) != NV_OK) + if ((status = rmGpuLocksAcquire(GPU_LOCK_FLAGS_COND_ACQUIRE, RM_LOCK_MODULES_TMR)) != NV_OK) { - return status; + PTMR_EVENT_PVT pEvent = (PTMR_EVENT_PVT) pTmrEvent; + // We failed to acquire the lock; schedule a timer to try again. + return osStartNanoTimer(pGpu->pOsGpuInfo, pEvent->super.pOSTmrCBdata, 1000); } if ((status = osCondAcquireRmSema(pSys->pSema)) != NV_OK) @@ -3003,7 +3037,7 @@ NV_STATUS rm_access_registry( (AccessType == NVOS38_ACCESS_TYPE_READ_BINARY); // LOCK: acquire API lock - if ((RmStatus = rmApiLockAcquire(bReadOnly ? RMAPI_LOCK_FLAGS_READ : RMAPI_LOCK_FLAGS_NONE, + if ((RmStatus = rmapiLockAcquire(bReadOnly ? RMAPI_LOCK_FLAGS_READ : RMAPI_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI)) == NV_OK) { RmStatus = RmAccessRegistry(hClient, @@ -3019,7 +3053,7 @@ NV_STATUS rm_access_registry( Entry); // UNLOCK: release API lock - rmApiLockRelease(); + rmapiLockRelease(); } return RmStatus; @@ -3036,7 +3070,7 @@ NV_STATUS rm_update_device_mapping_info( NV_STATUS RmStatus; // LOCK: acquire API lock - if ((RmStatus = rmApiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_GPU)) == NV_OK) + if ((RmStatus = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_GPU)) == NV_OK) { RmStatus = RmUpdateDeviceMappingInfo(hClient, hDevice, @@ -3045,7 +3079,7 @@ NV_STATUS rm_update_device_mapping_info( pNewCpuAddress); // UNLOCK: release API lock - rmApiLockRelease(); + rmapiLockRelease(); } return RmStatus; @@ -3060,7 +3094,6 @@ static void rm_is_device_rm_firmware_capable( { NvBool bIsFirmwareCapable = NV_FALSE; NvBool bEnableByDefault = NV_FALSE; - NvU16 pciDeviceId = pNv->pci_info.device_id; if (NV_IS_SOC_DISPLAY_DEVICE(pNv)) { @@ -3068,7 +3101,7 @@ static void rm_is_device_rm_firmware_capable( } else { - bIsFirmwareCapable = gpumgrIsDeviceRmFirmwareCapable(pciDeviceId, + bIsFirmwareCapable = gpumgrIsDeviceRmFirmwareCapable(pNv->pci_info.device_id, pmcBoot42, &bEnableByDefault); } @@ -3135,6 +3168,7 @@ NV_STATUS NV_API_CALL rm_is_supported_device( rmStatus = NV_ERR_OPERATING_SYSTEM; goto threadfree; } + NvU32 pmc_boot_1 = NV_PRIV_REG_RD32(reg_mapping, NV_PMC_BOOT_1); pmc_boot_0 = NV_PRIV_REG_RD32(reg_mapping, NV_PMC_BOOT_0); pmc_boot_42 = NV_PRIV_REG_RD32(reg_mapping, NV_PMC_BOOT_42); @@ -3195,6 +3229,10 @@ NV_STATUS NV_API_CALL rm_is_supported_device( goto print_unsupported; } + rmStatus = rm_is_vgpu_supported_device(pNv, pmc_boot_1); + + if (rmStatus != NV_OK) + goto print_unsupported; goto threadfree; print_unsupported: @@ -3331,7 +3369,7 @@ static NV_STATUS RmNonDPAuxI2CTransfer ( nv_state_t *pNv, NvU8 portId, - NvU8 type, + nv_i2c_cmd_t type, NvU8 addr, NvU8 command, NvU32 len, @@ -3411,6 +3449,17 @@ static NV_STATUS RmNonDPAuxI2CTransfer params->transType = NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW; break; + case NV_I2C_CMD_BLOCK_WRITE: + params->transData.i2cBufferData.bWrite = NV_TRUE; + /* fall through */ + + case NV_I2C_CMD_BLOCK_READ: + params->transType = NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW; + params->transData.i2cBufferData.registerAddress = command; + params->transData.i2cBufferData.messageLength = len; + params->transData.i2cBufferData.pMessage = pData; + break; + default: portMemFree(params); return NV_ERR_INVALID_ARGUMENT; @@ -3447,7 +3496,7 @@ NV_STATUS NV_API_CALL rm_i2c_transfer( nvidia_stack_t *sp, nv_state_t *pNv, void *pI2cAdapter, - NvU8 type, + nv_i2c_cmd_t type, NvU8 addr, NvU8 command, NvU32 len, @@ -3470,7 +3519,7 @@ NV_STATUS NV_API_CALL rm_i2c_transfer( if (pNvp->flags & NV_INIT_FLAG_PUBLIC_I2C) { // LOCK: acquire API lock - if ((rmStatus = rmApiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_I2C)) != NV_OK) + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_I2C)) != NV_OK) goto finish; unlockApi = NV_TRUE; @@ -3547,7 +3596,7 @@ finish: if (unlockApi) { // UNLOCK: release API lock - rmApiLockRelease(); + rmapiLockRelease(); } threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); @@ -3803,7 +3852,7 @@ NvBool NV_API_CALL rm_i2c_is_smbus_capable( if (pNvp->flags & NV_INIT_FLAG_PUBLIC_I2C) { // LOCK: acquire API lock - if ((rmStatus = rmApiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_I2C)) != NV_OK) + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_I2C)) != NV_OK) goto semafinish; unlock = NV_TRUE; @@ -3842,7 +3891,7 @@ semafinish: if (unlock) { // UNLOCK: release API lock - rmApiLockRelease(); + rmapiLockRelease(); } threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); @@ -3872,23 +3921,27 @@ NV_STATUS NV_API_CALL rm_perform_version_check( return rmStatus; } -NV_STATUS NV_API_CALL rm_system_event( +// +// Handles the Power Source Change event(AC/DC) for Notebooks. +// Notebooks from Maxwell have only one Gpu, so this functions grabs first Gpu +// from GpuMgr and call subdevice RmControl. +// +void NV_API_CALL rm_power_source_change_event( nvidia_stack_t *sp, - NvU32 event_type, NvU32 event_val ) { THREAD_STATE_NODE threadState; - NV_STATUS rmStatus; - void *fp; + void *fp; nv_state_t *nv; - OBJGPU *pGpu = gpumgrGetGpu(0);// Grab the first GPU + OBJGPU *pGpu = gpumgrGetGpu(0); + NV_STATUS rmStatus = NV_OK; NV_ENTER_RM_RUNTIME(sp,fp); threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); // LOCK: acquire API lock - if ((rmStatus = rmApiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_EVENT)) == NV_OK) + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_EVENT)) == NV_OK) { if (pGpu != NULL) { @@ -3900,7 +3953,7 @@ NV_STATUS NV_API_CALL rm_system_event( if ((rmStatus = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_EVENT)) == NV_OK) { - rmStatus = RmSystemEvent(nv, event_type, event_val); + rmStatus = RmPowerSourceChangeEvent(nv, event_val); // UNLOCK: release GPU lock rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); @@ -3908,14 +3961,19 @@ NV_STATUS NV_API_CALL rm_system_event( os_unref_dynamic_power(nv, NV_DYNAMIC_PM_FINE); } // UNLOCK: release API lock - rmApiLockRelease(); + rmapiLockRelease(); } } + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "%s: Failed to handle Power Source change event, status=0x%x\n", + __FUNCTION__, rmStatus); + } + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); NV_EXIT_RM_RUNTIME(sp,fp); - - return rmStatus; } NV_STATUS NV_API_CALL rm_p2p_dma_map_pages( @@ -3942,7 +4000,7 @@ NV_STATUS NV_API_CALL rm_p2p_dma_map_pages( NV_ENTER_RM_RUNTIME(sp,fp); threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); - if ((rmStatus = rmApiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK) + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK) { OBJGPU *pGpu = gpumgrGetGpuFromUuid(pGpuUuid, DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _TYPE, _SHA1) | @@ -3984,7 +4042,7 @@ NV_STATUS NV_API_CALL rm_p2p_dma_map_pages( } } - rmApiLockRelease(); + rmapiLockRelease(); } threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); @@ -4009,7 +4067,7 @@ NV_STATUS NV_API_CALL rm_p2p_get_gpu_info( threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); // LOCK: acquire API lock - rmStatus = rmApiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P); + rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P); if (rmStatus == NV_OK) { OBJGPU *pGpu; @@ -4039,7 +4097,7 @@ NV_STATUS NV_API_CALL rm_p2p_get_gpu_info( } // UNLOCK: release API lock - rmApiLockRelease(); + rmapiLockRelease(); } threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); @@ -4067,7 +4125,7 @@ NV_STATUS NV_API_CALL rm_p2p_get_pages_persistent( threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); // LOCK: acquire API lock - if ((rmStatus = rmApiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK) + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK) { rmStatus = RmP2PGetPagesPersistent(gpuVirtualAddress, length, @@ -4077,7 +4135,7 @@ NV_STATUS NV_API_CALL rm_p2p_get_pages_persistent( pPlatformData, pGpuInfo); // UNLOCK: release API lock - rmApiLockRelease(); + rmapiLockRelease(); } threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); @@ -4108,7 +4166,7 @@ NV_STATUS NV_API_CALL rm_p2p_get_pages( threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); // LOCK: acquire API lock - if ((rmStatus = rmApiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK) + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK) { OBJGPU *pGpu; rmStatus = RmP2PGetPagesWithoutCallbackRegistration(p2pToken, @@ -4143,7 +4201,7 @@ NV_STATUS NV_API_CALL rm_p2p_get_pages( } // UNLOCK: release API lock - rmApiLockRelease(); + rmapiLockRelease(); } threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); @@ -4170,13 +4228,13 @@ NV_STATUS NV_API_CALL rm_p2p_register_callback( threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); // LOCK: acquire API lock - if ((rmStatus = rmApiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK) + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK) { rmStatus = RmP2PRegisterCallback(p2pToken, gpuVirtualAddress, length, pPlatformData, pFreeCallback, pData); // UNLOCK: release API lock - rmApiLockRelease(); + rmapiLockRelease(); } threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); @@ -4199,12 +4257,12 @@ NV_STATUS NV_API_CALL rm_p2p_put_pages_persistent( threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); // LOCK: acquire API lock - if ((rmStatus = rmApiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK) + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK) { rmStatus = RmP2PPutPagesPersistent(p2pObject, pKey); // UNLOCK: release API lock - rmApiLockRelease(); + rmapiLockRelease(); } threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); @@ -4229,7 +4287,7 @@ NV_STATUS NV_API_CALL rm_p2p_put_pages( threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); // LOCK: acquire API lock - if ((rmStatus = rmApiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK) + if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK) { rmStatus = RmP2PPutPages(p2pToken, vaSpaceToken, @@ -4237,7 +4295,7 @@ NV_STATUS NV_API_CALL rm_p2p_put_pages( pKey); // UNLOCK: release API lock - rmApiLockRelease(); + rmapiLockRelease(); } threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); @@ -4253,7 +4311,6 @@ char* NV_API_CALL rm_get_gpu_uuid( { NV_STATUS rmStatus; const NvU8 *pGid; - OBJGPU *pGpu; char *pGidString; THREAD_STATE_NODE threadState; @@ -4285,16 +4342,7 @@ char* NV_API_CALL rm_get_gpu_uuid( } else { - const char *pTmpString; - - // No raw GID, but we still return a string - pGpu = NV_GET_NV_PRIV_PGPU(nv); - - if (rmStatus == NV_ERR_NOT_SUPPORTED && pGpu != NULL && - pGpu->getProperty(pGpu, PDB_PROP_GPU_STATE_INITIALIZED)) - pTmpString = "N/A"; - else - pTmpString = "GPU-???????\?-???\?-???\?-???\?-????????????"; + const char *pTmpString = "GPU-???????\?-???\?-???\?-???\?-????????????"; portStringCopy(pGidString, GPU_UUID_ASCII_LEN, pTmpString, portStringLength(pTmpString) + 1); @@ -4463,7 +4511,7 @@ NV_STATUS NV_API_CALL rm_log_gpu_crash( NV_ENTER_RM_RUNTIME(sp,fp); threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); - if ((status = rmApiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DIAG)) == NV_OK) + if ((status = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DIAG)) == NV_OK) { OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); @@ -4474,7 +4522,7 @@ NV_STATUS NV_API_CALL rm_log_gpu_crash( rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); } - rmApiLockRelease(); + rmapiLockRelease(); } threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); @@ -4564,6 +4612,10 @@ void RmInitAcpiMethods(OBJOS *pOS, OBJSYS *pSys, OBJGPU *pGpu) nv_acpi_methods_init(&handlesPresent); + // Check if NVPCF _DSM functions are implemented under NVPCF or GPU device scope. + RmCheckNvpcfDsmScope(pGpu); + acpiDsmInit(pGpu); + } // @@ -4817,7 +4869,7 @@ NvBool NV_API_CALL rm_is_device_sequestered( NV_ENTER_RM_RUNTIME(sp,fp); threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); - if (rmApiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_GPU) == NV_OK) + if (rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_GPU) == NV_OK) { // // If gpumgrQueryGpuDrainState succeeds, bDrain will be set as needed. @@ -4827,7 +4879,7 @@ NvBool NV_API_CALL rm_is_device_sequestered( // (void) gpumgrQueryGpuDrainState(pNv->gpu_id, &bDrain, NULL); - rmApiLockRelease(); + rmapiLockRelease(); } threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); @@ -4848,7 +4900,7 @@ void NV_API_CALL rm_check_for_gpu_surprise_removal( threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); // LOCK: acquire API lock. - if ((rmStatus = rmApiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_GPU)) == NV_OK) + if ((rmStatus = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_GPU)) == NV_OK) { OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); @@ -4859,7 +4911,7 @@ void NV_API_CALL rm_check_for_gpu_surprise_removal( } // UNLOCK: release api lock - rmApiLockRelease(); + rmapiLockRelease(); } threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); @@ -5011,7 +5063,7 @@ NV_STATUS NV_API_CALL rm_dma_buf_dup_mem_handle( pGpu = NV_GET_NV_PRIV_PGPU(nv); - NV_ASSERT(rmApiLockIsOwner()); + NV_ASSERT(rmapiLockIsOwner()); NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); @@ -5079,7 +5131,7 @@ void NV_API_CALL rm_dma_buf_undup_mem_handle( pGpu = NV_GET_NV_PRIV_PGPU(nv); - NV_ASSERT(rmApiLockIsOwner()); + NV_ASSERT(rmapiLockIsOwner()); NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); @@ -5117,7 +5169,7 @@ NV_STATUS NV_API_CALL rm_dma_buf_map_mem_handle( pGpu = NV_GET_NV_PRIV_PGPU(nv); pKernelBus = GPU_GET_KERNEL_BUS(pGpu); - NV_ASSERT(rmApiLockIsOwner()); + NV_ASSERT(rmapiLockIsOwner()); NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); @@ -5155,7 +5207,7 @@ NV_STATUS NV_API_CALL rm_dma_buf_unmap_mem_handle( pGpu = NV_GET_NV_PRIV_PGPU(nv); pKernelBus = GPU_GET_KERNEL_BUS(pGpu); - NV_ASSERT(rmApiLockIsOwner()); + NV_ASSERT(rmapiLockIsOwner()); NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); @@ -5186,7 +5238,7 @@ NV_STATUS NV_API_CALL rm_dma_buf_get_client_and_device( threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); // LOCK: acquire API lock - rmStatus = rmApiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI); + rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI); if (rmStatus == NV_OK) { OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); @@ -5201,7 +5253,7 @@ NV_STATUS NV_API_CALL rm_dma_buf_get_client_and_device( } // UNLOCK: release API lock - rmApiLockRelease(); + rmapiLockRelease(); } threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); @@ -5227,7 +5279,7 @@ void NV_API_CALL rm_dma_buf_put_client_and_device( threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); // LOCK: acquire API lock - rmStatus = rmApiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI); + rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI); if (rmStatus == NV_OK) { OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); @@ -5242,10 +5294,24 @@ void NV_API_CALL rm_dma_buf_put_client_and_device( } // UNLOCK: release API lock - rmApiLockRelease(); + rmapiLockRelease(); } NV_ASSERT_OK(rmStatus); threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); NV_EXIT_RM_RUNTIME(sp,fp); } + +// +// Fetches GSP ucode data for usage during RM Init +// NOTE: Used only on VMWware +// + +NvBool NV_API_CALL rm_is_altstack_in_use(void) +{ +#if defined(__use_altstack__) + return NV_TRUE; +#else + return NV_FALSE; +#endif +} diff --git a/src/nvidia/arch/nvalloc/unix/src/osinit.c b/src/nvidia/arch/nvalloc/unix/src/osinit.c index 91eefe67c..5080e50b5 100644 --- a/src/nvidia/arch/nvalloc/unix/src/osinit.c +++ b/src/nvidia/arch/nvalloc/unix/src/osinit.c @@ -55,12 +55,13 @@ #include #include #include -#include +#include #include -#include +#include "liblogdecode.h" #include #include +#include #include #include @@ -72,6 +73,7 @@ #include +#include "platform/nbsi/nbsi_read.h" #include "gpu_mgr/gpu_db.h" #include #include @@ -119,7 +121,6 @@ typedef enum /* rm firmware errors */ RM_INIT_FIRMWARE_POLICY_FAILED = 0x60, RM_INIT_FIRMWARE_FETCH_FAILED, - RM_INIT_FIRMWARE_VALIDATION_FAILED, RM_INIT_FIRMWARE_INIT_FAILED, RM_INIT_MAX_FAILURES @@ -638,6 +639,15 @@ osInitNvMapping( sysApplyLockingPolicy(pSys); pGpu->busInfo.IntLine = nv->interrupt_line; + + // + // Set the DMA address size as soon as we have the HAL to call to + // determine the precise number of physical address bits supported + // by the architecture. DMA allocations should not be made before + // this point. + // + nv_set_dma_address_size(nv, gpuGetPhysAddrWidth_HAL(pGpu, ADDR_SYSMEM)); + pGpu->dmaStartAddress = (RmPhysAddr)nv_get_dma_start_address(nv); if (nv->fb != NULL) { @@ -726,15 +736,6 @@ osTeardownScalability( return clTeardownPcie(pGpu, pCl); } -static inline void -RmSetDeviceDmaAddressSize( - nv_state_t *nv, - NvU8 numDmaAddressBits -) -{ - nv_set_dma_address_size(nv, numDmaAddressBits); -} - static void populateDeviceAttributes( OBJGPU *pGpu, @@ -884,8 +885,6 @@ RmInitNvDevice( return; } - RmSetDeviceDmaAddressSize(nv, gpuGetPhysAddrWidth_HAL(pGpu, ADDR_SYSMEM)); - os_disable_console_access(); status->rmStatus = gpumgrStateInitGpu(pGpu); @@ -1089,7 +1088,10 @@ RmSetupRegisters( nv->fb->cpu_address, nv->fb->size); } - nv_os_map_kernel_space(nv, nv->regs); + { + nv_os_map_kernel_space(nv, nv->regs); + } + if (nv->regs->map == NULL) { NV_DEV_PRINTF(NV_DBG_ERRORS, nv, "Failed to map regs registers!!\n"); @@ -1144,7 +1146,7 @@ NvBool RmInitPrivateState( NV_SET_NV_PRIV(pNv, NULL); - if (!NV_IS_SOC_DISPLAY_DEVICE(pNv)) + if (!NV_IS_SOC_DISPLAY_DEVICE(pNv) && !NV_IS_SOC_IGPU_DEVICE(pNv)) { pNv->regs->map_u = os_map_kernel_space(pNv->regs->cpu_address, os_page_size, @@ -1185,11 +1187,13 @@ NvBool RmInitPrivateState( pNv->iovaspace_id = nv_requires_dma_remap(pNv) ? gpuId : NV_IOVA_DOMAIN_NONE; + kvgpumgrAttachGpu(pNv->gpu_id); + // // Set up a reasonable default DMA address size, based on the minimum // possible on currently supported GPUs. // - RmSetDeviceDmaAddressSize(pNv, NV_GPU_MIN_SUPPORTED_DMA_ADDR_WIDTH); + nv_set_dma_address_size(pNv, NV_GPU_MIN_SUPPORTED_DMA_ADDR_WIDTH); os_mem_set(nvp, 0, sizeof(*nvp)); nvp->status = NV_ERR_INVALID_STATE; @@ -1269,6 +1273,8 @@ void RmFreePrivateState( gpumgrUnregisterGpuId(pNv->gpu_id); + kvgpumgrDetachGpu(pNv->gpu_id); + RmDestroyRegistry(pNv); if (nvp != NULL) @@ -1448,78 +1454,6 @@ fail: return NV_FALSE; } -static NvBool verifyGspFirmware( - const void *pGspFwBuf, - NvU32 gspFwBufSize -) -{ - // - // This array will be populated with a sha256 hash of the GSP-RM firmware - // binary in a post-compile step. We really want this array to be 'const', - // but adding that qualifier here makes the compiler perform undesirable - // optimization assuming the array is always going to be zero. The - // .gspfwhash-rodata section is marked readonly when it is populated with - // the real hash in lieu of 'const'. - // - static NvU8 __attribute__((section(".gspfwhash-rodata"))) - expectedFwHash[NV_SHA256_DIGEST_SIZE] = {}; - NvU32 i; - NvBool bHashCheck = NV_FALSE; - - // - // To allow for simple incremental build workflow, we will only - // perform the firmware hash check if the expected hash has been - // embedded into the kernel binary. - // - for (i = 0; i < NV_SHA256_DIGEST_SIZE; i++) - { - if (expectedFwHash[i] != 0) - { - bHashCheck = NV_TRUE; - break; - } - } - - if (bHashCheck) - { - NvU8 gspFwHash[NV_SHA256_DIGEST_SIZE]; - - nv_sha256(pGspFwBuf, gspFwBufSize, gspFwHash); - - #define NvU64_BIG_ENDIAN(buf) \ - ((NvU64)(buf)[0] << 56) | ((NvU64)(buf)[1] << 48) | \ - ((NvU64)(buf)[2] << 40) | ((NvU64)(buf)[3] << 32) | \ - ((NvU64)(buf)[4] << 24) | ((NvU64)(buf)[5] << 16) | \ - ((NvU64)(buf)[6] << 8) | ((NvU64)(buf)[7] << 0) - - if (portMemCmp(expectedFwHash, gspFwHash, NV_SHA256_DIGEST_SIZE) != 0) - { - NV_PRINTF(LEVEL_ERROR, "GSP firmware validation failed: hash mismatch\n"); - NV_PRINTF(LEVEL_ERROR, "Expected GSP firmware hash: %016llx%016llx%016llx%016llx\n", - NvU64_BIG_ENDIAN(&expectedFwHash[0]), NvU64_BIG_ENDIAN(&expectedFwHash[8]), - NvU64_BIG_ENDIAN(&expectedFwHash[16]), NvU64_BIG_ENDIAN(&expectedFwHash[24])); - NV_PRINTF(LEVEL_ERROR, "Got GSP firmware hash: %016llx%016llx%016llx%016llx\n", - NvU64_BIG_ENDIAN(&gspFwHash[0]), NvU64_BIG_ENDIAN(&gspFwHash[8]), - NvU64_BIG_ENDIAN(&gspFwHash[16]), NvU64_BIG_ENDIAN(&gspFwHash[24])); - NV_PRINTF(LEVEL_ERROR, "The GSP firmware version must exactly match the RM (nv-kernel.o) build.\n"); - NV_PRINTF(LEVEL_ERROR, "Most likely cause of this error is an out of band update to one of the components\n"); - - return NV_FALSE; - } - else - { - NV_PRINTF(LEVEL_NOTICE, "GSP firmware hash: %016llx%016llx%016llx%016llx\n", - NvU64_BIG_ENDIAN(&gspFwHash[0]), NvU64_BIG_ENDIAN(&gspFwHash[8]), - NvU64_BIG_ENDIAN(&gspFwHash[16]), NvU64_BIG_ENDIAN(&gspFwHash[24])); - } - } - else - { - NV_PRINTF(LEVEL_NOTICE, "GSP firmware hash not found.\n"); - } - return NV_TRUE; -} - NvBool RmInitAdapter( nv_state_t *nv ) @@ -1583,9 +1517,16 @@ NvBool RmInitAdapter( // if (nv->request_firmware) { - RmSetDeviceDmaAddressSize(nv, NV_GSP_GPU_MIN_SUPPORTED_DMA_ADDR_WIDTH); + NvU32 gpuArch = (DRF_VAL(_PMC, _BOOT_42, _ARCHITECTURE, nvp->pmc_boot_42) << + GPU_ARCH_SHIFT); + NvU32 gpuImpl = DRF_VAL(_PMC, _BOOT_42, _IMPLEMENTATION, nvp->pmc_boot_42); - gspFwHandle = nv_get_firmware(nv, NV_FIRMWARE_GSP, + nv_firmware_chip_family_t chipFamily = nv_firmware_get_chip_family(gpuArch, gpuImpl); + + nv_set_dma_address_size(nv, NV_GSP_GPU_MIN_SUPPORTED_DMA_ADDR_WIDTH); + + gspFwHandle = nv_get_firmware(nv, NV_FIRMWARE_TYPE_GSP, + chipFamily, &gspFw.pBuf, &gspFw.size); if (gspFwHandle == NULL && @@ -1596,21 +1537,16 @@ NvBool RmInitAdapter( } else if (gspFwHandle != NULL) { - if (!verifyGspFirmware(gspFw.pBuf, gspFw.size)) - { - RM_SET_ERROR(status, RM_INIT_FIRMWARE_VALIDATION_FAILED); - goto shutdown; - } - #if LIBOS_LOG_DECODE_ENABLE if (nv->enable_firmware_logs) { - gspFwLogHandle = nv_get_firmware(nv, NV_FIRMWARE_GSP_LOG, + gspFwLogHandle = nv_get_firmware(nv, NV_FIRMWARE_TYPE_GSP_LOG, + chipFamily, &gspFw.pLogElf, &gspFw.logElfSize); if (gspFwLogHandle == NULL) { - NV_PRINTF(LEVEL_ERROR, "Failed to load gsp_log.bin, no GSP-RM logs will be printed (non-fatal)\n"); + NV_PRINTF(LEVEL_ERROR, "Failed to load gsp_log_*.bin, no GSP-RM logs will be printed (non-fatal)\n"); } } #endif @@ -1669,6 +1605,8 @@ NvBool RmInitAdapter( RmSetConsolePreservationParams(pGpu); + RmInitAcpiMethods(pOS, pSys, pGpu); + // // If GSP fw RM support is enabled then start the GSP microcode // (including the task running the full instance of the RM) and @@ -1710,17 +1648,11 @@ NvBool RmInitAdapter( populateDeviceAttributes(pGpu, nv); - RmInitAcpiMethods(pOS, pSys, pGpu); - - status.rmStatus = RmInitX86Emu(pGpu); - if (status.rmStatus != NV_OK) - { - RM_SET_ERROR(status, RM_INIT_VBIOS_X86EMU_FAILED); - NV_PRINTF(LEVEL_ERROR, - "RmInitX86Emu failed, bailing out of RmInitAdapter\n"); - goto shutdown; - } initVendorSpecificRegistry(pGpu, nv->pci_info.device_id); + if (!IS_VIRTUAL(pGpu) && !IS_GSP_CLIENT(pGpu)) + { + initNbsiTable(pGpu); + } // finally, initialize the device RmInitNvDevice(devicereference, &status); @@ -1809,6 +1741,15 @@ NvBool RmInitAdapter( goto shutdown; } + status.rmStatus = RmInitX86Emu(pGpu); + if (status.rmStatus != NV_OK) + { + RM_SET_ERROR(status, RM_INIT_VBIOS_X86EMU_FAILED); + NV_PRINTF(LEVEL_ERROR, + "RmInitX86Emu failed, bailing out of RmInitAdapter\n"); + goto shutdown; + } + // i2c only on master device?? RmI2cAddGpuPorts(nv); nvp->flags |= NV_INIT_FLAG_PUBLIC_I2C; @@ -1861,10 +1802,10 @@ NvBool RmInitAdapter( if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_NONE) == NV_OK) { // - // As we have already acquired the API Lock here, we are - // calling RmSystemEvent directly instead of rm_system_event. + // As we have already acquired the API Lock here, we are calling + // RmPowerSourceChangeEvent directly instead of rm_power_source_change_event. // - RmSystemEvent(nv, NV_SYSTEM_ACPI_BATTERY_POWER_EVENT, !ac_plugged); + RmPowerSourceChangeEvent(nv, !ac_plugged); // UNLOCK: release GPU lock rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); @@ -1878,7 +1819,8 @@ NvBool RmInitAdapter( // OpenRM with a special registry key, if not on a Data Center GPU. const GspStaticConfigInfo *pSCI = GPU_GET_GSP_STATIC_INFO(pGpu); - if (pSCI->computeBranding != COMPUTE_BRANDING_TYPE_TESLA) + if (pSCI->computeBranding != COMPUTE_BRANDING_TYPE_TESLA && + ((pGpu->idInfo.PCIDeviceID >> 16) & 0xffff) != NV_PCI_DEVID_DEVICE_PG189_SKU600) { NvU32 data = NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_DEFAULT; RmReadRegistryDword(nv, NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS, &data); @@ -1949,6 +1891,8 @@ void RmShutdownAdapter( { RmDestroyDeferredDynamicPowerManagement(nv); + freeNbsiTable(pGpu); + gpuFreeEventHandle(pGpu); OBJCL *pCl = SYS_GET_CL(pSys); diff --git a/src/nvidia/arch/nvalloc/unix/src/osmemdesc.c b/src/nvidia/arch/nvalloc/unix/src/osmemdesc.c index 8afc791ca..ad49cf71a 100644 --- a/src/nvidia/arch/nvalloc/unix/src/osmemdesc.c +++ b/src/nvidia/arch/nvalloc/unix/src/osmemdesc.c @@ -526,7 +526,9 @@ osCreateOsDescriptorFromPhysAddr NvU64 base = 0; NvU32 cache_type = NV_MEMORY_CACHED; NvU64 memdescFlags = MEMDESC_FLAGS_NONE; - + NvU64 *pPhys_addrs; + NvU64 num_os_pages; + NvU32 idx; // Currently only work with contiguous sysmem allocations if (!FLD_TEST_DRF(OS02, _FLAGS, _PHYSICALITY, _CONTIGUOUS, flags)) { @@ -565,21 +567,34 @@ osCreateOsDescriptorFromPhysAddr pPteArray = memdescGetPteArray(pMemDesc, AT_CPU); pPteArray[0] = base; + num_os_pages = NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount); + pPhys_addrs = portMemAllocNonPaged(sizeof(NvU64) * num_os_pages); + if (pPhys_addrs == NULL) + return NV_ERR_NO_MEMORY; + + for (idx = 0; idx < num_os_pages; idx++) + { + pPhys_addrs[idx] = base + (idx * os_page_size); + } + *ppPrivate = NULL; - rmStatus = nv_register_phys_pages(NV_GET_NV_STATE(pGpu), pPteArray, - NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount), + rmStatus = nv_register_phys_pages(NV_GET_NV_STATE(pGpu), pPhys_addrs, + num_os_pages, memdescGetCpuCacheAttrib(pMemDesc), ppPrivate); if (rmStatus != NV_OK) { memdescDestroy(pMemDesc); - return rmStatus; + goto cleanup; } memdescSetMemData(pMemDesc, *ppPrivate, osDestroyOsDescriptorFromPhysAddr); - return NV_OK; +cleanup: + portMemFree(pPhys_addrs); + + return rmStatus; } static NV_STATUS diff --git a/src/nvidia/arch/nvalloc/unix/src/rmobjexportimport.c b/src/nvidia/arch/nvalloc/unix/src/rmobjexportimport.c index 570354661..dcc8d94ad 100644 --- a/src/nvidia/arch/nvalloc/unix/src/rmobjexportimport.c +++ b/src/nvidia/arch/nvalloc/unix/src/rmobjexportimport.c @@ -340,6 +340,7 @@ NV_STATUS RmExportObject(NvHandle hSrcClient, NvHandle hSrcObject, RmObjExportHandle hDstObject; NvU32 deviceInstance = NV_MAX_DEVICES; NvHandle hTmpObject; + NvBool bClientAsDstParent = NV_FALSE; NV_STATUS status; RM_API *pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL); @@ -370,9 +371,10 @@ NV_STATUS RmExportObject(NvHandle hSrcClient, NvHandle hSrcObject, hTmpObject = pResourceRef->pParentRef ? pResourceRef->pParentRef->hResource : 0; } while (hTmpObject != 0); + // If a memory object is not parented by a device, use client as a parent. if ((hTmpObject == 0) || (deviceInstance >= NV_MAX_DEVICES)) { - return NV_ERR_OBJECT_NOT_FOUND; + bClientAsDstParent = NV_TRUE; } status = RmRefObjExportImport(); @@ -382,9 +384,10 @@ NV_STATUS RmExportObject(NvHandle hSrcClient, NvHandle hSrcObject, return status; } - if (objExportDevice[deviceInstance].hRmDevice == 0 || - serverutilValidateNewResourceHandle(hObjExportRmClient, - objExportDevice[deviceInstance].hRmDevice)) + if (!bClientAsDstParent && + ((objExportDevice[deviceInstance].hRmDevice == 0) || + serverutilValidateNewResourceHandle(hObjExportRmClient, + objExportDevice[deviceInstance].hRmDevice))) { // // Device object has not been created or it got destroyed in the @@ -465,6 +468,7 @@ NV_STATUS RmExportObject(NvHandle hSrcClient, NvHandle hSrcObject, // If duping under device handle fails, try subdevice handle. status = pRmApi->DupObject(pRmApi, hObjExportRmClient, + bClientAsDstParent ? hObjExportRmClient : objExportDevice[deviceInstance].hRmDevice, &hDstObject, hSrcClient, @@ -472,7 +476,7 @@ NV_STATUS RmExportObject(NvHandle hSrcClient, NvHandle hSrcObject, 0 /* flags */); if (status != NV_OK) { - if (status == NV_ERR_INVALID_OBJECT_PARENT) + if (!bClientAsDstParent && (status == NV_ERR_INVALID_OBJECT_PARENT)) { NV_PRINTF(LEVEL_INFO, "pRmApi->DupObject(Dev, failed due to invalid parent in %s." @@ -584,6 +588,12 @@ NV_STATUS RmImportObject(NvHandle hDstClient, NvHandle hDstParent, case NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC: *pObjectType = NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC; break; +#if defined(NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC_MC) && \ + defined(NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC_MC) + case NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC_MC: + *pObjectType = NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC_MC; + break; +#endif default: NV_ASSERT_OK_OR_RETURN(NV_ERR_INVALID_ARGUMENT); } diff --git a/src/nvidia/arch/nvalloc/unix/src/unix_console.c b/src/nvidia/arch/nvalloc/unix/src/unix_console.c index ad78a4c38..8b1c05537 100644 --- a/src/nvidia/arch/nvalloc/unix/src/unix_console.c +++ b/src/nvidia/arch/nvalloc/unix/src/unix_console.c @@ -25,17 +25,19 @@ #include #include #include -#include -#include #include #include #include +#include -NV_STATUS deviceCtrlCmdOsUnixVTGetFBInfo_IMPL(Device *pDevice, - NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS *pParams) +NV_STATUS deviceCtrlCmdOsUnixVTGetFBInfo_IMPL +( + Device *pDevice, + NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS *pParams +) { OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); - nv_state_t *nv = NV_GET_NV_STATE(pGpu); + NvBool bContinue = NV_TRUE; if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_FB) == NV_OK) { @@ -45,8 +47,9 @@ NV_STATUS deviceCtrlCmdOsUnixVTGetFBInfo_IMPL(Device *pDevice, SLI_LOOP_START(SLI_LOOP_FLAGS_NONE) MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + nv_state_t *nv = NV_GET_NV_STATE(pGpu); - if (memmgrGetReservedConsoleMemDesc(pGpu, pMemoryManager) != NULL) + if ((memmgrGetReservedConsoleMemDesc(pGpu, pMemoryManager) != NULL) && bContinue) { NvU64 baseAddr; @@ -61,6 +64,11 @@ NV_STATUS deviceCtrlCmdOsUnixVTGetFBInfo_IMPL(Device *pDevice, &pParams->pitch, nv->bars[NV_GPU_BAR_INDEX_FB].cpu_address, nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + 0x1000000); + + if (baseAddr != 0) + { + bContinue = NV_FALSE; + } } SLI_LOOP_END @@ -74,3 +82,37 @@ NV_STATUS deviceCtrlCmdOsUnixVTGetFBInfo_IMPL(Device *pDevice, return NV_OK; } + + +void +dispdeviceFillVgaSavedDisplayState +( + OBJGPU *pGpu, + NvU64 vgaAddr, + NvU8 vgaMemType, + NvBool vgaValid, + NvU64 workspaceAddr, + NvU8 workspaceMemType, + NvBool workspaceValid, + NvBool baseValid, + NvBool workspaceBaseValid +) +{ + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + NvBool use_vbios = NV_PRIMARY_VGA(nv) && RmGpuHasIOSpaceEnabled(nv); + + if (use_vbios) + { + nvp->vga.base.addr = vgaAddr; + nvp->vga.base.memTarget = vgaMemType; + nvp->vga.base.valid = vgaValid; + nvp->vga.baseValid = baseValid; + + nvp->vga.workspaceBase.addr = workspaceAddr; + nvp->vga.workspaceBase.memTarget = workspaceMemType; + nvp->vga.workspaceBase.valid = workspaceValid; + nvp->vga.workspaceBaseValid = workspaceBaseValid; + } +} + diff --git a/src/nvidia/arch/nvalloc/unix/src/unix_intr.c b/src/nvidia/arch/nvalloc/unix/src/unix_intr.c index b05249ba1..d60a30d73 100644 --- a/src/nvidia/arch/nvalloc/unix/src/unix_intr.c +++ b/src/nvidia/arch/nvalloc/unix/src/unix_intr.c @@ -28,10 +28,13 @@ #include #include #include "kernel/gpu/intr/intr.h" -#include +#include "gpu/bif/kernel_bif.h" +#include "gpu/mmu/kern_gmmu.h" #include "gpu/disp/kern_disp.h" +#include #include "objtmr.h" + static NvBool osInterruptPending( OBJGPU *pGpu, NvBool *serviced, @@ -134,7 +137,7 @@ static NvBool osInterruptPending( } // LOCK: try to acquire GPUs lock - if (rmDeviceGpuLocksAcquire(pDeviceLockGpu, GPUS_LOCK_FLAGS_COND_ACQUIRE, RM_LOCK_MODULES_ISR) == NV_OK) + if (rmDeviceGpuLocksAcquire(pDeviceLockGpu, GPU_LOCK_FLAGS_COND_ACQUIRE, RM_LOCK_MODULES_ISR) == NV_OK) { threadStateInitISRAndDeferredIntHandler(&threadState, pDeviceLockGpu, THREAD_STATE_FLAGS_IS_ISR); @@ -569,3 +572,129 @@ void NV_API_CALL rm_isr_bh_unlocked( NV_EXIT_RM_RUNTIME(sp,fp); } +NV_STATUS NV_API_CALL rm_gpu_copy_mmu_faults( + nvidia_stack_t *sp, + nv_state_t *nv, + NvU32 *faultsCopied +) +{ + NV_STATUS status = NV_OK; + OBJGPU *pGpu; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + pGpu = NV_GET_NV_PRIV_PGPU(nv); + if (pGpu == NULL || faultsCopied == NULL) + { + status = NV_ERR_OBJECT_NOT_FOUND; + goto done; + } + + // Non-replayable faults are copied to the client shadow buffer by GSP-RM. + if (IS_GSP_CLIENT(pGpu)) + { + status = NV_ERR_NOT_SUPPORTED; + goto done; + } + +done: + NV_EXIT_RM_RUNTIME(sp,fp); + + return status; +} + +// +// Use this call when MMU faults needs to be copied +// outisde of RM lock. +// +NV_STATUS NV_API_CALL rm_gpu_copy_mmu_faults_unlocked( + nvidia_stack_t *sp, + nv_state_t *nv, + NvU32 *faultsCopied +) +{ + OBJGPU *pGpu; + void *fp; + NV_STATUS status = NV_OK; + + NV_ENTER_RM_RUNTIME(sp,fp); + + pGpu = NV_GET_NV_PRIV_PGPU(nv); + if (pGpu == NULL || faultsCopied == NULL) + { + status = NV_ERR_OBJECT_NOT_FOUND; + goto done; + } + + // Non-replayable faults are copied to the client shadow buffer by GSP-RM. + if (IS_GSP_CLIENT(pGpu)) + { + status = NV_ERR_NOT_SUPPORTED; + goto done; + } + +done: + NV_EXIT_RM_RUNTIME(sp,fp); + + return status; +} + +// +// Wrapper to handle calls to copy mmu faults +// +NV_STATUS rm_gpu_handle_mmu_faults( + nvidia_stack_t *sp, + nv_state_t *nv, + NvU32 *faultsCopied +) +{ + NvU32 status = NV_OK; + + *faultsCopied = 0; + + OBJGPU *pGpu; + pGpu = NV_GET_NV_PRIV_PGPU(nv); + + if (pGpu == NULL) + { + return NV_ERR_OBJECT_NOT_FOUND; + } + + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && !IS_VIRTUAL(pGpu)) + { + THREAD_STATE_NODE threadState; + + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + Intr *pIntr = GPU_GET_INTR(pGpu); + + NvU32 hw_put = 0; + NvU32 hw_get = 0; + + threadStateInitISRLockless(&threadState, pGpu, THREAD_STATE_FLAGS_IS_ISR_LOCKLESS); + + kgmmuReadFaultBufferPutPtr_HAL(pGpu, pKernelGmmu, NON_REPLAYABLE_FAULT_BUFFER, + &hw_put, &threadState); + + kgmmuReadFaultBufferGetPtr_HAL(pGpu, pKernelGmmu, NON_REPLAYABLE_FAULT_BUFFER, + &hw_get, &threadState); + + if(hw_get != hw_put) + { + // We have to clear the top level interrupt bit here since otherwise + // the bottom half will attempt to service the interrupt on the CPU + // side before GSP recieves the notification and services it + kgmmuClearNonReplayableFaultIntr(pGpu, pKernelGmmu, &threadState); + status = intrTriggerPrivDoorbell_HAL(pGpu, pIntr, NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_HANDLE); + + } + + threadStateFreeISRLockless(&threadState, pGpu, THREAD_STATE_FLAGS_IS_ISR_LOCKLESS); + } + else + { + status = rm_gpu_copy_mmu_faults_unlocked(sp, nv, faultsCopied); + } + return status; +} + diff --git a/src/nvidia/exports_link_command.txt b/src/nvidia/exports_link_command.txt index 1f6011da0..cf0e1d8d7 100644 --- a/src/nvidia/exports_link_command.txt +++ b/src/nvidia/exports_link_command.txt @@ -39,7 +39,7 @@ --undefined=rm_acquire_all_gpus_lock --undefined=rm_release_all_gpus_lock --undefined=rm_shutdown_rm ---undefined=rm_system_event +--undefined=rm_power_source_change_event --undefined=rm_write_registry_binary --undefined=rm_write_registry_dword --undefined=rm_write_registry_string @@ -153,6 +153,7 @@ --undefined=nvswitch_lib_is_i2c_supported --undefined=nvswitch_lib_i2c_transfer --undefined=rm_gpu_copy_mmu_faults +--undefined=rm_gpu_handle_mmu_faults --undefined=rm_gpu_copy_mmu_faults_unlocked --undefined=rm_gpu_need_4k_page_isolation --undefined=rm_is_chipset_io_coherent @@ -188,4 +189,4 @@ --undefined=rm_get_gpu_gcx_support --undefined=rm_is_iommu_needed_for_sriov --undefined=rm_disable_iomap_wc ---undefined=rm_get_clientnvpcf_power_limits +--undefined=rm_is_altstack_in_use diff --git a/src/nvidia/generated/g_access_cntr_buffer_nvoc.c b/src/nvidia/generated/g_access_cntr_buffer_nvoc.c index 1adec79d5..1b57c336e 100644 --- a/src/nvidia/generated/g_access_cntr_buffer_nvoc.c +++ b/src/nvidia/generated/g_access_cntr_buffer_nvoc.c @@ -207,6 +207,10 @@ static void __nvoc_thunk_RsResource_accesscntrPreDestruct(struct AccessCounterBu resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_AccessCounterBuffer_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_RsResource_accesscntrIsDuplicate(struct AccessCounterBuffer *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_AccessCounterBuffer_RsResource.offset), hMemory, pDuplicate); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_accesscntrGetNotificationListPtr(struct AccessCounterBuffer *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_AccessCounterBuffer_Notifier.offset)); } @@ -518,6 +522,8 @@ static void __nvoc_init_funcTable_AccessCounterBuffer_1(AccessCounterBuffer *pTh pThis->__accesscntrPreDestruct__ = &__nvoc_thunk_RsResource_accesscntrPreDestruct; + pThis->__accesscntrIsDuplicate__ = &__nvoc_thunk_RsResource_accesscntrIsDuplicate; + pThis->__accesscntrGetNotificationListPtr__ = &__nvoc_thunk_Notifier_accesscntrGetNotificationListPtr; pThis->__accesscntrGetNotificationShare__ = &__nvoc_thunk_Notifier_accesscntrGetNotificationShare; diff --git a/src/nvidia/generated/g_access_cntr_buffer_nvoc.h b/src/nvidia/generated/g_access_cntr_buffer_nvoc.h index f2f3eed6f..997c0adb8 100644 --- a/src/nvidia/generated/g_access_cntr_buffer_nvoc.h +++ b/src/nvidia/generated/g_access_cntr_buffer_nvoc.h @@ -93,6 +93,7 @@ struct AccessCounterBuffer { NV_STATUS (*__accesscntrUnregisterEvent__)(struct AccessCounterBuffer *, NvHandle, NvHandle, NvHandle, NvHandle); NvBool (*__accesscntrCanCopy__)(struct AccessCounterBuffer *); void (*__accesscntrPreDestruct__)(struct AccessCounterBuffer *); + NV_STATUS (*__accesscntrIsDuplicate__)(struct AccessCounterBuffer *, NvHandle, NvBool *); PEVENTNOTIFICATION *(*__accesscntrGetNotificationListPtr__)(struct AccessCounterBuffer *); struct NotifShare *(*__accesscntrGetNotificationShare__)(struct AccessCounterBuffer *); NvBool (*__accesscntrAccessCallback__)(struct AccessCounterBuffer *, struct RsClient *, void *, RsAccessRight); @@ -160,6 +161,7 @@ NV_STATUS __nvoc_objCreate_AccessCounterBuffer(AccessCounterBuffer**, Dynamic*, #define accesscntrUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) accesscntrUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define accesscntrCanCopy(pResource) accesscntrCanCopy_DISPATCH(pResource) #define accesscntrPreDestruct(pResource) accesscntrPreDestruct_DISPATCH(pResource) +#define accesscntrIsDuplicate(pResource, hMemory, pDuplicate) accesscntrIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define accesscntrGetNotificationListPtr(pNotifier) accesscntrGetNotificationListPtr_DISPATCH(pNotifier) #define accesscntrGetNotificationShare(pNotifier) accesscntrGetNotificationShare_DISPATCH(pNotifier) #define accesscntrAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) accesscntrAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) @@ -325,6 +327,10 @@ static inline void accesscntrPreDestruct_DISPATCH(struct AccessCounterBuffer *pR pResource->__accesscntrPreDestruct__(pResource); } +static inline NV_STATUS accesscntrIsDuplicate_DISPATCH(struct AccessCounterBuffer *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__accesscntrIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline PEVENTNOTIFICATION *accesscntrGetNotificationListPtr_DISPATCH(struct AccessCounterBuffer *pNotifier) { return pNotifier->__accesscntrGetNotificationListPtr__(pNotifier); } @@ -338,8 +344,10 @@ static inline NvBool accesscntrAccessCallback_DISPATCH(struct AccessCounterBuffe } NV_STATUS accesscntrConstruct_IMPL(struct AccessCounterBuffer *arg_pAccessCounterBuffer, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_accesscntrConstruct(arg_pAccessCounterBuffer, arg_pCallContext, arg_pParams) accesscntrConstruct_IMPL(arg_pAccessCounterBuffer, arg_pCallContext, arg_pParams) void accesscntrDestruct_IMPL(struct AccessCounterBuffer *pAccessCounterBuffer); + #define __nvoc_accesscntrDestruct(pAccessCounterBuffer) accesscntrDestruct_IMPL(pAccessCounterBuffer) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_allclasses.h b/src/nvidia/generated/g_allclasses.h index 9f60568d5..278c45728 100644 --- a/src/nvidia/generated/g_allclasses.h +++ b/src/nvidia/generated/g_allclasses.h @@ -48,14 +48,19 @@ #include // NV01_MEMORY_LOCAL_PRIVILEGED #include // NV01_MEMORY_LOCAL_USER #include // NV01_MEMORY_VIRTUAL +#include // NV_MEMORY_MAPPER #include // NV01_MEMORY_LOCAL_PHYSICAL #include // NV01_MEMORY_SYSTEM_OS_DESCRIPTOR #include // NV01_MEMORY_DEVICELESS #include // NV01_MEMORY_FRAMEBUFFER_CONSOLE #include // NV01_MEMORY_HW_RESOURCES +#include // NV01_MEMORY_LIST_SYSTEM +#include // NV01_MEMORY_LIST_FBMEM +#include // NV01_MEMORY_LIST_OBJECT #include // NV01_MEMORY_FLA #include // NV_MEMORY_FABRIC #include // FABRIC_VASPACE_A +#include // NV_MEMORY_MULTICAST_FABRIC #include // IO_VASPACE_A #include // NV01_NULL #include // NV01_EVENT @@ -76,6 +81,7 @@ #include // AMPERE_CHANNEL_GPFIFO_A #include // HOPPER_CHANNEL_GPFIFO_A #include // NV04_SOFTWARE_TEST +#include // NV30_GSYNC #include // VOLTA_USERMODE_A #include // TURING_USERMODE_A #include // AMPERE_USERMODE_A @@ -99,6 +105,7 @@ #include // NVC67B_WINDOW_IMM_CHANNEL_DMA #include // NVC67D_CORE_CHANNEL_DMA #include // NVC67E_WINDOW_CHANNEL_DMA +#include // NVC77F_ANY_CHANNEL_DMA #include // NVC770_DISPLAY #include // NVC771_DISP_SF_USER #include // NVC77D_CORE_CHANNEL_DMA @@ -160,8 +167,11 @@ #include // HOPPER_A #include // HOPPER_COMPUTE_A #include // NV40_DEBUG_BUFFER +#include // RM_USER_SHARED_DATA #include // GT200_DEBUGGER #include // NV40_I2C +#include // NVA081_VGPU_CONFIG +#include // NVA084_KERNEL_HOST_VGPU_DEVICE #include // NV0060_SYNC_GPU_BOOST #include // GP100_UVM_SW #include // NV_EVENT_BUFFER @@ -270,6 +280,10 @@ #define NV1_MEMORY_SYSTEM_DYNAMIC (0x00000070) // alias #endif +#ifndef NV_MEMORY_MAPPER +#define NV_MEMORY_MAPPER (0x000000fe) +#endif + #ifndef NV01_MEMORY_LOCAL_PHYSICAL #define NV01_MEMORY_LOCAL_PHYSICAL (0x000000c2) #endif @@ -290,6 +304,18 @@ #define NV01_MEMORY_HW_RESOURCES (0x000000b1) #endif +#ifndef NV01_MEMORY_LIST_SYSTEM +#define NV01_MEMORY_LIST_SYSTEM (0x00000081) +#endif + +#ifndef NV01_MEMORY_LIST_FBMEM +#define NV01_MEMORY_LIST_FBMEM (0x00000082) +#endif + +#ifndef NV01_MEMORY_LIST_OBJECT +#define NV01_MEMORY_LIST_OBJECT (0x00000083) +#endif + #ifndef NV01_MEMORY_FLA #define NV01_MEMORY_FLA (0x000000f3) #endif @@ -302,6 +328,10 @@ #define FABRIC_VASPACE_A (0x000000fc) #endif +#ifndef NV_MEMORY_MULTICAST_FABRIC +#define NV_MEMORY_MULTICAST_FABRIC (0x000000fd) +#endif + #ifndef IO_VASPACE_A #define IO_VASPACE_A (0x000000f2) #endif @@ -409,6 +439,10 @@ #define NV4_SOFTWARE_TEST (0x0000007d) // alias #endif +#ifndef NV30_GSYNC +#define NV30_GSYNC (0x000030f1) +#endif + #ifndef VOLTA_USERMODE_A #define VOLTA_USERMODE_A (0x0000c361) #endif @@ -501,6 +535,10 @@ #define NVC67E_WINDOW_CHANNEL_DMA (0x0000c67e) #endif +#ifndef NVC77F_ANY_CHANNEL_DMA +#define NVC77F_ANY_CHANNEL_DMA (0x0000c77f) +#endif + #ifndef NVC770_DISPLAY #define NVC770_DISPLAY (0x0000c770) #endif @@ -745,6 +783,10 @@ #define NV40_DEBUG_BUFFER (0x000000db) #endif +#ifndef RM_USER_SHARED_DATA +#define RM_USER_SHARED_DATA (0x000000de) +#endif + #ifndef GT200_DEBUGGER #define GT200_DEBUGGER (0x000083de) #endif @@ -753,6 +795,14 @@ #define NV40_I2C (0x0000402c) #endif +#ifndef NVA081_VGPU_CONFIG +#define NVA081_VGPU_CONFIG (0x0000a081) +#endif + +#ifndef NVA084_KERNEL_HOST_VGPU_DEVICE +#define NVA084_KERNEL_HOST_VGPU_DEVICE (0x0000a084) +#endif + #ifndef NV0060_SYNC_GPU_BOOST #define NV0060_SYNC_GPU_BOOST (0x00000060) #endif diff --git a/src/nvidia/generated/g_binary_api_nvoc.c b/src/nvidia/generated/g_binary_api_nvoc.c index d641c7e08..a8690b074 100644 --- a/src/nvidia/generated/g_binary_api_nvoc.c +++ b/src/nvidia/generated/g_binary_api_nvoc.c @@ -165,6 +165,10 @@ static NV_STATUS __nvoc_thunk_RsResource_binapiUnmapFrom(struct BinaryApi *pReso return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_binapiIsDuplicate(struct BinaryApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_binapiControl_Epilogue(struct BinaryApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RmResource.offset), pCallContext, pParams); } @@ -257,6 +261,8 @@ static void __nvoc_init_funcTable_BinaryApi_1(BinaryApi *pThis) { pThis->__binapiUnmapFrom__ = &__nvoc_thunk_RsResource_binapiUnmapFrom; + pThis->__binapiIsDuplicate__ = &__nvoc_thunk_RsResource_binapiIsDuplicate; + pThis->__binapiControl_Epilogue__ = &__nvoc_thunk_RmResource_binapiControl_Epilogue; pThis->__binapiControlLookup__ = &__nvoc_thunk_RsResource_binapiControlLookup; @@ -494,6 +500,10 @@ static NV_STATUS __nvoc_thunk_RsResource_binapiprivUnmapFrom(struct BinaryApiPri return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_binapiprivIsDuplicate(struct BinaryApiPrivileged *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_binapiprivControl_Epilogue(struct BinaryApiPrivileged *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RmResource.offset), pCallContext, pParams); } @@ -586,6 +596,8 @@ static void __nvoc_init_funcTable_BinaryApiPrivileged_1(BinaryApiPrivileged *pTh pThis->__binapiprivUnmapFrom__ = &__nvoc_thunk_RsResource_binapiprivUnmapFrom; + pThis->__binapiprivIsDuplicate__ = &__nvoc_thunk_RsResource_binapiprivIsDuplicate; + pThis->__binapiprivControl_Epilogue__ = &__nvoc_thunk_RmResource_binapiprivControl_Epilogue; pThis->__binapiprivControlLookup__ = &__nvoc_thunk_RsResource_binapiprivControlLookup; diff --git a/src/nvidia/generated/g_binary_api_nvoc.h b/src/nvidia/generated/g_binary_api_nvoc.h index c4758ca46..eb767006b 100644 --- a/src/nvidia/generated/g_binary_api_nvoc.h +++ b/src/nvidia/generated/g_binary_api_nvoc.h @@ -72,6 +72,7 @@ struct BinaryApi { NV_STATUS (*__binapiInternalControlForward__)(struct BinaryApi *, NvU32, void *, NvU32); void (*__binapiPreDestruct__)(struct BinaryApi *); NV_STATUS (*__binapiUnmapFrom__)(struct BinaryApi *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__binapiIsDuplicate__)(struct BinaryApi *, NvHandle, NvBool *); void (*__binapiControl_Epilogue__)(struct BinaryApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__binapiControlLookup__)(struct BinaryApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__binapiMap__)(struct BinaryApi *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -124,6 +125,7 @@ NV_STATUS __nvoc_objCreate_BinaryApi(BinaryApi**, Dynamic*, NvU32, struct CALL_C #define binapiInternalControlForward(pGpuResource, command, pParams, size) binapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define binapiPreDestruct(pResource) binapiPreDestruct_DISPATCH(pResource) #define binapiUnmapFrom(pResource, pParams) binapiUnmapFrom_DISPATCH(pResource, pParams) +#define binapiIsDuplicate(pResource, hMemory, pDuplicate) binapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define binapiControl_Epilogue(pResource, pCallContext, pParams) binapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define binapiControlLookup(pResource, pParams, ppEntry) binapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define binapiMap(pGpuResource, pCallContext, pParams, pCpuMapping) binapiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -202,6 +204,10 @@ static inline NV_STATUS binapiUnmapFrom_DISPATCH(struct BinaryApi *pResource, RS return pResource->__binapiUnmapFrom__(pResource, pParams); } +static inline NV_STATUS binapiIsDuplicate_DISPATCH(struct BinaryApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__binapiIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void binapiControl_Epilogue_DISPATCH(struct BinaryApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__binapiControl_Epilogue__(pResource, pCallContext, pParams); } @@ -219,6 +225,7 @@ static inline NvBool binapiAccessCallback_DISPATCH(struct BinaryApi *pResource, } NV_STATUS binapiConstruct_IMPL(struct BinaryApi *arg_pResource, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_binapiConstruct(arg_pResource, arg_pCallContext, arg_pParams) binapiConstruct_IMPL(arg_pResource, arg_pCallContext, arg_pParams) #undef PRIVATE_FIELD @@ -256,6 +263,7 @@ struct BinaryApiPrivileged { NV_STATUS (*__binapiprivInternalControlForward__)(struct BinaryApiPrivileged *, NvU32, void *, NvU32); void (*__binapiprivPreDestruct__)(struct BinaryApiPrivileged *); NV_STATUS (*__binapiprivUnmapFrom__)(struct BinaryApiPrivileged *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__binapiprivIsDuplicate__)(struct BinaryApiPrivileged *, NvHandle, NvBool *); void (*__binapiprivControl_Epilogue__)(struct BinaryApiPrivileged *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__binapiprivControlLookup__)(struct BinaryApiPrivileged *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__binapiprivMap__)(struct BinaryApiPrivileged *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -308,6 +316,7 @@ NV_STATUS __nvoc_objCreate_BinaryApiPrivileged(BinaryApiPrivileged**, Dynamic*, #define binapiprivInternalControlForward(pGpuResource, command, pParams, size) binapiprivInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define binapiprivPreDestruct(pResource) binapiprivPreDestruct_DISPATCH(pResource) #define binapiprivUnmapFrom(pResource, pParams) binapiprivUnmapFrom_DISPATCH(pResource, pParams) +#define binapiprivIsDuplicate(pResource, hMemory, pDuplicate) binapiprivIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define binapiprivControl_Epilogue(pResource, pCallContext, pParams) binapiprivControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define binapiprivControlLookup(pResource, pParams, ppEntry) binapiprivControlLookup_DISPATCH(pResource, pParams, ppEntry) #define binapiprivMap(pGpuResource, pCallContext, pParams, pCpuMapping) binapiprivMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -386,6 +395,10 @@ static inline NV_STATUS binapiprivUnmapFrom_DISPATCH(struct BinaryApiPrivileged return pResource->__binapiprivUnmapFrom__(pResource, pParams); } +static inline NV_STATUS binapiprivIsDuplicate_DISPATCH(struct BinaryApiPrivileged *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__binapiprivIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void binapiprivControl_Epilogue_DISPATCH(struct BinaryApiPrivileged *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__binapiprivControl_Epilogue__(pResource, pCallContext, pParams); } @@ -403,6 +416,7 @@ static inline NvBool binapiprivAccessCallback_DISPATCH(struct BinaryApiPrivilege } NV_STATUS binapiprivConstruct_IMPL(struct BinaryApiPrivileged *arg_pResource, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_binapiprivConstruct(arg_pResource, arg_pCallContext, arg_pParams) binapiprivConstruct_IMPL(arg_pResource, arg_pCallContext, arg_pParams) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_bindata.c b/src/nvidia/generated/g_bindata.c index adc1a985d..fcd1660a8 100644 --- a/src/nvidia/generated/g_bindata.c +++ b/src/nvidia/generated/g_bindata.c @@ -56,8 +56,8 @@ struct BINDATA_STORAGE_PVT_ALL #include "g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c" #include "g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c" #include "g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c" -#include "g_bindata_kgspGetBinArchiveGspRmCcGfwDebugSigned_GH100.c" -#include "g_bindata_kgspGetBinArchiveGspRmCcGfwProdSigned_GH100.c" +#include "g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c" +#include "g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c" @@ -84,8 +84,8 @@ struct BINDATA_STORAGE_PVT_ALL #include "g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c" #include "g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c" #include "g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c" -#include "g_bindata_kgspGetBinArchiveGspRmCcGfwDebugSigned_GH100.c" -#include "g_bindata_kgspGetBinArchiveGspRmCcGfwProdSigned_GH100.c" +#include "g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c" +#include "g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c" @@ -110,8 +110,8 @@ BINDATA_CONST struct BINDATA_STORAGE_PVT_ALL g_bindata_pvt = #include "g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c" #include "g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c" #include "g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c" -#include "g_bindata_kgspGetBinArchiveGspRmCcGfwDebugSigned_GH100.c" -#include "g_bindata_kgspGetBinArchiveGspRmCcGfwProdSigned_GH100.c" +#include "g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c" +#include "g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c" @@ -139,8 +139,8 @@ const NvU32 g_bindata_pvt_count = sizeof(g_bindata_pvt) / sizeof(BINDATA_STORAGE #include "g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c" #include "g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c" #include "g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c" -#include "g_bindata_kgspGetBinArchiveGspRmCcGfwDebugSigned_GH100.c" -#include "g_bindata_kgspGetBinArchiveGspRmCcGfwProdSigned_GH100.c" +#include "g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c" +#include "g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c" diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_AD102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_AD102.c index ca422b91b..f00b3cb1a 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_AD102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_AD102.c @@ -3237,6 +3237,14 @@ const BINDATA_ARCHIVE *kgspGetBinArchiveBooterLoadUcode_AD102(struct KernelGsp * #endif // defined(BINDATA_INCLUDE_FUNCTION) +#if defined(BINDATA_INCLUDE_FUNCTION_STUB) +const BINDATA_ARCHIVE *kgspGetBinArchiveBooterLoadUcode_AD102(struct KernelGsp *pKernelGsp) +{ + return NULL; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION_STUB) + + diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c index d8a6e50d3..9b221d6f8 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c @@ -3418,6 +3418,14 @@ const BINDATA_ARCHIVE *kgspGetBinArchiveBooterLoadUcode_GA100(struct KernelGsp * #endif // defined(BINDATA_INCLUDE_FUNCTION) +#if defined(BINDATA_INCLUDE_FUNCTION_STUB) +const BINDATA_ARCHIVE *kgspGetBinArchiveBooterLoadUcode_GA100(struct KernelGsp *pKernelGsp) +{ + return NULL; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION_STUB) + + diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c index f654ded1a..84ae32666 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c @@ -3614,6 +3614,14 @@ const BINDATA_ARCHIVE *kgspGetBinArchiveBooterLoadUcode_GA102(struct KernelGsp * #endif // defined(BINDATA_INCLUDE_FUNCTION) +#if defined(BINDATA_INCLUDE_FUNCTION_STUB) +const BINDATA_ARCHIVE *kgspGetBinArchiveBooterLoadUcode_GA102(struct KernelGsp *pKernelGsp) +{ + return NULL; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION_STUB) + + diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c index 919a574e7..e8e8183ce 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c @@ -3420,6 +3420,14 @@ const BINDATA_ARCHIVE *kgspGetBinArchiveBooterLoadUcode_TU102(struct KernelGsp * #endif // defined(BINDATA_INCLUDE_FUNCTION) +#if defined(BINDATA_INCLUDE_FUNCTION_STUB) +const BINDATA_ARCHIVE *kgspGetBinArchiveBooterLoadUcode_TU102(struct KernelGsp *pKernelGsp) +{ + return NULL; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION_STUB) + + diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c index 33f6f3531..2752bd7d0 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c @@ -3408,6 +3408,14 @@ const BINDATA_ARCHIVE *kgspGetBinArchiveBooterLoadUcode_TU116(struct KernelGsp * #endif // defined(BINDATA_INCLUDE_FUNCTION) +#if defined(BINDATA_INCLUDE_FUNCTION_STUB) +const BINDATA_ARCHIVE *kgspGetBinArchiveBooterLoadUcode_TU116(struct KernelGsp *pKernelGsp) +{ + return NULL; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION_STUB) + + diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c index 05fe73c52..2dac85e84 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c @@ -1364,6 +1364,14 @@ const BINDATA_ARCHIVE *kgspGetBinArchiveBooterUnloadUcode_AD102(struct KernelGsp #endif // defined(BINDATA_INCLUDE_FUNCTION) +#if defined(BINDATA_INCLUDE_FUNCTION_STUB) +const BINDATA_ARCHIVE *kgspGetBinArchiveBooterUnloadUcode_AD102(struct KernelGsp *pKernelGsp) +{ + return NULL; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION_STUB) + + diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c index 18b6d6a81..c7b34fba7 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c @@ -1270,6 +1270,14 @@ const BINDATA_ARCHIVE *kgspGetBinArchiveBooterUnloadUcode_GA100(struct KernelGsp #endif // defined(BINDATA_INCLUDE_FUNCTION) +#if defined(BINDATA_INCLUDE_FUNCTION_STUB) +const BINDATA_ARCHIVE *kgspGetBinArchiveBooterUnloadUcode_GA100(struct KernelGsp *pKernelGsp) +{ + return NULL; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION_STUB) + + diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c index f311434ef..896b27640 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c @@ -1359,6 +1359,14 @@ const BINDATA_ARCHIVE *kgspGetBinArchiveBooterUnloadUcode_GA102(struct KernelGsp #endif // defined(BINDATA_INCLUDE_FUNCTION) +#if defined(BINDATA_INCLUDE_FUNCTION_STUB) +const BINDATA_ARCHIVE *kgspGetBinArchiveBooterUnloadUcode_GA102(struct KernelGsp *pKernelGsp) +{ + return NULL; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION_STUB) + + diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU102.c index 723f63e70..8d151f7bb 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU102.c @@ -1216,6 +1216,14 @@ const BINDATA_ARCHIVE *kgspGetBinArchiveBooterUnloadUcode_TU102(struct KernelGsp #endif // defined(BINDATA_INCLUDE_FUNCTION) +#if defined(BINDATA_INCLUDE_FUNCTION_STUB) +const BINDATA_ARCHIVE *kgspGetBinArchiveBooterUnloadUcode_TU102(struct KernelGsp *pKernelGsp) +{ + return NULL; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION_STUB) + + diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU116.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU116.c index 9501f9f42..759da2dc6 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU116.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU116.c @@ -1216,6 +1216,14 @@ const BINDATA_ARCHIVE *kgspGetBinArchiveBooterUnloadUcode_TU116(struct KernelGsp #endif // defined(BINDATA_INCLUDE_FUNCTION) +#if defined(BINDATA_INCLUDE_FUNCTION_STUB) +const BINDATA_ARCHIVE *kgspGetBinArchiveBooterUnloadUcode_TU116(struct KernelGsp *pKernelGsp) +{ + return NULL; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION_STUB) + + diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c index f70694604..4b54971d3 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c @@ -29,475 +29,1867 @@ #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmBoot_AD102("ucode_image_dbg") -// FILE NAME: kernel/inc/gsprm/bin/g_gsprm_skbl_dbg_ad102_riscv_image.bin +// FILE NAME: kernel/inc/gsprm/bin/g_gsprm_skbl_dbg_libos3_ad102_riscv_image.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 12288 -// COMPRESSED SIZE (bytes): 7342 +// DATA SIZE (bytes): 32768 +// COMPRESSED SIZE (bytes): 29603 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_AD102_ucode_image_dbg_data[] = { - 0xed, 0x97, 0x65, 0x54, 0x94, 0x6d, 0xd7, 0xf7, 0x67, 0x88, 0x19, 0x40, 0x3a, 0x87, 0x90, 0xee, - 0xee, 0x96, 0x90, 0x4e, 0xe9, 0x46, 0x62, 0x84, 0x01, 0x24, 0x86, 0x46, 0xba, 0x07, 0x04, 0xa9, - 0xa1, 0x1b, 0x44, 0x5a, 0xa5, 0x43, 0xe9, 0x46, 0x10, 0x91, 0xe6, 0xa2, 0x1b, 0x04, 0xa5, 0x91, - 0x10, 0x78, 0xf4, 0x82, 0xfb, 0x7e, 0x9e, 0x8f, 0xef, 0xf7, 0xd7, 0xff, 0x5a, 0xb3, 0x7e, 0x73, - 0xee, 0xbd, 0xcf, 0x63, 0x1f, 0x7b, 0xaf, 0x7d, 0x1c, 0x6b, 0xc6, 0x75, 0x57, 0x53, 0x68, 0x00, - 0x59, 0xbd, 0xb2, 0xf1, 0x4c, 0xc6, 0xe4, 0xe3, 0xf7, 0xf6, 0xe0, 0x71, 0x3d, 0xeb, 0x61, 0x2a, - 0x6a, 0x69, 0xbf, 0xca, 0xe4, 0xf8, 0xa6, 0x5a, 0xf7, 0x82, 0xa4, 0xd7, 0xd8, 0xfb, 0xc4, 0xc2, - 0x35, 0x44, 0x62, 0x2d, 0xef, 0x3f, 0xe1, 0xbe, 0xd7, 0x8a, 0xbf, 0xe5, 0x2e, 0x0e, 0x3f, 0x8f, - 0x10, 0xe0, 0x64, 0x3b, 0x16, 0xb3, 0x9f, 0xa1, 0x07, 0x35, 0xce, 0x7d, 0x14, 0x91, 0x58, 0xe2, - 0xd0, 0xaa, 0xba, 0x7a, 0x23, 0x54, 0x75, 0xd0, 0x30, 0x23, 0xe6, 0xd6, 0x4b, 0x7b, 0xb9, 0xdc, - 0xf8, 0xd4, 0x3e, 0x79, 0xd2, 0xa3, 0x9b, 0xfe, 0x8c, 0xba, 0x91, 0x43, 0x22, 0x0c, 0x82, 0x75, - 0xd4, 0x69, 0x9a, 0xd5, 0x3f, 0xf0, 0x4d, 0xe5, 0xb1, 0x76, 0x9c, 0xc9, 0x3f, 0x93, 0x9a, 0x5f, - 0xfa, 0x45, 0x55, 0xb8, 0xb9, 0xdb, 0xdd, 0xb0, 0x71, 0x74, 0x66, 0x70, 0x85, 0x43, 0x30, 0x40, - 0x49, 0x4a, 0xa7, 0x4e, 0x65, 0x9f, 0xcf, 0x4d, 0x93, 0xec, 0x1a, 0x4e, 0xb1, 0x85, 0xcc, 0x9e, - 0x0f, 0x93, 0x4a, 0xa1, 0xf9, 0xe7, 0x2e, 0x49, 0xa3, 0x18, 0xa1, 0x8d, 0x4f, 0x0c, 0xbb, 0x8b, - 0xc9, 0xb6, 0x68, 0x46, 0x2c, 0x2b, 0x8a, 0xef, 0x85, 0x00, 0xe7, 0xfb, 0x78, 0x34, 0xdd, 0x15, - 0x93, 0xa8, 0x52, 0xdb, 0x5a, 0x20, 0x41, 0xa3, 0xa7, 0x9b, 0xae, 0x93, 0xef, 0x46, 0x31, 0xfd, - 0xc4, 0xba, 0xdb, 0x05, 0x19, 0x43, 0xd1, 0xa3, 0x58, 0x2c, 0xf7, 0x66, 0x46, 0x35, 0x25, 0xcc, - 0xb2, 0x47, 0x3d, 0xdd, 0x94, 0x76, 0x56, 0xc2, 0x0d, 0x7a, 0xb3, 0x8e, 0x30, 0xcb, 0x9f, 0x4d, - 0x7d, 0x9d, 0xe6, 0x95, 0x5d, 0x99, 0x2d, 0x76, 0xb7, 0xa3, 0xc9, 0x1d, 0x75, 0x92, 0x94, 0x0b, - 0x16, 0xdd, 0x6a, 0x4f, 0x1d, 0xb2, 0x40, 0x8c, 0x11, 0x9a, 0xb0, 0x3f, 0xab, 0xc9, 0x4d, 0xf6, - 0x74, 0x15, 0x29, 0xf2, 0x9b, 0xfc, 0x59, 0x38, 0xcc, 0x6b, 0x7e, 0x6c, 0xcb, 0xf8, 0xdd, 0xdf, - 0x31, 0x34, 0xe1, 0x15, 0x76, 0xda, 0x27, 0x66, 0x57, 0x47, 0x3d, 0x47, 0xbc, 0x27, 0x32, 0xbe, - 0x8f, 0x77, 0xbc, 0x04, 0xec, 0xdb, 0x33, 0xca, 0x71, 0x1f, 0x99, 0x2a, 0xd0, 0x08, 0x09, 0xa9, - 0xac, 0xde, 0x94, 0x48, 0x38, 0xe4, 0x69, 0x47, 0xff, 0x6a, 0x2e, 0x05, 0x39, 0x1a, 0xa5, 0x59, - 0x75, 0xc5, 0x23, 0x0b, 0xa8, 0x3b, 0x04, 0x29, 0x39, 0x29, 0x04, 0xf8, 0xd2, 0xbf, 0x2c, 0xf1, - 0x63, 0x9f, 0xd1, 0x66, 0x7b, 0xc4, 0x79, 0x5d, 0xd5, 0x0b, 0x36, 0xc8, 0xf1, 0x79, 0xfe, 0x48, - 0xe0, 0x30, 0x5c, 0x0f, 0x02, 0xcc, 0xcd, 0x66, 0x66, 0x52, 0x78, 0x97, 0x9e, 0xf6, 0xb3, 0x84, - 0x3c, 0x54, 0x67, 0xa0, 0x58, 0x1a, 0x6f, 0xdb, 0x41, 0x29, 0xaa, 0x56, 0x40, 0x1d, 0x5b, 0x69, - 0xfa, 0xa6, 0x86, 0xf9, 0xde, 0x29, 0x0e, 0x1e, 0x24, 0x33, 0x6d, 0xf7, 0x7c, 0xae, 0x21, 0x22, - 0xc0, 0x06, 0xf7, 0x11, 0xef, 0xae, 0xb4, 0xd1, 0x15, 0x87, 0xbc, 0x5c, 0x1d, 0xca, 0xfb, 0x57, - 0xde, 0x5b, 0x95, 0x2b, 0xb1, 0x40, 0x7d, 0xee, 0x38, 0x93, 0xfd, 0x68, 0x3f, 0x5d, 0x93, 0xd5, - 0xae, 0x9b, 0xb0, 0x83, 0x4d, 0x24, 0x5d, 0x96, 0xca, 0x83, 0x80, 0x5a, 0xdb, 0x4c, 0xf8, 0x73, - 0xc7, 0x33, 0xa7, 0x86, 0xb7, 0x1d, 0xdc, 0x40, 0x2e, 0x2a, 0x29, 0xaa, 0x83, 0x96, 0x9e, 0x07, - 0xe6, 0xd7, 0x52, 0xb8, 0x24, 0xb9, 0x14, 0xf4, 0x4f, 0xd1, 0x5b, 0x34, 0xcd, 0x2f, 0x0e, 0x78, - 0x06, 0xc8, 0x0d, 0x46, 0x8a, 0x19, 0xde, 0x43, 0x07, 0xeb, 0x4a, 0x5f, 0xec, 0xf0, 0xed, 0x2e, - 0xf6, 0x50, 0xab, 0x39, 0xd8, 0x93, 0x76, 0xb0, 0xb0, 0x04, 0x78, 0x81, 0x06, 0x9c, 0x23, 0x64, - 0x10, 0x27, 0x0f, 0x0f, 0x29, 0xfa, 0xc7, 0x4a, 0x2f, 0x3f, 0x32, 0xf3, 0x6a, 0xc9, 0x92, 0x5f, - 0xfb, 0x8b, 0x4f, 0x5a, 0xef, 0xf0, 0x09, 0xdb, 0xdc, 0x90, 0x10, 0x58, 0x0d, 0xa5, 0x68, 0x3f, - 0x28, 0xa2, 0x2f, 0x73, 0x61, 0xe4, 0x60, 0x6c, 0x2f, 0x50, 0x39, 0xf6, 0xe7, 0x94, 0x85, 0x21, - 0x2f, 0x73, 0x4a, 0x50, 0x3f, 0x48, 0x9a, 0x7b, 0xa1, 0x17, 0x3f, 0x37, 0xac, 0x32, 0x12, 0x92, - 0x11, 0x90, 0x02, 0xa9, 0x33, 0xe8, 0xd1, 0xda, 0xc1, 0x7e, 0x2d, 0x32, 0x63, 0xe2, 0x0f, 0x3c, - 0x86, 0x91, 0x85, 0xe2, 0x0e, 0x84, 0xce, 0x5a, 0xd0, 0x5f, 0xe5, 0x79, 0x16, 0xf2, 0x5b, 0xbf, - 0xb7, 0x17, 0x19, 0xd4, 0x3d, 0xc0, 0x63, 0x7b, 0xeb, 0x46, 0xe5, 0xa5, 0xdf, 0x6f, 0x85, 0xf6, - 0xe4, 0x46, 0xab, 0xa1, 0x3c, 0x40, 0x64, 0x0e, 0x93, 0xb1, 0xac, 0x62, 0x1f, 0xe7, 0xf5, 0x3b, - 0x06, 0xf2, 0xee, 0x86, 0xdd, 0x7d, 0x01, 0x24, 0xc0, 0x8e, 0x15, 0x8f, 0xff, 0x15, 0xee, 0x40, - 0xa1, 0xd3, 0x21, 0x90, 0x9e, 0x8f, 0x80, 0x2f, 0x3b, 0x7d, 0xf3, 0x31, 0x9f, 0x16, 0xed, 0x0a, - 0x9d, 0x35, 0x3b, 0x6d, 0x0a, 0xbd, 0xbe, 0x5a, 0xcf, 0x89, 0xec, 0x3c, 0x8d, 0x72, 0x74, 0xe7, - 0x07, 0x46, 0xbe, 0x25, 0x1d, 0xe5, 0x83, 0x45, 0xb2, 0x4d, 0x17, 0x82, 0x5c, 0xb8, 0xaf, 0x0d, - 0x9e, 0x52, 0x4b, 0x61, 0xe1, 0xa4, 0x8f, 0x8c, 0xc2, 0xcb, 0x12, 0x9b, 0x70, 0x1b, 0xdc, 0x5a, - 0x31, 0x6c, 0x92, 0x9d, 0x22, 0x4d, 0xd3, 0x33, 0xa5, 0x6b, 0xb1, 0x94, 0xb4, 0x8e, 0x12, 0x84, - 0xe1, 0xea, 0xa2, 0x49, 0x91, 0x3c, 0xd9, 0x99, 0x4f, 0x53, 0xc4, 0xd5, 0x9e, 0xba, 0x99, 0x58, - 0x27, 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0xb1, 0x8a, 0x71, 0xfc, 0xc5, 0x8a, 0xf2, 0x5f, 0xac, 0xff, 0xd4, 0x8e, 0xe2, 0x7f, 0x59, + 0x0f, 0x5b, 0x9a, 0x21, 0xe7, 0x21, 0xda, 0x5f, 0x3a, 0x12, 0x78, 0x28, 0x0d, 0xba, 0x21, 0x11, + 0x3e, 0x38, 0xc0, 0xdf, 0x16, 0xd9, 0x5f, 0x56, 0x22, 0x18, 0x00, 0x24, 0xf2, 0xe0, 0xdf, 0x76, + 0x29, 0xf5, 0xbf, 0x6c, 0x7e, 0x84, 0xff, 0xb2, 0xc9, 0xfe, 0xb2, 0x93, 0x45, 0x91, 0x07, 0x09, + 0x4d, 0xff, 0x4f, 0x06, 0x3d, 0xa2, 0xff, 0x61, 0x20, 0x63, 0xf8, 0xd7, 0x9a, 0x12, 0x53, 0x41, + 0x81, 0xfc, 0x13, 0x99, 0x4e, 0x4b, 0x01, 0x12, 0xd1, 0xc0, 0xfe, 0xd2, 0x1a, 0x4f, 0xc0, 0x01, + 0x13, 0x5f, 0x5e, 0xe0, 0xda, 0x0f, 0x12, 0xd5, 0x82, 0x01, 0xfc, 0xc9, 0xd0, 0x20, 0xfe, 0xca, + 0x09, 0x61, 0x46, 0x06, 0xcc, 0x0e, 0x01, 0x40, 0x84, 0xff, 0x0a, 0x40, 0x10, 0xff, 0xcf, 0xb9, + 0x22, 0xcd, 0x32, 0x0c, 0x1b, 0xcc, 0x4c, 0x1d, 0x01, 0xc8, 0x36, 0x79, 0x8a, 0xed, 0x37, 0x49, + 0x0c, 0x01, 0xd3, 0xdb, 0x8a, 0x01, 0x8d, 0x84, 0x1c, 0xfd, 0xb7, 0x6e, 0xb0, 0x15, 0x03, 0x28, + 0x46, 0x53, 0xf6, 0x37, 0x2b, 0xff, 0xec, 0xdf, 0x31, 0xa1, 0xc4, 0x59, 0x86, 0x51, 0x83, 0xff, + 0xf4, 0xdb, 0x5f, 0x7a, 0xda, 0x3f, 0x7a, 0x28, 0x61, 0x96, 0x61, 0xd2, 0x60, 0x66, 0x30, 0x28, + 0x3c, 0x16, 0x38, 0x38, 0x3c, 0x16, 0x18, 0xd8, 0x2d, 0xc2, 0xc4, 0x3f, 0xfd, 0x80, 0xff, 0x77, + 0xff, 0x5d, 0x7d, 0x78, 0xf7, 0xfe, 0x77, 0xbd, 0x48, 0xfe, 0xcf, 0x75, 0xed, 0xa2, 0xfc, 0xcf, + 0xba, 0x4a, 0x89, 0xfe, 0xa7, 0xab, 0x4f, 0xb0, 0xff, 0xee, 0xea, 0xf0, 0xc8, 0xa3, 0x3f, 0xff, + 0xf0, 0xe2, 0xfc, 0x7d, 0xe2, 0xc9, 0x00, 0x82, 0x23, 0xfd, 0x6f, 0xfe, 0xbb, 0x9f, 0xff, 0xe2, + 0x31, 0xc4, 0xf8, 0xdf, 0x72, 0xfe, 0xd3, 0x81, 0xf8, 0xf0, 0x1c, 0xf6, 0x60, 0x9f, 0x7f, 0xfb, + 0x9d, 0xfc, 0x15, 0xcd, 0xfb, 0x88, 0x0c, 0xc1, 0x23, 0xf6, 0x4f, 0x7e, 0xf4, 0xff, 0x59, 0x45, + 0xe9, 0x5f, 0x3a, 0x1b, 0x38, 0x1c, 0xc0, 0x7f, 0xd9, 0x64, 0xe8, 0x69, 0x86, 0xd9, 0xa6, 0x99, + 0xa1, 0xe0, 0x76, 0xd8, 0xff, 0xb5, 0x4e, 0xb4, 0x2c, 0x43, 0x50, 0xd3, 0xb4, 0x41, 0x36, 0xf0, + 0xd3, 0x1f, 0x96, 0xdc, 0x7f, 0xf6, 0x11, 0xf5, 0x7f, 0xd9, 0x87, 0xbf, 0x74, 0x24, 0x30, 0x00, + 0xd4, 0xb8, 0x41, 0xb6, 0x10, 0x10, 0xf8, 0x7f, 0x5d, 0x81, 0xff, 0xba, 0xfe, 0x33, 0x6f, 0x94, + 0xff, 0xda, 0x89, 0x7f, 0xe2, 0x90, 0xfe, 0x62, 0x0b, 0x51, 0xa6, 0xfe, 0xb7, 0xaf, 0xf0, 0xbf, + 0xae, 0x4c, 0xf2, 0x71, 0x83, 0x68, 0x7f, 0x75, 0x24, 0x12, 0x58, 0x08, 0x02, 0xbc, 0x01, 0xfa, + 0x00, 0x12, 0x38, 0x00, 0xcc, 0x7f, 0x65, 0x36, 0x45, 0xf8, 0xbf, 0x47, 0x9f, 0xc0, 0x66, 0x19, + 0x12, 0xe5, 0x81, 0x03, 0x84, 0x19, 0x10, 0xba, 0xfe, 0x73, 0xde, 0xe0, 0xff, 0xd9, 0x55, 0x3b, + 0x82, 0xff, 0x39, 0x8f, 0xff, 0x6b, 0x7f, 0xc1, 0xfe, 0x7b, 0x57, 0xff, 0xae, 0x67, 0x03, 0x04, + 0x08, 0xc2, 0xbf, 0x1e, 0xab, 0xf8, 0xcc, 0x20, 0x01, 0xff, 0x46, 0x3d, 0xd4, 0xbf, 0xed, 0x57, + 0xbf, 0xbf, 0x91, 0xb8, 0x0c, 0xef, 0xdf, 0x48, 0xfe, 0x0f, 0xe6, 0xfd, 0x23, 0x8d, 0x7a, 0x98, + 0x6c, 0x04, 0x35, 0x9c, 0x9b, 0x30, 0x80, 0xff, 0xf8, 0x81, 0xfd, 0x8d, 0x20, 0xff, 0x20, 0xc4, + 0x3f, 0x08, 0xff, 0xcf, 0x38, 0xf9, 0x3f, 0x88, 0xfe, 0x0f, 0x22, 0xff, 0x83, 0xd8, 0xff, 0xe0, + 0x2e, 0xd0, 0xdf, 0x08, 0x00, 0xfa, 0x4f, 0x9e, 0x7f, 0x90, 0xfa, 0xbf, 0xec, 0x7f, 0xe6, 0x69, + 0x87, 0xf2, 0x37, 0x3a, 0xfd, 0x83, 0x6e, 0xff, 0xe0, 0x7f, 0xbf, 0x20, 0x84, 0xd1, 0xff, 0x0d, + 0x41, 0x00, 0xf0, 0xff, 0xc6, 0x9f, 0x7f, 0xe4, 0xbf, 0xc7, 0xfd, 0xfe, 0xf9, 0xfd, 0x25, 0x75, + 0x90, 0xff, 0xaf, 0x5e, 0x39, 0xff, 0x91, 0xff, 0xc8, 0x7f, 0xe4, 0x3f, 0xf2, 0x1f, 0xf9, 0x8f, + 0xfc, 0x47, 0xfe, 0x23, 0xff, 0x91, 0xff, 0x0f, 0xe5, 0xff, 0x02, 0x92, 0x1b, 0x75, 0x0b, 0x00, + 0x80, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -507,8 +1899,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_AD102_ucode_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 12288, // uncompressed data size (bytes) - 7342, // compressed data size (bytes) + 32768, // uncompressed data size (bytes) + 29603, // compressed data size (bytes) kgspBinArchiveGspRmBoot_AD102_ucode_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -520,7 +1912,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_AD102_ucode_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmBoot_AD102("ucode_desc_dbg") -// FILE NAME: kernel/inc/gsprm/bin/g_gsprm_skbl_dbg_ad102_riscv_desc.bin +// FILE NAME: kernel/inc/gsprm/bin/g_gsprm_skbl_dbg_libos3_ad102_riscv_desc.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES @@ -530,9 +1922,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_AD102_ucode_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_AD102_ucode_desc_dbg_data[] = { - 0x63, 0x65, 0x00, 0x02, 0x05, 0x06, 0x86, 0x0d, 0xac, 0x40, 0xac, 0xca, 0xc0, 0x20, 0xc0, 0x80, - 0x05, 0x70, 0x40, 0x31, 0x33, 0x10, 0x73, 0x03, 0x31, 0x2f, 0x03, 0x03, 0x23, 0x36, 0x75, 0x06, - 0x10, 0x41, 0x00, 0x42, 0x1a, 0xfd, 0xdc, 0x54, 0x00, 0x00, 0x00, + 0x63, 0x65, 0x00, 0x82, 0x02, 0x06, 0x06, 0x07, 0x36, 0x20, 0x2e, 0x63, 0x60, 0x10, 0x60, 0xc0, + 0x02, 0x38, 0xa0, 0xd8, 0x01, 0x88, 0x3d, 0x80, 0x58, 0x9d, 0x81, 0x81, 0x11, 0x9b, 0xba, 0x06, + 0x88, 0x20, 0x00, 0x3c, 0xec, 0x41, 0xdd, 0x54, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -555,475 +1947,1867 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_AD102_ucode_desc_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmBoot_AD102("ucode_image_prod") -// FILE NAME: kernel/inc/gsprm/bin/g_gsprm_skbl_prod_ad102_riscv_image.bin +// FILE NAME: kernel/inc/gsprm/bin/g_gsprm_skbl_prod_libos3_ad102_riscv_image.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 12288 -// COMPRESSED SIZE (bytes): 7340 +// DATA SIZE (bytes): 32768 +// COMPRESSED SIZE (bytes): 29603 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_AD102_ucode_image_prod_data[] = { - 0xed, 0x94, 0x75, 0x54, 0xd4, 0x5d, 0xb7, 0xc7, 0x87, 0x9a, 0x01, 0x09, 0xe9, 0x19, 0x87, 0x90, - 0x1e, 0xba, 0x4b, 0x4a, 0xba, 0x91, 0x92, 0x6e, 0x86, 0x50, 0x1a, 0x14, 0x24, 0x14, 0xe9, 0xee, - 0x94, 0x92, 0xee, 0x16, 0xa4, 0x11, 0x18, 0xba, 0xa5, 0x43, 0xba, 0x91, 0x41, 0x09, 0x29, 0x25, - 0xae, 0x3e, 0xf0, 0xbc, 0xf7, 0xfd, 0xf3, 0xfe, 0x7f, 0xfd, 0xae, 0x35, 0xeb, 0x33, 0x67, 0xef, - 0xfd, 0x3b, 0xfb, 0xec, 0xbd, 0xf6, 0x39, 0x5d, 0xbb, 0x52, 0x5d, 0xed, 0x7d, 0x8f, 0xca, 0x4d, - 0xcc, 0xcb, 0x60, 0x06, 0x08, 0x4e, 0x84, 0xfe, 0x55, 0x22, 0xbb, 0xe4, 0x4c, 0xc1, 0xf3, 0x10, - 0x78, 0xca, 0xf8, 0xe4, 0x2a, 0xea, 0x90, 0xed, 0xbc, 0x7f, 0xc0, 0x5e, 0xc3, 0x4d, 0x00, 0x75, - 0x9e, 0xac, 0xba, 0xb6, 0x6d, 0x3b, 0x1b, 0x3d, 0xca, 0x93, 0xb8, 0x6f, 0xc1, 0x2b, 0x0d, 0x44, - 0xb5, 0x1f, 0x3c, 0x9c, 0xe6, 0x9b, 0x19, 0xea, 0x1c, 0xbb, 0x54, 0x30, 0x98, 0xaa, 0x15, 0x12, - 0x9e, 0xa9, 0xd5, 0x8c, 0x5c, 0x2a, 0x5f, 0x32, 0xb9, 0xc2, 0x98, 0xa0, 0xd1, 0x38, 0xa7, 0x18, - 0x8e, 0x40, 0x8e, 0xef, 0x19, 0x6f, 0xde, 0xda, 0xd2, 0xe7, 0x71, 0xd0, 0x3f, 0x66, 0x6a, 0x71, - 0xe8, 0x9a, 0x98, 0x2a, 0xec, 0x89, 0xe3, 0x63, 0xfe, 0x45, 0xdd, 0x79, 0x34, 0x86, 0x64, 0x52, - 0x8b, 0x7c, 0xab, 0x65, 0xc0, 0x9b, 0xd2, 0x85, 0x37, 0xe2, 0xad, 0xbf, 0x7a, 0xf1, 0x8b, 0x92, - 0x71, 0x14, 0xdd, 0x43, 0x9f, 0x4b, 0x1e, 0x81, 0x86, 0xf5, 0x83, 0xa1, 0x9c, 0xdb, 0xb3, 0x6c, - 0xc5, 0xe4, 0x27, 0xf3, 0xe7, 0x70, 0x8f, 0x03, 0x63, 0x6e, 0xd4, 0xa3, 0xaf, 0x64, 0x0f, 0xa5, - 0xcf, 0x26, 0x19, 0xbb, 0xb2, 0xd0, 0xb7, 0xf6, 0x69, 0x06, 0xe4, 0x75, 0x5d, 0xa0, 0xd7, 0x03, - 0xdf, 0xd8, 0x25, 0xa1, 0x36, 0x17, 0x98, 0xf4, 0x8b, 0x20, 0x34, 0xfa, 0xd9, 0x08, 0x14, 0x96, - 0xc6, 0xe7, 0x93, 0x8f, 0x9c, 0x68, 0x8b, 0x4e, 0x5f, 0x1a, 0xba, 0xd3, 0xe7, 0xbc, 0xa2, 0xf6, - 0xe0, 0x23, 0x71, 0xfd, 0x16, 0xdb, 0xf5, 0xe3, 0x47, 0x0a, 0x0e, 0x4d, 0xbd, 0x75, 0x94, 0x60, - 0x49, 0xd2, 0x07, 0xaa, 0xfe, 0x3e, 0x28, 0x2c, 0xaa, 0xa6, 0x72, 0x9e, 0x9a, 0x85, 0x0e, 0x8f, - 0xef, 0x0a, 0xcd, 0x09, 0x53, 0xe4, 0xa1, 0x32, 0x3a, 0x8a, 0x66, 0xf8, 0xb8, 0xca, 0x4f, 0x98, - 0xb1, 0xd4, 0x37, 0x53, 0xb4, 0xa9, 0x78, 0xb8, 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0x38, 0xe7, 0x5f, 0xac, 0xa8, 0xff, 0xc5, 0xfa, 0x4f, 0xee, 0x28, 0xff, 0x97, + 0xf5, 0xb0, 0xa7, 0x1a, 0x72, 0x1d, 0xa2, 0xff, 0xa5, 0x23, 0x83, 0x87, 0xd0, 0x62, 0x18, 0x12, + 0x13, 0x80, 0x03, 0xfc, 0x6d, 0x91, 0xff, 0x65, 0x25, 0x80, 0x01, 0x40, 0xa2, 0x0c, 0xfc, 0x6d, + 0x97, 0xd0, 0xfc, 0xcb, 0x16, 0x40, 0xfc, 0x2f, 0x9b, 0xfc, 0x2f, 0x3b, 0x49, 0x0c, 0x65, 0x80, + 0xc8, 0xf4, 0xff, 0x64, 0xd0, 0x23, 0xfe, 0x1f, 0x06, 0x72, 0xc6, 0x7f, 0xad, 0x29, 0x21, 0x05, + 0x14, 0xc8, 0x2f, 0x81, 0xf9, 0xb4, 0x04, 0x20, 0x01, 0x1d, 0xec, 0x2f, 0xad, 0xe1, 0x04, 0x1c, + 0x30, 0xe1, 0xe5, 0x05, 0xbe, 0xed, 0x20, 0x41, 0x2d, 0x08, 0xc0, 0x8f, 0x1c, 0x1d, 0xe2, 0x2f, + 0x9f, 0x10, 0x66, 0xe4, 0xc0, 0x1c, 0x10, 0x00, 0xc4, 0x04, 0xaf, 0x00, 0x84, 0x71, 0xff, 0xec, + 0x2b, 0xb2, 0x4c, 0xc3, 0xd0, 0x81, 0x8c, 0x94, 0x61, 0x80, 0x2c, 0x93, 0xa7, 0x98, 0x3e, 0x93, + 0x84, 0x60, 0x30, 0xbd, 0xad, 0x68, 0xd0, 0x08, 0xc8, 0x91, 0x7f, 0xeb, 0x06, 0x5b, 0xd1, 0x80, + 0xe2, 0xb4, 0xa5, 0x7f, 0xb3, 0x0a, 0xcc, 0xfc, 0x3d, 0x26, 0x84, 0x24, 0xd3, 0x30, 0x72, 0xe0, + 0x9f, 0x7a, 0xfb, 0x4b, 0x4f, 0xfd, 0x47, 0x0f, 0x21, 0xca, 0x34, 0x4c, 0x1c, 0xc8, 0x08, 0x02, + 0x45, 0xc0, 0x06, 0x07, 0x47, 0xc0, 0x06, 0x03, 0xbb, 0x45, 0x1c, 0xff, 0xa7, 0x1e, 0x08, 0xfe, + 0xae, 0xbf, 0xab, 0x0f, 0xaf, 0x9e, 0xff, 0xce, 0x17, 0xe9, 0xff, 0xb9, 0xae, 0x5d, 0xd4, 0xff, + 0x59, 0x57, 0x09, 0xf1, 0xff, 0x54, 0xf5, 0x09, 0xce, 0xdf, 0x55, 0x1d, 0x16, 0x71, 0xb4, 0xf1, + 0x0f, 0x2f, 0xee, 0xdf, 0x3b, 0x9e, 0x1c, 0x20, 0x28, 0xc2, 0xef, 0xe6, 0xbf, 0xeb, 0xf9, 0x2f, + 0x1e, 0x43, 0xcc, 0xff, 0xcd, 0xe7, 0x3f, 0x15, 0x48, 0x80, 0xc0, 0x69, 0x0f, 0xf6, 0xf9, 0x77, + 0xbf, 0x93, 0xbf, 0x46, 0xf3, 0x3d, 0xa2, 0x40, 0xf0, 0x8a, 0xff, 0xe3, 0x1f, 0xe3, 0x7f, 0x56, + 0x51, 0xf2, 0x97, 0xce, 0x0e, 0x0e, 0x0f, 0xf0, 0x5f, 0x36, 0x39, 0x46, 0xaa, 0x61, 0x96, 0x69, + 0x46, 0x08, 0xb8, 0x1d, 0xce, 0x7f, 0xad, 0x13, 0x3d, 0xd3, 0x10, 0xd4, 0x34, 0x75, 0x80, 0x1d, + 0xfc, 0xf4, 0x87, 0x35, 0xe7, 0x9f, 0x38, 0xa2, 0xfd, 0x2f, 0x71, 0xf8, 0x4b, 0x47, 0x06, 0x03, + 0x40, 0x8b, 0x1d, 0x60, 0x0f, 0x06, 0x41, 0xf8, 0xd7, 0x15, 0xf8, 0xaf, 0xeb, 0x3f, 0xf3, 0x46, + 0xfd, 0xaf, 0x48, 0xfc, 0x33, 0x0e, 0xf9, 0x2f, 0xb6, 0x60, 0x65, 0x9a, 0x7f, 0xf7, 0x15, 0xf9, + 0xd7, 0x95, 0x59, 0x3e, 0x76, 0x00, 0xfd, 0xaf, 0x8a, 0x44, 0x06, 0x0b, 0x46, 0x44, 0x30, 0xc0, + 0xe8, 0x47, 0x06, 0x07, 0x80, 0xf9, 0x2f, 0xcf, 0xa6, 0x88, 0xff, 0xf7, 0xd1, 0x27, 0x70, 0x99, + 0x86, 0xc4, 0xb9, 0xe0, 0x00, 0xa1, 0x06, 0x44, 0xae, 0xff, 0xec, 0x37, 0x84, 0x7f, 0xa2, 0x6a, + 0x47, 0xf8, 0x3f, 0xfb, 0xf1, 0x7f, 0xad, 0x2f, 0xb8, 0x7f, 0x47, 0xf5, 0xef, 0x7c, 0xd6, 0x43, + 0x80, 0x20, 0xfe, 0xeb, 0xb1, 0x4a, 0xc0, 0x02, 0xe2, 0xff, 0x6f, 0xd4, 0x43, 0xfb, 0xdb, 0x7e, + 0xf5, 0xfd, 0x1b, 0x49, 0x4a, 0xf1, 0xff, 0x8d, 0x14, 0xff, 0x60, 0xee, 0x3f, 0xd2, 0xa0, 0x87, + 0xc5, 0x4e, 0x58, 0xcd, 0xb5, 0x09, 0x03, 0xf8, 0x4f, 0x3f, 0xb0, 0xbf, 0x11, 0xe4, 0x1f, 0x84, + 0xf8, 0x07, 0x11, 0xfe, 0x69, 0xa7, 0xf8, 0x07, 0x31, 0xfe, 0x41, 0x94, 0x7f, 0x10, 0xe7, 0x1f, + 0xdc, 0x05, 0xfa, 0x1b, 0x01, 0x40, 0xff, 0xf1, 0xf3, 0x0f, 0xd2, 0xfc, 0x97, 0xfd, 0xcf, 0x3c, + 0xed, 0x50, 0xff, 0x46, 0xa7, 0x7f, 0xd0, 0xed, 0x1f, 0xfc, 0xef, 0x03, 0x42, 0x04, 0xe3, 0xdf, + 0x10, 0x08, 0x80, 0xf0, 0x6f, 0xfc, 0xf9, 0x47, 0xfe, 0xbb, 0xdd, 0xf7, 0x9f, 0xdf, 0x5f, 0x52, + 0x0b, 0xf9, 0xff, 0xea, 0xc8, 0xf9, 0x8f, 0xfc, 0x47, 0xfe, 0x23, 0xff, 0x91, 0xff, 0xc8, 0x7f, + 0xe4, 0x3f, 0xf2, 0x1f, 0xf9, 0x8f, 0xfc, 0x7f, 0x28, 0xff, 0x17, 0x68, 0x41, 0x13, 0xc2, 0x00, + 0x80, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1033,8 +3817,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_AD102_ucode_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 12288, // uncompressed data size (bytes) - 7340, // compressed data size (bytes) + 32768, // uncompressed data size (bytes) + 29603, // compressed data size (bytes) kgspBinArchiveGspRmBoot_AD102_ucode_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1046,7 +3830,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_AD102_ucode_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmBoot_AD102("ucode_desc_prod") -// FILE NAME: kernel/inc/gsprm/bin/g_gsprm_skbl_prod_ad102_riscv_desc.bin +// FILE NAME: kernel/inc/gsprm/bin/g_gsprm_skbl_prod_libos3_ad102_riscv_desc.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES @@ -1056,9 +3840,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_AD102_ucode_image_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_AD102_ucode_desc_prod_data[] = { - 0x63, 0x65, 0x00, 0x02, 0x05, 0x06, 0x86, 0x0d, 0xac, 0x40, 0xac, 0xca, 0xc0, 0x20, 0xc0, 0x80, - 0x05, 0x70, 0x40, 0x31, 0x33, 0x10, 0x73, 0x03, 0x31, 0x2f, 0x03, 0x03, 0x23, 0x36, 0x75, 0x06, - 0x10, 0x41, 0x00, 0x42, 0x1a, 0xfd, 0xdc, 0x54, 0x00, 0x00, 0x00, + 0x63, 0x65, 0x00, 0x82, 0x02, 0x06, 0x06, 0x07, 0x36, 0x20, 0x2e, 0x63, 0x60, 0x10, 0x60, 0xc0, + 0x02, 0x38, 0xa0, 0xd8, 0x01, 0x88, 0x3d, 0x80, 0x58, 0x9d, 0x81, 0x81, 0x11, 0x9b, 0xba, 0x06, + 0x88, 0x20, 0x00, 0x3c, 0xec, 0x41, 0xdd, 0x54, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1106,6 +3890,14 @@ const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmBoot_AD102(struct KernelGsp *pKerne #endif // defined(BINDATA_INCLUDE_FUNCTION) +#if defined(BINDATA_INCLUDE_FUNCTION_STUB) +const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmBoot_AD102(struct KernelGsp *pKernelGsp) +{ + return NULL; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION_STUB) + + diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GA100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GA100.c index dff2bd6aa..e8dca94e0 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GA100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GA100.c @@ -169,6 +169,14 @@ const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmBoot_GA100(struct KernelGsp *pKerne #endif // defined(BINDATA_INCLUDE_FUNCTION) +#if defined(BINDATA_INCLUDE_FUNCTION_STUB) +const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmBoot_GA100(struct KernelGsp *pKernelGsp) +{ + return NULL; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION_STUB) + + diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c index 748d948b9..502af8dbf 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c @@ -1107,6 +1107,14 @@ const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmBoot_GA102(struct KernelGsp *pKerne #endif // defined(BINDATA_INCLUDE_FUNCTION) +#if defined(BINDATA_INCLUDE_FUNCTION_STUB) +const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmBoot_GA102(struct KernelGsp *pKernelGsp) +{ + return NULL; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION_STUB) + + diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c index 5d4ba5fa1..286831e2c 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c @@ -29,7658 +29,7755 @@ #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmBoot_GH100("ucode_image_dbg") -// FILE NAME: kernel/inc/gspcc/bin/g_cc_gsp_gh100_gsprm_dbg_image.bin +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dbg_image.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 122880 -// COMPRESSED SIZE (bytes): 122261 +// DATA SIZE (bytes): 126976 +// COMPRESSED SIZE (bytes): 123814 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GH100_ucode_image_dbg_data[] = { - 0xec, 0x97, 0xd3, 0x92, 0x28, 0x0a, 0x94, 0x64, 0xcb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, - 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 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0x79, + 0x5e, 0x67, 0xcb, 0x92, 0x5c, 0x9f, 0x88, 0x43, 0xa8, 0xcb, 0xa6, 0x3b, 0x77, 0x3c, 0xe8, 0xdc, + 0x57, 0x9a, 0x4d, 0xec, 0x45, 0x0d, 0x92, 0x82, 0xd6, 0xe8, 0x4d, 0x44, 0x16, 0xf4, 0x95, 0xee, + 0xb8, 0xdc, 0xf1, 0x98, 0x4a, 0x7c, 0x8c, 0xf8, 0x98, 0x97, 0x3d, 0x2d, 0x95, 0xa1, 0x2e, 0xad, + 0x14, 0x00, 0x30, 0x36, 0x0b, 0x88, 0x6c, 0x40, 0xe7, 0x9f, 0x56, 0x02, 0xf8, 0xcf, 0x7f, 0xfe, + 0xf3, 0x9f, 0xff, 0xfc, 0xe7, 0x3f, 0xff, 0xf9, 0xcf, 0x7f, 0xfe, 0x1f, 0xf9, 0x3f, 0x23, 0x54, + 0x66, 0x04, 0x00, 0xf0, 0x01, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -7690,8 +7787,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GH100_ucode_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 122880, // uncompressed data size (bytes) - 122261, // compressed data size (bytes) + 126976, // uncompressed data size (bytes) + 123814, // compressed data size (bytes) kgspBinArchiveGspRmBoot_GH100_ucode_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -7703,7 +7800,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GH100_ucode_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmBoot_GH100("ucode_desc_dbg") -// FILE NAME: kernel/inc/gspcc/bin/g_cc_gsp_gh100_gsprm_dbg_desc.bin +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dbg_desc.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES @@ -7713,8 +7810,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GH100_ucode_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GH100_ucode_desc_dbg_data[] = { - 0x63, 0x65, 0x20, 0x02, 0x70, 0x41, 0x71, 0x25, 0x10, 0x37, 0x03, 0x71, 0x0c, 0x23, 0x03, 0x23, - 0x1e, 0x7d, 0x00, 0x80, 0x97, 0x91, 0xad, 0x54, 0x00, 0x00, 0x00, + 0x63, 0x65, 0x20, 0x02, 0x70, 0x41, 0x71, 0x25, 0x10, 0x37, 0x03, 0x71, 0x12, 0x23, 0x03, 0x23, + 0x1e, 0x7d, 0x00, 0x9f, 0x32, 0x0c, 0x15, 0x54, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -7737,7681 +7834,7778 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GH100_ucode_desc_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmBoot_GH100("ucode_image_prod") -// FILE NAME: kernel/inc/gspcc/bin/g_cc_gsp_gh100_gsprm_prd_image.bin +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_prd_image.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 122880 -// COMPRESSED SIZE (bytes): 122636 +// DATA SIZE (bytes): 126976 +// COMPRESSED SIZE (bytes): 124189 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GH100_ucode_image_prod_data[] = { - 0x9c, 0x96, 0xc3, 0x8e, 0x28, 0x0a, 0x80, 0x44, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, - 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0xed, 0xbe, 0x6d, 0xdb, 0xf3, 0x7e, 0x60, 0x66, 0x31, 0x67, - 0x5d, 0x8b, 0x4a, 0x2a, 0x39, 0xa9, 0xa6, 0x9f, 0x6f, 0x9e, 0xcd, 0x13, 0xb6, 0x50, 0x1e, 0x13, - 0xe2, 0x49, 0xec, 0x24, 0x69, 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0xb7, 0x92, 0xd7, 0xef, 0x2b, 0x40, 0xe0, 0xd5, 0xc8, 0x0a, 0xb1, 0x4b, + 0x58, 0x4f, 0x1b, 0xaa, 0x89, 0x24, 0x3e, 0x76, 0xc3, 0x8e, 0x73, 0x94, 0x88, 0xac, 0x78, 0xa2, + 0x92, 0x33, 0x33, 0x51, 0x33, 0x51, 0x44, 0x77, 0xa2, 0x1a, 0xb7, 0x40, 0x4b, 0x83, 0xbb, 0x8b, + 0x88, 0xc1, 0xa9, 0xd8, 0x38, 0xc7, 0x05, 0x21, 0x5e, 0x16, 0x00, 0x91, 0xd1, 0xc9, 0x31, 0x5a, + 0x8c, 0x51, 0xfa, 0xee, 0x61, 0x7f, 0x6a, 0x7c, 0xad, 0x8e, 0x7a, 0x48, 0x3d, 0x7c, 0xfd, 0xe3, + 0xb4, 0xfb, 0xa2, 0x94, 0x11, 0xfd, 0xd8, 0x96, 0xab, 0x91, 0x2c, 0xab, 0x00, 0x0e, 0x69, 0xf1, + 0xb2, 0xbd, 0x96, 0x6c, 0x58, 0x7f, 0x3e, 0x08, 0x35, 0x40, 0x41, 0x95, 0x09, 0x30, 0x66, 0x13, + 0x16, 0xff, 0x87, 0x7c, 0xe7, 0x59, 0x31, 0x99, 0xcd, 0x37, 0x31, 0x58, 0xdb, 0x11, 0x1f, 0xdf, + 0x77, 0x8f, 0x0e, 0xf0, 0x9f, 0xff, 0xfc, 0xe7, 0x3f, 0xff, 0xf9, 0xcf, 0x7f, 0xfe, 0xf3, 0x9f, + 0xff, 0xfc, 0x3f, 0xf2, 0x7f, 0x33, 0x9e, 0x06, 0x17, 0x00, 0xf0, 0x01, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -15421,8 +15615,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GH100_ucode_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 122880, // uncompressed data size (bytes) - 122636, // compressed data size (bytes) + 126976, // uncompressed data size (bytes) + 124189, // compressed data size (bytes) kgspBinArchiveGspRmBoot_GH100_ucode_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -15434,7 +15628,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GH100_ucode_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_DATA) // // FUNCTION: kgspGetBinArchiveGspRmBoot_GH100("ucode_desc_prod") -// FILE NAME: kernel/inc/gspcc/bin/g_cc_gsp_gh100_gsprm_prd_desc.bin +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_prd_desc.bin // FILE TYPE: BINARY // VAR NAME: N/A // COMPRESSION: YES @@ -15444,8 +15638,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GH100_ucode_image_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GH100_ucode_desc_prod_data[] = { - 0x63, 0x65, 0x20, 0x02, 0x70, 0x41, 0x71, 0x25, 0x10, 0x37, 0x03, 0x71, 0x0c, 0x23, 0x03, 0x23, - 0x1e, 0x7d, 0x00, 0x80, 0x97, 0x91, 0xad, 0x54, 0x00, 0x00, 0x00, + 0x63, 0x65, 0x20, 0x02, 0x70, 0x41, 0x71, 0x25, 0x10, 0x37, 0x03, 0x71, 0x12, 0x23, 0x03, 0x23, + 0x1e, 0x7d, 0x00, 0x9f, 0x32, 0x0c, 0x15, 0x54, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -15493,6 +15687,14 @@ const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmBoot_GH100(struct KernelGsp *pKerne #endif // defined(BINDATA_INCLUDE_FUNCTION) +#if defined(BINDATA_INCLUDE_FUNCTION_STUB) +const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmBoot_GH100(struct KernelGsp *pKernelGsp) +{ + return NULL; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION_STUB) + + diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_TU102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_TU102.c index cd9ca7c07..fd912cdad 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_TU102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_TU102.c @@ -169,6 +169,14 @@ const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmBoot_TU102(struct KernelGsp *pKerne #endif // defined(BINDATA_INCLUDE_FUNCTION) +#if defined(BINDATA_INCLUDE_FUNCTION_STUB) +const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmBoot_TU102(struct KernelGsp *pKernelGsp) +{ + return NULL; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION_STUB) + + diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcGfwDebugSigned_GH100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcGfwDebugSigned_GH100.c deleted file mode 100644 index a2683b4f2..000000000 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcGfwDebugSigned_GH100.c +++ /dev/null @@ -1,7884 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - - -/* THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT! */ - - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveGspRmCcGfwDebugSigned_GH100("ucode_image") -// FILE NAME: kernel/inc/gspcc/bin/g_cc_gsp_gh100_gsprm_dbg_gfw_image.bin -// FILE TYPE: BINARY -// VAR NAME: N/A -// COMPRESSION: YES -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 122696 -// COMPRESSED SIZE (bytes): 122284 -// -static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcGfwDebugSigned_GH100_ucode_image_data[] = -{ - 0x8c, 0x97, 0xc3, 0x92, 0x28, 0x0a, 0x90, 0x44, 0x9b, 0xb7, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, - 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0xdd, 0x3d, 0x2f, 0x26, 0xe6, 0x03, 0x26, - 0x37, 0x55, 0xeb, 0xcc, 0x88, 0x3a, 0x95, 0xc0, 0x20, 0xe2, 0x00, 0x00, 0x7b, 0x80, 0x00, 0xff, - 0x2b, 0xed, 0xff, 0x9b, 0x1e, 0x00, 0x00, 0x20, 0xff, 0xb7, 0x02, 0x92, 0x03, 0xfc, 0xbf, 0x24, - 0x54, 0x6d, 0xb5, 0xb9, 0x11, 0xb0, 0x95, 0x3c, 0xcf, 0xdd, 0x01, 0x90, 0x65, 0x0b, 0xf3, 0x30, - 0xf7, 0x27, 0x7d, 0xaa, 0x7c, 0x4d, 0x0a, 0xbd, 0xeb, 0x1e, 0xad, 0x10, 0xb3, 0x58, 0xca, 0x4d, - 0xd3, 0x45, 0x15, 0x97, 0xd1, 0xff, 0xb2, 0xe5, 0xc8, 0xea, 0xc6, 0x69, 0xa8, 0x3b, 0xc9, 0x7b, - 0x7f, 0x9e, 0x11, 0xb6, 0x17, 0x2b, 0x0d, 0x18, 0xf8, 0x22, 0x86, 0x89, 0xdc, 0x0d, 0xbe, 0x72, - 0x1b, 0x91, 0xb5, 0xab, 0xe2, 0x16, 0x44, 0x15, 0xbd, 0x74, 0x28, 0x41, 0x6a, 0x87, 0x16, 0x41, - 0xbd, 0x2a, 0xec, 0x3d, 0xc2, 0x4d, 0x56, 0x12, 0x46, 0x69, 0x36, 0xf7, 0xcd, 0xb2, 0x50, 0xc4, - 0x8b, 0x44, 0x11, 0x56, 0x98, 0xc9, 0x7e, 0xba, 0xd5, 0xa7, 0xea, 0xb6, 0x2a, 0xb1, 0x59, 0x5e, - 0x5d, 0x8c, 0x8f, 0x33, 0x4a, 0xa5, 0x73, 0xdb, 0x0c, 0xc7, 0x55, 0x78, 0x9f, 0x7d, 0x29, 0xeb, - 0xa7, 0x33, 0x49, 0xb8, 0xb5, 0x46, 0x49, 0x9f, 0x55, 0xc2, 0xb3, 0x6e, 0xa3, 0x3c, 0x52, 0xca, - 0xd8, 0x2d, 0x14, 0x96, 0xc6, 0xd9, 0x05, 0x46, 0x9b, 0xc2, 0x70, 0x17, 0x9b, 0x78, 0xb2, 0xec, - 0x43, 0x0d, 0x9d, 0x76, 0x9c, 0xe1, 0x64, 0x07, 0xe8, 0x83, 0x5b, 0x35, 0x4a, 0xaf, 0xf1, 0x40, - 0x66, 0xab, 0xeb, 0x94, 0x5f, 0x67, 0x76, 0x5d, 0x40, 0xa2, 0xd6, 0x62, 0x37, 0x80, 0x7d, 0xbc, - 0x15, 0x56, 0xec, 0x5b, 0x97, 0x8c, 0xc3, 0x3a, 0xa9, 0x79, 0x73, 0x77, 0x2f, 0x2b, 0x23, 0x64, - 0x4a, 0x38, 0xa1, 0x8e, 0x5b, 0xfd, 0x52, 0x8f, 0xc0, 0xe9, 0x2f, 0x27, 0x91, 0xd8, 0x81, 0x90, - 0xea, 0xe2, 0xf8, 0x2e, 0x03, 0x8a, 0x4e, 0x1a, 0x1a, 0xf9, 0x28, 0x4f, 0x16, 0xdf, 0x20, 0xc7, - 0x97, 0xd1, 0x0e, 0xdb, 0x92, 0x9f, 0xdc, 0x8f, 0xad, 0x35, 0x96, 0xfc, 0x25, 0x47, 0x0e, 0x1d, - 0x04, 0xa3, 0xac, 0x6a, 0xea, 0x23, 0xbc, 0x86, 0xf5, 0x67, 0xe3, 0x70, 0xc8, 0x04, 0x2d, 0x14, - 0x24, 0x29, 0x0d, 0x58, 0x24, 0xd7, 0xb2, 0xa4, 0xbb, 0xc6, 0x6f, 0x08, 0x28, 0x22, 0x1a, 0x14, - 0x27, 0xc3, 0x53, 0x28, 0xb5, 0x9d, 0x5c, 0xcc, 0xce, 0x69, 0x99, 0x08, 0xc1, 0xdf, 0x81, 0x24, - 0xd8, 0x93, 0x84, 0xcb, 0xe1, 0x6f, 0x3a, 0xc8, 0x7f, 0xc1, 0xed, 0x5e, 0xab, 0x05, 0xb4, 0xcc, - 0x5b, 0x8e, 0xe1, 0x9f, 0x83, 0x0f, 0xc1, 0xa4, 0x22, 0xc3, 0x4e, 0x05, 0x5b, 0xdc, 0x92, 0xae, - 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0x66, 0xea, 0xad, 0xd6, 0xc6, 0xec, 0x3c, 0x4d, 0xb0, 0x09, 0xf9, 0xc4, 0xaf, 0x92, 0x0b, 0x02, - 0xac, 0x25, 0x55, 0x12, 0x30, 0x4e, 0x97, 0x6d, 0x62, 0xd9, 0xc8, 0x4a, 0x50, 0x50, 0xa1, 0x2d, - 0xb8, 0xc8, 0xac, 0x76, 0xc1, 0x2c, 0x56, 0x6a, 0xd2, 0x2e, 0x44, 0x2d, 0xfd, 0x69, 0x20, 0x39, - 0xee, 0xfb, 0x87, 0xa6, 0x0a, 0x3f, 0x4e, 0xe5, 0xf9, 0x9f, 0x59, 0x20, 0x92, 0xf6, 0xc8, 0x19, - 0x97, 0x7a, 0x48, 0x83, 0xf4, 0x4c, 0xdb, 0x1d, 0x45, 0x9a, 0xb5, 0xc7, 0xd4, 0xaa, 0x63, 0x6f, - 0xa1, 0xb6, 0x08, 0xcf, 0x68, 0x0f, 0x42, 0xef, 0x89, 0x2e, 0x81, 0xc5, 0xa2, 0xc2, 0xd6, 0x4e, - 0x55, 0x97, 0xe4, 0xc4, 0x12, 0x41, 0xd6, 0xa2, 0xdd, 0x26, 0x0e, 0x57, 0x36, 0xc4, 0xe6, 0x57, - 0x83, 0x16, 0x07, 0x50, 0xbe, 0x1d, 0x2e, 0xad, 0xe4, 0x62, 0x9b, 0x04, 0x35, 0xd8, 0x18, 0x17, - 0x7c, 0x1d, 0xf9, 0xef, 0xdb, 0x8f, 0xc6, 0xbe, 0x90, 0xef, 0xf2, 0x34, 0x8a, 0x6b, 0x47, 0x43, - 0x09, 0x7f, 0x0d, 0x05, 0x1e, 0xe5, 0xe3, 0x5e, 0x4f, 0xbd, 0x21, 0xe2, 0x65, 0xf2, 0xce, 0x1d, - 0xa6, 0x7d, 0xbd, 0x2d, 0x4c, 0x35, 0x22, 0x55, 0x28, 0x49, 0xec, 0xee, 0x15, 0xb6, 0x75, 0x45, - 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NV_TRUE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveGspRmCcGfwDebugSigned_GH100("ucode_hash") -// FILE NAME: kernel/inc/gspcc/bin/g_cc_gsp_gh100_gsprm_dbg_gfw_hash.bin -// FILE TYPE: BINARY -// VAR NAME: N/A -// COMPRESSION: YES -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 48 -// COMPRESSED SIZE (bytes): 61 -// -static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcGfwDebugSigned_GH100_ucode_hash_data[] = -{ - 0x01, 0x30, 0x00, 0xcf, 0xff, 0x31, 0xf2, 0x97, 0xfe, 0xfc, 0x97, 0x35, 0xc5, 0x70, 0x3e, 0x99, - 0x52, 0xcf, 0x77, 0x03, 0xf9, 0xc2, 0x58, 0x50, 0xe1, 0x94, 0x84, 0x2c, 0xbf, 0xf3, 0x76, 0xd3, - 0x8c, 0xfc, 0x09, 0xec, 0x19, 0x7e, 0x19, 0x1d, 0x68, 0x56, 0xe6, 0x59, 0xf1, 0x80, 0x39, 0x6d, - 0xc0, 0x7a, 0x97, 0x26, 0x0f, 0x9a, 0x32, 0xb1, 0x5c, 0x30, 0x00, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcGfwDebugSigned_GH100_ucode_hash_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 48, // uncompressed data size (bytes) - 61, // compressed data size (bytes) - kgspBinArchiveGspRmCcGfwDebugSigned_GH100_ucode_hash_data, // compressed data pointer - NV_TRUE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveGspRmCcGfwDebugSigned_GH100("ucode_sig") -// FILE NAME: kernel/inc/gspcc/bin/g_cc_gsp_gh100_gsprm_dbg_gfw_sig.bin -// FILE TYPE: BINARY -// VAR NAME: N/A -// COMPRESSION: YES -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 384 -// COMPRESSED SIZE (bytes): 397 -// -static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcGfwDebugSigned_GH100_ucode_sig_data[] = -{ - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x82, 0x47, 0xd5, 0x77, 0x95, 0x34, 0x94, 0xf2, 0x7a, 0x82, 0xe8, - 0x78, 0xb7, 0x08, 0x96, 0xdd, 0xf5, 0x58, 0xd8, 0x5a, 0x7f, 0x9f, 0xff, 0x29, 0x70, 0x91, 0x41, - 0x75, 0xd5, 0x9d, 0xb8, 0xd8, 0x62, 0xe3, 0xb3, 0x81, 0xf6, 0x0c, 0x3d, 0x91, 0x73, 0xa5, 0x64, - 0x95, 0xf5, 0xf0, 0x10, 0x2a, 0x80, 0x5e, 0x93, 0x4d, 0xda, 0x7e, 0x44, 0xdd, 0x60, 0xc8, 0x87, - 0x69, 0xf3, 0x1e, 0x46, 0x3b, 0x4a, 0xd8, 0x8a, 0x3a, 0xe5, 0x3b, 0x17, 0xbb, 0xc0, 0x06, 0x7d, - 0x25, 0xe5, 0x9a, 0x1d, 0x31, 0xc6, 0x1a, 0x48, 0xe2, 0xdd, 0x4b, 0x99, 0xfb, 0x1e, 0x92, 0x5c, - 0xcf, 0x6c, 0x7f, 0x37, 0x95, 0x5b, 0xc4, 0xca, 0x8b, 0x9f, 0xe1, 0x3a, 0xef, 0x35, 0xbd, 0x66, - 0x75, 0x8b, 0x9e, 0x1e, 0xc0, 0x57, 0x7d, 0x7b, 0x87, 0x88, 0x13, 0x4b, 0xe1, 0xb1, 0xe3, 0xad, - 0x6f, 0xed, 0xeb, 0x5f, 0x9f, 0x98, 0xbe, 0xf5, 0x3f, 0xfe, 0x09, 0xf9, 0xe6, 0xc8, 0x4c, 0x4c, - 0x73, 0x6d, 0x01, 0xa3, 0x61, 0x20, 0x9e, 0xb3, 0x33, 0x8b, 0x07, 0xc1, 0xb2, 0xe7, 0x84, 0x18, - 0x94, 0x95, 0x97, 0xa3, 0xf8, 0x93, 0xf7, 0x3a, 0x71, 0xbf, 0x92, 0xb0, 0x18, 0xf7, 0xe8, 0xa5, - 0x85, 0xdb, 0x74, 0xa7, 0x90, 0x9d, 0x9b, 0x2f, 0xf8, 0x67, 0xe5, 0x05, 0x3d, 0xb4, 0xec, 0xf2, - 0xa1, 0x75, 0x22, 0xb6, 0x58, 0x09, 0x28, 0xa1, 0x72, 0x3f, 0xe3, 0xe7, 0x11, 0x1b, 0xfe, 0x18, - 0xdf, 0x53, 0xab, 0x5d, 0xb5, 0xbc, 0xcb, 0xa9, 0x12, 0x9a, 0xac, 0x89, 0xc2, 0xfa, 0xca, 0xe3, - 0xa9, 0xc6, 0x9e, 0xe1, 0xbe, 0x51, 0x15, 0xfc, 0x74, 0x58, 0x0c, 0x33, 0x4e, 0x2a, 0x54, 0x90, - 0x0e, 0x1f, 0xcf, 0x0c, 0x07, 0x9d, 0x7c, 0xf1, 0xd9, 0x38, 0xb4, 0x58, 0x30, 0xb6, 0xb5, 0x15, - 0x62, 0x4f, 0x36, 0x92, 0x24, 0x34, 0x29, 0x88, 0xb5, 0x8a, 0x84, 0x43, 0xb9, 0xf6, 0x22, 0x2e, - 0xaa, 0x84, 0x39, 0x15, 0xf7, 0x22, 0x93, 0x3c, 0x03, 0x05, 0x82, 0xd7, 0x02, 0x2c, 0xf2, 0x72, - 0xfc, 0x9b, 0xb6, 0x83, 0xf0, 0x77, 0x53, 0x76, 0xb3, 0xa2, 0xa6, 0xb2, 0x23, 0xda, 0xda, 0x77, - 0x4d, 0x94, 0xbf, 0xfd, 0x33, 0xc5, 0xc0, 0xd2, 0x00, 0xdf, 0xc5, 0x59, 0x82, 0x65, 0x5d, 0xdd, - 0xf0, 0x9e, 0x99, 0xd0, 0xf8, 0x00, 0x63, 0x3e, 0x3b, 0xef, 0x53, 0xbe, 0xf5, 0x4d, 0x78, 0xa7, - 0x59, 0x6a, 0x1c, 0x44, 0xd6, 0x99, 0xa1, 0xb9, 0xd5, 0x7f, 0xd9, 0x83, 0xbd, 0xae, 0x17, 0x3b, - 0xbe, 0x97, 0x91, 0x80, 0x7c, 0xad, 0x92, 0xdb, 0x5c, 0x25, 0x6b, 0x09, 0x5c, 0xc4, 0x13, 0xaa, - 0xc7, 0x1c, 0x6c, 0xa5, 0x48, 0xd1, 0x0a, 0x7f, 0xb5, 0x42, 0x27, 0x87, 0x56, 0x79, 0x40, 0x43, - 0x5e, 0x63, 0x93, 0x03, 0x08, 0x71, 0x34, 0xab, 0x24, 0x80, 0x01, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcGfwDebugSigned_GH100_ucode_sig_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 384, // uncompressed data size (bytes) - 397, // compressed data size (bytes) - kgspBinArchiveGspRmCcGfwDebugSigned_GH100_ucode_sig_data, // compressed data pointer - NV_TRUE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveGspRmCcGfwDebugSigned_GH100("ucode_pkey") -// FILE NAME: kernel/inc/gspcc/bin/g_cc_gsp_gh100_gsprm_dbg_gfw_pub_key.bin -// FILE TYPE: BINARY -// VAR NAME: N/A -// COMPRESSION: YES -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 384 -// COMPRESSED SIZE (bytes): 397 -// -static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcGfwDebugSigned_GH100_ucode_pkey_data[] = -{ - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0xb1, 0xb2, 0x7a, 0x80, 0x2b, 0x7d, 0x7c, 0xc5, 0x65, 0x9b, 0x93, - 0x52, 0x4d, 0x36, 0x1d, 0xf9, 0x78, 0x50, 0xd6, 0x3f, 0x24, 0xad, 0x30, 0x50, 0x48, 0x5e, 0xe7, - 0x17, 0xea, 0xa5, 0x90, 0xd0, 0x16, 0xf8, 0xb2, 0xf2, 0x8e, 0x5c, 0x85, 0x38, 0x65, 0xab, 0xa7, - 0x28, 0x02, 0xef, 0x55, 0x9f, 0x32, 0x16, 0x19, 0x49, 0xc8, 0x71, 0x8e, 0x5f, 0x2d, 0xf7, 0x48, - 0x75, 0x47, 0xc1, 0x7f, 0xd7, 0x17, 0xb7, 0x8c, 0xbb, 0xad, 0xa7, 0xf2, 0x8b, 0xcb, 0x0f, 0xad, - 0xef, 0x3d, 0x09, 0x88, 0x47, 0x0f, 0x43, 0xdc, 0x6b, 0x0f, 0xc6, 0xac, 0x9e, 0x9e, 0x76, 0x09, - 0xa8, 0xbd, 0xc6, 0xe5, 0x9c, 0x20, 0xc2, 0x60, 0x3f, 0x10, 0xa8, 0xe1, 0x62, 0x91, 0x97, 0x4f, - 0x95, 0x52, 0x3a, 0xd3, 0xa8, 0xfe, 0x66, 0xe4, 0xe4, 0xef, 0xbb, 0xab, 0x20, 0xd8, 0x1b, 0xf2, - 0xc9, 0x04, 0x01, 0x1d, 0x39, 0xe6, 0x3c, 0x1a, 0xe4, 0xfd, 0xb6, 0xd1, 0x18, 0x81, 0x5e, 0x78, - 0xec, 0xee, 0x63, 0xd4, 0x91, 0x3a, 0x05, 0x2c, 0x36, 0x84, 0xbd, 0xb1, 0xfa, 0xb7, 0xf4, 0x5a, - 0xf6, 0xd0, 0x7f, 0x78, 0xe4, 0x16, 0x00, 0x2b, 0xc0, 0xac, 0x9e, 0x89, 0x50, 0x78, 0xbb, 0xe7, - 0x4d, 0x9d, 0xf4, 0xc9, 0xfe, 0xb7, 0x29, 0x65, 0x6f, 0x33, 0x91, 0x2c, 0x3a, 0x7d, 0x8e, 0xc5, - 0x84, 0xd6, 0x55, 0x3b, 0x79, 0x0c, 0xea, 0x93, 0x9f, 0x64, 0x49, 0x1a, 0xf5, 0x2c, 0xc8, 0x10, - 0x92, 0x90, 0xb1, 0xe3, 0x0e, 0xd0, 0xf4, 0xad, 0x11, 0x3b, 0x20, 0xb1, 0x2d, 0xc7, 0xa6, 0x6e, - 0xd3, 0x9c, 0x67, 0x49, 0x3e, 0xad, 0xea, 0x44, 0x09, 0x96, 0x96, 0xce, 0x1e, 0x7a, 0xcd, 0x40, - 0x30, 0xa2, 0xdb, 0xce, 0x60, 0x19, 0xd8, 0x8d, 0x96, 0x5e, 0x0c, 0x30, 0xcd, 0xe3, 0xcb, 0x02, - 0x3e, 0x2b, 0x26, 0x38, 0x2b, 0x2c, 0x09, 0xa6, 0xc8, 0xad, 0xbb, 0xde, 0x67, 0x33, 0xaf, 0x53, - 0x72, 0x7c, 0x77, 0xe2, 0xb8, 0xe2, 0xe0, 0x11, 0xb8, 0x26, 0xe7, 0x92, 0x29, 0x8b, 0xe1, 0xef, - 0x6a, 0x7e, 0x49, 0x09, 0x37, 0xde, 0x61, 0xc5, 0xeb, 0x11, 0x72, 0x47, 0x85, 0x2a, 0x66, 0x6c, - 0x5f, 0x02, 0xb5, 0x86, 0x82, 0x81, 0x56, 0x8e, 0x1c, 0xa4, 0xf8, 0xab, 0x7e, 0x1f, 0x9b, 0x84, - 0x5b, 0xdd, 0xc1, 0x7d, 0x62, 0xa1, 0xd2, 0x96, 0xc8, 0x1e, 0x2f, 0x32, 0xcd, 0x18, 0x0d, 0x6c, - 0x4a, 0x1c, 0xa0, 0x82, 0x74, 0x28, 0x15, 0xf9, 0xa1, 0x65, 0x52, 0x03, 0x8a, 0x7f, 0x0d, 0xff, - 0xd1, 0x15, 0x04, 0x99, 0x7d, 0xd8, 0xa3, 0x04, 0xe3, 0x22, 0x60, 0x40, 0x74, 0xf6, 0x08, 0x48, - 0x24, 0xe8, 0xbc, 0x54, 0x19, 0x3c, 0xc4, 0x38, 0xfc, 0xa9, 0x5e, 0x92, 0xa4, 0xae, 0x0a, 0x8a, - 0xef, 0xca, 0x63, 0x96, 0x9d, 0xf3, 0x87, 0x94, 0x2b, 0x80, 0x01, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcGfwDebugSigned_GH100_ucode_pkey_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 384, // uncompressed data size (bytes) - 397, // compressed data size (bytes) - kgspBinArchiveGspRmCcGfwDebugSigned_GH100_ucode_pkey_data, // compressed data pointer - NV_TRUE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_ARCHIVE) -// -// Bindata Archive structure -// -static const BINDATA_ARCHIVE __kgspGetBinArchiveGspRmCcGfwDebugSigned_GH100 = -{ - 4, // entryNum - { - // entries[] : { "name", pBinStorage } - { "ucode_image" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmCcGfwDebugSigned_GH100_ucode_image_storage_pvt }, - { "ucode_hash" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmCcGfwDebugSigned_GH100_ucode_hash_storage_pvt }, - { "ucode_sig" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmCcGfwDebugSigned_GH100_ucode_sig_storage_pvt }, - { "ucode_pkey" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmCcGfwDebugSigned_GH100_ucode_pkey_storage_pvt }, - } -}; - -#endif // defined(BINDATA_INCLUDE_ARCHIVE) - - - -#if defined(BINDATA_INCLUDE_FUNCTION) -const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmCcGfwDebugSigned_GH100(struct KernelGsp *pKernelGsp) -{ - return &__kgspGetBinArchiveGspRmCcGfwDebugSigned_GH100; -} -#endif // defined(BINDATA_INCLUDE_FUNCTION) - - - - - diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcGfwProdSigned_GH100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcGfwProdSigned_GH100.c deleted file mode 100644 index 9a0e49ea0..000000000 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcGfwProdSigned_GH100.c +++ /dev/null @@ -1,7908 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - - -/* THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT! */ - - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveGspRmCcGfwProdSigned_GH100("ucode_image") -// FILE NAME: kernel/inc/gspcc/bin/g_cc_gsp_gh100_gsprm_prd_gfw_image.bin -// FILE TYPE: BINARY -// VAR NAME: N/A -// COMPRESSION: YES -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 122696 -// COMPRESSED SIZE (bytes): 122661 -// -static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcGfwProdSigned_GH100_ucode_image_data[] = -{ - 0x8c, 0x97, 0xc3, 0x92, 0x28, 0x0a, 0x80, 0x43, 0xdb, 0xb6, 0x6d, 0xdb, 0x36, 0x6e, 0xdb, 0xb6, - 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0xad, 0x79, 0x35, 0x35, 0x1f, 0x30, 0xd9, - 0x24, 0xab, 0x64, 0x7b, 0x02, 0x0c, 0x22, 0x0e, 0x00, 0xb0, 0x07, 0x08, 0xf0, 0xbf, 0xd2, 0xfe, - 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122696, // uncompressed data size (bytes) - 122661, // compressed data size (bytes) - kgspBinArchiveGspRmCcGfwProdSigned_GH100_ucode_image_data, // compressed data pointer - NV_TRUE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveGspRmCcGfwProdSigned_GH100("ucode_hash") -// FILE NAME: kernel/inc/gspcc/bin/g_cc_gsp_gh100_gsprm_prd_gfw_hash.bin -// FILE TYPE: BINARY -// VAR NAME: N/A -// COMPRESSION: YES -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 48 -// COMPRESSED SIZE (bytes): 61 -// -static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcGfwProdSigned_GH100_ucode_hash_data[] = -{ - 0x01, 0x30, 0x00, 0xcf, 0xff, 0x7d, 0x76, 0xf8, 0x43, 0xa9, 0xee, 0xe8, 0x60, 0xa1, 0xad, 0x46, - 0x44, 0x30, 0xd9, 0xf4, 0xc4, 0x7f, 0xbd, 0xed, 0xdd, 0xd2, 0x4b, 0x5e, 0x16, 0x37, 0xe2, 0x5b, - 0x50, 0x76, 0xa8, 0x48, 0x87, 0xe5, 0xe0, 0x64, 0x59, 0x1c, 0x8a, 0xb7, 0x59, 0xe8, 0x71, 0x30, - 0x76, 0x8b, 0x26, 0x84, 0x9e, 0xb5, 0x51, 0xd5, 0x33, 0x30, 0x00, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcGfwProdSigned_GH100_ucode_hash_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 48, // uncompressed data size (bytes) - 61, // compressed data size (bytes) - kgspBinArchiveGspRmCcGfwProdSigned_GH100_ucode_hash_data, // compressed data pointer - NV_TRUE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveGspRmCcGfwProdSigned_GH100("ucode_sig") -// FILE NAME: kernel/inc/gspcc/bin/g_cc_gsp_gh100_gsprm_prd_gfw_sig.bin -// FILE TYPE: BINARY -// VAR NAME: N/A -// COMPRESSION: YES -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 384 -// COMPRESSED SIZE (bytes): 397 -// -static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcGfwProdSigned_GH100_ucode_sig_data[] = -{ - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x04, 0x4a, 0x26, 0x73, 0x30, 0x94, 0xde, 0xaa, 0x24, 0xa2, 0xc3, - 0xb5, 0x00, 0x22, 0xa4, 0x0a, 0xef, 0x1a, 0xaa, 0x39, 0x70, 0xc7, 0x17, 0xcc, 0x6e, 0x54, 0x2d, - 0xe2, 0x2a, 0xad, 0xfd, 0x00, 0xee, 0xdd, 0xa3, 0xb3, 0x16, 0xf0, 0x26, 0x78, 0x04, 0xe6, 0xfc, - 0x7d, 0xf1, 0x11, 0x5a, 0xc9, 0x1b, 0xcc, 0x98, 0xc1, 0x51, 0x84, 0xeb, 0x92, 0x34, 0xd9, 0x28, - 0x76, 0x17, 0x76, 0x55, 0x14, 0x97, 0x68, 0x0a, 0xb8, 0xe8, 0xa3, 0xe0, 0x07, 0x6c, 0xdc, 0x2b, - 0x31, 0x0a, 0x82, 0x1d, 0xb9, 0x52, 0x74, 0x3c, 0x09, 0xec, 0x68, 0x7d, 0x1b, 0x18, 0x31, 0x16, - 0x3b, 0x7a, 0x94, 0x36, 0x0e, 0x75, 0x57, 0x74, 0x4b, 0x1b, 0x7f, 0xae, 0x03, 0x6e, 0x50, 0x6b, - 0x6d, 0x09, 0x92, 0x9a, 0x3b, 0xec, 0x71, 0x5c, 0x54, 0x15, 0x75, 0x79, 0x43, 0x4d, 0x38, 0xcd, - 0xdf, 0xfd, 0xe4, 0x00, 0x7e, 0xdf, 0x19, 0x1e, 0x89, 0xb9, 0x23, 0x66, 0x93, 0x11, 0x7d, 0x22, - 0xab, 0x82, 0xe6, 0x3d, 0x34, 0xd8, 0x63, 0xfa, 0xae, 0x6e, 0x44, 0xaf, 0x4b, 0x58, 0xdf, 0xd3, - 0x16, 0x5b, 0xe2, 0xbf, 0x75, 0x3f, 0xa1, 0x96, 0x38, 0x09, 0x0f, 0x3e, 0x50, 0xef, 0x0b, 0x16, - 0xe3, 0x89, 0xad, 0xc2, 0x81, 0x83, 0xe6, 0x38, 0xf9, 0xaa, 0x33, 0x09, 0x0e, 0x93, 0x5e, 0x76, - 0x5f, 0xfd, 0x99, 0x82, 0xbd, 0xd0, 0xe4, 0xd8, 0x15, 0x26, 0x58, 0x0f, 0xfb, 0x49, 0xbd, 0xf7, - 0xbd, 0x6b, 0x07, 0xef, 0x3d, 0x26, 0xd0, 0x8b, 0x5b, 0x5b, 0x60, 0x94, 0xcb, 0xd6, 0x67, 0x96, - 0x83, 0xaa, 0xe9, 0x66, 0xd7, 0x21, 0x40, 0x2c, 0xd4, 0xbd, 0x84, 0xf1, 0xcb, 0x8e, 0x1c, 0xf1, - 0xdd, 0xad, 0x46, 0x4d, 0x08, 0xdc, 0x33, 0xcf, 0x62, 0x3b, 0xc0, 0x78, 0x4d, 0x80, 0x96, 0x44, - 0x9e, 0x2f, 0xae, 0x80, 0xb1, 0x29, 0xef, 0x1f, 0x1d, 0xb3, 0x76, 0x57, 0x2c, 0x01, 0xca, 0x03, - 0x0e, 0x06, 0xc3, 0xe9, 0xc1, 0xe7, 0xeb, 0xd9, 0x6a, 0x7c, 0x27, 0x17, 0xeb, 0x8e, 0x7a, 0xe2, - 0xe0, 0x28, 0xbd, 0x6f, 0x6e, 0x4e, 0xe6, 0x07, 0xe5, 0x22, 0x27, 0x34, 0x78, 0x56, 0xdf, 0xd5, - 0x90, 0x27, 0xdb, 0x63, 0xb5, 0xc5, 0x1b, 0x8a, 0x17, 0x66, 0x04, 0x75, 0x9d, 0xc6, 0x2b, 0xcf, - 0xde, 0xb6, 0xe1, 0xe9, 0xfe, 0x54, 0xcf, 0x5d, 0xa2, 0xc8, 0xc7, 0xb3, 0x86, 0xf9, 0xd4, 0x25, - 0xf5, 0xc8, 0x36, 0x13, 0x8e, 0xf5, 0xe5, 0xc9, 0xf6, 0x2d, 0xa3, 0x48, 0xa0, 0x13, 0xb6, 0x07, - 0xb5, 0x25, 0x2f, 0xae, 0x63, 0x06, 0x71, 0xf7, 0x11, 0x74, 0xa4, 0xac, 0xc7, 0x3c, 0xc9, 0x09, - 0x82, 0xf2, 0xa5, 0x60, 0xcc, 0x11, 0x0a, 0xb4, 0xe7, 0xa8, 0xf0, 0x0a, 0x5a, 0x2c, 0x63, 0x30, - 0xe7, 0x21, 0x48, 0xb2, 0xbe, 0xfd, 0xc2, 0x18, 0x58, 0x80, 0x01, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcGfwProdSigned_GH100_ucode_sig_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 384, // uncompressed data size (bytes) - 397, // compressed data size (bytes) - kgspBinArchiveGspRmCcGfwProdSigned_GH100_ucode_sig_data, // compressed data pointer - NV_TRUE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveGspRmCcGfwProdSigned_GH100("ucode_pkey") -// FILE NAME: kernel/inc/gspcc/bin/g_cc_gsp_gh100_gsprm_prd_gfw_pub_key.bin -// FILE TYPE: BINARY -// VAR NAME: N/A -// COMPRESSION: YES -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 384 -// COMPRESSED SIZE (bytes): 397 -// -static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcGfwProdSigned_GH100_ucode_pkey_data[] = -{ - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0xb6, 0x61, 0x74, 0x8c, 0x50, 0xfd, 0x5d, 0x6b, 0xbc, 0x71, 0xe9, - 0xcf, 0x5e, 0xf6, 0x8b, 0x5d, 0xd5, 0x36, 0xe8, 0xaf, 0xca, 0x7a, 0x14, 0x6a, 0x3d, 0x1f, 0xa6, - 0x8b, 0x37, 0xf9, 0x3e, 0x5a, 0x44, 0xec, 0xb6, 0x6a, 0x39, 0x25, 0x78, 0xce, 0xd6, 0xf0, 0xe2, - 0xa1, 0x40, 0xae, 0x82, 0x22, 0x60, 0xaa, 0xf3, 0x6a, 0xd3, 0x4d, 0xe6, 0xc1, 0x38, 0x18, 0x4e, - 0xfc, 0xd6, 0x6c, 0x61, 0x38, 0x73, 0x13, 0x26, 0x71, 0xa8, 0xb8, 0x9c, 0xeb, 0x07, 0x28, 0x4e, - 0x86, 0x2b, 0xe2, 0x5e, 0xf8, 0xfd, 0x2c, 0x01, 0x51, 0x6f, 0x1c, 0xf9, 0x47, 0x36, 0x62, 0xcc, - 0x59, 0x24, 0x67, 0xf8, 0x5d, 0x13, 0x39, 0x52, 0xd9, 0x0b, 0xbf, 0x92, 0x98, 0xad, 0x98, 0x2b, - 0x53, 0x4d, 0x35, 0xda, 0x06, 0x7e, 0x89, 0x07, 0x2f, 0xb0, 0x0f, 0x12, 0x44, 0x1d, 0xe8, 0xa8, - 0xed, 0x40, 0x9c, 0x84, 0x8a, 0x99, 0x7e, 0x09, 0x05, 0xee, 0x9c, 0x62, 0x2a, 0x6e, 0xdb, 0xe3, - 0xc2, 0x7c, 0x39, 0x7c, 0xdb, 0x30, 0x49, 0x26, 0x58, 0xf1, 0x94, 0xa6, 0xd1, 0x8b, 0xda, 0x79, - 0x18, 0xed, 0x12, 0xdf, 0x72, 0xfd, 0x5b, 0x3d, 0x13, 0xab, 0xcc, 0xce, 0x20, 0x80, 0xd8, 0xe7, - 0x5d, 0x6c, 0xcf, 0x3e, 0x3a, 0x7c, 0x29, 0xda, 0xf4, 0xdb, 0x7a, 0xc0, 0x2a, 0x4d, 0xc7, 0xdc, - 0xe8, 0x09, 0xe6, 0x2a, 0xca, 0x6c, 0x33, 0xed, 0xf1, 0x96, 0xe5, 0x26, 0xb0, 0xc6, 0xcc, 0x22, - 0x15, 0xd2, 0x42, 0x47, 0x71, 0xe5, 0x6d, 0x2e, 0xda, 0xcd, 0x1d, 0x28, 0x59, 0xe9, 0x4d, 0x48, - 0xca, 0x36, 0xd4, 0x85, 0x6a, 0x26, 0x8e, 0x3e, 0xc7, 0xd7, 0x14, 0x77, 0x5e, 0x54, 0xda, 0x98, - 0xf8, 0x65, 0xaf, 0xea, 0x63, 0x46, 0xcd, 0xca, 0xd0, 0xbf, 0x9e, 0x31, 0xb2, 0x24, 0x7f, 0x4e, - 0xe5, 0xa3, 0x32, 0x5e, 0x22, 0x3a, 0xed, 0xed, 0xbe, 0xad, 0x5e, 0xa2, 0x36, 0x07, 0x41, 0x7f, - 0x94, 0x7b, 0x6f, 0x77, 0xea, 0xf6, 0xf3, 0x4e, 0xd3, 0x47, 0x39, 0x9c, 0xd0, 0x96, 0x70, 0x78, - 0x0c, 0x30, 0x9a, 0xa7, 0xe7, 0x85, 0x7e, 0xa6, 0xce, 0x00, 0x86, 0xfb, 0x91, 0xef, 0xe3, 0x31, - 0x1f, 0xc1, 0x5e, 0xda, 0xf3, 0x59, 0xdd, 0x36, 0xfe, 0x19, 0x2b, 0xca, 0xa4, 0x46, 0x5a, 0x52, - 0xaa, 0x65, 0x31, 0x00, 0x0b, 0x61, 0x57, 0x30, 0x8b, 0x0d, 0x13, 0xe6, 0xdc, 0xb3, 0x64, 0x61, - 0x98, 0x07, 0x52, 0xbc, 0x3e, 0x05, 0x26, 0x84, 0x96, 0xd0, 0x85, 0x62, 0x72, 0xd3, 0x9f, 0x60, - 0xf9, 0xc1, 0x33, 0x69, 0x1b, 0x49, 0x3e, 0x74, 0x08, 0x51, 0x2e, 0x97, 0x1b, 0x45, 0x54, 0x7c, - 0x4b, 0xd1, 0x51, 0x83, 0xaa, 0xf0, 0x9b, 0xff, 0x0c, 0xfb, 0x2f, 0x33, 0xcd, 0xe5, 0x1b, 0xcf, - 0x4f, 0x02, 0x0d, 0xf6, 0x1b, 0xdb, 0x48, 0x80, 0x58, 0x80, 0x01, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcGfwProdSigned_GH100_ucode_pkey_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 384, // uncompressed data size (bytes) - 397, // compressed data size (bytes) - kgspBinArchiveGspRmCcGfwProdSigned_GH100_ucode_pkey_data, // compressed data pointer - NV_TRUE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_ARCHIVE) -// -// Bindata Archive structure -// -static const BINDATA_ARCHIVE __kgspGetBinArchiveGspRmCcGfwProdSigned_GH100 = -{ - 4, // entryNum - { - // entries[] : { "name", pBinStorage } - { "ucode_image" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmCcGfwProdSigned_GH100_ucode_image_storage_pvt }, - { "ucode_hash" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmCcGfwProdSigned_GH100_ucode_hash_storage_pvt }, - { "ucode_sig" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmCcGfwProdSigned_GH100_ucode_sig_storage_pvt }, - { "ucode_pkey" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmCcGfwProdSigned_GH100_ucode_pkey_storage_pvt }, - } -}; - -#endif // defined(BINDATA_INCLUDE_ARCHIVE) - - - -#if defined(BINDATA_INCLUDE_FUNCTION) -const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmCcGfwProdSigned_GH100(struct KernelGsp *pKernelGsp) -{ - return &__kgspGetBinArchiveGspRmCcGfwProdSigned_GH100; -} -#endif // defined(BINDATA_INCLUDE_FUNCTION) - - - - - diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c new file mode 100644 index 000000000..83f2ed55c --- /dev/null +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c @@ -0,0 +1,7988 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +/* THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT! */ + + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100("ucode_image") +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dbg_gfw_image.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 124232 +// COMPRESSED SIZE (bytes): 123818 +// +static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_image_data[] = +{ + 0x8c, 0x97, 0xc3, 0x96, 0x28, 0x0a, 0x90, 0x04, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, + 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xee, 0xdb, 0xb6, 0x6d, 0xdb, 0xf3, 0xce, 0x9c, 0xf9, 0x80, 0xc9, + 0x4d, 0xd5, 0x2e, 0x97, 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0xf9, 0x42, 0x5f, 0xac, 0xf5, 0x08, 0x1c, 0x5d, 0x69, 0xa6, + 0xf5, 0x36, 0x76, 0x58, 0x47, 0x54, 0xd1, 0x24, 0x95, 0x39, 0xca, 0x74, 0x02, 0xac, 0x09, 0xc9, + 0x5b, 0xb3, 0xca, 0x45, 0xed, 0x1b, 0x97, 0x07, 0x27, 0xbf, 0xa6, 0x42, 0x3c, 0x0f, 0xe1, 0xa8, + 0x48, 0x70, 0xed, 0xfd, 0xf5, 0x69, 0x0a, 0x8c, 0xf4, 0xae, 0xde, 0x95, 0xf9, 0xf3, 0x7c, 0x11, + 0x67, 0x5a, 0x87, 0x75, 0x34, 0xe4, 0xde, 0xc7, 0xa1, 0xfb, 0xa0, 0x9e, 0x92, 0x8b, 0x56, 0x37, + 0xf0, 0x5f, 0xcd, 0xf9, 0xd1, 0x25, 0x1d, 0xf1, 0x5c, 0x1c, 0x9d, 0x8a, 0x41, 0x29, 0x4e, 0xd5, + 0xe3, 0x59, 0x86, 0xf1, 0x22, 0xc7, 0x99, 0x54, 0x29, 0x36, 0xce, 0x8c, 0x3a, 0x35, 0x55, 0x67, + 0xb4, 0x00, 0x80, 0xd2, 0xc9, 0x07, 0x5d, 0x5e, 0xb5, 0xbe, 0x51, 0xfb, 0x54, 0xb2, 0x3a, 0x00, + 0x76, 0xc6, 0xa1, 0x1d, 0x2c, 0x23, 0x43, 0x8d, 0x50, 0xbb, 0x07, 0x1d, 0x83, 0xa3, 0xd9, 0xca, + 0x33, 0x69, 0x2b, 0x5e, 0x87, 0x11, 0xab, 0x99, 0xfc, 0x56, 0x0f, 0xc3, 0x87, 0xd1, 0x9d, 0xdb, + 0xa1, 0xe0, 0x86, 0x17, 0x97, 0x5f, 0x54, 0xb4, 0xa1, 0x29, 0xab, 0xfc, 0xac, 0x99, 0xbd, 0x98, + 0x84, 0xb7, 0xe3, 0x32, 0x0c, 0xc5, 0x14, 0xc1, 0xcb, 0x15, 0x8b, 0x0d, 0xcc, 0xe5, 0xd2, 0xde, + 0xfe, 0xc0, 0x56, 0xc6, 0x6d, 0x4d, 0x1c, 0x49, 0x73, 0x50, 0x15, 0x82, 0x4a, 0xe5, 0x64, 0x18, + 0x8b, 0xdc, 0x77, 0x8b, 0xbb, 0xd7, 0xd4, 0xc2, 0xed, 0x77, 0x16, 0x0b, 0x0b, 0x24, 0x34, 0xb4, + 0xff, 0x01, 0x16, 0x85, 0xf1, 0xa4, 0x48, 0xe5, 0x01, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_image_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 124232, // uncompressed data size (bytes) + 123818, // compressed data size (bytes) + kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_image_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100("ucode_hash") +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dbg_gfw_hash.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 48 +// COMPRESSED SIZE (bytes): 61 +// +static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_hash_data[] = +{ + 0x01, 0x30, 0x00, 0xcf, 0xff, 0x2b, 0x75, 0x8a, 0x60, 0x87, 0x0c, 0xd1, 0xbb, 0x32, 0x64, 0x8a, + 0xeb, 0x3f, 0xbe, 0xd4, 0x9f, 0xa8, 0xc9, 0x29, 0x0b, 0xdf, 0xb3, 0xc3, 0x97, 0x17, 0x8f, 0x35, + 0x37, 0x4d, 0x72, 0x6f, 0x0e, 0xff, 0x41, 0x07, 0x21, 0x37, 0x13, 0x19, 0x1d, 0x11, 0x09, 0xe4, + 0xda, 0x06, 0xc3, 0x6b, 0x3b, 0x91, 0x02, 0xde, 0xbd, 0x30, 0x00, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_hash_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 48, // uncompressed data size (bytes) + 61, // compressed data size (bytes) + kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_hash_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100("ucode_sig") +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dbg_gfw_sig.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 384 +// COMPRESSED SIZE (bytes): 397 +// +static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_sig_data[] = +{ + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x5e, 0xf8, 0x92, 0xc4, 0x6a, 0x05, 0xe2, 0x40, 0xce, 0x41, 0x1e, + 0x9c, 0x35, 0xcd, 0x6b, 0xa0, 0xe1, 0x8c, 0x7c, 0xb9, 0x78, 0xbd, 0x3d, 0x47, 0x32, 0x1d, 0xa0, + 0x2a, 0xa7, 0x32, 0x0a, 0x69, 0x69, 0x91, 0xd4, 0x8c, 0xa6, 0xb3, 0x8f, 0x93, 0xcf, 0xd4, 0x54, + 0x23, 0x0a, 0xbe, 0xee, 0xa2, 0x61, 0x30, 0x2d, 0xc8, 0x1f, 0xf4, 0x6a, 0x39, 0xa1, 0xbe, 0x06, + 0x34, 0xeb, 0x64, 0x67, 0x7b, 0xe8, 0x04, 0xdd, 0x39, 0x13, 0xcb, 0xb9, 0x56, 0x6a, 0xaa, 0xd5, + 0xfc, 0xb7, 0x96, 0xf7, 0xbd, 0xf0, 0xd1, 0x4a, 0x5c, 0x0c, 0x0b, 0x7e, 0x77, 0x5c, 0x10, 0xc3, + 0x13, 0x85, 0x8f, 0x29, 0x77, 0x6c, 0xc3, 0x1d, 0x19, 0x14, 0xa6, 0x7b, 0x02, 0x29, 0xde, 0x55, + 0x92, 0x8d, 0x7e, 0x73, 0x63, 0x8f, 0x41, 0xc8, 0x9a, 0x36, 0xe0, 0x9d, 0xed, 0x5e, 0x47, 0x09, + 0xdc, 0x3e, 0x51, 0xad, 0xc0, 0x07, 0xef, 0x93, 0x16, 0xe9, 0x06, 0x1e, 0xac, 0xc7, 0xa9, 0xdb, + 0x08, 0xdd, 0x76, 0x7f, 0xb7, 0xdf, 0xc1, 0xc6, 0x19, 0xdf, 0x65, 0x0d, 0x9c, 0x38, 0x1e, 0xb7, + 0x76, 0xaa, 0x09, 0xbf, 0x32, 0xc5, 0x9b, 0xf1, 0x11, 0x22, 0x06, 0x4b, 0xdc, 0x5d, 0x02, 0x4a, + 0xb9, 0xb0, 0x7f, 0x88, 0x3d, 0x9a, 0xf8, 0x2c, 0xf8, 0xcc, 0xfd, 0x20, 0x95, 0x52, 0x09, 0x35, + 0xf5, 0x79, 0xcb, 0x2d, 0x1c, 0xd0, 0xa7, 0xa2, 0x91, 0x15, 0xeb, 0xbc, 0x9f, 0x9b, 0xc5, 0x5c, + 0x34, 0xc1, 0xa8, 0x75, 0x28, 0xb8, 0x71, 0x3d, 0x83, 0x74, 0x1b, 0x15, 0x3b, 0xce, 0x67, 0x45, + 0x0e, 0x43, 0xc0, 0xf0, 0xa8, 0x08, 0x7b, 0xa3, 0x7c, 0x1b, 0xc0, 0x18, 0xb7, 0xe3, 0xe4, 0xac, + 0x42, 0x9d, 0x23, 0x42, 0x5d, 0x8d, 0x9f, 0x0a, 0x10, 0x91, 0x83, 0x50, 0x5f, 0xf9, 0x05, 0x4d, + 0x6c, 0x4b, 0x7c, 0x3d, 0x40, 0x59, 0x04, 0x64, 0xca, 0x4f, 0x7e, 0xbc, 0xb6, 0x5a, 0xe9, 0xb0, + 0xbe, 0x8d, 0xf0, 0x2f, 0x59, 0xf1, 0xce, 0x59, 0x6c, 0xe8, 0x74, 0x3b, 0x52, 0xfa, 0x99, 0xb6, + 0xec, 0x83, 0x01, 0x3b, 0xaa, 0x98, 0x29, 0xe0, 0x37, 0x88, 0x19, 0xed, 0x92, 0xd4, 0xff, 0x86, + 0xaa, 0xa8, 0xf1, 0x3a, 0x24, 0x3e, 0x4e, 0x0b, 0xd7, 0xc5, 0xab, 0x0c, 0x35, 0xf7, 0x12, 0x85, + 0x18, 0xfd, 0x63, 0xb3, 0xa3, 0xe2, 0x00, 0xfe, 0xe9, 0xd3, 0x13, 0xe9, 0xff, 0x3e, 0xb0, 0xd8, + 0x2a, 0x32, 0xa9, 0x31, 0x7c, 0x89, 0x7a, 0xac, 0xf8, 0xac, 0xbe, 0x0c, 0xab, 0xec, 0x59, 0x70, + 0x67, 0x8d, 0xf6, 0x2c, 0x4e, 0x0c, 0x8d, 0x13, 0x19, 0xa9, 0xd0, 0xe4, 0xff, 0x2f, 0xb1, 0xbf, + 0x6e, 0xd6, 0xb2, 0x52, 0x9f, 0x5f, 0x3c, 0x2e, 0xd6, 0x11, 0xb0, 0x81, 0x1a, 0x5f, 0xd3, 0x11, + 0x2a, 0x82, 0x63, 0xe1, 0x16, 0xb3, 0x6f, 0xc1, 0xc9, 0x80, 0x01, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_sig_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 384, // uncompressed data size (bytes) + 397, // compressed data size (bytes) + kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_sig_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100("ucode_pkey") +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dbg_gfw_pub_key.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 384 +// COMPRESSED SIZE (bytes): 397 +// +static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_pkey_data[] = +{ + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0xb1, 0xb2, 0x7a, 0x80, 0x2b, 0x7d, 0x7c, 0xc5, 0x65, 0x9b, 0x93, + 0x52, 0x4d, 0x36, 0x1d, 0xf9, 0x78, 0x50, 0xd6, 0x3f, 0x24, 0xad, 0x30, 0x50, 0x48, 0x5e, 0xe7, + 0x17, 0xea, 0xa5, 0x90, 0xd0, 0x16, 0xf8, 0xb2, 0xf2, 0x8e, 0x5c, 0x85, 0x38, 0x65, 0xab, 0xa7, + 0x28, 0x02, 0xef, 0x55, 0x9f, 0x32, 0x16, 0x19, 0x49, 0xc8, 0x71, 0x8e, 0x5f, 0x2d, 0xf7, 0x48, + 0x75, 0x47, 0xc1, 0x7f, 0xd7, 0x17, 0xb7, 0x8c, 0xbb, 0xad, 0xa7, 0xf2, 0x8b, 0xcb, 0x0f, 0xad, + 0xef, 0x3d, 0x09, 0x88, 0x47, 0x0f, 0x43, 0xdc, 0x6b, 0x0f, 0xc6, 0xac, 0x9e, 0x9e, 0x76, 0x09, + 0xa8, 0xbd, 0xc6, 0xe5, 0x9c, 0x20, 0xc2, 0x60, 0x3f, 0x10, 0xa8, 0xe1, 0x62, 0x91, 0x97, 0x4f, + 0x95, 0x52, 0x3a, 0xd3, 0xa8, 0xfe, 0x66, 0xe4, 0xe4, 0xef, 0xbb, 0xab, 0x20, 0xd8, 0x1b, 0xf2, + 0xc9, 0x04, 0x01, 0x1d, 0x39, 0xe6, 0x3c, 0x1a, 0xe4, 0xfd, 0xb6, 0xd1, 0x18, 0x81, 0x5e, 0x78, + 0xec, 0xee, 0x63, 0xd4, 0x91, 0x3a, 0x05, 0x2c, 0x36, 0x84, 0xbd, 0xb1, 0xfa, 0xb7, 0xf4, 0x5a, + 0xf6, 0xd0, 0x7f, 0x78, 0xe4, 0x16, 0x00, 0x2b, 0xc0, 0xac, 0x9e, 0x89, 0x50, 0x78, 0xbb, 0xe7, + 0x4d, 0x9d, 0xf4, 0xc9, 0xfe, 0xb7, 0x29, 0x65, 0x6f, 0x33, 0x91, 0x2c, 0x3a, 0x7d, 0x8e, 0xc5, + 0x84, 0xd6, 0x55, 0x3b, 0x79, 0x0c, 0xea, 0x93, 0x9f, 0x64, 0x49, 0x1a, 0xf5, 0x2c, 0xc8, 0x10, + 0x92, 0x90, 0xb1, 0xe3, 0x0e, 0xd0, 0xf4, 0xad, 0x11, 0x3b, 0x20, 0xb1, 0x2d, 0xc7, 0xa6, 0x6e, + 0xd3, 0x9c, 0x67, 0x49, 0x3e, 0xad, 0xea, 0x44, 0x09, 0x96, 0x96, 0xce, 0x1e, 0x7a, 0xcd, 0x40, + 0x30, 0xa2, 0xdb, 0xce, 0x60, 0x19, 0xd8, 0x8d, 0x96, 0x5e, 0x0c, 0x30, 0xcd, 0xe3, 0xcb, 0x02, + 0x3e, 0x2b, 0x26, 0x38, 0x2b, 0x2c, 0x09, 0xa6, 0xc8, 0xad, 0xbb, 0xde, 0x67, 0x33, 0xaf, 0x53, + 0x72, 0x7c, 0x77, 0xe2, 0xb8, 0xe2, 0xe0, 0x11, 0xb8, 0x26, 0xe7, 0x92, 0x29, 0x8b, 0xe1, 0xef, + 0x6a, 0x7e, 0x49, 0x09, 0x37, 0xde, 0x61, 0xc5, 0xeb, 0x11, 0x72, 0x47, 0x85, 0x2a, 0x66, 0x6c, + 0x5f, 0x02, 0xb5, 0x86, 0x82, 0x81, 0x56, 0x8e, 0x1c, 0xa4, 0xf8, 0xab, 0x7e, 0x1f, 0x9b, 0x84, + 0x5b, 0xdd, 0xc1, 0x7d, 0x62, 0xa1, 0xd2, 0x96, 0xc8, 0x1e, 0x2f, 0x32, 0xcd, 0x18, 0x0d, 0x6c, + 0x4a, 0x1c, 0xa0, 0x82, 0x74, 0x28, 0x15, 0xf9, 0xa1, 0x65, 0x52, 0x03, 0x8a, 0x7f, 0x0d, 0xff, + 0xd1, 0x15, 0x04, 0x99, 0x7d, 0xd8, 0xa3, 0x04, 0xe3, 0x22, 0x60, 0x40, 0x74, 0xf6, 0x08, 0x48, + 0x24, 0xe8, 0xbc, 0x54, 0x19, 0x3c, 0xc4, 0x38, 0xfc, 0xa9, 0x5e, 0x92, 0xa4, 0xae, 0x0a, 0x8a, + 0xef, 0xca, 0x63, 0x96, 0x9d, 0xf3, 0x87, 0x94, 0x2b, 0x80, 0x01, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_pkey_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 384, // uncompressed data size (bytes) + 397, // compressed data size (bytes) + kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_pkey_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_ARCHIVE) +// +// Bindata Archive structure +// +static const BINDATA_ARCHIVE __kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100 = +{ + 4, // entryNum + { + // entries[] : { "name", pBinStorage } + { "ucode_image" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_image_storage_pvt }, + { "ucode_hash" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_hash_storage_pvt }, + { "ucode_sig" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_sig_storage_pvt }, + { "ucode_pkey" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_pkey_storage_pvt }, + } +}; + +#endif // defined(BINDATA_INCLUDE_ARCHIVE) + + + +#if defined(BINDATA_INCLUDE_FUNCTION) +const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100(struct KernelGsp *pKernelGsp) +{ + return &__kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION) + + +#if defined(BINDATA_INCLUDE_FUNCTION_STUB) +const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100(struct KernelGsp *pKernelGsp) +{ + return NULL; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION_STUB) + + + + + diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c new file mode 100644 index 000000000..a47fe4e80 --- /dev/null +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c @@ -0,0 +1,8012 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +/* THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT! */ + + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100("ucode_image") +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_prd_gfw_image.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 124232 +// COMPRESSED SIZE (bytes): 124201 +// +static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_image_data[] = +{ + 0x00, 0x4c, 0x80, 0xb3, 0x7f, 0x03, 0x04, 0x48, 0x00, 0x00, 0xe5, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x62, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x79, 0x00, 0x00, 0x04, 0x01, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa4, 0xed, 0x6f, + 0x66, 0x9c, 0x74, 0x5c, 0xac, 0xbb, 0xb9, 0xfb, 0x0a, 0x46, 0xe2, 0x3e, 0x88, 0x73, 0xa6, 0xc8, + 0x6a, 0x11, 0x66, 0x1f, 0xe5, 0x88, 0x0b, 0x40, 0x92, 0x29, 0x92, 0x0e, 0x18, 0xee, 0xc3, 0x8c, + 0xc6, 0xf8, 0xc6, 0xbd, 0xa3, 0x41, 0x72, 0x34, 0x62, 0x93, 0xc9, 0x40, 0xea, 0x0d, 0x03, 0x1a, + 0x04, 0x73, 0x3b, 0x68, 0x17, 0x33, 0x67, 0x75, 0xe6, 0xe5, 0x13, 0xc5, 0x7f, 0x55, 0x07, 0x08, + 0x5f, 0x38, 0x64, 0xd9, 0x77, 0xca, 0x66, 0xb3, 0x22, 0xd8, 0xdd, 0xd6, 0x6c, 0x03, 0x53, 0xe3, + 0x55, 0xf6, 0x0a, 0x07, 0xe3, 0xba, 0x03, 0x8e, 0x82, 0xf4, 0x7e, 0x9e, 0x0e, 0xa7, 0xd7, 0x51, + 0x74, 0x30, 0xea, 0x85, 0xd1, 0x7d, 0x24, 0xa9, 0x25, 0x96, 0x74, 0x91, 0x11, 0x91, 0x7c, 0xa2, + 0xe7, 0xf2, 0xa8, 0x67, 0xed, 0x7a, 0x4b, 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0x39, 0x36, 0x2b, 0xa1, 0xd7, 0x9e, 0x63, + 0x0e, 0x19, 0xf4, 0x98, 0x34, 0x02, 0x32, 0xde, 0xb1, 0xe1, 0xea, 0xf6, 0xf0, 0x44, 0xce, 0xbe, + 0x81, 0xc1, 0xaf, 0x70, 0xe5, 0x31, 0xdb, 0xa8, 0x07, 0x7b, 0x6f, 0xd3, 0x00, 0x51, 0x8f, 0x1c, + 0x81, 0x14, 0x39, 0x85, 0xd1, 0xf7, 0x21, 0xbf, 0x3a, 0xde, 0x3c, 0x10, 0xe7, 0x0b, 0xca, 0xc2, + 0x66, 0x78, 0xec, 0xa7, 0x02, 0xd5, 0x4e, 0xb5, 0x4d, 0xf2, 0x41, 0xc2, 0x96, 0x91, 0x74, 0x53, + 0x04, 0xb1, 0xa7, 0x21, 0x87, 0xb8, 0xb7, 0x80, 0xfc, 0x16, 0xc4, 0x48, 0xb0, 0xa6, 0xdc, 0xf4, + 0x97, 0xfc, 0x04, 0x57, 0x3f, 0x16, 0x12, 0xde, 0x72, 0x43, 0x12, 0x70, 0xde, 0x97, 0xe0, 0x22, + 0xc1, 0xb6, 0x5e, 0xfa, 0xb2, 0xa4, 0x21, 0x8f, 0x16, 0x8a, 0x62, 0x47, 0xa6, 0xc2, 0x08, 0x5f, + 0x64, 0x77, 0x30, 0xa3, 0x83, 0x2e, 0x26, 0x62, 0xa7, 0x06, 0x4c, 0x33, 0x9b, 0xe8, 0x86, 0x26, + 0x2f, 0x41, 0x8f, 0xf2, 0x03, 0x98, 0x79, 0x1d, 0xc9, 0x24, 0xe8, 0x5d, 0x33, 0x07, 0xc3, 0xc2, + 0xf1, 0x3d, 0xb6, 0x0c, 0xed, 0xc6, 0xa4, 0x07, 0xac, 0xeb, 0x55, 0x12, 0x94, 0x33, 0x81, 0x2d, + 0xd1, 0xb8, 0x14, 0xab, 0xef, 0xa6, 0x0d, 0x86, 0x83, 0xfc, 0x09, 0x43, 0x24, 0x71, 0x5d, 0x24, + 0x1d, 0xae, 0x29, 0x68, 0x18, 0x05, 0x98, 0x62, 0x32, 0xef, 0x37, 0xf8, 0x28, 0x29, 0xb9, 0xa6, + 0x67, 0xb7, 0x0a, 0xdf, 0x45, 0x2c, 0x73, 0x34, 0xe8, 0x70, 0x35, 0xf5, 0xb2, 0x49, 0xf8, 0x8c, + 0x11, 0x3b, 0x3d, 0x2d, 0xdb, 0x88, 0x54, 0x88, 0x58, 0x17, 0x4d, 0xb8, 0x72, 0x57, 0xa0, 0xc5, + 0xbe, 0x3c, 0xc0, 0x58, 0x9f, 0xb8, 0x9d, 0x5e, 0x87, 0xee, 0x7a, 0x2d, 0x3f, 0xe4, 0xac, 0x6d, + 0x2d, 0x37, 0x48, 0xce, 0x88, 0x03, 0x64, 0x4c, 0x91, 0x9f, 0x42, 0x09, 0x4c, 0x6c, 0xe6, 0x0d, + 0x51, 0x86, 0xf6, 0x9c, 0x78, 0x57, 0x0b, 0xe7, 0x8b, 0x7f, 0xb0, 0x8e, 0xf8, 0x43, 0xc7, 0xce, + 0xe2, 0xf9, 0xdb, 0xf0, 0x46, 0x17, 0x5c, 0x7b, 0xcb, 0x9a, 0xf7, 0x3c, 0x3b, 0x42, 0x34, 0xf3, + 0x2f, 0xd4, 0x11, 0xa0, 0x99, 0xca, 0x4f, 0x7f, 0x72, 0xe3, 0x17, 0x22, 0x78, 0x78, 0x82, 0xff, + 0x03, 0x43, 0xc5, 0xc0, 0x71, 0xa3, 0x22, 0x62, 0x0d, 0x9b, 0x05, 0x4f, 0xc3, 0x39, 0xc8, 0xeb, + 0x2b, 0x56, 0x1f, 0xef, 0xf6, 0x30, 0xdf, 0x49, 0xa7, 0xb9, 0x6e, 0xd4, 0xf6, 0x99, 0xb9, 0xea, + 0xfb, 0x9d, 0x5f, 0x5b, 0x8a, 0x83, 0x7c, 0xb5, 0x7d, 0xda, 0x0c, 0xc2, 0x8c, 0xb4, 0x84, 0x8e, + 0x36, 0x65, 0x56, 0x89, 0x43, 0xf2, 0xff, 0x9f, 0x67, 0xd0, 0xf4, 0x4f, 0x6e, 0xf4, 0x6b, 0x21, + 0x8d, 0x66, 0x3b, 0x7a, 0x62, 0xc1, 0x58, 0x94, 0xba, 0xd3, 0xf6, 0xaa, 0x17, 0x86, 0x5c, 0xc7, + 0x96, 0xed, 0x2f, 0x25, 0xd1, 0x52, 0x17, 0x89, 0x1c, 0x82, 0xaa, 0x59, 0xa8, 0x1f, 0x6e, 0x70, + 0xef, 0x9d, 0xf8, 0x77, 0xe5, 0xf7, 0x23, 0xf1, 0xfd, 0xbc, 0x0a, 0xb4, 0x4d, 0xfe, 0x06, 0xd0, + 0x87, 0xc0, 0xb7, 0xa7, 0x0c, 0x34, 0x1f, 0xb1, 0x68, 0x77, 0x0e, 0xd2, 0x2d, 0x61, 0x23, 0xff, + 0x03, 0x04, 0x35, 0x03, 0xf4, 0x48, 0xe5, 0x01, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_image_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 124232, // uncompressed data size (bytes) + 124201, // compressed data size (bytes) + kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_image_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100("ucode_hash") +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_prd_gfw_hash.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 48 +// COMPRESSED SIZE (bytes): 61 +// +static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_hash_data[] = +{ + 0x01, 0x30, 0x00, 0xcf, 0xff, 0x3a, 0x5c, 0x79, 0x51, 0x33, 0xff, 0xd2, 0xd0, 0xdf, 0xa9, 0x6f, + 0x62, 0x3e, 0xd3, 0xa9, 0x0c, 0x87, 0x97, 0x2e, 0x70, 0x62, 0x43, 0xb1, 0x89, 0xf5, 0x67, 0x58, + 0xaa, 0xa9, 0xc4, 0xd5, 0x68, 0x03, 0x39, 0xaa, 0xfb, 0x3c, 0xeb, 0x11, 0x81, 0xc6, 0xc8, 0xc7, + 0x34, 0xc4, 0x85, 0x59, 0xf0, 0x0f, 0xcb, 0x74, 0x60, 0x30, 0x00, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_hash_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 48, // uncompressed data size (bytes) + 61, // compressed data size (bytes) + kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_hash_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100("ucode_sig") +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_prd_gfw_sig.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 384 +// COMPRESSED SIZE (bytes): 397 +// +static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_sig_data[] = +{ + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x2b, 0xe3, 0x35, 0xee, 0x18, 0xdf, 0xca, 0x3f, 0x66, 0x20, 0xb4, + 0x53, 0x84, 0x89, 0xed, 0xc2, 0x25, 0x72, 0x05, 0xb2, 0xd8, 0x19, 0x8e, 0xab, 0xe0, 0x90, 0xc8, + 0x7c, 0x2e, 0x9c, 0xbc, 0x6a, 0x37, 0x8b, 0xdc, 0x43, 0x37, 0xaf, 0x0c, 0x43, 0xc3, 0xd2, 0xbf, + 0xb2, 0xc7, 0xef, 0xea, 0x90, 0x17, 0x89, 0x2d, 0x3f, 0xca, 0x9f, 0xb8, 0xe8, 0xe7, 0xad, 0xf9, + 0x50, 0xe9, 0xa3, 0xc9, 0x92, 0x94, 0xd8, 0x2b, 0x21, 0x75, 0x67, 0xad, 0x34, 0xae, 0x5b, 0xbf, + 0x91, 0x5d, 0x15, 0x96, 0x15, 0x45, 0xf8, 0xfd, 0xf7, 0x2f, 0xcd, 0x0e, 0xb4, 0x18, 0x46, 0x82, + 0x08, 0x96, 0xa2, 0x6a, 0x2f, 0x1a, 0x6e, 0x6a, 0xfa, 0xcb, 0x56, 0x90, 0x29, 0x68, 0x9a, 0xff, + 0xec, 0x05, 0x60, 0x12, 0x6d, 0x0c, 0x0e, 0x87, 0xff, 0xb0, 0x3f, 0xd6, 0xdf, 0xaa, 0xf9, 0x5f, + 0x63, 0x32, 0xef, 0x76, 0x90, 0x18, 0x0a, 0xac, 0x36, 0x2a, 0xc9, 0xe1, 0x5a, 0x52, 0xe6, 0x00, + 0x2a, 0x41, 0x07, 0x9d, 0x7d, 0x62, 0x28, 0x90, 0x4f, 0x4a, 0x36, 0x8d, 0xec, 0xa4, 0x30, 0xeb, + 0x1f, 0x26, 0xe6, 0x28, 0xa7, 0x1d, 0xa9, 0x72, 0x30, 0xa9, 0x24, 0x05, 0x7c, 0x03, 0xd2, 0x6d, + 0x34, 0x1f, 0x4d, 0x1c, 0xdb, 0xb8, 0xd4, 0x61, 0x72, 0x05, 0xc9, 0xa5, 0xc2, 0xed, 0xda, 0xdc, + 0x37, 0xd1, 0x2f, 0x14, 0x34, 0xe9, 0x2a, 0xb5, 0xc1, 0x2d, 0xb4, 0x3d, 0x6e, 0xbf, 0x88, 0x8b, + 0x1a, 0x6f, 0xb2, 0xd2, 0xd7, 0x5d, 0xe3, 0x29, 0x32, 0xd8, 0xed, 0x38, 0x67, 0x2c, 0x58, 0x28, + 0x4f, 0x8a, 0x29, 0x82, 0xfb, 0x08, 0x7b, 0x4b, 0xa9, 0x45, 0xb8, 0x44, 0x00, 0x3a, 0x0e, 0xb2, + 0xc4, 0xca, 0x23, 0xea, 0x40, 0x8e, 0xe9, 0xb4, 0x28, 0xfb, 0x40, 0x91, 0x40, 0x51, 0xa2, 0xdd, + 0x16, 0xfb, 0x26, 0xd4, 0x92, 0x57, 0x17, 0xe9, 0xaf, 0x66, 0xc9, 0xfe, 0xd5, 0xc9, 0x7c, 0xf5, + 0x66, 0x4c, 0x54, 0x6f, 0x9d, 0x0b, 0x64, 0x55, 0x5c, 0x20, 0xc7, 0x83, 0x77, 0xd4, 0x01, 0x70, + 0x1c, 0xe1, 0x0b, 0xe2, 0xd8, 0x23, 0xfa, 0x31, 0x5a, 0xd1, 0xa5, 0x67, 0x50, 0x96, 0x8f, 0x02, + 0x83, 0xa8, 0x07, 0x8c, 0xef, 0xba, 0x3e, 0x4d, 0x88, 0xe4, 0x54, 0xeb, 0x0c, 0xca, 0x31, 0x8d, + 0xfd, 0x26, 0xcd, 0x31, 0x02, 0xbc, 0x81, 0x6b, 0x51, 0x21, 0x60, 0x11, 0x69, 0xeb, 0x35, 0x9f, + 0xa1, 0x1d, 0x8c, 0x10, 0xfa, 0xb8, 0xd6, 0x1f, 0xe8, 0x41, 0x32, 0xdc, 0x9e, 0xfb, 0x9e, 0xc4, + 0x3b, 0x80, 0xd9, 0x11, 0x71, 0x98, 0x39, 0x6c, 0xbb, 0x35, 0xa2, 0xbe, 0xab, 0xef, 0x57, 0xf8, + 0xd0, 0x1d, 0x47, 0x62, 0xdc, 0x0b, 0x54, 0xdd, 0x50, 0x12, 0x1a, 0x1f, 0x01, 0xba, 0x1d, 0xf0, + 0x30, 0x62, 0xd3, 0xa4, 0xd9, 0xf5, 0xdd, 0xce, 0x1d, 0x80, 0x01, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_sig_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 384, // uncompressed data size (bytes) + 397, // compressed data size (bytes) + kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_sig_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100("ucode_pkey") +// FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_prd_gfw_pub_key.bin +// FILE TYPE: BINARY +// VAR NAME: N/A +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 384 +// COMPRESSED SIZE (bytes): 397 +// +static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_pkey_data[] = +{ + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0xb6, 0x61, 0x74, 0x8c, 0x50, 0xfd, 0x5d, 0x6b, 0xbc, 0x71, 0xe9, + 0xcf, 0x5e, 0xf6, 0x8b, 0x5d, 0xd5, 0x36, 0xe8, 0xaf, 0xca, 0x7a, 0x14, 0x6a, 0x3d, 0x1f, 0xa6, + 0x8b, 0x37, 0xf9, 0x3e, 0x5a, 0x44, 0xec, 0xb6, 0x6a, 0x39, 0x25, 0x78, 0xce, 0xd6, 0xf0, 0xe2, + 0xa1, 0x40, 0xae, 0x82, 0x22, 0x60, 0xaa, 0xf3, 0x6a, 0xd3, 0x4d, 0xe6, 0xc1, 0x38, 0x18, 0x4e, + 0xfc, 0xd6, 0x6c, 0x61, 0x38, 0x73, 0x13, 0x26, 0x71, 0xa8, 0xb8, 0x9c, 0xeb, 0x07, 0x28, 0x4e, + 0x86, 0x2b, 0xe2, 0x5e, 0xf8, 0xfd, 0x2c, 0x01, 0x51, 0x6f, 0x1c, 0xf9, 0x47, 0x36, 0x62, 0xcc, + 0x59, 0x24, 0x67, 0xf8, 0x5d, 0x13, 0x39, 0x52, 0xd9, 0x0b, 0xbf, 0x92, 0x98, 0xad, 0x98, 0x2b, + 0x53, 0x4d, 0x35, 0xda, 0x06, 0x7e, 0x89, 0x07, 0x2f, 0xb0, 0x0f, 0x12, 0x44, 0x1d, 0xe8, 0xa8, + 0xed, 0x40, 0x9c, 0x84, 0x8a, 0x99, 0x7e, 0x09, 0x05, 0xee, 0x9c, 0x62, 0x2a, 0x6e, 0xdb, 0xe3, + 0xc2, 0x7c, 0x39, 0x7c, 0xdb, 0x30, 0x49, 0x26, 0x58, 0xf1, 0x94, 0xa6, 0xd1, 0x8b, 0xda, 0x79, + 0x18, 0xed, 0x12, 0xdf, 0x72, 0xfd, 0x5b, 0x3d, 0x13, 0xab, 0xcc, 0xce, 0x20, 0x80, 0xd8, 0xe7, + 0x5d, 0x6c, 0xcf, 0x3e, 0x3a, 0x7c, 0x29, 0xda, 0xf4, 0xdb, 0x7a, 0xc0, 0x2a, 0x4d, 0xc7, 0xdc, + 0xe8, 0x09, 0xe6, 0x2a, 0xca, 0x6c, 0x33, 0xed, 0xf1, 0x96, 0xe5, 0x26, 0xb0, 0xc6, 0xcc, 0x22, + 0x15, 0xd2, 0x42, 0x47, 0x71, 0xe5, 0x6d, 0x2e, 0xda, 0xcd, 0x1d, 0x28, 0x59, 0xe9, 0x4d, 0x48, + 0xca, 0x36, 0xd4, 0x85, 0x6a, 0x26, 0x8e, 0x3e, 0xc7, 0xd7, 0x14, 0x77, 0x5e, 0x54, 0xda, 0x98, + 0xf8, 0x65, 0xaf, 0xea, 0x63, 0x46, 0xcd, 0xca, 0xd0, 0xbf, 0x9e, 0x31, 0xb2, 0x24, 0x7f, 0x4e, + 0xe5, 0xa3, 0x32, 0x5e, 0x22, 0x3a, 0xed, 0xed, 0xbe, 0xad, 0x5e, 0xa2, 0x36, 0x07, 0x41, 0x7f, + 0x94, 0x7b, 0x6f, 0x77, 0xea, 0xf6, 0xf3, 0x4e, 0xd3, 0x47, 0x39, 0x9c, 0xd0, 0x96, 0x70, 0x78, + 0x0c, 0x30, 0x9a, 0xa7, 0xe7, 0x85, 0x7e, 0xa6, 0xce, 0x00, 0x86, 0xfb, 0x91, 0xef, 0xe3, 0x31, + 0x1f, 0xc1, 0x5e, 0xda, 0xf3, 0x59, 0xdd, 0x36, 0xfe, 0x19, 0x2b, 0xca, 0xa4, 0x46, 0x5a, 0x52, + 0xaa, 0x65, 0x31, 0x00, 0x0b, 0x61, 0x57, 0x30, 0x8b, 0x0d, 0x13, 0xe6, 0xdc, 0xb3, 0x64, 0x61, + 0x98, 0x07, 0x52, 0xbc, 0x3e, 0x05, 0x26, 0x84, 0x96, 0xd0, 0x85, 0x62, 0x72, 0xd3, 0x9f, 0x60, + 0xf9, 0xc1, 0x33, 0x69, 0x1b, 0x49, 0x3e, 0x74, 0x08, 0x51, 0x2e, 0x97, 0x1b, 0x45, 0x54, 0x7c, + 0x4b, 0xd1, 0x51, 0x83, 0xaa, 0xf0, 0x9b, 0xff, 0x0c, 0xfb, 0x2f, 0x33, 0xcd, 0xe5, 0x1b, 0xcf, + 0x4f, 0x02, 0x0d, 0xf6, 0x1b, 0xdb, 0x48, 0x80, 0x58, 0x80, 0x01, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_pkey_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 384, // uncompressed data size (bytes) + 397, // compressed data size (bytes) + kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_pkey_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_ARCHIVE) +// +// Bindata Archive structure +// +static const BINDATA_ARCHIVE __kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100 = +{ + 4, // entryNum + { + // entries[] : { "name", pBinStorage } + { "ucode_image" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_image_storage_pvt }, + { "ucode_hash" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_hash_storage_pvt }, + { "ucode_sig" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_sig_storage_pvt }, + { "ucode_pkey" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_pkey_storage_pvt }, + } +}; + +#endif // defined(BINDATA_INCLUDE_ARCHIVE) + + + +#if defined(BINDATA_INCLUDE_FUNCTION) +const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100(struct KernelGsp *pKernelGsp) +{ + return &__kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION) + + +#if defined(BINDATA_INCLUDE_FUNCTION_STUB) +const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100(struct KernelGsp *pKernelGsp) +{ + return NULL; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION_STUB) + + + + + diff --git a/src/nvidia/generated/g_bindata_ksec2GetBinArchiveBlUcode_TU102.c b/src/nvidia/generated/g_bindata_ksec2GetBinArchiveBlUcode_TU102.c index 011591088..d0ec7fa9c 100644 --- a/src/nvidia/generated/g_bindata_ksec2GetBinArchiveBlUcode_TU102.c +++ b/src/nvidia/generated/g_bindata_ksec2GetBinArchiveBlUcode_TU102.c @@ -142,6 +142,14 @@ const BINDATA_ARCHIVE *ksec2GetBinArchiveBlUcode_TU102(struct KernelSec2 *pKerne #endif // defined(BINDATA_INCLUDE_FUNCTION) +#if defined(BINDATA_INCLUDE_FUNCTION_STUB) +const BINDATA_ARCHIVE *ksec2GetBinArchiveBlUcode_TU102(struct KernelSec2 *pKernelSec2) +{ + return NULL; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION_STUB) + + diff --git a/src/nvidia/generated/g_channel_descendant_nvoc.c b/src/nvidia/generated/g_channel_descendant_nvoc.c index 8bbcdf94f..5e19349cf 100644 --- a/src/nvidia/generated/g_channel_descendant_nvoc.c +++ b/src/nvidia/generated/g_channel_descendant_nvoc.c @@ -203,6 +203,10 @@ static void __nvoc_thunk_RsResource_chandesPreDestruct(struct ChannelDescendant resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ChannelDescendant_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_RsResource_chandesIsDuplicate(struct ChannelDescendant *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ChannelDescendant_RsResource.offset), hMemory, pDuplicate); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_chandesGetNotificationListPtr(struct ChannelDescendant *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_ChannelDescendant_Notifier.offset)); } @@ -327,6 +331,8 @@ static void __nvoc_init_funcTable_ChannelDescendant_1(ChannelDescendant *pThis, pThis->__chandesPreDestruct__ = &__nvoc_thunk_RsResource_chandesPreDestruct; + pThis->__chandesIsDuplicate__ = &__nvoc_thunk_RsResource_chandesIsDuplicate; + pThis->__chandesGetNotificationListPtr__ = &__nvoc_thunk_Notifier_chandesGetNotificationListPtr; pThis->__chandesGetNotificationShare__ = &__nvoc_thunk_Notifier_chandesGetNotificationShare; diff --git a/src/nvidia/generated/g_channel_descendant_nvoc.h b/src/nvidia/generated/g_channel_descendant_nvoc.h index 2d9f1db87..7980f95f2 100644 --- a/src/nvidia/generated/g_channel_descendant_nvoc.h +++ b/src/nvidia/generated/g_channel_descendant_nvoc.h @@ -147,6 +147,7 @@ struct ChannelDescendant { NV_STATUS (*__chandesUnregisterEvent__)(struct ChannelDescendant *, NvHandle, NvHandle, NvHandle, NvHandle); NvBool (*__chandesCanCopy__)(struct ChannelDescendant *); void (*__chandesPreDestruct__)(struct ChannelDescendant *); + NV_STATUS (*__chandesIsDuplicate__)(struct ChannelDescendant *, NvHandle, NvBool *); PEVENTNOTIFICATION *(*__chandesGetNotificationListPtr__)(struct ChannelDescendant *); struct NotifShare *(*__chandesGetNotificationShare__)(struct ChannelDescendant *); NV_STATUS (*__chandesMap__)(struct ChannelDescendant *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -211,6 +212,7 @@ NV_STATUS __nvoc_objCreate_ChannelDescendant(ChannelDescendant**, Dynamic*, NvU3 #define chandesUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) chandesUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define chandesCanCopy(pResource) chandesCanCopy_DISPATCH(pResource) #define chandesPreDestruct(pResource) chandesPreDestruct_DISPATCH(pResource) +#define chandesIsDuplicate(pResource, hMemory, pDuplicate) chandesIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define chandesGetNotificationListPtr(pNotifier) chandesGetNotificationListPtr_DISPATCH(pNotifier) #define chandesGetNotificationShare(pNotifier) chandesGetNotificationShare_DISPATCH(pNotifier) #define chandesMap(pGpuResource, pCallContext, pParams, pCpuMapping) chandesMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -219,6 +221,7 @@ static inline void chandesIsolateOnDestruct_b3696a(struct ChannelDescendant *pCh return; } + #ifdef __nvoc_channel_descendant_h_disabled static inline void chandesIsolateOnDestruct(struct ChannelDescendant *pChannelDescendant) { NV_ASSERT_FAILED_PRECOMP("ChannelDescendant was disabled!"); @@ -233,6 +236,7 @@ static inline void chandesDestroy_b3696a(struct ChannelDescendant *pChannelDesce return; } + #ifdef __nvoc_channel_descendant_h_disabled static inline void chandesDestroy(struct ChannelDescendant *pChannelDescendant) { NV_ASSERT_FAILED_PRECOMP("ChannelDescendant was disabled!"); @@ -349,6 +353,10 @@ static inline void chandesPreDestruct_DISPATCH(struct ChannelDescendant *pResour pResource->__chandesPreDestruct__(pResource); } +static inline NV_STATUS chandesIsDuplicate_DISPATCH(struct ChannelDescendant *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__chandesIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline PEVENTNOTIFICATION *chandesGetNotificationListPtr_DISPATCH(struct ChannelDescendant *pNotifier) { return pNotifier->__chandesGetNotificationListPtr__(pNotifier); } @@ -366,8 +374,10 @@ static inline NvBool chandesAccessCallback_DISPATCH(struct ChannelDescendant *pR } NV_STATUS chandesConstruct_IMPL(struct ChannelDescendant *arg_pChannelDescendant, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams, PARAM_TO_ENGDESC_FUNCTION *arg_pParamToEngDescFn); + #define __nvoc_chandesConstruct(arg_pChannelDescendant, arg_pCallContext, arg_pParams, arg_pParamToEngDescFn) chandesConstruct_IMPL(arg_pChannelDescendant, arg_pCallContext, arg_pParams, arg_pParamToEngDescFn) void chandesDestruct_IMPL(struct ChannelDescendant *pChannelDescendant); + #define __nvoc_chandesDestruct(pChannelDescendant) chandesDestruct_IMPL(pChannelDescendant) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_chips2halspec_nvoc.c b/src/nvidia/generated/g_chips2halspec_nvoc.c index 210fc7ffe..14461df74 100644 --- a/src/nvidia/generated/g_chips2halspec_nvoc.c +++ b/src/nvidia/generated/g_chips2halspec_nvoc.c @@ -79,10 +79,20 @@ void __nvoc_init_halspec_ChipHal(ChipHal *pChipHal, NvU32 arch, NvU32 impl, NvU3 { pChipHal->__nvoc_HalVarIdx = 54; } + // AD106 + else if(arch == 0x19 && impl == 0x6) + { + pChipHal->__nvoc_HalVarIdx = 55; + } + // AD107 + else if(arch == 0x19 && impl == 0x7) + { + pChipHal->__nvoc_HalVarIdx = 56; + } // GH100 else if(arch == 0x18 && impl == 0x0) { - pChipHal->__nvoc_HalVarIdx = 59; + pChipHal->__nvoc_HalVarIdx = 60; } } diff --git a/src/nvidia/generated/g_chips2halspec_nvoc.h b/src/nvidia/generated/g_chips2halspec_nvoc.h index 01e8af72a..00cb4ffae 100644 --- a/src/nvidia/generated/g_chips2halspec_nvoc.h +++ b/src/nvidia/generated/g_chips2halspec_nvoc.h @@ -99,8 +99,8 @@ void __nvoc_init_halspec_DispIpHal(DispIpHal*, NvU32); // delete ~DISPv0400 & (TU102 | TU104 | TU106 | TU116 | TU117); // delete DISPv0401 & ~(GA102 | GA103 | GA104 | GA106 | GA107); // delete ~DISPv0401 & (GA102 | GA103 | GA104 | GA106 | GA107); -// delete DISPv0404 & ~(AD102 | AD103 | AD104); -// delete ~DISPv0404 & (AD102 | AD103 | AD104); +// delete DISPv0404 & ~(AD102 | AD103 | AD104 | AD106 | AD107); +// delete ~DISPv0404 & (AD102 | AD103 | AD104 | AD106 | AD107); /* DPU IP versions */ diff --git a/src/nvidia/generated/g_chipset_nvoc.h b/src/nvidia/generated/g_chipset_nvoc.h index f06fd1a38..a2c006934 100644 --- a/src/nvidia/generated/g_chipset_nvoc.h +++ b/src/nvidia/generated/g_chipset_nvoc.h @@ -410,6 +410,7 @@ NV_STATUS __nvoc_objCreate_OBJCL(OBJCL**, Dynamic*, NvU32); NV_STATUS clInit_IMPL(struct OBJGPU *arg0, struct OBJCL *pCl); + #ifdef __nvoc_chipset_h_disabled static inline NV_STATUS clInit(struct OBJGPU *arg0, struct OBJCL *pCl) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -423,6 +424,7 @@ static inline NV_STATUS clInit(struct OBJGPU *arg0, struct OBJCL *pCl) { void clUpdateConfig_IMPL(struct OBJGPU *arg0, struct OBJCL *pCl); + #ifdef __nvoc_chipset_h_disabled static inline void clUpdateConfig(struct OBJGPU *arg0, struct OBJCL *pCl) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -435,6 +437,7 @@ static inline void clUpdateConfig(struct OBJGPU *arg0, struct OBJCL *pCl) { NV_STATUS clTeardown_IMPL(struct OBJGPU *arg0, struct OBJCL *pCl); + #ifdef __nvoc_chipset_h_disabled static inline NV_STATUS clTeardown(struct OBJGPU *arg0, struct OBJCL *pCl) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -448,6 +451,7 @@ static inline NV_STATUS clTeardown(struct OBJGPU *arg0, struct OBJCL *pCl) { void clInitPropertiesFromRegistry_IMPL(struct OBJGPU *arg0, struct OBJCL *pCl); + #ifdef __nvoc_chipset_h_disabled static inline void clInitPropertiesFromRegistry(struct OBJGPU *arg0, struct OBJCL *pCl) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -460,6 +464,7 @@ static inline void clInitPropertiesFromRegistry(struct OBJGPU *arg0, struct OBJC NV_STATUS clGetFHBHandle_IMPL(struct OBJCL *arg0, void **arg1, NvU16 *arg2, NvU16 *arg3); + #ifdef __nvoc_chipset_h_disabled static inline NV_STATUS clGetFHBHandle(struct OBJCL *arg0, void **arg1, NvU16 *arg2, NvU16 *arg3) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -473,6 +478,7 @@ static inline NV_STATUS clGetFHBHandle(struct OBJCL *arg0, void **arg1, NvU16 *a NvU32 clInitMappingPciBusDevice_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1); + #ifdef __nvoc_chipset_h_disabled static inline NvU32 clInitMappingPciBusDevice(struct OBJGPU *arg0, struct OBJCL *arg1) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -486,6 +492,7 @@ static inline NvU32 clInitMappingPciBusDevice(struct OBJGPU *arg0, struct OBJCL NV_STATUS clFindFHBAndGetChipsetInfoIndex_IMPL(struct OBJCL *arg0, NvU16 *arg1); + #ifdef __nvoc_chipset_h_disabled static inline NV_STATUS clFindFHBAndGetChipsetInfoIndex(struct OBJCL *arg0, NvU16 *arg1) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -499,6 +506,7 @@ static inline NV_STATUS clFindFHBAndGetChipsetInfoIndex(struct OBJCL *arg0, NvU1 NV_STATUS clInitPcie_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1); + #ifdef __nvoc_chipset_h_disabled static inline NV_STATUS clInitPcie(struct OBJGPU *arg0, struct OBJCL *arg1) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -512,6 +520,7 @@ static inline NV_STATUS clInitPcie(struct OBJGPU *arg0, struct OBJCL *arg1) { void clUpdatePcieConfig_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1); + #ifdef __nvoc_chipset_h_disabled static inline void clUpdatePcieConfig(struct OBJGPU *arg0, struct OBJCL *arg1) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -524,6 +533,7 @@ static inline void clUpdatePcieConfig(struct OBJGPU *arg0, struct OBJCL *arg1) { NV_STATUS clTeardownPcie_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1); + #ifdef __nvoc_chipset_h_disabled static inline NV_STATUS clTeardownPcie(struct OBJGPU *arg0, struct OBJCL *arg1) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -537,6 +547,7 @@ static inline NV_STATUS clTeardownPcie(struct OBJGPU *arg0, struct OBJCL *arg1) NV_STATUS clPcieReadPortConfigReg_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1, PORTDATA *arg2, NvU32 arg3, NvU32 *arg4); + #ifdef __nvoc_chipset_h_disabled static inline NV_STATUS clPcieReadPortConfigReg(struct OBJGPU *arg0, struct OBJCL *arg1, PORTDATA *arg2, NvU32 arg3, NvU32 *arg4) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -550,6 +561,7 @@ static inline NV_STATUS clPcieReadPortConfigReg(struct OBJGPU *arg0, struct OBJC NV_STATUS clPcieWriteRootPortConfigReg_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1, NvU32 arg2, NvU32 arg3); + #ifdef __nvoc_chipset_h_disabled static inline NV_STATUS clPcieWriteRootPortConfigReg(struct OBJGPU *arg0, struct OBJCL *arg1, NvU32 arg2, NvU32 arg3) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -563,6 +575,7 @@ static inline NV_STATUS clPcieWriteRootPortConfigReg(struct OBJGPU *arg0, struct NV_STATUS clPcieReadAerCapability_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1, struct PcieAerCapability *arg2); + #ifdef __nvoc_chipset_h_disabled static inline NV_STATUS clPcieReadAerCapability(struct OBJGPU *arg0, struct OBJCL *arg1, struct PcieAerCapability *arg2) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -576,6 +589,7 @@ static inline NV_STATUS clPcieReadAerCapability(struct OBJGPU *arg0, struct OBJC NV_STATUS clPcieReadL1SsCapability_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1, struct PexL1SubstateCapability *arg2); + #ifdef __nvoc_chipset_h_disabled static inline NV_STATUS clPcieReadL1SsCapability(struct OBJGPU *arg0, struct OBJCL *arg1, struct PexL1SubstateCapability *arg2) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -589,6 +603,7 @@ static inline NV_STATUS clPcieReadL1SsCapability(struct OBJGPU *arg0, struct OBJ NV_STATUS clPcieReadDevCtrlStatus_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1, NvU32 *arg2, NvU32 *arg3); + #ifdef __nvoc_chipset_h_disabled static inline NV_STATUS clPcieReadDevCtrlStatus(struct OBJGPU *arg0, struct OBJCL *arg1, NvU32 *arg2, NvU32 *arg3) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -602,6 +617,7 @@ static inline NV_STATUS clPcieReadDevCtrlStatus(struct OBJGPU *arg0, struct OBJC NV_STATUS clPcieClearDevCtrlStatus_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1, NvU32 *arg2); + #ifdef __nvoc_chipset_h_disabled static inline NV_STATUS clPcieClearDevCtrlStatus(struct OBJGPU *arg0, struct OBJCL *arg1, NvU32 *arg2) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -615,6 +631,7 @@ static inline NV_STATUS clPcieClearDevCtrlStatus(struct OBJGPU *arg0, struct OBJ NvU16 clPcieReadWord_IMPL(struct OBJCL *arg0, NvU32 arg1, NvU8 arg2, NvU8 arg3, NvU8 arg4, NvU32 arg5); + #ifdef __nvoc_chipset_h_disabled static inline NvU16 clPcieReadWord(struct OBJCL *arg0, NvU32 arg1, NvU8 arg2, NvU8 arg3, NvU8 arg4, NvU32 arg5) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -628,6 +645,7 @@ static inline NvU16 clPcieReadWord(struct OBJCL *arg0, NvU32 arg1, NvU8 arg2, Nv NvU32 clPcieReadDword_IMPL(struct OBJCL *arg0, NvU32 arg1, NvU8 arg2, NvU8 arg3, NvU8 arg4, NvU32 arg5); + #ifdef __nvoc_chipset_h_disabled static inline NvU32 clPcieReadDword(struct OBJCL *arg0, NvU32 arg1, NvU8 arg2, NvU8 arg3, NvU8 arg4, NvU32 arg5) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -641,6 +659,7 @@ static inline NvU32 clPcieReadDword(struct OBJCL *arg0, NvU32 arg1, NvU8 arg2, N void clPcieWriteWord_IMPL(struct OBJCL *arg0, NvU32 arg1, NvU8 arg2, NvU8 arg3, NvU8 arg4, NvU32 arg5, NvU16 arg6); + #ifdef __nvoc_chipset_h_disabled static inline void clPcieWriteWord(struct OBJCL *arg0, NvU32 arg1, NvU8 arg2, NvU8 arg3, NvU8 arg4, NvU32 arg5, NvU16 arg6) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -653,6 +672,7 @@ static inline void clPcieWriteWord(struct OBJCL *arg0, NvU32 arg1, NvU8 arg2, Nv void clPcieWriteDword_IMPL(struct OBJCL *arg0, NvU32 arg1, NvU8 arg2, NvU8 arg3, NvU8 arg4, NvU32 arg5, NvU32 arg6); + #ifdef __nvoc_chipset_h_disabled static inline void clPcieWriteDword(struct OBJCL *arg0, NvU32 arg1, NvU8 arg2, NvU8 arg3, NvU8 arg4, NvU32 arg5, NvU32 arg6) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -665,6 +685,7 @@ static inline void clPcieWriteDword(struct OBJCL *arg0, NvU32 arg1, NvU8 arg2, N NvBool clFindBR04_IMPL(POBJGPU *pGpus, NvU32 NumGpus, NvBool flat, NvU32 devId, struct OBJCL *pCl); + #ifdef __nvoc_chipset_h_disabled static inline NvBool clFindBR04(POBJGPU *pGpus, NvU32 NumGpus, NvBool flat, NvU32 devId, struct OBJCL *pCl) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -678,6 +699,7 @@ static inline NvBool clFindBR04(POBJGPU *pGpus, NvU32 NumGpus, NvBool flat, NvU3 NV_STATUS clResumeBridge_IMPL(struct OBJCL *pCl); + #ifdef __nvoc_chipset_h_disabled static inline NV_STATUS clResumeBridge(struct OBJCL *pCl) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -691,6 +713,7 @@ static inline NV_STATUS clResumeBridge(struct OBJCL *pCl) { NV_STATUS clChangeUpstreamBusSpeed_IMPL(NvU8 primaryBus, struct OBJCL *pCl, NvU32 cmd); + #ifdef __nvoc_chipset_h_disabled static inline NV_STATUS clChangeUpstreamBusSpeed(NvU8 primaryBus, struct OBJCL *pCl, NvU32 cmd) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -704,6 +727,7 @@ static inline NV_STATUS clChangeUpstreamBusSpeed(NvU8 primaryBus, struct OBJCL * NV_STATUS clGetUpstreamBusSpeed_IMPL(NvU8 primaryBus, struct OBJCL *pCl, NvU32 *speed); + #ifdef __nvoc_chipset_h_disabled static inline NV_STATUS clGetUpstreamBusSpeed(NvU8 primaryBus, struct OBJCL *pCl, NvU32 *speed) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -717,6 +741,7 @@ static inline NV_STATUS clGetUpstreamBusSpeed(NvU8 primaryBus, struct OBJCL *pCl NV_STATUS clHWBCGetUpstreamBAR0_IMPL(NvU8 primaryBus, struct OBJCL *pCl, RmPhysAddr *pBAR0); + #ifdef __nvoc_chipset_h_disabled static inline NV_STATUS clHWBCGetUpstreamBAR0(NvU8 primaryBus, struct OBJCL *pCl, RmPhysAddr *pBAR0) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -730,6 +755,7 @@ static inline NV_STATUS clHWBCGetUpstreamBAR0(NvU8 primaryBus, struct OBJCL *pCl void *clFindP2PBrdg_IMPL(struct OBJCL *arg0, NvU32 arg1, NvU8 arg2, NvU8 *arg3, NvU8 *arg4, NvU8 *arg5, NvU16 *arg6, NvU16 *arg7); + #ifdef __nvoc_chipset_h_disabled static inline void *clFindP2PBrdg(struct OBJCL *arg0, NvU32 arg1, NvU8 arg2, NvU8 *arg3, NvU8 *arg4, NvU8 *arg5, NvU16 *arg6, NvU16 *arg7) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -743,6 +769,7 @@ static inline void *clFindP2PBrdg(struct OBJCL *arg0, NvU32 arg1, NvU8 arg2, NvU void *clFindBrdgUpstreamPort_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1, NvBool arg2, NvU8 *arg3, NvU8 *arg4, NvU8 *arg5, NvU16 *arg6, NvU16 *arg7, NvU8 *arg8); + #ifdef __nvoc_chipset_h_disabled static inline void *clFindBrdgUpstreamPort(struct OBJGPU *arg0, struct OBJCL *arg1, NvBool arg2, NvU8 *arg3, NvU8 *arg4, NvU8 *arg5, NvU16 *arg6, NvU16 *arg7, NvU8 *arg8) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -756,6 +783,7 @@ static inline void *clFindBrdgUpstreamPort(struct OBJGPU *arg0, struct OBJCL *ar NV_STATUS clSetPortPcieCapOffset_IMPL(struct OBJCL *arg0, void *arg1, NvU32 *arg2); + #ifdef __nvoc_chipset_h_disabled static inline NV_STATUS clSetPortPcieCapOffset(struct OBJCL *arg0, void *arg1, NvU32 *arg2) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -769,6 +797,7 @@ static inline NV_STATUS clSetPortPcieCapOffset(struct OBJCL *arg0, void *arg1, N NV_STATUS clGetRsdtXsdtTablesAddr_IMPL(struct OBJCL *arg0, NvU32 *arg1, NvU64 *arg2); + #ifdef __nvoc_chipset_h_disabled static inline NV_STATUS clGetRsdtXsdtTablesAddr(struct OBJCL *arg0, NvU32 *arg1, NvU64 *arg2) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -782,6 +811,7 @@ static inline NV_STATUS clGetRsdtXsdtTablesAddr(struct OBJCL *arg0, NvU32 *arg1, NvBool clGetMcfgTableFromOS_IMPL(struct OBJCL *arg0, struct OBJOS *arg1, void **arg2, NvU32 *arg3); + #ifdef __nvoc_chipset_h_disabled static inline NvBool clGetMcfgTableFromOS(struct OBJCL *arg0, struct OBJOS *arg1, void **arg2, NvU32 *arg3) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -795,6 +825,7 @@ static inline NvBool clGetMcfgTableFromOS(struct OBJCL *arg0, struct OBJOS *arg1 NvU64 clScanForTable_IMPL(struct OBJCL *arg0, struct OBJOS *arg1, NvU64 arg2, NvU64 arg3, NvU32 arg4); + #ifdef __nvoc_chipset_h_disabled static inline NvU64 clScanForTable(struct OBJCL *arg0, struct OBJOS *arg1, NvU64 arg2, NvU64 arg3, NvU32 arg4) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -808,6 +839,7 @@ static inline NvU64 clScanForTable(struct OBJCL *arg0, struct OBJOS *arg1, NvU64 NV_STATUS clStorePcieConfigSpaceBaseFromMcfg_IMPL(struct OBJCL *pCl); + #ifdef __nvoc_chipset_h_disabled static inline NV_STATUS clStorePcieConfigSpaceBaseFromMcfg(struct OBJCL *pCl) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -821,6 +853,7 @@ static inline NV_STATUS clStorePcieConfigSpaceBaseFromMcfg(struct OBJCL *pCl) { NV_STATUS clInsertPcieConfigSpaceBase_IMPL(struct OBJCL *arg0, RmPhysAddr arg1, NvU32 arg2, NvU8 arg3, NvU8 arg4); + #ifdef __nvoc_chipset_h_disabled static inline NV_STATUS clInsertPcieConfigSpaceBase(struct OBJCL *arg0, RmPhysAddr arg1, NvU32 arg2, NvU8 arg3, NvU8 arg4) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -834,6 +867,7 @@ static inline NV_STATUS clInsertPcieConfigSpaceBase(struct OBJCL *arg0, RmPhysAd RmPhysAddr clFindPcieConfigSpaceBase_IMPL(struct OBJCL *arg0, NvU32 arg1, NvU8 arg2); + #ifdef __nvoc_chipset_h_disabled static inline RmPhysAddr clFindPcieConfigSpaceBase(struct OBJCL *arg0, NvU32 arg1, NvU8 arg2) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -849,6 +883,7 @@ static inline RmPhysAddr clFindPcieConfigSpaceBase(struct OBJCL *arg0, NvU32 arg void clFreePcieConfigSpaceBase_IMPL(struct OBJCL *pCl); + #ifdef __nvoc_chipset_h_disabled static inline void clFreePcieConfigSpaceBase(struct OBJCL *pCl) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -861,6 +896,7 @@ static inline void clFreePcieConfigSpaceBase(struct OBJCL *pCl) { NV_STATUS clInitDeviceInfo_IMPL(struct OBJCL *arg0, struct OBJGPU *arg1); + #ifdef __nvoc_chipset_h_disabled static inline NV_STATUS clInitDeviceInfo(struct OBJCL *arg0, struct OBJGPU *arg1) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -874,6 +910,7 @@ static inline NV_STATUS clInitDeviceInfo(struct OBJCL *arg0, struct OBJGPU *arg1 void clCountBR_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1, NvU8 *arg2, NvU8 *arg3, NvU8 *arg4); + #ifdef __nvoc_chipset_h_disabled static inline void clCountBR(struct OBJGPU *arg0, struct OBJCL *arg1, NvU8 *arg2, NvU8 *arg3, NvU8 *arg4) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -886,6 +923,7 @@ static inline void clCountBR(struct OBJGPU *arg0, struct OBJCL *arg1, NvU8 *arg2 void clFindCommonBR_IMPL(struct OBJGPU *pGpu1, struct OBJGPU *pGpu2, struct OBJCL *pCl, NvU8 *pBR03Bus, NvU8 *pBR04Bus, NvU8 *pPLXBus, NvBool bScanAll); + #ifdef __nvoc_chipset_h_disabled static inline void clFindCommonBR(struct OBJGPU *pGpu1, struct OBJGPU *pGpu2, struct OBJCL *pCl, NvU8 *pBR03Bus, NvU8 *pBR04Bus, NvU8 *pPLXBus, NvBool bScanAll) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -898,6 +936,7 @@ static inline void clFindCommonBR(struct OBJGPU *pGpu1, struct OBJGPU *pGpu2, st void clFindCommonDownstreamBR_IMPL(struct OBJGPU *pGpu1, struct OBJGPU *pGpu2, struct OBJCL *pCl, NvU8 *pPciSwitchBus); + #ifdef __nvoc_chipset_h_disabled static inline void clFindCommonDownstreamBR(struct OBJGPU *pGpu1, struct OBJGPU *pGpu2, struct OBJCL *pCl, NvU8 *pPciSwitchBus) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -910,6 +949,7 @@ static inline void clFindCommonDownstreamBR(struct OBJGPU *pGpu1, struct OBJGPU void clFindBR_IMPL(struct OBJGPU *pGpu, struct OBJCL *pCl, NvU8 *pBR03Bus, NvU8 *pBR04Bus, NvBool *pBRNotBR04A03, NvBool *pNoUnsupportedBRFound, NvBool *pNoOnboardBR04, NvU8 *pPLXBus); + #ifdef __nvoc_chipset_h_disabled static inline void clFindBR(struct OBJGPU *pGpu, struct OBJCL *pCl, NvU8 *pBR03Bus, NvU8 *pBR04Bus, NvBool *pBRNotBR04A03, NvBool *pNoUnsupportedBRFound, NvBool *pNoOnboardBR04, NvU8 *pPLXBus) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -922,6 +962,7 @@ static inline void clFindBR(struct OBJGPU *pGpu, struct OBJCL *pCl, NvU8 *pBR03B void clSearchBR04_IMPL(struct OBJCL *pCl, NvU8 *pBR04BusArray, NvU8 *pBR04RevArray, NvU8 *pBR04Count); + #ifdef __nvoc_chipset_h_disabled static inline void clSearchBR04(struct OBJCL *pCl, NvU8 *pBR04BusArray, NvU8 *pBR04RevArray, NvU8 *pBR04Count) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -934,6 +975,7 @@ static inline void clSearchBR04(struct OBJCL *pCl, NvU8 *pBR04BusArray, NvU8 *pB NV_STATUS clPcieGetMaxCapableLinkWidth_IMPL(struct OBJCL *pCl, struct OBJGPU *pGpu, NvU32 *maxCapableLinkWidth); + #ifdef __nvoc_chipset_h_disabled static inline NV_STATUS clPcieGetMaxCapableLinkWidth(struct OBJCL *pCl, struct OBJGPU *pGpu, NvU32 *maxCapableLinkWidth) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -947,6 +989,7 @@ static inline NV_STATUS clPcieGetMaxCapableLinkWidth(struct OBJCL *pCl, struct O NV_STATUS clPcieIsRelaxedOrderingSafe_IMPL(struct OBJCL *pCl, struct OBJGPU *pGpu, NvBool *result); + #ifdef __nvoc_chipset_h_disabled static inline NV_STATUS clPcieIsRelaxedOrderingSafe(struct OBJCL *pCl, struct OBJGPU *pGpu, NvBool *result) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -960,6 +1003,7 @@ static inline NV_STATUS clPcieIsRelaxedOrderingSafe(struct OBJCL *pCl, struct OB NV_STATUS clStoreBusTopologyCache_IMPL(struct OBJCL *pCl, NvU32 secDomain, NvU16 secBus); + #ifdef __nvoc_chipset_h_disabled static inline NV_STATUS clStoreBusTopologyCache(struct OBJCL *pCl, NvU32 secDomain, NvU16 secBus) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -973,6 +1017,7 @@ static inline NV_STATUS clStoreBusTopologyCache(struct OBJCL *pCl, NvU32 secDoma void clFreeBusTopologyCache_IMPL(struct OBJCL *pCl); + #ifdef __nvoc_chipset_h_disabled static inline void clFreeBusTopologyCache(struct OBJCL *pCl) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -985,6 +1030,7 @@ static inline void clFreeBusTopologyCache(struct OBJCL *pCl) { NvBool clAreGpusBehindSameBridge_IMPL(struct OBJCL *pCl, struct OBJGPU *pGpu1, struct OBJGPU *pGpu2); + #ifdef __nvoc_chipset_h_disabled static inline NvBool clAreGpusBehindSameBridge(struct OBJCL *pCl, struct OBJGPU *pGpu1, struct OBJGPU *pGpu2) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -998,6 +1044,7 @@ static inline NvBool clAreGpusBehindSameBridge(struct OBJCL *pCl, struct OBJGPU NvBool clIsL1MaskEnabledForUpstreamPort_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1); + #ifdef __nvoc_chipset_h_disabled static inline NvBool clIsL1MaskEnabledForUpstreamPort(struct OBJGPU *arg0, struct OBJCL *arg1) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -1011,6 +1058,7 @@ static inline NvBool clIsL1MaskEnabledForUpstreamPort(struct OBJGPU *arg0, struc NV_STATUS clControlL0sL1LinkControlUpstreamPort_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1, NvBool arg2); + #ifdef __nvoc_chipset_h_disabled static inline NV_STATUS clControlL0sL1LinkControlUpstreamPort(struct OBJGPU *arg0, struct OBJCL *arg1, NvBool arg2) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -1024,6 +1072,7 @@ static inline NV_STATUS clControlL0sL1LinkControlUpstreamPort(struct OBJGPU *arg NV_STATUS clChipsetAspmPublicControl_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1, NvU32 arg2); + #ifdef __nvoc_chipset_h_disabled static inline NV_STATUS clChipsetAspmPublicControl(struct OBJGPU *arg0, struct OBJCL *arg1, NvU32 arg2) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -1037,6 +1086,7 @@ static inline NV_STATUS clChipsetAspmPublicControl(struct OBJGPU *arg0, struct O NvBool clRootportNeedsNosnoopWAR_FWCLIENT(struct OBJGPU *arg0, struct OBJCL *arg1); + #ifdef __nvoc_chipset_h_disabled static inline NvBool clRootportNeedsNosnoopWAR(struct OBJGPU *arg0, struct OBJCL *arg1) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -1048,11 +1098,28 @@ static inline NvBool clRootportNeedsNosnoopWAR(struct OBJGPU *arg0, struct OBJCL #define clRootportNeedsNosnoopWAR_HAL(arg0, arg1) clRootportNeedsNosnoopWAR(arg0, arg1) +NvU16 clPcieGetGpuLostDiagnosticData_IMPL(struct OBJGPU *pGpu, struct OBJCL *arg0, NvU8 *pBuffer, NvU32 size); + + +#ifdef __nvoc_chipset_h_disabled +static inline NvU16 clPcieGetGpuLostDiagnosticData(struct OBJGPU *pGpu, struct OBJCL *arg0, NvU8 *pBuffer, NvU32 size) { + NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); + return 0; +} +#else //__nvoc_chipset_h_disabled +#define clPcieGetGpuLostDiagnosticData(pGpu, arg0, pBuffer, size) clPcieGetGpuLostDiagnosticData_IMPL(pGpu, arg0, pBuffer, size) +#endif //__nvoc_chipset_h_disabled + +#define clPcieGetGpuLostDiagnosticData_HAL(pGpu, arg0, pBuffer, size) clPcieGetGpuLostDiagnosticData(pGpu, arg0, pBuffer, size) + NV_STATUS clConstruct_IMPL(struct OBJCL *arg_pCl); + #define __nvoc_clConstruct(arg_pCl) clConstruct_IMPL(arg_pCl) void clDestruct_IMPL(struct OBJCL *pCl); + #define __nvoc_clDestruct(pCl) clDestruct_IMPL(pCl) NvBool clUpstreamVgaDecodeEnabled_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1); + #ifdef __nvoc_chipset_h_disabled static inline NvBool clUpstreamVgaDecodeEnabled(struct OBJGPU *arg0, struct OBJCL *arg1) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -1063,6 +1130,7 @@ static inline NvBool clUpstreamVgaDecodeEnabled(struct OBJGPU *arg0, struct OBJC #endif //__nvoc_chipset_h_disabled NV_STATUS clPcieGetRootGenSpeed_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1, NvU8 *arg2); + #ifdef __nvoc_chipset_h_disabled static inline NV_STATUS clPcieGetRootGenSpeed(struct OBJGPU *arg0, struct OBJCL *arg1, NvU8 *arg2) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -1073,6 +1141,7 @@ static inline NV_STATUS clPcieGetRootGenSpeed(struct OBJGPU *arg0, struct OBJCL #endif //__nvoc_chipset_h_disabled NV_STATUS clPcieGetDownstreamPortLinkCap2_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1, NvU32 *arg2); + #ifdef __nvoc_chipset_h_disabled static inline NV_STATUS clPcieGetDownstreamPortLinkCap2(struct OBJGPU *arg0, struct OBJCL *arg1, NvU32 *arg2) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -1083,6 +1152,7 @@ static inline NV_STATUS clPcieGetDownstreamPortLinkCap2(struct OBJGPU *arg0, str #endif //__nvoc_chipset_h_disabled NV_STATUS clCheckUpstreamLtrSupport_IMPL(struct OBJGPU *arg0, struct OBJCL *arg1, NvBool *arg2); + #ifdef __nvoc_chipset_h_disabled static inline NV_STATUS clCheckUpstreamLtrSupport(struct OBJGPU *arg0, struct OBJCL *arg1, NvBool *arg2) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -1093,6 +1163,7 @@ static inline NV_STATUS clCheckUpstreamLtrSupport(struct OBJGPU *arg0, struct OB #endif //__nvoc_chipset_h_disabled NV_STATUS clGetAtomicTypesSupported_IMPL(NvU32 arg0, NvU8 arg1, struct OBJCL *arg2, NvU32 *arg3); + #ifdef __nvoc_chipset_h_disabled static inline NV_STATUS clGetAtomicTypesSupported(NvU32 arg0, NvU8 arg1, struct OBJCL *arg2, NvU32 *arg3) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); @@ -1103,6 +1174,7 @@ static inline NV_STATUS clGetAtomicTypesSupported(NvU32 arg0, NvU8 arg1, struct #endif //__nvoc_chipset_h_disabled void clSyncWithGsp_IMPL(struct OBJCL *arg0, GspSystemInfo *arg1); + #ifdef __nvoc_chipset_h_disabled static inline void clSyncWithGsp(struct OBJCL *arg0, GspSystemInfo *arg1) { NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); diff --git a/src/nvidia/generated/g_client_nvoc.c b/src/nvidia/generated/g_client_nvoc.c index 99ed93996..7cd9f8a67 100644 --- a/src/nvidia/generated/g_client_nvoc.c +++ b/src/nvidia/generated/g_client_nvoc.c @@ -241,6 +241,14 @@ static NV_STATUS __nvoc_thunk_RmClient_clientPostProcessPendingFreeList(struct R return rmclientPostProcessPendingFreeList((struct RmClient *)(((unsigned char *)pClient) - __nvoc_rtti_RmClient_RsClient.offset), ppFirstLowPriRef); } +static RS_PRIV_LEVEL __nvoc_thunk_RmClient_clientGetCachedPrivilege(struct RsClient *pClient) { + return rmclientGetCachedPrivilege((struct RmClient *)(((unsigned char *)pClient) - __nvoc_rtti_RmClient_RsClient.offset)); +} + +static NvBool __nvoc_thunk_RmClient_clientIsAdmin(struct RsClient *pClient, RS_PRIV_LEVEL privLevel) { + return rmclientIsAdmin((struct RmClient *)(((unsigned char *)pClient) - __nvoc_rtti_RmClient_RsClient.offset), privLevel); +} + static NV_STATUS __nvoc_thunk_RsClient_rmclientDestructResourceRef(struct RmClient *pClient, RsServer *pServer, struct RsResourceRef *pResourceRef) { return clientDestructResourceRef((struct RsClient *)(((unsigned char *)pClient) + __nvoc_rtti_RmClient_RsClient.offset), pServer, pResourceRef); } @@ -306,6 +314,10 @@ static void __nvoc_init_funcTable_RmClient_1(RmClient *pThis) { pThis->__rmclientPostProcessPendingFreeList__ = &rmclientPostProcessPendingFreeList_IMPL; + pThis->__rmclientGetCachedPrivilege__ = &rmclientGetCachedPrivilege_IMPL; + + pThis->__rmclientIsAdmin__ = &rmclientIsAdmin_IMPL; + pThis->__nvoc_base_RsClient.__clientValidate__ = &__nvoc_thunk_RmClient_clientValidate; pThis->__nvoc_base_RsClient.__clientFreeResource__ = &__nvoc_thunk_RmClient_clientFreeResource; @@ -316,6 +328,10 @@ static void __nvoc_init_funcTable_RmClient_1(RmClient *pThis) { pThis->__nvoc_base_RsClient.__clientPostProcessPendingFreeList__ = &__nvoc_thunk_RmClient_clientPostProcessPendingFreeList; + pThis->__nvoc_base_RsClient.__clientGetCachedPrivilege__ = &__nvoc_thunk_RmClient_clientGetCachedPrivilege; + + pThis->__nvoc_base_RsClient.__clientIsAdmin__ = &__nvoc_thunk_RmClient_clientIsAdmin; + pThis->__rmclientDestructResourceRef__ = &__nvoc_thunk_RsClient_rmclientDestructResourceRef; pThis->__rmclientValidateNewResourceHandle__ = &__nvoc_thunk_RsClient_rmclientValidateNewResourceHandle; diff --git a/src/nvidia/generated/g_client_nvoc.h b/src/nvidia/generated/g_client_nvoc.h index 499e23af5..22ec24ad6 100644 --- a/src/nvidia/generated/g_client_nvoc.h +++ b/src/nvidia/generated/g_client_nvoc.h @@ -92,8 +92,10 @@ NV_STATUS __nvoc_objCreate_UserInfo(UserInfo**, Dynamic*, NvU32); __nvoc_objCreate_UserInfo((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) NV_STATUS userinfoConstruct_IMPL(struct UserInfo *arg_pUserInfo); + #define __nvoc_userinfoConstruct(arg_pUserInfo) userinfoConstruct_IMPL(arg_pUserInfo) void userinfoDestruct_IMPL(struct UserInfo *pUserInfo); + #define __nvoc_userinfoDestruct(pUserInfo) userinfoDestruct_IMPL(pUserInfo) #undef PRIVATE_FIELD @@ -123,6 +125,8 @@ struct RmClient { NV_STATUS (*__rmclientInterMap__)(struct RmClient *, struct RsResourceRef *, struct RsResourceRef *, struct RS_INTER_MAP_PARAMS *); void (*__rmclientInterUnmap__)(struct RmClient *, struct RsResourceRef *, struct RS_INTER_UNMAP_PARAMS *); NV_STATUS (*__rmclientPostProcessPendingFreeList__)(struct RmClient *, struct RsResourceRef **); + RS_PRIV_LEVEL (*__rmclientGetCachedPrivilege__)(struct RmClient *); + NvBool (*__rmclientIsAdmin__)(struct RmClient *, RS_PRIV_LEVEL); NV_STATUS (*__rmclientDestructResourceRef__)(struct RmClient *, RsServer *, struct RsResourceRef *); NV_STATUS (*__rmclientValidateNewResourceHandle__)(struct RmClient *, NvHandle, NvBool); NV_STATUS (*__rmclientShareResource__)(struct RmClient *, struct RsResourceRef *, RS_SHARE_POLICY *, struct CALL_CONTEXT *); @@ -177,6 +181,8 @@ NV_STATUS __nvoc_objCreate_RmClient(RmClient**, Dynamic*, NvU32, struct PORT_MEM #define rmclientInterMap(pClient, pMapperRef, pMappableRef, pParams) rmclientInterMap_DISPATCH(pClient, pMapperRef, pMappableRef, pParams) #define rmclientInterUnmap(pClient, pMapperRef, pParams) rmclientInterUnmap_DISPATCH(pClient, pMapperRef, pParams) #define rmclientPostProcessPendingFreeList(pClient, ppFirstLowPriRef) rmclientPostProcessPendingFreeList_DISPATCH(pClient, ppFirstLowPriRef) +#define rmclientGetCachedPrivilege(pClient) rmclientGetCachedPrivilege_DISPATCH(pClient) +#define rmclientIsAdmin(pClient, privLevel) rmclientIsAdmin_DISPATCH(pClient, privLevel) #define rmclientDestructResourceRef(pClient, pServer, pResourceRef) rmclientDestructResourceRef_DISPATCH(pClient, pServer, pResourceRef) #define rmclientValidateNewResourceHandle(pClient, hResource, bRestrict) rmclientValidateNewResourceHandle_DISPATCH(pClient, hResource, bRestrict) #define rmclientShareResource(pClient, pResourceRef, pSharePolicy, pCallContext) rmclientShareResource_DISPATCH(pClient, pResourceRef, pSharePolicy, pCallContext) @@ -211,6 +217,18 @@ static inline NV_STATUS rmclientPostProcessPendingFreeList_DISPATCH(struct RmCli return pClient->__rmclientPostProcessPendingFreeList__(pClient, ppFirstLowPriRef); } +RS_PRIV_LEVEL rmclientGetCachedPrivilege_IMPL(struct RmClient *pClient); + +static inline RS_PRIV_LEVEL rmclientGetCachedPrivilege_DISPATCH(struct RmClient *pClient) { + return pClient->__rmclientGetCachedPrivilege__(pClient); +} + +NvBool rmclientIsAdmin_IMPL(struct RmClient *pClient, RS_PRIV_LEVEL privLevel); + +static inline NvBool rmclientIsAdmin_DISPATCH(struct RmClient *pClient, RS_PRIV_LEVEL privLevel) { + return pClient->__rmclientIsAdmin__(pClient, privLevel); +} + static inline NV_STATUS rmclientDestructResourceRef_DISPATCH(struct RmClient *pClient, RsServer *pServer, struct RsResourceRef *pResourceRef) { return pClient->__rmclientDestructResourceRef__(pClient, pServer, pResourceRef); } @@ -228,32 +246,13 @@ static inline NV_STATUS rmclientUnmapMemory_DISPATCH(struct RmClient *pClient, s } NV_STATUS rmclientConstruct_IMPL(struct RmClient *arg_pClient, struct PORT_MEM_ALLOCATOR *arg_pAllocator, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_rmclientConstruct(arg_pClient, arg_pAllocator, arg_pParams) rmclientConstruct_IMPL(arg_pClient, arg_pAllocator, arg_pParams) void rmclientDestruct_IMPL(struct RmClient *pClient); + #define __nvoc_rmclientDestruct(pClient) rmclientDestruct_IMPL(pClient) -RS_PRIV_LEVEL rmclientGetCachedPrivilege_IMPL(struct RmClient *pClient); -#ifdef __nvoc_client_h_disabled -static inline RS_PRIV_LEVEL rmclientGetCachedPrivilege(struct RmClient *pClient) { - NV_ASSERT_FAILED_PRECOMP("RmClient was disabled!"); - RS_PRIV_LEVEL ret; - portMemSet(&ret, 0, sizeof(RS_PRIV_LEVEL)); - return ret; -} -#else //__nvoc_client_h_disabled -#define rmclientGetCachedPrivilege(pClient) rmclientGetCachedPrivilege_IMPL(pClient) -#endif //__nvoc_client_h_disabled - -NvBool rmclientIsAdmin_IMPL(struct RmClient *pClient, RS_PRIV_LEVEL privLevel); -#ifdef __nvoc_client_h_disabled -static inline NvBool rmclientIsAdmin(struct RmClient *pClient, RS_PRIV_LEVEL privLevel) { - NV_ASSERT_FAILED_PRECOMP("RmClient was disabled!"); - return NV_FALSE; -} -#else //__nvoc_client_h_disabled -#define rmclientIsAdmin(pClient, privLevel) rmclientIsAdmin_IMPL(pClient, privLevel) -#endif //__nvoc_client_h_disabled - void rmclientSetClientFlags_IMPL(struct RmClient *pClient, NvU32 clientFlags); + #ifdef __nvoc_client_h_disabled static inline void rmclientSetClientFlags(struct RmClient *pClient, NvU32 clientFlags) { NV_ASSERT_FAILED_PRECOMP("RmClient was disabled!"); @@ -263,6 +262,7 @@ static inline void rmclientSetClientFlags(struct RmClient *pClient, NvU32 client #endif //__nvoc_client_h_disabled void *rmclientGetSecurityToken_IMPL(struct RmClient *pClient); + #ifdef __nvoc_client_h_disabled static inline void *rmclientGetSecurityToken(struct RmClient *pClient) { NV_ASSERT_FAILED_PRECOMP("RmClient was disabled!"); @@ -273,6 +273,7 @@ static inline void *rmclientGetSecurityToken(struct RmClient *pClient) { #endif //__nvoc_client_h_disabled NvBool rmclientIsCapableOrAdmin_IMPL(struct RmClient *pClient, NvU32 capability, RS_PRIV_LEVEL privLevel); + #ifdef __nvoc_client_h_disabled static inline NvBool rmclientIsCapableOrAdmin(struct RmClient *pClient, NvU32 capability, RS_PRIV_LEVEL privLevel) { NV_ASSERT_FAILED_PRECOMP("RmClient was disabled!"); @@ -283,6 +284,7 @@ static inline NvBool rmclientIsCapableOrAdmin(struct RmClient *pClient, NvU32 ca #endif //__nvoc_client_h_disabled NvBool rmclientIsCapable_IMPL(struct RmClient *pClient, NvU32 capability); + #ifdef __nvoc_client_h_disabled static inline NvBool rmclientIsCapable(struct RmClient *pClient, NvU32 capability) { NV_ASSERT_FAILED_PRECOMP("RmClient was disabled!"); diff --git a/src/nvidia/generated/g_client_resource_nvoc.c b/src/nvidia/generated/g_client_resource_nvoc.c index 33a763b88..e848b1901 100644 --- a/src/nvidia/generated/g_client_resource_nvoc.c +++ b/src/nvidia/generated/g_client_resource_nvoc.c @@ -158,6 +158,10 @@ static NV_STATUS __nvoc_thunk_RsResource_cliresUnmapFrom(struct RmClientResource return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RmClientResource_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_cliresIsDuplicate(struct RmClientResource *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RmClientResource_RsResource.offset), hMemory, pDuplicate); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_cliresGetNotificationListPtr(struct RmClientResource *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_RmClientResource_Notifier.offset)); } @@ -369,6 +373,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient #endif }, { /* [12] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemExecuteAcpiMethod_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x130u, + /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdSystemExecuteAcpiMethod" +#endif + }, + { /* [13] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -383,7 +402,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetGpusPowerStatus" #endif }, - { /* [13] */ + { /* [14] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -398,7 +417,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetPrivilegedStatus" #endif }, - { /* [14] */ + { /* [15] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -413,7 +432,37 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetFabricStatus" #endif }, - { /* [15] */ + { /* [16] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdVgpuGetVgpuVersion_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x137u, + /*paramSize=*/ sizeof(NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdVgpuGetVgpuVersion" +#endif + }, + { /* [17] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdVgpuSetVgpuVersion_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x138u, + /*paramSize=*/ sizeof(NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdVgpuSetVgpuVersion" +#endif + }, + { /* [18] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -428,7 +477,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetRmInstanceId" #endif }, - { /* [16] */ + { /* [19] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -443,7 +492,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetP2pCapsMatrix" #endif }, - { /* [17] */ + { /* [20] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemNVPCFGetPowerModeInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x13bu, + /*paramSize=*/ sizeof(NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdSystemNVPCFGetPowerModeInfo" +#endif + }, + { /* [21] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -458,7 +522,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemSyncExternalFabricMgmt" #endif }, - { /* [18] */ + { /* [22] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -473,7 +537,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetClientDatabaseInfo" #endif }, - { /* [19] */ + { /* [23] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -488,7 +552,52 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetBuildVersionV2" #endif }, - { /* [20] */ + { /* [24] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x807u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemRmctrlCacheModeCtrl_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x807u) + /*flags=*/ 0x807u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x13fu, + /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdSystemRmctrlCacheModeCtrl" +#endif + }, + { /* [25] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemPfmreqhndlrGetPerfSensorCounters_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x146u, + /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdSystemPfmreqhndlrGetPerfSensorCounters" +#endif + }, + { /* [26] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemPfmreqhndlrGetExtendedPerfSensorCounters_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x147u, + /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdSystemPfmreqhndlrGetExtendedPerfSensorCounters" +#endif + }, + { /* [27] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -503,13 +612,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetFeatures" #endif }, - { /* [21] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + { /* [28] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuGetAttachedIds_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) - /*flags=*/ 0x811u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + /*flags=*/ 0x813u, /*accessRight=*/0x0u, /*methodId=*/ 0x201u, /*paramSize=*/ sizeof(NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS), @@ -518,7 +627,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetAttachedIds" #endif }, - { /* [22] */ + { /* [29] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -533,7 +642,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetIdInfo" #endif }, - { /* [23] */ + { /* [30] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -548,7 +657,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetInitStatus" #endif }, - { /* [24] */ + { /* [31] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -563,7 +672,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetDeviceIds" #endif }, - { /* [25] */ + { /* [32] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -578,7 +687,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetIdInfoV2" #endif }, - { /* [26] */ + { /* [33] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -593,7 +702,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetProbedIds" #endif }, - { /* [27] */ + { /* [34] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -608,7 +717,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuAttachIds" #endif }, - { /* [28] */ + { /* [35] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -623,7 +732,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuDetachIds" #endif }, - { /* [29] */ + { /* [36] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -638,7 +747,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetPciInfo" #endif }, - { /* [30] */ + { /* [37] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -653,7 +762,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetSvmSize" #endif }, - { /* [31] */ + { /* [38] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -668,7 +777,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetUuidInfo" #endif }, - { /* [32] */ + { /* [39] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -683,7 +792,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetUuidFromGpuId" #endif }, - { /* [33] */ + { /* [40] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -698,7 +807,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuModifyGpuDrainState" #endif }, - { /* [34] */ + { /* [41] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -713,7 +822,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuQueryGpuDrainState" #endif }, - { /* [35] */ + { /* [42] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -728,7 +837,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetMemOpEnable" #endif }, - { /* [36] */ + { /* [43] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -743,7 +852,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuDisableNvlinkInit" #endif }, - { /* [37] */ + { /* [44] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -758,7 +867,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdLegacyConfig" #endif }, - { /* [38] */ + { /* [45] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -773,7 +882,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdIdleChannels" #endif }, - { /* [39] */ + { /* [46] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdPushGspUcode_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x285u, + /*paramSize=*/ sizeof(NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdPushGspUcode" +#endif + }, + { /* [47] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -788,7 +912,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGsyncGetAttachedIds" #endif }, - { /* [40] */ + { /* [48] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -803,7 +927,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGsyncGetIdInfo" #endif }, - { /* [41] */ + { /* [49] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -818,7 +942,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdEventSetNotification" #endif }, - { /* [42] */ + { /* [50] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -833,7 +957,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdEventGetSystemEventStatus" #endif }, - { /* [43] */ + { /* [51] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -848,7 +972,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetDumpSize" #endif }, - { /* [44] */ + { /* [52] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -863,7 +987,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetDump" #endif }, - { /* [45] */ + { /* [53] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -878,7 +1002,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetTimestamp" #endif }, - { /* [46] */ + { /* [54] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -893,7 +1017,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetNvlogInfo" #endif }, - { /* [47] */ + { /* [55] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -908,7 +1032,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetNvlogBufferInfo" #endif }, - { /* [48] */ + { /* [56] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -923,7 +1047,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetNvlog" #endif }, - { /* [49] */ + { /* [57] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -938,7 +1062,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetRcerrRpt" #endif }, - { /* [50] */ + { /* [58] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -953,7 +1077,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSetSubProcessID" #endif }, - { /* [51] */ + { /* [59] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -968,7 +1092,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdDisableSubProcessUserdIsolation" #endif }, - { /* [52] */ + { /* [60] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -983,7 +1107,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSyncGpuBoostInfo" #endif }, - { /* [53] */ + { /* [61] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x5u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -998,7 +1122,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSyncGpuBoostGroupCreate" #endif }, - { /* [54] */ + { /* [62] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x5u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1013,7 +1137,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSyncGpuBoostGroupDestroy" #endif }, - { /* [55] */ + { /* [63] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1028,13 +1152,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSyncGpuBoostGroupInfo" #endif }, - { /* [56] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + { /* [64] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuAcctSetAccountingState_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) - /*flags=*/ 0x4u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) + /*flags=*/ 0x140004u, /*accessRight=*/0x0u, /*methodId=*/ 0xb01u, /*paramSize=*/ sizeof(NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS), @@ -1043,7 +1167,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuAcctSetAccountingState" #endif }, - { /* [57] */ + { /* [65] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1058,7 +1182,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuAcctGetAccountingState" #endif }, - { /* [58] */ + { /* [66] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1073,7 +1197,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuAcctGetProcAccountingInfo" #endif }, - { /* [59] */ + { /* [67] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1088,13 +1212,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuAcctGetAccountingPids" #endif }, - { /* [60] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + { /* [68] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuAcctClearAccountingData_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) - /*flags=*/ 0x4u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) + /*flags=*/ 0x140004u, /*accessRight=*/0x0u, /*methodId=*/ 0xb05u, /*paramSize=*/ sizeof(NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS), @@ -1103,7 +1227,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuAcctClearAccountingData" #endif }, - { /* [61] */ + { /* [69] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdVgpuGetStartData_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xc01u, + /*paramSize=*/ sizeof(NV0000_CTRL_VGPU_GET_START_DATA_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdVgpuGetStartData" +#endif + }, + { /* [70] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1118,7 +1257,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdClientGetAddrSpaceType" #endif }, - { /* [62] */ + { /* [71] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1133,7 +1272,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdClientGetHandleInfo" #endif }, - { /* [63] */ + { /* [72] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1148,7 +1287,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdClientGetAccessRights" #endif }, - { /* [64] */ + { /* [73] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1163,7 +1302,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdClientSetInheritedSharePolicy" #endif }, - { /* [65] */ + { /* [74] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1178,7 +1317,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdClientGetChildHandle" #endif }, - { /* [66] */ + { /* [75] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1193,7 +1332,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdClientShareObject" #endif }, - { /* [67] */ + { /* [76] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdObjectsAreDuplicates_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xd07u, + /*paramSize=*/ sizeof(NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdObjectsAreDuplicates" +#endif + }, + { /* [77] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1208,7 +1362,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdOsUnixFlushUserCache" #endif }, - { /* [68] */ + { /* [78] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1223,7 +1377,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdOsUnixExportObjectToFd" #endif }, - { /* [69] */ + { /* [79] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1238,7 +1392,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdOsUnixImportObjectFromFd" #endif }, - { /* [70] */ + { /* [80] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1253,7 +1407,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdOsUnixGetExportObjectInfo" #endif }, - { /* [71] */ + { /* [81] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1268,7 +1422,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdOsUnixCreateExportObjectFd" #endif }, - { /* [72] */ + { /* [82] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1283,7 +1437,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdOsUnixExportObjectsToFd" #endif }, - { /* [73] */ + { /* [83] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1303,7 +1457,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient const struct NVOC_EXPORT_INFO __nvoc_export_info_RmClientResource = { - /*numEntries=*/ 74, + /*numEntries=*/ 84, /*pExportEntries=*/ __nvoc_exported_method_def_RmClientResource }; @@ -1370,6 +1524,10 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdSystemGetBuildVersionV2__ = &cliresCtrlCmdSystemGetBuildVersionV2_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdSystemExecuteAcpiMethod__ = &cliresCtrlCmdSystemExecuteAcpiMethod_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4013u) pThis->__cliresCtrlCmdSystemGetChipsetInfo__ = &cliresCtrlCmdSystemGetChipsetInfo_IMPL; #endif @@ -1438,6 +1596,10 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdSystemGetClientDatabaseInfo__ = &cliresCtrlCmdSystemGetClientDatabaseInfo_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x807u) + pThis->__cliresCtrlCmdSystemRmctrlCacheModeCtrl__ = &cliresCtrlCmdSystemRmctrlCacheModeCtrl_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__cliresCtrlCmdNvdGetDumpSize__ = &cliresCtrlCmdNvdGetDumpSize_IMPL; #endif @@ -1491,6 +1653,10 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + pThis->__cliresCtrlCmdObjectsAreDuplicates__ = &cliresCtrlCmdObjectsAreDuplicates_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) pThis->__cliresCtrlCmdGpuGetAttachedIds__ = &cliresCtrlCmdGpuGetAttachedIds_IMPL; #endif @@ -1562,6 +1728,10 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdIdleChannels__ = &cliresCtrlCmdIdleChannels_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdPushGspUcode__ = &cliresCtrlCmdPushGspUcode_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__cliresCtrlCmdGsyncGetAttachedIds__ = &cliresCtrlCmdGsyncGetAttachedIds_IMPL; #endif @@ -1606,7 +1776,7 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdOsUnixFlushUserCache__ = &cliresCtrlCmdOsUnixFlushUserCache_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) pThis->__cliresCtrlCmdGpuAcctSetAccountingState__ = &cliresCtrlCmdGpuAcctSetAccountingState_IMPL; #endif @@ -1622,7 +1792,7 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdGpuAcctGetAccountingPids__ = &cliresCtrlCmdGpuAcctGetAccountingPids_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) pThis->__cliresCtrlCmdGpuAcctClearAccountingData__ = &cliresCtrlCmdGpuAcctClearAccountingData_IMPL; #endif @@ -1650,10 +1820,34 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdSyncGpuBoostGroupInfo__ = &cliresCtrlCmdSyncGpuBoostGroupInfo_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdVgpuGetStartData__ = &cliresCtrlCmdVgpuGetStartData_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdVgpuGetVgpuVersion__ = &cliresCtrlCmdVgpuGetVgpuVersion_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdVgpuSetVgpuVersion__ = &cliresCtrlCmdVgpuSetVgpuVersion_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdSystemNVPCFGetPowerModeInfo__ = &cliresCtrlCmdSystemNVPCFGetPowerModeInfo_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) pThis->__cliresCtrlCmdSystemSyncExternalFabricMgmt__ = &cliresCtrlCmdSystemSyncExternalFabricMgmt_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdSystemPfmreqhndlrGetPerfSensorCounters__ = &cliresCtrlCmdSystemPfmreqhndlrGetPerfSensorCounters_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdSystemPfmreqhndlrGetExtendedPerfSensorCounters__ = &cliresCtrlCmdSystemPfmreqhndlrGetExtendedPerfSensorCounters_IMPL; +#endif + pThis->__nvoc_base_RsClientResource.__nvoc_base_RsResource.__resAccessCallback__ = &__nvoc_thunk_RmClientResource_resAccessCallback; pThis->__nvoc_base_RsClientResource.__nvoc_base_RsResource.__resShareCallback__ = &__nvoc_thunk_RmClientResource_resShareCallback; @@ -1682,6 +1876,8 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresUnmapFrom__ = &__nvoc_thunk_RsResource_cliresUnmapFrom; + pThis->__cliresIsDuplicate__ = &__nvoc_thunk_RsResource_cliresIsDuplicate; + pThis->__cliresGetNotificationListPtr__ = &__nvoc_thunk_Notifier_cliresGetNotificationListPtr; pThis->__cliresControl_Epilogue__ = &__nvoc_thunk_RsResource_cliresControl_Epilogue; diff --git a/src/nvidia/generated/g_client_resource_nvoc.h b/src/nvidia/generated/g_client_resource_nvoc.h index b5e0a98a2..8ffd05074 100644 --- a/src/nvidia/generated/g_client_resource_nvoc.h +++ b/src/nvidia/generated/g_client_resource_nvoc.h @@ -48,7 +48,6 @@ extern "C" { #include "ctrl/ctrl0000/ctrl0000nvd.h" #include "ctrl/ctrl0000/ctrl0000proc.h" #include "ctrl/ctrl0000/ctrl0000syncgpuboost.h" -#include "ctrl/ctrl0000/ctrl0000gspc.h" #include "ctrl/ctrl0000/ctrl0000vgpu.h" #include "ctrl/ctrl0000/ctrl0000client.h" @@ -79,6 +78,7 @@ struct RmClientResource { NV_STATUS (*__cliresCtrlCmdSystemGetCpuInfo__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetFeatures__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetBuildVersionV2__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS *); + NV_STATUS (*__cliresCtrlCmdSystemExecuteAcpiMethod__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetChipsetInfo__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemSetMemorySize__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetClassList__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS *); @@ -96,6 +96,7 @@ struct RmClientResource { NV_STATUS (*__cliresCtrlCmdSystemGetFabricStatus__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetRmInstanceId__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetClientDatabaseInfo__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS *); + NV_STATUS (*__cliresCtrlCmdSystemRmctrlCacheModeCtrl__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS *); NV_STATUS (*__cliresCtrlCmdNvdGetDumpSize__)(struct RmClientResource *, NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS *); NV_STATUS (*__cliresCtrlCmdNvdGetDump__)(struct RmClientResource *, NV0000_CTRL_NVD_GET_DUMP_PARAMS *); NV_STATUS (*__cliresCtrlCmdNvdGetTimestamp__)(struct RmClientResource *, NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS *); @@ -109,6 +110,7 @@ struct RmClientResource { NV_STATUS (*__cliresCtrlCmdClientSetInheritedSharePolicy__)(struct RmClientResource *, NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS *); NV_STATUS (*__cliresCtrlCmdClientShareObject__)(struct RmClientResource *, NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS *); NV_STATUS (*__cliresCtrlCmdClientGetChildHandle__)(struct RmClientResource *, NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS *); + NV_STATUS (*__cliresCtrlCmdObjectsAreDuplicates__)(struct RmClientResource *, NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS *); NV_STATUS (*__cliresCtrlCmdGpuGetAttachedIds__)(struct RmClientResource *, NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS *); NV_STATUS (*__cliresCtrlCmdGpuGetIdInfo__)(struct RmClientResource *, NV0000_CTRL_GPU_GET_ID_INFO_PARAMS *); NV_STATUS (*__cliresCtrlCmdGpuGetIdInfoV2__)(struct RmClientResource *, NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS *); @@ -127,6 +129,7 @@ struct RmClientResource { NV_STATUS (*__cliresCtrlCmdGpuDisableNvlinkInit__)(struct RmClientResource *, NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS *); NV_STATUS (*__cliresCtrlCmdLegacyConfig__)(struct RmClientResource *, NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS *); NV_STATUS (*__cliresCtrlCmdIdleChannels__)(struct RmClientResource *, NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS *); + NV_STATUS (*__cliresCtrlCmdPushGspUcode__)(struct RmClientResource *, NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS *); NV_STATUS (*__cliresCtrlCmdGsyncGetAttachedIds__)(struct RmClientResource *, NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS *); NV_STATUS (*__cliresCtrlCmdGsyncGetIdInfo__)(struct RmClientResource *, NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS *); NV_STATUS (*__cliresCtrlCmdEventSetNotification__)(struct RmClientResource *, NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS *); @@ -149,7 +152,13 @@ struct RmClientResource { NV_STATUS (*__cliresCtrlCmdSyncGpuBoostGroupCreate__)(struct RmClientResource *, NV0000_SYNC_GPU_BOOST_GROUP_CREATE_PARAMS *); NV_STATUS (*__cliresCtrlCmdSyncGpuBoostGroupDestroy__)(struct RmClientResource *, NV0000_SYNC_GPU_BOOST_GROUP_DESTROY_PARAMS *); NV_STATUS (*__cliresCtrlCmdSyncGpuBoostGroupInfo__)(struct RmClientResource *, NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS *); + NV_STATUS (*__cliresCtrlCmdVgpuGetStartData__)(struct RmClientResource *, NV0000_CTRL_VGPU_GET_START_DATA_PARAMS *); + NV_STATUS (*__cliresCtrlCmdVgpuGetVgpuVersion__)(struct RmClientResource *, NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS *); + NV_STATUS (*__cliresCtrlCmdVgpuSetVgpuVersion__)(struct RmClientResource *, NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS *); + NV_STATUS (*__cliresCtrlCmdSystemNVPCFGetPowerModeInfo__)(struct RmClientResource *, NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemSyncExternalFabricMgmt__)(struct RmClientResource *, NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS *); + NV_STATUS (*__cliresCtrlCmdSystemPfmreqhndlrGetPerfSensorCounters__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS *); + NV_STATUS (*__cliresCtrlCmdSystemPfmreqhndlrGetExtendedPerfSensorCounters__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS *); NV_STATUS (*__cliresControl__)(struct RmClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__cliresUnmap__)(struct RmClientResource *, struct CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__cliresMapTo__)(struct RmClientResource *, RS_RES_MAP_TO_PARAMS *); @@ -162,6 +171,7 @@ struct RmClientResource { NV_STATUS (*__cliresControl_Prologue__)(struct RmClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__cliresPreDestruct__)(struct RmClientResource *); NV_STATUS (*__cliresUnmapFrom__)(struct RmClientResource *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__cliresIsDuplicate__)(struct RmClientResource *, NvHandle, NvBool *); PEVENTNOTIFICATION *(*__cliresGetNotificationListPtr__)(struct RmClientResource *); void (*__cliresControl_Epilogue__)(struct RmClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); struct NotifShare *(*__cliresGetNotificationShare__)(struct RmClientResource *); @@ -203,6 +213,7 @@ NV_STATUS __nvoc_objCreate_RmClientResource(RmClientResource**, Dynamic*, NvU32, #define cliresCtrlCmdSystemGetCpuInfo(pRmCliRes, pCpuInfoParams) cliresCtrlCmdSystemGetCpuInfo_DISPATCH(pRmCliRes, pCpuInfoParams) #define cliresCtrlCmdSystemGetFeatures(pRmCliRes, pParams) cliresCtrlCmdSystemGetFeatures_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdSystemGetBuildVersionV2(pRmCliRes, pParams) cliresCtrlCmdSystemGetBuildVersionV2_DISPATCH(pRmCliRes, pParams) +#define cliresCtrlCmdSystemExecuteAcpiMethod(pRmCliRes, pAcpiMethodParams) cliresCtrlCmdSystemExecuteAcpiMethod_DISPATCH(pRmCliRes, pAcpiMethodParams) #define cliresCtrlCmdSystemGetChipsetInfo(pRmCliRes, pChipsetInfo) cliresCtrlCmdSystemGetChipsetInfo_DISPATCH(pRmCliRes, pChipsetInfo) #define cliresCtrlCmdSystemSetMemorySize(pRmCliRes, pParams) cliresCtrlCmdSystemSetMemorySize_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdSystemGetClassList(pRmCliRes, pParams) cliresCtrlCmdSystemGetClassList_DISPATCH(pRmCliRes, pParams) @@ -220,6 +231,7 @@ NV_STATUS __nvoc_objCreate_RmClientResource(RmClientResource**, Dynamic*, NvU32, #define cliresCtrlCmdSystemGetFabricStatus(pRmCliRes, pParams) cliresCtrlCmdSystemGetFabricStatus_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdSystemGetRmInstanceId(pRmCliRes, pRmInstanceIdParams) cliresCtrlCmdSystemGetRmInstanceId_DISPATCH(pRmCliRes, pRmInstanceIdParams) #define cliresCtrlCmdSystemGetClientDatabaseInfo(pRmCliRes, pParams) cliresCtrlCmdSystemGetClientDatabaseInfo_DISPATCH(pRmCliRes, pParams) +#define cliresCtrlCmdSystemRmctrlCacheModeCtrl(pRmCliRes, pParams) cliresCtrlCmdSystemRmctrlCacheModeCtrl_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdNvdGetDumpSize(pRmCliRes, pDumpSizeParams) cliresCtrlCmdNvdGetDumpSize_DISPATCH(pRmCliRes, pDumpSizeParams) #define cliresCtrlCmdNvdGetDump(pRmCliRes, pDumpParams) cliresCtrlCmdNvdGetDump_DISPATCH(pRmCliRes, pDumpParams) #define cliresCtrlCmdNvdGetTimestamp(pRmCliRes, pTimestampParams) cliresCtrlCmdNvdGetTimestamp_DISPATCH(pRmCliRes, pTimestampParams) @@ -233,6 +245,7 @@ NV_STATUS __nvoc_objCreate_RmClientResource(RmClientResource**, Dynamic*, NvU32, #define cliresCtrlCmdClientSetInheritedSharePolicy(pRmCliRes, pParams) cliresCtrlCmdClientSetInheritedSharePolicy_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdClientShareObject(pRmCliRes, pParams) cliresCtrlCmdClientShareObject_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdClientGetChildHandle(pRmCliRes, pParams) cliresCtrlCmdClientGetChildHandle_DISPATCH(pRmCliRes, pParams) +#define cliresCtrlCmdObjectsAreDuplicates(pRmCliRes, pParams) cliresCtrlCmdObjectsAreDuplicates_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdGpuGetAttachedIds(pRmCliRes, pGpuAttachedIds) cliresCtrlCmdGpuGetAttachedIds_DISPATCH(pRmCliRes, pGpuAttachedIds) #define cliresCtrlCmdGpuGetIdInfo(pRmCliRes, pGpuIdInfoParams) cliresCtrlCmdGpuGetIdInfo_DISPATCH(pRmCliRes, pGpuIdInfoParams) #define cliresCtrlCmdGpuGetIdInfoV2(pRmCliRes, pGpuIdInfoParams) cliresCtrlCmdGpuGetIdInfoV2_DISPATCH(pRmCliRes, pGpuIdInfoParams) @@ -251,6 +264,7 @@ NV_STATUS __nvoc_objCreate_RmClientResource(RmClientResource**, Dynamic*, NvU32, #define cliresCtrlCmdGpuDisableNvlinkInit(pRmCliRes, pParams) cliresCtrlCmdGpuDisableNvlinkInit_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdLegacyConfig(pRmCliRes, pParams) cliresCtrlCmdLegacyConfig_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdIdleChannels(pRmCliRes, pParams) cliresCtrlCmdIdleChannels_DISPATCH(pRmCliRes, pParams) +#define cliresCtrlCmdPushGspUcode(pRmCliRes, pParams) cliresCtrlCmdPushGspUcode_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdGsyncGetAttachedIds(pRmCliRes, pGsyncAttachedIds) cliresCtrlCmdGsyncGetAttachedIds_DISPATCH(pRmCliRes, pGsyncAttachedIds) #define cliresCtrlCmdGsyncGetIdInfo(pRmCliRes, pGsyncIdInfoParams) cliresCtrlCmdGsyncGetIdInfo_DISPATCH(pRmCliRes, pGsyncIdInfoParams) #define cliresCtrlCmdEventSetNotification(pRmCliRes, pEventSetNotificationParams) cliresCtrlCmdEventSetNotification_DISPATCH(pRmCliRes, pEventSetNotificationParams) @@ -273,7 +287,13 @@ NV_STATUS __nvoc_objCreate_RmClientResource(RmClientResource**, Dynamic*, NvU32, #define cliresCtrlCmdSyncGpuBoostGroupCreate(pRmCliRes, pParams) cliresCtrlCmdSyncGpuBoostGroupCreate_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdSyncGpuBoostGroupDestroy(pRmCliRes, pParams) cliresCtrlCmdSyncGpuBoostGroupDestroy_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdSyncGpuBoostGroupInfo(pRmCliRes, pParams) cliresCtrlCmdSyncGpuBoostGroupInfo_DISPATCH(pRmCliRes, pParams) +#define cliresCtrlCmdVgpuGetStartData(pRmCliRes, pVgpuStartParams) cliresCtrlCmdVgpuGetStartData_DISPATCH(pRmCliRes, pVgpuStartParams) +#define cliresCtrlCmdVgpuGetVgpuVersion(pRmCliRes, vgpuVersionInfo) cliresCtrlCmdVgpuGetVgpuVersion_DISPATCH(pRmCliRes, vgpuVersionInfo) +#define cliresCtrlCmdVgpuSetVgpuVersion(pRmCliRes, vgpuVersionInfo) cliresCtrlCmdVgpuSetVgpuVersion_DISPATCH(pRmCliRes, vgpuVersionInfo) +#define cliresCtrlCmdSystemNVPCFGetPowerModeInfo(pRmCliRes, pParams) cliresCtrlCmdSystemNVPCFGetPowerModeInfo_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdSystemSyncExternalFabricMgmt(pRmCliRes, pExtFabricMgmtParams) cliresCtrlCmdSystemSyncExternalFabricMgmt_DISPATCH(pRmCliRes, pExtFabricMgmtParams) +#define cliresCtrlCmdSystemPfmreqhndlrGetPerfSensorCounters(pRmCliRes, pParams) cliresCtrlCmdSystemPfmreqhndlrGetPerfSensorCounters_DISPATCH(pRmCliRes, pParams) +#define cliresCtrlCmdSystemPfmreqhndlrGetExtendedPerfSensorCounters(pRmCliRes, pParams) cliresCtrlCmdSystemPfmreqhndlrGetExtendedPerfSensorCounters_DISPATCH(pRmCliRes, pParams) #define cliresControl(pResource, pCallContext, pParams) cliresControl_DISPATCH(pResource, pCallContext, pParams) #define cliresUnmap(pResource, pCallContext, pCpuMapping) cliresUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define cliresMapTo(pResource, pParams) cliresMapTo_DISPATCH(pResource, pParams) @@ -286,6 +306,7 @@ NV_STATUS __nvoc_objCreate_RmClientResource(RmClientResource**, Dynamic*, NvU32, #define cliresControl_Prologue(pResource, pCallContext, pParams) cliresControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define cliresPreDestruct(pResource) cliresPreDestruct_DISPATCH(pResource) #define cliresUnmapFrom(pResource, pParams) cliresUnmapFrom_DISPATCH(pResource, pParams) +#define cliresIsDuplicate(pResource, hMemory, pDuplicate) cliresIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define cliresGetNotificationListPtr(pNotifier) cliresGetNotificationListPtr_DISPATCH(pNotifier) #define cliresControl_Epilogue(pResource, pCallContext, pParams) cliresControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define cliresGetNotificationShare(pNotifier) cliresGetNotificationShare_DISPATCH(pNotifier) @@ -322,6 +343,12 @@ static inline NV_STATUS cliresCtrlCmdSystemGetBuildVersionV2_DISPATCH(struct RmC return pRmCliRes->__cliresCtrlCmdSystemGetBuildVersionV2__(pRmCliRes, pParams); } +NV_STATUS cliresCtrlCmdSystemExecuteAcpiMethod_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS *pAcpiMethodParams); + +static inline NV_STATUS cliresCtrlCmdSystemExecuteAcpiMethod_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS *pAcpiMethodParams) { + return pRmCliRes->__cliresCtrlCmdSystemExecuteAcpiMethod__(pRmCliRes, pAcpiMethodParams); +} + NV_STATUS cliresCtrlCmdSystemGetChipsetInfo_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS *pChipsetInfo); static inline NV_STATUS cliresCtrlCmdSystemGetChipsetInfo_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS *pChipsetInfo) { @@ -424,6 +451,12 @@ static inline NV_STATUS cliresCtrlCmdSystemGetClientDatabaseInfo_DISPATCH(struct return pRmCliRes->__cliresCtrlCmdSystemGetClientDatabaseInfo__(pRmCliRes, pParams); } +NV_STATUS cliresCtrlCmdSystemRmctrlCacheModeCtrl_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS *pParams); + +static inline NV_STATUS cliresCtrlCmdSystemRmctrlCacheModeCtrl_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS *pParams) { + return pRmCliRes->__cliresCtrlCmdSystemRmctrlCacheModeCtrl__(pRmCliRes, pParams); +} + NV_STATUS cliresCtrlCmdNvdGetDumpSize_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS *pDumpSizeParams); static inline NV_STATUS cliresCtrlCmdNvdGetDumpSize_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_NVD_GET_DUMP_SIZE_PARAMS *pDumpSizeParams) { @@ -502,6 +535,12 @@ static inline NV_STATUS cliresCtrlCmdClientGetChildHandle_DISPATCH(struct RmClie return pRmCliRes->__cliresCtrlCmdClientGetChildHandle__(pRmCliRes, pParams); } +NV_STATUS cliresCtrlCmdObjectsAreDuplicates_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS *pParams); + +static inline NV_STATUS cliresCtrlCmdObjectsAreDuplicates_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS *pParams) { + return pRmCliRes->__cliresCtrlCmdObjectsAreDuplicates__(pRmCliRes, pParams); +} + NV_STATUS cliresCtrlCmdGpuGetAttachedIds_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS *pGpuAttachedIds); static inline NV_STATUS cliresCtrlCmdGpuGetAttachedIds_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS *pGpuAttachedIds) { @@ -610,6 +649,12 @@ static inline NV_STATUS cliresCtrlCmdIdleChannels_DISPATCH(struct RmClientResour return pRmCliRes->__cliresCtrlCmdIdleChannels__(pRmCliRes, pParams); } +NV_STATUS cliresCtrlCmdPushGspUcode_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS *pParams); + +static inline NV_STATUS cliresCtrlCmdPushGspUcode_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS *pParams) { + return pRmCliRes->__cliresCtrlCmdPushGspUcode__(pRmCliRes, pParams); +} + NV_STATUS cliresCtrlCmdGsyncGetAttachedIds_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS *pGsyncAttachedIds); static inline NV_STATUS cliresCtrlCmdGsyncGetAttachedIds_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS *pGsyncAttachedIds) { @@ -742,12 +787,48 @@ static inline NV_STATUS cliresCtrlCmdSyncGpuBoostGroupInfo_DISPATCH(struct RmCli return pRmCliRes->__cliresCtrlCmdSyncGpuBoostGroupInfo__(pRmCliRes, pParams); } +NV_STATUS cliresCtrlCmdVgpuGetStartData_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_VGPU_GET_START_DATA_PARAMS *pVgpuStartParams); + +static inline NV_STATUS cliresCtrlCmdVgpuGetStartData_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_VGPU_GET_START_DATA_PARAMS *pVgpuStartParams) { + return pRmCliRes->__cliresCtrlCmdVgpuGetStartData__(pRmCliRes, pVgpuStartParams); +} + +NV_STATUS cliresCtrlCmdVgpuGetVgpuVersion_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS *vgpuVersionInfo); + +static inline NV_STATUS cliresCtrlCmdVgpuGetVgpuVersion_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS *vgpuVersionInfo) { + return pRmCliRes->__cliresCtrlCmdVgpuGetVgpuVersion__(pRmCliRes, vgpuVersionInfo); +} + +NV_STATUS cliresCtrlCmdVgpuSetVgpuVersion_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS *vgpuVersionInfo); + +static inline NV_STATUS cliresCtrlCmdVgpuSetVgpuVersion_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS *vgpuVersionInfo) { + return pRmCliRes->__cliresCtrlCmdVgpuSetVgpuVersion__(pRmCliRes, vgpuVersionInfo); +} + +NV_STATUS cliresCtrlCmdSystemNVPCFGetPowerModeInfo_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS *pParams); + +static inline NV_STATUS cliresCtrlCmdSystemNVPCFGetPowerModeInfo_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS *pParams) { + return pRmCliRes->__cliresCtrlCmdSystemNVPCFGetPowerModeInfo__(pRmCliRes, pParams); +} + NV_STATUS cliresCtrlCmdSystemSyncExternalFabricMgmt_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS *pExtFabricMgmtParams); static inline NV_STATUS cliresCtrlCmdSystemSyncExternalFabricMgmt_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS *pExtFabricMgmtParams) { return pRmCliRes->__cliresCtrlCmdSystemSyncExternalFabricMgmt__(pRmCliRes, pExtFabricMgmtParams); } +NV_STATUS cliresCtrlCmdSystemPfmreqhndlrGetPerfSensorCounters_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS *pParams); + +static inline NV_STATUS cliresCtrlCmdSystemPfmreqhndlrGetPerfSensorCounters_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS *pParams) { + return pRmCliRes->__cliresCtrlCmdSystemPfmreqhndlrGetPerfSensorCounters__(pRmCliRes, pParams); +} + +NV_STATUS cliresCtrlCmdSystemPfmreqhndlrGetExtendedPerfSensorCounters_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS *pParams); + +static inline NV_STATUS cliresCtrlCmdSystemPfmreqhndlrGetExtendedPerfSensorCounters_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS *pParams) { + return pRmCliRes->__cliresCtrlCmdSystemPfmreqhndlrGetExtendedPerfSensorCounters__(pRmCliRes, pParams); +} + static inline NV_STATUS cliresControl_DISPATCH(struct RmClientResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__cliresControl__(pResource, pCallContext, pParams); } @@ -796,6 +877,10 @@ static inline NV_STATUS cliresUnmapFrom_DISPATCH(struct RmClientResource *pResou return pResource->__cliresUnmapFrom__(pResource, pParams); } +static inline NV_STATUS cliresIsDuplicate_DISPATCH(struct RmClientResource *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__cliresIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline PEVENTNOTIFICATION *cliresGetNotificationListPtr_DISPATCH(struct RmClientResource *pNotifier) { return pNotifier->__cliresGetNotificationListPtr__(pNotifier); } @@ -821,8 +906,10 @@ static inline NV_STATUS cliresGetOrAllocNotifShare_DISPATCH(struct RmClientResou } NV_STATUS cliresConstruct_IMPL(struct RmClientResource *arg_pRmCliRes, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_cliresConstruct(arg_pRmCliRes, arg_pCallContext, arg_pParams) cliresConstruct_IMPL(arg_pRmCliRes, arg_pCallContext, arg_pParams) void cliresDestruct_IMPL(struct RmClientResource *pRmCliRes); + #define __nvoc_cliresDestruct(pRmCliRes) cliresDestruct_IMPL(pRmCliRes) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_compute_instance_subscription_nvoc.c b/src/nvidia/generated/g_compute_instance_subscription_nvoc.c index 8bee30fe8..58e63e216 100644 --- a/src/nvidia/generated/g_compute_instance_subscription_nvoc.c +++ b/src/nvidia/generated/g_compute_instance_subscription_nvoc.c @@ -165,6 +165,10 @@ static NV_STATUS __nvoc_thunk_RsResource_cisubscriptionUnmapFrom(struct ComputeI return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_cisubscriptionIsDuplicate(struct ComputeInstanceSubscription *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_cisubscriptionControl_Epilogue(struct ComputeInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RmResource.offset), pCallContext, pParams); } @@ -286,6 +290,8 @@ static void __nvoc_init_funcTable_ComputeInstanceSubscription_1(ComputeInstanceS pThis->__cisubscriptionUnmapFrom__ = &__nvoc_thunk_RsResource_cisubscriptionUnmapFrom; + pThis->__cisubscriptionIsDuplicate__ = &__nvoc_thunk_RsResource_cisubscriptionIsDuplicate; + pThis->__cisubscriptionControl_Epilogue__ = &__nvoc_thunk_RmResource_cisubscriptionControl_Epilogue; pThis->__cisubscriptionControlLookup__ = &__nvoc_thunk_RsResource_cisubscriptionControlLookup; diff --git a/src/nvidia/generated/g_compute_instance_subscription_nvoc.h b/src/nvidia/generated/g_compute_instance_subscription_nvoc.h index d81d4e390..61536b0ea 100644 --- a/src/nvidia/generated/g_compute_instance_subscription_nvoc.h +++ b/src/nvidia/generated/g_compute_instance_subscription_nvoc.h @@ -83,6 +83,7 @@ struct ComputeInstanceSubscription { NV_STATUS (*__cisubscriptionInternalControlForward__)(struct ComputeInstanceSubscription *, NvU32, void *, NvU32); void (*__cisubscriptionPreDestruct__)(struct ComputeInstanceSubscription *); NV_STATUS (*__cisubscriptionUnmapFrom__)(struct ComputeInstanceSubscription *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__cisubscriptionIsDuplicate__)(struct ComputeInstanceSubscription *, NvHandle, NvBool *); void (*__cisubscriptionControl_Epilogue__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__cisubscriptionControlLookup__)(struct ComputeInstanceSubscription *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__cisubscriptionMap__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -138,6 +139,7 @@ NV_STATUS __nvoc_objCreate_ComputeInstanceSubscription(ComputeInstanceSubscripti #define cisubscriptionInternalControlForward(pGpuResource, command, pParams, size) cisubscriptionInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define cisubscriptionPreDestruct(pResource) cisubscriptionPreDestruct_DISPATCH(pResource) #define cisubscriptionUnmapFrom(pResource, pParams) cisubscriptionUnmapFrom_DISPATCH(pResource, pParams) +#define cisubscriptionIsDuplicate(pResource, hMemory, pDuplicate) cisubscriptionIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define cisubscriptionControl_Epilogue(pResource, pCallContext, pParams) cisubscriptionControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define cisubscriptionControlLookup(pResource, pParams, ppEntry) cisubscriptionControlLookup_DISPATCH(pResource, pParams, ppEntry) #define cisubscriptionMap(pGpuResource, pCallContext, pParams, pCpuMapping) cisubscriptionMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -222,6 +224,10 @@ static inline NV_STATUS cisubscriptionUnmapFrom_DISPATCH(struct ComputeInstanceS return pResource->__cisubscriptionUnmapFrom__(pResource, pParams); } +static inline NV_STATUS cisubscriptionIsDuplicate_DISPATCH(struct ComputeInstanceSubscription *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__cisubscriptionIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void cisubscriptionControl_Epilogue_DISPATCH(struct ComputeInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__cisubscriptionControl_Epilogue__(pResource, pCallContext, pParams); } @@ -239,10 +245,13 @@ static inline NvBool cisubscriptionAccessCallback_DISPATCH(struct ComputeInstanc } NV_STATUS cisubscriptionGetComputeInstanceSubscription_IMPL(struct RsClient *arg0, NvHandle arg1, struct ComputeInstanceSubscription **arg2); + #define cisubscriptionGetComputeInstanceSubscription(arg0, arg1, arg2) cisubscriptionGetComputeInstanceSubscription_IMPL(arg0, arg1, arg2) NV_STATUS cisubscriptionConstruct_IMPL(struct ComputeInstanceSubscription *arg_pComputeInstanceSubscription, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_cisubscriptionConstruct(arg_pComputeInstanceSubscription, arg_pCallContext, arg_pParams) cisubscriptionConstruct_IMPL(arg_pComputeInstanceSubscription, arg_pCallContext, arg_pParams) NV_STATUS cisubscriptionCopyConstruct_IMPL(struct ComputeInstanceSubscription *arg0, CALL_CONTEXT *arg1, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg2); + #ifdef __nvoc_compute_instance_subscription_h_disabled static inline NV_STATUS cisubscriptionCopyConstruct(struct ComputeInstanceSubscription *arg0, CALL_CONTEXT *arg1, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg2) { NV_ASSERT_FAILED_PRECOMP("ComputeInstanceSubscription was disabled!"); @@ -253,6 +262,7 @@ static inline NV_STATUS cisubscriptionCopyConstruct(struct ComputeInstanceSubscr #endif //__nvoc_compute_instance_subscription_h_disabled void cisubscriptionDestruct_IMPL(struct ComputeInstanceSubscription *arg0); + #define __nvoc_cisubscriptionDestruct(arg0) cisubscriptionDestruct_IMPL(arg0) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_console_mem_nvoc.c b/src/nvidia/generated/g_console_mem_nvoc.c index 1dafe3169..8f709ae93 100644 --- a/src/nvidia/generated/g_console_mem_nvoc.c +++ b/src/nvidia/generated/g_console_mem_nvoc.c @@ -145,8 +145,12 @@ static NV_STATUS __nvoc_thunk_RmResource_conmemControl_Prologue(struct ConsoleMe return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_Memory_conmemIsReady(struct ConsoleMemory *pMemory) { - return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset)); +static NvBool __nvoc_thunk_Memory_conmemIsGpuMapAllowed(struct ConsoleMemory *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), pGpu); +} + +static NV_STATUS __nvoc_thunk_Memory_conmemIsReady(struct ConsoleMemory *pMemory, NvBool bCopyConstructorContext) { + return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), bCopyConstructorContext); } static NV_STATUS __nvoc_thunk_Memory_conmemCheckCopyPermissions(struct ConsoleMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { @@ -157,6 +161,10 @@ static void __nvoc_thunk_RsResource_conmemPreDestruct(struct ConsoleMemory *pRes resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_Memory_conmemIsDuplicate(struct ConsoleMemory *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), hMemory, pDuplicate); +} + static NV_STATUS __nvoc_thunk_RsResource_conmemUnmapFrom(struct ConsoleMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset), pParams); } @@ -243,12 +251,16 @@ static void __nvoc_init_funcTable_ConsoleMemory_1(ConsoleMemory *pThis) { pThis->__conmemControl_Prologue__ = &__nvoc_thunk_RmResource_conmemControl_Prologue; + pThis->__conmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_conmemIsGpuMapAllowed; + pThis->__conmemIsReady__ = &__nvoc_thunk_Memory_conmemIsReady; pThis->__conmemCheckCopyPermissions__ = &__nvoc_thunk_Memory_conmemCheckCopyPermissions; pThis->__conmemPreDestruct__ = &__nvoc_thunk_RsResource_conmemPreDestruct; + pThis->__conmemIsDuplicate__ = &__nvoc_thunk_Memory_conmemIsDuplicate; + pThis->__conmemUnmapFrom__ = &__nvoc_thunk_RsResource_conmemUnmapFrom; pThis->__conmemControl_Epilogue__ = &__nvoc_thunk_RmResource_conmemControl_Epilogue; diff --git a/src/nvidia/generated/g_console_mem_nvoc.h b/src/nvidia/generated/g_console_mem_nvoc.h index b55113bbc..ef14876c9 100644 --- a/src/nvidia/generated/g_console_mem_nvoc.h +++ b/src/nvidia/generated/g_console_mem_nvoc.h @@ -66,9 +66,11 @@ struct ConsoleMemory { NvU32 (*__conmemGetRefCount__)(struct ConsoleMemory *); NV_STATUS (*__conmemMapTo__)(struct ConsoleMemory *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__conmemControl_Prologue__)(struct ConsoleMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__conmemIsReady__)(struct ConsoleMemory *); + NvBool (*__conmemIsGpuMapAllowed__)(struct ConsoleMemory *, struct OBJGPU *); + NV_STATUS (*__conmemIsReady__)(struct ConsoleMemory *, NvBool); NV_STATUS (*__conmemCheckCopyPermissions__)(struct ConsoleMemory *, struct OBJGPU *, NvHandle); void (*__conmemPreDestruct__)(struct ConsoleMemory *); + NV_STATUS (*__conmemIsDuplicate__)(struct ConsoleMemory *, NvHandle, NvBool *); NV_STATUS (*__conmemUnmapFrom__)(struct ConsoleMemory *, RS_RES_UNMAP_FROM_PARAMS *); void (*__conmemControl_Epilogue__)(struct ConsoleMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__conmemControlLookup__)(struct ConsoleMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); @@ -117,9 +119,11 @@ NV_STATUS __nvoc_objCreate_ConsoleMemory(ConsoleMemory**, Dynamic*, NvU32, CALL_ #define conmemGetRefCount(pResource) conmemGetRefCount_DISPATCH(pResource) #define conmemMapTo(pResource, pParams) conmemMapTo_DISPATCH(pResource, pParams) #define conmemControl_Prologue(pResource, pCallContext, pParams) conmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define conmemIsReady(pMemory) conmemIsReady_DISPATCH(pMemory) +#define conmemIsGpuMapAllowed(pMemory, pGpu) conmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define conmemIsReady(pMemory, bCopyConstructorContext) conmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define conmemCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) conmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) #define conmemPreDestruct(pResource) conmemPreDestruct_DISPATCH(pResource) +#define conmemIsDuplicate(pMemory, hMemory, pDuplicate) conmemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) #define conmemUnmapFrom(pResource, pParams) conmemUnmapFrom_DISPATCH(pResource, pParams) #define conmemControl_Epilogue(pResource, pCallContext, pParams) conmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define conmemControlLookup(pResource, pParams, ppEntry) conmemControlLookup_DISPATCH(pResource, pParams, ppEntry) @@ -179,8 +183,12 @@ static inline NV_STATUS conmemControl_Prologue_DISPATCH(struct ConsoleMemory *pR return pResource->__conmemControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS conmemIsReady_DISPATCH(struct ConsoleMemory *pMemory) { - return pMemory->__conmemIsReady__(pMemory); +static inline NvBool conmemIsGpuMapAllowed_DISPATCH(struct ConsoleMemory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__conmemIsGpuMapAllowed__(pMemory, pGpu); +} + +static inline NV_STATUS conmemIsReady_DISPATCH(struct ConsoleMemory *pMemory, NvBool bCopyConstructorContext) { + return pMemory->__conmemIsReady__(pMemory, bCopyConstructorContext); } static inline NV_STATUS conmemCheckCopyPermissions_DISPATCH(struct ConsoleMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { @@ -191,6 +199,10 @@ static inline void conmemPreDestruct_DISPATCH(struct ConsoleMemory *pResource) { pResource->__conmemPreDestruct__(pResource); } +static inline NV_STATUS conmemIsDuplicate_DISPATCH(struct ConsoleMemory *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return pMemory->__conmemIsDuplicate__(pMemory, hMemory, pDuplicate); +} + static inline NV_STATUS conmemUnmapFrom_DISPATCH(struct ConsoleMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return pResource->__conmemUnmapFrom__(pResource, pParams); } @@ -212,6 +224,7 @@ static inline NvBool conmemAccessCallback_DISPATCH(struct ConsoleMemory *pResour } NV_STATUS conmemConstruct_IMPL(struct ConsoleMemory *arg_pConsoleMemory, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_conmemConstruct(arg_pConsoleMemory, arg_pCallContext, arg_pParams) conmemConstruct_IMPL(arg_pConsoleMemory, arg_pCallContext, arg_pParams) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_context_dma_nvoc.c b/src/nvidia/generated/g_context_dma_nvoc.c index f686355af..dde7cc317 100644 --- a/src/nvidia/generated/g_context_dma_nvoc.c +++ b/src/nvidia/generated/g_context_dma_nvoc.c @@ -170,6 +170,10 @@ static void __nvoc_thunk_RsResource_ctxdmaPreDestruct(struct ContextDma *pResour resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_RsResource_ctxdmaIsDuplicate(struct ContextDma *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset), hMemory, pDuplicate); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_ctxdmaGetNotificationListPtr(struct ContextDma *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_ContextDma_Notifier.offset)); } @@ -348,6 +352,8 @@ static void __nvoc_init_funcTable_ContextDma_1(ContextDma *pThis) { pThis->__ctxdmaPreDestruct__ = &__nvoc_thunk_RsResource_ctxdmaPreDestruct; + pThis->__ctxdmaIsDuplicate__ = &__nvoc_thunk_RsResource_ctxdmaIsDuplicate; + pThis->__ctxdmaGetNotificationListPtr__ = &__nvoc_thunk_Notifier_ctxdmaGetNotificationListPtr; pThis->__ctxdmaControl_Epilogue__ = &__nvoc_thunk_RmResource_ctxdmaControl_Epilogue; diff --git a/src/nvidia/generated/g_context_dma_nvoc.h b/src/nvidia/generated/g_context_dma_nvoc.h index 77e92cdca..8534d0410 100644 --- a/src/nvidia/generated/g_context_dma_nvoc.h +++ b/src/nvidia/generated/g_context_dma_nvoc.h @@ -108,6 +108,7 @@ struct ContextDma { NV_STATUS (*__ctxdmaControl_Prologue__)(struct ContextDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__ctxdmaAddAdditionalDependants__)(struct RsClient *, struct ContextDma *, RsResourceRef *); void (*__ctxdmaPreDestruct__)(struct ContextDma *); + NV_STATUS (*__ctxdmaIsDuplicate__)(struct ContextDma *, NvHandle, NvBool *); PEVENTNOTIFICATION *(*__ctxdmaGetNotificationListPtr__)(struct ContextDma *); void (*__ctxdmaControl_Epilogue__)(struct ContextDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); struct NotifShare *(*__ctxdmaGetNotificationShare__)(struct ContextDma *); @@ -184,6 +185,7 @@ NV_STATUS __nvoc_objCreate_ContextDma(ContextDma**, Dynamic*, NvU32, struct CALL #define ctxdmaControl_Prologue(pResource, pCallContext, pParams) ctxdmaControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define ctxdmaAddAdditionalDependants(pClient, pResource, pReference) ctxdmaAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define ctxdmaPreDestruct(pResource) ctxdmaPreDestruct_DISPATCH(pResource) +#define ctxdmaIsDuplicate(pResource, hMemory, pDuplicate) ctxdmaIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define ctxdmaGetNotificationListPtr(pNotifier) ctxdmaGetNotificationListPtr_DISPATCH(pNotifier) #define ctxdmaControl_Epilogue(pResource, pCallContext, pParams) ctxdmaControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define ctxdmaGetNotificationShare(pNotifier) ctxdmaGetNotificationShare_DISPATCH(pNotifier) @@ -292,6 +294,10 @@ static inline void ctxdmaPreDestruct_DISPATCH(struct ContextDma *pResource) { pResource->__ctxdmaPreDestruct__(pResource); } +static inline NV_STATUS ctxdmaIsDuplicate_DISPATCH(struct ContextDma *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__ctxdmaIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline PEVENTNOTIFICATION *ctxdmaGetNotificationListPtr_DISPATCH(struct ContextDma *pNotifier) { return pNotifier->__ctxdmaGetNotificationListPtr__(pNotifier); } @@ -317,10 +323,13 @@ static inline NV_STATUS ctxdmaGetOrAllocNotifShare_DISPATCH(struct ContextDma *p } NV_STATUS ctxdmaConstruct_IMPL(struct ContextDma *arg_pCtxdma, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_ctxdmaConstruct(arg_pCtxdma, arg_pCallContext, arg_pParams) ctxdmaConstruct_IMPL(arg_pCtxdma, arg_pCallContext, arg_pParams) void ctxdmaDestruct_IMPL(struct ContextDma *pCtxdma); + #define __nvoc_ctxdmaDestruct(pCtxdma) ctxdmaDestruct_IMPL(pCtxdma) NvBool ctxdmaIsBound_IMPL(struct ContextDma *pContextDma); + #ifdef __nvoc_context_dma_h_disabled static inline NvBool ctxdmaIsBound(struct ContextDma *pContextDma) { NV_ASSERT_FAILED_PRECOMP("ContextDma was disabled!"); @@ -331,6 +340,7 @@ static inline NvBool ctxdmaIsBound(struct ContextDma *pContextDma) { #endif //__nvoc_context_dma_h_disabled NV_STATUS ctxdmaGetByHandle_IMPL(struct RsClient *pClient, NvHandle hContextDma, struct ContextDma **arg0); + #define ctxdmaGetByHandle(pClient, hContextDma, arg0) ctxdmaGetByHandle_IMPL(pClient, hContextDma, arg0) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_dbgbuffer_nvoc.c b/src/nvidia/generated/g_dbgbuffer_nvoc.c index 9be61cb84..b216107ca 100644 --- a/src/nvidia/generated/g_dbgbuffer_nvoc.c +++ b/src/nvidia/generated/g_dbgbuffer_nvoc.c @@ -169,6 +169,10 @@ static NV_STATUS __nvoc_thunk_RsResource_dbgbufUnmapFrom(struct DebugBufferApi * return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_dbgbufIsDuplicate(struct DebugBufferApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_dbgbufControl_Epilogue(struct DebugBufferApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RmResource.offset), pCallContext, pParams); } @@ -266,6 +270,8 @@ static void __nvoc_init_funcTable_DebugBufferApi_1(DebugBufferApi *pThis) { pThis->__dbgbufUnmapFrom__ = &__nvoc_thunk_RsResource_dbgbufUnmapFrom; + pThis->__dbgbufIsDuplicate__ = &__nvoc_thunk_RsResource_dbgbufIsDuplicate; + pThis->__dbgbufControl_Epilogue__ = &__nvoc_thunk_RmResource_dbgbufControl_Epilogue; pThis->__dbgbufControlLookup__ = &__nvoc_thunk_RsResource_dbgbufControlLookup; diff --git a/src/nvidia/generated/g_dbgbuffer_nvoc.h b/src/nvidia/generated/g_dbgbuffer_nvoc.h index d087c40f4..d15bd3c89 100644 --- a/src/nvidia/generated/g_dbgbuffer_nvoc.h +++ b/src/nvidia/generated/g_dbgbuffer_nvoc.h @@ -80,6 +80,7 @@ struct DebugBufferApi { NV_STATUS (*__dbgbufInternalControlForward__)(struct DebugBufferApi *, NvU32, void *, NvU32); void (*__dbgbufPreDestruct__)(struct DebugBufferApi *); NV_STATUS (*__dbgbufUnmapFrom__)(struct DebugBufferApi *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__dbgbufIsDuplicate__)(struct DebugBufferApi *, NvHandle, NvBool *); void (*__dbgbufControl_Epilogue__)(struct DebugBufferApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dbgbufControlLookup__)(struct DebugBufferApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvBool (*__dbgbufAccessCallback__)(struct DebugBufferApi *, struct RsClient *, void *, RsAccessRight); @@ -133,6 +134,7 @@ NV_STATUS __nvoc_objCreate_DebugBufferApi(DebugBufferApi**, Dynamic*, NvU32, CAL #define dbgbufInternalControlForward(pGpuResource, command, pParams, size) dbgbufInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define dbgbufPreDestruct(pResource) dbgbufPreDestruct_DISPATCH(pResource) #define dbgbufUnmapFrom(pResource, pParams) dbgbufUnmapFrom_DISPATCH(pResource, pParams) +#define dbgbufIsDuplicate(pResource, hMemory, pDuplicate) dbgbufIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define dbgbufControl_Epilogue(pResource, pCallContext, pParams) dbgbufControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define dbgbufControlLookup(pResource, pParams, ppEntry) dbgbufControlLookup_DISPATCH(pResource, pParams, ppEntry) #define dbgbufAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) dbgbufAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) @@ -220,6 +222,10 @@ static inline NV_STATUS dbgbufUnmapFrom_DISPATCH(struct DebugBufferApi *pResourc return pResource->__dbgbufUnmapFrom__(pResource, pParams); } +static inline NV_STATUS dbgbufIsDuplicate_DISPATCH(struct DebugBufferApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__dbgbufIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void dbgbufControl_Epilogue_DISPATCH(struct DebugBufferApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__dbgbufControl_Epilogue__(pResource, pCallContext, pParams); } @@ -233,8 +239,10 @@ static inline NvBool dbgbufAccessCallback_DISPATCH(struct DebugBufferApi *pResou } NV_STATUS dbgbufConstruct_IMPL(struct DebugBufferApi *arg_pDebugBufferApi, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_dbgbufConstruct(arg_pDebugBufferApi, arg_pCallContext, arg_pParams) dbgbufConstruct_IMPL(arg_pDebugBufferApi, arg_pCallContext, arg_pParams) void dbgbufDestruct_IMPL(struct DebugBufferApi *pDebugBufferApi); + #define __nvoc_dbgbufDestruct(pDebugBufferApi) dbgbufDestruct_IMPL(pDebugBufferApi) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_dce_client_nvoc.h b/src/nvidia/generated/g_dce_client_nvoc.h index 29147d09b..c5028b208 100644 --- a/src/nvidia/generated/g_dce_client_nvoc.h +++ b/src/nvidia/generated/g_dce_client_nvoc.h @@ -223,6 +223,7 @@ static inline NvBool dceclientIsPresent_DISPATCH(POBJGPU pGpu, struct OBJDCECLIE } NV_STATUS dceclientInitRpcInfra_IMPL(struct OBJGPU *arg0, struct OBJDCECLIENTRM *arg1); + #ifdef __nvoc_dce_client_h_disabled static inline NV_STATUS dceclientInitRpcInfra(struct OBJGPU *arg0, struct OBJDCECLIENTRM *arg1) { NV_ASSERT_FAILED_PRECOMP("OBJDCECLIENTRM was disabled!"); @@ -233,6 +234,7 @@ static inline NV_STATUS dceclientInitRpcInfra(struct OBJGPU *arg0, struct OBJDCE #endif //__nvoc_dce_client_h_disabled void dceclientDeinitRpcInfra_IMPL(struct OBJDCECLIENTRM *arg0); + #ifdef __nvoc_dce_client_h_disabled static inline void dceclientDeinitRpcInfra(struct OBJDCECLIENTRM *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJDCECLIENTRM was disabled!"); @@ -242,6 +244,7 @@ static inline void dceclientDeinitRpcInfra(struct OBJDCECLIENTRM *arg0) { #endif //__nvoc_dce_client_h_disabled NV_STATUS dceclientDceRmInit_IMPL(struct OBJGPU *arg0, struct OBJDCECLIENTRM *arg1, NvBool arg2); + #ifdef __nvoc_dce_client_h_disabled static inline NV_STATUS dceclientDceRmInit(struct OBJGPU *arg0, struct OBJDCECLIENTRM *arg1, NvBool arg2) { NV_ASSERT_FAILED_PRECOMP("OBJDCECLIENTRM was disabled!"); @@ -252,6 +255,7 @@ static inline NV_STATUS dceclientDceRmInit(struct OBJGPU *arg0, struct OBJDCECLI #endif //__nvoc_dce_client_h_disabled NV_STATUS dceclientSendRpc_IMPL(struct OBJDCECLIENTRM *arg0, void *arg1, NvU32 arg2); + #ifdef __nvoc_dce_client_h_disabled static inline NV_STATUS dceclientSendRpc(struct OBJDCECLIENTRM *arg0, void *arg1, NvU32 arg2) { NV_ASSERT_FAILED_PRECOMP("OBJDCECLIENTRM was disabled!"); diff --git a/src/nvidia/generated/g_deferred_api_nvoc.c b/src/nvidia/generated/g_deferred_api_nvoc.c index cbbb6e212..2ced6e1d6 100644 --- a/src/nvidia/generated/g_deferred_api_nvoc.c +++ b/src/nvidia/generated/g_deferred_api_nvoc.c @@ -220,6 +220,10 @@ static void __nvoc_thunk_RsResource_defapiPreDestruct(struct DeferredApiObject * resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DeferredApiObject_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_RsResource_defapiIsDuplicate(struct DeferredApiObject *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DeferredApiObject_RsResource.offset), hMemory, pDuplicate); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_defapiGetNotificationListPtr(struct DeferredApiObject *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DeferredApiObject_Notifier.offset)); } @@ -395,6 +399,8 @@ static void __nvoc_init_funcTable_DeferredApiObject_1(DeferredApiObject *pThis) pThis->__defapiPreDestruct__ = &__nvoc_thunk_RsResource_defapiPreDestruct; + pThis->__defapiIsDuplicate__ = &__nvoc_thunk_RsResource_defapiIsDuplicate; + pThis->__defapiGetNotificationListPtr__ = &__nvoc_thunk_Notifier_defapiGetNotificationListPtr; pThis->__defapiGetNotificationShare__ = &__nvoc_thunk_Notifier_defapiGetNotificationShare; diff --git a/src/nvidia/generated/g_deferred_api_nvoc.h b/src/nvidia/generated/g_deferred_api_nvoc.h index 0e2c3eca9..e1dae0b98 100644 --- a/src/nvidia/generated/g_deferred_api_nvoc.h +++ b/src/nvidia/generated/g_deferred_api_nvoc.h @@ -52,27 +52,7 @@ typedef struct _def_deferred_api_info RS_PRIV_LEVEL privLevel; // privilege level of the client that initiated deferred call. void * pDeferredApiInfo; NvP64 pDeferredPrivateData; -} DEFERRED_API_INFO, *PDEFERRED_API_INFO; - -// RS-TODO: Delete. Keeping old typedef for transition. -typedef struct DeferredApiObject *PDEFERRED_API_OBJECT; - -#ifndef __NVOC_CLASS_DeferredApiObject_TYPEDEF__ -#define __NVOC_CLASS_DeferredApiObject_TYPEDEF__ -typedef struct DeferredApiObject DeferredApiObject; -#endif /* __NVOC_CLASS_DeferredApiObject_TYPEDEF__ */ - -#ifndef __nvoc_class_id_DeferredApiObject -#define __nvoc_class_id_DeferredApiObject 0x8ea933 -#endif /* __nvoc_class_id_DeferredApiObject */ - - - -NV_STATUS Class5080GetDeferredApiInfo( - PDEFERRED_API_OBJECT pDeferredApiObject, - NvHandle hDeferredApi, - PDEFERRED_API_INFO *ppCliDeferredApi -); +} DEFERRED_API_INFO; /*! @@ -123,6 +103,7 @@ struct DeferredApiObject { NV_STATUS (*__defapiUnregisterEvent__)(struct DeferredApiObject *, NvHandle, NvHandle, NvHandle, NvHandle); NvBool (*__defapiCanCopy__)(struct DeferredApiObject *); void (*__defapiPreDestruct__)(struct DeferredApiObject *); + NV_STATUS (*__defapiIsDuplicate__)(struct DeferredApiObject *, NvHandle, NvBool *); PEVENTNOTIFICATION *(*__defapiGetNotificationListPtr__)(struct DeferredApiObject *); struct NotifShare *(*__defapiGetNotificationShare__)(struct DeferredApiObject *); NV_STATUS (*__defapiMap__)(struct DeferredApiObject *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -187,6 +168,7 @@ NV_STATUS __nvoc_objCreate_DeferredApiObject(DeferredApiObject**, Dynamic*, NvU3 #define defapiUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) defapiUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define defapiCanCopy(pResource) defapiCanCopy_DISPATCH(pResource) #define defapiPreDestruct(pResource) defapiPreDestruct_DISPATCH(pResource) +#define defapiIsDuplicate(pResource, hMemory, pDuplicate) defapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define defapiGetNotificationListPtr(pNotifier) defapiGetNotificationListPtr_DISPATCH(pNotifier) #define defapiGetNotificationShare(pNotifier) defapiGetNotificationShare_DISPATCH(pNotifier) #define defapiMap(pGpuResource, pCallContext, pParams, pCpuMapping) defapiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -313,6 +295,10 @@ static inline void defapiPreDestruct_DISPATCH(struct DeferredApiObject *pResourc pResource->__defapiPreDestruct__(pResource); } +static inline NV_STATUS defapiIsDuplicate_DISPATCH(struct DeferredApiObject *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__defapiIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline PEVENTNOTIFICATION *defapiGetNotificationListPtr_DISPATCH(struct DeferredApiObject *pNotifier) { return pNotifier->__defapiGetNotificationListPtr__(pNotifier); } @@ -330,8 +316,10 @@ static inline NV_STATUS defapiGetOrAllocNotifShare_DISPATCH(struct DeferredApiOb } NV_STATUS defapiConstruct_IMPL(struct DeferredApiObject *arg_pDeferredApi, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_defapiConstruct(arg_pDeferredApi, arg_pCallContext, arg_pParams) defapiConstruct_IMPL(arg_pDeferredApi, arg_pCallContext, arg_pParams) void defapiDestruct_IMPL(struct DeferredApiObject *pDeferredApi); + #define __nvoc_defapiDestruct(pDeferredApi) defapiDestruct_IMPL(pDeferredApi) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_device_nvoc.c b/src/nvidia/generated/g_device_nvoc.c index e4f37695b..d775537b1 100644 --- a/src/nvidia/generated/g_device_nvoc.c +++ b/src/nvidia/generated/g_device_nvoc.c @@ -165,6 +165,10 @@ static NV_STATUS __nvoc_thunk_RsResource_deviceUnmapFrom(struct Device *pResourc return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_deviceIsDuplicate(struct Device *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_deviceControl_Epilogue(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RmResource.offset), pCallContext, pParams); } @@ -368,6 +372,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] #endif }, { /* [12] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) deviceCtrlCmdGpuGetSriovCaps_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x800291u, + /*paramSize=*/ sizeof(NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Device.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "deviceCtrlCmdGpuGetSriovCaps" +#endif + }, + { /* [13] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -382,7 +401,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuGetClasslistV2" #endif }, - { /* [13] */ + { /* [14] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -397,7 +416,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuGetFindSubDeviceHandle" #endif }, - { /* [14] */ + { /* [15] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x211u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -412,7 +431,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuGetBrandCaps" #endif }, - { /* [15] */ + { /* [16] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -427,7 +446,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuSetVgpuVfBar1Size" #endif }, - { /* [16] */ + { /* [17] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x812u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -442,7 +461,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdKGrGetCaps" #endif }, - { /* [17] */ + { /* [18] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -457,7 +476,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdKGrGetInfo" #endif }, - { /* [18] */ + { /* [19] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -472,7 +491,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdKGrGetTpcPartitionMode" #endif }, - { /* [19] */ + { /* [20] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -487,7 +506,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdKGrSetTpcPartitionMode" #endif }, - { /* [20] */ + { /* [21] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x812u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -502,7 +521,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdKGrGetCapsV2" #endif }, - { /* [21] */ + { /* [22] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -517,7 +536,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdKGrGetInfoV2" #endif }, - { /* [22] */ + { /* [23] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -532,7 +551,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFbGetCaps" #endif }, - { /* [23] */ + { /* [24] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -547,7 +566,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFbGetCompbitStoreInfo" #endif }, - { /* [24] */ + { /* [25] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -562,7 +581,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFbGetCapsV2" #endif }, - { /* [25] */ + { /* [26] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -577,7 +596,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdHostGetCaps" #endif }, - { /* [26] */ + { /* [27] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -592,7 +611,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdHostGetCapsV2" #endif }, - { /* [27] */ + { /* [28] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -607,7 +626,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoGetCaps" #endif }, - { /* [28] */ + { /* [29] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -622,7 +641,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoStartSelectedChannels" #endif }, - { /* [29] */ + { /* [30] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -637,7 +656,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoGetEngineContextProperties" #endif }, - { /* [30] */ + { /* [31] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -652,7 +671,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoGetChannelList" #endif }, - { /* [31] */ + { /* [32] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2211u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -667,7 +686,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoGetLatencyBufferSize" #endif }, - { /* [32] */ + { /* [33] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -682,7 +701,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoSetChannelProperties" #endif }, - { /* [33] */ + { /* [34] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -697,7 +716,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoStopRunlist" #endif }, - { /* [34] */ + { /* [35] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -712,7 +731,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoStartRunlist" #endif }, - { /* [35] */ + { /* [36] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -727,7 +746,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoGetCapsV2" #endif }, - { /* [36] */ + { /* [37] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -742,7 +761,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoIdleChannels" #endif }, - { /* [37] */ + { /* [38] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -757,7 +776,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaGetPteInfo" #endif }, - { /* [38] */ + { /* [39] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -772,7 +791,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaFlush" #endif }, - { /* [39] */ + { /* [40] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -787,7 +806,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaAdvSchedGetVaCaps" #endif }, - { /* [40] */ + { /* [41] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -802,7 +821,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaGetPdeInfo" #endif }, - { /* [41] */ + { /* [42] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -817,7 +836,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaSetPteInfo" #endif }, - { /* [42] */ + { /* [43] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -832,7 +851,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaInvalidateTLB" #endif }, - { /* [43] */ + { /* [44] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -847,7 +866,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaGetCaps" #endif }, - { /* [44] */ + { /* [45] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -862,7 +881,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaSetVASpaceSize" #endif }, - { /* [45] */ + { /* [46] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -877,7 +896,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaUpdatePde2" #endif }, - { /* [46] */ + { /* [47] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -892,13 +911,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaEnablePrivilegedRange" #endif }, - { /* [47] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + { /* [48] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c0000u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) deviceCtrlCmdDmaSetDefaultVASpace_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) - /*flags=*/ 0x0u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c0000u) + /*flags=*/ 0x1c0000u, /*accessRight=*/0x0u, /*methodId=*/ 0x801812u, /*paramSize=*/ sizeof(NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS), @@ -907,13 +926,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaSetDefaultVASpace" #endif }, - { /* [48] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + { /* [49] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) deviceCtrlCmdDmaSetPageDirectory_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) - /*flags=*/ 0x4u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) + /*flags=*/ 0x140004u, /*accessRight=*/0x0u, /*methodId=*/ 0x801813u, /*paramSize=*/ sizeof(NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS), @@ -922,13 +941,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaSetPageDirectory" #endif }, - { /* [49] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + { /* [50] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) deviceCtrlCmdDmaUnsetPageDirectory_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) - /*flags=*/ 0x4u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) + /*flags=*/ 0x140004u, /*accessRight=*/0x0u, /*methodId=*/ 0x801814u, /*paramSize=*/ sizeof(NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS), @@ -937,7 +956,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaUnsetPageDirectory" #endif }, - { /* [50] */ + { /* [51] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -952,7 +971,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdMsencGetCaps" #endif }, - { /* [51] */ + { /* [52] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -967,7 +986,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdBspGetCapsV2" #endif }, - { /* [52] */ + { /* [53] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -982,7 +1001,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdOsUnixVTSwitch" #endif }, - { /* [53] */ + { /* [54] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -997,7 +1016,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdOsUnixVTGetFBInfo" #endif }, - { /* [54] */ + { /* [55] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1012,7 +1031,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdNvjpgGetCapsV2" #endif }, - { /* [55] */ + { /* [56] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1027,7 +1046,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdInternalPerfCudaLimitDisable" #endif }, - { /* [56] */ + { /* [57] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1042,7 +1061,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdInternalPerfGetUnderpoweredGpuCount" #endif }, - { /* [57] */ + { /* [58] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1062,7 +1081,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] const struct NVOC_EXPORT_INFO __nvoc_export_info_Device = { - /*numEntries=*/ 58, + /*numEntries=*/ 59, /*pExportEntries=*/ __nvoc_exported_method_def_Device }; @@ -1127,11 +1146,11 @@ static void __nvoc_init_funcTable_Device_1(Device *pThis) { pThis->__deviceCtrlCmdDmaUpdatePde2__ = &deviceCtrlCmdDmaUpdatePde2_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) pThis->__deviceCtrlCmdDmaSetPageDirectory__ = &deviceCtrlCmdDmaSetPageDirectory_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) pThis->__deviceCtrlCmdDmaUnsetPageDirectory__ = &deviceCtrlCmdDmaUnsetPageDirectory_IMPL; #endif @@ -1167,7 +1186,7 @@ static void __nvoc_init_funcTable_Device_1(Device *pThis) { pThis->__deviceCtrlCmdDmaEnablePrivilegedRange__ = &deviceCtrlCmdDmaEnablePrivilegedRange_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c0000u) pThis->__deviceCtrlCmdDmaSetDefaultVASpace__ = &deviceCtrlCmdDmaSetDefaultVASpace_IMPL; #endif @@ -1311,6 +1330,10 @@ static void __nvoc_init_funcTable_Device_1(Device *pThis) { pThis->__deviceCtrlCmdGpuGetBrandCaps__ = &deviceCtrlCmdGpuGetBrandCaps_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__deviceCtrlCmdGpuGetSriovCaps__ = &deviceCtrlCmdGpuGetSriovCaps_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) pThis->__deviceCtrlCmdGpuGetFindSubDeviceHandle__ = &deviceCtrlCmdGpuGetFindSubDeviceHandle_IMPL; #endif @@ -1371,6 +1394,8 @@ static void __nvoc_init_funcTable_Device_1(Device *pThis) { pThis->__deviceUnmapFrom__ = &__nvoc_thunk_RsResource_deviceUnmapFrom; + pThis->__deviceIsDuplicate__ = &__nvoc_thunk_RsResource_deviceIsDuplicate; + pThis->__deviceControl_Epilogue__ = &__nvoc_thunk_RmResource_deviceControl_Epilogue; pThis->__deviceControlLookup__ = &__nvoc_thunk_RsResource_deviceControlLookup; diff --git a/src/nvidia/generated/g_device_nvoc.h b/src/nvidia/generated/g_device_nvoc.h index a1e0f4921..f0e45c9b1 100644 --- a/src/nvidia/generated/g_device_nvoc.h +++ b/src/nvidia/generated/g_device_nvoc.h @@ -48,7 +48,7 @@ extern "C" { #include "ctrl/ctrl0080.h" // rmcontrol params // Forward declaration -struct HOST_VGPU_DEVICE; +struct KERNEL_HOST_VGPU_DEVICE; struct OBJVASPACE; #ifndef __NVOC_CLASS_OBJVASPACE_TYPEDEF__ @@ -62,9 +62,6 @@ typedef struct OBJVASPACE OBJVASPACE; -// TODO: Remove this after adding KERNEL_HOST_VGPU_DEVICE -typedef struct HOST_VGPU_DEVICE KERNEL_HOST_VGPU_DEVICE; - /** * A device consists of one or more GPUs. Devices provide broadcast * semantics; that is, operations involving a device are applied to all GPUs @@ -138,6 +135,7 @@ struct Device { NV_STATUS (*__deviceCtrlCmdGpuSetSparseTextureComputeMode__)(struct Device *, NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS *); NV_STATUS (*__deviceCtrlCmdGpuGetVgxCaps__)(struct Device *, NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS *); NV_STATUS (*__deviceCtrlCmdGpuGetBrandCaps__)(struct Device *, NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS *); + NV_STATUS (*__deviceCtrlCmdGpuGetSriovCaps__)(struct Device *, NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS *); NV_STATUS (*__deviceCtrlCmdGpuGetFindSubDeviceHandle__)(struct Device *, NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM *); NV_STATUS (*__deviceCtrlCmdMsencGetCaps__)(struct Device *, NV0080_CTRL_MSENC_GET_CAPS_PARAMS *); NV_STATUS (*__deviceCtrlCmdBspGetCapsV2__)(struct Device *, NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2 *); @@ -160,6 +158,7 @@ struct Device { NvBool (*__deviceCanCopy__)(struct Device *); void (*__devicePreDestruct__)(struct Device *); NV_STATUS (*__deviceUnmapFrom__)(struct Device *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__deviceIsDuplicate__)(struct Device *, NvHandle, NvBool *); void (*__deviceControl_Epilogue__)(struct Device *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__deviceControlLookup__)(struct Device *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__deviceMap__)(struct Device *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -181,8 +180,7 @@ struct Device { NvU64 vaLimitInternal; NvU64 vaSize; NvU32 vaMode; - struct HOST_VGPU_DEVICE *pHostVgpuDevice; - KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice; + struct KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice; }; #ifndef __NVOC_CLASS_Device_TYPEDEF__ @@ -267,6 +265,7 @@ NV_STATUS __nvoc_objCreate_Device(Device**, Dynamic*, NvU32, struct CALL_CONTEXT #define deviceCtrlCmdGpuSetSparseTextureComputeMode(pDevice, pModeParams) deviceCtrlCmdGpuSetSparseTextureComputeMode_DISPATCH(pDevice, pModeParams) #define deviceCtrlCmdGpuGetVgxCaps(pDevice, pParams) deviceCtrlCmdGpuGetVgxCaps_DISPATCH(pDevice, pParams) #define deviceCtrlCmdGpuGetBrandCaps(pDevice, pParams) deviceCtrlCmdGpuGetBrandCaps_DISPATCH(pDevice, pParams) +#define deviceCtrlCmdGpuGetSriovCaps(pDevice, pParams) deviceCtrlCmdGpuGetSriovCaps_DISPATCH(pDevice, pParams) #define deviceCtrlCmdGpuGetFindSubDeviceHandle(pDevice, pParams) deviceCtrlCmdGpuGetFindSubDeviceHandle_DISPATCH(pDevice, pParams) #define deviceCtrlCmdMsencGetCaps(pDevice, pMsencCapsParams) deviceCtrlCmdMsencGetCaps_DISPATCH(pDevice, pMsencCapsParams) #define deviceCtrlCmdBspGetCapsV2(pDevice, pBspCapParams) deviceCtrlCmdBspGetCapsV2_DISPATCH(pDevice, pBspCapParams) @@ -289,6 +288,7 @@ NV_STATUS __nvoc_objCreate_Device(Device**, Dynamic*, NvU32, struct CALL_CONTEXT #define deviceCanCopy(pResource) deviceCanCopy_DISPATCH(pResource) #define devicePreDestruct(pResource) devicePreDestruct_DISPATCH(pResource) #define deviceUnmapFrom(pResource, pParams) deviceUnmapFrom_DISPATCH(pResource, pParams) +#define deviceIsDuplicate(pResource, hMemory, pDuplicate) deviceIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define deviceControl_Epilogue(pResource, pCallContext, pParams) deviceControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define deviceControlLookup(pResource, pParams, ppEntry) deviceControlLookup_DISPATCH(pResource, pParams, ppEntry) #define deviceMap(pGpuResource, pCallContext, pParams, pCpuMapping) deviceMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -617,6 +617,12 @@ static inline NV_STATUS deviceCtrlCmdGpuGetBrandCaps_DISPATCH(struct Device *pDe return pDevice->__deviceCtrlCmdGpuGetBrandCaps__(pDevice, pParams); } +NV_STATUS deviceCtrlCmdGpuGetSriovCaps_IMPL(struct Device *pDevice, NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS *pParams); + +static inline NV_STATUS deviceCtrlCmdGpuGetSriovCaps_DISPATCH(struct Device *pDevice, NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS *pParams) { + return pDevice->__deviceCtrlCmdGpuGetSriovCaps__(pDevice, pParams); +} + NV_STATUS deviceCtrlCmdGpuGetFindSubDeviceHandle_IMPL(struct Device *pDevice, NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM *pParams); static inline NV_STATUS deviceCtrlCmdGpuGetFindSubDeviceHandle_DISPATCH(struct Device *pDevice, NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM *pParams) { @@ -717,6 +723,10 @@ static inline NV_STATUS deviceUnmapFrom_DISPATCH(struct Device *pResource, RS_RE return pResource->__deviceUnmapFrom__(pResource, pParams); } +static inline NV_STATUS deviceIsDuplicate_DISPATCH(struct Device *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__deviceIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void deviceControl_Epilogue_DISPATCH(struct Device *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__deviceControl_Epilogue__(pResource, pCallContext, pParams); } @@ -734,10 +744,13 @@ static inline NvBool deviceAccessCallback_DISPATCH(struct Device *pResource, str } NV_STATUS deviceConstruct_IMPL(struct Device *arg_pResource, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_deviceConstruct(arg_pResource, arg_pCallContext, arg_pParams) deviceConstruct_IMPL(arg_pResource, arg_pCallContext, arg_pParams) void deviceDestruct_IMPL(struct Device *pResource); + #define __nvoc_deviceDestruct(pResource) deviceDestruct_IMPL(pResource) NV_STATUS deviceInit_IMPL(struct Device *pDevice, struct CALL_CONTEXT *pCallContext, NvHandle hClient, NvHandle hDevice, NvU32 deviceInst, NvHandle hClientShare, NvHandle hTargetClient, NvHandle hTargetDevice, NvU64 vaSize, NvU64 vaStartInternal, NvU64 vaLimitInternal, NvU32 allocFlags, NvU32 vaMode); + #ifdef __nvoc_device_h_disabled static inline NV_STATUS deviceInit(struct Device *pDevice, struct CALL_CONTEXT *pCallContext, NvHandle hClient, NvHandle hDevice, NvU32 deviceInst, NvHandle hClientShare, NvHandle hTargetClient, NvHandle hTargetDevice, NvU64 vaSize, NvU64 vaStartInternal, NvU64 vaLimitInternal, NvU32 allocFlags, NvU32 vaMode) { NV_ASSERT_FAILED_PRECOMP("Device was disabled!"); @@ -748,12 +761,16 @@ static inline NV_STATUS deviceInit(struct Device *pDevice, struct CALL_CONTEXT * #endif //__nvoc_device_h_disabled NV_STATUS deviceGetByHandle_IMPL(struct RsClient *pClient, NvHandle hDevice, struct Device **ppDevice); + #define deviceGetByHandle(pClient, hDevice, ppDevice) deviceGetByHandle_IMPL(pClient, hDevice, ppDevice) NV_STATUS deviceGetByInstance_IMPL(struct RsClient *pClient, NvU32 deviceInstance, struct Device **ppDevice); + #define deviceGetByInstance(pClient, deviceInstance, ppDevice) deviceGetByInstance_IMPL(pClient, deviceInstance, ppDevice) NV_STATUS deviceGetByGpu_IMPL(struct RsClient *pClient, struct OBJGPU *pGpu, NvBool bAnyInGroup, struct Device **ppDevice); + #define deviceGetByGpu(pClient, pGpu, bAnyInGroup, ppDevice) deviceGetByGpu_IMPL(pClient, pGpu, bAnyInGroup, ppDevice) NV_STATUS deviceGetDefaultVASpace_IMPL(struct Device *pDevice, struct OBJVASPACE **ppVAS); + #ifdef __nvoc_device_h_disabled static inline NV_STATUS deviceGetDefaultVASpace(struct Device *pDevice, struct OBJVASPACE **ppVAS) { NV_ASSERT_FAILED_PRECOMP("Device was disabled!"); @@ -764,6 +781,7 @@ static inline NV_STATUS deviceGetDefaultVASpace(struct Device *pDevice, struct O #endif //__nvoc_device_h_disabled NV_STATUS deviceSetClientShare_IMPL(struct Device *pDevice, NvHandle hClientShare, NvU64 vaSize, NvU64 vaStartInternal, NvU64 vaLimitInternal, NvU32 deviceAllocFlags); + #ifdef __nvoc_device_h_disabled static inline NV_STATUS deviceSetClientShare(struct Device *pDevice, NvHandle hClientShare, NvU64 vaSize, NvU64 vaStartInternal, NvU64 vaLimitInternal, NvU32 deviceAllocFlags) { NV_ASSERT_FAILED_PRECOMP("Device was disabled!"); @@ -774,6 +792,7 @@ static inline NV_STATUS deviceSetClientShare(struct Device *pDevice, NvHandle hC #endif //__nvoc_device_h_disabled void deviceRemoveFromClientShare_IMPL(struct Device *pDevice); + #ifdef __nvoc_device_h_disabled static inline void deviceRemoveFromClientShare(struct Device *pDevice) { NV_ASSERT_FAILED_PRECOMP("Device was disabled!"); @@ -783,6 +802,7 @@ static inline void deviceRemoveFromClientShare(struct Device *pDevice) { #endif //__nvoc_device_h_disabled NV_STATUS deviceSetDefaultVASpace_IMPL(struct Device *pDevice, NvHandle hVASpace); + #ifdef __nvoc_device_h_disabled static inline NV_STATUS deviceSetDefaultVASpace(struct Device *pDevice, NvHandle hVASpace) { NV_ASSERT_FAILED_PRECOMP("Device was disabled!"); diff --git a/src/nvidia/generated/g_disp_capabilities_nvoc.c b/src/nvidia/generated/g_disp_capabilities_nvoc.c index 3a417eb7e..1255696f7 100644 --- a/src/nvidia/generated/g_disp_capabilities_nvoc.c +++ b/src/nvidia/generated/g_disp_capabilities_nvoc.c @@ -165,6 +165,10 @@ static NV_STATUS __nvoc_thunk_RsResource_dispcapUnmapFrom(struct DispCapabilitie return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_dispcapIsDuplicate(struct DispCapabilities *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_dispcapControl_Epilogue(struct DispCapabilities *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RmResource.offset), pCallContext, pParams); } @@ -257,6 +261,8 @@ static void __nvoc_init_funcTable_DispCapabilities_1(DispCapabilities *pThis) { pThis->__dispcapUnmapFrom__ = &__nvoc_thunk_RsResource_dispcapUnmapFrom; + pThis->__dispcapIsDuplicate__ = &__nvoc_thunk_RsResource_dispcapIsDuplicate; + pThis->__dispcapControl_Epilogue__ = &__nvoc_thunk_RmResource_dispcapControl_Epilogue; pThis->__dispcapControlLookup__ = &__nvoc_thunk_RsResource_dispcapControlLookup; diff --git a/src/nvidia/generated/g_disp_capabilities_nvoc.h b/src/nvidia/generated/g_disp_capabilities_nvoc.h index 185980a24..a8884e085 100644 --- a/src/nvidia/generated/g_disp_capabilities_nvoc.h +++ b/src/nvidia/generated/g_disp_capabilities_nvoc.h @@ -78,6 +78,7 @@ struct DispCapabilities { NV_STATUS (*__dispcapInternalControlForward__)(struct DispCapabilities *, NvU32, void *, NvU32); void (*__dispcapPreDestruct__)(struct DispCapabilities *); NV_STATUS (*__dispcapUnmapFrom__)(struct DispCapabilities *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__dispcapIsDuplicate__)(struct DispCapabilities *, NvHandle, NvBool *); void (*__dispcapControl_Epilogue__)(struct DispCapabilities *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dispcapControlLookup__)(struct DispCapabilities *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__dispcapMap__)(struct DispCapabilities *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -132,6 +133,7 @@ NV_STATUS __nvoc_objCreate_DispCapabilities(DispCapabilities**, Dynamic*, NvU32, #define dispcapInternalControlForward(pGpuResource, command, pParams, size) dispcapInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define dispcapPreDestruct(pResource) dispcapPreDestruct_DISPATCH(pResource) #define dispcapUnmapFrom(pResource, pParams) dispcapUnmapFrom_DISPATCH(pResource, pParams) +#define dispcapIsDuplicate(pResource, hMemory, pDuplicate) dispcapIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define dispcapControl_Epilogue(pResource, pCallContext, pParams) dispcapControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define dispcapControlLookup(pResource, pParams, ppEntry) dispcapControlLookup_DISPATCH(pResource, pParams, ppEntry) #define dispcapMap(pGpuResource, pCallContext, pParams, pCpuMapping) dispcapMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -210,6 +212,10 @@ static inline NV_STATUS dispcapUnmapFrom_DISPATCH(struct DispCapabilities *pReso return pResource->__dispcapUnmapFrom__(pResource, pParams); } +static inline NV_STATUS dispcapIsDuplicate_DISPATCH(struct DispCapabilities *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__dispcapIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void dispcapControl_Epilogue_DISPATCH(struct DispCapabilities *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__dispcapControl_Epilogue__(pResource, pCallContext, pParams); } @@ -227,6 +233,7 @@ static inline NvBool dispcapAccessCallback_DISPATCH(struct DispCapabilities *pRe } NV_STATUS dispcapConstruct_IMPL(struct DispCapabilities *arg_pDispCapabilities, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_dispcapConstruct(arg_pDispCapabilities, arg_pCallContext, arg_pParams) dispcapConstruct_IMPL(arg_pDispCapabilities, arg_pCallContext, arg_pParams) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_disp_channel_nvoc.c b/src/nvidia/generated/g_disp_channel_nvoc.c index e925b3cc9..edd3ca5d6 100644 --- a/src/nvidia/generated/g_disp_channel_nvoc.c +++ b/src/nvidia/generated/g_disp_channel_nvoc.c @@ -203,6 +203,10 @@ static void __nvoc_thunk_RsResource_dispchnPreDestruct(struct DispChannel *pReso resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannel_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_RsResource_dispchnIsDuplicate(struct DispChannel *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannel_RsResource.offset), hMemory, pDuplicate); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_dispchnGetNotificationListPtr(struct DispChannel *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispChannel_Notifier.offset)); } @@ -313,6 +317,8 @@ static void __nvoc_init_funcTable_DispChannel_1(DispChannel *pThis) { pThis->__dispchnPreDestruct__ = &__nvoc_thunk_RsResource_dispchnPreDestruct; + pThis->__dispchnIsDuplicate__ = &__nvoc_thunk_RsResource_dispchnIsDuplicate; + pThis->__dispchnGetNotificationListPtr__ = &__nvoc_thunk_Notifier_dispchnGetNotificationListPtr; pThis->__dispchnGetNotificationShare__ = &__nvoc_thunk_Notifier_dispchnGetNotificationShare; @@ -593,6 +599,10 @@ static void __nvoc_thunk_RsResource_dispchnpioPreDestruct(struct DispChannelPio resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelPio_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_RsResource_dispchnpioIsDuplicate(struct DispChannelPio *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelPio_RsResource.offset), hMemory, pDuplicate); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_dispchnpioGetNotificationListPtr(struct DispChannelPio *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispChannelPio_Notifier.offset)); } @@ -693,6 +703,8 @@ static void __nvoc_init_funcTable_DispChannelPio_1(DispChannelPio *pThis) { pThis->__dispchnpioPreDestruct__ = &__nvoc_thunk_RsResource_dispchnpioPreDestruct; + pThis->__dispchnpioIsDuplicate__ = &__nvoc_thunk_RsResource_dispchnpioIsDuplicate; + pThis->__dispchnpioGetNotificationListPtr__ = &__nvoc_thunk_Notifier_dispchnpioGetNotificationListPtr; pThis->__dispchnpioGetNotificationShare__ = &__nvoc_thunk_Notifier_dispchnpioGetNotificationShare; @@ -971,6 +983,10 @@ static void __nvoc_thunk_RsResource_dispchndmaPreDestruct(struct DispChannelDma resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelDma_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_RsResource_dispchndmaIsDuplicate(struct DispChannelDma *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelDma_RsResource.offset), hMemory, pDuplicate); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_dispchndmaGetNotificationListPtr(struct DispChannelDma *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispChannelDma_Notifier.offset)); } @@ -1071,6 +1087,8 @@ static void __nvoc_init_funcTable_DispChannelDma_1(DispChannelDma *pThis) { pThis->__dispchndmaPreDestruct__ = &__nvoc_thunk_RsResource_dispchndmaPreDestruct; + pThis->__dispchndmaIsDuplicate__ = &__nvoc_thunk_RsResource_dispchndmaIsDuplicate; + pThis->__dispchndmaGetNotificationListPtr__ = &__nvoc_thunk_Notifier_dispchndmaGetNotificationListPtr; pThis->__dispchndmaGetNotificationShare__ = &__nvoc_thunk_Notifier_dispchndmaGetNotificationShare; diff --git a/src/nvidia/generated/g_disp_channel_nvoc.h b/src/nvidia/generated/g_disp_channel_nvoc.h index 6b9091cf0..5d2a21800 100644 --- a/src/nvidia/generated/g_disp_channel_nvoc.h +++ b/src/nvidia/generated/g_disp_channel_nvoc.h @@ -112,6 +112,7 @@ struct DispChannel { NV_STATUS (*__dispchnUnregisterEvent__)(struct DispChannel *, NvHandle, NvHandle, NvHandle, NvHandle); NvBool (*__dispchnCanCopy__)(struct DispChannel *); void (*__dispchnPreDestruct__)(struct DispChannel *); + NV_STATUS (*__dispchnIsDuplicate__)(struct DispChannel *, NvHandle, NvBool *); PEVENTNOTIFICATION *(*__dispchnGetNotificationListPtr__)(struct DispChannel *); struct NotifShare *(*__dispchnGetNotificationShare__)(struct DispChannel *); NV_STATUS (*__dispchnMap__)(struct DispChannel *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -177,6 +178,7 @@ NV_STATUS __nvoc_objCreate_DispChannel(DispChannel**, Dynamic*, NvU32, struct CA #define dispchnUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) dispchnUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define dispchnCanCopy(pResource) dispchnCanCopy_DISPATCH(pResource) #define dispchnPreDestruct(pResource) dispchnPreDestruct_DISPATCH(pResource) +#define dispchnIsDuplicate(pResource, hMemory, pDuplicate) dispchnIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define dispchnGetNotificationListPtr(pNotifier) dispchnGetNotificationListPtr_DISPATCH(pNotifier) #define dispchnGetNotificationShare(pNotifier) dispchnGetNotificationShare_DISPATCH(pNotifier) #define dispchnMap(pGpuResource, pCallContext, pParams, pCpuMapping) dispchnMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -275,6 +277,10 @@ static inline void dispchnPreDestruct_DISPATCH(struct DispChannel *pResource) { pResource->__dispchnPreDestruct__(pResource); } +static inline NV_STATUS dispchnIsDuplicate_DISPATCH(struct DispChannel *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__dispchnIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline PEVENTNOTIFICATION *dispchnGetNotificationListPtr_DISPATCH(struct DispChannel *pNotifier) { return pNotifier->__dispchnGetNotificationListPtr__(pNotifier); } @@ -292,10 +298,13 @@ static inline NvBool dispchnAccessCallback_DISPATCH(struct DispChannel *pResourc } NV_STATUS dispchnConstruct_IMPL(struct DispChannel *arg_pDispChannel, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams, NvU32 arg_isDma); + #define __nvoc_dispchnConstruct(arg_pDispChannel, arg_pCallContext, arg_pParams, arg_isDma) dispchnConstruct_IMPL(arg_pDispChannel, arg_pCallContext, arg_pParams, arg_isDma) void dispchnDestruct_IMPL(struct DispChannel *pDispChannel); + #define __nvoc_dispchnDestruct(pDispChannel) dispchnDestruct_IMPL(pDispChannel) void dispchnSetRegBaseOffsetAndSize_IMPL(struct DispChannel *pDispChannel, struct OBJGPU *pGpu); + #ifdef __nvoc_disp_channel_h_disabled static inline void dispchnSetRegBaseOffsetAndSize(struct DispChannel *pDispChannel, struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("DispChannel was disabled!"); @@ -305,6 +314,7 @@ static inline void dispchnSetRegBaseOffsetAndSize(struct DispChannel *pDispChann #endif //__nvoc_disp_channel_h_disabled NV_STATUS dispchnGrabChannel_IMPL(struct DispChannel *pDispChannel, NvHandle hClient, NvHandle hParent, NvHandle hChannel, NvU32 hClass, void *pAllocParms); + #ifdef __nvoc_disp_channel_h_disabled static inline NV_STATUS dispchnGrabChannel(struct DispChannel *pDispChannel, NvHandle hClient, NvHandle hParent, NvHandle hChannel, NvU32 hClass, void *pAllocParms) { NV_ASSERT_FAILED_PRECOMP("DispChannel was disabled!"); @@ -315,12 +325,16 @@ static inline NV_STATUS dispchnGrabChannel(struct DispChannel *pDispChannel, NvH #endif //__nvoc_disp_channel_h_disabled NV_STATUS dispchnBindCtx_IMPL(struct OBJGPU *pGpu, struct ContextDma *pContextDma, NvHandle hDispChannel); + #define dispchnBindCtx(pGpu, pContextDma, hDispChannel) dispchnBindCtx_IMPL(pGpu, pContextDma, hDispChannel) NV_STATUS dispchnUnbindCtx_IMPL(struct OBJGPU *pGpu, struct ContextDma *pContextDma, NvHandle hDispChannel); + #define dispchnUnbindCtx(pGpu, pContextDma, hDispChannel) dispchnUnbindCtx_IMPL(pGpu, pContextDma, hDispChannel) void dispchnUnbindCtxFromAllChannels_IMPL(struct OBJGPU *pGpu, struct ContextDma *pContextDma); + #define dispchnUnbindCtxFromAllChannels(pGpu, pContextDma) dispchnUnbindCtxFromAllChannels_IMPL(pGpu, pContextDma) void dispchnUnbindAllCtx_IMPL(struct OBJGPU *pGpu, struct DispChannel *pDispChannel); + #ifdef __nvoc_disp_channel_h_disabled static inline void dispchnUnbindAllCtx(struct OBJGPU *pGpu, struct DispChannel *pDispChannel) { NV_ASSERT_FAILED_PRECOMP("DispChannel was disabled!"); @@ -330,6 +344,7 @@ static inline void dispchnUnbindAllCtx(struct OBJGPU *pGpu, struct DispChannel * #endif //__nvoc_disp_channel_h_disabled NV_STATUS dispchnGetByHandle_IMPL(struct RsClient *pClient, NvHandle hDisplayChannel, struct DispChannel **ppDispChannel); + #define dispchnGetByHandle(pClient, hDisplayChannel, ppDispChannel) dispchnGetByHandle_IMPL(pClient, hDisplayChannel, ppDispChannel) #undef PRIVATE_FIELD @@ -377,6 +392,7 @@ struct DispChannelPio { NV_STATUS (*__dispchnpioUnregisterEvent__)(struct DispChannelPio *, NvHandle, NvHandle, NvHandle, NvHandle); NvBool (*__dispchnpioCanCopy__)(struct DispChannelPio *); void (*__dispchnpioPreDestruct__)(struct DispChannelPio *); + NV_STATUS (*__dispchnpioIsDuplicate__)(struct DispChannelPio *, NvHandle, NvBool *); PEVENTNOTIFICATION *(*__dispchnpioGetNotificationListPtr__)(struct DispChannelPio *); struct NotifShare *(*__dispchnpioGetNotificationShare__)(struct DispChannelPio *); NV_STATUS (*__dispchnpioMap__)(struct DispChannelPio *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -434,6 +450,7 @@ NV_STATUS __nvoc_objCreate_DispChannelPio(DispChannelPio**, Dynamic*, NvU32, str #define dispchnpioUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) dispchnpioUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define dispchnpioCanCopy(pResource) dispchnpioCanCopy_DISPATCH(pResource) #define dispchnpioPreDestruct(pResource) dispchnpioPreDestruct_DISPATCH(pResource) +#define dispchnpioIsDuplicate(pResource, hMemory, pDuplicate) dispchnpioIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define dispchnpioGetNotificationListPtr(pNotifier) dispchnpioGetNotificationListPtr_DISPATCH(pNotifier) #define dispchnpioGetNotificationShare(pNotifier) dispchnpioGetNotificationShare_DISPATCH(pNotifier) #define dispchnpioMap(pGpuResource, pCallContext, pParams, pCpuMapping) dispchnpioMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -530,6 +547,10 @@ static inline void dispchnpioPreDestruct_DISPATCH(struct DispChannelPio *pResour pResource->__dispchnpioPreDestruct__(pResource); } +static inline NV_STATUS dispchnpioIsDuplicate_DISPATCH(struct DispChannelPio *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__dispchnpioIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline PEVENTNOTIFICATION *dispchnpioGetNotificationListPtr_DISPATCH(struct DispChannelPio *pNotifier) { return pNotifier->__dispchnpioGetNotificationListPtr__(pNotifier); } @@ -547,6 +568,7 @@ static inline NvBool dispchnpioAccessCallback_DISPATCH(struct DispChannelPio *pR } NV_STATUS dispchnpioConstruct_IMPL(struct DispChannelPio *arg_pDispChannelPio, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_dispchnpioConstruct(arg_pDispChannelPio, arg_pCallContext, arg_pParams) dispchnpioConstruct_IMPL(arg_pDispChannelPio, arg_pCallContext, arg_pParams) #undef PRIVATE_FIELD @@ -594,6 +616,7 @@ struct DispChannelDma { NV_STATUS (*__dispchndmaUnregisterEvent__)(struct DispChannelDma *, NvHandle, NvHandle, NvHandle, NvHandle); NvBool (*__dispchndmaCanCopy__)(struct DispChannelDma *); void (*__dispchndmaPreDestruct__)(struct DispChannelDma *); + NV_STATUS (*__dispchndmaIsDuplicate__)(struct DispChannelDma *, NvHandle, NvBool *); PEVENTNOTIFICATION *(*__dispchndmaGetNotificationListPtr__)(struct DispChannelDma *); struct NotifShare *(*__dispchndmaGetNotificationShare__)(struct DispChannelDma *); NV_STATUS (*__dispchndmaMap__)(struct DispChannelDma *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -651,6 +674,7 @@ NV_STATUS __nvoc_objCreate_DispChannelDma(DispChannelDma**, Dynamic*, NvU32, str #define dispchndmaUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) dispchndmaUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define dispchndmaCanCopy(pResource) dispchndmaCanCopy_DISPATCH(pResource) #define dispchndmaPreDestruct(pResource) dispchndmaPreDestruct_DISPATCH(pResource) +#define dispchndmaIsDuplicate(pResource, hMemory, pDuplicate) dispchndmaIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define dispchndmaGetNotificationListPtr(pNotifier) dispchndmaGetNotificationListPtr_DISPATCH(pNotifier) #define dispchndmaGetNotificationShare(pNotifier) dispchndmaGetNotificationShare_DISPATCH(pNotifier) #define dispchndmaMap(pGpuResource, pCallContext, pParams, pCpuMapping) dispchndmaMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -747,6 +771,10 @@ static inline void dispchndmaPreDestruct_DISPATCH(struct DispChannelDma *pResour pResource->__dispchndmaPreDestruct__(pResource); } +static inline NV_STATUS dispchndmaIsDuplicate_DISPATCH(struct DispChannelDma *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__dispchndmaIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline PEVENTNOTIFICATION *dispchndmaGetNotificationListPtr_DISPATCH(struct DispChannelDma *pNotifier) { return pNotifier->__dispchndmaGetNotificationListPtr__(pNotifier); } @@ -764,6 +792,7 @@ static inline NvBool dispchndmaAccessCallback_DISPATCH(struct DispChannelDma *pR } NV_STATUS dispchndmaConstruct_IMPL(struct DispChannelDma *arg_pDispChannelDma, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_dispchndmaConstruct(arg_pDispChannelDma, arg_pCallContext, arg_pParams) dispchndmaConstruct_IMPL(arg_pDispChannelDma, arg_pCallContext, arg_pParams) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_disp_inst_mem_nvoc.c b/src/nvidia/generated/g_disp_inst_mem_nvoc.c index d884a48e2..32deea27e 100644 --- a/src/nvidia/generated/g_disp_inst_mem_nvoc.c +++ b/src/nvidia/generated/g_disp_inst_mem_nvoc.c @@ -107,10 +107,7 @@ static void __nvoc_init_funcTable_DisplayInstanceMemory_1(DisplayInstanceMemory PORT_UNREFERENCED_VARIABLE(dispIpHal_HalVarIdx); // Hal function -- instmemGetSize - if (0) - { - } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ { pThis->__instmemGetSize__ = &instmemGetSize_v03_00; } @@ -120,10 +117,7 @@ static void __nvoc_init_funcTable_DisplayInstanceMemory_1(DisplayInstanceMemory } // Hal function -- instmemGetHashTableBaseAddr - if (0) - { - } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ { pThis->__instmemGetHashTableBaseAddr__ = &instmemGetHashTableBaseAddr_v03_00; } @@ -133,10 +127,7 @@ static void __nvoc_init_funcTable_DisplayInstanceMemory_1(DisplayInstanceMemory } // Hal function -- instmemIsValid - if (0) - { - } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ { pThis->__instmemIsValid__ = &instmemIsValid_v03_00; } @@ -146,10 +137,7 @@ static void __nvoc_init_funcTable_DisplayInstanceMemory_1(DisplayInstanceMemory } // Hal function -- instmemGenerateHashTableData - if (0) - { - } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ { pThis->__instmemGenerateHashTableData__ = &instmemGenerateHashTableData_v03_00; } @@ -159,10 +147,7 @@ static void __nvoc_init_funcTable_DisplayInstanceMemory_1(DisplayInstanceMemory } // Hal function -- instmemHashFunc - if (0) - { - } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ { pThis->__instmemHashFunc__ = &instmemHashFunc_v03_00; } @@ -172,10 +157,7 @@ static void __nvoc_init_funcTable_DisplayInstanceMemory_1(DisplayInstanceMemory } // Hal function -- instmemCommitContextDma - if (0) - { - } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ { pThis->__instmemCommitContextDma__ = &instmemCommitContextDma_v03_00; } @@ -185,10 +167,7 @@ static void __nvoc_init_funcTable_DisplayInstanceMemory_1(DisplayInstanceMemory } // Hal function -- instmemUpdateContextDma - if (0) - { - } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ { pThis->__instmemUpdateContextDma__ = &instmemUpdateContextDma_v03_00; } diff --git a/src/nvidia/generated/g_disp_inst_mem_nvoc.h b/src/nvidia/generated/g_disp_inst_mem_nvoc.h index 6ca7157e1..7cf0e2d94 100644 --- a/src/nvidia/generated/g_disp_inst_mem_nvoc.h +++ b/src/nvidia/generated/g_disp_inst_mem_nvoc.h @@ -158,6 +158,7 @@ static inline void instmemDecommitContextDma_b3696a(OBJGPU *pGpu, struct Display return; } + #ifdef __nvoc_disp_inst_mem_h_disabled static inline void instmemDecommitContextDma(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, struct ContextDma *pContextDma) { NV_ASSERT_FAILED_PRECOMP("DisplayInstanceMemory was disabled!"); @@ -239,10 +240,13 @@ static inline NV_STATUS instmemUpdateContextDma_DISPATCH(OBJGPU *pGpu, struct Di } NV_STATUS instmemConstruct_IMPL(struct DisplayInstanceMemory *arg_pInstMem); + #define __nvoc_instmemConstruct(arg_pInstMem) instmemConstruct_IMPL(arg_pInstMem) void instmemDestruct_IMPL(struct DisplayInstanceMemory *pInstMem); + #define __nvoc_instmemDestruct(pInstMem) instmemDestruct_IMPL(pInstMem) NV_STATUS instmemStateInitLocked_IMPL(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem); + #ifdef __nvoc_disp_inst_mem_h_disabled static inline NV_STATUS instmemStateInitLocked(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem) { NV_ASSERT_FAILED_PRECOMP("DisplayInstanceMemory was disabled!"); @@ -253,6 +257,7 @@ static inline NV_STATUS instmemStateInitLocked(OBJGPU *pGpu, struct DisplayInsta #endif //__nvoc_disp_inst_mem_h_disabled void instmemStateDestroy_IMPL(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem); + #ifdef __nvoc_disp_inst_mem_h_disabled static inline void instmemStateDestroy(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem) { NV_ASSERT_FAILED_PRECOMP("DisplayInstanceMemory was disabled!"); @@ -262,6 +267,7 @@ static inline void instmemStateDestroy(OBJGPU *pGpu, struct DisplayInstanceMemor #endif //__nvoc_disp_inst_mem_h_disabled NV_STATUS instmemStateLoad_IMPL(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 flags); + #ifdef __nvoc_disp_inst_mem_h_disabled static inline NV_STATUS instmemStateLoad(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 flags) { NV_ASSERT_FAILED_PRECOMP("DisplayInstanceMemory was disabled!"); @@ -272,6 +278,7 @@ static inline NV_STATUS instmemStateLoad(OBJGPU *pGpu, struct DisplayInstanceMem #endif //__nvoc_disp_inst_mem_h_disabled NV_STATUS instmemStateUnload_IMPL(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 flags); + #ifdef __nvoc_disp_inst_mem_h_disabled static inline NV_STATUS instmemStateUnload(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 flags) { NV_ASSERT_FAILED_PRECOMP("DisplayInstanceMemory was disabled!"); @@ -282,6 +289,7 @@ static inline NV_STATUS instmemStateUnload(OBJGPU *pGpu, struct DisplayInstanceM #endif //__nvoc_disp_inst_mem_h_disabled void instmemSetMemory_IMPL(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NV_ADDRESS_SPACE dispInstMemAddrSpace, NvU32 dispInstMemAttr, NvU64 dispInstMemBase, NvU32 dispInstMemSize); + #ifdef __nvoc_disp_inst_mem_h_disabled static inline void instmemSetMemory(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NV_ADDRESS_SPACE dispInstMemAddrSpace, NvU32 dispInstMemAttr, NvU64 dispInstMemBase, NvU32 dispInstMemSize) { NV_ASSERT_FAILED_PRECOMP("DisplayInstanceMemory was disabled!"); @@ -291,6 +299,7 @@ static inline void instmemSetMemory(OBJGPU *pGpu, struct DisplayInstanceMemory * #endif //__nvoc_disp_inst_mem_h_disabled NV_STATUS instmemBindContextDma_IMPL(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, struct ContextDma *pContextDma, struct DispChannel *pDispChannel); + #ifdef __nvoc_disp_inst_mem_h_disabled static inline NV_STATUS instmemBindContextDma(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, struct ContextDma *pContextDma, struct DispChannel *pDispChannel) { NV_ASSERT_FAILED_PRECOMP("DisplayInstanceMemory was disabled!"); @@ -301,6 +310,7 @@ static inline NV_STATUS instmemBindContextDma(OBJGPU *pGpu, struct DisplayInstan #endif //__nvoc_disp_inst_mem_h_disabled NV_STATUS instmemUnbindContextDma_IMPL(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, struct ContextDma *pContextDma, struct DispChannel *pDispChannel); + #ifdef __nvoc_disp_inst_mem_h_disabled static inline NV_STATUS instmemUnbindContextDma(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, struct ContextDma *pContextDma, struct DispChannel *pDispChannel) { NV_ASSERT_FAILED_PRECOMP("DisplayInstanceMemory was disabled!"); @@ -311,6 +321,7 @@ static inline NV_STATUS instmemUnbindContextDma(OBJGPU *pGpu, struct DisplayInst #endif //__nvoc_disp_inst_mem_h_disabled void instmemUnbindContextDmaFromAllChannels_IMPL(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, struct ContextDma *pContextDma); + #ifdef __nvoc_disp_inst_mem_h_disabled static inline void instmemUnbindContextDmaFromAllChannels(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, struct ContextDma *pContextDma) { NV_ASSERT_FAILED_PRECOMP("DisplayInstanceMemory was disabled!"); @@ -320,6 +331,7 @@ static inline void instmemUnbindContextDmaFromAllChannels(OBJGPU *pGpu, struct D #endif //__nvoc_disp_inst_mem_h_disabled void instmemUnbindDispChannelContextDmas_IMPL(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, struct DispChannel *pDispChannel); + #ifdef __nvoc_disp_inst_mem_h_disabled static inline void instmemUnbindDispChannelContextDmas(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, struct DispChannel *pDispChannel) { NV_ASSERT_FAILED_PRECOMP("DisplayInstanceMemory was disabled!"); @@ -329,6 +341,7 @@ static inline void instmemUnbindDispChannelContextDmas(OBJGPU *pGpu, struct Disp #endif //__nvoc_disp_inst_mem_h_disabled NV_STATUS instmemReserveContextDma_IMPL(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 *offset); + #ifdef __nvoc_disp_inst_mem_h_disabled static inline NV_STATUS instmemReserveContextDma(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 *offset) { NV_ASSERT_FAILED_PRECOMP("DisplayInstanceMemory was disabled!"); @@ -339,6 +352,7 @@ static inline NV_STATUS instmemReserveContextDma(OBJGPU *pGpu, struct DisplayIns #endif //__nvoc_disp_inst_mem_h_disabled NV_STATUS instmemFreeContextDma_IMPL(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 offset); + #ifdef __nvoc_disp_inst_mem_h_disabled static inline NV_STATUS instmemFreeContextDma(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 offset) { NV_ASSERT_FAILED_PRECOMP("DisplayInstanceMemory was disabled!"); diff --git a/src/nvidia/generated/g_disp_objs_nvoc.c b/src/nvidia/generated/g_disp_objs_nvoc.c index 015935023..6accf17ec 100644 --- a/src/nvidia/generated/g_disp_objs_nvoc.c +++ b/src/nvidia/generated/g_disp_objs_nvoc.c @@ -174,6 +174,10 @@ static NV_STATUS __nvoc_thunk_RsResource_dispapiUnmapFrom(struct DisplayApi *pRe return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_dispapiIsDuplicate(struct DisplayApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset), hMemory, pDuplicate); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_dispapiGetNotificationListPtr(struct DisplayApi *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DisplayApi_Notifier.offset)); } @@ -292,6 +296,8 @@ static void __nvoc_init_funcTable_DisplayApi_1(DisplayApi *pThis, RmHalspecOwner pThis->__dispapiUnmapFrom__ = &__nvoc_thunk_RsResource_dispapiUnmapFrom; + pThis->__dispapiIsDuplicate__ = &__nvoc_thunk_RsResource_dispapiIsDuplicate; + pThis->__dispapiGetNotificationListPtr__ = &__nvoc_thunk_Notifier_dispapiGetNotificationListPtr; pThis->__dispapiGetNotificationShare__ = &__nvoc_thunk_Notifier_dispapiGetNotificationShare; @@ -544,6 +550,10 @@ static NV_STATUS __nvoc_thunk_RsResource_dispobjUnmapFrom(struct DispObject *pRe return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_dispobjIsDuplicate(struct DispObject *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset), hMemory, pDuplicate); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_dispobjGetNotificationListPtr(struct DispObject *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispObject_Notifier.offset)); } @@ -1229,6 +1239,8 @@ static void __nvoc_init_funcTable_DispObject_1(DispObject *pThis, RmHalspecOwner pThis->__dispobjUnmapFrom__ = &__nvoc_thunk_RsResource_dispobjUnmapFrom; + pThis->__dispobjIsDuplicate__ = &__nvoc_thunk_RsResource_dispobjIsDuplicate; + pThis->__dispobjGetNotificationListPtr__ = &__nvoc_thunk_Notifier_dispobjGetNotificationListPtr; pThis->__dispobjControl_Epilogue__ = &__nvoc_thunk_DisplayApi_dispobjControl_Epilogue; @@ -1491,6 +1503,10 @@ static NV_STATUS __nvoc_thunk_RsResource_nvdispapiUnmapFrom(struct NvDispApi *pR return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_nvdispapiIsDuplicate(struct NvDispApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset), hMemory, pDuplicate); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_nvdispapiGetNotificationListPtr(struct NvDispApi *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_NvDispApi_Notifier.offset)); } @@ -1729,6 +1745,8 @@ static void __nvoc_init_funcTable_NvDispApi_1(NvDispApi *pThis) { pThis->__nvdispapiUnmapFrom__ = &__nvoc_thunk_RsResource_nvdispapiUnmapFrom; + pThis->__nvdispapiIsDuplicate__ = &__nvoc_thunk_RsResource_nvdispapiIsDuplicate; + pThis->__nvdispapiGetNotificationListPtr__ = &__nvoc_thunk_Notifier_nvdispapiGetNotificationListPtr; pThis->__nvdispapiControl_Epilogue__ = &__nvoc_thunk_DisplayApi_nvdispapiControl_Epilogue; @@ -1983,6 +2001,10 @@ static NV_STATUS __nvoc_thunk_RsResource_dispswobjUnmapFrom(struct DispSwObj *pR return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_dispswobjIsDuplicate(struct DispSwObj *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset), hMemory, pDuplicate); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_dispswobjGetNotificationListPtr(struct DispSwObj *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispSwObj_Notifier.offset)); } @@ -2164,6 +2186,8 @@ static void __nvoc_init_funcTable_DispSwObj_1(DispSwObj *pThis) { pThis->__dispswobjUnmapFrom__ = &__nvoc_thunk_RsResource_dispswobjUnmapFrom; + pThis->__dispswobjIsDuplicate__ = &__nvoc_thunk_RsResource_dispswobjIsDuplicate; + pThis->__dispswobjGetNotificationListPtr__ = &__nvoc_thunk_Notifier_dispswobjGetNotificationListPtr; pThis->__dispswobjControl_Epilogue__ = &__nvoc_thunk_DisplayApi_dispswobjControl_Epilogue; @@ -2417,6 +2441,10 @@ static NV_STATUS __nvoc_thunk_RsResource_dispcmnUnmapFrom(struct DispCommon *pRe return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_dispcmnIsDuplicate(struct DispCommon *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset), hMemory, pDuplicate); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_dispcmnGetNotificationListPtr(struct DispCommon *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispCommon_Notifier.offset)); } @@ -2478,12 +2506,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm #endif }, { /* [2] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSystemGetVblankCounter_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, /*accessRight=*/0x0u, /*methodId=*/ 0x730109u, /*paramSize=*/ sizeof(NV0073_CTRL_SYSTEM_GET_VBLANK_COUNTER_PARAMS), @@ -2523,12 +2551,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm #endif }, { /* [5] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8210u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSystemGetConnectState_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8210u) + /*flags=*/ 0x8210u, /*accessRight=*/0x0u, /*methodId=*/ 0x730122u, /*paramSize=*/ sizeof(NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS), @@ -2538,12 +2566,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm #endif }, { /* [6] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSystemGetHotplugConfig_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x730123u, /*paramSize=*/ sizeof(NV0073_CTRL_SYSTEM_GET_SET_HOTPLUG_CONFIG_PARAMS), @@ -2598,6 +2626,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm #endif }, { /* [10] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSystemGetAcpiIdMap_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x73015au, + /*paramSize=*/ sizeof(NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdSystemGetAcpiIdMap" +#endif + }, + { /* [11] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2612,13 +2655,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemGetInternalDisplays" #endif }, - { /* [11] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [12] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSystemGetBootDisplays_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x730166u, /*paramSize=*/ sizeof(NV0073_CTRL_SYSTEM_GET_BOOT_DISPLAYS_PARAMS), @@ -2627,7 +2670,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemGetBootDisplays" #endif }, - { /* [12] */ + { /* [13] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x12u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x12u) + /*flags=*/ 0x12u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x730168u, + /*paramSize=*/ sizeof(NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdSystemExecuteAcpiMethod" +#endif + }, + { /* [14] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2642,7 +2700,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemGetHotplugUnplugState" #endif }, - { /* [13] */ + { /* [15] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2657,7 +2715,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdClearELVBlock" #endif }, - { /* [14] */ + { /* [16] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2672,7 +2730,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemArmLightweightSupervisor" #endif }, - { /* [15] */ + { /* [17] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2687,7 +2745,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemConfigVrrPstateSwitch" #endif }, - { /* [16] */ + { /* [18] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2702,7 +2760,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemQueryDisplayIdsWithMux" #endif }, - { /* [17] */ + { /* [19] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2717,13 +2775,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemAllocateDisplayBandwidth" #endif }, - { /* [18] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [20] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSystemGetHotplugEventConfig_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x730197u, /*paramSize=*/ sizeof(NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS), @@ -2732,13 +2790,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemGetHotplugEventConfig" #endif }, - { /* [19] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [21] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSystemSetHotplugEventConfig_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x730198u, /*paramSize=*/ sizeof(NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS), @@ -2747,7 +2805,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemSetHotplugEventConfig" #endif }, - { /* [20] */ + { /* [22] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2762,7 +2820,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpRecordChannelRegisters" #endif }, - { /* [21] */ + { /* [23] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2777,7 +2835,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSystemCheckSidebandI2cSupport" #endif }, - { /* [22] */ + { /* [24] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSystemCheckSidebandSrSupport_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*flags=*/ 0x200u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x73019du, + /*paramSize=*/ sizeof(NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdSystemCheckSidebandSrSupport" +#endif + }, + { /* [25] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2792,13 +2865,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetI2cPortid" #endif }, - { /* [23] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) + { /* [26] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x206u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSpecificGetType_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) - /*flags=*/ 0x212u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x206u) + /*flags=*/ 0x206u, /*accessRight=*/0x0u, /*methodId=*/ 0x730240u, /*paramSize=*/ sizeof(NV0073_CTRL_SPECIFIC_GET_TYPE_PARAMS), @@ -2807,13 +2880,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetType" #endif }, - { /* [24] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [27] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSpecificFakeDevice_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x730243u, /*paramSize=*/ sizeof(NV0073_CTRL_CMD_SPECIFIC_FAKE_DEVICE_PARAMS), @@ -2822,13 +2895,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificFakeDevice" #endif }, - { /* [25] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [28] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSpecificGetEdidV2_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x730245u, /*paramSize=*/ sizeof(NV0073_CTRL_SPECIFIC_GET_EDID_V2_PARAMS), @@ -2837,7 +2910,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetEdidV2" #endif }, - { /* [26] */ + { /* [29] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2852,7 +2925,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetEdidV2" #endif }, - { /* [27] */ + { /* [30] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2867,7 +2940,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetConnectorData" #endif }, - { /* [28] */ + { /* [31] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2882,13 +2955,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetHdmiEnable" #endif }, - { /* [29] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [32] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSpecificCtrlHdmi_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x730274u, /*paramSize=*/ sizeof(NV0073_CTRL_SPECIFIC_CTRL_HDMI_PARAMS), @@ -2897,13 +2970,43 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificCtrlHdmi" #endif }, - { /* [30] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [33] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSpecificSetAcpiIdMapping_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*flags=*/ 0x4u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x730284u, + /*paramSize=*/ sizeof(NV0073_CTRL_SPECIFIC_SET_ACPI_ID_MAPPING_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdSpecificSetAcpiIdMapping" +#endif + }, + { /* [34] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSpecificGetAcpiDodDisplayPortAttachment_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x730285u, + /*paramSize=*/ sizeof(NV0073_CTRL_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdSpecificGetAcpiDodDisplayPortAttachment" +#endif + }, + { /* [35] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSpecificGetAllHeadMask_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x730287u, /*paramSize=*/ sizeof(NV0073_CTRL_SPECIFIC_GET_ALL_HEAD_MASK_PARAMS), @@ -2912,7 +3015,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetAllHeadMask" #endif }, - { /* [31] */ + { /* [36] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2927,7 +3030,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetOdPacket" #endif }, - { /* [32] */ + { /* [37] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2942,7 +3045,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetOdPacketCtrl" #endif }, - { /* [33] */ + { /* [38] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2957,13 +3060,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetPclkLimit" #endif }, - { /* [34] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) + { /* [39] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x206u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSpecificOrGetInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) - /*flags=*/ 0x212u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x206u) + /*flags=*/ 0x206u, /*accessRight=*/0x0u, /*methodId=*/ 0x73028bu, /*paramSize=*/ sizeof(NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS), @@ -2972,7 +3075,37 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificOrGetInfo" #endif }, - { /* [35] */ + { /* [40] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSpecificGetBacklightBrightness_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*flags=*/ 0x200u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x730291u, + /*paramSize=*/ sizeof(NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdSpecificGetBacklightBrightness" +#endif + }, + { /* [41] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSpecificSetBacklightBrightness_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*flags=*/ 0x200u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x730292u, + /*paramSize=*/ sizeof(NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdSpecificSetBacklightBrightness" +#endif + }, + { /* [42] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2987,7 +3120,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetHdmiSinkCaps" #endif }, - { /* [36] */ + { /* [43] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3002,7 +3135,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetMonitorPower" #endif }, - { /* [37] */ + { /* [44] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3017,7 +3150,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetHdmiFrlLinkConfig" #endif }, - { /* [38] */ + { /* [45] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3032,7 +3165,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificApplyEdidOverrideV2" #endif }, - { /* [39] */ + { /* [46] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3047,7 +3180,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetHdmiGpuCaps" #endif }, - { /* [40] */ + { /* [47] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3062,7 +3195,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificDisplayChange" #endif }, - { /* [41] */ + { /* [48] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3077,7 +3210,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetHdmiScdcData" #endif }, - { /* [42] */ + { /* [49] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3092,7 +3225,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificIsDirectmodeDisplay" #endif }, - { /* [43] */ + { /* [50] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3107,7 +3240,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetHdmiFrlCapacityComputation" #endif }, - { /* [44] */ + { /* [51] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3122,7 +3255,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetSharedGenericPacket" #endif }, - { /* [45] */ + { /* [52] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3137,7 +3270,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificAcquireSharedGenericPacket" #endif }, - { /* [46] */ + { /* [53] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3152,7 +3285,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificReleaseSharedGenericPacket" #endif }, - { /* [47] */ + { /* [54] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3167,7 +3300,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificDispI2cReadWrite" #endif }, - { /* [48] */ + { /* [55] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSpecificGetValidHeadWindowAssignment_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x7302adu, + /*paramSize=*/ sizeof(NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdSpecificGetValidHeadWindowAssignment" +#endif + }, + { /* [56] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3182,13 +3330,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdInternalGetHotplugUnplugState" #endif }, - { /* [49] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) + { /* [57] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x206u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDfpGetInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) - /*flags=*/ 0x212u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x206u) + /*flags=*/ 0x206u, /*accessRight=*/0x0u, /*methodId=*/ 0x731140u, /*paramSize=*/ sizeof(NV0073_CTRL_DFP_GET_INFO_PARAMS), @@ -3197,7 +3345,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetInfo" #endif }, - { /* [50] */ + { /* [58] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3212,7 +3360,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetDisplayportDongleInfo" #endif }, - { /* [51] */ + { /* [59] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3227,13 +3375,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpSetEldAudioCaps" #endif }, - { /* [52] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [60] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDfpGetSpreadSpectrum_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x73114cu, /*paramSize=*/ sizeof(NV0073_CTRL_DFP_GET_SPREAD_SPECTRUM_PARAMS), @@ -3242,13 +3390,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetSpreadSpectrum" #endif }, - { /* [53] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [61] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDfpUpdateDynamicDfpCache_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x73114eu, /*paramSize=*/ sizeof(NV0073_CTRL_DFP_UPDATE_DYNAMIC_DFP_CACHE_PARAMS), @@ -3257,7 +3405,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpUpdateDynamicDfpCache" #endif }, - { /* [54] */ + { /* [62] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3272,13 +3420,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpSetAudioEnable" #endif }, - { /* [55] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [63] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDfpAssignSor_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x731152u, /*paramSize=*/ sizeof(NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS), @@ -3287,13 +3435,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpAssignSor" #endif }, - { /* [56] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [64] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDfpGetPadlinkMask_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x731153u, /*paramSize=*/ sizeof(NV0073_CTRL_DFP_GET_PADLINK_MASK_PARAMS), @@ -3302,13 +3450,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetPadlinkMask" #endif }, - { /* [57] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [65] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDfpGetLcdGpioPinNum_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x731154u, /*paramSize=*/ sizeof(NV0073_CTRL_DFP_GET_LCD_GPIO_PIN_NUM_PARAMS), @@ -3317,13 +3465,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetLcdGpioPinNum" #endif }, - { /* [58] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [66] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDfpConfigTwoHeadOneOr_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x731156u, /*paramSize=*/ sizeof(NV0073_CTRL_DFP_CONFIG_TWO_HEAD_ONE_OR_PARAMS), @@ -3332,13 +3480,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpConfigTwoHeadOneOr" #endif }, - { /* [59] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [67] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDfpDscCrcControl_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x731157u, /*paramSize=*/ sizeof(NV0073_CTRL_DFP_DSC_CRC_CONTROL_PARAMS), @@ -3347,7 +3495,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpDscCrcControl" #endif }, - { /* [60] */ + { /* [68] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3362,7 +3510,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpInitMuxData" #endif }, - { /* [61] */ + { /* [69] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3377,7 +3525,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpSwitchDispMux" #endif }, - { /* [62] */ + { /* [70] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3392,7 +3540,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpRunPreDispMuxOperations" #endif }, - { /* [63] */ + { /* [71] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3407,7 +3555,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpRunPostDispMuxOperations" #endif }, - { /* [64] */ + { /* [72] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3422,13 +3570,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetDispMuxStatus" #endif }, - { /* [65] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [73] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDfpGetDsiModeTiming_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x731166u, /*paramSize=*/ sizeof(NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS), @@ -3437,7 +3585,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetDsiModeTiming" #endif }, - { /* [66] */ + { /* [74] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x202u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3452,13 +3600,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetFixedModeTiming" #endif }, - { /* [67] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [75] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpAuxchCtrl_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8204u) + /*flags=*/ 0x8204u, /*accessRight=*/0x0u, /*methodId=*/ 0x731341u, /*paramSize=*/ sizeof(NV0073_CTRL_DP_AUXCH_CTRL_PARAMS), @@ -3467,13 +3615,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpAuxchCtrl" #endif }, - { /* [68] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [76] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpAuxchSetSema_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x731342u, /*paramSize=*/ sizeof(NV0073_CTRL_DP_AUXCH_SET_SEMA_PARAMS), @@ -3482,13 +3630,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpAuxchSetSema" #endif }, - { /* [69] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [77] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpCtrl_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8204u) + /*flags=*/ 0x8204u, /*accessRight=*/0x0u, /*methodId=*/ 0x731343u, /*paramSize=*/ sizeof(NV0073_CTRL_DP_CTRL_PARAMS), @@ -3497,13 +3645,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpCtrl" #endif }, - { /* [70] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [78] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpGetLaneData_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x731345u, /*paramSize=*/ sizeof(NV0073_CTRL_DP_LANE_DATA_PARAMS), @@ -3512,13 +3660,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetLaneData" #endif }, - { /* [71] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [79] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpSetLaneData_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x731346u, /*paramSize=*/ sizeof(NV0073_CTRL_DP_LANE_DATA_PARAMS), @@ -3527,13 +3675,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetLaneData" #endif }, - { /* [72] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [80] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpSetTestpattern_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x731347u, /*paramSize=*/ sizeof(NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS), @@ -3542,13 +3690,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetTestpattern" #endif }, - { /* [73] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [81] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpSetPreemphasisDrivecurrentPostcursor2Data_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x731351u, /*paramSize=*/ sizeof(NV0073_CTRL_DP_SET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS), @@ -3557,13 +3705,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetPreemphasisDrivecurrentPostcursor2Data" #endif }, - { /* [74] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [82] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpGetPreemphasisDrivecurrentPostcursor2Data_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x731352u, /*paramSize=*/ sizeof(NV0073_CTRL_DP_GET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS), @@ -3572,13 +3720,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetPreemphasisDrivecurrentPostcursor2Data" #endif }, - { /* [75] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [83] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpMainLinkCtrl_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x731356u, /*paramSize=*/ sizeof(NV0073_CTRL_DP_MAIN_LINK_CTRL_PARAMS), @@ -3587,13 +3735,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpMainLinkCtrl" #endif }, - { /* [76] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [84] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpGetAudioMuteStream_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x731358u, /*paramSize=*/ sizeof(NV0073_CTRL_DP_GET_AUDIO_MUTESTREAM_PARAMS), @@ -3602,7 +3750,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetAudioMuteStream" #endif }, - { /* [77] */ + { /* [85] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3617,13 +3765,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetAudioMuteStream" #endif }, - { /* [78] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [86] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpASSRCtrl_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x73135au, /*paramSize=*/ sizeof(NV0073_CTRL_DP_ASSR_CTRL_PARAMS), @@ -3632,13 +3780,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpASSRCtrl" #endif }, - { /* [79] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [87] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpTopologyAllocateDisplayId_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x73135bu, /*paramSize=*/ sizeof(NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID_PARAMS), @@ -3647,13 +3795,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpTopologyAllocateDisplayId" #endif }, - { /* [80] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [88] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpTopologyFreeDisplayId_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x73135cu, /*paramSize=*/ sizeof(NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS), @@ -3662,13 +3810,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpTopologyFreeDisplayId" #endif }, - { /* [81] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [89] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpGetLinkConfig_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x731360u, /*paramSize=*/ sizeof(NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS), @@ -3677,13 +3825,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetLinkConfig" #endif }, - { /* [82] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [90] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpGetEDPData_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x731361u, /*paramSize=*/ sizeof(NV0073_CTRL_DP_GET_EDP_DATA_PARAMS), @@ -3692,13 +3840,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetEDPData" #endif }, - { /* [83] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [91] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpConfigStream_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x731362u, /*paramSize=*/ sizeof(NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS), @@ -3707,13 +3855,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpConfigStream" #endif }, - { /* [84] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [92] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpSetRateGov_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x731363u, /*paramSize=*/ sizeof(NV0073_CTRL_CMD_DP_SET_RATE_GOV_PARAMS), @@ -3722,13 +3870,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetRateGov" #endif }, - { /* [85] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [93] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpSetManualDisplayPort_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x731365u, /*paramSize=*/ sizeof(NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT_PARAMS), @@ -3737,13 +3885,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetManualDisplayPort" #endif }, - { /* [86] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [94] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpSetEcf_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x731366u, /*paramSize=*/ sizeof(NV0073_CTRL_CMD_DP_SET_ECF_PARAMS), @@ -3752,13 +3900,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetEcf" #endif }, - { /* [87] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [95] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpSendACT_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x731367u, /*paramSize=*/ sizeof(NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS), @@ -3767,13 +3915,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSendACT" #endif }, - { /* [88] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) + { /* [96] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x206u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpGetCaps_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) - /*flags=*/ 0x212u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x206u) + /*flags=*/ 0x206u, /*accessRight=*/0x0u, /*methodId=*/ 0x731369u, /*paramSize=*/ sizeof(NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS), @@ -3782,13 +3930,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetCaps" #endif }, - { /* [89] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [97] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpGenerateFakeInterrupt_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*flags=*/ 0x4u, /*accessRight=*/0x0u, /*methodId=*/ 0x73136bu, /*paramSize=*/ sizeof(NV0073_CTRL_CMD_DP_GENERATE_FAKE_INTERRUPT_PARAMS), @@ -3797,13 +3945,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGenerateFakeInterrupt" #endif }, - { /* [90] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [98] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpConfigRadScratchReg_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x73136cu, /*paramSize=*/ sizeof(NV0073_CTRL_CMD_DP_CONFIG_RAD_SCRATCH_REG_PARAMS), @@ -3812,13 +3960,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpConfigRadScratchReg" #endif }, - { /* [91] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [99] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpConfigSingleHeadMultiStream_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x73136eu, /*paramSize=*/ sizeof(NV0073_CTRL_CMD_DP_CONFIG_SINGLE_HEAD_MULTI_STREAM_PARAMS), @@ -3827,13 +3975,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpConfigSingleHeadMultiStream" #endif }, - { /* [92] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [100] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpSetTriggerSelect_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x73136fu, /*paramSize=*/ sizeof(NV0073_CTRL_CMD_DP_SET_TRIGGER_SELECT_PARAMS), @@ -3842,13 +3990,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetTriggerSelect" #endif }, - { /* [93] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [101] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpSetTriggerAll_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x731370u, /*paramSize=*/ sizeof(NV0073_CTRL_CMD_DP_SET_TRIGGER_ALL_PARAMS), @@ -3857,7 +4005,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetTriggerAll" #endif }, - { /* [94] */ + { /* [102] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3872,13 +4020,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetAuxLogData" #endif }, - { /* [95] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [103] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpConfigIndexedLinkRates_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x731377u, /*paramSize=*/ sizeof(NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS), @@ -3887,13 +4035,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpConfigIndexedLinkRates" #endif }, - { /* [96] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [104] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpSetStereoMSAProperties_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x731378u, /*paramSize=*/ sizeof(NV0073_CTRL_CMD_DP_SET_STEREO_MSA_PROPERTIES_PARAMS), @@ -3902,13 +4050,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetStereoMSAProperties" #endif }, - { /* [97] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [105] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpConfigureFec_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x73137au, /*paramSize=*/ sizeof(NV0073_CTRL_CMD_DP_CONFIGURE_FEC_PARAMS), @@ -3917,13 +4065,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpConfigureFec" #endif }, - { /* [98] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [106] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpConfigMacroPad_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x73137bu, /*paramSize=*/ sizeof(NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_PARAMS), @@ -3932,7 +4080,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpConfigMacroPad" #endif }, - { /* [99] */ + { /* [107] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3947,13 +4095,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpAuxchI2cTransferCtrl" #endif }, - { /* [100] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [108] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpEnableVrr_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x73137du, /*paramSize=*/ sizeof(NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS), @@ -3962,13 +4110,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpEnableVrr" #endif }, - { /* [101] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [109] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpGetGenericInfoframe_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x73137eu, /*paramSize=*/ sizeof(NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_PARAMS), @@ -3977,13 +4125,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetGenericInfoframe" #endif }, - { /* [102] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [110] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpGetMsaAttributes_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x73137fu, /*paramSize=*/ sizeof(NV0073_CTRL_DP_GET_MSA_ATTRIBUTES_PARAMS), @@ -3992,7 +4140,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetMsaAttributes" #endif }, - { /* [103] */ + { /* [111] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4007,13 +4155,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpInternalLcdOverdrive" #endif }, - { /* [104] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [112] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDpSetMSAPropertiesv2_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, /*accessRight=*/0x0u, /*methodId=*/ 0x731381u, /*paramSize=*/ sizeof(NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS), @@ -4027,7 +4175,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm const struct NVOC_EXPORT_INFO __nvoc_export_info_DispCommon = { - /*numEntries=*/ 105, + /*numEntries=*/ 113, /*pExportEntries=*/ __nvoc_exported_method_def_DispCommon }; @@ -4063,7 +4211,7 @@ __nvoc_ctor_DispCommon_exit: static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { PORT_UNREFERENCED_VARIABLE(pThis); -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__dispcmnCtrlCmdSystemGetVblankCounter__ = &dispcmnCtrlCmdSystemGetVblankCounter_IMPL; #endif @@ -4071,11 +4219,15 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdSystemGetVblankEnable__ = &dispcmnCtrlCmdSystemGetVblankEnable_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + pThis->__dispcmnCtrlCmdSystemCheckSidebandSrSupport__ = &dispcmnCtrlCmdSystemCheckSidebandSrSupport_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) pThis->__dispcmnCtrlCmdSystemGetInternalDisplays__ = &dispcmnCtrlCmdSystemGetInternalDisplays_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpEnableVrr__ = &dispcmnCtrlCmdDpEnableVrr_IMPL; #endif @@ -4087,15 +4239,15 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdSpecificDisplayChange__ = &dispcmnCtrlCmdSpecificDisplayChange_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDfpGetSpreadSpectrum__ = &dispcmnCtrlCmdDfpGetSpreadSpectrum_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDfpGetLcdGpioPinNum__ = &dispcmnCtrlCmdDfpGetLcdGpioPinNum_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpGetAudioMuteStream__ = &dispcmnCtrlCmdDpGetAudioMuteStream_IMPL; #endif @@ -4103,14 +4255,22 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdDpAuxchI2cTransferCtrl__ = &dispcmnCtrlCmdDpAuxchI2cTransferCtrl_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpASSRCtrl__ = &dispcmnCtrlCmdDpASSRCtrl_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpSetEcf__ = &dispcmnCtrlCmdDpSetEcf_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + pThis->__dispcmnCtrlCmdSpecificGetBacklightBrightness__ = &dispcmnCtrlCmdSpecificGetBacklightBrightness_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + pThis->__dispcmnCtrlCmdSpecificSetBacklightBrightness__ = &dispcmnCtrlCmdSpecificSetBacklightBrightness_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDfpSwitchDispMux__ = &dispcmnCtrlCmdDfpSwitchDispMux_IMPL; #endif @@ -4135,6 +4295,22 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdDfpInternalLcdOverdrive__ = &dispcmnCtrlCmdDfpInternalLcdOverdrive_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x12u) + pThis->__dispcmnCtrlCmdSystemExecuteAcpiMethod__ = &dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__dispcmnCtrlCmdSystemGetAcpiIdMap__ = &dispcmnCtrlCmdSystemGetAcpiIdMap_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + pThis->__dispcmnCtrlCmdSpecificSetAcpiIdMapping__ = &dispcmnCtrlCmdSpecificSetAcpiIdMapping_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + pThis->__dispcmnCtrlCmdSpecificGetAcpiDodDisplayPortAttachment__ = &dispcmnCtrlCmdSpecificGetAcpiDodDisplayPortAttachment_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__dispcmnCtrlCmdSystemGetCapsV2__ = &dispcmnCtrlCmdSystemGetCapsV2_IMPL; #endif @@ -4151,7 +4327,7 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdSystemGetSuppported__ = &dispcmnCtrlCmdSystemGetSuppported_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8210u) pThis->__dispcmnCtrlCmdSystemGetConnectState__ = &dispcmnCtrlCmdSystemGetConnectState_IMPL; #endif @@ -4171,7 +4347,7 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdSystemGetActive__ = &dispcmnCtrlCmdSystemGetActive_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdSystemGetBootDisplays__ = &dispcmnCtrlCmdSystemGetBootDisplays_IMPL; #endif @@ -4187,15 +4363,15 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdSystemAllocateDisplayBandwidth__ = &dispcmnCtrlCmdSystemAllocateDisplayBandwidth_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdSystemGetHotplugConfig__ = &dispcmnCtrlCmdSystemGetHotplugConfig_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdSystemGetHotplugEventConfig__ = &dispcmnCtrlCmdSystemGetHotplugEventConfig_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdSystemSetHotplugEventConfig__ = &dispcmnCtrlCmdSystemSetHotplugEventConfig_IMPL; #endif @@ -4207,11 +4383,11 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdSystemConfigVrrPstateSwitch__ = &dispcmnCtrlCmdSystemConfigVrrPstateSwitch_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x206u) pThis->__dispcmnCtrlCmdSpecificGetType__ = &dispcmnCtrlCmdSpecificGetType_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdSpecificGetEdidV2__ = &dispcmnCtrlCmdSpecificGetEdidV2_IMPL; #endif @@ -4219,7 +4395,7 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdSpecificSetEdidV2__ = &dispcmnCtrlCmdSpecificSetEdidV2_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdSpecificFakeDevice__ = &dispcmnCtrlCmdSpecificFakeDevice_IMPL; #endif @@ -4231,11 +4407,11 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdSpecificSetHdmiEnable__ = &dispcmnCtrlCmdSpecificSetHdmiEnable_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdSpecificCtrlHdmi__ = &dispcmnCtrlCmdSpecificCtrlHdmi_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdSpecificGetAllHeadMask__ = &dispcmnCtrlCmdSpecificGetAllHeadMask_IMPL; #endif @@ -4259,7 +4435,7 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdSpecificSetOdPacketCtrl__ = &dispcmnCtrlCmdSpecificSetOdPacketCtrl_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x206u) pThis->__dispcmnCtrlCmdSpecificOrGetInfo__ = &dispcmnCtrlCmdSpecificOrGetInfo_IMPL; #endif @@ -4307,7 +4483,11 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdSpecificDispI2cReadWrite__ = &dispcmnCtrlCmdSpecificDispI2cReadWrite_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__dispcmnCtrlCmdSpecificGetValidHeadWindowAssignment__ = &dispcmnCtrlCmdSpecificGetValidHeadWindowAssignment_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x206u) pThis->__dispcmnCtrlCmdDfpGetInfo__ = &dispcmnCtrlCmdDfpGetInfo_IMPL; #endif @@ -4323,15 +4503,15 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdDfpSetAudioEnable__ = &dispcmnCtrlCmdDfpSetAudioEnable_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDfpUpdateDynamicDfpCache__ = &dispcmnCtrlCmdDfpUpdateDynamicDfpCache_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDfpAssignSor__ = &dispcmnCtrlCmdDfpAssignSor_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDfpDscCrcControl__ = &dispcmnCtrlCmdDfpDscCrcControl_IMPL; #endif @@ -4339,15 +4519,15 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdDfpInitMuxData__ = &dispcmnCtrlCmdDfpInitMuxData_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDfpGetDsiModeTiming__ = &dispcmnCtrlCmdDfpGetDsiModeTiming_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDfpConfigTwoHeadOneOr__ = &dispcmnCtrlCmdDfpConfigTwoHeadOneOr_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDfpGetPadlinkMask__ = &dispcmnCtrlCmdDfpGetPadlinkMask_IMPL; #endif @@ -4355,31 +4535,31 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdDfpGetFixedModeTiming__ = &dispcmnCtrlCmdDfpGetFixedModeTiming_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8204u) pThis->__dispcmnCtrlCmdDpAuxchCtrl__ = &dispcmnCtrlCmdDpAuxchCtrl_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpAuxchSetSema__ = &dispcmnCtrlCmdDpAuxchSetSema_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8204u) pThis->__dispcmnCtrlCmdDpCtrl__ = &dispcmnCtrlCmdDpCtrl_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpGetLaneData__ = &dispcmnCtrlCmdDpGetLaneData_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpSetLaneData__ = &dispcmnCtrlCmdDpSetLaneData_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpSetTestpattern__ = &dispcmnCtrlCmdDpSetTestpattern_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpMainLinkCtrl__ = &dispcmnCtrlCmdDpMainLinkCtrl_IMPL; #endif @@ -4387,67 +4567,67 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdDpSetAudioMuteStream__ = &dispcmnCtrlCmdDpSetAudioMuteStream_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpGetLinkConfig__ = &dispcmnCtrlCmdDpGetLinkConfig_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpGetEDPData__ = &dispcmnCtrlCmdDpGetEDPData_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpTopologyAllocateDisplayId__ = &dispcmnCtrlCmdDpTopologyAllocateDisplayId_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpTopologyFreeDisplayId__ = &dispcmnCtrlCmdDpTopologyFreeDisplayId_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpConfigStream__ = &dispcmnCtrlCmdDpConfigStream_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpConfigSingleHeadMultiStream__ = &dispcmnCtrlCmdDpConfigSingleHeadMultiStream_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpSetRateGov__ = &dispcmnCtrlCmdDpSetRateGov_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpSendACT__ = &dispcmnCtrlCmdDpSendACT_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpSetManualDisplayPort__ = &dispcmnCtrlCmdDpSetManualDisplayPort_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x206u) pThis->__dispcmnCtrlCmdDpGetCaps__ = &dispcmnCtrlCmdDpGetCaps_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpSetMSAPropertiesv2__ = &dispcmnCtrlCmdDpSetMSAPropertiesv2_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpSetStereoMSAProperties__ = &dispcmnCtrlCmdDpSetStereoMSAProperties_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) pThis->__dispcmnCtrlCmdDpGenerateFakeInterrupt__ = &dispcmnCtrlCmdDpGenerateFakeInterrupt_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpConfigRadScratchReg__ = &dispcmnCtrlCmdDpConfigRadScratchReg_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpSetTriggerSelect__ = &dispcmnCtrlCmdDpSetTriggerSelect_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpSetTriggerAll__ = &dispcmnCtrlCmdDpSetTriggerAll_IMPL; #endif @@ -4455,31 +4635,31 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdDpGetAuxLogData__ = &dispcmnCtrlCmdDpGetAuxLogData_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpConfigIndexedLinkRates__ = &dispcmnCtrlCmdDpConfigIndexedLinkRates_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpConfigureFec__ = &dispcmnCtrlCmdDpConfigureFec_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpGetGenericInfoframe__ = &dispcmnCtrlCmdDpGetGenericInfoframe_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpGetMsaAttributes__ = &dispcmnCtrlCmdDpGetMsaAttributes_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpConfigMacroPad__ = &dispcmnCtrlCmdDpConfigMacroPad_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpSetPreemphasisDrivecurrentPostcursor2Data__ = &dispcmnCtrlCmdDpSetPreemphasisDrivecurrentPostcursor2Data_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpGetPreemphasisDrivecurrentPostcursor2Data__ = &dispcmnCtrlCmdDpGetPreemphasisDrivecurrentPostcursor2Data_IMPL; #endif @@ -4517,6 +4697,8 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnUnmapFrom__ = &__nvoc_thunk_RsResource_dispcmnUnmapFrom; + pThis->__dispcmnIsDuplicate__ = &__nvoc_thunk_RsResource_dispcmnIsDuplicate; + pThis->__dispcmnGetNotificationListPtr__ = &__nvoc_thunk_Notifier_dispcmnGetNotificationListPtr; pThis->__dispcmnControl_Epilogue__ = &__nvoc_thunk_DisplayApi_dispcmnControl_Epilogue; diff --git a/src/nvidia/generated/g_disp_objs_nvoc.h b/src/nvidia/generated/g_disp_objs_nvoc.h index 976126449..c5dafeb04 100644 --- a/src/nvidia/generated/g_disp_objs_nvoc.h +++ b/src/nvidia/generated/g_disp_objs_nvoc.h @@ -133,6 +133,7 @@ struct DisplayApi { void (*__dispapiAddAdditionalDependants__)(struct RsClient *, struct DisplayApi *, RsResourceRef *); void (*__dispapiPreDestruct__)(struct DisplayApi *); NV_STATUS (*__dispapiUnmapFrom__)(struct DisplayApi *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__dispapiIsDuplicate__)(struct DisplayApi *, NvHandle, NvBool *); PEVENTNOTIFICATION *(*__dispapiGetNotificationListPtr__)(struct DisplayApi *); struct NotifShare *(*__dispapiGetNotificationShare__)(struct DisplayApi *); NV_STATUS (*__dispapiControlLookup__)(struct DisplayApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); @@ -193,6 +194,7 @@ NV_STATUS __nvoc_objCreate_DisplayApi(DisplayApi**, Dynamic*, NvU32, struct CALL #define dispapiAddAdditionalDependants(pClient, pResource, pReference) dispapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define dispapiPreDestruct(pResource) dispapiPreDestruct_DISPATCH(pResource) #define dispapiUnmapFrom(pResource, pParams) dispapiUnmapFrom_DISPATCH(pResource, pParams) +#define dispapiIsDuplicate(pResource, hMemory, pDuplicate) dispapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define dispapiGetNotificationListPtr(pNotifier) dispapiGetNotificationListPtr_DISPATCH(pNotifier) #define dispapiGetNotificationShare(pNotifier) dispapiGetNotificationShare_DISPATCH(pNotifier) #define dispapiControlLookup(pResource, pParams, ppEntry) dispapiControlLookup_DISPATCH(pResource, pParams, ppEntry) @@ -200,6 +202,7 @@ NV_STATUS __nvoc_objCreate_DisplayApi(DisplayApi**, Dynamic*, NvU32, struct CALL #define dispapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) dispapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) NV_STATUS dispapiSetUnicastAndSynchronize_KERNEL(struct DisplayApi *pDisplayApi, struct OBJGPUGRP *pGpuGroup, struct OBJGPU **ppGpu, NvU32 subDeviceInstance); + #ifdef __nvoc_disp_objs_h_disabled static inline NV_STATUS dispapiSetUnicastAndSynchronize(struct DisplayApi *pDisplayApi, struct OBJGPUGRP *pGpuGroup, struct OBJGPU **ppGpu, NvU32 subDeviceInstance) { NV_ASSERT_FAILED_PRECOMP("DisplayApi was disabled!"); @@ -289,6 +292,10 @@ static inline NV_STATUS dispapiUnmapFrom_DISPATCH(struct DisplayApi *pResource, return pResource->__dispapiUnmapFrom__(pResource, pParams); } +static inline NV_STATUS dispapiIsDuplicate_DISPATCH(struct DisplayApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__dispapiIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline PEVENTNOTIFICATION *dispapiGetNotificationListPtr_DISPATCH(struct DisplayApi *pNotifier) { return pNotifier->__dispapiGetNotificationListPtr__(pNotifier); } @@ -310,10 +317,13 @@ static inline NV_STATUS dispapiGetOrAllocNotifShare_DISPATCH(struct DisplayApi * } NV_STATUS dispapiConstruct_IMPL(struct DisplayApi *arg_pDisplayApi, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_dispapiConstruct(arg_pDisplayApi, arg_pCallContext, arg_pParams) dispapiConstruct_IMPL(arg_pDisplayApi, arg_pCallContext, arg_pParams) void dispapiDestruct_IMPL(struct DisplayApi *pDisplayApi); + #define __nvoc_dispapiDestruct(pDisplayApi) dispapiDestruct_IMPL(pDisplayApi) NV_STATUS dispapiCtrlCmdEventSetNotification_IMPL(struct DisplayApi *pDisplayApi, NV5070_CTRL_EVENT_SET_NOTIFICATION_PARAMS *pSetEventParams); + #ifdef __nvoc_disp_objs_h_disabled static inline NV_STATUS dispapiCtrlCmdEventSetNotification(struct DisplayApi *pDisplayApi, NV5070_CTRL_EVENT_SET_NOTIFICATION_PARAMS *pSetEventParams) { NV_ASSERT_FAILED_PRECOMP("DisplayApi was disabled!"); @@ -396,6 +406,7 @@ struct DispObject { void (*__dispobjAddAdditionalDependants__)(struct RsClient *, struct DispObject *, RsResourceRef *); void (*__dispobjPreDestruct__)(struct DispObject *); NV_STATUS (*__dispobjUnmapFrom__)(struct DispObject *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__dispobjIsDuplicate__)(struct DispObject *, NvHandle, NvBool *); PEVENTNOTIFICATION *(*__dispobjGetNotificationListPtr__)(struct DispObject *); void (*__dispobjControl_Epilogue__)(struct DispObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); struct NotifShare *(*__dispobjGetNotificationShare__)(struct DispObject *); @@ -480,6 +491,7 @@ NV_STATUS __nvoc_objCreate_DispObject(DispObject**, Dynamic*, NvU32, struct CALL #define dispobjAddAdditionalDependants(pClient, pResource, pReference) dispobjAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define dispobjPreDestruct(pResource) dispobjPreDestruct_DISPATCH(pResource) #define dispobjUnmapFrom(pResource, pParams) dispobjUnmapFrom_DISPATCH(pResource, pParams) +#define dispobjIsDuplicate(pResource, hMemory, pDuplicate) dispobjIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define dispobjGetNotificationListPtr(pNotifier) dispobjGetNotificationListPtr_DISPATCH(pNotifier) #define dispobjControl_Epilogue(pDisplayApi, pCallContext, pRsParams) dispobjControl_Epilogue_DISPATCH(pDisplayApi, pCallContext, pRsParams) #define dispobjGetNotificationShare(pNotifier) dispobjGetNotificationShare_DISPATCH(pNotifier) @@ -488,6 +500,7 @@ NV_STATUS __nvoc_objCreate_DispObject(DispObject**, Dynamic*, NvU32, struct CALL #define dispobjGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) dispobjGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) NV_STATUS dispobjConstructHal_IMPL(struct DispObject *pDispObject, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); + #ifdef __nvoc_disp_objs_h_disabled static inline NV_STATUS dispobjConstructHal(struct DispObject *pDispObject, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { NV_ASSERT_FAILED_PRECOMP("DispObject was disabled!"); @@ -747,6 +760,10 @@ static inline NV_STATUS dispobjUnmapFrom_DISPATCH(struct DispObject *pResource, return pResource->__dispobjUnmapFrom__(pResource, pParams); } +static inline NV_STATUS dispobjIsDuplicate_DISPATCH(struct DispObject *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__dispobjIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline PEVENTNOTIFICATION *dispobjGetNotificationListPtr_DISPATCH(struct DispObject *pNotifier) { return pNotifier->__dispobjGetNotificationListPtr__(pNotifier); } @@ -772,12 +789,16 @@ static inline NV_STATUS dispobjGetOrAllocNotifShare_DISPATCH(struct DispObject * } NV_STATUS dispobjConstruct_IMPL(struct DispObject *arg_pDispObject, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_dispobjConstruct(arg_pDispObject, arg_pCallContext, arg_pParams) dispobjConstruct_IMPL(arg_pDispObject, arg_pCallContext, arg_pParams) NV_STATUS dispobjGetByHandle_IMPL(struct RsClient *pClient, NvHandle hDispObject, struct DispObject **ppDispObject); + #define dispobjGetByHandle(pClient, hDispObject, ppDispObject) dispobjGetByHandle_IMPL(pClient, hDispObject, ppDispObject) NV_STATUS dispobjGetByDevice_IMPL(struct RsClient *pClient, struct Device *pDevice, struct DispObject **ppDispObject); + #define dispobjGetByDevice(pClient, pDevice, ppDispObject) dispobjGetByDevice_IMPL(pClient, pDevice, ppDispObject) void dispobjClearRmFreeFlags_IMPL(struct DispObject *pDispObject); + #ifdef __nvoc_disp_objs_h_disabled static inline void dispobjClearRmFreeFlags(struct DispObject *pDispObject) { NV_ASSERT_FAILED_PRECOMP("DispObject was disabled!"); @@ -787,6 +808,7 @@ static inline void dispobjClearRmFreeFlags(struct DispObject *pDispObject) { #endif //__nvoc_disp_objs_h_disabled NvBool dispobjGetRmFreeFlags_IMPL(struct DispObject *pDispObject); + #ifdef __nvoc_disp_objs_h_disabled static inline NvBool dispobjGetRmFreeFlags(struct DispObject *pDispObject) { NV_ASSERT_FAILED_PRECOMP("DispObject was disabled!"); @@ -847,6 +869,7 @@ struct NvDispApi { void (*__nvdispapiAddAdditionalDependants__)(struct RsClient *, struct NvDispApi *, RsResourceRef *); void (*__nvdispapiPreDestruct__)(struct NvDispApi *); NV_STATUS (*__nvdispapiUnmapFrom__)(struct NvDispApi *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__nvdispapiIsDuplicate__)(struct NvDispApi *, NvHandle, NvBool *); PEVENTNOTIFICATION *(*__nvdispapiGetNotificationListPtr__)(struct NvDispApi *); void (*__nvdispapiControl_Epilogue__)(struct NvDispApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); struct NotifShare *(*__nvdispapiGetNotificationShare__)(struct NvDispApi *); @@ -907,6 +930,7 @@ NV_STATUS __nvoc_objCreate_NvDispApi(NvDispApi**, Dynamic*, NvU32, struct CALL_C #define nvdispapiAddAdditionalDependants(pClient, pResource, pReference) nvdispapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define nvdispapiPreDestruct(pResource) nvdispapiPreDestruct_DISPATCH(pResource) #define nvdispapiUnmapFrom(pResource, pParams) nvdispapiUnmapFrom_DISPATCH(pResource, pParams) +#define nvdispapiIsDuplicate(pResource, hMemory, pDuplicate) nvdispapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define nvdispapiGetNotificationListPtr(pNotifier) nvdispapiGetNotificationListPtr_DISPATCH(pNotifier) #define nvdispapiControl_Epilogue(pDisplayApi, pCallContext, pRsParams) nvdispapiControl_Epilogue_DISPATCH(pDisplayApi, pCallContext, pRsParams) #define nvdispapiGetNotificationShare(pNotifier) nvdispapiGetNotificationShare_DISPATCH(pNotifier) @@ -1023,6 +1047,10 @@ static inline NV_STATUS nvdispapiUnmapFrom_DISPATCH(struct NvDispApi *pResource, return pResource->__nvdispapiUnmapFrom__(pResource, pParams); } +static inline NV_STATUS nvdispapiIsDuplicate_DISPATCH(struct NvDispApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__nvdispapiIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline PEVENTNOTIFICATION *nvdispapiGetNotificationListPtr_DISPATCH(struct NvDispApi *pNotifier) { return pNotifier->__nvdispapiGetNotificationListPtr__(pNotifier); } @@ -1048,6 +1076,7 @@ static inline NV_STATUS nvdispapiGetOrAllocNotifShare_DISPATCH(struct NvDispApi } NV_STATUS nvdispapiConstruct_IMPL(struct NvDispApi *arg_pNvdispApi, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_nvdispapiConstruct(arg_pNvdispApi, arg_pCallContext, arg_pParams) nvdispapiConstruct_IMPL(arg_pNvdispApi, arg_pCallContext, arg_pParams) #undef PRIVATE_FIELD @@ -1099,6 +1128,7 @@ struct DispSwObj { void (*__dispswobjAddAdditionalDependants__)(struct RsClient *, struct DispSwObj *, RsResourceRef *); void (*__dispswobjPreDestruct__)(struct DispSwObj *); NV_STATUS (*__dispswobjUnmapFrom__)(struct DispSwObj *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__dispswobjIsDuplicate__)(struct DispSwObj *, NvHandle, NvBool *); PEVENTNOTIFICATION *(*__dispswobjGetNotificationListPtr__)(struct DispSwObj *); void (*__dispswobjControl_Epilogue__)(struct DispSwObj *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); struct NotifShare *(*__dispswobjGetNotificationShare__)(struct DispSwObj *); @@ -1156,6 +1186,7 @@ NV_STATUS __nvoc_objCreate_DispSwObj(DispSwObj**, Dynamic*, NvU32, struct CALL_C #define dispswobjAddAdditionalDependants(pClient, pResource, pReference) dispswobjAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define dispswobjPreDestruct(pResource) dispswobjPreDestruct_DISPATCH(pResource) #define dispswobjUnmapFrom(pResource, pParams) dispswobjUnmapFrom_DISPATCH(pResource, pParams) +#define dispswobjIsDuplicate(pResource, hMemory, pDuplicate) dispswobjIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define dispswobjGetNotificationListPtr(pNotifier) dispswobjGetNotificationListPtr_DISPATCH(pNotifier) #define dispswobjControl_Epilogue(pDisplayApi, pCallContext, pRsParams) dispswobjControl_Epilogue_DISPATCH(pDisplayApi, pCallContext, pRsParams) #define dispswobjGetNotificationShare(pNotifier) dispswobjGetNotificationShare_DISPATCH(pNotifier) @@ -1254,6 +1285,10 @@ static inline NV_STATUS dispswobjUnmapFrom_DISPATCH(struct DispSwObj *pResource, return pResource->__dispswobjUnmapFrom__(pResource, pParams); } +static inline NV_STATUS dispswobjIsDuplicate_DISPATCH(struct DispSwObj *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__dispswobjIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline PEVENTNOTIFICATION *dispswobjGetNotificationListPtr_DISPATCH(struct DispSwObj *pNotifier) { return pNotifier->__dispswobjGetNotificationListPtr__(pNotifier); } @@ -1279,6 +1314,7 @@ static inline NV_STATUS dispswobjGetOrAllocNotifShare_DISPATCH(struct DispSwObj } NV_STATUS dispswobjConstruct_IMPL(struct DispSwObj *arg_pDispSwObj, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_dispswobjConstruct(arg_pDispSwObj, arg_pCallContext, arg_pParams) dispswobjConstruct_IMPL(arg_pDispSwObj, arg_pCallContext, arg_pParams) #undef PRIVATE_FIELD @@ -1307,6 +1343,7 @@ struct DispCommon { struct DispCommon *__nvoc_pbase_DispCommon; NV_STATUS (*__dispcmnCtrlCmdSystemGetVblankCounter__)(struct DispCommon *, NV0073_CTRL_SYSTEM_GET_VBLANK_COUNTER_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSystemGetVblankEnable__)(struct DispCommon *, NV0073_CTRL_SYSTEM_GET_VBLANK_ENABLE_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdSystemCheckSidebandSrSupport__)(struct DispCommon *, NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSystemGetInternalDisplays__)(struct DispCommon *, NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDpEnableVrr__)(struct DispCommon *, NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdClearELVBlock__)(struct DispCommon *, NV0073_CTRL_SYSTEM_CLEAR_ELV_BLOCK_PARAMS *); @@ -1317,12 +1354,18 @@ struct DispCommon { NV_STATUS (*__dispcmnCtrlCmdDpAuxchI2cTransferCtrl__)(struct DispCommon *, NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_CTRL_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDpASSRCtrl__)(struct DispCommon *, NV0073_CTRL_DP_ASSR_CTRL_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDpSetEcf__)(struct DispCommon *, NV0073_CTRL_CMD_DP_SET_ECF_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdSpecificGetBacklightBrightness__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdSpecificSetBacklightBrightness__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpSwitchDispMux__)(struct DispCommon *, NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpRunPreDispMuxOperations__)(struct DispCommon *, NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpRunPostDispMuxOperations__)(struct DispCommon *, NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpGetDispMuxStatus__)(struct DispCommon *, NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpRecordChannelRegisters__)(struct DispCommon *, NV0073_CTRL_CMD_SYSTEM_RECORD_CHANNEL_REGS_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpInternalLcdOverdrive__)(struct DispCommon *, NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdSystemExecuteAcpiMethod__)(struct DispCommon *, NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdSystemGetAcpiIdMap__)(struct DispCommon *, NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdSpecificSetAcpiIdMapping__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_SET_ACPI_ID_MAPPING_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdSpecificGetAcpiDodDisplayPortAttachment__)(struct DispCommon *, NV0073_CTRL_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSystemGetCapsV2__)(struct DispCommon *, NV0073_CTRL_SYSTEM_GET_CAPS_V2_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSystemGetNumHeads__)(struct DispCommon *, NV0073_CTRL_SYSTEM_GET_NUM_HEADS_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSystemGetScanline__)(struct DispCommon *, NV0073_CTRL_SYSTEM_GET_SCANLINE_PARAMS *); @@ -1366,6 +1409,7 @@ struct DispCommon { NV_STATUS (*__dispcmnCtrlCmdSpecificIsDirectmodeDisplay__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_IS_DIRECTMODE_DISPLAY_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSpecificSetHdmiFrlCapacityComputation__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSpecificDispI2cReadWrite__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdSpecificGetValidHeadWindowAssignment__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpGetInfo__)(struct DispCommon *, NV0073_CTRL_DFP_GET_INFO_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpGetDisplayportDongleInfo__)(struct DispCommon *, NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpSetEldAudioCaps__)(struct DispCommon *, NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS *); @@ -1427,6 +1471,7 @@ struct DispCommon { void (*__dispcmnAddAdditionalDependants__)(struct RsClient *, struct DispCommon *, RsResourceRef *); void (*__dispcmnPreDestruct__)(struct DispCommon *); NV_STATUS (*__dispcmnUnmapFrom__)(struct DispCommon *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__dispcmnIsDuplicate__)(struct DispCommon *, NvHandle, NvBool *); PEVENTNOTIFICATION *(*__dispcmnGetNotificationListPtr__)(struct DispCommon *); void (*__dispcmnControl_Epilogue__)(struct DispCommon *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); struct NotifShare *(*__dispcmnGetNotificationShare__)(struct DispCommon *); @@ -1467,6 +1512,7 @@ NV_STATUS __nvoc_objCreate_DispCommon(DispCommon**, Dynamic*, NvU32, struct CALL #define dispcmnCtrlCmdSystemGetVblankCounter(pDispCommon, pVBCounterParams) dispcmnCtrlCmdSystemGetVblankCounter_DISPATCH(pDispCommon, pVBCounterParams) #define dispcmnCtrlCmdSystemGetVblankEnable(pDispCommon, pVBEnableParams) dispcmnCtrlCmdSystemGetVblankEnable_DISPATCH(pDispCommon, pVBEnableParams) +#define dispcmnCtrlCmdSystemCheckSidebandSrSupport(pDispCommon, pParams) dispcmnCtrlCmdSystemCheckSidebandSrSupport_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSystemGetInternalDisplays(pDispCommon, pInternalDisplaysParams) dispcmnCtrlCmdSystemGetInternalDisplays_DISPATCH(pDispCommon, pInternalDisplaysParams) #define dispcmnCtrlCmdDpEnableVrr(pDispCommon, pParams) dispcmnCtrlCmdDpEnableVrr_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdClearELVBlock(pDispCommon, pParams) dispcmnCtrlCmdClearELVBlock_DISPATCH(pDispCommon, pParams) @@ -1477,12 +1523,18 @@ NV_STATUS __nvoc_objCreate_DispCommon(DispCommon**, Dynamic*, NvU32, struct CALL #define dispcmnCtrlCmdDpAuxchI2cTransferCtrl(pDispCommon, pParams) dispcmnCtrlCmdDpAuxchI2cTransferCtrl_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDpASSRCtrl(pDispCommon, pParams) dispcmnCtrlCmdDpASSRCtrl_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDpSetEcf(pDispCommon, pCtrlEcfParams) dispcmnCtrlCmdDpSetEcf_DISPATCH(pDispCommon, pCtrlEcfParams) +#define dispcmnCtrlCmdSpecificGetBacklightBrightness(pDispCommon, pAllHeadMaskParams) dispcmnCtrlCmdSpecificGetBacklightBrightness_DISPATCH(pDispCommon, pAllHeadMaskParams) +#define dispcmnCtrlCmdSpecificSetBacklightBrightness(pDispCommon, pParams) dispcmnCtrlCmdSpecificSetBacklightBrightness_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpSwitchDispMux(pDispCommon, pParams) dispcmnCtrlCmdDfpSwitchDispMux_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpRunPreDispMuxOperations(pDispCommon, pParams) dispcmnCtrlCmdDfpRunPreDispMuxOperations_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpRunPostDispMuxOperations(pDispCommon, pParams) dispcmnCtrlCmdDfpRunPostDispMuxOperations_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpGetDispMuxStatus(pDispCommon, pParams) dispcmnCtrlCmdDfpGetDispMuxStatus_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpRecordChannelRegisters(pDispCommon, pParams) dispcmnCtrlCmdDfpRecordChannelRegisters_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpInternalLcdOverdrive(pDispCommon, pParams) dispcmnCtrlCmdDfpInternalLcdOverdrive_DISPATCH(pDispCommon, pParams) +#define dispcmnCtrlCmdSystemExecuteAcpiMethod(pDispCommon, pAcpiMethodParams) dispcmnCtrlCmdSystemExecuteAcpiMethod_DISPATCH(pDispCommon, pAcpiMethodParams) +#define dispcmnCtrlCmdSystemGetAcpiIdMap(pDispCommon, pAcpiIdMapParams) dispcmnCtrlCmdSystemGetAcpiIdMap_DISPATCH(pDispCommon, pAcpiIdMapParams) +#define dispcmnCtrlCmdSpecificSetAcpiIdMapping(pDispCommon, pParams) dispcmnCtrlCmdSpecificSetAcpiIdMapping_DISPATCH(pDispCommon, pParams) +#define dispcmnCtrlCmdSpecificGetAcpiDodDisplayPortAttachment(pDispCommon, pParams) dispcmnCtrlCmdSpecificGetAcpiDodDisplayPortAttachment_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSystemGetCapsV2(pDispCommon, pCapsParams) dispcmnCtrlCmdSystemGetCapsV2_DISPATCH(pDispCommon, pCapsParams) #define dispcmnCtrlCmdSystemGetNumHeads(pDispCommon, pNumHeadsParams) dispcmnCtrlCmdSystemGetNumHeads_DISPATCH(pDispCommon, pNumHeadsParams) #define dispcmnCtrlCmdSystemGetScanline(pDispCommon, pScanlineParams) dispcmnCtrlCmdSystemGetScanline_DISPATCH(pDispCommon, pScanlineParams) @@ -1526,6 +1578,7 @@ NV_STATUS __nvoc_objCreate_DispCommon(DispCommon**, Dynamic*, NvU32, struct CALL #define dispcmnCtrlCmdSpecificIsDirectmodeDisplay(pDispCommon, pParams) dispcmnCtrlCmdSpecificIsDirectmodeDisplay_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSpecificSetHdmiFrlCapacityComputation(pDispCommon, pParams) dispcmnCtrlCmdSpecificSetHdmiFrlCapacityComputation_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSpecificDispI2cReadWrite(pDispCommon, pParams) dispcmnCtrlCmdSpecificDispI2cReadWrite_DISPATCH(pDispCommon, pParams) +#define dispcmnCtrlCmdSpecificGetValidHeadWindowAssignment(pDispCommon, pParams) dispcmnCtrlCmdSpecificGetValidHeadWindowAssignment_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpGetInfo(pDispCommon, pParams) dispcmnCtrlCmdDfpGetInfo_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpGetDisplayportDongleInfo(pDispCommon, pParams) dispcmnCtrlCmdDfpGetDisplayportDongleInfo_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpSetEldAudioCaps(pDispCommon, pEldAudioCapsParams) dispcmnCtrlCmdDfpSetEldAudioCaps_DISPATCH(pDispCommon, pEldAudioCapsParams) @@ -1587,6 +1640,7 @@ NV_STATUS __nvoc_objCreate_DispCommon(DispCommon**, Dynamic*, NvU32, struct CALL #define dispcmnAddAdditionalDependants(pClient, pResource, pReference) dispcmnAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define dispcmnPreDestruct(pResource) dispcmnPreDestruct_DISPATCH(pResource) #define dispcmnUnmapFrom(pResource, pParams) dispcmnUnmapFrom_DISPATCH(pResource, pParams) +#define dispcmnIsDuplicate(pResource, hMemory, pDuplicate) dispcmnIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define dispcmnGetNotificationListPtr(pNotifier) dispcmnGetNotificationListPtr_DISPATCH(pNotifier) #define dispcmnControl_Epilogue(pDisplayApi, pCallContext, pRsParams) dispcmnControl_Epilogue_DISPATCH(pDisplayApi, pCallContext, pRsParams) #define dispcmnGetNotificationShare(pNotifier) dispcmnGetNotificationShare_DISPATCH(pNotifier) @@ -1605,6 +1659,12 @@ static inline NV_STATUS dispcmnCtrlCmdSystemGetVblankEnable_DISPATCH(struct Disp return pDispCommon->__dispcmnCtrlCmdSystemGetVblankEnable__(pDispCommon, pVBEnableParams); } +NV_STATUS dispcmnCtrlCmdSystemCheckSidebandSrSupport_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdSystemCheckSidebandSrSupport_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdSystemCheckSidebandSrSupport__(pDispCommon, pParams); +} + NV_STATUS dispcmnCtrlCmdSystemGetInternalDisplays_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS *pInternalDisplaysParams); static inline NV_STATUS dispcmnCtrlCmdSystemGetInternalDisplays_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS *pInternalDisplaysParams) { @@ -1665,6 +1725,18 @@ static inline NV_STATUS dispcmnCtrlCmdDpSetEcf_DISPATCH(struct DispCommon *pDisp return pDispCommon->__dispcmnCtrlCmdDpSetEcf__(pDispCommon, pCtrlEcfParams); } +NV_STATUS dispcmnCtrlCmdSpecificGetBacklightBrightness_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS *pAllHeadMaskParams); + +static inline NV_STATUS dispcmnCtrlCmdSpecificGetBacklightBrightness_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS *pAllHeadMaskParams) { + return pDispCommon->__dispcmnCtrlCmdSpecificGetBacklightBrightness__(pDispCommon, pAllHeadMaskParams); +} + +NV_STATUS dispcmnCtrlCmdSpecificSetBacklightBrightness_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdSpecificSetBacklightBrightness_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdSpecificSetBacklightBrightness__(pDispCommon, pParams); +} + NV_STATUS dispcmnCtrlCmdDfpSwitchDispMux_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS *pParams); static inline NV_STATUS dispcmnCtrlCmdDfpSwitchDispMux_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS *pParams) { @@ -1701,6 +1773,30 @@ static inline NV_STATUS dispcmnCtrlCmdDfpInternalLcdOverdrive_DISPATCH(struct Di return pDispCommon->__dispcmnCtrlCmdDfpInternalLcdOverdrive__(pDispCommon, pParams); } +NV_STATUS dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS *pAcpiMethodParams); + +static inline NV_STATUS dispcmnCtrlCmdSystemExecuteAcpiMethod_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS *pAcpiMethodParams) { + return pDispCommon->__dispcmnCtrlCmdSystemExecuteAcpiMethod__(pDispCommon, pAcpiMethodParams); +} + +NV_STATUS dispcmnCtrlCmdSystemGetAcpiIdMap_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS *pAcpiIdMapParams); + +static inline NV_STATUS dispcmnCtrlCmdSystemGetAcpiIdMap_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_GET_ACPI_ID_MAP_PARAMS *pAcpiIdMapParams) { + return pDispCommon->__dispcmnCtrlCmdSystemGetAcpiIdMap__(pDispCommon, pAcpiIdMapParams); +} + +NV_STATUS dispcmnCtrlCmdSpecificSetAcpiIdMapping_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_SET_ACPI_ID_MAPPING_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdSpecificSetAcpiIdMapping_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_SET_ACPI_ID_MAPPING_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdSpecificSetAcpiIdMapping__(pDispCommon, pParams); +} + +NV_STATUS dispcmnCtrlCmdSpecificGetAcpiDodDisplayPortAttachment_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdSpecificGetAcpiDodDisplayPortAttachment_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_GET_ACPI_DOD_DISPLAY_PORT_ATTACHMENT_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdSpecificGetAcpiDodDisplayPortAttachment__(pDispCommon, pParams); +} + NV_STATUS dispcmnCtrlCmdSystemGetCapsV2_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_GET_CAPS_V2_PARAMS *pCapsParams); static inline NV_STATUS dispcmnCtrlCmdSystemGetCapsV2_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_GET_CAPS_V2_PARAMS *pCapsParams) { @@ -1959,6 +2055,12 @@ static inline NV_STATUS dispcmnCtrlCmdSpecificDispI2cReadWrite_DISPATCH(struct D return pDispCommon->__dispcmnCtrlCmdSpecificDispI2cReadWrite__(pDispCommon, pParams); } +NV_STATUS dispcmnCtrlCmdSpecificGetValidHeadWindowAssignment_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdSpecificGetValidHeadWindowAssignment_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdSpecificGetValidHeadWindowAssignment__(pDispCommon, pParams); +} + NV_STATUS dispcmnCtrlCmdDfpGetInfo_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_DFP_GET_INFO_PARAMS *pParams); static inline NV_STATUS dispcmnCtrlCmdDfpGetInfo_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_DFP_GET_INFO_PARAMS *pParams) { @@ -2291,6 +2393,10 @@ static inline NV_STATUS dispcmnUnmapFrom_DISPATCH(struct DispCommon *pResource, return pResource->__dispcmnUnmapFrom__(pResource, pParams); } +static inline NV_STATUS dispcmnIsDuplicate_DISPATCH(struct DispCommon *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__dispcmnIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline PEVENTNOTIFICATION *dispcmnGetNotificationListPtr_DISPATCH(struct DispCommon *pNotifier) { return pNotifier->__dispcmnGetNotificationListPtr__(pNotifier); } @@ -2316,10 +2422,13 @@ static inline NV_STATUS dispcmnGetOrAllocNotifShare_DISPATCH(struct DispCommon * } NV_STATUS dispcmnConstruct_IMPL(struct DispCommon *arg_pDispCommon, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_dispcmnConstruct(arg_pDispCommon, arg_pCallContext, arg_pParams) dispcmnConstruct_IMPL(arg_pDispCommon, arg_pCallContext, arg_pParams) NV_STATUS dispcmnGetByHandle_IMPL(struct RsClient *pClient, NvHandle hDispCommon, struct DispCommon **ppDispCommon); + #define dispcmnGetByHandle(pClient, hDispCommon, ppDispCommon) dispcmnGetByHandle_IMPL(pClient, hDispCommon, ppDispCommon) void dispcmnGetByDevice_IMPL(struct RsClient *pClient, NvHandle hDevice, struct DispCommon **ppDispCommon); + #define dispcmnGetByDevice(pClient, hDevice, ppDispCommon) dispcmnGetByDevice_IMPL(pClient, hDevice, ppDispCommon) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_disp_sf_user_nvoc.c b/src/nvidia/generated/g_disp_sf_user_nvoc.c index c7c3a33c1..279760081 100644 --- a/src/nvidia/generated/g_disp_sf_user_nvoc.c +++ b/src/nvidia/generated/g_disp_sf_user_nvoc.c @@ -165,6 +165,10 @@ static NV_STATUS __nvoc_thunk_RsResource_dispsfUnmapFrom(struct DispSfUser *pRes return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_dispsfIsDuplicate(struct DispSfUser *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_dispsfControl_Epilogue(struct DispSfUser *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RmResource.offset), pCallContext, pParams); } @@ -257,6 +261,8 @@ static void __nvoc_init_funcTable_DispSfUser_1(DispSfUser *pThis) { pThis->__dispsfUnmapFrom__ = &__nvoc_thunk_RsResource_dispsfUnmapFrom; + pThis->__dispsfIsDuplicate__ = &__nvoc_thunk_RsResource_dispsfIsDuplicate; + pThis->__dispsfControl_Epilogue__ = &__nvoc_thunk_RmResource_dispsfControl_Epilogue; pThis->__dispsfControlLookup__ = &__nvoc_thunk_RsResource_dispsfControlLookup; diff --git a/src/nvidia/generated/g_disp_sf_user_nvoc.h b/src/nvidia/generated/g_disp_sf_user_nvoc.h index 0baf74e72..c735a4d80 100644 --- a/src/nvidia/generated/g_disp_sf_user_nvoc.h +++ b/src/nvidia/generated/g_disp_sf_user_nvoc.h @@ -78,6 +78,7 @@ struct DispSfUser { NV_STATUS (*__dispsfInternalControlForward__)(struct DispSfUser *, NvU32, void *, NvU32); void (*__dispsfPreDestruct__)(struct DispSfUser *); NV_STATUS (*__dispsfUnmapFrom__)(struct DispSfUser *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__dispsfIsDuplicate__)(struct DispSfUser *, NvHandle, NvBool *); void (*__dispsfControl_Epilogue__)(struct DispSfUser *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dispsfControlLookup__)(struct DispSfUser *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__dispsfMap__)(struct DispSfUser *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -132,6 +133,7 @@ NV_STATUS __nvoc_objCreate_DispSfUser(DispSfUser**, Dynamic*, NvU32, struct CALL #define dispsfInternalControlForward(pGpuResource, command, pParams, size) dispsfInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define dispsfPreDestruct(pResource) dispsfPreDestruct_DISPATCH(pResource) #define dispsfUnmapFrom(pResource, pParams) dispsfUnmapFrom_DISPATCH(pResource, pParams) +#define dispsfIsDuplicate(pResource, hMemory, pDuplicate) dispsfIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define dispsfControl_Epilogue(pResource, pCallContext, pParams) dispsfControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define dispsfControlLookup(pResource, pParams, ppEntry) dispsfControlLookup_DISPATCH(pResource, pParams, ppEntry) #define dispsfMap(pGpuResource, pCallContext, pParams, pCpuMapping) dispsfMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -210,6 +212,10 @@ static inline NV_STATUS dispsfUnmapFrom_DISPATCH(struct DispSfUser *pResource, R return pResource->__dispsfUnmapFrom__(pResource, pParams); } +static inline NV_STATUS dispsfIsDuplicate_DISPATCH(struct DispSfUser *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__dispsfIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void dispsfControl_Epilogue_DISPATCH(struct DispSfUser *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__dispsfControl_Epilogue__(pResource, pCallContext, pParams); } @@ -227,6 +233,7 @@ static inline NvBool dispsfAccessCallback_DISPATCH(struct DispSfUser *pResource, } NV_STATUS dispsfConstruct_IMPL(struct DispSfUser *arg_pDispSfUser, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_dispsfConstruct(arg_pDispSfUser, arg_pCallContext, arg_pParams) dispsfConstruct_IMPL(arg_pDispSfUser, arg_pCallContext, arg_pParams) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_dispsw_nvoc.c b/src/nvidia/generated/g_dispsw_nvoc.c index 2bd90294e..1e8656595 100644 --- a/src/nvidia/generated/g_dispsw_nvoc.c +++ b/src/nvidia/generated/g_dispsw_nvoc.c @@ -220,6 +220,10 @@ static void __nvoc_thunk_RsResource_dispswPreDestruct(struct DispSwObject *pReso resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObject_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_RsResource_dispswIsDuplicate(struct DispSwObject *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObject_RsResource.offset), hMemory, pDuplicate); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_dispswGetNotificationListPtr(struct DispSwObject *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DispSwObject_Notifier.offset)); } @@ -310,10 +314,7 @@ static void __nvoc_init_funcTable_DispSwObject_1(DispSwObject *pThis, RmHalspecO PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // Hal function -- dispswGetSwMethods - if (0) - { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { pThis->__dispswGetSwMethods__ = &dispswGetSwMethods_46f6a7; } @@ -372,6 +373,8 @@ static void __nvoc_init_funcTable_DispSwObject_1(DispSwObject *pThis, RmHalspecO pThis->__dispswPreDestruct__ = &__nvoc_thunk_RsResource_dispswPreDestruct; + pThis->__dispswIsDuplicate__ = &__nvoc_thunk_RsResource_dispswIsDuplicate; + pThis->__dispswGetNotificationListPtr__ = &__nvoc_thunk_Notifier_dispswGetNotificationListPtr; pThis->__dispswGetNotificationShare__ = &__nvoc_thunk_Notifier_dispswGetNotificationShare; diff --git a/src/nvidia/generated/g_dispsw_nvoc.h b/src/nvidia/generated/g_dispsw_nvoc.h index a06e4d4de..c9c56c45b 100644 --- a/src/nvidia/generated/g_dispsw_nvoc.h +++ b/src/nvidia/generated/g_dispsw_nvoc.h @@ -148,6 +148,7 @@ struct DispSwObject { NV_STATUS (*__dispswUnregisterEvent__)(struct DispSwObject *, NvHandle, NvHandle, NvHandle, NvHandle); NvBool (*__dispswCanCopy__)(struct DispSwObject *); void (*__dispswPreDestruct__)(struct DispSwObject *); + NV_STATUS (*__dispswIsDuplicate__)(struct DispSwObject *, NvHandle, NvBool *); PEVENTNOTIFICATION *(*__dispswGetNotificationListPtr__)(struct DispSwObject *); struct NotifShare *(*__dispswGetNotificationShare__)(struct DispSwObject *); NV_STATUS (*__dispswMap__)(struct DispSwObject *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -213,6 +214,7 @@ NV_STATUS __nvoc_objCreate_DispSwObject(DispSwObject**, Dynamic*, NvU32, CALL_CO #define dispswUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) dispswUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define dispswCanCopy(pResource) dispswCanCopy_DISPATCH(pResource) #define dispswPreDestruct(pResource) dispswPreDestruct_DISPATCH(pResource) +#define dispswIsDuplicate(pResource, hMemory, pDuplicate) dispswIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define dispswGetNotificationListPtr(pNotifier) dispswGetNotificationListPtr_DISPATCH(pNotifier) #define dispswGetNotificationShare(pNotifier) dispswGetNotificationShare_DISPATCH(pNotifier) #define dispswMap(pGpuResource, pCallContext, pParams, pCpuMapping) dispswMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -327,6 +329,10 @@ static inline void dispswPreDestruct_DISPATCH(struct DispSwObject *pResource) { pResource->__dispswPreDestruct__(pResource); } +static inline NV_STATUS dispswIsDuplicate_DISPATCH(struct DispSwObject *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__dispswIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline PEVENTNOTIFICATION *dispswGetNotificationListPtr_DISPATCH(struct DispSwObject *pNotifier) { return pNotifier->__dispswGetNotificationListPtr__(pNotifier); } @@ -344,8 +350,10 @@ static inline NV_STATUS dispswGetOrAllocNotifShare_DISPATCH(struct DispSwObject } NV_STATUS dispswConstruct_IMPL(struct DispSwObject *arg_pDispSw, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_dispswConstruct(arg_pDispSw, arg_pCallContext, arg_pParams) dispswConstruct_IMPL(arg_pDispSw, arg_pCallContext, arg_pParams) void dispswDestruct_IMPL(struct DispSwObject *pDispSw); + #define __nvoc_dispswDestruct(pDispSw) dispswDestruct_IMPL(pDispSw) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_eng_desc_nvoc.h b/src/nvidia/generated/g_eng_desc_nvoc.h index affe9030b..074b22169 100644 --- a/src/nvidia/generated/g_eng_desc_nvoc.h +++ b/src/nvidia/generated/g_eng_desc_nvoc.h @@ -212,16 +212,16 @@ typedef struct OBJHSHUBMANAGER OBJHSHUBMANAGER; #endif /* __nvoc_class_id_OBJHSHUBMANAGER */ -struct OBJHSHUB; +struct Hshub; -#ifndef __NVOC_CLASS_OBJHSHUB_TYPEDEF__ -#define __NVOC_CLASS_OBJHSHUB_TYPEDEF__ -typedef struct OBJHSHUB OBJHSHUB; -#endif /* __NVOC_CLASS_OBJHSHUB_TYPEDEF__ */ +#ifndef __NVOC_CLASS_Hshub_TYPEDEF__ +#define __NVOC_CLASS_Hshub_TYPEDEF__ +typedef struct Hshub Hshub; +#endif /* __NVOC_CLASS_Hshub_TYPEDEF__ */ -#ifndef __nvoc_class_id_OBJHSHUB -#define __nvoc_class_id_OBJHSHUB 0x43d089 -#endif /* __nvoc_class_id_OBJHSHUB */ +#ifndef __nvoc_class_id_Hshub +#define __nvoc_class_id_Hshub 0x5b3331 +#endif /* __nvoc_class_id_Hshub */ struct OBJTMR; @@ -536,16 +536,16 @@ typedef struct OBJDPU OBJDPU; #endif /* __nvoc_class_id_OBJDPU */ -struct OBJFAN; +struct Fan; -#ifndef __NVOC_CLASS_OBJFAN_TYPEDEF__ -#define __NVOC_CLASS_OBJFAN_TYPEDEF__ -typedef struct OBJFAN OBJFAN; -#endif /* __NVOC_CLASS_OBJFAN_TYPEDEF__ */ +#ifndef __NVOC_CLASS_Fan_TYPEDEF__ +#define __NVOC_CLASS_Fan_TYPEDEF__ +typedef struct Fan Fan; +#endif /* __NVOC_CLASS_Fan_TYPEDEF__ */ -#ifndef __nvoc_class_id_OBJFAN -#define __nvoc_class_id_OBJFAN 0xda9ade -#endif /* __nvoc_class_id_OBJFAN */ +#ifndef __nvoc_class_id_Fan +#define __nvoc_class_id_Fan 0xadd018 +#endif /* __nvoc_class_id_Fan */ struct DisplayInstanceMemory; @@ -608,16 +608,16 @@ typedef struct OBJHDA OBJHDA; #endif /* __nvoc_class_id_OBJHDA */ -struct OBJI2C; +struct I2c; -#ifndef __NVOC_CLASS_OBJI2C_TYPEDEF__ -#define __NVOC_CLASS_OBJI2C_TYPEDEF__ -typedef struct OBJI2C OBJI2C; -#endif /* __NVOC_CLASS_OBJI2C_TYPEDEF__ */ +#ifndef __NVOC_CLASS_I2c_TYPEDEF__ +#define __NVOC_CLASS_I2c_TYPEDEF__ +typedef struct I2c I2c; +#endif /* __NVOC_CLASS_I2c_TYPEDEF__ */ -#ifndef __nvoc_class_id_OBJI2C -#define __nvoc_class_id_OBJI2C 0x2bc374 -#endif /* __nvoc_class_id_OBJI2C */ +#ifndef __nvoc_class_id_I2c +#define __nvoc_class_id_I2c 0x48e035 +#endif /* __nvoc_class_id_I2c */ struct KernelRc; @@ -1361,7 +1361,7 @@ typedef struct KernelCcu KernelCcu; #define ENG_INVALID MKENGDESC(classId(OBJINVALID), 0) #define ENG_SW MKENGDESC(classId(OBJSWENG), 0) #define ENG_GPU MKENGDESC(classId(OBJGPU), 0) -#define ENG_FLCN MKENGDESC(classId(Falcon), 0) +#define ENG_FLCN MKENGDESC(classId(Falcon), 0) #define ENG_MC MKENGDESC(classId(OBJMC), 0) #define ENG_KERNEL_MC MKENGDESC(classId(KernelMc), 0) #define ENG_PRIV_RING MKENGDESC(classId(PrivRing), 0) @@ -1389,13 +1389,13 @@ typedef struct KernelCcu KernelCcu; #define ENG_KERNEL_DISPLAY MKENGDESC(classId(KernelDisplay), 0) #define ENG_DISP MKENGDESC(classId(OBJDISP), 0) #define ENG_DPU MKENGDESC(classId(OBJDPU), 0) -#define ENG_FAN MKENGDESC(classId(OBJFAN), 0) +#define ENG_FAN MKENGDESC(classId(Fan), 0) #define ENG_INST MKENGDESC(classId(DisplayInstanceMemory), 0) #define ENG_KERNEL_HEAD MKENGDESC(classId(KernelHead), 0) #define ENG_VOLT MKENGDESC(classId(OBJVOLT), 0) #define ENG_INTR MKENGDESC(classId(Intr), 0) #define ENG_HDA MKENGDESC(classId(OBJHDA), 0) -#define ENG_I2C MKENGDESC(classId(OBJI2C), 0) +#define ENG_I2C MKENGDESC(classId(I2c), 0) #define ENG_KERNEL_RC MKENGDESC(classId(KernelRc), 0) #define ENG_RC MKENGDESC(classId(OBJRC), 0) #define ENG_SOR MKENGDESC(classId(OBJSOR), 0) @@ -1441,7 +1441,7 @@ typedef struct KernelCcu KernelCcu; #define ENG_KERNEL_SEC2 MKENGDESC(classId(KernelSec2), 0) #define ENG_DISPMACRO MKENGDESC(classId(OBJDISPMACRO), 0) #define ENG_NNE MKENGDESC(classId(OBJNNE), 0) -#define ENG_SMBPBI MKENGDESC(classId(Smbpbi), 0) +#define ENG_SMBPBI MKENGDESC(classId(Smbpbi), 0) #define ENG_DSI MKENGDESC(classId(OBJDSI), 0) #define ENG_DCECLIENTRM MKENGDESC(classId(OBJDCECLIENTRM), 0) #define ENG_DCB MKENGDESC(classId(OBJDCB), 0) @@ -1499,9 +1499,9 @@ typedef struct KernelCcu KernelCcu; #define GET_IOCTRL_IDX(engDesc) ENGDESC_FIELD(engDesc, _INST) // Indexed HSHUB engine tag reference -#define ENG_HSHUB(x) MKENGDESC(classId(OBJHSHUB), x) +#define ENG_HSHUB(x) MKENGDESC(classId(Hshub), x) #define ENG_HSHUB__SIZE_1 5 -#define IS_HSHUB(engDesc) (ENGDESC_FIELD(engDesc, _CLASS) == classId(OBJHSHUB)) +#define IS_HSHUB(engDesc) (ENGDESC_FIELD(engDesc, _CLASS) == classId(Hshub)) #define GET_HSHUB_IDX(engDesc) ENGDESC_FIELD(engDesc, _INST) // Indexed IOCTRL engine tag reference diff --git a/src/nvidia/generated/g_eng_state_nvoc.h b/src/nvidia/generated/g_eng_state_nvoc.h index f9853bde6..d45b02903 100644 --- a/src/nvidia/generated/g_eng_state_nvoc.h +++ b/src/nvidia/generated/g_eng_state_nvoc.h @@ -293,6 +293,7 @@ static inline NvBool engstateIsPresent_DISPATCH(POBJGPU pGpu, POBJENGSTATE pEngs } NV_STATUS engstateConstructBase_IMPL(struct OBJENGSTATE *arg0, struct OBJGPU *arg1, ENGDESCRIPTOR arg2); + #ifdef __nvoc_eng_state_h_disabled static inline NV_STATUS engstateConstructBase(struct OBJENGSTATE *arg0, struct OBJGPU *arg1, ENGDESCRIPTOR arg2) { NV_ASSERT_FAILED_PRECOMP("OBJENGSTATE was disabled!"); @@ -303,6 +304,7 @@ static inline NV_STATUS engstateConstructBase(struct OBJENGSTATE *arg0, struct O #endif //__nvoc_eng_state_h_disabled void engstateLogStateTransitionPre_IMPL(struct OBJENGSTATE *arg0, ENGSTATE_STATE arg1, ENGSTATE_TRANSITION_DATA *arg2); + #ifdef __nvoc_eng_state_h_disabled static inline void engstateLogStateTransitionPre(struct OBJENGSTATE *arg0, ENGSTATE_STATE arg1, ENGSTATE_TRANSITION_DATA *arg2) { NV_ASSERT_FAILED_PRECOMP("OBJENGSTATE was disabled!"); @@ -312,6 +314,7 @@ static inline void engstateLogStateTransitionPre(struct OBJENGSTATE *arg0, ENGST #endif //__nvoc_eng_state_h_disabled void engstateLogStateTransitionPost_IMPL(struct OBJENGSTATE *arg0, ENGSTATE_STATE arg1, ENGSTATE_TRANSITION_DATA *arg2); + #ifdef __nvoc_eng_state_h_disabled static inline void engstateLogStateTransitionPost(struct OBJENGSTATE *arg0, ENGSTATE_STATE arg1, ENGSTATE_TRANSITION_DATA *arg2) { NV_ASSERT_FAILED_PRECOMP("OBJENGSTATE was disabled!"); @@ -321,6 +324,7 @@ static inline void engstateLogStateTransitionPost(struct OBJENGSTATE *arg0, ENGS #endif //__nvoc_eng_state_h_disabled const char *engstateGetName_IMPL(struct OBJENGSTATE *arg0); + #ifdef __nvoc_eng_state_h_disabled static inline const char *engstateGetName(struct OBJENGSTATE *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJENGSTATE was disabled!"); @@ -331,8 +335,10 @@ static inline const char *engstateGetName(struct OBJENGSTATE *arg0) { #endif //__nvoc_eng_state_h_disabled void engstateDestruct_IMPL(POBJENGSTATE pEngstate); + #define __nvoc_engstateDestruct(pEngstate) engstateDestruct_IMPL(pEngstate) NV_STATUS engstateStatePreInit_IMPL(POBJGPU pGpu, POBJENGSTATE pEngstate); + #ifdef __nvoc_eng_state_h_disabled static inline NV_STATUS engstateStatePreInit(POBJGPU pGpu, POBJENGSTATE pEngstate) { NV_ASSERT_FAILED_PRECOMP("OBJENGSTATE was disabled!"); @@ -343,6 +349,7 @@ static inline NV_STATUS engstateStatePreInit(POBJGPU pGpu, POBJENGSTATE pEngstat #endif //__nvoc_eng_state_h_disabled NV_STATUS engstateStateInit_IMPL(POBJGPU pGpu, POBJENGSTATE pEngstate); + #ifdef __nvoc_eng_state_h_disabled static inline NV_STATUS engstateStateInit(POBJGPU pGpu, POBJENGSTATE pEngstate) { NV_ASSERT_FAILED_PRECOMP("OBJENGSTATE was disabled!"); @@ -353,6 +360,7 @@ static inline NV_STATUS engstateStateInit(POBJGPU pGpu, POBJENGSTATE pEngstate) #endif //__nvoc_eng_state_h_disabled ENGDESCRIPTOR engstateGetDescriptor_IMPL(POBJENGSTATE pEngstate); + #ifdef __nvoc_eng_state_h_disabled static inline ENGDESCRIPTOR engstateGetDescriptor(POBJENGSTATE pEngstate) { NV_ASSERT_FAILED_PRECOMP("OBJENGSTATE was disabled!"); @@ -365,6 +373,7 @@ static inline ENGDESCRIPTOR engstateGetDescriptor(POBJENGSTATE pEngstate) { #endif //__nvoc_eng_state_h_disabled struct OBJFIFO *engstateGetFifo_IMPL(POBJENGSTATE pEngstate); + #ifdef __nvoc_eng_state_h_disabled static inline struct OBJFIFO *engstateGetFifo(POBJENGSTATE pEngstate) { NV_ASSERT_FAILED_PRECOMP("OBJENGSTATE was disabled!"); diff --git a/src/nvidia/generated/g_event_buffer_nvoc.c b/src/nvidia/generated/g_event_buffer_nvoc.c index 7ac02b9bc..398e706f6 100644 --- a/src/nvidia/generated/g_event_buffer_nvoc.c +++ b/src/nvidia/generated/g_event_buffer_nvoc.c @@ -140,6 +140,10 @@ static NV_STATUS __nvoc_thunk_RsResource_eventbufferUnmapFrom(struct EventBuffer return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_eventbufferIsDuplicate(struct EventBuffer *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_eventbufferControl_Epilogue(struct EventBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RmResource.offset), pCallContext, pParams); } @@ -308,6 +312,8 @@ static void __nvoc_init_funcTable_EventBuffer_1(EventBuffer *pThis) { pThis->__eventbufferUnmapFrom__ = &__nvoc_thunk_RsResource_eventbufferUnmapFrom; + pThis->__eventbufferIsDuplicate__ = &__nvoc_thunk_RsResource_eventbufferIsDuplicate; + pThis->__eventbufferControl_Epilogue__ = &__nvoc_thunk_RmResource_eventbufferControl_Epilogue; pThis->__eventbufferControlLookup__ = &__nvoc_thunk_RsResource_eventbufferControlLookup; diff --git a/src/nvidia/generated/g_event_buffer_nvoc.h b/src/nvidia/generated/g_event_buffer_nvoc.h index 6a7e12c80..8a0549319 100644 --- a/src/nvidia/generated/g_event_buffer_nvoc.h +++ b/src/nvidia/generated/g_event_buffer_nvoc.h @@ -99,6 +99,7 @@ struct EventBuffer { NV_STATUS (*__eventbufferMapTo__)(struct EventBuffer *, RS_RES_MAP_TO_PARAMS *); void (*__eventbufferPreDestruct__)(struct EventBuffer *); NV_STATUS (*__eventbufferUnmapFrom__)(struct EventBuffer *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__eventbufferIsDuplicate__)(struct EventBuffer *, NvHandle, NvBool *); void (*__eventbufferControl_Epilogue__)(struct EventBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__eventbufferControlLookup__)(struct EventBuffer *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__eventbufferMap__)(struct EventBuffer *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -171,6 +172,7 @@ NV_STATUS __nvoc_objCreate_EventBuffer(EventBuffer**, Dynamic*, NvU32, struct CA #define eventbufferMapTo(pResource, pParams) eventbufferMapTo_DISPATCH(pResource, pParams) #define eventbufferPreDestruct(pResource) eventbufferPreDestruct_DISPATCH(pResource) #define eventbufferUnmapFrom(pResource, pParams) eventbufferUnmapFrom_DISPATCH(pResource, pParams) +#define eventbufferIsDuplicate(pResource, hMemory, pDuplicate) eventbufferIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define eventbufferControl_Epilogue(pResource, pCallContext, pParams) eventbufferControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define eventbufferControlLookup(pResource, pParams, ppEntry) eventbufferControlLookup_DISPATCH(pResource, pParams, ppEntry) #define eventbufferMap(pResource, pCallContext, pParams, pCpuMapping) eventbufferMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) @@ -255,6 +257,10 @@ static inline NV_STATUS eventbufferUnmapFrom_DISPATCH(struct EventBuffer *pResou return pResource->__eventbufferUnmapFrom__(pResource, pParams); } +static inline NV_STATUS eventbufferIsDuplicate_DISPATCH(struct EventBuffer *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__eventbufferIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void eventbufferControl_Epilogue_DISPATCH(struct EventBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__eventbufferControl_Epilogue__(pResource, pCallContext, pParams); } @@ -272,8 +278,10 @@ static inline NvBool eventbufferAccessCallback_DISPATCH(struct EventBuffer *pRes } NV_STATUS eventbufferConstruct_IMPL(struct EventBuffer *arg_pEventBuffer, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_eventbufferConstruct(arg_pEventBuffer, arg_pCallContext, arg_pParams) eventbufferConstruct_IMPL(arg_pEventBuffer, arg_pCallContext, arg_pParams) void eventbufferDestruct_IMPL(struct EventBuffer *pEventBuffer); + #define __nvoc_eventbufferDestruct(pEventBuffer) eventbufferDestruct_IMPL(pEventBuffer) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_event_nvoc.c b/src/nvidia/generated/g_event_nvoc.c index 570e4f2b8..d2b8d9e02 100644 --- a/src/nvidia/generated/g_event_nvoc.c +++ b/src/nvidia/generated/g_event_nvoc.c @@ -295,6 +295,10 @@ static NV_STATUS __nvoc_thunk_RsResource_eventUnmapFrom(struct Event *pResource, return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_eventIsDuplicate(struct Event *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_eventControl_Epilogue(struct Event *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RmResource.offset), pCallContext, pParams); } @@ -378,6 +382,8 @@ static void __nvoc_init_funcTable_Event_1(Event *pThis) { pThis->__eventUnmapFrom__ = &__nvoc_thunk_RsResource_eventUnmapFrom; + pThis->__eventIsDuplicate__ = &__nvoc_thunk_RsResource_eventIsDuplicate; + pThis->__eventControl_Epilogue__ = &__nvoc_thunk_RmResource_eventControl_Epilogue; pThis->__eventControlLookup__ = &__nvoc_thunk_RsResource_eventControlLookup; diff --git a/src/nvidia/generated/g_event_nvoc.h b/src/nvidia/generated/g_event_nvoc.h index ab8d3a0c5..38935b93e 100644 --- a/src/nvidia/generated/g_event_nvoc.h +++ b/src/nvidia/generated/g_event_nvoc.h @@ -39,6 +39,7 @@ extern "C" { #include "nvoc/prelude.h" #include "resserv/rs_server.h" #include "rmapi/resource.h" +#include "kernel/gpu/gpu_engine_type.h" typedef struct _def_system_event_queue SYSTEM_EVENTS_QUEUE; @@ -146,8 +147,10 @@ NV_STATUS __nvoc_objCreate_NotifShare(NotifShare**, Dynamic*, NvU32); __nvoc_objCreate_NotifShare((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) NV_STATUS shrnotifConstruct_IMPL(struct NotifShare *arg_pNotifShare); + #define __nvoc_shrnotifConstruct(arg_pNotifShare) shrnotifConstruct_IMPL(arg_pNotifShare) void shrnotifDestruct_IMPL(struct NotifShare *pNotifShare); + #define __nvoc_shrnotifDestruct(pNotifShare) shrnotifDestruct_IMPL(pNotifShare) #undef PRIVATE_FIELD @@ -182,6 +185,7 @@ struct Event { NV_STATUS (*__eventMapTo__)(struct Event *, RS_RES_MAP_TO_PARAMS *); void (*__eventPreDestruct__)(struct Event *); NV_STATUS (*__eventUnmapFrom__)(struct Event *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__eventIsDuplicate__)(struct Event *, NvHandle, NvBool *); void (*__eventControl_Epilogue__)(struct Event *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__eventControlLookup__)(struct Event *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__eventMap__)(struct Event *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -234,6 +238,7 @@ NV_STATUS __nvoc_objCreate_Event(Event**, Dynamic*, NvU32, struct CALL_CONTEXT * #define eventMapTo(pResource, pParams) eventMapTo_DISPATCH(pResource, pParams) #define eventPreDestruct(pResource) eventPreDestruct_DISPATCH(pResource) #define eventUnmapFrom(pResource, pParams) eventUnmapFrom_DISPATCH(pResource, pParams) +#define eventIsDuplicate(pResource, hMemory, pDuplicate) eventIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define eventControl_Epilogue(pResource, pCallContext, pParams) eventControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define eventControlLookup(pResource, pParams, ppEntry) eventControlLookup_DISPATCH(pResource, pParams, ppEntry) #define eventMap(pResource, pCallContext, pParams, pCpuMapping) eventMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) @@ -294,6 +299,10 @@ static inline NV_STATUS eventUnmapFrom_DISPATCH(struct Event *pResource, RS_RES_ return pResource->__eventUnmapFrom__(pResource, pParams); } +static inline NV_STATUS eventIsDuplicate_DISPATCH(struct Event *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__eventIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void eventControl_Epilogue_DISPATCH(struct Event *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__eventControl_Epilogue__(pResource, pCallContext, pParams); } @@ -311,10 +320,13 @@ static inline NvBool eventAccessCallback_DISPATCH(struct Event *pResource, struc } NV_STATUS eventConstruct_IMPL(struct Event *arg_pEvent, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_eventConstruct(arg_pEvent, arg_pCallContext, arg_pParams) eventConstruct_IMPL(arg_pEvent, arg_pCallContext, arg_pParams) void eventDestruct_IMPL(struct Event *pEvent); + #define __nvoc_eventDestruct(pEvent) eventDestruct_IMPL(pEvent) NV_STATUS eventInit_IMPL(struct Event *pEvent, struct CALL_CONTEXT *pCallContext, NvHandle hNotifierClient, NvHandle hNotifierResource, PEVENTNOTIFICATION **pppEventNotification); + #ifdef __nvoc_event_h_disabled static inline NV_STATUS eventInit(struct Event *pEvent, struct CALL_CONTEXT *pCallContext, NvHandle hNotifierClient, NvHandle hNotifierResource, PEVENTNOTIFICATION **pppEventNotification) { NV_ASSERT_FAILED_PRECOMP("Event was disabled!"); @@ -399,10 +411,13 @@ static inline NV_STATUS inotifyGetOrAllocNotifShare_DISPATCH(struct INotifier *p } NV_STATUS inotifyConstruct_IMPL(struct INotifier *arg_pNotifier, struct CALL_CONTEXT *arg_pCallContext); + #define __nvoc_inotifyConstruct(arg_pNotifier, arg_pCallContext) inotifyConstruct_IMPL(arg_pNotifier, arg_pCallContext) void inotifyDestruct_IMPL(struct INotifier *pNotifier); + #define __nvoc_inotifyDestruct(pNotifier) inotifyDestruct_IMPL(pNotifier) PEVENTNOTIFICATION inotifyGetNotificationList_IMPL(struct INotifier *pNotifier); + #ifdef __nvoc_event_h_disabled static inline PEVENTNOTIFICATION inotifyGetNotificationList(struct INotifier *pNotifier) { NV_ASSERT_FAILED_PRECOMP("INotifier was disabled!"); @@ -500,8 +515,10 @@ static inline NV_STATUS notifyGetOrAllocNotifShare_DISPATCH(struct Notifier *pNo } NV_STATUS notifyConstruct_IMPL(struct Notifier *arg_pNotifier, struct CALL_CONTEXT *arg_pCallContext); + #define __nvoc_notifyConstruct(arg_pNotifier, arg_pCallContext) notifyConstruct_IMPL(arg_pNotifier, arg_pCallContext) void notifyDestruct_IMPL(struct Notifier *pNotifier); + #define __nvoc_notifyDestruct(pNotifier) notifyDestruct_IMPL(pNotifier) #undef PRIVATE_FIELD @@ -517,9 +534,9 @@ NV_STATUS registerEventNotification(PEVENTNOTIFICATION*, NvHandle, NvHandle, NvH NV_STATUS unregisterEventNotification(PEVENTNOTIFICATION*, NvHandle, NvHandle, NvHandle); NV_STATUS unregisterEventNotificationWithData(PEVENTNOTIFICATION *, NvHandle, NvHandle, NvHandle, NvBool, NvP64); NV_STATUS bindEventNotificationToSubdevice(PEVENTNOTIFICATION, NvHandle, NvU32); -NV_STATUS engineNonStallIntrNotify(OBJGPU *, NvU32); +NV_STATUS engineNonStallIntrNotify(OBJGPU *, RM_ENGINE_TYPE); NV_STATUS notifyEvents(OBJGPU*, EVENTNOTIFICATION*, NvU32, NvU32, NvU32, NV_STATUS, NvU32); -NV_STATUS engineNonStallIntrNotifyEvent(OBJGPU *, NvU32, NvHandle); +NV_STATUS engineNonStallIntrNotifyEvent(OBJGPU *, RM_ENGINE_TYPE, NvHandle); #endif // _EVENT_H_ diff --git a/src/nvidia/generated/g_fabric_nvoc.h b/src/nvidia/generated/g_fabric_nvoc.h index cd0059ed6..fb07d7615 100644 --- a/src/nvidia/generated/g_fabric_nvoc.h +++ b/src/nvidia/generated/g_fabric_nvoc.h @@ -43,13 +43,39 @@ extern "C" { #include "core/core.h" #include "core/system.h" +#include "containers/multimap.h" +#include "containers/map.h" #include "class/cl000f.h" #include "ctrl/ctrl000f.h" + + // **************************************************************************** // Type Definitions // **************************************************************************** +typedef struct +{ + void *pData; +} FabricCacheMapEntry; + +MAKE_MAP(FabricCacheMap, FabricCacheMapEntry); + +typedef struct +{ + FabricCacheMap map; +} FabricCacheEntry; + +MAKE_MULTIMAP(FabricCache, FabricCacheEntry); + +#include "nvlink_inband_msg.h" + +NV_STATUS fabricInitInbandMsgHdr(nvlink_inband_msg_header_t *pMsgHdr, + NvU32 type, + NvU32 len); + +void fabricMulticastWaitOnTeamCleanupCallback(void *pCbData); + // // The Fabric object is used to encapsulate the NVLink fabric // @@ -64,6 +90,8 @@ struct Fabric { struct Object *__nvoc_pbase_Object; struct Fabric *__nvoc_pbase_Fabric; NvU32 flags; + PORT_MUTEX *pMulticastFabricOpsMutex; + FabricCache fabricMulticastCache; }; #ifndef __NVOC_CLASS_Fabric_TYPEDEF__ @@ -95,10 +123,13 @@ NV_STATUS __nvoc_objCreate_Fabric(Fabric**, Dynamic*, NvU32); __nvoc_objCreate_Fabric((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) NV_STATUS fabricConstruct_IMPL(struct Fabric *arg_pFabric); + #define __nvoc_fabricConstruct(arg_pFabric) fabricConstruct_IMPL(arg_pFabric) void fabricDestruct_IMPL(struct Fabric *pFabric); + #define __nvoc_fabricDestruct(pFabric) fabricDestruct_IMPL(pFabric) void fabricSetFmSessionFlags_IMPL(struct Fabric *pFabric, NvU32 flags); + #ifdef __nvoc_fabric_h_disabled static inline void fabricSetFmSessionFlags(struct Fabric *pFabric, NvU32 flags) { NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); @@ -108,6 +139,7 @@ static inline void fabricSetFmSessionFlags(struct Fabric *pFabric, NvU32 flags) #endif //__nvoc_fabric_h_disabled NvU32 fabricGetFmSessionFlags_IMPL(struct Fabric *pFabric); + #ifdef __nvoc_fabric_h_disabled static inline NvU32 fabricGetFmSessionFlags(struct Fabric *pFabric) { NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); @@ -117,6 +149,90 @@ static inline NvU32 fabricGetFmSessionFlags(struct Fabric *pFabric) { #define fabricGetFmSessionFlags(pFabric) fabricGetFmSessionFlags_IMPL(pFabric) #endif //__nvoc_fabric_h_disabled +void fabricMulticastFabricOpsMutexAcquire_IMPL(struct Fabric *pFabric); + +#ifdef __nvoc_fabric_h_disabled +static inline void fabricMulticastFabricOpsMutexAcquire(struct Fabric *pFabric) { + NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); +} +#else //__nvoc_fabric_h_disabled +#define fabricMulticastFabricOpsMutexAcquire(pFabric) fabricMulticastFabricOpsMutexAcquire_IMPL(pFabric) +#endif //__nvoc_fabric_h_disabled + +void fabricMulticastFabricOpsMutexRelease_IMPL(struct Fabric *pFabric); + +#ifdef __nvoc_fabric_h_disabled +static inline void fabricMulticastFabricOpsMutexRelease(struct Fabric *pFabric) { + NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); +} +#else //__nvoc_fabric_h_disabled +#define fabricMulticastFabricOpsMutexRelease(pFabric) fabricMulticastFabricOpsMutexRelease_IMPL(pFabric) +#endif //__nvoc_fabric_h_disabled + +NV_STATUS fabricMulticastSetupCacheInsertUnderLock_IMPL(struct Fabric *pFabric, NvU64 requesId, void *pData); + +#ifdef __nvoc_fabric_h_disabled +static inline NV_STATUS fabricMulticastSetupCacheInsertUnderLock(struct Fabric *pFabric, NvU64 requesId, void *pData) { + NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_fabric_h_disabled +#define fabricMulticastSetupCacheInsertUnderLock(pFabric, requesId, pData) fabricMulticastSetupCacheInsertUnderLock_IMPL(pFabric, requesId, pData) +#endif //__nvoc_fabric_h_disabled + +void fabricMulticastSetupCacheDeleteUnderLock_IMPL(struct Fabric *pFabric, NvU64 requesId); + +#ifdef __nvoc_fabric_h_disabled +static inline void fabricMulticastSetupCacheDeleteUnderLock(struct Fabric *pFabric, NvU64 requesId) { + NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); +} +#else //__nvoc_fabric_h_disabled +#define fabricMulticastSetupCacheDeleteUnderLock(pFabric, requesId) fabricMulticastSetupCacheDeleteUnderLock_IMPL(pFabric, requesId) +#endif //__nvoc_fabric_h_disabled + +void *fabricMulticastSetupCacheGetUnderLock_IMPL(struct Fabric *pFabric, NvU64 requestId); + +#ifdef __nvoc_fabric_h_disabled +static inline void *fabricMulticastSetupCacheGetUnderLock(struct Fabric *pFabric, NvU64 requestId) { + NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); + return NULL; +} +#else //__nvoc_fabric_h_disabled +#define fabricMulticastSetupCacheGetUnderLock(pFabric, requestId) fabricMulticastSetupCacheGetUnderLock_IMPL(pFabric, requestId) +#endif //__nvoc_fabric_h_disabled + +NV_STATUS fabricMulticastCleanupCacheInsertUnderLock_IMPL(struct Fabric *pFabric, NvU64 requesId, void *pData); + +#ifdef __nvoc_fabric_h_disabled +static inline NV_STATUS fabricMulticastCleanupCacheInsertUnderLock(struct Fabric *pFabric, NvU64 requesId, void *pData) { + NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_fabric_h_disabled +#define fabricMulticastCleanupCacheInsertUnderLock(pFabric, requesId, pData) fabricMulticastCleanupCacheInsertUnderLock_IMPL(pFabric, requesId, pData) +#endif //__nvoc_fabric_h_disabled + +void fabricMulticastCleanupCacheDeleteUnderLock_IMPL(struct Fabric *pFabric, NvU64 requesId); + +#ifdef __nvoc_fabric_h_disabled +static inline void fabricMulticastCleanupCacheDeleteUnderLock(struct Fabric *pFabric, NvU64 requesId) { + NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); +} +#else //__nvoc_fabric_h_disabled +#define fabricMulticastCleanupCacheDeleteUnderLock(pFabric, requesId) fabricMulticastCleanupCacheDeleteUnderLock_IMPL(pFabric, requesId) +#endif //__nvoc_fabric_h_disabled + +void *fabricMulticastCleanupCacheGetUnderLock_IMPL(struct Fabric *pFabric, NvU64 requestId); + +#ifdef __nvoc_fabric_h_disabled +static inline void *fabricMulticastCleanupCacheGetUnderLock(struct Fabric *pFabric, NvU64 requestId) { + NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); + return NULL; +} +#else //__nvoc_fabric_h_disabled +#define fabricMulticastCleanupCacheGetUnderLock(pFabric, requestId) fabricMulticastCleanupCacheGetUnderLock_IMPL(pFabric, requestId) +#endif //__nvoc_fabric_h_disabled + #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_fabric_vaspace_nvoc.c b/src/nvidia/generated/g_fabric_vaspace_nvoc.c index cfdf1601b..a83ca6905 100644 --- a/src/nvidia/generated/g_fabric_vaspace_nvoc.c +++ b/src/nvidia/generated/g_fabric_vaspace_nvoc.c @@ -170,6 +170,10 @@ static NV_STATUS __nvoc_thunk_OBJVASPACE_fabricvaspaceSetPteInfo(struct FABRIC_V return vaspaceSetPteInfo((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_FABRIC_VASPACE_OBJVASPACE.offset), pGpu, pParams); } +static NV_STATUS __nvoc_thunk_OBJVASPACE_fabricvaspaceFreeV2(struct FABRIC_VASPACE *pVAS, NvU64 vAddr, NvU64 *pSize) { + return vaspaceFreeV2((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_FABRIC_VASPACE_OBJVASPACE.offset), vAddr, pSize); +} + static NV_STATUS __nvoc_thunk_OBJVASPACE_fabricvaspaceGetPasid(struct FABRIC_VASPACE *pVAS, NvU32 *pPasid) { return vaspaceGetPasid((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_FABRIC_VASPACE_OBJVASPACE.offset), pPasid); } @@ -288,6 +292,8 @@ static void __nvoc_init_funcTable_FABRIC_VASPACE_1(FABRIC_VASPACE *pThis) { pThis->__fabricvaspaceSetPteInfo__ = &__nvoc_thunk_OBJVASPACE_fabricvaspaceSetPteInfo; + pThis->__fabricvaspaceFreeV2__ = &__nvoc_thunk_OBJVASPACE_fabricvaspaceFreeV2; + pThis->__fabricvaspaceGetPasid__ = &__nvoc_thunk_OBJVASPACE_fabricvaspaceGetPasid; pThis->__fabricvaspaceGetPageTableInfo__ = &__nvoc_thunk_OBJVASPACE_fabricvaspaceGetPageTableInfo; diff --git a/src/nvidia/generated/g_fabric_vaspace_nvoc.h b/src/nvidia/generated/g_fabric_vaspace_nvoc.h index 87fd835ee..d1001ea2e 100644 --- a/src/nvidia/generated/g_fabric_vaspace_nvoc.h +++ b/src/nvidia/generated/g_fabric_vaspace_nvoc.h @@ -48,6 +48,7 @@ extern "C" { #include "gpu/mem_mgr/heap.h" #include "gpu/mem_mgr/virt_mem_allocator.h" #include "ctrl/ctrl0080/ctrl0080dma.h" +#include "gpu/mem_mgr/mem_desc.h" #include "containers/list.h" #include "containers/map.h" @@ -60,6 +61,8 @@ typedef struct NvU64 offset; } FABRIC_VA_TO_GPA_MAP_NODE; +#define FABRIC_VASPACE_MAP_FLAGS_READ_ONLY NVBIT(0) + /*! * RM-registered/managed Fabric virtual address space. */ @@ -100,6 +103,7 @@ struct FABRIC_VASPACE { NvU64 (*__fabricvaspaceGetVaStart__)(struct FABRIC_VASPACE *); NV_STATUS (*__fabricvaspaceIncAllocRefCnt__)(struct FABRIC_VASPACE *, NvU64); NV_STATUS (*__fabricvaspaceSetPteInfo__)(struct FABRIC_VASPACE *, struct OBJGPU *, NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS *); + NV_STATUS (*__fabricvaspaceFreeV2__)(struct FABRIC_VASPACE *, NvU64, NvU64 *); NV_STATUS (*__fabricvaspaceGetPasid__)(struct FABRIC_VASPACE *, NvU32 *); NV_STATUS (*__fabricvaspaceGetPageTableInfo__)(struct FABRIC_VASPACE *, NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS *); NV_STATUS (*__fabricvaspaceReserveMempool__)(struct FABRIC_VASPACE *, struct OBJGPU *, NvHandle, NvU64, NvU64, NvU32); @@ -108,6 +112,10 @@ struct FABRIC_VASPACE { NvHandle hClient; NvHandle hDevice; NODE *pFabricVaToGpaMap; + NvU64 ucFabricBase; + NvU64 ucFabricLimit; + NvU64 ucFabricInUseSize; + NvU64 ucFabricFreeSize; NvU32 gfid; NvBool bRpcAlloc; }; @@ -166,6 +174,7 @@ NV_STATUS __nvoc_objCreate_FABRIC_VASPACE(FABRIC_VASPACE**, Dynamic*, NvU32); #define fabricvaspaceGetVaStart(pVAS) fabricvaspaceGetVaStart_DISPATCH(pVAS) #define fabricvaspaceIncAllocRefCnt(pVAS, vAddr) fabricvaspaceIncAllocRefCnt_DISPATCH(pVAS, vAddr) #define fabricvaspaceSetPteInfo(pVAS, pGpu, pParams) fabricvaspaceSetPteInfo_DISPATCH(pVAS, pGpu, pParams) +#define fabricvaspaceFreeV2(pVAS, vAddr, pSize) fabricvaspaceFreeV2_DISPATCH(pVAS, vAddr, pSize) #define fabricvaspaceGetPasid(pVAS, pPasid) fabricvaspaceGetPasid_DISPATCH(pVAS, pPasid) #define fabricvaspaceGetPageTableInfo(pVAS, pParams) fabricvaspaceGetPageTableInfo_DISPATCH(pVAS, pParams) #define fabricvaspaceReserveMempool(pVAS, pGpu, hClient, size, pageSizeLockMask, flags) fabricvaspaceReserveMempool_DISPATCH(pVAS, pGpu, hClient, size, pageSizeLockMask, flags) @@ -293,6 +302,10 @@ static inline NV_STATUS fabricvaspaceSetPteInfo_DISPATCH(struct FABRIC_VASPACE * return pVAS->__fabricvaspaceSetPteInfo__(pVAS, pGpu, pParams); } +static inline NV_STATUS fabricvaspaceFreeV2_DISPATCH(struct FABRIC_VASPACE *pVAS, NvU64 vAddr, NvU64 *pSize) { + return pVAS->__fabricvaspaceFreeV2__(pVAS, vAddr, pSize); +} + static inline NV_STATUS fabricvaspaceGetPasid_DISPATCH(struct FABRIC_VASPACE *pVAS, NvU32 *pPasid) { return pVAS->__fabricvaspaceGetPasid__(pVAS, pPasid); } @@ -305,9 +318,19 @@ static inline NV_STATUS fabricvaspaceReserveMempool_DISPATCH(struct FABRIC_VASPA return pVAS->__fabricvaspaceReserveMempool__(pVAS, pGpu, hClient, size, pageSizeLockMask, flags); } +static inline NvU64 fabricvaspaceGetUCFlaStart(struct FABRIC_VASPACE *pFabricVAS) { + return pFabricVAS->ucFabricBase; +} + +static inline NvU64 fabricvaspaceGetUCFlaLimit(struct FABRIC_VASPACE *pFabricVAS) { + return pFabricVAS->ucFabricLimit; +} + void fabricvaspaceDestruct_IMPL(struct FABRIC_VASPACE *pFabricVAS); + #define __nvoc_fabricvaspaceDestruct(pFabricVAS) fabricvaspaceDestruct_IMPL(pFabricVAS) NV_STATUS fabricvaspaceAllocNonContiguous_IMPL(struct FABRIC_VASPACE *pFabricVAS, NvU64 size, NvU64 align, NvU64 rangeLo, NvU64 rangeHi, NvU64 pageSize, VAS_ALLOC_FLAGS flags, NvU64 **ppAddr, NvU32 *pNumAddr); + #ifdef __nvoc_fabric_vaspace_h_disabled static inline NV_STATUS fabricvaspaceAllocNonContiguous(struct FABRIC_VASPACE *pFabricVAS, NvU64 size, NvU64 align, NvU64 rangeLo, NvU64 rangeHi, NvU64 pageSize, VAS_ALLOC_FLAGS flags, NvU64 **ppAddr, NvU32 *pNumAddr) { NV_ASSERT_FAILED_PRECOMP("FABRIC_VASPACE was disabled!"); @@ -318,6 +341,7 @@ static inline NV_STATUS fabricvaspaceAllocNonContiguous(struct FABRIC_VASPACE *p #endif //__nvoc_fabric_vaspace_h_disabled void fabricvaspaceBatchFree_IMPL(struct FABRIC_VASPACE *pFabricVAS, NvU64 *pAddr, NvU32 numAddr, NvU32 stride); + #ifdef __nvoc_fabric_vaspace_h_disabled static inline void fabricvaspaceBatchFree(struct FABRIC_VASPACE *pFabricVAS, NvU64 *pAddr, NvU32 numAddr, NvU32 stride) { NV_ASSERT_FAILED_PRECOMP("FABRIC_VASPACE was disabled!"); @@ -327,6 +351,7 @@ static inline void fabricvaspaceBatchFree(struct FABRIC_VASPACE *pFabricVAS, NvU #endif //__nvoc_fabric_vaspace_h_disabled NV_STATUS fabricvaspaceGetFreeHeap_IMPL(struct FABRIC_VASPACE *pFabricVAS, NvU64 *pFreeSize); + #ifdef __nvoc_fabric_vaspace_h_disabled static inline NV_STATUS fabricvaspaceGetFreeHeap(struct FABRIC_VASPACE *pFabricVAS, NvU64 *pFreeSize) { NV_ASSERT_FAILED_PRECOMP("FABRIC_VASPACE was disabled!"); @@ -337,6 +362,7 @@ static inline NV_STATUS fabricvaspaceGetFreeHeap(struct FABRIC_VASPACE *pFabricV #endif //__nvoc_fabric_vaspace_h_disabled NV_STATUS fabricvaspaceGetGpaMemdesc_IMPL(struct FABRIC_VASPACE *pFabricVAS, MEMORY_DESCRIPTOR *pFabricMemdesc, struct OBJGPU *pMappingGpu, MEMORY_DESCRIPTOR **ppAdjustedMemdesc); + #ifdef __nvoc_fabric_vaspace_h_disabled static inline NV_STATUS fabricvaspaceGetGpaMemdesc(struct FABRIC_VASPACE *pFabricVAS, MEMORY_DESCRIPTOR *pFabricMemdesc, struct OBJGPU *pMappingGpu, MEMORY_DESCRIPTOR **ppAdjustedMemdesc) { NV_ASSERT_FAILED_PRECOMP("FABRIC_VASPACE was disabled!"); @@ -347,6 +373,7 @@ static inline NV_STATUS fabricvaspaceGetGpaMemdesc(struct FABRIC_VASPACE *pFabri #endif //__nvoc_fabric_vaspace_h_disabled void fabricvaspacePutGpaMemdesc_IMPL(struct FABRIC_VASPACE *pFabricVAS, MEMORY_DESCRIPTOR *pMemDesc); + #ifdef __nvoc_fabric_vaspace_h_disabled static inline void fabricvaspacePutGpaMemdesc(struct FABRIC_VASPACE *pFabricVAS, MEMORY_DESCRIPTOR *pMemDesc) { NV_ASSERT_FAILED_PRECOMP("FABRIC_VASPACE was disabled!"); @@ -356,6 +383,7 @@ static inline void fabricvaspacePutGpaMemdesc(struct FABRIC_VASPACE *pFabricVAS, #endif //__nvoc_fabric_vaspace_h_disabled NV_STATUS fabricvaspaceVaToGpaMapInsert_IMPL(struct FABRIC_VASPACE *pFabricVAS, NvU64 vAddr, MEMORY_DESCRIPTOR *pVidMemDesc, NvU64 offset); + #ifdef __nvoc_fabric_vaspace_h_disabled static inline NV_STATUS fabricvaspaceVaToGpaMapInsert(struct FABRIC_VASPACE *pFabricVAS, NvU64 vAddr, MEMORY_DESCRIPTOR *pVidMemDesc, NvU64 offset) { NV_ASSERT_FAILED_PRECOMP("FABRIC_VASPACE was disabled!"); @@ -366,6 +394,7 @@ static inline NV_STATUS fabricvaspaceVaToGpaMapInsert(struct FABRIC_VASPACE *pFa #endif //__nvoc_fabric_vaspace_h_disabled void fabricvaspaceVaToGpaMapRemove_IMPL(struct FABRIC_VASPACE *pFabricVAS, NvU64 vAddr); + #ifdef __nvoc_fabric_vaspace_h_disabled static inline void fabricvaspaceVaToGpaMapRemove(struct FABRIC_VASPACE *pFabricVAS, NvU64 vAddr) { NV_ASSERT_FAILED_PRECOMP("FABRIC_VASPACE was disabled!"); @@ -374,6 +403,49 @@ static inline void fabricvaspaceVaToGpaMapRemove(struct FABRIC_VASPACE *pFabricV #define fabricvaspaceVaToGpaMapRemove(pFabricVAS, vAddr) fabricvaspaceVaToGpaMapRemove_IMPL(pFabricVAS, vAddr) #endif //__nvoc_fabric_vaspace_h_disabled +NV_STATUS fabricvaspaceAllocMulticast_IMPL(struct FABRIC_VASPACE *pFabricVAS, NvU64 pageSize, NvU64 alignment, VAS_ALLOC_FLAGS flags, NvU64 base, NvU64 size); + +#ifdef __nvoc_fabric_vaspace_h_disabled +static inline NV_STATUS fabricvaspaceAllocMulticast(struct FABRIC_VASPACE *pFabricVAS, NvU64 pageSize, NvU64 alignment, VAS_ALLOC_FLAGS flags, NvU64 base, NvU64 size) { + NV_ASSERT_FAILED_PRECOMP("FABRIC_VASPACE was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_fabric_vaspace_h_disabled +#define fabricvaspaceAllocMulticast(pFabricVAS, pageSize, alignment, flags, base, size) fabricvaspaceAllocMulticast_IMPL(pFabricVAS, pageSize, alignment, flags, base, size) +#endif //__nvoc_fabric_vaspace_h_disabled + +NV_STATUS fabricvaspaceMapPhysMemdesc_IMPL(struct FABRIC_VASPACE *pFabricVAS, MEMORY_DESCRIPTOR *pFabricMemDesc, NvU64 fabricOffset, MEMORY_DESCRIPTOR *pPhysMemDesc, NvU64 physOffset, NvU64 physMapLength, NvU32 flags); + +#ifdef __nvoc_fabric_vaspace_h_disabled +static inline NV_STATUS fabricvaspaceMapPhysMemdesc(struct FABRIC_VASPACE *pFabricVAS, MEMORY_DESCRIPTOR *pFabricMemDesc, NvU64 fabricOffset, MEMORY_DESCRIPTOR *pPhysMemDesc, NvU64 physOffset, NvU64 physMapLength, NvU32 flags) { + NV_ASSERT_FAILED_PRECOMP("FABRIC_VASPACE was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_fabric_vaspace_h_disabled +#define fabricvaspaceMapPhysMemdesc(pFabricVAS, pFabricMemDesc, fabricOffset, pPhysMemDesc, physOffset, physMapLength, flags) fabricvaspaceMapPhysMemdesc_IMPL(pFabricVAS, pFabricMemDesc, fabricOffset, pPhysMemDesc, physOffset, physMapLength, flags) +#endif //__nvoc_fabric_vaspace_h_disabled + +void fabricvaspaceUnmapPhysMemdesc_IMPL(struct FABRIC_VASPACE *pFabricVAS, MEMORY_DESCRIPTOR *pFabricMemDesc, NvU64 fabricOffset, MEMORY_DESCRIPTOR *pPhysMemDesc, NvU64 physMapLength); + +#ifdef __nvoc_fabric_vaspace_h_disabled +static inline void fabricvaspaceUnmapPhysMemdesc(struct FABRIC_VASPACE *pFabricVAS, MEMORY_DESCRIPTOR *pFabricMemDesc, NvU64 fabricOffset, MEMORY_DESCRIPTOR *pPhysMemDesc, NvU64 physMapLength) { + NV_ASSERT_FAILED_PRECOMP("FABRIC_VASPACE was disabled!"); +} +#else //__nvoc_fabric_vaspace_h_disabled +#define fabricvaspaceUnmapPhysMemdesc(pFabricVAS, pFabricMemDesc, fabricOffset, pPhysMemDesc, physMapLength) fabricvaspaceUnmapPhysMemdesc_IMPL(pFabricVAS, pFabricMemDesc, fabricOffset, pPhysMemDesc, physMapLength) +#endif //__nvoc_fabric_vaspace_h_disabled + +NV_STATUS fabricvaspaceInitUCRange_IMPL(struct FABRIC_VASPACE *pFabricVAS, struct OBJGPU *pGpu, NvU64 ucFabricBase, NvU64 ucFabricSize); + +#ifdef __nvoc_fabric_vaspace_h_disabled +static inline NV_STATUS fabricvaspaceInitUCRange(struct FABRIC_VASPACE *pFabricVAS, struct OBJGPU *pGpu, NvU64 ucFabricBase, NvU64 ucFabricSize) { + NV_ASSERT_FAILED_PRECOMP("FABRIC_VASPACE was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_fabric_vaspace_h_disabled +#define fabricvaspaceInitUCRange(pFabricVAS, pGpu, ucFabricBase, ucFabricSize) fabricvaspaceInitUCRange_IMPL(pFabricVAS, pGpu, ucFabricBase, ucFabricSize) +#endif //__nvoc_fabric_vaspace_h_disabled + #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_fbsr_nvoc.c b/src/nvidia/generated/g_fbsr_nvoc.c index 719979936..f1aaa4c8c 100644 --- a/src/nvidia/generated/g_fbsr_nvoc.c +++ b/src/nvidia/generated/g_fbsr_nvoc.c @@ -72,10 +72,14 @@ void __nvoc_dtor_OBJFBSR(OBJFBSR *pThis) { void __nvoc_init_dataField_OBJFBSR(OBJFBSR *pThis, RmHalspecOwner *pRmhalspecowner) { ChipHal *chipHal = &pRmhalspecowner->chipHal; const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; PORT_UNREFERENCED_VARIABLE(pThis); PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); PORT_UNREFERENCED_VARIABLE(chipHal); PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); } NV_STATUS __nvoc_ctor_Object(Object* ); @@ -95,35 +99,39 @@ __nvoc_ctor_OBJFBSR_exit: static void __nvoc_init_funcTable_OBJFBSR_1(OBJFBSR *pThis, RmHalspecOwner *pRmhalspecowner) { ChipHal *chipHal = &pRmhalspecowner->chipHal; const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; PORT_UNREFERENCED_VARIABLE(pThis); PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); PORT_UNREFERENCED_VARIABLE(chipHal); PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // Hal function -- fbsrBegin - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ - { - pThis->__fbsrBegin__ = &fbsrBegin_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x080003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ - { - pThis->__fbsrBegin__ = &fbsrBegin_GM107; - } - else if (0) + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__fbsrBegin__ = &fbsrBegin_GA100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ + { + pThis->__fbsrBegin__ = &fbsrBegin_GM107; + } } // Hal function -- fbsrEnd - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ - { - pThis->__fbsrEnd__ = &fbsrEnd_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x080003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ - { - pThis->__fbsrEnd__ = &fbsrEnd_GM107; - } - else if (0) + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__fbsrEnd__ = &fbsrEnd_GA100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ + { + pThis->__fbsrEnd__ = &fbsrEnd_GM107; + } } } diff --git a/src/nvidia/generated/g_fbsr_nvoc.h b/src/nvidia/generated/g_fbsr_nvoc.h index 551f53478..eba2b381c 100644 --- a/src/nvidia/generated/g_fbsr_nvoc.h +++ b/src/nvidia/generated/g_fbsr_nvoc.h @@ -68,6 +68,16 @@ typedef struct NvU64 avblViewSz; // Chunk of mapped view that's unprocessed i.e., not restored or can be saved. } BACKINGSTORE_SECTION_INFO; +// Struct to hold info on a region being saved/restored +typedef struct +{ + MEMORY_DESCRIPTOR *pVidMemDesc; // MEMORY_DESCRIPTOR of FBMEM region being saved/restored + MEMORY_DESCRIPTOR *pSysMemDesc; // MEMORY_DESCRIPTOR of SYSMEM region used to save FB region to/restore from + NvU64 vidOffset; // Offset in FBMEM region to save/restore + NvU64 sysOffset; // Offset in SYSMEM region to save to/restore from + NvU64 size; // Size of region being saved/restored +} FBSR_REGION_RECORD; + typedef struct OBJFBSR *POBJFBSR; #ifndef __NVOC_CLASS_OBJFBSR_TYPEDEF__ @@ -97,14 +107,18 @@ struct OBJFBSR { struct OBJCE *pCe; FBSR_OP_TYPE op; MEMORY_DESCRIPTOR *pSysMemDesc; - PFBSR_NODE pSysMemNodeHead; - PFBSR_NODE pSysMemNodeCurrent; + FBSR_NODE *pSysMemNodeHead; + FBSR_NODE *pSysMemNodeCurrent; BACKINGSTORE_SECTION_INFO pagedBufferInfo; + FBSR_REGION_RECORD *pRegionRecords; NvU32 *pPinnedBuffer; NvU8 *pDmaBuffer; void *pMapCookie; NvU64 length; NvU64 sysOffset; + NvU64 gspFbAllocsSysOffset; + NvU32 numRegions; + NvU32 regionRecordIndex; NvBool bOperationFailed; NvBool bValid; NvBool bInitialized; @@ -146,6 +160,7 @@ NV_STATUS __nvoc_objCreate_OBJFBSR(OBJFBSR**, Dynamic*, NvU32); #define fbsrEnd_HAL(pGpu, pFbsr) fbsrEnd_DISPATCH(pGpu, pFbsr) NV_STATUS fbsrInit_GM107(struct OBJGPU *pGpu, struct OBJFBSR *pFbsr); + #ifdef __nvoc_fbsr_h_disabled static inline NV_STATUS fbsrInit(struct OBJGPU *pGpu, struct OBJFBSR *pFbsr) { NV_ASSERT_FAILED_PRECOMP("OBJFBSR was disabled!"); @@ -159,6 +174,7 @@ static inline NV_STATUS fbsrInit(struct OBJGPU *pGpu, struct OBJFBSR *pFbsr) { void fbsrDestroy_GM107(struct OBJGPU *pGpu, struct OBJFBSR *pFbsr); + #ifdef __nvoc_fbsr_h_disabled static inline void fbsrDestroy(struct OBJGPU *pGpu, struct OBJFBSR *pFbsr) { NV_ASSERT_FAILED_PRECOMP("OBJFBSR was disabled!"); @@ -171,6 +187,7 @@ static inline void fbsrDestroy(struct OBJGPU *pGpu, struct OBJFBSR *pFbsr) { void fbsrCopyMemoryMemDesc_GM107(struct OBJGPU *pGpu, struct OBJFBSR *pFbsr, MEMORY_DESCRIPTOR *pVidMemDesc); + #ifdef __nvoc_fbsr_h_disabled static inline void fbsrCopyMemoryMemDesc(struct OBJGPU *pGpu, struct OBJFBSR *pFbsr, MEMORY_DESCRIPTOR *pVidMemDesc) { NV_ASSERT_FAILED_PRECOMP("OBJFBSR was disabled!"); @@ -181,14 +198,26 @@ static inline void fbsrCopyMemoryMemDesc(struct OBJGPU *pGpu, struct OBJFBSR *pF #define fbsrCopyMemoryMemDesc_HAL(pGpu, pFbsr, pVidMemDesc) fbsrCopyMemoryMemDesc(pGpu, pFbsr, pVidMemDesc) +static inline NV_STATUS fbsrExecuteSaveRestore_46f6a7(struct OBJGPU *pGpu, struct OBJFBSR *pFbsr) { + return NV_ERR_NOT_SUPPORTED; +} + + +#ifdef __nvoc_fbsr_h_disabled +static inline NV_STATUS fbsrExecuteSaveRestore(struct OBJGPU *pGpu, struct OBJFBSR *pFbsr) { + NV_ASSERT_FAILED_PRECOMP("OBJFBSR was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_fbsr_h_disabled +#define fbsrExecuteSaveRestore(pGpu, pFbsr) fbsrExecuteSaveRestore_46f6a7(pGpu, pFbsr) +#endif //__nvoc_fbsr_h_disabled + +#define fbsrExecuteSaveRestore_HAL(pGpu, pFbsr) fbsrExecuteSaveRestore(pGpu, pFbsr) + NV_STATUS fbsrBegin_GA100(struct OBJGPU *pGpu, struct OBJFBSR *pFbsr, FBSR_OP_TYPE op); NV_STATUS fbsrBegin_GM107(struct OBJGPU *pGpu, struct OBJFBSR *pFbsr, FBSR_OP_TYPE op); -static inline NV_STATUS fbsrBegin_46f6a7(struct OBJGPU *pGpu, struct OBJFBSR *pFbsr, FBSR_OP_TYPE op) { - return NV_ERR_NOT_SUPPORTED; -} - static inline NV_STATUS fbsrBegin_DISPATCH(struct OBJGPU *pGpu, struct OBJFBSR *pFbsr, FBSR_OP_TYPE op) { return pFbsr->__fbsrBegin__(pGpu, pFbsr, op); } @@ -197,15 +226,12 @@ NV_STATUS fbsrEnd_GA100(struct OBJGPU *pGpu, struct OBJFBSR *pFbsr); NV_STATUS fbsrEnd_GM107(struct OBJGPU *pGpu, struct OBJFBSR *pFbsr); -static inline NV_STATUS fbsrEnd_5baef9(struct OBJGPU *pGpu, struct OBJFBSR *pFbsr) { - NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); -} - static inline NV_STATUS fbsrEnd_DISPATCH(struct OBJGPU *pGpu, struct OBJFBSR *pFbsr) { return pFbsr->__fbsrEnd__(pGpu, pFbsr); } NV_STATUS fbsrObjectInit_IMPL(struct OBJFBSR *pFbsr, NvU32 arg0); + #ifdef __nvoc_fbsr_h_disabled static inline NV_STATUS fbsrObjectInit(struct OBJFBSR *pFbsr, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("OBJFBSR was disabled!"); @@ -216,6 +242,7 @@ static inline NV_STATUS fbsrObjectInit(struct OBJFBSR *pFbsr, NvU32 arg0) { #endif //__nvoc_fbsr_h_disabled NV_STATUS fbsrReserveSysMemoryForPowerMgmt_IMPL(struct OBJGPU *pGpu, struct OBJFBSR *pFbsr, NvU64 arg0); + #ifdef __nvoc_fbsr_h_disabled static inline NV_STATUS fbsrReserveSysMemoryForPowerMgmt(struct OBJGPU *pGpu, struct OBJFBSR *pFbsr, NvU64 arg0) { NV_ASSERT_FAILED_PRECOMP("OBJFBSR was disabled!"); @@ -226,6 +253,7 @@ static inline NV_STATUS fbsrReserveSysMemoryForPowerMgmt(struct OBJGPU *pGpu, st #endif //__nvoc_fbsr_h_disabled void fbsrFreeReservedSysMemoryForPowerMgmt_IMPL(struct OBJFBSR *pFbsr); + #ifdef __nvoc_fbsr_h_disabled static inline void fbsrFreeReservedSysMemoryForPowerMgmt(struct OBJFBSR *pFbsr) { NV_ASSERT_FAILED_PRECOMP("OBJFBSR was disabled!"); @@ -245,8 +273,9 @@ static inline void fbsrFreeReservedSysMemoryForPowerMgmt(struct OBJFBSR *pFbsr) #define FBSR_TYPE_DMA 4 // Copy using DMA. Fastest. #define FBSR_TYPE_CPU 5 // CPU. Used when we don't have enough resources for DMA. #define FBSR_TYPE_FILE 6 // DMA from FB to scratch sysmem buffer of 64K size , which in turn copies to temporary file backed system memory +#define FBSR_TYPE_GSP 7 // FBSR for GSP regions -#define NUM_FBSR_TYPES (FBSR_TYPE_FILE + 1) +#define NUM_FBSR_TYPES (FBSR_TYPE_GSP + 1) // FBSR_TYPE_GSP to be last FBSR Type, insert any new FBSR types above FBSR_TYPE_GSP #endif // FBSR_H diff --git a/src/nvidia/generated/g_fla_mem_nvoc.c b/src/nvidia/generated/g_fla_mem_nvoc.c index 2e598d130..7f7c8e4ab 100644 --- a/src/nvidia/generated/g_fla_mem_nvoc.c +++ b/src/nvidia/generated/g_fla_mem_nvoc.c @@ -145,8 +145,12 @@ static NV_STATUS __nvoc_thunk_RmResource_flamemControl_Prologue(struct FlaMemory return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_Memory_flamemIsReady(struct FlaMemory *pMemory) { - return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset)); +static NvBool __nvoc_thunk_Memory_flamemIsGpuMapAllowed(struct FlaMemory *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), pGpu); +} + +static NV_STATUS __nvoc_thunk_Memory_flamemIsReady(struct FlaMemory *pMemory, NvBool bCopyConstructorContext) { + return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), bCopyConstructorContext); } static NV_STATUS __nvoc_thunk_Memory_flamemCheckCopyPermissions(struct FlaMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { @@ -157,6 +161,10 @@ static void __nvoc_thunk_RsResource_flamemPreDestruct(struct FlaMemory *pResourc resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_Memory_flamemIsDuplicate(struct FlaMemory *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), hMemory, pDuplicate); +} + static NV_STATUS __nvoc_thunk_RsResource_flamemUnmapFrom(struct FlaMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RsResource.offset), pParams); } @@ -246,12 +254,16 @@ static void __nvoc_init_funcTable_FlaMemory_1(FlaMemory *pThis) { pThis->__flamemControl_Prologue__ = &__nvoc_thunk_RmResource_flamemControl_Prologue; + pThis->__flamemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_flamemIsGpuMapAllowed; + pThis->__flamemIsReady__ = &__nvoc_thunk_Memory_flamemIsReady; pThis->__flamemCheckCopyPermissions__ = &__nvoc_thunk_Memory_flamemCheckCopyPermissions; pThis->__flamemPreDestruct__ = &__nvoc_thunk_RsResource_flamemPreDestruct; + pThis->__flamemIsDuplicate__ = &__nvoc_thunk_Memory_flamemIsDuplicate; + pThis->__flamemUnmapFrom__ = &__nvoc_thunk_RsResource_flamemUnmapFrom; pThis->__flamemControl_Epilogue__ = &__nvoc_thunk_RmResource_flamemControl_Epilogue; diff --git a/src/nvidia/generated/g_fla_mem_nvoc.h b/src/nvidia/generated/g_fla_mem_nvoc.h index 00fac5930..7bbf2d28f 100644 --- a/src/nvidia/generated/g_fla_mem_nvoc.h +++ b/src/nvidia/generated/g_fla_mem_nvoc.h @@ -67,9 +67,11 @@ struct FlaMemory { NvU32 (*__flamemGetRefCount__)(struct FlaMemory *); NV_STATUS (*__flamemMapTo__)(struct FlaMemory *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__flamemControl_Prologue__)(struct FlaMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__flamemIsReady__)(struct FlaMemory *); + NvBool (*__flamemIsGpuMapAllowed__)(struct FlaMemory *, struct OBJGPU *); + NV_STATUS (*__flamemIsReady__)(struct FlaMemory *, NvBool); NV_STATUS (*__flamemCheckCopyPermissions__)(struct FlaMemory *, struct OBJGPU *, NvHandle); void (*__flamemPreDestruct__)(struct FlaMemory *); + NV_STATUS (*__flamemIsDuplicate__)(struct FlaMemory *, NvHandle, NvBool *); NV_STATUS (*__flamemUnmapFrom__)(struct FlaMemory *, RS_RES_UNMAP_FROM_PARAMS *); void (*__flamemControl_Epilogue__)(struct FlaMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__flamemControlLookup__)(struct FlaMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); @@ -122,9 +124,11 @@ NV_STATUS __nvoc_objCreate_FlaMemory(FlaMemory**, Dynamic*, NvU32, CALL_CONTEXT #define flamemGetRefCount(pResource) flamemGetRefCount_DISPATCH(pResource) #define flamemMapTo(pResource, pParams) flamemMapTo_DISPATCH(pResource, pParams) #define flamemControl_Prologue(pResource, pCallContext, pParams) flamemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define flamemIsReady(pMemory) flamemIsReady_DISPATCH(pMemory) +#define flamemIsGpuMapAllowed(pMemory, pGpu) flamemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define flamemIsReady(pMemory, bCopyConstructorContext) flamemIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define flamemCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) flamemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) #define flamemPreDestruct(pResource) flamemPreDestruct_DISPATCH(pResource) +#define flamemIsDuplicate(pMemory, hMemory, pDuplicate) flamemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) #define flamemUnmapFrom(pResource, pParams) flamemUnmapFrom_DISPATCH(pResource, pParams) #define flamemControl_Epilogue(pResource, pCallContext, pParams) flamemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define flamemControlLookup(pResource, pParams, ppEntry) flamemControlLookup_DISPATCH(pResource, pParams, ppEntry) @@ -190,8 +194,12 @@ static inline NV_STATUS flamemControl_Prologue_DISPATCH(struct FlaMemory *pResou return pResource->__flamemControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS flamemIsReady_DISPATCH(struct FlaMemory *pMemory) { - return pMemory->__flamemIsReady__(pMemory); +static inline NvBool flamemIsGpuMapAllowed_DISPATCH(struct FlaMemory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__flamemIsGpuMapAllowed__(pMemory, pGpu); +} + +static inline NV_STATUS flamemIsReady_DISPATCH(struct FlaMemory *pMemory, NvBool bCopyConstructorContext) { + return pMemory->__flamemIsReady__(pMemory, bCopyConstructorContext); } static inline NV_STATUS flamemCheckCopyPermissions_DISPATCH(struct FlaMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { @@ -202,6 +210,10 @@ static inline void flamemPreDestruct_DISPATCH(struct FlaMemory *pResource) { pResource->__flamemPreDestruct__(pResource); } +static inline NV_STATUS flamemIsDuplicate_DISPATCH(struct FlaMemory *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return pMemory->__flamemIsDuplicate__(pMemory, hMemory, pDuplicate); +} + static inline NV_STATUS flamemUnmapFrom_DISPATCH(struct FlaMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return pResource->__flamemUnmapFrom__(pResource, pParams); } @@ -223,8 +235,10 @@ static inline NvBool flamemAccessCallback_DISPATCH(struct FlaMemory *pResource, } NV_STATUS flamemConstruct_IMPL(struct FlaMemory *arg_pFlaMemory, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_flamemConstruct(arg_pFlaMemory, arg_pCallContext, arg_pParams) flamemConstruct_IMPL(arg_pFlaMemory, arg_pCallContext, arg_pParams) void flamemDestruct_IMPL(struct FlaMemory *pFlaMemory); + #define __nvoc_flamemDestruct(pFlaMemory) flamemDestruct_IMPL(pFlaMemory) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_fm_session_api_nvoc.c b/src/nvidia/generated/g_fm_session_api_nvoc.c index 46a91e290..596dd968c 100644 --- a/src/nvidia/generated/g_fm_session_api_nvoc.c +++ b/src/nvidia/generated/g_fm_session_api_nvoc.c @@ -170,6 +170,10 @@ static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiUnmapFrom(struct FmSessionA return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiIsDuplicate(struct FmSessionApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), hMemory, pDuplicate); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_fmsessionapiGetNotificationListPtr(struct FmSessionApi *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_FmSessionApi_Notifier.offset)); } @@ -321,6 +325,8 @@ static void __nvoc_init_funcTable_FmSessionApi_1(FmSessionApi *pThis) { pThis->__fmsessionapiUnmapFrom__ = &__nvoc_thunk_RsResource_fmsessionapiUnmapFrom; + pThis->__fmsessionapiIsDuplicate__ = &__nvoc_thunk_RsResource_fmsessionapiIsDuplicate; + pThis->__fmsessionapiGetNotificationListPtr__ = &__nvoc_thunk_Notifier_fmsessionapiGetNotificationListPtr; pThis->__fmsessionapiControl_Epilogue__ = &__nvoc_thunk_RmResource_fmsessionapiControl_Epilogue; diff --git a/src/nvidia/generated/g_fm_session_api_nvoc.h b/src/nvidia/generated/g_fm_session_api_nvoc.h index 10f6ad99f..1295b49ff 100644 --- a/src/nvidia/generated/g_fm_session_api_nvoc.h +++ b/src/nvidia/generated/g_fm_session_api_nvoc.h @@ -99,6 +99,7 @@ struct FmSessionApi { void (*__fmsessionapiAddAdditionalDependants__)(struct RsClient *, struct FmSessionApi *, RsResourceRef *); void (*__fmsessionapiPreDestruct__)(struct FmSessionApi *); NV_STATUS (*__fmsessionapiUnmapFrom__)(struct FmSessionApi *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__fmsessionapiIsDuplicate__)(struct FmSessionApi *, NvHandle, NvBool *); PEVENTNOTIFICATION *(*__fmsessionapiGetNotificationListPtr__)(struct FmSessionApi *); void (*__fmsessionapiControl_Epilogue__)(struct FmSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); struct NotifShare *(*__fmsessionapiGetNotificationShare__)(struct FmSessionApi *); @@ -155,6 +156,7 @@ NV_STATUS __nvoc_objCreate_FmSessionApi(FmSessionApi**, Dynamic*, NvU32, struct #define fmsessionapiAddAdditionalDependants(pClient, pResource, pReference) fmsessionapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define fmsessionapiPreDestruct(pResource) fmsessionapiPreDestruct_DISPATCH(pResource) #define fmsessionapiUnmapFrom(pResource, pParams) fmsessionapiUnmapFrom_DISPATCH(pResource, pParams) +#define fmsessionapiIsDuplicate(pResource, hMemory, pDuplicate) fmsessionapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define fmsessionapiGetNotificationListPtr(pNotifier) fmsessionapiGetNotificationListPtr_DISPATCH(pNotifier) #define fmsessionapiControl_Epilogue(pResource, pCallContext, pParams) fmsessionapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define fmsessionapiGetNotificationShare(pNotifier) fmsessionapiGetNotificationShare_DISPATCH(pNotifier) @@ -241,6 +243,10 @@ static inline NV_STATUS fmsessionapiUnmapFrom_DISPATCH(struct FmSessionApi *pRes return pResource->__fmsessionapiUnmapFrom__(pResource, pParams); } +static inline NV_STATUS fmsessionapiIsDuplicate_DISPATCH(struct FmSessionApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__fmsessionapiIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline PEVENTNOTIFICATION *fmsessionapiGetNotificationListPtr_DISPATCH(struct FmSessionApi *pNotifier) { return pNotifier->__fmsessionapiGetNotificationListPtr__(pNotifier); } @@ -266,8 +272,10 @@ static inline NV_STATUS fmsessionapiGetOrAllocNotifShare_DISPATCH(struct FmSessi } NV_STATUS fmsessionapiConstruct_IMPL(struct FmSessionApi *arg_pFmSessionApi, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_fmsessionapiConstruct(arg_pFmSessionApi, arg_pCallContext, arg_pParams) fmsessionapiConstruct_IMPL(arg_pFmSessionApi, arg_pCallContext, arg_pParams) void fmsessionapiDestruct_IMPL(struct FmSessionApi *pFmSessionApi); + #define __nvoc_fmsessionapiDestruct(pFmSessionApi) fmsessionapiDestruct_IMPL(pFmSessionApi) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_generic_engine_nvoc.c b/src/nvidia/generated/g_generic_engine_nvoc.c index da30a409d..213f1f264 100644 --- a/src/nvidia/generated/g_generic_engine_nvoc.c +++ b/src/nvidia/generated/g_generic_engine_nvoc.c @@ -169,6 +169,10 @@ static NV_STATUS __nvoc_thunk_RsResource_genapiUnmapFrom(struct GenericEngineApi return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_genapiIsDuplicate(struct GenericEngineApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_genapiControl_Epilogue(struct GenericEngineApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RmResource.offset), pCallContext, pParams); } @@ -311,6 +315,8 @@ static void __nvoc_init_funcTable_GenericEngineApi_1(GenericEngineApi *pThis) { pThis->__genapiUnmapFrom__ = &__nvoc_thunk_RsResource_genapiUnmapFrom; + pThis->__genapiIsDuplicate__ = &__nvoc_thunk_RsResource_genapiIsDuplicate; + pThis->__genapiControl_Epilogue__ = &__nvoc_thunk_RmResource_genapiControl_Epilogue; pThis->__genapiControlLookup__ = &__nvoc_thunk_RsResource_genapiControlLookup; diff --git a/src/nvidia/generated/g_generic_engine_nvoc.h b/src/nvidia/generated/g_generic_engine_nvoc.h index 3939cbd9c..76d50221f 100644 --- a/src/nvidia/generated/g_generic_engine_nvoc.h +++ b/src/nvidia/generated/g_generic_engine_nvoc.h @@ -77,6 +77,7 @@ struct GenericEngineApi { NV_STATUS (*__genapiInternalControlForward__)(struct GenericEngineApi *, NvU32, void *, NvU32); void (*__genapiPreDestruct__)(struct GenericEngineApi *); NV_STATUS (*__genapiUnmapFrom__)(struct GenericEngineApi *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__genapiIsDuplicate__)(struct GenericEngineApi *, NvHandle, NvBool *); void (*__genapiControl_Epilogue__)(struct GenericEngineApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__genapiControlLookup__)(struct GenericEngineApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvBool (*__genapiAccessCallback__)(struct GenericEngineApi *, struct RsClient *, void *, RsAccessRight); @@ -131,6 +132,7 @@ NV_STATUS __nvoc_objCreate_GenericEngineApi(GenericEngineApi**, Dynamic*, NvU32, #define genapiInternalControlForward(pGpuResource, command, pParams, size) genapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define genapiPreDestruct(pResource) genapiPreDestruct_DISPATCH(pResource) #define genapiUnmapFrom(pResource, pParams) genapiUnmapFrom_DISPATCH(pResource, pParams) +#define genapiIsDuplicate(pResource, hMemory, pDuplicate) genapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define genapiControl_Epilogue(pResource, pCallContext, pParams) genapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define genapiControlLookup(pResource, pParams, ppEntry) genapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define genapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) genapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) @@ -228,6 +230,10 @@ static inline NV_STATUS genapiUnmapFrom_DISPATCH(struct GenericEngineApi *pResou return pResource->__genapiUnmapFrom__(pResource, pParams); } +static inline NV_STATUS genapiIsDuplicate_DISPATCH(struct GenericEngineApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__genapiIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void genapiControl_Epilogue_DISPATCH(struct GenericEngineApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__genapiControl_Epilogue__(pResource, pCallContext, pParams); } @@ -241,8 +247,10 @@ static inline NvBool genapiAccessCallback_DISPATCH(struct GenericEngineApi *pRes } NV_STATUS genapiConstruct_IMPL(struct GenericEngineApi *arg_pGenericEngineApi, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_genapiConstruct(arg_pGenericEngineApi, arg_pCallContext, arg_pParams) genapiConstruct_IMPL(arg_pGenericEngineApi, arg_pCallContext, arg_pParams) void genapiDestruct_IMPL(struct GenericEngineApi *pGenericEngineApi); + #define __nvoc_genapiDestruct(pGenericEngineApi) genapiDestruct_IMPL(pGenericEngineApi) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_gpu_acct_nvoc.h b/src/nvidia/generated/g_gpu_acct_nvoc.h index 9b307ab2f..a91f0e6ea 100644 --- a/src/nvidia/generated/g_gpu_acct_nvoc.h +++ b/src/nvidia/generated/g_gpu_acct_nvoc.h @@ -37,10 +37,12 @@ extern "C" { #include "core/system.h" #include "containers/map.h" #include "containers/list.h" +#include "virtualization/common_vgpu_mgr.h" #include "ctrl/ctrl0000/ctrl0000gpuacct.h" #include "ctrl/ctrl0000/ctrl0000gpu.h" // NV0000_CTRL_GPU_MAX_ATTACHED_GPUS #include "ctrl/ctrl2080/ctrl2080perf.h" // NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS + typedef struct TMR_EVENT TMR_EVENT; // Sum of NV_MAX_LIVE_ACCT_PROCESS and NV_MAX_DEAD_ACCT_PROCESS is defined as @@ -95,6 +97,17 @@ typedef struct GPU_ACCT_PROC_LIST procList; } GPU_ACCT_PROC_DATA_STORE; +typedef struct +{ + NvU32 vmPId; // Plugin/VM process id. + NvU32 isAccountingEnabled;// Whether accounting is enabled on + // this VM. + GPU_ACCT_PROC_DATA_STORE liveVMProcAcctInfo; // Pointer to list of live processes + // running on this VM. + GPU_ACCT_PROC_DATA_STORE deadVMProcAcctInfo; // Pointer to list of dead processes + // running on this VM. +} GPUACCT_VM_INSTANCE_INFO; + typedef struct { TMR_EVENT *pTmrEvent; // Pointer to the timer event created to schedule main callback @@ -108,7 +121,7 @@ typedef struct // running on this GPU. GPU_ACCT_PROC_DATA_STORE deadProcAcctInfo; // Pointer to list of dead processes // running on this GPU. - + GPUACCT_VM_INSTANCE_INFO vmInstanceInfo[MAX_VGPU_DEVICES_PER_PGPU]; } GPUACCT_GPU_INSTANCE_INFO; #ifdef NVOC_GPU_ACCT_H_PRIVATE_ACCESS_ALLOWED @@ -153,10 +166,13 @@ NV_STATUS __nvoc_objCreate_GpuAccounting(GpuAccounting**, Dynamic*, NvU32); __nvoc_objCreate_GpuAccounting((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) NV_STATUS gpuacctConstruct_IMPL(struct GpuAccounting *arg_); + #define __nvoc_gpuacctConstruct(arg_) gpuacctConstruct_IMPL(arg_) void gpuacctDestruct_IMPL(struct GpuAccounting *arg0); + #define __nvoc_gpuacctDestruct(arg0) gpuacctDestruct_IMPL(arg0) NV_STATUS gpuacctGetAccountingMode_IMPL(struct GpuAccounting *arg0, NvU32 arg1, NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS *arg2); + #ifdef __nvoc_gpu_acct_h_disabled static inline NV_STATUS gpuacctGetAccountingMode(struct GpuAccounting *arg0, NvU32 arg1, NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS *arg2) { NV_ASSERT_FAILED_PRECOMP("GpuAccounting was disabled!"); @@ -167,6 +183,7 @@ static inline NV_STATUS gpuacctGetAccountingMode(struct GpuAccounting *arg0, NvU #endif //__nvoc_gpu_acct_h_disabled NV_STATUS gpuacctEnableAccounting_IMPL(struct GpuAccounting *arg0, NvU32 arg1, NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS *arg2); + #ifdef __nvoc_gpu_acct_h_disabled static inline NV_STATUS gpuacctEnableAccounting(struct GpuAccounting *arg0, NvU32 arg1, NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS *arg2) { NV_ASSERT_FAILED_PRECOMP("GpuAccounting was disabled!"); @@ -177,6 +194,7 @@ static inline NV_STATUS gpuacctEnableAccounting(struct GpuAccounting *arg0, NvU3 #endif //__nvoc_gpu_acct_h_disabled NV_STATUS gpuacctDisableAccounting_IMPL(struct GpuAccounting *arg0, NvU32 arg1, NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS *arg2); + #ifdef __nvoc_gpu_acct_h_disabled static inline NV_STATUS gpuacctDisableAccounting(struct GpuAccounting *arg0, NvU32 arg1, NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS *arg2) { NV_ASSERT_FAILED_PRECOMP("GpuAccounting was disabled!"); @@ -187,6 +205,7 @@ static inline NV_STATUS gpuacctDisableAccounting(struct GpuAccounting *arg0, NvU #endif //__nvoc_gpu_acct_h_disabled NV_STATUS gpuacctClearAccountingData_IMPL(struct GpuAccounting *arg0, NvU32 arg1, NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS *arg2); + #ifdef __nvoc_gpu_acct_h_disabled static inline NV_STATUS gpuacctClearAccountingData(struct GpuAccounting *arg0, NvU32 arg1, NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS *arg2) { NV_ASSERT_FAILED_PRECOMP("GpuAccounting was disabled!"); @@ -197,6 +216,7 @@ static inline NV_STATUS gpuacctClearAccountingData(struct GpuAccounting *arg0, N #endif //__nvoc_gpu_acct_h_disabled NV_STATUS gpuacctStartGpuAccounting_IMPL(struct GpuAccounting *arg0, NvU32 arg1, NvU32 arg2, NvU32 arg3); + #ifdef __nvoc_gpu_acct_h_disabled static inline NV_STATUS gpuacctStartGpuAccounting(struct GpuAccounting *arg0, NvU32 arg1, NvU32 arg2, NvU32 arg3) { NV_ASSERT_FAILED_PRECOMP("GpuAccounting was disabled!"); @@ -207,6 +227,7 @@ static inline NV_STATUS gpuacctStartGpuAccounting(struct GpuAccounting *arg0, Nv #endif //__nvoc_gpu_acct_h_disabled NV_STATUS gpuacctStopGpuAccounting_IMPL(struct GpuAccounting *arg0, NvU32 arg1, NvU32 arg2, NvU32 arg3); + #ifdef __nvoc_gpu_acct_h_disabled static inline NV_STATUS gpuacctStopGpuAccounting(struct GpuAccounting *arg0, NvU32 arg1, NvU32 arg2, NvU32 arg3) { NV_ASSERT_FAILED_PRECOMP("GpuAccounting was disabled!"); @@ -217,6 +238,7 @@ static inline NV_STATUS gpuacctStopGpuAccounting(struct GpuAccounting *arg0, NvU #endif //__nvoc_gpu_acct_h_disabled NV_STATUS gpuacctUpdateProcPeakFbUsage_IMPL(struct GpuAccounting *arg0, NvU32 arg1, NvU32 arg2, NvU32 arg3, NvU64 arg4); + #ifdef __nvoc_gpu_acct_h_disabled static inline NV_STATUS gpuacctUpdateProcPeakFbUsage(struct GpuAccounting *arg0, NvU32 arg1, NvU32 arg2, NvU32 arg3, NvU64 arg4) { NV_ASSERT_FAILED_PRECOMP("GpuAccounting was disabled!"); @@ -227,6 +249,7 @@ static inline NV_STATUS gpuacctUpdateProcPeakFbUsage(struct GpuAccounting *arg0, #endif //__nvoc_gpu_acct_h_disabled NV_STATUS gpuacctGetProcAcctInfo_IMPL(struct GpuAccounting *arg0, NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS *arg1); + #ifdef __nvoc_gpu_acct_h_disabled static inline NV_STATUS gpuacctGetProcAcctInfo(struct GpuAccounting *arg0, NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS *arg1) { NV_ASSERT_FAILED_PRECOMP("GpuAccounting was disabled!"); @@ -237,6 +260,7 @@ static inline NV_STATUS gpuacctGetProcAcctInfo(struct GpuAccounting *arg0, NV000 #endif //__nvoc_gpu_acct_h_disabled NV_STATUS gpuacctGetAcctPids_IMPL(struct GpuAccounting *arg0, NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS *arg1); + #ifdef __nvoc_gpu_acct_h_disabled static inline NV_STATUS gpuacctGetAcctPids(struct GpuAccounting *arg0, NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS *arg1) { NV_ASSERT_FAILED_PRECOMP("GpuAccounting was disabled!"); @@ -247,6 +271,7 @@ static inline NV_STATUS gpuacctGetAcctPids(struct GpuAccounting *arg0, NV0000_CT #endif //__nvoc_gpu_acct_h_disabled NV_STATUS gpuacctSetProcType_IMPL(struct GpuAccounting *arg0, NvU32 arg1, NvU32 arg2, NvU32 arg3, NvU32 arg4); + #ifdef __nvoc_gpu_acct_h_disabled static inline NV_STATUS gpuacctSetProcType(struct GpuAccounting *arg0, NvU32 arg1, NvU32 arg2, NvU32 arg3, NvU32 arg4) { NV_ASSERT_FAILED_PRECOMP("GpuAccounting was disabled!"); @@ -259,6 +284,8 @@ static inline NV_STATUS gpuacctSetProcType(struct GpuAccounting *arg0, NvU32 arg #undef PRIVATE_FIELD +void vmAcctInitState(struct OBJGPU *pGpu, NvU32 vmPid); +void vmAcctDestructState(NvU32 vmPid, struct OBJGPU *pGpu); void gpuacctProcessGpuUtil(GPUACCT_GPU_INSTANCE_INFO *, NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE *); #endif diff --git a/src/nvidia/generated/g_gpu_boost_mgr_nvoc.h b/src/nvidia/generated/g_gpu_boost_mgr_nvoc.h index 954cc03a9..6c23096ab 100644 --- a/src/nvidia/generated/g_gpu_boost_mgr_nvoc.h +++ b/src/nvidia/generated/g_gpu_boost_mgr_nvoc.h @@ -140,10 +140,13 @@ NV_STATUS __nvoc_objCreate_OBJGPUBOOSTMGR(OBJGPUBOOSTMGR**, Dynamic*, NvU32); __nvoc_objCreate_OBJGPUBOOSTMGR((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) NV_STATUS gpuboostmgrConstruct_IMPL(struct OBJGPUBOOSTMGR *arg_pBoostMgr); + #define __nvoc_gpuboostmgrConstruct(arg_pBoostMgr) gpuboostmgrConstruct_IMPL(arg_pBoostMgr) void gpuboostmgrDestruct_IMPL(struct OBJGPUBOOSTMGR *pBoostMgr); + #define __nvoc_gpuboostmgrDestruct(pBoostMgr) gpuboostmgrDestruct_IMPL(pBoostMgr) NV_STATUS gpuboostmgrCreateGroup_IMPL(struct OBJGPUBOOSTMGR *pBoostMgr, NV0000_SYNC_GPU_BOOST_GROUP_CONFIG *pBoostConfig); + #ifdef __nvoc_gpu_boost_mgr_h_disabled static inline NV_STATUS gpuboostmgrCreateGroup(struct OBJGPUBOOSTMGR *pBoostMgr, NV0000_SYNC_GPU_BOOST_GROUP_CONFIG *pBoostConfig) { NV_ASSERT_FAILED_PRECOMP("OBJGPUBOOSTMGR was disabled!"); @@ -154,6 +157,7 @@ static inline NV_STATUS gpuboostmgrCreateGroup(struct OBJGPUBOOSTMGR *pBoostMgr, #endif //__nvoc_gpu_boost_mgr_h_disabled NV_STATUS gpuboostmgrDestroyGroup_IMPL(struct OBJGPUBOOSTMGR *pBoostMgr, NvU32 boostGroupId); + #ifdef __nvoc_gpu_boost_mgr_h_disabled static inline NV_STATUS gpuboostmgrDestroyGroup(struct OBJGPUBOOSTMGR *pBoostMgr, NvU32 boostGroupId) { NV_ASSERT_FAILED_PRECOMP("OBJGPUBOOSTMGR was disabled!"); @@ -164,6 +168,7 @@ static inline NV_STATUS gpuboostmgrDestroyGroup(struct OBJGPUBOOSTMGR *pBoostMgr #endif //__nvoc_gpu_boost_mgr_h_disabled NV_STATUS gpuboostmgrQueryGroups_IMPL(struct OBJGPUBOOSTMGR *pBoostMgr, NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS *pParams); + #ifdef __nvoc_gpu_boost_mgr_h_disabled static inline NV_STATUS gpuboostmgrQueryGroups(struct OBJGPUBOOSTMGR *pBoostMgr, NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS *pParams) { NV_ASSERT_FAILED_PRECOMP("OBJGPUBOOSTMGR was disabled!"); @@ -174,6 +179,7 @@ static inline NV_STATUS gpuboostmgrQueryGroups(struct OBJGPUBOOSTMGR *pBoostMgr, #endif //__nvoc_gpu_boost_mgr_h_disabled NV_STATUS gpuboostmgrCheckConfig_IMPL(struct OBJGPUBOOSTMGR *pBoostMgr, NV0000_SYNC_GPU_BOOST_GROUP_CONFIG *pBoostConfig); + #ifdef __nvoc_gpu_boost_mgr_h_disabled static inline NV_STATUS gpuboostmgrCheckConfig(struct OBJGPUBOOSTMGR *pBoostMgr, NV0000_SYNC_GPU_BOOST_GROUP_CONFIG *pBoostConfig) { NV_ASSERT_FAILED_PRECOMP("OBJGPUBOOSTMGR was disabled!"); @@ -184,6 +190,7 @@ static inline NV_STATUS gpuboostmgrCheckConfig(struct OBJGPUBOOSTMGR *pBoostMgr, #endif //__nvoc_gpu_boost_mgr_h_disabled NV_STATUS gpuboostmgrValidateGroupId_IMPL(struct OBJGPUBOOSTMGR *pBoostMgr, NvU32 boostGroupId); + #ifdef __nvoc_gpu_boost_mgr_h_disabled static inline NV_STATUS gpuboostmgrValidateGroupId(struct OBJGPUBOOSTMGR *pBoostMgr, NvU32 boostGroupId) { NV_ASSERT_FAILED_PRECOMP("OBJGPUBOOSTMGR was disabled!"); @@ -194,6 +201,7 @@ static inline NV_STATUS gpuboostmgrValidateGroupId(struct OBJGPUBOOSTMGR *pBoost #endif //__nvoc_gpu_boost_mgr_h_disabled NV_STATUS gpuboostmgrIncrementRefCount_IMPL(struct OBJGPUBOOSTMGR *pBoostMgr, NvU32 boostGroupId); + #ifdef __nvoc_gpu_boost_mgr_h_disabled static inline NV_STATUS gpuboostmgrIncrementRefCount(struct OBJGPUBOOSTMGR *pBoostMgr, NvU32 boostGroupId) { NV_ASSERT_FAILED_PRECOMP("OBJGPUBOOSTMGR was disabled!"); @@ -204,6 +212,7 @@ static inline NV_STATUS gpuboostmgrIncrementRefCount(struct OBJGPUBOOSTMGR *pBoo #endif //__nvoc_gpu_boost_mgr_h_disabled NV_STATUS gpuboostmgrDecrementRefCount_IMPL(struct OBJGPUBOOSTMGR *pBoostMgr, NvU32 boostGroupId); + #ifdef __nvoc_gpu_boost_mgr_h_disabled static inline NV_STATUS gpuboostmgrDecrementRefCount(struct OBJGPUBOOSTMGR *pBoostMgr, NvU32 boostGroupId) { NV_ASSERT_FAILED_PRECOMP("OBJGPUBOOSTMGR was disabled!"); @@ -214,6 +223,7 @@ static inline NV_STATUS gpuboostmgrDecrementRefCount(struct OBJGPUBOOSTMGR *pBoo #endif //__nvoc_gpu_boost_mgr_h_disabled OBJGPU *gpuboostmgrGpuItr_IMPL(struct OBJGPUBOOSTMGR *pBoostMgr, NvU32 grpId, NvU32 *pIndex); + #ifdef __nvoc_gpu_boost_mgr_h_disabled static inline OBJGPU *gpuboostmgrGpuItr(struct OBJGPUBOOSTMGR *pBoostMgr, NvU32 grpId, NvU32 *pIndex) { NV_ASSERT_FAILED_PRECOMP("OBJGPUBOOSTMGR was disabled!"); @@ -224,6 +234,7 @@ static inline OBJGPU *gpuboostmgrGpuItr(struct OBJGPUBOOSTMGR *pBoostMgr, NvU32 #endif //__nvoc_gpu_boost_mgr_h_disabled NV_STATUS gpuboostmgrGetBoostGrpIdFromGpu_IMPL(struct OBJGPUBOOSTMGR *pBoostMgr, OBJGPU *pGpu, NvU32 *pGrpId); + #ifdef __nvoc_gpu_boost_mgr_h_disabled static inline NV_STATUS gpuboostmgrGetBoostGrpIdFromGpu(struct OBJGPUBOOSTMGR *pBoostMgr, OBJGPU *pGpu, NvU32 *pGrpId) { NV_ASSERT_FAILED_PRECOMP("OBJGPUBOOSTMGR was disabled!"); @@ -234,6 +245,7 @@ static inline NV_STATUS gpuboostmgrGetBoostGrpIdFromGpu(struct OBJGPUBOOSTMGR *p #endif //__nvoc_gpu_boost_mgr_h_disabled NvBool gpuboostmgrIsBoostGrpActive_IMPL(struct OBJGPUBOOSTMGR *pBoostMgr, NvU32 grpId); + #ifdef __nvoc_gpu_boost_mgr_h_disabled static inline NvBool gpuboostmgrIsBoostGrpActive(struct OBJGPUBOOSTMGR *pBoostMgr, NvU32 grpId) { NV_ASSERT_FAILED_PRECOMP("OBJGPUBOOSTMGR was disabled!"); diff --git a/src/nvidia/generated/g_gpu_class_list.c b/src/nvidia/generated/g_gpu_class_list.c index c8736a795..2d1eb916a 100644 --- a/src/nvidia/generated/g_gpu_class_list.c +++ b/src/nvidia/generated/g_gpu_class_list.c @@ -29,7 +29,7 @@ const CLASSDESCRIPTOR * -gpuGetClassDescriptorList_TU102(POBJGPU pGpu, NvU32 *pNumClasses) +gpuGetClassDescriptorList_TU102(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { static const CLASSDESCRIPTOR halTU102ClassDescriptorList[] = { { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, @@ -54,6 +54,8 @@ gpuGetClassDescriptorList_TU102(POBJGPU pGpu, NvU32 *pNumClasses) { NV50_MEMORY_VIRTUAL, ENG_DMA }, { NV50_P2P, ENG_BUS }, { NV50_THIRD_PARTY_P2P, ENG_BUS }, + { NVA081_VGPU_CONFIG, ENG_GPU }, + { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, { NVC371_DISP_SF_USER, ENG_KERNEL_DISPLAY }, { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY }, { NVC4B0_VIDEO_DECODER, ENG_NVDEC(0) }, @@ -64,6 +66,7 @@ gpuGetClassDescriptorList_TU102(POBJGPU pGpu, NvU32 *pNumClasses) { NVC57B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, { NVC57D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, { NVC57E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, + { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_A, ENG_GR(0) }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, { TURING_COMPUTE_A, ENG_GR(0) }, @@ -79,16 +82,18 @@ gpuGetClassDescriptorList_TU102(POBJGPU pGpu, NvU32 *pNumClasses) #define HALTU102_NUM_CLASS_DESCS (sizeof(halTU102ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) - ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALTU102_NUM_CLASS_DESCS); + #define HALTU102_NUM_CLASSES 52 - *pNumClasses = HALTU102_NUM_CLASS_DESCS; + ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALTU102_NUM_CLASSES); + + *pNumClassDescriptors = HALTU102_NUM_CLASS_DESCS; return halTU102ClassDescriptorList; } const CLASSDESCRIPTOR * -gpuGetClassDescriptorList_TU104(POBJGPU pGpu, NvU32 *pNumClasses) +gpuGetClassDescriptorList_TU104(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { static const CLASSDESCRIPTOR halTU104ClassDescriptorList[] = { { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, @@ -113,6 +118,8 @@ gpuGetClassDescriptorList_TU104(POBJGPU pGpu, NvU32 *pNumClasses) { NV50_MEMORY_VIRTUAL, ENG_DMA }, { NV50_P2P, ENG_BUS }, { NV50_THIRD_PARTY_P2P, ENG_BUS }, + { NVA081_VGPU_CONFIG, ENG_GPU }, + { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, { NVC371_DISP_SF_USER, ENG_KERNEL_DISPLAY }, { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY }, { NVC4B0_VIDEO_DECODER, ENG_NVDEC(0) }, @@ -124,6 +131,7 @@ gpuGetClassDescriptorList_TU104(POBJGPU pGpu, NvU32 *pNumClasses) { NVC57B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, { NVC57D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, { NVC57E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, + { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_A, ENG_GR(0) }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, { TURING_COMPUTE_A, ENG_GR(0) }, @@ -139,16 +147,18 @@ gpuGetClassDescriptorList_TU104(POBJGPU pGpu, NvU32 *pNumClasses) #define HALTU104_NUM_CLASS_DESCS (sizeof(halTU104ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) - ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALTU104_NUM_CLASS_DESCS); + #define HALTU104_NUM_CLASSES 52 - *pNumClasses = HALTU104_NUM_CLASS_DESCS; + ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALTU104_NUM_CLASSES); + + *pNumClassDescriptors = HALTU104_NUM_CLASS_DESCS; return halTU104ClassDescriptorList; } const CLASSDESCRIPTOR * -gpuGetClassDescriptorList_TU106(POBJGPU pGpu, NvU32 *pNumClasses) +gpuGetClassDescriptorList_TU106(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { static const CLASSDESCRIPTOR halTU106ClassDescriptorList[] = { { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, @@ -173,6 +183,8 @@ gpuGetClassDescriptorList_TU106(POBJGPU pGpu, NvU32 *pNumClasses) { NV50_MEMORY_VIRTUAL, ENG_DMA }, { NV50_P2P, ENG_BUS }, { NV50_THIRD_PARTY_P2P, ENG_BUS }, + { NVA081_VGPU_CONFIG, ENG_GPU }, + { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, { NVC371_DISP_SF_USER, ENG_KERNEL_DISPLAY }, { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY }, { NVC4B0_VIDEO_DECODER, ENG_NVDEC(0) }, @@ -185,6 +197,7 @@ gpuGetClassDescriptorList_TU106(POBJGPU pGpu, NvU32 *pNumClasses) { NVC57B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, { NVC57D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, { NVC57E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, + { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_A, ENG_GR(0) }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, { TURING_COMPUTE_A, ENG_GR(0) }, @@ -200,16 +213,18 @@ gpuGetClassDescriptorList_TU106(POBJGPU pGpu, NvU32 *pNumClasses) #define HALTU106_NUM_CLASS_DESCS (sizeof(halTU106ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) - ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALTU106_NUM_CLASS_DESCS); + #define HALTU106_NUM_CLASSES 52 - *pNumClasses = HALTU106_NUM_CLASS_DESCS; + ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALTU106_NUM_CLASSES); + + *pNumClassDescriptors = HALTU106_NUM_CLASS_DESCS; return halTU106ClassDescriptorList; } const CLASSDESCRIPTOR * -gpuGetClassDescriptorList_TU116(POBJGPU pGpu, NvU32 *pNumClasses) +gpuGetClassDescriptorList_TU116(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { static const CLASSDESCRIPTOR halTU116ClassDescriptorList[] = { { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, @@ -234,6 +249,8 @@ gpuGetClassDescriptorList_TU116(POBJGPU pGpu, NvU32 *pNumClasses) { NV50_MEMORY_VIRTUAL, ENG_DMA }, { NV50_P2P, ENG_BUS }, { NV50_THIRD_PARTY_P2P, ENG_BUS }, + { NVA081_VGPU_CONFIG, ENG_GPU }, + { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, { NVC371_DISP_SF_USER, ENG_KERNEL_DISPLAY }, { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY }, { NVC4B0_VIDEO_DECODER, ENG_NVDEC(0) }, @@ -244,6 +261,7 @@ gpuGetClassDescriptorList_TU116(POBJGPU pGpu, NvU32 *pNumClasses) { NVC57B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, { NVC57D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, { NVC57E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, + { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_A, ENG_GR(0) }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, { TURING_COMPUTE_A, ENG_GR(0) }, @@ -259,16 +277,18 @@ gpuGetClassDescriptorList_TU116(POBJGPU pGpu, NvU32 *pNumClasses) #define HALTU116_NUM_CLASS_DESCS (sizeof(halTU116ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) - ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALTU116_NUM_CLASS_DESCS); + #define HALTU116_NUM_CLASSES 52 - *pNumClasses = HALTU116_NUM_CLASS_DESCS; + ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALTU116_NUM_CLASSES); + + *pNumClassDescriptors = HALTU116_NUM_CLASS_DESCS; return halTU116ClassDescriptorList; } const CLASSDESCRIPTOR * -gpuGetClassDescriptorList_TU117(POBJGPU pGpu, NvU32 *pNumClasses) +gpuGetClassDescriptorList_TU117(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { static const CLASSDESCRIPTOR halTU117ClassDescriptorList[] = { { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, @@ -293,6 +313,8 @@ gpuGetClassDescriptorList_TU117(POBJGPU pGpu, NvU32 *pNumClasses) { NV50_MEMORY_VIRTUAL, ENG_DMA }, { NV50_P2P, ENG_BUS }, { NV50_THIRD_PARTY_P2P, ENG_BUS }, + { NVA081_VGPU_CONFIG, ENG_GPU }, + { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, { NVB4B7_VIDEO_ENCODER, ENG_MSENC(0) }, { NVC371_DISP_SF_USER, ENG_KERNEL_DISPLAY }, { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY }, @@ -303,6 +325,7 @@ gpuGetClassDescriptorList_TU117(POBJGPU pGpu, NvU32 *pNumClasses) { NVC57B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, { NVC57D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, { NVC57E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, + { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_A, ENG_GR(0) }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, { TURING_COMPUTE_A, ENG_GR(0) }, @@ -318,16 +341,18 @@ gpuGetClassDescriptorList_TU117(POBJGPU pGpu, NvU32 *pNumClasses) #define HALTU117_NUM_CLASS_DESCS (sizeof(halTU117ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) - ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALTU117_NUM_CLASS_DESCS); + #define HALTU117_NUM_CLASSES 52 - *pNumClasses = HALTU117_NUM_CLASS_DESCS; + ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALTU117_NUM_CLASSES); + + *pNumClassDescriptors = HALTU117_NUM_CLASS_DESCS; return halTU117ClassDescriptorList; } const CLASSDESCRIPTOR * -gpuGetClassDescriptorList_GA100(POBJGPU pGpu, NvU32 *pNumClasses) +gpuGetClassDescriptorList_GA100(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { static const CLASSDESCRIPTOR halGA100ClassDescriptorList[] = { { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, @@ -370,6 +395,8 @@ gpuGetClassDescriptorList_GA100(POBJGPU pGpu, NvU32 *pNumClasses) { NV50_MEMORY_VIRTUAL, ENG_DMA }, { NV50_P2P, ENG_BUS }, { NV50_THIRD_PARTY_P2P, ENG_BUS }, + { NVA081_VGPU_CONFIG, ENG_GPU }, + { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, { NVC4D1_VIDEO_NVJPG, ENG_NVJPG }, { NVC6B0_VIDEO_DECODER, ENG_NVDEC(0) }, { NVC6B0_VIDEO_DECODER, ENG_NVDEC(1) }, @@ -377,6 +404,7 @@ gpuGetClassDescriptorList_GA100(POBJGPU pGpu, NvU32 *pNumClasses) { NVC6B0_VIDEO_DECODER, ENG_NVDEC(3) }, { NVC6B0_VIDEO_DECODER, ENG_NVDEC(4) }, { NVC6FA_VIDEO_OFA, ENG_OFA }, + { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, { TURING_USERMODE_A, ENG_GPU }, { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, @@ -385,16 +413,18 @@ gpuGetClassDescriptorList_GA100(POBJGPU pGpu, NvU32 *pNumClasses) #define HALGA100_NUM_CLASS_DESCS (sizeof(halGA100ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) - ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALGA100_NUM_CLASS_DESCS); + #define HALGA100_NUM_CLASSES 46 - *pNumClasses = HALGA100_NUM_CLASS_DESCS; + ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALGA100_NUM_CLASSES); + + *pNumClassDescriptors = HALGA100_NUM_CLASS_DESCS; return halGA100ClassDescriptorList; } const CLASSDESCRIPTOR * -gpuGetClassDescriptorList_GA102(POBJGPU pGpu, NvU32 *pNumClasses) +gpuGetClassDescriptorList_GA102(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { static const CLASSDESCRIPTOR halGA102ClassDescriptorList[] = { { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, @@ -428,6 +458,8 @@ gpuGetClassDescriptorList_GA102(POBJGPU pGpu, NvU32 *pNumClasses) { NV50_MEMORY_VIRTUAL, ENG_DMA }, { NV50_P2P, ENG_BUS }, { NV50_THIRD_PARTY_P2P, ENG_BUS }, + { NVA081_VGPU_CONFIG, ENG_GPU }, + { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY }, { NVC670_DISPLAY, ENG_KERNEL_DISPLAY }, { NVC671_DISP_SF_USER, ENG_KERNEL_DISPLAY }, @@ -436,10 +468,12 @@ gpuGetClassDescriptorList_GA102(POBJGPU pGpu, NvU32 *pNumClasses) { NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, { NVC67D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, { NVC67E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, + { NVC77F_ANY_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, { NVC7B0_VIDEO_DECODER, ENG_NVDEC(0) }, { NVC7B0_VIDEO_DECODER, ENG_NVDEC(1) }, { NVC7B7_VIDEO_ENCODER, ENG_MSENC(0) }, { NVC7FA_VIDEO_OFA, ENG_OFA }, + { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, { TURING_USERMODE_A, ENG_GPU }, { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, @@ -448,16 +482,18 @@ gpuGetClassDescriptorList_GA102(POBJGPU pGpu, NvU32 *pNumClasses) #define HALGA102_NUM_CLASS_DESCS (sizeof(halGA102ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) - ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALGA102_NUM_CLASS_DESCS); + #define HALGA102_NUM_CLASSES 58 - *pNumClasses = HALGA102_NUM_CLASS_DESCS; + ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALGA102_NUM_CLASSES); + + *pNumClassDescriptors = HALGA102_NUM_CLASS_DESCS; return halGA102ClassDescriptorList; } const CLASSDESCRIPTOR * -gpuGetClassDescriptorList_GA103(POBJGPU pGpu, NvU32 *pNumClasses) +gpuGetClassDescriptorList_GA103(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { static const CLASSDESCRIPTOR halGA103ClassDescriptorList[] = { { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, @@ -491,6 +527,8 @@ gpuGetClassDescriptorList_GA103(POBJGPU pGpu, NvU32 *pNumClasses) { NV50_MEMORY_VIRTUAL, ENG_DMA }, { NV50_P2P, ENG_BUS }, { NV50_THIRD_PARTY_P2P, ENG_BUS }, + { NVA081_VGPU_CONFIG, ENG_GPU }, + { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY }, { NVC670_DISPLAY, ENG_KERNEL_DISPLAY }, { NVC671_DISP_SF_USER, ENG_KERNEL_DISPLAY }, @@ -499,10 +537,12 @@ gpuGetClassDescriptorList_GA103(POBJGPU pGpu, NvU32 *pNumClasses) { NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, { NVC67D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, { NVC67E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, + { NVC77F_ANY_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, { NVC7B0_VIDEO_DECODER, ENG_NVDEC(0) }, { NVC7B0_VIDEO_DECODER, ENG_NVDEC(1) }, { NVC7B7_VIDEO_ENCODER, ENG_MSENC(0) }, { NVC7FA_VIDEO_OFA, ENG_OFA }, + { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, { TURING_USERMODE_A, ENG_GPU }, { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, @@ -511,16 +551,18 @@ gpuGetClassDescriptorList_GA103(POBJGPU pGpu, NvU32 *pNumClasses) #define HALGA103_NUM_CLASS_DESCS (sizeof(halGA103ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) - ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALGA103_NUM_CLASS_DESCS); + #define HALGA103_NUM_CLASSES 58 - *pNumClasses = HALGA103_NUM_CLASS_DESCS; + ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALGA103_NUM_CLASSES); + + *pNumClassDescriptors = HALGA103_NUM_CLASS_DESCS; return halGA103ClassDescriptorList; } const CLASSDESCRIPTOR * -gpuGetClassDescriptorList_GA104(POBJGPU pGpu, NvU32 *pNumClasses) +gpuGetClassDescriptorList_GA104(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { static const CLASSDESCRIPTOR halGA104ClassDescriptorList[] = { { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, @@ -554,6 +596,8 @@ gpuGetClassDescriptorList_GA104(POBJGPU pGpu, NvU32 *pNumClasses) { NV50_MEMORY_VIRTUAL, ENG_DMA }, { NV50_P2P, ENG_BUS }, { NV50_THIRD_PARTY_P2P, ENG_BUS }, + { NVA081_VGPU_CONFIG, ENG_GPU }, + { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY }, { NVC670_DISPLAY, ENG_KERNEL_DISPLAY }, { NVC671_DISP_SF_USER, ENG_KERNEL_DISPLAY }, @@ -562,10 +606,12 @@ gpuGetClassDescriptorList_GA104(POBJGPU pGpu, NvU32 *pNumClasses) { NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, { NVC67D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, { NVC67E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, + { NVC77F_ANY_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, { NVC7B0_VIDEO_DECODER, ENG_NVDEC(0) }, { NVC7B0_VIDEO_DECODER, ENG_NVDEC(1) }, { NVC7B7_VIDEO_ENCODER, ENG_MSENC(0) }, { NVC7FA_VIDEO_OFA, ENG_OFA }, + { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, { TURING_USERMODE_A, ENG_GPU }, { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, @@ -574,16 +620,18 @@ gpuGetClassDescriptorList_GA104(POBJGPU pGpu, NvU32 *pNumClasses) #define HALGA104_NUM_CLASS_DESCS (sizeof(halGA104ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) - ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALGA104_NUM_CLASS_DESCS); + #define HALGA104_NUM_CLASSES 58 - *pNumClasses = HALGA104_NUM_CLASS_DESCS; + ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALGA104_NUM_CLASSES); + + *pNumClassDescriptors = HALGA104_NUM_CLASS_DESCS; return halGA104ClassDescriptorList; } const CLASSDESCRIPTOR * -gpuGetClassDescriptorList_GA106(POBJGPU pGpu, NvU32 *pNumClasses) +gpuGetClassDescriptorList_GA106(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { static const CLASSDESCRIPTOR halGA106ClassDescriptorList[] = { { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, @@ -617,6 +665,8 @@ gpuGetClassDescriptorList_GA106(POBJGPU pGpu, NvU32 *pNumClasses) { NV50_MEMORY_VIRTUAL, ENG_DMA }, { NV50_P2P, ENG_BUS }, { NV50_THIRD_PARTY_P2P, ENG_BUS }, + { NVA081_VGPU_CONFIG, ENG_GPU }, + { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY }, { NVC670_DISPLAY, ENG_KERNEL_DISPLAY }, { NVC671_DISP_SF_USER, ENG_KERNEL_DISPLAY }, @@ -625,10 +675,12 @@ gpuGetClassDescriptorList_GA106(POBJGPU pGpu, NvU32 *pNumClasses) { NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, { NVC67D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, { NVC67E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, + { NVC77F_ANY_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, { NVC7B0_VIDEO_DECODER, ENG_NVDEC(0) }, { NVC7B0_VIDEO_DECODER, ENG_NVDEC(1) }, { NVC7B7_VIDEO_ENCODER, ENG_MSENC(0) }, { NVC7FA_VIDEO_OFA, ENG_OFA }, + { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, { TURING_USERMODE_A, ENG_GPU }, { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, @@ -637,16 +689,18 @@ gpuGetClassDescriptorList_GA106(POBJGPU pGpu, NvU32 *pNumClasses) #define HALGA106_NUM_CLASS_DESCS (sizeof(halGA106ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) - ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALGA106_NUM_CLASS_DESCS); + #define HALGA106_NUM_CLASSES 58 - *pNumClasses = HALGA106_NUM_CLASS_DESCS; + ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALGA106_NUM_CLASSES); + + *pNumClassDescriptors = HALGA106_NUM_CLASS_DESCS; return halGA106ClassDescriptorList; } const CLASSDESCRIPTOR * -gpuGetClassDescriptorList_GA107(POBJGPU pGpu, NvU32 *pNumClasses) +gpuGetClassDescriptorList_GA107(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { static const CLASSDESCRIPTOR halGA107ClassDescriptorList[] = { { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, @@ -680,6 +734,8 @@ gpuGetClassDescriptorList_GA107(POBJGPU pGpu, NvU32 *pNumClasses) { NV50_MEMORY_VIRTUAL, ENG_DMA }, { NV50_P2P, ENG_BUS }, { NV50_THIRD_PARTY_P2P, ENG_BUS }, + { NVA081_VGPU_CONFIG, ENG_GPU }, + { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY }, { NVC670_DISPLAY, ENG_KERNEL_DISPLAY }, { NVC671_DISP_SF_USER, ENG_KERNEL_DISPLAY }, @@ -688,10 +744,12 @@ gpuGetClassDescriptorList_GA107(POBJGPU pGpu, NvU32 *pNumClasses) { NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, { NVC67D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, { NVC67E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, + { NVC77F_ANY_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, { NVC7B0_VIDEO_DECODER, ENG_NVDEC(0) }, { NVC7B0_VIDEO_DECODER, ENG_NVDEC(1) }, { NVC7B7_VIDEO_ENCODER, ENG_MSENC(0) }, { NVC7FA_VIDEO_OFA, ENG_OFA }, + { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, { TURING_USERMODE_A, ENG_GPU }, { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, @@ -700,16 +758,18 @@ gpuGetClassDescriptorList_GA107(POBJGPU pGpu, NvU32 *pNumClasses) #define HALGA107_NUM_CLASS_DESCS (sizeof(halGA107ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) - ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALGA107_NUM_CLASS_DESCS); + #define HALGA107_NUM_CLASSES 58 - *pNumClasses = HALGA107_NUM_CLASS_DESCS; + ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALGA107_NUM_CLASSES); + + *pNumClassDescriptors = HALGA107_NUM_CLASS_DESCS; return halGA107ClassDescriptorList; } const CLASSDESCRIPTOR * -gpuGetClassDescriptorList_AD102(POBJGPU pGpu, NvU32 *pNumClasses) +gpuGetClassDescriptorList_AD102(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { static const CLASSDESCRIPTOR halAD102ClassDescriptorList[] = { { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, @@ -743,6 +803,8 @@ gpuGetClassDescriptorList_AD102(POBJGPU pGpu, NvU32 *pNumClasses) { NV50_MEMORY_VIRTUAL, ENG_DMA }, { NV50_P2P, ENG_BUS }, { NV50_THIRD_PARTY_P2P, ENG_BUS }, + { NVA081_VGPU_CONFIG, ENG_GPU }, + { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY }, { NVC67A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY }, { NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, @@ -751,6 +813,7 @@ gpuGetClassDescriptorList_AD102(POBJGPU pGpu, NvU32 *pNumClasses) { NVC771_DISP_SF_USER, ENG_KERNEL_DISPLAY }, { NVC773_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY }, { NVC77D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, + { NVC77F_ANY_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, { NVC9B0_VIDEO_DECODER, ENG_NVDEC(0) }, { NVC9B0_VIDEO_DECODER, ENG_NVDEC(1) }, { NVC9B0_VIDEO_DECODER, ENG_NVDEC(2) }, @@ -763,6 +826,7 @@ gpuGetClassDescriptorList_AD102(POBJGPU pGpu, NvU32 *pNumClasses) { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(2) }, { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(3) }, { NVC9FA_VIDEO_OFA, ENG_OFA }, + { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, { TURING_USERMODE_A, ENG_GPU }, { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, @@ -771,16 +835,18 @@ gpuGetClassDescriptorList_AD102(POBJGPU pGpu, NvU32 *pNumClasses) #define HALAD102_NUM_CLASS_DESCS (sizeof(halAD102ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) - ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALAD102_NUM_CLASS_DESCS); + #define HALAD102_NUM_CLASSES 59 - *pNumClasses = HALAD102_NUM_CLASS_DESCS; + ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALAD102_NUM_CLASSES); + + *pNumClassDescriptors = HALAD102_NUM_CLASS_DESCS; return halAD102ClassDescriptorList; } const CLASSDESCRIPTOR * -gpuGetClassDescriptorList_AD103(POBJGPU pGpu, NvU32 *pNumClasses) +gpuGetClassDescriptorList_AD103(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { static const CLASSDESCRIPTOR halAD103ClassDescriptorList[] = { { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, @@ -814,6 +880,8 @@ gpuGetClassDescriptorList_AD103(POBJGPU pGpu, NvU32 *pNumClasses) { NV50_MEMORY_VIRTUAL, ENG_DMA }, { NV50_P2P, ENG_BUS }, { NV50_THIRD_PARTY_P2P, ENG_BUS }, + { NVA081_VGPU_CONFIG, ENG_GPU }, + { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY }, { NVC67A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY }, { NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, @@ -822,6 +890,7 @@ gpuGetClassDescriptorList_AD103(POBJGPU pGpu, NvU32 *pNumClasses) { NVC771_DISP_SF_USER, ENG_KERNEL_DISPLAY }, { NVC773_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY }, { NVC77D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, + { NVC77F_ANY_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, { NVC9B0_VIDEO_DECODER, ENG_NVDEC(0) }, { NVC9B0_VIDEO_DECODER, ENG_NVDEC(1) }, { NVC9B0_VIDEO_DECODER, ENG_NVDEC(2) }, @@ -834,6 +903,7 @@ gpuGetClassDescriptorList_AD103(POBJGPU pGpu, NvU32 *pNumClasses) { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(2) }, { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(3) }, { NVC9FA_VIDEO_OFA, ENG_OFA }, + { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, { TURING_USERMODE_A, ENG_GPU }, { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, @@ -842,16 +912,18 @@ gpuGetClassDescriptorList_AD103(POBJGPU pGpu, NvU32 *pNumClasses) #define HALAD103_NUM_CLASS_DESCS (sizeof(halAD103ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) - ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALAD103_NUM_CLASS_DESCS); + #define HALAD103_NUM_CLASSES 59 - *pNumClasses = HALAD103_NUM_CLASS_DESCS; + ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALAD103_NUM_CLASSES); + + *pNumClassDescriptors = HALAD103_NUM_CLASS_DESCS; return halAD103ClassDescriptorList; } const CLASSDESCRIPTOR * -gpuGetClassDescriptorList_AD104(POBJGPU pGpu, NvU32 *pNumClasses) +gpuGetClassDescriptorList_AD104(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { static const CLASSDESCRIPTOR halAD104ClassDescriptorList[] = { { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, @@ -885,6 +957,8 @@ gpuGetClassDescriptorList_AD104(POBJGPU pGpu, NvU32 *pNumClasses) { NV50_MEMORY_VIRTUAL, ENG_DMA }, { NV50_P2P, ENG_BUS }, { NV50_THIRD_PARTY_P2P, ENG_BUS }, + { NVA081_VGPU_CONFIG, ENG_GPU }, + { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY }, { NVC67A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY }, { NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, @@ -893,6 +967,7 @@ gpuGetClassDescriptorList_AD104(POBJGPU pGpu, NvU32 *pNumClasses) { NVC771_DISP_SF_USER, ENG_KERNEL_DISPLAY }, { NVC773_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY }, { NVC77D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, + { NVC77F_ANY_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, { NVC9B0_VIDEO_DECODER, ENG_NVDEC(0) }, { NVC9B0_VIDEO_DECODER, ENG_NVDEC(1) }, { NVC9B0_VIDEO_DECODER, ENG_NVDEC(2) }, @@ -905,6 +980,7 @@ gpuGetClassDescriptorList_AD104(POBJGPU pGpu, NvU32 *pNumClasses) { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(2) }, { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(3) }, { NVC9FA_VIDEO_OFA, ENG_OFA }, + { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, { TURING_USERMODE_A, ENG_GPU }, { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, @@ -913,16 +989,172 @@ gpuGetClassDescriptorList_AD104(POBJGPU pGpu, NvU32 *pNumClasses) #define HALAD104_NUM_CLASS_DESCS (sizeof(halAD104ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) - ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALAD104_NUM_CLASS_DESCS); + #define HALAD104_NUM_CLASSES 59 - *pNumClasses = HALAD104_NUM_CLASS_DESCS; + ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALAD104_NUM_CLASSES); + + *pNumClassDescriptors = HALAD104_NUM_CLASS_DESCS; return halAD104ClassDescriptorList; } const CLASSDESCRIPTOR * -gpuGetClassDescriptorList_GH100(POBJGPU pGpu, NvU32 *pNumClasses) +gpuGetClassDescriptorList_AD106(POBJGPU pGpu, NvU32 *pNumClassDescriptors) +{ + static const CLASSDESCRIPTOR halAD106ClassDescriptorList[] = { + { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, + { ADA_A, ENG_GR(0) }, + { ADA_COMPUTE_A, ENG_GR(0) }, + { AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, + { AMPERE_DMA_COPY_B, ENG_CE(0) }, + { AMPERE_DMA_COPY_B, ENG_CE(1) }, + { AMPERE_DMA_COPY_B, ENG_CE(2) }, + { AMPERE_DMA_COPY_B, ENG_CE(3) }, + { AMPERE_DMA_COPY_B, ENG_CE(4) }, + { AMPERE_USERMODE_A, ENG_GPU }, + { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO }, + { FERMI_TWOD_A, ENG_GR(0) }, + { FERMI_VASPACE_A, ENG_DMA }, + { G84_PERFBUFFER, ENG_BUS }, + { GF100_DISP_SW, ENG_SW }, + { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_MASTER, ENG_GPU }, + { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, + { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, + { GP100_UVM_SW, ENG_SW }, + { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, + { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, + { MMU_FAULT_BUFFER, ENG_GR(0) }, + { NV0060_SYNC_GPU_BOOST, ENG_GPU }, + { NV01_MEMORY_VIRTUAL, ENG_DMA }, + { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY }, + { NV04_SOFTWARE_TEST, ENG_SW }, + { NV50_DEFERRED_API_CLASS, ENG_SW }, + { NV50_MEMORY_VIRTUAL, ENG_DMA }, + { NV50_P2P, ENG_BUS }, + { NV50_THIRD_PARTY_P2P, ENG_BUS }, + { NVA081_VGPU_CONFIG, ENG_GPU }, + { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, + { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY }, + { NVC67A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY }, + { NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, + { NVC67E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, + { NVC770_DISPLAY, ENG_KERNEL_DISPLAY }, + { NVC771_DISP_SF_USER, ENG_KERNEL_DISPLAY }, + { NVC773_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY }, + { NVC77D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, + { NVC77F_ANY_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, + { NVC9B0_VIDEO_DECODER, ENG_NVDEC(0) }, + { NVC9B0_VIDEO_DECODER, ENG_NVDEC(1) }, + { NVC9B0_VIDEO_DECODER, ENG_NVDEC(2) }, + { NVC9B0_VIDEO_DECODER, ENG_NVDEC(3) }, + { NVC9B7_VIDEO_ENCODER, ENG_MSENC(0) }, + { NVC9B7_VIDEO_ENCODER, ENG_MSENC(1) }, + { NVC9B7_VIDEO_ENCODER, ENG_MSENC(2) }, + { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(0) }, + { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(1) }, + { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(2) }, + { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(3) }, + { NVC9FA_VIDEO_OFA, ENG_OFA }, + { RM_USER_SHARED_DATA, ENG_GPU }, + { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, + { TURING_USERMODE_A, ENG_GPU }, + { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, + { VOLTA_USERMODE_A, ENG_GPU }, + }; + + #define HALAD106_NUM_CLASS_DESCS (sizeof(halAD106ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) + + #define HALAD106_NUM_CLASSES 59 + + ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALAD106_NUM_CLASSES); + + *pNumClassDescriptors = HALAD106_NUM_CLASS_DESCS; + return halAD106ClassDescriptorList; +} + + + +const CLASSDESCRIPTOR * +gpuGetClassDescriptorList_AD107(POBJGPU pGpu, NvU32 *pNumClassDescriptors) +{ + static const CLASSDESCRIPTOR halAD107ClassDescriptorList[] = { + { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, + { ADA_A, ENG_GR(0) }, + { ADA_COMPUTE_A, ENG_GR(0) }, + { AMPERE_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, + { AMPERE_DMA_COPY_B, ENG_CE(0) }, + { AMPERE_DMA_COPY_B, ENG_CE(1) }, + { AMPERE_DMA_COPY_B, ENG_CE(2) }, + { AMPERE_DMA_COPY_B, ENG_CE(3) }, + { AMPERE_DMA_COPY_B, ENG_CE(4) }, + { AMPERE_USERMODE_A, ENG_GPU }, + { FERMI_CONTEXT_SHARE_A, ENG_KERNEL_FIFO }, + { FERMI_TWOD_A, ENG_GR(0) }, + { FERMI_VASPACE_A, ENG_DMA }, + { G84_PERFBUFFER, ENG_BUS }, + { GF100_DISP_SW, ENG_SW }, + { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_MASTER, ENG_GPU }, + { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, + { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, + { GP100_UVM_SW, ENG_SW }, + { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, + { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, + { MMU_FAULT_BUFFER, ENG_GR(0) }, + { NV0060_SYNC_GPU_BOOST, ENG_GPU }, + { NV01_MEMORY_VIRTUAL, ENG_DMA }, + { NV04_DISPLAY_COMMON, ENG_KERNEL_DISPLAY }, + { NV04_SOFTWARE_TEST, ENG_SW }, + { NV50_DEFERRED_API_CLASS, ENG_SW }, + { NV50_MEMORY_VIRTUAL, ENG_DMA }, + { NV50_P2P, ENG_BUS }, + { NV50_THIRD_PARTY_P2P, ENG_BUS }, + { NVA081_VGPU_CONFIG, ENG_GPU }, + { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, + { NVC372_DISPLAY_SW, ENG_KERNEL_DISPLAY }, + { NVC67A_CURSOR_IMM_CHANNEL_PIO, ENG_KERNEL_DISPLAY }, + { NVC67B_WINDOW_IMM_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, + { NVC67E_WINDOW_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, + { NVC770_DISPLAY, ENG_KERNEL_DISPLAY }, + { NVC771_DISP_SF_USER, ENG_KERNEL_DISPLAY }, + { NVC773_DISP_CAPABILITIES, ENG_KERNEL_DISPLAY }, + { NVC77D_CORE_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, + { NVC77F_ANY_CHANNEL_DMA, ENG_KERNEL_DISPLAY }, + { NVC9B0_VIDEO_DECODER, ENG_NVDEC(0) }, + { NVC9B0_VIDEO_DECODER, ENG_NVDEC(1) }, + { NVC9B0_VIDEO_DECODER, ENG_NVDEC(2) }, + { NVC9B0_VIDEO_DECODER, ENG_NVDEC(3) }, + { NVC9B7_VIDEO_ENCODER, ENG_MSENC(0) }, + { NVC9B7_VIDEO_ENCODER, ENG_MSENC(1) }, + { NVC9B7_VIDEO_ENCODER, ENG_MSENC(2) }, + { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(0) }, + { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(1) }, + { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(2) }, + { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(3) }, + { NVC9FA_VIDEO_OFA, ENG_OFA }, + { RM_USER_SHARED_DATA, ENG_GPU }, + { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, + { TURING_USERMODE_A, ENG_GPU }, + { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, + { VOLTA_USERMODE_A, ENG_GPU }, + }; + + #define HALAD107_NUM_CLASS_DESCS (sizeof(halAD107ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) + + #define HALAD107_NUM_CLASSES 59 + + ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALAD107_NUM_CLASSES); + + *pNumClassDescriptors = HALAD107_NUM_CLASS_DESCS; + return halAD107ClassDescriptorList; +} + + + +const CLASSDESCRIPTOR * +gpuGetClassDescriptorList_GH100(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { static const CLASSDESCRIPTOR halGH100ClassDescriptorList[] = { { ACCESS_COUNTER_NOTIFY_BUFFER, ENG_GR(0) }, @@ -967,6 +1199,8 @@ gpuGetClassDescriptorList_GH100(POBJGPU pGpu, NvU32 *pNumClasses) { NV50_MEMORY_VIRTUAL, ENG_DMA }, { NV50_P2P, ENG_BUS }, { NV50_THIRD_PARTY_P2P, ENG_BUS }, + { NVA081_VGPU_CONFIG, ENG_GPU }, + { NVA084_KERNEL_HOST_VGPU_DEVICE, ENG_GPU }, { NVB8B0_VIDEO_DECODER, ENG_NVDEC(0) }, { NVB8B0_VIDEO_DECODER, ENG_NVDEC(1) }, { NVB8B0_VIDEO_DECODER, ENG_NVDEC(2) }, @@ -984,6 +1218,7 @@ gpuGetClassDescriptorList_GH100(POBJGPU pGpu, NvU32 *pNumClasses) { NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(6) }, { NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(7) }, { NVB8FA_VIDEO_OFA, ENG_OFA }, + { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, { TURING_USERMODE_A, ENG_GPU }, { VOLTA_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, @@ -992,9 +1227,11 @@ gpuGetClassDescriptorList_GH100(POBJGPU pGpu, NvU32 *pNumClasses) #define HALGH100_NUM_CLASS_DESCS (sizeof(halGH100ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) - ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALGH100_NUM_CLASS_DESCS); + #define HALGH100_NUM_CLASSES 49 - *pNumClasses = HALGH100_NUM_CLASS_DESCS; + ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALGH100_NUM_CLASSES); + + *pNumClassDescriptors = HALGH100_NUM_CLASS_DESCS; return halGH100ClassDescriptorList; } diff --git a/src/nvidia/generated/g_gpu_db_nvoc.h b/src/nvidia/generated/g_gpu_db_nvoc.h index 3013f662e..38c4b0a1c 100644 --- a/src/nvidia/generated/g_gpu_db_nvoc.h +++ b/src/nvidia/generated/g_gpu_db_nvoc.h @@ -134,8 +134,10 @@ NV_STATUS __nvoc_objCreate_GpuDb(GpuDb**, Dynamic*, NvU32); __nvoc_objCreate_GpuDb((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) NV_STATUS gpudbConstruct_IMPL(struct GpuDb *arg_pGpuDb); + #define __nvoc_gpudbConstruct(arg_pGpuDb) gpudbConstruct_IMPL(arg_pGpuDb) void gpudbDestruct_IMPL(struct GpuDb *pGpuDb); + #define __nvoc_gpudbDestruct(pGpuDb) gpudbDestruct_IMPL(pGpuDb) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_gpu_group_nvoc.h b/src/nvidia/generated/g_gpu_group_nvoc.h index dca3585c8..48f550207 100644 --- a/src/nvidia/generated/g_gpu_group_nvoc.h +++ b/src/nvidia/generated/g_gpu_group_nvoc.h @@ -181,6 +181,7 @@ NV_STATUS __nvoc_objCreate_OBJGPUGRP(OBJGPUGRP**, Dynamic*, NvU32); __nvoc_objCreate_OBJGPUGRP((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) NV_STATUS gpugrpCreate_IMPL(struct OBJGPUGRP *pGpuGrp, NvU32 gpuMask); + #ifdef __nvoc_gpu_group_h_disabled static inline NV_STATUS gpugrpCreate(struct OBJGPUGRP *pGpuGrp, NvU32 gpuMask) { NV_ASSERT_FAILED_PRECOMP("OBJGPUGRP was disabled!"); @@ -191,6 +192,7 @@ static inline NV_STATUS gpugrpCreate(struct OBJGPUGRP *pGpuGrp, NvU32 gpuMask) { #endif //__nvoc_gpu_group_h_disabled NV_STATUS gpugrpDestroy_IMPL(struct OBJGPUGRP *pGpuGrp); + #ifdef __nvoc_gpu_group_h_disabled static inline NV_STATUS gpugrpDestroy(struct OBJGPUGRP *pGpuGrp) { NV_ASSERT_FAILED_PRECOMP("OBJGPUGRP was disabled!"); @@ -201,6 +203,7 @@ static inline NV_STATUS gpugrpDestroy(struct OBJGPUGRP *pGpuGrp) { #endif //__nvoc_gpu_group_h_disabled NvU32 gpugrpGetGpuMask_IMPL(struct OBJGPUGRP *pGpuGrp); + #ifdef __nvoc_gpu_group_h_disabled static inline NvU32 gpugrpGetGpuMask(struct OBJGPUGRP *pGpuGrp) { NV_ASSERT_FAILED_PRECOMP("OBJGPUGRP was disabled!"); @@ -211,6 +214,7 @@ static inline NvU32 gpugrpGetGpuMask(struct OBJGPUGRP *pGpuGrp) { #endif //__nvoc_gpu_group_h_disabled void gpugrpSetGpuMask_IMPL(struct OBJGPUGRP *pGpuGrp, NvU32 gpuMask); + #ifdef __nvoc_gpu_group_h_disabled static inline void gpugrpSetGpuMask(struct OBJGPUGRP *pGpuGrp, NvU32 gpuMask) { NV_ASSERT_FAILED_PRECOMP("OBJGPUGRP was disabled!"); @@ -220,6 +224,7 @@ static inline void gpugrpSetGpuMask(struct OBJGPUGRP *pGpuGrp, NvU32 gpuMask) { #endif //__nvoc_gpu_group_h_disabled NvBool gpugrpGetBcEnabledState_IMPL(struct OBJGPUGRP *pGpuGrp); + #ifdef __nvoc_gpu_group_h_disabled static inline NvBool gpugrpGetBcEnabledState(struct OBJGPUGRP *pGpuGrp) { NV_ASSERT_FAILED_PRECOMP("OBJGPUGRP was disabled!"); @@ -230,6 +235,7 @@ static inline NvBool gpugrpGetBcEnabledState(struct OBJGPUGRP *pGpuGrp) { #endif //__nvoc_gpu_group_h_disabled void gpugrpSetBcEnabledState_IMPL(struct OBJGPUGRP *pGpuGrp, NvBool bcState); + #ifdef __nvoc_gpu_group_h_disabled static inline void gpugrpSetBcEnabledState(struct OBJGPUGRP *pGpuGrp, NvBool bcState) { NV_ASSERT_FAILED_PRECOMP("OBJGPUGRP was disabled!"); @@ -239,6 +245,7 @@ static inline void gpugrpSetBcEnabledState(struct OBJGPUGRP *pGpuGrp, NvBool bcS #endif //__nvoc_gpu_group_h_disabled void gpugrpSetParentGpu_IMPL(struct OBJGPUGRP *pGpuGrp, struct OBJGPU *pParentGpu); + #ifdef __nvoc_gpu_group_h_disabled static inline void gpugrpSetParentGpu(struct OBJGPUGRP *pGpuGrp, struct OBJGPU *pParentGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPUGRP was disabled!"); @@ -248,6 +255,7 @@ static inline void gpugrpSetParentGpu(struct OBJGPUGRP *pGpuGrp, struct OBJGPU * #endif //__nvoc_gpu_group_h_disabled struct OBJGPU *gpugrpGetParentGpu_IMPL(struct OBJGPUGRP *pGpuGrp); + #ifdef __nvoc_gpu_group_h_disabled static inline struct OBJGPU *gpugrpGetParentGpu(struct OBJGPUGRP *pGpuGrp) { NV_ASSERT_FAILED_PRECOMP("OBJGPUGRP was disabled!"); @@ -258,6 +266,7 @@ static inline struct OBJGPU *gpugrpGetParentGpu(struct OBJGPUGRP *pGpuGrp) { #endif //__nvoc_gpu_group_h_disabled NV_STATUS gpugrpCreateGlobalVASpace_IMPL(struct OBJGPUGRP *pGpuGrp, struct OBJGPU *pGpu, NvU32 vaspaceClass, NvU64 vaStart, NvU64 vaEnd, NvU32 vaspaceFlags, struct OBJVASPACE **ppGlobalVAS); + #ifdef __nvoc_gpu_group_h_disabled static inline NV_STATUS gpugrpCreateGlobalVASpace(struct OBJGPUGRP *pGpuGrp, struct OBJGPU *pGpu, NvU32 vaspaceClass, NvU64 vaStart, NvU64 vaEnd, NvU32 vaspaceFlags, struct OBJVASPACE **ppGlobalVAS) { NV_ASSERT_FAILED_PRECOMP("OBJGPUGRP was disabled!"); @@ -268,6 +277,7 @@ static inline NV_STATUS gpugrpCreateGlobalVASpace(struct OBJGPUGRP *pGpuGrp, str #endif //__nvoc_gpu_group_h_disabled NV_STATUS gpugrpDestroyGlobalVASpace_IMPL(struct OBJGPUGRP *pGpuGrp, struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_group_h_disabled static inline NV_STATUS gpugrpDestroyGlobalVASpace(struct OBJGPUGRP *pGpuGrp, struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPUGRP was disabled!"); @@ -278,6 +288,7 @@ static inline NV_STATUS gpugrpDestroyGlobalVASpace(struct OBJGPUGRP *pGpuGrp, st #endif //__nvoc_gpu_group_h_disabled NV_STATUS gpugrpGetGlobalVASpace_IMPL(struct OBJGPUGRP *pGpuGrp, struct OBJVASPACE **ppGlobalVAS); + #ifdef __nvoc_gpu_group_h_disabled static inline NV_STATUS gpugrpGetGlobalVASpace(struct OBJGPUGRP *pGpuGrp, struct OBJVASPACE **ppGlobalVAS) { NV_ASSERT_FAILED_PRECOMP("OBJGPUGRP was disabled!"); @@ -288,6 +299,7 @@ static inline NV_STATUS gpugrpGetGlobalVASpace(struct OBJGPUGRP *pGpuGrp, struct #endif //__nvoc_gpu_group_h_disabled NV_STATUS gpugrpGetGpuFromSubDeviceInstance_IMPL(struct OBJGPUGRP *pGpuGrp, NvU32 subDeviceInst, struct OBJGPU **ppGpu); + #ifdef __nvoc_gpu_group_h_disabled static inline NV_STATUS gpugrpGetGpuFromSubDeviceInstance(struct OBJGPUGRP *pGpuGrp, NvU32 subDeviceInst, struct OBJGPU **ppGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPUGRP was disabled!"); diff --git a/src/nvidia/generated/g_gpu_instance_subscription_nvoc.c b/src/nvidia/generated/g_gpu_instance_subscription_nvoc.c index 1c8358177..70da87a7c 100644 --- a/src/nvidia/generated/g_gpu_instance_subscription_nvoc.c +++ b/src/nvidia/generated/g_gpu_instance_subscription_nvoc.c @@ -165,6 +165,10 @@ static NV_STATUS __nvoc_thunk_RsResource_gisubscriptionUnmapFrom(struct GPUInsta return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_gisubscriptionIsDuplicate(struct GPUInstanceSubscription *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_gisubscriptionControl_Epilogue(struct GPUInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RmResource.offset), pCallContext, pParams); } @@ -275,6 +279,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_GPUInsta /*pClassInfo=*/ &(__nvoc_class_def_GPUInstanceSubscription.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "gisubscriptionCtrlCmdExecPartitionsImport" +#endif + }, + { /* [6] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) gisubscriptionCtrlCmdExecPartitionsGetProfileCapacity_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xc63701a9u, + /*paramSize=*/ sizeof(NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GPUInstanceSubscription.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "gisubscriptionCtrlCmdExecPartitionsGetProfileCapacity" #endif }, @@ -282,7 +301,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_GPUInsta const struct NVOC_EXPORT_INFO __nvoc_export_info_GPUInstanceSubscription = { - /*numEntries=*/ 6, + /*numEntries=*/ 7, /*pExportEntries=*/ __nvoc_exported_method_def_GPUInstanceSubscription }; @@ -333,6 +352,10 @@ static void __nvoc_init_funcTable_GPUInstanceSubscription_1(GPUInstanceSubscript pThis->__gisubscriptionCtrlCmdExecPartitionsGet__ = &gisubscriptionCtrlCmdExecPartitionsGet_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__gisubscriptionCtrlCmdExecPartitionsGetProfileCapacity__ = &gisubscriptionCtrlCmdExecPartitionsGetProfileCapacity_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__gisubscriptionCtrlCmdExecPartitionsGetActiveIds__ = &gisubscriptionCtrlCmdExecPartitionsGetActiveIds_IMPL; #endif @@ -381,6 +404,8 @@ static void __nvoc_init_funcTable_GPUInstanceSubscription_1(GPUInstanceSubscript pThis->__gisubscriptionUnmapFrom__ = &__nvoc_thunk_RsResource_gisubscriptionUnmapFrom; + pThis->__gisubscriptionIsDuplicate__ = &__nvoc_thunk_RsResource_gisubscriptionIsDuplicate; + pThis->__gisubscriptionControl_Epilogue__ = &__nvoc_thunk_RmResource_gisubscriptionControl_Epilogue; pThis->__gisubscriptionControlLookup__ = &__nvoc_thunk_RsResource_gisubscriptionControlLookup; diff --git a/src/nvidia/generated/g_gpu_instance_subscription_nvoc.h b/src/nvidia/generated/g_gpu_instance_subscription_nvoc.h index c82bbd70e..bb1031b45 100644 --- a/src/nvidia/generated/g_gpu_instance_subscription_nvoc.h +++ b/src/nvidia/generated/g_gpu_instance_subscription_nvoc.h @@ -67,6 +67,7 @@ struct GPUInstanceSubscription { NV_STATUS (*__gisubscriptionCtrlCmdExecPartitionsCreate__)(struct GPUInstanceSubscription *, NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS *); NV_STATUS (*__gisubscriptionCtrlCmdExecPartitionsDelete__)(struct GPUInstanceSubscription *, NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS *); NV_STATUS (*__gisubscriptionCtrlCmdExecPartitionsGet__)(struct GPUInstanceSubscription *, NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS *); + NV_STATUS (*__gisubscriptionCtrlCmdExecPartitionsGetProfileCapacity__)(struct GPUInstanceSubscription *, NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY_PARAMS *); NV_STATUS (*__gisubscriptionCtrlCmdExecPartitionsGetActiveIds__)(struct GPUInstanceSubscription *, NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS_PARAMS *); NV_STATUS (*__gisubscriptionCtrlCmdExecPartitionsExport__)(struct GPUInstanceSubscription *, NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS *); NV_STATUS (*__gisubscriptionCtrlCmdExecPartitionsImport__)(struct GPUInstanceSubscription *, NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS *); @@ -87,6 +88,7 @@ struct GPUInstanceSubscription { NV_STATUS (*__gisubscriptionInternalControlForward__)(struct GPUInstanceSubscription *, NvU32, void *, NvU32); void (*__gisubscriptionPreDestruct__)(struct GPUInstanceSubscription *); NV_STATUS (*__gisubscriptionUnmapFrom__)(struct GPUInstanceSubscription *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__gisubscriptionIsDuplicate__)(struct GPUInstanceSubscription *, NvHandle, NvBool *); void (*__gisubscriptionControl_Epilogue__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__gisubscriptionControlLookup__)(struct GPUInstanceSubscription *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__gisubscriptionMap__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -129,6 +131,7 @@ NV_STATUS __nvoc_objCreate_GPUInstanceSubscription(GPUInstanceSubscription**, Dy #define gisubscriptionCtrlCmdExecPartitionsCreate(arg0, arg1) gisubscriptionCtrlCmdExecPartitionsCreate_DISPATCH(arg0, arg1) #define gisubscriptionCtrlCmdExecPartitionsDelete(arg0, arg1) gisubscriptionCtrlCmdExecPartitionsDelete_DISPATCH(arg0, arg1) #define gisubscriptionCtrlCmdExecPartitionsGet(arg0, arg1) gisubscriptionCtrlCmdExecPartitionsGet_DISPATCH(arg0, arg1) +#define gisubscriptionCtrlCmdExecPartitionsGetProfileCapacity(arg0, arg1) gisubscriptionCtrlCmdExecPartitionsGetProfileCapacity_DISPATCH(arg0, arg1) #define gisubscriptionCtrlCmdExecPartitionsGetActiveIds(arg0, arg1) gisubscriptionCtrlCmdExecPartitionsGetActiveIds_DISPATCH(arg0, arg1) #define gisubscriptionCtrlCmdExecPartitionsExport(arg0, arg1) gisubscriptionCtrlCmdExecPartitionsExport_DISPATCH(arg0, arg1) #define gisubscriptionCtrlCmdExecPartitionsImport(arg0, arg1) gisubscriptionCtrlCmdExecPartitionsImport_DISPATCH(arg0, arg1) @@ -149,6 +152,7 @@ NV_STATUS __nvoc_objCreate_GPUInstanceSubscription(GPUInstanceSubscription**, Dy #define gisubscriptionInternalControlForward(pGpuResource, command, pParams, size) gisubscriptionInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define gisubscriptionPreDestruct(pResource) gisubscriptionPreDestruct_DISPATCH(pResource) #define gisubscriptionUnmapFrom(pResource, pParams) gisubscriptionUnmapFrom_DISPATCH(pResource, pParams) +#define gisubscriptionIsDuplicate(pResource, hMemory, pDuplicate) gisubscriptionIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define gisubscriptionControl_Epilogue(pResource, pCallContext, pParams) gisubscriptionControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define gisubscriptionControlLookup(pResource, pParams, ppEntry) gisubscriptionControlLookup_DISPATCH(pResource, pParams, ppEntry) #define gisubscriptionMap(pGpuResource, pCallContext, pParams, pCpuMapping) gisubscriptionMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -177,6 +181,12 @@ static inline NV_STATUS gisubscriptionCtrlCmdExecPartitionsGet_DISPATCH(struct G return arg0->__gisubscriptionCtrlCmdExecPartitionsGet__(arg0, arg1); } +NV_STATUS gisubscriptionCtrlCmdExecPartitionsGetProfileCapacity_IMPL(struct GPUInstanceSubscription *arg0, NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY_PARAMS *arg1); + +static inline NV_STATUS gisubscriptionCtrlCmdExecPartitionsGetProfileCapacity_DISPATCH(struct GPUInstanceSubscription *arg0, NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY_PARAMS *arg1) { + return arg0->__gisubscriptionCtrlCmdExecPartitionsGetProfileCapacity__(arg0, arg1); +} + NV_STATUS gisubscriptionCtrlCmdExecPartitionsGetActiveIds_IMPL(struct GPUInstanceSubscription *arg0, NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS_PARAMS *arg1); static inline NV_STATUS gisubscriptionCtrlCmdExecPartitionsGetActiveIds_DISPATCH(struct GPUInstanceSubscription *arg0, NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS_PARAMS *arg1) { @@ -263,6 +273,10 @@ static inline NV_STATUS gisubscriptionUnmapFrom_DISPATCH(struct GPUInstanceSubsc return pResource->__gisubscriptionUnmapFrom__(pResource, pParams); } +static inline NV_STATUS gisubscriptionIsDuplicate_DISPATCH(struct GPUInstanceSubscription *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__gisubscriptionIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void gisubscriptionControl_Epilogue_DISPATCH(struct GPUInstanceSubscription *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__gisubscriptionControl_Epilogue__(pResource, pCallContext, pParams); } @@ -284,14 +298,19 @@ static inline NvBool gisubscriptionIsDeviceProfiling(struct GPUInstanceSubscript } NV_STATUS gisubscriptionGetGPUInstanceSubscription_IMPL(struct RsClient *arg0, NvHandle arg1, struct GPUInstanceSubscription **arg2); + #define gisubscriptionGetGPUInstanceSubscription(arg0, arg1, arg2) gisubscriptionGetGPUInstanceSubscription_IMPL(arg0, arg1, arg2) NvBool gisubscriptionShouldClassBeFreedOnUnsubscribe_IMPL(NvU32 internalClassId); + #define gisubscriptionShouldClassBeFreedOnUnsubscribe(internalClassId) gisubscriptionShouldClassBeFreedOnUnsubscribe_IMPL(internalClassId) void gisubscriptionCleanupOnUnsubscribe_IMPL(CALL_CONTEXT *arg0); + #define gisubscriptionCleanupOnUnsubscribe(arg0) gisubscriptionCleanupOnUnsubscribe_IMPL(arg0) NV_STATUS gisubscriptionConstruct_IMPL(struct GPUInstanceSubscription *arg_pGPUInstanceSubscription, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_gisubscriptionConstruct(arg_pGPUInstanceSubscription, arg_pCallContext, arg_pParams) gisubscriptionConstruct_IMPL(arg_pGPUInstanceSubscription, arg_pCallContext, arg_pParams) NV_STATUS gisubscriptionCopyConstruct_IMPL(struct GPUInstanceSubscription *arg0, CALL_CONTEXT *arg1, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg2); + #ifdef __nvoc_gpu_instance_subscription_h_disabled static inline NV_STATUS gisubscriptionCopyConstruct(struct GPUInstanceSubscription *arg0, CALL_CONTEXT *arg1, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg2) { NV_ASSERT_FAILED_PRECOMP("GPUInstanceSubscription was disabled!"); @@ -302,8 +321,10 @@ static inline NV_STATUS gisubscriptionCopyConstruct(struct GPUInstanceSubscripti #endif //__nvoc_gpu_instance_subscription_h_disabled void gisubscriptionDestruct_IMPL(struct GPUInstanceSubscription *arg0); + #define __nvoc_gisubscriptionDestruct(arg0) gisubscriptionDestruct_IMPL(arg0) NvBool gisubscriptionIsDuped_IMPL(struct GPUInstanceSubscription *arg0); + #ifdef __nvoc_gpu_instance_subscription_h_disabled static inline NvBool gisubscriptionIsDuped(struct GPUInstanceSubscription *arg0) { NV_ASSERT_FAILED_PRECOMP("GPUInstanceSubscription was disabled!"); diff --git a/src/nvidia/generated/g_gpu_mgmt_api_nvoc.c b/src/nvidia/generated/g_gpu_mgmt_api_nvoc.c index 2e30ec588..de8999db4 100644 --- a/src/nvidia/generated/g_gpu_mgmt_api_nvoc.c +++ b/src/nvidia/generated/g_gpu_mgmt_api_nvoc.c @@ -140,6 +140,10 @@ static NV_STATUS __nvoc_thunk_RsResource_gpumgmtapiUnmapFrom(struct GpuManagemen return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_gpumgmtapiIsDuplicate(struct GpuManagementApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_gpumgmtapiControl_Epilogue(struct GpuManagementApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RmResource.offset), pCallContext, pParams); } @@ -251,6 +255,8 @@ static void __nvoc_init_funcTable_GpuManagementApi_1(GpuManagementApi *pThis) { pThis->__gpumgmtapiUnmapFrom__ = &__nvoc_thunk_RsResource_gpumgmtapiUnmapFrom; + pThis->__gpumgmtapiIsDuplicate__ = &__nvoc_thunk_RsResource_gpumgmtapiIsDuplicate; + pThis->__gpumgmtapiControl_Epilogue__ = &__nvoc_thunk_RmResource_gpumgmtapiControl_Epilogue; pThis->__gpumgmtapiControlLookup__ = &__nvoc_thunk_RsResource_gpumgmtapiControlLookup; diff --git a/src/nvidia/generated/g_gpu_mgmt_api_nvoc.h b/src/nvidia/generated/g_gpu_mgmt_api_nvoc.h index 72e3eba78..ff5a5d82c 100644 --- a/src/nvidia/generated/g_gpu_mgmt_api_nvoc.h +++ b/src/nvidia/generated/g_gpu_mgmt_api_nvoc.h @@ -75,6 +75,7 @@ struct GpuManagementApi { NV_STATUS (*__gpumgmtapiMapTo__)(struct GpuManagementApi *, RS_RES_MAP_TO_PARAMS *); void (*__gpumgmtapiPreDestruct__)(struct GpuManagementApi *); NV_STATUS (*__gpumgmtapiUnmapFrom__)(struct GpuManagementApi *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__gpumgmtapiIsDuplicate__)(struct GpuManagementApi *, NvHandle, NvBool *); void (*__gpumgmtapiControl_Epilogue__)(struct GpuManagementApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__gpumgmtapiControlLookup__)(struct GpuManagementApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__gpumgmtapiMap__)(struct GpuManagementApi *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -124,6 +125,7 @@ NV_STATUS __nvoc_objCreate_GpuManagementApi(GpuManagementApi**, Dynamic*, NvU32, #define gpumgmtapiMapTo(pResource, pParams) gpumgmtapiMapTo_DISPATCH(pResource, pParams) #define gpumgmtapiPreDestruct(pResource) gpumgmtapiPreDestruct_DISPATCH(pResource) #define gpumgmtapiUnmapFrom(pResource, pParams) gpumgmtapiUnmapFrom_DISPATCH(pResource, pParams) +#define gpumgmtapiIsDuplicate(pResource, hMemory, pDuplicate) gpumgmtapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define gpumgmtapiControl_Epilogue(pResource, pCallContext, pParams) gpumgmtapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define gpumgmtapiControlLookup(pResource, pParams, ppEntry) gpumgmtapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define gpumgmtapiMap(pResource, pCallContext, pParams, pCpuMapping) gpumgmtapiMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) @@ -190,6 +192,10 @@ static inline NV_STATUS gpumgmtapiUnmapFrom_DISPATCH(struct GpuManagementApi *pR return pResource->__gpumgmtapiUnmapFrom__(pResource, pParams); } +static inline NV_STATUS gpumgmtapiIsDuplicate_DISPATCH(struct GpuManagementApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__gpumgmtapiIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void gpumgmtapiControl_Epilogue_DISPATCH(struct GpuManagementApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__gpumgmtapiControl_Epilogue__(pResource, pCallContext, pParams); } @@ -207,8 +213,10 @@ static inline NvBool gpumgmtapiAccessCallback_DISPATCH(struct GpuManagementApi * } NV_STATUS gpumgmtapiConstruct_IMPL(struct GpuManagementApi *arg_pGpuMgmt, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_gpumgmtapiConstruct(arg_pGpuMgmt, arg_pCallContext, arg_pParams) gpumgmtapiConstruct_IMPL(arg_pGpuMgmt, arg_pCallContext, arg_pParams) void gpumgmtapiDestruct_IMPL(struct GpuManagementApi *pGpuMgmt); + #define __nvoc_gpumgmtapiDestruct(pGpuMgmt) gpumgmtapiDestruct_IMPL(pGpuMgmt) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_gpu_mgr_nvoc.h b/src/nvidia/generated/g_gpu_mgr_nvoc.h index f2cae81b3..1ae0e2121 100644 --- a/src/nvidia/generated/g_gpu_mgr_nvoc.h +++ b/src/nvidia/generated/g_gpu_mgr_nvoc.h @@ -46,6 +46,7 @@ struct OBJGPU; #include "gpu/gpu_device_mapping.h" #include "gpu/gpu_access.h" #include "ctrl/ctrl0000/ctrl0000gpu.h" +#include "ctrl/ctrl2080/ctrl2080ce.h" #include "ctrl/ctrl2080/ctrl2080internal.h" #include "ctrl/ctrlc637.h" #include "nvoc/utility.h" @@ -53,17 +54,12 @@ struct OBJGPU; #include "gpu/perf/kern_perf_gpuboostsync.h" -#include "class/cl2080.h" // NV2080_ENGINE_TYPE_* - #include "utils/nvbitvector.h" TYPEDEF_BITVECTOR(MC_ENGINE_BITVECTOR); #define GPUMGR_MAX_GPU_INSTANCES 8 #define GPUMGR_MAX_COMPUTE_INSTANCES 8 -MAKE_BITVECTOR(ENGTYPE_BIT_VECTOR, NV2080_ENGINE_TYPE_LAST); -typedef ENGTYPE_BIT_VECTOR *PENGTYPE_BIT_VECTOR; - // // Terminology: // GPU -> entity sitting on the bus @@ -82,7 +78,6 @@ typedef ENGTYPE_BIT_VECTOR *PENGTYPE_BIT_VECTOR; #define gpumgrGetSliLinkConnectionCount(pGpu) ((NvU32) 0) #define gpumgrGetSLIConfig(gpuInstance, onlyWithSliLink) ((NvU32) 0) #define gpumgrDisableVidLink(pGpu, head, max_dr_port) -#define gpumgrGetGpuVidLinkMaxPixelClock(pGpu, pMaxPclkMhz) (NV_ERR_NOT_SUPPORTED) #define gpumgrPinsetToPinsetTableIndex(pinset, pPinsetIndex) (NV_ERR_NOT_SUPPORTED) #define gpumgrGetBcEnabledStatus(g) (NV_FALSE) #define gpumgrGetBcEnabledStatusEx(g, t) (NV_FALSE) @@ -136,18 +131,6 @@ typedef struct _def_gpumgr_save_vbios_state #define SLI_BT_VIDLINK 0 #define SLI_BT_NVLINK 1 -// -// This is the same as what is maintained in gpu/ce/ce.h -// Make sure to update/match these defines in both the files. -// We had to re-define here instead of using gpu/ce/ce.h directly -// because there were compilation dependencies that prevented us -// from adding gpu/ce/ce.h -// -#define NV_CE_PCE2LCE_CONFIG__SIZE_1_MAX 32 -#define NV_CE_GRCE_CONFIG__SIZE_1 2 -#define NV_CE_MAX_HSHUBS 5 // Same as GPU_MAX_HSHUBS - - typedef struct NVLINK_TOPOLOGY_PARAMS { NvU32 sysmemLinks; @@ -159,10 +142,10 @@ typedef struct NVLINK_TOPOLOGY_PARAMS NvU32 numPeers; NvBool bSwitchConfig; // Ampere + - NvU32 pceAvailableMaskPerHshub[NV_CE_MAX_HSHUBS]; + NvU32 pceAvailableMaskPerHshub[NV2080_CTRL_CE_MAX_HSHUBS]; NvU32 fbhubPceMask; - NvU32 maxPceLceMap[NV_CE_PCE2LCE_CONFIG__SIZE_1_MAX]; - NvU32 maxGrceConfig[NV_CE_GRCE_CONFIG__SIZE_1]; + NvU32 maxPceLceMap[NV2080_CTRL_MAX_PCES]; + NvU32 maxGrceConfig[NV2080_CTRL_MAX_GRCES]; NvU32 maxExposeCeMask; NvU32 maxTopoIdx; // For table configs only; not applicable for algorithm } NVLINK_TOPOLOGY_PARAMS, *PNVLINK_TOPOLOGY_PARAMS; @@ -229,7 +212,7 @@ typedef struct GPUMGR_SAVE_MIG_INSTANCE_TOPOLOGY NvU64 domainBusDevice; // Flag checking whether we have restored from static info since boot NvBool bVgpuRestoredFromStaticInfo; - // MIG state last registered for the GPU this struct was saved for. + // MIG repartitioning mode last registered for the GPU this struct was saved for. NvBool bMIGEnabled; // Saved instance information. May or may not have any valid entries. GPUMGR_SAVE_GPU_INSTANCE saveGI[GPUMGR_MAX_GPU_INSTANCES]; @@ -261,6 +244,7 @@ struct OBJGPUMGR { void *probedGpusLock; NvU32 gpuAttachCount; NvU32 gpuAttachMask; + NvU32 gpuMonolithicRmMask; NvU32 persistentSwStateGpuMask; NvU32 deviceCount; struct OBJGPUGRP *pGpuGrpTable[32]; @@ -308,66 +292,87 @@ NV_STATUS __nvoc_objCreate_OBJGPUMGR(OBJGPUMGR**, Dynamic*, NvU32); NV_STATUS gpumgrInitPcieP2PCapsCache_IMPL(struct OBJGPUMGR *pGpuMgr); + #define gpumgrInitPcieP2PCapsCache(pGpuMgr) gpumgrInitPcieP2PCapsCache_IMPL(pGpuMgr) #define gpumgrInitPcieP2PCapsCache_HAL(pGpuMgr) gpumgrInitPcieP2PCapsCache(pGpuMgr) void gpumgrDestroyPcieP2PCapsCache_IMPL(struct OBJGPUMGR *pGpuMgr); + #define gpumgrDestroyPcieP2PCapsCache(pGpuMgr) gpumgrDestroyPcieP2PCapsCache_IMPL(pGpuMgr) #define gpumgrDestroyPcieP2PCapsCache_HAL(pGpuMgr) gpumgrDestroyPcieP2PCapsCache(pGpuMgr) NV_STATUS gpumgrStorePcieP2PCapsCache_IMPL(NvU32 gpuMask, NvU8 p2pWriteCapStatus, NvU8 p2pReadCapStatus); + #define gpumgrStorePcieP2PCapsCache(gpuMask, p2pWriteCapStatus, p2pReadCapStatus) gpumgrStorePcieP2PCapsCache_IMPL(gpuMask, p2pWriteCapStatus, p2pReadCapStatus) #define gpumgrStorePcieP2PCapsCache_HAL(gpuMask, p2pWriteCapStatus, p2pReadCapStatus) gpumgrStorePcieP2PCapsCache(gpuMask, p2pWriteCapStatus, p2pReadCapStatus) void gpumgrRemovePcieP2PCapsFromCache_IMPL(NvU32 gpuId); + #define gpumgrRemovePcieP2PCapsFromCache(gpuId) gpumgrRemovePcieP2PCapsFromCache_IMPL(gpuId) #define gpumgrRemovePcieP2PCapsFromCache_HAL(gpuId) gpumgrRemovePcieP2PCapsFromCache(gpuId) NvBool gpumgrGetPcieP2PCapsFromCache_IMPL(NvU32 gpuMask, NvU8 *pP2PWriteCapStatus, NvU8 *pP2PReadCapStatus); + #define gpumgrGetPcieP2PCapsFromCache(gpuMask, pP2PWriteCapStatus, pP2PReadCapStatus) gpumgrGetPcieP2PCapsFromCache_IMPL(gpuMask, pP2PWriteCapStatus, pP2PReadCapStatus) #define gpumgrGetPcieP2PCapsFromCache_HAL(gpuMask, pP2PWriteCapStatus, pP2PReadCapStatus) gpumgrGetPcieP2PCapsFromCache(gpuMask, pP2PWriteCapStatus, pP2PReadCapStatus) NV_STATUS gpumgrConstruct_IMPL(struct OBJGPUMGR *arg_); + #define __nvoc_gpumgrConstruct(arg_) gpumgrConstruct_IMPL(arg_) void gpumgrDestruct_IMPL(struct OBJGPUMGR *arg0); + #define __nvoc_gpumgrDestruct(arg0) gpumgrDestruct_IMPL(arg0) void gpumgrAddSystemNvlinkTopo_IMPL(NvU64 DomainBusDevice); + #define gpumgrAddSystemNvlinkTopo(DomainBusDevice) gpumgrAddSystemNvlinkTopo_IMPL(DomainBusDevice) NvBool gpumgrGetSystemNvlinkTopo_IMPL(NvU64 DomainBusDevice, struct NVLINK_TOPOLOGY_PARAMS *pTopoParams); + #define gpumgrGetSystemNvlinkTopo(DomainBusDevice, pTopoParams) gpumgrGetSystemNvlinkTopo_IMPL(DomainBusDevice, pTopoParams) void gpumgrUpdateSystemNvlinkTopo_IMPL(NvU64 DomainBusDevice, struct NVLINK_TOPOLOGY_PARAMS *pTopoParams); + #define gpumgrUpdateSystemNvlinkTopo(DomainBusDevice, pTopoParams) gpumgrUpdateSystemNvlinkTopo_IMPL(DomainBusDevice, pTopoParams) NV_STATUS gpumgrSetGpuInitDisabledNvlinks_IMPL(NvU32 gpuId, NvU32 mask, NvBool bSkipHwNvlinkDisable); + #define gpumgrSetGpuInitDisabledNvlinks(gpuId, mask, bSkipHwNvlinkDisable) gpumgrSetGpuInitDisabledNvlinks_IMPL(gpuId, mask, bSkipHwNvlinkDisable) NV_STATUS gpumgrGetGpuInitDisabledNvlinks_IMPL(NvU32 gpuId, NvU32 *pMask, NvBool *pbSkipHwNvlinkDisable); + #define gpumgrGetGpuInitDisabledNvlinks(gpuId, pMask, pbSkipHwNvlinkDisable) gpumgrGetGpuInitDisabledNvlinks_IMPL(gpuId, pMask, pbSkipHwNvlinkDisable) NvBool gpumgrCheckIndirectPeer_IMPL(struct OBJGPU *pGpu, struct OBJGPU *pRemoteGpu); + #define gpumgrCheckIndirectPeer(pGpu, pRemoteGpu) gpumgrCheckIndirectPeer_IMPL(pGpu, pRemoteGpu) void gpumgrAddSystemMIGInstanceTopo_IMPL(NvU64 domainBusDevice); + #define gpumgrAddSystemMIGInstanceTopo(domainBusDevice) gpumgrAddSystemMIGInstanceTopo_IMPL(domainBusDevice) NvBool gpumgrGetSystemMIGInstanceTopo_IMPL(NvU64 domainBusDevice, struct GPUMGR_SAVE_MIG_INSTANCE_TOPOLOGY **ppTopoParams); + #define gpumgrGetSystemMIGInstanceTopo(domainBusDevice, ppTopoParams) gpumgrGetSystemMIGInstanceTopo_IMPL(domainBusDevice, ppTopoParams) NvBool gpumgrIsSystemMIGEnabled_IMPL(NvU64 domainBusDevice); + #define gpumgrIsSystemMIGEnabled(domainBusDevice) gpumgrIsSystemMIGEnabled_IMPL(domainBusDevice) void gpumgrSetSystemMIGEnabled_IMPL(NvU64 domainBusDevice, NvBool bMIGEnabled); + #define gpumgrSetSystemMIGEnabled(domainBusDevice, bMIGEnabled) gpumgrSetSystemMIGEnabled_IMPL(domainBusDevice, bMIGEnabled) void gpumgrUnregisterRmCapsForMIGGI_IMPL(NvU64 gpuDomainBusDevice); + #define gpumgrUnregisterRmCapsForMIGGI(gpuDomainBusDevice) gpumgrUnregisterRmCapsForMIGGI_IMPL(gpuDomainBusDevice) void gpumgrUpdateBoardId_IMPL(struct OBJGPU *arg0); + #define gpumgrUpdateBoardId(arg0) gpumgrUpdateBoardId_IMPL(arg0) void gpumgrServiceInterrupts_IMPL(NvU32 arg0, MC_ENGINE_BITVECTOR *arg1, NvBool arg2); + #define gpumgrServiceInterrupts(arg0, arg1, arg2) gpumgrServiceInterrupts_IMPL(arg0, arg1, arg2) #undef PRIVATE_FIELD typedef struct { NvBool specified; // Set this flag when using this struct + NvBool bIsIGPU; // Set this flag for iGPU - DEVICE_MAPPING deviceMapping[SOC_DEV_MAPPING_MAX]; // Register Aperture mapping + DEVICE_MAPPING deviceMapping[DEVICE_INDEX_MAX]; // Register Aperture mapping NvU32 socChipId0; // Chip ID used for HAL binding NvU32 iovaspaceId; // SMMU client ID } SOCGPUATTACHARG; @@ -476,6 +481,7 @@ void gpumgrClearDeviceMaskFromGpuInstTable(NvU32 gpuMask); NvBool gpumgrSetGpuAcquire(OBJGPU *pGpu); void gpumgrSetGpuRelease(void); NvU8 gpumgrGetGpuBridgeType(void); +NvBool gpumgrAreAllGpusInOffloadMode(void); // // gpumgrIsSubDeviceCountOne diff --git a/src/nvidia/generated/g_gpu_nvoc.c b/src/nvidia/generated/g_gpu_nvoc.c index 23f67babe..313f5d913 100644 --- a/src/nvidia/generated/g_gpu_nvoc.c +++ b/src/nvidia/generated/g_gpu_nvoc.c @@ -19,7 +19,10 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmHalspecOwner; extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJTRACEABLE; -void __nvoc_init_OBJGPU(OBJGPU*, NvU32 ChipHal_arch, NvU32 ChipHal_impl, NvU32 ChipHal_hidrev, RM_RUNTIME_VARIANT RmVariantHal_rmVariant, NvU32 DispIpHal_ipver); +void __nvoc_init_OBJGPU(OBJGPU*, + NvU32 ChipHal_arch, NvU32 ChipHal_impl, NvU32 ChipHal_hidrev, + RM_RUNTIME_VARIANT RmVariantHal_rmVariant, + NvU32 DispIpHal_ipver); void __nvoc_init_funcTable_OBJGPU(OBJGPU*); NV_STATUS __nvoc_ctor_OBJGPU(OBJGPU*, NvU32 arg_gpuInstance); void __nvoc_init_dataField_OBJGPU(OBJGPU*); @@ -105,67 +108,54 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { pThis->setProperty(pThis, PDB_PROP_GPU_IS_CONNECTED, ((NvBool)(0 == 0))); // NVOC Property Hal field -- PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY - if (0) - { - } // default - else { pThis->setProperty(pThis, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY, ((NvBool)(0 != 0))); } // NVOC Property Hal field -- PDB_PROP_GPU_TEGRA_SOC_IGPU - if (0) - { - } // default - else { pThis->setProperty(pThis, PDB_PROP_GPU_TEGRA_SOC_IGPU, ((NvBool)(0 != 0))); } // NVOC Property Hal field -- PDB_PROP_GPU_ATS_SUPPORTED - if (0) - { - } // default - else { pThis->setProperty(pThis, PDB_PROP_GPU_ATS_SUPPORTED, ((NvBool)(0 != 0))); } - // NVOC Property Hal field -- PDB_PROP_GPU_IS_UEFI - if (0) + // NVOC Property Hal field -- PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ { + pThis->setProperty(pThis, PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE, ((NvBool)(0 == 0))); } // default else + { + pThis->setProperty(pThis, PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE, ((NvBool)(0 != 0))); + } + + // NVOC Property Hal field -- PDB_PROP_GPU_IS_UEFI + // default { pThis->setProperty(pThis, PDB_PROP_GPU_IS_UEFI, ((NvBool)(0 != 0))); } // NVOC Property Hal field -- PDB_PROP_GPU_ZERO_FB - if (0) - { - } // default - else { pThis->setProperty(pThis, PDB_PROP_GPU_ZERO_FB, ((NvBool)(0 != 0))); } // NVOC Property Hal field -- PDB_PROP_GPU_CAN_OPTIMIZE_COMPUTE_USE_CASE - if (0) - { - } // default - else { pThis->setProperty(pThis, PDB_PROP_GPU_CAN_OPTIMIZE_COMPUTE_USE_CASE, ((NvBool)(0 != 0))); } // NVOC Property Hal field -- PDB_PROP_GPU_MIG_SUPPORTED - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_GPU_MIG_SUPPORTED, ((NvBool)(0 == 0))); } @@ -176,7 +166,7 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { } // NVOC Property Hal field -- PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->setProperty(pThis, PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED, ((NvBool)(0 == 0))); } @@ -187,7 +177,7 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { } // NVOC Property Hal field -- PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->setProperty(pThis, PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED, ((NvBool)(0 == 0))); } @@ -198,7 +188,7 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { } // NVOC Property Hal field -- PDB_PROP_GPU_IS_COT_ENABLED - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->setProperty(pThis, PDB_PROP_GPU_IS_COT_ENABLED, ((NvBool)(0 == 0))); } @@ -208,8 +198,11 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { pThis->setProperty(pThis, PDB_PROP_GPU_IS_COT_ENABLED, ((NvBool)(0 != 0))); } + // NVOC Property Hal field -- PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE + pThis->setProperty(pThis, PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE, ((NvBool)(0 != 0))); + // NVOC Property Hal field -- PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->setProperty(pThis, PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK, ((NvBool)(0 != 0))); } @@ -218,16 +211,14 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { { pThis->setProperty(pThis, PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK, ((NvBool)(0 == 0))); } + pThis->setProperty(pThis, PDB_PROP_GPU_OPTIMUS_GOLD_CFG_SPACE_RESTORE, ((NvBool)(0 == 0))); pThis->boardId = ~0; pThis->deviceInstance = 32; // Hal field -- isVirtual - if (0) - { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { pThis->isVirtual = ((NvBool)(0 != 0)); } @@ -237,9 +228,6 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { { pThis->isGspClient = ((NvBool)(0 == 0)); } - else if (0) - { - } pThis->bIsDebugModeEnabled = ((NvBool)(0 != 0)); @@ -250,11 +238,7 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { pThis->boardInfo = ((void *)0); // Hal field -- bUnifiedMemorySpaceEnabled - if (0) - { - } // default - else { pThis->bUnifiedMemorySpaceEnabled = ((NvBool)(0 != 0)); } @@ -263,38 +247,25 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { pThis->bWarBug200577889SriovHeavyEnabled = ((NvBool)(0 != 0)); // Hal field -- bNeed4kPageIsolation - if (0) - { - } // default - else { pThis->bNeed4kPageIsolation = ((NvBool)(0 != 0)); } // Hal field -- bInstLoc47bitPaWar - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->bInstLoc47bitPaWar = ((NvBool)(0 == 0)); } - // default - else - { - pThis->bInstLoc47bitPaWar = ((NvBool)(0 != 0)); - } // Hal field -- bIsBarPteInSysmemSupported - if (0) - { - } // default - else { pThis->bIsBarPteInSysmemSupported = ((NvBool)(0 != 0)); } // Hal field -- bClientRmAllocatedCtxBuffer - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->bClientRmAllocatedCtxBuffer = ((NvBool)(0 == 0)); } @@ -305,7 +276,7 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { } // Hal field -- bVidmemPreservationBrokenBug3172217 - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->bVidmemPreservationBrokenBug3172217 = ((NvBool)(0 == 0)); } @@ -316,11 +287,7 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { } // Hal field -- bInstanceMemoryAlwaysCached - if (0) - { - } // default - else { pThis->bInstanceMemoryAlwaysCached = ((NvBool)(0 != 0)); } @@ -328,14 +295,15 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { pThis->bIsGeforce = ((NvBool)(0 == 0)); // Hal field -- bComputePolicyTimesliceSupported - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->bComputePolicyTimesliceSupported = ((NvBool)(0 == 0)); } - // default - else + + // Hal field -- bSriovCapable + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { - pThis->bComputePolicyTimesliceSupported = ((NvBool)(0 != 0)); + pThis->bSriovCapable = ((NvBool)(0 == 0)); } } @@ -380,165 +348,98 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // Hal function -- gpuWriteBusConfigReg - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__gpuWriteBusConfigReg__ = &gpuWriteBusConfigReg_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__gpuWriteBusConfigReg__ = &gpuWriteBusConfigReg_GH100; } - else if (0) - { - } - else if (0) - { - } // Hal function -- gpuReadBusConfigReg - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__gpuReadBusConfigReg__ = &gpuReadBusConfigReg_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__gpuReadBusConfigReg__ = &gpuReadBusConfigReg_GH100; } - else if (0) - { - } - else if (0) - { - } // Hal function -- gpuReadBusConfigRegEx - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__gpuReadBusConfigRegEx__ = &gpuReadBusConfigRegEx_GM107; } - else if (0) - { - } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__gpuReadBusConfigRegEx__ = &gpuReadBusConfigRegEx_46f6a7; } // Hal function -- gpuReadFunctionConfigReg - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__gpuReadFunctionConfigReg__ = &gpuReadFunctionConfigReg_GM107; } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__gpuReadFunctionConfigReg__ = &gpuReadFunctionConfigReg_5baef9; } // Hal function -- gpuWriteFunctionConfigReg - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__gpuWriteFunctionConfigReg__ = &gpuWriteFunctionConfigReg_GM107; } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__gpuWriteFunctionConfigReg__ = &gpuWriteFunctionConfigReg_5baef9; } // Hal function -- gpuWriteFunctionConfigRegEx - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__gpuWriteFunctionConfigRegEx__ = &gpuWriteFunctionConfigRegEx_GM107; } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__gpuWriteFunctionConfigRegEx__ = &gpuWriteFunctionConfigRegEx_5baef9; } // Hal function -- gpuGetIdInfo - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__gpuGetIdInfo__ = &gpuGetIdInfo_GM107; } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__gpuGetIdInfo__ = &gpuGetIdInfo_GH100; } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } // Hal function -- gpuHandleSanityCheckRegReadError - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__gpuHandleSanityCheckRegReadError__ = &gpuHandleSanityCheckRegReadError_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__gpuHandleSanityCheckRegReadError__ = &gpuHandleSanityCheckRegReadError_GH100; } - else if (0) + + // Hal function -- gpuHandleSecFault + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { + pThis->__gpuHandleSecFault__ = &gpuHandleSecFault_GH100; + } + // default + else + { + pThis->__gpuHandleSecFault__ = &gpuHandleSecFault_b3696a; } // Hal function -- gpuGetChildrenPresent - if (0) - { - } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000320UL) )) /* ChipHal: TU102 | TU116 | TU117 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000320UL) )) /* ChipHal: TU102 | TU116 | TU117 */ { pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_TU102; } @@ -558,80 +459,17 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { { pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_GA102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00700000UL) )) /* ChipHal: AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_AD102; } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__gpuGetChildrenPresent__ = &gpuGetChildrenPresent_GH100; } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } // Hal function -- gpuGetClassDescriptorList - if (0) - { - } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000120UL) )) /* ChipHal: TU102 | TU116 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000120UL) )) /* ChipHal: TU102 | TU116 */ { pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_TU102; } @@ -655,91 +493,34 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { { pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_GA102; } - else if (0) - { - } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00700000UL) )) /* ChipHal: AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_AD102; } - else if (0) - { - } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__gpuGetClassDescriptorList__ = &gpuGetClassDescriptorList_GH100; } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } // Hal function -- gpuGetPhysAddrWidth - if (0) - { - } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__gpuGetPhysAddrWidth__ = &gpuGetPhysAddrWidth_TU102; } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__gpuGetPhysAddrWidth__ = &gpuGetPhysAddrWidth_GH100; } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } // Hal function -- gpuFuseSupportsDisplay if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__gpuFuseSupportsDisplay__ = &gpuFuseSupportsDisplay_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__gpuFuseSupportsDisplay__ = &gpuFuseSupportsDisplay_GA100; } - else if (0) - { - } - else if (0) - { - } // Hal function -- gpuClearFbhubPoisonIntrForBug2924523 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ @@ -748,29 +529,26 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { { pThis->__gpuClearFbhubPoisonIntrForBug2924523__ = &gpuClearFbhubPoisonIntrForBug2924523_GA100_KERNEL; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__gpuClearFbhubPoisonIntrForBug2924523__ = &gpuClearFbhubPoisonIntrForBug2924523_56cd7a; } } - else if (0) + + // Hal function -- gpuReadDeviceId + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { -#if 0 - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ - { - pThis->__gpuClearFbhubPoisonIntrForBug2924523__ = &gpuClearFbhubPoisonIntrForBug2924523_GA100_PHYSICAL; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ - { - pThis->__gpuClearFbhubPoisonIntrForBug2924523__ = &gpuClearFbhubPoisonIntrForBug2924523_56cd7a; - } -#endif + pThis->__gpuReadDeviceId__ = &gpuReadDeviceId_GM107; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__gpuReadDeviceId__ = &gpuReadDeviceId_GH100; } // Hal function -- gpuConstructDeviceInfoTable if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__gpuConstructDeviceInfoTable__ = &gpuConstructDeviceInfoTable_FWCLIENT; } @@ -780,27 +558,13 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { pThis->__gpuConstructDeviceInfoTable__ = &gpuConstructDeviceInfoTable_56cd7a; } } - else if (0) - { -#if 0 - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ - { - pThis->__gpuConstructDeviceInfoTable__ = &gpuConstructDeviceInfoTable_GA100; - } - // default - else - { - pThis->__gpuConstructDeviceInfoTable__ = &gpuConstructDeviceInfoTable_56cd7a; - } -#endif - } // Hal function -- gpuGetFlaVasSize - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__gpuGetFlaVasSize__ = &gpuGetFlaVasSize_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__gpuGetFlaVasSize__ = &gpuGetFlaVasSize_GH100; } @@ -810,7 +574,7 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { } // Hal function -- gpuIsAtsSupportedWithSmcMemPartitioning - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__gpuIsAtsSupportedWithSmcMemPartitioning__ = &gpuIsAtsSupportedWithSmcMemPartitioning_GH100; } @@ -819,6 +583,17 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { { pThis->__gpuIsAtsSupportedWithSmcMemPartitioning__ = &gpuIsAtsSupportedWithSmcMemPartitioning_491d52; } + + // Hal function -- gpuIsSliCapableWithoutDisplay + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__gpuIsSliCapableWithoutDisplay__ = &gpuIsSliCapableWithoutDisplay_cbe027; + } + // default + else + { + pThis->__gpuIsSliCapableWithoutDisplay__ = &gpuIsSliCapableWithoutDisplay_491d52; + } } void __nvoc_init_funcTable_OBJGPU(OBJGPU *pThis) { @@ -828,7 +603,10 @@ void __nvoc_init_funcTable_OBJGPU(OBJGPU *pThis) { void __nvoc_init_Object(Object*); void __nvoc_init_RmHalspecOwner(RmHalspecOwner*, NvU32, NvU32, NvU32, RM_RUNTIME_VARIANT, NvU32); void __nvoc_init_OBJTRACEABLE(OBJTRACEABLE*); -void __nvoc_init_OBJGPU(OBJGPU *pThis, NvU32 ChipHal_arch, NvU32 ChipHal_impl, NvU32 ChipHal_hidrev, RM_RUNTIME_VARIANT RmVariantHal_rmVariant, NvU32 DispIpHal_ipver) { +void __nvoc_init_OBJGPU(OBJGPU *pThis, + NvU32 ChipHal_arch, NvU32 ChipHal_impl, NvU32 ChipHal_hidrev, + RM_RUNTIME_VARIANT RmVariantHal_rmVariant, + NvU32 DispIpHal_ipver) { pThis->__nvoc_pbase_OBJGPU = pThis; pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Object; pThis->__nvoc_pbase_RmHalspecOwner = &pThis->__nvoc_base_RmHalspecOwner; @@ -839,7 +617,10 @@ void __nvoc_init_OBJGPU(OBJGPU *pThis, NvU32 ChipHal_arch, NvU32 ChipHal_impl, N __nvoc_init_funcTable_OBJGPU(pThis); } -NV_STATUS __nvoc_objCreate_OBJGPU(OBJGPU **ppThis, Dynamic *pParent, NvU32 createFlags, NvU32 ChipHal_arch, NvU32 ChipHal_impl, NvU32 ChipHal_hidrev, RM_RUNTIME_VARIANT RmVariantHal_rmVariant, NvU32 DispIpHal_ipver, NvU32 arg_gpuInstance) { +NV_STATUS __nvoc_objCreate_OBJGPU(OBJGPU **ppThis, Dynamic *pParent, NvU32 createFlags, + NvU32 ChipHal_arch, NvU32 ChipHal_impl, NvU32 ChipHal_hidrev, + RM_RUNTIME_VARIANT RmVariantHal_rmVariant, + NvU32 DispIpHal_ipver, NvU32 arg_gpuInstance) { NV_STATUS status; Object *pParentObj; OBJGPU *pThis; diff --git a/src/nvidia/generated/g_gpu_nvoc.h b/src/nvidia/generated/g_gpu_nvoc.h index 009543ab8..cf7ed2cce 100644 --- a/src/nvidia/generated/g_gpu_nvoc.h +++ b/src/nvidia/generated/g_gpu_nvoc.h @@ -58,10 +58,12 @@ typedef struct GPUATTACHARG GPUATTACHARG; * A child module generally includes the header of its parent. A child module header included * by the parent module affects all the sibling modules. * */ +#include "ctrl/ctrl0000/ctrl0000system.h" #include "ctrl/ctrl0080/ctrl0080gpu.h" // NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS (form hal) #include "ctrl/ctrl2080/ctrl2080internal.h" // NV2080_CTRL_CMD_INTERNAL_MAX_BSPS/NVENCS #include "ctrl/ctrl2080/ctrl2080ecc.h" #include "ctrl/ctrl2080/ctrl2080nvd.h" +#include "ctrl/ctrl0073/ctrl0073system.h" #include "class/cl2080.h" #include "class/cl90cd.h" @@ -70,10 +72,10 @@ typedef struct GPUATTACHARG GPUATTACHARG; #include "gpu/gpu_timeout.h" #include "gpu/gpu_access.h" +#include "gpu/gpu_shared_data_map.h" #include "platform/acpi_common.h" -#include "acpigenfuncs.h" -#include "nvacpitypes.h" +#include "gpu/gpu_acpi_data.h" #include "platform/sli/sli.h" #include "core/core.h" @@ -87,6 +89,7 @@ typedef struct GPUATTACHARG GPUATTACHARG; #include "gpu/gpu_uuid.h" #include "prereq_tracker/prereq_tracker.h" #include "gpu/gpu_halspec.h" +#include "kernel/gpu/gpu_engine_type.h" #include "rmapi/control.h" #include "rmapi/event.h" @@ -95,7 +98,8 @@ typedef struct GPUATTACHARG GPUATTACHARG; #include "kernel/gpu/gr/fecs_event_list.h" #include "class/cl90cdfecs.h" -#include "nvdevid.h" +#include "gpu/gpu_fabric_probe.h" + #include "nv_arch.h" #include "g_rmconfig_util.h" // prototypes for rmconfig utility functions, eg: rmcfg_IsGK104() @@ -295,37 +299,6 @@ typedef enum COMPUTE_BRANDING_TYPE_TESLA, } COMPUTE_BRANDING_TYPE; -#define MAX_DSM_SUPPORTED_FUNCS_RTN_LEN 8 // # bytes to store supported functions - -typedef struct { - // supported function status and cache - NvU32 suppFuncStatus; - NvU8 suppFuncs[MAX_DSM_SUPPORTED_FUNCS_RTN_LEN]; - NvU32 suppFuncsLen; - NvBool bArg3isInteger; - // callback status and cache - NvU32 callbackStatus; - NvU32 callback; -} ACPI_DSM_CACHE; - -typedef struct { - - ACPI_DSM_CACHE dsm[ACPI_DSM_FUNCTION_COUNT]; - ACPI_DSM_FUNCTION dispStatusHotplugFunc; - ACPI_DSM_FUNCTION dispStatusConfigFunc; - ACPI_DSM_FUNCTION perfPostPowerStateFunc; - ACPI_DSM_FUNCTION stereo3dStateActiveFunc; - NvU32 dsmPlatCapsCache[ACPI_DSM_FUNCTION_COUNT]; - NvU32 MDTLFeatureSupport; - - // cache of generic func/subfunction remappings. - ACPI_DSM_FUNCTION dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_COUNT]; - NvU32 dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_COUNT]; - NvU32 dsmCurrentFuncSupport; - -} ACPI_DATA; - - #define OOR_ARCH_DEF(x) \ NV_ENUM_ENTRY(x, OOR_ARCH_X86_64, 0x00000000) \ NV_ENUM_ENTRY(x, OOR_ARCH_PPC64LE, 0x00000001) \ @@ -439,6 +412,11 @@ static NV_INLINE NvU32 gpuEncodeBusDevice(NvU8 bus, NvU8 device) // NvU32 gpuGenerate32BitId(NvU32 domain, NvU8 bus, NvU8 device); +// +// Generate a 32-bit id from a physical address +// +NvU32 gpuGenerate32BitIdFromPhysAddr(RmPhysAddr addr); + // // Helpers for getting domain, bus and device of a GPU // @@ -653,6 +631,16 @@ typedef struct hwbc_list struct hwbc_list *pNext; } HWBC_LIST; +/*! + * GFID allocation state + */ +typedef enum +{ + GFID_FREE = 0, + GFID_ALLOCATED = 1, + GFID_INVALIDATED = 2, +} GFID_ALLOC_STATUS; + typedef struct SRIOV_P2P_INFO { NvU32 gfid; @@ -661,6 +649,17 @@ typedef struct SRIOV_P2P_INFO NvU32 destRefCount; } SRIOV_P2P_INFO, *PSRIOV_P2P_INFO; +typedef struct +{ + NvU32 peerGpuId; + NvU32 peerGpuInstance; + NvU32 p2pCaps; + NvU32 p2pOptimalReadCEs; + NvU32 p2pOptimalWriteCEs; + NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE]; + NvU32 busPeerId; +} GPU_P2P_PEER_GPU_CAPS; + // // typedef of private struct used in OBJGPU's data field // @@ -692,7 +691,7 @@ typedef struct typedef struct { NvU32 size; - NvU32 *pType; + RM_ENGINE_TYPE *pType; NvBool bValid; } _GPU_ENGINE_DB; @@ -812,6 +811,9 @@ typedef struct NV2080_CTRL_INTERNAL_DEVICE_INFO DEVICE_INFO2_TABLE; #define NV_SIM_MODE_INVALID (~0x0U) #endif +#define GPU_IS_NVSWITCH_DETECTED(pGpu) \ + (pGpu->nvswitchSupport == NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_SUPPORTED) + // // The actual GPU object definition // @@ -837,14 +839,20 @@ struct OBJGPU { NV_STATUS (*__gpuWriteFunctionConfigRegEx__)(struct OBJGPU *, NvU32, NvU32, NvU32, THREAD_STATE_NODE *); void (*__gpuGetIdInfo__)(struct OBJGPU *); void (*__gpuHandleSanityCheckRegReadError__)(struct OBJGPU *, NvU32, NvU32); + void (*__gpuHandleSecFault__)(struct OBJGPU *); const GPUCHILDPRESENT *(*__gpuGetChildrenPresent__)(struct OBJGPU *, NvU32 *); const CLASSDESCRIPTOR *(*__gpuGetClassDescriptorList__)(struct OBJGPU *, NvU32 *); NvU32 (*__gpuGetPhysAddrWidth__)(struct OBJGPU *, NV_ADDRESS_SPACE); NvBool (*__gpuFuseSupportsDisplay__)(struct OBJGPU *); NV_STATUS (*__gpuClearFbhubPoisonIntrForBug2924523__)(struct OBJGPU *); + void (*__gpuReadDeviceId__)(struct OBJGPU *, NvU32 *, NvU32 *); NV_STATUS (*__gpuConstructDeviceInfoTable__)(struct OBJGPU *); NvU64 (*__gpuGetFlaVasSize__)(struct OBJGPU *, NvBool); NvBool (*__gpuIsAtsSupportedWithSmcMemPartitioning__)(struct OBJGPU *); + NvBool (*__gpuIsSliCapableWithoutDisplay__)(struct OBJGPU *); + GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo; + NvU32 moduleId; + NvU8 nvswitchSupport; NvBool PDB_PROP_GPU_IN_STANDBY; NvBool PDB_PROP_GPU_IN_HIBERNATE; NvBool PDB_PROP_GPU_IN_PM_CODEPATH; @@ -873,6 +881,7 @@ struct OBJGPU { NvBool PDB_PROP_GPU_ATS_SUPPORTED; NvBool PDB_PROP_GPU_SECONDARY_BUS_RESET_PENDING; NvBool PDB_PROP_GPU_IN_BUGCHECK_CALLBACK_ROUTINE; + NvBool PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE; NvBool PDB_PROP_GPU_IS_UEFI; NvBool PDB_PROP_GPU_ZERO_FB; NvBool PDB_PROP_GPU_CAN_OPTIMIZE_COMPUTE_USE_CASE; @@ -880,6 +889,7 @@ struct OBJGPU { NvBool PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED; NvBool PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED; NvBool PDB_PROP_GPU_IS_COT_ENABLED; + NvBool PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE; NvBool PDB_PROP_GPU_SWRL_GRANULAR_LOCKING; NvBool PDB_PROP_GPU_IN_SLI_LINK_CODEPATH; NvBool PDB_PROP_GPU_IS_PLX_PRESENT; @@ -917,11 +927,16 @@ struct OBJGPU { NvBool PDB_PROP_GPU_NVLINK_P2P_LOOPBACK_DISABLED; NvBool PDB_PROP_GPU_NV_USERMODE_ENABLED; NvBool PDB_PROP_GPU_IN_FATAL_ERROR; + NvBool PDB_PROP_GPU_OPTIMUS_GOLD_CFG_SPACE_RESTORE; + NvBool PDB_PROP_GPU_VGA_ENABLED; + NvBool PDB_PROP_GPU_IS_MXM_3X; + NvBool PDB_PROP_GPU_GSYNC_III_ATTACHED; + NvBool PDB_PROP_GPU_QSYNC_II_ATTACHED; OS_GPU_INFO *pOsGpuInfo; OS_RM_CAPS *pOsRmCaps; NvU32 halImpl; void *hPci; - ENGINE_EVENT_LIST engineNonstallIntr[52]; + ENGINE_EVENT_LIST engineNonstallIntr[62]; NvBool bIsSOC; NvU32 gpuInstance; NvU32 gpuDisabled; @@ -953,8 +968,6 @@ struct OBJGPU { NvBool instSetViaAttachArg; NvU32 activeFBIOs; NvU64 gpuVbiosPostTime; - NvBool bIsCeMapInitialized; - NvBool bIsKCeMapInitialized; NvU32 uefiScanoutSurfaceSizeInMB; RmPhysAddr dmaStartAddress; NvU32 gpuDeviceMapCount; @@ -1009,6 +1022,8 @@ struct OBJGPU { NvU32 netlistNum; RmCtrlDeferredCmd pRmCtrlDeferredCmd[2]; ACPI_DATA acpi; + ACPI_METHOD_DATA acpiMethodData; + NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS backLightMethodData; NvU32 activeFifoEventMthdNotifiers; struct Falcon *constructedFalcons[70]; NvU32 numConstructedFalcons; @@ -1042,6 +1057,7 @@ struct OBJGPU { NvU32 maxSubdeviceBackReferences; NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS *pChipInfo; NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS *boardInfo; + GpuSharedDataMap userSharedData; NvBool bBar2MovedByVtd; NvBool bBar1Is64Bit; NvBool bSurpriseRemovalSupported; @@ -1054,6 +1070,8 @@ struct OBJGPU { NvBool bIsRtlsim; NvBool bIsPassthru; NvBool bIsVirtualWithSriov; + NvU32 P2PPeerGpuCount; + GPU_P2P_PEER_GPU_CAPS P2PPeerGpuCaps[32]; NvBool bCpuFirmwareHandlesFbEccInterruptEnabled; NvBool bStateLoading; NvBool bStateUnloading; @@ -1071,7 +1089,6 @@ struct OBJGPU { NvU32 instLocOverrides4; NvBool bInstLoc47bitPaWar; NvU32 instVprOverrides; - NvBool bdisableTconOd; NvU32 optimizeUseCaseOverride; NvS16 fecsCtxswLogConsumerCount; NvS16 videoCtxswLogConsumerCount; @@ -1098,6 +1115,10 @@ struct OBJGPU { NvBool bComputePolicyTimesliceSupported; NvBool bGlobalPoisonFuseEnabled; RmPhysAddr simAccessBufPhysAddr; + NvU8 fabricProbeRetryDelay; + NvU8 fabricProbeSlowdownThreshold; + NvBool bVgpuGspPluginOffloadEnabled; + NvBool bSriovCapable; }; #ifndef __NVOC_CLASS_OBJGPU_TYPEDEF__ @@ -1131,6 +1152,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; #define PDB_PROP_GPU_DO_NOT_CHECK_REG_ACCESS_IN_PM_CODEPATH_BASE_NAME PDB_PROP_GPU_DO_NOT_CHECK_REG_ACCESS_IN_PM_CODEPATH #define PDB_PROP_GPU_IN_FATAL_ERROR_BASE_CAST #define PDB_PROP_GPU_IN_FATAL_ERROR_BASE_NAME PDB_PROP_GPU_IN_FATAL_ERROR +#define PDB_PROP_GPU_VGA_ENABLED_BASE_CAST +#define PDB_PROP_GPU_VGA_ENABLED_BASE_NAME PDB_PROP_GPU_VGA_ENABLED #define PDB_PROP_GPU_IN_PM_RESUME_CODEPATH_BASE_CAST #define PDB_PROP_GPU_IN_PM_RESUME_CODEPATH_BASE_NAME PDB_PROP_GPU_IN_PM_RESUME_CODEPATH #define PDB_PROP_GPU_IN_STANDBY_BASE_CAST @@ -1199,6 +1222,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; #define PDB_PROP_GPU_MIG_SUPPORTED_BASE_NAME PDB_PROP_GPU_MIG_SUPPORTED #define PDB_PROP_GPU_IN_BUGCHECK_CALLBACK_ROUTINE_BASE_CAST #define PDB_PROP_GPU_IN_BUGCHECK_CALLBACK_ROUTINE_BASE_NAME PDB_PROP_GPU_IN_BUGCHECK_CALLBACK_ROUTINE +#define PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE_BASE_CAST +#define PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE_BASE_NAME PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE #define PDB_PROP_GPU_CAN_OPTIMIZE_COMPUTE_USE_CASE_BASE_CAST #define PDB_PROP_GPU_CAN_OPTIMIZE_COMPUTE_USE_CASE_BASE_NAME PDB_PROP_GPU_CAN_OPTIMIZE_COMPUTE_USE_CASE #define PDB_PROP_GPU_ACCOUNTING_ON_BASE_CAST @@ -1229,10 +1254,18 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; #define PDB_PROP_GPU_STATE_INITIALIZED_BASE_NAME PDB_PROP_GPU_STATE_INITIALIZED #define PDB_PROP_GPU_NV_USERMODE_ENABLED_BASE_CAST #define PDB_PROP_GPU_NV_USERMODE_ENABLED_BASE_NAME PDB_PROP_GPU_NV_USERMODE_ENABLED +#define PDB_PROP_GPU_IS_MXM_3X_BASE_CAST +#define PDB_PROP_GPU_IS_MXM_3X_BASE_NAME PDB_PROP_GPU_IS_MXM_3X #define PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS_BASE_CAST #define PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS_BASE_NAME PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS +#define PDB_PROP_GPU_GSYNC_III_ATTACHED_BASE_CAST +#define PDB_PROP_GPU_GSYNC_III_ATTACHED_BASE_NAME PDB_PROP_GPU_GSYNC_III_ATTACHED +#define PDB_PROP_GPU_QSYNC_II_ATTACHED_BASE_CAST +#define PDB_PROP_GPU_QSYNC_II_ATTACHED_BASE_NAME PDB_PROP_GPU_QSYNC_II_ATTACHED #define PDB_PROP_GPU_IS_BR04_PRESENT_BASE_CAST #define PDB_PROP_GPU_IS_BR04_PRESENT_BASE_NAME PDB_PROP_GPU_IS_BR04_PRESENT +#define PDB_PROP_GPU_OPTIMUS_GOLD_CFG_SPACE_RESTORE_BASE_CAST +#define PDB_PROP_GPU_OPTIMUS_GOLD_CFG_SPACE_RESTORE_BASE_NAME PDB_PROP_GPU_OPTIMUS_GOLD_CFG_SPACE_RESTORE #define PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM_BASE_CAST #define PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM_BASE_NAME PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM #define PDB_PROP_GPU_NVLINK_P2P_LOOPBACK_DISABLED_BASE_CAST @@ -1255,6 +1288,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; #define PDB_PROP_GPU_IGNORE_REPLAYABLE_FAULTS_BASE_NAME PDB_PROP_GPU_IGNORE_REPLAYABLE_FAULTS #define PDB_PROP_GPU_PRIMARY_DEVICE_BASE_CAST #define PDB_PROP_GPU_PRIMARY_DEVICE_BASE_NAME PDB_PROP_GPU_PRIMARY_DEVICE +#define PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE_BASE_CAST +#define PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE_BASE_NAME PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE #define PDB_PROP_GPU_BEHIND_BRIDGE_BASE_CAST #define PDB_PROP_GPU_BEHIND_BRIDGE_BASE_NAME PDB_PROP_GPU_BEHIND_BRIDGE #define PDB_PROP_GPU_UPSTREAM_PORT_L1_POR_MOBILE_ONLY_BASE_CAST @@ -1268,7 +1303,10 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; NV_STATUS __nvoc_objCreateDynamic_OBJGPU(OBJGPU**, Dynamic*, NvU32, va_list); -NV_STATUS __nvoc_objCreate_OBJGPU(OBJGPU**, Dynamic*, NvU32, NvU32, NvU32, NvU32, RM_RUNTIME_VARIANT, NvU32, NvU32 arg_gpuInstance); +NV_STATUS __nvoc_objCreate_OBJGPU(OBJGPU**, Dynamic*, NvU32, + NvU32 ChipHal_arch, NvU32 ChipHal_impl, NvU32 ChipHal_hidrev, + RM_RUNTIME_VARIANT RmVariantHal_rmVariant, + NvU32 DispIpHal_ipver, NvU32 arg_gpuInstance); #define __objCreate_OBJGPU(ppNewObj, pParent, createFlags, ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, DispIpHal_ipver, arg_gpuInstance) \ __nvoc_objCreate_OBJGPU((ppNewObj), staticCast((pParent), Dynamic), (createFlags), ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, DispIpHal_ipver, arg_gpuInstance) @@ -1288,6 +1326,8 @@ NV_STATUS __nvoc_objCreate_OBJGPU(OBJGPU**, Dynamic*, NvU32, NvU32, NvU32, NvU32 #define gpuGetIdInfo_HAL(pGpu) gpuGetIdInfo_DISPATCH(pGpu) #define gpuHandleSanityCheckRegReadError(pGpu, addr, value) gpuHandleSanityCheckRegReadError_DISPATCH(pGpu, addr, value) #define gpuHandleSanityCheckRegReadError_HAL(pGpu, addr, value) gpuHandleSanityCheckRegReadError_DISPATCH(pGpu, addr, value) +#define gpuHandleSecFault(pGpu) gpuHandleSecFault_DISPATCH(pGpu) +#define gpuHandleSecFault_HAL(pGpu) gpuHandleSecFault_DISPATCH(pGpu) #define gpuGetChildrenPresent(pGpu, pNumEntries) gpuGetChildrenPresent_DISPATCH(pGpu, pNumEntries) #define gpuGetChildrenPresent_HAL(pGpu, pNumEntries) gpuGetChildrenPresent_DISPATCH(pGpu, pNumEntries) #define gpuGetClassDescriptorList(pGpu, arg0) gpuGetClassDescriptorList_DISPATCH(pGpu, arg0) @@ -1298,16 +1338,21 @@ NV_STATUS __nvoc_objCreate_OBJGPU(OBJGPU**, Dynamic*, NvU32, NvU32, NvU32, NvU32 #define gpuFuseSupportsDisplay_HAL(pGpu) gpuFuseSupportsDisplay_DISPATCH(pGpu) #define gpuClearFbhubPoisonIntrForBug2924523(pGpu) gpuClearFbhubPoisonIntrForBug2924523_DISPATCH(pGpu) #define gpuClearFbhubPoisonIntrForBug2924523_HAL(pGpu) gpuClearFbhubPoisonIntrForBug2924523_DISPATCH(pGpu) +#define gpuReadDeviceId(pGpu, arg0, arg1) gpuReadDeviceId_DISPATCH(pGpu, arg0, arg1) +#define gpuReadDeviceId_HAL(pGpu, arg0, arg1) gpuReadDeviceId_DISPATCH(pGpu, arg0, arg1) #define gpuConstructDeviceInfoTable(pGpu) gpuConstructDeviceInfoTable_DISPATCH(pGpu) #define gpuConstructDeviceInfoTable_HAL(pGpu) gpuConstructDeviceInfoTable_DISPATCH(pGpu) #define gpuGetFlaVasSize(pGpu, bNvswitchVirtualization) gpuGetFlaVasSize_DISPATCH(pGpu, bNvswitchVirtualization) #define gpuGetFlaVasSize_HAL(pGpu, bNvswitchVirtualization) gpuGetFlaVasSize_DISPATCH(pGpu, bNvswitchVirtualization) #define gpuIsAtsSupportedWithSmcMemPartitioning(pGpu) gpuIsAtsSupportedWithSmcMemPartitioning_DISPATCH(pGpu) #define gpuIsAtsSupportedWithSmcMemPartitioning_HAL(pGpu) gpuIsAtsSupportedWithSmcMemPartitioning_DISPATCH(pGpu) +#define gpuIsSliCapableWithoutDisplay(pGpu) gpuIsSliCapableWithoutDisplay_DISPATCH(pGpu) +#define gpuIsSliCapableWithoutDisplay_HAL(pGpu) gpuIsSliCapableWithoutDisplay_DISPATCH(pGpu) static inline NV_STATUS gpuConstructPhysical_56cd7a(struct OBJGPU *pGpu) { return NV_OK; } + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuConstructPhysical(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1323,6 +1368,7 @@ static inline void gpuDestructPhysical_b3696a(struct OBJGPU *pGpu) { return; } + #ifdef __nvoc_gpu_h_disabled static inline void gpuDestructPhysical(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1335,6 +1381,7 @@ static inline void gpuDestructPhysical(struct OBJGPU *pGpu) { NV_STATUS gpuStatePreInit_IMPL(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuStatePreInit(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1348,6 +1395,7 @@ static inline NV_STATUS gpuStatePreInit(struct OBJGPU *pGpu) { NV_STATUS gpuStateLoad_IMPL(struct OBJGPU *pGpu, NvU32 arg0); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuStateLoad(struct OBJGPU *pGpu, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1361,6 +1409,7 @@ static inline NV_STATUS gpuStateLoad(struct OBJGPU *pGpu, NvU32 arg0) { NV_STATUS gpuStateDestroy_IMPL(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuStateDestroy(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1376,6 +1425,7 @@ static inline NV_STATUS gpuApplyOverrides_46f6a7(struct OBJGPU *pGpu, NvU32 arg0 return NV_ERR_NOT_SUPPORTED; } + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuApplyOverrides(struct OBJGPU *pGpu, NvU32 arg0, NvU32 arg1) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1391,6 +1441,7 @@ static inline NV_STATUS gpuInitDevinitOverridesFromRegistry_56cd7a(struct OBJGPU return NV_OK; } + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuInitDevinitOverridesFromRegistry(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1406,6 +1457,7 @@ static inline NV_STATUS gpuApplyDevinitReg032Override_46f6a7(struct OBJGPU *pGpu return NV_ERR_NOT_SUPPORTED; } + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuApplyDevinitReg032Override(struct OBJGPU *pGpu, NvU32 *arg0, NvU32 *arg1) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1421,6 +1473,7 @@ static inline NV_STATUS gpuCheckPCIIDMismatch_56cd7a(struct OBJGPU *pGpu, struct return NV_OK; } + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuCheckPCIIDMismatch(struct OBJGPU *pGpu, struct OBJVBIOS *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1436,6 +1489,7 @@ static inline NvBool gpuCheckGpuIDMismatch_491d52(struct OBJGPU *pGpu, NvU32 *ar return ((NvBool)(0 != 0)); } + #ifdef __nvoc_gpu_h_disabled static inline NvBool gpuCheckGpuIDMismatch(struct OBJGPU *pGpu, NvU32 *arg0, NvU32 *arg1) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1447,8 +1501,83 @@ static inline NvBool gpuCheckGpuIDMismatch(struct OBJGPU *pGpu, NvU32 *arg0, NvU #define gpuCheckGpuIDMismatch_HAL(pGpu, arg0, arg1) gpuCheckGpuIDMismatch(pGpu, arg0, arg1) +static inline NV_STATUS gpuPowerManagementEnterPreUnloadPhysical_56cd7a(struct OBJGPU *pGpu) { + return NV_OK; +} + +NV_STATUS gpuPowerManagementEnterPreUnloadPhysical_IMPL(struct OBJGPU *pGpu); + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuPowerManagementEnterPreUnloadPhysical(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuPowerManagementEnterPreUnloadPhysical(pGpu) gpuPowerManagementEnterPreUnloadPhysical_56cd7a(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuPowerManagementEnterPreUnloadPhysical_HAL(pGpu) gpuPowerManagementEnterPreUnloadPhysical(pGpu) + +static inline NV_STATUS gpuPowerManagementEnterPostUnloadPhysical_56cd7a(struct OBJGPU *pGpu, NvU32 newLevel) { + return NV_OK; +} + +NV_STATUS gpuPowerManagementEnterPostUnloadPhysical_IMPL(struct OBJGPU *pGpu, NvU32 newLevel); + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuPowerManagementEnterPostUnloadPhysical(struct OBJGPU *pGpu, NvU32 newLevel) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuPowerManagementEnterPostUnloadPhysical(pGpu, newLevel) gpuPowerManagementEnterPostUnloadPhysical_56cd7a(pGpu, newLevel) +#endif //__nvoc_gpu_h_disabled + +#define gpuPowerManagementEnterPostUnloadPhysical_HAL(pGpu, newLevel) gpuPowerManagementEnterPostUnloadPhysical(pGpu, newLevel) + +static inline NV_STATUS gpuPowerManagementResumePreLoadPhysical_56cd7a(struct OBJGPU *pGpu, NvU32 oldLevel, NvU32 flags) { + return NV_OK; +} + +NV_STATUS gpuPowerManagementResumePreLoadPhysical_IMPL(struct OBJGPU *pGpu, NvU32 oldLevel, NvU32 flags); + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuPowerManagementResumePreLoadPhysical(struct OBJGPU *pGpu, NvU32 oldLevel, NvU32 flags) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuPowerManagementResumePreLoadPhysical(pGpu, oldLevel, flags) gpuPowerManagementResumePreLoadPhysical_56cd7a(pGpu, oldLevel, flags) +#endif //__nvoc_gpu_h_disabled + +#define gpuPowerManagementResumePreLoadPhysical_HAL(pGpu, oldLevel, flags) gpuPowerManagementResumePreLoadPhysical(pGpu, oldLevel, flags) + +static inline NV_STATUS gpuPowerManagementResumePostLoadPhysical_56cd7a(struct OBJGPU *pGpu) { + return NV_OK; +} + +NV_STATUS gpuPowerManagementResumePostLoadPhysical_IMPL(struct OBJGPU *pGpu); + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuPowerManagementResumePostLoadPhysical(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuPowerManagementResumePostLoadPhysical(pGpu) gpuPowerManagementResumePostLoadPhysical_56cd7a(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuPowerManagementResumePostLoadPhysical_HAL(pGpu) gpuPowerManagementResumePostLoadPhysical(pGpu) + NV_STATUS gpuGetNameString_KERNEL(struct OBJGPU *pGpu, NvU32 arg0, void *arg1); +NV_STATUS gpuGetNameString_IMPL(struct OBJGPU *pGpu, NvU32 arg0, void *arg1); + + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuGetNameString(struct OBJGPU *pGpu, NvU32 arg0, void *arg1) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1462,6 +1591,9 @@ static inline NV_STATUS gpuGetNameString(struct OBJGPU *pGpu, NvU32 arg0, void * NV_STATUS gpuGetShortNameString_KERNEL(struct OBJGPU *pGpu, NvU8 *arg0); +NV_STATUS gpuGetShortNameString_IMPL(struct OBJGPU *pGpu, NvU8 *arg0); + + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuGetShortNameString(struct OBJGPU *pGpu, NvU8 *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1475,6 +1607,7 @@ static inline NV_STATUS gpuGetShortNameString(struct OBJGPU *pGpu, NvU8 *arg0) { void gpuInitBranding_FWCLIENT(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline void gpuInitBranding(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1487,6 +1620,7 @@ static inline void gpuInitBranding(struct OBJGPU *pGpu) { BRANDING_TYPE gpuDetectBranding_FWCLIENT(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline BRANDING_TYPE gpuDetectBranding(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1502,6 +1636,7 @@ static inline BRANDING_TYPE gpuDetectBranding(struct OBJGPU *pGpu) { COMPUTE_BRANDING_TYPE gpuDetectComputeBranding_FWCLIENT(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline COMPUTE_BRANDING_TYPE gpuDetectComputeBranding(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1517,6 +1652,7 @@ static inline COMPUTE_BRANDING_TYPE gpuDetectComputeBranding(struct OBJGPU *pGpu BRANDING_TYPE gpuDetectVgxBranding_FWCLIENT(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline BRANDING_TYPE gpuDetectVgxBranding(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1530,10 +1666,24 @@ static inline BRANDING_TYPE gpuDetectVgxBranding(struct OBJGPU *pGpu) { #define gpuDetectVgxBranding_HAL(pGpu) gpuDetectVgxBranding(pGpu) +void gpuInitProperties_FWCLIENT(struct OBJGPU *pGpu); + + +#ifdef __nvoc_gpu_h_disabled +static inline void gpuInitProperties(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); +} +#else //__nvoc_gpu_h_disabled +#define gpuInitProperties(pGpu) gpuInitProperties_FWCLIENT(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuInitProperties_HAL(pGpu) gpuInitProperties(pGpu) + static inline void gpuDeterminePersistantIllumSettings_b3696a(struct OBJGPU *pGpu) { return; } + #ifdef __nvoc_gpu_h_disabled static inline void gpuDeterminePersistantIllumSettings(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1548,6 +1698,7 @@ static inline NV_STATUS gpuInitSliIllumination_46f6a7(struct OBJGPU *pGpu) { return NV_ERR_NOT_SUPPORTED; } + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuInitSliIllumination(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1561,6 +1712,7 @@ static inline NV_STATUS gpuInitSliIllumination(struct OBJGPU *pGpu) { NV_STATUS gpuBuildGenericKernelFalconList_IMPL(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuBuildGenericKernelFalconList(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1574,6 +1726,7 @@ static inline NV_STATUS gpuBuildGenericKernelFalconList(struct OBJGPU *pGpu) { void gpuDestroyGenericKernelFalconList_IMPL(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline void gpuDestroyGenericKernelFalconList(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1586,6 +1739,7 @@ static inline void gpuDestroyGenericKernelFalconList(struct OBJGPU *pGpu) { struct GenericKernelFalcon *gpuGetGenericKernelFalconForEngine_IMPL(struct OBJGPU *pGpu, ENGDESCRIPTOR arg0); + #ifdef __nvoc_gpu_h_disabled static inline struct GenericKernelFalcon *gpuGetGenericKernelFalconForEngine(struct OBJGPU *pGpu, ENGDESCRIPTOR arg0) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1599,6 +1753,7 @@ static inline struct GenericKernelFalcon *gpuGetGenericKernelFalconForEngine(str void gpuRegisterGenericKernelFalconIntrService_IMPL(struct OBJGPU *pGpu, void *pRecords); + #ifdef __nvoc_gpu_h_disabled static inline void gpuRegisterGenericKernelFalconIntrService(struct OBJGPU *pGpu, void *pRecords) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1613,6 +1768,7 @@ static inline void gpuGetHwDefaults_b3696a(struct OBJGPU *pGpu) { return; } + #ifdef __nvoc_gpu_h_disabled static inline void gpuGetHwDefaults(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1625,6 +1781,7 @@ static inline void gpuGetHwDefaults(struct OBJGPU *pGpu) { RmPhysAddr gpuGetDmaEndAddress_IMPL(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline RmPhysAddr gpuGetDmaEndAddress(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1642,6 +1799,7 @@ static inline NV_STATUS gpuMarkDeviceForReset_46f6a7(struct OBJGPU *pGpu) { return NV_ERR_NOT_SUPPORTED; } + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuMarkDeviceForReset(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1657,6 +1815,7 @@ static inline NV_STATUS gpuMarkDeviceForDrainAndReset_46f6a7(struct OBJGPU *pGpu return NV_ERR_NOT_SUPPORTED; } + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuMarkDeviceForDrainAndReset(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1672,6 +1831,7 @@ static inline NvU32 gpuGetSliFingerPinsetMask_4a4dee(struct OBJGPU *pGpu) { return 0; } + #ifdef __nvoc_gpu_h_disabled static inline NvU32 gpuGetSliFingerPinsetMask(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1687,6 +1847,7 @@ static inline NV_STATUS gpuPrivSecInitRegistryOverrides_56cd7a(struct OBJGPU *pG return NV_OK; } + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuPrivSecInitRegistryOverrides(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1702,6 +1863,7 @@ static inline void gpuDestroyOverrides_b3696a(struct OBJGPU *pGpu) { return; } + #ifdef __nvoc_gpu_h_disabled static inline void gpuDestroyOverrides(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1714,6 +1876,7 @@ static inline void gpuDestroyOverrides(struct OBJGPU *pGpu) { NV_STATUS gpuSetPower_GM107(struct OBJGPU *pGpu, NvU32 arg1, NvU32 arg2, NvU32 arg3); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuSetPower(struct OBJGPU *pGpu, NvU32 arg1, NvU32 arg2, NvU32 arg3) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1729,6 +1892,9 @@ static inline void gpuUpdateIdInfo_b3696a(struct OBJGPU *pGpu) { return; } +void gpuUpdateIdInfo_GK104(struct OBJGPU *pGpu); + + #ifdef __nvoc_gpu_h_disabled static inline void gpuUpdateIdInfo(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1743,6 +1909,7 @@ static inline NvU32 gpuGetDeviceIDList_4a4dee(struct OBJGPU *pGpu, DEVICE_ID_MAP return 0; } + #ifdef __nvoc_gpu_h_disabled static inline NvU32 gpuGetDeviceIDList(struct OBJGPU *pGpu, DEVICE_ID_MAPPING **arg0) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1756,6 +1923,9 @@ static inline NvU32 gpuGetDeviceIDList(struct OBJGPU *pGpu, DEVICE_ID_MAPPING ** NV_STATUS gpuGenGidData_FWCLIENT(struct OBJGPU *pGpu, NvU8 *pGidData, NvU32 gidSize, NvU32 gidFlags); +NV_STATUS gpuGenGidData_GK104(struct OBJGPU *pGpu, NvU8 *pGidData, NvU32 gidSize, NvU32 gidFlags); + + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuGenGidData(struct OBJGPU *pGpu, NvU8 *pGidData, NvU32 gidSize, NvU32 gidFlags) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1769,6 +1939,11 @@ static inline NV_STATUS gpuGenGidData(struct OBJGPU *pGpu, NvU8 *pGidData, NvU32 NvU8 gpuGetChipSubRev_FWCLIENT(struct OBJGPU *pGpu); +NvU8 gpuGetChipSubRev_GK104(struct OBJGPU *pGpu); + +NvU8 gpuGetChipSubRev_GA100(struct OBJGPU *pGpu); + + #ifdef __nvoc_gpu_h_disabled static inline NvU8 gpuGetChipSubRev(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1782,6 +1957,9 @@ static inline NvU8 gpuGetChipSubRev(struct OBJGPU *pGpu) { NvU32 gpuGetEmulationRev1_FWCLIENT(struct OBJGPU *pGpu); +NvU32 gpuGetEmulationRev1_GM107(struct OBJGPU *pGpu); + + #ifdef __nvoc_gpu_h_disabled static inline NvU32 gpuGetEmulationRev1(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1797,6 +1975,9 @@ static inline NV_STATUS gpuPerformUniversalValidation_56cd7a(struct OBJGPU *pGpu return NV_OK; } +NV_STATUS gpuPerformUniversalValidation_GM107(struct OBJGPU *pGpu); + + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuPerformUniversalValidation(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1810,6 +1991,7 @@ static inline NV_STATUS gpuPerformUniversalValidation(struct OBJGPU *pGpu) { NvU32 gpuGetVirtRegPhysOffset_TU102(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline NvU32 gpuGetVirtRegPhysOffset(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1823,6 +2005,9 @@ static inline NvU32 gpuGetVirtRegPhysOffset(struct OBJGPU *pGpu) { NV_STATUS gpuGetRegBaseOffset_FWCLIENT(struct OBJGPU *pGpu, NvU32 arg0, NvU32 *arg1); +NV_STATUS gpuGetRegBaseOffset_TU102(struct OBJGPU *pGpu, NvU32 arg0, NvU32 *arg1); + + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuGetRegBaseOffset(struct OBJGPU *pGpu, NvU32 arg0, NvU32 *arg1) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1838,6 +2023,11 @@ static inline void gpuGetSanityCheckRegReadError_b3696a(struct OBJGPU *pGpu, NvU return; } +void gpuGetSanityCheckRegReadError_GK104(struct OBJGPU *pGpu, NvU32 value, const char **pErrorString); + +void gpuGetSanityCheckRegReadError_GA100(struct OBJGPU *pGpu, NvU32 value, const char **pErrorString); + + #ifdef __nvoc_gpu_h_disabled static inline void gpuGetSanityCheckRegReadError(struct OBJGPU *pGpu, NvU32 value, const char **pErrorString) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1852,6 +2042,11 @@ static inline NV_STATUS gpuSanityCheckVirtRegAccess_56cd7a(struct OBJGPU *pGpu, return NV_OK; } +NV_STATUS gpuSanityCheckVirtRegAccess_TU102(struct OBJGPU *pGpu, NvU32 arg0); + +NV_STATUS gpuSanityCheckVirtRegAccess_GH100(struct OBJGPU *pGpu, NvU32 arg0); + + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuSanityCheckVirtRegAccess(struct OBJGPU *pGpu, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1865,6 +2060,7 @@ static inline NV_STATUS gpuSanityCheckVirtRegAccess(struct OBJGPU *pGpu, NvU32 a NV_STATUS gpuInitRegistryOverrides_KERNEL(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuInitRegistryOverrides(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1878,6 +2074,7 @@ static inline NV_STATUS gpuInitRegistryOverrides(struct OBJGPU *pGpu) { NV_STATUS gpuInitInstLocOverrides_IMPL(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuInitInstLocOverrides(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1891,6 +2088,7 @@ static inline NV_STATUS gpuInitInstLocOverrides(struct OBJGPU *pGpu) { const GPUCHILDORDER *gpuGetChildrenOrder_GM200(struct OBJGPU *pGpu, NvU32 *pNumEntries); + #ifdef __nvoc_gpu_h_disabled static inline const GPUCHILDORDER *gpuGetChildrenOrder(struct OBJGPU *pGpu, NvU32 *pNumEntries) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1904,6 +2102,9 @@ static inline const GPUCHILDORDER *gpuGetChildrenOrder(struct OBJGPU *pGpu, NvU3 NV_STATUS gpuInitSriov_FWCLIENT(struct OBJGPU *pGpu); +NV_STATUS gpuInitSriov_TU102(struct OBJGPU *pGpu); + + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuInitSriov(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1917,6 +2118,9 @@ static inline NV_STATUS gpuInitSriov(struct OBJGPU *pGpu) { NV_STATUS gpuDeinitSriov_FWCLIENT(struct OBJGPU *pGpu); +NV_STATUS gpuDeinitSriov_TU102(struct OBJGPU *pGpu); + + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuDeinitSriov(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1932,6 +2136,7 @@ static inline NV_STATUS gpuCreateDefaultClientShare_56cd7a(struct OBJGPU *pGpu) return NV_OK; } + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuCreateDefaultClientShare(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1947,6 +2152,7 @@ static inline void gpuDestroyDefaultClientShare_b3696a(struct OBJGPU *pGpu) { return; } + #ifdef __nvoc_gpu_h_disabled static inline void gpuDestroyDefaultClientShare(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1959,6 +2165,9 @@ static inline void gpuDestroyDefaultClientShare(struct OBJGPU *pGpu) { NvU32 gpuGetActiveFBIOs_FWCLIENT(struct OBJGPU *pGpu); +NvU32 gpuGetActiveFBIOs_GM107(struct OBJGPU *pGpu); + + #ifdef __nvoc_gpu_h_disabled static inline NvU32 gpuGetActiveFBIOs(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1974,6 +2183,7 @@ static inline NvBool gpuIsDebuggerActive_8031b9(struct OBJGPU *pGpu) { return pGpu->bIsDebugModeEnabled; } + #ifdef __nvoc_gpu_h_disabled static inline NvBool gpuIsDebuggerActive(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1987,6 +2197,7 @@ static inline NvBool gpuIsDebuggerActive(struct OBJGPU *pGpu) { NV_STATUS gpuExecGrCtxRegops_GK104(struct OBJGPU *pGpu, struct Graphics *arg0, struct KernelChannel *arg1, NV2080_CTRL_GPU_REG_OP *pRegOps, NvU32 regOpCount, RMTIMEOUT *pTimeout, NvBool bStopCtxsw); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuExecGrCtxRegops(struct OBJGPU *pGpu, struct Graphics *arg0, struct KernelChannel *arg1, NV2080_CTRL_GPU_REG_OP *pRegOps, NvU32 regOpCount, RMTIMEOUT *pTimeout, NvBool bStopCtxsw) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -1998,8 +2209,27 @@ static inline NV_STATUS gpuExecGrCtxRegops(struct OBJGPU *pGpu, struct Graphics #define gpuExecGrCtxRegops_HAL(pGpu, arg0, arg1, pRegOps, regOpCount, pTimeout, bStopCtxsw) gpuExecGrCtxRegops(pGpu, arg0, arg1, pRegOps, regOpCount, pTimeout, bStopCtxsw) +NV_STATUS gpuExtdevConstruct_GK104(struct OBJGPU *pGpu); + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuExtdevConstruct(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuExtdevConstruct(pGpu) gpuExtdevConstruct_GK104(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuExtdevConstruct_HAL(pGpu) gpuExtdevConstruct(pGpu) + NvU32 gpuReadBAR1Size_FWCLIENT(struct OBJGPU *pGpu); +NvU32 gpuReadBAR1Size_TU102(struct OBJGPU *pGpu); + +NvU32 gpuReadBAR1Size_GH100(struct OBJGPU *pGpu); + + #ifdef __nvoc_gpu_h_disabled static inline NvU32 gpuReadBAR1Size(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2013,6 +2243,9 @@ static inline NvU32 gpuReadBAR1Size(struct OBJGPU *pGpu) { NvBool gpuCheckPageRetirementSupport_GSPCLIENT(struct OBJGPU *pGpu); +NvBool gpuCheckPageRetirementSupport_GV100(struct OBJGPU *pGpu); + + #ifdef __nvoc_gpu_h_disabled static inline NvBool gpuCheckPageRetirementSupport(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2026,6 +2259,9 @@ static inline NvBool gpuCheckPageRetirementSupport(struct OBJGPU *pGpu) { NvBool gpuIsInternalSku_FWCLIENT(struct OBJGPU *pGpu); +NvBool gpuIsInternalSku_GP100(struct OBJGPU *pGpu); + + #ifdef __nvoc_gpu_h_disabled static inline NvBool gpuIsInternalSku(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2037,10 +2273,31 @@ static inline NvBool gpuIsInternalSku(struct OBJGPU *pGpu) { #define gpuIsInternalSku_HAL(pGpu) gpuIsInternalSku(pGpu) +NV_STATUS gpuGetSriovCaps_TU102(struct OBJGPU *pGpu, NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS *arg0); + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuGetSriovCaps(struct OBJGPU *pGpu, NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS *arg0) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuGetSriovCaps(pGpu, arg0) gpuGetSriovCaps_TU102(pGpu, arg0) +#endif //__nvoc_gpu_h_disabled + +#define gpuGetSriovCaps_HAL(pGpu, arg0) gpuGetSriovCaps(pGpu, arg0) + static inline NvBool gpuCheckIsP2PAllocated_491d52(struct OBJGPU *pGpu) { return ((NvBool)(0 != 0)); } +NvBool gpuCheckIsP2PAllocated_GA100(struct OBJGPU *pGpu); + +static inline NvBool gpuCheckIsP2PAllocated_108313(struct OBJGPU *pGpu) { + NV_ASSERT_OR_RETURN_PRECOMP(0, ((NvBool)(0 != 0))); +} + + #ifdef __nvoc_gpu_h_disabled static inline NvBool gpuCheckIsP2PAllocated(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2052,8 +2309,24 @@ static inline NvBool gpuCheckIsP2PAllocated(struct OBJGPU *pGpu) { #define gpuCheckIsP2PAllocated_HAL(pGpu) gpuCheckIsP2PAllocated(pGpu) +static inline void gpuDecodeDeviceInfoTableGroupId_b3696a(struct OBJGPU *pGpu, DEVICE_INFO2_TABLE *pEntry, NvU32 *pDeviceAccum) { + return; +} + + +#ifdef __nvoc_gpu_h_disabled +static inline void gpuDecodeDeviceInfoTableGroupId(struct OBJGPU *pGpu, DEVICE_INFO2_TABLE *pEntry, NvU32 *pDeviceAccum) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); +} +#else //__nvoc_gpu_h_disabled +#define gpuDecodeDeviceInfoTableGroupId(pGpu, pEntry, pDeviceAccum) gpuDecodeDeviceInfoTableGroupId_b3696a(pGpu, pEntry, pDeviceAccum) +#endif //__nvoc_gpu_h_disabled + +#define gpuDecodeDeviceInfoTableGroupId_HAL(pGpu, pEntry, pDeviceAccum) gpuDecodeDeviceInfoTableGroupId(pGpu, pEntry, pDeviceAccum) + NV_STATUS gpuVerifyExistence_IMPL(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuVerifyExistence(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2069,6 +2342,9 @@ static inline void gpuResetVFRegisters_b3696a(struct OBJGPU *pGpu, NvU32 gfid) { return; } +void gpuResetVFRegisters_TU102(struct OBJGPU *pGpu, NvU32 gfid); + + #ifdef __nvoc_gpu_h_disabled static inline void gpuResetVFRegisters(struct OBJGPU *pGpu, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2081,6 +2357,17 @@ static inline void gpuResetVFRegisters(struct OBJGPU *pGpu, NvU32 gfid) { NvU32 gpuGetLitterValues_FWCLIENT(struct OBJGPU *pGpu, NvU32 index); +NvU32 gpuGetLitterValues_TU102(struct OBJGPU *pGpu, NvU32 index); + +NvU32 gpuGetLitterValues_GA100(struct OBJGPU *pGpu, NvU32 index); + +NvU32 gpuGetLitterValues_GA102(struct OBJGPU *pGpu, NvU32 index); + +NvU32 gpuGetLitterValues_AD102(struct OBJGPU *pGpu, NvU32 index); + +NvU32 gpuGetLitterValues_GH100(struct OBJGPU *pGpu, NvU32 index); + + #ifdef __nvoc_gpu_h_disabled static inline NvU32 gpuGetLitterValues(struct OBJGPU *pGpu, NvU32 index) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2094,6 +2381,7 @@ static inline NvU32 gpuGetLitterValues(struct OBJGPU *pGpu, NvU32 index) { NvBool gpuIsGlobalPoisonFuseEnabled_FWCLIENT(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline NvBool gpuIsGlobalPoisonFuseEnabled(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2105,10 +2393,39 @@ static inline NvBool gpuIsGlobalPoisonFuseEnabled(struct OBJGPU *pGpu) { #define gpuIsGlobalPoisonFuseEnabled_HAL(pGpu) gpuIsGlobalPoisonFuseEnabled(pGpu) +NV_STATUS gpuInitOptimusSettings_IMPL(struct OBJGPU *pGpu); + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuInitOptimusSettings(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuInitOptimusSettings(pGpu) gpuInitOptimusSettings_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuInitOptimusSettings_HAL(pGpu) gpuInitOptimusSettings(pGpu) + +NV_STATUS gpuDeinitOptimusSettings_IMPL(struct OBJGPU *pGpu); + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuDeinitOptimusSettings(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuDeinitOptimusSettings(pGpu) gpuDeinitOptimusSettings_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuDeinitOptimusSettings_HAL(pGpu) gpuDeinitOptimusSettings(pGpu) + static inline NV_STATUS gpuSetCacheOnlyModeOverrides_56cd7a(struct OBJGPU *pGpu) { return NV_OK; } + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuSetCacheOnlyModeOverrides(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2122,6 +2439,7 @@ static inline NV_STATUS gpuSetCacheOnlyModeOverrides(struct OBJGPU *pGpu) { NV_STATUS gpuGetCeFaultMethodBufferSize_KERNEL(struct OBJGPU *arg0, NvU32 *arg1); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuGetCeFaultMethodBufferSize(struct OBJGPU *arg0, NvU32 *arg1) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2133,29 +2451,44 @@ static inline NV_STATUS gpuGetCeFaultMethodBufferSize(struct OBJGPU *arg0, NvU32 #define gpuGetCeFaultMethodBufferSize_HAL(arg0, arg1) gpuGetCeFaultMethodBufferSize(arg0, arg1) -static inline NV_STATUS gpuSetVFBarSizes_56cd7a(struct OBJGPU *pGpu, NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS *arg0) { - return NV_OK; +static inline NV_STATUS gpuSetVFBarSizes_46f6a7(struct OBJGPU *pGpu, NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS *arg0) { + return NV_ERR_NOT_SUPPORTED; } +NV_STATUS gpuSetVFBarSizes_GA102(struct OBJGPU *pGpu, NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS *arg0); + + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuSetVFBarSizes(struct OBJGPU *pGpu, NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_gpu_h_disabled -#define gpuSetVFBarSizes(pGpu, arg0) gpuSetVFBarSizes_56cd7a(pGpu, arg0) +#define gpuSetVFBarSizes(pGpu, arg0) gpuSetVFBarSizes_46f6a7(pGpu, arg0) #endif //__nvoc_gpu_h_disabled #define gpuSetVFBarSizes_HAL(pGpu, arg0) gpuSetVFBarSizes(pGpu, arg0) +static inline GPU_P2P_PEER_GPU_CAPS *gpuFindP2PPeerGpuCapsByGpuId_80f438(struct OBJGPU *pGpu, NvU32 peerGpuId) { + NV_ASSERT_OR_RETURN_PRECOMP(0, ((void *)0)); +} + + +#ifdef __nvoc_gpu_h_disabled +static inline GPU_P2P_PEER_GPU_CAPS *gpuFindP2PPeerGpuCapsByGpuId(struct OBJGPU *pGpu, NvU32 peerGpuId) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NULL; +} +#else //__nvoc_gpu_h_disabled +#define gpuFindP2PPeerGpuCapsByGpuId(pGpu, peerGpuId) gpuFindP2PPeerGpuCapsByGpuId_80f438(pGpu, peerGpuId) +#endif //__nvoc_gpu_h_disabled + +#define gpuFindP2PPeerGpuCapsByGpuId_HAL(pGpu, peerGpuId) gpuFindP2PPeerGpuCapsByGpuId(pGpu, peerGpuId) + NV_STATUS gpuWriteBusConfigReg_GM107(struct OBJGPU *pGpu, NvU32 index, NvU32 value); NV_STATUS gpuWriteBusConfigReg_GH100(struct OBJGPU *pGpu, NvU32 index, NvU32 value); -static inline NV_STATUS gpuWriteBusConfigReg_46f6a7(struct OBJGPU *pGpu, NvU32 index, NvU32 value) { - return NV_ERR_NOT_SUPPORTED; -} - static inline NV_STATUS gpuWriteBusConfigReg_DISPATCH(struct OBJGPU *pGpu, NvU32 index, NvU32 value) { return pGpu->__gpuWriteBusConfigReg__(pGpu, index, value); } @@ -2164,10 +2497,6 @@ NV_STATUS gpuReadBusConfigReg_GM107(struct OBJGPU *pGpu, NvU32 index, NvU32 *dat NV_STATUS gpuReadBusConfigReg_GH100(struct OBJGPU *pGpu, NvU32 index, NvU32 *data); -static inline NV_STATUS gpuReadBusConfigReg_46f6a7(struct OBJGPU *pGpu, NvU32 index, NvU32 *data) { - return NV_ERR_NOT_SUPPORTED; -} - static inline NV_STATUS gpuReadBusConfigReg_DISPATCH(struct OBJGPU *pGpu, NvU32 index, NvU32 *data) { return pGpu->__gpuReadBusConfigReg__(pGpu, index, data); } @@ -2216,10 +2545,6 @@ void gpuGetIdInfo_GM107(struct OBJGPU *pGpu); void gpuGetIdInfo_GH100(struct OBJGPU *pGpu); -static inline void gpuGetIdInfo_b3696a(struct OBJGPU *pGpu) { - return; -} - static inline void gpuGetIdInfo_DISPATCH(struct OBJGPU *pGpu) { pGpu->__gpuGetIdInfo__(pGpu); } @@ -2228,12 +2553,18 @@ void gpuHandleSanityCheckRegReadError_GM107(struct OBJGPU *pGpu, NvU32 addr, NvU void gpuHandleSanityCheckRegReadError_GH100(struct OBJGPU *pGpu, NvU32 addr, NvU32 value); -static inline void gpuHandleSanityCheckRegReadError_b3696a(struct OBJGPU *pGpu, NvU32 addr, NvU32 value) { +static inline void gpuHandleSanityCheckRegReadError_DISPATCH(struct OBJGPU *pGpu, NvU32 addr, NvU32 value) { + pGpu->__gpuHandleSanityCheckRegReadError__(pGpu, addr, value); +} + +void gpuHandleSecFault_GH100(struct OBJGPU *pGpu); + +static inline void gpuHandleSecFault_b3696a(struct OBJGPU *pGpu) { return; } -static inline void gpuHandleSanityCheckRegReadError_DISPATCH(struct OBJGPU *pGpu, NvU32 addr, NvU32 value) { - pGpu->__gpuHandleSanityCheckRegReadError__(pGpu, addr, value); +static inline void gpuHandleSecFault_DISPATCH(struct OBJGPU *pGpu) { + pGpu->__gpuHandleSecFault__(pGpu); } const GPUCHILDPRESENT *gpuGetChildrenPresent_TU102(struct OBJGPU *pGpu, NvU32 *pNumEntries); @@ -2286,10 +2617,6 @@ NvBool gpuFuseSupportsDisplay_GM107(struct OBJGPU *pGpu); NvBool gpuFuseSupportsDisplay_GA100(struct OBJGPU *pGpu); -static inline NvBool gpuFuseSupportsDisplay_491d52(struct OBJGPU *pGpu) { - return ((NvBool)(0 != 0)); -} - static inline NvBool gpuFuseSupportsDisplay_DISPATCH(struct OBJGPU *pGpu) { return pGpu->__gpuFuseSupportsDisplay__(pGpu); } @@ -2306,6 +2633,14 @@ static inline NV_STATUS gpuClearFbhubPoisonIntrForBug2924523_DISPATCH(struct OBJ return pGpu->__gpuClearFbhubPoisonIntrForBug2924523__(pGpu); } +void gpuReadDeviceId_GM107(struct OBJGPU *pGpu, NvU32 *arg0, NvU32 *arg1); + +void gpuReadDeviceId_GH100(struct OBJGPU *pGpu, NvU32 *arg0, NvU32 *arg1); + +static inline void gpuReadDeviceId_DISPATCH(struct OBJGPU *pGpu, NvU32 *arg0, NvU32 *arg1) { + pGpu->__gpuReadDeviceId__(pGpu, arg0, arg1); +} + NV_STATUS gpuConstructDeviceInfoTable_FWCLIENT(struct OBJGPU *pGpu); static inline NV_STATUS gpuConstructDeviceInfoTable_56cd7a(struct OBJGPU *pGpu) { @@ -2340,6 +2675,18 @@ static inline NvBool gpuIsAtsSupportedWithSmcMemPartitioning_DISPATCH(struct OBJ return pGpu->__gpuIsAtsSupportedWithSmcMemPartitioning__(pGpu); } +static inline NvBool gpuIsSliCapableWithoutDisplay_cbe027(struct OBJGPU *pGpu) { + return ((NvBool)(0 == 0)); +} + +static inline NvBool gpuIsSliCapableWithoutDisplay_491d52(struct OBJGPU *pGpu) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool gpuIsSliCapableWithoutDisplay_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuIsSliCapableWithoutDisplay__(pGpu); +} + static inline PENGDESCRIPTOR gpuGetInitEngineDescriptors(struct OBJGPU *pGpu) { return pGpu->engineOrder.pEngineInitDescriptors; } @@ -2573,13 +2920,19 @@ static inline NvBool gpuIsComputePolicyTimesliceSupported(struct OBJGPU *pGpu) { return pGpu->bComputePolicyTimesliceSupported; } +static inline NvBool gpuIsSriovCapable(struct OBJGPU *pGpu) { + return pGpu->bSriovCapable; +} + static inline NvBool gpuIsCpuFirmwareHandlesFbEccInterruptEnabled(struct OBJGPU *pGpu) { return pGpu->bCpuFirmwareHandlesFbEccInterruptEnabled; } NV_STATUS gpuConstruct_IMPL(struct OBJGPU *arg_pGpu, NvU32 arg_gpuInstance); + #define __nvoc_gpuConstruct(arg_pGpu, arg_gpuInstance) gpuConstruct_IMPL(arg_pGpu, arg_gpuInstance) NV_STATUS gpuBindHalLegacy_IMPL(struct OBJGPU *pGpu, NvU32 chipId0, NvU32 chipId1); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuBindHalLegacy(struct OBJGPU *pGpu, NvU32 chipId0, NvU32 chipId1) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2590,6 +2943,7 @@ static inline NV_STATUS gpuBindHalLegacy(struct OBJGPU *pGpu, NvU32 chipId0, NvU #endif //__nvoc_gpu_h_disabled NV_STATUS gpuPostConstruct_IMPL(struct OBJGPU *pGpu, GPUATTACHARG *arg0); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuPostConstruct(struct OBJGPU *pGpu, GPUATTACHARG *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2600,6 +2954,7 @@ static inline NV_STATUS gpuPostConstruct(struct OBJGPU *pGpu, GPUATTACHARG *arg0 #endif //__nvoc_gpu_h_disabled NV_STATUS gpuCreateObject_IMPL(struct OBJGPU *pGpu, NVOC_CLASS_ID arg0, NvU32 arg1); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuCreateObject(struct OBJGPU *pGpu, NVOC_CLASS_ID arg0, NvU32 arg1) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2610,8 +2965,10 @@ static inline NV_STATUS gpuCreateObject(struct OBJGPU *pGpu, NVOC_CLASS_ID arg0, #endif //__nvoc_gpu_h_disabled void gpuDestruct_IMPL(struct OBJGPU *pGpu); + #define __nvoc_gpuDestruct(pGpu) gpuDestruct_IMPL(pGpu) NV_STATUS gpuStateInit_IMPL(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuStateInit(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2622,6 +2979,7 @@ static inline NV_STATUS gpuStateInit(struct OBJGPU *pGpu) { #endif //__nvoc_gpu_h_disabled NV_STATUS gpuStateUnload_IMPL(struct OBJGPU *pGpu, NvU32 arg0); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuStateUnload(struct OBJGPU *pGpu, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2632,6 +2990,7 @@ static inline NV_STATUS gpuStateUnload(struct OBJGPU *pGpu, NvU32 arg0) { #endif //__nvoc_gpu_h_disabled NV_STATUS gpuInitDispIpHal_IMPL(struct OBJGPU *pGpu, NvU32 ipver); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuInitDispIpHal(struct OBJGPU *pGpu, NvU32 ipver) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2642,6 +3001,7 @@ static inline NV_STATUS gpuInitDispIpHal(struct OBJGPU *pGpu, NvU32 ipver) { #endif //__nvoc_gpu_h_disabled void gpuServiceInterruptsAllGpus_IMPL(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline void gpuServiceInterruptsAllGpus(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2651,6 +3011,7 @@ static inline void gpuServiceInterruptsAllGpus(struct OBJGPU *pGpu) { #endif //__nvoc_gpu_h_disabled NvBool gpuIsImplementation_IMPL(struct OBJGPU *pGpu, HAL_IMPLEMENTATION arg0, NvU32 arg1, NvU32 arg2); + #ifdef __nvoc_gpu_h_disabled static inline NvBool gpuIsImplementation(struct OBJGPU *pGpu, HAL_IMPLEMENTATION arg0, NvU32 arg1, NvU32 arg2) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2661,6 +3022,7 @@ static inline NvBool gpuIsImplementation(struct OBJGPU *pGpu, HAL_IMPLEMENTATION #endif //__nvoc_gpu_h_disabled NvBool gpuIsImplementationOrBetter_IMPL(struct OBJGPU *pGpu, HAL_IMPLEMENTATION arg0, NvU32 arg1, NvU32 arg2); + #ifdef __nvoc_gpu_h_disabled static inline NvBool gpuIsImplementationOrBetter(struct OBJGPU *pGpu, HAL_IMPLEMENTATION arg0, NvU32 arg1, NvU32 arg2) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2671,6 +3033,7 @@ static inline NvBool gpuIsImplementationOrBetter(struct OBJGPU *pGpu, HAL_IMPLEM #endif //__nvoc_gpu_h_disabled NvBool gpuIsGpuFullPower_IMPL(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline NvBool gpuIsGpuFullPower(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2681,6 +3044,7 @@ static inline NvBool gpuIsGpuFullPower(struct OBJGPU *pGpu) { #endif //__nvoc_gpu_h_disabled NvBool gpuIsGpuFullPowerForPmResume_IMPL(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline NvBool gpuIsGpuFullPowerForPmResume(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2691,6 +3055,7 @@ static inline NvBool gpuIsGpuFullPowerForPmResume(struct OBJGPU *pGpu) { #endif //__nvoc_gpu_h_disabled NV_STATUS gpuBuildClassDB_IMPL(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuBuildClassDB(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2701,6 +3066,7 @@ static inline NV_STATUS gpuBuildClassDB(struct OBJGPU *pGpu) { #endif //__nvoc_gpu_h_disabled NV_STATUS gpuDestroyClassDB_IMPL(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuDestroyClassDB(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2711,6 +3077,7 @@ static inline NV_STATUS gpuDestroyClassDB(struct OBJGPU *pGpu) { #endif //__nvoc_gpu_h_disabled NV_STATUS gpuDeleteEngineFromClassDB_IMPL(struct OBJGPU *pGpu, NvU32 arg0); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuDeleteEngineFromClassDB(struct OBJGPU *pGpu, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2721,6 +3088,7 @@ static inline NV_STATUS gpuDeleteEngineFromClassDB(struct OBJGPU *pGpu, NvU32 ar #endif //__nvoc_gpu_h_disabled NV_STATUS gpuDeleteEngineOnPreInit_IMPL(struct OBJGPU *pGpu, NvU32 arg0); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuDeleteEngineOnPreInit(struct OBJGPU *pGpu, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2731,6 +3099,7 @@ static inline NV_STATUS gpuDeleteEngineOnPreInit(struct OBJGPU *pGpu, NvU32 arg0 #endif //__nvoc_gpu_h_disabled NV_STATUS gpuAddClassToClassDBByEngTag_IMPL(struct OBJGPU *pGpu, NvU32 arg0); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuAddClassToClassDBByEngTag(struct OBJGPU *pGpu, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2741,6 +3110,7 @@ static inline NV_STATUS gpuAddClassToClassDBByEngTag(struct OBJGPU *pGpu, NvU32 #endif //__nvoc_gpu_h_disabled NV_STATUS gpuAddClassToClassDBByClassId_IMPL(struct OBJGPU *pGpu, NvU32 arg0); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuAddClassToClassDBByClassId(struct OBJGPU *pGpu, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2751,6 +3121,7 @@ static inline NV_STATUS gpuAddClassToClassDBByClassId(struct OBJGPU *pGpu, NvU32 #endif //__nvoc_gpu_h_disabled NV_STATUS gpuAddClassToClassDBByEngTagClassId_IMPL(struct OBJGPU *pGpu, NvU32 arg0, NvU32 arg1); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuAddClassToClassDBByEngTagClassId(struct OBJGPU *pGpu, NvU32 arg0, NvU32 arg1) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2761,6 +3132,7 @@ static inline NV_STATUS gpuAddClassToClassDBByEngTagClassId(struct OBJGPU *pGpu, #endif //__nvoc_gpu_h_disabled NV_STATUS gpuDeleteClassFromClassDBByClassId_IMPL(struct OBJGPU *pGpu, NvU32 arg0); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuDeleteClassFromClassDBByClassId(struct OBJGPU *pGpu, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2771,6 +3143,7 @@ static inline NV_STATUS gpuDeleteClassFromClassDBByClassId(struct OBJGPU *pGpu, #endif //__nvoc_gpu_h_disabled NV_STATUS gpuDeleteClassFromClassDBByEngTag_IMPL(struct OBJGPU *pGpu, NvU32 arg0); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuDeleteClassFromClassDBByEngTag(struct OBJGPU *pGpu, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2781,6 +3154,7 @@ static inline NV_STATUS gpuDeleteClassFromClassDBByEngTag(struct OBJGPU *pGpu, N #endif //__nvoc_gpu_h_disabled NV_STATUS gpuDeleteClassFromClassDBByEngTagClassId_IMPL(struct OBJGPU *pGpu, NvU32 arg0, NvU32 arg1); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuDeleteClassFromClassDBByEngTagClassId(struct OBJGPU *pGpu, NvU32 arg0, NvU32 arg1) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2791,6 +3165,7 @@ static inline NV_STATUS gpuDeleteClassFromClassDBByEngTagClassId(struct OBJGPU * #endif //__nvoc_gpu_h_disabled NvBool gpuIsClassSupported_IMPL(struct OBJGPU *pGpu, NvU32 arg0); + #ifdef __nvoc_gpu_h_disabled static inline NvBool gpuIsClassSupported(struct OBJGPU *pGpu, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2801,6 +3176,7 @@ static inline NvBool gpuIsClassSupported(struct OBJGPU *pGpu, NvU32 arg0) { #endif //__nvoc_gpu_h_disabled NV_STATUS gpuGetClassByClassId_IMPL(struct OBJGPU *pGpu, NvU32 arg0, PCLASSDESCRIPTOR *arg1); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuGetClassByClassId(struct OBJGPU *pGpu, NvU32 arg0, PCLASSDESCRIPTOR *arg1) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2811,6 +3187,7 @@ static inline NV_STATUS gpuGetClassByClassId(struct OBJGPU *pGpu, NvU32 arg0, PC #endif //__nvoc_gpu_h_disabled NV_STATUS gpuGetClassByEngineAndClassId_IMPL(struct OBJGPU *pGpu, NvU32 arg0, NvU32 arg1, PCLASSDESCRIPTOR *arg2); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuGetClassByEngineAndClassId(struct OBJGPU *pGpu, NvU32 arg0, NvU32 arg1, PCLASSDESCRIPTOR *arg2) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2821,6 +3198,7 @@ static inline NV_STATUS gpuGetClassByEngineAndClassId(struct OBJGPU *pGpu, NvU32 #endif //__nvoc_gpu_h_disabled NV_STATUS gpuGetClassList_IMPL(struct OBJGPU *pGpu, NvU32 *arg0, NvU32 *arg1, NvU32 arg2); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuGetClassList(struct OBJGPU *pGpu, NvU32 *arg0, NvU32 *arg1, NvU32 arg2) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2831,6 +3209,7 @@ static inline NV_STATUS gpuGetClassList(struct OBJGPU *pGpu, NvU32 *arg0, NvU32 #endif //__nvoc_gpu_h_disabled NV_STATUS gpuConstructEngineTable_IMPL(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuConstructEngineTable(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2841,6 +3220,7 @@ static inline NV_STATUS gpuConstructEngineTable(struct OBJGPU *pGpu) { #endif //__nvoc_gpu_h_disabled void gpuDestroyEngineTable_IMPL(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline void gpuDestroyEngineTable(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2850,6 +3230,7 @@ static inline void gpuDestroyEngineTable(struct OBJGPU *pGpu) { #endif //__nvoc_gpu_h_disabled NV_STATUS gpuUpdateEngineTable_IMPL(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuUpdateEngineTable(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2859,9 +3240,10 @@ static inline NV_STATUS gpuUpdateEngineTable(struct OBJGPU *pGpu) { #define gpuUpdateEngineTable(pGpu) gpuUpdateEngineTable_IMPL(pGpu) #endif //__nvoc_gpu_h_disabled -NvBool gpuCheckEngineTable_IMPL(struct OBJGPU *pGpu, NvU32 arg0); +NvBool gpuCheckEngineTable_IMPL(struct OBJGPU *pGpu, RM_ENGINE_TYPE arg0); + #ifdef __nvoc_gpu_h_disabled -static inline NvBool gpuCheckEngineTable(struct OBJGPU *pGpu, NvU32 arg0) { +static inline NvBool gpuCheckEngineTable(struct OBJGPU *pGpu, RM_ENGINE_TYPE arg0) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); return NV_FALSE; } @@ -2869,9 +3251,10 @@ static inline NvBool gpuCheckEngineTable(struct OBJGPU *pGpu, NvU32 arg0) { #define gpuCheckEngineTable(pGpu, arg0) gpuCheckEngineTable_IMPL(pGpu, arg0) #endif //__nvoc_gpu_h_disabled -NV_STATUS gpuXlateEngDescToClientEngineId_IMPL(struct OBJGPU *pGpu, ENGDESCRIPTOR arg0, NvU32 *arg1); +NV_STATUS gpuXlateEngDescToClientEngineId_IMPL(struct OBJGPU *pGpu, ENGDESCRIPTOR arg0, RM_ENGINE_TYPE *arg1); + #ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuXlateEngDescToClientEngineId(struct OBJGPU *pGpu, ENGDESCRIPTOR arg0, NvU32 *arg1) { +static inline NV_STATUS gpuXlateEngDescToClientEngineId(struct OBJGPU *pGpu, ENGDESCRIPTOR arg0, RM_ENGINE_TYPE *arg1) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -2879,9 +3262,10 @@ static inline NV_STATUS gpuXlateEngDescToClientEngineId(struct OBJGPU *pGpu, ENG #define gpuXlateEngDescToClientEngineId(pGpu, arg0, arg1) gpuXlateEngDescToClientEngineId_IMPL(pGpu, arg0, arg1) #endif //__nvoc_gpu_h_disabled -NV_STATUS gpuXlateClientEngineIdToEngDesc_IMPL(struct OBJGPU *pGpu, NvU32 arg0, ENGDESCRIPTOR *arg1); +NV_STATUS gpuXlateClientEngineIdToEngDesc_IMPL(struct OBJGPU *pGpu, RM_ENGINE_TYPE arg0, ENGDESCRIPTOR *arg1); + #ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuXlateClientEngineIdToEngDesc(struct OBJGPU *pGpu, NvU32 arg0, ENGDESCRIPTOR *arg1) { +static inline NV_STATUS gpuXlateClientEngineIdToEngDesc(struct OBJGPU *pGpu, RM_ENGINE_TYPE arg0, ENGDESCRIPTOR *arg1) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -2889,9 +3273,10 @@ static inline NV_STATUS gpuXlateClientEngineIdToEngDesc(struct OBJGPU *pGpu, NvU #define gpuXlateClientEngineIdToEngDesc(pGpu, arg0, arg1) gpuXlateClientEngineIdToEngDesc_IMPL(pGpu, arg0, arg1) #endif //__nvoc_gpu_h_disabled -NV_STATUS gpuGetFlcnFromClientEngineId_IMPL(struct OBJGPU *pGpu, NvU32 arg0, struct Falcon **arg1); +NV_STATUS gpuGetFlcnFromClientEngineId_IMPL(struct OBJGPU *pGpu, RM_ENGINE_TYPE arg0, struct Falcon **arg1); + #ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuGetFlcnFromClientEngineId(struct OBJGPU *pGpu, NvU32 arg0, struct Falcon **arg1) { +static inline NV_STATUS gpuGetFlcnFromClientEngineId(struct OBJGPU *pGpu, RM_ENGINE_TYPE arg0, struct Falcon **arg1) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -2900,6 +3285,7 @@ static inline NV_STATUS gpuGetFlcnFromClientEngineId(struct OBJGPU *pGpu, NvU32 #endif //__nvoc_gpu_h_disabled NvBool gpuIsEngDescSupported_IMPL(struct OBJGPU *pGpu, NvU32 arg0); + #ifdef __nvoc_gpu_h_disabled static inline NvBool gpuIsEngDescSupported(struct OBJGPU *pGpu, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2910,6 +3296,7 @@ static inline NvBool gpuIsEngDescSupported(struct OBJGPU *pGpu, NvU32 arg0) { #endif //__nvoc_gpu_h_disabled NV_STATUS gpuReadBusConfigCycle_IMPL(struct OBJGPU *pGpu, NvU32 index, NvU32 *pData); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuReadBusConfigCycle(struct OBJGPU *pGpu, NvU32 index, NvU32 *pData) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2920,6 +3307,7 @@ static inline NV_STATUS gpuReadBusConfigCycle(struct OBJGPU *pGpu, NvU32 index, #endif //__nvoc_gpu_h_disabled NV_STATUS gpuWriteBusConfigCycle_IMPL(struct OBJGPU *pGpu, NvU32 index, NvU32 value); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuWriteBusConfigCycle(struct OBJGPU *pGpu, NvU32 index, NvU32 value) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2929,7 +3317,23 @@ static inline NV_STATUS gpuWriteBusConfigCycle(struct OBJGPU *pGpu, NvU32 index, #define gpuWriteBusConfigCycle(pGpu, index, value) gpuWriteBusConfigCycle_IMPL(pGpu, index, value) #endif //__nvoc_gpu_h_disabled +RM_ENGINE_TYPE gpuGetRmEngineType_IMPL(NvU32 index); + +#define gpuGetRmEngineType(index) gpuGetRmEngineType_IMPL(index) +void gpuGetRmEngineTypeList_IMPL(NvU32 *pNv2080EngineList, NvU32 engineCount, RM_ENGINE_TYPE *pRmEngineList); + +#define gpuGetRmEngineTypeList(pNv2080EngineList, engineCount, pRmEngineList) gpuGetRmEngineTypeList_IMPL(pNv2080EngineList, engineCount, pRmEngineList) +NvU32 gpuGetNv2080EngineType_IMPL(RM_ENGINE_TYPE index); + +#define gpuGetNv2080EngineType(index) gpuGetNv2080EngineType_IMPL(index) +void gpuGetNv2080EngineTypeList_IMPL(RM_ENGINE_TYPE *pRmEngineList, NvU32 engineCount, NvU32 *pNv2080EngineList); + +#define gpuGetNv2080EngineTypeList(pRmEngineList, engineCount, pNv2080EngineList) gpuGetNv2080EngineTypeList_IMPL(pRmEngineList, engineCount, pNv2080EngineList) +NV_STATUS gpuGetRmEngineTypeCapMask_IMPL(NvU32 *NV2080EngineTypeCap, NvU32 capSize, NvU32 *RmEngineTypeCap); + +#define gpuGetRmEngineTypeCapMask(NV2080EngineTypeCap, capSize, RmEngineTypeCap) gpuGetRmEngineTypeCapMask_IMPL(NV2080EngineTypeCap, capSize, RmEngineTypeCap) NvU32 gpuGetGpuMask_IMPL(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline NvU32 gpuGetGpuMask(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2940,6 +3344,7 @@ static inline NvU32 gpuGetGpuMask(struct OBJGPU *pGpu) { #endif //__nvoc_gpu_h_disabled void gpuChangeComputeModeRefCount_IMPL(struct OBJGPU *pGpu, NvU32 arg0); + #ifdef __nvoc_gpu_h_disabled static inline void gpuChangeComputeModeRefCount(struct OBJGPU *pGpu, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2949,6 +3354,7 @@ static inline void gpuChangeComputeModeRefCount(struct OBJGPU *pGpu, NvU32 arg0) #endif //__nvoc_gpu_h_disabled NV_STATUS gpuEnterShutdown_IMPL(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuEnterShutdown(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2959,6 +3365,7 @@ static inline NV_STATUS gpuEnterShutdown(struct OBJGPU *pGpu) { #endif //__nvoc_gpu_h_disabled NV_STATUS gpuSanityCheck_IMPL(struct OBJGPU *pGpu, NvU32 arg0, NvU32 *arg1); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuSanityCheck(struct OBJGPU *pGpu, NvU32 arg0, NvU32 *arg1) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2969,6 +3376,7 @@ static inline NV_STATUS gpuSanityCheck(struct OBJGPU *pGpu, NvU32 arg0, NvU32 *a #endif //__nvoc_gpu_h_disabled DEVICE_MAPPING *gpuGetDeviceMapping_IMPL(struct OBJGPU *pGpu, DEVICE_INDEX arg0, NvU32 arg1); + #ifdef __nvoc_gpu_h_disabled static inline DEVICE_MAPPING *gpuGetDeviceMapping(struct OBJGPU *pGpu, DEVICE_INDEX arg0, NvU32 arg1) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2979,6 +3387,7 @@ static inline DEVICE_MAPPING *gpuGetDeviceMapping(struct OBJGPU *pGpu, DEVICE_IN #endif //__nvoc_gpu_h_disabled DEVICE_MAPPING *gpuGetDeviceMappingFromDeviceID_IMPL(struct OBJGPU *pGpu, NvU32 arg0, NvU32 arg1); + #ifdef __nvoc_gpu_h_disabled static inline DEVICE_MAPPING *gpuGetDeviceMappingFromDeviceID(struct OBJGPU *pGpu, NvU32 arg0, NvU32 arg1) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2989,6 +3398,7 @@ static inline DEVICE_MAPPING *gpuGetDeviceMappingFromDeviceID(struct OBJGPU *pGp #endif //__nvoc_gpu_h_disabled NV_STATUS gpuGetGidInfo_IMPL(struct OBJGPU *pGpu, NvU8 **ppGidString, NvU32 *pGidStrlen, NvU32 gidFlags); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuGetGidInfo(struct OBJGPU *pGpu, NvU8 **ppGidString, NvU32 *pGidStrlen, NvU32 gidFlags) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -2999,6 +3409,7 @@ static inline NV_STATUS gpuGetGidInfo(struct OBJGPU *pGpu, NvU8 **ppGidString, N #endif //__nvoc_gpu_h_disabled void gpuSetThreadBcState_IMPL(struct OBJGPU *pGpu, NvBool arg0); + #ifdef __nvoc_gpu_h_disabled static inline void gpuSetThreadBcState(struct OBJGPU *pGpu, NvBool arg0) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -3008,6 +3419,7 @@ static inline void gpuSetThreadBcState(struct OBJGPU *pGpu, NvBool arg0) { #endif //__nvoc_gpu_h_disabled void gpuSetDisconnectedProperties_IMPL(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline void gpuSetDisconnectedProperties(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -3017,6 +3429,7 @@ static inline void gpuSetDisconnectedProperties(struct OBJGPU *pGpu) { #endif //__nvoc_gpu_h_disabled NV_STATUS gpuAddConstructedFalcon_IMPL(struct OBJGPU *pGpu, struct Falcon *arg0); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuAddConstructedFalcon(struct OBJGPU *pGpu, struct Falcon *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -3027,6 +3440,7 @@ static inline NV_STATUS gpuAddConstructedFalcon(struct OBJGPU *pGpu, struct Falc #endif //__nvoc_gpu_h_disabled NV_STATUS gpuRemoveConstructedFalcon_IMPL(struct OBJGPU *pGpu, struct Falcon *arg0); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuRemoveConstructedFalcon(struct OBJGPU *pGpu, struct Falcon *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -3037,6 +3451,7 @@ static inline NV_STATUS gpuRemoveConstructedFalcon(struct OBJGPU *pGpu, struct F #endif //__nvoc_gpu_h_disabled NV_STATUS gpuGetConstructedFalcon_IMPL(struct OBJGPU *pGpu, NvU32 arg0, struct Falcon **arg1); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuGetConstructedFalcon(struct OBJGPU *pGpu, NvU32 arg0, struct Falcon **arg1) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -3047,6 +3462,7 @@ static inline NV_STATUS gpuGetConstructedFalcon(struct OBJGPU *pGpu, NvU32 arg0, #endif //__nvoc_gpu_h_disabled NV_STATUS gpuGetSparseTextureComputeMode_IMPL(struct OBJGPU *pGpu, NvU32 *arg0, NvU32 *arg1, NvU32 *arg2); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuGetSparseTextureComputeMode(struct OBJGPU *pGpu, NvU32 *arg0, NvU32 *arg1, NvU32 *arg2) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -3057,6 +3473,7 @@ static inline NV_STATUS gpuGetSparseTextureComputeMode(struct OBJGPU *pGpu, NvU3 #endif //__nvoc_gpu_h_disabled NV_STATUS gpuSetSparseTextureComputeMode_IMPL(struct OBJGPU *pGpu, NvU32 arg0); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuSetSparseTextureComputeMode(struct OBJGPU *pGpu, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -3067,6 +3484,7 @@ static inline NV_STATUS gpuSetSparseTextureComputeMode(struct OBJGPU *pGpu, NvU3 #endif //__nvoc_gpu_h_disabled struct OBJENGSTATE *gpuGetEngstate_IMPL(struct OBJGPU *pGpu, ENGDESCRIPTOR arg0); + #ifdef __nvoc_gpu_h_disabled static inline struct OBJENGSTATE *gpuGetEngstate(struct OBJGPU *pGpu, ENGDESCRIPTOR arg0) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -3077,6 +3495,7 @@ static inline struct OBJENGSTATE *gpuGetEngstate(struct OBJGPU *pGpu, ENGDESCRIP #endif //__nvoc_gpu_h_disabled struct OBJENGSTATE *gpuGetEngstateNoShare_IMPL(struct OBJGPU *pGpu, ENGDESCRIPTOR arg0); + #ifdef __nvoc_gpu_h_disabled static inline struct OBJENGSTATE *gpuGetEngstateNoShare(struct OBJGPU *pGpu, ENGDESCRIPTOR arg0) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -3087,6 +3506,7 @@ static inline struct OBJENGSTATE *gpuGetEngstateNoShare(struct OBJGPU *pGpu, ENG #endif //__nvoc_gpu_h_disabled struct KernelFifo *gpuGetKernelFifoShared_IMPL(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline struct KernelFifo *gpuGetKernelFifoShared(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -3097,6 +3517,7 @@ static inline struct KernelFifo *gpuGetKernelFifoShared(struct OBJGPU *pGpu) { #endif //__nvoc_gpu_h_disabled NvBool gpuGetNextEngstate_IMPL(struct OBJGPU *pGpu, ENGSTATE_ITER *pIt, struct OBJENGSTATE **ppEngState); + #ifdef __nvoc_gpu_h_disabled static inline NvBool gpuGetNextEngstate(struct OBJGPU *pGpu, ENGSTATE_ITER *pIt, struct OBJENGSTATE **ppEngState) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -3106,17 +3527,8 @@ static inline NvBool gpuGetNextEngstate(struct OBJGPU *pGpu, ENGSTATE_ITER *pIt, #define gpuGetNextEngstate(pGpu, pIt, ppEngState) gpuGetNextEngstate_IMPL(pGpu, pIt, ppEngState) #endif //__nvoc_gpu_h_disabled -NvBool gpuGetNextStaticIntrable_IMPL(struct OBJGPU *pGpu, GPU_CHILD_ITER *pIt, struct OBJINTRABLE **ppIntrable); -#ifdef __nvoc_gpu_h_disabled -static inline NvBool gpuGetNextStaticIntrable(struct OBJGPU *pGpu, GPU_CHILD_ITER *pIt, struct OBJINTRABLE **ppIntrable) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_FALSE; -} -#else //__nvoc_gpu_h_disabled -#define gpuGetNextStaticIntrable(pGpu, pIt, ppIntrable) gpuGetNextStaticIntrable_IMPL(pGpu, pIt, ppIntrable) -#endif //__nvoc_gpu_h_disabled - struct OBJHOSTENG *gpuGetHosteng_IMPL(struct OBJGPU *pGpu, ENGDESCRIPTOR arg0); + #ifdef __nvoc_gpu_h_disabled static inline struct OBJHOSTENG *gpuGetHosteng(struct OBJGPU *pGpu, ENGDESCRIPTOR arg0) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -3127,6 +3539,7 @@ static inline struct OBJHOSTENG *gpuGetHosteng(struct OBJGPU *pGpu, ENGDESCRIPTO #endif //__nvoc_gpu_h_disabled NV_STATUS gpuConstructUserRegisterAccessMap_IMPL(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuConstructUserRegisterAccessMap(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -3137,6 +3550,7 @@ static inline NV_STATUS gpuConstructUserRegisterAccessMap(struct OBJGPU *pGpu) { #endif //__nvoc_gpu_h_disabled NV_STATUS gpuInitRegisterAccessMap_IMPL(struct OBJGPU *pGpu, NvU8 *arg0, NvU32 arg1, const NvU8 *arg2, const NvU32 arg3); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuInitRegisterAccessMap(struct OBJGPU *pGpu, NvU8 *arg0, NvU32 arg1, const NvU8 *arg2, const NvU32 arg3) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -3147,6 +3561,7 @@ static inline NV_STATUS gpuInitRegisterAccessMap(struct OBJGPU *pGpu, NvU8 *arg0 #endif //__nvoc_gpu_h_disabled NV_STATUS gpuSetUserRegisterAccessPermissions_IMPL(struct OBJGPU *pGpu, NvU32 offset, NvU32 size, NvBool bAllow); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuSetUserRegisterAccessPermissions(struct OBJGPU *pGpu, NvU32 offset, NvU32 size, NvBool bAllow) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -3157,6 +3572,7 @@ static inline NV_STATUS gpuSetUserRegisterAccessPermissions(struct OBJGPU *pGpu, #endif //__nvoc_gpu_h_disabled NV_STATUS gpuSetUserRegisterAccessPermissionsInBulk_IMPL(struct OBJGPU *pGpu, const NvU32 *regOffsetsAndSizesArr, NvU32 arrSizeBytes, NvBool bAllow); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuSetUserRegisterAccessPermissionsInBulk(struct OBJGPU *pGpu, const NvU32 *regOffsetsAndSizesArr, NvU32 arrSizeBytes, NvBool bAllow) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -3167,6 +3583,7 @@ static inline NV_STATUS gpuSetUserRegisterAccessPermissionsInBulk(struct OBJGPU #endif //__nvoc_gpu_h_disabled NvBool gpuGetUserRegisterAccessPermissions_IMPL(struct OBJGPU *pGpu, NvU32 offset); + #ifdef __nvoc_gpu_h_disabled static inline NvBool gpuGetUserRegisterAccessPermissions(struct OBJGPU *pGpu, NvU32 offset) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -3177,6 +3594,7 @@ static inline NvBool gpuGetUserRegisterAccessPermissions(struct OBJGPU *pGpu, Nv #endif //__nvoc_gpu_h_disabled void gpuDumpCallbackRegister_IMPL(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline void gpuDumpCallbackRegister(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -3185,17 +3603,19 @@ static inline void gpuDumpCallbackRegister(struct OBJGPU *pGpu) { #define gpuDumpCallbackRegister(pGpu) gpuDumpCallbackRegister_IMPL(pGpu) #endif //__nvoc_gpu_h_disabled -NV_STATUS gpuSanityCheckGfid_IMPL(struct OBJGPU *pGpu, NvU32 gfid, NvBool bInUse); +NV_STATUS gpuGetGfidState_IMPL(struct OBJGPU *pGpu, NvU32 gfid, GFID_ALLOC_STATUS *pState); + #ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuSanityCheckGfid(struct OBJGPU *pGpu, NvU32 gfid, NvBool bInUse) { +static inline NV_STATUS gpuGetGfidState(struct OBJGPU *pGpu, NvU32 gfid, GFID_ALLOC_STATUS *pState) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_gpu_h_disabled -#define gpuSanityCheckGfid(pGpu, gfid, bInUse) gpuSanityCheckGfid_IMPL(pGpu, gfid, bInUse) +#define gpuGetGfidState(pGpu, gfid, pState) gpuGetGfidState_IMPL(pGpu, gfid, pState) #endif //__nvoc_gpu_h_disabled void gpuSetGfidUsage_IMPL(struct OBJGPU *pGpu, NvU32 gfid, NvBool bInUse); + #ifdef __nvoc_gpu_h_disabled static inline void gpuSetGfidUsage(struct OBJGPU *pGpu, NvU32 gfid, NvBool bInUse) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -3204,7 +3624,18 @@ static inline void gpuSetGfidUsage(struct OBJGPU *pGpu, NvU32 gfid, NvBool bInUs #define gpuSetGfidUsage(pGpu, gfid, bInUse) gpuSetGfidUsage_IMPL(pGpu, gfid, bInUse) #endif //__nvoc_gpu_h_disabled +void gpuSetGfidInvalidated_IMPL(struct OBJGPU *pGpu, NvU32 gfid); + +#ifdef __nvoc_gpu_h_disabled +static inline void gpuSetGfidInvalidated(struct OBJGPU *pGpu, NvU32 gfid) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); +} +#else //__nvoc_gpu_h_disabled +#define gpuSetGfidInvalidated(pGpu, gfid) gpuSetGfidInvalidated_IMPL(pGpu, gfid) +#endif //__nvoc_gpu_h_disabled + NV_STATUS gpuSetExternalKernelClientCount_IMPL(struct OBJGPU *pGpu, NvBool bIncr); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuSetExternalKernelClientCount(struct OBJGPU *pGpu, NvBool bIncr) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -3215,6 +3646,7 @@ static inline NV_STATUS gpuSetExternalKernelClientCount(struct OBJGPU *pGpu, NvB #endif //__nvoc_gpu_h_disabled NvBool gpuIsInUse_IMPL(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline NvBool gpuIsInUse(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -3225,6 +3657,7 @@ static inline NvBool gpuIsInUse(struct OBJGPU *pGpu) { #endif //__nvoc_gpu_h_disabled NvU32 gpuGetUserClientCount_IMPL(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline NvU32 gpuGetUserClientCount(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -3235,6 +3668,7 @@ static inline NvU32 gpuGetUserClientCount(struct OBJGPU *pGpu) { #endif //__nvoc_gpu_h_disabled NvU32 gpuGetExternalClientCount_IMPL(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline NvU32 gpuGetExternalClientCount(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -3245,6 +3679,7 @@ static inline NvU32 gpuGetExternalClientCount(struct OBJGPU *pGpu) { #endif //__nvoc_gpu_h_disabled void gpuNotifySubDeviceEvent_IMPL(struct OBJGPU *pGpu, NvU32 notifyIndex, void *pNotifyParams, NvU32 notifyParamsSize, NvV32 info32, NvV16 info16); + #ifdef __nvoc_gpu_h_disabled static inline void gpuNotifySubDeviceEvent(struct OBJGPU *pGpu, NvU32 notifyIndex, void *pNotifyParams, NvU32 notifyParamsSize, NvV32 info32, NvV16 info16) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -3254,6 +3689,7 @@ static inline void gpuNotifySubDeviceEvent(struct OBJGPU *pGpu, NvU32 notifyInde #endif //__nvoc_gpu_h_disabled NV_STATUS gpuRegisterSubdevice_IMPL(struct OBJGPU *pGpu, struct Subdevice *pSubdevice); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuRegisterSubdevice(struct OBJGPU *pGpu, struct Subdevice *pSubdevice) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -3264,6 +3700,7 @@ static inline NV_STATUS gpuRegisterSubdevice(struct OBJGPU *pGpu, struct Subdevi #endif //__nvoc_gpu_h_disabled void gpuUnregisterSubdevice_IMPL(struct OBJGPU *pGpu, struct Subdevice *pSubdevice); + #ifdef __nvoc_gpu_h_disabled static inline void gpuUnregisterSubdevice(struct OBJGPU *pGpu, struct Subdevice *pSubdevice) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -3272,7 +3709,18 @@ static inline void gpuUnregisterSubdevice(struct OBJGPU *pGpu, struct Subdevice #define gpuUnregisterSubdevice(pGpu, pSubdevice) gpuUnregisterSubdevice_IMPL(pGpu, pSubdevice) #endif //__nvoc_gpu_h_disabled +void gpuGspPluginTriggeredEvent_IMPL(struct OBJGPU *pGpu, NvU32 gfid, NvU32 notifyIndex); + +#ifdef __nvoc_gpu_h_disabled +static inline void gpuGspPluginTriggeredEvent(struct OBJGPU *pGpu, NvU32 gfid, NvU32 notifyIndex) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); +} +#else //__nvoc_gpu_h_disabled +#define gpuGspPluginTriggeredEvent(pGpu, gfid, notifyIndex) gpuGspPluginTriggeredEvent_IMPL(pGpu, gfid, notifyIndex) +#endif //__nvoc_gpu_h_disabled + NV_STATUS gpuGetProcWithObject_IMPL(struct OBJGPU *pGpu, NvU32 elementID, NvU32 internalClassId, NvU32 *pPidArray, NvU32 *pPidArrayCount, MIG_INSTANCE_REF *pRef); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuGetProcWithObject(struct OBJGPU *pGpu, NvU32 elementID, NvU32 internalClassId, NvU32 *pPidArray, NvU32 *pPidArrayCount, MIG_INSTANCE_REF *pRef) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -3283,6 +3731,7 @@ static inline NV_STATUS gpuGetProcWithObject(struct OBJGPU *pGpu, NvU32 elementI #endif //__nvoc_gpu_h_disabled NV_STATUS gpuFindClientInfoWithPidIterator_IMPL(struct OBJGPU *pGpu, NvU32 pid, NvU32 subPid, NvU32 internalClassId, NV2080_CTRL_GPU_PID_INFO_DATA *pData, NV2080_CTRL_SMC_SUBSCRIPTION_INFO *pSmcInfo, MIG_INSTANCE_REF *pRef, NvBool bGlobalInfo); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuFindClientInfoWithPidIterator(struct OBJGPU *pGpu, NvU32 pid, NvU32 subPid, NvU32 internalClassId, NV2080_CTRL_GPU_PID_INFO_DATA *pData, NV2080_CTRL_SMC_SUBSCRIPTION_INFO *pSmcInfo, MIG_INSTANCE_REF *pRef, NvBool bGlobalInfo) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -3293,6 +3742,7 @@ static inline NV_STATUS gpuFindClientInfoWithPidIterator(struct OBJGPU *pGpu, Nv #endif //__nvoc_gpu_h_disabled NvBool gpuCheckSysmemAccess_IMPL(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline NvBool gpuCheckSysmemAccess(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -3303,6 +3753,7 @@ static inline NvBool gpuCheckSysmemAccess(struct OBJGPU *pGpu) { #endif //__nvoc_gpu_h_disabled void gpuInitChipInfo_IMPL(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled static inline void gpuInitChipInfo(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -3312,6 +3763,7 @@ static inline void gpuInitChipInfo(struct OBJGPU *pGpu) { #endif //__nvoc_gpu_h_disabled NV_STATUS gpuSanityCheckRegRead_IMPL(struct OBJGPU *pGpu, NvU32 addr, NvU32 size, void *pValue); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuSanityCheckRegRead(struct OBJGPU *pGpu, NvU32 addr, NvU32 size, void *pValue) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -3322,6 +3774,7 @@ static inline NV_STATUS gpuSanityCheckRegRead(struct OBJGPU *pGpu, NvU32 addr, N #endif //__nvoc_gpu_h_disabled NV_STATUS gpuSanityCheckRegisterAccess_IMPL(struct OBJGPU *pGpu, NvU32 addr, NvU32 *pRetVal); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuSanityCheckRegisterAccess(struct OBJGPU *pGpu, NvU32 addr, NvU32 *pRetVal) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -3332,6 +3785,7 @@ static inline NV_STATUS gpuSanityCheckRegisterAccess(struct OBJGPU *pGpu, NvU32 #endif //__nvoc_gpu_h_disabled NV_STATUS gpuValidateRegOffset_IMPL(struct OBJGPU *pGpu, NvU32 arg0); + #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuValidateRegOffset(struct OBJGPU *pGpu, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); @@ -3350,12 +3804,9 @@ NV_STATUS gpuGetByRef (RsResourceRef *pContextRef, NvBool *pbBroadcast, struct O // Look up pGpu associated with a hResource NV_STATUS gpuGetByHandle(struct RsClient *pClient, NvHandle hResource, NvBool *pbBroadcast, struct OBJGPU **ppGpu); -// Checks if an SR-IOV GFID is in use -#define GPU_IS_SRIOV_GFID_IN_USE(gfid) ((gpuSanityCheckGfid(pGpu, gfid, NV_TRUE) == NV_ERR_IN_USE) ? NV_TRUE : NV_FALSE) - #define GPU_GFID_PF (0) -#define IS_GFID_PF(gfid) ((gfid) == GPU_GFID_PF) -#define IS_GFID_VF(gfid) ((gfid) != GPU_GFID_PF) +#define IS_GFID_PF(gfid) (((NvU32)(gfid)) == GPU_GFID_PF) +#define IS_GFID_VF(gfid) (((NvU32)(gfid)) != GPU_GFID_PF) // Invalid P2P GFID #define INVALID_P2P_GFID (0xFFFFFFFF) @@ -3465,8 +3916,10 @@ static NvU32 gpuGetNumCEs(struct OBJGPU *pGpu) #define IS_SRIOV_HEAVY_GUEST(pGpu) NV_FALSE #define IS_SRIOV_FULL_GUEST(pGpu) NV_FALSE #define IS_SRIOV_HEAVY_HOST(pGpu) NV_FALSE -#define IS_SRIOV_FULL_HOST(pGpu) NV_FALSE -#define IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) NV_FALSE +#define IS_SRIOV_FULL_HOST(pGpu) ((hypervisorIsVgxHyper()) && gpuIsSriovEnabled(pGpu) && !IS_SRIOV_HEAVY(pGpu)) +#define IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) ((pGpu)->bVgpuGspPluginOffloadEnabled) +#define IS_SRIOV_WITH_VGPU_GSP_ENABLED(pGpu) (gpuIsSriovEnabled(pGpu) && IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && !IS_SRIOV_HEAVY(pGpu)) +#define IS_SRIOV_WITH_VGPU_GSP_DISABLED(pGpu) (gpuIsSriovEnabled(pGpu) && !IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && !IS_SRIOV_HEAVY(pGpu)) extern GPU_CHILD_ITER gpuGetPossibleEngDescriptorIter(void); extern NvBool gpuGetNextPossibleEngDescriptor(GPU_CHILD_ITER *pIt, ENGDESCRIPTOR *pEngDesc); @@ -3538,14 +3991,9 @@ NV_STATUS gpuValidateRegOps(struct OBJGPU *, NV2080_CTRL_GPU_REG_OP *, NvU32, Nv // Identifiers for gpuGetRegBaseOffset HAL interface. // #define NV_REG_BASE_GR (0x00000001) -#define NV_REG_BASE_PM (0x00000002) -#define NV_REG_BASE_TIMER (0x00000003) -#define NV_REG_BASE_DFD (0x00000004) -#define NV_REG_BASE_FLUSH (0x00000005) -#define NV_REG_BASE_LTCG (0x00000006) -#define NV_REG_BASE_TOP (0x00000007) -#define NV_REG_BASE_MASTER (0x0000000A) -#define NV_REG_BASE_USERMODE (0x0000000B) +#define NV_REG_BASE_TIMER (0x00000002) +#define NV_REG_BASE_MASTER (0x00000003) +#define NV_REG_BASE_USERMODE (0x00000004) #define NV_REG_BASE_LAST NV_REG_BASE_USERMODE ct_assert(NV_REG_BASE_LAST < NV2080_CTRL_INTERNAL_GET_CHIP_INFO_REG_BASE_MAX); @@ -3566,10 +4014,13 @@ ct_assert(NV_REG_BASE_LAST < NV2080_CTRL_INTERNAL_GET_CHIP_INFO_REG_BASE_MAX); #define gpuDeleteInfoBlock(pGpu, ppListHead, dataId) deleteInfoPtr(ppListHead, dataId); #define gpuTestInfoBlock(pGpu, pListHead, dataId) testInfoPtr(pListHead, dataId); +typedef struct _vgpu_static_info VGPU_STATIC_INFO; +typedef struct GspStaticConfigInfo_t GspStaticConfigInfo; + // Static info getters -void *gpuGetStaticInfo(struct OBJGPU *pGpu); +VGPU_STATIC_INFO *gpuGetStaticInfo(struct OBJGPU *pGpu); #define GPU_GET_STATIC_INFO(pGpu) gpuGetStaticInfo(pGpu) -void *gpuGetGspStaticInfo(struct OBJGPU *pGpu); +GspStaticConfigInfo *gpuGetGspStaticInfo(struct OBJGPU *pGpu); #define GPU_GET_GSP_STATIC_INFO(pGpu) gpuGetGspStaticInfo(pGpu) diff --git a/src/nvidia/generated/g_gpu_resource_nvoc.c b/src/nvidia/generated/g_gpu_resource_nvoc.c index 00b40f0cf..793cd55ce 100644 --- a/src/nvidia/generated/g_gpu_resource_nvoc.c +++ b/src/nvidia/generated/g_gpu_resource_nvoc.c @@ -144,6 +144,10 @@ static NV_STATUS __nvoc_thunk_RsResource_gpuresUnmapFrom(struct GpuResource *pRe return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_gpuresIsDuplicate(struct GpuResource *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_gpuresControl_Epilogue(struct GpuResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RmResource.offset), pCallContext, pParams); } @@ -240,6 +244,8 @@ static void __nvoc_init_funcTable_GpuResource_1(GpuResource *pThis) { pThis->__gpuresUnmapFrom__ = &__nvoc_thunk_RsResource_gpuresUnmapFrom; + pThis->__gpuresIsDuplicate__ = &__nvoc_thunk_RsResource_gpuresIsDuplicate; + pThis->__gpuresControl_Epilogue__ = &__nvoc_thunk_RmResource_gpuresControl_Epilogue; pThis->__gpuresControlLookup__ = &__nvoc_thunk_RsResource_gpuresControlLookup; diff --git a/src/nvidia/generated/g_gpu_resource_nvoc.h b/src/nvidia/generated/g_gpu_resource_nvoc.h index 80136153c..2c84005ac 100644 --- a/src/nvidia/generated/g_gpu_resource_nvoc.h +++ b/src/nvidia/generated/g_gpu_resource_nvoc.h @@ -120,6 +120,7 @@ struct GpuResource { NV_STATUS (*__gpuresMapTo__)(struct GpuResource *, RS_RES_MAP_TO_PARAMS *); void (*__gpuresPreDestruct__)(struct GpuResource *); NV_STATUS (*__gpuresUnmapFrom__)(struct GpuResource *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__gpuresIsDuplicate__)(struct GpuResource *, NvHandle, NvBool *); void (*__gpuresControl_Epilogue__)(struct GpuResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__gpuresControlLookup__)(struct GpuResource *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvBool (*__gpuresAccessCallback__)(struct GpuResource *, struct RsClient *, void *, RsAccessRight); @@ -177,6 +178,7 @@ NV_STATUS __nvoc_objCreate_GpuResource(GpuResource**, Dynamic*, NvU32, struct CA #define gpuresMapTo(pResource, pParams) gpuresMapTo_DISPATCH(pResource, pParams) #define gpuresPreDestruct(pResource) gpuresPreDestruct_DISPATCH(pResource) #define gpuresUnmapFrom(pResource, pParams) gpuresUnmapFrom_DISPATCH(pResource, pParams) +#define gpuresIsDuplicate(pResource, hMemory, pDuplicate) gpuresIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define gpuresControl_Epilogue(pResource, pCallContext, pParams) gpuresControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define gpuresControlLookup(pResource, pParams, ppEntry) gpuresControlLookup_DISPATCH(pResource, pParams, ppEntry) #define gpuresAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) gpuresAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) @@ -272,6 +274,10 @@ static inline NV_STATUS gpuresUnmapFrom_DISPATCH(struct GpuResource *pResource, return pResource->__gpuresUnmapFrom__(pResource, pParams); } +static inline NV_STATUS gpuresIsDuplicate_DISPATCH(struct GpuResource *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__gpuresIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void gpuresControl_Epilogue_DISPATCH(struct GpuResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__gpuresControl_Epilogue__(pResource, pCallContext, pParams); } @@ -285,8 +291,10 @@ static inline NvBool gpuresAccessCallback_DISPATCH(struct GpuResource *pResource } NV_STATUS gpuresConstruct_IMPL(struct GpuResource *arg_pGpuResource, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_gpuresConstruct(arg_pGpuResource, arg_pCallContext, arg_pParams) gpuresConstruct_IMPL(arg_pGpuResource, arg_pCallContext, arg_pParams) NV_STATUS gpuresCopyConstruct_IMPL(struct GpuResource *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); + #ifdef __nvoc_gpu_resource_h_disabled static inline NV_STATUS gpuresCopyConstruct(struct GpuResource *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { NV_ASSERT_FAILED_PRECOMP("GpuResource was disabled!"); @@ -297,6 +305,7 @@ static inline NV_STATUS gpuresCopyConstruct(struct GpuResource *pGpuResource, st #endif //__nvoc_gpu_resource_h_disabled void gpuresSetGpu_IMPL(struct GpuResource *pGpuResource, struct OBJGPU *pGpu, NvBool bBcResource); + #ifdef __nvoc_gpu_resource_h_disabled static inline void gpuresSetGpu(struct GpuResource *pGpuResource, struct OBJGPU *pGpu, NvBool bBcResource) { NV_ASSERT_FAILED_PRECOMP("GpuResource was disabled!"); @@ -306,6 +315,7 @@ static inline void gpuresSetGpu(struct GpuResource *pGpuResource, struct OBJGPU #endif //__nvoc_gpu_resource_h_disabled void gpuresControlSetup_IMPL(struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, struct GpuResource *pGpuResource); + #ifdef __nvoc_gpu_resource_h_disabled static inline void gpuresControlSetup(struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, struct GpuResource *pGpuResource) { NV_ASSERT_FAILED_PRECOMP("GpuResource was disabled!"); @@ -315,8 +325,10 @@ static inline void gpuresControlSetup(struct RS_RES_CONTROL_PARAMS_INTERNAL *pPa #endif //__nvoc_gpu_resource_h_disabled NV_STATUS gpuresGetByHandle_IMPL(struct RsClient *pClient, NvHandle hResource, struct GpuResource **ppGpuResource); + #define gpuresGetByHandle(pClient, hResource, ppGpuResource) gpuresGetByHandle_IMPL(pClient, hResource, ppGpuResource) NV_STATUS gpuresGetByDeviceOrSubdeviceHandle_IMPL(struct RsClient *pClient, NvHandle hResource, struct GpuResource **ppGpuResource); + #define gpuresGetByDeviceOrSubdeviceHandle(pClient, hResource, ppGpuResource) gpuresGetByDeviceOrSubdeviceHandle_IMPL(pClient, hResource, ppGpuResource) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_gpu_user_shared_data_nvoc.c b/src/nvidia/generated/g_gpu_user_shared_data_nvoc.c new file mode 100644 index 000000000..025788917 --- /dev/null +++ b/src/nvidia/generated/g_gpu_user_shared_data_nvoc.c @@ -0,0 +1,342 @@ +#define NVOC_GPU_USER_SHARED_DATA_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_gpu_user_shared_data_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0x5e7d1f = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_GpuUserSharedData; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RsResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResourceCommon; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_GpuResource; + +void __nvoc_init_GpuUserSharedData(GpuUserSharedData*); +void __nvoc_init_funcTable_GpuUserSharedData(GpuUserSharedData*); +NV_STATUS __nvoc_ctor_GpuUserSharedData(GpuUserSharedData*, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +void __nvoc_init_dataField_GpuUserSharedData(GpuUserSharedData*); +void __nvoc_dtor_GpuUserSharedData(GpuUserSharedData*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_GpuUserSharedData; + +static const struct NVOC_RTTI __nvoc_rtti_GpuUserSharedData_GpuUserSharedData = { + /*pClassDef=*/ &__nvoc_class_def_GpuUserSharedData, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_GpuUserSharedData, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_GpuUserSharedData_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(GpuUserSharedData, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_GpuUserSharedData_RsResource = { + /*pClassDef=*/ &__nvoc_class_def_RsResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(GpuUserSharedData, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_GpuUserSharedData_RmResourceCommon = { + /*pClassDef=*/ &__nvoc_class_def_RmResourceCommon, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(GpuUserSharedData, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon), +}; + +static const struct NVOC_RTTI __nvoc_rtti_GpuUserSharedData_RmResource = { + /*pClassDef=*/ &__nvoc_class_def_RmResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(GpuUserSharedData, __nvoc_base_GpuResource.__nvoc_base_RmResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_GpuUserSharedData_GpuResource = { + /*pClassDef=*/ &__nvoc_class_def_GpuResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(GpuUserSharedData, __nvoc_base_GpuResource), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_GpuUserSharedData = { + /*numRelatives=*/ 6, + /*relatives=*/ { + &__nvoc_rtti_GpuUserSharedData_GpuUserSharedData, + &__nvoc_rtti_GpuUserSharedData_GpuResource, + &__nvoc_rtti_GpuUserSharedData_RmResource, + &__nvoc_rtti_GpuUserSharedData_RmResourceCommon, + &__nvoc_rtti_GpuUserSharedData_RsResource, + &__nvoc_rtti_GpuUserSharedData_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_GpuUserSharedData = +{ + /*classInfo=*/ { + /*size=*/ sizeof(GpuUserSharedData), + /*classId=*/ classId(GpuUserSharedData), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "GpuUserSharedData", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_GpuUserSharedData, + /*pCastInfo=*/ &__nvoc_castinfo_GpuUserSharedData, + /*pExportInfo=*/ &__nvoc_export_info_GpuUserSharedData +}; + +static NV_STATUS __nvoc_thunk_GpuUserSharedData_gpuresMap(struct GpuResource *pData, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { + return gpushareddataMap((struct GpuUserSharedData *)(((unsigned char *)pData) - __nvoc_rtti_GpuUserSharedData_GpuResource.offset), pCallContext, pParams, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_GpuUserSharedData_gpuresUnmap(struct GpuResource *pData, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpushareddataUnmap((struct GpuUserSharedData *)(((unsigned char *)pData) - __nvoc_rtti_GpuUserSharedData_GpuResource.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_GpuUserSharedData_gpuresGetMapAddrSpace(struct GpuResource *pData, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpushareddataGetMapAddrSpace((struct GpuUserSharedData *)(((unsigned char *)pData) - __nvoc_rtti_GpuUserSharedData_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NV_STATUS __nvoc_thunk_GpuUserSharedData_rmresGetMemoryMappingDescriptor(struct RmResource *pData, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return gpushareddataGetMemoryMappingDescriptor((struct GpuUserSharedData *)(((unsigned char *)pData) - __nvoc_rtti_GpuUserSharedData_RmResource.offset), ppMemDesc); +} + +static NvBool __nvoc_thunk_GpuResource_gpushareddataShareCallback(struct GpuUserSharedData *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GpuUserSharedData_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_GpuResource_gpushareddataControl(struct GpuUserSharedData *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GpuUserSharedData_GpuResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_gpushareddataGetMemInterMapParams(struct GpuUserSharedData *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GpuUserSharedData_RmResource.offset), pParams); +} + +static NvHandle __nvoc_thunk_GpuResource_gpushareddataGetInternalObjectHandle(struct GpuUserSharedData *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GpuUserSharedData_GpuResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_gpushareddataControlFilter(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset), pCallContext, pParams); +} + +static void __nvoc_thunk_RsResource_gpushareddataAddAdditionalDependants(struct RsClient *pClient, struct GpuUserSharedData *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset), pReference); +} + +static NvU32 __nvoc_thunk_RsResource_gpushareddataGetRefCount(struct GpuUserSharedData *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RmResource_gpushareddataCheckMemInterUnmap(struct GpuUserSharedData *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GpuUserSharedData_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_gpushareddataMapTo(struct GpuUserSharedData *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_gpushareddataControl_Prologue(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_gpushareddataGetRegBaseOffsetAndSize(struct GpuUserSharedData *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GpuUserSharedData_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NvBool __nvoc_thunk_RsResource_gpushareddataCanCopy(struct GpuUserSharedData *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_gpushareddataInternalControlForward(struct GpuUserSharedData *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GpuUserSharedData_GpuResource.offset), command, pParams, size); +} + +static void __nvoc_thunk_RsResource_gpushareddataPreDestruct(struct GpuUserSharedData *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_gpushareddataUnmapFrom(struct GpuUserSharedData *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_gpushareddataIsDuplicate(struct GpuUserSharedData *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_gpushareddataControl_Epilogue(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_gpushareddataControlLookup(struct GpuUserSharedData *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset), pParams, ppEntry); +} + +static NvBool __nvoc_thunk_RmResource_gpushareddataAccessCallback(struct GpuUserSharedData *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RmResource.offset), pInvokingClient, pAllocParams, accessRight); +} + +const struct NVOC_EXPORT_INFO __nvoc_export_info_GpuUserSharedData = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_GpuResource(GpuResource*); +void __nvoc_dtor_GpuUserSharedData(GpuUserSharedData *pThis) { + __nvoc_gpushareddataDestruct(pThis); + __nvoc_dtor_GpuResource(&pThis->__nvoc_base_GpuResource); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_GpuUserSharedData(GpuUserSharedData *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_GpuResource(GpuResource* , struct CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); +NV_STATUS __nvoc_ctor_GpuUserSharedData(GpuUserSharedData *pThis, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_GpuResource(&pThis->__nvoc_base_GpuResource, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_GpuUserSharedData_fail_GpuResource; + __nvoc_init_dataField_GpuUserSharedData(pThis); + + status = __nvoc_gpushareddataConstruct(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_GpuUserSharedData_fail__init; + goto __nvoc_ctor_GpuUserSharedData_exit; // Success + +__nvoc_ctor_GpuUserSharedData_fail__init: + __nvoc_dtor_GpuResource(&pThis->__nvoc_base_GpuResource); +__nvoc_ctor_GpuUserSharedData_fail_GpuResource: +__nvoc_ctor_GpuUserSharedData_exit: + + return status; +} + +static void __nvoc_init_funcTable_GpuUserSharedData_1(GpuUserSharedData *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); + + pThis->__gpushareddataMap__ = &gpushareddataMap_IMPL; + + pThis->__gpushareddataUnmap__ = &gpushareddataUnmap_IMPL; + + pThis->__gpushareddataGetMapAddrSpace__ = &gpushareddataGetMapAddrSpace_IMPL; + + pThis->__gpushareddataGetMemoryMappingDescriptor__ = &gpushareddataGetMemoryMappingDescriptor_IMPL; + + pThis->__nvoc_base_GpuResource.__gpuresMap__ = &__nvoc_thunk_GpuUserSharedData_gpuresMap; + + pThis->__nvoc_base_GpuResource.__gpuresUnmap__ = &__nvoc_thunk_GpuUserSharedData_gpuresUnmap; + + pThis->__nvoc_base_GpuResource.__gpuresGetMapAddrSpace__ = &__nvoc_thunk_GpuUserSharedData_gpuresGetMapAddrSpace; + + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__rmresGetMemoryMappingDescriptor__ = &__nvoc_thunk_GpuUserSharedData_rmresGetMemoryMappingDescriptor; + + pThis->__gpushareddataShareCallback__ = &__nvoc_thunk_GpuResource_gpushareddataShareCallback; + + pThis->__gpushareddataControl__ = &__nvoc_thunk_GpuResource_gpushareddataControl; + + pThis->__gpushareddataGetMemInterMapParams__ = &__nvoc_thunk_RmResource_gpushareddataGetMemInterMapParams; + + pThis->__gpushareddataGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_gpushareddataGetInternalObjectHandle; + + pThis->__gpushareddataControlFilter__ = &__nvoc_thunk_RsResource_gpushareddataControlFilter; + + pThis->__gpushareddataAddAdditionalDependants__ = &__nvoc_thunk_RsResource_gpushareddataAddAdditionalDependants; + + pThis->__gpushareddataGetRefCount__ = &__nvoc_thunk_RsResource_gpushareddataGetRefCount; + + pThis->__gpushareddataCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_gpushareddataCheckMemInterUnmap; + + pThis->__gpushareddataMapTo__ = &__nvoc_thunk_RsResource_gpushareddataMapTo; + + pThis->__gpushareddataControl_Prologue__ = &__nvoc_thunk_RmResource_gpushareddataControl_Prologue; + + pThis->__gpushareddataGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_gpushareddataGetRegBaseOffsetAndSize; + + pThis->__gpushareddataCanCopy__ = &__nvoc_thunk_RsResource_gpushareddataCanCopy; + + pThis->__gpushareddataInternalControlForward__ = &__nvoc_thunk_GpuResource_gpushareddataInternalControlForward; + + pThis->__gpushareddataPreDestruct__ = &__nvoc_thunk_RsResource_gpushareddataPreDestruct; + + pThis->__gpushareddataUnmapFrom__ = &__nvoc_thunk_RsResource_gpushareddataUnmapFrom; + + pThis->__gpushareddataIsDuplicate__ = &__nvoc_thunk_RsResource_gpushareddataIsDuplicate; + + pThis->__gpushareddataControl_Epilogue__ = &__nvoc_thunk_RmResource_gpushareddataControl_Epilogue; + + pThis->__gpushareddataControlLookup__ = &__nvoc_thunk_RsResource_gpushareddataControlLookup; + + pThis->__gpushareddataAccessCallback__ = &__nvoc_thunk_RmResource_gpushareddataAccessCallback; +} + +void __nvoc_init_funcTable_GpuUserSharedData(GpuUserSharedData *pThis) { + __nvoc_init_funcTable_GpuUserSharedData_1(pThis); +} + +void __nvoc_init_GpuResource(GpuResource*); +void __nvoc_init_GpuUserSharedData(GpuUserSharedData *pThis) { + pThis->__nvoc_pbase_GpuUserSharedData = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; + pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource; + pThis->__nvoc_pbase_RmResourceCommon = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon; + pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource; + pThis->__nvoc_pbase_GpuResource = &pThis->__nvoc_base_GpuResource; + __nvoc_init_GpuResource(&pThis->__nvoc_base_GpuResource); + __nvoc_init_funcTable_GpuUserSharedData(pThis); +} + +NV_STATUS __nvoc_objCreate_GpuUserSharedData(GpuUserSharedData **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status; + Object *pParentObj; + GpuUserSharedData *pThis; + + pThis = portMemAllocNonPaged(sizeof(GpuUserSharedData)); + if (pThis == NULL) return NV_ERR_NO_MEMORY; + + portMemSet(pThis, 0, sizeof(GpuUserSharedData)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_GpuUserSharedData); + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_GpuUserSharedData(pThis); + status = __nvoc_ctor_GpuUserSharedData(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_objCreate_GpuUserSharedData_cleanup; + + *ppThis = pThis; + return NV_OK; + +__nvoc_objCreate_GpuUserSharedData_cleanup: + // do not call destructors here since the constructor already called them + portMemFree(pThis); + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_GpuUserSharedData(GpuUserSharedData **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + struct CALL_CONTEXT * arg_pCallContext = va_arg(args, struct CALL_CONTEXT *); + struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams = va_arg(args, struct RS_RES_ALLOC_PARAMS_INTERNAL *); + + status = __nvoc_objCreate_GpuUserSharedData(ppThis, pParent, createFlags, arg_pCallContext, arg_pParams); + + return status; +} + diff --git a/src/nvidia/generated/g_gpu_user_shared_data_nvoc.h b/src/nvidia/generated/g_gpu_user_shared_data_nvoc.h new file mode 100644 index 000000000..ca8a7c078 --- /dev/null +++ b/src/nvidia/generated/g_gpu_user_shared_data_nvoc.h @@ -0,0 +1,253 @@ +#ifndef _G_GPU_USER_SHARED_DATA_NVOC_H_ +#define _G_GPU_USER_SHARED_DATA_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_gpu_user_shared_data_nvoc.h" + +#ifndef GPU_USER_SHARED_DATA_H +#define GPU_USER_SHARED_DATA_H + +#include "core/core.h" +#include "gpu/gpu_resource.h" +#include "gpu/mem_mgr/mem_desc.h" + +// **************************************************************************** +// Type definitions +// **************************************************************************** + +/*! + * RM internal class representing RM_USER_SHARED_DATA + */ +#ifdef NVOC_GPU_USER_SHARED_DATA_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct GpuUserSharedData { + const struct NVOC_RTTI *__nvoc_rtti; + struct GpuResource __nvoc_base_GpuResource; + struct Object *__nvoc_pbase_Object; + struct RsResource *__nvoc_pbase_RsResource; + struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; + struct RmResource *__nvoc_pbase_RmResource; + struct GpuResource *__nvoc_pbase_GpuResource; + struct GpuUserSharedData *__nvoc_pbase_GpuUserSharedData; + NV_STATUS (*__gpushareddataMap__)(struct GpuUserSharedData *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); + NV_STATUS (*__gpushareddataUnmap__)(struct GpuUserSharedData *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__gpushareddataGetMapAddrSpace__)(struct GpuUserSharedData *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NV_STATUS (*__gpushareddataGetMemoryMappingDescriptor__)(struct GpuUserSharedData *, struct MEMORY_DESCRIPTOR **); + NvBool (*__gpushareddataShareCallback__)(struct GpuUserSharedData *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__gpushareddataControl__)(struct GpuUserSharedData *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__gpushareddataGetMemInterMapParams__)(struct GpuUserSharedData *, RMRES_MEM_INTER_MAP_PARAMS *); + NvHandle (*__gpushareddataGetInternalObjectHandle__)(struct GpuUserSharedData *); + NV_STATUS (*__gpushareddataControlFilter__)(struct GpuUserSharedData *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__gpushareddataAddAdditionalDependants__)(struct RsClient *, struct GpuUserSharedData *, RsResourceRef *); + NvU32 (*__gpushareddataGetRefCount__)(struct GpuUserSharedData *); + NV_STATUS (*__gpushareddataCheckMemInterUnmap__)(struct GpuUserSharedData *, NvBool); + NV_STATUS (*__gpushareddataMapTo__)(struct GpuUserSharedData *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__gpushareddataControl_Prologue__)(struct GpuUserSharedData *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__gpushareddataGetRegBaseOffsetAndSize__)(struct GpuUserSharedData *, struct OBJGPU *, NvU32 *, NvU32 *); + NvBool (*__gpushareddataCanCopy__)(struct GpuUserSharedData *); + NV_STATUS (*__gpushareddataInternalControlForward__)(struct GpuUserSharedData *, NvU32, void *, NvU32); + void (*__gpushareddataPreDestruct__)(struct GpuUserSharedData *); + NV_STATUS (*__gpushareddataUnmapFrom__)(struct GpuUserSharedData *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__gpushareddataIsDuplicate__)(struct GpuUserSharedData *, NvHandle, NvBool *); + void (*__gpushareddataControl_Epilogue__)(struct GpuUserSharedData *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__gpushareddataControlLookup__)(struct GpuUserSharedData *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvBool (*__gpushareddataAccessCallback__)(struct GpuUserSharedData *, struct RsClient *, void *, RsAccessRight); +}; + +#ifndef __NVOC_CLASS_GpuUserSharedData_TYPEDEF__ +#define __NVOC_CLASS_GpuUserSharedData_TYPEDEF__ +typedef struct GpuUserSharedData GpuUserSharedData; +#endif /* __NVOC_CLASS_GpuUserSharedData_TYPEDEF__ */ + +#ifndef __nvoc_class_id_GpuUserSharedData +#define __nvoc_class_id_GpuUserSharedData 0x5e7d1f +#endif /* __nvoc_class_id_GpuUserSharedData */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_GpuUserSharedData; + +#define __staticCast_GpuUserSharedData(pThis) \ + ((pThis)->__nvoc_pbase_GpuUserSharedData) + +#ifdef __nvoc_gpu_user_shared_data_h_disabled +#define __dynamicCast_GpuUserSharedData(pThis) ((GpuUserSharedData*)NULL) +#else //__nvoc_gpu_user_shared_data_h_disabled +#define __dynamicCast_GpuUserSharedData(pThis) \ + ((GpuUserSharedData*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(GpuUserSharedData))) +#endif //__nvoc_gpu_user_shared_data_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_GpuUserSharedData(GpuUserSharedData**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_GpuUserSharedData(GpuUserSharedData**, Dynamic*, NvU32, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +#define __objCreate_GpuUserSharedData(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ + __nvoc_objCreate_GpuUserSharedData((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) + +#define gpushareddataMap(pData, pCallContext, pParams, pCpuMapping) gpushareddataMap_DISPATCH(pData, pCallContext, pParams, pCpuMapping) +#define gpushareddataUnmap(pData, pCallContext, pCpuMapping) gpushareddataUnmap_DISPATCH(pData, pCallContext, pCpuMapping) +#define gpushareddataGetMapAddrSpace(pData, pCallContext, mapFlags, pAddrSpace) gpushareddataGetMapAddrSpace_DISPATCH(pData, pCallContext, mapFlags, pAddrSpace) +#define gpushareddataGetMemoryMappingDescriptor(pData, ppMemDesc) gpushareddataGetMemoryMappingDescriptor_DISPATCH(pData, ppMemDesc) +#define gpushareddataShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) gpushareddataShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define gpushareddataControl(pGpuResource, pCallContext, pParams) gpushareddataControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define gpushareddataGetMemInterMapParams(pRmResource, pParams) gpushareddataGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define gpushareddataGetInternalObjectHandle(pGpuResource) gpushareddataGetInternalObjectHandle_DISPATCH(pGpuResource) +#define gpushareddataControlFilter(pResource, pCallContext, pParams) gpushareddataControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define gpushareddataAddAdditionalDependants(pClient, pResource, pReference) gpushareddataAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define gpushareddataGetRefCount(pResource) gpushareddataGetRefCount_DISPATCH(pResource) +#define gpushareddataCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) gpushareddataCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define gpushareddataMapTo(pResource, pParams) gpushareddataMapTo_DISPATCH(pResource, pParams) +#define gpushareddataControl_Prologue(pResource, pCallContext, pParams) gpushareddataControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define gpushareddataGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) gpushareddataGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define gpushareddataCanCopy(pResource) gpushareddataCanCopy_DISPATCH(pResource) +#define gpushareddataInternalControlForward(pGpuResource, command, pParams, size) gpushareddataInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define gpushareddataPreDestruct(pResource) gpushareddataPreDestruct_DISPATCH(pResource) +#define gpushareddataUnmapFrom(pResource, pParams) gpushareddataUnmapFrom_DISPATCH(pResource, pParams) +#define gpushareddataIsDuplicate(pResource, hMemory, pDuplicate) gpushareddataIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define gpushareddataControl_Epilogue(pResource, pCallContext, pParams) gpushareddataControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define gpushareddataControlLookup(pResource, pParams, ppEntry) gpushareddataControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define gpushareddataAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) gpushareddataAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +NV_STATUS gpushareddataMap_IMPL(struct GpuUserSharedData *pData, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping); + +static inline NV_STATUS gpushareddataMap_DISPATCH(struct GpuUserSharedData *pData, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { + return pData->__gpushareddataMap__(pData, pCallContext, pParams, pCpuMapping); +} + +NV_STATUS gpushareddataUnmap_IMPL(struct GpuUserSharedData *pData, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping); + +static inline NV_STATUS gpushareddataUnmap_DISPATCH(struct GpuUserSharedData *pData, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pData->__gpushareddataUnmap__(pData, pCallContext, pCpuMapping); +} + +NV_STATUS gpushareddataGetMapAddrSpace_IMPL(struct GpuUserSharedData *pData, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace); + +static inline NV_STATUS gpushareddataGetMapAddrSpace_DISPATCH(struct GpuUserSharedData *pData, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pData->__gpushareddataGetMapAddrSpace__(pData, pCallContext, mapFlags, pAddrSpace); +} + +NV_STATUS gpushareddataGetMemoryMappingDescriptor_IMPL(struct GpuUserSharedData *pData, struct MEMORY_DESCRIPTOR **ppMemDesc); + +static inline NV_STATUS gpushareddataGetMemoryMappingDescriptor_DISPATCH(struct GpuUserSharedData *pData, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pData->__gpushareddataGetMemoryMappingDescriptor__(pData, ppMemDesc); +} + +static inline NvBool gpushareddataShareCallback_DISPATCH(struct GpuUserSharedData *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pGpuResource->__gpushareddataShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS gpushareddataControl_DISPATCH(struct GpuUserSharedData *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__gpushareddataControl__(pGpuResource, pCallContext, pParams); +} + +static inline NV_STATUS gpushareddataGetMemInterMapParams_DISPATCH(struct GpuUserSharedData *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__gpushareddataGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NvHandle gpushareddataGetInternalObjectHandle_DISPATCH(struct GpuUserSharedData *pGpuResource) { + return pGpuResource->__gpushareddataGetInternalObjectHandle__(pGpuResource); +} + +static inline NV_STATUS gpushareddataControlFilter_DISPATCH(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__gpushareddataControlFilter__(pResource, pCallContext, pParams); +} + +static inline void gpushareddataAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct GpuUserSharedData *pResource, RsResourceRef *pReference) { + pResource->__gpushareddataAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NvU32 gpushareddataGetRefCount_DISPATCH(struct GpuUserSharedData *pResource) { + return pResource->__gpushareddataGetRefCount__(pResource); +} + +static inline NV_STATUS gpushareddataCheckMemInterUnmap_DISPATCH(struct GpuUserSharedData *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__gpushareddataCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS gpushareddataMapTo_DISPATCH(struct GpuUserSharedData *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__gpushareddataMapTo__(pResource, pParams); +} + +static inline NV_STATUS gpushareddataControl_Prologue_DISPATCH(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__gpushareddataControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS gpushareddataGetRegBaseOffsetAndSize_DISPATCH(struct GpuUserSharedData *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__gpushareddataGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NvBool gpushareddataCanCopy_DISPATCH(struct GpuUserSharedData *pResource) { + return pResource->__gpushareddataCanCopy__(pResource); +} + +static inline NV_STATUS gpushareddataInternalControlForward_DISPATCH(struct GpuUserSharedData *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__gpushareddataInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline void gpushareddataPreDestruct_DISPATCH(struct GpuUserSharedData *pResource) { + pResource->__gpushareddataPreDestruct__(pResource); +} + +static inline NV_STATUS gpushareddataUnmapFrom_DISPATCH(struct GpuUserSharedData *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__gpushareddataUnmapFrom__(pResource, pParams); +} + +static inline NV_STATUS gpushareddataIsDuplicate_DISPATCH(struct GpuUserSharedData *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__gpushareddataIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void gpushareddataControl_Epilogue_DISPATCH(struct GpuUserSharedData *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__gpushareddataControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS gpushareddataControlLookup_DISPATCH(struct GpuUserSharedData *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__gpushareddataControlLookup__(pResource, pParams, ppEntry); +} + +static inline NvBool gpushareddataAccessCallback_DISPATCH(struct GpuUserSharedData *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return pResource->__gpushareddataAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); +} + +NV_STATUS gpushareddataConstruct_IMPL(struct GpuUserSharedData *arg_pData, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + +#define __nvoc_gpushareddataConstruct(arg_pData, arg_pCallContext, arg_pParams) gpushareddataConstruct_IMPL(arg_pData, arg_pCallContext, arg_pParams) +void gpushareddataDestruct_IMPL(struct GpuUserSharedData *pData); + +#define __nvoc_gpushareddataDestruct(pData) gpushareddataDestruct_IMPL(pData) +#undef PRIVATE_FIELD + + +#endif // GPU_USER_SHARED_DATA_H + + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_GPU_USER_SHARED_DATA_NVOC_H_ diff --git a/src/nvidia/generated/g_gpu_vaspace_nvoc.c b/src/nvidia/generated/g_gpu_vaspace_nvoc.c index 34dee63d3..b0a1d89ae 100644 --- a/src/nvidia/generated/g_gpu_vaspace_nvoc.c +++ b/src/nvidia/generated/g_gpu_vaspace_nvoc.c @@ -174,6 +174,10 @@ static NvBool __nvoc_thunk_OBJGVASPACE_vaspaceIsInternalVaRestricted(struct OBJV return gvaspaceIsInternalVaRestricted((struct OBJGVASPACE *)(((unsigned char *)pGVAS) - __nvoc_rtti_OBJGVASPACE_OBJVASPACE.offset)); } +static NV_STATUS __nvoc_thunk_OBJGVASPACE_vaspaceFreeV2(struct OBJVASPACE *pGVAS, NvU64 vAddr, NvU64 *pSize) { + return gvaspaceFreeV2((struct OBJGVASPACE *)(((unsigned char *)pGVAS) - __nvoc_rtti_OBJGVASPACE_OBJVASPACE.offset), vAddr, pSize); +} + static NvU64 __nvoc_thunk_OBJVASPACE_gvaspaceGetVaLimit(struct OBJGVASPACE *pVAS) { return vaspaceGetVaLimit((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_OBJGVASPACE_OBJVASPACE.offset)); } @@ -270,6 +274,8 @@ static void __nvoc_init_funcTable_OBJGVASPACE_1(OBJGVASPACE *pThis) { pThis->__gvaspaceIsInternalVaRestricted__ = &gvaspaceIsInternalVaRestricted_IMPL; + pThis->__gvaspaceFreeV2__ = &gvaspaceFreeV2_IMPL; + pThis->__nvoc_base_OBJVASPACE.__vaspaceConstruct___ = &__nvoc_thunk_OBJGVASPACE_vaspaceConstruct_; pThis->__nvoc_base_OBJVASPACE.__vaspaceReserveMempool__ = &__nvoc_thunk_OBJGVASPACE_vaspaceReserveMempool; @@ -324,6 +330,8 @@ static void __nvoc_init_funcTable_OBJGVASPACE_1(OBJGVASPACE *pThis) { pThis->__nvoc_base_OBJVASPACE.__vaspaceIsInternalVaRestricted__ = &__nvoc_thunk_OBJGVASPACE_vaspaceIsInternalVaRestricted; + pThis->__nvoc_base_OBJVASPACE.__vaspaceFreeV2__ = &__nvoc_thunk_OBJGVASPACE_vaspaceFreeV2; + pThis->__gvaspaceGetVaLimit__ = &__nvoc_thunk_OBJVASPACE_gvaspaceGetVaLimit; pThis->__gvaspaceGetVaStart__ = &__nvoc_thunk_OBJVASPACE_gvaspaceGetVaStart; diff --git a/src/nvidia/generated/g_gpu_vaspace_nvoc.h b/src/nvidia/generated/g_gpu_vaspace_nvoc.h index e5b2ff300..9107e32d0 100644 --- a/src/nvidia/generated/g_gpu_vaspace_nvoc.h +++ b/src/nvidia/generated/g_gpu_vaspace_nvoc.h @@ -245,6 +245,7 @@ struct OBJGVASPACE { NV_STATUS (*__gvaspaceGetPteInfo__)(struct OBJGVASPACE *, struct OBJGPU *, NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS *, RmPhysAddr *); NV_STATUS (*__gvaspaceSetPteInfo__)(struct OBJGVASPACE *, struct OBJGPU *, NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS *); NvBool (*__gvaspaceIsInternalVaRestricted__)(struct OBJGVASPACE *); + NV_STATUS (*__gvaspaceFreeV2__)(struct OBJGVASPACE *, NvU64, NvU64 *); NvU64 (*__gvaspaceGetVaLimit__)(struct OBJGVASPACE *); NvU64 (*__gvaspaceGetVaStart__)(struct OBJGVASPACE *); struct OBJEHEAP *pHeap; @@ -328,6 +329,7 @@ NV_STATUS __nvoc_objCreate_OBJGVASPACE(OBJGVASPACE**, Dynamic*, NvU32); #define gvaspaceGetPteInfo(pVAS, pGpu, pParams, pPhysAddr) gvaspaceGetPteInfo_DISPATCH(pVAS, pGpu, pParams, pPhysAddr) #define gvaspaceSetPteInfo(pVAS, pGpu, pParams) gvaspaceSetPteInfo_DISPATCH(pVAS, pGpu, pParams) #define gvaspaceIsInternalVaRestricted(pGVAS) gvaspaceIsInternalVaRestricted_DISPATCH(pGVAS) +#define gvaspaceFreeV2(pGVAS, vAddr, pSize) gvaspaceFreeV2_DISPATCH(pGVAS, vAddr, pSize) #define gvaspaceGetVaLimit(pVAS) gvaspaceGetVaLimit_DISPATCH(pVAS) #define gvaspaceGetVaStart(pVAS) gvaspaceGetVaStart_DISPATCH(pVAS) NV_STATUS gvaspaceConstruct__IMPL(struct OBJGVASPACE *pGVAS, NvU32 classId, NvU32 vaspaceId, NvU64 vaStart, NvU64 vaLimit, NvU64 vaStartInternal, NvU64 vaLimitInternal, NvU32 flags); @@ -492,6 +494,12 @@ static inline NvBool gvaspaceIsInternalVaRestricted_DISPATCH(struct OBJGVASPACE return pGVAS->__gvaspaceIsInternalVaRestricted__(pGVAS); } +NV_STATUS gvaspaceFreeV2_IMPL(struct OBJGVASPACE *pGVAS, NvU64 vAddr, NvU64 *pSize); + +static inline NV_STATUS gvaspaceFreeV2_DISPATCH(struct OBJGVASPACE *pGVAS, NvU64 vAddr, NvU64 *pSize) { + return pGVAS->__gvaspaceFreeV2__(pGVAS, vAddr, pSize); +} + static inline NvU64 gvaspaceGetVaLimit_DISPATCH(struct OBJGVASPACE *pVAS) { return pVAS->__gvaspaceGetVaLimit__(pVAS); } @@ -508,8 +516,10 @@ static inline NvU32 gvaspaceGetReservedVaspaceBase(struct OBJGVASPACE *pGVAS, st } void gvaspaceDestruct_IMPL(struct OBJGVASPACE *pGVAS); + #define __nvoc_gvaspaceDestruct(pGVAS) gvaspaceDestruct_IMPL(pGVAS) NV_STATUS gvaspaceExternalRootDirCommit_IMPL(struct OBJGVASPACE *pGVAS, NvHandle hClient, struct OBJGPU *pGpu, NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS *pParams); + #ifdef __nvoc_gpu_vaspace_h_disabled static inline NV_STATUS gvaspaceExternalRootDirCommit(struct OBJGVASPACE *pGVAS, NvHandle hClient, struct OBJGPU *pGpu, NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS *pParams) { NV_ASSERT_FAILED_PRECOMP("OBJGVASPACE was disabled!"); @@ -520,6 +530,7 @@ static inline NV_STATUS gvaspaceExternalRootDirCommit(struct OBJGVASPACE *pGVAS, #endif //__nvoc_gpu_vaspace_h_disabled NV_STATUS gvaspaceExternalRootDirRevoke_IMPL(struct OBJGVASPACE *pGVAS, struct OBJGPU *pGpu, NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS *pParams); + #ifdef __nvoc_gpu_vaspace_h_disabled static inline NV_STATUS gvaspaceExternalRootDirRevoke(struct OBJGVASPACE *pGVAS, struct OBJGPU *pGpu, NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS *pParams) { NV_ASSERT_FAILED_PRECOMP("OBJGVASPACE was disabled!"); @@ -530,6 +541,7 @@ static inline NV_STATUS gvaspaceExternalRootDirRevoke(struct OBJGVASPACE *pGVAS, #endif //__nvoc_gpu_vaspace_h_disabled NV_STATUS gvaspaceResize_IMPL(struct OBJGVASPACE *pGVAS, NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS *pParams); + #ifdef __nvoc_gpu_vaspace_h_disabled static inline NV_STATUS gvaspaceResize(struct OBJGVASPACE *pGVAS, NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS *pParams) { NV_ASSERT_FAILED_PRECOMP("OBJGVASPACE was disabled!"); @@ -540,6 +552,7 @@ static inline NV_STATUS gvaspaceResize(struct OBJGVASPACE *pGVAS, NV0080_CTRL_DM #endif //__nvoc_gpu_vaspace_h_disabled NV_STATUS gvaspaceUpdatePde2_IMPL(struct OBJGVASPACE *pGVAS, struct OBJGPU *pGpu, NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *pParams); + #ifdef __nvoc_gpu_vaspace_h_disabled static inline NV_STATUS gvaspaceUpdatePde2(struct OBJGVASPACE *pGVAS, struct OBJGPU *pGpu, NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS *pParams) { NV_ASSERT_FAILED_PRECOMP("OBJGVASPACE was disabled!"); @@ -550,6 +563,7 @@ static inline NV_STATUS gvaspaceUpdatePde2(struct OBJGVASPACE *pGVAS, struct OBJ #endif //__nvoc_gpu_vaspace_h_disabled const struct GMMU_FMT *gvaspaceGetGmmuFmt_IMPL(struct OBJGVASPACE *pGVAS, struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_vaspace_h_disabled static inline const struct GMMU_FMT *gvaspaceGetGmmuFmt(struct OBJGVASPACE *pGVAS, struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGVASPACE was disabled!"); @@ -560,6 +574,7 @@ static inline const struct GMMU_FMT *gvaspaceGetGmmuFmt(struct OBJGVASPACE *pGVA #endif //__nvoc_gpu_vaspace_h_disabled GVAS_GPU_STATE *gvaspaceGetGpuState_IMPL(struct OBJGVASPACE *pGVAS, struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_vaspace_h_disabled static inline GVAS_GPU_STATE *gvaspaceGetGpuState(struct OBJGVASPACE *pGVAS, struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGVASPACE was disabled!"); @@ -570,6 +585,7 @@ static inline GVAS_GPU_STATE *gvaspaceGetGpuState(struct OBJGVASPACE *pGVAS, str #endif //__nvoc_gpu_vaspace_h_disabled void gvaspaceWalkUserCtxAcquire_IMPL(struct OBJGVASPACE *pGVAS, struct OBJGPU *pGpu, const GVAS_BLOCK *pVASBlock, struct MMU_WALK_USER_CTX *pUserCtx); + #ifdef __nvoc_gpu_vaspace_h_disabled static inline void gvaspaceWalkUserCtxAcquire(struct OBJGVASPACE *pGVAS, struct OBJGPU *pGpu, const GVAS_BLOCK *pVASBlock, struct MMU_WALK_USER_CTX *pUserCtx) { NV_ASSERT_FAILED_PRECOMP("OBJGVASPACE was disabled!"); @@ -579,6 +595,7 @@ static inline void gvaspaceWalkUserCtxAcquire(struct OBJGVASPACE *pGVAS, struct #endif //__nvoc_gpu_vaspace_h_disabled void gvaspaceWalkUserCtxRelease_IMPL(struct OBJGVASPACE *pGVAS, struct MMU_WALK_USER_CTX *pUserCtx); + #ifdef __nvoc_gpu_vaspace_h_disabled static inline void gvaspaceWalkUserCtxRelease(struct OBJGVASPACE *pGVAS, struct MMU_WALK_USER_CTX *pUserCtx) { NV_ASSERT_FAILED_PRECOMP("OBJGVASPACE was disabled!"); @@ -588,6 +605,7 @@ static inline void gvaspaceWalkUserCtxRelease(struct OBJGVASPACE *pGVAS, struct #endif //__nvoc_gpu_vaspace_h_disabled NV_STATUS gvaspaceIncChanGrpRefCnt_IMPL(struct OBJGVASPACE *pGVAS, KernelChannelGroup *pKernelChannelGroup); + #ifdef __nvoc_gpu_vaspace_h_disabled static inline NV_STATUS gvaspaceIncChanGrpRefCnt(struct OBJGVASPACE *pGVAS, KernelChannelGroup *pKernelChannelGroup) { NV_ASSERT_FAILED_PRECOMP("OBJGVASPACE was disabled!"); @@ -598,6 +616,7 @@ static inline NV_STATUS gvaspaceIncChanGrpRefCnt(struct OBJGVASPACE *pGVAS, Kern #endif //__nvoc_gpu_vaspace_h_disabled NV_STATUS gvaspaceDecChanGrpRefCnt_IMPL(struct OBJGVASPACE *pGVAS, KernelChannelGroup *pKernelChannelGroup); + #ifdef __nvoc_gpu_vaspace_h_disabled static inline NV_STATUS gvaspaceDecChanGrpRefCnt(struct OBJGVASPACE *pGVAS, KernelChannelGroup *pKernelChannelGroup) { NV_ASSERT_FAILED_PRECOMP("OBJGVASPACE was disabled!"); @@ -608,6 +627,7 @@ static inline NV_STATUS gvaspaceDecChanGrpRefCnt(struct OBJGVASPACE *pGVAS, Kern #endif //__nvoc_gpu_vaspace_h_disabled NvU32 gvaspaceGetChanGrpRefCnt_IMPL(struct OBJGVASPACE *pGVAS, KernelChannelGroup *pKernelChannelGroup); + #ifdef __nvoc_gpu_vaspace_h_disabled static inline NvU32 gvaspaceGetChanGrpRefCnt(struct OBJGVASPACE *pGVAS, KernelChannelGroup *pKernelChannelGroup) { NV_ASSERT_FAILED_PRECOMP("OBJGVASPACE was disabled!"); @@ -618,6 +638,7 @@ static inline NvU32 gvaspaceGetChanGrpRefCnt(struct OBJGVASPACE *pGVAS, KernelCh #endif //__nvoc_gpu_vaspace_h_disabled NV_STATUS gvaspaceCheckChanGrpRefCnt_IMPL(struct OBJGVASPACE *pGVAS, KernelChannelGroup *pKernelChannelGroup); + #ifdef __nvoc_gpu_vaspace_h_disabled static inline NV_STATUS gvaspaceCheckChanGrpRefCnt(struct OBJGVASPACE *pGVAS, KernelChannelGroup *pKernelChannelGroup) { NV_ASSERT_FAILED_PRECOMP("OBJGVASPACE was disabled!"); @@ -628,6 +649,7 @@ static inline NV_STATUS gvaspaceCheckChanGrpRefCnt(struct OBJGVASPACE *pGVAS, Ke #endif //__nvoc_gpu_vaspace_h_disabled NV_STATUS gvaspaceUnregisterAllChanGrps_IMPL(struct OBJGVASPACE *pGVAS, struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_vaspace_h_disabled static inline NV_STATUS gvaspaceUnregisterAllChanGrps(struct OBJGVASPACE *pGVAS, struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGVASPACE was disabled!"); @@ -638,6 +660,7 @@ static inline NV_STATUS gvaspaceUnregisterAllChanGrps(struct OBJGVASPACE *pGVAS, #endif //__nvoc_gpu_vaspace_h_disabled NV_STATUS gvaspaceReservePageTableEntries_IMPL(struct OBJGVASPACE *pGVAS, struct OBJGPU *pGpu, const NvU64 vaLo, const NvU64 vaHi, const NvU64 pageSizeMask); + #ifdef __nvoc_gpu_vaspace_h_disabled static inline NV_STATUS gvaspaceReservePageTableEntries(struct OBJGVASPACE *pGVAS, struct OBJGPU *pGpu, const NvU64 vaLo, const NvU64 vaHi, const NvU64 pageSizeMask) { NV_ASSERT_FAILED_PRECOMP("OBJGVASPACE was disabled!"); @@ -648,6 +671,7 @@ static inline NV_STATUS gvaspaceReservePageTableEntries(struct OBJGVASPACE *pGVA #endif //__nvoc_gpu_vaspace_h_disabled NV_STATUS gvaspaceReleasePageTableEntries_IMPL(struct OBJGVASPACE *pGVAS, struct OBJGPU *pGpu, const NvU64 vaLo, const NvU64 vaHi, const NvU64 pageSizeMask); + #ifdef __nvoc_gpu_vaspace_h_disabled static inline NV_STATUS gvaspaceReleasePageTableEntries(struct OBJGVASPACE *pGVAS, struct OBJGPU *pGpu, const NvU64 vaLo, const NvU64 vaHi, const NvU64 pageSizeMask) { NV_ASSERT_FAILED_PRECOMP("OBJGVASPACE was disabled!"); @@ -658,6 +682,7 @@ static inline NV_STATUS gvaspaceReleasePageTableEntries(struct OBJGVASPACE *pGVA #endif //__nvoc_gpu_vaspace_h_disabled NV_STATUS gvaspaceGetPageLevelInfo_IMPL(struct OBJGVASPACE *pGVAS, struct OBJGPU *pGpu, NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS *pParams); + #ifdef __nvoc_gpu_vaspace_h_disabled static inline NV_STATUS gvaspaceGetPageLevelInfo(struct OBJGVASPACE *pGVAS, struct OBJGPU *pGpu, NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS *pParams) { NV_ASSERT_FAILED_PRECOMP("OBJGVASPACE was disabled!"); @@ -668,6 +693,7 @@ static inline NV_STATUS gvaspaceGetPageLevelInfo(struct OBJGVASPACE *pGVAS, stru #endif //__nvoc_gpu_vaspace_h_disabled NV_STATUS gvaspaceCopyServerRmReservedPdesToServerRm_IMPL(struct OBJGVASPACE *pGVAS, struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_vaspace_h_disabled static inline NV_STATUS gvaspaceCopyServerRmReservedPdesToServerRm(struct OBJGVASPACE *pGVAS, struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGVASPACE was disabled!"); @@ -678,6 +704,7 @@ static inline NV_STATUS gvaspaceCopyServerRmReservedPdesToServerRm(struct OBJGVA #endif //__nvoc_gpu_vaspace_h_disabled NV_STATUS gvaspaceGetFreeHeap_IMPL(struct OBJGVASPACE *pGVAS, NvU64 *pFreeSize); + #ifdef __nvoc_gpu_vaspace_h_disabled static inline NV_STATUS gvaspaceGetFreeHeap(struct OBJGVASPACE *pGVAS, NvU64 *pFreeSize) { NV_ASSERT_FAILED_PRECOMP("OBJGVASPACE was disabled!"); @@ -688,6 +715,7 @@ static inline NV_STATUS gvaspaceGetFreeHeap(struct OBJGVASPACE *pGVAS, NvU64 *pF #endif //__nvoc_gpu_vaspace_h_disabled NvBool gvaspaceIsInUse_IMPL(struct OBJGVASPACE *pGVAS); + #ifdef __nvoc_gpu_vaspace_h_disabled static inline NvBool gvaspaceIsInUse(struct OBJGVASPACE *pGVAS) { NV_ASSERT_FAILED_PRECOMP("OBJGVASPACE was disabled!"); @@ -697,6 +725,28 @@ static inline NvBool gvaspaceIsInUse(struct OBJGVASPACE *pGVAS) { #define gvaspaceIsInUse(pGVAS) gvaspaceIsInUse_IMPL(pGVAS) #endif //__nvoc_gpu_vaspace_h_disabled +NV_STATUS gvaspaceReserveSplitVaSpace_IMPL(struct OBJGVASPACE *pGVAS, struct OBJGPU *pGpu); + +#ifdef __nvoc_gpu_vaspace_h_disabled +static inline NV_STATUS gvaspaceReserveSplitVaSpace(struct OBJGVASPACE *pGVAS, struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGVASPACE was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_vaspace_h_disabled +#define gvaspaceReserveSplitVaSpace(pGVAS, pGpu) gvaspaceReserveSplitVaSpace_IMPL(pGVAS, pGpu) +#endif //__nvoc_gpu_vaspace_h_disabled + +NV_STATUS gvaspaceCopyServerReservedPdes_IMPL(struct OBJGVASPACE *pGVAS, struct OBJGPU *pGpu, NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS *pCopyServerReservedPdesParams); + +#ifdef __nvoc_gpu_vaspace_h_disabled +static inline NV_STATUS gvaspaceCopyServerReservedPdes(struct OBJGVASPACE *pGVAS, struct OBJGPU *pGpu, NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS *pCopyServerReservedPdesParams) { + NV_ASSERT_FAILED_PRECOMP("OBJGVASPACE was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_vaspace_h_disabled +#define gvaspaceCopyServerReservedPdes(pGVAS, pGpu, pCopyServerReservedPdesParams) gvaspaceCopyServerReservedPdes_IMPL(pGVAS, pGpu, pCopyServerReservedPdesParams) +#endif //__nvoc_gpu_vaspace_h_disabled + #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_gsync_api_nvoc.c b/src/nvidia/generated/g_gsync_api_nvoc.c new file mode 100644 index 000000000..2e8a80031 --- /dev/null +++ b/src/nvidia/generated/g_gsync_api_nvoc.c @@ -0,0 +1,920 @@ +#define NVOC_GSYNC_API_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_gsync_api_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0x214628 = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_GSyncApi; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RsResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResourceCommon; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_INotifier; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Notifier; + +void __nvoc_init_GSyncApi(GSyncApi*); +void __nvoc_init_funcTable_GSyncApi(GSyncApi*); +NV_STATUS __nvoc_ctor_GSyncApi(GSyncApi*, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +void __nvoc_init_dataField_GSyncApi(GSyncApi*); +void __nvoc_dtor_GSyncApi(GSyncApi*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_GSyncApi; + +static const struct NVOC_RTTI __nvoc_rtti_GSyncApi_GSyncApi = { + /*pClassDef=*/ &__nvoc_class_def_GSyncApi, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_GSyncApi, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_GSyncApi_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(GSyncApi, __nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_GSyncApi_RsResource = { + /*pClassDef=*/ &__nvoc_class_def_RsResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(GSyncApi, __nvoc_base_RmResource.__nvoc_base_RsResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_GSyncApi_RmResourceCommon = { + /*pClassDef=*/ &__nvoc_class_def_RmResourceCommon, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(GSyncApi, __nvoc_base_RmResource.__nvoc_base_RmResourceCommon), +}; + +static const struct NVOC_RTTI __nvoc_rtti_GSyncApi_RmResource = { + /*pClassDef=*/ &__nvoc_class_def_RmResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(GSyncApi, __nvoc_base_RmResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_GSyncApi_INotifier = { + /*pClassDef=*/ &__nvoc_class_def_INotifier, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(GSyncApi, __nvoc_base_Notifier.__nvoc_base_INotifier), +}; + +static const struct NVOC_RTTI __nvoc_rtti_GSyncApi_Notifier = { + /*pClassDef=*/ &__nvoc_class_def_Notifier, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(GSyncApi, __nvoc_base_Notifier), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_GSyncApi = { + /*numRelatives=*/ 7, + /*relatives=*/ { + &__nvoc_rtti_GSyncApi_GSyncApi, + &__nvoc_rtti_GSyncApi_Notifier, + &__nvoc_rtti_GSyncApi_INotifier, + &__nvoc_rtti_GSyncApi_RmResource, + &__nvoc_rtti_GSyncApi_RmResourceCommon, + &__nvoc_rtti_GSyncApi_RsResource, + &__nvoc_rtti_GSyncApi_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_GSyncApi = +{ + /*classInfo=*/ { + /*size=*/ sizeof(GSyncApi), + /*classId=*/ classId(GSyncApi), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "GSyncApi", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_GSyncApi, + /*pCastInfo=*/ &__nvoc_castinfo_GSyncApi, + /*pExportInfo=*/ &__nvoc_export_info_GSyncApi +}; + +static NV_STATUS __nvoc_thunk_GSyncApi_resControl(struct RsResource *pGsyncApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gsyncapiControl((struct GSyncApi *)(((unsigned char *)pGsyncApi) - __nvoc_rtti_GSyncApi_RsResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_RmResource_gsyncapiShareCallback(struct GSyncApi *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RmResource_gsyncapiCheckMemInterUnmap(struct GSyncApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GSyncApi_RmResource.offset), bSubdeviceHandleProvided); +} + +static NvBool __nvoc_thunk_RmResource_gsyncapiAccessCallback(struct GSyncApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RmResource.offset), pInvokingClient, pAllocParams, accessRight); +} + +static NV_STATUS __nvoc_thunk_RmResource_gsyncapiGetMemInterMapParams(struct GSyncApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GSyncApi_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_gsyncapiGetMemoryMappingDescriptor(struct GSyncApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_GSyncApi_RmResource.offset), ppMemDesc); +} + +static void __nvoc_thunk_Notifier_gsyncapiSetNotificationShare(struct GSyncApi *pNotifier, struct NotifShare *pNotifShare) { + notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_GSyncApi_Notifier.offset), pNotifShare); +} + +static NV_STATUS __nvoc_thunk_RsResource_gsyncapiControlFilter(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), pCallContext, pParams); +} + +static NvU32 __nvoc_thunk_RsResource_gsyncapiGetRefCount(struct GSyncApi *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_Notifier_gsyncapiUnregisterEvent(struct GSyncApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { + return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_GSyncApi_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); +} + +static NV_STATUS __nvoc_thunk_RsResource_gsyncapiUnmap(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), pCallContext, pCpuMapping); +} + +static NvBool __nvoc_thunk_RsResource_gsyncapiCanCopy(struct GSyncApi *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RmResource_gsyncapiControl_Prologue(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_gsyncapiMapTo(struct GSyncApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RsResource_gsyncapiAddAdditionalDependants(struct RsClient *pClient, struct GSyncApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), pReference); +} + +static void __nvoc_thunk_RsResource_gsyncapiPreDestruct(struct GSyncApi *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_gsyncapiUnmapFrom(struct GSyncApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_gsyncapiIsDuplicate(struct GSyncApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), hMemory, pDuplicate); +} + +static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_gsyncapiGetNotificationListPtr(struct GSyncApi *pNotifier) { + return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_GSyncApi_Notifier.offset)); +} + +static void __nvoc_thunk_RmResource_gsyncapiControl_Epilogue(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RmResource.offset), pCallContext, pParams); +} + +static struct NotifShare *__nvoc_thunk_Notifier_gsyncapiGetNotificationShare(struct GSyncApi *pNotifier) { + return notifyGetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_GSyncApi_Notifier.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_gsyncapiControlLookup(struct GSyncApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), pParams, ppEntry); +} + +static NV_STATUS __nvoc_thunk_RsResource_gsyncapiMap(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { + return resMap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), pCallContext, pParams, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_Notifier_gsyncapiGetOrAllocNotifShare(struct GSyncApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { + return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_GSyncApi_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); +} + +#if !defined(NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG) +#define NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(x) (0) +#endif + +static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_GSyncApi[] = +{ + { /* [0] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncGetVersion_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x30f10101u, + /*paramSize=*/ sizeof(NV30F1_CTRL_GSYNC_GET_VERSION_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GSyncApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "gsyncapiCtrlCmdGsyncGetVersion" +#endif + }, + { /* [1] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncGetStatusSignals_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x30f10102u, + /*paramSize=*/ sizeof(NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GSyncApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "gsyncapiCtrlCmdGsyncGetStatusSignals" +#endif + }, + { /* [2] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncGetControlParams_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x30f10103u, + /*paramSize=*/ sizeof(NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GSyncApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "gsyncapiCtrlCmdGsyncGetControlParams" +#endif + }, + { /* [3] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncSetControlParams_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x30f10104u, + /*paramSize=*/ sizeof(NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GSyncApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "gsyncapiCtrlCmdGsyncSetControlParams" +#endif + }, + { /* [4] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncGetCaps_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x30f10105u, + /*paramSize=*/ sizeof(NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GSyncApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "gsyncapiCtrlCmdGsyncGetCaps" +#endif + }, + { /* [5] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGetGsyncGpuTopology_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x30f10106u, + /*paramSize=*/ sizeof(NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GSyncApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "gsyncapiCtrlCmdGetGsyncGpuTopology" +#endif + }, + { /* [6] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncGetControlSync_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x30f10110u, + /*paramSize=*/ sizeof(NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GSyncApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "gsyncapiCtrlCmdGsyncGetControlSync" +#endif + }, + { /* [7] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncSetControlSync_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x30f10111u, + /*paramSize=*/ sizeof(NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GSyncApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "gsyncapiCtrlCmdGsyncSetControlSync" +#endif + }, + { /* [8] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncSetControlUnsync_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x30f10112u, + /*paramSize=*/ sizeof(NV30F1_CTRL_GSYNC_SET_CONTROL_UNSYNC_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GSyncApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "gsyncapiCtrlCmdGsyncSetControlUnsync" +#endif + }, + { /* [9] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncGetStatusSync_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x30f10113u, + /*paramSize=*/ sizeof(NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GSyncApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "gsyncapiCtrlCmdGsyncGetStatusSync" +#endif + }, + { /* [10] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncGetStatus_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x30f10114u, + /*paramSize=*/ sizeof(NV30F1_CTRL_GSYNC_GET_STATUS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GSyncApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "gsyncapiCtrlCmdGsyncGetStatus" +#endif + }, + { /* [11] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncGetControlTesting_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x30f10120u, + /*paramSize=*/ sizeof(NV30F1_CTRL_GSYNC_GET_CONTROL_TESTING_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GSyncApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "gsyncapiCtrlCmdGsyncGetControlTesting" +#endif + }, + { /* [12] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncSetControlTesting_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x30f10121u, + /*paramSize=*/ sizeof(NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GSyncApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "gsyncapiCtrlCmdGsyncSetControlTesting" +#endif + }, + { /* [13] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncSetControlWatchdog_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x30f10130u, + /*paramSize=*/ sizeof(NV30F1_CTRL_GSYNC_SET_CONTROL_WATCHDOG_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GSyncApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "gsyncapiCtrlCmdGsyncSetControlWatchdog" +#endif + }, + { /* [14] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncGetControlInterlaceMode_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x30f10140u, + /*paramSize=*/ sizeof(NV30F1_CTRL_GSYNC_GET_CONTROL_INTERLACE_MODE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GSyncApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "gsyncapiCtrlCmdGsyncGetControlInterlaceMode" +#endif + }, + { /* [15] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncSetControlInterlaceMode_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x30f10141u, + /*paramSize=*/ sizeof(NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GSyncApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "gsyncapiCtrlCmdGsyncSetControlInterlaceMode" +#endif + }, + { /* [16] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncGetControlSwapBarrier_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x30f10150u, + /*paramSize=*/ sizeof(NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_BARRIER_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GSyncApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "gsyncapiCtrlCmdGsyncGetControlSwapBarrier" +#endif + }, + { /* [17] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncSetControlSwapBarrier_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x30f10151u, + /*paramSize=*/ sizeof(NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GSyncApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "gsyncapiCtrlCmdGsyncSetControlSwapBarrier" +#endif + }, + { /* [18] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncGetControlSwapLockWindow_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x30f10153u, + /*paramSize=*/ sizeof(NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GSyncApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "gsyncapiCtrlCmdGsyncGetControlSwapLockWindow" +#endif + }, + { /* [19] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncGetOptimizedTiming_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x30f10160u, + /*paramSize=*/ sizeof(NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GSyncApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "gsyncapiCtrlCmdGsyncGetOptimizedTiming" +#endif + }, + { /* [20] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncSetEventNotification_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x30f10170u, + /*paramSize=*/ sizeof(NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GSyncApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "gsyncapiCtrlCmdGsyncSetEventNotification" +#endif + }, + { /* [21] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncSetControlStereoLockMode_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x30f10172u, + /*paramSize=*/ sizeof(NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GSyncApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "gsyncapiCtrlCmdGsyncSetControlStereoLockMode" +#endif + }, + { /* [22] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncGetControlStereoLockMode_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x30f10173u, + /*paramSize=*/ sizeof(NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GSyncApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "gsyncapiCtrlCmdGsyncGetControlStereoLockMode" +#endif + }, + { /* [23] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncReadRegister_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x30f10180u, + /*paramSize=*/ sizeof(NV30F1_CTRL_GSYNC_READ_REGISTER_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GSyncApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "gsyncapiCtrlCmdGsyncReadRegister" +#endif + }, + { /* [24] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncWriteRegister_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*flags=*/ 0x4u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x30f10181u, + /*paramSize=*/ sizeof(NV30F1_CTRL_GSYNC_WRITE_REGISTER_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GSyncApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "gsyncapiCtrlCmdGsyncWriteRegister" +#endif + }, + { /* [25] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncSetLocalSync_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x30f10185u, + /*paramSize=*/ sizeof(NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GSyncApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "gsyncapiCtrlCmdGsyncSetLocalSync" +#endif + }, + { /* [26] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncConfigFlash_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x30f10186u, + /*paramSize=*/ sizeof(NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GSyncApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "gsyncapiCtrlCmdGsyncConfigFlash" +#endif + }, + { /* [27] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncGetHouseSyncMode_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x30f10187u, + /*paramSize=*/ sizeof(NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GSyncApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "gsyncapiCtrlCmdGsyncGetHouseSyncMode" +#endif + }, + { /* [28] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncSetHouseSyncMode_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x30f10188u, + /*paramSize=*/ sizeof(NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GSyncApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "gsyncapiCtrlCmdGsyncSetHouseSyncMode" +#endif + }, + +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_GSyncApi = +{ + /*numEntries=*/ 29, + /*pExportEntries=*/ __nvoc_exported_method_def_GSyncApi +}; + +void __nvoc_dtor_RmResource(RmResource*); +void __nvoc_dtor_Notifier(Notifier*); +void __nvoc_dtor_GSyncApi(GSyncApi *pThis) { + __nvoc_dtor_RmResource(&pThis->__nvoc_base_RmResource); + __nvoc_dtor_Notifier(&pThis->__nvoc_base_Notifier); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_GSyncApi(GSyncApi *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_RmResource(RmResource* , struct CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); +NV_STATUS __nvoc_ctor_Notifier(Notifier* , struct CALL_CONTEXT *); +NV_STATUS __nvoc_ctor_GSyncApi(GSyncApi *pThis, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_RmResource(&pThis->__nvoc_base_RmResource, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_GSyncApi_fail_RmResource; + status = __nvoc_ctor_Notifier(&pThis->__nvoc_base_Notifier, arg_pCallContext); + if (status != NV_OK) goto __nvoc_ctor_GSyncApi_fail_Notifier; + __nvoc_init_dataField_GSyncApi(pThis); + + status = __nvoc_gsyncapiConstruct(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_GSyncApi_fail__init; + goto __nvoc_ctor_GSyncApi_exit; // Success + +__nvoc_ctor_GSyncApi_fail__init: + __nvoc_dtor_Notifier(&pThis->__nvoc_base_Notifier); +__nvoc_ctor_GSyncApi_fail_Notifier: + __nvoc_dtor_RmResource(&pThis->__nvoc_base_RmResource); +__nvoc_ctor_GSyncApi_fail_RmResource: +__nvoc_ctor_GSyncApi_exit: + + return status; +} + +static void __nvoc_init_funcTable_GSyncApi_1(GSyncApi *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); + + pThis->__gsyncapiControl__ = &gsyncapiControl_IMPL; + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__gsyncapiCtrlCmdGsyncGetVersion__ = &gsyncapiCtrlCmdGsyncGetVersion_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__gsyncapiCtrlCmdGetGsyncGpuTopology__ = &gsyncapiCtrlCmdGetGsyncGpuTopology_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__gsyncapiCtrlCmdGsyncGetStatusSignals__ = &gsyncapiCtrlCmdGsyncGetStatusSignals_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__gsyncapiCtrlCmdGsyncGetControlParams__ = &gsyncapiCtrlCmdGsyncGetControlParams_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__gsyncapiCtrlCmdGsyncSetControlParams__ = &gsyncapiCtrlCmdGsyncSetControlParams_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__gsyncapiCtrlCmdGsyncGetControlSync__ = &gsyncapiCtrlCmdGsyncGetControlSync_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__gsyncapiCtrlCmdGsyncSetControlSync__ = &gsyncapiCtrlCmdGsyncSetControlSync_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__gsyncapiCtrlCmdGsyncSetControlUnsync__ = &gsyncapiCtrlCmdGsyncSetControlUnsync_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__gsyncapiCtrlCmdGsyncGetStatusSync__ = &gsyncapiCtrlCmdGsyncGetStatusSync_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__gsyncapiCtrlCmdGsyncGetStatus__ = &gsyncapiCtrlCmdGsyncGetStatus_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__gsyncapiCtrlCmdGsyncGetControlTesting__ = &gsyncapiCtrlCmdGsyncGetControlTesting_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__gsyncapiCtrlCmdGsyncSetControlTesting__ = &gsyncapiCtrlCmdGsyncSetControlTesting_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__gsyncapiCtrlCmdGsyncSetControlWatchdog__ = &gsyncapiCtrlCmdGsyncSetControlWatchdog_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__gsyncapiCtrlCmdGsyncGetControlInterlaceMode__ = &gsyncapiCtrlCmdGsyncGetControlInterlaceMode_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__gsyncapiCtrlCmdGsyncSetControlInterlaceMode__ = &gsyncapiCtrlCmdGsyncSetControlInterlaceMode_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__gsyncapiCtrlCmdGsyncGetControlSwapBarrier__ = &gsyncapiCtrlCmdGsyncGetControlSwapBarrier_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__gsyncapiCtrlCmdGsyncSetControlSwapBarrier__ = &gsyncapiCtrlCmdGsyncSetControlSwapBarrier_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__gsyncapiCtrlCmdGsyncGetControlSwapLockWindow__ = &gsyncapiCtrlCmdGsyncGetControlSwapLockWindow_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__gsyncapiCtrlCmdGsyncGetCaps__ = &gsyncapiCtrlCmdGsyncGetCaps_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__gsyncapiCtrlCmdGsyncGetOptimizedTiming__ = &gsyncapiCtrlCmdGsyncGetOptimizedTiming_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__gsyncapiCtrlCmdGsyncSetEventNotification__ = &gsyncapiCtrlCmdGsyncSetEventNotification_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__gsyncapiCtrlCmdGsyncGetControlStereoLockMode__ = &gsyncapiCtrlCmdGsyncGetControlStereoLockMode_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__gsyncapiCtrlCmdGsyncSetControlStereoLockMode__ = &gsyncapiCtrlCmdGsyncSetControlStereoLockMode_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__gsyncapiCtrlCmdGsyncReadRegister__ = &gsyncapiCtrlCmdGsyncReadRegister_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + pThis->__gsyncapiCtrlCmdGsyncWriteRegister__ = &gsyncapiCtrlCmdGsyncWriteRegister_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__gsyncapiCtrlCmdGsyncSetLocalSync__ = &gsyncapiCtrlCmdGsyncSetLocalSync_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__gsyncapiCtrlCmdGsyncConfigFlash__ = &gsyncapiCtrlCmdGsyncConfigFlash_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__gsyncapiCtrlCmdGsyncGetHouseSyncMode__ = &gsyncapiCtrlCmdGsyncGetHouseSyncMode_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__gsyncapiCtrlCmdGsyncSetHouseSyncMode__ = &gsyncapiCtrlCmdGsyncSetHouseSyncMode_IMPL; +#endif + + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__resControl__ = &__nvoc_thunk_GSyncApi_resControl; + + pThis->__gsyncapiShareCallback__ = &__nvoc_thunk_RmResource_gsyncapiShareCallback; + + pThis->__gsyncapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_gsyncapiCheckMemInterUnmap; + + pThis->__gsyncapiAccessCallback__ = &__nvoc_thunk_RmResource_gsyncapiAccessCallback; + + pThis->__gsyncapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_gsyncapiGetMemInterMapParams; + + pThis->__gsyncapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_gsyncapiGetMemoryMappingDescriptor; + + pThis->__gsyncapiSetNotificationShare__ = &__nvoc_thunk_Notifier_gsyncapiSetNotificationShare; + + pThis->__gsyncapiControlFilter__ = &__nvoc_thunk_RsResource_gsyncapiControlFilter; + + pThis->__gsyncapiGetRefCount__ = &__nvoc_thunk_RsResource_gsyncapiGetRefCount; + + pThis->__gsyncapiUnregisterEvent__ = &__nvoc_thunk_Notifier_gsyncapiUnregisterEvent; + + pThis->__gsyncapiUnmap__ = &__nvoc_thunk_RsResource_gsyncapiUnmap; + + pThis->__gsyncapiCanCopy__ = &__nvoc_thunk_RsResource_gsyncapiCanCopy; + + pThis->__gsyncapiControl_Prologue__ = &__nvoc_thunk_RmResource_gsyncapiControl_Prologue; + + pThis->__gsyncapiMapTo__ = &__nvoc_thunk_RsResource_gsyncapiMapTo; + + pThis->__gsyncapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_gsyncapiAddAdditionalDependants; + + pThis->__gsyncapiPreDestruct__ = &__nvoc_thunk_RsResource_gsyncapiPreDestruct; + + pThis->__gsyncapiUnmapFrom__ = &__nvoc_thunk_RsResource_gsyncapiUnmapFrom; + + pThis->__gsyncapiIsDuplicate__ = &__nvoc_thunk_RsResource_gsyncapiIsDuplicate; + + pThis->__gsyncapiGetNotificationListPtr__ = &__nvoc_thunk_Notifier_gsyncapiGetNotificationListPtr; + + pThis->__gsyncapiControl_Epilogue__ = &__nvoc_thunk_RmResource_gsyncapiControl_Epilogue; + + pThis->__gsyncapiGetNotificationShare__ = &__nvoc_thunk_Notifier_gsyncapiGetNotificationShare; + + pThis->__gsyncapiControlLookup__ = &__nvoc_thunk_RsResource_gsyncapiControlLookup; + + pThis->__gsyncapiMap__ = &__nvoc_thunk_RsResource_gsyncapiMap; + + pThis->__gsyncapiGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_gsyncapiGetOrAllocNotifShare; +} + +void __nvoc_init_funcTable_GSyncApi(GSyncApi *pThis) { + __nvoc_init_funcTable_GSyncApi_1(pThis); +} + +void __nvoc_init_RmResource(RmResource*); +void __nvoc_init_Notifier(Notifier*); +void __nvoc_init_GSyncApi(GSyncApi *pThis) { + pThis->__nvoc_pbase_GSyncApi = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; + pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource; + pThis->__nvoc_pbase_RmResourceCommon = &pThis->__nvoc_base_RmResource.__nvoc_base_RmResourceCommon; + pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_RmResource; + pThis->__nvoc_pbase_INotifier = &pThis->__nvoc_base_Notifier.__nvoc_base_INotifier; + pThis->__nvoc_pbase_Notifier = &pThis->__nvoc_base_Notifier; + __nvoc_init_RmResource(&pThis->__nvoc_base_RmResource); + __nvoc_init_Notifier(&pThis->__nvoc_base_Notifier); + __nvoc_init_funcTable_GSyncApi(pThis); +} + +NV_STATUS __nvoc_objCreate_GSyncApi(GSyncApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status; + Object *pParentObj; + GSyncApi *pThis; + + pThis = portMemAllocNonPaged(sizeof(GSyncApi)); + if (pThis == NULL) return NV_ERR_NO_MEMORY; + + portMemSet(pThis, 0, sizeof(GSyncApi)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_GSyncApi); + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_GSyncApi(pThis); + status = __nvoc_ctor_GSyncApi(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_objCreate_GSyncApi_cleanup; + + *ppThis = pThis; + return NV_OK; + +__nvoc_objCreate_GSyncApi_cleanup: + // do not call destructors here since the constructor already called them + portMemFree(pThis); + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_GSyncApi(GSyncApi **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + struct CALL_CONTEXT * arg_pCallContext = va_arg(args, struct CALL_CONTEXT *); + struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams = va_arg(args, struct RS_RES_ALLOC_PARAMS_INTERNAL *); + + status = __nvoc_objCreate_GSyncApi(ppThis, pParent, createFlags, arg_pCallContext, arg_pParams); + + return status; +} + diff --git a/src/nvidia/generated/g_gsync_api_nvoc.h b/src/nvidia/generated/g_gsync_api_nvoc.h new file mode 100644 index 000000000..a902e7251 --- /dev/null +++ b/src/nvidia/generated/g_gsync_api_nvoc.h @@ -0,0 +1,489 @@ +#ifndef _G_GSYNC_API_NVOC_H_ +#define _G_GSYNC_API_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_gsync_api_nvoc.h" + +#ifndef GSYNCAPI_H_ +#define GSYNCAPI_H_ + +/* ------------------------ Includes --------------------------------------- */ +#include "ctrl/ctrl30f1.h" +#include "resserv/resserv.h" +#include "rmapi/resource.h" +#include "core/core.h" +#include "rmapi/event.h" + +/* ------------------------ Macros & Defines ------------------------------- */ + +#ifdef NVOC_GSYNC_API_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct GSyncApi { + const struct NVOC_RTTI *__nvoc_rtti; + struct RmResource __nvoc_base_RmResource; + struct Notifier __nvoc_base_Notifier; + struct Object *__nvoc_pbase_Object; + struct RsResource *__nvoc_pbase_RsResource; + struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; + struct RmResource *__nvoc_pbase_RmResource; + struct INotifier *__nvoc_pbase_INotifier; + struct Notifier *__nvoc_pbase_Notifier; + struct GSyncApi *__nvoc_pbase_GSyncApi; + NV_STATUS (*__gsyncapiControl__)(struct GSyncApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__gsyncapiCtrlCmdGsyncGetVersion__)(struct GSyncApi *, NV30F1_CTRL_GSYNC_GET_VERSION_PARAMS *); + NV_STATUS (*__gsyncapiCtrlCmdGetGsyncGpuTopology__)(struct GSyncApi *, NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PARAMS *); + NV_STATUS (*__gsyncapiCtrlCmdGsyncGetStatusSignals__)(struct GSyncApi *, NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_PARAMS *); + NV_STATUS (*__gsyncapiCtrlCmdGsyncGetControlParams__)(struct GSyncApi *, NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS *); + NV_STATUS (*__gsyncapiCtrlCmdGsyncSetControlParams__)(struct GSyncApi *, NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS *); + NV_STATUS (*__gsyncapiCtrlCmdGsyncGetControlSync__)(struct GSyncApi *, NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS *); + NV_STATUS (*__gsyncapiCtrlCmdGsyncSetControlSync__)(struct GSyncApi *, NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_PARAMS *); + NV_STATUS (*__gsyncapiCtrlCmdGsyncSetControlUnsync__)(struct GSyncApi *, NV30F1_CTRL_GSYNC_SET_CONTROL_UNSYNC_PARAMS *); + NV_STATUS (*__gsyncapiCtrlCmdGsyncGetStatusSync__)(struct GSyncApi *, NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_PARAMS *); + NV_STATUS (*__gsyncapiCtrlCmdGsyncGetStatus__)(struct GSyncApi *, NV30F1_CTRL_GSYNC_GET_STATUS_PARAMS *); + NV_STATUS (*__gsyncapiCtrlCmdGsyncGetControlTesting__)(struct GSyncApi *, NV30F1_CTRL_GSYNC_GET_CONTROL_TESTING_PARAMS *); + NV_STATUS (*__gsyncapiCtrlCmdGsyncSetControlTesting__)(struct GSyncApi *, NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS *); + NV_STATUS (*__gsyncapiCtrlCmdGsyncSetControlWatchdog__)(struct GSyncApi *, NV30F1_CTRL_GSYNC_SET_CONTROL_WATCHDOG_PARAMS *); + NV_STATUS (*__gsyncapiCtrlCmdGsyncGetControlInterlaceMode__)(struct GSyncApi *, NV30F1_CTRL_GSYNC_GET_CONTROL_INTERLACE_MODE_PARAMS *); + NV_STATUS (*__gsyncapiCtrlCmdGsyncSetControlInterlaceMode__)(struct GSyncApi *, NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS *); + NV_STATUS (*__gsyncapiCtrlCmdGsyncGetControlSwapBarrier__)(struct GSyncApi *, NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_BARRIER_PARAMS *); + NV_STATUS (*__gsyncapiCtrlCmdGsyncSetControlSwapBarrier__)(struct GSyncApi *, NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS *); + NV_STATUS (*__gsyncapiCtrlCmdGsyncGetControlSwapLockWindow__)(struct GSyncApi *, NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS *); + NV_STATUS (*__gsyncapiCtrlCmdGsyncGetCaps__)(struct GSyncApi *, NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS *); + NV_STATUS (*__gsyncapiCtrlCmdGsyncGetOptimizedTiming__)(struct GSyncApi *, NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS *); + NV_STATUS (*__gsyncapiCtrlCmdGsyncSetEventNotification__)(struct GSyncApi *, NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_PARAMS *); + NV_STATUS (*__gsyncapiCtrlCmdGsyncGetControlStereoLockMode__)(struct GSyncApi *, NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS *); + NV_STATUS (*__gsyncapiCtrlCmdGsyncSetControlStereoLockMode__)(struct GSyncApi *, NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS *); + NV_STATUS (*__gsyncapiCtrlCmdGsyncReadRegister__)(struct GSyncApi *, NV30F1_CTRL_GSYNC_READ_REGISTER_PARAMS *); + NV_STATUS (*__gsyncapiCtrlCmdGsyncWriteRegister__)(struct GSyncApi *, NV30F1_CTRL_GSYNC_WRITE_REGISTER_PARAMS *); + NV_STATUS (*__gsyncapiCtrlCmdGsyncSetLocalSync__)(struct GSyncApi *, NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS *); + NV_STATUS (*__gsyncapiCtrlCmdGsyncConfigFlash__)(struct GSyncApi *, NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH_PARAMS *); + NV_STATUS (*__gsyncapiCtrlCmdGsyncGetHouseSyncMode__)(struct GSyncApi *, NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS *); + NV_STATUS (*__gsyncapiCtrlCmdGsyncSetHouseSyncMode__)(struct GSyncApi *, NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS *); + NvBool (*__gsyncapiShareCallback__)(struct GSyncApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__gsyncapiCheckMemInterUnmap__)(struct GSyncApi *, NvBool); + NvBool (*__gsyncapiAccessCallback__)(struct GSyncApi *, struct RsClient *, void *, RsAccessRight); + NV_STATUS (*__gsyncapiGetMemInterMapParams__)(struct GSyncApi *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__gsyncapiGetMemoryMappingDescriptor__)(struct GSyncApi *, struct MEMORY_DESCRIPTOR **); + void (*__gsyncapiSetNotificationShare__)(struct GSyncApi *, struct NotifShare *); + NV_STATUS (*__gsyncapiControlFilter__)(struct GSyncApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvU32 (*__gsyncapiGetRefCount__)(struct GSyncApi *); + NV_STATUS (*__gsyncapiUnregisterEvent__)(struct GSyncApi *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__gsyncapiUnmap__)(struct GSyncApi *, struct CALL_CONTEXT *, RsCpuMapping *); + NvBool (*__gsyncapiCanCopy__)(struct GSyncApi *); + NV_STATUS (*__gsyncapiControl_Prologue__)(struct GSyncApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__gsyncapiMapTo__)(struct GSyncApi *, RS_RES_MAP_TO_PARAMS *); + void (*__gsyncapiAddAdditionalDependants__)(struct RsClient *, struct GSyncApi *, RsResourceRef *); + void (*__gsyncapiPreDestruct__)(struct GSyncApi *); + NV_STATUS (*__gsyncapiUnmapFrom__)(struct GSyncApi *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__gsyncapiIsDuplicate__)(struct GSyncApi *, NvHandle, NvBool *); + PEVENTNOTIFICATION *(*__gsyncapiGetNotificationListPtr__)(struct GSyncApi *); + void (*__gsyncapiControl_Epilogue__)(struct GSyncApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + struct NotifShare *(*__gsyncapiGetNotificationShare__)(struct GSyncApi *); + NV_STATUS (*__gsyncapiControlLookup__)(struct GSyncApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__gsyncapiMap__)(struct GSyncApi *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); + NV_STATUS (*__gsyncapiGetOrAllocNotifShare__)(struct GSyncApi *, NvHandle, NvHandle, struct NotifShare **); + NvU32 instance; + NvU32 classNum; + NvU32 notifyAction; + NvU32 lastEventNotified; + PEVENTNOTIFICATION pEventByType[9]; + NvBool oldEventNotification; +}; + +#ifndef __NVOC_CLASS_GSyncApi_TYPEDEF__ +#define __NVOC_CLASS_GSyncApi_TYPEDEF__ +typedef struct GSyncApi GSyncApi; +#endif /* __NVOC_CLASS_GSyncApi_TYPEDEF__ */ + +#ifndef __nvoc_class_id_GSyncApi +#define __nvoc_class_id_GSyncApi 0x214628 +#endif /* __nvoc_class_id_GSyncApi */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_GSyncApi; + +#define __staticCast_GSyncApi(pThis) \ + ((pThis)->__nvoc_pbase_GSyncApi) + +#ifdef __nvoc_gsync_api_h_disabled +#define __dynamicCast_GSyncApi(pThis) ((GSyncApi*)NULL) +#else //__nvoc_gsync_api_h_disabled +#define __dynamicCast_GSyncApi(pThis) \ + ((GSyncApi*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(GSyncApi))) +#endif //__nvoc_gsync_api_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_GSyncApi(GSyncApi**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_GSyncApi(GSyncApi**, Dynamic*, NvU32, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +#define __objCreate_GSyncApi(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ + __nvoc_objCreate_GSyncApi((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) + +#define gsyncapiControl(pGsyncApi, pCallContext, pParams) gsyncapiControl_DISPATCH(pGsyncApi, pCallContext, pParams) +#define gsyncapiCtrlCmdGsyncGetVersion(pGsyncApi, pGsyncGetVersionParams) gsyncapiCtrlCmdGsyncGetVersion_DISPATCH(pGsyncApi, pGsyncGetVersionParams) +#define gsyncapiCtrlCmdGetGsyncGpuTopology(pGsyncApi, pParams) gsyncapiCtrlCmdGetGsyncGpuTopology_DISPATCH(pGsyncApi, pParams) +#define gsyncapiCtrlCmdGsyncGetStatusSignals(pGsyncApi, pParams) gsyncapiCtrlCmdGsyncGetStatusSignals_DISPATCH(pGsyncApi, pParams) +#define gsyncapiCtrlCmdGsyncGetControlParams(pGsyncApi, pParams) gsyncapiCtrlCmdGsyncGetControlParams_DISPATCH(pGsyncApi, pParams) +#define gsyncapiCtrlCmdGsyncSetControlParams(pGsyncApi, pParams) gsyncapiCtrlCmdGsyncSetControlParams_DISPATCH(pGsyncApi, pParams) +#define gsyncapiCtrlCmdGsyncGetControlSync(pGsyncApi, pParams) gsyncapiCtrlCmdGsyncGetControlSync_DISPATCH(pGsyncApi, pParams) +#define gsyncapiCtrlCmdGsyncSetControlSync(pGsyncApi, pParams) gsyncapiCtrlCmdGsyncSetControlSync_DISPATCH(pGsyncApi, pParams) +#define gsyncapiCtrlCmdGsyncSetControlUnsync(pGsyncApi, pParams) gsyncapiCtrlCmdGsyncSetControlUnsync_DISPATCH(pGsyncApi, pParams) +#define gsyncapiCtrlCmdGsyncGetStatusSync(pGsyncApi, pParams) gsyncapiCtrlCmdGsyncGetStatusSync_DISPATCH(pGsyncApi, pParams) +#define gsyncapiCtrlCmdGsyncGetStatus(pGsyncApi, pParams) gsyncapiCtrlCmdGsyncGetStatus_DISPATCH(pGsyncApi, pParams) +#define gsyncapiCtrlCmdGsyncGetControlTesting(pGsyncApi, pParams) gsyncapiCtrlCmdGsyncGetControlTesting_DISPATCH(pGsyncApi, pParams) +#define gsyncapiCtrlCmdGsyncSetControlTesting(pGsyncApi, pParams) gsyncapiCtrlCmdGsyncSetControlTesting_DISPATCH(pGsyncApi, pParams) +#define gsyncapiCtrlCmdGsyncSetControlWatchdog(pGsyncApi, pParams) gsyncapiCtrlCmdGsyncSetControlWatchdog_DISPATCH(pGsyncApi, pParams) +#define gsyncapiCtrlCmdGsyncGetControlInterlaceMode(pGsyncApi, pParams) gsyncapiCtrlCmdGsyncGetControlInterlaceMode_DISPATCH(pGsyncApi, pParams) +#define gsyncapiCtrlCmdGsyncSetControlInterlaceMode(pGsyncApi, pParams) gsyncapiCtrlCmdGsyncSetControlInterlaceMode_DISPATCH(pGsyncApi, pParams) +#define gsyncapiCtrlCmdGsyncGetControlSwapBarrier(pGsyncApi, pParams) gsyncapiCtrlCmdGsyncGetControlSwapBarrier_DISPATCH(pGsyncApi, pParams) +#define gsyncapiCtrlCmdGsyncSetControlSwapBarrier(pGsyncApi, pParams) gsyncapiCtrlCmdGsyncSetControlSwapBarrier_DISPATCH(pGsyncApi, pParams) +#define gsyncapiCtrlCmdGsyncGetControlSwapLockWindow(pGsyncApi, pParams) gsyncapiCtrlCmdGsyncGetControlSwapLockWindow_DISPATCH(pGsyncApi, pParams) +#define gsyncapiCtrlCmdGsyncGetCaps(pGsyncApi, pParams) gsyncapiCtrlCmdGsyncGetCaps_DISPATCH(pGsyncApi, pParams) +#define gsyncapiCtrlCmdGsyncGetOptimizedTiming(pGsyncApi, pParams) gsyncapiCtrlCmdGsyncGetOptimizedTiming_DISPATCH(pGsyncApi, pParams) +#define gsyncapiCtrlCmdGsyncSetEventNotification(pGsyncApi, pSetEventParams) gsyncapiCtrlCmdGsyncSetEventNotification_DISPATCH(pGsyncApi, pSetEventParams) +#define gsyncapiCtrlCmdGsyncGetControlStereoLockMode(pGsyncApi, pParams) gsyncapiCtrlCmdGsyncGetControlStereoLockMode_DISPATCH(pGsyncApi, pParams) +#define gsyncapiCtrlCmdGsyncSetControlStereoLockMode(pGsyncApi, pParams) gsyncapiCtrlCmdGsyncSetControlStereoLockMode_DISPATCH(pGsyncApi, pParams) +#define gsyncapiCtrlCmdGsyncReadRegister(pGsyncApi, pParams) gsyncapiCtrlCmdGsyncReadRegister_DISPATCH(pGsyncApi, pParams) +#define gsyncapiCtrlCmdGsyncWriteRegister(pGsyncApi, pParams) gsyncapiCtrlCmdGsyncWriteRegister_DISPATCH(pGsyncApi, pParams) +#define gsyncapiCtrlCmdGsyncSetLocalSync(pGsyncApi, pParams) gsyncapiCtrlCmdGsyncSetLocalSync_DISPATCH(pGsyncApi, pParams) +#define gsyncapiCtrlCmdGsyncConfigFlash(pGsyncApi, pParams) gsyncapiCtrlCmdGsyncConfigFlash_DISPATCH(pGsyncApi, pParams) +#define gsyncapiCtrlCmdGsyncGetHouseSyncMode(pGsyncApi, pParams) gsyncapiCtrlCmdGsyncGetHouseSyncMode_DISPATCH(pGsyncApi, pParams) +#define gsyncapiCtrlCmdGsyncSetHouseSyncMode(pGsyncApi, pParams) gsyncapiCtrlCmdGsyncSetHouseSyncMode_DISPATCH(pGsyncApi, pParams) +#define gsyncapiShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) gsyncapiShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define gsyncapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) gsyncapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define gsyncapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) gsyncapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +#define gsyncapiGetMemInterMapParams(pRmResource, pParams) gsyncapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define gsyncapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) gsyncapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define gsyncapiSetNotificationShare(pNotifier, pNotifShare) gsyncapiSetNotificationShare_DISPATCH(pNotifier, pNotifShare) +#define gsyncapiControlFilter(pResource, pCallContext, pParams) gsyncapiControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define gsyncapiGetRefCount(pResource) gsyncapiGetRefCount_DISPATCH(pResource) +#define gsyncapiUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) gsyncapiUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define gsyncapiUnmap(pResource, pCallContext, pCpuMapping) gsyncapiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define gsyncapiCanCopy(pResource) gsyncapiCanCopy_DISPATCH(pResource) +#define gsyncapiControl_Prologue(pResource, pCallContext, pParams) gsyncapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define gsyncapiMapTo(pResource, pParams) gsyncapiMapTo_DISPATCH(pResource, pParams) +#define gsyncapiAddAdditionalDependants(pClient, pResource, pReference) gsyncapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define gsyncapiPreDestruct(pResource) gsyncapiPreDestruct_DISPATCH(pResource) +#define gsyncapiUnmapFrom(pResource, pParams) gsyncapiUnmapFrom_DISPATCH(pResource, pParams) +#define gsyncapiIsDuplicate(pResource, hMemory, pDuplicate) gsyncapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define gsyncapiGetNotificationListPtr(pNotifier) gsyncapiGetNotificationListPtr_DISPATCH(pNotifier) +#define gsyncapiControl_Epilogue(pResource, pCallContext, pParams) gsyncapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define gsyncapiGetNotificationShare(pNotifier) gsyncapiGetNotificationShare_DISPATCH(pNotifier) +#define gsyncapiControlLookup(pResource, pParams, ppEntry) gsyncapiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define gsyncapiMap(pResource, pCallContext, pParams, pCpuMapping) gsyncapiMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) +#define gsyncapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) gsyncapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +NV_STATUS gsyncapiControl_IMPL(struct GSyncApi *pGsyncApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); + +static inline NV_STATUS gsyncapiControl_DISPATCH(struct GSyncApi *pGsyncApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGsyncApi->__gsyncapiControl__(pGsyncApi, pCallContext, pParams); +} + +NV_STATUS gsyncapiCtrlCmdGsyncGetVersion_IMPL(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_GET_VERSION_PARAMS *pGsyncGetVersionParams); + +static inline NV_STATUS gsyncapiCtrlCmdGsyncGetVersion_DISPATCH(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_GET_VERSION_PARAMS *pGsyncGetVersionParams) { + return pGsyncApi->__gsyncapiCtrlCmdGsyncGetVersion__(pGsyncApi, pGsyncGetVersionParams); +} + +NV_STATUS gsyncapiCtrlCmdGetGsyncGpuTopology_IMPL(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PARAMS *pParams); + +static inline NV_STATUS gsyncapiCtrlCmdGetGsyncGpuTopology_DISPATCH(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PARAMS *pParams) { + return pGsyncApi->__gsyncapiCtrlCmdGetGsyncGpuTopology__(pGsyncApi, pParams); +} + +NV_STATUS gsyncapiCtrlCmdGsyncGetStatusSignals_IMPL(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_PARAMS *pParams); + +static inline NV_STATUS gsyncapiCtrlCmdGsyncGetStatusSignals_DISPATCH(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_PARAMS *pParams) { + return pGsyncApi->__gsyncapiCtrlCmdGsyncGetStatusSignals__(pGsyncApi, pParams); +} + +NV_STATUS gsyncapiCtrlCmdGsyncGetControlParams_IMPL(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS *pParams); + +static inline NV_STATUS gsyncapiCtrlCmdGsyncGetControlParams_DISPATCH(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS *pParams) { + return pGsyncApi->__gsyncapiCtrlCmdGsyncGetControlParams__(pGsyncApi, pParams); +} + +NV_STATUS gsyncapiCtrlCmdGsyncSetControlParams_IMPL(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS *pParams); + +static inline NV_STATUS gsyncapiCtrlCmdGsyncSetControlParams_DISPATCH(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS *pParams) { + return pGsyncApi->__gsyncapiCtrlCmdGsyncSetControlParams__(pGsyncApi, pParams); +} + +NV_STATUS gsyncapiCtrlCmdGsyncGetControlSync_IMPL(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS *pParams); + +static inline NV_STATUS gsyncapiCtrlCmdGsyncGetControlSync_DISPATCH(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS *pParams) { + return pGsyncApi->__gsyncapiCtrlCmdGsyncGetControlSync__(pGsyncApi, pParams); +} + +NV_STATUS gsyncapiCtrlCmdGsyncSetControlSync_IMPL(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_PARAMS *pParams); + +static inline NV_STATUS gsyncapiCtrlCmdGsyncSetControlSync_DISPATCH(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_PARAMS *pParams) { + return pGsyncApi->__gsyncapiCtrlCmdGsyncSetControlSync__(pGsyncApi, pParams); +} + +NV_STATUS gsyncapiCtrlCmdGsyncSetControlUnsync_IMPL(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_SET_CONTROL_UNSYNC_PARAMS *pParams); + +static inline NV_STATUS gsyncapiCtrlCmdGsyncSetControlUnsync_DISPATCH(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_SET_CONTROL_UNSYNC_PARAMS *pParams) { + return pGsyncApi->__gsyncapiCtrlCmdGsyncSetControlUnsync__(pGsyncApi, pParams); +} + +NV_STATUS gsyncapiCtrlCmdGsyncGetStatusSync_IMPL(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_PARAMS *pParams); + +static inline NV_STATUS gsyncapiCtrlCmdGsyncGetStatusSync_DISPATCH(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_PARAMS *pParams) { + return pGsyncApi->__gsyncapiCtrlCmdGsyncGetStatusSync__(pGsyncApi, pParams); +} + +NV_STATUS gsyncapiCtrlCmdGsyncGetStatus_IMPL(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_GET_STATUS_PARAMS *pParams); + +static inline NV_STATUS gsyncapiCtrlCmdGsyncGetStatus_DISPATCH(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_GET_STATUS_PARAMS *pParams) { + return pGsyncApi->__gsyncapiCtrlCmdGsyncGetStatus__(pGsyncApi, pParams); +} + +NV_STATUS gsyncapiCtrlCmdGsyncGetControlTesting_IMPL(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_GET_CONTROL_TESTING_PARAMS *pParams); + +static inline NV_STATUS gsyncapiCtrlCmdGsyncGetControlTesting_DISPATCH(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_GET_CONTROL_TESTING_PARAMS *pParams) { + return pGsyncApi->__gsyncapiCtrlCmdGsyncGetControlTesting__(pGsyncApi, pParams); +} + +NV_STATUS gsyncapiCtrlCmdGsyncSetControlTesting_IMPL(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS *pParams); + +static inline NV_STATUS gsyncapiCtrlCmdGsyncSetControlTesting_DISPATCH(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS *pParams) { + return pGsyncApi->__gsyncapiCtrlCmdGsyncSetControlTesting__(pGsyncApi, pParams); +} + +NV_STATUS gsyncapiCtrlCmdGsyncSetControlWatchdog_IMPL(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_SET_CONTROL_WATCHDOG_PARAMS *pParams); + +static inline NV_STATUS gsyncapiCtrlCmdGsyncSetControlWatchdog_DISPATCH(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_SET_CONTROL_WATCHDOG_PARAMS *pParams) { + return pGsyncApi->__gsyncapiCtrlCmdGsyncSetControlWatchdog__(pGsyncApi, pParams); +} + +NV_STATUS gsyncapiCtrlCmdGsyncGetControlInterlaceMode_IMPL(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_GET_CONTROL_INTERLACE_MODE_PARAMS *pParams); + +static inline NV_STATUS gsyncapiCtrlCmdGsyncGetControlInterlaceMode_DISPATCH(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_GET_CONTROL_INTERLACE_MODE_PARAMS *pParams) { + return pGsyncApi->__gsyncapiCtrlCmdGsyncGetControlInterlaceMode__(pGsyncApi, pParams); +} + +NV_STATUS gsyncapiCtrlCmdGsyncSetControlInterlaceMode_IMPL(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS *pParams); + +static inline NV_STATUS gsyncapiCtrlCmdGsyncSetControlInterlaceMode_DISPATCH(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS *pParams) { + return pGsyncApi->__gsyncapiCtrlCmdGsyncSetControlInterlaceMode__(pGsyncApi, pParams); +} + +NV_STATUS gsyncapiCtrlCmdGsyncGetControlSwapBarrier_IMPL(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_BARRIER_PARAMS *pParams); + +static inline NV_STATUS gsyncapiCtrlCmdGsyncGetControlSwapBarrier_DISPATCH(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_BARRIER_PARAMS *pParams) { + return pGsyncApi->__gsyncapiCtrlCmdGsyncGetControlSwapBarrier__(pGsyncApi, pParams); +} + +NV_STATUS gsyncapiCtrlCmdGsyncSetControlSwapBarrier_IMPL(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS *pParams); + +static inline NV_STATUS gsyncapiCtrlCmdGsyncSetControlSwapBarrier_DISPATCH(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS *pParams) { + return pGsyncApi->__gsyncapiCtrlCmdGsyncSetControlSwapBarrier__(pGsyncApi, pParams); +} + +NV_STATUS gsyncapiCtrlCmdGsyncGetControlSwapLockWindow_IMPL(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS *pParams); + +static inline NV_STATUS gsyncapiCtrlCmdGsyncGetControlSwapLockWindow_DISPATCH(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS *pParams) { + return pGsyncApi->__gsyncapiCtrlCmdGsyncGetControlSwapLockWindow__(pGsyncApi, pParams); +} + +NV_STATUS gsyncapiCtrlCmdGsyncGetCaps_IMPL(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS *pParams); + +static inline NV_STATUS gsyncapiCtrlCmdGsyncGetCaps_DISPATCH(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS *pParams) { + return pGsyncApi->__gsyncapiCtrlCmdGsyncGetCaps__(pGsyncApi, pParams); +} + +NV_STATUS gsyncapiCtrlCmdGsyncGetOptimizedTiming_IMPL(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS *pParams); + +static inline NV_STATUS gsyncapiCtrlCmdGsyncGetOptimizedTiming_DISPATCH(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS *pParams) { + return pGsyncApi->__gsyncapiCtrlCmdGsyncGetOptimizedTiming__(pGsyncApi, pParams); +} + +NV_STATUS gsyncapiCtrlCmdGsyncSetEventNotification_IMPL(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_PARAMS *pSetEventParams); + +static inline NV_STATUS gsyncapiCtrlCmdGsyncSetEventNotification_DISPATCH(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_PARAMS *pSetEventParams) { + return pGsyncApi->__gsyncapiCtrlCmdGsyncSetEventNotification__(pGsyncApi, pSetEventParams); +} + +NV_STATUS gsyncapiCtrlCmdGsyncGetControlStereoLockMode_IMPL(struct GSyncApi *pGsyncApi, NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS *pParams); + +static inline NV_STATUS gsyncapiCtrlCmdGsyncGetControlStereoLockMode_DISPATCH(struct GSyncApi *pGsyncApi, NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS *pParams) { + return pGsyncApi->__gsyncapiCtrlCmdGsyncGetControlStereoLockMode__(pGsyncApi, pParams); +} + +NV_STATUS gsyncapiCtrlCmdGsyncSetControlStereoLockMode_IMPL(struct GSyncApi *pGsyncApi, NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS *pParams); + +static inline NV_STATUS gsyncapiCtrlCmdGsyncSetControlStereoLockMode_DISPATCH(struct GSyncApi *pGsyncApi, NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS *pParams) { + return pGsyncApi->__gsyncapiCtrlCmdGsyncSetControlStereoLockMode__(pGsyncApi, pParams); +} + +NV_STATUS gsyncapiCtrlCmdGsyncReadRegister_IMPL(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_READ_REGISTER_PARAMS *pParams); + +static inline NV_STATUS gsyncapiCtrlCmdGsyncReadRegister_DISPATCH(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_READ_REGISTER_PARAMS *pParams) { + return pGsyncApi->__gsyncapiCtrlCmdGsyncReadRegister__(pGsyncApi, pParams); +} + +NV_STATUS gsyncapiCtrlCmdGsyncWriteRegister_IMPL(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_WRITE_REGISTER_PARAMS *pParams); + +static inline NV_STATUS gsyncapiCtrlCmdGsyncWriteRegister_DISPATCH(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_WRITE_REGISTER_PARAMS *pParams) { + return pGsyncApi->__gsyncapiCtrlCmdGsyncWriteRegister__(pGsyncApi, pParams); +} + +NV_STATUS gsyncapiCtrlCmdGsyncSetLocalSync_IMPL(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS *pParams); + +static inline NV_STATUS gsyncapiCtrlCmdGsyncSetLocalSync_DISPATCH(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS *pParams) { + return pGsyncApi->__gsyncapiCtrlCmdGsyncSetLocalSync__(pGsyncApi, pParams); +} + +NV_STATUS gsyncapiCtrlCmdGsyncConfigFlash_IMPL(struct GSyncApi *pGsyncApi, NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH_PARAMS *pParams); + +static inline NV_STATUS gsyncapiCtrlCmdGsyncConfigFlash_DISPATCH(struct GSyncApi *pGsyncApi, NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH_PARAMS *pParams) { + return pGsyncApi->__gsyncapiCtrlCmdGsyncConfigFlash__(pGsyncApi, pParams); +} + +NV_STATUS gsyncapiCtrlCmdGsyncGetHouseSyncMode_IMPL(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS *pParams); + +static inline NV_STATUS gsyncapiCtrlCmdGsyncGetHouseSyncMode_DISPATCH(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS *pParams) { + return pGsyncApi->__gsyncapiCtrlCmdGsyncGetHouseSyncMode__(pGsyncApi, pParams); +} + +NV_STATUS gsyncapiCtrlCmdGsyncSetHouseSyncMode_IMPL(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS *pParams); + +static inline NV_STATUS gsyncapiCtrlCmdGsyncSetHouseSyncMode_DISPATCH(struct GSyncApi *pGsyncApi, NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS *pParams) { + return pGsyncApi->__gsyncapiCtrlCmdGsyncSetHouseSyncMode__(pGsyncApi, pParams); +} + +static inline NvBool gsyncapiShareCallback_DISPATCH(struct GSyncApi *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__gsyncapiShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS gsyncapiCheckMemInterUnmap_DISPATCH(struct GSyncApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__gsyncapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NvBool gsyncapiAccessCallback_DISPATCH(struct GSyncApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return pResource->__gsyncapiAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); +} + +static inline NV_STATUS gsyncapiGetMemInterMapParams_DISPATCH(struct GSyncApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__gsyncapiGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS gsyncapiGetMemoryMappingDescriptor_DISPATCH(struct GSyncApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__gsyncapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +} + +static inline void gsyncapiSetNotificationShare_DISPATCH(struct GSyncApi *pNotifier, struct NotifShare *pNotifShare) { + pNotifier->__gsyncapiSetNotificationShare__(pNotifier, pNotifShare); +} + +static inline NV_STATUS gsyncapiControlFilter_DISPATCH(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__gsyncapiControlFilter__(pResource, pCallContext, pParams); +} + +static inline NvU32 gsyncapiGetRefCount_DISPATCH(struct GSyncApi *pResource) { + return pResource->__gsyncapiGetRefCount__(pResource); +} + +static inline NV_STATUS gsyncapiUnregisterEvent_DISPATCH(struct GSyncApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { + return pNotifier->__gsyncapiUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); +} + +static inline NV_STATUS gsyncapiUnmap_DISPATCH(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pResource->__gsyncapiUnmap__(pResource, pCallContext, pCpuMapping); +} + +static inline NvBool gsyncapiCanCopy_DISPATCH(struct GSyncApi *pResource) { + return pResource->__gsyncapiCanCopy__(pResource); +} + +static inline NV_STATUS gsyncapiControl_Prologue_DISPATCH(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__gsyncapiControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS gsyncapiMapTo_DISPATCH(struct GSyncApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__gsyncapiMapTo__(pResource, pParams); +} + +static inline void gsyncapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct GSyncApi *pResource, RsResourceRef *pReference) { + pResource->__gsyncapiAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline void gsyncapiPreDestruct_DISPATCH(struct GSyncApi *pResource) { + pResource->__gsyncapiPreDestruct__(pResource); +} + +static inline NV_STATUS gsyncapiUnmapFrom_DISPATCH(struct GSyncApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__gsyncapiUnmapFrom__(pResource, pParams); +} + +static inline NV_STATUS gsyncapiIsDuplicate_DISPATCH(struct GSyncApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__gsyncapiIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline PEVENTNOTIFICATION *gsyncapiGetNotificationListPtr_DISPATCH(struct GSyncApi *pNotifier) { + return pNotifier->__gsyncapiGetNotificationListPtr__(pNotifier); +} + +static inline void gsyncapiControl_Epilogue_DISPATCH(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__gsyncapiControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline struct NotifShare *gsyncapiGetNotificationShare_DISPATCH(struct GSyncApi *pNotifier) { + return pNotifier->__gsyncapiGetNotificationShare__(pNotifier); +} + +static inline NV_STATUS gsyncapiControlLookup_DISPATCH(struct GSyncApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__gsyncapiControlLookup__(pResource, pParams, ppEntry); +} + +static inline NV_STATUS gsyncapiMap_DISPATCH(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { + return pResource->__gsyncapiMap__(pResource, pCallContext, pParams, pCpuMapping); +} + +static inline NV_STATUS gsyncapiGetOrAllocNotifShare_DISPATCH(struct GSyncApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { + return pNotifier->__gsyncapiGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); +} + +NV_STATUS gsyncapiConstruct_IMPL(struct GSyncApi *arg_pGsyncApi, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + +#define __nvoc_gsyncapiConstruct(arg_pGsyncApi, arg_pCallContext, arg_pParams) gsyncapiConstruct_IMPL(arg_pGsyncApi, arg_pCallContext, arg_pParams) +#undef PRIVATE_FIELD + + +void CliNotifyGsyncEvent (NvU32, NvU32); + +#endif // GSYNCAPI_H_ + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_GSYNC_API_NVOC_H_ diff --git a/src/nvidia/generated/g_gsync_nvoc.c b/src/nvidia/generated/g_gsync_nvoc.c new file mode 100644 index 000000000..9fec6af9b --- /dev/null +++ b/src/nvidia/generated/g_gsync_nvoc.c @@ -0,0 +1,154 @@ +#define NVOC_GSYNC_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_gsync_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0xd07fd0 = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGSYNCMGR; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +void __nvoc_init_OBJGSYNCMGR(OBJGSYNCMGR*); +void __nvoc_init_funcTable_OBJGSYNCMGR(OBJGSYNCMGR*); +NV_STATUS __nvoc_ctor_OBJGSYNCMGR(OBJGSYNCMGR*); +void __nvoc_init_dataField_OBJGSYNCMGR(OBJGSYNCMGR*); +void __nvoc_dtor_OBJGSYNCMGR(OBJGSYNCMGR*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_OBJGSYNCMGR; + +static const struct NVOC_RTTI __nvoc_rtti_OBJGSYNCMGR_OBJGSYNCMGR = { + /*pClassDef=*/ &__nvoc_class_def_OBJGSYNCMGR, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_OBJGSYNCMGR, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_OBJGSYNCMGR_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(OBJGSYNCMGR, __nvoc_base_Object), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_OBJGSYNCMGR = { + /*numRelatives=*/ 2, + /*relatives=*/ { + &__nvoc_rtti_OBJGSYNCMGR_OBJGSYNCMGR, + &__nvoc_rtti_OBJGSYNCMGR_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGSYNCMGR = +{ + /*classInfo=*/ { + /*size=*/ sizeof(OBJGSYNCMGR), + /*classId=*/ classId(OBJGSYNCMGR), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "OBJGSYNCMGR", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_OBJGSYNCMGR, + /*pCastInfo=*/ &__nvoc_castinfo_OBJGSYNCMGR, + /*pExportInfo=*/ &__nvoc_export_info_OBJGSYNCMGR +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_OBJGSYNCMGR = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_Object(Object*); +void __nvoc_dtor_OBJGSYNCMGR(OBJGSYNCMGR *pThis) { + __nvoc_gsyncmgrDestruct(pThis); + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_OBJGSYNCMGR(OBJGSYNCMGR *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_Object(Object* ); +NV_STATUS __nvoc_ctor_OBJGSYNCMGR(OBJGSYNCMGR *pThis) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_Object(&pThis->__nvoc_base_Object); + if (status != NV_OK) goto __nvoc_ctor_OBJGSYNCMGR_fail_Object; + __nvoc_init_dataField_OBJGSYNCMGR(pThis); + + status = __nvoc_gsyncmgrConstruct(pThis); + if (status != NV_OK) goto __nvoc_ctor_OBJGSYNCMGR_fail__init; + goto __nvoc_ctor_OBJGSYNCMGR_exit; // Success + +__nvoc_ctor_OBJGSYNCMGR_fail__init: + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); +__nvoc_ctor_OBJGSYNCMGR_fail_Object: +__nvoc_ctor_OBJGSYNCMGR_exit: + + return status; +} + +static void __nvoc_init_funcTable_OBJGSYNCMGR_1(OBJGSYNCMGR *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_funcTable_OBJGSYNCMGR(OBJGSYNCMGR *pThis) { + __nvoc_init_funcTable_OBJGSYNCMGR_1(pThis); +} + +void __nvoc_init_Object(Object*); +void __nvoc_init_OBJGSYNCMGR(OBJGSYNCMGR *pThis) { + pThis->__nvoc_pbase_OBJGSYNCMGR = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Object; + __nvoc_init_Object(&pThis->__nvoc_base_Object); + __nvoc_init_funcTable_OBJGSYNCMGR(pThis); +} + +NV_STATUS __nvoc_objCreate_OBJGSYNCMGR(OBJGSYNCMGR **ppThis, Dynamic *pParent, NvU32 createFlags) { + NV_STATUS status; + Object *pParentObj; + OBJGSYNCMGR *pThis; + + pThis = portMemAllocNonPaged(sizeof(OBJGSYNCMGR)); + if (pThis == NULL) return NV_ERR_NO_MEMORY; + + portMemSet(pThis, 0, sizeof(OBJGSYNCMGR)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJGSYNCMGR); + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_OBJGSYNCMGR(pThis); + status = __nvoc_ctor_OBJGSYNCMGR(pThis); + if (status != NV_OK) goto __nvoc_objCreate_OBJGSYNCMGR_cleanup; + + *ppThis = pThis; + return NV_OK; + +__nvoc_objCreate_OBJGSYNCMGR_cleanup: + // do not call destructors here since the constructor already called them + portMemFree(pThis); + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_OBJGSYNCMGR(OBJGSYNCMGR **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + + status = __nvoc_objCreate_OBJGSYNCMGR(ppThis, pParent, createFlags); + + return status; +} + diff --git a/src/nvidia/generated/g_gsync_nvoc.h b/src/nvidia/generated/g_gsync_nvoc.h new file mode 100644 index 000000000..0e260023b --- /dev/null +++ b/src/nvidia/generated/g_gsync_nvoc.h @@ -0,0 +1,297 @@ +#ifndef _G_GSYNC_NVOC_H_ +#define _G_GSYNC_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_gsync_nvoc.h" + +#ifndef GSYNC_H_ +#define GSYNC_H_ + +/* ------------------------ Includes --------------------------------------- */ +#include "core/core.h" +#include "core/system.h" +#include "gpu/external_device/external_device.h" +#include "ctrl/ctrl0000/ctrl0000gsync.h" +#include "ctrl/ctrl30f1.h" +#include "class/cl30f1.h" + +/* ------------------------ Types definitions ------------------------------ */ +typedef enum { + /* Following value is valid for all gsync devices */ + gsync_Connector_None = + NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_NONE, + + /* For P2060 four connectors are index based i.e. 0 to 3 */ +} GSYNCCONNECTOR; + +typedef enum { + gsync_SyncPolarity_RisingEdge = + NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_RISING_EDGE, + gsync_SyncPolarity_FallingEdge = + NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_FALLING_EDGE, + gsync_SyncPolarity_BothEdges = + NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_BOTH_EDGES +} GSYNCSYNCPOLARITY; + +typedef enum { + gsync_VideoMode_None = + NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NONE, + gsync_VideoMode_TTL = + NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_TTL, + gsync_VideoMode_NTSCPALSECAM = + NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NTSCPALSECAM, + gsync_VideoMode_HDTV = + NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_HDTV, + + /* Following value is valid from P2060 only */ + gsync_VideoMode_COMPOSITE = + NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_COMPOSITE +} GSYNCVIDEOMODE; + +typedef enum { + gsync_Signal_RJ45_0 = 0, + gsync_Signal_RJ45_1 = 1, + gsync_Signal_House = 2, + gsync_Signal_Supported = 3 +} GSYNCSYNCSIGNAL; + +typedef enum { + gsync_Status_Refresh = 0, + gsync_Status_HouseSyncIncoming = 1, + gsync_Status_bSyncReady = 2, + gsync_Status_bSwapReady = 3, + gsync_Status_bTiming = 4, + gsync_Status_bStereoSync = 5, + gsync_Status_bHouseSync = 6, + gsync_Status_bPort0Input = 7, + gsync_Status_bPort1Input = 8, + gsync_Status_bPort0Ethernet = 9, + gsync_Status_bPort1Ethernet = 10, + gsync_Status_UniversalFrameCount = 11, + gsync_Status_bInternalSlave = 12, +} GSYNCSTATUS; + +typedef enum { + refRead = 0, + refFetchGet = 1, + refSetCommit = 2, +} REFTYPE; + +typedef NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS GSYNCTIMINGPARAMS; +typedef NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS GSYNCCAPSPARAMS; + +typedef NV_STATUS GsyncShutdownProvider(NvU32); + +typedef NvBool GsyncGpuCanBeMaster (struct OBJGPU *, PDACEXTERNALDEVICE); +typedef NV_STATUS GsyncGetSyncPolarity (struct OBJGPU *, PDACEXTERNALDEVICE, GSYNCSYNCPOLARITY *); +typedef NV_STATUS GsyncSetSyncPolarity (struct OBJGPU *, PDACEXTERNALDEVICE, GSYNCSYNCPOLARITY); +typedef NV_STATUS GsyncGetVideoMode (struct OBJGPU *, PDACEXTERNALDEVICE, GSYNCVIDEOMODE*); +typedef NV_STATUS GsyncSetVideoMode (struct OBJGPU *, PDACEXTERNALDEVICE, GSYNCVIDEOMODE); +typedef NV_STATUS GsyncGetNSync (struct OBJGPU *, PDACEXTERNALDEVICE, NvU32 *); +typedef NV_STATUS GsyncSetNSync (struct OBJGPU *, PDACEXTERNALDEVICE, NvU32); +typedef NV_STATUS GsyncGetSyncSkew (struct OBJGPU *, PDACEXTERNALDEVICE, NvU32 *); +typedef NV_STATUS GsyncSetSyncSkew (struct OBJGPU *, PDACEXTERNALDEVICE, NvU32); +typedef NV_STATUS GsyncGetUseHouse (struct OBJGPU *, PDACEXTERNALDEVICE, NvU32 *); +typedef NV_STATUS GsyncSetUseHouse (struct OBJGPU *, PDACEXTERNALDEVICE, NvU32); +typedef NV_STATUS GsyncGetSyncStartDelay (struct OBJGPU *, PDACEXTERNALDEVICE, NvU32 *); +typedef NV_STATUS GsyncSetSyncStartDelay (struct OBJGPU *, PDACEXTERNALDEVICE, NvU32); +typedef NV_STATUS GsyncGetEmitTestSignal (struct OBJGPU *, PDACEXTERNALDEVICE, NvU32 *); +typedef NV_STATUS GsyncSetEmitTestSignal (struct OBJGPU *, PDACEXTERNALDEVICE, NvU32); +typedef NV_STATUS GsyncGetInterlaceMode (struct OBJGPU *, PDACEXTERNALDEVICE, NvU32 *); +typedef NV_STATUS GsyncSetInterlaceMode (struct OBJGPU *, PDACEXTERNALDEVICE, NvU32); +typedef NV_STATUS GsyncRefSwapBarrier (struct OBJGPU *, PDACEXTERNALDEVICE, REFTYPE, NvBool *); +typedef NV_STATUS GsyncRefSignal (struct OBJGPU *, PDACEXTERNALDEVICE, REFTYPE, GSYNCSYNCSIGNAL, NvBool TestRate, NvU32 *); +typedef NV_STATUS GsyncRefMaster (struct OBJGPU *, PDACEXTERNALDEVICE, REFTYPE, NvU32 *, NvU32 *, NvBool, NvBool); +typedef NV_STATUS GsyncRefSlaves (struct OBJGPU *, PDACEXTERNALDEVICE, REFTYPE, NvU32 *, NvU32 *); +typedef NV_STATUS GsyncGetCplStatus (struct OBJGPU *, PDACEXTERNALDEVICE, GSYNCSTATUS, NvU32 *); +typedef NV_STATUS GsyncSetWatchdog (struct OBJGPU *, PDACEXTERNALDEVICE, NvU32); +typedef NV_STATUS GsyncGetRevision (struct OBJGPU *, PDACEXTERNALDEVICE, GSYNCCAPSPARAMS *); +typedef NV_STATUS GsyncRefMasterable (struct OBJGPU *, PDACEXTERNALDEVICE, REFTYPE, NvU32 *, NvU32 *); +typedef NV_STATUS GsyncGetStereoLockMode (struct OBJGPU *, PDACEXTERNALDEVICE, NvU32 *); +typedef NV_STATUS GsyncSetStereoLockMode (struct OBJGPU *, PDACEXTERNALDEVICE, NvU32); +typedef NV_STATUS GsyncOptimizeTiming (struct OBJGPU *, GSYNCTIMINGPARAMS *); +typedef NV_STATUS GsyncSetMosaic (struct OBJGPU *, PDACEXTERNALDEVICE, NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS *); +typedef NV_STATUS GsyncConfigFlashGsync (struct OBJGPU *, PDACEXTERNALDEVICE, NvU32); +typedef NV_STATUS GsyncGetHouseSyncMode (struct OBJGPU *, PDACEXTERNALDEVICE, NvU8*); +typedef NV_STATUS GsyncSetHouseSyncMode (struct OBJGPU *, PDACEXTERNALDEVICE, NvU8); + +typedef struct GSYNC_HAL_IFACES { + + GsyncGpuCanBeMaster *gsyncGpuCanBeMaster; + GsyncGetSyncPolarity *gsyncGetSyncPolarity; + GsyncSetSyncPolarity *gsyncSetSyncPolarity; + GsyncGetVideoMode *gsyncGetVideoMode; + GsyncSetVideoMode *gsyncSetVideoMode; + GsyncGetNSync *gsyncGetNSync; + GsyncSetNSync *gsyncSetNSync; + GsyncGetSyncSkew *gsyncGetSyncSkew; + GsyncSetSyncSkew *gsyncSetSyncSkew; + GsyncGetUseHouse *gsyncGetUseHouse; + GsyncSetUseHouse *gsyncSetUseHouse; + GsyncGetSyncStartDelay *gsyncGetSyncStartDelay; + GsyncSetSyncStartDelay *gsyncSetSyncStartDelay; + GsyncGetEmitTestSignal *gsyncGetEmitTestSignal; + GsyncSetEmitTestSignal *gsyncSetEmitTestSignal; + GsyncGetInterlaceMode *gsyncGetInterlaceMode; + GsyncSetInterlaceMode *gsyncSetInterlaceMode; + GsyncRefSwapBarrier *gsyncRefSwapBarrier; + GsyncRefSignal *gsyncRefSignal; + GsyncRefMaster *gsyncRefMaster; + GsyncRefSlaves *gsyncRefSlaves; + GsyncGetCplStatus *gsyncGetCplStatus; + GsyncSetWatchdog *gsyncSetWatchdog; + GsyncGetRevision *gsyncGetRevision; + GsyncRefMasterable *gsyncRefMasterable; + GsyncOptimizeTiming *gsyncOptimizeTiming; + GsyncGetStereoLockMode *gsyncGetStereoLockMode; + GsyncSetStereoLockMode *gsyncSetStereoLockMode; + GsyncSetMosaic *gsyncSetMosaic; + GsyncConfigFlashGsync *gsyncConfigFlashGsync; + GsyncGetHouseSyncMode *gsyncGetHouseSyncMode; + GsyncSetHouseSyncMode *gsyncSetHouseSyncMode; + +} GSYNC_HAL_IFACES; + +typedef struct _def_gsync { + NvU32 gsyncId; + NvU32 gpuCount; + NvU32 connectorCount; + struct { + NvU32 gpuId; + NvU32 connector; + NvU32 proxyGpuId; + } gpus[NV30F1_CTRL_MAX_GPUS_PER_GSYNC]; + + PDACEXTERNALDEVICE pExtDev; + + // + // Set for the gsync objects lifetime until + // any gsyncSetControlWatchdog has come in + // as this indicated client's are taking care + // and don't want any automatic solution. + // + NvBool bAutomaticWatchdogScheduling; + NvBool bDoEventFiltering; + + // Bitmask of Masterable GPU connectors. + NvU8 masterableGpuConnectors; + + // gsync hal + GSYNC_HAL_IFACES gsyncHal; + +} OBJGSYNC, *POBJGSYNC; + +/* ------------------------ Macros & Defines ------------------------------- */ +#define FLIPLOCK_LSR_MIN_TIME_FOR_SAWP_BARRIER_NV50 0x3FF //max LSR_MIN_TIME value for nv50 +#define FLIPLOCK_LSR_MIN_TIME_FOR_SAWP_BARRIER_GF100 0x3FF //max LSR_MIN_TIME value for gf100 +#define FLIPLOCK_LSR_MIN_TIME_FOR_SAWP_BARRIER_V02 0x3FF //max LSR_MIN_TIME value for gf11x+ + +typedef struct OBJGSYNCMGR *POBJGSYNCMGR; + +#ifdef NVOC_GSYNC_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct OBJGSYNCMGR { + const struct NVOC_RTTI *__nvoc_rtti; + struct Object __nvoc_base_Object; + struct Object *__nvoc_pbase_Object; + struct OBJGSYNCMGR *__nvoc_pbase_OBJGSYNCMGR; + NvU32 gsyncCount; + OBJGSYNC gsyncTable[4]; +}; + +#ifndef __NVOC_CLASS_OBJGSYNCMGR_TYPEDEF__ +#define __NVOC_CLASS_OBJGSYNCMGR_TYPEDEF__ +typedef struct OBJGSYNCMGR OBJGSYNCMGR; +#endif /* __NVOC_CLASS_OBJGSYNCMGR_TYPEDEF__ */ + +#ifndef __nvoc_class_id_OBJGSYNCMGR +#define __nvoc_class_id_OBJGSYNCMGR 0xd07fd0 +#endif /* __nvoc_class_id_OBJGSYNCMGR */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGSYNCMGR; + +#define __staticCast_OBJGSYNCMGR(pThis) \ + ((pThis)->__nvoc_pbase_OBJGSYNCMGR) + +#ifdef __nvoc_gsync_h_disabled +#define __dynamicCast_OBJGSYNCMGR(pThis) ((OBJGSYNCMGR*)NULL) +#else //__nvoc_gsync_h_disabled +#define __dynamicCast_OBJGSYNCMGR(pThis) \ + ((OBJGSYNCMGR*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(OBJGSYNCMGR))) +#endif //__nvoc_gsync_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_OBJGSYNCMGR(OBJGSYNCMGR**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_OBJGSYNCMGR(OBJGSYNCMGR**, Dynamic*, NvU32); +#define __objCreate_OBJGSYNCMGR(ppNewObj, pParent, createFlags) \ + __nvoc_objCreate_OBJGSYNCMGR((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) + +NV_STATUS gsyncmgrConstruct_IMPL(struct OBJGSYNCMGR *arg_pGsyncmgr); + +#define __nvoc_gsyncmgrConstruct(arg_pGsyncmgr) gsyncmgrConstruct_IMPL(arg_pGsyncmgr) +void gsyncmgrDestruct_IMPL(struct OBJGSYNCMGR *pGsyncmgr); + +#define __nvoc_gsyncmgrDestruct(pGsyncmgr) gsyncmgrDestruct_IMPL(pGsyncmgr) +#undef PRIVATE_FIELD + + + +NV_STATUS gsyncGetAttachedIds(NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS *); +NV_STATUS gsyncGetIdInfo(NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS *); +NV_STATUS gsyncAttachGpu(PDACEXTERNALDEVICE pExtDev, struct OBJGPU *pGpu, + GSYNCCONNECTOR con, struct OBJGPU *pProxyGpu, + DAC_EXTERNAL_DEVICES externalDevice); +NV_STATUS gsyncRemoveGpu(struct OBJGPU *pGpu); +NvBool gsyncIsInstanceValid(NvU32 gsyncInst); +struct OBJGPU *gsyncGetMasterableGpuByInstance(NvU32 gsyncInst); +NV_STATUS gsyncSignalServiceRequested(NvU32 gsyncInst, NvU32 eventFlags, NvU32 iface); +NvU32 gsyncGetGsyncInstance(struct OBJGPU *pGpu); +NvU32 gsyncFilterEvents(NvU32, NvU32); +NvU32 gsyncConvertNewEventToOldEventNum(NvU32); +NvBool gsyncAreAllGpusInConfigAttachedToSameGsyncBoard(struct OBJGPU **pGpus, NvU32 gpuCount); + +OBJGSYNC *gsyncmgrGetGsync(struct OBJGPU *); + +#ifdef DEBUG +void gsyncDbgPrintGsyncEvents(NvU32 DebugLevel, NvU32 events, NvU32 iface); +#else +#define gsyncDbgPrintGsyncEvents(DebugLevel, events, iface) +#endif + +#endif // GSYNC_H_ + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_GSYNC_NVOC_H_ diff --git a/src/nvidia/generated/g_hal.h b/src/nvidia/generated/g_hal.h index 0d8243635..4d032ed45 100644 --- a/src/nvidia/generated/g_hal.h +++ b/src/nvidia/generated/g_hal.h @@ -121,6 +121,8 @@ typedef enum HAL_IMPL_AD102, HAL_IMPL_AD103, HAL_IMPL_AD104, + HAL_IMPL_AD106, + HAL_IMPL_AD107, HAL_IMPL_GH100, HAL_IMPL_T001_FERMI_NOT_EXIST, HAL_IMPL_T124, @@ -155,6 +157,8 @@ typedef enum { HAL_IMPL_AD102, "AD102" }, \ { HAL_IMPL_AD103, "AD103" }, \ { HAL_IMPL_AD104, "AD104" }, \ + { HAL_IMPL_AD106, "AD106" }, \ + { HAL_IMPL_AD107, "AD107" }, \ { HAL_IMPL_GH100, "GH100" } diff --git a/src/nvidia/generated/g_hal_archimpl.h b/src/nvidia/generated/g_hal_archimpl.h index be9fd50a8..47ffbec39 100644 --- a/src/nvidia/generated/g_hal_archimpl.h +++ b/src/nvidia/generated/g_hal_archimpl.h @@ -5,7 +5,7 @@ // Profile: shipping-gpus-openrm // Template: templates/gt_hal_archimpl.h // -// Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +// Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X // #ifndef _G_RMCFG_HAL_ARCHIMPL_H_ @@ -80,6 +80,8 @@ const struct ChipID { NV_PMC_BOOT_0_ARCHITECTURE_AD100, NV_PMC_BOOT_0_IMPLEMENTATION_2, 0x0 } , // AD102 { NV_PMC_BOOT_0_ARCHITECTURE_AD100, NV_PMC_BOOT_0_IMPLEMENTATION_3, 0x0 } , // AD103 { NV_PMC_BOOT_0_ARCHITECTURE_AD100, NV_PMC_BOOT_0_IMPLEMENTATION_4, 0x0 } , // AD104 + { NV_PMC_BOOT_0_ARCHITECTURE_AD100, NV_PMC_BOOT_0_IMPLEMENTATION_6, 0x0 } , // AD106 + { NV_PMC_BOOT_0_ARCHITECTURE_AD100, NV_PMC_BOOT_0_IMPLEMENTATION_7, 0x0 } , // AD107 { NV_PMC_BOOT_0_ARCHITECTURE_GH100, NV_PMC_BOOT_0_IMPLEMENTATION_0, 0x0 } , // GH100 { 0x0, 0x0, 0x0 } , // T001_FERMI_NOT_EXIST (disabled) { 0x0, 0x0, 0x0 } , // T124 (disabled) diff --git a/src/nvidia/generated/g_hal_mgr_nvoc.h b/src/nvidia/generated/g_hal_mgr_nvoc.h index 8485dce72..05ea44e4f 100644 --- a/src/nvidia/generated/g_hal_mgr_nvoc.h +++ b/src/nvidia/generated/g_hal_mgr_nvoc.h @@ -63,7 +63,7 @@ struct OBJHALMGR { struct Object __nvoc_base_Object; struct Object *__nvoc_pbase_Object; struct OBJHALMGR *__nvoc_pbase_OBJHALMGR; - struct OBJHAL *pHalList[64]; + struct OBJHAL *pHalList[66]; }; #ifndef __NVOC_CLASS_OBJHALMGR_TYPEDEF__ @@ -95,10 +95,13 @@ NV_STATUS __nvoc_objCreate_OBJHALMGR(OBJHALMGR**, Dynamic*, NvU32); __nvoc_objCreate_OBJHALMGR((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) NV_STATUS halmgrConstruct_IMPL(struct OBJHALMGR *arg_); + #define __nvoc_halmgrConstruct(arg_) halmgrConstruct_IMPL(arg_) void halmgrDestruct_IMPL(struct OBJHALMGR *arg0); + #define __nvoc_halmgrDestruct(arg0) halmgrDestruct_IMPL(arg0) NV_STATUS halmgrCreateHal_IMPL(struct OBJHALMGR *arg0, NvU32 arg1); + #ifdef __nvoc_hal_mgr_h_disabled static inline NV_STATUS halmgrCreateHal(struct OBJHALMGR *arg0, NvU32 arg1) { NV_ASSERT_FAILED_PRECOMP("OBJHALMGR was disabled!"); @@ -109,6 +112,7 @@ static inline NV_STATUS halmgrCreateHal(struct OBJHALMGR *arg0, NvU32 arg1) { #endif //__nvoc_hal_mgr_h_disabled NV_STATUS halmgrGetHalForGpu_IMPL(struct OBJHALMGR *arg0, NvU32 arg1, NvU32 arg2, NvU32 *arg3); + #ifdef __nvoc_hal_mgr_h_disabled static inline NV_STATUS halmgrGetHalForGpu(struct OBJHALMGR *arg0, NvU32 arg1, NvU32 arg2, NvU32 *arg3) { NV_ASSERT_FAILED_PRECOMP("OBJHALMGR was disabled!"); @@ -119,6 +123,7 @@ static inline NV_STATUS halmgrGetHalForGpu(struct OBJHALMGR *arg0, NvU32 arg1, N #endif //__nvoc_hal_mgr_h_disabled struct OBJHAL *halmgrGetHal_IMPL(struct OBJHALMGR *arg0, NvU32 arg1); + #ifdef __nvoc_hal_mgr_h_disabled static inline struct OBJHAL *halmgrGetHal(struct OBJHALMGR *arg0, NvU32 arg1) { NV_ASSERT_FAILED_PRECOMP("OBJHALMGR was disabled!"); diff --git a/src/nvidia/generated/g_hal_nvoc.h b/src/nvidia/generated/g_hal_nvoc.h index 4fa2daa8d..5d3267900 100644 --- a/src/nvidia/generated/g_hal_nvoc.h +++ b/src/nvidia/generated/g_hal_nvoc.h @@ -120,6 +120,7 @@ NV_STATUS __nvoc_objCreate_OBJHAL(OBJHAL**, Dynamic*, NvU32); __nvoc_objCreate_OBJHAL((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) PMODULEDESCRIPTOR objhalGetModuleDescriptor_IMPL(struct OBJHAL *pHal); + #ifdef __nvoc_hal_h_disabled static inline PMODULEDESCRIPTOR objhalGetModuleDescriptor(struct OBJHAL *pHal) { NV_ASSERT_FAILED_PRECOMP("OBJHAL was disabled!"); diff --git a/src/nvidia/generated/g_hal_private.h b/src/nvidia/generated/g_hal_private.h index 9d7df66e0..f90562ec9 100644 --- a/src/nvidia/generated/g_hal_private.h +++ b/src/nvidia/generated/g_hal_private.h @@ -5,7 +5,7 @@ // Profile: shipping-gpus-openrm // Template: templates/gt_hal_private.h // -// Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +// Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X // // @@ -55,6 +55,8 @@ # define RMCFG_HAL_SETUP_AD102 1 # define RMCFG_HAL_SETUP_AD103 1 # define RMCFG_HAL_SETUP_AD104 1 +# define RMCFG_HAL_SETUP_AD106 1 +# define RMCFG_HAL_SETUP_AD107 1 #endif // AD10X #if defined(RMCFG_HAL_SETUP_GH10X) @@ -64,7 +66,6 @@ #endif // RMCFG_ENGINE_SETUP // pull in private headers for each engine -#include "g_os_private.h" #include "g_rpc_private.h" @@ -285,6 +286,36 @@ NV_STATUS registerHalModule_AD104(void) #endif // AD10X or AD104 +#if defined(RMCFG_HAL_SETUP_AD106) + +static const HAL_IFACE_SETUP halIface_AD106 = { + + rpcHalIfacesSetup_AD106, + +}; + +NV_STATUS registerHalModule_AD106(void) +{ + return registerHalModule(HAL_IMPL_AD106, &halIface_AD106); +} + +#endif // AD10X or AD106 + +#if defined(RMCFG_HAL_SETUP_AD107) + +static const HAL_IFACE_SETUP halIface_AD107 = { + + rpcHalIfacesSetup_AD107, + +}; + +NV_STATUS registerHalModule_AD107(void) +{ + return registerHalModule(HAL_IMPL_AD107, &halIface_AD107); +} + +#endif // AD10X or AD107 + #if defined(RMCFG_HAL_SETUP_GH100) static const HAL_IFACE_SETUP halIface_GH100 = { diff --git a/src/nvidia/generated/g_hal_register.h b/src/nvidia/generated/g_hal_register.h index d48b6eec6..ce3b0beda 100644 --- a/src/nvidia/generated/g_hal_register.h +++ b/src/nvidia/generated/g_hal_register.h @@ -5,7 +5,7 @@ // Profile: shipping-gpus-openrm // Template: templates/gt_hal_register.h // -// Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +// Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X // #ifndef _G_RMCFG_HAL_REGISTER_H_ @@ -90,6 +90,8 @@ static NV_STATUS NV_INLINE REGISTER_GA10X_HALS(void) NV_STATUS registerHalModule_AD102(void); NV_STATUS registerHalModule_AD103(void); NV_STATUS registerHalModule_AD104(void); +NV_STATUS registerHalModule_AD106(void); +NV_STATUS registerHalModule_AD107(void); static NV_STATUS NV_INLINE REGISTER_AD10X_HALS(void) { @@ -107,6 +109,14 @@ static NV_STATUS NV_INLINE REGISTER_AD10X_HALS(void) if (rmStatus != NV_OK) return rmStatus; + rmStatus = registerHalModule_AD106(); + if (rmStatus != NV_OK) + return rmStatus; + + rmStatus = registerHalModule_AD107(); + if (rmStatus != NV_OK) + return rmStatus; + return NV_OK; } diff --git a/src/nvidia/generated/g_hal_stubs.h b/src/nvidia/generated/g_hal_stubs.h index 01607b635..e02bacb06 100644 --- a/src/nvidia/generated/g_hal_stubs.h +++ b/src/nvidia/generated/g_hal_stubs.h @@ -5,14 +5,13 @@ // Profile: shipping-gpus-openrm // Template: templates/gt_hal_stubs.h // -// Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +// Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X // #ifndef _G_RMCFG_HAL_STUBS_H_ #define _G_RMCFG_HAL_STUBS_H_ // pull in private headers for each engine -#include "g_os_private.h" #include "g_rpc_private.h" @@ -551,6 +550,16 @@ NV_STATUS gpioWritePinHwEnum_MISSING( return NV_ERR_NOT_SUPPORTED; } +// GPIO:hal:CHECK_PROTECTION - GPIO disabled +NV_STATUS gpioCheckProtection_MISSING( + POBJGPIO pGpio, + NvU32 gpioPin, + NvBool *pbIsProtected +) +{ + return NV_ERR_NOT_SUPPORTED; +} + // GPIO:hal:READ_INPUT - GPIO disabled NV_STATUS gpioReadInput_FWCLIENT( POBJGPIO pGpio, @@ -655,7 +664,7 @@ NvU32 gpioInitAndGetPinNum_FWCLIENT( return (NvU32) 0; } -// RPC:hal:VGPU_PF_REG_READ32 - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +// RPC:hal:VGPU_PF_REG_READ32 - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X NV_STATUS rpcVgpuPfRegRead32_STUB( POBJGPU pGpu, POBJRPC pRpc, @@ -667,7 +676,7 @@ NV_STATUS rpcVgpuPfRegRead32_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:DUMP_PROTOBUF_COMPONENT - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +// RPC:hal:DUMP_PROTOBUF_COMPONENT - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X NV_STATUS rpcDumpProtobufComponent_STUB( POBJGPU pGpu, POBJRPC pRpc, @@ -679,7 +688,7 @@ NV_STATUS rpcDumpProtobufComponent_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:ALLOC_MEMORY - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +// RPC:hal:ALLOC_MEMORY - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X NV_STATUS rpcAllocMemory_STUB( POBJGPU pGpu, POBJRPC pRpc, @@ -694,7 +703,7 @@ NV_STATUS rpcAllocMemory_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:GPU_EXEC_REG_OPS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +// RPC:hal:GPU_EXEC_REG_OPS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X NV_STATUS rpcGpuExecRegOps_STUB( POBJGPU pGpu, POBJRPC pRpc, @@ -707,7 +716,7 @@ NV_STATUS rpcGpuExecRegOps_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:RMFS_INIT - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +// RPC:hal:RMFS_INIT - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X NV_STATUS rpcRmfsInit_STUB( POBJGPU pGpu, POBJRPC pRpc, @@ -717,7 +726,7 @@ NV_STATUS rpcRmfsInit_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:UNSET_PAGE_DIRECTORY - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +// RPC:hal:UNSET_PAGE_DIRECTORY - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X NV_STATUS rpcUnsetPageDirectory_STUB( POBJGPU pGpu, POBJRPC pRpc, @@ -729,7 +738,7 @@ NV_STATUS rpcUnsetPageDirectory_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:GET_GSP_STATIC_INFO - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +// RPC:hal:GET_GSP_STATIC_INFO - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X NV_STATUS rpcGetGspStaticInfo_STUB( POBJGPU pGpu, POBJRPC pRpc @@ -738,7 +747,7 @@ NV_STATUS rpcGetGspStaticInfo_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:GSP_SET_SYSTEM_INFO - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +// RPC:hal:GSP_SET_SYSTEM_INFO - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X NV_STATUS rpcGspSetSystemInfo_STUB( POBJGPU pGpu, POBJRPC pRpc @@ -747,7 +756,7 @@ NV_STATUS rpcGspSetSystemInfo_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:RMFS_CLEANUP - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +// RPC:hal:RMFS_CLEANUP - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X NV_STATUS rpcRmfsCleanup_STUB( POBJGPU pGpu, POBJRPC pRpc @@ -756,7 +765,7 @@ NV_STATUS rpcRmfsCleanup_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:SET_PAGE_DIRECTORY - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +// RPC:hal:SET_PAGE_DIRECTORY - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X NV_STATUS rpcSetPageDirectory_STUB( POBJGPU pGpu, POBJRPC pRpc, @@ -768,7 +777,7 @@ NV_STATUS rpcSetPageDirectory_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:UNLOADING_GUEST_DRIVER - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +// RPC:hal:UNLOADING_GUEST_DRIVER - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X NV_STATUS rpcUnloadingGuestDriver_STUB( POBJGPU pGpu, POBJRPC pRpc, @@ -780,7 +789,7 @@ NV_STATUS rpcUnloadingGuestDriver_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:SET_REGISTRY - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +// RPC:hal:SET_REGISTRY - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X NV_STATUS rpcSetRegistry_STUB( POBJGPU pGpu, POBJRPC pRpc @@ -789,7 +798,7 @@ NV_STATUS rpcSetRegistry_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:RMFS_CLOSE_QUEUE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +// RPC:hal:RMFS_CLOSE_QUEUE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X NV_STATUS rpcRmfsCloseQueue_STUB( POBJGPU pGpu, POBJRPC pRpc @@ -798,7 +807,7 @@ NV_STATUS rpcRmfsCloseQueue_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:GET_STATIC_INFO - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +// RPC:hal:GET_STATIC_INFO - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X NV_STATUS rpcGetStaticInfo_STUB( POBJGPU pGpu, POBJRPC pRpc @@ -807,7 +816,7 @@ NV_STATUS rpcGetStaticInfo_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:IDLE_CHANNELS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +// RPC:hal:IDLE_CHANNELS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X NV_STATUS rpcIdleChannels_STUB( OBJGPU *pArg1, POBJRPC pRpc, @@ -822,7 +831,7 @@ NV_STATUS rpcIdleChannels_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:UPDATE_BAR_PDE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +// RPC:hal:UPDATE_BAR_PDE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X NV_STATUS rpcUpdateBarPde_STUB( POBJGPU pGpu, POBJRPC pRpc, @@ -834,7 +843,7 @@ NV_STATUS rpcUpdateBarPde_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:MAP_MEMORY_DMA - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +// RPC:hal:MAP_MEMORY_DMA - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X NV_STATUS rpcMapMemoryDma_STUB( POBJGPU pGpu, POBJRPC pRpc, @@ -851,7 +860,7 @@ NV_STATUS rpcMapMemoryDma_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:UNMAP_MEMORY_DMA - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +// RPC:hal:UNMAP_MEMORY_DMA - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X NV_STATUS rpcUnmapMemoryDma_STUB( POBJGPU pGpu, POBJRPC pRpc, @@ -866,7 +875,7 @@ NV_STATUS rpcUnmapMemoryDma_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:RMFS_TEST - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +// RPC:hal:RMFS_TEST - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X NV_STATUS rpcRmfsTest_STUB( POBJGPU pGpu, POBJRPC pRpc, @@ -879,6 +888,17 @@ NV_STATUS rpcRmfsTest_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS - RPCSTRUCTURECOPY disabled +NV_STATUS deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_STUB( + NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + // RPCSTRUCTURECOPY:hal:IGRP_IP_VERSIONS_GET_INFO - RPCSTRUCTURECOPY disabled NV_STATUS rpcstructurecopy_iGrp_ipVersions_getInfo_STUB( IGRP_IP_VERSIONS_TABLE_INFO *pArg1 diff --git a/src/nvidia/generated/g_hda_codec_api_nvoc.c b/src/nvidia/generated/g_hda_codec_api_nvoc.c index 4d72d26fd..fe4fed75b 100644 --- a/src/nvidia/generated/g_hda_codec_api_nvoc.c +++ b/src/nvidia/generated/g_hda_codec_api_nvoc.c @@ -165,6 +165,10 @@ static NV_STATUS __nvoc_thunk_RsResource_hdacodecUnmapFrom(struct Hdacodec *pRes return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_hdacodecIsDuplicate(struct Hdacodec *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_hdacodecControl_Epilogue(struct Hdacodec *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RmResource.offset), pCallContext, pParams); } @@ -255,6 +259,8 @@ static void __nvoc_init_funcTable_Hdacodec_1(Hdacodec *pThis) { pThis->__hdacodecUnmapFrom__ = &__nvoc_thunk_RsResource_hdacodecUnmapFrom; + pThis->__hdacodecIsDuplicate__ = &__nvoc_thunk_RsResource_hdacodecIsDuplicate; + pThis->__hdacodecControl_Epilogue__ = &__nvoc_thunk_RmResource_hdacodecControl_Epilogue; pThis->__hdacodecControlLookup__ = &__nvoc_thunk_RsResource_hdacodecControlLookup; diff --git a/src/nvidia/generated/g_hda_codec_api_nvoc.h b/src/nvidia/generated/g_hda_codec_api_nvoc.h index 39aebb188..22590ee9e 100644 --- a/src/nvidia/generated/g_hda_codec_api_nvoc.h +++ b/src/nvidia/generated/g_hda_codec_api_nvoc.h @@ -72,6 +72,7 @@ struct Hdacodec { NV_STATUS (*__hdacodecInternalControlForward__)(struct Hdacodec *, NvU32, void *, NvU32); void (*__hdacodecPreDestruct__)(struct Hdacodec *); NV_STATUS (*__hdacodecUnmapFrom__)(struct Hdacodec *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__hdacodecIsDuplicate__)(struct Hdacodec *, NvHandle, NvBool *); void (*__hdacodecControl_Epilogue__)(struct Hdacodec *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__hdacodecControlLookup__)(struct Hdacodec *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__hdacodecMap__)(struct Hdacodec *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -124,6 +125,7 @@ NV_STATUS __nvoc_objCreate_Hdacodec(Hdacodec**, Dynamic*, NvU32, struct CALL_CON #define hdacodecInternalControlForward(pGpuResource, command, pParams, size) hdacodecInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define hdacodecPreDestruct(pResource) hdacodecPreDestruct_DISPATCH(pResource) #define hdacodecUnmapFrom(pResource, pParams) hdacodecUnmapFrom_DISPATCH(pResource, pParams) +#define hdacodecIsDuplicate(pResource, hMemory, pDuplicate) hdacodecIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define hdacodecControl_Epilogue(pResource, pCallContext, pParams) hdacodecControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define hdacodecControlLookup(pResource, pParams, ppEntry) hdacodecControlLookup_DISPATCH(pResource, pParams, ppEntry) #define hdacodecMap(pGpuResource, pCallContext, pParams, pCpuMapping) hdacodecMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -200,6 +202,10 @@ static inline NV_STATUS hdacodecUnmapFrom_DISPATCH(struct Hdacodec *pResource, R return pResource->__hdacodecUnmapFrom__(pResource, pParams); } +static inline NV_STATUS hdacodecIsDuplicate_DISPATCH(struct Hdacodec *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__hdacodecIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void hdacodecControl_Epilogue_DISPATCH(struct Hdacodec *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__hdacodecControl_Epilogue__(pResource, pCallContext, pParams); } @@ -217,6 +223,7 @@ static inline NvBool hdacodecAccessCallback_DISPATCH(struct Hdacodec *pResource, } NV_STATUS hdacodecConstruct_IMPL(struct Hdacodec *arg_pHdacodecApi, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_hdacodecConstruct(arg_pHdacodecApi, arg_pCallContext, arg_pParams) hdacodecConstruct_IMPL(arg_pHdacodecApi, arg_pCallContext, arg_pParams) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_heap_nvoc.h b/src/nvidia/generated/g_heap_nvoc.h index 4b7164947..91a9ab319 100644 --- a/src/nvidia/generated/g_heap_nvoc.h +++ b/src/nvidia/generated/g_heap_nvoc.h @@ -346,6 +346,7 @@ NV_STATUS __nvoc_objCreate_Heap(Heap**, Dynamic*, NvU32); __nvoc_objCreate_Heap((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) NV_STATUS heapInit_IMPL(struct OBJGPU *arg0, struct Heap *arg1, NvU64 arg2, NvU64 arg3, HEAP_TYPE_INTERNAL arg4, NvU32 arg5, void *arg6); + #ifdef __nvoc_heap_h_disabled static inline NV_STATUS heapInit(struct OBJGPU *arg0, struct Heap *arg1, NvU64 arg2, NvU64 arg3, HEAP_TYPE_INTERNAL arg4, NvU32 arg5, void *arg6) { NV_ASSERT_FAILED_PRECOMP("Heap was disabled!"); @@ -356,6 +357,7 @@ static inline NV_STATUS heapInit(struct OBJGPU *arg0, struct Heap *arg1, NvU64 a #endif //__nvoc_heap_h_disabled NV_STATUS heapInitInternal_IMPL(struct OBJGPU *arg0, struct Heap *arg1, NvU64 arg2, NvU64 arg3, HEAP_TYPE_INTERNAL arg4, void *arg5); + #ifdef __nvoc_heap_h_disabled static inline NV_STATUS heapInitInternal(struct OBJGPU *arg0, struct Heap *arg1, NvU64 arg2, NvU64 arg3, HEAP_TYPE_INTERNAL arg4, void *arg5) { NV_ASSERT_FAILED_PRECOMP("Heap was disabled!"); @@ -366,8 +368,10 @@ static inline NV_STATUS heapInitInternal(struct OBJGPU *arg0, struct Heap *arg1, #endif //__nvoc_heap_h_disabled void heapDestruct_IMPL(struct Heap *arg0); + #define __nvoc_heapDestruct(arg0) heapDestruct_IMPL(arg0) NV_STATUS heapAlloc_IMPL(struct OBJGPU *arg0, NvHandle arg1, struct Heap *arg2, MEMORY_ALLOCATION_REQUEST *arg3, NvHandle arg4, OBJHEAP_ALLOC_DATA *arg5, FB_ALLOC_INFO *arg6, HWRESOURCE_INFO **arg7, NvBool *arg8, NvBool arg9, NvBool arg10); + #ifdef __nvoc_heap_h_disabled static inline NV_STATUS heapAlloc(struct OBJGPU *arg0, NvHandle arg1, struct Heap *arg2, MEMORY_ALLOCATION_REQUEST *arg3, NvHandle arg4, OBJHEAP_ALLOC_DATA *arg5, FB_ALLOC_INFO *arg6, HWRESOURCE_INFO **arg7, NvBool *arg8, NvBool arg9, NvBool arg10) { NV_ASSERT_FAILED_PRECOMP("Heap was disabled!"); @@ -378,6 +382,7 @@ static inline NV_STATUS heapAlloc(struct OBJGPU *arg0, NvHandle arg1, struct Hea #endif //__nvoc_heap_h_disabled NV_STATUS heapFree_IMPL(struct OBJGPU *pGpu, struct Heap *pHeap, NvU32 owner, MEMORY_DESCRIPTOR *pMemDesc); + #ifdef __nvoc_heap_h_disabled static inline NV_STATUS heapFree(struct OBJGPU *pGpu, struct Heap *pHeap, NvU32 owner, MEMORY_DESCRIPTOR *pMemDesc) { NV_ASSERT_FAILED_PRECOMP("Heap was disabled!"); @@ -388,6 +393,7 @@ static inline NV_STATUS heapFree(struct OBJGPU *pGpu, struct Heap *pHeap, NvU32 #endif //__nvoc_heap_h_disabled NV_STATUS heapReference_IMPL(struct OBJGPU *arg0, struct Heap *arg1, NvU32 arg2, MEMORY_DESCRIPTOR *arg3); + #ifdef __nvoc_heap_h_disabled static inline NV_STATUS heapReference(struct OBJGPU *arg0, struct Heap *arg1, NvU32 arg2, MEMORY_DESCRIPTOR *arg3) { NV_ASSERT_FAILED_PRECOMP("Heap was disabled!"); @@ -398,6 +404,7 @@ static inline NV_STATUS heapReference(struct OBJGPU *arg0, struct Heap *arg1, Nv #endif //__nvoc_heap_h_disabled NV_STATUS heapInfo_IMPL(struct Heap *arg0, NvU64 *arg1, NvU64 *arg2, NvU64 *arg3, NvU64 *arg4, NvU64 *arg5); + #ifdef __nvoc_heap_h_disabled static inline NV_STATUS heapInfo(struct Heap *arg0, NvU64 *arg1, NvU64 *arg2, NvU64 *arg3, NvU64 *arg4, NvU64 *arg5) { NV_ASSERT_FAILED_PRECOMP("Heap was disabled!"); @@ -408,6 +415,7 @@ static inline NV_STATUS heapInfo(struct Heap *arg0, NvU64 *arg1, NvU64 *arg2, Nv #endif //__nvoc_heap_h_disabled NV_STATUS heapInfoTypeAllocBlocks_IMPL(struct Heap *arg0, NvU32 arg1, NvU64 *arg2); + #ifdef __nvoc_heap_h_disabled static inline NV_STATUS heapInfoTypeAllocBlocks(struct Heap *arg0, NvU32 arg1, NvU64 *arg2) { NV_ASSERT_FAILED_PRECOMP("Heap was disabled!"); @@ -418,6 +426,7 @@ static inline NV_STATUS heapInfoTypeAllocBlocks(struct Heap *arg0, NvU32 arg1, N #endif //__nvoc_heap_h_disabled NV_STATUS heapGetSize_IMPL(struct Heap *arg0, NvU64 *arg1); + #ifdef __nvoc_heap_h_disabled static inline NV_STATUS heapGetSize(struct Heap *arg0, NvU64 *arg1) { NV_ASSERT_FAILED_PRECOMP("Heap was disabled!"); @@ -428,6 +437,7 @@ static inline NV_STATUS heapGetSize(struct Heap *arg0, NvU64 *arg1) { #endif //__nvoc_heap_h_disabled NV_STATUS heapGetFree_IMPL(struct Heap *arg0, NvU64 *arg1); + #ifdef __nvoc_heap_h_disabled static inline NV_STATUS heapGetFree(struct Heap *arg0, NvU64 *arg1) { NV_ASSERT_FAILED_PRECOMP("Heap was disabled!"); @@ -438,6 +448,7 @@ static inline NV_STATUS heapGetFree(struct Heap *arg0, NvU64 *arg1) { #endif //__nvoc_heap_h_disabled NV_STATUS heapGetUsableSize_IMPL(struct Heap *arg0, NvU64 *arg1); + #ifdef __nvoc_heap_h_disabled static inline NV_STATUS heapGetUsableSize(struct Heap *arg0, NvU64 *arg1) { NV_ASSERT_FAILED_PRECOMP("Heap was disabled!"); @@ -448,6 +459,7 @@ static inline NV_STATUS heapGetUsableSize(struct Heap *arg0, NvU64 *arg1) { #endif //__nvoc_heap_h_disabled NV_STATUS heapGetBase_IMPL(struct Heap *arg0, NvU64 *arg1); + #ifdef __nvoc_heap_h_disabled static inline NV_STATUS heapGetBase(struct Heap *arg0, NvU64 *arg1) { NV_ASSERT_FAILED_PRECOMP("Heap was disabled!"); @@ -458,6 +470,7 @@ static inline NV_STATUS heapGetBase(struct Heap *arg0, NvU64 *arg1) { #endif //__nvoc_heap_h_disabled NV_STATUS heapGetBlock_IMPL(struct Heap *arg0, NvU64 arg1, struct MEM_BLOCK **arg2); + #ifdef __nvoc_heap_h_disabled static inline NV_STATUS heapGetBlock(struct Heap *arg0, NvU64 arg1, struct MEM_BLOCK **arg2) { NV_ASSERT_FAILED_PRECOMP("Heap was disabled!"); @@ -468,6 +481,7 @@ static inline NV_STATUS heapGetBlock(struct Heap *arg0, NvU64 arg1, struct MEM_B #endif //__nvoc_heap_h_disabled NV_STATUS heapGetBlockHandle_IMPL(struct Heap *arg0, NvU32 arg1, NvU32 arg2, NvU64 arg3, NvBool arg4, NvHandle *arg5); + #ifdef __nvoc_heap_h_disabled static inline NV_STATUS heapGetBlockHandle(struct Heap *arg0, NvU32 arg1, NvU32 arg2, NvU64 arg3, NvBool arg4, NvHandle *arg5) { NV_ASSERT_FAILED_PRECOMP("Heap was disabled!"); @@ -478,6 +492,7 @@ static inline NV_STATUS heapGetBlockHandle(struct Heap *arg0, NvU32 arg1, NvU32 #endif //__nvoc_heap_h_disabled NvU32 heapGetNumBlocks_IMPL(struct Heap *arg0); + #ifdef __nvoc_heap_h_disabled static inline NvU32 heapGetNumBlocks(struct Heap *arg0) { NV_ASSERT_FAILED_PRECOMP("Heap was disabled!"); @@ -488,6 +503,7 @@ static inline NvU32 heapGetNumBlocks(struct Heap *arg0) { #endif //__nvoc_heap_h_disabled NV_STATUS heapGetBlockInfo_IMPL(struct Heap *arg0, NvU32 arg1, NVOS32_HEAP_DUMP_BLOCK *arg2); + #ifdef __nvoc_heap_h_disabled static inline NV_STATUS heapGetBlockInfo(struct Heap *arg0, NvU32 arg1, NVOS32_HEAP_DUMP_BLOCK *arg2) { NV_ASSERT_FAILED_PRECOMP("Heap was disabled!"); @@ -498,6 +514,7 @@ static inline NV_STATUS heapGetBlockInfo(struct Heap *arg0, NvU32 arg1, NVOS32_H #endif //__nvoc_heap_h_disabled NV_STATUS heapAllocHint_IMPL(struct OBJGPU *arg0, struct Heap *arg1, NvHandle arg2, NvHandle arg3, HEAP_ALLOC_HINT_PARAMS *arg4); + #ifdef __nvoc_heap_h_disabled static inline NV_STATUS heapAllocHint(struct OBJGPU *arg0, struct Heap *arg1, NvHandle arg2, NvHandle arg3, HEAP_ALLOC_HINT_PARAMS *arg4) { NV_ASSERT_FAILED_PRECOMP("Heap was disabled!"); @@ -508,6 +525,7 @@ static inline NV_STATUS heapAllocHint(struct OBJGPU *arg0, struct Heap *arg1, Nv #endif //__nvoc_heap_h_disabled NV_STATUS heapHwAlloc_IMPL(struct OBJGPU *arg0, struct Heap *arg1, NvHandle arg2, NvHandle arg3, NvHandle arg4, MEMORY_HW_RESOURCES_ALLOCATION_REQUEST *arg5, NvU32 *arg6, NvU32 *arg7); + #ifdef __nvoc_heap_h_disabled static inline NV_STATUS heapHwAlloc(struct OBJGPU *arg0, struct Heap *arg1, NvHandle arg2, NvHandle arg3, NvHandle arg4, MEMORY_HW_RESOURCES_ALLOCATION_REQUEST *arg5, NvU32 *arg6, NvU32 *arg7) { NV_ASSERT_FAILED_PRECOMP("Heap was disabled!"); @@ -518,6 +536,7 @@ static inline NV_STATUS heapHwAlloc(struct OBJGPU *arg0, struct Heap *arg1, NvHa #endif //__nvoc_heap_h_disabled void heapHwFree_IMPL(struct OBJGPU *arg0, struct Heap *arg1, struct Memory *arg2, NvU32 arg3); + #ifdef __nvoc_heap_h_disabled static inline void heapHwFree(struct OBJGPU *arg0, struct Heap *arg1, struct Memory *arg2, NvU32 arg3) { NV_ASSERT_FAILED_PRECOMP("Heap was disabled!"); @@ -527,6 +546,7 @@ static inline void heapHwFree(struct OBJGPU *arg0, struct Heap *arg1, struct Mem #endif //__nvoc_heap_h_disabled NV_STATUS heapFreeBlockCount_IMPL(struct OBJGPU *arg0, struct Heap *arg1, NvU32 *arg2); + #ifdef __nvoc_heap_h_disabled static inline NV_STATUS heapFreeBlockCount(struct OBJGPU *arg0, struct Heap *arg1, NvU32 *arg2) { NV_ASSERT_FAILED_PRECOMP("Heap was disabled!"); @@ -537,6 +557,7 @@ static inline NV_STATUS heapFreeBlockCount(struct OBJGPU *arg0, struct Heap *arg #endif //__nvoc_heap_h_disabled NV_STATUS heapFreeBlockInfo_IMPL(struct OBJGPU *arg0, struct Heap *arg1, NvU32 arg2, void *arg3); + #ifdef __nvoc_heap_h_disabled static inline NV_STATUS heapFreeBlockInfo(struct OBJGPU *arg0, struct Heap *arg1, NvU32 arg2, void *arg3) { NV_ASSERT_FAILED_PRECOMP("Heap was disabled!"); @@ -547,6 +568,7 @@ static inline NV_STATUS heapFreeBlockInfo(struct OBJGPU *arg0, struct Heap *arg1 #endif //__nvoc_heap_h_disabled NV_STATUS heapInitRegistryOverrides_IMPL(struct OBJGPU *arg0, struct Heap *arg1); + #ifdef __nvoc_heap_h_disabled static inline NV_STATUS heapInitRegistryOverrides(struct OBJGPU *arg0, struct Heap *arg1) { NV_ASSERT_FAILED_PRECOMP("Heap was disabled!"); @@ -557,6 +579,7 @@ static inline NV_STATUS heapInitRegistryOverrides(struct OBJGPU *arg0, struct He #endif //__nvoc_heap_h_disabled NV_STATUS heapBlackListPages_IMPL(struct OBJGPU *arg0, struct Heap *arg1); + #ifdef __nvoc_heap_h_disabled static inline NV_STATUS heapBlackListPages(struct OBJGPU *arg0, struct Heap *arg1) { NV_ASSERT_FAILED_PRECOMP("Heap was disabled!"); @@ -567,6 +590,7 @@ static inline NV_STATUS heapBlackListPages(struct OBJGPU *arg0, struct Heap *arg #endif //__nvoc_heap_h_disabled NV_STATUS heapFreeBlackListedPages_IMPL(struct OBJGPU *arg0, struct Heap *arg1); + #ifdef __nvoc_heap_h_disabled static inline NV_STATUS heapFreeBlackListedPages(struct OBJGPU *arg0, struct Heap *arg1) { NV_ASSERT_FAILED_PRECOMP("Heap was disabled!"); @@ -577,6 +601,7 @@ static inline NV_STATUS heapFreeBlackListedPages(struct OBJGPU *arg0, struct Hea #endif //__nvoc_heap_h_disabled NV_STATUS heapAddPageToBlackList_IMPL(struct OBJGPU *pGpu, struct Heap *pHeap, NvU64 pageNumber, NvU32 type); + #ifdef __nvoc_heap_h_disabled static inline NV_STATUS heapAddPageToBlackList(struct OBJGPU *pGpu, struct Heap *pHeap, NvU64 pageNumber, NvU32 type) { NV_ASSERT_FAILED_PRECOMP("Heap was disabled!"); @@ -587,6 +612,7 @@ static inline NV_STATUS heapAddPageToBlackList(struct OBJGPU *pGpu, struct Heap #endif //__nvoc_heap_h_disabled NV_STATUS heapStoreBlackList_IMPL(struct OBJGPU *arg0, struct Heap *arg1, NvU64 *arg2, NvU64 *arg3, NvU32 arg4); + #ifdef __nvoc_heap_h_disabled static inline NV_STATUS heapStoreBlackList(struct OBJGPU *arg0, struct Heap *arg1, NvU64 *arg2, NvU64 *arg3, NvU32 arg4) { NV_ASSERT_FAILED_PRECOMP("Heap was disabled!"); @@ -597,6 +623,7 @@ static inline NV_STATUS heapStoreBlackList(struct OBJGPU *arg0, struct Heap *arg #endif //__nvoc_heap_h_disabled NvBool heapIsPmaManaged_IMPL(struct OBJGPU *arg0, struct Heap *arg1, NvU64 arg2, NvU64 arg3); + #ifdef __nvoc_heap_h_disabled static inline NvBool heapIsPmaManaged(struct OBJGPU *arg0, struct Heap *arg1, NvU64 arg2, NvU64 arg3) { NV_ASSERT_FAILED_PRECOMP("Heap was disabled!"); @@ -607,6 +634,7 @@ static inline NvBool heapIsPmaManaged(struct OBJGPU *arg0, struct Heap *arg1, Nv #endif //__nvoc_heap_h_disabled NvU32 heapAddRef_IMPL(struct Heap *arg0); + #ifdef __nvoc_heap_h_disabled static inline NvU32 heapAddRef(struct Heap *arg0) { NV_ASSERT_FAILED_PRECOMP("Heap was disabled!"); @@ -617,6 +645,7 @@ static inline NvU32 heapAddRef(struct Heap *arg0) { #endif //__nvoc_heap_h_disabled NvU32 heapRemoveRef_IMPL(struct Heap *arg0); + #ifdef __nvoc_heap_h_disabled static inline NvU32 heapRemoveRef(struct Heap *arg0) { NV_ASSERT_FAILED_PRECOMP("Heap was disabled!"); @@ -627,6 +656,7 @@ static inline NvU32 heapRemoveRef(struct Heap *arg0) { #endif //__nvoc_heap_h_disabled NV_STATUS heapResize_IMPL(struct Heap *arg0, NvS64 arg1); + #ifdef __nvoc_heap_h_disabled static inline NV_STATUS heapResize(struct Heap *arg0, NvS64 arg1) { NV_ASSERT_FAILED_PRECOMP("Heap was disabled!"); @@ -637,6 +667,7 @@ static inline NV_STATUS heapResize(struct Heap *arg0, NvS64 arg1) { #endif //__nvoc_heap_h_disabled void heapFilterBlackListPages_IMPL(struct Heap *arg0, NvU64 arg1, NvU64 arg2); + #ifdef __nvoc_heap_h_disabled static inline void heapFilterBlackListPages(struct Heap *arg0, NvU64 arg1, NvU64 arg2) { NV_ASSERT_FAILED_PRECOMP("Heap was disabled!"); @@ -646,6 +677,7 @@ static inline void heapFilterBlackListPages(struct Heap *arg0, NvU64 arg1, NvU64 #endif //__nvoc_heap_h_disabled NV_STATUS heapStorePendingBlackList_IMPL(struct OBJGPU *arg0, struct Heap *arg1, NvU64 arg2, NvU64 arg3); + #ifdef __nvoc_heap_h_disabled static inline NV_STATUS heapStorePendingBlackList(struct OBJGPU *arg0, struct Heap *arg1, NvU64 arg2, NvU64 arg3) { NV_ASSERT_FAILED_PRECOMP("Heap was disabled!"); diff --git a/src/nvidia/generated/g_hw_resources_nvoc.c b/src/nvidia/generated/g_hw_resources_nvoc.c index cf1c4487f..3a20492d0 100644 --- a/src/nvidia/generated/g_hw_resources_nvoc.c +++ b/src/nvidia/generated/g_hw_resources_nvoc.c @@ -145,8 +145,12 @@ static NV_STATUS __nvoc_thunk_RmResource_hwresControl_Prologue(struct MemoryHwRe return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_Memory_hwresIsReady(struct MemoryHwResources *pMemory) { - return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset)); +static NvBool __nvoc_thunk_Memory_hwresIsGpuMapAllowed(struct MemoryHwResources *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), pGpu); +} + +static NV_STATUS __nvoc_thunk_Memory_hwresIsReady(struct MemoryHwResources *pMemory, NvBool bCopyConstructorContext) { + return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), bCopyConstructorContext); } static NV_STATUS __nvoc_thunk_Memory_hwresCheckCopyPermissions(struct MemoryHwResources *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { @@ -157,6 +161,10 @@ static void __nvoc_thunk_RsResource_hwresPreDestruct(struct MemoryHwResources *p resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_Memory_hwresIsDuplicate(struct MemoryHwResources *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), hMemory, pDuplicate); +} + static NV_STATUS __nvoc_thunk_RsResource_hwresUnmapFrom(struct MemoryHwResources *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RsResource.offset), pParams); } @@ -244,12 +252,16 @@ static void __nvoc_init_funcTable_MemoryHwResources_1(MemoryHwResources *pThis) pThis->__hwresControl_Prologue__ = &__nvoc_thunk_RmResource_hwresControl_Prologue; + pThis->__hwresIsGpuMapAllowed__ = &__nvoc_thunk_Memory_hwresIsGpuMapAllowed; + pThis->__hwresIsReady__ = &__nvoc_thunk_Memory_hwresIsReady; pThis->__hwresCheckCopyPermissions__ = &__nvoc_thunk_Memory_hwresCheckCopyPermissions; pThis->__hwresPreDestruct__ = &__nvoc_thunk_RsResource_hwresPreDestruct; + pThis->__hwresIsDuplicate__ = &__nvoc_thunk_Memory_hwresIsDuplicate; + pThis->__hwresUnmapFrom__ = &__nvoc_thunk_RsResource_hwresUnmapFrom; pThis->__hwresControl_Epilogue__ = &__nvoc_thunk_RmResource_hwresControl_Epilogue; diff --git a/src/nvidia/generated/g_hw_resources_nvoc.h b/src/nvidia/generated/g_hw_resources_nvoc.h index e5c0ca1da..8da45bd94 100644 --- a/src/nvidia/generated/g_hw_resources_nvoc.h +++ b/src/nvidia/generated/g_hw_resources_nvoc.h @@ -66,9 +66,11 @@ struct MemoryHwResources { NvU32 (*__hwresGetRefCount__)(struct MemoryHwResources *); NV_STATUS (*__hwresMapTo__)(struct MemoryHwResources *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__hwresControl_Prologue__)(struct MemoryHwResources *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__hwresIsReady__)(struct MemoryHwResources *); + NvBool (*__hwresIsGpuMapAllowed__)(struct MemoryHwResources *, struct OBJGPU *); + NV_STATUS (*__hwresIsReady__)(struct MemoryHwResources *, NvBool); NV_STATUS (*__hwresCheckCopyPermissions__)(struct MemoryHwResources *, struct OBJGPU *, NvHandle); void (*__hwresPreDestruct__)(struct MemoryHwResources *); + NV_STATUS (*__hwresIsDuplicate__)(struct MemoryHwResources *, NvHandle, NvBool *); NV_STATUS (*__hwresUnmapFrom__)(struct MemoryHwResources *, RS_RES_UNMAP_FROM_PARAMS *); void (*__hwresControl_Epilogue__)(struct MemoryHwResources *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__hwresControlLookup__)(struct MemoryHwResources *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); @@ -117,9 +119,11 @@ NV_STATUS __nvoc_objCreate_MemoryHwResources(MemoryHwResources**, Dynamic*, NvU3 #define hwresGetRefCount(pResource) hwresGetRefCount_DISPATCH(pResource) #define hwresMapTo(pResource, pParams) hwresMapTo_DISPATCH(pResource, pParams) #define hwresControl_Prologue(pResource, pCallContext, pParams) hwresControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define hwresIsReady(pMemory) hwresIsReady_DISPATCH(pMemory) +#define hwresIsGpuMapAllowed(pMemory, pGpu) hwresIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define hwresIsReady(pMemory, bCopyConstructorContext) hwresIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define hwresCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) hwresCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) #define hwresPreDestruct(pResource) hwresPreDestruct_DISPATCH(pResource) +#define hwresIsDuplicate(pMemory, hMemory, pDuplicate) hwresIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) #define hwresUnmapFrom(pResource, pParams) hwresUnmapFrom_DISPATCH(pResource, pParams) #define hwresControl_Epilogue(pResource, pCallContext, pParams) hwresControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define hwresControlLookup(pResource, pParams, ppEntry) hwresControlLookup_DISPATCH(pResource, pParams, ppEntry) @@ -179,8 +183,12 @@ static inline NV_STATUS hwresControl_Prologue_DISPATCH(struct MemoryHwResources return pResource->__hwresControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS hwresIsReady_DISPATCH(struct MemoryHwResources *pMemory) { - return pMemory->__hwresIsReady__(pMemory); +static inline NvBool hwresIsGpuMapAllowed_DISPATCH(struct MemoryHwResources *pMemory, struct OBJGPU *pGpu) { + return pMemory->__hwresIsGpuMapAllowed__(pMemory, pGpu); +} + +static inline NV_STATUS hwresIsReady_DISPATCH(struct MemoryHwResources *pMemory, NvBool bCopyConstructorContext) { + return pMemory->__hwresIsReady__(pMemory, bCopyConstructorContext); } static inline NV_STATUS hwresCheckCopyPermissions_DISPATCH(struct MemoryHwResources *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { @@ -191,6 +199,10 @@ static inline void hwresPreDestruct_DISPATCH(struct MemoryHwResources *pResource pResource->__hwresPreDestruct__(pResource); } +static inline NV_STATUS hwresIsDuplicate_DISPATCH(struct MemoryHwResources *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return pMemory->__hwresIsDuplicate__(pMemory, hMemory, pDuplicate); +} + static inline NV_STATUS hwresUnmapFrom_DISPATCH(struct MemoryHwResources *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return pResource->__hwresUnmapFrom__(pResource, pParams); } @@ -212,8 +224,10 @@ static inline NvBool hwresAccessCallback_DISPATCH(struct MemoryHwResources *pRes } NV_STATUS hwresConstruct_IMPL(struct MemoryHwResources *arg_pMemoryHwResources, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_hwresConstruct(arg_pMemoryHwResources, arg_pCallContext, arg_pParams) hwresConstruct_IMPL(arg_pMemoryHwResources, arg_pCallContext, arg_pParams) void hwresDestruct_IMPL(struct MemoryHwResources *pMemoryHwResources); + #define __nvoc_hwresDestruct(pMemoryHwResources) hwresDestruct_IMPL(pMemoryHwResources) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_hypervisor_nvoc.c b/src/nvidia/generated/g_hypervisor_nvoc.c new file mode 100644 index 000000000..e33606906 --- /dev/null +++ b/src/nvidia/generated/g_hypervisor_nvoc.c @@ -0,0 +1,154 @@ +#define NVOC_HYPERVISOR_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_hypervisor_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0x33c1ba = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJHYPERVISOR; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +void __nvoc_init_OBJHYPERVISOR(OBJHYPERVISOR*); +void __nvoc_init_funcTable_OBJHYPERVISOR(OBJHYPERVISOR*); +NV_STATUS __nvoc_ctor_OBJHYPERVISOR(OBJHYPERVISOR*); +void __nvoc_init_dataField_OBJHYPERVISOR(OBJHYPERVISOR*); +void __nvoc_dtor_OBJHYPERVISOR(OBJHYPERVISOR*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_OBJHYPERVISOR; + +static const struct NVOC_RTTI __nvoc_rtti_OBJHYPERVISOR_OBJHYPERVISOR = { + /*pClassDef=*/ &__nvoc_class_def_OBJHYPERVISOR, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_OBJHYPERVISOR, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_OBJHYPERVISOR_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(OBJHYPERVISOR, __nvoc_base_Object), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_OBJHYPERVISOR = { + /*numRelatives=*/ 2, + /*relatives=*/ { + &__nvoc_rtti_OBJHYPERVISOR_OBJHYPERVISOR, + &__nvoc_rtti_OBJHYPERVISOR_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_OBJHYPERVISOR = +{ + /*classInfo=*/ { + /*size=*/ sizeof(OBJHYPERVISOR), + /*classId=*/ classId(OBJHYPERVISOR), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "OBJHYPERVISOR", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_OBJHYPERVISOR, + /*pCastInfo=*/ &__nvoc_castinfo_OBJHYPERVISOR, + /*pExportInfo=*/ &__nvoc_export_info_OBJHYPERVISOR +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_OBJHYPERVISOR = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_Object(Object*); +void __nvoc_dtor_OBJHYPERVISOR(OBJHYPERVISOR *pThis) { + __nvoc_hypervisorDestruct(pThis); + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_OBJHYPERVISOR(OBJHYPERVISOR *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_Object(Object* ); +NV_STATUS __nvoc_ctor_OBJHYPERVISOR(OBJHYPERVISOR *pThis) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_Object(&pThis->__nvoc_base_Object); + if (status != NV_OK) goto __nvoc_ctor_OBJHYPERVISOR_fail_Object; + __nvoc_init_dataField_OBJHYPERVISOR(pThis); + + status = __nvoc_hypervisorConstruct(pThis); + if (status != NV_OK) goto __nvoc_ctor_OBJHYPERVISOR_fail__init; + goto __nvoc_ctor_OBJHYPERVISOR_exit; // Success + +__nvoc_ctor_OBJHYPERVISOR_fail__init: + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); +__nvoc_ctor_OBJHYPERVISOR_fail_Object: +__nvoc_ctor_OBJHYPERVISOR_exit: + + return status; +} + +static void __nvoc_init_funcTable_OBJHYPERVISOR_1(OBJHYPERVISOR *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_funcTable_OBJHYPERVISOR(OBJHYPERVISOR *pThis) { + __nvoc_init_funcTable_OBJHYPERVISOR_1(pThis); +} + +void __nvoc_init_Object(Object*); +void __nvoc_init_OBJHYPERVISOR(OBJHYPERVISOR *pThis) { + pThis->__nvoc_pbase_OBJHYPERVISOR = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Object; + __nvoc_init_Object(&pThis->__nvoc_base_Object); + __nvoc_init_funcTable_OBJHYPERVISOR(pThis); +} + +NV_STATUS __nvoc_objCreate_OBJHYPERVISOR(OBJHYPERVISOR **ppThis, Dynamic *pParent, NvU32 createFlags) { + NV_STATUS status; + Object *pParentObj; + OBJHYPERVISOR *pThis; + + pThis = portMemAllocNonPaged(sizeof(OBJHYPERVISOR)); + if (pThis == NULL) return NV_ERR_NO_MEMORY; + + portMemSet(pThis, 0, sizeof(OBJHYPERVISOR)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJHYPERVISOR); + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_OBJHYPERVISOR(pThis); + status = __nvoc_ctor_OBJHYPERVISOR(pThis); + if (status != NV_OK) goto __nvoc_objCreate_OBJHYPERVISOR_cleanup; + + *ppThis = pThis; + return NV_OK; + +__nvoc_objCreate_OBJHYPERVISOR_cleanup: + // do not call destructors here since the constructor already called them + portMemFree(pThis); + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_OBJHYPERVISOR(OBJHYPERVISOR **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + + status = __nvoc_objCreate_OBJHYPERVISOR(ppThis, pParent, createFlags); + + return status; +} + diff --git a/src/nvidia/generated/g_hypervisor_nvoc.h b/src/nvidia/generated/g_hypervisor_nvoc.h index 29f00a3ac..7126164b5 100644 --- a/src/nvidia/generated/g_hypervisor_nvoc.h +++ b/src/nvidia/generated/g_hypervisor_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -44,6 +44,20 @@ extern "C" { #include "nv-hypervisor.h" #include "mem_mgr/mem.h" +/* ------------------------ Forward Declarations ---------------------------- */ +struct OBJOS; + +#ifndef __NVOC_CLASS_OBJOS_TYPEDEF__ +#define __NVOC_CLASS_OBJOS_TYPEDEF__ +typedef struct OBJOS OBJOS; +#endif /* __NVOC_CLASS_OBJOS_TYPEDEF__ */ + +#ifndef __nvoc_class_id_OBJOS +#define __nvoc_class_id_OBJOS 0xaa1d70 +#endif /* __nvoc_class_id_OBJOS */ + + + typedef struct OBJHYPERVISOR *POBJHYPERVISOR; #ifndef __NVOC_CLASS_OBJHYPERVISOR_TYPEDEF__ @@ -68,6 +82,7 @@ struct OBJHYPERVISOR { struct Object __nvoc_base_Object; struct Object *__nvoc_pbase_Object; struct OBJHYPERVISOR *__nvoc_pbase_OBJHYPERVISOR; + NvBool PDB_PROP_HYPERVISOR_DRIVERVM_ENABLED; NvBool bDetected; NvBool bIsHVMGuest; HYPERVISOR_TYPE type; @@ -96,6 +111,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJHYPERVISOR; ((OBJHYPERVISOR*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(OBJHYPERVISOR))) #endif //__nvoc_hypervisor_h_disabled +#define PDB_PROP_HYPERVISOR_DRIVERVM_ENABLED_BASE_CAST +#define PDB_PROP_HYPERVISOR_DRIVERVM_ENABLED_BASE_NAME PDB_PROP_HYPERVISOR_DRIVERVM_ENABLED NV_STATUS __nvoc_objCreateDynamic_OBJHYPERVISOR(OBJHYPERVISOR**, Dynamic*, NvU32, va_list); @@ -103,32 +120,281 @@ NV_STATUS __nvoc_objCreate_OBJHYPERVISOR(OBJHYPERVISOR**, Dynamic*, NvU32); #define __objCreate_OBJHYPERVISOR(ppNewObj, pParent, createFlags) \ __nvoc_objCreate_OBJHYPERVISOR((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) -static inline NvBool hypervisorIsVgxHyper_491d52(void) { - return ((NvBool)(0 != 0)); -} +NvBool hypervisorIsVgxHyper_IMPL(void); -#define hypervisorIsVgxHyper() hypervisorIsVgxHyper_491d52() + +#define hypervisorIsVgxHyper() hypervisorIsVgxHyper_IMPL() #define hypervisorIsVgxHyper_HAL() hypervisorIsVgxHyper() -static inline NvBool hypervisorCheckForAdminAccess(NvHandle hClient, NvU32 rmCtrlId) { - return ((NvBool)(0 != 0)); +NV_STATUS hypervisorInjectInterrupt_IMPL(struct OBJHYPERVISOR *arg0, VGPU_NS_INTR *arg1); + + +#ifdef __nvoc_hypervisor_h_disabled +static inline NV_STATUS hypervisorInjectInterrupt(struct OBJHYPERVISOR *arg0, VGPU_NS_INTR *arg1) { + NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_hypervisor_h_disabled +#define hypervisorInjectInterrupt(arg0, arg1) hypervisorInjectInterrupt_IMPL(arg0, arg1) +#endif //__nvoc_hypervisor_h_disabled + +#define hypervisorInjectInterrupt_HAL(arg0, arg1) hypervisorInjectInterrupt(arg0, arg1) + +void hypervisorSetHypervVgpuSupported_IMPL(struct OBJHYPERVISOR *arg0); + + +#ifdef __nvoc_hypervisor_h_disabled +static inline void hypervisorSetHypervVgpuSupported(struct OBJHYPERVISOR *arg0) { + NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); +} +#else //__nvoc_hypervisor_h_disabled +#define hypervisorSetHypervVgpuSupported(arg0) hypervisorSetHypervVgpuSupported_IMPL(arg0) +#endif //__nvoc_hypervisor_h_disabled + +#define hypervisorSetHypervVgpuSupported_HAL(arg0) hypervisorSetHypervVgpuSupported(arg0) + +static inline NV_STATUS hypervisorSetupGuestVmBusChannel_56cd7a(struct OBJHYPERVISOR *arg0, struct OBJGPU *arg1) { + return NV_OK; } -static inline NvBool hypervisorCheckForObjectAccess(NvHandle hClient) { - return ((NvBool)(0 != 0)); + +#ifdef __nvoc_hypervisor_h_disabled +static inline NV_STATUS hypervisorSetupGuestVmBusChannel(struct OBJHYPERVISOR *arg0, struct OBJGPU *arg1) { + NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_hypervisor_h_disabled +#define hypervisorSetupGuestVmBusChannel(arg0, arg1) hypervisorSetupGuestVmBusChannel_56cd7a(arg0, arg1) +#endif //__nvoc_hypervisor_h_disabled + +#define hypervisorSetupGuestVmBusChannel_HAL(arg0, arg1) hypervisorSetupGuestVmBusChannel(arg0, arg1) + +static inline void hypervisorDestroyGuestVmBusChannel_b3696a(struct OBJHYPERVISOR *arg0) { + return; } -static inline NvBool hypervisorCheckForGspOffloadAccess(POBJGPU pGpu, NvU32 rmCtrlId) { - return ((NvBool)(0 != 0)); + +#ifdef __nvoc_hypervisor_h_disabled +static inline void hypervisorDestroyGuestVmBusChannel(struct OBJHYPERVISOR *arg0) { + NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); +} +#else //__nvoc_hypervisor_h_disabled +#define hypervisorDestroyGuestVmBusChannel(arg0) hypervisorDestroyGuestVmBusChannel_b3696a(arg0) +#endif //__nvoc_hypervisor_h_disabled + +#define hypervisorDestroyGuestVmBusChannel_HAL(arg0) hypervisorDestroyGuestVmBusChannel(arg0) + +static inline NV_STATUS hypervisorSetupHostVmBusChannel_56cd7a(struct OBJHYPERVISOR *arg0, NvU64 arg1, struct OBJGPU *arg2, HOST_VGPU_DEVICE *arg3) { + return NV_OK; } -static inline NvBool hypervisorIsType(HYPERVISOR_TYPE hyperType) { - return ((NvBool)(0 != 0)); + +#ifdef __nvoc_hypervisor_h_disabled +static inline NV_STATUS hypervisorSetupHostVmBusChannel(struct OBJHYPERVISOR *arg0, NvU64 arg1, struct OBJGPU *arg2, HOST_VGPU_DEVICE *arg3) { + NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); + return NV_ERR_NOT_SUPPORTED; } +#else //__nvoc_hypervisor_h_disabled +#define hypervisorSetupHostVmBusChannel(arg0, arg1, arg2, arg3) hypervisorSetupHostVmBusChannel_56cd7a(arg0, arg1, arg2, arg3) +#endif //__nvoc_hypervisor_h_disabled + +#define hypervisorSetupHostVmBusChannel_HAL(arg0, arg1, arg2, arg3) hypervisorSetupHostVmBusChannel(arg0, arg1, arg2, arg3) + +static inline void hypervisorResetHostVmBusChannel_b3696a(struct OBJHYPERVISOR *arg0, HOST_VGPU_DEVICE *arg1) { + return; +} + + +#ifdef __nvoc_hypervisor_h_disabled +static inline void hypervisorResetHostVmBusChannel(struct OBJHYPERVISOR *arg0, HOST_VGPU_DEVICE *arg1) { + NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); +} +#else //__nvoc_hypervisor_h_disabled +#define hypervisorResetHostVmBusChannel(arg0, arg1) hypervisorResetHostVmBusChannel_b3696a(arg0, arg1) +#endif //__nvoc_hypervisor_h_disabled + +#define hypervisorResetHostVmBusChannel_HAL(arg0, arg1) hypervisorResetHostVmBusChannel(arg0, arg1) + +static inline NV_STATUS hypervisorGuestPinPages_56cd7a(struct OBJHYPERVISOR *arg0, MEMORY_DESCRIPTOR *arg1) { + return NV_OK; +} + + +#ifdef __nvoc_hypervisor_h_disabled +static inline NV_STATUS hypervisorGuestPinPages(struct OBJHYPERVISOR *arg0, MEMORY_DESCRIPTOR *arg1) { + NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_hypervisor_h_disabled +#define hypervisorGuestPinPages(arg0, arg1) hypervisorGuestPinPages_56cd7a(arg0, arg1) +#endif //__nvoc_hypervisor_h_disabled + +#define hypervisorGuestPinPages_HAL(arg0, arg1) hypervisorGuestPinPages(arg0, arg1) + +static inline NV_STATUS hypervisorGuestPinPagesUsingPfns_56cd7a(struct OBJHYPERVISOR *arg0, NvU32 arg1, NvU64 *arg2) { + return NV_OK; +} + + +#ifdef __nvoc_hypervisor_h_disabled +static inline NV_STATUS hypervisorGuestPinPagesUsingPfns(struct OBJHYPERVISOR *arg0, NvU32 arg1, NvU64 *arg2) { + NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_hypervisor_h_disabled +#define hypervisorGuestPinPagesUsingPfns(arg0, arg1, arg2) hypervisorGuestPinPagesUsingPfns_56cd7a(arg0, arg1, arg2) +#endif //__nvoc_hypervisor_h_disabled + +#define hypervisorGuestPinPagesUsingPfns_HAL(arg0, arg1, arg2) hypervisorGuestPinPagesUsingPfns(arg0, arg1, arg2) + +static inline NV_STATUS hypervisorSendEventToGuest_56cd7a(struct OBJHYPERVISOR *arg0, void *arg1) { + return NV_OK; +} + + +#ifdef __nvoc_hypervisor_h_disabled +static inline NV_STATUS hypervisorSendEventToGuest(struct OBJHYPERVISOR *arg0, void *arg1) { + NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_hypervisor_h_disabled +#define hypervisorSendEventToGuest(arg0, arg1) hypervisorSendEventToGuest_56cd7a(arg0, arg1) +#endif //__nvoc_hypervisor_h_disabled + +#define hypervisorSendEventToGuest_HAL(arg0, arg1) hypervisorSendEventToGuest(arg0, arg1) + +static inline NV_STATUS hypervisorAllocHostVmbusChannel_56cd7a(struct OBJHYPERVISOR *arg0, HOST_VGPU_DEVICE *arg1) { + return NV_OK; +} + + +#ifdef __nvoc_hypervisor_h_disabled +static inline NV_STATUS hypervisorAllocHostVmbusChannel(struct OBJHYPERVISOR *arg0, HOST_VGPU_DEVICE *arg1) { + NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_hypervisor_h_disabled +#define hypervisorAllocHostVmbusChannel(arg0, arg1) hypervisorAllocHostVmbusChannel_56cd7a(arg0, arg1) +#endif //__nvoc_hypervisor_h_disabled + +#define hypervisorAllocHostVmbusChannel_HAL(arg0, arg1) hypervisorAllocHostVmbusChannel(arg0, arg1) + +static inline void hypervisorFreeHostVmbusChannel_b3696a(struct OBJHYPERVISOR *arg0, HOST_VGPU_DEVICE *arg1) { + return; +} + + +#ifdef __nvoc_hypervisor_h_disabled +static inline void hypervisorFreeHostVmbusChannel(struct OBJHYPERVISOR *arg0, HOST_VGPU_DEVICE *arg1) { + NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); +} +#else //__nvoc_hypervisor_h_disabled +#define hypervisorFreeHostVmbusChannel(arg0, arg1) hypervisorFreeHostVmbusChannel_b3696a(arg0, arg1) +#endif //__nvoc_hypervisor_h_disabled + +#define hypervisorFreeHostVmbusChannel_HAL(arg0, arg1) hypervisorFreeHostVmbusChannel(arg0, arg1) + +static inline NV_STATUS hypervisorVmbusHostCompletePacket_56cd7a(struct OBJHYPERVISOR *arg0, NvU64 arg1, HOST_VGPU_DEVICE *arg2) { + return NV_OK; +} + + +#ifdef __nvoc_hypervisor_h_disabled +static inline NV_STATUS hypervisorVmbusHostCompletePacket(struct OBJHYPERVISOR *arg0, NvU64 arg1, HOST_VGPU_DEVICE *arg2) { + NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_hypervisor_h_disabled +#define hypervisorVmbusHostCompletePacket(arg0, arg1, arg2) hypervisorVmbusHostCompletePacket_56cd7a(arg0, arg1, arg2) +#endif //__nvoc_hypervisor_h_disabled + +#define hypervisorVmbusHostCompletePacket_HAL(arg0, arg1, arg2) hypervisorVmbusHostCompletePacket(arg0, arg1, arg2) + +NvBool hypervisorCheckForObjectAccess_IMPL(NvHandle hClient); + +#define hypervisorCheckForObjectAccess(hClient) hypervisorCheckForObjectAccess_IMPL(hClient) +NvBool hypervisorIsType_IMPL(HYPERVISOR_TYPE hyperType); + +#define hypervisorIsType(hyperType) hypervisorIsType_IMPL(hyperType) +NV_STATUS hypervisorConstruct_IMPL(struct OBJHYPERVISOR *arg_); + +#define __nvoc_hypervisorConstruct(arg_) hypervisorConstruct_IMPL(arg_) +void hypervisorDestruct_IMPL(struct OBJHYPERVISOR *arg0); + +#define __nvoc_hypervisorDestruct(arg0) hypervisorDestruct_IMPL(arg0) +NV_STATUS hypervisorDetection_IMPL(struct OBJHYPERVISOR *arg0, struct OBJOS *arg1); + +#ifdef __nvoc_hypervisor_h_disabled +static inline NV_STATUS hypervisorDetection(struct OBJHYPERVISOR *arg0, struct OBJOS *arg1) { + NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_hypervisor_h_disabled +#define hypervisorDetection(arg0, arg1) hypervisorDetection_IMPL(arg0, arg1) +#endif //__nvoc_hypervisor_h_disabled + +NvBool hypervisorPcieP2pDetection_IMPL(struct OBJHYPERVISOR *arg0, NvU32 arg1); + +#ifdef __nvoc_hypervisor_h_disabled +static inline NvBool hypervisorPcieP2pDetection(struct OBJHYPERVISOR *arg0, NvU32 arg1) { + NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); + return NV_FALSE; +} +#else //__nvoc_hypervisor_h_disabled +#define hypervisorPcieP2pDetection(arg0, arg1) hypervisorPcieP2pDetection_IMPL(arg0, arg1) +#endif //__nvoc_hypervisor_h_disabled + +HYPERVISOR_TYPE hypervisorGetHypervisorType_IMPL(struct OBJHYPERVISOR *arg0); + +#ifdef __nvoc_hypervisor_h_disabled +static inline HYPERVISOR_TYPE hypervisorGetHypervisorType(struct OBJHYPERVISOR *arg0) { + NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); + HYPERVISOR_TYPE ret; + portMemSet(&ret, 0, sizeof(HYPERVISOR_TYPE)); + return ret; +} +#else //__nvoc_hypervisor_h_disabled +#define hypervisorGetHypervisorType(arg0) hypervisorGetHypervisorType_IMPL(arg0) +#endif //__nvoc_hypervisor_h_disabled #undef PRIVATE_FIELD +#ifdef HAVE_DESIGNATED_INITIALIZERS +#define SFINIT(f, v) f = v +#else +#define SFINIT(f, v) v +#endif + +// OPS for different hypervisor operations at runtime + +// +// A hypervisor specific function for post detection (after hypervisor type +// has been identified). As the post detection, there could be hypervisor +// specific requirement to detect root/parent/child partition. +// +typedef NV_STATUS (*HypervisorPostDetection)(struct OBJOS *, NvBool *); + +// +// A hypervisor specific function to identify if a hypervisor +// is allowed to run GPUs present in the mask (in: param) under +// PCI-E P2P configuration +// +typedef NvBool (*HypervisorIsPcieP2PSupported)(NvU32); + +typedef struct _hypervisor_ops +{ + const char *hypervisorName; + const char *hypervisorSig; + HypervisorPostDetection hypervisorPostDetection; + HypervisorIsPcieP2PSupported hypervisorIsPcieP2PSupported; +} HYPERVISOR_OPS, *PHYPERVISOR_OPS; + +extern HYPERVISOR_OPS kvmHypervisorOps; +extern HYPERVISOR_OPS xenHypervisorOps; +extern HYPERVISOR_OPS hypervHypervisorOps; +extern HYPERVISOR_OPS vmwareHypervisorOps; + #endif // HYPERVISOR_H #ifdef __cplusplus diff --git a/src/nvidia/generated/g_i2c_api_nvoc.c b/src/nvidia/generated/g_i2c_api_nvoc.c index 834684c15..3cfff37ad 100644 --- a/src/nvidia/generated/g_i2c_api_nvoc.c +++ b/src/nvidia/generated/g_i2c_api_nvoc.c @@ -165,6 +165,10 @@ static NV_STATUS __nvoc_thunk_RsResource_i2capiUnmapFrom(struct I2cApi *pResourc return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_i2capiIsDuplicate(struct I2cApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_i2capiControl_Epilogue(struct I2cApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RmResource.offset), pCallContext, pParams); } @@ -360,6 +364,8 @@ static void __nvoc_init_funcTable_I2cApi_1(I2cApi *pThis) { pThis->__i2capiUnmapFrom__ = &__nvoc_thunk_RsResource_i2capiUnmapFrom; + pThis->__i2capiIsDuplicate__ = &__nvoc_thunk_RsResource_i2capiIsDuplicate; + pThis->__i2capiControl_Epilogue__ = &__nvoc_thunk_RmResource_i2capiControl_Epilogue; pThis->__i2capiControlLookup__ = &__nvoc_thunk_RsResource_i2capiControlLookup; diff --git a/src/nvidia/generated/g_i2c_api_nvoc.h b/src/nvidia/generated/g_i2c_api_nvoc.h index ebb1d1e3f..dd0afaaa6 100644 --- a/src/nvidia/generated/g_i2c_api_nvoc.h +++ b/src/nvidia/generated/g_i2c_api_nvoc.h @@ -78,6 +78,7 @@ struct I2cApi { NV_STATUS (*__i2capiInternalControlForward__)(struct I2cApi *, NvU32, void *, NvU32); void (*__i2capiPreDestruct__)(struct I2cApi *); NV_STATUS (*__i2capiUnmapFrom__)(struct I2cApi *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__i2capiIsDuplicate__)(struct I2cApi *, NvHandle, NvBool *); void (*__i2capiControl_Epilogue__)(struct I2cApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__i2capiControlLookup__)(struct I2cApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__i2capiMap__)(struct I2cApi *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -135,6 +136,7 @@ NV_STATUS __nvoc_objCreate_I2cApi(I2cApi**, Dynamic*, NvU32, struct CALL_CONTEXT #define i2capiInternalControlForward(pGpuResource, command, pParams, size) i2capiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define i2capiPreDestruct(pResource) i2capiPreDestruct_DISPATCH(pResource) #define i2capiUnmapFrom(pResource, pParams) i2capiUnmapFrom_DISPATCH(pResource, pParams) +#define i2capiIsDuplicate(pResource, hMemory, pDuplicate) i2capiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define i2capiControl_Epilogue(pResource, pCallContext, pParams) i2capiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define i2capiControlLookup(pResource, pParams, ppEntry) i2capiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define i2capiMap(pGpuResource, pCallContext, pParams, pCpuMapping) i2capiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -241,6 +243,10 @@ static inline NV_STATUS i2capiUnmapFrom_DISPATCH(struct I2cApi *pResource, RS_RE return pResource->__i2capiUnmapFrom__(pResource, pParams); } +static inline NV_STATUS i2capiIsDuplicate_DISPATCH(struct I2cApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__i2capiIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void i2capiControl_Epilogue_DISPATCH(struct I2cApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__i2capiControl_Epilogue__(pResource, pCallContext, pParams); } @@ -258,8 +264,10 @@ static inline NvBool i2capiAccessCallback_DISPATCH(struct I2cApi *pResource, str } NV_STATUS i2capiConstruct_IMPL(struct I2cApi *arg_pI2cApi, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_i2capiConstruct(arg_pI2cApi, arg_pCallContext, arg_pParams) i2capiConstruct_IMPL(arg_pI2cApi, arg_pCallContext, arg_pParams) void i2capiDestruct_IMPL(struct I2cApi *pI2cApi); + #define __nvoc_i2capiDestruct(pI2cApi) i2capiDestruct_IMPL(pI2cApi) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_intr_nvoc.c b/src/nvidia/generated/g_intr_nvoc.c index 65fd44b05..12a4aa245 100644 --- a/src/nvidia/generated/g_intr_nvoc.c +++ b/src/nvidia/generated/g_intr_nvoc.c @@ -172,15 +172,10 @@ void __nvoc_init_dataField_Intr(Intr *pThis, RmHalspecOwner *pRmhalspecowner) { PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // NVOC Property Hal field -- PDB_PROP_INTR_HOST_DRIVEN_ENGINES_REMOVED_FROM_PMC - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_INTR_HOST_DRIVEN_ENGINES_REMOVED_FROM_PMC, ((NvBool)(0 == 0))); } - // default - else - { - pThis->setProperty(pThis, PDB_PROP_INTR_HOST_DRIVEN_ENGINES_REMOVED_FROM_PMC, ((NvBool)(0 != 0))); - } // NVOC Property Hal field -- PDB_PROP_INTR_READ_ONLY_EVEN_NUMBERED_INTR_LEAF_REGS if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ @@ -194,7 +189,7 @@ void __nvoc_init_dataField_Intr(Intr *pThis, RmHalspecOwner *pRmhalspecowner) { } // NVOC Property Hal field -- PDB_PROP_INTR_ENUMERATIONS_ON_ENGINE_RESET - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->setProperty(pThis, PDB_PROP_INTR_ENUMERATIONS_ON_ENGINE_RESET, ((NvBool)(0 == 0))); } @@ -205,37 +200,22 @@ void __nvoc_init_dataField_Intr(Intr *pThis, RmHalspecOwner *pRmhalspecowner) { } // NVOC Property Hal field -- PDB_PROP_INTR_SIMPLIFIED_VBLANK_HANDLING_FOR_CTRL_TREE - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_INTR_SIMPLIFIED_VBLANK_HANDLING_FOR_CTRL_TREE, ((NvBool)(0 == 0))); } - // default - else - { - pThis->setProperty(pThis, PDB_PROP_INTR_SIMPLIFIED_VBLANK_HANDLING_FOR_CTRL_TREE, ((NvBool)(0 != 0))); - } // NVOC Property Hal field -- PDB_PROP_INTR_MASK_SUPPORTED - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_INTR_MASK_SUPPORTED, ((NvBool)(0 == 0))); } - // default - else - { - pThis->setProperty(pThis, PDB_PROP_INTR_MASK_SUPPORTED, ((NvBool)(0 != 0))); - } // Hal field -- bDefaultNonstallNotify - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->bDefaultNonstallNotify = ((NvBool)(0 == 0)); } - // default - else - { - pThis->bDefaultNonstallNotify = ((NvBool)(0 != 0)); - } pThis->bTablesPopulated = ((NvBool)(0 != 0)); @@ -279,17 +259,11 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec pThis->__intrStateDestroy__ = &intrStateDestroy_IMPL; // Hal function -- intrDecodeStallIntrEn - if (0) - { - } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__intrDecodeStallIntrEn__ = &intrDecodeStallIntrEn_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__intrDecodeStallIntrEn__ = &intrDecodeStallIntrEn_4a4dee; } @@ -299,29 +273,23 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec { pThis->__intrGetNonStallBaseVector__ = &intrGetNonStallBaseVector_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__intrGetNonStallBaseVector__ = &intrGetNonStallBaseVector_c067f9; } - else if (0) - { - } // Hal function -- intrGetUvmSharedLeafEnDisableMask if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__intrGetUvmSharedLeafEnDisableMask__ = &intrGetUvmSharedLeafEnDisableMask_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__intrGetUvmSharedLeafEnDisableMask__ = &intrGetUvmSharedLeafEnDisableMask_GA100; } - else if (0) - { - } // Hal function -- intrSetDisplayInterruptEnable - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__intrSetDisplayInterruptEnable__ = &intrSetDisplayInterruptEnable_TU102; } @@ -336,98 +304,77 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec { pThis->__intrReadRegTopEnSet__ = &intrReadRegTopEnSet_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__intrReadRegTopEnSet__ = &intrReadRegTopEnSet_GA102; } - else if (0) - { - } // Hal function -- intrWriteRegTopEnSet if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ { pThis->__intrWriteRegTopEnSet__ = &intrWriteRegTopEnSet_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__intrWriteRegTopEnSet__ = &intrWriteRegTopEnSet_GA102; } - else if (0) - { - } // Hal function -- intrWriteRegTopEnClear if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ { pThis->__intrWriteRegTopEnClear__ = &intrWriteRegTopEnClear_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__intrWriteRegTopEnClear__ = &intrWriteRegTopEnClear_GA102; } - else if (0) - { - } // Hal function -- intrGetStallSubtreeLast - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__intrGetStallSubtreeLast__ = &intrGetStallSubtreeLast_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__intrGetStallSubtreeLast__ = &intrGetStallSubtreeLast_GH100; } - else if (0) - { - } // Hal function -- intrGetNumLeaves - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__intrGetNumLeaves__ = &intrGetNumLeaves_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__intrGetNumLeaves__ = &intrGetNumLeaves_GH100; } - else if (0) - { - } // Hal function -- intrGetLeafSize - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__intrGetLeafSize__ = &intrGetLeafSize_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__intrGetLeafSize__ = &intrGetLeafSize_GH100; } - else if (0) - { - } // Hal function -- intrGetIntrTopNonStallMask - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__intrGetIntrTopNonStallMask__ = &intrGetIntrTopNonStallMask_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__intrGetIntrTopNonStallMask__ = &intrGetIntrTopNonStallMask_GH100; } - else if (0) - { - } // Hal function -- intrSanityCheckEngineIntrStallVector - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__intrSanityCheckEngineIntrStallVector__ = &intrSanityCheckEngineIntrStallVector_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__intrSanityCheckEngineIntrStallVector__ = &intrSanityCheckEngineIntrStallVector_GH100; } @@ -438,11 +385,11 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec } // Hal function -- intrSanityCheckEngineIntrNotificationVector - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__intrSanityCheckEngineIntrNotificationVector__ = &intrSanityCheckEngineIntrNotificationVector_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__intrSanityCheckEngineIntrNotificationVector__ = &intrSanityCheckEngineIntrNotificationVector_GH100; } @@ -453,70 +400,43 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec } // Hal function -- intrStateLoad - if (0) - { - } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__intrStateLoad__ = &intrStateLoad_TU102; } - else if (0) - { - } // Hal function -- intrStateUnload - if (0) - { - } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__intrStateUnload__ = &intrStateUnload_TU102; } - else if (0) - { - } // Hal function -- intrSetIntrMask - if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__intrSetIntrMask__ = &intrSetIntrMask_GP100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__intrSetIntrMask__ = &intrSetIntrMask_46f6a7; } // Hal function -- intrSetIntrEnInHw - if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__intrSetIntrEnInHw__ = &intrSetIntrEnInHw_GP100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__intrSetIntrEnInHw__ = &intrSetIntrEnInHw_d44104; } // Hal function -- intrGetIntrEnFromHw - if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__intrGetIntrEnFromHw__ = &intrGetIntrEnFromHw_GP100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__intrGetIntrEnFromHw__ = &intrGetIntrEnFromHw_b2b553; } diff --git a/src/nvidia/generated/g_intr_nvoc.h b/src/nvidia/generated/g_intr_nvoc.h index 4e539e581..7c42efb24 100644 --- a/src/nvidia/generated/g_intr_nvoc.h +++ b/src/nvidia/generated/g_intr_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -36,7 +36,6 @@ extern "C" { #include "gpu/gpu.h" #include "gpu/eng_state.h" -#include "kernel/gpu/intrable/intrable.h" #include "nvoc/utility.h" #include "utils/nvbitvector.h" #include "dev_ctrl_defines.h" @@ -88,13 +87,13 @@ typedef struct NvBool bDisableNonStall; } INTR_TABLE_ENTRY; -#define INTR_TABLE_MAX_INTRS_PER_ENTRY 4 +#define INTR_TABLE_MAX_INTRS_PER_ENTRY 6 // // The max number of interrupts we can fit in the dynamically populated, // but statically sized, interrupt table. // -#define INTR_TABLE_MAX_STATIC_PHYSICAL_INTRS 17 +#define INTR_TABLE_MAX_STATIC_PHYSICAL_INTRS 19 #define INTR_TABLE_MAX_STATIC_KERNEL_INTRS 17 #define POPULATE_INTR_TABLE(pTable, numEntries, localMcEngineIdxs, localIntrVectors, localCount, localMax) \ @@ -250,12 +249,12 @@ struct Intr { NvU32 replayableFaultIntrVector; NvU32 accessCntrIntrVector; NvU32 displayIntrVector; - NvU32 cpuTopEnMask; - IntrServiceRecord intrServiceTable[155]; + NvU32 intrTopEnMask; + IntrServiceRecord intrServiceTable[163]; NvBool bDefaultNonstallNotify; NvU32 intrTableSz; INTR_TABLE_ENTRY *pIntrTable; - INTR_TABLE_ENTRY pStaticPhysicalTable[17]; + INTR_TABLE_ENTRY pStaticPhysicalTable[19]; INTR_TABLE_ENTRY pStaticKernelTable[17]; NvBool bDpcStarted; union MC_ENGINE_BITVECTOR pmcIntrPending; @@ -377,6 +376,7 @@ NV_STATUS __nvoc_objCreate_Intr(Intr**, Dynamic*, NvU32); #define intrIsPresent(pGpu, pEngstate) intrIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS intrCheckFecsEventbufferPending_IMPL(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0, NvBool *arg1); + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrCheckFecsEventbufferPending(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0, NvBool *arg1) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -390,6 +390,7 @@ static inline NV_STATUS intrCheckFecsEventbufferPending(OBJGPU *pGpu, struct Int NV_STATUS intrCheckAndServiceFecsEventbuffer_IMPL(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0, struct THREAD_STATE_NODE *arg1); + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrCheckAndServiceFecsEventbuffer(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0, struct THREAD_STATE_NODE *arg1) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -405,6 +406,9 @@ static inline NV_STATUS intrStateDestroyPhysical_56cd7a(OBJGPU *pGpu, struct Int return NV_OK; } +NV_STATUS intrStateDestroyPhysical_IMPL(OBJGPU *pGpu, struct Intr *pIntr); + + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrStateDestroyPhysical(OBJGPU *pGpu, struct Intr *pIntr) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -420,6 +424,7 @@ static inline void intrSetInterruptMaskBug1470153War_b3696a(OBJGPU *pGpu, struct return; } + #ifdef __nvoc_intr_h_disabled static inline void intrSetInterruptMaskBug1470153War(OBJGPU *pGpu, struct Intr *pIntr) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -432,6 +437,7 @@ static inline void intrSetInterruptMaskBug1470153War(OBJGPU *pGpu, struct Intr * NV_STATUS intrGetPendingNonStall_TU102(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0, struct THREAD_STATE_NODE *arg1); + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrGetPendingNonStall(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0, struct THREAD_STATE_NODE *arg1) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -445,6 +451,7 @@ static inline NV_STATUS intrGetPendingNonStall(OBJGPU *pGpu, struct Intr *pIntr, NV_STATUS intrServiceNonStall_TU102(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0, struct THREAD_STATE_NODE *arg1); + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrServiceNonStall(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0, struct THREAD_STATE_NODE *arg1) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -458,6 +465,7 @@ static inline NV_STATUS intrServiceNonStall(OBJGPU *pGpu, struct Intr *pIntr, un NvU32 intrGetNonStallEnable_TU102(OBJGPU *pGpu, struct Intr *pIntr, struct THREAD_STATE_NODE *arg0); + #ifdef __nvoc_intr_h_disabled static inline NvU32 intrGetNonStallEnable(OBJGPU *pGpu, struct Intr *pIntr, struct THREAD_STATE_NODE *arg0) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -471,6 +479,7 @@ static inline NvU32 intrGetNonStallEnable(OBJGPU *pGpu, struct Intr *pIntr, stru void intrDisableNonStall_TU102(OBJGPU *pGpu, struct Intr *pIntr, struct THREAD_STATE_NODE *arg0); + #ifdef __nvoc_intr_h_disabled static inline void intrDisableNonStall(OBJGPU *pGpu, struct Intr *pIntr, struct THREAD_STATE_NODE *arg0) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -483,6 +492,7 @@ static inline void intrDisableNonStall(OBJGPU *pGpu, struct Intr *pIntr, struct void intrRestoreNonStall_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, struct THREAD_STATE_NODE *arg1); + #ifdef __nvoc_intr_h_disabled static inline void intrRestoreNonStall(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, struct THREAD_STATE_NODE *arg1) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -495,6 +505,7 @@ static inline void intrRestoreNonStall(OBJGPU *pGpu, struct Intr *pIntr, NvU32 a void intrGetStallInterruptMode_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 *pIntrmode, NvBool *pPending); + #ifdef __nvoc_intr_h_disabled static inline void intrGetStallInterruptMode(OBJGPU *pGpu, struct Intr *pIntr, NvU32 *pIntrmode, NvBool *pPending) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -507,6 +518,7 @@ static inline void intrGetStallInterruptMode(OBJGPU *pGpu, struct Intr *pIntr, N void intrEncodeStallIntrEn_GP100(OBJGPU *pGpu, struct Intr *pIntr, NvU32 intrEn, NvU32 *pIntrEnSet, NvU32 *pIntrEnClear); + #ifdef __nvoc_intr_h_disabled static inline void intrEncodeStallIntrEn(OBJGPU *pGpu, struct Intr *pIntr, NvU32 intrEn, NvU32 *pIntrEnSet, NvU32 *pIntrEnClear) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -519,6 +531,7 @@ static inline void intrEncodeStallIntrEn(OBJGPU *pGpu, struct Intr *pIntr, NvU32 NV_STATUS intrCheckAndServiceNonReplayableFault_TU102(OBJGPU *pGpu, struct Intr *pIntr, struct THREAD_STATE_NODE *arg0); + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrCheckAndServiceNonReplayableFault(OBJGPU *pGpu, struct Intr *pIntr, struct THREAD_STATE_NODE *arg0) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -534,6 +547,13 @@ static inline NvU32 intrGetStallBaseVector_4a4dee(OBJGPU *pGpu, struct Intr *pIn return 0; } +NvU32 intrGetStallBaseVector_TU102(OBJGPU *pGpu, struct Intr *pIntr); + +static inline NvU32 intrGetStallBaseVector_c067f9(OBJGPU *pGpu, struct Intr *pIntr) { + NV_ASSERT_OR_RETURN_PRECOMP(0, 0); +} + + #ifdef __nvoc_intr_h_disabled static inline NvU32 intrGetStallBaseVector(OBJGPU *pGpu, struct Intr *pIntr) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -547,6 +567,7 @@ static inline NvU32 intrGetStallBaseVector(OBJGPU *pGpu, struct Intr *pIntr) { void intrEnableLeaf_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 intrVector); + #ifdef __nvoc_intr_h_disabled static inline void intrEnableLeaf(OBJGPU *pGpu, struct Intr *pIntr, NvU32 intrVector) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -559,6 +580,7 @@ static inline void intrEnableLeaf(OBJGPU *pGpu, struct Intr *pIntr, NvU32 intrVe void intrDisableLeaf_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 intrVector); + #ifdef __nvoc_intr_h_disabled static inline void intrDisableLeaf(OBJGPU *pGpu, struct Intr *pIntr, NvU32 intrVector) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -571,6 +593,7 @@ static inline void intrDisableLeaf(OBJGPU *pGpu, struct Intr *pIntr, NvU32 intrV void intrEnableTopNonstall_TU102(OBJGPU *pGpu, struct Intr *pIntr, struct THREAD_STATE_NODE *pThreadState); + #ifdef __nvoc_intr_h_disabled static inline void intrEnableTopNonstall(OBJGPU *pGpu, struct Intr *pIntr, struct THREAD_STATE_NODE *pThreadState) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -583,6 +606,7 @@ static inline void intrEnableTopNonstall(OBJGPU *pGpu, struct Intr *pIntr, struc void intrDisableTopNonstall_TU102(OBJGPU *pGpu, struct Intr *pIntr, struct THREAD_STATE_NODE *pThreadState); + #ifdef __nvoc_intr_h_disabled static inline void intrDisableTopNonstall(OBJGPU *pGpu, struct Intr *pIntr, struct THREAD_STATE_NODE *pThreadState) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -595,6 +619,7 @@ static inline void intrDisableTopNonstall(OBJGPU *pGpu, struct Intr *pIntr, stru void intrSetStall_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 intrType, struct THREAD_STATE_NODE *pThreadState); + #ifdef __nvoc_intr_h_disabled static inline void intrSetStall(OBJGPU *pGpu, struct Intr *pIntr, NvU32 intrType, struct THREAD_STATE_NODE *pThreadState) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -607,6 +632,7 @@ static inline void intrSetStall(OBJGPU *pGpu, struct Intr *pIntr, NvU32 intrType void intrClearLeafVector_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 vector, struct THREAD_STATE_NODE *pThreadState); + #ifdef __nvoc_intr_h_disabled static inline void intrClearLeafVector(OBJGPU *pGpu, struct Intr *pIntr, NvU32 vector, struct THREAD_STATE_NODE *pThreadState) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -621,6 +647,9 @@ static inline void intrClearCpuLeafVector_b3696a(OBJGPU *pGpu, struct Intr *pInt return; } +void intrClearCpuLeafVector_GH100(OBJGPU *pGpu, struct Intr *pIntr, NvU32 vector, struct THREAD_STATE_NODE *pThreadState); + + #ifdef __nvoc_intr_h_disabled static inline void intrClearCpuLeafVector(OBJGPU *pGpu, struct Intr *pIntr, NvU32 vector, struct THREAD_STATE_NODE *pThreadState) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -635,6 +664,9 @@ static inline void intrWriteCpuRegLeaf_b3696a(OBJGPU *pGpu, struct Intr *pIntr, return; } +void intrWriteCpuRegLeaf_GH100(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); + + #ifdef __nvoc_intr_h_disabled static inline void intrWriteCpuRegLeaf(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -647,6 +679,7 @@ static inline void intrWriteCpuRegLeaf(OBJGPU *pGpu, struct Intr *pIntr, NvU32 a NvBool intrIsVectorPending_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 vector, struct THREAD_STATE_NODE *pThreadState); + #ifdef __nvoc_intr_h_disabled static inline NvBool intrIsVectorPending(OBJGPU *pGpu, struct Intr *pIntr, NvU32 vector, struct THREAD_STATE_NODE *pThreadState) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -660,6 +693,7 @@ static inline NvBool intrIsVectorPending(OBJGPU *pGpu, struct Intr *pIntr, NvU32 NV_STATUS intrSetStallSWIntr_TU102(OBJGPU *pGpu, struct Intr *pIntr); + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrSetStallSWIntr(OBJGPU *pGpu, struct Intr *pIntr) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -673,6 +707,7 @@ static inline NV_STATUS intrSetStallSWIntr(OBJGPU *pGpu, struct Intr *pIntr) { NV_STATUS intrClearStallSWIntr_TU102(OBJGPU *pGpu, struct Intr *pIntr); + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrClearStallSWIntr(OBJGPU *pGpu, struct Intr *pIntr) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -686,6 +721,7 @@ static inline NV_STATUS intrClearStallSWIntr(OBJGPU *pGpu, struct Intr *pIntr) { void intrEnableStallSWIntr_TU102(OBJGPU *pGpu, struct Intr *pIntr); + #ifdef __nvoc_intr_h_disabled static inline void intrEnableStallSWIntr(OBJGPU *pGpu, struct Intr *pIntr) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -698,6 +734,7 @@ static inline void intrEnableStallSWIntr(OBJGPU *pGpu, struct Intr *pIntr) { void intrDisableStallSWIntr_TU102(OBJGPU *pGpu, struct Intr *pIntr); + #ifdef __nvoc_intr_h_disabled static inline void intrDisableStallSWIntr(OBJGPU *pGpu, struct Intr *pIntr) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -708,9 +745,8 @@ static inline void intrDisableStallSWIntr(OBJGPU *pGpu, struct Intr *pIntr) { #define intrDisableStallSWIntr_HAL(pGpu, pIntr) intrDisableStallSWIntr(pGpu, pIntr) -static inline NV_STATUS intrEnableVirtualIntrLeaf_46f6a7(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid) { - return NV_ERR_NOT_SUPPORTED; -} +NV_STATUS intrEnableVirtualIntrLeaf_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid); + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrEnableVirtualIntrLeaf(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid) { @@ -718,21 +754,20 @@ static inline NV_STATUS intrEnableVirtualIntrLeaf(OBJGPU *pGpu, struct Intr *pIn return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_intr_h_disabled -#define intrEnableVirtualIntrLeaf(pGpu, pIntr, gfid) intrEnableVirtualIntrLeaf_46f6a7(pGpu, pIntr, gfid) +#define intrEnableVirtualIntrLeaf(pGpu, pIntr, gfid) intrEnableVirtualIntrLeaf_TU102(pGpu, pIntr, gfid) #endif //__nvoc_intr_h_disabled #define intrEnableVirtualIntrLeaf_HAL(pGpu, pIntr, gfid) intrEnableVirtualIntrLeaf(pGpu, pIntr, gfid) -static inline void intrServiceVirtual_b3696a(OBJGPU *pGpu, struct Intr *pIntr) { - return; -} +void intrServiceVirtual_TU102(OBJGPU *pGpu, struct Intr *pIntr); + #ifdef __nvoc_intr_h_disabled static inline void intrServiceVirtual(OBJGPU *pGpu, struct Intr *pIntr) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); } #else //__nvoc_intr_h_disabled -#define intrServiceVirtual(pGpu, pIntr) intrServiceVirtual_b3696a(pGpu, pIntr) +#define intrServiceVirtual(pGpu, pIntr) intrServiceVirtual_TU102(pGpu, pIntr) #endif //__nvoc_intr_h_disabled #define intrServiceVirtual_HAL(pGpu, pIntr) intrServiceVirtual(pGpu, pIntr) @@ -741,6 +776,9 @@ static inline void intrResetIntrRegistersForVF_b3696a(OBJGPU *pGpu, struct Intr return; } +void intrResetIntrRegistersForVF_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid); + + #ifdef __nvoc_intr_h_disabled static inline void intrResetIntrRegistersForVF(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -755,6 +793,9 @@ static inline NV_STATUS intrSaveIntrRegValue_46f6a7(OBJGPU *pGpu, struct Intr *p return NV_ERR_NOT_SUPPORTED; } +NV_STATUS intrSaveIntrRegValue_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 *arg1, NvU32 *arg2); + + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrSaveIntrRegValue(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 *arg1, NvU32 *arg2) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -770,6 +811,9 @@ static inline NV_STATUS intrRestoreIntrRegValue_46f6a7(OBJGPU *pGpu, struct Intr return NV_ERR_NOT_SUPPORTED; } +NV_STATUS intrRestoreIntrRegValue_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, NvU32 *arg2); + + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrRestoreIntrRegValue(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, NvU32 *arg2) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -785,6 +829,9 @@ static inline NV_STATUS intrTriggerCpuDoorbellForVF_46f6a7(OBJGPU *pGpu, struct return NV_ERR_NOT_SUPPORTED; } +NV_STATUS intrTriggerCpuDoorbellForVF_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid); + + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrTriggerCpuDoorbellForVF(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -796,9 +843,8 @@ static inline NV_STATUS intrTriggerCpuDoorbellForVF(OBJGPU *pGpu, struct Intr *p #define intrTriggerCpuDoorbellForVF_HAL(pGpu, pIntr, gfid) intrTriggerCpuDoorbellForVF(pGpu, pIntr, gfid) -static inline NV_STATUS intrTriggerPrivDoorbell_46f6a7(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid) { - return NV_ERR_NOT_SUPPORTED; -} +NV_STATUS intrTriggerPrivDoorbell_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid); + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrTriggerPrivDoorbell(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid) { @@ -806,13 +852,14 @@ static inline NV_STATUS intrTriggerPrivDoorbell(OBJGPU *pGpu, struct Intr *pIntr return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_intr_h_disabled -#define intrTriggerPrivDoorbell(pGpu, pIntr, gfid) intrTriggerPrivDoorbell_46f6a7(pGpu, pIntr, gfid) +#define intrTriggerPrivDoorbell(pGpu, pIntr, gfid) intrTriggerPrivDoorbell_TU102(pGpu, pIntr, gfid) #endif //__nvoc_intr_h_disabled #define intrTriggerPrivDoorbell_HAL(pGpu, pIntr, gfid) intrTriggerPrivDoorbell(pGpu, pIntr, gfid) void intrRetriggerTopLevel_TU102(OBJGPU *pGpu, struct Intr *pIntr); + #ifdef __nvoc_intr_h_disabled static inline void intrRetriggerTopLevel(OBJGPU *pGpu, struct Intr *pIntr) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -825,6 +872,7 @@ static inline void intrRetriggerTopLevel(OBJGPU *pGpu, struct Intr *pIntr) { NV_STATUS intrGetLeafStatus_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 *arg0, struct THREAD_STATE_NODE *arg1); + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrGetLeafStatus(OBJGPU *pGpu, struct Intr *pIntr, NvU32 *arg0, struct THREAD_STATE_NODE *arg1) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -838,6 +886,7 @@ static inline NV_STATUS intrGetLeafStatus(OBJGPU *pGpu, struct Intr *pIntr, NvU3 NV_STATUS intrGetPendingDisplayIntr_TU102(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *pEngines, struct THREAD_STATE_NODE *pThreadState); + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrGetPendingDisplayIntr(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *pEngines, struct THREAD_STATE_NODE *pThreadState) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -851,6 +900,7 @@ static inline NV_STATUS intrGetPendingDisplayIntr(OBJGPU *pGpu, struct Intr *pIn void intrDumpState_TU102(OBJGPU *pGpu, struct Intr *pIntr); + #ifdef __nvoc_intr_h_disabled static inline void intrDumpState(OBJGPU *pGpu, struct Intr *pIntr) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -863,6 +913,7 @@ static inline void intrDumpState(OBJGPU *pGpu, struct Intr *pIntr) { NV_STATUS intrCacheIntrFields_TU102(OBJGPU *pGpu, struct Intr *pIntr); + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrCacheIntrFields(OBJGPU *pGpu, struct Intr *pIntr) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -876,6 +927,7 @@ static inline NV_STATUS intrCacheIntrFields(OBJGPU *pGpu, struct Intr *pIntr) { NvU32 intrReadRegLeafEnSet_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, struct THREAD_STATE_NODE *arg1); + #ifdef __nvoc_intr_h_disabled static inline NvU32 intrReadRegLeafEnSet(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, struct THREAD_STATE_NODE *arg1) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -889,6 +941,7 @@ static inline NvU32 intrReadRegLeafEnSet(OBJGPU *pGpu, struct Intr *pIntr, NvU32 NvU32 intrReadRegLeaf_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, struct THREAD_STATE_NODE *arg1); + #ifdef __nvoc_intr_h_disabled static inline NvU32 intrReadRegLeaf(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, struct THREAD_STATE_NODE *arg1) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -902,6 +955,7 @@ static inline NvU32 intrReadRegLeaf(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0 NvU32 intrReadRegTop_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, struct THREAD_STATE_NODE *arg1); + #ifdef __nvoc_intr_h_disabled static inline NvU32 intrReadRegTop(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, struct THREAD_STATE_NODE *arg1) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -915,6 +969,7 @@ static inline NvU32 intrReadRegTop(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, void intrWriteRegLeafEnSet_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); + #ifdef __nvoc_intr_h_disabled static inline void intrWriteRegLeafEnSet(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -927,6 +982,7 @@ static inline void intrWriteRegLeafEnSet(OBJGPU *pGpu, struct Intr *pIntr, NvU32 void intrWriteRegLeafEnClear_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); + #ifdef __nvoc_intr_h_disabled static inline void intrWriteRegLeafEnClear(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -939,6 +995,7 @@ static inline void intrWriteRegLeafEnClear(OBJGPU *pGpu, struct Intr *pIntr, NvU void intrWriteRegLeaf_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); + #ifdef __nvoc_intr_h_disabled static inline void intrWriteRegLeaf(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -953,6 +1010,9 @@ static inline NvU32 intrUpdateIntrCtrlValue_4a4dee(OBJGPU *pGpu, struct Intr *pI return 0; } +NvU32 intrUpdateIntrCtrlValue_GH100(OBJGPU *pGpu, struct Intr *pIntr, NvU32 intrCtrl, NvU32 routing); + + #ifdef __nvoc_intr_h_disabled static inline NvU32 intrUpdateIntrCtrlValue(OBJGPU *pGpu, struct Intr *pIntr, NvU32 intrCtrl, NvU32 routing) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -968,6 +1028,9 @@ static inline void intrSetRouting_b3696a(OBJGPU *pGpu, struct Intr *pIntr, NvU32 return; } +void intrSetRouting_GH100(OBJGPU *pGpu, struct Intr *pIntr, NvU32 intrCtrl, NvU32 intrCtrlReg, NvU32 routing); + + #ifdef __nvoc_intr_h_disabled static inline void intrSetRouting(OBJGPU *pGpu, struct Intr *pIntr, NvU32 intrCtrl, NvU32 intrCtrlReg, NvU32 routing) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -982,6 +1045,9 @@ static inline void intrRouteFBInterruptsToSystemFirmware_b3696a(OBJGPU *pGpu, st return; } +void intrRouteFBInterruptsToSystemFirmware_GH100(OBJGPU *pGpu, struct Intr *pIntr, NvBool bEnable); + + #ifdef __nvoc_intr_h_disabled static inline void intrRouteFBInterruptsToSystemFirmware(OBJGPU *pGpu, struct Intr *pIntr, NvBool bEnable) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -996,6 +1062,7 @@ static inline NV_STATUS intrInitDynamicInterruptTable_5baef9(OBJGPU *pGpu, struc NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrInitDynamicInterruptTable(OBJGPU *pGpu, struct Intr *pIntr, struct OBJFIFO *arg0, INTR_TABLE_ENTRY *arg1, NvU32 arg2, NvU32 initFlags) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1011,6 +1078,7 @@ static inline NV_STATUS intrInitAnyInterruptTable_5baef9(OBJGPU *pGpu, struct In NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrInitAnyInterruptTable(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY **ppIntrTable, NvU32 *pIntrTableSz, NvU32 initFlags) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1024,6 +1092,7 @@ static inline NV_STATUS intrInitAnyInterruptTable(OBJGPU *pGpu, struct Intr *pIn NV_STATUS intrInitInterruptTable_KERNEL(OBJGPU *pGpu, struct Intr *pIntr); + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrInitInterruptTable(OBJGPU *pGpu, struct Intr *pIntr) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1037,6 +1106,7 @@ static inline NV_STATUS intrInitInterruptTable(OBJGPU *pGpu, struct Intr *pIntr) NV_STATUS intrGetInterruptTable_IMPL(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY **arg0, NvU32 *arg1); + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrGetInterruptTable(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY **arg0, NvU32 *arg1) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1050,6 +1120,7 @@ static inline NV_STATUS intrGetInterruptTable(OBJGPU *pGpu, struct Intr *pIntr, NV_STATUS intrDestroyInterruptTable_IMPL(OBJGPU *pGpu, struct Intr *pIntr); + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrDestroyInterruptTable(OBJGPU *pGpu, struct Intr *pIntr) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1065,6 +1136,11 @@ static inline NV_STATUS intrGetStaticVFmcEngines_5baef9(OBJGPU *pGpu, struct Int NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } +NV_STATUS intrGetStaticVFmcEngines_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU16 **ppMcEngines, NvU32 *pCount); + +NV_STATUS intrGetStaticVFmcEngines_GA100(OBJGPU *pGpu, struct Intr *pIntr, NvU16 **ppMcEngines, NvU32 *pCount); + + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrGetStaticVFmcEngines(OBJGPU *pGpu, struct Intr *pIntr, NvU16 **ppMcEngines, NvU32 *pCount) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1080,6 +1156,15 @@ static inline NV_STATUS intrGetStaticInterruptTable_5baef9(OBJGPU *pGpu, struct NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } +NV_STATUS intrGetStaticInterruptTable_TU102(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY *pTable, NvU32 *pCount, NvU32 maxCount, NvU32 initFlags); + +NV_STATUS intrGetStaticInterruptTable_GA100(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY *pTable, NvU32 *pCount, NvU32 maxCount, NvU32 initFlags); + +NV_STATUS intrGetStaticInterruptTable_GA102(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY *pTable, NvU32 *pCount, NvU32 maxCount, NvU32 initFlags); + +NV_STATUS intrGetStaticInterruptTable_GH100(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY *pTable, NvU32 *pCount, NvU32 maxCount, NvU32 initFlags); + + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrGetStaticInterruptTable(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY *pTable, NvU32 *pCount, NvU32 maxCount, NvU32 initFlags) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1095,6 +1180,11 @@ static inline NvU32 intrGetGPUHostInterruptTableSize_5baef9(OBJGPU *pGpu, struct NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } +NvU32 intrGetGPUHostInterruptTableSize_GM107(OBJGPU *pGpu, struct Intr *pIntr, NvU32 initFlags); + +NvU32 intrGetGPUHostInterruptTableSize_GA100(OBJGPU *pGpu, struct Intr *pIntr, NvU32 initFlags); + + #ifdef __nvoc_intr_h_disabled static inline NvU32 intrGetGPUHostInterruptTableSize(OBJGPU *pGpu, struct Intr *pIntr, NvU32 initFlags) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1110,6 +1200,11 @@ static inline NV_STATUS intrInitGPUHostInterruptTable_5baef9(OBJGPU *pGpu, struc NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } +NV_STATUS intrInitGPUHostInterruptTable_GM107(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY *arg0, NvU32 arg1, NvU32 initFlags); + +NV_STATUS intrInitGPUHostInterruptTable_GA100(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY *arg0, NvU32 arg1, NvU32 initFlags); + + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrInitGPUHostInterruptTable(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY *arg0, NvU32 arg1, NvU32 initFlags) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1125,6 +1220,7 @@ static inline NV_STATUS intrInitEngineSchedInterruptTable_5baef9(OBJGPU *pGpu, s NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrInitEngineSchedInterruptTable(OBJGPU *pGpu, struct Intr *pIntr, INTR_TABLE_ENTRY *arg0, NvU32 arg1) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1138,6 +1234,7 @@ static inline NV_STATUS intrInitEngineSchedInterruptTable(OBJGPU *pGpu, struct I void intrServiceStall_IMPL(OBJGPU *pGpu, struct Intr *pIntr); + #ifdef __nvoc_intr_h_disabled static inline void intrServiceStall(OBJGPU *pGpu, struct Intr *pIntr) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1150,6 +1247,7 @@ static inline void intrServiceStall(OBJGPU *pGpu, struct Intr *pIntr) { void intrServiceStallList_IMPL(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0, NvBool arg1); + #ifdef __nvoc_intr_h_disabled static inline void intrServiceStallList(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0, NvBool arg1) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1162,6 +1260,7 @@ static inline void intrServiceStallList(OBJGPU *pGpu, struct Intr *pIntr, union void intrServiceStallSingle_IMPL(OBJGPU *pGpu, struct Intr *pIntr, NvU16 arg0, NvBool arg1); + #ifdef __nvoc_intr_h_disabled static inline void intrServiceStallSingle(OBJGPU *pGpu, struct Intr *pIntr, NvU16 arg0, NvBool arg1) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1174,6 +1273,7 @@ static inline void intrServiceStallSingle(OBJGPU *pGpu, struct Intr *pIntr, NvU1 void intrProcessDPCQueue_IMPL(OBJGPU *pGpu, struct Intr *pIntr); + #ifdef __nvoc_intr_h_disabled static inline void intrProcessDPCQueue(OBJGPU *pGpu, struct Intr *pIntr) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1186,6 +1286,7 @@ static inline void intrProcessDPCQueue(OBJGPU *pGpu, struct Intr *pIntr) { NV_STATUS intrGetIntrMask_GP100(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0, struct THREAD_STATE_NODE *arg1); + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrGetIntrMask(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0, struct THREAD_STATE_NODE *arg1) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1201,6 +1302,13 @@ static inline NV_STATUS intrGetEccIntrMaskOffset_5baef9(OBJGPU *pGpu, struct Int NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } +NV_STATUS intrGetEccIntrMaskOffset_GP100(OBJGPU *pGpu, struct Intr *pIntr, NvU32 *arg0, NvU32 *arg1); + +static inline NV_STATUS intrGetEccIntrMaskOffset_46f6a7(OBJGPU *pGpu, struct Intr *pIntr, NvU32 *arg0, NvU32 *arg1) { + return NV_ERR_NOT_SUPPORTED; +} + + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrGetEccIntrMaskOffset(OBJGPU *pGpu, struct Intr *pIntr, NvU32 *arg0, NvU32 *arg1) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1216,6 +1324,13 @@ static inline NV_STATUS intrGetNvlinkIntrMaskOffset_5baef9(OBJGPU *pGpu, struct NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } +NV_STATUS intrGetNvlinkIntrMaskOffset_GP100(OBJGPU *pGpu, struct Intr *pIntr, NvU32 *arg0, NvU32 *arg1); + +static inline NV_STATUS intrGetNvlinkIntrMaskOffset_46f6a7(OBJGPU *pGpu, struct Intr *pIntr, NvU32 *arg0, NvU32 *arg1) { + return NV_ERR_NOT_SUPPORTED; +} + + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrGetNvlinkIntrMaskOffset(OBJGPU *pGpu, struct Intr *pIntr, NvU32 *arg0, NvU32 *arg1) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1231,6 +1346,13 @@ static inline NV_STATUS intrGetEccVirtualFunctionIntrMask_5baef9(OBJGPU *pGpu, s NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } +NV_STATUS intrGetEccVirtualFunctionIntrMask_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvHandle arg0, NvU32 *arg1); + +NV_STATUS intrGetEccVirtualFunctionIntrMask_GA100(OBJGPU *pGpu, struct Intr *pIntr, NvHandle arg0, NvU32 *arg1); + +NV_STATUS intrGetEccVirtualFunctionIntrMask_GH100(OBJGPU *pGpu, struct Intr *pIntr, NvHandle arg0, NvU32 *arg1); + + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrGetEccVirtualFunctionIntrMask(OBJGPU *pGpu, struct Intr *pIntr, NvHandle arg0, NvU32 *arg1) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1246,6 +1368,13 @@ static inline NV_STATUS intrGetNvlinkVirtualFunctionIntrMask_5baef9(OBJGPU *pGpu NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } +NV_STATUS intrGetNvlinkVirtualFunctionIntrMask_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 *arg1); + +NV_STATUS intrGetNvlinkVirtualFunctionIntrMask_GA100(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 *arg1); + +NV_STATUS intrGetNvlinkVirtualFunctionIntrMask_GH100(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 *arg1); + + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrGetNvlinkVirtualFunctionIntrMask(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 *arg1) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1261,6 +1390,15 @@ static inline NvU32 intrGetEccVirtualFunctionIntrSmcMaskAll_5baef9(OBJGPU *pGpu, NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } +NvU32 intrGetEccVirtualFunctionIntrSmcMaskAll_GA100(OBJGPU *pGpu, struct Intr *pIntr); + +NvU32 intrGetEccVirtualFunctionIntrSmcMaskAll_GA102(OBJGPU *pGpu, struct Intr *pIntr); + +static inline NvU32 intrGetEccVirtualFunctionIntrSmcMaskAll_4a4dee(OBJGPU *pGpu, struct Intr *pIntr) { + return 0; +} + + #ifdef __nvoc_intr_h_disabled static inline NvU32 intrGetEccVirtualFunctionIntrSmcMaskAll(OBJGPU *pGpu, struct Intr *pIntr) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1276,6 +1414,13 @@ static inline NvBool intrRequiresPossibleErrorNotifier_491d52(OBJGPU *pGpu, stru return ((NvBool)(0 != 0)); } +NvBool intrRequiresPossibleErrorNotifier_TU102(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *pEngines); + +NvBool intrRequiresPossibleErrorNotifier_GA100(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *pEngines); + +NvBool intrRequiresPossibleErrorNotifier_GH100(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *pEngines); + + #ifdef __nvoc_intr_h_disabled static inline NvBool intrRequiresPossibleErrorNotifier(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *pEngines) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1291,6 +1436,9 @@ static inline NvU32 intrReadErrCont_491d52(OBJGPU *pGpu, struct Intr *pIntr) { return ((NvBool)(0 != 0)); } +NvU32 intrReadErrCont_TU102(OBJGPU *pGpu, struct Intr *pIntr); + + #ifdef __nvoc_intr_h_disabled static inline NvU32 intrReadErrCont(OBJGPU *pGpu, struct Intr *pIntr) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1304,6 +1452,7 @@ static inline NvU32 intrReadErrCont(OBJGPU *pGpu, struct Intr *pIntr) { NV_STATUS intrGetPendingStall_GP100(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0, struct THREAD_STATE_NODE *arg1); + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrGetPendingStall(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0, struct THREAD_STATE_NODE *arg1) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1317,6 +1466,7 @@ static inline NV_STATUS intrGetPendingStall(OBJGPU *pGpu, struct Intr *pIntr, un NV_STATUS intrGetPendingStallEngines_TU102(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0, struct THREAD_STATE_NODE *arg1); + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrGetPendingStallEngines(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0, struct THREAD_STATE_NODE *arg1) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1330,6 +1480,7 @@ static inline NV_STATUS intrGetPendingStallEngines(OBJGPU *pGpu, struct Intr *pI NvBool intrIsIntrEnabled_IMPL(OBJGPU *pGpu, struct Intr *pIntr, struct THREAD_STATE_NODE *arg0); + #ifdef __nvoc_intr_h_disabled static inline NvBool intrIsIntrEnabled(OBJGPU *pGpu, struct Intr *pIntr, struct THREAD_STATE_NODE *arg0) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1345,6 +1496,7 @@ static inline void intrSetHubLeafIntr_b3696a(OBJGPU *pGpu, struct Intr *pIntr, N return; } + #ifdef __nvoc_intr_h_disabled static inline void intrSetHubLeafIntr(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 *arg1, NvU32 *arg2, struct THREAD_STATE_NODE *arg3) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1357,6 +1509,7 @@ static inline void intrSetHubLeafIntr(OBJGPU *pGpu, struct Intr *pIntr, NvU32 ar void intrGetHubLeafIntrPending_STUB(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0, struct THREAD_STATE_NODE *arg1); + #ifdef __nvoc_intr_h_disabled static inline void intrGetHubLeafIntrPending(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0, struct THREAD_STATE_NODE *arg1) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1407,10 +1560,6 @@ static inline NvU32 intrGetNonStallBaseVector_c067f9(OBJGPU *pGpu, struct Intr * NV_ASSERT_OR_RETURN_PRECOMP(0, 0); } -static inline NvU32 intrGetNonStallBaseVector_4a4dee(OBJGPU *pGpu, struct Intr *pIntr) { - return 0; -} - static inline NvU32 intrGetNonStallBaseVector_DISPATCH(OBJGPU *pGpu, struct Intr *pIntr) { return pIntr->__intrGetNonStallBaseVector__(pGpu, pIntr); } @@ -1419,10 +1568,6 @@ NvU64 intrGetUvmSharedLeafEnDisableMask_TU102(OBJGPU *pGpu, struct Intr *pIntr); NvU64 intrGetUvmSharedLeafEnDisableMask_GA100(OBJGPU *pGpu, struct Intr *pIntr); -static inline NvU64 intrGetUvmSharedLeafEnDisableMask_5baef9(OBJGPU *pGpu, struct Intr *pIntr) { - NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); -} - static inline NvU64 intrGetUvmSharedLeafEnDisableMask_DISPATCH(OBJGPU *pGpu, struct Intr *pIntr) { return pIntr->__intrGetUvmSharedLeafEnDisableMask__(pGpu, pIntr); } @@ -1441,10 +1586,6 @@ NvU32 intrReadRegTopEnSet_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, st NvU32 intrReadRegTopEnSet_GA102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, struct THREAD_STATE_NODE *arg1); -static inline NvU32 intrReadRegTopEnSet_b2b553(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, struct THREAD_STATE_NODE *arg1) { - return 0; -} - static inline NvU32 intrReadRegTopEnSet_DISPATCH(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, struct THREAD_STATE_NODE *arg1) { return pIntr->__intrReadRegTopEnSet__(pGpu, pIntr, arg0, arg1); } @@ -1453,10 +1594,6 @@ void intrWriteRegTopEnSet_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, Nv void intrWriteRegTopEnSet_GA102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); -static inline void intrWriteRegTopEnSet_d44104(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2) { - return; -} - static inline void intrWriteRegTopEnSet_DISPATCH(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2) { pIntr->__intrWriteRegTopEnSet__(pGpu, pIntr, arg0, arg1, arg2); } @@ -1465,10 +1602,6 @@ void intrWriteRegTopEnClear_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, void intrWriteRegTopEnClear_GA102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); -static inline void intrWriteRegTopEnClear_d44104(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2) { - return; -} - static inline void intrWriteRegTopEnClear_DISPATCH(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2) { pIntr->__intrWriteRegTopEnClear__(pGpu, pIntr, arg0, arg1, arg2); } @@ -1477,10 +1610,6 @@ NvU32 intrGetStallSubtreeLast_TU102(OBJGPU *pGpu, struct Intr *pIntr); NvU32 intrGetStallSubtreeLast_GH100(OBJGPU *pGpu, struct Intr *pIntr); -static inline NvU32 intrGetStallSubtreeLast_474d46(OBJGPU *pGpu, struct Intr *pIntr) { - NV_ASSERT_OR_RETURN_PRECOMP(0, 0); -} - static inline NvU32 intrGetStallSubtreeLast_DISPATCH(OBJGPU *pGpu, struct Intr *pIntr) { return pIntr->__intrGetStallSubtreeLast__(pGpu, pIntr); } @@ -1489,10 +1618,6 @@ NvU32 intrGetNumLeaves_TU102(OBJGPU *pGpu, struct Intr *pIntr); NvU32 intrGetNumLeaves_GH100(OBJGPU *pGpu, struct Intr *pIntr); -static inline NvU32 intrGetNumLeaves_474d46(OBJGPU *pGpu, struct Intr *pIntr) { - NV_ASSERT_OR_RETURN_PRECOMP(0, 0); -} - static inline NvU32 intrGetNumLeaves_DISPATCH(OBJGPU *pGpu, struct Intr *pIntr) { return pIntr->__intrGetNumLeaves__(pGpu, pIntr); } @@ -1501,10 +1626,6 @@ NvU32 intrGetLeafSize_TU102(OBJGPU *pGpu, struct Intr *pIntr); NvU32 intrGetLeafSize_GH100(OBJGPU *pGpu, struct Intr *pIntr); -static inline NvU32 intrGetLeafSize_474d46(OBJGPU *pGpu, struct Intr *pIntr) { - NV_ASSERT_OR_RETURN_PRECOMP(0, 0); -} - static inline NvU32 intrGetLeafSize_DISPATCH(OBJGPU *pGpu, struct Intr *pIntr) { return pIntr->__intrGetLeafSize__(pGpu, pIntr); } @@ -1513,10 +1634,6 @@ NvU32 intrGetIntrTopNonStallMask_TU102(OBJGPU *pGpu, struct Intr *pIntr); NvU32 intrGetIntrTopNonStallMask_GH100(OBJGPU *pGpu, struct Intr *pIntr); -static inline NvU32 intrGetIntrTopNonStallMask_474d46(OBJGPU *pGpu, struct Intr *pIntr) { - NV_ASSERT_OR_RETURN_PRECOMP(0, 0); -} - static inline NvU32 intrGetIntrTopNonStallMask_DISPATCH(OBJGPU *pGpu, struct Intr *pIntr) { return pIntr->__intrGetIntrTopNonStallMask__(pGpu, pIntr); } @@ -1547,20 +1664,12 @@ static inline void intrSanityCheckEngineIntrNotificationVector_DISPATCH(OBJGPU * NV_STATUS intrStateLoad_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0); -static inline NV_STATUS intrStateLoad_56cd7a(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0) { - return NV_OK; -} - static inline NV_STATUS intrStateLoad_DISPATCH(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0) { return pIntr->__intrStateLoad__(pGpu, pIntr, arg0); } NV_STATUS intrStateUnload_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0); -static inline NV_STATUS intrStateUnload_56cd7a(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0) { - return NV_OK; -} - static inline NV_STATUS intrStateUnload_DISPATCH(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0) { return pIntr->__intrStateUnload__(pGpu, pIntr, arg0); } @@ -1652,8 +1761,10 @@ static inline NvBool intrIsPresent_DISPATCH(POBJGPU pGpu, struct Intr *pEngstate } void intrDestruct_IMPL(struct Intr *pIntr); + #define __nvoc_intrDestruct(pIntr) intrDestruct_IMPL(pIntr) NV_STATUS intrServiceNonStallBottomHalf_IMPL(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0, struct THREAD_STATE_NODE *arg1); + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrServiceNonStallBottomHalf(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0, struct THREAD_STATE_NODE *arg1) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1664,6 +1775,7 @@ static inline NV_STATUS intrServiceNonStallBottomHalf(OBJGPU *pGpu, struct Intr #endif //__nvoc_intr_h_disabled NV_STATUS intrServiceNotificationRecords_IMPL(OBJGPU *pGpu, struct Intr *pIntr, NvU16 mcEngineIdx, struct THREAD_STATE_NODE *arg0); + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrServiceNotificationRecords(OBJGPU *pGpu, struct Intr *pIntr, NvU16 mcEngineIdx, struct THREAD_STATE_NODE *arg0) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1674,6 +1786,7 @@ static inline NV_STATUS intrServiceNotificationRecords(OBJGPU *pGpu, struct Intr #endif //__nvoc_intr_h_disabled void intrServiceStallListAllGpusCond_IMPL(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0, NvBool arg1); + #ifdef __nvoc_intr_h_disabled static inline void intrServiceStallListAllGpusCond(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0, NvBool arg1) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1683,6 +1796,7 @@ static inline void intrServiceStallListAllGpusCond(OBJGPU *pGpu, struct Intr *pI #endif //__nvoc_intr_h_disabled void intrServiceStallListDevice_IMPL(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0, NvBool arg1); + #ifdef __nvoc_intr_h_disabled static inline void intrServiceStallListDevice(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0, NvBool arg1) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1692,6 +1806,7 @@ static inline void intrServiceStallListDevice(OBJGPU *pGpu, struct Intr *pIntr, #endif //__nvoc_intr_h_disabled NvU32 intrServiceInterruptRecords_IMPL(OBJGPU *pGpu, struct Intr *pIntr, NvU16 arg0, NvBool *arg1); + #ifdef __nvoc_intr_h_disabled static inline NvU32 intrServiceInterruptRecords(OBJGPU *pGpu, struct Intr *pIntr, NvU16 arg0, NvBool *arg1) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1702,6 +1817,7 @@ static inline NvU32 intrServiceInterruptRecords(OBJGPU *pGpu, struct Intr *pIntr #endif //__nvoc_intr_h_disabled void intrQueueDpc_IMPL(OBJGPU *pGpu, struct Intr *pIntr, DPCQUEUE *arg0, DPCNODE *arg1); + #ifdef __nvoc_intr_h_disabled static inline void intrQueueDpc(OBJGPU *pGpu, struct Intr *pIntr, DPCQUEUE *arg0, DPCNODE *arg1) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1711,6 +1827,7 @@ static inline void intrQueueDpc(OBJGPU *pGpu, struct Intr *pIntr, DPCQUEUE *arg0 #endif //__nvoc_intr_h_disabled DPCNODE *intrDequeueDpc_IMPL(OBJGPU *pGpu, struct Intr *pIntr, DPCQUEUE *arg0); + #ifdef __nvoc_intr_h_disabled static inline DPCNODE *intrDequeueDpc(OBJGPU *pGpu, struct Intr *pIntr, DPCQUEUE *arg0) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1721,6 +1838,7 @@ static inline DPCNODE *intrDequeueDpc(OBJGPU *pGpu, struct Intr *pIntr, DPCQUEUE #endif //__nvoc_intr_h_disabled NvBool intrIsDpcQueueEmpty_IMPL(OBJGPU *pGpu, struct Intr *pIntr, DPCQUEUE *arg0); + #ifdef __nvoc_intr_h_disabled static inline NvBool intrIsDpcQueueEmpty(OBJGPU *pGpu, struct Intr *pIntr, DPCQUEUE *arg0) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1731,6 +1849,7 @@ static inline NvBool intrIsDpcQueueEmpty(OBJGPU *pGpu, struct Intr *pIntr, DPCQU #endif //__nvoc_intr_h_disabled void intrQueueInterruptBasedDpc_IMPL(OBJGPU *pGpu, struct Intr *pIntr, NvU16 arg0); + #ifdef __nvoc_intr_h_disabled static inline void intrQueueInterruptBasedDpc(OBJGPU *pGpu, struct Intr *pIntr, NvU16 arg0) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1740,6 +1859,7 @@ static inline void intrQueueInterruptBasedDpc(OBJGPU *pGpu, struct Intr *pIntr, #endif //__nvoc_intr_h_disabled NvU32 intrConvertEngineMaskToPmcIntrMask_IMPL(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0); + #ifdef __nvoc_intr_h_disabled static inline NvU32 intrConvertEngineMaskToPmcIntrMask(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1750,6 +1870,7 @@ static inline NvU32 intrConvertEngineMaskToPmcIntrMask(OBJGPU *pGpu, struct Intr #endif //__nvoc_intr_h_disabled void intrConvertPmcIntrMaskToEngineMask_IMPL(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, union MC_ENGINE_BITVECTOR *arg1); + #ifdef __nvoc_intr_h_disabled static inline void intrConvertPmcIntrMaskToEngineMask(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, union MC_ENGINE_BITVECTOR *arg1) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1759,6 +1880,7 @@ static inline void intrConvertPmcIntrMaskToEngineMask(OBJGPU *pGpu, struct Intr #endif //__nvoc_intr_h_disabled NvU32 intrGetVectorFromEngineId_IMPL(OBJGPU *pGpu, struct Intr *pIntr, NvU16 mcEngineId, NvBool bNonStall); + #ifdef __nvoc_intr_h_disabled static inline NvU32 intrGetVectorFromEngineId(OBJGPU *pGpu, struct Intr *pIntr, NvU16 mcEngineId, NvBool bNonStall) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1769,6 +1891,7 @@ static inline NvU32 intrGetVectorFromEngineId(OBJGPU *pGpu, struct Intr *pIntr, #endif //__nvoc_intr_h_disabled NV_STATUS intrGetSmallestNotificationVector_IMPL(OBJGPU *pGpu, struct Intr *pIntr, NvU32 *arg0); + #ifdef __nvoc_intr_h_disabled static inline NV_STATUS intrGetSmallestNotificationVector(OBJGPU *pGpu, struct Intr *pIntr, NvU32 *arg0) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1779,6 +1902,7 @@ static inline NV_STATUS intrGetSmallestNotificationVector(OBJGPU *pGpu, struct I #endif //__nvoc_intr_h_disabled void intrSetIntrMaskUnblocked_IMPL(struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0); + #ifdef __nvoc_intr_h_disabled static inline void intrSetIntrMaskUnblocked(struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1788,6 +1912,7 @@ static inline void intrSetIntrMaskUnblocked(struct Intr *pIntr, union MC_ENGINE_ #endif //__nvoc_intr_h_disabled void intrGetIntrMaskUnblocked_IMPL(struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0); + #ifdef __nvoc_intr_h_disabled static inline void intrGetIntrMaskUnblocked(struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1797,6 +1922,7 @@ static inline void intrGetIntrMaskUnblocked(struct Intr *pIntr, union MC_ENGINE_ #endif //__nvoc_intr_h_disabled void intrSetIntrMaskFlags_IMPL(struct Intr *pIntr, NvU32 arg0); + #ifdef __nvoc_intr_h_disabled static inline void intrSetIntrMaskFlags(struct Intr *pIntr, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1806,6 +1932,7 @@ static inline void intrSetIntrMaskFlags(struct Intr *pIntr, NvU32 arg0) { #endif //__nvoc_intr_h_disabled NvU32 intrGetIntrMaskFlags_IMPL(struct Intr *pIntr); + #ifdef __nvoc_intr_h_disabled static inline NvU32 intrGetIntrMaskFlags(struct Intr *pIntr) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1816,6 +1943,7 @@ static inline NvU32 intrGetIntrMaskFlags(struct Intr *pIntr) { #endif //__nvoc_intr_h_disabled void intrSetDefaultIntrEn_IMPL(struct Intr *pIntr, NvU32 arg0); + #ifdef __nvoc_intr_h_disabled static inline void intrSetDefaultIntrEn(struct Intr *pIntr, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1825,6 +1953,7 @@ static inline void intrSetDefaultIntrEn(struct Intr *pIntr, NvU32 arg0) { #endif //__nvoc_intr_h_disabled NvU32 intrGetDefaultIntrEn_IMPL(struct Intr *pIntr); + #ifdef __nvoc_intr_h_disabled static inline NvU32 intrGetDefaultIntrEn(struct Intr *pIntr) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1835,6 +1964,7 @@ static inline NvU32 intrGetDefaultIntrEn(struct Intr *pIntr) { #endif //__nvoc_intr_h_disabled void intrSetIntrEn_IMPL(struct Intr *pIntr, NvU32 arg0); + #ifdef __nvoc_intr_h_disabled static inline void intrSetIntrEn(struct Intr *pIntr, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1844,6 +1974,7 @@ static inline void intrSetIntrEn(struct Intr *pIntr, NvU32 arg0) { #endif //__nvoc_intr_h_disabled NvU32 intrGetIntrEn_IMPL(struct Intr *pIntr); + #ifdef __nvoc_intr_h_disabled static inline NvU32 intrGetIntrEn(struct Intr *pIntr) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1854,6 +1985,7 @@ static inline NvU32 intrGetIntrEn(struct Intr *pIntr) { #endif //__nvoc_intr_h_disabled void intrSaveIntrEn0FromHw_IMPL(OBJGPU *pGpu, struct Intr *pIntr); + #ifdef __nvoc_intr_h_disabled static inline void intrSaveIntrEn0FromHw(OBJGPU *pGpu, struct Intr *pIntr) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); @@ -1863,6 +1995,7 @@ static inline void intrSaveIntrEn0FromHw(OBJGPU *pGpu, struct Intr *pIntr) { #endif //__nvoc_intr_h_disabled void intrGetGmmuInterrupts_IMPL(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0, struct THREAD_STATE_NODE *arg1); + #ifdef __nvoc_intr_h_disabled static inline void intrGetGmmuInterrupts(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0, struct THREAD_STATE_NODE *arg1) { NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); diff --git a/src/nvidia/generated/g_intr_service_nvoc.h b/src/nvidia/generated/g_intr_service_nvoc.h index 214be5ad0..4d33474a3 100644 --- a/src/nvidia/generated/g_intr_service_nvoc.h +++ b/src/nvidia/generated/g_intr_service_nvoc.h @@ -122,9 +122,9 @@ NV_STATUS __nvoc_objCreate_IntrService(IntrService**, Dynamic*, NvU32); #define intrservClearInterrupt(pGpu, pIntrService, pParams) intrservClearInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define intrservServiceInterrupt(pGpu, pIntrService, pParams) intrservServiceInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define intrservServiceNotificationInterrupt(pGpu, pIntrService, pParams) intrservServiceNotificationInterrupt_DISPATCH(pGpu, pIntrService, pParams) -void intrservRegisterIntrService_IMPL(struct OBJGPU *pGpu, struct IntrService *pIntrService, IntrServiceRecord pRecords[155]); +void intrservRegisterIntrService_IMPL(struct OBJGPU *pGpu, struct IntrService *pIntrService, IntrServiceRecord pRecords[163]); -static inline void intrservRegisterIntrService_DISPATCH(struct OBJGPU *pGpu, struct IntrService *pIntrService, IntrServiceRecord pRecords[155]) { +static inline void intrservRegisterIntrService_DISPATCH(struct OBJGPU *pGpu, struct IntrService *pIntrService, IntrServiceRecord pRecords[163]) { pIntrService->__intrservRegisterIntrService__(pGpu, pIntrService, pRecords); } diff --git a/src/nvidia/generated/g_intrable_nvoc.c b/src/nvidia/generated/g_intrable_nvoc.c deleted file mode 100644 index 916ac4e2f..000000000 --- a/src/nvidia/generated/g_intrable_nvoc.c +++ /dev/null @@ -1,118 +0,0 @@ -#define NVOC_INTRABLE_H_PRIVATE_ACCESS_ALLOWED -#include "nvoc/runtime.h" -#include "nvoc/rtti.h" -#include "nvtypes.h" -#include "nvport/nvport.h" -#include "nvport/inline/util_valist.h" -#include "utils/nvassert.h" -#include "g_intrable_nvoc.h" - -#ifdef DEBUG -char __nvoc_class_id_uniqueness_check_0x31ccb7 = 1; -#endif - -extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJINTRABLE; - -void __nvoc_init_OBJINTRABLE(OBJINTRABLE*, RmHalspecOwner* ); -void __nvoc_init_funcTable_OBJINTRABLE(OBJINTRABLE*, RmHalspecOwner* ); -NV_STATUS __nvoc_ctor_OBJINTRABLE(OBJINTRABLE*, RmHalspecOwner* ); -void __nvoc_init_dataField_OBJINTRABLE(OBJINTRABLE*, RmHalspecOwner* ); -void __nvoc_dtor_OBJINTRABLE(OBJINTRABLE*); -extern const struct NVOC_EXPORT_INFO __nvoc_export_info_OBJINTRABLE; - -static const struct NVOC_RTTI __nvoc_rtti_OBJINTRABLE_OBJINTRABLE = { - /*pClassDef=*/ &__nvoc_class_def_OBJINTRABLE, - /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_OBJINTRABLE, - /*offset=*/ 0, -}; - -static const struct NVOC_CASTINFO __nvoc_castinfo_OBJINTRABLE = { - /*numRelatives=*/ 1, - /*relatives=*/ { - &__nvoc_rtti_OBJINTRABLE_OBJINTRABLE, - }, -}; - -// Not instantiable because it's not derived from class "Object" -const struct NVOC_CLASS_DEF __nvoc_class_def_OBJINTRABLE = -{ - /*classInfo=*/ { - /*size=*/ sizeof(OBJINTRABLE), - /*classId=*/ classId(OBJINTRABLE), - /*providerId=*/ &__nvoc_rtti_provider, -#if NV_PRINTF_STRINGS_ALLOWED - /*name=*/ "OBJINTRABLE", -#endif - }, - /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) NULL, - /*pCastInfo=*/ &__nvoc_castinfo_OBJINTRABLE, - /*pExportInfo=*/ &__nvoc_export_info_OBJINTRABLE -}; - -const struct NVOC_EXPORT_INFO __nvoc_export_info_OBJINTRABLE = -{ - /*numEntries=*/ 0, - /*pExportEntries=*/ 0 -}; - -void __nvoc_dtor_OBJINTRABLE(OBJINTRABLE *pThis) { - PORT_UNREFERENCED_VARIABLE(pThis); -} - -void __nvoc_init_dataField_OBJINTRABLE(OBJINTRABLE *pThis, RmHalspecOwner *pRmhalspecowner) { - RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; - const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; - ChipHal *chipHal = &pRmhalspecowner->chipHal; - const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; - PORT_UNREFERENCED_VARIABLE(pThis); - PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); - PORT_UNREFERENCED_VARIABLE(rmVariantHal); - PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); - PORT_UNREFERENCED_VARIABLE(chipHal); - PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); -} - -NV_STATUS __nvoc_ctor_OBJINTRABLE(OBJINTRABLE *pThis, RmHalspecOwner *pRmhalspecowner) { - NV_STATUS status = NV_OK; - __nvoc_init_dataField_OBJINTRABLE(pThis, pRmhalspecowner); - - status = __nvoc_intrableConstruct(pThis); - if (status != NV_OK) goto __nvoc_ctor_OBJINTRABLE_fail__init; - goto __nvoc_ctor_OBJINTRABLE_exit; // Success - -__nvoc_ctor_OBJINTRABLE_fail__init: -__nvoc_ctor_OBJINTRABLE_exit: - - return status; -} - -static void __nvoc_init_funcTable_OBJINTRABLE_1(OBJINTRABLE *pThis, RmHalspecOwner *pRmhalspecowner) { - RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; - const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; - ChipHal *chipHal = &pRmhalspecowner->chipHal; - const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; - PORT_UNREFERENCED_VARIABLE(pThis); - PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); - PORT_UNREFERENCED_VARIABLE(rmVariantHal); - PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); - PORT_UNREFERENCED_VARIABLE(chipHal); - PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); - - pThis->__intrableGetNotificationIntrVector__ = &intrableGetNotificationIntrVector_IMPL; - - pThis->__intrableGetPhysicalIntrVectors__ = &intrableGetPhysicalIntrVectors_IMPL; - - pThis->__intrableGetKernelIntrVectors__ = &intrableGetKernelIntrVectors_IMPL; - - pThis->__intrableSetNotificationIntrVector__ = &intrableSetNotificationIntrVector_IMPL; -} - -void __nvoc_init_funcTable_OBJINTRABLE(OBJINTRABLE *pThis, RmHalspecOwner *pRmhalspecowner) { - __nvoc_init_funcTable_OBJINTRABLE_1(pThis, pRmhalspecowner); -} - -void __nvoc_init_OBJINTRABLE(OBJINTRABLE *pThis, RmHalspecOwner *pRmhalspecowner) { - pThis->__nvoc_pbase_OBJINTRABLE = pThis; - __nvoc_init_funcTable_OBJINTRABLE(pThis, pRmhalspecowner); -} - diff --git a/src/nvidia/generated/g_intrable_nvoc.h b/src/nvidia/generated/g_intrable_nvoc.h deleted file mode 100644 index 81687e343..000000000 --- a/src/nvidia/generated/g_intrable_nvoc.h +++ /dev/null @@ -1,208 +0,0 @@ -#ifndef _G_INTRABLE_NVOC_H_ -#define _G_INTRABLE_NVOC_H_ -#include "nvoc/runtime.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * SPDX-FileCopyrightText: Copyright (c) 2019-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "g_intrable_nvoc.h" - -#ifndef INTRABLE_H -#define INTRABLE_H - -/*! - * @file intrable.h - * @brief Provides definitions for all OBJINTRABLE data structures and interfaces. - */ - -#include "core/core.h" -#include "gpu/gpu_halspec.h" - -typedef struct OBJINTRABLE *POBJINTRABLE; - -/*! - * Interface class for all Intrable modules. - */ -#ifdef NVOC_INTRABLE_H_PRIVATE_ACCESS_ALLOWED -#define PRIVATE_FIELD(x) x -#else -#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) -#endif -struct OBJINTRABLE { - const struct NVOC_RTTI *__nvoc_rtti; - struct OBJINTRABLE *__nvoc_pbase_OBJINTRABLE; - NV_STATUS (*__intrableGetNotificationIntrVector__)(OBJGPU *, struct OBJINTRABLE *, NvU32 *); - NV_STATUS (*__intrableGetPhysicalIntrVectors__)(OBJGPU *, struct OBJINTRABLE *, NvU32, NvU32 *, NvU32 *, NvU32 *); - NV_STATUS (*__intrableGetKernelIntrVectors__)(OBJGPU *, struct OBJINTRABLE *, NvU32, NvU32 *, NvU32 *, NvU32 *); - NV_STATUS (*__intrableSetNotificationIntrVector__)(OBJGPU *, struct OBJINTRABLE *, NvU32); - NvU32 partitionAssignedNotificationVector; - NvU32 originalNotificationIntrVector; -}; - -#ifndef __NVOC_CLASS_OBJINTRABLE_TYPEDEF__ -#define __NVOC_CLASS_OBJINTRABLE_TYPEDEF__ -typedef struct OBJINTRABLE OBJINTRABLE; -#endif /* __NVOC_CLASS_OBJINTRABLE_TYPEDEF__ */ - -#ifndef __nvoc_class_id_OBJINTRABLE -#define __nvoc_class_id_OBJINTRABLE 0x31ccb7 -#endif /* __nvoc_class_id_OBJINTRABLE */ - -extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJINTRABLE; - -#define __staticCast_OBJINTRABLE(pThis) \ - ((pThis)->__nvoc_pbase_OBJINTRABLE) - -#ifdef __nvoc_intrable_h_disabled -#define __dynamicCast_OBJINTRABLE(pThis) ((OBJINTRABLE*)NULL) -#else //__nvoc_intrable_h_disabled -#define __dynamicCast_OBJINTRABLE(pThis) \ - ((OBJINTRABLE*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(OBJINTRABLE))) -#endif //__nvoc_intrable_h_disabled - - -NV_STATUS __nvoc_objCreateDynamic_OBJINTRABLE(OBJINTRABLE**, Dynamic*, NvU32, va_list); - -NV_STATUS __nvoc_objCreate_OBJINTRABLE(OBJINTRABLE**, Dynamic*, NvU32); -#define __objCreate_OBJINTRABLE(ppNewObj, pParent, createFlags) \ - __nvoc_objCreate_OBJINTRABLE((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) - -#define intrableGetNotificationIntrVector(pGpu, pIntrable, pIntrVector) intrableGetNotificationIntrVector_DISPATCH(pGpu, pIntrable, pIntrVector) -#define intrableGetPhysicalIntrVectors(pGpu, pIntrable, maxIntrs, pIntrs, pMcEngineIdxs, pCount) intrableGetPhysicalIntrVectors_DISPATCH(pGpu, pIntrable, maxIntrs, pIntrs, pMcEngineIdxs, pCount) -#define intrableGetKernelIntrVectors(pGpu, pIntrable, maxIntrs, pIntrs, pMcEngineIdxs, pCount) intrableGetKernelIntrVectors_DISPATCH(pGpu, pIntrable, maxIntrs, pIntrs, pMcEngineIdxs, pCount) -#define intrableSetNotificationIntrVector(pGpu, pIntrable, intrVector) intrableSetNotificationIntrVector_DISPATCH(pGpu, pIntrable, intrVector) -static inline NvU32 intrableUpdateIntrCtrlValue_4a4dee(OBJGPU *pGpu, struct OBJINTRABLE *pIntrable, NvU32 intrCtrl, NvU32 routing) { - return 0; -} - -#ifdef __nvoc_intrable_h_disabled -static inline NvU32 intrableUpdateIntrCtrlValue(OBJGPU *pGpu, struct OBJINTRABLE *pIntrable, NvU32 intrCtrl, NvU32 routing) { - NV_ASSERT_FAILED_PRECOMP("OBJINTRABLE was disabled!"); - return 0; -} -#else //__nvoc_intrable_h_disabled -#define intrableUpdateIntrCtrlValue(pGpu, pIntrable, intrCtrl, routing) intrableUpdateIntrCtrlValue_4a4dee(pGpu, pIntrable, intrCtrl, routing) -#endif //__nvoc_intrable_h_disabled - -#define intrableUpdateIntrCtrlValue_HAL(pGpu, pIntrable, intrCtrl, routing) intrableUpdateIntrCtrlValue(pGpu, pIntrable, intrCtrl, routing) - -static inline void intrableSetRouting_b3696a(OBJGPU *pGpu, struct OBJINTRABLE *pIntrable, NvU32 intrCtrl, NvU32 intrCtrlReg, NvU32 routing) { - return; -} - -#ifdef __nvoc_intrable_h_disabled -static inline void intrableSetRouting(OBJGPU *pGpu, struct OBJINTRABLE *pIntrable, NvU32 intrCtrl, NvU32 intrCtrlReg, NvU32 routing) { - NV_ASSERT_FAILED_PRECOMP("OBJINTRABLE was disabled!"); -} -#else //__nvoc_intrable_h_disabled -#define intrableSetRouting(pGpu, pIntrable, intrCtrl, intrCtrlReg, routing) intrableSetRouting_b3696a(pGpu, pIntrable, intrCtrl, intrCtrlReg, routing) -#endif //__nvoc_intrable_h_disabled - -#define intrableSetRouting_HAL(pGpu, pIntrable, intrCtrl, intrCtrlReg, routing) intrableSetRouting(pGpu, pIntrable, intrCtrl, intrCtrlReg, routing) - -NV_STATUS intrableGetNotificationIntrVector_IMPL(OBJGPU *pGpu, struct OBJINTRABLE *pIntrable, NvU32 *pIntrVector); - -static inline NV_STATUS intrableGetNotificationIntrVector_DISPATCH(OBJGPU *pGpu, struct OBJINTRABLE *pIntrable, NvU32 *pIntrVector) { - return pIntrable->__intrableGetNotificationIntrVector__(pGpu, pIntrable, pIntrVector); -} - -NV_STATUS intrableGetPhysicalIntrVectors_IMPL(OBJGPU *pGpu, struct OBJINTRABLE *pIntrable, NvU32 maxIntrs, NvU32 *pIntrs, NvU32 *pMcEngineIdxs, NvU32 *pCount); - -static inline NV_STATUS intrableGetPhysicalIntrVectors_DISPATCH(OBJGPU *pGpu, struct OBJINTRABLE *pIntrable, NvU32 maxIntrs, NvU32 *pIntrs, NvU32 *pMcEngineIdxs, NvU32 *pCount) { - return pIntrable->__intrableGetPhysicalIntrVectors__(pGpu, pIntrable, maxIntrs, pIntrs, pMcEngineIdxs, pCount); -} - -NV_STATUS intrableGetKernelIntrVectors_IMPL(OBJGPU *pGpu, struct OBJINTRABLE *pIntrable, NvU32 maxIntrs, NvU32 *pIntrs, NvU32 *pMcEngineIdxs, NvU32 *pCount); - -static inline NV_STATUS intrableGetKernelIntrVectors_DISPATCH(OBJGPU *pGpu, struct OBJINTRABLE *pIntrable, NvU32 maxIntrs, NvU32 *pIntrs, NvU32 *pMcEngineIdxs, NvU32 *pCount) { - return pIntrable->__intrableGetKernelIntrVectors__(pGpu, pIntrable, maxIntrs, pIntrs, pMcEngineIdxs, pCount); -} - -NV_STATUS intrableSetNotificationIntrVector_IMPL(OBJGPU *pGpu, struct OBJINTRABLE *pIntrable, NvU32 intrVector); - -static inline NV_STATUS intrableSetNotificationIntrVector_DISPATCH(OBJGPU *pGpu, struct OBJINTRABLE *pIntrable, NvU32 intrVector) { - return pIntrable->__intrableSetNotificationIntrVector__(pGpu, pIntrable, intrVector); -} - -NV_STATUS intrableConstruct_IMPL(struct OBJINTRABLE *arg_pIntrable); -#define __nvoc_intrableConstruct(arg_pIntrable) intrableConstruct_IMPL(arg_pIntrable) -NV_STATUS intrableCacheAndSetPartitionNotificationIntrVector_IMPL(OBJGPU *pGpu, struct OBJINTRABLE *pIntrable, NvU32 intrVector); -#ifdef __nvoc_intrable_h_disabled -static inline NV_STATUS intrableCacheAndSetPartitionNotificationIntrVector(OBJGPU *pGpu, struct OBJINTRABLE *pIntrable, NvU32 intrVector) { - NV_ASSERT_FAILED_PRECOMP("OBJINTRABLE was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_intrable_h_disabled -#define intrableCacheAndSetPartitionNotificationIntrVector(pGpu, pIntrable, intrVector) intrableCacheAndSetPartitionNotificationIntrVector_IMPL(pGpu, pIntrable, intrVector) -#endif //__nvoc_intrable_h_disabled - -NV_STATUS intrableSetPartitionNotificationIntrVector_IMPL(OBJGPU *pGpu, struct OBJINTRABLE *pIntrable); -#ifdef __nvoc_intrable_h_disabled -static inline NV_STATUS intrableSetPartitionNotificationIntrVector(OBJGPU *pGpu, struct OBJINTRABLE *pIntrable) { - NV_ASSERT_FAILED_PRECOMP("OBJINTRABLE was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_intrable_h_disabled -#define intrableSetPartitionNotificationIntrVector(pGpu, pIntrable) intrableSetPartitionNotificationIntrVector_IMPL(pGpu, pIntrable) -#endif //__nvoc_intrable_h_disabled - -NV_STATUS intrableGetPartitionNotificationIntrVector_IMPL(OBJGPU *pGpu, struct OBJINTRABLE *pIntrable); -#ifdef __nvoc_intrable_h_disabled -static inline NV_STATUS intrableGetPartitionNotificationIntrVector(OBJGPU *pGpu, struct OBJINTRABLE *pIntrable) { - NV_ASSERT_FAILED_PRECOMP("OBJINTRABLE was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_intrable_h_disabled -#define intrableGetPartitionNotificationIntrVector(pGpu, pIntrable) intrableGetPartitionNotificationIntrVector_IMPL(pGpu, pIntrable) -#endif //__nvoc_intrable_h_disabled - -NV_STATUS intrableRevertNotificationIntrVector_IMPL(OBJGPU *pGpu, struct OBJINTRABLE *pIntrable); -#ifdef __nvoc_intrable_h_disabled -static inline NV_STATUS intrableRevertNotificationIntrVector(OBJGPU *pGpu, struct OBJINTRABLE *pIntrable) { - NV_ASSERT_FAILED_PRECOMP("OBJINTRABLE was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_intrable_h_disabled -#define intrableRevertNotificationIntrVector(pGpu, pIntrable) intrableRevertNotificationIntrVector_IMPL(pGpu, pIntrable) -#endif //__nvoc_intrable_h_disabled - -#undef PRIVATE_FIELD - - -#define INTRABLE_MAX_INTR_PER_ENGINE (1) -#define INTRABLE_MAX_INTR_PER_HOST_ENGINE (1) - -#define INTR_ROUTE_DISABLE 0 -#define INTR_ROUTE_PHYSICAL 1 -#define INTR_ROUTE_KERNEL 2 - -#endif // INTRABLE_H - -#ifdef __cplusplus -} // extern "C" -#endif -#endif // _G_INTRABLE_NVOC_H_ diff --git a/src/nvidia/generated/g_io_vaspace_nvoc.c b/src/nvidia/generated/g_io_vaspace_nvoc.c index eff89cc51..7c66710ee 100644 --- a/src/nvidia/generated/g_io_vaspace_nvoc.c +++ b/src/nvidia/generated/g_io_vaspace_nvoc.c @@ -166,6 +166,10 @@ static NV_STATUS __nvoc_thunk_OBJVASPACE_iovaspaceSetPteInfo(struct OBJIOVASPACE return vaspaceSetPteInfo((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_OBJIOVASPACE_OBJVASPACE.offset), pGpu, pParams); } +static NV_STATUS __nvoc_thunk_OBJVASPACE_iovaspaceFreeV2(struct OBJIOVASPACE *pVAS, NvU64 vAddr, NvU64 *pSize) { + return vaspaceFreeV2((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_OBJIOVASPACE_OBJVASPACE.offset), vAddr, pSize); +} + static NV_STATUS __nvoc_thunk_OBJVASPACE_iovaspaceGetPasid(struct OBJIOVASPACE *pVAS, NvU32 *pPasid) { return vaspaceGetPasid((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_OBJIOVASPACE_OBJVASPACE.offset), pPasid); } @@ -282,6 +286,8 @@ static void __nvoc_init_funcTable_OBJIOVASPACE_1(OBJIOVASPACE *pThis) { pThis->__iovaspaceSetPteInfo__ = &__nvoc_thunk_OBJVASPACE_iovaspaceSetPteInfo; + pThis->__iovaspaceFreeV2__ = &__nvoc_thunk_OBJVASPACE_iovaspaceFreeV2; + pThis->__iovaspaceGetPasid__ = &__nvoc_thunk_OBJVASPACE_iovaspaceGetPasid; pThis->__iovaspaceGetPageTableInfo__ = &__nvoc_thunk_OBJVASPACE_iovaspaceGetPageTableInfo; diff --git a/src/nvidia/generated/g_io_vaspace_nvoc.h b/src/nvidia/generated/g_io_vaspace_nvoc.h index a63b3a9c3..dd578a3a3 100644 --- a/src/nvidia/generated/g_io_vaspace_nvoc.h +++ b/src/nvidia/generated/g_io_vaspace_nvoc.h @@ -171,6 +171,7 @@ struct OBJIOVASPACE { NV_STATUS (*__iovaspacePinRootPageDir__)(struct OBJIOVASPACE *, struct OBJGPU *); void (*__iovaspaceUnpinRootPageDir__)(struct OBJIOVASPACE *, struct OBJGPU *); NV_STATUS (*__iovaspaceSetPteInfo__)(struct OBJIOVASPACE *, struct OBJGPU *, NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS *); + NV_STATUS (*__iovaspaceFreeV2__)(struct OBJIOVASPACE *, NvU64, NvU64 *); NV_STATUS (*__iovaspaceGetPasid__)(struct OBJIOVASPACE *, NvU32 *); NV_STATUS (*__iovaspaceGetPageTableInfo__)(struct OBJIOVASPACE *, NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS *); NV_STATUS (*__iovaspaceReserveMempool__)(struct OBJIOVASPACE *, struct OBJGPU *, NvHandle, NvU64, NvU64, NvU32); @@ -231,6 +232,7 @@ NV_STATUS __nvoc_objCreate_OBJIOVASPACE(OBJIOVASPACE**, Dynamic*, NvU32); #define iovaspacePinRootPageDir(pVAS, pGpu) iovaspacePinRootPageDir_DISPATCH(pVAS, pGpu) #define iovaspaceUnpinRootPageDir(pVAS, pGpu) iovaspaceUnpinRootPageDir_DISPATCH(pVAS, pGpu) #define iovaspaceSetPteInfo(pVAS, pGpu, pParams) iovaspaceSetPteInfo_DISPATCH(pVAS, pGpu, pParams) +#define iovaspaceFreeV2(pVAS, vAddr, pSize) iovaspaceFreeV2_DISPATCH(pVAS, vAddr, pSize) #define iovaspaceGetPasid(pVAS, pPasid) iovaspaceGetPasid_DISPATCH(pVAS, pPasid) #define iovaspaceGetPageTableInfo(pVAS, pParams) iovaspaceGetPageTableInfo_DISPATCH(pVAS, pParams) #define iovaspaceReserveMempool(pVAS, pGpu, hClient, size, pageSizeLockMask, flags) iovaspaceReserveMempool_DISPATCH(pVAS, pGpu, hClient, size, pageSizeLockMask, flags) @@ -351,6 +353,10 @@ static inline NV_STATUS iovaspaceSetPteInfo_DISPATCH(struct OBJIOVASPACE *pVAS, return pVAS->__iovaspaceSetPteInfo__(pVAS, pGpu, pParams); } +static inline NV_STATUS iovaspaceFreeV2_DISPATCH(struct OBJIOVASPACE *pVAS, NvU64 vAddr, NvU64 *pSize) { + return pVAS->__iovaspaceFreeV2__(pVAS, vAddr, pSize); +} + static inline NV_STATUS iovaspaceGetPasid_DISPATCH(struct OBJIOVASPACE *pVAS, NvU32 *pPasid) { return pVAS->__iovaspaceGetPasid__(pVAS, pPasid); } @@ -368,8 +374,10 @@ static inline NV_STATUS iovaspaceMap_DISPATCH(struct OBJIOVASPACE *pVAS, struct } void iovaspaceDestruct_IMPL(struct OBJIOVASPACE *pIOVAS); + #define __nvoc_iovaspaceDestruct(pIOVAS) iovaspaceDestruct_IMPL(pIOVAS) NV_STATUS iovaspaceAcquireMapping_IMPL(struct OBJIOVASPACE *pIOVAS, PMEMORY_DESCRIPTOR pIovaMapping); + #ifdef __nvoc_io_vaspace_h_disabled static inline NV_STATUS iovaspaceAcquireMapping(struct OBJIOVASPACE *pIOVAS, PMEMORY_DESCRIPTOR pIovaMapping) { NV_ASSERT_FAILED_PRECOMP("OBJIOVASPACE was disabled!"); @@ -380,6 +388,7 @@ static inline NV_STATUS iovaspaceAcquireMapping(struct OBJIOVASPACE *pIOVAS, PME #endif //__nvoc_io_vaspace_h_disabled void iovaspaceReleaseMapping_IMPL(struct OBJIOVASPACE *pIOVAS, PIOVAMAPPING pIovaMapping); + #ifdef __nvoc_io_vaspace_h_disabled static inline void iovaspaceReleaseMapping(struct OBJIOVASPACE *pIOVAS, PIOVAMAPPING pIovaMapping) { NV_ASSERT_FAILED_PRECOMP("OBJIOVASPACE was disabled!"); @@ -389,6 +398,7 @@ static inline void iovaspaceReleaseMapping(struct OBJIOVASPACE *pIOVAS, PIOVAMAP #endif //__nvoc_io_vaspace_h_disabled void iovaspaceDestroyMapping_IMPL(struct OBJIOVASPACE *pIOVAS, PIOVAMAPPING pIovaMapping); + #ifdef __nvoc_io_vaspace_h_disabled static inline void iovaspaceDestroyMapping(struct OBJIOVASPACE *pIOVAS, PIOVAMAPPING pIovaMapping) { NV_ASSERT_FAILED_PRECOMP("OBJIOVASPACE was disabled!"); diff --git a/src/nvidia/generated/g_journal_nvoc.h b/src/nvidia/generated/g_journal_nvoc.h index 46edce4e6..4968511d5 100644 --- a/src/nvidia/generated/g_journal_nvoc.h +++ b/src/nvidia/generated/g_journal_nvoc.h @@ -89,6 +89,12 @@ typedef struct _def_sys_error_info void * pNextError; // Used to walk error list } SYS_ERROR_INFO; +// Max errors that should be logged into a SYS_ERROR_INFO. +#define MAX_ERROR_LOG_COUNT (0x10) + +// Max error that should be added to SYS_ERROR_INFO.pErrorList +#define MAX_ERROR_LIST_COUNT (0x10) + typedef struct RING_BUFFER_LOG RING_BUFFER_LOG, *PRING_BUFFER_LOG; // A node in the linked list of ring buffers @@ -156,6 +162,7 @@ typedef struct _nocatQueueDescriptor NvU8 tag[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; NvU64 cacheFreshnessPeriodticks; NV2080_NOCAT_JOURNAL_GPU_STATE nocatGpuState; // cache contains the state of the + // associated GPU if there is one. NvU32 nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COUNTER_COUNT]; } nocatQueueDescriptor; @@ -189,6 +196,8 @@ struct OBJRCDB { NvBool RcErrRptRecordsDropped; struct Falcon *pCrashedFlcn; nocatQueueDescriptor nocatJournalDescriptor; + NvU64 systemTimeReference; + NvU64 timeStampFreq; }; #ifndef __NVOC_CLASS_OBJRCDB_TYPEDEF__ @@ -224,10 +233,13 @@ NV_STATUS __nvoc_objCreate_OBJRCDB(OBJRCDB**, Dynamic*, NvU32); __nvoc_objCreate_OBJRCDB((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) NV_STATUS rcdbConstruct_IMPL(struct OBJRCDB *arg_pRcdb); + #define __nvoc_rcdbConstruct(arg_pRcdb) rcdbConstruct_IMPL(arg_pRcdb) void rcdbDestruct_IMPL(struct OBJRCDB *pRcdb); + #define __nvoc_rcdbDestruct(pRcdb) rcdbDestruct_IMPL(pRcdb) NV_STATUS rcdbSavePreviousDriverVersion_IMPL(struct OBJGPU *pGpu, struct OBJRCDB *pRcdb); + #ifdef __nvoc_journal_h_disabled static inline NV_STATUS rcdbSavePreviousDriverVersion(struct OBJGPU *pGpu, struct OBJRCDB *pRcdb) { NV_ASSERT_FAILED_PRECOMP("OBJRCDB was disabled!"); @@ -238,6 +250,7 @@ static inline NV_STATUS rcdbSavePreviousDriverVersion(struct OBJGPU *pGpu, struc #endif //__nvoc_journal_h_disabled NV_STATUS rcdbClearErrorHistory_IMPL(struct OBJRCDB *pRcdb); + #ifdef __nvoc_journal_h_disabled static inline NV_STATUS rcdbClearErrorHistory(struct OBJRCDB *pRcdb) { NV_ASSERT_FAILED_PRECOMP("OBJRCDB was disabled!"); @@ -248,6 +261,7 @@ static inline NV_STATUS rcdbClearErrorHistory(struct OBJRCDB *pRcdb) { #endif //__nvoc_journal_h_disabled NV_STATUS rcdbDeleteErrorElement_IMPL(struct OBJRCDB *pRcdb, void *arg0); + #ifdef __nvoc_journal_h_disabled static inline NV_STATUS rcdbDeleteErrorElement(struct OBJRCDB *pRcdb, void *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJRCDB was disabled!"); @@ -258,6 +272,7 @@ static inline NV_STATUS rcdbDeleteErrorElement(struct OBJRCDB *pRcdb, void *arg0 #endif //__nvoc_journal_h_disabled void rcdbDestroyRingBufferCollection_IMPL(struct OBJRCDB *pRcdb); + #ifdef __nvoc_journal_h_disabled static inline void rcdbDestroyRingBufferCollection(struct OBJRCDB *pRcdb) { NV_ASSERT_FAILED_PRECOMP("OBJRCDB was disabled!"); @@ -267,6 +282,7 @@ static inline void rcdbDestroyRingBufferCollection(struct OBJRCDB *pRcdb) { #endif //__nvoc_journal_h_disabled NV_STATUS rcdbAllocNextJournalRec_IMPL(struct OBJRCDB *pRcdb, NVCD_RECORD **arg0, NvU8 arg1, NvU8 arg2, NvU16 arg3); + #ifdef __nvoc_journal_h_disabled static inline NV_STATUS rcdbAllocNextJournalRec(struct OBJRCDB *pRcdb, NVCD_RECORD **arg0, NvU8 arg1, NvU8 arg2, NvU16 arg3) { NV_ASSERT_FAILED_PRECOMP("OBJRCDB was disabled!"); @@ -277,6 +293,7 @@ static inline NV_STATUS rcdbAllocNextJournalRec(struct OBJRCDB *pRcdb, NVCD_RECO #endif //__nvoc_journal_h_disabled NV_STATUS rcdbAddBugCheckRec_IMPL(struct OBJGPU *pGpu, struct OBJRCDB *pRcdb, NvU32 bugCheckCode); + #ifdef __nvoc_journal_h_disabled static inline NV_STATUS rcdbAddBugCheckRec(struct OBJGPU *pGpu, struct OBJRCDB *pRcdb, NvU32 bugCheckCode) { NV_ASSERT_FAILED_PRECOMP("OBJRCDB was disabled!"); @@ -287,6 +304,7 @@ static inline NV_STATUS rcdbAddBugCheckRec(struct OBJGPU *pGpu, struct OBJRCDB * #endif //__nvoc_journal_h_disabled NV_STATUS rcdbAddPowerStateRec_IMPL(struct OBJGPU *pGpu, struct OBJRCDB *pRcdb, NvU32 powerEvent, NvU32 state, NvU32 fastBootPowerState); + #ifdef __nvoc_journal_h_disabled static inline NV_STATUS rcdbAddPowerStateRec(struct OBJGPU *pGpu, struct OBJRCDB *pRcdb, NvU32 powerEvent, NvU32 state, NvU32 fastBootPowerState) { NV_ASSERT_FAILED_PRECOMP("OBJRCDB was disabled!"); @@ -297,6 +315,7 @@ static inline NV_STATUS rcdbAddPowerStateRec(struct OBJGPU *pGpu, struct OBJRCDB #endif //__nvoc_journal_h_disabled NV_STATUS rcdbDumpInitGpuAccessibleFlag_IMPL(struct OBJGPU *pGpu, struct OBJRCDB *pRcdb); + #ifdef __nvoc_journal_h_disabled static inline NV_STATUS rcdbDumpInitGpuAccessibleFlag(struct OBJGPU *pGpu, struct OBJRCDB *pRcdb) { NV_ASSERT_FAILED_PRECOMP("OBJRCDB was disabled!"); @@ -307,6 +326,7 @@ static inline NV_STATUS rcdbDumpInitGpuAccessibleFlag(struct OBJGPU *pGpu, struc #endif //__nvoc_journal_h_disabled NvU8 *rcdbCreateRingBuffer_IMPL(struct OBJRCDB *pRcdb, RMCD_RECORD_TYPE type, NvU32 maxEntries); + #ifdef __nvoc_journal_h_disabled static inline NvU8 *rcdbCreateRingBuffer(struct OBJRCDB *pRcdb, RMCD_RECORD_TYPE type, NvU32 maxEntries) { NV_ASSERT_FAILED_PRECOMP("OBJRCDB was disabled!"); @@ -317,6 +337,7 @@ static inline NvU8 *rcdbCreateRingBuffer(struct OBJRCDB *pRcdb, RMCD_RECORD_TYPE #endif //__nvoc_journal_h_disabled void rcdbDestroyRingBuffer_IMPL(struct OBJRCDB *pRcdb, RMCD_RECORD_TYPE type); + #ifdef __nvoc_journal_h_disabled static inline void rcdbDestroyRingBuffer(struct OBJRCDB *pRcdb, RMCD_RECORD_TYPE type) { NV_ASSERT_FAILED_PRECOMP("OBJRCDB was disabled!"); @@ -326,6 +347,7 @@ static inline void rcdbDestroyRingBuffer(struct OBJRCDB *pRcdb, RMCD_RECORD_TYPE #endif //__nvoc_journal_h_disabled void rcdbAddRecToRingBuffer_IMPL(struct OBJGPU *pGpu, struct OBJRCDB *pRcdb, RMCD_RECORD_TYPE type, NvU32 recordSize, NvU8 *pRecord); + #ifdef __nvoc_journal_h_disabled static inline void rcdbAddRecToRingBuffer(struct OBJGPU *pGpu, struct OBJRCDB *pRcdb, RMCD_RECORD_TYPE type, NvU32 recordSize, NvU8 *pRecord) { NV_ASSERT_FAILED_PRECOMP("OBJRCDB was disabled!"); @@ -335,6 +357,7 @@ static inline void rcdbAddRecToRingBuffer(struct OBJGPU *pGpu, struct OBJRCDB *p #endif //__nvoc_journal_h_disabled NvU32 rcdbGetOcaRecordSize_IMPL(struct OBJRCDB *pRcdb, RMCD_RECORD_TYPE type); + #ifdef __nvoc_journal_h_disabled static inline NvU32 rcdbGetOcaRecordSize(struct OBJRCDB *pRcdb, RMCD_RECORD_TYPE type) { NV_ASSERT_FAILED_PRECOMP("OBJRCDB was disabled!"); @@ -345,6 +368,7 @@ static inline NvU32 rcdbGetOcaRecordSize(struct OBJRCDB *pRcdb, RMCD_RECORD_TYPE #endif //__nvoc_journal_h_disabled NvU32 rcdbDumpJournal_IMPL(struct OBJRCDB *pRcdb, struct OBJGPU *pGpu, PRB_ENCODER *pPrbEnc, NVD_STATE *pNvDumpState, const PRB_FIELD_DESC *pFieldDesc); + #ifdef __nvoc_journal_h_disabled static inline NvU32 rcdbDumpJournal(struct OBJRCDB *pRcdb, struct OBJGPU *pGpu, PRB_ENCODER *pPrbEnc, NVD_STATE *pNvDumpState, const PRB_FIELD_DESC *pFieldDesc) { NV_ASSERT_FAILED_PRECOMP("OBJRCDB was disabled!"); @@ -355,6 +379,7 @@ static inline NvU32 rcdbDumpJournal(struct OBJRCDB *pRcdb, struct OBJGPU *pGpu, #endif //__nvoc_journal_h_disabled NV_STATUS rcdbDumpComponent_IMPL(struct OBJRCDB *pRcdb, NvU32 component, NVDUMP_BUFFER *pBuffer, NVDUMP_BUFFER_POLICY policy, PrbBufferCallback *pBufferCallback); + #ifdef __nvoc_journal_h_disabled static inline NV_STATUS rcdbDumpComponent(struct OBJRCDB *pRcdb, NvU32 component, NVDUMP_BUFFER *pBuffer, NVDUMP_BUFFER_POLICY policy, PrbBufferCallback *pBufferCallback) { NV_ASSERT_FAILED_PRECOMP("OBJRCDB was disabled!"); @@ -365,6 +390,7 @@ static inline NV_STATUS rcdbDumpComponent(struct OBJRCDB *pRcdb, NvU32 component #endif //__nvoc_journal_h_disabled NV_STATUS rcdbDumpSystemInfo_IMPL(struct OBJRCDB *pRcdb, PRB_ENCODER *pPrbEnc, NVD_STATE *pNvDumpState); + #ifdef __nvoc_journal_h_disabled static inline NV_STATUS rcdbDumpSystemInfo(struct OBJRCDB *pRcdb, PRB_ENCODER *pPrbEnc, NVD_STATE *pNvDumpState) { NV_ASSERT_FAILED_PRECOMP("OBJRCDB was disabled!"); @@ -375,6 +401,7 @@ static inline NV_STATUS rcdbDumpSystemInfo(struct OBJRCDB *pRcdb, PRB_ENCODER *p #endif //__nvoc_journal_h_disabled NV_STATUS rcdbDumpSystemFunc_IMPL(struct OBJRCDB *pRcdb, PRB_ENCODER *pPrbEnc, NVD_STATE *pNvDumpState); + #ifdef __nvoc_journal_h_disabled static inline NV_STATUS rcdbDumpSystemFunc(struct OBJRCDB *pRcdb, PRB_ENCODER *pPrbEnc, NVD_STATE *pNvDumpState) { NV_ASSERT_FAILED_PRECOMP("OBJRCDB was disabled!"); @@ -385,6 +412,7 @@ static inline NV_STATUS rcdbDumpSystemFunc(struct OBJRCDB *pRcdb, PRB_ENCODER *p #endif //__nvoc_journal_h_disabled NvU32 rcdbDumpErrorCounters_IMPL(struct OBJRCDB *pRcDB, struct OBJGPU *pGpu, PRB_ENCODER *pPrbEnc); + #ifdef __nvoc_journal_h_disabled static inline NvU32 rcdbDumpErrorCounters(struct OBJRCDB *pRcDB, struct OBJGPU *pGpu, PRB_ENCODER *pPrbEnc) { NV_ASSERT_FAILED_PRECOMP("OBJRCDB was disabled!"); @@ -395,6 +423,7 @@ static inline NvU32 rcdbDumpErrorCounters(struct OBJRCDB *pRcDB, struct OBJGPU * #endif //__nvoc_journal_h_disabled NV_STATUS rcdbGetRcDiagRecBoundaries_IMPL(struct OBJRCDB *pRcdb, NvU16 *arg0, NvU16 *arg1, NvU32 arg2, NvU32 arg3); + #ifdef __nvoc_journal_h_disabled static inline NV_STATUS rcdbGetRcDiagRecBoundaries(struct OBJRCDB *pRcdb, NvU16 *arg0, NvU16 *arg1, NvU32 arg2, NvU32 arg3) { NV_ASSERT_FAILED_PRECOMP("OBJRCDB was disabled!"); @@ -405,6 +434,7 @@ static inline NV_STATUS rcdbGetRcDiagRecBoundaries(struct OBJRCDB *pRcdb, NvU16 #endif //__nvoc_journal_h_disabled NV_STATUS rcdbAddRcDiagRec_IMPL(struct OBJGPU *pGpu, struct OBJRCDB *pRcdb, RmRcDiag_RECORD *arg0); + #ifdef __nvoc_journal_h_disabled static inline NV_STATUS rcdbAddRcDiagRec(struct OBJGPU *pGpu, struct OBJRCDB *pRcdb, RmRcDiag_RECORD *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJRCDB was disabled!"); @@ -415,6 +445,7 @@ static inline NV_STATUS rcdbAddRcDiagRec(struct OBJGPU *pGpu, struct OBJRCDB *pR #endif //__nvoc_journal_h_disabled NV_STATUS rcdbGetRcDiagRec_IMPL(struct OBJRCDB *pRcdb, NvU16 arg0, RmRCCommonJournal_RECORD **arg1, NvU32 arg2, NvU32 arg3); + #ifdef __nvoc_journal_h_disabled static inline NV_STATUS rcdbGetRcDiagRec(struct OBJRCDB *pRcdb, NvU16 arg0, RmRCCommonJournal_RECORD **arg1, NvU32 arg2, NvU32 arg3) { NV_ASSERT_FAILED_PRECOMP("OBJRCDB was disabled!"); @@ -425,6 +456,7 @@ static inline NV_STATUS rcdbGetRcDiagRec(struct OBJRCDB *pRcdb, NvU16 arg0, RmRC #endif //__nvoc_journal_h_disabled NV_STATUS rcdbUpdateRcDiagRecContext_IMPL(struct OBJRCDB *pRcdb, NvU16 arg0, NvU16 arg1, NvU32 arg2, NvU32 arg3); + #ifdef __nvoc_journal_h_disabled static inline NV_STATUS rcdbUpdateRcDiagRecContext(struct OBJRCDB *pRcdb, NvU16 arg0, NvU16 arg1, NvU32 arg2, NvU32 arg3) { NV_ASSERT_FAILED_PRECOMP("OBJRCDB was disabled!"); @@ -435,8 +467,10 @@ static inline NV_STATUS rcdbUpdateRcDiagRecContext(struct OBJRCDB *pRcdb, NvU16 #endif //__nvoc_journal_h_disabled void rcdbInitNocatGpuCache_IMPL(struct OBJGPU *pGpu); + #define rcdbInitNocatGpuCache(pGpu) rcdbInitNocatGpuCache_IMPL(pGpu) void rcdbCleanupNocatGpuCache_IMPL(struct OBJGPU *pGpu); + #define rcdbCleanupNocatGpuCache(pGpu) rcdbCleanupNocatGpuCache_IMPL(pGpu) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_kern_bus_nvoc.c b/src/nvidia/generated/g_kern_bus_nvoc.c index aa5d41b3f..23c85c236 100644 --- a/src/nvidia/generated/g_kern_bus_nvoc.c +++ b/src/nvidia/generated/g_kern_bus_nvoc.c @@ -78,6 +78,10 @@ static NV_STATUS __nvoc_thunk_KernelBus_engstateStateInitLocked(OBJGPU *pGpu, st return kbusStateInitLocked(pGpu, (struct KernelBus *)(((unsigned char *)pKernelBus) - __nvoc_rtti_KernelBus_OBJENGSTATE.offset)); } +static NV_STATUS __nvoc_thunk_KernelBus_engstateStateLoad(OBJGPU *pGpu, struct OBJENGSTATE *pKernelBus, NvU32 arg0) { + return kbusStateLoad(pGpu, (struct KernelBus *)(((unsigned char *)pKernelBus) - __nvoc_rtti_KernelBus_OBJENGSTATE.offset), arg0); +} + static NV_STATUS __nvoc_thunk_KernelBus_engstateStatePostLoad(OBJGPU *pGpu, struct OBJENGSTATE *pKernelBus, NvU32 arg0) { return kbusStatePostLoad(pGpu, (struct KernelBus *)(((unsigned char *)pKernelBus) - __nvoc_rtti_KernelBus_OBJENGSTATE.offset), arg0); } @@ -98,10 +102,6 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbusReconcileTunableState(POBJGPU pGpu return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBus_OBJENGSTATE.offset), pTunableState); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbusStateLoad(POBJGPU pGpu, struct KernelBus *pEngstate, NvU32 arg0) { - return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBus_OBJENGSTATE.offset), arg0); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbusStatePreLoad(POBJGPU pGpu, struct KernelBus *pEngstate, NvU32 arg0) { return engstateStatePreLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBus_OBJENGSTATE.offset), arg0); } @@ -172,7 +172,7 @@ void __nvoc_init_dataField_KernelBus(KernelBus *pThis, RmHalspecOwner *pRmhalspe PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // Hal field -- bFlaDummyPageEnabled - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->bFlaDummyPageEnabled = ((NvBool)(0 == 0)); } @@ -183,76 +183,60 @@ void __nvoc_init_dataField_KernelBus(KernelBus *pThis, RmHalspecOwner *pRmhalspe } // Hal field -- bP2pMailboxClientAllocatedBug3466714VoltaAndUp - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->bP2pMailboxClientAllocatedBug3466714VoltaAndUp = ((NvBool)(0 == 0)); } - // default - else - { - pThis->bP2pMailboxClientAllocatedBug3466714VoltaAndUp = ((NvBool)(0 != 0)); - } // Hal field -- bBug2751296LimitBar2PtSize - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->bBug2751296LimitBar2PtSize = ((NvBool)(0 == 0)); } - // default - else - { - pThis->bBug2751296LimitBar2PtSize = ((NvBool)(0 != 0)); - } // Hal field -- bAllowReflectedMappingAccess - if (0) - { - } // default - else { pThis->bAllowReflectedMappingAccess = ((NvBool)(0 != 0)); } // Hal field -- bBar2Tunnelled - if (0) - { - } // default - else { pThis->bBar2Tunnelled = ((NvBool)(0 != 0)); } // Hal field -- bBar2InternalOnly - if (0) - { - } - else if (0) - { - } // default - else { pThis->bBar2InternalOnly = ((NvBool)(0 != 0)); } + // Hal field -- bSkipBar2TestOnGc6Exit + // default + { + pThis->bSkipBar2TestOnGc6Exit = ((NvBool)(0 != 0)); + } + // Hal field -- bReadCpuPointerToFlush - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->bReadCpuPointerToFlush = ((NvBool)(0 == 0)); } + + // NVOC Property Hal field -- PDB_PROP_KBUS_NVLINK_DECONFIG_HSHUB_ON_NO_MAPPING + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->setProperty(pThis, PDB_PROP_KBUS_NVLINK_DECONFIG_HSHUB_ON_NO_MAPPING, ((NvBool)(0 == 0))); + } // default else { - pThis->bReadCpuPointerToFlush = ((NvBool)(0 != 0)); + pThis->setProperty(pThis, PDB_PROP_KBUS_NVLINK_DECONFIG_HSHUB_ON_NO_MAPPING, ((NvBool)(0 != 0))); } // NVOC Property Hal field -- PDB_PROP_KBUS_IS_MISSING - if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_KBUS_IS_MISSING, ((NvBool)(0 != 0))); } @@ -287,143 +271,115 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * pThis->__kbusConstructEngine__ = &kbusConstructEngine_IMPL; // Hal function -- kbusStatePreInitLocked - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kbusStatePreInitLocked__ = &kbusStatePreInitLocked_GM107; } - else if (0) - { - } - else if (0) - { - } pThis->__kbusStateInitLocked__ = &kbusStateInitLocked_IMPL; + // Hal function -- kbusStateLoad + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->__kbusStateLoad__ = &kbusStateLoad_GM107; + } + } + // Hal function -- kbusStatePostLoad - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kbusStatePostLoad__ = &kbusStatePostLoad_GM107; } - else if (0) - { - } // Hal function -- kbusStatePreUnload - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kbusStatePreUnload__ = &kbusStatePreUnload_GM107; } - else if (0) - { - } // Hal function -- kbusStateUnload - if (0) + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kbusStateUnload__ = &kbusStateUnload_GM107; } - else if (0) - { - } } // Hal function -- kbusStateDestroy - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kbusStateDestroy__ = &kbusStateDestroy_GM107; } - else if (0) - { - } // Hal function -- kbusTeardownBar2CpuAperture - if (0) + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbusTeardownBar2CpuAperture__ = &kbusTeardownBar2CpuAperture_GM107; } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbusTeardownBar2CpuAperture__ = &kbusTeardownBar2CpuAperture_GH100; } - else if (0) - { - } } // Hal function -- kbusGetP2PMailboxAttributes - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbusGetP2PMailboxAttributes__ = &kbusGetP2PMailboxAttributes_GM200; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbusGetP2PMailboxAttributes__ = &kbusGetP2PMailboxAttributes_GH100; } - else if (0) - { - } // Hal function -- kbusCreateP2PMapping - if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbusCreateP2PMapping__ = &kbusCreateP2PMapping_GP100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbusCreateP2PMapping__ = &kbusCreateP2PMapping_GH100; } - else if (0) - { - } // Hal function -- kbusRemoveP2PMapping - if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbusRemoveP2PMapping__ = &kbusRemoveP2PMapping_GP100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbusRemoveP2PMapping__ = &kbusRemoveP2PMapping_GH100; } - else if (0) - { - } // Hal function -- kbusGetPeerId - if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbusGetPeerId__ = &kbusGetPeerId_GP100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbusGetPeerId__ = &kbusGetPeerId_GH100; } + // Hal function -- kbusGetNvSwitchPeerId + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->__kbusGetNvSwitchPeerId__ = &kbusGetNvSwitchPeerId_GA100; + } + // default + else + { + pThis->__kbusGetNvSwitchPeerId__ = &kbusGetNvSwitchPeerId_c732fb; + } + // Hal function -- kbusGetUnusedPciePeerId - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kbusGetUnusedPciePeerId__ = &kbusGetUnusedPciePeerId_GM107; } @@ -433,80 +389,64 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * } // Hal function -- kbusIsPeerIdValid - if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbusIsPeerIdValid__ = &kbusIsPeerIdValid_GP100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbusIsPeerIdValid__ = &kbusIsPeerIdValid_GH100; } // Hal function -- kbusGetNvlinkP2PPeerId - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - pThis->__kbusGetNvlinkP2PPeerId__ = &kbusGetNvlinkP2PPeerId_GP100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ - { - pThis->__kbusGetNvlinkP2PPeerId__ = &kbusGetNvlinkP2PPeerId_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ - { - pThis->__kbusGetNvlinkP2PPeerId__ = &kbusGetNvlinkP2PPeerId_56cd7a; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ + { + pThis->__kbusGetNvlinkP2PPeerId__ = &kbusGetNvlinkP2PPeerId_GP100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->__kbusGetNvlinkP2PPeerId__ = &kbusGetNvlinkP2PPeerId_GA100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ + { + pThis->__kbusGetNvlinkP2PPeerId__ = &kbusGetNvlinkP2PPeerId_56cd7a; + } } // Hal function -- kbusWriteP2PWmbTag - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbusWriteP2PWmbTag__ = &kbusWriteP2PWmbTag_GM200; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbusWriteP2PWmbTag__ = &kbusWriteP2PWmbTag_GH100; } - else if (0) - { - } // Hal function -- kbusSetupP2PDomainAccess - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbusSetupP2PDomainAccess__ = &kbusSetupP2PDomainAccess_GM200; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbusSetupP2PDomainAccess__ = &kbusSetupP2PDomainAccess_GH100; } - else if (0) - { - } // Hal function -- kbusNeedWarForBug999673 - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbusNeedWarForBug999673__ = &kbusNeedWarForBug999673_GM200; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbusNeedWarForBug999673__ = &kbusNeedWarForBug999673_491d52; } - // Hal function -- kbusRemoveNvlinkPeerMapping - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ - { - pThis->__kbusRemoveNvlinkPeerMapping__ = &kbusRemoveNvlinkPeerMapping_GP100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ - { - pThis->__kbusRemoveNvlinkPeerMapping__ = &kbusRemoveNvlinkPeerMapping_56cd7a; - } - // Hal function -- kbusCreateP2PMappingForC2C - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbusCreateP2PMappingForC2C__ = &kbusCreateP2PMappingForC2C_GH100; } @@ -517,7 +457,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * } // Hal function -- kbusRemoveP2PMappingForC2C - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbusRemoveP2PMappingForC2C__ = &kbusRemoveP2PMappingForC2C_GH100; } @@ -528,7 +468,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * } // Hal function -- kbusUnreserveP2PPeerIds - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kbusUnreserveP2PPeerIds__ = &kbusUnreserveP2PPeerIds_GP100; } @@ -538,7 +478,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * } // Hal function -- kbusCreateP2PMappingForBar1P2P - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbusCreateP2PMappingForBar1P2P__ = &kbusCreateP2PMappingForBar1P2P_GH100; } @@ -549,7 +489,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * } // Hal function -- kbusRemoveP2PMappingForBar1P2P - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbusRemoveP2PMappingForBar1P2P__ = &kbusRemoveP2PMappingForBar1P2P_GH100; } @@ -560,7 +500,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * } // Hal function -- kbusHasPcieBar1P2PMapping - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbusHasPcieBar1P2PMapping__ = &kbusHasPcieBar1P2PMapping_GH100; } @@ -570,112 +510,183 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * pThis->__kbusHasPcieBar1P2PMapping__ = &kbusHasPcieBar1P2PMapping_491d52; } + // Hal function -- kbusCheckFlaSupportedAndInit + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ + { + pThis->__kbusCheckFlaSupportedAndInit__ = &kbusCheckFlaSupportedAndInit_GA100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__kbusCheckFlaSupportedAndInit__ = &kbusCheckFlaSupportedAndInit_ac1694; + } + + // Hal function -- kbusDetermineFlaRangeAndAllocate + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + { + pThis->__kbusDetermineFlaRangeAndAllocate__ = &kbusDetermineFlaRangeAndAllocate_GA100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusDetermineFlaRangeAndAllocate__ = &kbusDetermineFlaRangeAndAllocate_GH100; + } + // default + else + { + pThis->__kbusDetermineFlaRangeAndAllocate__ = &kbusDetermineFlaRangeAndAllocate_395e98; + } + // Hal function -- kbusAllocateFlaVaspace - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ { pThis->__kbusAllocateFlaVaspace__ = &kbusAllocateFlaVaspace_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusAllocateFlaVaspace__ = &kbusAllocateFlaVaspace_GH100; + } + // default + else { pThis->__kbusAllocateFlaVaspace__ = &kbusAllocateFlaVaspace_395e98; } + // Hal function -- kbusAllocateLegacyFlaVaspace + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ + { + pThis->__kbusAllocateLegacyFlaVaspace__ = &kbusAllocateLegacyFlaVaspace_GA100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__kbusAllocateLegacyFlaVaspace__ = &kbusAllocateLegacyFlaVaspace_395e98; + } + // Hal function -- kbusAllocateHostManagedFlaVaspace - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kbusAllocateHostManagedFlaVaspace__ = &kbusAllocateHostManagedFlaVaspace_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbusAllocateHostManagedFlaVaspace__ = &kbusAllocateHostManagedFlaVaspace_395e98; } - // Hal function -- kbusInitFla - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ - { - pThis->__kbusInitFla__ = &kbusInitFla_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ - { - pThis->__kbusInitFla__ = &kbusInitFla_ac1694; - } - - // Hal function -- kbusGetFlaVaspace - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ - { - pThis->__kbusGetFlaVaspace__ = &kbusGetFlaVaspace_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ - { - pThis->__kbusGetFlaVaspace__ = &kbusGetFlaVaspace_395e98; - } - // Hal function -- kbusDestroyFla - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ { pThis->__kbusDestroyFla__ = &kbusDestroyFla_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusDestroyFla__ = &kbusDestroyFla_GH100; + } + // default + else { pThis->__kbusDestroyFla__ = &kbusDestroyFla_d44104; } + // Hal function -- kbusGetFlaVaspace + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ + { + pThis->__kbusGetFlaVaspace__ = &kbusGetFlaVaspace_GA100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__kbusGetFlaVaspace__ = &kbusGetFlaVaspace_395e98; + } + // Hal function -- kbusDestroyHostManagedFlaVaspace - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kbusDestroyHostManagedFlaVaspace__ = &kbusDestroyHostManagedFlaVaspace_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbusDestroyHostManagedFlaVaspace__ = &kbusDestroyHostManagedFlaVaspace_d44104; } // Hal function -- kbusVerifyFlaRange - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kbusVerifyFlaRange__ = &kbusVerifyFlaRange_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbusVerifyFlaRange__ = &kbusVerifyFlaRange_bf6dfa; } // Hal function -- kbusConstructFlaInstBlk - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kbusConstructFlaInstBlk__ = &kbusConstructFlaInstBlk_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbusConstructFlaInstBlk__ = &kbusConstructFlaInstBlk_395e98; } // Hal function -- kbusDestructFlaInstBlk - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kbusDestructFlaInstBlk__ = &kbusDestructFlaInstBlk_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbusDestructFlaInstBlk__ = &kbusDestructFlaInstBlk_d44104; } // Hal function -- kbusValidateFlaBaseAddress - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kbusValidateFlaBaseAddress__ = &kbusValidateFlaBaseAddress_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbusValidateFlaBaseAddress__ = &kbusValidateFlaBaseAddress_395e98; } + // Hal function -- kbusSetupUnbindFla + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + { + pThis->__kbusSetupUnbindFla__ = &kbusSetupUnbindFla_GA100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusSetupUnbindFla__ = &kbusSetupUnbindFla_GH100; + } + // default + else + { + pThis->__kbusSetupUnbindFla__ = &kbusSetupUnbindFla_46f6a7; + } + } + + // Hal function -- kbusSetupBindFla + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + { + pThis->__kbusSetupBindFla__ = &kbusSetupBindFla_GA100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusSetupBindFla__ = &kbusSetupBindFla_GH100; + } + // default + else + { + pThis->__kbusSetupBindFla__ = &kbusSetupBindFla_46f6a7; + } + } + // Hal function -- kbusIsDirectMappingAllowed if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__kbusIsDirectMappingAllowed__ = &kbusIsDirectMappingAllowed_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kbusIsDirectMappingAllowed__ = &kbusIsDirectMappingAllowed_GA100; } @@ -685,92 +696,89 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * { pThis->__kbusUseDirectSysmemMap__ = &kbusUseDirectSysmemMap_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kbusUseDirectSysmemMap__ = &kbusUseDirectSysmemMap_GA100; } - else if (0) + + // Hal function -- kbusWriteBAR0WindowBase + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { + pThis->__kbusWriteBAR0WindowBase__ = &kbusWriteBAR0WindowBase_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__kbusWriteBAR0WindowBase__ = &kbusWriteBAR0WindowBase_395e98; + } + + // Hal function -- kbusReadBAR0WindowBase + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusReadBAR0WindowBase__ = &kbusReadBAR0WindowBase_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__kbusReadBAR0WindowBase__ = &kbusReadBAR0WindowBase_13cd8d; + } + + // Hal function -- kbusValidateBAR0WindowBase + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusValidateBAR0WindowBase__ = &kbusValidateBAR0WindowBase_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__kbusValidateBAR0WindowBase__ = &kbusValidateBAR0WindowBase_ceaee8; } // Hal function -- kbusSetBAR0WindowVidOffset - if (0) + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbusSetBAR0WindowVidOffset__ = &kbusSetBAR0WindowVidOffset_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbusSetBAR0WindowVidOffset__ = &kbusSetBAR0WindowVidOffset_GH100; } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } } // Hal function -- kbusGetBAR0WindowVidOffset - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbusGetBAR0WindowVidOffset__ = &kbusGetBAR0WindowVidOffset_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbusGetBAR0WindowVidOffset__ = &kbusGetBAR0WindowVidOffset_GH100; } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } // Hal function -- kbusVerifyBar2 - if (0) + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbusVerifyBar2__ = &kbusVerifyBar2_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbusVerifyBar2__ = &kbusVerifyBar2_GH100; } - else if (0) - { - } - else if (0) - { - } } // Hal function -- kbusFlushPcieForBar0Doorbell - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbusFlushPcieForBar0Doorbell__ = &kbusFlushPcieForBar0Doorbell_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbusFlushPcieForBar0Doorbell__ = &kbusFlushPcieForBar0Doorbell_56cd7a; } // Hal function -- kbusMapCoherentCpuMapping - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbusMapCoherentCpuMapping__ = &kbusMapCoherentCpuMapping_GV100; } @@ -781,7 +789,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * } // Hal function -- kbusUnmapCoherentCpuMapping - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbusUnmapCoherentCpuMapping__ = &kbusUnmapCoherentCpuMapping_GV100; } @@ -792,7 +800,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * } // Hal function -- kbusTeardownCoherentCpuMapping - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbusTeardownCoherentCpuMapping__ = &kbusTeardownCoherentCpuMapping_GV100; } @@ -808,6 +816,8 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_thunk_KernelBus_engstateStateInitLocked; + pThis->__nvoc_base_OBJENGSTATE.__engstateStateLoad__ = &__nvoc_thunk_KernelBus_engstateStateLoad; + pThis->__nvoc_base_OBJENGSTATE.__engstateStatePostLoad__ = &__nvoc_thunk_KernelBus_engstateStatePostLoad; pThis->__nvoc_base_OBJENGSTATE.__engstateStatePreUnload__ = &__nvoc_thunk_KernelBus_engstateStatePreUnload; @@ -818,8 +828,6 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * pThis->__kbusReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kbusReconcileTunableState; - pThis->__kbusStateLoad__ = &__nvoc_thunk_OBJENGSTATE_kbusStateLoad; - pThis->__kbusStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_kbusStatePreLoad; pThis->__kbusStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_kbusStatePostUnload; @@ -847,6 +855,24 @@ void __nvoc_init_funcTable_KernelBus(KernelBus *pThis, RmHalspecOwner *pRmhalspe __nvoc_init_funcTable_KernelBus_1(pThis, pRmhalspecowner); } +NvU32 kbusGetP2PWriteMailboxAddressSize_STATIC_DISPATCH(OBJGPU *pGpu) { + ChipHal *chipHal = &staticCast(pGpu, RmHalspecOwner)->chipHal; + const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; + + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + return kbusGetP2PWriteMailboxAddressSize_GH100(pGpu); + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + return kbusGetP2PWriteMailboxAddressSize_474d46(pGpu); + } + + NV_ASSERT_FAILED("No hal impl found for kbusGetP2PWriteMailboxAddressSize"); + + return 0; +} + void __nvoc_init_OBJENGSTATE(OBJENGSTATE*); void __nvoc_init_KernelBus(KernelBus *pThis, RmHalspecOwner *pRmhalspecowner) { pThis->__nvoc_pbase_KernelBus = pThis; diff --git a/src/nvidia/generated/g_kern_bus_nvoc.h b/src/nvidia/generated/g_kern_bus_nvoc.h index bdfb1180a..5f57ead0a 100644 --- a/src/nvidia/generated/g_kern_bus_nvoc.h +++ b/src/nvidia/generated/g_kern_bus_nvoc.h @@ -147,8 +147,7 @@ typedef enum // Inst Block #define GF100_BUS_INSTANCEBLOCK_SIZE 4096 -// @ref busMigrateBarMapping_GV100 to see how FB region is organized -#define COHERENT_CPU_MAPPING_WPR 0x0 +#define COHERENT_CPU_MAPPING_REGION_0 0x0 #define COHERENT_CPU_MAPPING_REGION_1 0x1 #define COHERENT_CPU_MAPPING_REGION_2 0x2 #define COHERENT_CPU_MAPPING_TOTAL_REGIONS 0x3 // Should change it when num of regions changed @@ -252,6 +251,7 @@ struct __nvoc_inner_struc_KernelBus_4__ { NvBool bFlaRangeRegistered; NvU64 base; NvU64 size; + NvBool bToggleBindPoint; }; struct __nvoc_inner_struc_KernelBus_5__ { @@ -297,6 +297,7 @@ struct KernelBus { NV_STATUS (*__kbusConstructEngine__)(OBJGPU *, struct KernelBus *, ENGDESCRIPTOR); NV_STATUS (*__kbusStatePreInitLocked__)(OBJGPU *, struct KernelBus *); NV_STATUS (*__kbusStateInitLocked__)(OBJGPU *, struct KernelBus *); + NV_STATUS (*__kbusStateLoad__)(OBJGPU *, struct KernelBus *, NvU32); NV_STATUS (*__kbusStatePostLoad__)(OBJGPU *, struct KernelBus *, NvU32); NV_STATUS (*__kbusStatePreUnload__)(OBJGPU *, struct KernelBus *, NvU32); NV_STATUS (*__kbusStateUnload__)(OBJGPU *, struct KernelBus *, NvU32); @@ -306,31 +307,38 @@ struct KernelBus { NV_STATUS (*__kbusCreateP2PMapping__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32 *, NvU32 *, NvU32); NV_STATUS (*__kbusRemoveP2PMapping__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32, NvU32, NvU32); NvU32 (*__kbusGetPeerId__)(OBJGPU *, struct KernelBus *, OBJGPU *); + NvU32 (*__kbusGetNvSwitchPeerId__)(OBJGPU *, struct KernelBus *); NvU32 (*__kbusGetUnusedPciePeerId__)(OBJGPU *, struct KernelBus *); NV_STATUS (*__kbusIsPeerIdValid__)(OBJGPU *, struct KernelBus *, NvU32); NV_STATUS (*__kbusGetNvlinkP2PPeerId__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32 *); void (*__kbusWriteP2PWmbTag__)(OBJGPU *, struct KernelBus *, NvU32, NvU64); RmPhysAddr (*__kbusSetupP2PDomainAccess__)(OBJGPU *, struct KernelBus *, OBJGPU *, PMEMORY_DESCRIPTOR *); NvBool (*__kbusNeedWarForBug999673__)(OBJGPU *, struct KernelBus *, OBJGPU *); - NV_STATUS (*__kbusRemoveNvlinkPeerMapping__)(OBJGPU *, struct KernelBus *, OBJGPU *, NvU32, NvU32); NV_STATUS (*__kbusCreateP2PMappingForC2C__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32 *, NvU32 *, NvU32); NV_STATUS (*__kbusRemoveP2PMappingForC2C__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32, NvU32, NvU32); NV_STATUS (*__kbusUnreserveP2PPeerIds__)(OBJGPU *, struct KernelBus *, NvU32); NV_STATUS (*__kbusCreateP2PMappingForBar1P2P__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32); NV_STATUS (*__kbusRemoveP2PMappingForBar1P2P__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32); NvBool (*__kbusHasPcieBar1P2PMapping__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *); + NV_STATUS (*__kbusCheckFlaSupportedAndInit__)(OBJGPU *, struct KernelBus *, NvU64, NvU64); + NV_STATUS (*__kbusDetermineFlaRangeAndAllocate__)(OBJGPU *, struct KernelBus *, NvU64, NvU64); NV_STATUS (*__kbusAllocateFlaVaspace__)(OBJGPU *, struct KernelBus *, NvU64, NvU64); + NV_STATUS (*__kbusAllocateLegacyFlaVaspace__)(OBJGPU *, struct KernelBus *, NvU64, NvU64); NV_STATUS (*__kbusAllocateHostManagedFlaVaspace__)(OBJGPU *, struct KernelBus *, NvHandle, NvHandle, NvHandle, NvHandle, NvU64, NvU64, NvU32); - NV_STATUS (*__kbusInitFla__)(OBJGPU *, struct KernelBus *, NvU64, NvU64); - NV_STATUS (*__kbusGetFlaVaspace__)(OBJGPU *, struct KernelBus *, struct OBJVASPACE **); void (*__kbusDestroyFla__)(OBJGPU *, struct KernelBus *); + NV_STATUS (*__kbusGetFlaVaspace__)(OBJGPU *, struct KernelBus *, struct OBJVASPACE **); void (*__kbusDestroyHostManagedFlaVaspace__)(OBJGPU *, struct KernelBus *, NvU32); NvBool (*__kbusVerifyFlaRange__)(OBJGPU *, struct KernelBus *, NvU64, NvU64); NV_STATUS (*__kbusConstructFlaInstBlk__)(OBJGPU *, struct KernelBus *, NvU32); void (*__kbusDestructFlaInstBlk__)(OBJGPU *, struct KernelBus *); NV_STATUS (*__kbusValidateFlaBaseAddress__)(OBJGPU *, struct KernelBus *, NvU64); + NV_STATUS (*__kbusSetupUnbindFla__)(OBJGPU *, struct KernelBus *); + NV_STATUS (*__kbusSetupBindFla__)(OBJGPU *, struct KernelBus *, NvU32); NV_STATUS (*__kbusIsDirectMappingAllowed__)(OBJGPU *, struct KernelBus *, PMEMORY_DESCRIPTOR, NvU32, NvBool *); NV_STATUS (*__kbusUseDirectSysmemMap__)(OBJGPU *, struct KernelBus *, MEMORY_DESCRIPTOR *, NvBool *); + NV_STATUS (*__kbusWriteBAR0WindowBase__)(OBJGPU *, struct KernelBus *, NvU32); + NvU32 (*__kbusReadBAR0WindowBase__)(OBJGPU *, struct KernelBus *); + NvBool (*__kbusValidateBAR0WindowBase__)(OBJGPU *, struct KernelBus *, NvU32); NV_STATUS (*__kbusSetBAR0WindowVidOffset__)(OBJGPU *, struct KernelBus *, NvU64); NvU64 (*__kbusGetBAR0WindowVidOffset__)(OBJGPU *, struct KernelBus *); NV_STATUS (*__kbusVerifyBar2__)(OBJGPU *, struct KernelBus *, PMEMORY_DESCRIPTOR, NvU8 *, NvU64, NvU64); @@ -339,7 +347,6 @@ struct KernelBus { void (*__kbusUnmapCoherentCpuMapping__)(OBJGPU *, struct KernelBus *, PMEMORY_DESCRIPTOR); void (*__kbusTeardownCoherentCpuMapping__)(OBJGPU *, struct KernelBus *, NvBool); NV_STATUS (*__kbusReconcileTunableState__)(POBJGPU, struct KernelBus *, void *); - NV_STATUS (*__kbusStateLoad__)(POBJGPU, struct KernelBus *, NvU32); NV_STATUS (*__kbusStatePreLoad__)(POBJGPU, struct KernelBus *, NvU32); NV_STATUS (*__kbusStatePostUnload__)(POBJGPU, struct KernelBus *, NvU32); NV_STATUS (*__kbusStateInitUnlocked__)(POBJGPU, struct KernelBus *); @@ -387,16 +394,19 @@ struct KernelBus { NvBool bBar2SysmemAccessEnabled; NvBool bBar2TestSkipped; NvBool bUsePhysicalBar2InitPagetable; + NvBool bIsBar2SetupInPhysicalMode; NvBool bPreserveBar1ConsoleEnabled; NvBool bBar1ConsolePreserved; NvBool bBug2751296LimitBar2PtSize; NvBool bAllowReflectedMappingAccess; NvBool bBar2Tunnelled; NvBool bBar2InternalOnly; + NvBool bSkipBar2TestOnGc6Exit; NvBool bFbFlushDisabled; PMEMORY_DESCRIPTOR pFlushMemDesc; NvU8 *pReadToFlush; NvBool bReadCpuPointerToFlush; + NvBool PDB_PROP_KBUS_NVLINK_DECONFIG_HSHUB_ON_NO_MAPPING; NvU32 PTEBAR2Aperture; NvU32 PTEBAR2Attr; NvU32 PDEBAR2Aperture; @@ -428,6 +438,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelBus; #define PDB_PROP_KBUS_IS_MISSING_BASE_CAST __nvoc_base_OBJENGSTATE. #define PDB_PROP_KBUS_IS_MISSING_BASE_NAME PDB_PROP_ENGSTATE_IS_MISSING +#define PDB_PROP_KBUS_NVLINK_DECONFIG_HSHUB_ON_NO_MAPPING_BASE_CAST +#define PDB_PROP_KBUS_NVLINK_DECONFIG_HSHUB_ON_NO_MAPPING_BASE_NAME PDB_PROP_KBUS_NVLINK_DECONFIG_HSHUB_ON_NO_MAPPING NV_STATUS __nvoc_objCreateDynamic_KernelBus(KernelBus**, Dynamic*, NvU32, va_list); @@ -439,6 +451,8 @@ NV_STATUS __nvoc_objCreate_KernelBus(KernelBus**, Dynamic*, NvU32); #define kbusStatePreInitLocked(pGpu, pKernelBus) kbusStatePreInitLocked_DISPATCH(pGpu, pKernelBus) #define kbusStatePreInitLocked_HAL(pGpu, pKernelBus) kbusStatePreInitLocked_DISPATCH(pGpu, pKernelBus) #define kbusStateInitLocked(pGpu, pKernelBus) kbusStateInitLocked_DISPATCH(pGpu, pKernelBus) +#define kbusStateLoad(pGpu, pKernelBus, arg0) kbusStateLoad_DISPATCH(pGpu, pKernelBus, arg0) +#define kbusStateLoad_HAL(pGpu, pKernelBus, arg0) kbusStateLoad_DISPATCH(pGpu, pKernelBus, arg0) #define kbusStatePostLoad(pGpu, pKernelBus, arg0) kbusStatePostLoad_DISPATCH(pGpu, pKernelBus, arg0) #define kbusStatePostLoad_HAL(pGpu, pKernelBus, arg0) kbusStatePostLoad_DISPATCH(pGpu, pKernelBus, arg0) #define kbusStatePreUnload(pGpu, pKernelBus, arg0) kbusStatePreUnload_DISPATCH(pGpu, pKernelBus, arg0) @@ -449,6 +463,8 @@ NV_STATUS __nvoc_objCreate_KernelBus(KernelBus**, Dynamic*, NvU32); #define kbusStateDestroy_HAL(pGpu, pKernelBus) kbusStateDestroy_DISPATCH(pGpu, pKernelBus) #define kbusTeardownBar2CpuAperture(pGpu, pKernelBus, gfid) kbusTeardownBar2CpuAperture_DISPATCH(pGpu, pKernelBus, gfid) #define kbusTeardownBar2CpuAperture_HAL(pGpu, pKernelBus, gfid) kbusTeardownBar2CpuAperture_DISPATCH(pGpu, pKernelBus, gfid) +#define kbusGetP2PWriteMailboxAddressSize(pGpu) kbusGetP2PWriteMailboxAddressSize_STATIC_DISPATCH(pGpu) +#define kbusGetP2PWriteMailboxAddressSize_HAL(pGpu) kbusGetP2PWriteMailboxAddressSize_STATIC_DISPATCH(pGpu) #define kbusGetP2PMailboxAttributes(pGpu, pKernelBus, pMailboxAreaSize, pMailboxAlignmentSize, pMailboxMaxOffset64KB) kbusGetP2PMailboxAttributes_DISPATCH(pGpu, pKernelBus, pMailboxAreaSize, pMailboxAlignmentSize, pMailboxMaxOffset64KB) #define kbusGetP2PMailboxAttributes_HAL(pGpu, pKernelBus, pMailboxAreaSize, pMailboxAlignmentSize, pMailboxMaxOffset64KB) kbusGetP2PMailboxAttributes_DISPATCH(pGpu, pKernelBus, pMailboxAreaSize, pMailboxAlignmentSize, pMailboxMaxOffset64KB) #define kbusCreateP2PMapping(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusCreateP2PMapping_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) @@ -457,6 +473,8 @@ NV_STATUS __nvoc_objCreate_KernelBus(KernelBus**, Dynamic*, NvU32); #define kbusRemoveP2PMapping_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusRemoveP2PMapping_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) #define kbusGetPeerId(pGpu, pKernelBus, pPeerGpu) kbusGetPeerId_DISPATCH(pGpu, pKernelBus, pPeerGpu) #define kbusGetPeerId_HAL(pGpu, pKernelBus, pPeerGpu) kbusGetPeerId_DISPATCH(pGpu, pKernelBus, pPeerGpu) +#define kbusGetNvSwitchPeerId(pGpu, pKernelBus) kbusGetNvSwitchPeerId_DISPATCH(pGpu, pKernelBus) +#define kbusGetNvSwitchPeerId_HAL(pGpu, pKernelBus) kbusGetNvSwitchPeerId_DISPATCH(pGpu, pKernelBus) #define kbusGetUnusedPciePeerId(pGpu, pKernelBus) kbusGetUnusedPciePeerId_DISPATCH(pGpu, pKernelBus) #define kbusGetUnusedPciePeerId_HAL(pGpu, pKernelBus) kbusGetUnusedPciePeerId_DISPATCH(pGpu, pKernelBus) #define kbusIsPeerIdValid(pGpu, pKernelBus, peerId) kbusIsPeerIdValid_DISPATCH(pGpu, pKernelBus, peerId) @@ -469,8 +487,6 @@ NV_STATUS __nvoc_objCreate_KernelBus(KernelBus**, Dynamic*, NvU32); #define kbusSetupP2PDomainAccess_HAL(pGpu0, pKernelBus0, pGpu1, ppP2PDomMemDesc) kbusSetupP2PDomainAccess_DISPATCH(pGpu0, pKernelBus0, pGpu1, ppP2PDomMemDesc) #define kbusNeedWarForBug999673(pGpu, pKernelBus, pRemoteGpu) kbusNeedWarForBug999673_DISPATCH(pGpu, pKernelBus, pRemoteGpu) #define kbusNeedWarForBug999673_HAL(pGpu, pKernelBus, pRemoteGpu) kbusNeedWarForBug999673_DISPATCH(pGpu, pKernelBus, pRemoteGpu) -#define kbusRemoveNvlinkPeerMapping(pGpu, pKernelBus, pGpu1, arg0, attributes) kbusRemoveNvlinkPeerMapping_DISPATCH(pGpu, pKernelBus, pGpu1, arg0, attributes) -#define kbusRemoveNvlinkPeerMapping_HAL(pGpu, pKernelBus, pGpu1, arg0, attributes) kbusRemoveNvlinkPeerMapping_DISPATCH(pGpu, pKernelBus, pGpu1, arg0, attributes) #define kbusCreateP2PMappingForC2C(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusCreateP2PMappingForC2C_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) #define kbusCreateP2PMappingForC2C_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusCreateP2PMappingForC2C_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) #define kbusRemoveP2PMappingForC2C(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusRemoveP2PMappingForC2C_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) @@ -483,16 +499,20 @@ NV_STATUS __nvoc_objCreate_KernelBus(KernelBus**, Dynamic*, NvU32); #define kbusRemoveP2PMappingForBar1P2P_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) kbusRemoveP2PMappingForBar1P2P_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) #define kbusHasPcieBar1P2PMapping(pGpu0, pKernelBus0, pGpu1, pKernelBus1) kbusHasPcieBar1P2PMapping_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1) #define kbusHasPcieBar1P2PMapping_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1) kbusHasPcieBar1P2PMapping_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1) +#define kbusCheckFlaSupportedAndInit(pGpu, pKernelBus, base, size) kbusCheckFlaSupportedAndInit_DISPATCH(pGpu, pKernelBus, base, size) +#define kbusCheckFlaSupportedAndInit_HAL(pGpu, pKernelBus, base, size) kbusCheckFlaSupportedAndInit_DISPATCH(pGpu, pKernelBus, base, size) +#define kbusDetermineFlaRangeAndAllocate(pGpu, pKernelBus, base, size) kbusDetermineFlaRangeAndAllocate_DISPATCH(pGpu, pKernelBus, base, size) +#define kbusDetermineFlaRangeAndAllocate_HAL(pGpu, pKernelBus, base, size) kbusDetermineFlaRangeAndAllocate_DISPATCH(pGpu, pKernelBus, base, size) #define kbusAllocateFlaVaspace(pGpu, pKernelBus, arg0, arg1) kbusAllocateFlaVaspace_DISPATCH(pGpu, pKernelBus, arg0, arg1) #define kbusAllocateFlaVaspace_HAL(pGpu, pKernelBus, arg0, arg1) kbusAllocateFlaVaspace_DISPATCH(pGpu, pKernelBus, arg0, arg1) +#define kbusAllocateLegacyFlaVaspace(pGpu, pKernelBus, arg0, arg1) kbusAllocateLegacyFlaVaspace_DISPATCH(pGpu, pKernelBus, arg0, arg1) +#define kbusAllocateLegacyFlaVaspace_HAL(pGpu, pKernelBus, arg0, arg1) kbusAllocateLegacyFlaVaspace_DISPATCH(pGpu, pKernelBus, arg0, arg1) #define kbusAllocateHostManagedFlaVaspace(pGpu, pKernelBus, arg0, arg1, arg2, arg3, arg4, arg5, arg6) kbusAllocateHostManagedFlaVaspace_DISPATCH(pGpu, pKernelBus, arg0, arg1, arg2, arg3, arg4, arg5, arg6) #define kbusAllocateHostManagedFlaVaspace_HAL(pGpu, pKernelBus, arg0, arg1, arg2, arg3, arg4, arg5, arg6) kbusAllocateHostManagedFlaVaspace_DISPATCH(pGpu, pKernelBus, arg0, arg1, arg2, arg3, arg4, arg5, arg6) -#define kbusInitFla(pGpu, pKernelBus, base, size) kbusInitFla_DISPATCH(pGpu, pKernelBus, base, size) -#define kbusInitFla_HAL(pGpu, pKernelBus, base, size) kbusInitFla_DISPATCH(pGpu, pKernelBus, base, size) -#define kbusGetFlaVaspace(pGpu, pKernelBus, arg0) kbusGetFlaVaspace_DISPATCH(pGpu, pKernelBus, arg0) -#define kbusGetFlaVaspace_HAL(pGpu, pKernelBus, arg0) kbusGetFlaVaspace_DISPATCH(pGpu, pKernelBus, arg0) #define kbusDestroyFla(pGpu, pKernelBus) kbusDestroyFla_DISPATCH(pGpu, pKernelBus) #define kbusDestroyFla_HAL(pGpu, pKernelBus) kbusDestroyFla_DISPATCH(pGpu, pKernelBus) +#define kbusGetFlaVaspace(pGpu, pKernelBus, arg0) kbusGetFlaVaspace_DISPATCH(pGpu, pKernelBus, arg0) +#define kbusGetFlaVaspace_HAL(pGpu, pKernelBus, arg0) kbusGetFlaVaspace_DISPATCH(pGpu, pKernelBus, arg0) #define kbusDestroyHostManagedFlaVaspace(pGpu, pKernelBus, arg0) kbusDestroyHostManagedFlaVaspace_DISPATCH(pGpu, pKernelBus, arg0) #define kbusDestroyHostManagedFlaVaspace_HAL(pGpu, pKernelBus, arg0) kbusDestroyHostManagedFlaVaspace_DISPATCH(pGpu, pKernelBus, arg0) #define kbusVerifyFlaRange(pGpu, pKernelBus, arg0, arg1) kbusVerifyFlaRange_DISPATCH(pGpu, pKernelBus, arg0, arg1) @@ -503,10 +523,20 @@ NV_STATUS __nvoc_objCreate_KernelBus(KernelBus**, Dynamic*, NvU32); #define kbusDestructFlaInstBlk_HAL(pGpu, pKernelBus) kbusDestructFlaInstBlk_DISPATCH(pGpu, pKernelBus) #define kbusValidateFlaBaseAddress(pGpu, pKernelBus, flaBaseAddr) kbusValidateFlaBaseAddress_DISPATCH(pGpu, pKernelBus, flaBaseAddr) #define kbusValidateFlaBaseAddress_HAL(pGpu, pKernelBus, flaBaseAddr) kbusValidateFlaBaseAddress_DISPATCH(pGpu, pKernelBus, flaBaseAddr) +#define kbusSetupUnbindFla(pGpu, pKernelBus) kbusSetupUnbindFla_DISPATCH(pGpu, pKernelBus) +#define kbusSetupUnbindFla_HAL(pGpu, pKernelBus) kbusSetupUnbindFla_DISPATCH(pGpu, pKernelBus) +#define kbusSetupBindFla(pGpu, pKernelBus, gfid) kbusSetupBindFla_DISPATCH(pGpu, pKernelBus, gfid) +#define kbusSetupBindFla_HAL(pGpu, pKernelBus, gfid) kbusSetupBindFla_DISPATCH(pGpu, pKernelBus, gfid) #define kbusIsDirectMappingAllowed(pGpu, pKernelBus, arg0, arg1, arg2) kbusIsDirectMappingAllowed_DISPATCH(pGpu, pKernelBus, arg0, arg1, arg2) #define kbusIsDirectMappingAllowed_HAL(pGpu, pKernelBus, arg0, arg1, arg2) kbusIsDirectMappingAllowed_DISPATCH(pGpu, pKernelBus, arg0, arg1, arg2) #define kbusUseDirectSysmemMap(pGpu, pKernelBus, arg0, arg1) kbusUseDirectSysmemMap_DISPATCH(pGpu, pKernelBus, arg0, arg1) #define kbusUseDirectSysmemMap_HAL(pGpu, pKernelBus, arg0, arg1) kbusUseDirectSysmemMap_DISPATCH(pGpu, pKernelBus, arg0, arg1) +#define kbusWriteBAR0WindowBase(pGpu, pKernelBus, base) kbusWriteBAR0WindowBase_DISPATCH(pGpu, pKernelBus, base) +#define kbusWriteBAR0WindowBase_HAL(pGpu, pKernelBus, base) kbusWriteBAR0WindowBase_DISPATCH(pGpu, pKernelBus, base) +#define kbusReadBAR0WindowBase(pGpu, pKernelBus) kbusReadBAR0WindowBase_DISPATCH(pGpu, pKernelBus) +#define kbusReadBAR0WindowBase_HAL(pGpu, pKernelBus) kbusReadBAR0WindowBase_DISPATCH(pGpu, pKernelBus) +#define kbusValidateBAR0WindowBase(pGpu, pKernelBus, base) kbusValidateBAR0WindowBase_DISPATCH(pGpu, pKernelBus, base) +#define kbusValidateBAR0WindowBase_HAL(pGpu, pKernelBus, base) kbusValidateBAR0WindowBase_DISPATCH(pGpu, pKernelBus, base) #define kbusSetBAR0WindowVidOffset(pGpu, pKernelBus, vidOffset) kbusSetBAR0WindowVidOffset_DISPATCH(pGpu, pKernelBus, vidOffset) #define kbusSetBAR0WindowVidOffset_HAL(pGpu, pKernelBus, vidOffset) kbusSetBAR0WindowVidOffset_DISPATCH(pGpu, pKernelBus, vidOffset) #define kbusGetBAR0WindowVidOffset(pGpu, pKernelBus) kbusGetBAR0WindowVidOffset_DISPATCH(pGpu, pKernelBus) @@ -522,7 +552,6 @@ NV_STATUS __nvoc_objCreate_KernelBus(KernelBus**, Dynamic*, NvU32); #define kbusTeardownCoherentCpuMapping(pGpu, pKernelBus, arg0) kbusTeardownCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, arg0) #define kbusTeardownCoherentCpuMapping_HAL(pGpu, pKernelBus, arg0) kbusTeardownCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, arg0) #define kbusReconcileTunableState(pGpu, pEngstate, pTunableState) kbusReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kbusStateLoad(pGpu, pEngstate, arg0) kbusStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kbusStatePreLoad(pGpu, pEngstate, arg0) kbusStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kbusStatePostUnload(pGpu, pEngstate, arg0) kbusStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) #define kbusStateInitUnlocked(pGpu, pEngstate) kbusStateInitUnlocked_DISPATCH(pGpu, pEngstate) @@ -536,6 +565,7 @@ NV_STATUS __nvoc_objCreate_KernelBus(KernelBus**, Dynamic*, NvU32); #define kbusIsPresent(pGpu, pEngstate) kbusIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS kbusInitBarsSize_KERNEL(OBJGPU *pGpu, struct KernelBus *pKernelBus); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusInitBarsSize(OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -549,6 +579,7 @@ static inline NV_STATUS kbusInitBarsSize(OBJGPU *pGpu, struct KernelBus *pKernel NV_STATUS kbusConstructHal_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusConstructHal(OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -562,6 +593,7 @@ static inline NV_STATUS kbusConstructHal(OBJGPU *pGpu, struct KernelBus *pKernel NV_STATUS kbusStateInitLockedKernel_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusStateInitLockedKernel(OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -577,6 +609,9 @@ static inline NV_STATUS kbusStateInitLockedPhysical_56cd7a(OBJGPU *pGpu, struct return NV_OK; } +NV_STATUS kbusStateInitLockedPhysical_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus); + + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusStateInitLockedPhysical(OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -588,8 +623,11 @@ static inline NV_STATUS kbusStateInitLockedPhysical(OBJGPU *pGpu, struct KernelB #define kbusStateInitLockedPhysical_HAL(pGpu, pKernelBus) kbusStateInitLockedPhysical(pGpu, pKernelBus) +NvU8 *kbusMapBar2Aperture_VBAR2_SRIOV(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU32 transfer_flags); + NvU8 *kbusMapBar2Aperture_VBAR2(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU32 transfer_flags); + #ifdef __nvoc_kern_bus_h_disabled static inline NvU8 *kbusMapBar2Aperture(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU32 transfer_flags) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -601,8 +639,11 @@ static inline NvU8 *kbusMapBar2Aperture(OBJGPU *pGpu, struct KernelBus *pKernelB #define kbusMapBar2Aperture_HAL(pGpu, pKernelBus, pMemDesc, transfer_flags) kbusMapBar2Aperture(pGpu, pKernelBus, pMemDesc, transfer_flags) +NvU8 *kbusValidateBar2ApertureMapping_VBAR2_SRIOV(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU8 *p); + NvU8 *kbusValidateBar2ApertureMapping_VBAR2(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU8 *p); + #ifdef __nvoc_kern_bus_h_disabled static inline NvU8 *kbusValidateBar2ApertureMapping(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU8 *p) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -614,8 +655,11 @@ static inline NvU8 *kbusValidateBar2ApertureMapping(OBJGPU *pGpu, struct KernelB #define kbusValidateBar2ApertureMapping_HAL(pGpu, pKernelBus, pMemDesc, p) kbusValidateBar2ApertureMapping(pGpu, pKernelBus, pMemDesc, p) +void kbusUnmapBar2ApertureWithFlags_VBAR2_SRIOV(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU8 **pCpuPtr, NvU32 flags); + void kbusUnmapBar2ApertureWithFlags_VBAR2(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU8 **pCpuPtr, NvU32 flags); + #ifdef __nvoc_kern_bus_h_disabled static inline void kbusUnmapBar2ApertureWithFlags(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU8 **pCpuPtr, NvU32 flags) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -628,6 +672,7 @@ static inline void kbusUnmapBar2ApertureWithFlags(OBJGPU *pGpu, struct KernelBus NV_STATUS kbusUpdateRmAperture_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU64 arg1, NvU64 arg2, NvU32 arg3); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusUpdateRmAperture(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU64 arg1, NvU64 arg2, NvU32 arg3) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -641,6 +686,7 @@ static inline NV_STATUS kbusUpdateRmAperture(OBJGPU *pGpu, struct KernelBus *pKe NV_STATUS kbusSetupBar2GpuVaSpace_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusSetupBar2GpuVaSpace(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -654,6 +700,7 @@ static inline NV_STATUS kbusSetupBar2GpuVaSpace(OBJGPU *pGpu, struct KernelBus * NV_STATUS kbusTeardownBar2GpuVaSpace_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusTeardownBar2GpuVaSpace(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -667,6 +714,7 @@ static inline NV_STATUS kbusTeardownBar2GpuVaSpace(OBJGPU *pGpu, struct KernelBu NvU32 kbusGetSizeOfBar2PageTables_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus); + #ifdef __nvoc_kern_bus_h_disabled static inline NvU32 kbusGetSizeOfBar2PageTables(OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -680,6 +728,7 @@ static inline NvU32 kbusGetSizeOfBar2PageTables(OBJGPU *pGpu, struct KernelBus * NvU32 kbusGetSizeOfBar2PageDirs_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus); + #ifdef __nvoc_kern_bus_h_disabled static inline NvU32 kbusGetSizeOfBar2PageDirs(OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -693,6 +742,9 @@ static inline NvU32 kbusGetSizeOfBar2PageDirs(OBJGPU *pGpu, struct KernelBus *pK NvU64 kbusGetVaLimitForBar2_KERNEL(OBJGPU *pGpu, struct KernelBus *pKernelBus); +NvU64 kbusGetVaLimitForBar2_PHYSICAL(OBJGPU *pGpu, struct KernelBus *pKernelBus); + + #ifdef __nvoc_kern_bus_h_disabled static inline NvU64 kbusGetVaLimitForBar2(OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -706,6 +758,7 @@ static inline NvU64 kbusGetVaLimitForBar2(OBJGPU *pGpu, struct KernelBus *pKerne NV_STATUS kbusCommitBar2_KERNEL(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusCommitBar2(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -719,6 +772,7 @@ static inline NV_STATUS kbusCommitBar2(OBJGPU *pGpu, struct KernelBus *pKernelBu MMU_WALK *kbusGetBar2GmmuWalker_GM107(struct KernelBus *pKernelBus); + #ifdef __nvoc_kern_bus_h_disabled static inline MMU_WALK *kbusGetBar2GmmuWalker(struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -732,6 +786,7 @@ static inline MMU_WALK *kbusGetBar2GmmuWalker(struct KernelBus *pKernelBus) { const struct GMMU_FMT *kbusGetBar2GmmuFmt_GM107(struct KernelBus *pKernelBus); + #ifdef __nvoc_kern_bus_h_disabled static inline const struct GMMU_FMT *kbusGetBar2GmmuFmt(struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -745,6 +800,7 @@ static inline const struct GMMU_FMT *kbusGetBar2GmmuFmt(struct KernelBus *pKerne NV_STATUS kbusPatchBar1Pdb_GSPCLIENT(OBJGPU *pGpu, struct KernelBus *pKernelBus); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusPatchBar1Pdb(OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -758,6 +814,7 @@ static inline NV_STATUS kbusPatchBar1Pdb(OBJGPU *pGpu, struct KernelBus *pKernel NV_STATUS kbusPatchBar2Pdb_GSPCLIENT(OBJGPU *pGpu, struct KernelBus *pKernelBus); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusPatchBar2Pdb(OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -771,6 +828,7 @@ static inline NV_STATUS kbusPatchBar2Pdb(OBJGPU *pGpu, struct KernelBus *pKernel NV_STATUS kbusSetBarsApertureSize_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusSetBarsApertureSize(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -784,6 +842,7 @@ static inline NV_STATUS kbusSetBarsApertureSize(OBJGPU *pGpu, struct KernelBus * NV_STATUS kbusConstructVirtualBar2_VBAR2(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusConstructVirtualBar2(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -797,6 +856,7 @@ static inline NV_STATUS kbusConstructVirtualBar2(OBJGPU *pGpu, struct KernelBus void kbusDestructVirtualBar2_VBAR2(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvBool shutdown, NvU32 gfid); + #ifdef __nvoc_kern_bus_h_disabled static inline void kbusDestructVirtualBar2(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvBool shutdown, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -809,6 +869,7 @@ static inline void kbusDestructVirtualBar2(OBJGPU *pGpu, struct KernelBus *pKern void kbusFlushVirtualBar2_VBAR2(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvBool shutdown, NvU32 gfid); + #ifdef __nvoc_kern_bus_h_disabled static inline void kbusFlushVirtualBar2(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvBool shutdown, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -821,6 +882,7 @@ static inline void kbusFlushVirtualBar2(OBJGPU *pGpu, struct KernelBus *pKernelB NV_STATUS kbusInitVirtualBar2_VBAR2(OBJGPU *pGpu, struct KernelBus *pKernelBus); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusInitVirtualBar2(OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -834,6 +896,7 @@ static inline NV_STATUS kbusInitVirtualBar2(OBJGPU *pGpu, struct KernelBus *pKer NV_STATUS kbusPreInitVirtualBar2_VBAR2(OBJGPU *pGpu, struct KernelBus *pKernelBus); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusPreInitVirtualBar2(OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -847,6 +910,7 @@ static inline NV_STATUS kbusPreInitVirtualBar2(OBJGPU *pGpu, struct KernelBus *p NV_STATUS kbusConstructVirtualBar2CpuVisibleHeap_VBAR2(struct KernelBus *pKernelBus, NvU32 gfid); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusConstructVirtualBar2CpuVisibleHeap(struct KernelBus *pKernelBus, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -862,6 +926,9 @@ static inline NV_STATUS kbusConstructVirtualBar2CpuInvisibleHeap_56cd7a(struct K return NV_OK; } +NV_STATUS kbusConstructVirtualBar2CpuInvisibleHeap_VBAR2(struct KernelBus *pKernelBus, NvU32 gfid); + + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusConstructVirtualBar2CpuInvisibleHeap(struct KernelBus *pKernelBus, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -877,6 +944,9 @@ static inline NV_STATUS kbusMapCpuInvisibleBar2Aperture_46f6a7(OBJGPU *pGpu, str return NV_ERR_NOT_SUPPORTED; } +NV_STATUS kbusMapCpuInvisibleBar2Aperture_VBAR2(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 *pVaddr, NvU64 allocSize, NvU32 allocFlags, NvU32 gfid); + + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusMapCpuInvisibleBar2Aperture(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 *pVaddr, NvU64 allocSize, NvU32 allocFlags, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -892,6 +962,9 @@ static inline void kbusUnmapCpuInvisibleBar2Aperture_b3696a(OBJGPU *pGpu, struct return; } +void kbusUnmapCpuInvisibleBar2Aperture_VBAR2(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 vAddr, NvU32 gfid); + + #ifdef __nvoc_kern_bus_h_disabled static inline void kbusUnmapCpuInvisibleBar2Aperture(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 vAddr, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -904,6 +977,7 @@ static inline void kbusUnmapCpuInvisibleBar2Aperture(OBJGPU *pGpu, struct Kernel NV_STATUS kbusSetupCpuPointerForBusFlush_GV100(OBJGPU *pGpu, struct KernelBus *pKernelBus); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusSetupCpuPointerForBusFlush(OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -917,6 +991,7 @@ static inline NV_STATUS kbusSetupCpuPointerForBusFlush(OBJGPU *pGpu, struct Kern void kbusDestroyCpuPointerForBusFlush_GV100(OBJGPU *pGpu, struct KernelBus *pKernelBus); + #ifdef __nvoc_kern_bus_h_disabled static inline void kbusDestroyCpuPointerForBusFlush(OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -929,6 +1004,7 @@ static inline void kbusDestroyCpuPointerForBusFlush(OBJGPU *pGpu, struct KernelB NV_STATUS kbusSetupBar2CpuAperture_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusSetupBar2CpuAperture(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -942,6 +1018,7 @@ static inline NV_STATUS kbusSetupBar2CpuAperture(OBJGPU *pGpu, struct KernelBus NV_STATUS kbusSetP2PMailboxBar1Area_GM200(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 mailboxBar1Addr, NvU32 mailboxTotalSize); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusSetP2PMailboxBar1Area(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 mailboxBar1Addr, NvU32 mailboxTotalSize) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -955,6 +1032,7 @@ static inline NV_STATUS kbusSetP2PMailboxBar1Area(OBJGPU *pGpu, struct KernelBus void kbusUnsetP2PMailboxBar1Area_GM200(OBJGPU *pGpu, struct KernelBus *pKernelBus); + #ifdef __nvoc_kern_bus_h_disabled static inline void kbusUnsetP2PMailboxBar1Area(OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -967,6 +1045,7 @@ static inline void kbusUnsetP2PMailboxBar1Area(OBJGPU *pGpu, struct KernelBus *p NV_STATUS kbusAllocP2PMailboxBar1_GM200(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid, NvU64 vaRangeMax); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusAllocP2PMailboxBar1(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid, NvU64 vaRangeMax) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -980,6 +1059,7 @@ static inline NV_STATUS kbusAllocP2PMailboxBar1(OBJGPU *pGpu, struct KernelBus * RmPhysAddr kbusSetupMailboxAccess_GM200(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pGpu1, NvU32 localPeerId, PMEMORY_DESCRIPTOR *ppWMBoxMemDesc); + #ifdef __nvoc_kern_bus_h_disabled static inline RmPhysAddr kbusSetupMailboxAccess(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pGpu1, NvU32 localPeerId, PMEMORY_DESCRIPTOR *ppWMBoxMemDesc) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -995,6 +1075,7 @@ static inline RmPhysAddr kbusSetupMailboxAccess(OBJGPU *pGpu, struct KernelBus * void kbusDestroyPeerAccess_GM200(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerNum); + #ifdef __nvoc_kern_bus_h_disabled static inline void kbusDestroyPeerAccess(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerNum) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1007,6 +1088,7 @@ static inline void kbusDestroyPeerAccess(OBJGPU *pGpu, struct KernelBus *pKernel NvU32 kbusGetPeerIdFromTable_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 locPeerIdx, NvU32 remPeerIdx); + #ifdef __nvoc_kern_bus_h_disabled static inline NvU32 kbusGetPeerIdFromTable(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 locPeerIdx, NvU32 remPeerIdx) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1020,6 +1102,7 @@ static inline NvU32 kbusGetPeerIdFromTable(OBJGPU *pGpu, struct KernelBus *pKern NvU32 kbusGetUnusedPeerId_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus); + #ifdef __nvoc_kern_bus_h_disabled static inline NvU32 kbusGetUnusedPeerId(OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1033,6 +1116,7 @@ static inline NvU32 kbusGetUnusedPeerId(OBJGPU *pGpu, struct KernelBus *pKernelB NV_STATUS kbusReserveP2PPeerIds_GM200(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerMask); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusReserveP2PPeerIds(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerMask) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1046,6 +1130,7 @@ static inline NV_STATUS kbusReserveP2PPeerIds(OBJGPU *pGpu, struct KernelBus *pK NV_STATUS kbusCreateP2PMappingForMailbox_GM200(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusCreateP2PMappingForMailbox(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1059,6 +1144,7 @@ static inline NV_STATUS kbusCreateP2PMappingForMailbox(OBJGPU *pGpu0, struct Ker NV_STATUS kbusRemoveP2PMappingForMailbox_GM200(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusRemoveP2PMappingForMailbox(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1072,6 +1158,7 @@ static inline NV_STATUS kbusRemoveP2PMappingForMailbox(OBJGPU *pGpu0, struct Ker void kbusSetupMailboxes_GM200(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 arg0, NvU32 arg1); + #ifdef __nvoc_kern_bus_h_disabled static inline void kbusSetupMailboxes(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 arg0, NvU32 arg1) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1084,6 +1171,7 @@ static inline void kbusSetupMailboxes(OBJGPU *pGpu0, struct KernelBus *pKernelBu NV_STATUS kbusCreateP2PMappingForNvlink_GP100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusCreateP2PMappingForNvlink(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1097,6 +1185,7 @@ static inline NV_STATUS kbusCreateP2PMappingForNvlink(OBJGPU *pGpu0, struct Kern NV_STATUS kbusRemoveP2PMappingForNvlink_GP100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusRemoveP2PMappingForNvlink(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1110,6 +1199,7 @@ static inline NV_STATUS kbusRemoveP2PMappingForNvlink(OBJGPU *pGpu0, struct Kern NvU32 kbusGetNvlinkPeerNumberMask_GP100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerId); + #ifdef __nvoc_kern_bus_h_disabled static inline NvU32 kbusGetNvlinkPeerNumberMask(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerId) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1123,6 +1213,7 @@ static inline NvU32 kbusGetNvlinkPeerNumberMask(OBJGPU *pGpu, struct KernelBus * void kbusUnlinkP2P_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBu); + #ifdef __nvoc_kern_bus_h_disabled static inline void kbusUnlinkP2P(OBJGPU *pGpu, struct KernelBus *pKernelBu) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1137,6 +1228,7 @@ static inline NvBool kbusIsPcieBar1P2PMappingSupported_491d52(OBJGPU *pGpu0, str return ((NvBool)(0 != 0)); } + #ifdef __nvoc_kern_bus_h_disabled static inline NvBool kbusIsPcieBar1P2PMappingSupported(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1152,6 +1244,7 @@ static inline void kbusSetupBar1P2PCapability_b3696a(OBJGPU *pGpu, struct Kernel return; } + #ifdef __nvoc_kern_bus_h_disabled static inline void kbusSetupBar1P2PCapability(OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1162,34 +1255,9 @@ static inline void kbusSetupBar1P2PCapability(OBJGPU *pGpu, struct KernelBus *pK #define kbusSetupBar1P2PCapability_HAL(pGpu, pKernelBus) kbusSetupBar1P2PCapability(pGpu, pKernelBus) -NV_STATUS kbusSetupUnbindFla_KERNEL(OBJGPU *pGpu, struct KernelBus *pKernelBus); - -#ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusSetupUnbindFla(OBJGPU *pGpu, struct KernelBus *pKernelBus) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_bus_h_disabled -#define kbusSetupUnbindFla(pGpu, pKernelBus) kbusSetupUnbindFla_KERNEL(pGpu, pKernelBus) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusSetupUnbindFla_HAL(pGpu, pKernelBus) kbusSetupUnbindFla(pGpu, pKernelBus) - -NV_STATUS kbusSetupBindFla_KERNEL(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); - -#ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusSetupBindFla(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_bus_h_disabled -#define kbusSetupBindFla(pGpu, pKernelBus, gfid) kbusSetupBindFla_KERNEL(pGpu, pKernelBus, gfid) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusSetupBindFla_HAL(pGpu, pKernelBus, gfid) kbusSetupBindFla(pGpu, pKernelBus, gfid) - NV_STATUS kbusFlushSingle_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusFlushSingle(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1203,6 +1271,7 @@ static inline NV_STATUS kbusFlushSingle(OBJGPU *pGpu, struct KernelBus *pKernelB NV_STATUS kbusSendSysmembarSingle_KERNEL(OBJGPU *pGpu, struct KernelBus *pKernelBus); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusSendSysmembarSingle(OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1216,6 +1285,7 @@ static inline NV_STATUS kbusSendSysmembarSingle(OBJGPU *pGpu, struct KernelBus * void kbusInitPciBars_GM107(struct KernelBus *pKernelBus); + #ifdef __nvoc_kern_bus_h_disabled static inline void kbusInitPciBars(struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1228,6 +1298,7 @@ static inline void kbusInitPciBars(struct KernelBus *pKernelBus) { NV_STATUS kbusInitBarsBaseInfo_GM107(struct KernelBus *pKernelBus); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusInitBarsBaseInfo(struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1241,6 +1312,7 @@ static inline NV_STATUS kbusInitBarsBaseInfo(struct KernelBus *pKernelBus) { NV_STATUS kbusMemAccessBar0Window_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 physAddr, void *pData, NvU64 accessSize, NvBool bRead, NV_ADDRESS_SPACE addrSpace); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusMemAccessBar0Window(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 physAddr, void *pData, NvU64 accessSize, NvBool bRead, NV_ADDRESS_SPACE addrSpace) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1254,6 +1326,7 @@ static inline NV_STATUS kbusMemAccessBar0Window(OBJGPU *pGpu, struct KernelBus * NV_STATUS kbusMemCopyBar0Window_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, RmPhysAddr physAddr, void *pData, NvLength copySize, NvBool bRead); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusMemCopyBar0Window(OBJGPU *pGpu, struct KernelBus *pKernelBus, RmPhysAddr physAddr, void *pData, NvLength copySize, NvBool bRead) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1267,6 +1340,7 @@ static inline NV_STATUS kbusMemCopyBar0Window(OBJGPU *pGpu, struct KernelBus *pK NvU64 kbusGetBAR0WindowAddress_GM107(struct KernelBus *pKernelBus); + #ifdef __nvoc_kern_bus_h_disabled static inline NvU64 kbusGetBAR0WindowAddress(struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1280,6 +1354,7 @@ static inline NvU64 kbusGetBAR0WindowAddress(struct KernelBus *pKernelBus) { NV_STATUS kbusSetupBar0WindowBeforeBar2Bootstrap_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 *arg0); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusSetupBar0WindowBeforeBar2Bootstrap(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 *arg0) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1293,6 +1368,7 @@ static inline NV_STATUS kbusSetupBar0WindowBeforeBar2Bootstrap(OBJGPU *pGpu, str void kbusRestoreBar0WindowAfterBar2Bootstrap_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0); + #ifdef __nvoc_kern_bus_h_disabled static inline void kbusRestoreBar0WindowAfterBar2Bootstrap(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1305,6 +1381,7 @@ static inline void kbusRestoreBar0WindowAfterBar2Bootstrap(OBJGPU *pGpu, struct NV_STATUS kbusInitBar2_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusInitBar2(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1318,6 +1395,7 @@ static inline NV_STATUS kbusInitBar2(OBJGPU *pGpu, struct KernelBus *pKernelBus, NV_STATUS kbusDestroyBar2_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusDestroyBar2(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1331,6 +1409,7 @@ static inline NV_STATUS kbusDestroyBar2(OBJGPU *pGpu, struct KernelBus *pKernelB NV_STATUS kbusInitBar1_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusInitBar1(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1344,6 +1423,7 @@ static inline NV_STATUS kbusInitBar1(OBJGPU *pGpu, struct KernelBus *pKernelBus, NV_STATUS kbusDestroyBar1_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusDestroyBar1(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1357,6 +1437,7 @@ static inline NV_STATUS kbusDestroyBar1(OBJGPU *pGpu, struct KernelBus *pKernelB NV_STATUS kbusMapFbAperture_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU64 offset, NvU64 *pAperOffset, NvU64 *pLength, NvU32 flags, NvHandle hClient); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusMapFbAperture(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU64 offset, NvU64 *pAperOffset, NvU64 *pLength, NvU32 flags, NvHandle hClient) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1370,6 +1451,7 @@ static inline NV_STATUS kbusMapFbAperture(OBJGPU *pGpu, struct KernelBus *pKerne NV_STATUS kbusUnmapFbAperture_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU64 aperOffset, NvU64 length, NvU32 flags); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusUnmapFbAperture(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU64 aperOffset, NvU64 length, NvU32 flags) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1383,6 +1465,7 @@ static inline NV_STATUS kbusUnmapFbAperture(OBJGPU *pGpu, struct KernelBus *pKer void kbusReleaseRmAperture_VBAR2(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0); + #ifdef __nvoc_kern_bus_h_disabled static inline void kbusReleaseRmAperture(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1395,6 +1478,7 @@ static inline void kbusReleaseRmAperture(OBJGPU *pGpu, struct KernelBus *pKernel struct OBJVASPACE *kbusGetBar1VASpace_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus); + #ifdef __nvoc_kern_bus_h_disabled static inline struct OBJVASPACE *kbusGetBar1VASpace(OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1410,6 +1494,7 @@ static inline NV_STATUS kbusInitInstBlk_56cd7a(OBJGPU *pGpu, struct KernelBus *p return NV_OK; } + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusInitInstBlk(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR pInstBlkMemDesc, PMEMORY_DESCRIPTOR pPDB, NvU64 vaLimit, NvU32 bigPageSize, struct OBJVASPACE *pVAS) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1425,6 +1510,9 @@ static inline NV_STATUS kbusBar1InstBlkVasUpdate_56cd7a(OBJGPU *pGpu, struct Ker return NV_OK; } +NV_STATUS kbusBar1InstBlkVasUpdate_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus); + + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusBar1InstBlkVasUpdate(OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1438,6 +1526,7 @@ static inline NV_STATUS kbusBar1InstBlkVasUpdate(OBJGPU *pGpu, struct KernelBus NvBool kbusCheckEngine_KERNEL(OBJGPU *pGpu, struct KernelBus *pKernelBus, ENGDESCRIPTOR desc); + #ifdef __nvoc_kern_bus_h_disabled static inline NvBool kbusCheckEngine(OBJGPU *pGpu, struct KernelBus *pKernelBus, ENGDESCRIPTOR desc) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1451,6 +1540,7 @@ static inline NvBool kbusCheckEngine(OBJGPU *pGpu, struct KernelBus *pKernelBus, NV_STATUS kbusFlush_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusFlush(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1466,6 +1556,7 @@ static inline NV_STATUS kbusCreateCoherentCpuMapping_46f6a7(OBJGPU *pGpu, struct return NV_ERR_NOT_SUPPORTED; } + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusCreateCoherentCpuMapping(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvBool bFlush) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1481,6 +1572,7 @@ static inline void kbusTeardownCoherentCpuMappingAcr_b3696a(OBJGPU *pGpu, struct return; } + #ifdef __nvoc_kern_bus_h_disabled static inline void kbusTeardownCoherentCpuMappingAcr(OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -1499,10 +1591,6 @@ static inline NV_STATUS kbusConstructEngine_DISPATCH(OBJGPU *pGpu, struct Kernel NV_STATUS kbusStatePreInitLocked_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus); -static inline NV_STATUS kbusStatePreInitLocked_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus) { - return NV_OK; -} - static inline NV_STATUS kbusStatePreInitLocked_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus) { return pKernelBus->__kbusStatePreInitLocked__(pGpu, pKernelBus); } @@ -1513,30 +1601,24 @@ static inline NV_STATUS kbusStateInitLocked_DISPATCH(OBJGPU *pGpu, struct Kernel return pKernelBus->__kbusStateInitLocked__(pGpu, pKernelBus); } -NV_STATUS kbusStatePostLoad_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0); +NV_STATUS kbusStateLoad_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0); -static inline NV_STATUS kbusStatePostLoad_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0) { - return NV_OK; +static inline NV_STATUS kbusStateLoad_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0) { + return pKernelBus->__kbusStateLoad__(pGpu, pKernelBus, arg0); } +NV_STATUS kbusStatePostLoad_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0); + static inline NV_STATUS kbusStatePostLoad_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0) { return pKernelBus->__kbusStatePostLoad__(pGpu, pKernelBus, arg0); } NV_STATUS kbusStatePreUnload_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0); -static inline NV_STATUS kbusStatePreUnload_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0) { - return NV_OK; -} - static inline NV_STATUS kbusStatePreUnload_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0) { return pKernelBus->__kbusStatePreUnload__(pGpu, pKernelBus, arg0); } -static inline NV_STATUS kbusStateUnload_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags) { - return NV_OK; -} - NV_STATUS kbusStateUnload_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags); static inline NV_STATUS kbusStateUnload_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags) { @@ -1549,10 +1631,6 @@ static inline void kbusStateDestroy_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKe pKernelBus->__kbusStateDestroy__(pGpu, pKernelBus); } -static inline NV_STATUS kbusTeardownBar2CpuAperture_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { - return NV_OK; -} - NV_STATUS kbusTeardownBar2CpuAperture_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); NV_STATUS kbusTeardownBar2CpuAperture_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); @@ -1561,14 +1639,18 @@ static inline NV_STATUS kbusTeardownBar2CpuAperture_DISPATCH(OBJGPU *pGpu, struc return pKernelBus->__kbusTeardownBar2CpuAperture__(pGpu, pKernelBus, gfid); } +NvU32 kbusGetP2PWriteMailboxAddressSize_GH100(OBJGPU *pGpu); + +static inline NvU32 kbusGetP2PWriteMailboxAddressSize_474d46(OBJGPU *pGpu) { + NV_ASSERT_OR_RETURN_PRECOMP(0, 0); +} + +NvU32 kbusGetP2PWriteMailboxAddressSize_STATIC_DISPATCH(OBJGPU *pGpu); + void kbusGetP2PMailboxAttributes_GM200(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 *pMailboxAreaSize, NvU32 *pMailboxAlignmentSize, NvU32 *pMailboxMaxOffset64KB); void kbusGetP2PMailboxAttributes_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 *pMailboxAreaSize, NvU32 *pMailboxAlignmentSize, NvU32 *pMailboxMaxOffset64KB); -static inline void kbusGetP2PMailboxAttributes_b3696a(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 *pMailboxAreaSize, NvU32 *pMailboxAlignmentSize, NvU32 *pMailboxMaxOffset64KB) { - return; -} - static inline void kbusGetP2PMailboxAttributes_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 *pMailboxAreaSize, NvU32 *pMailboxAlignmentSize, NvU32 *pMailboxMaxOffset64KB) { pKernelBus->__kbusGetP2PMailboxAttributes__(pGpu, pKernelBus, pMailboxAreaSize, pMailboxAlignmentSize, pMailboxMaxOffset64KB); } @@ -1577,10 +1659,6 @@ NV_STATUS kbusCreateP2PMapping_GP100(OBJGPU *pGpu0, struct KernelBus *pKernelBus NV_STATUS kbusCreateP2PMapping_GH100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes); -static inline NV_STATUS kbusCreateP2PMapping_46f6a7(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes) { - return NV_ERR_NOT_SUPPORTED; -} - static inline NV_STATUS kbusCreateP2PMapping_DISPATCH(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes) { return pKernelBus0->__kbusCreateP2PMapping__(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes); } @@ -1589,10 +1667,6 @@ NV_STATUS kbusRemoveP2PMapping_GP100(OBJGPU *pGpu0, struct KernelBus *pKernelBus NV_STATUS kbusRemoveP2PMapping_GH100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes); -static inline NV_STATUS kbusRemoveP2PMapping_46f6a7(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes) { - return NV_ERR_NOT_SUPPORTED; -} - static inline NV_STATUS kbusRemoveP2PMapping_DISPATCH(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes) { return pKernelBus0->__kbusRemoveP2PMapping__(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes); } @@ -1605,6 +1679,16 @@ static inline NvU32 kbusGetPeerId_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKern return pKernelBus->__kbusGetPeerId__(pGpu, pKernelBus, pPeerGpu); } +NvU32 kbusGetNvSwitchPeerId_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus); + +static inline NvU32 kbusGetNvSwitchPeerId_c732fb(OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return 4294967295U; +} + +static inline NvU32 kbusGetNvSwitchPeerId_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return pKernelBus->__kbusGetNvSwitchPeerId__(pGpu, pKernelBus); +} + NvU32 kbusGetUnusedPciePeerId_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus); NvU32 kbusGetUnusedPciePeerId_TU102(OBJGPU *pGpu, struct KernelBus *pKernelBus); @@ -1637,10 +1721,6 @@ void kbusWriteP2PWmbTag_GM200(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 void kbusWriteP2PWmbTag_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 remote2Local, NvU64 p2pWmbTag); -static inline void kbusWriteP2PWmbTag_f2d351(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 remote2Local, NvU64 p2pWmbTag) { - NV_ASSERT_PRECOMP(0); -} - static inline void kbusWriteP2PWmbTag_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 remote2Local, NvU64 p2pWmbTag) { pKernelBus->__kbusWriteP2PWmbTag__(pGpu, pKernelBus, remote2Local, p2pWmbTag); } @@ -1649,10 +1729,6 @@ RmPhysAddr kbusSetupP2PDomainAccess_GM200(OBJGPU *pGpu0, struct KernelBus *pKern RmPhysAddr kbusSetupP2PDomainAccess_GH100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, PMEMORY_DESCRIPTOR *ppP2PDomMemDesc); -static inline RmPhysAddr kbusSetupP2PDomainAccess_100832(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, PMEMORY_DESCRIPTOR *ppP2PDomMemDesc) { - NV_ASSERT_OR_RETURN_PRECOMP(0, ~0ULL); -} - static inline RmPhysAddr kbusSetupP2PDomainAccess_DISPATCH(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, PMEMORY_DESCRIPTOR *ppP2PDomMemDesc) { return pKernelBus0->__kbusSetupP2PDomainAccess__(pGpu0, pKernelBus0, pGpu1, ppP2PDomMemDesc); } @@ -1667,16 +1743,6 @@ static inline NvBool kbusNeedWarForBug999673_DISPATCH(OBJGPU *pGpu, struct Kerne return pKernelBus->__kbusNeedWarForBug999673__(pGpu, pKernelBus, pRemoteGpu); } -NV_STATUS kbusRemoveNvlinkPeerMapping_GP100(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pGpu1, NvU32 arg0, NvU32 attributes); - -static inline NV_STATUS kbusRemoveNvlinkPeerMapping_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pGpu1, NvU32 arg0, NvU32 attributes) { - return NV_OK; -} - -static inline NV_STATUS kbusRemoveNvlinkPeerMapping_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pGpu1, NvU32 arg0, NvU32 attributes) { - return pKernelBus->__kbusRemoveNvlinkPeerMapping__(pGpu, pKernelBus, pGpu1, arg0, attributes); -} - NV_STATUS kbusCreateP2PMappingForC2C_GH100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes); static inline NV_STATUS kbusCreateP2PMappingForC2C_46f6a7(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes) { @@ -1737,8 +1803,32 @@ static inline NvBool kbusHasPcieBar1P2PMapping_DISPATCH(OBJGPU *pGpu0, struct Ke return pKernelBus0->__kbusHasPcieBar1P2PMapping__(pGpu0, pKernelBus0, pGpu1, pKernelBus1); } +NV_STATUS kbusCheckFlaSupportedAndInit_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 base, NvU64 size); + +static inline NV_STATUS kbusCheckFlaSupportedAndInit_ac1694(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 base, NvU64 size) { + return NV_OK; +} + +static inline NV_STATUS kbusCheckFlaSupportedAndInit_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 base, NvU64 size) { + return pKernelBus->__kbusCheckFlaSupportedAndInit__(pGpu, pKernelBus, base, size); +} + +NV_STATUS kbusDetermineFlaRangeAndAllocate_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 base, NvU64 size); + +NV_STATUS kbusDetermineFlaRangeAndAllocate_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 base, NvU64 size); + +static inline NV_STATUS kbusDetermineFlaRangeAndAllocate_395e98(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 base, NvU64 size) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kbusDetermineFlaRangeAndAllocate_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 base, NvU64 size) { + return pKernelBus->__kbusDetermineFlaRangeAndAllocate__(pGpu, pKernelBus, base, size); +} + NV_STATUS kbusAllocateFlaVaspace_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0, NvU64 arg1); +NV_STATUS kbusAllocateFlaVaspace_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0, NvU64 arg1); + static inline NV_STATUS kbusAllocateFlaVaspace_395e98(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0, NvU64 arg1) { return NV_ERR_NOT_SUPPORTED; } @@ -1747,6 +1837,16 @@ static inline NV_STATUS kbusAllocateFlaVaspace_DISPATCH(OBJGPU *pGpu, struct Ker return pKernelBus->__kbusAllocateFlaVaspace__(pGpu, pKernelBus, arg0, arg1); } +NV_STATUS kbusAllocateLegacyFlaVaspace_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0, NvU64 arg1); + +static inline NV_STATUS kbusAllocateLegacyFlaVaspace_395e98(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0, NvU64 arg1) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kbusAllocateLegacyFlaVaspace_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0, NvU64 arg1) { + return pKernelBus->__kbusAllocateLegacyFlaVaspace__(pGpu, pKernelBus, arg0, arg1); +} + NV_STATUS kbusAllocateHostManagedFlaVaspace_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle arg0, NvHandle arg1, NvHandle arg2, NvHandle arg3, NvU64 arg4, NvU64 arg5, NvU32 arg6); static inline NV_STATUS kbusAllocateHostManagedFlaVaspace_395e98(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle arg0, NvHandle arg1, NvHandle arg2, NvHandle arg3, NvU64 arg4, NvU64 arg5, NvU32 arg6) { @@ -1757,14 +1857,16 @@ static inline NV_STATUS kbusAllocateHostManagedFlaVaspace_DISPATCH(OBJGPU *pGpu, return pKernelBus->__kbusAllocateHostManagedFlaVaspace__(pGpu, pKernelBus, arg0, arg1, arg2, arg3, arg4, arg5, arg6); } -NV_STATUS kbusInitFla_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 base, NvU64 size); +void kbusDestroyFla_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus); -static inline NV_STATUS kbusInitFla_ac1694(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 base, NvU64 size) { - return NV_OK; +void kbusDestroyFla_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus); + +static inline void kbusDestroyFla_d44104(OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return; } -static inline NV_STATUS kbusInitFla_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 base, NvU64 size) { - return pKernelBus->__kbusInitFla__(pGpu, pKernelBus, base, size); +static inline void kbusDestroyFla_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus) { + pKernelBus->__kbusDestroyFla__(pGpu, pKernelBus); } NV_STATUS kbusGetFlaVaspace_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus, struct OBJVASPACE **arg0); @@ -1777,16 +1879,6 @@ static inline NV_STATUS kbusGetFlaVaspace_DISPATCH(OBJGPU *pGpu, struct KernelBu return pKernelBus->__kbusGetFlaVaspace__(pGpu, pKernelBus, arg0); } -void kbusDestroyFla_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus); - -static inline void kbusDestroyFla_d44104(OBJGPU *pGpu, struct KernelBus *pKernelBus) { - return; -} - -static inline void kbusDestroyFla_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus) { - pKernelBus->__kbusDestroyFla__(pGpu, pKernelBus); -} - void kbusDestroyHostManagedFlaVaspace_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0); static inline void kbusDestroyHostManagedFlaVaspace_d44104(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0) { @@ -1837,6 +1929,30 @@ static inline NV_STATUS kbusValidateFlaBaseAddress_DISPATCH(OBJGPU *pGpu, struct return pKernelBus->__kbusValidateFlaBaseAddress__(pGpu, pKernelBus, flaBaseAddr); } +NV_STATUS kbusSetupUnbindFla_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus); + +NV_STATUS kbusSetupUnbindFla_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus); + +static inline NV_STATUS kbusSetupUnbindFla_46f6a7(OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kbusSetupUnbindFla_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return pKernelBus->__kbusSetupUnbindFla__(pGpu, pKernelBus); +} + +NV_STATUS kbusSetupBindFla_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); + +NV_STATUS kbusSetupBindFla_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); + +static inline NV_STATUS kbusSetupBindFla_46f6a7(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kbusSetupBindFla_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { + return pKernelBus->__kbusSetupBindFla__(pGpu, pKernelBus, gfid); +} + NV_STATUS kbusIsDirectMappingAllowed_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU32 arg1, NvBool *arg2); NV_STATUS kbusIsDirectMappingAllowed_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU32 arg1, NvBool *arg2); @@ -1849,26 +1965,46 @@ NV_STATUS kbusUseDirectSysmemMap_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBu NV_STATUS kbusUseDirectSysmemMap_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *arg0, NvBool *arg1); -static inline NV_STATUS kbusUseDirectSysmemMap_46f6a7(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *arg0, NvBool *arg1) { - return NV_ERR_NOT_SUPPORTED; -} - static inline NV_STATUS kbusUseDirectSysmemMap_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *arg0, NvBool *arg1) { return pKernelBus->__kbusUseDirectSysmemMap__(pGpu, pKernelBus, arg0, arg1); } -static inline NV_STATUS kbusSetBAR0WindowVidOffset_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 vidOffset) { - return NV_OK; +NV_STATUS kbusWriteBAR0WindowBase_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 base); + +static inline NV_STATUS kbusWriteBAR0WindowBase_395e98(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 base) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kbusWriteBAR0WindowBase_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 base) { + return pKernelBus->__kbusWriteBAR0WindowBase__(pGpu, pKernelBus, base); +} + +NvU32 kbusReadBAR0WindowBase_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus); + +static inline NvU32 kbusReadBAR0WindowBase_13cd8d(OBJGPU *pGpu, struct KernelBus *pKernelBus) { + NV_ASSERT_PRECOMP(0); + return 0; +} + +static inline NvU32 kbusReadBAR0WindowBase_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return pKernelBus->__kbusReadBAR0WindowBase__(pGpu, pKernelBus); +} + +NvBool kbusValidateBAR0WindowBase_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 base); + +static inline NvBool kbusValidateBAR0WindowBase_ceaee8(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 base) { + NV_ASSERT_PRECOMP(0); + return ((NvBool)(0 != 0)); +} + +static inline NvBool kbusValidateBAR0WindowBase_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 base) { + return pKernelBus->__kbusValidateBAR0WindowBase__(pGpu, pKernelBus, base); } NV_STATUS kbusSetBAR0WindowVidOffset_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 vidOffset); NV_STATUS kbusSetBAR0WindowVidOffset_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 vidOffset); -static inline NV_STATUS kbusSetBAR0WindowVidOffset_395e98(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 vidOffset) { - return NV_ERR_NOT_SUPPORTED; -} - static inline NV_STATUS kbusSetBAR0WindowVidOffset_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 vidOffset) { return pKernelBus->__kbusSetBAR0WindowVidOffset__(pGpu, pKernelBus, vidOffset); } @@ -1877,19 +2013,10 @@ NvU64 kbusGetBAR0WindowVidOffset_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBu NvU64 kbusGetBAR0WindowVidOffset_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus); -static inline NvU64 kbusGetBAR0WindowVidOffset_13cd8d(OBJGPU *pGpu, struct KernelBus *pKernelBus) { - NV_ASSERT_PRECOMP(0); - return 0; -} - static inline NvU64 kbusGetBAR0WindowVidOffset_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus) { return pKernelBus->__kbusGetBAR0WindowVidOffset__(pGpu, pKernelBus); } -static inline NV_STATUS kbusVerifyBar2_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR memDescIn, NvU8 *pCpuPtrIn, NvU64 offset, NvU64 size) { - return NV_OK; -} - NV_STATUS kbusVerifyBar2_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR memDescIn, NvU8 *pCpuPtrIn, NvU64 offset, NvU64 size); NV_STATUS kbusVerifyBar2_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR memDescIn, NvU8 *pCpuPtrIn, NvU64 offset, NvU64 size); @@ -1942,10 +2069,6 @@ static inline NV_STATUS kbusReconcileTunableState_DISPATCH(POBJGPU pGpu, struct return pEngstate->__kbusReconcileTunableState__(pGpu, pEngstate, pTunableState); } -static inline NV_STATUS kbusStateLoad_DISPATCH(POBJGPU pGpu, struct KernelBus *pEngstate, NvU32 arg0) { - return pEngstate->__kbusStateLoad__(pGpu, pEngstate, arg0); -} - static inline NV_STATUS kbusStatePreLoad_DISPATCH(POBJGPU pGpu, struct KernelBus *pEngstate, NvU32 arg0) { return pEngstate->__kbusStatePreLoad__(pGpu, pEngstate, arg0); } @@ -2063,8 +2186,10 @@ static inline NvBool kbusIsBar1P2PCapable(struct KernelBus *pKernelBus) { } void kbusDestruct_IMPL(struct KernelBus *pKernelBus); + #define __nvoc_kbusDestruct(pKernelBus) kbusDestruct_IMPL(pKernelBus) void kbusGetDeviceCaps_IMPL(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU8 *pHostCaps, NvBool bCapsInitialized); + #ifdef __nvoc_kern_bus_h_disabled static inline void kbusGetDeviceCaps(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU8 *pHostCaps, NvBool bCapsInitialized) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -2074,6 +2199,7 @@ static inline void kbusGetDeviceCaps(OBJGPU *pGpu, struct KernelBus *pKernelBus, #endif //__nvoc_kern_bus_h_disabled void kbusDestroyMailbox_IMPL(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, NvU32 peerIdx); + #ifdef __nvoc_kern_bus_h_disabled static inline void kbusDestroyMailbox(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, NvU32 peerIdx) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -2083,8 +2209,10 @@ static inline void kbusDestroyMailbox(OBJGPU *pGpu0, struct KernelBus *pKernelBu #endif //__nvoc_kern_bus_h_disabled RmPhysAddr kbusSetupPeerBarAccess_IMPL(OBJGPU *pGpu0, OBJGPU *pGpu1, RmPhysAddr arg0, NvU64 arg1, PMEMORY_DESCRIPTOR *arg2); + #define kbusSetupPeerBarAccess(pGpu0, pGpu1, arg0, arg1, arg2) kbusSetupPeerBarAccess_IMPL(pGpu0, pGpu1, arg0, arg1, arg2) NV_STATUS kbusSendSysmembar_IMPL(OBJGPU *pGpu, struct KernelBus *pKernelBus); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusSendSysmembar(OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -2095,6 +2223,7 @@ static inline NV_STATUS kbusSendSysmembar(OBJGPU *pGpu, struct KernelBus *pKerne #endif //__nvoc_kern_bus_h_disabled NV_STATUS kbusSendBusInfo_IMPL(OBJGPU *pGpu, struct KernelBus *pKernelBus, NV2080_CTRL_BUS_INFO *pBusInfo); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusSendBusInfo(OBJGPU *pGpu, struct KernelBus *pKernelBus, NV2080_CTRL_BUS_INFO *pBusInfo) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -2105,6 +2234,7 @@ static inline NV_STATUS kbusSendBusInfo(OBJGPU *pGpu, struct KernelBus *pKernelB #endif //__nvoc_kern_bus_h_disabled NvU64 kbusGetPciBarSize_IMPL(struct KernelBus *pKernelBus, NvU32 index); + #ifdef __nvoc_kern_bus_h_disabled static inline NvU64 kbusGetPciBarSize(struct KernelBus *pKernelBus, NvU32 index) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -2115,6 +2245,7 @@ static inline NvU64 kbusGetPciBarSize(struct KernelBus *pKernelBus, NvU32 index) #endif //__nvoc_kern_bus_h_disabled RmPhysAddr kbusGetPciBarOffset_IMPL(struct KernelBus *pKernelBus, NvU32 index); + #ifdef __nvoc_kern_bus_h_disabled static inline RmPhysAddr kbusGetPciBarOffset(struct KernelBus *pKernelBus, NvU32 index) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -2127,6 +2258,7 @@ static inline RmPhysAddr kbusGetPciBarOffset(struct KernelBus *pKernelBus, NvU32 #endif //__nvoc_kern_bus_h_disabled NV_STATUS kbusIsGpuP2pAlive_IMPL(OBJGPU *pGpu, struct KernelBus *pKernelBus); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusIsGpuP2pAlive(OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -2137,6 +2269,7 @@ static inline NV_STATUS kbusIsGpuP2pAlive(OBJGPU *pGpu, struct KernelBus *pKerne #endif //__nvoc_kern_bus_h_disabled void kbusDetermineBar1Force64KBMapping_IMPL(struct KernelBus *pKernelBus); + #ifdef __nvoc_kern_bus_h_disabled static inline void kbusDetermineBar1Force64KBMapping(struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -2146,6 +2279,7 @@ static inline void kbusDetermineBar1Force64KBMapping(struct KernelBus *pKernelBu #endif //__nvoc_kern_bus_h_disabled void kbusDetermineBar1ApertureLength_IMPL(struct KernelBus *pKernelBus, NvU32 gfid); + #ifdef __nvoc_kern_bus_h_disabled static inline void kbusDetermineBar1ApertureLength(struct KernelBus *pKernelBus, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -2155,6 +2289,7 @@ static inline void kbusDetermineBar1ApertureLength(struct KernelBus *pKernelBus, #endif //__nvoc_kern_bus_h_disabled NV_STATUS kbusMapFbApertureByHandle_IMPL(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle hClient, NvHandle hMemory, NvU64 offset, NvU64 size, NvU64 *pBar1Va); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusMapFbApertureByHandle(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle hClient, NvHandle hMemory, NvU64 offset, NvU64 size, NvU64 *pBar1Va) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -2165,6 +2300,7 @@ static inline NV_STATUS kbusMapFbApertureByHandle(OBJGPU *pGpu, struct KernelBus #endif //__nvoc_kern_bus_h_disabled NV_STATUS kbusUnmapFbApertureByHandle_IMPL(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle hClient, NvHandle hMemory, NvU64 bar1Va); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusUnmapFbApertureByHandle(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle hClient, NvHandle hMemory, NvU64 bar1Va) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -2175,6 +2311,7 @@ static inline NV_STATUS kbusUnmapFbApertureByHandle(OBJGPU *pGpu, struct KernelB #endif //__nvoc_kern_bus_h_disabled NV_STATUS kbusGetBar1VARangeForClient_IMPL(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle arg0, struct NV_RANGE *arg1); + #ifdef __nvoc_kern_bus_h_disabled static inline NV_STATUS kbusGetBar1VARangeForClient(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle arg0, struct NV_RANGE *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -2185,6 +2322,7 @@ static inline NV_STATUS kbusGetBar1VARangeForClient(OBJGPU *pGpu, struct KernelB #endif //__nvoc_kern_bus_h_disabled NvU32 kbusGetFlushAperture_IMPL(struct KernelBus *pKernelBus, NV_ADDRESS_SPACE addrSpace); + #ifdef __nvoc_kern_bus_h_disabled static inline NvU32 kbusGetFlushAperture(struct KernelBus *pKernelBus, NV_ADDRESS_SPACE addrSpace) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); @@ -2195,6 +2333,7 @@ static inline NvU32 kbusGetFlushAperture(struct KernelBus *pKernelBus, NV_ADDRES #endif //__nvoc_kern_bus_h_disabled NvU8 *kbusCpuOffsetInBar2WindowGet_IMPL(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc); + #ifdef __nvoc_kern_bus_h_disabled static inline NvU8 *kbusCpuOffsetInBar2WindowGet(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); diff --git a/src/nvidia/generated/g_kern_disp_nvoc.c b/src/nvidia/generated/g_kern_disp_nvoc.c index 0fb018501..47ff2479f 100644 --- a/src/nvidia/generated/g_kern_disp_nvoc.c +++ b/src/nvidia/generated/g_kern_disp_nvoc.c @@ -99,7 +99,7 @@ static NV_STATUS __nvoc_thunk_KernelDisplay_engstateStateUnload(OBJGPU *pGpu, st return kdispStateUnload(pGpu, (struct KernelDisplay *)(((unsigned char *)pKernelDisplay) - __nvoc_rtti_KernelDisplay_OBJENGSTATE.offset), flags); } -static void __nvoc_thunk_KernelDisplay_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pKernelDisplay, IntrServiceRecord pRecords[155]) { +static void __nvoc_thunk_KernelDisplay_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pKernelDisplay, IntrServiceRecord pRecords[163]) { kdispRegisterIntrService(pGpu, (struct KernelDisplay *)(((unsigned char *)pKernelDisplay) - __nvoc_rtti_KernelDisplay_IntrService.offset), pRecords); } @@ -203,28 +203,22 @@ void __nvoc_init_dataField_KernelDisplay(KernelDisplay *pThis, RmHalspecOwner *p PORT_UNREFERENCED_VARIABLE(dispIpHal_HalVarIdx); // NVOC Property Hal field -- PDB_PROP_KDISP_IS_MISSING - if (0) - { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { pThis->setProperty(pThis, PDB_PROP_KDISP_IS_MISSING, ((NvBool)(0 != 0))); } // NVOC Property Hal field -- PDB_PROP_KDISP_IMP_ENABLE - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_KDISP_IMP_ENABLE, ((NvBool)(0 == 0))); } - // default - else - { - pThis->setProperty(pThis, PDB_PROP_KDISP_IMP_ENABLE, ((NvBool)(0 != 0))); - } pThis->pStaticInfo = ((void *)0); pThis->bWarPurgeSatellitesOnCoreFree = ((NvBool)(0 != 0)); + + pThis->bExtdevIntrSupported = ((NvBool)(0 != 0)); } NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); @@ -279,71 +273,40 @@ static void __nvoc_init_funcTable_KernelDisplay_1(KernelDisplay *pThis, RmHalspe // Hal function -- kdispServiceInterrupt if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - pThis->__kdispServiceInterrupt__ = &kdispServiceInterrupt_d3ef2b; - } - else if (0) - { + pThis->__kdispServiceInterrupt__ = &kdispServiceInterrupt_cd2c9e; } // Hal function -- kdispSelectClass - if (0) - { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ { pThis->__kdispSelectClass__ = &kdispSelectClass_46f6a7; } - else if (0) - { - } else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ { pThis->__kdispSelectClass__ = &kdispSelectClass_v03_00_KERNEL; } } - else if (0) - { -#if 0 - if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ - { - pThis->__kdispSelectClass__ = &kdispSelectClass_46f6a7; - } - else if (0) - { - } - else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ - { - pThis->__kdispSelectClass__ = &kdispSelectClass_v03_00_KERNEL; - } -#endif - } // Hal function -- kdispGetChannelNum if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ { pThis->__kdispGetChannelNum__ = &kdispGetChannelNum_46f6a7; } - else if (0) - { - } - else if (0) - { - } else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ { pThis->__kdispGetChannelNum__ = &kdispGetChannelNum_v03_00; } // Hal function -- kdispGetDisplayCapsBaseAndSize - if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ )) + if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ )) { pThis->__kdispGetDisplayCapsBaseAndSize__ = &kdispGetDisplayCapsBaseAndSize_b3696a; } else if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* DispIpHal: DISPv0400 */ ) || ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000800UL) )) /* DispIpHal: DISPv0401 */ ) || - ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00700000UL) )) /* ChipHal: AD102 | AD103 | AD104 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004000UL) )) /* DispIpHal: DISPv0404 */ )) + ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004000UL) )) /* DispIpHal: DISPv0404 */ )) { pThis->__kdispGetDisplayCapsBaseAndSize__ = &kdispGetDisplayCapsBaseAndSize_v03_00; } @@ -353,9 +316,6 @@ static void __nvoc_init_funcTable_KernelDisplay_1(KernelDisplay *pThis, RmHalspe { pThis->__kdispGetDisplaySfUserBaseAndSize__ = &kdispGetDisplaySfUserBaseAndSize_b3696a; } - else if (0) - { - } else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ { pThis->__kdispGetDisplaySfUserBaseAndSize__ = &kdispGetDisplaySfUserBaseAndSize_v03_00; @@ -366,29 +326,67 @@ static void __nvoc_init_funcTable_KernelDisplay_1(KernelDisplay *pThis, RmHalspe { pThis->__kdispGetDisplayChannelUserBaseAndSize__ = &kdispGetDisplayChannelUserBaseAndSize_46f6a7; } - else if (0) - { - } - else if (0) - { - } else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ { pThis->__kdispGetDisplayChannelUserBaseAndSize__ = &kdispGetDisplayChannelUserBaseAndSize_v03_00; } // Hal function -- kdispGetVgaWorkspaceBase - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kdispGetVgaWorkspaceBase__ = &kdispGetVgaWorkspaceBase_v04_00; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kdispGetVgaWorkspaceBase__ = &kdispGetVgaWorkspaceBase_491d52; } - // default - else + + // Hal function -- kdispReadRgLineCountAndFrameCount + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + { + pThis->__kdispReadRgLineCountAndFrameCount__ = &kdispReadRgLineCountAndFrameCount_v03_00_KERNEL; + } + // default + else + { + pThis->__kdispReadRgLineCountAndFrameCount__ = &kdispReadRgLineCountAndFrameCount_46f6a7; + } + } + + // Hal function -- kdispRestoreOriginalLsrMinTime + if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* DispIpHal: DISPv0400 */ ) || + ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000800UL) )) /* DispIpHal: DISPv0401 */ ) || + ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004000UL) )) /* DispIpHal: DISPv0404 */ )) + { + pThis->__kdispRestoreOriginalLsrMinTime__ = &kdispRestoreOriginalLsrMinTime_v03_00; + } + else if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ )) + { + pThis->__kdispRestoreOriginalLsrMinTime__ = &kdispRestoreOriginalLsrMinTime_b3696a; + } + + // Hal function -- kdispComputeLsrMinTimeValue + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + { + pThis->__kdispComputeLsrMinTimeValue__ = &kdispComputeLsrMinTimeValue_v02_07; + } + else if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ + { + pThis->__kdispComputeLsrMinTimeValue__ = &kdispComputeLsrMinTimeValue_56cd7a; + } + + // Hal function -- kdispSetSwapBarrierLsrMinTime + if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* DispIpHal: DISPv0400 */ ) || + ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00000800UL) )) /* DispIpHal: DISPv0401 */ ) || + ((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004000UL) )) /* DispIpHal: DISPv0404 */ )) + { + pThis->__kdispSetSwapBarrierLsrMinTime__ = &kdispSetSwapBarrierLsrMinTime_v03_00; + } + else if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ && (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00008000UL) )) /* DispIpHal: DISPv0000 */ )) + { + pThis->__kdispSetSwapBarrierLsrMinTime__ = &kdispSetSwapBarrierLsrMinTime_b3696a; } pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelDisplay_engstateConstructEngine; diff --git a/src/nvidia/generated/g_kern_disp_nvoc.h b/src/nvidia/generated/g_kern_disp_nvoc.h index fa6d57289..41fb8c2d0 100644 --- a/src/nvidia/generated/g_kern_disp_nvoc.h +++ b/src/nvidia/generated/g_kern_disp_nvoc.h @@ -114,6 +114,10 @@ struct KernelDisplay { void (*__kdispGetDisplaySfUserBaseAndSize__)(OBJGPU *, struct KernelDisplay *, NvU32 *, NvU32 *); NV_STATUS (*__kdispGetDisplayChannelUserBaseAndSize__)(OBJGPU *, struct KernelDisplay *, DISPCHNCLASS, NvU32, NvU32 *, NvU32 *); NvBool (*__kdispGetVgaWorkspaceBase__)(OBJGPU *, struct KernelDisplay *, NvU64 *); + NV_STATUS (*__kdispReadRgLineCountAndFrameCount__)(OBJGPU *, struct KernelDisplay *, NvU32, NvU32 *, NvU32 *); + void (*__kdispRestoreOriginalLsrMinTime__)(OBJGPU *, struct KernelDisplay *, NvU32, NvU32); + NV_STATUS (*__kdispComputeLsrMinTimeValue__)(OBJGPU *, struct KernelDisplay *, NvU32, NvU32, NvU32 *); + void (*__kdispSetSwapBarrierLsrMinTime__)(OBJGPU *, struct KernelDisplay *, NvU32, NvU32 *, NvU32); NV_STATUS (*__kdispReconcileTunableState__)(POBJGPU, struct KernelDisplay *, void *); NV_STATUS (*__kdispServiceNotificationInterrupt__)(OBJGPU *, struct KernelDisplay *, IntrServiceServiceNotificationInterruptArguments *); NV_STATUS (*__kdispStatePreLoad__)(POBJGPU, struct KernelDisplay *, NvU32); @@ -137,6 +141,8 @@ struct KernelDisplay { NvBool bWarPurgeSatellitesOnCoreFree; struct RgLineCallback *rgLineCallbackPerHead[4][2]; NvU32 isrVblankHeads; + NvBool bExtdevIntrSupported; + NvU32 numHeads; }; #ifndef __NVOC_CLASS_KernelDisplay_TYPEDEF__ @@ -192,6 +198,14 @@ NV_STATUS __nvoc_objCreate_KernelDisplay(KernelDisplay**, Dynamic*, NvU32); #define kdispGetDisplayChannelUserBaseAndSize_HAL(pGpu, pKernelDisplay, channelClass, channelInstance, pOffset, pSize) kdispGetDisplayChannelUserBaseAndSize_DISPATCH(pGpu, pKernelDisplay, channelClass, channelInstance, pOffset, pSize) #define kdispGetVgaWorkspaceBase(pGpu, pKernelDisplay, pOffset) kdispGetVgaWorkspaceBase_DISPATCH(pGpu, pKernelDisplay, pOffset) #define kdispGetVgaWorkspaceBase_HAL(pGpu, pKernelDisplay, pOffset) kdispGetVgaWorkspaceBase_DISPATCH(pGpu, pKernelDisplay, pOffset) +#define kdispReadRgLineCountAndFrameCount(pGpu, pKernelDisplay, head, pLineCount, pFrameCount) kdispReadRgLineCountAndFrameCount_DISPATCH(pGpu, pKernelDisplay, head, pLineCount, pFrameCount) +#define kdispReadRgLineCountAndFrameCount_HAL(pGpu, pKernelDisplay, head, pLineCount, pFrameCount) kdispReadRgLineCountAndFrameCount_DISPATCH(pGpu, pKernelDisplay, head, pLineCount, pFrameCount) +#define kdispRestoreOriginalLsrMinTime(pGpu, pKernelDisplay, head, origLsrMinTime) kdispRestoreOriginalLsrMinTime_DISPATCH(pGpu, pKernelDisplay, head, origLsrMinTime) +#define kdispRestoreOriginalLsrMinTime_HAL(pGpu, pKernelDisplay, head, origLsrMinTime) kdispRestoreOriginalLsrMinTime_DISPATCH(pGpu, pKernelDisplay, head, origLsrMinTime) +#define kdispComputeLsrMinTimeValue(pGpu, pKernelDisplay, head, swapRdyHiLsrMinTime, pComputedLsrMinTime) kdispComputeLsrMinTimeValue_DISPATCH(pGpu, pKernelDisplay, head, swapRdyHiLsrMinTime, pComputedLsrMinTime) +#define kdispComputeLsrMinTimeValue_HAL(pGpu, pKernelDisplay, head, swapRdyHiLsrMinTime, pComputedLsrMinTime) kdispComputeLsrMinTimeValue_DISPATCH(pGpu, pKernelDisplay, head, swapRdyHiLsrMinTime, pComputedLsrMinTime) +#define kdispSetSwapBarrierLsrMinTime(pGpu, pKernelDisplay, head, pOrigLsrMinTime, newLsrMinTime) kdispSetSwapBarrierLsrMinTime_DISPATCH(pGpu, pKernelDisplay, head, pOrigLsrMinTime, newLsrMinTime) +#define kdispSetSwapBarrierLsrMinTime_HAL(pGpu, pKernelDisplay, head, pOrigLsrMinTime, newLsrMinTime) kdispSetSwapBarrierLsrMinTime_DISPATCH(pGpu, pKernelDisplay, head, pOrigLsrMinTime, newLsrMinTime) #define kdispReconcileTunableState(pGpu, pEngstate, pTunableState) kdispReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kdispServiceNotificationInterrupt(pGpu, pIntrService, pParams) kdispServiceNotificationInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define kdispStatePreLoad(pGpu, pEngstate, arg0) kdispStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) @@ -210,6 +224,7 @@ NV_STATUS __nvoc_objCreate_KernelDisplay(KernelDisplay**, Dynamic*, NvU32); #define kdispIsPresent(pGpu, pEngstate) kdispIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS kdispConstructInstMem_IMPL(struct KernelDisplay *pKernelDisplay); + #ifdef __nvoc_kern_disp_h_disabled static inline NV_STATUS kdispConstructInstMem(struct KernelDisplay *pKernelDisplay) { NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); @@ -223,6 +238,7 @@ static inline NV_STATUS kdispConstructInstMem(struct KernelDisplay *pKernelDispl void kdispDestructInstMem_IMPL(struct KernelDisplay *pKernelDisplay); + #ifdef __nvoc_kern_disp_h_disabled static inline void kdispDestructInstMem(struct KernelDisplay *pKernelDisplay) { NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); @@ -237,6 +253,7 @@ static inline NvS32 kdispGetBaseOffset_4a4dee(OBJGPU *pGpu, struct KernelDisplay return 0; } + #ifdef __nvoc_kern_disp_h_disabled static inline NvS32 kdispGetBaseOffset(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay) { NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); @@ -252,6 +269,7 @@ static inline NV_STATUS kdispImportImpData_56cd7a(struct KernelDisplay *pKernelD return NV_OK; } + #ifdef __nvoc_kern_disp_h_disabled static inline NV_STATUS kdispImportImpData(struct KernelDisplay *pKernelDisplay) { NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); @@ -267,6 +285,7 @@ static inline NV_STATUS kdispArbAndAllocDisplayBandwidth_46f6a7(OBJGPU *pGpu, st return NV_ERR_NOT_SUPPORTED; } + #ifdef __nvoc_kern_disp_h_disabled static inline NV_STATUS kdispArbAndAllocDisplayBandwidth(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, enum DISPLAY_ICC_BW_CLIENT iccBwClient, NvU32 minRequiredIsoBandwidthKBPS, NvU32 minRequiredFloorBandwidthKBPS) { NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); @@ -280,6 +299,7 @@ static inline NV_STATUS kdispArbAndAllocDisplayBandwidth(OBJGPU *pGpu, struct Ke NV_STATUS kdispSetPushBufferParamsToPhysical_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, struct DispChannel *pDispChannel, NvHandle hObjectBuffer, struct ContextDma *pBufferContextDma, NvU32 hClass, NvU32 channelInstance, DISPCHNCLASS internalDispChnClass); + #ifdef __nvoc_kern_disp_h_disabled static inline NV_STATUS kdispSetPushBufferParamsToPhysical(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, struct DispChannel *pDispChannel, NvHandle hObjectBuffer, struct ContextDma *pBufferContextDma, NvU32 hClass, NvU32 channelInstance, DISPCHNCLASS internalDispChnClass) { NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); @@ -295,6 +315,7 @@ static inline NV_STATUS kdispAcquireDispChannelHw_56cd7a(struct KernelDisplay *p return NV_OK; } + #ifdef __nvoc_kern_disp_h_disabled static inline NV_STATUS kdispAcquireDispChannelHw(struct KernelDisplay *pKernelDisplay, struct DispChannel *pDispChannel, NvU32 channelInstance, NvHandle hObjectBuffer, NvU32 initialGetPutOffset, NvBool allowGrabWithinSameClient, NvBool connectPbAtGrab) { NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); @@ -310,6 +331,7 @@ static inline NV_STATUS kdispReleaseDispChannelHw_56cd7a(struct KernelDisplay *p return NV_OK; } + #ifdef __nvoc_kern_disp_h_disabled static inline NV_STATUS kdispReleaseDispChannelHw(struct KernelDisplay *pKernelDisplay, struct DispChannel *pDispChannel) { NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); @@ -323,6 +345,7 @@ static inline NV_STATUS kdispReleaseDispChannelHw(struct KernelDisplay *pKernelD NV_STATUS kdispMapDispChannel_IMPL(struct KernelDisplay *pKernelDisplay, struct DispChannel *pDispChannel); + #ifdef __nvoc_kern_disp_h_disabled static inline NV_STATUS kdispMapDispChannel(struct KernelDisplay *pKernelDisplay, struct DispChannel *pDispChannel) { NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); @@ -336,6 +359,7 @@ static inline NV_STATUS kdispMapDispChannel(struct KernelDisplay *pKernelDisplay void kdispUnbindUnmapDispChannel_IMPL(struct KernelDisplay *pKernelDisplay, struct DispChannel *pDispChannel); + #ifdef __nvoc_kern_disp_h_disabled static inline void kdispUnbindUnmapDispChannel(struct KernelDisplay *pKernelDisplay, struct DispChannel *pDispChannel) { NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); @@ -348,6 +372,7 @@ static inline void kdispUnbindUnmapDispChannel(struct KernelDisplay *pKernelDisp NV_STATUS kdispRegisterRgLineCallback_IMPL(struct KernelDisplay *pKernelDisplay, struct RgLineCallback *pRgLineCallback, NvU32 head, NvU32 rgIntrLine, NvBool bEnable); + #ifdef __nvoc_kern_disp_h_disabled static inline NV_STATUS kdispRegisterRgLineCallback(struct KernelDisplay *pKernelDisplay, struct RgLineCallback *pRgLineCallback, NvU32 head, NvU32 rgIntrLine, NvBool bEnable) { NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); @@ -361,6 +386,7 @@ static inline NV_STATUS kdispRegisterRgLineCallback(struct KernelDisplay *pKerne void kdispInvokeRgLineCallback_KERNEL(struct KernelDisplay *pKernelDisplay, NvU32 head, NvU32 rgIntrLine, NvBool bIsIrqlIsr); + #ifdef __nvoc_kern_disp_h_disabled static inline void kdispInvokeRgLineCallback(struct KernelDisplay *pKernelDisplay, NvU32 head, NvU32 rgIntrLine, NvBool bIsIrqlIsr) { NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); @@ -373,6 +399,7 @@ static inline void kdispInvokeRgLineCallback(struct KernelDisplay *pKernelDispla void kdispServiceVblank_KERNEL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); + #ifdef __nvoc_kern_disp_h_disabled static inline void kdispServiceVblank(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); @@ -385,6 +412,7 @@ static inline void kdispServiceVblank(OBJGPU *pGpu, struct KernelDisplay *pKerne NvU32 kdispReadPendingVblank_KERNEL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, struct THREAD_STATE_NODE *arg0); + #ifdef __nvoc_kern_disp_h_disabled static inline NvU32 kdispReadPendingVblank(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, struct THREAD_STATE_NODE *arg0) { NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); @@ -400,6 +428,7 @@ static inline void kdispInvokeDisplayModesetCallback_b3696a(struct KernelDisplay return; } + #ifdef __nvoc_kern_disp_h_disabled static inline void kdispInvokeDisplayModesetCallback(struct KernelDisplay *pKernelDisplay, NvBool bModesetStart, NvU32 minRequiredIsoBandwidthKBPS, NvU32 minRequiredFloorBandwidthKBPS) { NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); @@ -410,6 +439,37 @@ static inline void kdispInvokeDisplayModesetCallback(struct KernelDisplay *pKern #define kdispInvokeDisplayModesetCallback_HAL(pKernelDisplay, bModesetStart, minRequiredIsoBandwidthKBPS, minRequiredFloorBandwidthKBPS) kdispInvokeDisplayModesetCallback(pKernelDisplay, bModesetStart, minRequiredIsoBandwidthKBPS, minRequiredFloorBandwidthKBPS) +static inline NV_STATUS kdispDsmMxmMxcbExecuteAcpi_92bfc3(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, void *pInOutData, NvU16 *outDataSize) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + + +#ifdef __nvoc_kern_disp_h_disabled +static inline NV_STATUS kdispDsmMxmMxcbExecuteAcpi(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, void *pInOutData, NvU16 *outDataSize) { + NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kern_disp_h_disabled +#define kdispDsmMxmMxcbExecuteAcpi(pGpu, pKernelDisplay, pInOutData, outDataSize) kdispDsmMxmMxcbExecuteAcpi_92bfc3(pGpu, pKernelDisplay, pInOutData, outDataSize) +#endif //__nvoc_kern_disp_h_disabled + +#define kdispDsmMxmMxcbExecuteAcpi_HAL(pGpu, pKernelDisplay, pInOutData, outDataSize) kdispDsmMxmMxcbExecuteAcpi(pGpu, pKernelDisplay, pInOutData, outDataSize) + +NV_STATUS kdispInitBrightcStateLoad_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay); + + +#ifdef __nvoc_kern_disp_h_disabled +static inline NV_STATUS kdispInitBrightcStateLoad(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay) { + NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kern_disp_h_disabled +#define kdispInitBrightcStateLoad(pGpu, pKernelDisplay) kdispInitBrightcStateLoad_IMPL(pGpu, pKernelDisplay) +#endif //__nvoc_kern_disp_h_disabled + +#define kdispInitBrightcStateLoad_HAL(pGpu, pKernelDisplay) kdispInitBrightcStateLoad(pGpu, pKernelDisplay) + NV_STATUS kdispConstructEngine_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, ENGDESCRIPTOR engDesc); static inline NV_STATUS kdispConstructEngine_DISPATCH(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, ENGDESCRIPTOR engDesc) { @@ -446,14 +506,14 @@ static inline NV_STATUS kdispStateUnload_DISPATCH(OBJGPU *pGpu, struct KernelDis return pKernelDisplay->__kdispStateUnload__(pGpu, pKernelDisplay, flags); } -void kdispRegisterIntrService_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, IntrServiceRecord pRecords[155]); +void kdispRegisterIntrService_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, IntrServiceRecord pRecords[163]); -static inline void kdispRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, IntrServiceRecord pRecords[155]) { +static inline void kdispRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, IntrServiceRecord pRecords[163]) { pKernelDisplay->__kdispRegisterIntrService__(pGpu, pKernelDisplay, pRecords); } -static inline NvU32 kdispServiceInterrupt_d3ef2b(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, IntrServiceServiceInterruptArguments *pParams) { - kdispServiceVblank(pGpu, pKernelDisplay, 0, ((2) | (16)), ((void *)0)); +static inline NvU32 kdispServiceInterrupt_cd2c9e(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, IntrServiceServiceInterruptArguments *pParams) { + kdispServiceVblank(pGpu, pKernelDisplay, 0, ((2) | (4)), ((void *)0)); return NV_OK; } @@ -461,19 +521,12 @@ static inline NvU32 kdispServiceInterrupt_DISPATCH(OBJGPU *pGpu, struct KernelDi return pKernelDisplay->__kdispServiceInterrupt__(pGpu, pKernelDisplay, pParams); } -static inline NV_STATUS kdispSelectClass_ef1e3d(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 swClass) { - NV_ASSERT_FAILED_PRECOMP("Cannot call kdispSelectClass on ucode"); - return NV_ERR_NOT_SUPPORTED; -} - static inline NV_STATUS kdispSelectClass_46f6a7(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 swClass) { return NV_ERR_NOT_SUPPORTED; } NV_STATUS kdispSelectClass_v03_00_KERNEL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 swClass); -NV_STATUS kdispSelectClass_v03_00_KERNEL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 swClass); - static inline NV_STATUS kdispSelectClass_DISPATCH(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 swClass) { return pKernelDisplay->__kdispSelectClass__(pGpu, pKernelDisplay, swClass); } @@ -524,15 +577,52 @@ static inline NvBool kdispGetVgaWorkspaceBase_491d52(OBJGPU *pGpu, struct Kernel return ((NvBool)(0 != 0)); } -static inline NvBool kdispGetVgaWorkspaceBase_ceaee8(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU64 *pOffset) { - NV_ASSERT_PRECOMP(0); - return ((NvBool)(0 != 0)); -} - static inline NvBool kdispGetVgaWorkspaceBase_DISPATCH(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU64 *pOffset) { return pKernelDisplay->__kdispGetVgaWorkspaceBase__(pGpu, pKernelDisplay, pOffset); } +NV_STATUS kdispReadRgLineCountAndFrameCount_v03_00_PHYSICAL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 head, NvU32 *pLineCount, NvU32 *pFrameCount); + +static inline NV_STATUS kdispReadRgLineCountAndFrameCount_46f6a7(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 head, NvU32 *pLineCount, NvU32 *pFrameCount) { + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS kdispReadRgLineCountAndFrameCount_v03_00_KERNEL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 head, NvU32 *pLineCount, NvU32 *pFrameCount); + +static inline NV_STATUS kdispReadRgLineCountAndFrameCount_DISPATCH(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 head, NvU32 *pLineCount, NvU32 *pFrameCount) { + return pKernelDisplay->__kdispReadRgLineCountAndFrameCount__(pGpu, pKernelDisplay, head, pLineCount, pFrameCount); +} + +void kdispRestoreOriginalLsrMinTime_v03_00(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 head, NvU32 origLsrMinTime); + +static inline void kdispRestoreOriginalLsrMinTime_b3696a(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 head, NvU32 origLsrMinTime) { + return; +} + +static inline void kdispRestoreOriginalLsrMinTime_DISPATCH(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 head, NvU32 origLsrMinTime) { + pKernelDisplay->__kdispRestoreOriginalLsrMinTime__(pGpu, pKernelDisplay, head, origLsrMinTime); +} + +NV_STATUS kdispComputeLsrMinTimeValue_v02_07(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 head, NvU32 swapRdyHiLsrMinTime, NvU32 *pComputedLsrMinTime); + +static inline NV_STATUS kdispComputeLsrMinTimeValue_56cd7a(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 head, NvU32 swapRdyHiLsrMinTime, NvU32 *pComputedLsrMinTime) { + return NV_OK; +} + +static inline NV_STATUS kdispComputeLsrMinTimeValue_DISPATCH(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 head, NvU32 swapRdyHiLsrMinTime, NvU32 *pComputedLsrMinTime) { + return pKernelDisplay->__kdispComputeLsrMinTimeValue__(pGpu, pKernelDisplay, head, swapRdyHiLsrMinTime, pComputedLsrMinTime); +} + +void kdispSetSwapBarrierLsrMinTime_v03_00(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 head, NvU32 *pOrigLsrMinTime, NvU32 newLsrMinTime); + +static inline void kdispSetSwapBarrierLsrMinTime_b3696a(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 head, NvU32 *pOrigLsrMinTime, NvU32 newLsrMinTime) { + return; +} + +static inline void kdispSetSwapBarrierLsrMinTime_DISPATCH(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 head, NvU32 *pOrigLsrMinTime, NvU32 newLsrMinTime) { + pKernelDisplay->__kdispSetSwapBarrierLsrMinTime__(pGpu, pKernelDisplay, head, pOrigLsrMinTime, newLsrMinTime); +} + static inline NV_STATUS kdispReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelDisplay *pEngstate, void *pTunableState) { return pEngstate->__kdispReconcileTunableState__(pGpu, pEngstate, pTunableState); } @@ -598,8 +688,10 @@ static inline NvBool kdispIsPresent_DISPATCH(POBJGPU pGpu, struct KernelDisplay } void kdispDestruct_IMPL(struct KernelDisplay *pKernelDisplay); + #define __nvoc_kdispDestruct(pKernelDisplay) kdispDestruct_IMPL(pKernelDisplay) NV_STATUS kdispConstructKhead_IMPL(struct KernelDisplay *pKernelDisplay); + #ifdef __nvoc_kern_disp_h_disabled static inline NV_STATUS kdispConstructKhead(struct KernelDisplay *pKernelDisplay) { NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); @@ -610,6 +702,7 @@ static inline NV_STATUS kdispConstructKhead(struct KernelDisplay *pKernelDisplay #endif //__nvoc_kern_disp_h_disabled void kdispDestructKhead_IMPL(struct KernelDisplay *pKernelDisplay); + #ifdef __nvoc_kern_disp_h_disabled static inline void kdispDestructKhead(struct KernelDisplay *pKernelDisplay) { NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); @@ -619,6 +712,7 @@ static inline void kdispDestructKhead(struct KernelDisplay *pKernelDisplay) { #endif //__nvoc_kern_disp_h_disabled NV_STATUS kdispGetIntChnClsForHwCls_IMPL(struct KernelDisplay *pKernelDisplay, NvU32 hwClass, DISPCHNCLASS *pDispChnClass); + #ifdef __nvoc_kern_disp_h_disabled static inline NV_STATUS kdispGetIntChnClsForHwCls(struct KernelDisplay *pKernelDisplay, NvU32 hwClass, DISPCHNCLASS *pDispChnClass) { NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); @@ -629,6 +723,7 @@ static inline NV_STATUS kdispGetIntChnClsForHwCls(struct KernelDisplay *pKernelD #endif //__nvoc_kern_disp_h_disabled void kdispNotifyEvent_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 notifyIndex, void *pNotifyParams, NvU32 notifyParamsSize, NvV32 info32, NvV16 info16); + #ifdef __nvoc_kern_disp_h_disabled static inline void kdispNotifyEvent(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 notifyIndex, void *pNotifyParams, NvU32 notifyParamsSize, NvV32 info32, NvV16 info16) { NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); @@ -638,6 +733,7 @@ static inline void kdispNotifyEvent(OBJGPU *pGpu, struct KernelDisplay *pKernelD #endif //__nvoc_kern_disp_h_disabled void kdispSetWarPurgeSatellitesOnCoreFree_IMPL(struct KernelDisplay *pKernelDisplay, NvBool value); + #ifdef __nvoc_kern_disp_h_disabled static inline void kdispSetWarPurgeSatellitesOnCoreFree(struct KernelDisplay *pKernelDisplay, NvBool value) { NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); @@ -649,6 +745,18 @@ static inline void kdispSetWarPurgeSatellitesOnCoreFree(struct KernelDisplay *pK #undef PRIVATE_FIELD +void +dispdeviceFillVgaSavedDisplayState( OBJGPU *pGpu, + NvU64 vgaAddr, + NvU8 vgaMemType, + NvBool vgaValid, + NvU64 workspaceAddr, + NvU8 workspaceMemType, + NvBool workspaceValid, + NvBool baseValid, + NvBool workspaceBaseValid +); + static NV_INLINE struct KernelHead* kdispGetHead ( @@ -663,6 +771,20 @@ kdispGetHead return pKernelDisplay->pKernelHead[head]; } + +static NV_INLINE NvU32 +kdispGetNumHeads(struct KernelDisplay *pKernelDisplay) +{ + NV_ASSERT(pKernelDisplay != NULL); + return pKernelDisplay->numHeads; +} + +static NV_INLINE NvU32 +kdispGetIsPrimaryVga(struct KernelDisplay *pKernelDisplay) +{ + NV_ASSERT(pKernelDisplay->pStaticInfo != NULL); + return pKernelDisplay->pStaticInfo->bPrimaryVga; +} #endif // KERN_DISP_H #ifdef __cplusplus diff --git a/src/nvidia/generated/g_kern_fsp_nvoc.c b/src/nvidia/generated/g_kern_fsp_nvoc.c index 84c61e6b5..111578c8b 100644 --- a/src/nvidia/generated/g_kern_fsp_nvoc.c +++ b/src/nvidia/generated/g_kern_fsp_nvoc.c @@ -167,7 +167,7 @@ void __nvoc_init_dataField_KernelFsp(KernelFsp *pThis, RmHalspecOwner *pRmhalspe PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); // NVOC Property Hal field -- PDB_PROP_KFSP_IS_MISSING - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->setProperty(pThis, PDB_PROP_KFSP_IS_MISSING, ((NvBool)(0 != 0))); } @@ -219,7 +219,7 @@ static void __nvoc_init_funcTable_KernelFsp_1(KernelFsp *pThis, RmHalspecOwner * pThis->__kfspPollForResponse__ = &kfspPollForResponse_IMPL; // Hal function -- kfspGspFmcIsEnforced - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kfspGspFmcIsEnforced__ = &kfspGspFmcIsEnforced_GH100; } @@ -230,197 +230,208 @@ static void __nvoc_init_funcTable_KernelFsp_1(KernelFsp *pThis, RmHalspecOwner * } // Hal function -- kfspSendBootCommands - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kfspSendBootCommands__ = &kfspSendBootCommands_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kfspSendBootCommands__ = &kfspSendBootCommands_ac1694; } // Hal function -- kfspWaitForSecureBoot - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kfspWaitForSecureBoot__ = &kfspWaitForSecureBoot_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kfspWaitForSecureBoot__ = &kfspWaitForSecureBoot_395e98; } // Hal function -- kfspGetRmChannelSize - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kfspGetRmChannelSize__ = &kfspGetRmChannelSize_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kfspGetRmChannelSize__ = &kfspGetRmChannelSize_b2b553; } // Hal function -- kfspConfigEmemc - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kfspConfigEmemc__ = &kfspConfigEmemc_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kfspConfigEmemc__ = &kfspConfigEmemc_395e98; } // Hal function -- kfspUpdateQueueHeadTail - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kfspUpdateQueueHeadTail__ = &kfspUpdateQueueHeadTail_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kfspUpdateQueueHeadTail__ = &kfspUpdateQueueHeadTail_d44104; } // Hal function -- kfspGetQueueHeadTail - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kfspGetQueueHeadTail__ = &kfspGetQueueHeadTail_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kfspGetQueueHeadTail__ = &kfspGetQueueHeadTail_d44104; } // Hal function -- kfspUpdateMsgQueueHeadTail - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kfspUpdateMsgQueueHeadTail__ = &kfspUpdateMsgQueueHeadTail_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kfspUpdateMsgQueueHeadTail__ = &kfspUpdateMsgQueueHeadTail_d44104; } // Hal function -- kfspGetMsgQueueHeadTail - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kfspGetMsgQueueHeadTail__ = &kfspGetMsgQueueHeadTail_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kfspGetMsgQueueHeadTail__ = &kfspGetMsgQueueHeadTail_d44104; } // Hal function -- kfspNvdmToSeid - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kfspNvdmToSeid__ = &kfspNvdmToSeid_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kfspNvdmToSeid__ = &kfspNvdmToSeid_b2b553; } // Hal function -- kfspCreateMctpHeader - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kfspCreateMctpHeader__ = &kfspCreateMctpHeader_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kfspCreateMctpHeader__ = &kfspCreateMctpHeader_b2b553; } // Hal function -- kfspCreateNvdmHeader - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kfspCreateNvdmHeader__ = &kfspCreateNvdmHeader_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kfspCreateNvdmHeader__ = &kfspCreateNvdmHeader_b2b553; } // Hal function -- kfspWriteToEmem - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kfspWriteToEmem__ = &kfspWriteToEmem_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kfspWriteToEmem__ = &kfspWriteToEmem_395e98; } // Hal function -- kfspReadFromEmem - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kfspReadFromEmem__ = &kfspReadFromEmem_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kfspReadFromEmem__ = &kfspReadFromEmem_395e98; } // Hal function -- kfspGetPacketInfo - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kfspGetPacketInfo__ = &kfspGetPacketInfo_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kfspGetPacketInfo__ = &kfspGetPacketInfo_395e98; } // Hal function -- kfspValidateMctpPayloadHeader - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kfspValidateMctpPayloadHeader__ = &kfspValidateMctpPayloadHeader_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kfspValidateMctpPayloadHeader__ = &kfspValidateMctpPayloadHeader_395e98; } // Hal function -- kfspProcessNvdmMessage - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kfspProcessNvdmMessage__ = &kfspProcessNvdmMessage_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kfspProcessNvdmMessage__ = &kfspProcessNvdmMessage_395e98; } // Hal function -- kfspProcessCommandResponse - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kfspProcessCommandResponse__ = &kfspProcessCommandResponse_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kfspProcessCommandResponse__ = &kfspProcessCommandResponse_395e98; } // Hal function -- kfspDumpDebugState - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kfspDumpDebugState__ = &kfspDumpDebugState_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kfspDumpDebugState__ = &kfspDumpDebugState_d44104; } // Hal function -- kfspErrorCode2NvStatusMap - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kfspErrorCode2NvStatusMap__ = &kfspErrorCode2NvStatusMap_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kfspErrorCode2NvStatusMap__ = &kfspErrorCode2NvStatusMap_395e98; } + // Hal function -- kfspGetExtraReservedMemorySize + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfspGetExtraReservedMemorySize__ = &kfspGetExtraReservedMemorySize_GH100; + } + // default + else + { + pThis->__kfspGetExtraReservedMemorySize__ = &kfspGetExtraReservedMemorySize_4a4dee; + } + // Hal function -- kfspCheckGspSecureScratch - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kfspCheckGspSecureScratch__ = &kfspCheckGspSecureScratch_GH100; } diff --git a/src/nvidia/generated/g_kern_fsp_nvoc.h b/src/nvidia/generated/g_kern_fsp_nvoc.h index f80d1d387..0fa2171ee 100644 --- a/src/nvidia/generated/g_kern_fsp_nvoc.h +++ b/src/nvidia/generated/g_kern_fsp_nvoc.h @@ -37,7 +37,6 @@ extern "C" { #include "core/core.h" #include "gpu/eng_state.h" #include "kernel/gpu/fifo/channel_descendant.h" -#include "kernel/gpu/intrable/intrable.h" #include "kernel/gpu/intr/intr_service.h" #include "fsp/nvdm_payload_cmd_response.h" @@ -165,6 +164,7 @@ struct KernelFsp { NV_STATUS (*__kfspProcessCommandResponse__)(struct OBJGPU *, struct KernelFsp *, NvU8 *, NvU32); void (*__kfspDumpDebugState__)(struct OBJGPU *, struct KernelFsp *); NV_STATUS (*__kfspErrorCode2NvStatusMap__)(struct OBJGPU *, struct KernelFsp *, NvU32); + NvU64 (*__kfspGetExtraReservedMemorySize__)(struct OBJGPU *, struct KernelFsp *); NvBool (*__kfspCheckGspSecureScratch__)(struct OBJGPU *, struct KernelFsp *); NV_STATUS (*__kfspReconcileTunableState__)(POBJGPU, struct KernelFsp *, void *); NV_STATUS (*__kfspStateLoad__)(POBJGPU, struct KernelFsp *, NvU32); @@ -289,6 +289,8 @@ NV_STATUS __nvoc_objCreate_KernelFsp(KernelFsp**, Dynamic*, NvU32); #define kfspDumpDebugState_HAL(pGpu, pKernelFsp) kfspDumpDebugState_DISPATCH(pGpu, pKernelFsp) #define kfspErrorCode2NvStatusMap(pGpu, pKernelFsp, errorCode) kfspErrorCode2NvStatusMap_DISPATCH(pGpu, pKernelFsp, errorCode) #define kfspErrorCode2NvStatusMap_HAL(pGpu, pKernelFsp, errorCode) kfspErrorCode2NvStatusMap_DISPATCH(pGpu, pKernelFsp, errorCode) +#define kfspGetExtraReservedMemorySize(pGpu, pKernelFsp) kfspGetExtraReservedMemorySize_DISPATCH(pGpu, pKernelFsp) +#define kfspGetExtraReservedMemorySize_HAL(pGpu, pKernelFsp) kfspGetExtraReservedMemorySize_DISPATCH(pGpu, pKernelFsp) #define kfspCheckGspSecureScratch(pGpu, pKernelFsp) kfspCheckGspSecureScratch_DISPATCH(pGpu, pKernelFsp) #define kfspCheckGspSecureScratch_HAL(pGpu, pKernelFsp) kfspCheckGspSecureScratch_DISPATCH(pGpu, pKernelFsp) #define kfspReconcileTunableState(pGpu, pEngstate, pTunableState) kfspReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) @@ -563,6 +565,16 @@ static inline NV_STATUS kfspErrorCode2NvStatusMap_DISPATCH(struct OBJGPU *pGpu, return pKernelFsp->__kfspErrorCode2NvStatusMap__(pGpu, pKernelFsp, errorCode); } +NvU64 kfspGetExtraReservedMemorySize_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp); + +static inline NvU64 kfspGetExtraReservedMemorySize_4a4dee(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + return 0; +} + +static inline NvU64 kfspGetExtraReservedMemorySize_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + return pKernelFsp->__kfspGetExtraReservedMemorySize__(pGpu, pKernelFsp); +} + NvBool kfspCheckGspSecureScratch_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp); static inline NvBool kfspCheckGspSecureScratch_491d52(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { diff --git a/src/nvidia/generated/g_kern_gmmu_nvoc.c b/src/nvidia/generated/g_kern_gmmu_nvoc.c index 5ec7c1151..01dba5bb1 100644 --- a/src/nvidia/generated/g_kern_gmmu_nvoc.c +++ b/src/nvidia/generated/g_kern_gmmu_nvoc.c @@ -83,15 +83,19 @@ static NV_STATUS __nvoc_thunk_KernelGmmu_engstateStateInitLocked(OBJGPU *pGpu, s return kgmmuStateInitLocked(pGpu, (struct KernelGmmu *)(((unsigned char *)pKernelGmmu) - __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_KernelGmmu_engstateStatePostLoad(OBJGPU *pGpu, struct OBJENGSTATE *pKernelGmmu, NvU32 flags) { - return kgmmuStatePostLoad(pGpu, (struct KernelGmmu *)(((unsigned char *)pKernelGmmu) - __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset), flags); +static NV_STATUS __nvoc_thunk_KernelGmmu_engstateStatePostLoad(OBJGPU *pGpu, struct OBJENGSTATE *pKernelGmmu, NvU32 arg0) { + return kgmmuStatePostLoad(pGpu, (struct KernelGmmu *)(((unsigned char *)pKernelGmmu) - __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset), arg0); +} + +static NV_STATUS __nvoc_thunk_KernelGmmu_engstateStatePreUnload(OBJGPU *pGpu, struct OBJENGSTATE *pKernelGmmu, NvU32 arg0) { + return kgmmuStatePreUnload(pGpu, (struct KernelGmmu *)(((unsigned char *)pKernelGmmu) - __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset), arg0); } static void __nvoc_thunk_KernelGmmu_engstateStateDestroy(OBJGPU *pGpu, struct OBJENGSTATE *pKernelGmmu) { kgmmuStateDestroy(pGpu, (struct KernelGmmu *)(((unsigned char *)pKernelGmmu) - __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset)); } -static void __nvoc_thunk_KernelGmmu_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pKernelGmmu, IntrServiceRecord arg0[155]) { +static void __nvoc_thunk_KernelGmmu_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pKernelGmmu, IntrServiceRecord arg0[163]) { kgmmuRegisterIntrService(pGpu, (struct KernelGmmu *)(((unsigned char *)pKernelGmmu) - __nvoc_rtti_KernelGmmu_IntrService.offset), arg0); } @@ -123,10 +127,6 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgmmuStatePostUnload(POBJGPU pGpu, str return engstateStatePostUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgmmuStatePreUnload(POBJGPU pGpu, struct KernelGmmu *pEngstate, NvU32 arg0) { - return engstateStatePreUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset), arg0); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgmmuStateInitUnlocked(POBJGPU pGpu, struct KernelGmmu *pEngstate) { return engstateStateInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset)); } @@ -199,41 +199,25 @@ void __nvoc_init_dataField_KernelGmmu(KernelGmmu *pThis, RmHalspecOwner *pRmhals PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // NVOC Property Hal field -- PDB_PROP_KGMMU_SYSMEM_FAULT_BUFFER_GPU_UNCACHED - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_KGMMU_SYSMEM_FAULT_BUFFER_GPU_UNCACHED, ((NvBool)(0 == 0))); } - // default - else - { - pThis->setProperty(pThis, PDB_PROP_KGMMU_SYSMEM_FAULT_BUFFER_GPU_UNCACHED, ((NvBool)(0 != 0))); - } // Hal field -- defaultBigPageSize - if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->defaultBigPageSize = (64 * 1024); } - else if (0) - { - } // Hal field -- bHugePageSupported - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->bHugePageSupported = ((NvBool)(0 == 0)); } - // default - else - { - pThis->bHugePageSupported = ((NvBool)(0 != 0)); - } // Hal field -- bPageSize512mbSupported - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->bPageSize512mbSupported = ((NvBool)(0 == 0)); } @@ -255,15 +239,10 @@ void __nvoc_init_dataField_KernelGmmu(KernelGmmu *pThis, RmHalspecOwner *pRmhals } // Hal field -- bVaspaceInteropSupported - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->bVaspaceInteropSupported = ((NvBool)(0 == 0)); } - // default - else - { - pThis->bVaspaceInteropSupported = ((NvBool)(0 != 0)); - } } NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); @@ -302,12 +281,15 @@ static void __nvoc_init_funcTable_KernelGmmu_1(KernelGmmu *pThis, RmHalspecOwner pThis->__kgmmuStateInitLocked__ = &kgmmuStateInitLocked_IMPL; // Hal function -- kgmmuStatePostLoad - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kgmmuStatePostLoad__ = &kgmmuStatePostLoad_IMPL; } - else if (0) + + // Hal function -- kgmmuStatePreUnload + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { + pThis->__kgmmuStatePreUnload__ = &kgmmuStatePreUnload_IMPL; } pThis->__kgmmuStateDestroy__ = &kgmmuStateDestroy_IMPL; @@ -317,42 +299,27 @@ static void __nvoc_init_funcTable_KernelGmmu_1(KernelGmmu *pThis, RmHalspecOwner pThis->__kgmmuServiceInterrupt__ = &kgmmuServiceInterrupt_IMPL; // Hal function -- kgmmuInstBlkVaLimitGet - if (0) - { - } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__kgmmuInstBlkVaLimitGet__ = &kgmmuInstBlkVaLimitGet_GV100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kgmmuInstBlkVaLimitGet__ = &kgmmuInstBlkVaLimitGet_f03539; } // Hal function -- kgmmuSetTlbInvalidateMembarWarParameters - if (0) - { - } - else if (0) - { - } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__kgmmuSetTlbInvalidateMembarWarParameters__ = &kgmmuSetTlbInvalidateMembarWarParameters_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kgmmuSetTlbInvalidateMembarWarParameters__ = &kgmmuSetTlbInvalidateMembarWarParameters_4a4dee; } // Hal function -- kgmmuSetTlbInvalidationScope - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kgmmuSetTlbInvalidationScope__ = &kgmmuSetTlbInvalidationScope_GA100; } @@ -362,176 +329,125 @@ static void __nvoc_init_funcTable_KernelGmmu_1(KernelGmmu *pThis, RmHalspecOwner } // Hal function -- kgmmuFmtInitPteComptagLine - if (0) - { - } - else if (0) - { - } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kgmmuFmtInitPteComptagLine__ = &kgmmuFmtInitPteComptagLine_TU10X; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kgmmuFmtInitPteComptagLine__ = &kgmmuFmtInitPteComptagLine_b3696a; } // Hal function -- kgmmuFmtInitPeerPteFld - if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kgmmuFmtInitPeerPteFld__ = &kgmmuFmtInitPeerPteFld_TU10X; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kgmmuFmtInitPeerPteFld__ = &kgmmuFmtInitPeerPteFld_b3696a; } // Hal function -- kgmmuFmtInitPte - if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kgmmuFmtInitPte__ = &kgmmuFmtInitPte_GP10X; } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kgmmuFmtInitPte__ = &kgmmuFmtInitPte_GH10X; } - else if (0) - { - } // Hal function -- kgmmuFmtInitPde - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kgmmuFmtInitPde__ = &kgmmuFmtInitPde_GP10X; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kgmmuFmtInitPde__ = &kgmmuFmtInitPde_GH10X; } - else if (0) - { - } // Hal function -- kgmmuFmtIsVersionSupported - if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kgmmuFmtIsVersionSupported__ = &kgmmuFmtIsVersionSupported_GP10X; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kgmmuFmtIsVersionSupported__ = &kgmmuFmtIsVersionSupported_GH10X; } - else if (0) - { - } // Hal function -- kgmmuFmtInitLevels - if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__kgmmuFmtInitLevels__ = &kgmmuFmtInitLevels_GP10X; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kgmmuFmtInitLevels__ = &kgmmuFmtInitLevels_GA10X; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kgmmuFmtInitLevels__ = &kgmmuFmtInitLevels_GH10X; } - else if (0) - { - } // Hal function -- kgmmuFmtInitPdeMulti - if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kgmmuFmtInitPdeMulti__ = &kgmmuFmtInitPdeMulti_GP10X; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kgmmuFmtInitPdeMulti__ = &kgmmuFmtInitPdeMulti_GH10X; } - else if (0) - { - } // Hal function -- kgmmuFmtFamiliesInit - if (0) - { - } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kgmmuFmtFamiliesInit__ = &kgmmuFmtFamiliesInit_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kgmmuFmtFamiliesInit__ = &kgmmuFmtFamiliesInit_GH100; } - else if (0) - { - } // Hal function -- kgmmuTranslatePtePcfFromSw - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kgmmuTranslatePtePcfFromSw__ = &kgmmuTranslatePtePcfFromSw_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kgmmuTranslatePtePcfFromSw__ = &kgmmuTranslatePtePcfFromSw_56cd7a; } // Hal function -- kgmmuTranslatePtePcfFromHw - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kgmmuTranslatePtePcfFromHw__ = &kgmmuTranslatePtePcfFromHw_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kgmmuTranslatePtePcfFromHw__ = &kgmmuTranslatePtePcfFromHw_56cd7a; } // Hal function -- kgmmuTranslatePdePcfFromSw - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kgmmuTranslatePdePcfFromSw__ = &kgmmuTranslatePdePcfFromSw_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kgmmuTranslatePdePcfFromSw__ = &kgmmuTranslatePdePcfFromSw_56cd7a; } // Hal function -- kgmmuTranslatePdePcfFromHw - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kgmmuTranslatePdePcfFromHw__ = &kgmmuTranslatePdePcfFromHw_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kgmmuTranslatePdePcfFromHw__ = &kgmmuTranslatePdePcfFromHw_56cd7a; } @@ -541,24 +457,20 @@ static void __nvoc_init_funcTable_KernelGmmu_1(KernelGmmu *pThis, RmHalspecOwner { pThis->__kgmmuSetupWarForBug2720120__ = &kgmmuSetupWarForBug2720120_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kgmmuSetupWarForBug2720120__ = &kgmmuSetupWarForBug2720120_56cd7a; } // Hal function -- kgmmuGetGraphicsEngineId - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kgmmuGetGraphicsEngineId__ = &kgmmuGetGraphicsEngineId_GV100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kgmmuGetGraphicsEngineId__ = &kgmmuGetGraphicsEngineId_GH100; } - // default - else - { - } pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelGmmu_engstateConstructEngine; @@ -566,6 +478,8 @@ static void __nvoc_init_funcTable_KernelGmmu_1(KernelGmmu *pThis, RmHalspecOwner pThis->__nvoc_base_OBJENGSTATE.__engstateStatePostLoad__ = &__nvoc_thunk_KernelGmmu_engstateStatePostLoad; + pThis->__nvoc_base_OBJENGSTATE.__engstateStatePreUnload__ = &__nvoc_thunk_KernelGmmu_engstateStatePreUnload; + pThis->__nvoc_base_OBJENGSTATE.__engstateStateDestroy__ = &__nvoc_thunk_KernelGmmu_engstateStateDestroy; pThis->__nvoc_base_IntrService.__intrservRegisterIntrService__ = &__nvoc_thunk_KernelGmmu_intrservRegisterIntrService; @@ -584,8 +498,6 @@ static void __nvoc_init_funcTable_KernelGmmu_1(KernelGmmu *pThis, RmHalspecOwner pThis->__kgmmuStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_kgmmuStatePostUnload; - pThis->__kgmmuStatePreUnload__ = &__nvoc_thunk_OBJENGSTATE_kgmmuStatePreUnload; - pThis->__kgmmuStateInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kgmmuStateInitUnlocked; pThis->__kgmmuInitMissing__ = &__nvoc_thunk_OBJENGSTATE_kgmmuInitMissing; diff --git a/src/nvidia/generated/g_kern_gmmu_nvoc.h b/src/nvidia/generated/g_kern_gmmu_nvoc.h index 13b8cdf26..1576f22ab 100644 --- a/src/nvidia/generated/g_kern_gmmu_nvoc.h +++ b/src/nvidia/generated/g_kern_gmmu_nvoc.h @@ -275,6 +275,7 @@ struct KernelGmmu { NV_STATUS (*__kgmmuConstructEngine__)(OBJGPU *, struct KernelGmmu *, ENGDESCRIPTOR); NV_STATUS (*__kgmmuStateInitLocked__)(OBJGPU *, struct KernelGmmu *); NV_STATUS (*__kgmmuStatePostLoad__)(OBJGPU *, struct KernelGmmu *, NvU32); + NV_STATUS (*__kgmmuStatePreUnload__)(OBJGPU *, struct KernelGmmu *, NvU32); void (*__kgmmuStateDestroy__)(OBJGPU *, struct KernelGmmu *); void (*__kgmmuRegisterIntrService__)(OBJGPU *, struct KernelGmmu *, IntrServiceRecord *); NvU32 (*__kgmmuServiceInterrupt__)(OBJGPU *, struct KernelGmmu *, IntrServiceServiceInterruptArguments *); @@ -301,7 +302,6 @@ struct KernelGmmu { NV_STATUS (*__kgmmuServiceNotificationInterrupt__)(struct OBJGPU *, struct KernelGmmu *, IntrServiceServiceNotificationInterruptArguments *); NV_STATUS (*__kgmmuStatePreLoad__)(POBJGPU, struct KernelGmmu *, NvU32); NV_STATUS (*__kgmmuStatePostUnload__)(POBJGPU, struct KernelGmmu *, NvU32); - NV_STATUS (*__kgmmuStatePreUnload__)(POBJGPU, struct KernelGmmu *, NvU32); NV_STATUS (*__kgmmuStateInitUnlocked__)(POBJGPU, struct KernelGmmu *); void (*__kgmmuInitMissing__)(POBJGPU, struct KernelGmmu *); NV_STATUS (*__kgmmuStatePreInitLocked__)(POBJGPU, struct KernelGmmu *); @@ -316,8 +316,87 @@ struct KernelGmmu { NvBool PDB_PROP_KGMMU_SYSMEM_FAULT_BUFFER_GPU_UNCACHED; NvBool PDB_PROP_KGMMU_FAULT_BUFFER_DISABLED; const NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pStaticInfo; - GMMU_FMT_FAMILY *pFmtFamilies[3]; NvU32 defaultBigPageSize; + NvU32 uvmSharedIntrRmOwnsMask; + GMMU_FMT_FAMILY *PRIVATE_FIELD(pFmtFamilies)[3]; + NvU32 PRIVATE_FIELD(PDEAperture); + NvU32 PRIVATE_FIELD(PDEAttr); + NvU32 PRIVATE_FIELD(PDEBAR1Aperture); + NvU32 PRIVATE_FIELD(PDEBAR1Attr); + NvU32 PRIVATE_FIELD(PTEAperture); + NvU32 PRIVATE_FIELD(PTEAttr); + NvU32 PRIVATE_FIELD(PTEBAR1Aperture); + NvU32 PRIVATE_FIELD(PTEBAR1Attr); + NvU32 PRIVATE_FIELD(overrideBigPageSize); + NvBool PRIVATE_FIELD(bEnablePerVaspaceBigPage); + NvBool PRIVATE_FIELD(bIgnoreHubTlbInvalidate); + NvU64 PRIVATE_FIELD(maxVASize); + struct NV_FIELD_ENUM_ENTRY PRIVATE_FIELD(pdeApertures)[5]; + struct NV_FIELD_ENUM_ENTRY PRIVATE_FIELD(pteApertures)[5]; + MEMORY_DESCRIPTOR *PRIVATE_FIELD(pWarSmallPageTable); + MEMORY_DESCRIPTOR *PRIVATE_FIELD(pWarPageDirectory0); + struct GMMU_FAULT_BUFFER PRIVATE_FIELD(mmuFaultBuffer)[64]; + NvU64 PRIVATE_FIELD(sysmemBaseAddress); + NvBool PRIVATE_FIELD(bHugePageSupported); + NvBool PRIVATE_FIELD(bPageSize512mbSupported); + NvBool PRIVATE_FIELD(bBug2720120WarEnabled); + NvBool PRIVATE_FIELD(bVaspaceInteropSupported); +}; +struct KernelGmmu_PRIVATE { + const struct NVOC_RTTI *__nvoc_rtti; + struct OBJENGSTATE __nvoc_base_OBJENGSTATE; + struct IntrService __nvoc_base_IntrService; + struct Object *__nvoc_pbase_Object; + struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; + struct IntrService *__nvoc_pbase_IntrService; + struct KernelGmmu *__nvoc_pbase_KernelGmmu; + NV_STATUS (*__kgmmuConstructEngine__)(OBJGPU *, struct KernelGmmu *, ENGDESCRIPTOR); + NV_STATUS (*__kgmmuStateInitLocked__)(OBJGPU *, struct KernelGmmu *); + NV_STATUS (*__kgmmuStatePostLoad__)(OBJGPU *, struct KernelGmmu *, NvU32); + NV_STATUS (*__kgmmuStatePreUnload__)(OBJGPU *, struct KernelGmmu *, NvU32); + void (*__kgmmuStateDestroy__)(OBJGPU *, struct KernelGmmu *); + void (*__kgmmuRegisterIntrService__)(OBJGPU *, struct KernelGmmu *, IntrServiceRecord *); + NvU32 (*__kgmmuServiceInterrupt__)(OBJGPU *, struct KernelGmmu *, IntrServiceServiceInterruptArguments *); + NV_STATUS (*__kgmmuInstBlkVaLimitGet__)(struct KernelGmmu *, struct OBJVASPACE *, NvU32, INST_BLK_INIT_PARAMS *, NvU32 *, NvU64 *); + NvU32 (*__kgmmuSetTlbInvalidateMembarWarParameters__)(OBJGPU *, struct KernelGmmu *, TLB_INVALIDATE_PARAMS *); + NV_STATUS (*__kgmmuSetTlbInvalidationScope__)(OBJGPU *, struct KernelGmmu *, NvU32, TLB_INVALIDATE_PARAMS *); + void (*__kgmmuFmtInitPteComptagLine__)(struct KernelGmmu *, struct GMMU_FMT_PTE *, const NvU32); + void (*__kgmmuFmtInitPeerPteFld__)(struct KernelGmmu *, struct GMMU_FMT_PTE *, const NvU32); + void (*__kgmmuFmtInitPte__)(struct KernelGmmu *, struct GMMU_FMT_PTE *, const NvU32, const struct NV_FIELD_ENUM_ENTRY *, const NvBool); + void (*__kgmmuFmtInitPde__)(struct KernelGmmu *, struct GMMU_FMT_PDE *, const NvU32, const struct NV_FIELD_ENUM_ENTRY *); + NvBool (*__kgmmuFmtIsVersionSupported__)(struct KernelGmmu *, NvU32); + void (*__kgmmuFmtInitLevels__)(struct KernelGmmu *, MMU_FMT_LEVEL *, const NvU32, const NvU32, const NvU32); + void (*__kgmmuFmtInitPdeMulti__)(struct KernelGmmu *, struct GMMU_FMT_PDE_MULTI *, const NvU32, const struct NV_FIELD_ENUM_ENTRY *); + NV_STATUS (*__kgmmuFmtFamiliesInit__)(OBJGPU *, struct KernelGmmu *); + NV_STATUS (*__kgmmuTranslatePtePcfFromSw__)(struct KernelGmmu *, NvU32, NvU32 *); + NV_STATUS (*__kgmmuTranslatePtePcfFromHw__)(struct KernelGmmu *, NvU32, NvBool, NvU32 *); + NV_STATUS (*__kgmmuTranslatePdePcfFromSw__)(struct KernelGmmu *, NvU32, NvU32 *); + NV_STATUS (*__kgmmuTranslatePdePcfFromHw__)(struct KernelGmmu *, NvU32, GMMU_APERTURE, NvU32 *); + NV_STATUS (*__kgmmuSetupWarForBug2720120__)(struct KernelGmmu *, GMMU_FMT_FAMILY *); + NvU32 (*__kgmmuGetGraphicsEngineId__)(struct KernelGmmu *); + NV_STATUS (*__kgmmuReconcileTunableState__)(POBJGPU, struct KernelGmmu *, void *); + NV_STATUS (*__kgmmuStateLoad__)(POBJGPU, struct KernelGmmu *, NvU32); + NV_STATUS (*__kgmmuStateUnload__)(POBJGPU, struct KernelGmmu *, NvU32); + NV_STATUS (*__kgmmuServiceNotificationInterrupt__)(struct OBJGPU *, struct KernelGmmu *, IntrServiceServiceNotificationInterruptArguments *); + NV_STATUS (*__kgmmuStatePreLoad__)(POBJGPU, struct KernelGmmu *, NvU32); + NV_STATUS (*__kgmmuStatePostUnload__)(POBJGPU, struct KernelGmmu *, NvU32); + NV_STATUS (*__kgmmuStateInitUnlocked__)(POBJGPU, struct KernelGmmu *); + void (*__kgmmuInitMissing__)(POBJGPU, struct KernelGmmu *); + NV_STATUS (*__kgmmuStatePreInitLocked__)(POBJGPU, struct KernelGmmu *); + NV_STATUS (*__kgmmuStatePreInitUnlocked__)(POBJGPU, struct KernelGmmu *); + NV_STATUS (*__kgmmuGetTunableState__)(POBJGPU, struct KernelGmmu *, void *); + NV_STATUS (*__kgmmuCompareTunableState__)(POBJGPU, struct KernelGmmu *, void *, void *); + void (*__kgmmuFreeTunableState__)(POBJGPU, struct KernelGmmu *, void *); + NvBool (*__kgmmuClearInterrupt__)(struct OBJGPU *, struct KernelGmmu *, IntrServiceClearInterruptArguments *); + NV_STATUS (*__kgmmuAllocTunableState__)(POBJGPU, struct KernelGmmu *, void **); + NV_STATUS (*__kgmmuSetTunableState__)(POBJGPU, struct KernelGmmu *, void *); + NvBool (*__kgmmuIsPresent__)(POBJGPU, struct KernelGmmu *); + NvBool PDB_PROP_KGMMU_SYSMEM_FAULT_BUFFER_GPU_UNCACHED; + NvBool PDB_PROP_KGMMU_FAULT_BUFFER_DISABLED; + const NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pStaticInfo; + NvU32 defaultBigPageSize; + NvU32 uvmSharedIntrRmOwnsMask; + GMMU_FMT_FAMILY *pFmtFamilies[3]; NvU32 PDEAperture; NvU32 PDEAttr; NvU32 PDEBAR1Aperture; @@ -335,7 +414,6 @@ struct KernelGmmu { MEMORY_DESCRIPTOR *pWarSmallPageTable; MEMORY_DESCRIPTOR *pWarPageDirectory0; struct GMMU_FAULT_BUFFER mmuFaultBuffer[64]; - NvU32 uvmSharedIntrRmOwnsMask; NvU64 sysmemBaseAddress; NvBool bHugePageSupported; NvBool bPageSize512mbSupported; @@ -379,8 +457,10 @@ NV_STATUS __nvoc_objCreate_KernelGmmu(KernelGmmu**, Dynamic*, NvU32); #define kgmmuConstructEngine(pGpu, pKernelGmmu, arg0) kgmmuConstructEngine_DISPATCH(pGpu, pKernelGmmu, arg0) #define kgmmuStateInitLocked(pGpu, pKernelGmmu) kgmmuStateInitLocked_DISPATCH(pGpu, pKernelGmmu) -#define kgmmuStatePostLoad(pGpu, pKernelGmmu, flags) kgmmuStatePostLoad_DISPATCH(pGpu, pKernelGmmu, flags) -#define kgmmuStatePostLoad_HAL(pGpu, pKernelGmmu, flags) kgmmuStatePostLoad_DISPATCH(pGpu, pKernelGmmu, flags) +#define kgmmuStatePostLoad(pGpu, pKernelGmmu, arg0) kgmmuStatePostLoad_DISPATCH(pGpu, pKernelGmmu, arg0) +#define kgmmuStatePostLoad_HAL(pGpu, pKernelGmmu, arg0) kgmmuStatePostLoad_DISPATCH(pGpu, pKernelGmmu, arg0) +#define kgmmuStatePreUnload(pGpu, pKernelGmmu, arg0) kgmmuStatePreUnload_DISPATCH(pGpu, pKernelGmmu, arg0) +#define kgmmuStatePreUnload_HAL(pGpu, pKernelGmmu, arg0) kgmmuStatePreUnload_DISPATCH(pGpu, pKernelGmmu, arg0) #define kgmmuStateDestroy(pGpu, pKernelGmmu) kgmmuStateDestroy_DISPATCH(pGpu, pKernelGmmu) #define kgmmuRegisterIntrService(pGpu, pKernelGmmu, arg0) kgmmuRegisterIntrService_DISPATCH(pGpu, pKernelGmmu, arg0) #define kgmmuServiceInterrupt(pGpu, pKernelGmmu, pParams) kgmmuServiceInterrupt_DISPATCH(pGpu, pKernelGmmu, pParams) @@ -424,7 +504,6 @@ NV_STATUS __nvoc_objCreate_KernelGmmu(KernelGmmu**, Dynamic*, NvU32); #define kgmmuServiceNotificationInterrupt(pGpu, pIntrService, pParams) kgmmuServiceNotificationInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define kgmmuStatePreLoad(pGpu, pEngstate, arg0) kgmmuStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kgmmuStatePostUnload(pGpu, pEngstate, arg0) kgmmuStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) -#define kgmmuStatePreUnload(pGpu, pEngstate, arg0) kgmmuStatePreUnload_DISPATCH(pGpu, pEngstate, arg0) #define kgmmuStateInitUnlocked(pGpu, pEngstate) kgmmuStateInitUnlocked_DISPATCH(pGpu, pEngstate) #define kgmmuInitMissing(pGpu, pEngstate) kgmmuInitMissing_DISPATCH(pGpu, pEngstate) #define kgmmuStatePreInitLocked(pGpu, pEngstate) kgmmuStatePreInitLocked_DISPATCH(pGpu, pEngstate) @@ -438,6 +517,7 @@ NV_STATUS __nvoc_objCreate_KernelGmmu(KernelGmmu**, Dynamic*, NvU32); #define kgmmuIsPresent(pGpu, pEngstate) kgmmuIsPresent_DISPATCH(pGpu, pEngstate) NvU32 kgmmuGetMaxBigPageSize_GM107(struct KernelGmmu *pKernelGmmu); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NvU32 kgmmuGetMaxBigPageSize(struct KernelGmmu *pKernelGmmu) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -453,6 +533,7 @@ static inline NvU32 kgmmuGetVaspaceClass_f515df(struct KernelGmmu *pKernelGmmu) return (37105); } + #ifdef __nvoc_kern_gmmu_h_disabled static inline NvU32 kgmmuGetVaspaceClass(struct KernelGmmu *pKernelGmmu) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -466,6 +547,7 @@ static inline NvU32 kgmmuGetVaspaceClass(struct KernelGmmu *pKernelGmmu) { NV_STATUS kgmmuInstBlkAtsGet_GV100(struct KernelGmmu *pKernelGmmu, struct OBJVASPACE *pVAS, NvU32 subctxid, NvU32 *pOffset, NvU32 *pData); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NV_STATUS kgmmuInstBlkAtsGet(struct KernelGmmu *pKernelGmmu, struct OBJVASPACE *pVAS, NvU32 subctxid, NvU32 *pOffset, NvU32 *pData) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -479,6 +561,7 @@ static inline NV_STATUS kgmmuInstBlkAtsGet(struct KernelGmmu *pKernelGmmu, struc NV_STATUS kgmmuInstBlkPageDirBaseGet_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, struct OBJVASPACE *pVAS, INST_BLK_INIT_PARAMS *pParams, NvU32 subctxid, NvU32 *pOffsetLo, NvU32 *pDataLo, NvU32 *pOffsetHi, NvU32 *pDataHi); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NV_STATUS kgmmuInstBlkPageDirBaseGet(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, struct OBJVASPACE *pVAS, INST_BLK_INIT_PARAMS *pParams, NvU32 subctxid, NvU32 *pOffsetLo, NvU32 *pDataLo, NvU32 *pOffsetHi, NvU32 *pDataHi) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -492,6 +575,7 @@ static inline NV_STATUS kgmmuInstBlkPageDirBaseGet(OBJGPU *pGpu, struct KernelGm NvU32 kgmmuGetPDBAllocSize_GP100(struct KernelGmmu *pKernelGmmu, const MMU_FMT_LEVEL *arg0, NvU64 arg1); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NvU32 kgmmuGetPDBAllocSize(struct KernelGmmu *pKernelGmmu, const MMU_FMT_LEVEL *arg0, NvU64 arg1) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -505,6 +589,7 @@ static inline NvU32 kgmmuGetPDBAllocSize(struct KernelGmmu *pKernelGmmu, const M NvU32 kgmmuGetBigPageSize_GM107(struct KernelGmmu *pKernelGmmu); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NvU32 kgmmuGetBigPageSize(struct KernelGmmu *pKernelGmmu) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -518,6 +603,7 @@ static inline NvU32 kgmmuGetBigPageSize(struct KernelGmmu *pKernelGmmu) { NV_STATUS kgmmuInitStaticInfo_KERNEL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pStaticInfo); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NV_STATUS kgmmuInitStaticInfo(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pStaticInfo) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -531,6 +617,7 @@ static inline NV_STATUS kgmmuInitStaticInfo(OBJGPU *pGpu, struct KernelGmmu *pKe void kgmmuFmtInitCaps_GM20X(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT *pFmt); + #ifdef __nvoc_kern_gmmu_h_disabled static inline void kgmmuFmtInitCaps(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT *pFmt) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -543,6 +630,7 @@ static inline void kgmmuFmtInitCaps(struct KernelGmmu *pKernelGmmu, struct GMMU_ void kgmmuFmtInitPteApertures_GM10X(struct KernelGmmu *pKernelGmmu, struct NV_FIELD_ENUM_ENTRY *pEntries); + #ifdef __nvoc_kern_gmmu_h_disabled static inline void kgmmuFmtInitPteApertures(struct KernelGmmu *pKernelGmmu, struct NV_FIELD_ENUM_ENTRY *pEntries) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -555,6 +643,7 @@ static inline void kgmmuFmtInitPteApertures(struct KernelGmmu *pKernelGmmu, stru void kgmmuFmtInitPdeApertures_GM10X(struct KernelGmmu *pKernelGmmu, struct NV_FIELD_ENUM_ENTRY *pEntries); + #ifdef __nvoc_kern_gmmu_h_disabled static inline void kgmmuFmtInitPdeApertures(struct KernelGmmu *pKernelGmmu, struct NV_FIELD_ENUM_ENTRY *pEntries) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -567,6 +656,7 @@ static inline void kgmmuFmtInitPdeApertures(struct KernelGmmu *pKernelGmmu, stru void kgmmuInvalidateTlb_GM107(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, MEMORY_DESCRIPTOR *pRootPageDir, NvU32 vaspaceFlags, VAS_PTE_UPDATE_TYPE update_type, NvU32 gfid, NvU32 invalidation_scope); + #ifdef __nvoc_kern_gmmu_h_disabled static inline void kgmmuInvalidateTlb(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, MEMORY_DESCRIPTOR *pRootPageDir, NvU32 vaspaceFlags, VAS_PTE_UPDATE_TYPE update_type, NvU32 gfid, NvU32 invalidation_scope) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -579,6 +669,7 @@ static inline void kgmmuInvalidateTlb(OBJGPU *pGpu, struct KernelGmmu *pKernelGm NV_STATUS kgmmuCheckPendingInvalidates_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, RMTIMEOUT *pTimeOut, NvU32 gfid); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NV_STATUS kgmmuCheckPendingInvalidates(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, RMTIMEOUT *pTimeOut, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -592,6 +683,7 @@ static inline NV_STATUS kgmmuCheckPendingInvalidates(OBJGPU *pGpu, struct Kernel NV_STATUS kgmmuCommitTlbInvalidate_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, TLB_INVALIDATE_PARAMS *pParams); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NV_STATUS kgmmuCommitTlbInvalidate(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, TLB_INVALIDATE_PARAMS *pParams) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -605,6 +697,7 @@ static inline NV_STATUS kgmmuCommitTlbInvalidate(OBJGPU *pGpu, struct KernelGmmu void kgmmuSetPdbToInvalidate_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, TLB_INVALIDATE_PARAMS *pParams); + #ifdef __nvoc_kern_gmmu_h_disabled static inline void kgmmuSetPdbToInvalidate(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, TLB_INVALIDATE_PARAMS *pParams) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -615,8 +708,23 @@ static inline void kgmmuSetPdbToInvalidate(OBJGPU *pGpu, struct KernelGmmu *pKer #define kgmmuSetPdbToInvalidate_HAL(pGpu, pKernelGmmu, pParams) kgmmuSetPdbToInvalidate(pGpu, pKernelGmmu, pParams) +NV_STATUS kgmmuEnableComputePeerAddressing_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 flags); + + +#ifdef __nvoc_kern_gmmu_h_disabled +static inline NV_STATUS kgmmuEnableComputePeerAddressing(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 flags) { + NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kern_gmmu_h_disabled +#define kgmmuEnableComputePeerAddressing(pGpu, pKernelGmmu, flags) kgmmuEnableComputePeerAddressing_IMPL(pGpu, pKernelGmmu, flags) +#endif //__nvoc_kern_gmmu_h_disabled + +#define kgmmuEnableComputePeerAddressing_HAL(pGpu, pKernelGmmu, flags) kgmmuEnableComputePeerAddressing(pGpu, pKernelGmmu, flags) + void kgmmuDetermineMaxVASize_GM107(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + #ifdef __nvoc_kern_gmmu_h_disabled static inline void kgmmuDetermineMaxVASize(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -629,6 +737,7 @@ static inline void kgmmuDetermineMaxVASize(OBJGPU *pGpu, struct KernelGmmu *pKer NV_STATUS kgmmuGetFaultRegisterMappings_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvP64 *pFaultBufferGet, NvP64 *pFaultBufferPut, NvP64 *pFaultBufferInfo, NvP64 *faultIntr, NvP64 *faultIntrSet, NvP64 *faultIntrClear, NvU32 *faultMask, NvP64 *pPrefetchCtrl); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NV_STATUS kgmmuGetFaultRegisterMappings(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvP64 *pFaultBufferGet, NvP64 *pFaultBufferPut, NvP64 *pFaultBufferInfo, NvP64 *faultIntr, NvP64 *faultIntrSet, NvP64 *faultIntrClear, NvU32 *faultMask, NvP64 *pPrefetchCtrl) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -642,6 +751,7 @@ static inline NV_STATUS kgmmuGetFaultRegisterMappings(OBJGPU *pGpu, struct Kerne const char *kgmmuGetFaultTypeString_GP100(struct KernelGmmu *pKernelGmmu, NvU32 faultType); + #ifdef __nvoc_kern_gmmu_h_disabled static inline const char *kgmmuGetFaultTypeString(struct KernelGmmu *pKernelGmmu, NvU32 faultType) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -655,6 +765,7 @@ static inline const char *kgmmuGetFaultTypeString(struct KernelGmmu *pKernelGmmu NV_STATUS kgmmuChangeReplayableFaultOwnership_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvBool arg0); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NV_STATUS kgmmuChangeReplayableFaultOwnership(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvBool arg0) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -668,6 +779,7 @@ static inline NV_STATUS kgmmuChangeReplayableFaultOwnership(OBJGPU *pGpu, struct NV_STATUS kgmmuServiceReplayableFault_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NV_STATUS kgmmuServiceReplayableFault(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -681,6 +793,7 @@ static inline NV_STATUS kgmmuServiceReplayableFault(OBJGPU *pGpu, struct KernelG NV_STATUS kgmmuReportFaultBufferOverflow_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NV_STATUS kgmmuReportFaultBufferOverflow(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -694,6 +807,7 @@ static inline NV_STATUS kgmmuReportFaultBufferOverflow(OBJGPU *pGpu, struct Kern NV_STATUS kgmmuReadFaultBufferGetPtr_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvU32 *pGetOffset, struct THREAD_STATE_NODE *arg0); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NV_STATUS kgmmuReadFaultBufferGetPtr(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvU32 *pGetOffset, struct THREAD_STATE_NODE *arg0) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -705,21 +819,23 @@ static inline NV_STATUS kgmmuReadFaultBufferGetPtr(OBJGPU *pGpu, struct KernelGm #define kgmmuReadFaultBufferGetPtr_HAL(pGpu, pKernelGmmu, index, pGetOffset, arg0) kgmmuReadFaultBufferGetPtr(pGpu, pKernelGmmu, index, pGetOffset, arg0) -NV_STATUS kgmmuReadFaultBufferPutPtr_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvU32 *pPutOffset); +NV_STATUS kgmmuReadFaultBufferPutPtr_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvU32 *pPutOffset, struct THREAD_STATE_NODE *arg0); + #ifdef __nvoc_kern_gmmu_h_disabled -static inline NV_STATUS kgmmuReadFaultBufferPutPtr(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvU32 *pPutOffset) { +static inline NV_STATUS kgmmuReadFaultBufferPutPtr(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvU32 *pPutOffset, struct THREAD_STATE_NODE *arg0) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kern_gmmu_h_disabled -#define kgmmuReadFaultBufferPutPtr(pGpu, pKernelGmmu, index, pPutOffset) kgmmuReadFaultBufferPutPtr_TU102(pGpu, pKernelGmmu, index, pPutOffset) +#define kgmmuReadFaultBufferPutPtr(pGpu, pKernelGmmu, index, pPutOffset, arg0) kgmmuReadFaultBufferPutPtr_TU102(pGpu, pKernelGmmu, index, pPutOffset, arg0) #endif //__nvoc_kern_gmmu_h_disabled -#define kgmmuReadFaultBufferPutPtr_HAL(pGpu, pKernelGmmu, index, pPutOffset) kgmmuReadFaultBufferPutPtr(pGpu, pKernelGmmu, index, pPutOffset) +#define kgmmuReadFaultBufferPutPtr_HAL(pGpu, pKernelGmmu, index, pPutOffset, arg0) kgmmuReadFaultBufferPutPtr(pGpu, pKernelGmmu, index, pPutOffset, arg0) NvU32 kgmmuReadMmuFaultBufferSize_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0, NvU32 gfid); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NvU32 kgmmuReadMmuFaultBufferSize(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -733,6 +849,7 @@ static inline NvU32 kgmmuReadMmuFaultBufferSize(OBJGPU *pGpu, struct KernelGmmu NvU32 kgmmuReadMmuFaultStatus_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 gfid); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NvU32 kgmmuReadMmuFaultStatus(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -746,6 +863,7 @@ static inline NvU32 kgmmuReadMmuFaultStatus(OBJGPU *pGpu, struct KernelGmmu *pKe void kgmmuWriteMmuFaultStatus_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0); + #ifdef __nvoc_kern_gmmu_h_disabled static inline void kgmmuWriteMmuFaultStatus(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -758,6 +876,7 @@ static inline void kgmmuWriteMmuFaultStatus(OBJGPU *pGpu, struct KernelGmmu *pKe NvBool kgmmuIsNonReplayableFaultPending_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NvBool kgmmuIsNonReplayableFaultPending(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -771,6 +890,7 @@ static inline NvBool kgmmuIsNonReplayableFaultPending(OBJGPU *pGpu, struct Kerne NV_STATUS kgmmuClientShadowFaultBufferAlloc_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NV_STATUS kgmmuClientShadowFaultBufferAlloc(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -784,6 +904,7 @@ static inline NV_STATUS kgmmuClientShadowFaultBufferAlloc(OBJGPU *pGpu, struct K NV_STATUS kgmmuClientShadowFaultBufferFree_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NV_STATUS kgmmuClientShadowFaultBufferFree(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -797,6 +918,7 @@ static inline NV_STATUS kgmmuClientShadowFaultBufferFree(OBJGPU *pGpu, struct Ke void kgmmuEncodeSysmemAddrs_GM107(struct KernelGmmu *pKernelGmmu, NvU64 *pAddresses, NvU64 count); + #ifdef __nvoc_kern_gmmu_h_disabled static inline void kgmmuEncodeSysmemAddrs(struct KernelGmmu *pKernelGmmu, NvU64 *pAddresses, NvU64 count) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -809,6 +931,7 @@ static inline void kgmmuEncodeSysmemAddrs(struct KernelGmmu *pKernelGmmu, NvU64 NvU8 kgmmuGetHwPteApertureFromMemdesc_GM107(struct KernelGmmu *pKernelGmmu, MEMORY_DESCRIPTOR *pDesc); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NvU8 kgmmuGetHwPteApertureFromMemdesc(struct KernelGmmu *pKernelGmmu, MEMORY_DESCRIPTOR *pDesc) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -822,6 +945,7 @@ static inline NvU8 kgmmuGetHwPteApertureFromMemdesc(struct KernelGmmu *pKernelGm NvBool kgmmuTestAccessCounterWriteNak_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NvBool kgmmuTestAccessCounterWriteNak(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -835,6 +959,7 @@ static inline NvBool kgmmuTestAccessCounterWriteNak(OBJGPU *pGpu, struct KernelG NV_STATUS kgmmuEnableNvlinkComputePeerAddressing_GV100(struct KernelGmmu *pKernelGmmu); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NV_STATUS kgmmuEnableNvlinkComputePeerAddressing(struct KernelGmmu *pKernelGmmu) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -846,6 +971,19 @@ static inline NV_STATUS kgmmuEnableNvlinkComputePeerAddressing(struct KernelGmmu #define kgmmuEnableNvlinkComputePeerAddressing_HAL(pKernelGmmu) kgmmuEnableNvlinkComputePeerAddressing(pKernelGmmu) +void kgmmuClearNonReplayableFaultIntr_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, struct THREAD_STATE_NODE *arg0); + + +#ifdef __nvoc_kern_gmmu_h_disabled +static inline void kgmmuClearNonReplayableFaultIntr(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, struct THREAD_STATE_NODE *arg0) { + NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); +} +#else //__nvoc_kern_gmmu_h_disabled +#define kgmmuClearNonReplayableFaultIntr(pGpu, pKernelGmmu, arg0) kgmmuClearNonReplayableFaultIntr_TU102(pGpu, pKernelGmmu, arg0) +#endif //__nvoc_kern_gmmu_h_disabled + +#define kgmmuClearNonReplayableFaultIntr_HAL(pGpu, pKernelGmmu, arg0) kgmmuClearNonReplayableFaultIntr(pGpu, pKernelGmmu, arg0) + NV_STATUS kgmmuConstructEngine_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, ENGDESCRIPTOR arg0); static inline NV_STATUS kgmmuConstructEngine_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, ENGDESCRIPTOR arg0) { @@ -858,14 +996,16 @@ static inline NV_STATUS kgmmuStateInitLocked_DISPATCH(OBJGPU *pGpu, struct Kerne return pKernelGmmu->__kgmmuStateInitLocked__(pGpu, pKernelGmmu); } -NV_STATUS kgmmuStatePostLoad_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 flags); +NV_STATUS kgmmuStatePostLoad_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0); -static inline NV_STATUS kgmmuStatePostLoad_56cd7a(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 flags) { - return NV_OK; +static inline NV_STATUS kgmmuStatePostLoad_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0) { + return pKernelGmmu->__kgmmuStatePostLoad__(pGpu, pKernelGmmu, arg0); } -static inline NV_STATUS kgmmuStatePostLoad_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 flags) { - return pKernelGmmu->__kgmmuStatePostLoad__(pGpu, pKernelGmmu, flags); +NV_STATUS kgmmuStatePreUnload_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0); + +static inline NV_STATUS kgmmuStatePreUnload_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0) { + return pKernelGmmu->__kgmmuStatePreUnload__(pGpu, pKernelGmmu, arg0); } void kgmmuStateDestroy_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); @@ -874,9 +1014,9 @@ static inline void kgmmuStateDestroy_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *p pKernelGmmu->__kgmmuStateDestroy__(pGpu, pKernelGmmu); } -void kgmmuRegisterIntrService_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, IntrServiceRecord arg0[155]); +void kgmmuRegisterIntrService_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, IntrServiceRecord arg0[163]); -static inline void kgmmuRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, IntrServiceRecord arg0[155]) { +static inline void kgmmuRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, IntrServiceRecord arg0[163]) { pKernelGmmu->__kgmmuRegisterIntrService__(pGpu, pKernelGmmu, arg0); } @@ -941,10 +1081,6 @@ void kgmmuFmtInitPte_GP10X(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PTE * void kgmmuFmtInitPte_GH10X(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PTE *pPte, const NvU32 version, const struct NV_FIELD_ENUM_ENTRY *pPteApertures, const NvBool bUnifiedAperture); -static inline void kgmmuFmtInitPte_b3696a(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PTE *pPte, const NvU32 version, const struct NV_FIELD_ENUM_ENTRY *pPteApertures, const NvBool bUnifiedAperture) { - return; -} - static inline void kgmmuFmtInitPte_DISPATCH(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PTE *pPte, const NvU32 version, const struct NV_FIELD_ENUM_ENTRY *pPteApertures, const NvBool bUnifiedAperture) { pKernelGmmu->__kgmmuFmtInitPte__(pKernelGmmu, pPte, version, pPteApertures, bUnifiedAperture); } @@ -953,10 +1089,6 @@ void kgmmuFmtInitPde_GP10X(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PDE * void kgmmuFmtInitPde_GH10X(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PDE *pPde, const NvU32 version, const struct NV_FIELD_ENUM_ENTRY *pPdeApertures); -static inline void kgmmuFmtInitPde_b3696a(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PDE *pPde, const NvU32 version, const struct NV_FIELD_ENUM_ENTRY *pPdeApertures) { - return; -} - static inline void kgmmuFmtInitPde_DISPATCH(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PDE *pPde, const NvU32 version, const struct NV_FIELD_ENUM_ENTRY *pPdeApertures) { pKernelGmmu->__kgmmuFmtInitPde__(pKernelGmmu, pPde, version, pPdeApertures); } @@ -965,10 +1097,6 @@ NvBool kgmmuFmtIsVersionSupported_GP10X(struct KernelGmmu *pKernelGmmu, NvU32 ve NvBool kgmmuFmtIsVersionSupported_GH10X(struct KernelGmmu *pKernelGmmu, NvU32 version); -static inline NvBool kgmmuFmtIsVersionSupported_491d52(struct KernelGmmu *pKernelGmmu, NvU32 version) { - return ((NvBool)(0 != 0)); -} - static inline NvBool kgmmuFmtIsVersionSupported_DISPATCH(struct KernelGmmu *pKernelGmmu, NvU32 version) { return pKernelGmmu->__kgmmuFmtIsVersionSupported__(pKernelGmmu, version); } @@ -979,10 +1107,6 @@ void kgmmuFmtInitLevels_GA10X(struct KernelGmmu *pKernelGmmu, MMU_FMT_LEVEL *pLe void kgmmuFmtInitLevels_GH10X(struct KernelGmmu *pKernelGmmu, MMU_FMT_LEVEL *pLevels, const NvU32 numLevels, const NvU32 version, const NvU32 bigPageShift); -static inline void kgmmuFmtInitLevels_b3696a(struct KernelGmmu *pKernelGmmu, MMU_FMT_LEVEL *pLevels, const NvU32 numLevels, const NvU32 version, const NvU32 bigPageShift) { - return; -} - static inline void kgmmuFmtInitLevels_DISPATCH(struct KernelGmmu *pKernelGmmu, MMU_FMT_LEVEL *pLevels, const NvU32 numLevels, const NvU32 version, const NvU32 bigPageShift) { pKernelGmmu->__kgmmuFmtInitLevels__(pKernelGmmu, pLevels, numLevels, version, bigPageShift); } @@ -991,10 +1115,6 @@ void kgmmuFmtInitPdeMulti_GP10X(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_ void kgmmuFmtInitPdeMulti_GH10X(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PDE_MULTI *pPdeMulti, const NvU32 version, const struct NV_FIELD_ENUM_ENTRY *pPdeApertures); -static inline void kgmmuFmtInitPdeMulti_b3696a(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PDE_MULTI *pPdeMulti, const NvU32 version, const struct NV_FIELD_ENUM_ENTRY *pPdeApertures) { - return; -} - static inline void kgmmuFmtInitPdeMulti_DISPATCH(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT_PDE_MULTI *pPdeMulti, const NvU32 version, const struct NV_FIELD_ENUM_ENTRY *pPdeApertures) { pKernelGmmu->__kgmmuFmtInitPdeMulti__(pKernelGmmu, pPdeMulti, version, pPdeApertures); } @@ -1003,10 +1123,6 @@ NV_STATUS kgmmuFmtFamiliesInit_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmm NV_STATUS kgmmuFmtFamiliesInit_GH100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); -static inline NV_STATUS kgmmuFmtFamiliesInit_56cd7a(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { - return NV_OK; -} - static inline NV_STATUS kgmmuFmtFamiliesInit_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { return pKernelGmmu->__kgmmuFmtFamiliesInit__(pGpu, pKernelGmmu); } @@ -1065,10 +1181,6 @@ NvU32 kgmmuGetGraphicsEngineId_GV100(struct KernelGmmu *pKernelGmmu); NvU32 kgmmuGetGraphicsEngineId_GH100(struct KernelGmmu *pKernelGmmu); -static inline NvU32 kgmmuGetGraphicsEngineId_4a4dee(struct KernelGmmu *pKernelGmmu) { - return 0; -} - static inline NvU32 kgmmuGetGraphicsEngineId_DISPATCH(struct KernelGmmu *pKernelGmmu) { return pKernelGmmu->__kgmmuGetGraphicsEngineId__(pKernelGmmu); } @@ -1097,10 +1209,6 @@ static inline NV_STATUS kgmmuStatePostUnload_DISPATCH(POBJGPU pGpu, struct Kerne return pEngstate->__kgmmuStatePostUnload__(pGpu, pEngstate, arg0); } -static inline NV_STATUS kgmmuStatePreUnload_DISPATCH(POBJGPU pGpu, struct KernelGmmu *pEngstate, NvU32 arg0) { - return pEngstate->__kgmmuStatePreUnload__(pGpu, pEngstate, arg0); -} - static inline NV_STATUS kgmmuStateInitUnlocked_DISPATCH(POBJGPU pGpu, struct KernelGmmu *pEngstate) { return pEngstate->__kgmmuStateInitUnlocked__(pGpu, pEngstate); } @@ -1146,72 +1254,100 @@ static inline NvBool kgmmuIsPresent_DISPATCH(POBJGPU pGpu, struct KernelGmmu *pE } static inline NvU32 kgmmuGetPDEAperture(struct KernelGmmu *pKernelGmmu) { - return pKernelGmmu->PDEAperture; + struct KernelGmmu_PRIVATE *pKernelGmmu_PRIVATE = (struct KernelGmmu_PRIVATE *)pKernelGmmu; + return pKernelGmmu_PRIVATE->PDEAperture; } static inline NvU32 kgmmuGetPTEAperture(struct KernelGmmu *pKernelGmmu) { - return pKernelGmmu->PTEAperture; + struct KernelGmmu_PRIVATE *pKernelGmmu_PRIVATE = (struct KernelGmmu_PRIVATE *)pKernelGmmu; + return pKernelGmmu_PRIVATE->PTEAperture; } static inline NvU32 kgmmuGetPDEBAR1Aperture(struct KernelGmmu *pKernelGmmu) { - return pKernelGmmu->PDEBAR1Aperture; + struct KernelGmmu_PRIVATE *pKernelGmmu_PRIVATE = (struct KernelGmmu_PRIVATE *)pKernelGmmu; + return pKernelGmmu_PRIVATE->PDEBAR1Aperture; } static inline NvU32 kgmmuGetPTEBAR1Aperture(struct KernelGmmu *pKernelGmmu) { - return pKernelGmmu->PTEBAR1Aperture; + struct KernelGmmu_PRIVATE *pKernelGmmu_PRIVATE = (struct KernelGmmu_PRIVATE *)pKernelGmmu; + return pKernelGmmu_PRIVATE->PTEBAR1Aperture; } static inline NvU32 kgmmuGetPDEBAR1Attr(struct KernelGmmu *pKernelGmmu) { - return pKernelGmmu->PDEBAR1Attr; + struct KernelGmmu_PRIVATE *pKernelGmmu_PRIVATE = (struct KernelGmmu_PRIVATE *)pKernelGmmu; + return pKernelGmmu_PRIVATE->PDEBAR1Attr; } static inline NvU32 kgmmuGetPTEBAR1Attr(struct KernelGmmu *pKernelGmmu) { - return pKernelGmmu->PTEBAR1Attr; + struct KernelGmmu_PRIVATE *pKernelGmmu_PRIVATE = (struct KernelGmmu_PRIVATE *)pKernelGmmu; + return pKernelGmmu_PRIVATE->PTEBAR1Attr; } static inline NvU32 kgmmuGetPDEAttr(struct KernelGmmu *pKernelGmmu) { - return pKernelGmmu->PDEAttr; + struct KernelGmmu_PRIVATE *pKernelGmmu_PRIVATE = (struct KernelGmmu_PRIVATE *)pKernelGmmu; + return pKernelGmmu_PRIVATE->PDEAttr; } static inline NvU32 kgmmuGetPTEAttr(struct KernelGmmu *pKernelGmmu) { - return pKernelGmmu->PTEAttr; + struct KernelGmmu_PRIVATE *pKernelGmmu_PRIVATE = (struct KernelGmmu_PRIVATE *)pKernelGmmu; + return pKernelGmmu_PRIVATE->PTEAttr; } static inline NvU32 kgmmuGetBigPageSizeOverride(struct KernelGmmu *pKernelGmmu) { - return pKernelGmmu->overrideBigPageSize; + struct KernelGmmu_PRIVATE *pKernelGmmu_PRIVATE = (struct KernelGmmu_PRIVATE *)pKernelGmmu; + return pKernelGmmu_PRIVATE->overrideBigPageSize; } static inline void kgmmuSetBigPageSizeOverride(struct KernelGmmu *pKernelGmmu, NvU32 bigPageSize) { - pKernelGmmu->overrideBigPageSize = bigPageSize; + struct KernelGmmu_PRIVATE *pKernelGmmu_PRIVATE = (struct KernelGmmu_PRIVATE *)pKernelGmmu; + pKernelGmmu_PRIVATE->overrideBigPageSize = bigPageSize; } static inline NvBool kgmmuIsPerVaspaceBigPageEn(struct KernelGmmu *pKernelGmmu) { - return pKernelGmmu->bEnablePerVaspaceBigPage; + struct KernelGmmu_PRIVATE *pKernelGmmu_PRIVATE = (struct KernelGmmu_PRIVATE *)pKernelGmmu; + return pKernelGmmu_PRIVATE->bEnablePerVaspaceBigPage; } static inline NvBool kgmmuIsIgnoreHubTlbInvalidate(struct KernelGmmu *pKernelGmmu) { - return pKernelGmmu->bIgnoreHubTlbInvalidate; + struct KernelGmmu_PRIVATE *pKernelGmmu_PRIVATE = (struct KernelGmmu_PRIVATE *)pKernelGmmu; + return pKernelGmmu_PRIVATE->bIgnoreHubTlbInvalidate; } static inline NvBool kgmmuIsHugePageSupported(struct KernelGmmu *pKernelGmmu) { - return pKernelGmmu->bHugePageSupported; + struct KernelGmmu_PRIVATE *pKernelGmmu_PRIVATE = (struct KernelGmmu_PRIVATE *)pKernelGmmu; + return pKernelGmmu_PRIVATE->bHugePageSupported; } static inline NvBool kgmmuIsPageSize512mbSupported(struct KernelGmmu *pKernelGmmu) { - return pKernelGmmu->bPageSize512mbSupported; + struct KernelGmmu_PRIVATE *pKernelGmmu_PRIVATE = (struct KernelGmmu_PRIVATE *)pKernelGmmu; + return pKernelGmmu_PRIVATE->bPageSize512mbSupported; } static inline NvBool kgmmuIsBug2720120WarEnabled(struct KernelGmmu *pKernelGmmu) { - return pKernelGmmu->bBug2720120WarEnabled; + struct KernelGmmu_PRIVATE *pKernelGmmu_PRIVATE = (struct KernelGmmu_PRIVATE *)pKernelGmmu; + return pKernelGmmu_PRIVATE->bBug2720120WarEnabled; } static inline NvBool kgmmuIsVaspaceInteropSupported(struct KernelGmmu *pKernelGmmu) { - return pKernelGmmu->bVaspaceInteropSupported; + struct KernelGmmu_PRIVATE *pKernelGmmu_PRIVATE = (struct KernelGmmu_PRIVATE *)pKernelGmmu; + return pKernelGmmu_PRIVATE->bVaspaceInteropSupported; +} + +static inline NvU64 kgmmuGetMaxVASize(struct KernelGmmu *pKernelGmmu) { + struct KernelGmmu_PRIVATE *pKernelGmmu_PRIVATE = (struct KernelGmmu_PRIVATE *)pKernelGmmu; + return pKernelGmmu_PRIVATE->maxVASize; +} + +static inline NvU64 kgmmuGetSysBaseAddress(struct KernelGmmu *pKernelGmmu) { + struct KernelGmmu_PRIVATE *pKernelGmmu_PRIVATE = (struct KernelGmmu_PRIVATE *)pKernelGmmu; + return pKernelGmmu_PRIVATE->sysmemBaseAddress; } void kgmmuDestruct_IMPL(struct KernelGmmu *pKernelGmmu); + #define __nvoc_kgmmuDestruct(pKernelGmmu) kgmmuDestruct_IMPL(pKernelGmmu) NV_STATUS kgmmuFmtInit_IMPL(struct KernelGmmu *pKernelGmmu); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NV_STATUS kgmmuFmtInit(struct KernelGmmu *pKernelGmmu) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -1222,6 +1358,7 @@ static inline NV_STATUS kgmmuFmtInit(struct KernelGmmu *pKernelGmmu) { #endif //__nvoc_kern_gmmu_h_disabled GMMU_APERTURE kgmmuGetMemAperture_IMPL(struct KernelGmmu *pKernelGmmu, MEMORY_DESCRIPTOR *pMemDesc); + #ifdef __nvoc_kern_gmmu_h_disabled static inline GMMU_APERTURE kgmmuGetMemAperture(struct KernelGmmu *pKernelGmmu, MEMORY_DESCRIPTOR *pMemDesc) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -1234,6 +1371,7 @@ static inline GMMU_APERTURE kgmmuGetMemAperture(struct KernelGmmu *pKernelGmmu, #endif //__nvoc_kern_gmmu_h_disabled const GMMU_FMT_FAMILY *kgmmuFmtGetFamily_IMPL(struct KernelGmmu *pKernelGmmu, NvU32 version); + #ifdef __nvoc_kern_gmmu_h_disabled static inline const GMMU_FMT_FAMILY *kgmmuFmtGetFamily(struct KernelGmmu *pKernelGmmu, NvU32 version) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -1244,6 +1382,7 @@ static inline const GMMU_FMT_FAMILY *kgmmuFmtGetFamily(struct KernelGmmu *pKerne #endif //__nvoc_kern_gmmu_h_disabled const NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *kgmmuGetStaticInfo_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + #ifdef __nvoc_kern_gmmu_h_disabled static inline const NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *kgmmuGetStaticInfo(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -1254,6 +1393,7 @@ static inline const NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *kgmmuGetSt #endif //__nvoc_kern_gmmu_h_disabled const struct GMMU_FMT *kgmmuFmtGet_IMPL(struct KernelGmmu *pKernelGmmu, NvU32 version, NvU64 bigPageSize); + #ifdef __nvoc_kern_gmmu_h_disabled static inline const struct GMMU_FMT *kgmmuFmtGet(struct KernelGmmu *pKernelGmmu, NvU32 version, NvU64 bigPageSize) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -1264,6 +1404,7 @@ static inline const struct GMMU_FMT *kgmmuFmtGet(struct KernelGmmu *pKernelGmmu, #endif //__nvoc_kern_gmmu_h_disabled void kgmmuExtractPteInfo_IMPL(struct KernelGmmu *pKernelGmmu, union GMMU_ENTRY_VALUE *arg0, NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK *arg1, const struct GMMU_FMT *arg2, const MMU_FMT_LEVEL *arg3); + #ifdef __nvoc_kern_gmmu_h_disabled static inline void kgmmuExtractPteInfo(struct KernelGmmu *pKernelGmmu, union GMMU_ENTRY_VALUE *arg0, NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK *arg1, const struct GMMU_FMT *arg2, const MMU_FMT_LEVEL *arg3) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -1273,6 +1414,7 @@ static inline void kgmmuExtractPteInfo(struct KernelGmmu *pKernelGmmu, union GMM #endif //__nvoc_kern_gmmu_h_disabled void kgmmuFieldSetKindCompTags_IMPL(struct KernelGmmu *pKernelGmmu, const struct GMMU_FMT *pFmt, const MMU_FMT_LEVEL *pLevel, const COMPR_INFO *pCompr, NvU64 physAddr, NvU64 surfOffset, NvU32 pteIndex, NvU8 *pEntries); + #ifdef __nvoc_kern_gmmu_h_disabled static inline void kgmmuFieldSetKindCompTags(struct KernelGmmu *pKernelGmmu, const struct GMMU_FMT *pFmt, const MMU_FMT_LEVEL *pLevel, const COMPR_INFO *pCompr, NvU64 physAddr, NvU64 surfOffset, NvU32 pteIndex, NvU8 *pEntries) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -1282,6 +1424,7 @@ static inline void kgmmuFieldSetKindCompTags(struct KernelGmmu *pKernelGmmu, con #endif //__nvoc_kern_gmmu_h_disabled NvBool kgmmuFmtIsBigPageSizeSupported_IMPL(struct KernelGmmu *pKernelGmmu, NvU64 bigPageSize); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NvBool kgmmuFmtIsBigPageSizeSupported(struct KernelGmmu *pKernelGmmu, NvU64 bigPageSize) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -1292,6 +1435,7 @@ static inline NvBool kgmmuFmtIsBigPageSizeSupported(struct KernelGmmu *pKernelGm #endif //__nvoc_kern_gmmu_h_disabled const struct GMMU_FMT *kgmmuFmtGetLatestSupportedFormat_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + #ifdef __nvoc_kern_gmmu_h_disabled static inline const struct GMMU_FMT *kgmmuFmtGetLatestSupportedFormat(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -1302,6 +1446,7 @@ static inline const struct GMMU_FMT *kgmmuFmtGetLatestSupportedFormat(OBJGPU *pG #endif //__nvoc_kern_gmmu_h_disabled NvU32 kgmmuGetMinBigPageSize_IMPL(struct KernelGmmu *pKernelGmmu); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NvU32 kgmmuGetMinBigPageSize(struct KernelGmmu *pKernelGmmu) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -1312,6 +1457,7 @@ static inline NvU32 kgmmuGetMinBigPageSize(struct KernelGmmu *pKernelGmmu) { #endif //__nvoc_kern_gmmu_h_disabled NV_STATUS kgmmuInstBlkInit_IMPL(struct KernelGmmu *pKernelGmmu, PMEMORY_DESCRIPTOR pInstBlkDesc, struct OBJVASPACE *pVAS, NvU32 subctxId, INST_BLK_INIT_PARAMS *pInstBlkParams); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NV_STATUS kgmmuInstBlkInit(struct KernelGmmu *pKernelGmmu, PMEMORY_DESCRIPTOR pInstBlkDesc, struct OBJVASPACE *pVAS, NvU32 subctxId, INST_BLK_INIT_PARAMS *pInstBlkParams) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -1322,6 +1468,7 @@ static inline NV_STATUS kgmmuInstBlkInit(struct KernelGmmu *pKernelGmmu, PMEMORY #endif //__nvoc_kern_gmmu_h_disabled NV_STATUS kgmmuFaultBufferReplayableAllocate_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvHandle arg0, NvHandle arg1); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NV_STATUS kgmmuFaultBufferReplayableAllocate(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvHandle arg0, NvHandle arg1) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -1332,6 +1479,7 @@ static inline NV_STATUS kgmmuFaultBufferReplayableAllocate(OBJGPU *pGpu, struct #endif //__nvoc_kern_gmmu_h_disabled NV_STATUS kgmmuFaultBufferReplayableDestroy_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NV_STATUS kgmmuFaultBufferReplayableDestroy(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -1342,6 +1490,7 @@ static inline NV_STATUS kgmmuFaultBufferReplayableDestroy(OBJGPU *pGpu, struct K #endif //__nvoc_kern_gmmu_h_disabled NV_STATUS kgmmuFaultBufferAlloc_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0, NvU32 arg1); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NV_STATUS kgmmuFaultBufferAlloc(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0, NvU32 arg1) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -1352,6 +1501,7 @@ static inline NV_STATUS kgmmuFaultBufferAlloc(OBJGPU *pGpu, struct KernelGmmu *p #endif //__nvoc_kern_gmmu_h_disabled NV_STATUS kgmmuFaultBufferCreateMemDesc_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0, NvU32 arg1, NvU64 arg2, MEMORY_DESCRIPTOR **arg3); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NV_STATUS kgmmuFaultBufferCreateMemDesc(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0, NvU32 arg1, NvU64 arg2, MEMORY_DESCRIPTOR **arg3) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -1362,6 +1512,7 @@ static inline NV_STATUS kgmmuFaultBufferCreateMemDesc(OBJGPU *pGpu, struct Kerne #endif //__nvoc_kern_gmmu_h_disabled NV_STATUS kgmmuFaultBufferGetAddressSpace_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0, NvU32 *arg1, NvU32 *arg2); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NV_STATUS kgmmuFaultBufferGetAddressSpace(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0, NvU32 *arg1, NvU32 *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -1372,6 +1523,7 @@ static inline NV_STATUS kgmmuFaultBufferGetAddressSpace(OBJGPU *pGpu, struct Ker #endif //__nvoc_kern_gmmu_h_disabled NV_STATUS kgmmuFaultBufferFree_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NV_STATUS kgmmuFaultBufferFree(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -1382,6 +1534,7 @@ static inline NV_STATUS kgmmuFaultBufferFree(OBJGPU *pGpu, struct KernelGmmu *pK #endif //__nvoc_kern_gmmu_h_disabled NV_STATUS kgmmuFaultBufferUnregister_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NV_STATUS kgmmuFaultBufferUnregister(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -1392,6 +1545,7 @@ static inline NV_STATUS kgmmuFaultBufferUnregister(OBJGPU *pGpu, struct KernelGm #endif //__nvoc_kern_gmmu_h_disabled NV_STATUS kgmmuClientShadowFaultBufferNonreplayableAllocate_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NV_STATUS kgmmuClientShadowFaultBufferNonreplayableAllocate(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -1402,6 +1556,7 @@ static inline NV_STATUS kgmmuClientShadowFaultBufferNonreplayableAllocate(OBJGPU #endif //__nvoc_kern_gmmu_h_disabled NV_STATUS kgmmuClientShadowFaultBufferNonreplayableDestroy_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NV_STATUS kgmmuClientShadowFaultBufferNonreplayableDestroy(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -1412,6 +1567,7 @@ static inline NV_STATUS kgmmuClientShadowFaultBufferNonreplayableDestroy(OBJGPU #endif //__nvoc_kern_gmmu_h_disabled NV_STATUS kgmmuClientShadowFaultBufferRegister_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NV_STATUS kgmmuClientShadowFaultBufferRegister(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -1422,6 +1578,7 @@ static inline NV_STATUS kgmmuClientShadowFaultBufferRegister(OBJGPU *pGpu, struc #endif //__nvoc_kern_gmmu_h_disabled void kgmmuClientShadowFaultBufferUnregister_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + #ifdef __nvoc_kern_gmmu_h_disabled static inline void kgmmuClientShadowFaultBufferUnregister(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -1431,6 +1588,7 @@ static inline void kgmmuClientShadowFaultBufferUnregister(OBJGPU *pGpu, struct K #endif //__nvoc_kern_gmmu_h_disabled void kgmmuClientShadowFaultBufferPagesDestroy_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvBool arg0); + #ifdef __nvoc_kern_gmmu_h_disabled static inline void kgmmuClientShadowFaultBufferPagesDestroy(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvBool arg0) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -1440,6 +1598,7 @@ static inline void kgmmuClientShadowFaultBufferPagesDestroy(OBJGPU *pGpu, struct #endif //__nvoc_kern_gmmu_h_disabled void kgmmuClientShadowFaultBufferQueueDestroy_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvBool arg0); + #ifdef __nvoc_kern_gmmu_h_disabled static inline void kgmmuClientShadowFaultBufferQueueDestroy(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvBool arg0) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -1449,6 +1608,7 @@ static inline void kgmmuClientShadowFaultBufferQueueDestroy(OBJGPU *pGpu, struct #endif //__nvoc_kern_gmmu_h_disabled NvU64 kgmmuGetSizeOfPageTables_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, const struct GMMU_FMT *arg0, NvU64 arg1, NvU64 arg2, NvU64 arg3); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NvU64 kgmmuGetSizeOfPageTables(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, const struct GMMU_FMT *arg0, NvU64 arg1, NvU64 arg2, NvU64 arg3) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -1459,6 +1619,7 @@ static inline NvU64 kgmmuGetSizeOfPageTables(OBJGPU *pGpu, struct KernelGmmu *pK #endif //__nvoc_kern_gmmu_h_disabled NvU64 kgmmuGetSizeOfPageDirs_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, const struct GMMU_FMT *arg0, NvU64 arg1, NvU64 arg2, NvU64 arg3); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NvU64 kgmmuGetSizeOfPageDirs(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, const struct GMMU_FMT *arg0, NvU64 arg1, NvU64 arg2, NvU64 arg3) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -1469,8 +1630,10 @@ static inline NvU64 kgmmuGetSizeOfPageDirs(OBJGPU *pGpu, struct KernelGmmu *pKer #endif //__nvoc_kern_gmmu_h_disabled GMMU_APERTURE kgmmuGetExternalAllocAperture_IMPL(NvU32 addressSpace); + #define kgmmuGetExternalAllocAperture(addressSpace) kgmmuGetExternalAllocAperture_IMPL(addressSpace) void kgmmuEncodePhysAddrs_IMPL(struct KernelGmmu *pKernelGmmu, const GMMU_APERTURE aperture, NvU64 *pAddresses, NvU64 fabricBaseAddress, NvU64 count); + #ifdef __nvoc_kern_gmmu_h_disabled static inline void kgmmuEncodePhysAddrs(struct KernelGmmu *pKernelGmmu, const GMMU_APERTURE aperture, NvU64 *pAddresses, NvU64 fabricBaseAddress, NvU64 count) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -1480,6 +1643,7 @@ static inline void kgmmuEncodePhysAddrs(struct KernelGmmu *pKernelGmmu, const GM #endif //__nvoc_kern_gmmu_h_disabled NvU64 kgmmuEncodePhysAddr_IMPL(struct KernelGmmu *pKernelGmmu, const GMMU_APERTURE aperture, NvU64 physAddr, NvU64 fabricBaseAddress); + #ifdef __nvoc_kern_gmmu_h_disabled static inline NvU64 kgmmuEncodePhysAddr(struct KernelGmmu *pKernelGmmu, const GMMU_APERTURE aperture, NvU64 physAddr, NvU64 fabricBaseAddress) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -1490,6 +1654,7 @@ static inline NvU64 kgmmuEncodePhysAddr(struct KernelGmmu *pKernelGmmu, const GM #endif //__nvoc_kern_gmmu_h_disabled void kgmmuAccessCntrChangeIntrOwnership_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvBool arg0); + #ifdef __nvoc_kern_gmmu_h_disabled static inline void kgmmuAccessCntrChangeIntrOwnership(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvBool arg0) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); @@ -1498,6 +1663,28 @@ static inline void kgmmuAccessCntrChangeIntrOwnership(OBJGPU *pGpu, struct Kerne #define kgmmuAccessCntrChangeIntrOwnership(pGpu, pKernelGmmu, arg0) kgmmuAccessCntrChangeIntrOwnership_IMPL(pGpu, pKernelGmmu, arg0) #endif //__nvoc_kern_gmmu_h_disabled +NvS32 *kgmmuGetFatalFaultIntrPendingState_IMPL(struct KernelGmmu *pKernelGmmu, NvU8 gfid); + +#ifdef __nvoc_kern_gmmu_h_disabled +static inline NvS32 *kgmmuGetFatalFaultIntrPendingState(struct KernelGmmu *pKernelGmmu, NvU8 gfid) { + NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); + return NULL; +} +#else //__nvoc_kern_gmmu_h_disabled +#define kgmmuGetFatalFaultIntrPendingState(pKernelGmmu, gfid) kgmmuGetFatalFaultIntrPendingState_IMPL(pKernelGmmu, gfid) +#endif //__nvoc_kern_gmmu_h_disabled + +struct HW_FAULT_BUFFER *kgmmuGetHwFaultBufferPtr_IMPL(struct KernelGmmu *pKernelGmmu, NvU8 gfid, NvU8 faultBufferIndex); + +#ifdef __nvoc_kern_gmmu_h_disabled +static inline struct HW_FAULT_BUFFER *kgmmuGetHwFaultBufferPtr(struct KernelGmmu *pKernelGmmu, NvU8 gfid, NvU8 faultBufferIndex) { + NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); + return NULL; +} +#else //__nvoc_kern_gmmu_h_disabled +#define kgmmuGetHwFaultBufferPtr(pKernelGmmu, gfid, faultBufferIndex) kgmmuGetHwFaultBufferPtr_IMPL(pKernelGmmu, gfid, faultBufferIndex) +#endif //__nvoc_kern_gmmu_h_disabled + #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_kern_mem_sys_nvoc.c b/src/nvidia/generated/g_kern_mem_sys_nvoc.c index d8c9de3be..d279d724c 100644 --- a/src/nvidia/generated/g_kern_mem_sys_nvoc.c +++ b/src/nvidia/generated/g_kern_mem_sys_nvoc.c @@ -172,39 +172,25 @@ void __nvoc_init_dataField_KernelMemorySystem(KernelMemorySystem *pThis, RmHalsp PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // Hal field -- bDisableTiledCachingInvalidatesWithEccBug1521641 - if (0) - { - } // default - else { pThis->bDisableTiledCachingInvalidatesWithEccBug1521641 = ((NvBool)(0 != 0)); } // Hal field -- bGpuCacheEnable - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->bGpuCacheEnable = ((NvBool)(0 == 0)); } - // default - else - { - pThis->bGpuCacheEnable = ((NvBool)(0 != 0)); - } // Hal field -- bNumaNodesAdded pThis->bNumaNodesAdded = ((NvBool)(0 != 0)); // Hal field -- bL2CleanFbPull - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->bL2CleanFbPull = ((NvBool)(0 == 0)); } - // default - else - { - pThis->bL2CleanFbPull = ((NvBool)(0 != 0)); - } // Hal field -- bPreserveComptagBackingStoreOnSuspend pThis->bPreserveComptagBackingStoreOnSuspend = ((NvBool)(0 != 0)); @@ -245,7 +231,7 @@ static void __nvoc_init_funcTable_KernelMemorySystem_1(KernelMemorySystem *pThis pThis->__kmemsysStateDestroy__ = &kmemsysStateDestroy_IMPL; // Hal function -- kmemsysGetFbNumaInfo - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kmemsysGetFbNumaInfo__ = &kmemsysGetFbNumaInfo_GV100; } @@ -259,138 +245,88 @@ static void __nvoc_init_funcTable_KernelMemorySystem_1(KernelMemorySystem *pThis { pThis->__kmemsysReadUsableFbSize__ = &kmemsysReadUsableFbSize_GP102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kmemsysReadUsableFbSize__ = &kmemsysReadUsableFbSize_GA102; } - // default - else - { - } // Hal function -- kmemsysCacheOp - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kmemsysCacheOp__ = &kmemsysCacheOp_GM200; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kmemsysCacheOp__ = &kmemsysCacheOp_GH100; } - else if (0) - { - } // Hal function -- kmemsysDoCacheOp - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kmemsysDoCacheOp__ = &kmemsysDoCacheOp_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kmemsysDoCacheOp__ = &kmemsysDoCacheOp_GH100; } - else if (0) - { - } // Hal function -- kmemsysReadL2SysmemInvalidateReg - if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kmemsysReadL2SysmemInvalidateReg__ = &kmemsysReadL2SysmemInvalidateReg_TU102; } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kmemsysReadL2SysmemInvalidateReg__ = &kmemsysReadL2SysmemInvalidateReg_68b109; } // Hal function -- kmemsysWriteL2SysmemInvalidateReg - if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kmemsysWriteL2SysmemInvalidateReg__ = &kmemsysWriteL2SysmemInvalidateReg_TU102; } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kmemsysWriteL2SysmemInvalidateReg__ = &kmemsysWriteL2SysmemInvalidateReg_f2d351; } // Hal function -- kmemsysReadL2PeermemInvalidateReg - if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kmemsysReadL2PeermemInvalidateReg__ = &kmemsysReadL2PeermemInvalidateReg_TU102; } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kmemsysReadL2PeermemInvalidateReg__ = &kmemsysReadL2PeermemInvalidateReg_68b109; } // Hal function -- kmemsysWriteL2PeermemInvalidateReg - if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kmemsysWriteL2PeermemInvalidateReg__ = &kmemsysWriteL2PeermemInvalidateReg_TU102; } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kmemsysWriteL2PeermemInvalidateReg__ = &kmemsysWriteL2PeermemInvalidateReg_f2d351; } // Hal function -- kmemsysInitFlushSysmemBuffer - if (0) - { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__kmemsysInitFlushSysmemBuffer__ = &kmemsysInitFlushSysmemBuffer_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kmemsysInitFlushSysmemBuffer__ = &kmemsysInitFlushSysmemBuffer_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kmemsysInitFlushSysmemBuffer__ = &kmemsysInitFlushSysmemBuffer_GH100; - } - else if (0) - { - } - else if (0) - { - } } // Hal function -- kmemsysProgramSysmemFlushBuffer - if (0) + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x007003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kmemsysProgramSysmemFlushBuffer__ = &kmemsysProgramSysmemFlushBuffer_GM107; } @@ -398,20 +334,14 @@ static void __nvoc_init_funcTable_KernelMemorySystem_1(KernelMemorySystem *pThis { pThis->__kmemsysProgramSysmemFlushBuffer__ = &kmemsysProgramSysmemFlushBuffer_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kmemsysProgramSysmemFlushBuffer__ = &kmemsysProgramSysmemFlushBuffer_GH100; } - else if (0) - { - } } // Hal function -- kmemsysIsPagePLCable - if (0) - { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ { @@ -429,12 +359,9 @@ static void __nvoc_init_funcTable_KernelMemorySystem_1(KernelMemorySystem *pThis } // Hal function -- kmemsysReadMIGMemoryCfg - if (0) + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kmemsysReadMIGMemoryCfg__ = &kmemsysReadMIGMemoryCfg_GA100; } @@ -446,10 +373,7 @@ static void __nvoc_init_funcTable_KernelMemorySystem_1(KernelMemorySystem *pThis } // Hal function -- kmemsysInitMIGMemoryPartitionTable - if (0) - { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ { @@ -463,11 +387,11 @@ static void __nvoc_init_funcTable_KernelMemorySystem_1(KernelMemorySystem *pThis } // Hal function -- kmemsysSwizzIdToVmmuSegmentsRange - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kmemsysSwizzIdToVmmuSegmentsRange__ = &kmemsysSwizzIdToVmmuSegmentsRange_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kmemsysSwizzIdToVmmuSegmentsRange__ = &kmemsysSwizzIdToVmmuSegmentsRange_GH100; } diff --git a/src/nvidia/generated/g_kern_mem_sys_nvoc.h b/src/nvidia/generated/g_kern_mem_sys_nvoc.h index 714f26cdc..8ff796e07 100644 --- a/src/nvidia/generated/g_kern_mem_sys_nvoc.h +++ b/src/nvidia/generated/g_kern_mem_sys_nvoc.h @@ -329,6 +329,7 @@ NV_STATUS __nvoc_objCreate_KernelMemorySystem(KernelMemorySystem**, Dynamic*, Nv #define kmemsysIsPresent(pGpu, pEngstate) kmemsysIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS kmemsysGetUsableFbSize_KERNEL(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU64 *pFbSize); + #ifdef __nvoc_kern_mem_sys_h_disabled static inline NV_STATUS kmemsysGetUsableFbSize(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU64 *pFbSize) { NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); @@ -344,6 +345,13 @@ static inline void kmemsysAssertSysmemFlushBufferValid_b3696a(OBJGPU *pGpu, stru return; } +void kmemsysAssertSysmemFlushBufferValid_GM107(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); + +void kmemsysAssertSysmemFlushBufferValid_GA100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); + +void kmemsysAssertSysmemFlushBufferValid_GH100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); + + #ifdef __nvoc_kern_mem_sys_h_disabled static inline void kmemsysAssertSysmemFlushBufferValid(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); @@ -354,8 +362,23 @@ static inline void kmemsysAssertSysmemFlushBufferValid(OBJGPU *pGpu, struct Kern #define kmemsysAssertSysmemFlushBufferValid_HAL(pGpu, pKernelMemorySystem) kmemsysAssertSysmemFlushBufferValid(pGpu, pKernelMemorySystem) +NvU32 kmemsysGetFlushSysmemBufferAddrShift_GM107(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); + + +#ifdef __nvoc_kern_mem_sys_h_disabled +static inline NvU32 kmemsysGetFlushSysmemBufferAddrShift(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); + return 0; +} +#else //__nvoc_kern_mem_sys_h_disabled +#define kmemsysGetFlushSysmemBufferAddrShift(pGpu, pKernelMemorySystem) kmemsysGetFlushSysmemBufferAddrShift_GM107(pGpu, pKernelMemorySystem) +#endif //__nvoc_kern_mem_sys_h_disabled + +#define kmemsysGetFlushSysmemBufferAddrShift_HAL(pGpu, pKernelMemorySystem) kmemsysGetFlushSysmemBufferAddrShift(pGpu, pKernelMemorySystem) + NV_STATUS kmemsysInitStaticConfig_KERNEL(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, MEMORY_SYSTEM_STATIC_CONFIG *pConfig); + #ifdef __nvoc_kern_mem_sys_h_disabled static inline NV_STATUS kmemsysInitStaticConfig(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, MEMORY_SYSTEM_STATIC_CONFIG *pConfig) { NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); @@ -371,6 +394,9 @@ static inline NV_STATUS kmemsysPreFillCacheOnlyMemory_56cd7a(OBJGPU *pGpu, struc return NV_OK; } +NV_STATUS kmemsysPreFillCacheOnlyMemory_GM107(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU64 arg0, NvU64 arg1); + + #ifdef __nvoc_kern_mem_sys_h_disabled static inline NV_STATUS kmemsysPreFillCacheOnlyMemory(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU64 arg0, NvU64 arg1) { NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); @@ -386,6 +412,7 @@ static inline NV_STATUS kmemsysCheckDisplayRemapperRange_14278f(OBJGPU *pGpu, st NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_INVALID_STATE); } + #ifdef __nvoc_kern_mem_sys_h_disabled static inline NV_STATUS kmemsysCheckDisplayRemapperRange(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU64 arg0, NvU64 arg1) { NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); @@ -401,6 +428,7 @@ static inline void kmemsysPostHeapCreate_b3696a(OBJGPU *pGpu, struct KernelMemor return; } + #ifdef __nvoc_kern_mem_sys_h_disabled static inline void kmemsysPostHeapCreate(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); @@ -415,6 +443,7 @@ static inline void kmemsysPreHeapDestruct_b3696a(OBJGPU *pGpu, struct KernelMemo return; } + #ifdef __nvoc_kern_mem_sys_h_disabled static inline void kmemsysPreHeapDestruct(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); @@ -427,6 +456,7 @@ static inline void kmemsysPreHeapDestruct(OBJGPU *pGpu, struct KernelMemorySyste NV_STATUS kmemsysAllocComprResources_KERNEL(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, FB_ALLOC_INFO *arg0, NvU64 arg1, NvU32 arg2, NvU32 *arg3, NvU32 arg4); + #ifdef __nvoc_kern_mem_sys_h_disabled static inline NV_STATUS kmemsysAllocComprResources(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, FB_ALLOC_INFO *arg0, NvU64 arg1, NvU32 arg2, NvU32 *arg3, NvU32 arg4) { NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); @@ -442,6 +472,7 @@ static inline void kmemsysFreeComprResources_b3696a(OBJGPU *pGpu, struct KernelM return; } + #ifdef __nvoc_kern_mem_sys_h_disabled static inline void kmemsysFreeComprResources(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 hwResId) { NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); @@ -454,6 +485,7 @@ static inline void kmemsysFreeComprResources(OBJGPU *pGpu, struct KernelMemorySy NV_STATUS kmemsysPopulateMIGGPUInstanceMemConfig_KERNEL(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); + #ifdef __nvoc_kern_mem_sys_h_disabled static inline NV_STATUS kmemsysPopulateMIGGPUInstanceMemConfig(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); @@ -503,10 +535,6 @@ NV_STATUS kmemsysReadUsableFbSize_GP102(OBJGPU *pGpu, struct KernelMemorySystem NV_STATUS kmemsysReadUsableFbSize_GA102(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU64 *pFbSize); -static inline NV_STATUS kmemsysReadUsableFbSize_5baef9(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU64 *pFbSize) { - NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); -} - static inline NV_STATUS kmemsysReadUsableFbSize_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU64 *pFbSize) { return pKernelMemorySystem->__kmemsysReadUsableFbSize__(pGpu, pKernelMemorySystem, pFbSize); } @@ -515,10 +543,6 @@ NV_STATUS kmemsysCacheOp_GM200(OBJGPU *pGpu, struct KernelMemorySystem *pKernelM NV_STATUS kmemsysCacheOp_GH100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, PMEMORY_DESCRIPTOR arg0, FB_CACHE_MEMTYPE arg1, FB_CACHE_OP operation); -static inline NV_STATUS kmemsysCacheOp_56cd7a(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, PMEMORY_DESCRIPTOR arg0, FB_CACHE_MEMTYPE arg1, FB_CACHE_OP operation) { - return NV_OK; -} - static inline NV_STATUS kmemsysCacheOp_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, PMEMORY_DESCRIPTOR arg0, FB_CACHE_MEMTYPE arg1, FB_CACHE_OP operation) { return pKernelMemorySystem->__kmemsysCacheOp__(pGpu, pKernelMemorySystem, arg0, arg1, operation); } @@ -527,10 +551,6 @@ NV_STATUS kmemsysDoCacheOp_GM107(OBJGPU *pGpu, struct KernelMemorySystem *pKerne NV_STATUS kmemsysDoCacheOp_GH100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 arg0, NvU32 arg1, NvU32 arg2, PRMTIMEOUT arg3); -static inline NV_STATUS kmemsysDoCacheOp_46f6a7(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 arg0, NvU32 arg1, NvU32 arg2, PRMTIMEOUT arg3) { - return NV_ERR_NOT_SUPPORTED; -} - static inline NV_STATUS kmemsysDoCacheOp_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 arg0, NvU32 arg1, NvU32 arg2, PRMTIMEOUT arg3) { return pKernelMemorySystem->__kmemsysDoCacheOp__(pGpu, pKernelMemorySystem, arg0, arg1, arg2, arg3); } @@ -575,24 +595,14 @@ static inline void kmemsysWriteL2PeermemInvalidateReg_DISPATCH(OBJGPU *pGpu, str pKernelMemorySystem->__kmemsysWriteL2PeermemInvalidateReg__(pGpu, pKernelMemorySystem, arg0); } -static inline NV_STATUS kmemsysInitFlushSysmemBuffer_56cd7a(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { - return NV_OK; -} - NV_STATUS kmemsysInitFlushSysmemBuffer_GM107(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); NV_STATUS kmemsysInitFlushSysmemBuffer_GA100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); -NV_STATUS kmemsysInitFlushSysmemBuffer_GH100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); - static inline NV_STATUS kmemsysInitFlushSysmemBuffer_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { return pKernelMemorySystem->__kmemsysInitFlushSysmemBuffer__(pGpu, pKernelMemorySystem); } -static inline void kmemsysProgramSysmemFlushBuffer_b3696a(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { - return; -} - void kmemsysProgramSysmemFlushBuffer_GM107(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); void kmemsysProgramSysmemFlushBuffer_GA100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); @@ -603,10 +613,6 @@ static inline void kmemsysProgramSysmemFlushBuffer_DISPATCH(OBJGPU *pGpu, struct pKernelMemorySystem->__kmemsysProgramSysmemFlushBuffer__(pGpu, pKernelMemorySystem); } -static inline NvBool kmemsysIsPagePLCable_cbe027(OBJGPU *pGpu, struct KernelMemorySystem *KernelMemorySystem, NvU64 physAddr, NvU64 pageSize) { - return ((NvBool)(0 == 0)); -} - NvBool kmemsysIsPagePLCable_GA100(OBJGPU *pGpu, struct KernelMemorySystem *KernelMemorySystem, NvU64 physAddr, NvU64 pageSize); NvBool kmemsysIsPagePLCable_GA102(OBJGPU *pGpu, struct KernelMemorySystem *KernelMemorySystem, NvU64 physAddr, NvU64 pageSize); @@ -716,8 +722,10 @@ static inline NvBool kmemsysIsL2CleanFbPull(struct KernelMemorySystem *pKernelMe } void kmemsysDestruct_IMPL(struct KernelMemorySystem *pKernelMemorySystem); + #define __nvoc_kmemsysDestruct(pKernelMemorySystem) kmemsysDestruct_IMPL(pKernelMemorySystem) NV_STATUS kmemsysEnsureSysmemFlushBufferInitialized_IMPL(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); + #ifdef __nvoc_kern_mem_sys_h_disabled static inline NV_STATUS kmemsysEnsureSysmemFlushBufferInitialized(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); @@ -728,6 +736,7 @@ static inline NV_STATUS kmemsysEnsureSysmemFlushBufferInitialized(OBJGPU *pGpu, #endif //__nvoc_kern_mem_sys_h_disabled const MEMORY_SYSTEM_STATIC_CONFIG *kmemsysGetStaticConfig_IMPL(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); + #ifdef __nvoc_kern_mem_sys_h_disabled static inline const MEMORY_SYSTEM_STATIC_CONFIG *kmemsysGetStaticConfig(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); @@ -738,6 +747,7 @@ static inline const MEMORY_SYSTEM_STATIC_CONFIG *kmemsysGetStaticConfig(OBJGPU * #endif //__nvoc_kern_mem_sys_h_disabled NV_STATUS kmemsysSetupCoherentCpuLink_IMPL(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvBool bFlush); + #ifdef __nvoc_kern_mem_sys_h_disabled static inline NV_STATUS kmemsysSetupCoherentCpuLink(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvBool bFlush) { NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); @@ -748,6 +758,7 @@ static inline NV_STATUS kmemsysSetupCoherentCpuLink(OBJGPU *pGpu, struct KernelM #endif //__nvoc_kern_mem_sys_h_disabled void kmemsysTeardownCoherentCpuLink_IMPL(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvBool bFlush); + #ifdef __nvoc_kern_mem_sys_h_disabled static inline void kmemsysTeardownCoherentCpuLink(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvBool bFlush) { NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); @@ -757,6 +768,7 @@ static inline void kmemsysTeardownCoherentCpuLink(OBJGPU *pGpu, struct KernelMem #endif //__nvoc_kern_mem_sys_h_disabled NV_STATUS kmemsysSendL2InvalidateEvict_IMPL(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 flags); + #ifdef __nvoc_kern_mem_sys_h_disabled static inline NV_STATUS kmemsysSendL2InvalidateEvict(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 flags) { NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); @@ -767,6 +779,7 @@ static inline NV_STATUS kmemsysSendL2InvalidateEvict(OBJGPU *pGpu, struct Kernel #endif //__nvoc_kern_mem_sys_h_disabled NV_STATUS kmemsysSendFlushL2AllRamsAndCaches_IMPL(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); + #ifdef __nvoc_kern_mem_sys_h_disabled static inline NV_STATUS kmemsysSendFlushL2AllRamsAndCaches(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); @@ -777,6 +790,7 @@ static inline NV_STATUS kmemsysSendFlushL2AllRamsAndCaches(OBJGPU *pGpu, struct #endif //__nvoc_kern_mem_sys_h_disabled NV_STATUS kmemsysSwizzIdToMIGMemSize_IMPL(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 swizzId, struct NV_RANGE totalRange, NvU32 *pPartitionSizeFlag, NvU64 *pSizeInBytes); + #ifdef __nvoc_kern_mem_sys_h_disabled static inline NV_STATUS kmemsysSwizzIdToMIGMemSize(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 swizzId, struct NV_RANGE totalRange, NvU32 *pPartitionSizeFlag, NvU64 *pSizeInBytes) { NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); @@ -787,6 +801,7 @@ static inline NV_STATUS kmemsysSwizzIdToMIGMemSize(OBJGPU *pGpu, struct KernelMe #endif //__nvoc_kern_mem_sys_h_disabled NV_STATUS kmemsysSwizzIdToMIGMemRange_IMPL(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 swizzId, struct NV_RANGE totalRange, struct NV_RANGE *pAddrRange); + #ifdef __nvoc_kern_mem_sys_h_disabled static inline NV_STATUS kmemsysSwizzIdToMIGMemRange(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 swizzId, struct NV_RANGE totalRange, struct NV_RANGE *pAddrRange) { NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); @@ -797,6 +812,7 @@ static inline NV_STATUS kmemsysSwizzIdToMIGMemRange(OBJGPU *pGpu, struct KernelM #endif //__nvoc_kern_mem_sys_h_disabled NV_STATUS kmemsysGetMIGGPUInstanceMemInfo_IMPL(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 swizzId, struct NV_RANGE *pAddrRange); + #ifdef __nvoc_kern_mem_sys_h_disabled static inline NV_STATUS kmemsysGetMIGGPUInstanceMemInfo(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 swizzId, struct NV_RANGE *pAddrRange) { NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); @@ -807,6 +823,7 @@ static inline NV_STATUS kmemsysGetMIGGPUInstanceMemInfo(OBJGPU *pGpu, struct Ker #endif //__nvoc_kern_mem_sys_h_disabled NV_STATUS kmemsysGetMIGGPUInstanceMemConfigFromSwizzId_IMPL(OBJGPU *arg0, struct KernelMemorySystem *arg1, NvU32 swizzId, const MIG_GPU_INSTANCE_MEMORY_CONFIG **arg2); + #ifdef __nvoc_kern_mem_sys_h_disabled static inline NV_STATUS kmemsysGetMIGGPUInstanceMemConfigFromSwizzId(OBJGPU *arg0, struct KernelMemorySystem *arg1, NvU32 swizzId, const MIG_GPU_INSTANCE_MEMORY_CONFIG **arg2) { NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); @@ -817,6 +834,7 @@ static inline NV_STATUS kmemsysGetMIGGPUInstanceMemConfigFromSwizzId(OBJGPU *arg #endif //__nvoc_kern_mem_sys_h_disabled NV_STATUS kmemsysInitMIGGPUInstanceMemConfigForSwizzId_IMPL(OBJGPU *arg0, struct KernelMemorySystem *arg1, NvU32 swizzId, NvU64 startingVmmuSegment, NvU64 memSizeInVmmuSegment); + #ifdef __nvoc_kern_mem_sys_h_disabled static inline NV_STATUS kmemsysInitMIGGPUInstanceMemConfigForSwizzId(OBJGPU *arg0, struct KernelMemorySystem *arg1, NvU32 swizzId, NvU64 startingVmmuSegment, NvU64 memSizeInVmmuSegment) { NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); diff --git a/src/nvidia/generated/g_kern_perf_nvoc.c b/src/nvidia/generated/g_kern_perf_nvoc.c index f4241c426..83eced674 100644 --- a/src/nvidia/generated/g_kern_perf_nvoc.c +++ b/src/nvidia/generated/g_kern_perf_nvoc.c @@ -66,22 +66,26 @@ const struct NVOC_CLASS_DEF __nvoc_class_def_KernelPerf = /*pExportInfo=*/ &__nvoc_export_info_KernelPerf }; -static NV_STATUS __nvoc_thunk_KernelPerf_engstateConstructEngine(OBJGPU *pGpu, struct OBJENGSTATE *pKernelPerf, ENGDESCRIPTOR engDesc) { +static NV_STATUS __nvoc_thunk_KernelPerf_engstateConstructEngine(struct OBJGPU *pGpu, struct OBJENGSTATE *pKernelPerf, ENGDESCRIPTOR engDesc) { return kperfConstructEngine(pGpu, (struct KernelPerf *)(((unsigned char *)pKernelPerf) - __nvoc_rtti_KernelPerf_OBJENGSTATE.offset), engDesc); } -static NV_STATUS __nvoc_thunk_KernelPerf_engstateStateInitLocked(OBJGPU *pGpu, struct OBJENGSTATE *pKernelPerf) { +static NV_STATUS __nvoc_thunk_KernelPerf_engstateStateInitLocked(struct OBJGPU *pGpu, struct OBJENGSTATE *pKernelPerf) { return kperfStateInitLocked(pGpu, (struct KernelPerf *)(((unsigned char *)pKernelPerf) - __nvoc_rtti_KernelPerf_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_KernelPerf_engstateStateLoad(OBJGPU *pGpu, struct OBJENGSTATE *pKernelPerf, NvU32 flags) { +static NV_STATUS __nvoc_thunk_KernelPerf_engstateStateLoad(struct OBJGPU *pGpu, struct OBJENGSTATE *pKernelPerf, NvU32 flags) { return kperfStateLoad(pGpu, (struct KernelPerf *)(((unsigned char *)pKernelPerf) - __nvoc_rtti_KernelPerf_OBJENGSTATE.offset), flags); } -static NV_STATUS __nvoc_thunk_KernelPerf_engstateStateUnload(OBJGPU *pGpu, struct OBJENGSTATE *pKernelPerf, NvU32 flags) { +static NV_STATUS __nvoc_thunk_KernelPerf_engstateStateUnload(struct OBJGPU *pGpu, struct OBJENGSTATE *pKernelPerf, NvU32 flags) { return kperfStateUnload(pGpu, (struct KernelPerf *)(((unsigned char *)pKernelPerf) - __nvoc_rtti_KernelPerf_OBJENGSTATE.offset), flags); } +static void __nvoc_thunk_KernelPerf_engstateStateDestroy(struct OBJGPU *pGpu, struct OBJENGSTATE *pKernelPerf) { + kperfStateDestroy(pGpu, (struct KernelPerf *)(((unsigned char *)pKernelPerf) - __nvoc_rtti_KernelPerf_OBJENGSTATE.offset)); +} + static NV_STATUS __nvoc_thunk_OBJENGSTATE_kperfReconcileTunableState(POBJGPU pGpu, struct KernelPerf *pEngstate, void *pTunableState) { return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPerf_OBJENGSTATE.offset), pTunableState); } @@ -94,10 +98,6 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_kperfStatePostUnload(POBJGPU pGpu, str return engstateStatePostUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPerf_OBJENGSTATE.offset), arg0); } -static void __nvoc_thunk_OBJENGSTATE_kperfStateDestroy(POBJGPU pGpu, struct KernelPerf *pEngstate) { - engstateStateDestroy(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPerf_OBJENGSTATE.offset)); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kperfStatePreUnload(POBJGPU pGpu, struct KernelPerf *pEngstate, NvU32 arg0) { return engstateStatePreUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPerf_OBJENGSTATE.offset), arg0); } @@ -197,6 +197,8 @@ static void __nvoc_init_funcTable_KernelPerf_1(KernelPerf *pThis, RmHalspecOwner pThis->__kperfStateUnload__ = &kperfStateUnload_IMPL; + pThis->__kperfStateDestroy__ = &kperfStateDestroy_IMPL; + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelPerf_engstateConstructEngine; pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_thunk_KernelPerf_engstateStateInitLocked; @@ -205,14 +207,14 @@ static void __nvoc_init_funcTable_KernelPerf_1(KernelPerf *pThis, RmHalspecOwner pThis->__nvoc_base_OBJENGSTATE.__engstateStateUnload__ = &__nvoc_thunk_KernelPerf_engstateStateUnload; + pThis->__nvoc_base_OBJENGSTATE.__engstateStateDestroy__ = &__nvoc_thunk_KernelPerf_engstateStateDestroy; + pThis->__kperfReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kperfReconcileTunableState; pThis->__kperfStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_kperfStatePreLoad; pThis->__kperfStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_kperfStatePostUnload; - pThis->__kperfStateDestroy__ = &__nvoc_thunk_OBJENGSTATE_kperfStateDestroy; - pThis->__kperfStatePreUnload__ = &__nvoc_thunk_OBJENGSTATE_kperfStatePreUnload; pThis->__kperfStateInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kperfStateInitUnlocked; diff --git a/src/nvidia/generated/g_kern_perf_nvoc.h b/src/nvidia/generated/g_kern_perf_nvoc.h index 5c015d856..535603ce7 100644 --- a/src/nvidia/generated/g_kern_perf_nvoc.h +++ b/src/nvidia/generated/g_kern_perf_nvoc.h @@ -44,8 +44,6 @@ extern "C" { #include "gpu/gpu.h" #include "gpu/eng_state.h" #include "gpu/gpu_halspec.h" -#include "gpu/perf/kern_perf_boost.h" -#include "gpu/perf/kern_perf_1hz.h" #include "gpu/perf/kern_perf_gpuboostsync.h" #include "ctrl/ctrl2080/ctrl2080perf.h" @@ -74,14 +72,14 @@ struct KernelPerf { struct Object *__nvoc_pbase_Object; struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; struct KernelPerf *__nvoc_pbase_KernelPerf; - NV_STATUS (*__kperfConstructEngine__)(OBJGPU *, struct KernelPerf *, ENGDESCRIPTOR); - NV_STATUS (*__kperfStateInitLocked__)(OBJGPU *, struct KernelPerf *); - NV_STATUS (*__kperfStateLoad__)(OBJGPU *, struct KernelPerf *, NvU32); - NV_STATUS (*__kperfStateUnload__)(OBJGPU *, struct KernelPerf *, NvU32); + NV_STATUS (*__kperfConstructEngine__)(struct OBJGPU *, struct KernelPerf *, ENGDESCRIPTOR); + NV_STATUS (*__kperfStateInitLocked__)(struct OBJGPU *, struct KernelPerf *); + NV_STATUS (*__kperfStateLoad__)(struct OBJGPU *, struct KernelPerf *, NvU32); + NV_STATUS (*__kperfStateUnload__)(struct OBJGPU *, struct KernelPerf *, NvU32); + void (*__kperfStateDestroy__)(struct OBJGPU *, struct KernelPerf *); NV_STATUS (*__kperfReconcileTunableState__)(POBJGPU, struct KernelPerf *, void *); NV_STATUS (*__kperfStatePreLoad__)(POBJGPU, struct KernelPerf *, NvU32); NV_STATUS (*__kperfStatePostUnload__)(POBJGPU, struct KernelPerf *, NvU32); - void (*__kperfStateDestroy__)(POBJGPU, struct KernelPerf *); NV_STATUS (*__kperfStatePreUnload__)(POBJGPU, struct KernelPerf *, NvU32); NV_STATUS (*__kperfStateInitUnlocked__)(POBJGPU, struct KernelPerf *); void (*__kperfInitMissing__)(POBJGPU, struct KernelPerf *); @@ -96,9 +94,6 @@ struct KernelPerf { NvBool (*__kperfIsPresent__)(POBJGPU, struct KernelPerf *); struct KERNEL_PERF_GPU_BOOST_SYNC sliGpuBoostSync; NvU32 reentrancyMask; - KERNEL_PERF_BOOST_HINTS perfBoostHints; - KERNEL_PERF_1HZ timer1HzCallback; - NvU32 longestDurationIndex; }; #ifndef __NVOC_CLASS_KernelPerf_TYPEDEF__ @@ -135,10 +130,10 @@ NV_STATUS __nvoc_objCreate_KernelPerf(KernelPerf**, Dynamic*, NvU32); #define kperfStateInitLocked(pGpu, pKernelPerf) kperfStateInitLocked_DISPATCH(pGpu, pKernelPerf) #define kperfStateLoad(pGpu, pKernelPerf, flags) kperfStateLoad_DISPATCH(pGpu, pKernelPerf, flags) #define kperfStateUnload(pGpu, pKernelPerf, flags) kperfStateUnload_DISPATCH(pGpu, pKernelPerf, flags) +#define kperfStateDestroy(pGpu, pKernelPerf) kperfStateDestroy_DISPATCH(pGpu, pKernelPerf) #define kperfReconcileTunableState(pGpu, pEngstate, pTunableState) kperfReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kperfStatePreLoad(pGpu, pEngstate, arg0) kperfStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kperfStatePostUnload(pGpu, pEngstate, arg0) kperfStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) -#define kperfStateDestroy(pGpu, pEngstate) kperfStateDestroy_DISPATCH(pGpu, pEngstate) #define kperfStatePreUnload(pGpu, pEngstate, arg0) kperfStatePreUnload_DISPATCH(pGpu, pEngstate, arg0) #define kperfStateInitUnlocked(pGpu, pEngstate) kperfStateInitUnlocked_DISPATCH(pGpu, pEngstate) #define kperfInitMissing(pGpu, pEngstate) kperfInitMissing_DISPATCH(pGpu, pEngstate) @@ -151,10 +146,11 @@ NV_STATUS __nvoc_objCreate_KernelPerf(KernelPerf**, Dynamic*, NvU32); #define kperfAllocTunableState(pGpu, pEngstate, ppTunableState) kperfAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) #define kperfSetTunableState(pGpu, pEngstate, pTunableState) kperfSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kperfIsPresent(pGpu, pEngstate) kperfIsPresent_DISPATCH(pGpu, pEngstate) -NV_STATUS kperfGpuBoostSyncStateInit_IMPL(OBJGPU *pGpu, struct KernelPerf *pKernelPerf); +NV_STATUS kperfGpuBoostSyncStateInit_IMPL(struct OBJGPU *pGpu, struct KernelPerf *pKernelPerf); + #ifdef __nvoc_kern_perf_h_disabled -static inline NV_STATUS kperfGpuBoostSyncStateInit(OBJGPU *pGpu, struct KernelPerf *pKernelPerf) { +static inline NV_STATUS kperfGpuBoostSyncStateInit(struct OBJGPU *pGpu, struct KernelPerf *pKernelPerf) { NV_ASSERT_FAILED_PRECOMP("KernelPerf was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -166,6 +162,7 @@ static inline NV_STATUS kperfGpuBoostSyncStateInit(OBJGPU *pGpu, struct KernelPe NV_STATUS kperfBoostSet_3x(struct KernelPerf *pKernelPerf, struct Subdevice *pSubdevice, NV2080_CTRL_PERF_BOOST_PARAMS *pBoostParams); + #ifdef __nvoc_kern_perf_h_disabled static inline NV_STATUS kperfBoostSet(struct KernelPerf *pKernelPerf, struct Subdevice *pSubdevice, NV2080_CTRL_PERF_BOOST_PARAMS *pBoostParams) { NV_ASSERT_FAILED_PRECOMP("KernelPerf was disabled!"); @@ -177,30 +174,36 @@ static inline NV_STATUS kperfBoostSet(struct KernelPerf *pKernelPerf, struct Sub #define kperfBoostSet_HAL(pKernelPerf, pSubdevice, pBoostParams) kperfBoostSet(pKernelPerf, pSubdevice, pBoostParams) -NV_STATUS kperfConstructEngine_IMPL(OBJGPU *pGpu, struct KernelPerf *pKernelPerf, ENGDESCRIPTOR engDesc); +NV_STATUS kperfConstructEngine_IMPL(struct OBJGPU *pGpu, struct KernelPerf *pKernelPerf, ENGDESCRIPTOR engDesc); -static inline NV_STATUS kperfConstructEngine_DISPATCH(OBJGPU *pGpu, struct KernelPerf *pKernelPerf, ENGDESCRIPTOR engDesc) { +static inline NV_STATUS kperfConstructEngine_DISPATCH(struct OBJGPU *pGpu, struct KernelPerf *pKernelPerf, ENGDESCRIPTOR engDesc) { return pKernelPerf->__kperfConstructEngine__(pGpu, pKernelPerf, engDesc); } -NV_STATUS kperfStateInitLocked_IMPL(OBJGPU *pGpu, struct KernelPerf *pKernelPerf); +NV_STATUS kperfStateInitLocked_IMPL(struct OBJGPU *pGpu, struct KernelPerf *pKernelPerf); -static inline NV_STATUS kperfStateInitLocked_DISPATCH(OBJGPU *pGpu, struct KernelPerf *pKernelPerf) { +static inline NV_STATUS kperfStateInitLocked_DISPATCH(struct OBJGPU *pGpu, struct KernelPerf *pKernelPerf) { return pKernelPerf->__kperfStateInitLocked__(pGpu, pKernelPerf); } -NV_STATUS kperfStateLoad_IMPL(OBJGPU *pGpu, struct KernelPerf *pKernelPerf, NvU32 flags); +NV_STATUS kperfStateLoad_IMPL(struct OBJGPU *pGpu, struct KernelPerf *pKernelPerf, NvU32 flags); -static inline NV_STATUS kperfStateLoad_DISPATCH(OBJGPU *pGpu, struct KernelPerf *pKernelPerf, NvU32 flags) { +static inline NV_STATUS kperfStateLoad_DISPATCH(struct OBJGPU *pGpu, struct KernelPerf *pKernelPerf, NvU32 flags) { return pKernelPerf->__kperfStateLoad__(pGpu, pKernelPerf, flags); } -NV_STATUS kperfStateUnload_IMPL(OBJGPU *pGpu, struct KernelPerf *pKernelPerf, NvU32 flags); +NV_STATUS kperfStateUnload_IMPL(struct OBJGPU *pGpu, struct KernelPerf *pKernelPerf, NvU32 flags); -static inline NV_STATUS kperfStateUnload_DISPATCH(OBJGPU *pGpu, struct KernelPerf *pKernelPerf, NvU32 flags) { +static inline NV_STATUS kperfStateUnload_DISPATCH(struct OBJGPU *pGpu, struct KernelPerf *pKernelPerf, NvU32 flags) { return pKernelPerf->__kperfStateUnload__(pGpu, pKernelPerf, flags); } +void kperfStateDestroy_IMPL(struct OBJGPU *pGpu, struct KernelPerf *pKernelPerf); + +static inline void kperfStateDestroy_DISPATCH(struct OBJGPU *pGpu, struct KernelPerf *pKernelPerf) { + pKernelPerf->__kperfStateDestroy__(pGpu, pKernelPerf); +} + static inline NV_STATUS kperfReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelPerf *pEngstate, void *pTunableState) { return pEngstate->__kperfReconcileTunableState__(pGpu, pEngstate, pTunableState); } @@ -213,10 +216,6 @@ static inline NV_STATUS kperfStatePostUnload_DISPATCH(POBJGPU pGpu, struct Kerne return pEngstate->__kperfStatePostUnload__(pGpu, pEngstate, arg0); } -static inline void kperfStateDestroy_DISPATCH(POBJGPU pGpu, struct KernelPerf *pEngstate) { - pEngstate->__kperfStateDestroy__(pGpu, pEngstate); -} - static inline NV_STATUS kperfStatePreUnload_DISPATCH(POBJGPU pGpu, struct KernelPerf *pEngstate, NvU32 arg0) { return pEngstate->__kperfStatePreUnload__(pGpu, pEngstate, arg0); } @@ -265,9 +264,10 @@ static inline NvBool kperfIsPresent_DISPATCH(POBJGPU pGpu, struct KernelPerf *pE return pEngstate->__kperfIsPresent__(pGpu, pEngstate); } -NV_STATUS kperfBoostStateInit_IMPL(OBJGPU *pGpu, struct KernelPerf *pKernelPerf); +NV_STATUS kperfBoostStateInit_IMPL(struct OBJGPU *pGpu, struct KernelPerf *pKernelPerf); + #ifdef __nvoc_kern_perf_h_disabled -static inline NV_STATUS kperfBoostStateInit(OBJGPU *pGpu, struct KernelPerf *pKernelPerf) { +static inline NV_STATUS kperfBoostStateInit(struct OBJGPU *pGpu, struct KernelPerf *pKernelPerf) { NV_ASSERT_FAILED_PRECOMP("KernelPerf was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -275,9 +275,10 @@ static inline NV_STATUS kperfBoostStateInit(OBJGPU *pGpu, struct KernelPerf *pKe #define kperfBoostStateInit(pGpu, pKernelPerf) kperfBoostStateInit_IMPL(pGpu, pKernelPerf) #endif //__nvoc_kern_perf_h_disabled -NV_STATUS kperfGpuBoostSyncActivate_IMPL(OBJGPU *pGpu, struct KernelPerf *pKernelPerf, NvBool bActivate); +NV_STATUS kperfGpuBoostSyncActivate_IMPL(struct OBJGPU *pGpu, struct KernelPerf *pKernelPerf, NvBool bActivate); + #ifdef __nvoc_kern_perf_h_disabled -static inline NV_STATUS kperfGpuBoostSyncActivate(OBJGPU *pGpu, struct KernelPerf *pKernelPerf, NvBool bActivate) { +static inline NV_STATUS kperfGpuBoostSyncActivate(struct OBJGPU *pGpu, struct KernelPerf *pKernelPerf, NvBool bActivate) { NV_ASSERT_FAILED_PRECOMP("KernelPerf was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -285,9 +286,10 @@ static inline NV_STATUS kperfGpuBoostSyncActivate(OBJGPU *pGpu, struct KernelPer #define kperfGpuBoostSyncActivate(pGpu, pKernelPerf, bActivate) kperfGpuBoostSyncActivate_IMPL(pGpu, pKernelPerf, bActivate) #endif //__nvoc_kern_perf_h_disabled -NV_STATUS kperfDoSyncGpuBoostLimits_IMPL(OBJGPU *pGpu, struct KernelPerf *pKernelPerf, NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS *pParams); +NV_STATUS kperfDoSyncGpuBoostLimits_IMPL(struct OBJGPU *pGpu, struct KernelPerf *pKernelPerf, NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS *pParams); + #ifdef __nvoc_kern_perf_h_disabled -static inline NV_STATUS kperfDoSyncGpuBoostLimits(OBJGPU *pGpu, struct KernelPerf *pKernelPerf, NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS *pParams) { +static inline NV_STATUS kperfDoSyncGpuBoostLimits(struct OBJGPU *pGpu, struct KernelPerf *pKernelPerf, NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS *pParams) { NV_ASSERT_FAILED_PRECOMP("KernelPerf was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -295,9 +297,10 @@ static inline NV_STATUS kperfDoSyncGpuBoostLimits(OBJGPU *pGpu, struct KernelPer #define kperfDoSyncGpuBoostLimits(pGpu, pKernelPerf, pParams) kperfDoSyncGpuBoostLimits_IMPL(pGpu, pKernelPerf, pParams) #endif //__nvoc_kern_perf_h_disabled -NV_STATUS kperfReentrancy_IMPL(OBJGPU *pGpu, struct KernelPerf *pKernelPerf, NvU32 function, NvBool bSet); +NV_STATUS kperfReentrancy_IMPL(struct OBJGPU *pGpu, struct KernelPerf *pKernelPerf, NvU32 function, NvBool bSet); + #ifdef __nvoc_kern_perf_h_disabled -static inline NV_STATUS kperfReentrancy(OBJGPU *pGpu, struct KernelPerf *pKernelPerf, NvU32 function, NvBool bSet) { +static inline NV_STATUS kperfReentrancy(struct OBJGPU *pGpu, struct KernelPerf *pKernelPerf, NvU32 function, NvBool bSet) { NV_ASSERT_FAILED_PRECOMP("KernelPerf was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -305,24 +308,6 @@ static inline NV_STATUS kperfReentrancy(OBJGPU *pGpu, struct KernelPerf *pKernel #define kperfReentrancy(pGpu, pKernelPerf, function, bSet) kperfReentrancy_IMPL(pGpu, pKernelPerf, function, bSet) #endif //__nvoc_kern_perf_h_disabled -void kperfTimer1HzCallback_IMPL(OBJGPU *pGpu, struct KernelPerf *pKernelPerf); -#ifdef __nvoc_kern_perf_h_disabled -static inline void kperfTimer1HzCallback(OBJGPU *pGpu, struct KernelPerf *pKernelPerf) { - NV_ASSERT_FAILED_PRECOMP("KernelPerf was disabled!"); -} -#else //__nvoc_kern_perf_h_disabled -#define kperfTimer1HzCallback(pGpu, pKernelPerf) kperfTimer1HzCallback_IMPL(pGpu, pKernelPerf) -#endif //__nvoc_kern_perf_h_disabled - -void kperfBoostHintCallback_IMPL(OBJGPU *pGpu, struct KernelPerf *pKernelPerf); -#ifdef __nvoc_kern_perf_h_disabled -static inline void kperfBoostHintCallback(OBJGPU *pGpu, struct KernelPerf *pKernelPerf) { - NV_ASSERT_FAILED_PRECOMP("KernelPerf was disabled!"); -} -#else //__nvoc_kern_perf_h_disabled -#define kperfBoostHintCallback(pGpu, pKernelPerf) kperfBoostHintCallback_IMPL(pGpu, pKernelPerf) -#endif //__nvoc_kern_perf_h_disabled - #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_kern_perfbuffer_nvoc.c b/src/nvidia/generated/g_kern_perfbuffer_nvoc.c index 5656f4166..e26af1a6c 100644 --- a/src/nvidia/generated/g_kern_perfbuffer_nvoc.c +++ b/src/nvidia/generated/g_kern_perfbuffer_nvoc.c @@ -165,6 +165,10 @@ static NV_STATUS __nvoc_thunk_RsResource_perfbufferUnmapFrom(struct PerfBuffer * return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_perfbufferIsDuplicate(struct PerfBuffer *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_perfbufferControl_Epilogue(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RmResource.offset), pCallContext, pParams); } @@ -266,6 +270,8 @@ static void __nvoc_init_funcTable_PerfBuffer_1(PerfBuffer *pThis, RmHalspecOwner pThis->__perfbufferUnmapFrom__ = &__nvoc_thunk_RsResource_perfbufferUnmapFrom; + pThis->__perfbufferIsDuplicate__ = &__nvoc_thunk_RsResource_perfbufferIsDuplicate; + pThis->__perfbufferControl_Epilogue__ = &__nvoc_thunk_RmResource_perfbufferControl_Epilogue; pThis->__perfbufferControlLookup__ = &__nvoc_thunk_RsResource_perfbufferControlLookup; diff --git a/src/nvidia/generated/g_kern_perfbuffer_nvoc.h b/src/nvidia/generated/g_kern_perfbuffer_nvoc.h index 2f0dccd41..d7660022a 100644 --- a/src/nvidia/generated/g_kern_perfbuffer_nvoc.h +++ b/src/nvidia/generated/g_kern_perfbuffer_nvoc.h @@ -73,6 +73,7 @@ struct PerfBuffer { NV_STATUS (*__perfbufferInternalControlForward__)(struct PerfBuffer *, NvU32, void *, NvU32); void (*__perfbufferPreDestruct__)(struct PerfBuffer *); NV_STATUS (*__perfbufferUnmapFrom__)(struct PerfBuffer *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__perfbufferIsDuplicate__)(struct PerfBuffer *, NvHandle, NvBool *); void (*__perfbufferControl_Epilogue__)(struct PerfBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__perfbufferControlLookup__)(struct PerfBuffer *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__perfbufferMap__)(struct PerfBuffer *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -126,12 +127,14 @@ NV_STATUS __nvoc_objCreate_PerfBuffer(PerfBuffer**, Dynamic*, NvU32, struct CALL #define perfbufferInternalControlForward(pGpuResource, command, pParams, size) perfbufferInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define perfbufferPreDestruct(pResource) perfbufferPreDestruct_DISPATCH(pResource) #define perfbufferUnmapFrom(pResource, pParams) perfbufferUnmapFrom_DISPATCH(pResource, pParams) +#define perfbufferIsDuplicate(pResource, hMemory, pDuplicate) perfbufferIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define perfbufferControl_Epilogue(pResource, pCallContext, pParams) perfbufferControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define perfbufferControlLookup(pResource, pParams, ppEntry) perfbufferControlLookup_DISPATCH(pResource, pParams, ppEntry) #define perfbufferMap(pGpuResource, pCallContext, pParams, pCpuMapping) perfbufferMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define perfbufferAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) perfbufferAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS perfbufferConstructHal_KERNEL(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); + #ifdef __nvoc_kern_perfbuffer_h_disabled static inline NV_STATUS perfbufferConstructHal(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { NV_ASSERT_FAILED_PRECOMP("PerfBuffer was disabled!"); @@ -147,6 +150,7 @@ static inline void perfbufferDestruct_b3696a(struct PerfBuffer *pResource) { return; } + #define __nvoc_perfbufferDestruct(pResource) perfbufferDestruct_b3696a(pResource) static inline NvBool perfbufferShareCallback_DISPATCH(struct PerfBuffer *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pGpuResource->__perfbufferShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); @@ -220,6 +224,10 @@ static inline NV_STATUS perfbufferUnmapFrom_DISPATCH(struct PerfBuffer *pResourc return pResource->__perfbufferUnmapFrom__(pResource, pParams); } +static inline NV_STATUS perfbufferIsDuplicate_DISPATCH(struct PerfBuffer *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__perfbufferIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void perfbufferControl_Epilogue_DISPATCH(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__perfbufferControl_Epilogue__(pResource, pCallContext, pParams); } @@ -241,6 +249,7 @@ static inline NV_STATUS __nvoc_perfbufferConstruct(struct PerfBuffer *arg_pResou } NV_STATUS perfbufferPrivilegeCheck_IMPL(struct PerfBuffer *pPerfBuffer); + #ifdef __nvoc_kern_perfbuffer_h_disabled static inline NV_STATUS perfbufferPrivilegeCheck(struct PerfBuffer *pPerfBuffer) { NV_ASSERT_FAILED_PRECOMP("PerfBuffer was disabled!"); diff --git a/src/nvidia/generated/g_kern_pmu_nvoc.c b/src/nvidia/generated/g_kern_pmu_nvoc.c index 4820c1961..662941ab5 100644 --- a/src/nvidia/generated/g_kern_pmu_nvoc.c +++ b/src/nvidia/generated/g_kern_pmu_nvoc.c @@ -17,10 +17,10 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJENGSTATE; -void __nvoc_init_KernelPmu(KernelPmu*); -void __nvoc_init_funcTable_KernelPmu(KernelPmu*); -NV_STATUS __nvoc_ctor_KernelPmu(KernelPmu*); -void __nvoc_init_dataField_KernelPmu(KernelPmu*); +void __nvoc_init_KernelPmu(KernelPmu*, RmHalspecOwner* ); +void __nvoc_init_funcTable_KernelPmu(KernelPmu*, RmHalspecOwner* ); +NV_STATUS __nvoc_ctor_KernelPmu(KernelPmu*, RmHalspecOwner* ); +void __nvoc_init_dataField_KernelPmu(KernelPmu*, RmHalspecOwner* ); void __nvoc_dtor_KernelPmu(KernelPmu*); extern const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelPmu; @@ -70,6 +70,10 @@ static NV_STATUS __nvoc_thunk_KernelPmu_engstateConstructEngine(struct OBJGPU *p return kpmuConstructEngine(pGpu, (struct KernelPmu *)(((unsigned char *)pKernelPmu) - __nvoc_rtti_KernelPmu_OBJENGSTATE.offset), engDesc); } +static NV_STATUS __nvoc_thunk_KernelPmu_engstateStateInitLocked(struct OBJGPU *pGpu, struct OBJENGSTATE *pKernelPmu) { + return kpmuStateInitLocked(pGpu, (struct KernelPmu *)(((unsigned char *)pKernelPmu) - __nvoc_rtti_KernelPmu_OBJENGSTATE.offset)); +} + static NV_STATUS __nvoc_thunk_OBJENGSTATE_kpmuReconcileTunableState(POBJGPU pGpu, struct KernelPmu *pEngstate, void *pTunableState) { return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPmu_OBJENGSTATE.offset), pTunableState); } @@ -82,10 +86,6 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_kpmuStateUnload(POBJGPU pGpu, struct K return engstateStateUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPmu_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kpmuStateInitLocked(POBJGPU pGpu, struct KernelPmu *pEngstate) { - return engstateStateInitLocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPmu_OBJENGSTATE.offset)); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kpmuStatePreLoad(POBJGPU pGpu, struct KernelPmu *pEngstate, NvU32 arg0) { return engstateStatePreLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPmu_OBJENGSTATE.offset), arg0); } @@ -159,16 +159,21 @@ void __nvoc_dtor_KernelPmu(KernelPmu *pThis) { PORT_UNREFERENCED_VARIABLE(pThis); } -void __nvoc_init_dataField_KernelPmu(KernelPmu *pThis) { +void __nvoc_init_dataField_KernelPmu(KernelPmu *pThis, RmHalspecOwner *pRmhalspecowner) { + ChipHal *chipHal = &pRmhalspecowner->chipHal; + const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(chipHal); + PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); } NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); -NV_STATUS __nvoc_ctor_KernelPmu(KernelPmu *pThis) { +NV_STATUS __nvoc_ctor_KernelPmu(KernelPmu *pThis, RmHalspecOwner *pRmhalspecowner) { NV_STATUS status = NV_OK; status = __nvoc_ctor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); if (status != NV_OK) goto __nvoc_ctor_KernelPmu_fail_OBJENGSTATE; - __nvoc_init_dataField_KernelPmu(pThis); + __nvoc_init_dataField_KernelPmu(pThis, pRmhalspecowner); goto __nvoc_ctor_KernelPmu_exit; // Success __nvoc_ctor_KernelPmu_fail_OBJENGSTATE: @@ -177,21 +182,39 @@ __nvoc_ctor_KernelPmu_exit: return status; } -static void __nvoc_init_funcTable_KernelPmu_1(KernelPmu *pThis) { +static void __nvoc_init_funcTable_KernelPmu_1(KernelPmu *pThis, RmHalspecOwner *pRmhalspecowner) { + ChipHal *chipHal = &pRmhalspecowner->chipHal; + const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(chipHal); + PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); pThis->__kpmuConstructEngine__ = &kpmuConstructEngine_IMPL; + pThis->__kpmuStateInitLocked__ = &kpmuStateInitLocked_IMPL; + + // Hal function -- kpmuPreOsGlobalErotGrantRequest + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__kpmuPreOsGlobalErotGrantRequest__ = &kpmuPreOsGlobalErotGrantRequest_AD102; + } + // default + else + { + pThis->__kpmuPreOsGlobalErotGrantRequest__ = &kpmuPreOsGlobalErotGrantRequest_56cd7a; + } + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelPmu_engstateConstructEngine; + pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_thunk_KernelPmu_engstateStateInitLocked; + pThis->__kpmuReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kpmuReconcileTunableState; pThis->__kpmuStateLoad__ = &__nvoc_thunk_OBJENGSTATE_kpmuStateLoad; pThis->__kpmuStateUnload__ = &__nvoc_thunk_OBJENGSTATE_kpmuStateUnload; - pThis->__kpmuStateInitLocked__ = &__nvoc_thunk_OBJENGSTATE_kpmuStateInitLocked; - pThis->__kpmuStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_kpmuStatePreLoad; pThis->__kpmuStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_kpmuStatePostUnload; @@ -223,23 +246,24 @@ static void __nvoc_init_funcTable_KernelPmu_1(KernelPmu *pThis) { pThis->__kpmuIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kpmuIsPresent; } -void __nvoc_init_funcTable_KernelPmu(KernelPmu *pThis) { - __nvoc_init_funcTable_KernelPmu_1(pThis); +void __nvoc_init_funcTable_KernelPmu(KernelPmu *pThis, RmHalspecOwner *pRmhalspecowner) { + __nvoc_init_funcTable_KernelPmu_1(pThis, pRmhalspecowner); } void __nvoc_init_OBJENGSTATE(OBJENGSTATE*); -void __nvoc_init_KernelPmu(KernelPmu *pThis) { +void __nvoc_init_KernelPmu(KernelPmu *pThis, RmHalspecOwner *pRmhalspecowner) { pThis->__nvoc_pbase_KernelPmu = pThis; pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object; pThis->__nvoc_pbase_OBJENGSTATE = &pThis->__nvoc_base_OBJENGSTATE; __nvoc_init_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); - __nvoc_init_funcTable_KernelPmu(pThis); + __nvoc_init_funcTable_KernelPmu(pThis, pRmhalspecowner); } NV_STATUS __nvoc_objCreate_KernelPmu(KernelPmu **ppThis, Dynamic *pParent, NvU32 createFlags) { NV_STATUS status; Object *pParentObj; KernelPmu *pThis; + RmHalspecOwner *pRmhalspecowner; pThis = portMemAllocNonPaged(sizeof(KernelPmu)); if (pThis == NULL) return NV_ERR_NO_MEMORY; @@ -258,8 +282,12 @@ NV_STATUS __nvoc_objCreate_KernelPmu(KernelPmu **ppThis, Dynamic *pParent, NvU32 pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.pParent = NULL; } - __nvoc_init_KernelPmu(pThis); - status = __nvoc_ctor_KernelPmu(pThis); + if ((pRmhalspecowner = dynamicCast(pParent, RmHalspecOwner)) == NULL) + pRmhalspecowner = objFindAncestorOfType(RmHalspecOwner, pParent); + NV_ASSERT_OR_RETURN(pRmhalspecowner != NULL, NV_ERR_INVALID_ARGUMENT); + + __nvoc_init_KernelPmu(pThis, pRmhalspecowner); + status = __nvoc_ctor_KernelPmu(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_KernelPmu_cleanup; *ppThis = pThis; diff --git a/src/nvidia/generated/g_kern_pmu_nvoc.h b/src/nvidia/generated/g_kern_pmu_nvoc.h index f3f65a252..c146573e1 100644 --- a/src/nvidia/generated/g_kern_pmu_nvoc.h +++ b/src/nvidia/generated/g_kern_pmu_nvoc.h @@ -43,7 +43,7 @@ extern "C" { #include "gpu/gpu.h" #include "gpu/eng_state.h" -#include "logdecode.h" +#include "liblogdecode.h" #define PMU_LOG_BUFFER_MAX_SIZE 0x1000 @@ -65,10 +65,11 @@ struct KernelPmu { struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; struct KernelPmu *__nvoc_pbase_KernelPmu; NV_STATUS (*__kpmuConstructEngine__)(struct OBJGPU *, struct KernelPmu *, ENGDESCRIPTOR); + NV_STATUS (*__kpmuStateInitLocked__)(struct OBJGPU *, struct KernelPmu *); + NV_STATUS (*__kpmuPreOsGlobalErotGrantRequest__)(struct OBJGPU *, struct KernelPmu *); NV_STATUS (*__kpmuReconcileTunableState__)(POBJGPU, struct KernelPmu *, void *); NV_STATUS (*__kpmuStateLoad__)(POBJGPU, struct KernelPmu *, NvU32); NV_STATUS (*__kpmuStateUnload__)(POBJGPU, struct KernelPmu *, NvU32); - NV_STATUS (*__kpmuStateInitLocked__)(POBJGPU, struct KernelPmu *); NV_STATUS (*__kpmuStatePreLoad__)(POBJGPU, struct KernelPmu *, NvU32); NV_STATUS (*__kpmuStatePostUnload__)(POBJGPU, struct KernelPmu *, NvU32); void (*__kpmuStateDestroy__)(POBJGPU, struct KernelPmu *); @@ -88,6 +89,7 @@ struct KernelPmu { NvU32 printBufSize; NvU8 *pPrintBuf; void *pLogElf; + NvU32 logElfSize; }; #ifndef __NVOC_CLASS_KernelPmu_TYPEDEF__ @@ -121,10 +123,12 @@ NV_STATUS __nvoc_objCreate_KernelPmu(KernelPmu**, Dynamic*, NvU32); __nvoc_objCreate_KernelPmu((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) #define kpmuConstructEngine(pGpu, pKernelPmu, engDesc) kpmuConstructEngine_DISPATCH(pGpu, pKernelPmu, engDesc) +#define kpmuStateInitLocked(pGpu, pKernelPmu) kpmuStateInitLocked_DISPATCH(pGpu, pKernelPmu) +#define kpmuPreOsGlobalErotGrantRequest(pGpu, pKernelPmu) kpmuPreOsGlobalErotGrantRequest_DISPATCH(pGpu, pKernelPmu) +#define kpmuPreOsGlobalErotGrantRequest_HAL(pGpu, pKernelPmu) kpmuPreOsGlobalErotGrantRequest_DISPATCH(pGpu, pKernelPmu) #define kpmuReconcileTunableState(pGpu, pEngstate, pTunableState) kpmuReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kpmuStateLoad(pGpu, pEngstate, arg0) kpmuStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kpmuStateUnload(pGpu, pEngstate, arg0) kpmuStateUnload_DISPATCH(pGpu, pEngstate, arg0) -#define kpmuStateInitLocked(pGpu, pEngstate) kpmuStateInitLocked_DISPATCH(pGpu, pEngstate) #define kpmuStatePreLoad(pGpu, pEngstate, arg0) kpmuStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kpmuStatePostUnload(pGpu, pEngstate, arg0) kpmuStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) #define kpmuStateDestroy(pGpu, pEngstate) kpmuStateDestroy_DISPATCH(pGpu, pEngstate) @@ -146,6 +150,22 @@ static inline NV_STATUS kpmuConstructEngine_DISPATCH(struct OBJGPU *pGpu, struct return pKernelPmu->__kpmuConstructEngine__(pGpu, pKernelPmu, engDesc); } +NV_STATUS kpmuStateInitLocked_IMPL(struct OBJGPU *pGpu, struct KernelPmu *pKernelPmu); + +static inline NV_STATUS kpmuStateInitLocked_DISPATCH(struct OBJGPU *pGpu, struct KernelPmu *pKernelPmu) { + return pKernelPmu->__kpmuStateInitLocked__(pGpu, pKernelPmu); +} + +NV_STATUS kpmuPreOsGlobalErotGrantRequest_AD102(struct OBJGPU *pGpu, struct KernelPmu *pKernelPmu); + +static inline NV_STATUS kpmuPreOsGlobalErotGrantRequest_56cd7a(struct OBJGPU *pGpu, struct KernelPmu *pKernelPmu) { + return NV_OK; +} + +static inline NV_STATUS kpmuPreOsGlobalErotGrantRequest_DISPATCH(struct OBJGPU *pGpu, struct KernelPmu *pKernelPmu) { + return pKernelPmu->__kpmuPreOsGlobalErotGrantRequest__(pGpu, pKernelPmu); +} + static inline NV_STATUS kpmuReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelPmu *pEngstate, void *pTunableState) { return pEngstate->__kpmuReconcileTunableState__(pGpu, pEngstate, pTunableState); } @@ -158,10 +178,6 @@ static inline NV_STATUS kpmuStateUnload_DISPATCH(POBJGPU pGpu, struct KernelPmu return pEngstate->__kpmuStateUnload__(pGpu, pEngstate, arg0); } -static inline NV_STATUS kpmuStateInitLocked_DISPATCH(POBJGPU pGpu, struct KernelPmu *pEngstate) { - return pEngstate->__kpmuStateInitLocked__(pGpu, pEngstate); -} - static inline NV_STATUS kpmuStatePreLoad_DISPATCH(POBJGPU pGpu, struct KernelPmu *pEngstate, NvU32 arg0) { return pEngstate->__kpmuStatePreLoad__(pGpu, pEngstate, arg0); } @@ -223,8 +239,10 @@ static inline NvBool kpmuIsPresent_DISPATCH(POBJGPU pGpu, struct KernelPmu *pEng } void kpmuDestruct_IMPL(struct KernelPmu *pKernelPmu); + #define __nvoc_kpmuDestruct(pKernelPmu) kpmuDestruct_IMPL(pKernelPmu) NV_STATUS kpmuInitLibosLoggingStructures_IMPL(struct OBJGPU *pGpu, struct KernelPmu *pKernelPmu); + #ifdef __nvoc_kern_pmu_h_disabled static inline NV_STATUS kpmuInitLibosLoggingStructures(struct OBJGPU *pGpu, struct KernelPmu *pKernelPmu) { NV_ASSERT_FAILED_PRECOMP("KernelPmu was disabled!"); @@ -235,6 +253,7 @@ static inline NV_STATUS kpmuInitLibosLoggingStructures(struct OBJGPU *pGpu, stru #endif //__nvoc_kern_pmu_h_disabled void kpmuFreeLibosLoggingStructures_IMPL(struct OBJGPU *pGpu, struct KernelPmu *pKernelPmu); + #ifdef __nvoc_kern_pmu_h_disabled static inline void kpmuFreeLibosLoggingStructures(struct OBJGPU *pGpu, struct KernelPmu *pKernelPmu) { NV_ASSERT_FAILED_PRECOMP("KernelPmu was disabled!"); @@ -244,6 +263,7 @@ static inline void kpmuFreeLibosLoggingStructures(struct OBJGPU *pGpu, struct Ke #endif //__nvoc_kern_pmu_h_disabled void kpmuLogBuf_IMPL(struct OBJGPU *pGpu, struct KernelPmu *pKernelPmu, NvU8 *pBuf, NvU32 bufSize); + #ifdef __nvoc_kern_pmu_h_disabled static inline void kpmuLogBuf(struct OBJGPU *pGpu, struct KernelPmu *pKernelPmu, NvU8 *pBuf, NvU32 bufSize) { NV_ASSERT_FAILED_PRECOMP("KernelPmu was disabled!"); diff --git a/src/nvidia/generated/g_kernel_bif_nvoc.c b/src/nvidia/generated/g_kernel_bif_nvoc.c index d503a910d..7370f1ea9 100644 --- a/src/nvidia/generated/g_kernel_bif_nvoc.c +++ b/src/nvidia/generated/g_kernel_bif_nvoc.c @@ -171,18 +171,13 @@ void __nvoc_init_dataField_KernelBif(KernelBif *pThis, RmHalspecOwner *pRmhalspe PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // NVOC Property Hal field -- PDB_PROP_KBIF_CHECK_IF_GPU_EXISTS_DEF - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_KBIF_CHECK_IF_GPU_EXISTS_DEF, ((NvBool)(0 == 0))); } - // default - else - { - pThis->setProperty(pThis, PDB_PROP_KBIF_CHECK_IF_GPU_EXISTS_DEF, ((NvBool)(0 != 0))); - } // NVOC Property Hal field -- PDB_PROP_KBIF_IS_FMODEL_MSI_BROKEN - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->setProperty(pThis, PDB_PROP_KBIF_IS_FMODEL_MSI_BROKEN, ((NvBool)(0 == 0))); } @@ -193,7 +188,7 @@ void __nvoc_init_dataField_KernelBif(KernelBif *pThis, RmHalspecOwner *pRmhalspe } // NVOC Property Hal field -- PDB_PROP_KBIF_USE_CONFIG_SPACE_TO_REARM_MSI - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->setProperty(pThis, PDB_PROP_KBIF_USE_CONFIG_SPACE_TO_REARM_MSI, ((NvBool)(0 != 0))); } @@ -204,27 +199,19 @@ void __nvoc_init_dataField_KernelBif(KernelBif *pThis, RmHalspecOwner *pRmhalspe } // NVOC Property Hal field -- PDB_PROP_KBIF_P2P_READS_DISABLED - if (0) - { - } // default - else { pThis->setProperty(pThis, PDB_PROP_KBIF_P2P_READS_DISABLED, ((NvBool)(0 != 0))); } // NVOC Property Hal field -- PDB_PROP_KBIF_P2P_WRITES_DISABLED - if (0) - { - } // default - else { pThis->setProperty(pThis, PDB_PROP_KBIF_P2P_WRITES_DISABLED, ((NvBool)(0 != 0))); } // NVOC Property Hal field -- PDB_PROP_KBIF_UPSTREAM_LTR_SUPPORT_WAR_BUG_200634944 - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_KBIF_UPSTREAM_LTR_SUPPORT_WAR_BUG_200634944, ((NvBool)(0 == 0))); } @@ -267,207 +254,153 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner * pThis->__kbifStateInitLocked__ = &kbifStateInitLocked_IMPL; // Hal function -- kbifStateLoad - if (0) - { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { pThis->__kbifStateLoad__ = &kbifStateLoad_IMPL; } // Hal function -- kbifStatePostLoad - if (0) - { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { pThis->__kbifStatePostLoad__ = &kbifStatePostLoad_IMPL; } // Hal function -- kbifStateUnload - if (0) - { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { pThis->__kbifStateUnload__ = &kbifStateUnload_IMPL; } // Hal function -- kbifGetXveStatusBits - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbifGetXveStatusBits__ = &kbifGetXveStatusBits_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbifGetXveStatusBits__ = &kbifGetXveStatusBits_GH100; } - else if (0) - { - } // Hal function -- kbifClearXveStatus - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbifClearXveStatus__ = &kbifClearXveStatus_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbifClearXveStatus__ = &kbifClearXveStatus_GH100; } - else if (0) - { - } // Hal function -- kbifGetXveAerBits - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbifGetXveAerBits__ = &kbifGetXveAerBits_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbifGetXveAerBits__ = &kbifGetXveAerBits_GH100; } - else if (0) - { - } // Hal function -- kbifClearXveAer - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbifClearXveAer__ = &kbifClearXveAer_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbifClearXveAer__ = &kbifClearXveAer_GH100; } - else if (0) - { - } // Hal function -- kbifGetPcieConfigAccessTestRegisters - if (0) + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbifGetPcieConfigAccessTestRegisters__ = &kbifGetPcieConfigAccessTestRegisters_GM107; } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbifGetPcieConfigAccessTestRegisters__ = &kbifGetPcieConfigAccessTestRegisters_b3696a; } } // Hal function -- kbifVerifyPcieConfigAccessTestRegisters - if (0) + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbifVerifyPcieConfigAccessTestRegisters__ = &kbifVerifyPcieConfigAccessTestRegisters_GM107; } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbifVerifyPcieConfigAccessTestRegisters__ = &kbifVerifyPcieConfigAccessTestRegisters_46f6a7; } } // Hal function -- kbifRearmMSI - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbifRearmMSI__ = &kbifRearmMSI_GM107; } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbifRearmMSI__ = &kbifRearmMSI_f2d351; } - else if (0) - { - } // Hal function -- kbifIsMSIEnabledInHW - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbifIsMSIEnabledInHW__ = &kbifIsMSIEnabledInHW_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbifIsMSIEnabledInHW__ = &kbifIsMSIEnabledInHW_GH100; } - else if (0) - { - } // Hal function -- kbifIsMSIXEnabledInHW - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbifIsMSIXEnabledInHW__ = &kbifIsMSIXEnabledInHW_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbifIsMSIXEnabledInHW__ = &kbifIsMSIXEnabledInHW_GH100; } - else if (0) - { - } // Hal function -- kbifIsPciIoAccessEnabled - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbifIsPciIoAccessEnabled__ = &kbifIsPciIoAccessEnabled_GM107; } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kbifIsPciIoAccessEnabled__ = &kbifIsPciIoAccessEnabled_491d52; } // Hal function -- kbifIs3dController - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbifIs3dController__ = &kbifIs3dController_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbifIs3dController__ = &kbifIs3dController_GH100; } - else if (0) - { - } // Hal function -- kbifExecC73War - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbifExecC73War__ = &kbifExecC73War_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbifExecC73War__ = &kbifExecC73War_b3696a; } // Hal function -- kbifEnableExtendedTagSupport - if (0) + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbifEnableExtendedTagSupport__ = &kbifEnableExtendedTagSupport_GH100; } @@ -479,48 +412,33 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner * } // Hal function -- kbifPcieConfigEnableRelaxedOrdering - if (0) + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbifPcieConfigEnableRelaxedOrdering__ = &kbifPcieConfigEnableRelaxedOrdering_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbifPcieConfigEnableRelaxedOrdering__ = &kbifPcieConfigEnableRelaxedOrdering_GH100; } - else if (0) - { - } } // Hal function -- kbifPcieConfigDisableRelaxedOrdering - if (0) + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbifPcieConfigDisableRelaxedOrdering__ = &kbifPcieConfigDisableRelaxedOrdering_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbifPcieConfigDisableRelaxedOrdering__ = &kbifPcieConfigDisableRelaxedOrdering_GH100; } - else if (0) - { - } } // Hal function -- kbifInitRelaxedOrderingFromEmulatedConfigSpace - if (0) - { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ { @@ -534,44 +452,32 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner * } // Hal function -- kbifEnableNoSnoop - if (0) + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbifEnableNoSnoop__ = &kbifEnableNoSnoop_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbifEnableNoSnoop__ = &kbifEnableNoSnoop_GH100; } - else if (0) - { - } - else if (0) - { - } } // Hal function -- kbifApplyWARBug3208922 - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbifApplyWARBug3208922__ = &kbifApplyWARBug3208922_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x080003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ { pThis->__kbifApplyWARBug3208922__ = &kbifApplyWARBug3208922_b3696a; } // Hal function -- kbifProbePcieReqAtomicCaps - if (0) + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbifProbePcieReqAtomicCaps__ = &kbifProbePcieReqAtomicCaps_GH100; } @@ -583,31 +489,24 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner * } // Hal function -- kbifGetPciConfigSpacePriMirror - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbifGetPciConfigSpacePriMirror__ = &kbifGetPciConfigSpacePriMirror_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbifGetPciConfigSpacePriMirror__ = &kbifGetPciConfigSpacePriMirror_GH100; } - // default - else - { - } // Hal function -- kbifGetBusOptionsAddr - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kbifGetBusOptionsAddr__ = &kbifGetBusOptionsAddr_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kbifGetBusOptionsAddr__ = &kbifGetBusOptionsAddr_GH100; } - else if (0) - { - } pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelBif_engstateConstructEngine; diff --git a/src/nvidia/generated/g_kernel_bif_nvoc.h b/src/nvidia/generated/g_kernel_bif_nvoc.h index 0b29f90f4..0014a6e49 100644 --- a/src/nvidia/generated/g_kernel_bif_nvoc.h +++ b/src/nvidia/generated/g_kernel_bif_nvoc.h @@ -40,7 +40,6 @@ extern "C" { #include "gpu/eng_state.h" #include "gpu/gpu_halspec.h" #include "gpu/intr/intr_service.h" -#include "gpu/intrable/intrable.h" #include "gpu/mem_mgr/mem_desc.h" #include "rmpbicmdif.h" #include "nvoc/utility.h" @@ -75,7 +74,7 @@ typedef enum BUS_OPTIONS } BUS_OPTIONS; -typedef struct HOST_VGPU_DEVICE HOST_VGPU_DEVICE; +typedef struct KERNEL_HOST_VGPU_DEVICE KERNEL_HOST_VGPU_DEVICE; #ifdef NVOC_KERNEL_BIF_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x @@ -279,6 +278,7 @@ static inline NvU32 kbifGetBusIntfType_2f2c74(struct KernelBif *pKernelBif) { return (3); } + #ifdef __nvoc_kernel_bif_h_disabled static inline NvU32 kbifGetBusIntfType(struct KernelBif *pKernelBif) { NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); @@ -292,6 +292,7 @@ static inline NvU32 kbifGetBusIntfType(struct KernelBif *pKernelBif) { void kbifInitDmaCaps_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + #ifdef __nvoc_kernel_bif_h_disabled static inline void kbifInitDmaCaps(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); @@ -304,6 +305,7 @@ static inline void kbifInitDmaCaps(struct OBJGPU *pGpu, struct KernelBif *pKerne void kbifClearConfigErrors_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool arg0, NvU32 arg1); + #ifdef __nvoc_kernel_bif_h_disabled static inline void kbifClearConfigErrors(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool arg0, NvU32 arg1) { NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); @@ -316,6 +318,7 @@ static inline void kbifClearConfigErrors(struct OBJGPU *pGpu, struct KernelBif * void kbifDisableP2PTransactions_TU102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + #ifdef __nvoc_kernel_bif_h_disabled static inline void kbifDisableP2PTransactions(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); @@ -326,6 +329,34 @@ static inline void kbifDisableP2PTransactions(struct OBJGPU *pGpu, struct Kernel #define kbifDisableP2PTransactions_HAL(pGpu, pKernelBif) kbifDisableP2PTransactions(pGpu, pKernelBif) +NV_STATUS kbifGetNumVFSparseMmapRegions_TU102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, NvU32 *numAreas); + + +#ifdef __nvoc_kernel_bif_h_disabled +static inline NV_STATUS kbifGetNumVFSparseMmapRegions(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, NvU32 *numAreas) { + NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_bif_h_disabled +#define kbifGetNumVFSparseMmapRegions(pGpu, pKernelBif, pKernelHostVgpuDevice, numAreas) kbifGetNumVFSparseMmapRegions_TU102(pGpu, pKernelBif, pKernelHostVgpuDevice, numAreas) +#endif //__nvoc_kernel_bif_h_disabled + +#define kbifGetNumVFSparseMmapRegions_HAL(pGpu, pKernelBif, pKernelHostVgpuDevice, numAreas) kbifGetNumVFSparseMmapRegions(pGpu, pKernelBif, pKernelHostVgpuDevice, numAreas) + +NV_STATUS kbifGetVFSparseMmapRegions_TU102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, NvU64 os_page_size, NvU64 *offsets, NvU64 *sizes); + + +#ifdef __nvoc_kernel_bif_h_disabled +static inline NV_STATUS kbifGetVFSparseMmapRegions(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, NvU64 os_page_size, NvU64 *offsets, NvU64 *sizes) { + NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_bif_h_disabled +#define kbifGetVFSparseMmapRegions(pGpu, pKernelBif, pKernelHostVgpuDevice, os_page_size, offsets, sizes) kbifGetVFSparseMmapRegions_TU102(pGpu, pKernelBif, pKernelHostVgpuDevice, os_page_size, offsets, sizes) +#endif //__nvoc_kernel_bif_h_disabled + +#define kbifGetVFSparseMmapRegions_HAL(pGpu, pKernelBif, pKernelHostVgpuDevice, os_page_size, offsets, sizes) kbifGetVFSparseMmapRegions(pGpu, pKernelBif, pKernelHostVgpuDevice, os_page_size, offsets, sizes) + NV_STATUS kbifConstructEngine_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, ENGDESCRIPTOR arg0); static inline NV_STATUS kbifConstructEngine_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, ENGDESCRIPTOR arg0) { @@ -338,30 +369,18 @@ static inline NV_STATUS kbifStateInitLocked_DISPATCH(struct OBJGPU *pGpu, struct return pKernelBif->__kbifStateInitLocked__(pGpu, pKernelBif); } -static inline NV_STATUS kbifStateLoad_56cd7a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0) { - return NV_OK; -} - NV_STATUS kbifStateLoad_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0); static inline NV_STATUS kbifStateLoad_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0) { return pKernelBif->__kbifStateLoad__(pGpu, pKernelBif, arg0); } -static inline NV_STATUS kbifStatePostLoad_56cd7a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0) { - return NV_OK; -} - NV_STATUS kbifStatePostLoad_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0); static inline NV_STATUS kbifStatePostLoad_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0) { return pKernelBif->__kbifStatePostLoad__(pGpu, pKernelBif, arg0); } -static inline NV_STATUS kbifStateUnload_56cd7a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0) { - return NV_OK; -} - NV_STATUS kbifStateUnload_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0); static inline NV_STATUS kbifStateUnload_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0) { @@ -372,10 +391,6 @@ NV_STATUS kbifGetXveStatusBits_GM107(struct OBJGPU *pGpu, struct KernelBif *pKer NV_STATUS kbifGetXveStatusBits_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pBits, NvU32 *pStatus); -static inline NV_STATUS kbifGetXveStatusBits_56cd7a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pBits, NvU32 *pStatus) { - return NV_OK; -} - static inline NV_STATUS kbifGetXveStatusBits_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pBits, NvU32 *pStatus) { return pKernelBif->__kbifGetXveStatusBits__(pGpu, pKernelBif, pBits, pStatus); } @@ -384,10 +399,6 @@ NV_STATUS kbifClearXveStatus_GM107(struct OBJGPU *pGpu, struct KernelBif *pKerne NV_STATUS kbifClearXveStatus_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pStatus); -static inline NV_STATUS kbifClearXveStatus_56cd7a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pStatus) { - return NV_OK; -} - static inline NV_STATUS kbifClearXveStatus_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pStatus) { return pKernelBif->__kbifClearXveStatus__(pGpu, pKernelBif, pStatus); } @@ -396,10 +407,6 @@ NV_STATUS kbifGetXveAerBits_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernel NV_STATUS kbifGetXveAerBits_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pBits); -static inline NV_STATUS kbifGetXveAerBits_56cd7a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pBits) { - return NV_OK; -} - static inline NV_STATUS kbifGetXveAerBits_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pBits) { return pKernelBif->__kbifGetXveAerBits__(pGpu, pKernelBif, pBits); } @@ -408,19 +415,10 @@ NV_STATUS kbifClearXveAer_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBi NV_STATUS kbifClearXveAer_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 bits); -static inline NV_STATUS kbifClearXveAer_56cd7a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 bits) { - return NV_OK; -} - static inline NV_STATUS kbifClearXveAer_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 bits) { return pKernelBif->__kbifClearXveAer__(pGpu, pKernelBif, bits); } -static inline void kbifGetPcieConfigAccessTestRegisters_e426af(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pciStart, NvU32 *pcieStart) { - NV_ASSERT_PRECOMP(0); - return; -} - void kbifGetPcieConfigAccessTestRegisters_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pciStart, NvU32 *pcieStart); static inline void kbifGetPcieConfigAccessTestRegisters_b3696a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pciStart, NvU32 *pcieStart) { @@ -431,11 +429,6 @@ static inline void kbifGetPcieConfigAccessTestRegisters_DISPATCH(struct OBJGPU * pKernelBif->__kbifGetPcieConfigAccessTestRegisters__(pGpu, pKernelBif, pciStart, pcieStart); } -static inline NV_STATUS kbifVerifyPcieConfigAccessTestRegisters_92bfc3(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 nvXveId, NvU32 nvXveVccapHdr) { - NV_ASSERT_PRECOMP(0); - return NV_ERR_NOT_SUPPORTED; -} - NV_STATUS kbifVerifyPcieConfigAccessTestRegisters_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 nvXveId, NvU32 nvXveVccapHdr); static inline NV_STATUS kbifVerifyPcieConfigAccessTestRegisters_46f6a7(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 nvXveId, NvU32 nvXveVccapHdr) { @@ -452,10 +445,6 @@ static inline void kbifRearmMSI_f2d351(struct OBJGPU *pGpu, struct KernelBif *pK NV_ASSERT_PRECOMP(0); } -static inline void kbifRearmMSI_b3696a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { - return; -} - static inline void kbifRearmMSI_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { pKernelBif->__kbifRearmMSI__(pGpu, pKernelBif); } @@ -464,10 +453,6 @@ NvBool kbifIsMSIEnabledInHW_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernel NvBool kbifIsMSIEnabledInHW_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); -static inline NvBool kbifIsMSIEnabledInHW_491d52(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { - return ((NvBool)(0 != 0)); -} - static inline NvBool kbifIsMSIEnabledInHW_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { return pKernelBif->__kbifIsMSIEnabledInHW__(pGpu, pKernelBif); } @@ -476,10 +461,6 @@ NvBool kbifIsMSIXEnabledInHW_TU102(struct OBJGPU *pGpu, struct KernelBif *pKerne NvBool kbifIsMSIXEnabledInHW_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); -static inline NvBool kbifIsMSIXEnabledInHW_491d52(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { - return ((NvBool)(0 != 0)); -} - static inline NvBool kbifIsMSIXEnabledInHW_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { return pKernelBif->__kbifIsMSIXEnabledInHW__(pGpu, pKernelBif); } @@ -498,10 +479,6 @@ NvBool kbifIs3dController_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBi NvBool kbifIs3dController_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); -static inline NvBool kbifIs3dController_491d52(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { - return ((NvBool)(0 != 0)); -} - static inline NvBool kbifIs3dController_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { return pKernelBif->__kbifIs3dController__(pGpu, pKernelBif); } @@ -516,11 +493,6 @@ static inline void kbifExecC73War_DISPATCH(struct OBJGPU *pGpu, struct KernelBif pKernelBif->__kbifExecC73War__(pGpu, pKernelBif); } -static inline void kbifEnableExtendedTagSupport_e426af(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { - NV_ASSERT_PRECOMP(0); - return; -} - void kbifEnableExtendedTagSupport_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); static inline void kbifEnableExtendedTagSupport_b3696a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { @@ -531,36 +503,18 @@ static inline void kbifEnableExtendedTagSupport_DISPATCH(struct OBJGPU *pGpu, st pKernelBif->__kbifEnableExtendedTagSupport__(pGpu, pKernelBif); } -static inline void kbifPcieConfigEnableRelaxedOrdering_e426af(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { - NV_ASSERT_PRECOMP(0); - return; -} - void kbifPcieConfigEnableRelaxedOrdering_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); void kbifPcieConfigEnableRelaxedOrdering_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); -static inline void kbifPcieConfigEnableRelaxedOrdering_b3696a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { - return; -} - static inline void kbifPcieConfigEnableRelaxedOrdering_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { pKernelBif->__kbifPcieConfigEnableRelaxedOrdering__(pGpu, pKernelBif); } -static inline void kbifPcieConfigDisableRelaxedOrdering_e426af(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { - NV_ASSERT_PRECOMP(0); - return; -} - void kbifPcieConfigDisableRelaxedOrdering_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); void kbifPcieConfigDisableRelaxedOrdering_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); -static inline void kbifPcieConfigDisableRelaxedOrdering_b3696a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { - return; -} - static inline void kbifPcieConfigDisableRelaxedOrdering_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { pKernelBif->__kbifPcieConfigDisableRelaxedOrdering__(pGpu, pKernelBif); } @@ -575,23 +529,10 @@ static inline void kbifInitRelaxedOrderingFromEmulatedConfigSpace_DISPATCH(struc pBif->__kbifInitRelaxedOrderingFromEmulatedConfigSpace__(pGpu, pBif); } -static inline NV_STATUS kbifEnableNoSnoop_92bfc3(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool bEnable) { - NV_ASSERT_PRECOMP(0); - return NV_ERR_NOT_SUPPORTED; -} - NV_STATUS kbifEnableNoSnoop_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool bEnable); NV_STATUS kbifEnableNoSnoop_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool bEnable); -static inline NV_STATUS kbifEnableNoSnoop_56cd7a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool bEnable) { - return NV_OK; -} - -static inline NV_STATUS kbifEnableNoSnoop_46f6a7(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool bEnable) { - return NV_ERR_NOT_SUPPORTED; -} - static inline NV_STATUS kbifEnableNoSnoop_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool bEnable) { return pKernelBif->__kbifEnableNoSnoop__(pGpu, pKernelBif, bEnable); } @@ -620,10 +561,6 @@ NV_STATUS kbifGetPciConfigSpacePriMirror_GM107(struct OBJGPU *pGpu, struct Kerne NV_STATUS kbifGetPciConfigSpacePriMirror_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pMirrorBase, NvU32 *pMirrorSize); -static inline NV_STATUS kbifGetPciConfigSpacePriMirror_46f6a7(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pMirrorBase, NvU32 *pMirrorSize) { - return NV_ERR_NOT_SUPPORTED; -} - static inline NV_STATUS kbifGetPciConfigSpacePriMirror_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pMirrorBase, NvU32 *pMirrorSize) { return pKernelBif->__kbifGetPciConfigSpacePriMirror__(pGpu, pKernelBif, pMirrorBase, pMirrorSize); } @@ -632,10 +569,6 @@ NV_STATUS kbifGetBusOptionsAddr_GM107(struct OBJGPU *pGpu, struct KernelBif *pKe NV_STATUS kbifGetBusOptionsAddr_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, BUS_OPTIONS options, NvU32 *addrReg); -static inline NV_STATUS kbifGetBusOptionsAddr_46f6a7(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, BUS_OPTIONS options, NvU32 *addrReg) { - return NV_ERR_NOT_SUPPORTED; -} - static inline NV_STATUS kbifGetBusOptionsAddr_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, BUS_OPTIONS options, NvU32 *addrReg) { return pKernelBif->__kbifGetBusOptionsAddr__(pGpu, pKernelBif, options, addrReg); } @@ -701,6 +634,7 @@ static inline NvBool kbifIsPresent_DISPATCH(POBJGPU pGpu, struct KernelBif *pEng } NV_STATUS kbifStaticInfoInit_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + #ifdef __nvoc_kernel_bif_h_disabled static inline NV_STATUS kbifStaticInfoInit(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); @@ -711,6 +645,7 @@ static inline NV_STATUS kbifStaticInfoInit(struct OBJGPU *pGpu, struct KernelBif #endif //__nvoc_kernel_bif_h_disabled void kbifInitPcieDeviceControlStatus_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + #ifdef __nvoc_kernel_bif_h_disabled static inline void kbifInitPcieDeviceControlStatus(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); @@ -720,6 +655,7 @@ static inline void kbifInitPcieDeviceControlStatus(struct OBJGPU *pGpu, struct K #endif //__nvoc_kernel_bif_h_disabled void kbifCheckAndRearmMSI_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + #ifdef __nvoc_kernel_bif_h_disabled static inline void kbifCheckAndRearmMSI(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); @@ -729,6 +665,7 @@ static inline void kbifCheckAndRearmMSI(struct OBJGPU *pGpu, struct KernelBif *p #endif //__nvoc_kernel_bif_h_disabled NvBool kbifIsMSIEnabled_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + #ifdef __nvoc_kernel_bif_h_disabled static inline NvBool kbifIsMSIEnabled(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); @@ -739,6 +676,7 @@ static inline NvBool kbifIsMSIEnabled(struct OBJGPU *pGpu, struct KernelBif *pKe #endif //__nvoc_kernel_bif_h_disabled NvBool kbifIsMSIXEnabled_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + #ifdef __nvoc_kernel_bif_h_disabled static inline NvBool kbifIsMSIXEnabled(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); @@ -749,6 +687,7 @@ static inline NvBool kbifIsMSIXEnabled(struct OBJGPU *pGpu, struct KernelBif *pK #endif //__nvoc_kernel_bif_h_disabled NvBool kbifIsPciBusFamily_IMPL(struct KernelBif *pKernelBif); + #ifdef __nvoc_kernel_bif_h_disabled static inline NvBool kbifIsPciBusFamily(struct KernelBif *pKernelBif) { NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); @@ -759,6 +698,7 @@ static inline NvBool kbifIsPciBusFamily(struct KernelBif *pKernelBif) { #endif //__nvoc_kernel_bif_h_disabled NV_STATUS kbifControlGetPCIEInfo_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NV2080_CTRL_BUS_INFO *pBusInfo); + #ifdef __nvoc_kernel_bif_h_disabled static inline NV_STATUS kbifControlGetPCIEInfo(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NV2080_CTRL_BUS_INFO *pBusInfo) { NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); @@ -769,6 +709,7 @@ static inline NV_STATUS kbifControlGetPCIEInfo(struct OBJGPU *pGpu, struct Kerne #endif //__nvoc_kernel_bif_h_disabled NvU32 kbifGetDmaCaps_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + #ifdef __nvoc_kernel_bif_h_disabled static inline NvU32 kbifGetDmaCaps(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); diff --git a/src/nvidia/generated/g_kernel_ccu_api_nvoc.c b/src/nvidia/generated/g_kernel_ccu_api_nvoc.c index 2736c7110..ae582382c 100644 --- a/src/nvidia/generated/g_kernel_ccu_api_nvoc.c +++ b/src/nvidia/generated/g_kernel_ccu_api_nvoc.c @@ -169,6 +169,10 @@ static NV_STATUS __nvoc_thunk_RsResource_kccuapiUnmapFrom(struct KernelCcuApi *p return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_kccuapiIsDuplicate(struct KernelCcuApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_kccuapiControl_Epilogue(struct KernelCcuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RmResource.offset), pCallContext, pParams); } @@ -215,6 +219,36 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCc /*pClassInfo=*/ &(__nvoc_class_def_KernelCcuApi.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "kccuapiCtrlCmdUnsubscribe" +#endif + }, + { /* [2] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) kccuapiCtrlCmdSetStreamState_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xcbca0103u, + /*paramSize=*/ sizeof(NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_KernelCcuApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "kccuapiCtrlCmdSetStreamState" +#endif + }, + { /* [3] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) kccuapiCtrlCmdGetStreamState_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xcbca0104u, + /*paramSize=*/ sizeof(NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_KernelCcuApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "kccuapiCtrlCmdGetStreamState" #endif }, @@ -222,7 +256,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCc const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelCcuApi = { - /*numEntries=*/ 2, + /*numEntries=*/ 4, /*pExportEntries=*/ __nvoc_exported_method_def_KernelCcuApi }; @@ -275,6 +309,14 @@ static void __nvoc_init_funcTable_KernelCcuApi_1(KernelCcuApi *pThis) { pThis->__kccuapiCtrlCmdUnsubscribe__ = &kccuapiCtrlCmdUnsubscribe_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__kccuapiCtrlCmdSetStreamState__ = &kccuapiCtrlCmdSetStreamState_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__kccuapiCtrlCmdGetStreamState__ = &kccuapiCtrlCmdGetStreamState_IMPL; +#endif + pThis->__nvoc_base_GpuResource.__gpuresMap__ = &__nvoc_thunk_KernelCcuApi_gpuresMap; pThis->__nvoc_base_GpuResource.__gpuresUnmap__ = &__nvoc_thunk_KernelCcuApi_gpuresUnmap; @@ -313,6 +355,8 @@ static void __nvoc_init_funcTable_KernelCcuApi_1(KernelCcuApi *pThis) { pThis->__kccuapiUnmapFrom__ = &__nvoc_thunk_RsResource_kccuapiUnmapFrom; + pThis->__kccuapiIsDuplicate__ = &__nvoc_thunk_RsResource_kccuapiIsDuplicate; + pThis->__kccuapiControl_Epilogue__ = &__nvoc_thunk_RmResource_kccuapiControl_Epilogue; pThis->__kccuapiControlLookup__ = &__nvoc_thunk_RsResource_kccuapiControlLookup; diff --git a/src/nvidia/generated/g_kernel_ccu_api_nvoc.h b/src/nvidia/generated/g_kernel_ccu_api_nvoc.h index 366a914c2..e3152677d 100644 --- a/src/nvidia/generated/g_kernel_ccu_api_nvoc.h +++ b/src/nvidia/generated/g_kernel_ccu_api_nvoc.h @@ -63,6 +63,8 @@ struct KernelCcuApi { NV_STATUS (*__kccuapiGetMemoryMappingDescriptor__)(struct KernelCcuApi *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__kccuapiCtrlCmdSubscribe__)(struct KernelCcuApi *, NV_COUNTER_COLLECTION_UNIT_SUBSCRIBE_PARAMS *); NV_STATUS (*__kccuapiCtrlCmdUnsubscribe__)(struct KernelCcuApi *); + NV_STATUS (*__kccuapiCtrlCmdSetStreamState__)(struct KernelCcuApi *, NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS *); + NV_STATUS (*__kccuapiCtrlCmdGetStreamState__)(struct KernelCcuApi *, NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS *); NvBool (*__kccuapiShareCallback__)(struct KernelCcuApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__kccuapiControl__)(struct KernelCcuApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kccuapiGetMemInterMapParams__)(struct KernelCcuApi *, RMRES_MEM_INTER_MAP_PARAMS *); @@ -78,6 +80,7 @@ struct KernelCcuApi { NV_STATUS (*__kccuapiInternalControlForward__)(struct KernelCcuApi *, NvU32, void *, NvU32); void (*__kccuapiPreDestruct__)(struct KernelCcuApi *); NV_STATUS (*__kccuapiUnmapFrom__)(struct KernelCcuApi *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__kccuapiIsDuplicate__)(struct KernelCcuApi *, NvHandle, NvBool *); void (*__kccuapiControl_Epilogue__)(struct KernelCcuApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kccuapiControlLookup__)(struct KernelCcuApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvBool (*__kccuapiAccessCallback__)(struct KernelCcuApi *, struct RsClient *, void *, RsAccessRight); @@ -117,6 +120,8 @@ NV_STATUS __nvoc_objCreate_KernelCcuApi(KernelCcuApi**, Dynamic*, NvU32, struct #define kccuapiGetMemoryMappingDescriptor(pKernelCcuApi, ppMemDesc) kccuapiGetMemoryMappingDescriptor_DISPATCH(pKernelCcuApi, ppMemDesc) #define kccuapiCtrlCmdSubscribe(pKernelCcuApi, pParams) kccuapiCtrlCmdSubscribe_DISPATCH(pKernelCcuApi, pParams) #define kccuapiCtrlCmdUnsubscribe(pKernelCcuApi) kccuapiCtrlCmdUnsubscribe_DISPATCH(pKernelCcuApi) +#define kccuapiCtrlCmdSetStreamState(pKernelCcuApi, pParams) kccuapiCtrlCmdSetStreamState_DISPATCH(pKernelCcuApi, pParams) +#define kccuapiCtrlCmdGetStreamState(pKernelCcuApi, pParams) kccuapiCtrlCmdGetStreamState_DISPATCH(pKernelCcuApi, pParams) #define kccuapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) kccuapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) #define kccuapiControl(pGpuResource, pCallContext, pParams) kccuapiControl_DISPATCH(pGpuResource, pCallContext, pParams) #define kccuapiGetMemInterMapParams(pRmResource, pParams) kccuapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) @@ -132,6 +137,7 @@ NV_STATUS __nvoc_objCreate_KernelCcuApi(KernelCcuApi**, Dynamic*, NvU32, struct #define kccuapiInternalControlForward(pGpuResource, command, pParams, size) kccuapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define kccuapiPreDestruct(pResource) kccuapiPreDestruct_DISPATCH(pResource) #define kccuapiUnmapFrom(pResource, pParams) kccuapiUnmapFrom_DISPATCH(pResource, pParams) +#define kccuapiIsDuplicate(pResource, hMemory, pDuplicate) kccuapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define kccuapiControl_Epilogue(pResource, pCallContext, pParams) kccuapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define kccuapiControlLookup(pResource, pParams, ppEntry) kccuapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define kccuapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) kccuapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) @@ -171,6 +177,18 @@ static inline NV_STATUS kccuapiCtrlCmdUnsubscribe_DISPATCH(struct KernelCcuApi * return pKernelCcuApi->__kccuapiCtrlCmdUnsubscribe__(pKernelCcuApi); } +NV_STATUS kccuapiCtrlCmdSetStreamState_IMPL(struct KernelCcuApi *pKernelCcuApi, NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS *pParams); + +static inline NV_STATUS kccuapiCtrlCmdSetStreamState_DISPATCH(struct KernelCcuApi *pKernelCcuApi, NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS *pParams) { + return pKernelCcuApi->__kccuapiCtrlCmdSetStreamState__(pKernelCcuApi, pParams); +} + +NV_STATUS kccuapiCtrlCmdGetStreamState_IMPL(struct KernelCcuApi *pKernelCcuApi, NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS *pParams); + +static inline NV_STATUS kccuapiCtrlCmdGetStreamState_DISPATCH(struct KernelCcuApi *pKernelCcuApi, NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS *pParams) { + return pKernelCcuApi->__kccuapiCtrlCmdGetStreamState__(pKernelCcuApi, pParams); +} + static inline NvBool kccuapiShareCallback_DISPATCH(struct KernelCcuApi *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pGpuResource->__kccuapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } @@ -231,6 +249,10 @@ static inline NV_STATUS kccuapiUnmapFrom_DISPATCH(struct KernelCcuApi *pResource return pResource->__kccuapiUnmapFrom__(pResource, pParams); } +static inline NV_STATUS kccuapiIsDuplicate_DISPATCH(struct KernelCcuApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__kccuapiIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void kccuapiControl_Epilogue_DISPATCH(struct KernelCcuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__kccuapiControl_Epilogue__(pResource, pCallContext, pParams); } @@ -244,8 +266,10 @@ static inline NvBool kccuapiAccessCallback_DISPATCH(struct KernelCcuApi *pResour } NV_STATUS kccuapiConstruct_IMPL(struct KernelCcuApi *arg_pKernelCcuApi, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_kccuapiConstruct(arg_pKernelCcuApi, arg_pCallContext, arg_pParams) kccuapiConstruct_IMPL(arg_pKernelCcuApi, arg_pCallContext, arg_pParams) void kccuapiDestruct_IMPL(struct KernelCcuApi *pKernelCcuApi); + #define __nvoc_kccuapiDestruct(pKernelCcuApi) kccuapiDestruct_IMPL(pKernelCcuApi) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_kernel_ccu_nvoc.c b/src/nvidia/generated/g_kernel_ccu_nvoc.c index b9f2cf4c9..2e5def272 100644 --- a/src/nvidia/generated/g_kernel_ccu_nvoc.c +++ b/src/nvidia/generated/g_kernel_ccu_nvoc.c @@ -162,10 +162,14 @@ void __nvoc_dtor_KernelCcu(KernelCcu *pThis) { void __nvoc_init_dataField_KernelCcu(KernelCcu *pThis, RmHalspecOwner *pRmhalspecowner) { RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; + ChipHal *chipHal = &pRmhalspecowner->chipHal; + const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; PORT_UNREFERENCED_VARIABLE(pThis); PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); PORT_UNREFERENCED_VARIABLE(rmVariantHal); PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); + PORT_UNREFERENCED_VARIABLE(chipHal); + PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); } NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); @@ -185,24 +189,36 @@ __nvoc_ctor_KernelCcu_exit: static void __nvoc_init_funcTable_KernelCcu_1(KernelCcu *pThis, RmHalspecOwner *pRmhalspecowner) { RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; + ChipHal *chipHal = &pRmhalspecowner->chipHal; + const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; PORT_UNREFERENCED_VARIABLE(pThis); PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); PORT_UNREFERENCED_VARIABLE(rmVariantHal); PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); + PORT_UNREFERENCED_VARIABLE(chipHal); + PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); // Hal function -- kccuConstructEngine if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { pThis->__kccuConstructEngine__ = &kccuConstructEngine_IMPL; } - else if (0) - { - } pThis->__kccuStateLoad__ = &kccuStateLoad_IMPL; pThis->__kccuStateUnload__ = &kccuStateUnload_IMPL; + // Hal function -- kccuMigShrBufHandler + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kccuMigShrBufHandler__ = &kccuMigShrBufHandler_GH100; + } + // default + else + { + pThis->__kccuMigShrBufHandler__ = &kccuMigShrBufHandler_46f6a7; + } + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelCcu_engstateConstructEngine; pThis->__nvoc_base_OBJENGSTATE.__engstateStateLoad__ = &__nvoc_thunk_KernelCcu_engstateStateLoad; diff --git a/src/nvidia/generated/g_kernel_ccu_nvoc.h b/src/nvidia/generated/g_kernel_ccu_nvoc.h index 3e729adea..b033f283e 100644 --- a/src/nvidia/generated/g_kernel_ccu_nvoc.h +++ b/src/nvidia/generated/g_kernel_ccu_nvoc.h @@ -45,6 +45,8 @@ extern "C" { #include "gpu/eng_state.h" #include "rmapi/rmapi.h" #include "objtmr.h" +#include "ctrl/ctrlcbca.h" +#include "ctrl/ctrl2080/ctrl2080internal.h" /*! * KernelCcu is a logical abstraction of the GPU Ccu Engine. The @@ -65,9 +67,17 @@ extern "C" { #define CCU_SHRBUF_COUNT_MAX (GPUMGR_MAX_GPU_INSTANCES + CCU_DEV_SHRBUF_COUNT) #define CCU_MIG_SWIZZID_SIZE (sizeof(NvU8)) #define CCU_MIG_INVALID_SWIZZID (0xFF) +#define CCU_MIG_COMPUTEID_SIZE (sizeof(NvU8)) +#define CCU_MIG_INVALID_COMPUTEID (0xFF) + +#define CCU_DEV_COUNTER_ENTRY_MAX (2048) +#define CCU_MIG_COUNTER_ENTRY_MAX (256) + +#define CCU_STREAM_STATE_DISABLE (0) +#define CCU_STREAM_STATE_ENABLE (1) #define CCU_GPU_SHARED_BUFFER_SIZE_MAX (CCU_PER_GPU_COUNTER_Q_SIZE + (2 * CCU_TIMESTAMP_SIZE) + CCU_MIG_SWIZZID_SIZE) // 16K counter block + head & tail timestamp size + mig-SwizzId size -#define CCU_MIG_INST_SHARED_BUFFER_SIZE_MAX (CCU_MIG_INST_COUNTER_Q_SIZE + (2 * CCU_TIMESTAMP_SIZE) + CCU_MIG_SWIZZID_SIZE) // 2K counter block + head & tail timestamp size + mig-SwizzId size +#define CCU_MIG_INST_SHARED_BUFFER_SIZE_MAX (CCU_MIG_INST_COUNTER_Q_SIZE + (2 * CCU_TIMESTAMP_SIZE) + CCU_MIG_SWIZZID_SIZE + CCU_MIG_COMPUTEID_SIZE) // 2K counter block + head & tail timestamp size + mig-SwizzId size + compute-instId size typedef struct { @@ -81,6 +91,7 @@ typedef struct NvU64 *pHeadTimeStamp; // Timestamp before the start of counter block NvU64 *pTailTimeStamp; // Timestamp at the end of counter block NvU8 *pSwizzId; // Mig inst swizz id + NvU8 *pComputeId; // Compute inst id NvP64 pCounterBlock; // Counter block start address NvU32 counterBlockSize; // Counter block size } CCU_SHRBUF_INFO; @@ -105,6 +116,7 @@ struct KernelCcu { NV_STATUS (*__kccuConstructEngine__)(OBJGPU *, struct KernelCcu *, ENGDESCRIPTOR); NV_STATUS (*__kccuStateLoad__)(OBJGPU *, struct KernelCcu *, NvU32); NV_STATUS (*__kccuStateUnload__)(OBJGPU *, struct KernelCcu *, NvU32); + NV_STATUS (*__kccuMigShrBufHandler__)(OBJGPU *, struct KernelCcu *, NvBool); NV_STATUS (*__kccuReconcileTunableState__)(POBJGPU, struct KernelCcu *, void *); NV_STATUS (*__kccuStateInitLocked__)(POBJGPU, struct KernelCcu *); NV_STATUS (*__kccuStatePreLoad__)(POBJGPU, struct KernelCcu *, NvU32); @@ -123,7 +135,9 @@ struct KernelCcu { NV_STATUS (*__kccuSetTunableState__)(POBJGPU, struct KernelCcu *, void *); NvBool (*__kccuIsPresent__)(POBJGPU, struct KernelCcu *); MEMORY_DESCRIPTOR *pMemDesc[9]; + NvBool bStreamState; CCU_SHRBUF shrBuf[9]; + NvBool bMigShrBufAllocated; }; #ifndef __NVOC_CLASS_KernelCcu_TYPEDEF__ @@ -160,6 +174,8 @@ NV_STATUS __nvoc_objCreate_KernelCcu(KernelCcu**, Dynamic*, NvU32); #define kccuConstructEngine_HAL(pGpu, pKernelCcu, engDesc) kccuConstructEngine_DISPATCH(pGpu, pKernelCcu, engDesc) #define kccuStateLoad(arg0, arg1, flags) kccuStateLoad_DISPATCH(arg0, arg1, flags) #define kccuStateUnload(arg0, arg1, flags) kccuStateUnload_DISPATCH(arg0, arg1, flags) +#define kccuMigShrBufHandler(arg0, arg1, bMigEnabled) kccuMigShrBufHandler_DISPATCH(arg0, arg1, bMigEnabled) +#define kccuMigShrBufHandler_HAL(arg0, arg1, bMigEnabled) kccuMigShrBufHandler_DISPATCH(arg0, arg1, bMigEnabled) #define kccuReconcileTunableState(pGpu, pEngstate, pTunableState) kccuReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kccuStateInitLocked(pGpu, pEngstate) kccuStateInitLocked_DISPATCH(pGpu, pEngstate) #define kccuStatePreLoad(pGpu, pEngstate, arg0) kccuStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) @@ -179,13 +195,10 @@ NV_STATUS __nvoc_objCreate_KernelCcu(KernelCcu**, Dynamic*, NvU32); #define kccuIsPresent(pGpu, pEngstate) kccuIsPresent_DISPATCH(pGpu, pEngstate) void kccuDestruct_IMPL(struct KernelCcu *arg0); + #define __nvoc_kccuDestruct(arg0) kccuDestruct_IMPL(arg0) NV_STATUS kccuConstructEngine_IMPL(OBJGPU *pGpu, struct KernelCcu *pKernelCcu, ENGDESCRIPTOR engDesc); -static inline NV_STATUS kccuConstructEngine_46f6a7(OBJGPU *pGpu, struct KernelCcu *pKernelCcu, ENGDESCRIPTOR engDesc) { - return NV_ERR_NOT_SUPPORTED; -} - static inline NV_STATUS kccuConstructEngine_DISPATCH(OBJGPU *pGpu, struct KernelCcu *pKernelCcu, ENGDESCRIPTOR engDesc) { return pKernelCcu->__kccuConstructEngine__(pGpu, pKernelCcu, engDesc); } @@ -202,6 +215,16 @@ static inline NV_STATUS kccuStateUnload_DISPATCH(OBJGPU *arg0, struct KernelCcu return arg1->__kccuStateUnload__(arg0, arg1, flags); } +static inline NV_STATUS kccuMigShrBufHandler_46f6a7(OBJGPU *arg0, struct KernelCcu *arg1, NvBool bMigEnabled) { + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS kccuMigShrBufHandler_GH100(OBJGPU *arg0, struct KernelCcu *arg1, NvBool bMigEnabled); + +static inline NV_STATUS kccuMigShrBufHandler_DISPATCH(OBJGPU *arg0, struct KernelCcu *arg1, NvBool bMigEnabled) { + return arg1->__kccuMigShrBufHandler__(arg0, arg1, bMigEnabled); +} + static inline NV_STATUS kccuReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEngstate, void *pTunableState) { return pEngstate->__kccuReconcileTunableState__(pGpu, pEngstate, pTunableState); } @@ -271,6 +294,7 @@ static inline NvBool kccuIsPresent_DISPATCH(POBJGPU pGpu, struct KernelCcu *pEng } NV_STATUS kccuMemDescGetForSwizzId_IMPL(OBJGPU *arg0, struct KernelCcu *arg1, NvU8 swizzId, MEMORY_DESCRIPTOR **arg2); + #ifdef __nvoc_kernel_ccu_h_disabled static inline NV_STATUS kccuMemDescGetForSwizzId(OBJGPU *arg0, struct KernelCcu *arg1, NvU8 swizzId, MEMORY_DESCRIPTOR **arg2) { NV_ASSERT_FAILED_PRECOMP("KernelCcu was disabled!"); @@ -281,6 +305,7 @@ static inline NV_STATUS kccuMemDescGetForSwizzId(OBJGPU *arg0, struct KernelCcu #endif //__nvoc_kernel_ccu_h_disabled NV_STATUS kccuMemDescGetForShrBufId_IMPL(OBJGPU *arg0, struct KernelCcu *arg1, NvU32 shrbufId, MEMORY_DESCRIPTOR **arg2); + #ifdef __nvoc_kernel_ccu_h_disabled static inline NV_STATUS kccuMemDescGetForShrBufId(OBJGPU *arg0, struct KernelCcu *arg1, NvU32 shrbufId, MEMORY_DESCRIPTOR **arg2) { NV_ASSERT_FAILED_PRECOMP("KernelCcu was disabled!"); @@ -291,6 +316,7 @@ static inline NV_STATUS kccuMemDescGetForShrBufId(OBJGPU *arg0, struct KernelCcu #endif //__nvoc_kernel_ccu_h_disabled NvU32 kccuCounterBlockSizeGet_IMPL(OBJGPU *arg0, struct KernelCcu *arg1, NvBool bDevCounter); + #ifdef __nvoc_kernel_ccu_h_disabled static inline NvU32 kccuCounterBlockSizeGet(OBJGPU *arg0, struct KernelCcu *arg1, NvBool bDevCounter) { NV_ASSERT_FAILED_PRECOMP("KernelCcu was disabled!"); @@ -300,6 +326,71 @@ static inline NvU32 kccuCounterBlockSizeGet(OBJGPU *arg0, struct KernelCcu *arg1 #define kccuCounterBlockSizeGet(arg0, arg1, bDevCounter) kccuCounterBlockSizeGet_IMPL(arg0, arg1, bDevCounter) #endif //__nvoc_kernel_ccu_h_disabled +NV_STATUS kccuStreamStateSet_IMPL(OBJGPU *arg0, struct KernelCcu *arg1, NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS *arg2); + +#ifdef __nvoc_kernel_ccu_h_disabled +static inline NV_STATUS kccuStreamStateSet(OBJGPU *arg0, struct KernelCcu *arg1, NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS *arg2) { + NV_ASSERT_FAILED_PRECOMP("KernelCcu was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_ccu_h_disabled +#define kccuStreamStateSet(arg0, arg1, arg2) kccuStreamStateSet_IMPL(arg0, arg1, arg2) +#endif //__nvoc_kernel_ccu_h_disabled + +NvBool kccuStreamStateGet_IMPL(OBJGPU *arg0, struct KernelCcu *arg1); + +#ifdef __nvoc_kernel_ccu_h_disabled +static inline NvBool kccuStreamStateGet(OBJGPU *arg0, struct KernelCcu *arg1) { + NV_ASSERT_FAILED_PRECOMP("KernelCcu was disabled!"); + return NV_FALSE; +} +#else //__nvoc_kernel_ccu_h_disabled +#define kccuStreamStateGet(arg0, arg1) kccuStreamStateGet_IMPL(arg0, arg1) +#endif //__nvoc_kernel_ccu_h_disabled + +NV_STATUS kccuInitMigSharedBuffer_IMPL(OBJGPU *arg0, struct KernelCcu *arg1); + +#ifdef __nvoc_kernel_ccu_h_disabled +static inline NV_STATUS kccuInitMigSharedBuffer(OBJGPU *arg0, struct KernelCcu *arg1) { + NV_ASSERT_FAILED_PRECOMP("KernelCcu was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_ccu_h_disabled +#define kccuInitMigSharedBuffer(arg0, arg1) kccuInitMigSharedBuffer_IMPL(arg0, arg1) +#endif //__nvoc_kernel_ccu_h_disabled + +NV_STATUS kccuShrBufInfoToCcu_IMPL(OBJGPU *arg0, struct KernelCcu *arg1, NvU32 shrBufStartIdx); + +#ifdef __nvoc_kernel_ccu_h_disabled +static inline NV_STATUS kccuShrBufInfoToCcu(OBJGPU *arg0, struct KernelCcu *arg1, NvU32 shrBufStartIdx) { + NV_ASSERT_FAILED_PRECOMP("KernelCcu was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_ccu_h_disabled +#define kccuShrBufInfoToCcu(arg0, arg1, shrBufStartIdx) kccuShrBufInfoToCcu_IMPL(arg0, arg1, shrBufStartIdx) +#endif //__nvoc_kernel_ccu_h_disabled + +void kccuShrBufIdxCleanup_IMPL(OBJGPU *arg0, struct KernelCcu *arg1, NvU32 shrBufIdx); + +#ifdef __nvoc_kernel_ccu_h_disabled +static inline void kccuShrBufIdxCleanup(OBJGPU *arg0, struct KernelCcu *arg1, NvU32 shrBufIdx) { + NV_ASSERT_FAILED_PRECOMP("KernelCcu was disabled!"); +} +#else //__nvoc_kernel_ccu_h_disabled +#define kccuShrBufIdxCleanup(arg0, arg1, shrBufIdx) kccuShrBufIdxCleanup_IMPL(arg0, arg1, shrBufIdx) +#endif //__nvoc_kernel_ccu_h_disabled + +NV_STATUS kccuMemDescGetForComputeInst_IMPL(OBJGPU *arg0, struct KernelCcu *arg1, NvU8 swizzId, NvU8 computeId, MEMORY_DESCRIPTOR **arg2); + +#ifdef __nvoc_kernel_ccu_h_disabled +static inline NV_STATUS kccuMemDescGetForComputeInst(OBJGPU *arg0, struct KernelCcu *arg1, NvU8 swizzId, NvU8 computeId, MEMORY_DESCRIPTOR **arg2) { + NV_ASSERT_FAILED_PRECOMP("KernelCcu was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_ccu_h_disabled +#define kccuMemDescGetForComputeInst(arg0, arg1, swizzId, computeId, arg2) kccuMemDescGetForComputeInst_IMPL(arg0, arg1, swizzId, computeId, arg2) +#endif //__nvoc_kernel_ccu_h_disabled + #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_kernel_ce_context_nvoc.c b/src/nvidia/generated/g_kernel_ce_context_nvoc.c index 1e873d6ae..78a7be16f 100644 --- a/src/nvidia/generated/g_kernel_ce_context_nvoc.c +++ b/src/nvidia/generated/g_kernel_ce_context_nvoc.c @@ -220,6 +220,10 @@ static void __nvoc_thunk_RsResource_kcectxPreDestruct(struct KernelCeContext *pR resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCeContext_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_RsResource_kcectxIsDuplicate(struct KernelCeContext *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCeContext_RsResource.offset), hMemory, pDuplicate); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_kcectxGetNotificationListPtr(struct KernelCeContext *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelCeContext_Notifier.offset)); } @@ -325,6 +329,8 @@ static void __nvoc_init_funcTable_KernelCeContext_1(KernelCeContext *pThis) { pThis->__kcectxPreDestruct__ = &__nvoc_thunk_RsResource_kcectxPreDestruct; + pThis->__kcectxIsDuplicate__ = &__nvoc_thunk_RsResource_kcectxIsDuplicate; + pThis->__kcectxGetNotificationListPtr__ = &__nvoc_thunk_Notifier_kcectxGetNotificationListPtr; pThis->__kcectxGetNotificationShare__ = &__nvoc_thunk_Notifier_kcectxGetNotificationShare; diff --git a/src/nvidia/generated/g_kernel_ce_context_nvoc.h b/src/nvidia/generated/g_kernel_ce_context_nvoc.h index aa1a6fcde..e24415f1d 100644 --- a/src/nvidia/generated/g_kernel_ce_context_nvoc.h +++ b/src/nvidia/generated/g_kernel_ce_context_nvoc.h @@ -87,6 +87,7 @@ struct KernelCeContext { NV_STATUS (*__kcectxUnregisterEvent__)(struct KernelCeContext *, NvHandle, NvHandle, NvHandle, NvHandle); NvBool (*__kcectxCanCopy__)(struct KernelCeContext *); void (*__kcectxPreDestruct__)(struct KernelCeContext *); + NV_STATUS (*__kcectxIsDuplicate__)(struct KernelCeContext *, NvHandle, NvBool *); PEVENTNOTIFICATION *(*__kcectxGetNotificationListPtr__)(struct KernelCeContext *); struct NotifShare *(*__kcectxGetNotificationShare__)(struct KernelCeContext *); NV_STATUS (*__kcectxMap__)(struct KernelCeContext *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -146,6 +147,7 @@ NV_STATUS __nvoc_objCreate_KernelCeContext(KernelCeContext**, Dynamic*, NvU32, C #define kcectxUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) kcectxUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define kcectxCanCopy(pResource) kcectxCanCopy_DISPATCH(pResource) #define kcectxPreDestruct(pResource) kcectxPreDestruct_DISPATCH(pResource) +#define kcectxIsDuplicate(pResource, hMemory, pDuplicate) kcectxIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define kcectxGetNotificationListPtr(pNotifier) kcectxGetNotificationListPtr_DISPATCH(pNotifier) #define kcectxGetNotificationShare(pNotifier) kcectxGetNotificationShare_DISPATCH(pNotifier) #define kcectxMap(pGpuResource, pCallContext, pParams, pCpuMapping) kcectxMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -250,6 +252,10 @@ static inline void kcectxPreDestruct_DISPATCH(struct KernelCeContext *pResource) pResource->__kcectxPreDestruct__(pResource); } +static inline NV_STATUS kcectxIsDuplicate_DISPATCH(struct KernelCeContext *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__kcectxIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline PEVENTNOTIFICATION *kcectxGetNotificationListPtr_DISPATCH(struct KernelCeContext *pNotifier) { return pNotifier->__kcectxGetNotificationListPtr__(pNotifier); } @@ -267,8 +273,10 @@ static inline NV_STATUS kcectxGetOrAllocNotifShare_DISPATCH(struct KernelCeConte } NV_STATUS kcectxConstruct_IMPL(struct KernelCeContext *arg_pKCeContext, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_kcectxConstruct(arg_pKCeContext, arg_pCallContext, arg_pParams) kcectxConstruct_IMPL(arg_pKCeContext, arg_pCallContext, arg_pParams) void kcectxDestruct_IMPL(struct KernelCeContext *pKCeContext); + #define __nvoc_kcectxDestruct(pKCeContext) kcectxDestruct_IMPL(pKCeContext) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_kernel_ce_nvoc.c b/src/nvidia/generated/g_kernel_ce_nvoc.c index 653c8fe6f..e9e792e20 100644 --- a/src/nvidia/generated/g_kernel_ce_nvoc.c +++ b/src/nvidia/generated/g_kernel_ce_nvoc.c @@ -87,11 +87,7 @@ static NV_STATUS __nvoc_thunk_KernelCE_engstateStateLoad(OBJGPU *arg0, struct OB return kceStateLoad(arg0, (struct KernelCE *)(((unsigned char *)arg1) - __nvoc_rtti_KernelCE_OBJENGSTATE.offset), arg2); } -static NV_STATUS __nvoc_thunk_KernelCE_engstateStateUnload(OBJGPU *pGpu, struct OBJENGSTATE *pKCe, NvU32 flags) { - return kceStateUnload(pGpu, (struct KernelCE *)(((unsigned char *)pKCe) - __nvoc_rtti_KernelCE_OBJENGSTATE.offset), flags); -} - -static void __nvoc_thunk_KernelCE_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[155]) { +static void __nvoc_thunk_KernelCE_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[163]) { kceRegisterIntrService(arg0, (struct KernelCE *)(((unsigned char *)arg1) - __nvoc_rtti_KernelCE_IntrService.offset), arg2); } @@ -103,6 +99,10 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceReconcileTunableState(POBJGPU pGpu, return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset), pTunableState); } +static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceStateUnload(POBJGPU pGpu, struct KernelCE *pEngstate, NvU32 arg0) { + return engstateStateUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset), arg0); +} + static NV_STATUS __nvoc_thunk_OBJENGSTATE_kceStateInitLocked(POBJGPU pGpu, struct KernelCE *pEngstate) { return engstateStateInitLocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelCE_OBJENGSTATE.offset)); } @@ -232,71 +232,43 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR pThis->__kceConstructEngine__ = &kceConstructEngine_IMPL; // Hal function -- kceIsPresent - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kceIsPresent__ = &kceIsPresent_IMPL; } - else if (0) - { - } // Hal function -- kceStateLoad - if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kceStateLoad__ = &kceStateLoad_GP100; } - else if (0) - { - } - - // Hal function -- kceStateUnload - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ - { - pThis->__kceStateUnload__ = &kceStateUnload_GP100; - } - // default - else - { - } pThis->__kceRegisterIntrService__ = &kceRegisterIntrService_IMPL; pThis->__kceServiceNotificationInterrupt__ = &kceServiceNotificationInterrupt_IMPL; // Hal function -- kceGetNvlinkAutoConfigCeValues - if (0) - { - } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__kceGetNvlinkAutoConfigCeValues__ = &kceGetNvlinkAutoConfigCeValues_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kceGetNvlinkAutoConfigCeValues__ = &kceGetNvlinkAutoConfigCeValues_GA100; } - else if (0) - { - } // Hal function -- kceGetNvlinkMaxTopoForTable if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__kceGetNvlinkMaxTopoForTable__ = &kceGetNvlinkMaxTopoForTable_GP100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kceGetNvlinkMaxTopoForTable__ = &kceGetNvlinkMaxTopoForTable_491d52; } // Hal function -- kceIsCurrentMaxTopology - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kceIsCurrentMaxTopology__ = &kceIsCurrentMaxTopology_GA100; } @@ -305,30 +277,8 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR pThis->__kceIsCurrentMaxTopology__ = &kceIsCurrentMaxTopology_491d52; } - // Hal function -- kceGetGrceConfigSize1 - if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ - { - pThis->__kceGetGrceConfigSize1__ = &kceGetGrceConfigSize1_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ - { - pThis->__kceGetGrceConfigSize1__ = &kceGetGrceConfigSize1_GA100; - } - else if (0) - { - } - // Hal function -- kceGetPce2lceConfigSize1 - if (0) - { - } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__kceGetPce2lceConfigSize1__ = &kceGetPce2lceConfigSize1_TU102; } @@ -336,60 +286,45 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR { pThis->__kceGetPce2lceConfigSize1__ = &kceGetPce2lceConfigSize1_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kceGetPce2lceConfigSize1__ = &kceGetPce2lceConfigSize1_GA102; } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kceGetPce2lceConfigSize1__ = &kceGetPce2lceConfigSize1_GH100; } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } // Hal function -- kceGetMappings - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kceGetMappings__ = &kceGetMappings_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kceGetMappings__ = &kceGetMappings_GH100; } - else if (0) - { - } else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__kceGetMappings__ = &kceGetMappings_46f6a7; } // Hal function -- kceMapPceLceForC2C - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kceMapPceLceForC2C__ = &kceMapPceLceForC2C_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kceMapPceLceForC2C__ = &kceMapPceLceForC2C_46f6a7; } // Hal function -- kceMapPceLceForGRCE - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kceMapPceLceForGRCE__ = &kceMapPceLceForGRCE_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kceMapPceLceForGRCE__ = &kceMapPceLceForGRCE_b3696a; } @@ -399,21 +334,21 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR { pThis->__kceMapPceLceForSysmemLinks__ = &kceMapPceLceForSysmemLinks_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kceMapPceLceForSysmemLinks__ = &kceMapPceLceForSysmemLinks_GA102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x080003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ { pThis->__kceMapPceLceForSysmemLinks__ = &kceMapPceLceForSysmemLinks_46f6a7; } // Hal function -- kceMapPceLceForNvlinkPeers - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kceMapPceLceForNvlinkPeers__ = &kceMapPceLceForNvlinkPeers_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kceMapPceLceForNvlinkPeers__ = &kceMapPceLceForNvlinkPeers_GH100; } @@ -427,38 +362,35 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR { pThis->__kceGetSysmemSupportedLceMask__ = &kceGetSysmemSupportedLceMask_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kceGetSysmemSupportedLceMask__ = &kceGetSysmemSupportedLceMask_GA102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x080003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ { pThis->__kceGetSysmemSupportedLceMask__ = &kceGetSysmemSupportedLceMask_4a4dee; } // Hal function -- kceMapAsyncLceDefault - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kceMapAsyncLceDefault__ = &kceMapAsyncLceDefault_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kceMapAsyncLceDefault__ = &kceMapAsyncLceDefault_GH100; } - else if (0) - { - } else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__kceMapAsyncLceDefault__ = &kceMapAsyncLceDefault_46f6a7; } // Hal function -- kceGetNvlinkPeerSupportedLceMask - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kceGetNvlinkPeerSupportedLceMask__ = &kceGetNvlinkPeerSupportedLceMask_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kceGetNvlinkPeerSupportedLceMask__ = &kceGetNvlinkPeerSupportedLceMask_GA102; } @@ -472,7 +404,7 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR { pThis->__kceGetGrceSupportedLceMask__ = &kceGetGrceSupportedLceMask_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kceGetGrceSupportedLceMask__ = &kceGetGrceSupportedLceMask_GA102; } @@ -486,11 +418,11 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR { pThis->__kceIsGenXorHigherSupported__ = &kceIsGenXorHigherSupported_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kceIsGenXorHigherSupported__ = &kceIsGenXorHigherSupported_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kceIsGenXorHigherSupported__ = &kceIsGenXorHigherSupported_cbe027; } @@ -500,7 +432,7 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR { pThis->__kceApplyGen4orHigherMapping__ = &kceApplyGen4orHigherMapping_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kceApplyGen4orHigherMapping__ = &kceApplyGen4orHigherMapping_b3696a; } @@ -511,14 +443,14 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR pThis->__nvoc_base_OBJENGSTATE.__engstateStateLoad__ = &__nvoc_thunk_KernelCE_engstateStateLoad; - pThis->__nvoc_base_OBJENGSTATE.__engstateStateUnload__ = &__nvoc_thunk_KernelCE_engstateStateUnload; - pThis->__nvoc_base_IntrService.__intrservRegisterIntrService__ = &__nvoc_thunk_KernelCE_intrservRegisterIntrService; pThis->__nvoc_base_IntrService.__intrservServiceNotificationInterrupt__ = &__nvoc_thunk_KernelCE_intrservServiceNotificationInterrupt; pThis->__kceReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kceReconcileTunableState; + pThis->__kceStateUnload__ = &__nvoc_thunk_OBJENGSTATE_kceStateUnload; + pThis->__kceStateInitLocked__ = &__nvoc_thunk_OBJENGSTATE_kceStateInitLocked; pThis->__kceStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_kceStatePreLoad; diff --git a/src/nvidia/generated/g_kernel_ce_nvoc.h b/src/nvidia/generated/g_kernel_ce_nvoc.h index cc19f5271..33eabd0c7 100644 --- a/src/nvidia/generated/g_kernel_ce_nvoc.h +++ b/src/nvidia/generated/g_kernel_ce_nvoc.h @@ -110,13 +110,11 @@ struct KernelCE { NV_STATUS (*__kceConstructEngine__)(OBJGPU *, struct KernelCE *, ENGDESCRIPTOR); NvBool (*__kceIsPresent__)(OBJGPU *, struct KernelCE *); NV_STATUS (*__kceStateLoad__)(OBJGPU *, struct KernelCE *, NvU32); - NV_STATUS (*__kceStateUnload__)(OBJGPU *, struct KernelCE *, NvU32); void (*__kceRegisterIntrService__)(OBJGPU *, struct KernelCE *, IntrServiceRecord *); NV_STATUS (*__kceServiceNotificationInterrupt__)(OBJGPU *, struct KernelCE *, IntrServiceServiceNotificationInterruptArguments *); NV_STATUS (*__kceGetNvlinkAutoConfigCeValues__)(OBJGPU *, struct KernelCE *, NvU32 *, NvU32 *, NvU32 *); NvBool (*__kceGetNvlinkMaxTopoForTable__)(OBJGPU *, struct KernelCE *, struct NVLINK_TOPOLOGY_PARAMS *, void *, NvU32, NvU32 *); NvBool (*__kceIsCurrentMaxTopology__)(OBJGPU *, struct KernelCE *, struct NVLINK_TOPOLOGY_PARAMS *, NvU32 *, NvU32 *); - NvU32 (*__kceGetGrceConfigSize1__)(struct KernelCE *); NvU32 (*__kceGetPce2lceConfigSize1__)(struct KernelCE *); NV_STATUS (*__kceGetMappings__)(OBJGPU *, struct KernelCE *, NVLINK_TOPOLOGY_PARAMS *, NvU32 *, NvU32 *, NvU32 *); NV_STATUS (*__kceMapPceLceForC2C__)(OBJGPU *, struct KernelCE *, NvU32 *, NvU32 *, NvU32 *); @@ -130,6 +128,7 @@ struct KernelCE { NvBool (*__kceIsGenXorHigherSupported__)(OBJGPU *, struct KernelCE *, NvU32); void (*__kceApplyGen4orHigherMapping__)(OBJGPU *, struct KernelCE *, NvU32 *, NvU32 *, NvU32, NvU32); NV_STATUS (*__kceReconcileTunableState__)(POBJGPU, struct KernelCE *, void *); + NV_STATUS (*__kceStateUnload__)(POBJGPU, struct KernelCE *, NvU32); NV_STATUS (*__kceStateInitLocked__)(POBJGPU, struct KernelCE *); NV_STATUS (*__kceStatePreLoad__)(POBJGPU, struct KernelCE *, NvU32); NV_STATUS (*__kceStatePostUnload__)(POBJGPU, struct KernelCE *, NvU32); @@ -148,6 +147,7 @@ struct KernelCE { NV_STATUS (*__kceSetTunableState__)(POBJGPU, struct KernelCE *, void *); NvU32 (*__kceServiceInterrupt__)(OBJGPU *, struct KernelCE *, IntrServiceServiceInterruptArguments *); NvU32 publicID; + NvBool bShimOwner; NvBool bStubbed; NvU32 nvlinkPeerMask; NvU32 nvlinkNumPeers; @@ -191,8 +191,6 @@ NV_STATUS __nvoc_objCreate_KernelCE(KernelCE**, Dynamic*, NvU32); #define kceIsPresent_HAL(pGpu, pKCe) kceIsPresent_DISPATCH(pGpu, pKCe) #define kceStateLoad(arg0, arg1, arg2) kceStateLoad_DISPATCH(arg0, arg1, arg2) #define kceStateLoad_HAL(arg0, arg1, arg2) kceStateLoad_DISPATCH(arg0, arg1, arg2) -#define kceStateUnload(pGpu, pKCe, flags) kceStateUnload_DISPATCH(pGpu, pKCe, flags) -#define kceStateUnload_HAL(pGpu, pKCe, flags) kceStateUnload_DISPATCH(pGpu, pKCe, flags) #define kceRegisterIntrService(arg0, arg1, arg2) kceRegisterIntrService_DISPATCH(arg0, arg1, arg2) #define kceServiceNotificationInterrupt(arg0, arg1, arg2) kceServiceNotificationInterrupt_DISPATCH(arg0, arg1, arg2) #define kceGetNvlinkAutoConfigCeValues(pGpu, pKCe, arg0, arg1, arg2) kceGetNvlinkAutoConfigCeValues_DISPATCH(pGpu, pKCe, arg0, arg1, arg2) @@ -201,8 +199,6 @@ NV_STATUS __nvoc_objCreate_KernelCE(KernelCE**, Dynamic*, NvU32); #define kceGetNvlinkMaxTopoForTable_HAL(pGpu, pKCe, arg0, arg1, arg2, arg3) kceGetNvlinkMaxTopoForTable_DISPATCH(pGpu, pKCe, arg0, arg1, arg2, arg3) #define kceIsCurrentMaxTopology(pGpu, arg0, arg1, arg2, arg3) kceIsCurrentMaxTopology_DISPATCH(pGpu, arg0, arg1, arg2, arg3) #define kceIsCurrentMaxTopology_HAL(pGpu, arg0, arg1, arg2, arg3) kceIsCurrentMaxTopology_DISPATCH(pGpu, arg0, arg1, arg2, arg3) -#define kceGetGrceConfigSize1(arg0) kceGetGrceConfigSize1_DISPATCH(arg0) -#define kceGetGrceConfigSize1_HAL(arg0) kceGetGrceConfigSize1_DISPATCH(arg0) #define kceGetPce2lceConfigSize1(arg0) kceGetPce2lceConfigSize1_DISPATCH(arg0) #define kceGetPce2lceConfigSize1_HAL(arg0) kceGetPce2lceConfigSize1_DISPATCH(arg0) #define kceGetMappings(pGpu, pCe, arg0, arg1, arg2, arg3) kceGetMappings_DISPATCH(pGpu, pCe, arg0, arg1, arg2, arg3) @@ -228,6 +224,7 @@ NV_STATUS __nvoc_objCreate_KernelCE(KernelCE**, Dynamic*, NvU32); #define kceApplyGen4orHigherMapping(pGpu, pCe, arg0, arg1, arg2, arg3) kceApplyGen4orHigherMapping_DISPATCH(pGpu, pCe, arg0, arg1, arg2, arg3) #define kceApplyGen4orHigherMapping_HAL(pGpu, pCe, arg0, arg1, arg2, arg3) kceApplyGen4orHigherMapping_DISPATCH(pGpu, pCe, arg0, arg1, arg2, arg3) #define kceReconcileTunableState(pGpu, pEngstate, pTunableState) kceReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) +#define kceStateUnload(pGpu, pEngstate, arg0) kceStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define kceStateInitLocked(pGpu, pEngstate) kceStateInitLocked_DISPATCH(pGpu, pEngstate) #define kceStatePreLoad(pGpu, pEngstate, arg0) kceStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kceStatePostUnload(pGpu, pEngstate, arg0) kceStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) @@ -249,6 +246,7 @@ static inline void kceNonstallIntrCheckAndClear_b3696a(OBJGPU *arg0, struct Kern return; } + #ifdef __nvoc_kernel_ce_h_disabled static inline void kceNonstallIntrCheckAndClear(OBJGPU *arg0, struct KernelCE *arg1, struct THREAD_STATE_NODE *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelCE was disabled!"); @@ -261,6 +259,7 @@ static inline void kceNonstallIntrCheckAndClear(OBJGPU *arg0, struct KernelCE *a NV_STATUS kceUpdateClassDB_KERNEL(OBJGPU *pGpu, struct KernelCE *pKCe); + #ifdef __nvoc_kernel_ce_h_disabled static inline NV_STATUS kceUpdateClassDB(OBJGPU *pGpu, struct KernelCE *pKCe) { NV_ASSERT_FAILED_PRECOMP("KernelCE was disabled!"); @@ -274,6 +273,7 @@ static inline NV_STATUS kceUpdateClassDB(OBJGPU *pGpu, struct KernelCE *pKCe) { NvBool kceIsCeSysmemRead_GP100(OBJGPU *pGpu, struct KernelCE *pKCe); + #ifdef __nvoc_kernel_ce_h_disabled static inline NvBool kceIsCeSysmemRead(OBJGPU *pGpu, struct KernelCE *pKCe) { NV_ASSERT_FAILED_PRECOMP("KernelCE was disabled!"); @@ -287,6 +287,7 @@ static inline NvBool kceIsCeSysmemRead(OBJGPU *pGpu, struct KernelCE *pKCe) { NvBool kceIsCeSysmemWrite_GP100(OBJGPU *pGpu, struct KernelCE *pKCe); + #ifdef __nvoc_kernel_ce_h_disabled static inline NvBool kceIsCeSysmemWrite(OBJGPU *pGpu, struct KernelCE *pKCe) { NV_ASSERT_FAILED_PRECOMP("KernelCE was disabled!"); @@ -300,6 +301,7 @@ static inline NvBool kceIsCeSysmemWrite(OBJGPU *pGpu, struct KernelCE *pKCe) { NvBool kceIsCeNvlinkP2P_GP100(OBJGPU *pGpu, struct KernelCE *pKCe); + #ifdef __nvoc_kernel_ce_h_disabled static inline NvBool kceIsCeNvlinkP2P(OBJGPU *pGpu, struct KernelCE *pKCe) { NV_ASSERT_FAILED_PRECOMP("KernelCE was disabled!"); @@ -313,6 +315,7 @@ static inline NvBool kceIsCeNvlinkP2P(OBJGPU *pGpu, struct KernelCE *pKCe) { NV_STATUS kceGetP2PCes_GV100(struct KernelCE *arg0, OBJGPU *pGpu, NvU32 gpuMask, NvU32 *nvlinkP2PCeMask); + #ifdef __nvoc_kernel_ce_h_disabled static inline NV_STATUS kceGetP2PCes(struct KernelCE *arg0, OBJGPU *pGpu, NvU32 gpuMask, NvU32 *nvlinkP2PCeMask) { NV_ASSERT_FAILED_PRECOMP("KernelCE was disabled!"); @@ -326,6 +329,7 @@ static inline NV_STATUS kceGetP2PCes(struct KernelCE *arg0, OBJGPU *pGpu, NvU32 void kceGetSysmemRWLCEs_GV100(struct KernelCE *arg0, NvU32 *rd, NvU32 *wr); + #ifdef __nvoc_kernel_ce_h_disabled static inline void kceGetSysmemRWLCEs(struct KernelCE *arg0, NvU32 *rd, NvU32 *wr) { NV_ASSERT_FAILED_PRECOMP("KernelCE was disabled!"); @@ -338,6 +342,7 @@ static inline void kceGetSysmemRWLCEs(struct KernelCE *arg0, NvU32 *rd, NvU32 *w void kceClearAssignedNvlinkPeerMasks_GV100(OBJGPU *pGpu, struct KernelCE *pKCe); + #ifdef __nvoc_kernel_ce_h_disabled static inline void kceClearAssignedNvlinkPeerMasks(OBJGPU *pGpu, struct KernelCE *pKCe) { NV_ASSERT_FAILED_PRECOMP("KernelCE was disabled!"); @@ -350,6 +355,7 @@ static inline void kceClearAssignedNvlinkPeerMasks(OBJGPU *pGpu, struct KernelCE NvBool kceGetAutoConfigTableEntry_GV100(OBJGPU *pGpu, struct KernelCE *pKCe, struct NVLINK_TOPOLOGY_PARAMS *arg0, struct NVLINK_CE_AUTO_CONFIG_TABLE *arg1, NvU32 arg2, NvU32 *arg3, NvU32 *arg4); + #ifdef __nvoc_kernel_ce_h_disabled static inline NvBool kceGetAutoConfigTableEntry(OBJGPU *pGpu, struct KernelCE *pKCe, struct NVLINK_TOPOLOGY_PARAMS *arg0, struct NVLINK_CE_AUTO_CONFIG_TABLE *arg1, NvU32 arg2, NvU32 *arg3, NvU32 *arg4) { NV_ASSERT_FAILED_PRECOMP("KernelCE was disabled!"); @@ -361,6 +367,20 @@ static inline NvBool kceGetAutoConfigTableEntry(OBJGPU *pGpu, struct KernelCE *p #define kceGetAutoConfigTableEntry_HAL(pGpu, pKCe, arg0, arg1, arg2, arg3, arg4) kceGetAutoConfigTableEntry(pGpu, pKCe, arg0, arg1, arg2, arg3, arg4) +NvU32 kceGetGrceConfigSize1_TU102(struct KernelCE *arg0); + + +#ifdef __nvoc_kernel_ce_h_disabled +static inline NvU32 kceGetGrceConfigSize1(struct KernelCE *arg0) { + NV_ASSERT_FAILED_PRECOMP("KernelCE was disabled!"); + return 0; +} +#else //__nvoc_kernel_ce_h_disabled +#define kceGetGrceConfigSize1(arg0) kceGetGrceConfigSize1_TU102(arg0) +#endif //__nvoc_kernel_ce_h_disabled + +#define kceGetGrceConfigSize1_HAL(arg0) kceGetGrceConfigSize1(arg0) + NV_STATUS kceConstructEngine_IMPL(OBJGPU *pGpu, struct KernelCE *pKCe, ENGDESCRIPTOR arg0); static inline NV_STATUS kceConstructEngine_DISPATCH(OBJGPU *pGpu, struct KernelCE *pKCe, ENGDESCRIPTOR arg0) { @@ -369,37 +389,19 @@ static inline NV_STATUS kceConstructEngine_DISPATCH(OBJGPU *pGpu, struct KernelC NvBool kceIsPresent_IMPL(OBJGPU *pGpu, struct KernelCE *pKCe); -static inline NvBool kceIsPresent_491d52(OBJGPU *pGpu, struct KernelCE *pKCe) { - return ((NvBool)(0 != 0)); -} - static inline NvBool kceIsPresent_DISPATCH(OBJGPU *pGpu, struct KernelCE *pKCe) { return pKCe->__kceIsPresent__(pGpu, pKCe); } NV_STATUS kceStateLoad_GP100(OBJGPU *arg0, struct KernelCE *arg1, NvU32 arg2); -static inline NV_STATUS kceStateLoad_46f6a7(OBJGPU *arg0, struct KernelCE *arg1, NvU32 arg2) { - return NV_ERR_NOT_SUPPORTED; -} - static inline NV_STATUS kceStateLoad_DISPATCH(OBJGPU *arg0, struct KernelCE *arg1, NvU32 arg2) { return arg1->__kceStateLoad__(arg0, arg1, arg2); } -NV_STATUS kceStateUnload_GP100(OBJGPU *pGpu, struct KernelCE *pKCe, NvU32 flags); +void kceRegisterIntrService_IMPL(OBJGPU *arg0, struct KernelCE *arg1, IntrServiceRecord arg2[163]); -static inline NV_STATUS kceStateUnload_56cd7a(OBJGPU *pGpu, struct KernelCE *pKCe, NvU32 flags) { - return NV_OK; -} - -static inline NV_STATUS kceStateUnload_DISPATCH(OBJGPU *pGpu, struct KernelCE *pKCe, NvU32 flags) { - return pKCe->__kceStateUnload__(pGpu, pKCe, flags); -} - -void kceRegisterIntrService_IMPL(OBJGPU *arg0, struct KernelCE *arg1, IntrServiceRecord arg2[155]); - -static inline void kceRegisterIntrService_DISPATCH(OBJGPU *arg0, struct KernelCE *arg1, IntrServiceRecord arg2[155]) { +static inline void kceRegisterIntrService_DISPATCH(OBJGPU *arg0, struct KernelCE *arg1, IntrServiceRecord arg2[163]) { arg1->__kceRegisterIntrService__(arg0, arg1, arg2); } @@ -413,10 +415,6 @@ NV_STATUS kceGetNvlinkAutoConfigCeValues_TU102(OBJGPU *pGpu, struct KernelCE *pK NV_STATUS kceGetNvlinkAutoConfigCeValues_GA100(OBJGPU *pGpu, struct KernelCE *pKCe, NvU32 *arg0, NvU32 *arg1, NvU32 *arg2); -static inline NV_STATUS kceGetNvlinkAutoConfigCeValues_56cd7a(OBJGPU *pGpu, struct KernelCE *pKCe, NvU32 *arg0, NvU32 *arg1, NvU32 *arg2) { - return NV_OK; -} - static inline NV_STATUS kceGetNvlinkAutoConfigCeValues_DISPATCH(OBJGPU *pGpu, struct KernelCE *pKCe, NvU32 *arg0, NvU32 *arg1, NvU32 *arg2) { return pKCe->__kceGetNvlinkAutoConfigCeValues__(pGpu, pKCe, arg0, arg1, arg2); } @@ -441,18 +439,6 @@ static inline NvBool kceIsCurrentMaxTopology_DISPATCH(OBJGPU *pGpu, struct Kerne return arg0->__kceIsCurrentMaxTopology__(pGpu, arg0, arg1, arg2, arg3); } -NvU32 kceGetGrceConfigSize1_TU102(struct KernelCE *arg0); - -NvU32 kceGetGrceConfigSize1_GA100(struct KernelCE *arg0); - -static inline NvU32 kceGetGrceConfigSize1_4a4dee(struct KernelCE *arg0) { - return 0; -} - -static inline NvU32 kceGetGrceConfigSize1_DISPATCH(struct KernelCE *arg0) { - return arg0->__kceGetGrceConfigSize1__(arg0); -} - NvU32 kceGetPce2lceConfigSize1_TU102(struct KernelCE *arg0); NvU32 kceGetPce2lceConfigSize1_GA100(struct KernelCE *arg0); @@ -461,10 +447,6 @@ NvU32 kceGetPce2lceConfigSize1_GA102(struct KernelCE *arg0); NvU32 kceGetPce2lceConfigSize1_GH100(struct KernelCE *arg0); -static inline NvU32 kceGetPce2lceConfigSize1_4a4dee(struct KernelCE *arg0) { - return 0; -} - static inline NvU32 kceGetPce2lceConfigSize1_DISPATCH(struct KernelCE *arg0) { return arg0->__kceGetPce2lceConfigSize1__(arg0); } @@ -599,6 +581,10 @@ static inline NV_STATUS kceReconcileTunableState_DISPATCH(POBJGPU pGpu, struct K return pEngstate->__kceReconcileTunableState__(pGpu, pEngstate, pTunableState); } +static inline NV_STATUS kceStateUnload_DISPATCH(POBJGPU pGpu, struct KernelCE *pEngstate, NvU32 arg0) { + return pEngstate->__kceStateUnload__(pGpu, pEngstate, arg0); +} + static inline NV_STATUS kceStateInitLocked_DISPATCH(POBJGPU pGpu, struct KernelCE *pEngstate) { return pEngstate->__kceStateInitLocked__(pGpu, pEngstate); } @@ -667,7 +653,11 @@ static inline NvU32 kceServiceInterrupt_DISPATCH(OBJGPU *pGpu, struct KernelCE * return pIntrService->__kceServiceInterrupt__(pGpu, pIntrService, pParams); } +NV_STATUS kceFindFirstInstance_IMPL(OBJGPU *pGpu, struct KernelCE **ppKCe); + +#define kceFindFirstInstance(pGpu, ppKCe) kceFindFirstInstance_IMPL(pGpu, ppKCe) NV_STATUS kceTopLevelPceLceMappingsUpdate_IMPL(OBJGPU *pGpu, struct KernelCE *pKCe); + #ifdef __nvoc_kernel_ce_h_disabled static inline NV_STATUS kceTopLevelPceLceMappingsUpdate(OBJGPU *pGpu, struct KernelCE *pKCe) { NV_ASSERT_FAILED_PRECOMP("KernelCE was disabled!"); @@ -678,20 +668,35 @@ static inline NV_STATUS kceTopLevelPceLceMappingsUpdate(OBJGPU *pGpu, struct Ker #endif //__nvoc_kernel_ce_h_disabled NV_STATUS kceGetFaultMethodBufferSize_IMPL(OBJGPU *pGpu, NvU32 *size); + #define kceGetFaultMethodBufferSize(pGpu, size) kceGetFaultMethodBufferSize_IMPL(pGpu, size) NV_STATUS kceGetAvailableHubPceMask_IMPL(OBJGPU *pGpu, NVLINK_TOPOLOGY_PARAMS *pTopoParams); + #define kceGetAvailableHubPceMask(pGpu, pTopoParams) kceGetAvailableHubPceMask_IMPL(pGpu, pTopoParams) -NV_STATUS kceGetDeviceCaps_IMPL(OBJGPU *gpu, struct KernelCE *pKCe, NvU32 engineType, NvU8 *ceCaps); +NV_STATUS kceGetDeviceCaps_IMPL(OBJGPU *gpu, struct KernelCE *pKCe, RM_ENGINE_TYPE rmEngineType, NvU8 *ceCaps); + #ifdef __nvoc_kernel_ce_h_disabled -static inline NV_STATUS kceGetDeviceCaps(OBJGPU *gpu, struct KernelCE *pKCe, NvU32 engineType, NvU8 *ceCaps) { +static inline NV_STATUS kceGetDeviceCaps(OBJGPU *gpu, struct KernelCE *pKCe, RM_ENGINE_TYPE rmEngineType, NvU8 *ceCaps) { NV_ASSERT_FAILED_PRECOMP("KernelCE was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_ce_h_disabled -#define kceGetDeviceCaps(gpu, pKCe, engineType, ceCaps) kceGetDeviceCaps_IMPL(gpu, pKCe, engineType, ceCaps) +#define kceGetDeviceCaps(gpu, pKCe, rmEngineType, ceCaps) kceGetDeviceCaps_IMPL(gpu, pKCe, rmEngineType, ceCaps) +#endif //__nvoc_kernel_ce_h_disabled + +NV_STATUS kceFindShimOwner_IMPL(OBJGPU *gpu, struct KernelCE *pKCe, struct KernelCE **ppKCe); + +#ifdef __nvoc_kernel_ce_h_disabled +static inline NV_STATUS kceFindShimOwner(OBJGPU *gpu, struct KernelCE *pKCe, struct KernelCE **ppKCe) { + NV_ASSERT_FAILED_PRECOMP("KernelCE was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_ce_h_disabled +#define kceFindShimOwner(gpu, pKCe, ppKCe) kceFindShimOwner_IMPL(gpu, pKCe, ppKCe) #endif //__nvoc_kernel_ce_h_disabled NV_STATUS kceGetCeFromNvlinkConfig_IMPL(OBJGPU *pGpu, struct KernelCE *pKCe, NvU32 arg0, NvU32 *arg1, NvU32 *arg2, NvU32 *arg3); + #ifdef __nvoc_kernel_ce_h_disabled static inline NV_STATUS kceGetCeFromNvlinkConfig(OBJGPU *pGpu, struct KernelCE *pKCe, NvU32 arg0, NvU32 *arg1, NvU32 *arg2, NvU32 *arg3) { NV_ASSERT_FAILED_PRECOMP("KernelCE was disabled!"); @@ -704,6 +709,51 @@ static inline NV_STATUS kceGetCeFromNvlinkConfig(OBJGPU *pGpu, struct KernelCE * #undef PRIVATE_FIELD +// Iterate over all KCE objects +#define KCE_ITER_ALL_BEGIN(pGpu, pKCeIter, si) \ + { \ + NvU32 maxCe = gpuGetNumCEs(pGpu); \ + NvU32 kceInst; \ + for (kceInst = (si); kceInst < maxCe; kceInst++) \ + { \ + pKCeIter = GPU_GET_KCE(pGpu, kceInst); \ + if (pKCeIter == NULL) \ + { \ + continue; \ + } + +// Iterate over all CE visible to hClient +#define KCE_ITER_CLIENT_BEGIN(pGpu, pKCeIter, hClient) \ + { \ + NvU32 maxCe = ENG_CE__SIZE_1; \ + NV_STATUS kceStatus; \ + NvU32 kceInst; \ + NvU32 kceIdx; \ + for (kceInst = 0; kceInst < maxCe; kceInst++) \ + { \ + kceStatus = ceIndexFromType(pGpu, hClient, RM_ENGINE_TYPE_COPY(kceInst), &kceIdx); \ + if (kceStatus != NV_OK) \ + { \ + continue; \ + } \ + pKCeIter = GPU_GET_KCE(pGpu, kceIdx); \ + if (pKCeIter == NULL) \ + { \ + continue; \ + } + +#define KCE_ITER_END \ + } \ + } + +#define KCE_ITER_END_OR_RETURN_ERROR \ + } \ + if (kceInst == maxCe) \ + { \ + return NV_ERR_INSUFFICIENT_RESOURCES; \ + } \ + } + #endif // KERNEL_CE_H #ifdef __cplusplus diff --git a/src/nvidia/generated/g_kernel_channel_group_api_nvoc.c b/src/nvidia/generated/g_kernel_channel_group_api_nvoc.c index 6659c48ed..f4edd147a 100644 --- a/src/nvidia/generated/g_kernel_channel_group_api_nvoc.c +++ b/src/nvidia/generated/g_kernel_channel_group_api_nvoc.c @@ -165,6 +165,10 @@ static NV_STATUS __nvoc_thunk_RsResource_kchangrpapiUnmapFrom(struct KernelChann return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_kchangrpapiIsDuplicate(struct KernelChannelGroupApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_kchangrpapiControl_Epilogue(struct KernelChannelGroupApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RmResource.offset), pCallContext, pParams); } @@ -368,12 +372,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh #endif }, { /* [12] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x142200u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) kchangrpapiCtrlCmdInternalPromoteFaultMethodBuffers_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) - /*flags=*/ 0x2200u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x142200u) + /*flags=*/ 0x142200u, /*accessRight=*/0x0u, /*methodId=*/ 0xa06c010au, /*paramSize=*/ sizeof(NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS), @@ -507,7 +511,7 @@ static void __nvoc_init_funcTable_KernelChannelGroupApi_1(KernelChannelGroupApi pThis->__kchangrpapiCtrlCmdProgramVidmemPromote__ = &kchangrpapiCtrlCmdProgramVidmemPromote_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x142200u) pThis->__kchangrpapiCtrlCmdInternalPromoteFaultMethodBuffers__ = &kchangrpapiCtrlCmdInternalPromoteFaultMethodBuffers_IMPL; #endif @@ -575,6 +579,8 @@ static void __nvoc_init_funcTable_KernelChannelGroupApi_1(KernelChannelGroupApi pThis->__kchangrpapiUnmapFrom__ = &__nvoc_thunk_RsResource_kchangrpapiUnmapFrom; + pThis->__kchangrpapiIsDuplicate__ = &__nvoc_thunk_RsResource_kchangrpapiIsDuplicate; + pThis->__kchangrpapiControl_Epilogue__ = &__nvoc_thunk_RmResource_kchangrpapiControl_Epilogue; pThis->__kchangrpapiControlLookup__ = &__nvoc_thunk_RsResource_kchangrpapiControlLookup; diff --git a/src/nvidia/generated/g_kernel_channel_group_api_nvoc.h b/src/nvidia/generated/g_kernel_channel_group_api_nvoc.h index c9f69eeb3..3bb218f44 100644 --- a/src/nvidia/generated/g_kernel_channel_group_api_nvoc.h +++ b/src/nvidia/generated/g_kernel_channel_group_api_nvoc.h @@ -118,6 +118,7 @@ struct KernelChannelGroupApi { NV_STATUS (*__kchangrpapiInternalControlForward__)(struct KernelChannelGroupApi *, NvU32, void *, NvU32); void (*__kchangrpapiPreDestruct__)(struct KernelChannelGroupApi *); NV_STATUS (*__kchangrpapiUnmapFrom__)(struct KernelChannelGroupApi *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__kchangrpapiIsDuplicate__)(struct KernelChannelGroupApi *, NvHandle, NvBool *); void (*__kchangrpapiControl_Epilogue__)(struct KernelChannelGroupApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kchangrpapiControlLookup__)(struct KernelChannelGroupApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__kchangrpapiMap__)(struct KernelChannelGroupApi *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -128,6 +129,7 @@ struct KernelChannelGroupApi { NvHandle hKernelGraphicsContext; NvHandle hLegacykCtxShareSync; NvHandle hLegacykCtxShareAsync; + NvHandle hVASpace; }; #ifndef __NVOC_CLASS_KernelChannelGroupApi_TYPEDEF__ @@ -193,6 +195,7 @@ NV_STATUS __nvoc_objCreate_KernelChannelGroupApi(KernelChannelGroupApi**, Dynami #define kchangrpapiInternalControlForward(pGpuResource, command, pParams, size) kchangrpapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define kchangrpapiPreDestruct(pResource) kchangrpapiPreDestruct_DISPATCH(pResource) #define kchangrpapiUnmapFrom(pResource, pParams) kchangrpapiUnmapFrom_DISPATCH(pResource, pParams) +#define kchangrpapiIsDuplicate(pResource, hMemory, pDuplicate) kchangrpapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define kchangrpapiControl_Epilogue(pResource, pCallContext, pParams) kchangrpapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define kchangrpapiControlLookup(pResource, pParams, ppEntry) kchangrpapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define kchangrpapiMap(pGpuResource, pCallContext, pParams, pCpuMapping) kchangrpapiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -383,6 +386,10 @@ static inline NV_STATUS kchangrpapiUnmapFrom_DISPATCH(struct KernelChannelGroupA return pResource->__kchangrpapiUnmapFrom__(pResource, pParams); } +static inline NV_STATUS kchangrpapiIsDuplicate_DISPATCH(struct KernelChannelGroupApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__kchangrpapiIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void kchangrpapiControl_Epilogue_DISPATCH(struct KernelChannelGroupApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__kchangrpapiControl_Epilogue__(pResource, pCallContext, pParams); } @@ -400,8 +407,10 @@ static inline NvBool kchangrpapiAccessCallback_DISPATCH(struct KernelChannelGrou } NV_STATUS kchangrpapiConstruct_IMPL(struct KernelChannelGroupApi *arg_pKernelChannelGroupApi, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_kchangrpapiConstruct(arg_pKernelChannelGroupApi, arg_pCallContext, arg_pParams) kchangrpapiConstruct_IMPL(arg_pKernelChannelGroupApi, arg_pCallContext, arg_pParams) NV_STATUS kchangrpapiCopyConstruct_IMPL(struct KernelChannelGroupApi *pKernelChannelGroupApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); + #ifdef __nvoc_kernel_channel_group_api_h_disabled static inline NV_STATUS kchangrpapiCopyConstruct(struct KernelChannelGroupApi *pKernelChannelGroupApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { NV_ASSERT_FAILED_PRECOMP("KernelChannelGroupApi was disabled!"); @@ -412,6 +421,7 @@ static inline NV_STATUS kchangrpapiCopyConstruct(struct KernelChannelGroupApi *p #endif //__nvoc_kernel_channel_group_api_h_disabled void kchangrpapiDestruct_IMPL(struct KernelChannelGroupApi *pKernelChannelGroupApi); + #define __nvoc_kchangrpapiDestruct(pKernelChannelGroupApi) kchangrpapiDestruct_IMPL(pKernelChannelGroupApi) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_kernel_channel_group_nvoc.h b/src/nvidia/generated/g_kernel_channel_group_nvoc.h index ed4857619..9b6ac5f44 100644 --- a/src/nvidia/generated/g_kernel_channel_group_nvoc.h +++ b/src/nvidia/generated/g_kernel_channel_group_nvoc.h @@ -124,7 +124,7 @@ struct KernelChannelGroup { NvU32 grpID; NvU32 runlistId; NvU32 chanCount; - NvU32 engineType; + RM_ENGINE_TYPE engineType; struct OBJVASPACE *pVAS; NvU32 gfid; struct OBJEHEAP *pSubctxIdHeap; @@ -178,6 +178,9 @@ static inline NV_STATUS kchangrpSetInterleaveLevelSched_56cd7a(struct OBJGPU *pG return NV_OK; } +NV_STATUS kchangrpSetInterleaveLevelSched_GM107(struct OBJGPU *pGpu, struct KernelChannelGroup *pKernelChannelGroup, NvU32 value); + + #ifdef __nvoc_kernel_channel_group_h_disabled static inline NV_STATUS kchangrpSetInterleaveLevelSched(struct OBJGPU *pGpu, struct KernelChannelGroup *pKernelChannelGroup, NvU32 value) { NV_ASSERT_FAILED_PRECOMP("KernelChannelGroup was disabled!"); @@ -191,6 +194,7 @@ static inline NV_STATUS kchangrpSetInterleaveLevelSched(struct OBJGPU *pGpu, str NvU32 kchangrpGetDefaultRunlist_GM107(struct OBJGPU *pGpu, struct KernelChannelGroup *pKernelChannelGroup); + #ifdef __nvoc_kernel_channel_group_h_disabled static inline NvU32 kchangrpGetDefaultRunlist(struct OBJGPU *pGpu, struct KernelChannelGroup *pKernelChannelGroup) { NV_ASSERT_FAILED_PRECOMP("KernelChannelGroup was disabled!"); @@ -206,6 +210,9 @@ static inline void kchangrpUpdateSubcontextMask_b3696a(struct OBJGPU *pGpu, stru return; } +void kchangrpUpdateSubcontextMask_GV100(struct OBJGPU *pGpu, struct KernelChannelGroup *arg0, NvU32 arg1, NvBool arg2); + + #ifdef __nvoc_kernel_channel_group_h_disabled static inline void kchangrpUpdateSubcontextMask(struct OBJGPU *pGpu, struct KernelChannelGroup *arg0, NvU32 arg1, NvBool arg2) { NV_ASSERT_FAILED_PRECOMP("KernelChannelGroup was disabled!"); @@ -220,6 +227,7 @@ static inline void kchangrpSetSubcontextZombieState_b3696a(struct OBJGPU *pGpu, return; } + #ifdef __nvoc_kernel_channel_group_h_disabled static inline void kchangrpSetSubcontextZombieState(struct OBJGPU *pGpu, struct KernelChannelGroup *arg0, NvU32 arg1, NvBool arg2) { NV_ASSERT_FAILED_PRECOMP("KernelChannelGroup was disabled!"); @@ -235,6 +243,7 @@ static inline NvBool kchangrpGetSubcontextZombieState_ceaee8(struct OBJGPU *pGpu return ((NvBool)(0 != 0)); } + #ifdef __nvoc_kernel_channel_group_h_disabled static inline NvBool kchangrpGetSubcontextZombieState(struct OBJGPU *pGpu, struct KernelChannelGroup *arg0, NvU32 arg1) { NV_ASSERT_FAILED_PRECOMP("KernelChannelGroup was disabled!"); @@ -250,6 +259,7 @@ static inline NV_STATUS kchangrpFreeGrSubcontextHdrs_56cd7a(struct OBJGPU *pGpu, return NV_OK; } + #ifdef __nvoc_kernel_channel_group_h_disabled static inline NV_STATUS kchangrpFreeGrSubcontextHdrs(struct OBJGPU *pGpu, struct KernelChannelGroup *arg0) { NV_ASSERT_FAILED_PRECOMP("KernelChannelGroup was disabled!"); @@ -263,6 +273,7 @@ static inline NV_STATUS kchangrpFreeGrSubcontextHdrs(struct OBJGPU *pGpu, struct NV_STATUS kchangrpAllocFaultMethodBuffers_GV100(struct OBJGPU *pGpu, struct KernelChannelGroup *pKernelChannelGroup); + #ifdef __nvoc_kernel_channel_group_h_disabled static inline NV_STATUS kchangrpAllocFaultMethodBuffers(struct OBJGPU *pGpu, struct KernelChannelGroup *pKernelChannelGroup) { NV_ASSERT_FAILED_PRECOMP("KernelChannelGroup was disabled!"); @@ -276,6 +287,7 @@ static inline NV_STATUS kchangrpAllocFaultMethodBuffers(struct OBJGPU *pGpu, str NV_STATUS kchangrpFreeFaultMethodBuffers_GV100(struct OBJGPU *pGpu, struct KernelChannelGroup *pKernelChannelGroup); + #ifdef __nvoc_kernel_channel_group_h_disabled static inline NV_STATUS kchangrpFreeFaultMethodBuffers(struct OBJGPU *pGpu, struct KernelChannelGroup *pKernelChannelGroup) { NV_ASSERT_FAILED_PRECOMP("KernelChannelGroup was disabled!"); @@ -289,6 +301,7 @@ static inline NV_STATUS kchangrpFreeFaultMethodBuffers(struct OBJGPU *pGpu, stru NV_STATUS kchangrpMapFaultMethodBuffers_GV100(struct OBJGPU *pGpu, struct KernelChannelGroup *pKernelChannelGroup, NvU32 runqueue); + #ifdef __nvoc_kernel_channel_group_h_disabled static inline NV_STATUS kchangrpMapFaultMethodBuffers(struct OBJGPU *pGpu, struct KernelChannelGroup *pKernelChannelGroup, NvU32 runqueue) { NV_ASSERT_FAILED_PRECOMP("KernelChannelGroup was disabled!"); @@ -302,6 +315,7 @@ static inline NV_STATUS kchangrpMapFaultMethodBuffers(struct OBJGPU *pGpu, struc NV_STATUS kchangrpUnmapFaultMethodBuffers_GV100(struct OBJGPU *pGpu, struct KernelChannelGroup *pKernelChannelGroup, NvU32 runqueue); + #ifdef __nvoc_kernel_channel_group_h_disabled static inline NV_STATUS kchangrpUnmapFaultMethodBuffers(struct OBJGPU *pGpu, struct KernelChannelGroup *pKernelChannelGroup, NvU32 runqueue) { NV_ASSERT_FAILED_PRECOMP("KernelChannelGroup was disabled!"); @@ -317,6 +331,7 @@ static inline NV_STATUS kchangrpSetRealtime_56cd7a(struct OBJGPU *pGpu, struct K return NV_OK; } + #ifdef __nvoc_kernel_channel_group_h_disabled static inline NV_STATUS kchangrpSetRealtime(struct OBJGPU *pGpu, struct KernelChannelGroup *pKernelChannelGroup, NvBool bRealtime) { NV_ASSERT_FAILED_PRECOMP("KernelChannelGroup was disabled!"); @@ -329,10 +344,13 @@ static inline NV_STATUS kchangrpSetRealtime(struct OBJGPU *pGpu, struct KernelCh #define kchangrpSetRealtime_HAL(pGpu, pKernelChannelGroup, bRealtime) kchangrpSetRealtime(pGpu, pKernelChannelGroup, bRealtime) NV_STATUS kchangrpConstruct_IMPL(struct KernelChannelGroup *arg_pKernelChannelGroup); + #define __nvoc_kchangrpConstruct(arg_pKernelChannelGroup) kchangrpConstruct_IMPL(arg_pKernelChannelGroup) void kchangrpDestruct_IMPL(struct KernelChannelGroup *pKernelChannelGroup); + #define __nvoc_kchangrpDestruct(pKernelChannelGroup) kchangrpDestruct_IMPL(pKernelChannelGroup) void kchangrpSetState_IMPL(struct KernelChannelGroup *pKernelChannelGroup, NvU32 subdevice, CHANNELGROUP_STATE state); + #ifdef __nvoc_kernel_channel_group_h_disabled static inline void kchangrpSetState(struct KernelChannelGroup *pKernelChannelGroup, NvU32 subdevice, CHANNELGROUP_STATE state) { NV_ASSERT_FAILED_PRECOMP("KernelChannelGroup was disabled!"); @@ -342,6 +360,7 @@ static inline void kchangrpSetState(struct KernelChannelGroup *pKernelChannelGro #endif //__nvoc_kernel_channel_group_h_disabled void kchangrpClearState_IMPL(struct KernelChannelGroup *pKernelChannelGroup, NvU32 subdevice, CHANNELGROUP_STATE state); + #ifdef __nvoc_kernel_channel_group_h_disabled static inline void kchangrpClearState(struct KernelChannelGroup *pKernelChannelGroup, NvU32 subdevice, CHANNELGROUP_STATE state) { NV_ASSERT_FAILED_PRECOMP("KernelChannelGroup was disabled!"); @@ -351,6 +370,7 @@ static inline void kchangrpClearState(struct KernelChannelGroup *pKernelChannelG #endif //__nvoc_kernel_channel_group_h_disabled NvBool kchangrpIsStateSet_IMPL(struct KernelChannelGroup *pKernelChannelGroup, NvU32 subdevice, CHANNELGROUP_STATE state); + #ifdef __nvoc_kernel_channel_group_h_disabled static inline NvBool kchangrpIsStateSet(struct KernelChannelGroup *pKernelChannelGroup, NvU32 subdevice, CHANNELGROUP_STATE state) { NV_ASSERT_FAILED_PRECOMP("KernelChannelGroup was disabled!"); @@ -361,6 +381,7 @@ static inline NvBool kchangrpIsStateSet(struct KernelChannelGroup *pKernelChanne #endif //__nvoc_kernel_channel_group_h_disabled NV_STATUS kchangrpAddChannel_IMPL(struct OBJGPU *pGpu, struct KernelChannelGroup *pKernelChannelGroup, struct KernelChannel *pKernelChannel); + #ifdef __nvoc_kernel_channel_group_h_disabled static inline NV_STATUS kchangrpAddChannel(struct OBJGPU *pGpu, struct KernelChannelGroup *pKernelChannelGroup, struct KernelChannel *pKernelChannel) { NV_ASSERT_FAILED_PRECOMP("KernelChannelGroup was disabled!"); @@ -371,6 +392,7 @@ static inline NV_STATUS kchangrpAddChannel(struct OBJGPU *pGpu, struct KernelCha #endif //__nvoc_kernel_channel_group_h_disabled NV_STATUS kchangrpRemoveChannel_IMPL(struct OBJGPU *pGpu, struct KernelChannelGroup *pKernelChannelGroup, struct KernelChannel *pKernelChannel); + #ifdef __nvoc_kernel_channel_group_h_disabled static inline NV_STATUS kchangrpRemoveChannel(struct OBJGPU *pGpu, struct KernelChannelGroup *pKernelChannelGroup, struct KernelChannel *pKernelChannel) { NV_ASSERT_FAILED_PRECOMP("KernelChannelGroup was disabled!"); @@ -381,6 +403,7 @@ static inline NV_STATUS kchangrpRemoveChannel(struct OBJGPU *pGpu, struct Kernel #endif //__nvoc_kernel_channel_group_h_disabled NV_STATUS kchangrpInit_IMPL(struct OBJGPU *pGpu, struct KernelChannelGroup *pKernelChannelGroup, struct OBJVASPACE *pVAS, NvU32 gfid); + #ifdef __nvoc_kernel_channel_group_h_disabled static inline NV_STATUS kchangrpInit(struct OBJGPU *pGpu, struct KernelChannelGroup *pKernelChannelGroup, struct OBJVASPACE *pVAS, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelChannelGroup was disabled!"); @@ -391,6 +414,7 @@ static inline NV_STATUS kchangrpInit(struct OBJGPU *pGpu, struct KernelChannelGr #endif //__nvoc_kernel_channel_group_h_disabled NV_STATUS kchangrpDestroy_IMPL(struct OBJGPU *pGpu, struct KernelChannelGroup *pKernelChannelGroup); + #ifdef __nvoc_kernel_channel_group_h_disabled static inline NV_STATUS kchangrpDestroy(struct OBJGPU *pGpu, struct KernelChannelGroup *pKernelChannelGroup) { NV_ASSERT_FAILED_PRECOMP("KernelChannelGroup was disabled!"); @@ -401,6 +425,7 @@ static inline NV_STATUS kchangrpDestroy(struct OBJGPU *pGpu, struct KernelChanne #endif //__nvoc_kernel_channel_group_h_disabled NV_STATUS kchangrpAllocEngineContextDescriptor_IMPL(struct OBJGPU *pGpu, struct KernelChannelGroup *pKernelChannelGroup); + #ifdef __nvoc_kernel_channel_group_h_disabled static inline NV_STATUS kchangrpAllocEngineContextDescriptor(struct OBJGPU *pGpu, struct KernelChannelGroup *pKernelChannelGroup) { NV_ASSERT_FAILED_PRECOMP("KernelChannelGroup was disabled!"); @@ -411,6 +436,7 @@ static inline NV_STATUS kchangrpAllocEngineContextDescriptor(struct OBJGPU *pGpu #endif //__nvoc_kernel_channel_group_h_disabled NV_STATUS kchangrpGetEngineContextMemDesc_IMPL(struct OBJGPU *pGpu, struct KernelChannelGroup *arg0, MEMORY_DESCRIPTOR **arg1); + #ifdef __nvoc_kernel_channel_group_h_disabled static inline NV_STATUS kchangrpGetEngineContextMemDesc(struct OBJGPU *pGpu, struct KernelChannelGroup *arg0, MEMORY_DESCRIPTOR **arg1) { NV_ASSERT_FAILED_PRECOMP("KernelChannelGroup was disabled!"); @@ -421,6 +447,7 @@ static inline NV_STATUS kchangrpGetEngineContextMemDesc(struct OBJGPU *pGpu, str #endif //__nvoc_kernel_channel_group_h_disabled NV_STATUS kchangrpSetInterleaveLevel_IMPL(struct OBJGPU *pGpu, struct KernelChannelGroup *pKernelChannelGroup, NvU32 value); + #ifdef __nvoc_kernel_channel_group_h_disabled static inline NV_STATUS kchangrpSetInterleaveLevel(struct OBJGPU *pGpu, struct KernelChannelGroup *pKernelChannelGroup, NvU32 value) { NV_ASSERT_FAILED_PRECOMP("KernelChannelGroup was disabled!"); diff --git a/src/nvidia/generated/g_kernel_channel_nvoc.c b/src/nvidia/generated/g_kernel_channel_nvoc.c index 1b6accfe9..ec06a9c27 100644 --- a/src/nvidia/generated/g_kernel_channel_nvoc.c +++ b/src/nvidia/generated/g_kernel_channel_nvoc.c @@ -207,6 +207,10 @@ static void __nvoc_thunk_RsResource_kchannelPreDestruct(struct KernelChannel *pR resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannel_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_RsResource_kchannelIsDuplicate(struct KernelChannel *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannel_RsResource.offset), hMemory, pDuplicate); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_kchannelGetNotificationListPtr(struct KernelChannel *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelChannel_Notifier.offset)); } @@ -691,12 +695,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh #endif }, { /* [31] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x42204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) kchannelCtrlCmdMigrateEngineCtxData_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) - /*flags=*/ 0x2204u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x42204u) + /*flags=*/ 0x42204u, /*accessRight=*/0x0u, /*methodId=*/ 0xb06f010du, /*paramSize=*/ sizeof(NVB06F_CTRL_MIGRATE_ENGINE_CTX_DATA_PARAMS), @@ -736,12 +740,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh #endif }, { /* [34] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) kchannelCtrlCmdSetChannelHwState_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) - /*flags=*/ 0x2204u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u) + /*flags=*/ 0x102204u, /*accessRight=*/0x0u, /*methodId=*/ 0xb06f0110u, /*paramSize=*/ sizeof(NVB06F_CTRL_SET_CHANNEL_HW_STATE_PARAMS), @@ -766,12 +770,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh #endif }, { /* [36] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) kchannelCtrlCmdRestoreEngineCtxData_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) - /*flags=*/ 0x2204u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u) + /*flags=*/ 0x102204u, /*accessRight=*/0x0u, /*methodId=*/ 0xb06f0112u, /*paramSize=*/ sizeof(NVB06F_CTRL_RESTORE_ENGINE_CTX_DATA_PARAMS), @@ -1023,34 +1027,28 @@ static void __nvoc_init_funcTable_KernelChannel_1(KernelChannel *pThis, RmHalspe pThis->__kchannelCheckMemInterUnmap__ = &kchannelCheckMemInterUnmap_IMPL; // Hal function -- kchannelCreateUserMemDesc - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kchannelCreateUserMemDesc__ = &kchannelCreateUserMemDesc_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kchannelCreateUserMemDesc__ = &kchannelCreateUserMemDesc_GA10B; } - else if (0) - { - } // Hal function -- kchannelIsUserdAddrSizeValid if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__kchannelIsUserdAddrSizeValid__ = &kchannelIsUserdAddrSizeValid_GV100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kchannelIsUserdAddrSizeValid__ = &kchannelIsUserdAddrSizeValid_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kchannelIsUserdAddrSizeValid__ = &kchannelIsUserdAddrSizeValid_GH100; } - else if (0) - { - } #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) pThis->__kchannelCtrlCmdResetIsolatedChannel__ = &kchannelCtrlCmdResetIsolatedChannel_IMPL; @@ -1156,7 +1154,7 @@ static void __nvoc_init_funcTable_KernelChannel_1(KernelChannel *pThis, RmHalspe pThis->__kchannelCtrlCmdGetEngineCtxData__ = &kchannelCtrlCmdGetEngineCtxData_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x42204u) pThis->__kchannelCtrlCmdMigrateEngineCtxData__ = &kchannelCtrlCmdMigrateEngineCtxData_IMPL; #endif @@ -1168,7 +1166,7 @@ static void __nvoc_init_funcTable_KernelChannel_1(KernelChannel *pThis, RmHalspe pThis->__kchannelCtrlCmdGetChannelHwState__ = &kchannelCtrlCmdGetChannelHwState_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u) pThis->__kchannelCtrlCmdSetChannelHwState__ = &kchannelCtrlCmdSetChannelHwState_IMPL; #endif @@ -1176,7 +1174,7 @@ static void __nvoc_init_funcTable_KernelChannel_1(KernelChannel *pThis, RmHalspe pThis->__kchannelCtrlCmdSaveEngineCtxData__ = &kchannelCtrlCmdSaveEngineCtxData_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u) pThis->__kchannelCtrlCmdRestoreEngineCtxData__ = &kchannelCtrlCmdRestoreEngineCtxData_IMPL; #endif @@ -1292,6 +1290,8 @@ static void __nvoc_init_funcTable_KernelChannel_1(KernelChannel *pThis, RmHalspe pThis->__kchannelPreDestruct__ = &__nvoc_thunk_RsResource_kchannelPreDestruct; + pThis->__kchannelIsDuplicate__ = &__nvoc_thunk_RsResource_kchannelIsDuplicate; + pThis->__kchannelGetNotificationListPtr__ = &__nvoc_thunk_Notifier_kchannelGetNotificationListPtr; pThis->__kchannelGetNotificationShare__ = &__nvoc_thunk_Notifier_kchannelGetNotificationShare; diff --git a/src/nvidia/generated/g_kernel_channel_nvoc.h b/src/nvidia/generated/g_kernel_channel_nvoc.h index b6a27e0d8..740ecb5b3 100644 --- a/src/nvidia/generated/g_kernel_channel_nvoc.h +++ b/src/nvidia/generated/g_kernel_channel_nvoc.h @@ -39,6 +39,7 @@ extern "C" { #include "resserv/resserv.h" #include "nvoc/prelude.h" #include "gpu/gpu_resource.h" +#include "kernel/gpu/gpu_engine_type.h" #include "kernel/gpu/fifo/kernel_ctxshare.h" #include "kernel/gpu/fifo/kernel_fifo.h" #include "kernel/gpu/gr/kernel_graphics_context.h" @@ -84,14 +85,14 @@ typedef struct UserInfo UserInfo; /*! * @brief Type of hErrorContext or hEccErrorContext * - * This is RPCed to GSP in #NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS.internalFlags + * This is RPCed to GSP in #NV_CHANNEL_ALLOC_PARAMS.internalFlags * along with the actual memdesc in - * #NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS.errorNotifierMem and - * #NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS.eccErrorNotifierMem. + * #NV_CHANNEL_ALLOC_PARAMS.errorNotifierMem and + * #NV_CHANNEL_ALLOC_PARAMS.eccErrorNotifierMem. */ typedef enum { /*! - * Initial state as passed in NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS by + * Initial state as passed in NV_CHANNEL_ALLOC_PARAMS by * kernel CPU-RM clients. */ ERROR_NOTIFIER_TYPE_UNKNOWN = 0, @@ -113,7 +114,7 @@ typedef enum { // typedef struct { RS_ORDERED_ITERATOR rsIter; - NvU32 engineID; + RM_ENGINE_TYPE engineID; NvU32 classID; } KernelChannelChildIterator; @@ -169,7 +170,7 @@ typedef struct _def_instance_block MEMORY_DESCRIPTOR *pRLMemDesc; } FIFO_INSTANCE_BLOCK; -/* Bitfields in NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS.internalFlags */ +/* Bitfields in NV_CHANNEL_ALLOC_PARAMS.internalFlags */ #define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_PRIVILEGE 1:0 #define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_PRIVILEGE_USER 0x0 #define NV_KERNELCHANNEL_ALLOC_INTERNALFLAGS_PRIVILEGE_ADMIN 0x1 @@ -279,6 +280,7 @@ struct KernelChannel { NV_STATUS (*__kchannelUnregisterEvent__)(struct KernelChannel *, NvHandle, NvHandle, NvHandle, NvHandle); NvBool (*__kchannelCanCopy__)(struct KernelChannel *); void (*__kchannelPreDestruct__)(struct KernelChannel *); + NV_STATUS (*__kchannelIsDuplicate__)(struct KernelChannel *, NvHandle, NvBool *); PEVENTNOTIFICATION *(*__kchannelGetNotificationListPtr__)(struct KernelChannel *); struct NotifShare *(*__kchannelGetNotificationShare__)(struct KernelChannel *); NvBool (*__kchannelAccessCallback__)(struct KernelChannel *, struct RsClient *, void *, RsAccessRight); @@ -319,7 +321,7 @@ struct KernelChannel { NvU32 cid; struct MIG_INSTANCE_REF partitionRef; NvU32 runqueue; - NvU32 engineType; + RM_ENGINE_TYPE engineType; }; #ifndef __NVOC_CLASS_KernelChannel_TYPEDEF__ @@ -426,11 +428,13 @@ NV_STATUS __nvoc_objCreate_KernelChannel(KernelChannel**, Dynamic*, NvU32, CALL_ #define kchannelUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) kchannelUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define kchannelCanCopy(pResource) kchannelCanCopy_DISPATCH(pResource) #define kchannelPreDestruct(pResource) kchannelPreDestruct_DISPATCH(pResource) +#define kchannelIsDuplicate(pResource, hMemory, pDuplicate) kchannelIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define kchannelGetNotificationListPtr(pNotifier) kchannelGetNotificationListPtr_DISPATCH(pNotifier) #define kchannelGetNotificationShare(pNotifier) kchannelGetNotificationShare_DISPATCH(pNotifier) #define kchannelAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) kchannelAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS kchannelNotifyRc_IMPL(struct KernelChannel *pKernelChannel); + #ifdef __nvoc_kernel_channel_h_disabled static inline NV_STATUS kchannelNotifyRc(struct KernelChannel *pKernelChannel) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); @@ -444,6 +448,7 @@ static inline NV_STATUS kchannelNotifyRc(struct KernelChannel *pKernelChannel) { NvBool kchannelIsSchedulable_IMPL(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel); + #ifdef __nvoc_kernel_channel_h_disabled static inline NvBool kchannelIsSchedulable(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); @@ -457,6 +462,7 @@ static inline NvBool kchannelIsSchedulable(struct OBJGPU *pGpu, struct KernelCha NV_STATUS kchannelAllocMem_GM107(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, NvU32 Flags, NvU32 verifFlags); + #ifdef __nvoc_kernel_channel_h_disabled static inline NV_STATUS kchannelAllocMem(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, NvU32 Flags, NvU32 verifFlags) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); @@ -470,6 +476,7 @@ static inline NV_STATUS kchannelAllocMem(struct OBJGPU *pGpu, struct KernelChann void kchannelDestroyMem_GM107(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel); + #ifdef __nvoc_kernel_channel_h_disabled static inline void kchannelDestroyMem(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); @@ -482,6 +489,7 @@ static inline void kchannelDestroyMem(struct OBJGPU *pGpu, struct KernelChannel NV_STATUS kchannelGetChannelPhysicalState_KERNEL(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, NV208F_CTRL_FIFO_GET_CHANNEL_STATE_PARAMS *pChannelStateParams); + #ifdef __nvoc_kernel_channel_h_disabled static inline NV_STATUS kchannelGetChannelPhysicalState(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, NV208F_CTRL_FIFO_GET_CHANNEL_STATE_PARAMS *pChannelStateParams) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); @@ -498,6 +506,7 @@ static inline NvU32 kchannelEmbedRunlistIDForSMC_13cd8d(struct OBJGPU *pGpu, str return 0; } + #ifdef __nvoc_kernel_channel_h_disabled static inline NvU32 kchannelEmbedRunlistIDForSMC(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); @@ -511,6 +520,7 @@ static inline NvU32 kchannelEmbedRunlistIDForSMC(struct OBJGPU *pGpu, struct Ker NV_STATUS kchannelAllocHwID_GM107(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, NvHandle hClient, NvU32 Flags, NvU32 verifFlags2, NvU32 ChID); + #ifdef __nvoc_kernel_channel_h_disabled static inline NV_STATUS kchannelAllocHwID(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, NvHandle hClient, NvU32 Flags, NvU32 verifFlags2, NvU32 ChID) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); @@ -524,6 +534,7 @@ static inline NV_STATUS kchannelAllocHwID(struct OBJGPU *pGpu, struct KernelChan NV_STATUS kchannelFreeHwID_GM107(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel); + #ifdef __nvoc_kernel_channel_h_disabled static inline NV_STATUS kchannelFreeHwID(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); @@ -537,6 +548,7 @@ static inline NV_STATUS kchannelFreeHwID(struct OBJGPU *pGpu, struct KernelChann NV_STATUS kchannelGetUserdInfo_GM107(struct OBJGPU *pGpu, struct KernelChannel *arg0, NvU64 *userBase, NvU64 *offset, NvU64 *length); + #ifdef __nvoc_kernel_channel_h_disabled static inline NV_STATUS kchannelGetUserdInfo(struct OBJGPU *pGpu, struct KernelChannel *arg0, NvU64 *userBase, NvU64 *offset, NvU64 *length) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); @@ -550,6 +562,7 @@ static inline NV_STATUS kchannelGetUserdInfo(struct OBJGPU *pGpu, struct KernelC NV_STATUS kchannelGetUserdBar1MapOffset_GM107(struct OBJGPU *pGpu, struct KernelChannel *arg0, NvU64 *bar1Offset, NvU32 *bar1MapSize); + #ifdef __nvoc_kernel_channel_h_disabled static inline NV_STATUS kchannelGetUserdBar1MapOffset(struct OBJGPU *pGpu, struct KernelChannel *arg0, NvU64 *bar1Offset, NvU32 *bar1MapSize) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); @@ -563,6 +576,7 @@ static inline NV_STATUS kchannelGetUserdBar1MapOffset(struct OBJGPU *pGpu, struc NV_STATUS kchannelCreateUserdMemDescBc_GV100(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, NvHandle arg0, NvHandle *arg1, NvU64 *arg2); + #ifdef __nvoc_kernel_channel_h_disabled static inline NV_STATUS kchannelCreateUserdMemDescBc(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, NvHandle arg0, NvHandle *arg1, NvU64 *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); @@ -576,6 +590,7 @@ static inline NV_STATUS kchannelCreateUserdMemDescBc(struct OBJGPU *pGpu, struct NV_STATUS kchannelCreateUserdMemDesc_GV100(struct OBJGPU *pGpu, struct KernelChannel *arg0, NvHandle arg1, NvHandle arg2, NvU64 arg3, NvU64 *arg4, NvU32 *arg5); + #ifdef __nvoc_kernel_channel_h_disabled static inline NV_STATUS kchannelCreateUserdMemDesc(struct OBJGPU *pGpu, struct KernelChannel *arg0, NvHandle arg1, NvHandle arg2, NvU64 arg3, NvU64 *arg4, NvU32 *arg5) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); @@ -587,12 +602,12 @@ static inline NV_STATUS kchannelCreateUserdMemDesc(struct OBJGPU *pGpu, struct K #define kchannelCreateUserdMemDesc_HAL(pGpu, arg0, arg1, arg2, arg3, arg4, arg5) kchannelCreateUserdMemDesc(pGpu, arg0, arg1, arg2, arg3, arg4, arg5) -NV_STATUS kchannelDestroyUserdMemDesc_GV100(struct OBJGPU *pGpu, struct KernelChannel *arg0); +void kchannelDestroyUserdMemDesc_GV100(struct OBJGPU *pGpu, struct KernelChannel *arg0); + #ifdef __nvoc_kernel_channel_h_disabled -static inline NV_STATUS kchannelDestroyUserdMemDesc(struct OBJGPU *pGpu, struct KernelChannel *arg0) { +static inline void kchannelDestroyUserdMemDesc(struct OBJGPU *pGpu, struct KernelChannel *arg0) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); - return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_channel_h_disabled #define kchannelDestroyUserdMemDesc(pGpu, arg0) kchannelDestroyUserdMemDesc_GV100(pGpu, arg0) @@ -602,6 +617,7 @@ static inline NV_STATUS kchannelDestroyUserdMemDesc(struct OBJGPU *pGpu, struct NV_STATUS kchannelGetEngine_GM107(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, NvU32 *engDesc); + #ifdef __nvoc_kernel_channel_h_disabled static inline NV_STATUS kchannelGetEngine(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, NvU32 *engDesc) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); @@ -617,6 +633,7 @@ static inline NV_STATUS kchannelFwdToInternalCtrl_56cd7a(struct OBJGPU *pGpu, st return NV_OK; } + #ifdef __nvoc_kernel_channel_h_disabled static inline NV_STATUS kchannelFwdToInternalCtrl(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, NvU32 internalCmd, RmCtrlParams *pRmCtrlParams) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); @@ -628,12 +645,13 @@ static inline NV_STATUS kchannelFwdToInternalCtrl(struct OBJGPU *pGpu, struct Ke #define kchannelFwdToInternalCtrl_HAL(pGpu, pKernelChannel, internalCmd, pRmCtrlParams) kchannelFwdToInternalCtrl(pGpu, pKernelChannel, internalCmd, pRmCtrlParams) -static inline NV_STATUS kchannelAllocChannel_56cd7a(struct KernelChannel *pKernelChannel, NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS *pChannelGpfifoParams) { +static inline NV_STATUS kchannelAllocChannel_56cd7a(struct KernelChannel *pKernelChannel, NV_CHANNEL_ALLOC_PARAMS *pChannelGpfifoParams) { return NV_OK; } + #ifdef __nvoc_kernel_channel_h_disabled -static inline NV_STATUS kchannelAllocChannel(struct KernelChannel *pKernelChannel, NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS *pChannelGpfifoParams) { +static inline NV_STATUS kchannelAllocChannel(struct KernelChannel *pKernelChannel, NV_CHANNEL_ALLOC_PARAMS *pChannelGpfifoParams) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -647,6 +665,7 @@ static inline NvBool kchannelIsValid_cbe027(struct KernelChannel *pKernelChannel return ((NvBool)(0 == 0)); } + #ifdef __nvoc_kernel_channel_h_disabled static inline NvBool kchannelIsValid(struct KernelChannel *pKernelChannel) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); @@ -658,21 +677,23 @@ static inline NvBool kchannelIsValid(struct KernelChannel *pKernelChannel) { #define kchannelIsValid_HAL(pKernelChannel) kchannelIsValid(pKernelChannel) -NV_STATUS kchannelGetClassEngineID_GM107(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, NvHandle handle, NvU32 *classEngineID, NvU32 *classID, NvU32 *engineID); +NV_STATUS kchannelGetClassEngineID_GM107(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, NvHandle handle, NvU32 *classEngineID, NvU32 *classID, RM_ENGINE_TYPE *rmEngineID); + #ifdef __nvoc_kernel_channel_h_disabled -static inline NV_STATUS kchannelGetClassEngineID(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, NvHandle handle, NvU32 *classEngineID, NvU32 *classID, NvU32 *engineID) { +static inline NV_STATUS kchannelGetClassEngineID(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, NvHandle handle, NvU32 *classEngineID, NvU32 *classID, RM_ENGINE_TYPE *rmEngineID) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_channel_h_disabled -#define kchannelGetClassEngineID(pGpu, pKernelChannel, handle, classEngineID, classID, engineID) kchannelGetClassEngineID_GM107(pGpu, pKernelChannel, handle, classEngineID, classID, engineID) +#define kchannelGetClassEngineID(pGpu, pKernelChannel, handle, classEngineID, classID, rmEngineID) kchannelGetClassEngineID_GM107(pGpu, pKernelChannel, handle, classEngineID, classID, rmEngineID) #endif //__nvoc_kernel_channel_h_disabled -#define kchannelGetClassEngineID_HAL(pGpu, pKernelChannel, handle, classEngineID, classID, engineID) kchannelGetClassEngineID(pGpu, pKernelChannel, handle, classEngineID, classID, engineID) +#define kchannelGetClassEngineID_HAL(pGpu, pKernelChannel, handle, classEngineID, classID, rmEngineID) kchannelGetClassEngineID(pGpu, pKernelChannel, handle, classEngineID, classID, rmEngineID) NV_STATUS kchannelEnableVirtualContext_GM107(struct KernelChannel *arg0); + #ifdef __nvoc_kernel_channel_h_disabled static inline NV_STATUS kchannelEnableVirtualContext(struct KernelChannel *arg0) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); @@ -718,10 +739,6 @@ NV_STATUS kchannelCreateUserMemDesc_GM107(struct OBJGPU *pGpu, struct KernelChan NV_STATUS kchannelCreateUserMemDesc_GA10B(struct OBJGPU *pGpu, struct KernelChannel *arg0); -static inline NV_STATUS kchannelCreateUserMemDesc_56cd7a(struct OBJGPU *pGpu, struct KernelChannel *arg0) { - return NV_OK; -} - static inline NV_STATUS kchannelCreateUserMemDesc_DISPATCH(struct OBJGPU *pGpu, struct KernelChannel *arg0) { return arg0->__kchannelCreateUserMemDesc__(pGpu, arg0); } @@ -732,10 +749,6 @@ NvBool kchannelIsUserdAddrSizeValid_GA100(struct KernelChannel *pKernelChannel, NvBool kchannelIsUserdAddrSizeValid_GH100(struct KernelChannel *pKernelChannel, NvU32 userdAddrLo, NvU32 userdAddrHi); -static inline NvBool kchannelIsUserdAddrSizeValid_cbe027(struct KernelChannel *pKernelChannel, NvU32 userdAddrLo, NvU32 userdAddrHi) { - return ((NvBool)(0 == 0)); -} - static inline NvBool kchannelIsUserdAddrSizeValid_DISPATCH(struct KernelChannel *pKernelChannel, NvU32 userdAddrLo, NvU32 userdAddrHi) { return pKernelChannel->__kchannelIsUserdAddrSizeValid__(pKernelChannel, userdAddrLo, userdAddrHi); } @@ -1154,6 +1167,10 @@ static inline void kchannelPreDestruct_DISPATCH(struct KernelChannel *pResource) pResource->__kchannelPreDestruct__(pResource); } +static inline NV_STATUS kchannelIsDuplicate_DISPATCH(struct KernelChannel *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__kchannelIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline PEVENTNOTIFICATION *kchannelGetNotificationListPtr_DISPATCH(struct KernelChannel *pNotifier) { return pNotifier->__kchannelGetNotificationListPtr__(pNotifier); } @@ -1200,15 +1217,18 @@ static inline void kchannelSetRunlistId(struct KernelChannel *pKernelChannel, Nv pKernelChannel->runlistId = runlistId; } -static inline NvU32 kchannelGetEngineType(struct KernelChannel *pKernelChannel) { +static inline RM_ENGINE_TYPE kchannelGetEngineType(struct KernelChannel *pKernelChannel) { return pKernelChannel->engineType; } NV_STATUS kchannelConstruct_IMPL(struct KernelChannel *arg_pKernelChannel, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_kchannelConstruct(arg_pKernelChannel, arg_pCallContext, arg_pParams) kchannelConstruct_IMPL(arg_pKernelChannel, arg_pCallContext, arg_pParams) void kchannelDestruct_IMPL(struct KernelChannel *pResource); + #define __nvoc_kchannelDestruct(pResource) kchannelDestruct_IMPL(pResource) NV_STATUS kchannelRegisterChild_IMPL(struct KernelChannel *pKernelChannel, ChannelDescendant *pObject); + #ifdef __nvoc_kernel_channel_h_disabled static inline NV_STATUS kchannelRegisterChild(struct KernelChannel *pKernelChannel, ChannelDescendant *pObject) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); @@ -1219,6 +1239,7 @@ static inline NV_STATUS kchannelRegisterChild(struct KernelChannel *pKernelChann #endif //__nvoc_kernel_channel_h_disabled NV_STATUS kchannelDeregisterChild_IMPL(struct KernelChannel *pKernelChannel, ChannelDescendant *pObject); + #ifdef __nvoc_kernel_channel_h_disabled static inline NV_STATUS kchannelDeregisterChild(struct KernelChannel *pKernelChannel, ChannelDescendant *pObject) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); @@ -1229,6 +1250,7 @@ static inline NV_STATUS kchannelDeregisterChild(struct KernelChannel *pKernelCha #endif //__nvoc_kernel_channel_h_disabled void kchannelNotifyGeneric_IMPL(struct KernelChannel *pKernelChannel, NvU32 notifyIndex, void *pNotifyParams, NvU32 notifyParamsSize); + #ifdef __nvoc_kernel_channel_h_disabled static inline void kchannelNotifyGeneric(struct KernelChannel *pKernelChannel, NvU32 notifyIndex, void *pNotifyParams, NvU32 notifyParamsSize) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); @@ -1238,6 +1260,7 @@ static inline void kchannelNotifyGeneric(struct KernelChannel *pKernelChannel, N #endif //__nvoc_kernel_channel_h_disabled NvBool kchannelCheckIsKernel_IMPL(struct KernelChannel *pKernelChannel); + #ifdef __nvoc_kernel_channel_h_disabled static inline NvBool kchannelCheckIsKernel(struct KernelChannel *pKernelChannel) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); @@ -1248,6 +1271,7 @@ static inline NvBool kchannelCheckIsKernel(struct KernelChannel *pKernelChannel) #endif //__nvoc_kernel_channel_h_disabled NvBool kchannelCheckIsAdmin_IMPL(struct KernelChannel *pKernelChannel); + #ifdef __nvoc_kernel_channel_h_disabled static inline NvBool kchannelCheckIsAdmin(struct KernelChannel *pKernelChannel) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); @@ -1257,17 +1281,19 @@ static inline NvBool kchannelCheckIsAdmin(struct KernelChannel *pKernelChannel) #define kchannelCheckIsAdmin(pKernelChannel) kchannelCheckIsAdmin_IMPL(pKernelChannel) #endif //__nvoc_kernel_channel_h_disabled -NV_STATUS kchannelBindToRunlist_IMPL(struct KernelChannel *pKernelChannel, NvU32 localEngineType, ENGDESCRIPTOR engineDesc); +NV_STATUS kchannelBindToRunlist_IMPL(struct KernelChannel *pKernelChannel, RM_ENGINE_TYPE localRmEngineType, ENGDESCRIPTOR engineDesc); + #ifdef __nvoc_kernel_channel_h_disabled -static inline NV_STATUS kchannelBindToRunlist(struct KernelChannel *pKernelChannel, NvU32 localEngineType, ENGDESCRIPTOR engineDesc) { +static inline NV_STATUS kchannelBindToRunlist(struct KernelChannel *pKernelChannel, RM_ENGINE_TYPE localRmEngineType, ENGDESCRIPTOR engineDesc) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_channel_h_disabled -#define kchannelBindToRunlist(pKernelChannel, localEngineType, engineDesc) kchannelBindToRunlist_IMPL(pKernelChannel, localEngineType, engineDesc) +#define kchannelBindToRunlist(pKernelChannel, localRmEngineType, engineDesc) kchannelBindToRunlist_IMPL(pKernelChannel, localRmEngineType, engineDesc) #endif //__nvoc_kernel_channel_h_disabled NV_STATUS kchannelSetEngineContextMemDesc_IMPL(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, NvU32 engine, MEMORY_DESCRIPTOR *pMemDesc); + #ifdef __nvoc_kernel_channel_h_disabled static inline NV_STATUS kchannelSetEngineContextMemDesc(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, NvU32 engine, MEMORY_DESCRIPTOR *pMemDesc) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); @@ -1278,6 +1304,7 @@ static inline NV_STATUS kchannelSetEngineContextMemDesc(struct OBJGPU *pGpu, str #endif //__nvoc_kernel_channel_h_disabled NV_STATUS kchannelMapEngineCtxBuf_IMPL(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, NvU32 engine); + #ifdef __nvoc_kernel_channel_h_disabled static inline NV_STATUS kchannelMapEngineCtxBuf(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, NvU32 engine) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); @@ -1288,6 +1315,7 @@ static inline NV_STATUS kchannelMapEngineCtxBuf(struct OBJGPU *pGpu, struct Kern #endif //__nvoc_kernel_channel_h_disabled NV_STATUS kchannelUnmapEngineCtxBuf_IMPL(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, NvU32 engine); + #ifdef __nvoc_kernel_channel_h_disabled static inline NV_STATUS kchannelUnmapEngineCtxBuf(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, NvU32 engine) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); @@ -1298,6 +1326,7 @@ static inline NV_STATUS kchannelUnmapEngineCtxBuf(struct OBJGPU *pGpu, struct Ke #endif //__nvoc_kernel_channel_h_disabled NV_STATUS kchannelCheckBcStateCurrent_IMPL(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel); + #ifdef __nvoc_kernel_channel_h_disabled static inline NV_STATUS kchannelCheckBcStateCurrent(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); @@ -1308,6 +1337,7 @@ static inline NV_STATUS kchannelCheckBcStateCurrent(struct OBJGPU *pGpu, struct #endif //__nvoc_kernel_channel_h_disabled NV_STATUS kchannelUpdateWorkSubmitTokenNotifIndex_IMPL(struct OBJGPU *pGpu, struct KernelChannel *arg0, NvU32 index); + #ifdef __nvoc_kernel_channel_h_disabled static inline NV_STATUS kchannelUpdateWorkSubmitTokenNotifIndex(struct OBJGPU *pGpu, struct KernelChannel *arg0, NvU32 index) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); @@ -1318,6 +1348,7 @@ static inline NV_STATUS kchannelUpdateWorkSubmitTokenNotifIndex(struct OBJGPU *p #endif //__nvoc_kernel_channel_h_disabled NV_STATUS kchannelNotifyWorkSubmitToken_IMPL(struct OBJGPU *pGpu, struct KernelChannel *arg0, NvU32 token); + #ifdef __nvoc_kernel_channel_h_disabled static inline NV_STATUS kchannelNotifyWorkSubmitToken(struct OBJGPU *pGpu, struct KernelChannel *arg0, NvU32 token) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); @@ -1328,6 +1359,7 @@ static inline NV_STATUS kchannelNotifyWorkSubmitToken(struct OBJGPU *pGpu, struc #endif //__nvoc_kernel_channel_h_disabled NV_STATUS kchannelMapUserD_IMPL(struct OBJGPU *pGpu, struct KernelChannel *arg0, RS_PRIV_LEVEL arg1, NvU64 arg2, NvU32 arg3, NvP64 *arg4, NvP64 *arg5); + #ifdef __nvoc_kernel_channel_h_disabled static inline NV_STATUS kchannelMapUserD(struct OBJGPU *pGpu, struct KernelChannel *arg0, RS_PRIV_LEVEL arg1, NvU64 arg2, NvU32 arg3, NvP64 *arg4, NvP64 *arg5) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); @@ -1338,6 +1370,7 @@ static inline NV_STATUS kchannelMapUserD(struct OBJGPU *pGpu, struct KernelChann #endif //__nvoc_kernel_channel_h_disabled void kchannelUnmapUserD_IMPL(struct OBJGPU *pGpu, struct KernelChannel *arg0, RS_PRIV_LEVEL arg1, NvP64 *arg2, NvP64 *arg3); + #ifdef __nvoc_kernel_channel_h_disabled static inline void kchannelUnmapUserD(struct OBJGPU *pGpu, struct KernelChannel *arg0, RS_PRIV_LEVEL arg1, NvP64 *arg2, NvP64 *arg3) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); @@ -1347,10 +1380,13 @@ static inline void kchannelUnmapUserD(struct OBJGPU *pGpu, struct KernelChannel #endif //__nvoc_kernel_channel_h_disabled NV_STATUS kchannelGetFromDualHandle_IMPL(NvHandle arg0, NvHandle arg1, struct KernelChannel **arg2); + #define kchannelGetFromDualHandle(arg0, arg1, arg2) kchannelGetFromDualHandle_IMPL(arg0, arg1, arg2) NV_STATUS kchannelGetFromDualHandleRestricted_IMPL(NvHandle arg0, NvHandle arg1, struct KernelChannel **arg2); + #define kchannelGetFromDualHandleRestricted(arg0, arg1, arg2) kchannelGetFromDualHandleRestricted_IMPL(arg0, arg1, arg2) NvU32 kchannelGetGfid_IMPL(struct KernelChannel *pKernelChannel); + #ifdef __nvoc_kernel_channel_h_disabled static inline NvU32 kchannelGetGfid(struct KernelChannel *pKernelChannel) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); @@ -1394,7 +1430,7 @@ NV_STATUS kchannelGetNotifierInfo(struct OBJGPU *pGpu, // Utils to iterate over ChannelDescendants on one Channels void kchannelGetChildIterator(struct KernelChannel *pKernelChannel, NvU32 classID, - NvU32 engineID, + RM_ENGINE_TYPE engineID, KernelChannelChildIterator *pIter); ChannelDescendant *kchannelGetNextChild(KernelChannelChildIterator *pIter); // Simpler function to call if you just need one result diff --git a/src/nvidia/generated/g_kernel_ctxshare_nvoc.c b/src/nvidia/generated/g_kernel_ctxshare_nvoc.c index d05cb1164..25033deef 100644 --- a/src/nvidia/generated/g_kernel_ctxshare_nvoc.c +++ b/src/nvidia/generated/g_kernel_ctxshare_nvoc.c @@ -335,6 +335,10 @@ static NV_STATUS __nvoc_thunk_RsResource_kctxshareapiUnmapFrom(struct KernelCtxS return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_kctxshareapiIsDuplicate(struct KernelCtxShareApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_kctxshareapiControl_Epilogue(struct KernelCtxShareApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RmResource.offset), pCallContext, pParams); } @@ -494,6 +498,8 @@ static void __nvoc_init_funcTable_KernelCtxShareApi_1(KernelCtxShareApi *pThis) pThis->__kctxshareapiUnmapFrom__ = &__nvoc_thunk_RsResource_kctxshareapiUnmapFrom; + pThis->__kctxshareapiIsDuplicate__ = &__nvoc_thunk_RsResource_kctxshareapiIsDuplicate; + pThis->__kctxshareapiControl_Epilogue__ = &__nvoc_thunk_RmResource_kctxshareapiControl_Epilogue; pThis->__kctxshareapiControlLookup__ = &__nvoc_thunk_RsResource_kctxshareapiControlLookup; diff --git a/src/nvidia/generated/g_kernel_ctxshare_nvoc.h b/src/nvidia/generated/g_kernel_ctxshare_nvoc.h index 5d7bddb10..159f5b24e 100644 --- a/src/nvidia/generated/g_kernel_ctxshare_nvoc.h +++ b/src/nvidia/generated/g_kernel_ctxshare_nvoc.h @@ -128,6 +128,7 @@ static inline NV_STATUS kctxshareInit_56cd7a(struct KernelCtxShare *pKernelCtxSh return NV_OK; } + #ifdef __nvoc_kernel_ctxshare_h_disabled static inline NV_STATUS kctxshareInit(struct KernelCtxShare *pKernelCtxShare, struct KernelCtxShareApi *pKernelCtxShareApi, struct OBJGPU *pGpu, struct OBJVASPACE *pVAS, struct KernelChannelGroupApi *pKernelChannelGroupApi, NvU64 offset, PEMEMBLOCK pBlock) { NV_ASSERT_FAILED_PRECOMP("KernelCtxShare was disabled!"); @@ -143,6 +144,7 @@ static inline NV_STATUS kctxshareDestroy_56cd7a(struct KernelCtxShare *pKernelCt return NV_OK; } + #ifdef __nvoc_kernel_ctxshare_h_disabled static inline NV_STATUS kctxshareDestroy(struct KernelCtxShare *pKernelCtxShare, struct KernelCtxShareApi *pKernelCtxShareApi, struct OBJGPU *pGpu, struct KernelChannelGroupApi *pKernelChannelGroupApi, NvBool bRelease) { NV_ASSERT_FAILED_PRECOMP("KernelCtxShare was disabled!"); @@ -155,8 +157,10 @@ static inline NV_STATUS kctxshareDestroy(struct KernelCtxShare *pKernelCtxShare, #define kctxshareDestroy_HAL(pKernelCtxShare, pKernelCtxShareApi, pGpu, pKernelChannelGroupApi, bRelease) kctxshareDestroy(pKernelCtxShare, pKernelCtxShareApi, pGpu, pKernelChannelGroupApi, bRelease) NV_STATUS kctxshareConstruct_IMPL(struct KernelCtxShare *arg_pKernelCtxShare); + #define __nvoc_kctxshareConstruct(arg_pKernelCtxShare) kctxshareConstruct_IMPL(arg_pKernelCtxShare) NV_STATUS kctxshareInitCommon_IMPL(struct KernelCtxShare *pKernelCtxShare, struct KernelCtxShareApi *pKernelCtxShareApi, struct OBJGPU *pGpu, struct OBJVASPACE *pVAS, NvU32 Flags, NvU32 *pSubctxId, struct KernelChannelGroupApi *pKernelChannelGroupApi); + #ifdef __nvoc_kernel_ctxshare_h_disabled static inline NV_STATUS kctxshareInitCommon(struct KernelCtxShare *pKernelCtxShare, struct KernelCtxShareApi *pKernelCtxShareApi, struct OBJGPU *pGpu, struct OBJVASPACE *pVAS, NvU32 Flags, NvU32 *pSubctxId, struct KernelChannelGroupApi *pKernelChannelGroupApi) { NV_ASSERT_FAILED_PRECOMP("KernelCtxShare was disabled!"); @@ -167,6 +171,7 @@ static inline NV_STATUS kctxshareInitCommon(struct KernelCtxShare *pKernelCtxSha #endif //__nvoc_kernel_ctxshare_h_disabled NV_STATUS kctxshareDestroyCommon_IMPL(struct KernelCtxShare *pKernelCtxShare, struct KernelCtxShareApi *pKernelCtxShareApi, struct OBJGPU *pGpu, struct KernelChannelGroupApi *pKernelChannelGroupApi); + #ifdef __nvoc_kernel_ctxshare_h_disabled static inline NV_STATUS kctxshareDestroyCommon(struct KernelCtxShare *pKernelCtxShare, struct KernelCtxShareApi *pKernelCtxShareApi, struct OBJGPU *pGpu, struct KernelChannelGroupApi *pKernelChannelGroupApi) { NV_ASSERT_FAILED_PRECOMP("KernelCtxShare was disabled!"); @@ -177,6 +182,7 @@ static inline NV_STATUS kctxshareDestroyCommon(struct KernelCtxShare *pKernelCtx #endif //__nvoc_kernel_ctxshare_h_disabled void kctxshareDestruct_IMPL(struct KernelCtxShare *pKernelCtxShare); + #define __nvoc_kctxshareDestruct(pKernelCtxShare) kctxshareDestruct_IMPL(pKernelCtxShare) #undef PRIVATE_FIELD @@ -216,11 +222,13 @@ struct KernelCtxShareApi { NV_STATUS (*__kctxshareapiInternalControlForward__)(struct KernelCtxShareApi *, NvU32, void *, NvU32); void (*__kctxshareapiPreDestruct__)(struct KernelCtxShareApi *); NV_STATUS (*__kctxshareapiUnmapFrom__)(struct KernelCtxShareApi *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__kctxshareapiIsDuplicate__)(struct KernelCtxShareApi *, NvHandle, NvBool *); void (*__kctxshareapiControl_Epilogue__)(struct KernelCtxShareApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kctxshareapiControlLookup__)(struct KernelCtxShareApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__kctxshareapiMap__)(struct KernelCtxShareApi *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__kctxshareapiAccessCallback__)(struct KernelCtxShareApi *, struct RsClient *, void *, RsAccessRight); struct KernelCtxShare *pShareData; + NvHandle hVASpace; }; #ifndef __NVOC_CLASS_KernelCtxShareApi_TYPEDEF__ @@ -272,6 +280,7 @@ NV_STATUS __nvoc_objCreate_KernelCtxShareApi(KernelCtxShareApi**, Dynamic*, NvU3 #define kctxshareapiInternalControlForward(pGpuResource, command, pParams, size) kctxshareapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define kctxshareapiPreDestruct(pResource) kctxshareapiPreDestruct_DISPATCH(pResource) #define kctxshareapiUnmapFrom(pResource, pParams) kctxshareapiUnmapFrom_DISPATCH(pResource, pParams) +#define kctxshareapiIsDuplicate(pResource, hMemory, pDuplicate) kctxshareapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define kctxshareapiControl_Epilogue(pResource, pCallContext, pParams) kctxshareapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define kctxshareapiControlLookup(pResource, pParams, ppEntry) kctxshareapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define kctxshareapiMap(pGpuResource, pCallContext, pParams, pCpuMapping) kctxshareapiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -368,6 +377,10 @@ static inline NV_STATUS kctxshareapiUnmapFrom_DISPATCH(struct KernelCtxShareApi return pResource->__kctxshareapiUnmapFrom__(pResource, pParams); } +static inline NV_STATUS kctxshareapiIsDuplicate_DISPATCH(struct KernelCtxShareApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__kctxshareapiIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void kctxshareapiControl_Epilogue_DISPATCH(struct KernelCtxShareApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__kctxshareapiControl_Epilogue__(pResource, pCallContext, pParams); } @@ -385,8 +398,10 @@ static inline NvBool kctxshareapiAccessCallback_DISPATCH(struct KernelCtxShareAp } NV_STATUS kctxshareapiConstruct_IMPL(struct KernelCtxShareApi *arg_pKernelCtxShareApi, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_kctxshareapiConstruct(arg_pKernelCtxShareApi, arg_pCallContext, arg_pParams) kctxshareapiConstruct_IMPL(arg_pKernelCtxShareApi, arg_pCallContext, arg_pParams) NV_STATUS kctxshareapiCopyConstruct_IMPL(struct KernelCtxShareApi *pKernelCtxShareApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); + #ifdef __nvoc_kernel_ctxshare_h_disabled static inline NV_STATUS kctxshareapiCopyConstruct(struct KernelCtxShareApi *pKernelCtxShareApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { NV_ASSERT_FAILED_PRECOMP("KernelCtxShareApi was disabled!"); @@ -397,6 +412,7 @@ static inline NV_STATUS kctxshareapiCopyConstruct(struct KernelCtxShareApi *pKer #endif //__nvoc_kernel_ctxshare_h_disabled void kctxshareapiDestruct_IMPL(struct KernelCtxShareApi *pKernelCtxShareApi); + #define __nvoc_kctxshareapiDestruct(pKernelCtxShareApi) kctxshareapiDestruct_IMPL(pKernelCtxShareApi) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_kernel_falcon_nvoc.c b/src/nvidia/generated/g_kernel_falcon_nvoc.c index e50affe99..203f22c71 100644 --- a/src/nvidia/generated/g_kernel_falcon_nvoc.c +++ b/src/nvidia/generated/g_kernel_falcon_nvoc.c @@ -104,22 +104,16 @@ static void __nvoc_init_funcTable_KernelFalcon_1(KernelFalcon *pThis, RmHalspecO { pThis->__kflcnIsRiscvActive__ = &kflcnIsRiscvActive_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kflcnIsRiscvActive__ = &kflcnIsRiscvActive_GA10X; } - else if (0) - { - } - } - else if (0) - { } // Hal function -- kflcnRiscvProgramBcr if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kflcnRiscvProgramBcr__ = &kflcnRiscvProgramBcr_GA102; } @@ -128,14 +122,11 @@ static void __nvoc_init_funcTable_KernelFalcon_1(KernelFalcon *pThis, RmHalspecO pThis->__kflcnRiscvProgramBcr__ = &kflcnRiscvProgramBcr_f2d351; } } - else if (0) - { - } // Hal function -- kflcnSwitchToFalcon if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kflcnSwitchToFalcon__ = &kflcnSwitchToFalcon_GA10X; } @@ -144,9 +135,6 @@ static void __nvoc_init_funcTable_KernelFalcon_1(KernelFalcon *pThis, RmHalspecO pThis->__kflcnSwitchToFalcon__ = &kflcnSwitchToFalcon_b3696a; } } - else if (0) - { - } pThis->__kflcnResetHw__ = NULL; @@ -163,14 +151,11 @@ static void __nvoc_init_funcTable_KernelFalcon_1(KernelFalcon *pThis, RmHalspecO pThis->__kflcnPreResetWait__ = &kflcnPreResetWait_56cd7a; } } - else if (0) - { - } // Hal function -- kflcnWaitForResetToFinish if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kflcnWaitForResetToFinish__ = &kflcnWaitForResetToFinish_GA102; } @@ -178,12 +163,6 @@ static void __nvoc_init_funcTable_KernelFalcon_1(KernelFalcon *pThis, RmHalspecO { pThis->__kflcnWaitForResetToFinish__ = &kflcnWaitForResetToFinish_TU102; } - else if (0) - { - } - } - else if (0) - { } pThis->__kflcnIsEngineInReset__ = NULL; @@ -195,22 +174,16 @@ static void __nvoc_init_funcTable_KernelFalcon_1(KernelFalcon *pThis, RmHalspecO { pThis->__kflcnReadIntrStatus__ = &kflcnReadIntrStatus_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kflcnReadIntrStatus__ = &kflcnReadIntrStatus_GA102; } - else if (0) - { - } - } - else if (0) - { } // Hal function -- kflcnIntrRetrigger if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kflcnIntrRetrigger__ = &kflcnIntrRetrigger_GA100; } @@ -219,9 +192,6 @@ static void __nvoc_init_funcTable_KernelFalcon_1(KernelFalcon *pThis, RmHalspecO pThis->__kflcnIntrRetrigger__ = &kflcnIntrRetrigger_b3696a; } } - else if (0) - { - } // Hal function -- kflcnMaskImemAddr if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ @@ -230,16 +200,10 @@ static void __nvoc_init_funcTable_KernelFalcon_1(KernelFalcon *pThis, RmHalspecO { pThis->__kflcnMaskImemAddr__ = &kflcnMaskImemAddr_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kflcnMaskImemAddr__ = &kflcnMaskImemAddr_GA100; } - else if (0) - { - } - } - else if (0) - { } // Hal function -- kflcnMaskDmemAddr @@ -249,16 +213,10 @@ static void __nvoc_init_funcTable_KernelFalcon_1(KernelFalcon *pThis, RmHalspecO { pThis->__kflcnMaskDmemAddr__ = &kflcnMaskDmemAddr_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kflcnMaskDmemAddr__ = &kflcnMaskDmemAddr_GA100; } - else if (0) - { - } - } - else if (0) - { } } @@ -347,7 +305,7 @@ static NvBool __nvoc_thunk_GenericKernelFalcon_kflcnIsEngineInReset(struct OBJGP return gkflcnIsEngineInReset(pGpu, (struct GenericKernelFalcon *)(((unsigned char *)pGenKernFlcn) - __nvoc_rtti_GenericKernelFalcon_KernelFalcon.offset)); } -static void __nvoc_thunk_GenericKernelFalcon_intrservRegisterIntrService(struct OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[155]) { +static void __nvoc_thunk_GenericKernelFalcon_intrservRegisterIntrService(struct OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[163]) { gkflcnRegisterIntrService(arg0, (struct GenericKernelFalcon *)(((unsigned char *)arg1) - __nvoc_rtti_GenericKernelFalcon_IntrService.offset), arg2); } @@ -384,15 +342,15 @@ void __nvoc_init_dataField_GenericKernelFalcon(GenericKernelFalcon *pThis) { } NV_STATUS __nvoc_ctor_KernelFalcon(KernelFalcon* , RmHalspecOwner* ); -NV_STATUS __nvoc_ctor_IntrService(IntrService* , RmHalspecOwner* ); -NV_STATUS __nvoc_ctor_Object(Object* , RmHalspecOwner* ); +NV_STATUS __nvoc_ctor_IntrService(IntrService* ); +NV_STATUS __nvoc_ctor_Object(Object* ); NV_STATUS __nvoc_ctor_GenericKernelFalcon(GenericKernelFalcon *pThis, RmHalspecOwner *pRmhalspecowner, struct OBJGPU * arg_pGpu, KernelFalconEngineConfig * arg_pFalconConfig) { NV_STATUS status = NV_OK; status = __nvoc_ctor_KernelFalcon(&pThis->__nvoc_base_KernelFalcon, pRmhalspecowner); if (status != NV_OK) goto __nvoc_ctor_GenericKernelFalcon_fail_KernelFalcon; - status = __nvoc_ctor_IntrService(&pThis->__nvoc_base_IntrService, pRmhalspecowner); + status = __nvoc_ctor_IntrService(&pThis->__nvoc_base_IntrService); if (status != NV_OK) goto __nvoc_ctor_GenericKernelFalcon_fail_IntrService; - status = __nvoc_ctor_Object(&pThis->__nvoc_base_Object, pRmhalspecowner); + status = __nvoc_ctor_Object(&pThis->__nvoc_base_Object); if (status != NV_OK) goto __nvoc_ctor_GenericKernelFalcon_fail_Object; __nvoc_init_dataField_GenericKernelFalcon(pThis); @@ -441,16 +399,16 @@ void __nvoc_init_funcTable_GenericKernelFalcon(GenericKernelFalcon *pThis) { } void __nvoc_init_KernelFalcon(KernelFalcon*, RmHalspecOwner* ); -void __nvoc_init_IntrService(IntrService*, RmHalspecOwner* ); -void __nvoc_init_Object(Object*, RmHalspecOwner* ); +void __nvoc_init_IntrService(IntrService*); +void __nvoc_init_Object(Object*); void __nvoc_init_GenericKernelFalcon(GenericKernelFalcon *pThis, RmHalspecOwner *pRmhalspecowner) { pThis->__nvoc_pbase_GenericKernelFalcon = pThis; pThis->__nvoc_pbase_KernelFalcon = &pThis->__nvoc_base_KernelFalcon; pThis->__nvoc_pbase_IntrService = &pThis->__nvoc_base_IntrService; pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Object; __nvoc_init_KernelFalcon(&pThis->__nvoc_base_KernelFalcon, pRmhalspecowner); - __nvoc_init_IntrService(&pThis->__nvoc_base_IntrService, pRmhalspecowner); - __nvoc_init_Object(&pThis->__nvoc_base_Object, pRmhalspecowner); + __nvoc_init_IntrService(&pThis->__nvoc_base_IntrService); + __nvoc_init_Object(&pThis->__nvoc_base_Object); __nvoc_init_funcTable_GenericKernelFalcon(pThis); } diff --git a/src/nvidia/generated/g_kernel_falcon_nvoc.h b/src/nvidia/generated/g_kernel_falcon_nvoc.h index ce971af9b..00ffe25e1 100644 --- a/src/nvidia/generated/g_kernel_falcon_nvoc.h +++ b/src/nvidia/generated/g_kernel_falcon_nvoc.h @@ -153,6 +153,7 @@ NV_STATUS __nvoc_objCreate_KernelFalcon(KernelFalcon**, Dynamic*, NvU32); #define kflcnMaskDmemAddr_HAL(pGpu, pKernelFlcn, addr) kflcnMaskDmemAddr_DISPATCH(pGpu, pKernelFlcn, addr) NvU32 kflcnRegRead_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset); + #ifdef __nvoc_kernel_falcon_h_disabled static inline NvU32 kflcnRegRead(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset) { NV_ASSERT_FAILED_PRECOMP("KernelFalcon was disabled!"); @@ -166,6 +167,7 @@ static inline NvU32 kflcnRegRead(struct OBJGPU *pGpu, struct KernelFalcon *pKern void kflcnRegWrite_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset, NvU32 data); + #ifdef __nvoc_kernel_falcon_h_disabled static inline void kflcnRegWrite(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset, NvU32 data) { NV_ASSERT_FAILED_PRECOMP("KernelFalcon was disabled!"); @@ -178,6 +180,7 @@ static inline void kflcnRegWrite(struct OBJGPU *pGpu, struct KernelFalcon *pKern NvU32 kflcnRiscvRegRead_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset); + #ifdef __nvoc_kernel_falcon_h_disabled static inline NvU32 kflcnRiscvRegRead(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset) { NV_ASSERT_FAILED_PRECOMP("KernelFalcon was disabled!"); @@ -191,6 +194,7 @@ static inline NvU32 kflcnRiscvRegRead(struct OBJGPU *pGpu, struct KernelFalcon * void kflcnRiscvRegWrite_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset, NvU32 data); + #ifdef __nvoc_kernel_falcon_h_disabled static inline void kflcnRiscvRegWrite(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset, NvU32 data) { NV_ASSERT_FAILED_PRECOMP("KernelFalcon was disabled!"); @@ -203,6 +207,7 @@ static inline void kflcnRiscvRegWrite(struct OBJGPU *pGpu, struct KernelFalcon * NvBool kflcnIsRiscvCpuEnabled_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn); + #ifdef __nvoc_kernel_falcon_h_disabled static inline NvBool kflcnIsRiscvCpuEnabled(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { NV_ASSERT_FAILED_PRECOMP("KernelFalcon was disabled!"); @@ -216,6 +221,7 @@ static inline NvBool kflcnIsRiscvCpuEnabled(struct OBJGPU *pGpu, struct KernelFa void kflcnReset_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn); + #ifdef __nvoc_kernel_falcon_h_disabled static inline void kflcnReset(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { NV_ASSERT_FAILED_PRECOMP("KernelFalcon was disabled!"); @@ -228,6 +234,7 @@ static inline void kflcnReset(struct OBJGPU *pGpu, struct KernelFalcon *pKernelF void kflcnSecureReset_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn); + #ifdef __nvoc_kernel_falcon_h_disabled static inline void kflcnSecureReset(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { NV_ASSERT_FAILED_PRECOMP("KernelFalcon was disabled!"); @@ -240,6 +247,7 @@ static inline void kflcnSecureReset(struct OBJGPU *pGpu, struct KernelFalcon *pK void kflcnEnable_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvBool bEnable); + #ifdef __nvoc_kernel_falcon_h_disabled static inline void kflcnEnable(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvBool bEnable) { NV_ASSERT_FAILED_PRECOMP("KernelFalcon was disabled!"); @@ -252,6 +260,7 @@ static inline void kflcnEnable(struct OBJGPU *pGpu, struct KernelFalcon *pKernel void kflcnStartCpu_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn); + #ifdef __nvoc_kernel_falcon_h_disabled static inline void kflcnStartCpu(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { NV_ASSERT_FAILED_PRECOMP("KernelFalcon was disabled!"); @@ -264,6 +273,7 @@ static inline void kflcnStartCpu(struct OBJGPU *pGpu, struct KernelFalcon *pKern void kflcnDisableCtxReq_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn); + #ifdef __nvoc_kernel_falcon_h_disabled static inline void kflcnDisableCtxReq(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { NV_ASSERT_FAILED_PRECOMP("KernelFalcon was disabled!"); @@ -276,6 +286,7 @@ static inline void kflcnDisableCtxReq(struct OBJGPU *pGpu, struct KernelFalcon * NV_STATUS kflcnWaitForHalt_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 timeoutUs, NvU32 flags); + #ifdef __nvoc_kernel_falcon_h_disabled static inline NV_STATUS kflcnWaitForHalt(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 timeoutUs, NvU32 flags) { NV_ASSERT_FAILED_PRECOMP("KernelFalcon was disabled!"); @@ -291,10 +302,6 @@ NvBool kflcnIsRiscvActive_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKerne NvBool kflcnIsRiscvActive_GA10X(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn); -static inline NvBool kflcnIsRiscvActive_108313(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { - NV_ASSERT_OR_RETURN_PRECOMP(0, ((NvBool)(0 != 0))); -} - static inline NvBool kflcnIsRiscvActive_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { return pKernelFlcn->__kflcnIsRiscvActive__(pGpu, pKernelFlcn); } @@ -315,10 +322,6 @@ static inline void kflcnSwitchToFalcon_b3696a(struct OBJGPU *pGpu, struct Kernel return; } -static inline void kflcnSwitchToFalcon_f2d351(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { - NV_ASSERT_PRECOMP(0); -} - static inline void kflcnSwitchToFalcon_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { pKernelFlcn->__kflcnSwitchToFalcon__(pGpu, pKernelFlcn); } @@ -333,10 +336,6 @@ static inline NV_STATUS kflcnPreResetWait_56cd7a(struct OBJGPU *pGpu, struct Ker return NV_OK; } -static inline NV_STATUS kflcnPreResetWait_5baef9(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { - NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); -} - static inline NV_STATUS kflcnPreResetWait_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { return pKernelFlcn->__kflcnPreResetWait__(pGpu, pKernelFlcn); } @@ -345,14 +344,6 @@ NV_STATUS kflcnWaitForResetToFinish_GA102(struct OBJGPU *pGpu, struct KernelFalc NV_STATUS kflcnWaitForResetToFinish_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn); -static inline NV_STATUS kflcnWaitForResetToFinish_56cd7a(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { - return NV_OK; -} - -static inline NV_STATUS kflcnWaitForResetToFinish_5baef9(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { - NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); -} - static inline NV_STATUS kflcnWaitForResetToFinish_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { return pKernelFlcn->__kflcnWaitForResetToFinish__(pGpu, pKernelFlcn); } @@ -365,10 +356,6 @@ NvU32 kflcnReadIntrStatus_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKerne NvU32 kflcnReadIntrStatus_GA102(struct OBJGPU *pGpu, struct KernelFalcon *pKerneFlcn); -static inline NvU32 kflcnReadIntrStatus_474d46(struct OBJGPU *pGpu, struct KernelFalcon *pKerneFlcn) { - NV_ASSERT_OR_RETURN_PRECOMP(0, 0); -} - static inline NvU32 kflcnReadIntrStatus_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKerneFlcn) { return pKerneFlcn->__kflcnReadIntrStatus__(pGpu, pKerneFlcn); } @@ -379,10 +366,6 @@ static inline void kflcnIntrRetrigger_b3696a(struct OBJGPU *pGpu, struct KernelF return; } -static inline void kflcnIntrRetrigger_f2d351(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { - NV_ASSERT_PRECOMP(0); -} - static inline void kflcnIntrRetrigger_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { pKernelFlcn->__kflcnIntrRetrigger__(pGpu, pKernelFlcn); } @@ -391,10 +374,6 @@ NvU32 kflcnMaskImemAddr_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelF NvU32 kflcnMaskImemAddr_GA100(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 addr); -static inline NvU32 kflcnMaskImemAddr_474d46(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 addr) { - NV_ASSERT_OR_RETURN_PRECOMP(0, 0); -} - static inline NvU32 kflcnMaskImemAddr_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 addr) { return pKernelFlcn->__kflcnMaskImemAddr__(pGpu, pKernelFlcn, addr); } @@ -403,15 +382,12 @@ NvU32 kflcnMaskDmemAddr_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelF NvU32 kflcnMaskDmemAddr_GA100(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 addr); -static inline NvU32 kflcnMaskDmemAddr_474d46(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 addr) { - NV_ASSERT_OR_RETURN_PRECOMP(0, 0); -} - static inline NvU32 kflcnMaskDmemAddr_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 addr) { return pKernelFlcn->__kflcnMaskDmemAddr__(pGpu, pKernelFlcn, addr); } void kflcnConfigureEngine_IMPL(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFalcon, KernelFalconEngineConfig *pFalconConfig); + #ifdef __nvoc_kernel_falcon_h_disabled static inline void kflcnConfigureEngine(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFalcon, KernelFalconEngineConfig *pFalconConfig) { NV_ASSERT_FAILED_PRECOMP("KernelFalcon was disabled!"); @@ -421,6 +397,7 @@ static inline void kflcnConfigureEngine(struct OBJGPU *pGpu, struct KernelFalcon #endif //__nvoc_kernel_falcon_h_disabled NV_STATUS kflcnAllocContext_IMPL(struct OBJGPU *arg0, struct KernelFalcon *arg1, struct KernelChannel *arg2, NvU32 arg3); + #ifdef __nvoc_kernel_falcon_h_disabled static inline NV_STATUS kflcnAllocContext(struct OBJGPU *arg0, struct KernelFalcon *arg1, struct KernelChannel *arg2, NvU32 arg3) { NV_ASSERT_FAILED_PRECOMP("KernelFalcon was disabled!"); @@ -431,6 +408,7 @@ static inline NV_STATUS kflcnAllocContext(struct OBJGPU *arg0, struct KernelFalc #endif //__nvoc_kernel_falcon_h_disabled NV_STATUS kflcnFreeContext_IMPL(struct OBJGPU *arg0, struct KernelFalcon *arg1, struct KernelChannel *arg2, NvU32 arg3); + #ifdef __nvoc_kernel_falcon_h_disabled static inline NV_STATUS kflcnFreeContext(struct OBJGPU *arg0, struct KernelFalcon *arg1, struct KernelChannel *arg2, NvU32 arg3) { NV_ASSERT_FAILED_PRECOMP("KernelFalcon was disabled!"); @@ -441,6 +419,7 @@ static inline NV_STATUS kflcnFreeContext(struct OBJGPU *arg0, struct KernelFalco #endif //__nvoc_kernel_falcon_h_disabled struct KernelFalcon *kflcnGetKernelFalconForEngine_IMPL(struct OBJGPU *pGpu, ENGDESCRIPTOR physEngDesc); + #define kflcnGetKernelFalconForEngine(pGpu, physEngDesc) kflcnGetKernelFalconForEngine_IMPL(pGpu, physEngDesc) #undef PRIVATE_FIELD @@ -514,9 +493,9 @@ static inline NvBool gkflcnIsEngineInReset_DISPATCH(struct OBJGPU *pGpu, struct return pGenKernFlcn->__gkflcnIsEngineInReset__(pGpu, pGenKernFlcn); } -void gkflcnRegisterIntrService_IMPL(struct OBJGPU *arg0, struct GenericKernelFalcon *arg1, IntrServiceRecord arg2[155]); +void gkflcnRegisterIntrService_IMPL(struct OBJGPU *arg0, struct GenericKernelFalcon *arg1, IntrServiceRecord arg2[163]); -static inline void gkflcnRegisterIntrService_DISPATCH(struct OBJGPU *arg0, struct GenericKernelFalcon *arg1, IntrServiceRecord arg2[155]) { +static inline void gkflcnRegisterIntrService_DISPATCH(struct OBJGPU *arg0, struct GenericKernelFalcon *arg1, IntrServiceRecord arg2[163]) { arg1->__gkflcnRegisterIntrService__(arg0, arg1, arg2); } @@ -535,6 +514,7 @@ static inline NvU32 gkflcnServiceInterrupt_DISPATCH(struct OBJGPU *pGpu, struct } NV_STATUS gkflcnConstruct_IMPL(struct GenericKernelFalcon *arg_pGenKernFlcn, struct OBJGPU *arg_pGpu, KernelFalconEngineConfig *arg_pFalconConfig); + #define __nvoc_gkflcnConstruct(arg_pGenKernFlcn, arg_pGpu, arg_pFalconConfig) gkflcnConstruct_IMPL(arg_pGenKernFlcn, arg_pGpu, arg_pFalconConfig) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_kernel_fifo_nvoc.c b/src/nvidia/generated/g_kernel_fifo_nvoc.c index b3df44baf..78e39bd7a 100644 --- a/src/nvidia/generated/g_kernel_fifo_nvoc.c +++ b/src/nvidia/generated/g_kernel_fifo_nvoc.c @@ -172,21 +172,16 @@ void __nvoc_init_dataField_KernelFifo(KernelFifo *pThis, RmHalspecOwner *pRmhals PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // Hal field -- bUseChidHeap - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->bUseChidHeap = ((NvBool)(0 == 0)); } - // default - else - { - pThis->bUseChidHeap = ((NvBool)(0 != 0)); - } // Hal field -- bUsePerRunlistChram pThis->bUsePerRunlistChram = ((NvBool)(0 != 0)); // Hal field -- bIsPerRunlistChramSupportedInHw - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->bIsPerRunlistChramSupportedInHw = ((NvBool)(0 == 0)); } @@ -197,7 +192,7 @@ void __nvoc_init_dataField_KernelFifo(KernelFifo *pThis, RmHalspecOwner *pRmhals } // Hal field -- bHostEngineExpansion - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->bHostEngineExpansion = ((NvBool)(0 == 0)); } @@ -208,58 +203,34 @@ void __nvoc_init_dataField_KernelFifo(KernelFifo *pThis, RmHalspecOwner *pRmhals } // Hal field -- bHostHasLbOverflow - if (0) - { - } // default - else { pThis->bHostHasLbOverflow = ((NvBool)(0 != 0)); } // Hal field -- bSubcontextSupported - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->bSubcontextSupported = ((NvBool)(0 == 0)); } - // default - else - { - pThis->bSubcontextSupported = ((NvBool)(0 != 0)); - } // Hal field -- bMixedInstmemApertureDefAllowed - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->bMixedInstmemApertureDefAllowed = ((NvBool)(0 == 0)); } - // default - else - { - pThis->bMixedInstmemApertureDefAllowed = ((NvBool)(0 != 0)); - } // Hal field -- bIsZombieSubctxWarEnabled - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->bIsZombieSubctxWarEnabled = ((NvBool)(0 == 0)); } - // default - else - { - pThis->bIsZombieSubctxWarEnabled = ((NvBool)(0 != 0)); - } // Hal field -- bIsSchedSupported - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->bIsSchedSupported = ((NvBool)(0 == 0)); } - // default - else - { - pThis->bIsSchedSupported = ((NvBool)(0 != 0)); - } } NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); @@ -295,28 +266,19 @@ static void __nvoc_init_funcTable_KernelFifo_1(KernelFifo *pThis, RmHalspecOwner pThis->__kfifoStateDestroy__ = &kfifoStateDestroy_IMPL; // Hal function -- kfifoStatePostLoad - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kfifoStatePostLoad__ = &kfifoStatePostLoad_GM107; } - else if (0) - { - } - else if (0) - { - } // Hal function -- kfifoStatePreUnload - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kfifoStatePreUnload__ = &kfifoStatePreUnload_GM107; } - else if (0) - { - } // Hal function -- kfifoCheckChannelAllocAddrSpaces - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kfifoCheckChannelAllocAddrSpaces__ = &kfifoCheckChannelAllocAddrSpaces_GH100; } @@ -327,21 +289,21 @@ static void __nvoc_init_funcTable_KernelFifo_1(KernelFifo *pThis, RmHalspecOwner } // Hal function -- kfifoGetMmioUsermodeOffset - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kfifoGetMmioUsermodeOffset__ = &kfifoGetMmioUsermodeOffset_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kfifoGetMmioUsermodeOffset__ = &kfifoGetMmioUsermodeOffset_474d46; } // Hal function -- kfifoGetMmioUsermodeSize - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kfifoGetMmioUsermodeSize__ = &kfifoGetMmioUsermodeSize_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kfifoGetMmioUsermodeSize__ = &kfifoGetMmioUsermodeSize_474d46; } @@ -351,19 +313,13 @@ static void __nvoc_init_funcTable_KernelFifo_1(KernelFifo *pThis, RmHalspecOwner { pThis->__kfifoChannelGroupGetLocalMaxSubcontext__ = &kfifoChannelGroupGetLocalMaxSubcontext_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kfifoChannelGroupGetLocalMaxSubcontext__ = &kfifoChannelGroupGetLocalMaxSubcontext_GA100; } - else if (0) - { - } - else if (0) - { - } // Hal function -- kfifoGetCtxBufferMapFlags - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kfifoGetCtxBufferMapFlags__ = &kfifoGetCtxBufferMapFlags_GH100; } @@ -374,71 +330,34 @@ static void __nvoc_init_funcTable_KernelFifo_1(KernelFifo *pThis, RmHalspecOwner } // Hal function -- kfifoEngineInfoXlate - if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__kfifoEngineInfoXlate__ = &kfifoEngineInfoXlate_GV100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kfifoEngineInfoXlate__ = &kfifoEngineInfoXlate_GA100; } - else if (0) - { - } - else if (0) - { - } // Hal function -- kfifoGenerateWorkSubmitToken - if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__kfifoGenerateWorkSubmitToken__ = &kfifoGenerateWorkSubmitToken_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kfifoGenerateWorkSubmitToken__ = &kfifoGenerateWorkSubmitToken_GA100; } - else if (0) - { - } // Hal function -- kfifoUpdateUsermodeDoorbell - if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__kfifoUpdateUsermodeDoorbell__ = &kfifoUpdateUsermodeDoorbell_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kfifoUpdateUsermodeDoorbell__ = &kfifoUpdateUsermodeDoorbell_GA100; } - else if (0) - { - } - - // Hal function -- kfifoGetMaxNumRunlists - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ - { - pThis->__kfifoGetMaxNumRunlists__ = &kfifoGetMaxNumRunlists_GM107; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kfifoGetMaxNumRunlists__ = &kfifoGetMaxNumRunlists_GH100; - } - else if (0) - { - } - else if (0) - { - } // Hal function -- kfifoRunlistGetBaseShift if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ @@ -449,42 +368,30 @@ static void __nvoc_init_funcTable_KernelFifo_1(KernelFifo *pThis, RmHalspecOwner { pThis->__kfifoRunlistGetBaseShift__ = &kfifoRunlistGetBaseShift_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kfifoRunlistGetBaseShift__ = &kfifoRunlistGetBaseShift_GA102; } - else if (0) - { - } // Hal function -- kfifoGetMaxCeChannelGroups if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__kfifoGetMaxCeChannelGroups__ = &kfifoGetMaxCeChannelGroups_GV100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kfifoGetMaxCeChannelGroups__ = &kfifoGetMaxCeChannelGroups_GA100; } - else if (0) - { - } // Hal function -- kfifoSetupUserD if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__kfifoSetupUserD__ = &kfifoSetupUserD_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kfifoSetupUserD__ = &kfifoSetupUserD_GA100; } - else if (0) - { - } - else if (0) - { - } pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelFifo_engstateConstructEngine; diff --git a/src/nvidia/generated/g_kernel_fifo_nvoc.h b/src/nvidia/generated/g_kernel_fifo_nvoc.h index 08dbfa10e..3b27b0a8a 100644 --- a/src/nvidia/generated/g_kernel_fifo_nvoc.h +++ b/src/nvidia/generated/g_kernel_fifo_nvoc.h @@ -40,11 +40,10 @@ extern "C" { * Defines and structures used for the KernelFifo Object. * \***************************************************************************/ -#include "class/cl2080.h" // NV2080_ENGINE_TYPE_LAST - #include "kernel/gpu/eng_state.h" #include "kernel/gpu/gpu_halspec.h" #include "kernel/gpu/fifo/channel_descendant.h" +#include "kernel/gpu/gpu_engine_type.h" #include "containers/eheap_old.h" #include "containers/map.h" @@ -278,8 +277,8 @@ typedef enum ENGINE_INFO_TYPE_ENG_DESC = 0, // HW engine ID ENGINE_INFO_TYPE_FIFO_TAG, - // NV2080_ENGINE_TYPE_* - ENGINE_INFO_TYPE_NV2080, + // RM_ENGINE_TYPE_* + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, // runlist id (meaning varies by GPU) ENGINE_INFO_TYPE_RUNLIST, // NV_PFIFO_INTR_MMU_FAULT_ENG_ID_* @@ -327,6 +326,12 @@ typedef struct _def_fifo_engine_list char engineName[FIFO_ENGINE_NAME_MAX_SIZE]; } FIFO_ENGINE_LIST, *PFIFO_ENGINE_LIST; +typedef struct +{ + NvU32 nv2080EngineType; + NvU32 mcIdx; +} FIFO_GUEST_ENGINE_TABLE; + typedef struct _def_engine_info { NvU32 maxNumPbdmas; // max number of PBDMAs @@ -421,7 +426,6 @@ struct KernelFifo { NV_STATUS (*__kfifoEngineInfoXlate__)(struct OBJGPU *, struct KernelFifo *, ENGINE_INFO_TYPE, NvU32, ENGINE_INFO_TYPE, NvU32 *); NV_STATUS (*__kfifoGenerateWorkSubmitToken__)(struct OBJGPU *, struct KernelFifo *, struct KernelChannel *, NvU32 *, NvBool); NV_STATUS (*__kfifoUpdateUsermodeDoorbell__)(struct OBJGPU *, struct KernelFifo *, NvU32, NvU32); - NvU32 (*__kfifoGetMaxNumRunlists__)(struct OBJGPU *, struct KernelFifo *); NvU32 (*__kfifoRunlistGetBaseShift__)(struct KernelFifo *); NvU32 (*__kfifoGetMaxCeChannelGroups__)(struct OBJGPU *, struct KernelFifo *); void (*__kfifoSetupUserD__)(struct KernelFifo *, NvU8 *); @@ -468,7 +472,7 @@ struct KernelFifo { NvU32 InstAttr; const NV_ADDRESS_SPACE *pInstAllocList; MEMORY_DESCRIPTOR *pDummyPageMemDesc; - CTX_BUF_POOL_INFO *pRunlistBufPool[52]; + CTX_BUF_POOL_INFO *pRunlistBufPool[62]; MEMORY_DESCRIPTOR ***pppRunlistBufMemDesc; }; @@ -525,8 +529,6 @@ NV_STATUS __nvoc_objCreate_KernelFifo(KernelFifo**, Dynamic*, NvU32); #define kfifoGenerateWorkSubmitToken_HAL(pGpu, arg0, arg1, pGeneratedToken, bUsedForHost) kfifoGenerateWorkSubmitToken_DISPATCH(pGpu, arg0, arg1, pGeneratedToken, bUsedForHost) #define kfifoUpdateUsermodeDoorbell(arg0, arg1, workSubmitToken, runlisId) kfifoUpdateUsermodeDoorbell_DISPATCH(arg0, arg1, workSubmitToken, runlisId) #define kfifoUpdateUsermodeDoorbell_HAL(arg0, arg1, workSubmitToken, runlisId) kfifoUpdateUsermodeDoorbell_DISPATCH(arg0, arg1, workSubmitToken, runlisId) -#define kfifoGetMaxNumRunlists(pGpu, pKernelFifo) kfifoGetMaxNumRunlists_DISPATCH(pGpu, pKernelFifo) -#define kfifoGetMaxNumRunlists_HAL(pGpu, pKernelFifo) kfifoGetMaxNumRunlists_DISPATCH(pGpu, pKernelFifo) #define kfifoRunlistGetBaseShift(pKernelFifo) kfifoRunlistGetBaseShift_DISPATCH(pKernelFifo) #define kfifoRunlistGetBaseShift_HAL(pKernelFifo) kfifoRunlistGetBaseShift_DISPATCH(pKernelFifo) #define kfifoGetMaxCeChannelGroups(pGpu, pKernelFifo) kfifoGetMaxCeChannelGroups_DISPATCH(pGpu, pKernelFifo) @@ -550,6 +552,7 @@ NV_STATUS __nvoc_objCreate_KernelFifo(KernelFifo**, Dynamic*, NvU32); #define kfifoIsPresent(pGpu, pEngstate) kfifoIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS kfifoConstructHal_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoConstructHal(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -565,6 +568,7 @@ static inline NV_STATUS kfifoChannelGroupSetTimesliceSched_56cd7a(struct OBJGPU return NV_OK; } + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoChannelGroupSetTimesliceSched(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, struct KernelChannelGroup *pKernelChannelGroup, NvU64 timesliceUs, NvBool bSkipSubmit) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -578,6 +582,7 @@ static inline NV_STATUS kfifoChannelGroupSetTimesliceSched(struct OBJGPU *pGpu, NvU32 kfifoRunlistQueryNumChannels_KERNEL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 runlistId); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NvU32 kfifoRunlistQueryNumChannels(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 runlistId) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -591,6 +596,7 @@ static inline NvU32 kfifoRunlistQueryNumChannels(struct OBJGPU *pGpu, struct Ker NV_STATUS kfifoIdleChannelsPerDevice_KERNEL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvHandle *phClients, NvHandle *phDevices, NvHandle *phChannels, NvU32 numChannels, NvU32 flags, NvU32 timeout); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoIdleChannelsPerDevice(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvHandle *phClients, NvHandle *phDevices, NvHandle *phChannels, NvU32 numChannels, NvU32 flags, NvU32 timeout) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -604,6 +610,7 @@ static inline NV_STATUS kfifoIdleChannelsPerDevice(struct OBJGPU *pGpu, struct K NvU64 kfifoChannelGroupGetDefaultTimeslice_GV100(struct KernelFifo *pKernelFifo); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NvU64 kfifoChannelGroupGetDefaultTimeslice(struct KernelFifo *pKernelFifo) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -619,6 +626,7 @@ static inline NvU64 kfifoRunlistGetMinTimeSlice_4a4dee(struct KernelFifo *pKerne return 0; } + #ifdef __nvoc_kernel_fifo_h_disabled static inline NvU64 kfifoRunlistGetMinTimeSlice(struct KernelFifo *pKernelFifo) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -632,6 +640,7 @@ static inline NvU64 kfifoRunlistGetMinTimeSlice(struct KernelFifo *pKernelFifo) NV_STATUS kfifoGetInstMemInfo_GM107(struct KernelFifo *pKernelFifo, NvU64 *pSize, NvU64 *pAlignment, NvBool *pbInstProtectedMem, NvU32 *pInstAttr, const NV_ADDRESS_SPACE **ppInstAllocList); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoGetInstMemInfo(struct KernelFifo *pKernelFifo, NvU64 *pSize, NvU64 *pAlignment, NvBool *pbInstProtectedMem, NvU32 *pInstAttr, const NV_ADDRESS_SPACE **ppInstAllocList) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -645,6 +654,7 @@ static inline NV_STATUS kfifoGetInstMemInfo(struct KernelFifo *pKernelFifo, NvU6 void kfifoGetInstBlkSizeAlign_GM107(struct KernelFifo *pKernelFifo, NvU32 *pSize, NvU32 *pShift); + #ifdef __nvoc_kernel_fifo_h_disabled static inline void kfifoGetInstBlkSizeAlign(struct KernelFifo *pKernelFifo, NvU32 *pSize, NvU32 *pShift) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -655,21 +665,23 @@ static inline void kfifoGetInstBlkSizeAlign(struct KernelFifo *pKernelFifo, NvU3 #define kfifoGetInstBlkSizeAlign_HAL(pKernelFifo, pSize, pShift) kfifoGetInstBlkSizeAlign(pKernelFifo, pSize, pShift) -NvU32 kfifoGetDefaultRunlist_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 engineType); +NvU32 kfifoGetDefaultRunlist_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, RM_ENGINE_TYPE rmEngineType); + #ifdef __nvoc_kernel_fifo_h_disabled -static inline NvU32 kfifoGetDefaultRunlist(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 engineType) { +static inline NvU32 kfifoGetDefaultRunlist(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, RM_ENGINE_TYPE rmEngineType) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); return 0; } #else //__nvoc_kernel_fifo_h_disabled -#define kfifoGetDefaultRunlist(pGpu, pKernelFifo, engineType) kfifoGetDefaultRunlist_GM107(pGpu, pKernelFifo, engineType) +#define kfifoGetDefaultRunlist(pGpu, pKernelFifo, rmEngineType) kfifoGetDefaultRunlist_GM107(pGpu, pKernelFifo, rmEngineType) #endif //__nvoc_kernel_fifo_h_disabled -#define kfifoGetDefaultRunlist_HAL(pGpu, pKernelFifo, engineType) kfifoGetDefaultRunlist(pGpu, pKernelFifo, engineType) +#define kfifoGetDefaultRunlist_HAL(pGpu, pKernelFifo, rmEngineType) kfifoGetDefaultRunlist(pGpu, pKernelFifo, rmEngineType) NvBool kfifoValidateSCGTypeAndRunqueue_GP102(struct KernelFifo *pKernelFifo, NvU32 scgType, NvU32 runqueue); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NvBool kfifoValidateSCGTypeAndRunqueue(struct KernelFifo *pKernelFifo, NvU32 scgType, NvU32 runqueue) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -683,6 +695,7 @@ static inline NvBool kfifoValidateSCGTypeAndRunqueue(struct KernelFifo *pKernelF NvBool kfifoValidateEngineAndRunqueue_GP102(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 engDesc, NvU32 runqueue); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NvBool kfifoValidateEngineAndRunqueue(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 engDesc, NvU32 runqueue) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -696,6 +709,7 @@ static inline NvBool kfifoValidateEngineAndRunqueue(struct OBJGPU *pGpu, struct NvBool kfifoValidateEngineAndSubctxType_GP102(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 engDesc, NvU32 subctxType); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NvBool kfifoValidateEngineAndSubctxType(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 engDesc, NvU32 subctxType) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -709,6 +723,7 @@ static inline NvBool kfifoValidateEngineAndSubctxType(struct OBJGPU *pGpu, struc NV_STATUS kfifoRmctrlGetWorkSubmitToken_GV100(struct KernelFifo *pKernelFifo, NvHandle hClient, NvHandle hChannel, NvU32 *pWorkSubmitToken); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoRmctrlGetWorkSubmitToken(struct KernelFifo *pKernelFifo, NvHandle hClient, NvHandle hChannel, NvU32 *pWorkSubmitToken) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -722,6 +737,7 @@ static inline NV_STATUS kfifoRmctrlGetWorkSubmitToken(struct KernelFifo *pKernel NV_STATUS kfifoChannelGetFifoContextMemDesc_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, struct KernelChannel *pKernelChannel, FIFO_CTX engState, MEMORY_DESCRIPTOR **ppMemdesc); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoChannelGetFifoContextMemDesc(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, struct KernelChannel *pKernelChannel, FIFO_CTX engState, MEMORY_DESCRIPTOR **ppMemdesc) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -735,6 +751,7 @@ static inline NV_STATUS kfifoChannelGetFifoContextMemDesc(struct OBJGPU *pGpu, s NV_STATUS kfifoConvertInstToKernelChannel_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, INST_BLOCK_DESC *arg0, struct KernelChannel **arg1); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoConvertInstToKernelChannel(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, INST_BLOCK_DESC *arg0, struct KernelChannel **arg1) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -748,6 +765,7 @@ static inline NV_STATUS kfifoConvertInstToKernelChannel(struct OBJGPU *pGpu, str NV_STATUS kfifoGetUsermodeMapInfo_GV100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU64 *arg0, NvU32 *arg1); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoGetUsermodeMapInfo(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU64 *arg0, NvU32 *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -761,6 +779,7 @@ static inline NV_STATUS kfifoGetUsermodeMapInfo(struct OBJGPU *pGpu, struct Kern NvU32 kfifoGetMaxSubcontext_GV100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvBool arg0); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NvU32 kfifoGetMaxSubcontext(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvBool arg0) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -774,6 +793,7 @@ static inline NvU32 kfifoGetMaxSubcontext(struct OBJGPU *pGpu, struct KernelFifo NvU32 kfifoGetMaxSubcontextFromGr_KERNEL(struct OBJGPU *pGpu, struct KernelFifo *pKernel); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NvU32 kfifoGetMaxSubcontextFromGr(struct OBJGPU *pGpu, struct KernelFifo *pKernel) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -789,6 +809,7 @@ static inline NvU32 kfifoGetNumRunqueues_adde13(struct OBJGPU *pGpu, struct Kern return 2; } + #ifdef __nvoc_kernel_fifo_h_disabled static inline NvU32 kfifoGetNumRunqueues(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -802,6 +823,7 @@ static inline NvU32 kfifoGetNumRunqueues(struct OBJGPU *pGpu, struct KernelFifo NvU32 kfifoGetMaxChannelGroupSize_GV100(struct KernelFifo *pKernelFifo); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NvU32 kfifoGetMaxChannelGroupSize(struct KernelFifo *pKernelFifo) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -817,6 +839,7 @@ static inline NV_STATUS kfifoAddObject_56cd7a(struct OBJGPU *pGpu, struct Kernel return NV_OK; } + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoAddObject(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, struct ChannelDescendant *pObject) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -832,6 +855,7 @@ static inline NV_STATUS kfifoDeleteObject_56cd7a(struct OBJGPU *pGpu, struct Ker return NV_OK; } + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoDeleteObject(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, struct ChannelDescendant *pObject) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -845,6 +869,7 @@ static inline NV_STATUS kfifoDeleteObject(struct OBJGPU *pGpu, struct KernelFifo NV_STATUS kfifoConstructEngineList_KERNEL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoConstructEngineList(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -856,21 +881,23 @@ static inline NV_STATUS kfifoConstructEngineList(struct OBJGPU *pGpu, struct Ker #define kfifoConstructEngineList_HAL(pGpu, pKernelFifo) kfifoConstructEngineList(pGpu, pKernelFifo) -NV_STATUS kfifoGetHostDeviceInfoTable_KERNEL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, ENGINE_INFO *pEngineInfo); +NV_STATUS kfifoGetHostDeviceInfoTable_KERNEL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, ENGINE_INFO *pEngineInfo, NvHandle hMigClient); + #ifdef __nvoc_kernel_fifo_h_disabled -static inline NV_STATUS kfifoGetHostDeviceInfoTable(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, ENGINE_INFO *pEngineInfo) { +static inline NV_STATUS kfifoGetHostDeviceInfoTable(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, ENGINE_INFO *pEngineInfo, NvHandle hMigClient) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_fifo_h_disabled -#define kfifoGetHostDeviceInfoTable(pGpu, pKernelFifo, pEngineInfo) kfifoGetHostDeviceInfoTable_KERNEL(pGpu, pKernelFifo, pEngineInfo) +#define kfifoGetHostDeviceInfoTable(pGpu, pKernelFifo, pEngineInfo, hMigClient) kfifoGetHostDeviceInfoTable_KERNEL(pGpu, pKernelFifo, pEngineInfo, hMigClient) #endif //__nvoc_kernel_fifo_h_disabled -#define kfifoGetHostDeviceInfoTable_HAL(pGpu, pKernelFifo, pEngineInfo) kfifoGetHostDeviceInfoTable(pGpu, pKernelFifo, pEngineInfo) +#define kfifoGetHostDeviceInfoTable_HAL(pGpu, pKernelFifo, pEngineInfo, hMigClient) kfifoGetHostDeviceInfoTable(pGpu, pKernelFifo, pEngineInfo, hMigClient) void kfifoGetSubctxType_GV100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, struct KernelChannel *arg0, NvU32 *arg1); + #ifdef __nvoc_kernel_fifo_h_disabled static inline void kfifoGetSubctxType(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, struct KernelChannel *arg0, NvU32 *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -885,6 +912,13 @@ static inline NV_STATUS kfifoGenerateInternalWorkSubmitToken_c04480(struct OBJGP NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } +NV_STATUS kfifoGenerateInternalWorkSubmitToken_GA100(struct OBJGPU *pGpu, struct KernelFifo *arg0, struct KernelChannel *arg1); + +static inline NV_STATUS kfifoGenerateInternalWorkSubmitToken_5baef9(struct OBJGPU *pGpu, struct KernelFifo *arg0, struct KernelChannel *arg1) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoGenerateInternalWorkSubmitToken(struct OBJGPU *pGpu, struct KernelFifo *arg0, struct KernelChannel *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -900,6 +934,13 @@ static inline NV_STATUS kfifoUpdateInternalDoorbellForUsermode_c04480(struct OBJ NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } +NV_STATUS kfifoUpdateInternalDoorbellForUsermode_GA100(struct OBJGPU *arg0, struct KernelFifo *arg1, NvU32 workSubmitToken, NvU32 runlisId); + +static inline NV_STATUS kfifoUpdateInternalDoorbellForUsermode_5baef9(struct OBJGPU *arg0, struct KernelFifo *arg1, NvU32 workSubmitToken, NvU32 runlisId) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoUpdateInternalDoorbellForUsermode(struct OBJGPU *arg0, struct KernelFifo *arg1, NvU32 workSubmitToken, NvU32 runlisId) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -915,6 +956,7 @@ static inline NvBool kfifoIsLiteModeEnabled_491d52(struct OBJGPU *pGpu, struct K return ((NvBool)(0 != 0)); } + #ifdef __nvoc_kernel_fifo_h_disabled static inline NvBool kfifoIsLiteModeEnabled(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -928,6 +970,7 @@ static inline NvBool kfifoIsLiteModeEnabled(struct OBJGPU *pGpu, struct KernelFi NvU32 kfifoGetNumEngines_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NvU32 kfifoGetNumEngines(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -941,6 +984,7 @@ static inline NvU32 kfifoGetNumEngines(struct OBJGPU *pGpu, struct KernelFifo *p const char *kfifoGetEngineName_GM107(struct KernelFifo *pKernelFifo, ENGINE_INFO_TYPE inType, NvU32 inVal); + #ifdef __nvoc_kernel_fifo_h_disabled static inline const char *kfifoGetEngineName(struct KernelFifo *pKernelFifo, ENGINE_INFO_TYPE inType, NvU32 inVal) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -952,8 +996,23 @@ static inline const char *kfifoGetEngineName(struct KernelFifo *pKernelFifo, ENG #define kfifoGetEngineName_HAL(pKernelFifo, inType, inVal) kfifoGetEngineName(pKernelFifo, inType, inVal) +NvU32 kfifoGetMaxNumRunlists_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); + + +#ifdef __nvoc_kernel_fifo_h_disabled +static inline NvU32 kfifoGetMaxNumRunlists(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { + NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); + return 0; +} +#else //__nvoc_kernel_fifo_h_disabled +#define kfifoGetMaxNumRunlists(pGpu, pKernelFifo) kfifoGetMaxNumRunlists_GM107(pGpu, pKernelFifo) +#endif //__nvoc_kernel_fifo_h_disabled + +#define kfifoGetMaxNumRunlists_HAL(pGpu, pKernelFifo) kfifoGetMaxNumRunlists(pGpu, pKernelFifo) + NV_STATUS kfifoGetEnginePbdmaIds_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, ENGINE_INFO_TYPE type, NvU32 val, NvU32 **ppPbdmaIds, NvU32 *pNumPbdmas); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoGetEnginePbdmaIds(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, ENGINE_INFO_TYPE type, NvU32 val, NvU32 **ppPbdmaIds, NvU32 *pNumPbdmas) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -967,6 +1026,7 @@ static inline NV_STATUS kfifoGetEnginePbdmaIds(struct OBJGPU *pGpu, struct Kerne NV_STATUS kfifoGetEnginePartnerList_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS *pParams); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoGetEnginePartnerList(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS *pParams) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -982,6 +1042,7 @@ static inline NvBool kfifoRunlistIsTsgHeaderSupported_cbe027(struct OBJGPU *pGpu return ((NvBool)(0 == 0)); } + #ifdef __nvoc_kernel_fifo_h_disabled static inline NvBool kfifoRunlistIsTsgHeaderSupported(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -995,6 +1056,7 @@ static inline NvBool kfifoRunlistIsTsgHeaderSupported(struct OBJGPU *pGpu, struc NvU32 kfifoRunlistGetEntrySize_GV100(struct KernelFifo *arg0); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NvU32 kfifoRunlistGetEntrySize(struct KernelFifo *arg0) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1010,6 +1072,7 @@ static inline void kfifoSetupBar1UserdSnoop_b3696a(struct OBJGPU *pGpu, struct K return; } + #ifdef __nvoc_kernel_fifo_h_disabled static inline void kfifoSetupBar1UserdSnoop(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvBool bEnable, NvU64 offset) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1022,6 +1085,7 @@ static inline void kfifoSetupBar1UserdSnoop(struct OBJGPU *pGpu, struct KernelFi NV_STATUS kfifoPreAllocUserD_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoPreAllocUserD(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1035,6 +1099,7 @@ static inline NV_STATUS kfifoPreAllocUserD(struct OBJGPU *pGpu, struct KernelFif void kfifoFreePreAllocUserD_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); + #ifdef __nvoc_kernel_fifo_h_disabled static inline void kfifoFreePreAllocUserD(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1049,6 +1114,7 @@ static inline NvU64 kfifoGetUserdBar1MapStartOffset_4a4dee(struct OBJGPU *pGpu, return 0; } + #ifdef __nvoc_kernel_fifo_h_disabled static inline NvU64 kfifoGetUserdBar1MapStartOffset(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1062,6 +1128,7 @@ static inline NvU64 kfifoGetUserdBar1MapStartOffset(struct OBJGPU *pGpu, struct NV_STATUS kfifoGetUserdBar1MapInfo_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU64 *bar1Offset, NvU32 *bar1MapSize); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoGetUserdBar1MapInfo(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU64 *bar1Offset, NvU32 *bar1MapSize) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1075,6 +1142,7 @@ static inline NV_STATUS kfifoGetUserdBar1MapInfo(struct OBJGPU *pGpu, struct Ker void kfifoGetUserdSizeAlign_GM107(struct KernelFifo *pKernelFifo, NvU32 *pSize, NvU32 *pAddrShift); + #ifdef __nvoc_kernel_fifo_h_disabled static inline void kfifoGetUserdSizeAlign(struct KernelFifo *pKernelFifo, NvU32 *pSize, NvU32 *pAddrShift) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1087,6 +1155,7 @@ static inline void kfifoGetUserdSizeAlign(struct KernelFifo *pKernelFifo, NvU32 NV_STATUS kfifoGetUserdLocation_GM107(struct KernelFifo *pKernelFifo, NvU32 *pUserdAperture, NvU32 *pUserdAttribute); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoGetUserdLocation(struct KernelFifo *pKernelFifo, NvU32 *pUserdAperture, NvU32 *pUserdAttribute) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1100,6 +1169,7 @@ static inline NV_STATUS kfifoGetUserdLocation(struct KernelFifo *pKernelFifo, Nv NvU32 kfifoCalcTotalSizeOfFaultMethodBuffers_GV100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvBool bCalcForFbRsvd); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NvU32 kfifoCalcTotalSizeOfFaultMethodBuffers(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvBool bCalcForFbRsvd) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1113,6 +1183,7 @@ static inline NvU32 kfifoCalcTotalSizeOfFaultMethodBuffers(struct OBJGPU *pGpu, NV_STATUS kfifoCheckEngine_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 engDesc, NvBool *pPresent); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoCheckEngine(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 engDesc, NvBool *pPresent) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1126,6 +1197,7 @@ static inline NV_STATUS kfifoCheckEngine(struct OBJGPU *pGpu, struct KernelFifo NV_STATUS kfifoGetVChIdForSChId_FWCLIENT(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 chId, NvU32 gfid, NvU32 engineId, NvU32 *pVChid); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoGetVChIdForSChId(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 chId, NvU32 gfid, NvU32 engineId, NvU32 *pVChid) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1137,25 +1209,27 @@ static inline NV_STATUS kfifoGetVChIdForSChId(struct OBJGPU *pGpu, struct Kernel #define kfifoGetVChIdForSChId_HAL(pGpu, pKernelFifo, chId, gfid, engineId, pVChid) kfifoGetVChIdForSChId(pGpu, pKernelFifo, chId, gfid, engineId, pVChid) -static inline NV_STATUS kfifoProgramChIdTable_56cd7a(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 offset, NvU32 numChannels, struct HOST_VGPU_DEVICE *pHostVgpuDevice) { +static inline NV_STATUS kfifoProgramChIdTable_56cd7a(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 offset, NvU32 numChannels, NvU32 gfid, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { return NV_OK; } + #ifdef __nvoc_kernel_fifo_h_disabled -static inline NV_STATUS kfifoProgramChIdTable(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 offset, NvU32 numChannels, struct HOST_VGPU_DEVICE *pHostVgpuDevice) { +static inline NV_STATUS kfifoProgramChIdTable(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 offset, NvU32 numChannels, NvU32 gfid, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_fifo_h_disabled -#define kfifoProgramChIdTable(pGpu, pKernelFifo, pChidMgr, offset, numChannels, pHostVgpuDevice) kfifoProgramChIdTable_56cd7a(pGpu, pKernelFifo, pChidMgr, offset, numChannels, pHostVgpuDevice) +#define kfifoProgramChIdTable(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, hMigClient, engineFifoListNumEntries, pEngineFifoList) kfifoProgramChIdTable_56cd7a(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, hMigClient, engineFifoListNumEntries, pEngineFifoList) #endif //__nvoc_kernel_fifo_h_disabled -#define kfifoProgramChIdTable_HAL(pGpu, pKernelFifo, pChidMgr, offset, numChannels, pHostVgpuDevice) kfifoProgramChIdTable(pGpu, pKernelFifo, pChidMgr, offset, numChannels, pHostVgpuDevice) +#define kfifoProgramChIdTable_HAL(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, hMigClient, engineFifoListNumEntries, pEngineFifoList) kfifoProgramChIdTable(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, hMigClient, engineFifoListNumEntries, pEngineFifoList) static inline NV_STATUS kfifoRestoreSchedPolicy_56cd7a(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { return NV_OK; } + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoRestoreSchedPolicy(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1169,6 +1243,7 @@ static inline NV_STATUS kfifoRestoreSchedPolicy(struct OBJGPU *pGpu, struct Kern NV_STATUS kfifoRunlistSetId_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, struct KernelChannel *arg0, NvU32 runlistId); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoRunlistSetId(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, struct KernelChannel *arg0, NvU32 runlistId) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1182,6 +1257,7 @@ static inline NV_STATUS kfifoRunlistSetId(struct OBJGPU *pGpu, struct KernelFifo NV_STATUS kfifoRunlistSetIdByEngine_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, struct KernelChannel *arg0, NvU32 engDesc); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoRunlistSetIdByEngine(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, struct KernelChannel *arg0, NvU32 engDesc) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1213,20 +1289,12 @@ static inline void kfifoStateDestroy_DISPATCH(struct OBJGPU *pGpu, struct Kernel NV_STATUS kfifoStatePostLoad_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 flags); -static inline NV_STATUS kfifoStatePostLoad_56cd7a(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 flags) { - return NV_OK; -} - static inline NV_STATUS kfifoStatePostLoad_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 flags) { return pKernelFifo->__kfifoStatePostLoad__(pGpu, pKernelFifo, flags); } NV_STATUS kfifoStatePreUnload_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 flags); -static inline NV_STATUS kfifoStatePreUnload_56cd7a(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 flags) { - return NV_OK; -} - static inline NV_STATUS kfifoStatePreUnload_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 flags) { return pKernelFifo->__kfifoStatePreUnload__(pGpu, pKernelFifo, flags); } @@ -1265,10 +1333,6 @@ NvU32 kfifoChannelGroupGetLocalMaxSubcontext_GM107(struct OBJGPU *pGpu, struct K NvU32 kfifoChannelGroupGetLocalMaxSubcontext_GA100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, struct KernelChannelGroup *arg0, NvBool arg1); -static inline NvU32 kfifoChannelGroupGetLocalMaxSubcontext_474d46(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, struct KernelChannelGroup *arg0, NvBool arg1) { - NV_ASSERT_OR_RETURN_PRECOMP(0, 0); -} - static inline NvU32 kfifoChannelGroupGetLocalMaxSubcontext_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, struct KernelChannelGroup *arg0, NvBool arg1) { return pKernelFifo->__kfifoChannelGroupGetLocalMaxSubcontext__(pGpu, pKernelFifo, arg0, arg1); } @@ -1287,10 +1351,6 @@ NV_STATUS kfifoEngineInfoXlate_GV100(struct OBJGPU *pGpu, struct KernelFifo *pKe NV_STATUS kfifoEngineInfoXlate_GA100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, ENGINE_INFO_TYPE inType, NvU32 inVal, ENGINE_INFO_TYPE outType, NvU32 *pOutVal); -static inline NV_STATUS kfifoEngineInfoXlate_46f6a7(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, ENGINE_INFO_TYPE inType, NvU32 inVal, ENGINE_INFO_TYPE outType, NvU32 *pOutVal) { - return NV_ERR_NOT_SUPPORTED; -} - static inline NV_STATUS kfifoEngineInfoXlate_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, ENGINE_INFO_TYPE inType, NvU32 inVal, ENGINE_INFO_TYPE outType, NvU32 *pOutVal) { return pKernelFifo->__kfifoEngineInfoXlate__(pGpu, pKernelFifo, inType, inVal, outType, pOutVal); } @@ -1299,10 +1359,6 @@ NV_STATUS kfifoGenerateWorkSubmitToken_TU102(struct OBJGPU *pGpu, struct KernelF NV_STATUS kfifoGenerateWorkSubmitToken_GA100(struct OBJGPU *pGpu, struct KernelFifo *arg0, struct KernelChannel *arg1, NvU32 *pGeneratedToken, NvBool bUsedForHost); -static inline NV_STATUS kfifoGenerateWorkSubmitToken_56cd7a(struct OBJGPU *pGpu, struct KernelFifo *arg0, struct KernelChannel *arg1, NvU32 *pGeneratedToken, NvBool bUsedForHost) { - return NV_OK; -} - static inline NV_STATUS kfifoGenerateWorkSubmitToken_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *arg0, struct KernelChannel *arg1, NvU32 *pGeneratedToken, NvBool bUsedForHost) { return arg0->__kfifoGenerateWorkSubmitToken__(pGpu, arg0, arg1, pGeneratedToken, bUsedForHost); } @@ -1311,36 +1367,16 @@ NV_STATUS kfifoUpdateUsermodeDoorbell_TU102(struct OBJGPU *arg0, struct KernelFi NV_STATUS kfifoUpdateUsermodeDoorbell_GA100(struct OBJGPU *arg0, struct KernelFifo *arg1, NvU32 workSubmitToken, NvU32 runlisId); -static inline NV_STATUS kfifoUpdateUsermodeDoorbell_46f6a7(struct OBJGPU *arg0, struct KernelFifo *arg1, NvU32 workSubmitToken, NvU32 runlisId) { - return NV_ERR_NOT_SUPPORTED; -} - static inline NV_STATUS kfifoUpdateUsermodeDoorbell_DISPATCH(struct OBJGPU *arg0, struct KernelFifo *arg1, NvU32 workSubmitToken, NvU32 runlisId) { return arg1->__kfifoUpdateUsermodeDoorbell__(arg0, arg1, workSubmitToken, runlisId); } -NvU32 kfifoGetMaxNumRunlists_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); - -NvU32 kfifoGetMaxNumRunlists_GH100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); - -static inline NvU32 kfifoGetMaxNumRunlists_4a4dee(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { - return 0; -} - -static inline NvU32 kfifoGetMaxNumRunlists_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { - return pKernelFifo->__kfifoGetMaxNumRunlists__(pGpu, pKernelFifo); -} - NvU32 kfifoRunlistGetBaseShift_GM107(struct KernelFifo *pKernelFifo); NvU32 kfifoRunlistGetBaseShift_GA100(struct KernelFifo *pKernelFifo); NvU32 kfifoRunlistGetBaseShift_GA102(struct KernelFifo *pKernelFifo); -static inline NvU32 kfifoRunlistGetBaseShift_474d46(struct KernelFifo *pKernelFifo) { - NV_ASSERT_OR_RETURN_PRECOMP(0, 0); -} - static inline NvU32 kfifoRunlistGetBaseShift_DISPATCH(struct KernelFifo *pKernelFifo) { return pKernelFifo->__kfifoRunlistGetBaseShift__(pKernelFifo); } @@ -1349,10 +1385,6 @@ NvU32 kfifoGetMaxCeChannelGroups_GV100(struct OBJGPU *pGpu, struct KernelFifo *p NvU32 kfifoGetMaxCeChannelGroups_GA100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); -static inline NvU32 kfifoGetMaxCeChannelGroups_474d46(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { - NV_ASSERT_OR_RETURN_PRECOMP(0, 0); -} - static inline NvU32 kfifoGetMaxCeChannelGroups_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { return pKernelFifo->__kfifoGetMaxCeChannelGroups__(pGpu, pKernelFifo); } @@ -1361,10 +1393,6 @@ void kfifoSetupUserD_GM107(struct KernelFifo *pKernelFifo, NvU8 *pUserD); void kfifoSetupUserD_GA100(struct KernelFifo *pKernelFifo, NvU8 *pUserD); -static inline void kfifoSetupUserD_f2d351(struct KernelFifo *pKernelFifo, NvU8 *pUserD) { - NV_ASSERT_PRECOMP(0); -} - static inline void kfifoSetupUserD_DISPATCH(struct KernelFifo *pKernelFifo, NvU8 *pUserD) { pKernelFifo->__kfifoSetupUserD__(pKernelFifo, pUserD); } @@ -1429,18 +1457,6 @@ static inline NvBool kfifoIsPresent_DISPATCH(POBJGPU pGpu, struct KernelFifo *pE return pEngstate->__kfifoIsPresent__(pGpu, pEngstate); } -static inline NV_STATUS kfifoChidMgrReserveSystemChids(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 numChannels, struct HOST_VGPU_DEVICE *pHostVgpuDevice, NvU32 flags) { - return NV_ERR_NOT_SUPPORTED; -} - -static inline NV_STATUS kfifoChidMgrFreeSystemChids(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, struct HOST_VGPU_DEVICE *pHostVgpuDevice) { - return NV_ERR_NOT_SUPPORTED; -} - -static inline NV_STATUS kfifoSetChidOffset(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 offset, NvU32 numChannels, struct HOST_VGPU_DEVICE *pHostVgpuDevice) { - return NV_ERR_NOT_SUPPORTED; -} - static inline const ENGINE_INFO *kfifoGetEngineInfo(struct KernelFifo *pKernelFifo) { if (pKernelFifo->engineInfo.engineInfoList == ((void *)0)) return ((void *)0); @@ -1500,7 +1516,7 @@ static inline NvBool kfifoIsSchedSupported(struct KernelFifo *pKernelFifo) { } static inline struct KernelSchedMgr *kfifoGetKernelSchedMgr(struct KernelFifo *pKernelFifo) { - return (struct KernelSchedMgr *)pKernelFifo->pKernelSchedMgr; + return pKernelFifo->pKernelSchedMgr; } static inline MEMORY_DESCRIPTOR *kfifoGetDummyPageMemDesc(struct KernelFifo *pKernelFifo) { @@ -1508,8 +1524,10 @@ static inline MEMORY_DESCRIPTOR *kfifoGetDummyPageMemDesc(struct KernelFifo *pKe } void kfifoDestruct_IMPL(struct KernelFifo *pKernelFifo); + #define __nvoc_kfifoDestruct(pKernelFifo) kfifoDestruct_IMPL(pKernelFifo) NV_STATUS kfifoChidMgrConstruct_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoChidMgrConstruct(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1520,6 +1538,7 @@ static inline NV_STATUS kfifoChidMgrConstruct(struct OBJGPU *pGpu, struct Kernel #endif //__nvoc_kernel_fifo_h_disabled void kfifoChidMgrDestruct_IMPL(struct KernelFifo *pKernelFifo); + #ifdef __nvoc_kernel_fifo_h_disabled static inline void kfifoChidMgrDestruct(struct KernelFifo *pKernelFifo) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1529,6 +1548,7 @@ static inline void kfifoChidMgrDestruct(struct KernelFifo *pKernelFifo) { #endif //__nvoc_kernel_fifo_h_disabled NV_STATUS kfifoChidMgrAllocChid_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvHandle hClient, CHANNEL_HW_ID_ALLOC_MODE arg0, NvBool bForceInternalIdx, NvU32 internalIdx, NvBool bForceUserdPage, NvU32 userdPageIdx, NvU32 ChID, struct KernelChannel *arg1); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoChidMgrAllocChid(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvHandle hClient, CHANNEL_HW_ID_ALLOC_MODE arg0, NvBool bForceInternalIdx, NvU32 internalIdx, NvBool bForceUserdPage, NvU32 userdPageIdx, NvU32 ChID, struct KernelChannel *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1539,6 +1559,7 @@ static inline NV_STATUS kfifoChidMgrAllocChid(struct OBJGPU *pGpu, struct Kernel #endif //__nvoc_kernel_fifo_h_disabled NV_STATUS kfifoChidMgrRetainChid_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 ChID); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoChidMgrRetainChid(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 ChID) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1549,6 +1570,7 @@ static inline NV_STATUS kfifoChidMgrRetainChid(struct OBJGPU *pGpu, struct Kerne #endif //__nvoc_kernel_fifo_h_disabled NV_STATUS kfifoChidMgrReleaseChid_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 ChID); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoChidMgrReleaseChid(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 ChID) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1559,6 +1581,7 @@ static inline NV_STATUS kfifoChidMgrReleaseChid(struct OBJGPU *pGpu, struct Kern #endif //__nvoc_kernel_fifo_h_disabled NV_STATUS kfifoChidMgrFreeChid_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 ChID); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoChidMgrFreeChid(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 ChID) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1568,7 +1591,41 @@ static inline NV_STATUS kfifoChidMgrFreeChid(struct OBJGPU *pGpu, struct KernelF #define kfifoChidMgrFreeChid(pGpu, pKernelFifo, pChidMgr, ChID) kfifoChidMgrFreeChid_IMPL(pGpu, pKernelFifo, pChidMgr, ChID) #endif //__nvoc_kernel_fifo_h_disabled +NV_STATUS kfifoChidMgrReserveSystemChids_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 numChannels, NvU32 flags, NvU32 gfid, NvU32 *pChidOffset, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList); + +#ifdef __nvoc_kernel_fifo_h_disabled +static inline NV_STATUS kfifoChidMgrReserveSystemChids(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 numChannels, NvU32 flags, NvU32 gfid, NvU32 *pChidOffset, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { + NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_fifo_h_disabled +#define kfifoChidMgrReserveSystemChids(pGpu, pKernelFifo, pChidMgr, numChannels, flags, gfid, pChidOffset, hMigClient, engineFifoListNumEntries, pEngineFifoList) kfifoChidMgrReserveSystemChids_IMPL(pGpu, pKernelFifo, pChidMgr, numChannels, flags, gfid, pChidOffset, hMigClient, engineFifoListNumEntries, pEngineFifoList) +#endif //__nvoc_kernel_fifo_h_disabled + +NV_STATUS kfifoChidMgrFreeSystemChids_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 gfid, NvU32 *pChidOffset, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList); + +#ifdef __nvoc_kernel_fifo_h_disabled +static inline NV_STATUS kfifoChidMgrFreeSystemChids(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 gfid, NvU32 *pChidOffset, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { + NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_fifo_h_disabled +#define kfifoChidMgrFreeSystemChids(pGpu, pKernelFifo, pChidMgr, gfid, pChidOffset, hMigClient, engineFifoListNumEntries, pEngineFifoList) kfifoChidMgrFreeSystemChids_IMPL(pGpu, pKernelFifo, pChidMgr, gfid, pChidOffset, hMigClient, engineFifoListNumEntries, pEngineFifoList) +#endif //__nvoc_kernel_fifo_h_disabled + +NV_STATUS kfifoSetChidOffset_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 offset, NvU32 numChannels, NvU32 gfid, NvU32 *pChidOffset, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList); + +#ifdef __nvoc_kernel_fifo_h_disabled +static inline NV_STATUS kfifoSetChidOffset(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 offset, NvU32 numChannels, NvU32 gfid, NvU32 *pChidOffset, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { + NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_fifo_h_disabled +#define kfifoSetChidOffset(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, pChidOffset, hMigClient, engineFifoListNumEntries, pEngineFifoList) kfifoSetChidOffset_IMPL(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, pChidOffset, hMigClient, engineFifoListNumEntries, pEngineFifoList) +#endif //__nvoc_kernel_fifo_h_disabled + NvU32 kfifoChidMgrGetNumChannels_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NvU32 kfifoChidMgrGetNumChannels(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1579,6 +1636,7 @@ static inline NvU32 kfifoChidMgrGetNumChannels(struct OBJGPU *pGpu, struct Kerne #endif //__nvoc_kernel_fifo_h_disabled NV_STATUS kfifoChidMgrAllocChannelGroupHwID_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 *pGrpId); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoChidMgrAllocChannelGroupHwID(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 *pGrpId) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1589,6 +1647,7 @@ static inline NV_STATUS kfifoChidMgrAllocChannelGroupHwID(struct OBJGPU *pGpu, s #endif //__nvoc_kernel_fifo_h_disabled NV_STATUS kfifoChidMgrFreeChannelGroupHwID_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 grpId); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoChidMgrFreeChannelGroupHwID(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 grpId) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1599,6 +1658,7 @@ static inline NV_STATUS kfifoChidMgrFreeChannelGroupHwID(struct OBJGPU *pGpu, st #endif //__nvoc_kernel_fifo_h_disabled struct KernelChannelGroup *kfifoChidMgrGetKernelChannelGroup_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 grpID); + #ifdef __nvoc_kernel_fifo_h_disabled static inline struct KernelChannelGroup *kfifoChidMgrGetKernelChannelGroup(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 grpID) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1609,6 +1669,7 @@ static inline struct KernelChannelGroup *kfifoChidMgrGetKernelChannelGroup(struc #endif //__nvoc_kernel_fifo_h_disabled struct KernelChannel *kfifoChidMgrGetKernelChannel_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 ChID); + #ifdef __nvoc_kernel_fifo_h_disabled static inline struct KernelChannel *kfifoChidMgrGetKernelChannel(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 ChID) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1619,6 +1680,7 @@ static inline struct KernelChannel *kfifoChidMgrGetKernelChannel(struct OBJGPU * #endif //__nvoc_kernel_fifo_h_disabled CHID_MGR *kfifoGetChidMgr_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 runlistId); + #ifdef __nvoc_kernel_fifo_h_disabled static inline CHID_MGR *kfifoGetChidMgr(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 runlistId) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1628,17 +1690,19 @@ static inline CHID_MGR *kfifoGetChidMgr(struct OBJGPU *pGpu, struct KernelFifo * #define kfifoGetChidMgr(pGpu, pKernelFifo, runlistId) kfifoGetChidMgr_IMPL(pGpu, pKernelFifo, runlistId) #endif //__nvoc_kernel_fifo_h_disabled -NV_STATUS kfifoGetChidMgrFromType_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 engineType, NvU32 value, CHID_MGR **arg0); +NV_STATUS kfifoGetChidMgrFromType_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 engineInfoType, NvU32 value, CHID_MGR **arg0); + #ifdef __nvoc_kernel_fifo_h_disabled -static inline NV_STATUS kfifoGetChidMgrFromType(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 engineType, NvU32 value, CHID_MGR **arg0) { +static inline NV_STATUS kfifoGetChidMgrFromType(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 engineInfoType, NvU32 value, CHID_MGR **arg0) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_fifo_h_disabled -#define kfifoGetChidMgrFromType(pGpu, pKernelFifo, engineType, value, arg0) kfifoGetChidMgrFromType_IMPL(pGpu, pKernelFifo, engineType, value, arg0) +#define kfifoGetChidMgrFromType(pGpu, pKernelFifo, engineInfoType, value, arg0) kfifoGetChidMgrFromType_IMPL(pGpu, pKernelFifo, engineInfoType, value, arg0) #endif //__nvoc_kernel_fifo_h_disabled struct KernelChannelGroup *kfifoGetChannelGroup_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 grpID, NvU32 runlistID); + #ifdef __nvoc_kernel_fifo_h_disabled static inline struct KernelChannelGroup *kfifoGetChannelGroup(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 grpID, NvU32 runlistID) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1649,6 +1713,7 @@ static inline struct KernelChannelGroup *kfifoGetChannelGroup(struct OBJGPU *pGp #endif //__nvoc_kernel_fifo_h_disabled NvU32 kfifoGetChannelGroupsInUse_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NvU32 kfifoGetChannelGroupsInUse(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1659,6 +1724,7 @@ static inline NvU32 kfifoGetChannelGroupsInUse(struct OBJGPU *pGpu, struct Kerne #endif //__nvoc_kernel_fifo_h_disabled NvU32 kfifoGetRunlistChannelGroupsInUse_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 runlistId); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NvU32 kfifoGetRunlistChannelGroupsInUse(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 runlistId) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1669,6 +1735,7 @@ static inline NvU32 kfifoGetRunlistChannelGroupsInUse(struct OBJGPU *pGpu, struc #endif //__nvoc_kernel_fifo_h_disabled void kfifoGetChannelIterator_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHANNEL_ITERATOR *pIt); + #ifdef __nvoc_kernel_fifo_h_disabled static inline void kfifoGetChannelIterator(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHANNEL_ITERATOR *pIt) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1678,6 +1745,7 @@ static inline void kfifoGetChannelIterator(struct OBJGPU *pGpu, struct KernelFif #endif //__nvoc_kernel_fifo_h_disabled NV_STATUS kfifoGetNextKernelChannel_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHANNEL_ITERATOR *pIt, struct KernelChannel **ppKernelChannel); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoGetNextKernelChannel(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHANNEL_ITERATOR *pIt, struct KernelChannel **ppKernelChannel) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1688,6 +1756,7 @@ static inline NV_STATUS kfifoGetNextKernelChannel(struct OBJGPU *pGpu, struct Ke #endif //__nvoc_kernel_fifo_h_disabled void kfifoFillMemInfo_IMPL(struct KernelFifo *pKernelFifo, MEMORY_DESCRIPTOR *pMemDesc, NV2080_CTRL_FIFO_MEM_INFO *pMemory); + #ifdef __nvoc_kernel_fifo_h_disabled static inline void kfifoFillMemInfo(struct KernelFifo *pKernelFifo, MEMORY_DESCRIPTOR *pMemDesc, NV2080_CTRL_FIFO_MEM_INFO *pMemory) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1696,17 +1765,19 @@ static inline void kfifoFillMemInfo(struct KernelFifo *pKernelFifo, MEMORY_DESCR #define kfifoFillMemInfo(pKernelFifo, pMemDesc, pMemory) kfifoFillMemInfo_IMPL(pKernelFifo, pMemDesc, pMemory) #endif //__nvoc_kernel_fifo_h_disabled -NvU32 kfifoGetAllocatedChannelMask_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); +NvU32 kfifoGetAllocatedChannelMask_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 runlistId, NvU32 *pBitMask, NvLength bitMaskSize); + #ifdef __nvoc_kernel_fifo_h_disabled -static inline NvU32 kfifoGetAllocatedChannelMask(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { +static inline NvU32 kfifoGetAllocatedChannelMask(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 runlistId, NvU32 *pBitMask, NvLength bitMaskSize) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); return 0; } #else //__nvoc_kernel_fifo_h_disabled -#define kfifoGetAllocatedChannelMask(pGpu, pKernelFifo) kfifoGetAllocatedChannelMask_IMPL(pGpu, pKernelFifo) +#define kfifoGetAllocatedChannelMask(pGpu, pKernelFifo, runlistId, pBitMask, bitMaskSize) kfifoGetAllocatedChannelMask_IMPL(pGpu, pKernelFifo, runlistId, pBitMask, bitMaskSize) #endif //__nvoc_kernel_fifo_h_disabled NV_STATUS kfifoChannelListCreate_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHANNEL_LIST **arg0); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoChannelListCreate(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHANNEL_LIST **arg0) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1717,6 +1788,7 @@ static inline NV_STATUS kfifoChannelListCreate(struct OBJGPU *pGpu, struct Kerne #endif //__nvoc_kernel_fifo_h_disabled NV_STATUS kfifoChannelListDestroy_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHANNEL_LIST *arg0); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoChannelListDestroy(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHANNEL_LIST *arg0) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1727,6 +1799,7 @@ static inline NV_STATUS kfifoChannelListDestroy(struct OBJGPU *pGpu, struct Kern #endif //__nvoc_kernel_fifo_h_disabled NV_STATUS kfifoChannelListAppend_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, struct KernelChannel *arg0, CHANNEL_LIST *arg1); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoChannelListAppend(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, struct KernelChannel *arg0, CHANNEL_LIST *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1737,6 +1810,7 @@ static inline NV_STATUS kfifoChannelListAppend(struct OBJGPU *pGpu, struct Kerne #endif //__nvoc_kernel_fifo_h_disabled NV_STATUS kfifoChannelListRemove_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, struct KernelChannel *arg0, CHANNEL_LIST *arg1); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoChannelListRemove(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, struct KernelChannel *arg0, CHANNEL_LIST *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1746,9 +1820,10 @@ static inline NV_STATUS kfifoChannelListRemove(struct OBJGPU *pGpu, struct Kerne #define kfifoChannelListRemove(pGpu, pKernelFifo, arg0, arg1) kfifoChannelListRemove_IMPL(pGpu, pKernelFifo, arg0, arg1) #endif //__nvoc_kernel_fifo_h_disabled -NvBool kfifoEngineListHasChannel_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 *arg0, NvU32 arg1); +NvBool kfifoEngineListHasChannel_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, RM_ENGINE_TYPE *arg0, NvU32 arg1); + #ifdef __nvoc_kernel_fifo_h_disabled -static inline NvBool kfifoEngineListHasChannel(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 *arg0, NvU32 arg1) { +static inline NvBool kfifoEngineListHasChannel(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, RM_ENGINE_TYPE *arg0, NvU32 arg1) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); return NV_FALSE; } @@ -1756,17 +1831,19 @@ static inline NvBool kfifoEngineListHasChannel(struct OBJGPU *pGpu, struct Kerne #define kfifoEngineListHasChannel(pGpu, pKernelFifo, arg0, arg1) kfifoEngineListHasChannel_IMPL(pGpu, pKernelFifo, arg0, arg1) #endif //__nvoc_kernel_fifo_h_disabled -CTX_BUF_POOL_INFO *kfifoGetRunlistBufPool_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 engineType); +CTX_BUF_POOL_INFO *kfifoGetRunlistBufPool_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, RM_ENGINE_TYPE rmEngineType); + #ifdef __nvoc_kernel_fifo_h_disabled -static inline CTX_BUF_POOL_INFO *kfifoGetRunlistBufPool(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 engineType) { +static inline CTX_BUF_POOL_INFO *kfifoGetRunlistBufPool(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, RM_ENGINE_TYPE rmEngineType) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); return NULL; } #else //__nvoc_kernel_fifo_h_disabled -#define kfifoGetRunlistBufPool(pGpu, pKernelFifo, engineType) kfifoGetRunlistBufPool_IMPL(pGpu, pKernelFifo, engineType) +#define kfifoGetRunlistBufPool(pGpu, pKernelFifo, rmEngineType) kfifoGetRunlistBufPool_IMPL(pGpu, pKernelFifo, rmEngineType) #endif //__nvoc_kernel_fifo_h_disabled NV_STATUS kfifoGetRunlistBufInfo_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 arg0, NvBool arg1, NvU32 arg2, NvU64 *arg3, NvU64 *arg4); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoGetRunlistBufInfo(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 arg0, NvBool arg1, NvU32 arg2, NvU64 *arg3, NvU64 *arg4) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1777,6 +1854,7 @@ static inline NV_STATUS kfifoGetRunlistBufInfo(struct OBJGPU *pGpu, struct Kerne #endif //__nvoc_kernel_fifo_h_disabled NV_STATUS kfifoAddSchedulingHandler_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, PFifoSchedulingHandler pPostSchedulingEnableHandler, void *pPostSchedulingEnableHandlerData, PFifoSchedulingHandler pPreSchedulingDisableHandler, void *pPreSchedulingDisableHandlerData); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoAddSchedulingHandler(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, PFifoSchedulingHandler pPostSchedulingEnableHandler, void *pPostSchedulingEnableHandlerData, PFifoSchedulingHandler pPreSchedulingDisableHandler, void *pPreSchedulingDisableHandlerData) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1787,6 +1865,7 @@ static inline NV_STATUS kfifoAddSchedulingHandler(struct OBJGPU *pGpu, struct Ke #endif //__nvoc_kernel_fifo_h_disabled void kfifoRemoveSchedulingHandler_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, PFifoSchedulingHandler pPostSchedulingEnableHandler, void *pPostSchedulingEnableHandlerData, PFifoSchedulingHandler pPreSchedulingDisableHandler, void *pPreSchedulingDisableHandlerData); + #ifdef __nvoc_kernel_fifo_h_disabled static inline void kfifoRemoveSchedulingHandler(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, PFifoSchedulingHandler pPostSchedulingEnableHandler, void *pPostSchedulingEnableHandlerData, PFifoSchedulingHandler pPreSchedulingDisableHandler, void *pPreSchedulingDisableHandlerData) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1796,6 +1875,7 @@ static inline void kfifoRemoveSchedulingHandler(struct OBJGPU *pGpu, struct Kern #endif //__nvoc_kernel_fifo_h_disabled NV_STATUS kfifoTriggerPostSchedulingEnableCallback_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoTriggerPostSchedulingEnableCallback(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1806,6 +1886,7 @@ static inline NV_STATUS kfifoTriggerPostSchedulingEnableCallback(struct OBJGPU * #endif //__nvoc_kernel_fifo_h_disabled NV_STATUS kfifoTriggerPreSchedulingDisableCallback_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoTriggerPreSchedulingDisableCallback(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1816,6 +1897,7 @@ static inline NV_STATUS kfifoTriggerPreSchedulingDisableCallback(struct OBJGPU * #endif //__nvoc_kernel_fifo_h_disabled NvU32 kfifoGetMaxChannelsInSystem_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NvU32 kfifoGetMaxChannelsInSystem(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1826,6 +1908,7 @@ static inline NvU32 kfifoGetMaxChannelsInSystem(struct OBJGPU *pGpu, struct Kern #endif //__nvoc_kernel_fifo_h_disabled NvU32 kfifoGetMaxChannelGroupsInSystem_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NvU32 kfifoGetMaxChannelGroupsInSystem(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1836,6 +1919,7 @@ static inline NvU32 kfifoGetMaxChannelGroupsInSystem(struct OBJGPU *pGpu, struct #endif //__nvoc_kernel_fifo_h_disabled void kfifoGetDeviceCaps_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU8 *pKfifoCaps, NvBool bCapsInitialized); + #ifdef __nvoc_kernel_fifo_h_disabled static inline void kfifoGetDeviceCaps(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU8 *pKfifoCaps, NvBool bCapsInitialized) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1845,6 +1929,7 @@ static inline void kfifoGetDeviceCaps(struct OBJGPU *pGpu, struct KernelFifo *pK #endif //__nvoc_kernel_fifo_h_disabled NvU32 kfifoReturnPushbufferCaps_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NvU32 kfifoReturnPushbufferCaps(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1855,8 +1940,10 @@ static inline NvU32 kfifoReturnPushbufferCaps(struct OBJGPU *pGpu, struct Kernel #endif //__nvoc_kernel_fifo_h_disabled void kfifoRunlistGetBufAllocParams_IMPL(struct OBJGPU *pGpu, NV_ADDRESS_SPACE *pAperture, NvU32 *pAttr, NvU64 *pAllocFlags); + #define kfifoRunlistGetBufAllocParams(pGpu, pAperture, pAttr, pAllocFlags) kfifoRunlistGetBufAllocParams_IMPL(pGpu, pAperture, pAttr, pAllocFlags) NV_STATUS kfifoRunlistAllocBuffers_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvBool bSupportTsg, NV_ADDRESS_SPACE aperture, NvU32 runlistId, NvU32 attr, NvU64 allocFlags, NvU64 maxRunlistEntries, NvBool bHWRL, PMEMORY_DESCRIPTOR *ppMemDesc); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoRunlistAllocBuffers(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvBool bSupportTsg, NV_ADDRESS_SPACE aperture, NvU32 runlistId, NvU32 attr, NvU64 allocFlags, NvU64 maxRunlistEntries, NvBool bHWRL, PMEMORY_DESCRIPTOR *ppMemDesc) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1866,9 +1953,10 @@ static inline NV_STATUS kfifoRunlistAllocBuffers(struct OBJGPU *pGpu, struct Ker #define kfifoRunlistAllocBuffers(pGpu, pKernelFifo, bSupportTsg, aperture, runlistId, attr, allocFlags, maxRunlistEntries, bHWRL, ppMemDesc) kfifoRunlistAllocBuffers_IMPL(pGpu, pKernelFifo, bSupportTsg, aperture, runlistId, attr, allocFlags, maxRunlistEntries, bHWRL, ppMemDesc) #endif //__nvoc_kernel_fifo_h_disabled -NV_STATUS kfifoGetEngineListForRunlist_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 runlistId, NvU32 *pOutEngineIds, NvU32 *pNumEngines); +NV_STATUS kfifoGetEngineListForRunlist_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 runlistId, RM_ENGINE_TYPE *pOutEngineIds, NvU32 *pNumEngines); + #ifdef __nvoc_kernel_fifo_h_disabled -static inline NV_STATUS kfifoGetEngineListForRunlist(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 runlistId, NvU32 *pOutEngineIds, NvU32 *pNumEngines) { +static inline NV_STATUS kfifoGetEngineListForRunlist(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 runlistId, RM_ENGINE_TYPE *pOutEngineIds, NvU32 *pNumEngines) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1877,6 +1965,7 @@ static inline NV_STATUS kfifoGetEngineListForRunlist(struct OBJGPU *pGpu, struct #endif //__nvoc_kernel_fifo_h_disabled NvU32 kfifoGetChannelClassId_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NvU32 kfifoGetChannelClassId(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1887,6 +1976,7 @@ static inline NvU32 kfifoGetChannelClassId(struct OBJGPU *pGpu, struct KernelFif #endif //__nvoc_kernel_fifo_h_disabled NV_STATUS kfifoChannelGroupSetTimeslice_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, struct KernelChannelGroup *pKernelChannelGroup, NvU64 timesliceUs, NvBool bSkipSubmit); + #ifdef __nvoc_kernel_fifo_h_disabled static inline NV_STATUS kfifoChannelGroupSetTimeslice(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, struct KernelChannelGroup *pKernelChannelGroup, NvU64 timesliceUs, NvBool bSkipSubmit) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); @@ -1896,6 +1986,9 @@ static inline NV_STATUS kfifoChannelGroupSetTimeslice(struct OBJGPU *pGpu, struc #define kfifoChannelGroupSetTimeslice(pGpu, pKernelFifo, pKernelChannelGroup, timesliceUs, bSkipSubmit) kfifoChannelGroupSetTimeslice_IMPL(pGpu, pKernelFifo, pKernelChannelGroup, timesliceUs, bSkipSubmit) #endif //__nvoc_kernel_fifo_h_disabled +const FIFO_GUEST_ENGINE_TABLE *kfifoGetGuestEngineLookupTable_IMPL(NvU32 *pTableSize); + +#define kfifoGetGuestEngineLookupTable(pTableSize) kfifoGetGuestEngineLookupTable_IMPL(pTableSize) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_kernel_graphics_context_nvoc.c b/src/nvidia/generated/g_kernel_graphics_context_nvoc.c index f4e7a62c3..597752517 100644 --- a/src/nvidia/generated/g_kernel_graphics_context_nvoc.c +++ b/src/nvidia/generated/g_kernel_graphics_context_nvoc.c @@ -165,6 +165,10 @@ static NV_STATUS __nvoc_thunk_RsResource_kgrctxUnmapFrom(struct KernelGraphicsCo return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_kgrctxIsDuplicate(struct KernelGraphicsContext *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_kgrctxControl_Epilogue(struct KernelGraphicsContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RmResource.offset), pCallContext, pParams); } @@ -363,6 +367,8 @@ static void __nvoc_init_funcTable_KernelGraphicsContext_1(KernelGraphicsContext pThis->__kgrctxUnmapFrom__ = &__nvoc_thunk_RsResource_kgrctxUnmapFrom; + pThis->__kgrctxIsDuplicate__ = &__nvoc_thunk_RsResource_kgrctxIsDuplicate; + pThis->__kgrctxControl_Epilogue__ = &__nvoc_thunk_RmResource_kgrctxControl_Epilogue; pThis->__kgrctxControlLookup__ = &__nvoc_thunk_RsResource_kgrctxControlLookup; diff --git a/src/nvidia/generated/g_kernel_graphics_context_nvoc.h b/src/nvidia/generated/g_kernel_graphics_context_nvoc.h index 317885468..34006173b 100644 --- a/src/nvidia/generated/g_kernel_graphics_context_nvoc.h +++ b/src/nvidia/generated/g_kernel_graphics_context_nvoc.h @@ -41,8 +41,8 @@ extern "C" { #include "ctrl/ctrl0090.h" #include "mmu/gmmu_fmt.h" #include "gpu/gpu_halspec.h" -#include "utils/nv_enum.h" #include "mem_mgr/vaddr_list.h" +#include "kernel/gpu/gr/kernel_graphics_context_buffers.h" struct KernelChannel; @@ -75,23 +75,11 @@ typedef struct NvU32 cpuAttr; } GR_BUFFER_ATTR; -typedef struct +typedef struct NV_CONTEXT_BUFFER { - MEMORY_DESCRIPTOR *memDesc; + MEMORY_DESCRIPTOR *pMemDesc; VA_LIST vAddrList; -} GR_CTX_PATCHBUFFER; - -typedef struct -{ - MEMORY_DESCRIPTOR *memDesc; - VA_LIST vAddrList; -} GR_CTX_ZCULLBUFFER; - -typedef struct -{ - MEMORY_DESCRIPTOR *memDesc; - VA_LIST vAddrList; -} GR_CTX_PMBUFFER; +} NV_CONTEXT_BUFFER; typedef enum { @@ -102,54 +90,10 @@ typedef enum GR_OBJECT_TYPE_INVALID, } GR_OBJECT_TYPE; -typedef struct -{ - MEMORY_DESCRIPTOR *pMemDesc; - NvU64 virtualAddr; -} GR_CTX_PREEMPTBUFFER; - -/* - * Global buffer types. These are shared between contexts - * each PF/VF context normally. A GraphicsContext may have - * a private allocation for security (VPR) or when - * graphics preemption is enabled. - * - * Not all buffer types are supported on every GPU. - */ -#define GR_GLOBALCTX_BUFFER_DEF(x) \ - NV_ENUM_ENTRY(x, GR_GLOBALCTX_BUFFER_BUNDLE_CB, 0x00000000) \ - NV_ENUM_ENTRY(x, GR_GLOBALCTX_BUFFER_PAGEPOOL, 0x00000001) \ - NV_ENUM_ENTRY(x, GR_GLOBALCTX_BUFFER_ATTRIBUTE_CB, 0x00000002) \ - NV_ENUM_ENTRY(x, GR_GLOBALCTX_BUFFER_RTV_CB, 0x00000003) \ - NV_ENUM_ENTRY(x, GR_GLOBALCTX_BUFFER_GFXP_POOL, 0x00000004) \ - NV_ENUM_ENTRY(x, GR_GLOBALCTX_BUFFER_GFXP_CTRL_BLK, 0x00000005) \ - NV_ENUM_ENTRY(x, GR_GLOBALCTX_BUFFER_FECS_EVENT, 0x00000006) \ - NV_ENUM_ENTRY(x, GR_GLOBALCTX_BUFFER_PRIV_ACCESS_MAP, 0x00000007) \ - NV_ENUM_ENTRY(x, GR_GLOBALCTX_BUFFER_UNRESTRICTED_PRIV_ACCESS_MAP, 0x00000008) \ - NV_ENUM_ENTRY(x, GR_GLOBAL_BUFFER_GLOBAL_PRIV_ACCESS_MAP, 0x00000009) - -NV_ENUM_DEF(GR_GLOBALCTX_BUFFER, GR_GLOBALCTX_BUFFER_DEF) -#define GR_GLOBALCTX_BUFFER_COUNT NV_ENUM_SIZE(GR_GLOBALCTX_BUFFER) - - -#define GR_CTX_BUFFER_DEF(x) \ - NV_ENUM_ENTRY(x, GR_CTX_BUFFER_MAIN, 0x00000000) \ - NV_ENUM_ENTRY(x, GR_CTX_BUFFER_ZCULL, 0x00000001) \ - NV_ENUM_ENTRY(x, GR_CTX_BUFFER_PM, 0x00000002) \ - NV_ENUM_ENTRY(x, GR_CTX_BUFFER_PREEMPT, 0x00000003) \ - NV_ENUM_ENTRY(x, GR_CTX_BUFFER_SPILL, 0x00000004) \ - NV_ENUM_ENTRY(x, GR_CTX_BUFFER_BETA_CB, 0x00000005) \ - NV_ENUM_ENTRY(x, GR_CTX_BUFFER_PAGEPOOL, 0x00000006) \ - NV_ENUM_ENTRY(x, GR_CTX_BUFFER_RTV_CB, 0x00000007) \ - NV_ENUM_ENTRY(x, GR_CTX_BUFFER_PATCH, 0x00000008) - -NV_ENUM_DEF(GR_CTX_BUFFER, GR_CTX_BUFFER_DEF) - typedef struct { MEMORY_DESCRIPTOR *memDesc[GR_GLOBALCTX_BUFFER_COUNT]; NvBool bAllocated; - NvBool bFecsBufferAllocated; // FIXME merge this with bAllocated // Tracks whether Physical has initialized the memory descriptor for the promoted Kernel buffer NvBool bInitialized[GR_GLOBALCTX_BUFFER_COUNT]; @@ -240,6 +184,7 @@ struct KernelGraphicsContext { NV_STATUS (*__kgrctxInternalControlForward__)(struct KernelGraphicsContext *, NvU32, void *, NvU32); void (*__kgrctxPreDestruct__)(struct KernelGraphicsContext *); NV_STATUS (*__kgrctxUnmapFrom__)(struct KernelGraphicsContext *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__kgrctxIsDuplicate__)(struct KernelGraphicsContext *, NvHandle, NvBool *); void (*__kgrctxControl_Epilogue__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kgrctxControlLookup__)(struct KernelGraphicsContext *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__kgrctxMap__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -297,12 +242,14 @@ NV_STATUS __nvoc_objCreate_KernelGraphicsContext(KernelGraphicsContext**, Dynami #define kgrctxInternalControlForward(pGpuResource, command, pParams, size) kgrctxInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define kgrctxPreDestruct(pResource) kgrctxPreDestruct_DISPATCH(pResource) #define kgrctxUnmapFrom(pResource, pParams) kgrctxUnmapFrom_DISPATCH(pResource, pParams) +#define kgrctxIsDuplicate(pResource, hMemory, pDuplicate) kgrctxIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define kgrctxControl_Epilogue(pResource, pCallContext, pParams) kgrctxControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define kgrctxControlLookup(pResource, pParams, ppEntry) kgrctxControlLookup_DISPATCH(pResource, pParams, ppEntry) #define kgrctxMap(pGpuResource, pCallContext, pParams, pCpuMapping) kgrctxMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define kgrctxAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) kgrctxAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool kgrctxShouldManageCtxBuffers_KERNEL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, NvU32 gfid); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline NvBool kgrctxShouldManageCtxBuffers(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -314,21 +261,9 @@ static inline NvBool kgrctxShouldManageCtxBuffers(struct OBJGPU *arg0, struct Ke #define kgrctxShouldManageCtxBuffers_HAL(arg0, arg1, gfid) kgrctxShouldManageCtxBuffers(arg0, arg1, gfid) -NV_STATUS kgrctxReleaseSubctxResources_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, struct OBJVASPACE *arg3, NvU32 veid); - -#ifdef __nvoc_kernel_graphics_context_h_disabled -static inline NV_STATUS kgrctxReleaseSubctxResources(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, struct OBJVASPACE *arg3, NvU32 veid) { - NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_graphics_context_h_disabled -#define kgrctxReleaseSubctxResources(arg0, arg1, arg2, arg3, veid) kgrctxReleaseSubctxResources_IMPL(arg0, arg1, arg2, arg3, veid) -#endif //__nvoc_kernel_graphics_context_h_disabled - -#define kgrctxReleaseSubctxResources_HAL(arg0, arg1, arg2, arg3, veid) kgrctxReleaseSubctxResources(arg0, arg1, arg2, arg3, veid) - NvBool kgrctxShouldCleanup_KERNEL(struct OBJGPU *pGpu, struct KernelGraphicsContext *pKernelGraphicsContext); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline NvBool kgrctxShouldCleanup(struct OBJGPU *pGpu, struct KernelGraphicsContext *pKernelGraphicsContext) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -342,6 +277,7 @@ static inline NvBool kgrctxShouldCleanup(struct OBJGPU *pGpu, struct KernelGraph NvBool kgrctxShouldPreAllocPmBuffer_PF(struct OBJGPU *pGpu, struct KernelGraphicsContext *pKernelGraphicsContext, struct KernelChannel *pKernelChannel); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline NvBool kgrctxShouldPreAllocPmBuffer(struct OBJGPU *pGpu, struct KernelGraphicsContext *pKernelGraphicsContext, struct KernelChannel *pKernelChannel) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -355,6 +291,7 @@ static inline NvBool kgrctxShouldPreAllocPmBuffer(struct OBJGPU *pGpu, struct Ke void kgrctxUnmapBuffers_KERNEL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, KernelGraphicsContextUnicast *arg2, struct KernelChannel *arg3); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline void kgrctxUnmapBuffers(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, KernelGraphicsContextUnicast *arg2, struct KernelChannel *arg3) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -367,6 +304,7 @@ static inline void kgrctxUnmapBuffers(struct OBJGPU *arg0, struct KernelGraphics NV_STATUS kgrctxUnmapCtxBuffers_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphicsObject *arg2, struct KernelGraphics *arg3, NvBool bDestructor); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline NV_STATUS kgrctxUnmapCtxBuffers(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphicsObject *arg2, struct KernelGraphics *arg3, NvBool bDestructor) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -380,6 +318,7 @@ static inline NV_STATUS kgrctxUnmapCtxBuffers(struct OBJGPU *arg0, struct Kernel void kgrctxIncObjectCount_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, NvU32 classNum); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline void kgrctxIncObjectCount(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, NvU32 classNum) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -392,6 +331,7 @@ static inline void kgrctxIncObjectCount(struct OBJGPU *arg0, struct KernelGraphi void kgrctxDecObjectCount_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, NvU32 classNum); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline void kgrctxDecObjectCount(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, NvU32 classNum) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -404,6 +344,7 @@ static inline void kgrctxDecObjectCount(struct OBJGPU *arg0, struct KernelGraphi GR_GLOBALCTX_BUFFER kgrctxGetRegisterAccessMapId_PF(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelChannel *arg2); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline GR_GLOBALCTX_BUFFER kgrctxGetRegisterAccessMapId(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelChannel *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -519,6 +460,10 @@ static inline NV_STATUS kgrctxUnmapFrom_DISPATCH(struct KernelGraphicsContext *p return pResource->__kgrctxUnmapFrom__(pResource, pParams); } +static inline NV_STATUS kgrctxIsDuplicate_DISPATCH(struct KernelGraphicsContext *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__kgrctxIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void kgrctxControl_Epilogue_DISPATCH(struct KernelGraphicsContext *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__kgrctxControl_Epilogue__(pResource, pCallContext, pParams); } @@ -536,26 +481,37 @@ static inline NvBool kgrctxAccessCallback_DISPATCH(struct KernelGraphicsContext } NV_STATUS kgrctxFromKernelChannel_IMPL(struct KernelChannel *arg0, struct KernelGraphicsContext **arg1); + #define kgrctxFromKernelChannel(arg0, arg1) kgrctxFromKernelChannel_IMPL(arg0, arg1) NV_STATUS kgrctxFromKernelChannelGroupApi_IMPL(struct KernelChannelGroupApi *arg0, struct KernelGraphicsContext **arg1); + #define kgrctxFromKernelChannelGroupApi(arg0, arg1) kgrctxFromKernelChannelGroupApi_IMPL(arg0, arg1) NV_STATUS kgrctxGetGlobalContextBufferExternalId_IMPL(GR_GLOBALCTX_BUFFER arg0, NvU32 *pExternalId); + #define kgrctxGetGlobalContextBufferExternalId(arg0, pExternalId) kgrctxGetGlobalContextBufferExternalId_IMPL(arg0, pExternalId) NV_STATUS kgrctxGetGlobalContextBufferInternalId_IMPL(NvU32 externalId, GR_GLOBALCTX_BUFFER *arg0); + #define kgrctxGetGlobalContextBufferInternalId(externalId, arg0) kgrctxGetGlobalContextBufferInternalId_IMPL(externalId, arg0) NV_STATUS kgrctxCtxBufferToFifoEngineId_IMPL(GR_CTX_BUFFER arg0, NvU32 *pFifoEngineId); + #define kgrctxCtxBufferToFifoEngineId(arg0, pFifoEngineId) kgrctxCtxBufferToFifoEngineId_IMPL(arg0, pFifoEngineId) NV_STATUS kgrctxGlobalCtxBufferToFifoEngineId_IMPL(GR_GLOBALCTX_BUFFER arg0, NvU32 *pFifoEngineId); + #define kgrctxGlobalCtxBufferToFifoEngineId(arg0, pFifoEngineId) kgrctxGlobalCtxBufferToFifoEngineId_IMPL(arg0, pFifoEngineId) NV_STATUS kgrctxGetGidInfoInPlace_IMPL(struct OBJGPU *pGpu, NvU8 *pUuidBuffer, NvU32 uuidBufferSize, NvU32 flags); + #define kgrctxGetGidInfoInPlace(pGpu, pUuidBuffer, uuidBufferSize, flags) kgrctxGetGidInfoInPlace_IMPL(pGpu, pUuidBuffer, uuidBufferSize, flags) GMMU_APERTURE kgrctxGetExternalAllocAperture_IMPL(NvU32 addressSpace); + #define kgrctxGetExternalAllocAperture(addressSpace) kgrctxGetExternalAllocAperture_IMPL(addressSpace) NV_STATUS kgrctxFillCtxBufferInfo_IMPL(struct MEMORY_DESCRIPTOR *arg0, NvU32 externalId, NvBool bBufferGlobal, NV2080_CTRL_GR_CTX_BUFFER_INFO *arg1); + #define kgrctxFillCtxBufferInfo(arg0, externalId, bBufferGlobal, arg1) kgrctxFillCtxBufferInfo_IMPL(arg0, externalId, bBufferGlobal, arg1) NV_STATUS kgrctxConstruct_IMPL(struct KernelGraphicsContext *arg_pKernelGraphicsContext, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_kgrctxConstruct(arg_pKernelGraphicsContext, arg_pCallContext, arg_pParams) kgrctxConstruct_IMPL(arg_pKernelGraphicsContext, arg_pCallContext, arg_pParams) NV_STATUS kgrctxCopyConstruct_IMPL(struct KernelGraphicsContext *arg0, struct CALL_CONTEXT *arg1, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg2); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline NV_STATUS kgrctxCopyConstruct(struct KernelGraphicsContext *arg0, struct CALL_CONTEXT *arg1, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -566,8 +522,10 @@ static inline NV_STATUS kgrctxCopyConstruct(struct KernelGraphicsContext *arg0, #endif //__nvoc_kernel_graphics_context_h_disabled void kgrctxDestruct_IMPL(struct KernelGraphicsContext *arg0); + #define __nvoc_kgrctxDestruct(arg0) kgrctxDestruct_IMPL(arg0) NV_STATUS kgrctxGetUnicast_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, KernelGraphicsContextUnicast **arg2); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline NV_STATUS kgrctxGetUnicast(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, KernelGraphicsContextUnicast **arg2) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -577,7 +535,19 @@ static inline NV_STATUS kgrctxGetUnicast(struct OBJGPU *arg0, struct KernelGraph #define kgrctxGetUnicast(arg0, arg1, arg2) kgrctxGetUnicast_IMPL(arg0, arg1, arg2) #endif //__nvoc_kernel_graphics_context_h_disabled +NV_STATUS kgrctxLookupMmuFaultInfo_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS *arg2); + +#ifdef __nvoc_kernel_graphics_context_h_disabled +static inline NV_STATUS kgrctxLookupMmuFaultInfo(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS *arg2) { + NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_graphics_context_h_disabled +#define kgrctxLookupMmuFaultInfo(arg0, arg1, arg2) kgrctxLookupMmuFaultInfo_IMPL(arg0, arg1, arg2) +#endif //__nvoc_kernel_graphics_context_h_disabled + NV_STATUS kgrctxLookupMmuFault_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, NV83DE_MMU_FAULT_INFO *arg2); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline NV_STATUS kgrctxLookupMmuFault(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, NV83DE_MMU_FAULT_INFO *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -588,6 +558,7 @@ static inline NV_STATUS kgrctxLookupMmuFault(struct OBJGPU *arg0, struct KernelG #endif //__nvoc_kernel_graphics_context_h_disabled NV_STATUS kgrctxClearMmuFault_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline NV_STATUS kgrctxClearMmuFault(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -597,16 +568,18 @@ static inline NV_STATUS kgrctxClearMmuFault(struct OBJGPU *arg0, struct KernelGr #define kgrctxClearMmuFault(arg0, arg1) kgrctxClearMmuFault_IMPL(arg0, arg1) #endif //__nvoc_kernel_graphics_context_h_disabled -void kgrctxRecordMmuFault_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, NvU32 mmuFaultInfo); +void kgrctxRecordMmuFault_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, NvU32 mmuFaultInfo, NvU64 mmuFaultAddress, NvU32 mmuFaultType, NvU32 mmuFaultAccessType); + #ifdef __nvoc_kernel_graphics_context_h_disabled -static inline void kgrctxRecordMmuFault(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, NvU32 mmuFaultInfo) { +static inline void kgrctxRecordMmuFault(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, NvU32 mmuFaultInfo, NvU64 mmuFaultAddress, NvU32 mmuFaultType, NvU32 mmuFaultAccessType) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); } #else //__nvoc_kernel_graphics_context_h_disabled -#define kgrctxRecordMmuFault(arg0, arg1, mmuFaultInfo) kgrctxRecordMmuFault_IMPL(arg0, arg1, mmuFaultInfo) +#define kgrctxRecordMmuFault(arg0, arg1, mmuFaultInfo, mmuFaultAddress, mmuFaultType, mmuFaultAccessType) kgrctxRecordMmuFault_IMPL(arg0, arg1, mmuFaultInfo, mmuFaultAddress, mmuFaultType, mmuFaultAccessType) #endif //__nvoc_kernel_graphics_context_h_disabled NvBool kgrctxIsMainContextAllocated_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline NvBool kgrctxIsMainContextAllocated(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -617,6 +590,7 @@ static inline NvBool kgrctxIsMainContextAllocated(struct OBJGPU *arg0, struct Ke #endif //__nvoc_kernel_graphics_context_h_disabled NV_STATUS kgrctxGetMainContextBuffer_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct MEMORY_DESCRIPTOR **arg2); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline NV_STATUS kgrctxGetMainContextBuffer(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct MEMORY_DESCRIPTOR **arg2) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -627,6 +601,7 @@ static inline NV_STATUS kgrctxGetMainContextBuffer(struct OBJGPU *arg0, struct K #endif //__nvoc_kernel_graphics_context_h_disabled NV_STATUS kgrctxGetBufferCount_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, NvU32 *pBufferCount); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline NV_STATUS kgrctxGetBufferCount(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, NvU32 *pBufferCount) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -637,6 +612,7 @@ static inline NV_STATUS kgrctxGetBufferCount(struct OBJGPU *arg0, struct KernelG #endif //__nvoc_kernel_graphics_context_h_disabled NV_STATUS kgrctxGetCtxBuffers_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, NvU32 gfid, NvU32 bufferCount, struct MEMORY_DESCRIPTOR **arg3, NvU32 *pCtxBufferType, NvU32 *pBufferCountOut, NvU32 *pFirstGlobalBuffer); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline NV_STATUS kgrctxGetCtxBuffers(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, NvU32 gfid, NvU32 bufferCount, struct MEMORY_DESCRIPTOR **arg3, NvU32 *pCtxBufferType, NvU32 *pBufferCountOut, NvU32 *pFirstGlobalBuffer) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -647,6 +623,7 @@ static inline NV_STATUS kgrctxGetCtxBuffers(struct OBJGPU *arg0, struct KernelGr #endif //__nvoc_kernel_graphics_context_h_disabled NV_STATUS kgrctxGetCtxBufferInfo_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, NvU32 gfid, NvU32 bufferMaxCount, NvU32 *pBufferCount, NV2080_CTRL_GR_CTX_BUFFER_INFO *arg3); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline NV_STATUS kgrctxGetCtxBufferInfo(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, NvU32 gfid, NvU32 bufferMaxCount, NvU32 *pBufferCount, NV2080_CTRL_GR_CTX_BUFFER_INFO *arg3) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -657,6 +634,7 @@ static inline NV_STATUS kgrctxGetCtxBufferInfo(struct OBJGPU *arg0, struct Kerne #endif //__nvoc_kernel_graphics_context_h_disabled NV_STATUS kgrctxGetCtxBufferPtes_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, NvU32 gfid, NvU32 bufferType, NvU32 firstPage, NvU64 *pPhysAddrs, NvU32 addrsSize, NvU32 *pNumPages, NvBool *pbNoMorePages); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline NV_STATUS kgrctxGetCtxBufferPtes(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, NvU32 gfid, NvU32 bufferType, NvU32 firstPage, NvU64 *pPhysAddrs, NvU32 addrsSize, NvU32 *pNumPages, NvBool *pbNoMorePages) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -667,6 +645,7 @@ static inline NV_STATUS kgrctxGetCtxBufferPtes(struct OBJGPU *arg0, struct Kerne #endif //__nvoc_kernel_graphics_context_h_disabled NV_STATUS kgrctxAllocMainCtxBuffer_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, struct KernelChannel *arg3); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline NV_STATUS kgrctxAllocMainCtxBuffer(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, struct KernelChannel *arg3) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -677,6 +656,7 @@ static inline NV_STATUS kgrctxAllocMainCtxBuffer(struct OBJGPU *arg0, struct Ker #endif //__nvoc_kernel_graphics_context_h_disabled NV_STATUS kgrctxAllocPatchBuffer_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, struct KernelChannel *arg3); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline NV_STATUS kgrctxAllocPatchBuffer(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, struct KernelChannel *arg3) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -687,6 +667,7 @@ static inline NV_STATUS kgrctxAllocPatchBuffer(struct OBJGPU *arg0, struct Kerne #endif //__nvoc_kernel_graphics_context_h_disabled NV_STATUS kgrctxAllocPmBuffer_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, struct KernelChannel *arg3); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline NV_STATUS kgrctxAllocPmBuffer(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, struct KernelChannel *arg3) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -697,6 +678,7 @@ static inline NV_STATUS kgrctxAllocPmBuffer(struct OBJGPU *arg0, struct KernelGr #endif //__nvoc_kernel_graphics_context_h_disabled NV_STATUS kgrctxAllocCtxBuffers_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, struct KernelGraphicsObject *arg3); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline NV_STATUS kgrctxAllocCtxBuffers(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, struct KernelGraphicsObject *arg3) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -707,6 +689,7 @@ static inline NV_STATUS kgrctxAllocCtxBuffers(struct OBJGPU *arg0, struct Kernel #endif //__nvoc_kernel_graphics_context_h_disabled NV_STATUS kgrctxMapGlobalCtxBuffer_IMPL(struct OBJGPU *pGpu, struct KernelGraphicsContext *arg0, struct KernelGraphics *arg1, NvU32 gfid, struct OBJVASPACE *arg2, GR_GLOBALCTX_BUFFER arg3, NvBool bIsReadOnly); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline NV_STATUS kgrctxMapGlobalCtxBuffer(struct OBJGPU *pGpu, struct KernelGraphicsContext *arg0, struct KernelGraphics *arg1, NvU32 gfid, struct OBJVASPACE *arg2, GR_GLOBALCTX_BUFFER arg3, NvBool bIsReadOnly) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -717,6 +700,7 @@ static inline NV_STATUS kgrctxMapGlobalCtxBuffer(struct OBJGPU *pGpu, struct Ker #endif //__nvoc_kernel_graphics_context_h_disabled NV_STATUS kgrctxMapGlobalCtxBuffers_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, NvU32 gfid, struct KernelChannel *arg3); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline NV_STATUS kgrctxMapGlobalCtxBuffers(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, NvU32 gfid, struct KernelChannel *arg3) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -727,6 +711,7 @@ static inline NV_STATUS kgrctxMapGlobalCtxBuffers(struct OBJGPU *arg0, struct Ke #endif //__nvoc_kernel_graphics_context_h_disabled NV_STATUS kgrctxMapCtxBuffers_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, struct KernelGraphicsObject *arg3); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline NV_STATUS kgrctxMapCtxBuffers(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, struct KernelGraphicsObject *arg3) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -737,6 +722,7 @@ static inline NV_STATUS kgrctxMapCtxBuffers(struct OBJGPU *arg0, struct KernelGr #endif //__nvoc_kernel_graphics_context_h_disabled NV_STATUS kgrctxPrepareInitializeCtxBuffer_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, struct KernelChannel *arg3, NvU32 externalId, NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY *arg4, NvBool *pbAddEntry); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline NV_STATUS kgrctxPrepareInitializeCtxBuffer(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, struct KernelChannel *arg3, NvU32 externalId, NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY *arg4, NvBool *pbAddEntry) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -747,6 +733,7 @@ static inline NV_STATUS kgrctxPrepareInitializeCtxBuffer(struct OBJGPU *arg0, st #endif //__nvoc_kernel_graphics_context_h_disabled NV_STATUS kgrctxPreparePromoteCtxBuffer_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelChannel *arg2, NvU32 externalId, NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY *arg3, NvBool *pbAddEntry); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline NV_STATUS kgrctxPreparePromoteCtxBuffer(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelChannel *arg2, NvU32 externalId, NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY *arg3, NvBool *pbAddEntry) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -757,6 +744,7 @@ static inline NV_STATUS kgrctxPreparePromoteCtxBuffer(struct OBJGPU *arg0, struc #endif //__nvoc_kernel_graphics_context_h_disabled void kgrctxMarkCtxBufferInitialized_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, struct KernelChannel *arg3, NvU32 externalId); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline void kgrctxMarkCtxBufferInitialized(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, struct KernelChannel *arg3, NvU32 externalId) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -766,6 +754,7 @@ static inline void kgrctxMarkCtxBufferInitialized(struct OBJGPU *arg0, struct Ke #endif //__nvoc_kernel_graphics_context_h_disabled NV_STATUS kgrctxSetupDeferredPmBuffer_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, struct KernelChannel *arg3); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline NV_STATUS kgrctxSetupDeferredPmBuffer(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, struct KernelChannel *arg3) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -776,6 +765,7 @@ static inline NV_STATUS kgrctxSetupDeferredPmBuffer(struct OBJGPU *arg0, struct #endif //__nvoc_kernel_graphics_context_h_disabled void kgrctxUnmapGlobalCtxBuffers_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, struct OBJVASPACE *arg3, NvU32 gfid); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline void kgrctxUnmapGlobalCtxBuffers(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, struct OBJVASPACE *arg3, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -785,6 +775,7 @@ static inline void kgrctxUnmapGlobalCtxBuffers(struct OBJGPU *arg0, struct Kerne #endif //__nvoc_kernel_graphics_context_h_disabled void kgrctxUnmapGlobalCtxBuffer_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, struct OBJVASPACE *arg3, GR_GLOBALCTX_BUFFER arg4); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline void kgrctxUnmapGlobalCtxBuffer(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, struct OBJVASPACE *arg3, GR_GLOBALCTX_BUFFER arg4) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -794,6 +785,7 @@ static inline void kgrctxUnmapGlobalCtxBuffer(struct OBJGPU *arg0, struct Kernel #endif //__nvoc_kernel_graphics_context_h_disabled void kgrctxUnmapMainCtxBuffer_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, struct KernelChannel *arg3); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline void kgrctxUnmapMainCtxBuffer(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, struct KernelChannel *arg3) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -803,6 +795,7 @@ static inline void kgrctxUnmapMainCtxBuffer(struct OBJGPU *arg0, struct KernelGr #endif //__nvoc_kernel_graphics_context_h_disabled void kgrctxUnmapCtxPmBuffer_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, struct OBJVASPACE *arg3); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline void kgrctxUnmapCtxPmBuffer(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, struct OBJVASPACE *arg3) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -811,7 +804,28 @@ static inline void kgrctxUnmapCtxPmBuffer(struct OBJGPU *arg0, struct KernelGrap #define kgrctxUnmapCtxPmBuffer(arg0, arg1, arg2, arg3) kgrctxUnmapCtxPmBuffer_IMPL(arg0, arg1, arg2, arg3) #endif //__nvoc_kernel_graphics_context_h_disabled +void kgrctxUnmapCtxZcullBuffer_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, struct OBJVASPACE *arg3); + +#ifdef __nvoc_kernel_graphics_context_h_disabled +static inline void kgrctxUnmapCtxZcullBuffer(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, struct OBJVASPACE *arg3) { + NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); +} +#else //__nvoc_kernel_graphics_context_h_disabled +#define kgrctxUnmapCtxZcullBuffer(arg0, arg1, arg2, arg3) kgrctxUnmapCtxZcullBuffer_IMPL(arg0, arg1, arg2, arg3) +#endif //__nvoc_kernel_graphics_context_h_disabled + +void kgrctxUnmapCtxPreemptionBuffers_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, struct OBJVASPACE *arg3); + +#ifdef __nvoc_kernel_graphics_context_h_disabled +static inline void kgrctxUnmapCtxPreemptionBuffers(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, struct OBJVASPACE *arg3) { + NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); +} +#else //__nvoc_kernel_graphics_context_h_disabled +#define kgrctxUnmapCtxPreemptionBuffers(arg0, arg1, arg2, arg3) kgrctxUnmapCtxPreemptionBuffers_IMPL(arg0, arg1, arg2, arg3) +#endif //__nvoc_kernel_graphics_context_h_disabled + void kgrctxUnmapAssociatedCtxBuffers_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, struct KernelChannel *arg3); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline void kgrctxUnmapAssociatedCtxBuffers(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelGraphics *arg2, struct KernelChannel *arg3) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -821,6 +835,7 @@ static inline void kgrctxUnmapAssociatedCtxBuffers(struct OBJGPU *arg0, struct K #endif //__nvoc_kernel_graphics_context_h_disabled void kgrctxFreeMainCtxBuffer_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline void kgrctxFreeMainCtxBuffer(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -829,25 +844,28 @@ static inline void kgrctxFreeMainCtxBuffer(struct OBJGPU *arg0, struct KernelGra #define kgrctxFreeMainCtxBuffer(arg0, arg1) kgrctxFreeMainCtxBuffer_IMPL(arg0, arg1) #endif //__nvoc_kernel_graphics_context_h_disabled -void kgrctxFreeZcullBuffer_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct OBJVASPACE *arg2); +void kgrctxFreeZcullBuffer_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1); + #ifdef __nvoc_kernel_graphics_context_h_disabled -static inline void kgrctxFreeZcullBuffer(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct OBJVASPACE *arg2) { +static inline void kgrctxFreeZcullBuffer(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); } #else //__nvoc_kernel_graphics_context_h_disabled -#define kgrctxFreeZcullBuffer(arg0, arg1, arg2) kgrctxFreeZcullBuffer_IMPL(arg0, arg1, arg2) +#define kgrctxFreeZcullBuffer(arg0, arg1) kgrctxFreeZcullBuffer_IMPL(arg0, arg1) #endif //__nvoc_kernel_graphics_context_h_disabled -void kgrctxFreeCtxPreemptionBuffers_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct OBJVASPACE *arg2); +void kgrctxFreeCtxPreemptionBuffers_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1); + #ifdef __nvoc_kernel_graphics_context_h_disabled -static inline void kgrctxFreeCtxPreemptionBuffers(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct OBJVASPACE *arg2) { +static inline void kgrctxFreeCtxPreemptionBuffers(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); } #else //__nvoc_kernel_graphics_context_h_disabled -#define kgrctxFreeCtxPreemptionBuffers(arg0, arg1, arg2) kgrctxFreeCtxPreemptionBuffers_IMPL(arg0, arg1, arg2) +#define kgrctxFreeCtxPreemptionBuffers(arg0, arg1) kgrctxFreeCtxPreemptionBuffers_IMPL(arg0, arg1) #endif //__nvoc_kernel_graphics_context_h_disabled void kgrctxFreePatchBuffer_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline void kgrctxFreePatchBuffer(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -857,6 +875,7 @@ static inline void kgrctxFreePatchBuffer(struct OBJGPU *arg0, struct KernelGraph #endif //__nvoc_kernel_graphics_context_h_disabled void kgrctxFreePmBuffer_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline void kgrctxFreePmBuffer(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -866,6 +885,7 @@ static inline void kgrctxFreePmBuffer(struct OBJGPU *arg0, struct KernelGraphics #endif //__nvoc_kernel_graphics_context_h_disabled void kgrctxFreeLocalGlobalCtxBuffers_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline void kgrctxFreeLocalGlobalCtxBuffers(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -875,6 +895,7 @@ static inline void kgrctxFreeLocalGlobalCtxBuffers(struct OBJGPU *arg0, struct K #endif //__nvoc_kernel_graphics_context_h_disabled void kgrctxFreeAssociatedCtxBuffers_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline void kgrctxFreeAssociatedCtxBuffers(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); @@ -898,23 +919,28 @@ static inline void kgrctxFreeAssociatedCtxBuffers(struct OBJGPU *arg0, struct Ke struct KernelGraphicsContextUnicast { NvU32 channelObjects; NvU32 objectCounts[4]; - GR_CTX_PATCHBUFFER ctxPatchBuffer; - GR_CTX_ZCULLBUFFER zcullCtxswBuffer; - GR_CTX_PMBUFFER pmCtxswBuffer; + NV_CONTEXT_BUFFER ctxPatchBuffer; + NV_CONTEXT_BUFFER zcullCtxswBuffer; + NV_CONTEXT_BUFFER pmCtxswBuffer; struct MEMORY_DESCRIPTOR *pMainCtxBuffer; GR_GLOBALCTX_BUFFERS localCtxBuffer; VA_LIST globalCtxBufferVaList[10]; NvBool bKGrMainCtxBufferInitialized; NvBool bKGrPatchCtxBufferInitialized; NvBool bKGrPmCtxBufferInitialized; - GR_CTX_PREEMPTBUFFER preemptCtxswBuffer; - GR_CTX_PREEMPTBUFFER spillCtxswBuffer; - GR_CTX_PREEMPTBUFFER betaCBCtxswBuffer; - GR_CTX_PREEMPTBUFFER pagepoolCtxswBuffer; - GR_CTX_PREEMPTBUFFER rtvCbCtxswBuffer; + NV_CONTEXT_BUFFER preemptCtxswBuffer; + NV_CONTEXT_BUFFER spillCtxswBuffer; + NV_CONTEXT_BUFFER betaCBCtxswBuffer; + NV_CONTEXT_BUFFER pagepoolCtxswBuffer; + NV_CONTEXT_BUFFER rtvCbCtxswBuffer; NvBool bVprChannel; NvBool bSupportsPerSubctxHeader; - NV83DE_MMU_FAULT_INFO mmuFaultInfo; + struct MMU_FAULT_INFO { + NV83DE_MMU_FAULT_INFO mmuFaultInfo; + NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_ENTRY mmuFaultInfoList[4]; + NvU32 head; + NvU32 tail; + } mmuFault; }; @@ -956,8 +982,10 @@ NV_STATUS __nvoc_objCreate_KernelGraphicsContextShared(KernelGraphicsContextShar __nvoc_objCreate_KernelGraphicsContextShared((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) NV_STATUS shrkgrctxConstruct_IMPL(struct KernelGraphicsContextShared *arg_); + #define __nvoc_shrkgrctxConstruct(arg_) shrkgrctxConstruct_IMPL(arg_) NV_STATUS shrkgrctxInit_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContextShared *arg1, struct KernelGraphicsContext *arg2); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline NV_STATUS shrkgrctxInit(struct OBJGPU *arg0, struct KernelGraphicsContextShared *arg1, struct KernelGraphicsContext *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContextShared was disabled!"); @@ -968,6 +996,7 @@ static inline NV_STATUS shrkgrctxInit(struct OBJGPU *arg0, struct KernelGraphics #endif //__nvoc_kernel_graphics_context_h_disabled NV_STATUS shrkgrctxConstructUnicast_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContextShared *arg1, struct KernelGraphicsContext *arg2, struct KernelGraphics *arg3, KernelGraphicsContextUnicast *arg4); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline NV_STATUS shrkgrctxConstructUnicast(struct OBJGPU *arg0, struct KernelGraphicsContextShared *arg1, struct KernelGraphicsContext *arg2, struct KernelGraphics *arg3, KernelGraphicsContextUnicast *arg4) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContextShared was disabled!"); @@ -978,8 +1007,10 @@ static inline NV_STATUS shrkgrctxConstructUnicast(struct OBJGPU *arg0, struct Ke #endif //__nvoc_kernel_graphics_context_h_disabled void shrkgrctxDestruct_IMPL(struct KernelGraphicsContextShared *arg0); + #define __nvoc_shrkgrctxDestruct(arg0) shrkgrctxDestruct_IMPL(arg0) void shrkgrctxTeardown_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContextShared *arg1, struct KernelGraphicsContext *arg2); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline void shrkgrctxTeardown(struct OBJGPU *arg0, struct KernelGraphicsContextShared *arg1, struct KernelGraphicsContext *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContextShared was disabled!"); @@ -989,6 +1020,7 @@ static inline void shrkgrctxTeardown(struct OBJGPU *arg0, struct KernelGraphicsC #endif //__nvoc_kernel_graphics_context_h_disabled void shrkgrctxDestructUnicast_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContextShared *arg1, struct KernelGraphicsContext *arg2, KernelGraphicsContextUnicast *arg3); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline void shrkgrctxDestructUnicast(struct OBJGPU *arg0, struct KernelGraphicsContextShared *arg1, struct KernelGraphicsContext *arg2, KernelGraphicsContextUnicast *arg3) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContextShared was disabled!"); @@ -998,6 +1030,7 @@ static inline void shrkgrctxDestructUnicast(struct OBJGPU *arg0, struct KernelGr #endif //__nvoc_kernel_graphics_context_h_disabled void shrkgrctxDetach_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContextShared *arg1, struct KernelGraphicsContext *arg2, struct KernelChannel *arg3); + #ifdef __nvoc_kernel_graphics_context_h_disabled static inline void shrkgrctxDetach(struct OBJGPU *arg0, struct KernelGraphicsContextShared *arg1, struct KernelGraphicsContext *arg2, struct KernelChannel *arg3) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContextShared was disabled!"); diff --git a/src/nvidia/generated/g_kernel_graphics_manager_nvoc.h b/src/nvidia/generated/g_kernel_graphics_manager_nvoc.h index d8ecabb45..0f1405471 100644 --- a/src/nvidia/generated/g_kernel_graphics_manager_nvoc.h +++ b/src/nvidia/generated/g_kernel_graphics_manager_nvoc.h @@ -229,18 +229,25 @@ static inline NvBool kgrmgrIsPresent_DISPATCH(POBJGPU pGpu, struct KernelGraphic } void kgrmgrGetGrObjectType_IMPL(NvU32 classNum, NvU32 *pObjectType); + #define kgrmgrGetGrObjectType(classNum, pObjectType) kgrmgrGetGrObjectType_IMPL(classNum, pObjectType) NvBool kgrmgrIsCtxBufSupported_IMPL(GR_CTX_BUFFER arg0, NvBool bClassSupported2D); + #define kgrmgrIsCtxBufSupported(arg0, bClassSupported2D) kgrmgrIsCtxBufSupported_IMPL(arg0, bClassSupported2D) NvBool kgrmgrIsGlobalCtxBufSupported_IMPL(GR_GLOBALCTX_BUFFER arg0, NvBool bClassSupported2D); + #define kgrmgrIsGlobalCtxBufSupported(arg0, bClassSupported2D) kgrmgrIsGlobalCtxBufSupported_IMPL(arg0, bClassSupported2D) void kgrmgrCtrlSetEngineID_IMPL(NvU32 engID, NV2080_CTRL_GR_ROUTE_INFO *arg0); + #define kgrmgrCtrlSetEngineID(engID, arg0) kgrmgrCtrlSetEngineID_IMPL(engID, arg0) void kgrmgrCtrlSetChannelHandle_IMPL(NvHandle hChannel, NV2080_CTRL_GR_ROUTE_INFO *arg0); + #define kgrmgrCtrlSetChannelHandle(hChannel, arg0) kgrmgrCtrlSetChannelHandle_IMPL(hChannel, arg0) void kgrmgrDestruct_IMPL(struct KernelGraphicsManager *arg0); + #define __nvoc_kgrmgrDestruct(arg0) kgrmgrDestruct_IMPL(arg0) void kgrmgrSetLegacyKgraphicsStaticInfo_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, struct KernelGraphics *arg2); + #ifdef __nvoc_kernel_graphics_manager_h_disabled static inline void kgrmgrSetLegacyKgraphicsStaticInfo(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, struct KernelGraphics *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); @@ -250,6 +257,7 @@ static inline void kgrmgrSetLegacyKgraphicsStaticInfo(struct OBJGPU *arg0, struc #endif //__nvoc_kernel_graphics_manager_h_disabled NV_STATUS kgrmgrCtrlRouteKGR_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvHandle hClient, const NV2080_CTRL_GR_ROUTE_INFO *pGrRouteInfo, struct KernelGraphics **ppKernelGraphics); + #ifdef __nvoc_kernel_graphics_manager_h_disabled static inline NV_STATUS kgrmgrCtrlRouteKGR(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvHandle hClient, const NV2080_CTRL_GR_ROUTE_INFO *pGrRouteInfo, struct KernelGraphics **ppKernelGraphics) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); @@ -260,6 +268,7 @@ static inline NV_STATUS kgrmgrCtrlRouteKGR(struct OBJGPU *arg0, struct KernelGra #endif //__nvoc_kernel_graphics_manager_h_disabled NvU32 kgrmgrGetLegacyGpcMask_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1); + #ifdef __nvoc_kernel_graphics_manager_h_disabled static inline NvU32 kgrmgrGetLegacyGpcMask(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); @@ -270,6 +279,7 @@ static inline NvU32 kgrmgrGetLegacyGpcMask(struct OBJGPU *arg0, struct KernelGra #endif //__nvoc_kernel_graphics_manager_h_disabled NvU32 kgrmgrGetLegacyTpcMask_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 gpcId); + #ifdef __nvoc_kernel_graphics_manager_h_disabled static inline NvU32 kgrmgrGetLegacyTpcMask(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 gpcId) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); @@ -280,6 +290,7 @@ static inline NvU32 kgrmgrGetLegacyTpcMask(struct OBJGPU *arg0, struct KernelGra #endif //__nvoc_kernel_graphics_manager_h_disabled NV_STATUS kgrmgrGetLegacyPpcMask_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 physGpcId, NvU32 *pPpcMask); + #ifdef __nvoc_kernel_graphics_manager_h_disabled static inline NV_STATUS kgrmgrGetLegacyPpcMask(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 physGpcId, NvU32 *pPpcMask) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); @@ -290,6 +301,7 @@ static inline NV_STATUS kgrmgrGetLegacyPpcMask(struct OBJGPU *arg0, struct Kerne #endif //__nvoc_kernel_graphics_manager_h_disabled NvU32 kgrmgrGetLegacyZcullMask_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 physGpcId); + #ifdef __nvoc_kernel_graphics_manager_h_disabled static inline NvU32 kgrmgrGetLegacyZcullMask(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 physGpcId) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); @@ -299,17 +311,19 @@ static inline NvU32 kgrmgrGetLegacyZcullMask(struct OBJGPU *arg0, struct KernelG #define kgrmgrGetLegacyZcullMask(arg0, arg1, physGpcId) kgrmgrGetLegacyZcullMask_IMPL(arg0, arg1, physGpcId) #endif //__nvoc_kernel_graphics_manager_h_disabled -NV_STATUS kgrmgrAllocVeidsForGrIdx_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 grIdx, NvU32 gpcCount, KERNEL_MIG_GPU_INSTANCE *arg2); +NV_STATUS kgrmgrAllocVeidsForGrIdx_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 grIdx, NvU32 veidSpanOffset, NvU32 veidCount, KERNEL_MIG_GPU_INSTANCE *arg2); + #ifdef __nvoc_kernel_graphics_manager_h_disabled -static inline NV_STATUS kgrmgrAllocVeidsForGrIdx(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 grIdx, NvU32 gpcCount, KERNEL_MIG_GPU_INSTANCE *arg2) { +static inline NV_STATUS kgrmgrAllocVeidsForGrIdx(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 grIdx, NvU32 veidSpanOffset, NvU32 veidCount, KERNEL_MIG_GPU_INSTANCE *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_graphics_manager_h_disabled -#define kgrmgrAllocVeidsForGrIdx(arg0, arg1, grIdx, gpcCount, arg2) kgrmgrAllocVeidsForGrIdx_IMPL(arg0, arg1, grIdx, gpcCount, arg2) +#define kgrmgrAllocVeidsForGrIdx(arg0, arg1, grIdx, veidSpanOffset, veidCount, arg2) kgrmgrAllocVeidsForGrIdx_IMPL(arg0, arg1, grIdx, veidSpanOffset, veidCount, arg2) #endif //__nvoc_kernel_graphics_manager_h_disabled void kgrmgrClearVeidsForGrIdx_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 grIdx); + #ifdef __nvoc_kernel_graphics_manager_h_disabled static inline void kgrmgrClearVeidsForGrIdx(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 grIdx) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); @@ -319,6 +333,7 @@ static inline void kgrmgrClearVeidsForGrIdx(struct OBJGPU *arg0, struct KernelGr #endif //__nvoc_kernel_graphics_manager_h_disabled NV_STATUS kgrmgrGetMaxVeidsPerGpc_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 *pMaxVeidsPerGpc); + #ifdef __nvoc_kernel_graphics_manager_h_disabled static inline NV_STATUS kgrmgrGetMaxVeidsPerGpc(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 *pMaxVeidsPerGpc) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); @@ -329,6 +344,7 @@ static inline NV_STATUS kgrmgrGetMaxVeidsPerGpc(struct OBJGPU *arg0, struct Kern #endif //__nvoc_kernel_graphics_manager_h_disabled NV_STATUS kgrmgrGetVeidBaseForGrIdx_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 grIdx, NvU32 *pVeidStart); + #ifdef __nvoc_kernel_graphics_manager_h_disabled static inline NV_STATUS kgrmgrGetVeidBaseForGrIdx(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 grIdx, NvU32 *pVeidStart) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); @@ -339,6 +355,7 @@ static inline NV_STATUS kgrmgrGetVeidBaseForGrIdx(struct OBJGPU *arg0, struct Ke #endif //__nvoc_kernel_graphics_manager_h_disabled NV_STATUS kgrmgrGetGrIdxForVeid_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 veid, NvU32 *pGrIdx); + #ifdef __nvoc_kernel_graphics_manager_h_disabled static inline NV_STATUS kgrmgrGetGrIdxForVeid(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 veid, NvU32 *pGrIdx) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); @@ -349,6 +366,7 @@ static inline NV_STATUS kgrmgrGetGrIdxForVeid(struct OBJGPU *arg0, struct Kernel #endif //__nvoc_kernel_graphics_manager_h_disabled NV_STATUS kgrmgrDiscoverMaxLocalCtxBufInfo_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, struct KernelGraphics *arg2, NvU32 swizzId); + #ifdef __nvoc_kernel_graphics_manager_h_disabled static inline NV_STATUS kgrmgrDiscoverMaxLocalCtxBufInfo(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, struct KernelGraphics *arg2, NvU32 swizzId) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); @@ -359,6 +377,7 @@ static inline NV_STATUS kgrmgrDiscoverMaxLocalCtxBufInfo(struct OBJGPU *arg0, st #endif //__nvoc_kernel_graphics_manager_h_disabled const CTX_BUF_INFO *kgrmgrGetGlobalCtxBufInfo_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, GR_GLOBALCTX_BUFFER arg2); + #ifdef __nvoc_kernel_graphics_manager_h_disabled static inline const CTX_BUF_INFO *kgrmgrGetGlobalCtxBufInfo(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, GR_GLOBALCTX_BUFFER arg2) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); @@ -369,6 +388,7 @@ static inline const CTX_BUF_INFO *kgrmgrGetGlobalCtxBufInfo(struct OBJGPU *arg0, #endif //__nvoc_kernel_graphics_manager_h_disabled void kgrmgrSetGlobalCtxBufInfo_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, GR_GLOBALCTX_BUFFER arg2, NvU64 size, NvU64 align, RM_ATTR_PAGE_SIZE attr, NvBool bContiguous); + #ifdef __nvoc_kernel_graphics_manager_h_disabled static inline void kgrmgrSetGlobalCtxBufInfo(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, GR_GLOBALCTX_BUFFER arg2, NvU64 size, NvU64 align, RM_ATTR_PAGE_SIZE attr, NvBool bContiguous) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); @@ -378,6 +398,7 @@ static inline void kgrmgrSetGlobalCtxBufInfo(struct OBJGPU *arg0, struct KernelG #endif //__nvoc_kernel_graphics_manager_h_disabled NV_STATUS kgrmgrDiscoverMaxGlobalCtxBufSizes_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, struct KernelGraphics *arg2, NvBool bMemoryPartitioningNeeded); + #ifdef __nvoc_kernel_graphics_manager_h_disabled static inline NV_STATUS kgrmgrDiscoverMaxGlobalCtxBufSizes(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, struct KernelGraphics *arg2, NvBool bMemoryPartitioningNeeded) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); @@ -388,6 +409,7 @@ static inline NV_STATUS kgrmgrDiscoverMaxGlobalCtxBufSizes(struct OBJGPU *arg0, #endif //__nvoc_kernel_graphics_manager_h_disabled NvU32 kgrmgrGetLegacyGpcTpcCount_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 gpcId); + #ifdef __nvoc_kernel_graphics_manager_h_disabled static inline NvU32 kgrmgrGetLegacyGpcTpcCount(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 gpcId) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); @@ -397,6 +419,17 @@ static inline NvU32 kgrmgrGetLegacyGpcTpcCount(struct OBJGPU *arg0, struct Kerne #define kgrmgrGetLegacyGpcTpcCount(arg0, arg1, gpcId) kgrmgrGetLegacyGpcTpcCount_IMPL(arg0, arg1, gpcId) #endif //__nvoc_kernel_graphics_manager_h_disabled +NV_STATUS kgrmgrCheckVeidsRequest_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU64 *pInUseMask, NvU32 veidCount, NvU32 *pSpanStart, KERNEL_MIG_GPU_INSTANCE *arg2); + +#ifdef __nvoc_kernel_graphics_manager_h_disabled +static inline NV_STATUS kgrmgrCheckVeidsRequest(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU64 *pInUseMask, NvU32 veidCount, NvU32 *pSpanStart, KERNEL_MIG_GPU_INSTANCE *arg2) { + NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_graphics_manager_h_disabled +#define kgrmgrCheckVeidsRequest(arg0, arg1, pInUseMask, veidCount, pSpanStart, arg2) kgrmgrCheckVeidsRequest_IMPL(arg0, arg1, pInUseMask, veidCount, pSpanStart, arg2) +#endif //__nvoc_kernel_graphics_manager_h_disabled + #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_kernel_graphics_nvoc.c b/src/nvidia/generated/g_kernel_graphics_nvoc.c index bd2b2e4bf..c0ddce77b 100644 --- a/src/nvidia/generated/g_kernel_graphics_nvoc.c +++ b/src/nvidia/generated/g_kernel_graphics_nvoc.c @@ -107,7 +107,7 @@ static NV_STATUS __nvoc_thunk_KernelGraphics_engstateStatePostLoad(OBJGPU *arg0, return kgraphicsStatePostLoad(arg0, (struct KernelGraphics *)(((unsigned char *)arg1) - __nvoc_rtti_KernelGraphics_OBJENGSTATE.offset), flags); } -static void __nvoc_thunk_KernelGraphics_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[155]) { +static void __nvoc_thunk_KernelGraphics_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[163]) { kgraphicsRegisterIntrService(arg0, (struct KernelGraphics *)(((unsigned char *)arg1) - __nvoc_rtti_KernelGraphics_IntrService.offset), arg2); } @@ -199,68 +199,40 @@ void __nvoc_init_dataField_KernelGraphics(KernelGraphics *pThis, RmHalspecOwner PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // Hal field -- bCtxswLoggingSupported - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->bCtxswLoggingSupported = ((NvBool)(0 == 0)); } - // default - else - { - pThis->bCtxswLoggingSupported = ((NvBool)(0 != 0)); - } // Hal field -- bDeferContextInit if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { pThis->bDeferContextInit = ((NvBool)(0 != 0)); } - else if (0) - { - } // Hal field -- bPerSubcontextContextHeaderSupported - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->bPerSubcontextContextHeaderSupported = ((NvBool)(0 == 0)); } - // default - else - { - pThis->bPerSubcontextContextHeaderSupported = ((NvBool)(0 != 0)); - } // Hal field -- bSetContextBuffersGPUPrivileged - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->bSetContextBuffersGPUPrivileged = ((NvBool)(0 == 0)); } - // default - else - { - pThis->bSetContextBuffersGPUPrivileged = ((NvBool)(0 != 0)); - } // Hal field -- bUcodeSupportsPrivAccessMap - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->bUcodeSupportsPrivAccessMap = ((NvBool)(0 == 0)); } - // default - else - { - pThis->bUcodeSupportsPrivAccessMap = ((NvBool)(0 != 0)); - } // Hal field -- bRtvCbSupported - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->bRtvCbSupported = ((NvBool)(0 == 0)); } - // default - else - { - pThis->bRtvCbSupported = ((NvBool)(0 != 0)); - } } NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); @@ -315,22 +287,16 @@ static void __nvoc_init_funcTable_KernelGraphics_1(KernelGraphics *pThis, RmHals pThis->__kgraphicsServiceNotificationInterrupt__ = &kgraphicsServiceNotificationInterrupt_IMPL; // Hal function -- kgraphicsClearInterrupt - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kgraphicsClearInterrupt__ = &kgraphicsClearInterrupt_GP100; } - else if (0) - { - } // Hal function -- kgraphicsServiceInterrupt - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kgraphicsServiceInterrupt__ = &kgraphicsServiceInterrupt_GP100; } - else if (0) - { - } pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelGraphics_engstateConstructEngine; diff --git a/src/nvidia/generated/g_kernel_graphics_nvoc.h b/src/nvidia/generated/g_kernel_graphics_nvoc.h index 8be4b3fa6..3f4e983b1 100644 --- a/src/nvidia/generated/g_kernel_graphics_nvoc.h +++ b/src/nvidia/generated/g_kernel_graphics_nvoc.h @@ -260,6 +260,7 @@ static inline NvBool kgraphicsShouldForceMainCtxContiguity_cbe027(OBJGPU *arg0, return ((NvBool)(0 == 0)); } + #ifdef __nvoc_kernel_graphics_h_disabled static inline NvBool kgraphicsShouldForceMainCtxContiguity(OBJGPU *arg0, struct KernelGraphics *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); @@ -273,6 +274,7 @@ static inline NvBool kgraphicsShouldForceMainCtxContiguity(OBJGPU *arg0, struct NV_STATUS kgraphicsAllocKgraphicsBuffers_KERNEL(OBJGPU *arg0, struct KernelGraphics *arg1, struct KernelGraphicsContext *arg2, struct KernelChannel *arg3); + #ifdef __nvoc_kernel_graphics_h_disabled static inline NV_STATUS kgraphicsAllocKgraphicsBuffers(OBJGPU *arg0, struct KernelGraphics *arg1, struct KernelGraphicsContext *arg2, struct KernelChannel *arg3) { NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); @@ -286,6 +288,7 @@ static inline NV_STATUS kgraphicsAllocKgraphicsBuffers(OBJGPU *arg0, struct Kern NV_STATUS kgraphicsAllocGrGlobalCtxBuffers_TU102(OBJGPU *arg0, struct KernelGraphics *arg1, NvU32 gfid, struct KernelGraphicsContext *arg2); + #ifdef __nvoc_kernel_graphics_h_disabled static inline NV_STATUS kgraphicsAllocGrGlobalCtxBuffers(OBJGPU *arg0, struct KernelGraphics *arg1, NvU32 gfid, struct KernelGraphicsContext *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); @@ -299,6 +302,7 @@ static inline NV_STATUS kgraphicsAllocGrGlobalCtxBuffers(OBJGPU *arg0, struct Ke NV_STATUS kgraphicsAllocGlobalCtxBuffers_GP100(OBJGPU *arg0, struct KernelGraphics *arg1, NvU32 gfid); + #ifdef __nvoc_kernel_graphics_h_disabled static inline NV_STATUS kgraphicsAllocGlobalCtxBuffers(OBJGPU *arg0, struct KernelGraphics *arg1, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); @@ -312,6 +316,7 @@ static inline NV_STATUS kgraphicsAllocGlobalCtxBuffers(OBJGPU *arg0, struct Kern NV_STATUS kgraphicsLoadStaticInfo_KERNEL(OBJGPU *arg0, struct KernelGraphics *arg1, NvU32 swizzId); + #ifdef __nvoc_kernel_graphics_h_disabled static inline NV_STATUS kgraphicsLoadStaticInfo(OBJGPU *arg0, struct KernelGraphics *arg1, NvU32 swizzId) { NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); @@ -327,6 +332,7 @@ static inline void kgraphicsNonstallIntrCheckAndClear_b3696a(OBJGPU *arg0, struc return; } + #ifdef __nvoc_kernel_graphics_h_disabled static inline void kgraphicsNonstallIntrCheckAndClear(OBJGPU *arg0, struct KernelGraphics *arg1, struct THREAD_STATE_NODE *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); @@ -339,6 +345,7 @@ static inline void kgraphicsNonstallIntrCheckAndClear(OBJGPU *arg0, struct Kerne void kgraphicsInitFecsRegistryOverrides_GP100(OBJGPU *arg0, struct KernelGraphics *arg1); + #ifdef __nvoc_kernel_graphics_h_disabled static inline void kgraphicsInitFecsRegistryOverrides(OBJGPU *arg0, struct KernelGraphics *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); @@ -351,6 +358,7 @@ static inline void kgraphicsInitFecsRegistryOverrides(OBJGPU *arg0, struct Kerne NvBool kgraphicsIsUnrestrictedAccessMapSupported_PF(OBJGPU *arg0, struct KernelGraphics *arg1); + #ifdef __nvoc_kernel_graphics_h_disabled static inline NvBool kgraphicsIsUnrestrictedAccessMapSupported(OBJGPU *arg0, struct KernelGraphics *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); @@ -410,9 +418,9 @@ static inline NV_STATUS kgraphicsStatePostLoad_DISPATCH(OBJGPU *arg0, struct Ker return arg1->__kgraphicsStatePostLoad__(arg0, arg1, flags); } -void kgraphicsRegisterIntrService_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1, IntrServiceRecord arg2[155]); +void kgraphicsRegisterIntrService_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1, IntrServiceRecord arg2[163]); -static inline void kgraphicsRegisterIntrService_DISPATCH(OBJGPU *arg0, struct KernelGraphics *arg1, IntrServiceRecord arg2[155]) { +static inline void kgraphicsRegisterIntrService_DISPATCH(OBJGPU *arg0, struct KernelGraphics *arg1, IntrServiceRecord arg2[163]) { arg1->__kgraphicsRegisterIntrService__(arg0, arg1, arg2); } @@ -424,20 +432,12 @@ static inline NV_STATUS kgraphicsServiceNotificationInterrupt_DISPATCH(OBJGPU *a NvBool kgraphicsClearInterrupt_GP100(OBJGPU *arg0, struct KernelGraphics *arg1, IntrServiceClearInterruptArguments *arg2); -static inline NvBool kgraphicsClearInterrupt_5baef9(OBJGPU *arg0, struct KernelGraphics *arg1, IntrServiceClearInterruptArguments *arg2) { - NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); -} - static inline NvBool kgraphicsClearInterrupt_DISPATCH(OBJGPU *arg0, struct KernelGraphics *arg1, IntrServiceClearInterruptArguments *arg2) { return arg1->__kgraphicsClearInterrupt__(arg0, arg1, arg2); } NvU32 kgraphicsServiceInterrupt_GP100(OBJGPU *arg0, struct KernelGraphics *arg1, IntrServiceServiceInterruptArguments *arg2); -static inline NvU32 kgraphicsServiceInterrupt_5baef9(OBJGPU *arg0, struct KernelGraphics *arg1, IntrServiceServiceInterruptArguments *arg2) { - NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); -} - static inline NvU32 kgraphicsServiceInterrupt_DISPATCH(OBJGPU *arg0, struct KernelGraphics *arg1, IntrServiceServiceInterruptArguments *arg2) { return arg1->__kgraphicsServiceInterrupt__(arg0, arg1, arg2); } @@ -547,8 +547,10 @@ static inline NvBool kgraphicsIsRtvCbSupported(OBJGPU *pGpu, struct KernelGraphi } void kgraphicsDestruct_IMPL(struct KernelGraphics *arg0); + #define __nvoc_kgraphicsDestruct(arg0) kgraphicsDestruct_IMPL(arg0) void kgraphicsInvalidateStaticInfo_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1); + #ifdef __nvoc_kernel_graphics_h_disabled static inline void kgraphicsInvalidateStaticInfo(OBJGPU *arg0, struct KernelGraphics *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); @@ -558,6 +560,7 @@ static inline void kgraphicsInvalidateStaticInfo(OBJGPU *arg0, struct KernelGrap #endif //__nvoc_kernel_graphics_h_disabled const CTX_BUF_INFO *kgraphicsGetCtxBufferInfo_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1, GR_CTX_BUFFER arg2); + #ifdef __nvoc_kernel_graphics_h_disabled static inline const CTX_BUF_INFO *kgraphicsGetCtxBufferInfo(OBJGPU *arg0, struct KernelGraphics *arg1, GR_CTX_BUFFER arg2) { NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); @@ -568,6 +571,7 @@ static inline const CTX_BUF_INFO *kgraphicsGetCtxBufferInfo(OBJGPU *arg0, struct #endif //__nvoc_kernel_graphics_h_disabled void kgraphicsSetCtxBufferInfo_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1, GR_CTX_BUFFER arg2, NvU64 size, NvU64 align, RM_ATTR_PAGE_SIZE attr, NvBool bContiguous); + #ifdef __nvoc_kernel_graphics_h_disabled static inline void kgraphicsSetCtxBufferInfo(OBJGPU *arg0, struct KernelGraphics *arg1, GR_CTX_BUFFER arg2, NvU64 size, NvU64 align, RM_ATTR_PAGE_SIZE attr, NvBool bContiguous) { NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); @@ -577,6 +581,7 @@ static inline void kgraphicsSetCtxBufferInfo(OBJGPU *arg0, struct KernelGraphics #endif //__nvoc_kernel_graphics_h_disabled void kgraphicsClearCtxBufferInfo_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1); + #ifdef __nvoc_kernel_graphics_h_disabled static inline void kgraphicsClearCtxBufferInfo(OBJGPU *arg0, struct KernelGraphics *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); @@ -586,6 +591,7 @@ static inline void kgraphicsClearCtxBufferInfo(OBJGPU *arg0, struct KernelGraphi #endif //__nvoc_kernel_graphics_h_disabled NV_STATUS kgraphicsInitCtxBufPool_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1, struct Heap *arg2); + #ifdef __nvoc_kernel_graphics_h_disabled static inline NV_STATUS kgraphicsInitCtxBufPool(OBJGPU *arg0, struct KernelGraphics *arg1, struct Heap *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); @@ -596,6 +602,7 @@ static inline NV_STATUS kgraphicsInitCtxBufPool(OBJGPU *arg0, struct KernelGraph #endif //__nvoc_kernel_graphics_h_disabled struct CTX_BUF_POOL_INFO *kgraphicsGetCtxBufPool_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1); + #ifdef __nvoc_kernel_graphics_h_disabled static inline struct CTX_BUF_POOL_INFO *kgraphicsGetCtxBufPool(OBJGPU *arg0, struct KernelGraphics *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); @@ -606,6 +613,7 @@ static inline struct CTX_BUF_POOL_INFO *kgraphicsGetCtxBufPool(OBJGPU *arg0, str #endif //__nvoc_kernel_graphics_h_disabled void kgraphicsDestroyCtxBufPool_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1); + #ifdef __nvoc_kernel_graphics_h_disabled static inline void kgraphicsDestroyCtxBufPool(OBJGPU *arg0, struct KernelGraphics *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); @@ -615,6 +623,7 @@ static inline void kgraphicsDestroyCtxBufPool(OBJGPU *arg0, struct KernelGraphic #endif //__nvoc_kernel_graphics_h_disabled GR_GLOBALCTX_BUFFERS *kgraphicsGetGlobalCtxBuffers_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1, NvU32 gfid); + #ifdef __nvoc_kernel_graphics_h_disabled static inline GR_GLOBALCTX_BUFFERS *kgraphicsGetGlobalCtxBuffers(OBJGPU *arg0, struct KernelGraphics *arg1, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); @@ -625,6 +634,7 @@ static inline GR_GLOBALCTX_BUFFERS *kgraphicsGetGlobalCtxBuffers(OBJGPU *arg0, s #endif //__nvoc_kernel_graphics_h_disabled NvBool kgraphicsIsGlobalCtxBufferSizeAligned_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1, GR_GLOBALCTX_BUFFER arg2); + #ifdef __nvoc_kernel_graphics_h_disabled static inline NvBool kgraphicsIsGlobalCtxBufferSizeAligned(OBJGPU *arg0, struct KernelGraphics *arg1, GR_GLOBALCTX_BUFFER arg2) { NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); @@ -635,6 +645,7 @@ static inline NvBool kgraphicsIsGlobalCtxBufferSizeAligned(OBJGPU *arg0, struct #endif //__nvoc_kernel_graphics_h_disabled const GR_BUFFER_ATTR *kgraphicsGetGlobalPrivAccessMapAttr_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1); + #ifdef __nvoc_kernel_graphics_h_disabled static inline const GR_BUFFER_ATTR *kgraphicsGetGlobalPrivAccessMapAttr(OBJGPU *arg0, struct KernelGraphics *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); @@ -645,6 +656,7 @@ static inline const GR_BUFFER_ATTR *kgraphicsGetGlobalPrivAccessMapAttr(OBJGPU * #endif //__nvoc_kernel_graphics_h_disabled NV_STATUS kgraphicsMapCtxBuffer_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1, MEMORY_DESCRIPTOR *arg2, struct OBJVASPACE *arg3, VA_LIST *arg4, NvBool bAlignSize, NvBool bIsReadOnly); + #ifdef __nvoc_kernel_graphics_h_disabled static inline NV_STATUS kgraphicsMapCtxBuffer(OBJGPU *arg0, struct KernelGraphics *arg1, MEMORY_DESCRIPTOR *arg2, struct OBJVASPACE *arg3, VA_LIST *arg4, NvBool bAlignSize, NvBool bIsReadOnly) { NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); @@ -655,6 +667,7 @@ static inline NV_STATUS kgraphicsMapCtxBuffer(OBJGPU *arg0, struct KernelGraphic #endif //__nvoc_kernel_graphics_h_disabled void kgraphicsUnmapCtxBuffer_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1, struct OBJVASPACE *arg2, VA_LIST *arg3); + #ifdef __nvoc_kernel_graphics_h_disabled static inline void kgraphicsUnmapCtxBuffer(OBJGPU *arg0, struct KernelGraphics *arg1, struct OBJVASPACE *arg2, VA_LIST *arg3) { NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); @@ -664,6 +677,7 @@ static inline void kgraphicsUnmapCtxBuffer(OBJGPU *arg0, struct KernelGraphics * #endif //__nvoc_kernel_graphics_h_disabled void kgraphicsFreeGlobalCtxBuffers_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1, NvU32 gfid); + #ifdef __nvoc_kernel_graphics_h_disabled static inline void kgraphicsFreeGlobalCtxBuffers(OBJGPU *arg0, struct KernelGraphics *arg1, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); @@ -673,6 +687,7 @@ static inline void kgraphicsFreeGlobalCtxBuffers(OBJGPU *arg0, struct KernelGrap #endif //__nvoc_kernel_graphics_h_disabled NV_STATUS kgraphicsGetMainCtxBufferSize_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1, NvBool bIncludeSubctxHdrs, NvU32 *pSize); + #ifdef __nvoc_kernel_graphics_h_disabled static inline NV_STATUS kgraphicsGetMainCtxBufferSize(OBJGPU *arg0, struct KernelGraphics *arg1, NvBool bIncludeSubctxHdrs, NvU32 *pSize) { NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); @@ -683,6 +698,7 @@ static inline NV_STATUS kgraphicsGetMainCtxBufferSize(OBJGPU *arg0, struct Kerne #endif //__nvoc_kernel_graphics_h_disabled NV_STATUS kgraphicsGetClassByType_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1, NvU32 objectType, NvU32 *pClass); + #ifdef __nvoc_kernel_graphics_h_disabled static inline NV_STATUS kgraphicsGetClassByType(OBJGPU *arg0, struct KernelGraphics *arg1, NvU32 objectType, NvU32 *pClass) { NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); @@ -693,6 +709,7 @@ static inline NV_STATUS kgraphicsGetClassByType(OBJGPU *arg0, struct KernelGraph #endif //__nvoc_kernel_graphics_h_disabled const GR_BUFFER_ATTR *kgraphicsGetContextBufferAttr_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1, GR_CTX_BUFFER arg2); + #ifdef __nvoc_kernel_graphics_h_disabled static inline const GR_BUFFER_ATTR *kgraphicsGetContextBufferAttr(OBJGPU *arg0, struct KernelGraphics *arg1, GR_CTX_BUFFER arg2) { NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); @@ -703,6 +720,7 @@ static inline const GR_BUFFER_ATTR *kgraphicsGetContextBufferAttr(OBJGPU *arg0, #endif //__nvoc_kernel_graphics_h_disabled NV_STATUS kgraphicsCreateGoldenImageChannel_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1); + #ifdef __nvoc_kernel_graphics_h_disabled static inline NV_STATUS kgraphicsCreateGoldenImageChannel(OBJGPU *arg0, struct KernelGraphics *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); @@ -713,6 +731,7 @@ static inline NV_STATUS kgraphicsCreateGoldenImageChannel(OBJGPU *arg0, struct K #endif //__nvoc_kernel_graphics_h_disabled NV_STATUS kgraphicsInitializeDeferredStaticData_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1, NvHandle hClient, NvHandle hSubdevice); + #ifdef __nvoc_kernel_graphics_h_disabled static inline NV_STATUS kgraphicsInitializeDeferredStaticData(OBJGPU *arg0, struct KernelGraphics *arg1, NvHandle hClient, NvHandle hSubdevice) { NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); @@ -723,6 +742,7 @@ static inline NV_STATUS kgraphicsInitializeDeferredStaticData(OBJGPU *arg0, stru #endif //__nvoc_kernel_graphics_h_disabled const struct KGRAPHICS_STATIC_INFO *kgraphicsGetStaticInfo_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1); + #ifdef __nvoc_kernel_graphics_h_disabled static inline const struct KGRAPHICS_STATIC_INFO *kgraphicsGetStaticInfo(OBJGPU *arg0, struct KernelGraphics *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); @@ -733,6 +753,7 @@ static inline const struct KGRAPHICS_STATIC_INFO *kgraphicsGetStaticInfo(OBJGPU #endif //__nvoc_kernel_graphics_h_disabled NV_STATUS kgraphicsGetCaps_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1, NvU8 *pGrCaps); + #ifdef __nvoc_kernel_graphics_h_disabled static inline NV_STATUS kgraphicsGetCaps(OBJGPU *arg0, struct KernelGraphics *arg1, NvU8 *pGrCaps) { NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); diff --git a/src/nvidia/generated/g_kernel_graphics_object_nvoc.c b/src/nvidia/generated/g_kernel_graphics_object_nvoc.c index 56f6eb4ec..f95267727 100644 --- a/src/nvidia/generated/g_kernel_graphics_object_nvoc.c +++ b/src/nvidia/generated/g_kernel_graphics_object_nvoc.c @@ -220,6 +220,10 @@ static void __nvoc_thunk_RsResource_kgrobjPreDestruct(struct KernelGraphicsObjec resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsObject_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_RsResource_kgrobjIsDuplicate(struct KernelGraphicsObject *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsObject_RsResource.offset), hMemory, pDuplicate); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_kgrobjGetNotificationListPtr(struct KernelGraphicsObject *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelGraphicsObject_Notifier.offset)); } @@ -345,6 +349,8 @@ static void __nvoc_init_funcTable_KernelGraphicsObject_1(KernelGraphicsObject *p pThis->__kgrobjPreDestruct__ = &__nvoc_thunk_RsResource_kgrobjPreDestruct; + pThis->__kgrobjIsDuplicate__ = &__nvoc_thunk_RsResource_kgrobjIsDuplicate; + pThis->__kgrobjGetNotificationListPtr__ = &__nvoc_thunk_Notifier_kgrobjGetNotificationListPtr; pThis->__kgrobjGetNotificationShare__ = &__nvoc_thunk_Notifier_kgrobjGetNotificationShare; diff --git a/src/nvidia/generated/g_kernel_graphics_object_nvoc.h b/src/nvidia/generated/g_kernel_graphics_object_nvoc.h index f72afc321..7005d4736 100644 --- a/src/nvidia/generated/g_kernel_graphics_object_nvoc.h +++ b/src/nvidia/generated/g_kernel_graphics_object_nvoc.h @@ -101,6 +101,7 @@ struct KernelGraphicsObject { NV_STATUS (*__kgrobjUnregisterEvent__)(struct KernelGraphicsObject *, NvHandle, NvHandle, NvHandle, NvHandle); NvBool (*__kgrobjCanCopy__)(struct KernelGraphicsObject *); void (*__kgrobjPreDestruct__)(struct KernelGraphicsObject *); + NV_STATUS (*__kgrobjIsDuplicate__)(struct KernelGraphicsObject *, NvHandle, NvBool *); PEVENTNOTIFICATION *(*__kgrobjGetNotificationListPtr__)(struct KernelGraphicsObject *); struct NotifShare *(*__kgrobjGetNotificationShare__)(struct KernelGraphicsObject *); NV_STATUS (*__kgrobjMap__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -163,12 +164,14 @@ NV_STATUS __nvoc_objCreate_KernelGraphicsObject(KernelGraphicsObject**, Dynamic* #define kgrobjUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) kgrobjUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define kgrobjCanCopy(pResource) kgrobjCanCopy_DISPATCH(pResource) #define kgrobjPreDestruct(pResource) kgrobjPreDestruct_DISPATCH(pResource) +#define kgrobjIsDuplicate(pResource, hMemory, pDuplicate) kgrobjIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define kgrobjGetNotificationListPtr(pNotifier) kgrobjGetNotificationListPtr_DISPATCH(pNotifier) #define kgrobjGetNotificationShare(pNotifier) kgrobjGetNotificationShare_DISPATCH(pNotifier) #define kgrobjMap(pGpuResource, pCallContext, pParams, pCpuMapping) kgrobjMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define kgrobjGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) kgrobjGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) void kgrobjGetPromoteIds_FWCLIENT(struct OBJGPU *arg0, struct KernelGraphicsObject *arg1, NvU32 maxPromoteIds, NvU32 *pPromoteIds, NvU32 *pNumEntries, NvBool *pbPromote); + #ifdef __nvoc_kernel_graphics_object_h_disabled static inline void kgrobjGetPromoteIds(struct OBJGPU *arg0, struct KernelGraphicsObject *arg1, NvU32 maxPromoteIds, NvU32 *pPromoteIds, NvU32 *pNumEntries, NvBool *pbPromote) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsObject was disabled!"); @@ -181,6 +184,7 @@ static inline void kgrobjGetPromoteIds(struct OBJGPU *arg0, struct KernelGraphic NvBool kgrobjShouldCleanup_KERNEL(struct OBJGPU *arg0, struct KernelGraphicsObject *arg1); + #ifdef __nvoc_kernel_graphics_object_h_disabled static inline NvBool kgrobjShouldCleanup(struct OBJGPU *arg0, struct KernelGraphicsObject *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsObject was disabled!"); @@ -194,6 +198,7 @@ static inline NvBool kgrobjShouldCleanup(struct OBJGPU *arg0, struct KernelGraph NV_STATUS kgrobjSetComputeMmio_IMPL(struct OBJGPU *arg0, struct KernelGraphicsObject *arg1); + #ifdef __nvoc_kernel_graphics_object_h_disabled static inline NV_STATUS kgrobjSetComputeMmio(struct OBJGPU *arg0, struct KernelGraphicsObject *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsObject was disabled!"); @@ -207,6 +212,7 @@ static inline NV_STATUS kgrobjSetComputeMmio(struct OBJGPU *arg0, struct KernelG void kgrobjFreeComputeMmio_IMPL(struct OBJGPU *arg0, struct KernelGraphicsObject *arg1); + #ifdef __nvoc_kernel_graphics_object_h_disabled static inline void kgrobjFreeComputeMmio(struct OBJGPU *arg0, struct KernelGraphicsObject *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsObject was disabled!"); @@ -319,6 +325,10 @@ static inline void kgrobjPreDestruct_DISPATCH(struct KernelGraphicsObject *pReso pResource->__kgrobjPreDestruct__(pResource); } +static inline NV_STATUS kgrobjIsDuplicate_DISPATCH(struct KernelGraphicsObject *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__kgrobjIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline PEVENTNOTIFICATION *kgrobjGetNotificationListPtr_DISPATCH(struct KernelGraphicsObject *pNotifier) { return pNotifier->__kgrobjGetNotificationListPtr__(pNotifier); } @@ -336,10 +346,13 @@ static inline NV_STATUS kgrobjGetOrAllocNotifShare_DISPATCH(struct KernelGraphic } NV_STATUS kgrobjConstruct_IMPL(struct KernelGraphicsObject *arg_pKernelGraphicsObject, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_kgrobjConstruct(arg_pKernelGraphicsObject, arg_pCallContext, arg_pParams) kgrobjConstruct_IMPL(arg_pKernelGraphicsObject, arg_pCallContext, arg_pParams) void kgrobjDestruct_IMPL(struct KernelGraphicsObject *pKernelGraphicsObject); + #define __nvoc_kgrobjDestruct(pKernelGraphicsObject) kgrobjDestruct_IMPL(pKernelGraphicsObject) NV_STATUS kgrobjPromoteContext_IMPL(struct OBJGPU *arg0, struct KernelGraphicsObject *arg1, struct KernelGraphics *arg2); + #ifdef __nvoc_kernel_graphics_object_h_disabled static inline NV_STATUS kgrobjPromoteContext(struct OBJGPU *arg0, struct KernelGraphicsObject *arg1, struct KernelGraphics *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsObject was disabled!"); diff --git a/src/nvidia/generated/g_kernel_gsp_nvoc.c b/src/nvidia/generated/g_kernel_gsp_nvoc.c index 610d24215..1906741ee 100644 --- a/src/nvidia/generated/g_kernel_gsp_nvoc.c +++ b/src/nvidia/generated/g_kernel_gsp_nvoc.c @@ -88,7 +88,7 @@ static NV_STATUS __nvoc_thunk_KernelGsp_engstateConstructEngine(struct OBJGPU *p return kgspConstructEngine(pGpu, (struct KernelGsp *)(((unsigned char *)pKernelGsp) - __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), arg0); } -static void __nvoc_thunk_KernelGsp_intrservRegisterIntrService(struct OBJGPU *pGpu, struct IntrService *pKernelGsp, IntrServiceRecord pRecords[155]) { +static void __nvoc_thunk_KernelGsp_intrservRegisterIntrService(struct OBJGPU *pGpu, struct IntrService *pKernelGsp, IntrServiceRecord pRecords[163]) { kgspRegisterIntrService(pGpu, (struct KernelGsp *)(((unsigned char *)pKernelGsp) - __nvoc_rtti_KernelGsp_IntrService.offset), pRecords); } @@ -218,7 +218,7 @@ void __nvoc_init_dataField_KernelGsp(KernelGsp *pThis, RmHalspecOwner *pRmhalspe PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // Hal field -- bPartitionedFmc - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->bPartitionedFmc = ((NvBool)(0 == 0)); } @@ -229,14 +229,14 @@ void __nvoc_init_dataField_KernelGsp(KernelGsp *pThis, RmHalspecOwner *pRmhalspe } } -NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* , RmHalspecOwner* ); -NV_STATUS __nvoc_ctor_IntrService(IntrService* , RmHalspecOwner* ); +NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); +NV_STATUS __nvoc_ctor_IntrService(IntrService* ); NV_STATUS __nvoc_ctor_KernelFalcon(KernelFalcon* , RmHalspecOwner* ); NV_STATUS __nvoc_ctor_KernelGsp(KernelGsp *pThis, RmHalspecOwner *pRmhalspecowner) { NV_STATUS status = NV_OK; - status = __nvoc_ctor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE, pRmhalspecowner); + status = __nvoc_ctor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); if (status != NV_OK) goto __nvoc_ctor_KernelGsp_fail_OBJENGSTATE; - status = __nvoc_ctor_IntrService(&pThis->__nvoc_base_IntrService, pRmhalspecowner); + status = __nvoc_ctor_IntrService(&pThis->__nvoc_base_IntrService); if (status != NV_OK) goto __nvoc_ctor_KernelGsp_fail_IntrService; status = __nvoc_ctor_KernelFalcon(&pThis->__nvoc_base_KernelFalcon, pRmhalspecowner); if (status != NV_OK) goto __nvoc_ctor_KernelGsp_fail_KernelFalcon; @@ -278,16 +278,10 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * { pThis->__kgspConfigureFalcon__ = &kgspConfigureFalcon_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kgspConfigureFalcon__ = &kgspConfigureFalcon_GA102; } - else if (0) - { - } - } - else if (0) - { } // Hal function -- kgspIsDebugModeEnabled @@ -297,54 +291,36 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * { pThis->__kgspIsDebugModeEnabled__ = &kgspIsDebugModeEnabled_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kgspIsDebugModeEnabled__ = &kgspIsDebugModeEnabled_GA100; } - else if (0) - { - } - } - else if (0) - { } // Hal function -- kgspAllocBootArgs if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kgspAllocBootArgs__ = &kgspAllocBootArgs_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kgspAllocBootArgs__ = &kgspAllocBootArgs_GH100; } - else if (0) - { - } - } - else if (0) - { } // Hal function -- kgspFreeBootArgs if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kgspFreeBootArgs__ = &kgspFreeBootArgs_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kgspFreeBootArgs__ = &kgspFreeBootArgs_GH100; } - else if (0) - { - } - } - else if (0) - { } // Hal function -- kgspBootstrapRiscvOSEarly @@ -354,20 +330,14 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * { pThis->__kgspBootstrapRiscvOSEarly__ = &kgspBootstrapRiscvOSEarly_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kgspBootstrapRiscvOSEarly__ = &kgspBootstrapRiscvOSEarly_GA102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kgspBootstrapRiscvOSEarly__ = &kgspBootstrapRiscvOSEarly_GH100; } - else if (0) - { - } - } - else if (0) - { } // Hal function -- kgspGetGspRmBootUcodeStorage @@ -377,17 +347,15 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * { pThis->__kgspGetGspRmBootUcodeStorage__ = &kgspGetGspRmBootUcodeStorage_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kgspGetGspRmBootUcodeStorage__ = &kgspGetGspRmBootUcodeStorage_GA102; } - else if (0) + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { + pThis->__kgspGetGspRmBootUcodeStorage__ = &kgspGetGspRmBootUcodeStorage_GH100; } } - else if (0) - { - } // Hal function -- kgspGetBinArchiveGspRmBoot if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ @@ -404,93 +372,68 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * { pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_GA102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00700000UL) )) /* ChipHal: AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_AD102; } - else if (0) - { - } - } - else if (0) - { } - // Hal function -- kgspGetBinArchiveGspRmCcGfwDebugSigned + // Hal function -- kgspGetBinArchiveGspRmFmcGfwDebugSigned if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kgspGetBinArchiveGspRmCcGfwDebugSigned__ = &kgspGetBinArchiveGspRmCcGfwDebugSigned_GH100; + pThis->__kgspGetBinArchiveGspRmFmcGfwDebugSigned__ = &kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100; } // default else { - pThis->__kgspGetBinArchiveGspRmCcGfwDebugSigned__ = &kgspGetBinArchiveGspRmCcGfwDebugSigned_80f438; + pThis->__kgspGetBinArchiveGspRmFmcGfwDebugSigned__ = &kgspGetBinArchiveGspRmFmcGfwDebugSigned_80f438; } } - else if (0) - { - } - // Hal function -- kgspGetBinArchiveGspRmCcGfwProdSigned + // Hal function -- kgspGetBinArchiveGspRmFmcGfwProdSigned if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kgspGetBinArchiveGspRmCcGfwProdSigned__ = &kgspGetBinArchiveGspRmCcGfwProdSigned_GH100; + pThis->__kgspGetBinArchiveGspRmFmcGfwProdSigned__ = &kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100; } // default else { - pThis->__kgspGetBinArchiveGspRmCcGfwProdSigned__ = &kgspGetBinArchiveGspRmCcGfwProdSigned_80f438; + pThis->__kgspGetBinArchiveGspRmFmcGfwProdSigned__ = &kgspGetBinArchiveGspRmFmcGfwProdSigned_80f438; } } - else if (0) - { - } // Hal function -- kgspCalculateFbLayout if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kgspCalculateFbLayout__ = &kgspCalculateFbLayout_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kgspCalculateFbLayout__ = &kgspCalculateFbLayout_GH100; } - else if (0) - { - } - } - else if (0) - { } // Hal function -- kgspGetNonWprHeapSize if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kgspGetNonWprHeapSize__ = &kgspGetNonWprHeapSize_ed6b8b; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kgspGetNonWprHeapSize__ = &kgspGetNonWprHeapSize_d505ea; } - // default - else - { - } - } - else if (0) - { } // Hal function -- kgspExecuteSequencerCommand @@ -500,16 +443,10 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * { pThis->__kgspExecuteSequencerCommand__ = &kgspExecuteSequencerCommand_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kgspExecuteSequencerCommand__ = &kgspExecuteSequencerCommand_GA102; } - else if (0) - { - } - } - else if (0) - { } // Hal function -- kgspReadUcodeFuseVersion @@ -519,153 +456,111 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * { pThis->__kgspReadUcodeFuseVersion__ = &kgspReadUcodeFuseVersion_b2b553; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kgspReadUcodeFuseVersion__ = &kgspReadUcodeFuseVersion_GA100; } - else if (0) - { - } - } - else if (0) - { } // Hal function -- kgspResetHw if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kgspResetHw__ = &kgspResetHw_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kgspResetHw__ = &kgspResetHw_GH100; } - else if (0) - { - } - } - else if (0) - { } // Hal function -- kgspIsEngineInReset if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kgspIsEngineInReset__ = &kgspIsEngineInReset_TU102; } - else if (0) - { - } - } - else if (0) - { } // Hal function -- kgspGetFrtsSize if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kgspGetFrtsSize__ = &kgspGetFrtsSize_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kgspGetFrtsSize__ = &kgspGetFrtsSize_4a4dee; } } - else if (0) - { - } // Hal function -- kgspExtractVbiosFromRom if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kgspExtractVbiosFromRom__ = &kgspExtractVbiosFromRom_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kgspExtractVbiosFromRom__ = &kgspExtractVbiosFromRom_395e98; } - else if (0) - { - } - } - else if (0) - { } // Hal function -- kgspExecuteFwsecFrts if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kgspExecuteFwsecFrts__ = &kgspExecuteFwsecFrts_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kgspExecuteFwsecFrts__ = &kgspExecuteFwsecFrts_5baef9; } } - else if (0) - { - } // Hal function -- kgspExecuteFwsecSb if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kgspExecuteFwsecSb__ = &kgspExecuteFwsecSb_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kgspExecuteFwsecSb__ = &kgspExecuteFwsecSb_ac1694; } - else if (0) - { - } - } - else if (0) - { } // Hal function -- kgspExecuteBooterLoad if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kgspExecuteBooterLoad__ = &kgspExecuteBooterLoad_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kgspExecuteBooterLoad__ = &kgspExecuteBooterLoad_5baef9; } } - else if (0) - { - } // Hal function -- kgspExecuteBooterUnloadIfNeeded if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kgspExecuteBooterUnloadIfNeeded__ = &kgspExecuteBooterUnloadIfNeeded_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kgspExecuteBooterUnloadIfNeeded__ = &kgspExecuteBooterUnloadIfNeeded_5baef9; } } - else if (0) - { - } // Hal function -- kgspExecuteHsFalcon if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ @@ -674,36 +569,27 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * { pThis->__kgspExecuteHsFalcon__ = &kgspExecuteHsFalcon_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kgspExecuteHsFalcon__ = &kgspExecuteHsFalcon_GA102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kgspExecuteHsFalcon__ = &kgspExecuteHsFalcon_5baef9; } } - else if (0) - { - } // Hal function -- kgspWaitForGfwBootOk if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kgspWaitForGfwBootOk__ = &kgspWaitForGfwBootOk_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kgspWaitForGfwBootOk__ = &kgspWaitForGfwBootOk_GH100; } - else if (0) - { - } - } - else if (0) - { } // Hal function -- kgspGetBinArchiveBooterLoadUcode @@ -725,18 +611,15 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * { pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_GA102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00700000UL) )) /* ChipHal: AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_AD102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_80f438; } } - else if (0) - { - } // Hal function -- kgspGetBinArchiveBooterUnloadUcode if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ @@ -757,59 +640,47 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * { pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_GA102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00700000UL) )) /* ChipHal: AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_AD102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_80f438; } } - else if (0) - { - } - // Hal function -- kgspGetSignatureSectionName + // Hal function -- kgspGetWprHeapSize if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x1000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | GH100 */ { - pThis->__kgspGetSignatureSectionName__ = &kgspGetSignatureSectionName_63b8e2; + pThis->__kgspGetWprHeapSize__ = &kgspGetWprHeapSize_e77d51; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ { - pThis->__kgspGetSignatureSectionName__ = &kgspGetSignatureSectionName_e46f5b; + pThis->__kgspGetWprHeapSize__ = &kgspGetWprHeapSize_38f3bc; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000000e0UL) )) /* ChipHal: TU102 | TU104 | TU106 */ + } + + // Hal function -- kgspGetSignatureSectionNamePrefix + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kgspGetSignatureSectionName__ = &kgspGetSignatureSectionName_cbc19d; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000300UL) )) /* ChipHal: TU116 | TU117 */ - { - pThis->__kgspGetSignatureSectionName__ = &kgspGetSignatureSectionName_ab7237; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00700000UL) )) /* ChipHal: AD102 | AD103 | AD104 */ - { - pThis->__kgspGetSignatureSectionName__ = &kgspGetSignatureSectionName_20361c; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kgspGetSignatureSectionName__ = &kgspGetSignatureSectionName_5f1986; + pThis->__kgspGetSignatureSectionNamePrefix__ = &kgspGetSignatureSectionNamePrefix_GH100; } // default else { + pThis->__kgspGetSignatureSectionNamePrefix__ = &kgspGetSignatureSectionNamePrefix_789efb; } } - else if (0) - { - } // Hal function -- kgspSetupGspFmcArgs if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kgspSetupGspFmcArgs__ = &kgspSetupGspFmcArgs_GH100; } @@ -819,9 +690,6 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * pThis->__kgspSetupGspFmcArgs__ = &kgspSetupGspFmcArgs_5baef9; } } - else if (0) - { - } pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelGsp_engstateConstructEngine; @@ -880,8 +748,8 @@ void __nvoc_init_funcTable_KernelGsp(KernelGsp *pThis, RmHalspecOwner *pRmhalspe __nvoc_init_funcTable_KernelGsp_1(pThis, pRmhalspecowner); } -void __nvoc_init_OBJENGSTATE(OBJENGSTATE*, RmHalspecOwner* ); -void __nvoc_init_IntrService(IntrService*, RmHalspecOwner* ); +void __nvoc_init_OBJENGSTATE(OBJENGSTATE*); +void __nvoc_init_IntrService(IntrService*); void __nvoc_init_KernelFalcon(KernelFalcon*, RmHalspecOwner* ); void __nvoc_init_KernelGsp(KernelGsp *pThis, RmHalspecOwner *pRmhalspecowner) { pThis->__nvoc_pbase_KernelGsp = pThis; @@ -889,8 +757,8 @@ void __nvoc_init_KernelGsp(KernelGsp *pThis, RmHalspecOwner *pRmhalspecowner) { pThis->__nvoc_pbase_OBJENGSTATE = &pThis->__nvoc_base_OBJENGSTATE; pThis->__nvoc_pbase_IntrService = &pThis->__nvoc_base_IntrService; pThis->__nvoc_pbase_KernelFalcon = &pThis->__nvoc_base_KernelFalcon; - __nvoc_init_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE, pRmhalspecowner); - __nvoc_init_IntrService(&pThis->__nvoc_base_IntrService, pRmhalspecowner); + __nvoc_init_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); + __nvoc_init_IntrService(&pThis->__nvoc_base_IntrService); __nvoc_init_KernelFalcon(&pThis->__nvoc_base_KernelFalcon, pRmhalspecowner); __nvoc_init_funcTable_KernelGsp(pThis, pRmhalspecowner); } diff --git a/src/nvidia/generated/g_kernel_gsp_nvoc.h b/src/nvidia/generated/g_kernel_gsp_nvoc.h index 9f26a8887..510011df6 100644 --- a/src/nvidia/generated/g_kernel_gsp_nvoc.h +++ b/src/nvidia/generated/g_kernel_gsp_nvoc.h @@ -48,17 +48,18 @@ extern "C" { #include "gpu/falcon/kernel_falcon.h" #include "gpu/gsp/gsp_static_config.h" #include "gpu/gsp/gsp_init_args.h" +#include "nv-firmware.h" #include "rmRiscvUcode.h" #include "libos_init_args.h" #include "gsp_fw_wpr_meta.h" -#include "logdecode.h" +#include "liblogdecode.h" /*! * Forward declarations */ typedef struct SimAccessBuffer SimAccessBuffer; -typedef struct GSP_CC_BOOT_PARAMS GSP_CC_BOOT_PARAMS; +typedef struct GSP_FMC_BOOT_PARAMS GSP_FMC_BOOT_PARAMS; /*! * Structure for VBIOS image for early FRTS. @@ -188,17 +189,23 @@ typedef struct KernelGspFlcnUcode */ typedef struct GSP_FIRMWARE { - const void *pBuf; // buffer holding the firmware (ucode) - NvU32 size; // size of the firmware - const void *pLogElf; // firmware logging section and symbol information to decode logs - NvU32 logElfSize; // size of the gsp log elf binary + const void *pBuf; // buffer holding the firmware (ucode) + NvU32 size; // size of the firmware + const void *pImageData; // points to the GSP FW image start inside the pBuf buffer + NvU64 imageSize; // GSP FW image size inside the pBuf buffer + const void *pSignatureData; // points to the GSP FW signature start inside the pBuf buffer + NvU64 signatureSize; // GSP FW signature size inside the pBuf buffer + const void *pLogElf; // firmware logging section and symbol information to decode logs + NvU32 logElfSize; // size of the gsp log elf binary } GSP_FIRMWARE; /*! - * All signature sections in the elf must start with this prefix which can be - * used to identify them + * Known ELF section names (or name prefixes) of gsp_*.bin or gsp_log_*.bin. */ -#define SIGNATURE_SECTION_NAME_PREFIX ".fwsignature_" +#define GSP_VERSION_SECTION_NAME ".fwversion" +#define GSP_IMAGE_SECTION_NAME ".fwimage" +#define GSP_LOGGING_SECTION_NAME ".fwlogging" +#define GSP_SIGNATURE_SECTION_NAME_PREFIX ".fwsignature_" /*! * Index into libosLogDecode array. @@ -206,6 +213,7 @@ typedef struct GSP_FIRMWARE enum { LOGIDX_INIT, + LOGIDX_VGPU, LOGIDX_RM, LOGIDX_SIZE }; @@ -250,8 +258,8 @@ struct KernelGsp { NV_STATUS (*__kgspBootstrapRiscvOSEarly__)(struct OBJGPU *, struct KernelGsp *, GSP_FIRMWARE *); void (*__kgspGetGspRmBootUcodeStorage__)(struct OBJGPU *, struct KernelGsp *, BINDATA_STORAGE **, BINDATA_STORAGE **); const BINDATA_ARCHIVE *(*__kgspGetBinArchiveGspRmBoot__)(struct KernelGsp *); - const BINDATA_ARCHIVE *(*__kgspGetBinArchiveGspRmCcGfwDebugSigned__)(struct KernelGsp *); - const BINDATA_ARCHIVE *(*__kgspGetBinArchiveGspRmCcGfwProdSigned__)(struct KernelGsp *); + const BINDATA_ARCHIVE *(*__kgspGetBinArchiveGspRmFmcGfwDebugSigned__)(struct KernelGsp *); + const BINDATA_ARCHIVE *(*__kgspGetBinArchiveGspRmFmcGfwProdSigned__)(struct KernelGsp *); NV_STATUS (*__kgspCalculateFbLayout__)(struct OBJGPU *, struct KernelGsp *, GSP_FIRMWARE *); NvU32 (*__kgspGetNonWprHeapSize__)(struct OBJGPU *, struct KernelGsp *); NV_STATUS (*__kgspExecuteSequencerCommand__)(struct OBJGPU *, struct KernelGsp *, NvU32, NvU32 *, NvU32); @@ -268,7 +276,8 @@ struct KernelGsp { NV_STATUS (*__kgspWaitForGfwBootOk__)(struct OBJGPU *, struct KernelGsp *); const BINDATA_ARCHIVE *(*__kgspGetBinArchiveBooterLoadUcode__)(struct KernelGsp *); const BINDATA_ARCHIVE *(*__kgspGetBinArchiveBooterUnloadUcode__)(struct KernelGsp *); - const char *(*__kgspGetSignatureSectionName__)(struct OBJGPU *, struct KernelGsp *); + NvU64 (*__kgspGetWprHeapSize__)(struct OBJGPU *, struct KernelGsp *); + const char *(*__kgspGetSignatureSectionNamePrefix__)(struct OBJGPU *, struct KernelGsp *); NV_STATUS (*__kgspSetupGspFmcArgs__)(struct OBJGPU *, struct KernelGsp *, GSP_FIRMWARE *); void (*__kgspStateDestroy__)(POBJGPU, struct KernelGsp *); void (*__kgspFreeTunableState__)(POBJGPU, struct KernelGsp *, void *); @@ -299,7 +308,7 @@ struct KernelGsp { GspFwWprMeta *pWprMeta; NvP64 pWprMetaMappingPriv; MEMORY_DESCRIPTOR *pGspFmcArgumentsDescriptor; - GSP_CC_BOOT_PARAMS *pGspFmcArgumentsCached; + GSP_FMC_BOOT_PARAMS *pGspFmcArgumentsCached; NvP64 pGspFmcArgumentsMappingPriv; MEMORY_DESCRIPTOR *pLibosInitArgumentsDescriptor; LibosMemoryRegionInitArgument *pLibosInitArgumentsCached; @@ -315,11 +324,12 @@ struct KernelGsp { MEMORY_DESCRIPTOR *pGspUCodeRadix3Descriptor; MEMORY_DESCRIPTOR *pSignatureMemdesc; LIBOS_LOG_DECODE logDecode; - RM_LIBOS_LOG_MEM rmLibosLogMem[2]; + RM_LIBOS_LOG_MEM rmLibosLogMem[3]; void *pLogElf; NvBool bLibosLogsPollingEnabled; - NvBool bXid119Printed; NvBool bInInit; + NvBool bPollingForRpcResponse; + NvBool bXid119Printed; MEMORY_DESCRIPTOR *pMemDesc_simAccessBuf; SimAccessBuffer *pSimAccessBuf; NvP64 pSimAccessBufPriv; @@ -374,10 +384,10 @@ NV_STATUS __nvoc_objCreate_KernelGsp(KernelGsp**, Dynamic*, NvU32); #define kgspGetGspRmBootUcodeStorage_HAL(pGpu, pKernelGsp, ppBinStorageImage, ppBinStorageDesc) kgspGetGspRmBootUcodeStorage_DISPATCH(pGpu, pKernelGsp, ppBinStorageImage, ppBinStorageDesc) #define kgspGetBinArchiveGspRmBoot(pKernelGsp) kgspGetBinArchiveGspRmBoot_DISPATCH(pKernelGsp) #define kgspGetBinArchiveGspRmBoot_HAL(pKernelGsp) kgspGetBinArchiveGspRmBoot_DISPATCH(pKernelGsp) -#define kgspGetBinArchiveGspRmCcGfwDebugSigned(pKernelGsp) kgspGetBinArchiveGspRmCcGfwDebugSigned_DISPATCH(pKernelGsp) -#define kgspGetBinArchiveGspRmCcGfwDebugSigned_HAL(pKernelGsp) kgspGetBinArchiveGspRmCcGfwDebugSigned_DISPATCH(pKernelGsp) -#define kgspGetBinArchiveGspRmCcGfwProdSigned(pKernelGsp) kgspGetBinArchiveGspRmCcGfwProdSigned_DISPATCH(pKernelGsp) -#define kgspGetBinArchiveGspRmCcGfwProdSigned_HAL(pKernelGsp) kgspGetBinArchiveGspRmCcGfwProdSigned_DISPATCH(pKernelGsp) +#define kgspGetBinArchiveGspRmFmcGfwDebugSigned(pKernelGsp) kgspGetBinArchiveGspRmFmcGfwDebugSigned_DISPATCH(pKernelGsp) +#define kgspGetBinArchiveGspRmFmcGfwDebugSigned_HAL(pKernelGsp) kgspGetBinArchiveGspRmFmcGfwDebugSigned_DISPATCH(pKernelGsp) +#define kgspGetBinArchiveGspRmFmcGfwProdSigned(pKernelGsp) kgspGetBinArchiveGspRmFmcGfwProdSigned_DISPATCH(pKernelGsp) +#define kgspGetBinArchiveGspRmFmcGfwProdSigned_HAL(pKernelGsp) kgspGetBinArchiveGspRmFmcGfwProdSigned_DISPATCH(pKernelGsp) #define kgspCalculateFbLayout(pGpu, pKernelGsp, pGspFw) kgspCalculateFbLayout_DISPATCH(pGpu, pKernelGsp, pGspFw) #define kgspCalculateFbLayout_HAL(pGpu, pKernelGsp, pGspFw) kgspCalculateFbLayout_DISPATCH(pGpu, pKernelGsp, pGspFw) #define kgspGetNonWprHeapSize(pGpu, pKernelGsp) kgspGetNonWprHeapSize_DISPATCH(pGpu, pKernelGsp) @@ -410,8 +420,10 @@ NV_STATUS __nvoc_objCreate_KernelGsp(KernelGsp**, Dynamic*, NvU32); #define kgspGetBinArchiveBooterLoadUcode_HAL(pKernelGsp) kgspGetBinArchiveBooterLoadUcode_DISPATCH(pKernelGsp) #define kgspGetBinArchiveBooterUnloadUcode(pKernelGsp) kgspGetBinArchiveBooterUnloadUcode_DISPATCH(pKernelGsp) #define kgspGetBinArchiveBooterUnloadUcode_HAL(pKernelGsp) kgspGetBinArchiveBooterUnloadUcode_DISPATCH(pKernelGsp) -#define kgspGetSignatureSectionName(pGpu, pKernelGsp) kgspGetSignatureSectionName_DISPATCH(pGpu, pKernelGsp) -#define kgspGetSignatureSectionName_HAL(pGpu, pKernelGsp) kgspGetSignatureSectionName_DISPATCH(pGpu, pKernelGsp) +#define kgspGetWprHeapSize(pGpu, pKernelGsp) kgspGetWprHeapSize_DISPATCH(pGpu, pKernelGsp) +#define kgspGetWprHeapSize_HAL(pGpu, pKernelGsp) kgspGetWprHeapSize_DISPATCH(pGpu, pKernelGsp) +#define kgspGetSignatureSectionNamePrefix(pGpu, pKernelGsp) kgspGetSignatureSectionNamePrefix_DISPATCH(pGpu, pKernelGsp) +#define kgspGetSignatureSectionNamePrefix_HAL(pGpu, pKernelGsp) kgspGetSignatureSectionNamePrefix_DISPATCH(pGpu, pKernelGsp) #define kgspSetupGspFmcArgs(pGpu, pKernelGsp, pGspFw) kgspSetupGspFmcArgs_DISPATCH(pGpu, pKernelGsp, pGspFw) #define kgspSetupGspFmcArgs_HAL(pGpu, pKernelGsp, pGspFw) kgspSetupGspFmcArgs_DISPATCH(pGpu, pKernelGsp, pGspFw) #define kgspStateDestroy(pGpu, pEngstate) kgspStateDestroy_DISPATCH(pGpu, pEngstate) @@ -437,6 +449,7 @@ NV_STATUS __nvoc_objCreate_KernelGsp(KernelGsp**, Dynamic*, NvU32); #define kgspSetTunableState(pGpu, pEngstate, pTunableState) kgspSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) void kgspProgramLibosBootArgsAddr_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + #ifdef __nvoc_kernel_gsp_h_disabled static inline void kgspProgramLibosBootArgsAddr(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); @@ -449,6 +462,7 @@ static inline void kgspProgramLibosBootArgsAddr(struct OBJGPU *pGpu, struct Kern NV_STATUS kgspSetCmdQueueHead_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 queueIdx, NvU32 value); + #ifdef __nvoc_kernel_gsp_h_disabled static inline NV_STATUS kgspSetCmdQueueHead(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 queueIdx, NvU32 value) { NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); @@ -462,6 +476,7 @@ static inline NV_STATUS kgspSetCmdQueueHead(struct OBJGPU *pGpu, struct KernelGs void kgspHealthCheck_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + #ifdef __nvoc_kernel_gsp_h_disabled static inline void kgspHealthCheck(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); @@ -474,6 +489,7 @@ static inline void kgspHealthCheck(struct OBJGPU *pGpu, struct KernelGsp *pKerne NvU32 kgspService_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + #ifdef __nvoc_kernel_gsp_h_disabled static inline NvU32 kgspService(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); @@ -487,6 +503,7 @@ static inline NvU32 kgspService(struct OBJGPU *pGpu, struct KernelGsp *pKernelGs NV_STATUS kgspWaitForProcessorSuspend_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + #ifdef __nvoc_kernel_gsp_h_disabled static inline NV_STATUS kgspWaitForProcessorSuspend(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); @@ -504,9 +521,9 @@ static inline NV_STATUS kgspConstructEngine_DISPATCH(struct OBJGPU *pGpu, struct return pKernelGsp->__kgspConstructEngine__(pGpu, pKernelGsp, arg0); } -void kgspRegisterIntrService_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, IntrServiceRecord pRecords[155]); +void kgspRegisterIntrService_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, IntrServiceRecord pRecords[163]); -static inline void kgspRegisterIntrService_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, IntrServiceRecord pRecords[155]) { +static inline void kgspRegisterIntrService_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, IntrServiceRecord pRecords[163]) { pKernelGsp->__kgspRegisterIntrService__(pGpu, pKernelGsp, pRecords); } @@ -520,10 +537,6 @@ void kgspConfigureFalcon_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp void kgspConfigureFalcon_GA102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); -static inline void kgspConfigureFalcon_f2d351(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - NV_ASSERT_PRECOMP(0); -} - static inline void kgspConfigureFalcon_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { pKernelGsp->__kgspConfigureFalcon__(pGpu, pKernelGsp); } @@ -532,10 +545,6 @@ NvBool kgspIsDebugModeEnabled_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKern NvBool kgspIsDebugModeEnabled_GA100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); -static inline NvBool kgspIsDebugModeEnabled_108313(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - NV_ASSERT_OR_RETURN_PRECOMP(0, ((NvBool)(0 != 0))); -} - static inline NvBool kgspIsDebugModeEnabled_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { return pKernelGsp->__kgspIsDebugModeEnabled__(pGpu, pKernelGsp); } @@ -544,10 +553,6 @@ NV_STATUS kgspAllocBootArgs_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernel NV_STATUS kgspAllocBootArgs_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); -static inline NV_STATUS kgspAllocBootArgs_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); -} - static inline NV_STATUS kgspAllocBootArgs_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { return pKernelGsp->__kgspAllocBootArgs__(pGpu, pKernelGsp); } @@ -556,10 +561,6 @@ void kgspFreeBootArgs_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); void kgspFreeBootArgs_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); -static inline void kgspFreeBootArgs_f2d351(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - NV_ASSERT_PRECOMP(0); -} - static inline void kgspFreeBootArgs_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { pKernelGsp->__kgspFreeBootArgs__(pGpu, pKernelGsp); } @@ -570,10 +571,6 @@ NV_STATUS kgspBootstrapRiscvOSEarly_GA102(struct OBJGPU *pGpu, struct KernelGsp NV_STATUS kgspBootstrapRiscvOSEarly_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw); -static inline NV_STATUS kgspBootstrapRiscvOSEarly_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw) { - NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); -} - static inline NV_STATUS kgspBootstrapRiscvOSEarly_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw) { return pKernelGsp->__kgspBootstrapRiscvOSEarly__(pGpu, pKernelGsp, pGspFw); } @@ -582,9 +579,7 @@ void kgspGetGspRmBootUcodeStorage_TU102(struct OBJGPU *pGpu, struct KernelGsp *p void kgspGetGspRmBootUcodeStorage_GA102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, BINDATA_STORAGE **ppBinStorageImage, BINDATA_STORAGE **ppBinStorageDesc); -static inline void kgspGetGspRmBootUcodeStorage_f2d351(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, BINDATA_STORAGE **ppBinStorageImage, BINDATA_STORAGE **ppBinStorageDesc) { - NV_ASSERT_PRECOMP(0); -} +void kgspGetGspRmBootUcodeStorage_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, BINDATA_STORAGE **ppBinStorageImage, BINDATA_STORAGE **ppBinStorageDesc); static inline void kgspGetGspRmBootUcodeStorage_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, BINDATA_STORAGE **ppBinStorageImage, BINDATA_STORAGE **ppBinStorageDesc) { pKernelGsp->__kgspGetGspRmBootUcodeStorage__(pGpu, pKernelGsp, ppBinStorageImage, ppBinStorageDesc); @@ -600,42 +595,34 @@ const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmBoot_GH100(struct KernelGsp *pKerne const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmBoot_AD102(struct KernelGsp *pKernelGsp); -static inline const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmBoot_80f438(struct KernelGsp *pKernelGsp) { - NV_ASSERT_OR_RETURN_PRECOMP(0, ((void *)0)); -} - static inline const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmBoot_DISPATCH(struct KernelGsp *pKernelGsp) { return pKernelGsp->__kgspGetBinArchiveGspRmBoot__(pKernelGsp); } -const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmCcGfwDebugSigned_GH100(struct KernelGsp *pKernelGsp); +const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100(struct KernelGsp *pKernelGsp); -static inline const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmCcGfwDebugSigned_80f438(struct KernelGsp *pKernelGsp) { +static inline const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmFmcGfwDebugSigned_80f438(struct KernelGsp *pKernelGsp) { NV_ASSERT_OR_RETURN_PRECOMP(0, ((void *)0)); } -static inline const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmCcGfwDebugSigned_DISPATCH(struct KernelGsp *pKernelGsp) { - return pKernelGsp->__kgspGetBinArchiveGspRmCcGfwDebugSigned__(pKernelGsp); +static inline const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmFmcGfwDebugSigned_DISPATCH(struct KernelGsp *pKernelGsp) { + return pKernelGsp->__kgspGetBinArchiveGspRmFmcGfwDebugSigned__(pKernelGsp); } -const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmCcGfwProdSigned_GH100(struct KernelGsp *pKernelGsp); +const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100(struct KernelGsp *pKernelGsp); -static inline const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmCcGfwProdSigned_80f438(struct KernelGsp *pKernelGsp) { +static inline const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmFmcGfwProdSigned_80f438(struct KernelGsp *pKernelGsp) { NV_ASSERT_OR_RETURN_PRECOMP(0, ((void *)0)); } -static inline const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmCcGfwProdSigned_DISPATCH(struct KernelGsp *pKernelGsp) { - return pKernelGsp->__kgspGetBinArchiveGspRmCcGfwProdSigned__(pKernelGsp); +static inline const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmFmcGfwProdSigned_DISPATCH(struct KernelGsp *pKernelGsp) { + return pKernelGsp->__kgspGetBinArchiveGspRmFmcGfwProdSigned__(pKernelGsp); } NV_STATUS kgspCalculateFbLayout_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw); NV_STATUS kgspCalculateFbLayout_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw); -static inline NV_STATUS kgspCalculateFbLayout_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw) { - NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); -} - static inline NV_STATUS kgspCalculateFbLayout_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw) { return pKernelGsp->__kgspCalculateFbLayout__(pGpu, pKernelGsp, pGspFw); } @@ -648,10 +635,6 @@ static inline NvU32 kgspGetNonWprHeapSize_d505ea(struct OBJGPU *pGpu, struct Ker return 2097152; } -static inline NvU32 kgspGetNonWprHeapSize_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); -} - static inline NvU32 kgspGetNonWprHeapSize_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { return pKernelGsp->__kgspGetNonWprHeapSize__(pGpu, pKernelGsp); } @@ -660,10 +643,6 @@ NV_STATUS kgspExecuteSequencerCommand_TU102(struct OBJGPU *pGpu, struct KernelGs NV_STATUS kgspExecuteSequencerCommand_GA102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 opCode, NvU32 *pPayLoad, NvU32 payloadSize); -static inline NV_STATUS kgspExecuteSequencerCommand_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 opCode, NvU32 *pPayLoad, NvU32 payloadSize) { - NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); -} - static inline NV_STATUS kgspExecuteSequencerCommand_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 opCode, NvU32 *pPayLoad, NvU32 payloadSize) { return pKernelGsp->__kgspExecuteSequencerCommand__(pGpu, pKernelGsp, opCode, pPayLoad, payloadSize); } @@ -674,10 +653,6 @@ static inline NvU32 kgspReadUcodeFuseVersion_b2b553(struct OBJGPU *pGpu, struct NvU32 kgspReadUcodeFuseVersion_GA100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 ucodeId); -static inline NvU32 kgspReadUcodeFuseVersion_474d46(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 ucodeId) { - NV_ASSERT_OR_RETURN_PRECOMP(0, 0); -} - static inline NvU32 kgspReadUcodeFuseVersion_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 ucodeId) { return pKernelGsp->__kgspReadUcodeFuseVersion__(pGpu, pKernelGsp, ucodeId); } @@ -686,20 +661,12 @@ NV_STATUS kgspResetHw_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); NV_STATUS kgspResetHw_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); -static inline NV_STATUS kgspResetHw_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); -} - static inline NV_STATUS kgspResetHw_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { return pKernelGsp->__kgspResetHw__(pGpu, pKernelGsp); } NvBool kgspIsEngineInReset_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); -static inline NvBool kgspIsEngineInReset_108313(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - NV_ASSERT_OR_RETURN_PRECOMP(0, ((NvBool)(0 != 0))); -} - static inline NvBool kgspIsEngineInReset_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { return pKernelGsp->__kgspIsEngineInReset__(pGpu, pKernelGsp); } @@ -710,10 +677,6 @@ static inline NvU32 kgspGetFrtsSize_4a4dee(struct OBJGPU *pGpu, struct KernelGsp return 0; } -static inline NvU32 kgspGetFrtsSize_474d46(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - NV_ASSERT_OR_RETURN_PRECOMP(0, 0); -} - static inline NvU32 kgspGetFrtsSize_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { return pKernelGsp->__kgspGetFrtsSize__(pGpu, pKernelGsp); } @@ -724,10 +687,6 @@ static inline NV_STATUS kgspExtractVbiosFromRom_395e98(struct OBJGPU *pGpu, stru return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS kgspExtractVbiosFromRom_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspVbiosImg **ppVbiosImg) { - NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); -} - static inline NV_STATUS kgspExtractVbiosFromRom_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspVbiosImg **ppVbiosImg) { return pKernelGsp->__kgspExtractVbiosFromRom__(pGpu, pKernelGsp, ppVbiosImg); } @@ -748,10 +707,6 @@ static inline NV_STATUS kgspExecuteFwsecSb_ac1694(struct OBJGPU *pGpu, struct Ke return NV_OK; } -static inline NV_STATUS kgspExecuteFwsecSb_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode *pFwsecUcode) { - NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); -} - static inline NV_STATUS kgspExecuteFwsecSb_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode *pFwsecUcode) { return pKernelGsp->__kgspExecuteFwsecSb__(pGpu, pKernelGsp, pFwsecUcode); } @@ -792,10 +747,6 @@ NV_STATUS kgspWaitForGfwBootOk_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKer NV_STATUS kgspWaitForGfwBootOk_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); -static inline NV_STATUS kgspWaitForGfwBootOk_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); -} - static inline NV_STATUS kgspWaitForGfwBootOk_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { return pKernelGsp->__kgspWaitForGfwBootOk__(pGpu, pKernelGsp); } @@ -836,40 +787,26 @@ static inline const BINDATA_ARCHIVE *kgspGetBinArchiveBooterUnloadUcode_DISPATCH return pKernelGsp->__kgspGetBinArchiveBooterUnloadUcode__(pKernelGsp); } -static inline const char *kgspGetSignatureSectionName_63b8e2(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - return ".fwsignature_ga100"; +static inline NvU64 kgspGetWprHeapSize_e77d51(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return (64 * 1024 * 1024); } -static inline const char *kgspGetSignatureSectionName_e46f5b(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - return ".fwsignature_ga10x"; +static inline NvU64 kgspGetWprHeapSize_38f3bc(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return (80 * 1024 * 1024); } -static inline const char *kgspGetSignatureSectionName_cbc19d(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - return ".fwsignature_tu10x"; +static inline NvU64 kgspGetWprHeapSize_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return pKernelGsp->__kgspGetWprHeapSize__(pGpu, pKernelGsp); } -static inline const char *kgspGetSignatureSectionName_ab7237(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - return ".fwsignature_tu11x"; +const char *kgspGetSignatureSectionNamePrefix_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + +static inline const char *kgspGetSignatureSectionNamePrefix_789efb(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return ".fwsignature_"; } -static inline const char *kgspGetSignatureSectionName_20361c(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - return ".fwsignature_ad10x"; -} - -static inline const char *kgspGetSignatureSectionName_5f1986(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - return ".fwsignature_gh100"; -} - -static inline const char *kgspGetSignatureSectionName_9e2234(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - return ((void *)0); -} - -static inline const char *kgspGetSignatureSectionName_80f438(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - NV_ASSERT_OR_RETURN_PRECOMP(0, ((void *)0)); -} - -static inline const char *kgspGetSignatureSectionName_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - return pKernelGsp->__kgspGetSignatureSectionName__(pGpu, pKernelGsp); +static inline const char *kgspGetSignatureSectionNamePrefix_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return pKernelGsp->__kgspGetSignatureSectionNamePrefix__(pGpu, pKernelGsp); } NV_STATUS kgspSetupGspFmcArgs_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw); @@ -967,8 +904,10 @@ static inline NV_STATUS kgspSetTunableState_DISPATCH(POBJGPU pGpu, struct Kernel } void kgspDestruct_IMPL(struct KernelGsp *pKernelGsp); + #define __nvoc_kgspDestruct(pKernelGsp) kgspDestruct_IMPL(pKernelGsp) void kgspPopulateGspRmInitArgs_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_SR_INIT_ARGUMENTS *pGspSrInitArgs); + #ifdef __nvoc_kernel_gsp_h_disabled static inline void kgspPopulateGspRmInitArgs(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_SR_INIT_ARGUMENTS *pGspSrInitArgs) { NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); @@ -978,6 +917,7 @@ static inline void kgspPopulateGspRmInitArgs(struct OBJGPU *pGpu, struct KernelG #endif //__nvoc_kernel_gsp_h_disabled NV_STATUS kgspInitRm_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw); + #ifdef __nvoc_kernel_gsp_h_disabled static inline NV_STATUS kgspInitRm(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw) { NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); @@ -988,6 +928,7 @@ static inline NV_STATUS kgspInitRm(struct OBJGPU *pGpu, struct KernelGsp *pKerne #endif //__nvoc_kernel_gsp_h_disabled NV_STATUS kgspUnloadRm_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + #ifdef __nvoc_kernel_gsp_h_disabled static inline NV_STATUS kgspUnloadRm(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); @@ -998,6 +939,7 @@ static inline NV_STATUS kgspUnloadRm(struct OBJGPU *pGpu, struct KernelGsp *pKer #endif //__nvoc_kernel_gsp_h_disabled NV_STATUS kgspPrepareBootBinaryImage_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + #ifdef __nvoc_kernel_gsp_h_disabled static inline NV_STATUS kgspPrepareBootBinaryImage(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); @@ -1008,6 +950,7 @@ static inline NV_STATUS kgspPrepareBootBinaryImage(struct OBJGPU *pGpu, struct K #endif //__nvoc_kernel_gsp_h_disabled void kgspSetupLibosInitArgs_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + #ifdef __nvoc_kernel_gsp_h_disabled static inline void kgspSetupLibosInitArgs(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); @@ -1017,6 +960,7 @@ static inline void kgspSetupLibosInitArgs(struct OBJGPU *pGpu, struct KernelGsp #endif //__nvoc_kernel_gsp_h_disabled void kgspRpcRecvEvents_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + #ifdef __nvoc_kernel_gsp_h_disabled static inline void kgspRpcRecvEvents(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); @@ -1026,6 +970,7 @@ static inline void kgspRpcRecvEvents(struct OBJGPU *pGpu, struct KernelGsp *pKer #endif //__nvoc_kernel_gsp_h_disabled NV_STATUS kgspWaitForRmInitDone_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + #ifdef __nvoc_kernel_gsp_h_disabled static inline NV_STATUS kgspWaitForRmInitDone(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); @@ -1036,6 +981,7 @@ static inline NV_STATUS kgspWaitForRmInitDone(struct OBJGPU *pGpu, struct Kernel #endif //__nvoc_kernel_gsp_h_disabled NV_STATUS kgspInitLogging_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw); + #ifdef __nvoc_kernel_gsp_h_disabled static inline NV_STATUS kgspInitLogging(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw) { NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); @@ -1046,6 +992,7 @@ static inline NV_STATUS kgspInitLogging(struct OBJGPU *pGpu, struct KernelGsp *p #endif //__nvoc_kernel_gsp_h_disabled NV_STATUS kgspStartLogPolling_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + #ifdef __nvoc_kernel_gsp_h_disabled static inline NV_STATUS kgspStartLogPolling(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); @@ -1056,6 +1003,7 @@ static inline NV_STATUS kgspStartLogPolling(struct OBJGPU *pGpu, struct KernelGs #endif //__nvoc_kernel_gsp_h_disabled void kgspDumpGspLogs_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvBool arg0); + #ifdef __nvoc_kernel_gsp_h_disabled static inline void kgspDumpGspLogs(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvBool arg0) { NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); @@ -1065,6 +1013,7 @@ static inline void kgspDumpGspLogs(struct OBJGPU *pGpu, struct KernelGsp *pKerne #endif //__nvoc_kernel_gsp_h_disabled NV_STATUS kgspExecuteSequencerBuffer_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, void *pRunCpuSeqParams); + #ifdef __nvoc_kernel_gsp_h_disabled static inline NV_STATUS kgspExecuteSequencerBuffer(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, void *pRunCpuSeqParams) { NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); @@ -1075,6 +1024,7 @@ static inline NV_STATUS kgspExecuteSequencerBuffer(struct OBJGPU *pGpu, struct K #endif //__nvoc_kernel_gsp_h_disabled NV_STATUS kgspParseFwsecUcodeFromVbiosImg_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const KernelGspVbiosImg *const pVbiosImg, KernelGspFlcnUcode **ppFwsecUcode); + #ifdef __nvoc_kernel_gsp_h_disabled static inline NV_STATUS kgspParseFwsecUcodeFromVbiosImg(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const KernelGspVbiosImg *const pVbiosImg, KernelGspFlcnUcode **ppFwsecUcode) { NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); @@ -1085,6 +1035,7 @@ static inline NV_STATUS kgspParseFwsecUcodeFromVbiosImg(struct OBJGPU *pGpu, str #endif //__nvoc_kernel_gsp_h_disabled NV_STATUS kgspAllocateBooterLoadUcodeImage_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode **ppBooterLoadUcode); + #ifdef __nvoc_kernel_gsp_h_disabled static inline NV_STATUS kgspAllocateBooterLoadUcodeImage(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode **ppBooterLoadUcode) { NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); @@ -1095,6 +1046,7 @@ static inline NV_STATUS kgspAllocateBooterLoadUcodeImage(struct OBJGPU *pGpu, st #endif //__nvoc_kernel_gsp_h_disabled NV_STATUS kgspAllocateBooterUnloadUcodeImage_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode **ppBooterUnloadUcode); + #ifdef __nvoc_kernel_gsp_h_disabled static inline NV_STATUS kgspAllocateBooterUnloadUcodeImage(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode **ppBooterUnloadUcode) { NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); diff --git a/src/nvidia/generated/g_kernel_head_nvoc.c b/src/nvidia/generated/g_kernel_head_nvoc.c index 0390b7d35..54ff23e8b 100644 --- a/src/nvidia/generated/g_kernel_head_nvoc.c +++ b/src/nvidia/generated/g_kernel_head_nvoc.c @@ -116,72 +116,54 @@ static void __nvoc_init_funcTable_KernelHead_1(KernelHead *pThis, RmHalspecOwner // Hal function -- kheadProcessVblankCallbacks if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kheadProcessVblankCallbacks__ = &kheadProcessVblankCallbacks_IMPL; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kheadProcessVblankCallbacks__ = &kheadProcessVblankCallbacks_e426af; } } - else if (0) - { - } // Hal function -- kheadResetPendingVblank if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kheadResetPendingVblank__ = &kheadResetPendingVblank_v04_00_KERNEL; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kheadResetPendingVblank__ = &kheadResetPendingVblank_e426af; } } - else if (0) - { - } - else if (0) - { - } // Hal function -- kheadResetPendingVblankForKernel if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { - pThis->__kheadResetPendingVblankForKernel__ = &kheadResetPendingVblankForKernel_v04_00_KERNEL; + pThis->__kheadResetPendingVblankForKernel__ = &kheadResetPendingVblankForKernel_1ad688; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kheadResetPendingVblankForKernel__ = &kheadResetPendingVblankForKernel_e426af; } } - else if (0) - { - } - else if (0) - { - } // Hal function -- kheadReadPendingVblank if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kheadReadPendingVblank__ = &kheadReadPendingVblank_v04_00_KERNEL; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kheadReadPendingVblank__ = &kheadReadPendingVblank_92bfc3; } } - else if (0) - { - } } void __nvoc_init_funcTable_KernelHead(KernelHead *pThis, RmHalspecOwner *pRmhalspecowner) { diff --git a/src/nvidia/generated/g_kernel_head_nvoc.h b/src/nvidia/generated/g_kernel_head_nvoc.h index 4ebe31e4f..ca4158faa 100644 --- a/src/nvidia/generated/g_kernel_head_nvoc.h +++ b/src/nvidia/generated/g_kernel_head_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -66,7 +66,17 @@ struct __nvoc_inner_struc_KernelHead_1__ { struct { VBLANKCALLBACK *pListLL; VBLANKCALLBACK *pListNL; + VBLANKCALLBACK gatherInfo; } Callback; + struct { + struct { + NvU64 Current; + NvU64 Last; + NvU32 Average; + } Time; + NvU32 Count; + NvU32 Timeout; + } Info; NvU32 IntrState; }; @@ -116,12 +126,13 @@ NV_STATUS __nvoc_objCreate_KernelHead(KernelHead**, Dynamic*, NvU32); #define kheadProcessVblankCallbacks_HAL(pGpu, pKernelHead, arg0) kheadProcessVblankCallbacks_DISPATCH(pGpu, pKernelHead, arg0) #define kheadResetPendingVblank(pGpu, pKhead, arg0) kheadResetPendingVblank_DISPATCH(pGpu, pKhead, arg0) #define kheadResetPendingVblank_HAL(pGpu, pKhead, arg0) kheadResetPendingVblank_DISPATCH(pGpu, pKhead, arg0) -#define kheadResetPendingVblankForKernel(pGpu, pKhead, arg0) kheadResetPendingVblankForKernel_DISPATCH(pGpu, pKhead, arg0) -#define kheadResetPendingVblankForKernel_HAL(pGpu, pKhead, arg0) kheadResetPendingVblankForKernel_DISPATCH(pGpu, pKhead, arg0) +#define kheadResetPendingVblankForKernel(pGpu, pKhead, pThreadState) kheadResetPendingVblankForKernel_DISPATCH(pGpu, pKhead, pThreadState) +#define kheadResetPendingVblankForKernel_HAL(pGpu, pKhead, pThreadState) kheadResetPendingVblankForKernel_DISPATCH(pGpu, pKhead, pThreadState) #define kheadReadPendingVblank(pGpu, pKernelHead, intr) kheadReadPendingVblank_DISPATCH(pGpu, pKernelHead, intr) #define kheadReadPendingVblank_HAL(pGpu, pKernelHead, intr) kheadReadPendingVblank_DISPATCH(pGpu, pKernelHead, intr) NvU32 kheadGetVblankTotalCounter_IMPL(struct KernelHead *pKernelHead); + #ifdef __nvoc_kernel_head_h_disabled static inline NvU32 kheadGetVblankTotalCounter(struct KernelHead *pKernelHead) { NV_ASSERT_FAILED_PRECOMP("KernelHead was disabled!"); @@ -135,6 +146,7 @@ static inline NvU32 kheadGetVblankTotalCounter(struct KernelHead *pKernelHead) { void kheadSetVblankTotalCounter_IMPL(struct KernelHead *pKernelHead, NvU32 arg0); + #ifdef __nvoc_kernel_head_h_disabled static inline void kheadSetVblankTotalCounter(struct KernelHead *pKernelHead, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("KernelHead was disabled!"); @@ -147,6 +159,7 @@ static inline void kheadSetVblankTotalCounter(struct KernelHead *pKernelHead, Nv NvU32 kheadGetVblankLowLatencyCounter_IMPL(struct KernelHead *pKernelHead); + #ifdef __nvoc_kernel_head_h_disabled static inline NvU32 kheadGetVblankLowLatencyCounter(struct KernelHead *pKernelHead) { NV_ASSERT_FAILED_PRECOMP("KernelHead was disabled!"); @@ -160,6 +173,7 @@ static inline NvU32 kheadGetVblankLowLatencyCounter(struct KernelHead *pKernelHe void kheadSetVblankLowLatencyCounter_IMPL(struct KernelHead *pKernelHead, NvU32 arg0); + #ifdef __nvoc_kernel_head_h_disabled static inline void kheadSetVblankLowLatencyCounter(struct KernelHead *pKernelHead, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("KernelHead was disabled!"); @@ -174,6 +188,7 @@ static inline NvU32 kheadGetVblankNormLatencyCounter_46f6a7(struct KernelHead *p return NV_ERR_NOT_SUPPORTED; } + #ifdef __nvoc_kernel_head_h_disabled static inline NvU32 kheadGetVblankNormLatencyCounter(struct KernelHead *pKernelHead) { NV_ASSERT_FAILED_PRECOMP("KernelHead was disabled!"); @@ -189,6 +204,7 @@ static inline void kheadSetVblankNormLatencyCounter_b3696a(struct KernelHead *pK return; } + #ifdef __nvoc_kernel_head_h_disabled static inline void kheadSetVblankNormLatencyCounter(struct KernelHead *pKernelHead, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("KernelHead was disabled!"); @@ -203,6 +219,7 @@ static inline NvBool kheadReadVblankIntrEnable_491d52(struct OBJGPU *pGpu, struc return ((NvBool)(0 != 0)); } + #ifdef __nvoc_kernel_head_h_disabled static inline NvBool kheadReadVblankIntrEnable(struct OBJGPU *pGpu, struct KernelHead *pKernelHead) { NV_ASSERT_FAILED_PRECOMP("KernelHead was disabled!"); @@ -218,6 +235,7 @@ static inline NvBool kheadGetDisplayInitialized_491d52(struct OBJGPU *pGpu, stru return ((NvBool)(0 != 0)); } + #ifdef __nvoc_kernel_head_h_disabled static inline NvBool kheadGetDisplayInitialized(struct OBJGPU *pGpu, struct KernelHead *pKernelHead) { NV_ASSERT_FAILED_PRECOMP("KernelHead was disabled!"); @@ -233,6 +251,7 @@ static inline void kheadWriteVblankIntrEnable_b3696a(struct OBJGPU *pGpu, struct return; } + #ifdef __nvoc_kernel_head_h_disabled static inline void kheadWriteVblankIntrEnable(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvBool arg0) { NV_ASSERT_FAILED_PRECOMP("KernelHead was disabled!"); @@ -243,6 +262,35 @@ static inline void kheadWriteVblankIntrEnable(struct OBJGPU *pGpu, struct Kernel #define kheadWriteVblankIntrEnable_HAL(pGpu, pKernelHead, arg0) kheadWriteVblankIntrEnable(pGpu, pKernelHead, arg0) +void kheadSetVblankGatherInfo_IMPL(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvBool arg0); + + +#ifdef __nvoc_kernel_head_h_disabled +static inline void kheadSetVblankGatherInfo(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvBool arg0) { + NV_ASSERT_FAILED_PRECOMP("KernelHead was disabled!"); +} +#else //__nvoc_kernel_head_h_disabled +#define kheadSetVblankGatherInfo(pGpu, pKernelHead, arg0) kheadSetVblankGatherInfo_IMPL(pGpu, pKernelHead, arg0) +#endif //__nvoc_kernel_head_h_disabled + +#define kheadSetVblankGatherInfo_HAL(pGpu, pKernelHead, arg0) kheadSetVblankGatherInfo(pGpu, pKernelHead, arg0) + +NvU32 kheadTickVblankInfo_IMPL(struct OBJGPU *pGpu, struct KernelHead *pKernelHead); + + +#ifdef __nvoc_kernel_head_h_disabled +static inline NvU32 kheadTickVblankInfo(struct OBJGPU *pGpu, struct KernelHead *pKernelHead) { + NV_ASSERT_FAILED_PRECOMP("KernelHead was disabled!"); + return 0; +} +#else //__nvoc_kernel_head_h_disabled +#define kheadTickVblankInfo(pGpu, pKernelHead) kheadTickVblankInfo_IMPL(pGpu, pKernelHead) +#endif //__nvoc_kernel_head_h_disabled + +#define kheadTickVblankInfo_HAL(pGpu, pKernelHead) kheadTickVblankInfo(pGpu, pKernelHead) + +void kheadProcessVblankCallbacks_IMPL(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvU32 arg0); + static inline void kheadProcessVblankCallbacks_e426af(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvU32 arg0) { NV_ASSERT_PRECOMP(0); return; @@ -263,19 +311,17 @@ static inline void kheadResetPendingVblank_DISPATCH(struct OBJGPU *pGpu, struct pKhead->__kheadResetPendingVblank__(pGpu, pKhead, arg0); } -void kheadResetPendingVblankForKernel_v04_00_KERNEL(struct OBJGPU *pGpu, struct KernelHead *pKhead, THREAD_STATE_NODE *arg0); +static inline void kheadResetPendingVblankForKernel_1ad688(struct OBJGPU *pGpu, struct KernelHead *pKhead, THREAD_STATE_NODE *pThreadState) { + kheadResetPendingVblank(pGpu, pKhead, pThreadState); +} -static inline void kheadResetPendingVblankForKernel_e426af(struct OBJGPU *pGpu, struct KernelHead *pKhead, THREAD_STATE_NODE *arg0) { +static inline void kheadResetPendingVblankForKernel_e426af(struct OBJGPU *pGpu, struct KernelHead *pKhead, THREAD_STATE_NODE *pThreadState) { NV_ASSERT_PRECOMP(0); return; } -static inline void kheadResetPendingVblankForKernel_b3696a(struct OBJGPU *pGpu, struct KernelHead *pKhead, THREAD_STATE_NODE *arg0) { - return; -} - -static inline void kheadResetPendingVblankForKernel_DISPATCH(struct OBJGPU *pGpu, struct KernelHead *pKhead, THREAD_STATE_NODE *arg0) { - pKhead->__kheadResetPendingVblankForKernel__(pGpu, pKhead, arg0); +static inline void kheadResetPendingVblankForKernel_DISPATCH(struct OBJGPU *pGpu, struct KernelHead *pKhead, THREAD_STATE_NODE *pThreadState) { + pKhead->__kheadResetPendingVblankForKernel__(pGpu, pKhead, pThreadState); } NvU32 kheadReadPendingVblank_v04_00_KERNEL(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvU32 intr); @@ -290,8 +336,10 @@ static inline NvU32 kheadReadPendingVblank_DISPATCH(struct OBJGPU *pGpu, struct } NV_STATUS kheadConstruct_IMPL(struct KernelHead *arg_pKernelHead); + #define __nvoc_kheadConstruct(arg_pKernelHead) kheadConstruct_IMPL(arg_pKernelHead) void kheadAddVblankCallback_IMPL(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, VBLANKCALLBACK *arg0); + #ifdef __nvoc_kernel_head_h_disabled static inline void kheadAddVblankCallback(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, VBLANKCALLBACK *arg0) { NV_ASSERT_FAILED_PRECOMP("KernelHead was disabled!"); @@ -301,6 +349,7 @@ static inline void kheadAddVblankCallback(struct OBJGPU *pGpu, struct KernelHead #endif //__nvoc_kernel_head_h_disabled void kheadDeleteVblankCallback_IMPL(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, VBLANKCALLBACK *arg0); + #ifdef __nvoc_kernel_head_h_disabled static inline void kheadDeleteVblankCallback(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, VBLANKCALLBACK *arg0) { NV_ASSERT_FAILED_PRECOMP("KernelHead was disabled!"); @@ -310,6 +359,7 @@ static inline void kheadDeleteVblankCallback(struct OBJGPU *pGpu, struct KernelH #endif //__nvoc_kernel_head_h_disabled NvU32 kheadCheckVblankCallbacksQueued_IMPL(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvU32 arg0, NvU32 *arg1); + #ifdef __nvoc_kernel_head_h_disabled static inline NvU32 kheadCheckVblankCallbacksQueued(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvU32 arg0, NvU32 *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelHead was disabled!"); @@ -320,6 +370,7 @@ static inline NvU32 kheadCheckVblankCallbacksQueued(struct OBJGPU *pGpu, struct #endif //__nvoc_kernel_head_h_disabled NvU32 kheadReadVblankIntrState_IMPL(struct OBJGPU *pGpu, struct KernelHead *pKernelHead); + #ifdef __nvoc_kernel_head_h_disabled static inline NvU32 kheadReadVblankIntrState(struct OBJGPU *pGpu, struct KernelHead *pKernelHead) { NV_ASSERT_FAILED_PRECOMP("KernelHead was disabled!"); @@ -330,6 +381,7 @@ static inline NvU32 kheadReadVblankIntrState(struct OBJGPU *pGpu, struct KernelH #endif //__nvoc_kernel_head_h_disabled void kheadWriteVblankIntrState_IMPL(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvU32 arg0); + #ifdef __nvoc_kernel_head_h_disabled static inline void kheadWriteVblankIntrState(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("KernelHead was disabled!"); @@ -341,8 +393,6 @@ static inline void kheadWriteVblankIntrState(struct OBJGPU *pGpu, struct KernelH #undef PRIVATE_FIELD -void kheadProcessVblankCallbacks_IMPL(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvU32 state); - #endif // KERNEL_HEAD_H #ifdef __cplusplus diff --git a/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.c b/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.c new file mode 100644 index 000000000..e55fae9ee --- /dev/null +++ b/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.c @@ -0,0 +1,730 @@ +#define NVOC_KERNEL_HOSTVGPUDEVICEAPI_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_kernel_hostvgpudeviceapi_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0xe32156 = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelHostVgpuDeviceShr; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RsShared; + +void __nvoc_init_KernelHostVgpuDeviceShr(KernelHostVgpuDeviceShr*); +void __nvoc_init_funcTable_KernelHostVgpuDeviceShr(KernelHostVgpuDeviceShr*); +NV_STATUS __nvoc_ctor_KernelHostVgpuDeviceShr(KernelHostVgpuDeviceShr*); +void __nvoc_init_dataField_KernelHostVgpuDeviceShr(KernelHostVgpuDeviceShr*); +void __nvoc_dtor_KernelHostVgpuDeviceShr(KernelHostVgpuDeviceShr*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelHostVgpuDeviceShr; + +static const struct NVOC_RTTI __nvoc_rtti_KernelHostVgpuDeviceShr_KernelHostVgpuDeviceShr = { + /*pClassDef=*/ &__nvoc_class_def_KernelHostVgpuDeviceShr, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_KernelHostVgpuDeviceShr, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_KernelHostVgpuDeviceShr_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(KernelHostVgpuDeviceShr, __nvoc_base_RsShared.__nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_KernelHostVgpuDeviceShr_RsShared = { + /*pClassDef=*/ &__nvoc_class_def_RsShared, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(KernelHostVgpuDeviceShr, __nvoc_base_RsShared), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_KernelHostVgpuDeviceShr = { + /*numRelatives=*/ 3, + /*relatives=*/ { + &__nvoc_rtti_KernelHostVgpuDeviceShr_KernelHostVgpuDeviceShr, + &__nvoc_rtti_KernelHostVgpuDeviceShr_RsShared, + &__nvoc_rtti_KernelHostVgpuDeviceShr_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_KernelHostVgpuDeviceShr = +{ + /*classInfo=*/ { + /*size=*/ sizeof(KernelHostVgpuDeviceShr), + /*classId=*/ classId(KernelHostVgpuDeviceShr), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "KernelHostVgpuDeviceShr", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_KernelHostVgpuDeviceShr, + /*pCastInfo=*/ &__nvoc_castinfo_KernelHostVgpuDeviceShr, + /*pExportInfo=*/ &__nvoc_export_info_KernelHostVgpuDeviceShr +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelHostVgpuDeviceShr = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_RsShared(RsShared*); +void __nvoc_dtor_KernelHostVgpuDeviceShr(KernelHostVgpuDeviceShr *pThis) { + __nvoc_kernelhostvgpudeviceshrDestruct(pThis); + __nvoc_dtor_RsShared(&pThis->__nvoc_base_RsShared); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_KernelHostVgpuDeviceShr(KernelHostVgpuDeviceShr *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_RsShared(RsShared* ); +NV_STATUS __nvoc_ctor_KernelHostVgpuDeviceShr(KernelHostVgpuDeviceShr *pThis) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_RsShared(&pThis->__nvoc_base_RsShared); + if (status != NV_OK) goto __nvoc_ctor_KernelHostVgpuDeviceShr_fail_RsShared; + __nvoc_init_dataField_KernelHostVgpuDeviceShr(pThis); + + status = __nvoc_kernelhostvgpudeviceshrConstruct(pThis); + if (status != NV_OK) goto __nvoc_ctor_KernelHostVgpuDeviceShr_fail__init; + goto __nvoc_ctor_KernelHostVgpuDeviceShr_exit; // Success + +__nvoc_ctor_KernelHostVgpuDeviceShr_fail__init: + __nvoc_dtor_RsShared(&pThis->__nvoc_base_RsShared); +__nvoc_ctor_KernelHostVgpuDeviceShr_fail_RsShared: +__nvoc_ctor_KernelHostVgpuDeviceShr_exit: + + return status; +} + +static void __nvoc_init_funcTable_KernelHostVgpuDeviceShr_1(KernelHostVgpuDeviceShr *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_funcTable_KernelHostVgpuDeviceShr(KernelHostVgpuDeviceShr *pThis) { + __nvoc_init_funcTable_KernelHostVgpuDeviceShr_1(pThis); +} + +void __nvoc_init_RsShared(RsShared*); +void __nvoc_init_KernelHostVgpuDeviceShr(KernelHostVgpuDeviceShr *pThis) { + pThis->__nvoc_pbase_KernelHostVgpuDeviceShr = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_RsShared.__nvoc_base_Object; + pThis->__nvoc_pbase_RsShared = &pThis->__nvoc_base_RsShared; + __nvoc_init_RsShared(&pThis->__nvoc_base_RsShared); + __nvoc_init_funcTable_KernelHostVgpuDeviceShr(pThis); +} + +NV_STATUS __nvoc_objCreate_KernelHostVgpuDeviceShr(KernelHostVgpuDeviceShr **ppThis, Dynamic *pParent, NvU32 createFlags) { + NV_STATUS status; + Object *pParentObj; + KernelHostVgpuDeviceShr *pThis; + + pThis = portMemAllocNonPaged(sizeof(KernelHostVgpuDeviceShr)); + if (pThis == NULL) return NV_ERR_NO_MEMORY; + + portMemSet(pThis, 0, sizeof(KernelHostVgpuDeviceShr)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelHostVgpuDeviceShr); + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_RsShared.__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_RsShared.__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_KernelHostVgpuDeviceShr(pThis); + status = __nvoc_ctor_KernelHostVgpuDeviceShr(pThis); + if (status != NV_OK) goto __nvoc_objCreate_KernelHostVgpuDeviceShr_cleanup; + + *ppThis = pThis; + return NV_OK; + +__nvoc_objCreate_KernelHostVgpuDeviceShr_cleanup: + // do not call destructors here since the constructor already called them + portMemFree(pThis); + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_KernelHostVgpuDeviceShr(KernelHostVgpuDeviceShr **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + + status = __nvoc_objCreate_KernelHostVgpuDeviceShr(ppThis, pParent, createFlags); + + return status; +} + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0xb12d7d = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelHostVgpuDeviceApi; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RsResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResourceCommon; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_GpuResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_INotifier; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Notifier; + +void __nvoc_init_KernelHostVgpuDeviceApi(KernelHostVgpuDeviceApi*); +void __nvoc_init_funcTable_KernelHostVgpuDeviceApi(KernelHostVgpuDeviceApi*); +NV_STATUS __nvoc_ctor_KernelHostVgpuDeviceApi(KernelHostVgpuDeviceApi*, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +void __nvoc_init_dataField_KernelHostVgpuDeviceApi(KernelHostVgpuDeviceApi*); +void __nvoc_dtor_KernelHostVgpuDeviceApi(KernelHostVgpuDeviceApi*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelHostVgpuDeviceApi; + +static const struct NVOC_RTTI __nvoc_rtti_KernelHostVgpuDeviceApi_KernelHostVgpuDeviceApi = { + /*pClassDef=*/ &__nvoc_class_def_KernelHostVgpuDeviceApi, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_KernelHostVgpuDeviceApi, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_KernelHostVgpuDeviceApi_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(KernelHostVgpuDeviceApi, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_KernelHostVgpuDeviceApi_RsResource = { + /*pClassDef=*/ &__nvoc_class_def_RsResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(KernelHostVgpuDeviceApi, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_KernelHostVgpuDeviceApi_RmResourceCommon = { + /*pClassDef=*/ &__nvoc_class_def_RmResourceCommon, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(KernelHostVgpuDeviceApi, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon), +}; + +static const struct NVOC_RTTI __nvoc_rtti_KernelHostVgpuDeviceApi_RmResource = { + /*pClassDef=*/ &__nvoc_class_def_RmResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(KernelHostVgpuDeviceApi, __nvoc_base_GpuResource.__nvoc_base_RmResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_KernelHostVgpuDeviceApi_GpuResource = { + /*pClassDef=*/ &__nvoc_class_def_GpuResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(KernelHostVgpuDeviceApi, __nvoc_base_GpuResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_KernelHostVgpuDeviceApi_INotifier = { + /*pClassDef=*/ &__nvoc_class_def_INotifier, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(KernelHostVgpuDeviceApi, __nvoc_base_Notifier.__nvoc_base_INotifier), +}; + +static const struct NVOC_RTTI __nvoc_rtti_KernelHostVgpuDeviceApi_Notifier = { + /*pClassDef=*/ &__nvoc_class_def_Notifier, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(KernelHostVgpuDeviceApi, __nvoc_base_Notifier), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_KernelHostVgpuDeviceApi = { + /*numRelatives=*/ 8, + /*relatives=*/ { + &__nvoc_rtti_KernelHostVgpuDeviceApi_KernelHostVgpuDeviceApi, + &__nvoc_rtti_KernelHostVgpuDeviceApi_Notifier, + &__nvoc_rtti_KernelHostVgpuDeviceApi_INotifier, + &__nvoc_rtti_KernelHostVgpuDeviceApi_GpuResource, + &__nvoc_rtti_KernelHostVgpuDeviceApi_RmResource, + &__nvoc_rtti_KernelHostVgpuDeviceApi_RmResourceCommon, + &__nvoc_rtti_KernelHostVgpuDeviceApi_RsResource, + &__nvoc_rtti_KernelHostVgpuDeviceApi_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_KernelHostVgpuDeviceApi = +{ + /*classInfo=*/ { + /*size=*/ sizeof(KernelHostVgpuDeviceApi), + /*classId=*/ classId(KernelHostVgpuDeviceApi), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "KernelHostVgpuDeviceApi", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_KernelHostVgpuDeviceApi, + /*pCastInfo=*/ &__nvoc_castinfo_KernelHostVgpuDeviceApi, + /*pExportInfo=*/ &__nvoc_export_info_KernelHostVgpuDeviceApi +}; + +static NvBool __nvoc_thunk_KernelHostVgpuDeviceApi_resCanCopy(struct RsResource *pKernelHostVgpuDeviceApi) { + return kernelhostvgpudeviceapiCanCopy((struct KernelHostVgpuDeviceApi *)(((unsigned char *)pKernelHostVgpuDeviceApi) - __nvoc_rtti_KernelHostVgpuDeviceApi_RsResource.offset)); +} + +static NvBool __nvoc_thunk_GpuResource_kernelhostvgpudeviceapiShareCallback(struct KernelHostVgpuDeviceApi *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RsResource_kernelhostvgpudeviceapiMapTo(struct KernelHostVgpuDeviceApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Notifier_kernelhostvgpudeviceapiGetOrAllocNotifShare(struct KernelHostVgpuDeviceApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { + return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelHostVgpuDeviceApi_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); +} + +static NV_STATUS __nvoc_thunk_RmResource_kernelhostvgpudeviceapiCheckMemInterUnmap(struct KernelHostVgpuDeviceApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_GpuResource_kernelhostvgpudeviceapiGetMapAddrSpace(struct KernelHostVgpuDeviceApi *pGpuResource, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static void __nvoc_thunk_Notifier_kernelhostvgpudeviceapiSetNotificationShare(struct KernelHostVgpuDeviceApi *pNotifier, struct NotifShare *pNotifShare) { + notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelHostVgpuDeviceApi_Notifier.offset), pNotifShare); +} + +static NvU32 __nvoc_thunk_RsResource_kernelhostvgpudeviceapiGetRefCount(struct KernelHostVgpuDeviceApi *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_kernelhostvgpudeviceapiAddAdditionalDependants(struct RsClient *pClient, struct KernelHostVgpuDeviceApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_kernelhostvgpudeviceapiControl_Prologue(struct KernelHostVgpuDeviceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_kernelhostvgpudeviceapiGetRegBaseOffsetAndSize(struct KernelHostVgpuDeviceApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NV_STATUS __nvoc_thunk_GpuResource_kernelhostvgpudeviceapiInternalControlForward(struct KernelHostVgpuDeviceApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_kernelhostvgpudeviceapiUnmapFrom(struct KernelHostVgpuDeviceApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_kernelhostvgpudeviceapiControl_Epilogue(struct KernelHostVgpuDeviceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_kernelhostvgpudeviceapiControlLookup(struct KernelHostVgpuDeviceApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RsResource.offset), pParams, ppEntry); +} + +static NvHandle __nvoc_thunk_GpuResource_kernelhostvgpudeviceapiGetInternalObjectHandle(struct KernelHostVgpuDeviceApi *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_GpuResource.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_kernelhostvgpudeviceapiControl(struct KernelHostVgpuDeviceApi *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_GpuResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_kernelhostvgpudeviceapiUnmap(struct KernelHostVgpuDeviceApi *pGpuResource, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_GpuResource.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_RmResource_kernelhostvgpudeviceapiGetMemInterMapParams(struct KernelHostVgpuDeviceApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_kernelhostvgpudeviceapiGetMemoryMappingDescriptor(struct KernelHostVgpuDeviceApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RmResource.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_kernelhostvgpudeviceapiControlFilter(struct KernelHostVgpuDeviceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_Notifier_kernelhostvgpudeviceapiUnregisterEvent(struct KernelHostVgpuDeviceApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { + return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelHostVgpuDeviceApi_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); +} + +static void __nvoc_thunk_RsResource_kernelhostvgpudeviceapiPreDestruct(struct KernelHostVgpuDeviceApi *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_kernelhostvgpudeviceapiIsDuplicate(struct KernelHostVgpuDeviceApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RsResource.offset), hMemory, pDuplicate); +} + +static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_kernelhostvgpudeviceapiGetNotificationListPtr(struct KernelHostVgpuDeviceApi *pNotifier) { + return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelHostVgpuDeviceApi_Notifier.offset)); +} + +static struct NotifShare *__nvoc_thunk_Notifier_kernelhostvgpudeviceapiGetNotificationShare(struct KernelHostVgpuDeviceApi *pNotifier) { + return notifyGetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelHostVgpuDeviceApi_Notifier.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_kernelhostvgpudeviceapiMap(struct KernelHostVgpuDeviceApi *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { + return gpuresMap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_GpuResource.offset), pCallContext, pParams, pCpuMapping); +} + +static NvBool __nvoc_thunk_RmResource_kernelhostvgpudeviceapiAccessCallback(struct KernelHostVgpuDeviceApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RmResource.offset), pInvokingClient, pAllocParams, accessRight); +} + +#if !defined(NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG) +#define NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(x) (0) +#endif + +static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelHostVgpuDeviceApi[] = +{ + { /* [0] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) kernelhostvgpudeviceapiCtrlCmdSetVgpuDeviceInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa0840101u, + /*paramSize=*/ sizeof(NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_KernelHostVgpuDeviceApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "kernelhostvgpudeviceapiCtrlCmdSetVgpuDeviceInfo" +#endif + }, + { /* [1] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) kernelhostvgpudeviceapiCtrlCmdSetVgpuGuestLifeCycleState_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa0840102u, + /*paramSize=*/ sizeof(NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_KernelHostVgpuDeviceApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "kernelhostvgpudeviceapiCtrlCmdSetVgpuGuestLifeCycleState" +#endif + }, + { /* [2] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) kernelhostvgpudeviceapiCtrlCmdSetOfflinedPagePatchInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa0840103u, + /*paramSize=*/ sizeof(NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_KernelHostVgpuDeviceApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "kernelhostvgpudeviceapiCtrlCmdSetOfflinedPagePatchInfo" +#endif + }, + { /* [3] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) kernelhostvgpudeviceapiCtrlCmdVfConfigSpaceAccess_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa0840104u, + /*paramSize=*/ sizeof(NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_KernelHostVgpuDeviceApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "kernelhostvgpudeviceapiCtrlCmdVfConfigSpaceAccess" +#endif + }, + { /* [4] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8010u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) kernelhostvgpudeviceapiCtrlCmdBindFecsEvtbuf_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8010u) + /*flags=*/ 0x8010u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa0840105u, + /*paramSize=*/ sizeof(NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_KernelHostVgpuDeviceApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "kernelhostvgpudeviceapiCtrlCmdBindFecsEvtbuf" +#endif + }, + { /* [5] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) kernelhostvgpudeviceapiCtrlCmdTriggerPrivDoorbell_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa0840106u, + /*paramSize=*/ sizeof(NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_KernelHostVgpuDeviceApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "kernelhostvgpudeviceapiCtrlCmdTriggerPrivDoorbell" +#endif + }, + { /* [6] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) kernelhostvgpudeviceapiCtrlCmdEventSetNotification_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa0840107u, + /*paramSize=*/ sizeof(NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_KernelHostVgpuDeviceApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "kernelhostvgpudeviceapiCtrlCmdEventSetNotification" +#endif + }, + { /* [7] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) kernelhostvgpudeviceapiCtrlCmdSetSriovState_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa0840108u, + /*paramSize=*/ sizeof(NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_KernelHostVgpuDeviceApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "kernelhostvgpudeviceapiCtrlCmdSetSriovState" +#endif + }, + { /* [8] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) kernelhostvgpudeviceapiCtrlCmdSetGuestId_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa0840109u, + /*paramSize=*/ sizeof(NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_KernelHostVgpuDeviceApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "kernelhostvgpudeviceapiCtrlCmdSetGuestId" +#endif + }, + +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelHostVgpuDeviceApi = +{ + /*numEntries=*/ 9, + /*pExportEntries=*/ __nvoc_exported_method_def_KernelHostVgpuDeviceApi +}; + +void __nvoc_dtor_GpuResource(GpuResource*); +void __nvoc_dtor_Notifier(Notifier*); +void __nvoc_dtor_KernelHostVgpuDeviceApi(KernelHostVgpuDeviceApi *pThis) { + __nvoc_kernelhostvgpudeviceapiDestruct(pThis); + __nvoc_dtor_GpuResource(&pThis->__nvoc_base_GpuResource); + __nvoc_dtor_Notifier(&pThis->__nvoc_base_Notifier); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_KernelHostVgpuDeviceApi(KernelHostVgpuDeviceApi *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_GpuResource(GpuResource* , CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); +NV_STATUS __nvoc_ctor_Notifier(Notifier* , CALL_CONTEXT *); +NV_STATUS __nvoc_ctor_KernelHostVgpuDeviceApi(KernelHostVgpuDeviceApi *pThis, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_GpuResource(&pThis->__nvoc_base_GpuResource, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_KernelHostVgpuDeviceApi_fail_GpuResource; + status = __nvoc_ctor_Notifier(&pThis->__nvoc_base_Notifier, arg_pCallContext); + if (status != NV_OK) goto __nvoc_ctor_KernelHostVgpuDeviceApi_fail_Notifier; + __nvoc_init_dataField_KernelHostVgpuDeviceApi(pThis); + + status = __nvoc_kernelhostvgpudeviceapiConstruct(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_KernelHostVgpuDeviceApi_fail__init; + goto __nvoc_ctor_KernelHostVgpuDeviceApi_exit; // Success + +__nvoc_ctor_KernelHostVgpuDeviceApi_fail__init: + __nvoc_dtor_Notifier(&pThis->__nvoc_base_Notifier); +__nvoc_ctor_KernelHostVgpuDeviceApi_fail_Notifier: + __nvoc_dtor_GpuResource(&pThis->__nvoc_base_GpuResource); +__nvoc_ctor_KernelHostVgpuDeviceApi_fail_GpuResource: +__nvoc_ctor_KernelHostVgpuDeviceApi_exit: + + return status; +} + +static void __nvoc_init_funcTable_KernelHostVgpuDeviceApi_1(KernelHostVgpuDeviceApi *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); + + pThis->__kernelhostvgpudeviceapiCanCopy__ = &kernelhostvgpudeviceapiCanCopy_IMPL; + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__kernelhostvgpudeviceapiCtrlCmdSetVgpuDeviceInfo__ = &kernelhostvgpudeviceapiCtrlCmdSetVgpuDeviceInfo_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__kernelhostvgpudeviceapiCtrlCmdSetVgpuGuestLifeCycleState__ = &kernelhostvgpudeviceapiCtrlCmdSetVgpuGuestLifeCycleState_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__kernelhostvgpudeviceapiCtrlCmdSetOfflinedPagePatchInfo__ = &kernelhostvgpudeviceapiCtrlCmdSetOfflinedPagePatchInfo_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__kernelhostvgpudeviceapiCtrlCmdVfConfigSpaceAccess__ = &kernelhostvgpudeviceapiCtrlCmdVfConfigSpaceAccess_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8010u) + pThis->__kernelhostvgpudeviceapiCtrlCmdBindFecsEvtbuf__ = &kernelhostvgpudeviceapiCtrlCmdBindFecsEvtbuf_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__kernelhostvgpudeviceapiCtrlCmdTriggerPrivDoorbell__ = &kernelhostvgpudeviceapiCtrlCmdTriggerPrivDoorbell_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__kernelhostvgpudeviceapiCtrlCmdEventSetNotification__ = &kernelhostvgpudeviceapiCtrlCmdEventSetNotification_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__kernelhostvgpudeviceapiCtrlCmdSetSriovState__ = &kernelhostvgpudeviceapiCtrlCmdSetSriovState_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__kernelhostvgpudeviceapiCtrlCmdSetGuestId__ = &kernelhostvgpudeviceapiCtrlCmdSetGuestId_IMPL; +#endif + + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__resCanCopy__ = &__nvoc_thunk_KernelHostVgpuDeviceApi_resCanCopy; + + pThis->__kernelhostvgpudeviceapiShareCallback__ = &__nvoc_thunk_GpuResource_kernelhostvgpudeviceapiShareCallback; + + pThis->__kernelhostvgpudeviceapiMapTo__ = &__nvoc_thunk_RsResource_kernelhostvgpudeviceapiMapTo; + + pThis->__kernelhostvgpudeviceapiGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_kernelhostvgpudeviceapiGetOrAllocNotifShare; + + pThis->__kernelhostvgpudeviceapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_kernelhostvgpudeviceapiCheckMemInterUnmap; + + pThis->__kernelhostvgpudeviceapiGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_kernelhostvgpudeviceapiGetMapAddrSpace; + + pThis->__kernelhostvgpudeviceapiSetNotificationShare__ = &__nvoc_thunk_Notifier_kernelhostvgpudeviceapiSetNotificationShare; + + pThis->__kernelhostvgpudeviceapiGetRefCount__ = &__nvoc_thunk_RsResource_kernelhostvgpudeviceapiGetRefCount; + + pThis->__kernelhostvgpudeviceapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_kernelhostvgpudeviceapiAddAdditionalDependants; + + pThis->__kernelhostvgpudeviceapiControl_Prologue__ = &__nvoc_thunk_RmResource_kernelhostvgpudeviceapiControl_Prologue; + + pThis->__kernelhostvgpudeviceapiGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_kernelhostvgpudeviceapiGetRegBaseOffsetAndSize; + + pThis->__kernelhostvgpudeviceapiInternalControlForward__ = &__nvoc_thunk_GpuResource_kernelhostvgpudeviceapiInternalControlForward; + + pThis->__kernelhostvgpudeviceapiUnmapFrom__ = &__nvoc_thunk_RsResource_kernelhostvgpudeviceapiUnmapFrom; + + pThis->__kernelhostvgpudeviceapiControl_Epilogue__ = &__nvoc_thunk_RmResource_kernelhostvgpudeviceapiControl_Epilogue; + + pThis->__kernelhostvgpudeviceapiControlLookup__ = &__nvoc_thunk_RsResource_kernelhostvgpudeviceapiControlLookup; + + pThis->__kernelhostvgpudeviceapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_kernelhostvgpudeviceapiGetInternalObjectHandle; + + pThis->__kernelhostvgpudeviceapiControl__ = &__nvoc_thunk_GpuResource_kernelhostvgpudeviceapiControl; + + pThis->__kernelhostvgpudeviceapiUnmap__ = &__nvoc_thunk_GpuResource_kernelhostvgpudeviceapiUnmap; + + pThis->__kernelhostvgpudeviceapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_kernelhostvgpudeviceapiGetMemInterMapParams; + + pThis->__kernelhostvgpudeviceapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_kernelhostvgpudeviceapiGetMemoryMappingDescriptor; + + pThis->__kernelhostvgpudeviceapiControlFilter__ = &__nvoc_thunk_RsResource_kernelhostvgpudeviceapiControlFilter; + + pThis->__kernelhostvgpudeviceapiUnregisterEvent__ = &__nvoc_thunk_Notifier_kernelhostvgpudeviceapiUnregisterEvent; + + pThis->__kernelhostvgpudeviceapiPreDestruct__ = &__nvoc_thunk_RsResource_kernelhostvgpudeviceapiPreDestruct; + + pThis->__kernelhostvgpudeviceapiIsDuplicate__ = &__nvoc_thunk_RsResource_kernelhostvgpudeviceapiIsDuplicate; + + pThis->__kernelhostvgpudeviceapiGetNotificationListPtr__ = &__nvoc_thunk_Notifier_kernelhostvgpudeviceapiGetNotificationListPtr; + + pThis->__kernelhostvgpudeviceapiGetNotificationShare__ = &__nvoc_thunk_Notifier_kernelhostvgpudeviceapiGetNotificationShare; + + pThis->__kernelhostvgpudeviceapiMap__ = &__nvoc_thunk_GpuResource_kernelhostvgpudeviceapiMap; + + pThis->__kernelhostvgpudeviceapiAccessCallback__ = &__nvoc_thunk_RmResource_kernelhostvgpudeviceapiAccessCallback; +} + +void __nvoc_init_funcTable_KernelHostVgpuDeviceApi(KernelHostVgpuDeviceApi *pThis) { + __nvoc_init_funcTable_KernelHostVgpuDeviceApi_1(pThis); +} + +void __nvoc_init_GpuResource(GpuResource*); +void __nvoc_init_Notifier(Notifier*); +void __nvoc_init_KernelHostVgpuDeviceApi(KernelHostVgpuDeviceApi *pThis) { + pThis->__nvoc_pbase_KernelHostVgpuDeviceApi = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; + pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource; + pThis->__nvoc_pbase_RmResourceCommon = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon; + pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource; + pThis->__nvoc_pbase_GpuResource = &pThis->__nvoc_base_GpuResource; + pThis->__nvoc_pbase_INotifier = &pThis->__nvoc_base_Notifier.__nvoc_base_INotifier; + pThis->__nvoc_pbase_Notifier = &pThis->__nvoc_base_Notifier; + __nvoc_init_GpuResource(&pThis->__nvoc_base_GpuResource); + __nvoc_init_Notifier(&pThis->__nvoc_base_Notifier); + __nvoc_init_funcTable_KernelHostVgpuDeviceApi(pThis); +} + +NV_STATUS __nvoc_objCreate_KernelHostVgpuDeviceApi(KernelHostVgpuDeviceApi **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status; + Object *pParentObj; + KernelHostVgpuDeviceApi *pThis; + + pThis = portMemAllocNonPaged(sizeof(KernelHostVgpuDeviceApi)); + if (pThis == NULL) return NV_ERR_NO_MEMORY; + + portMemSet(pThis, 0, sizeof(KernelHostVgpuDeviceApi)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelHostVgpuDeviceApi); + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_KernelHostVgpuDeviceApi(pThis); + status = __nvoc_ctor_KernelHostVgpuDeviceApi(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_objCreate_KernelHostVgpuDeviceApi_cleanup; + + *ppThis = pThis; + return NV_OK; + +__nvoc_objCreate_KernelHostVgpuDeviceApi_cleanup: + // do not call destructors here since the constructor already called them + portMemFree(pThis); + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_KernelHostVgpuDeviceApi(KernelHostVgpuDeviceApi **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + CALL_CONTEXT * arg_pCallContext = va_arg(args, CALL_CONTEXT *); + struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams = va_arg(args, struct RS_RES_ALLOC_PARAMS_INTERNAL *); + + status = __nvoc_objCreate_KernelHostVgpuDeviceApi(ppThis, pParent, createFlags, arg_pCallContext, arg_pParams); + + return status; +} + diff --git a/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.h b/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.h new file mode 100644 index 000000000..a47492319 --- /dev/null +++ b/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.h @@ -0,0 +1,422 @@ +#ifndef _G_KERNEL_HOSTVGPUDEVICEAPI_NVOC_H_ +#define _G_KERNEL_HOSTVGPUDEVICEAPI_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_kernel_hostvgpudeviceapi_nvoc.h" + +#ifndef _KERNEL_HOSTVGPUDEVICEAPI_H_ +#define _KERNEL_HOSTVGPUDEVICEAPI_H_ + +#include "core/core.h" +#include "virtualization/kernel_vgpu_mgr.h" +#include "rmapi/client.h" +#include "gpu/gpu_resource.h" + +#include "class/cla084.h" + +#ifdef NVOC_KERNEL_HOSTVGPUDEVICEAPI_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct KernelHostVgpuDeviceShr { + const struct NVOC_RTTI *__nvoc_rtti; + struct RsShared __nvoc_base_RsShared; + struct Object *__nvoc_pbase_Object; + struct RsShared *__nvoc_pbase_RsShared; + struct KernelHostVgpuDeviceShr *__nvoc_pbase_KernelHostVgpuDeviceShr; + KERNEL_HOST_VGPU_DEVICE *pDevice; +}; + +#ifndef __NVOC_CLASS_KernelHostVgpuDeviceShr_TYPEDEF__ +#define __NVOC_CLASS_KernelHostVgpuDeviceShr_TYPEDEF__ +typedef struct KernelHostVgpuDeviceShr KernelHostVgpuDeviceShr; +#endif /* __NVOC_CLASS_KernelHostVgpuDeviceShr_TYPEDEF__ */ + +#ifndef __nvoc_class_id_KernelHostVgpuDeviceShr +#define __nvoc_class_id_KernelHostVgpuDeviceShr 0xe32156 +#endif /* __nvoc_class_id_KernelHostVgpuDeviceShr */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelHostVgpuDeviceShr; + +#define __staticCast_KernelHostVgpuDeviceShr(pThis) \ + ((pThis)->__nvoc_pbase_KernelHostVgpuDeviceShr) + +#ifdef __nvoc_kernel_hostvgpudeviceapi_h_disabled +#define __dynamicCast_KernelHostVgpuDeviceShr(pThis) ((KernelHostVgpuDeviceShr*)NULL) +#else //__nvoc_kernel_hostvgpudeviceapi_h_disabled +#define __dynamicCast_KernelHostVgpuDeviceShr(pThis) \ + ((KernelHostVgpuDeviceShr*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(KernelHostVgpuDeviceShr))) +#endif //__nvoc_kernel_hostvgpudeviceapi_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_KernelHostVgpuDeviceShr(KernelHostVgpuDeviceShr**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_KernelHostVgpuDeviceShr(KernelHostVgpuDeviceShr**, Dynamic*, NvU32); +#define __objCreate_KernelHostVgpuDeviceShr(ppNewObj, pParent, createFlags) \ + __nvoc_objCreate_KernelHostVgpuDeviceShr((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) + +NV_STATUS kernelhostvgpudeviceshrConstruct_IMPL(struct KernelHostVgpuDeviceShr *arg_pKernelHostVgpuDeviceShr); + +#define __nvoc_kernelhostvgpudeviceshrConstruct(arg_pKernelHostVgpuDeviceShr) kernelhostvgpudeviceshrConstruct_IMPL(arg_pKernelHostVgpuDeviceShr) +void kernelhostvgpudeviceshrDestruct_IMPL(struct KernelHostVgpuDeviceShr *pKernelHostVgpuDeviceShr); + +#define __nvoc_kernelhostvgpudeviceshrDestruct(pKernelHostVgpuDeviceShr) kernelhostvgpudeviceshrDestruct_IMPL(pKernelHostVgpuDeviceShr) +#undef PRIVATE_FIELD + + +void destroyKernelHostVgpuDeviceShare(struct OBJGPU *pGpu, struct KernelHostVgpuDeviceShr* pShare); + +#ifdef NVOC_KERNEL_HOSTVGPUDEVICEAPI_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct KernelHostVgpuDeviceApi { + const struct NVOC_RTTI *__nvoc_rtti; + struct GpuResource __nvoc_base_GpuResource; + struct Notifier __nvoc_base_Notifier; + struct Object *__nvoc_pbase_Object; + struct RsResource *__nvoc_pbase_RsResource; + struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; + struct RmResource *__nvoc_pbase_RmResource; + struct GpuResource *__nvoc_pbase_GpuResource; + struct INotifier *__nvoc_pbase_INotifier; + struct Notifier *__nvoc_pbase_Notifier; + struct KernelHostVgpuDeviceApi *__nvoc_pbase_KernelHostVgpuDeviceApi; + NvBool (*__kernelhostvgpudeviceapiCanCopy__)(struct KernelHostVgpuDeviceApi *); + NV_STATUS (*__kernelhostvgpudeviceapiCtrlCmdSetVgpuDeviceInfo__)(struct KernelHostVgpuDeviceApi *, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS *); + NV_STATUS (*__kernelhostvgpudeviceapiCtrlCmdSetVgpuGuestLifeCycleState__)(struct KernelHostVgpuDeviceApi *, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE_PARAMS *); + NV_STATUS (*__kernelhostvgpudeviceapiCtrlCmdSetOfflinedPagePatchInfo__)(struct KernelHostVgpuDeviceApi *, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO_PARAMS *); + NV_STATUS (*__kernelhostvgpudeviceapiCtrlCmdVfConfigSpaceAccess__)(struct KernelHostVgpuDeviceApi *, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS_PARAMS *); + NV_STATUS (*__kernelhostvgpudeviceapiCtrlCmdBindFecsEvtbuf__)(struct KernelHostVgpuDeviceApi *, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF_PARAMS *); + NV_STATUS (*__kernelhostvgpudeviceapiCtrlCmdTriggerPrivDoorbell__)(struct KernelHostVgpuDeviceApi *, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL_PARAMS *); + NV_STATUS (*__kernelhostvgpudeviceapiCtrlCmdEventSetNotification__)(struct KernelHostVgpuDeviceApi *, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION_PARAMS *); + NV_STATUS (*__kernelhostvgpudeviceapiCtrlCmdSetSriovState__)(struct KernelHostVgpuDeviceApi *, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS *); + NV_STATUS (*__kernelhostvgpudeviceapiCtrlCmdSetGuestId__)(struct KernelHostVgpuDeviceApi *, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS *); + NvBool (*__kernelhostvgpudeviceapiShareCallback__)(struct KernelHostVgpuDeviceApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__kernelhostvgpudeviceapiMapTo__)(struct KernelHostVgpuDeviceApi *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__kernelhostvgpudeviceapiGetOrAllocNotifShare__)(struct KernelHostVgpuDeviceApi *, NvHandle, NvHandle, struct NotifShare **); + NV_STATUS (*__kernelhostvgpudeviceapiCheckMemInterUnmap__)(struct KernelHostVgpuDeviceApi *, NvBool); + NV_STATUS (*__kernelhostvgpudeviceapiGetMapAddrSpace__)(struct KernelHostVgpuDeviceApi *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + void (*__kernelhostvgpudeviceapiSetNotificationShare__)(struct KernelHostVgpuDeviceApi *, struct NotifShare *); + NvU32 (*__kernelhostvgpudeviceapiGetRefCount__)(struct KernelHostVgpuDeviceApi *); + void (*__kernelhostvgpudeviceapiAddAdditionalDependants__)(struct RsClient *, struct KernelHostVgpuDeviceApi *, RsResourceRef *); + NV_STATUS (*__kernelhostvgpudeviceapiControl_Prologue__)(struct KernelHostVgpuDeviceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__kernelhostvgpudeviceapiGetRegBaseOffsetAndSize__)(struct KernelHostVgpuDeviceApi *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__kernelhostvgpudeviceapiInternalControlForward__)(struct KernelHostVgpuDeviceApi *, NvU32, void *, NvU32); + NV_STATUS (*__kernelhostvgpudeviceapiUnmapFrom__)(struct KernelHostVgpuDeviceApi *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__kernelhostvgpudeviceapiControl_Epilogue__)(struct KernelHostVgpuDeviceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__kernelhostvgpudeviceapiControlLookup__)(struct KernelHostVgpuDeviceApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__kernelhostvgpudeviceapiGetInternalObjectHandle__)(struct KernelHostVgpuDeviceApi *); + NV_STATUS (*__kernelhostvgpudeviceapiControl__)(struct KernelHostVgpuDeviceApi *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__kernelhostvgpudeviceapiUnmap__)(struct KernelHostVgpuDeviceApi *, CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__kernelhostvgpudeviceapiGetMemInterMapParams__)(struct KernelHostVgpuDeviceApi *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__kernelhostvgpudeviceapiGetMemoryMappingDescriptor__)(struct KernelHostVgpuDeviceApi *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__kernelhostvgpudeviceapiControlFilter__)(struct KernelHostVgpuDeviceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__kernelhostvgpudeviceapiUnregisterEvent__)(struct KernelHostVgpuDeviceApi *, NvHandle, NvHandle, NvHandle, NvHandle); + void (*__kernelhostvgpudeviceapiPreDestruct__)(struct KernelHostVgpuDeviceApi *); + NV_STATUS (*__kernelhostvgpudeviceapiIsDuplicate__)(struct KernelHostVgpuDeviceApi *, NvHandle, NvBool *); + PEVENTNOTIFICATION *(*__kernelhostvgpudeviceapiGetNotificationListPtr__)(struct KernelHostVgpuDeviceApi *); + struct NotifShare *(*__kernelhostvgpudeviceapiGetNotificationShare__)(struct KernelHostVgpuDeviceApi *); + NV_STATUS (*__kernelhostvgpudeviceapiMap__)(struct KernelHostVgpuDeviceApi *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); + NvBool (*__kernelhostvgpudeviceapiAccessCallback__)(struct KernelHostVgpuDeviceApi *, struct RsClient *, void *, RsAccessRight); + struct KernelHostVgpuDeviceShr *pShared; + NvU32 notifyActions[5]; +}; + +#ifndef __NVOC_CLASS_KernelHostVgpuDeviceApi_TYPEDEF__ +#define __NVOC_CLASS_KernelHostVgpuDeviceApi_TYPEDEF__ +typedef struct KernelHostVgpuDeviceApi KernelHostVgpuDeviceApi; +#endif /* __NVOC_CLASS_KernelHostVgpuDeviceApi_TYPEDEF__ */ + +#ifndef __nvoc_class_id_KernelHostVgpuDeviceApi +#define __nvoc_class_id_KernelHostVgpuDeviceApi 0xb12d7d +#endif /* __nvoc_class_id_KernelHostVgpuDeviceApi */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelHostVgpuDeviceApi; + +#define __staticCast_KernelHostVgpuDeviceApi(pThis) \ + ((pThis)->__nvoc_pbase_KernelHostVgpuDeviceApi) + +#ifdef __nvoc_kernel_hostvgpudeviceapi_h_disabled +#define __dynamicCast_KernelHostVgpuDeviceApi(pThis) ((KernelHostVgpuDeviceApi*)NULL) +#else //__nvoc_kernel_hostvgpudeviceapi_h_disabled +#define __dynamicCast_KernelHostVgpuDeviceApi(pThis) \ + ((KernelHostVgpuDeviceApi*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(KernelHostVgpuDeviceApi))) +#endif //__nvoc_kernel_hostvgpudeviceapi_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_KernelHostVgpuDeviceApi(KernelHostVgpuDeviceApi**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_KernelHostVgpuDeviceApi(KernelHostVgpuDeviceApi**, Dynamic*, NvU32, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +#define __objCreate_KernelHostVgpuDeviceApi(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ + __nvoc_objCreate_KernelHostVgpuDeviceApi((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) + +#define kernelhostvgpudeviceapiCanCopy(pKernelHostVgpuDeviceApi) kernelhostvgpudeviceapiCanCopy_DISPATCH(pKernelHostVgpuDeviceApi) +#define kernelhostvgpudeviceapiCtrlCmdSetVgpuDeviceInfo(pKernelHostVgpuDeviceApi, pParams) kernelhostvgpudeviceapiCtrlCmdSetVgpuDeviceInfo_DISPATCH(pKernelHostVgpuDeviceApi, pParams) +#define kernelhostvgpudeviceapiCtrlCmdSetVgpuGuestLifeCycleState(pKernelHostVgpuDeviceApi, pParams) kernelhostvgpudeviceapiCtrlCmdSetVgpuGuestLifeCycleState_DISPATCH(pKernelHostVgpuDeviceApi, pParams) +#define kernelhostvgpudeviceapiCtrlCmdSetOfflinedPagePatchInfo(pKernelHostVgpuDeviceApi, pParams) kernelhostvgpudeviceapiCtrlCmdSetOfflinedPagePatchInfo_DISPATCH(pKernelHostVgpuDeviceApi, pParams) +#define kernelhostvgpudeviceapiCtrlCmdVfConfigSpaceAccess(pKernelHostVgpuDeviceApi, pParams) kernelhostvgpudeviceapiCtrlCmdVfConfigSpaceAccess_DISPATCH(pKernelHostVgpuDeviceApi, pParams) +#define kernelhostvgpudeviceapiCtrlCmdBindFecsEvtbuf(pKernelHostVgpuDeviceApi, pParams) kernelhostvgpudeviceapiCtrlCmdBindFecsEvtbuf_DISPATCH(pKernelHostVgpuDeviceApi, pParams) +#define kernelhostvgpudeviceapiCtrlCmdTriggerPrivDoorbell(pKernelHostVgpuDeviceApi, pParams) kernelhostvgpudeviceapiCtrlCmdTriggerPrivDoorbell_DISPATCH(pKernelHostVgpuDeviceApi, pParams) +#define kernelhostvgpudeviceapiCtrlCmdEventSetNotification(pKernelHostVgpuDeviceApi, pSetEventParams) kernelhostvgpudeviceapiCtrlCmdEventSetNotification_DISPATCH(pKernelHostVgpuDeviceApi, pSetEventParams) +#define kernelhostvgpudeviceapiCtrlCmdSetSriovState(pKernelHostVgpuDeviceApi, pParams) kernelhostvgpudeviceapiCtrlCmdSetSriovState_DISPATCH(pKernelHostVgpuDeviceApi, pParams) +#define kernelhostvgpudeviceapiCtrlCmdSetGuestId(pKernelHostVgpuDeviceApi, pParams) kernelhostvgpudeviceapiCtrlCmdSetGuestId_DISPATCH(pKernelHostVgpuDeviceApi, pParams) +#define kernelhostvgpudeviceapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) kernelhostvgpudeviceapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define kernelhostvgpudeviceapiMapTo(pResource, pParams) kernelhostvgpudeviceapiMapTo_DISPATCH(pResource, pParams) +#define kernelhostvgpudeviceapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) kernelhostvgpudeviceapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +#define kernelhostvgpudeviceapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) kernelhostvgpudeviceapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define kernelhostvgpudeviceapiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) kernelhostvgpudeviceapiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define kernelhostvgpudeviceapiSetNotificationShare(pNotifier, pNotifShare) kernelhostvgpudeviceapiSetNotificationShare_DISPATCH(pNotifier, pNotifShare) +#define kernelhostvgpudeviceapiGetRefCount(pResource) kernelhostvgpudeviceapiGetRefCount_DISPATCH(pResource) +#define kernelhostvgpudeviceapiAddAdditionalDependants(pClient, pResource, pReference) kernelhostvgpudeviceapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define kernelhostvgpudeviceapiControl_Prologue(pResource, pCallContext, pParams) kernelhostvgpudeviceapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define kernelhostvgpudeviceapiGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) kernelhostvgpudeviceapiGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define kernelhostvgpudeviceapiInternalControlForward(pGpuResource, command, pParams, size) kernelhostvgpudeviceapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define kernelhostvgpudeviceapiUnmapFrom(pResource, pParams) kernelhostvgpudeviceapiUnmapFrom_DISPATCH(pResource, pParams) +#define kernelhostvgpudeviceapiControl_Epilogue(pResource, pCallContext, pParams) kernelhostvgpudeviceapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define kernelhostvgpudeviceapiControlLookup(pResource, pParams, ppEntry) kernelhostvgpudeviceapiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define kernelhostvgpudeviceapiGetInternalObjectHandle(pGpuResource) kernelhostvgpudeviceapiGetInternalObjectHandle_DISPATCH(pGpuResource) +#define kernelhostvgpudeviceapiControl(pGpuResource, pCallContext, pParams) kernelhostvgpudeviceapiControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define kernelhostvgpudeviceapiUnmap(pGpuResource, pCallContext, pCpuMapping) kernelhostvgpudeviceapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define kernelhostvgpudeviceapiGetMemInterMapParams(pRmResource, pParams) kernelhostvgpudeviceapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define kernelhostvgpudeviceapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) kernelhostvgpudeviceapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define kernelhostvgpudeviceapiControlFilter(pResource, pCallContext, pParams) kernelhostvgpudeviceapiControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define kernelhostvgpudeviceapiUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) kernelhostvgpudeviceapiUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define kernelhostvgpudeviceapiPreDestruct(pResource) kernelhostvgpudeviceapiPreDestruct_DISPATCH(pResource) +#define kernelhostvgpudeviceapiIsDuplicate(pResource, hMemory, pDuplicate) kernelhostvgpudeviceapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define kernelhostvgpudeviceapiGetNotificationListPtr(pNotifier) kernelhostvgpudeviceapiGetNotificationListPtr_DISPATCH(pNotifier) +#define kernelhostvgpudeviceapiGetNotificationShare(pNotifier) kernelhostvgpudeviceapiGetNotificationShare_DISPATCH(pNotifier) +#define kernelhostvgpudeviceapiMap(pGpuResource, pCallContext, pParams, pCpuMapping) kernelhostvgpudeviceapiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) +#define kernelhostvgpudeviceapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) kernelhostvgpudeviceapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +NvBool kernelhostvgpudeviceapiCanCopy_IMPL(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi); + +static inline NvBool kernelhostvgpudeviceapiCanCopy_DISPATCH(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi) { + return pKernelHostVgpuDeviceApi->__kernelhostvgpudeviceapiCanCopy__(pKernelHostVgpuDeviceApi); +} + +NV_STATUS kernelhostvgpudeviceapiCtrlCmdSetVgpuDeviceInfo_IMPL(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS *pParams); + +static inline NV_STATUS kernelhostvgpudeviceapiCtrlCmdSetVgpuDeviceInfo_DISPATCH(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS *pParams) { + return pKernelHostVgpuDeviceApi->__kernelhostvgpudeviceapiCtrlCmdSetVgpuDeviceInfo__(pKernelHostVgpuDeviceApi, pParams); +} + +NV_STATUS kernelhostvgpudeviceapiCtrlCmdSetVgpuGuestLifeCycleState_IMPL(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE_PARAMS *pParams); + +static inline NV_STATUS kernelhostvgpudeviceapiCtrlCmdSetVgpuGuestLifeCycleState_DISPATCH(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE_PARAMS *pParams) { + return pKernelHostVgpuDeviceApi->__kernelhostvgpudeviceapiCtrlCmdSetVgpuGuestLifeCycleState__(pKernelHostVgpuDeviceApi, pParams); +} + +NV_STATUS kernelhostvgpudeviceapiCtrlCmdSetOfflinedPagePatchInfo_IMPL(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO_PARAMS *pParams); + +static inline NV_STATUS kernelhostvgpudeviceapiCtrlCmdSetOfflinedPagePatchInfo_DISPATCH(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO_PARAMS *pParams) { + return pKernelHostVgpuDeviceApi->__kernelhostvgpudeviceapiCtrlCmdSetOfflinedPagePatchInfo__(pKernelHostVgpuDeviceApi, pParams); +} + +NV_STATUS kernelhostvgpudeviceapiCtrlCmdVfConfigSpaceAccess_IMPL(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS_PARAMS *pParams); + +static inline NV_STATUS kernelhostvgpudeviceapiCtrlCmdVfConfigSpaceAccess_DISPATCH(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS_PARAMS *pParams) { + return pKernelHostVgpuDeviceApi->__kernelhostvgpudeviceapiCtrlCmdVfConfigSpaceAccess__(pKernelHostVgpuDeviceApi, pParams); +} + +NV_STATUS kernelhostvgpudeviceapiCtrlCmdBindFecsEvtbuf_IMPL(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF_PARAMS *pParams); + +static inline NV_STATUS kernelhostvgpudeviceapiCtrlCmdBindFecsEvtbuf_DISPATCH(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF_PARAMS *pParams) { + return pKernelHostVgpuDeviceApi->__kernelhostvgpudeviceapiCtrlCmdBindFecsEvtbuf__(pKernelHostVgpuDeviceApi, pParams); +} + +NV_STATUS kernelhostvgpudeviceapiCtrlCmdTriggerPrivDoorbell_IMPL(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL_PARAMS *pParams); + +static inline NV_STATUS kernelhostvgpudeviceapiCtrlCmdTriggerPrivDoorbell_DISPATCH(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL_PARAMS *pParams) { + return pKernelHostVgpuDeviceApi->__kernelhostvgpudeviceapiCtrlCmdTriggerPrivDoorbell__(pKernelHostVgpuDeviceApi, pParams); +} + +NV_STATUS kernelhostvgpudeviceapiCtrlCmdEventSetNotification_IMPL(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION_PARAMS *pSetEventParams); + +static inline NV_STATUS kernelhostvgpudeviceapiCtrlCmdEventSetNotification_DISPATCH(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION_PARAMS *pSetEventParams) { + return pKernelHostVgpuDeviceApi->__kernelhostvgpudeviceapiCtrlCmdEventSetNotification__(pKernelHostVgpuDeviceApi, pSetEventParams); +} + +NV_STATUS kernelhostvgpudeviceapiCtrlCmdSetSriovState_IMPL(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS *pParams); + +static inline NV_STATUS kernelhostvgpudeviceapiCtrlCmdSetSriovState_DISPATCH(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS *pParams) { + return pKernelHostVgpuDeviceApi->__kernelhostvgpudeviceapiCtrlCmdSetSriovState__(pKernelHostVgpuDeviceApi, pParams); +} + +NV_STATUS kernelhostvgpudeviceapiCtrlCmdSetGuestId_IMPL(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS *pParams); + +static inline NV_STATUS kernelhostvgpudeviceapiCtrlCmdSetGuestId_DISPATCH(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS *pParams) { + return pKernelHostVgpuDeviceApi->__kernelhostvgpudeviceapiCtrlCmdSetGuestId__(pKernelHostVgpuDeviceApi, pParams); +} + +static inline NvBool kernelhostvgpudeviceapiShareCallback_DISPATCH(struct KernelHostVgpuDeviceApi *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pGpuResource->__kernelhostvgpudeviceapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS kernelhostvgpudeviceapiMapTo_DISPATCH(struct KernelHostVgpuDeviceApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__kernelhostvgpudeviceapiMapTo__(pResource, pParams); +} + +static inline NV_STATUS kernelhostvgpudeviceapiGetOrAllocNotifShare_DISPATCH(struct KernelHostVgpuDeviceApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { + return pNotifier->__kernelhostvgpudeviceapiGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); +} + +static inline NV_STATUS kernelhostvgpudeviceapiCheckMemInterUnmap_DISPATCH(struct KernelHostVgpuDeviceApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__kernelhostvgpudeviceapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS kernelhostvgpudeviceapiGetMapAddrSpace_DISPATCH(struct KernelHostVgpuDeviceApi *pGpuResource, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__kernelhostvgpudeviceapiGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline void kernelhostvgpudeviceapiSetNotificationShare_DISPATCH(struct KernelHostVgpuDeviceApi *pNotifier, struct NotifShare *pNotifShare) { + pNotifier->__kernelhostvgpudeviceapiSetNotificationShare__(pNotifier, pNotifShare); +} + +static inline NvU32 kernelhostvgpudeviceapiGetRefCount_DISPATCH(struct KernelHostVgpuDeviceApi *pResource) { + return pResource->__kernelhostvgpudeviceapiGetRefCount__(pResource); +} + +static inline void kernelhostvgpudeviceapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct KernelHostVgpuDeviceApi *pResource, RsResourceRef *pReference) { + pResource->__kernelhostvgpudeviceapiAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS kernelhostvgpudeviceapiControl_Prologue_DISPATCH(struct KernelHostVgpuDeviceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__kernelhostvgpudeviceapiControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS kernelhostvgpudeviceapiGetRegBaseOffsetAndSize_DISPATCH(struct KernelHostVgpuDeviceApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__kernelhostvgpudeviceapiGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NV_STATUS kernelhostvgpudeviceapiInternalControlForward_DISPATCH(struct KernelHostVgpuDeviceApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__kernelhostvgpudeviceapiInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS kernelhostvgpudeviceapiUnmapFrom_DISPATCH(struct KernelHostVgpuDeviceApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__kernelhostvgpudeviceapiUnmapFrom__(pResource, pParams); +} + +static inline void kernelhostvgpudeviceapiControl_Epilogue_DISPATCH(struct KernelHostVgpuDeviceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__kernelhostvgpudeviceapiControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS kernelhostvgpudeviceapiControlLookup_DISPATCH(struct KernelHostVgpuDeviceApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__kernelhostvgpudeviceapiControlLookup__(pResource, pParams, ppEntry); +} + +static inline NvHandle kernelhostvgpudeviceapiGetInternalObjectHandle_DISPATCH(struct KernelHostVgpuDeviceApi *pGpuResource) { + return pGpuResource->__kernelhostvgpudeviceapiGetInternalObjectHandle__(pGpuResource); +} + +static inline NV_STATUS kernelhostvgpudeviceapiControl_DISPATCH(struct KernelHostVgpuDeviceApi *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__kernelhostvgpudeviceapiControl__(pGpuResource, pCallContext, pParams); +} + +static inline NV_STATUS kernelhostvgpudeviceapiUnmap_DISPATCH(struct KernelHostVgpuDeviceApi *pGpuResource, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pGpuResource->__kernelhostvgpudeviceapiUnmap__(pGpuResource, pCallContext, pCpuMapping); +} + +static inline NV_STATUS kernelhostvgpudeviceapiGetMemInterMapParams_DISPATCH(struct KernelHostVgpuDeviceApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__kernelhostvgpudeviceapiGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS kernelhostvgpudeviceapiGetMemoryMappingDescriptor_DISPATCH(struct KernelHostVgpuDeviceApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__kernelhostvgpudeviceapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +} + +static inline NV_STATUS kernelhostvgpudeviceapiControlFilter_DISPATCH(struct KernelHostVgpuDeviceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__kernelhostvgpudeviceapiControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS kernelhostvgpudeviceapiUnregisterEvent_DISPATCH(struct KernelHostVgpuDeviceApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { + return pNotifier->__kernelhostvgpudeviceapiUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); +} + +static inline void kernelhostvgpudeviceapiPreDestruct_DISPATCH(struct KernelHostVgpuDeviceApi *pResource) { + pResource->__kernelhostvgpudeviceapiPreDestruct__(pResource); +} + +static inline NV_STATUS kernelhostvgpudeviceapiIsDuplicate_DISPATCH(struct KernelHostVgpuDeviceApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__kernelhostvgpudeviceapiIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline PEVENTNOTIFICATION *kernelhostvgpudeviceapiGetNotificationListPtr_DISPATCH(struct KernelHostVgpuDeviceApi *pNotifier) { + return pNotifier->__kernelhostvgpudeviceapiGetNotificationListPtr__(pNotifier); +} + +static inline struct NotifShare *kernelhostvgpudeviceapiGetNotificationShare_DISPATCH(struct KernelHostVgpuDeviceApi *pNotifier) { + return pNotifier->__kernelhostvgpudeviceapiGetNotificationShare__(pNotifier); +} + +static inline NV_STATUS kernelhostvgpudeviceapiMap_DISPATCH(struct KernelHostVgpuDeviceApi *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { + return pGpuResource->__kernelhostvgpudeviceapiMap__(pGpuResource, pCallContext, pParams, pCpuMapping); +} + +static inline NvBool kernelhostvgpudeviceapiAccessCallback_DISPATCH(struct KernelHostVgpuDeviceApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return pResource->__kernelhostvgpudeviceapiAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); +} + +NV_STATUS kernelhostvgpudeviceapiConstruct_IMPL(struct KernelHostVgpuDeviceApi *arg_pKernelHostVgpuDeviceApi, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + +#define __nvoc_kernelhostvgpudeviceapiConstruct(arg_pKernelHostVgpuDeviceApi, arg_pCallContext, arg_pParams) kernelhostvgpudeviceapiConstruct_IMPL(arg_pKernelHostVgpuDeviceApi, arg_pCallContext, arg_pParams) +NV_STATUS kernelhostvgpudeviceapiCopyConstruct_IMPL(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); + +#ifdef __nvoc_kernel_hostvgpudeviceapi_h_disabled +static inline NV_STATUS kernelhostvgpudeviceapiCopyConstruct(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { + NV_ASSERT_FAILED_PRECOMP("KernelHostVgpuDeviceApi was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_hostvgpudeviceapi_h_disabled +#define kernelhostvgpudeviceapiCopyConstruct(pKernelHostVgpuDeviceApi, pCallContext, pParams) kernelhostvgpudeviceapiCopyConstruct_IMPL(pKernelHostVgpuDeviceApi, pCallContext, pParams) +#endif //__nvoc_kernel_hostvgpudeviceapi_h_disabled + +void kernelhostvgpudeviceapiDestruct_IMPL(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi); + +#define __nvoc_kernelhostvgpudeviceapiDestruct(pKernelHostVgpuDeviceApi) kernelhostvgpudeviceapiDestruct_IMPL(pKernelHostVgpuDeviceApi) +#undef PRIVATE_FIELD + + +NV_STATUS +kernelhostvgpudeviceGetGuestFbInfo(struct OBJGPU *pGpu, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, + VGPU_DEVICE_GUEST_FB_INFO *pFbInfo); + +NV_STATUS +kernelhostvgpudeviceSetGuestFbInfo(struct OBJGPU *pGpu, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, + NvU64 offset, NvU64 length); + +#endif // _KERNEL_HOSTVGPUDEVICEAPI_H_ + + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_KERNEL_HOSTVGPUDEVICEAPI_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_ioctrl_nvoc.c b/src/nvidia/generated/g_kernel_ioctrl_nvoc.c index a00a5dde0..4f6bad131 100644 --- a/src/nvidia/generated/g_kernel_ioctrl_nvoc.c +++ b/src/nvidia/generated/g_kernel_ioctrl_nvoc.c @@ -171,16 +171,13 @@ void __nvoc_init_dataField_KernelIoctrl(KernelIoctrl *pThis, RmHalspecOwner *pRm PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); // NVOC Property Hal field -- PDB_PROP_KIOCTRL_IS_MISSING - if (0) - { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { pThis->setProperty(pThis, PDB_PROP_KIOCTRL_IS_MISSING, ((NvBool)(0 != 0))); } // NVOC Property Hal field -- PDB_PROP_KIOCTRL_MINION_AVAILABLE - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_KIOCTRL_MINION_AVAILABLE, ((NvBool)(0 == 0))); } @@ -220,12 +217,9 @@ static void __nvoc_init_funcTable_KernelIoctrl_1(KernelIoctrl *pThis, RmHalspecO pThis->__kioctrlConstructEngine__ = &kioctrlConstructEngine_IMPL; // Hal function -- kioctrlGetMinionEnableDefault - if (0) + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kioctrlGetMinionEnableDefault__ = &kioctrlGetMinionEnableDefault_GV100; } @@ -236,12 +230,9 @@ static void __nvoc_init_funcTable_KernelIoctrl_1(KernelIoctrl *pThis, RmHalspecO } // Hal function -- kioctrlMinionConstruct - if (0) + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kioctrlMinionConstruct__ = &kioctrlMinionConstruct_GV100; } diff --git a/src/nvidia/generated/g_kernel_ioctrl_nvoc.h b/src/nvidia/generated/g_kernel_ioctrl_nvoc.h index 97d92c8f5..fb0043b21 100644 --- a/src/nvidia/generated/g_kernel_ioctrl_nvoc.h +++ b/src/nvidia/generated/g_kernel_ioctrl_nvoc.h @@ -259,6 +259,7 @@ static inline NvBool kioctrlIsPresent_DISPATCH(POBJGPU pGpu, struct KernelIoctrl } void kioctrlDestructEngine_IMPL(struct KernelIoctrl *arg0); + #ifdef __nvoc_kernel_ioctrl_h_disabled static inline void kioctrlDestructEngine(struct KernelIoctrl *arg0) { NV_ASSERT_FAILED_PRECOMP("KernelIoctrl was disabled!"); diff --git a/src/nvidia/generated/g_kernel_mc_nvoc.c b/src/nvidia/generated/g_kernel_mc_nvoc.c index 4b53d808d..2de971eb9 100644 --- a/src/nvidia/generated/g_kernel_mc_nvoc.c +++ b/src/nvidia/generated/g_kernel_mc_nvoc.c @@ -198,26 +198,20 @@ static void __nvoc_init_funcTable_KernelMc_1(KernelMc *pThis, RmHalspecOwner *pR { pThis->__kmcWritePmcEnableReg__ = &kmcWritePmcEnableReg_GK104; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kmcWritePmcEnableReg__ = &kmcWritePmcEnableReg_GA100; } - else if (0) - { - } // Hal function -- kmcReadPmcEnableReg if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__kmcReadPmcEnableReg__ = &kmcReadPmcEnableReg_GK104; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__kmcReadPmcEnableReg__ = &kmcReadPmcEnableReg_GA100; } - else if (0) - { - } pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_thunk_KernelMc_engstateStateInitLocked; diff --git a/src/nvidia/generated/g_kernel_mc_nvoc.h b/src/nvidia/generated/g_kernel_mc_nvoc.h index 8ff0c1ae6..f248e5565 100644 --- a/src/nvidia/generated/g_kernel_mc_nvoc.h +++ b/src/nvidia/generated/g_kernel_mc_nvoc.h @@ -143,6 +143,7 @@ NV_STATUS __nvoc_objCreate_KernelMc(KernelMc**, Dynamic*, NvU32); #define kmcIsPresent(pGpu, pEngstate) kmcIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS kmcPrepareForXVEReset_GK104(struct OBJGPU *pGpu, struct KernelMc *pKernelMc); + #ifdef __nvoc_kernel_mc_h_disabled static inline NV_STATUS kmcPrepareForXVEReset(struct OBJGPU *pGpu, struct KernelMc *pKernelMc) { NV_ASSERT_FAILED_PRECOMP("KernelMc was disabled!"); @@ -156,6 +157,7 @@ static inline NV_STATUS kmcPrepareForXVEReset(struct OBJGPU *pGpu, struct Kernel NV_STATUS kmcGetMcBar0MapInfo_GK104(struct OBJGPU *pGpu, struct KernelMc *pKernelMc, NvU64 *arg0, NvU32 *arg1); + #ifdef __nvoc_kernel_mc_h_disabled static inline NV_STATUS kmcGetMcBar0MapInfo(struct OBJGPU *pGpu, struct KernelMc *pKernelMc, NvU64 *arg0, NvU32 *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelMc was disabled!"); @@ -183,10 +185,6 @@ NV_STATUS kmcWritePmcEnableReg_GK104(struct OBJGPU *pGpu, struct KernelMc *pKern NV_STATUS kmcWritePmcEnableReg_GA100(struct OBJGPU *pGpu, struct KernelMc *pKernelMc, NvU32 arg0, NvBool arg1, NvBool arg2); -static inline NV_STATUS kmcWritePmcEnableReg_46f6a7(struct OBJGPU *pGpu, struct KernelMc *pKernelMc, NvU32 arg0, NvBool arg1, NvBool arg2) { - return NV_ERR_NOT_SUPPORTED; -} - static inline NV_STATUS kmcWritePmcEnableReg_DISPATCH(struct OBJGPU *pGpu, struct KernelMc *pKernelMc, NvU32 arg0, NvBool arg1, NvBool arg2) { return pKernelMc->__kmcWritePmcEnableReg__(pGpu, pKernelMc, arg0, arg1, arg2); } @@ -195,10 +193,6 @@ NvU32 kmcReadPmcEnableReg_GK104(struct OBJGPU *pGpu, struct KernelMc *pKernelMc, NvU32 kmcReadPmcEnableReg_GA100(struct OBJGPU *pGpu, struct KernelMc *pKernelMc, NvBool arg0); -static inline NvU32 kmcReadPmcEnableReg_4a4dee(struct OBJGPU *pGpu, struct KernelMc *pKernelMc, NvBool arg0) { - return 0; -} - static inline NvU32 kmcReadPmcEnableReg_DISPATCH(struct OBJGPU *pGpu, struct KernelMc *pKernelMc, NvBool arg0) { return pKernelMc->__kmcReadPmcEnableReg__(pGpu, pKernelMc, arg0); } diff --git a/src/nvidia/generated/g_kernel_mig_manager_nvoc.c b/src/nvidia/generated/g_kernel_mig_manager_nvoc.c index 82589addb..5d0ae8916 100644 --- a/src/nvidia/generated/g_kernel_mig_manager_nvoc.c +++ b/src/nvidia/generated/g_kernel_mig_manager_nvoc.c @@ -205,23 +205,17 @@ static void __nvoc_init_funcTable_KernelMIGManager_1(KernelMIGManager *pThis, Rm pThis->__kmigmgrStateUnload__ = &kmigmgrStateUnload_IMPL; // Hal function -- kmigmgrCreateGPUInstanceCheck - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kmigmgrCreateGPUInstanceCheck__ = &kmigmgrCreateGPUInstanceCheck_GA100; } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kmigmgrCreateGPUInstanceCheck__ = &kmigmgrCreateGPUInstanceCheck_46f6a7; } // Hal function -- kmigmgrIsDevinitMIGBitSet - if (0) - { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ { @@ -239,16 +233,10 @@ static void __nvoc_init_funcTable_KernelMIGManager_1(KernelMIGManager *pThis, Rm { pThis->__kmigmgrIsGPUInstanceCombinationValid__ = &kmigmgrIsGPUInstanceCombinationValid_GA100; } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kmigmgrIsGPUInstanceCombinationValid__ = &kmigmgrIsGPUInstanceCombinationValid_GH100; } - else if (0) - { - } // default else { @@ -260,13 +248,10 @@ static void __nvoc_init_funcTable_KernelMIGManager_1(KernelMIGManager *pThis, Rm { pThis->__kmigmgrIsGPUInstanceFlagValid__ = &kmigmgrIsGPUInstanceFlagValid_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__kmigmgrIsGPUInstanceFlagValid__ = &kmigmgrIsGPUInstanceFlagValid_GH100; } - else if (0) - { - } // default else { @@ -274,45 +259,33 @@ static void __nvoc_init_funcTable_KernelMIGManager_1(KernelMIGManager *pThis, Rm } // Hal function -- kmigmgrIsMemoryPartitioningRequested - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kmigmgrIsMemoryPartitioningRequested__ = &kmigmgrIsMemoryPartitioningRequested_GA100; } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kmigmgrIsMemoryPartitioningRequested__ = &kmigmgrIsMemoryPartitioningRequested_491d52; } // Hal function -- kmigmgrIsMemoryPartitioningNeeded - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kmigmgrIsMemoryPartitioningNeeded__ = &kmigmgrIsMemoryPartitioningNeeded_GA100; } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kmigmgrIsMemoryPartitioningNeeded__ = &kmigmgrIsMemoryPartitioningNeeded_491d52; } // Hal function -- kmigmgrMemSizeFlagToSwizzIdRange - if (0) + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000400UL) )) /* ChipHal: GA100 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { pThis->__kmigmgrMemSizeFlagToSwizzIdRange__ = &kmigmgrMemSizeFlagToSwizzIdRange_GA100; } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__kmigmgrMemSizeFlagToSwizzIdRange__ = &kmigmgrMemSizeFlagToSwizzIdRange_d64cd6; } diff --git a/src/nvidia/generated/g_kernel_mig_manager_nvoc.h b/src/nvidia/generated/g_kernel_mig_manager_nvoc.h index b28a3b51a..46cf1d165 100644 --- a/src/nvidia/generated/g_kernel_mig_manager_nvoc.h +++ b/src/nvidia/generated/g_kernel_mig_manager_nvoc.h @@ -41,6 +41,7 @@ extern "C" { #include "kernel/gpu/gr/kernel_graphics_manager.h" #include "kernel/gpu_mgr/gpu_mgr.h" #include "kernel/gpu/mmu/kern_gmmu.h" +#include "kernel/gpu/nvbitmask.h" #include "ctrl/ctrlc637.h" @@ -73,6 +74,10 @@ typedef struct MIG_GPU_INSTANCE MIG_GPU_INSTANCE; #define KMIGMGR_MAX_GPU_INSTANCES GPUMGR_MAX_GPU_INSTANCES #define KMIGMGR_MAX_COMPUTE_INSTANCES GPUMGR_MAX_COMPUTE_INSTANCES #define KMIGMGR_COMPUTE_INSTANCE_ID_INVALID 0xFFFFFFFF +#define KMIGMGR_COMPUTE_SIZE_INVALID NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE +#define KMIGMGR_MAX_GPU_CTSID 21 +#define KMIGMGR_CTSID_INVALID 0xFFFFFFFFUL +#define KMIGMGR_SPAN_OFFSET_INVALID KMIGMGR_CTSID_INVALID #define KMIGMGR_INSTANCE_ATTRIBUTION_ID_INVALID \ ((KMIGMGR_MAX_GPU_SWIZZID * KMIGMGR_MAX_GPU_SWIZZID) + \ @@ -138,11 +143,16 @@ typedef struct MIG_RESOURCE_ALLOCATION * Bitvector of local engine IDs associated with this instance. */ ENGTYPE_BIT_VECTOR localEngines; - + /*! * Virtualized GPC Count */ NvU32 virtualGpcCount; + + /*! + * Number of SMs + */ + NvU32 smCount; } MIG_RESOURCE_ALLOCATION; typedef struct MIG_COMPUTE_INSTANCE @@ -188,6 +198,21 @@ typedef struct MIG_COMPUTE_INSTANCE * Handles for RPC's into this instance */ KMIGMGR_INSTANCE_HANDLES instanceHandles; + + /*! + * Span start of this compute instance indicating the "position" of the + * instance within a GPU instance's view. For non-CTS ID enabled chips, + * this corresponds to the start of a VEID segment. For CTS-ID chips, this + * corresponds to the offset from the first CTS ID of a given profile size. + */ + NvU32 spanStart; + + /*! + * Compute Profile size associated with this MIG compute instance + * To associate an instance with a given compute profile, since a CTS + * ID may not have been assigned. + */ + NvU32 computeSize; } MIG_COMPUTE_INSTANCE; /*! @@ -202,21 +227,26 @@ typedef struct MIG_COMPUTE_INSTANCE * Parameter refers to saved compute instance data. Most resources claimed by new * compute instance are determined by the save data, and others are claimed via * allocator. + * requestFlags * TYPE_REQUEST_WITH_IDS * Parameter refers to request data passed in via EXEC_PARTITIONS_CREATE ctrl - * call. All resources claimed by new instance are chosen via allocator. + * call. All resources claimed by new instance are chosen via allocator unless + * the _AT_SPAN flag is also specified. * RM also tries to allocate instance with compute instance id * requested by user. This flag is only supported on vGPU enabled RM build * and will be removed when vgpu plugin implements virtualized compute * instance ID support. (bug 2938187) + * TYPE_REQUEST_AT_SPAN + * Parameter refers to request data passed in via EXEC_PARTITIONS_CREATE ctrl + * call. All resources claimed by new instance are attempt to be claimed by + * the RM allocater starting at the specified resource span. */ typedef struct KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS { enum { KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS_TYPE_REQUEST, - KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS_TYPE_RESTORE, - KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS_TYPE_REQUEST_WITH_IDS + KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS_TYPE_RESTORE } type; union { @@ -224,6 +254,7 @@ typedef struct KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS { NvU32 count; NVC637_CTRL_EXEC_PARTITIONS_INFO *pReqComputeInstanceInfo; + NvU32 requestFlags; } request; struct { @@ -232,6 +263,13 @@ typedef struct KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS } inst; } KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS; +typedef struct KMIGMGR_CONFIGURE_INSTANCE_PARAMS +{ + NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE profile; + NvU32 ctsId; + NvU32 veidSpanStart; +} KMIGMGR_CONFIGURE_INSTANCE_REQUEST; + typedef struct KERNEL_MIG_GPU_INSTANCE { /*! Structure containing GPU instance profile */ @@ -244,14 +282,14 @@ typedef struct KERNEL_MIG_GPU_INSTANCE /*! * Mask of physical engines in this GPU instance which are assigned exclusively - * to some compute instance. Indexed via NV2080_ENGINE_TYPE_* + * to some compute instance. Indexed via RM_ENGINE_TYPE_* */ ENGTYPE_BIT_VECTOR exclusiveEngMask; /*! * Mask of physical engines in this GPU instance which are assigned to at least * one compute instance, but may be assigned to others. - * Indexed via NV2080_ENGINE_TYPE_* + * Indexed via RM_ENGINE_TYPE_* */ ENGTYPE_BIT_VECTOR sharedEngMask; @@ -331,6 +369,21 @@ typedef struct KERNEL_MIG_GPU_INSTANCE * Handles for RPC's into this instance */ KMIGMGR_INSTANCE_HANDLES instanceHandles; + + /*! + * Mask of CTS IDs in use + */ + NvU64 ctsIdsInUseMask; + + /*! + * GR to CTS ID mapping + */ + NvU32 grCtsIdMap[KMIGMGR_MAX_COMPUTE_INSTANCES]; + + /*! + * Mask tracking which compute spans are currently in-use + */ + NvU32 spanInUseMask; } KERNEL_MIG_GPU_INSTANCE; /*! @@ -383,7 +436,7 @@ typedef struct KERNEL_MIG_MANAGER_STATIC_INFO NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS *pProfiles; /*! Mask of partitionable engines which are present on this GPU. */ - NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS *pPartitionableEngines; + NvU32 partitionableEngineMask[NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX]; /*! Per swizzId FB memory page ranges */ NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS *pSwizzIdFbMemPageRanges; @@ -446,6 +499,7 @@ struct KernelMIGManager { NvBool bReenableWatchdog; union ENGTYPE_BIT_VECTOR partitionableEnginesInUse; NvBool bDeviceProfilingInUse; + NvBool bMIGAutoOnlineEnabled; }; #ifndef __NVOC_CLASS_KernelMIGManager_TYPEDEF__ @@ -514,6 +568,7 @@ NV_STATUS __nvoc_objCreate_KernelMIGManager(KernelMIGManager**, Dynamic*, NvU32) #define kmigmgrIsPresent(pGpu, pEngstate) kmigmgrIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS kmigmgrLoadStaticInfo_KERNEL(OBJGPU *arg0, struct KernelMIGManager *arg1); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrLoadStaticInfo(OBJGPU *arg0, struct KernelMIGManager *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -529,6 +584,7 @@ static inline NV_STATUS kmigmgrSetStaticInfo_46f6a7(OBJGPU *arg0, struct KernelM return NV_ERR_NOT_SUPPORTED; } + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrSetStaticInfo(OBJGPU *arg0, struct KernelMIGManager *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -544,6 +600,7 @@ static inline void kmigmgrClearStaticInfo_b3696a(OBJGPU *arg0, struct KernelMIGM return; } + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline void kmigmgrClearStaticInfo(OBJGPU *arg0, struct KernelMIGManager *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -558,6 +615,7 @@ static inline NV_STATUS kmigmgrSaveToPersistenceFromVgpuStaticInfo_46f6a7(OBJGPU return NV_ERR_NOT_SUPPORTED; } + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrSaveToPersistenceFromVgpuStaticInfo(OBJGPU *arg0, struct KernelMIGManager *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -571,6 +629,7 @@ static inline NV_STATUS kmigmgrSaveToPersistenceFromVgpuStaticInfo(OBJGPU *arg0, NV_STATUS kmigmgrDeleteGPUInstanceRunlists_FWCLIENT(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrDeleteGPUInstanceRunlists(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -584,6 +643,7 @@ static inline NV_STATUS kmigmgrDeleteGPUInstanceRunlists(OBJGPU *arg0, struct Ke NV_STATUS kmigmgrCreateGPUInstanceRunlists_FWCLIENT(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrCreateGPUInstanceRunlists(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -597,6 +657,7 @@ static inline NV_STATUS kmigmgrCreateGPUInstanceRunlists(OBJGPU *arg0, struct Ke NV_STATUS kmigmgrRestoreFromPersistence_PF(OBJGPU *arg0, struct KernelMIGManager *arg1); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrRestoreFromPersistence(OBJGPU *arg0, struct KernelMIGManager *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -610,6 +671,7 @@ static inline NV_STATUS kmigmgrRestoreFromPersistence(OBJGPU *arg0, struct Kerne void kmigmgrDetectReducedConfig_KERNEL(OBJGPU *arg0, struct KernelMIGManager *arg1); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline void kmigmgrDetectReducedConfig(OBJGPU *arg0, struct KernelMIGManager *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -624,6 +686,7 @@ static inline NV_STATUS kmigmgrGenerateComputeInstanceUuid_5baef9(OBJGPU *arg0, NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrGenerateComputeInstanceUuid(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId, NvU32 globalGrIdx, NvUuid *pUuid) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -637,6 +700,7 @@ static inline NV_STATUS kmigmgrGenerateComputeInstanceUuid(OBJGPU *arg0, struct NV_STATUS kmigmgrCreateComputeInstances_FWCLIENT(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2, NvBool bQuery, KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS arg3, NvU32 *pCIIds, NvBool bCreateCap); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrCreateComputeInstances(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2, NvBool bQuery, KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS arg3, NvU32 *pCIIds, NvBool bCreateCap) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -650,6 +714,7 @@ static inline NV_STATUS kmigmgrCreateComputeInstances(OBJGPU *arg0, struct Kerne NV_STATUS kmigmgrSetMIGState_FWCLIENT(OBJGPU *arg0, struct KernelMIGManager *arg1, NvBool bMemoryPartitioningNeeded, NvBool bEnable, NvBool bUnload); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrSetMIGState(OBJGPU *arg0, struct KernelMIGManager *arg1, NvBool bMemoryPartitioningNeeded, NvBool bEnable, NvBool bUnload) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -661,6 +726,20 @@ static inline NV_STATUS kmigmgrSetMIGState(OBJGPU *arg0, struct KernelMIGManager #define kmigmgrSetMIGState_HAL(arg0, arg1, bMemoryPartitioningNeeded, bEnable, bUnload) kmigmgrSetMIGState(arg0, arg1, bMemoryPartitioningNeeded, bEnable, bUnload) +NvBool kmigmgrIsCTSAlignmentRequired_PF(OBJGPU *arg0, struct KernelMIGManager *arg1); + + +#ifdef __nvoc_kernel_mig_manager_h_disabled +static inline NvBool kmigmgrIsCTSAlignmentRequired(OBJGPU *arg0, struct KernelMIGManager *arg1) { + NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); + return NV_FALSE; +} +#else //__nvoc_kernel_mig_manager_h_disabled +#define kmigmgrIsCTSAlignmentRequired(arg0, arg1) kmigmgrIsCTSAlignmentRequired_PF(arg0, arg1) +#endif //__nvoc_kernel_mig_manager_h_disabled + +#define kmigmgrIsCTSAlignmentRequired_HAL(arg0, arg1) kmigmgrIsCTSAlignmentRequired(arg0, arg1) + NV_STATUS kmigmgrConstructEngine_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, ENGDESCRIPTOR arg2); static inline NV_STATUS kmigmgrConstructEngine_DISPATCH(OBJGPU *arg0, struct KernelMIGManager *arg1, ENGDESCRIPTOR arg2) { @@ -838,40 +917,58 @@ static inline NvBool kmigmgrIsA100ReducedConfig(OBJGPU *pGpu, struct KernelMIGMa } NV_STATUS kmigmgrIncRefCount_IMPL(struct RsShared *arg0); + #define kmigmgrIncRefCount(arg0) kmigmgrIncRefCount_IMPL(arg0) NV_STATUS kmigmgrDecRefCount_IMPL(struct RsShared *arg0); + #define kmigmgrDecRefCount(arg0) kmigmgrDecRefCount_IMPL(arg0) struct MIG_INSTANCE_REF kmigmgrMakeGIReference_IMPL(KERNEL_MIG_GPU_INSTANCE *arg0); + #define kmigmgrMakeGIReference(arg0) kmigmgrMakeGIReference_IMPL(arg0) struct MIG_INSTANCE_REF kmigmgrMakeCIReference_IMPL(KERNEL_MIG_GPU_INSTANCE *arg0, MIG_COMPUTE_INSTANCE *arg1); + #define kmigmgrMakeCIReference(arg0, arg1) kmigmgrMakeCIReference_IMPL(arg0, arg1) -NV_STATUS kmigmgrEngineTypeXlate_IMPL(union ENGTYPE_BIT_VECTOR *pSrc, NvU32 srcEngineType, union ENGTYPE_BIT_VECTOR *pDst, NvU32 *pDstEngineType); +NV_STATUS kmigmgrEngineTypeXlate_IMPL(union ENGTYPE_BIT_VECTOR *pSrc, RM_ENGINE_TYPE srcEngineType, union ENGTYPE_BIT_VECTOR *pDst, RM_ENGINE_TYPE *pDstEngineType); + #define kmigmgrEngineTypeXlate(pSrc, srcEngineType, pDst, pDstEngineType) kmigmgrEngineTypeXlate_IMPL(pSrc, srcEngineType, pDst, pDstEngineType) NvBool kmigmgrIsInstanceAttributionIdValid_IMPL(NvU16 id); + #define kmigmgrIsInstanceAttributionIdValid(id) kmigmgrIsInstanceAttributionIdValid_IMPL(id) struct MIG_INSTANCE_REF kmigmgrMakeNoMIGReference_IMPL(void); + #define kmigmgrMakeNoMIGReference() kmigmgrMakeNoMIGReference_IMPL() NvBool kmigmgrIsMIGReferenceValid_IMPL(struct MIG_INSTANCE_REF *arg0); + #define kmigmgrIsMIGReferenceValid(arg0) kmigmgrIsMIGReferenceValid_IMPL(arg0) NvBool kmigmgrAreMIGReferencesSame_IMPL(struct MIG_INSTANCE_REF *arg0, struct MIG_INSTANCE_REF *arg1); + #define kmigmgrAreMIGReferencesSame(arg0, arg1) kmigmgrAreMIGReferencesSame_IMPL(arg0, arg1) -NvU32 kmigmgrCountEnginesOfType_IMPL(const union ENGTYPE_BIT_VECTOR *arg0, NvU32 arg1); +NvU32 kmigmgrCountEnginesOfType_IMPL(const union ENGTYPE_BIT_VECTOR *arg0, RM_ENGINE_TYPE arg1); + #define kmigmgrCountEnginesOfType(arg0, arg1) kmigmgrCountEnginesOfType_IMPL(arg0, arg1) NvU16 kmigmgrGetAttributionIdFromMIGReference_IMPL(struct MIG_INSTANCE_REF arg0); + #define kmigmgrGetAttributionIdFromMIGReference(arg0) kmigmgrGetAttributionIdFromMIGReference_IMPL(arg0) NV_STATUS kmigmgrAllocateInstanceEngines_IMPL(union ENGTYPE_BIT_VECTOR *pSourceEngines, NvBool bShared, struct NV_RANGE engTypeRange, NvU32 reqEngCount, union ENGTYPE_BIT_VECTOR *pOutEngines, union ENGTYPE_BIT_VECTOR *pExclusiveEngines, union ENGTYPE_BIT_VECTOR *pSharedEngines); + #define kmigmgrAllocateInstanceEngines(pSourceEngines, bShared, engTypeRange, reqEngCount, pOutEngines, pExclusiveEngines, pSharedEngines) kmigmgrAllocateInstanceEngines_IMPL(pSourceEngines, bShared, engTypeRange, reqEngCount, pOutEngines, pExclusiveEngines, pSharedEngines) void kmigmgrGetLocalEngineMask_IMPL(union ENGTYPE_BIT_VECTOR *pPhysicalEngineMask, union ENGTYPE_BIT_VECTOR *pLocalEngineMask); + #define kmigmgrGetLocalEngineMask(pPhysicalEngineMask, pLocalEngineMask) kmigmgrGetLocalEngineMask_IMPL(pPhysicalEngineMask, pLocalEngineMask) NV_STATUS kmigmgrAllocGPUInstanceHandles_IMPL(OBJGPU *arg0, NvU32 swizzId, KERNEL_MIG_GPU_INSTANCE *arg1); + #define kmigmgrAllocGPUInstanceHandles(arg0, swizzId, arg1) kmigmgrAllocGPUInstanceHandles_IMPL(arg0, swizzId, arg1) void kmigmgrFreeGPUInstanceHandles_IMPL(KERNEL_MIG_GPU_INSTANCE *arg0); + #define kmigmgrFreeGPUInstanceHandles(arg0) kmigmgrFreeGPUInstanceHandles_IMPL(arg0) NvBool kmigmgrIsGPUInstanceReadyToBeDestroyed_IMPL(KERNEL_MIG_GPU_INSTANCE *arg0); + #define kmigmgrIsGPUInstanceReadyToBeDestroyed(arg0) kmigmgrIsGPUInstanceReadyToBeDestroyed_IMPL(arg0) void kmigmgrDestruct_IMPL(struct KernelMIGManager *arg0); + #define __nvoc_kmigmgrDestruct(arg0) kmigmgrDestruct_IMPL(arg0) void kmigmgrInitRegistryOverrides_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline void kmigmgrInitRegistryOverrides(OBJGPU *arg0, struct KernelMIGManager *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -881,6 +978,7 @@ static inline void kmigmgrInitRegistryOverrides(OBJGPU *arg0, struct KernelMIGMa #endif //__nvoc_kernel_mig_manager_h_disabled KERNEL_MIG_GPU_INSTANCE *kmigmgrGetMIGGpuInstanceSlot_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 i); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline KERNEL_MIG_GPU_INSTANCE *kmigmgrGetMIGGpuInstanceSlot(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 i) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -891,6 +989,7 @@ static inline KERNEL_MIG_GPU_INSTANCE *kmigmgrGetMIGGpuInstanceSlot(OBJGPU *arg0 #endif //__nvoc_kernel_mig_manager_h_disabled NvBool kmigmgrIsMIGSupported_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NvBool kmigmgrIsMIGSupported(OBJGPU *arg0, struct KernelMIGManager *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -901,6 +1000,7 @@ static inline NvBool kmigmgrIsMIGSupported(OBJGPU *arg0, struct KernelMIGManager #endif //__nvoc_kernel_mig_manager_h_disabled NvBool kmigmgrIsMIGEnabled_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NvBool kmigmgrIsMIGEnabled(OBJGPU *arg0, struct KernelMIGManager *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -911,6 +1011,7 @@ static inline NvBool kmigmgrIsMIGEnabled(OBJGPU *arg0, struct KernelMIGManager * #endif //__nvoc_kernel_mig_manager_h_disabled NvBool kmigmgrIsMIGGpuInstancingEnabled_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NvBool kmigmgrIsMIGGpuInstancingEnabled(OBJGPU *arg0, struct KernelMIGManager *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -921,6 +1022,7 @@ static inline NvBool kmigmgrIsMIGGpuInstancingEnabled(OBJGPU *arg0, struct Kerne #endif //__nvoc_kernel_mig_manager_h_disabled NvBool kmigmgrIsMIGMemPartitioningEnabled_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NvBool kmigmgrIsMIGMemPartitioningEnabled(OBJGPU *arg0, struct KernelMIGManager *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -931,6 +1033,7 @@ static inline NvBool kmigmgrIsMIGMemPartitioningEnabled(OBJGPU *arg0, struct Ker #endif //__nvoc_kernel_mig_manager_h_disabled const KERNEL_MIG_MANAGER_STATIC_INFO *kmigmgrGetStaticInfo_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline const KERNEL_MIG_MANAGER_STATIC_INFO *kmigmgrGetStaticInfo(OBJGPU *arg0, struct KernelMIGManager *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -941,6 +1044,7 @@ static inline const KERNEL_MIG_MANAGER_STATIC_INFO *kmigmgrGetStaticInfo(OBJGPU #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrSaveToPersistence_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrSaveToPersistence(OBJGPU *arg0, struct KernelMIGManager *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -951,6 +1055,7 @@ static inline NV_STATUS kmigmgrSaveToPersistence(OBJGPU *arg0, struct KernelMIGM #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrDisableWatchdog_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrDisableWatchdog(OBJGPU *arg0, struct KernelMIGManager *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -961,6 +1066,7 @@ static inline NV_STATUS kmigmgrDisableWatchdog(OBJGPU *arg0, struct KernelMIGMan #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrRestoreWatchdog_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrRestoreWatchdog(OBJGPU *arg0, struct KernelMIGManager *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -971,6 +1077,7 @@ static inline NV_STATUS kmigmgrRestoreWatchdog(OBJGPU *arg0, struct KernelMIGMan #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrSetSwizzIdInUse_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrSetSwizzIdInUse(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -981,6 +1088,7 @@ static inline NV_STATUS kmigmgrSetSwizzIdInUse(OBJGPU *arg0, struct KernelMIGMan #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrClearSwizzIdInUse_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrClearSwizzIdInUse(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -991,6 +1099,7 @@ static inline NV_STATUS kmigmgrClearSwizzIdInUse(OBJGPU *arg0, struct KernelMIGM #endif //__nvoc_kernel_mig_manager_h_disabled NvBool kmigmgrIsSwizzIdInUse_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NvBool kmigmgrIsSwizzIdInUse(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1001,6 +1110,7 @@ static inline NvBool kmigmgrIsSwizzIdInUse(OBJGPU *arg0, struct KernelMIGManager #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrGetInvalidSwizzIdMask_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId, NvU64 *pUnsupportedSwizzIdMask); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrGetInvalidSwizzIdMask(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId, NvU64 *pUnsupportedSwizzIdMask) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1011,6 +1121,7 @@ static inline NV_STATUS kmigmgrGetInvalidSwizzIdMask(OBJGPU *arg0, struct Kernel #endif //__nvoc_kernel_mig_manager_h_disabled NvBool kmigmgrIsMIGNvlinkP2PSupported_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NvBool kmigmgrIsMIGNvlinkP2PSupported(OBJGPU *arg0, struct KernelMIGManager *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1021,6 +1132,7 @@ static inline NvBool kmigmgrIsMIGNvlinkP2PSupported(OBJGPU *arg0, struct KernelM #endif //__nvoc_kernel_mig_manager_h_disabled NvU64 kmigmgrGetSwizzIdInUseMask_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NvU64 kmigmgrGetSwizzIdInUseMask(OBJGPU *arg0, struct KernelMIGManager *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1031,6 +1143,7 @@ static inline NvU64 kmigmgrGetSwizzIdInUseMask(OBJGPU *arg0, struct KernelMIGMan #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrSetEnginesInUse_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, union ENGTYPE_BIT_VECTOR *pEngines); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrSetEnginesInUse(OBJGPU *arg0, struct KernelMIGManager *arg1, union ENGTYPE_BIT_VECTOR *pEngines) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1041,6 +1154,7 @@ static inline NV_STATUS kmigmgrSetEnginesInUse(OBJGPU *arg0, struct KernelMIGMan #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrClearEnginesInUse_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, union ENGTYPE_BIT_VECTOR *pEngines); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrClearEnginesInUse(OBJGPU *arg0, struct KernelMIGManager *arg1, union ENGTYPE_BIT_VECTOR *pEngines) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1050,37 +1164,41 @@ static inline NV_STATUS kmigmgrClearEnginesInUse(OBJGPU *arg0, struct KernelMIGM #define kmigmgrClearEnginesInUse(arg0, arg1, pEngines) kmigmgrClearEnginesInUse_IMPL(arg0, arg1, pEngines) #endif //__nvoc_kernel_mig_manager_h_disabled -NvBool kmigmgrIsEngineInUse_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 engineType); +NvBool kmigmgrIsEngineInUse_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, RM_ENGINE_TYPE rmEngineType); + #ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NvBool kmigmgrIsEngineInUse(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 engineType) { +static inline NvBool kmigmgrIsEngineInUse(OBJGPU *arg0, struct KernelMIGManager *arg1, RM_ENGINE_TYPE rmEngineType) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); return NV_FALSE; } #else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrIsEngineInUse(arg0, arg1, engineType) kmigmgrIsEngineInUse_IMPL(arg0, arg1, engineType) +#define kmigmgrIsEngineInUse(arg0, arg1, rmEngineType) kmigmgrIsEngineInUse_IMPL(arg0, arg1, rmEngineType) #endif //__nvoc_kernel_mig_manager_h_disabled -NvBool kmigmgrIsEnginePartitionable_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 engineType); +NvBool kmigmgrIsEnginePartitionable_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, RM_ENGINE_TYPE rmEngineType); + #ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NvBool kmigmgrIsEnginePartitionable(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 engineType) { +static inline NvBool kmigmgrIsEnginePartitionable(OBJGPU *arg0, struct KernelMIGManager *arg1, RM_ENGINE_TYPE rmEngineType) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); return NV_FALSE; } #else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrIsEnginePartitionable(arg0, arg1, engineType) kmigmgrIsEnginePartitionable_IMPL(arg0, arg1, engineType) +#define kmigmgrIsEnginePartitionable(arg0, arg1, rmEngineType) kmigmgrIsEnginePartitionable_IMPL(arg0, arg1, rmEngineType) #endif //__nvoc_kernel_mig_manager_h_disabled -NvBool kmigmgrIsEngineInInstance_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 globalEngType, struct MIG_INSTANCE_REF arg2); +NvBool kmigmgrIsEngineInInstance_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, RM_ENGINE_TYPE globalRmEngType, struct MIG_INSTANCE_REF arg2); + #ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NvBool kmigmgrIsEngineInInstance(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 globalEngType, struct MIG_INSTANCE_REF arg2) { +static inline NvBool kmigmgrIsEngineInInstance(OBJGPU *arg0, struct KernelMIGManager *arg1, RM_ENGINE_TYPE globalRmEngType, struct MIG_INSTANCE_REF arg2) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); return NV_FALSE; } #else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrIsEngineInInstance(arg0, arg1, globalEngType, arg2) kmigmgrIsEngineInInstance_IMPL(arg0, arg1, globalEngType, arg2) +#define kmigmgrIsEngineInInstance(arg0, arg1, globalRmEngType, arg2) kmigmgrIsEngineInInstance_IMPL(arg0, arg1, globalRmEngType, arg2) #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrGetFreeEngines_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 engineCount, struct NV_RANGE engineRange, union ENGTYPE_BIT_VECTOR *pInstanceEngines); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrGetFreeEngines(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 engineCount, struct NV_RANGE engineRange, union ENGTYPE_BIT_VECTOR *pInstanceEngines) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1091,6 +1209,7 @@ static inline NV_STATUS kmigmgrGetFreeEngines(OBJGPU *arg0, struct KernelMIGMana #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrCreateGPUInstance_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 *pSwizzId, KMIGMGR_CREATE_GPU_INSTANCE_PARAMS arg2, NvBool bValid, NvBool bCreateCap); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrCreateGPUInstance(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 *pSwizzId, KMIGMGR_CREATE_GPU_INSTANCE_PARAMS arg2, NvBool bValid, NvBool bCreateCap) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1101,6 +1220,7 @@ static inline NV_STATUS kmigmgrCreateGPUInstance(OBJGPU *arg0, struct KernelMIGM #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrInvalidateGPUInstance_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId, NvBool bUnload); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrInvalidateGPUInstance(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId, NvBool bUnload) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1111,6 +1231,7 @@ static inline NV_STATUS kmigmgrInvalidateGPUInstance(OBJGPU *arg0, struct Kernel #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrInitGPUInstanceScrubber_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrInitGPUInstanceScrubber(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1121,6 +1242,7 @@ static inline NV_STATUS kmigmgrInitGPUInstanceScrubber(OBJGPU *arg0, struct Kern #endif //__nvoc_kernel_mig_manager_h_disabled void kmigmgrDestroyGPUInstanceScrubber_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline void kmigmgrDestroyGPUInstanceScrubber(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1130,6 +1252,7 @@ static inline void kmigmgrDestroyGPUInstanceScrubber(OBJGPU *arg0, struct Kernel #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrInitGPUInstanceBufPools_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrInitGPUInstanceBufPools(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1140,6 +1263,7 @@ static inline NV_STATUS kmigmgrInitGPUInstanceBufPools(OBJGPU *arg0, struct Kern #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrInitGPUInstanceGrBufPools_IMPL(OBJGPU *pGpu, struct KernelMIGManager *arg0, KERNEL_MIG_GPU_INSTANCE *arg1); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrInitGPUInstanceGrBufPools(OBJGPU *pGpu, struct KernelMIGManager *arg0, KERNEL_MIG_GPU_INSTANCE *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1150,6 +1274,7 @@ static inline NV_STATUS kmigmgrInitGPUInstanceGrBufPools(OBJGPU *pGpu, struct Ke #endif //__nvoc_kernel_mig_manager_h_disabled void kmigmgrDestroyGPUInstanceGrBufPools_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline void kmigmgrDestroyGPUInstanceGrBufPools(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1159,6 +1284,7 @@ static inline void kmigmgrDestroyGPUInstanceGrBufPools(OBJGPU *arg0, struct Kern #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrInitGPUInstancePool_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrInitGPUInstancePool(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1169,6 +1295,7 @@ static inline NV_STATUS kmigmgrInitGPUInstancePool(OBJGPU *arg0, struct KernelMI #endif //__nvoc_kernel_mig_manager_h_disabled void kmigmgrDestroyGPUInstancePool_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline void kmigmgrDestroyGPUInstancePool(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1178,6 +1305,7 @@ static inline void kmigmgrDestroyGPUInstancePool(OBJGPU *arg0, struct KernelMIGM #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrInitGPUInstanceRunlistBufPools_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrInitGPUInstanceRunlistBufPools(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1188,6 +1316,7 @@ static inline NV_STATUS kmigmgrInitGPUInstanceRunlistBufPools(OBJGPU *arg0, stru #endif //__nvoc_kernel_mig_manager_h_disabled void kmigmgrDestroyGPUInstanceRunlistBufPools_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline void kmigmgrDestroyGPUInstanceRunlistBufPools(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1197,6 +1326,7 @@ static inline void kmigmgrDestroyGPUInstanceRunlistBufPools(OBJGPU *arg0, struct #endif //__nvoc_kernel_mig_manager_h_disabled void kmigmgrPrintSubscribingClients_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline void kmigmgrPrintSubscribingClients(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1206,6 +1336,7 @@ static inline void kmigmgrPrintSubscribingClients(OBJGPU *arg0, struct KernelMIG #endif //__nvoc_kernel_mig_manager_h_disabled void kmigmgrInitGPUInstanceInfo_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline void kmigmgrInitGPUInstanceInfo(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1215,6 +1346,7 @@ static inline void kmigmgrInitGPUInstanceInfo(OBJGPU *arg0, struct KernelMIGMana #endif //__nvoc_kernel_mig_manager_h_disabled void kmigmgrTrimInstanceRunlistBufPools_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline void kmigmgrTrimInstanceRunlistBufPools(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1224,6 +1356,7 @@ static inline void kmigmgrTrimInstanceRunlistBufPools(OBJGPU *arg0, struct Kerne #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrSetDeviceProfilingInUse_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrSetDeviceProfilingInUse(OBJGPU *arg0, struct KernelMIGManager *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1234,6 +1367,7 @@ static inline NV_STATUS kmigmgrSetDeviceProfilingInUse(OBJGPU *arg0, struct Kern #endif //__nvoc_kernel_mig_manager_h_disabled void kmigmgrClearDeviceProfilingInUse_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline void kmigmgrClearDeviceProfilingInUse(OBJGPU *arg0, struct KernelMIGManager *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1243,6 +1377,7 @@ static inline void kmigmgrClearDeviceProfilingInUse(OBJGPU *arg0, struct KernelM #endif //__nvoc_kernel_mig_manager_h_disabled NvBool kmigmgrIsDeviceProfilingInUse_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NvBool kmigmgrIsDeviceProfilingInUse(OBJGPU *arg0, struct KernelMIGManager *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1253,6 +1388,7 @@ static inline NvBool kmigmgrIsDeviceProfilingInUse(OBJGPU *arg0, struct KernelMI #endif //__nvoc_kernel_mig_manager_h_disabled NvBool kmigmgrIsClientUsingDeviceProfiling_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NvBool kmigmgrIsClientUsingDeviceProfiling(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1263,6 +1399,7 @@ static inline NvBool kmigmgrIsClientUsingDeviceProfiling(OBJGPU *arg0, struct Ke #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrEnableAllLCEs_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvBool bEnableAllLCEs); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrEnableAllLCEs(OBJGPU *arg0, struct KernelMIGManager *arg1, NvBool bEnableAllLCEs) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1273,6 +1410,7 @@ static inline NV_STATUS kmigmgrEnableAllLCEs(OBJGPU *arg0, struct KernelMIGManag #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrGetInstanceRefFromClient_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, struct MIG_INSTANCE_REF *arg2); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrGetInstanceRefFromClient(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, struct MIG_INSTANCE_REF *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1283,6 +1421,7 @@ static inline NV_STATUS kmigmgrGetInstanceRefFromClient(OBJGPU *arg0, struct Ker #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrGetMemoryPartitionHeapFromClient_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, struct Heap **arg2); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrGetMemoryPartitionHeapFromClient(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, struct Heap **arg2) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1293,6 +1432,7 @@ static inline NV_STATUS kmigmgrGetMemoryPartitionHeapFromClient(OBJGPU *arg0, st #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrGetSwizzIdFromClient_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, NvU32 *pSwizzId); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrGetSwizzIdFromClient(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, NvU32 *pSwizzId) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1303,6 +1443,7 @@ static inline NV_STATUS kmigmgrGetSwizzIdFromClient(OBJGPU *arg0, struct KernelM #endif //__nvoc_kernel_mig_manager_h_disabled void kmigmgrPrintGPUInstanceInfo_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline void kmigmgrPrintGPUInstanceInfo(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1312,6 +1453,7 @@ static inline void kmigmgrPrintGPUInstanceInfo(OBJGPU *arg0, struct KernelMIGMan #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrSetGPUInstanceInfo_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId, KMIGMGR_CREATE_GPU_INSTANCE_PARAMS arg2); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrSetGPUInstanceInfo(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId, KMIGMGR_CREATE_GPU_INSTANCE_PARAMS arg2) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1322,6 +1464,7 @@ static inline NV_STATUS kmigmgrSetGPUInstanceInfo(OBJGPU *arg0, struct KernelMIG #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrGetGPUInstanceInfo_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId, KERNEL_MIG_GPU_INSTANCE **arg2); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrGetGPUInstanceInfo(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId, KERNEL_MIG_GPU_INSTANCE **arg2) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1331,9 +1474,10 @@ static inline NV_STATUS kmigmgrGetGPUInstanceInfo(OBJGPU *arg0, struct KernelMIG #define kmigmgrGetGPUInstanceInfo(arg0, arg1, swizzId, arg2) kmigmgrGetGPUInstanceInfo_IMPL(arg0, arg1, swizzId, arg2) #endif //__nvoc_kernel_mig_manager_h_disabled -NV_STATUS kmigmgrGetLocalToGlobalEngineType_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, struct MIG_INSTANCE_REF arg2, NvU32 localEngType, NvU32 *pGlobalEngType); +NV_STATUS kmigmgrGetLocalToGlobalEngineType_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, struct MIG_INSTANCE_REF arg2, RM_ENGINE_TYPE localEngType, RM_ENGINE_TYPE *pGlobalEngType); + #ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrGetLocalToGlobalEngineType(OBJGPU *arg0, struct KernelMIGManager *arg1, struct MIG_INSTANCE_REF arg2, NvU32 localEngType, NvU32 *pGlobalEngType) { +static inline NV_STATUS kmigmgrGetLocalToGlobalEngineType(OBJGPU *arg0, struct KernelMIGManager *arg1, struct MIG_INSTANCE_REF arg2, RM_ENGINE_TYPE localEngType, RM_ENGINE_TYPE *pGlobalEngType) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1341,9 +1485,10 @@ static inline NV_STATUS kmigmgrGetLocalToGlobalEngineType(OBJGPU *arg0, struct K #define kmigmgrGetLocalToGlobalEngineType(arg0, arg1, arg2, localEngType, pGlobalEngType) kmigmgrGetLocalToGlobalEngineType_IMPL(arg0, arg1, arg2, localEngType, pGlobalEngType) #endif //__nvoc_kernel_mig_manager_h_disabled -NV_STATUS kmigmgrGetGlobalToLocalEngineType_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, struct MIG_INSTANCE_REF arg2, NvU32 globalEngType, NvU32 *pLocalEngType); +NV_STATUS kmigmgrGetGlobalToLocalEngineType_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, struct MIG_INSTANCE_REF arg2, RM_ENGINE_TYPE globalEngType, RM_ENGINE_TYPE *pLocalEngType); + #ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrGetGlobalToLocalEngineType(OBJGPU *arg0, struct KernelMIGManager *arg1, struct MIG_INSTANCE_REF arg2, NvU32 globalEngType, NvU32 *pLocalEngType) { +static inline NV_STATUS kmigmgrGetGlobalToLocalEngineType(OBJGPU *arg0, struct KernelMIGManager *arg1, struct MIG_INSTANCE_REF arg2, RM_ENGINE_TYPE globalEngType, RM_ENGINE_TYPE *pLocalEngType) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1351,9 +1496,10 @@ static inline NV_STATUS kmigmgrGetGlobalToLocalEngineType(OBJGPU *arg0, struct K #define kmigmgrGetGlobalToLocalEngineType(arg0, arg1, arg2, globalEngType, pLocalEngType) kmigmgrGetGlobalToLocalEngineType_IMPL(arg0, arg1, arg2, globalEngType, pLocalEngType) #endif //__nvoc_kernel_mig_manager_h_disabled -NV_STATUS kmigmgrFilterEngineList_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Subdevice *arg2, NvU32 *pEngineTypes, NvU32 *pEngineCount); +NV_STATUS kmigmgrFilterEngineList_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Subdevice *arg2, RM_ENGINE_TYPE *pEngineTypes, NvU32 *pEngineCount); + #ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrFilterEngineList(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Subdevice *arg2, NvU32 *pEngineTypes, NvU32 *pEngineCount) { +static inline NV_STATUS kmigmgrFilterEngineList(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Subdevice *arg2, RM_ENGINE_TYPE *pEngineTypes, NvU32 *pEngineCount) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1362,6 +1508,7 @@ static inline NV_STATUS kmigmgrFilterEngineList(OBJGPU *arg0, struct KernelMIGMa #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrFilterEnginePartnerList_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Subdevice *arg2, NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS *arg3); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrFilterEnginePartnerList(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Subdevice *arg2, NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS *arg3) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1372,6 +1519,7 @@ static inline NV_STATUS kmigmgrFilterEnginePartnerList(OBJGPU *arg0, struct Kern #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrGetProfileByPartitionFlag_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 partitionFlag, const NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO **arg2); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrGetProfileByPartitionFlag(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 partitionFlag, const NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO **arg2) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1382,6 +1530,7 @@ static inline NV_STATUS kmigmgrGetProfileByPartitionFlag(OBJGPU *arg0, struct Ke #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrSaveComputeInstances_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2, GPUMGR_SAVE_COMPUTE_INSTANCE *arg3); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrSaveComputeInstances(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2, GPUMGR_SAVE_COMPUTE_INSTANCE *arg3) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1392,6 +1541,7 @@ static inline NV_STATUS kmigmgrSaveComputeInstances(OBJGPU *arg0, struct KernelM #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrSetPartitioningMode_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrSetPartitioningMode(OBJGPU *arg0, struct KernelMIGManager *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1401,17 +1551,19 @@ static inline NV_STATUS kmigmgrSetPartitioningMode(OBJGPU *arg0, struct KernelMI #define kmigmgrSetPartitioningMode(arg0, arg1) kmigmgrSetPartitioningMode_IMPL(arg0, arg1) #endif //__nvoc_kernel_mig_manager_h_disabled -NV_STATUS kmigmgrGetMIGReferenceFromEngineType_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 engineType, struct MIG_INSTANCE_REF *arg2); +NV_STATUS kmigmgrGetMIGReferenceFromEngineType_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, RM_ENGINE_TYPE rmEngineType, struct MIG_INSTANCE_REF *arg2); + #ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrGetMIGReferenceFromEngineType(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 engineType, struct MIG_INSTANCE_REF *arg2) { +static inline NV_STATUS kmigmgrGetMIGReferenceFromEngineType(OBJGPU *arg0, struct KernelMIGManager *arg1, RM_ENGINE_TYPE rmEngineType, struct MIG_INSTANCE_REF *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrGetMIGReferenceFromEngineType(arg0, arg1, engineType, arg2) kmigmgrGetMIGReferenceFromEngineType_IMPL(arg0, arg1, engineType, arg2) +#define kmigmgrGetMIGReferenceFromEngineType(arg0, arg1, rmEngineType, arg2) kmigmgrGetMIGReferenceFromEngineType_IMPL(arg0, arg1, rmEngineType, arg2) #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrGetGPUInstanceScrubberCe_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, NvU32 *ceInst); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrGetGPUInstanceScrubberCe(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, NvU32 *ceInst) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1422,6 +1574,7 @@ static inline NV_STATUS kmigmgrGetGPUInstanceScrubberCe(OBJGPU *arg0, struct Ker #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrDescribeGPUInstances_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS *arg2); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrDescribeGPUInstances(OBJGPU *arg0, struct KernelMIGManager *arg1, NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1432,6 +1585,7 @@ static inline NV_STATUS kmigmgrDescribeGPUInstances(OBJGPU *arg0, struct KernelM #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrSwizzIdToResourceAllocation_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId, KMIGMGR_CREATE_GPU_INSTANCE_PARAMS arg2, KERNEL_MIG_GPU_INSTANCE *arg3, MIG_RESOURCE_ALLOCATION *arg4); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrSwizzIdToResourceAllocation(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId, KMIGMGR_CREATE_GPU_INSTANCE_PARAMS arg2, KERNEL_MIG_GPU_INSTANCE *arg3, MIG_RESOURCE_ALLOCATION *arg4) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1442,6 +1596,7 @@ static inline NV_STATUS kmigmgrSwizzIdToResourceAllocation(OBJGPU *arg0, struct #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrAllocComputeInstanceHandles_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2, MIG_COMPUTE_INSTANCE *arg3); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrAllocComputeInstanceHandles(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2, MIG_COMPUTE_INSTANCE *arg3) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1452,6 +1607,7 @@ static inline NV_STATUS kmigmgrAllocComputeInstanceHandles(OBJGPU *arg0, struct #endif //__nvoc_kernel_mig_manager_h_disabled void kmigmgrFreeComputeInstanceHandles_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2, MIG_COMPUTE_INSTANCE *arg3); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline void kmigmgrFreeComputeInstanceHandles(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2, MIG_COMPUTE_INSTANCE *arg3) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1461,6 +1617,7 @@ static inline void kmigmgrFreeComputeInstanceHandles(OBJGPU *arg0, struct Kernel #endif //__nvoc_kernel_mig_manager_h_disabled void kmigmgrReleaseComputeInstanceEngines_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2, MIG_COMPUTE_INSTANCE *arg3); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline void kmigmgrReleaseComputeInstanceEngines(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2, MIG_COMPUTE_INSTANCE *arg3) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1470,6 +1627,7 @@ static inline void kmigmgrReleaseComputeInstanceEngines(OBJGPU *arg0, struct Ker #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrDeleteComputeInstance_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2, NvU32 CIId, NvBool bUnload); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrDeleteComputeInstance(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2, NvU32 CIId, NvBool bUnload) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1479,17 +1637,19 @@ static inline NV_STATUS kmigmgrDeleteComputeInstance(OBJGPU *arg0, struct Kernel #define kmigmgrDeleteComputeInstance(arg0, arg1, arg2, CIId, bUnload) kmigmgrDeleteComputeInstance_IMPL(arg0, arg1, arg2, CIId, bUnload) #endif //__nvoc_kernel_mig_manager_h_disabled -NV_STATUS kmigmgrConfigureGPUInstance_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId, NvU32 *pGpcCountPerGr, NvU32 updateEngMask); +NV_STATUS kmigmgrConfigureGPUInstance_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId, const KMIGMGR_CONFIGURE_INSTANCE_REQUEST *pConfigRequestPerCi, NvU32 updateEngMask); + #ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrConfigureGPUInstance(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId, NvU32 *pGpcCountPerGr, NvU32 updateEngMask) { +static inline NV_STATUS kmigmgrConfigureGPUInstance(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId, const KMIGMGR_CONFIGURE_INSTANCE_REQUEST *pConfigRequestPerCi, NvU32 updateEngMask) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrConfigureGPUInstance(arg0, arg1, swizzId, pGpcCountPerGr, updateEngMask) kmigmgrConfigureGPUInstance_IMPL(arg0, arg1, swizzId, pGpcCountPerGr, updateEngMask) +#define kmigmgrConfigureGPUInstance(arg0, arg1, swizzId, pConfigRequestPerCi, updateEngMask) kmigmgrConfigureGPUInstance_IMPL(arg0, arg1, swizzId, pConfigRequestPerCi, updateEngMask) #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrInvalidateGrGpcMapping_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2, NvU32 grIdx); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrInvalidateGrGpcMapping(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2, NvU32 grIdx) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1500,6 +1660,7 @@ static inline NV_STATUS kmigmgrInvalidateGrGpcMapping(OBJGPU *arg0, struct Kerne #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrInvalidateGr_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2, NvU32 grIdx); + #ifdef __nvoc_kernel_mig_manager_h_disabled static inline NV_STATUS kmigmgrInvalidateGr(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2, NvU32 grIdx) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); @@ -1509,6 +1670,150 @@ static inline NV_STATUS kmigmgrInvalidateGr(OBJGPU *arg0, struct KernelMIGManage #define kmigmgrInvalidateGr(arg0, arg1, arg2, grIdx) kmigmgrInvalidateGr_IMPL(arg0, arg1, arg2, grIdx) #endif //__nvoc_kernel_mig_manager_h_disabled +NvU32 kmigmgrGetNextComputeSize_IMPL(NvBool bGetNextSmallest, NvU32 computeSize); + +#define kmigmgrGetNextComputeSize(bGetNextSmallest, computeSize) kmigmgrGetNextComputeSize_IMPL(bGetNextSmallest, computeSize) +NV_STATUS kmigmgrGetSkylineFromSize_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 computeSize, const NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO **ppSkyline); + +#ifdef __nvoc_kernel_mig_manager_h_disabled +static inline NV_STATUS kmigmgrGetSkylineFromSize(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 computeSize, const NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO **ppSkyline) { + NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_mig_manager_h_disabled +#define kmigmgrGetSkylineFromSize(arg0, arg1, computeSize, ppSkyline) kmigmgrGetSkylineFromSize_IMPL(arg0, arg1, computeSize, ppSkyline) +#endif //__nvoc_kernel_mig_manager_h_disabled + +NV_STATUS kmigmgrGetComputeProfileFromSize_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 computeSize, NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE *pProfile); + +#ifdef __nvoc_kernel_mig_manager_h_disabled +static inline NV_STATUS kmigmgrGetComputeProfileFromSize(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 computeSize, NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE *pProfile) { + NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_mig_manager_h_disabled +#define kmigmgrGetComputeProfileFromSize(arg0, arg1, computeSize, pProfile) kmigmgrGetComputeProfileFromSize_IMPL(arg0, arg1, computeSize, pProfile) +#endif //__nvoc_kernel_mig_manager_h_disabled + +NV_STATUS kmigmgrGetComputeProfileFromSmCount_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 smCount, NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE *pProfile); + +#ifdef __nvoc_kernel_mig_manager_h_disabled +static inline NV_STATUS kmigmgrGetComputeProfileFromSmCount(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 smCount, NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE *pProfile) { + NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_mig_manager_h_disabled +#define kmigmgrGetComputeProfileFromSmCount(arg0, arg1, smCount, pProfile) kmigmgrGetComputeProfileFromSmCount_IMPL(arg0, arg1, smCount, pProfile) +#endif //__nvoc_kernel_mig_manager_h_disabled + +NV_STATUS kmigmgrGetComputeProfileFromGpcCount_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 gpcCount, NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE *pProfile); + +#ifdef __nvoc_kernel_mig_manager_h_disabled +static inline NV_STATUS kmigmgrGetComputeProfileFromGpcCount(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 gpcCount, NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE *pProfile) { + NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_mig_manager_h_disabled +#define kmigmgrGetComputeProfileFromGpcCount(arg0, arg1, gpcCount, pProfile) kmigmgrGetComputeProfileFromGpcCount_IMPL(arg0, arg1, gpcCount, pProfile) +#endif //__nvoc_kernel_mig_manager_h_disabled + +NV_STATUS kmigmgrGetComputeProfileFromCTSId_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 ctsId, NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE *pProfile); + +#ifdef __nvoc_kernel_mig_manager_h_disabled +static inline NV_STATUS kmigmgrGetComputeProfileFromCTSId(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 ctsId, NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE *pProfile) { + NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_mig_manager_h_disabled +#define kmigmgrGetComputeProfileFromCTSId(arg0, arg1, ctsId, pProfile) kmigmgrGetComputeProfileFromCTSId_IMPL(arg0, arg1, ctsId, pProfile) +#endif //__nvoc_kernel_mig_manager_h_disabled + +NV_STATUS kmigmgrGetInvalidCTSIdMask_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 ctsId, NvU64 *pInvalidCTSIdMask); + +#ifdef __nvoc_kernel_mig_manager_h_disabled +static inline NV_STATUS kmigmgrGetInvalidCTSIdMask(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 ctsId, NvU64 *pInvalidCTSIdMask) { + NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_mig_manager_h_disabled +#define kmigmgrGetInvalidCTSIdMask(arg0, arg1, ctsId, pInvalidCTSIdMask) kmigmgrGetInvalidCTSIdMask_IMPL(arg0, arg1, ctsId, pInvalidCTSIdMask) +#endif //__nvoc_kernel_mig_manager_h_disabled + +struct NV_RANGE kmigmgrComputeProfileSizeToCTSIdRange_IMPL(NvU32 computeSize); + +#define kmigmgrComputeProfileSizeToCTSIdRange(computeSize) kmigmgrComputeProfileSizeToCTSIdRange_IMPL(computeSize) +NV_STATUS kmigmgrGetFreeCTSId_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 *pCtsId, NvU64 globalValidCtsMask, NvU64 ctsIdInUseMask, NvU32 profileSize); + +#ifdef __nvoc_kernel_mig_manager_h_disabled +static inline NV_STATUS kmigmgrGetFreeCTSId(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 *pCtsId, NvU64 globalValidCtsMask, NvU64 ctsIdInUseMask, NvU32 profileSize) { + NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_mig_manager_h_disabled +#define kmigmgrGetFreeCTSId(arg0, arg1, pCtsId, globalValidCtsMask, ctsIdInUseMask, profileSize) kmigmgrGetFreeCTSId_IMPL(arg0, arg1, pCtsId, globalValidCtsMask, ctsIdInUseMask, profileSize) +#endif //__nvoc_kernel_mig_manager_h_disabled + +NvU32 kmigmgrGetComputeSizeFromCTSId_IMPL(NvU32 ctsId); + +#define kmigmgrGetComputeSizeFromCTSId(ctsId) kmigmgrGetComputeSizeFromCTSId_IMPL(ctsId) +NvU32 kmigmgrSmallestComputeProfileSize_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1); + +#ifdef __nvoc_kernel_mig_manager_h_disabled +static inline NvU32 kmigmgrSmallestComputeProfileSize(OBJGPU *arg0, struct KernelMIGManager *arg1) { + NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); + return 0; +} +#else //__nvoc_kernel_mig_manager_h_disabled +#define kmigmgrSmallestComputeProfileSize(arg0, arg1) kmigmgrSmallestComputeProfileSize_IMPL(arg0, arg1) +#endif //__nvoc_kernel_mig_manager_h_disabled + +void kmigmgrSetCTSIdInUse_IMPL(KERNEL_MIG_GPU_INSTANCE *arg0, NvU32 ctsId, NvU32 grId, NvBool bInUse); + +#define kmigmgrSetCTSIdInUse(arg0, ctsId, grId, bInUse) kmigmgrSetCTSIdInUse_IMPL(arg0, ctsId, grId, bInUse) +NV_STATUS kmigmgrXlateSpanStartToCTSId_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 computeSize, NvU32 spanStart, NvU32 *pCtsId); + +#ifdef __nvoc_kernel_mig_manager_h_disabled +static inline NV_STATUS kmigmgrXlateSpanStartToCTSId(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 computeSize, NvU32 spanStart, NvU32 *pCtsId) { + NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_mig_manager_h_disabled +#define kmigmgrXlateSpanStartToCTSId(arg0, arg1, computeSize, spanStart, pCtsId) kmigmgrXlateSpanStartToCTSId_IMPL(arg0, arg1, computeSize, spanStart, pCtsId) +#endif //__nvoc_kernel_mig_manager_h_disabled + +NV_STATUS kmigmgrGetSlotBasisMask_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU64 *pMask); + +#ifdef __nvoc_kernel_mig_manager_h_disabled +static inline NV_STATUS kmigmgrGetSlotBasisMask(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU64 *pMask) { + NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_mig_manager_h_disabled +#define kmigmgrGetSlotBasisMask(arg0, arg1, pMask) kmigmgrGetSlotBasisMask_IMPL(arg0, arg1, pMask) +#endif //__nvoc_kernel_mig_manager_h_disabled + +NvU32 kmigmgrGetSpanStartFromCTSId_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 ctsId); + +#ifdef __nvoc_kernel_mig_manager_h_disabled +static inline NvU32 kmigmgrGetSpanStartFromCTSId(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 ctsId) { + NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); + return 0; +} +#else //__nvoc_kernel_mig_manager_h_disabled +#define kmigmgrGetSpanStartFromCTSId(arg0, arg1, ctsId) kmigmgrGetSpanStartFromCTSId_IMPL(arg0, arg1, ctsId) +#endif //__nvoc_kernel_mig_manager_h_disabled + +NvBool kmigmgrIsCTSIdAvailable_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU64 ctsIdValidMask, NvU64 ctsIdInUseMask, NvU32 ctsId); + +#ifdef __nvoc_kernel_mig_manager_h_disabled +static inline NvBool kmigmgrIsCTSIdAvailable(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU64 ctsIdValidMask, NvU64 ctsIdInUseMask, NvU32 ctsId) { + NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); + return NV_FALSE; +} +#else //__nvoc_kernel_mig_manager_h_disabled +#define kmigmgrIsCTSIdAvailable(arg0, arg1, ctsIdValidMask, ctsIdInUseMask, ctsId) kmigmgrIsCTSIdAvailable_IMPL(arg0, arg1, ctsIdValidMask, ctsIdInUseMask, ctsId) +#endif //__nvoc_kernel_mig_manager_h_disabled + #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.c b/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.c index f0dcc0553..5eb62487d 100644 --- a/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.c +++ b/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.c @@ -220,6 +220,10 @@ static void __nvoc_thunk_RsResource_nvdecctxPreDestruct(struct NvdecContext *pRe resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvdecContext_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_RsResource_nvdecctxIsDuplicate(struct NvdecContext *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvdecContext_RsResource.offset), hMemory, pDuplicate); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_nvdecctxGetNotificationListPtr(struct NvdecContext *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_NvdecContext_Notifier.offset)); } @@ -335,6 +339,8 @@ static void __nvoc_init_funcTable_NvdecContext_1(NvdecContext *pThis, RmHalspecO pThis->__nvdecctxPreDestruct__ = &__nvoc_thunk_RsResource_nvdecctxPreDestruct; + pThis->__nvdecctxIsDuplicate__ = &__nvoc_thunk_RsResource_nvdecctxIsDuplicate; + pThis->__nvdecctxGetNotificationListPtr__ = &__nvoc_thunk_Notifier_nvdecctxGetNotificationListPtr; pThis->__nvdecctxGetNotificationShare__ = &__nvoc_thunk_Notifier_nvdecctxGetNotificationShare; diff --git a/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.h b/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.h index 3025c7ba4..72867537c 100644 --- a/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.h +++ b/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.h @@ -83,6 +83,7 @@ struct NvdecContext { NV_STATUS (*__nvdecctxUnregisterEvent__)(struct NvdecContext *, NvHandle, NvHandle, NvHandle, NvHandle); NvBool (*__nvdecctxCanCopy__)(struct NvdecContext *); void (*__nvdecctxPreDestruct__)(struct NvdecContext *); + NV_STATUS (*__nvdecctxIsDuplicate__)(struct NvdecContext *, NvHandle, NvBool *); PEVENTNOTIFICATION *(*__nvdecctxGetNotificationListPtr__)(struct NvdecContext *); struct NotifShare *(*__nvdecctxGetNotificationShare__)(struct NvdecContext *); NV_STATUS (*__nvdecctxMap__)(struct NvdecContext *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -142,12 +143,14 @@ NV_STATUS __nvoc_objCreate_NvdecContext(NvdecContext**, Dynamic*, NvU32, struct #define nvdecctxUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) nvdecctxUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define nvdecctxCanCopy(pResource) nvdecctxCanCopy_DISPATCH(pResource) #define nvdecctxPreDestruct(pResource) nvdecctxPreDestruct_DISPATCH(pResource) +#define nvdecctxIsDuplicate(pResource, hMemory, pDuplicate) nvdecctxIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define nvdecctxGetNotificationListPtr(pNotifier) nvdecctxGetNotificationListPtr_DISPATCH(pNotifier) #define nvdecctxGetNotificationShare(pNotifier) nvdecctxGetNotificationShare_DISPATCH(pNotifier) #define nvdecctxMap(pGpuResource, pCallContext, pParams, pCpuMapping) nvdecctxMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define nvdecctxGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) nvdecctxGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) NV_STATUS nvdecctxConstructHal_KERNEL(struct NvdecContext *pNvdecContext, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); + #ifdef __nvoc_kernel_nvdec_ctx_h_disabled static inline NV_STATUS nvdecctxConstructHal(struct NvdecContext *pNvdecContext, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { NV_ASSERT_FAILED_PRECOMP("NvdecContext was disabled!"); @@ -161,6 +164,7 @@ static inline NV_STATUS nvdecctxConstructHal(struct NvdecContext *pNvdecContext, void nvdecctxDestructHal_KERNEL(struct NvdecContext *pNvdecContext); + #ifdef __nvoc_kernel_nvdec_ctx_h_disabled static inline void nvdecctxDestructHal(struct NvdecContext *pNvdecContext) { NV_ASSERT_FAILED_PRECOMP("NvdecContext was disabled!"); @@ -271,6 +275,10 @@ static inline void nvdecctxPreDestruct_DISPATCH(struct NvdecContext *pResource) pResource->__nvdecctxPreDestruct__(pResource); } +static inline NV_STATUS nvdecctxIsDuplicate_DISPATCH(struct NvdecContext *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__nvdecctxIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline PEVENTNOTIFICATION *nvdecctxGetNotificationListPtr_DISPATCH(struct NvdecContext *pNotifier) { return pNotifier->__nvdecctxGetNotificationListPtr__(pNotifier); } diff --git a/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.c b/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.c index 37f36484e..9740f5cc1 100644 --- a/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.c +++ b/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.c @@ -220,6 +220,10 @@ static void __nvoc_thunk_RsResource_msencctxPreDestruct(struct MsencContext *pRe resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MsencContext_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_RsResource_msencctxIsDuplicate(struct MsencContext *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MsencContext_RsResource.offset), hMemory, pDuplicate); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_msencctxGetNotificationListPtr(struct MsencContext *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_MsencContext_Notifier.offset)); } @@ -335,6 +339,8 @@ static void __nvoc_init_funcTable_MsencContext_1(MsencContext *pThis, RmHalspecO pThis->__msencctxPreDestruct__ = &__nvoc_thunk_RsResource_msencctxPreDestruct; + pThis->__msencctxIsDuplicate__ = &__nvoc_thunk_RsResource_msencctxIsDuplicate; + pThis->__msencctxGetNotificationListPtr__ = &__nvoc_thunk_Notifier_msencctxGetNotificationListPtr; pThis->__msencctxGetNotificationShare__ = &__nvoc_thunk_Notifier_msencctxGetNotificationShare; diff --git a/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.h b/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.h index e2e0e70ac..9da17e2bc 100644 --- a/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.h +++ b/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.h @@ -83,6 +83,7 @@ struct MsencContext { NV_STATUS (*__msencctxUnregisterEvent__)(struct MsencContext *, NvHandle, NvHandle, NvHandle, NvHandle); NvBool (*__msencctxCanCopy__)(struct MsencContext *); void (*__msencctxPreDestruct__)(struct MsencContext *); + NV_STATUS (*__msencctxIsDuplicate__)(struct MsencContext *, NvHandle, NvBool *); PEVENTNOTIFICATION *(*__msencctxGetNotificationListPtr__)(struct MsencContext *); struct NotifShare *(*__msencctxGetNotificationShare__)(struct MsencContext *); NV_STATUS (*__msencctxMap__)(struct MsencContext *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -142,12 +143,14 @@ NV_STATUS __nvoc_objCreate_MsencContext(MsencContext**, Dynamic*, NvU32, struct #define msencctxUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) msencctxUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define msencctxCanCopy(pResource) msencctxCanCopy_DISPATCH(pResource) #define msencctxPreDestruct(pResource) msencctxPreDestruct_DISPATCH(pResource) +#define msencctxIsDuplicate(pResource, hMemory, pDuplicate) msencctxIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define msencctxGetNotificationListPtr(pNotifier) msencctxGetNotificationListPtr_DISPATCH(pNotifier) #define msencctxGetNotificationShare(pNotifier) msencctxGetNotificationShare_DISPATCH(pNotifier) #define msencctxMap(pGpuResource, pCallContext, pParams, pCpuMapping) msencctxMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define msencctxGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) msencctxGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) NV_STATUS msencctxConstructHal_KERNEL(struct MsencContext *pMsencContext, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); + #ifdef __nvoc_kernel_nvenc_ctx_h_disabled static inline NV_STATUS msencctxConstructHal(struct MsencContext *pMsencContext, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { NV_ASSERT_FAILED_PRECOMP("MsencContext was disabled!"); @@ -161,6 +164,7 @@ static inline NV_STATUS msencctxConstructHal(struct MsencContext *pMsencContext, void msencctxDestructHal_KERNEL(struct MsencContext *pMsencContext); + #ifdef __nvoc_kernel_nvenc_ctx_h_disabled static inline void msencctxDestructHal(struct MsencContext *pMsencContext) { NV_ASSERT_FAILED_PRECOMP("MsencContext was disabled!"); @@ -271,6 +275,10 @@ static inline void msencctxPreDestruct_DISPATCH(struct MsencContext *pResource) pResource->__msencctxPreDestruct__(pResource); } +static inline NV_STATUS msencctxIsDuplicate_DISPATCH(struct MsencContext *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__msencctxIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline PEVENTNOTIFICATION *msencctxGetNotificationListPtr_DISPATCH(struct MsencContext *pNotifier) { return pNotifier->__msencctxGetNotificationListPtr__(pNotifier); } diff --git a/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.c b/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.c index b1a2e1607..5b011761e 100644 --- a/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.c +++ b/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.c @@ -220,6 +220,10 @@ static void __nvoc_thunk_RsResource_nvjpgctxPreDestruct(struct NvjpgContext *pRe resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvjpgContext_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_RsResource_nvjpgctxIsDuplicate(struct NvjpgContext *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvjpgContext_RsResource.offset), hMemory, pDuplicate); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_nvjpgctxGetNotificationListPtr(struct NvjpgContext *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_NvjpgContext_Notifier.offset)); } @@ -335,6 +339,8 @@ static void __nvoc_init_funcTable_NvjpgContext_1(NvjpgContext *pThis, RmHalspecO pThis->__nvjpgctxPreDestruct__ = &__nvoc_thunk_RsResource_nvjpgctxPreDestruct; + pThis->__nvjpgctxIsDuplicate__ = &__nvoc_thunk_RsResource_nvjpgctxIsDuplicate; + pThis->__nvjpgctxGetNotificationListPtr__ = &__nvoc_thunk_Notifier_nvjpgctxGetNotificationListPtr; pThis->__nvjpgctxGetNotificationShare__ = &__nvoc_thunk_Notifier_nvjpgctxGetNotificationShare; diff --git a/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.h b/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.h index 4560a4cbb..64a4e24ec 100644 --- a/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.h +++ b/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.h @@ -83,6 +83,7 @@ struct NvjpgContext { NV_STATUS (*__nvjpgctxUnregisterEvent__)(struct NvjpgContext *, NvHandle, NvHandle, NvHandle, NvHandle); NvBool (*__nvjpgctxCanCopy__)(struct NvjpgContext *); void (*__nvjpgctxPreDestruct__)(struct NvjpgContext *); + NV_STATUS (*__nvjpgctxIsDuplicate__)(struct NvjpgContext *, NvHandle, NvBool *); PEVENTNOTIFICATION *(*__nvjpgctxGetNotificationListPtr__)(struct NvjpgContext *); struct NotifShare *(*__nvjpgctxGetNotificationShare__)(struct NvjpgContext *); NV_STATUS (*__nvjpgctxMap__)(struct NvjpgContext *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -142,12 +143,14 @@ NV_STATUS __nvoc_objCreate_NvjpgContext(NvjpgContext**, Dynamic*, NvU32, struct #define nvjpgctxUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) nvjpgctxUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define nvjpgctxCanCopy(pResource) nvjpgctxCanCopy_DISPATCH(pResource) #define nvjpgctxPreDestruct(pResource) nvjpgctxPreDestruct_DISPATCH(pResource) +#define nvjpgctxIsDuplicate(pResource, hMemory, pDuplicate) nvjpgctxIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define nvjpgctxGetNotificationListPtr(pNotifier) nvjpgctxGetNotificationListPtr_DISPATCH(pNotifier) #define nvjpgctxGetNotificationShare(pNotifier) nvjpgctxGetNotificationShare_DISPATCH(pNotifier) #define nvjpgctxMap(pGpuResource, pCallContext, pParams, pCpuMapping) nvjpgctxMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define nvjpgctxGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) nvjpgctxGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) NV_STATUS nvjpgctxConstructHal_KERNEL(struct NvjpgContext *pNvjpgContext, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); + #ifdef __nvoc_kernel_nvjpg_ctx_h_disabled static inline NV_STATUS nvjpgctxConstructHal(struct NvjpgContext *pNvjpgContext, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { NV_ASSERT_FAILED_PRECOMP("NvjpgContext was disabled!"); @@ -161,6 +164,7 @@ static inline NV_STATUS nvjpgctxConstructHal(struct NvjpgContext *pNvjpgContext, void nvjpgctxDestructHal_KERNEL(struct NvjpgContext *pNvjpgContext); + #ifdef __nvoc_kernel_nvjpg_ctx_h_disabled static inline void nvjpgctxDestructHal(struct NvjpgContext *pNvjpgContext) { NV_ASSERT_FAILED_PRECOMP("NvjpgContext was disabled!"); @@ -271,6 +275,10 @@ static inline void nvjpgctxPreDestruct_DISPATCH(struct NvjpgContext *pResource) pResource->__nvjpgctxPreDestruct__(pResource); } +static inline NV_STATUS nvjpgctxIsDuplicate_DISPATCH(struct NvjpgContext *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__nvjpgctxIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline PEVENTNOTIFICATION *nvjpgctxGetNotificationListPtr_DISPATCH(struct NvjpgContext *pNotifier) { return pNotifier->__nvjpgctxGetNotificationListPtr__(pNotifier); } diff --git a/src/nvidia/generated/g_kernel_nvlink_nvoc.c b/src/nvidia/generated/g_kernel_nvlink_nvoc.c index e4eddf20c..0a20a62ed 100644 --- a/src/nvidia/generated/g_kernel_nvlink_nvoc.c +++ b/src/nvidia/generated/g_kernel_nvlink_nvoc.c @@ -172,17 +172,13 @@ void __nvoc_init_dataField_KernelNvlink(KernelNvlink *pThis, RmHalspecOwner *pRm PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); // NVOC Property Hal field -- PDB_PROP_KNVLINK_IS_MISSING - if (0) - { - } // default - else { pThis->setProperty(pThis, PDB_PROP_KNVLINK_IS_MISSING, ((NvBool)(0 != 0))); } // NVOC Property Hal field -- PDB_PROP_KNVLINK_ENABLED - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_KNVLINK_ENABLED, ((NvBool)(0 == 0))); } @@ -193,7 +189,7 @@ void __nvoc_init_dataField_KernelNvlink(KernelNvlink *pThis, RmHalspecOwner *pRm } // NVOC Property Hal field -- PDB_PROP_KNVLINK_UNSET_NVLINK_PEER_SUPPORTED - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_KNVLINK_UNSET_NVLINK_PEER_SUPPORTED, ((NvBool)(0 == 0))); } @@ -203,41 +199,25 @@ void __nvoc_init_dataField_KernelNvlink(KernelNvlink *pThis, RmHalspecOwner *pRm pThis->setProperty(pThis, PDB_PROP_KNVLINK_UNSET_NVLINK_PEER_SUPPORTED, ((NvBool)(0 != 0))); } - // NVOC Property Hal field -- PDB_PROP_KNVLINK_UNSET_NVLINK_PEER_REFCNT - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + // NVOC Property Hal field -- PDB_PROP_KNVLINK_CONFIG_REQUIRE_INITIALIZED_LINKS_CHECK + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->setProperty(pThis, PDB_PROP_KNVLINK_UNSET_NVLINK_PEER_REFCNT, ((NvBool)(0 != 0))); + pThis->setProperty(pThis, PDB_PROP_KNVLINK_CONFIG_REQUIRE_INITIALIZED_LINKS_CHECK, ((NvBool)(0 == 0))); } // default else { - pThis->setProperty(pThis, PDB_PROP_KNVLINK_UNSET_NVLINK_PEER_REFCNT, ((NvBool)(0 == 0))); - } - - // NVOC Property Hal field -- PDB_PROP_KNVLINK_DECONFIG_HSHUB_ON_NO_MAPPING - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ - { - pThis->setProperty(pThis, PDB_PROP_KNVLINK_DECONFIG_HSHUB_ON_NO_MAPPING, ((NvBool)(0 == 0))); - } - // default - else - { - pThis->setProperty(pThis, PDB_PROP_KNVLINK_DECONFIG_HSHUB_ON_NO_MAPPING, ((NvBool)(0 != 0))); + pThis->setProperty(pThis, PDB_PROP_KNVLINK_CONFIG_REQUIRE_INITIALIZED_LINKS_CHECK, ((NvBool)(0 != 0))); } // NVOC Property Hal field -- PDB_PROP_KNVLINK_LANE_SHUTDOWN_ENABLED - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_KNVLINK_LANE_SHUTDOWN_ENABLED, ((NvBool)(0 == 0))); } - // default - else - { - pThis->setProperty(pThis, PDB_PROP_KNVLINK_LANE_SHUTDOWN_ENABLED, ((NvBool)(0 != 0))); - } // NVOC Property Hal field -- PDB_PROP_KNVLINK_LANE_SHUTDOWN_ON_UNLOAD - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_KNVLINK_LANE_SHUTDOWN_ON_UNLOAD, ((NvBool)(0 == 0))); } @@ -248,15 +228,10 @@ void __nvoc_init_dataField_KernelNvlink(KernelNvlink *pThis, RmHalspecOwner *pRm } // NVOC Property Hal field -- PDB_PROP_KNVLINK_LINKRESET_AFTER_SHUTDOWN - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_KNVLINK_LINKRESET_AFTER_SHUTDOWN, ((NvBool)(0 == 0))); } - // default - else - { - pThis->setProperty(pThis, PDB_PROP_KNVLINK_LINKRESET_AFTER_SHUTDOWN, ((NvBool)(0 != 0))); - } // NVOC Property Hal field -- PDB_PROP_KNVLINK_BUG2274645_RESET_FOR_RTD3_FGC6 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ @@ -284,7 +259,7 @@ void __nvoc_init_dataField_KernelNvlink(KernelNvlink *pThis, RmHalspecOwner *pRm pThis->setProperty(pThis, PDB_PROP_KNVLINK_WAR_BUG_3471679_PEERID_FILTERING, ((NvBool)(0 != 0))); // NVOC Property Hal field -- PDB_PROP_KNVLINK_MINION_GFW_BOOT - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->setProperty(pThis, PDB_PROP_KNVLINK_MINION_GFW_BOOT, ((NvBool)(0 == 0))); } @@ -295,7 +270,7 @@ void __nvoc_init_dataField_KernelNvlink(KernelNvlink *pThis, RmHalspecOwner *pRm } // NVOC Property Hal field -- PDB_PROP_KNVLINK_SYSMEM_SUPPORT_ENABLED - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_KNVLINK_SYSMEM_SUPPORT_ENABLED, ((NvBool)(0 != 0))); } @@ -348,20 +323,32 @@ static void __nvoc_init_funcTable_KernelNvlink_1(KernelNvlink *pThis, RmHalspecO pThis->__knvlinkIsPresent__ = &knvlinkIsPresent_IMPL; - // Hal function -- knvlinkValidateFabricBaseAddress - if (0) + // Hal function -- knvlinkSetUniqueFabricBaseAddress + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (0) + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { + pThis->__knvlinkSetUniqueFabricBaseAddress__ = &knvlinkSetUniqueFabricBaseAddress_GV100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__knvlinkSetUniqueFabricBaseAddress__ = &knvlinkSetUniqueFabricBaseAddress_GH100; + } + // default + else + { + pThis->__knvlinkSetUniqueFabricBaseAddress__ = &knvlinkSetUniqueFabricBaseAddress_46f6a7; + } + } + + // Hal function -- knvlinkValidateFabricBaseAddress + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__knvlinkValidateFabricBaseAddress__ = &knvlinkValidateFabricBaseAddress_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__knvlinkValidateFabricBaseAddress__ = &knvlinkValidateFabricBaseAddress_GH100; } @@ -373,54 +360,39 @@ static void __nvoc_init_funcTable_KernelNvlink_1(KernelNvlink *pThis, RmHalspecO } // Hal function -- knvlinkGetConnectedLinksMask - if (0) + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__knvlinkGetConnectedLinksMask__ = &knvlinkGetConnectedLinksMask_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000380UL) )) /* ChipHal: TU106 | TU116 | TU117 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000380UL) )) /* ChipHal: TU106 | TU116 | TU117 | GH100 */ { pThis->__knvlinkGetConnectedLinksMask__ = &knvlinkGetConnectedLinksMask_15a734; } } // Hal function -- knvlinkEnableLinksPostTopology - if (0) - { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ { pThis->__knvlinkEnableLinksPostTopology__ = &knvlinkEnableLinksPostTopology_GV100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ff80UL) )) /* ChipHal: TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ff80UL) )) /* ChipHal: TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__knvlinkEnableLinksPostTopology__ = &knvlinkEnableLinksPostTopology_56cd7a; } } // Hal function -- knvlinkOverrideConfig - if (0) + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ { pThis->__knvlinkOverrideConfig__ = &knvlinkOverrideConfig_GV100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__knvlinkOverrideConfig__ = &knvlinkOverrideConfig_GA100; } @@ -431,18 +403,9 @@ static void __nvoc_init_funcTable_KernelNvlink_1(KernelNvlink *pThis, RmHalspecO } // Hal function -- knvlinkFilterBridgeLinks - if (0) + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (0) - { - } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__knvlinkFilterBridgeLinks__ = &knvlinkFilterBridgeLinks_TU102; } @@ -453,48 +416,39 @@ static void __nvoc_init_funcTable_KernelNvlink_1(KernelNvlink *pThis, RmHalspecO } // Hal function -- knvlinkGetUniquePeerIdMask - if (0) - { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ { pThis->__knvlinkGetUniquePeerIdMask__ = &knvlinkGetUniquePeerIdMask_GP100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ff80UL) )) /* ChipHal: TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ff80UL) )) /* ChipHal: TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__knvlinkGetUniquePeerIdMask__ = &knvlinkGetUniquePeerIdMask_15a734; } } // Hal function -- knvlinkGetUniquePeerId - if (0) - { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ { pThis->__knvlinkGetUniquePeerId__ = &knvlinkGetUniquePeerId_GP100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ff80UL) )) /* ChipHal: TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ff80UL) )) /* ChipHal: TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__knvlinkGetUniquePeerId__ = &knvlinkGetUniquePeerId_c732fb; } } // Hal function -- knvlinkRemoveMapping - if (0) - { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ { pThis->__knvlinkRemoveMapping__ = &knvlinkRemoveMapping_GP100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__knvlinkRemoveMapping__ = &knvlinkRemoveMapping_GA100; } @@ -505,12 +459,9 @@ static void __nvoc_init_funcTable_KernelNvlink_1(KernelNvlink *pThis, RmHalspecO } // Hal function -- knvlinkGetP2POptimalCEs - if (0) + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__knvlinkGetP2POptimalCEs__ = &knvlinkGetP2POptimalCEs_GP100; } @@ -521,12 +472,9 @@ static void __nvoc_init_funcTable_KernelNvlink_1(KernelNvlink *pThis, RmHalspecO } // Hal function -- knvlinkConstructHal - if (0) + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__knvlinkConstructHal__ = &knvlinkConstructHal_GV100; } @@ -537,12 +485,9 @@ static void __nvoc_init_funcTable_KernelNvlink_1(KernelNvlink *pThis, RmHalspecO } // Hal function -- knvlinkSetupPeerMapping - if (0) + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__knvlinkSetupPeerMapping__ = &knvlinkSetupPeerMapping_GP100; } @@ -553,15 +498,9 @@ static void __nvoc_init_funcTable_KernelNvlink_1(KernelNvlink *pThis, RmHalspecO } // Hal function -- knvlinkProgramLinkSpeed - if (0) + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc60UL) )) /* ChipHal: TU102 | TU104 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__knvlinkProgramLinkSpeed__ = &knvlinkProgramLinkSpeed_GV100; } @@ -572,69 +511,83 @@ static void __nvoc_init_funcTable_KernelNvlink_1(KernelNvlink *pThis, RmHalspecO } // Hal function -- knvlinkPoweredUpForD3 - if (0) - { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ { pThis->__knvlinkPoweredUpForD3__ = &knvlinkPoweredUpForD3_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ff80UL) )) /* ChipHal: TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ff80UL) )) /* ChipHal: TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__knvlinkPoweredUpForD3__ = &knvlinkPoweredUpForD3_491d52; } } // Hal function -- knvlinkIsAliSupported - if (0) + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__knvlinkIsAliSupported__ = &knvlinkIsAliSupported_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__knvlinkIsAliSupported__ = &knvlinkIsAliSupported_56cd7a; } } // Hal function -- knvlinkPostSetupNvlinkPeer - if (0) + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__knvlinkPostSetupNvlinkPeer__ = &knvlinkPostSetupNvlinkPeer_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__knvlinkPostSetupNvlinkPeer__ = &knvlinkPostSetupNvlinkPeer_56cd7a; } } // Hal function -- knvlinkDiscoverPostRxDetLinks - if (0) + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__knvlinkDiscoverPostRxDetLinks__ = &knvlinkDiscoverPostRxDetLinks_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__knvlinkDiscoverPostRxDetLinks__ = &knvlinkDiscoverPostRxDetLinks_46f6a7; } } + // Hal function -- knvlinkLogAliDebugMessages + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__knvlinkLogAliDebugMessages__ = &knvlinkLogAliDebugMessages_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__knvlinkLogAliDebugMessages__ = &knvlinkLogAliDebugMessages_46f6a7; + } + } + + // Hal function -- knvlinkIsFloorSweepingNeeded + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__knvlinkIsFloorSweepingNeeded__ = &knvlinkIsFloorSweepingNeeded_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__knvlinkIsFloorSweepingNeeded__ = &knvlinkIsFloorSweepingNeeded_491d52; + } + } + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelNvlink_engstateConstructEngine; pThis->__nvoc_base_OBJENGSTATE.__engstateStatePreInitLocked__ = &__nvoc_thunk_KernelNvlink_engstateStatePreInitLocked; diff --git a/src/nvidia/generated/g_kernel_nvlink_nvoc.h b/src/nvidia/generated/g_kernel_nvlink_nvoc.h index 9ae207e45..97f045ce0 100644 --- a/src/nvidia/generated/g_kernel_nvlink_nvoc.h +++ b/src/nvidia/generated/g_kernel_nvlink_nvoc.h @@ -49,6 +49,10 @@ extern "C" { #include "kernel/gpu/nvlink/kernel_ioctrl.h" #include "ctrl/ctrl2080/ctrl2080nvlink.h" // rmcontrol params +#include "ctrl/ctrl2080/ctrl2080pmgr.h" + +#include "nvlink_inband_drv_header.h" +#include "nvlink_inband_msg.h" #if defined(INCLUDE_NVLINK_LIB) @@ -177,6 +181,14 @@ typedef struct _def_knvlink_link } KNVLINK_RM_LINK, *PKNVLINK_RM_LINK; +typedef struct NVLINK_INBAND_CALLBACK +{ + NvU32 messageType; + void (*pCallback)(OBJGPU *pGpu, + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pMessage); + NvU32 wqItemFlags; +} NVLINK_INBAND_MSG_CALLBACK; + /*! * KernelNvlink is a logical abstraction of the GPU Nvlink Engine. The @@ -202,6 +214,7 @@ struct KernelNvlink { NV_STATUS (*__knvlinkStateUnload__)(OBJGPU *, struct KernelNvlink *, NvU32); NV_STATUS (*__knvlinkStatePostUnload__)(OBJGPU *, struct KernelNvlink *, NvU32); NvBool (*__knvlinkIsPresent__)(OBJGPU *, struct KernelNvlink *); + NV_STATUS (*__knvlinkSetUniqueFabricBaseAddress__)(OBJGPU *, struct KernelNvlink *, NvU64); NV_STATUS (*__knvlinkValidateFabricBaseAddress__)(OBJGPU *, struct KernelNvlink *, NvU64); NvU32 (*__knvlinkGetConnectedLinksMask__)(OBJGPU *, struct KernelNvlink *); NV_STATUS (*__knvlinkEnableLinksPostTopology__)(OBJGPU *, struct KernelNvlink *, NvU32); @@ -218,6 +231,8 @@ struct KernelNvlink { NV_STATUS (*__knvlinkIsAliSupported__)(OBJGPU *, struct KernelNvlink *); NV_STATUS (*__knvlinkPostSetupNvlinkPeer__)(OBJGPU *, struct KernelNvlink *); NV_STATUS (*__knvlinkDiscoverPostRxDetLinks__)(OBJGPU *, struct KernelNvlink *, OBJGPU *); + NV_STATUS (*__knvlinkLogAliDebugMessages__)(OBJGPU *, struct KernelNvlink *); + NvBool (*__knvlinkIsFloorSweepingNeeded__)(OBJGPU *, struct KernelNvlink *, NvU32, NvU32); NV_STATUS (*__knvlinkReconcileTunableState__)(POBJGPU, struct KernelNvlink *, void *); NV_STATUS (*__knvlinkStateInitLocked__)(POBJGPU, struct KernelNvlink *); NV_STATUS (*__knvlinkStatePreLoad__)(POBJGPU, struct KernelNvlink *, NvU32); @@ -235,8 +250,7 @@ struct KernelNvlink { NvBool PDB_PROP_KNVLINK_SINGLE_LANE_POWER_STATE_ENABLED; NvBool PDB_PROP_KNVLINK_L2_POWER_STATE_ENABLED; NvBool PDB_PROP_KNVLINK_UNSET_NVLINK_PEER_SUPPORTED; - NvBool PDB_PROP_KNVLINK_UNSET_NVLINK_PEER_REFCNT; - NvBool PDB_PROP_KNVLINK_DECONFIG_HSHUB_ON_NO_MAPPING; + NvBool PDB_PROP_KNVLINK_CONFIG_REQUIRE_INITIALIZED_LINKS_CHECK; NvBool PDB_PROP_KNVLINK_LANE_SHUTDOWN_ENABLED; NvBool PDB_PROP_KNVLINK_LANE_SHUTDOWN_ON_UNLOAD; NvBool PDB_PROP_KNVLINK_LINKRESET_AFTER_SHUTDOWN; @@ -270,11 +284,13 @@ struct KernelNvlink { NvU32 enabledLinks; NvU32 initializedLinks; KNVLINK_RM_LINK nvlinkLinks[18]; + NvBool bIsGpuDegraded; NvU32 postRxDetLinkMask; NvU32 disconnectedLinkMask; NvU32 sysmemLinkMask; NvU32 peerLinkMasks[32]; NvU32 forcedSysmemDeviceType; + NVLINK_INBAND_MSG_CALLBACK inbandCallback[5]; nvlink_device *pNvlinkDev; NvU32 deviceLockRefcount; NvBool bVerifTrainingEnable; @@ -318,16 +334,16 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelNvlink; #define PDB_PROP_KNVLINK_MINION_GFW_BOOT_BASE_CAST #define PDB_PROP_KNVLINK_MINION_GFW_BOOT_BASE_NAME PDB_PROP_KNVLINK_MINION_GFW_BOOT -#define PDB_PROP_KNVLINK_SYSMEM_SUPPORT_ENABLED_BASE_CAST -#define PDB_PROP_KNVLINK_SYSMEM_SUPPORT_ENABLED_BASE_NAME PDB_PROP_KNVLINK_SYSMEM_SUPPORT_ENABLED +#define PDB_PROP_KNVLINK_CONFIG_REQUIRE_INITIALIZED_LINKS_CHECK_BASE_CAST +#define PDB_PROP_KNVLINK_CONFIG_REQUIRE_INITIALIZED_LINKS_CHECK_BASE_NAME PDB_PROP_KNVLINK_CONFIG_REQUIRE_INITIALIZED_LINKS_CHECK #define PDB_PROP_KNVLINK_LANE_SHUTDOWN_ENABLED_BASE_CAST #define PDB_PROP_KNVLINK_LANE_SHUTDOWN_ENABLED_BASE_NAME PDB_PROP_KNVLINK_LANE_SHUTDOWN_ENABLED +#define PDB_PROP_KNVLINK_SYSMEM_SUPPORT_ENABLED_BASE_CAST +#define PDB_PROP_KNVLINK_SYSMEM_SUPPORT_ENABLED_BASE_NAME PDB_PROP_KNVLINK_SYSMEM_SUPPORT_ENABLED #define PDB_PROP_KNVLINK_MINION_FORCE_ALI_TRAINING_BASE_CAST #define PDB_PROP_KNVLINK_MINION_FORCE_ALI_TRAINING_BASE_NAME PDB_PROP_KNVLINK_MINION_FORCE_ALI_TRAINING #define PDB_PROP_KNVLINK_ENABLED_BASE_CAST #define PDB_PROP_KNVLINK_ENABLED_BASE_NAME PDB_PROP_KNVLINK_ENABLED -#define PDB_PROP_KNVLINK_UNSET_NVLINK_PEER_REFCNT_BASE_CAST -#define PDB_PROP_KNVLINK_UNSET_NVLINK_PEER_REFCNT_BASE_NAME PDB_PROP_KNVLINK_UNSET_NVLINK_PEER_REFCNT #define PDB_PROP_KNVLINK_UNSET_NVLINK_PEER_SUPPORTED_BASE_CAST #define PDB_PROP_KNVLINK_UNSET_NVLINK_PEER_SUPPORTED_BASE_NAME PDB_PROP_KNVLINK_UNSET_NVLINK_PEER_SUPPORTED #define PDB_PROP_KNVLINK_MINION_FORCE_NON_ALI_TRAINING_BASE_CAST @@ -344,8 +360,6 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelNvlink; #define PDB_PROP_KNVLINK_BUG2274645_RESET_FOR_RTD3_FGC6_BASE_NAME PDB_PROP_KNVLINK_BUG2274645_RESET_FOR_RTD3_FGC6 #define PDB_PROP_KNVLINK_LANE_SHUTDOWN_ON_UNLOAD_BASE_CAST #define PDB_PROP_KNVLINK_LANE_SHUTDOWN_ON_UNLOAD_BASE_NAME PDB_PROP_KNVLINK_LANE_SHUTDOWN_ON_UNLOAD -#define PDB_PROP_KNVLINK_DECONFIG_HSHUB_ON_NO_MAPPING_BASE_CAST -#define PDB_PROP_KNVLINK_DECONFIG_HSHUB_ON_NO_MAPPING_BASE_NAME PDB_PROP_KNVLINK_DECONFIG_HSHUB_ON_NO_MAPPING #define PDB_PROP_KNVLINK_L2_POWER_STATE_FOR_LONG_IDLE_BASE_CAST #define PDB_PROP_KNVLINK_L2_POWER_STATE_FOR_LONG_IDLE_BASE_NAME PDB_PROP_KNVLINK_L2_POWER_STATE_FOR_LONG_IDLE #define PDB_PROP_KNVLINK_LINKRESET_AFTER_SHUTDOWN_BASE_CAST @@ -364,6 +378,8 @@ NV_STATUS __nvoc_objCreate_KernelNvlink(KernelNvlink**, Dynamic*, NvU32); #define knvlinkStateUnload(arg0, arg1, arg2) knvlinkStateUnload_DISPATCH(arg0, arg1, arg2) #define knvlinkStatePostUnload(arg0, arg1, arg2) knvlinkStatePostUnload_DISPATCH(arg0, arg1, arg2) #define knvlinkIsPresent(arg0, arg1) knvlinkIsPresent_DISPATCH(arg0, arg1) +#define knvlinkSetUniqueFabricBaseAddress(pGpu, pKernelNvlink, arg0) knvlinkSetUniqueFabricBaseAddress_DISPATCH(pGpu, pKernelNvlink, arg0) +#define knvlinkSetUniqueFabricBaseAddress_HAL(pGpu, pKernelNvlink, arg0) knvlinkSetUniqueFabricBaseAddress_DISPATCH(pGpu, pKernelNvlink, arg0) #define knvlinkValidateFabricBaseAddress(pGpu, pKernelNvlink, arg0) knvlinkValidateFabricBaseAddress_DISPATCH(pGpu, pKernelNvlink, arg0) #define knvlinkValidateFabricBaseAddress_HAL(pGpu, pKernelNvlink, arg0) knvlinkValidateFabricBaseAddress_DISPATCH(pGpu, pKernelNvlink, arg0) #define knvlinkGetConnectedLinksMask(pGpu, pKernelNvlink) knvlinkGetConnectedLinksMask_DISPATCH(pGpu, pKernelNvlink) @@ -396,6 +412,10 @@ NV_STATUS __nvoc_objCreate_KernelNvlink(KernelNvlink**, Dynamic*, NvU32); #define knvlinkPostSetupNvlinkPeer_HAL(pGpu, pKernelNvlink) knvlinkPostSetupNvlinkPeer_DISPATCH(pGpu, pKernelNvlink) #define knvlinkDiscoverPostRxDetLinks(pGpu, pKernelNvlink, pPeerGpu) knvlinkDiscoverPostRxDetLinks_DISPATCH(pGpu, pKernelNvlink, pPeerGpu) #define knvlinkDiscoverPostRxDetLinks_HAL(pGpu, pKernelNvlink, pPeerGpu) knvlinkDiscoverPostRxDetLinks_DISPATCH(pGpu, pKernelNvlink, pPeerGpu) +#define knvlinkLogAliDebugMessages(pGpu, pKernelNvlink) knvlinkLogAliDebugMessages_DISPATCH(pGpu, pKernelNvlink) +#define knvlinkLogAliDebugMessages_HAL(pGpu, pKernelNvlink) knvlinkLogAliDebugMessages_DISPATCH(pGpu, pKernelNvlink) +#define knvlinkIsFloorSweepingNeeded(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl) knvlinkIsFloorSweepingNeeded_DISPATCH(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl) +#define knvlinkIsFloorSweepingNeeded_HAL(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl) knvlinkIsFloorSweepingNeeded_DISPATCH(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl) #define knvlinkReconcileTunableState(pGpu, pEngstate, pTunableState) knvlinkReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define knvlinkStateInitLocked(pGpu, pEngstate) knvlinkStateInitLocked_DISPATCH(pGpu, pEngstate) #define knvlinkStatePreLoad(pGpu, pEngstate, arg0) knvlinkStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) @@ -411,6 +431,7 @@ NV_STATUS __nvoc_objCreate_KernelNvlink(KernelNvlink**, Dynamic*, NvU32); #define knvlinkSetTunableState(pGpu, pEngstate, pTunableState) knvlinkSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) NvBool knvlinkIsForcedConfig_IMPL(OBJGPU *arg0, struct KernelNvlink *arg1); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NvBool knvlinkIsForcedConfig(OBJGPU *arg0, struct KernelNvlink *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -424,6 +445,7 @@ static inline NvBool knvlinkIsForcedConfig(OBJGPU *arg0, struct KernelNvlink *ar NV_STATUS knvlinkApplyRegkeyOverrides_IMPL(OBJGPU *pGpu, struct KernelNvlink *arg0); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkApplyRegkeyOverrides(OBJGPU *pGpu, struct KernelNvlink *arg0) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -437,6 +459,7 @@ static inline NV_STATUS knvlinkApplyRegkeyOverrides(OBJGPU *pGpu, struct KernelN NvBool knvlinkIsNvlinkDefaultEnabled_IMPL(OBJGPU *pGpu, struct KernelNvlink *arg0); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NvBool knvlinkIsNvlinkDefaultEnabled(OBJGPU *pGpu, struct KernelNvlink *arg0) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -450,6 +473,7 @@ static inline NvBool knvlinkIsNvlinkDefaultEnabled(OBJGPU *pGpu, struct KernelNv NvBool knvlinkIsP2pLoopbackSupported_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NvBool knvlinkIsP2pLoopbackSupported(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -463,6 +487,7 @@ static inline NvBool knvlinkIsP2pLoopbackSupported(OBJGPU *pGpu, struct KernelNv NvBool knvlinkIsP2pLoopbackSupportedPerLink_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NvBool knvlinkIsP2pLoopbackSupportedPerLink(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -476,6 +501,7 @@ static inline NvBool knvlinkIsP2pLoopbackSupportedPerLink(OBJGPU *pGpu, struct K NvBool knvlinkIsNvlinkP2pSupported_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pPeerGpu); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NvBool knvlinkIsNvlinkP2pSupported(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pPeerGpu) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -489,6 +515,7 @@ static inline NvBool knvlinkIsNvlinkP2pSupported(OBJGPU *pGpu, struct KernelNvli NvBool knvlinkCheckNvswitchP2pConfig_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pPeerGpu); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NvBool knvlinkCheckNvswitchP2pConfig(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pPeerGpu) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -502,6 +529,7 @@ static inline NvBool knvlinkCheckNvswitchP2pConfig(OBJGPU *pGpu, struct KernelNv NV_STATUS knvlinkGetP2pConnectionStatus_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pPeerGpu); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkGetP2pConnectionStatus(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pPeerGpu) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -515,6 +543,7 @@ static inline NV_STATUS knvlinkGetP2pConnectionStatus(OBJGPU *pGpu, struct Kerne NV_STATUS knvlinkUpdateCurrentConfig_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkUpdateCurrentConfig(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -528,6 +557,7 @@ static inline NV_STATUS knvlinkUpdateCurrentConfig(OBJGPU *pGpu, struct KernelNv void knvlinkCoreDriverLoadWar_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline void knvlinkCoreDriverLoadWar(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -540,6 +570,7 @@ static inline void knvlinkCoreDriverLoadWar(OBJGPU *pGpu, struct KernelNvlink *p void knvlinkCoreDriverUnloadWar_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline void knvlinkCoreDriverUnloadWar(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -552,6 +583,7 @@ static inline void knvlinkCoreDriverUnloadWar(OBJGPU *pGpu, struct KernelNvlink NV_STATUS knvlinkCoreIsDriverSupported_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkCoreIsDriverSupported(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -565,6 +597,7 @@ static inline NV_STATUS knvlinkCoreIsDriverSupported(OBJGPU *pGpu, struct Kernel NV_STATUS knvlinkCoreAddDevice_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkCoreAddDevice(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -578,6 +611,7 @@ static inline NV_STATUS knvlinkCoreAddDevice(OBJGPU *pGpu, struct KernelNvlink * NV_STATUS knvlinkCoreAddLink_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkCoreAddLink(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -591,6 +625,7 @@ static inline NV_STATUS knvlinkCoreAddLink(OBJGPU *pGpu, struct KernelNvlink *pK NV_STATUS knvlinkCoreRemoveDevice_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkCoreRemoveDevice(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -602,8 +637,22 @@ static inline NV_STATUS knvlinkCoreRemoveDevice(OBJGPU *pGpu, struct KernelNvlin #define knvlinkCoreRemoveDevice_HAL(pGpu, pKernelNvlink) knvlinkCoreRemoveDevice(pGpu, pKernelNvlink) +void knvlinkSetDegradedMode_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0); + + +#ifdef __nvoc_kernel_nvlink_h_disabled +static inline void knvlinkSetDegradedMode(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { + NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); +} +#else //__nvoc_kernel_nvlink_h_disabled +#define knvlinkSetDegradedMode(pGpu, pKernelNvlink, arg0) knvlinkSetDegradedMode_IMPL(pGpu, pKernelNvlink, arg0) +#endif //__nvoc_kernel_nvlink_h_disabled + +#define knvlinkSetDegradedMode_HAL(pGpu, pKernelNvlink, arg0) knvlinkSetDegradedMode(pGpu, pKernelNvlink, arg0) + NV_STATUS knvlinkCoreRemoveLink_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkCoreRemoveLink(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -617,6 +666,7 @@ static inline NV_STATUS knvlinkCoreRemoveLink(OBJGPU *pGpu, struct KernelNvlink NV_STATUS knvlinkCoreShutdownDeviceLinks_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvBool bForcePowerDown); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkCoreShutdownDeviceLinks(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvBool bForcePowerDown) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -630,6 +680,7 @@ static inline NV_STATUS knvlinkCoreShutdownDeviceLinks(OBJGPU *pGpu, struct Kern NV_STATUS knvlinkCoreResetDeviceLinks_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkCoreResetDeviceLinks(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -643,6 +694,7 @@ static inline NV_STATUS knvlinkCoreResetDeviceLinks(OBJGPU *pGpu, struct KernelN NV_STATUS knvlinkCoreUpdateDeviceUUID_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkCoreUpdateDeviceUUID(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -654,8 +706,37 @@ static inline NV_STATUS knvlinkCoreUpdateDeviceUUID(OBJGPU *pGpu, struct KernelN #define knvlinkCoreUpdateDeviceUUID_HAL(pGpu, pKernelNvlink) knvlinkCoreUpdateDeviceUUID(pGpu, pKernelNvlink) +NV_STATUS knvlinkRegisterInbandCallback_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NVLINK_INBAND_MSG_CALLBACK *params); + + +#ifdef __nvoc_kernel_nvlink_h_disabled +static inline NV_STATUS knvlinkRegisterInbandCallback(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NVLINK_INBAND_MSG_CALLBACK *params) { + NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_nvlink_h_disabled +#define knvlinkRegisterInbandCallback(pGpu, pKernelNvlink, params) knvlinkRegisterInbandCallback_IMPL(pGpu, pKernelNvlink, params) +#endif //__nvoc_kernel_nvlink_h_disabled + +#define knvlinkRegisterInbandCallback_HAL(pGpu, pKernelNvlink, params) knvlinkRegisterInbandCallback(pGpu, pKernelNvlink, params) + +NV_STATUS knvlinkUnregisterInbandCallback_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU16 msgType); + + +#ifdef __nvoc_kernel_nvlink_h_disabled +static inline NV_STATUS knvlinkUnregisterInbandCallback(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU16 msgType) { + NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_nvlink_h_disabled +#define knvlinkUnregisterInbandCallback(pGpu, pKernelNvlink, msgType) knvlinkUnregisterInbandCallback_IMPL(pGpu, pKernelNvlink, msgType) +#endif //__nvoc_kernel_nvlink_h_disabled + +#define knvlinkUnregisterInbandCallback_HAL(pGpu, pKernelNvlink, msgType) knvlinkUnregisterInbandCallback(pGpu, pKernelNvlink, msgType) + NV_STATUS knvlinkCoreGetRemoteDeviceInfo_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkCoreGetRemoteDeviceInfo(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -669,6 +750,7 @@ static inline NV_STATUS knvlinkCoreGetRemoteDeviceInfo(OBJGPU *pGpu, struct Kern NvBool knvlinkIsGpuConnectedToNvswitch_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NvBool knvlinkIsGpuConnectedToNvswitch(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -682,6 +764,7 @@ static inline NvBool knvlinkIsGpuConnectedToNvswitch(OBJGPU *pGpu, struct Kernel NvBool knvlinkIsLinkConnected_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NvBool knvlinkIsLinkConnected(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -695,6 +778,7 @@ static inline NvBool knvlinkIsLinkConnected(OBJGPU *pGpu, struct KernelNvlink *p NV_STATUS knvlinkTrainSysmemLinksToActive_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkTrainSysmemLinksToActive(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -708,6 +792,7 @@ static inline NV_STATUS knvlinkTrainSysmemLinksToActive(OBJGPU *pGpu, struct Ker NV_STATUS knvlinkTrainP2pLinksToActive_IMPL(OBJGPU *pGpu0, OBJGPU *pGpu1, struct KernelNvlink *pKernelNvlink); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkTrainP2pLinksToActive(OBJGPU *pGpu0, OBJGPU *pGpu1, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -721,6 +806,7 @@ static inline NV_STATUS knvlinkTrainP2pLinksToActive(OBJGPU *pGpu0, OBJGPU *pGpu NV_STATUS knvlinkCheckTrainingIsComplete_IMPL(OBJGPU *pGpu0, OBJGPU *pGpu1, struct KernelNvlink *pKernelNvlink); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkCheckTrainingIsComplete(OBJGPU *pGpu0, OBJGPU *pGpu1, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -734,6 +820,7 @@ static inline NV_STATUS knvlinkCheckTrainingIsComplete(OBJGPU *pGpu0, OBJGPU *pG NV_STATUS knvlinkTrainFabricLinksToActive_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkTrainFabricLinksToActive(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -747,6 +834,7 @@ static inline NV_STATUS knvlinkTrainFabricLinksToActive(OBJGPU *pGpu, struct Ker NV_STATUS knvlinkRetrainLink_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 linkId, NvBool bFromOff); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkRetrainLink(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 linkId, NvBool bFromOff) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -760,6 +848,7 @@ static inline NV_STATUS knvlinkRetrainLink(OBJGPU *pGpu, struct KernelNvlink *pK NvU32 knvlinkGetEnabledLinkMask_IMPL(OBJGPU *pGpu, struct KernelNvlink *arg0); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NvU32 knvlinkGetEnabledLinkMask(OBJGPU *pGpu, struct KernelNvlink *arg0) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -773,6 +862,7 @@ static inline NvU32 knvlinkGetEnabledLinkMask(OBJGPU *pGpu, struct KernelNvlink NvU32 knvlinkGetDiscoveredLinkMask_IMPL(OBJGPU *pGpu, struct KernelNvlink *arg0); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NvU32 knvlinkGetDiscoveredLinkMask(OBJGPU *pGpu, struct KernelNvlink *arg0) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -786,6 +876,7 @@ static inline NvU32 knvlinkGetDiscoveredLinkMask(OBJGPU *pGpu, struct KernelNvli NV_STATUS knvlinkProcessInitDisabledLinks_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkProcessInitDisabledLinks(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -799,6 +890,7 @@ static inline NV_STATUS knvlinkProcessInitDisabledLinks(OBJGPU *pGpu, struct Ker NvU32 knvlinkGetNumLinksToSystem_IMPL(OBJGPU *arg0, struct KernelNvlink *arg1); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NvU32 knvlinkGetNumLinksToSystem(OBJGPU *arg0, struct KernelNvlink *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -812,6 +904,7 @@ static inline NvU32 knvlinkGetNumLinksToSystem(OBJGPU *arg0, struct KernelNvlink NvU32 knvlinkGetNumLinksToPeer_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pRemoteGpu); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NvU32 knvlinkGetNumLinksToPeer(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pRemoteGpu) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -825,6 +918,7 @@ static inline NvU32 knvlinkGetNumLinksToPeer(OBJGPU *pGpu, struct KernelNvlink * NvU32 knvlinkGetLinkMaskToPeer_IMPL(OBJGPU *pGpu0, struct KernelNvlink *pKernelNvlink0, OBJGPU *pGpu1); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NvU32 knvlinkGetLinkMaskToPeer(OBJGPU *pGpu0, struct KernelNvlink *pKernelNvlink0, OBJGPU *pGpu1) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -838,6 +932,7 @@ static inline NvU32 knvlinkGetLinkMaskToPeer(OBJGPU *pGpu0, struct KernelNvlink NV_STATUS knvlinkSetLinkMaskToPeer_IMPL(OBJGPU *pGpu0, struct KernelNvlink *pKernelNvlink0, OBJGPU *pGpu1, NvU32 peerLinkMask); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkSetLinkMaskToPeer(OBJGPU *pGpu0, struct KernelNvlink *pKernelNvlink0, OBJGPU *pGpu1, NvU32 peerLinkMask) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -851,6 +946,7 @@ static inline NV_STATUS knvlinkSetLinkMaskToPeer(OBJGPU *pGpu0, struct KernelNvl NvU32 knvlinkGetPeersNvlinkMaskFromHshub_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NvU32 knvlinkGetPeersNvlinkMaskFromHshub(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -864,6 +960,7 @@ static inline NvU32 knvlinkGetPeersNvlinkMaskFromHshub(OBJGPU *pGpu, struct Kern NV_STATUS knvlinkPrepareForXVEReset_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvBool bForcePowerDown); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkPrepareForXVEReset(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvBool bForcePowerDown) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -877,6 +974,7 @@ static inline NV_STATUS knvlinkPrepareForXVEReset(OBJGPU *pGpu, struct KernelNvl NV_STATUS knvlinkEnterExitSleep_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0, NvBool arg1); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkEnterExitSleep(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0, NvBool arg1) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -890,6 +988,7 @@ static inline NV_STATUS knvlinkEnterExitSleep(OBJGPU *pGpu, struct KernelNvlink NV_STATUS knvlinkSyncLinkMasksAndVbiosInfo_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkSyncLinkMasksAndVbiosInfo(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -901,8 +1000,37 @@ static inline NV_STATUS knvlinkSyncLinkMasksAndVbiosInfo(OBJGPU *pGpu, struct Ke #define knvlinkSyncLinkMasksAndVbiosInfo_HAL(pGpu, pKernelNvlink) knvlinkSyncLinkMasksAndVbiosInfo(pGpu, pKernelNvlink) +NV_STATUS knvlinkInbandMsgCallbackDispatcher_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvLink, NvU32 dataSize, NvU8 *pMessage); + + +#ifdef __nvoc_kernel_nvlink_h_disabled +static inline NV_STATUS knvlinkInbandMsgCallbackDispatcher(OBJGPU *pGpu, struct KernelNvlink *pKernelNvLink, NvU32 dataSize, NvU8 *pMessage) { + NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_nvlink_h_disabled +#define knvlinkInbandMsgCallbackDispatcher(pGpu, pKernelNvLink, dataSize, pMessage) knvlinkInbandMsgCallbackDispatcher_IMPL(pGpu, pKernelNvLink, dataSize, pMessage) +#endif //__nvoc_kernel_nvlink_h_disabled + +#define knvlinkInbandMsgCallbackDispatcher_HAL(pGpu, pKernelNvLink, dataSize, pMessage) knvlinkInbandMsgCallbackDispatcher(pGpu, pKernelNvLink, dataSize, pMessage) + +NV_STATUS knvlinkSendInbandData_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS *pParams); + + +#ifdef __nvoc_kernel_nvlink_h_disabled +static inline NV_STATUS knvlinkSendInbandData(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS *pParams) { + NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_nvlink_h_disabled +#define knvlinkSendInbandData(pGpu, pKernelNvlink, pParams) knvlinkSendInbandData_IMPL(pGpu, pKernelNvlink, pParams) +#endif //__nvoc_kernel_nvlink_h_disabled + +#define knvlinkSendInbandData_HAL(pGpu, pKernelNvlink, pParams) knvlinkSendInbandData(pGpu, pKernelNvlink, pParams) + NV_STATUS knvlinkUpdateLinkConnectionStatus_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkUpdateLinkConnectionStatus(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -916,6 +1044,7 @@ static inline NV_STATUS knvlinkUpdateLinkConnectionStatus(OBJGPU *pGpu, struct K NV_STATUS knvlinkPreTrainLinksToActiveAli_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0, NvBool arg1); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkPreTrainLinksToActiveAli(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0, NvBool arg1) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -929,6 +1058,7 @@ static inline NV_STATUS knvlinkPreTrainLinksToActiveAli(OBJGPU *pGpu, struct Ker NV_STATUS knvlinkTrainLinksToActiveAli_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0, NvBool arg1); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkTrainLinksToActiveAli(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0, NvBool arg1) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -942,6 +1072,7 @@ static inline NV_STATUS knvlinkTrainLinksToActiveAli(OBJGPU *pGpu, struct Kernel NV_STATUS knvlinkUpdatePostRxDetectLinkMask_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkUpdatePostRxDetectLinkMask(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -955,6 +1086,7 @@ static inline NV_STATUS knvlinkUpdatePostRxDetectLinkMask(OBJGPU *pGpu, struct K NV_STATUS knvlinkCopyNvlinkDeviceInfo_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkCopyNvlinkDeviceInfo(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -968,6 +1100,7 @@ static inline NV_STATUS knvlinkCopyNvlinkDeviceInfo(OBJGPU *pGpu, struct KernelN NV_STATUS knvlinkCopyIoctrlDeviceInfo_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkCopyIoctrlDeviceInfo(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -981,6 +1114,7 @@ static inline NV_STATUS knvlinkCopyIoctrlDeviceInfo(OBJGPU *pGpu, struct KernelN NV_STATUS knvlinkSetupTopologyForForcedConfig_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkSetupTopologyForForcedConfig(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -994,6 +1128,7 @@ static inline NV_STATUS knvlinkSetupTopologyForForcedConfig(OBJGPU *pGpu, struct NV_STATUS knvlinkSyncLaneShutdownProps_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkSyncLaneShutdownProps(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -1007,6 +1142,7 @@ static inline NV_STATUS knvlinkSyncLaneShutdownProps(OBJGPU *pGpu, struct Kernel void knvlinkSetPowerFeatures_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline void knvlinkSetPowerFeatures(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -1019,6 +1155,7 @@ static inline void knvlinkSetPowerFeatures(OBJGPU *pGpu, struct KernelNvlink *pK NV_STATUS knvlinkExecGspRmRpc_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0, void *arg1, NvU32 arg2); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkExecGspRmRpc(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0, void *arg1, NvU32 arg2) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -1032,6 +1169,7 @@ static inline NV_STATUS knvlinkExecGspRmRpc(OBJGPU *pGpu, struct KernelNvlink *p NvBool knvlinkIsNvswitchProxyPresent_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NvBool knvlinkIsNvswitchProxyPresent(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -1045,6 +1183,7 @@ static inline NvBool knvlinkIsNvswitchProxyPresent(OBJGPU *pGpu, struct KernelNv void knvlinkDetectNvswitchProxy_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline void knvlinkDetectNvswitchProxy(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -1057,6 +1196,7 @@ static inline void knvlinkDetectNvswitchProxy(OBJGPU *pGpu, struct KernelNvlink NV_STATUS knvlinkSetUniqueFlaBaseAddress_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkSetUniqueFlaBaseAddress(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -1068,10 +1208,25 @@ static inline NV_STATUS knvlinkSetUniqueFlaBaseAddress(OBJGPU *pGpu, struct Kern #define knvlinkSetUniqueFlaBaseAddress_HAL(pGpu, pKernelNvlink, arg0) knvlinkSetUniqueFlaBaseAddress(pGpu, pKernelNvlink, arg0) +NV_STATUS knvlinkFloorSweep_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 numLinksPerIp, NvU32 *pNumActiveLinks); + + +#ifdef __nvoc_kernel_nvlink_h_disabled +static inline NV_STATUS knvlinkFloorSweep(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 numLinksPerIp, NvU32 *pNumActiveLinks) { + NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_nvlink_h_disabled +#define knvlinkFloorSweep(pGpu, pKernelNvlink, numLinksPerIp, pNumActiveLinks) knvlinkFloorSweep_IMPL(pGpu, pKernelNvlink, numLinksPerIp, pNumActiveLinks) +#endif //__nvoc_kernel_nvlink_h_disabled + +#define knvlinkFloorSweep_HAL(pGpu, pKernelNvlink, numLinksPerIp, pNumActiveLinks) knvlinkFloorSweep(pGpu, pKernelNvlink, numLinksPerIp, pNumActiveLinks) + static inline NvU64 knvlinkGetUniqueFabricBaseAddress_72249a(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { return pKernelNvlink->fabricBaseAddr; } + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NvU64 knvlinkGetUniqueFabricBaseAddress(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -1083,21 +1238,9 @@ static inline NvU64 knvlinkGetUniqueFabricBaseAddress(OBJGPU *pGpu, struct Kerne #define knvlinkGetUniqueFabricBaseAddress_HAL(pGpu, pKernelNvlink) knvlinkGetUniqueFabricBaseAddress(pGpu, pKernelNvlink) -NV_STATUS knvlinkSetUniqueFabricBaseAddress_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0); - -#ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkSetUniqueFabricBaseAddress(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0) { - NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_nvlink_h_disabled -#define knvlinkSetUniqueFabricBaseAddress(pGpu, pKernelNvlink, arg0) knvlinkSetUniqueFabricBaseAddress_IMPL(pGpu, pKernelNvlink, arg0) -#endif //__nvoc_kernel_nvlink_h_disabled - -#define knvlinkSetUniqueFabricBaseAddress_HAL(pGpu, pKernelNvlink, arg0) knvlinkSetUniqueFabricBaseAddress(pGpu, pKernelNvlink, arg0) - NV_STATUS knvlinkStatePostLoadHal_GV100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkStatePostLoadHal(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -1111,6 +1254,7 @@ static inline NV_STATUS knvlinkStatePostLoadHal(OBJGPU *pGpu, struct KernelNvlin NV_STATUS knvlinkApplyNvswitchDegradedModeSettings_GV100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 *switchLinkMasks); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkApplyNvswitchDegradedModeSettings(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 *switchLinkMasks) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -1124,6 +1268,7 @@ static inline NV_STATUS knvlinkApplyNvswitchDegradedModeSettings(OBJGPU *pGpu, s NvU32 knvlinkGetNumActiveLinksPerIoctrl_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NvU32 knvlinkGetNumActiveLinksPerIoctrl(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -1137,6 +1282,7 @@ static inline NvU32 knvlinkGetNumActiveLinksPerIoctrl(OBJGPU *pGpu, struct Kerne NvU32 knvlinkGetTotalNumLinksPerIoctrl_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NvU32 knvlinkGetTotalNumLinksPerIoctrl(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -1190,8 +1336,16 @@ static inline NvBool knvlinkIsPresent_DISPATCH(OBJGPU *arg0, struct KernelNvlink return arg1->__knvlinkIsPresent__(arg0, arg1); } -static inline NV_STATUS knvlinkValidateFabricBaseAddress_56cd7a(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0) { - return NV_OK; +NV_STATUS knvlinkSetUniqueFabricBaseAddress_GV100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0); + +NV_STATUS knvlinkSetUniqueFabricBaseAddress_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0); + +static inline NV_STATUS knvlinkSetUniqueFabricBaseAddress_46f6a7(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS knvlinkSetUniqueFabricBaseAddress_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0) { + return pKernelNvlink->__knvlinkSetUniqueFabricBaseAddress__(pGpu, pKernelNvlink, arg0); } NV_STATUS knvlinkValidateFabricBaseAddress_GA100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0); @@ -1238,10 +1392,6 @@ static inline NV_STATUS knvlinkOverrideConfig_DISPATCH(OBJGPU *pGpu, struct Kern return pKernelNvlink->__knvlinkOverrideConfig__(pGpu, pKernelNvlink, arg0); } -static inline NV_STATUS knvlinkFilterBridgeLinks_56cd7a(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { - return NV_OK; -} - NV_STATUS knvlinkFilterBridgeLinks_TU102(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); static inline NV_STATUS knvlinkFilterBridgeLinks_46f6a7(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { @@ -1252,10 +1402,6 @@ static inline NV_STATUS knvlinkFilterBridgeLinks_DISPATCH(OBJGPU *pGpu, struct K return pKernelNvlink->__knvlinkFilterBridgeLinks__(pGpu, pKernelNvlink); } -static inline NvU32 knvlinkGetUniquePeerIdMask_4a4dee(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { - return 0; -} - NvU32 knvlinkGetUniquePeerIdMask_GP100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); static inline NvU32 knvlinkGetUniquePeerIdMask_15a734(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { @@ -1358,10 +1504,6 @@ static inline NV_STATUS knvlinkPostSetupNvlinkPeer_DISPATCH(OBJGPU *pGpu, struct return pKernelNvlink->__knvlinkPostSetupNvlinkPeer__(pGpu, pKernelNvlink); } -static inline NV_STATUS knvlinkDiscoverPostRxDetLinks_56cd7a(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pPeerGpu) { - return NV_OK; -} - NV_STATUS knvlinkDiscoverPostRxDetLinks_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pPeerGpu); static inline NV_STATUS knvlinkDiscoverPostRxDetLinks_46f6a7(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pPeerGpu) { @@ -1372,6 +1514,26 @@ static inline NV_STATUS knvlinkDiscoverPostRxDetLinks_DISPATCH(OBJGPU *pGpu, str return pKernelNvlink->__knvlinkDiscoverPostRxDetLinks__(pGpu, pKernelNvlink, pPeerGpu); } +NV_STATUS knvlinkLogAliDebugMessages_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); + +static inline NV_STATUS knvlinkLogAliDebugMessages_46f6a7(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS knvlinkLogAliDebugMessages_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { + return pKernelNvlink->__knvlinkLogAliDebugMessages__(pGpu, pKernelNvlink); +} + +static inline NvBool knvlinkIsFloorSweepingNeeded_491d52(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 numActiveLinksPerIoctrl, NvU32 numLinksPerIoctrl) { + return ((NvBool)(0 != 0)); +} + +NvBool knvlinkIsFloorSweepingNeeded_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 numActiveLinksPerIoctrl, NvU32 numLinksPerIoctrl); + +static inline NvBool knvlinkIsFloorSweepingNeeded_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 numActiveLinksPerIoctrl, NvU32 numLinksPerIoctrl) { + return pKernelNvlink->__knvlinkIsFloorSweepingNeeded__(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl); +} + static inline NV_STATUS knvlinkReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelNvlink *pEngstate, void *pTunableState) { return pEngstate->__knvlinkReconcileTunableState__(pGpu, pEngstate, pTunableState); } @@ -1425,8 +1587,10 @@ static inline NV_STATUS knvlinkSetTunableState_DISPATCH(POBJGPU pGpu, struct Ker } void knvlinkDestruct_IMPL(struct KernelNvlink *arg0); + #define __nvoc_knvlinkDestruct(arg0) knvlinkDestruct_IMPL(arg0) NV_STATUS knvlinkRemoveMissingIoctrlObjects_IMPL(OBJGPU *arg0, struct KernelNvlink *arg1); + #ifdef __nvoc_kernel_nvlink_h_disabled static inline NV_STATUS knvlinkRemoveMissingIoctrlObjects(OBJGPU *arg0, struct KernelNvlink *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); @@ -1497,8 +1661,6 @@ NvlStatus knvlinkCoreAliTrainingCallback (nvlink_link *link); // NVLINK Utility Functions void knvlinkUtoa(NvU8 *, NvU64, NvU64); -NV_STATUS knvlinkCtrlCmdBusGetNvlinkCaps(OBJGPU *pGpu, NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS *pParams); - #endif // _KERNEL_NVLINK_H_ #ifdef __cplusplus diff --git a/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.c b/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.c index ebb5f8561..c566e4e2d 100644 --- a/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.c +++ b/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.c @@ -220,6 +220,10 @@ static void __nvoc_thunk_RsResource_ofactxPreDestruct(struct OfaContext *pResour resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OfaContext_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_RsResource_ofactxIsDuplicate(struct OfaContext *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OfaContext_RsResource.offset), hMemory, pDuplicate); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_ofactxGetNotificationListPtr(struct OfaContext *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_OfaContext_Notifier.offset)); } @@ -335,6 +339,8 @@ static void __nvoc_init_funcTable_OfaContext_1(OfaContext *pThis, RmHalspecOwner pThis->__ofactxPreDestruct__ = &__nvoc_thunk_RsResource_ofactxPreDestruct; + pThis->__ofactxIsDuplicate__ = &__nvoc_thunk_RsResource_ofactxIsDuplicate; + pThis->__ofactxGetNotificationListPtr__ = &__nvoc_thunk_Notifier_ofactxGetNotificationListPtr; pThis->__ofactxGetNotificationShare__ = &__nvoc_thunk_Notifier_ofactxGetNotificationShare; diff --git a/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.h b/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.h index 63c9f61bf..657521f28 100644 --- a/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.h +++ b/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.h @@ -81,6 +81,7 @@ struct OfaContext { NV_STATUS (*__ofactxUnregisterEvent__)(struct OfaContext *, NvHandle, NvHandle, NvHandle, NvHandle); NvBool (*__ofactxCanCopy__)(struct OfaContext *); void (*__ofactxPreDestruct__)(struct OfaContext *); + NV_STATUS (*__ofactxIsDuplicate__)(struct OfaContext *, NvHandle, NvBool *); PEVENTNOTIFICATION *(*__ofactxGetNotificationListPtr__)(struct OfaContext *); struct NotifShare *(*__ofactxGetNotificationShare__)(struct OfaContext *); NV_STATUS (*__ofactxMap__)(struct OfaContext *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -140,12 +141,14 @@ NV_STATUS __nvoc_objCreate_OfaContext(OfaContext**, Dynamic*, NvU32, struct CALL #define ofactxUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) ofactxUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define ofactxCanCopy(pResource) ofactxCanCopy_DISPATCH(pResource) #define ofactxPreDestruct(pResource) ofactxPreDestruct_DISPATCH(pResource) +#define ofactxIsDuplicate(pResource, hMemory, pDuplicate) ofactxIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define ofactxGetNotificationListPtr(pNotifier) ofactxGetNotificationListPtr_DISPATCH(pNotifier) #define ofactxGetNotificationShare(pNotifier) ofactxGetNotificationShare_DISPATCH(pNotifier) #define ofactxMap(pGpuResource, pCallContext, pParams, pCpuMapping) ofactxMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define ofactxGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) ofactxGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) NV_STATUS ofactxConstructHal_KERNEL(struct OfaContext *pOfaContext, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); + #ifdef __nvoc_kernel_ofa_ctx_h_disabled static inline NV_STATUS ofactxConstructHal(struct OfaContext *pOfaContext, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { NV_ASSERT_FAILED_PRECOMP("OfaContext was disabled!"); @@ -159,6 +162,7 @@ static inline NV_STATUS ofactxConstructHal(struct OfaContext *pOfaContext, struc void ofactxDestructHal_KERNEL(struct OfaContext *pOfaContext); + #ifdef __nvoc_kernel_ofa_ctx_h_disabled static inline void ofactxDestructHal(struct OfaContext *pOfaContext) { NV_ASSERT_FAILED_PRECOMP("OfaContext was disabled!"); @@ -269,6 +273,10 @@ static inline void ofactxPreDestruct_DISPATCH(struct OfaContext *pResource) { pResource->__ofactxPreDestruct__(pResource); } +static inline NV_STATUS ofactxIsDuplicate_DISPATCH(struct OfaContext *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__ofactxIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline PEVENTNOTIFICATION *ofactxGetNotificationListPtr_DISPATCH(struct OfaContext *pNotifier) { return pNotifier->__ofactxGetNotificationListPtr__(pNotifier); } diff --git a/src/nvidia/generated/g_kernel_rc_nvoc.h b/src/nvidia/generated/g_kernel_rc_nvoc.h index ee92cb0a4..2026ec8ed 100644 --- a/src/nvidia/generated/g_kernel_rc_nvoc.h +++ b/src/nvidia/generated/g_kernel_rc_nvoc.h @@ -41,16 +41,15 @@ extern "C" { #include "kernel/gpu/mmu/kern_gmmu.h" #include "kernel/gpu/rc/kernel_rc_watchdog.h" #include "kernel/gpu/rc/kernel_rc_watchdog_private.h" +#include "kernel/gpu/gpu_engine_type.h" #include "kernel/gpu/subdevice/subdevice.h" #include "kernel/rmapi/client_resource.h" - typedef enum { RC_NOTIFIER_SCOPE_CHANNEL = 0, RC_NOTIFIER_SCOPE_TSG, } RC_NOTIFIER_SCOPE; - /*! * Kernel interface for RC (Robust Channels) and Watchdog */ @@ -145,34 +144,37 @@ NV_STATUS __nvoc_objCreate_KernelRc(KernelRc**, Dynamic*, NvU32); #define krcAllocTunableState(pGpu, pEngstate, ppTunableState) krcAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) #define krcSetTunableState(pGpu, pEngstate, pTunableState) krcSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define krcIsPresent(pGpu, pEngstate) krcIsPresent_DISPATCH(pGpu, pEngstate) -NV_STATUS krcErrorWriteNotifier_CPU(struct OBJGPU *pGpu, struct KernelRc *pKernelRc, struct KernelChannel *pKernelChannel, NvU32 exceptType, NvU32 localEngineType, NV_STATUS notifierStatus, NvU32 *pFlushFlags); +NV_STATUS krcErrorWriteNotifier_CPU(struct OBJGPU *pGpu, struct KernelRc *pKernelRc, struct KernelChannel *pKernelChannel, NvU32 exceptType, RM_ENGINE_TYPE localRmEngineType, NV_STATUS notifierStatus, NvU32 *pFlushFlags); + #ifdef __nvoc_kernel_rc_h_disabled -static inline NV_STATUS krcErrorWriteNotifier(struct OBJGPU *pGpu, struct KernelRc *pKernelRc, struct KernelChannel *pKernelChannel, NvU32 exceptType, NvU32 localEngineType, NV_STATUS notifierStatus, NvU32 *pFlushFlags) { +static inline NV_STATUS krcErrorWriteNotifier(struct OBJGPU *pGpu, struct KernelRc *pKernelRc, struct KernelChannel *pKernelChannel, NvU32 exceptType, RM_ENGINE_TYPE localRmEngineType, NV_STATUS notifierStatus, NvU32 *pFlushFlags) { NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_rc_h_disabled -#define krcErrorWriteNotifier(pGpu, pKernelRc, pKernelChannel, exceptType, localEngineType, notifierStatus, pFlushFlags) krcErrorWriteNotifier_CPU(pGpu, pKernelRc, pKernelChannel, exceptType, localEngineType, notifierStatus, pFlushFlags) +#define krcErrorWriteNotifier(pGpu, pKernelRc, pKernelChannel, exceptType, localRmEngineType, notifierStatus, pFlushFlags) krcErrorWriteNotifier_CPU(pGpu, pKernelRc, pKernelChannel, exceptType, localRmEngineType, notifierStatus, pFlushFlags) #endif //__nvoc_kernel_rc_h_disabled -#define krcErrorWriteNotifier_HAL(pGpu, pKernelRc, pKernelChannel, exceptType, localEngineType, notifierStatus, pFlushFlags) krcErrorWriteNotifier(pGpu, pKernelRc, pKernelChannel, exceptType, localEngineType, notifierStatus, pFlushFlags) +#define krcErrorWriteNotifier_HAL(pGpu, pKernelRc, pKernelChannel, exceptType, localRmEngineType, notifierStatus, pFlushFlags) krcErrorWriteNotifier(pGpu, pKernelRc, pKernelChannel, exceptType, localRmEngineType, notifierStatus, pFlushFlags) + +NV_STATUS krcErrorSendEventNotifications_KERNEL(struct OBJGPU *pGpu, struct KernelRc *pKernelRc, struct KernelChannel *pKernelChannel, RM_ENGINE_TYPE rmEngineType, NvU32 exceptType, RC_NOTIFIER_SCOPE scope, NvU16 partitionAttributionId); -NV_STATUS krcErrorSendEventNotifications_KERNEL(struct OBJGPU *pGpu, struct KernelRc *pKernelRc, struct KernelChannel *pKernelChannel, NvU32 engineId, NvU32 exceptType, RC_NOTIFIER_SCOPE scope, NvU16 partitionAttributionId); #ifdef __nvoc_kernel_rc_h_disabled -static inline NV_STATUS krcErrorSendEventNotifications(struct OBJGPU *pGpu, struct KernelRc *pKernelRc, struct KernelChannel *pKernelChannel, NvU32 engineId, NvU32 exceptType, RC_NOTIFIER_SCOPE scope, NvU16 partitionAttributionId) { +static inline NV_STATUS krcErrorSendEventNotifications(struct OBJGPU *pGpu, struct KernelRc *pKernelRc, struct KernelChannel *pKernelChannel, RM_ENGINE_TYPE rmEngineType, NvU32 exceptType, RC_NOTIFIER_SCOPE scope, NvU16 partitionAttributionId) { NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_rc_h_disabled -#define krcErrorSendEventNotifications(pGpu, pKernelRc, pKernelChannel, engineId, exceptType, scope, partitionAttributionId) krcErrorSendEventNotifications_KERNEL(pGpu, pKernelRc, pKernelChannel, engineId, exceptType, scope, partitionAttributionId) +#define krcErrorSendEventNotifications(pGpu, pKernelRc, pKernelChannel, rmEngineType, exceptType, scope, partitionAttributionId) krcErrorSendEventNotifications_KERNEL(pGpu, pKernelRc, pKernelChannel, rmEngineType, exceptType, scope, partitionAttributionId) #endif //__nvoc_kernel_rc_h_disabled -#define krcErrorSendEventNotifications_HAL(pGpu, pKernelRc, pKernelChannel, engineId, exceptType, scope, partitionAttributionId) krcErrorSendEventNotifications(pGpu, pKernelRc, pKernelChannel, engineId, exceptType, scope, partitionAttributionId) +#define krcErrorSendEventNotifications_HAL(pGpu, pKernelRc, pKernelChannel, rmEngineType, exceptType, scope, partitionAttributionId) krcErrorSendEventNotifications(pGpu, pKernelRc, pKernelChannel, rmEngineType, exceptType, scope, partitionAttributionId) NV_STATUS krcErrorSendEventNotificationsCtxDma_FWCLIENT(struct OBJGPU *pGpu, struct KernelRc *pKernelRc, struct KernelChannel *pKernelChannel, RC_NOTIFIER_SCOPE scope); + #ifdef __nvoc_kernel_rc_h_disabled static inline NV_STATUS krcErrorSendEventNotificationsCtxDma(struct OBJGPU *pGpu, struct KernelRc *pKernelRc, struct KernelChannel *pKernelChannel, RC_NOTIFIER_SCOPE scope) { NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); @@ -186,6 +188,7 @@ static inline NV_STATUS krcErrorSendEventNotificationsCtxDma(struct OBJGPU *pGpu void krcGetMigAttributionForError_KERNEL(struct KernelRc *pKernelRc, NvU32 exceptType, NvU16 *pGpuPartitionId, NvU16 *pComputeInstanceId); + #ifdef __nvoc_kernel_rc_h_disabled static inline void krcGetMigAttributionForError(struct KernelRc *pKernelRc, NvU32 exceptType, NvU16 *pGpuPartitionId, NvU16 *pComputeInstanceId) { NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); @@ -198,6 +201,7 @@ static inline void krcGetMigAttributionForError(struct KernelRc *pKernelRc, NvU3 struct KernelChannel *krcGetChannelInError_FWCLIENT(struct KernelRc *pKernelRc); + #ifdef __nvoc_kernel_rc_h_disabled static inline struct KernelChannel *krcGetChannelInError(struct KernelRc *pKernelRc) { NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); @@ -211,6 +215,7 @@ static inline struct KernelChannel *krcGetChannelInError(struct KernelRc *pKerne NV_STATUS krcSubdeviceCtrlGetErrorInfoCheckPermissions_KERNEL(struct KernelRc *pKernelRc, struct Subdevice *pSubdevice); + #ifdef __nvoc_kernel_rc_h_disabled static inline NV_STATUS krcSubdeviceCtrlGetErrorInfoCheckPermissions(struct KernelRc *pKernelRc, struct Subdevice *pSubdevice) { NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); @@ -224,6 +229,7 @@ static inline NV_STATUS krcSubdeviceCtrlGetErrorInfoCheckPermissions(struct Kern NV_STATUS krcCheckBusError_KERNEL(struct OBJGPU *pGpu, struct KernelRc *pKernelRc); + #ifdef __nvoc_kernel_rc_h_disabled static inline NV_STATUS krcCheckBusError(struct OBJGPU *pGpu, struct KernelRc *pKernelRc) { NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); @@ -237,6 +243,7 @@ static inline NV_STATUS krcCheckBusError(struct OBJGPU *pGpu, struct KernelRc *p NV_STATUS krcCliresCtrlNvdGetRcerrRptCheckPermissions_KERNEL(struct KernelRc *pKernelRc, struct RmClientResource *pRmCliRes, NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS *pReportParams); + #ifdef __nvoc_kernel_rc_h_disabled static inline NV_STATUS krcCliresCtrlNvdGetRcerrRptCheckPermissions(struct KernelRc *pKernelRc, struct RmClientResource *pRmCliRes, NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS *pReportParams) { NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); @@ -250,6 +257,7 @@ static inline NV_STATUS krcCliresCtrlNvdGetRcerrRptCheckPermissions(struct Kerne NV_STATUS krcWatchdogInit_IMPL(struct OBJGPU *pGpu, struct KernelRc *pKernelRc); + #ifdef __nvoc_kernel_rc_h_disabled static inline NV_STATUS krcWatchdogInit(struct OBJGPU *pGpu, struct KernelRc *pKernelRc) { NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); @@ -263,6 +271,7 @@ static inline NV_STATUS krcWatchdogInit(struct OBJGPU *pGpu, struct KernelRc *pK void krcWatchdogInitPushbuffer_IMPL(struct OBJGPU *pGpu, struct KernelRc *pKernelRc); + #ifdef __nvoc_kernel_rc_h_disabled static inline void krcWatchdogInitPushbuffer(struct OBJGPU *pGpu, struct KernelRc *pKernelRc) { NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); @@ -275,6 +284,7 @@ static inline void krcWatchdogInitPushbuffer(struct OBJGPU *pGpu, struct KernelR void krcWatchdog_IMPL(struct OBJGPU *pGpu, struct KernelRc *pKernelRc); + #ifdef __nvoc_kernel_rc_h_disabled static inline void krcWatchdog(struct OBJGPU *pGpu, struct KernelRc *pKernelRc) { NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); @@ -287,6 +297,7 @@ static inline void krcWatchdog(struct OBJGPU *pGpu, struct KernelRc *pKernelRc) void krcWatchdogRecovery_KERNEL(struct OBJGPU *pGpu, struct KernelRc *pKernelRc); + #ifdef __nvoc_kernel_rc_h_disabled static inline void krcWatchdogRecovery(struct OBJGPU *pGpu, struct KernelRc *pKernelRc) { NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); @@ -297,24 +308,11 @@ static inline void krcWatchdogRecovery(struct OBJGPU *pGpu, struct KernelRc *pKe #define krcWatchdogRecovery_HAL(pGpu, pKernelRc) krcWatchdogRecovery(pGpu, pKernelRc) -static inline void krcWatchdogCallbackVblankRecovery_b3696a(struct OBJGPU *pGpu, struct KernelRc *pKernelRc) { - return; -} - -#ifdef __nvoc_kernel_rc_h_disabled -static inline void krcWatchdogCallbackVblankRecovery(struct OBJGPU *pGpu, struct KernelRc *pKernelRc) { - NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); -} -#else //__nvoc_kernel_rc_h_disabled -#define krcWatchdogCallbackVblankRecovery(pGpu, pKernelRc) krcWatchdogCallbackVblankRecovery_b3696a(pGpu, pKernelRc) -#endif //__nvoc_kernel_rc_h_disabled - -#define krcWatchdogCallbackVblankRecovery_HAL(pGpu, pKernelRc) krcWatchdogCallbackVblankRecovery(pGpu, pKernelRc) - static inline void krcWatchdogCallbackPerf_b3696a(struct OBJGPU *pGpu, struct KernelRc *pKernelRc) { return; } + #ifdef __nvoc_kernel_rc_h_disabled static inline void krcWatchdogCallbackPerf(struct OBJGPU *pGpu, struct KernelRc *pKernelRc) { NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); @@ -408,6 +406,7 @@ static inline NvBool krcIsPresent_DISPATCH(POBJGPU pGpu, struct KernelRc *pEngst } void krcInitRegistryOverridesDelayed_IMPL(struct OBJGPU *pGpu, struct KernelRc *pKernelRc); + #ifdef __nvoc_kernel_rc_h_disabled static inline void krcInitRegistryOverridesDelayed(struct OBJGPU *pGpu, struct KernelRc *pKernelRc) { NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); @@ -417,6 +416,7 @@ static inline void krcInitRegistryOverridesDelayed(struct OBJGPU *pGpu, struct K #endif //__nvoc_kernel_rc_h_disabled NV_STATUS krcErrorSetNotifier_IMPL(struct OBJGPU *pGpu, struct KernelRc *pKernelRc, struct KernelChannel *pKernelChannel, NvU32 exceptType, NvU32 nv2080EngineType, RC_NOTIFIER_SCOPE scope); + #ifdef __nvoc_kernel_rc_h_disabled static inline NV_STATUS krcErrorSetNotifier(struct OBJGPU *pGpu, struct KernelRc *pKernelRc, struct KernelChannel *pKernelChannel, NvU32 exceptType, NvU32 nv2080EngineType, RC_NOTIFIER_SCOPE scope) { NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); @@ -427,6 +427,7 @@ static inline NV_STATUS krcErrorSetNotifier(struct OBJGPU *pGpu, struct KernelRc #endif //__nvoc_kernel_rc_h_disabled NV_STATUS krcReadVirtMem_IMPL(struct OBJGPU *pGpu, struct KernelRc *pKernelRc, struct KernelChannel *pKernelChannel, NvU64 virtAddr, NvP64 bufPtr, NvU32 bufSize); + #ifdef __nvoc_kernel_rc_h_disabled static inline NV_STATUS krcReadVirtMem(struct OBJGPU *pGpu, struct KernelRc *pKernelRc, struct KernelChannel *pKernelChannel, NvU64 virtAddr, NvP64 bufPtr, NvU32 bufSize) { NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); @@ -437,6 +438,7 @@ static inline NV_STATUS krcReadVirtMem(struct OBJGPU *pGpu, struct KernelRc *pKe #endif //__nvoc_kernel_rc_h_disabled void krcReportXid_IMPL(struct OBJGPU *pGpu, struct KernelRc *pKernelRc, NvU32 exceptType, const char *pMsg); + #ifdef __nvoc_kernel_rc_h_disabled static inline void krcReportXid(struct OBJGPU *pGpu, struct KernelRc *pKernelRc, NvU32 exceptType, const char *pMsg) { NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); @@ -446,6 +448,7 @@ static inline void krcReportXid(struct OBJGPU *pGpu, struct KernelRc *pKernelRc, #endif //__nvoc_kernel_rc_h_disabled NvBool krcTestAllowAlloc_IMPL(struct OBJGPU *pGpu, struct KernelRc *pKernelRc, NvU32 failMask); + #ifdef __nvoc_kernel_rc_h_disabled static inline NvBool krcTestAllowAlloc(struct OBJGPU *pGpu, struct KernelRc *pKernelRc, NvU32 failMask) { NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); @@ -455,17 +458,19 @@ static inline NvBool krcTestAllowAlloc(struct OBJGPU *pGpu, struct KernelRc *pKe #define krcTestAllowAlloc(pGpu, pKernelRc, failMask) krcTestAllowAlloc_IMPL(pGpu, pKernelRc, failMask) #endif //__nvoc_kernel_rc_h_disabled -NvBool krcErrorInvokeCallback_IMPL(struct OBJGPU *pGpu, struct KernelRc *pKernelRc, struct KernelChannel *pKernelChannel, FIFO_MMU_EXCEPTION_DATA *pMmuExceptionData, NvU32 exceptType, NvU32 exceptLevel, NvU32 engineId, NvU32 rcDiagStart); +NvBool krcErrorInvokeCallback_IMPL(struct OBJGPU *pGpu, struct KernelRc *pKernelRc, struct KernelChannel *pKernelChannel, FIFO_MMU_EXCEPTION_DATA *pMmuExceptionData, NvU32 exceptType, NvU32 exceptLevel, RM_ENGINE_TYPE rmEngineType, NvU32 rcDiagStart); + #ifdef __nvoc_kernel_rc_h_disabled -static inline NvBool krcErrorInvokeCallback(struct OBJGPU *pGpu, struct KernelRc *pKernelRc, struct KernelChannel *pKernelChannel, FIFO_MMU_EXCEPTION_DATA *pMmuExceptionData, NvU32 exceptType, NvU32 exceptLevel, NvU32 engineId, NvU32 rcDiagStart) { +static inline NvBool krcErrorInvokeCallback(struct OBJGPU *pGpu, struct KernelRc *pKernelRc, struct KernelChannel *pKernelChannel, FIFO_MMU_EXCEPTION_DATA *pMmuExceptionData, NvU32 exceptType, NvU32 exceptLevel, RM_ENGINE_TYPE rmEngineType, NvU32 rcDiagStart) { NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); return NV_FALSE; } #else //__nvoc_kernel_rc_h_disabled -#define krcErrorInvokeCallback(pGpu, pKernelRc, pKernelChannel, pMmuExceptionData, exceptType, exceptLevel, engineId, rcDiagStart) krcErrorInvokeCallback_IMPL(pGpu, pKernelRc, pKernelChannel, pMmuExceptionData, exceptType, exceptLevel, engineId, rcDiagStart) +#define krcErrorInvokeCallback(pGpu, pKernelRc, pKernelChannel, pMmuExceptionData, exceptType, exceptLevel, rmEngineType, rcDiagStart) krcErrorInvokeCallback_IMPL(pGpu, pKernelRc, pKernelChannel, pMmuExceptionData, exceptType, exceptLevel, rmEngineType, rcDiagStart) #endif //__nvoc_kernel_rc_h_disabled NV_STATUS krcSubdeviceCtrlCmdRcGetErrorCount_IMPL(struct KernelRc *pKernelRc, struct Subdevice *pSubdevice, NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS *pParams); + #ifdef __nvoc_kernel_rc_h_disabled static inline NV_STATUS krcSubdeviceCtrlCmdRcGetErrorCount(struct KernelRc *pKernelRc, struct Subdevice *pSubdevice, NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS *pParams) { NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); @@ -476,6 +481,7 @@ static inline NV_STATUS krcSubdeviceCtrlCmdRcGetErrorCount(struct KernelRc *pKer #endif //__nvoc_kernel_rc_h_disabled NV_STATUS krcSubdeviceCtrlCmdRcGetErrorV2_IMPL(struct KernelRc *pKernelRc, struct Subdevice *pSubdevice, NV2080_CTRL_RC_GET_ERROR_V2_PARAMS *pParams); + #ifdef __nvoc_kernel_rc_h_disabled static inline NV_STATUS krcSubdeviceCtrlCmdRcGetErrorV2(struct KernelRc *pKernelRc, struct Subdevice *pSubdevice, NV2080_CTRL_RC_GET_ERROR_V2_PARAMS *pParams) { NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); @@ -486,6 +492,7 @@ static inline NV_STATUS krcSubdeviceCtrlCmdRcGetErrorV2(struct KernelRc *pKernel #endif //__nvoc_kernel_rc_h_disabled NV_STATUS krcWatchdogChangeState_IMPL(struct KernelRc *pKernelRc, struct Subdevice *pSubdevice, RC_CHANGE_WATCHDOG_STATE_OPERATION_TYPE operation); + #ifdef __nvoc_kernel_rc_h_disabled static inline NV_STATUS krcWatchdogChangeState(struct KernelRc *pKernelRc, struct Subdevice *pSubdevice, RC_CHANGE_WATCHDOG_STATE_OPERATION_TYPE operation) { NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); @@ -496,6 +503,7 @@ static inline NV_STATUS krcWatchdogChangeState(struct KernelRc *pKernelRc, struc #endif //__nvoc_kernel_rc_h_disabled void krcWatchdogEnable_IMPL(struct KernelRc *pKernelRc, NvBool bOverRide); + #ifdef __nvoc_kernel_rc_h_disabled static inline void krcWatchdogEnable(struct KernelRc *pKernelRc, NvBool bOverRide) { NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); @@ -505,6 +513,7 @@ static inline void krcWatchdogEnable(struct KernelRc *pKernelRc, NvBool bOverRid #endif //__nvoc_kernel_rc_h_disabled void krcWatchdogDisable_IMPL(struct KernelRc *pKernelRc); + #ifdef __nvoc_kernel_rc_h_disabled static inline void krcWatchdogDisable(struct KernelRc *pKernelRc) { NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); @@ -514,6 +523,7 @@ static inline void krcWatchdogDisable(struct KernelRc *pKernelRc) { #endif //__nvoc_kernel_rc_h_disabled NV_STATUS krcWatchdogShutdown_IMPL(struct OBJGPU *pGpu, struct KernelRc *pKernelRc); + #ifdef __nvoc_kernel_rc_h_disabled static inline NV_STATUS krcWatchdogShutdown(struct OBJGPU *pGpu, struct KernelRc *pKernelRc) { NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); @@ -524,6 +534,7 @@ static inline NV_STATUS krcWatchdogShutdown(struct OBJGPU *pGpu, struct KernelRc #endif //__nvoc_kernel_rc_h_disabled void krcWatchdogGetReservationCounts_IMPL(struct KernelRc *pKernelRc, NvS32 *pEnable, NvS32 *pDisable, NvS32 *pSoftDisable); + #ifdef __nvoc_kernel_rc_h_disabled static inline void krcWatchdogGetReservationCounts(struct KernelRc *pKernelRc, NvS32 *pEnable, NvS32 *pDisable, NvS32 *pSoftDisable) { NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); @@ -533,6 +544,7 @@ static inline void krcWatchdogGetReservationCounts(struct KernelRc *pKernelRc, N #endif //__nvoc_kernel_rc_h_disabled void krcWatchdogWriteNotifierToGpfifo_IMPL(struct OBJGPU *pGpu, struct KernelRc *pKernelRc); + #ifdef __nvoc_kernel_rc_h_disabled static inline void krcWatchdogWriteNotifierToGpfifo(struct OBJGPU *pGpu, struct KernelRc *pKernelRc) { NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); @@ -541,6 +553,16 @@ static inline void krcWatchdogWriteNotifierToGpfifo(struct OBJGPU *pGpu, struct #define krcWatchdogWriteNotifierToGpfifo(pGpu, pKernelRc) krcWatchdogWriteNotifierToGpfifo_IMPL(pGpu, pKernelRc) #endif //__nvoc_kernel_rc_h_disabled +void krcWatchdogCallbackVblankRecovery_IMPL(struct OBJGPU *pGpu, struct KernelRc *pKernelRc); + +#ifdef __nvoc_kernel_rc_h_disabled +static inline void krcWatchdogCallbackVblankRecovery(struct OBJGPU *pGpu, struct KernelRc *pKernelRc) { + NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); +} +#else //__nvoc_kernel_rc_h_disabled +#define krcWatchdogCallbackVblankRecovery(pGpu, pKernelRc) krcWatchdogCallbackVblankRecovery_IMPL(pGpu, pKernelRc) +#endif //__nvoc_kernel_rc_h_disabled + #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_kernel_sched_mgr_nvoc.h b/src/nvidia/generated/g_kernel_sched_mgr_nvoc.h index 2aef42b2c..fca873988 100644 --- a/src/nvidia/generated/g_kernel_sched_mgr_nvoc.h +++ b/src/nvidia/generated/g_kernel_sched_mgr_nvoc.h @@ -39,8 +39,6 @@ extern "C" { #ifndef _KERNELSCHEDMGR_H_ #define _KERNELSCHEDMGR_H_ -typedef enum __SCHED_POLICY SCHED_POLICY; - /* -------------------------------- Includes -------------------------------- */ #include "core/core.h" @@ -50,16 +48,8 @@ typedef enum __SCHED_POLICY SCHED_POLICY; /* ------------------------------- Datatypes --------------------------------*/ -enum __SCHED_POLICY -{ - SCHED_POLICY_DEFAULT = 0, - SCHED_POLICY_VGPU_RELATIVE, - SCHED_POLICY_PGPU_SHARE, - SCHED_POLICY_WDDM_COMPATIBILITY, - SCHED_POLICY_GFN_LSTT, - SCHED_POLICY_CHANNEL_INTERLEAVED, - SCHED_POLICY_CHANNEL_INTERLEAVED_WDDM, -}; +#define SCHED_POLICY_DEFAULT 0 +typedef NvU32 SCHED_POLICY; /*! * Class of scheduling manager for all the runlists. @@ -115,6 +105,7 @@ static inline NvU32 kschedmgrGetSchedPolicy(struct KernelSchedMgr *pKernelSchedM } void kschedmgrConstructPolicy_IMPL(struct KernelSchedMgr *pKernelSchedMgr, struct OBJGPU *pGpu); + #ifdef __nvoc_kernel_sched_mgr_h_disabled static inline void kschedmgrConstructPolicy(struct KernelSchedMgr *pKernelSchedMgr, struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("KernelSchedMgr was disabled!"); diff --git a/src/nvidia/generated/g_kernel_sec2_nvoc.c b/src/nvidia/generated/g_kernel_sec2_nvoc.c index 45019018d..fbd17dbba 100644 --- a/src/nvidia/generated/g_kernel_sec2_nvoc.c +++ b/src/nvidia/generated/g_kernel_sec2_nvoc.c @@ -191,11 +191,11 @@ void __nvoc_init_dataField_KernelSec2(KernelSec2 *pThis, RmHalspecOwner *pRmhals PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); } -NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* , RmHalspecOwner* ); +NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); NV_STATUS __nvoc_ctor_KernelFalcon(KernelFalcon* , RmHalspecOwner* ); NV_STATUS __nvoc_ctor_KernelSec2(KernelSec2 *pThis, RmHalspecOwner *pRmhalspecowner) { NV_STATUS status = NV_OK; - status = __nvoc_ctor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE, pRmhalspecowner); + status = __nvoc_ctor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); if (status != NV_OK) goto __nvoc_ctor_KernelSec2_fail_OBJENGSTATE; status = __nvoc_ctor_KernelFalcon(&pThis->__nvoc_base_KernelFalcon, pRmhalspecowner); if (status != NV_OK) goto __nvoc_ctor_KernelSec2_fail_KernelFalcon; @@ -227,9 +227,6 @@ static void __nvoc_init_funcTable_KernelSec2_1(KernelSec2 *pThis, RmHalspecOwner { pThis->__ksec2ConstructEngine__ = &ksec2ConstructEngine_IMPL; } - else if (0) - { - } // Hal function -- ksec2ConfigureFalcon if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ @@ -242,50 +239,41 @@ static void __nvoc_init_funcTable_KernelSec2_1(KernelSec2 *pThis, RmHalspecOwner { pThis->__ksec2ConfigureFalcon__ = &ksec2ConfigureFalcon_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__ksec2ConfigureFalcon__ = &ksec2ConfigureFalcon_GA102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__ksec2ConfigureFalcon__ = &ksec2ConfigureFalcon_f2d351; } } - else if (0) - { - } // Hal function -- ksec2ResetHw if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__ksec2ResetHw__ = &ksec2ResetHw_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__ksec2ResetHw__ = &ksec2ResetHw_5baef9; } } - else if (0) - { - } // Hal function -- ksec2IsEngineInReset if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__ksec2IsEngineInReset__ = &ksec2IsEngineInReset_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__ksec2IsEngineInReset__ = &ksec2IsEngineInReset_108313; } } - else if (0) - { - } // Hal function -- ksec2ReadUcodeFuseVersion if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ @@ -294,16 +282,10 @@ static void __nvoc_init_funcTable_KernelSec2_1(KernelSec2 *pThis, RmHalspecOwner { pThis->__ksec2ReadUcodeFuseVersion__ = &ksec2ReadUcodeFuseVersion_b2b553; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__ksec2ReadUcodeFuseVersion__ = &ksec2ReadUcodeFuseVersion_GA100; } - else if (0) - { - } - } - else if (0) - { } // Hal function -- ksec2GetBinArchiveBlUcode @@ -313,14 +295,11 @@ static void __nvoc_init_funcTable_KernelSec2_1(KernelSec2 *pThis, RmHalspecOwner { pThis->__ksec2GetBinArchiveBlUcode__ = &ksec2GetBinArchiveBlUcode_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08700000UL) )) /* ChipHal: AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__ksec2GetBinArchiveBlUcode__ = &ksec2GetBinArchiveBlUcode_80f438; } } - else if (0) - { - } // Hal function -- ksec2GetGenericBlUcode if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ @@ -329,14 +308,11 @@ static void __nvoc_init_funcTable_KernelSec2_1(KernelSec2 *pThis, RmHalspecOwner { pThis->__ksec2GetGenericBlUcode__ = &ksec2GetGenericBlUcode_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08700000UL) )) /* ChipHal: AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__ksec2GetGenericBlUcode__ = &ksec2GetGenericBlUcode_5baef9; } } - else if (0) - { - } pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelSec2_engstateConstructEngine; @@ -387,14 +363,14 @@ void __nvoc_init_funcTable_KernelSec2(KernelSec2 *pThis, RmHalspecOwner *pRmhals __nvoc_init_funcTable_KernelSec2_1(pThis, pRmhalspecowner); } -void __nvoc_init_OBJENGSTATE(OBJENGSTATE*, RmHalspecOwner* ); +void __nvoc_init_OBJENGSTATE(OBJENGSTATE*); void __nvoc_init_KernelFalcon(KernelFalcon*, RmHalspecOwner* ); void __nvoc_init_KernelSec2(KernelSec2 *pThis, RmHalspecOwner *pRmhalspecowner) { pThis->__nvoc_pbase_KernelSec2 = pThis; pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object; pThis->__nvoc_pbase_OBJENGSTATE = &pThis->__nvoc_base_OBJENGSTATE; pThis->__nvoc_pbase_KernelFalcon = &pThis->__nvoc_base_KernelFalcon; - __nvoc_init_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE, pRmhalspecowner); + __nvoc_init_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); __nvoc_init_KernelFalcon(&pThis->__nvoc_base_KernelFalcon, pRmhalspecowner); __nvoc_init_funcTable_KernelSec2(pThis, pRmhalspecowner); } diff --git a/src/nvidia/generated/g_kernel_sec2_nvoc.h b/src/nvidia/generated/g_kernel_sec2_nvoc.h index 19bff7b64..bfd97083d 100644 --- a/src/nvidia/generated/g_kernel_sec2_nvoc.h +++ b/src/nvidia/generated/g_kernel_sec2_nvoc.h @@ -152,10 +152,6 @@ NV_STATUS __nvoc_objCreate_KernelSec2(KernelSec2**, Dynamic*, NvU32); #define ksec2IsPresent(pGpu, pEngstate) ksec2IsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS ksec2ConstructEngine_IMPL(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, ENGDESCRIPTOR arg0); -static inline NV_STATUS ksec2ConstructEngine_395e98(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, ENGDESCRIPTOR arg0) { - return NV_ERR_NOT_SUPPORTED; -} - static inline NV_STATUS ksec2ConstructEngine_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, ENGDESCRIPTOR arg0) { return pKernelSec2->__ksec2ConstructEngine__(pGpu, pKernelSec2, arg0); } @@ -200,10 +196,6 @@ static inline NvU32 ksec2ReadUcodeFuseVersion_b2b553(struct OBJGPU *pGpu, struct NvU32 ksec2ReadUcodeFuseVersion_GA100(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, NvU32 ucodeId); -static inline NvU32 ksec2ReadUcodeFuseVersion_474d46(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, NvU32 ucodeId) { - NV_ASSERT_OR_RETURN_PRECOMP(0, 0); -} - static inline NvU32 ksec2ReadUcodeFuseVersion_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, NvU32 ucodeId) { return pKernelSec2->__ksec2ReadUcodeFuseVersion__(pGpu, pKernelSec2, ucodeId); } @@ -305,6 +297,7 @@ static inline NvBool ksec2IsPresent_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pE } void ksec2Destruct_IMPL(struct KernelSec2 *pKernelSec2); + #define __nvoc_ksec2Destruct(pKernelSec2) ksec2Destruct_IMPL(pKernelSec2) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.c b/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.c index baf2911d5..cf2094ce1 100644 --- a/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.c +++ b/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.c @@ -378,6 +378,10 @@ static void __nvoc_thunk_RsResource_ksmdbgssnPreDestruct(struct KernelSMDebugger resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelSMDebuggerSession_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_RsResource_ksmdbgssnIsDuplicate(struct KernelSMDebuggerSession *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelSMDebuggerSession_RsResource.offset), hMemory, pDuplicate); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_ksmdbgssnGetNotificationListPtr(struct KernelSMDebuggerSession *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelSMDebuggerSession_Notifier.offset)); } @@ -788,6 +792,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSM /*pClassInfo=*/ &(__nvoc_class_def_KernelSMDebuggerSession.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "ksmdbgssnCtrlCmdDebugWriteBatchMemory" +#endif + }, + { /* [26] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) ksmdbgssnCtrlCmdDebugReadMMUFaultInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x83de0328u, + /*paramSize=*/ sizeof(NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_KernelSMDebuggerSession.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "ksmdbgssnCtrlCmdDebugReadMMUFaultInfo" #endif }, @@ -795,7 +814,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSM const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelSMDebuggerSession = { - /*numEntries=*/ 26, + /*numEntries=*/ 27, /*pExportEntries=*/ __nvoc_exported_method_def_KernelSMDebuggerSession }; @@ -947,6 +966,10 @@ static void __nvoc_init_funcTable_KernelSMDebuggerSession_1(KernelSMDebuggerSess pThis->__ksmdbgssnCtrlCmdDebugWriteBatchMemory__ = &ksmdbgssnCtrlCmdDebugWriteBatchMemory_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__ksmdbgssnCtrlCmdDebugReadMMUFaultInfo__ = &ksmdbgssnCtrlCmdDebugReadMMUFaultInfo_IMPL; +#endif + pThis->__nvoc_base_GpuResource.__gpuresInternalControlForward__ = &__nvoc_thunk_KernelSMDebuggerSession_gpuresInternalControlForward; pThis->__nvoc_base_GpuResource.__gpuresGetInternalObjectHandle__ = &__nvoc_thunk_KernelSMDebuggerSession_gpuresGetInternalObjectHandle; @@ -993,6 +1016,8 @@ static void __nvoc_init_funcTable_KernelSMDebuggerSession_1(KernelSMDebuggerSess pThis->__ksmdbgssnPreDestruct__ = &__nvoc_thunk_RsResource_ksmdbgssnPreDestruct; + pThis->__ksmdbgssnIsDuplicate__ = &__nvoc_thunk_RsResource_ksmdbgssnIsDuplicate; + pThis->__ksmdbgssnGetNotificationListPtr__ = &__nvoc_thunk_Notifier_ksmdbgssnGetNotificationListPtr; pThis->__ksmdbgssnGetNotificationShare__ = &__nvoc_thunk_Notifier_ksmdbgssnGetNotificationShare; diff --git a/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.h b/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.h index 20367bad2..efa1bd3f7 100644 --- a/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.h +++ b/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.h @@ -35,10 +35,10 @@ extern "C" { #define KERNEL_SM_DEBUGGER_SESSION_H #include "gpu/gpu_halspec.h" -#include "utils/nv_enum.h" #include "gpu/gpu_resource.h" #include "rmapi/event.h" #include "rmapi/control.h" +#include "kernel/gpu/gr/kernel_sm_debugger_exception.h" #include "ctrl/ctrl83de.h" @@ -73,30 +73,6 @@ typedef struct KernelGraphicsObject KernelGraphicsObject; #define STOP_ON_ANYSM_MODE_ENABLED (0x00000001) #define STOP_ON_ANYSM_MODE_DISABLED (0x00000002) -#define SMDBG_EXCEPTION_TYPE_DEF(x) \ - NV_ENUM_ENTRY(x, SMDBG_EXCEPTION_TYPE_FATAL, 0) \ - NV_ENUM_ENTRY(x, SMDBG_EXCEPTION_TYPE_TRAP, 1) \ - NV_ENUM_ENTRY(x, SMDBG_EXCEPTION_TYPE_SINGLE_STEP, 2) \ - NV_ENUM_ENTRY(x, SMDBG_EXCEPTION_TYPE_INT, 3) \ - NV_ENUM_ENTRY(x, SMDBG_EXCEPTION_TYPE_CILP, 4) \ - NV_ENUM_ENTRY(x, SMDBG_EXCEPTION_TYPE_PREEMPTION_STARTED, 5) - -NV_ENUM_DEF(SMDBG_EXCEPTION_TYPE, SMDBG_EXCEPTION_TYPE_DEF); -ct_assert(NV_ENUM_IS_CONTIGUOUS(SMDBG_EXCEPTION_TYPE)); - -ct_assert(NVBIT32(SMDBG_EXCEPTION_TYPE_FATAL) == - NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_FATAL); -ct_assert(NVBIT32(SMDBG_EXCEPTION_TYPE_TRAP) == - NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_TRAP); -ct_assert(NVBIT32(SMDBG_EXCEPTION_TYPE_SINGLE_STEP) == - NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_SINGLE_STEP); -ct_assert(NVBIT32(SMDBG_EXCEPTION_TYPE_INT) == - NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_INT); -ct_assert(NVBIT32(SMDBG_EXCEPTION_TYPE_CILP) == - NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_CILP); -ct_assert(NVBIT32(SMDBG_EXCEPTION_TYPE_PREEMPTION_STARTED) == - NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PREEMPTION_STARTED); - // // Debugger Session object for automatically freeing and // invalidating the debugger object when underlying objects that it @@ -208,6 +184,7 @@ struct KernelSMDebuggerSession { NV_STATUS (*__ksmdbgssnCtrlCmdDebugGetSingleSmDebuggerStatus__)(struct KernelSMDebuggerSession *, NV83DE_CTRL_DEBUG_GET_SINGLE_SM_DEBUGGER_STATUS_PARAMS *); NV_STATUS (*__ksmdbgssnCtrlCmdDebugReadBatchMemory__)(struct KernelSMDebuggerSession *, NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS *); NV_STATUS (*__ksmdbgssnCtrlCmdDebugWriteBatchMemory__)(struct KernelSMDebuggerSession *, NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS *); + NV_STATUS (*__ksmdbgssnCtrlCmdDebugReadMMUFaultInfo__)(struct KernelSMDebuggerSession *, NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS *); NvBool (*__ksmdbgssnShareCallback__)(struct KernelSMDebuggerSession *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__ksmdbgssnMapTo__)(struct KernelSMDebuggerSession *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__ksmdbgssnGetOrAllocNotifShare__)(struct KernelSMDebuggerSession *, NvHandle, NvHandle, struct NotifShare **); @@ -229,6 +206,7 @@ struct KernelSMDebuggerSession { NV_STATUS (*__ksmdbgssnUnregisterEvent__)(struct KernelSMDebuggerSession *, NvHandle, NvHandle, NvHandle, NvHandle); NvBool (*__ksmdbgssnCanCopy__)(struct KernelSMDebuggerSession *); void (*__ksmdbgssnPreDestruct__)(struct KernelSMDebuggerSession *); + NV_STATUS (*__ksmdbgssnIsDuplicate__)(struct KernelSMDebuggerSession *, NvHandle, NvBool *); PEVENTNOTIFICATION *(*__ksmdbgssnGetNotificationListPtr__)(struct KernelSMDebuggerSession *); struct NotifShare *(*__ksmdbgssnGetNotificationShare__)(struct KernelSMDebuggerSession *); NV_STATUS (*__ksmdbgssnMap__)(struct KernelSMDebuggerSession *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -303,6 +281,7 @@ NV_STATUS __nvoc_objCreate_KernelSMDebuggerSession(KernelSMDebuggerSession**, Dy #define ksmdbgssnCtrlCmdDebugGetSingleSmDebuggerStatus(pKernelSMDebuggerSession, pParams) ksmdbgssnCtrlCmdDebugGetSingleSmDebuggerStatus_DISPATCH(pKernelSMDebuggerSession, pParams) #define ksmdbgssnCtrlCmdDebugReadBatchMemory(arg0, arg1) ksmdbgssnCtrlCmdDebugReadBatchMemory_DISPATCH(arg0, arg1) #define ksmdbgssnCtrlCmdDebugWriteBatchMemory(arg0, arg1) ksmdbgssnCtrlCmdDebugWriteBatchMemory_DISPATCH(arg0, arg1) +#define ksmdbgssnCtrlCmdDebugReadMMUFaultInfo(arg0, arg1) ksmdbgssnCtrlCmdDebugReadMMUFaultInfo_DISPATCH(arg0, arg1) #define ksmdbgssnShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) ksmdbgssnShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) #define ksmdbgssnMapTo(pResource, pParams) ksmdbgssnMapTo_DISPATCH(pResource, pParams) #define ksmdbgssnGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) ksmdbgssnGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) @@ -324,6 +303,7 @@ NV_STATUS __nvoc_objCreate_KernelSMDebuggerSession(KernelSMDebuggerSession**, Dy #define ksmdbgssnUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) ksmdbgssnUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define ksmdbgssnCanCopy(pResource) ksmdbgssnCanCopy_DISPATCH(pResource) #define ksmdbgssnPreDestruct(pResource) ksmdbgssnPreDestruct_DISPATCH(pResource) +#define ksmdbgssnIsDuplicate(pResource, hMemory, pDuplicate) ksmdbgssnIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define ksmdbgssnGetNotificationListPtr(pNotifier) ksmdbgssnGetNotificationListPtr_DISPATCH(pNotifier) #define ksmdbgssnGetNotificationShare(pNotifier) ksmdbgssnGetNotificationShare_DISPATCH(pNotifier) #define ksmdbgssnMap(pGpuResource, pCallContext, pParams, pCpuMapping) ksmdbgssnMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -528,6 +508,12 @@ static inline NV_STATUS ksmdbgssnCtrlCmdDebugWriteBatchMemory_DISPATCH(struct Ke return arg0->__ksmdbgssnCtrlCmdDebugWriteBatchMemory__(arg0, arg1); } +NV_STATUS ksmdbgssnCtrlCmdDebugReadMMUFaultInfo_IMPL(struct KernelSMDebuggerSession *arg0, NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS *arg1); + +static inline NV_STATUS ksmdbgssnCtrlCmdDebugReadMMUFaultInfo_DISPATCH(struct KernelSMDebuggerSession *arg0, NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS *arg1) { + return arg0->__ksmdbgssnCtrlCmdDebugReadMMUFaultInfo__(arg0, arg1); +} + static inline NvBool ksmdbgssnShareCallback_DISPATCH(struct KernelSMDebuggerSession *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pGpuResource->__ksmdbgssnShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } @@ -612,6 +598,10 @@ static inline void ksmdbgssnPreDestruct_DISPATCH(struct KernelSMDebuggerSession pResource->__ksmdbgssnPreDestruct__(pResource); } +static inline NV_STATUS ksmdbgssnIsDuplicate_DISPATCH(struct KernelSMDebuggerSession *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__ksmdbgssnIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline PEVENTNOTIFICATION *ksmdbgssnGetNotificationListPtr_DISPATCH(struct KernelSMDebuggerSession *pNotifier) { return pNotifier->__ksmdbgssnGetNotificationListPtr__(pNotifier); } @@ -629,10 +619,13 @@ static inline NvBool ksmdbgssnAccessCallback_DISPATCH(struct KernelSMDebuggerSes } NV_STATUS ksmdbgssnConstruct_IMPL(struct KernelSMDebuggerSession *arg_pKernelSMDebuggerSession, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_ksmdbgssnConstruct(arg_pKernelSMDebuggerSession, arg_pCallContext, arg_pParams) ksmdbgssnConstruct_IMPL(arg_pKernelSMDebuggerSession, arg_pCallContext, arg_pParams) void ksmdbgssnDestruct_IMPL(struct KernelSMDebuggerSession *arg0); + #define __nvoc_ksmdbgssnDestruct(arg0) ksmdbgssnDestruct_IMPL(arg0) void ksmdbgssnFreeCallback_IMPL(struct KernelSMDebuggerSession *arg0); + #ifdef __nvoc_kernel_sm_debugger_session_h_disabled static inline void ksmdbgssnFreeCallback(struct KernelSMDebuggerSession *arg0) { NV_ASSERT_FAILED_PRECOMP("KernelSMDebuggerSession was disabled!"); diff --git a/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.c b/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.c new file mode 100644 index 000000000..d312e7497 --- /dev/null +++ b/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.c @@ -0,0 +1,154 @@ +#define NVOC_KERNEL_VGPU_MGR_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_kernel_vgpu_mgr_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0xa793dd = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelVgpuMgr; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +void __nvoc_init_KernelVgpuMgr(KernelVgpuMgr*); +void __nvoc_init_funcTable_KernelVgpuMgr(KernelVgpuMgr*); +NV_STATUS __nvoc_ctor_KernelVgpuMgr(KernelVgpuMgr*); +void __nvoc_init_dataField_KernelVgpuMgr(KernelVgpuMgr*); +void __nvoc_dtor_KernelVgpuMgr(KernelVgpuMgr*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelVgpuMgr; + +static const struct NVOC_RTTI __nvoc_rtti_KernelVgpuMgr_KernelVgpuMgr = { + /*pClassDef=*/ &__nvoc_class_def_KernelVgpuMgr, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_KernelVgpuMgr, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_KernelVgpuMgr_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(KernelVgpuMgr, __nvoc_base_Object), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_KernelVgpuMgr = { + /*numRelatives=*/ 2, + /*relatives=*/ { + &__nvoc_rtti_KernelVgpuMgr_KernelVgpuMgr, + &__nvoc_rtti_KernelVgpuMgr_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_KernelVgpuMgr = +{ + /*classInfo=*/ { + /*size=*/ sizeof(KernelVgpuMgr), + /*classId=*/ classId(KernelVgpuMgr), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "KernelVgpuMgr", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_KernelVgpuMgr, + /*pCastInfo=*/ &__nvoc_castinfo_KernelVgpuMgr, + /*pExportInfo=*/ &__nvoc_export_info_KernelVgpuMgr +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelVgpuMgr = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_Object(Object*); +void __nvoc_dtor_KernelVgpuMgr(KernelVgpuMgr *pThis) { + __nvoc_kvgpumgrDestruct(pThis); + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_KernelVgpuMgr(KernelVgpuMgr *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_Object(Object* ); +NV_STATUS __nvoc_ctor_KernelVgpuMgr(KernelVgpuMgr *pThis) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_Object(&pThis->__nvoc_base_Object); + if (status != NV_OK) goto __nvoc_ctor_KernelVgpuMgr_fail_Object; + __nvoc_init_dataField_KernelVgpuMgr(pThis); + + status = __nvoc_kvgpumgrConstruct(pThis); + if (status != NV_OK) goto __nvoc_ctor_KernelVgpuMgr_fail__init; + goto __nvoc_ctor_KernelVgpuMgr_exit; // Success + +__nvoc_ctor_KernelVgpuMgr_fail__init: + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); +__nvoc_ctor_KernelVgpuMgr_fail_Object: +__nvoc_ctor_KernelVgpuMgr_exit: + + return status; +} + +static void __nvoc_init_funcTable_KernelVgpuMgr_1(KernelVgpuMgr *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_funcTable_KernelVgpuMgr(KernelVgpuMgr *pThis) { + __nvoc_init_funcTable_KernelVgpuMgr_1(pThis); +} + +void __nvoc_init_Object(Object*); +void __nvoc_init_KernelVgpuMgr(KernelVgpuMgr *pThis) { + pThis->__nvoc_pbase_KernelVgpuMgr = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Object; + __nvoc_init_Object(&pThis->__nvoc_base_Object); + __nvoc_init_funcTable_KernelVgpuMgr(pThis); +} + +NV_STATUS __nvoc_objCreate_KernelVgpuMgr(KernelVgpuMgr **ppThis, Dynamic *pParent, NvU32 createFlags) { + NV_STATUS status; + Object *pParentObj; + KernelVgpuMgr *pThis; + + pThis = portMemAllocNonPaged(sizeof(KernelVgpuMgr)); + if (pThis == NULL) return NV_ERR_NO_MEMORY; + + portMemSet(pThis, 0, sizeof(KernelVgpuMgr)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelVgpuMgr); + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_KernelVgpuMgr(pThis); + status = __nvoc_ctor_KernelVgpuMgr(pThis); + if (status != NV_OK) goto __nvoc_objCreate_KernelVgpuMgr_cleanup; + + *ppThis = pThis; + return NV_OK; + +__nvoc_objCreate_KernelVgpuMgr_cleanup: + // do not call destructors here since the constructor already called them + portMemFree(pThis); + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_KernelVgpuMgr(KernelVgpuMgr **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + + status = __nvoc_objCreate_KernelVgpuMgr(ppThis, pParent, createFlags); + + return status; +} + diff --git a/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.h b/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.h new file mode 100644 index 000000000..ae4c277f2 --- /dev/null +++ b/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.h @@ -0,0 +1,377 @@ +#ifndef _G_KERNEL_VGPU_MGR_NVOC_H_ +#define _G_KERNEL_VGPU_MGR_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_kernel_vgpu_mgr_nvoc.h" + +#ifndef __kernel_vgpu_mgr_h__ +#define __kernel_vgpu_mgr_h__ + +#include "ctrl/ctrl2080/ctrl2080vgpumgrinternal.h" +#include "ctrl/ctrla081.h" +#include "ctrl/ctrla084.h" + +#include "gpu/gpu.h" +#include "nv-hypervisor.h" +#include "nvlimits.h" +#include "core/core.h" +#include "resserv/resserv.h" +#include "nvoc/prelude.h" +#include "kernel/gpu/fifo/kernel_fifo.h" +#include "virtualization/common_vgpu_mgr.h" + +struct PhysMemSubAlloc; + +#ifndef __NVOC_CLASS_PhysMemSubAlloc_TYPEDEF__ +#define __NVOC_CLASS_PhysMemSubAlloc_TYPEDEF__ +typedef struct PhysMemSubAlloc PhysMemSubAlloc; +#endif /* __NVOC_CLASS_PhysMemSubAlloc_TYPEDEF__ */ + +#ifndef __nvoc_class_id_PhysMemSubAlloc +#define __nvoc_class_id_PhysMemSubAlloc 0x2351fc +#endif /* __nvoc_class_id_PhysMemSubAlloc */ + + +struct VgpuConfigApi; + +#ifndef __NVOC_CLASS_VgpuConfigApi_TYPEDEF__ +#define __NVOC_CLASS_VgpuConfigApi_TYPEDEF__ +typedef struct VgpuConfigApi VgpuConfigApi; +#endif /* __NVOC_CLASS_VgpuConfigApi_TYPEDEF__ */ + +#ifndef __nvoc_class_id_VgpuConfigApi +#define __nvoc_class_id_VgpuConfigApi 0x4d560a +#endif /* __nvoc_class_id_VgpuConfigApi */ + + + +/* vGPU events info lookup node*/ +typedef struct VGPU_EVENT_INFO_NODE +{ + NvHandle hClient; + NvHandle hVgpuConfig; + struct VgpuConfigApi *pVgpuConfigApi; +} VGPU_CONFIG_EVENT_INFO_NODE; + +MAKE_LIST(VGPU_CONFIG_EVENT_INFO_NODE_LIST, VGPU_CONFIG_EVENT_INFO_NODE); + +/* This structure represents vGPU guest's (VM's) information */ +typedef struct +{ + VM_ID_TYPE vmIdType; + VM_ID guestVmId; + NvU8 vmName[NVA081_VM_NAME_SIZE]; /* Used only on KVM */ +} KERNEL_GUEST_VM_INFO; + +/* This structure represents vgpu device's FB information + * which is visible to that guest. Here, 'offset' is offset + * from start of physical FB addresses in host FB space. + */ +typedef struct VGPU_DEVICE_GUEST_FB_INFO +{ + NvU64 offset; + NvU64 length; + NvBool bValid; +} VGPU_DEVICE_GUEST_FB_INFO; + +/* This structure represents guest vgpu device's (assigned to VM) information. + For VGPU-GSP, only KERNEL_HOST_VGPU_DEVICE is avaliable on kernel. */ +typedef struct KERNEL_HOST_VGPU_DEVICE +{ + NvU32 vgpuType; + NvHandle hClient; /*Internal RM client to dup smcPartition*/ + struct KERNEL_VGPU_GUEST *vgpuGuest; + NvU32 gfid; + NvU32 swizzId; + NvU32 numPluginChannels; + NvU32 chidOffset[RM_ENGINE_TYPE_LAST]; + NvU8 vgpuUuid[RM_SHA1_GID_SIZE]; + void *pVgpuVfioRef; + struct REQUEST_VGPU_INFO_NODE *pRequestVgpuInfoNode; + struct PhysMemSubAlloc *pPhysMemSubAlloc; + NvU32 gpuInstance; + struct HOST_VGPU_DEVICE *pHostVgpuDevice; + // Legacy fields + NvHandle hPluginFBAllocationClient; + VGPU_DEVICE_GUEST_FB_INFO vgpuDeviceGuestFbInfo; + NvU32 *pGuestFbSegment; + NvU32 guestFbSegmentPageSize; + NvBool bOfflinedPageInfoValid; + NvU32 offlinedPageCount; /* offlined page count */ + NvU64 offlinedPageGpa[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES]; +} KERNEL_HOST_VGPU_DEVICE; + +MAKE_LIST(KERNEL_HOST_VGPU_DEVICE_LIST, KERNEL_HOST_VGPU_DEVICE); + +/* vGPU guest definition */ +typedef struct KERNEL_VGPU_GUEST +{ + KERNEL_GUEST_VM_INFO guestVmInfo; // guest VM's information + NvU32 numVgpuDevices; +} KERNEL_VGPU_GUEST; + +MAKE_LIST(KERNEL_VGPU_GUEST_LIST, KERNEL_VGPU_GUEST); + +/* pGPU information */ +typedef struct +{ + NvU32 gpuPciId; + NvU32 supportedTypeIds[MAX_VGPU_TYPES_PER_PGPU]; + NvU32 numActiveVgpu; + NvU32 numVgpuTypes; + NvU32 vgpuConfigState; + KERNEL_HOST_VGPU_DEVICE_LIST listHostVgpuDeviceHead; + VGPU_TYPE *vgpuTypes[MAX_VGPU_TYPES_PER_PGPU]; + NvBool isAttached; + // Per VF per engine ChidOffset. Used for reserving guest channels per engine + NvU32 chidOffset[VGPU_MAX_GFID][RM_ENGINE_TYPE_LAST]; + VGPU_CONFIG_EVENT_INFO_NODE_LIST listVgpuConfigEventsHead; + NvBool sriovEnabled; + NvU32 numCreatedVgpu; // Used only on KVM + vgpu_vf_pci_info vfPciInfo[MAX_VF_COUNT_PER_GPU]; // Used only on KVM + NvU64 createdVfMask; // Used only on KVM + + /*! + * SwizzId Map. HW currently uses only 14 swizzIds. Every bit position + * in this mask represents swizzID and a "1" in bitMask states SwzzId + * in already assigned to a vGPU device. + */ + NvU64 assignedSwizzIdMask; + NvU32 fractionalMultiVgpu; +} KERNEL_PHYS_GPU_INFO; + +/* vGPU info received from mdev kernel module for KVM */ +typedef struct REQUEST_VGPU_INFO_NODE +{ + char configParams[VGPU_CONFIG_PARAMS_MAX_LENGTH]; + NvU8 mdevUuid[VGPU_UUID_SIZE]; + void *waitQueue; + NvU8 *vmName; + NvS32 *returnStatus; + NvU32 gpuPciId; + NvU32 qemuPid; + NvU16 vgpuId; + VGPU_DEVICE_STATE deviceState; + NvU32 gpuPciBdf; + NvU32 swizzId; + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice; +} REQUEST_VGPU_INFO_NODE; + +MAKE_LIST(REQUEST_VGPU_INFO_NODE_LIST, REQUEST_VGPU_INFO_NODE); + +#ifdef NVOC_KERNEL_VGPU_MGR_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct KernelVgpuMgr { + const struct NVOC_RTTI *__nvoc_rtti; + struct Object __nvoc_base_Object; + struct Object *__nvoc_pbase_Object; + struct KernelVgpuMgr *__nvoc_pbase_KernelVgpuMgr; + KERNEL_PHYS_GPU_INFO pgpuInfo[32]; + NvU32 pgpuCount; + VGPU_TYPE_LIST listVgpuTypeHead; + KERNEL_VGPU_GUEST_LIST listVgpuGuestHead; + NvU32 user_min_supported_version; + NvU32 user_max_supported_version; + struct OBJEHEAP *pHeap; + REQUEST_VGPU_INFO_NODE_LIST listRequestVgpuHead; + MEMORY_DESCRIPTOR *pGspPluginHeapMemDesc; +}; + +#ifndef __NVOC_CLASS_KernelVgpuMgr_TYPEDEF__ +#define __NVOC_CLASS_KernelVgpuMgr_TYPEDEF__ +typedef struct KernelVgpuMgr KernelVgpuMgr; +#endif /* __NVOC_CLASS_KernelVgpuMgr_TYPEDEF__ */ + +#ifndef __nvoc_class_id_KernelVgpuMgr +#define __nvoc_class_id_KernelVgpuMgr 0xa793dd +#endif /* __nvoc_class_id_KernelVgpuMgr */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelVgpuMgr; + +#define __staticCast_KernelVgpuMgr(pThis) \ + ((pThis)->__nvoc_pbase_KernelVgpuMgr) + +#ifdef __nvoc_kernel_vgpu_mgr_h_disabled +#define __dynamicCast_KernelVgpuMgr(pThis) ((KernelVgpuMgr*)NULL) +#else //__nvoc_kernel_vgpu_mgr_h_disabled +#define __dynamicCast_KernelVgpuMgr(pThis) \ + ((KernelVgpuMgr*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(KernelVgpuMgr))) +#endif //__nvoc_kernel_vgpu_mgr_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_KernelVgpuMgr(KernelVgpuMgr**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_KernelVgpuMgr(KernelVgpuMgr**, Dynamic*, NvU32); +#define __objCreate_KernelVgpuMgr(ppNewObj, pParent, createFlags) \ + __nvoc_objCreate_KernelVgpuMgr((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) + +NV_STATUS kvgpumgrConstruct_IMPL(struct KernelVgpuMgr *arg_pKernelVgpuMgr); + +#define __nvoc_kvgpumgrConstruct(arg_pKernelVgpuMgr) kvgpumgrConstruct_IMPL(arg_pKernelVgpuMgr) +void kvgpumgrDestruct_IMPL(struct KernelVgpuMgr *pKernelVgpuMgr); + +#define __nvoc_kvgpumgrDestruct(pKernelVgpuMgr) kvgpumgrDestruct_IMPL(pKernelVgpuMgr) +#undef PRIVATE_FIELD + + +NV_STATUS +kvgpumgrGetPgpuIndex(struct KernelVgpuMgr *pKernelVgpuMgr, NvU32 gpuPciId, NvU32* index); + +NV_STATUS +kvgpumgrGetVgpuTypeInfo(NvU32 vgpuTypeId, VGPU_TYPE **vgpuType); + +NV_STATUS +kvgpumgrPgpuAddVgpuType(struct OBJGPU *pGpu, NvBool discardVgpuTypes, NVA081_CTRL_VGPU_INFO *pVgpuInfo); + +NV_STATUS +kvgpumgrGetConfigEventInfoFromDb(NvHandle hClient, NvHandle hVgpuConfig, + VGPU_CONFIG_EVENT_INFO_NODE **ppVgpuConfigEventInfoNode, + NvU32 pgpuIndex); + +NV_STATUS +kvgpumgrAttachGpu(NvU32 gpuPciId); + +NV_STATUS +kvgpumgrDetachGpu(NvU32 gpuPciId); + +NV_STATUS +kvgpumgrRegisterGuestId(NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS *pParams, + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, struct OBJGPU *pGpu); + +NV_STATUS +kvgpumgrGuestRegister(struct OBJGPU *pGpu, + NvU32 gfid, + NvU32 vgpuType, + NvU32 vmPid, + VM_ID_TYPE vmIdType, + VM_ID guestVmId, + NvHandle hPluginFBAllocationClient, + NvU32 numChannels, + NvU32 numPluginChannels, + NvU32 swizzId, + NvU32 vgpuDeviceInstanceId, + NvBool bDisableDefaultSmcExecPartRestore, + KERNEL_HOST_VGPU_DEVICE **ppKernelHostVgpuDevice); + +NV_STATUS +kvgpumgrGuestUnregister(struct OBJGPU *pGpu, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice); + +NV_STATUS +kvgpumgrGetMaxInstanceOfVgpu(NvU32 vgpuTypeId, NvU32 *maxInstanceVgpu); + +NV_STATUS +kvgpumgrCheckVgpuTypeCreatable(KERNEL_PHYS_GPU_INFO *pPhysGpuInfo, VGPU_TYPE *vgpuTypeInfo); + +NV_STATUS +kvgpumgrEnumerateVgpuPerPgpu(struct OBJGPU *pGpu, NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS *pParams); + +NV_STATUS +kvgpumgrClearGuestVmInfo(struct OBJGPU *pGpu, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice); + +NV_STATUS +kvgpumgrGetSwizzId(struct OBJGPU *pGpu, + KERNEL_PHYS_GPU_INFO *pPhysGpuInfo, + NvU32 partitionFlag, + NvU32 *swizzId); + +NV_STATUS +kvgpumgrGetVgpuFbUsage(struct OBJGPU *pGpu, NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS *pParams); + +NV_STATUS +kvgpumgrSetVgpuEncoderCapacity(struct OBJGPU *pGpu, NvU8 *vgpuUuid, NvU32 encoderCapacity); + +NV_STATUS +kvgpumgrStart(const NvU8 *pMdevUuid, void *waitQueue, NvS32 *returnStatus, + NvU8 *vmName, NvU32 qemuPid); + +NV_STATUS +kvgpumgrCreateRequestVgpu(NvU32 gpuPciId, const NvU8 *pMdevUuid, + NvU32 vgpuTypeId, NvU16 *vgpuId, NvU32 gpuPciBdf); + +NV_STATUS +kvgpumgrDeleteRequestVgpu(const NvU8 *pMdevUuid, NvU16 vgpuId); + +NV_STATUS +kvgpumgrGetHostVgpuDeviceFromMdevUuid(NvU32 gpuPciId, const NvU8 *pMdevUuid, + KERNEL_HOST_VGPU_DEVICE **ppKernelHostVgpuDevice); + +NV_STATUS +kvgpumgrGetHostVgpuDeviceFromVmId(NvU32 gpuPciId, VM_ID guestVmId, + KERNEL_HOST_VGPU_DEVICE **ppKernelHostVgpuDevice, + VM_ID_TYPE vmIdType); + +NV_STATUS +kvgpumgrGetCreatableVgpuTypes(struct OBJGPU *pGpu, struct KernelVgpuMgr *pKernelVgpuMgr, NvU32 pgpuIndex, NvU32* numVgpuTypes, NvU32* vgpuTypes); + +NvU32 +kvgpumgrGetPgpuDevIdEncoding(struct OBJGPU *pGpu, NvU8 *pgpuString, NvU32 strSize); + +NvU32 +kvgpumgrGetPgpuSubdevIdEncoding(struct OBJGPU *pGpu, NvU8 *pgpuString, NvU32 strSize); + +NvU32 +kvgpumgrGetPgpuFSEncoding(struct OBJGPU *pGpu, NvU8 *pgpuString, NvU32 strSize); + +NvU32 +kvgpumgrGetPgpuCapEncoding(struct OBJGPU *pGpu, NvU8 *pgpuString, NvU32 strSize); + +NvBool +kvgpumgrCheckPgpuMigrationSupport(struct OBJGPU *pGpu); + +NV_STATUS +kvgpumgrGetHostVgpuVersion(NvU32 *user_min_supported_version, + NvU32 *user_max_supported_version); + +NV_STATUS +kvgpumgrSetHostVgpuVersion(NvU32 user_min_supported_version, + NvU32 user_max_supported_version); + +NV_STATUS +kvgpumgrGetPartitionFlag(NvU32 vgpuTypeId, + NvU32 *partitionFlag); + +NV_STATUS +kvgpumgrProcessVfInfo(NvU32 gpuPciId, NvU8 cmd, NvU32 domain, NvU32 bus, NvU32 slot, NvU32 function, NvBool isMdevAttached, vgpu_vf_pci_info *vf_info); + +NV_STATUS +kvgpumgrSendAllVgpuTypesToGsp(struct OBJGPU *pGpu); + +NvBool +kvgpumgrIsHeterogeneousVgpuSupported(void); + +#endif // __kernel_vgpu_mgr_h__ + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_KERNEL_VGPU_MGR_NVOC_H_ diff --git a/src/nvidia/generated/g_mem_desc_nvoc.h b/src/nvidia/generated/g_mem_desc_nvoc.h index 93536e7d2..69dabeb12 100644 --- a/src/nvidia/generated/g_mem_desc_nvoc.h +++ b/src/nvidia/generated/g_mem_desc_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -88,8 +88,8 @@ typedef NvU32 NV_ADDRESS_SPACE; #define ADDR_FBMEM 2 // Frame buffer memory space #define ADDR_REGMEM 3 // NV register memory space #define ADDR_VIRTUAL 4 // Virtual address space only -#define ADDR_FABRIC 5 // Fabric address space for the GPA based addressing. #define ADDR_FABRIC_V2 6 // Fabric address space for the FLA based addressing. Will replace ADDR_FABRIC. +#define ADDR_FABRIC_MC 8 // Multicast fabric address space (MCFLA) // // Address translation identifiers: @@ -162,6 +162,18 @@ typedef struct ADDRESS_TRANSLATION_ *ADDRESS_TRANSLATION; #define AT_VARIANT(x) ((struct ADDRESS_TRANSLATION_ *)x) #define AT_VALUE(x) ((NvU64)(NvUPtr)(x)) +// +// RM defined Memdesc surface names. The names are sent to Mods to enable feature verification. +// +#define NV_RM_SURF_NAME_INSTANCE_BLOCK "rm_instance_block_surface" +#define NV_RM_SURF_NAME_PAGE_TABLE "rm_page_table_surface" +#define NV_RM_SURF_NAME_NONREPLAYABLE_FAULT_BUFFER "rm_non_replayable_fault_buffer_surface" +#define NV_RM_SURF_NAME_REPLAYABLE_FAULT_BUFFER "rm_replayable_fault_buffer_surface" +#define NV_RM_SURF_NAME_CE_FAULT_METHOD_BUFFER "rm_ce_fault_method_buffer_surface" +#define NV_RM_SURF_NAME_ACCESS_COUNTER_BUFFER "rm_access_counter_buffer_surface" +#define NV_RM_SURF_NAME_VAB "rm_vab_surface" +#define NV_RM_SURF_NAME_GR_CIRCULAR_BUFFER "rm_gr_ctx_circular_buffer_surface" + // // Overrides address translation in SR-IOV enabled usecases // @@ -367,6 +379,13 @@ typedef struct MEMORY_DESCRIPTOR // We verified that memdesc is safe to be mapped as large pages NvBool bForceHugePages; + // Memory handle that libos 3+ returns for dynamically mapped sysmem + NvU32 libosRegionHandle; + NvU64 baseVirtualAddress; + + // Indicates granularity of mapping. Will be used to implement dynamic page sizes. + NvU32 pageArrayGranularity; + // // If PhysicallyContiguous is NV_TRUE, this array consists of one element. // If PhysicallyContiguous is NV_FALSE, this array is actually larger and has @@ -893,6 +912,25 @@ NV_STATUS memdescRegisterToGSP(OBJGPU *pGpu, NvHandle hClient, NvHandle hParent, NV_STATUS memdescDeregisterFromGSP(OBJGPU *pGpu, NvHandle hClient, NvHandle hParent, NvHandle hMemory); +/*! +* @brief Send memory descriptor from CPU-RM to GSP +* +* This function will create a MemoryList object with the MEMORY_DESCRIPTOR information on CPU-RM +* It will then use memdescRegisterToGSP API to create a corresponding MemoryList object on GSP-RM +* with the same Handle as that on CPU-RM +* +* This MemoryList object has the same MEMORY_DESCRIPTOR info as the input pMemDesc +* The CPU-RM handle can be sent to GSP-RM and then used on GSP end to retrieve the MemoryList object +* and then the corresponding MEMORY_DESCRIPTOR +* +* @param[in] pGpu OBJGPU pointer +* @param[in] pMemDesc MemDesc pointer +* @param[out] pHandle Pointer to handle of MemoryList object +* +* @returns NV_STATUS +*/ +NV_STATUS memdescSendMemDescToGSP(OBJGPU *pGpu, MEMORY_DESCRIPTOR *pMemDesc, NvHandle *pHandle); + // cache maintenance functions void memdescFlushGpuCaches(OBJGPU *pGpu, MEMORY_DESCRIPTOR *pMemDesc); void memdescFlushCpuCaches(OBJGPU *pGpu, MEMORY_DESCRIPTOR *pMemDesc); @@ -901,6 +939,15 @@ void memdescFlushCpuCaches(OBJGPU *pGpu, MEMORY_DESCRIPTOR *pMemDesc); void* memdescMapInternal(OBJGPU *pGpu, MEMORY_DESCRIPTOR *pMemDesc, NvU32 flags); void memdescUnmapInternal(OBJGPU *pGpu, MEMORY_DESCRIPTOR *pMemDesc, NvU32 flags); +/*! + * @brief Set the name of the surface. + * + * @param[in] pGpu OBJGPU pointer. + * @param[in] pMemDesc MEMORY_DESCRIPTOR pointer that the name is to be set for. + * @param[in] name const char pointer to the name to be set. + */ +void memdescSetName(OBJGPU*, MEMORY_DESCRIPTOR *pMemDesc, const char *name, const char *suffix); + // // External flags: // ALLOC_PER_SUBDEVICE Allocate independent system memory for each GPU @@ -1077,6 +1124,20 @@ void memdescUnmapInternal(OBJGPU *pGpu, MEMORY_DESCRIPTOR *pMemDesc, NvU32 flags // currently for this, so a WAR is required for r515. The intent // is to remove this by r525. // +#define MEMDESC_FLAGS_WSL_SHARED_MEMORY NVBIT64(46) + +// +// Skip IOMMU mapping creation during alloc for sysmem. +// A mapping might be requested later with custom parameters. +// +#define MEMDESC_FLAGS_SKIP_IOMMU_MAPPING NVBIT64(47) + +// +// Specical case to allocate the runlists for Guests from its GPA +// In MODS, VM's GPA allocated from subheap so using this define to +// Forcing memdesc to allocated from subheap +// +#define MEMDESC_FLAGS_FORCE_ALLOC_FROM_SUBHEAP NVBIT64(48) #endif // _MEMDESC_H_ diff --git a/src/nvidia/generated/g_mem_fabric_nvoc.c b/src/nvidia/generated/g_mem_fabric_nvoc.c index e5817964e..098cb3fee 100644 --- a/src/nvidia/generated/g_mem_fabric_nvoc.c +++ b/src/nvidia/generated/g_mem_fabric_nvoc.c @@ -145,8 +145,12 @@ static NV_STATUS __nvoc_thunk_RmResource_memoryfabricControl_Prologue(struct Mem return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_Memory_memoryfabricIsReady(struct MemoryFabric *pMemory) { - return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabric_Memory.offset)); +static NvBool __nvoc_thunk_Memory_memoryfabricIsGpuMapAllowed(struct MemoryFabric *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabric_Memory.offset), pGpu); +} + +static NV_STATUS __nvoc_thunk_Memory_memoryfabricIsReady(struct MemoryFabric *pMemory, NvBool bCopyConstructorContext) { + return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabric_Memory.offset), bCopyConstructorContext); } static NV_STATUS __nvoc_thunk_Memory_memoryfabricCheckCopyPermissions(struct MemoryFabric *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { @@ -157,6 +161,10 @@ static void __nvoc_thunk_RsResource_memoryfabricPreDestruct(struct MemoryFabric resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_Memory_memoryfabricIsDuplicate(struct MemoryFabric *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabric_Memory.offset), hMemory, pDuplicate); +} + static NV_STATUS __nvoc_thunk_RsResource_memoryfabricUnmapFrom(struct MemoryFabric *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RsResource.offset), pParams); } @@ -199,18 +207,48 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_MemoryFa #endif }, { /* [1] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2840u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2844u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) memoryfabricCtrlCmdDescribe_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2840u) - /*flags=*/ 0x2840u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2844u) + /*flags=*/ 0x2844u, /*accessRight=*/0x0u, /*methodId=*/ 0xf80102u, /*paramSize=*/ sizeof(NV00F8_CTRL_DESCRIBE_PARAMS), /*pClassInfo=*/ &(__nvoc_class_def_MemoryFabric.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "memoryfabricCtrlCmdDescribe" +#endif + }, + { /* [2] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8810u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) memoryfabricCtrlAttachMem_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8810u) + /*flags=*/ 0x8810u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xf80103u, + /*paramSize=*/ sizeof(NV00F8_CTRL_ATTACH_MEM_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_MemoryFabric.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "memoryfabricCtrlAttachMem" +#endif + }, + { /* [3] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8810u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) memoryfabricCtrlDetachMem_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8810u) + /*flags=*/ 0x8810u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xf80104u, + /*paramSize=*/ sizeof(NV00F8_CTRL_DETACH_MEM_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_MemoryFabric.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "memoryfabricCtrlDetachMem" #endif }, @@ -218,7 +256,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_MemoryFa const struct NVOC_EXPORT_INFO __nvoc_export_info_MemoryFabric = { - /*numEntries=*/ 2, + /*numEntries=*/ 4, /*pExportEntries=*/ __nvoc_exported_method_def_MemoryFabric }; @@ -265,10 +303,18 @@ static void __nvoc_init_funcTable_MemoryFabric_1(MemoryFabric *pThis) { pThis->__memoryfabricCtrlGetInfo__ = &memoryfabricCtrlGetInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2840u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2844u) pThis->__memoryfabricCtrlCmdDescribe__ = &memoryfabricCtrlCmdDescribe_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8810u) + pThis->__memoryfabricCtrlAttachMem__ = &memoryfabricCtrlAttachMem_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8810u) + pThis->__memoryfabricCtrlDetachMem__ = &memoryfabricCtrlDetachMem_IMPL; +#endif + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__resCanCopy__ = &__nvoc_thunk_MemoryFabric_resCanCopy; pThis->__nvoc_base_Memory.__memControl__ = &__nvoc_thunk_MemoryFabric_memControl; @@ -295,12 +341,16 @@ static void __nvoc_init_funcTable_MemoryFabric_1(MemoryFabric *pThis) { pThis->__memoryfabricControl_Prologue__ = &__nvoc_thunk_RmResource_memoryfabricControl_Prologue; + pThis->__memoryfabricIsGpuMapAllowed__ = &__nvoc_thunk_Memory_memoryfabricIsGpuMapAllowed; + pThis->__memoryfabricIsReady__ = &__nvoc_thunk_Memory_memoryfabricIsReady; pThis->__memoryfabricCheckCopyPermissions__ = &__nvoc_thunk_Memory_memoryfabricCheckCopyPermissions; pThis->__memoryfabricPreDestruct__ = &__nvoc_thunk_RsResource_memoryfabricPreDestruct; + pThis->__memoryfabricIsDuplicate__ = &__nvoc_thunk_Memory_memoryfabricIsDuplicate; + pThis->__memoryfabricUnmapFrom__ = &__nvoc_thunk_RsResource_memoryfabricUnmapFrom; pThis->__memoryfabricControl_Epilogue__ = &__nvoc_thunk_RmResource_memoryfabricControl_Epilogue; diff --git a/src/nvidia/generated/g_mem_fabric_nvoc.h b/src/nvidia/generated/g_mem_fabric_nvoc.h index 6807d38af..6736c9958 100644 --- a/src/nvidia/generated/g_mem_fabric_nvoc.h +++ b/src/nvidia/generated/g_mem_fabric_nvoc.h @@ -71,6 +71,8 @@ struct MemoryFabric { NV_STATUS (*__memoryfabricControl__)(struct MemoryFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memoryfabricCtrlGetInfo__)(struct MemoryFabric *, NV00F8_CTRL_GET_INFO_PARAMS *); NV_STATUS (*__memoryfabricCtrlCmdDescribe__)(struct MemoryFabric *, NV00F8_CTRL_DESCRIBE_PARAMS *); + NV_STATUS (*__memoryfabricCtrlAttachMem__)(struct MemoryFabric *, NV00F8_CTRL_ATTACH_MEM_PARAMS *); + NV_STATUS (*__memoryfabricCtrlDetachMem__)(struct MemoryFabric *, NV00F8_CTRL_DETACH_MEM_PARAMS *); NV_STATUS (*__memoryfabricCheckMemInterUnmap__)(struct MemoryFabric *, NvBool); NV_STATUS (*__memoryfabricUnmap__)(struct MemoryFabric *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__memoryfabricGetMemInterMapParams__)(struct MemoryFabric *, RMRES_MEM_INTER_MAP_PARAMS *); @@ -82,9 +84,11 @@ struct MemoryFabric { NvU32 (*__memoryfabricGetRefCount__)(struct MemoryFabric *); NV_STATUS (*__memoryfabricMapTo__)(struct MemoryFabric *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__memoryfabricControl_Prologue__)(struct MemoryFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__memoryfabricIsReady__)(struct MemoryFabric *); + NvBool (*__memoryfabricIsGpuMapAllowed__)(struct MemoryFabric *, struct OBJGPU *); + NV_STATUS (*__memoryfabricIsReady__)(struct MemoryFabric *, NvBool); NV_STATUS (*__memoryfabricCheckCopyPermissions__)(struct MemoryFabric *, struct OBJGPU *, NvHandle); void (*__memoryfabricPreDestruct__)(struct MemoryFabric *); + NV_STATUS (*__memoryfabricIsDuplicate__)(struct MemoryFabric *, NvHandle, NvBool *); NV_STATUS (*__memoryfabricUnmapFrom__)(struct MemoryFabric *, RS_RES_UNMAP_FROM_PARAMS *); void (*__memoryfabricControl_Epilogue__)(struct MemoryFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memoryfabricControlLookup__)(struct MemoryFabric *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); @@ -125,6 +129,8 @@ NV_STATUS __nvoc_objCreate_MemoryFabric(MemoryFabric**, Dynamic*, NvU32, CALL_CO #define memoryfabricControl(pMemoryFabric, pCallContext, pParams) memoryfabricControl_DISPATCH(pMemoryFabric, pCallContext, pParams) #define memoryfabricCtrlGetInfo(pMemoryFabric, pParams) memoryfabricCtrlGetInfo_DISPATCH(pMemoryFabric, pParams) #define memoryfabricCtrlCmdDescribe(pMemoryFabric, pParams) memoryfabricCtrlCmdDescribe_DISPATCH(pMemoryFabric, pParams) +#define memoryfabricCtrlAttachMem(pMemoryFabric, pParams) memoryfabricCtrlAttachMem_DISPATCH(pMemoryFabric, pParams) +#define memoryfabricCtrlDetachMem(pMemoryFabric, pParams) memoryfabricCtrlDetachMem_DISPATCH(pMemoryFabric, pParams) #define memoryfabricCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) memoryfabricCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) #define memoryfabricUnmap(pMemory, pCallContext, pCpuMapping) memoryfabricUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define memoryfabricGetMemInterMapParams(pMemory, pParams) memoryfabricGetMemInterMapParams_DISPATCH(pMemory, pParams) @@ -136,9 +142,11 @@ NV_STATUS __nvoc_objCreate_MemoryFabric(MemoryFabric**, Dynamic*, NvU32, CALL_CO #define memoryfabricGetRefCount(pResource) memoryfabricGetRefCount_DISPATCH(pResource) #define memoryfabricMapTo(pResource, pParams) memoryfabricMapTo_DISPATCH(pResource, pParams) #define memoryfabricControl_Prologue(pResource, pCallContext, pParams) memoryfabricControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define memoryfabricIsReady(pMemory) memoryfabricIsReady_DISPATCH(pMemory) +#define memoryfabricIsGpuMapAllowed(pMemory, pGpu) memoryfabricIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define memoryfabricIsReady(pMemory, bCopyConstructorContext) memoryfabricIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define memoryfabricCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) memoryfabricCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) #define memoryfabricPreDestruct(pResource) memoryfabricPreDestruct_DISPATCH(pResource) +#define memoryfabricIsDuplicate(pMemory, hMemory, pDuplicate) memoryfabricIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) #define memoryfabricUnmapFrom(pResource, pParams) memoryfabricUnmapFrom_DISPATCH(pResource, pParams) #define memoryfabricControl_Epilogue(pResource, pCallContext, pParams) memoryfabricControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define memoryfabricControlLookup(pResource, pParams, ppEntry) memoryfabricControlLookup_DISPATCH(pResource, pParams, ppEntry) @@ -174,6 +182,18 @@ static inline NV_STATUS memoryfabricCtrlCmdDescribe_DISPATCH(struct MemoryFabric return pMemoryFabric->__memoryfabricCtrlCmdDescribe__(pMemoryFabric, pParams); } +NV_STATUS memoryfabricCtrlAttachMem_IMPL(struct MemoryFabric *pMemoryFabric, NV00F8_CTRL_ATTACH_MEM_PARAMS *pParams); + +static inline NV_STATUS memoryfabricCtrlAttachMem_DISPATCH(struct MemoryFabric *pMemoryFabric, NV00F8_CTRL_ATTACH_MEM_PARAMS *pParams) { + return pMemoryFabric->__memoryfabricCtrlAttachMem__(pMemoryFabric, pParams); +} + +NV_STATUS memoryfabricCtrlDetachMem_IMPL(struct MemoryFabric *pMemoryFabric, NV00F8_CTRL_DETACH_MEM_PARAMS *pParams); + +static inline NV_STATUS memoryfabricCtrlDetachMem_DISPATCH(struct MemoryFabric *pMemoryFabric, NV00F8_CTRL_DETACH_MEM_PARAMS *pParams) { + return pMemoryFabric->__memoryfabricCtrlDetachMem__(pMemoryFabric, pParams); +} + static inline NV_STATUS memoryfabricCheckMemInterUnmap_DISPATCH(struct MemoryFabric *pMemory, NvBool bSubdeviceHandleProvided) { return pMemory->__memoryfabricCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } @@ -218,8 +238,12 @@ static inline NV_STATUS memoryfabricControl_Prologue_DISPATCH(struct MemoryFabri return pResource->__memoryfabricControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS memoryfabricIsReady_DISPATCH(struct MemoryFabric *pMemory) { - return pMemory->__memoryfabricIsReady__(pMemory); +static inline NvBool memoryfabricIsGpuMapAllowed_DISPATCH(struct MemoryFabric *pMemory, struct OBJGPU *pGpu) { + return pMemory->__memoryfabricIsGpuMapAllowed__(pMemory, pGpu); +} + +static inline NV_STATUS memoryfabricIsReady_DISPATCH(struct MemoryFabric *pMemory, NvBool bCopyConstructorContext) { + return pMemory->__memoryfabricIsReady__(pMemory, bCopyConstructorContext); } static inline NV_STATUS memoryfabricCheckCopyPermissions_DISPATCH(struct MemoryFabric *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { @@ -230,6 +254,10 @@ static inline void memoryfabricPreDestruct_DISPATCH(struct MemoryFabric *pResour pResource->__memoryfabricPreDestruct__(pResource); } +static inline NV_STATUS memoryfabricIsDuplicate_DISPATCH(struct MemoryFabric *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return pMemory->__memoryfabricIsDuplicate__(pMemory, hMemory, pDuplicate); +} + static inline NV_STATUS memoryfabricUnmapFrom_DISPATCH(struct MemoryFabric *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return pResource->__memoryfabricUnmapFrom__(pResource, pParams); } @@ -251,31 +279,28 @@ static inline NvBool memoryfabricAccessCallback_DISPATCH(struct MemoryFabric *pR } NV_STATUS memoryfabricConstruct_IMPL(struct MemoryFabric *arg_pMemoryFabric, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_memoryfabricConstruct(arg_pMemoryFabric, arg_pCallContext, arg_pParams) memoryfabricConstruct_IMPL(arg_pMemoryFabric, arg_pCallContext, arg_pParams) void memoryfabricDestruct_IMPL(struct MemoryFabric *pMemoryFabric); -#define __nvoc_memoryfabricDestruct(pMemoryFabric) memoryfabricDestruct_IMPL(pMemoryFabric) -NvBool memoryfabricCanExport_IMPL(struct MemoryFabric *pMemoryFabric); -#ifdef __nvoc_mem_fabric_h_disabled -static inline NvBool memoryfabricCanExport(struct MemoryFabric *pMemoryFabric) { - NV_ASSERT_FAILED_PRECOMP("MemoryFabric was disabled!"); - return NV_FALSE; -} -#else //__nvoc_mem_fabric_h_disabled -#define memoryfabricCanExport(pMemoryFabric) memoryfabricCanExport_IMPL(pMemoryFabric) -#endif //__nvoc_mem_fabric_h_disabled +#define __nvoc_memoryfabricDestruct(pMemoryFabric) memoryfabricDestruct_IMPL(pMemoryFabric) #undef PRIVATE_FIELD typedef struct { - // - // TODO: Only sticky non-partial mappings are supported currently, so all - // the fabric addrs are mapped to the single vidmem memory object. However, - // when partial mappings are supported, we will need a per-fabric memdesc - // tree to track the mappings for multiple vidmem memory objects. - // - NvHandle hDupedVidmem; + MEMORY_DESCRIPTOR *pPhysMemDesc; + NvU64 physMapLength; + NvHandle hDupedPhysMem; + NODE node; +} FABRIC_ATTCH_MEM_INFO_NODE; + +typedef struct +{ + // Tracks memory attached using NV00F8_CTRL_CMD_ATTACH_MEM + PNODE pAttachMemInfoTree; + + NvHandle hDupedPhysMem; NV_PHYSICAL_MEMORY_ATTRS physAttrs; diff --git a/src/nvidia/generated/g_mem_list_nvoc.c b/src/nvidia/generated/g_mem_list_nvoc.c new file mode 100644 index 000000000..1f701b0a3 --- /dev/null +++ b/src/nvidia/generated/g_mem_list_nvoc.c @@ -0,0 +1,335 @@ +#define NVOC_MEM_LIST_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_mem_list_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0x298f78 = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_MemoryList; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RsResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResourceCommon; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Memory; + +void __nvoc_init_MemoryList(MemoryList*); +void __nvoc_init_funcTable_MemoryList(MemoryList*); +NV_STATUS __nvoc_ctor_MemoryList(MemoryList*, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +void __nvoc_init_dataField_MemoryList(MemoryList*); +void __nvoc_dtor_MemoryList(MemoryList*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_MemoryList; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryList_MemoryList = { + /*pClassDef=*/ &__nvoc_class_def_MemoryList, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_MemoryList, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryList_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(MemoryList, __nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryList_RsResource = { + /*pClassDef=*/ &__nvoc_class_def_RsResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(MemoryList, __nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryList_RmResourceCommon = { + /*pClassDef=*/ &__nvoc_class_def_RmResourceCommon, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(MemoryList, __nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon), +}; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryList_RmResource = { + /*pClassDef=*/ &__nvoc_class_def_RmResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(MemoryList, __nvoc_base_Memory.__nvoc_base_RmResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryList_Memory = { + /*pClassDef=*/ &__nvoc_class_def_Memory, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(MemoryList, __nvoc_base_Memory), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_MemoryList = { + /*numRelatives=*/ 6, + /*relatives=*/ { + &__nvoc_rtti_MemoryList_MemoryList, + &__nvoc_rtti_MemoryList_Memory, + &__nvoc_rtti_MemoryList_RmResource, + &__nvoc_rtti_MemoryList_RmResourceCommon, + &__nvoc_rtti_MemoryList_RsResource, + &__nvoc_rtti_MemoryList_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_MemoryList = +{ + /*classInfo=*/ { + /*size=*/ sizeof(MemoryList), + /*classId=*/ classId(MemoryList), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "MemoryList", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_MemoryList, + /*pCastInfo=*/ &__nvoc_castinfo_MemoryList, + /*pExportInfo=*/ &__nvoc_export_info_MemoryList +}; + +static NvBool __nvoc_thunk_MemoryList_resCanCopy(struct RsResource *pMemoryList) { + return memlistCanCopy((struct MemoryList *)(((unsigned char *)pMemoryList) - __nvoc_rtti_MemoryList_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_Memory_memlistCheckMemInterUnmap(struct MemoryList *pMemory, NvBool bSubdeviceHandleProvided) { + return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_Memory_memlistControl(struct MemoryList *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_memlistUnmap(struct MemoryList *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_Memory_memlistGetMemInterMapParams(struct MemoryList *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_memlistGetMemoryMappingDescriptor(struct MemoryList *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_Memory_memlistGetMapAddrSpace(struct MemoryList *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvBool __nvoc_thunk_RmResource_memlistShareCallback(struct MemoryList *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RsResource_memlistControlFilter(struct MemoryList *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RsResource.offset), pCallContext, pParams); +} + +static void __nvoc_thunk_RsResource_memlistAddAdditionalDependants(struct RsClient *pClient, struct MemoryList *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RsResource.offset), pReference); +} + +static NvU32 __nvoc_thunk_RsResource_memlistGetRefCount(struct MemoryList *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_memlistMapTo(struct MemoryList *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_memlistControl_Prologue(struct MemoryList *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_Memory_memlistIsGpuMapAllowed(struct MemoryList *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), pGpu); +} + +static NV_STATUS __nvoc_thunk_Memory_memlistIsReady(struct MemoryList *pMemory, NvBool bCopyConstructorContext) { + return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), bCopyConstructorContext); +} + +static NV_STATUS __nvoc_thunk_Memory_memlistCheckCopyPermissions(struct MemoryList *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), pDstGpu, hDstClientNvBool); +} + +static void __nvoc_thunk_RsResource_memlistPreDestruct(struct MemoryList *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_Memory_memlistIsDuplicate(struct MemoryList *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), hMemory, pDuplicate); +} + +static NV_STATUS __nvoc_thunk_RsResource_memlistUnmapFrom(struct MemoryList *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_memlistControl_Epilogue(struct MemoryList *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_memlistControlLookup(struct MemoryList *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RsResource.offset), pParams, ppEntry); +} + +static NV_STATUS __nvoc_thunk_Memory_memlistMap(struct MemoryList *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { + return memMap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), pCallContext, pParams, pCpuMapping); +} + +static NvBool __nvoc_thunk_RmResource_memlistAccessCallback(struct MemoryList *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RmResource.offset), pInvokingClient, pAllocParams, accessRight); +} + +const struct NVOC_EXPORT_INFO __nvoc_export_info_MemoryList = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_Memory(Memory*); +void __nvoc_dtor_MemoryList(MemoryList *pThis) { + __nvoc_dtor_Memory(&pThis->__nvoc_base_Memory); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_MemoryList(MemoryList *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_Memory(Memory* , CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); +NV_STATUS __nvoc_ctor_MemoryList(MemoryList *pThis, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_Memory(&pThis->__nvoc_base_Memory, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_MemoryList_fail_Memory; + __nvoc_init_dataField_MemoryList(pThis); + + status = __nvoc_memlistConstruct(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_MemoryList_fail__init; + goto __nvoc_ctor_MemoryList_exit; // Success + +__nvoc_ctor_MemoryList_fail__init: + __nvoc_dtor_Memory(&pThis->__nvoc_base_Memory); +__nvoc_ctor_MemoryList_fail_Memory: +__nvoc_ctor_MemoryList_exit: + + return status; +} + +static void __nvoc_init_funcTable_MemoryList_1(MemoryList *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); + + pThis->__memlistCanCopy__ = &memlistCanCopy_IMPL; + + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__resCanCopy__ = &__nvoc_thunk_MemoryList_resCanCopy; + + pThis->__memlistCheckMemInterUnmap__ = &__nvoc_thunk_Memory_memlistCheckMemInterUnmap; + + pThis->__memlistControl__ = &__nvoc_thunk_Memory_memlistControl; + + pThis->__memlistUnmap__ = &__nvoc_thunk_Memory_memlistUnmap; + + pThis->__memlistGetMemInterMapParams__ = &__nvoc_thunk_Memory_memlistGetMemInterMapParams; + + pThis->__memlistGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_memlistGetMemoryMappingDescriptor; + + pThis->__memlistGetMapAddrSpace__ = &__nvoc_thunk_Memory_memlistGetMapAddrSpace; + + pThis->__memlistShareCallback__ = &__nvoc_thunk_RmResource_memlistShareCallback; + + pThis->__memlistControlFilter__ = &__nvoc_thunk_RsResource_memlistControlFilter; + + pThis->__memlistAddAdditionalDependants__ = &__nvoc_thunk_RsResource_memlistAddAdditionalDependants; + + pThis->__memlistGetRefCount__ = &__nvoc_thunk_RsResource_memlistGetRefCount; + + pThis->__memlistMapTo__ = &__nvoc_thunk_RsResource_memlistMapTo; + + pThis->__memlistControl_Prologue__ = &__nvoc_thunk_RmResource_memlistControl_Prologue; + + pThis->__memlistIsGpuMapAllowed__ = &__nvoc_thunk_Memory_memlistIsGpuMapAllowed; + + pThis->__memlistIsReady__ = &__nvoc_thunk_Memory_memlistIsReady; + + pThis->__memlistCheckCopyPermissions__ = &__nvoc_thunk_Memory_memlistCheckCopyPermissions; + + pThis->__memlistPreDestruct__ = &__nvoc_thunk_RsResource_memlistPreDestruct; + + pThis->__memlistIsDuplicate__ = &__nvoc_thunk_Memory_memlistIsDuplicate; + + pThis->__memlistUnmapFrom__ = &__nvoc_thunk_RsResource_memlistUnmapFrom; + + pThis->__memlistControl_Epilogue__ = &__nvoc_thunk_RmResource_memlistControl_Epilogue; + + pThis->__memlistControlLookup__ = &__nvoc_thunk_RsResource_memlistControlLookup; + + pThis->__memlistMap__ = &__nvoc_thunk_Memory_memlistMap; + + pThis->__memlistAccessCallback__ = &__nvoc_thunk_RmResource_memlistAccessCallback; +} + +void __nvoc_init_funcTable_MemoryList(MemoryList *pThis) { + __nvoc_init_funcTable_MemoryList_1(pThis); +} + +void __nvoc_init_Memory(Memory*); +void __nvoc_init_MemoryList(MemoryList *pThis) { + pThis->__nvoc_pbase_MemoryList = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; + pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource; + pThis->__nvoc_pbase_RmResourceCommon = &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon; + pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_Memory.__nvoc_base_RmResource; + pThis->__nvoc_pbase_Memory = &pThis->__nvoc_base_Memory; + __nvoc_init_Memory(&pThis->__nvoc_base_Memory); + __nvoc_init_funcTable_MemoryList(pThis); +} + +NV_STATUS __nvoc_objCreate_MemoryList(MemoryList **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status; + Object *pParentObj; + MemoryList *pThis; + + pThis = portMemAllocNonPaged(sizeof(MemoryList)); + if (pThis == NULL) return NV_ERR_NO_MEMORY; + + portMemSet(pThis, 0, sizeof(MemoryList)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MemoryList); + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_MemoryList(pThis); + status = __nvoc_ctor_MemoryList(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_objCreate_MemoryList_cleanup; + + *ppThis = pThis; + return NV_OK; + +__nvoc_objCreate_MemoryList_cleanup: + // do not call destructors here since the constructor already called them + portMemFree(pThis); + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_MemoryList(MemoryList **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + CALL_CONTEXT * arg_pCallContext = va_arg(args, CALL_CONTEXT *); + struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams = va_arg(args, struct RS_RES_ALLOC_PARAMS_INTERNAL *); + + status = __nvoc_objCreate_MemoryList(ppThis, pParent, createFlags, arg_pCallContext, arg_pParams); + + return status; +} + diff --git a/src/nvidia/generated/g_mem_list_nvoc.h b/src/nvidia/generated/g_mem_list_nvoc.h new file mode 100644 index 000000000..21d2bda25 --- /dev/null +++ b/src/nvidia/generated/g_mem_list_nvoc.h @@ -0,0 +1,238 @@ +#ifndef _G_MEM_LIST_NVOC_H_ +#define _G_MEM_LIST_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_mem_list_nvoc.h" + +#ifndef _MEMORY_LIST_H_ +#define _MEMORY_LIST_H_ + +#include "mem_mgr/mem.h" + +/*! + * These classes are used by the vGPU support to create memory objects for memory + * assigned to a guest VM. + */ +#ifdef NVOC_MEM_LIST_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct MemoryList { + const struct NVOC_RTTI *__nvoc_rtti; + struct Memory __nvoc_base_Memory; + struct Object *__nvoc_pbase_Object; + struct RsResource *__nvoc_pbase_RsResource; + struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; + struct RmResource *__nvoc_pbase_RmResource; + struct Memory *__nvoc_pbase_Memory; + struct MemoryList *__nvoc_pbase_MemoryList; + NvBool (*__memlistCanCopy__)(struct MemoryList *); + NV_STATUS (*__memlistCheckMemInterUnmap__)(struct MemoryList *, NvBool); + NV_STATUS (*__memlistControl__)(struct MemoryList *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memlistUnmap__)(struct MemoryList *, CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__memlistGetMemInterMapParams__)(struct MemoryList *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__memlistGetMemoryMappingDescriptor__)(struct MemoryList *, MEMORY_DESCRIPTOR **); + NV_STATUS (*__memlistGetMapAddrSpace__)(struct MemoryList *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvBool (*__memlistShareCallback__)(struct MemoryList *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__memlistControlFilter__)(struct MemoryList *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__memlistAddAdditionalDependants__)(struct RsClient *, struct MemoryList *, RsResourceRef *); + NvU32 (*__memlistGetRefCount__)(struct MemoryList *); + NV_STATUS (*__memlistMapTo__)(struct MemoryList *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__memlistControl_Prologue__)(struct MemoryList *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__memlistIsGpuMapAllowed__)(struct MemoryList *, struct OBJGPU *); + NV_STATUS (*__memlistIsReady__)(struct MemoryList *, NvBool); + NV_STATUS (*__memlistCheckCopyPermissions__)(struct MemoryList *, struct OBJGPU *, NvHandle); + void (*__memlistPreDestruct__)(struct MemoryList *); + NV_STATUS (*__memlistIsDuplicate__)(struct MemoryList *, NvHandle, NvBool *); + NV_STATUS (*__memlistUnmapFrom__)(struct MemoryList *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__memlistControl_Epilogue__)(struct MemoryList *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memlistControlLookup__)(struct MemoryList *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__memlistMap__)(struct MemoryList *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); + NvBool (*__memlistAccessCallback__)(struct MemoryList *, struct RsClient *, void *, RsAccessRight); +}; + +#ifndef __NVOC_CLASS_MemoryList_TYPEDEF__ +#define __NVOC_CLASS_MemoryList_TYPEDEF__ +typedef struct MemoryList MemoryList; +#endif /* __NVOC_CLASS_MemoryList_TYPEDEF__ */ + +#ifndef __nvoc_class_id_MemoryList +#define __nvoc_class_id_MemoryList 0x298f78 +#endif /* __nvoc_class_id_MemoryList */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_MemoryList; + +#define __staticCast_MemoryList(pThis) \ + ((pThis)->__nvoc_pbase_MemoryList) + +#ifdef __nvoc_mem_list_h_disabled +#define __dynamicCast_MemoryList(pThis) ((MemoryList*)NULL) +#else //__nvoc_mem_list_h_disabled +#define __dynamicCast_MemoryList(pThis) \ + ((MemoryList*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(MemoryList))) +#endif //__nvoc_mem_list_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_MemoryList(MemoryList**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_MemoryList(MemoryList**, Dynamic*, NvU32, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +#define __objCreate_MemoryList(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ + __nvoc_objCreate_MemoryList((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) + +#define memlistCanCopy(pMemoryList) memlistCanCopy_DISPATCH(pMemoryList) +#define memlistCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) memlistCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define memlistControl(pMemory, pCallContext, pParams) memlistControl_DISPATCH(pMemory, pCallContext, pParams) +#define memlistUnmap(pMemory, pCallContext, pCpuMapping) memlistUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) +#define memlistGetMemInterMapParams(pMemory, pParams) memlistGetMemInterMapParams_DISPATCH(pMemory, pParams) +#define memlistGetMemoryMappingDescriptor(pMemory, ppMemDesc) memlistGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) +#define memlistGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) memlistGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define memlistShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) memlistShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define memlistControlFilter(pResource, pCallContext, pParams) memlistControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define memlistAddAdditionalDependants(pClient, pResource, pReference) memlistAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define memlistGetRefCount(pResource) memlistGetRefCount_DISPATCH(pResource) +#define memlistMapTo(pResource, pParams) memlistMapTo_DISPATCH(pResource, pParams) +#define memlistControl_Prologue(pResource, pCallContext, pParams) memlistControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define memlistIsGpuMapAllowed(pMemory, pGpu) memlistIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define memlistIsReady(pMemory, bCopyConstructorContext) memlistIsReady_DISPATCH(pMemory, bCopyConstructorContext) +#define memlistCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) memlistCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define memlistPreDestruct(pResource) memlistPreDestruct_DISPATCH(pResource) +#define memlistIsDuplicate(pMemory, hMemory, pDuplicate) memlistIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) +#define memlistUnmapFrom(pResource, pParams) memlistUnmapFrom_DISPATCH(pResource, pParams) +#define memlistControl_Epilogue(pResource, pCallContext, pParams) memlistControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define memlistControlLookup(pResource, pParams, ppEntry) memlistControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define memlistMap(pMemory, pCallContext, pParams, pCpuMapping) memlistMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) +#define memlistAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) memlistAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +NvBool memlistCanCopy_IMPL(struct MemoryList *pMemoryList); + +static inline NvBool memlistCanCopy_DISPATCH(struct MemoryList *pMemoryList) { + return pMemoryList->__memlistCanCopy__(pMemoryList); +} + +static inline NV_STATUS memlistCheckMemInterUnmap_DISPATCH(struct MemoryList *pMemory, NvBool bSubdeviceHandleProvided) { + return pMemory->__memlistCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); +} + +static inline NV_STATUS memlistControl_DISPATCH(struct MemoryList *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pMemory->__memlistControl__(pMemory, pCallContext, pParams); +} + +static inline NV_STATUS memlistUnmap_DISPATCH(struct MemoryList *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pMemory->__memlistUnmap__(pMemory, pCallContext, pCpuMapping); +} + +static inline NV_STATUS memlistGetMemInterMapParams_DISPATCH(struct MemoryList *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pMemory->__memlistGetMemInterMapParams__(pMemory, pParams); +} + +static inline NV_STATUS memlistGetMemoryMappingDescriptor_DISPATCH(struct MemoryList *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return pMemory->__memlistGetMemoryMappingDescriptor__(pMemory, ppMemDesc); +} + +static inline NV_STATUS memlistGetMapAddrSpace_DISPATCH(struct MemoryList *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemory->__memlistGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvBool memlistShareCallback_DISPATCH(struct MemoryList *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__memlistShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS memlistControlFilter_DISPATCH(struct MemoryList *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memlistControlFilter__(pResource, pCallContext, pParams); +} + +static inline void memlistAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct MemoryList *pResource, RsResourceRef *pReference) { + pResource->__memlistAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NvU32 memlistGetRefCount_DISPATCH(struct MemoryList *pResource) { + return pResource->__memlistGetRefCount__(pResource); +} + +static inline NV_STATUS memlistMapTo_DISPATCH(struct MemoryList *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__memlistMapTo__(pResource, pParams); +} + +static inline NV_STATUS memlistControl_Prologue_DISPATCH(struct MemoryList *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memlistControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool memlistIsGpuMapAllowed_DISPATCH(struct MemoryList *pMemory, struct OBJGPU *pGpu) { + return pMemory->__memlistIsGpuMapAllowed__(pMemory, pGpu); +} + +static inline NV_STATUS memlistIsReady_DISPATCH(struct MemoryList *pMemory, NvBool bCopyConstructorContext) { + return pMemory->__memlistIsReady__(pMemory, bCopyConstructorContext); +} + +static inline NV_STATUS memlistCheckCopyPermissions_DISPATCH(struct MemoryList *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { + return pMemory->__memlistCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +} + +static inline void memlistPreDestruct_DISPATCH(struct MemoryList *pResource) { + pResource->__memlistPreDestruct__(pResource); +} + +static inline NV_STATUS memlistIsDuplicate_DISPATCH(struct MemoryList *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return pMemory->__memlistIsDuplicate__(pMemory, hMemory, pDuplicate); +} + +static inline NV_STATUS memlistUnmapFrom_DISPATCH(struct MemoryList *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__memlistUnmapFrom__(pResource, pParams); +} + +static inline void memlistControl_Epilogue_DISPATCH(struct MemoryList *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__memlistControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS memlistControlLookup_DISPATCH(struct MemoryList *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__memlistControlLookup__(pResource, pParams, ppEntry); +} + +static inline NV_STATUS memlistMap_DISPATCH(struct MemoryList *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { + return pMemory->__memlistMap__(pMemory, pCallContext, pParams, pCpuMapping); +} + +static inline NvBool memlistAccessCallback_DISPATCH(struct MemoryList *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return pResource->__memlistAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); +} + +NV_STATUS memlistConstruct_IMPL(struct MemoryList *arg_pMemoryList, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + +#define __nvoc_memlistConstruct(arg_pMemoryList, arg_pCallContext, arg_pParams) memlistConstruct_IMPL(arg_pMemoryList, arg_pCallContext, arg_pParams) +#undef PRIVATE_FIELD + + +#endif + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_MEM_LIST_NVOC_H_ diff --git a/src/nvidia/generated/g_mem_mapper_nvoc.c b/src/nvidia/generated/g_mem_mapper_nvoc.c new file mode 100644 index 000000000..a82079aa4 --- /dev/null +++ b/src/nvidia/generated/g_mem_mapper_nvoc.c @@ -0,0 +1,361 @@ +#define NVOC_MEM_MAPPER_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_mem_mapper_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0xb8e4a2 = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_MemoryMapper; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RsResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResourceCommon; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_GpuResource; + +void __nvoc_init_MemoryMapper(MemoryMapper*); +void __nvoc_init_funcTable_MemoryMapper(MemoryMapper*); +NV_STATUS __nvoc_ctor_MemoryMapper(MemoryMapper*, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +void __nvoc_init_dataField_MemoryMapper(MemoryMapper*); +void __nvoc_dtor_MemoryMapper(MemoryMapper*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_MemoryMapper; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryMapper_MemoryMapper = { + /*pClassDef=*/ &__nvoc_class_def_MemoryMapper, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_MemoryMapper, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryMapper_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(MemoryMapper, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryMapper_RsResource = { + /*pClassDef=*/ &__nvoc_class_def_RsResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(MemoryMapper, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryMapper_RmResourceCommon = { + /*pClassDef=*/ &__nvoc_class_def_RmResourceCommon, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(MemoryMapper, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon), +}; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryMapper_RmResource = { + /*pClassDef=*/ &__nvoc_class_def_RmResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(MemoryMapper, __nvoc_base_GpuResource.__nvoc_base_RmResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryMapper_GpuResource = { + /*pClassDef=*/ &__nvoc_class_def_GpuResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(MemoryMapper, __nvoc_base_GpuResource), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_MemoryMapper = { + /*numRelatives=*/ 6, + /*relatives=*/ { + &__nvoc_rtti_MemoryMapper_MemoryMapper, + &__nvoc_rtti_MemoryMapper_GpuResource, + &__nvoc_rtti_MemoryMapper_RmResource, + &__nvoc_rtti_MemoryMapper_RmResourceCommon, + &__nvoc_rtti_MemoryMapper_RsResource, + &__nvoc_rtti_MemoryMapper_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_MemoryMapper = +{ + /*classInfo=*/ { + /*size=*/ sizeof(MemoryMapper), + /*classId=*/ classId(MemoryMapper), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "MemoryMapper", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_MemoryMapper, + /*pCastInfo=*/ &__nvoc_castinfo_MemoryMapper, + /*pExportInfo=*/ &__nvoc_export_info_MemoryMapper +}; + +static NvBool __nvoc_thunk_GpuResource_memmapperShareCallback(struct MemoryMapper *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MemoryMapper_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_GpuResource_memmapperControl(struct MemoryMapper *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MemoryMapper_GpuResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_memmapperUnmap(struct MemoryMapper *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MemoryMapper_GpuResource.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_RmResource_memmapperGetMemInterMapParams(struct MemoryMapper *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_MemoryMapper_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_memmapperGetMemoryMappingDescriptor(struct MemoryMapper *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_MemoryMapper_RmResource.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_GpuResource_memmapperGetMapAddrSpace(struct MemoryMapper *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MemoryMapper_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvHandle __nvoc_thunk_GpuResource_memmapperGetInternalObjectHandle(struct MemoryMapper *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MemoryMapper_GpuResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_memmapperControlFilter(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset), pCallContext, pParams); +} + +static void __nvoc_thunk_RsResource_memmapperAddAdditionalDependants(struct RsClient *pClient, struct MemoryMapper *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset), pReference); +} + +static NvU32 __nvoc_thunk_RsResource_memmapperGetRefCount(struct MemoryMapper *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RmResource_memmapperCheckMemInterUnmap(struct MemoryMapper *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_MemoryMapper_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_memmapperMapTo(struct MemoryMapper *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_memmapperControl_Prologue(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_memmapperGetRegBaseOffsetAndSize(struct MemoryMapper *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MemoryMapper_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NvBool __nvoc_thunk_RsResource_memmapperCanCopy(struct MemoryMapper *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_memmapperInternalControlForward(struct MemoryMapper *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MemoryMapper_GpuResource.offset), command, pParams, size); +} + +static void __nvoc_thunk_RsResource_memmapperPreDestruct(struct MemoryMapper *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_memmapperUnmapFrom(struct MemoryMapper *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_memmapperIsDuplicate(struct MemoryMapper *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_memmapperControl_Epilogue(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_memmapperControlLookup(struct MemoryMapper *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset), pParams, ppEntry); +} + +static NV_STATUS __nvoc_thunk_GpuResource_memmapperMap(struct MemoryMapper *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { + return gpuresMap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MemoryMapper_GpuResource.offset), pCallContext, pParams, pCpuMapping); +} + +static NvBool __nvoc_thunk_RmResource_memmapperAccessCallback(struct MemoryMapper *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RmResource.offset), pInvokingClient, pAllocParams, accessRight); +} + +#if !defined(NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG) +#define NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(x) (0) +#endif + +static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_MemoryMapper[] = +{ + { /* [0] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) memmapperCtrlCmdSubmitPagingOperations_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xfe0002u, + /*paramSize=*/ sizeof(NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_MemoryMapper.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "memmapperCtrlCmdSubmitPagingOperations" +#endif + }, + +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_MemoryMapper = +{ + /*numEntries=*/ 1, + /*pExportEntries=*/ __nvoc_exported_method_def_MemoryMapper +}; + +void __nvoc_dtor_GpuResource(GpuResource*); +void __nvoc_dtor_MemoryMapper(MemoryMapper *pThis) { + __nvoc_dtor_GpuResource(&pThis->__nvoc_base_GpuResource); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_MemoryMapper(MemoryMapper *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_GpuResource(GpuResource* , struct CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); +NV_STATUS __nvoc_ctor_MemoryMapper(MemoryMapper *pThis, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_GpuResource(&pThis->__nvoc_base_GpuResource, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_MemoryMapper_fail_GpuResource; + __nvoc_init_dataField_MemoryMapper(pThis); + + status = __nvoc_memmapperConstruct(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_MemoryMapper_fail__init; + goto __nvoc_ctor_MemoryMapper_exit; // Success + +__nvoc_ctor_MemoryMapper_fail__init: + __nvoc_dtor_GpuResource(&pThis->__nvoc_base_GpuResource); +__nvoc_ctor_MemoryMapper_fail_GpuResource: +__nvoc_ctor_MemoryMapper_exit: + + return status; +} + +static void __nvoc_init_funcTable_MemoryMapper_1(MemoryMapper *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__memmapperCtrlCmdSubmitPagingOperations__ = &memmapperCtrlCmdSubmitPagingOperations_IMPL; +#endif + + pThis->__memmapperShareCallback__ = &__nvoc_thunk_GpuResource_memmapperShareCallback; + + pThis->__memmapperControl__ = &__nvoc_thunk_GpuResource_memmapperControl; + + pThis->__memmapperUnmap__ = &__nvoc_thunk_GpuResource_memmapperUnmap; + + pThis->__memmapperGetMemInterMapParams__ = &__nvoc_thunk_RmResource_memmapperGetMemInterMapParams; + + pThis->__memmapperGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_memmapperGetMemoryMappingDescriptor; + + pThis->__memmapperGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_memmapperGetMapAddrSpace; + + pThis->__memmapperGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_memmapperGetInternalObjectHandle; + + pThis->__memmapperControlFilter__ = &__nvoc_thunk_RsResource_memmapperControlFilter; + + pThis->__memmapperAddAdditionalDependants__ = &__nvoc_thunk_RsResource_memmapperAddAdditionalDependants; + + pThis->__memmapperGetRefCount__ = &__nvoc_thunk_RsResource_memmapperGetRefCount; + + pThis->__memmapperCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_memmapperCheckMemInterUnmap; + + pThis->__memmapperMapTo__ = &__nvoc_thunk_RsResource_memmapperMapTo; + + pThis->__memmapperControl_Prologue__ = &__nvoc_thunk_RmResource_memmapperControl_Prologue; + + pThis->__memmapperGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_memmapperGetRegBaseOffsetAndSize; + + pThis->__memmapperCanCopy__ = &__nvoc_thunk_RsResource_memmapperCanCopy; + + pThis->__memmapperInternalControlForward__ = &__nvoc_thunk_GpuResource_memmapperInternalControlForward; + + pThis->__memmapperPreDestruct__ = &__nvoc_thunk_RsResource_memmapperPreDestruct; + + pThis->__memmapperUnmapFrom__ = &__nvoc_thunk_RsResource_memmapperUnmapFrom; + + pThis->__memmapperIsDuplicate__ = &__nvoc_thunk_RsResource_memmapperIsDuplicate; + + pThis->__memmapperControl_Epilogue__ = &__nvoc_thunk_RmResource_memmapperControl_Epilogue; + + pThis->__memmapperControlLookup__ = &__nvoc_thunk_RsResource_memmapperControlLookup; + + pThis->__memmapperMap__ = &__nvoc_thunk_GpuResource_memmapperMap; + + pThis->__memmapperAccessCallback__ = &__nvoc_thunk_RmResource_memmapperAccessCallback; +} + +void __nvoc_init_funcTable_MemoryMapper(MemoryMapper *pThis) { + __nvoc_init_funcTable_MemoryMapper_1(pThis); +} + +void __nvoc_init_GpuResource(GpuResource*); +void __nvoc_init_MemoryMapper(MemoryMapper *pThis) { + pThis->__nvoc_pbase_MemoryMapper = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; + pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource; + pThis->__nvoc_pbase_RmResourceCommon = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon; + pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource; + pThis->__nvoc_pbase_GpuResource = &pThis->__nvoc_base_GpuResource; + __nvoc_init_GpuResource(&pThis->__nvoc_base_GpuResource); + __nvoc_init_funcTable_MemoryMapper(pThis); +} + +NV_STATUS __nvoc_objCreate_MemoryMapper(MemoryMapper **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status; + Object *pParentObj; + MemoryMapper *pThis; + + pThis = portMemAllocNonPaged(sizeof(MemoryMapper)); + if (pThis == NULL) return NV_ERR_NO_MEMORY; + + portMemSet(pThis, 0, sizeof(MemoryMapper)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MemoryMapper); + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_MemoryMapper(pThis); + status = __nvoc_ctor_MemoryMapper(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_objCreate_MemoryMapper_cleanup; + + *ppThis = pThis; + return NV_OK; + +__nvoc_objCreate_MemoryMapper_cleanup: + // do not call destructors here since the constructor already called them + portMemFree(pThis); + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_MemoryMapper(MemoryMapper **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + struct CALL_CONTEXT * arg_pCallContext = va_arg(args, struct CALL_CONTEXT *); + struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams = va_arg(args, struct RS_RES_ALLOC_PARAMS_INTERNAL *); + + status = __nvoc_objCreate_MemoryMapper(ppThis, pParent, createFlags, arg_pCallContext, arg_pParams); + + return status; +} + diff --git a/src/nvidia/generated/g_mem_mapper_nvoc.h b/src/nvidia/generated/g_mem_mapper_nvoc.h new file mode 100644 index 000000000..52e11e279 --- /dev/null +++ b/src/nvidia/generated/g_mem_mapper_nvoc.h @@ -0,0 +1,276 @@ +#ifndef _G_MEM_MAPPER_NVOC_H_ +#define _G_MEM_MAPPER_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_mem_mapper_nvoc.h" + +#ifndef MEMORY_MAPPER_H +#define MEMORY_MAPPER_H + +#include "core/core.h" +#include "rmapi/rmapi.h" +#include "rmapi/resource.h" +#include "gpu/gpu_resource.h" + +#include "class/cl00fe.h" +#include "ctrl/ctrl00fe.h" + +struct Subdevice; + +#ifndef __NVOC_CLASS_Subdevice_TYPEDEF__ +#define __NVOC_CLASS_Subdevice_TYPEDEF__ +typedef struct Subdevice Subdevice; +#endif /* __NVOC_CLASS_Subdevice_TYPEDEF__ */ + +#ifndef __nvoc_class_id_Subdevice +#define __nvoc_class_id_Subdevice 0x4b01b3 +#endif /* __nvoc_class_id_Subdevice */ + + +struct OBJGPU; + +#ifndef __NVOC_CLASS_OBJGPU_TYPEDEF__ +#define __NVOC_CLASS_OBJGPU_TYPEDEF__ +typedef struct OBJGPU OBJGPU; +#endif /* __NVOC_CLASS_OBJGPU_TYPEDEF__ */ + +#ifndef __nvoc_class_id_OBJGPU +#define __nvoc_class_id_OBJGPU 0x7ef3cb +#endif /* __nvoc_class_id_OBJGPU */ + + + +/*! + * MemoryMapper provides paging operations channel interface to userspace clients. + */ +#ifdef NVOC_MEM_MAPPER_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct MemoryMapper { + const struct NVOC_RTTI *__nvoc_rtti; + struct GpuResource __nvoc_base_GpuResource; + struct Object *__nvoc_pbase_Object; + struct RsResource *__nvoc_pbase_RsResource; + struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; + struct RmResource *__nvoc_pbase_RmResource; + struct GpuResource *__nvoc_pbase_GpuResource; + struct MemoryMapper *__nvoc_pbase_MemoryMapper; + NV_STATUS (*__memmapperCtrlCmdSubmitPagingOperations__)(struct MemoryMapper *, NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS *); + NvBool (*__memmapperShareCallback__)(struct MemoryMapper *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__memmapperControl__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memmapperUnmap__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__memmapperGetMemInterMapParams__)(struct MemoryMapper *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__memmapperGetMemoryMappingDescriptor__)(struct MemoryMapper *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__memmapperGetMapAddrSpace__)(struct MemoryMapper *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvHandle (*__memmapperGetInternalObjectHandle__)(struct MemoryMapper *); + NV_STATUS (*__memmapperControlFilter__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__memmapperAddAdditionalDependants__)(struct RsClient *, struct MemoryMapper *, RsResourceRef *); + NvU32 (*__memmapperGetRefCount__)(struct MemoryMapper *); + NV_STATUS (*__memmapperCheckMemInterUnmap__)(struct MemoryMapper *, NvBool); + NV_STATUS (*__memmapperMapTo__)(struct MemoryMapper *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__memmapperControl_Prologue__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memmapperGetRegBaseOffsetAndSize__)(struct MemoryMapper *, struct OBJGPU *, NvU32 *, NvU32 *); + NvBool (*__memmapperCanCopy__)(struct MemoryMapper *); + NV_STATUS (*__memmapperInternalControlForward__)(struct MemoryMapper *, NvU32, void *, NvU32); + void (*__memmapperPreDestruct__)(struct MemoryMapper *); + NV_STATUS (*__memmapperUnmapFrom__)(struct MemoryMapper *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__memmapperIsDuplicate__)(struct MemoryMapper *, NvHandle, NvBool *); + void (*__memmapperControl_Epilogue__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memmapperControlLookup__)(struct MemoryMapper *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__memmapperMap__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); + NvBool (*__memmapperAccessCallback__)(struct MemoryMapper *, struct RsClient *, void *, RsAccessRight); + struct Subdevice *pSubDevice; +}; + +#ifndef __NVOC_CLASS_MemoryMapper_TYPEDEF__ +#define __NVOC_CLASS_MemoryMapper_TYPEDEF__ +typedef struct MemoryMapper MemoryMapper; +#endif /* __NVOC_CLASS_MemoryMapper_TYPEDEF__ */ + +#ifndef __nvoc_class_id_MemoryMapper +#define __nvoc_class_id_MemoryMapper 0xb8e4a2 +#endif /* __nvoc_class_id_MemoryMapper */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_MemoryMapper; + +#define __staticCast_MemoryMapper(pThis) \ + ((pThis)->__nvoc_pbase_MemoryMapper) + +#ifdef __nvoc_mem_mapper_h_disabled +#define __dynamicCast_MemoryMapper(pThis) ((MemoryMapper*)NULL) +#else //__nvoc_mem_mapper_h_disabled +#define __dynamicCast_MemoryMapper(pThis) \ + ((MemoryMapper*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(MemoryMapper))) +#endif //__nvoc_mem_mapper_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_MemoryMapper(MemoryMapper**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_MemoryMapper(MemoryMapper**, Dynamic*, NvU32, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +#define __objCreate_MemoryMapper(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ + __nvoc_objCreate_MemoryMapper((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) + +#define memmapperCtrlCmdSubmitPagingOperations(pMemoryMapper, pParams) memmapperCtrlCmdSubmitPagingOperations_DISPATCH(pMemoryMapper, pParams) +#define memmapperShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) memmapperShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define memmapperControl(pGpuResource, pCallContext, pParams) memmapperControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define memmapperUnmap(pGpuResource, pCallContext, pCpuMapping) memmapperUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define memmapperGetMemInterMapParams(pRmResource, pParams) memmapperGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define memmapperGetMemoryMappingDescriptor(pRmResource, ppMemDesc) memmapperGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define memmapperGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) memmapperGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define memmapperGetInternalObjectHandle(pGpuResource) memmapperGetInternalObjectHandle_DISPATCH(pGpuResource) +#define memmapperControlFilter(pResource, pCallContext, pParams) memmapperControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define memmapperAddAdditionalDependants(pClient, pResource, pReference) memmapperAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define memmapperGetRefCount(pResource) memmapperGetRefCount_DISPATCH(pResource) +#define memmapperCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) memmapperCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define memmapperMapTo(pResource, pParams) memmapperMapTo_DISPATCH(pResource, pParams) +#define memmapperControl_Prologue(pResource, pCallContext, pParams) memmapperControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define memmapperGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) memmapperGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define memmapperCanCopy(pResource) memmapperCanCopy_DISPATCH(pResource) +#define memmapperInternalControlForward(pGpuResource, command, pParams, size) memmapperInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define memmapperPreDestruct(pResource) memmapperPreDestruct_DISPATCH(pResource) +#define memmapperUnmapFrom(pResource, pParams) memmapperUnmapFrom_DISPATCH(pResource, pParams) +#define memmapperIsDuplicate(pResource, hMemory, pDuplicate) memmapperIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define memmapperControl_Epilogue(pResource, pCallContext, pParams) memmapperControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define memmapperControlLookup(pResource, pParams, ppEntry) memmapperControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define memmapperMap(pGpuResource, pCallContext, pParams, pCpuMapping) memmapperMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) +#define memmapperAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) memmapperAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +NV_STATUS memmapperCtrlCmdSubmitPagingOperations_IMPL(struct MemoryMapper *pMemoryMapper, NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS *pParams); + +static inline NV_STATUS memmapperCtrlCmdSubmitPagingOperations_DISPATCH(struct MemoryMapper *pMemoryMapper, NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS *pParams) { + return pMemoryMapper->__memmapperCtrlCmdSubmitPagingOperations__(pMemoryMapper, pParams); +} + +static inline NvBool memmapperShareCallback_DISPATCH(struct MemoryMapper *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pGpuResource->__memmapperShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS memmapperControl_DISPATCH(struct MemoryMapper *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__memmapperControl__(pGpuResource, pCallContext, pParams); +} + +static inline NV_STATUS memmapperUnmap_DISPATCH(struct MemoryMapper *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__memmapperUnmap__(pGpuResource, pCallContext, pCpuMapping); +} + +static inline NV_STATUS memmapperGetMemInterMapParams_DISPATCH(struct MemoryMapper *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__memmapperGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS memmapperGetMemoryMappingDescriptor_DISPATCH(struct MemoryMapper *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__memmapperGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +} + +static inline NV_STATUS memmapperGetMapAddrSpace_DISPATCH(struct MemoryMapper *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__memmapperGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvHandle memmapperGetInternalObjectHandle_DISPATCH(struct MemoryMapper *pGpuResource) { + return pGpuResource->__memmapperGetInternalObjectHandle__(pGpuResource); +} + +static inline NV_STATUS memmapperControlFilter_DISPATCH(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memmapperControlFilter__(pResource, pCallContext, pParams); +} + +static inline void memmapperAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct MemoryMapper *pResource, RsResourceRef *pReference) { + pResource->__memmapperAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NvU32 memmapperGetRefCount_DISPATCH(struct MemoryMapper *pResource) { + return pResource->__memmapperGetRefCount__(pResource); +} + +static inline NV_STATUS memmapperCheckMemInterUnmap_DISPATCH(struct MemoryMapper *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__memmapperCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS memmapperMapTo_DISPATCH(struct MemoryMapper *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__memmapperMapTo__(pResource, pParams); +} + +static inline NV_STATUS memmapperControl_Prologue_DISPATCH(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memmapperControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS memmapperGetRegBaseOffsetAndSize_DISPATCH(struct MemoryMapper *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__memmapperGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NvBool memmapperCanCopy_DISPATCH(struct MemoryMapper *pResource) { + return pResource->__memmapperCanCopy__(pResource); +} + +static inline NV_STATUS memmapperInternalControlForward_DISPATCH(struct MemoryMapper *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__memmapperInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline void memmapperPreDestruct_DISPATCH(struct MemoryMapper *pResource) { + pResource->__memmapperPreDestruct__(pResource); +} + +static inline NV_STATUS memmapperUnmapFrom_DISPATCH(struct MemoryMapper *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__memmapperUnmapFrom__(pResource, pParams); +} + +static inline NV_STATUS memmapperIsDuplicate_DISPATCH(struct MemoryMapper *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__memmapperIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void memmapperControl_Epilogue_DISPATCH(struct MemoryMapper *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__memmapperControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS memmapperControlLookup_DISPATCH(struct MemoryMapper *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__memmapperControlLookup__(pResource, pParams, ppEntry); +} + +static inline NV_STATUS memmapperMap_DISPATCH(struct MemoryMapper *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__memmapperMap__(pGpuResource, pCallContext, pParams, pCpuMapping); +} + +static inline NvBool memmapperAccessCallback_DISPATCH(struct MemoryMapper *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return pResource->__memmapperAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); +} + +NV_STATUS memmapperConstruct_IMPL(struct MemoryMapper *arg_pMemoryMapper, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + +#define __nvoc_memmapperConstruct(arg_pMemoryMapper, arg_pCallContext, arg_pParams) memmapperConstruct_IMPL(arg_pMemoryMapper, arg_pCallContext, arg_pParams) +#undef PRIVATE_FIELD + + +#endif // MEMORY_MAPPER_H + + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_MEM_MAPPER_NVOC_H_ diff --git a/src/nvidia/generated/g_mem_mgr_nvoc.c b/src/nvidia/generated/g_mem_mgr_nvoc.c index 38be567d1..889a1e4e7 100644 --- a/src/nvidia/generated/g_mem_mgr_nvoc.c +++ b/src/nvidia/generated/g_mem_mgr_nvoc.c @@ -172,74 +172,43 @@ void __nvoc_init_dataField_MemoryManager(MemoryManager *pThis, RmHalspecOwner *p PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // Hal field -- bFbRegionsSupported - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->bFbRegionsSupported = ((NvBool)(0 == 0)); } - // default - else - { - pThis->bFbRegionsSupported = ((NvBool)(0 != 0)); - } // Hal field -- bPmaEnabled - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->bPmaEnabled = ((NvBool)(0 == 0)); } - // default - else - { - pThis->bPmaEnabled = ((NvBool)(0 != 0)); - } // Hal field -- bClientPageTablesPmaManaged - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->bClientPageTablesPmaManaged = ((NvBool)(0 == 0)); } - // default - else - { - pThis->bClientPageTablesPmaManaged = ((NvBool)(0 != 0)); - } // Hal field -- bScanoutSysmem - if (0) - { - } // default - else { pThis->bScanoutSysmem = ((NvBool)(0 != 0)); } // Hal field -- bDisallowSplitLowerMemory - if (0) - { - } // default - else { pThis->bDisallowSplitLowerMemory = ((NvBool)(0 != 0)); } // Hal field -- bSmallPageCompression - if (0) - { - } // default - else { pThis->bSmallPageCompression = ((NvBool)(0 != 0)); } // Hal field -- bSysmemCompressionSupportDef - if (0) - { - } // default - else { pThis->bSysmemCompressionSupportDef = ((NvBool)(0 != 0)); } @@ -255,21 +224,10 @@ void __nvoc_init_dataField_MemoryManager(MemoryManager *pThis, RmHalspecOwner *p pThis->bBug2301372IncreaseRmReserveMemoryWar = ((NvBool)(0 != 0)); } - // Hal field -- bBug3620359IncreaseRmReserveMemoryWar - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00700000UL) )) /* ChipHal: AD102 | AD103 | AD104 */ - { - pThis->bBug3620359IncreaseRmReserveMemoryWar = ((NvBool)(0 == 0)); - } - // default - else - { - pThis->bBug3620359IncreaseRmReserveMemoryWar = ((NvBool)(0 != 0)); - } - pThis->bEnableDynamicPageOfflining = ((NvBool)(0 != 0)); // Hal field -- bVgpuPmaSupport - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->bVgpuPmaSupport = ((NvBool)(0 == 0)); } @@ -279,30 +237,22 @@ void __nvoc_init_dataField_MemoryManager(MemoryManager *pThis, RmHalspecOwner *p pThis->bVgpuPmaSupport = ((NvBool)(0 != 0)); } + pThis->bEnableDynamicGranularityPageArrays = ((NvBool)(0 != 0)); + // Hal field -- bAllowNoncontiguousAllocation - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->bAllowNoncontiguousAllocation = ((NvBool)(0 == 0)); } - // default - else - { - pThis->bAllowNoncontiguousAllocation = ((NvBool)(0 != 0)); - } // Hal field -- bScrubOnFreeEnabled - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->bScrubOnFreeEnabled = ((NvBool)(0 == 0)); } - // default - else - { - pThis->bScrubOnFreeEnabled = ((NvBool)(0 != 0)); - } // Hal field -- bFastScrubberEnabled - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->bFastScrubberEnabled = ((NvBool)(0 == 0)); } @@ -354,11 +304,11 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe pThis->__memmgrStateDestroy__ = &memmgrStateDestroy_IMPL; // Hal function -- memmgrMemUtilsCheckMemoryFastScrubEnable - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__memmgrMemUtilsCheckMemoryFastScrubEnable__ = &memmgrMemUtilsCheckMemoryFastScrubEnable_GH100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__memmgrMemUtilsCheckMemoryFastScrubEnable__ = &memmgrMemUtilsCheckMemoryFastScrubEnable_491d52; } @@ -368,97 +318,67 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe { pThis->__memmgrAllocDetermineAlignment__ = &memmgrAllocDetermineAlignment_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__memmgrAllocDetermineAlignment__ = &memmgrAllocDetermineAlignment_GA100; } - else if (0) - { - } - else if (0) - { - } // Hal function -- memmgrGetMaxContextSize - if (0) - { - } - else if (0) - { - } - else if (0) - { - } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__memmgrGetMaxContextSize__ = &memmgrGetMaxContextSize_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0800fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x1000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | GH100 */ { pThis->__memmgrGetMaxContextSize__ = &memmgrGetMaxContextSize_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00700000UL) )) /* ChipHal: AD102 | AD103 | AD104 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__memmgrGetMaxContextSize__ = &memmgrGetMaxContextSize_AD102; } - else if (0) - { - } // Hal function -- memmgrScrubRegistryOverrides if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__memmgrScrubRegistryOverrides__ = &memmgrScrubRegistryOverrides_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__memmgrScrubRegistryOverrides__ = &memmgrScrubRegistryOverrides_GA100; } - else if (0) - { - } // Hal function -- memmgrGetPteKindBl - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__memmgrGetPteKindBl__ = &memmgrGetPteKindBl_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__memmgrGetPteKindBl__ = &memmgrGetPteKindBl_474d46; } // Hal function -- memmgrGetPteKindPitch - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__memmgrGetPteKindPitch__ = &memmgrGetPteKindPitch_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__memmgrGetPteKindPitch__ = &memmgrGetPteKindPitch_474d46; } // Hal function -- memmgrChooseKindCompressC - if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__memmgrChooseKindCompressC__ = &memmgrChooseKindCompressC_GP100; } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__memmgrChooseKindCompressC__ = &memmgrChooseKindCompressC_474d46; } // Hal function -- memmgrGetFlaKind - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__memmgrGetFlaKind__ = &memmgrGetFlaKind_GA100; } @@ -472,7 +392,7 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe { pThis->__memmgrDetermineComptag__ = &memmgrDetermineComptag_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__memmgrDetermineComptag__ = &memmgrDetermineComptag_13cd8d; } @@ -493,7 +413,7 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe { pThis->__memmgrReadMmuLock__ = &memmgrReadMmuLock_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__memmgrReadMmuLock__ = &memmgrReadMmuLock_e133c0; } @@ -503,7 +423,7 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe { pThis->__memmgrBlockMemLockedMemory__ = &memmgrBlockMemLockedMemory_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__memmgrBlockMemLockedMemory__ = &memmgrBlockMemLockedMemory_56cd7a; } @@ -513,13 +433,13 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe { pThis->__memmgrInsertUnprotectedRegionAtBottomOfFb__ = &memmgrInsertUnprotectedRegionAtBottomOfFb_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__memmgrInsertUnprotectedRegionAtBottomOfFb__ = &memmgrInsertUnprotectedRegionAtBottomOfFb_56cd7a; } // Hal function -- memmgrGetDisablePlcKind - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__memmgrGetDisablePlcKind__ = &memmgrGetDisablePlcKind_GA100; } @@ -533,7 +453,7 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe { pThis->__memmgrEnableDynamicPageOfflining__ = &memmgrEnableDynamicPageOfflining_GA100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__memmgrEnableDynamicPageOfflining__ = &memmgrEnableDynamicPageOfflining_GA102; } @@ -547,13 +467,10 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe { pThis->__memmgrGetBlackListPages__ = &memmgrGetBlackListPages_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__memmgrGetBlackListPages__ = &memmgrGetBlackListPages_GA100; } - else if (0) - { - } pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_MemoryManager_engstateConstructEngine; diff --git a/src/nvidia/generated/g_mem_mgr_nvoc.h b/src/nvidia/generated/g_mem_mgr_nvoc.h index c7e65aebe..47fda2c80 100644 --- a/src/nvidia/generated/g_mem_mgr_nvoc.h +++ b/src/nvidia/generated/g_mem_mgr_nvoc.h @@ -43,6 +43,8 @@ extern "C" { #include "mem_mgr/mem.h" +#include "mem_mgr/mem_list.h" + #include "gpu/mem_mgr/virt_mem_allocator_common.h" #include "containers/map.h" #include "gpu/mem_mgr/heap_base.h" @@ -327,9 +329,13 @@ typedef struct _def_fb_mem_node } FB_MEM_NODE, *PFB_MEM_NODE; // defines for MemoryManager::fbsrReservedRanges -#define MAX_FBSR_RESERVED_REGIONS 2 // Max. Memory descriptors for RM Instance memory +#define MAX_FBSR_RESERVED_REGIONS 6 // Max. Memory descriptors for RM Instance memory #define FBSR_RESERVED_INST_MEMORY_BEFORE_BAR2PTE 0 #define FBSR_RESERVED_INST_MEMORY_AFTER_BAR2PTE 1 +#define FBSR_RESERVED_INST_MEMORY_GSP_HEAP 2 +#define FBSR_RESERVED_INST_MEMORY_GSP_NON_WPR 3 +#define FBSR_RESERVED_INST_MEMORY_GSP_WPR 4 +#define FBSR_RESERVED_INST_MEMORY_VGA_WORKSPACE 5 /*! * MemoryManager provides the root memory management of GPU video memory. @@ -448,10 +454,10 @@ struct MemoryManager { NvBool bSysmemCompressionSupportDef; NvBool bBug1698088IncreaseRmReserveMemoryWar; NvBool bBug2301372IncreaseRmReserveMemoryWar; - NvBool bBug3620359IncreaseRmReserveMemoryWar; NvBool bEnableFbsrFileMode; NvBool bEnableDynamicPageOfflining; NvBool bVgpuPmaSupport; + NvBool bEnableDynamicGranularityPageArrays; NvBool bAllowNoncontiguousAllocation; NvBool bEccInterleavedVidmemScrub; NvBool bScrubberInitialized; @@ -477,11 +483,11 @@ struct MemoryManager { NvU64 overrideHeapMax; NvU64 fbOverrideStartKb; NvU64 rsvdMemorySizeIncrement; - struct OBJFBSR *pFbsr[7]; + struct OBJFBSR *pFbsr[8]; struct OBJFBSR *pActiveFbsr; NvU32 fbsrStartMode; NvU32 fixedFbsrModesMask; - MEMORY_DESCRIPTOR *fbsrReservedRanges[2]; + MEMORY_DESCRIPTOR *fbsrReservedRanges[6]; PFB_MEM_NODE pMemHeadNode; PFB_MEM_NODE pMemTailNode; struct RM_POOL_ALLOC_MEM_RESERVE_INFO *pPageLevelReserve; @@ -574,8 +580,37 @@ NV_STATUS __nvoc_objCreate_MemoryManager(MemoryManager**, Dynamic*, NvU32); #define memmgrAllocTunableState(pGpu, pEngstate, ppTunableState) memmgrAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) #define memmgrSetTunableState(pGpu, pEngstate, pTunableState) memmgrSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define memmgrIsPresent(pGpu, pEngstate) memmgrIsPresent_DISPATCH(pGpu, pEngstate) +NV_STATUS memmgrSavePowerMgmtState_KERNEL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + + +#ifdef __nvoc_mem_mgr_h_disabled +static inline NV_STATUS memmgrSavePowerMgmtState(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { + NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_mem_mgr_h_disabled +#define memmgrSavePowerMgmtState(pGpu, pMemoryManager) memmgrSavePowerMgmtState_KERNEL(pGpu, pMemoryManager) +#endif //__nvoc_mem_mgr_h_disabled + +#define memmgrSavePowerMgmtState_HAL(pGpu, pMemoryManager) memmgrSavePowerMgmtState(pGpu, pMemoryManager) + +NV_STATUS memmgrRestorePowerMgmtState_KERNEL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + + +#ifdef __nvoc_mem_mgr_h_disabled +static inline NV_STATUS memmgrRestorePowerMgmtState(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { + NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_mem_mgr_h_disabled +#define memmgrRestorePowerMgmtState(pGpu, pMemoryManager) memmgrRestorePowerMgmtState_KERNEL(pGpu, pMemoryManager) +#endif //__nvoc_mem_mgr_h_disabled + +#define memmgrRestorePowerMgmtState_HAL(pGpu, pMemoryManager) memmgrRestorePowerMgmtState(pGpu, pMemoryManager) + NvU32 memmgrDeterminePageSize_IMPL(struct MemoryManager *pMemoryManager, NvHandle hClient, NvU64 memSize, NvU32 memFormat, NvU32 pageFormatFlags, NvU32 *pRetAttr, NvU32 *pRetAttr2); + #ifdef __nvoc_mem_mgr_h_disabled static inline NvU32 memmgrDeterminePageSize(struct MemoryManager *pMemoryManager, NvHandle hClient, NvU64 memSize, NvU32 memFormat, NvU32 pageFormatFlags, NvU32 *pRetAttr, NvU32 *pRetAttr2) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -591,6 +626,7 @@ static inline NV_STATUS memmgrReserveConsoleRegion_56cd7a(OBJGPU *pGpu, struct M return NV_OK; } + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrReserveConsoleRegion(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_REGION_DESCRIPTOR *arg0) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -604,6 +640,7 @@ static inline NV_STATUS memmgrReserveConsoleRegion(OBJGPU *pGpu, struct MemoryMa NV_STATUS memmgrAllocateConsoleRegion_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_REGION_DESCRIPTOR *arg0); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrAllocateConsoleRegion(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_REGION_DESCRIPTOR *arg0) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -617,6 +654,7 @@ static inline NV_STATUS memmgrAllocateConsoleRegion(OBJGPU *pGpu, struct MemoryM NV_STATUS memmgrGetKindComprForGpu_KERNEL(struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR *arg0, OBJGPU *pGpu, NvU64 offset, NvU32 *kind, COMPR_INFO *pComprInfo); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrGetKindComprForGpu(struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR *arg0, OBJGPU *pGpu, NvU64 offset, NvU32 *kind, COMPR_INFO *pComprInfo) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -630,6 +668,7 @@ static inline NV_STATUS memmgrGetKindComprForGpu(struct MemoryManager *pMemoryMa NV_STATUS memmgrScrubInit_GP100(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrScrubInit(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -643,6 +682,7 @@ static inline NV_STATUS memmgrScrubInit(OBJGPU *pGpu, struct MemoryManager *pMem NV_STATUS memmgrScrubHandlePostSchedulingEnable_GP100(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrScrubHandlePostSchedulingEnable(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -658,6 +698,7 @@ static inline void memmgrGetScrubState_f2d351(OBJGPU *pGpu, struct MemoryManager NV_ASSERT_PRECOMP(0); } + #ifdef __nvoc_mem_mgr_h_disabled static inline void memmgrGetScrubState(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU64 *arg0, NvU64 *arg1, NvBool *arg2) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -672,6 +713,7 @@ static inline void memmgrScrubInternalRegions_b3696a(OBJGPU *pGpu, struct Memory return; } + #ifdef __nvoc_mem_mgr_h_disabled static inline void memmgrScrubInternalRegions(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -686,6 +728,9 @@ static inline NvBool memmgrEccScrubInProgress_491d52(OBJGPU *pGpu, struct Memory return ((NvBool)(0 != 0)); } +NvBool memmgrEccScrubInProgress_GP100(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + + #ifdef __nvoc_mem_mgr_h_disabled static inline NvBool memmgrEccScrubInProgress(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -701,6 +746,7 @@ static inline void memmgrAsyncScrubRegion_f2d351(OBJGPU *pGpu, struct MemoryMana NV_ASSERT_PRECOMP(0); } + #ifdef __nvoc_mem_mgr_h_disabled static inline void memmgrAsyncScrubRegion(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU64 arg0, NvU64 arg1) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -713,6 +759,7 @@ static inline void memmgrAsyncScrubRegion(OBJGPU *pGpu, struct MemoryManager *pM NV_STATUS memmgrScrubHandlePreSchedulingDisable_GP100(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrScrubHandlePreSchedulingDisable(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -726,6 +773,7 @@ static inline NV_STATUS memmgrScrubHandlePreSchedulingDisable(OBJGPU *pGpu, stru void memmgrScrubDestroy_GP100(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + #ifdef __nvoc_mem_mgr_h_disabled static inline void memmgrScrubDestroy(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -740,6 +788,9 @@ static inline void memmgrScrubMemory_b3696a(OBJGPU *pGpu, struct MemoryManager * return; } +void memmgrScrubMemory_GP100(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, RmPhysAddr arg0, NvU64 arg1); + + #ifdef __nvoc_mem_mgr_h_disabled static inline void memmgrScrubMemory(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, RmPhysAddr arg0, NvU64 arg1) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -752,6 +803,7 @@ static inline void memmgrScrubMemory(OBJGPU *pGpu, struct MemoryManager *pMemory NV_STATUS memmgrMemUtilsMemSetBlocking_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0, RmPhysAddr arg1, NvU64 arg2); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrMemUtilsMemSetBlocking(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0, RmPhysAddr arg1, NvU64 arg2) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -765,6 +817,7 @@ static inline NV_STATUS memmgrMemUtilsMemSetBlocking(OBJGPU *pGpu, struct Memory NV_STATUS memmgrMemUtilsMemSet_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0, RmPhysAddr arg1, NvU64 arg2, NvU32 arg3, NvU32 *arg4); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrMemUtilsMemSet(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0, RmPhysAddr arg1, NvU64 arg2, NvU32 arg3, NvU32 *arg4) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -778,6 +831,7 @@ static inline NV_STATUS memmgrMemUtilsMemSet(OBJGPU *pGpu, struct MemoryManager NV_STATUS memmgrMemUtilsMemSetBatched_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0, RmPhysAddr arg1, NvU64 arg2); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrMemUtilsMemSetBatched(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0, RmPhysAddr arg1, NvU64 arg2) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -791,6 +845,7 @@ static inline NV_STATUS memmgrMemUtilsMemSetBatched(OBJGPU *pGpu, struct MemoryM NV_STATUS memmgrMemUtilsMemCopyBatched_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0, RmPhysAddr arg1, NV_ADDRESS_SPACE arg2, NvU32 arg3, RmPhysAddr arg4, NV_ADDRESS_SPACE arg5, NvU32 arg6, NvU64 arg7); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrMemUtilsMemCopyBatched(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0, RmPhysAddr arg1, NV_ADDRESS_SPACE arg2, NvU32 arg3, RmPhysAddr arg4, NV_ADDRESS_SPACE arg5, NvU32 arg6, NvU64 arg7) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -804,6 +859,7 @@ static inline NV_STATUS memmgrMemUtilsMemCopyBatched(OBJGPU *pGpu, struct Memory NV_STATUS memmgrMemUtilsAllocateEccScrubber_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrMemUtilsAllocateEccScrubber(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -817,6 +873,7 @@ static inline NV_STATUS memmgrMemUtilsAllocateEccScrubber(OBJGPU *pGpu, struct M NV_STATUS memmgrMemUtilsAllocateEccAllocScrubber_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrMemUtilsAllocateEccAllocScrubber(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -830,6 +887,7 @@ static inline NV_STATUS memmgrMemUtilsAllocateEccAllocScrubber(OBJGPU *pGpu, str NV_STATUS memmgrMemUtilsChannelInitialize_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrMemUtilsChannelInitialize(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -843,6 +901,7 @@ static inline NV_STATUS memmgrMemUtilsChannelInitialize(OBJGPU *pGpu, struct Mem NV_STATUS memmgrMemUtilsCopyEngineInitialize_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrMemUtilsCopyEngineInitialize(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -856,6 +915,7 @@ static inline NV_STATUS memmgrMemUtilsCopyEngineInitialize(OBJGPU *pGpu, struct NV_STATUS memmgrMemUtilsGetCopyEngineClass_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 *pClass); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrMemUtilsGetCopyEngineClass(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 *pClass) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -869,6 +929,7 @@ static inline NV_STATUS memmgrMemUtilsGetCopyEngineClass(OBJGPU *pGpu, struct Me NV_STATUS memmgrMemUtilsCreateMemoryAlias_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrMemUtilsCreateMemoryAlias(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -882,6 +943,7 @@ static inline NV_STATUS memmgrMemUtilsCreateMemoryAlias(OBJGPU *pGpu, struct Mem NV_STATUS memmgrAllocHal_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_ALLOC_INFO *pFbAllocInfo); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrAllocHal(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_ALLOC_INFO *pFbAllocInfo) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -895,6 +957,7 @@ static inline NV_STATUS memmgrAllocHal(OBJGPU *pGpu, struct MemoryManager *pMemo NV_STATUS memmgrFreeHal_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_ALLOC_INFO *pFbAllocInfo, PRMTIMEOUT pTimeout); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrFreeHal(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_ALLOC_INFO *pFbAllocInfo, PRMTIMEOUT pTimeout) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -910,6 +973,7 @@ static inline NV_STATUS memmgrUpdateSurfaceCompression_5baef9(OBJGPU *pGpu, stru NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrUpdateSurfaceCompression(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, Memory *arg0, NvBool arg1) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -923,6 +987,7 @@ static inline NV_STATUS memmgrUpdateSurfaceCompression(OBJGPU *pGpu, struct Memo NV_STATUS memmgrGetBankPlacementData_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 *pBankPlacementLowData); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrGetBankPlacementData(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 *pBankPlacementLowData) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -936,6 +1001,7 @@ static inline NV_STATUS memmgrGetBankPlacementData(OBJGPU *pGpu, struct MemoryMa void memmgrDirtyForPmTest_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvBool partialDirty); + #ifdef __nvoc_mem_mgr_h_disabled static inline void memmgrDirtyForPmTest(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvBool partialDirty) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -948,6 +1014,7 @@ static inline void memmgrDirtyForPmTest(OBJGPU *pGpu, struct MemoryManager *pMem NvU32 memmgrGetReservedHeapSizeMb_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + #ifdef __nvoc_mem_mgr_h_disabled static inline NvU32 memmgrGetReservedHeapSizeMb(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -959,10 +1026,13 @@ static inline NvU32 memmgrGetReservedHeapSizeMb(OBJGPU *pGpu, struct MemoryManag #define memmgrGetReservedHeapSizeMb_HAL(pGpu, pMemoryManager) memmgrGetReservedHeapSizeMb(pGpu, pMemoryManager) +NV_STATUS memmgrInitFbRegionsHal_TU102(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + static inline NV_STATUS memmgrInitFbRegionsHal_56cd7a(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { return NV_OK; } + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrInitFbRegionsHal(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -976,6 +1046,7 @@ static inline NV_STATUS memmgrInitFbRegionsHal(OBJGPU *pGpu, struct MemoryManage void memmgrHandleSizeOverrides_GP100(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + #ifdef __nvoc_mem_mgr_h_disabled static inline void memmgrHandleSizeOverrides(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -988,6 +1059,7 @@ static inline void memmgrHandleSizeOverrides(OBJGPU *pGpu, struct MemoryManager NV_STATUS memmgrFinishHandleSizeOverrides_GP100(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrFinishHandleSizeOverrides(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1001,6 +1073,7 @@ static inline NV_STATUS memmgrFinishHandleSizeOverrides(OBJGPU *pGpu, struct Mem NV_STATUS memmgrGetBAR1InfoForClient_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvHandle arg0, PGETBAR1INFO bar1Info); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrGetBAR1InfoForClient(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvHandle arg0, PGETBAR1INFO bar1Info) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1016,6 +1089,7 @@ static inline NvU64 memmgrGetFbTaxSize_4a4dee(OBJGPU *pGpu, struct MemoryManager return 0; } + #ifdef __nvoc_mem_mgr_h_disabled static inline NvU64 memmgrGetFbTaxSize(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1027,9 +1101,12 @@ static inline NvU64 memmgrGetFbTaxSize(OBJGPU *pGpu, struct MemoryManager *pMemo #define memmgrGetFbTaxSize_HAL(pGpu, pMemoryManager) memmgrGetFbTaxSize(pGpu, pMemoryManager) -static inline NvU64 memmgrGetVgpuHostRmReservedFb_4a4dee(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 vgpuTypeId) { - return 0; -} +NvU64 memmgrGetVgpuHostRmReservedFb_KERNEL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 vgpuTypeId); + +NvU64 memmgrGetVgpuHostRmReservedFb_TU102(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 vgpuTypeId); + +NvU64 memmgrGetVgpuHostRmReservedFb_GA100(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 vgpuTypeId); + #ifdef __nvoc_mem_mgr_h_disabled static inline NvU64 memmgrGetVgpuHostRmReservedFb(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 vgpuTypeId) { @@ -1037,13 +1114,14 @@ static inline NvU64 memmgrGetVgpuHostRmReservedFb(OBJGPU *pGpu, struct MemoryMan return 0; } #else //__nvoc_mem_mgr_h_disabled -#define memmgrGetVgpuHostRmReservedFb(pGpu, pMemoryManager, vgpuTypeId) memmgrGetVgpuHostRmReservedFb_4a4dee(pGpu, pMemoryManager, vgpuTypeId) +#define memmgrGetVgpuHostRmReservedFb(pGpu, pMemoryManager, vgpuTypeId) memmgrGetVgpuHostRmReservedFb_KERNEL(pGpu, pMemoryManager, vgpuTypeId) #endif //__nvoc_mem_mgr_h_disabled #define memmgrGetVgpuHostRmReservedFb_HAL(pGpu, pMemoryManager, vgpuTypeId) memmgrGetVgpuHostRmReservedFb(pGpu, pMemoryManager, vgpuTypeId) NvU64 memmgrGetRsvdSizeForSr_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + #ifdef __nvoc_mem_mgr_h_disabled static inline NvU64 memmgrGetRsvdSizeForSr(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1059,6 +1137,7 @@ static inline NvBool memmgrVerifyDepthSurfaceAttrs_cbe027(struct MemoryManager * return ((NvBool)(0 == 0)); } + #ifdef __nvoc_mem_mgr_h_disabled static inline NvBool memmgrVerifyDepthSurfaceAttrs(struct MemoryManager *pMemoryManager, NvU32 arg0, NvU32 arg1) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1070,10 +1149,17 @@ static inline NvBool memmgrVerifyDepthSurfaceAttrs(struct MemoryManager *pMemory #define memmgrVerifyDepthSurfaceAttrs_HAL(pMemoryManager, arg0, arg1) memmgrVerifyDepthSurfaceAttrs(pMemoryManager, arg0, arg1) +NV_STATUS memmgrAllocMemToSaveVgaWorkspace_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR **arg0, MEMORY_DESCRIPTOR **arg1); + +static inline NV_STATUS memmgrAllocMemToSaveVgaWorkspace_46f6a7(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR **arg0, MEMORY_DESCRIPTOR **arg1) { + return NV_ERR_NOT_SUPPORTED; +} + static inline NV_STATUS memmgrAllocMemToSaveVgaWorkspace_5baef9(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR **arg0, MEMORY_DESCRIPTOR **arg1) { NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrAllocMemToSaveVgaWorkspace(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR **arg0, MEMORY_DESCRIPTOR **arg1) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1087,6 +1173,7 @@ static inline NV_STATUS memmgrAllocMemToSaveVgaWorkspace(OBJGPU *pGpu, struct Me NvBool memmgrComparePhysicalAddresses_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 arg0, NvU64 arg1, NvU32 arg2, NvU64 arg3); + #ifdef __nvoc_mem_mgr_h_disabled static inline NvBool memmgrComparePhysicalAddresses(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 arg0, NvU64 arg1, NvU32 arg2, NvU64 arg3) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1100,6 +1187,7 @@ static inline NvBool memmgrComparePhysicalAddresses(OBJGPU *pGpu, struct MemoryM RmPhysAddr memmgrGetInvalidOffset_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + #ifdef __nvoc_mem_mgr_h_disabled static inline RmPhysAddr memmgrGetInvalidOffset(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1115,6 +1203,7 @@ static inline RmPhysAddr memmgrGetInvalidOffset(OBJGPU *pGpu, struct MemoryManag NvU32 memmgrGetAddrSpaceSizeMB_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + #ifdef __nvoc_mem_mgr_h_disabled static inline NvU32 memmgrGetAddrSpaceSizeMB(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1128,6 +1217,7 @@ static inline NvU32 memmgrGetAddrSpaceSizeMB(OBJGPU *pGpu, struct MemoryManager NvU32 memmgrGetUsableMemSizeMB_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + #ifdef __nvoc_mem_mgr_h_disabled static inline NvU32 memmgrGetUsableMemSizeMB(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1141,6 +1231,7 @@ static inline NvU32 memmgrGetUsableMemSizeMB(OBJGPU *pGpu, struct MemoryManager NV_STATUS memmgrGetSurfacePhysAttr_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, Memory *pMemory, NvU64 *pOffset, NvU32 *pMemAperture, NvU32 *pMemKind, NvU32 *pComprOffset, NvU32 *pComprKind, NvU32 *pLineMin, NvU32 *pLineMax, NvU32 *pZCullId, NvU32 *pGpuCacheAttr, NvU32 *pGpuP2PCacheAttr, NvU64 *contigSegmentSize); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrGetSurfacePhysAttr(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, Memory *pMemory, NvU64 *pOffset, NvU32 *pMemAperture, NvU32 *pMemKind, NvU32 *pComprOffset, NvU32 *pComprKind, NvU32 *pLineMin, NvU32 *pLineMax, NvU32 *pZCullId, NvU32 *pGpuCacheAttr, NvU32 *pGpuP2PCacheAttr, NvU64 *contigSegmentSize) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1156,6 +1247,7 @@ static inline NvBool memmgrVerifyComprAttrs_cbe027(struct MemoryManager *pMemory return ((NvBool)(0 == 0)); } + #ifdef __nvoc_mem_mgr_h_disabled static inline NvBool memmgrVerifyComprAttrs(struct MemoryManager *pMemoryManager, NvU32 arg0, NvU32 arg1, NvU32 arg2) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1169,6 +1261,7 @@ static inline NvBool memmgrVerifyComprAttrs(struct MemoryManager *pMemoryManager NvBool memmgrIsKindCompressible_TU102(struct MemoryManager *pMemoryManager, NvU32 arg0); + #ifdef __nvoc_mem_mgr_h_disabled static inline NvBool memmgrIsKindCompressible(struct MemoryManager *pMemoryManager, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1184,6 +1277,7 @@ static inline NvBool memmgrIsKindBlocklinear_491d52(struct MemoryManager *pMemor return ((NvBool)(0 != 0)); } + #ifdef __nvoc_mem_mgr_h_disabled static inline NvBool memmgrIsKindBlocklinear(struct MemoryManager *pMemoryManager, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1197,6 +1291,7 @@ static inline NvBool memmgrIsKindBlocklinear(struct MemoryManager *pMemoryManage NvU32 memmgrChooseKindZ_TU102(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_ALLOC_PAGE_FORMAT *arg0); + #ifdef __nvoc_mem_mgr_h_disabled static inline NvU32 memmgrChooseKindZ(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_ALLOC_PAGE_FORMAT *arg0) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1210,6 +1305,7 @@ static inline NvU32 memmgrChooseKindZ(OBJGPU *pGpu, struct MemoryManager *pMemor NvU32 memmgrChooseKindCompressZ_TU102(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_ALLOC_PAGE_FORMAT *arg0); + #ifdef __nvoc_mem_mgr_h_disabled static inline NvU32 memmgrChooseKindCompressZ(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_ALLOC_PAGE_FORMAT *arg0) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1225,6 +1321,7 @@ static inline NvU32 memmgrChooseKindCompressCForMS2_4a4dee(OBJGPU *pGpu, struct return 0; } + #ifdef __nvoc_mem_mgr_h_disabled static inline NvU32 memmgrChooseKindCompressCForMS2(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1238,6 +1335,7 @@ static inline NvU32 memmgrChooseKindCompressCForMS2(OBJGPU *pGpu, struct MemoryM NvU32 memmgrGetUncompressedKind_TU102(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 kind, NvBool releaseReacquire); + #ifdef __nvoc_mem_mgr_h_disabled static inline NvU32 memmgrGetUncompressedKind(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 kind, NvBool releaseReacquire) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1253,6 +1351,7 @@ static inline NV_STATUS memmgrGetUncompressedKindForMS2_5baef9(OBJGPU *pGpu, str NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrGetUncompressedKindForMS2(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 arg0, NvU32 *arg1) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1266,6 +1365,7 @@ static inline NV_STATUS memmgrGetUncompressedKindForMS2(OBJGPU *pGpu, struct Mem NV_STATUS memmgrChooseKind_TU102(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_ALLOC_PAGE_FORMAT *arg0, NvU32 arg1, NvU32 *arg2); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrChooseKind(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_ALLOC_PAGE_FORMAT *arg0, NvU32 arg1, NvU32 *arg2) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1279,6 +1379,7 @@ static inline NV_STATUS memmgrChooseKind(OBJGPU *pGpu, struct MemoryManager *pMe NvBool memmgrIsKind_TU102(struct MemoryManager *pMemoryManager, FB_IS_KIND_OP arg0, NvU32 arg1); + #ifdef __nvoc_mem_mgr_h_disabled static inline NvBool memmgrIsKind(struct MemoryManager *pMemoryManager, FB_IS_KIND_OP arg0, NvU32 arg1) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1292,6 +1393,7 @@ static inline NvBool memmgrIsKind(struct MemoryManager *pMemoryManager, FB_IS_KI NvU32 memmgrGetMessageKind_TU102(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + #ifdef __nvoc_mem_mgr_h_disabled static inline NvU32 memmgrGetMessageKind(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1305,6 +1407,7 @@ static inline NvU32 memmgrGetMessageKind(OBJGPU *pGpu, struct MemoryManager *pMe NvU32 memmgrGetDefaultPteKindForNoHandle_TU102(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + #ifdef __nvoc_mem_mgr_h_disabled static inline NvU32 memmgrGetDefaultPteKindForNoHandle(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1318,6 +1421,7 @@ static inline NvU32 memmgrGetDefaultPteKindForNoHandle(OBJGPU *pGpu, struct Memo NvBool memmgrIsSurfaceBlockLinear_TU102(struct MemoryManager *pMemoryManager, Memory *arg0, NvU32 arg1, NvU32 arg2); + #ifdef __nvoc_mem_mgr_h_disabled static inline NvBool memmgrIsSurfaceBlockLinear(struct MemoryManager *pMemoryManager, Memory *arg0, NvU32 arg1, NvU32 arg2) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1331,6 +1435,7 @@ static inline NvBool memmgrIsSurfaceBlockLinear(struct MemoryManager *pMemoryMan NvU32 memmgrGetHwPteKindFromSwPteKind_TU102(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 pteKind); + #ifdef __nvoc_mem_mgr_h_disabled static inline NvU32 memmgrGetHwPteKindFromSwPteKind(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 pteKind) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1344,6 +1449,7 @@ static inline NvU32 memmgrGetHwPteKindFromSwPteKind(OBJGPU *pGpu, struct MemoryM NvU32 memmgrGetSwPteKindFromHwPteKind_TU102(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 pteKind); + #ifdef __nvoc_mem_mgr_h_disabled static inline NvU32 memmgrGetSwPteKindFromHwPteKind(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 pteKind) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1357,6 +1463,7 @@ static inline NvU32 memmgrGetSwPteKindFromHwPteKind(OBJGPU *pGpu, struct MemoryM void memmgrGetPteKindForScrubber_TU102(struct MemoryManager *pMemoryManager, NvU32 *arg0); + #ifdef __nvoc_mem_mgr_h_disabled static inline void memmgrGetPteKindForScrubber(struct MemoryManager *pMemoryManager, NvU32 *arg0) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1369,6 +1476,7 @@ static inline void memmgrGetPteKindForScrubber(struct MemoryManager *pMemoryMana NvU32 memmgrGetCtagOffsetFromParams_TU102(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_ALLOC_INFO *arg0); + #ifdef __nvoc_mem_mgr_h_disabled static inline NvU32 memmgrGetCtagOffsetFromParams(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_ALLOC_INFO *arg0) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1382,6 +1490,7 @@ static inline NvU32 memmgrGetCtagOffsetFromParams(OBJGPU *pGpu, struct MemoryMan void memmgrSetCtagOffsetInParams_TU102(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_ALLOC_INFO *arg0, NvU32 arg1); + #ifdef __nvoc_mem_mgr_h_disabled static inline void memmgrSetCtagOffsetInParams(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_ALLOC_INFO *arg0, NvU32 arg1) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1394,6 +1503,7 @@ static inline void memmgrSetCtagOffsetInParams(OBJGPU *pGpu, struct MemoryManage void memmgrChannelPushSemaphoreMethodsBlock_GP100(struct MemoryManager *pMemoryManager, NvU32 arg0, NvU64 arg1, NvU32 arg2, NvU32 **arg3); + #ifdef __nvoc_mem_mgr_h_disabled static inline void memmgrChannelPushSemaphoreMethodsBlock(struct MemoryManager *pMemoryManager, NvU32 arg0, NvU64 arg1, NvU32 arg2, NvU32 **arg3) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1406,6 +1516,7 @@ static inline void memmgrChannelPushSemaphoreMethodsBlock(struct MemoryManager * void memmgrChannelPushAddressMethodsBlock_GP100(struct MemoryManager *pMemoryManager, NvBool arg0, NvU32 arg1, RmPhysAddr arg2, NvU32 **arg3); + #ifdef __nvoc_mem_mgr_h_disabled static inline void memmgrChannelPushAddressMethodsBlock(struct MemoryManager *pMemoryManager, NvBool arg0, NvU32 arg1, RmPhysAddr arg2, NvU32 **arg3) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1418,6 +1529,7 @@ static inline void memmgrChannelPushAddressMethodsBlock(struct MemoryManager *pM NV_STATUS memmgrScrubMapDoorbellRegion_GV100(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrScrubMapDoorbellRegion(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1431,6 +1543,7 @@ static inline NV_STATUS memmgrScrubMapDoorbellRegion(OBJGPU *pGpu, struct Memory NV_STATUS memmgrSetAllocParameters_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_ALLOC_INFO *pFbAllocInfo); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrSetAllocParameters(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_ALLOC_INFO *pFbAllocInfo) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1444,6 +1557,7 @@ static inline NV_STATUS memmgrSetAllocParameters(OBJGPU *pGpu, struct MemoryMana void memmgrCalcReservedFbSpaceForUVM_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU64 *arg0); + #ifdef __nvoc_mem_mgr_h_disabled static inline void memmgrCalcReservedFbSpaceForUVM(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU64 *arg0) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1456,6 +1570,9 @@ static inline void memmgrCalcReservedFbSpaceForUVM(OBJGPU *pGpu, struct MemoryMa void memmgrCalcReservedFbSpaceHal_FWCLIENT(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU64 *arg0, NvU64 *arg1, NvU64 *arg2); +void memmgrCalcReservedFbSpaceHal_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU64 *arg0, NvU64 *arg1, NvU64 *arg2); + + #ifdef __nvoc_mem_mgr_h_disabled static inline void memmgrCalcReservedFbSpaceHal(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU64 *arg0, NvU64 *arg1, NvU64 *arg2) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1470,6 +1587,9 @@ static inline NvU32 memmgrGetGrHeapReservationSize_4a4dee(OBJGPU *pGpu, struct M return 0; } +NvU32 memmgrGetGrHeapReservationSize_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + + #ifdef __nvoc_mem_mgr_h_disabled static inline NvU32 memmgrGetGrHeapReservationSize(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1483,6 +1603,7 @@ static inline NvU32 memmgrGetGrHeapReservationSize(OBJGPU *pGpu, struct MemoryMa NvU32 memmgrGetRunlistEntriesReservedFbSpace_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + #ifdef __nvoc_mem_mgr_h_disabled static inline NvU32 memmgrGetRunlistEntriesReservedFbSpace(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1496,6 +1617,7 @@ static inline NvU32 memmgrGetRunlistEntriesReservedFbSpace(OBJGPU *pGpu, struct NvU32 memmgrGetUserdReservedFbSpace_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + #ifdef __nvoc_mem_mgr_h_disabled static inline NvU32 memmgrGetUserdReservedFbSpace(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1509,6 +1631,7 @@ static inline NvU32 memmgrGetUserdReservedFbSpace(OBJGPU *pGpu, struct MemoryMan NV_STATUS memmgrInitReservedMemory_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU64 arg0); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrInitReservedMemory(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU64 arg0) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1522,6 +1645,9 @@ static inline NV_STATUS memmgrInitReservedMemory(OBJGPU *pGpu, struct MemoryMana NV_STATUS memmgrPreInitReservedMemory_FWCLIENT(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); +NV_STATUS memmgrPreInitReservedMemory_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrPreInitReservedMemory(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1535,6 +1661,9 @@ static inline NV_STATUS memmgrPreInitReservedMemory(OBJGPU *pGpu, struct MemoryM NV_STATUS memmgrInitBaseFbRegions_FWCLIENT(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); +NV_STATUS memmgrInitBaseFbRegions_GP102(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrInitBaseFbRegions(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1548,6 +1677,7 @@ static inline NV_STATUS memmgrInitBaseFbRegions(OBJGPU *pGpu, struct MemoryManag NV_STATUS memmgrSetMemDescPageSize_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, PMEMORY_DESCRIPTOR arg0, ADDRESS_TRANSLATION arg1, RM_ATTR_PAGE_SIZE arg2); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrSetMemDescPageSize(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, PMEMORY_DESCRIPTOR arg0, ADDRESS_TRANSLATION arg1, RM_ATTR_PAGE_SIZE arg2) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1561,6 +1691,7 @@ static inline NV_STATUS memmgrSetMemDescPageSize(OBJGPU *pGpu, struct MemoryMana NV_STATUS memmgrSetPartitionableMem_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrSetPartitionableMem(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1574,6 +1705,7 @@ static inline NV_STATUS memmgrSetPartitionableMem(OBJGPU *pGpu, struct MemoryMan NV_STATUS memmgrAllocMIGGPUInstanceMemory_PF(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 swizzId, NvHandle *phMemory, struct NV_RANGE *pAddrRange, struct Heap **ppMemoryPartitionHeap); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrAllocMIGGPUInstanceMemory(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 swizzId, NvHandle *phMemory, struct NV_RANGE *pAddrRange, struct Heap **ppMemoryPartitionHeap) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1587,6 +1719,7 @@ static inline NV_STATUS memmgrAllocMIGGPUInstanceMemory(OBJGPU *pGpu, struct Mem NV_STATUS memmgrGetBlackListPagesForHeap_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, struct Heap *pHeap); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrGetBlackListPagesForHeap(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, struct Heap *pHeap) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1602,6 +1735,7 @@ static inline NV_STATUS memmgrDiscoverMIGPartitionableMemoryRange_46f6a7(OBJGPU return NV_ERR_NOT_SUPPORTED; } + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrDiscoverMIGPartitionableMemoryRange(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, struct NV_RANGE *pMemoryRange) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1613,6 +1747,37 @@ static inline NV_STATUS memmgrDiscoverMIGPartitionableMemoryRange(OBJGPU *pGpu, #define memmgrDiscoverMIGPartitionableMemoryRange_HAL(pGpu, pMemoryManager, pMemoryRange) memmgrDiscoverMIGPartitionableMemoryRange(pGpu, pMemoryManager, pMemoryRange) +void memmgrFreeFbsrMemory_KERNEL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + + +#ifdef __nvoc_mem_mgr_h_disabled +static inline void memmgrFreeFbsrMemory(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { + NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); +} +#else //__nvoc_mem_mgr_h_disabled +#define memmgrFreeFbsrMemory(pGpu, pMemoryManager) memmgrFreeFbsrMemory_KERNEL(pGpu, pMemoryManager) +#endif //__nvoc_mem_mgr_h_disabled + +#define memmgrFreeFbsrMemory_HAL(pGpu, pMemoryManager) memmgrFreeFbsrMemory(pGpu, pMemoryManager) + +static inline NV_STATUS memmgrCreateVgaWorkspaceMemDesc_46f6a7(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS memmgrCreateVgaWorkspaceMemDesc_TU102(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + + +#ifdef __nvoc_mem_mgr_h_disabled +static inline NV_STATUS memmgrCreateVgaWorkspaceMemDesc(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { + NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_mem_mgr_h_disabled +#define memmgrCreateVgaWorkspaceMemDesc(pGpu, pMemoryManager) memmgrCreateVgaWorkspaceMemDesc_46f6a7(pGpu, pMemoryManager) +#endif //__nvoc_mem_mgr_h_disabled + +#define memmgrCreateVgaWorkspaceMemDesc_HAL(pGpu, pMemoryManager) memmgrCreateVgaWorkspaceMemDesc(pGpu, pMemoryManager) + NV_STATUS memmgrConstructEngine_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, ENGDESCRIPTOR arg0); static inline NV_STATUS memmgrConstructEngine_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, ENGDESCRIPTOR arg0) { @@ -1669,14 +1834,6 @@ NV_STATUS memmgrAllocDetermineAlignment_GM107(OBJGPU *pGpu, struct MemoryManager NV_STATUS memmgrAllocDetermineAlignment_GA100(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU64 *pMemSize, NvU64 *pAlign, NvU64 alignPad, NvU32 allocFlags, NvU32 retAttr, NvU32 retAttr2, NvU64 hwAlignment); -static inline NV_STATUS memmgrAllocDetermineAlignment_5baef9(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU64 *pMemSize, NvU64 *pAlign, NvU64 alignPad, NvU32 allocFlags, NvU32 retAttr, NvU32 retAttr2, NvU64 hwAlignment) { - NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); -} - -static inline NV_STATUS memmgrAllocDetermineAlignment_56cd7a(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU64 *pMemSize, NvU64 *pAlign, NvU64 alignPad, NvU32 allocFlags, NvU32 retAttr, NvU32 retAttr2, NvU64 hwAlignment) { - return NV_OK; -} - static inline NV_STATUS memmgrAllocDetermineAlignment_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU64 *pMemSize, NvU64 *pAlign, NvU64 alignPad, NvU32 allocFlags, NvU32 retAttr, NvU32 retAttr2, NvU64 hwAlignment) { return pMemoryManager->__memmgrAllocDetermineAlignment__(pGpu, pMemoryManager, pMemSize, pAlign, alignPad, allocFlags, retAttr, retAttr2, hwAlignment); } @@ -1687,10 +1844,6 @@ NvU64 memmgrGetMaxContextSize_GA100(OBJGPU *pGpu, struct MemoryManager *pMemoryM NvU64 memmgrGetMaxContextSize_AD102(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); -static inline NvU64 memmgrGetMaxContextSize_4a4dee(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { - return 0; -} - static inline NvU64 memmgrGetMaxContextSize_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { return pMemoryManager->__memmgrGetMaxContextSize__(pGpu, pMemoryManager); } @@ -1699,10 +1852,6 @@ void memmgrScrubRegistryOverrides_GM107(OBJGPU *pGpu, struct MemoryManager *pMem void memmgrScrubRegistryOverrides_GA100(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); -static inline void memmgrScrubRegistryOverrides_b3696a(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { - return; -} - static inline void memmgrScrubRegistryOverrides_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { pMemoryManager->__memmgrScrubRegistryOverrides__(pGpu, pMemoryManager); } @@ -1825,10 +1974,6 @@ NV_STATUS memmgrGetBlackListPages_GM107(OBJGPU *pGpu, struct MemoryManager *pMem NV_STATUS memmgrGetBlackListPages_GA100(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, BLACKLIST_ADDRESS *pBlAddrs, NvU32 *pCount); -static inline NV_STATUS memmgrGetBlackListPages_46f6a7(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, BLACKLIST_ADDRESS *pBlAddrs, NvU32 *pCount) { - return NV_ERR_NOT_SUPPORTED; -} - static inline NV_STATUS memmgrGetBlackListPages_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, BLACKLIST_ADDRESS *pBlAddrs, NvU32 *pCount) { return pMemoryManager->__memmgrGetBlackListPages__(pGpu, pMemoryManager, pBlAddrs, pCount); } @@ -1954,28 +2099,10 @@ static inline NvU32 memmgrGetRsvdMemorySize(struct MemoryManager *pMemoryManager } void memmgrDestruct_IMPL(struct MemoryManager *pMemoryManager); + #define __nvoc_memmgrDestruct(pMemoryManager) memmgrDestruct_IMPL(pMemoryManager) -NV_STATUS memmgrSavePowerMgmtState_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); -#ifdef __nvoc_mem_mgr_h_disabled -static inline NV_STATUS memmgrSavePowerMgmtState(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { - NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_mem_mgr_h_disabled -#define memmgrSavePowerMgmtState(pGpu, pMemoryManager) memmgrSavePowerMgmtState_IMPL(pGpu, pMemoryManager) -#endif //__nvoc_mem_mgr_h_disabled - -NV_STATUS memmgrRestorePowerMgmtState_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); -#ifdef __nvoc_mem_mgr_h_disabled -static inline NV_STATUS memmgrRestorePowerMgmtState(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { - NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_mem_mgr_h_disabled -#define memmgrRestorePowerMgmtState(pGpu, pMemoryManager) memmgrRestorePowerMgmtState_IMPL(pGpu, pMemoryManager) -#endif //__nvoc_mem_mgr_h_disabled - NV_STATUS memmgrAllocResources_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, MEMORY_ALLOCATION_REQUEST *pAllocRequest, FB_ALLOC_INFO *pFbAllocInfo); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrAllocResources(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, MEMORY_ALLOCATION_REQUEST *pAllocRequest, FB_ALLOC_INFO *pFbAllocInfo) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1986,6 +2113,7 @@ static inline NV_STATUS memmgrAllocResources(OBJGPU *pGpu, struct MemoryManager #endif //__nvoc_mem_mgr_h_disabled NV_STATUS memmgrFree_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, struct Heap *arg0, NvHandle arg1, NvHandle arg2, NvHandle arg3, NvU32 arg4, MEMORY_DESCRIPTOR *arg5); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrFree(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, struct Heap *arg0, NvHandle arg1, NvHandle arg2, NvHandle arg3, NvU32 arg4, MEMORY_DESCRIPTOR *arg5) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -1995,7 +2123,40 @@ static inline NV_STATUS memmgrFree(OBJGPU *pGpu, struct MemoryManager *pMemoryMa #define memmgrFree(pGpu, pMemoryManager, arg0, arg1, arg2, arg3, arg4, arg5) memmgrFree_IMPL(pGpu, pMemoryManager, arg0, arg1, arg2, arg3, arg4, arg5) #endif //__nvoc_mem_mgr_h_disabled +NV_STATUS memmgrAddMemNode_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR *pMemDesc, NvBool bFreeDescriptor); + +#ifdef __nvoc_mem_mgr_h_disabled +static inline NV_STATUS memmgrAddMemNode(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR *pMemDesc, NvBool bFreeDescriptor) { + NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_mem_mgr_h_disabled +#define memmgrAddMemNode(pGpu, pMemoryManager, pMemDesc, bFreeDescriptor) memmgrAddMemNode_IMPL(pGpu, pMemoryManager, pMemDesc, bFreeDescriptor) +#endif //__nvoc_mem_mgr_h_disabled + +NV_STATUS memmgrAddMemNodes_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvBool bSaveAllRmAllocations); + +#ifdef __nvoc_mem_mgr_h_disabled +static inline NV_STATUS memmgrAddMemNodes(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvBool bSaveAllRmAllocations) { + NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_mem_mgr_h_disabled +#define memmgrAddMemNodes(pGpu, pMemoryManager, bSaveAllRmAllocations) memmgrAddMemNodes_IMPL(pGpu, pMemoryManager, bSaveAllRmAllocations) +#endif //__nvoc_mem_mgr_h_disabled + +void memmgrRemoveMemNodes_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + +#ifdef __nvoc_mem_mgr_h_disabled +static inline void memmgrRemoveMemNodes(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { + NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); +} +#else //__nvoc_mem_mgr_h_disabled +#define memmgrRemoveMemNodes(pGpu, pMemoryManager) memmgrRemoveMemNodes_IMPL(pGpu, pMemoryManager) +#endif //__nvoc_mem_mgr_h_disabled + struct Heap *memmgrGetDeviceSuballocator_IMPL(struct MemoryManager *pMemoryManager, NvBool bForceSubheap); + #ifdef __nvoc_mem_mgr_h_disabled static inline struct Heap *memmgrGetDeviceSuballocator(struct MemoryManager *pMemoryManager, NvBool bForceSubheap) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2006,6 +2167,7 @@ static inline struct Heap *memmgrGetDeviceSuballocator(struct MemoryManager *pMe #endif //__nvoc_mem_mgr_h_disabled NV_STATUS memmgrMemCopy_IMPL(struct MemoryManager *pMemoryManager, TRANSFER_SURFACE *pDst, TRANSFER_SURFACE *pSrc, NvU32 size, NvU32 flags); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrMemCopy(struct MemoryManager *pMemoryManager, TRANSFER_SURFACE *pDst, TRANSFER_SURFACE *pSrc, NvU32 size, NvU32 flags) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2016,6 +2178,7 @@ static inline NV_STATUS memmgrMemCopy(struct MemoryManager *pMemoryManager, TRAN #endif //__nvoc_mem_mgr_h_disabled NV_STATUS memmgrMemSet_IMPL(struct MemoryManager *pMemoryManager, TRANSFER_SURFACE *pDst, NvU32 value, NvU32 size, NvU32 flags); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrMemSet(struct MemoryManager *pMemoryManager, TRANSFER_SURFACE *pDst, NvU32 value, NvU32 size, NvU32 flags) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2026,6 +2189,7 @@ static inline NV_STATUS memmgrMemSet(struct MemoryManager *pMemoryManager, TRANS #endif //__nvoc_mem_mgr_h_disabled NV_STATUS memmgrMemWrite_IMPL(struct MemoryManager *pMemoryManager, TRANSFER_SURFACE *pDst, void *pBuf, NvU64 size, NvU32 flags); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrMemWrite(struct MemoryManager *pMemoryManager, TRANSFER_SURFACE *pDst, void *pBuf, NvU64 size, NvU32 flags) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2036,6 +2200,7 @@ static inline NV_STATUS memmgrMemWrite(struct MemoryManager *pMemoryManager, TRA #endif //__nvoc_mem_mgr_h_disabled NV_STATUS memmgrMemRead_IMPL(struct MemoryManager *pMemoryManager, TRANSFER_SURFACE *pSrc, void *pBuf, NvU64 size, NvU32 flags); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrMemRead(struct MemoryManager *pMemoryManager, TRANSFER_SURFACE *pSrc, void *pBuf, NvU64 size, NvU32 flags) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2046,6 +2211,7 @@ static inline NV_STATUS memmgrMemRead(struct MemoryManager *pMemoryManager, TRAN #endif //__nvoc_mem_mgr_h_disabled NvU8 *memmgrMemBeginTransfer_IMPL(struct MemoryManager *pMemoryManager, TRANSFER_SURFACE *pTransferInfo, NvU64 shadowBufSize, NvU32 flags); + #ifdef __nvoc_mem_mgr_h_disabled static inline NvU8 *memmgrMemBeginTransfer(struct MemoryManager *pMemoryManager, TRANSFER_SURFACE *pTransferInfo, NvU64 shadowBufSize, NvU32 flags) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2056,6 +2222,7 @@ static inline NvU8 *memmgrMemBeginTransfer(struct MemoryManager *pMemoryManager, #endif //__nvoc_mem_mgr_h_disabled void memmgrMemEndTransfer_IMPL(struct MemoryManager *pMemoryManager, TRANSFER_SURFACE *pTransferInfo, NvU64 shadowBufSize, NvU32 flags); + #ifdef __nvoc_mem_mgr_h_disabled static inline void memmgrMemEndTransfer(struct MemoryManager *pMemoryManager, TRANSFER_SURFACE *pTransferInfo, NvU64 shadowBufSize, NvU32 flags) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2065,6 +2232,7 @@ static inline void memmgrMemEndTransfer(struct MemoryManager *pMemoryManager, TR #endif //__nvoc_mem_mgr_h_disabled NvU8 *memmgrMemDescBeginTransfer_IMPL(struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR *pMemDesc, NvU32 flags); + #ifdef __nvoc_mem_mgr_h_disabled static inline NvU8 *memmgrMemDescBeginTransfer(struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR *pMemDesc, NvU32 flags) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2075,6 +2243,7 @@ static inline NvU8 *memmgrMemDescBeginTransfer(struct MemoryManager *pMemoryMana #endif //__nvoc_mem_mgr_h_disabled void memmgrMemDescEndTransfer_IMPL(struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR *pMemDesc, NvU32 flags); + #ifdef __nvoc_mem_mgr_h_disabled static inline void memmgrMemDescEndTransfer(struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR *pMemDesc, NvU32 flags) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2084,6 +2253,7 @@ static inline void memmgrMemDescEndTransfer(struct MemoryManager *pMemoryManager #endif //__nvoc_mem_mgr_h_disabled NV_STATUS memmgrMemDescMemSet_IMPL(struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR *pMemDesc, NvU32 value, NvU32 flags); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrMemDescMemSet(struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR *pMemDesc, NvU32 value, NvU32 flags) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2094,6 +2264,7 @@ static inline NV_STATUS memmgrMemDescMemSet(struct MemoryManager *pMemoryManager #endif //__nvoc_mem_mgr_h_disabled NV_ADDRESS_SPACE memmgrAllocGetAddrSpace_IMPL(struct MemoryManager *pMemoryManager, NvU32 flags, NvU32 attr); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_ADDRESS_SPACE memmgrAllocGetAddrSpace(struct MemoryManager *pMemoryManager, NvU32 flags, NvU32 attr) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2106,6 +2277,7 @@ static inline NV_ADDRESS_SPACE memmgrAllocGetAddrSpace(struct MemoryManager *pMe #endif //__nvoc_mem_mgr_h_disabled NV_STATUS memmgrCreateHeap_IMPL(struct MemoryManager *pMemoryManager); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrCreateHeap(struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2116,6 +2288,7 @@ static inline NV_STATUS memmgrCreateHeap(struct MemoryManager *pMemoryManager) { #endif //__nvoc_mem_mgr_h_disabled NV_STATUS memmgrGetUsedRamSize_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU64 *arg0); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrGetUsedRamSize(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU64 *arg0) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2126,6 +2299,7 @@ static inline NV_STATUS memmgrGetUsedRamSize(OBJGPU *pGpu, struct MemoryManager #endif //__nvoc_mem_mgr_h_disabled NV_STATUS memmgrAllocHwResources_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_ALLOC_INFO *arg0); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrAllocHwResources(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_ALLOC_INFO *arg0) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2136,6 +2310,7 @@ static inline NV_STATUS memmgrAllocHwResources(OBJGPU *pGpu, struct MemoryManage #endif //__nvoc_mem_mgr_h_disabled NV_STATUS memmgrFreeHwResources_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_ALLOC_INFO *arg0); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrFreeHwResources(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_ALLOC_INFO *arg0) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2146,6 +2321,7 @@ static inline NV_STATUS memmgrFreeHwResources(OBJGPU *pGpu, struct MemoryManager #endif //__nvoc_mem_mgr_h_disabled NvBool memmgrLargePageSupported_IMPL(struct MemoryManager *pMemoryManager, NV_ADDRESS_SPACE arg0); + #ifdef __nvoc_mem_mgr_h_disabled static inline NvBool memmgrLargePageSupported(struct MemoryManager *pMemoryManager, NV_ADDRESS_SPACE arg0) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2156,6 +2332,7 @@ static inline NvBool memmgrLargePageSupported(struct MemoryManager *pMemoryManag #endif //__nvoc_mem_mgr_h_disabled NvBool memmgrComprSupported_IMPL(struct MemoryManager *pMemoryManager, NV_ADDRESS_SPACE arg0); + #ifdef __nvoc_mem_mgr_h_disabled static inline NvBool memmgrComprSupported(struct MemoryManager *pMemoryManager, NV_ADDRESS_SPACE arg0) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2166,6 +2343,7 @@ static inline NvBool memmgrComprSupported(struct MemoryManager *pMemoryManager, #endif //__nvoc_mem_mgr_h_disabled NvU32 memmgrGetMappableRamSizeMb_IMPL(struct MemoryManager *pMemoryManager); + #ifdef __nvoc_mem_mgr_h_disabled static inline NvU32 memmgrGetMappableRamSizeMb(struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2176,6 +2354,7 @@ static inline NvU32 memmgrGetMappableRamSizeMb(struct MemoryManager *pMemoryMana #endif //__nvoc_mem_mgr_h_disabled PFB_REGION_DESCRIPTOR memmgrLookupFbRegionByOffset_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, RmPhysAddr fbOffset, RmPhysAddr fbLimit); + #ifdef __nvoc_mem_mgr_h_disabled static inline PFB_REGION_DESCRIPTOR memmgrLookupFbRegionByOffset(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, RmPhysAddr fbOffset, RmPhysAddr fbLimit) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2186,6 +2365,7 @@ static inline PFB_REGION_DESCRIPTOR memmgrLookupFbRegionByOffset(OBJGPU *pGpu, s #endif //__nvoc_mem_mgr_h_disabled NV_STATUS memmgrFillMemdescForPhysAttr_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, PMEMORY_DESCRIPTOR arg0, ADDRESS_TRANSLATION arg1, NvU64 *arg2, NvU32 *arg3, NvU32 *arg4, NvU32 *arg5, NvU32 *arg6, NvU32 *arg7, NvU64 *arg8); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrFillMemdescForPhysAttr(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, PMEMORY_DESCRIPTOR arg0, ADDRESS_TRANSLATION arg1, NvU64 *arg2, NvU32 *arg3, NvU32 *arg4, NvU32 *arg5, NvU32 *arg6, NvU32 *arg7, NvU64 *arg8) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2196,6 +2376,7 @@ static inline NV_STATUS memmgrFillMemdescForPhysAttr(OBJGPU *pGpu, struct Memory #endif //__nvoc_mem_mgr_h_disabled NV_STATUS memmgrSetPlatformPmaSupport_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrSetPlatformPmaSupport(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2206,6 +2387,7 @@ static inline NV_STATUS memmgrSetPlatformPmaSupport(OBJGPU *pGpu, struct MemoryM #endif //__nvoc_mem_mgr_h_disabled void memmgrRegionSetupForPma_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + #ifdef __nvoc_mem_mgr_h_disabled static inline void memmgrRegionSetupForPma(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2215,6 +2397,7 @@ static inline void memmgrRegionSetupForPma(OBJGPU *pGpu, struct MemoryManager *p #endif //__nvoc_mem_mgr_h_disabled NV_STATUS memmgrInitFbRegions_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrInitFbRegions(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2225,6 +2408,7 @@ static inline NV_STATUS memmgrInitFbRegions(OBJGPU *pGpu, struct MemoryManager * #endif //__nvoc_mem_mgr_h_disabled void memmgrRegionSetupCommon_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + #ifdef __nvoc_mem_mgr_h_disabled static inline void memmgrRegionSetupCommon(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2234,6 +2418,7 @@ static inline void memmgrRegionSetupCommon(OBJGPU *pGpu, struct MemoryManager *p #endif //__nvoc_mem_mgr_h_disabled void memmgrRegenerateFbRegionPriority_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + #ifdef __nvoc_mem_mgr_h_disabled static inline void memmgrRegenerateFbRegionPriority(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2243,6 +2428,7 @@ static inline void memmgrRegenerateFbRegionPriority(OBJGPU *pGpu, struct MemoryM #endif //__nvoc_mem_mgr_h_disabled NvU32 memmgrInsertFbRegion_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, PFB_REGION_DESCRIPTOR arg0); + #ifdef __nvoc_mem_mgr_h_disabled static inline NvU32 memmgrInsertFbRegion(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, PFB_REGION_DESCRIPTOR arg0) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2253,6 +2439,7 @@ static inline NvU32 memmgrInsertFbRegion(OBJGPU *pGpu, struct MemoryManager *pMe #endif //__nvoc_mem_mgr_h_disabled void memmgrDumpFbRegions_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + #ifdef __nvoc_mem_mgr_h_disabled static inline void memmgrDumpFbRegions(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2262,6 +2449,7 @@ static inline void memmgrDumpFbRegions(OBJGPU *pGpu, struct MemoryManager *pMemo #endif //__nvoc_mem_mgr_h_disabled void memmgrClearFbRegions_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + #ifdef __nvoc_mem_mgr_h_disabled static inline void memmgrClearFbRegions(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2271,6 +2459,7 @@ static inline void memmgrClearFbRegions(OBJGPU *pGpu, struct MemoryManager *pMem #endif //__nvoc_mem_mgr_h_disabled void memmgrReleaseConsoleRegion_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + #ifdef __nvoc_mem_mgr_h_disabled static inline void memmgrReleaseConsoleRegion(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2280,6 +2469,7 @@ static inline void memmgrReleaseConsoleRegion(OBJGPU *pGpu, struct MemoryManager #endif //__nvoc_mem_mgr_h_disabled PMEMORY_DESCRIPTOR memmgrGetReservedConsoleMemDesc_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + #ifdef __nvoc_mem_mgr_h_disabled static inline PMEMORY_DESCRIPTOR memmgrGetReservedConsoleMemDesc(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2290,6 +2480,7 @@ static inline PMEMORY_DESCRIPTOR memmgrGetReservedConsoleMemDesc(OBJGPU *pGpu, s #endif //__nvoc_mem_mgr_h_disabled void memmgrReserveBar2BackingStore_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU64 *arg0); + #ifdef __nvoc_mem_mgr_h_disabled static inline void memmgrReserveBar2BackingStore(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU64 *arg0) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2299,6 +2490,7 @@ static inline void memmgrReserveBar2BackingStore(OBJGPU *pGpu, struct MemoryMana #endif //__nvoc_mem_mgr_h_disabled void memmgrCalcReservedFbSpace_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + #ifdef __nvoc_mem_mgr_h_disabled static inline void memmgrCalcReservedFbSpace(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2308,6 +2500,7 @@ static inline void memmgrCalcReservedFbSpace(OBJGPU *pGpu, struct MemoryManager #endif //__nvoc_mem_mgr_h_disabled void memmgrMemUtilsSetupChannelBufferSizes_IMPL(struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0, NvU32 arg1); + #ifdef __nvoc_mem_mgr_h_disabled static inline void memmgrMemUtilsSetupChannelBufferSizes(struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0, NvU32 arg1) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2317,6 +2510,7 @@ static inline void memmgrMemUtilsSetupChannelBufferSizes(struct MemoryManager *p #endif //__nvoc_mem_mgr_h_disabled NV_STATUS memmgrGetKindComprFromMemDesc_IMPL(struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR *arg0, NvU64 offset, NvU32 *kind, COMPR_INFO *pComprInfo); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrGetKindComprFromMemDesc(struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR *arg0, NvU64 offset, NvU32 *kind, COMPR_INFO *pComprInfo) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2327,6 +2521,7 @@ static inline NV_STATUS memmgrGetKindComprFromMemDesc(struct MemoryManager *pMem #endif //__nvoc_mem_mgr_h_disabled NvBool memmgrIsCompressible_IMPL(struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR *arg0); + #ifdef __nvoc_mem_mgr_h_disabled static inline NvBool memmgrIsCompressible(struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR *arg0) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2337,6 +2532,7 @@ static inline NvBool memmgrIsCompressible(struct MemoryManager *pMemoryManager, #endif //__nvoc_mem_mgr_h_disabled NV_STATUS memmgrFillComprInfo_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 arg0, NvU32 arg1, NvU32 arg2, NvU64 arg3, NvU32 arg4, COMPR_INFO *arg5); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrFillComprInfo(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 arg0, NvU32 arg1, NvU32 arg2, NvU64 arg3, NvU32 arg4, COMPR_INFO *arg5) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2347,6 +2543,7 @@ static inline NV_STATUS memmgrFillComprInfo(OBJGPU *pGpu, struct MemoryManager * #endif //__nvoc_mem_mgr_h_disabled void memmgrComprInfoDisableCompression_IMPL(struct MemoryManager *pMemoryManager, COMPR_INFO *pComprInfo); + #ifdef __nvoc_mem_mgr_h_disabled static inline void memmgrComprInfoDisableCompression(struct MemoryManager *pMemoryManager, COMPR_INFO *pComprInfo) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2356,6 +2553,7 @@ static inline void memmgrComprInfoDisableCompression(struct MemoryManager *pMemo #endif //__nvoc_mem_mgr_h_disabled void memmgrFillComprInfoUncompressed_IMPL(struct MemoryManager *pMemoryManager, NvU32 kind, COMPR_INFO *pComprInfo); + #ifdef __nvoc_mem_mgr_h_disabled static inline void memmgrFillComprInfoUncompressed(struct MemoryManager *pMemoryManager, NvU32 kind, COMPR_INFO *pComprInfo) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2365,6 +2563,7 @@ static inline void memmgrFillComprInfoUncompressed(struct MemoryManager *pMemory #endif //__nvoc_mem_mgr_h_disabled NV_STATUS memmgrPmaInitialize_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, PMA *pPma); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrPmaInitialize(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, PMA *pPma) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2375,6 +2574,7 @@ static inline NV_STATUS memmgrPmaInitialize(OBJGPU *pGpu, struct MemoryManager * #endif //__nvoc_mem_mgr_h_disabled NV_STATUS memmgrPmaRegisterRegions_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, struct Heap *pHeap, PMA *pPma); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrPmaRegisterRegions(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, struct Heap *pHeap, PMA *pPma) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2385,6 +2585,7 @@ static inline NV_STATUS memmgrPmaRegisterRegions(OBJGPU *pGpu, struct MemoryMana #endif //__nvoc_mem_mgr_h_disabled NV_STATUS memmgrSetMIGPartitionableBAR1Range_IMPL(OBJGPU *arg0, struct MemoryManager *arg1); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrSetMIGPartitionableBAR1Range(OBJGPU *arg0, struct MemoryManager *arg1) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2395,6 +2596,7 @@ static inline NV_STATUS memmgrSetMIGPartitionableBAR1Range(OBJGPU *arg0, struct #endif //__nvoc_mem_mgr_h_disabled struct NV_RANGE memmgrGetMIGPartitionableBAR1Range_IMPL(OBJGPU *arg0, struct MemoryManager *arg1); + #ifdef __nvoc_mem_mgr_h_disabled static inline struct NV_RANGE memmgrGetMIGPartitionableBAR1Range(OBJGPU *arg0, struct MemoryManager *arg1) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2407,6 +2609,7 @@ static inline struct NV_RANGE memmgrGetMIGPartitionableBAR1Range(OBJGPU *arg0, s #endif //__nvoc_mem_mgr_h_disabled void memmgrSetMIGPartitionableMemoryRange_IMPL(OBJGPU *arg0, struct MemoryManager *arg1, struct NV_RANGE arg2); + #ifdef __nvoc_mem_mgr_h_disabled static inline void memmgrSetMIGPartitionableMemoryRange(OBJGPU *arg0, struct MemoryManager *arg1, struct NV_RANGE arg2) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2416,6 +2619,7 @@ static inline void memmgrSetMIGPartitionableMemoryRange(OBJGPU *arg0, struct Mem #endif //__nvoc_mem_mgr_h_disabled struct NV_RANGE memmgrGetMIGPartitionableMemoryRange_IMPL(OBJGPU *arg0, struct MemoryManager *arg1); + #ifdef __nvoc_mem_mgr_h_disabled static inline struct NV_RANGE memmgrGetMIGPartitionableMemoryRange(OBJGPU *arg0, struct MemoryManager *arg1) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2428,6 +2632,7 @@ static inline struct NV_RANGE memmgrGetMIGPartitionableMemoryRange(OBJGPU *arg0, #endif //__nvoc_mem_mgr_h_disabled NV_STATUS memmgrFreeMIGGPUInstanceMemory_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 swizzId, NvHandle hMemory, struct Heap **ppMemoryPartitionHeap); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrFreeMIGGPUInstanceMemory(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 swizzId, NvHandle hMemory, struct Heap **ppMemoryPartitionHeap) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2438,6 +2643,7 @@ static inline NV_STATUS memmgrFreeMIGGPUInstanceMemory(OBJGPU *pGpu, struct Memo #endif //__nvoc_mem_mgr_h_disabled NV_STATUS memmgrPageLevelPoolsCreate_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrPageLevelPoolsCreate(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2448,6 +2654,7 @@ static inline NV_STATUS memmgrPageLevelPoolsCreate(OBJGPU *pGpu, struct MemoryMa #endif //__nvoc_mem_mgr_h_disabled void memmgrPageLevelPoolsDestroy_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + #ifdef __nvoc_mem_mgr_h_disabled static inline void memmgrPageLevelPoolsDestroy(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2457,6 +2664,7 @@ static inline void memmgrPageLevelPoolsDestroy(OBJGPU *pGpu, struct MemoryManage #endif //__nvoc_mem_mgr_h_disabled NV_STATUS memmgrPageLevelPoolsGetInfo_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvHandle arg0, struct RM_POOL_ALLOC_MEM_RESERVE_INFO **arg1); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrPageLevelPoolsGetInfo(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvHandle arg0, struct RM_POOL_ALLOC_MEM_RESERVE_INFO **arg1) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2467,6 +2675,7 @@ static inline NV_STATUS memmgrPageLevelPoolsGetInfo(OBJGPU *pGpu, struct MemoryM #endif //__nvoc_mem_mgr_h_disabled NV_STATUS memmgrAllocMIGMemoryAllocationInternalHandles_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrAllocMIGMemoryAllocationInternalHandles(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2477,6 +2686,7 @@ static inline NV_STATUS memmgrAllocMIGMemoryAllocationInternalHandles(OBJGPU *pG #endif //__nvoc_mem_mgr_h_disabled void memmgrFreeMIGMemoryAllocationInternalHandles_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + #ifdef __nvoc_mem_mgr_h_disabled static inline void memmgrFreeMIGMemoryAllocationInternalHandles(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2486,6 +2696,7 @@ static inline void memmgrFreeMIGMemoryAllocationInternalHandles(OBJGPU *pGpu, st #endif //__nvoc_mem_mgr_h_disabled void memmgrGetFreeMemoryForAllMIGGPUInstances_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU64 *pBytes); + #ifdef __nvoc_mem_mgr_h_disabled static inline void memmgrGetFreeMemoryForAllMIGGPUInstances(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU64 *pBytes) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2495,6 +2706,7 @@ static inline void memmgrGetFreeMemoryForAllMIGGPUInstances(OBJGPU *pGpu, struct #endif //__nvoc_mem_mgr_h_disabled void memmgrGetTopLevelScrubberStatus_IMPL(OBJGPU *arg0, struct MemoryManager *arg1, NvBool *pbTopLevelScrubberEnabled, NvBool *pbTopLevelScrubberConstructed); + #ifdef __nvoc_mem_mgr_h_disabled static inline void memmgrGetTopLevelScrubberStatus(OBJGPU *arg0, struct MemoryManager *arg1, NvBool *pbTopLevelScrubberEnabled, NvBool *pbTopLevelScrubberConstructed) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2504,6 +2716,7 @@ static inline void memmgrGetTopLevelScrubberStatus(OBJGPU *arg0, struct MemoryMa #endif //__nvoc_mem_mgr_h_disabled NV_STATUS memmgrSaveAndDestroyTopLevelScrubber_IMPL(OBJGPU *arg0, struct MemoryManager *arg1); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrSaveAndDestroyTopLevelScrubber(OBJGPU *arg0, struct MemoryManager *arg1) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2514,6 +2727,7 @@ static inline NV_STATUS memmgrSaveAndDestroyTopLevelScrubber(OBJGPU *arg0, struc #endif //__nvoc_mem_mgr_h_disabled NV_STATUS memmgrInitSavedTopLevelScrubber_IMPL(OBJGPU *arg0, struct MemoryManager *arg1); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrInitSavedTopLevelScrubber(OBJGPU *arg0, struct MemoryManager *arg1) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); @@ -2524,6 +2738,7 @@ static inline NV_STATUS memmgrInitSavedTopLevelScrubber(OBJGPU *arg0, struct Mem #endif //__nvoc_mem_mgr_h_disabled NV_STATUS memmgrReserveMemoryForFsp_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + #ifdef __nvoc_mem_mgr_h_disabled static inline NV_STATUS memmgrReserveMemoryForFsp(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); diff --git a/src/nvidia/generated/g_mem_multicast_fabric_nvoc.c b/src/nvidia/generated/g_mem_multicast_fabric_nvoc.c new file mode 100644 index 000000000..1ef3f8f5c --- /dev/null +++ b/src/nvidia/generated/g_mem_multicast_fabric_nvoc.c @@ -0,0 +1,414 @@ +#define NVOC_MEM_MULTICAST_FABRIC_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_mem_multicast_fabric_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0x130210 = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_MemoryMulticastFabric; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RsResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResourceCommon; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Memory; + +void __nvoc_init_MemoryMulticastFabric(MemoryMulticastFabric*); +void __nvoc_init_funcTable_MemoryMulticastFabric(MemoryMulticastFabric*); +NV_STATUS __nvoc_ctor_MemoryMulticastFabric(MemoryMulticastFabric*, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +void __nvoc_init_dataField_MemoryMulticastFabric(MemoryMulticastFabric*); +void __nvoc_dtor_MemoryMulticastFabric(MemoryMulticastFabric*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_MemoryMulticastFabric; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryMulticastFabric_MemoryMulticastFabric = { + /*pClassDef=*/ &__nvoc_class_def_MemoryMulticastFabric, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_MemoryMulticastFabric, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryMulticastFabric_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(MemoryMulticastFabric, __nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryMulticastFabric_RsResource = { + /*pClassDef=*/ &__nvoc_class_def_RsResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(MemoryMulticastFabric, __nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryMulticastFabric_RmResourceCommon = { + /*pClassDef=*/ &__nvoc_class_def_RmResourceCommon, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(MemoryMulticastFabric, __nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon), +}; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryMulticastFabric_RmResource = { + /*pClassDef=*/ &__nvoc_class_def_RmResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(MemoryMulticastFabric, __nvoc_base_Memory.__nvoc_base_RmResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryMulticastFabric_Memory = { + /*pClassDef=*/ &__nvoc_class_def_Memory, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(MemoryMulticastFabric, __nvoc_base_Memory), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_MemoryMulticastFabric = { + /*numRelatives=*/ 6, + /*relatives=*/ { + &__nvoc_rtti_MemoryMulticastFabric_MemoryMulticastFabric, + &__nvoc_rtti_MemoryMulticastFabric_Memory, + &__nvoc_rtti_MemoryMulticastFabric_RmResource, + &__nvoc_rtti_MemoryMulticastFabric_RmResourceCommon, + &__nvoc_rtti_MemoryMulticastFabric_RsResource, + &__nvoc_rtti_MemoryMulticastFabric_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_MemoryMulticastFabric = +{ + /*classInfo=*/ { + /*size=*/ sizeof(MemoryMulticastFabric), + /*classId=*/ classId(MemoryMulticastFabric), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "MemoryMulticastFabric", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_MemoryMulticastFabric, + /*pCastInfo=*/ &__nvoc_castinfo_MemoryMulticastFabric, + /*pExportInfo=*/ &__nvoc_export_info_MemoryMulticastFabric +}; + +static NvBool __nvoc_thunk_MemoryMulticastFabric_resCanCopy(struct RsResource *pMemoryMulticastFabric) { + return memorymulticastfabricCanCopy((struct MemoryMulticastFabric *)(((unsigned char *)pMemoryMulticastFabric) - __nvoc_rtti_MemoryMulticastFabric_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_MemoryMulticastFabric_memIsReady(struct Memory *pMemoryMulticastFabric, NvBool bCopyConstructorContext) { + return memorymulticastfabricIsReady((struct MemoryMulticastFabric *)(((unsigned char *)pMemoryMulticastFabric) - __nvoc_rtti_MemoryMulticastFabric_Memory.offset), bCopyConstructorContext); +} + +static NV_STATUS __nvoc_thunk_MemoryMulticastFabric_memControl(struct Memory *pMemoryMulticastFabric, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return memorymulticastfabricControl((struct MemoryMulticastFabric *)(((unsigned char *)pMemoryMulticastFabric) - __nvoc_rtti_MemoryMulticastFabric_Memory.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_MemoryMulticastFabric_rmresControl_Prologue(struct RmResource *pMemoryMulticastFabric, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return memorymulticastfabricControl_Prologue((struct MemoryMulticastFabric *)(((unsigned char *)pMemoryMulticastFabric) - __nvoc_rtti_MemoryMulticastFabric_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_MemoryMulticastFabric_memIsGpuMapAllowed(struct Memory *pMemoryMulticastFabric, struct OBJGPU *pGpu) { + return memorymulticastfabricIsGpuMapAllowed((struct MemoryMulticastFabric *)(((unsigned char *)pMemoryMulticastFabric) - __nvoc_rtti_MemoryMulticastFabric_Memory.offset), pGpu); +} + +static NV_STATUS __nvoc_thunk_MemoryMulticastFabric_memGetMapAddrSpace(struct Memory *pMemoryMulticastFabric, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memorymulticastfabricGetMapAddrSpace((struct MemoryMulticastFabric *)(((unsigned char *)pMemoryMulticastFabric) - __nvoc_rtti_MemoryMulticastFabric_Memory.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NV_STATUS __nvoc_thunk_Memory_memorymulticastfabricCheckMemInterUnmap(struct MemoryMulticastFabric *pMemory, NvBool bSubdeviceHandleProvided) { + return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryMulticastFabric_Memory.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_Memory_memorymulticastfabricUnmap(struct MemoryMulticastFabric *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryMulticastFabric_Memory.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_Memory_memorymulticastfabricGetMemInterMapParams(struct MemoryMulticastFabric *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryMulticastFabric_Memory.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_memorymulticastfabricGetMemoryMappingDescriptor(struct MemoryMulticastFabric *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryMulticastFabric_Memory.offset), ppMemDesc); +} + +static NvBool __nvoc_thunk_RmResource_memorymulticastfabricShareCallback(struct MemoryMulticastFabric *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RsResource_memorymulticastfabricControlFilter(struct MemoryMulticastFabric *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RsResource.offset), pCallContext, pParams); +} + +static void __nvoc_thunk_RsResource_memorymulticastfabricAddAdditionalDependants(struct RsClient *pClient, struct MemoryMulticastFabric *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RsResource.offset), pReference); +} + +static NvU32 __nvoc_thunk_RsResource_memorymulticastfabricGetRefCount(struct MemoryMulticastFabric *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_memorymulticastfabricMapTo(struct MemoryMulticastFabric *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_memorymulticastfabricCheckCopyPermissions(struct MemoryMulticastFabric *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryMulticastFabric_Memory.offset), pDstGpu, hDstClientNvBool); +} + +static void __nvoc_thunk_RsResource_memorymulticastfabricPreDestruct(struct MemoryMulticastFabric *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_Memory_memorymulticastfabricIsDuplicate(struct MemoryMulticastFabric *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryMulticastFabric_Memory.offset), hMemory, pDuplicate); +} + +static NV_STATUS __nvoc_thunk_RsResource_memorymulticastfabricUnmapFrom(struct MemoryMulticastFabric *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_memorymulticastfabricControl_Epilogue(struct MemoryMulticastFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_memorymulticastfabricControlLookup(struct MemoryMulticastFabric *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RsResource.offset), pParams, ppEntry); +} + +static NV_STATUS __nvoc_thunk_Memory_memorymulticastfabricMap(struct MemoryMulticastFabric *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { + return memMap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryMulticastFabric_Memory.offset), pCallContext, pParams, pCpuMapping); +} + +static NvBool __nvoc_thunk_RmResource_memorymulticastfabricAccessCallback(struct MemoryMulticastFabric *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RmResource.offset), pInvokingClient, pAllocParams, accessRight); +} + +#if !defined(NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG) +#define NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(x) (0) +#endif + +static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_MemoryMulticastFabric[] = +{ + { /* [0] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) memorymulticastfabricCtrlGetInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xfd0101u, + /*paramSize=*/ sizeof(NV00FD_CTRL_GET_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_MemoryMulticastFabric.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "memorymulticastfabricCtrlGetInfo" +#endif + }, + { /* [1] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) memorymulticastfabricCtrlAttachMem_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xfd0102u, + /*paramSize=*/ sizeof(NV00FD_CTRL_ATTACH_MEM_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_MemoryMulticastFabric.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "memorymulticastfabricCtrlAttachMem" +#endif + }, + { /* [2] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) memorymulticastfabricCtrlRegisterEvent_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xfd0103u, + /*paramSize=*/ sizeof(NV00FD_CTRL_REGISTER_EVENT_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_MemoryMulticastFabric.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "memorymulticastfabricCtrlRegisterEvent" +#endif + }, + +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_MemoryMulticastFabric = +{ + /*numEntries=*/ 3, + /*pExportEntries=*/ __nvoc_exported_method_def_MemoryMulticastFabric +}; + +void __nvoc_dtor_Memory(Memory*); +void __nvoc_dtor_MemoryMulticastFabric(MemoryMulticastFabric *pThis) { + __nvoc_memorymulticastfabricDestruct(pThis); + __nvoc_dtor_Memory(&pThis->__nvoc_base_Memory); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_MemoryMulticastFabric(MemoryMulticastFabric *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_Memory(Memory* , CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); +NV_STATUS __nvoc_ctor_MemoryMulticastFabric(MemoryMulticastFabric *pThis, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_Memory(&pThis->__nvoc_base_Memory, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_MemoryMulticastFabric_fail_Memory; + __nvoc_init_dataField_MemoryMulticastFabric(pThis); + + status = __nvoc_memorymulticastfabricConstruct(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_MemoryMulticastFabric_fail__init; + goto __nvoc_ctor_MemoryMulticastFabric_exit; // Success + +__nvoc_ctor_MemoryMulticastFabric_fail__init: + __nvoc_dtor_Memory(&pThis->__nvoc_base_Memory); +__nvoc_ctor_MemoryMulticastFabric_fail_Memory: +__nvoc_ctor_MemoryMulticastFabric_exit: + + return status; +} + +static void __nvoc_init_funcTable_MemoryMulticastFabric_1(MemoryMulticastFabric *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); + + pThis->__memorymulticastfabricCanCopy__ = &memorymulticastfabricCanCopy_IMPL; + + pThis->__memorymulticastfabricCopyConstruct__ = &memorymulticastfabricCopyConstruct_IMPL; + + pThis->__memorymulticastfabricIsReady__ = &memorymulticastfabricIsReady_IMPL; + + pThis->__memorymulticastfabricControl__ = &memorymulticastfabricControl_IMPL; + + pThis->__memorymulticastfabricControl_Prologue__ = &memorymulticastfabricControl_Prologue_IMPL; + + pThis->__memorymulticastfabricIsGpuMapAllowed__ = &memorymulticastfabricIsGpuMapAllowed_IMPL; + + pThis->__memorymulticastfabricGetMapAddrSpace__ = &memorymulticastfabricGetMapAddrSpace_IMPL; + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + pThis->__memorymulticastfabricCtrlGetInfo__ = &memorymulticastfabricCtrlGetInfo_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + pThis->__memorymulticastfabricCtrlAttachMem__ = &memorymulticastfabricCtrlAttachMem_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + pThis->__memorymulticastfabricCtrlRegisterEvent__ = &memorymulticastfabricCtrlRegisterEvent_IMPL; +#endif + + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__resCanCopy__ = &__nvoc_thunk_MemoryMulticastFabric_resCanCopy; + + pThis->__nvoc_base_Memory.__memIsReady__ = &__nvoc_thunk_MemoryMulticastFabric_memIsReady; + + pThis->__nvoc_base_Memory.__memControl__ = &__nvoc_thunk_MemoryMulticastFabric_memControl; + + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__rmresControl_Prologue__ = &__nvoc_thunk_MemoryMulticastFabric_rmresControl_Prologue; + + pThis->__nvoc_base_Memory.__memIsGpuMapAllowed__ = &__nvoc_thunk_MemoryMulticastFabric_memIsGpuMapAllowed; + + pThis->__nvoc_base_Memory.__memGetMapAddrSpace__ = &__nvoc_thunk_MemoryMulticastFabric_memGetMapAddrSpace; + + pThis->__memorymulticastfabricCheckMemInterUnmap__ = &__nvoc_thunk_Memory_memorymulticastfabricCheckMemInterUnmap; + + pThis->__memorymulticastfabricUnmap__ = &__nvoc_thunk_Memory_memorymulticastfabricUnmap; + + pThis->__memorymulticastfabricGetMemInterMapParams__ = &__nvoc_thunk_Memory_memorymulticastfabricGetMemInterMapParams; + + pThis->__memorymulticastfabricGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_memorymulticastfabricGetMemoryMappingDescriptor; + + pThis->__memorymulticastfabricShareCallback__ = &__nvoc_thunk_RmResource_memorymulticastfabricShareCallback; + + pThis->__memorymulticastfabricControlFilter__ = &__nvoc_thunk_RsResource_memorymulticastfabricControlFilter; + + pThis->__memorymulticastfabricAddAdditionalDependants__ = &__nvoc_thunk_RsResource_memorymulticastfabricAddAdditionalDependants; + + pThis->__memorymulticastfabricGetRefCount__ = &__nvoc_thunk_RsResource_memorymulticastfabricGetRefCount; + + pThis->__memorymulticastfabricMapTo__ = &__nvoc_thunk_RsResource_memorymulticastfabricMapTo; + + pThis->__memorymulticastfabricCheckCopyPermissions__ = &__nvoc_thunk_Memory_memorymulticastfabricCheckCopyPermissions; + + pThis->__memorymulticastfabricPreDestruct__ = &__nvoc_thunk_RsResource_memorymulticastfabricPreDestruct; + + pThis->__memorymulticastfabricIsDuplicate__ = &__nvoc_thunk_Memory_memorymulticastfabricIsDuplicate; + + pThis->__memorymulticastfabricUnmapFrom__ = &__nvoc_thunk_RsResource_memorymulticastfabricUnmapFrom; + + pThis->__memorymulticastfabricControl_Epilogue__ = &__nvoc_thunk_RmResource_memorymulticastfabricControl_Epilogue; + + pThis->__memorymulticastfabricControlLookup__ = &__nvoc_thunk_RsResource_memorymulticastfabricControlLookup; + + pThis->__memorymulticastfabricMap__ = &__nvoc_thunk_Memory_memorymulticastfabricMap; + + pThis->__memorymulticastfabricAccessCallback__ = &__nvoc_thunk_RmResource_memorymulticastfabricAccessCallback; +} + +void __nvoc_init_funcTable_MemoryMulticastFabric(MemoryMulticastFabric *pThis) { + __nvoc_init_funcTable_MemoryMulticastFabric_1(pThis); +} + +void __nvoc_init_Memory(Memory*); +void __nvoc_init_MemoryMulticastFabric(MemoryMulticastFabric *pThis) { + pThis->__nvoc_pbase_MemoryMulticastFabric = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; + pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource; + pThis->__nvoc_pbase_RmResourceCommon = &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon; + pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_Memory.__nvoc_base_RmResource; + pThis->__nvoc_pbase_Memory = &pThis->__nvoc_base_Memory; + __nvoc_init_Memory(&pThis->__nvoc_base_Memory); + __nvoc_init_funcTable_MemoryMulticastFabric(pThis); +} + +NV_STATUS __nvoc_objCreate_MemoryMulticastFabric(MemoryMulticastFabric **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status; + Object *pParentObj; + MemoryMulticastFabric *pThis; + + pThis = portMemAllocNonPaged(sizeof(MemoryMulticastFabric)); + if (pThis == NULL) return NV_ERR_NO_MEMORY; + + portMemSet(pThis, 0, sizeof(MemoryMulticastFabric)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MemoryMulticastFabric); + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_MemoryMulticastFabric(pThis); + status = __nvoc_ctor_MemoryMulticastFabric(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_objCreate_MemoryMulticastFabric_cleanup; + + *ppThis = pThis; + return NV_OK; + +__nvoc_objCreate_MemoryMulticastFabric_cleanup: + // do not call destructors here since the constructor already called them + portMemFree(pThis); + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_MemoryMulticastFabric(MemoryMulticastFabric **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + CALL_CONTEXT * arg_pCallContext = va_arg(args, CALL_CONTEXT *); + struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams = va_arg(args, struct RS_RES_ALLOC_PARAMS_INTERNAL *); + + status = __nvoc_objCreate_MemoryMulticastFabric(ppThis, pParent, createFlags, arg_pCallContext, arg_pParams); + + return status; +} + diff --git a/src/nvidia/generated/g_mem_multicast_fabric_nvoc.h b/src/nvidia/generated/g_mem_multicast_fabric_nvoc.h new file mode 100644 index 000000000..20c234721 --- /dev/null +++ b/src/nvidia/generated/g_mem_multicast_fabric_nvoc.h @@ -0,0 +1,389 @@ +#ifndef _G_MEM_MULTICAST_FABRIC_NVOC_H_ +#define _G_MEM_MULTICAST_FABRIC_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/****************************************************************************** + * + * Description: + * This file contains the functions for managing multicast fabric memory + * + *****************************************************************************/ + +#include "g_mem_multicast_fabric_nvoc.h" + +#ifndef _MEMORYMULTICASTFABRIC_H_ +#define _MEMORYMULTICASTFABRIC_H_ + + + +#include "mem_mgr/mem.h" +#include "rmapi/resource.h" + +#include "class/cl00fd.h" +#include "ctrl/ctrl00fd.h" +#include "ctrl/ctrl2080/ctrl2080nvlink.h" + +// **************************************************************************** +// Type Definitions +// **************************************************************************** +typedef struct mem_multicast_fabric_attach_mem_info +{ + NvU64 offset; + NvU64 mapOffset; + NvU64 mapLength; + NvU32 flags; + OBJGPU *pGpu; + MEMORY_DESCRIPTOR *pPhysMemDesc; + NvHandle hDupedPhysMem; + NvU64 gpuProbeHandle; +} MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO; + +typedef struct mem_multicast_fabric_client_info +{ + void *pOsEvent; + struct Memory *pMemory; +} MEM_MULTICAST_FABRIC_CLIENT_INFO; + +typedef struct mem_multicast_fabric_gpu_os_info +{ + void *gpuOsInfo; +} MEM_MULTICAST_FABRIC_GPU_OS_INFO; + +MAKE_LIST(MemMulticastFabricAttachMemInfoList, MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO); + +MAKE_LIST(MemMulticastFabricClientInfoList, MEM_MULTICAST_FABRIC_CLIENT_INFO); + +MAKE_LIST(MemMulticastFabricGpuOsInfoList, MEM_MULTICAST_FABRIC_GPU_OS_INFO); + +typedef enum +{ + MEM_MULTICAST_FABRIC_TEAM_SETUP_REQUEST = 0, + MEM_MULTICAST_FABRIC_TEAM_RELEASE_REQUEST, +} MEM_MULTICAST_FABRIC_REQUEST_TYPE; + +typedef struct mem_multicast_fabric_descriptor +{ + // Refcount to keep this descriptor alive + NvU64 refCount; + + // List of clients waiting on this object to be ready + MemMulticastFabricClientInfoList waitingClientsList; + + // List of attach mem info of GPUs already attached to the mutlicast object + MemMulticastFabricAttachMemInfoList attachMemInfoList; + + // Mask representing the list of attached GPUs + NvU32 attachedGpusMask; + + // List of GPU OS Info + MemMulticastFabricGpuOsInfoList gpuOsInfoList; + + // Boolean to be set when pMemDesc is installed + NvBool bMemdescInstalled; + + // Memory descriptor associated with the multicast object + MEMORY_DESCRIPTOR *pMemDesc; + + // Unique handle assigned for the multicast team by FM + NvU64 mcTeamHandle; + + // Status of the multicast team + NV_STATUS mcTeamStatus; + + // Boolean to be set when an Inband request has been sent to FM and is currently in progress + NvBool bInbandReqInProgress; + + // Request Id associated with the Inband request in progress when bInbandReqSent is set to true + NvU64 inbandReqId; + + // Alignment for the multicast FLA allocation + NvU64 alignment; + + // Multicast FLA allocation size + NvU64 allocSize; + + // Page size for the multicast FLA + NvU32 pageSize; + + // Multicast FLA allocation flags + NvU32 allocFlags; + + // Max. number of unique GPUs associated with the multicast object + NvU32 numMaxGpus; + + // No. of unique GPUs currently attached to the multicast object + NvU32 numAttachedGpus; +} MEM_MULTICAST_FABRIC_DESCRIPTOR; + +#ifdef NVOC_MEM_MULTICAST_FABRIC_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct MemoryMulticastFabric { + const struct NVOC_RTTI *__nvoc_rtti; + struct Memory __nvoc_base_Memory; + struct Object *__nvoc_pbase_Object; + struct RsResource *__nvoc_pbase_RsResource; + struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; + struct RmResource *__nvoc_pbase_RmResource; + struct Memory *__nvoc_pbase_Memory; + struct MemoryMulticastFabric *__nvoc_pbase_MemoryMulticastFabric; + NvBool (*__memorymulticastfabricCanCopy__)(struct MemoryMulticastFabric *); + NV_STATUS (*__memorymulticastfabricCopyConstruct__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); + NV_STATUS (*__memorymulticastfabricIsReady__)(struct MemoryMulticastFabric *, NvBool); + NV_STATUS (*__memorymulticastfabricControl__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memorymulticastfabricControl_Prologue__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__memorymulticastfabricIsGpuMapAllowed__)(struct MemoryMulticastFabric *, struct OBJGPU *); + NV_STATUS (*__memorymulticastfabricGetMapAddrSpace__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NV_STATUS (*__memorymulticastfabricCtrlGetInfo__)(struct MemoryMulticastFabric *, NV00FD_CTRL_GET_INFO_PARAMS *); + NV_STATUS (*__memorymulticastfabricCtrlAttachMem__)(struct MemoryMulticastFabric *, NV00FD_CTRL_ATTACH_MEM_PARAMS *); + NV_STATUS (*__memorymulticastfabricCtrlRegisterEvent__)(struct MemoryMulticastFabric *, NV00FD_CTRL_REGISTER_EVENT_PARAMS *); + NV_STATUS (*__memorymulticastfabricCheckMemInterUnmap__)(struct MemoryMulticastFabric *, NvBool); + NV_STATUS (*__memorymulticastfabricUnmap__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__memorymulticastfabricGetMemInterMapParams__)(struct MemoryMulticastFabric *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__memorymulticastfabricGetMemoryMappingDescriptor__)(struct MemoryMulticastFabric *, MEMORY_DESCRIPTOR **); + NvBool (*__memorymulticastfabricShareCallback__)(struct MemoryMulticastFabric *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__memorymulticastfabricControlFilter__)(struct MemoryMulticastFabric *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__memorymulticastfabricAddAdditionalDependants__)(struct RsClient *, struct MemoryMulticastFabric *, RsResourceRef *); + NvU32 (*__memorymulticastfabricGetRefCount__)(struct MemoryMulticastFabric *); + NV_STATUS (*__memorymulticastfabricMapTo__)(struct MemoryMulticastFabric *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__memorymulticastfabricCheckCopyPermissions__)(struct MemoryMulticastFabric *, struct OBJGPU *, NvHandle); + void (*__memorymulticastfabricPreDestruct__)(struct MemoryMulticastFabric *); + NV_STATUS (*__memorymulticastfabricIsDuplicate__)(struct MemoryMulticastFabric *, NvHandle, NvBool *); + NV_STATUS (*__memorymulticastfabricUnmapFrom__)(struct MemoryMulticastFabric *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__memorymulticastfabricControl_Epilogue__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memorymulticastfabricControlLookup__)(struct MemoryMulticastFabric *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__memorymulticastfabricMap__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); + NvBool (*__memorymulticastfabricAccessCallback__)(struct MemoryMulticastFabric *, struct RsClient *, void *, RsAccessRight); + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc; +}; + +#ifndef __NVOC_CLASS_MemoryMulticastFabric_TYPEDEF__ +#define __NVOC_CLASS_MemoryMulticastFabric_TYPEDEF__ +typedef struct MemoryMulticastFabric MemoryMulticastFabric; +#endif /* __NVOC_CLASS_MemoryMulticastFabric_TYPEDEF__ */ + +#ifndef __nvoc_class_id_MemoryMulticastFabric +#define __nvoc_class_id_MemoryMulticastFabric 0x130210 +#endif /* __nvoc_class_id_MemoryMulticastFabric */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_MemoryMulticastFabric; + +#define __staticCast_MemoryMulticastFabric(pThis) \ + ((pThis)->__nvoc_pbase_MemoryMulticastFabric) + +#ifdef __nvoc_mem_multicast_fabric_h_disabled +#define __dynamicCast_MemoryMulticastFabric(pThis) ((MemoryMulticastFabric*)NULL) +#else //__nvoc_mem_multicast_fabric_h_disabled +#define __dynamicCast_MemoryMulticastFabric(pThis) \ + ((MemoryMulticastFabric*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(MemoryMulticastFabric))) +#endif //__nvoc_mem_multicast_fabric_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_MemoryMulticastFabric(MemoryMulticastFabric**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_MemoryMulticastFabric(MemoryMulticastFabric**, Dynamic*, NvU32, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +#define __objCreate_MemoryMulticastFabric(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ + __nvoc_objCreate_MemoryMulticastFabric((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) + +#define memorymulticastfabricCanCopy(pMemoryMulticastFabric) memorymulticastfabricCanCopy_DISPATCH(pMemoryMulticastFabric) +#define memorymulticastfabricCopyConstruct(pMemoryMulticastFabric, pCallContext, pParams) memorymulticastfabricCopyConstruct_DISPATCH(pMemoryMulticastFabric, pCallContext, pParams) +#define memorymulticastfabricIsReady(pMemoryMulticastFabric, bCopyConstructorContext) memorymulticastfabricIsReady_DISPATCH(pMemoryMulticastFabric, bCopyConstructorContext) +#define memorymulticastfabricControl(pMemoryMulticastFabric, pCallContext, pParams) memorymulticastfabricControl_DISPATCH(pMemoryMulticastFabric, pCallContext, pParams) +#define memorymulticastfabricControl_Prologue(pMemoryMulticastFabric, pCallContext, pParams) memorymulticastfabricControl_Prologue_DISPATCH(pMemoryMulticastFabric, pCallContext, pParams) +#define memorymulticastfabricIsGpuMapAllowed(pMemoryMulticastFabric, pGpu) memorymulticastfabricIsGpuMapAllowed_DISPATCH(pMemoryMulticastFabric, pGpu) +#define memorymulticastfabricGetMapAddrSpace(pMemoryMulticastFabric, pCallContext, mapFlags, pAddrSpace) memorymulticastfabricGetMapAddrSpace_DISPATCH(pMemoryMulticastFabric, pCallContext, mapFlags, pAddrSpace) +#define memorymulticastfabricCtrlGetInfo(pMemoryMulticastFabric, pParams) memorymulticastfabricCtrlGetInfo_DISPATCH(pMemoryMulticastFabric, pParams) +#define memorymulticastfabricCtrlAttachMem(pMemoryMulticastFabric, pParams) memorymulticastfabricCtrlAttachMem_DISPATCH(pMemoryMulticastFabric, pParams) +#define memorymulticastfabricCtrlRegisterEvent(pMemoryMulticastFabric, pParams) memorymulticastfabricCtrlRegisterEvent_DISPATCH(pMemoryMulticastFabric, pParams) +#define memorymulticastfabricCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) memorymulticastfabricCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define memorymulticastfabricUnmap(pMemory, pCallContext, pCpuMapping) memorymulticastfabricUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) +#define memorymulticastfabricGetMemInterMapParams(pMemory, pParams) memorymulticastfabricGetMemInterMapParams_DISPATCH(pMemory, pParams) +#define memorymulticastfabricGetMemoryMappingDescriptor(pMemory, ppMemDesc) memorymulticastfabricGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) +#define memorymulticastfabricShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) memorymulticastfabricShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define memorymulticastfabricControlFilter(pResource, pCallContext, pParams) memorymulticastfabricControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define memorymulticastfabricAddAdditionalDependants(pClient, pResource, pReference) memorymulticastfabricAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define memorymulticastfabricGetRefCount(pResource) memorymulticastfabricGetRefCount_DISPATCH(pResource) +#define memorymulticastfabricMapTo(pResource, pParams) memorymulticastfabricMapTo_DISPATCH(pResource, pParams) +#define memorymulticastfabricCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) memorymulticastfabricCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define memorymulticastfabricPreDestruct(pResource) memorymulticastfabricPreDestruct_DISPATCH(pResource) +#define memorymulticastfabricIsDuplicate(pMemory, hMemory, pDuplicate) memorymulticastfabricIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) +#define memorymulticastfabricUnmapFrom(pResource, pParams) memorymulticastfabricUnmapFrom_DISPATCH(pResource, pParams) +#define memorymulticastfabricControl_Epilogue(pResource, pCallContext, pParams) memorymulticastfabricControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define memorymulticastfabricControlLookup(pResource, pParams, ppEntry) memorymulticastfabricControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define memorymulticastfabricMap(pMemory, pCallContext, pParams, pCpuMapping) memorymulticastfabricMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) +#define memorymulticastfabricAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) memorymulticastfabricAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +NvBool memorymulticastfabricCanCopy_IMPL(struct MemoryMulticastFabric *pMemoryMulticastFabric); + +static inline NvBool memorymulticastfabricCanCopy_DISPATCH(struct MemoryMulticastFabric *pMemoryMulticastFabric) { + return pMemoryMulticastFabric->__memorymulticastfabricCanCopy__(pMemoryMulticastFabric); +} + +NV_STATUS memorymulticastfabricCopyConstruct_IMPL(struct MemoryMulticastFabric *pMemoryMulticastFabric, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); + +static inline NV_STATUS memorymulticastfabricCopyConstruct_DISPATCH(struct MemoryMulticastFabric *pMemoryMulticastFabric, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { + return pMemoryMulticastFabric->__memorymulticastfabricCopyConstruct__(pMemoryMulticastFabric, pCallContext, pParams); +} + +NV_STATUS memorymulticastfabricIsReady_IMPL(struct MemoryMulticastFabric *pMemoryMulticastFabric, NvBool bCopyConstructorContext); + +static inline NV_STATUS memorymulticastfabricIsReady_DISPATCH(struct MemoryMulticastFabric *pMemoryMulticastFabric, NvBool bCopyConstructorContext) { + return pMemoryMulticastFabric->__memorymulticastfabricIsReady__(pMemoryMulticastFabric, bCopyConstructorContext); +} + +NV_STATUS memorymulticastfabricControl_IMPL(struct MemoryMulticastFabric *pMemoryMulticastFabric, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); + +static inline NV_STATUS memorymulticastfabricControl_DISPATCH(struct MemoryMulticastFabric *pMemoryMulticastFabric, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pMemoryMulticastFabric->__memorymulticastfabricControl__(pMemoryMulticastFabric, pCallContext, pParams); +} + +NV_STATUS memorymulticastfabricControl_Prologue_IMPL(struct MemoryMulticastFabric *pMemoryMulticastFabric, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); + +static inline NV_STATUS memorymulticastfabricControl_Prologue_DISPATCH(struct MemoryMulticastFabric *pMemoryMulticastFabric, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pMemoryMulticastFabric->__memorymulticastfabricControl_Prologue__(pMemoryMulticastFabric, pCallContext, pParams); +} + +NvBool memorymulticastfabricIsGpuMapAllowed_IMPL(struct MemoryMulticastFabric *pMemoryMulticastFabric, struct OBJGPU *pGpu); + +static inline NvBool memorymulticastfabricIsGpuMapAllowed_DISPATCH(struct MemoryMulticastFabric *pMemoryMulticastFabric, struct OBJGPU *pGpu) { + return pMemoryMulticastFabric->__memorymulticastfabricIsGpuMapAllowed__(pMemoryMulticastFabric, pGpu); +} + +NV_STATUS memorymulticastfabricGetMapAddrSpace_IMPL(struct MemoryMulticastFabric *pMemoryMulticastFabric, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace); + +static inline NV_STATUS memorymulticastfabricGetMapAddrSpace_DISPATCH(struct MemoryMulticastFabric *pMemoryMulticastFabric, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemoryMulticastFabric->__memorymulticastfabricGetMapAddrSpace__(pMemoryMulticastFabric, pCallContext, mapFlags, pAddrSpace); +} + +NV_STATUS memorymulticastfabricCtrlGetInfo_IMPL(struct MemoryMulticastFabric *pMemoryMulticastFabric, NV00FD_CTRL_GET_INFO_PARAMS *pParams); + +static inline NV_STATUS memorymulticastfabricCtrlGetInfo_DISPATCH(struct MemoryMulticastFabric *pMemoryMulticastFabric, NV00FD_CTRL_GET_INFO_PARAMS *pParams) { + return pMemoryMulticastFabric->__memorymulticastfabricCtrlGetInfo__(pMemoryMulticastFabric, pParams); +} + +NV_STATUS memorymulticastfabricCtrlAttachMem_IMPL(struct MemoryMulticastFabric *pMemoryMulticastFabric, NV00FD_CTRL_ATTACH_MEM_PARAMS *pParams); + +static inline NV_STATUS memorymulticastfabricCtrlAttachMem_DISPATCH(struct MemoryMulticastFabric *pMemoryMulticastFabric, NV00FD_CTRL_ATTACH_MEM_PARAMS *pParams) { + return pMemoryMulticastFabric->__memorymulticastfabricCtrlAttachMem__(pMemoryMulticastFabric, pParams); +} + +NV_STATUS memorymulticastfabricCtrlRegisterEvent_IMPL(struct MemoryMulticastFabric *pMemoryMulticastFabric, NV00FD_CTRL_REGISTER_EVENT_PARAMS *pParams); + +static inline NV_STATUS memorymulticastfabricCtrlRegisterEvent_DISPATCH(struct MemoryMulticastFabric *pMemoryMulticastFabric, NV00FD_CTRL_REGISTER_EVENT_PARAMS *pParams) { + return pMemoryMulticastFabric->__memorymulticastfabricCtrlRegisterEvent__(pMemoryMulticastFabric, pParams); +} + +static inline NV_STATUS memorymulticastfabricCheckMemInterUnmap_DISPATCH(struct MemoryMulticastFabric *pMemory, NvBool bSubdeviceHandleProvided) { + return pMemory->__memorymulticastfabricCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); +} + +static inline NV_STATUS memorymulticastfabricUnmap_DISPATCH(struct MemoryMulticastFabric *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pMemory->__memorymulticastfabricUnmap__(pMemory, pCallContext, pCpuMapping); +} + +static inline NV_STATUS memorymulticastfabricGetMemInterMapParams_DISPATCH(struct MemoryMulticastFabric *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pMemory->__memorymulticastfabricGetMemInterMapParams__(pMemory, pParams); +} + +static inline NV_STATUS memorymulticastfabricGetMemoryMappingDescriptor_DISPATCH(struct MemoryMulticastFabric *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return pMemory->__memorymulticastfabricGetMemoryMappingDescriptor__(pMemory, ppMemDesc); +} + +static inline NvBool memorymulticastfabricShareCallback_DISPATCH(struct MemoryMulticastFabric *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__memorymulticastfabricShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS memorymulticastfabricControlFilter_DISPATCH(struct MemoryMulticastFabric *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memorymulticastfabricControlFilter__(pResource, pCallContext, pParams); +} + +static inline void memorymulticastfabricAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct MemoryMulticastFabric *pResource, RsResourceRef *pReference) { + pResource->__memorymulticastfabricAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NvU32 memorymulticastfabricGetRefCount_DISPATCH(struct MemoryMulticastFabric *pResource) { + return pResource->__memorymulticastfabricGetRefCount__(pResource); +} + +static inline NV_STATUS memorymulticastfabricMapTo_DISPATCH(struct MemoryMulticastFabric *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__memorymulticastfabricMapTo__(pResource, pParams); +} + +static inline NV_STATUS memorymulticastfabricCheckCopyPermissions_DISPATCH(struct MemoryMulticastFabric *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { + return pMemory->__memorymulticastfabricCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); +} + +static inline void memorymulticastfabricPreDestruct_DISPATCH(struct MemoryMulticastFabric *pResource) { + pResource->__memorymulticastfabricPreDestruct__(pResource); +} + +static inline NV_STATUS memorymulticastfabricIsDuplicate_DISPATCH(struct MemoryMulticastFabric *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return pMemory->__memorymulticastfabricIsDuplicate__(pMemory, hMemory, pDuplicate); +} + +static inline NV_STATUS memorymulticastfabricUnmapFrom_DISPATCH(struct MemoryMulticastFabric *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__memorymulticastfabricUnmapFrom__(pResource, pParams); +} + +static inline void memorymulticastfabricControl_Epilogue_DISPATCH(struct MemoryMulticastFabric *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__memorymulticastfabricControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS memorymulticastfabricControlLookup_DISPATCH(struct MemoryMulticastFabric *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__memorymulticastfabricControlLookup__(pResource, pParams, ppEntry); +} + +static inline NV_STATUS memorymulticastfabricMap_DISPATCH(struct MemoryMulticastFabric *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { + return pMemory->__memorymulticastfabricMap__(pMemory, pCallContext, pParams, pCpuMapping); +} + +static inline NvBool memorymulticastfabricAccessCallback_DISPATCH(struct MemoryMulticastFabric *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return pResource->__memorymulticastfabricAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); +} + +NV_STATUS memorymulticastfabricConstruct_IMPL(struct MemoryMulticastFabric *arg_pMemoryMulticastFabric, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + +#define __nvoc_memorymulticastfabricConstruct(arg_pMemoryMulticastFabric, arg_pCallContext, arg_pParams) memorymulticastfabricConstruct_IMPL(arg_pMemoryMulticastFabric, arg_pCallContext, arg_pParams) +void memorymulticastfabricDestruct_IMPL(struct MemoryMulticastFabric *pMemoryMulticastFabric); + +#define __nvoc_memorymulticastfabricDestruct(pMemoryMulticastFabric) memorymulticastfabricDestruct_IMPL(pMemoryMulticastFabric) +#undef PRIVATE_FIELD + + +void memorymulticastfabricTeamSetupResponseCallback(OBJGPU *pGpu, + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pMessage); + +#endif // _MEMORYMULTICASTFABRIC_H_ + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_MEM_MULTICAST_FABRIC_NVOC_H_ diff --git a/src/nvidia/generated/g_mem_nvoc.c b/src/nvidia/generated/g_mem_nvoc.c index 70b77f205..e8987e1bf 100644 --- a/src/nvidia/generated/g_mem_nvoc.c +++ b/src/nvidia/generated/g_mem_nvoc.c @@ -84,6 +84,10 @@ const struct NVOC_CLASS_DEF __nvoc_class_def_Memory = /*pExportInfo=*/ &__nvoc_export_info_Memory }; +static NV_STATUS __nvoc_thunk_Memory_resIsDuplicate(struct RsResource *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) - __nvoc_rtti_Memory_RsResource.offset), hMemory, pDuplicate); +} + static NV_STATUS __nvoc_thunk_Memory_resControl(struct RsResource *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return memControl((struct Memory *)(((unsigned char *)pMemory) - __nvoc_rtti_Memory_RsResource.offset), pCallContext, pParams); } @@ -165,21 +169,6 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Memory[] { /* [0] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, -#else - /*pFunc=*/ (void (*)(void)) memCtrlCmdGetSurfacePartitionStrideLvm_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, - /*accessRight=*/0x0u, - /*methodId=*/ 0x410105u, - /*paramSize=*/ sizeof(NV0041_CTRL_GET_SURFACE_PARTITION_STRIDE_PARAMS), - /*pClassInfo=*/ &(__nvoc_class_def_Memory.classInfo), -#if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "memCtrlCmdGetSurfacePartitionStrideLvm" -#endif - }, - { /* [1] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) memCtrlCmdGetSurfaceInfoLvm_IMPL, #endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) @@ -192,7 +181,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Memory[] /*func=*/ "memCtrlCmdGetSurfaceInfoLvm" #endif }, - { /* [2] */ + { /* [1] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -207,7 +196,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Memory[] /*func=*/ "memCtrlCmdGetSurfaceCompressionCoverageLvm" #endif }, - { /* [3] */ + { /* [2] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -222,7 +211,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Memory[] /*func=*/ "memCtrlCmdSurfaceFlushGpuCache" #endif }, - { /* [4] */ + { /* [3] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -237,7 +226,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Memory[] /*func=*/ "memCtrlCmdGetMemPageSize" #endif }, - { /* [5] */ + { /* [4] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -252,7 +241,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Memory[] /*func=*/ "memCtrlCmdSetTag" #endif }, - { /* [6] */ + { /* [5] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -272,7 +261,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Memory[] const struct NVOC_EXPORT_INFO __nvoc_export_info_Memory = { - /*numEntries=*/ 7, + /*numEntries=*/ 6, /*pExportEntries=*/ __nvoc_exported_method_def_Memory }; @@ -309,6 +298,8 @@ __nvoc_ctor_Memory_exit: static void __nvoc_init_funcTable_Memory_1(Memory *pThis) { PORT_UNREFERENCED_VARIABLE(pThis); + pThis->__memIsDuplicate__ = &memIsDuplicate_IMPL; + pThis->__memGetMapAddrSpace__ = &memGetMapAddrSpace_IMPL; pThis->__memControl__ = &memControl_IMPL; @@ -327,12 +318,10 @@ static void __nvoc_init_funcTable_Memory_1(Memory *pThis) { pThis->__memIsReady__ = &memIsReady_IMPL; -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - pThis->__memCtrlCmdGetSurfaceCompressionCoverageLvm__ = &memCtrlCmdGetSurfaceCompressionCoverageLvm_IMPL; -#endif + pThis->__memIsGpuMapAllowed__ = &memIsGpuMapAllowed_0c883b; #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - pThis->__memCtrlCmdGetSurfacePartitionStrideLvm__ = &memCtrlCmdGetSurfacePartitionStrideLvm_IMPL; + pThis->__memCtrlCmdGetSurfaceCompressionCoverageLvm__ = &memCtrlCmdGetSurfaceCompressionCoverageLvm_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) @@ -355,6 +344,8 @@ static void __nvoc_init_funcTable_Memory_1(Memory *pThis) { pThis->__memCtrlCmdGetTag__ = &memCtrlCmdGetTag_IMPL; #endif + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__resIsDuplicate__ = &__nvoc_thunk_Memory_resIsDuplicate; + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__resControl__ = &__nvoc_thunk_Memory_resControl; pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__resMap__ = &__nvoc_thunk_Memory_resMap; diff --git a/src/nvidia/generated/g_mem_nvoc.h b/src/nvidia/generated/g_mem_nvoc.h index 9e59b16f9..e36eecfc5 100644 --- a/src/nvidia/generated/g_mem_nvoc.h +++ b/src/nvidia/generated/g_mem_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -149,6 +149,7 @@ struct Memory { struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; struct RmResource *__nvoc_pbase_RmResource; struct Memory *__nvoc_pbase_Memory; + NV_STATUS (*__memIsDuplicate__)(struct Memory *, NvHandle, NvBool *); NV_STATUS (*__memGetMapAddrSpace__)(struct Memory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); NV_STATUS (*__memControl__)(struct Memory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memMap__)(struct Memory *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -157,9 +158,9 @@ struct Memory { NV_STATUS (*__memCheckMemInterUnmap__)(struct Memory *, NvBool); NV_STATUS (*__memGetMemoryMappingDescriptor__)(struct Memory *, MEMORY_DESCRIPTOR **); NV_STATUS (*__memCheckCopyPermissions__)(struct Memory *, struct OBJGPU *, NvHandle); - NV_STATUS (*__memIsReady__)(struct Memory *); + NV_STATUS (*__memIsReady__)(struct Memory *, NvBool); + NvBool (*__memIsGpuMapAllowed__)(struct Memory *, struct OBJGPU *); NV_STATUS (*__memCtrlCmdGetSurfaceCompressionCoverageLvm__)(struct Memory *, NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS *); - NV_STATUS (*__memCtrlCmdGetSurfacePartitionStrideLvm__)(struct Memory *, NV0041_CTRL_GET_SURFACE_PARTITION_STRIDE_PARAMS *); NV_STATUS (*__memCtrlCmdGetSurfaceInfoLvm__)(struct Memory *, NV0041_CTRL_GET_SURFACE_INFO_PARAMS *); NV_STATUS (*__memCtrlCmdSurfaceFlushGpuCache__)(struct Memory *, NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_PARAMS *); NV_STATUS (*__memCtrlCmdGetMemPageSize__)(struct Memory *, NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS *); @@ -234,6 +235,7 @@ NV_STATUS __nvoc_objCreate_Memory(Memory**, Dynamic*, NvU32, CALL_CONTEXT * arg_ #define __objCreate_Memory(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ __nvoc_objCreate_Memory((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) +#define memIsDuplicate(pMemory, hMemory, pDuplicate) memIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) #define memGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) memGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) #define memControl(pMemory, pCallContext, pParams) memControl_DISPATCH(pMemory, pCallContext, pParams) #define memMap(pMemory, pCallContext, pParams, pCpuMapping) memMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) @@ -242,9 +244,9 @@ NV_STATUS __nvoc_objCreate_Memory(Memory**, Dynamic*, NvU32, CALL_CONTEXT * arg_ #define memCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) memCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) #define memGetMemoryMappingDescriptor(pMemory, ppMemDesc) memGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) #define memCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) memCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) -#define memIsReady(pMemory) memIsReady_DISPATCH(pMemory) +#define memIsReady(pMemory, bCopyConstructorContext) memIsReady_DISPATCH(pMemory, bCopyConstructorContext) +#define memIsGpuMapAllowed(pMemory, pGpu) memIsGpuMapAllowed_DISPATCH(pMemory, pGpu) #define memCtrlCmdGetSurfaceCompressionCoverageLvm(pMemory, pParams) memCtrlCmdGetSurfaceCompressionCoverageLvm_DISPATCH(pMemory, pParams) -#define memCtrlCmdGetSurfacePartitionStrideLvm(pMemory, pParams) memCtrlCmdGetSurfacePartitionStrideLvm_DISPATCH(pMemory, pParams) #define memCtrlCmdGetSurfaceInfoLvm(pMemory, pSurfaceInfoParams) memCtrlCmdGetSurfaceInfoLvm_DISPATCH(pMemory, pSurfaceInfoParams) #define memCtrlCmdSurfaceFlushGpuCache(pMemory, pCacheFlushParams) memCtrlCmdSurfaceFlushGpuCache_DISPATCH(pMemory, pCacheFlushParams) #define memCtrlCmdGetMemPageSize(pMemory, pPageSizeParams) memCtrlCmdGetMemPageSize_DISPATCH(pMemory, pPageSizeParams) @@ -262,6 +264,12 @@ NV_STATUS __nvoc_objCreate_Memory(Memory**, Dynamic*, NvU32, CALL_CONTEXT * arg_ #define memControl_Epilogue(pResource, pCallContext, pParams) memControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define memControlLookup(pResource, pParams, ppEntry) memControlLookup_DISPATCH(pResource, pParams, ppEntry) #define memAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) memAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +NV_STATUS memIsDuplicate_IMPL(struct Memory *pMemory, NvHandle hMemory, NvBool *pDuplicate); + +static inline NV_STATUS memIsDuplicate_DISPATCH(struct Memory *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return pMemory->__memIsDuplicate__(pMemory, hMemory, pDuplicate); +} + NV_STATUS memGetMapAddrSpace_IMPL(struct Memory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace); static inline NV_STATUS memGetMapAddrSpace_DISPATCH(struct Memory *pMemory, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -314,10 +322,18 @@ static inline NV_STATUS memCheckCopyPermissions_DISPATCH(struct Memory *pMemory, return pMemory->__memCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); } -NV_STATUS memIsReady_IMPL(struct Memory *pMemory); +NV_STATUS memIsReady_IMPL(struct Memory *pMemory, NvBool bCopyConstructorContext); -static inline NV_STATUS memIsReady_DISPATCH(struct Memory *pMemory) { - return pMemory->__memIsReady__(pMemory); +static inline NV_STATUS memIsReady_DISPATCH(struct Memory *pMemory, NvBool bCopyConstructorContext) { + return pMemory->__memIsReady__(pMemory, bCopyConstructorContext); +} + +static inline NvBool memIsGpuMapAllowed_0c883b(struct Memory *pMemory, struct OBJGPU *pGpu) { + return ((NvBool)(0 == 0)); +} + +static inline NvBool memIsGpuMapAllowed_DISPATCH(struct Memory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__memIsGpuMapAllowed__(pMemory, pGpu); } NV_STATUS memCtrlCmdGetSurfaceCompressionCoverageLvm_IMPL(struct Memory *pMemory, NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS *pParams); @@ -326,12 +342,6 @@ static inline NV_STATUS memCtrlCmdGetSurfaceCompressionCoverageLvm_DISPATCH(stru return pMemory->__memCtrlCmdGetSurfaceCompressionCoverageLvm__(pMemory, pParams); } -NV_STATUS memCtrlCmdGetSurfacePartitionStrideLvm_IMPL(struct Memory *pMemory, NV0041_CTRL_GET_SURFACE_PARTITION_STRIDE_PARAMS *pParams); - -static inline NV_STATUS memCtrlCmdGetSurfacePartitionStrideLvm_DISPATCH(struct Memory *pMemory, NV0041_CTRL_GET_SURFACE_PARTITION_STRIDE_PARAMS *pParams) { - return pMemory->__memCtrlCmdGetSurfacePartitionStrideLvm__(pMemory, pParams); -} - NV_STATUS memCtrlCmdGetSurfaceInfoLvm_IMPL(struct Memory *pMemory, NV0041_CTRL_GET_SURFACE_INFO_PARAMS *pSurfaceInfoParams); static inline NV_STATUS memCtrlCmdGetSurfaceInfoLvm_DISPATCH(struct Memory *pMemory, NV0041_CTRL_GET_SURFACE_INFO_PARAMS *pSurfaceInfoParams) { @@ -411,8 +421,10 @@ static inline NvBool memAccessCallback_DISPATCH(struct Memory *pResource, struct } NV_STATUS memConstruct_IMPL(struct Memory *arg_pMemory, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_memConstruct(arg_pMemory, arg_pCallContext, arg_pParams) memConstruct_IMPL(arg_pMemory, arg_pCallContext, arg_pParams) NV_STATUS memCopyConstruct_IMPL(struct Memory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); + #ifdef __nvoc_mem_h_disabled static inline NV_STATUS memCopyConstruct(struct Memory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { NV_ASSERT_FAILED_PRECOMP("Memory was disabled!"); @@ -423,8 +435,10 @@ static inline NV_STATUS memCopyConstruct(struct Memory *pMemory, CALL_CONTEXT *p #endif //__nvoc_mem_h_disabled void memDestruct_IMPL(struct Memory *pMemory); + #define __nvoc_memDestruct(pMemory) memDestruct_IMPL(pMemory) NV_STATUS memConstructCommon_IMPL(struct Memory *pMemory, NvU32 categoryClassId, NvU32 flags, MEMORY_DESCRIPTOR *pMemDesc, NvU32 heapOwner, struct Heap *pHeap, NvU32 attr, NvU32 attr2, NvU32 Pitch, NvU32 type, NvU32 tag, HWRESOURCE_INFO *pHwResource); + #ifdef __nvoc_mem_h_disabled static inline NV_STATUS memConstructCommon(struct Memory *pMemory, NvU32 categoryClassId, NvU32 flags, MEMORY_DESCRIPTOR *pMemDesc, NvU32 heapOwner, struct Heap *pHeap, NvU32 attr, NvU32 attr2, NvU32 Pitch, NvU32 type, NvU32 tag, HWRESOURCE_INFO *pHwResource) { NV_ASSERT_FAILED_PRECOMP("Memory was disabled!"); @@ -435,6 +449,7 @@ static inline NV_STATUS memConstructCommon(struct Memory *pMemory, NvU32 categor #endif //__nvoc_mem_h_disabled void memDestructCommon_IMPL(struct Memory *pMemory); + #ifdef __nvoc_mem_h_disabled static inline void memDestructCommon(struct Memory *pMemory) { NV_ASSERT_FAILED_PRECOMP("Memory was disabled!"); @@ -444,8 +459,10 @@ static inline void memDestructCommon(struct Memory *pMemory) { #endif //__nvoc_mem_h_disabled NV_STATUS memCreateMemDesc_IMPL(struct OBJGPU *pGpu, MEMORY_DESCRIPTOR **ppMemDesc, NV_ADDRESS_SPACE addrSpace, NvU64 FBOffset, NvU64 length, NvU32 attr, NvU32 attr2); + #define memCreateMemDesc(pGpu, ppMemDesc, addrSpace, FBOffset, length, attr, attr2) memCreateMemDesc_IMPL(pGpu, ppMemDesc, addrSpace, FBOffset, length, attr, attr2) NV_STATUS memCreateKernelMapping_IMPL(struct Memory *pMemory, NvU32 Protect, NvBool bClear); + #ifdef __nvoc_mem_h_disabled static inline NV_STATUS memCreateKernelMapping(struct Memory *pMemory, NvU32 Protect, NvBool bClear) { NV_ASSERT_FAILED_PRECOMP("Memory was disabled!"); @@ -456,10 +473,13 @@ static inline NV_STATUS memCreateKernelMapping(struct Memory *pMemory, NvU32 Pro #endif //__nvoc_mem_h_disabled NV_STATUS memGetByHandle_IMPL(struct RsClient *pClient, NvHandle hMemory, struct Memory **ppMemory); + #define memGetByHandle(pClient, hMemory, ppMemory) memGetByHandle_IMPL(pClient, hMemory, ppMemory) NV_STATUS memGetByHandleAndDevice_IMPL(struct RsClient *pClient, NvHandle hMemory, NvHandle hDevice, struct Memory **ppMemory); + #define memGetByHandleAndDevice(pClient, hMemory, hDevice, ppMemory) memGetByHandleAndDevice_IMPL(pClient, hMemory, hDevice, ppMemory) NV_STATUS memGetByHandleAndGroupedGpu_IMPL(struct RsClient *pClient, NvHandle hMemory, struct OBJGPU *pGpu, struct Memory **ppMemory); + #define memGetByHandleAndGroupedGpu(pClient, hMemory, pGpu, ppMemory) memGetByHandleAndGroupedGpu_IMPL(pClient, hMemory, pGpu, ppMemory) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_mig_config_session_nvoc.c b/src/nvidia/generated/g_mig_config_session_nvoc.c index e2555681e..175098c4d 100644 --- a/src/nvidia/generated/g_mig_config_session_nvoc.c +++ b/src/nvidia/generated/g_mig_config_session_nvoc.c @@ -140,6 +140,10 @@ static NV_STATUS __nvoc_thunk_RsResource_migconfigsessionUnmapFrom(struct MIGCon return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_migconfigsessionIsDuplicate(struct MIGConfigSession *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_migconfigsessionControl_Epilogue(struct MIGConfigSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RmResource.offset), pCallContext, pParams); } @@ -223,6 +227,8 @@ static void __nvoc_init_funcTable_MIGConfigSession_1(MIGConfigSession *pThis) { pThis->__migconfigsessionUnmapFrom__ = &__nvoc_thunk_RsResource_migconfigsessionUnmapFrom; + pThis->__migconfigsessionIsDuplicate__ = &__nvoc_thunk_RsResource_migconfigsessionIsDuplicate; + pThis->__migconfigsessionControl_Epilogue__ = &__nvoc_thunk_RmResource_migconfigsessionControl_Epilogue; pThis->__migconfigsessionControlLookup__ = &__nvoc_thunk_RsResource_migconfigsessionControlLookup; diff --git a/src/nvidia/generated/g_mig_config_session_nvoc.h b/src/nvidia/generated/g_mig_config_session_nvoc.h index 5ce5f3adb..28304fd44 100644 --- a/src/nvidia/generated/g_mig_config_session_nvoc.h +++ b/src/nvidia/generated/g_mig_config_session_nvoc.h @@ -79,6 +79,7 @@ struct MIGConfigSession { NV_STATUS (*__migconfigsessionMapTo__)(struct MIGConfigSession *, RS_RES_MAP_TO_PARAMS *); void (*__migconfigsessionPreDestruct__)(struct MIGConfigSession *); NV_STATUS (*__migconfigsessionUnmapFrom__)(struct MIGConfigSession *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__migconfigsessionIsDuplicate__)(struct MIGConfigSession *, NvHandle, NvBool *); void (*__migconfigsessionControl_Epilogue__)(struct MIGConfigSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__migconfigsessionControlLookup__)(struct MIGConfigSession *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__migconfigsessionMap__)(struct MIGConfigSession *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -128,6 +129,7 @@ NV_STATUS __nvoc_objCreate_MIGConfigSession(MIGConfigSession**, Dynamic*, NvU32, #define migconfigsessionMapTo(pResource, pParams) migconfigsessionMapTo_DISPATCH(pResource, pParams) #define migconfigsessionPreDestruct(pResource) migconfigsessionPreDestruct_DISPATCH(pResource) #define migconfigsessionUnmapFrom(pResource, pParams) migconfigsessionUnmapFrom_DISPATCH(pResource, pParams) +#define migconfigsessionIsDuplicate(pResource, hMemory, pDuplicate) migconfigsessionIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define migconfigsessionControl_Epilogue(pResource, pCallContext, pParams) migconfigsessionControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define migconfigsessionControlLookup(pResource, pParams, ppEntry) migconfigsessionControlLookup_DISPATCH(pResource, pParams, ppEntry) #define migconfigsessionMap(pResource, pCallContext, pParams, pCpuMapping) migconfigsessionMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) @@ -188,6 +190,10 @@ static inline NV_STATUS migconfigsessionUnmapFrom_DISPATCH(struct MIGConfigSessi return pResource->__migconfigsessionUnmapFrom__(pResource, pParams); } +static inline NV_STATUS migconfigsessionIsDuplicate_DISPATCH(struct MIGConfigSession *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__migconfigsessionIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void migconfigsessionControl_Epilogue_DISPATCH(struct MIGConfigSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__migconfigsessionControl_Epilogue__(pResource, pCallContext, pParams); } @@ -205,8 +211,10 @@ static inline NvBool migconfigsessionAccessCallback_DISPATCH(struct MIGConfigSes } NV_STATUS migconfigsessionConstruct_IMPL(struct MIGConfigSession *arg_pMIGConfigSession, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_migconfigsessionConstruct(arg_pMIGConfigSession, arg_pCallContext, arg_pParams) migconfigsessionConstruct_IMPL(arg_pMIGConfigSession, arg_pCallContext, arg_pParams) void migconfigsessionDestruct_IMPL(struct MIGConfigSession *pMIGConfigSession); + #define __nvoc_migconfigsessionDestruct(pMIGConfigSession) migconfigsessionDestruct_IMPL(pMIGConfigSession) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_mig_monitor_session_nvoc.c b/src/nvidia/generated/g_mig_monitor_session_nvoc.c index 234ef2eeb..d27790536 100644 --- a/src/nvidia/generated/g_mig_monitor_session_nvoc.c +++ b/src/nvidia/generated/g_mig_monitor_session_nvoc.c @@ -140,6 +140,10 @@ static NV_STATUS __nvoc_thunk_RsResource_migmonitorsessionUnmapFrom(struct MIGMo return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_migmonitorsessionIsDuplicate(struct MIGMonitorSession *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_migmonitorsessionControl_Epilogue(struct MIGMonitorSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RmResource.offset), pCallContext, pParams); } @@ -223,6 +227,8 @@ static void __nvoc_init_funcTable_MIGMonitorSession_1(MIGMonitorSession *pThis) pThis->__migmonitorsessionUnmapFrom__ = &__nvoc_thunk_RsResource_migmonitorsessionUnmapFrom; + pThis->__migmonitorsessionIsDuplicate__ = &__nvoc_thunk_RsResource_migmonitorsessionIsDuplicate; + pThis->__migmonitorsessionControl_Epilogue__ = &__nvoc_thunk_RmResource_migmonitorsessionControl_Epilogue; pThis->__migmonitorsessionControlLookup__ = &__nvoc_thunk_RsResource_migmonitorsessionControlLookup; diff --git a/src/nvidia/generated/g_mig_monitor_session_nvoc.h b/src/nvidia/generated/g_mig_monitor_session_nvoc.h index 2670536ec..1cf41dc39 100644 --- a/src/nvidia/generated/g_mig_monitor_session_nvoc.h +++ b/src/nvidia/generated/g_mig_monitor_session_nvoc.h @@ -80,6 +80,7 @@ struct MIGMonitorSession { NV_STATUS (*__migmonitorsessionMapTo__)(struct MIGMonitorSession *, RS_RES_MAP_TO_PARAMS *); void (*__migmonitorsessionPreDestruct__)(struct MIGMonitorSession *); NV_STATUS (*__migmonitorsessionUnmapFrom__)(struct MIGMonitorSession *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__migmonitorsessionIsDuplicate__)(struct MIGMonitorSession *, NvHandle, NvBool *); void (*__migmonitorsessionControl_Epilogue__)(struct MIGMonitorSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__migmonitorsessionControlLookup__)(struct MIGMonitorSession *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__migmonitorsessionMap__)(struct MIGMonitorSession *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -129,6 +130,7 @@ NV_STATUS __nvoc_objCreate_MIGMonitorSession(MIGMonitorSession**, Dynamic*, NvU3 #define migmonitorsessionMapTo(pResource, pParams) migmonitorsessionMapTo_DISPATCH(pResource, pParams) #define migmonitorsessionPreDestruct(pResource) migmonitorsessionPreDestruct_DISPATCH(pResource) #define migmonitorsessionUnmapFrom(pResource, pParams) migmonitorsessionUnmapFrom_DISPATCH(pResource, pParams) +#define migmonitorsessionIsDuplicate(pResource, hMemory, pDuplicate) migmonitorsessionIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define migmonitorsessionControl_Epilogue(pResource, pCallContext, pParams) migmonitorsessionControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define migmonitorsessionControlLookup(pResource, pParams, ppEntry) migmonitorsessionControlLookup_DISPATCH(pResource, pParams, ppEntry) #define migmonitorsessionMap(pResource, pCallContext, pParams, pCpuMapping) migmonitorsessionMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) @@ -189,6 +191,10 @@ static inline NV_STATUS migmonitorsessionUnmapFrom_DISPATCH(struct MIGMonitorSes return pResource->__migmonitorsessionUnmapFrom__(pResource, pParams); } +static inline NV_STATUS migmonitorsessionIsDuplicate_DISPATCH(struct MIGMonitorSession *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__migmonitorsessionIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void migmonitorsessionControl_Epilogue_DISPATCH(struct MIGMonitorSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__migmonitorsessionControl_Epilogue__(pResource, pCallContext, pParams); } @@ -206,8 +212,10 @@ static inline NvBool migmonitorsessionAccessCallback_DISPATCH(struct MIGMonitorS } NV_STATUS migmonitorsessionConstruct_IMPL(struct MIGMonitorSession *arg_pMIGMonitorSession, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_migmonitorsessionConstruct(arg_pMIGMonitorSession, arg_pCallContext, arg_pParams) migmonitorsessionConstruct_IMPL(arg_pMIGMonitorSession, arg_pCallContext, arg_pParams) void migmonitorsessionDestruct_IMPL(struct MIGMonitorSession *pMIGMonitorSession); + #define __nvoc_migmonitorsessionDestruct(pMIGMonitorSession) migmonitorsessionDestruct_IMPL(pMIGMonitorSession) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_mmu_fault_buffer_nvoc.c b/src/nvidia/generated/g_mmu_fault_buffer_nvoc.c index a0c8417d1..ac08fd7de 100644 --- a/src/nvidia/generated/g_mmu_fault_buffer_nvoc.c +++ b/src/nvidia/generated/g_mmu_fault_buffer_nvoc.c @@ -207,6 +207,10 @@ static void __nvoc_thunk_RsResource_faultbufPreDestruct(struct MmuFaultBuffer *p resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MmuFaultBuffer_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_RsResource_faultbufIsDuplicate(struct MmuFaultBuffer *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MmuFaultBuffer_RsResource.offset), hMemory, pDuplicate); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_faultbufGetNotificationListPtr(struct MmuFaultBuffer *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_MmuFaultBuffer_Notifier.offset)); } @@ -404,6 +408,8 @@ static void __nvoc_init_funcTable_MmuFaultBuffer_1(MmuFaultBuffer *pThis) { pThis->__faultbufPreDestruct__ = &__nvoc_thunk_RsResource_faultbufPreDestruct; + pThis->__faultbufIsDuplicate__ = &__nvoc_thunk_RsResource_faultbufIsDuplicate; + pThis->__faultbufGetNotificationListPtr__ = &__nvoc_thunk_Notifier_faultbufGetNotificationListPtr; pThis->__faultbufGetNotificationShare__ = &__nvoc_thunk_Notifier_faultbufGetNotificationShare; diff --git a/src/nvidia/generated/g_mmu_fault_buffer_nvoc.h b/src/nvidia/generated/g_mmu_fault_buffer_nvoc.h index 0cb36e69d..7befe639f 100644 --- a/src/nvidia/generated/g_mmu_fault_buffer_nvoc.h +++ b/src/nvidia/generated/g_mmu_fault_buffer_nvoc.h @@ -88,6 +88,7 @@ struct MmuFaultBuffer { NV_STATUS (*__faultbufUnregisterEvent__)(struct MmuFaultBuffer *, NvHandle, NvHandle, NvHandle, NvHandle); NvBool (*__faultbufCanCopy__)(struct MmuFaultBuffer *); void (*__faultbufPreDestruct__)(struct MmuFaultBuffer *); + NV_STATUS (*__faultbufIsDuplicate__)(struct MmuFaultBuffer *, NvHandle, NvBool *); PEVENTNOTIFICATION *(*__faultbufGetNotificationListPtr__)(struct MmuFaultBuffer *); struct NotifShare *(*__faultbufGetNotificationShare__)(struct MmuFaultBuffer *); NvBool (*__faultbufAccessCallback__)(struct MmuFaultBuffer *, struct RsClient *, void *, RsAccessRight); @@ -149,6 +150,7 @@ NV_STATUS __nvoc_objCreate_MmuFaultBuffer(MmuFaultBuffer**, Dynamic*, NvU32, str #define faultbufUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) faultbufUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define faultbufCanCopy(pResource) faultbufCanCopy_DISPATCH(pResource) #define faultbufPreDestruct(pResource) faultbufPreDestruct_DISPATCH(pResource) +#define faultbufIsDuplicate(pResource, hMemory, pDuplicate) faultbufIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define faultbufGetNotificationListPtr(pNotifier) faultbufGetNotificationListPtr_DISPATCH(pNotifier) #define faultbufGetNotificationShare(pNotifier) faultbufGetNotificationShare_DISPATCH(pNotifier) #define faultbufAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) faultbufAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) @@ -278,6 +280,10 @@ static inline void faultbufPreDestruct_DISPATCH(struct MmuFaultBuffer *pResource pResource->__faultbufPreDestruct__(pResource); } +static inline NV_STATUS faultbufIsDuplicate_DISPATCH(struct MmuFaultBuffer *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__faultbufIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline PEVENTNOTIFICATION *faultbufGetNotificationListPtr_DISPATCH(struct MmuFaultBuffer *pNotifier) { return pNotifier->__faultbufGetNotificationListPtr__(pNotifier); } @@ -291,8 +297,10 @@ static inline NvBool faultbufAccessCallback_DISPATCH(struct MmuFaultBuffer *pRes } NV_STATUS faultbufConstruct_IMPL(struct MmuFaultBuffer *arg_pMmuFaultBuffer, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_faultbufConstruct(arg_pMmuFaultBuffer, arg_pCallContext, arg_pParams) faultbufConstruct_IMPL(arg_pMmuFaultBuffer, arg_pCallContext, arg_pParams) void faultbufDestruct_IMPL(struct MmuFaultBuffer *pMmuFaultBuffer); + #define __nvoc_faultbufDestruct(pMmuFaultBuffer) faultbufDestruct_IMPL(pMmuFaultBuffer) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_mps_api_nvoc.c b/src/nvidia/generated/g_mps_api_nvoc.c index 8a0ae1fe4..225f873b8 100644 --- a/src/nvidia/generated/g_mps_api_nvoc.c +++ b/src/nvidia/generated/g_mps_api_nvoc.c @@ -140,6 +140,10 @@ static NV_STATUS __nvoc_thunk_RsResource_mpsApiUnmapFrom(struct MpsApi *pResourc return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_mpsApiIsDuplicate(struct MpsApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_mpsApiControl_Epilogue(struct MpsApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RmResource.offset), pCallContext, pParams); } @@ -223,6 +227,8 @@ static void __nvoc_init_funcTable_MpsApi_1(MpsApi *pThis) { pThis->__mpsApiUnmapFrom__ = &__nvoc_thunk_RsResource_mpsApiUnmapFrom; + pThis->__mpsApiIsDuplicate__ = &__nvoc_thunk_RsResource_mpsApiIsDuplicate; + pThis->__mpsApiControl_Epilogue__ = &__nvoc_thunk_RmResource_mpsApiControl_Epilogue; pThis->__mpsApiControlLookup__ = &__nvoc_thunk_RsResource_mpsApiControlLookup; diff --git a/src/nvidia/generated/g_mps_api_nvoc.h b/src/nvidia/generated/g_mps_api_nvoc.h index f8415ffaa..863d26394 100644 --- a/src/nvidia/generated/g_mps_api_nvoc.h +++ b/src/nvidia/generated/g_mps_api_nvoc.h @@ -84,6 +84,7 @@ struct MpsApi { NV_STATUS (*__mpsApiMapTo__)(struct MpsApi *, RS_RES_MAP_TO_PARAMS *); void (*__mpsApiPreDestruct__)(struct MpsApi *); NV_STATUS (*__mpsApiUnmapFrom__)(struct MpsApi *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__mpsApiIsDuplicate__)(struct MpsApi *, NvHandle, NvBool *); void (*__mpsApiControl_Epilogue__)(struct MpsApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__mpsApiControlLookup__)(struct MpsApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__mpsApiMap__)(struct MpsApi *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -132,6 +133,7 @@ NV_STATUS __nvoc_objCreate_MpsApi(MpsApi**, Dynamic*, NvU32, CALL_CONTEXT * arg_ #define mpsApiMapTo(pResource, pParams) mpsApiMapTo_DISPATCH(pResource, pParams) #define mpsApiPreDestruct(pResource) mpsApiPreDestruct_DISPATCH(pResource) #define mpsApiUnmapFrom(pResource, pParams) mpsApiUnmapFrom_DISPATCH(pResource, pParams) +#define mpsApiIsDuplicate(pResource, hMemory, pDuplicate) mpsApiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define mpsApiControl_Epilogue(pResource, pCallContext, pParams) mpsApiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define mpsApiControlLookup(pResource, pParams, ppEntry) mpsApiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define mpsApiMap(pResource, pCallContext, pParams, pCpuMapping) mpsApiMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) @@ -192,6 +194,10 @@ static inline NV_STATUS mpsApiUnmapFrom_DISPATCH(struct MpsApi *pResource, RS_RE return pResource->__mpsApiUnmapFrom__(pResource, pParams); } +static inline NV_STATUS mpsApiIsDuplicate_DISPATCH(struct MpsApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__mpsApiIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void mpsApiControl_Epilogue_DISPATCH(struct MpsApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__mpsApiControl_Epilogue__(pResource, pCallContext, pParams); } @@ -209,8 +215,10 @@ static inline NvBool mpsApiAccessCallback_DISPATCH(struct MpsApi *pResource, str } NV_STATUS mpsApiConstruct_IMPL(struct MpsApi *arg_pMpsApi, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_mpsApiConstruct(arg_pMpsApi, arg_pCallContext, arg_pParams) mpsApiConstruct_IMPL(arg_pMpsApi, arg_pCallContext, arg_pParams) void mpsApiDestruct_IMPL(struct MpsApi *pMpsApi); + #define __nvoc_mpsApiDestruct(pMpsApi) mpsApiDestruct_IMPL(pMpsApi) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_no_device_mem_nvoc.c b/src/nvidia/generated/g_no_device_mem_nvoc.c index 245dfdfd3..d288bb366 100644 --- a/src/nvidia/generated/g_no_device_mem_nvoc.c +++ b/src/nvidia/generated/g_no_device_mem_nvoc.c @@ -141,12 +141,16 @@ static NV_STATUS __nvoc_thunk_RmResource_nodevicememControl_Prologue(struct NoDe return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RmResource.offset), pCallContext, pParams); } +static NvBool __nvoc_thunk_Memory_nodevicememIsGpuMapAllowed(struct NoDeviceMemory *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_NoDeviceMemory_Memory.offset), pGpu); +} + static NvBool __nvoc_thunk_RsResource_nodevicememCanCopy(struct NoDeviceMemory *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_Memory_nodevicememIsReady(struct NoDeviceMemory *pMemory) { - return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_NoDeviceMemory_Memory.offset)); +static NV_STATUS __nvoc_thunk_Memory_nodevicememIsReady(struct NoDeviceMemory *pMemory, NvBool bCopyConstructorContext) { + return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_NoDeviceMemory_Memory.offset), bCopyConstructorContext); } static NV_STATUS __nvoc_thunk_Memory_nodevicememCheckCopyPermissions(struct NoDeviceMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { @@ -157,6 +161,10 @@ static void __nvoc_thunk_RsResource_nodevicememPreDestruct(struct NoDeviceMemory resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_Memory_nodevicememIsDuplicate(struct NoDeviceMemory *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_NoDeviceMemory_Memory.offset), hMemory, pDuplicate); +} + static NV_STATUS __nvoc_thunk_RsResource_nodevicememUnmapFrom(struct NoDeviceMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RsResource.offset), pParams); } @@ -242,6 +250,8 @@ static void __nvoc_init_funcTable_NoDeviceMemory_1(NoDeviceMemory *pThis) { pThis->__nodevicememControl_Prologue__ = &__nvoc_thunk_RmResource_nodevicememControl_Prologue; + pThis->__nodevicememIsGpuMapAllowed__ = &__nvoc_thunk_Memory_nodevicememIsGpuMapAllowed; + pThis->__nodevicememCanCopy__ = &__nvoc_thunk_RsResource_nodevicememCanCopy; pThis->__nodevicememIsReady__ = &__nvoc_thunk_Memory_nodevicememIsReady; @@ -250,6 +260,8 @@ static void __nvoc_init_funcTable_NoDeviceMemory_1(NoDeviceMemory *pThis) { pThis->__nodevicememPreDestruct__ = &__nvoc_thunk_RsResource_nodevicememPreDestruct; + pThis->__nodevicememIsDuplicate__ = &__nvoc_thunk_Memory_nodevicememIsDuplicate; + pThis->__nodevicememUnmapFrom__ = &__nvoc_thunk_RsResource_nodevicememUnmapFrom; pThis->__nodevicememControl_Epilogue__ = &__nvoc_thunk_RmResource_nodevicememControl_Epilogue; diff --git a/src/nvidia/generated/g_no_device_mem_nvoc.h b/src/nvidia/generated/g_no_device_mem_nvoc.h index 83904f607..3f9562b30 100644 --- a/src/nvidia/generated/g_no_device_mem_nvoc.h +++ b/src/nvidia/generated/g_no_device_mem_nvoc.h @@ -67,10 +67,12 @@ struct NoDeviceMemory { NvU32 (*__nodevicememGetRefCount__)(struct NoDeviceMemory *); NV_STATUS (*__nodevicememMapTo__)(struct NoDeviceMemory *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__nodevicememControl_Prologue__)(struct NoDeviceMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__nodevicememIsGpuMapAllowed__)(struct NoDeviceMemory *, struct OBJGPU *); NvBool (*__nodevicememCanCopy__)(struct NoDeviceMemory *); - NV_STATUS (*__nodevicememIsReady__)(struct NoDeviceMemory *); + NV_STATUS (*__nodevicememIsReady__)(struct NoDeviceMemory *, NvBool); NV_STATUS (*__nodevicememCheckCopyPermissions__)(struct NoDeviceMemory *, struct OBJGPU *, NvHandle); void (*__nodevicememPreDestruct__)(struct NoDeviceMemory *); + NV_STATUS (*__nodevicememIsDuplicate__)(struct NoDeviceMemory *, NvHandle, NvBool *); NV_STATUS (*__nodevicememUnmapFrom__)(struct NoDeviceMemory *, RS_RES_UNMAP_FROM_PARAMS *); void (*__nodevicememControl_Epilogue__)(struct NoDeviceMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__nodevicememControlLookup__)(struct NoDeviceMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); @@ -118,10 +120,12 @@ NV_STATUS __nvoc_objCreate_NoDeviceMemory(NoDeviceMemory**, Dynamic*, NvU32, CAL #define nodevicememGetRefCount(pResource) nodevicememGetRefCount_DISPATCH(pResource) #define nodevicememMapTo(pResource, pParams) nodevicememMapTo_DISPATCH(pResource, pParams) #define nodevicememControl_Prologue(pResource, pCallContext, pParams) nodevicememControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define nodevicememIsGpuMapAllowed(pMemory, pGpu) nodevicememIsGpuMapAllowed_DISPATCH(pMemory, pGpu) #define nodevicememCanCopy(pResource) nodevicememCanCopy_DISPATCH(pResource) -#define nodevicememIsReady(pMemory) nodevicememIsReady_DISPATCH(pMemory) +#define nodevicememIsReady(pMemory, bCopyConstructorContext) nodevicememIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define nodevicememCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) nodevicememCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) #define nodevicememPreDestruct(pResource) nodevicememPreDestruct_DISPATCH(pResource) +#define nodevicememIsDuplicate(pMemory, hMemory, pDuplicate) nodevicememIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) #define nodevicememUnmapFrom(pResource, pParams) nodevicememUnmapFrom_DISPATCH(pResource, pParams) #define nodevicememControl_Epilogue(pResource, pCallContext, pParams) nodevicememControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define nodevicememControlLookup(pResource, pParams, ppEntry) nodevicememControlLookup_DISPATCH(pResource, pParams, ppEntry) @@ -177,12 +181,16 @@ static inline NV_STATUS nodevicememControl_Prologue_DISPATCH(struct NoDeviceMemo return pResource->__nodevicememControl_Prologue__(pResource, pCallContext, pParams); } +static inline NvBool nodevicememIsGpuMapAllowed_DISPATCH(struct NoDeviceMemory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__nodevicememIsGpuMapAllowed__(pMemory, pGpu); +} + static inline NvBool nodevicememCanCopy_DISPATCH(struct NoDeviceMemory *pResource) { return pResource->__nodevicememCanCopy__(pResource); } -static inline NV_STATUS nodevicememIsReady_DISPATCH(struct NoDeviceMemory *pMemory) { - return pMemory->__nodevicememIsReady__(pMemory); +static inline NV_STATUS nodevicememIsReady_DISPATCH(struct NoDeviceMemory *pMemory, NvBool bCopyConstructorContext) { + return pMemory->__nodevicememIsReady__(pMemory, bCopyConstructorContext); } static inline NV_STATUS nodevicememCheckCopyPermissions_DISPATCH(struct NoDeviceMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { @@ -193,6 +201,10 @@ static inline void nodevicememPreDestruct_DISPATCH(struct NoDeviceMemory *pResou pResource->__nodevicememPreDestruct__(pResource); } +static inline NV_STATUS nodevicememIsDuplicate_DISPATCH(struct NoDeviceMemory *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return pMemory->__nodevicememIsDuplicate__(pMemory, hMemory, pDuplicate); +} + static inline NV_STATUS nodevicememUnmapFrom_DISPATCH(struct NoDeviceMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return pResource->__nodevicememUnmapFrom__(pResource, pParams); } @@ -214,8 +226,10 @@ static inline NvBool nodevicememAccessCallback_DISPATCH(struct NoDeviceMemory *p } NV_STATUS nodevicememConstruct_IMPL(struct NoDeviceMemory *arg_pNoDeviceMemory, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_nodevicememConstruct(arg_pNoDeviceMemory, arg_pCallContext, arg_pParams) nodevicememConstruct_IMPL(arg_pNoDeviceMemory, arg_pCallContext, arg_pParams) void nodevicememDestruct_IMPL(struct NoDeviceMemory *pNoDeviceMemory); + #define __nvoc_nodevicememDestruct(pNoDeviceMemory) nodevicememDestruct_IMPL(pNoDeviceMemory) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_nv_debug_dump_nvoc.h b/src/nvidia/generated/g_nv_debug_dump_nvoc.h index 44b011691..9b6fda5e8 100644 --- a/src/nvidia/generated/g_nv_debug_dump_nvoc.h +++ b/src/nvidia/generated/g_nv_debug_dump_nvoc.h @@ -322,8 +322,10 @@ static inline NvBool nvdIsPresent_DISPATCH(POBJGPU pGpu, struct NvDebugDump *pEn } void nvdDestruct_IMPL(struct NvDebugDump *pNvd); + #define __nvoc_nvdDestruct(pNvd) nvdDestruct_IMPL(pNvd) NV_STATUS nvdDumpComponent_IMPL(struct OBJGPU *pGpu, struct NvDebugDump *pNvd, NvU32 component, NVDUMP_BUFFER *pBuffer, NVDUMP_BUFFER_POLICY policy, PrbBufferCallback *pBufferCallback); + #ifdef __nvoc_nv_debug_dump_h_disabled static inline NV_STATUS nvdDumpComponent(struct OBJGPU *pGpu, struct NvDebugDump *pNvd, NvU32 component, NVDUMP_BUFFER *pBuffer, NVDUMP_BUFFER_POLICY policy, PrbBufferCallback *pBufferCallback) { NV_ASSERT_FAILED_PRECOMP("NvDebugDump was disabled!"); @@ -334,6 +336,7 @@ static inline NV_STATUS nvdDumpComponent(struct OBJGPU *pGpu, struct NvDebugDump #endif //__nvoc_nv_debug_dump_h_disabled NV_STATUS nvdAllocDebugBuffer_IMPL(struct OBJGPU *pGpu, struct NvDebugDump *pNvd, NvU32 arg0, NvU32 *arg1, MEMORY_DESCRIPTOR **arg2); + #ifdef __nvoc_nv_debug_dump_h_disabled static inline NV_STATUS nvdAllocDebugBuffer(struct OBJGPU *pGpu, struct NvDebugDump *pNvd, NvU32 arg0, NvU32 *arg1, MEMORY_DESCRIPTOR **arg2) { NV_ASSERT_FAILED_PRECOMP("NvDebugDump was disabled!"); @@ -344,6 +347,7 @@ static inline NV_STATUS nvdAllocDebugBuffer(struct OBJGPU *pGpu, struct NvDebugD #endif //__nvoc_nv_debug_dump_h_disabled NV_STATUS nvdFreeDebugBuffer_IMPL(struct OBJGPU *pGpu, struct NvDebugDump *pNvd, MEMORY_DESCRIPTOR *arg0); + #ifdef __nvoc_nv_debug_dump_h_disabled static inline NV_STATUS nvdFreeDebugBuffer(struct OBJGPU *pGpu, struct NvDebugDump *pNvd, MEMORY_DESCRIPTOR *arg0) { NV_ASSERT_FAILED_PRECOMP("NvDebugDump was disabled!"); @@ -354,6 +358,7 @@ static inline NV_STATUS nvdFreeDebugBuffer(struct OBJGPU *pGpu, struct NvDebugDu #endif //__nvoc_nv_debug_dump_h_disabled NV_STATUS nvdDumpDebugBuffers_IMPL(struct OBJGPU *pGpu, struct NvDebugDump *pNvd, PRB_ENCODER *arg0); + #ifdef __nvoc_nv_debug_dump_h_disabled static inline NV_STATUS nvdDumpDebugBuffers(struct OBJGPU *pGpu, struct NvDebugDump *pNvd, PRB_ENCODER *arg0) { NV_ASSERT_FAILED_PRECOMP("NvDebugDump was disabled!"); @@ -364,6 +369,7 @@ static inline NV_STATUS nvdDumpDebugBuffers(struct OBJGPU *pGpu, struct NvDebugD #endif //__nvoc_nv_debug_dump_h_disabled NV_STATUS nvdEngineSignUp_IMPL(struct OBJGPU *pGpu, struct NvDebugDump *pNvd, NvdDumpEngineFunc *arg0, NvU32 engDesc, NvU32 flags, void *arg1); + #ifdef __nvoc_nv_debug_dump_h_disabled static inline NV_STATUS nvdEngineSignUp(struct OBJGPU *pGpu, struct NvDebugDump *pNvd, NvdDumpEngineFunc *arg0, NvU32 engDesc, NvU32 flags, void *arg1) { NV_ASSERT_FAILED_PRECOMP("NvDebugDump was disabled!"); @@ -374,6 +380,7 @@ static inline NV_STATUS nvdEngineSignUp(struct OBJGPU *pGpu, struct NvDebugDump #endif //__nvoc_nv_debug_dump_h_disabled NV_STATUS nvdEngineRelease_IMPL(struct OBJGPU *pGpu, struct NvDebugDump *pNvd); + #ifdef __nvoc_nv_debug_dump_h_disabled static inline NV_STATUS nvdEngineRelease(struct OBJGPU *pGpu, struct NvDebugDump *pNvd) { NV_ASSERT_FAILED_PRECOMP("NvDebugDump was disabled!"); @@ -384,6 +391,7 @@ static inline NV_STATUS nvdEngineRelease(struct OBJGPU *pGpu, struct NvDebugDump #endif //__nvoc_nv_debug_dump_h_disabled NV_STATUS nvdDoEngineDump_IMPL(struct OBJGPU *pGpu, struct NvDebugDump *pNvd, PRB_ENCODER *pPrbEnc, NVD_STATE *pNvDumpState, NvU32 arg0); + #ifdef __nvoc_nv_debug_dump_h_disabled static inline NV_STATUS nvdDoEngineDump(struct OBJGPU *pGpu, struct NvDebugDump *pNvd, PRB_ENCODER *pPrbEnc, NVD_STATE *pNvDumpState, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("NvDebugDump was disabled!"); @@ -394,6 +402,7 @@ static inline NV_STATUS nvdDoEngineDump(struct OBJGPU *pGpu, struct NvDebugDump #endif //__nvoc_nv_debug_dump_h_disabled NV_STATUS nvdDumpAllEngines_IMPL(struct OBJGPU *pGpu, struct NvDebugDump *pNvd, PRB_ENCODER *pPrbEnc, NVD_STATE *pNvDumpState); + #ifdef __nvoc_nv_debug_dump_h_disabled static inline NV_STATUS nvdDumpAllEngines(struct OBJGPU *pGpu, struct NvDebugDump *pNvd, PRB_ENCODER *pPrbEnc, NVD_STATE *pNvDumpState) { NV_ASSERT_FAILED_PRECOMP("NvDebugDump was disabled!"); @@ -404,6 +413,7 @@ static inline NV_STATUS nvdDumpAllEngines(struct OBJGPU *pGpu, struct NvDebugDum #endif //__nvoc_nv_debug_dump_h_disabled NV_STATUS nvdFindEngine_IMPL(struct OBJGPU *pGpu, struct NvDebugDump *pNvd, NvU32 engDesc, NVD_ENGINE_CALLBACK **ppEngineCallback); + #ifdef __nvoc_nv_debug_dump_h_disabled static inline NV_STATUS nvdFindEngine(struct OBJGPU *pGpu, struct NvDebugDump *pNvd, NvU32 engDesc, NVD_ENGINE_CALLBACK **ppEngineCallback) { NV_ASSERT_FAILED_PRECOMP("NvDebugDump was disabled!"); diff --git a/src/nvidia/generated/g_nv_name_released.h b/src/nvidia/generated/g_nv_name_released.h index 29cd17bfe..d208cfb4e 100644 --- a/src/nvidia/generated/g_nv_name_released.h +++ b/src/nvidia/generated/g_nv_name_released.h @@ -815,6 +815,17 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x20B6, 0x1492, 0x10de, "NVIDIA PG506-232" }, { 0x20B7, 0x1532, 0x10de, "NVIDIA A30" }, { 0x20F1, 0x145f, 0x10de, "NVIDIA A100-PCIE-40GB" }, + { 0x20F3, 0x179b, 0x10de, "NVIDIA A800-SXM4-80GB" }, + { 0x20F3, 0x179c, 0x10de, "NVIDIA A800-SXM4-80GB" }, + { 0x20F3, 0x179d, 0x10de, "NVIDIA A800-SXM4-80GB" }, + { 0x20F3, 0x179e, 0x10de, "NVIDIA A800-SXM4-80GB" }, + { 0x20F3, 0x179f, 0x10de, "NVIDIA A800-SXM4-80GB" }, + { 0x20F3, 0x17a0, 0x10de, "NVIDIA A800-SXM4-80GB" }, + { 0x20F3, 0x17a1, 0x10de, "NVIDIA A800-SXM4-80GB" }, + { 0x20F3, 0x17a2, 0x10de, "NVIDIA A800-SXM4-80GB" }, + { 0x20F5, 0x1799, 0x10de, "NVIDIA A800 80GB PCIe" }, + { 0x20F5, 0x179a, 0x10de, "NVIDIA A800 80GB PCIe LC" }, + { 0x20F6, 0x17a3, 0x10de, "NVIDIA A800 40GB PCIe" }, { 0x2182, 0x0000, 0x0000, "NVIDIA GeForce GTX 1660 Ti" }, { 0x2184, 0x0000, 0x0000, "NVIDIA GeForce GTX 1660" }, { 0x2187, 0x0000, 0x0000, "NVIDIA GeForce GTX 1650 SUPER" }, @@ -1330,6 +1341,44 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x20F1, 0x149c, 0x10DE, "GRID A100-20C" }, { 0x20F1, 0x149d, 0x10DE, "GRID A100-40C" }, { 0x20F1, 0x160e, 0x10DE, "GRID A100-1-5CME" }, + { 0x20F3, 0x17b2, 0x10DE, "GRID A800DX-1-10CME" }, + { 0x20F3, 0x17b3, 0x10DE, "GRID A800DX-1-10C" }, + { 0x20F3, 0x17b4, 0x10DE, "GRID A800DX-2-20C" }, + { 0x20F3, 0x17b5, 0x10DE, "GRID A800DX-3-40C" }, + { 0x20F3, 0x17b6, 0x10DE, "GRID A800DX-4-40C" }, + { 0x20F3, 0x17b7, 0x10DE, "GRID A800DX-7-80C" }, + { 0x20F3, 0x17b8, 0x10DE, "GRID A800DX-4C" }, + { 0x20F3, 0x17b9, 0x10DE, "GRID A800DX-8C" }, + { 0x20F3, 0x17ba, 0x10DE, "GRID A800DX-10C" }, + { 0x20F3, 0x17bb, 0x10DE, "GRID A800DX-16C" }, + { 0x20F3, 0x17bc, 0x10DE, "GRID A800DX-20C" }, + { 0x20F3, 0x17bd, 0x10DE, "GRID A800DX-40C" }, + { 0x20F3, 0x17be, 0x10DE, "GRID A800DX-80C" }, + { 0x20F5, 0x17bf, 0x10DE, "GRID A800D-1-10CME" }, + { 0x20F5, 0x17c0, 0x10DE, "GRID A800D-1-10C" }, + { 0x20F5, 0x17c1, 0x10DE, "GRID A800D-2-20C" }, + { 0x20F5, 0x17c2, 0x10DE, "GRID A800D-3-40C" }, + { 0x20F5, 0x17c3, 0x10DE, "GRID A800D-4-40C" }, + { 0x20F5, 0x17c4, 0x10DE, "GRID A800D-7-80C" }, + { 0x20F5, 0x17c5, 0x10DE, "GRID A800D-4C" }, + { 0x20F5, 0x17c6, 0x10DE, "GRID A800D-8C" }, + { 0x20F5, 0x17c7, 0x10DE, "GRID A800D-10C" }, + { 0x20F5, 0x17c8, 0x10DE, "GRID A800D-16C" }, + { 0x20F5, 0x17c9, 0x10DE, "GRID A800D-20C" }, + { 0x20F5, 0x17ca, 0x10DE, "GRID A800D-40C" }, + { 0x20F5, 0x17cb, 0x10DE, "GRID A800D-80C" }, + { 0x20F6, 0x17cc, 0x10DE, "GRID A800-1-5CME" }, + { 0x20F6, 0x17cd, 0x10DE, "GRID A800-1-5C" }, + { 0x20F6, 0x17ce, 0x10DE, "GRID A800-2-10C" }, + { 0x20F6, 0x17cf, 0x10DE, "GRID A800-3-20C" }, + { 0x20F6, 0x17d0, 0x10DE, "GRID A800-4-20C" }, + { 0x20F6, 0x17d1, 0x10DE, "GRID A800-7-40C" }, + { 0x20F6, 0x17d2, 0x10DE, "GRID A800-4C" }, + { 0x20F6, 0x17d3, 0x10DE, "GRID A800-5C" }, + { 0x20F6, 0x17d4, 0x10DE, "GRID A800-8C" }, + { 0x20F6, 0x17d5, 0x10DE, "GRID A800-10C" }, + { 0x20F6, 0x17d6, 0x10DE, "GRID A800-20C" }, + { 0x20F6, 0x17d7, 0x10DE, "GRID A800-40C" }, { 0x2230, 0x14fa, 0x10DE, "NVIDIA RTXA6000-1B" }, { 0x2230, 0x14fb, 0x10DE, "NVIDIA RTXA6000-2B" }, { 0x2230, 0x14fc, 0x10DE, "NVIDIA RTXA6000-1Q" }, @@ -1479,18 +1528,34 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2238, 0x16b8, 0x10DE, "NVIDIA A10M-10C" }, { 0x2238, 0x16b9, 0x10DE, "NVIDIA A10M-20C" }, { 0x2238, 0x16e6, 0x10DE, "NVIDIA A10M-1" }, - { 0x2331, 0x16d3, 0x10DE, "GRID H100-1-10C" }, - { 0x2331, 0x16d4, 0x10DE, "GRID H100-2-20C" }, - { 0x2331, 0x16d5, 0x10DE, "GRID H100-3-40C" }, - { 0x2331, 0x16d6, 0x10DE, "GRID H100-4-40C" }, - { 0x2331, 0x16d7, 0x10DE, "GRID H100-7-80C" }, - { 0x2331, 0x16d8, 0x10DE, "GRID H100-4C" }, - { 0x2331, 0x16d9, 0x10DE, "GRID H100-8C" }, - { 0x2331, 0x16da, 0x10DE, "GRID H100-10C" }, - { 0x2331, 0x16db, 0x10DE, "GRID H100-16C" }, - { 0x2331, 0x16dc, 0x10DE, "GRID H100-20C" }, - { 0x2331, 0x16dd, 0x10DE, "GRID H100-40C" }, - { 0x2331, 0x16de, 0x10DE, "GRID H100-80C" }, + { 0x2322, 0x17e2, 0x10DE, "NVIDIA H800-1-10CME" }, + { 0x2322, 0x17e3, 0x10DE, "NVIDIA H800-1-10C" }, + { 0x2322, 0x17e4, 0x10DE, "NVIDIA H800-2-20C" }, + { 0x2322, 0x17e5, 0x10DE, "NVIDIA H800-3-40C" }, + { 0x2322, 0x17e6, 0x10DE, "NVIDIA H800-4-40C" }, + { 0x2322, 0x17e7, 0x10DE, "NVIDIA H800-7-80C" }, + { 0x2322, 0x17e8, 0x10DE, "NVIDIA H800-4C" }, + { 0x2322, 0x17e9, 0x10DE, "NVIDIA H800-5C" }, + { 0x2322, 0x17ea, 0x10DE, "NVIDIA H800-8C" }, + { 0x2322, 0x17eb, 0x10DE, "NVIDIA H800-10C" }, + { 0x2322, 0x17ec, 0x10DE, "NVIDIA H800-16C" }, + { 0x2322, 0x17ed, 0x10DE, "NVIDIA H800-20C" }, + { 0x2322, 0x17ee, 0x10DE, "NVIDIA H800-40C" }, + { 0x2322, 0x17ef, 0x10DE, "NVIDIA H800-80C" }, + { 0x2331, 0x16d3, 0x10DE, "NVIDIA H100-1-10C" }, + { 0x2331, 0x16d4, 0x10DE, "NVIDIA H100-2-20C" }, + { 0x2331, 0x16d5, 0x10DE, "NVIDIA H100-3-40C" }, + { 0x2331, 0x16d6, 0x10DE, "NVIDIA H100-4-40C" }, + { 0x2331, 0x16d7, 0x10DE, "NVIDIA H100-7-80C" }, + { 0x2331, 0x16d8, 0x10DE, "NVIDIA H100-4C" }, + { 0x2331, 0x16d9, 0x10DE, "NVIDIA H100-8C" }, + { 0x2331, 0x16da, 0x10DE, "NVIDIA H100-10C" }, + { 0x2331, 0x16db, 0x10DE, "NVIDIA H100-16C" }, + { 0x2331, 0x16dc, 0x10DE, "NVIDIA H100-20C" }, + { 0x2331, 0x16dd, 0x10DE, "NVIDIA H100-40C" }, + { 0x2331, 0x16de, 0x10DE, "NVIDIA H100-80C" }, + { 0x2331, 0x1798, 0x10DE, "NVIDIA H100-5C" }, + { 0x2331, 0x17f0, 0x10DE, "NVIDIA H100-1-10CME" }, { 0x25B6, 0x159d, 0x10DE, "NVIDIA A16-1B" }, { 0x25B6, 0x159e, 0x10DE, "NVIDIA A16-2B" }, { 0x25B6, 0x159f, 0x10DE, "NVIDIA A16-1Q" }, diff --git a/src/nvidia/generated/g_object_nvoc.h b/src/nvidia/generated/g_object_nvoc.h index d9df8bb3e..e12e664b5 100644 --- a/src/nvidia/generated/g_object_nvoc.h +++ b/src/nvidia/generated/g_object_nvoc.h @@ -110,6 +110,7 @@ NV_STATUS __nvoc_objCreate_Object(Object**, Dynamic*, NvU32); __nvoc_objCreate_Object((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) void objAddChild_IMPL(struct Object *pObj, struct Object *pChild); + #ifdef __nvoc_object_h_disabled static inline void objAddChild(struct Object *pObj, struct Object *pChild) { NV_ASSERT_FAILED_PRECOMP("Object was disabled!"); @@ -119,6 +120,7 @@ static inline void objAddChild(struct Object *pObj, struct Object *pChild) { #endif //__nvoc_object_h_disabled void objRemoveChild_IMPL(struct Object *pObj, struct Object *pChild); + #ifdef __nvoc_object_h_disabled static inline void objRemoveChild(struct Object *pObj, struct Object *pChild) { NV_ASSERT_FAILED_PRECOMP("Object was disabled!"); @@ -128,6 +130,7 @@ static inline void objRemoveChild(struct Object *pObj, struct Object *pChild) { #endif //__nvoc_object_h_disabled struct Object *objGetChild_IMPL(struct Object *pObj); + #ifdef __nvoc_object_h_disabled static inline struct Object *objGetChild(struct Object *pObj) { NV_ASSERT_FAILED_PRECOMP("Object was disabled!"); @@ -138,6 +141,7 @@ static inline struct Object *objGetChild(struct Object *pObj) { #endif //__nvoc_object_h_disabled struct Object *objGetSibling_IMPL(struct Object *pObj); + #ifdef __nvoc_object_h_disabled static inline struct Object *objGetSibling(struct Object *pObj) { NV_ASSERT_FAILED_PRECOMP("Object was disabled!"); @@ -148,6 +152,7 @@ static inline struct Object *objGetSibling(struct Object *pObj) { #endif //__nvoc_object_h_disabled struct Object *objGetDirectParent_IMPL(struct Object *pObj); + #ifdef __nvoc_object_h_disabled static inline struct Object *objGetDirectParent(struct Object *pObj) { NV_ASSERT_FAILED_PRECOMP("Object was disabled!"); diff --git a/src/nvidia/generated/g_objgpumon_nvoc.h b/src/nvidia/generated/g_objgpumon_nvoc.h index aa06b8164..65f6f9b9f 100644 --- a/src/nvidia/generated/g_objgpumon_nvoc.h +++ b/src/nvidia/generated/g_objgpumon_nvoc.h @@ -132,6 +132,7 @@ NV_STATUS __nvoc_objCreate_OBJGPUMON(OBJGPUMON**, Dynamic*, NvU32); #define gpumonIsPresent(pGpu, pEngstate) gpumonIsPresent_DISPATCH(pGpu, pEngstate) void gpumonGetContextProcessInfo_GM107(struct OBJGPU *pGpu, struct OBJGPUMON *pGpumon, NvU32 arg0, NvU32 *arg1, NvU32 *arg2, const char **arg3); + #ifdef __nvoc_objgpumon_h_disabled static inline void gpumonGetContextProcessInfo(struct OBJGPU *pGpu, struct OBJGPUMON *pGpumon, NvU32 arg0, NvU32 *arg1, NvU32 *arg2, const char **arg3) { NV_ASSERT_FAILED_PRECOMP("OBJGPUMON was disabled!"); @@ -223,6 +224,7 @@ static inline NvBool gpumonIsPresent_DISPATCH(POBJGPU pGpu, struct OBJGPUMON *pE } NV_STATUS gpumonGetPerfmonUtilSamples_IMPL(struct OBJGPU *pGpu, struct OBJGPUMON *pGpumon, NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE *arg0, NvU32 arg1, NvU32 *arg2); + #ifdef __nvoc_objgpumon_h_disabled static inline NV_STATUS gpumonGetPerfmonUtilSamples(struct OBJGPU *pGpu, struct OBJGPUMON *pGpumon, NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE *arg0, NvU32 arg1, NvU32 *arg2) { NV_ASSERT_FAILED_PRECOMP("OBJGPUMON was disabled!"); diff --git a/src/nvidia/generated/g_objtmr_nvoc.c b/src/nvidia/generated/g_objtmr_nvoc.c index 8697633b6..e197a04eb 100644 --- a/src/nvidia/generated/g_objtmr_nvoc.c +++ b/src/nvidia/generated/g_objtmr_nvoc.c @@ -17,8 +17,6 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJENGSTATE; -extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJINTRABLE; - extern const struct NVOC_CLASS_DEF __nvoc_class_def_IntrService; void __nvoc_init_OBJTMR(OBJTMR*, RmHalspecOwner* ); @@ -46,12 +44,6 @@ static const struct NVOC_RTTI __nvoc_rtti_OBJTMR_OBJENGSTATE = { /*offset=*/ NV_OFFSETOF(OBJTMR, __nvoc_base_OBJENGSTATE), }; -static const struct NVOC_RTTI __nvoc_rtti_OBJTMR_OBJINTRABLE = { - /*pClassDef=*/ &__nvoc_class_def_OBJINTRABLE, - /*dtor=*/ &__nvoc_destructFromBase, - /*offset=*/ NV_OFFSETOF(OBJTMR, __nvoc_base_OBJINTRABLE), -}; - static const struct NVOC_RTTI __nvoc_rtti_OBJTMR_IntrService = { /*pClassDef=*/ &__nvoc_class_def_IntrService, /*dtor=*/ &__nvoc_destructFromBase, @@ -59,11 +51,10 @@ static const struct NVOC_RTTI __nvoc_rtti_OBJTMR_IntrService = { }; static const struct NVOC_CASTINFO __nvoc_castinfo_OBJTMR = { - /*numRelatives=*/ 5, + /*numRelatives=*/ 4, /*relatives=*/ { &__nvoc_rtti_OBJTMR_OBJTMR, &__nvoc_rtti_OBJTMR_IntrService, - &__nvoc_rtti_OBJTMR_OBJINTRABLE, &__nvoc_rtti_OBJTMR_OBJENGSTATE, &__nvoc_rtti_OBJTMR_Object, }, @@ -84,7 +75,7 @@ const struct NVOC_CLASS_DEF __nvoc_class_def_OBJTMR = /*pExportInfo=*/ &__nvoc_export_info_OBJTMR }; -static void __nvoc_thunk_OBJTMR_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pTmr, IntrServiceRecord pRecords[155]) { +static void __nvoc_thunk_OBJTMR_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pTmr, IntrServiceRecord pRecords[163]) { tmrRegisterIntrService(pGpu, (struct OBJTMR *)(((unsigned char *)pTmr) - __nvoc_rtti_OBJTMR_IntrService.offset), pRecords); } @@ -120,36 +111,12 @@ static void __nvoc_thunk_OBJTMR_engstateStateDestroy(OBJGPU *pGpu, struct OBJENG tmrStateDestroy(pGpu, (struct OBJTMR *)(((unsigned char *)pTmr) - __nvoc_rtti_OBJTMR_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJTMR_intrableGetPhysicalIntrVectors(OBJGPU *pGpu, struct OBJINTRABLE *pTmr, NvU32 maxIntrs, NvU32 *pIntrs, NvU32 *pMcEngineIdxs, NvU32 *pCount) { - return tmrGetPhysicalIntrVectors(pGpu, (struct OBJTMR *)(((unsigned char *)pTmr) - __nvoc_rtti_OBJTMR_OBJINTRABLE.offset), maxIntrs, pIntrs, pMcEngineIdxs, pCount); -} - -static void __nvoc_thunk_OBJENGSTATE_tmrFreeTunableState(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_tmrCompareTunableState(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static NV_STATUS __nvoc_thunk_OBJINTRABLE_tmrGetNotificationIntrVector(struct OBJGPU *pGpu, struct OBJTMR *pIntrable, NvU32 *pIntrVector) { - return intrableGetNotificationIntrVector(pGpu, (struct OBJINTRABLE *)(((unsigned char *)pIntrable) + __nvoc_rtti_OBJTMR_OBJINTRABLE.offset), pIntrVector); -} - -static NvBool __nvoc_thunk_OBJENGSTATE_tmrIsPresent(POBJGPU pGpu, struct OBJTMR *pEngstate) { - return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset)); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_tmrReconcileTunableState(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunableState) { return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset), pTunableState); } -static NV_STATUS __nvoc_thunk_OBJINTRABLE_tmrGetKernelIntrVectors(struct OBJGPU *pGpu, struct OBJTMR *pIntrable, NvU32 maxIntrs, NvU32 *pIntrs, NvU32 *pMcEngineIdxs, NvU32 *pCount) { - return intrableGetKernelIntrVectors(pGpu, (struct OBJINTRABLE *)(((unsigned char *)pIntrable) + __nvoc_rtti_OBJTMR_OBJINTRABLE.offset), maxIntrs, pIntrs, pMcEngineIdxs, pCount); -} - -static NV_STATUS __nvoc_thunk_OBJINTRABLE_tmrSetNotificationIntrVector(struct OBJGPU *pGpu, struct OBJTMR *pIntrable, NvU32 intrVector) { - return intrableSetNotificationIntrVector(pGpu, (struct OBJINTRABLE *)(((unsigned char *)pIntrable) + __nvoc_rtti_OBJTMR_OBJINTRABLE.offset), intrVector); +static NV_STATUS __nvoc_thunk_IntrService_tmrServiceNotificationInterrupt(OBJGPU *pGpu, struct OBJTMR *pIntrService, IntrServiceServiceNotificationInterruptArguments *pParams) { + return intrservServiceNotificationInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_OBJTMR_IntrService.offset), pParams); } static NV_STATUS __nvoc_thunk_OBJENGSTATE_tmrStatePreLoad(POBJGPU pGpu, struct OBJTMR *pEngstate, NvU32 arg0) { @@ -164,10 +131,6 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_tmrStatePreUnload(POBJGPU pGpu, struct return engstateStatePreUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_tmrGetTunableState(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset), pTunableState); -} - static void __nvoc_thunk_OBJENGSTATE_tmrInitMissing(POBJGPU pGpu, struct OBJTMR *pEngstate) { engstateInitMissing(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset)); } @@ -180,8 +143,16 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_tmrStatePreInitUnlocked(POBJGPU pGpu, return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_IntrService_tmrServiceNotificationInterrupt(OBJGPU *pGpu, struct OBJTMR *pIntrService, IntrServiceServiceNotificationInterruptArguments *pParams) { - return intrservServiceNotificationInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_OBJTMR_IntrService.offset), pParams); +static NV_STATUS __nvoc_thunk_OBJENGSTATE_tmrGetTunableState(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunableState) { + return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset), pTunableState); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_tmrCompareTunableState(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunables1, void *pTunables2) { + return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset), pTunables1, pTunables2); +} + +static void __nvoc_thunk_OBJENGSTATE_tmrFreeTunableState(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunableState) { + engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset), pTunableState); } static NV_STATUS __nvoc_thunk_OBJENGSTATE_tmrStatePostLoad(POBJGPU pGpu, struct OBJTMR *pEngstate, NvU32 arg0) { @@ -196,6 +167,10 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_tmrSetTunableState(POBJGPU pGpu, struc return engstateSetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset), pTunableState); } +static NvBool __nvoc_thunk_OBJENGSTATE_tmrIsPresent(POBJGPU pGpu, struct OBJTMR *pEngstate) { + return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset)); +} + const struct NVOC_EXPORT_INFO __nvoc_export_info_OBJTMR = { /*numEntries=*/ 0, @@ -203,12 +178,10 @@ const struct NVOC_EXPORT_INFO __nvoc_export_info_OBJTMR = }; void __nvoc_dtor_OBJENGSTATE(OBJENGSTATE*); -void __nvoc_dtor_OBJINTRABLE(OBJINTRABLE*); void __nvoc_dtor_IntrService(IntrService*); void __nvoc_dtor_OBJTMR(OBJTMR *pThis) { __nvoc_tmrDestruct(pThis); __nvoc_dtor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); - __nvoc_dtor_OBJINTRABLE(&pThis->__nvoc_base_OBJINTRABLE); __nvoc_dtor_IntrService(&pThis->__nvoc_base_IntrService); PORT_UNREFERENCED_VARIABLE(pThis); } @@ -226,18 +199,13 @@ void __nvoc_init_dataField_OBJTMR(OBJTMR *pThis, RmHalspecOwner *pRmhalspecowner PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // NVOC Property Hal field -- PDB_PROP_TMR_USE_COUNTDOWN_TIMER_FOR_RM_CALLBACKS - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_TMR_USE_COUNTDOWN_TIMER_FOR_RM_CALLBACKS, ((NvBool)(0 == 0))); } - // default - else - { - pThis->setProperty(pThis, PDB_PROP_TMR_USE_COUNTDOWN_TIMER_FOR_RM_CALLBACKS, ((NvBool)(0 != 0))); - } // NVOC Property Hal field -- PDB_PROP_TMR_ALARM_INTR_REMOVED_FROM_PMC_TREE - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_TMR_ALARM_INTR_REMOVED_FROM_PMC_TREE, ((NvBool)(0 == 0))); } @@ -248,19 +216,15 @@ void __nvoc_init_dataField_OBJTMR(OBJTMR *pThis, RmHalspecOwner *pRmhalspecowner } // NVOC Property Hal field -- PDB_PROP_TMR_USE_OS_TIMER_FOR_CALLBACKS - if (0) + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - } - // default - else - { - pThis->setProperty(pThis, PDB_PROP_TMR_USE_OS_TIMER_FOR_CALLBACKS, ((NvBool)(0 != 0))); + pThis->setProperty(pThis, PDB_PROP_TMR_USE_OS_TIMER_FOR_CALLBACKS, ((NvBool)(0 == 0))); } pThis->setProperty(pThis, PDB_PROP_TMR_USE_PTIMER_FOR_OSTIMER_CALLBACKS, (0)); pThis->setProperty(pThis, PDB_PROP_TMR_USE_POLLING_FOR_CALLBACKS, (0)); // NVOC Property Hal field -- PDB_PROP_TMR_USE_SECOND_COUNTDOWN_TIMER_FOR_SWRL - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->setProperty(pThis, PDB_PROP_TMR_USE_SECOND_COUNTDOWN_TIMER_FOR_SWRL, ((NvBool)(0 == 0))); } @@ -271,23 +235,18 @@ void __nvoc_init_dataField_OBJTMR(OBJTMR *pThis, RmHalspecOwner *pRmhalspecowner } } -NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* , RmHalspecOwner* ); -NV_STATUS __nvoc_ctor_OBJINTRABLE(OBJINTRABLE* , RmHalspecOwner* ); -NV_STATUS __nvoc_ctor_IntrService(IntrService* , RmHalspecOwner* ); +NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); +NV_STATUS __nvoc_ctor_IntrService(IntrService* ); NV_STATUS __nvoc_ctor_OBJTMR(OBJTMR *pThis, RmHalspecOwner *pRmhalspecowner) { NV_STATUS status = NV_OK; - status = __nvoc_ctor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE, pRmhalspecowner); + status = __nvoc_ctor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); if (status != NV_OK) goto __nvoc_ctor_OBJTMR_fail_OBJENGSTATE; - status = __nvoc_ctor_OBJINTRABLE(&pThis->__nvoc_base_OBJINTRABLE, pRmhalspecowner); - if (status != NV_OK) goto __nvoc_ctor_OBJTMR_fail_OBJINTRABLE; - status = __nvoc_ctor_IntrService(&pThis->__nvoc_base_IntrService, pRmhalspecowner); + status = __nvoc_ctor_IntrService(&pThis->__nvoc_base_IntrService); if (status != NV_OK) goto __nvoc_ctor_OBJTMR_fail_IntrService; __nvoc_init_dataField_OBJTMR(pThis, pRmhalspecowner); goto __nvoc_ctor_OBJTMR_exit; // Success __nvoc_ctor_OBJTMR_fail_IntrService: - __nvoc_dtor_OBJINTRABLE(&pThis->__nvoc_base_OBJINTRABLE); -__nvoc_ctor_OBJTMR_fail_OBJINTRABLE: __nvoc_dtor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); __nvoc_ctor_OBJTMR_fail_OBJENGSTATE: __nvoc_ctor_OBJTMR_exit: @@ -316,25 +275,6 @@ static void __nvoc_init_funcTable_OBJTMR_1(OBJTMR *pThis, RmHalspecOwner *pRmhal { pThis->__tmrServiceInterrupt__ = &tmrServiceInterrupt_56cd7a; } - else if (0) - { -#if 0 - if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ - { - pThis->__tmrServiceInterrupt__ = &tmrServiceInterrupt_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ - { - pThis->__tmrServiceInterrupt__ = &tmrServiceInterrupt_GA100; - } - else if (0) - { - } -#endif - } pThis->__tmrConstructEngine__ = &tmrConstructEngine_IMPL; @@ -349,127 +289,70 @@ static void __nvoc_init_funcTable_OBJTMR_1(OBJTMR *pThis, RmHalspecOwner *pRmhal pThis->__tmrStateDestroy__ = &tmrStateDestroy_IMPL; // Hal function -- tmrSetCurrentTime - if (0) + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__tmrSetCurrentTime__ = &tmrSetCurrentTime_GV100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__tmrSetCurrentTime__ = &tmrSetCurrentTime_GH100; } - else if (0) - { - } } // Hal function -- tmrGetTimeEx - if (0) + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - } - else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__tmrGetTimeEx__ = &tmrGetTimeEx_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__tmrGetTimeEx__ = &tmrGetTimeEx_GH100; } - else if (0) - { - } } // Hal function -- tmrSetCountdownIntrDisable - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__tmrSetCountdownIntrDisable__ = &tmrSetCountdownIntrDisable_GM200; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__tmrSetCountdownIntrDisable__ = &tmrSetCountdownIntrDisable_56cd7a; } - // default - else - { - } // Hal function -- tmrSetCountdown - if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__tmrSetCountdown__ = &tmrSetCountdown_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__tmrSetCountdown__ = &tmrSetCountdown_GH100; } - else if (0) - { - } // Hal function -- tmrGrTickFreqChange - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__tmrGrTickFreqChange__ = &tmrGrTickFreqChange_GM107; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__tmrGrTickFreqChange__ = &tmrGrTickFreqChange_46f6a7; } // Hal function -- tmrGetGpuPtimerOffset - if (0) - { - } - else if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__tmrGetGpuPtimerOffset__ = &tmrGetGpuPtimerOffset_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__tmrGetGpuPtimerOffset__ = &tmrGetGpuPtimerOffset_GA100; } - else if (0) - { - } - else if (0) - { - } - - // Hal function -- tmrGetPhysicalIntrVectors - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - pThis->__tmrGetPhysicalIntrVectors__ = &tmrGetPhysicalIntrVectors_46f6a7; - } - else if (0) - { -#if 0 - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ - { - pThis->__tmrGetPhysicalIntrVectors__ = &tmrGetPhysicalIntrVectors_GH100; - } - // default - else - { - pThis->__tmrGetPhysicalIntrVectors__ = &tmrGetPhysicalIntrVectors_46f6a7; - } -#endif - } pThis->__nvoc_base_IntrService.__intrservRegisterIntrService__ = &__nvoc_thunk_OBJTMR_intrservRegisterIntrService; @@ -489,21 +372,9 @@ static void __nvoc_init_funcTable_OBJTMR_1(OBJTMR *pThis, RmHalspecOwner *pRmhal pThis->__nvoc_base_OBJENGSTATE.__engstateStateDestroy__ = &__nvoc_thunk_OBJTMR_engstateStateDestroy; - pThis->__nvoc_base_OBJINTRABLE.__intrableGetPhysicalIntrVectors__ = &__nvoc_thunk_OBJTMR_intrableGetPhysicalIntrVectors; - - pThis->__tmrFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_tmrFreeTunableState; - - pThis->__tmrCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_tmrCompareTunableState; - - pThis->__tmrGetNotificationIntrVector__ = &__nvoc_thunk_OBJINTRABLE_tmrGetNotificationIntrVector; - - pThis->__tmrIsPresent__ = &__nvoc_thunk_OBJENGSTATE_tmrIsPresent; - pThis->__tmrReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_tmrReconcileTunableState; - pThis->__tmrGetKernelIntrVectors__ = &__nvoc_thunk_OBJINTRABLE_tmrGetKernelIntrVectors; - - pThis->__tmrSetNotificationIntrVector__ = &__nvoc_thunk_OBJINTRABLE_tmrSetNotificationIntrVector; + pThis->__tmrServiceNotificationInterrupt__ = &__nvoc_thunk_IntrService_tmrServiceNotificationInterrupt; pThis->__tmrStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_tmrStatePreLoad; @@ -511,39 +382,40 @@ static void __nvoc_init_funcTable_OBJTMR_1(OBJTMR *pThis, RmHalspecOwner *pRmhal pThis->__tmrStatePreUnload__ = &__nvoc_thunk_OBJENGSTATE_tmrStatePreUnload; - pThis->__tmrGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_tmrGetTunableState; - pThis->__tmrInitMissing__ = &__nvoc_thunk_OBJENGSTATE_tmrInitMissing; pThis->__tmrStatePreInitLocked__ = &__nvoc_thunk_OBJENGSTATE_tmrStatePreInitLocked; pThis->__tmrStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_tmrStatePreInitUnlocked; - pThis->__tmrServiceNotificationInterrupt__ = &__nvoc_thunk_IntrService_tmrServiceNotificationInterrupt; + pThis->__tmrGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_tmrGetTunableState; + + pThis->__tmrCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_tmrCompareTunableState; + + pThis->__tmrFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_tmrFreeTunableState; pThis->__tmrStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_tmrStatePostLoad; pThis->__tmrAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_tmrAllocTunableState; pThis->__tmrSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_tmrSetTunableState; + + pThis->__tmrIsPresent__ = &__nvoc_thunk_OBJENGSTATE_tmrIsPresent; } void __nvoc_init_funcTable_OBJTMR(OBJTMR *pThis, RmHalspecOwner *pRmhalspecowner) { __nvoc_init_funcTable_OBJTMR_1(pThis, pRmhalspecowner); } -void __nvoc_init_OBJENGSTATE(OBJENGSTATE*, RmHalspecOwner* ); -void __nvoc_init_OBJINTRABLE(OBJINTRABLE*, RmHalspecOwner* ); -void __nvoc_init_IntrService(IntrService*, RmHalspecOwner* ); +void __nvoc_init_OBJENGSTATE(OBJENGSTATE*); +void __nvoc_init_IntrService(IntrService*); void __nvoc_init_OBJTMR(OBJTMR *pThis, RmHalspecOwner *pRmhalspecowner) { pThis->__nvoc_pbase_OBJTMR = pThis; pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object; pThis->__nvoc_pbase_OBJENGSTATE = &pThis->__nvoc_base_OBJENGSTATE; - pThis->__nvoc_pbase_OBJINTRABLE = &pThis->__nvoc_base_OBJINTRABLE; pThis->__nvoc_pbase_IntrService = &pThis->__nvoc_base_IntrService; - __nvoc_init_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE, pRmhalspecowner); - __nvoc_init_OBJINTRABLE(&pThis->__nvoc_base_OBJINTRABLE, pRmhalspecowner); - __nvoc_init_IntrService(&pThis->__nvoc_base_IntrService, pRmhalspecowner); + __nvoc_init_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); + __nvoc_init_IntrService(&pThis->__nvoc_base_IntrService); __nvoc_init_funcTable_OBJTMR(pThis, pRmhalspecowner); } diff --git a/src/nvidia/generated/g_objtmr_nvoc.h b/src/nvidia/generated/g_objtmr_nvoc.h index 1002c1e9c..7ebaf7444 100644 --- a/src/nvidia/generated/g_objtmr_nvoc.h +++ b/src/nvidia/generated/g_objtmr_nvoc.h @@ -47,7 +47,6 @@ extern "C" { #include "lib/ref_count.h" #include "os/os.h" #include "nvoc/utility.h" -#include "kernel/gpu/intrable/intrable.h" #include "kernel/gpu/intr/intr_service.h" /* ------------------------ Macros ----------------------------------------- */ @@ -69,6 +68,7 @@ extern "C" { // !!NOTE: This is OBSOLETE, it should be moved directly to FIFO, where it's needed #define TMR_FLAG_RELEASE_SEMAPHORE NVBIT(1) #define TMR_FLAG_OS_TIMER_QUEUED NVBIT(2) +#define TMR_FLAG_USE_OS_TIMER NVBIT(3) #define TMR_GET_GPU(p) ENG_GET_GPU(p) @@ -182,11 +182,9 @@ typedef struct TMR_EVENT_GENERAL_PARAMS { struct OBJTMR { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; - struct OBJINTRABLE __nvoc_base_OBJINTRABLE; struct IntrService __nvoc_base_IntrService; struct Object *__nvoc_pbase_Object; struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; - struct OBJINTRABLE *__nvoc_pbase_OBJINTRABLE; struct IntrService *__nvoc_pbase_IntrService; struct OBJTMR *__nvoc_pbase_OBJTMR; void (*__tmrRegisterIntrService__)(OBJGPU *, struct OBJTMR *, IntrServiceRecord *); @@ -204,25 +202,21 @@ struct OBJTMR { NV_STATUS (*__tmrSetCountdown__)(OBJGPU *, struct OBJTMR *, NvU32, NvU32, struct THREAD_STATE_NODE *); NV_STATUS (*__tmrGrTickFreqChange__)(OBJGPU *, struct OBJTMR *, NvBool); NV_STATUS (*__tmrGetGpuPtimerOffset__)(OBJGPU *, struct OBJTMR *, NvU32 *, NvU32 *); - NV_STATUS (*__tmrGetPhysicalIntrVectors__)(OBJGPU *, struct OBJTMR *, NvU32, NvU32 *, NvU32 *, NvU32 *); - void (*__tmrFreeTunableState__)(POBJGPU, struct OBJTMR *, void *); - NV_STATUS (*__tmrCompareTunableState__)(POBJGPU, struct OBJTMR *, void *, void *); - NV_STATUS (*__tmrGetNotificationIntrVector__)(struct OBJGPU *, struct OBJTMR *, NvU32 *); - NvBool (*__tmrIsPresent__)(POBJGPU, struct OBJTMR *); NV_STATUS (*__tmrReconcileTunableState__)(POBJGPU, struct OBJTMR *, void *); - NV_STATUS (*__tmrGetKernelIntrVectors__)(struct OBJGPU *, struct OBJTMR *, NvU32, NvU32 *, NvU32 *, NvU32 *); - NV_STATUS (*__tmrSetNotificationIntrVector__)(struct OBJGPU *, struct OBJTMR *, NvU32); + NV_STATUS (*__tmrServiceNotificationInterrupt__)(OBJGPU *, struct OBJTMR *, IntrServiceServiceNotificationInterruptArguments *); NV_STATUS (*__tmrStatePreLoad__)(POBJGPU, struct OBJTMR *, NvU32); NV_STATUS (*__tmrStatePostUnload__)(POBJGPU, struct OBJTMR *, NvU32); NV_STATUS (*__tmrStatePreUnload__)(POBJGPU, struct OBJTMR *, NvU32); - NV_STATUS (*__tmrGetTunableState__)(POBJGPU, struct OBJTMR *, void *); void (*__tmrInitMissing__)(POBJGPU, struct OBJTMR *); NV_STATUS (*__tmrStatePreInitLocked__)(POBJGPU, struct OBJTMR *); NV_STATUS (*__tmrStatePreInitUnlocked__)(POBJGPU, struct OBJTMR *); - NV_STATUS (*__tmrServiceNotificationInterrupt__)(OBJGPU *, struct OBJTMR *, IntrServiceServiceNotificationInterruptArguments *); + NV_STATUS (*__tmrGetTunableState__)(POBJGPU, struct OBJTMR *, void *); + NV_STATUS (*__tmrCompareTunableState__)(POBJGPU, struct OBJTMR *, void *, void *); + void (*__tmrFreeTunableState__)(POBJGPU, struct OBJTMR *, void *); NV_STATUS (*__tmrStatePostLoad__)(POBJGPU, struct OBJTMR *, NvU32); NV_STATUS (*__tmrAllocTunableState__)(POBJGPU, struct OBJTMR *, void **); NV_STATUS (*__tmrSetTunableState__)(POBJGPU, struct OBJTMR *, void *); + NvBool (*__tmrIsPresent__)(POBJGPU, struct OBJTMR *); NvBool PDB_PROP_TMR_USE_COUNTDOWN_TIMER_FOR_RM_CALLBACKS; NvBool PDB_PROP_TMR_ALARM_INTR_REMOVED_FROM_PMC_TREE; NvBool PDB_PROP_TMR_USE_OS_TIMER_FOR_CALLBACKS; @@ -311,28 +305,24 @@ NV_STATUS __nvoc_objCreate_OBJTMR(OBJTMR**, Dynamic*, NvU32); #define tmrGrTickFreqChange_HAL(pGpu, pTmr, arg0) tmrGrTickFreqChange_DISPATCH(pGpu, pTmr, arg0) #define tmrGetGpuPtimerOffset(pGpu, pTmr, arg0, arg1) tmrGetGpuPtimerOffset_DISPATCH(pGpu, pTmr, arg0, arg1) #define tmrGetGpuPtimerOffset_HAL(pGpu, pTmr, arg0, arg1) tmrGetGpuPtimerOffset_DISPATCH(pGpu, pTmr, arg0, arg1) -#define tmrGetPhysicalIntrVectors(pGpu, pTmr, maxIntrs, pIntrs, pMcEngineIdxs, pCount) tmrGetPhysicalIntrVectors_DISPATCH(pGpu, pTmr, maxIntrs, pIntrs, pMcEngineIdxs, pCount) -#define tmrGetPhysicalIntrVectors_HAL(pGpu, pTmr, maxIntrs, pIntrs, pMcEngineIdxs, pCount) tmrGetPhysicalIntrVectors_DISPATCH(pGpu, pTmr, maxIntrs, pIntrs, pMcEngineIdxs, pCount) -#define tmrFreeTunableState(pGpu, pEngstate, pTunableState) tmrFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define tmrCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) tmrCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define tmrGetNotificationIntrVector(pGpu, pIntrable, pIntrVector) tmrGetNotificationIntrVector_DISPATCH(pGpu, pIntrable, pIntrVector) -#define tmrIsPresent(pGpu, pEngstate) tmrIsPresent_DISPATCH(pGpu, pEngstate) #define tmrReconcileTunableState(pGpu, pEngstate, pTunableState) tmrReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define tmrGetKernelIntrVectors(pGpu, pIntrable, maxIntrs, pIntrs, pMcEngineIdxs, pCount) tmrGetKernelIntrVectors_DISPATCH(pGpu, pIntrable, maxIntrs, pIntrs, pMcEngineIdxs, pCount) -#define tmrSetNotificationIntrVector(pGpu, pIntrable, intrVector) tmrSetNotificationIntrVector_DISPATCH(pGpu, pIntrable, intrVector) +#define tmrServiceNotificationInterrupt(pGpu, pIntrService, pParams) tmrServiceNotificationInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define tmrStatePreLoad(pGpu, pEngstate, arg0) tmrStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define tmrStatePostUnload(pGpu, pEngstate, arg0) tmrStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) #define tmrStatePreUnload(pGpu, pEngstate, arg0) tmrStatePreUnload_DISPATCH(pGpu, pEngstate, arg0) -#define tmrGetTunableState(pGpu, pEngstate, pTunableState) tmrGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define tmrInitMissing(pGpu, pEngstate) tmrInitMissing_DISPATCH(pGpu, pEngstate) #define tmrStatePreInitLocked(pGpu, pEngstate) tmrStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define tmrStatePreInitUnlocked(pGpu, pEngstate) tmrStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define tmrServiceNotificationInterrupt(pGpu, pIntrService, pParams) tmrServiceNotificationInterrupt_DISPATCH(pGpu, pIntrService, pParams) +#define tmrGetTunableState(pGpu, pEngstate, pTunableState) tmrGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) +#define tmrCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) tmrCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) +#define tmrFreeTunableState(pGpu, pEngstate, pTunableState) tmrFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define tmrStatePostLoad(pGpu, pEngstate, arg0) tmrStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) #define tmrAllocTunableState(pGpu, pEngstate, ppTunableState) tmrAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) #define tmrSetTunableState(pGpu, pEngstate, pTunableState) tmrSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) +#define tmrIsPresent(pGpu, pEngstate) tmrIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS tmrGetCurrentTime_IMPL(struct OBJTMR *pTmr, NvU64 *pTime); + #ifdef __nvoc_objtmr_h_disabled static inline NV_STATUS tmrGetCurrentTime(struct OBJTMR *pTmr, NvU64 *pTime) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -346,6 +336,7 @@ static inline NV_STATUS tmrGetCurrentTime(struct OBJTMR *pTmr, NvU64 *pTime) { NV_STATUS tmrGetCurrentTimeEx_IMPL(struct OBJTMR *pTmr, NvU64 *pTime, struct THREAD_STATE_NODE *arg0); + #ifdef __nvoc_objtmr_h_disabled static inline NV_STATUS tmrGetCurrentTimeEx(struct OBJTMR *pTmr, NvU64 *pTime, struct THREAD_STATE_NODE *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -357,6 +348,11 @@ static inline NV_STATUS tmrGetCurrentTimeEx(struct OBJTMR *pTmr, NvU64 *pTime, s #define tmrGetCurrentTimeEx_HAL(pTmr, pTime, arg0) tmrGetCurrentTimeEx(pTmr, pTime, arg0) +NV_STATUS tmrDelay_OSTIMER(struct OBJTMR *pTmr, NvU32 arg0); + +NV_STATUS tmrDelay_PTIMER(struct OBJTMR *pTmr, NvU32 arg0); + + #ifdef __nvoc_objtmr_h_disabled static inline NV_STATUS tmrDelay(struct OBJTMR *pTmr, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -372,6 +368,15 @@ static inline NV_STATUS tmrSetAlarmIntrDisable_56cd7a(OBJGPU *pGpu, struct OBJTM return NV_OK; } +NV_STATUS tmrSetAlarmIntrDisable_GM107(OBJGPU *pGpu, struct OBJTMR *pTmr); + +NV_STATUS tmrSetAlarmIntrDisable_GA100(OBJGPU *pGpu, struct OBJTMR *pTmr); + +static inline NV_STATUS tmrSetAlarmIntrDisable_46f6a7(OBJGPU *pGpu, struct OBJTMR *pTmr) { + return NV_ERR_NOT_SUPPORTED; +} + + #ifdef __nvoc_objtmr_h_disabled static inline NV_STATUS tmrSetAlarmIntrDisable(OBJGPU *pGpu, struct OBJTMR *pTmr) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -387,6 +392,15 @@ static inline NV_STATUS tmrSetAlarmIntrEnable_56cd7a(OBJGPU *pGpu, struct OBJTMR return NV_OK; } +NV_STATUS tmrSetAlarmIntrEnable_GM107(OBJGPU *pGpu, struct OBJTMR *pTmr); + +NV_STATUS tmrSetAlarmIntrEnable_GA100(OBJGPU *pGpu, struct OBJTMR *pTmr); + +static inline NV_STATUS tmrSetAlarmIntrEnable_46f6a7(OBJGPU *pGpu, struct OBJTMR *pTmr) { + return NV_ERR_NOT_SUPPORTED; +} + + #ifdef __nvoc_objtmr_h_disabled static inline NV_STATUS tmrSetAlarmIntrEnable(OBJGPU *pGpu, struct OBJTMR *pTmr) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -402,6 +416,15 @@ static inline NV_STATUS tmrSetAlarmIntrReset_56cd7a(OBJGPU *pGpu, struct OBJTMR return NV_OK; } +NV_STATUS tmrSetAlarmIntrReset_GM107(OBJGPU *pGpu, struct OBJTMR *pTmr, struct THREAD_STATE_NODE *arg0); + +NV_STATUS tmrSetAlarmIntrReset_GA100(OBJGPU *pGpu, struct OBJTMR *pTmr, struct THREAD_STATE_NODE *arg0); + +static inline NV_STATUS tmrSetAlarmIntrReset_46f6a7(OBJGPU *pGpu, struct OBJTMR *pTmr, struct THREAD_STATE_NODE *arg0) { + return NV_ERR_NOT_SUPPORTED; +} + + #ifdef __nvoc_objtmr_h_disabled static inline NV_STATUS tmrSetAlarmIntrReset(OBJGPU *pGpu, struct OBJTMR *pTmr, struct THREAD_STATE_NODE *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -418,6 +441,11 @@ static inline NV_STATUS tmrGetIntrStatus_cb5ce8(OBJGPU *pGpu, struct OBJTMR *pTm return NV_OK; } +NV_STATUS tmrGetIntrStatus_TU102(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU32 *pStatus, struct THREAD_STATE_NODE *arg0); + +NV_STATUS tmrGetIntrStatus_GA100(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU32 *pStatus, struct THREAD_STATE_NODE *arg0); + + #ifdef __nvoc_objtmr_h_disabled static inline NV_STATUS tmrGetIntrStatus(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU32 *pStatus, struct THREAD_STATE_NODE *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -433,6 +461,9 @@ static inline NvU32 tmrGetTimeLo_cf0499(OBJGPU *pGpu, struct OBJTMR *pTmr) { return ((NvU32)(((NvU64)(osGetTimestamp())) & 4294967295U)); } +NvU32 tmrGetTimeLo_GM107(OBJGPU *pGpu, struct OBJTMR *pTmr); + + #ifdef __nvoc_objtmr_h_disabled static inline NvU32 tmrGetTimeLo(OBJGPU *pGpu, struct OBJTMR *pTmr) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -448,6 +479,9 @@ static inline NvU64 tmrGetTime_fa6bbe(OBJGPU *pGpu, struct OBJTMR *pTmr) { return osGetTimestamp(); } +NvU64 tmrGetTime_GM107(OBJGPU *pGpu, struct OBJTMR *pTmr); + + #ifdef __nvoc_objtmr_h_disabled static inline NvU64 tmrGetTime(OBJGPU *pGpu, struct OBJTMR *pTmr) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -461,6 +495,7 @@ static inline NvU64 tmrGetTime(OBJGPU *pGpu, struct OBJTMR *pTmr) { NvU32 tmrReadTimeLoReg_TU102(OBJGPU *pGpu, struct OBJTMR *pTmr, struct THREAD_STATE_NODE *arg0); + #ifdef __nvoc_objtmr_h_disabled static inline NvU32 tmrReadTimeLoReg(OBJGPU *pGpu, struct OBJTMR *pTmr, struct THREAD_STATE_NODE *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -474,6 +509,7 @@ static inline NvU32 tmrReadTimeLoReg(OBJGPU *pGpu, struct OBJTMR *pTmr, struct T NvU32 tmrReadTimeHiReg_TU102(OBJGPU *pGpu, struct OBJTMR *pTmr, struct THREAD_STATE_NODE *arg0); + #ifdef __nvoc_objtmr_h_disabled static inline NvU32 tmrReadTimeHiReg(OBJGPU *pGpu, struct OBJTMR *pTmr, struct THREAD_STATE_NODE *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -489,6 +525,13 @@ static inline NV_STATUS tmrSetAlarm_56cd7a(OBJGPU *pGpu, struct OBJTMR *pTmr, Nv return NV_OK; } +NV_STATUS tmrSetAlarm_GM107(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU64 alarm, struct THREAD_STATE_NODE *pThreadState); + +static inline NV_STATUS tmrSetAlarm_46f6a7(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU64 alarm, struct THREAD_STATE_NODE *pThreadState) { + return NV_ERR_NOT_SUPPORTED; +} + + #ifdef __nvoc_objtmr_h_disabled static inline NV_STATUS tmrSetAlarm(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU64 alarm, struct THREAD_STATE_NODE *pThreadState) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -504,6 +547,11 @@ static inline NvBool tmrGetAlarmPending_491d52(OBJGPU *pGpu, struct OBJTMR *pTmr return ((NvBool)(0 != 0)); } +NvBool tmrGetAlarmPending_GM107(OBJGPU *pGpu, struct OBJTMR *pTmr, struct THREAD_STATE_NODE *arg0); + +NvBool tmrGetAlarmPending_GA100(OBJGPU *pGpu, struct OBJTMR *pTmr, struct THREAD_STATE_NODE *arg0); + + #ifdef __nvoc_objtmr_h_disabled static inline NvBool tmrGetAlarmPending(OBJGPU *pGpu, struct OBJTMR *pTmr, struct THREAD_STATE_NODE *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -517,6 +565,7 @@ static inline NvBool tmrGetAlarmPending(OBJGPU *pGpu, struct OBJTMR *pTmr, struc NV_STATUS tmrSetCountdownIntrEnable_TU102(OBJGPU *pGpu, struct OBJTMR *pTmr); + #ifdef __nvoc_objtmr_h_disabled static inline NV_STATUS tmrSetCountdownIntrEnable(OBJGPU *pGpu, struct OBJTMR *pTmr) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -530,6 +579,7 @@ static inline NV_STATUS tmrSetCountdownIntrEnable(OBJGPU *pGpu, struct OBJTMR *p NV_STATUS tmrSetCountdownIntrReset_TU102(OBJGPU *pGpu, struct OBJTMR *pTmr, struct THREAD_STATE_NODE *arg0); + #ifdef __nvoc_objtmr_h_disabled static inline NV_STATUS tmrSetCountdownIntrReset(OBJGPU *pGpu, struct OBJTMR *pTmr, struct THREAD_STATE_NODE *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -545,6 +595,7 @@ static inline NvBool tmrGetCountdownPending_491d52(OBJGPU *pGpu, struct OBJTMR * return ((NvBool)(0 != 0)); } + #ifdef __nvoc_objtmr_h_disabled static inline NvBool tmrGetCountdownPending(OBJGPU *pGpu, struct OBJTMR *pTmr, struct THREAD_STATE_NODE *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -558,6 +609,7 @@ static inline NvBool tmrGetCountdownPending(OBJGPU *pGpu, struct OBJTMR *pTmr, s NV_STATUS tmrGetTimerBar0MapInfo_PTIMER(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU64 *arg0, NvU32 *arg1); + #ifdef __nvoc_objtmr_h_disabled static inline NV_STATUS tmrGetTimerBar0MapInfo(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU64 *arg0, NvU32 *arg1) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -573,6 +625,9 @@ static inline NvU32 tmrGetUtilsClkScaleFactor_4a4dee(OBJGPU *pGpu, struct OBJTMR return 0; } +NvU32 tmrGetUtilsClkScaleFactor_GM107(OBJGPU *pGpu, struct OBJTMR *pTmr); + + #ifdef __nvoc_objtmr_h_disabled static inline NvU32 tmrGetUtilsClkScaleFactor(OBJGPU *pGpu, struct OBJTMR *pTmr) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -586,6 +641,7 @@ static inline NvU32 tmrGetUtilsClkScaleFactor(OBJGPU *pGpu, struct OBJTMR *pTmr) NV_STATUS tmrGetGpuAndCpuTimestampPair_GM107(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU64 *arg0, NvU64 *arg1); + #ifdef __nvoc_objtmr_h_disabled static inline NV_STATUS tmrGetGpuAndCpuTimestampPair(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU64 *arg0, NvU64 *arg1) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -601,6 +657,11 @@ static inline void tmrResetTimerRegistersForVF_b3696a(OBJGPU *pGpu, struct OBJTM return; } +void tmrResetTimerRegistersForVF_TU102(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU32 gfid); + +void tmrResetTimerRegistersForVF_GH100(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU32 gfid); + + #ifdef __nvoc_objtmr_h_disabled static inline void tmrResetTimerRegistersForVF(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -611,9 +672,8 @@ static inline void tmrResetTimerRegistersForVF(OBJGPU *pGpu, struct OBJTMR *pTmr #define tmrResetTimerRegistersForVF_HAL(pGpu, pTmr, gfid) tmrResetTimerRegistersForVF(pGpu, pTmr, gfid) -static inline NV_STATUS tmrEventCreateOSTimer_46f6a7(struct OBJTMR *pTmr, PTMR_EVENT pEvent) { - return NV_ERR_NOT_SUPPORTED; -} +NV_STATUS tmrEventCreateOSTimer_OSTIMER(struct OBJTMR *pTmr, PTMR_EVENT pEvent); + #ifdef __nvoc_objtmr_h_disabled static inline NV_STATUS tmrEventCreateOSTimer(struct OBJTMR *pTmr, PTMR_EVENT pEvent) { @@ -621,14 +681,13 @@ static inline NV_STATUS tmrEventCreateOSTimer(struct OBJTMR *pTmr, PTMR_EVENT pE return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_objtmr_h_disabled -#define tmrEventCreateOSTimer(pTmr, pEvent) tmrEventCreateOSTimer_46f6a7(pTmr, pEvent) +#define tmrEventCreateOSTimer(pTmr, pEvent) tmrEventCreateOSTimer_OSTIMER(pTmr, pEvent) #endif //__nvoc_objtmr_h_disabled #define tmrEventCreateOSTimer_HAL(pTmr, pEvent) tmrEventCreateOSTimer(pTmr, pEvent) -static inline NV_STATUS tmrEventScheduleAbsOSTimer_46f6a7(struct OBJTMR *pTmr, PTMR_EVENT pEvent, NvU64 timeAbs) { - return NV_ERR_NOT_SUPPORTED; -} +NV_STATUS tmrEventScheduleAbsOSTimer_OSTIMER(struct OBJTMR *pTmr, PTMR_EVENT pEvent, NvU64 timeAbs); + #ifdef __nvoc_objtmr_h_disabled static inline NV_STATUS tmrEventScheduleAbsOSTimer(struct OBJTMR *pTmr, PTMR_EVENT pEvent, NvU64 timeAbs) { @@ -636,14 +695,13 @@ static inline NV_STATUS tmrEventScheduleAbsOSTimer(struct OBJTMR *pTmr, PTMR_EVE return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_objtmr_h_disabled -#define tmrEventScheduleAbsOSTimer(pTmr, pEvent, timeAbs) tmrEventScheduleAbsOSTimer_46f6a7(pTmr, pEvent, timeAbs) +#define tmrEventScheduleAbsOSTimer(pTmr, pEvent, timeAbs) tmrEventScheduleAbsOSTimer_OSTIMER(pTmr, pEvent, timeAbs) #endif //__nvoc_objtmr_h_disabled #define tmrEventScheduleAbsOSTimer_HAL(pTmr, pEvent, timeAbs) tmrEventScheduleAbsOSTimer(pTmr, pEvent, timeAbs) -static inline NV_STATUS tmrEventServiceOSTimerCallback_46f6a7(OBJGPU *pGpu, struct OBJTMR *pTmr, PTMR_EVENT pEvent) { - return NV_ERR_NOT_SUPPORTED; -} +NV_STATUS tmrEventServiceOSTimerCallback_OSTIMER(OBJGPU *pGpu, struct OBJTMR *pTmr, PTMR_EVENT pEvent); + #ifdef __nvoc_objtmr_h_disabled static inline NV_STATUS tmrEventServiceOSTimerCallback(OBJGPU *pGpu, struct OBJTMR *pTmr, PTMR_EVENT pEvent) { @@ -651,14 +709,13 @@ static inline NV_STATUS tmrEventServiceOSTimerCallback(OBJGPU *pGpu, struct OBJT return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_objtmr_h_disabled -#define tmrEventServiceOSTimerCallback(pGpu, pTmr, pEvent) tmrEventServiceOSTimerCallback_46f6a7(pGpu, pTmr, pEvent) +#define tmrEventServiceOSTimerCallback(pGpu, pTmr, pEvent) tmrEventServiceOSTimerCallback_OSTIMER(pGpu, pTmr, pEvent) #endif //__nvoc_objtmr_h_disabled #define tmrEventServiceOSTimerCallback_HAL(pGpu, pTmr, pEvent) tmrEventServiceOSTimerCallback(pGpu, pTmr, pEvent) -static inline NV_STATUS tmrEventCancelOSTimer_46f6a7(struct OBJTMR *pTmr, PTMR_EVENT pEvent) { - return NV_ERR_NOT_SUPPORTED; -} +NV_STATUS tmrEventCancelOSTimer_OSTIMER(struct OBJTMR *pTmr, PTMR_EVENT pEvent); + #ifdef __nvoc_objtmr_h_disabled static inline NV_STATUS tmrEventCancelOSTimer(struct OBJTMR *pTmr, PTMR_EVENT pEvent) { @@ -666,14 +723,13 @@ static inline NV_STATUS tmrEventCancelOSTimer(struct OBJTMR *pTmr, PTMR_EVENT pE return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_objtmr_h_disabled -#define tmrEventCancelOSTimer(pTmr, pEvent) tmrEventCancelOSTimer_46f6a7(pTmr, pEvent) +#define tmrEventCancelOSTimer(pTmr, pEvent) tmrEventCancelOSTimer_OSTIMER(pTmr, pEvent) #endif //__nvoc_objtmr_h_disabled #define tmrEventCancelOSTimer_HAL(pTmr, pEvent) tmrEventCancelOSTimer(pTmr, pEvent) -static inline NV_STATUS tmrEventDestroyOSTimer_46f6a7(struct OBJTMR *pTmr, PTMR_EVENT pEvent) { - return NV_ERR_NOT_SUPPORTED; -} +NV_STATUS tmrEventDestroyOSTimer_OSTIMER(struct OBJTMR *pTmr, PTMR_EVENT pEvent); + #ifdef __nvoc_objtmr_h_disabled static inline NV_STATUS tmrEventDestroyOSTimer(struct OBJTMR *pTmr, PTMR_EVENT pEvent) { @@ -681,14 +737,14 @@ static inline NV_STATUS tmrEventDestroyOSTimer(struct OBJTMR *pTmr, PTMR_EVENT p return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_objtmr_h_disabled -#define tmrEventDestroyOSTimer(pTmr, pEvent) tmrEventDestroyOSTimer_46f6a7(pTmr, pEvent) +#define tmrEventDestroyOSTimer(pTmr, pEvent) tmrEventDestroyOSTimer_OSTIMER(pTmr, pEvent) #endif //__nvoc_objtmr_h_disabled #define tmrEventDestroyOSTimer_HAL(pTmr, pEvent) tmrEventDestroyOSTimer(pTmr, pEvent) -void tmrRegisterIntrService_IMPL(OBJGPU *pGpu, struct OBJTMR *pTmr, IntrServiceRecord pRecords[155]); +void tmrRegisterIntrService_IMPL(OBJGPU *pGpu, struct OBJTMR *pTmr, IntrServiceRecord pRecords[163]); -static inline void tmrRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pTmr, IntrServiceRecord pRecords[155]) { +static inline void tmrRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pTmr, IntrServiceRecord pRecords[163]) { pTmr->__tmrRegisterIntrService__(pGpu, pTmr, pRecords); } @@ -706,10 +762,6 @@ NvU32 tmrServiceInterrupt_TU102(OBJGPU *pGpu, struct OBJTMR *pTmr, IntrServiceSe NvU32 tmrServiceInterrupt_GA100(OBJGPU *pGpu, struct OBJTMR *pTmr, IntrServiceServiceInterruptArguments *pParams); -static inline NvU32 tmrServiceInterrupt_46f6a7(OBJGPU *pGpu, struct OBJTMR *pTmr, IntrServiceServiceInterruptArguments *pParams) { - return NV_ERR_NOT_SUPPORTED; -} - static inline NvU32 tmrServiceInterrupt_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pTmr, IntrServiceServiceInterruptArguments *pParams) { return pTmr->__tmrServiceInterrupt__(pGpu, pTmr, pParams); } @@ -750,26 +802,14 @@ static inline void tmrStateDestroy_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pTmr) { pTmr->__tmrStateDestroy__(pGpu, pTmr); } -static inline NV_STATUS tmrSetCurrentTime_56cd7a(OBJGPU *pGpu, struct OBJTMR *pTmr) { - return NV_OK; -} - NV_STATUS tmrSetCurrentTime_GV100(OBJGPU *pGpu, struct OBJTMR *pTmr); NV_STATUS tmrSetCurrentTime_GH100(OBJGPU *pGpu, struct OBJTMR *pTmr); -static inline NV_STATUS tmrSetCurrentTime_46f6a7(OBJGPU *pGpu, struct OBJTMR *pTmr) { - return NV_ERR_NOT_SUPPORTED; -} - static inline NV_STATUS tmrSetCurrentTime_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pTmr) { return pTmr->__tmrSetCurrentTime__(pGpu, pTmr); } -static inline NvU64 tmrGetTimeEx_fa6bbe(OBJGPU *pGpu, struct OBJTMR *pTmr, struct THREAD_STATE_NODE *arg0) { - return osGetTimestamp(); -} - NvU64 tmrGetTimeEx_GM107(OBJGPU *pGpu, struct OBJTMR *pTmr, struct THREAD_STATE_NODE *arg0); NvU64 tmrGetTimeEx_GH100(OBJGPU *pGpu, struct OBJTMR *pTmr, struct THREAD_STATE_NODE *arg0); @@ -784,10 +824,6 @@ static inline NV_STATUS tmrSetCountdownIntrDisable_56cd7a(OBJGPU *pGpu, struct O return NV_OK; } -static inline NV_STATUS tmrSetCountdownIntrDisable_46f6a7(OBJGPU *pGpu, struct OBJTMR *pTmr) { - return NV_ERR_NOT_SUPPORTED; -} - static inline NV_STATUS tmrSetCountdownIntrDisable_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pTmr) { return pTmr->__tmrSetCountdownIntrDisable__(pGpu, pTmr); } @@ -796,10 +832,6 @@ NV_STATUS tmrSetCountdown_TU102(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU32 arg0, N NV_STATUS tmrSetCountdown_GH100(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); -static inline NV_STATUS tmrSetCountdown_46f6a7(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2) { - return NV_ERR_NOT_SUPPORTED; -} - static inline NV_STATUS tmrSetCountdown_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2) { return pTmr->__tmrSetCountdown__(pGpu, pTmr, arg0, arg1, arg2); } @@ -818,54 +850,16 @@ NV_STATUS tmrGetGpuPtimerOffset_TU102(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU32 * NV_STATUS tmrGetGpuPtimerOffset_GA100(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU32 *arg0, NvU32 *arg1); -static inline NV_STATUS tmrGetGpuPtimerOffset_46f6a7(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU32 *arg0, NvU32 *arg1) { - return NV_ERR_NOT_SUPPORTED; -} - -static inline NV_STATUS tmrGetGpuPtimerOffset_5baef9(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU32 *arg0, NvU32 *arg1) { - NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); -} - static inline NV_STATUS tmrGetGpuPtimerOffset_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU32 *arg0, NvU32 *arg1) { return pTmr->__tmrGetGpuPtimerOffset__(pGpu, pTmr, arg0, arg1); } -static inline NV_STATUS tmrGetPhysicalIntrVectors_46f6a7(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU32 maxIntrs, NvU32 *pIntrs, NvU32 *pMcEngineIdxs, NvU32 *pCount) { - return NV_ERR_NOT_SUPPORTED; -} - -NV_STATUS tmrGetPhysicalIntrVectors_GH100(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU32 maxIntrs, NvU32 *pIntrs, NvU32 *pMcEngineIdxs, NvU32 *pCount); - -static inline NV_STATUS tmrGetPhysicalIntrVectors_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU32 maxIntrs, NvU32 *pIntrs, NvU32 *pMcEngineIdxs, NvU32 *pCount) { - return pTmr->__tmrGetPhysicalIntrVectors__(pGpu, pTmr, maxIntrs, pIntrs, pMcEngineIdxs, pCount); -} - -static inline void tmrFreeTunableState_DISPATCH(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunableState) { - pEngstate->__tmrFreeTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS tmrCompareTunableState_DISPATCH(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__tmrCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline NV_STATUS tmrGetNotificationIntrVector_DISPATCH(struct OBJGPU *pGpu, struct OBJTMR *pIntrable, NvU32 *pIntrVector) { - return pIntrable->__tmrGetNotificationIntrVector__(pGpu, pIntrable, pIntrVector); -} - -static inline NvBool tmrIsPresent_DISPATCH(POBJGPU pGpu, struct OBJTMR *pEngstate) { - return pEngstate->__tmrIsPresent__(pGpu, pEngstate); -} - static inline NV_STATUS tmrReconcileTunableState_DISPATCH(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunableState) { return pEngstate->__tmrReconcileTunableState__(pGpu, pEngstate, pTunableState); } -static inline NV_STATUS tmrGetKernelIntrVectors_DISPATCH(struct OBJGPU *pGpu, struct OBJTMR *pIntrable, NvU32 maxIntrs, NvU32 *pIntrs, NvU32 *pMcEngineIdxs, NvU32 *pCount) { - return pIntrable->__tmrGetKernelIntrVectors__(pGpu, pIntrable, maxIntrs, pIntrs, pMcEngineIdxs, pCount); -} - -static inline NV_STATUS tmrSetNotificationIntrVector_DISPATCH(struct OBJGPU *pGpu, struct OBJTMR *pIntrable, NvU32 intrVector) { - return pIntrable->__tmrSetNotificationIntrVector__(pGpu, pIntrable, intrVector); +static inline NV_STATUS tmrServiceNotificationInterrupt_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pIntrService, IntrServiceServiceNotificationInterruptArguments *pParams) { + return pIntrService->__tmrServiceNotificationInterrupt__(pGpu, pIntrService, pParams); } static inline NV_STATUS tmrStatePreLoad_DISPATCH(POBJGPU pGpu, struct OBJTMR *pEngstate, NvU32 arg0) { @@ -880,10 +874,6 @@ static inline NV_STATUS tmrStatePreUnload_DISPATCH(POBJGPU pGpu, struct OBJTMR * return pEngstate->__tmrStatePreUnload__(pGpu, pEngstate, arg0); } -static inline NV_STATUS tmrGetTunableState_DISPATCH(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunableState) { - return pEngstate->__tmrGetTunableState__(pGpu, pEngstate, pTunableState); -} - static inline void tmrInitMissing_DISPATCH(POBJGPU pGpu, struct OBJTMR *pEngstate) { pEngstate->__tmrInitMissing__(pGpu, pEngstate); } @@ -896,8 +886,16 @@ static inline NV_STATUS tmrStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct OB return pEngstate->__tmrStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS tmrServiceNotificationInterrupt_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pIntrService, IntrServiceServiceNotificationInterruptArguments *pParams) { - return pIntrService->__tmrServiceNotificationInterrupt__(pGpu, pIntrService, pParams); +static inline NV_STATUS tmrGetTunableState_DISPATCH(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunableState) { + return pEngstate->__tmrGetTunableState__(pGpu, pEngstate, pTunableState); +} + +static inline NV_STATUS tmrCompareTunableState_DISPATCH(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunables1, void *pTunables2) { + return pEngstate->__tmrCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); +} + +static inline void tmrFreeTunableState_DISPATCH(POBJGPU pGpu, struct OBJTMR *pEngstate, void *pTunableState) { + pEngstate->__tmrFreeTunableState__(pGpu, pEngstate, pTunableState); } static inline NV_STATUS tmrStatePostLoad_DISPATCH(POBJGPU pGpu, struct OBJTMR *pEngstate, NvU32 arg0) { @@ -912,6 +910,10 @@ static inline NV_STATUS tmrSetTunableState_DISPATCH(POBJGPU pGpu, struct OBJTMR return pEngstate->__tmrSetTunableState__(pGpu, pEngstate, pTunableState); } +static inline NvBool tmrIsPresent_DISPATCH(POBJGPU pGpu, struct OBJTMR *pEngstate) { + return pEngstate->__tmrIsPresent__(pGpu, pEngstate); +} + static inline NvBool tmrServiceSwrlCallbacksPmcTree(OBJGPU *pGpu, struct OBJTMR *pTmr, struct THREAD_STATE_NODE *arg0) { return ((NvBool)(0 != 0)); } @@ -929,8 +931,10 @@ static inline NvBool tmrServiceSwrlWrapper(OBJGPU *pGpu, struct OBJTMR *pTmr, MC } void tmrDestruct_IMPL(struct OBJTMR *pTmr); + #define __nvoc_tmrDestruct(pTmr) tmrDestruct_IMPL(pTmr) NV_STATUS tmrEventCreate_IMPL(struct OBJTMR *pTmr, PTMR_EVENT *ppEvent, TIMEPROC callbackFn, void *pUserData, NvU32 flags); + #ifdef __nvoc_objtmr_h_disabled static inline NV_STATUS tmrEventCreate(struct OBJTMR *pTmr, PTMR_EVENT *ppEvent, TIMEPROC callbackFn, void *pUserData, NvU32 flags) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -941,6 +945,7 @@ static inline NV_STATUS tmrEventCreate(struct OBJTMR *pTmr, PTMR_EVENT *ppEvent, #endif //__nvoc_objtmr_h_disabled void tmrEventCancel_IMPL(struct OBJTMR *pTmr, PTMR_EVENT pEvent); + #ifdef __nvoc_objtmr_h_disabled static inline void tmrEventCancel(struct OBJTMR *pTmr, PTMR_EVENT pEvent) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -950,6 +955,7 @@ static inline void tmrEventCancel(struct OBJTMR *pTmr, PTMR_EVENT pEvent) { #endif //__nvoc_objtmr_h_disabled void tmrEventDestroy_IMPL(struct OBJTMR *pTmr, PTMR_EVENT pEvent); + #ifdef __nvoc_objtmr_h_disabled static inline void tmrEventDestroy(struct OBJTMR *pTmr, PTMR_EVENT pEvent) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -959,6 +965,7 @@ static inline void tmrEventDestroy(struct OBJTMR *pTmr, PTMR_EVENT pEvent) { #endif //__nvoc_objtmr_h_disabled void tmrInitCallbacks_IMPL(struct OBJTMR *pTmr); + #ifdef __nvoc_objtmr_h_disabled static inline void tmrInitCallbacks(struct OBJTMR *pTmr) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -968,6 +975,7 @@ static inline void tmrInitCallbacks(struct OBJTMR *pTmr) { #endif //__nvoc_objtmr_h_disabled void tmrSetCountdownCallback_IMPL(struct OBJTMR *pTmr, TIMEPROC_COUNTDOWN arg0); + #ifdef __nvoc_objtmr_h_disabled static inline void tmrSetCountdownCallback(struct OBJTMR *pTmr, TIMEPROC_COUNTDOWN arg0) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -977,6 +985,7 @@ static inline void tmrSetCountdownCallback(struct OBJTMR *pTmr, TIMEPROC_COUNTDO #endif //__nvoc_objtmr_h_disabled NV_STATUS tmrCancelCallback_IMPL(struct OBJTMR *pTmr, void *pObject); + #ifdef __nvoc_objtmr_h_disabled static inline NV_STATUS tmrCancelCallback(struct OBJTMR *pTmr, void *pObject) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -987,6 +996,7 @@ static inline NV_STATUS tmrCancelCallback(struct OBJTMR *pTmr, void *pObject) { #endif //__nvoc_objtmr_h_disabled NV_STATUS tmrGetCurrentDiffTime_IMPL(struct OBJTMR *pTmr, NvU64 arg0, NvU64 *arg1); + #ifdef __nvoc_objtmr_h_disabled static inline NV_STATUS tmrGetCurrentDiffTime(struct OBJTMR *pTmr, NvU64 arg0, NvU64 *arg1) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -997,6 +1007,7 @@ static inline NV_STATUS tmrGetCurrentDiffTime(struct OBJTMR *pTmr, NvU64 arg0, N #endif //__nvoc_objtmr_h_disabled void tmrGetSystemTime_IMPL(struct OBJTMR *pTmr, PDAYMSECTIME pTime); + #ifdef __nvoc_objtmr_h_disabled static inline void tmrGetSystemTime(struct OBJTMR *pTmr, PDAYMSECTIME pTime) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -1006,6 +1017,7 @@ static inline void tmrGetSystemTime(struct OBJTMR *pTmr, PDAYMSECTIME pTime) { #endif //__nvoc_objtmr_h_disabled NvBool tmrCheckCallbacksReleaseSem_IMPL(struct OBJTMR *pTmr, NvU32 chId); + #ifdef __nvoc_objtmr_h_disabled static inline NvBool tmrCheckCallbacksReleaseSem(struct OBJTMR *pTmr, NvU32 chId) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -1016,6 +1028,7 @@ static inline NvBool tmrCheckCallbacksReleaseSem(struct OBJTMR *pTmr, NvU32 chId #endif //__nvoc_objtmr_h_disabled NvBool tmrDiffExceedsTime_IMPL(struct OBJTMR *pTmr, PDAYMSECTIME pFutureTime, PDAYMSECTIME pPastTime, NvU32 time); + #ifdef __nvoc_objtmr_h_disabled static inline NvBool tmrDiffExceedsTime(struct OBJTMR *pTmr, PDAYMSECTIME pFutureTime, PDAYMSECTIME pPastTime, NvU32 time) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -1026,6 +1039,7 @@ static inline NvBool tmrDiffExceedsTime(struct OBJTMR *pTmr, PDAYMSECTIME pFutur #endif //__nvoc_objtmr_h_disabled NV_STATUS tmrEventScheduleAbs_IMPL(struct OBJTMR *pTmr, PTMR_EVENT pEvent, NvU64 timeAbs); + #ifdef __nvoc_objtmr_h_disabled static inline NV_STATUS tmrEventScheduleAbs(struct OBJTMR *pTmr, PTMR_EVENT pEvent, NvU64 timeAbs) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -1036,6 +1050,7 @@ static inline NV_STATUS tmrEventScheduleAbs(struct OBJTMR *pTmr, PTMR_EVENT pEve #endif //__nvoc_objtmr_h_disabled NV_STATUS tmrScheduleCallbackAbs_IMPL(struct OBJTMR *pTmr, TIMEPROC_OBSOLETE arg0, void *arg1, NvU64 arg2, NvU32 arg3, NvU32 arg4); + #ifdef __nvoc_objtmr_h_disabled static inline NV_STATUS tmrScheduleCallbackAbs(struct OBJTMR *pTmr, TIMEPROC_OBSOLETE arg0, void *arg1, NvU64 arg2, NvU32 arg3, NvU32 arg4) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -1046,6 +1061,7 @@ static inline NV_STATUS tmrScheduleCallbackAbs(struct OBJTMR *pTmr, TIMEPROC_OBS #endif //__nvoc_objtmr_h_disabled NV_STATUS tmrEventScheduleRel_IMPL(struct OBJTMR *pTmr, PTMR_EVENT pEvent, NvU64 timeRel); + #ifdef __nvoc_objtmr_h_disabled static inline NV_STATUS tmrEventScheduleRel(struct OBJTMR *pTmr, PTMR_EVENT pEvent, NvU64 timeRel) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -1056,6 +1072,7 @@ static inline NV_STATUS tmrEventScheduleRel(struct OBJTMR *pTmr, PTMR_EVENT pEve #endif //__nvoc_objtmr_h_disabled NV_STATUS tmrScheduleCallbackRel_IMPL(struct OBJTMR *pTmr, TIMEPROC_OBSOLETE arg0, void *arg1, NvU64 arg2, NvU32 arg3, NvU32 arg4); + #ifdef __nvoc_objtmr_h_disabled static inline NV_STATUS tmrScheduleCallbackRel(struct OBJTMR *pTmr, TIMEPROC_OBSOLETE arg0, void *arg1, NvU64 arg2, NvU32 arg3, NvU32 arg4) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -1066,6 +1083,7 @@ static inline NV_STATUS tmrScheduleCallbackRel(struct OBJTMR *pTmr, TIMEPROC_OBS #endif //__nvoc_objtmr_h_disabled NV_STATUS tmrScheduleCallbackRelSec_IMPL(struct OBJTMR *pTmr, TIMEPROC_OBSOLETE arg0, void *arg1, NvU32 arg2, NvU32 arg3, NvU32 arg4); + #ifdef __nvoc_objtmr_h_disabled static inline NV_STATUS tmrScheduleCallbackRelSec(struct OBJTMR *pTmr, TIMEPROC_OBSOLETE arg0, void *arg1, NvU32 arg2, NvU32 arg3, NvU32 arg4) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -1076,6 +1094,7 @@ static inline NV_STATUS tmrScheduleCallbackRelSec(struct OBJTMR *pTmr, TIMEPROC_ #endif //__nvoc_objtmr_h_disabled NvBool tmrEventOnList_IMPL(struct OBJTMR *pTmr, PTMR_EVENT pEvent); + #ifdef __nvoc_objtmr_h_disabled static inline NvBool tmrEventOnList(struct OBJTMR *pTmr, PTMR_EVENT pEvent) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -1086,6 +1105,7 @@ static inline NvBool tmrEventOnList(struct OBJTMR *pTmr, PTMR_EVENT pEvent) { #endif //__nvoc_objtmr_h_disabled NvBool tmrCallbackOnList_IMPL(struct OBJTMR *pTmr, TIMEPROC_OBSOLETE arg0, void *arg1); + #ifdef __nvoc_objtmr_h_disabled static inline NvBool tmrCallbackOnList(struct OBJTMR *pTmr, TIMEPROC_OBSOLETE arg0, void *arg1) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -1096,6 +1116,7 @@ static inline NvBool tmrCallbackOnList(struct OBJTMR *pTmr, TIMEPROC_OBSOLETE ar #endif //__nvoc_objtmr_h_disabled void tmrRmCallbackIntrEnable_IMPL(struct OBJTMR *pTmr, OBJGPU *pGpu); + #ifdef __nvoc_objtmr_h_disabled static inline void tmrRmCallbackIntrEnable(struct OBJTMR *pTmr, OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -1105,6 +1126,7 @@ static inline void tmrRmCallbackIntrEnable(struct OBJTMR *pTmr, OBJGPU *pGpu) { #endif //__nvoc_objtmr_h_disabled void tmrRmCallbackIntrDisable_IMPL(struct OBJTMR *pTmr, OBJGPU *pGpu); + #ifdef __nvoc_objtmr_h_disabled static inline void tmrRmCallbackIntrDisable(struct OBJTMR *pTmr, OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -1114,6 +1136,7 @@ static inline void tmrRmCallbackIntrDisable(struct OBJTMR *pTmr, OBJGPU *pGpu) { #endif //__nvoc_objtmr_h_disabled NV_STATUS tmrTimeUntilNextCallback_IMPL(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU64 *pTimeUntilCallbackNs); + #ifdef __nvoc_objtmr_h_disabled static inline NV_STATUS tmrTimeUntilNextCallback(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU64 *pTimeUntilCallbackNs) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -1124,6 +1147,7 @@ static inline NV_STATUS tmrTimeUntilNextCallback(OBJGPU *pGpu, struct OBJTMR *pT #endif //__nvoc_objtmr_h_disabled NvBool tmrCallExpiredCallbacks_IMPL(OBJGPU *pGpu, struct OBJTMR *pTmr); + #ifdef __nvoc_objtmr_h_disabled static inline NvBool tmrCallExpiredCallbacks(OBJGPU *pGpu, struct OBJTMR *pTmr) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -1134,6 +1158,7 @@ static inline NvBool tmrCallExpiredCallbacks(OBJGPU *pGpu, struct OBJTMR *pTmr) #endif //__nvoc_objtmr_h_disabled void tmrResetCallbackInterrupt_IMPL(OBJGPU *pGpu, struct OBJTMR *pTmr); + #ifdef __nvoc_objtmr_h_disabled static inline void tmrResetCallbackInterrupt(OBJGPU *pGpu, struct OBJTMR *pTmr) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -1143,6 +1168,7 @@ static inline void tmrResetCallbackInterrupt(OBJGPU *pGpu, struct OBJTMR *pTmr) #endif //__nvoc_objtmr_h_disabled NvBool tmrGetCallbackInterruptPending_IMPL(OBJGPU *pGpu, struct OBJTMR *pTmr); + #ifdef __nvoc_objtmr_h_disabled static inline NvBool tmrGetCallbackInterruptPending(OBJGPU *pGpu, struct OBJTMR *pTmr) { NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); @@ -1160,8 +1186,6 @@ NV_STATUS tmrCtrlCmdEventSchedule(OBJGPU *pGpu, TMR_EVENT_SCHEDULE_PARAMS *pPara NV_STATUS tmrCtrlCmdEventCancel(OBJGPU *pGpu, TMR_EVENT_GENERAL_PARAMS *pParams); NV_STATUS tmrCtrlCmdEventDestroy(OBJGPU *pGpu, TMR_EVENT_GENERAL_PARAMS *pParams); -NV_STATUS tmrDelay_OSTIMER(struct OBJTMR *pTmr, NvU32 nsec); - #endif // _OBJTMR_H_ #ifdef __cplusplus diff --git a/src/nvidia/generated/g_odb.h b/src/nvidia/generated/g_odb.h index 28aa96fce..e1b30513b 100644 --- a/src/nvidia/generated/g_odb.h +++ b/src/nvidia/generated/g_odb.h @@ -15,12 +15,6 @@ typedef struct OBJGPIO OBJGPIO; #endif /* __NVOC_CLASS_OBJGPIO_TYPEDEF__ */ typedef struct OBJGPIO *POBJGPIO; -#ifndef __NVOC_CLASS_OBJOS_TYPEDEF__ -#define __NVOC_CLASS_OBJOS_TYPEDEF__ -typedef struct OBJOS OBJOS; -#endif /* __NVOC_CLASS_OBJOS_TYPEDEF__ */ -typedef struct OBJOS *POBJOS; - #ifndef __NVOC_CLASS_OBJRPC_TYPEDEF__ #define __NVOC_CLASS_OBJRPC_TYPEDEF__ typedef struct OBJRPC OBJRPC; @@ -56,7 +50,6 @@ typedef struct OBJDISP *POBJDISP; // #define staticCast(pObj, TYPE) ((pObj)? __staticCast_##TYPE((pObj)) : NULL) // #define __staticCast_OBJGPIO(pObj) ((pObj)->__iom_pbase_OBJGPIO) -#define __staticCast_OBJOS(pObj) ((pObj)->__iom_pbase_OBJOS) #define __staticCast_OBJRPC(pObj) ((pObj)->__iom_pbase_OBJRPC) #define __staticCast_OBJRPCSTRUCTURECOPY(pObj) ((pObj)->__iom_pbase_OBJRPCSTRUCTURECOPY) @@ -65,7 +58,6 @@ typedef struct OBJDISP *POBJDISP; // #define dynamicCast(pObj, TYPE) (__dynamicCast_##TYPE((pObj))) // #define __dynamicCast_OBJGPIO(pObj) NULL -#define __dynamicCast_OBJOS(pObj) ((POBJOS)__nvoc_dynamicCast(staticCast((pObj), Dynamic), classInfo(OBJOS))) #define __dynamicCast_OBJRPC(pObj) ((POBJRPC)__nvoc_dynamicCast(staticCast((pObj), Dynamic), classInfo(OBJRPC))) #define __dynamicCast_OBJRPCSTRUCTURECOPY(pObj) NULL @@ -89,45 +81,6 @@ typedef struct OBJDISP *POBJDISP; #define PDB_PROP_GPIO_RM_PMU_GPIO_SYNC_ENABLED_DEF_BASE_CAST #define PDB_PROP_GPIO_RM_PMU_GPIO_SYNC_ENABLED_DEF_BASE_NAME pdb.PDB_PROP_GPIO_RM_PMU_GPIO_SYNC_ENABLED_DEF -#define PDB_PROP_OS_CACHED_MEMORY_MAPPINGS_FOR_ACPI_TABLE_BASE_CAST -#define PDB_PROP_OS_CACHED_MEMORY_MAPPINGS_FOR_ACPI_TABLE_BASE_NAME pdb.PDB_PROP_OS_CACHED_MEMORY_MAPPINGS_FOR_ACPI_TABLE - -#define PDB_PROP_OS_DOES_NOT_ALLOW_DIRECT_PCIE_MAPPINGS_BASE_CAST -#define PDB_PROP_OS_DOES_NOT_ALLOW_DIRECT_PCIE_MAPPINGS_BASE_NAME pdb.PDB_PROP_OS_DOES_NOT_ALLOW_DIRECT_PCIE_MAPPINGS - -#define PDB_PROP_OS_GET_ACPI_TABLE_FROM_UEFI_BASE_CAST -#define PDB_PROP_OS_GET_ACPI_TABLE_FROM_UEFI_BASE_NAME pdb.PDB_PROP_OS_GET_ACPI_TABLE_FROM_UEFI - -#define PDB_PROP_OS_LIMIT_GPU_RESET_BASE_CAST -#define PDB_PROP_OS_LIMIT_GPU_RESET_BASE_NAME pdb.PDB_PROP_OS_LIMIT_GPU_RESET - -#define PDB_PROP_OS_NO_PAGED_SEGMENT_ACCESS_BASE_CAST -#define PDB_PROP_OS_NO_PAGED_SEGMENT_ACCESS_BASE_NAME pdb.PDB_PROP_OS_NO_PAGED_SEGMENT_ACCESS - -#define PDB_PROP_OS_ONDEMAND_VBLANK_CONTROL_ENABLE_DEFAULT_BASE_CAST -#define PDB_PROP_OS_ONDEMAND_VBLANK_CONTROL_ENABLE_DEFAULT_BASE_NAME pdb.PDB_PROP_OS_ONDEMAND_VBLANK_CONTROL_ENABLE_DEFAULT - -#define PDB_PROP_OS_PAT_UNSUPPORTED_BASE_CAST -#define PDB_PROP_OS_PAT_UNSUPPORTED_BASE_NAME pdb.PDB_PROP_OS_PAT_UNSUPPORTED - -#define PDB_PROP_OS_SLI_ALLOWED_BASE_CAST -#define PDB_PROP_OS_SLI_ALLOWED_BASE_NAME pdb.PDB_PROP_OS_SLI_ALLOWED - -#define PDB_PROP_OS_SUPPORTS_DISPLAY_REMAPPER_BASE_CAST -#define PDB_PROP_OS_SUPPORTS_DISPLAY_REMAPPER_BASE_NAME pdb.PDB_PROP_OS_SUPPORTS_DISPLAY_REMAPPER - -#define PDB_PROP_OS_SUPPORTS_TDR_BASE_CAST -#define PDB_PROP_OS_SUPPORTS_TDR_BASE_NAME pdb.PDB_PROP_OS_SUPPORTS_TDR - -#define PDB_PROP_OS_SYSTEM_EVENTS_SUPPORTED_BASE_CAST -#define PDB_PROP_OS_SYSTEM_EVENTS_SUPPORTED_BASE_NAME pdb.PDB_PROP_OS_SYSTEM_EVENTS_SUPPORTED - -#define PDB_PROP_OS_UNCACHED_MEMORY_MAPPINGS_NOT_SUPPORTED_BASE_CAST -#define PDB_PROP_OS_UNCACHED_MEMORY_MAPPINGS_NOT_SUPPORTED_BASE_NAME pdb.PDB_PROP_OS_UNCACHED_MEMORY_MAPPINGS_NOT_SUPPORTED - -#define PDB_PROP_OS_WAIT_FOR_ACPI_SUBSYSTEM_BASE_CAST -#define PDB_PROP_OS_WAIT_FOR_ACPI_SUBSYSTEM_BASE_NAME pdb.PDB_PROP_OS_WAIT_FOR_ACPI_SUBSYSTEM - #endif // _G_ODB_H_ diff --git a/src/nvidia/generated/g_os_desc_mem_nvoc.c b/src/nvidia/generated/g_os_desc_mem_nvoc.c index c7e904759..1f8ef56ba 100644 --- a/src/nvidia/generated/g_os_desc_mem_nvoc.c +++ b/src/nvidia/generated/g_os_desc_mem_nvoc.c @@ -145,8 +145,12 @@ static NV_STATUS __nvoc_thunk_RmResource_osdescControl_Prologue(struct OsDescMem return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_Memory_osdescIsReady(struct OsDescMemory *pMemory) { - return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset)); +static NvBool __nvoc_thunk_Memory_osdescIsGpuMapAllowed(struct OsDescMemory *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), pGpu); +} + +static NV_STATUS __nvoc_thunk_Memory_osdescIsReady(struct OsDescMemory *pMemory, NvBool bCopyConstructorContext) { + return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), bCopyConstructorContext); } static NV_STATUS __nvoc_thunk_Memory_osdescCheckCopyPermissions(struct OsDescMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { @@ -157,6 +161,10 @@ static void __nvoc_thunk_RsResource_osdescPreDestruct(struct OsDescMemory *pReso resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_Memory_osdescIsDuplicate(struct OsDescMemory *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), hMemory, pDuplicate); +} + static NV_STATUS __nvoc_thunk_RsResource_osdescUnmapFrom(struct OsDescMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RsResource.offset), pParams); } @@ -243,12 +251,16 @@ static void __nvoc_init_funcTable_OsDescMemory_1(OsDescMemory *pThis) { pThis->__osdescControl_Prologue__ = &__nvoc_thunk_RmResource_osdescControl_Prologue; + pThis->__osdescIsGpuMapAllowed__ = &__nvoc_thunk_Memory_osdescIsGpuMapAllowed; + pThis->__osdescIsReady__ = &__nvoc_thunk_Memory_osdescIsReady; pThis->__osdescCheckCopyPermissions__ = &__nvoc_thunk_Memory_osdescCheckCopyPermissions; pThis->__osdescPreDestruct__ = &__nvoc_thunk_RsResource_osdescPreDestruct; + pThis->__osdescIsDuplicate__ = &__nvoc_thunk_Memory_osdescIsDuplicate; + pThis->__osdescUnmapFrom__ = &__nvoc_thunk_RsResource_osdescUnmapFrom; pThis->__osdescControl_Epilogue__ = &__nvoc_thunk_RmResource_osdescControl_Epilogue; diff --git a/src/nvidia/generated/g_os_desc_mem_nvoc.h b/src/nvidia/generated/g_os_desc_mem_nvoc.h index 863bdba1f..8566e9a7f 100644 --- a/src/nvidia/generated/g_os_desc_mem_nvoc.h +++ b/src/nvidia/generated/g_os_desc_mem_nvoc.h @@ -66,9 +66,11 @@ struct OsDescMemory { NvU32 (*__osdescGetRefCount__)(struct OsDescMemory *); NV_STATUS (*__osdescMapTo__)(struct OsDescMemory *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__osdescControl_Prologue__)(struct OsDescMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__osdescIsReady__)(struct OsDescMemory *); + NvBool (*__osdescIsGpuMapAllowed__)(struct OsDescMemory *, struct OBJGPU *); + NV_STATUS (*__osdescIsReady__)(struct OsDescMemory *, NvBool); NV_STATUS (*__osdescCheckCopyPermissions__)(struct OsDescMemory *, struct OBJGPU *, NvHandle); void (*__osdescPreDestruct__)(struct OsDescMemory *); + NV_STATUS (*__osdescIsDuplicate__)(struct OsDescMemory *, NvHandle, NvBool *); NV_STATUS (*__osdescUnmapFrom__)(struct OsDescMemory *, RS_RES_UNMAP_FROM_PARAMS *); void (*__osdescControl_Epilogue__)(struct OsDescMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__osdescControlLookup__)(struct OsDescMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); @@ -117,9 +119,11 @@ NV_STATUS __nvoc_objCreate_OsDescMemory(OsDescMemory**, Dynamic*, NvU32, CALL_CO #define osdescGetRefCount(pResource) osdescGetRefCount_DISPATCH(pResource) #define osdescMapTo(pResource, pParams) osdescMapTo_DISPATCH(pResource, pParams) #define osdescControl_Prologue(pResource, pCallContext, pParams) osdescControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define osdescIsReady(pMemory) osdescIsReady_DISPATCH(pMemory) +#define osdescIsGpuMapAllowed(pMemory, pGpu) osdescIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define osdescIsReady(pMemory, bCopyConstructorContext) osdescIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define osdescCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) osdescCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) #define osdescPreDestruct(pResource) osdescPreDestruct_DISPATCH(pResource) +#define osdescIsDuplicate(pMemory, hMemory, pDuplicate) osdescIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) #define osdescUnmapFrom(pResource, pParams) osdescUnmapFrom_DISPATCH(pResource, pParams) #define osdescControl_Epilogue(pResource, pCallContext, pParams) osdescControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define osdescControlLookup(pResource, pParams, ppEntry) osdescControlLookup_DISPATCH(pResource, pParams, ppEntry) @@ -179,8 +183,12 @@ static inline NV_STATUS osdescControl_Prologue_DISPATCH(struct OsDescMemory *pRe return pResource->__osdescControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS osdescIsReady_DISPATCH(struct OsDescMemory *pMemory) { - return pMemory->__osdescIsReady__(pMemory); +static inline NvBool osdescIsGpuMapAllowed_DISPATCH(struct OsDescMemory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__osdescIsGpuMapAllowed__(pMemory, pGpu); +} + +static inline NV_STATUS osdescIsReady_DISPATCH(struct OsDescMemory *pMemory, NvBool bCopyConstructorContext) { + return pMemory->__osdescIsReady__(pMemory, bCopyConstructorContext); } static inline NV_STATUS osdescCheckCopyPermissions_DISPATCH(struct OsDescMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { @@ -191,6 +199,10 @@ static inline void osdescPreDestruct_DISPATCH(struct OsDescMemory *pResource) { pResource->__osdescPreDestruct__(pResource); } +static inline NV_STATUS osdescIsDuplicate_DISPATCH(struct OsDescMemory *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return pMemory->__osdescIsDuplicate__(pMemory, hMemory, pDuplicate); +} + static inline NV_STATUS osdescUnmapFrom_DISPATCH(struct OsDescMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return pResource->__osdescUnmapFrom__(pResource, pParams); } @@ -212,6 +224,7 @@ static inline NvBool osdescAccessCallback_DISPATCH(struct OsDescMemory *pResourc } NV_STATUS osdescConstruct_IMPL(struct OsDescMemory *arg_pOsDescMemory, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_osdescConstruct(arg_pOsDescMemory, arg_pCallContext, arg_pParams) osdescConstruct_IMPL(arg_pOsDescMemory, arg_pCallContext, arg_pParams) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_os_hal.h b/src/nvidia/generated/g_os_hal.h index ab875c8eb..f08fbb4bd 100644 --- a/src/nvidia/generated/g_os_hal.h +++ b/src/nvidia/generated/g_os_hal.h @@ -1,88 +1,10 @@ // This file is automatically generated by rmconfig - DO NOT EDIT! // -// Provides access to OS Hal interfaces. -// // Profile: shipping-gpus-openrm -// Haldef: os.def -// Template: templates/gt_eng_hal.h +// Template: templates/gt_eng_empty.h // - -#ifndef _G_OSHAL_H_ -#define _G_OSHAL_H_ - +// The file is added to smoonth NVOC migration. After converting a module to +// NVOC class, the stale generated headers in output directory causes failures +// of incremental builds. This file ensures the content of the old header is +// removed. // -// Typedefs for OS public object interfaces. -// - - - -// -// "struct" to list OS's public interfaces, eg: pOs->osInit(pGpu, pOs) -// - - - -// -// macro defines to directly access OS's OBJ interfaces, -// eg: #define osReadFoo(_pGpu, _pOs) _pOs->obj._osReadFoo(_pGpu, _pOs) -// - - - -// -// macro defines to access OS's function pointers, -// eg: #define osReadFoo_FNPTR(_pOs) _pOs->obj.__osReadFoo__ -// or #define osReadFoo_FNPTR(_pOs) _pOs->__osReadFoo__ -// - - - -// -// Typedefs for OS HAL interfaces. -// - - - -// -// struct to access OS's hal interfaces, eg: pOs->hal.osReadFoo(pGpu, pOs) -// - - - -// -// macro defines to directly access OS's hal interfaces, -// eg: #define osReadFoo_HAL(_pGpu, _pOs) _pOs->hal.osReadFoo(_pGpu, _pOs) -// - - - -// -// Inline stub function definitions. -// - - - -// -// OS PDB properties -// - -typedef struct PDB_PROP_OS { - - NvBool PDB_PROP_OS_PAT_UNSUPPORTED; - NvBool PDB_PROP_OS_SLI_ALLOWED; - NvBool PDB_PROP_OS_SYSTEM_EVENTS_SUPPORTED; - NvBool PDB_PROP_OS_ONDEMAND_VBLANK_CONTROL_ENABLE_DEFAULT; - NvBool PDB_PROP_OS_WAIT_FOR_ACPI_SUBSYSTEM; - NvBool PDB_PROP_OS_UNCACHED_MEMORY_MAPPINGS_NOT_SUPPORTED; - NvBool PDB_PROP_OS_CACHED_MEMORY_MAPPINGS_FOR_ACPI_TABLE; - NvBool PDB_PROP_OS_LIMIT_GPU_RESET; - NvBool PDB_PROP_OS_SUPPORTS_TDR; - NvBool PDB_PROP_OS_GET_ACPI_TABLE_FROM_UEFI; - NvBool PDB_PROP_OS_SUPPORTS_DISPLAY_REMAPPER; // Set if this OS supports the display remapper (otherwise force DNISO to vidmem if display can't access all of sysmem). - NvBool PDB_PROP_OS_DOES_NOT_ALLOW_DIRECT_PCIE_MAPPINGS; // The OS does not allow the driver to map the PCIE config space. - NvBool PDB_PROP_OS_NO_PAGED_SEGMENT_ACCESS; // Accessing paged segment might cause problem at some code path. Set the flag up on the code path to make it fail osPagedSegmentAccessCheck() - -} PDB_PROP_OS; - - -#endif // _G_OSHAL_H_ diff --git a/src/nvidia/generated/g_os_iom.c b/src/nvidia/generated/g_os_iom.c deleted file mode 100644 index 4022d37f9..000000000 --- a/src/nvidia/generated/g_os_iom.c +++ /dev/null @@ -1,199 +0,0 @@ -// This file is automatically generated by rmconfig - DO NOT EDIT! -// -// Profile: shipping-gpus-openrm -// Template: templates/gt_eng_iom.c -// -#include "nvstatus.h" -#include "nvport/inline/util_valist.h" -#include "nvport/nvport.h" -#include "core/core.h" -#include "nvoc/rtti.h" -#include "os/os.h" -#include "gpu/gpu.h" - -#include "os/os.h" - -#include "g_os_private.h" - -// -// OS's object-level _STUB, _MISSING, _VGPUSTUB interface routines -// (if any) -// - - - - - - - - -// -// Initialize OS's object-level interfaces -// -void -osSetPropertiesSpecial -( - POBJOS pOs -) -{ - // SET_IF support for OS's PDB properties - if (!RMCFG_FEATURE_PLATFORM_UNIX) { - pOs->setProperty(pOs, PDB_PROP_OS_SUPPORTS_DISPLAY_REMAPPER, NV_TRUE); - } - -} - - - - - -// -// OS's run-time type information -// - -extern const struct NVOC_CLASS_DEF __iom_class_def_OBJOS; -extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; - -void __iom_dtor_OBJOS(POBJOS); -NV_STATUS __iom_objCreate_OBJOS(POBJOS *ppThis, Dynamic *pParent, NvU32 createFlags); - -const struct NVOC_RTTI __iom_rtti_OBJOS_OBJOS = -{ - &__iom_class_def_OBJOS, - (NVOC_DYNAMIC_DTOR)&__iom_dtor_OBJOS, - 0, -}; - -const struct NVOC_RTTI __iom_rtti_OBJOS_Object = -{ - &__nvoc_class_def_Object, - (NVOC_DYNAMIC_DTOR)&__nvoc_destructFromBase, - NV_OFFSETOF(OBJOS, __nvoc_base_Object), -}; - -static const struct NVOC_CASTINFO __iom_castinfo_OBJOS = -{ - 2, - { - &__iom_rtti_OBJOS_OBJOS, - &__iom_rtti_OBJOS_Object - } -}; - -extern const NVOC_RTTI_PROVIDER __iom_rtti_provider; -const struct NVOC_CLASS_DEF __iom_class_def_OBJOS = -{ - { - sizeof(OBJOS), - classId(OBJOS), - &__iom_rtti_provider, -#if NV_PRINTF_STRINGS_ALLOWED - "OBJOS", -#endif - }, - (NVOC_DYNAMIC_OBJ_CREATE)&__iom_objCreate_OBJOS, - &__iom_castinfo_OBJOS, -}; - - - - -// -// OS's object infrastructure boilerplate -// - -// initializers, constructors, and destructors for OS's base classes -void __nvoc_init_Object(Object*); -NV_STATUS __nvoc_ctor_Object(Object*); -void __nvoc_dtor_Object(Object*); -NV_STATUS __nvoc_vctor_Object(Dynamic*, va_list); - - -NV_STATUS __iom_ctor_OBJOS(POBJOS pOs) -{ - NV_STATUS status; - RMCFG_MODULE_ENABLED_OR_ASSERT_AND_BAIL(OS); - status = __nvoc_ctor_Object(&pOs->__nvoc_base_Object); - if (status != NV_OK) goto __iom_ctor_OBJOS_fail_Object; - return NV_OK; -__iom_ctor_OBJOS_fail_Object: - return status; -} - -NV_STATUS __iom_vctor_OBJOS(Dynamic *pDynamic, va_list args) -{ - NV_STATUS status; - POBJOS pThis = dynamicCast(pDynamic, OBJOS); - if (pThis != NULL) - { - status = __iom_ctor_OBJOS(pThis); - } - else - { - status = NV_ERR_INVALID_OBJECT; - } - return status; -} - -void __iom_dtor_OBJOS(POBJOS pOs) -{ - __nvoc_dtor_Object(&pOs->__nvoc_base_Object); -} - -// OS's object initializer function to set up vtables and RTTI -void __iom_init_OBJOS(POBJOS pOs) -{ - pOs->__nvoc_pbase_Object = &pOs->__nvoc_base_Object; - __nvoc_init_Object(&pOs->__nvoc_base_Object); - osSetPropertiesSpecial(pOs); -} - - -// -// OS's object creation routine -// -NV_STATUS __iom_objCreate_OBJOS(POBJOS *ppThis, Dynamic *pParent, NvU32 flags) -{ - NV_STATUS status; - Object *pParentObj; - POBJOS pThis = NULL; - - // var flags is used by NVOC but not enabled in IOM - PORT_UNREFERENCED_VARIABLE(flags); - - pThis = portMemAllocNonPaged(sizeof(OBJOS)); - if (!pThis) - { - status = NV_ERR_NO_MEMORY; - goto __iom_objCreate_OBJOS_cleanup; - } - - portMemSet(pThis, 0, sizeof(OBJOS)); - - __nvoc_initRtti(staticCast(pThis, Dynamic), &__iom_class_def_OBJOS); - - pParentObj = dynamicCast(pParent, Object); - if (pParent) - { - objAddChild(pParentObj, &pThis->__nvoc_base_Object); - } - - __iom_init_OBJOS(pThis); - status = __iom_ctor_OBJOS(pThis); - if (status != NV_OK) goto __iom_objCreate_OBJOS_cleanup; - - *ppThis = pThis; - - return NV_OK; - -__iom_objCreate_OBJOS_cleanup: - if (pThis) - { - // do not call destructors here since __iom_ctor_OBJOS already called them - portMemSet(pThis, 0, sizeof(OBJOS)); - portMemFree(pThis); - pThis = NULL; - } - return status; -} - diff --git a/src/nvidia/generated/g_os_nvoc.c b/src/nvidia/generated/g_os_nvoc.c new file mode 100644 index 000000000..5d7c8ebbd --- /dev/null +++ b/src/nvidia/generated/g_os_nvoc.c @@ -0,0 +1,149 @@ +#define NVOC_OS_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_os_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0xaa1d70 = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJOS; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +void __nvoc_init_OBJOS(OBJOS*); +void __nvoc_init_funcTable_OBJOS(OBJOS*); +NV_STATUS __nvoc_ctor_OBJOS(OBJOS*); +void __nvoc_init_dataField_OBJOS(OBJOS*); +void __nvoc_dtor_OBJOS(OBJOS*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_OBJOS; + +static const struct NVOC_RTTI __nvoc_rtti_OBJOS_OBJOS = { + /*pClassDef=*/ &__nvoc_class_def_OBJOS, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_OBJOS, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_OBJOS_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(OBJOS, __nvoc_base_Object), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_OBJOS = { + /*numRelatives=*/ 2, + /*relatives=*/ { + &__nvoc_rtti_OBJOS_OBJOS, + &__nvoc_rtti_OBJOS_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_OBJOS = +{ + /*classInfo=*/ { + /*size=*/ sizeof(OBJOS), + /*classId=*/ classId(OBJOS), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "OBJOS", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_OBJOS, + /*pCastInfo=*/ &__nvoc_castinfo_OBJOS, + /*pExportInfo=*/ &__nvoc_export_info_OBJOS +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_OBJOS = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_Object(Object*); +void __nvoc_dtor_OBJOS(OBJOS *pThis) { + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_OBJOS(OBJOS *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); + pThis->setProperty(pThis, PDB_PROP_OS_SUPPORTS_DISPLAY_REMAPPER, !(1)); +} + +NV_STATUS __nvoc_ctor_Object(Object* ); +NV_STATUS __nvoc_ctor_OBJOS(OBJOS *pThis) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_Object(&pThis->__nvoc_base_Object); + if (status != NV_OK) goto __nvoc_ctor_OBJOS_fail_Object; + __nvoc_init_dataField_OBJOS(pThis); + goto __nvoc_ctor_OBJOS_exit; // Success + +__nvoc_ctor_OBJOS_fail_Object: +__nvoc_ctor_OBJOS_exit: + + return status; +} + +static void __nvoc_init_funcTable_OBJOS_1(OBJOS *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_funcTable_OBJOS(OBJOS *pThis) { + __nvoc_init_funcTable_OBJOS_1(pThis); +} + +void __nvoc_init_Object(Object*); +void __nvoc_init_OBJOS(OBJOS *pThis) { + pThis->__nvoc_pbase_OBJOS = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Object; + __nvoc_init_Object(&pThis->__nvoc_base_Object); + __nvoc_init_funcTable_OBJOS(pThis); +} + +NV_STATUS __nvoc_objCreate_OBJOS(OBJOS **ppThis, Dynamic *pParent, NvU32 createFlags) { + NV_STATUS status; + Object *pParentObj; + OBJOS *pThis; + + pThis = portMemAllocNonPaged(sizeof(OBJOS)); + if (pThis == NULL) return NV_ERR_NO_MEMORY; + + portMemSet(pThis, 0, sizeof(OBJOS)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJOS); + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_OBJOS(pThis); + status = __nvoc_ctor_OBJOS(pThis); + if (status != NV_OK) goto __nvoc_objCreate_OBJOS_cleanup; + + *ppThis = pThis; + return NV_OK; + +__nvoc_objCreate_OBJOS_cleanup: + // do not call destructors here since the constructor already called them + portMemFree(pThis); + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_OBJOS(OBJOS **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + + status = __nvoc_objCreate_OBJOS(ppThis, pParent, createFlags); + + return status; +} + diff --git a/src/nvidia/generated/g_os_nvoc.h b/src/nvidia/generated/g_os_nvoc.h index 0ee6be853..882aa210b 100644 --- a/src/nvidia/generated/g_os_nvoc.h +++ b/src/nvidia/generated/g_os_nvoc.h @@ -56,6 +56,18 @@ extern "C" { #include "os/os_fixed_mode_timings_props.h" /* ------------------------ Forward Declarations ---------------------------- */ +struct OBJOS; + +#ifndef __NVOC_CLASS_OBJOS_TYPEDEF__ +#define __NVOC_CLASS_OBJOS_TYPEDEF__ +typedef struct OBJOS OBJOS; +#endif /* __NVOC_CLASS_OBJOS_TYPEDEF__ */ + +#ifndef __nvoc_class_id_OBJOS +#define __nvoc_class_id_OBJOS 0xaa1d70 +#endif /* __nvoc_class_id_OBJOS */ + + // // The OS module should NOT depend on RM modules. The only exception is @@ -187,7 +199,8 @@ typedef enum _OS_PEX_RECOVERY_STATUS #define OS_BUG_CHECK_BUGCODE_NVLINK_TL_ERR (4) #define OS_BUG_CHECK_BUGCODE_PAGED_SEGMENT (5) #define OS_BUG_CHECK_BUGCODE_BDOD_ON_ASSERT (6) -#define OS_BUG_CHECK_BUGCODE_LAST OS_BUG_CHECK_BUGCODE_BDOD_ON_ASSERT +#define OS_BUG_CHECK_BUGCODE_DISPLAY_UNDERFLOW (7) +#define OS_BUG_CHECK_BUGCODE_LAST OS_BUG_CHECK_BUGCODE_DISPLAY_UNDERFLOW #define OS_BUG_CHECK_BUGCODE_STR \ { \ @@ -196,8 +209,9 @@ typedef enum _OS_PEX_RECOVERY_STATUS "Bus Error", \ "Double Bit Error", \ "NVLink TL Error", \ - "Invalid Bindata Access" \ - "BSOD on Assert or Breakpoint" \ + "Invalid Bindata Access", \ + "BSOD on Assert or Breakpoint", \ + "Display Underflow" \ } // Flags needed by OSAllocPagesNode @@ -417,23 +431,23 @@ typedef NV_STATUS OSCallACPI_DSM(OBJGPU *pGpu, ACPI_DSM_FUNCTION acpiDSMFunctio typedef NV_STATUS OSGetUefiVariable(OBJGPU *, char *, LPGUID, NvU8 *, NvU32 *, NvU32 *); // The following functions are also implemented in WinNT -typedef void OSQADbgRegistryInit(OBJOS *); +typedef void OSQADbgRegistryInit(struct OBJOS *); typedef NV_STATUS OSGetVersionDump(void *); // End of WinNT // OS functions typically only implemented for MacOS core // These next functions also appear on UNIX -typedef NvU32 OSnv_rdcr4(OBJOS *); -typedef NvU64 OSnv_rdxcr0(OBJOS *); -typedef int OSnv_cpuid(OBJOS *, int, int, NvU32 *, NvU32 *, NvU32 *, NvU32 *); +typedef NvU32 OSnv_rdcr4(struct OBJOS *); +typedef NvU64 OSnv_rdxcr0(struct OBJOS *); +typedef int OSnv_cpuid(struct OBJOS *, int, int, NvU32 *, NvU32 *, NvU32 *, NvU32 *); // end of functions shared between MacOSX and UNIX // These next functions also appear on UNIX -typedef NvU32 OSnv_rdmsr(OBJOS *, NvU32, NvU32 *, NvU32 *); -typedef NvU32 OSnv_wrmsr(OBJOS *, NvU32, NvU32, NvU32); +typedef NvU32 OSnv_rdmsr(struct OBJOS *, NvU32, NvU32 *, NvU32 *); +typedef NvU32 OSnv_wrmsr(struct OBJOS *, NvU32, NvU32, NvU32); // end functions shared by MacOS and UNIX -typedef NvU32 OSRobustChannelsDefaultState(OBJOS *); +typedef NvU32 OSRobustChannelsDefaultState(struct OBJOS *); // NOTE: The following functions are also implemented in MODS typedef NV_STATUS OSSimEscapeWrite(OBJGPU *, const char *path, NvU32 Index, NvU32 Size, NvU32 Value); @@ -443,6 +457,7 @@ typedef NV_STATUS OSSimEscapeReadBuffer(OBJGPU *, const char *path, NvU32 typedef NvU32 OSGetSimulationMode(void); typedef void OSLogString(const char*, ...); typedef void OSFlushLog(void); +typedef void OSSetSurfaceName(void *pDescriptor, char *name); // End of MODS functions @@ -472,7 +487,7 @@ typedef struct typedef NV_STATUS OsGetSystemCpuLogicalCoreCounts(NvU32 *pCpuCoreCount); typedef NV_STATUS OsGetSystemCpuC0AndAPerfCounters(NvU32 coreIndex, POS_CPU_CORE_PERF_COUNTERS pCpuPerfData); -typedef void OsEnableCpuPerformanceCounters(OBJOS *pOS); +typedef void OsEnableCpuPerformanceCounters(struct OBJOS *pOS); typedef NV_STATUS OsCpuDpcObjInit(void **ppCpuDpcObj, OBJGPU *pGpu, NvU32 coreCount); typedef void OsCpuDpcObjQueue(void **ppCpuDpcObj, NvU32 coreCount, POS_CPU_CORE_PERF_COUNTERS pCpuPerfData); typedef void OsCpuDpcObjFree(void **ppCpuDpcObj); @@ -518,8 +533,8 @@ typedef struct // OS's. // -typedef NvBool OSRmInitRm(OBJOS *); -typedef NV_STATUS OSGetPanelStrapAndIndex(OBJOS *, OBJGPU *, NvU32 *, NvU32 *); +typedef NvBool OSRmInitRm(struct OBJOS *); +typedef NV_STATUS OSGetPanelStrapAndIndex(struct OBJOS *, OBJGPU *, NvU32 *, NvU32 *); typedef NV_STATUS OSNotifySbiosDisplayChangeEnd(OBJGPU *, NvU32); typedef NvU32 OSGetDfpScalerFromSbios(OBJGPU *); typedef NvU32 OSPollHotkeyState(OBJGPU *); @@ -550,6 +565,7 @@ typedef NV_STATUS OSSetGpuRailVoltage(OBJGPU *, NvU32, NvU32*); typedef NV_STATUS OSGetGpuRailVoltage(OBJGPU *, NvU32*); typedef NV_STATUS OSGetGpuRailVoltageInfo(OBJGPU *, NvU32 *, NvU32 *, NvU32 *); typedef NV_STATUS OSTegraSocGetImpImportData(TEGRA_IMP_IMPORT_DATA *); +typedef NV_STATUS OSTegraSocEnableDisableRfl(OS_GPU_INFO *, NvBool); typedef NV_STATUS OSTegraAllocateDisplayBandwidth(OS_GPU_INFO *, NvU32, NvU32); typedef NV_STATUS OSMemdrvQueryInterface(OS_GPU_INFO *); @@ -573,113 +589,141 @@ typedef RC_CALLBACK_STATUS OSRCCallback(OBJGPU *, NvHandle, NvHandle, NvHandle, typedef NvBool OSCheckCallback(OBJGPU *); typedef NV_STATUS OSReadPFPciConfigInVF(NvU32, NvU32*); -#include "g_os_odb.h" // (rmconfig) os public interface - // Actual definition of the OBJOS structure -struct OBJOS -{ - // - // Every object has a common object database structure at its start. - // WARNING: Never add anything above this structure definition. - // - OBJECT_BASE_DEFINITION(OS); - - // Function pointers to Misc OS routines - OSDbgBreakpointEnabled *osDbgBreakpointEnabled; - - // Function pointers to routines normally implemented by WinNT only - OSQADbgRegistryInit *osQADbgRegistryInit; - OSQueueWorkItem *osQueueWorkItem; - OSQueueWorkItemWithFlags *osQueueWorkItemWithFlags; - OSQueueSystemWorkItem *osQueueSystemWorkItem; - - // used to initialize OBJSTEREO - void* (*osGetStereoDongleInterface)(void); - - // Function pointers to routines normally implemented by MacOS core - OSnv_rdcr4 *osNv_rdcr4; - OSnv_rdxcr0 *osNv_rdxcr0; - OSnv_cpuid *osNv_cpuid; - - // Function pointers to routines only implemented by MacOSX - OSnv_rdmsr *osNv_rdmsr; - OSnv_wrmsr *osNv_wrmsr; - OSRobustChannelsDefaultState *osRobustChannelsDefaultState; - - OSSimEscapeWrite *osSimEscapeWrite; - OSSimEscapeWriteBuffer *osSimEscapeWriteBuffer; - OSSimEscapeRead *osSimEscapeRead; - OSSimEscapeReadBuffer *osSimEscapeReadBuffer; - - // Function pointer to API functions. Add other OS's before these - OSRmInitRm *osRmInitRm; - - OSGetSimulationMode *osGetSimulationMode; - - // Function pointers for MXM ACPI Calls - OSCallACPI_MXMX *osCallACPI_MXMX; - OSCallACPI_DDC *osCallACPI_DDC; - OSCallACPI_BCL *osCallACPI_BCL; - - // Function pointers for display MUX ACPI calls - OSCallACPI_MXDS *osCallACPI_MXDS; - OSCallACPI_MXDM *osCallACPI_MXDM; - OSCallACPI_MXID *osCallACPI_MXID; - OSCallACPI_LRST *osCallACPI_LRST; - - // Function pointers for Hybrid GPU WMI calls - OSCallACPI_NVHG_GPUON *osCallACPI_NVHG_GPUON; - OSCallACPI_NVHG_GPUOFF *osCallACPI_NVHG_GPUOFF; - OSCallACPI_NVHG_GPUSTA *osCallACPI_NVHG_GPUSTA; - OSCallACPI_NVHG_MXDS *osCallACPI_NVHG_MXDS; - OSCallACPI_NVHG_MXMX *osCallACPI_NVHG_MXMX; - OSCallACPI_NVHG_DOS *osCallACPI_NVHG_DOS; - OSCallACPI_NVHG_ROM *osCallACPI_NVHG_ROM; - OSCallACPI_NVHG_DCS *osCallACPI_NVHG_DCS; - OSCallACPI_DOD *osCallACPI_DOD; - - // Function pointers for Tegra systems - OSCallACPI_SUB *osCallACPI_SUB; - OSCallACPI_ON *osCallACPI_ON; - OSCallACPI_OFF *osCallACPI_OFF; - - // function pointers to all DSM calls - OSCallACPI_DSM *osCallACPI_DSM; - - // function pointers to UEFI runtime variable calls - OSGetUefiVariable *osGetUefiVariable; - - OSCheckCallback *osCheckCallback; - OSRCCallback *osRCCallback; - - // Function pointers Notebook Power Balancing WMI calls - OSCallACPI_NBPS *osCallACPI_NBPS; - OSCallACPI_NBSL *osCallACPI_NBSL; - - // Function pointers for Optimus GPU WMI calls - OSCallACPI_OPTM_GPUON *osCallACPI_OPTM_GPUON; - - OSSetupVBlank *osSetupVBlank; - - OSPexRecoveryCallback *osPexRecoveryCallback; - - // Function pointers for heap reserve tracking callbacks - OSInternalReserveAllocCallback *osInternalReserveAllocCallback; - OSInternalReserveFreeCallback *osInternalReserveFreeCallback; - - // In 4K pages +#ifdef NVOC_OS_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct OBJOS { + const struct NVOC_RTTI *__nvoc_rtti; + struct Object __nvoc_base_Object; + struct Object *__nvoc_pbase_Object; + struct OBJOS *__nvoc_pbase_OBJOS; + NvBool PDB_PROP_OS_PAT_UNSUPPORTED; + NvBool PDB_PROP_OS_SLI_ALLOWED; + NvBool PDB_PROP_OS_SYSTEM_EVENTS_SUPPORTED; + NvBool PDB_PROP_OS_ONDEMAND_VBLANK_CONTROL_ENABLE_DEFAULT; + NvBool PDB_PROP_OS_WAIT_FOR_ACPI_SUBSYSTEM; + NvBool PDB_PROP_OS_UNCACHED_MEMORY_MAPPINGS_NOT_SUPPORTED; + NvBool PDB_PROP_OS_CACHED_MEMORY_MAPPINGS_FOR_ACPI_TABLE; + NvBool PDB_PROP_OS_LIMIT_GPU_RESET; + NvBool PDB_PROP_OS_SUPPORTS_TDR; + NvBool PDB_PROP_OS_GET_ACPI_TABLE_FROM_UEFI; + NvBool PDB_PROP_OS_SUPPORTS_DISPLAY_REMAPPER; + NvBool PDB_PROP_OS_DOES_NOT_ALLOW_DIRECT_PCIE_MAPPINGS; + NvBool PDB_PROP_OS_NO_PAGED_SEGMENT_ACCESS; + OSDbgBreakpointEnabled *osDbgBreakpointEnabled; + OSQADbgRegistryInit *osQADbgRegistryInit; + OSQueueWorkItem *osQueueWorkItem; + OSQueueWorkItemWithFlags *osQueueWorkItemWithFlags; + OSQueueSystemWorkItem *osQueueSystemWorkItem; + void *(*osGetStereoDongleInterface)(void); + OSnv_rdcr4 *osNv_rdcr4; + OSnv_rdxcr0 *osNv_rdxcr0; + OSnv_cpuid *osNv_cpuid; + OSnv_rdmsr *osNv_rdmsr; + OSnv_wrmsr *osNv_wrmsr; + OSRobustChannelsDefaultState *osRobustChannelsDefaultState; + OSSimEscapeWrite *osSimEscapeWrite; + OSSimEscapeWriteBuffer *osSimEscapeWriteBuffer; + OSSimEscapeRead *osSimEscapeRead; + OSSimEscapeReadBuffer *osSimEscapeReadBuffer; + OSRmInitRm *osRmInitRm; + OSGetSimulationMode *osGetSimulationMode; + OSCallACPI_MXMX *osCallACPI_MXMX; + OSCallACPI_DDC *osCallACPI_DDC; + OSCallACPI_BCL *osCallACPI_BCL; + OSCallACPI_MXDS *osCallACPI_MXDS; + OSCallACPI_MXDM *osCallACPI_MXDM; + OSCallACPI_MXID *osCallACPI_MXID; + OSCallACPI_LRST *osCallACPI_LRST; + OSCallACPI_NVHG_GPUON *osCallACPI_NVHG_GPUON; + OSCallACPI_NVHG_GPUOFF *osCallACPI_NVHG_GPUOFF; + OSCallACPI_NVHG_GPUSTA *osCallACPI_NVHG_GPUSTA; + OSCallACPI_NVHG_MXDS *osCallACPI_NVHG_MXDS; + OSCallACPI_NVHG_MXMX *osCallACPI_NVHG_MXMX; + OSCallACPI_NVHG_DOS *osCallACPI_NVHG_DOS; + OSCallACPI_NVHG_ROM *osCallACPI_NVHG_ROM; + OSCallACPI_NVHG_DCS *osCallACPI_NVHG_DCS; + OSCallACPI_DOD *osCallACPI_DOD; + OSCallACPI_SUB *osCallACPI_SUB; + OSCallACPI_ON *osCallACPI_ON; + OSCallACPI_OFF *osCallACPI_OFF; + OSCallACPI_DSM *osCallACPI_DSM; + OSGetUefiVariable *osGetUefiVariable; + OSCheckCallback *osCheckCallback; + OSRCCallback *osRCCallback; + OSCallACPI_NBPS *osCallACPI_NBPS; + OSCallACPI_NBSL *osCallACPI_NBSL; + OSCallACPI_OPTM_GPUON *osCallACPI_OPTM_GPUON; + OSSetupVBlank *osSetupVBlank; + OSPexRecoveryCallback *osPexRecoveryCallback; + OSInternalReserveAllocCallback *osInternalReserveAllocCallback; + OSInternalReserveFreeCallback *osInternalReserveFreeCallback; NvU32 SystemMemorySize; - - // OS-specific page array interface. - OSPageArrayGetPhysAddr *osPageArrayGetPhysAddr; - - // mask holding dynamic power supported GPUs + OSPageArrayGetPhysAddr *osPageArrayGetPhysAddr; NvU32 dynamicPowerSupportGpuMask; - - // Flag for SIM_BUILD in MODS NvBool bIsSimMods; }; +#ifndef __NVOC_CLASS_OBJOS_TYPEDEF__ +#define __NVOC_CLASS_OBJOS_TYPEDEF__ +typedef struct OBJOS OBJOS; +#endif /* __NVOC_CLASS_OBJOS_TYPEDEF__ */ + +#ifndef __nvoc_class_id_OBJOS +#define __nvoc_class_id_OBJOS 0xaa1d70 +#endif /* __nvoc_class_id_OBJOS */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJOS; + +#define __staticCast_OBJOS(pThis) \ + ((pThis)->__nvoc_pbase_OBJOS) + +#ifdef __nvoc_os_h_disabled +#define __dynamicCast_OBJOS(pThis) ((OBJOS*)NULL) +#else //__nvoc_os_h_disabled +#define __dynamicCast_OBJOS(pThis) \ + ((OBJOS*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(OBJOS))) +#endif //__nvoc_os_h_disabled + +#define PDB_PROP_OS_SUPPORTS_DISPLAY_REMAPPER_BASE_CAST +#define PDB_PROP_OS_SUPPORTS_DISPLAY_REMAPPER_BASE_NAME PDB_PROP_OS_SUPPORTS_DISPLAY_REMAPPER +#define PDB_PROP_OS_NO_PAGED_SEGMENT_ACCESS_BASE_CAST +#define PDB_PROP_OS_NO_PAGED_SEGMENT_ACCESS_BASE_NAME PDB_PROP_OS_NO_PAGED_SEGMENT_ACCESS +#define PDB_PROP_OS_WAIT_FOR_ACPI_SUBSYSTEM_BASE_CAST +#define PDB_PROP_OS_WAIT_FOR_ACPI_SUBSYSTEM_BASE_NAME PDB_PROP_OS_WAIT_FOR_ACPI_SUBSYSTEM +#define PDB_PROP_OS_UNCACHED_MEMORY_MAPPINGS_NOT_SUPPORTED_BASE_CAST +#define PDB_PROP_OS_UNCACHED_MEMORY_MAPPINGS_NOT_SUPPORTED_BASE_NAME PDB_PROP_OS_UNCACHED_MEMORY_MAPPINGS_NOT_SUPPORTED +#define PDB_PROP_OS_LIMIT_GPU_RESET_BASE_CAST +#define PDB_PROP_OS_LIMIT_GPU_RESET_BASE_NAME PDB_PROP_OS_LIMIT_GPU_RESET +#define PDB_PROP_OS_ONDEMAND_VBLANK_CONTROL_ENABLE_DEFAULT_BASE_CAST +#define PDB_PROP_OS_ONDEMAND_VBLANK_CONTROL_ENABLE_DEFAULT_BASE_NAME PDB_PROP_OS_ONDEMAND_VBLANK_CONTROL_ENABLE_DEFAULT +#define PDB_PROP_OS_PAT_UNSUPPORTED_BASE_CAST +#define PDB_PROP_OS_PAT_UNSUPPORTED_BASE_NAME PDB_PROP_OS_PAT_UNSUPPORTED +#define PDB_PROP_OS_SLI_ALLOWED_BASE_CAST +#define PDB_PROP_OS_SLI_ALLOWED_BASE_NAME PDB_PROP_OS_SLI_ALLOWED +#define PDB_PROP_OS_DOES_NOT_ALLOW_DIRECT_PCIE_MAPPINGS_BASE_CAST +#define PDB_PROP_OS_DOES_NOT_ALLOW_DIRECT_PCIE_MAPPINGS_BASE_NAME PDB_PROP_OS_DOES_NOT_ALLOW_DIRECT_PCIE_MAPPINGS +#define PDB_PROP_OS_CACHED_MEMORY_MAPPINGS_FOR_ACPI_TABLE_BASE_CAST +#define PDB_PROP_OS_CACHED_MEMORY_MAPPINGS_FOR_ACPI_TABLE_BASE_NAME PDB_PROP_OS_CACHED_MEMORY_MAPPINGS_FOR_ACPI_TABLE +#define PDB_PROP_OS_SUPPORTS_TDR_BASE_CAST +#define PDB_PROP_OS_SUPPORTS_TDR_BASE_NAME PDB_PROP_OS_SUPPORTS_TDR +#define PDB_PROP_OS_GET_ACPI_TABLE_FROM_UEFI_BASE_CAST +#define PDB_PROP_OS_GET_ACPI_TABLE_FROM_UEFI_BASE_NAME PDB_PROP_OS_GET_ACPI_TABLE_FROM_UEFI +#define PDB_PROP_OS_SYSTEM_EVENTS_SUPPORTED_BASE_CAST +#define PDB_PROP_OS_SYSTEM_EVENTS_SUPPORTED_BASE_NAME PDB_PROP_OS_SYSTEM_EVENTS_SUPPORTED + +NV_STATUS __nvoc_objCreateDynamic_OBJOS(OBJOS**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_OBJOS(OBJOS**, Dynamic*, NvU32); +#define __objCreate_OBJOS(ppNewObj, pParent, createFlags) \ + __nvoc_objCreate_OBJOS((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) + +#undef PRIVATE_FIELD + + NV_STATUS addProbe(OBJGPU *, NvU32); @@ -700,6 +744,7 @@ NV_STATUS osTegraSocPmPowergate(OS_GPU_INFO *pOsGpuInfo); NV_STATUS osTegraSocPmUnpowergate(OS_GPU_INFO *pOsGpuInfo); NV_STATUS osTegraSocDeviceReset(OS_GPU_INFO *pOsGpuInfo); NV_STATUS osTegraSocGetImpImportData(TEGRA_IMP_IMPORT_DATA *pTegraImpImportData); +NV_STATUS osTegraSocEnableDisableRfl(OS_GPU_INFO *pOsGpuInfo, NvBool bEnable); NV_STATUS osTegraAllocateDisplayBandwidth(OS_GPU_INFO *pOsGpuInfo, NvU32 averageBandwidthKBPS, NvU32 floorBandwidthKBPS); @@ -796,6 +841,7 @@ NV_STATUS osVgpuRegisterMdev(OS_GPU_INFO *pArg1); NV_STATUS osIsVgpuVfioPresent(void); NV_STATUS osVgpuAllocVmbusEventDpc(void **ppArg1); void osVgpuScheduleVmbusEventDpc(void *pArg1, void *pArg2); +NV_STATUS rm_is_vgpu_supported_device(OS_GPU_INFO *pNv, NvU32 pmc_boot_1); NV_STATUS osLockPageableDataSection(RM_PAGEABLE_SECTION *pSection); NV_STATUS osUnlockPageableDataSection(RM_PAGEABLE_SECTION *pSection); @@ -992,6 +1038,9 @@ NV_STATUS osCancelNanoTimer(OS_GPU_INFO *pArg1, NV_STATUS osDestroyNanoTimer(OS_GPU_INFO *pArg1, void *pArg2); +NV_STATUS osGetValidWindowHeadMask(OS_GPU_INFO *pArg1, + NvU64 *pWindowHeadMask); + NV_STATUS osSchedule(void); NV_STATUS osDmaMapPages(OS_GPU_INFO *pArg1, @@ -1059,6 +1108,10 @@ NV_STATUS osGetTegraNumDpAuxInstances(OS_GPU_INFO *pArg1, NvU32 osTegraSocFuseRegRead(NvU32 addr); +NV_STATUS osTegraSocDpUphyPllInit(OS_GPU_INFO *pArg1, NvU32, NvU32); + +NV_STATUS osTegraSocDpUphyPllDeInit(OS_GPU_INFO *pArg1); + NV_STATUS osGetCurrentIrqPrivData(OS_GPU_INFO *pArg1, NvU32 *pArg2); @@ -1089,6 +1142,11 @@ NvBool osIsNvswitchPresent(void); void osQueueMMUFaultHandler(OBJGPU *); NvBool osIsGpuAccessible(OBJGPU *pGpu); +NvBool osIsGpuShutdown(OBJGPU *pGpu); + +NvBool osMatchGpuOsInfo(OBJGPU *pGpu, void *pOsInfo); + +void osReleaseGpuOsInfo(void *pOsInfo); void osGpuWriteReg008(OBJGPU *pGpu, NvU32 thisAddress, @@ -1358,6 +1416,7 @@ OSCondAcquireRmSema osCondAcquireRmSema; OSReleaseRmSema osReleaseRmSema; OSFlushLog osFlushLog; +OSSetSurfaceName osSetSurfaceName; #define MODS_ARCH_ERROR_PRINTF(format, ...) #define MODS_ARCH_INFO_PRINTF(format, ...) @@ -1367,8 +1426,8 @@ OSFlushLog osFlushLog; #define osAllocPages(a) osAllocPagesInternal(a) #define osFreePages(a) osFreePagesInternal(a) -extern NV_STATUS constructObjOS(OBJOS *); -extern void osInitObjOS(OBJOS *); +extern NV_STATUS constructObjOS(struct OBJOS *); +extern void osInitObjOS(struct OBJOS *); extern OSGetTimeoutParams osGetTimeoutParams; extern OSGetSimulationMode osGetSimulationMode; diff --git a/src/nvidia/generated/g_os_odb.h b/src/nvidia/generated/g_os_odb.h deleted file mode 100644 index 1bdfa915d..000000000 --- a/src/nvidia/generated/g_os_odb.h +++ /dev/null @@ -1,36 +0,0 @@ -// This file is automatically generated by rmconfig - DO NOT EDIT! -// -// Provides OS object boilerplate and RTTI. -// -// Profile: shipping-gpus-openrm -// Haldef: os.def -// Template: templates/gt_eng_odb.h -// - -#ifndef _G_OS_ODB_H_ -#define _G_OS_ODB_H_ - -#include "core/core.h" -#include "g_os_hal.h" - - -#define __OS_OBJECT_BASE_DEFINITION \ - const struct NVOC_RTTI *__nvoc_rtti; \ - Object __nvoc_base_Object; \ - Object *__nvoc_pbase_Object; \ - PDB_PROP_OS pdb - - -extern const struct NVOC_CLASS_DEF __iom_class_def_OBJOS; -#define __nvoc_class_def_OBJOS __iom_class_def_OBJOS - -#ifndef __nvoc_class_id_OBJOS -#define __nvoc_class_id_OBJOS 0xaa1d70 -#endif /* __nvoc_class_id_OBJOS */ - -#define __objCreate_OBJOS(ppNewObj, pParent, flags) \ - __iom_objCreate_OBJOS((ppNewObj), staticCast((pParent), Dynamic), flags) -NV_STATUS __iom_objCreate_OBJOS(POBJOS *ppNewObj, Dynamic *pParent, NvU32 flags); - - -#endif // _G_OS_ODB_H_ diff --git a/src/nvidia/generated/g_os_private.h b/src/nvidia/generated/g_os_private.h deleted file mode 100644 index 47a3154b6..000000000 --- a/src/nvidia/generated/g_os_private.h +++ /dev/null @@ -1,55 +0,0 @@ -// This file is automatically generated by rmconfig - DO NOT EDIT! -// -// Private HAL support for OS. -// -// Profile: shipping-gpus-openrm -// Haldef: os.def -// Template: templates/gt_eng_private.h -// - -#ifndef _G_OS_PRIVATE_H_ -#define _G_OS_PRIVATE_H_ - -#include "g_os_hal.h" - - - - - - - -// -// OS's object-level *non-static* interface functions (static ones are below) -// - - - -#if defined(RMCFG_ENGINE_SETUP) // for use by hal init only - - - - - - - - - - - -// -// Setup OS's hal interface function pointers -// - - - - - -#endif // RMCFG_ENGINE_SETUP - - - -// Were any _MOCK interfaces generated into g_os_private.h ? -#define OS_MOCK_FUNCTIONS_GENERATED 0 - - -#endif // _G_OS_PRIVATE_H_ diff --git a/src/nvidia/generated/g_p2p_api_nvoc.c b/src/nvidia/generated/g_p2p_api_nvoc.c index 7fea1ea77..aef49855f 100644 --- a/src/nvidia/generated/g_p2p_api_nvoc.c +++ b/src/nvidia/generated/g_p2p_api_nvoc.c @@ -140,6 +140,10 @@ static NV_STATUS __nvoc_thunk_RsResource_p2papiUnmapFrom(struct P2PApi *pResourc return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_p2papiIsDuplicate(struct P2PApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_p2papiControl_Epilogue(struct P2PApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RmResource.offset), pCallContext, pParams); } @@ -223,6 +227,8 @@ static void __nvoc_init_funcTable_P2PApi_1(P2PApi *pThis) { pThis->__p2papiUnmapFrom__ = &__nvoc_thunk_RsResource_p2papiUnmapFrom; + pThis->__p2papiIsDuplicate__ = &__nvoc_thunk_RsResource_p2papiIsDuplicate; + pThis->__p2papiControl_Epilogue__ = &__nvoc_thunk_RmResource_p2papiControl_Epilogue; pThis->__p2papiControlLookup__ = &__nvoc_thunk_RsResource_p2papiControlLookup; diff --git a/src/nvidia/generated/g_p2p_api_nvoc.h b/src/nvidia/generated/g_p2p_api_nvoc.h index 8c140ef74..68440cc1a 100644 --- a/src/nvidia/generated/g_p2p_api_nvoc.h +++ b/src/nvidia/generated/g_p2p_api_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2009-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -35,36 +35,7 @@ extern "C" { #define _P2P_API_H_ #include "core/core.h" -#include "gpu/mem_mgr/heap.h" #include "rmapi/client.h" -#include "rmapi/mapping_list.h" -#include "gpu/mem_mgr/mem_desc.h" -#include "platform/p2p/p2p_caps.h" - - -struct Subdevice; - -#ifndef __NVOC_CLASS_Subdevice_TYPEDEF__ -#define __NVOC_CLASS_Subdevice_TYPEDEF__ -typedef struct Subdevice Subdevice; -#endif /* __NVOC_CLASS_Subdevice_TYPEDEF__ */ - -#ifndef __nvoc_class_id_Subdevice -#define __nvoc_class_id_Subdevice 0x4b01b3 -#endif /* __nvoc_class_id_Subdevice */ - - - -struct _def_client_p2p_dma_mapping_info -{ - PCLI_DMA_MAPPING_INFO pPeer1Info; - PCLI_DMA_MAPPING_INFO pPeer2Info; -}; - -typedef struct _def_client_p2p_dma_mapping_info CLI_P2P_DMA_MAPPING_INFO, *PCLI_P2P_DMA_MAPPING_INFO; - -MAKE_MAP(CLI_P2P_DMA_MAPPING_INFO_MAP, CLI_P2P_DMA_MAPPING_INFO); - // // Definitions for P2PApi.attributes. @@ -108,17 +79,18 @@ struct P2PApi { NV_STATUS (*__p2papiMapTo__)(struct P2PApi *, RS_RES_MAP_TO_PARAMS *); void (*__p2papiPreDestruct__)(struct P2PApi *); NV_STATUS (*__p2papiUnmapFrom__)(struct P2PApi *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__p2papiIsDuplicate__)(struct P2PApi *, NvHandle, NvBool *); void (*__p2papiControl_Epilogue__)(struct P2PApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__p2papiControlLookup__)(struct P2PApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__p2papiMap__)(struct P2PApi *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__p2papiAccessCallback__)(struct P2PApi *, struct RsClient *, void *, RsAccessRight); - NODE Node; - struct Subdevice *peer1; - struct Subdevice *peer2; + struct OBJGPU *peer1; + struct OBJGPU *peer2; + NvU32 localGfid; + NvU32 remoteGfid; NvU32 peerId1; NvU32 peerId2; NvU32 attributes; - CLI_P2P_DMA_MAPPING_INFO_MAP dmaMappingMap; }; #ifndef __NVOC_CLASS_P2PApi_TYPEDEF__ @@ -163,6 +135,7 @@ NV_STATUS __nvoc_objCreate_P2PApi(P2PApi**, Dynamic*, NvU32, struct CALL_CONTEXT #define p2papiMapTo(pResource, pParams) p2papiMapTo_DISPATCH(pResource, pParams) #define p2papiPreDestruct(pResource) p2papiPreDestruct_DISPATCH(pResource) #define p2papiUnmapFrom(pResource, pParams) p2papiUnmapFrom_DISPATCH(pResource, pParams) +#define p2papiIsDuplicate(pResource, hMemory, pDuplicate) p2papiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define p2papiControl_Epilogue(pResource, pCallContext, pParams) p2papiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define p2papiControlLookup(pResource, pParams, ppEntry) p2papiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define p2papiMap(pResource, pCallContext, pParams, pCpuMapping) p2papiMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) @@ -223,6 +196,10 @@ static inline NV_STATUS p2papiUnmapFrom_DISPATCH(struct P2PApi *pResource, RS_RE return pResource->__p2papiUnmapFrom__(pResource, pParams); } +static inline NV_STATUS p2papiIsDuplicate_DISPATCH(struct P2PApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__p2papiIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void p2papiControl_Epilogue_DISPATCH(struct P2PApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__p2papiControl_Epilogue__(pResource, pCallContext, pParams); } @@ -240,36 +217,14 @@ static inline NvBool p2papiAccessCallback_DISPATCH(struct P2PApi *pResource, str } NV_STATUS p2papiConstruct_IMPL(struct P2PApi *arg_pResource, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_p2papiConstruct(arg_pResource, arg_pCallContext, arg_pParams) p2papiConstruct_IMPL(arg_pResource, arg_pCallContext, arg_pParams) void p2papiDestruct_IMPL(struct P2PApi *pResource); + #define __nvoc_p2papiDestruct(pResource) p2papiDestruct_IMPL(pResource) #undef PRIVATE_FIELD -typedef struct P2PApi *PCLI_P2P_INFO; // RS-TODO: Delete -MAKE_LIST(PCLI_P2P_INFO_LIST, PCLI_P2P_INFO); - -// Add a dma mapping info to the p2p object that maps the peer GPUs -NV_STATUS CliAddP2PDmaMappingInfo (NvHandle, NvHandle, NvU32, NvHandle, NvU32, PCLI_DMA_MAPPING_INFO); - -// Free the CliP2PList of a given client -NV_STATUS CliFreeP2PList (NvHandle); - -// Free the p2p infos of a subdevice -NV_STATUS CliFreeSubDeviceP2PList (struct Subdevice *, CALL_CONTEXT *); - -// Unmap the dma mappings associated with a p2p object and free the p2p pDmaMappingList -NV_STATUS CliFreeP2PDmaMappingList (NvHandle, PCLI_P2P_INFO); - -// Delete the dma mapping info from the p2p object when the memory is no longer peer mapped -NV_STATUS CliDelP2PDmaMappingInfo (NvHandle, PCLI_DMA_MAPPING_INFO); - -// Delete the dma mapping info from the p2p object when the memory is no longer peer mapped -NV_STATUS CliUpdateP2PDmaMappingInList (NvHandle, PCLI_DMA_MAPPING_INFO, NvU64); - -// Remove the P2P mapping corresponding to the P2P info passed in -NV_STATUS CliInvalidateP2PInfo (NvHandle, PCLI_P2P_INFO); - #endif // _P2P_API_H_ #ifdef __cplusplus diff --git a/src/nvidia/generated/g_phys_mem_nvoc.c b/src/nvidia/generated/g_phys_mem_nvoc.c index 90bc9c364..cc7315c5f 100644 --- a/src/nvidia/generated/g_phys_mem_nvoc.c +++ b/src/nvidia/generated/g_phys_mem_nvoc.c @@ -145,8 +145,12 @@ static NV_STATUS __nvoc_thunk_RmResource_physmemControl_Prologue(struct Physical return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_Memory_physmemIsReady(struct PhysicalMemory *pMemory) { - return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset)); +static NvBool __nvoc_thunk_Memory_physmemIsGpuMapAllowed(struct PhysicalMemory *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), pGpu); +} + +static NV_STATUS __nvoc_thunk_Memory_physmemIsReady(struct PhysicalMemory *pMemory, NvBool bCopyConstructorContext) { + return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), bCopyConstructorContext); } static NV_STATUS __nvoc_thunk_Memory_physmemCheckCopyPermissions(struct PhysicalMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { @@ -157,6 +161,10 @@ static void __nvoc_thunk_RsResource_physmemPreDestruct(struct PhysicalMemory *pR resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_Memory_physmemIsDuplicate(struct PhysicalMemory *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), hMemory, pDuplicate); +} + static NV_STATUS __nvoc_thunk_RsResource_physmemUnmapFrom(struct PhysicalMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RsResource.offset), pParams); } @@ -243,12 +251,16 @@ static void __nvoc_init_funcTable_PhysicalMemory_1(PhysicalMemory *pThis) { pThis->__physmemControl_Prologue__ = &__nvoc_thunk_RmResource_physmemControl_Prologue; + pThis->__physmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_physmemIsGpuMapAllowed; + pThis->__physmemIsReady__ = &__nvoc_thunk_Memory_physmemIsReady; pThis->__physmemCheckCopyPermissions__ = &__nvoc_thunk_Memory_physmemCheckCopyPermissions; pThis->__physmemPreDestruct__ = &__nvoc_thunk_RsResource_physmemPreDestruct; + pThis->__physmemIsDuplicate__ = &__nvoc_thunk_Memory_physmemIsDuplicate; + pThis->__physmemUnmapFrom__ = &__nvoc_thunk_RsResource_physmemUnmapFrom; pThis->__physmemControl_Epilogue__ = &__nvoc_thunk_RmResource_physmemControl_Epilogue; diff --git a/src/nvidia/generated/g_phys_mem_nvoc.h b/src/nvidia/generated/g_phys_mem_nvoc.h index 9cc28a363..5f9160460 100644 --- a/src/nvidia/generated/g_phys_mem_nvoc.h +++ b/src/nvidia/generated/g_phys_mem_nvoc.h @@ -68,9 +68,11 @@ struct PhysicalMemory { NvU32 (*__physmemGetRefCount__)(struct PhysicalMemory *); NV_STATUS (*__physmemMapTo__)(struct PhysicalMemory *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__physmemControl_Prologue__)(struct PhysicalMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__physmemIsReady__)(struct PhysicalMemory *); + NvBool (*__physmemIsGpuMapAllowed__)(struct PhysicalMemory *, struct OBJGPU *); + NV_STATUS (*__physmemIsReady__)(struct PhysicalMemory *, NvBool); NV_STATUS (*__physmemCheckCopyPermissions__)(struct PhysicalMemory *, struct OBJGPU *, NvHandle); void (*__physmemPreDestruct__)(struct PhysicalMemory *); + NV_STATUS (*__physmemIsDuplicate__)(struct PhysicalMemory *, NvHandle, NvBool *); NV_STATUS (*__physmemUnmapFrom__)(struct PhysicalMemory *, RS_RES_UNMAP_FROM_PARAMS *); void (*__physmemControl_Epilogue__)(struct PhysicalMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__physmemControlLookup__)(struct PhysicalMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); @@ -119,9 +121,11 @@ NV_STATUS __nvoc_objCreate_PhysicalMemory(PhysicalMemory**, Dynamic*, NvU32, CAL #define physmemGetRefCount(pResource) physmemGetRefCount_DISPATCH(pResource) #define physmemMapTo(pResource, pParams) physmemMapTo_DISPATCH(pResource, pParams) #define physmemControl_Prologue(pResource, pCallContext, pParams) physmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define physmemIsReady(pMemory) physmemIsReady_DISPATCH(pMemory) +#define physmemIsGpuMapAllowed(pMemory, pGpu) physmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define physmemIsReady(pMemory, bCopyConstructorContext) physmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define physmemCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) physmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) #define physmemPreDestruct(pResource) physmemPreDestruct_DISPATCH(pResource) +#define physmemIsDuplicate(pMemory, hMemory, pDuplicate) physmemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) #define physmemUnmapFrom(pResource, pParams) physmemUnmapFrom_DISPATCH(pResource, pParams) #define physmemControl_Epilogue(pResource, pCallContext, pParams) physmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define physmemControlLookup(pResource, pParams, ppEntry) physmemControlLookup_DISPATCH(pResource, pParams, ppEntry) @@ -181,8 +185,12 @@ static inline NV_STATUS physmemControl_Prologue_DISPATCH(struct PhysicalMemory * return pResource->__physmemControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS physmemIsReady_DISPATCH(struct PhysicalMemory *pMemory) { - return pMemory->__physmemIsReady__(pMemory); +static inline NvBool physmemIsGpuMapAllowed_DISPATCH(struct PhysicalMemory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__physmemIsGpuMapAllowed__(pMemory, pGpu); +} + +static inline NV_STATUS physmemIsReady_DISPATCH(struct PhysicalMemory *pMemory, NvBool bCopyConstructorContext) { + return pMemory->__physmemIsReady__(pMemory, bCopyConstructorContext); } static inline NV_STATUS physmemCheckCopyPermissions_DISPATCH(struct PhysicalMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { @@ -193,6 +201,10 @@ static inline void physmemPreDestruct_DISPATCH(struct PhysicalMemory *pResource) pResource->__physmemPreDestruct__(pResource); } +static inline NV_STATUS physmemIsDuplicate_DISPATCH(struct PhysicalMemory *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return pMemory->__physmemIsDuplicate__(pMemory, hMemory, pDuplicate); +} + static inline NV_STATUS physmemUnmapFrom_DISPATCH(struct PhysicalMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return pResource->__physmemUnmapFrom__(pResource, pParams); } @@ -214,6 +226,7 @@ static inline NvBool physmemAccessCallback_DISPATCH(struct PhysicalMemory *pReso } NV_STATUS physmemConstruct_IMPL(struct PhysicalMemory *arg_pPhysicalMemory, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_physmemConstruct(arg_pPhysicalMemory, arg_pCallContext, arg_pParams) physmemConstruct_IMPL(arg_pPhysicalMemory, arg_pCallContext, arg_pParams) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_platform_nvoc.h b/src/nvidia/generated/g_platform_nvoc.h index ee9d4a9ac..a2f7b62df 100644 --- a/src/nvidia/generated/g_platform_nvoc.h +++ b/src/nvidia/generated/g_platform_nvoc.h @@ -54,6 +54,7 @@ typedef struct OBJPFM OBJPFM; #include "core/core.h" #include "nvCpuUuid.h" +#include "platform/nbsi/nbsi_table.h" /*! * Data structure representing single BlobData entry. @@ -100,9 +101,7 @@ struct OBJPFM { NvBool PDB_PROP_PFM_MODS_USE_TWO_STAGE_RC_RECOVER; NvBool PDB_PROP_PFM_POSSIBLE_HIGHRES_BOOT; NvBool PDB_PROP_PFM_APPLE_EDP_SUPPORTED; - NvBool PDB_PROP_PFM_BLOB_DATA_INIT_ATTEMPTED; - NvBool PDB_PROP_PFM_BLOB_DATA_INIT_SUCCEEDED; - PFM_BLOB_DATA blobData; + NBSI_OBJ nbsi; ACPI_ID_MAPPING acpiIdMapping[32][16]; }; @@ -135,12 +134,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJPFM; #define PDB_PROP_PFM_IS_MOBILE_BASE_NAME PDB_PROP_PFM_IS_MOBILE #define PDB_PROP_PFM_MODS_USE_TWO_STAGE_RC_RECOVER_BASE_CAST #define PDB_PROP_PFM_MODS_USE_TWO_STAGE_RC_RECOVER_BASE_NAME PDB_PROP_PFM_MODS_USE_TWO_STAGE_RC_RECOVER -#define PDB_PROP_PFM_BLOB_DATA_INIT_ATTEMPTED_BASE_CAST -#define PDB_PROP_PFM_BLOB_DATA_INIT_ATTEMPTED_BASE_NAME PDB_PROP_PFM_BLOB_DATA_INIT_ATTEMPTED #define PDB_PROP_PFM_ENABLE_PERF_WITHOUT_MXM_BASE_CAST #define PDB_PROP_PFM_ENABLE_PERF_WITHOUT_MXM_BASE_NAME PDB_PROP_PFM_ENABLE_PERF_WITHOUT_MXM -#define PDB_PROP_PFM_BLOB_DATA_INIT_SUCCEEDED_BASE_CAST -#define PDB_PROP_PFM_BLOB_DATA_INIT_SUCCEEDED_BASE_NAME PDB_PROP_PFM_BLOB_DATA_INIT_SUCCEEDED #define PDB_PROP_PFM_SUPPORTS_ACPI_BASE_CAST #define PDB_PROP_PFM_SUPPORTS_ACPI_BASE_NAME PDB_PROP_PFM_SUPPORTS_ACPI #define PDB_PROP_PFM_IS_TOSHIBA_MOBILE_BASE_CAST @@ -157,10 +152,10 @@ NV_STATUS __nvoc_objCreate_OBJPFM(OBJPFM**, Dynamic*, NvU32); __nvoc_objCreate_OBJPFM((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) NV_STATUS pfmConstruct_IMPL(struct OBJPFM *arg_pPfm); + #define __nvoc_pfmConstruct(arg_pPfm) pfmConstruct_IMPL(arg_pPfm) -void pfmBlobDataDestroy_IMPL(struct OBJPFM *pPfm); -#define pfmBlobDataDestroy(pPfm) pfmBlobDataDestroy_IMPL(pPfm) void pfmUpdateAcpiIdMapping_IMPL(struct OBJPFM *arg0, OBJGPU *arg1, NvU32 arg2, NvU32 arg3, NvU32 arg4, NvU32 arg5); + #ifdef __nvoc_platform_h_disabled static inline void pfmUpdateAcpiIdMapping(struct OBJPFM *arg0, OBJGPU *arg1, NvU32 arg2, NvU32 arg3, NvU32 arg4, NvU32 arg5) { NV_ASSERT_FAILED_PRECOMP("OBJPFM was disabled!"); @@ -170,6 +165,7 @@ static inline void pfmUpdateAcpiIdMapping(struct OBJPFM *arg0, OBJGPU *arg1, NvU #endif //__nvoc_platform_h_disabled NvU32 pfmFindAcpiId_IMPL(struct OBJPFM *arg0, OBJGPU *arg1, NvU32 arg2); + #ifdef __nvoc_platform_h_disabled static inline NvU32 pfmFindAcpiId(struct OBJPFM *arg0, OBJGPU *arg1, NvU32 arg2) { NV_ASSERT_FAILED_PRECOMP("OBJPFM was disabled!"); @@ -180,6 +176,7 @@ static inline NvU32 pfmFindAcpiId(struct OBJPFM *arg0, OBJGPU *arg1, NvU32 arg2) #endif //__nvoc_platform_h_disabled NvU32 pfmFindDodIndex_IMPL(struct OBJPFM *arg0, OBJGPU *arg1, NvU32 arg2); + #ifdef __nvoc_platform_h_disabled static inline NvU32 pfmFindDodIndex(struct OBJPFM *arg0, OBJGPU *arg1, NvU32 arg2) { NV_ASSERT_FAILED_PRECOMP("OBJPFM was disabled!"); @@ -190,6 +187,7 @@ static inline NvU32 pfmFindDodIndex(struct OBJPFM *arg0, OBJGPU *arg1, NvU32 arg #endif //__nvoc_platform_h_disabled NvU32 pfmFindDevMaskFromDodIndex_IMPL(struct OBJPFM *arg0, OBJGPU *arg1, NvU32 arg2); + #ifdef __nvoc_platform_h_disabled static inline NvU32 pfmFindDevMaskFromDodIndex(struct OBJPFM *arg0, OBJGPU *arg1, NvU32 arg2) { NV_ASSERT_FAILED_PRECOMP("OBJPFM was disabled!"); @@ -200,6 +198,7 @@ static inline NvU32 pfmFindDevMaskFromDodIndex(struct OBJPFM *arg0, OBJGPU *arg1 #endif //__nvoc_platform_h_disabled NvU32 pfmFindDevMaskFromAcpiId_IMPL(struct OBJPFM *arg0, OBJGPU *arg1, NvU32 arg2); + #ifdef __nvoc_platform_h_disabled static inline NvU32 pfmFindDevMaskFromAcpiId(struct OBJPFM *arg0, OBJGPU *arg1, NvU32 arg2) { NV_ASSERT_FAILED_PRECOMP("OBJPFM was disabled!"); @@ -210,6 +209,7 @@ static inline NvU32 pfmFindDevMaskFromAcpiId(struct OBJPFM *arg0, OBJGPU *arg1, #endif //__nvoc_platform_h_disabled void pfmUpdateDeviceAcpiId_IMPL(struct OBJPFM *arg0, OBJGPU *arg1, NvU32 arg2, NvU32 arg3); + #ifdef __nvoc_platform_h_disabled static inline void pfmUpdateDeviceAcpiId(struct OBJPFM *arg0, OBJGPU *arg1, NvU32 arg2, NvU32 arg3) { NV_ASSERT_FAILED_PRECOMP("OBJPFM was disabled!"); diff --git a/src/nvidia/generated/g_platform_request_handler_nvoc.h b/src/nvidia/generated/g_platform_request_handler_nvoc.h new file mode 100644 index 000000000..13b9ce919 --- /dev/null +++ b/src/nvidia/generated/g_platform_request_handler_nvoc.h @@ -0,0 +1,454 @@ +#ifndef _G_PLATFORM_REQUEST_HANDLER_NVOC_H_ +#define _G_PLATFORM_REQUEST_HANDLER_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_platform_request_handler_nvoc.h" + +#ifndef PLATFORM_REQUEST_HANDLER_H +#define PLATFORM_REQUEST_HANDLER_H + +/*! + * @file + * @brief Provides definitions for PlatformRequestHandler data structures and interfaces. + * + * Defines and structures used for the PlatformRequestHandler Object. + * PlatformRequestHandler handles ACPI events from SBIOS within the Resource Manager. + * PlatformRequestHandler is a child of OBJSYS object. + */ + +/* ------------------------ Includes --------------------------------------- */ +#include "core/core.h" +#include "os/os.h" +#include "platform/platform_request_handler_utils.h" +#include "ctrl/ctrl0000/ctrl0000system.h" +#include "ctrl/ctrl2080/ctrl2080internal.h" + +/* ------------------------ Macros ----------------------------------------- */ +// +// Macro to check if SW ACPI version 2X or not +// +#define PFM_REQ_HNDLR_IS_ACPI_VERSION_SW_2X(pPlatformRequestHandler) \ + (pPlatformRequestHandler->sensorData.PFMREQHNDLRACPIData.acpiVersionSw == \ + NV0000_CTRL_PFM_REQ_HNDLR_ACPI_REVISION_SW_2X) + +#define PFM_REQ_HNDLR_MAX_SENSORS_IN_BLOCK (32U) + +#define PFM_REQ_HNDLR_MAX_GPU_SUPPORTED (4U) + +// The following macros are used to attach flags to the sensor IDs in the +// Sensor block map and to isolate the IDs from the Sensor block map. +#define PFM_REQ_HNDLR_PSR_PUB_TAG (0x00001000UL) +#define PFM_REQ_HNDLR_PSR_ID_MASK (0x00000FFFUL) +#define PFM_REQ_HNDLR_PSR_PUB_ENTRY(x) ((x) | PFM_REQ_HNDLR_PSR_PUB_TAG) +#define PFM_REQ_HNDLR_PSR_ID(x) ((x) & PFM_REQ_HNDLR_PSR_ID_MASK) +#define PFM_REQ_HNDLR_CURR_VALUE_PUB_ENTRY(s) PFM_REQ_HNDLR_PSR_PUB_ENTRY(PFM_REQ_HNDLR_CURR_VALUE(s)) + +// PlatformRequestHandler Counter IDs (block independent) +#define PFM_REQ_HNDLR_TGPU_SENSOR NV0000_CTRL_SYSTEM_PARAM_TGPU +#define PFM_REQ_HNDLR_CTGP_SENSOR NV0000_CTRL_SYSTEM_PARAM_CTGP +#define PFM_REQ_HNDLR_PPMD_SENSOR NV0000_CTRL_SYSTEM_PARAM_PPMD +#define PFM_REQ_HNDLR_PSHAREPARAMS_COUNT (9U) +#define PFM_REQ_HNDLR_CURR_BASE (2) +#define PFM_REQ_HNDLR_CURR_VALUE(s) (PFM_REQ_HNDLR_CURR_BASE + ((s)%PFM_REQ_HNDLR_PSHAREPARAMS_COUNT)) +#define PFM_REQ_HNDLR_LIMIT_BASE (PFM_REQ_HNDLR_CURR_BASE + PFM_REQ_HNDLR_PSHAREPARAMS_COUNT) +#define PFM_REQ_HNDLR_LIMIT(s) (PFM_REQ_HNDLR_LIMIT_BASE + ((s)%PFM_REQ_HNDLR_PSHAREPARAMS_COUNT)) +#define PFM_REQ_HNDLR_PERIOD_BASE (PFM_REQ_HNDLR_LIMIT_BASE + PFM_REQ_HNDLR_PSHAREPARAMS_COUNT) +#define PFM_REQ_HNDLR_PERIOD(s) (PFM_REQ_HNDLR_PERIOD_BASE + ((s)%PFM_REQ_HNDLR_PSHAREPARAMS_COUNT)) +#define PFM_REQ_HNDLR_VALID_SENSOR_ID(b,v) (((b) <= (v)) && ((v) < (b+PFM_REQ_HNDLR_PSHAREPARAMS_COUNT))) +#define PFM_REQ_HNDLR_VALID_VALUE_ID(v) PFM_REQ_HNDLR_VALID_SENSOR_ID(PFM_REQ_HNDLR_CURR_BASE,v) +#define PFM_REQ_HNDLR_VALID_LIMIT_ID(v) PFM_REQ_HNDLR_VALID_SENSOR_ID(PFM_REQ_HNDLR_LIMIT_BASE,v) +#define PFM_REQ_HNDLR_AVAIL_SENSOR_MSK (23U) +#define PFM_REQ_HNDLR_TC_ENABLE (71U) +#define PFM_REQ_HNDLR_PM1_STATE_AVAIL (74U) +#define PFM_REQ_HNDLR_TDP_IDX (96U) +#define PFM_REQ_HNDLR_VPS_PS20_SUPPORT (97U) +#define PFM_REQ_HNDLR_RESERVED_COUNTER (100U) // This should be the last counter, update as needed. + +#define PFM_REQ_HNDLR_NUM_COUNTERS (PFM_REQ_HNDLR_RESERVED_COUNTER + 1) + +#define PFM_REQ_HNDLR_DEFAULT_COUNTER_HOLD_PERIOD_MS (20U) + +// Header to sensor structure +typedef struct +{ + NvU32 status; + NvU32 ulVersion; + + NvU32 tGpu; + + // Reserved legacy fields, do not use!. + NvU32 rsvd[6]; + NvU32 ctgp; + NvU32 ppmd; +} PFM_REQ_HNDLR_PSHAREDATA, *PPFM_REQ_HNDLR_PSHAREDATA; + +// Single sensor block +typedef struct +{ + NvBool bSupported; // indicates if counter is supported on the current system. + NvBool bVolatile; // indicates if counter is volatile or non-volatile. + NvBool bInvalid; // indicates if the counter is valid. + NvBool bOverridden; // indicates if counter has been overridden by the user. + NvU32 value; // value of the counter. + NvU32 lastSampled; // the last time each sample was collected. + NvU32 minInterval; // minimum time between samples +} PFM_REQ_HNDLR_SENSOR_COUNTER; + +typedef struct +{ + // driver set values + NvBool bPfmReqHndlrSupported; // reflects if all the required ACPI commands for PlatformRequestHandler are supported. + + // ACPI set values. + NvBool bSystemParamLimitUpdate; // reflects SBIOS current value for new update limits being available. + NvBool bEDPpeakLimitUpdateRequest; // reflects SBIOS current request for EDPpeak limit update event. + NvBool bUserConfigTGPmodeRequest; // reflects SBIOS current request for User Configurable TGP mode aka Turbo mode update event. + NvBool bPlatformUserConfigTGPSupport; // reflects SBIOS static requests to override power delta for User Configurable TGP mode + NvU32 platformLimitDeltamW; // Cached limit from platform custimization + NvU32 prevSbiosVPStateLimit; // reflects previous VPState requested to be set by SBIOS. + + NvU32 acpiVersionSw; // mapping between spec and supported sw state +} PFM_REQ_HNDLR_ACPI_CACHE; + +/*! + * Data cache for VPstate Info + */ +typedef struct +{ + NvBool bVpsPs20Supported; // reflects VPStates PS 20 Support + NvU32 vPstateIdxHighest; // reflects the highest VPstate Idx from VBIOS +} PFM_REQ_HNDLR_VPSTATE_CACHE; + +/*! + * Data cache for PlatformRequestHandler sensor provider interface + */ +typedef struct +{ + NvU32 version; // SBIOS reported version of PlatformRequestHandler support + NvU32 counterHoldPeriod; // The period of time a volatile counter will be considered valid + PFM_REQ_HNDLR_SENSOR_COUNTER PFMREQHNDLRSensorCache[PFM_REQ_HNDLR_NUM_COUNTERS]; + PFM_REQ_HNDLR_ACPI_CACHE PFMREQHNDLRACPIData; + NvU32 PFMREQHNDLRShareParamsAvailMask; // mask of the SBIOS reported PShareParams counters. +} PFM_REQ_HNDLR_SENSOR_DATA, *PPFM_REQ_HNDLR_SENSOR_DATA; + +/*! + * Platform Power Mode related data + */ +typedef struct +{ + + /*! + * Set while OS work item is pending execution. + */ + NvBool bWorkItemPending; + + /*! + * Mask of all the platform power modes supported on the system. + */ + NvU8 ppmMaskCurrent; + + /*! + * Current Platform Power Mode. + */ + NvU8 ppmIdxCurrent; + + /*! + * Requested new Platform Power mode index to be set. + */ + NvU8 ppmIdxRequested; +} PFM_REQ_HNDLR_PPM_DATA; + +/*! + * Control tracking and cache limits from SBIOS + */ +typedef struct +{ + NvBool bStateInitialized; + NvBool bPM1ForcedOff; + NvBool bTGPUOverrideRequired; + + // Current status of system applied EDPpeak update event + NvBool bEDPpeakUpdateEnabled; + + // Current status of system applied user configurable TGP enable event + NvBool bUserConfigTGPmodeEnabled; + + // Current status of platform customized and applied user configurable TGP delta + NvBool bPlatformUserConfigTGPmodeEnabled; +} PFM_REQ_HNDLR_CONTROL_DATA; + +/*! + * When updating GPU System control parameters, we may evaluate the _DSM method + * to query the latest limit inside SBIOS. But we are not allowed to evaluate + * ACPI method in level > PASSIVE, thus if we want to update the system limit at + * DPC level, we need to queue a workitem to defer the ACPI evaluation to + * passive level. This struct is used to record whether a workitem is queued for + * this purpose and what counter has been touched before the workitem is + * executed. (Refer to _pfmreqhndlrUpdateSystemParamLimitWorkItem for more details) + */ +typedef struct +{ + /*! + * Set while OS work item is pending execution. + */ + NvBool bWorkItemPending; + + /*! + * Bit mask for the counter IDs of the sensor data which has been updated + * before the pending work item was executed. + */ + NvU32 queuedCounterMask; +} PFM_REQ_HNDLR_SYS_CONTROL_DATA; + +#ifdef NVOC_PLATFORM_REQUEST_HANDLER_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct PlatformRequestHandler { + const struct NVOC_RTTI *__nvoc_rtti; + struct Object __nvoc_base_Object; + struct Object *__nvoc_pbase_Object; + struct PlatformRequestHandler *__nvoc_pbase_PlatformRequestHandler; + NvBool PDB_PROP_PFMREQHNDLR_SUPPORTED; + NvBool PDB_PROP_PFMREQHNDLR_SYS_CONTROL_SUPPORTED; + NvBool PDB_PROP_PFMREQHNDLR_IS_PLATFORM_LEGACY; + NvU32 pfmreqhndlrSupportedGpuIdx; + PFM_REQ_HNDLR_SENSOR_DATA sensorData; + PFM_REQ_HNDLR_PPM_DATA ppmData; + PFM_REQ_HNDLR_CONTROL_DATA controlData; + PFM_REQ_HNDLR_SYS_CONTROL_DATA sysControlData; + NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_FRM_DATA_PARAMS frmData; + PFM_REQ_HNDLR_VPSTATE_CACHE vPstateCache; + NvU32 dsmVersion; +}; + +#ifndef __NVOC_CLASS_PlatformRequestHandler_TYPEDEF__ +#define __NVOC_CLASS_PlatformRequestHandler_TYPEDEF__ +typedef struct PlatformRequestHandler PlatformRequestHandler; +#endif /* __NVOC_CLASS_PlatformRequestHandler_TYPEDEF__ */ + +#ifndef __nvoc_class_id_PlatformRequestHandler +#define __nvoc_class_id_PlatformRequestHandler 0x641a7f +#endif /* __nvoc_class_id_PlatformRequestHandler */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_PlatformRequestHandler; + +#define __staticCast_PlatformRequestHandler(pThis) \ + ((pThis)->__nvoc_pbase_PlatformRequestHandler) + +#ifdef __nvoc_platform_request_handler_h_disabled +#define __dynamicCast_PlatformRequestHandler(pThis) ((PlatformRequestHandler*)NULL) +#else //__nvoc_platform_request_handler_h_disabled +#define __dynamicCast_PlatformRequestHandler(pThis) \ + ((PlatformRequestHandler*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(PlatformRequestHandler))) +#endif //__nvoc_platform_request_handler_h_disabled + +#define PDB_PROP_PFMREQHNDLR_SYS_CONTROL_SUPPORTED_BASE_CAST +#define PDB_PROP_PFMREQHNDLR_SYS_CONTROL_SUPPORTED_BASE_NAME PDB_PROP_PFMREQHNDLR_SYS_CONTROL_SUPPORTED +#define PDB_PROP_PFMREQHNDLR_IS_PLATFORM_LEGACY_BASE_CAST +#define PDB_PROP_PFMREQHNDLR_IS_PLATFORM_LEGACY_BASE_NAME PDB_PROP_PFMREQHNDLR_IS_PLATFORM_LEGACY +#define PDB_PROP_PFMREQHNDLR_SUPPORTED_BASE_CAST +#define PDB_PROP_PFMREQHNDLR_SUPPORTED_BASE_NAME PDB_PROP_PFMREQHNDLR_SUPPORTED + +NV_STATUS __nvoc_objCreateDynamic_PlatformRequestHandler(PlatformRequestHandler**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_PlatformRequestHandler(PlatformRequestHandler**, Dynamic*, NvU32); +#define __objCreate_PlatformRequestHandler(ppNewObj, pParent, createFlags) \ + __nvoc_objCreate_PlatformRequestHandler((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) + +NV_STATUS pfmreqhndlrConstruct_IMPL(struct PlatformRequestHandler *arg_pPlatformRequestHandler); + +#define __nvoc_pfmreqhndlrConstruct(arg_pPlatformRequestHandler) pfmreqhndlrConstruct_IMPL(arg_pPlatformRequestHandler) +NV_STATUS pfmreqhndlrStateInit_IMPL(struct PlatformRequestHandler *pPlatformRequestHandler); + +#ifdef __nvoc_platform_request_handler_h_disabled +static inline NV_STATUS pfmreqhndlrStateInit(struct PlatformRequestHandler *pPlatformRequestHandler) { + NV_ASSERT_FAILED_PRECOMP("PlatformRequestHandler was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_platform_request_handler_h_disabled +#define pfmreqhndlrStateInit(pPlatformRequestHandler) pfmreqhndlrStateInit_IMPL(pPlatformRequestHandler) +#endif //__nvoc_platform_request_handler_h_disabled + +void pfmreqhndlrStateDestroy_IMPL(struct PlatformRequestHandler *pPlatformRequestHandler); + +#ifdef __nvoc_platform_request_handler_h_disabled +static inline void pfmreqhndlrStateDestroy(struct PlatformRequestHandler *pPlatformRequestHandler) { + NV_ASSERT_FAILED_PRECOMP("PlatformRequestHandler was disabled!"); +} +#else //__nvoc_platform_request_handler_h_disabled +#define pfmreqhndlrStateDestroy(pPlatformRequestHandler) pfmreqhndlrStateDestroy_IMPL(pPlatformRequestHandler) +#endif //__nvoc_platform_request_handler_h_disabled + +NV_STATUS pfmreqhndlrStateLoad_IMPL(struct PlatformRequestHandler *pPlatformRequestHandler); + +#ifdef __nvoc_platform_request_handler_h_disabled +static inline NV_STATUS pfmreqhndlrStateLoad(struct PlatformRequestHandler *pPlatformRequestHandler) { + NV_ASSERT_FAILED_PRECOMP("PlatformRequestHandler was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_platform_request_handler_h_disabled +#define pfmreqhndlrStateLoad(pPlatformRequestHandler) pfmreqhndlrStateLoad_IMPL(pPlatformRequestHandler) +#endif //__nvoc_platform_request_handler_h_disabled + +NV_STATUS pfmreqhndlrStateUnload_IMPL(struct PlatformRequestHandler *pPlatformRequestHandler); + +#ifdef __nvoc_platform_request_handler_h_disabled +static inline NV_STATUS pfmreqhndlrStateUnload(struct PlatformRequestHandler *pPlatformRequestHandler) { + NV_ASSERT_FAILED_PRECOMP("PlatformRequestHandler was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_platform_request_handler_h_disabled +#define pfmreqhndlrStateUnload(pPlatformRequestHandler) pfmreqhndlrStateUnload_IMPL(pPlatformRequestHandler) +#endif //__nvoc_platform_request_handler_h_disabled + +NvBool pfmreqhndlrIsInitialized_IMPL(struct PlatformRequestHandler *pPlatformRequestHandler); + +#ifdef __nvoc_platform_request_handler_h_disabled +static inline NvBool pfmreqhndlrIsInitialized(struct PlatformRequestHandler *pPlatformRequestHandler) { + NV_ASSERT_FAILED_PRECOMP("PlatformRequestHandler was disabled!"); + return NV_FALSE; +} +#else //__nvoc_platform_request_handler_h_disabled +#define pfmreqhndlrIsInitialized(pPlatformRequestHandler) pfmreqhndlrIsInitialized_IMPL(pPlatformRequestHandler) +#endif //__nvoc_platform_request_handler_h_disabled + +NV_STATUS pfmreqhndlrControl_IMPL(struct PlatformRequestHandler *pPlatformRequestHandler, NvU16 arg0, NvU16 arg1, NvU32 *arg2); + +#ifdef __nvoc_platform_request_handler_h_disabled +static inline NV_STATUS pfmreqhndlrControl(struct PlatformRequestHandler *pPlatformRequestHandler, NvU16 arg0, NvU16 arg1, NvU32 *arg2) { + NV_ASSERT_FAILED_PRECOMP("PlatformRequestHandler was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_platform_request_handler_h_disabled +#define pfmreqhndlrControl(pPlatformRequestHandler, arg0, arg1, arg2) pfmreqhndlrControl_IMPL(pPlatformRequestHandler, arg0, arg1, arg2) +#endif //__nvoc_platform_request_handler_h_disabled + +NV_STATUS pfmreqhndlrPcontrol_IMPL(struct PlatformRequestHandler *pPlatformRequestHandler, NvU32 input, NvBool bSbiosCall); + +#ifdef __nvoc_platform_request_handler_h_disabled +static inline NV_STATUS pfmreqhndlrPcontrol(struct PlatformRequestHandler *pPlatformRequestHandler, NvU32 input, NvBool bSbiosCall) { + NV_ASSERT_FAILED_PRECOMP("PlatformRequestHandler was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_platform_request_handler_h_disabled +#define pfmreqhndlrPcontrol(pPlatformRequestHandler, input, bSbiosCall) pfmreqhndlrPcontrol_IMPL(pPlatformRequestHandler, input, bSbiosCall) +#endif //__nvoc_platform_request_handler_h_disabled + +NV_STATUS pfmreqhndlrOperatingLimitUpdate_IMPL(struct PlatformRequestHandler *pPlatformRequestHandler, NvU32 id, NvU32 limit, NvBool bSet); + +#ifdef __nvoc_platform_request_handler_h_disabled +static inline NV_STATUS pfmreqhndlrOperatingLimitUpdate(struct PlatformRequestHandler *pPlatformRequestHandler, NvU32 id, NvU32 limit, NvBool bSet) { + NV_ASSERT_FAILED_PRECOMP("PlatformRequestHandler was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_platform_request_handler_h_disabled +#define pfmreqhndlrOperatingLimitUpdate(pPlatformRequestHandler, id, limit, bSet) pfmreqhndlrOperatingLimitUpdate_IMPL(pPlatformRequestHandler, id, limit, bSet) +#endif //__nvoc_platform_request_handler_h_disabled + +NV_STATUS pfmreqhndlrHandleCheckPM1Available_IMPL(struct PlatformRequestHandler *pPlatformRequestHandler, OBJGPU *pGpu, NvBool *pbPM1Available); + +#ifdef __nvoc_platform_request_handler_h_disabled +static inline NV_STATUS pfmreqhndlrHandleCheckPM1Available(struct PlatformRequestHandler *pPlatformRequestHandler, OBJGPU *pGpu, NvBool *pbPM1Available) { + NV_ASSERT_FAILED_PRECOMP("PlatformRequestHandler was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_platform_request_handler_h_disabled +#define pfmreqhndlrHandleCheckPM1Available(pPlatformRequestHandler, pGpu, pbPM1Available) pfmreqhndlrHandleCheckPM1Available_IMPL(pPlatformRequestHandler, pGpu, pbPM1Available) +#endif //__nvoc_platform_request_handler_h_disabled + +NV_STATUS pfmreqhndlrGetPerfSensorCounterById_IMPL(struct PlatformRequestHandler *pPlatformRequestHandler, NvU16 counterId, NvU32 *pCounterVal); + +#ifdef __nvoc_platform_request_handler_h_disabled +static inline NV_STATUS pfmreqhndlrGetPerfSensorCounterById(struct PlatformRequestHandler *pPlatformRequestHandler, NvU16 counterId, NvU32 *pCounterVal) { + NV_ASSERT_FAILED_PRECOMP("PlatformRequestHandler was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_platform_request_handler_h_disabled +#define pfmreqhndlrGetPerfSensorCounterById(pPlatformRequestHandler, counterId, pCounterVal) pfmreqhndlrGetPerfSensorCounterById_IMPL(pPlatformRequestHandler, counterId, pCounterVal) +#endif //__nvoc_platform_request_handler_h_disabled + +NV_STATUS pfmreqhndlrHandleEdppeakLimitUpdate_IMPL(struct PlatformRequestHandler *pPlatformRequestHandler, OBJGPU *pGpu, NvBool bEnable); + +#ifdef __nvoc_platform_request_handler_h_disabled +static inline NV_STATUS pfmreqhndlrHandleEdppeakLimitUpdate(struct PlatformRequestHandler *pPlatformRequestHandler, OBJGPU *pGpu, NvBool bEnable) { + NV_ASSERT_FAILED_PRECOMP("PlatformRequestHandler was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_platform_request_handler_h_disabled +#define pfmreqhndlrHandleEdppeakLimitUpdate(pPlatformRequestHandler, pGpu, bEnable) pfmreqhndlrHandleEdppeakLimitUpdate_IMPL(pPlatformRequestHandler, pGpu, bEnable) +#endif //__nvoc_platform_request_handler_h_disabled + +NV_STATUS pfmreqhndlrHandleUserConfigurableTgpMode_IMPL(struct PlatformRequestHandler *pPlatformRequestHandler, OBJGPU *pGpu, NvBool bEnable); + +#ifdef __nvoc_platform_request_handler_h_disabled +static inline NV_STATUS pfmreqhndlrHandleUserConfigurableTgpMode(struct PlatformRequestHandler *pPlatformRequestHandler, OBJGPU *pGpu, NvBool bEnable) { + NV_ASSERT_FAILED_PRECOMP("PlatformRequestHandler was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_platform_request_handler_h_disabled +#define pfmreqhndlrHandleUserConfigurableTgpMode(pPlatformRequestHandler, pGpu, bEnable) pfmreqhndlrHandleUserConfigurableTgpMode_IMPL(pPlatformRequestHandler, pGpu, bEnable) +#endif //__nvoc_platform_request_handler_h_disabled + +NV_STATUS pfmreqhndlrStateSync_IMPL(struct PlatformRequestHandler *pPlatformRequestHandler, OBJGPU *pGpu, NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS *pParams); + +#ifdef __nvoc_platform_request_handler_h_disabled +static inline NV_STATUS pfmreqhndlrStateSync(struct PlatformRequestHandler *pPlatformRequestHandler, OBJGPU *pGpu, NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS *pParams) { + NV_ASSERT_FAILED_PRECOMP("PlatformRequestHandler was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_platform_request_handler_h_disabled +#define pfmreqhndlrStateSync(pPlatformRequestHandler, pGpu, pParams) pfmreqhndlrStateSync_IMPL(pPlatformRequestHandler, pGpu, pParams) +#endif //__nvoc_platform_request_handler_h_disabled + +#undef PRIVATE_FIELD + + +/* ------------------------ Function Prototypes ---------------------------- */ + +OBJGPU *pfmreqhndlrGetGpu (struct PlatformRequestHandler *pPlatformRequestHandler); +NV_STATUS pfmreqhndlrInitGpu (struct PlatformRequestHandler *pPlatformRequestHandler); +NV_STATUS pfmreqhndlrInitSensors (struct PlatformRequestHandler *pPlatformRequestHandler); +NV_STATUS pfmreqhndlrUpdatePerfCounter (struct PlatformRequestHandler *pPlatformRequestHandler, NvU32 id, NvU32 value); +NV_STATUS pfmreqhndlrHandleStatusChangeEvent (struct PlatformRequestHandler *pPlatformRequestHandler, OBJGPU *pGpu); +NV_STATUS pfmreqhndlrCallACPI (OBJGPU *pGpu, NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS *pParams); +NV_STATUS pfmreqhndlrCallACPI_EX (OBJGPU *pGpu, NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX *pParams); +NV_STATUS pfmreqhndlrPassiveModeTransition (NvBool bEnter, NvU32 apiLockFlag, NvU32 gpuLockFlag); +NV_STATUS pfmreqhndlrQueryPlatformPowerModeDataFromBIOS (struct PlatformRequestHandler *pPlatformRequestHandler); +NV_STATUS pfmreqhndlrGetPerfSensorCounters (NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS *pParams, NvU16 mapFlags); + +#endif // PLATFORM_REQUEST_HANDLER_H + + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_PLATFORM_REQUEST_HANDLER_NVOC_H_ diff --git a/src/nvidia/generated/g_prereq_tracker_nvoc.h b/src/nvidia/generated/g_prereq_tracker_nvoc.h index b29327e2a..7e15edb23 100644 --- a/src/nvidia/generated/g_prereq_tracker_nvoc.h +++ b/src/nvidia/generated/g_prereq_tracker_nvoc.h @@ -200,10 +200,13 @@ NV_STATUS __nvoc_objCreate_PrereqTracker(PrereqTracker**, Dynamic*, NvU32, struc __nvoc_objCreate_PrereqTracker((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pParent) NV_STATUS prereqConstruct_IMPL(struct PrereqTracker *arg_pTracker, struct OBJGPU *arg_pParent); + #define __nvoc_prereqConstruct(arg_pTracker, arg_pParent) prereqConstruct_IMPL(arg_pTracker, arg_pParent) void prereqDestruct_IMPL(struct PrereqTracker *pTracker); + #define __nvoc_prereqDestruct(pTracker) prereqDestruct_IMPL(pTracker) NV_STATUS prereqSatisfy_IMPL(struct PrereqTracker *pTracker, PREREQ_ID prereqId); + #ifdef __nvoc_prereq_tracker_h_disabled static inline NV_STATUS prereqSatisfy(struct PrereqTracker *pTracker, PREREQ_ID prereqId) { NV_ASSERT_FAILED_PRECOMP("PrereqTracker was disabled!"); @@ -214,6 +217,7 @@ static inline NV_STATUS prereqSatisfy(struct PrereqTracker *pTracker, PREREQ_ID #endif //__nvoc_prereq_tracker_h_disabled NV_STATUS prereqRetract_IMPL(struct PrereqTracker *pTracker, PREREQ_ID prereqId); + #ifdef __nvoc_prereq_tracker_h_disabled static inline NV_STATUS prereqRetract(struct PrereqTracker *pTracker, PREREQ_ID prereqId) { NV_ASSERT_FAILED_PRECOMP("PrereqTracker was disabled!"); @@ -224,6 +228,7 @@ static inline NV_STATUS prereqRetract(struct PrereqTracker *pTracker, PREREQ_ID #endif //__nvoc_prereq_tracker_h_disabled NvBool prereqIdIsSatisfied_IMPL(struct PrereqTracker *pTracker, PREREQ_ID prereqId); + #ifdef __nvoc_prereq_tracker_h_disabled static inline NvBool prereqIdIsSatisfied(struct PrereqTracker *pTracker, PREREQ_ID prereqId) { NV_ASSERT_FAILED_PRECOMP("PrereqTracker was disabled!"); @@ -234,6 +239,7 @@ static inline NvBool prereqIdIsSatisfied(struct PrereqTracker *pTracker, PREREQ_ #endif //__nvoc_prereq_tracker_h_disabled NV_STATUS prereqComposeEntry_IMPL(struct PrereqTracker *pTracker, GpuPrereqCallback *callback, union PREREQ_ID_BIT_VECTOR *pDepends, PREREQ_ENTRY **ppPrereq); + #ifdef __nvoc_prereq_tracker_h_disabled static inline NV_STATUS prereqComposeEntry(struct PrereqTracker *pTracker, GpuPrereqCallback *callback, union PREREQ_ID_BIT_VECTOR *pDepends, PREREQ_ENTRY **ppPrereq) { NV_ASSERT_FAILED_PRECOMP("PrereqTracker was disabled!"); diff --git a/src/nvidia/generated/g_profiler_v1_nvoc.c b/src/nvidia/generated/g_profiler_v1_nvoc.c index 7526f3114..4083f2b48 100644 --- a/src/nvidia/generated/g_profiler_v1_nvoc.c +++ b/src/nvidia/generated/g_profiler_v1_nvoc.c @@ -165,6 +165,10 @@ static NV_STATUS __nvoc_thunk_RsResource_profilerUnmapFrom(struct Profiler *pRes return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_profilerIsDuplicate(struct Profiler *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_profilerControl_Epilogue(struct Profiler *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RmResource.offset), pCallContext, pParams); } @@ -372,6 +376,8 @@ static void __nvoc_init_funcTable_Profiler_1(Profiler *pThis, RmHalspecOwner *pR pThis->__profilerUnmapFrom__ = &__nvoc_thunk_RsResource_profilerUnmapFrom; + pThis->__profilerIsDuplicate__ = &__nvoc_thunk_RsResource_profilerIsDuplicate; + pThis->__profilerControl_Epilogue__ = &__nvoc_thunk_RmResource_profilerControl_Epilogue; pThis->__profilerControlLookup__ = &__nvoc_thunk_RsResource_profilerControlLookup; diff --git a/src/nvidia/generated/g_profiler_v1_nvoc.h b/src/nvidia/generated/g_profiler_v1_nvoc.h index da5a4040b..643ce01b9 100644 --- a/src/nvidia/generated/g_profiler_v1_nvoc.h +++ b/src/nvidia/generated/g_profiler_v1_nvoc.h @@ -79,6 +79,7 @@ struct Profiler { NV_STATUS (*__profilerInternalControlForward__)(struct Profiler *, NvU32, void *, NvU32); void (*__profilerPreDestruct__)(struct Profiler *); NV_STATUS (*__profilerUnmapFrom__)(struct Profiler *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__profilerIsDuplicate__)(struct Profiler *, NvHandle, NvBool *); void (*__profilerControl_Epilogue__)(struct Profiler *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__profilerControlLookup__)(struct Profiler *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__profilerMap__)(struct Profiler *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -136,12 +137,14 @@ NV_STATUS __nvoc_objCreate_Profiler(Profiler**, Dynamic*, NvU32, struct CALL_CON #define profilerInternalControlForward(pGpuResource, command, pParams, size) profilerInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define profilerPreDestruct(pResource) profilerPreDestruct_DISPATCH(pResource) #define profilerUnmapFrom(pResource, pParams) profilerUnmapFrom_DISPATCH(pResource, pParams) +#define profilerIsDuplicate(pResource, hMemory, pDuplicate) profilerIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define profilerControl_Epilogue(pResource, pCallContext, pParams) profilerControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define profilerControlLookup(pResource, pParams, ppEntry) profilerControlLookup_DISPATCH(pResource, pParams, ppEntry) #define profilerMap(pGpuResource, pCallContext, pParams, pCpuMapping) profilerMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define profilerAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) profilerAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool profilerIsProfilingPermitted_IMPL(struct Profiler *pProfiler); + #ifdef __nvoc_profiler_v1_h_disabled static inline NvBool profilerIsProfilingPermitted(struct Profiler *pProfiler) { NV_ASSERT_FAILED_PRECOMP("Profiler was disabled!"); @@ -157,6 +160,7 @@ static inline NV_STATUS profilerConstructState_ac1694(struct Profiler *pProfiler return NV_OK; } + #ifdef __nvoc_profiler_v1_h_disabled static inline NV_STATUS profilerConstructState(struct Profiler *pProfiler, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { NV_ASSERT_FAILED_PRECOMP("Profiler was disabled!"); @@ -172,11 +176,13 @@ static inline void profilerDestruct_d44104(struct Profiler *pProfiler) { return; } + #define __nvoc_profilerDestruct(pProfiler) profilerDestruct_d44104(pProfiler) static inline NV_STATUS profilerControlHwpmSupported_ac1694(struct Profiler *pProfiler, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return NV_OK; } + #ifdef __nvoc_profiler_v1_h_disabled static inline NV_STATUS profilerControlHwpmSupported(struct Profiler *pProfiler, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { NV_ASSERT_FAILED_PRECOMP("Profiler was disabled!"); @@ -292,6 +298,10 @@ static inline NV_STATUS profilerUnmapFrom_DISPATCH(struct Profiler *pResource, R return pResource->__profilerUnmapFrom__(pResource, pParams); } +static inline NV_STATUS profilerIsDuplicate_DISPATCH(struct Profiler *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__profilerIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void profilerControl_Epilogue_DISPATCH(struct Profiler *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__profilerControl_Epilogue__(pResource, pCallContext, pParams); } @@ -309,6 +319,7 @@ static inline NvBool profilerAccessCallback_DISPATCH(struct Profiler *pResource, } NV_STATUS profilerConstruct_IMPL(struct Profiler *arg_pProfiler, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_profilerConstruct(arg_pProfiler, arg_pCallContext, arg_pParams) profilerConstruct_IMPL(arg_pProfiler, arg_pCallContext, arg_pParams) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_profiler_v2_nvoc.c b/src/nvidia/generated/g_profiler_v2_nvoc.c index 5f4395e92..e9da5cdeb 100644 --- a/src/nvidia/generated/g_profiler_v2_nvoc.c +++ b/src/nvidia/generated/g_profiler_v2_nvoc.c @@ -165,6 +165,10 @@ static NV_STATUS __nvoc_thunk_RsResource_profilerBaseUnmapFrom(struct ProfilerBa return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_profilerBaseIsDuplicate(struct ProfilerBase *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_profilerBaseControl_Epilogue(struct ProfilerBase *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RmResource.offset), pCallContext, pParams); } @@ -368,12 +372,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler #endif }, { /* [12] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdGetTotalHsCredits_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) + /*flags=*/ 0x2210u, /*accessRight=*/0x0u, /*methodId=*/ 0xb0cc010du, /*paramSize=*/ sizeof(NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS), @@ -383,12 +387,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler #endif }, { /* [13] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdSetHsCredits_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) + /*flags=*/ 0x2210u, /*accessRight=*/0x0u, /*methodId=*/ 0xb0cc010eu, /*paramSize=*/ sizeof(NVB0CC_CTRL_SET_HS_CREDITS_PARAMS), @@ -398,12 +402,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler #endif }, { /* [14] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdGetHsCredits_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) + /*flags=*/ 0x2210u, /*accessRight=*/0x0u, /*methodId=*/ 0xb0cc010fu, /*paramSize=*/ sizeof(NVB0CC_CTRL_GET_HS_CREDITS_PARAMS), @@ -550,15 +554,15 @@ static void __nvoc_init_funcTable_ProfilerBase_1(ProfilerBase *pThis, RmHalspecO pThis->__profilerBaseCtrlCmdReleasePmAreaPcSampler__ = &profilerBaseCtrlCmdReleasePmAreaPcSampler_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) pThis->__profilerBaseCtrlCmdGetTotalHsCredits__ = &profilerBaseCtrlCmdGetTotalHsCredits_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) pThis->__profilerBaseCtrlCmdGetHsCredits__ = &profilerBaseCtrlCmdGetHsCredits_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) pThis->__profilerBaseCtrlCmdSetHsCredits__ = &profilerBaseCtrlCmdSetHsCredits_IMPL; #endif @@ -598,6 +602,8 @@ static void __nvoc_init_funcTable_ProfilerBase_1(ProfilerBase *pThis, RmHalspecO pThis->__profilerBaseUnmapFrom__ = &__nvoc_thunk_RsResource_profilerBaseUnmapFrom; + pThis->__profilerBaseIsDuplicate__ = &__nvoc_thunk_RsResource_profilerBaseIsDuplicate; + pThis->__profilerBaseControl_Epilogue__ = &__nvoc_thunk_RmResource_profilerBaseControl_Epilogue; pThis->__profilerBaseControlLookup__ = &__nvoc_thunk_RsResource_profilerBaseControlLookup; @@ -840,6 +846,10 @@ static NV_STATUS __nvoc_thunk_RsResource_profilerDevUnmapFrom(struct ProfilerDev return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_profilerDevIsDuplicate(struct ProfilerDev *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_profilerDevControl_Epilogue(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RmResource.offset), pCallContext, pParams); } @@ -941,6 +951,8 @@ static void __nvoc_init_funcTable_ProfilerDev_1(ProfilerDev *pThis, RmHalspecOwn pThis->__profilerDevUnmapFrom__ = &__nvoc_thunk_RsResource_profilerDevUnmapFrom; + pThis->__profilerDevIsDuplicate__ = &__nvoc_thunk_RsResource_profilerDevIsDuplicate; + pThis->__profilerDevControl_Epilogue__ = &__nvoc_thunk_RmResource_profilerDevControl_Epilogue; pThis->__profilerDevControlLookup__ = &__nvoc_thunk_RsResource_profilerDevControlLookup; diff --git a/src/nvidia/generated/g_profiler_v2_nvoc.h b/src/nvidia/generated/g_profiler_v2_nvoc.h index 4a25d239b..945cbf211 100644 --- a/src/nvidia/generated/g_profiler_v2_nvoc.h +++ b/src/nvidia/generated/g_profiler_v2_nvoc.h @@ -101,6 +101,7 @@ struct ProfilerBase { NV_STATUS (*__profilerBaseInternalControlForward__)(struct ProfilerBase *, NvU32, void *, NvU32); void (*__profilerBasePreDestruct__)(struct ProfilerBase *); NV_STATUS (*__profilerBaseUnmapFrom__)(struct ProfilerBase *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__profilerBaseIsDuplicate__)(struct ProfilerBase *, NvHandle, NvBool *); void (*__profilerBaseControl_Epilogue__)(struct ProfilerBase *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__profilerBaseControlLookup__)(struct ProfilerBase *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__profilerBaseMap__)(struct ProfilerBase *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -170,6 +171,7 @@ NV_STATUS __nvoc_objCreate_ProfilerBase(ProfilerBase**, Dynamic*, NvU32, struct #define profilerBaseInternalControlForward(pGpuResource, command, pParams, size) profilerBaseInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define profilerBasePreDestruct(pResource) profilerBasePreDestruct_DISPATCH(pResource) #define profilerBaseUnmapFrom(pResource, pParams) profilerBaseUnmapFrom_DISPATCH(pResource, pParams) +#define profilerBaseIsDuplicate(pResource, hMemory, pDuplicate) profilerBaseIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define profilerBaseControl_Epilogue(pResource, pCallContext, pParams) profilerBaseControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define profilerBaseControlLookup(pResource, pParams, ppEntry) profilerBaseControlLookup_DISPATCH(pResource, pParams, ppEntry) #define profilerBaseMap(pGpuResource, pCallContext, pParams, pCpuMapping) profilerBaseMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -178,6 +180,7 @@ static inline NV_STATUS profilerBaseConstructState_56cd7a(struct ProfilerBase *p return NV_OK; } + #ifdef __nvoc_profiler_v2_h_disabled static inline NV_STATUS profilerBaseConstructState(struct ProfilerBase *pProf, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { NV_ASSERT_FAILED_PRECOMP("ProfilerBase was disabled!"); @@ -193,6 +196,7 @@ static inline void profilerBaseDestructState_b3696a(struct ProfilerBase *pProf) return; } + #ifdef __nvoc_profiler_v2_h_disabled static inline void profilerBaseDestructState(struct ProfilerBase *pProf) { NV_ASSERT_FAILED_PRECOMP("ProfilerBase was disabled!"); @@ -377,6 +381,10 @@ static inline NV_STATUS profilerBaseUnmapFrom_DISPATCH(struct ProfilerBase *pRes return pResource->__profilerBaseUnmapFrom__(pResource, pParams); } +static inline NV_STATUS profilerBaseIsDuplicate_DISPATCH(struct ProfilerBase *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__profilerBaseIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void profilerBaseControl_Epilogue_DISPATCH(struct ProfilerBase *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__profilerBaseControl_Epilogue__(pResource, pCallContext, pParams); } @@ -394,8 +402,10 @@ static inline NvBool profilerBaseAccessCallback_DISPATCH(struct ProfilerBase *pR } NV_STATUS profilerBaseConstruct_IMPL(struct ProfilerBase *arg_pProf, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_profilerBaseConstruct(arg_pProf, arg_pCallContext, arg_pParams) profilerBaseConstruct_IMPL(arg_pProf, arg_pCallContext, arg_pParams) void profilerBaseDestruct_IMPL(struct ProfilerBase *pProf); + #define __nvoc_profilerBaseDestruct(pProf) profilerBaseDestruct_IMPL(pProf) #undef PRIVATE_FIELD @@ -433,6 +443,7 @@ struct ProfilerDev { NV_STATUS (*__profilerDevInternalControlForward__)(struct ProfilerDev *, NvU32, void *, NvU32); void (*__profilerDevPreDestruct__)(struct ProfilerDev *); NV_STATUS (*__profilerDevUnmapFrom__)(struct ProfilerDev *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__profilerDevIsDuplicate__)(struct ProfilerDev *, NvHandle, NvBool *); void (*__profilerDevControl_Epilogue__)(struct ProfilerDev *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__profilerDevControlLookup__)(struct ProfilerDev *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__profilerDevMap__)(struct ProfilerDev *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -485,12 +496,14 @@ NV_STATUS __nvoc_objCreate_ProfilerDev(ProfilerDev**, Dynamic*, NvU32, struct CA #define profilerDevInternalControlForward(pGpuResource, command, pParams, size) profilerDevInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define profilerDevPreDestruct(pResource) profilerDevPreDestruct_DISPATCH(pResource) #define profilerDevUnmapFrom(pResource, pParams) profilerDevUnmapFrom_DISPATCH(pResource, pParams) +#define profilerDevIsDuplicate(pResource, hMemory, pDuplicate) profilerDevIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define profilerDevControl_Epilogue(pResource, pCallContext, pParams) profilerDevControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define profilerDevControlLookup(pResource, pParams, ppEntry) profilerDevControlLookup_DISPATCH(pResource, pParams, ppEntry) #define profilerDevMap(pGpuResource, pCallContext, pParams, pCpuMapping) profilerDevMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define profilerDevAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) profilerDevAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS profilerDevConstructState_IMPL(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams, PROFILER_CLIENT_PERMISSIONS clientPermissions); + #ifdef __nvoc_profiler_v2_h_disabled static inline NV_STATUS profilerDevConstructState(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams, PROFILER_CLIENT_PERMISSIONS clientPermissions) { NV_ASSERT_FAILED_PRECOMP("ProfilerDev was disabled!"); @@ -504,6 +517,7 @@ static inline NV_STATUS profilerDevConstructState(struct ProfilerDev *pResource, NV_STATUS profilerDevConstructStatePrologue_FWCLIENT(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); + #ifdef __nvoc_profiler_v2_h_disabled static inline NV_STATUS profilerDevConstructStatePrologue(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { NV_ASSERT_FAILED_PRECOMP("ProfilerDev was disabled!"); @@ -517,6 +531,7 @@ static inline NV_STATUS profilerDevConstructStatePrologue(struct ProfilerDev *pR NV_STATUS profilerDevConstructStateInterlude_IMPL(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams, PROFILER_CLIENT_PERMISSIONS clientPermissions); + #ifdef __nvoc_profiler_v2_h_disabled static inline NV_STATUS profilerDevConstructStateInterlude(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams, PROFILER_CLIENT_PERMISSIONS clientPermissions) { NV_ASSERT_FAILED_PRECOMP("ProfilerDev was disabled!"); @@ -532,6 +547,7 @@ static inline NV_STATUS profilerDevConstructStateEpilogue_56cd7a(struct Profiler return NV_OK; } + #ifdef __nvoc_profiler_v2_h_disabled static inline NV_STATUS profilerDevConstructStateEpilogue(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { NV_ASSERT_FAILED_PRECOMP("ProfilerDev was disabled!"); @@ -545,6 +561,7 @@ static inline NV_STATUS profilerDevConstructStateEpilogue(struct ProfilerDev *pR NvBool profilerDevQueryCapabilities_IMPL(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams, PROFILER_CLIENT_PERMISSIONS *pClientPermissions); + #ifdef __nvoc_profiler_v2_h_disabled static inline NvBool profilerDevQueryCapabilities(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams, PROFILER_CLIENT_PERMISSIONS *pClientPermissions) { NV_ASSERT_FAILED_PRECOMP("ProfilerDev was disabled!"); @@ -558,6 +575,7 @@ static inline NvBool profilerDevQueryCapabilities(struct ProfilerDev *pResource, void profilerDevDestructState_FWCLIENT(struct ProfilerDev *pResource); + #ifdef __nvoc_profiler_v2_h_disabled static inline void profilerDevDestructState(struct ProfilerDev *pResource) { NV_ASSERT_FAILED_PRECOMP("ProfilerDev was disabled!"); @@ -640,6 +658,10 @@ static inline NV_STATUS profilerDevUnmapFrom_DISPATCH(struct ProfilerDev *pResou return pResource->__profilerDevUnmapFrom__(pResource, pParams); } +static inline NV_STATUS profilerDevIsDuplicate_DISPATCH(struct ProfilerDev *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__profilerDevIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void profilerDevControl_Epilogue_DISPATCH(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__profilerDevControl_Epilogue__(pResource, pCallContext, pParams); } @@ -657,8 +679,10 @@ static inline NvBool profilerDevAccessCallback_DISPATCH(struct ProfilerDev *pRes } NV_STATUS profilerDevConstruct_IMPL(struct ProfilerDev *arg_pResource, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_profilerDevConstruct(arg_pResource, arg_pCallContext, arg_pParams) profilerDevConstruct_IMPL(arg_pResource, arg_pCallContext, arg_pParams) void profilerDevDestruct_IMPL(struct ProfilerDev *pResource); + #define __nvoc_profilerDevDestruct(pResource) profilerDevDestruct_IMPL(pResource) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_ref_count_nvoc.h b/src/nvidia/generated/g_ref_count_nvoc.h index 4d39c80e0..dfdb5ed34 100644 --- a/src/nvidia/generated/g_ref_count_nvoc.h +++ b/src/nvidia/generated/g_ref_count_nvoc.h @@ -139,10 +139,13 @@ NV_STATUS __nvoc_objCreate_OBJREFCNT(OBJREFCNT**, Dynamic*, NvU32, Dynamic * arg __nvoc_objCreate_OBJREFCNT((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pParent, arg_tag, arg_pStateChangeCallback, arg_pResetCallback) NV_STATUS refcntConstruct_IMPL(POBJREFCNT arg_pRefcnt, Dynamic *arg_pParent, NvU32 arg_tag, RefcntStateChangeCallback *arg_pStateChangeCallback, RefcntResetCallback *arg_pResetCallback); + #define __nvoc_refcntConstruct(arg_pRefcnt, arg_pParent, arg_tag, arg_pStateChangeCallback, arg_pResetCallback) refcntConstruct_IMPL(arg_pRefcnt, arg_pParent, arg_tag, arg_pStateChangeCallback, arg_pResetCallback) void refcntDestruct_IMPL(POBJREFCNT pRefcnt); + #define __nvoc_refcntDestruct(pRefcnt) refcntDestruct_IMPL(pRefcnt) NV_STATUS refcntRequestReference_IMPL(POBJREFCNT pRefcnt, NvU64 arg0, NvU32 arg1, NvBool arg2); + #ifdef __nvoc_ref_count_h_disabled static inline NV_STATUS refcntRequestReference(POBJREFCNT pRefcnt, NvU64 arg0, NvU32 arg1, NvBool arg2) { NV_ASSERT_FAILED_PRECOMP("OBJREFCNT was disabled!"); @@ -153,6 +156,7 @@ static inline NV_STATUS refcntRequestReference(POBJREFCNT pRefcnt, NvU64 arg0, N #endif //__nvoc_ref_count_h_disabled NV_STATUS refcntReleaseReferences_IMPL(POBJREFCNT pRefcnt, NvU64 arg0, NvBool arg1); + #ifdef __nvoc_ref_count_h_disabled static inline NV_STATUS refcntReleaseReferences(POBJREFCNT pRefcnt, NvU64 arg0, NvBool arg1) { NV_ASSERT_FAILED_PRECOMP("OBJREFCNT was disabled!"); @@ -163,6 +167,7 @@ static inline NV_STATUS refcntReleaseReferences(POBJREFCNT pRefcnt, NvU64 arg0, #endif //__nvoc_ref_count_h_disabled NV_STATUS refcntReset_IMPL(POBJREFCNT pRefcnt, NvBool arg0); + #ifdef __nvoc_ref_count_h_disabled static inline NV_STATUS refcntReset(POBJREFCNT pRefcnt, NvBool arg0) { NV_ASSERT_FAILED_PRECOMP("OBJREFCNT was disabled!"); diff --git a/src/nvidia/generated/g_reg_mem_nvoc.c b/src/nvidia/generated/g_reg_mem_nvoc.c index c54ea8f80..53d65e755 100644 --- a/src/nvidia/generated/g_reg_mem_nvoc.c +++ b/src/nvidia/generated/g_reg_mem_nvoc.c @@ -145,8 +145,12 @@ static NV_STATUS __nvoc_thunk_RmResource_regmemControl_Prologue(struct RegisterM return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_Memory_regmemIsReady(struct RegisterMemory *pMemory) { - return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset)); +static NvBool __nvoc_thunk_Memory_regmemIsGpuMapAllowed(struct RegisterMemory *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), pGpu); +} + +static NV_STATUS __nvoc_thunk_Memory_regmemIsReady(struct RegisterMemory *pMemory, NvBool bCopyConstructorContext) { + return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), bCopyConstructorContext); } static NV_STATUS __nvoc_thunk_Memory_regmemCheckCopyPermissions(struct RegisterMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { @@ -157,6 +161,10 @@ static void __nvoc_thunk_RsResource_regmemPreDestruct(struct RegisterMemory *pRe resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_Memory_regmemIsDuplicate(struct RegisterMemory *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), hMemory, pDuplicate); +} + static NV_STATUS __nvoc_thunk_RsResource_regmemUnmapFrom(struct RegisterMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RsResource.offset), pParams); } @@ -243,12 +251,16 @@ static void __nvoc_init_funcTable_RegisterMemory_1(RegisterMemory *pThis) { pThis->__regmemControl_Prologue__ = &__nvoc_thunk_RmResource_regmemControl_Prologue; + pThis->__regmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_regmemIsGpuMapAllowed; + pThis->__regmemIsReady__ = &__nvoc_thunk_Memory_regmemIsReady; pThis->__regmemCheckCopyPermissions__ = &__nvoc_thunk_Memory_regmemCheckCopyPermissions; pThis->__regmemPreDestruct__ = &__nvoc_thunk_RsResource_regmemPreDestruct; + pThis->__regmemIsDuplicate__ = &__nvoc_thunk_Memory_regmemIsDuplicate; + pThis->__regmemUnmapFrom__ = &__nvoc_thunk_RsResource_regmemUnmapFrom; pThis->__regmemControl_Epilogue__ = &__nvoc_thunk_RmResource_regmemControl_Epilogue; diff --git a/src/nvidia/generated/g_reg_mem_nvoc.h b/src/nvidia/generated/g_reg_mem_nvoc.h index 062965ac7..6b4f5e8f4 100644 --- a/src/nvidia/generated/g_reg_mem_nvoc.h +++ b/src/nvidia/generated/g_reg_mem_nvoc.h @@ -68,9 +68,11 @@ struct RegisterMemory { NvU32 (*__regmemGetRefCount__)(struct RegisterMemory *); NV_STATUS (*__regmemMapTo__)(struct RegisterMemory *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__regmemControl_Prologue__)(struct RegisterMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__regmemIsReady__)(struct RegisterMemory *); + NvBool (*__regmemIsGpuMapAllowed__)(struct RegisterMemory *, struct OBJGPU *); + NV_STATUS (*__regmemIsReady__)(struct RegisterMemory *, NvBool); NV_STATUS (*__regmemCheckCopyPermissions__)(struct RegisterMemory *, struct OBJGPU *, NvHandle); void (*__regmemPreDestruct__)(struct RegisterMemory *); + NV_STATUS (*__regmemIsDuplicate__)(struct RegisterMemory *, NvHandle, NvBool *); NV_STATUS (*__regmemUnmapFrom__)(struct RegisterMemory *, RS_RES_UNMAP_FROM_PARAMS *); void (*__regmemControl_Epilogue__)(struct RegisterMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__regmemControlLookup__)(struct RegisterMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); @@ -119,9 +121,11 @@ NV_STATUS __nvoc_objCreate_RegisterMemory(RegisterMemory**, Dynamic*, NvU32, CAL #define regmemGetRefCount(pResource) regmemGetRefCount_DISPATCH(pResource) #define regmemMapTo(pResource, pParams) regmemMapTo_DISPATCH(pResource, pParams) #define regmemControl_Prologue(pResource, pCallContext, pParams) regmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define regmemIsReady(pMemory) regmemIsReady_DISPATCH(pMemory) +#define regmemIsGpuMapAllowed(pMemory, pGpu) regmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define regmemIsReady(pMemory, bCopyConstructorContext) regmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define regmemCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) regmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) #define regmemPreDestruct(pResource) regmemPreDestruct_DISPATCH(pResource) +#define regmemIsDuplicate(pMemory, hMemory, pDuplicate) regmemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) #define regmemUnmapFrom(pResource, pParams) regmemUnmapFrom_DISPATCH(pResource, pParams) #define regmemControl_Epilogue(pResource, pCallContext, pParams) regmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define regmemControlLookup(pResource, pParams, ppEntry) regmemControlLookup_DISPATCH(pResource, pParams, ppEntry) @@ -181,8 +185,12 @@ static inline NV_STATUS regmemControl_Prologue_DISPATCH(struct RegisterMemory *p return pResource->__regmemControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS regmemIsReady_DISPATCH(struct RegisterMemory *pMemory) { - return pMemory->__regmemIsReady__(pMemory); +static inline NvBool regmemIsGpuMapAllowed_DISPATCH(struct RegisterMemory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__regmemIsGpuMapAllowed__(pMemory, pGpu); +} + +static inline NV_STATUS regmemIsReady_DISPATCH(struct RegisterMemory *pMemory, NvBool bCopyConstructorContext) { + return pMemory->__regmemIsReady__(pMemory, bCopyConstructorContext); } static inline NV_STATUS regmemCheckCopyPermissions_DISPATCH(struct RegisterMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { @@ -193,6 +201,10 @@ static inline void regmemPreDestruct_DISPATCH(struct RegisterMemory *pResource) pResource->__regmemPreDestruct__(pResource); } +static inline NV_STATUS regmemIsDuplicate_DISPATCH(struct RegisterMemory *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return pMemory->__regmemIsDuplicate__(pMemory, hMemory, pDuplicate); +} + static inline NV_STATUS regmemUnmapFrom_DISPATCH(struct RegisterMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return pResource->__regmemUnmapFrom__(pResource, pParams); } @@ -214,6 +226,7 @@ static inline NvBool regmemAccessCallback_DISPATCH(struct RegisterMemory *pResou } NV_STATUS regmemConstruct_IMPL(struct RegisterMemory *arg_pRegisterMemory, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_regmemConstruct(arg_pRegisterMemory, arg_pCallContext, arg_pParams) regmemConstruct_IMPL(arg_pRegisterMemory, arg_pCallContext, arg_pParams) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_resource_fwd_decls_nvoc.h b/src/nvidia/generated/g_resource_fwd_decls_nvoc.h index ac9fb1624..2eb7c8305 100644 --- a/src/nvidia/generated/g_resource_fwd_decls_nvoc.h +++ b/src/nvidia/generated/g_resource_fwd_decls_nvoc.h @@ -31,14 +31,12 @@ extern "C" { #include "g_resource_fwd_decls_nvoc.h" -// -// This header is a temporary WAR for CORERM-3115 -// When that RFE is implemented, we'll be able to generate these forward decls -// from resource_list.h directly -// #ifndef RESOURCE_FWD_DECLS_H #define RESOURCE_FWD_DECLS_H +#include "nvtypes.h" +#include "nvoc/prelude.h" +#include "nvoc/object.h" #include "rmconfig.h" // Base classes @@ -187,331 +185,7 @@ typedef struct RsShared RsShared; -// Allocatable resources -struct AccessCounterBuffer; - -#ifndef __NVOC_CLASS_AccessCounterBuffer_TYPEDEF__ -#define __NVOC_CLASS_AccessCounterBuffer_TYPEDEF__ -typedef struct AccessCounterBuffer AccessCounterBuffer; -#endif /* __NVOC_CLASS_AccessCounterBuffer_TYPEDEF__ */ - -#ifndef __nvoc_class_id_AccessCounterBuffer -#define __nvoc_class_id_AccessCounterBuffer 0x1f0074 -#endif /* __nvoc_class_id_AccessCounterBuffer */ - - -struct KernelCeContext; - -#ifndef __NVOC_CLASS_KernelCeContext_TYPEDEF__ -#define __NVOC_CLASS_KernelCeContext_TYPEDEF__ -typedef struct KernelCeContext KernelCeContext; -#endif /* __NVOC_CLASS_KernelCeContext_TYPEDEF__ */ - -#ifndef __nvoc_class_id_KernelCeContext -#define __nvoc_class_id_KernelCeContext 0x2d0ee9 -#endif /* __nvoc_class_id_KernelCeContext */ - - -struct Channel; - -#ifndef __NVOC_CLASS_Channel_TYPEDEF__ -#define __NVOC_CLASS_Channel_TYPEDEF__ -typedef struct Channel Channel; -#endif /* __NVOC_CLASS_Channel_TYPEDEF__ */ - -#ifndef __nvoc_class_id_Channel -#define __nvoc_class_id_Channel 0x781dc9 -#endif /* __nvoc_class_id_Channel */ - - -struct ConsoleMemory; - -#ifndef __NVOC_CLASS_ConsoleMemory_TYPEDEF__ -#define __NVOC_CLASS_ConsoleMemory_TYPEDEF__ -typedef struct ConsoleMemory ConsoleMemory; -#endif /* __NVOC_CLASS_ConsoleMemory_TYPEDEF__ */ - -#ifndef __nvoc_class_id_ConsoleMemory -#define __nvoc_class_id_ConsoleMemory 0xaac69e -#endif /* __nvoc_class_id_ConsoleMemory */ - - -struct ContextDma; - -#ifndef __NVOC_CLASS_ContextDma_TYPEDEF__ -#define __NVOC_CLASS_ContextDma_TYPEDEF__ -typedef struct ContextDma ContextDma; -#endif /* __NVOC_CLASS_ContextDma_TYPEDEF__ */ - -#ifndef __nvoc_class_id_ContextDma -#define __nvoc_class_id_ContextDma 0x88441b -#endif /* __nvoc_class_id_ContextDma */ - - -struct DebugBufferApi; - -#ifndef __NVOC_CLASS_DebugBufferApi_TYPEDEF__ -#define __NVOC_CLASS_DebugBufferApi_TYPEDEF__ -typedef struct DebugBufferApi DebugBufferApi; -#endif /* __NVOC_CLASS_DebugBufferApi_TYPEDEF__ */ - -#ifndef __nvoc_class_id_DebugBufferApi -#define __nvoc_class_id_DebugBufferApi 0x5e7a1b -#endif /* __nvoc_class_id_DebugBufferApi */ - - -struct DeferredApiObject; - -#ifndef __NVOC_CLASS_DeferredApiObject_TYPEDEF__ -#define __NVOC_CLASS_DeferredApiObject_TYPEDEF__ -typedef struct DeferredApiObject DeferredApiObject; -#endif /* __NVOC_CLASS_DeferredApiObject_TYPEDEF__ */ - -#ifndef __nvoc_class_id_DeferredApiObject -#define __nvoc_class_id_DeferredApiObject 0x8ea933 -#endif /* __nvoc_class_id_DeferredApiObject */ - - -struct Device; - -#ifndef __NVOC_CLASS_Device_TYPEDEF__ -#define __NVOC_CLASS_Device_TYPEDEF__ -typedef struct Device Device; -#endif /* __NVOC_CLASS_Device_TYPEDEF__ */ - -#ifndef __nvoc_class_id_Device -#define __nvoc_class_id_Device 0xe0ac20 -#endif /* __nvoc_class_id_Device */ - - -struct DiagApi; - -#ifndef __NVOC_CLASS_DiagApi_TYPEDEF__ -#define __NVOC_CLASS_DiagApi_TYPEDEF__ -typedef struct DiagApi DiagApi; -#endif /* __NVOC_CLASS_DiagApi_TYPEDEF__ */ - -#ifndef __nvoc_class_id_DiagApi -#define __nvoc_class_id_DiagApi 0xaa3066 -#endif /* __nvoc_class_id_DiagApi */ - - -struct DispCapabilities; - -#ifndef __NVOC_CLASS_DispCapabilities_TYPEDEF__ -#define __NVOC_CLASS_DispCapabilities_TYPEDEF__ -typedef struct DispCapabilities DispCapabilities; -#endif /* __NVOC_CLASS_DispCapabilities_TYPEDEF__ */ - -#ifndef __nvoc_class_id_DispCapabilities -#define __nvoc_class_id_DispCapabilities 0x99db3e -#endif /* __nvoc_class_id_DispCapabilities */ - - -struct DispChannelDma; - -#ifndef __NVOC_CLASS_DispChannelDma_TYPEDEF__ -#define __NVOC_CLASS_DispChannelDma_TYPEDEF__ -typedef struct DispChannelDma DispChannelDma; -#endif /* __NVOC_CLASS_DispChannelDma_TYPEDEF__ */ - -#ifndef __nvoc_class_id_DispChannelDma -#define __nvoc_class_id_DispChannelDma 0xfe3d2e -#endif /* __nvoc_class_id_DispChannelDma */ - - -struct DispChannelPio; - -#ifndef __NVOC_CLASS_DispChannelPio_TYPEDEF__ -#define __NVOC_CLASS_DispChannelPio_TYPEDEF__ -typedef struct DispChannelPio DispChannelPio; -#endif /* __NVOC_CLASS_DispChannelPio_TYPEDEF__ */ - -#ifndef __nvoc_class_id_DispChannelPio -#define __nvoc_class_id_DispChannelPio 0x10dec3 -#endif /* __nvoc_class_id_DispChannelPio */ - - -struct DispCommon; - -#ifndef __NVOC_CLASS_DispCommon_TYPEDEF__ -#define __NVOC_CLASS_DispCommon_TYPEDEF__ -typedef struct DispCommon DispCommon; -#endif /* __NVOC_CLASS_DispCommon_TYPEDEF__ */ - -#ifndef __nvoc_class_id_DispCommon -#define __nvoc_class_id_DispCommon 0x41f4f2 -#endif /* __nvoc_class_id_DispCommon */ - - -struct DispSfUser; - -#ifndef __NVOC_CLASS_DispSfUser_TYPEDEF__ -#define __NVOC_CLASS_DispSfUser_TYPEDEF__ -typedef struct DispSfUser DispSfUser; -#endif /* __NVOC_CLASS_DispSfUser_TYPEDEF__ */ - -#ifndef __nvoc_class_id_DispSfUser -#define __nvoc_class_id_DispSfUser 0xba7439 -#endif /* __nvoc_class_id_DispSfUser */ - - -struct DispSwObj; - -#ifndef __NVOC_CLASS_DispSwObj_TYPEDEF__ -#define __NVOC_CLASS_DispSwObj_TYPEDEF__ -typedef struct DispSwObj DispSwObj; -#endif /* __NVOC_CLASS_DispSwObj_TYPEDEF__ */ - -#ifndef __nvoc_class_id_DispSwObj -#define __nvoc_class_id_DispSwObj 0x6aa5e2 -#endif /* __nvoc_class_id_DispSwObj */ - - -struct DispSwObject; - -#ifndef __NVOC_CLASS_DispSwObject_TYPEDEF__ -#define __NVOC_CLASS_DispSwObject_TYPEDEF__ -typedef struct DispSwObject DispSwObject; -#endif /* __NVOC_CLASS_DispSwObject_TYPEDEF__ */ - -#ifndef __nvoc_class_id_DispSwObject -#define __nvoc_class_id_DispSwObject 0x99ad6d -#endif /* __nvoc_class_id_DispSwObject */ - - -struct Event; - -#ifndef __NVOC_CLASS_Event_TYPEDEF__ -#define __NVOC_CLASS_Event_TYPEDEF__ -typedef struct Event Event; -#endif /* __NVOC_CLASS_Event_TYPEDEF__ */ - -#ifndef __nvoc_class_id_Event -#define __nvoc_class_id_Event 0xa4ecfc -#endif /* __nvoc_class_id_Event */ - - -struct EventBuffer; - -#ifndef __NVOC_CLASS_EventBuffer_TYPEDEF__ -#define __NVOC_CLASS_EventBuffer_TYPEDEF__ -typedef struct EventBuffer EventBuffer; -#endif /* __NVOC_CLASS_EventBuffer_TYPEDEF__ */ - -#ifndef __nvoc_class_id_EventBuffer -#define __nvoc_class_id_EventBuffer 0x63502b -#endif /* __nvoc_class_id_EventBuffer */ - - -struct FbSegment; - -#ifndef __NVOC_CLASS_FbSegment_TYPEDEF__ -#define __NVOC_CLASS_FbSegment_TYPEDEF__ -typedef struct FbSegment FbSegment; -#endif /* __NVOC_CLASS_FbSegment_TYPEDEF__ */ - -#ifndef __nvoc_class_id_FbSegment -#define __nvoc_class_id_FbSegment 0x2d55be -#endif /* __nvoc_class_id_FbSegment */ - - -struct FlaMemory; - -#ifndef __NVOC_CLASS_FlaMemory_TYPEDEF__ -#define __NVOC_CLASS_FlaMemory_TYPEDEF__ -typedef struct FlaMemory FlaMemory; -#endif /* __NVOC_CLASS_FlaMemory_TYPEDEF__ */ - -#ifndef __nvoc_class_id_FlaMemory -#define __nvoc_class_id_FlaMemory 0xe61ee1 -#endif /* __nvoc_class_id_FlaMemory */ - - -struct FmSessionApi; - -#ifndef __NVOC_CLASS_FmSessionApi_TYPEDEF__ -#define __NVOC_CLASS_FmSessionApi_TYPEDEF__ -typedef struct FmSessionApi FmSessionApi; -#endif /* __NVOC_CLASS_FmSessionApi_TYPEDEF__ */ - -#ifndef __nvoc_class_id_FmSessionApi -#define __nvoc_class_id_FmSessionApi 0xdfbd08 -#endif /* __nvoc_class_id_FmSessionApi */ - - -struct GenericEngineApi; - -#ifndef __NVOC_CLASS_GenericEngineApi_TYPEDEF__ -#define __NVOC_CLASS_GenericEngineApi_TYPEDEF__ -typedef struct GenericEngineApi GenericEngineApi; -#endif /* __NVOC_CLASS_GenericEngineApi_TYPEDEF__ */ - -#ifndef __nvoc_class_id_GenericEngineApi -#define __nvoc_class_id_GenericEngineApi 0x4bc329 -#endif /* __nvoc_class_id_GenericEngineApi */ - - -struct GpuManagementApi; - -#ifndef __NVOC_CLASS_GpuManagementApi_TYPEDEF__ -#define __NVOC_CLASS_GpuManagementApi_TYPEDEF__ -typedef struct GpuManagementApi GpuManagementApi; -#endif /* __NVOC_CLASS_GpuManagementApi_TYPEDEF__ */ - -#ifndef __nvoc_class_id_GpuManagementApi -#define __nvoc_class_id_GpuManagementApi 0x376305 -#endif /* __nvoc_class_id_GpuManagementApi */ - - -struct GraphicsContext; - -#ifndef __NVOC_CLASS_GraphicsContext_TYPEDEF__ -#define __NVOC_CLASS_GraphicsContext_TYPEDEF__ -typedef struct GraphicsContext GraphicsContext; -#endif /* __NVOC_CLASS_GraphicsContext_TYPEDEF__ */ - -#ifndef __nvoc_class_id_GraphicsContext -#define __nvoc_class_id_GraphicsContext 0x954c97 -#endif /* __nvoc_class_id_GraphicsContext */ - - -struct GraphicsObject; - -#ifndef __NVOC_CLASS_GraphicsObject_TYPEDEF__ -#define __NVOC_CLASS_GraphicsObject_TYPEDEF__ -typedef struct GraphicsObject GraphicsObject; -#endif /* __NVOC_CLASS_GraphicsObject_TYPEDEF__ */ - -#ifndef __nvoc_class_id_GraphicsObject -#define __nvoc_class_id_GraphicsObject 0x8cddfd -#endif /* __nvoc_class_id_GraphicsObject */ - - -struct Griddisplayless; - -#ifndef __NVOC_CLASS_Griddisplayless_TYPEDEF__ -#define __NVOC_CLASS_Griddisplayless_TYPEDEF__ -typedef struct Griddisplayless Griddisplayless; -#endif /* __NVOC_CLASS_Griddisplayless_TYPEDEF__ */ - -#ifndef __nvoc_class_id_Griddisplayless -#define __nvoc_class_id_Griddisplayless 0x3d03b2 -#endif /* __nvoc_class_id_Griddisplayless */ - - -struct Hdacodec; - -#ifndef __NVOC_CLASS_Hdacodec_TYPEDEF__ -#define __NVOC_CLASS_Hdacodec_TYPEDEF__ -typedef struct Hdacodec Hdacodec; -#endif /* __NVOC_CLASS_Hdacodec_TYPEDEF__ */ - -#ifndef __nvoc_class_id_Hdacodec -#define __nvoc_class_id_Hdacodec 0xf59a20 -#endif /* __nvoc_class_id_Hdacodec */ - - +// Classes disabled in orin but required forward declarations to build. struct HostVgpuDeviceApi; #ifndef __NVOC_CLASS_HostVgpuDeviceApi_TYPEDEF__ @@ -523,163 +197,7 @@ typedef struct HostVgpuDeviceApi HostVgpuDeviceApi; #define __nvoc_class_id_HostVgpuDeviceApi 0x4c4173 #endif /* __nvoc_class_id_HostVgpuDeviceApi */ - -struct HostVgpuDeviceApi_KERNEL; - -#ifndef __NVOC_CLASS_HostVgpuDeviceApi_KERNEL_TYPEDEF__ -#define __NVOC_CLASS_HostVgpuDeviceApi_KERNEL_TYPEDEF__ -typedef struct HostVgpuDeviceApi_KERNEL HostVgpuDeviceApi_KERNEL; -#endif /* __NVOC_CLASS_HostVgpuDeviceApi_KERNEL_TYPEDEF__ */ - -#ifndef __nvoc_class_id_HostVgpuDeviceApi_KERNEL -#define __nvoc_class_id_HostVgpuDeviceApi_KERNEL 0xeb7e48 -#endif /* __nvoc_class_id_HostVgpuDeviceApi_KERNEL */ - - -struct I2cApi; - -#ifndef __NVOC_CLASS_I2cApi_TYPEDEF__ -#define __NVOC_CLASS_I2cApi_TYPEDEF__ -typedef struct I2cApi I2cApi; -#endif /* __NVOC_CLASS_I2cApi_TYPEDEF__ */ - -#ifndef __nvoc_class_id_I2cApi -#define __nvoc_class_id_I2cApi 0xceb8f6 -#endif /* __nvoc_class_id_I2cApi */ - - -struct KernelCcuApi; - -#ifndef __NVOC_CLASS_KernelCcuApi_TYPEDEF__ -#define __NVOC_CLASS_KernelCcuApi_TYPEDEF__ -typedef struct KernelCcuApi KernelCcuApi; -#endif /* __NVOC_CLASS_KernelCcuApi_TYPEDEF__ */ - -#ifndef __nvoc_class_id_KernelCcuApi -#define __nvoc_class_id_KernelCcuApi 0x3abed3 -#endif /* __nvoc_class_id_KernelCcuApi */ - - -struct KernelChannel; - -#ifndef __NVOC_CLASS_KernelChannel_TYPEDEF__ -#define __NVOC_CLASS_KernelChannel_TYPEDEF__ -typedef struct KernelChannel KernelChannel; -#endif /* __NVOC_CLASS_KernelChannel_TYPEDEF__ */ - -#ifndef __nvoc_class_id_KernelChannel -#define __nvoc_class_id_KernelChannel 0x5d8d70 -#endif /* __nvoc_class_id_KernelChannel */ - - -struct KernelChannelGroupApi; - -#ifndef __NVOC_CLASS_KernelChannelGroupApi_TYPEDEF__ -#define __NVOC_CLASS_KernelChannelGroupApi_TYPEDEF__ -typedef struct KernelChannelGroupApi KernelChannelGroupApi; -#endif /* __NVOC_CLASS_KernelChannelGroupApi_TYPEDEF__ */ - -#ifndef __nvoc_class_id_KernelChannelGroupApi -#define __nvoc_class_id_KernelChannelGroupApi 0x2b5b80 -#endif /* __nvoc_class_id_KernelChannelGroupApi */ - - -struct KernelCtxShareApi; - -#ifndef __NVOC_CLASS_KernelCtxShareApi_TYPEDEF__ -#define __NVOC_CLASS_KernelCtxShareApi_TYPEDEF__ -typedef struct KernelCtxShareApi KernelCtxShareApi; -#endif /* __NVOC_CLASS_KernelCtxShareApi_TYPEDEF__ */ - -#ifndef __nvoc_class_id_KernelCtxShareApi -#define __nvoc_class_id_KernelCtxShareApi 0x1f9af1 -#endif /* __nvoc_class_id_KernelCtxShareApi */ - - -struct KernelGraphicsContext; - -#ifndef __NVOC_CLASS_KernelGraphicsContext_TYPEDEF__ -#define __NVOC_CLASS_KernelGraphicsContext_TYPEDEF__ -typedef struct KernelGraphicsContext KernelGraphicsContext; -#endif /* __NVOC_CLASS_KernelGraphicsContext_TYPEDEF__ */ - -#ifndef __nvoc_class_id_KernelGraphicsContext -#define __nvoc_class_id_KernelGraphicsContext 0x7ead09 -#endif /* __nvoc_class_id_KernelGraphicsContext */ - - -struct KernelGraphicsObject; - -#ifndef __NVOC_CLASS_KernelGraphicsObject_TYPEDEF__ -#define __NVOC_CLASS_KernelGraphicsObject_TYPEDEF__ -typedef struct KernelGraphicsObject KernelGraphicsObject; -#endif /* __NVOC_CLASS_KernelGraphicsObject_TYPEDEF__ */ - -#ifndef __nvoc_class_id_KernelGraphicsObject -#define __nvoc_class_id_KernelGraphicsObject 0x097648 -#endif /* __nvoc_class_id_KernelGraphicsObject */ - - -struct KernelSMDebuggerSession; - -#ifndef __NVOC_CLASS_KernelSMDebuggerSession_TYPEDEF__ -#define __NVOC_CLASS_KernelSMDebuggerSession_TYPEDEF__ -typedef struct KernelSMDebuggerSession KernelSMDebuggerSession; -#endif /* __NVOC_CLASS_KernelSMDebuggerSession_TYPEDEF__ */ - -#ifndef __nvoc_class_id_KernelSMDebuggerSession -#define __nvoc_class_id_KernelSMDebuggerSession 0x4adc81 -#endif /* __nvoc_class_id_KernelSMDebuggerSession */ - - -struct MemoryFabric; - -#ifndef __NVOC_CLASS_MemoryFabric_TYPEDEF__ -#define __NVOC_CLASS_MemoryFabric_TYPEDEF__ -typedef struct MemoryFabric MemoryFabric; -#endif /* __NVOC_CLASS_MemoryFabric_TYPEDEF__ */ - -#ifndef __nvoc_class_id_MemoryFabric -#define __nvoc_class_id_MemoryFabric 0x127499 -#endif /* __nvoc_class_id_MemoryFabric */ - - -struct MemoryHwResources; - -#ifndef __NVOC_CLASS_MemoryHwResources_TYPEDEF__ -#define __NVOC_CLASS_MemoryHwResources_TYPEDEF__ -typedef struct MemoryHwResources MemoryHwResources; -#endif /* __NVOC_CLASS_MemoryHwResources_TYPEDEF__ */ - -#ifndef __nvoc_class_id_MemoryHwResources -#define __nvoc_class_id_MemoryHwResources 0x9a2a71 -#endif /* __nvoc_class_id_MemoryHwResources */ - - -struct MemoryList; - -#ifndef __NVOC_CLASS_MemoryList_TYPEDEF__ -#define __NVOC_CLASS_MemoryList_TYPEDEF__ -typedef struct MemoryList MemoryList; -#endif /* __NVOC_CLASS_MemoryList_TYPEDEF__ */ - -#ifndef __nvoc_class_id_MemoryList -#define __nvoc_class_id_MemoryList 0x298f78 -#endif /* __nvoc_class_id_MemoryList */ - - -struct MmuFaultBuffer; - -#ifndef __NVOC_CLASS_MmuFaultBuffer_TYPEDEF__ -#define __NVOC_CLASS_MmuFaultBuffer_TYPEDEF__ -typedef struct MmuFaultBuffer MmuFaultBuffer; -#endif /* __NVOC_CLASS_MmuFaultBuffer_TYPEDEF__ */ - -#ifndef __nvoc_class_id_MmuFaultBuffer -#define __nvoc_class_id_MmuFaultBuffer 0x7e1829 -#endif /* __nvoc_class_id_MmuFaultBuffer */ - - + // also used by open rm struct MpsApi; #ifndef __NVOC_CLASS_MpsApi_TYPEDEF__ @@ -692,246 +210,6 @@ typedef struct MpsApi MpsApi; #endif /* __nvoc_class_id_MpsApi */ -struct MsencContext; - -#ifndef __NVOC_CLASS_MsencContext_TYPEDEF__ -#define __NVOC_CLASS_MsencContext_TYPEDEF__ -typedef struct MsencContext MsencContext; -#endif /* __NVOC_CLASS_MsencContext_TYPEDEF__ */ - -#ifndef __nvoc_class_id_MsencContext -#define __nvoc_class_id_MsencContext 0x88c92a -#endif /* __nvoc_class_id_MsencContext */ - - -struct NoDeviceMemory; - -#ifndef __NVOC_CLASS_NoDeviceMemory_TYPEDEF__ -#define __NVOC_CLASS_NoDeviceMemory_TYPEDEF__ -typedef struct NoDeviceMemory NoDeviceMemory; -#endif /* __NVOC_CLASS_NoDeviceMemory_TYPEDEF__ */ - -#ifndef __nvoc_class_id_NoDeviceMemory -#define __nvoc_class_id_NoDeviceMemory 0x6c0832 -#endif /* __nvoc_class_id_NoDeviceMemory */ - - -struct NpuResource; - -#ifndef __NVOC_CLASS_NpuResource_TYPEDEF__ -#define __NVOC_CLASS_NpuResource_TYPEDEF__ -typedef struct NpuResource NpuResource; -#endif /* __NVOC_CLASS_NpuResource_TYPEDEF__ */ - -#ifndef __nvoc_class_id_NpuResource -#define __nvoc_class_id_NpuResource 0x4d1af2 -#endif /* __nvoc_class_id_NpuResource */ - - -struct NvdecContext; - -#ifndef __NVOC_CLASS_NvdecContext_TYPEDEF__ -#define __NVOC_CLASS_NvdecContext_TYPEDEF__ -typedef struct NvdecContext NvdecContext; -#endif /* __NVOC_CLASS_NvdecContext_TYPEDEF__ */ - -#ifndef __nvoc_class_id_NvdecContext -#define __nvoc_class_id_NvdecContext 0x70d2be -#endif /* __nvoc_class_id_NvdecContext */ - - -struct NvDispApi; - -#ifndef __NVOC_CLASS_NvDispApi_TYPEDEF__ -#define __NVOC_CLASS_NvDispApi_TYPEDEF__ -typedef struct NvDispApi NvDispApi; -#endif /* __NVOC_CLASS_NvDispApi_TYPEDEF__ */ - -#ifndef __nvoc_class_id_NvDispApi -#define __nvoc_class_id_NvDispApi 0x36aa0b -#endif /* __nvoc_class_id_NvDispApi */ - - -struct NvjpgContext; - -#ifndef __NVOC_CLASS_NvjpgContext_TYPEDEF__ -#define __NVOC_CLASS_NvjpgContext_TYPEDEF__ -typedef struct NvjpgContext NvjpgContext; -#endif /* __NVOC_CLASS_NvjpgContext_TYPEDEF__ */ - -#ifndef __nvoc_class_id_NvjpgContext -#define __nvoc_class_id_NvjpgContext 0x08c1ce -#endif /* __nvoc_class_id_NvjpgContext */ - - -struct OfaContext; - -#ifndef __NVOC_CLASS_OfaContext_TYPEDEF__ -#define __NVOC_CLASS_OfaContext_TYPEDEF__ -typedef struct OfaContext OfaContext; -#endif /* __NVOC_CLASS_OfaContext_TYPEDEF__ */ - -#ifndef __nvoc_class_id_OfaContext -#define __nvoc_class_id_OfaContext 0xf63d99 -#endif /* __nvoc_class_id_OfaContext */ - - -struct OsDescMemory; - -#ifndef __NVOC_CLASS_OsDescMemory_TYPEDEF__ -#define __NVOC_CLASS_OsDescMemory_TYPEDEF__ -typedef struct OsDescMemory OsDescMemory; -#endif /* __NVOC_CLASS_OsDescMemory_TYPEDEF__ */ - -#ifndef __nvoc_class_id_OsDescMemory -#define __nvoc_class_id_OsDescMemory 0xb3dacd -#endif /* __nvoc_class_id_OsDescMemory */ - - -struct UserLocalDescMemory; - -#ifndef __NVOC_CLASS_UserLocalDescMemory_TYPEDEF__ -#define __NVOC_CLASS_UserLocalDescMemory_TYPEDEF__ -typedef struct UserLocalDescMemory UserLocalDescMemory; -#endif /* __NVOC_CLASS_UserLocalDescMemory_TYPEDEF__ */ - -#ifndef __nvoc_class_id_UserLocalDescMemory -#define __nvoc_class_id_UserLocalDescMemory 0x799456 -#endif /* __nvoc_class_id_UserLocalDescMemory */ - - -struct P2PApi; - -#ifndef __NVOC_CLASS_P2PApi_TYPEDEF__ -#define __NVOC_CLASS_P2PApi_TYPEDEF__ -typedef struct P2PApi P2PApi; -#endif /* __NVOC_CLASS_P2PApi_TYPEDEF__ */ - -#ifndef __nvoc_class_id_P2PApi -#define __nvoc_class_id_P2PApi 0x3982b7 -#endif /* __nvoc_class_id_P2PApi */ - - -struct PerfBuffer; - -#ifndef __NVOC_CLASS_PerfBuffer_TYPEDEF__ -#define __NVOC_CLASS_PerfBuffer_TYPEDEF__ -typedef struct PerfBuffer PerfBuffer; -#endif /* __NVOC_CLASS_PerfBuffer_TYPEDEF__ */ - -#ifndef __nvoc_class_id_PerfBuffer -#define __nvoc_class_id_PerfBuffer 0x4bc43b -#endif /* __nvoc_class_id_PerfBuffer */ - - -struct PhysicalMemory; - -#ifndef __NVOC_CLASS_PhysicalMemory_TYPEDEF__ -#define __NVOC_CLASS_PhysicalMemory_TYPEDEF__ -typedef struct PhysicalMemory PhysicalMemory; -#endif /* __NVOC_CLASS_PhysicalMemory_TYPEDEF__ */ - -#ifndef __nvoc_class_id_PhysicalMemory -#define __nvoc_class_id_PhysicalMemory 0x5fccf2 -#endif /* __nvoc_class_id_PhysicalMemory */ - - -struct PhysMemSubAlloc; - -#ifndef __NVOC_CLASS_PhysMemSubAlloc_TYPEDEF__ -#define __NVOC_CLASS_PhysMemSubAlloc_TYPEDEF__ -typedef struct PhysMemSubAlloc PhysMemSubAlloc; -#endif /* __NVOC_CLASS_PhysMemSubAlloc_TYPEDEF__ */ - -#ifndef __nvoc_class_id_PhysMemSubAlloc -#define __nvoc_class_id_PhysMemSubAlloc 0x2351fc -#endif /* __nvoc_class_id_PhysMemSubAlloc */ - - -struct Profiler; - -#ifndef __NVOC_CLASS_Profiler_TYPEDEF__ -#define __NVOC_CLASS_Profiler_TYPEDEF__ -typedef struct Profiler Profiler; -#endif /* __NVOC_CLASS_Profiler_TYPEDEF__ */ - -#ifndef __nvoc_class_id_Profiler -#define __nvoc_class_id_Profiler 0x65b4c7 -#endif /* __nvoc_class_id_Profiler */ - - -struct ProfilerCtx; - -#ifndef __NVOC_CLASS_ProfilerCtx_TYPEDEF__ -#define __NVOC_CLASS_ProfilerCtx_TYPEDEF__ -typedef struct ProfilerCtx ProfilerCtx; -#endif /* __NVOC_CLASS_ProfilerCtx_TYPEDEF__ */ - -#ifndef __nvoc_class_id_ProfilerCtx -#define __nvoc_class_id_ProfilerCtx 0xe99229 -#endif /* __nvoc_class_id_ProfilerCtx */ - - -struct ProfilerDev; - -#ifndef __NVOC_CLASS_ProfilerDev_TYPEDEF__ -#define __NVOC_CLASS_ProfilerDev_TYPEDEF__ -typedef struct ProfilerDev ProfilerDev; -#endif /* __NVOC_CLASS_ProfilerDev_TYPEDEF__ */ - -#ifndef __nvoc_class_id_ProfilerDev -#define __nvoc_class_id_ProfilerDev 0x54d077 -#endif /* __nvoc_class_id_ProfilerDev */ - - -struct RegisterMemory; - -#ifndef __NVOC_CLASS_RegisterMemory_TYPEDEF__ -#define __NVOC_CLASS_RegisterMemory_TYPEDEF__ -typedef struct RegisterMemory RegisterMemory; -#endif /* __NVOC_CLASS_RegisterMemory_TYPEDEF__ */ - -#ifndef __nvoc_class_id_RegisterMemory -#define __nvoc_class_id_RegisterMemory 0x40d457 -#endif /* __nvoc_class_id_RegisterMemory */ - - -struct RemapperObject; - -#ifndef __NVOC_CLASS_RemapperObject_TYPEDEF__ -#define __NVOC_CLASS_RemapperObject_TYPEDEF__ -typedef struct RemapperObject RemapperObject; -#endif /* __NVOC_CLASS_RemapperObject_TYPEDEF__ */ - -#ifndef __nvoc_class_id_RemapperObject -#define __nvoc_class_id_RemapperObject 0xfc96cb -#endif /* __nvoc_class_id_RemapperObject */ - - -struct RgLineCallback; - -#ifndef __NVOC_CLASS_RgLineCallback_TYPEDEF__ -#define __NVOC_CLASS_RgLineCallback_TYPEDEF__ -typedef struct RgLineCallback RgLineCallback; -#endif /* __NVOC_CLASS_RgLineCallback_TYPEDEF__ */ - -#ifndef __nvoc_class_id_RgLineCallback -#define __nvoc_class_id_RgLineCallback 0xa3ff1c -#endif /* __nvoc_class_id_RgLineCallback */ - - -struct RmClientResource; - -#ifndef __NVOC_CLASS_RmClientResource_TYPEDEF__ -#define __NVOC_CLASS_RmClientResource_TYPEDEF__ -typedef struct RmClientResource RmClientResource; -#endif /* __NVOC_CLASS_RmClientResource_TYPEDEF__ */ - -#ifndef __nvoc_class_id_RmClientResource -#define __nvoc_class_id_RmClientResource 0x37a701 -#endif /* __nvoc_class_id_RmClientResource */ - - struct MIGConfigSession; #ifndef __NVOC_CLASS_MIGConfigSession_TYPEDEF__ @@ -944,16 +222,16 @@ typedef struct MIGConfigSession MIGConfigSession; #endif /* __nvoc_class_id_MIGConfigSession */ -struct ComputeInstanceSubscription; +struct FmSessionApi; -#ifndef __NVOC_CLASS_ComputeInstanceSubscription_TYPEDEF__ -#define __NVOC_CLASS_ComputeInstanceSubscription_TYPEDEF__ -typedef struct ComputeInstanceSubscription ComputeInstanceSubscription; -#endif /* __NVOC_CLASS_ComputeInstanceSubscription_TYPEDEF__ */ +#ifndef __NVOC_CLASS_FmSessionApi_TYPEDEF__ +#define __NVOC_CLASS_FmSessionApi_TYPEDEF__ +typedef struct FmSessionApi FmSessionApi; +#endif /* __NVOC_CLASS_FmSessionApi_TYPEDEF__ */ -#ifndef __nvoc_class_id_ComputeInstanceSubscription -#define __nvoc_class_id_ComputeInstanceSubscription 0xd1f238 -#endif /* __nvoc_class_id_ComputeInstanceSubscription */ +#ifndef __nvoc_class_id_FmSessionApi +#define __nvoc_class_id_FmSessionApi 0xdfbd08 +#endif /* __nvoc_class_id_FmSessionApi */ struct MIGMonitorSession; @@ -968,138 +246,6 @@ typedef struct MIGMonitorSession MIGMonitorSession; #endif /* __nvoc_class_id_MIGMonitorSession */ -struct GPUInstanceSubscription; - -#ifndef __NVOC_CLASS_GPUInstanceSubscription_TYPEDEF__ -#define __NVOC_CLASS_GPUInstanceSubscription_TYPEDEF__ -typedef struct GPUInstanceSubscription GPUInstanceSubscription; -#endif /* __NVOC_CLASS_GPUInstanceSubscription_TYPEDEF__ */ - -#ifndef __nvoc_class_id_GPUInstanceSubscription -#define __nvoc_class_id_GPUInstanceSubscription 0x91fde7 -#endif /* __nvoc_class_id_GPUInstanceSubscription */ - - -struct SMDebuggerSession; - -#ifndef __NVOC_CLASS_SMDebuggerSession_TYPEDEF__ -#define __NVOC_CLASS_SMDebuggerSession_TYPEDEF__ -typedef struct SMDebuggerSession SMDebuggerSession; -#endif /* __NVOC_CLASS_SMDebuggerSession_TYPEDEF__ */ - -#ifndef __nvoc_class_id_SMDebuggerSession -#define __nvoc_class_id_SMDebuggerSession 0x9afab7 -#endif /* __nvoc_class_id_SMDebuggerSession */ - - -struct SoftwareMethodTest; - -#ifndef __NVOC_CLASS_SoftwareMethodTest_TYPEDEF__ -#define __NVOC_CLASS_SoftwareMethodTest_TYPEDEF__ -typedef struct SoftwareMethodTest SoftwareMethodTest; -#endif /* __NVOC_CLASS_SoftwareMethodTest_TYPEDEF__ */ - -#ifndef __nvoc_class_id_SoftwareMethodTest -#define __nvoc_class_id_SoftwareMethodTest 0xdea092 -#endif /* __nvoc_class_id_SoftwareMethodTest */ - - -struct Subdevice; - -#ifndef __NVOC_CLASS_Subdevice_TYPEDEF__ -#define __NVOC_CLASS_Subdevice_TYPEDEF__ -typedef struct Subdevice Subdevice; -#endif /* __NVOC_CLASS_Subdevice_TYPEDEF__ */ - -#ifndef __nvoc_class_id_Subdevice -#define __nvoc_class_id_Subdevice 0x4b01b3 -#endif /* __nvoc_class_id_Subdevice */ - - -struct BinaryApi; - -#ifndef __NVOC_CLASS_BinaryApi_TYPEDEF__ -#define __NVOC_CLASS_BinaryApi_TYPEDEF__ -typedef struct BinaryApi BinaryApi; -#endif /* __NVOC_CLASS_BinaryApi_TYPEDEF__ */ - -#ifndef __nvoc_class_id_BinaryApi -#define __nvoc_class_id_BinaryApi 0xb7a47c -#endif /* __nvoc_class_id_BinaryApi */ - - -struct BinaryApiPrivileged; - -#ifndef __NVOC_CLASS_BinaryApiPrivileged_TYPEDEF__ -#define __NVOC_CLASS_BinaryApiPrivileged_TYPEDEF__ -typedef struct BinaryApiPrivileged BinaryApiPrivileged; -#endif /* __NVOC_CLASS_BinaryApiPrivileged_TYPEDEF__ */ - -#ifndef __nvoc_class_id_BinaryApiPrivileged -#define __nvoc_class_id_BinaryApiPrivileged 0x1c0579 -#endif /* __nvoc_class_id_BinaryApiPrivileged */ - - -struct SyncGpuBoost; - -#ifndef __NVOC_CLASS_SyncGpuBoost_TYPEDEF__ -#define __NVOC_CLASS_SyncGpuBoost_TYPEDEF__ -typedef struct SyncGpuBoost SyncGpuBoost; -#endif /* __NVOC_CLASS_SyncGpuBoost_TYPEDEF__ */ - -#ifndef __nvoc_class_id_SyncGpuBoost -#define __nvoc_class_id_SyncGpuBoost 0xc7e30b -#endif /* __nvoc_class_id_SyncGpuBoost */ - - -struct SyncpointMemory; - -#ifndef __NVOC_CLASS_SyncpointMemory_TYPEDEF__ -#define __NVOC_CLASS_SyncpointMemory_TYPEDEF__ -typedef struct SyncpointMemory SyncpointMemory; -#endif /* __NVOC_CLASS_SyncpointMemory_TYPEDEF__ */ - -#ifndef __nvoc_class_id_SyncpointMemory -#define __nvoc_class_id_SyncpointMemory 0x529def -#endif /* __nvoc_class_id_SyncpointMemory */ - - -struct SystemMemory; - -#ifndef __NVOC_CLASS_SystemMemory_TYPEDEF__ -#define __NVOC_CLASS_SystemMemory_TYPEDEF__ -typedef struct SystemMemory SystemMemory; -#endif /* __NVOC_CLASS_SystemMemory_TYPEDEF__ */ - -#ifndef __nvoc_class_id_SystemMemory -#define __nvoc_class_id_SystemMemory 0x007a98 -#endif /* __nvoc_class_id_SystemMemory */ - - -struct ThirdPartyP2P; - -#ifndef __NVOC_CLASS_ThirdPartyP2P_TYPEDEF__ -#define __NVOC_CLASS_ThirdPartyP2P_TYPEDEF__ -typedef struct ThirdPartyP2P ThirdPartyP2P; -#endif /* __NVOC_CLASS_ThirdPartyP2P_TYPEDEF__ */ - -#ifndef __nvoc_class_id_ThirdPartyP2P -#define __nvoc_class_id_ThirdPartyP2P 0x34d08b -#endif /* __nvoc_class_id_ThirdPartyP2P */ - - -struct TimedSemaSwObject; - -#ifndef __NVOC_CLASS_TimedSemaSwObject_TYPEDEF__ -#define __NVOC_CLASS_TimedSemaSwObject_TYPEDEF__ -typedef struct TimedSemaSwObject TimedSemaSwObject; -#endif /* __NVOC_CLASS_TimedSemaSwObject_TYPEDEF__ */ - -#ifndef __nvoc_class_id_TimedSemaSwObject -#define __nvoc_class_id_TimedSemaSwObject 0x335775 -#endif /* __nvoc_class_id_TimedSemaSwObject */ - - struct TimerApi; #ifndef __NVOC_CLASS_TimerApi_TYPEDEF__ @@ -1112,18 +258,157 @@ typedef struct TimerApi TimerApi; #endif /* __nvoc_class_id_TimerApi */ -struct UserModeApi; +struct KernelSMDebuggerSession; -#ifndef __NVOC_CLASS_UserModeApi_TYPEDEF__ -#define __NVOC_CLASS_UserModeApi_TYPEDEF__ -typedef struct UserModeApi UserModeApi; -#endif /* __NVOC_CLASS_UserModeApi_TYPEDEF__ */ +#ifndef __NVOC_CLASS_KernelSMDebuggerSession_TYPEDEF__ +#define __NVOC_CLASS_KernelSMDebuggerSession_TYPEDEF__ +typedef struct KernelSMDebuggerSession KernelSMDebuggerSession; +#endif /* __NVOC_CLASS_KernelSMDebuggerSession_TYPEDEF__ */ -#ifndef __nvoc_class_id_UserModeApi -#define __nvoc_class_id_UserModeApi 0x6f57ec -#endif /* __nvoc_class_id_UserModeApi */ +#ifndef __nvoc_class_id_KernelSMDebuggerSession +#define __nvoc_class_id_KernelSMDebuggerSession 0x4adc81 +#endif /* __nvoc_class_id_KernelSMDebuggerSession */ + +// NVOC only expand macros inside a class. Use the stub class +#ifdef NVOC_RESOURCE_FWD_DECLS_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct RmClientResource; + +#ifndef __NVOC_CLASS_RmClientResource_TYPEDEF__ +#define __NVOC_CLASS_RmClientResource_TYPEDEF__ +typedef struct RmClientResource RmClientResource; +#endif /* __NVOC_CLASS_RmClientResource_TYPEDEF__ */ + +#ifndef __nvoc_class_id_RmClientResource +#define __nvoc_class_id_RmClientResource 0x37a701 +#endif /* __nvoc_class_id_RmClientResource */ + +struct GpuManagementApi; + +#ifndef __NVOC_CLASS_GpuManagementApi_TYPEDEF__ +#define __NVOC_CLASS_GpuManagementApi_TYPEDEF__ +typedef struct GpuManagementApi GpuManagementApi; +#endif /* __NVOC_CLASS_GpuManagementApi_TYPEDEF__ */ + +#ifndef __nvoc_class_id_GpuManagementApi +#define __nvoc_class_id_GpuManagementApi 0x376305 +#endif /* __nvoc_class_id_GpuManagementApi */ + +struct EventBuffer; + +#ifndef __NVOC_CLASS_EventBuffer_TYPEDEF__ +#define __NVOC_CLASS_EventBuffer_TYPEDEF__ +typedef struct EventBuffer EventBuffer; +#endif /* __NVOC_CLASS_EventBuffer_TYPEDEF__ */ + +#ifndef __nvoc_class_id_EventBuffer +#define __nvoc_class_id_EventBuffer 0x63502b +#endif /* __nvoc_class_id_EventBuffer */ + +struct P2PApi; + +#ifndef __NVOC_CLASS_P2PApi_TYPEDEF__ +#define __NVOC_CLASS_P2PApi_TYPEDEF__ +typedef struct P2PApi P2PApi; +#endif /* __NVOC_CLASS_P2PApi_TYPEDEF__ */ + +#ifndef __nvoc_class_id_P2PApi +#define __nvoc_class_id_P2PApi 0x3982b7 +#endif /* __nvoc_class_id_P2PApi */ + +struct SyncGpuBoost; + +#ifndef __NVOC_CLASS_SyncGpuBoost_TYPEDEF__ +#define __NVOC_CLASS_SyncGpuBoost_TYPEDEF__ +typedef struct SyncGpuBoost SyncGpuBoost; +#endif /* __NVOC_CLASS_SyncGpuBoost_TYPEDEF__ */ + +#ifndef __nvoc_class_id_SyncGpuBoost +#define __nvoc_class_id_SyncGpuBoost 0xc7e30b +#endif /* __nvoc_class_id_SyncGpuBoost */ + +struct Device; + +#ifndef __NVOC_CLASS_Device_TYPEDEF__ +#define __NVOC_CLASS_Device_TYPEDEF__ +typedef struct Device Device; +#endif /* __NVOC_CLASS_Device_TYPEDEF__ */ + +#ifndef __nvoc_class_id_Device +#define __nvoc_class_id_Device 0xe0ac20 +#endif /* __nvoc_class_id_Device */ + +struct GSyncApi; + +#ifndef __NVOC_CLASS_GSyncApi_TYPEDEF__ +#define __NVOC_CLASS_GSyncApi_TYPEDEF__ +typedef struct GSyncApi GSyncApi; +#endif /* __NVOC_CLASS_GSyncApi_TYPEDEF__ */ + +#ifndef __nvoc_class_id_GSyncApi +#define __nvoc_class_id_GSyncApi 0x214628 +#endif /* __nvoc_class_id_GSyncApi */ + +struct Profiler; + +#ifndef __NVOC_CLASS_Profiler_TYPEDEF__ +#define __NVOC_CLASS_Profiler_TYPEDEF__ +typedef struct Profiler Profiler; +#endif /* __NVOC_CLASS_Profiler_TYPEDEF__ */ + +#ifndef __nvoc_class_id_Profiler +#define __nvoc_class_id_Profiler 0x65b4c7 +#endif /* __nvoc_class_id_Profiler */ + +struct ProfilerDev; + +#ifndef __NVOC_CLASS_ProfilerDev_TYPEDEF__ +#define __NVOC_CLASS_ProfilerDev_TYPEDEF__ +typedef struct ProfilerDev ProfilerDev; +#endif /* __NVOC_CLASS_ProfilerDev_TYPEDEF__ */ + +#ifndef __nvoc_class_id_ProfilerDev +#define __nvoc_class_id_ProfilerDev 0x54d077 +#endif /* __nvoc_class_id_ProfilerDev */ + +struct PerfBuffer; + +#ifndef __NVOC_CLASS_PerfBuffer_TYPEDEF__ +#define __NVOC_CLASS_PerfBuffer_TYPEDEF__ +typedef struct PerfBuffer PerfBuffer; +#endif /* __NVOC_CLASS_PerfBuffer_TYPEDEF__ */ + +#ifndef __nvoc_class_id_PerfBuffer +#define __nvoc_class_id_PerfBuffer 0x4bc43b +#endif /* __nvoc_class_id_PerfBuffer */ + +struct Hdacodec; + +#ifndef __NVOC_CLASS_Hdacodec_TYPEDEF__ +#define __NVOC_CLASS_Hdacodec_TYPEDEF__ +typedef struct Hdacodec Hdacodec; +#endif /* __NVOC_CLASS_Hdacodec_TYPEDEF__ */ + +#ifndef __nvoc_class_id_Hdacodec +#define __nvoc_class_id_Hdacodec 0xf59a20 +#endif /* __nvoc_class_id_Hdacodec */ + +struct KernelChannel; + +#ifndef __NVOC_CLASS_KernelChannel_TYPEDEF__ +#define __NVOC_CLASS_KernelChannel_TYPEDEF__ +typedef struct KernelChannel KernelChannel; +#endif /* __NVOC_CLASS_KernelChannel_TYPEDEF__ */ + +#ifndef __nvoc_class_id_KernelChannel +#define __nvoc_class_id_KernelChannel 0x5d8d70 +#endif /* __nvoc_class_id_KernelChannel */ + struct UvmChannelRetainer; #ifndef __NVOC_CLASS_UvmChannelRetainer_TYPEDEF__ @@ -1135,66 +420,82 @@ typedef struct UvmChannelRetainer UvmChannelRetainer; #define __nvoc_class_id_UvmChannelRetainer 0xa3f03a #endif /* __nvoc_class_id_UvmChannelRetainer */ +struct KernelCtxShareApi; -struct UvmSwObject; +#ifndef __NVOC_CLASS_KernelCtxShareApi_TYPEDEF__ +#define __NVOC_CLASS_KernelCtxShareApi_TYPEDEF__ +typedef struct KernelCtxShareApi KernelCtxShareApi; +#endif /* __NVOC_CLASS_KernelCtxShareApi_TYPEDEF__ */ -#ifndef __NVOC_CLASS_UvmSwObject_TYPEDEF__ -#define __NVOC_CLASS_UvmSwObject_TYPEDEF__ -typedef struct UvmSwObject UvmSwObject; -#endif /* __NVOC_CLASS_UvmSwObject_TYPEDEF__ */ +#ifndef __nvoc_class_id_KernelCtxShareApi +#define __nvoc_class_id_KernelCtxShareApi 0x1f9af1 +#endif /* __nvoc_class_id_KernelCtxShareApi */ -#ifndef __nvoc_class_id_UvmSwObject -#define __nvoc_class_id_UvmSwObject 0xc35503 -#endif /* __nvoc_class_id_UvmSwObject */ +struct KernelGraphicsContext; +#ifndef __NVOC_CLASS_KernelGraphicsContext_TYPEDEF__ +#define __NVOC_CLASS_KernelGraphicsContext_TYPEDEF__ +typedef struct KernelGraphicsContext KernelGraphicsContext; +#endif /* __NVOC_CLASS_KernelGraphicsContext_TYPEDEF__ */ -struct VaSpaceApi; +#ifndef __nvoc_class_id_KernelGraphicsContext +#define __nvoc_class_id_KernelGraphicsContext 0x7ead09 +#endif /* __nvoc_class_id_KernelGraphicsContext */ -#ifndef __NVOC_CLASS_VaSpaceApi_TYPEDEF__ -#define __NVOC_CLASS_VaSpaceApi_TYPEDEF__ -typedef struct VaSpaceApi VaSpaceApi; -#endif /* __NVOC_CLASS_VaSpaceApi_TYPEDEF__ */ +struct Subdevice; -#ifndef __nvoc_class_id_VaSpaceApi -#define __nvoc_class_id_VaSpaceApi 0xcd048b -#endif /* __nvoc_class_id_VaSpaceApi */ +#ifndef __NVOC_CLASS_Subdevice_TYPEDEF__ +#define __NVOC_CLASS_Subdevice_TYPEDEF__ +typedef struct Subdevice Subdevice; +#endif /* __NVOC_CLASS_Subdevice_TYPEDEF__ */ +#ifndef __nvoc_class_id_Subdevice +#define __nvoc_class_id_Subdevice 0x4b01b3 +#endif /* __nvoc_class_id_Subdevice */ -struct VblankCallback; +struct BinaryApi; -#ifndef __NVOC_CLASS_VblankCallback_TYPEDEF__ -#define __NVOC_CLASS_VblankCallback_TYPEDEF__ -typedef struct VblankCallback VblankCallback; -#endif /* __NVOC_CLASS_VblankCallback_TYPEDEF__ */ +#ifndef __NVOC_CLASS_BinaryApi_TYPEDEF__ +#define __NVOC_CLASS_BinaryApi_TYPEDEF__ +typedef struct BinaryApi BinaryApi; +#endif /* __NVOC_CLASS_BinaryApi_TYPEDEF__ */ -#ifndef __nvoc_class_id_VblankCallback -#define __nvoc_class_id_VblankCallback 0x4c1997 -#endif /* __nvoc_class_id_VblankCallback */ +#ifndef __nvoc_class_id_BinaryApi +#define __nvoc_class_id_BinaryApi 0xb7a47c +#endif /* __nvoc_class_id_BinaryApi */ +struct BinaryApiPrivileged; -struct VgpuApi; +#ifndef __NVOC_CLASS_BinaryApiPrivileged_TYPEDEF__ +#define __NVOC_CLASS_BinaryApiPrivileged_TYPEDEF__ +typedef struct BinaryApiPrivileged BinaryApiPrivileged; +#endif /* __NVOC_CLASS_BinaryApiPrivileged_TYPEDEF__ */ -#ifndef __NVOC_CLASS_VgpuApi_TYPEDEF__ -#define __NVOC_CLASS_VgpuApi_TYPEDEF__ -typedef struct VgpuApi VgpuApi; -#endif /* __NVOC_CLASS_VgpuApi_TYPEDEF__ */ +#ifndef __nvoc_class_id_BinaryApiPrivileged +#define __nvoc_class_id_BinaryApiPrivileged 0x1c0579 +#endif /* __nvoc_class_id_BinaryApiPrivileged */ -#ifndef __nvoc_class_id_VgpuApi -#define __nvoc_class_id_VgpuApi 0x7774f5 -#endif /* __nvoc_class_id_VgpuApi */ +struct KernelChannelGroupApi; +#ifndef __NVOC_CLASS_KernelChannelGroupApi_TYPEDEF__ +#define __NVOC_CLASS_KernelChannelGroupApi_TYPEDEF__ +typedef struct KernelChannelGroupApi KernelChannelGroupApi; +#endif /* __NVOC_CLASS_KernelChannelGroupApi_TYPEDEF__ */ -struct VgpuConfigApi; +#ifndef __nvoc_class_id_KernelChannelGroupApi +#define __nvoc_class_id_KernelChannelGroupApi 0x2b5b80 +#endif /* __nvoc_class_id_KernelChannelGroupApi */ -#ifndef __NVOC_CLASS_VgpuConfigApi_TYPEDEF__ -#define __NVOC_CLASS_VgpuConfigApi_TYPEDEF__ -typedef struct VgpuConfigApi VgpuConfigApi; -#endif /* __NVOC_CLASS_VgpuConfigApi_TYPEDEF__ */ +struct RegisterMemory; -#ifndef __nvoc_class_id_VgpuConfigApi -#define __nvoc_class_id_VgpuConfigApi 0x4d560a -#endif /* __nvoc_class_id_VgpuConfigApi */ +#ifndef __NVOC_CLASS_RegisterMemory_TYPEDEF__ +#define __NVOC_CLASS_RegisterMemory_TYPEDEF__ +typedef struct RegisterMemory RegisterMemory; +#endif /* __NVOC_CLASS_RegisterMemory_TYPEDEF__ */ +#ifndef __nvoc_class_id_RegisterMemory +#define __nvoc_class_id_RegisterMemory 0x40d457 +#endif /* __nvoc_class_id_RegisterMemory */ struct VideoMemory; @@ -1207,6 +508,16 @@ typedef struct VideoMemory VideoMemory; #define __nvoc_class_id_VideoMemory 0xed948f #endif /* __nvoc_class_id_VideoMemory */ +struct PhysicalMemory; + +#ifndef __NVOC_CLASS_PhysicalMemory_TYPEDEF__ +#define __NVOC_CLASS_PhysicalMemory_TYPEDEF__ +typedef struct PhysicalMemory PhysicalMemory; +#endif /* __NVOC_CLASS_PhysicalMemory_TYPEDEF__ */ + +#ifndef __nvoc_class_id_PhysicalMemory +#define __nvoc_class_id_PhysicalMemory 0x5fccf2 +#endif /* __nvoc_class_id_PhysicalMemory */ struct VirtualMemory; @@ -1219,6 +530,16 @@ typedef struct VirtualMemory VirtualMemory; #define __nvoc_class_id_VirtualMemory 0x2aea5c #endif /* __nvoc_class_id_VirtualMemory */ +struct SystemMemory; + +#ifndef __NVOC_CLASS_SystemMemory_TYPEDEF__ +#define __NVOC_CLASS_SystemMemory_TYPEDEF__ +typedef struct SystemMemory SystemMemory; +#endif /* __NVOC_CLASS_SystemMemory_TYPEDEF__ */ + +#ifndef __nvoc_class_id_SystemMemory +#define __nvoc_class_id_SystemMemory 0x007a98 +#endif /* __nvoc_class_id_SystemMemory */ struct VirtualMemoryRange; @@ -1231,18 +552,181 @@ typedef struct VirtualMemoryRange VirtualMemoryRange; #define __nvoc_class_id_VirtualMemoryRange 0x7032c6 #endif /* __nvoc_class_id_VirtualMemoryRange */ +struct MemoryMapper; -struct VmmuApi; +#ifndef __NVOC_CLASS_MemoryMapper_TYPEDEF__ +#define __NVOC_CLASS_MemoryMapper_TYPEDEF__ +typedef struct MemoryMapper MemoryMapper; +#endif /* __NVOC_CLASS_MemoryMapper_TYPEDEF__ */ -#ifndef __NVOC_CLASS_VmmuApi_TYPEDEF__ -#define __NVOC_CLASS_VmmuApi_TYPEDEF__ -typedef struct VmmuApi VmmuApi; -#endif /* __NVOC_CLASS_VmmuApi_TYPEDEF__ */ +#ifndef __nvoc_class_id_MemoryMapper +#define __nvoc_class_id_MemoryMapper 0xb8e4a2 +#endif /* __nvoc_class_id_MemoryMapper */ -#ifndef __nvoc_class_id_VmmuApi -#define __nvoc_class_id_VmmuApi 0x40d73a -#endif /* __nvoc_class_id_VmmuApi */ +struct OsDescMemory; +#ifndef __NVOC_CLASS_OsDescMemory_TYPEDEF__ +#define __NVOC_CLASS_OsDescMemory_TYPEDEF__ +typedef struct OsDescMemory OsDescMemory; +#endif /* __NVOC_CLASS_OsDescMemory_TYPEDEF__ */ + +#ifndef __nvoc_class_id_OsDescMemory +#define __nvoc_class_id_OsDescMemory 0xb3dacd +#endif /* __nvoc_class_id_OsDescMemory */ + +struct NoDeviceMemory; + +#ifndef __NVOC_CLASS_NoDeviceMemory_TYPEDEF__ +#define __NVOC_CLASS_NoDeviceMemory_TYPEDEF__ +typedef struct NoDeviceMemory NoDeviceMemory; +#endif /* __NVOC_CLASS_NoDeviceMemory_TYPEDEF__ */ + +#ifndef __nvoc_class_id_NoDeviceMemory +#define __nvoc_class_id_NoDeviceMemory 0x6c0832 +#endif /* __nvoc_class_id_NoDeviceMemory */ + +struct ConsoleMemory; + +#ifndef __NVOC_CLASS_ConsoleMemory_TYPEDEF__ +#define __NVOC_CLASS_ConsoleMemory_TYPEDEF__ +typedef struct ConsoleMemory ConsoleMemory; +#endif /* __NVOC_CLASS_ConsoleMemory_TYPEDEF__ */ + +#ifndef __nvoc_class_id_ConsoleMemory +#define __nvoc_class_id_ConsoleMemory 0xaac69e +#endif /* __nvoc_class_id_ConsoleMemory */ + +struct MemoryHwResources; + +#ifndef __NVOC_CLASS_MemoryHwResources_TYPEDEF__ +#define __NVOC_CLASS_MemoryHwResources_TYPEDEF__ +typedef struct MemoryHwResources MemoryHwResources; +#endif /* __NVOC_CLASS_MemoryHwResources_TYPEDEF__ */ + +#ifndef __nvoc_class_id_MemoryHwResources +#define __nvoc_class_id_MemoryHwResources 0x9a2a71 +#endif /* __nvoc_class_id_MemoryHwResources */ + +struct MemoryList; + +#ifndef __NVOC_CLASS_MemoryList_TYPEDEF__ +#define __NVOC_CLASS_MemoryList_TYPEDEF__ +typedef struct MemoryList MemoryList; +#endif /* __NVOC_CLASS_MemoryList_TYPEDEF__ */ + +#ifndef __nvoc_class_id_MemoryList +#define __nvoc_class_id_MemoryList 0x298f78 +#endif /* __nvoc_class_id_MemoryList */ + +struct FlaMemory; + +#ifndef __NVOC_CLASS_FlaMemory_TYPEDEF__ +#define __NVOC_CLASS_FlaMemory_TYPEDEF__ +typedef struct FlaMemory FlaMemory; +#endif /* __NVOC_CLASS_FlaMemory_TYPEDEF__ */ + +#ifndef __nvoc_class_id_FlaMemory +#define __nvoc_class_id_FlaMemory 0xe61ee1 +#endif /* __nvoc_class_id_FlaMemory */ + +struct MemoryFabric; + +#ifndef __NVOC_CLASS_MemoryFabric_TYPEDEF__ +#define __NVOC_CLASS_MemoryFabric_TYPEDEF__ +typedef struct MemoryFabric MemoryFabric; +#endif /* __NVOC_CLASS_MemoryFabric_TYPEDEF__ */ + +#ifndef __nvoc_class_id_MemoryFabric +#define __nvoc_class_id_MemoryFabric 0x127499 +#endif /* __nvoc_class_id_MemoryFabric */ + +struct VaSpaceApi; + +#ifndef __NVOC_CLASS_VaSpaceApi_TYPEDEF__ +#define __NVOC_CLASS_VaSpaceApi_TYPEDEF__ +typedef struct VaSpaceApi VaSpaceApi; +#endif /* __NVOC_CLASS_VaSpaceApi_TYPEDEF__ */ + +#ifndef __nvoc_class_id_VaSpaceApi +#define __nvoc_class_id_VaSpaceApi 0xcd048b +#endif /* __nvoc_class_id_VaSpaceApi */ + +struct MemoryMulticastFabric; + +#ifndef __NVOC_CLASS_MemoryMulticastFabric_TYPEDEF__ +#define __NVOC_CLASS_MemoryMulticastFabric_TYPEDEF__ +typedef struct MemoryMulticastFabric MemoryMulticastFabric; +#endif /* __NVOC_CLASS_MemoryMulticastFabric_TYPEDEF__ */ + +#ifndef __nvoc_class_id_MemoryMulticastFabric +#define __nvoc_class_id_MemoryMulticastFabric 0x130210 +#endif /* __nvoc_class_id_MemoryMulticastFabric */ + +struct VgpuConfigApi; + +#ifndef __NVOC_CLASS_VgpuConfigApi_TYPEDEF__ +#define __NVOC_CLASS_VgpuConfigApi_TYPEDEF__ +typedef struct VgpuConfigApi VgpuConfigApi; +#endif /* __NVOC_CLASS_VgpuConfigApi_TYPEDEF__ */ + +#ifndef __nvoc_class_id_VgpuConfigApi +#define __nvoc_class_id_VgpuConfigApi 0x4d560a +#endif /* __nvoc_class_id_VgpuConfigApi */ + +struct KernelHostVgpuDeviceApi; + +#ifndef __NVOC_CLASS_KernelHostVgpuDeviceApi_TYPEDEF__ +#define __NVOC_CLASS_KernelHostVgpuDeviceApi_TYPEDEF__ +typedef struct KernelHostVgpuDeviceApi KernelHostVgpuDeviceApi; +#endif /* __NVOC_CLASS_KernelHostVgpuDeviceApi_TYPEDEF__ */ + +#ifndef __nvoc_class_id_KernelHostVgpuDeviceApi +#define __nvoc_class_id_KernelHostVgpuDeviceApi 0xb12d7d +#endif /* __nvoc_class_id_KernelHostVgpuDeviceApi */ + +struct ThirdPartyP2P; + +#ifndef __NVOC_CLASS_ThirdPartyP2P_TYPEDEF__ +#define __NVOC_CLASS_ThirdPartyP2P_TYPEDEF__ +typedef struct ThirdPartyP2P ThirdPartyP2P; +#endif /* __NVOC_CLASS_ThirdPartyP2P_TYPEDEF__ */ + +#ifndef __nvoc_class_id_ThirdPartyP2P +#define __nvoc_class_id_ThirdPartyP2P 0x34d08b +#endif /* __nvoc_class_id_ThirdPartyP2P */ + +struct GenericEngineApi; + +#ifndef __NVOC_CLASS_GenericEngineApi_TYPEDEF__ +#define __NVOC_CLASS_GenericEngineApi_TYPEDEF__ +typedef struct GenericEngineApi GenericEngineApi; +#endif /* __NVOC_CLASS_GenericEngineApi_TYPEDEF__ */ + +#ifndef __nvoc_class_id_GenericEngineApi +#define __nvoc_class_id_GenericEngineApi 0x4bc329 +#endif /* __nvoc_class_id_GenericEngineApi */ + +struct I2cApi; + +#ifndef __NVOC_CLASS_I2cApi_TYPEDEF__ +#define __NVOC_CLASS_I2cApi_TYPEDEF__ +typedef struct I2cApi I2cApi; +#endif /* __NVOC_CLASS_I2cApi_TYPEDEF__ */ + +#ifndef __nvoc_class_id_I2cApi +#define __nvoc_class_id_I2cApi 0xceb8f6 +#endif /* __nvoc_class_id_I2cApi */ + +struct DiagApi; + +#ifndef __NVOC_CLASS_DiagApi_TYPEDEF__ +#define __NVOC_CLASS_DiagApi_TYPEDEF__ +typedef struct DiagApi DiagApi; +#endif /* __NVOC_CLASS_DiagApi_TYPEDEF__ */ + +#ifndef __nvoc_class_id_DiagApi +#define __nvoc_class_id_DiagApi 0xaa3066 +#endif /* __nvoc_class_id_DiagApi */ struct ZbcApi; @@ -1255,6 +739,509 @@ typedef struct ZbcApi ZbcApi; #define __nvoc_class_id_ZbcApi 0x397ee3 #endif /* __nvoc_class_id_ZbcApi */ +struct DebugBufferApi; + +#ifndef __NVOC_CLASS_DebugBufferApi_TYPEDEF__ +#define __NVOC_CLASS_DebugBufferApi_TYPEDEF__ +typedef struct DebugBufferApi DebugBufferApi; +#endif /* __NVOC_CLASS_DebugBufferApi_TYPEDEF__ */ + +#ifndef __nvoc_class_id_DebugBufferApi +#define __nvoc_class_id_DebugBufferApi 0x5e7a1b +#endif /* __nvoc_class_id_DebugBufferApi */ + +struct GpuUserSharedData; + +#ifndef __NVOC_CLASS_GpuUserSharedData_TYPEDEF__ +#define __NVOC_CLASS_GpuUserSharedData_TYPEDEF__ +typedef struct GpuUserSharedData GpuUserSharedData; +#endif /* __NVOC_CLASS_GpuUserSharedData_TYPEDEF__ */ + +#ifndef __nvoc_class_id_GpuUserSharedData +#define __nvoc_class_id_GpuUserSharedData 0x5e7d1f +#endif /* __nvoc_class_id_GpuUserSharedData */ + +struct UserModeApi; + +#ifndef __NVOC_CLASS_UserModeApi_TYPEDEF__ +#define __NVOC_CLASS_UserModeApi_TYPEDEF__ +typedef struct UserModeApi UserModeApi; +#endif /* __NVOC_CLASS_UserModeApi_TYPEDEF__ */ + +#ifndef __nvoc_class_id_UserModeApi +#define __nvoc_class_id_UserModeApi 0x6f57ec +#endif /* __nvoc_class_id_UserModeApi */ + +struct DispSfUser; + +#ifndef __NVOC_CLASS_DispSfUser_TYPEDEF__ +#define __NVOC_CLASS_DispSfUser_TYPEDEF__ +typedef struct DispSfUser DispSfUser; +#endif /* __NVOC_CLASS_DispSfUser_TYPEDEF__ */ + +#ifndef __nvoc_class_id_DispSfUser +#define __nvoc_class_id_DispSfUser 0xba7439 +#endif /* __nvoc_class_id_DispSfUser */ + +struct MmuFaultBuffer; + +#ifndef __NVOC_CLASS_MmuFaultBuffer_TYPEDEF__ +#define __NVOC_CLASS_MmuFaultBuffer_TYPEDEF__ +typedef struct MmuFaultBuffer MmuFaultBuffer; +#endif /* __NVOC_CLASS_MmuFaultBuffer_TYPEDEF__ */ + +#ifndef __nvoc_class_id_MmuFaultBuffer +#define __nvoc_class_id_MmuFaultBuffer 0x7e1829 +#endif /* __nvoc_class_id_MmuFaultBuffer */ + +struct AccessCounterBuffer; + +#ifndef __NVOC_CLASS_AccessCounterBuffer_TYPEDEF__ +#define __NVOC_CLASS_AccessCounterBuffer_TYPEDEF__ +typedef struct AccessCounterBuffer AccessCounterBuffer; +#endif /* __NVOC_CLASS_AccessCounterBuffer_TYPEDEF__ */ + +#ifndef __nvoc_class_id_AccessCounterBuffer +#define __nvoc_class_id_AccessCounterBuffer 0x1f0074 +#endif /* __nvoc_class_id_AccessCounterBuffer */ + +struct GPUInstanceSubscription; + +#ifndef __NVOC_CLASS_GPUInstanceSubscription_TYPEDEF__ +#define __NVOC_CLASS_GPUInstanceSubscription_TYPEDEF__ +typedef struct GPUInstanceSubscription GPUInstanceSubscription; +#endif /* __NVOC_CLASS_GPUInstanceSubscription_TYPEDEF__ */ + +#ifndef __nvoc_class_id_GPUInstanceSubscription +#define __nvoc_class_id_GPUInstanceSubscription 0x91fde7 +#endif /* __nvoc_class_id_GPUInstanceSubscription */ + +struct ComputeInstanceSubscription; + +#ifndef __NVOC_CLASS_ComputeInstanceSubscription_TYPEDEF__ +#define __NVOC_CLASS_ComputeInstanceSubscription_TYPEDEF__ +typedef struct ComputeInstanceSubscription ComputeInstanceSubscription; +#endif /* __NVOC_CLASS_ComputeInstanceSubscription_TYPEDEF__ */ + +#ifndef __nvoc_class_id_ComputeInstanceSubscription +#define __nvoc_class_id_ComputeInstanceSubscription 0xd1f238 +#endif /* __nvoc_class_id_ComputeInstanceSubscription */ + +struct NvDispApi; + +#ifndef __NVOC_CLASS_NvDispApi_TYPEDEF__ +#define __NVOC_CLASS_NvDispApi_TYPEDEF__ +typedef struct NvDispApi NvDispApi; +#endif /* __NVOC_CLASS_NvDispApi_TYPEDEF__ */ + +#ifndef __nvoc_class_id_NvDispApi +#define __nvoc_class_id_NvDispApi 0x36aa0b +#endif /* __nvoc_class_id_NvDispApi */ + +struct DispSwObj; + +#ifndef __NVOC_CLASS_DispSwObj_TYPEDEF__ +#define __NVOC_CLASS_DispSwObj_TYPEDEF__ +typedef struct DispSwObj DispSwObj; +#endif /* __NVOC_CLASS_DispSwObj_TYPEDEF__ */ + +#ifndef __nvoc_class_id_DispSwObj +#define __nvoc_class_id_DispSwObj 0x6aa5e2 +#endif /* __nvoc_class_id_DispSwObj */ + +struct DispCommon; + +#ifndef __NVOC_CLASS_DispCommon_TYPEDEF__ +#define __NVOC_CLASS_DispCommon_TYPEDEF__ +typedef struct DispCommon DispCommon; +#endif /* __NVOC_CLASS_DispCommon_TYPEDEF__ */ + +#ifndef __nvoc_class_id_DispCommon +#define __nvoc_class_id_DispCommon 0x41f4f2 +#endif /* __nvoc_class_id_DispCommon */ + +struct VblankCallback; + +#ifndef __NVOC_CLASS_VblankCallback_TYPEDEF__ +#define __NVOC_CLASS_VblankCallback_TYPEDEF__ +typedef struct VblankCallback VblankCallback; +#endif /* __NVOC_CLASS_VblankCallback_TYPEDEF__ */ + +#ifndef __nvoc_class_id_VblankCallback +#define __nvoc_class_id_VblankCallback 0x4c1997 +#endif /* __nvoc_class_id_VblankCallback */ + +struct RgLineCallback; + +#ifndef __NVOC_CLASS_RgLineCallback_TYPEDEF__ +#define __NVOC_CLASS_RgLineCallback_TYPEDEF__ +typedef struct RgLineCallback RgLineCallback; +#endif /* __NVOC_CLASS_RgLineCallback_TYPEDEF__ */ + +#ifndef __nvoc_class_id_RgLineCallback +#define __nvoc_class_id_RgLineCallback 0xa3ff1c +#endif /* __nvoc_class_id_RgLineCallback */ + +struct DispChannelPio; + +#ifndef __NVOC_CLASS_DispChannelPio_TYPEDEF__ +#define __NVOC_CLASS_DispChannelPio_TYPEDEF__ +typedef struct DispChannelPio DispChannelPio; +#endif /* __NVOC_CLASS_DispChannelPio_TYPEDEF__ */ + +#ifndef __nvoc_class_id_DispChannelPio +#define __nvoc_class_id_DispChannelPio 0x10dec3 +#endif /* __nvoc_class_id_DispChannelPio */ + +struct DispChannelDma; + +#ifndef __NVOC_CLASS_DispChannelDma_TYPEDEF__ +#define __NVOC_CLASS_DispChannelDma_TYPEDEF__ +typedef struct DispChannelDma DispChannelDma; +#endif /* __NVOC_CLASS_DispChannelDma_TYPEDEF__ */ + +#ifndef __nvoc_class_id_DispChannelDma +#define __nvoc_class_id_DispChannelDma 0xfe3d2e +#endif /* __nvoc_class_id_DispChannelDma */ + +struct DispCapabilities; + +#ifndef __NVOC_CLASS_DispCapabilities_TYPEDEF__ +#define __NVOC_CLASS_DispCapabilities_TYPEDEF__ +typedef struct DispCapabilities DispCapabilities; +#endif /* __NVOC_CLASS_DispCapabilities_TYPEDEF__ */ + +#ifndef __nvoc_class_id_DispCapabilities +#define __nvoc_class_id_DispCapabilities 0x99db3e +#endif /* __nvoc_class_id_DispCapabilities */ + +struct DispSwObject; + +#ifndef __NVOC_CLASS_DispSwObject_TYPEDEF__ +#define __NVOC_CLASS_DispSwObject_TYPEDEF__ +typedef struct DispSwObject DispSwObject; +#endif /* __NVOC_CLASS_DispSwObject_TYPEDEF__ */ + +#ifndef __nvoc_class_id_DispSwObject +#define __nvoc_class_id_DispSwObject 0x99ad6d +#endif /* __nvoc_class_id_DispSwObject */ + +struct TimedSemaSwObject; + +#ifndef __NVOC_CLASS_TimedSemaSwObject_TYPEDEF__ +#define __NVOC_CLASS_TimedSemaSwObject_TYPEDEF__ +typedef struct TimedSemaSwObject TimedSemaSwObject; +#endif /* __NVOC_CLASS_TimedSemaSwObject_TYPEDEF__ */ + +#ifndef __nvoc_class_id_TimedSemaSwObject +#define __nvoc_class_id_TimedSemaSwObject 0x335775 +#endif /* __nvoc_class_id_TimedSemaSwObject */ + +struct DeferredApiObject; + +#ifndef __NVOC_CLASS_DeferredApiObject_TYPEDEF__ +#define __NVOC_CLASS_DeferredApiObject_TYPEDEF__ +typedef struct DeferredApiObject DeferredApiObject; +#endif /* __NVOC_CLASS_DeferredApiObject_TYPEDEF__ */ + +#ifndef __nvoc_class_id_DeferredApiObject +#define __nvoc_class_id_DeferredApiObject 0x8ea933 +#endif /* __nvoc_class_id_DeferredApiObject */ + +struct UvmSwObject; + +#ifndef __NVOC_CLASS_UvmSwObject_TYPEDEF__ +#define __NVOC_CLASS_UvmSwObject_TYPEDEF__ +typedef struct UvmSwObject UvmSwObject; +#endif /* __NVOC_CLASS_UvmSwObject_TYPEDEF__ */ + +#ifndef __nvoc_class_id_UvmSwObject +#define __nvoc_class_id_UvmSwObject 0xc35503 +#endif /* __nvoc_class_id_UvmSwObject */ + +struct SoftwareMethodTest; + +#ifndef __NVOC_CLASS_SoftwareMethodTest_TYPEDEF__ +#define __NVOC_CLASS_SoftwareMethodTest_TYPEDEF__ +typedef struct SoftwareMethodTest SoftwareMethodTest; +#endif /* __NVOC_CLASS_SoftwareMethodTest_TYPEDEF__ */ + +#ifndef __nvoc_class_id_SoftwareMethodTest +#define __nvoc_class_id_SoftwareMethodTest 0xdea092 +#endif /* __nvoc_class_id_SoftwareMethodTest */ + +struct KernelCeContext; + +#ifndef __NVOC_CLASS_KernelCeContext_TYPEDEF__ +#define __NVOC_CLASS_KernelCeContext_TYPEDEF__ +typedef struct KernelCeContext KernelCeContext; +#endif /* __NVOC_CLASS_KernelCeContext_TYPEDEF__ */ + +#ifndef __nvoc_class_id_KernelCeContext +#define __nvoc_class_id_KernelCeContext 0x2d0ee9 +#endif /* __nvoc_class_id_KernelCeContext */ + +struct NvdecContext; + +#ifndef __NVOC_CLASS_NvdecContext_TYPEDEF__ +#define __NVOC_CLASS_NvdecContext_TYPEDEF__ +typedef struct NvdecContext NvdecContext; +#endif /* __NVOC_CLASS_NvdecContext_TYPEDEF__ */ + +#ifndef __nvoc_class_id_NvdecContext +#define __nvoc_class_id_NvdecContext 0x70d2be +#endif /* __nvoc_class_id_NvdecContext */ + +struct NvjpgContext; + +#ifndef __NVOC_CLASS_NvjpgContext_TYPEDEF__ +#define __NVOC_CLASS_NvjpgContext_TYPEDEF__ +typedef struct NvjpgContext NvjpgContext; +#endif /* __NVOC_CLASS_NvjpgContext_TYPEDEF__ */ + +#ifndef __nvoc_class_id_NvjpgContext +#define __nvoc_class_id_NvjpgContext 0x08c1ce +#endif /* __nvoc_class_id_NvjpgContext */ + +struct OfaContext; + +#ifndef __NVOC_CLASS_OfaContext_TYPEDEF__ +#define __NVOC_CLASS_OfaContext_TYPEDEF__ +typedef struct OfaContext OfaContext; +#endif /* __NVOC_CLASS_OfaContext_TYPEDEF__ */ + +#ifndef __nvoc_class_id_OfaContext +#define __nvoc_class_id_OfaContext 0xf63d99 +#endif /* __nvoc_class_id_OfaContext */ + +struct MsencContext; + +#ifndef __NVOC_CLASS_MsencContext_TYPEDEF__ +#define __NVOC_CLASS_MsencContext_TYPEDEF__ +typedef struct MsencContext MsencContext; +#endif /* __NVOC_CLASS_MsencContext_TYPEDEF__ */ + +#ifndef __nvoc_class_id_MsencContext +#define __nvoc_class_id_MsencContext 0x88c92a +#endif /* __nvoc_class_id_MsencContext */ + +struct KernelGraphicsObject; + +#ifndef __NVOC_CLASS_KernelGraphicsObject_TYPEDEF__ +#define __NVOC_CLASS_KernelGraphicsObject_TYPEDEF__ +typedef struct KernelGraphicsObject KernelGraphicsObject; +#endif /* __NVOC_CLASS_KernelGraphicsObject_TYPEDEF__ */ + +#ifndef __nvoc_class_id_KernelGraphicsObject +#define __nvoc_class_id_KernelGraphicsObject 0x097648 +#endif /* __nvoc_class_id_KernelGraphicsObject */ + +struct ContextDma; + +#ifndef __NVOC_CLASS_ContextDma_TYPEDEF__ +#define __NVOC_CLASS_ContextDma_TYPEDEF__ +typedef struct ContextDma ContextDma; +#endif /* __NVOC_CLASS_ContextDma_TYPEDEF__ */ + +#ifndef __nvoc_class_id_ContextDma +#define __nvoc_class_id_ContextDma 0x88441b +#endif /* __nvoc_class_id_ContextDma */ + +struct Event; + +#ifndef __NVOC_CLASS_Event_TYPEDEF__ +#define __NVOC_CLASS_Event_TYPEDEF__ +typedef struct Event Event; +#endif /* __NVOC_CLASS_Event_TYPEDEF__ */ + +#ifndef __nvoc_class_id_Event +#define __nvoc_class_id_Event 0xa4ecfc +#endif /* __nvoc_class_id_Event */ + +struct KernelCcuApi; + +#ifndef __NVOC_CLASS_KernelCcuApi_TYPEDEF__ +#define __NVOC_CLASS_KernelCcuApi_TYPEDEF__ +typedef struct KernelCcuApi KernelCcuApi; +#endif /* __NVOC_CLASS_KernelCcuApi_TYPEDEF__ */ + +#ifndef __nvoc_class_id_KernelCcuApi +#define __nvoc_class_id_KernelCcuApi 0x3abed3 +#endif /* __nvoc_class_id_KernelCcuApi */ + + +struct NVOCFwdDeclHack { + const struct NVOC_RTTI *__nvoc_rtti; + struct NVOCFwdDeclHack *__nvoc_pbase_NVOCFwdDeclHack; + struct RmClientResource *PRIVATE_FIELD(RmClientResource_NV01_ROOT); + struct RmClientResource *PRIVATE_FIELD(RmClientResource_NV01_ROOT_NON_PRIV); + struct RmClientResource *PRIVATE_FIELD(RmClientResource_NV01_ROOT_CLIENT); + struct MpsApi *PRIVATE_FIELD(MpsApi_MPS_COMPUTE); + struct FmSessionApi *PRIVATE_FIELD(FmSessionApi_FABRIC_MANAGER_SESSION); + struct GpuManagementApi *PRIVATE_FIELD(GpuManagementApi_NV0020_GPU_MANAGEMENT); + struct EventBuffer *PRIVATE_FIELD(EventBuffer_NV_EVENT_BUFFER); + struct P2PApi *PRIVATE_FIELD(P2PApi_NV50_P2P); + struct SyncGpuBoost *PRIVATE_FIELD(SyncGpuBoost_NV0060_SYNC_GPU_BOOST); + struct Device *PRIVATE_FIELD(Device_NV01_DEVICE_0); + struct KernelSMDebuggerSession *PRIVATE_FIELD(KernelSMDebuggerSession_GT200_DEBUGGER); + struct GSyncApi *PRIVATE_FIELD(GSyncApi_NV30_GSYNC); + struct Profiler *PRIVATE_FIELD(Profiler_GF100_PROFILER); + struct ProfilerDev *PRIVATE_FIELD(ProfilerDev_MAXWELL_PROFILER_DEVICE); + struct PerfBuffer *PRIVATE_FIELD(PerfBuffer_G84_PERFBUFFER); + struct Hdacodec *PRIVATE_FIELD(Hdacodec_GF100_HDACODEC); + struct KernelChannel *PRIVATE_FIELD(KernelChannel_GF100_CHANNEL_GPFIFO); + struct KernelChannel *PRIVATE_FIELD(KernelChannel_KEPLER_CHANNEL_GPFIFO_A); + struct KernelChannel *PRIVATE_FIELD(KernelChannel_KEPLER_CHANNEL_GPFIFO_B); + struct KernelChannel *PRIVATE_FIELD(KernelChannel_MAXWELL_CHANNEL_GPFIFO_A); + struct KernelChannel *PRIVATE_FIELD(KernelChannel_PASCAL_CHANNEL_GPFIFO_A); + struct KernelChannel *PRIVATE_FIELD(KernelChannel_VOLTA_CHANNEL_GPFIFO_A); + struct KernelChannel *PRIVATE_FIELD(KernelChannel_TURING_CHANNEL_GPFIFO_A); + struct KernelChannel *PRIVATE_FIELD(KernelChannel_AMPERE_CHANNEL_GPFIFO_A); + struct KernelChannel *PRIVATE_FIELD(KernelChannel_HOPPER_CHANNEL_GPFIFO_A); + struct UvmChannelRetainer *PRIVATE_FIELD(UvmChannelRetainer_UVM_CHANNEL_RETAINER); + struct KernelCtxShareApi *PRIVATE_FIELD(KernelCtxShareApi_FERMI_CONTEXT_SHARE_A); + struct KernelGraphicsContext *PRIVATE_FIELD(KernelGraphicsContext_KERNEL_GRAPHICS_CONTEXT); + struct Subdevice *PRIVATE_FIELD(Subdevice_NV20_SUBDEVICE_0); + struct BinaryApi *PRIVATE_FIELD(BinaryApi_NV2081_BINAPI); + struct BinaryApiPrivileged *PRIVATE_FIELD(BinaryApiPrivileged_NV2082_BINAPI_PRIVILEGED); + struct KernelChannelGroupApi *PRIVATE_FIELD(KernelChannelGroupApi_KEPLER_CHANNEL_GROUP_A); + struct RegisterMemory *PRIVATE_FIELD(RegisterMemory_NV01_MEMORY_LOCAL_PRIVILEGED); + struct VideoMemory *PRIVATE_FIELD(VideoMemory_NV01_MEMORY_LOCAL_USER); + struct PhysicalMemory *PRIVATE_FIELD(PhysicalMemory_NV01_MEMORY_LOCAL_PHYSICAL); + struct VirtualMemory *PRIVATE_FIELD(VirtualMemory_NV50_MEMORY_VIRTUAL); + struct SystemMemory *PRIVATE_FIELD(SystemMemory_NV01_MEMORY_SYSTEM); + struct VirtualMemoryRange *PRIVATE_FIELD(VirtualMemoryRange_NV01_MEMORY_VIRTUAL); + struct MemoryMapper *PRIVATE_FIELD(MemoryMapper_NV_MEMORY_MAPPER); + struct OsDescMemory *PRIVATE_FIELD(OsDescMemory_NV01_MEMORY_SYSTEM_OS_DESCRIPTOR); + struct NoDeviceMemory *PRIVATE_FIELD(NoDeviceMemory_NV01_MEMORY_DEVICELESS); + struct ConsoleMemory *PRIVATE_FIELD(ConsoleMemory_NV01_MEMORY_FRAMEBUFFER_CONSOLE); + struct MemoryHwResources *PRIVATE_FIELD(MemoryHwResources_NV01_MEMORY_HW_RESOURCES); + struct MemoryList *PRIVATE_FIELD(MemoryList_NV01_MEMORY_LIST_SYSTEM); + struct MemoryList *PRIVATE_FIELD(MemoryList_NV01_MEMORY_LIST_FBMEM); + struct MemoryList *PRIVATE_FIELD(MemoryList_NV01_MEMORY_LIST_OBJECT); + struct FlaMemory *PRIVATE_FIELD(FlaMemory_NV01_MEMORY_FLA); + struct MemoryFabric *PRIVATE_FIELD(MemoryFabric_NV_MEMORY_FABRIC); + struct VaSpaceApi *PRIVATE_FIELD(VaSpaceApi_FERMI_VASPACE_A); + struct MemoryMulticastFabric *PRIVATE_FIELD(MemoryMulticastFabric_NV_MEMORY_MULTICAST_FABRIC); + struct VgpuConfigApi *PRIVATE_FIELD(VgpuConfigApi_NVA081_VGPU_CONFIG); + struct KernelHostVgpuDeviceApi *PRIVATE_FIELD(KernelHostVgpuDeviceApi_NVA084_KERNEL_HOST_VGPU_DEVICE); + struct ThirdPartyP2P *PRIVATE_FIELD(ThirdPartyP2P_NV50_THIRD_PARTY_P2P); + struct GenericEngineApi *PRIVATE_FIELD(GenericEngineApi_GF100_SUBDEVICE_MASTER); + struct TimerApi *PRIVATE_FIELD(TimerApi_NV01_TIMER); + struct I2cApi *PRIVATE_FIELD(I2cApi_NV40_I2C); + struct DiagApi *PRIVATE_FIELD(DiagApi_NV20_SUBDEVICE_DIAG); + struct ZbcApi *PRIVATE_FIELD(ZbcApi_GF100_ZBC_CLEAR); + struct DebugBufferApi *PRIVATE_FIELD(DebugBufferApi_NV40_DEBUG_BUFFER); + struct GpuUserSharedData *PRIVATE_FIELD(GpuUserSharedData_RM_USER_SHARED_DATA); + struct UserModeApi *PRIVATE_FIELD(UserModeApi_VOLTA_USERMODE_A); + struct UserModeApi *PRIVATE_FIELD(UserModeApi_TURING_USERMODE_A); + struct UserModeApi *PRIVATE_FIELD(UserModeApi_AMPERE_USERMODE_A); + struct UserModeApi *PRIVATE_FIELD(UserModeApi_HOPPER_USERMODE_A); + struct DispSfUser *PRIVATE_FIELD(DispSfUser_NVC371_DISP_SF_USER); + struct DispSfUser *PRIVATE_FIELD(DispSfUser_NVC671_DISP_SF_USER); + struct DispSfUser *PRIVATE_FIELD(DispSfUser_NVC771_DISP_SF_USER); + struct MmuFaultBuffer *PRIVATE_FIELD(MmuFaultBuffer_MMU_FAULT_BUFFER); + struct AccessCounterBuffer *PRIVATE_FIELD(AccessCounterBuffer_ACCESS_COUNTER_NOTIFY_BUFFER); + struct GPUInstanceSubscription *PRIVATE_FIELD(GPUInstanceSubscription_AMPERE_SMC_PARTITION_REF); + struct ComputeInstanceSubscription *PRIVATE_FIELD(ComputeInstanceSubscription_AMPERE_SMC_EXEC_PARTITION_REF); + struct MIGConfigSession *PRIVATE_FIELD(MIGConfigSession_AMPERE_SMC_CONFIG_SESSION); + struct MIGMonitorSession *PRIVATE_FIELD(MIGMonitorSession_AMPERE_SMC_MONITOR_SESSION); + struct NvDispApi *PRIVATE_FIELD(NvDispApi_NVC570_DISPLAY); + struct NvDispApi *PRIVATE_FIELD(NvDispApi_NVC670_DISPLAY); + struct NvDispApi *PRIVATE_FIELD(NvDispApi_NVC770_DISPLAY); + struct DispSwObj *PRIVATE_FIELD(DispSwObj_NVC372_DISPLAY_SW); + struct DispCommon *PRIVATE_FIELD(DispCommon_NV04_DISPLAY_COMMON); + struct VblankCallback *PRIVATE_FIELD(VblankCallback_NV9010_VBLANK_CALLBACK); + struct RgLineCallback *PRIVATE_FIELD(RgLineCallback_NV0092_RG_LINE_CALLBACK); + struct DispChannelPio *PRIVATE_FIELD(DispChannelPio_NVC57A_CURSOR_IMM_CHANNEL_PIO); + struct DispChannelPio *PRIVATE_FIELD(DispChannelPio_NVC67A_CURSOR_IMM_CHANNEL_PIO); + struct DispChannelDma *PRIVATE_FIELD(DispChannelDma_NVC57B_WINDOW_IMM_CHANNEL_DMA); + struct DispChannelDma *PRIVATE_FIELD(DispChannelDma_NVC57D_CORE_CHANNEL_DMA); + struct DispChannelDma *PRIVATE_FIELD(DispChannelDma_NVC57E_WINDOW_CHANNEL_DMA); + struct DispCapabilities *PRIVATE_FIELD(DispCapabilities_NVC573_DISP_CAPABILITIES); + struct DispChannelDma *PRIVATE_FIELD(DispChannelDma_NVC67B_WINDOW_IMM_CHANNEL_DMA); + struct DispChannelDma *PRIVATE_FIELD(DispChannelDma_NVC67D_CORE_CHANNEL_DMA); + struct DispChannelDma *PRIVATE_FIELD(DispChannelDma_NVC77D_CORE_CHANNEL_DMA); + struct DispChannelDma *PRIVATE_FIELD(DispChannelDma_NVC77F_ANY_CHANNEL_DMA); + struct DispChannelDma *PRIVATE_FIELD(DispChannelDma_NVC67E_WINDOW_CHANNEL_DMA); + struct DispCapabilities *PRIVATE_FIELD(DispCapabilities_NVC673_DISP_CAPABILITIES); + struct DispCapabilities *PRIVATE_FIELD(DispCapabilities_NVC773_DISP_CAPABILITIES); + struct DispSwObject *PRIVATE_FIELD(DispSwObject_GF100_DISP_SW); + struct TimedSemaSwObject *PRIVATE_FIELD(TimedSemaSwObject_GF100_TIMED_SEMAPHORE_SW); + struct DeferredApiObject *PRIVATE_FIELD(DeferredApiObject_NV50_DEFERRED_API_CLASS); + struct UvmSwObject *PRIVATE_FIELD(UvmSwObject_GP100_UVM_SW); + struct SoftwareMethodTest *PRIVATE_FIELD(SoftwareMethodTest_NV04_SOFTWARE_TEST); + struct KernelCeContext *PRIVATE_FIELD(KernelCeContext_MAXWELL_DMA_COPY_A); + struct KernelCeContext *PRIVATE_FIELD(KernelCeContext_PASCAL_DMA_COPY_A); + struct KernelCeContext *PRIVATE_FIELD(KernelCeContext_TURING_DMA_COPY_A); + struct KernelCeContext *PRIVATE_FIELD(KernelCeContext_AMPERE_DMA_COPY_A); + struct KernelCeContext *PRIVATE_FIELD(KernelCeContext_AMPERE_DMA_COPY_B); + struct KernelCeContext *PRIVATE_FIELD(KernelCeContext_HOPPER_DMA_COPY_A); + struct NvdecContext *PRIVATE_FIELD(NvdecContext_NVB8B0_VIDEO_DECODER); + struct NvdecContext *PRIVATE_FIELD(NvdecContext_NVC4B0_VIDEO_DECODER); + struct NvdecContext *PRIVATE_FIELD(NvdecContext_NVC6B0_VIDEO_DECODER); + struct NvdecContext *PRIVATE_FIELD(NvdecContext_NVC7B0_VIDEO_DECODER); + struct NvdecContext *PRIVATE_FIELD(NvdecContext_NVC9B0_VIDEO_DECODER); + struct NvjpgContext *PRIVATE_FIELD(NvjpgContext_NVB8D1_VIDEO_NVJPG); + struct NvjpgContext *PRIVATE_FIELD(NvjpgContext_NVC4D1_VIDEO_NVJPG); + struct NvjpgContext *PRIVATE_FIELD(NvjpgContext_NVC9D1_VIDEO_NVJPG); + struct OfaContext *PRIVATE_FIELD(OfaContext_NVB8FA_VIDEO_OFA); + struct OfaContext *PRIVATE_FIELD(OfaContext_NVC6FA_VIDEO_OFA); + struct OfaContext *PRIVATE_FIELD(OfaContext_NVC7FA_VIDEO_OFA); + struct OfaContext *PRIVATE_FIELD(OfaContext_NVC9FA_VIDEO_OFA); + struct MsencContext *PRIVATE_FIELD(MsencContext_NVC4B7_VIDEO_ENCODER); + struct MsencContext *PRIVATE_FIELD(MsencContext_NVB4B7_VIDEO_ENCODER); + struct MsencContext *PRIVATE_FIELD(MsencContext_NVC7B7_VIDEO_ENCODER); + struct MsencContext *PRIVATE_FIELD(MsencContext_NVC9B7_VIDEO_ENCODER); + struct KernelGraphicsObject *PRIVATE_FIELD(KernelGraphicsObject_AMPERE_A); + struct KernelGraphicsObject *PRIVATE_FIELD(KernelGraphicsObject_AMPERE_COMPUTE_A); + struct KernelGraphicsObject *PRIVATE_FIELD(KernelGraphicsObject_AMPERE_B); + struct KernelGraphicsObject *PRIVATE_FIELD(KernelGraphicsObject_AMPERE_COMPUTE_B); + struct KernelGraphicsObject *PRIVATE_FIELD(KernelGraphicsObject_ADA_A); + struct KernelGraphicsObject *PRIVATE_FIELD(KernelGraphicsObject_ADA_COMPUTE_A); + struct KernelGraphicsObject *PRIVATE_FIELD(KernelGraphicsObject_HOPPER_A); + struct KernelGraphicsObject *PRIVATE_FIELD(KernelGraphicsObject_HOPPER_COMPUTE_A); + struct KernelGraphicsObject *PRIVATE_FIELD(KernelGraphicsObject_FERMI_TWOD_A); + struct KernelGraphicsObject *PRIVATE_FIELD(KernelGraphicsObject_KEPLER_INLINE_TO_MEMORY_B); + struct KernelGraphicsObject *PRIVATE_FIELD(KernelGraphicsObject_TURING_A); + struct KernelGraphicsObject *PRIVATE_FIELD(KernelGraphicsObject_TURING_COMPUTE_A); + struct ContextDma *PRIVATE_FIELD(ContextDma_NV01_CONTEXT_DMA); + struct Event *PRIVATE_FIELD(Event_NV01_EVENT); + struct Event *PRIVATE_FIELD(Event_NV01_EVENT_OS_EVENT); + struct Event *PRIVATE_FIELD(Event_NV01_EVENT_KERNEL_CALLBACK); + struct Event *PRIVATE_FIELD(Event_NV01_EVENT_KERNEL_CALLBACK_EX); + struct KernelCcuApi *PRIVATE_FIELD(KernelCcuApi_NV_COUNTER_COLLECTION_UNIT); +}; + +#ifndef __NVOC_CLASS_NVOCFwdDeclHack_TYPEDEF__ +#define __NVOC_CLASS_NVOCFwdDeclHack_TYPEDEF__ +typedef struct NVOCFwdDeclHack NVOCFwdDeclHack; +#endif /* __NVOC_CLASS_NVOCFwdDeclHack_TYPEDEF__ */ + +#ifndef __nvoc_class_id_NVOCFwdDeclHack +#define __nvoc_class_id_NVOCFwdDeclHack 0x0d01f5 +#endif /* __nvoc_class_id_NVOCFwdDeclHack */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_NVOCFwdDeclHack; + +#define __staticCast_NVOCFwdDeclHack(pThis) \ + ((pThis)->__nvoc_pbase_NVOCFwdDeclHack) + +#ifdef __nvoc_resource_fwd_decls_h_disabled +#define __dynamicCast_NVOCFwdDeclHack(pThis) ((NVOCFwdDeclHack*)NULL) +#else //__nvoc_resource_fwd_decls_h_disabled +#define __dynamicCast_NVOCFwdDeclHack(pThis) \ + ((NVOCFwdDeclHack*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(NVOCFwdDeclHack))) +#endif //__nvoc_resource_fwd_decls_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_NVOCFwdDeclHack(NVOCFwdDeclHack**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_NVOCFwdDeclHack(NVOCFwdDeclHack**, Dynamic*, NvU32); +#define __objCreate_NVOCFwdDeclHack(ppNewObj, pParent, createFlags) \ + __nvoc_objCreate_NVOCFwdDeclHack((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) + +#undef PRIVATE_FIELD #endif // RESOURCE_FWD_DECLS_H diff --git a/src/nvidia/generated/g_resource_nvoc.c b/src/nvidia/generated/g_resource_nvoc.c index 9547f8d99..c9421b538 100644 --- a/src/nvidia/generated/g_resource_nvoc.c +++ b/src/nvidia/generated/g_resource_nvoc.c @@ -210,6 +210,10 @@ static NV_STATUS __nvoc_thunk_RsResource_rmresUnmapFrom(struct RmResource *pReso return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RmResource_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_rmresIsDuplicate(struct RmResource *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RmResource_RsResource.offset), hMemory, pDuplicate); +} + static NV_STATUS __nvoc_thunk_RsResource_rmresControlLookup(struct RmResource *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RmResource_RsResource.offset), pParams, ppEntry); } @@ -303,6 +307,8 @@ static void __nvoc_init_funcTable_RmResource_1(RmResource *pThis) { pThis->__rmresUnmapFrom__ = &__nvoc_thunk_RsResource_rmresUnmapFrom; + pThis->__rmresIsDuplicate__ = &__nvoc_thunk_RsResource_rmresIsDuplicate; + pThis->__rmresControlLookup__ = &__nvoc_thunk_RsResource_rmresControlLookup; pThis->__rmresMap__ = &__nvoc_thunk_RsResource_rmresMap; diff --git a/src/nvidia/generated/g_resource_nvoc.h b/src/nvidia/generated/g_resource_nvoc.h index 4760fc578..313ad8530 100644 --- a/src/nvidia/generated/g_resource_nvoc.h +++ b/src/nvidia/generated/g_resource_nvoc.h @@ -166,6 +166,7 @@ NV_STATUS __nvoc_objCreate_RmResourceCommon(RmResourceCommon**, Dynamic*, NvU32) __nvoc_objCreate_RmResourceCommon((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) NV_STATUS rmrescmnConstruct_IMPL(struct RmResourceCommon *arg_pResourceCommmon); + #define __nvoc_rmrescmnConstruct(arg_pResourceCommmon) rmrescmnConstruct_IMPL(arg_pResourceCommmon) #undef PRIVATE_FIELD @@ -203,6 +204,7 @@ struct RmResource { NvBool (*__rmresCanCopy__)(struct RmResource *); void (*__rmresPreDestruct__)(struct RmResource *); NV_STATUS (*__rmresUnmapFrom__)(struct RmResource *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__rmresIsDuplicate__)(struct RmResource *, NvHandle, NvBool *); NV_STATUS (*__rmresControlLookup__)(struct RmResource *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__rmresMap__)(struct RmResource *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvU32 rpcGpuInstance; @@ -253,6 +255,7 @@ NV_STATUS __nvoc_objCreate_RmResource(RmResource**, Dynamic*, NvU32, struct CALL #define rmresCanCopy(pResource) rmresCanCopy_DISPATCH(pResource) #define rmresPreDestruct(pResource) rmresPreDestruct_DISPATCH(pResource) #define rmresUnmapFrom(pResource, pParams) rmresUnmapFrom_DISPATCH(pResource, pParams) +#define rmresIsDuplicate(pResource, hMemory, pDuplicate) rmresIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define rmresControlLookup(pResource, pParams, ppEntry) rmresControlLookup_DISPATCH(pResource, pParams, ppEntry) #define rmresMap(pResource, pCallContext, pParams, pCpuMapping) rmresMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) NvBool rmresAccessCallback_IMPL(struct RmResource *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight); @@ -333,6 +336,10 @@ static inline NV_STATUS rmresUnmapFrom_DISPATCH(struct RmResource *pResource, RS return pResource->__rmresUnmapFrom__(pResource, pParams); } +static inline NV_STATUS rmresIsDuplicate_DISPATCH(struct RmResource *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__rmresIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline NV_STATUS rmresControlLookup_DISPATCH(struct RmResource *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { return pResource->__rmresControlLookup__(pResource, pParams, ppEntry); } @@ -342,6 +349,7 @@ static inline NV_STATUS rmresMap_DISPATCH(struct RmResource *pResource, struct C } NV_STATUS rmresConstruct_IMPL(struct RmResource *arg_pResource, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_rmresConstruct(arg_pResource, arg_pCallContext, arg_pParams) rmresConstruct_IMPL(arg_pResource, arg_pCallContext, arg_pParams) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_resserv_nvoc.h b/src/nvidia/generated/g_resserv_nvoc.h index 426eff0f3..b42276697 100644 --- a/src/nvidia/generated/g_resserv_nvoc.h +++ b/src/nvidia/generated/g_resserv_nvoc.h @@ -177,22 +177,16 @@ typedef void *PUID_TOKEN; /// Client handles must start at this base value #define RS_CLIENT_HANDLE_BASE 0xC1D00000 -/// -/// Internal Client handles must start at this base value -/// at either of these two bases -/// +/// Internal Client handles start at this base value #define RS_CLIENT_INTERNAL_HANDLE_BASE 0xC1E00000 -#define RS_CLIENT_INTERNAL_HANDLE_BASE_EX 0xC1F00000 - // // Print a warning if any client's resource count exceeds this // threshold. Unless this was intentional, this is likely a client bug. // #define RS_CLIENT_RESOURCE_WARNING_THRESHOLD 100000 - -/// 0xFFFF max client handles. +#define RS_CLIENT_HANDLE_MAX 0x100000 // Must be power of two #define RS_CLIENT_HANDLE_BUCKET_COUNT 0x400 // 1024 #define RS_CLIENT_HANDLE_BUCKET_MASK 0x3FF diff --git a/src/nvidia/generated/g_rg_line_callback_nvoc.c b/src/nvidia/generated/g_rg_line_callback_nvoc.c index 728e35be1..6adffefb8 100644 --- a/src/nvidia/generated/g_rg_line_callback_nvoc.c +++ b/src/nvidia/generated/g_rg_line_callback_nvoc.c @@ -165,6 +165,10 @@ static NV_STATUS __nvoc_thunk_RsResource_rglcbUnmapFrom(struct RgLineCallback *p return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_rglcbIsDuplicate(struct RgLineCallback *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_rglcbControl_Epilogue(struct RgLineCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RmResource.offset), pCallContext, pParams); } @@ -256,6 +260,8 @@ static void __nvoc_init_funcTable_RgLineCallback_1(RgLineCallback *pThis) { pThis->__rglcbUnmapFrom__ = &__nvoc_thunk_RsResource_rglcbUnmapFrom; + pThis->__rglcbIsDuplicate__ = &__nvoc_thunk_RsResource_rglcbIsDuplicate; + pThis->__rglcbControl_Epilogue__ = &__nvoc_thunk_RmResource_rglcbControl_Epilogue; pThis->__rglcbControlLookup__ = &__nvoc_thunk_RsResource_rglcbControlLookup; diff --git a/src/nvidia/generated/g_rg_line_callback_nvoc.h b/src/nvidia/generated/g_rg_line_callback_nvoc.h index be0745202..8aeefe52d 100644 --- a/src/nvidia/generated/g_rg_line_callback_nvoc.h +++ b/src/nvidia/generated/g_rg_line_callback_nvoc.h @@ -85,6 +85,7 @@ struct RgLineCallback { NV_STATUS (*__rglcbInternalControlForward__)(struct RgLineCallback *, NvU32, void *, NvU32); void (*__rglcbPreDestruct__)(struct RgLineCallback *); NV_STATUS (*__rglcbUnmapFrom__)(struct RgLineCallback *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__rglcbIsDuplicate__)(struct RgLineCallback *, NvHandle, NvBool *); void (*__rglcbControl_Epilogue__)(struct RgLineCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__rglcbControlLookup__)(struct RgLineCallback *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__rglcbMap__)(struct RgLineCallback *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -93,7 +94,7 @@ struct RgLineCallback { NvU32 head; NvU32 rgLineNum; NV0092_REGISTER_RG_LINE_CALLBACK_FN pCallbkFn; - void *pCallbkParams; + NvP64 pCallbkParams; NvU32 rgIntrLine; struct DispCommon *pDispCommon; }; @@ -144,6 +145,7 @@ NV_STATUS __nvoc_objCreate_RgLineCallback(RgLineCallback**, Dynamic*, NvU32, str #define rglcbInternalControlForward(pGpuResource, command, pParams, size) rglcbInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define rglcbPreDestruct(pResource) rglcbPreDestruct_DISPATCH(pResource) #define rglcbUnmapFrom(pResource, pParams) rglcbUnmapFrom_DISPATCH(pResource, pParams) +#define rglcbIsDuplicate(pResource, hMemory, pDuplicate) rglcbIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define rglcbControl_Epilogue(pResource, pCallContext, pParams) rglcbControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define rglcbControlLookup(pResource, pParams, ppEntry) rglcbControlLookup_DISPATCH(pResource, pParams, ppEntry) #define rglcbMap(pGpuResource, pCallContext, pParams, pCpuMapping) rglcbMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -220,6 +222,10 @@ static inline NV_STATUS rglcbUnmapFrom_DISPATCH(struct RgLineCallback *pResource return pResource->__rglcbUnmapFrom__(pResource, pParams); } +static inline NV_STATUS rglcbIsDuplicate_DISPATCH(struct RgLineCallback *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__rglcbIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void rglcbControl_Epilogue_DISPATCH(struct RgLineCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__rglcbControl_Epilogue__(pResource, pCallContext, pParams); } @@ -237,10 +243,13 @@ static inline NvBool rglcbAccessCallback_DISPATCH(struct RgLineCallback *pResour } NV_STATUS rglcbConstruct_IMPL(struct RgLineCallback *arg_pRgLineCallback, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_rglcbConstruct(arg_pRgLineCallback, arg_pCallContext, arg_pParams) rglcbConstruct_IMPL(arg_pRgLineCallback, arg_pCallContext, arg_pParams) void rglcbDestruct_IMPL(struct RgLineCallback *pRgLineCallback); + #define __nvoc_rglcbDestruct(pRgLineCallback) rglcbDestruct_IMPL(pRgLineCallback) void rglcbInvoke_IMPL(struct RgLineCallback *pRgLineCallback, NvBool bIsIrqlIsr); + #ifdef __nvoc_rg_line_callback_h_disabled static inline void rglcbInvoke(struct RgLineCallback *pRgLineCallback, NvBool bIsIrqlIsr) { NV_ASSERT_FAILED_PRECOMP("RgLineCallback was disabled!"); diff --git a/src/nvidia/generated/g_rmconfig_private.h b/src/nvidia/generated/g_rmconfig_private.h index 64c5df2a2..00b745ab2 100644 --- a/src/nvidia/generated/g_rmconfig_private.h +++ b/src/nvidia/generated/g_rmconfig_private.h @@ -8,7 +8,7 @@ // Profile: shipping-gpus-openrm // Template: templates/gt_rmconfig_private.h // -// Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +// Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X // #ifndef _G_RMCFG_PRIVATE_H_ @@ -268,6 +268,12 @@ #define IsAD104(pGpu) rmcfg_IsAD104(pGpu) #define IsAD104orBetter(pGpu) rmcfg_IsAD104orBetter(pGpu) +#define IsAD106(pGpu) rmcfg_IsAD106(pGpu) +#define IsAD106orBetter(pGpu) rmcfg_IsAD106orBetter(pGpu) + +#define IsAD107(pGpu) rmcfg_IsAD107(pGpu) +#define IsAD107orBetter(pGpu) rmcfg_IsAD107orBetter(pGpu) + // Any AD10X chip? #define IsAD10X(pGpu) rmcfg_IsAD10X(pGpu) #define IsAD10XorBetter(pGpu) rmcfg_IsAD10XorBetter(pGpu) diff --git a/src/nvidia/generated/g_rmconfig_util.c b/src/nvidia/generated/g_rmconfig_util.c index 4407d9342..d2df98138 100644 --- a/src/nvidia/generated/g_rmconfig_util.c +++ b/src/nvidia/generated/g_rmconfig_util.c @@ -5,7 +5,7 @@ // Profile: shipping-gpus-openrm // Template: templates/gt_rmconfig_util.c // -// Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +// Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X // #include "gpu/gpu.h" @@ -186,9 +186,29 @@ NvBool rmcfg_IsAD104orBetter(POBJGPU pGpu) return gpuIsImplementationOrBetter(pGpu, HAL_IMPL_AD104, GPU_NO_MASK_REVISION, GPU_NO_REVISION); } +NvBool rmcfg_IsAD106(POBJGPU pGpu) +{ + return gpuIsImplementation(pGpu, HAL_IMPL_AD106, GPU_NO_MASK_REVISION, GPU_NO_REVISION); +} + +NvBool rmcfg_IsAD106orBetter(POBJGPU pGpu) +{ + return gpuIsImplementationOrBetter(pGpu, HAL_IMPL_AD106, GPU_NO_MASK_REVISION, GPU_NO_REVISION); +} + +NvBool rmcfg_IsAD107(POBJGPU pGpu) +{ + return gpuIsImplementation(pGpu, HAL_IMPL_AD107, GPU_NO_MASK_REVISION, GPU_NO_REVISION); +} + +NvBool rmcfg_IsAD107orBetter(POBJGPU pGpu) +{ + return gpuIsImplementationOrBetter(pGpu, HAL_IMPL_AD107, GPU_NO_MASK_REVISION, GPU_NO_REVISION); +} + NvBool rmcfg_IsAD10X(POBJGPU pGpu) { - return IsAD102(pGpu) || IsAD103(pGpu) || IsAD104(pGpu); + return IsAD102(pGpu) || IsAD103(pGpu) || IsAD104(pGpu) || IsAD106(pGpu) || IsAD107(pGpu); } NvBool rmcfg_IsAD10XorBetter(POBJGPU pGpu) @@ -253,7 +273,7 @@ NvBool rmcfg_IsAMPERE_CLASSIC_GPUSorBetter(POBJGPU pGpu) NvBool rmcfg_IsdADA(POBJGPU pGpu) { - return IsAD102(pGpu) || IsAD103(pGpu) || IsAD104(pGpu); + return IsAD102(pGpu) || IsAD103(pGpu) || IsAD104(pGpu) || IsAD106(pGpu) || IsAD107(pGpu); } NvBool rmcfg_IsdADAorBetter(POBJGPU pGpu) @@ -263,7 +283,7 @@ NvBool rmcfg_IsdADAorBetter(POBJGPU pGpu) NvBool rmcfg_IsADA_CLASSIC_GPUS(POBJGPU pGpu) { - return IsAD102(pGpu) || IsAD103(pGpu) || IsAD104(pGpu); + return IsAD102(pGpu) || IsAD103(pGpu) || IsAD104(pGpu) || IsAD106(pGpu) || IsAD107(pGpu); } NvBool rmcfg_IsADA_CLASSIC_GPUSorBetter(POBJGPU pGpu) @@ -296,7 +316,6 @@ NvBool rmcfg_IsHOPPER_CLASSIC_GPUSorBetter(POBJGPU pGpu) // NVOC class ID uniqueness checks #ifdef DEBUG char __nvoc_class_id_uniqueness_check_0x0x05c7b5 = 1; /* OBJGPIO */ -char __nvoc_class_id_uniqueness_check_0x0xaa1d70 = 1; /* OBJOS */ char __nvoc_class_id_uniqueness_check_0x0x1ab16a = 1; /* OBJRPC */ char __nvoc_class_id_uniqueness_check_0x0xd4dff8 = 1; /* OBJRPCSTRUCTURECOPY */ diff --git a/src/nvidia/generated/g_rmconfig_util.h b/src/nvidia/generated/g_rmconfig_util.h index 599b551de..32bf11997 100644 --- a/src/nvidia/generated/g_rmconfig_util.h +++ b/src/nvidia/generated/g_rmconfig_util.h @@ -7,7 +7,7 @@ // Profile: shipping-gpus-openrm // Template: templates/gt_rmconfig_util.h // -// Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +// Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X // #ifndef _G_RMCFG_UTIL_H_ @@ -51,6 +51,10 @@ NvBool rmcfg_IsAD103(POBJGPU pGpu); NvBool rmcfg_IsAD103orBetter(POBJGPU pGpu); NvBool rmcfg_IsAD104(POBJGPU pGpu); NvBool rmcfg_IsAD104orBetter(POBJGPU pGpu); +NvBool rmcfg_IsAD106(POBJGPU pGpu); +NvBool rmcfg_IsAD106orBetter(POBJGPU pGpu); +NvBool rmcfg_IsAD107(POBJGPU pGpu); +NvBool rmcfg_IsAD107orBetter(POBJGPU pGpu); NvBool rmcfg_IsAD10X(POBJGPU pGpu); NvBool rmcfg_IsAD10XorBetter(POBJGPU pGpu); NvBool rmcfg_IsGH100(POBJGPU pGpu); diff --git a/src/nvidia/generated/g_rpc-structures.h b/src/nvidia/generated/g_rpc-structures.h index dfb60389f..e99f5c70d 100644 --- a/src/nvidia/generated/g_rpc-structures.h +++ b/src/nvidia/generated/g_rpc-structures.h @@ -176,6 +176,31 @@ typedef struct rpc_vgpu_pf_reg_read32_v15_00 typedef rpc_vgpu_pf_reg_read32_v15_00 rpc_vgpu_pf_reg_read32_v; +typedef struct rpc_ctrl_subdevice_get_p2p_caps_v21_02 +{ + NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02 ctrlParams; +} rpc_ctrl_subdevice_get_p2p_caps_v21_02; + +typedef rpc_ctrl_subdevice_get_p2p_caps_v21_02 rpc_ctrl_subdevice_get_p2p_caps_v; + +typedef struct rpc_ctrl_bus_set_p2p_mapping_v21_03 +{ + NvHandle hClient; + NvHandle hObject; + NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03 params; +} rpc_ctrl_bus_set_p2p_mapping_v21_03; + +typedef rpc_ctrl_bus_set_p2p_mapping_v21_03 rpc_ctrl_bus_set_p2p_mapping_v; + +typedef struct rpc_ctrl_bus_unset_p2p_mapping_v21_03 +{ + NvHandle hClient; + NvHandle hObject; + NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03 params; +} rpc_ctrl_bus_unset_p2p_mapping_v21_03; + +typedef rpc_ctrl_bus_unset_p2p_mapping_v21_03 rpc_ctrl_bus_unset_p2p_mapping_v; + typedef struct rpc_rmfs_init_v15_00 { NvU64 statusQueuePhysAddr NV_ALIGN_BYTES(8); @@ -221,7 +246,8 @@ typedef struct rpc_gsp_rm_control_v03_00 NvU32 status; NvU32 paramsSize; NvBool serialized; - NvU8 reserved[3]; + NvBool copyOutOnError; + NvU8 reserved[2]; NvU8 params[]; } rpc_gsp_rm_control_v03_00; @@ -379,6 +405,18 @@ typedef struct rpc_semaphore_schedule_callback_v17_00 typedef rpc_semaphore_schedule_callback_v17_00 rpc_semaphore_schedule_callback_v; +typedef struct rpc_timed_semaphore_release_v01_00 +{ + NvU64 semaphoreVA NV_ALIGN_BYTES(8); + NvU64 notifierVA NV_ALIGN_BYTES(8); + NvU32 hVASpace; + NvU32 releaseValue; + NvU32 completionStatus; + NvHandle hClient; +} rpc_timed_semaphore_release_v01_00; + +typedef rpc_timed_semaphore_release_v01_00 rpc_timed_semaphore_release_v; + typedef struct rpc_perf_gpu_boost_sync_limits_callback_v17_00 { NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v17_00 params; @@ -393,6 +431,48 @@ typedef struct rpc_perf_bridgeless_info_update_v17_00 typedef rpc_perf_bridgeless_info_update_v17_00 rpc_perf_bridgeless_info_update_v; +typedef struct rpc_nvlink_inband_received_data_256_v17_00 +{ + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v17_00 params; +} rpc_nvlink_inband_received_data_256_v17_00; + +typedef rpc_nvlink_inband_received_data_256_v17_00 rpc_nvlink_inband_received_data_256_v; + +typedef struct rpc_nvlink_inband_received_data_512_v17_00 +{ + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_512_PARAMS_v17_00 params; +} rpc_nvlink_inband_received_data_512_v17_00; + +typedef rpc_nvlink_inband_received_data_512_v17_00 rpc_nvlink_inband_received_data_512_v; + +typedef struct rpc_nvlink_inband_received_data_1024_v17_00 +{ + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_1024_PARAMS_v17_00 params; +} rpc_nvlink_inband_received_data_1024_v17_00; + +typedef rpc_nvlink_inband_received_data_1024_v17_00 rpc_nvlink_inband_received_data_1024_v; + +typedef struct rpc_nvlink_inband_received_data_2048_v17_00 +{ + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_2048_PARAMS_v17_00 params; +} rpc_nvlink_inband_received_data_2048_v17_00; + +typedef rpc_nvlink_inband_received_data_2048_v17_00 rpc_nvlink_inband_received_data_2048_v; + +typedef struct rpc_nvlink_inband_received_data_4096_v17_00 +{ + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_4096_PARAMS_v17_00 params; +} rpc_nvlink_inband_received_data_4096_v17_00; + +typedef rpc_nvlink_inband_received_data_4096_v17_00 rpc_nvlink_inband_received_data_4096_v; + +typedef struct rpc_nvlink_is_gpu_degraded_v17_00 +{ + NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v17_00 params; +} rpc_nvlink_is_gpu_degraded_v17_00; + +typedef rpc_nvlink_is_gpu_degraded_v17_00 rpc_nvlink_is_gpu_degraded_v; + typedef struct rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 { NvU32 sysmemPfnBitmapRing; @@ -402,6 +482,23 @@ typedef struct rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 typedef rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 rpc_set_sysmem_dirty_page_tracking_buffer_v; +typedef struct rpc_extdev_intr_service_v17_00 +{ + NvU8 lossRegStatus; + NvU8 gainRegStatus; + NvU8 miscRegStatus; + NvBool rmStatus; +} rpc_extdev_intr_service_v17_00; + +typedef rpc_extdev_intr_service_v17_00 rpc_extdev_intr_service_v; + +typedef struct rpc_pfm_req_hndlr_state_sync_callback_v21_04 +{ + NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04 params; +} rpc_pfm_req_hndlr_state_sync_callback_v21_04; + +typedef rpc_pfm_req_hndlr_state_sync_callback_v21_04 rpc_pfm_req_hndlr_state_sync_callback_v; + #endif @@ -921,6 +1018,83 @@ static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_vgpu_pf_reg_read32_v15_00 = { }; #endif +#ifndef SKIP_PRINT_rpc_ctrl_subdevice_get_p2p_caps_v21_02 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_subdevice_get_p2p_caps_v21_02[] = { + { + .vtype = vtype_NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02, + .offset = NV_OFFSETOF(rpc_ctrl_subdevice_get_p2p_caps_v21_02, ctrlParams), + .name = "ctrlParams" + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_subdevice_get_p2p_caps_v21_02 = { + .name = "rpc_ctrl_subdevice_get_p2p_caps", + .header_length = NV_SIZEOF32(rpc_ctrl_subdevice_get_p2p_caps_v21_02), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_subdevice_get_p2p_caps_v21_02 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_bus_set_p2p_mapping_v21_03 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_bus_set_p2p_mapping_v21_03[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_bus_set_p2p_mapping_v21_03, hClient), + .name = "hClient" + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_bus_set_p2p_mapping_v21_03, hObject), + .name = "hObject" + }, + { + .vtype = vtype_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03, + .offset = NV_OFFSETOF(rpc_ctrl_bus_set_p2p_mapping_v21_03, params), + .name = "params" + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_bus_set_p2p_mapping_v21_03 = { + .name = "rpc_ctrl_bus_set_p2p_mapping", + .header_length = NV_SIZEOF32(rpc_ctrl_bus_set_p2p_mapping_v21_03), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_bus_set_p2p_mapping_v21_03 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_bus_unset_p2p_mapping_v21_03 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_bus_unset_p2p_mapping_v21_03[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_bus_unset_p2p_mapping_v21_03, hClient), + .name = "hClient" + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_bus_unset_p2p_mapping_v21_03, hObject), + .name = "hObject" + }, + { + .vtype = vtype_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03, + .offset = NV_OFFSETOF(rpc_ctrl_bus_unset_p2p_mapping_v21_03, params), + .name = "params" + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_bus_unset_p2p_mapping_v21_03 = { + .name = "rpc_ctrl_bus_unset_p2p_mapping", + .header_length = NV_SIZEOF32(rpc_ctrl_bus_unset_p2p_mapping_v21_03), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_bus_unset_p2p_mapping_v21_03 +}; +#endif + #ifndef SKIP_PRINT_rpc_rmfs_init_v15_00 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rmfs_init_v15_00[] = { { @@ -1114,10 +1288,15 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_rm_control_v03_00[] = { .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, serialized), .name = "serialized" }, + { + .vtype = vtype_NvBool, + .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, copyOutOnError), + .name = "copyOutOnError" + }, { .vtype = vtype_NvU8_array, .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, reserved), - .array_length = 3, + .array_length = 2, .name = "reserved" }, { @@ -1650,6 +1829,50 @@ static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_semaphore_schedule_callback_v17_00 = { }; #endif +#ifndef SKIP_PRINT_rpc_timed_semaphore_release_v01_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_timed_semaphore_release_v01_00[] = { + { + .vtype = vtype_NvU64, + .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, semaphoreVA), + .name = "semaphoreVA" + }, + { + .vtype = vtype_NvU64, + .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, notifierVA), + .name = "notifierVA" + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, hVASpace), + .name = "hVASpace" + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, releaseValue), + .name = "releaseValue" + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, completionStatus), + .name = "completionStatus" + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, hClient), + .name = "hClient" + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_timed_semaphore_release_v01_00 = { + .name = "rpc_timed_semaphore_release", + .header_length = NV_SIZEOF32(rpc_timed_semaphore_release_v01_00), + .fdesc = vmiopd_fdesc_t_rpc_timed_semaphore_release_v01_00 +}; +#endif + #ifndef SKIP_PRINT_rpc_perf_gpu_boost_sync_limits_callback_v17_00 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_perf_gpu_boost_sync_limits_callback_v17_00[] = { { @@ -1688,6 +1911,120 @@ static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_perf_bridgeless_info_update_v17_00 = { }; #endif +#ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_256_v17_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_inband_received_data_256_v17_00[] = { + { + .vtype = vtype_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v17_00, + .offset = NV_OFFSETOF(rpc_nvlink_inband_received_data_256_v17_00, params), + .name = "params" + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_inband_received_data_256_v17_00 = { + .name = "rpc_nvlink_inband_received_data_256", + .header_length = NV_SIZEOF32(rpc_nvlink_inband_received_data_256_v17_00), + .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_256_v17_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_512_v17_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_inband_received_data_512_v17_00[] = { + { + .vtype = vtype_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_512_PARAMS_v17_00, + .offset = NV_OFFSETOF(rpc_nvlink_inband_received_data_512_v17_00, params), + .name = "params" + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_inband_received_data_512_v17_00 = { + .name = "rpc_nvlink_inband_received_data_512", + .header_length = NV_SIZEOF32(rpc_nvlink_inband_received_data_512_v17_00), + .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_512_v17_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_1024_v17_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_inband_received_data_1024_v17_00[] = { + { + .vtype = vtype_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_1024_PARAMS_v17_00, + .offset = NV_OFFSETOF(rpc_nvlink_inband_received_data_1024_v17_00, params), + .name = "params" + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_inband_received_data_1024_v17_00 = { + .name = "rpc_nvlink_inband_received_data_1024", + .header_length = NV_SIZEOF32(rpc_nvlink_inband_received_data_1024_v17_00), + .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_1024_v17_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_2048_v17_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_inband_received_data_2048_v17_00[] = { + { + .vtype = vtype_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_2048_PARAMS_v17_00, + .offset = NV_OFFSETOF(rpc_nvlink_inband_received_data_2048_v17_00, params), + .name = "params" + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_inband_received_data_2048_v17_00 = { + .name = "rpc_nvlink_inband_received_data_2048", + .header_length = NV_SIZEOF32(rpc_nvlink_inband_received_data_2048_v17_00), + .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_2048_v17_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_4096_v17_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_inband_received_data_4096_v17_00[] = { + { + .vtype = vtype_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_4096_PARAMS_v17_00, + .offset = NV_OFFSETOF(rpc_nvlink_inband_received_data_4096_v17_00, params), + .name = "params" + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_inband_received_data_4096_v17_00 = { + .name = "rpc_nvlink_inband_received_data_4096", + .header_length = NV_SIZEOF32(rpc_nvlink_inband_received_data_4096_v17_00), + .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_4096_v17_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_nvlink_is_gpu_degraded_v17_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_is_gpu_degraded_v17_00[] = { + { + .vtype = vtype_NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v17_00, + .offset = NV_OFFSETOF(rpc_nvlink_is_gpu_degraded_v17_00, params), + .name = "params" + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_is_gpu_degraded_v17_00 = { + .name = "rpc_nvlink_is_gpu_degraded", + .header_length = NV_SIZEOF32(rpc_nvlink_is_gpu_degraded_v17_00), + .fdesc = vmiopd_fdesc_t_rpc_nvlink_is_gpu_degraded_v17_00 +}; +#endif + #ifndef SKIP_PRINT_rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_sysmem_dirty_page_tracking_buffer_v20_00[] = { { @@ -1717,6 +2054,59 @@ static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_set_sysmem_dirty_page_tracking_buffer_v }; #endif +#ifndef SKIP_PRINT_rpc_extdev_intr_service_v17_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_extdev_intr_service_v17_00[] = { + { + .vtype = vtype_NvU8, + .offset = NV_OFFSETOF(rpc_extdev_intr_service_v17_00, lossRegStatus), + .name = "lossRegStatus" + }, + { + .vtype = vtype_NvU8, + .offset = NV_OFFSETOF(rpc_extdev_intr_service_v17_00, gainRegStatus), + .name = "gainRegStatus" + }, + { + .vtype = vtype_NvU8, + .offset = NV_OFFSETOF(rpc_extdev_intr_service_v17_00, miscRegStatus), + .name = "miscRegStatus" + }, + { + .vtype = vtype_NvBool, + .offset = NV_OFFSETOF(rpc_extdev_intr_service_v17_00, rmStatus), + .name = "rmStatus" + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_extdev_intr_service_v17_00 = { + .name = "rpc_extdev_intr_service", + .header_length = NV_SIZEOF32(rpc_extdev_intr_service_v17_00), + .fdesc = vmiopd_fdesc_t_rpc_extdev_intr_service_v17_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_pfm_req_hndlr_state_sync_callback_v21_04 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_pfm_req_hndlr_state_sync_callback_v21_04[] = { + { + .vtype = vtype_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04, + .offset = NV_OFFSETOF(rpc_pfm_req_hndlr_state_sync_callback_v21_04, params), + .name = "params" + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_pfm_req_hndlr_state_sync_callback_v21_04 = { + .name = "rpc_pfm_req_hndlr_state_sync_callback", + .header_length = NV_SIZEOF32(rpc_pfm_req_hndlr_state_sync_callback_v21_04), + .fdesc = vmiopd_fdesc_t_rpc_pfm_req_hndlr_state_sync_callback_v21_04 +}; +#endif + #endif #ifdef RPC_DEBUG_PRINT_FUNCTIONS @@ -1850,6 +2240,27 @@ vmiopd_mdesc_t *rpcdebugVgpuPfRegRead32_v15_00(void) } #endif +#ifndef SKIP_PRINT_rpc_ctrl_subdevice_get_p2p_caps_v21_02 +vmiopd_mdesc_t *rpcdebugCtrlSubdeviceGetP2pCaps_v21_02(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_subdevice_get_p2p_caps_v21_02; +} +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_bus_set_p2p_mapping_v21_03 +vmiopd_mdesc_t *rpcdebugCtrlBusSetP2pMapping_v21_03(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_bus_set_p2p_mapping_v21_03; +} +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_bus_unset_p2p_mapping_v21_03 +vmiopd_mdesc_t *rpcdebugCtrlBusUnsetP2pMapping_v21_03(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_bus_unset_p2p_mapping_v21_03; +} +#endif + #ifndef SKIP_PRINT_rpc_rmfs_init_v15_00 vmiopd_mdesc_t *rpcdebugRmfsInit_v15_00(void) { @@ -2018,6 +2429,13 @@ vmiopd_mdesc_t *rpcdebugSemaphoreScheduleCallback_v17_00(void) } #endif +#ifndef SKIP_PRINT_rpc_timed_semaphore_release_v01_00 +vmiopd_mdesc_t *rpcdebugTimedSemaphoreRelease_v01_00(void) +{ + return &vmiopd_mdesc_t_rpc_timed_semaphore_release_v01_00; +} +#endif + #ifndef SKIP_PRINT_rpc_perf_gpu_boost_sync_limits_callback_v17_00 vmiopd_mdesc_t *rpcdebugPerfGpuBoostSyncLimitsCallback_v17_00(void) { @@ -2032,6 +2450,48 @@ vmiopd_mdesc_t *rpcdebugPerfBridgelessInfoUpdate_v17_00(void) } #endif +#ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_256_v17_00 +vmiopd_mdesc_t *rpcdebugNvlinkInbandReceivedData256_v17_00(void) +{ + return &vmiopd_mdesc_t_rpc_nvlink_inband_received_data_256_v17_00; +} +#endif + +#ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_512_v17_00 +vmiopd_mdesc_t *rpcdebugNvlinkInbandReceivedData512_v17_00(void) +{ + return &vmiopd_mdesc_t_rpc_nvlink_inband_received_data_512_v17_00; +} +#endif + +#ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_1024_v17_00 +vmiopd_mdesc_t *rpcdebugNvlinkInbandReceivedData1024_v17_00(void) +{ + return &vmiopd_mdesc_t_rpc_nvlink_inband_received_data_1024_v17_00; +} +#endif + +#ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_2048_v17_00 +vmiopd_mdesc_t *rpcdebugNvlinkInbandReceivedData2048_v17_00(void) +{ + return &vmiopd_mdesc_t_rpc_nvlink_inband_received_data_2048_v17_00; +} +#endif + +#ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_4096_v17_00 +vmiopd_mdesc_t *rpcdebugNvlinkInbandReceivedData4096_v17_00(void) +{ + return &vmiopd_mdesc_t_rpc_nvlink_inband_received_data_4096_v17_00; +} +#endif + +#ifndef SKIP_PRINT_rpc_nvlink_is_gpu_degraded_v17_00 +vmiopd_mdesc_t *rpcdebugNvlinkIsGpuDegraded_v17_00(void) +{ + return &vmiopd_mdesc_t_rpc_nvlink_is_gpu_degraded_v17_00; +} +#endif + #ifndef SKIP_PRINT_rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 vmiopd_mdesc_t *rpcdebugSetSysmemDirtyPageTrackingBuffer_v20_00(void) { @@ -2039,6 +2499,20 @@ vmiopd_mdesc_t *rpcdebugSetSysmemDirtyPageTrackingBuffer_v20_00(void) } #endif +#ifndef SKIP_PRINT_rpc_extdev_intr_service_v17_00 +vmiopd_mdesc_t *rpcdebugExtdevIntrService_v17_00(void) +{ + return &vmiopd_mdesc_t_rpc_extdev_intr_service_v17_00; +} +#endif + +#ifndef SKIP_PRINT_rpc_pfm_req_hndlr_state_sync_callback_v21_04 +vmiopd_mdesc_t *rpcdebugPfmReqHndlrStateSyncCallback_v21_04(void) +{ + return &vmiopd_mdesc_t_rpc_pfm_req_hndlr_state_sync_callback_v21_04; +} +#endif + #endif @@ -2075,6 +2549,12 @@ typedef union rpc_generic_union { rpc_update_bar_pde_v update_bar_pde_v; rpc_vgpu_pf_reg_read32_v15_00 vgpu_pf_reg_read32_v15_00; rpc_vgpu_pf_reg_read32_v vgpu_pf_reg_read32_v; + rpc_ctrl_subdevice_get_p2p_caps_v21_02 ctrl_subdevice_get_p2p_caps_v21_02; + rpc_ctrl_subdevice_get_p2p_caps_v ctrl_subdevice_get_p2p_caps_v; + rpc_ctrl_bus_set_p2p_mapping_v21_03 ctrl_bus_set_p2p_mapping_v21_03; + rpc_ctrl_bus_set_p2p_mapping_v ctrl_bus_set_p2p_mapping_v; + rpc_ctrl_bus_unset_p2p_mapping_v21_03 ctrl_bus_unset_p2p_mapping_v21_03; + rpc_ctrl_bus_unset_p2p_mapping_v ctrl_bus_unset_p2p_mapping_v; rpc_rmfs_init_v15_00 rmfs_init_v15_00; rpc_rmfs_init_v rmfs_init_v; rpc_rmfs_test_v15_00 rmfs_test_v15_00; @@ -2117,12 +2597,30 @@ typedef union rpc_generic_union { rpc_init_done_v init_done_v; rpc_semaphore_schedule_callback_v17_00 semaphore_schedule_callback_v17_00; rpc_semaphore_schedule_callback_v semaphore_schedule_callback_v; + rpc_timed_semaphore_release_v01_00 timed_semaphore_release_v01_00; + rpc_timed_semaphore_release_v timed_semaphore_release_v; rpc_perf_gpu_boost_sync_limits_callback_v17_00 perf_gpu_boost_sync_limits_callback_v17_00; rpc_perf_gpu_boost_sync_limits_callback_v perf_gpu_boost_sync_limits_callback_v; rpc_perf_bridgeless_info_update_v17_00 perf_bridgeless_info_update_v17_00; rpc_perf_bridgeless_info_update_v perf_bridgeless_info_update_v; + rpc_nvlink_inband_received_data_256_v17_00 nvlink_inband_received_data_256_v17_00; + rpc_nvlink_inband_received_data_256_v nvlink_inband_received_data_256_v; + rpc_nvlink_inband_received_data_512_v17_00 nvlink_inband_received_data_512_v17_00; + rpc_nvlink_inband_received_data_512_v nvlink_inband_received_data_512_v; + rpc_nvlink_inband_received_data_1024_v17_00 nvlink_inband_received_data_1024_v17_00; + rpc_nvlink_inband_received_data_1024_v nvlink_inband_received_data_1024_v; + rpc_nvlink_inband_received_data_2048_v17_00 nvlink_inband_received_data_2048_v17_00; + rpc_nvlink_inband_received_data_2048_v nvlink_inband_received_data_2048_v; + rpc_nvlink_inband_received_data_4096_v17_00 nvlink_inband_received_data_4096_v17_00; + rpc_nvlink_inband_received_data_4096_v nvlink_inband_received_data_4096_v; + rpc_nvlink_is_gpu_degraded_v17_00 nvlink_is_gpu_degraded_v17_00; + rpc_nvlink_is_gpu_degraded_v nvlink_is_gpu_degraded_v; rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 set_sysmem_dirty_page_tracking_buffer_v20_00; rpc_set_sysmem_dirty_page_tracking_buffer_v set_sysmem_dirty_page_tracking_buffer_v; + rpc_extdev_intr_service_v17_00 extdev_intr_service_v17_00; + rpc_extdev_intr_service_v extdev_intr_service_v; + rpc_pfm_req_hndlr_state_sync_callback_v21_04 pfm_req_hndlr_state_sync_callback_v21_04; + rpc_pfm_req_hndlr_state_sync_callback_v pfm_req_hndlr_state_sync_callback_v; } rpc_generic_union; #endif diff --git a/src/nvidia/generated/g_rpc_private.h b/src/nvidia/generated/g_rpc_private.h index 47d85d346..22524a1c7 100644 --- a/src/nvidia/generated/g_rpc_private.h +++ b/src/nvidia/generated/g_rpc_private.h @@ -15,58 +15,58 @@ // RPC:VGPU_PF_REG_READ32 RpcVgpuPfRegRead32 rpcVgpuPfRegRead32_v15_00; -RpcVgpuPfRegRead32 rpcVgpuPfRegRead32_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +RpcVgpuPfRegRead32 rpcVgpuPfRegRead32_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X // RPC:DUMP_PROTOBUF_COMPONENT RpcDumpProtobufComponent rpcDumpProtobufComponent_v18_12; -RpcDumpProtobufComponent rpcDumpProtobufComponent_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +RpcDumpProtobufComponent rpcDumpProtobufComponent_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X // RPC:ALLOC_MEMORY RpcAllocMemory rpcAllocMemory_v13_01; -RpcAllocMemory rpcAllocMemory_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +RpcAllocMemory rpcAllocMemory_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X // RPC:GPU_EXEC_REG_OPS RpcGpuExecRegOps rpcGpuExecRegOps_v12_01; -RpcGpuExecRegOps rpcGpuExecRegOps_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +RpcGpuExecRegOps rpcGpuExecRegOps_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X // RPC:RMFS_INIT RpcRmfsInit rpcRmfsInit_v15_00; -RpcRmfsInit rpcRmfsInit_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +RpcRmfsInit rpcRmfsInit_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X // RPC:UNSET_PAGE_DIRECTORY RpcUnsetPageDirectory rpcUnsetPageDirectory_v03_00; RpcUnsetPageDirectory rpcUnsetPageDirectory_v1E_05; -RpcUnsetPageDirectory rpcUnsetPageDirectory_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +RpcUnsetPageDirectory rpcUnsetPageDirectory_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X // RPC:GET_GSP_STATIC_INFO RpcGetGspStaticInfo rpcGetGspStaticInfo_v14_00; -RpcGetGspStaticInfo rpcGetGspStaticInfo_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +RpcGetGspStaticInfo rpcGetGspStaticInfo_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X // RPC:GSP_SET_SYSTEM_INFO RpcGspSetSystemInfo rpcGspSetSystemInfo_v17_00; -RpcGspSetSystemInfo rpcGspSetSystemInfo_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +RpcGspSetSystemInfo rpcGspSetSystemInfo_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X // RPC:RMFS_CLEANUP RpcRmfsCleanup rpcRmfsCleanup_v15_00; -RpcRmfsCleanup rpcRmfsCleanup_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +RpcRmfsCleanup rpcRmfsCleanup_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X // RPC:SET_PAGE_DIRECTORY RpcSetPageDirectory rpcSetPageDirectory_v03_00; RpcSetPageDirectory rpcSetPageDirectory_v1E_05; -RpcSetPageDirectory rpcSetPageDirectory_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +RpcSetPageDirectory rpcSetPageDirectory_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X // RPC:UNLOADING_GUEST_DRIVER RpcUnloadingGuestDriver rpcUnloadingGuestDriver_v03_00; RpcUnloadingGuestDriver rpcUnloadingGuestDriver_v1F_07; -RpcUnloadingGuestDriver rpcUnloadingGuestDriver_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +RpcUnloadingGuestDriver rpcUnloadingGuestDriver_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X // RPC:SET_REGISTRY RpcSetRegistry rpcSetRegistry_v17_00; -RpcSetRegistry rpcSetRegistry_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +RpcSetRegistry rpcSetRegistry_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X // RPC:RMFS_CLOSE_QUEUE RpcRmfsCloseQueue rpcRmfsCloseQueue_v15_00; -RpcRmfsCloseQueue rpcRmfsCloseQueue_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +RpcRmfsCloseQueue rpcRmfsCloseQueue_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X // RPC:GET_STATIC_INFO RpcGetStaticInfo rpcGetStaticInfo_v17_05; @@ -81,28 +81,27 @@ RpcGetStaticInfo rpcGetStaticInfo_v19_00; RpcGetStaticInfo rpcGetStaticInfo_v1A_00; RpcGetStaticInfo rpcGetStaticInfo_v1A_05; RpcGetStaticInfo rpcGetStaticInfo_v20_01; -RpcGetStaticInfo rpcGetStaticInfo_v20_04; -RpcGetStaticInfo rpcGetStaticInfo_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +RpcGetStaticInfo rpcGetStaticInfo_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X // RPC:IDLE_CHANNELS RpcIdleChannels rpcIdleChannels_v03_00; -RpcIdleChannels rpcIdleChannels_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +RpcIdleChannels rpcIdleChannels_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X // RPC:UPDATE_BAR_PDE RpcUpdateBarPde rpcUpdateBarPde_v15_00; -RpcUpdateBarPde rpcUpdateBarPde_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +RpcUpdateBarPde rpcUpdateBarPde_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X // RPC:MAP_MEMORY_DMA RpcMapMemoryDma rpcMapMemoryDma_v03_00; -RpcMapMemoryDma rpcMapMemoryDma_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +RpcMapMemoryDma rpcMapMemoryDma_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X // RPC:UNMAP_MEMORY_DMA RpcUnmapMemoryDma rpcUnmapMemoryDma_v03_00; -RpcUnmapMemoryDma rpcUnmapMemoryDma_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +RpcUnmapMemoryDma rpcUnmapMemoryDma_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X // RPC:RMFS_TEST RpcRmfsTest rpcRmfsTest_v15_00; -RpcRmfsTest rpcRmfsTest_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +RpcRmfsTest rpcRmfsTest_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X @@ -2183,7 +2182,143 @@ static void rpc_iGrp_ipVersions_Install_v20_03(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v20_04(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v21_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; + RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpc_iGrp_ipVersions_Install_v21_03(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; + RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpc_iGrp_ipVersions_Install_v21_04(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; + RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpc_iGrp_ipVersions_Install_v21_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; + RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpc_iGrp_ipVersions_Install_v21_06(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; + RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpc_iGrp_ipVersions_Install_v21_07(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; + RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpc_iGrp_ipVersions_Install_v21_08(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; + RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpc_iGrp_ipVersions_Install_v21_09(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; + RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpc_iGrp_ipVersions_Install_v21_0A(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -2269,10 +2404,8 @@ static NV_STATUS rpc_iGrp_ipVersions_Wrapup(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) pRpcHal->rpcGetStaticInfo = rpcGetStaticInfo_v1A_00; if (IsIPVersionInRange(pRpc, 0x1A050000, 0x2000FFFF)) pRpcHal->rpcGetStaticInfo = rpcGetStaticInfo_v1A_05; - if (IsIPVersionInRange(pRpc, 0x20010000, 0x2003FFFF)) + if (IsIPVersionInRange(pRpc, 0x20010000, 0xFFFFFFFF)) pRpcHal->rpcGetStaticInfo = rpcGetStaticInfo_v20_01; - if (IsIPVersionInRange(pRpc, 0x20040000, 0xFFFFFFFF)) - pRpcHal->rpcGetStaticInfo = rpcGetStaticInfo_v20_04; if (IsIPVersionInRange(pRpc, 0x03000000, 0xFFFFFFFF)) pRpcHal->rpcIdleChannels = rpcIdleChannels_v03_00; if (IsIPVersionInRange(pRpc, 0x15000000, 0xFFFFFFFF)) @@ -2680,8 +2813,32 @@ static NV_STATUS rpc_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v20_03[] = { { 0x20030000, 0xFFFFFFFF, }, // }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v20_04[] = { - { 0x20040000, 0xFFFFFFFF, }, // + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v21_02[] = { + { 0x21020000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v21_03[] = { + { 0x21030000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v21_04[] = { + { 0x21040000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v21_05[] = { + { 0x21050000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v21_06[] = { + { 0x21060000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v21_07[] = { + { 0x21070000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v21_08[] = { + { 0x21080000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v21_09[] = { + { 0x21090000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v21_0A[] = { + { 0x210A0000, 0xFFFFFFFF, }, // }; #define _RPC_HAL_IGRP_ENTRY_INIT(v) \ @@ -2809,7 +2966,15 @@ static NV_STATUS rpc_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) _RPC_HAL_IGRP_ENTRY_INIT(v20_01), // _RPC_HAL_IGRP_ENTRY_INIT(v20_02), // _RPC_HAL_IGRP_ENTRY_INIT(v20_03), // - _RPC_HAL_IGRP_ENTRY_INIT(v20_04), // + _RPC_HAL_IGRP_ENTRY_INIT(v21_02), // + _RPC_HAL_IGRP_ENTRY_INIT(v21_03), // + _RPC_HAL_IGRP_ENTRY_INIT(v21_04), // + _RPC_HAL_IGRP_ENTRY_INIT(v21_05), // + _RPC_HAL_IGRP_ENTRY_INIT(v21_06), // + _RPC_HAL_IGRP_ENTRY_INIT(v21_07), // + _RPC_HAL_IGRP_ENTRY_INIT(v21_08), // + _RPC_HAL_IGRP_ENTRY_INIT(v21_09), // + _RPC_HAL_IGRP_ENTRY_INIT(v21_0A), // }; #undef _RPC_HAL_IGRP_ENTRY_INIT @@ -3037,6 +3202,24 @@ static void rpcHalIfacesSetup_AD104(RPC_HAL_IFACES *pRpcHal) #endif // AD10X or AD104 +#if defined(RMCFG_HAL_SETUP_AD106) + +static void rpcHalIfacesSetup_AD106(RPC_HAL_IFACES *pRpcHal) +{ + rpcHalIfacesSetup_AD102(pRpcHal); // AD106 interfaces identical to AD102 +} + +#endif // AD10X or AD106 + +#if defined(RMCFG_HAL_SETUP_AD107) + +static void rpcHalIfacesSetup_AD107(RPC_HAL_IFACES *pRpcHal) +{ + rpcHalIfacesSetup_AD102(pRpcHal); // AD107 interfaces identical to AD102 +} + +#endif // AD10X or AD107 + #if defined(RMCFG_HAL_SETUP_GH100) static void rpcHalIfacesSetup_GH100(RPC_HAL_IFACES *pRpcHal) diff --git a/src/nvidia/generated/g_rs_client_nvoc.c b/src/nvidia/generated/g_rs_client_nvoc.c index 7dffc9329..33eeb681d 100644 --- a/src/nvidia/generated/g_rs_client_nvoc.c +++ b/src/nvidia/generated/g_rs_client_nvoc.c @@ -98,6 +98,10 @@ static void __nvoc_init_funcTable_RsClient_1(RsClient *pThis) { pThis->__clientValidate__ = &clientValidate_IMPL; + pThis->__clientGetCachedPrivilege__ = &clientGetCachedPrivilege_IMPL; + + pThis->__clientIsAdmin__ = &clientIsAdmin_IMPL; + pThis->__clientFreeResource__ = &clientFreeResource_IMPL; pThis->__clientDestructResourceRef__ = &clientDestructResourceRef_IMPL; @@ -275,6 +279,10 @@ static NV_STATUS __nvoc_thunk_RsResource_clientresUnmapFrom(struct RsClientResou return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RsClientResource_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_clientresIsDuplicate(struct RsClientResource *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RsClientResource_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RsResource_clientresControl_Epilogue(struct RsClientResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { resControl_Epilogue((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RsClientResource_RsResource.offset), pCallContext, pParams); } @@ -352,6 +360,8 @@ static void __nvoc_init_funcTable_RsClientResource_1(RsClientResource *pThis) { pThis->__clientresUnmapFrom__ = &__nvoc_thunk_RsResource_clientresUnmapFrom; + pThis->__clientresIsDuplicate__ = &__nvoc_thunk_RsResource_clientresIsDuplicate; + pThis->__clientresControl_Epilogue__ = &__nvoc_thunk_RsResource_clientresControl_Epilogue; pThis->__clientresControlLookup__ = &__nvoc_thunk_RsResource_clientresControlLookup; diff --git a/src/nvidia/generated/g_rs_client_nvoc.h b/src/nvidia/generated/g_rs_client_nvoc.h index c5cd0925d..0607b2576 100644 --- a/src/nvidia/generated/g_rs_client_nvoc.h +++ b/src/nvidia/generated/g_rs_client_nvoc.h @@ -80,6 +80,8 @@ struct RsClient { struct Object *__nvoc_pbase_Object; struct RsClient *__nvoc_pbase_RsClient; NV_STATUS (*__clientValidate__)(struct RsClient *, const API_SECURITY_INFO *); + RS_PRIV_LEVEL (*__clientGetCachedPrivilege__)(struct RsClient *); + NvBool (*__clientIsAdmin__)(struct RsClient *, RS_PRIV_LEVEL); NV_STATUS (*__clientFreeResource__)(struct RsClient *, RsServer *, struct RS_RES_FREE_PARAMS_INTERNAL *); NV_STATUS (*__clientDestructResourceRef__)(struct RsClient *, RsServer *, struct RsResourceRef *); NV_STATUS (*__clientUnmapMemory__)(struct RsClient *, struct RsResourceRef *, struct RS_LOCK_INFO *, struct RsCpuMapping **, API_SECURITY_INFO *); @@ -131,6 +133,8 @@ NV_STATUS __nvoc_objCreate_RsClient(RsClient**, Dynamic*, NvU32, struct PORT_MEM __nvoc_objCreate_RsClient((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pAllocator, arg_pParams) #define clientValidate(pClient, pSecInfo) clientValidate_DISPATCH(pClient, pSecInfo) +#define clientGetCachedPrivilege(pClient) clientGetCachedPrivilege_DISPATCH(pClient) +#define clientIsAdmin(pClient, privLevel) clientIsAdmin_DISPATCH(pClient, privLevel) #define clientFreeResource(pClient, pServer, pParams) clientFreeResource_DISPATCH(pClient, pServer, pParams) #define clientDestructResourceRef(pClient, pServer, pResourceRef) clientDestructResourceRef_DISPATCH(pClient, pServer, pResourceRef) #define clientUnmapMemory(pClient, pResourceRef, pLockInfo, ppCpuMapping, pSecInfo) clientUnmapMemory_DISPATCH(pClient, pResourceRef, pLockInfo, ppCpuMapping, pSecInfo) @@ -145,6 +149,18 @@ static inline NV_STATUS clientValidate_DISPATCH(struct RsClient *pClient, const return pClient->__clientValidate__(pClient, pSecInfo); } +RS_PRIV_LEVEL clientGetCachedPrivilege_IMPL(struct RsClient *pClient); + +static inline RS_PRIV_LEVEL clientGetCachedPrivilege_DISPATCH(struct RsClient *pClient) { + return pClient->__clientGetCachedPrivilege__(pClient); +} + +NvBool clientIsAdmin_IMPL(struct RsClient *pClient, RS_PRIV_LEVEL privLevel); + +static inline NvBool clientIsAdmin_DISPATCH(struct RsClient *pClient, RS_PRIV_LEVEL privLevel) { + return pClient->__clientIsAdmin__(pClient, privLevel); +} + NV_STATUS clientFreeResource_IMPL(struct RsClient *pClient, RsServer *pServer, struct RS_RES_FREE_PARAMS_INTERNAL *pParams); static inline NV_STATUS clientFreeResource_DISPATCH(struct RsClient *pClient, RsServer *pServer, struct RS_RES_FREE_PARAMS_INTERNAL *pParams) { @@ -194,10 +210,13 @@ static inline NV_STATUS clientShareResource_DISPATCH(struct RsClient *pClient, s } NV_STATUS clientConstruct_IMPL(struct RsClient *arg_pClient, struct PORT_MEM_ALLOCATOR *arg_pAllocator, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_clientConstruct(arg_pClient, arg_pAllocator, arg_pParams) clientConstruct_IMPL(arg_pClient, arg_pAllocator, arg_pParams) void clientDestruct_IMPL(struct RsClient *pClient); + #define __nvoc_clientDestruct(pClient) clientDestruct_IMPL(pClient) NV_STATUS clientGetResourceByRef_IMPL(struct RsClient *pClient, struct RsResourceRef *pResourceRef, struct RsResource **ppResource); + #ifdef __nvoc_rs_client_h_disabled static inline NV_STATUS clientGetResourceByRef(struct RsClient *pClient, struct RsResourceRef *pResourceRef, struct RsResource **ppResource) { NV_ASSERT_FAILED_PRECOMP("RsClient was disabled!"); @@ -208,6 +227,7 @@ static inline NV_STATUS clientGetResourceByRef(struct RsClient *pClient, struct #endif //__nvoc_rs_client_h_disabled NV_STATUS clientGetResource_IMPL(struct RsClient *pClient, NvHandle hResource, NvU32 internalClassId, struct RsResource **ppResource); + #ifdef __nvoc_rs_client_h_disabled static inline NV_STATUS clientGetResource(struct RsClient *pClient, NvHandle hResource, NvU32 internalClassId, struct RsResource **ppResource) { NV_ASSERT_FAILED_PRECOMP("RsClient was disabled!"); @@ -218,6 +238,7 @@ static inline NV_STATUS clientGetResource(struct RsClient *pClient, NvHandle hRe #endif //__nvoc_rs_client_h_disabled NV_STATUS clientGetResourceRef_IMPL(struct RsClient *pClient, NvHandle hResource, struct RsResourceRef **ppResourceRef); + #ifdef __nvoc_rs_client_h_disabled static inline NV_STATUS clientGetResourceRef(struct RsClient *pClient, NvHandle hResource, struct RsResourceRef **ppResourceRef) { NV_ASSERT_FAILED_PRECOMP("RsClient was disabled!"); @@ -228,6 +249,7 @@ static inline NV_STATUS clientGetResourceRef(struct RsClient *pClient, NvHandle #endif //__nvoc_rs_client_h_disabled NV_STATUS clientGetResourceRefWithAccess_IMPL(struct RsClient *pClient, NvHandle hResource, const RS_ACCESS_MASK *pRightsRequired, struct RsResourceRef **ppResourceRef); + #ifdef __nvoc_rs_client_h_disabled static inline NV_STATUS clientGetResourceRefWithAccess(struct RsClient *pClient, NvHandle hResource, const RS_ACCESS_MASK *pRightsRequired, struct RsResourceRef **ppResourceRef) { NV_ASSERT_FAILED_PRECOMP("RsClient was disabled!"); @@ -238,6 +260,7 @@ static inline NV_STATUS clientGetResourceRefWithAccess(struct RsClient *pClient, #endif //__nvoc_rs_client_h_disabled NV_STATUS clientGetResourceRefByType_IMPL(struct RsClient *pClient, NvHandle hResource, NvU32 internalClassId, struct RsResourceRef **ppResourceRef); + #ifdef __nvoc_rs_client_h_disabled static inline NV_STATUS clientGetResourceRefByType(struct RsClient *pClient, NvHandle hResource, NvU32 internalClassId, struct RsResourceRef **ppResourceRef) { NV_ASSERT_FAILED_PRECOMP("RsClient was disabled!"); @@ -248,6 +271,7 @@ static inline NV_STATUS clientGetResourceRefByType(struct RsClient *pClient, NvH #endif //__nvoc_rs_client_h_disabled NV_STATUS clientAllocResource_IMPL(struct RsClient *pClient, RsServer *pServer, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); + #ifdef __nvoc_rs_client_h_disabled static inline NV_STATUS clientAllocResource(struct RsClient *pClient, RsServer *pServer, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { NV_ASSERT_FAILED_PRECOMP("RsClient was disabled!"); @@ -258,6 +282,7 @@ static inline NV_STATUS clientAllocResource(struct RsClient *pClient, RsServer * #endif //__nvoc_rs_client_h_disabled NV_STATUS clientCopyResource_IMPL(struct RsClient *pClient, RsServer *pServer, struct RS_RES_DUP_PARAMS_INTERNAL *pParams); + #ifdef __nvoc_rs_client_h_disabled static inline NV_STATUS clientCopyResource(struct RsClient *pClient, RsServer *pServer, struct RS_RES_DUP_PARAMS_INTERNAL *pParams) { NV_ASSERT_FAILED_PRECOMP("RsClient was disabled!"); @@ -268,6 +293,7 @@ static inline NV_STATUS clientCopyResource(struct RsClient *pClient, RsServer *p #endif //__nvoc_rs_client_h_disabled NV_STATUS clientGenResourceHandle_IMPL(struct RsClient *pClient, NvHandle *pHandle); + #ifdef __nvoc_rs_client_h_disabled static inline NV_STATUS clientGenResourceHandle(struct RsClient *pClient, NvHandle *pHandle) { NV_ASSERT_FAILED_PRECOMP("RsClient was disabled!"); @@ -278,6 +304,7 @@ static inline NV_STATUS clientGenResourceHandle(struct RsClient *pClient, NvHand #endif //__nvoc_rs_client_h_disabled NV_STATUS clientAssignResourceHandle_IMPL(struct RsClient *pClient, NvHandle *phResource); + #ifdef __nvoc_rs_client_h_disabled static inline NV_STATUS clientAssignResourceHandle(struct RsClient *pClient, NvHandle *phResource) { NV_ASSERT_FAILED_PRECOMP("RsClient was disabled!"); @@ -288,6 +315,7 @@ static inline NV_STATUS clientAssignResourceHandle(struct RsClient *pClient, NvH #endif //__nvoc_rs_client_h_disabled NV_STATUS clientUpdatePendingFreeList_IMPL(struct RsClient *pClient, struct RsResourceRef *pTarget, struct RsResourceRef *pReference, NvBool bMove); + #ifdef __nvoc_rs_client_h_disabled static inline NV_STATUS clientUpdatePendingFreeList(struct RsClient *pClient, struct RsResourceRef *pTarget, struct RsResourceRef *pReference, NvBool bMove) { NV_ASSERT_FAILED_PRECOMP("RsClient was disabled!"); @@ -298,6 +326,7 @@ static inline NV_STATUS clientUpdatePendingFreeList(struct RsClient *pClient, st #endif //__nvoc_rs_client_h_disabled NV_STATUS clientAddAccessBackRef_IMPL(struct RsClient *pClient, struct RsResourceRef *pResourceRef); + #ifdef __nvoc_rs_client_h_disabled static inline NV_STATUS clientAddAccessBackRef(struct RsClient *pClient, struct RsResourceRef *pResourceRef) { NV_ASSERT_FAILED_PRECOMP("RsClient was disabled!"); @@ -308,6 +337,7 @@ static inline NV_STATUS clientAddAccessBackRef(struct RsClient *pClient, struct #endif //__nvoc_rs_client_h_disabled void clientFreeAccessBackRefs_IMPL(struct RsClient *pClient, RsServer *pServer); + #ifdef __nvoc_rs_client_h_disabled static inline void clientFreeAccessBackRefs(struct RsClient *pClient, RsServer *pServer) { NV_ASSERT_FAILED_PRECOMP("RsClient was disabled!"); @@ -317,6 +347,7 @@ static inline void clientFreeAccessBackRefs(struct RsClient *pClient, RsServer * #endif //__nvoc_rs_client_h_disabled NV_STATUS clientSetHandleGenerator_IMPL(struct RsClient *pClient, NvHandle handleRangeStart, NvHandle handleRangeSize); + #ifdef __nvoc_rs_client_h_disabled static inline NV_STATUS clientSetHandleGenerator(struct RsClient *pClient, NvHandle handleRangeStart, NvHandle handleRangeSize) { NV_ASSERT_FAILED_PRECOMP("RsClient was disabled!"); @@ -327,6 +358,7 @@ static inline NV_STATUS clientSetHandleGenerator(struct RsClient *pClient, NvHan #endif //__nvoc_rs_client_h_disabled NV_STATUS clientCanShareResource_IMPL(struct RsClient *pClient, struct RsResourceRef *pResourceRef, RS_SHARE_POLICY *pSharePolicy, struct CALL_CONTEXT *pCallContext); + #ifdef __nvoc_rs_client_h_disabled static inline NV_STATUS clientCanShareResource(struct RsClient *pClient, struct RsResourceRef *pResourceRef, RS_SHARE_POLICY *pSharePolicy, struct CALL_CONTEXT *pCallContext) { NV_ASSERT_FAILED_PRECOMP("RsClient was disabled!"); @@ -337,6 +369,7 @@ static inline NV_STATUS clientCanShareResource(struct RsClient *pClient, struct #endif //__nvoc_rs_client_h_disabled NV_STATUS clientShareResourceTargetClient_IMPL(struct RsClient *pClient, struct RsResourceRef *pResourceRef, RS_SHARE_POLICY *pSharePolicy, struct CALL_CONTEXT *pCallContext); + #ifdef __nvoc_rs_client_h_disabled static inline NV_STATUS clientShareResourceTargetClient(struct RsClient *pClient, struct RsResourceRef *pResourceRef, RS_SHARE_POLICY *pSharePolicy, struct CALL_CONTEXT *pCallContext) { NV_ASSERT_FAILED_PRECOMP("RsClient was disabled!"); @@ -347,6 +380,7 @@ static inline NV_STATUS clientShareResourceTargetClient(struct RsClient *pClient #endif //__nvoc_rs_client_h_disabled NV_STATUS clientSetRestrictedRange_IMPL(struct RsClient *pClient, NvHandle handleRangeStart, NvU32 handleRangeSize); + #ifdef __nvoc_rs_client_h_disabled static inline NV_STATUS clientSetRestrictedRange(struct RsClient *pClient, NvHandle handleRangeStart, NvU32 handleRangeSize) { NV_ASSERT_FAILED_PRECOMP("RsClient was disabled!"); @@ -437,6 +471,7 @@ struct RsClientResource { NV_STATUS (*__clientresControl_Prologue__)(struct RsClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__clientresPreDestruct__)(struct RsClientResource *); NV_STATUS (*__clientresUnmapFrom__)(struct RsClientResource *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__clientresIsDuplicate__)(struct RsClientResource *, NvHandle, NvBool *); void (*__clientresControl_Epilogue__)(struct RsClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__clientresControlLookup__)(struct RsClientResource *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__clientresMap__)(struct RsClientResource *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -483,6 +518,7 @@ NV_STATUS __nvoc_objCreate_RsClientResource(RsClientResource**, Dynamic*, NvU32, #define clientresControl_Prologue(pResource, pCallContext, pParams) clientresControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define clientresPreDestruct(pResource) clientresPreDestruct_DISPATCH(pResource) #define clientresUnmapFrom(pResource, pParams) clientresUnmapFrom_DISPATCH(pResource, pParams) +#define clientresIsDuplicate(pResource, hMemory, pDuplicate) clientresIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define clientresControl_Epilogue(pResource, pCallContext, pParams) clientresControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define clientresControlLookup(pResource, pParams, ppEntry) clientresControlLookup_DISPATCH(pResource, pParams, ppEntry) #define clientresMap(pResource, pCallContext, pParams, pCpuMapping) clientresMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) @@ -531,6 +567,10 @@ static inline NV_STATUS clientresUnmapFrom_DISPATCH(struct RsClientResource *pRe return pResource->__clientresUnmapFrom__(pResource, pParams); } +static inline NV_STATUS clientresIsDuplicate_DISPATCH(struct RsClientResource *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__clientresIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void clientresControl_Epilogue_DISPATCH(struct RsClientResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__clientresControl_Epilogue__(pResource, pCallContext, pParams); } @@ -548,8 +588,10 @@ static inline NvBool clientresAccessCallback_DISPATCH(struct RsClientResource *p } NV_STATUS clientresConstruct_IMPL(struct RsClientResource *arg_pClientRes, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_clientresConstruct(arg_pClientRes, arg_pCallContext, arg_pParams) clientresConstruct_IMPL(arg_pClientRes, arg_pCallContext, arg_pParams) void clientresDestruct_IMPL(struct RsClientResource *pClientRes); + #define __nvoc_clientresDestruct(pClientRes) clientresDestruct_IMPL(pClientRes) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_rs_resource_nvoc.c b/src/nvidia/generated/g_rs_resource_nvoc.c index f57685e2c..e0951164d 100644 --- a/src/nvidia/generated/g_rs_resource_nvoc.c +++ b/src/nvidia/generated/g_rs_resource_nvoc.c @@ -98,6 +98,8 @@ static void __nvoc_init_funcTable_RsResource_1(RsResource *pThis) { pThis->__resCanCopy__ = &resCanCopy_IMPL; + pThis->__resIsDuplicate__ = &resIsDuplicate_IMPL; + pThis->__resPreDestruct__ = &resPreDestruct_IMPL; pThis->__resControlLookup__ = &resControlLookup_IMPL; diff --git a/src/nvidia/generated/g_rs_resource_nvoc.h b/src/nvidia/generated/g_rs_resource_nvoc.h index a0a00003a..fc5d58903 100644 --- a/src/nvidia/generated/g_rs_resource_nvoc.h +++ b/src/nvidia/generated/g_rs_resource_nvoc.h @@ -244,6 +244,7 @@ struct RsResource { struct Object *__nvoc_pbase_Object; struct RsResource *__nvoc_pbase_RsResource; NvBool (*__resCanCopy__)(struct RsResource *); + NV_STATUS (*__resIsDuplicate__)(struct RsResource *, NvHandle, NvBool *); void (*__resPreDestruct__)(struct RsResource *); NV_STATUS (*__resControlLookup__)(struct RsResource *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__resControl__)(struct RsResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -292,6 +293,7 @@ NV_STATUS __nvoc_objCreate_RsResource(RsResource**, Dynamic*, NvU32, struct CALL __nvoc_objCreate_RsResource((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) #define resCanCopy(pResource) resCanCopy_DISPATCH(pResource) +#define resIsDuplicate(pResource, hMemory, pDuplicate) resIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define resPreDestruct(pResource) resPreDestruct_DISPATCH(pResource) #define resControlLookup(pResource, pParams, ppEntry) resControlLookup_DISPATCH(pResource, pParams, ppEntry) #define resControl(pResource, pCallContext, pParams) resControl_DISPATCH(pResource, pCallContext, pParams) @@ -312,6 +314,12 @@ static inline NvBool resCanCopy_DISPATCH(struct RsResource *pResource) { return pResource->__resCanCopy__(pResource); } +NV_STATUS resIsDuplicate_IMPL(struct RsResource *pResource, NvHandle hMemory, NvBool *pDuplicate); + +static inline NV_STATUS resIsDuplicate_DISPATCH(struct RsResource *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__resIsDuplicate__(pResource, hMemory, pDuplicate); +} + void resPreDestruct_IMPL(struct RsResource *pResource); static inline void resPreDestruct_DISPATCH(struct RsResource *pResource) { @@ -397,10 +405,13 @@ static inline void resAddAdditionalDependants_DISPATCH(struct RsClient *pClient, } NV_STATUS resConstruct_IMPL(struct RsResource *arg_pResource, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_resConstruct(arg_pResource, arg_pCallContext, arg_pParams) resConstruct_IMPL(arg_pResource, arg_pCallContext, arg_pParams) void resDestruct_IMPL(struct RsResource *pResource); + #define __nvoc_resDestruct(pResource) resDestruct_IMPL(pResource) NV_STATUS resSetFreeParams_IMPL(struct RsResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_FREE_PARAMS_INTERNAL *pParams); + #ifdef __nvoc_rs_resource_h_disabled static inline NV_STATUS resSetFreeParams(struct RsResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_FREE_PARAMS_INTERNAL *pParams) { NV_ASSERT_FAILED_PRECOMP("RsResource was disabled!"); @@ -411,6 +422,7 @@ static inline NV_STATUS resSetFreeParams(struct RsResource *pResource, struct CA #endif //__nvoc_rs_resource_h_disabled NV_STATUS resGetFreeParams_IMPL(struct RsResource *pResource, struct CALL_CONTEXT **ppCallContext, struct RS_RES_FREE_PARAMS_INTERNAL **ppParams); + #ifdef __nvoc_rs_resource_h_disabled static inline NV_STATUS resGetFreeParams(struct RsResource *pResource, struct CALL_CONTEXT **ppCallContext, struct RS_RES_FREE_PARAMS_INTERNAL **ppParams) { NV_ASSERT_FAILED_PRECOMP("RsResource was disabled!"); diff --git a/src/nvidia/generated/g_rs_server_nvoc.h b/src/nvidia/generated/g_rs_server_nvoc.h index 47e49cd1f..28eb2ab11 100644 --- a/src/nvidia/generated/g_rs_server_nvoc.h +++ b/src/nvidia/generated/g_rs_server_nvoc.h @@ -109,8 +109,10 @@ NV_STATUS __nvoc_objCreate_RsShared(RsShared**, Dynamic*, NvU32); __nvoc_objCreate_RsShared((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) NV_STATUS shrConstruct_IMPL(struct RsShared *arg_pShared); + #define __nvoc_shrConstruct(arg_pShared) shrConstruct_IMPL(arg_pShared) void shrDestruct_IMPL(struct RsShared *pShared); + #define __nvoc_shrDestruct(pShared) shrDestruct_IMPL(pShared) #undef PRIVATE_FIELD @@ -184,10 +186,13 @@ static inline void sessionRemoveDependency_DISPATCH(struct RsSession *pSession, } NV_STATUS sessionConstruct_IMPL(struct RsSession *arg_pSession); + #define __nvoc_sessionConstruct(arg_pSession) sessionConstruct_IMPL(arg_pSession) void sessionDestruct_IMPL(struct RsSession *pSession); + #define __nvoc_sessionDestruct(pSession) sessionDestruct_IMPL(pSession) NV_STATUS sessionAddDependant_IMPL(struct RsSession *pSession, RsResourceRef *pResourceRef); + #ifdef __nvoc_rs_server_h_disabled static inline NV_STATUS sessionAddDependant(struct RsSession *pSession, RsResourceRef *pResourceRef) { NV_ASSERT_FAILED_PRECOMP("RsSession was disabled!"); @@ -198,6 +203,7 @@ static inline NV_STATUS sessionAddDependant(struct RsSession *pSession, RsResour #endif //__nvoc_rs_server_h_disabled NV_STATUS sessionAddDependency_IMPL(struct RsSession *pSession, RsResourceRef *pResourceRef); + #ifdef __nvoc_rs_server_h_disabled static inline NV_STATUS sessionAddDependency(struct RsSession *pSession, RsResourceRef *pResourceRef) { NV_ASSERT_FAILED_PRECOMP("RsSession was disabled!"); @@ -208,6 +214,7 @@ static inline NV_STATUS sessionAddDependency(struct RsSession *pSession, RsResou #endif //__nvoc_rs_server_h_disabled NV_STATUS sessionCheckLocksForAdd_IMPL(struct RsSession *pSession, RsResourceRef *pResourceRef); + #ifdef __nvoc_rs_server_h_disabled static inline NV_STATUS sessionCheckLocksForAdd(struct RsSession *pSession, RsResourceRef *pResourceRef) { NV_ASSERT_FAILED_PRECOMP("RsSession was disabled!"); @@ -218,6 +225,7 @@ static inline NV_STATUS sessionCheckLocksForAdd(struct RsSession *pSession, RsRe #endif //__nvoc_rs_server_h_disabled void sessionCheckLocksForRemove_IMPL(struct RsSession *pSession, RsResourceRef *pResourceRef); + #ifdef __nvoc_rs_server_h_disabled static inline void sessionCheckLocksForRemove(struct RsSession *pSession, RsResourceRef *pResourceRef) { NV_ASSERT_FAILED_PRECOMP("RsSession was disabled!"); @@ -284,6 +292,10 @@ struct RsServer /// If true, control call param copies will be performed outside the top/api lock NvBool bUnlockedParamCopy; + // If true, calls annotated with ROUTE_TO_PHYISCAL will not grab global gpu locks + // (and the readonly API lock). + NvBool bRouteToPhysicalLockBypass; + /** * Setting this flag to false disables any attempts to * automatically acquire access rights or to control access to resources by @@ -302,6 +314,7 @@ struct RsServer RsShareList globalInternalSharePolicyList; NvU32 internalHandleBase; + NvU32 clientHandleBase; NvU32 activeClientCount; NvU64 activeResourceCount; @@ -469,6 +482,14 @@ RS_SHARE_ITERATOR serverShareIter(RsServer *pServer, NvU32 internalClassId); */ NvBool serverShareIterNext(RS_SHARE_ITERATOR*); +/** + * Set fixed client handle base in case clients wants to use a different + * base for client allocations + * @param[in] pServer + * @param[in] clientHandleBase + */ + NV_STATUS serverSetClientHandleBase(RsServer *pServer, NvU32 clientHandleBase); + /** * Allocate a resource. Assumes top-level lock has been taken. diff --git a/src/nvidia/generated/g_sdk-structures.h b/src/nvidia/generated/g_sdk-structures.h index 6f022d8bb..483c09b3c 100644 --- a/src/nvidia/generated/g_sdk-structures.h +++ b/src/nvidia/generated/g_sdk-structures.h @@ -30,6 +30,7 @@ #ifdef SDK_STRUCTURES // These are copy of sdk structures, that will be used for the communication between the vmioplugin & guest RM. +// #if condition can be removed when this file is included in OpenRM-Orin build. #include "vgpu/sdk-structures.h" typedef struct NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v03_00 { @@ -254,6 +255,54 @@ typedef struct UpdateBarPde_v15_00 typedef UpdateBarPde_v15_00 UpdateBarPde_v; +typedef struct NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v17_00 +{ + NvU32 dataSize; + NvU8 data[256]; +} NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v17_00; + +typedef NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v17_00 NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v; + +typedef struct NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_512_PARAMS_v17_00 +{ + NvU32 dataSize; + NvU8 data[512]; +} NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_512_PARAMS_v17_00; + +typedef NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_512_PARAMS_v17_00 NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_512_PARAMS_v; + +typedef struct NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_1024_PARAMS_v17_00 +{ + NvU32 dataSize; + NvU8 data[1024]; +} NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_1024_PARAMS_v17_00; + +typedef NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_1024_PARAMS_v17_00 NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_1024_PARAMS_v; + +typedef struct NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_2048_PARAMS_v17_00 +{ + NvU32 dataSize; + NvU8 data[2048]; +} NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_2048_PARAMS_v17_00; + +typedef NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_2048_PARAMS_v17_00 NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_2048_PARAMS_v; + +typedef struct NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_4096_PARAMS_v17_00 +{ + NvU32 dataSize; + NvU8 data[4096]; +} NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_4096_PARAMS_v17_00; + +typedef NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_4096_PARAMS_v17_00 NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_4096_PARAMS_v; + +typedef struct NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v17_00 +{ + NvU32 linkId; + NvBool bIsGpuDegraded; +} NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v17_00; + +typedef NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v17_00 NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v; + typedef struct gpu_exec_reg_ops_v03_00 { NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v03_00 reg_op_params; @@ -310,14 +359,175 @@ typedef struct ATOMIC_OP_v1F_08 typedef ATOMIC_OP_v1F_08 ATOMIC_OP_v; +typedef struct NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v21_02 +{ + NvU32 gpuId; + NvU8 gpuUuid[VM_UUID_SIZE_v21_02]; + NvU32 p2pCaps; + NvU32 p2pOptimalReadCEs; + NvU32 p2pOptimalWriteCEs; + NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v1F_0D]; + NvU32 busPeerId; +} NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v21_02; + +typedef NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v21_02 NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v; + +typedef struct NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02 +{ + NvBool bAllCaps; + NvBool bUseUuid; + NvU32 peerGpuCount; + NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v21_02 peerGpuCaps[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_v21_02]; +} NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02; + +typedef NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02 NV2080_CTRL_GET_P2P_CAPS_PARAMS_v; + +typedef struct NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03 +{ + NvU32 connectionType; + NvU32 peerId; + NvU32 bSpaAccessOnly; + NvBool bUseUuid; + NvU32 remoteGpuId; + NvU8 remoteGpuUuid[VM_UUID_SIZE_v21_02]; +} NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03; + +typedef NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03 NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v; + +typedef struct NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03 +{ + NvU32 connectionType; + NvU32 peerId; + NvBool bUseUuid; + NvU32 remoteGpuId; + NvU8 remoteGpuUuid[VM_UUID_SIZE_v21_02]; +} NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03; + +typedef NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03 NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v; + +typedef struct NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08 +{ + NvU8 chipletType; + NvU8 chipletIndex; + NvU8 numCredits; +} NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08; + +typedef NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08 NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v; + +typedef struct NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08 +{ + NvU8 status; + NvU8 entryIndex; +} NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08; + +typedef NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08 NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v; + +typedef struct NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08 +{ + NvU32 numCredits; +} NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08; + +typedef NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08 NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v; + +typedef struct NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08 +{ + NvU8 pmaChannelIdx; + NvU8 numEntries; + NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08 statusInfo; + NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08 creditInfo[NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08]; +} NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08; + +typedef NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08 NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v; + +typedef struct NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08 +{ + NvU8 pmaChannelIdx; + NvU8 numEntries; + NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08 statusInfo; + NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08 creditInfo[NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08]; +} NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08; + +typedef NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08 NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v; + +typedef struct NV2080_CTRL_CE_CAPS_v21_0A +{ + NvU8 capsTbl[NV2080_CTRL_CE_CAPS_TBL_SIZE_v21_0A]; +} NV2080_CTRL_CE_CAPS_v21_0A; + +typedef NV2080_CTRL_CE_CAPS_v21_0A NV2080_CTRL_CE_CAPS_v; + +typedef struct NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_v21_0A +{ + NV2080_CTRL_CE_CAPS_v21_0A ceCaps[NV2080_CTRL_MAX_PCES_v21_0A]; + NvU32 present; +} NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_v21_0A; + +typedef NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_v21_0A NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_v; + +typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI_v21_04 +{ + NvU32 sensorId; + NvU32 limit; +} NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI_v21_04; + +typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI_v21_04 NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI_v; + +typedef union NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04 +{ + NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI_v21_04 smbpbi; +} NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04; + +typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04 NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v; + +typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04 +{ + NvU8 type ; + NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04 data; +} NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04; + +typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04 NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v; + +typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04 +{ + NvU8 flags; + NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04 syncData; +} NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04; + +typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04 NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v; + #endif #ifdef SDK_UNION_MEMBER_NAME_FUNCTIONS +// Union member name functions for NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type +static char* _get_union_member_name_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type(NvU32 cmd) +{ + switch (cmd) + { + case NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_TYPE_SMBPBI: + return "smbpbi"; + + default: + return UNION_UNKNOWN_FIELD_PRINT; + } +} + +#define _get_union_member_name_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04(cmd) _get_union_member_name_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type(cmd) + #endif #ifdef SDK_UNION_MEMBER_NAME_FUNCTIONS_CMD +static NV_STATUS get_union_member_name_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04_data(void *msg, NvS32 bytes_remaining, char** name) +{ + NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04 *param = msg; + + if ((NvS32)(NV_OFFSETOF(NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04, type) + sizeof(param->type)) > bytes_remaining) + return NV_ERR_BUFFER_TOO_SMALL; + + *name = _get_union_member_name_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04(param->type); + return NV_OK; +} #endif diff --git a/src/nvidia/generated/g_standard_mem_nvoc.c b/src/nvidia/generated/g_standard_mem_nvoc.c index 9a64a73df..f72c41d16 100644 --- a/src/nvidia/generated/g_standard_mem_nvoc.c +++ b/src/nvidia/generated/g_standard_mem_nvoc.c @@ -145,8 +145,12 @@ static NV_STATUS __nvoc_thunk_RmResource_stdmemControl_Prologue(struct StandardM return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_Memory_stdmemIsReady(struct StandardMemory *pMemory) { - return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset)); +static NvBool __nvoc_thunk_Memory_stdmemIsGpuMapAllowed(struct StandardMemory *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), pGpu); +} + +static NV_STATUS __nvoc_thunk_Memory_stdmemIsReady(struct StandardMemory *pMemory, NvBool bCopyConstructorContext) { + return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), bCopyConstructorContext); } static NV_STATUS __nvoc_thunk_Memory_stdmemCheckCopyPermissions(struct StandardMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { @@ -157,6 +161,10 @@ static void __nvoc_thunk_RsResource_stdmemPreDestruct(struct StandardMemory *pRe resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_Memory_stdmemIsDuplicate(struct StandardMemory *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), hMemory, pDuplicate); +} + static NV_STATUS __nvoc_thunk_RsResource_stdmemUnmapFrom(struct StandardMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RsResource.offset), pParams); } @@ -243,12 +251,16 @@ static void __nvoc_init_funcTable_StandardMemory_1(StandardMemory *pThis) { pThis->__stdmemControl_Prologue__ = &__nvoc_thunk_RmResource_stdmemControl_Prologue; + pThis->__stdmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_stdmemIsGpuMapAllowed; + pThis->__stdmemIsReady__ = &__nvoc_thunk_Memory_stdmemIsReady; pThis->__stdmemCheckCopyPermissions__ = &__nvoc_thunk_Memory_stdmemCheckCopyPermissions; pThis->__stdmemPreDestruct__ = &__nvoc_thunk_RsResource_stdmemPreDestruct; + pThis->__stdmemIsDuplicate__ = &__nvoc_thunk_Memory_stdmemIsDuplicate; + pThis->__stdmemUnmapFrom__ = &__nvoc_thunk_RsResource_stdmemUnmapFrom; pThis->__stdmemControl_Epilogue__ = &__nvoc_thunk_RmResource_stdmemControl_Epilogue; diff --git a/src/nvidia/generated/g_standard_mem_nvoc.h b/src/nvidia/generated/g_standard_mem_nvoc.h index bb1573e05..f85ce18a7 100644 --- a/src/nvidia/generated/g_standard_mem_nvoc.h +++ b/src/nvidia/generated/g_standard_mem_nvoc.h @@ -82,9 +82,11 @@ struct StandardMemory { NvU32 (*__stdmemGetRefCount__)(struct StandardMemory *); NV_STATUS (*__stdmemMapTo__)(struct StandardMemory *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__stdmemControl_Prologue__)(struct StandardMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__stdmemIsReady__)(struct StandardMemory *); + NvBool (*__stdmemIsGpuMapAllowed__)(struct StandardMemory *, struct OBJGPU *); + NV_STATUS (*__stdmemIsReady__)(struct StandardMemory *, NvBool); NV_STATUS (*__stdmemCheckCopyPermissions__)(struct StandardMemory *, struct OBJGPU *, NvHandle); void (*__stdmemPreDestruct__)(struct StandardMemory *); + NV_STATUS (*__stdmemIsDuplicate__)(struct StandardMemory *, NvHandle, NvBool *); NV_STATUS (*__stdmemUnmapFrom__)(struct StandardMemory *, RS_RES_UNMAP_FROM_PARAMS *); void (*__stdmemControl_Epilogue__)(struct StandardMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__stdmemControlLookup__)(struct StandardMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); @@ -133,9 +135,11 @@ NV_STATUS __nvoc_objCreate_StandardMemory(StandardMemory**, Dynamic*, NvU32, CAL #define stdmemGetRefCount(pResource) stdmemGetRefCount_DISPATCH(pResource) #define stdmemMapTo(pResource, pParams) stdmemMapTo_DISPATCH(pResource, pParams) #define stdmemControl_Prologue(pResource, pCallContext, pParams) stdmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define stdmemIsReady(pMemory) stdmemIsReady_DISPATCH(pMemory) +#define stdmemIsGpuMapAllowed(pMemory, pGpu) stdmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define stdmemIsReady(pMemory, bCopyConstructorContext) stdmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define stdmemCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) stdmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) #define stdmemPreDestruct(pResource) stdmemPreDestruct_DISPATCH(pResource) +#define stdmemIsDuplicate(pMemory, hMemory, pDuplicate) stdmemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) #define stdmemUnmapFrom(pResource, pParams) stdmemUnmapFrom_DISPATCH(pResource, pParams) #define stdmemControl_Epilogue(pResource, pCallContext, pParams) stdmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define stdmemControlLookup(pResource, pParams, ppEntry) stdmemControlLookup_DISPATCH(pResource, pParams, ppEntry) @@ -143,6 +147,7 @@ NV_STATUS __nvoc_objCreate_StandardMemory(StandardMemory**, Dynamic*, NvU32, CAL #define stdmemAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) stdmemAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvU32 stdmemGetSysmemPageSize_IMPL(struct OBJGPU *pGpu, struct StandardMemory *pMemory); + #ifdef __nvoc_standard_mem_h_disabled static inline NvU32 stdmemGetSysmemPageSize(struct OBJGPU *pGpu, struct StandardMemory *pMemory) { NV_ASSERT_FAILED_PRECOMP("StandardMemory was disabled!"); @@ -208,8 +213,12 @@ static inline NV_STATUS stdmemControl_Prologue_DISPATCH(struct StandardMemory *p return pResource->__stdmemControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS stdmemIsReady_DISPATCH(struct StandardMemory *pMemory) { - return pMemory->__stdmemIsReady__(pMemory); +static inline NvBool stdmemIsGpuMapAllowed_DISPATCH(struct StandardMemory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__stdmemIsGpuMapAllowed__(pMemory, pGpu); +} + +static inline NV_STATUS stdmemIsReady_DISPATCH(struct StandardMemory *pMemory, NvBool bCopyConstructorContext) { + return pMemory->__stdmemIsReady__(pMemory, bCopyConstructorContext); } static inline NV_STATUS stdmemCheckCopyPermissions_DISPATCH(struct StandardMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { @@ -220,6 +229,10 @@ static inline void stdmemPreDestruct_DISPATCH(struct StandardMemory *pResource) pResource->__stdmemPreDestruct__(pResource); } +static inline NV_STATUS stdmemIsDuplicate_DISPATCH(struct StandardMemory *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return pMemory->__stdmemIsDuplicate__(pMemory, hMemory, pDuplicate); +} + static inline NV_STATUS stdmemUnmapFrom_DISPATCH(struct StandardMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return pResource->__stdmemUnmapFrom__(pResource, pParams); } @@ -241,14 +254,19 @@ static inline NvBool stdmemAccessCallback_DISPATCH(struct StandardMemory *pResou } NV_STATUS stdmemConstruct_IMPL(struct StandardMemory *arg_pStandardMemory, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_stdmemConstruct(arg_pStandardMemory, arg_pCallContext, arg_pParams) stdmemConstruct_IMPL(arg_pStandardMemory, arg_pCallContext, arg_pParams) NV_STATUS stdmemValidateParams_IMPL(struct OBJGPU *pGpu, NvHandle hClient, NV_MEMORY_ALLOCATION_PARAMS *pAllocData); + #define stdmemValidateParams(pGpu, hClient, pAllocData) stdmemValidateParams_IMPL(pGpu, hClient, pAllocData) void stdmemDumpInputAllocParams_IMPL(NV_MEMORY_ALLOCATION_PARAMS *pAllocData, CALL_CONTEXT *pCallContext); + #define stdmemDumpInputAllocParams(pAllocData, pCallContext) stdmemDumpInputAllocParams_IMPL(pAllocData, pCallContext) void stdmemDumpOutputAllocParams_IMPL(NV_MEMORY_ALLOCATION_PARAMS *pAllocData); + #define stdmemDumpOutputAllocParams(pAllocData) stdmemDumpOutputAllocParams_IMPL(pAllocData) NvU32 stdmemQueryPageSize_IMPL(struct MemoryManager *pMemoryManager, NvHandle hClient, NV_MEMORY_ALLOCATION_PARAMS *pAllocData); + #define stdmemQueryPageSize(pMemoryManager, hClient, pAllocData) stdmemQueryPageSize_IMPL(pMemoryManager, hClient, pAllocData) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_subdevice_diag_nvoc.c b/src/nvidia/generated/g_subdevice_diag_nvoc.c index bdad0db81..f09a7e2ce 100644 --- a/src/nvidia/generated/g_subdevice_diag_nvoc.c +++ b/src/nvidia/generated/g_subdevice_diag_nvoc.c @@ -203,6 +203,10 @@ static void __nvoc_thunk_RsResource_diagapiPreDestruct(struct DiagApi *pResource resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DiagApi_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_RsResource_diagapiIsDuplicate(struct DiagApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DiagApi_RsResource.offset), hMemory, pDuplicate); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_diagapiGetNotificationListPtr(struct DiagApi *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_DiagApi_Notifier.offset)); } @@ -301,6 +305,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DiagApi[ #endif }, { /* [5] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) diagapiCtrlCmdFbClearRemappedRows_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x208f0515u, + /*paramSize=*/ sizeof(NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DiagApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "diagapiCtrlCmdFbClearRemappedRows" +#endif + }, + { /* [6] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -315,7 +334,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DiagApi[ /*func=*/ "diagapiCtrlCmdBifPBIWriteCommand" #endif }, - { /* [6] */ + { /* [7] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -330,7 +349,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DiagApi[ /*func=*/ "diagapiCtrlCmdBifConfigRegRead" #endif }, - { /* [7] */ + { /* [8] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -345,7 +364,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DiagApi[ /*func=*/ "diagapiCtrlCmdBifConfigRegWrite" #endif }, - { /* [8] */ + { /* [9] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -358,21 +377,6 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DiagApi[ /*pClassInfo=*/ &(__nvoc_class_def_DiagApi.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "diagapiCtrlCmdBifInfo" -#endif - }, - { /* [9] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*pFunc=*/ (void (*)(void)) NULL, -#else - /*pFunc=*/ (void (*)(void)) diagapiCtrlCmdMmuGetNumHshubmmus_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, - /*accessRight=*/0x0u, - /*methodId=*/ 0x208f0b03u, - /*paramSize=*/ sizeof(NV208F_CTRL_MMU_GET_NUM_HSHUBMMUS_PARAMS), - /*pClassInfo=*/ &(__nvoc_class_def_DiagApi.classInfo), -#if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "diagapiCtrlCmdMmuGetNumHshubmmus" #endif }, { /* [10] */ @@ -492,6 +496,10 @@ static void __nvoc_init_funcTable_DiagApi_1(DiagApi *pThis) { pThis->__diagapiCtrlCmdFbEccSetKillPtr__ = &diagapiCtrlCmdFbEccSetKillPtr_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + pThis->__diagapiCtrlCmdFbClearRemappedRows__ = &diagapiCtrlCmdFbClearRemappedRows_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__diagapiCtrlCmdGpuGetRamSvopValues__ = &diagapiCtrlCmdGpuGetRamSvopValues_IMPL; #endif @@ -520,10 +528,6 @@ static void __nvoc_init_funcTable_DiagApi_1(DiagApi *pThis) { pThis->__diagapiCtrlCmdBifInfo__ = &diagapiCtrlCmdBifInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - pThis->__diagapiCtrlCmdMmuGetNumHshubmmus__ = &diagapiCtrlCmdMmuGetNumHshubmmus_IMPL; -#endif - pThis->__nvoc_base_GpuResource.__gpuresControl__ = &__nvoc_thunk_DiagApi_gpuresControl; pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__resControlFilter__ = &__nvoc_thunk_DiagApi_resControlFilter; @@ -570,6 +574,8 @@ static void __nvoc_init_funcTable_DiagApi_1(DiagApi *pThis) { pThis->__diagapiPreDestruct__ = &__nvoc_thunk_RsResource_diagapiPreDestruct; + pThis->__diagapiIsDuplicate__ = &__nvoc_thunk_RsResource_diagapiIsDuplicate; + pThis->__diagapiGetNotificationListPtr__ = &__nvoc_thunk_Notifier_diagapiGetNotificationListPtr; pThis->__diagapiGetNotificationShare__ = &__nvoc_thunk_Notifier_diagapiGetNotificationShare; diff --git a/src/nvidia/generated/g_subdevice_diag_nvoc.h b/src/nvidia/generated/g_subdevice_diag_nvoc.h index 22f708ed5..4a2a6b941 100644 --- a/src/nvidia/generated/g_subdevice_diag_nvoc.h +++ b/src/nvidia/generated/g_subdevice_diag_nvoc.h @@ -68,6 +68,7 @@ struct DiagApi { NV_STATUS (*__diagapiCtrlCmdFifoGetChannelState__)(struct DiagApi *, NV208F_CTRL_FIFO_GET_CHANNEL_STATE_PARAMS *); NV_STATUS (*__diagapiCtrlCmdFbCtrlGpuCache__)(struct DiagApi *, NV208F_CTRL_FB_CTRL_GPU_CACHE_PARAMS *); NV_STATUS (*__diagapiCtrlCmdFbEccSetKillPtr__)(struct DiagApi *, NV208F_CTRL_FB_ECC_SET_KILL_PTR_PARAMS *); + NV_STATUS (*__diagapiCtrlCmdFbClearRemappedRows__)(struct DiagApi *, NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS *); NV_STATUS (*__diagapiCtrlCmdGpuGetRamSvopValues__)(struct DiagApi *, NV208F_CTRL_GPU_RAM_SVOP_VALUES_PARAMS *); NV_STATUS (*__diagapiCtrlCmdGpuSetRamSvopValues__)(struct DiagApi *, NV208F_CTRL_GPU_RAM_SVOP_VALUES_PARAMS *); NV_STATUS (*__diagapiCtrlCmdGpuVerifyInforom__)(struct DiagApi *, NV208F_CTRL_GPU_VERIFY_INFOROM_PARAMS *); @@ -75,7 +76,6 @@ struct DiagApi { NV_STATUS (*__diagapiCtrlCmdBifConfigRegRead__)(struct DiagApi *, NV208F_CTRL_BIF_CONFIG_REG_READ_PARAMS *); NV_STATUS (*__diagapiCtrlCmdBifConfigRegWrite__)(struct DiagApi *, NV208F_CTRL_BIF_CONFIG_REG_WRITE_PARAMS *); NV_STATUS (*__diagapiCtrlCmdBifInfo__)(struct DiagApi *, NV208F_CTRL_BIF_INFO_PARAMS *); - NV_STATUS (*__diagapiCtrlCmdMmuGetNumHshubmmus__)(struct DiagApi *, NV208F_CTRL_MMU_GET_NUM_HSHUBMMUS_PARAMS *); NvBool (*__diagapiShareCallback__)(struct DiagApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__diagapiMapTo__)(struct DiagApi *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__diagapiGetOrAllocNotifShare__)(struct DiagApi *, NvHandle, NvHandle, struct NotifShare **); @@ -97,6 +97,7 @@ struct DiagApi { NV_STATUS (*__diagapiUnregisterEvent__)(struct DiagApi *, NvHandle, NvHandle, NvHandle, NvHandle); NvBool (*__diagapiCanCopy__)(struct DiagApi *); void (*__diagapiPreDestruct__)(struct DiagApi *); + NV_STATUS (*__diagapiIsDuplicate__)(struct DiagApi *, NvHandle, NvBool *); PEVENTNOTIFICATION *(*__diagapiGetNotificationListPtr__)(struct DiagApi *); struct NotifShare *(*__diagapiGetNotificationShare__)(struct DiagApi *); NV_STATUS (*__diagapiMap__)(struct DiagApi *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -139,6 +140,7 @@ NV_STATUS __nvoc_objCreate_DiagApi(DiagApi**, Dynamic*, NvU32, struct CALL_CONTE #define diagapiCtrlCmdFifoGetChannelState(pDiagApi, pChannelStateParams) diagapiCtrlCmdFifoGetChannelState_DISPATCH(pDiagApi, pChannelStateParams) #define diagapiCtrlCmdFbCtrlGpuCache(pDiagApi, pGpuCacheParams) diagapiCtrlCmdFbCtrlGpuCache_DISPATCH(pDiagApi, pGpuCacheParams) #define diagapiCtrlCmdFbEccSetKillPtr(pDiagApi, pParams) diagapiCtrlCmdFbEccSetKillPtr_DISPATCH(pDiagApi, pParams) +#define diagapiCtrlCmdFbClearRemappedRows(pDiagApi, pRemappedRowsParams) diagapiCtrlCmdFbClearRemappedRows_DISPATCH(pDiagApi, pRemappedRowsParams) #define diagapiCtrlCmdGpuGetRamSvopValues(pDiagApi, pGetRamSvopParams) diagapiCtrlCmdGpuGetRamSvopValues_DISPATCH(pDiagApi, pGetRamSvopParams) #define diagapiCtrlCmdGpuSetRamSvopValues(pDiagApi, pSetRamSvopParams) diagapiCtrlCmdGpuSetRamSvopValues_DISPATCH(pDiagApi, pSetRamSvopParams) #define diagapiCtrlCmdGpuVerifyInforom(pDiagApi, pParams) diagapiCtrlCmdGpuVerifyInforom_DISPATCH(pDiagApi, pParams) @@ -146,7 +148,6 @@ NV_STATUS __nvoc_objCreate_DiagApi(DiagApi**, Dynamic*, NvU32, struct CALL_CONTE #define diagapiCtrlCmdBifConfigRegRead(pDiagApi, pReadConfigReg) diagapiCtrlCmdBifConfigRegRead_DISPATCH(pDiagApi, pReadConfigReg) #define diagapiCtrlCmdBifConfigRegWrite(pDiagApi, pWriteConfigReg) diagapiCtrlCmdBifConfigRegWrite_DISPATCH(pDiagApi, pWriteConfigReg) #define diagapiCtrlCmdBifInfo(pDiagApi, pInfo) diagapiCtrlCmdBifInfo_DISPATCH(pDiagApi, pInfo) -#define diagapiCtrlCmdMmuGetNumHshubmmus(pDiagApi, pParams) diagapiCtrlCmdMmuGetNumHshubmmus_DISPATCH(pDiagApi, pParams) #define diagapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) diagapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) #define diagapiMapTo(pResource, pParams) diagapiMapTo_DISPATCH(pResource, pParams) #define diagapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) diagapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) @@ -168,6 +169,7 @@ NV_STATUS __nvoc_objCreate_DiagApi(DiagApi**, Dynamic*, NvU32, struct CALL_CONTE #define diagapiUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) diagapiUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define diagapiCanCopy(pResource) diagapiCanCopy_DISPATCH(pResource) #define diagapiPreDestruct(pResource) diagapiPreDestruct_DISPATCH(pResource) +#define diagapiIsDuplicate(pResource, hMemory, pDuplicate) diagapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define diagapiGetNotificationListPtr(pNotifier) diagapiGetNotificationListPtr_DISPATCH(pNotifier) #define diagapiGetNotificationShare(pNotifier) diagapiGetNotificationShare_DISPATCH(pNotifier) #define diagapiMap(pGpuResource, pCallContext, pParams, pCpuMapping) diagapiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -214,6 +216,12 @@ static inline NV_STATUS diagapiCtrlCmdFbEccSetKillPtr_DISPATCH(struct DiagApi *p return pDiagApi->__diagapiCtrlCmdFbEccSetKillPtr__(pDiagApi, pParams); } +NV_STATUS diagapiCtrlCmdFbClearRemappedRows_IMPL(struct DiagApi *pDiagApi, NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS *pRemappedRowsParams); + +static inline NV_STATUS diagapiCtrlCmdFbClearRemappedRows_DISPATCH(struct DiagApi *pDiagApi, NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS *pRemappedRowsParams) { + return pDiagApi->__diagapiCtrlCmdFbClearRemappedRows__(pDiagApi, pRemappedRowsParams); +} + NV_STATUS diagapiCtrlCmdGpuGetRamSvopValues_IMPL(struct DiagApi *pDiagApi, NV208F_CTRL_GPU_RAM_SVOP_VALUES_PARAMS *pGetRamSvopParams); static inline NV_STATUS diagapiCtrlCmdGpuGetRamSvopValues_DISPATCH(struct DiagApi *pDiagApi, NV208F_CTRL_GPU_RAM_SVOP_VALUES_PARAMS *pGetRamSvopParams) { @@ -256,12 +264,6 @@ static inline NV_STATUS diagapiCtrlCmdBifInfo_DISPATCH(struct DiagApi *pDiagApi, return pDiagApi->__diagapiCtrlCmdBifInfo__(pDiagApi, pInfo); } -NV_STATUS diagapiCtrlCmdMmuGetNumHshubmmus_IMPL(struct DiagApi *pDiagApi, NV208F_CTRL_MMU_GET_NUM_HSHUBMMUS_PARAMS *pParams); - -static inline NV_STATUS diagapiCtrlCmdMmuGetNumHshubmmus_DISPATCH(struct DiagApi *pDiagApi, NV208F_CTRL_MMU_GET_NUM_HSHUBMMUS_PARAMS *pParams) { - return pDiagApi->__diagapiCtrlCmdMmuGetNumHshubmmus__(pDiagApi, pParams); -} - static inline NvBool diagapiShareCallback_DISPATCH(struct DiagApi *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pGpuResource->__diagapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } @@ -346,6 +348,10 @@ static inline void diagapiPreDestruct_DISPATCH(struct DiagApi *pResource) { pResource->__diagapiPreDestruct__(pResource); } +static inline NV_STATUS diagapiIsDuplicate_DISPATCH(struct DiagApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__diagapiIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline PEVENTNOTIFICATION *diagapiGetNotificationListPtr_DISPATCH(struct DiagApi *pNotifier) { return pNotifier->__diagapiGetNotificationListPtr__(pNotifier); } @@ -363,6 +369,7 @@ static inline NvBool diagapiAccessCallback_DISPATCH(struct DiagApi *pResource, s } NV_STATUS diagapiConstruct_IMPL(struct DiagApi *arg_pDiagApi, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_diagapiConstruct(arg_pDiagApi, arg_pCallContext, arg_pParams) diagapiConstruct_IMPL(arg_pDiagApi, arg_pCallContext, arg_pParams) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_subdevice_nvoc.c b/src/nvidia/generated/g_subdevice_nvoc.c index c4b06b8ad..6d7ddf7ed 100644 --- a/src/nvidia/generated/g_subdevice_nvoc.c +++ b/src/nvidia/generated/g_subdevice_nvoc.c @@ -203,6 +203,10 @@ static NvBool __nvoc_thunk_RsResource_subdeviceCanCopy(struct Subdevice *pResour return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Subdevice_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_RsResource_subdeviceIsDuplicate(struct Subdevice *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Subdevice_RsResource.offset), hMemory, pDuplicate); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_subdeviceGetNotificationListPtr(struct Subdevice *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_Subdevice_Notifier.offset)); } @@ -241,12 +245,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [1] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa10u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa12u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuGetNameString_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa10u) - /*flags=*/ 0xa10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa12u) + /*flags=*/ 0xa12u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800110u, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS), @@ -256,12 +260,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [2] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4a10u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4a12u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuGetShortNameString_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4a10u) - /*flags=*/ 0x4a10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4a12u) + /*flags=*/ 0x4a12u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800111u, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS), @@ -406,12 +410,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [12] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuPromoteCtx_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) - /*flags=*/ 0x2204u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u) + /*flags=*/ 0x102204u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080012bu, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS), @@ -421,12 +425,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [13] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2200u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuEvictCtx_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) - /*flags=*/ 0x2200u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2200u) + /*flags=*/ 0x1c2200u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080012cu, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_EVICT_CTX_PARAMS), @@ -436,12 +440,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [14] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x142204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuInitializeCtx_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) - /*flags=*/ 0x2204u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x142204u) + /*flags=*/ 0x142204u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080012du, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS), @@ -1231,6 +1235,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [67] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuHandleVfPriFault_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) + /*flags=*/ 0x2210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800192u, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdGpuHandleVfPriFault" +#endif + }, + { /* [68] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1245,7 +1264,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuSetComputePolicyConfig" #endif }, - { /* [68] */ + { /* [69] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1260,7 +1279,37 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuGetComputePolicyConfig" #endif }, - { /* [69] */ + { /* [70] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuGetGfid_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800196u, + /*paramSize=*/ sizeof(NV2080_CTRL_GPU_GET_GFID_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdGpuGetGfid" +#endif + }, + { /* [71] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdUpdateGfidP2pCapability_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*flags=*/ 0x4u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800197u, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdUpdateGfidP2pCapability" +#endif + }, + { /* [72] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1275,7 +1324,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdValidateMemMapRequest" #endif }, - { /* [70] */ + { /* [73] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x12u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1290,7 +1339,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuGetEngineLoadTimes" #endif }, - { /* [71] */ + { /* [74] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGetP2pCaps_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x208001a0u, + /*paramSize=*/ sizeof(NV2080_CTRL_GET_P2P_CAPS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdGetP2pCaps" +#endif + }, + { /* [75] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1305,7 +1369,52 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuGetComputeProfiles" #endif }, - { /* [72] */ + { /* [76] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGetGpuFabricProbeInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) + /*flags=*/ 0x50u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x208001a3u, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdGetGpuFabricProbeInfo" +#endif + }, + { /* [77] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuGetChipDetails_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4210u) + /*flags=*/ 0x4210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x208001a4u, + /*paramSize=*/ sizeof(NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdGpuGetChipDetails" +#endif + }, + { /* [78] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuMigratableOps_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x208001a6u, + /*paramSize=*/ sizeof(NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdGpuMigratableOps" +#endif + }, + { /* [79] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1320,7 +1429,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEventSetNotification" #endif }, - { /* [73] */ + { /* [80] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1335,7 +1444,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEventSetTrigger" #endif }, - { /* [74] */ + { /* [81] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1350,7 +1459,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEventSetMemoryNotifies" #endif }, - { /* [75] */ + { /* [82] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1365,7 +1474,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEventSetSemaphoreMemory" #endif }, - { /* [76] */ + { /* [83] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1380,7 +1489,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEventSetSemaMemValidation" #endif }, - { /* [77] */ + { /* [84] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1395,7 +1504,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEventSetTriggerFifo" #endif }, - { /* [78] */ + { /* [85] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1410,7 +1519,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdTimerSchedule" #endif }, - { /* [79] */ + { /* [86] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1425,7 +1534,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdTimerCancel" #endif }, - { /* [80] */ + { /* [87] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1440,7 +1549,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdTimerGetTime" #endif }, - { /* [81] */ + { /* [88] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1455,7 +1564,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdTimerGetRegisterOffset" #endif }, - { /* [82] */ + { /* [89] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1470,7 +1579,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdTimerGetGpuCpuTimeCorrelationInfo" #endif }, - { /* [83] */ + { /* [90] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2010u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1485,7 +1594,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdTimerSetGrTickFreq" #endif }, - { /* [84] */ + { /* [91] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1500,7 +1609,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdI2cReadBuffer" #endif }, - { /* [85] */ + { /* [92] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1515,7 +1624,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdI2cWriteBuffer" #endif }, - { /* [86] */ + { /* [93] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1530,7 +1639,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdI2cReadReg" #endif }, - { /* [87] */ + { /* [94] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1545,7 +1654,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdI2cWriteReg" #endif }, - { /* [88] */ + { /* [95] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1560,7 +1669,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBiosGetSKUInfo" #endif }, - { /* [89] */ + { /* [96] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1575,7 +1684,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBiosGetPostTime" #endif }, - { /* [90] */ + { /* [97] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1590,7 +1699,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBiosGetUefiSupport" #endif }, - { /* [91] */ + { /* [98] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBiosGetNbsiV2_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x2080080eu, + /*paramSize=*/ sizeof(NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdBiosGetNbsiV2" +#endif + }, + { /* [99] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1605,7 +1729,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBiosGetInfoV2" #endif }, - { /* [92] */ + { /* [100] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1620,7 +1744,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDisplayGetStaticInfo" #endif }, - { /* [93] */ + { /* [101] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1635,7 +1759,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMemSysGetStaticConfig" #endif }, - { /* [94] */ + { /* [102] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1650,7 +1774,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer" #endif }, - { /* [95] */ + { /* [103] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1665,7 +1789,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer" #endif }, - { /* [96] */ + { /* [104] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1680,7 +1804,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetCaps" #endif }, - { /* [97] */ + { /* [105] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1695,13 +1819,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalUvmServiceAccessCntrBuffer" #endif }, - { /* [98] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) + { /* [106] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdKGrInternalStaticGetGlobalSmOrder_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) - /*flags=*/ 0x2600u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) + /*flags=*/ 0x1c2600u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800a22u, /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS), @@ -1710,7 +1834,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetGlobalSmOrder" #endif }, - { /* [99] */ + { /* [107] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1725,13 +1849,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMsencGetCaps" #endif }, - { /* [100] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) + { /* [108] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdKGrInternalStaticGetFloorsweepingMasks_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) - /*flags=*/ 0x2600u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) + /*flags=*/ 0x1c2600u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800a26u, /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS), @@ -1740,13 +1864,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetFloorsweepingMasks" #endif }, - { /* [101] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + { /* [109] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x80000u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdKGrGetCtxBufferPtes_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) - /*flags=*/ 0x0u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x80000u) + /*flags=*/ 0x80000u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800a28u, /*paramSize=*/ sizeof(NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS), @@ -1755,7 +1879,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCtxBufferPtes" #endif }, - { /* [102] */ + { /* [110] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1770,13 +1894,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalUvmGetAccessCntrBufferSize" #endif }, - { /* [103] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) + { /* [111] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdKGrInternalStaticGetInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) - /*flags=*/ 0x2600u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) + /*flags=*/ 0x1c2600u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800a2au, /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS), @@ -1785,13 +1909,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetInfo" #endif }, - { /* [104] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) + { /* [112] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdKGrInternalStaticGetZcullInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) - /*flags=*/ 0x2600u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) + /*flags=*/ 0x1c2600u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800a2cu, /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS), @@ -1800,13 +1924,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetZcullInfo" #endif }, - { /* [105] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) + { /* [113] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdKGrInternalStaticGetRopInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) - /*flags=*/ 0x2600u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) + /*flags=*/ 0x1c2600u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800a2eu, /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS), @@ -1815,13 +1939,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetRopInfo" #endif }, - { /* [106] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) + { /* [114] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdKGrInternalStaticGetPpcMasks_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) - /*flags=*/ 0x2600u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) + /*flags=*/ 0x1c2600u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800a30u, /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS), @@ -1830,13 +1954,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetPpcMasks" #endif }, - { /* [107] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) + { /* [115] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdKGrInternalStaticGetContextBuffersInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) - /*flags=*/ 0x2600u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) + /*flags=*/ 0x1c2600u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800a32u, /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS), @@ -1845,13 +1969,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetContextBuffersInfo" #endif }, - { /* [108] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) + { /* [116] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdKGrInternalStaticGetSmIssueRateModifier_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) - /*flags=*/ 0x2600u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) + /*flags=*/ 0x1c2600u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800a34u, /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS), @@ -1860,7 +1984,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetSmIssueRateModifier" #endif }, - { /* [109] */ + { /* [117] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1875,13 +1999,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGetChipInfo" #endif }, - { /* [110] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) + { /* [118] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdKGrInternalStaticGetFecsRecordSize_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) - /*flags=*/ 0x2600u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) + /*flags=*/ 0x1c2600u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800a3du, /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS), @@ -1890,13 +2014,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetFecsRecordSize" #endif }, - { /* [111] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) + { /* [119] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdKGrInternalStaticGetFecsTraceDefines_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) - /*flags=*/ 0x2600u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) + /*flags=*/ 0x1c2600u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800a3fu, /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS), @@ -1905,7 +2029,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetFecsTraceDefines" #endif }, - { /* [112] */ + { /* [120] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1920,7 +2044,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGetDeviceInfoTable" #endif }, - { /* [113] */ + { /* [121] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1935,7 +2059,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGetUserRegisterAccessMap" #endif }, - { /* [114] */ + { /* [122] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1950,13 +2074,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGetConstructedFalconInfo" #endif }, - { /* [115] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) + { /* [123] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdKGrInternalStaticGetPdbProperties_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) - /*flags=*/ 0x2600u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) + /*flags=*/ 0x1c2600u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800a48u, /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS), @@ -1965,7 +2089,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetPdbProperties" #endif }, - { /* [116] */ + { /* [124] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1980,7 +2104,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDisplayWriteInstMem" #endif }, - { /* [117] */ + { /* [125] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1995,7 +2119,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalRecoverAllComputeContexts" #endif }, - { /* [118] */ + { /* [126] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2010,7 +2134,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDisplayGetIpVersion" #endif }, - { /* [119] */ + { /* [127] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2025,7 +2149,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGetSmcMode" #endif }, - { /* [120] */ + { /* [128] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2040,7 +2164,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDisplaySetupRgLineIntr" #endif }, - { /* [121] */ + { /* [129] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2055,7 +2179,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMemSysSetPartitionableMem" #endif }, - { /* [122] */ + { /* [130] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2070,7 +2194,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalFifoPromoteRunlistBuffers" #endif }, - { /* [123] */ + { /* [131] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2085,37 +2209,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDisplaySetImportedImpData" #endif }, - { /* [124] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - /*pFunc=*/ (void (*)(void)) NULL, -#else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalBusBindLocalGfidForP2p_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - /*flags=*/ 0x600u, - /*accessRight=*/0x0u, - /*methodId=*/ 0x20800a55u, - /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_BUS_BIND_LOCAL_GFID_FOR_P2P_PARAMS), - /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), -#if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "subdeviceCtrlCmdInternalBusBindLocalGfidForP2p" -#endif - }, - { /* [125] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - /*pFunc=*/ (void (*)(void)) NULL, -#else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalBusBindRemoteGfidForP2p_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - /*flags=*/ 0x600u, - /*accessRight=*/0x0u, - /*methodId=*/ 0x20800a56u, - /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_BUS_BIND_REMOTE_GFID_FOR_P2P_PARAMS), - /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), -#if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "subdeviceCtrlCmdInternalBusBindRemoteGfidForP2p" -#endif - }, - { /* [126] */ + { /* [132] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2130,7 +2224,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDisplaySetChannelPushbuffer" #endif }, - { /* [127] */ + { /* [133] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2145,7 +2239,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGmmuGetStaticInfo" #endif }, - { /* [128] */ + { /* [134] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2160,7 +2254,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetHeapReservationSize" #endif }, - { /* [129] */ + { /* [135] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2175,7 +2269,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdIntrGetKernelTable" #endif }, - { /* [130] */ + { /* [136] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2190,7 +2284,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDisplayGetDisplayMask" #endif }, - { /* [131] */ + { /* [137] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2205,7 +2299,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalFifoGetNumChannels" #endif }, - { /* [132] */ + { /* [138] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2220,7 +2314,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalStaticKMIGmgrGetProfiles" #endif }, - { /* [133] */ + { /* [139] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2235,7 +2329,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalStaticKMIGmgrGetPartitionableEngines" #endif }, - { /* [134] */ + { /* [140] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2250,7 +2344,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalStaticKMIGmgrGetSwizzIdFbMemPageRanges" #endif }, - { /* [135] */ + { /* [141] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2265,7 +2359,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKMemSysGetMIGMemoryConfig" #endif }, - { /* [136] */ + { /* [142] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2280,7 +2374,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetZbcReferenced" #endif }, - { /* [137] */ + { /* [143] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2295,7 +2389,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalRcWatchdogTimeout" #endif }, - { /* [138] */ + { /* [144] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2310,7 +2404,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMemSysGetMIGMemoryPartitionTable" #endif }, - { /* [139] */ + { /* [145] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2325,7 +2419,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMemSysL2InvalidateEvict" #endif }, - { /* [140] */ + { /* [146] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2340,7 +2434,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMemSysFlushL2AllRamsAndCaches" #endif }, - { /* [141] */ + { /* [147] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2355,7 +2449,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMemSysDisableNvlinkPeers" #endif }, - { /* [142] */ + { /* [148] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2370,7 +2464,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMemSysProgramRawCompressionMode" #endif }, - { /* [143] */ + { /* [149] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2385,7 +2479,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalBusFlushWithSysmembar" #endif }, - { /* [144] */ + { /* [150] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2400,7 +2494,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalBusSetupP2pMailboxLocal" #endif }, - { /* [145] */ + { /* [151] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2415,7 +2509,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalBusSetupP2pMailboxRemote" #endif }, - { /* [146] */ + { /* [152] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2430,7 +2524,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalBusDestroyP2pMailbox" #endif }, - { /* [147] */ + { /* [153] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2445,7 +2539,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalBusCreateC2cPeerMapping" #endif }, - { /* [148] */ + { /* [154] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2460,7 +2554,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalBusRemoveC2cPeerMapping" #endif }, - { /* [149] */ + { /* [155] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2475,7 +2569,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfCudaLimitDisable" #endif }, - { /* [150] */ + { /* [156] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800a7bu, + /*paramSize=*/ 0, + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit" +#endif + }, + { /* [157] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2490,7 +2599,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfOptpCliClear" #endif }, - { /* [151] */ + { /* [158] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2505,7 +2614,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfGpuBoostSyncSetControl" #endif }, - { /* [152] */ + { /* [159] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2520,7 +2629,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfSyncGpuBoostSetLimits" #endif }, - { /* [153] */ + { /* [160] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2535,7 +2644,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfGpuBoostSyncGetInfo" #endif }, - { /* [154] */ + { /* [161] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalPerfGetAuxPowerState_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800a81u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalPerfGetAuxPowerState" +#endif + }, + { /* [162] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2550,7 +2674,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdHshubPeerConnConfig" #endif }, - { /* [155] */ + { /* [163] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2565,7 +2689,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdHshubFirstLinkPeerId" #endif }, - { /* [156] */ + { /* [164] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2580,7 +2704,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdHshubGetHshubIdForLinks" #endif }, - { /* [157] */ + { /* [165] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2595,7 +2719,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdHshubGetNumUnits" #endif }, - { /* [158] */ + { /* [166] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2610,7 +2734,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdHshubNextHshubId" #endif }, - { /* [159] */ + { /* [167] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2625,7 +2749,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfPerfmonClientReservationCheck" #endif }, - { /* [160] */ + { /* [168] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2640,7 +2764,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfPerfmonClientReservationSet" #endif }, - { /* [161] */ + { /* [169] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2655,7 +2779,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfBoostSet_2x" #endif }, - { /* [162] */ + { /* [170] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2670,7 +2794,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGmmuRegisterFaultBuffer" #endif }, - { /* [163] */ + { /* [171] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2685,7 +2809,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGmmuUnregisterFaultBuffer" #endif }, - { /* [164] */ + { /* [172] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2700,7 +2824,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGmmuRegisterClientShadowFaultBuffer" #endif }, - { /* [165] */ + { /* [173] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2715,7 +2839,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer" #endif }, - { /* [166] */ + { /* [174] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalGmmuCopyReservedSplitGVASpacePdesServer_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800a9fu, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalGmmuCopyReservedSplitGVASpacePdesServer" +#endif + }, + { /* [175] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2730,7 +2869,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfBoostSet_3x" #endif }, - { /* [167] */ + { /* [176] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2745,7 +2884,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfBoostClear_3x" #endif }, - { /* [168] */ + { /* [177] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2760,7 +2899,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalKMIGmgrExportGPUInstance" #endif }, - { /* [169] */ + { /* [178] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2775,7 +2914,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalKMIGmgrImportGPUInstance" #endif }, - { /* [170] */ + { /* [179] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2790,7 +2929,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBifGetStaticInfo" #endif }, - { /* [171] */ + { /* [180] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2805,7 +2944,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalNvlinkEnableComputePeerAddr" #endif }, - { /* [172] */ + { /* [181] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2820,7 +2959,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalNvlinkGetSetNvswitchFabricAddr" #endif }, - { /* [173] */ + { /* [182] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2835,7 +2974,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBifGetAspmL1Flags" #endif }, - { /* [174] */ + { /* [183] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2850,7 +2989,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfCfControllerSetMaxVGpuVMCount" #endif }, - { /* [175] */ + { /* [184] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2865,7 +3004,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCcuMap" #endif }, - { /* [176] */ + { /* [185] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2874,13 +3013,43 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*flags=*/ 0x600u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800ab4u, - /*paramSize=*/ 0, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS), /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "subdeviceCtrlCmdCcuUnmap" #endif }, - { /* [177] */ + { /* [186] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalSetP2pCaps_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ab5u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalSetP2pCaps" +#endif + }, + { /* [187] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalRemoveP2pCaps_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ab6u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalRemoveP2pCaps" +#endif + }, + { /* [188] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2895,7 +3064,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGetPcieP2pCaps" #endif }, - { /* [178] */ + { /* [189] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2910,7 +3079,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBifSetPcieRo" #endif }, - { /* [179] */ + { /* [190] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2925,7 +3094,157 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalStaticKMIGmgrGetComputeInstanceProfiles" #endif }, - { /* [180] */ + { /* [191] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdCcuSetStreamState_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800abdu, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdCcuSetStreamState" +#endif + }, + { /* [192] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalInitGpuIntr_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800abeu, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalInitGpuIntr" +#endif + }, + { /* [193] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalGsyncOptimizeTiming_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800abfu, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalGsyncOptimizeTiming" +#endif + }, + { /* [194] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalGsyncGetDisplayIds_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ac0u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalGsyncGetDisplayIds" +#endif + }, + { /* [195] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalGsyncSetStereoSync_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ac1u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalGsyncSetStereoSync" +#endif + }, + { /* [196] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalFbsrInit_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ac2u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalFbsrInit" +#endif + }, + { /* [197] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalFbsrSendRegionInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ac3u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalFbsrSendRegionInfo" +#endif + }, + { /* [198] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalGsyncGetVactiveLines_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ac4u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalGsyncGetVactiveLines" +#endif + }, + { /* [199] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalMemmgrGetVgpuHostRmReservedFb_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) + /*flags=*/ 0x610u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ac5u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalMemmgrGetVgpuHostRmReservedFb" +#endif + }, + { /* [200] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalPostInitBrightcStateLoad_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ac6u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalPostInitBrightcStateLoad" +#endif + }, + { /* [201] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2933,14 +3252,14 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*flags=*/ 0x600u, /*accessRight=*/0x0u, - /*methodId=*/ 0x20800ad8u, + /*methodId=*/ 0x20800ac7u, /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS), /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "subdeviceCtrlCmdInternalNvlinkGetNumActiveLinksPerIoctrl" #endif }, - { /* [181] */ + { /* [202] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2948,14 +3267,44 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*flags=*/ 0x600u, /*accessRight=*/0x0u, - /*methodId=*/ 0x20800ad9u, + /*methodId=*/ 0x20800ac8u, /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS), /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "subdeviceCtrlCmdInternalNvlinkGetTotalNumLinksPerIoctrl" #endif }, - { /* [182] */ + { /* [203] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalGsyncIsDisplayIdValid_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ac9u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalGsyncIsDisplayIdValid" +#endif + }, + { /* [204] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalGsyncSetOrRestoreGpioRasterSync_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800acau, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalGsyncSetOrRestoreGpioRasterSync" +#endif + }, + { /* [205] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2970,7 +3319,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGetCoherentFbApertureSize" #endif }, - { /* [183] */ + { /* [206] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2985,7 +3334,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdSetGpfifo" #endif }, - { /* [184] */ + { /* [207] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3000,7 +3349,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoBindEngines" #endif }, - { /* [185] */ + { /* [208] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3015,7 +3364,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdSetOperationalProperties" #endif }, - { /* [186] */ + { /* [209] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3030,7 +3379,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetPhysicalChannelCount" #endif }, - { /* [187] */ + { /* [210] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3045,7 +3394,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoGetInfo" #endif }, - { /* [188] */ + { /* [211] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3060,7 +3409,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoDisableChannels" #endif }, - { /* [189] */ + { /* [212] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3075,7 +3424,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoGetChannelMemInfo" #endif }, - { /* [190] */ + { /* [213] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3090,13 +3439,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoGetUserdLocation" #endif }, - { /* [191] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) + { /* [214] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2200u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFifoGetDeviceInfoTable_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) - /*flags=*/ 0x2200u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2200u) + /*flags=*/ 0x1c2200u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801112u, /*paramSize=*/ sizeof(NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS), @@ -3105,7 +3454,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoGetDeviceInfoTable" #endif }, - { /* [192] */ + { /* [215] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3120,7 +3469,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoClearFaultedBit" #endif }, - { /* [193] */ + { /* [216] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2310u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3135,7 +3484,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoRunlistSetSchedPolicy" #endif }, - { /* [194] */ + { /* [217] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3150,7 +3499,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoUpdateChannelInfo" #endif }, - { /* [195] */ + { /* [218] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3165,7 +3514,37 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoDisableUsermodeChannels" #endif }, - { /* [196] */ + { /* [219] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFifoSetupVfZombieSubctxPdb_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) + /*flags=*/ 0x2210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20801118u, + /*paramSize=*/ sizeof(NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdFifoSetupVfZombieSubctxPdb" +#endif + }, + { /* [220] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFifoGetAllocatedChannels_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*flags=*/ 0x4u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20801119u, + /*paramSize=*/ sizeof(NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdFifoGetAllocatedChannels" +#endif + }, + { /* [221] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3180,7 +3559,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetInfo" #endif }, - { /* [197] */ + { /* [222] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3195,7 +3574,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswZcullMode" #endif }, - { /* [198] */ + { /* [223] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3210,7 +3589,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetZcullInfo" #endif }, - { /* [199] */ + { /* [224] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2010u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3225,7 +3604,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswPmMode" #endif }, - { /* [200] */ + { /* [225] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3240,7 +3619,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswZcullBind" #endif }, - { /* [201] */ + { /* [226] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3255,7 +3634,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswPmBind" #endif }, - { /* [202] */ + { /* [227] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3270,7 +3649,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrSetGpcTileMap" #endif }, - { /* [203] */ + { /* [228] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3285,7 +3664,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswSmpcMode" #endif }, - { /* [204] */ + { /* [229] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3300,7 +3679,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetSmToGpcTpcMappings" #endif }, - { /* [205] */ + { /* [230] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3315,7 +3694,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrSetCtxswPreemptionMode" #endif }, - { /* [206] */ + { /* [231] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3330,7 +3709,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswPreemptionBind" #endif }, - { /* [207] */ + { /* [232] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3345,7 +3724,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrPcSamplingMode" #endif }, - { /* [208] */ + { /* [233] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3360,7 +3739,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetROPInfo" #endif }, - { /* [209] */ + { /* [234] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3375,7 +3754,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCtxswStats" #endif }, - { /* [210] */ + { /* [235] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3390,13 +3769,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCtxBufferSize" #endif }, - { /* [211] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + { /* [236] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x80000u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdKGrGetCtxBufferInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) - /*flags=*/ 0x0u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x80000u) + /*flags=*/ 0x80000u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801219u, /*paramSize=*/ sizeof(NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS), @@ -3405,7 +3784,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCtxBufferInfo" #endif }, - { /* [212] */ + { /* [237] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3420,7 +3799,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetGlobalSmOrder" #endif }, - { /* [213] */ + { /* [238] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3435,7 +3814,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCurrentResidentChannel" #endif }, - { /* [214] */ + { /* [239] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3450,7 +3829,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetVatAlarmData" #endif }, - { /* [215] */ + { /* [240] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3465,7 +3844,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetAttributeBufferSize" #endif }, - { /* [216] */ + { /* [241] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3480,7 +3859,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGfxPoolQuerySize" #endif }, - { /* [217] */ + { /* [242] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3495,7 +3874,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGfxPoolInitialize" #endif }, - { /* [218] */ + { /* [243] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3510,7 +3889,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGfxPoolAddSlots" #endif }, - { /* [219] */ + { /* [244] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3525,7 +3904,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGfxPoolRemoveSlots" #endif }, - { /* [220] */ + { /* [245] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x812u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3540,7 +3919,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCapsV2" #endif }, - { /* [221] */ + { /* [246] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3555,7 +3934,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetInfoV2" #endif }, - { /* [222] */ + { /* [247] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3570,7 +3949,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetGpcMask" #endif }, - { /* [223] */ + { /* [248] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3585,7 +3964,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetTpcMask" #endif }, - { /* [224] */ + { /* [249] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3600,7 +3979,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrSetTpcPartitionMode" #endif }, - { /* [225] */ + { /* [250] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3615,7 +3994,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetEngineContextProperties" #endif }, - { /* [226] */ + { /* [251] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3630,7 +4009,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetSmIssueRateModifier" #endif }, - { /* [227] */ + { /* [252] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3645,7 +4024,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrFecsBindEvtbufForUid" #endif }, - { /* [228] */ + { /* [253] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3660,7 +4039,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetPhysGpcMask" #endif }, - { /* [229] */ + { /* [254] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3675,7 +4054,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetPpcMask" #endif }, - { /* [230] */ + { /* [255] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3690,7 +4069,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetNumTpcsForGpc" #endif }, - { /* [231] */ + { /* [256] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3705,7 +4084,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCtxswModes" #endif }, - { /* [232] */ + { /* [257] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3720,7 +4099,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetGpcTileMap" #endif }, - { /* [233] */ + { /* [258] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3735,7 +4114,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetZcullMask" #endif }, - { /* [234] */ + { /* [259] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8010u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3750,7 +4129,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrFecsBindEvtbufForUidV2" #endif }, - { /* [235] */ + { /* [260] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3765,7 +4144,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetGfxGpcAndTpcInfo" #endif }, - { /* [236] */ + { /* [261] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3780,7 +4159,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetInfo" #endif }, - { /* [237] */ + { /* [262] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3795,7 +4174,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetInfoV2" #endif }, - { /* [238] */ + { /* [263] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3810,7 +4189,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCarveoutAddressInfo" #endif }, - { /* [239] */ + { /* [264] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3825,7 +4204,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCalibrationLockFailed" #endif }, - { /* [240] */ + { /* [265] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3840,7 +4219,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbFlushGpuCache" #endif }, - { /* [241] */ + { /* [266] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3855,7 +4234,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetGpuCacheAllocPolicy" #endif }, - { /* [242] */ + { /* [267] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3870,7 +4249,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetBar1Offset" #endif }, - { /* [243] */ + { /* [268] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3885,7 +4264,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetGpuCacheAllocPolicy" #endif }, - { /* [244] */ + { /* [269] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3900,7 +4279,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbIsKind" #endif }, - { /* [245] */ + { /* [270] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3915,7 +4294,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetGpuCacheInfo" #endif }, - { /* [246] */ + { /* [271] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3930,7 +4309,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetGpuCacheAllocPolicyV2" #endif }, - { /* [247] */ + { /* [272] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3945,7 +4324,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetGpuCacheAllocPolicyV2" #endif }, - { /* [248] */ + { /* [273] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3960,7 +4339,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetFBRegionInfo" #endif }, - { /* [249] */ + { /* [274] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3975,7 +4354,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetOfflinedPages" #endif }, - { /* [250] */ + { /* [275] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3990,7 +4369,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetLTCInfoForFBP" #endif }, - { /* [251] */ + { /* [276] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4005,7 +4384,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbCBCOp" #endif }, - { /* [252] */ + { /* [277] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4020,7 +4399,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCtagsForCbcEviction" #endif }, - { /* [253] */ + { /* [278] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4035,7 +4414,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetupVprRegion" #endif }, - { /* [254] */ + { /* [279] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4050,7 +4429,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCliManagedOfflinedPages" #endif }, - { /* [255] */ + { /* [280] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4065,7 +4444,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCompBitCopyConstructInfo" #endif }, - { /* [256] */ + { /* [281] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4080,7 +4459,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetRrd" #endif }, - { /* [257] */ + { /* [282] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4095,7 +4474,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetReadLimit" #endif }, - { /* [258] */ + { /* [283] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4110,7 +4489,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetWriteLimit" #endif }, - { /* [259] */ + { /* [284] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4125,7 +4504,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbPatchPbrForMining" #endif }, - { /* [260] */ + { /* [285] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4140,7 +4519,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetMemAlignment" #endif }, - { /* [261] */ + { /* [286] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4155,7 +4534,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetRemappedRows" #endif }, - { /* [262] */ + { /* [287] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4170,7 +4549,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetFsInfo" #endif }, - { /* [263] */ + { /* [288] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4185,7 +4564,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetRowRemapperHistogram" #endif }, - { /* [264] */ + { /* [289] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4200,7 +4579,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetDynamicOfflinedPages" #endif }, - { /* [265] */ + { /* [290] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4215,7 +4594,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbUpdateNumaStatus" #endif }, - { /* [266] */ + { /* [291] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4230,7 +4609,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetNumaInfo" #endif }, - { /* [267] */ + { /* [292] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x812u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4245,7 +4624,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcGetArchInfo" #endif }, - { /* [268] */ + { /* [293] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4260,7 +4639,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcServiceInterrupts" #endif }, - { /* [269] */ + { /* [294] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4275,7 +4654,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcGetManufacturer" #endif }, - { /* [270] */ + { /* [295] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4290,7 +4669,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcQueryHostclkSlowdownStatus" #endif }, - { /* [271] */ + { /* [296] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4305,7 +4684,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcSetHostclkSlowdownStatus" #endif }, - { /* [272] */ + { /* [297] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4320,7 +4699,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcChangeReplayableFaultOwnership" #endif }, - { /* [273] */ + { /* [298] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4335,7 +4714,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPciInfo" #endif }, - { /* [274] */ + { /* [299] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4350,7 +4729,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetInfo" #endif }, - { /* [275] */ + { /* [300] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4365,7 +4744,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPciBarInfo" #endif }, - { /* [276] */ + { /* [301] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4380,7 +4759,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetPcieLinkWidth" #endif }, - { /* [277] */ + { /* [302] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4395,7 +4774,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetPcieSpeed" #endif }, - { /* [278] */ + { /* [303] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4410,7 +4789,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetHwbcUpstreamPcieSpeed" #endif }, - { /* [279] */ + { /* [304] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4425,7 +4804,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetHwbcUpstreamPcieSpeed" #endif }, - { /* [280] */ + { /* [305] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4440,7 +4819,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusHWBCGetUpstreamBAR0" #endif }, - { /* [281] */ + { /* [306] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4455,7 +4834,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusServiceGpuMultifunctionState" #endif }, - { /* [282] */ + { /* [307] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4470,7 +4849,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPexCounters" #endif }, - { /* [283] */ + { /* [308] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4485,7 +4864,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusClearPexCounters" #endif }, - { /* [284] */ + { /* [309] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4500,7 +4879,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusFreezePexCounters" #endif }, - { /* [285] */ + { /* [310] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4515,7 +4894,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPexLaneCounters" #endif }, - { /* [286] */ + { /* [311] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4530,7 +4909,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPcieLtrLatency" #endif }, - { /* [287] */ + { /* [312] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4545,7 +4924,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetPcieLtrLatency" #endif }, - { /* [288] */ + { /* [313] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4560,7 +4939,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPexUtilCounters" #endif }, - { /* [289] */ + { /* [314] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4575,7 +4954,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusClearPexUtilCounters" #endif }, - { /* [290] */ + { /* [315] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4590,7 +4969,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetBFD" #endif }, - { /* [291] */ + { /* [316] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4605,7 +4984,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetAspmDisableFlags" #endif }, - { /* [292] */ + { /* [317] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4620,7 +4999,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetInfoV2" #endif }, - { /* [293] */ + { /* [318] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4635,7 +5014,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusControlPublicAspmBits" #endif }, - { /* [294] */ + { /* [319] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4650,7 +5029,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetNvlinkPeerIdMask" #endif }, - { /* [295] */ + { /* [320] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4665,7 +5044,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetEomParameters" #endif }, - { /* [296] */ + { /* [321] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4680,7 +5059,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetUphyDlnCfgSpace" #endif }, - { /* [297] */ + { /* [322] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4695,7 +5074,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetEomStatus" #endif }, - { /* [298] */ + { /* [323] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x6210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4710,7 +5089,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPcieReqAtomicsCaps" #endif }, - { /* [299] */ + { /* [324] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x6210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4725,7 +5104,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPcieSupportedGpuAtomics" #endif }, - { /* [300] */ + { /* [325] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4740,7 +5119,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetC2CInfo" #endif }, - { /* [301] */ + { /* [326] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4755,7 +5134,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSysmemAccess" #endif }, - { /* [302] */ + { /* [327] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4770,7 +5149,37 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetC2CErrorInfo" #endif }, - { /* [303] */ + { /* [328] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100200u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBusSetP2pMapping_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100200u) + /*flags=*/ 0x100200u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x2080182eu, + /*paramSize=*/ sizeof(NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdBusSetP2pMapping" +#endif + }, + { /* [329] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100200u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBusUnsetP2pMapping_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100200u) + /*flags=*/ 0x100200u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x2080182fu, + /*paramSize=*/ sizeof(NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdBusUnsetP2pMapping" +#endif + }, + { /* [330] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4785,13 +5194,28 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKPerfBoost" #endif }, - { /* [304] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [331] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdPerfSetPowerstate_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x2080205bu, + /*paramSize=*/ sizeof(NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdPerfSetPowerstate" +#endif + }, + { /* [332] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdPerfRatedTdpGetControl_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) + /*flags=*/ 0x212u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080206eu, /*paramSize=*/ sizeof(NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS), @@ -4800,11 +5224,11 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfRatedTdpGetControl" #endif }, - { /* [305] */ + { /* [333] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdPerfRatedTdpSetControl_a2e9a2, + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdPerfRatedTdpSetControl_DISPATCH, #endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*flags=*/ 0x10u, /*accessRight=*/0x0u, @@ -4815,11 +5239,26 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfRatedTdpSetControl" #endif }, - { /* [306] */ + { /* [334] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdPerfReservePerfmonHw_3f0664, + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdPerfSetAuxPowerState_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20802092u, + /*paramSize=*/ sizeof(NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdPerfSetAuxPowerState" +#endif + }, + { /* [335] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdPerfReservePerfmonHw_DISPATCH, #endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*flags=*/ 0x10u, /*accessRight=*/0x0u, @@ -4830,7 +5269,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfReservePerfmonHw" #endif }, - { /* [307] */ + { /* [336] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4845,7 +5284,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamplesV2" #endif }, - { /* [308] */ + { /* [337] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4860,7 +5299,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcReadVirtualMem" #endif }, - { /* [309] */ + { /* [338] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4875,7 +5314,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcGetErrorCount" #endif }, - { /* [310] */ + { /* [339] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4890,7 +5329,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcSetCleanErrorHistory" #endif }, - { /* [311] */ + { /* [340] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4905,7 +5344,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcGetWatchdogInfo" #endif }, - { /* [312] */ + { /* [341] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4920,7 +5359,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcDisableWatchdog" #endif }, - { /* [313] */ + { /* [342] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4935,7 +5374,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcEnableWatchdog" #endif }, - { /* [314] */ + { /* [343] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4950,7 +5389,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcReleaseWatchdogRequests" #endif }, - { /* [315] */ + { /* [344] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4965,7 +5404,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdSetRcRecovery" #endif }, - { /* [316] */ + { /* [345] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4980,7 +5419,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetRcRecovery" #endif }, - { /* [317] */ + { /* [346] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4995,7 +5434,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcSoftDisableWatchdog" #endif }, - { /* [318] */ + { /* [347] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5010,7 +5449,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdSetRcInfo" #endif }, - { /* [319] */ + { /* [348] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5025,7 +5464,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetRcInfo" #endif }, - { /* [320] */ + { /* [349] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5040,7 +5479,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcGetErrorV2" #endif }, - { /* [321] */ + { /* [350] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5055,7 +5494,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvdGetDumpSize" #endif }, - { /* [322] */ + { /* [351] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5070,7 +5509,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvdGetDump" #endif }, - { /* [323] */ + { /* [352] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5085,7 +5524,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvdGetNocatJournalRpt" #endif }, - { /* [324] */ + { /* [353] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5100,7 +5539,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvdSetNocatJournalData" #endif }, - { /* [325] */ + { /* [354] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5115,7 +5554,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDmaInvalidateTLB" #endif }, - { /* [326] */ + { /* [355] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5130,7 +5569,52 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDmaGetInfo" #endif }, - { /* [327] */ + { /* [356] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdPmgrGetModuleInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) + /*flags=*/ 0xa50u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20802609u, + /*paramSize=*/ sizeof(NV2080_CTRL_PMGR_MODULE_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdPmgrGetModuleInfo" +#endif + }, + { /* [357] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdLpwrDifrCtrl_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20802801u, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdLpwrDifrCtrl" +#endif + }, + { /* [358] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdLpwrDifrPrefetchResponse_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*flags=*/ 0x200u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20802802u, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdLpwrDifrPrefetchResponse" +#endif + }, + { /* [359] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5145,7 +5629,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetCaps" #endif }, - { /* [328] */ + { /* [360] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x211u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5160,7 +5644,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetCePceMask" #endif }, - { /* [329] */ + { /* [361] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5175,7 +5659,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetCapsV2" #endif }, - { /* [330] */ + { /* [362] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5190,7 +5674,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeUpdatePceLceMappings" #endif }, - { /* [331] */ + { /* [363] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5205,13 +5689,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeUpdateClassDB" #endif }, - { /* [332] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe40u) + { /* [364] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100e40u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdCeGetPhysicalCaps_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe40u) - /*flags=*/ 0xe40u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100e40u) + /*flags=*/ 0x100e40u, /*accessRight=*/0x0u, /*methodId=*/ 0x20802a07u, /*paramSize=*/ sizeof(NV2080_CTRL_CE_GET_CAPS_V2_PARAMS), @@ -5220,13 +5704,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetPhysicalCaps" #endif }, - { /* [333] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4200u) + { /* [365] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c0200u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdCeGetFaultMethodBufferSize_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4200u) - /*flags=*/ 0x4200u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c0200u) + /*flags=*/ 0x1c0200u, /*accessRight=*/0x0u, /*methodId=*/ 0x20802a08u, /*paramSize=*/ sizeof(NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS), @@ -5235,7 +5719,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetFaultMethodBufferSize" #endif }, - { /* [334] */ + { /* [366] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5250,13 +5734,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetHubPceMask" #endif }, - { /* [335] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + { /* [367] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdCeGetAllCaps_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) - /*flags=*/ 0x850u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) + /*flags=*/ 0x2850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20802a0au, /*paramSize=*/ sizeof(NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS), @@ -5265,7 +5749,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetAllCaps" #endif }, - { /* [336] */ + { /* [368] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe40u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5280,7 +5764,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetAllPhysicalCaps" #endif }, - { /* [337] */ + { /* [369] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5295,7 +5779,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetNvlinkCaps" #endif }, - { /* [338] */ + { /* [370] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5310,7 +5794,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetNvlinkStatus" #endif }, - { /* [339] */ + { /* [371] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBusGetNvlinkErrInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20803003u, + /*paramSize=*/ sizeof(NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdBusGetNvlinkErrInfo" +#endif + }, + { /* [372] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5325,7 +5824,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetNvlinkCounters" #endif }, - { /* [340] */ + { /* [373] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5340,7 +5839,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdClearNvlinkCounters" #endif }, - { /* [341] */ + { /* [374] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5355,7 +5854,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetLinkFatalErrorCounts" #endif }, - { /* [342] */ + { /* [375] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5370,7 +5869,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSetupEom" #endif }, - { /* [343] */ + { /* [376] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5385,7 +5884,37 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetPowerState" #endif }, - { /* [344] */ + { /* [377] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdNvlinGetLinkFomValues_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20803011u, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdNvlinGetLinkFomValues" +#endif + }, + { /* [378] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdNvlinkGetNvlinkEccErrors_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20803014u, + /*paramSize=*/ sizeof(NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdNvlinkGetNvlinkEccErrors" +#endif + }, + { /* [379] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5400,7 +5929,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkReadTpCounters" #endif }, - { /* [345] */ + { /* [380] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5415,7 +5944,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkEnableNvlinkPeer" #endif }, - { /* [346] */ + { /* [381] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5430,7 +5959,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetLpCounters" #endif }, - { /* [347] */ + { /* [382] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5445,7 +5974,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkCoreCallback" #endif }, - { /* [348] */ + { /* [383] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5460,7 +5989,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetAliEnabled" #endif }, - { /* [349] */ + { /* [384] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5475,7 +6004,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdateRemoteLocalSid" #endif }, - { /* [350] */ + { /* [385] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5490,7 +6019,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdateHshubMux" #endif }, - { /* [351] */ + { /* [386] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5505,7 +6034,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkPreSetupNvlinkPeer" #endif }, - { /* [352] */ + { /* [387] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5520,7 +6049,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkPostSetupNvlinkPeer" #endif }, - { /* [353] */ + { /* [388] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5535,7 +6064,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkRemoveNvlinkMapping" #endif }, - { /* [354] */ + { /* [389] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5550,7 +6079,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSaveRestoreHshubState" #endif }, - { /* [355] */ + { /* [390] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5565,7 +6094,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkProgramBufferready" #endif }, - { /* [356] */ + { /* [391] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5580,7 +6109,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdateCurrentConfig" #endif }, - { /* [357] */ + { /* [392] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5595,7 +6124,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSetLoopbackMode" #endif }, - { /* [358] */ + { /* [393] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5610,7 +6139,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdatePeerLinkMask" #endif }, - { /* [359] */ + { /* [394] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5625,7 +6154,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdateLinkConnection" #endif }, - { /* [360] */ + { /* [395] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5640,7 +6169,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkEnableLinksPostTopology" #endif }, - { /* [361] */ + { /* [396] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5655,7 +6184,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkPreLinkTrainAli" #endif }, - { /* [362] */ + { /* [397] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5670,7 +6199,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetRefreshCounters" #endif }, - { /* [363] */ + { /* [398] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5685,7 +6214,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkClearRefreshCounters" #endif }, - { /* [364] */ + { /* [399] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5700,7 +6229,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetLinkMaskPostRxDet" #endif }, - { /* [365] */ + { /* [400] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5715,7 +6244,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkLinkTrainAli" #endif }, - { /* [366] */ + { /* [401] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5730,7 +6259,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetNvlinkDeviceInfo" #endif }, - { /* [367] */ + { /* [402] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5745,7 +6274,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetIoctrlDeviceInfo" #endif }, - { /* [368] */ + { /* [403] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5760,7 +6289,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkProgramLinkSpeed" #endif }, - { /* [369] */ + { /* [404] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5775,7 +6304,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkAreLinksTrained" #endif }, - { /* [370] */ + { /* [405] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5790,7 +6319,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkResetLinks" #endif }, - { /* [371] */ + { /* [406] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5805,7 +6334,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkDisableDlInterrupts" #endif }, - { /* [372] */ + { /* [407] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5820,7 +6349,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetLinkAndClockInfo" #endif }, - { /* [373] */ + { /* [408] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5835,7 +6364,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSetupNvlinkSysmem" #endif }, - { /* [374] */ + { /* [409] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5850,7 +6379,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkProcessForcedConfigs" #endif }, - { /* [375] */ + { /* [410] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5865,7 +6394,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSyncLaneShutdownProps" #endif }, - { /* [376] */ + { /* [411] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5880,7 +6409,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkEnableSysmemNvlinkAts" #endif }, - { /* [377] */ + { /* [412] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5895,7 +6424,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkHshubGetSysmemNvlinkMask" #endif }, - { /* [378] */ + { /* [413] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5910,13 +6439,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetSetNvswitchFlaAddr" #endif }, - { /* [379] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) + { /* [414] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100201u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdNvlinkSyncLinkMasksAndVbiosInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) - /*flags=*/ 0x201u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100201u) + /*flags=*/ 0x100201u, /*accessRight=*/0x0u, /*methodId=*/ 0x20803039u, /*paramSize=*/ sizeof(NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS), @@ -5925,7 +6454,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSyncLinkMasksAndVbiosInfo" #endif }, - { /* [380] */ + { /* [415] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5940,7 +6469,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkEnableLinks" #endif }, - { /* [381] */ + { /* [416] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5955,7 +6484,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkProcessInitDisabledLinks" #endif }, - { /* [382] */ + { /* [417] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5970,7 +6499,37 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkEomControl" #endif }, - { /* [383] */ + { /* [418] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdNvlinkL1Threshold_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x2080303eu, + /*paramSize=*/ sizeof(NV2080_CTRL_NVLINK_L1_THRESHOLD_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdNvlinkL1Threshold" +#endif + }, + { /* [419] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1240u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdNvlinkInbandSendData_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1240u) + /*flags=*/ 0x1240u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x2080303fu, + /*paramSize=*/ sizeof(NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdNvlinkInbandSendData" +#endif + }, + { /* [420] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5985,7 +6544,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetDmemUsage" #endif }, - { /* [384] */ + { /* [421] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6000,7 +6559,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetEngineArch" #endif }, - { /* [385] */ + { /* [422] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6015,7 +6574,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnUstreamerQueueInfo" #endif }, - { /* [386] */ + { /* [423] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6030,7 +6589,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnUstreamerControlGet" #endif }, - { /* [387] */ + { /* [424] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6045,7 +6604,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnUstreamerControlSet" #endif }, - { /* [388] */ + { /* [425] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6060,7 +6619,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetCtxBufferInfo" #endif }, - { /* [389] */ + { /* [426] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6075,7 +6634,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetCtxBufferSize" #endif }, - { /* [390] */ + { /* [427] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6090,7 +6649,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEccGetClientExposedCounters" #endif }, - { /* [391] */ + { /* [428] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6105,7 +6664,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaRange" #endif }, - { /* [392] */ + { /* [429] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6120,7 +6679,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaSetupInstanceMemBlock" #endif }, - { /* [393] */ + { /* [430] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6135,7 +6694,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaGetRange" #endif }, - { /* [394] */ + { /* [431] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6150,7 +6709,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaGetFabricMemStats" #endif }, - { /* [395] */ + { /* [432] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x211u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6165,7 +6724,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGspGetFeatures" #endif }, - { /* [396] */ + { /* [433] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6180,7 +6739,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGrmgrGetGrFsInfo" #endif }, - { /* [397] */ + { /* [434] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x3u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6195,7 +6754,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixGc6BlockerRefCnt" #endif }, - { /* [398] */ + { /* [435] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6210,7 +6769,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixAllowDisallowGcoff" #endif }, - { /* [399] */ + { /* [436] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6225,7 +6784,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixAudioDynamicPower" #endif }, - { /* [400] */ + { /* [437] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6240,7 +6799,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixVidmemPersistenceStatus" #endif }, - { /* [401] */ + { /* [438] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6255,7 +6814,172 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixUpdateTgpStatus" #endif }, - { /* [402] */ + { /* [439] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20804001u, + /*paramSize=*/ sizeof(NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask" +#endif + }, + { /* [440] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20804002u, + /*paramSize=*/ sizeof(NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask" +#endif + }, + { /* [441] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20804003u, + /*paramSize=*/ sizeof(NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType" +#endif + }, + { /* [442] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdVgpuMgrInternalEnumerateVgpuPerPgpu_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20804004u, + /*paramSize=*/ sizeof(NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalEnumerateVgpuPerPgpu" +#endif + }, + { /* [443] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdVgpuMgrInternalClearGuestVmInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20804005u, + /*paramSize=*/ sizeof(NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalClearGuestVmInfo" +#endif + }, + { /* [444] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdVgpuMgrInternalGetVgpuFbUsage_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20804006u, + /*paramSize=*/ sizeof(NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetVgpuFbUsage" +#endif + }, + { /* [445] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdVgpuMgrInternalSetVgpuEncoderCapacity_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20804007u, + /*paramSize=*/ sizeof(NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalSetVgpuEncoderCapacity" +#endif + }, + { /* [446] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdVgpuMgrInternalCleanupGspVgpuPluginResources_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20804008u, + /*paramSize=*/ sizeof(NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalCleanupGspVgpuPluginResources" +#endif + }, + { /* [447] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdVgpuMgrInternalGetPgpuFsEncoding_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20804009u, + /*paramSize=*/ sizeof(NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetPgpuFsEncoding" +#endif + }, + { /* [448] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdVgpuMgrInternalGetPgpuMigrationSupport_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x2080400au, + /*paramSize=*/ sizeof(NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetPgpuMigrationSupport" +#endif + }, + { /* [449] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdVgpuMgrInternalSetVgpuMgrConfig_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x2080400bu, + /*paramSize=*/ sizeof(NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalSetVgpuMgrConfig" +#endif + }, + { /* [450] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6270,7 +6994,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetAvailableHshubMask" #endif }, - { /* [403] */ + { /* [451] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6290,7 +7014,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic const struct NVOC_EXPORT_INFO __nvoc_export_info_Subdevice = { - /*numEntries=*/ 404, + /*numEntries=*/ 452, /*pExportEntries=*/ __nvoc_exported_method_def_Subdevice }; @@ -6354,6 +7078,10 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdBiosGetInfoV2__ = &subdeviceCtrlCmdBiosGetInfoV2_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__subdeviceCtrlCmdBiosGetNbsiV2__ = &subdeviceCtrlCmdBiosGetNbsiV2_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__subdeviceCtrlCmdBiosGetSKUInfo__ = &subdeviceCtrlCmdBiosGetSKUInfo_IMPL; #endif @@ -6518,6 +7246,22 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdBusSysmemAccess__ = &subdeviceCtrlCmdBusSysmemAccess_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100200u) + pThis->__subdeviceCtrlCmdBusSetP2pMapping__ = &subdeviceCtrlCmdBusSetP2pMapping_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100200u) + pThis->__subdeviceCtrlCmdBusUnsetP2pMapping__ = &subdeviceCtrlCmdBusUnsetP2pMapping_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__subdeviceCtrlCmdGetNvlinkCounters__ = &subdeviceCtrlCmdGetNvlinkCounters_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + pThis->__subdeviceCtrlCmdClearNvlinkCounters__ = &subdeviceCtrlCmdClearNvlinkCounters_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdBusGetNvlinkCaps__ = &subdeviceCtrlCmdBusGetNvlinkCaps_IMPL; #endif @@ -6527,11 +7271,15 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - pThis->__subdeviceCtrlCmdGetNvlinkCounters__ = &subdeviceCtrlCmdGetNvlinkCounters_IMPL; + pThis->__subdeviceCtrlCmdBusGetNvlinkErrInfo__ = &subdeviceCtrlCmdBusGetNvlinkErrInfo_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) - pThis->__subdeviceCtrlCmdClearNvlinkCounters__ = &subdeviceCtrlCmdClearNvlinkCounters_IMPL; + pThis->__subdeviceCtrlCmdNvlinGetLinkFomValues__ = &subdeviceCtrlCmdNvlinGetLinkFomValues_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + pThis->__subdeviceCtrlCmdNvlinkGetNvlinkEccErrors__ = &subdeviceCtrlCmdNvlinkGetNvlinkEccErrors_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) @@ -6686,7 +7434,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdNvlinkGetSetNvswitchFlaAddr__ = &subdeviceCtrlCmdNvlinkGetSetNvswitchFlaAddr_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100201u) pThis->__subdeviceCtrlCmdNvlinkSyncLinkMasksAndVbiosInfo__ = &subdeviceCtrlCmdNvlinkSyncLinkMasksAndVbiosInfo_IMPL; #endif @@ -6698,10 +7446,18 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdNvlinkProcessInitDisabledLinks__ = &subdeviceCtrlCmdNvlinkProcessInitDisabledLinks_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1240u) + pThis->__subdeviceCtrlCmdNvlinkInbandSendData__ = &subdeviceCtrlCmdNvlinkInbandSendData_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) pThis->__subdeviceCtrlCmdNvlinkEomControl__ = &subdeviceCtrlCmdNvlinkEomControl_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + pThis->__subdeviceCtrlCmdNvlinkL1Threshold__ = &subdeviceCtrlCmdNvlinkL1Threshold_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__subdeviceCtrlCmdI2cReadBuffer__ = &subdeviceCtrlCmdI2cReadBuffer_IMPL; #endif @@ -6726,17 +7482,33 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamplesV2__ = &subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamplesV2_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) pThis->__subdeviceCtrlCmdPerfRatedTdpGetControl__ = &subdeviceCtrlCmdPerfRatedTdpGetControl_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - pThis->__subdeviceCtrlCmdPerfRatedTdpSetControl__ = &subdeviceCtrlCmdPerfRatedTdpSetControl_a2e9a2; -#endif + // Hal function -- subdeviceCtrlCmdPerfRatedTdpSetControl + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + pThis->__subdeviceCtrlCmdPerfRatedTdpSetControl__ = &subdeviceCtrlCmdPerfRatedTdpSetControl_KERNEL; + } -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - pThis->__subdeviceCtrlCmdPerfReservePerfmonHw__ = &subdeviceCtrlCmdPerfReservePerfmonHw_3f0664; -#endif + // Hal function -- subdeviceCtrlCmdPerfReservePerfmonHw + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + pThis->__subdeviceCtrlCmdPerfReservePerfmonHw__ = &subdeviceCtrlCmdPerfReservePerfmonHw_KERNEL; + } + + // Hal function -- subdeviceCtrlCmdPerfSetAuxPowerState + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + pThis->__subdeviceCtrlCmdPerfSetAuxPowerState__ = &subdeviceCtrlCmdPerfSetAuxPowerState_KERNEL; + } + + // Hal function -- subdeviceCtrlCmdPerfSetPowerstate + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + pThis->__subdeviceCtrlCmdPerfSetPowerstate__ = &subdeviceCtrlCmdPerfSetPowerstate_KERNEL; + } #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) pThis->__subdeviceCtrlCmdKPerfBoost__ = &subdeviceCtrlCmdKPerfBoost_IMPL; @@ -6762,6 +7534,10 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdFbGetHeapReservationSize__ = &subdeviceCtrlCmdFbGetHeapReservationSize_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) + pThis->__subdeviceCtrlCmdInternalMemmgrGetVgpuHostRmReservedFb__ = &subdeviceCtrlCmdInternalMemmgrGetVgpuHostRmReservedFb_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdFbGetInfo__ = &subdeviceCtrlCmdFbGetInfo_IMPL; #endif @@ -6942,10 +7718,14 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdFifoGetUserdLocation__ = &subdeviceCtrlCmdFifoGetUserdLocation_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2200u) pThis->__subdeviceCtrlCmdFifoGetDeviceInfoTable__ = &subdeviceCtrlCmdFifoGetDeviceInfoTable_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) + pThis->__subdeviceCtrlCmdFifoSetupVfZombieSubctxPdb__ = &subdeviceCtrlCmdFifoSetupVfZombieSubctxPdb_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) pThis->__subdeviceCtrlCmdFifoClearFaultedBit__ = &subdeviceCtrlCmdFifoClearFaultedBit_IMPL; #endif @@ -6966,6 +7746,10 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdInternalFifoGetNumChannels__ = &subdeviceCtrlCmdInternalFifoGetNumChannels_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + pThis->__subdeviceCtrlCmdFifoGetAllocatedChannels__ = &subdeviceCtrlCmdFifoGetAllocatedChannels_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) pThis->__subdeviceCtrlCmdKGrGetInfo__ = &subdeviceCtrlCmdKGrGetInfo_IMPL; #endif @@ -7042,11 +7826,11 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdKGrGetCtxBufferSize__ = &subdeviceCtrlCmdKGrGetCtxBufferSize_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x80000u) pThis->__subdeviceCtrlCmdKGrGetCtxBufferInfo__ = &subdeviceCtrlCmdKGrGetCtxBufferInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x80000u) pThis->__subdeviceCtrlCmdKGrGetCtxBufferPtes__ = &subdeviceCtrlCmdKGrGetCtxBufferPtes_IMPL; #endif @@ -7130,7 +7914,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdKGrGetGfxGpcAndTpcInfo__ = &subdeviceCtrlCmdKGrGetGfxGpcAndTpcInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) pThis->__subdeviceCtrlCmdKGrInternalStaticGetInfo__ = &subdeviceCtrlCmdKGrInternalStaticGetInfo_IMPL; #endif @@ -7138,43 +7922,43 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdKGrInternalStaticGetCaps__ = &subdeviceCtrlCmdKGrInternalStaticGetCaps_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) pThis->__subdeviceCtrlCmdKGrInternalStaticGetGlobalSmOrder__ = &subdeviceCtrlCmdKGrInternalStaticGetGlobalSmOrder_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) pThis->__subdeviceCtrlCmdKGrInternalStaticGetFloorsweepingMasks__ = &subdeviceCtrlCmdKGrInternalStaticGetFloorsweepingMasks_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) pThis->__subdeviceCtrlCmdKGrInternalStaticGetPpcMasks__ = &subdeviceCtrlCmdKGrInternalStaticGetPpcMasks_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) pThis->__subdeviceCtrlCmdKGrInternalStaticGetZcullInfo__ = &subdeviceCtrlCmdKGrInternalStaticGetZcullInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) pThis->__subdeviceCtrlCmdKGrInternalStaticGetRopInfo__ = &subdeviceCtrlCmdKGrInternalStaticGetRopInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) pThis->__subdeviceCtrlCmdKGrInternalStaticGetContextBuffersInfo__ = &subdeviceCtrlCmdKGrInternalStaticGetContextBuffersInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) pThis->__subdeviceCtrlCmdKGrInternalStaticGetSmIssueRateModifier__ = &subdeviceCtrlCmdKGrInternalStaticGetSmIssueRateModifier_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) pThis->__subdeviceCtrlCmdKGrInternalStaticGetFecsRecordSize__ = &subdeviceCtrlCmdKGrInternalStaticGetFecsRecordSize_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) pThis->__subdeviceCtrlCmdKGrInternalStaticGetFecsTraceDefines__ = &subdeviceCtrlCmdKGrInternalStaticGetFecsTraceDefines_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) pThis->__subdeviceCtrlCmdKGrInternalStaticGetPdbProperties__ = &subdeviceCtrlCmdKGrInternalStaticGetPdbProperties_IMPL; #endif @@ -7202,11 +7986,11 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdGpuSetOptimusInfo__ = &subdeviceCtrlCmdGpuSetOptimusInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa12u) pThis->__subdeviceCtrlCmdGpuGetNameString__ = &subdeviceCtrlCmdGpuGetNameString_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4a10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4a12u) pThis->__subdeviceCtrlCmdGpuGetShortNameString__ = &subdeviceCtrlCmdGpuGetShortNameString_IMPL; #endif @@ -7286,6 +8070,10 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdGpuExecRegOps__ = &subdeviceCtrlCmdGpuExecRegOps_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__subdeviceCtrlCmdGpuMigratableOps__ = &subdeviceCtrlCmdGpuMigratableOps_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__subdeviceCtrlCmdGpuQueryMode__ = &subdeviceCtrlCmdGpuQueryMode_IMPL; #endif @@ -7306,6 +8094,10 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdGpuQueryEccStatus__ = &subdeviceCtrlCmdGpuQueryEccStatus_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4210u) + pThis->__subdeviceCtrlCmdGpuGetChipDetails__ = &subdeviceCtrlCmdGpuGetChipDetails_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4210u) pThis->__subdeviceCtrlCmdGpuGetOEMBoardInfo__ = &subdeviceCtrlCmdGpuGetOEMBoardInfo_IMPL; #endif @@ -7333,16 +8125,25 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) pThis->__subdeviceCtrlCmdGpuReleaseComputeModeReservation__ = &subdeviceCtrlCmdGpuReleaseComputeModeReservation_IMPL; #endif +} -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) +static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) { + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x142204u) pThis->__subdeviceCtrlCmdGpuInitializeCtx__ = &subdeviceCtrlCmdGpuInitializeCtx_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u) pThis->__subdeviceCtrlCmdGpuPromoteCtx__ = &subdeviceCtrlCmdGpuPromoteCtx_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2200u) pThis->__subdeviceCtrlCmdGpuEvictCtx__ = &subdeviceCtrlCmdGpuEvictCtx_IMPL; #endif @@ -7393,15 +8194,6 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) pThis->__subdeviceCtrlCmdGpuReportNonReplayableFault__ = &subdeviceCtrlCmdGpuReportNonReplayableFault_IMPL; #endif -} - -static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) { - RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; - const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; - PORT_UNREFERENCED_VARIABLE(pThis); - PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); - PORT_UNREFERENCED_VARIABLE(rmVariantHal); - PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) pThis->__subdeviceCtrlCmdGpuGetEngineFaultInfo__ = &subdeviceCtrlCmdGpuGetEngineFaultInfo_IMPL; @@ -7419,6 +8211,10 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdGpuGetMaxSupportedPageSize__ = &subdeviceCtrlCmdGpuGetMaxSupportedPageSize_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) + pThis->__subdeviceCtrlCmdGpuHandleVfPriFault__ = &subdeviceCtrlCmdGpuHandleVfPriFault_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) pThis->__subdeviceCtrlCmdGpuSetComputePolicyConfig__ = &subdeviceCtrlCmdGpuSetComputePolicyConfig_IMPL; #endif @@ -7431,10 +8227,26 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdValidateMemMapRequest__ = &subdeviceCtrlCmdValidateMemMapRequest_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__subdeviceCtrlCmdGpuGetGfid__ = &subdeviceCtrlCmdGpuGetGfid_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + pThis->__subdeviceCtrlCmdUpdateGfidP2pCapability__ = &subdeviceCtrlCmdUpdateGfidP2pCapability_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x12u) pThis->__subdeviceCtrlCmdGpuGetEngineLoadTimes__ = &subdeviceCtrlCmdGpuGetEngineLoadTimes_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__subdeviceCtrlCmdGetP2pCaps__ = &subdeviceCtrlCmdGetP2pCaps_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) + pThis->__subdeviceCtrlCmdGetGpuFabricProbeInfo__ = &subdeviceCtrlCmdGetGpuFabricProbeInfo_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__subdeviceCtrlCmdEventSetTrigger__ = &subdeviceCtrlCmdEventSetTrigger_IMPL; #endif @@ -7555,15 +8367,23 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdNvdSetNocatJournalData__ = &subdeviceCtrlCmdNvdSetNocatJournalData_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) + pThis->__subdeviceCtrlCmdPmgrGetModuleInfo__ = &subdeviceCtrlCmdPmgrGetModuleInfo_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + pThis->__subdeviceCtrlCmdLpwrDifrPrefetchResponse__ = &subdeviceCtrlCmdLpwrDifrPrefetchResponse_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + pThis->__subdeviceCtrlCmdLpwrDifrCtrl__ = &subdeviceCtrlCmdLpwrDifrCtrl_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdCeGetCaps__ = &subdeviceCtrlCmdCeGetCaps_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) - pThis->__subdeviceCtrlCmdCeGetCapsV2__ = &subdeviceCtrlCmdCeGetCapsV2_IMPL; -#endif - -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) pThis->__subdeviceCtrlCmdCeGetAllCaps__ = &subdeviceCtrlCmdCeGetAllCaps_IMPL; #endif @@ -7575,6 +8395,10 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdCeUpdatePceLceMappings__ = &subdeviceCtrlCmdCeUpdatePceLceMappings_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + pThis->__subdeviceCtrlCmdCeGetCapsV2__ = &subdeviceCtrlCmdCeGetCapsV2_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__subdeviceCtrlCmdFlcnGetDmemUsage__ = &subdeviceCtrlCmdFlcnGetDmemUsage_IMPL; #endif @@ -7787,14 +8611,6 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdInternalGetSmcMode__ = &subdeviceCtrlCmdInternalGetSmcMode_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - pThis->__subdeviceCtrlCmdInternalBusBindLocalGfidForP2p__ = &subdeviceCtrlCmdInternalBusBindLocalGfidForP2p_IMPL; -#endif - -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - pThis->__subdeviceCtrlCmdInternalBusBindRemoteGfidForP2p__ = &subdeviceCtrlCmdInternalBusBindRemoteGfidForP2p_IMPL; -#endif - #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) pThis->__subdeviceCtrlCmdInternalBusFlushWithSysmembar__ = &subdeviceCtrlCmdInternalBusFlushWithSysmembar_IMPL; #endif @@ -7839,7 +8655,11 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer__ = &subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe40u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalGmmuCopyReservedSplitGVASpacePdesServer__ = &subdeviceCtrlCmdInternalGmmuCopyReservedSplitGVASpacePdesServer_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100e40u) pThis->__subdeviceCtrlCmdCeGetPhysicalCaps__ = &subdeviceCtrlCmdCeGetPhysicalCaps_IMPL; #endif @@ -7851,7 +8671,7 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdCeUpdateClassDB__ = &subdeviceCtrlCmdCeUpdateClassDB_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4200u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c0200u) pThis->__subdeviceCtrlCmdCeGetFaultMethodBufferSize__ = &subdeviceCtrlCmdCeGetFaultMethodBufferSize_IMPL; #endif @@ -7907,6 +8727,10 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdInternalPerfCfControllerSetMaxVGpuVMCount__ = &subdeviceCtrlCmdInternalPerfCfControllerSetMaxVGpuVMCount_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalPerfGetAuxPowerState__ = &subdeviceCtrlCmdInternalPerfGetAuxPowerState_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) pThis->__subdeviceCtrlCmdBifGetStaticInfo__ = &subdeviceCtrlCmdBifGetStaticInfo_IMPL; #endif @@ -7955,6 +8779,14 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdInternalNvlinkGetTotalNumLinksPerIoctrl__ = &subdeviceCtrlCmdInternalNvlinkGetTotalNumLinksPerIoctrl_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalSetP2pCaps__ = &subdeviceCtrlCmdInternalSetP2pCaps_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalRemoveP2pCaps__ = &subdeviceCtrlCmdInternalRemoveP2pCaps_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) pThis->__subdeviceCtrlCmdInternalGetPcieP2pCaps__ = &subdeviceCtrlCmdInternalGetPcieP2pCaps_IMPL; #endif @@ -7963,6 +8795,94 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdInternalGetCoherentFbApertureSize__ = &subdeviceCtrlCmdInternalGetCoherentFbApertureSize_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalInitGpuIntr__ = &subdeviceCtrlCmdInternalInitGpuIntr_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalGsyncOptimizeTiming__ = &subdeviceCtrlCmdInternalGsyncOptimizeTiming_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalGsyncGetDisplayIds__ = &subdeviceCtrlCmdInternalGsyncGetDisplayIds_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalGsyncSetStereoSync__ = &subdeviceCtrlCmdInternalGsyncSetStereoSync_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalGsyncGetVactiveLines__ = &subdeviceCtrlCmdInternalGsyncGetVactiveLines_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalGsyncIsDisplayIdValid__ = &subdeviceCtrlCmdInternalGsyncIsDisplayIdValid_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalGsyncSetOrRestoreGpioRasterSync__ = &subdeviceCtrlCmdInternalGsyncSetOrRestoreGpioRasterSync_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalFbsrInit__ = &subdeviceCtrlCmdInternalFbsrInit_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalFbsrSendRegionInfo__ = &subdeviceCtrlCmdInternalFbsrSendRegionInfo_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalPostInitBrightcStateLoad__ = &subdeviceCtrlCmdInternalPostInitBrightcStateLoad_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit__ = &subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask__ = &subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask__ = &subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType__ = &subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdVgpuMgrInternalEnumerateVgpuPerPgpu__ = &subdeviceCtrlCmdVgpuMgrInternalEnumerateVgpuPerPgpu_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdVgpuMgrInternalClearGuestVmInfo__ = &subdeviceCtrlCmdVgpuMgrInternalClearGuestVmInfo_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdVgpuMgrInternalGetVgpuFbUsage__ = &subdeviceCtrlCmdVgpuMgrInternalGetVgpuFbUsage_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdVgpuMgrInternalSetVgpuEncoderCapacity__ = &subdeviceCtrlCmdVgpuMgrInternalSetVgpuEncoderCapacity_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdVgpuMgrInternalCleanupGspVgpuPluginResources__ = &subdeviceCtrlCmdVgpuMgrInternalCleanupGspVgpuPluginResources_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdVgpuMgrInternalGetPgpuFsEncoding__ = &subdeviceCtrlCmdVgpuMgrInternalGetPgpuFsEncoding_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdVgpuMgrInternalGetPgpuMigrationSupport__ = &subdeviceCtrlCmdVgpuMgrInternalGetPgpuMigrationSupport_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdVgpuMgrInternalSetVgpuMgrConfig__ = &subdeviceCtrlCmdVgpuMgrInternalSetVgpuMgrConfig_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) pThis->__subdeviceCtrlCmdGetAvailableHshubMask__ = &subdeviceCtrlCmdGetAvailableHshubMask_IMPL; #endif @@ -7975,6 +8895,10 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdCcuUnmap__ = &subdeviceCtrlCmdCcuUnmap_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdCcuSetStreamState__ = &subdeviceCtrlCmdCcuSetStreamState_IMPL; +#endif + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__resPreDestruct__ = &__nvoc_thunk_Subdevice_resPreDestruct; pThis->__nvoc_base_GpuResource.__gpuresInternalControlForward__ = &__nvoc_thunk_Subdevice_gpuresInternalControlForward; @@ -8021,6 +8945,8 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCanCopy__ = &__nvoc_thunk_RsResource_subdeviceCanCopy; + pThis->__subdeviceIsDuplicate__ = &__nvoc_thunk_RsResource_subdeviceIsDuplicate; + pThis->__subdeviceGetNotificationListPtr__ = &__nvoc_thunk_Notifier_subdeviceGetNotificationListPtr; pThis->__subdeviceGetNotificationShare__ = &__nvoc_thunk_Notifier_subdeviceGetNotificationShare; diff --git a/src/nvidia/generated/g_subdevice_nvoc.h b/src/nvidia/generated/g_subdevice_nvoc.h index 3192cccf9..8120bce83 100644 --- a/src/nvidia/generated/g_subdevice_nvoc.h +++ b/src/nvidia/generated/g_subdevice_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -43,23 +43,8 @@ extern "C" { #include "gpu/gpu_halspec.h" #include "class/cl2080.h" -#include "ctrl/ctrl0000/ctrl0000system.h" #include "ctrl/ctrl2080.h" // rmcontrol parameters -#ifndef NV2080_NOTIFIERS_CE_IDX -// TODO these need to be moved to cl2080.h -#define NV2080_NOTIFIERS_CE_IDX(i) ((i) - NV2080_NOTIFIERS_CE0) -#define NV2080_NOTIFIERS_NVENC_IDX(i) ((i) - NV2080_NOTIFIERS_NVENC0) -#define NV2080_NOTIFIERS_NVDEC_IDX(i) ((i) - NV2080_NOTIFIERS_NVDEC0) -#define NV2080_NOTIFIERS_GR_IDX(i) ((i) - NV2080_NOTIFIERS_GR0) -#endif - -#define NV2080_ENGINE_RANGE_GR() rangeMake(NV2080_ENGINE_TYPE_GR(0), NV2080_ENGINE_TYPE_GR(NV2080_ENGINE_TYPE_GR_SIZE - 1)) -#define NV2080_ENGINE_RANGE_COPY() rangeMake(NV2080_ENGINE_TYPE_COPY(0), NV2080_ENGINE_TYPE_COPY(NV2080_ENGINE_TYPE_COPY_SIZE - 1)) -#define NV2080_ENGINE_RANGE_NVDEC() rangeMake(NV2080_ENGINE_TYPE_NVDEC(0), NV2080_ENGINE_TYPE_NVDEC(NV2080_ENGINE_TYPE_NVDEC_SIZE - 1)) -#define NV2080_ENGINE_RANGE_NVENC() rangeMake(NV2080_ENGINE_TYPE_NVENC(0), NV2080_ENGINE_TYPE_NVENC(NV2080_ENGINE_TYPE_NVENC_SIZE - 1)) -#define NV2080_ENGINE_RANGE_NVJPEG() rangeMake(NV2080_ENGINE_TYPE_NVJPEG(0), NV2080_ENGINE_TYPE_NVJPEG(NV2080_ENGINE_TYPE_NVJPEG_SIZE - 1)) - struct Device; #ifndef __NVOC_CLASS_Device_TYPEDEF__ @@ -135,6 +120,7 @@ struct Subdevice { NV_STATUS (*__subdeviceInternalControlForward__)(struct Subdevice *, NvU32, void *, NvU32); NV_STATUS (*__subdeviceControlFilter__)(struct Subdevice *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__subdeviceCtrlCmdBiosGetInfoV2__)(struct Subdevice *, NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdBiosGetNbsiV2__)(struct Subdevice *, NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdBiosGetSKUInfo__)(struct Subdevice *, NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdBiosGetPostTime__)(struct Subdevice *, NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdBiosGetUefiSupport__)(struct Subdevice *, NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS *); @@ -176,10 +162,15 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdBusGetC2CInfo__)(struct Subdevice *, NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdBusGetC2CErrorInfo__)(struct Subdevice *, NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdBusSysmemAccess__)(struct Subdevice *, NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS *); - NV_STATUS (*__subdeviceCtrlCmdBusGetNvlinkCaps__)(struct Subdevice *, NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS *); - NV_STATUS (*__subdeviceCtrlCmdBusGetNvlinkStatus__)(struct Subdevice *, NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdBusSetP2pMapping__)(struct Subdevice *, NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdBusUnsetP2pMapping__)(struct Subdevice *, NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGetNvlinkCounters__)(struct Subdevice *, NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdClearNvlinkCounters__)(struct Subdevice *, NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdBusGetNvlinkCaps__)(struct Subdevice *, NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdBusGetNvlinkStatus__)(struct Subdevice *, NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdBusGetNvlinkErrInfo__)(struct Subdevice *, NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdNvlinGetLinkFomValues__)(struct Subdevice *, NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdNvlinkGetNvlinkEccErrors__)(struct Subdevice *, NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdNvlinkGetLinkFatalErrorCounts__)(struct Subdevice *, NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdNvlinkSetupEom__)(struct Subdevice *, NV2080_CTRL_CMD_NVLINK_SETUP_EOM_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdNvlinkGetPowerState__)(struct Subdevice *, NV2080_CTRL_NVLINK_GET_POWER_STATE_PARAMS *); @@ -221,7 +212,9 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdNvlinkSyncLinkMasksAndVbiosInfo__)(struct Subdevice *, NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdNvlinkEnableLinks__)(struct Subdevice *); NV_STATUS (*__subdeviceCtrlCmdNvlinkProcessInitDisabledLinks__)(struct Subdevice *, NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdNvlinkInbandSendData__)(struct Subdevice *, NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdNvlinkEomControl__)(struct Subdevice *, NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdNvlinkL1Threshold__)(struct Subdevice *, NV2080_CTRL_NVLINK_L1_THRESHOLD_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdI2cReadBuffer__)(struct Subdevice *, NV2080_CTRL_I2C_READ_BUFFER_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdI2cWriteBuffer__)(struct Subdevice *, NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdI2cReadReg__)(struct Subdevice *, NV2080_CTRL_I2C_RW_REG_PARAMS *); @@ -231,12 +224,15 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdPerfRatedTdpGetControl__)(struct Subdevice *, NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdPerfRatedTdpSetControl__)(struct Subdevice *, NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdPerfReservePerfmonHw__)(struct Subdevice *, NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdPerfSetAuxPowerState__)(struct Subdevice *, NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdPerfSetPowerstate__)(struct Subdevice *, NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdKPerfBoost__)(struct Subdevice *, NV2080_CTRL_PERF_BOOST_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFbGetFBRegionInfo__)(struct Subdevice *, NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFbGetBar1Offset__)(struct Subdevice *, NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFbIsKind__)(struct Subdevice *, NV2080_CTRL_FB_IS_KIND_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFbGetMemAlignment__)(struct Subdevice *, NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFbGetHeapReservationSize__)(struct Subdevice *, NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalMemmgrGetVgpuHostRmReservedFb__)(struct Subdevice *, NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFbGetInfo__)(struct Subdevice *, NV2080_CTRL_FB_GET_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFbGetInfoV2__)(struct Subdevice *, NV2080_CTRL_FB_GET_INFO_V2_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFbGetCarveoutAddressInfo__)(struct Subdevice *, NV2080_CTRL_FB_GET_SYSTEM_CARVEOUT_ADDRESS_SPACE_INFO *); @@ -283,11 +279,13 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdFifoGetChannelMemInfo__)(struct Subdevice *, NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFifoGetUserdLocation__)(struct Subdevice *, NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFifoGetDeviceInfoTable__)(struct Subdevice *, NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdFifoSetupVfZombieSubctxPdb__)(struct Subdevice *, NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFifoClearFaultedBit__)(struct Subdevice *, NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFifoRunlistSetSchedPolicy__)(struct Subdevice *, NV2080_CTRL_FIFO_RUNLIST_SET_SCHED_POLICY_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFifoUpdateChannelInfo__)(struct Subdevice *, NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalFifoPromoteRunlistBuffers__)(struct Subdevice *, NV2080_CTRL_INTERNAL_FIFO_PROMOTE_RUNLIST_BUFFERS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalFifoGetNumChannels__)(struct Subdevice *, NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdFifoGetAllocatedChannels__)(struct Subdevice *, NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdKGrGetInfo__)(struct Subdevice *, NV2080_CTRL_GR_GET_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdKGrGetInfoV2__)(struct Subdevice *, NV2080_CTRL_GR_GET_INFO_V2_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdKGrGetCapsV2__)(struct Subdevice *, NV2080_CTRL_GR_GET_CAPS_V2_PARAMS *); @@ -368,11 +366,13 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdGpuGetFermiZcullInfo__)(struct Subdevice *, NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuGetPesInfo__)(struct Subdevice *, NV2080_CTRL_GPU_GET_PES_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuExecRegOps__)(struct Subdevice *, NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdGpuMigratableOps__)(struct Subdevice *, NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuQueryMode__)(struct Subdevice *, NV2080_CTRL_GPU_QUERY_MODE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuGetInforomImageVersion__)(struct Subdevice *, NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuGetInforomObjectVersion__)(struct Subdevice *, NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuQueryInforomEccSupport__)(struct Subdevice *); NV_STATUS (*__subdeviceCtrlCmdGpuQueryEccStatus__)(struct Subdevice *, NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdGpuGetChipDetails__)(struct Subdevice *, NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuGetOEMBoardInfo__)(struct Subdevice *, NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuGetOEMInfo__)(struct Subdevice *, NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuHandleGpuSR__)(struct Subdevice *); @@ -399,10 +399,15 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdGpuGetEngineRunlistPriBase__)(struct Subdevice *, NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuGetHwEngineId__)(struct Subdevice *, NV2080_CTRL_GPU_GET_HW_ENGINE_ID_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuGetMaxSupportedPageSize__)(struct Subdevice *, NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdGpuHandleVfPriFault__)(struct Subdevice *, NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuSetComputePolicyConfig__)(struct Subdevice *, NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuGetComputePolicyConfig__)(struct Subdevice *, NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdValidateMemMapRequest__)(struct Subdevice *, NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdGpuGetGfid__)(struct Subdevice *, NV2080_CTRL_GPU_GET_GFID_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdUpdateGfidP2pCapability__)(struct Subdevice *, NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuGetEngineLoadTimes__)(struct Subdevice *, NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdGetP2pCaps__)(struct Subdevice *, NV2080_CTRL_GET_P2P_CAPS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdGetGpuFabricProbeInfo__)(struct Subdevice *, NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdEventSetTrigger__)(struct Subdevice *); NV_STATUS (*__subdeviceCtrlCmdEventSetTriggerFifo__)(struct Subdevice *, NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdEventSetNotification__)(struct Subdevice *, NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS *); @@ -433,11 +438,14 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdNvdGetDump__)(struct Subdevice *, NV2080_CTRL_NVD_GET_DUMP_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdNvdGetNocatJournalRpt__)(struct Subdevice *, NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdNvdSetNocatJournalData__)(struct Subdevice *, NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdPmgrGetModuleInfo__)(struct Subdevice *, NV2080_CTRL_PMGR_MODULE_INFO_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdLpwrDifrPrefetchResponse__)(struct Subdevice *, NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdLpwrDifrCtrl__)(struct Subdevice *, NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdCeGetCaps__)(struct Subdevice *, NV2080_CTRL_CE_GET_CAPS_PARAMS *); - NV_STATUS (*__subdeviceCtrlCmdCeGetCapsV2__)(struct Subdevice *, NV2080_CTRL_CE_GET_CAPS_V2_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdCeGetAllCaps__)(struct Subdevice *, NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdCeGetCePceMask__)(struct Subdevice *, NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdCeUpdatePceLceMappings__)(struct Subdevice *, NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdCeGetCapsV2__)(struct Subdevice *, NV2080_CTRL_CE_GET_CAPS_V2_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFlcnGetDmemUsage__)(struct Subdevice *, NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFlcnGetEngineArch__)(struct Subdevice *, NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFlcnUstreamerQueueInfo__)(struct Subdevice *, NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS *); @@ -491,8 +499,6 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdInternalGetConstructedFalconInfo__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalRecoverAllComputeContexts__)(struct Subdevice *); NV_STATUS (*__subdeviceCtrlCmdInternalGetSmcMode__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS *); - NV_STATUS (*__subdeviceCtrlCmdInternalBusBindLocalGfidForP2p__)(struct Subdevice *, NV2080_CTRL_INTERNAL_BUS_BIND_LOCAL_GFID_FOR_P2P_PARAMS *); - NV_STATUS (*__subdeviceCtrlCmdInternalBusBindRemoteGfidForP2p__)(struct Subdevice *, NV2080_CTRL_INTERNAL_BUS_BIND_REMOTE_GFID_FOR_P2P_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalBusFlushWithSysmembar__)(struct Subdevice *); NV_STATUS (*__subdeviceCtrlCmdInternalBusSetupP2pMailboxLocal__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalBusSetupP2pMailboxRemote__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS *); @@ -504,6 +510,7 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdInternalGmmuUnregisterFaultBuffer__)(struct Subdevice *); NV_STATUS (*__subdeviceCtrlCmdInternalGmmuRegisterClientShadowFaultBuffer__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer__)(struct Subdevice *); + NV_STATUS (*__subdeviceCtrlCmdInternalGmmuCopyReservedSplitGVASpacePdesServer__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdCeGetPhysicalCaps__)(struct Subdevice *, NV2080_CTRL_CE_GET_CAPS_V2_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdCeGetAllPhysicalCaps__)(struct Subdevice *, NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdCeUpdateClassDB__)(struct Subdevice *, NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS *); @@ -521,6 +528,7 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdInternalPerfPerfmonClientReservationCheck__)(struct Subdevice *, NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_CHECK_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalPerfPerfmonClientReservationSet__)(struct Subdevice *, NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalPerfCfControllerSetMaxVGpuVMCount__)(struct Subdevice *, NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalPerfGetAuxPowerState__)(struct Subdevice *, NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdBifGetStaticInfo__)(struct Subdevice *, NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdBifGetAspmL1Flags__)(struct Subdevice *, NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdBifSetPcieRo__)(struct Subdevice *, NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS *); @@ -533,11 +541,36 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdInternalNvlinkGetSetNvswitchFabricAddr__)(struct Subdevice *, NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalNvlinkGetNumActiveLinksPerIoctrl__)(struct Subdevice *, NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalNvlinkGetTotalNumLinksPerIoctrl__)(struct Subdevice *, NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalSetP2pCaps__)(struct Subdevice *, NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalRemoveP2pCaps__)(struct Subdevice *, NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalGetPcieP2pCaps__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalGetCoherentFbApertureSize__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalInitGpuIntr__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalGsyncOptimizeTiming__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalGsyncGetDisplayIds__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalGsyncSetStereoSync__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalGsyncGetVactiveLines__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalGsyncIsDisplayIdValid__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalGsyncSetOrRestoreGpioRasterSync__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalFbsrInit__)(struct Subdevice *, NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalFbsrSendRegionInfo__)(struct Subdevice *, NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalPostInitBrightcStateLoad__)(struct Subdevice *, NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit__)(struct Subdevice *); + NV_STATUS (*__subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask__)(struct Subdevice *, NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask__)(struct Subdevice *, NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType__)(struct Subdevice *, NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdVgpuMgrInternalEnumerateVgpuPerPgpu__)(struct Subdevice *, NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdVgpuMgrInternalClearGuestVmInfo__)(struct Subdevice *, NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdVgpuMgrInternalGetVgpuFbUsage__)(struct Subdevice *, NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdVgpuMgrInternalSetVgpuEncoderCapacity__)(struct Subdevice *, NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdVgpuMgrInternalCleanupGspVgpuPluginResources__)(struct Subdevice *, NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdVgpuMgrInternalGetPgpuFsEncoding__)(struct Subdevice *, NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdVgpuMgrInternalGetPgpuMigrationSupport__)(struct Subdevice *, NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdVgpuMgrInternalSetVgpuMgrConfig__)(struct Subdevice *, NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGetAvailableHshubMask__)(struct Subdevice *, NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdCcuMap__)(struct Subdevice *, NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS *); - NV_STATUS (*__subdeviceCtrlCmdCcuUnmap__)(struct Subdevice *); + NV_STATUS (*__subdeviceCtrlCmdCcuUnmap__)(struct Subdevice *, NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdCcuSetStreamState__)(struct Subdevice *, NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS *); NvBool (*__subdeviceShareCallback__)(struct Subdevice *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__subdeviceMapTo__)(struct Subdevice *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__subdeviceGetOrAllocNotifShare__)(struct Subdevice *, NvHandle, NvHandle, struct NotifShare **); @@ -558,6 +591,7 @@ struct Subdevice { NV_STATUS (*__subdeviceGetMemoryMappingDescriptor__)(struct Subdevice *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__subdeviceUnregisterEvent__)(struct Subdevice *, NvHandle, NvHandle, NvHandle, NvHandle); NvBool (*__subdeviceCanCopy__)(struct Subdevice *); + NV_STATUS (*__subdeviceIsDuplicate__)(struct Subdevice *, NvHandle, NvBool *); PEVENTNOTIFICATION *(*__subdeviceGetNotificationListPtr__)(struct Subdevice *); struct NotifShare *(*__subdeviceGetNotificationShare__)(struct Subdevice *); NV_STATUS (*__subdeviceMap__)(struct Subdevice *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -566,9 +600,8 @@ struct Subdevice { NvU32 subDeviceInst; struct Device *pDevice; NvBool bMaxGrTickFreqRequested; - PNODE pP2PMappingList; NvU64 P2PfbMappedBytes; - NvU32 notifyActions[165]; + NvU32 notifyActions[177]; NvHandle hNotifierMemory; struct Memory *pNotifierMemory; NvHandle hSemMemory; @@ -583,7 +616,8 @@ struct Subdevice { NvBool bRcWatchdogSoftDisableRequested; NvBool bReservePerfMon; NvU32 perfBoostIndex; - NvU32 perfBoostRefCount; + NvU32 perfBoostHighRefCount; + NvU32 perfBoostLowRefCount; NvBool perfBoostEntryExists; NvBool bLockedClockModeRequested; NvU32 bNvlinkErrorInjectionModeRequested; @@ -624,6 +658,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceInternalControlForward(pSubdevice, command, pParams, size) subdeviceInternalControlForward_DISPATCH(pSubdevice, command, pParams, size) #define subdeviceControlFilter(pSubdevice, pCallContext, pParams) subdeviceControlFilter_DISPATCH(pSubdevice, pCallContext, pParams) #define subdeviceCtrlCmdBiosGetInfoV2(pSubdevice, pBiosInfoParams) subdeviceCtrlCmdBiosGetInfoV2_DISPATCH(pSubdevice, pBiosInfoParams) +#define subdeviceCtrlCmdBiosGetNbsiV2(pSubdevice, pNbsiParams) subdeviceCtrlCmdBiosGetNbsiV2_DISPATCH(pSubdevice, pNbsiParams) #define subdeviceCtrlCmdBiosGetSKUInfo(pSubdevice, pBiosGetSKUInfoParams) subdeviceCtrlCmdBiosGetSKUInfo_DISPATCH(pSubdevice, pBiosGetSKUInfoParams) #define subdeviceCtrlCmdBiosGetPostTime(pSubdevice, pBiosPostTime) subdeviceCtrlCmdBiosGetPostTime_DISPATCH(pSubdevice, pBiosPostTime) #define subdeviceCtrlCmdBiosGetUefiSupport(pSubdevice, pUEFIParams) subdeviceCtrlCmdBiosGetUefiSupport_DISPATCH(pSubdevice, pUEFIParams) @@ -665,10 +700,15 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdBusGetC2CInfo(pSubdevice, pParams) subdeviceCtrlCmdBusGetC2CInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBusGetC2CErrorInfo(pSubdevice, pParams) subdeviceCtrlCmdBusGetC2CErrorInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBusSysmemAccess(pSubdevice, pParams) subdeviceCtrlCmdBusSysmemAccess_DISPATCH(pSubdevice, pParams) -#define subdeviceCtrlCmdBusGetNvlinkCaps(pSubdevice, pParams) subdeviceCtrlCmdBusGetNvlinkCaps_DISPATCH(pSubdevice, pParams) -#define subdeviceCtrlCmdBusGetNvlinkStatus(pSubdevice, pParams) subdeviceCtrlCmdBusGetNvlinkStatus_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdBusSetP2pMapping(pSubdevice, pParams) subdeviceCtrlCmdBusSetP2pMapping_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdBusUnsetP2pMapping(pSubdevice, pParams) subdeviceCtrlCmdBusUnsetP2pMapping_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGetNvlinkCounters(pSubdevice, pParams) subdeviceCtrlCmdGetNvlinkCounters_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdClearNvlinkCounters(pSubdevice, pParams) subdeviceCtrlCmdClearNvlinkCounters_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdBusGetNvlinkCaps(pSubdevice, pParams) subdeviceCtrlCmdBusGetNvlinkCaps_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdBusGetNvlinkStatus(pSubdevice, pParams) subdeviceCtrlCmdBusGetNvlinkStatus_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdBusGetNvlinkErrInfo(pSubdevice, pParams) subdeviceCtrlCmdBusGetNvlinkErrInfo_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdNvlinGetLinkFomValues(pSubdevice, pParams) subdeviceCtrlCmdNvlinGetLinkFomValues_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdNvlinkGetNvlinkEccErrors(pSubdevice, pParams) subdeviceCtrlCmdNvlinkGetNvlinkEccErrors_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdNvlinkGetLinkFatalErrorCounts(pSubdevice, pParams) subdeviceCtrlCmdNvlinkGetLinkFatalErrorCounts_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdNvlinkSetupEom(pSubdevice, pParams) subdeviceCtrlCmdNvlinkSetupEom_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdNvlinkGetPowerState(pSubdevice, pParams) subdeviceCtrlCmdNvlinkGetPowerState_DISPATCH(pSubdevice, pParams) @@ -710,7 +750,9 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdNvlinkSyncLinkMasksAndVbiosInfo(pSubdevice, pParams) subdeviceCtrlCmdNvlinkSyncLinkMasksAndVbiosInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdNvlinkEnableLinks(pSubdevice) subdeviceCtrlCmdNvlinkEnableLinks_DISPATCH(pSubdevice) #define subdeviceCtrlCmdNvlinkProcessInitDisabledLinks(pSubdevice, pParams) subdeviceCtrlCmdNvlinkProcessInitDisabledLinks_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdNvlinkInbandSendData(pSubdevice, pParams) subdeviceCtrlCmdNvlinkInbandSendData_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdNvlinkEomControl(pSubdevice, pParams) subdeviceCtrlCmdNvlinkEomControl_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdNvlinkL1Threshold(pSubdevice, pParams) subdeviceCtrlCmdNvlinkL1Threshold_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdI2cReadBuffer(pSubdevice, pI2cParams) subdeviceCtrlCmdI2cReadBuffer_DISPATCH(pSubdevice, pI2cParams) #define subdeviceCtrlCmdI2cWriteBuffer(pSubdevice, pI2cParams) subdeviceCtrlCmdI2cWriteBuffer_DISPATCH(pSubdevice, pI2cParams) #define subdeviceCtrlCmdI2cReadReg(pSubdevice, pI2cParams) subdeviceCtrlCmdI2cReadReg_DISPATCH(pSubdevice, pI2cParams) @@ -719,13 +761,20 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamplesV2(pSubdevice, pParams) subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamplesV2_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdPerfRatedTdpGetControl(pSubdevice, pControlParams) subdeviceCtrlCmdPerfRatedTdpGetControl_DISPATCH(pSubdevice, pControlParams) #define subdeviceCtrlCmdPerfRatedTdpSetControl(pSubdevice, pControlParams) subdeviceCtrlCmdPerfRatedTdpSetControl_DISPATCH(pSubdevice, pControlParams) +#define subdeviceCtrlCmdPerfRatedTdpSetControl_HAL(pSubdevice, pControlParams) subdeviceCtrlCmdPerfRatedTdpSetControl_DISPATCH(pSubdevice, pControlParams) #define subdeviceCtrlCmdPerfReservePerfmonHw(pSubdevice, pPerfmonParams) subdeviceCtrlCmdPerfReservePerfmonHw_DISPATCH(pSubdevice, pPerfmonParams) +#define subdeviceCtrlCmdPerfReservePerfmonHw_HAL(pSubdevice, pPerfmonParams) subdeviceCtrlCmdPerfReservePerfmonHw_DISPATCH(pSubdevice, pPerfmonParams) +#define subdeviceCtrlCmdPerfSetAuxPowerState(pSubdevice, pPowerStateParams) subdeviceCtrlCmdPerfSetAuxPowerState_DISPATCH(pSubdevice, pPowerStateParams) +#define subdeviceCtrlCmdPerfSetAuxPowerState_HAL(pSubdevice, pPowerStateParams) subdeviceCtrlCmdPerfSetAuxPowerState_DISPATCH(pSubdevice, pPowerStateParams) +#define subdeviceCtrlCmdPerfSetPowerstate(pSubdevice, pPowerInfoParams) subdeviceCtrlCmdPerfSetPowerstate_DISPATCH(pSubdevice, pPowerInfoParams) +#define subdeviceCtrlCmdPerfSetPowerstate_HAL(pSubdevice, pPowerInfoParams) subdeviceCtrlCmdPerfSetPowerstate_DISPATCH(pSubdevice, pPowerInfoParams) #define subdeviceCtrlCmdKPerfBoost(pSubdevice, pBoostParams) subdeviceCtrlCmdKPerfBoost_DISPATCH(pSubdevice, pBoostParams) #define subdeviceCtrlCmdFbGetFBRegionInfo(pSubdevice, pGFBRIParams) subdeviceCtrlCmdFbGetFBRegionInfo_DISPATCH(pSubdevice, pGFBRIParams) #define subdeviceCtrlCmdFbGetBar1Offset(pSubdevice, pFbMemParams) subdeviceCtrlCmdFbGetBar1Offset_DISPATCH(pSubdevice, pFbMemParams) #define subdeviceCtrlCmdFbIsKind(pSubdevice, pIsKindParams) subdeviceCtrlCmdFbIsKind_DISPATCH(pSubdevice, pIsKindParams) #define subdeviceCtrlCmdFbGetMemAlignment(pSubdevice, pParams) subdeviceCtrlCmdFbGetMemAlignment_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdFbGetHeapReservationSize(pSubdevice, pParams) subdeviceCtrlCmdFbGetHeapReservationSize_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalMemmgrGetVgpuHostRmReservedFb(pSubdevice, pParams) subdeviceCtrlCmdInternalMemmgrGetVgpuHostRmReservedFb_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdFbGetInfo(pSubdevice, pFbInfoParams) subdeviceCtrlCmdFbGetInfo_DISPATCH(pSubdevice, pFbInfoParams) #define subdeviceCtrlCmdFbGetInfoV2(pSubdevice, pFbInfoParams) subdeviceCtrlCmdFbGetInfoV2_DISPATCH(pSubdevice, pFbInfoParams) #define subdeviceCtrlCmdFbGetCarveoutAddressInfo(pSubdevice, pParams) subdeviceCtrlCmdFbGetCarveoutAddressInfo_DISPATCH(pSubdevice, pParams) @@ -772,11 +821,13 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdFifoGetChannelMemInfo(pSubdevice, pChannelMemParams) subdeviceCtrlCmdFifoGetChannelMemInfo_DISPATCH(pSubdevice, pChannelMemParams) #define subdeviceCtrlCmdFifoGetUserdLocation(pSubdevice, pUserdLocationParams) subdeviceCtrlCmdFifoGetUserdLocation_DISPATCH(pSubdevice, pUserdLocationParams) #define subdeviceCtrlCmdFifoGetDeviceInfoTable(pSubdevice, pParams) subdeviceCtrlCmdFifoGetDeviceInfoTable_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdFifoSetupVfZombieSubctxPdb(pSubdevice, pParams) subdeviceCtrlCmdFifoSetupVfZombieSubctxPdb_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdFifoClearFaultedBit(pSubdevice, pParams) subdeviceCtrlCmdFifoClearFaultedBit_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdFifoRunlistSetSchedPolicy(pSubdevice, pSchedPolicyParams) subdeviceCtrlCmdFifoRunlistSetSchedPolicy_DISPATCH(pSubdevice, pSchedPolicyParams) #define subdeviceCtrlCmdFifoUpdateChannelInfo(pSubdevice, pChannelInfo) subdeviceCtrlCmdFifoUpdateChannelInfo_DISPATCH(pSubdevice, pChannelInfo) #define subdeviceCtrlCmdInternalFifoPromoteRunlistBuffers(pSubdevice, pParams) subdeviceCtrlCmdInternalFifoPromoteRunlistBuffers_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalFifoGetNumChannels(pSubdevice, pNumChannelsParams) subdeviceCtrlCmdInternalFifoGetNumChannels_DISPATCH(pSubdevice, pNumChannelsParams) +#define subdeviceCtrlCmdFifoGetAllocatedChannels(pSubdevice, pParams) subdeviceCtrlCmdFifoGetAllocatedChannels_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdKGrGetInfo(pSubdevice, pParams) subdeviceCtrlCmdKGrGetInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdKGrGetInfoV2(pSubdevice, pParams) subdeviceCtrlCmdKGrGetInfoV2_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdKGrGetCapsV2(pSubdevice, pGrCapsParams) subdeviceCtrlCmdKGrGetCapsV2_DISPATCH(pSubdevice, pGrCapsParams) @@ -857,11 +908,13 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdGpuGetFermiZcullInfo(pSubdevice, pGpuFermiZcullInfoParams) subdeviceCtrlCmdGpuGetFermiZcullInfo_DISPATCH(pSubdevice, pGpuFermiZcullInfoParams) #define subdeviceCtrlCmdGpuGetPesInfo(pSubdevice, pParams) subdeviceCtrlCmdGpuGetPesInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuExecRegOps(pSubdevice, pRegParams) subdeviceCtrlCmdGpuExecRegOps_DISPATCH(pSubdevice, pRegParams) +#define subdeviceCtrlCmdGpuMigratableOps(pSubdevice, pRegParams) subdeviceCtrlCmdGpuMigratableOps_DISPATCH(pSubdevice, pRegParams) #define subdeviceCtrlCmdGpuQueryMode(pSubdevice, pQueryMode) subdeviceCtrlCmdGpuQueryMode_DISPATCH(pSubdevice, pQueryMode) #define subdeviceCtrlCmdGpuGetInforomImageVersion(pSubdevice, pVersionInfo) subdeviceCtrlCmdGpuGetInforomImageVersion_DISPATCH(pSubdevice, pVersionInfo) #define subdeviceCtrlCmdGpuGetInforomObjectVersion(pSubdevice, pVersionInfo) subdeviceCtrlCmdGpuGetInforomObjectVersion_DISPATCH(pSubdevice, pVersionInfo) #define subdeviceCtrlCmdGpuQueryInforomEccSupport(pSubdevice) subdeviceCtrlCmdGpuQueryInforomEccSupport_DISPATCH(pSubdevice) #define subdeviceCtrlCmdGpuQueryEccStatus(pSubdevice, pParams) subdeviceCtrlCmdGpuQueryEccStatus_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdGpuGetChipDetails(pSubdevice, pParams) subdeviceCtrlCmdGpuGetChipDetails_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuGetOEMBoardInfo(pSubdevice, pBoardInfo) subdeviceCtrlCmdGpuGetOEMBoardInfo_DISPATCH(pSubdevice, pBoardInfo) #define subdeviceCtrlCmdGpuGetOEMInfo(pSubdevice, pOemInfo) subdeviceCtrlCmdGpuGetOEMInfo_DISPATCH(pSubdevice, pOemInfo) #define subdeviceCtrlCmdGpuHandleGpuSR(pSubdevice) subdeviceCtrlCmdGpuHandleGpuSR_DISPATCH(pSubdevice) @@ -888,10 +941,15 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdGpuGetEngineRunlistPriBase(pSubdevice, pParams) subdeviceCtrlCmdGpuGetEngineRunlistPriBase_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuGetHwEngineId(pSubdevice, pParams) subdeviceCtrlCmdGpuGetHwEngineId_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuGetMaxSupportedPageSize(pSubdevice, pParams) subdeviceCtrlCmdGpuGetMaxSupportedPageSize_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdGpuHandleVfPriFault(pSubdevice, pParams) subdeviceCtrlCmdGpuHandleVfPriFault_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuSetComputePolicyConfig(pSubdevice, pParams) subdeviceCtrlCmdGpuSetComputePolicyConfig_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuGetComputePolicyConfig(pSubdevice, pParams) subdeviceCtrlCmdGpuGetComputePolicyConfig_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdValidateMemMapRequest(pSubdevice, pParams) subdeviceCtrlCmdValidateMemMapRequest_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdGpuGetGfid(pSubdevice, pParams) subdeviceCtrlCmdGpuGetGfid_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdUpdateGfidP2pCapability(pSubdevice, pParams) subdeviceCtrlCmdUpdateGfidP2pCapability_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuGetEngineLoadTimes(pSubdevice, pParams) subdeviceCtrlCmdGpuGetEngineLoadTimes_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdGetP2pCaps(pSubdevice, pParams) subdeviceCtrlCmdGetP2pCaps_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdGetGpuFabricProbeInfo(pSubdevice, pParams) subdeviceCtrlCmdGetGpuFabricProbeInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdEventSetTrigger(pSubdevice) subdeviceCtrlCmdEventSetTrigger_DISPATCH(pSubdevice) #define subdeviceCtrlCmdEventSetTriggerFifo(pSubdevice, pTriggerFifoParams) subdeviceCtrlCmdEventSetTriggerFifo_DISPATCH(pSubdevice, pTriggerFifoParams) #define subdeviceCtrlCmdEventSetNotification(pSubdevice, pSetEventParams) subdeviceCtrlCmdEventSetNotification_DISPATCH(pSubdevice, pSetEventParams) @@ -922,11 +980,14 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdNvdGetDump(pSubdevice, pDumpParams) subdeviceCtrlCmdNvdGetDump_DISPATCH(pSubdevice, pDumpParams) #define subdeviceCtrlCmdNvdGetNocatJournalRpt(pSubdevice, pReportParams) subdeviceCtrlCmdNvdGetNocatJournalRpt_DISPATCH(pSubdevice, pReportParams) #define subdeviceCtrlCmdNvdSetNocatJournalData(pSubdevice, pReportParams) subdeviceCtrlCmdNvdSetNocatJournalData_DISPATCH(pSubdevice, pReportParams) +#define subdeviceCtrlCmdPmgrGetModuleInfo(pSubdevice, pModuleInfoParams) subdeviceCtrlCmdPmgrGetModuleInfo_DISPATCH(pSubdevice, pModuleInfoParams) +#define subdeviceCtrlCmdLpwrDifrPrefetchResponse(pSubdevice, pParams) subdeviceCtrlCmdLpwrDifrPrefetchResponse_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdLpwrDifrCtrl(pSubdevice, pParams) subdeviceCtrlCmdLpwrDifrCtrl_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdCeGetCaps(pSubdevice, pCeCapsParams) subdeviceCtrlCmdCeGetCaps_DISPATCH(pSubdevice, pCeCapsParams) -#define subdeviceCtrlCmdCeGetCapsV2(pSubdevice, pCeCapsParams) subdeviceCtrlCmdCeGetCapsV2_DISPATCH(pSubdevice, pCeCapsParams) #define subdeviceCtrlCmdCeGetAllCaps(pSubdevice, pCeCapsParams) subdeviceCtrlCmdCeGetAllCaps_DISPATCH(pSubdevice, pCeCapsParams) #define subdeviceCtrlCmdCeGetCePceMask(pSubdevice, pCePceMaskParams) subdeviceCtrlCmdCeGetCePceMask_DISPATCH(pSubdevice, pCePceMaskParams) #define subdeviceCtrlCmdCeUpdatePceLceMappings(pSubdevice, pCeUpdatePceLceMappingsParams) subdeviceCtrlCmdCeUpdatePceLceMappings_DISPATCH(pSubdevice, pCeUpdatePceLceMappingsParams) +#define subdeviceCtrlCmdCeGetCapsV2(pSubdevice, pCeCapsParams) subdeviceCtrlCmdCeGetCapsV2_DISPATCH(pSubdevice, pCeCapsParams) #define subdeviceCtrlCmdFlcnGetDmemUsage(pSubdevice, pFlcnDmemUsageParams) subdeviceCtrlCmdFlcnGetDmemUsage_DISPATCH(pSubdevice, pFlcnDmemUsageParams) #define subdeviceCtrlCmdFlcnGetEngineArch(pSubdevice, pParams) subdeviceCtrlCmdFlcnGetEngineArch_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdFlcnUstreamerQueueInfo(pSubdevice, pParams) subdeviceCtrlCmdFlcnUstreamerQueueInfo_DISPATCH(pSubdevice, pParams) @@ -980,8 +1041,6 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdInternalGetConstructedFalconInfo(pSubdevice, pParams) subdeviceCtrlCmdInternalGetConstructedFalconInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalRecoverAllComputeContexts(pSubdevice) subdeviceCtrlCmdInternalRecoverAllComputeContexts_DISPATCH(pSubdevice) #define subdeviceCtrlCmdInternalGetSmcMode(pSubdevice, pParams) subdeviceCtrlCmdInternalGetSmcMode_DISPATCH(pSubdevice, pParams) -#define subdeviceCtrlCmdInternalBusBindLocalGfidForP2p(pSubdevice, pParams) subdeviceCtrlCmdInternalBusBindLocalGfidForP2p_DISPATCH(pSubdevice, pParams) -#define subdeviceCtrlCmdInternalBusBindRemoteGfidForP2p(pSubdevice, pParams) subdeviceCtrlCmdInternalBusBindRemoteGfidForP2p_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalBusFlushWithSysmembar(pSubdevice) subdeviceCtrlCmdInternalBusFlushWithSysmembar_DISPATCH(pSubdevice) #define subdeviceCtrlCmdInternalBusSetupP2pMailboxLocal(pSubdevice, pParams) subdeviceCtrlCmdInternalBusSetupP2pMailboxLocal_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalBusSetupP2pMailboxRemote(pSubdevice, pParams) subdeviceCtrlCmdInternalBusSetupP2pMailboxRemote_DISPATCH(pSubdevice, pParams) @@ -993,6 +1052,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdInternalGmmuUnregisterFaultBuffer(pSubdevice) subdeviceCtrlCmdInternalGmmuUnregisterFaultBuffer_DISPATCH(pSubdevice) #define subdeviceCtrlCmdInternalGmmuRegisterClientShadowFaultBuffer(pSubdevice, pParams) subdeviceCtrlCmdInternalGmmuRegisterClientShadowFaultBuffer_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer(pSubdevice) subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer_DISPATCH(pSubdevice) +#define subdeviceCtrlCmdInternalGmmuCopyReservedSplitGVASpacePdesServer(pSubdevice, pCopyServerReservedPdesParams) subdeviceCtrlCmdInternalGmmuCopyReservedSplitGVASpacePdesServer_DISPATCH(pSubdevice, pCopyServerReservedPdesParams) #define subdeviceCtrlCmdCeGetPhysicalCaps(pSubdevice, pCeCapsParams) subdeviceCtrlCmdCeGetPhysicalCaps_DISPATCH(pSubdevice, pCeCapsParams) #define subdeviceCtrlCmdCeGetAllPhysicalCaps(pSubdevice, pCeCapsParams) subdeviceCtrlCmdCeGetAllPhysicalCaps_DISPATCH(pSubdevice, pCeCapsParams) #define subdeviceCtrlCmdCeUpdateClassDB(pSubdevice, params) subdeviceCtrlCmdCeUpdateClassDB_DISPATCH(pSubdevice, params) @@ -1010,6 +1070,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdInternalPerfPerfmonClientReservationCheck(pSubdevice, pParams) subdeviceCtrlCmdInternalPerfPerfmonClientReservationCheck_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalPerfPerfmonClientReservationSet(pSubdevice, pParams) subdeviceCtrlCmdInternalPerfPerfmonClientReservationSet_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalPerfCfControllerSetMaxVGpuVMCount(pSubdevice, pParams) subdeviceCtrlCmdInternalPerfCfControllerSetMaxVGpuVMCount_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalPerfGetAuxPowerState(pSubdevice, pParams) subdeviceCtrlCmdInternalPerfGetAuxPowerState_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBifGetStaticInfo(pSubdevice, pParams) subdeviceCtrlCmdBifGetStaticInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBifGetAspmL1Flags(pSubdevice, pParams) subdeviceCtrlCmdBifGetAspmL1Flags_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBifSetPcieRo(pSubdevice, pParams) subdeviceCtrlCmdBifSetPcieRo_DISPATCH(pSubdevice, pParams) @@ -1022,11 +1083,36 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdInternalNvlinkGetSetNvswitchFabricAddr(pSubdevice, pParams) subdeviceCtrlCmdInternalNvlinkGetSetNvswitchFabricAddr_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalNvlinkGetNumActiveLinksPerIoctrl(pSubdevice, pParams) subdeviceCtrlCmdInternalNvlinkGetNumActiveLinksPerIoctrl_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalNvlinkGetTotalNumLinksPerIoctrl(pSubdevice, pParams) subdeviceCtrlCmdInternalNvlinkGetTotalNumLinksPerIoctrl_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalSetP2pCaps(pSubdevice, pParams) subdeviceCtrlCmdInternalSetP2pCaps_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalRemoveP2pCaps(pSubdevice, pParams) subdeviceCtrlCmdInternalRemoveP2pCaps_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalGetPcieP2pCaps(pSubdevice, pParams) subdeviceCtrlCmdInternalGetPcieP2pCaps_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalGetCoherentFbApertureSize(pSubdevice, pParams) subdeviceCtrlCmdInternalGetCoherentFbApertureSize_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalInitGpuIntr(pSubdevice, pAttachParams) subdeviceCtrlCmdInternalInitGpuIntr_DISPATCH(pSubdevice, pAttachParams) +#define subdeviceCtrlCmdInternalGsyncOptimizeTiming(pSubdevice, pAttachParams) subdeviceCtrlCmdInternalGsyncOptimizeTiming_DISPATCH(pSubdevice, pAttachParams) +#define subdeviceCtrlCmdInternalGsyncGetDisplayIds(pSubdevice, pAttachParams) subdeviceCtrlCmdInternalGsyncGetDisplayIds_DISPATCH(pSubdevice, pAttachParams) +#define subdeviceCtrlCmdInternalGsyncSetStereoSync(pSubdevice, pAttachParams) subdeviceCtrlCmdInternalGsyncSetStereoSync_DISPATCH(pSubdevice, pAttachParams) +#define subdeviceCtrlCmdInternalGsyncGetVactiveLines(pSubdevice, pAttachParams) subdeviceCtrlCmdInternalGsyncGetVactiveLines_DISPATCH(pSubdevice, pAttachParams) +#define subdeviceCtrlCmdInternalGsyncIsDisplayIdValid(pSubdevice, pAttachParams) subdeviceCtrlCmdInternalGsyncIsDisplayIdValid_DISPATCH(pSubdevice, pAttachParams) +#define subdeviceCtrlCmdInternalGsyncSetOrRestoreGpioRasterSync(pSubdevice, pAttachParams) subdeviceCtrlCmdInternalGsyncSetOrRestoreGpioRasterSync_DISPATCH(pSubdevice, pAttachParams) +#define subdeviceCtrlCmdInternalFbsrInit(pSubdevice, pParams) subdeviceCtrlCmdInternalFbsrInit_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalFbsrSendRegionInfo(pSubdevice, pParams) subdeviceCtrlCmdInternalFbsrSendRegionInfo_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalPostInitBrightcStateLoad(pSubdevice, pParams) subdeviceCtrlCmdInternalPostInitBrightcStateLoad_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit(pSubdevice) subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit_DISPATCH(pSubdevice) +#define subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask(pSubdevice, pParams) subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask(pSubdevice, pParams) subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType(pSubdevice, pParams) subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdVgpuMgrInternalEnumerateVgpuPerPgpu(pSubdevice, pParams) subdeviceCtrlCmdVgpuMgrInternalEnumerateVgpuPerPgpu_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdVgpuMgrInternalClearGuestVmInfo(pSubdevice, pParams) subdeviceCtrlCmdVgpuMgrInternalClearGuestVmInfo_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdVgpuMgrInternalGetVgpuFbUsage(pSubdevice, pParams) subdeviceCtrlCmdVgpuMgrInternalGetVgpuFbUsage_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdVgpuMgrInternalSetVgpuEncoderCapacity(pSubdevice, pParams) subdeviceCtrlCmdVgpuMgrInternalSetVgpuEncoderCapacity_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdVgpuMgrInternalCleanupGspVgpuPluginResources(pSubdevice, pParams) subdeviceCtrlCmdVgpuMgrInternalCleanupGspVgpuPluginResources_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdVgpuMgrInternalGetPgpuFsEncoding(pSubdevice, pParams) subdeviceCtrlCmdVgpuMgrInternalGetPgpuFsEncoding_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdVgpuMgrInternalGetPgpuMigrationSupport(pSubdevice, pParams) subdeviceCtrlCmdVgpuMgrInternalGetPgpuMigrationSupport_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdVgpuMgrInternalSetVgpuMgrConfig(pSubdevice, pParams) subdeviceCtrlCmdVgpuMgrInternalSetVgpuMgrConfig_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGetAvailableHshubMask(pSubdevice, pParams) subdeviceCtrlCmdGetAvailableHshubMask_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdCcuMap(pSubdevice, pParams) subdeviceCtrlCmdCcuMap_DISPATCH(pSubdevice, pParams) -#define subdeviceCtrlCmdCcuUnmap(pSubdevice) subdeviceCtrlCmdCcuUnmap_DISPATCH(pSubdevice) +#define subdeviceCtrlCmdCcuUnmap(pSubdevice, pParams) subdeviceCtrlCmdCcuUnmap_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdCcuSetStreamState(pSubdevice, pParams) subdeviceCtrlCmdCcuSetStreamState_DISPATCH(pSubdevice, pParams) #define subdeviceShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) subdeviceShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) #define subdeviceMapTo(pResource, pParams) subdeviceMapTo_DISPATCH(pResource, pParams) #define subdeviceGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) subdeviceGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) @@ -1047,36 +1133,11 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceGetMemoryMappingDescriptor(pRmResource, ppMemDesc) subdeviceGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define subdeviceUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) subdeviceUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define subdeviceCanCopy(pResource) subdeviceCanCopy_DISPATCH(pResource) +#define subdeviceIsDuplicate(pResource, hMemory, pDuplicate) subdeviceIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define subdeviceGetNotificationListPtr(pNotifier) subdeviceGetNotificationListPtr_DISPATCH(pNotifier) #define subdeviceGetNotificationShare(pNotifier) subdeviceGetNotificationShare_DISPATCH(pNotifier) #define subdeviceMap(pGpuResource, pCallContext, pParams, pCpuMapping) subdeviceMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define subdeviceAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) subdeviceAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) -NV_STATUS subdeviceCtrlCmdPerfReservePerfmonHw_KERNEL(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS *pPerfmonParams); - -#ifdef __nvoc_subdevice_h_disabled -static inline NV_STATUS subdeviceCtrlCmdPerfReservePerfmonHw_internal(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS *pPerfmonParams) { - NV_ASSERT_FAILED_PRECOMP("Subdevice was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_subdevice_h_disabled -#define subdeviceCtrlCmdPerfReservePerfmonHw_internal(pSubdevice, pPerfmonParams) subdeviceCtrlCmdPerfReservePerfmonHw_KERNEL(pSubdevice, pPerfmonParams) -#endif //__nvoc_subdevice_h_disabled - -#define subdeviceCtrlCmdPerfReservePerfmonHw_internal_HAL(pSubdevice, pPerfmonParams) subdeviceCtrlCmdPerfReservePerfmonHw_internal(pSubdevice, pPerfmonParams) - -NV_STATUS subdeviceCtrlCmdPerfRatedTdpSetControl_KERNEL(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS *pControlParams); - -#ifdef __nvoc_subdevice_h_disabled -static inline NV_STATUS subdeviceCtrlCmdPerfRatedTdpSetControl_internal(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS *pControlParams) { - NV_ASSERT_FAILED_PRECOMP("Subdevice was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_subdevice_h_disabled -#define subdeviceCtrlCmdPerfRatedTdpSetControl_internal(pSubdevice, pControlParams) subdeviceCtrlCmdPerfRatedTdpSetControl_KERNEL(pSubdevice, pControlParams) -#endif //__nvoc_subdevice_h_disabled - -#define subdeviceCtrlCmdPerfRatedTdpSetControl_internal_HAL(pSubdevice, pControlParams) subdeviceCtrlCmdPerfRatedTdpSetControl_internal(pSubdevice, pControlParams) - void subdevicePreDestruct_IMPL(struct Subdevice *pResource); static inline void subdevicePreDestruct_DISPATCH(struct Subdevice *pResource) { @@ -1101,6 +1162,12 @@ static inline NV_STATUS subdeviceCtrlCmdBiosGetInfoV2_DISPATCH(struct Subdevice return pSubdevice->__subdeviceCtrlCmdBiosGetInfoV2__(pSubdevice, pBiosInfoParams); } +NV_STATUS subdeviceCtrlCmdBiosGetNbsiV2_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS *pNbsiParams); + +static inline NV_STATUS subdeviceCtrlCmdBiosGetNbsiV2_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS *pNbsiParams) { + return pSubdevice->__subdeviceCtrlCmdBiosGetNbsiV2__(pSubdevice, pNbsiParams); +} + NV_STATUS subdeviceCtrlCmdBiosGetSKUInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS *pBiosGetSKUInfoParams); static inline NV_STATUS subdeviceCtrlCmdBiosGetSKUInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS *pBiosGetSKUInfoParams) { @@ -1347,16 +1414,16 @@ static inline NV_STATUS subdeviceCtrlCmdBusSysmemAccess_DISPATCH(struct Subdevic return pSubdevice->__subdeviceCtrlCmdBusSysmemAccess__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdBusGetNvlinkCaps_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS *pParams); +NV_STATUS subdeviceCtrlCmdBusSetP2pMapping_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS *pParams); -static inline NV_STATUS subdeviceCtrlCmdBusGetNvlinkCaps_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS *pParams) { - return pSubdevice->__subdeviceCtrlCmdBusGetNvlinkCaps__(pSubdevice, pParams); +static inline NV_STATUS subdeviceCtrlCmdBusSetP2pMapping_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdBusSetP2pMapping__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdBusGetNvlinkStatus_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *pParams); +NV_STATUS subdeviceCtrlCmdBusUnsetP2pMapping_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS *pParams); -static inline NV_STATUS subdeviceCtrlCmdBusGetNvlinkStatus_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *pParams) { - return pSubdevice->__subdeviceCtrlCmdBusGetNvlinkStatus__(pSubdevice, pParams); +static inline NV_STATUS subdeviceCtrlCmdBusUnsetP2pMapping_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdBusUnsetP2pMapping__(pSubdevice, pParams); } NV_STATUS subdeviceCtrlCmdGetNvlinkCounters_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS *pParams); @@ -1371,6 +1438,36 @@ static inline NV_STATUS subdeviceCtrlCmdClearNvlinkCounters_DISPATCH(struct Subd return pSubdevice->__subdeviceCtrlCmdClearNvlinkCounters__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdBusGetNvlinkCaps_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdBusGetNvlinkCaps_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdBusGetNvlinkCaps__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdBusGetNvlinkStatus_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdBusGetNvlinkStatus_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdBusGetNvlinkStatus__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdBusGetNvlinkErrInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdBusGetNvlinkErrInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdBusGetNvlinkErrInfo__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdNvlinGetLinkFomValues_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdNvlinGetLinkFomValues_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_NVLINK_GET_LINK_FOM_VALUES_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdNvlinGetLinkFomValues__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdNvlinkGetNvlinkEccErrors_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdNvlinkGetNvlinkEccErrors_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdNvlinkGetNvlinkEccErrors__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdNvlinkGetLinkFatalErrorCounts_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdNvlinkGetLinkFatalErrorCounts_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_GET_LINK_FATAL_ERROR_COUNTS_PARAMS *pParams) { @@ -1617,12 +1714,24 @@ static inline NV_STATUS subdeviceCtrlCmdNvlinkProcessInitDisabledLinks_DISPATCH( return pSubdevice->__subdeviceCtrlCmdNvlinkProcessInitDisabledLinks__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdNvlinkInbandSendData_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdNvlinkInbandSendData_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdNvlinkInbandSendData__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdNvlinkEomControl_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdNvlinkEomControl_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS *pParams) { return pSubdevice->__subdeviceCtrlCmdNvlinkEomControl__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdNvlinkL1Threshold_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_L1_THRESHOLD_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdNvlinkL1Threshold_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_L1_THRESHOLD_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdNvlinkL1Threshold__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdI2cReadBuffer_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_I2C_READ_BUFFER_PARAMS *pI2cParams); static inline NV_STATUS subdeviceCtrlCmdI2cReadBuffer_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_I2C_READ_BUFFER_PARAMS *pI2cParams) { @@ -1665,22 +1774,30 @@ static inline NV_STATUS subdeviceCtrlCmdPerfRatedTdpGetControl_DISPATCH(struct S return pSubdevice->__subdeviceCtrlCmdPerfRatedTdpGetControl__(pSubdevice, pControlParams); } -static inline NV_STATUS subdeviceCtrlCmdPerfRatedTdpSetControl_a2e9a2(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS *pControlParams) { - return subdeviceCtrlCmdPerfRatedTdpSetControl_internal(pSubdevice, pControlParams); -} +NV_STATUS subdeviceCtrlCmdPerfRatedTdpSetControl_KERNEL(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS *pControlParams); static inline NV_STATUS subdeviceCtrlCmdPerfRatedTdpSetControl_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS *pControlParams) { return pSubdevice->__subdeviceCtrlCmdPerfRatedTdpSetControl__(pSubdevice, pControlParams); } -static inline NV_STATUS subdeviceCtrlCmdPerfReservePerfmonHw_3f0664(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS *pPerfmonParams) { - return subdeviceCtrlCmdPerfReservePerfmonHw_internal(pSubdevice, pPerfmonParams); -} +NV_STATUS subdeviceCtrlCmdPerfReservePerfmonHw_KERNEL(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS *pPerfmonParams); static inline NV_STATUS subdeviceCtrlCmdPerfReservePerfmonHw_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS *pPerfmonParams) { return pSubdevice->__subdeviceCtrlCmdPerfReservePerfmonHw__(pSubdevice, pPerfmonParams); } +NV_STATUS subdeviceCtrlCmdPerfSetAuxPowerState_KERNEL(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS *pPowerStateParams); + +static inline NV_STATUS subdeviceCtrlCmdPerfSetAuxPowerState_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS *pPowerStateParams) { + return pSubdevice->__subdeviceCtrlCmdPerfSetAuxPowerState__(pSubdevice, pPowerStateParams); +} + +NV_STATUS subdeviceCtrlCmdPerfSetPowerstate_KERNEL(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS *pPowerInfoParams); + +static inline NV_STATUS subdeviceCtrlCmdPerfSetPowerstate_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS *pPowerInfoParams) { + return pSubdevice->__subdeviceCtrlCmdPerfSetPowerstate__(pSubdevice, pPowerInfoParams); +} + NV_STATUS subdeviceCtrlCmdKPerfBoost_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_BOOST_PARAMS *pBoostParams); static inline NV_STATUS subdeviceCtrlCmdKPerfBoost_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_BOOST_PARAMS *pBoostParams) { @@ -1717,6 +1834,12 @@ static inline NV_STATUS subdeviceCtrlCmdFbGetHeapReservationSize_DISPATCH(struct return pSubdevice->__subdeviceCtrlCmdFbGetHeapReservationSize__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdInternalMemmgrGetVgpuHostRmReservedFb_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalMemmgrGetVgpuHostRmReservedFb_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalMemmgrGetVgpuHostRmReservedFb__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdFbGetInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_FB_GET_INFO_PARAMS *pFbInfoParams); static inline NV_STATUS subdeviceCtrlCmdFbGetInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_FB_GET_INFO_PARAMS *pFbInfoParams) { @@ -1995,6 +2118,12 @@ static inline NV_STATUS subdeviceCtrlCmdFifoGetDeviceInfoTable_DISPATCH(struct S return pSubdevice->__subdeviceCtrlCmdFifoGetDeviceInfoTable__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdFifoSetupVfZombieSubctxPdb_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdFifoSetupVfZombieSubctxPdb_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdFifoSetupVfZombieSubctxPdb__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdFifoClearFaultedBit_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdFifoClearFaultedBit_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS *pParams) { @@ -2025,6 +2154,12 @@ static inline NV_STATUS subdeviceCtrlCmdInternalFifoGetNumChannels_DISPATCH(stru return pSubdevice->__subdeviceCtrlCmdInternalFifoGetNumChannels__(pSubdevice, pNumChannelsParams); } +NV_STATUS subdeviceCtrlCmdFifoGetAllocatedChannels_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdFifoGetAllocatedChannels_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdFifoGetAllocatedChannels__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdKGrGetInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GR_GET_INFO_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdKGrGetInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GR_GET_INFO_PARAMS *pParams) { @@ -2505,6 +2640,12 @@ static inline NV_STATUS subdeviceCtrlCmdGpuExecRegOps_DISPATCH(struct Subdevice return pSubdevice->__subdeviceCtrlCmdGpuExecRegOps__(pSubdevice, pRegParams); } +NV_STATUS subdeviceCtrlCmdGpuMigratableOps_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS *pRegParams); + +static inline NV_STATUS subdeviceCtrlCmdGpuMigratableOps_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS *pRegParams) { + return pSubdevice->__subdeviceCtrlCmdGpuMigratableOps__(pSubdevice, pRegParams); +} + NV_STATUS subdeviceCtrlCmdGpuQueryMode_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_QUERY_MODE_PARAMS *pQueryMode); static inline NV_STATUS subdeviceCtrlCmdGpuQueryMode_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_QUERY_MODE_PARAMS *pQueryMode) { @@ -2535,6 +2676,12 @@ static inline NV_STATUS subdeviceCtrlCmdGpuQueryEccStatus_DISPATCH(struct Subdev return pSubdevice->__subdeviceCtrlCmdGpuQueryEccStatus__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdGpuGetChipDetails_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdGpuGetChipDetails_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdGpuGetChipDetails__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdGpuGetOEMBoardInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS *pBoardInfo); static inline NV_STATUS subdeviceCtrlCmdGpuGetOEMBoardInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS *pBoardInfo) { @@ -2691,6 +2838,12 @@ static inline NV_STATUS subdeviceCtrlCmdGpuGetMaxSupportedPageSize_DISPATCH(stru return pSubdevice->__subdeviceCtrlCmdGpuGetMaxSupportedPageSize__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdGpuHandleVfPriFault_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdGpuHandleVfPriFault_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdGpuHandleVfPriFault__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdGpuSetComputePolicyConfig_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdGpuSetComputePolicyConfig_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_SET_COMPUTE_POLICY_CONFIG_PARAMS *pParams) { @@ -2709,12 +2862,36 @@ static inline NV_STATUS subdeviceCtrlCmdValidateMemMapRequest_DISPATCH(struct Su return pSubdevice->__subdeviceCtrlCmdValidateMemMapRequest__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdGpuGetGfid_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_GFID_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdGpuGetGfid_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_GFID_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdGpuGetGfid__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdUpdateGfidP2pCapability_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdUpdateGfidP2pCapability_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdUpdateGfidP2pCapability__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdGpuGetEngineLoadTimes_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdGpuGetEngineLoadTimes_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS *pParams) { return pSubdevice->__subdeviceCtrlCmdGpuGetEngineLoadTimes__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdGetP2pCaps_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GET_P2P_CAPS_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdGetP2pCaps_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GET_P2P_CAPS_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdGetP2pCaps__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdGetGpuFabricProbeInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdGetGpuFabricProbeInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdGetGpuFabricProbeInfo__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdEventSetTrigger_IMPL(struct Subdevice *pSubdevice); static inline NV_STATUS subdeviceCtrlCmdEventSetTrigger_DISPATCH(struct Subdevice *pSubdevice) { @@ -2895,18 +3072,30 @@ static inline NV_STATUS subdeviceCtrlCmdNvdSetNocatJournalData_DISPATCH(struct S return pSubdevice->__subdeviceCtrlCmdNvdSetNocatJournalData__(pSubdevice, pReportParams); } +NV_STATUS subdeviceCtrlCmdPmgrGetModuleInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_PMGR_MODULE_INFO_PARAMS *pModuleInfoParams); + +static inline NV_STATUS subdeviceCtrlCmdPmgrGetModuleInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_PMGR_MODULE_INFO_PARAMS *pModuleInfoParams) { + return pSubdevice->__subdeviceCtrlCmdPmgrGetModuleInfo__(pSubdevice, pModuleInfoParams); +} + +NV_STATUS subdeviceCtrlCmdLpwrDifrPrefetchResponse_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdLpwrDifrPrefetchResponse_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdLpwrDifrPrefetchResponse__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdLpwrDifrCtrl_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdLpwrDifrCtrl_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdLpwrDifrCtrl__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdCeGetCaps_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CE_GET_CAPS_PARAMS *pCeCapsParams); static inline NV_STATUS subdeviceCtrlCmdCeGetCaps_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CE_GET_CAPS_PARAMS *pCeCapsParams) { return pSubdevice->__subdeviceCtrlCmdCeGetCaps__(pSubdevice, pCeCapsParams); } -NV_STATUS subdeviceCtrlCmdCeGetCapsV2_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CE_GET_CAPS_V2_PARAMS *pCeCapsParams); - -static inline NV_STATUS subdeviceCtrlCmdCeGetCapsV2_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CE_GET_CAPS_V2_PARAMS *pCeCapsParams) { - return pSubdevice->__subdeviceCtrlCmdCeGetCapsV2__(pSubdevice, pCeCapsParams); -} - NV_STATUS subdeviceCtrlCmdCeGetAllCaps_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *pCeCapsParams); static inline NV_STATUS subdeviceCtrlCmdCeGetAllCaps_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *pCeCapsParams) { @@ -2925,6 +3114,12 @@ static inline NV_STATUS subdeviceCtrlCmdCeUpdatePceLceMappings_DISPATCH(struct S return pSubdevice->__subdeviceCtrlCmdCeUpdatePceLceMappings__(pSubdevice, pCeUpdatePceLceMappingsParams); } +NV_STATUS subdeviceCtrlCmdCeGetCapsV2_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CE_GET_CAPS_V2_PARAMS *pCeCapsParams); + +static inline NV_STATUS subdeviceCtrlCmdCeGetCapsV2_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CE_GET_CAPS_V2_PARAMS *pCeCapsParams) { + return pSubdevice->__subdeviceCtrlCmdCeGetCapsV2__(pSubdevice, pCeCapsParams); +} + NV_STATUS subdeviceCtrlCmdFlcnGetDmemUsage_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS *pFlcnDmemUsageParams); static inline NV_STATUS subdeviceCtrlCmdFlcnGetDmemUsage_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS *pFlcnDmemUsageParams) { @@ -3243,18 +3438,6 @@ static inline NV_STATUS subdeviceCtrlCmdInternalGetSmcMode_DISPATCH(struct Subde return pSubdevice->__subdeviceCtrlCmdInternalGetSmcMode__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdInternalBusBindLocalGfidForP2p_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_BUS_BIND_LOCAL_GFID_FOR_P2P_PARAMS *pParams); - -static inline NV_STATUS subdeviceCtrlCmdInternalBusBindLocalGfidForP2p_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_BUS_BIND_LOCAL_GFID_FOR_P2P_PARAMS *pParams) { - return pSubdevice->__subdeviceCtrlCmdInternalBusBindLocalGfidForP2p__(pSubdevice, pParams); -} - -NV_STATUS subdeviceCtrlCmdInternalBusBindRemoteGfidForP2p_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_BUS_BIND_REMOTE_GFID_FOR_P2P_PARAMS *pParams); - -static inline NV_STATUS subdeviceCtrlCmdInternalBusBindRemoteGfidForP2p_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_BUS_BIND_REMOTE_GFID_FOR_P2P_PARAMS *pParams) { - return pSubdevice->__subdeviceCtrlCmdInternalBusBindRemoteGfidForP2p__(pSubdevice, pParams); -} - NV_STATUS subdeviceCtrlCmdInternalBusFlushWithSysmembar_IMPL(struct Subdevice *pSubdevice); static inline NV_STATUS subdeviceCtrlCmdInternalBusFlushWithSysmembar_DISPATCH(struct Subdevice *pSubdevice) { @@ -3321,6 +3504,12 @@ static inline NV_STATUS subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultB return pSubdevice->__subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer__(pSubdevice); } +NV_STATUS subdeviceCtrlCmdInternalGmmuCopyReservedSplitGVASpacePdesServer_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS *pCopyServerReservedPdesParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalGmmuCopyReservedSplitGVASpacePdesServer_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS *pCopyServerReservedPdesParams) { + return pSubdevice->__subdeviceCtrlCmdInternalGmmuCopyReservedSplitGVASpacePdesServer__(pSubdevice, pCopyServerReservedPdesParams); +} + NV_STATUS subdeviceCtrlCmdCeGetPhysicalCaps_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CE_GET_CAPS_V2_PARAMS *pCeCapsParams); static inline NV_STATUS subdeviceCtrlCmdCeGetPhysicalCaps_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CE_GET_CAPS_V2_PARAMS *pCeCapsParams) { @@ -3423,6 +3612,12 @@ static inline NV_STATUS subdeviceCtrlCmdInternalPerfCfControllerSetMaxVGpuVMCoun return pSubdevice->__subdeviceCtrlCmdInternalPerfCfControllerSetMaxVGpuVMCount__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdInternalPerfGetAuxPowerState_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalPerfGetAuxPowerState_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalPerfGetAuxPowerState__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdBifGetStaticInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdBifGetStaticInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS *pParams) { @@ -3495,6 +3690,18 @@ static inline NV_STATUS subdeviceCtrlCmdInternalNvlinkGetTotalNumLinksPerIoctrl_ return pSubdevice->__subdeviceCtrlCmdInternalNvlinkGetTotalNumLinksPerIoctrl__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdInternalSetP2pCaps_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalSetP2pCaps_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalSetP2pCaps__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalRemoveP2pCaps_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalRemoveP2pCaps_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalRemoveP2pCaps__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdInternalGetPcieP2pCaps_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdInternalGetPcieP2pCaps_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS *pParams) { @@ -3507,6 +3714,138 @@ static inline NV_STATUS subdeviceCtrlCmdInternalGetCoherentFbApertureSize_DISPAT return pSubdevice->__subdeviceCtrlCmdInternalGetCoherentFbApertureSize__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdInternalInitGpuIntr_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS *pAttachParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalInitGpuIntr_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS *pAttachParams) { + return pSubdevice->__subdeviceCtrlCmdInternalInitGpuIntr__(pSubdevice, pAttachParams); +} + +NV_STATUS subdeviceCtrlCmdInternalGsyncOptimizeTiming_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS *pAttachParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalGsyncOptimizeTiming_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS *pAttachParams) { + return pSubdevice->__subdeviceCtrlCmdInternalGsyncOptimizeTiming__(pSubdevice, pAttachParams); +} + +NV_STATUS subdeviceCtrlCmdInternalGsyncGetDisplayIds_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS *pAttachParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalGsyncGetDisplayIds_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS *pAttachParams) { + return pSubdevice->__subdeviceCtrlCmdInternalGsyncGetDisplayIds__(pSubdevice, pAttachParams); +} + +NV_STATUS subdeviceCtrlCmdInternalGsyncSetStereoSync_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS *pAttachParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalGsyncSetStereoSync_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS *pAttachParams) { + return pSubdevice->__subdeviceCtrlCmdInternalGsyncSetStereoSync__(pSubdevice, pAttachParams); +} + +NV_STATUS subdeviceCtrlCmdInternalGsyncGetVactiveLines_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS *pAttachParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalGsyncGetVactiveLines_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS *pAttachParams) { + return pSubdevice->__subdeviceCtrlCmdInternalGsyncGetVactiveLines__(pSubdevice, pAttachParams); +} + +NV_STATUS subdeviceCtrlCmdInternalGsyncIsDisplayIdValid_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS *pAttachParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalGsyncIsDisplayIdValid_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS *pAttachParams) { + return pSubdevice->__subdeviceCtrlCmdInternalGsyncIsDisplayIdValid__(pSubdevice, pAttachParams); +} + +NV_STATUS subdeviceCtrlCmdInternalGsyncSetOrRestoreGpioRasterSync_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS *pAttachParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalGsyncSetOrRestoreGpioRasterSync_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS *pAttachParams) { + return pSubdevice->__subdeviceCtrlCmdInternalGsyncSetOrRestoreGpioRasterSync__(pSubdevice, pAttachParams); +} + +NV_STATUS subdeviceCtrlCmdInternalFbsrInit_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalFbsrInit_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalFbsrInit__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalFbsrSendRegionInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalFbsrSendRegionInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalFbsrSendRegionInfo__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalPostInitBrightcStateLoad_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalPostInitBrightcStateLoad_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalPostInitBrightcStateLoad__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit_IMPL(struct Subdevice *pSubdevice); + +static inline NV_STATUS subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit_DISPATCH(struct Subdevice *pSubdevice) { + return pSubdevice->__subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit__(pSubdevice); +} + +NV_STATUS subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdVgpuMgrInternalEnumerateVgpuPerPgpu_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdVgpuMgrInternalEnumerateVgpuPerPgpu_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdVgpuMgrInternalEnumerateVgpuPerPgpu__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdVgpuMgrInternalClearGuestVmInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdVgpuMgrInternalClearGuestVmInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdVgpuMgrInternalClearGuestVmInfo__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdVgpuMgrInternalGetVgpuFbUsage_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdVgpuMgrInternalGetVgpuFbUsage_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdVgpuMgrInternalGetVgpuFbUsage__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdVgpuMgrInternalSetVgpuEncoderCapacity_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdVgpuMgrInternalSetVgpuEncoderCapacity_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdVgpuMgrInternalSetVgpuEncoderCapacity__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdVgpuMgrInternalCleanupGspVgpuPluginResources_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdVgpuMgrInternalCleanupGspVgpuPluginResources_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdVgpuMgrInternalCleanupGspVgpuPluginResources__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdVgpuMgrInternalGetPgpuFsEncoding_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdVgpuMgrInternalGetPgpuFsEncoding_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdVgpuMgrInternalGetPgpuFsEncoding__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdVgpuMgrInternalGetPgpuMigrationSupport_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdVgpuMgrInternalGetPgpuMigrationSupport_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdVgpuMgrInternalGetPgpuMigrationSupport__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdVgpuMgrInternalSetVgpuMgrConfig_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdVgpuMgrInternalSetVgpuMgrConfig_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdVgpuMgrInternalSetVgpuMgrConfig__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdGetAvailableHshubMask_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdGetAvailableHshubMask_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS *pParams) { @@ -3519,10 +3858,16 @@ static inline NV_STATUS subdeviceCtrlCmdCcuMap_DISPATCH(struct Subdevice *pSubde return pSubdevice->__subdeviceCtrlCmdCcuMap__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdCcuUnmap_IMPL(struct Subdevice *pSubdevice); +NV_STATUS subdeviceCtrlCmdCcuUnmap_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS *pParams); -static inline NV_STATUS subdeviceCtrlCmdCcuUnmap_DISPATCH(struct Subdevice *pSubdevice) { - return pSubdevice->__subdeviceCtrlCmdCcuUnmap__(pSubdevice); +static inline NV_STATUS subdeviceCtrlCmdCcuUnmap_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdCcuUnmap__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdCcuSetStreamState_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdCcuSetStreamState_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdCcuSetStreamState__(pSubdevice, pParams); } static inline NvBool subdeviceShareCallback_DISPATCH(struct Subdevice *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { @@ -3605,6 +3950,10 @@ static inline NvBool subdeviceCanCopy_DISPATCH(struct Subdevice *pResource) { return pResource->__subdeviceCanCopy__(pResource); } +static inline NV_STATUS subdeviceIsDuplicate_DISPATCH(struct Subdevice *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__subdeviceIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline PEVENTNOTIFICATION *subdeviceGetNotificationListPtr_DISPATCH(struct Subdevice *pNotifier) { return pNotifier->__subdeviceGetNotificationListPtr__(pNotifier); } @@ -3625,7 +3974,7 @@ static inline NV_STATUS subdeviceSetPerfmonReservation(struct Subdevice *pSubdev return NV_OK; } -static inline NV_STATUS subdeviceResetTGP(struct Subdevice *pSubdevice) { +static inline NV_STATUS subdeviceUnsetDynamicBoostLimit(struct Subdevice *pSubdevice) { return NV_OK; } @@ -3642,30 +3991,13 @@ static inline void subdeviceReleaseNvlinkErrorInjectionMode(struct Subdevice *pS } NV_STATUS subdeviceConstruct_IMPL(struct Subdevice *arg_pResource, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_subdeviceConstruct(arg_pResource, arg_pCallContext, arg_pParams) subdeviceConstruct_IMPL(arg_pResource, arg_pCallContext, arg_pParams) void subdeviceDestruct_IMPL(struct Subdevice *pResource); + #define __nvoc_subdeviceDestruct(pResource) subdeviceDestruct_IMPL(pResource) -NV_STATUS subdeviceAddP2PApi_IMPL(struct Subdevice *pSubdevice, struct P2PApi *pP2PApi); -#ifdef __nvoc_subdevice_h_disabled -static inline NV_STATUS subdeviceAddP2PApi(struct Subdevice *pSubdevice, struct P2PApi *pP2PApi) { - NV_ASSERT_FAILED_PRECOMP("Subdevice was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_subdevice_h_disabled -#define subdeviceAddP2PApi(pSubdevice, pP2PApi) subdeviceAddP2PApi_IMPL(pSubdevice, pP2PApi) -#endif //__nvoc_subdevice_h_disabled - -NV_STATUS subdeviceDelP2PApi_IMPL(struct Subdevice *pSubdevice, struct P2PApi *pP2PApi); -#ifdef __nvoc_subdevice_h_disabled -static inline NV_STATUS subdeviceDelP2PApi(struct Subdevice *pSubdevice, struct P2PApi *pP2PApi) { - NV_ASSERT_FAILED_PRECOMP("Subdevice was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_subdevice_h_disabled -#define subdeviceDelP2PApi(pSubdevice, pP2PApi) subdeviceDelP2PApi_IMPL(pSubdevice, pP2PApi) -#endif //__nvoc_subdevice_h_disabled - void subdeviceRestoreGrTickFreq_IMPL(struct Subdevice *pSubdevice, struct CALL_CONTEXT *pCallContext); + #ifdef __nvoc_subdevice_h_disabled static inline void subdeviceRestoreGrTickFreq(struct Subdevice *pSubdevice, struct CALL_CONTEXT *pCallContext) { NV_ASSERT_FAILED_PRECOMP("Subdevice was disabled!"); @@ -3675,6 +4007,7 @@ static inline void subdeviceRestoreGrTickFreq(struct Subdevice *pSubdevice, stru #endif //__nvoc_subdevice_h_disabled void subdeviceRestoreWatchdog_IMPL(struct Subdevice *pSubdevice); + #ifdef __nvoc_subdevice_h_disabled static inline void subdeviceRestoreWatchdog(struct Subdevice *pSubdevice) { NV_ASSERT_FAILED_PRECOMP("Subdevice was disabled!"); @@ -3684,6 +4017,7 @@ static inline void subdeviceRestoreWatchdog(struct Subdevice *pSubdevice) { #endif //__nvoc_subdevice_h_disabled void subdeviceUnsetGpuDebugMode_IMPL(struct Subdevice *pSubdevice); + #ifdef __nvoc_subdevice_h_disabled static inline void subdeviceUnsetGpuDebugMode(struct Subdevice *pSubdevice) { NV_ASSERT_FAILED_PRECOMP("Subdevice was disabled!"); @@ -3693,6 +4027,7 @@ static inline void subdeviceUnsetGpuDebugMode(struct Subdevice *pSubdevice) { #endif //__nvoc_subdevice_h_disabled void subdeviceReleaseComputeModeReservation_IMPL(struct Subdevice *pSubdevice, struct CALL_CONTEXT *pCallContext); + #ifdef __nvoc_subdevice_h_disabled static inline void subdeviceReleaseComputeModeReservation(struct Subdevice *pSubdevice, struct CALL_CONTEXT *pCallContext) { NV_ASSERT_FAILED_PRECOMP("Subdevice was disabled!"); @@ -3702,10 +4037,13 @@ static inline void subdeviceReleaseComputeModeReservation(struct Subdevice *pSub #endif //__nvoc_subdevice_h_disabled NV_STATUS subdeviceGetByHandle_IMPL(struct RsClient *pClient, NvHandle hSubdevice, struct Subdevice **ppSubdevice); + #define subdeviceGetByHandle(pClient, hSubdevice, ppSubdevice) subdeviceGetByHandle_IMPL(pClient, hSubdevice, ppSubdevice) NV_STATUS subdeviceGetByGpu_IMPL(struct RsClient *pClient, struct OBJGPU *pGpu, struct Subdevice **ppSubdevice); + #define subdeviceGetByGpu(pClient, pGpu, ppSubdevice) subdeviceGetByGpu_IMPL(pClient, pGpu, ppSubdevice) NV_STATUS subdeviceGetByInstance_IMPL(struct RsClient *pClient, NvHandle hDevice, NvU32 subDeviceInst, struct Subdevice **ppSubdevice); + #define subdeviceGetByInstance(pClient, hDevice, subDeviceInst, ppSubdevice) subdeviceGetByInstance_IMPL(pClient, hDevice, subDeviceInst, ppSubdevice) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_sw_test_nvoc.c b/src/nvidia/generated/g_sw_test_nvoc.c index 771bb74dd..b49fe2604 100644 --- a/src/nvidia/generated/g_sw_test_nvoc.c +++ b/src/nvidia/generated/g_sw_test_nvoc.c @@ -220,6 +220,10 @@ static void __nvoc_thunk_RsResource_swtestPreDestruct(struct SoftwareMethodTest resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SoftwareMethodTest_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_RsResource_swtestIsDuplicate(struct SoftwareMethodTest *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SoftwareMethodTest_RsResource.offset), hMemory, pDuplicate); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_swtestGetNotificationListPtr(struct SoftwareMethodTest *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_SoftwareMethodTest_Notifier.offset)); } @@ -327,6 +331,8 @@ static void __nvoc_init_funcTable_SoftwareMethodTest_1(SoftwareMethodTest *pThis pThis->__swtestPreDestruct__ = &__nvoc_thunk_RsResource_swtestPreDestruct; + pThis->__swtestIsDuplicate__ = &__nvoc_thunk_RsResource_swtestIsDuplicate; + pThis->__swtestGetNotificationListPtr__ = &__nvoc_thunk_Notifier_swtestGetNotificationListPtr; pThis->__swtestGetNotificationShare__ = &__nvoc_thunk_Notifier_swtestGetNotificationShare; diff --git a/src/nvidia/generated/g_sw_test_nvoc.h b/src/nvidia/generated/g_sw_test_nvoc.h index db82b9cb0..b98b55845 100644 --- a/src/nvidia/generated/g_sw_test_nvoc.h +++ b/src/nvidia/generated/g_sw_test_nvoc.h @@ -82,6 +82,7 @@ struct SoftwareMethodTest { NV_STATUS (*__swtestUnregisterEvent__)(struct SoftwareMethodTest *, NvHandle, NvHandle, NvHandle, NvHandle); NvBool (*__swtestCanCopy__)(struct SoftwareMethodTest *); void (*__swtestPreDestruct__)(struct SoftwareMethodTest *); + NV_STATUS (*__swtestIsDuplicate__)(struct SoftwareMethodTest *, NvHandle, NvBool *); PEVENTNOTIFICATION *(*__swtestGetNotificationListPtr__)(struct SoftwareMethodTest *); struct NotifShare *(*__swtestGetNotificationShare__)(struct SoftwareMethodTest *); NV_STATUS (*__swtestMap__)(struct SoftwareMethodTest *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -141,6 +142,7 @@ NV_STATUS __nvoc_objCreate_SoftwareMethodTest(SoftwareMethodTest**, Dynamic*, Nv #define swtestUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) swtestUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define swtestCanCopy(pResource) swtestCanCopy_DISPATCH(pResource) #define swtestPreDestruct(pResource) swtestPreDestruct_DISPATCH(pResource) +#define swtestIsDuplicate(pResource, hMemory, pDuplicate) swtestIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define swtestGetNotificationListPtr(pNotifier) swtestGetNotificationListPtr_DISPATCH(pNotifier) #define swtestGetNotificationShare(pNotifier) swtestGetNotificationShare_DISPATCH(pNotifier) #define swtestMap(pGpuResource, pCallContext, pParams, pCpuMapping) swtestMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -247,6 +249,10 @@ static inline void swtestPreDestruct_DISPATCH(struct SoftwareMethodTest *pResour pResource->__swtestPreDestruct__(pResource); } +static inline NV_STATUS swtestIsDuplicate_DISPATCH(struct SoftwareMethodTest *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__swtestIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline PEVENTNOTIFICATION *swtestGetNotificationListPtr_DISPATCH(struct SoftwareMethodTest *pNotifier) { return pNotifier->__swtestGetNotificationListPtr__(pNotifier); } @@ -264,8 +270,10 @@ static inline NV_STATUS swtestGetOrAllocNotifShare_DISPATCH(struct SoftwareMetho } NV_STATUS swtestConstruct_IMPL(struct SoftwareMethodTest *arg_pSwTest, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_swtestConstruct(arg_pSwTest, arg_pCallContext, arg_pParams) swtestConstruct_IMPL(arg_pSwTest, arg_pCallContext, arg_pParams) void swtestDestruct_IMPL(struct SoftwareMethodTest *pSwTest); + #define __nvoc_swtestDestruct(pSwTest) swtestDestruct_IMPL(pSwTest) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_swintr_nvoc.c b/src/nvidia/generated/g_swintr_nvoc.c index b1b7e5705..7fdc26490 100644 --- a/src/nvidia/generated/g_swintr_nvoc.c +++ b/src/nvidia/generated/g_swintr_nvoc.c @@ -17,14 +17,12 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJENGSTATE; -extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJINTRABLE; - extern const struct NVOC_CLASS_DEF __nvoc_class_def_IntrService; -void __nvoc_init_SwIntr(SwIntr*, RmHalspecOwner* ); -void __nvoc_init_funcTable_SwIntr(SwIntr*, RmHalspecOwner* ); -NV_STATUS __nvoc_ctor_SwIntr(SwIntr*, RmHalspecOwner* ); -void __nvoc_init_dataField_SwIntr(SwIntr*, RmHalspecOwner* ); +void __nvoc_init_SwIntr(SwIntr*); +void __nvoc_init_funcTable_SwIntr(SwIntr*); +NV_STATUS __nvoc_ctor_SwIntr(SwIntr*); +void __nvoc_init_dataField_SwIntr(SwIntr*); void __nvoc_dtor_SwIntr(SwIntr*); extern const struct NVOC_EXPORT_INFO __nvoc_export_info_SwIntr; @@ -46,12 +44,6 @@ static const struct NVOC_RTTI __nvoc_rtti_SwIntr_OBJENGSTATE = { /*offset=*/ NV_OFFSETOF(SwIntr, __nvoc_base_OBJENGSTATE), }; -static const struct NVOC_RTTI __nvoc_rtti_SwIntr_OBJINTRABLE = { - /*pClassDef=*/ &__nvoc_class_def_OBJINTRABLE, - /*dtor=*/ &__nvoc_destructFromBase, - /*offset=*/ NV_OFFSETOF(SwIntr, __nvoc_base_OBJINTRABLE), -}; - static const struct NVOC_RTTI __nvoc_rtti_SwIntr_IntrService = { /*pClassDef=*/ &__nvoc_class_def_IntrService, /*dtor=*/ &__nvoc_destructFromBase, @@ -59,11 +51,10 @@ static const struct NVOC_RTTI __nvoc_rtti_SwIntr_IntrService = { }; static const struct NVOC_CASTINFO __nvoc_castinfo_SwIntr = { - /*numRelatives=*/ 5, + /*numRelatives=*/ 4, /*relatives=*/ { &__nvoc_rtti_SwIntr_SwIntr, &__nvoc_rtti_SwIntr_IntrService, - &__nvoc_rtti_SwIntr_OBJINTRABLE, &__nvoc_rtti_SwIntr_OBJENGSTATE, &__nvoc_rtti_SwIntr_Object, }, @@ -84,7 +75,7 @@ const struct NVOC_CLASS_DEF __nvoc_class_def_SwIntr = /*pExportInfo=*/ &__nvoc_export_info_SwIntr }; -static void __nvoc_thunk_SwIntr_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pSwIntr, IntrServiceRecord pRecords[155]) { +static void __nvoc_thunk_SwIntr_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pSwIntr, IntrServiceRecord pRecords[163]) { swintrRegisterIntrService(pGpu, (struct SwIntr *)(((unsigned char *)pSwIntr) - __nvoc_rtti_SwIntr_IntrService.offset), pRecords); } @@ -92,34 +83,6 @@ static NvU32 __nvoc_thunk_SwIntr_intrservServiceInterrupt(OBJGPU *pGpu, struct I return swintrServiceInterrupt(pGpu, (struct SwIntr *)(((unsigned char *)pSwIntr) - __nvoc_rtti_SwIntr_IntrService.offset), pParams); } -static NV_STATUS __nvoc_thunk_SwIntr_intrableGetKernelIntrVectors(OBJGPU *pGpu, struct OBJINTRABLE *pSwIntr, NvU32 maxIntrs, NvU32 *pIntrs, NvU32 *pMcEngineIdxs, NvU32 *pCount) { - return swintrGetKernelIntrVectors(pGpu, (struct SwIntr *)(((unsigned char *)pSwIntr) - __nvoc_rtti_SwIntr_OBJINTRABLE.offset), maxIntrs, pIntrs, pMcEngineIdxs, pCount); -} - -static void __nvoc_thunk_OBJENGSTATE_swintrStateDestroy(POBJGPU pGpu, struct SwIntr *pEngstate) { - engstateStateDestroy(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset)); -} - -static void __nvoc_thunk_OBJENGSTATE_swintrFreeTunableState(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunableState) { - engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset), pTunableState); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_swintrCompareTunableState(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunables1, void *pTunables2) { - return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset), pTunables1, pTunables2); -} - -static NvBool __nvoc_thunk_IntrService_swintrClearInterrupt(OBJGPU *pGpu, struct SwIntr *pIntrService, IntrServiceClearInterruptArguments *pParams) { - return intrservClearInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_SwIntr_IntrService.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_OBJINTRABLE_swintrGetNotificationIntrVector(OBJGPU *pGpu, struct SwIntr *pIntrable, NvU32 *pIntrVector) { - return intrableGetNotificationIntrVector(pGpu, (struct OBJINTRABLE *)(((unsigned char *)pIntrable) + __nvoc_rtti_SwIntr_OBJINTRABLE.offset), pIntrVector); -} - -static NvBool __nvoc_thunk_OBJENGSTATE_swintrIsPresent(POBJGPU pGpu, struct SwIntr *pEngstate) { - return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset)); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_swintrReconcileTunableState(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunableState) { return engstateReconcileTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset), pTunableState); } @@ -128,16 +91,12 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_swintrStateLoad(POBJGPU pGpu, struct S return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJINTRABLE_swintrGetPhysicalIntrVectors(OBJGPU *pGpu, struct SwIntr *pIntrable, NvU32 maxIntrs, NvU32 *pIntrs, NvU32 *pMcEngineIdxs, NvU32 *pCount) { - return intrableGetPhysicalIntrVectors(pGpu, (struct OBJINTRABLE *)(((unsigned char *)pIntrable) + __nvoc_rtti_SwIntr_OBJINTRABLE.offset), maxIntrs, pIntrs, pMcEngineIdxs, pCount); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_swintrStateUnload(POBJGPU pGpu, struct SwIntr *pEngstate, NvU32 arg0) { return engstateStateUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJINTRABLE_swintrSetNotificationIntrVector(OBJGPU *pGpu, struct SwIntr *pIntrable, NvU32 intrVector) { - return intrableSetNotificationIntrVector(pGpu, (struct OBJINTRABLE *)(((unsigned char *)pIntrable) + __nvoc_rtti_SwIntr_OBJINTRABLE.offset), intrVector); +static NV_STATUS __nvoc_thunk_IntrService_swintrServiceNotificationInterrupt(OBJGPU *pGpu, struct SwIntr *pIntrService, IntrServiceServiceNotificationInterruptArguments *pParams) { + return intrservServiceNotificationInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_SwIntr_IntrService.offset), pParams); } static NV_STATUS __nvoc_thunk_OBJENGSTATE_swintrStateInitLocked(POBJGPU pGpu, struct SwIntr *pEngstate) { @@ -152,12 +111,12 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_swintrStatePostUnload(POBJGPU pGpu, st return engstateStatePostUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_swintrStatePreUnload(POBJGPU pGpu, struct SwIntr *pEngstate, NvU32 arg0) { - return engstateStatePreUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset), arg0); +static void __nvoc_thunk_OBJENGSTATE_swintrStateDestroy(POBJGPU pGpu, struct SwIntr *pEngstate) { + engstateStateDestroy(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_swintrGetTunableState(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunableState) { - return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset), pTunableState); +static NV_STATUS __nvoc_thunk_OBJENGSTATE_swintrStatePreUnload(POBJGPU pGpu, struct SwIntr *pEngstate, NvU32 arg0) { + return engstateStatePreUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset), arg0); } static NV_STATUS __nvoc_thunk_OBJENGSTATE_swintrStateInitUnlocked(POBJGPU pGpu, struct SwIntr *pEngstate) { @@ -176,8 +135,20 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_swintrStatePreInitUnlocked(POBJGPU pGp return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_IntrService_swintrServiceNotificationInterrupt(OBJGPU *pGpu, struct SwIntr *pIntrService, IntrServiceServiceNotificationInterruptArguments *pParams) { - return intrservServiceNotificationInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_SwIntr_IntrService.offset), pParams); +static NV_STATUS __nvoc_thunk_OBJENGSTATE_swintrGetTunableState(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunableState) { + return engstateGetTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset), pTunableState); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_swintrCompareTunableState(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunables1, void *pTunables2) { + return engstateCompareTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset), pTunables1, pTunables2); +} + +static void __nvoc_thunk_OBJENGSTATE_swintrFreeTunableState(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunableState) { + engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset), pTunableState); +} + +static NvBool __nvoc_thunk_IntrService_swintrClearInterrupt(OBJGPU *pGpu, struct SwIntr *pIntrService, IntrServiceClearInterruptArguments *pParams) { + return intrservClearInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_SwIntr_IntrService.offset), pParams); } static NV_STATUS __nvoc_thunk_OBJENGSTATE_swintrStatePostLoad(POBJGPU pGpu, struct SwIntr *pEngstate, NvU32 arg0) { @@ -196,6 +167,10 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_swintrConstructEngine(POBJGPU pGpu, st return engstateConstructEngine(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset), arg0); } +static NvBool __nvoc_thunk_OBJENGSTATE_swintrIsPresent(POBJGPU pGpu, struct SwIntr *pEngstate) { + return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_SwIntr_OBJENGSTATE.offset)); +} + const struct NVOC_EXPORT_INFO __nvoc_export_info_SwIntr = { /*numEntries=*/ 0, @@ -203,45 +178,29 @@ const struct NVOC_EXPORT_INFO __nvoc_export_info_SwIntr = }; void __nvoc_dtor_OBJENGSTATE(OBJENGSTATE*); -void __nvoc_dtor_OBJINTRABLE(OBJINTRABLE*); void __nvoc_dtor_IntrService(IntrService*); void __nvoc_dtor_SwIntr(SwIntr *pThis) { __nvoc_dtor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); - __nvoc_dtor_OBJINTRABLE(&pThis->__nvoc_base_OBJINTRABLE); __nvoc_dtor_IntrService(&pThis->__nvoc_base_IntrService); PORT_UNREFERENCED_VARIABLE(pThis); } -void __nvoc_init_dataField_SwIntr(SwIntr *pThis, RmHalspecOwner *pRmhalspecowner) { - ChipHal *chipHal = &pRmhalspecowner->chipHal; - const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; - RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; - const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; +void __nvoc_init_dataField_SwIntr(SwIntr *pThis) { PORT_UNREFERENCED_VARIABLE(pThis); - PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); - PORT_UNREFERENCED_VARIABLE(chipHal); - PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); - PORT_UNREFERENCED_VARIABLE(rmVariantHal); - PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); } -NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* , RmHalspecOwner* ); -NV_STATUS __nvoc_ctor_OBJINTRABLE(OBJINTRABLE* , RmHalspecOwner* ); -NV_STATUS __nvoc_ctor_IntrService(IntrService* , RmHalspecOwner* ); -NV_STATUS __nvoc_ctor_SwIntr(SwIntr *pThis, RmHalspecOwner *pRmhalspecowner) { +NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); +NV_STATUS __nvoc_ctor_IntrService(IntrService* ); +NV_STATUS __nvoc_ctor_SwIntr(SwIntr *pThis) { NV_STATUS status = NV_OK; - status = __nvoc_ctor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE, pRmhalspecowner); + status = __nvoc_ctor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); if (status != NV_OK) goto __nvoc_ctor_SwIntr_fail_OBJENGSTATE; - status = __nvoc_ctor_OBJINTRABLE(&pThis->__nvoc_base_OBJINTRABLE, pRmhalspecowner); - if (status != NV_OK) goto __nvoc_ctor_SwIntr_fail_OBJINTRABLE; - status = __nvoc_ctor_IntrService(&pThis->__nvoc_base_IntrService, pRmhalspecowner); + status = __nvoc_ctor_IntrService(&pThis->__nvoc_base_IntrService); if (status != NV_OK) goto __nvoc_ctor_SwIntr_fail_IntrService; - __nvoc_init_dataField_SwIntr(pThis, pRmhalspecowner); + __nvoc_init_dataField_SwIntr(pThis); goto __nvoc_ctor_SwIntr_exit; // Success __nvoc_ctor_SwIntr_fail_IntrService: - __nvoc_dtor_OBJINTRABLE(&pThis->__nvoc_base_OBJINTRABLE); -__nvoc_ctor_SwIntr_fail_OBJINTRABLE: __nvoc_dtor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); __nvoc_ctor_SwIntr_fail_OBJENGSTATE: __nvoc_ctor_SwIntr_exit: @@ -249,59 +208,24 @@ __nvoc_ctor_SwIntr_exit: return status; } -static void __nvoc_init_funcTable_SwIntr_1(SwIntr *pThis, RmHalspecOwner *pRmhalspecowner) { - ChipHal *chipHal = &pRmhalspecowner->chipHal; - const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; - RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; - const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; +static void __nvoc_init_funcTable_SwIntr_1(SwIntr *pThis) { PORT_UNREFERENCED_VARIABLE(pThis); - PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); - PORT_UNREFERENCED_VARIABLE(chipHal); - PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); - PORT_UNREFERENCED_VARIABLE(rmVariantHal); - PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); pThis->__swintrRegisterIntrService__ = &swintrRegisterIntrService_IMPL; pThis->__swintrServiceInterrupt__ = &swintrServiceInterrupt_IMPL; - // Hal function -- swintrGetKernelIntrVectors - if (0) - { - } - // default - else - { - pThis->__swintrGetKernelIntrVectors__ = &swintrGetKernelIntrVectors_46f6a7; - } - pThis->__nvoc_base_IntrService.__intrservRegisterIntrService__ = &__nvoc_thunk_SwIntr_intrservRegisterIntrService; pThis->__nvoc_base_IntrService.__intrservServiceInterrupt__ = &__nvoc_thunk_SwIntr_intrservServiceInterrupt; - pThis->__nvoc_base_OBJINTRABLE.__intrableGetKernelIntrVectors__ = &__nvoc_thunk_SwIntr_intrableGetKernelIntrVectors; - - pThis->__swintrStateDestroy__ = &__nvoc_thunk_OBJENGSTATE_swintrStateDestroy; - - pThis->__swintrFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_swintrFreeTunableState; - - pThis->__swintrCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_swintrCompareTunableState; - - pThis->__swintrClearInterrupt__ = &__nvoc_thunk_IntrService_swintrClearInterrupt; - - pThis->__swintrGetNotificationIntrVector__ = &__nvoc_thunk_OBJINTRABLE_swintrGetNotificationIntrVector; - - pThis->__swintrIsPresent__ = &__nvoc_thunk_OBJENGSTATE_swintrIsPresent; - pThis->__swintrReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_swintrReconcileTunableState; pThis->__swintrStateLoad__ = &__nvoc_thunk_OBJENGSTATE_swintrStateLoad; - pThis->__swintrGetPhysicalIntrVectors__ = &__nvoc_thunk_OBJINTRABLE_swintrGetPhysicalIntrVectors; - pThis->__swintrStateUnload__ = &__nvoc_thunk_OBJENGSTATE_swintrStateUnload; - pThis->__swintrSetNotificationIntrVector__ = &__nvoc_thunk_OBJINTRABLE_swintrSetNotificationIntrVector; + pThis->__swintrServiceNotificationInterrupt__ = &__nvoc_thunk_IntrService_swintrServiceNotificationInterrupt; pThis->__swintrStateInitLocked__ = &__nvoc_thunk_OBJENGSTATE_swintrStateInitLocked; @@ -309,9 +233,9 @@ static void __nvoc_init_funcTable_SwIntr_1(SwIntr *pThis, RmHalspecOwner *pRmhal pThis->__swintrStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_swintrStatePostUnload; - pThis->__swintrStatePreUnload__ = &__nvoc_thunk_OBJENGSTATE_swintrStatePreUnload; + pThis->__swintrStateDestroy__ = &__nvoc_thunk_OBJENGSTATE_swintrStateDestroy; - pThis->__swintrGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_swintrGetTunableState; + pThis->__swintrStatePreUnload__ = &__nvoc_thunk_OBJENGSTATE_swintrStatePreUnload; pThis->__swintrStateInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_swintrStateInitUnlocked; @@ -321,7 +245,13 @@ static void __nvoc_init_funcTable_SwIntr_1(SwIntr *pThis, RmHalspecOwner *pRmhal pThis->__swintrStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_swintrStatePreInitUnlocked; - pThis->__swintrServiceNotificationInterrupt__ = &__nvoc_thunk_IntrService_swintrServiceNotificationInterrupt; + pThis->__swintrGetTunableState__ = &__nvoc_thunk_OBJENGSTATE_swintrGetTunableState; + + pThis->__swintrCompareTunableState__ = &__nvoc_thunk_OBJENGSTATE_swintrCompareTunableState; + + pThis->__swintrFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_swintrFreeTunableState; + + pThis->__swintrClearInterrupt__ = &__nvoc_thunk_IntrService_swintrClearInterrupt; pThis->__swintrStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_swintrStatePostLoad; @@ -330,32 +260,30 @@ static void __nvoc_init_funcTable_SwIntr_1(SwIntr *pThis, RmHalspecOwner *pRmhal pThis->__swintrSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_swintrSetTunableState; pThis->__swintrConstructEngine__ = &__nvoc_thunk_OBJENGSTATE_swintrConstructEngine; + + pThis->__swintrIsPresent__ = &__nvoc_thunk_OBJENGSTATE_swintrIsPresent; } -void __nvoc_init_funcTable_SwIntr(SwIntr *pThis, RmHalspecOwner *pRmhalspecowner) { - __nvoc_init_funcTable_SwIntr_1(pThis, pRmhalspecowner); +void __nvoc_init_funcTable_SwIntr(SwIntr *pThis) { + __nvoc_init_funcTable_SwIntr_1(pThis); } -void __nvoc_init_OBJENGSTATE(OBJENGSTATE*, RmHalspecOwner* ); -void __nvoc_init_OBJINTRABLE(OBJINTRABLE*, RmHalspecOwner* ); -void __nvoc_init_IntrService(IntrService*, RmHalspecOwner* ); -void __nvoc_init_SwIntr(SwIntr *pThis, RmHalspecOwner *pRmhalspecowner) { +void __nvoc_init_OBJENGSTATE(OBJENGSTATE*); +void __nvoc_init_IntrService(IntrService*); +void __nvoc_init_SwIntr(SwIntr *pThis) { pThis->__nvoc_pbase_SwIntr = pThis; pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object; pThis->__nvoc_pbase_OBJENGSTATE = &pThis->__nvoc_base_OBJENGSTATE; - pThis->__nvoc_pbase_OBJINTRABLE = &pThis->__nvoc_base_OBJINTRABLE; pThis->__nvoc_pbase_IntrService = &pThis->__nvoc_base_IntrService; - __nvoc_init_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE, pRmhalspecowner); - __nvoc_init_OBJINTRABLE(&pThis->__nvoc_base_OBJINTRABLE, pRmhalspecowner); - __nvoc_init_IntrService(&pThis->__nvoc_base_IntrService, pRmhalspecowner); - __nvoc_init_funcTable_SwIntr(pThis, pRmhalspecowner); + __nvoc_init_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); + __nvoc_init_IntrService(&pThis->__nvoc_base_IntrService); + __nvoc_init_funcTable_SwIntr(pThis); } NV_STATUS __nvoc_objCreate_SwIntr(SwIntr **ppThis, Dynamic *pParent, NvU32 createFlags) { NV_STATUS status; Object *pParentObj; SwIntr *pThis; - RmHalspecOwner *pRmhalspecowner; pThis = portMemAllocNonPaged(sizeof(SwIntr)); if (pThis == NULL) return NV_ERR_NO_MEMORY; @@ -374,12 +302,8 @@ NV_STATUS __nvoc_objCreate_SwIntr(SwIntr **ppThis, Dynamic *pParent, NvU32 creat pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.pParent = NULL; } - if ((pRmhalspecowner = dynamicCast(pParent, RmHalspecOwner)) == NULL) - pRmhalspecowner = objFindAncestorOfType(RmHalspecOwner, pParent); - NV_ASSERT_OR_RETURN(pRmhalspecowner != NULL, NV_ERR_INVALID_ARGUMENT); - - __nvoc_init_SwIntr(pThis, pRmhalspecowner); - status = __nvoc_ctor_SwIntr(pThis, pRmhalspecowner); + __nvoc_init_SwIntr(pThis); + status = __nvoc_ctor_SwIntr(pThis); if (status != NV_OK) goto __nvoc_objCreate_SwIntr_cleanup; *ppThis = pThis; diff --git a/src/nvidia/generated/g_swintr_nvoc.h b/src/nvidia/generated/g_swintr_nvoc.h index f3b9129b4..4380dce53 100644 --- a/src/nvidia/generated/g_swintr_nvoc.h +++ b/src/nvidia/generated/g_swintr_nvoc.h @@ -43,7 +43,6 @@ extern "C" { #include "gpu/gpu.h" #include "gpu/eng_state.h" #include "kernel/gpu/intr/intr_service.h" -#include "kernel/gpu/intrable/intrable.h" #ifdef NVOC_SWINTR_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x @@ -53,41 +52,35 @@ extern "C" { struct SwIntr { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; - struct OBJINTRABLE __nvoc_base_OBJINTRABLE; struct IntrService __nvoc_base_IntrService; struct Object *__nvoc_pbase_Object; struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; - struct OBJINTRABLE *__nvoc_pbase_OBJINTRABLE; struct IntrService *__nvoc_pbase_IntrService; struct SwIntr *__nvoc_pbase_SwIntr; void (*__swintrRegisterIntrService__)(OBJGPU *, struct SwIntr *, IntrServiceRecord *); NvU32 (*__swintrServiceInterrupt__)(OBJGPU *, struct SwIntr *, IntrServiceServiceInterruptArguments *); - NV_STATUS (*__swintrGetKernelIntrVectors__)(OBJGPU *, struct SwIntr *, NvU32, NvU32 *, NvU32 *, NvU32 *); - void (*__swintrStateDestroy__)(POBJGPU, struct SwIntr *); - void (*__swintrFreeTunableState__)(POBJGPU, struct SwIntr *, void *); - NV_STATUS (*__swintrCompareTunableState__)(POBJGPU, struct SwIntr *, void *, void *); - NvBool (*__swintrClearInterrupt__)(OBJGPU *, struct SwIntr *, IntrServiceClearInterruptArguments *); - NV_STATUS (*__swintrGetNotificationIntrVector__)(OBJGPU *, struct SwIntr *, NvU32 *); - NvBool (*__swintrIsPresent__)(POBJGPU, struct SwIntr *); NV_STATUS (*__swintrReconcileTunableState__)(POBJGPU, struct SwIntr *, void *); NV_STATUS (*__swintrStateLoad__)(POBJGPU, struct SwIntr *, NvU32); - NV_STATUS (*__swintrGetPhysicalIntrVectors__)(OBJGPU *, struct SwIntr *, NvU32, NvU32 *, NvU32 *, NvU32 *); NV_STATUS (*__swintrStateUnload__)(POBJGPU, struct SwIntr *, NvU32); - NV_STATUS (*__swintrSetNotificationIntrVector__)(OBJGPU *, struct SwIntr *, NvU32); + NV_STATUS (*__swintrServiceNotificationInterrupt__)(OBJGPU *, struct SwIntr *, IntrServiceServiceNotificationInterruptArguments *); NV_STATUS (*__swintrStateInitLocked__)(POBJGPU, struct SwIntr *); NV_STATUS (*__swintrStatePreLoad__)(POBJGPU, struct SwIntr *, NvU32); NV_STATUS (*__swintrStatePostUnload__)(POBJGPU, struct SwIntr *, NvU32); + void (*__swintrStateDestroy__)(POBJGPU, struct SwIntr *); NV_STATUS (*__swintrStatePreUnload__)(POBJGPU, struct SwIntr *, NvU32); - NV_STATUS (*__swintrGetTunableState__)(POBJGPU, struct SwIntr *, void *); NV_STATUS (*__swintrStateInitUnlocked__)(POBJGPU, struct SwIntr *); void (*__swintrInitMissing__)(POBJGPU, struct SwIntr *); NV_STATUS (*__swintrStatePreInitLocked__)(POBJGPU, struct SwIntr *); NV_STATUS (*__swintrStatePreInitUnlocked__)(POBJGPU, struct SwIntr *); - NV_STATUS (*__swintrServiceNotificationInterrupt__)(OBJGPU *, struct SwIntr *, IntrServiceServiceNotificationInterruptArguments *); + NV_STATUS (*__swintrGetTunableState__)(POBJGPU, struct SwIntr *, void *); + NV_STATUS (*__swintrCompareTunableState__)(POBJGPU, struct SwIntr *, void *, void *); + void (*__swintrFreeTunableState__)(POBJGPU, struct SwIntr *, void *); + NvBool (*__swintrClearInterrupt__)(OBJGPU *, struct SwIntr *, IntrServiceClearInterruptArguments *); NV_STATUS (*__swintrStatePostLoad__)(POBJGPU, struct SwIntr *, NvU32); NV_STATUS (*__swintrAllocTunableState__)(POBJGPU, struct SwIntr *, void **); NV_STATUS (*__swintrSetTunableState__)(POBJGPU, struct SwIntr *, void *); NV_STATUS (*__swintrConstructEngine__)(POBJGPU, struct SwIntr *, ENGDESCRIPTOR); + NvBool (*__swintrIsPresent__)(POBJGPU, struct SwIntr *); }; #ifndef __NVOC_CLASS_SwIntr_TYPEDEF__ @@ -122,36 +115,31 @@ NV_STATUS __nvoc_objCreate_SwIntr(SwIntr**, Dynamic*, NvU32); #define swintrRegisterIntrService(pGpu, pSwIntr, pRecords) swintrRegisterIntrService_DISPATCH(pGpu, pSwIntr, pRecords) #define swintrServiceInterrupt(pGpu, pSwIntr, pParams) swintrServiceInterrupt_DISPATCH(pGpu, pSwIntr, pParams) -#define swintrGetKernelIntrVectors(pGpu, pSwIntr, maxIntrs, pIntrs, pMcEngineIdxs, pCount) swintrGetKernelIntrVectors_DISPATCH(pGpu, pSwIntr, maxIntrs, pIntrs, pMcEngineIdxs, pCount) -#define swintrGetKernelIntrVectors_HAL(pGpu, pSwIntr, maxIntrs, pIntrs, pMcEngineIdxs, pCount) swintrGetKernelIntrVectors_DISPATCH(pGpu, pSwIntr, maxIntrs, pIntrs, pMcEngineIdxs, pCount) -#define swintrStateDestroy(pGpu, pEngstate) swintrStateDestroy_DISPATCH(pGpu, pEngstate) -#define swintrFreeTunableState(pGpu, pEngstate, pTunableState) swintrFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define swintrCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) swintrCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) -#define swintrClearInterrupt(pGpu, pIntrService, pParams) swintrClearInterrupt_DISPATCH(pGpu, pIntrService, pParams) -#define swintrGetNotificationIntrVector(pGpu, pIntrable, pIntrVector) swintrGetNotificationIntrVector_DISPATCH(pGpu, pIntrable, pIntrVector) -#define swintrIsPresent(pGpu, pEngstate) swintrIsPresent_DISPATCH(pGpu, pEngstate) #define swintrReconcileTunableState(pGpu, pEngstate, pTunableState) swintrReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define swintrStateLoad(pGpu, pEngstate, arg0) swintrStateLoad_DISPATCH(pGpu, pEngstate, arg0) -#define swintrGetPhysicalIntrVectors(pGpu, pIntrable, maxIntrs, pIntrs, pMcEngineIdxs, pCount) swintrGetPhysicalIntrVectors_DISPATCH(pGpu, pIntrable, maxIntrs, pIntrs, pMcEngineIdxs, pCount) #define swintrStateUnload(pGpu, pEngstate, arg0) swintrStateUnload_DISPATCH(pGpu, pEngstate, arg0) -#define swintrSetNotificationIntrVector(pGpu, pIntrable, intrVector) swintrSetNotificationIntrVector_DISPATCH(pGpu, pIntrable, intrVector) +#define swintrServiceNotificationInterrupt(pGpu, pIntrService, pParams) swintrServiceNotificationInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define swintrStateInitLocked(pGpu, pEngstate) swintrStateInitLocked_DISPATCH(pGpu, pEngstate) #define swintrStatePreLoad(pGpu, pEngstate, arg0) swintrStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define swintrStatePostUnload(pGpu, pEngstate, arg0) swintrStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) +#define swintrStateDestroy(pGpu, pEngstate) swintrStateDestroy_DISPATCH(pGpu, pEngstate) #define swintrStatePreUnload(pGpu, pEngstate, arg0) swintrStatePreUnload_DISPATCH(pGpu, pEngstate, arg0) -#define swintrGetTunableState(pGpu, pEngstate, pTunableState) swintrGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define swintrStateInitUnlocked(pGpu, pEngstate) swintrStateInitUnlocked_DISPATCH(pGpu, pEngstate) #define swintrInitMissing(pGpu, pEngstate) swintrInitMissing_DISPATCH(pGpu, pEngstate) #define swintrStatePreInitLocked(pGpu, pEngstate) swintrStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define swintrStatePreInitUnlocked(pGpu, pEngstate) swintrStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define swintrServiceNotificationInterrupt(pGpu, pIntrService, pParams) swintrServiceNotificationInterrupt_DISPATCH(pGpu, pIntrService, pParams) +#define swintrGetTunableState(pGpu, pEngstate, pTunableState) swintrGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) +#define swintrCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) swintrCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) +#define swintrFreeTunableState(pGpu, pEngstate, pTunableState) swintrFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) +#define swintrClearInterrupt(pGpu, pIntrService, pParams) swintrClearInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define swintrStatePostLoad(pGpu, pEngstate, arg0) swintrStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) #define swintrAllocTunableState(pGpu, pEngstate, ppTunableState) swintrAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) #define swintrSetTunableState(pGpu, pEngstate, pTunableState) swintrSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define swintrConstructEngine(pGpu, pEngstate, arg0) swintrConstructEngine_DISPATCH(pGpu, pEngstate, arg0) -void swintrRegisterIntrService_IMPL(OBJGPU *pGpu, struct SwIntr *pSwIntr, IntrServiceRecord pRecords[155]); +#define swintrIsPresent(pGpu, pEngstate) swintrIsPresent_DISPATCH(pGpu, pEngstate) +void swintrRegisterIntrService_IMPL(OBJGPU *pGpu, struct SwIntr *pSwIntr, IntrServiceRecord pRecords[163]); -static inline void swintrRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct SwIntr *pSwIntr, IntrServiceRecord pRecords[155]) { +static inline void swintrRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct SwIntr *pSwIntr, IntrServiceRecord pRecords[163]) { pSwIntr->__swintrRegisterIntrService__(pGpu, pSwIntr, pRecords); } @@ -161,38 +149,6 @@ static inline NvU32 swintrServiceInterrupt_DISPATCH(OBJGPU *pGpu, struct SwIntr return pSwIntr->__swintrServiceInterrupt__(pGpu, pSwIntr, pParams); } -static inline NV_STATUS swintrGetKernelIntrVectors_46f6a7(OBJGPU *pGpu, struct SwIntr *pSwIntr, NvU32 maxIntrs, NvU32 *pIntrs, NvU32 *pMcEngineIdxs, NvU32 *pCount) { - return NV_ERR_NOT_SUPPORTED; -} - -static inline NV_STATUS swintrGetKernelIntrVectors_DISPATCH(OBJGPU *pGpu, struct SwIntr *pSwIntr, NvU32 maxIntrs, NvU32 *pIntrs, NvU32 *pMcEngineIdxs, NvU32 *pCount) { - return pSwIntr->__swintrGetKernelIntrVectors__(pGpu, pSwIntr, maxIntrs, pIntrs, pMcEngineIdxs, pCount); -} - -static inline void swintrStateDestroy_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngstate) { - pEngstate->__swintrStateDestroy__(pGpu, pEngstate); -} - -static inline void swintrFreeTunableState_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunableState) { - pEngstate->__swintrFreeTunableState__(pGpu, pEngstate, pTunableState); -} - -static inline NV_STATUS swintrCompareTunableState_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunables1, void *pTunables2) { - return pEngstate->__swintrCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); -} - -static inline NvBool swintrClearInterrupt_DISPATCH(OBJGPU *pGpu, struct SwIntr *pIntrService, IntrServiceClearInterruptArguments *pParams) { - return pIntrService->__swintrClearInterrupt__(pGpu, pIntrService, pParams); -} - -static inline NV_STATUS swintrGetNotificationIntrVector_DISPATCH(OBJGPU *pGpu, struct SwIntr *pIntrable, NvU32 *pIntrVector) { - return pIntrable->__swintrGetNotificationIntrVector__(pGpu, pIntrable, pIntrVector); -} - -static inline NvBool swintrIsPresent_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngstate) { - return pEngstate->__swintrIsPresent__(pGpu, pEngstate); -} - static inline NV_STATUS swintrReconcileTunableState_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunableState) { return pEngstate->__swintrReconcileTunableState__(pGpu, pEngstate, pTunableState); } @@ -201,16 +157,12 @@ static inline NV_STATUS swintrStateLoad_DISPATCH(POBJGPU pGpu, struct SwIntr *pE return pEngstate->__swintrStateLoad__(pGpu, pEngstate, arg0); } -static inline NV_STATUS swintrGetPhysicalIntrVectors_DISPATCH(OBJGPU *pGpu, struct SwIntr *pIntrable, NvU32 maxIntrs, NvU32 *pIntrs, NvU32 *pMcEngineIdxs, NvU32 *pCount) { - return pIntrable->__swintrGetPhysicalIntrVectors__(pGpu, pIntrable, maxIntrs, pIntrs, pMcEngineIdxs, pCount); -} - static inline NV_STATUS swintrStateUnload_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngstate, NvU32 arg0) { return pEngstate->__swintrStateUnload__(pGpu, pEngstate, arg0); } -static inline NV_STATUS swintrSetNotificationIntrVector_DISPATCH(OBJGPU *pGpu, struct SwIntr *pIntrable, NvU32 intrVector) { - return pIntrable->__swintrSetNotificationIntrVector__(pGpu, pIntrable, intrVector); +static inline NV_STATUS swintrServiceNotificationInterrupt_DISPATCH(OBJGPU *pGpu, struct SwIntr *pIntrService, IntrServiceServiceNotificationInterruptArguments *pParams) { + return pIntrService->__swintrServiceNotificationInterrupt__(pGpu, pIntrService, pParams); } static inline NV_STATUS swintrStateInitLocked_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngstate) { @@ -225,12 +177,12 @@ static inline NV_STATUS swintrStatePostUnload_DISPATCH(POBJGPU pGpu, struct SwIn return pEngstate->__swintrStatePostUnload__(pGpu, pEngstate, arg0); } -static inline NV_STATUS swintrStatePreUnload_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngstate, NvU32 arg0) { - return pEngstate->__swintrStatePreUnload__(pGpu, pEngstate, arg0); +static inline void swintrStateDestroy_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngstate) { + pEngstate->__swintrStateDestroy__(pGpu, pEngstate); } -static inline NV_STATUS swintrGetTunableState_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunableState) { - return pEngstate->__swintrGetTunableState__(pGpu, pEngstate, pTunableState); +static inline NV_STATUS swintrStatePreUnload_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngstate, NvU32 arg0) { + return pEngstate->__swintrStatePreUnload__(pGpu, pEngstate, arg0); } static inline NV_STATUS swintrStateInitUnlocked_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngstate) { @@ -249,8 +201,20 @@ static inline NV_STATUS swintrStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct return pEngstate->__swintrStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NV_STATUS swintrServiceNotificationInterrupt_DISPATCH(OBJGPU *pGpu, struct SwIntr *pIntrService, IntrServiceServiceNotificationInterruptArguments *pParams) { - return pIntrService->__swintrServiceNotificationInterrupt__(pGpu, pIntrService, pParams); +static inline NV_STATUS swintrGetTunableState_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunableState) { + return pEngstate->__swintrGetTunableState__(pGpu, pEngstate, pTunableState); +} + +static inline NV_STATUS swintrCompareTunableState_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunables1, void *pTunables2) { + return pEngstate->__swintrCompareTunableState__(pGpu, pEngstate, pTunables1, pTunables2); +} + +static inline void swintrFreeTunableState_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngstate, void *pTunableState) { + pEngstate->__swintrFreeTunableState__(pGpu, pEngstate, pTunableState); +} + +static inline NvBool swintrClearInterrupt_DISPATCH(OBJGPU *pGpu, struct SwIntr *pIntrService, IntrServiceClearInterruptArguments *pParams) { + return pIntrService->__swintrClearInterrupt__(pGpu, pIntrService, pParams); } static inline NV_STATUS swintrStatePostLoad_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngstate, NvU32 arg0) { @@ -269,6 +233,10 @@ static inline NV_STATUS swintrConstructEngine_DISPATCH(POBJGPU pGpu, struct SwIn return pEngstate->__swintrConstructEngine__(pGpu, pEngstate, arg0); } +static inline NvBool swintrIsPresent_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngstate) { + return pEngstate->__swintrIsPresent__(pGpu, pEngstate); +} + #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_syncgpuboost_nvoc.c b/src/nvidia/generated/g_syncgpuboost_nvoc.c index 1f30c80d7..d26a2f24f 100644 --- a/src/nvidia/generated/g_syncgpuboost_nvoc.c +++ b/src/nvidia/generated/g_syncgpuboost_nvoc.c @@ -140,6 +140,10 @@ static NV_STATUS __nvoc_thunk_RsResource_syncgpuboostUnmapFrom(struct SyncGpuBoo return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_syncgpuboostIsDuplicate(struct SyncGpuBoost *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_syncgpuboostControl_Epilogue(struct SyncGpuBoost *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RmResource.offset), pCallContext, pParams); } @@ -223,6 +227,8 @@ static void __nvoc_init_funcTable_SyncGpuBoost_1(SyncGpuBoost *pThis) { pThis->__syncgpuboostUnmapFrom__ = &__nvoc_thunk_RsResource_syncgpuboostUnmapFrom; + pThis->__syncgpuboostIsDuplicate__ = &__nvoc_thunk_RsResource_syncgpuboostIsDuplicate; + pThis->__syncgpuboostControl_Epilogue__ = &__nvoc_thunk_RmResource_syncgpuboostControl_Epilogue; pThis->__syncgpuboostControlLookup__ = &__nvoc_thunk_RsResource_syncgpuboostControlLookup; diff --git a/src/nvidia/generated/g_syncgpuboost_nvoc.h b/src/nvidia/generated/g_syncgpuboost_nvoc.h index 1fb151dbc..69e6cfe31 100644 --- a/src/nvidia/generated/g_syncgpuboost_nvoc.h +++ b/src/nvidia/generated/g_syncgpuboost_nvoc.h @@ -66,6 +66,7 @@ struct SyncGpuBoost { NV_STATUS (*__syncgpuboostMapTo__)(struct SyncGpuBoost *, RS_RES_MAP_TO_PARAMS *); void (*__syncgpuboostPreDestruct__)(struct SyncGpuBoost *); NV_STATUS (*__syncgpuboostUnmapFrom__)(struct SyncGpuBoost *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__syncgpuboostIsDuplicate__)(struct SyncGpuBoost *, NvHandle, NvBool *); void (*__syncgpuboostControl_Epilogue__)(struct SyncGpuBoost *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__syncgpuboostControlLookup__)(struct SyncGpuBoost *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__syncgpuboostMap__)(struct SyncGpuBoost *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -115,6 +116,7 @@ NV_STATUS __nvoc_objCreate_SyncGpuBoost(SyncGpuBoost**, Dynamic*, NvU32, struct #define syncgpuboostMapTo(pResource, pParams) syncgpuboostMapTo_DISPATCH(pResource, pParams) #define syncgpuboostPreDestruct(pResource) syncgpuboostPreDestruct_DISPATCH(pResource) #define syncgpuboostUnmapFrom(pResource, pParams) syncgpuboostUnmapFrom_DISPATCH(pResource, pParams) +#define syncgpuboostIsDuplicate(pResource, hMemory, pDuplicate) syncgpuboostIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define syncgpuboostControl_Epilogue(pResource, pCallContext, pParams) syncgpuboostControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define syncgpuboostControlLookup(pResource, pParams, ppEntry) syncgpuboostControlLookup_DISPATCH(pResource, pParams, ppEntry) #define syncgpuboostMap(pResource, pCallContext, pParams, pCpuMapping) syncgpuboostMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) @@ -175,6 +177,10 @@ static inline NV_STATUS syncgpuboostUnmapFrom_DISPATCH(struct SyncGpuBoost *pRes return pResource->__syncgpuboostUnmapFrom__(pResource, pParams); } +static inline NV_STATUS syncgpuboostIsDuplicate_DISPATCH(struct SyncGpuBoost *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__syncgpuboostIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void syncgpuboostControl_Epilogue_DISPATCH(struct SyncGpuBoost *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__syncgpuboostControl_Epilogue__(pResource, pCallContext, pParams); } @@ -192,8 +198,10 @@ static inline NvBool syncgpuboostAccessCallback_DISPATCH(struct SyncGpuBoost *pR } NV_STATUS syncgpuboostConstruct_IMPL(struct SyncGpuBoost *arg_pResource, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_syncgpuboostConstruct(arg_pResource, arg_pCallContext, arg_pParams) syncgpuboostConstruct_IMPL(arg_pResource, arg_pCallContext, arg_pParams) void syncgpuboostDestruct_IMPL(struct SyncGpuBoost *pResource); + #define __nvoc_syncgpuboostDestruct(pResource) syncgpuboostDestruct_IMPL(pResource) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_system_mem_nvoc.c b/src/nvidia/generated/g_system_mem_nvoc.c index ddfa4c0c4..1d30bc59d 100644 --- a/src/nvidia/generated/g_system_mem_nvoc.c +++ b/src/nvidia/generated/g_system_mem_nvoc.c @@ -146,16 +146,20 @@ static NV_STATUS __nvoc_thunk_RsResource_sysmemMapTo(struct SystemMemory *pResou return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RmResource_sysmemControl_Prologue(struct SystemMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RmResource.offset), pCallContext, pParams); -} - static NvBool __nvoc_thunk_StandardMemory_sysmemCanCopy(struct SystemMemory *pStandardMemory) { return stdmemCanCopy((struct StandardMemory *)(((unsigned char *)pStandardMemory) + __nvoc_rtti_SystemMemory_StandardMemory.offset)); } -static NV_STATUS __nvoc_thunk_Memory_sysmemIsReady(struct SystemMemory *pMemory) { - return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset)); +static NvBool __nvoc_thunk_Memory_sysmemIsGpuMapAllowed(struct SystemMemory *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), pGpu); +} + +static NV_STATUS __nvoc_thunk_RmResource_sysmemControl_Prologue(struct SystemMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_sysmemIsReady(struct SystemMemory *pMemory, NvBool bCopyConstructorContext) { + return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), bCopyConstructorContext); } static NV_STATUS __nvoc_thunk_Memory_sysmemCheckCopyPermissions(struct SystemMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { @@ -166,6 +170,10 @@ static void __nvoc_thunk_RsResource_sysmemPreDestruct(struct SystemMemory *pReso resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_Memory_sysmemIsDuplicate(struct SystemMemory *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), hMemory, pDuplicate); +} + static NV_STATUS __nvoc_thunk_RsResource_sysmemUnmapFrom(struct SystemMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RsResource.offset), pParams); } @@ -293,16 +301,20 @@ static void __nvoc_init_funcTable_SystemMemory_1(SystemMemory *pThis) { pThis->__sysmemMapTo__ = &__nvoc_thunk_RsResource_sysmemMapTo; - pThis->__sysmemControl_Prologue__ = &__nvoc_thunk_RmResource_sysmemControl_Prologue; - pThis->__sysmemCanCopy__ = &__nvoc_thunk_StandardMemory_sysmemCanCopy; + pThis->__sysmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_sysmemIsGpuMapAllowed; + + pThis->__sysmemControl_Prologue__ = &__nvoc_thunk_RmResource_sysmemControl_Prologue; + pThis->__sysmemIsReady__ = &__nvoc_thunk_Memory_sysmemIsReady; pThis->__sysmemCheckCopyPermissions__ = &__nvoc_thunk_Memory_sysmemCheckCopyPermissions; pThis->__sysmemPreDestruct__ = &__nvoc_thunk_RsResource_sysmemPreDestruct; + pThis->__sysmemIsDuplicate__ = &__nvoc_thunk_Memory_sysmemIsDuplicate; + pThis->__sysmemUnmapFrom__ = &__nvoc_thunk_RsResource_sysmemUnmapFrom; pThis->__sysmemControl_Epilogue__ = &__nvoc_thunk_RmResource_sysmemControl_Epilogue; diff --git a/src/nvidia/generated/g_system_mem_nvoc.h b/src/nvidia/generated/g_system_mem_nvoc.h index e099d44bb..1379cb0b9 100644 --- a/src/nvidia/generated/g_system_mem_nvoc.h +++ b/src/nvidia/generated/g_system_mem_nvoc.h @@ -65,11 +65,13 @@ struct SystemMemory { void (*__sysmemAddAdditionalDependants__)(struct RsClient *, struct SystemMemory *, RsResourceRef *); NvU32 (*__sysmemGetRefCount__)(struct SystemMemory *); NV_STATUS (*__sysmemMapTo__)(struct SystemMemory *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__sysmemControl_Prologue__)(struct SystemMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__sysmemCanCopy__)(struct SystemMemory *); - NV_STATUS (*__sysmemIsReady__)(struct SystemMemory *); + NvBool (*__sysmemIsGpuMapAllowed__)(struct SystemMemory *, struct OBJGPU *); + NV_STATUS (*__sysmemControl_Prologue__)(struct SystemMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__sysmemIsReady__)(struct SystemMemory *, NvBool); NV_STATUS (*__sysmemCheckCopyPermissions__)(struct SystemMemory *, struct OBJGPU *, NvHandle); void (*__sysmemPreDestruct__)(struct SystemMemory *); + NV_STATUS (*__sysmemIsDuplicate__)(struct SystemMemory *, NvHandle, NvBool *); NV_STATUS (*__sysmemUnmapFrom__)(struct SystemMemory *, RS_RES_UNMAP_FROM_PARAMS *); void (*__sysmemControl_Epilogue__)(struct SystemMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__sysmemControlLookup__)(struct SystemMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); @@ -118,11 +120,13 @@ NV_STATUS __nvoc_objCreate_SystemMemory(SystemMemory**, Dynamic*, NvU32, CALL_CO #define sysmemAddAdditionalDependants(pClient, pResource, pReference) sysmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define sysmemGetRefCount(pResource) sysmemGetRefCount_DISPATCH(pResource) #define sysmemMapTo(pResource, pParams) sysmemMapTo_DISPATCH(pResource, pParams) -#define sysmemControl_Prologue(pResource, pCallContext, pParams) sysmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define sysmemCanCopy(pStandardMemory) sysmemCanCopy_DISPATCH(pStandardMemory) -#define sysmemIsReady(pMemory) sysmemIsReady_DISPATCH(pMemory) +#define sysmemIsGpuMapAllowed(pMemory, pGpu) sysmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define sysmemControl_Prologue(pResource, pCallContext, pParams) sysmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define sysmemIsReady(pMemory, bCopyConstructorContext) sysmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define sysmemCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) sysmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) #define sysmemPreDestruct(pResource) sysmemPreDestruct_DISPATCH(pResource) +#define sysmemIsDuplicate(pMemory, hMemory, pDuplicate) sysmemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) #define sysmemUnmapFrom(pResource, pParams) sysmemUnmapFrom_DISPATCH(pResource, pParams) #define sysmemControl_Epilogue(pResource, pCallContext, pParams) sysmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define sysmemControlLookup(pResource, pParams, ppEntry) sysmemControlLookup_DISPATCH(pResource, pParams, ppEntry) @@ -130,6 +134,7 @@ NV_STATUS __nvoc_objCreate_SystemMemory(SystemMemory**, Dynamic*, NvU32, CALL_CO #define sysmemAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) sysmemAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS sysmemInitAllocRequest_HMM(struct OBJGPU *pGpu, struct SystemMemory *pSystemMemory, MEMORY_ALLOCATION_REQUEST *pAllocRequest); + #ifdef __nvoc_system_mem_h_disabled static inline NV_STATUS sysmemInitAllocRequest(struct OBJGPU *pGpu, struct SystemMemory *pSystemMemory, MEMORY_ALLOCATION_REQUEST *pAllocRequest) { NV_ASSERT_FAILED_PRECOMP("SystemMemory was disabled!"); @@ -197,16 +202,20 @@ static inline NV_STATUS sysmemMapTo_DISPATCH(struct SystemMemory *pResource, RS_ return pResource->__sysmemMapTo__(pResource, pParams); } -static inline NV_STATUS sysmemControl_Prologue_DISPATCH(struct SystemMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__sysmemControl_Prologue__(pResource, pCallContext, pParams); -} - static inline NvBool sysmemCanCopy_DISPATCH(struct SystemMemory *pStandardMemory) { return pStandardMemory->__sysmemCanCopy__(pStandardMemory); } -static inline NV_STATUS sysmemIsReady_DISPATCH(struct SystemMemory *pMemory) { - return pMemory->__sysmemIsReady__(pMemory); +static inline NvBool sysmemIsGpuMapAllowed_DISPATCH(struct SystemMemory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__sysmemIsGpuMapAllowed__(pMemory, pGpu); +} + +static inline NV_STATUS sysmemControl_Prologue_DISPATCH(struct SystemMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__sysmemControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS sysmemIsReady_DISPATCH(struct SystemMemory *pMemory, NvBool bCopyConstructorContext) { + return pMemory->__sysmemIsReady__(pMemory, bCopyConstructorContext); } static inline NV_STATUS sysmemCheckCopyPermissions_DISPATCH(struct SystemMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { @@ -217,6 +226,10 @@ static inline void sysmemPreDestruct_DISPATCH(struct SystemMemory *pResource) { pResource->__sysmemPreDestruct__(pResource); } +static inline NV_STATUS sysmemIsDuplicate_DISPATCH(struct SystemMemory *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return pMemory->__sysmemIsDuplicate__(pMemory, hMemory, pDuplicate); +} + static inline NV_STATUS sysmemUnmapFrom_DISPATCH(struct SystemMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return pResource->__sysmemUnmapFrom__(pResource, pParams); } @@ -238,6 +251,7 @@ static inline NvBool sysmemAccessCallback_DISPATCH(struct SystemMemory *pResourc } NV_STATUS sysmemConstruct_IMPL(struct SystemMemory *arg_pStandardMemory, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_sysmemConstruct(arg_pStandardMemory, arg_pCallContext, arg_pParams) sysmemConstruct_IMPL(arg_pStandardMemory, arg_pCallContext, arg_pParams) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_system_nvoc.c b/src/nvidia/generated/g_system_nvoc.c index 6b8117c52..d51cf00e6 100644 --- a/src/nvidia/generated/g_system_nvoc.c +++ b/src/nvidia/generated/g_system_nvoc.c @@ -83,13 +83,14 @@ void __nvoc_dtor_OBJSYS(OBJSYS *pThis) { void __nvoc_init_dataField_OBJSYS(OBJSYS *pThis) { PORT_UNREFERENCED_VARIABLE(pThis); - pThis->setProperty(pThis, PDB_PROP_SYS_VALIDATE_CLIENT_HANDLE, ((0) || (1))); + pThis->setProperty(pThis, PDB_PROP_SYS_VALIDATE_CLIENT_HANDLE, ((0) || (1) || (0))); pThis->setProperty(pThis, PDB_PROP_SYS_VALIDATE_CLIENT_HANDLE_STRICT, ((1) && !0)); pThis->setProperty(pThis, PDB_PROP_SYS_VALIDATE_KERNEL_BUFFERS, (0)); pThis->setProperty(pThis, PDB_PROP_SYS_INTERNAL_EVENT_BUFFER_ALLOC_ALLOWED, ((0) || (0))); pThis->setProperty(pThis, PDB_PROP_SYS_IS_AGGRESSIVE_GC6_ENABLED, (0)); pThis->setProperty(pThis, PDB_PROP_SYS_PRIORITY_BOOST, (0)); pThis->setProperty(pThis, PDB_PROP_SYS_PRIORITY_THROTTLE_DELAY_US, 16 * 1000); + pThis->setProperty(pThis, PDB_PROP_SYS_ROUTE_TO_PHYSICAL_LOCK_BYPASS, ((NvBool)(0 == 0))); } NV_STATUS __nvoc_ctor_Object(Object* ); diff --git a/src/nvidia/generated/g_system_nvoc.h b/src/nvidia/generated/g_system_nvoc.h index 1f9a36670..785e43981 100644 --- a/src/nvidia/generated/g_system_nvoc.h +++ b/src/nvidia/generated/g_system_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -57,7 +57,7 @@ extern "C" { #define SYS_GET_CL(p) ((p)->pCl) #define SYS_GET_SWINSTR(p) ((p)->pSwInstr) #define SYS_GET_GPUACCT(p) ((p)->pGpuAcct) -#define SYS_GET_GPS(p) ((p)->pGps) +#define SYS_GET_PFM_REQ_HNDLR(p) ((p)->pPlatformRequestHandler) #define SYS_GET_RCDB(p) ((p)->pRcDB) #define SYS_GET_VMM(p) (RMCFG_MODULE_VMM ? (p)->pVmm : NULL) #define SYS_GET_HYPERVISOR(p) ((p)->pHypervisor) @@ -68,7 +68,7 @@ extern "C" { #define SYS_GET_GPUDB(p) ((p)->pGpuDb) #define SYS_GET_HALMGR(p) ((p)->pHalMgr) -#define IsMobile(p) 0 +#define IsMobile(p) ((p)->getProperty((p), PDB_PROP_GPU_IS_MOBILE)) // // OS defines (Windows flavor can be added later on) @@ -140,16 +140,16 @@ typedef struct OBJDISPMGR OBJDISPMGR; #endif /* __nvoc_class_id_OBJDISPMGR */ -struct OBJGPS; +struct PlatformRequestHandler; -#ifndef __NVOC_CLASS_OBJGPS_TYPEDEF__ -#define __NVOC_CLASS_OBJGPS_TYPEDEF__ -typedef struct OBJGPS OBJGPS; -#endif /* __NVOC_CLASS_OBJGPS_TYPEDEF__ */ +#ifndef __NVOC_CLASS_PlatformRequestHandler_TYPEDEF__ +#define __NVOC_CLASS_PlatformRequestHandler_TYPEDEF__ +typedef struct PlatformRequestHandler PlatformRequestHandler; +#endif /* __NVOC_CLASS_PlatformRequestHandler_TYPEDEF__ */ -#ifndef __nvoc_class_id_OBJGPS -#define __nvoc_class_id_OBJGPS 0x7ee07d -#endif /* __nvoc_class_id_OBJGPS */ +#ifndef __nvoc_class_id_PlatformRequestHandler +#define __nvoc_class_id_PlatformRequestHandler 0x641a7f +#endif /* __nvoc_class_id_PlatformRequestHandler */ struct GpuAccounting; @@ -284,6 +284,18 @@ typedef struct OBJVGPUMGR OBJVGPUMGR; #endif /* __nvoc_class_id_OBJVGPUMGR */ +struct OBJOS; + +#ifndef __NVOC_CLASS_OBJOS_TYPEDEF__ +#define __NVOC_CLASS_OBJOS_TYPEDEF__ +typedef struct OBJOS OBJOS; +#endif /* __NVOC_CLASS_OBJOS_TYPEDEF__ */ + +#ifndef __nvoc_class_id_OBJOS +#define __nvoc_class_id_OBJOS 0xaa1d70 +#endif /* __nvoc_class_id_OBJOS */ + + typedef struct OBJRCDB Journal; @@ -386,7 +398,9 @@ struct OBJSYS { NvU32 apiLockMask; NvU32 apiLockModuleMask; NvU32 gpuLockModuleMask; + NvBool PDB_PROP_SYS_ROUTE_TO_PHYSICAL_LOCK_BYPASS; NvU32 pwrTransitionTimeoutOverride; + NvBool bMulticastFlaEnabled; SYS_STATIC_CONFIG staticConfig; NvU32 debugFlags; NvU32 backtraceStackDepth; @@ -397,6 +411,7 @@ struct OBJSYS { void *pSema; NvU32 binMask; PNODE pMemFilterList; + NvBool PDB_PROP_SYS_IS_QSYNC_FW_REVISION_CHECK_DISABLED; NvU64 rmInstanceId; NvU32 currentCid; OS_RM_CAPS *pOsRmCaps; @@ -404,12 +419,12 @@ struct OBJSYS { struct OBJGSYNCMGR *pGsyncMgr; struct OBJVGPUMGR *pVgpuMgr; struct KernelVgpuMgr *pKernelVgpuMgr; - OBJOS *pOS; + struct OBJOS *pOS; struct OBJCL *pCl; struct OBJPFM *pPfm; struct OBJSWINSTR *pSwInstr; struct GpuAccounting *pGpuAcct; - struct OBJGPS *pGps; + struct PlatformRequestHandler *pPlatformRequestHandler; Journal *pRcDB; struct OBJVMM *pVmm; struct OBJHYPERVISOR *pHypervisor; @@ -450,6 +465,10 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJSYS; #define PDB_PROP_SYS_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS_BASE_NAME PDB_PROP_SYS_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS #define PDB_PROP_SYS_POWER_BATTERY_BASE_CAST #define PDB_PROP_SYS_POWER_BATTERY_BASE_NAME PDB_PROP_SYS_POWER_BATTERY +#define PDB_PROP_SYS_IS_QSYNC_FW_REVISION_CHECK_DISABLED_BASE_CAST +#define PDB_PROP_SYS_IS_QSYNC_FW_REVISION_CHECK_DISABLED_BASE_NAME PDB_PROP_SYS_IS_QSYNC_FW_REVISION_CHECK_DISABLED +#define PDB_PROP_SYS_ROUTE_TO_PHYSICAL_LOCK_BYPASS_BASE_CAST +#define PDB_PROP_SYS_ROUTE_TO_PHYSICAL_LOCK_BYPASS_BASE_NAME PDB_PROP_SYS_ROUTE_TO_PHYSICAL_LOCK_BYPASS #define PDB_PROP_SYS_NVIF_INIT_DONE_BASE_CAST #define PDB_PROP_SYS_NVIF_INIT_DONE_BASE_NAME PDB_PROP_SYS_NVIF_INIT_DONE #define PDB_PROP_SYS_VALIDATE_CLIENT_HANDLE_STRICT_BASE_CAST @@ -519,10 +538,13 @@ static inline const SYS_STATIC_CONFIG *sysGetStaticConfig(struct OBJSYS *pSys) { } NV_STATUS sysConstruct_IMPL(struct OBJSYS *arg_); + #define __nvoc_sysConstruct(arg_) sysConstruct_IMPL(arg_) void sysDestruct_IMPL(struct OBJSYS *arg0); + #define __nvoc_sysDestruct(arg0) sysDestruct_IMPL(arg0) void sysInitRegistryOverrides_IMPL(struct OBJSYS *arg0); + #ifdef __nvoc_system_h_disabled static inline void sysInitRegistryOverrides(struct OBJSYS *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJSYS was disabled!"); @@ -532,6 +554,7 @@ static inline void sysInitRegistryOverrides(struct OBJSYS *arg0) { #endif //__nvoc_system_h_disabled void sysApplyLockingPolicy_IMPL(struct OBJSYS *arg0); + #ifdef __nvoc_system_h_disabled static inline void sysApplyLockingPolicy(struct OBJSYS *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJSYS was disabled!"); @@ -540,9 +563,10 @@ static inline void sysApplyLockingPolicy(struct OBJSYS *arg0) { #define sysApplyLockingPolicy(arg0) sysApplyLockingPolicy_IMPL(arg0) #endif //__nvoc_system_h_disabled -OBJOS *sysGetOs_IMPL(struct OBJSYS *arg0); +struct OBJOS *sysGetOs_IMPL(struct OBJSYS *arg0); + #ifdef __nvoc_system_h_disabled -static inline OBJOS *sysGetOs(struct OBJSYS *arg0) { +static inline struct OBJOS *sysGetOs(struct OBJSYS *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJSYS was disabled!"); return NULL; } @@ -551,6 +575,7 @@ static inline OBJOS *sysGetOs(struct OBJSYS *arg0) { #endif //__nvoc_system_h_disabled void sysEnableExternalFabricMgmt_IMPL(struct OBJSYS *arg0); + #ifdef __nvoc_system_h_disabled static inline void sysEnableExternalFabricMgmt(struct OBJSYS *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJSYS was disabled!"); @@ -560,6 +585,7 @@ static inline void sysEnableExternalFabricMgmt(struct OBJSYS *arg0) { #endif //__nvoc_system_h_disabled void sysForceInitFabricManagerState_IMPL(struct OBJSYS *arg0); + #ifdef __nvoc_system_h_disabled static inline void sysForceInitFabricManagerState(struct OBJSYS *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJSYS was disabled!"); @@ -569,6 +595,7 @@ static inline void sysForceInitFabricManagerState(struct OBJSYS *arg0) { #endif //__nvoc_system_h_disabled NV_STATUS sysSyncExternalFabricMgmtWAR_IMPL(struct OBJSYS *arg0, OBJGPU *arg1); + #ifdef __nvoc_system_h_disabled static inline NV_STATUS sysSyncExternalFabricMgmtWAR(struct OBJSYS *arg0, OBJGPU *arg1) { NV_ASSERT_FAILED_PRECOMP("OBJSYS was disabled!"); diff --git a/src/nvidia/generated/g_third_party_p2p_nvoc.c b/src/nvidia/generated/g_third_party_p2p_nvoc.c index 054b65889..3492093ec 100644 --- a/src/nvidia/generated/g_third_party_p2p_nvoc.c +++ b/src/nvidia/generated/g_third_party_p2p_nvoc.c @@ -165,6 +165,10 @@ static NV_STATUS __nvoc_thunk_RsResource_thirdpartyp2pUnmapFrom(struct ThirdPart return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_thirdpartyp2pIsDuplicate(struct ThirdPartyP2P *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_thirdpartyp2pControl_Epilogue(struct ThirdPartyP2P *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RmResource.offset), pCallContext, pParams); } @@ -360,6 +364,8 @@ static void __nvoc_init_funcTable_ThirdPartyP2P_1(ThirdPartyP2P *pThis) { pThis->__thirdpartyp2pUnmapFrom__ = &__nvoc_thunk_RsResource_thirdpartyp2pUnmapFrom; + pThis->__thirdpartyp2pIsDuplicate__ = &__nvoc_thunk_RsResource_thirdpartyp2pIsDuplicate; + pThis->__thirdpartyp2pControl_Epilogue__ = &__nvoc_thunk_RmResource_thirdpartyp2pControl_Epilogue; pThis->__thirdpartyp2pControlLookup__ = &__nvoc_thunk_RsResource_thirdpartyp2pControlLookup; diff --git a/src/nvidia/generated/g_third_party_p2p_nvoc.h b/src/nvidia/generated/g_third_party_p2p_nvoc.h index 1d958f21e..20197c866 100644 --- a/src/nvidia/generated/g_third_party_p2p_nvoc.h +++ b/src/nvidia/generated/g_third_party_p2p_nvoc.h @@ -217,6 +217,7 @@ struct ThirdPartyP2P { NV_STATUS (*__thirdpartyp2pInternalControlForward__)(struct ThirdPartyP2P *, NvU32, void *, NvU32); void (*__thirdpartyp2pPreDestruct__)(struct ThirdPartyP2P *); NV_STATUS (*__thirdpartyp2pUnmapFrom__)(struct ThirdPartyP2P *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__thirdpartyp2pIsDuplicate__)(struct ThirdPartyP2P *, NvHandle, NvBool *); void (*__thirdpartyp2pControl_Epilogue__)(struct ThirdPartyP2P *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__thirdpartyp2pControlLookup__)(struct ThirdPartyP2P *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__thirdpartyp2pMap__)(struct ThirdPartyP2P *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -288,6 +289,7 @@ NV_STATUS __nvoc_objCreate_ThirdPartyP2P(ThirdPartyP2P**, Dynamic*, NvU32, struc #define thirdpartyp2pInternalControlForward(pGpuResource, command, pParams, size) thirdpartyp2pInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define thirdpartyp2pPreDestruct(pResource) thirdpartyp2pPreDestruct_DISPATCH(pResource) #define thirdpartyp2pUnmapFrom(pResource, pParams) thirdpartyp2pUnmapFrom_DISPATCH(pResource, pParams) +#define thirdpartyp2pIsDuplicate(pResource, hMemory, pDuplicate) thirdpartyp2pIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define thirdpartyp2pControl_Epilogue(pResource, pCallContext, pParams) thirdpartyp2pControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define thirdpartyp2pControlLookup(pResource, pParams, ppEntry) thirdpartyp2pControlLookup_DISPATCH(pResource, pParams, ppEntry) #define thirdpartyp2pMap(pGpuResource, pCallContext, pParams, pCpuMapping) thirdpartyp2pMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -394,6 +396,10 @@ static inline NV_STATUS thirdpartyp2pUnmapFrom_DISPATCH(struct ThirdPartyP2P *pR return pResource->__thirdpartyp2pUnmapFrom__(pResource, pParams); } +static inline NV_STATUS thirdpartyp2pIsDuplicate_DISPATCH(struct ThirdPartyP2P *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__thirdpartyp2pIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void thirdpartyp2pControl_Epilogue_DISPATCH(struct ThirdPartyP2P *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__thirdpartyp2pControl_Epilogue__(pResource, pCallContext, pParams); } @@ -411,10 +417,13 @@ static inline NvBool thirdpartyp2pAccessCallback_DISPATCH(struct ThirdPartyP2P * } NV_STATUS thirdpartyp2pConstruct_IMPL(struct ThirdPartyP2P *arg_pResource, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_thirdpartyp2pConstruct(arg_pResource, arg_pCallContext, arg_pParams) thirdpartyp2pConstruct_IMPL(arg_pResource, arg_pCallContext, arg_pParams) void thirdpartyp2pDestruct_IMPL(struct ThirdPartyP2P *pResource); + #define __nvoc_thirdpartyp2pDestruct(pResource) thirdpartyp2pDestruct_IMPL(pResource) NvBool thirdpartyp2pIsValidClientPid_IMPL(struct ThirdPartyP2P *pThirdPartyP2P, NvU32 pid, NvHandle hClient); + #ifdef __nvoc_third_party_p2p_h_disabled static inline NvBool thirdpartyp2pIsValidClientPid(struct ThirdPartyP2P *pThirdPartyP2P, NvU32 pid, NvHandle hClient) { NV_ASSERT_FAILED_PRECOMP("ThirdPartyP2P was disabled!"); @@ -425,6 +434,7 @@ static inline NvBool thirdpartyp2pIsValidClientPid(struct ThirdPartyP2P *pThirdP #endif //__nvoc_third_party_p2p_h_disabled NV_STATUS thirdpartyp2pDelMappingInfoByKey_IMPL(struct ThirdPartyP2P *pThirdPartyP2P, void *pKey, NvBool bIsRsyncNeeded); + #ifdef __nvoc_third_party_p2p_h_disabled static inline NV_STATUS thirdpartyp2pDelMappingInfoByKey(struct ThirdPartyP2P *pThirdPartyP2P, void *pKey, NvBool bIsRsyncNeeded) { NV_ASSERT_FAILED_PRECOMP("ThirdPartyP2P was disabled!"); @@ -435,6 +445,7 @@ static inline NV_STATUS thirdpartyp2pDelMappingInfoByKey(struct ThirdPartyP2P *p #endif //__nvoc_third_party_p2p_h_disabled NV_STATUS thirdpartyp2pDelPersistentMappingInfoByKey_IMPL(struct ThirdPartyP2P *pThirdPartyP2P, void *pKey, NvBool bIsRsyncNeeded); + #ifdef __nvoc_third_party_p2p_h_disabled static inline NV_STATUS thirdpartyp2pDelPersistentMappingInfoByKey(struct ThirdPartyP2P *pThirdPartyP2P, void *pKey, NvBool bIsRsyncNeeded) { NV_ASSERT_FAILED_PRECOMP("ThirdPartyP2P was disabled!"); @@ -445,6 +456,7 @@ static inline NV_STATUS thirdpartyp2pDelPersistentMappingInfoByKey(struct ThirdP #endif //__nvoc_third_party_p2p_h_disabled NV_STATUS thirdpartyp2pGetVASpaceInfoFromToken_IMPL(struct ThirdPartyP2P *pThirdPartyP2P, NvU32 vaSpaceToken, PCLI_THIRD_PARTY_P2P_VASPACE_INFO *ppVASpaceInfo); + #ifdef __nvoc_third_party_p2p_h_disabled static inline NV_STATUS thirdpartyp2pGetVASpaceInfoFromToken(struct ThirdPartyP2P *pThirdPartyP2P, NvU32 vaSpaceToken, PCLI_THIRD_PARTY_P2P_VASPACE_INFO *ppVASpaceInfo) { NV_ASSERT_FAILED_PRECOMP("ThirdPartyP2P was disabled!"); @@ -455,6 +467,7 @@ static inline NV_STATUS thirdpartyp2pGetVASpaceInfoFromToken(struct ThirdPartyP2 #endif //__nvoc_third_party_p2p_h_disabled NV_STATUS thirdpartyp2pGetNextVASpaceInfo_IMPL(struct ThirdPartyP2P *pThirdPartyP2P, PCLI_THIRD_PARTY_P2P_VASPACE_INFO *arg0); + #ifdef __nvoc_third_party_p2p_h_disabled static inline NV_STATUS thirdpartyp2pGetNextVASpaceInfo(struct ThirdPartyP2P *pThirdPartyP2P, PCLI_THIRD_PARTY_P2P_VASPACE_INFO *arg0) { NV_ASSERT_FAILED_PRECOMP("ThirdPartyP2P was disabled!"); diff --git a/src/nvidia/generated/g_timed_sema_nvoc.c b/src/nvidia/generated/g_timed_sema_nvoc.c index c88fed3bd..83e44aae0 100644 --- a/src/nvidia/generated/g_timed_sema_nvoc.c +++ b/src/nvidia/generated/g_timed_sema_nvoc.c @@ -220,6 +220,10 @@ static void __nvoc_thunk_RsResource_tsemaPreDestruct(struct TimedSemaSwObject *p resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimedSemaSwObject_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_RsResource_tsemaIsDuplicate(struct TimedSemaSwObject *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimedSemaSwObject_RsResource.offset), hMemory, pDuplicate); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_tsemaGetNotificationListPtr(struct TimedSemaSwObject *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_TimedSemaSwObject_Notifier.offset)); } @@ -393,6 +397,8 @@ static void __nvoc_init_funcTable_TimedSemaSwObject_1(TimedSemaSwObject *pThis) pThis->__tsemaPreDestruct__ = &__nvoc_thunk_RsResource_tsemaPreDestruct; + pThis->__tsemaIsDuplicate__ = &__nvoc_thunk_RsResource_tsemaIsDuplicate; + pThis->__tsemaGetNotificationListPtr__ = &__nvoc_thunk_Notifier_tsemaGetNotificationListPtr; pThis->__tsemaGetNotificationShare__ = &__nvoc_thunk_Notifier_tsemaGetNotificationShare; diff --git a/src/nvidia/generated/g_timed_sema_nvoc.h b/src/nvidia/generated/g_timed_sema_nvoc.h index 61361c2dc..21eef5ffd 100644 --- a/src/nvidia/generated/g_timed_sema_nvoc.h +++ b/src/nvidia/generated/g_timed_sema_nvoc.h @@ -97,6 +97,7 @@ struct TimedSemaSwObject { NV_STATUS (*__tsemaUnregisterEvent__)(struct TimedSemaSwObject *, NvHandle, NvHandle, NvHandle, NvHandle); NvBool (*__tsemaCanCopy__)(struct TimedSemaSwObject *); void (*__tsemaPreDestruct__)(struct TimedSemaSwObject *); + NV_STATUS (*__tsemaIsDuplicate__)(struct TimedSemaSwObject *, NvHandle, NvBool *); PEVENTNOTIFICATION *(*__tsemaGetNotificationListPtr__)(struct TimedSemaSwObject *); struct NotifShare *(*__tsemaGetNotificationShare__)(struct TimedSemaSwObject *); NV_STATUS (*__tsemaMap__)(struct TimedSemaSwObject *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -172,10 +173,17 @@ NV_STATUS __nvoc_objCreate_TimedSemaSwObject(TimedSemaSwObject**, Dynamic*, NvU3 #define tsemaUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) tsemaUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define tsemaCanCopy(pResource) tsemaCanCopy_DISPATCH(pResource) #define tsemaPreDestruct(pResource) tsemaPreDestruct_DISPATCH(pResource) +#define tsemaIsDuplicate(pResource, hMemory, pDuplicate) tsemaIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define tsemaGetNotificationListPtr(pNotifier) tsemaGetNotificationListPtr_DISPATCH(pNotifier) #define tsemaGetNotificationShare(pNotifier) tsemaGetNotificationShare_DISPATCH(pNotifier) #define tsemaMap(pGpuResource, pCallContext, pParams, pCpuMapping) tsemaMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define tsemaGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) tsemaGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +NV_STATUS tsemaRelease_KERNEL(struct OBJGPU *pGpu, NvU64 semaphoreVA, NvU64 notifierVA, NvU32 hVASpace, NvU32 releasevalue, NvU32 completionStatus, NvHandle hClient); + + +#define tsemaRelease(pGpu, semaphoreVA, notifierVA, hVASpace, releasevalue, completionStatus, hClient) tsemaRelease_KERNEL(pGpu, semaphoreVA, notifierVA, hVASpace, releasevalue, completionStatus, hClient) +#define tsemaRelease_HAL(pGpu, semaphoreVA, notifierVA, hVASpace, releasevalue, completionStatus, hClient) tsemaRelease(pGpu, semaphoreVA, notifierVA, hVASpace, releasevalue, completionStatus, hClient) + NV_STATUS tsemaGetSwMethods_IMPL(struct TimedSemaSwObject *pTimedSemSw, METHOD **ppMethods, NvU32 *pNumMethods); static inline NV_STATUS tsemaGetSwMethods_DISPATCH(struct TimedSemaSwObject *pTimedSemSw, METHOD **ppMethods, NvU32 *pNumMethods) { @@ -296,6 +304,10 @@ static inline void tsemaPreDestruct_DISPATCH(struct TimedSemaSwObject *pResource pResource->__tsemaPreDestruct__(pResource); } +static inline NV_STATUS tsemaIsDuplicate_DISPATCH(struct TimedSemaSwObject *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__tsemaIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline PEVENTNOTIFICATION *tsemaGetNotificationListPtr_DISPATCH(struct TimedSemaSwObject *pNotifier) { return pNotifier->__tsemaGetNotificationListPtr__(pNotifier); } @@ -313,8 +325,10 @@ static inline NV_STATUS tsemaGetOrAllocNotifShare_DISPATCH(struct TimedSemaSwObj } NV_STATUS tsemaConstruct_IMPL(struct TimedSemaSwObject *arg_pTimedSemSw, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_tsemaConstruct(arg_pTimedSemSw, arg_pCallContext, arg_pParams) tsemaConstruct_IMPL(arg_pTimedSemSw, arg_pCallContext, arg_pParams) void tsemaDestruct_IMPL(struct TimedSemaSwObject *pTimedSemSw); + #define __nvoc_tsemaDestruct(pTimedSemSw) tsemaDestruct_IMPL(pTimedSemSw) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_tmr_nvoc.c b/src/nvidia/generated/g_tmr_nvoc.c index e6f048f2f..e9cd7ba6f 100644 --- a/src/nvidia/generated/g_tmr_nvoc.c +++ b/src/nvidia/generated/g_tmr_nvoc.c @@ -203,6 +203,10 @@ static void __nvoc_thunk_RsResource_tmrapiPreDestruct(struct TimerApi *pResource resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimerApi_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_RsResource_tmrapiIsDuplicate(struct TimerApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimerApi_RsResource.offset), hMemory, pDuplicate); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_tmrapiGetNotificationListPtr(struct TimerApi *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_TimerApi_Notifier.offset)); } @@ -341,6 +345,8 @@ static void __nvoc_init_funcTable_TimerApi_1(TimerApi *pThis) { pThis->__tmrapiPreDestruct__ = &__nvoc_thunk_RsResource_tmrapiPreDestruct; + pThis->__tmrapiIsDuplicate__ = &__nvoc_thunk_RsResource_tmrapiIsDuplicate; + pThis->__tmrapiGetNotificationListPtr__ = &__nvoc_thunk_Notifier_tmrapiGetNotificationListPtr; pThis->__tmrapiGetNotificationShare__ = &__nvoc_thunk_Notifier_tmrapiGetNotificationShare; diff --git a/src/nvidia/generated/g_tmr_nvoc.h b/src/nvidia/generated/g_tmr_nvoc.h index 21be57f28..ac9e24803 100644 --- a/src/nvidia/generated/g_tmr_nvoc.h +++ b/src/nvidia/generated/g_tmr_nvoc.h @@ -121,6 +121,7 @@ struct TimerApi { NV_STATUS (*__tmrapiUnregisterEvent__)(struct TimerApi *, NvHandle, NvHandle, NvHandle, NvHandle); NvBool (*__tmrapiCanCopy__)(struct TimerApi *); void (*__tmrapiPreDestruct__)(struct TimerApi *); + NV_STATUS (*__tmrapiIsDuplicate__)(struct TimerApi *, NvHandle, NvBool *); PEVENTNOTIFICATION *(*__tmrapiGetNotificationListPtr__)(struct TimerApi *); struct NotifShare *(*__tmrapiGetNotificationShare__)(struct TimerApi *); NV_STATUS (*__tmrapiMap__)(struct TimerApi *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -179,6 +180,7 @@ NV_STATUS __nvoc_objCreate_TimerApi(TimerApi**, Dynamic*, NvU32, struct CALL_CON #define tmrapiUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) tmrapiUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define tmrapiCanCopy(pResource) tmrapiCanCopy_DISPATCH(pResource) #define tmrapiPreDestruct(pResource) tmrapiPreDestruct_DISPATCH(pResource) +#define tmrapiIsDuplicate(pResource, hMemory, pDuplicate) tmrapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define tmrapiGetNotificationListPtr(pNotifier) tmrapiGetNotificationListPtr_DISPATCH(pNotifier) #define tmrapiGetNotificationShare(pNotifier) tmrapiGetNotificationShare_DISPATCH(pNotifier) #define tmrapiMap(pGpuResource, pCallContext, pParams, pCpuMapping) tmrapiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -283,6 +285,10 @@ static inline void tmrapiPreDestruct_DISPATCH(struct TimerApi *pResource) { pResource->__tmrapiPreDestruct__(pResource); } +static inline NV_STATUS tmrapiIsDuplicate_DISPATCH(struct TimerApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__tmrapiIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline PEVENTNOTIFICATION *tmrapiGetNotificationListPtr_DISPATCH(struct TimerApi *pNotifier) { return pNotifier->__tmrapiGetNotificationListPtr__(pNotifier); } @@ -300,10 +306,13 @@ static inline NvBool tmrapiAccessCallback_DISPATCH(struct TimerApi *pResource, s } NV_STATUS tmrapiConstruct_IMPL(struct TimerApi *arg_pTimerApi, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_tmrapiConstruct(arg_pTimerApi, arg_pCallContext, arg_pParams) tmrapiConstruct_IMPL(arg_pTimerApi, arg_pCallContext, arg_pParams) void tmrapiDestruct_IMPL(struct TimerApi *pTimerApi); + #define __nvoc_tmrapiDestruct(pTimerApi) tmrapiDestruct_IMPL(pTimerApi) void tmrapiDeregisterEvents_IMPL(struct TimerApi *pTimerApi); + #ifdef __nvoc_tmr_h_disabled static inline void tmrapiDeregisterEvents(struct TimerApi *pTimerApi) { NV_ASSERT_FAILED_PRECOMP("TimerApi was disabled!"); diff --git a/src/nvidia/generated/g_usermode_api_nvoc.c b/src/nvidia/generated/g_usermode_api_nvoc.c index c97a6d4c9..766b49bee 100644 --- a/src/nvidia/generated/g_usermode_api_nvoc.c +++ b/src/nvidia/generated/g_usermode_api_nvoc.c @@ -145,8 +145,12 @@ static NV_STATUS __nvoc_thunk_RmResource_usrmodeControl_Prologue(struct UserMode return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_Memory_usrmodeIsReady(struct UserModeApi *pMemory) { - return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset)); +static NvBool __nvoc_thunk_Memory_usrmodeIsGpuMapAllowed(struct UserModeApi *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), pGpu); +} + +static NV_STATUS __nvoc_thunk_Memory_usrmodeIsReady(struct UserModeApi *pMemory, NvBool bCopyConstructorContext) { + return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), bCopyConstructorContext); } static NV_STATUS __nvoc_thunk_Memory_usrmodeCheckCopyPermissions(struct UserModeApi *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { @@ -157,6 +161,10 @@ static void __nvoc_thunk_RsResource_usrmodePreDestruct(struct UserModeApi *pReso resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_Memory_usrmodeIsDuplicate(struct UserModeApi *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), hMemory, pDuplicate); +} + static NV_STATUS __nvoc_thunk_RsResource_usrmodeUnmapFrom(struct UserModeApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RsResource.offset), pParams); } @@ -226,14 +234,11 @@ static void __nvoc_init_funcTable_UserModeApi_1(UserModeApi *pThis, RmHalspecOwn PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); // Hal function -- usrmodeConstructHal - if (0) - { - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0070ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->__usrmodeConstructHal__ = &usrmodeConstructHal_GV100; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__usrmodeConstructHal__ = &usrmodeConstructHal_GH100; } @@ -266,12 +271,16 @@ static void __nvoc_init_funcTable_UserModeApi_1(UserModeApi *pThis, RmHalspecOwn pThis->__usrmodeControl_Prologue__ = &__nvoc_thunk_RmResource_usrmodeControl_Prologue; + pThis->__usrmodeIsGpuMapAllowed__ = &__nvoc_thunk_Memory_usrmodeIsGpuMapAllowed; + pThis->__usrmodeIsReady__ = &__nvoc_thunk_Memory_usrmodeIsReady; pThis->__usrmodeCheckCopyPermissions__ = &__nvoc_thunk_Memory_usrmodeCheckCopyPermissions; pThis->__usrmodePreDestruct__ = &__nvoc_thunk_RsResource_usrmodePreDestruct; + pThis->__usrmodeIsDuplicate__ = &__nvoc_thunk_Memory_usrmodeIsDuplicate; + pThis->__usrmodeUnmapFrom__ = &__nvoc_thunk_RsResource_usrmodeUnmapFrom; pThis->__usrmodeControl_Epilogue__ = &__nvoc_thunk_RmResource_usrmodeControl_Epilogue; diff --git a/src/nvidia/generated/g_usermode_api_nvoc.h b/src/nvidia/generated/g_usermode_api_nvoc.h index c63b107ba..86ca62e17 100644 --- a/src/nvidia/generated/g_usermode_api_nvoc.h +++ b/src/nvidia/generated/g_usermode_api_nvoc.h @@ -72,9 +72,11 @@ struct UserModeApi { NvU32 (*__usrmodeGetRefCount__)(struct UserModeApi *); NV_STATUS (*__usrmodeMapTo__)(struct UserModeApi *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__usrmodeControl_Prologue__)(struct UserModeApi *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__usrmodeIsReady__)(struct UserModeApi *); + NvBool (*__usrmodeIsGpuMapAllowed__)(struct UserModeApi *, struct OBJGPU *); + NV_STATUS (*__usrmodeIsReady__)(struct UserModeApi *, NvBool); NV_STATUS (*__usrmodeCheckCopyPermissions__)(struct UserModeApi *, struct OBJGPU *, NvHandle); void (*__usrmodePreDestruct__)(struct UserModeApi *); + NV_STATUS (*__usrmodeIsDuplicate__)(struct UserModeApi *, NvHandle, NvBool *); NV_STATUS (*__usrmodeUnmapFrom__)(struct UserModeApi *, RS_RES_UNMAP_FROM_PARAMS *); void (*__usrmodeControl_Epilogue__)(struct UserModeApi *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__usrmodeControlLookup__)(struct UserModeApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); @@ -125,18 +127,16 @@ NV_STATUS __nvoc_objCreate_UserModeApi(UserModeApi**, Dynamic*, NvU32, CALL_CONT #define usrmodeGetRefCount(pResource) usrmodeGetRefCount_DISPATCH(pResource) #define usrmodeMapTo(pResource, pParams) usrmodeMapTo_DISPATCH(pResource, pParams) #define usrmodeControl_Prologue(pResource, pCallContext, pParams) usrmodeControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define usrmodeIsReady(pMemory) usrmodeIsReady_DISPATCH(pMemory) +#define usrmodeIsGpuMapAllowed(pMemory, pGpu) usrmodeIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define usrmodeIsReady(pMemory, bCopyConstructorContext) usrmodeIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define usrmodeCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) usrmodeCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) #define usrmodePreDestruct(pResource) usrmodePreDestruct_DISPATCH(pResource) +#define usrmodeIsDuplicate(pMemory, hMemory, pDuplicate) usrmodeIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) #define usrmodeUnmapFrom(pResource, pParams) usrmodeUnmapFrom_DISPATCH(pResource, pParams) #define usrmodeControl_Epilogue(pResource, pCallContext, pParams) usrmodeControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define usrmodeControlLookup(pResource, pParams, ppEntry) usrmodeControlLookup_DISPATCH(pResource, pParams, ppEntry) #define usrmodeMap(pMemory, pCallContext, pParams, pCpuMapping) usrmodeMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) #define usrmodeAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) usrmodeAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) -static inline NV_STATUS usrmodeConstructHal_46f6a7(struct UserModeApi *pUserModeApi, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { - return NV_ERR_NOT_SUPPORTED; -} - NV_STATUS usrmodeConstructHal_GV100(struct UserModeApi *pUserModeApi, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); NV_STATUS usrmodeConstructHal_GH100(struct UserModeApi *pUserModeApi, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); @@ -199,8 +199,12 @@ static inline NV_STATUS usrmodeControl_Prologue_DISPATCH(struct UserModeApi *pRe return pResource->__usrmodeControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS usrmodeIsReady_DISPATCH(struct UserModeApi *pMemory) { - return pMemory->__usrmodeIsReady__(pMemory); +static inline NvBool usrmodeIsGpuMapAllowed_DISPATCH(struct UserModeApi *pMemory, struct OBJGPU *pGpu) { + return pMemory->__usrmodeIsGpuMapAllowed__(pMemory, pGpu); +} + +static inline NV_STATUS usrmodeIsReady_DISPATCH(struct UserModeApi *pMemory, NvBool bCopyConstructorContext) { + return pMemory->__usrmodeIsReady__(pMemory, bCopyConstructorContext); } static inline NV_STATUS usrmodeCheckCopyPermissions_DISPATCH(struct UserModeApi *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { @@ -211,6 +215,10 @@ static inline void usrmodePreDestruct_DISPATCH(struct UserModeApi *pResource) { pResource->__usrmodePreDestruct__(pResource); } +static inline NV_STATUS usrmodeIsDuplicate_DISPATCH(struct UserModeApi *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return pMemory->__usrmodeIsDuplicate__(pMemory, hMemory, pDuplicate); +} + static inline NV_STATUS usrmodeUnmapFrom_DISPATCH(struct UserModeApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return pResource->__usrmodeUnmapFrom__(pResource, pParams); } @@ -232,6 +240,7 @@ static inline NvBool usrmodeAccessCallback_DISPATCH(struct UserModeApi *pResourc } NV_STATUS usrmodeConstruct_IMPL(struct UserModeApi *arg_pUserModeApi, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_usrmodeConstruct(arg_pUserModeApi, arg_pCallContext, arg_pParams) usrmodeConstruct_IMPL(arg_pUserModeApi, arg_pCallContext, arg_pParams) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_uvm_channel_retainer_nvoc.c b/src/nvidia/generated/g_uvm_channel_retainer_nvoc.c index 61c27da8c..368d52345 100644 --- a/src/nvidia/generated/g_uvm_channel_retainer_nvoc.c +++ b/src/nvidia/generated/g_uvm_channel_retainer_nvoc.c @@ -165,6 +165,10 @@ static NV_STATUS __nvoc_thunk_RsResource_uvmchanrtnrUnmapFrom(struct UvmChannelR return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_uvmchanrtnrIsDuplicate(struct UvmChannelRetainer *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_uvmchanrtnrControl_Epilogue(struct UvmChannelRetainer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RmResource.offset), pCallContext, pParams); } @@ -266,6 +270,8 @@ static void __nvoc_init_funcTable_UvmChannelRetainer_1(UvmChannelRetainer *pThis pThis->__uvmchanrtnrUnmapFrom__ = &__nvoc_thunk_RsResource_uvmchanrtnrUnmapFrom; + pThis->__uvmchanrtnrIsDuplicate__ = &__nvoc_thunk_RsResource_uvmchanrtnrIsDuplicate; + pThis->__uvmchanrtnrControl_Epilogue__ = &__nvoc_thunk_RmResource_uvmchanrtnrControl_Epilogue; pThis->__uvmchanrtnrControlLookup__ = &__nvoc_thunk_RsResource_uvmchanrtnrControlLookup; diff --git a/src/nvidia/generated/g_uvm_channel_retainer_nvoc.h b/src/nvidia/generated/g_uvm_channel_retainer_nvoc.h index 9bbda2e91..413ec9ed5 100644 --- a/src/nvidia/generated/g_uvm_channel_retainer_nvoc.h +++ b/src/nvidia/generated/g_uvm_channel_retainer_nvoc.h @@ -86,6 +86,7 @@ struct UvmChannelRetainer { NV_STATUS (*__uvmchanrtnrInternalControlForward__)(struct UvmChannelRetainer *, NvU32, void *, NvU32); void (*__uvmchanrtnrPreDestruct__)(struct UvmChannelRetainer *); NV_STATUS (*__uvmchanrtnrUnmapFrom__)(struct UvmChannelRetainer *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__uvmchanrtnrIsDuplicate__)(struct UvmChannelRetainer *, NvHandle, NvBool *); void (*__uvmchanrtnrControl_Epilogue__)(struct UvmChannelRetainer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__uvmchanrtnrControlLookup__)(struct UvmChannelRetainer *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__uvmchanrtnrMap__)(struct UvmChannelRetainer *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -141,12 +142,14 @@ NV_STATUS __nvoc_objCreate_UvmChannelRetainer(UvmChannelRetainer**, Dynamic*, Nv #define uvmchanrtnrInternalControlForward(pGpuResource, command, pParams, size) uvmchanrtnrInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define uvmchanrtnrPreDestruct(pResource) uvmchanrtnrPreDestruct_DISPATCH(pResource) #define uvmchanrtnrUnmapFrom(pResource, pParams) uvmchanrtnrUnmapFrom_DISPATCH(pResource, pParams) +#define uvmchanrtnrIsDuplicate(pResource, hMemory, pDuplicate) uvmchanrtnrIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define uvmchanrtnrControl_Epilogue(pResource, pCallContext, pParams) uvmchanrtnrControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define uvmchanrtnrControlLookup(pResource, pParams, ppEntry) uvmchanrtnrControlLookup_DISPATCH(pResource, pParams, ppEntry) #define uvmchanrtnrMap(pGpuResource, pCallContext, pParams, pCpuMapping) uvmchanrtnrMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define uvmchanrtnrAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) uvmchanrtnrAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NvBool uvmchanrtnrIsAllocationAllowed_IMPL(struct UvmChannelRetainer *pUvmChannelRetainer, CALL_CONTEXT *pCallContext, struct KernelChannel *pKernelChannel); + #ifdef __nvoc_uvm_channel_retainer_h_disabled static inline NvBool uvmchanrtnrIsAllocationAllowed(struct UvmChannelRetainer *pUvmChannelRetainer, CALL_CONTEXT *pCallContext, struct KernelChannel *pKernelChannel) { NV_ASSERT_FAILED_PRECOMP("UvmChannelRetainer was disabled!"); @@ -230,6 +233,10 @@ static inline NV_STATUS uvmchanrtnrUnmapFrom_DISPATCH(struct UvmChannelRetainer return pResource->__uvmchanrtnrUnmapFrom__(pResource, pParams); } +static inline NV_STATUS uvmchanrtnrIsDuplicate_DISPATCH(struct UvmChannelRetainer *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__uvmchanrtnrIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void uvmchanrtnrControl_Epilogue_DISPATCH(struct UvmChannelRetainer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__uvmchanrtnrControl_Epilogue__(pResource, pCallContext, pParams); } @@ -247,8 +254,10 @@ static inline NvBool uvmchanrtnrAccessCallback_DISPATCH(struct UvmChannelRetaine } NV_STATUS uvmchanrtnrConstruct_IMPL(struct UvmChannelRetainer *arg_pUvmChannelRetainer, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_uvmchanrtnrConstruct(arg_pUvmChannelRetainer, arg_pCallContext, arg_pParams) uvmchanrtnrConstruct_IMPL(arg_pUvmChannelRetainer, arg_pCallContext, arg_pParams) void uvmchanrtnrDestruct_IMPL(struct UvmChannelRetainer *pUvmChannelRetainer); + #define __nvoc_uvmchanrtnrDestruct(pUvmChannelRetainer) uvmchanrtnrDestruct_IMPL(pUvmChannelRetainer) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_uvm_nvoc.c b/src/nvidia/generated/g_uvm_nvoc.c index 200130a20..7e4960d79 100644 --- a/src/nvidia/generated/g_uvm_nvoc.c +++ b/src/nvidia/generated/g_uvm_nvoc.c @@ -83,7 +83,7 @@ static NV_STATUS __nvoc_thunk_OBJUVM_engstateStateInitUnlocked(OBJGPU *pGpu, str return uvmStateInitUnlocked(pGpu, (struct OBJUVM *)(((unsigned char *)pUvm) - __nvoc_rtti_OBJUVM_OBJENGSTATE.offset)); } -static void __nvoc_thunk_OBJUVM_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *pUvm, IntrServiceRecord arg1[155]) { +static void __nvoc_thunk_OBJUVM_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *pUvm, IntrServiceRecord arg1[163]) { uvmRegisterIntrService(arg0, (struct OBJUVM *)(((unsigned char *)pUvm) - __nvoc_rtti_OBJUVM_IntrService.offset), arg1); } diff --git a/src/nvidia/generated/g_uvm_nvoc.h b/src/nvidia/generated/g_uvm_nvoc.h index de8699e9c..6134e2738 100644 --- a/src/nvidia/generated/g_uvm_nvoc.h +++ b/src/nvidia/generated/g_uvm_nvoc.h @@ -187,6 +187,7 @@ NV_STATUS __nvoc_objCreate_OBJUVM(OBJUVM**, Dynamic*, NvU32); #define uvmIsPresent(pGpu, pEngstate) uvmIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS uvmInitializeAccessCntrBuffer_IMPL(OBJGPU *pGpu, struct OBJUVM *pUvm); + #ifdef __nvoc_uvm_h_disabled static inline NV_STATUS uvmInitializeAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); @@ -200,6 +201,7 @@ static inline NV_STATUS uvmInitializeAccessCntrBuffer(OBJGPU *pGpu, struct OBJUV NV_STATUS uvmTerminateAccessCntrBuffer_IMPL(OBJGPU *pGpu, struct OBJUVM *pUvm); + #ifdef __nvoc_uvm_h_disabled static inline NV_STATUS uvmTerminateAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); @@ -213,6 +215,7 @@ static inline NV_STATUS uvmTerminateAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM NV_STATUS uvmInitAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm); + #ifdef __nvoc_uvm_h_disabled static inline NV_STATUS uvmInitAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); @@ -226,6 +229,7 @@ static inline NV_STATUS uvmInitAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUv NV_STATUS uvmDestroyAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm); + #ifdef __nvoc_uvm_h_disabled static inline NV_STATUS uvmDestroyAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); @@ -241,6 +245,7 @@ static inline NV_STATUS uvmAccessCntrBufferUnregister_ac1694(OBJGPU *arg0, struc return NV_OK; } + #ifdef __nvoc_uvm_h_disabled static inline NV_STATUS uvmAccessCntrBufferUnregister(OBJGPU *arg0, struct OBJUVM *arg1) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); @@ -256,6 +261,7 @@ static inline NV_STATUS uvmAccessCntrBufferRegister_ac1694(OBJGPU *arg0, struct return NV_OK; } + #ifdef __nvoc_uvm_h_disabled static inline NV_STATUS uvmAccessCntrBufferRegister(OBJGPU *arg0, struct OBJUVM *arg1, NvU32 arg2, RmPhysAddr *arg3) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); @@ -269,6 +275,7 @@ static inline NV_STATUS uvmAccessCntrBufferRegister(OBJGPU *arg0, struct OBJUVM NV_STATUS uvmUnloadAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm); + #ifdef __nvoc_uvm_h_disabled static inline NV_STATUS uvmUnloadAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); @@ -282,6 +289,7 @@ static inline NV_STATUS uvmUnloadAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *p NV_STATUS uvmSetupAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm); + #ifdef __nvoc_uvm_h_disabled static inline NV_STATUS uvmSetupAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); @@ -295,6 +303,7 @@ static inline NV_STATUS uvmSetupAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pU NV_STATUS uvmReadAccessCntrBufferPutPtr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 *arg0); + #ifdef __nvoc_uvm_h_disabled static inline NV_STATUS uvmReadAccessCntrBufferPutPtr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); @@ -308,6 +317,7 @@ static inline NV_STATUS uvmReadAccessCntrBufferPutPtr(OBJGPU *pGpu, struct OBJUV NV_STATUS uvmReadAccessCntrBufferGetPtr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 *arg0); + #ifdef __nvoc_uvm_h_disabled static inline NV_STATUS uvmReadAccessCntrBufferGetPtr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); @@ -321,6 +331,7 @@ static inline NV_STATUS uvmReadAccessCntrBufferGetPtr(OBJGPU *pGpu, struct OBJUV NV_STATUS uvmReadAccessCntrBufferFullPtr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvBool *arg0); + #ifdef __nvoc_uvm_h_disabled static inline NV_STATUS uvmReadAccessCntrBufferFullPtr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvBool *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); @@ -334,6 +345,7 @@ static inline NV_STATUS uvmReadAccessCntrBufferFullPtr(OBJGPU *pGpu, struct OBJU NV_STATUS uvmResetAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0); + #ifdef __nvoc_uvm_h_disabled static inline NV_STATUS uvmResetAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); @@ -347,6 +359,7 @@ static inline NV_STATUS uvmResetAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pU NV_STATUS uvmAccessCntrSetGranularity_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, ACCESS_CNTR_TYPE arg0, NvU32 arg1); + #ifdef __nvoc_uvm_h_disabled static inline NV_STATUS uvmAccessCntrSetGranularity(OBJGPU *pGpu, struct OBJUVM *pUvm, ACCESS_CNTR_TYPE arg0, NvU32 arg1) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); @@ -360,6 +373,7 @@ static inline NV_STATUS uvmAccessCntrSetGranularity(OBJGPU *pGpu, struct OBJUVM NV_STATUS uvmAccessCntrSetThreshold_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0); + #ifdef __nvoc_uvm_h_disabled static inline NV_STATUS uvmAccessCntrSetThreshold(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); @@ -373,6 +387,7 @@ static inline NV_STATUS uvmAccessCntrSetThreshold(OBJGPU *pGpu, struct OBJUVM *p NV_STATUS uvmAccessCntrSetCounterLimit_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0, NvU32 arg1); + #ifdef __nvoc_uvm_h_disabled static inline NV_STATUS uvmAccessCntrSetCounterLimit(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0, NvU32 arg1) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); @@ -386,6 +401,7 @@ static inline NV_STATUS uvmAccessCntrSetCounterLimit(OBJGPU *pGpu, struct OBJUVM NV_STATUS uvmWriteAccessCntrBufferGetPtr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0); + #ifdef __nvoc_uvm_h_disabled static inline NV_STATUS uvmWriteAccessCntrBufferGetPtr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); @@ -399,6 +415,7 @@ static inline NV_STATUS uvmWriteAccessCntrBufferGetPtr(OBJGPU *pGpu, struct OBJU NV_STATUS uvmEnableAccessCntr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvBool arg0); + #ifdef __nvoc_uvm_h_disabled static inline NV_STATUS uvmEnableAccessCntr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvBool arg0) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); @@ -412,6 +429,7 @@ static inline NV_STATUS uvmEnableAccessCntr(OBJGPU *pGpu, struct OBJUVM *pUvm, N NV_STATUS uvmDisableAccessCntr_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, NvBool arg0); + #ifdef __nvoc_uvm_h_disabled static inline NV_STATUS uvmDisableAccessCntr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvBool arg0) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); @@ -425,6 +443,7 @@ static inline NV_STATUS uvmDisableAccessCntr(OBJGPU *pGpu, struct OBJUVM *pUvm, NV_STATUS uvmEnableAccessCntrIntr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0); + #ifdef __nvoc_uvm_h_disabled static inline NV_STATUS uvmEnableAccessCntrIntr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); @@ -438,6 +457,7 @@ static inline NV_STATUS uvmEnableAccessCntrIntr(OBJGPU *pGpu, struct OBJUVM *pUv NV_STATUS uvmDisableAccessCntrIntr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm); + #ifdef __nvoc_uvm_h_disabled static inline NV_STATUS uvmDisableAccessCntrIntr(OBJGPU *pGpu, struct OBJUVM *pUvm) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); @@ -451,6 +471,7 @@ static inline NV_STATUS uvmDisableAccessCntrIntr(OBJGPU *pGpu, struct OBJUVM *pU NV_STATUS uvmGetAccessCntrRegisterMappings_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvP64 *arg0, NvP64 *arg1, NvP64 *arg2, NvP64 *arg3, NvP64 *arg4, NvP64 *arg5, NvU32 *arg6); + #ifdef __nvoc_uvm_h_disabled static inline NV_STATUS uvmGetAccessCntrRegisterMappings(OBJGPU *pGpu, struct OBJUVM *pUvm, NvP64 *arg0, NvP64 *arg1, NvP64 *arg2, NvP64 *arg3, NvP64 *arg4, NvP64 *arg5, NvU32 *arg6) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); @@ -464,6 +485,7 @@ static inline NV_STATUS uvmGetAccessCntrRegisterMappings(OBJGPU *pGpu, struct OB NV_STATUS uvmAccessCntrService_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm); + #ifdef __nvoc_uvm_h_disabled static inline NV_STATUS uvmAccessCntrService(OBJGPU *pGpu, struct OBJUVM *pUvm) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); @@ -477,6 +499,7 @@ static inline NV_STATUS uvmAccessCntrService(OBJGPU *pGpu, struct OBJUVM *pUvm) NvU32 uvmGetAccessCounterBufferSize_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm); + #ifdef __nvoc_uvm_h_disabled static inline NvU32 uvmGetAccessCounterBufferSize(OBJGPU *pGpu, struct OBJUVM *pUvm) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); @@ -488,55 +511,59 @@ static inline NvU32 uvmGetAccessCounterBufferSize(OBJGPU *pGpu, struct OBJUVM *p #define uvmGetAccessCounterBufferSize_HAL(pGpu, pUvm) uvmGetAccessCounterBufferSize(pGpu, pUvm) -void uvmWriteAccessCntrBufferHiReg_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0); +void uvmProgramWriteAccessCntrBufferAddress_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU64 addr); + #ifdef __nvoc_uvm_h_disabled -static inline void uvmWriteAccessCntrBufferHiReg(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0) { +static inline void uvmProgramWriteAccessCntrBufferAddress(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU64 addr) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); } #else //__nvoc_uvm_h_disabled -#define uvmWriteAccessCntrBufferHiReg(pGpu, pUvm, arg0) uvmWriteAccessCntrBufferHiReg_TU102(pGpu, pUvm, arg0) +#define uvmProgramWriteAccessCntrBufferAddress(pGpu, pUvm, addr) uvmProgramWriteAccessCntrBufferAddress_TU102(pGpu, pUvm, addr) #endif //__nvoc_uvm_h_disabled -#define uvmWriteAccessCntrBufferHiReg_HAL(pGpu, pUvm, arg0) uvmWriteAccessCntrBufferHiReg(pGpu, pUvm, arg0) +#define uvmProgramWriteAccessCntrBufferAddress_HAL(pGpu, pUvm, addr) uvmProgramWriteAccessCntrBufferAddress(pGpu, pUvm, addr) + +void uvmProgramAccessCntrBufferEnabled_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvBool bEn); -void uvmWriteAccessCntrBufferLoReg_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0); #ifdef __nvoc_uvm_h_disabled -static inline void uvmWriteAccessCntrBufferLoReg(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0) { +static inline void uvmProgramAccessCntrBufferEnabled(OBJGPU *pGpu, struct OBJUVM *pUvm, NvBool bEn) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); } #else //__nvoc_uvm_h_disabled -#define uvmWriteAccessCntrBufferLoReg(pGpu, pUvm, arg0) uvmWriteAccessCntrBufferLoReg_TU102(pGpu, pUvm, arg0) +#define uvmProgramAccessCntrBufferEnabled(pGpu, pUvm, bEn) uvmProgramAccessCntrBufferEnabled_TU102(pGpu, pUvm, bEn) #endif //__nvoc_uvm_h_disabled -#define uvmWriteAccessCntrBufferLoReg_HAL(pGpu, pUvm, arg0) uvmWriteAccessCntrBufferLoReg(pGpu, pUvm, arg0) +#define uvmProgramAccessCntrBufferEnabled_HAL(pGpu, pUvm, bEn) uvmProgramAccessCntrBufferEnabled(pGpu, pUvm, bEn) + +NvBool uvmIsAccessCntrBufferEnabled_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm); -NvU32 uvmReadAccessCntrBufferLoReg_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm); #ifdef __nvoc_uvm_h_disabled -static inline NvU32 uvmReadAccessCntrBufferLoReg(OBJGPU *pGpu, struct OBJUVM *pUvm) { +static inline NvBool uvmIsAccessCntrBufferEnabled(OBJGPU *pGpu, struct OBJUVM *pUvm) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); - return 0; + return NV_FALSE; } #else //__nvoc_uvm_h_disabled -#define uvmReadAccessCntrBufferLoReg(pGpu, pUvm) uvmReadAccessCntrBufferLoReg_TU102(pGpu, pUvm) +#define uvmIsAccessCntrBufferEnabled(pGpu, pUvm) uvmIsAccessCntrBufferEnabled_TU102(pGpu, pUvm) #endif //__nvoc_uvm_h_disabled -#define uvmReadAccessCntrBufferLoReg_HAL(pGpu, pUvm) uvmReadAccessCntrBufferLoReg(pGpu, pUvm) +#define uvmIsAccessCntrBufferEnabled_HAL(pGpu, pUvm) uvmIsAccessCntrBufferEnabled(pGpu, pUvm) + +NvBool uvmIsAccessCntrBufferPushed_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm); -NvU32 uvmReadAccessCntrBufferInfoReg_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm); #ifdef __nvoc_uvm_h_disabled -static inline NvU32 uvmReadAccessCntrBufferInfoReg(OBJGPU *pGpu, struct OBJUVM *pUvm) { +static inline NvBool uvmIsAccessCntrBufferPushed(OBJGPU *pGpu, struct OBJUVM *pUvm) { NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); - return 0; + return NV_FALSE; } #else //__nvoc_uvm_h_disabled -#define uvmReadAccessCntrBufferInfoReg(pGpu, pUvm) uvmReadAccessCntrBufferInfoReg_TU102(pGpu, pUvm) +#define uvmIsAccessCntrBufferPushed(pGpu, pUvm) uvmIsAccessCntrBufferPushed_TU102(pGpu, pUvm) #endif //__nvoc_uvm_h_disabled -#define uvmReadAccessCntrBufferInfoReg_HAL(pGpu, pUvm) uvmReadAccessCntrBufferInfoReg(pGpu, pUvm) +#define uvmIsAccessCntrBufferPushed_HAL(pGpu, pUvm) uvmIsAccessCntrBufferPushed(pGpu, pUvm) void uvmStateDestroy_IMPL(OBJGPU *pGpu, struct OBJUVM *pUvm); @@ -550,9 +577,9 @@ static inline NV_STATUS uvmStateInitUnlocked_DISPATCH(OBJGPU *pGpu, struct OBJUV return pUvm->__uvmStateInitUnlocked__(pGpu, pUvm); } -void uvmRegisterIntrService_IMPL(OBJGPU *arg0, struct OBJUVM *pUvm, IntrServiceRecord arg1[155]); +void uvmRegisterIntrService_IMPL(OBJGPU *arg0, struct OBJUVM *pUvm, IntrServiceRecord arg1[163]); -static inline void uvmRegisterIntrService_DISPATCH(OBJGPU *arg0, struct OBJUVM *pUvm, IntrServiceRecord arg1[155]) { +static inline void uvmRegisterIntrService_DISPATCH(OBJGPU *arg0, struct OBJUVM *pUvm, IntrServiceRecord arg1[163]) { pUvm->__uvmRegisterIntrService__(arg0, pUvm, arg1); } diff --git a/src/nvidia/generated/g_uvm_sw_nvoc.c b/src/nvidia/generated/g_uvm_sw_nvoc.c index 708821691..8e2200a1a 100644 --- a/src/nvidia/generated/g_uvm_sw_nvoc.c +++ b/src/nvidia/generated/g_uvm_sw_nvoc.c @@ -220,6 +220,10 @@ static void __nvoc_thunk_RsResource_uvmswPreDestruct(struct UvmSwObject *pResour resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmSwObject_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_RsResource_uvmswIsDuplicate(struct UvmSwObject *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmSwObject_RsResource.offset), hMemory, pDuplicate); +} + static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_uvmswGetNotificationListPtr(struct UvmSwObject *pNotifier) { return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_UvmSwObject_Notifier.offset)); } @@ -290,9 +294,6 @@ static void __nvoc_init_funcTable_UvmSwObject_1(UvmSwObject *pThis, RmHalspecOwn { pThis->__uvmswGetSwMethods__ = &uvmswGetSwMethods_56cd7a; } - else if (0) - { - } pThis->__nvoc_base_ChannelDescendant.__chandesGetSwMethods__ = &__nvoc_thunk_UvmSwObject_chandesGetSwMethods; @@ -344,6 +345,8 @@ static void __nvoc_init_funcTable_UvmSwObject_1(UvmSwObject *pThis, RmHalspecOwn pThis->__uvmswPreDestruct__ = &__nvoc_thunk_RsResource_uvmswPreDestruct; + pThis->__uvmswIsDuplicate__ = &__nvoc_thunk_RsResource_uvmswIsDuplicate; + pThis->__uvmswGetNotificationListPtr__ = &__nvoc_thunk_Notifier_uvmswGetNotificationListPtr; pThis->__uvmswGetNotificationShare__ = &__nvoc_thunk_Notifier_uvmswGetNotificationShare; diff --git a/src/nvidia/generated/g_uvm_sw_nvoc.h b/src/nvidia/generated/g_uvm_sw_nvoc.h index 60d6d1d88..d4c647737 100644 --- a/src/nvidia/generated/g_uvm_sw_nvoc.h +++ b/src/nvidia/generated/g_uvm_sw_nvoc.h @@ -82,6 +82,7 @@ struct UvmSwObject { NV_STATUS (*__uvmswUnregisterEvent__)(struct UvmSwObject *, NvHandle, NvHandle, NvHandle, NvHandle); NvBool (*__uvmswCanCopy__)(struct UvmSwObject *); void (*__uvmswPreDestruct__)(struct UvmSwObject *); + NV_STATUS (*__uvmswIsDuplicate__)(struct UvmSwObject *, NvHandle, NvBool *); PEVENTNOTIFICATION *(*__uvmswGetNotificationListPtr__)(struct UvmSwObject *); struct NotifShare *(*__uvmswGetNotificationShare__)(struct UvmSwObject *); NV_STATUS (*__uvmswMap__)(struct UvmSwObject *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -147,6 +148,7 @@ NV_STATUS __nvoc_objCreate_UvmSwObject(UvmSwObject**, Dynamic*, NvU32, struct CA #define uvmswUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) uvmswUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define uvmswCanCopy(pResource) uvmswCanCopy_DISPATCH(pResource) #define uvmswPreDestruct(pResource) uvmswPreDestruct_DISPATCH(pResource) +#define uvmswIsDuplicate(pResource, hMemory, pDuplicate) uvmswIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define uvmswGetNotificationListPtr(pNotifier) uvmswGetNotificationListPtr_DISPATCH(pNotifier) #define uvmswGetNotificationShare(pNotifier) uvmswGetNotificationShare_DISPATCH(pNotifier) #define uvmswMap(pGpuResource, pCallContext, pParams, pCpuMapping) uvmswMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -255,6 +257,10 @@ static inline void uvmswPreDestruct_DISPATCH(struct UvmSwObject *pResource) { pResource->__uvmswPreDestruct__(pResource); } +static inline NV_STATUS uvmswIsDuplicate_DISPATCH(struct UvmSwObject *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__uvmswIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline PEVENTNOTIFICATION *uvmswGetNotificationListPtr_DISPATCH(struct UvmSwObject *pNotifier) { return pNotifier->__uvmswGetNotificationListPtr__(pNotifier); } @@ -272,10 +278,13 @@ static inline NV_STATUS uvmswGetOrAllocNotifShare_DISPATCH(struct UvmSwObject *p } NV_STATUS uvmswConstruct_IMPL(struct UvmSwObject *arg_pUvmSw, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_uvmswConstruct(arg_pUvmSw, arg_pCallContext, arg_pParams) uvmswConstruct_IMPL(arg_pUvmSw, arg_pCallContext, arg_pParams) void uvmswDestruct_IMPL(struct UvmSwObject *pUvmSw); + #define __nvoc_uvmswDestruct(pUvmSw) uvmswDestruct_IMPL(pUvmSw) void uvmswInitSwMethodState_IMPL(struct UvmSwObject *pUvmSw); + #ifdef __nvoc_uvm_sw_h_disabled static inline void uvmswInitSwMethodState(struct UvmSwObject *pUvmSw) { NV_ASSERT_FAILED_PRECOMP("UvmSwObject was disabled!"); diff --git a/src/nvidia/generated/g_vaspace_api_nvoc.c b/src/nvidia/generated/g_vaspace_api_nvoc.c index f3da323ea..27369a163 100644 --- a/src/nvidia/generated/g_vaspace_api_nvoc.c +++ b/src/nvidia/generated/g_vaspace_api_nvoc.c @@ -165,6 +165,10 @@ static NV_STATUS __nvoc_thunk_RsResource_vaspaceapiUnmapFrom(struct VaSpaceApi * return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_vaspaceapiIsDuplicate(struct VaSpaceApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_vaspaceapiControl_Epilogue(struct VaSpaceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RmResource.offset), pCallContext, pParams); } @@ -203,12 +207,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_VaSpaceA #endif }, { /* [1] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x80000u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) vaspaceapiCtrlCmdVaspaceGetPageLevelInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) - /*flags=*/ 0x0u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x80000u) + /*flags=*/ 0x80000u, /*accessRight=*/0x0u, /*methodId=*/ 0x90f10102u, /*paramSize=*/ sizeof(NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS), @@ -218,12 +222,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_VaSpaceA #endif }, { /* [2] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x80000u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) vaspaceapiCtrlCmdVaspaceReserveEntries_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) - /*flags=*/ 0x0u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x80000u) + /*flags=*/ 0x80000u, /*accessRight=*/0x0u, /*methodId=*/ 0x90f10103u, /*paramSize=*/ sizeof(NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS), @@ -233,12 +237,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_VaSpaceA #endif }, { /* [3] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x80000u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) vaspaceapiCtrlCmdVaspaceReleaseEntries_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) - /*flags=*/ 0x0u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x80000u) + /*flags=*/ 0x80000u, /*accessRight=*/0x0u, /*methodId=*/ 0x90f10104u, /*paramSize=*/ sizeof(NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS), @@ -248,12 +252,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_VaSpaceA #endif }, { /* [4] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) vaspaceapiCtrlCmdVaspaceCopyServerReservedPdes_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) - /*flags=*/ 0x4u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) + /*flags=*/ 0x140004u, /*accessRight=*/0x0u, /*methodId=*/ 0x90f10106u, /*paramSize=*/ sizeof(NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS), @@ -310,19 +314,19 @@ static void __nvoc_init_funcTable_VaSpaceApi_1(VaSpaceApi *pThis) { pThis->__vaspaceapiCtrlCmdVaspaceGetGmmuFormat__ = &vaspaceapiCtrlCmdVaspaceGetGmmuFormat_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x80000u) pThis->__vaspaceapiCtrlCmdVaspaceGetPageLevelInfo__ = &vaspaceapiCtrlCmdVaspaceGetPageLevelInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x80000u) pThis->__vaspaceapiCtrlCmdVaspaceReserveEntries__ = &vaspaceapiCtrlCmdVaspaceReserveEntries_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x80000u) pThis->__vaspaceapiCtrlCmdVaspaceReleaseEntries__ = &vaspaceapiCtrlCmdVaspaceReleaseEntries_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) pThis->__vaspaceapiCtrlCmdVaspaceCopyServerReservedPdes__ = &vaspaceapiCtrlCmdVaspaceCopyServerReservedPdes_IMPL; #endif @@ -362,6 +366,8 @@ static void __nvoc_init_funcTable_VaSpaceApi_1(VaSpaceApi *pThis) { pThis->__vaspaceapiUnmapFrom__ = &__nvoc_thunk_RsResource_vaspaceapiUnmapFrom; + pThis->__vaspaceapiIsDuplicate__ = &__nvoc_thunk_RsResource_vaspaceapiIsDuplicate; + pThis->__vaspaceapiControl_Epilogue__ = &__nvoc_thunk_RmResource_vaspaceapiControl_Epilogue; pThis->__vaspaceapiControlLookup__ = &__nvoc_thunk_RsResource_vaspaceapiControlLookup; diff --git a/src/nvidia/generated/g_vaspace_api_nvoc.h b/src/nvidia/generated/g_vaspace_api_nvoc.h index 43877f7b5..caa2af86b 100644 --- a/src/nvidia/generated/g_vaspace_api_nvoc.h +++ b/src/nvidia/generated/g_vaspace_api_nvoc.h @@ -90,6 +90,7 @@ struct VaSpaceApi { NV_STATUS (*__vaspaceapiInternalControlForward__)(struct VaSpaceApi *, NvU32, void *, NvU32); void (*__vaspaceapiPreDestruct__)(struct VaSpaceApi *); NV_STATUS (*__vaspaceapiUnmapFrom__)(struct VaSpaceApi *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__vaspaceapiIsDuplicate__)(struct VaSpaceApi *, NvHandle, NvBool *); void (*__vaspaceapiControl_Epilogue__)(struct VaSpaceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vaspaceapiControlLookup__)(struct VaSpaceApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__vaspaceapiMap__)(struct VaSpaceApi *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -149,6 +150,7 @@ NV_STATUS __nvoc_objCreate_VaSpaceApi(VaSpaceApi**, Dynamic*, NvU32, struct CALL #define vaspaceapiInternalControlForward(pGpuResource, command, pParams, size) vaspaceapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define vaspaceapiPreDestruct(pResource) vaspaceapiPreDestruct_DISPATCH(pResource) #define vaspaceapiUnmapFrom(pResource, pParams) vaspaceapiUnmapFrom_DISPATCH(pResource, pParams) +#define vaspaceapiIsDuplicate(pResource, hMemory, pDuplicate) vaspaceapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define vaspaceapiControl_Epilogue(pResource, pCallContext, pParams) vaspaceapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define vaspaceapiControlLookup(pResource, pParams, ppEntry) vaspaceapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define vaspaceapiMap(pGpuResource, pCallContext, pParams, pCpuMapping) vaspaceapiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -257,6 +259,10 @@ static inline NV_STATUS vaspaceapiUnmapFrom_DISPATCH(struct VaSpaceApi *pResourc return pResource->__vaspaceapiUnmapFrom__(pResource, pParams); } +static inline NV_STATUS vaspaceapiIsDuplicate_DISPATCH(struct VaSpaceApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__vaspaceapiIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void vaspaceapiControl_Epilogue_DISPATCH(struct VaSpaceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__vaspaceapiControl_Epilogue__(pResource, pCallContext, pParams); } @@ -274,8 +280,10 @@ static inline NvBool vaspaceapiAccessCallback_DISPATCH(struct VaSpaceApi *pResou } NV_STATUS vaspaceapiConstruct_IMPL(struct VaSpaceApi *arg_pResource, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_vaspaceapiConstruct(arg_pResource, arg_pCallContext, arg_pParams) vaspaceapiConstruct_IMPL(arg_pResource, arg_pCallContext, arg_pParams) NV_STATUS vaspaceapiCopyConstruct_IMPL(struct VaSpaceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); + #ifdef __nvoc_vaspace_api_h_disabled static inline NV_STATUS vaspaceapiCopyConstruct(struct VaSpaceApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { NV_ASSERT_FAILED_PRECOMP("VaSpaceApi was disabled!"); @@ -286,6 +294,7 @@ static inline NV_STATUS vaspaceapiCopyConstruct(struct VaSpaceApi *pResource, st #endif //__nvoc_vaspace_api_h_disabled void vaspaceapiDestruct_IMPL(struct VaSpaceApi *pResource); + #define __nvoc_vaspaceapiDestruct(pResource) vaspaceapiDestruct_IMPL(pResource) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_vaspace_nvoc.c b/src/nvidia/generated/g_vaspace_nvoc.c index a0ff813f9..ad775654e 100644 --- a/src/nvidia/generated/g_vaspace_nvoc.c +++ b/src/nvidia/generated/g_vaspace_nvoc.c @@ -153,6 +153,8 @@ static void __nvoc_init_funcTable_OBJVASPACE_1(OBJVASPACE *pThis) { pThis->__vaspaceGetPteInfo__ = &vaspaceGetPteInfo_b7902c; pThis->__vaspaceSetPteInfo__ = &vaspaceSetPteInfo_b7902c; + + pThis->__vaspaceFreeV2__ = &vaspaceFreeV2_b7902c; } void __nvoc_init_funcTable_OBJVASPACE(OBJVASPACE *pThis) { diff --git a/src/nvidia/generated/g_vaspace_nvoc.h b/src/nvidia/generated/g_vaspace_nvoc.h index 09f356ef1..6369c1188 100644 --- a/src/nvidia/generated/g_vaspace_nvoc.h +++ b/src/nvidia/generated/g_vaspace_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -169,7 +169,7 @@ typedef enum #define VASPACE_FLAGS_RESTRICTED_RM_INTERNAL_VALIMITS NVBIT(3) #define VASPACE_FLAGS_MINIMIZE_PTETABLE_SIZE NVBIT(4) #define VASPACE_FLAGS_RETRY_PTE_ALLOC_IN_SYS NVBIT(5) -// unused NVBIT(6) +#define VASPACE_FLAGS_REQUIRE_FIXED_OFFSET NVBIT(6) #define VASPACE_FLAGS_BAR_BAR1 NVBIT(7) #define VASPACE_FLAGS_BAR_BAR2 NVBIT(8) #define VASPACE_FLAGS_BAR_IFB NVBIT(9) @@ -270,6 +270,7 @@ struct OBJVASPACE { NV_STATUS (*__vaspaceGetPageTableInfo__)(struct OBJVASPACE *, NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS *); NV_STATUS (*__vaspaceGetPteInfo__)(struct OBJVASPACE *, struct OBJGPU *, NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS *, RmPhysAddr *); NV_STATUS (*__vaspaceSetPteInfo__)(struct OBJVASPACE *, struct OBJGPU *, NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS *); + NV_STATUS (*__vaspaceFreeV2__)(struct OBJVASPACE *, NvU64, NvU64 *); NvU32 gpuMask; ADDRESS_TRANSLATION addressTranslation; NvU32 refCnt; @@ -335,6 +336,7 @@ NV_STATUS __nvoc_objCreate_OBJVASPACE(OBJVASPACE**, Dynamic*, NvU32); #define vaspaceGetPageTableInfo(pVAS, pParams) vaspaceGetPageTableInfo_DISPATCH(pVAS, pParams) #define vaspaceGetPteInfo(pVAS, pGpu, pParams, pPhysAddr) vaspaceGetPteInfo_DISPATCH(pVAS, pGpu, pParams, pPhysAddr) #define vaspaceSetPteInfo(pVAS, pGpu, pParams) vaspaceSetPteInfo_DISPATCH(pVAS, pGpu, pParams) +#define vaspaceFreeV2(pVAS, vAddr, pSize) vaspaceFreeV2_DISPATCH(pVAS, vAddr, pSize) static inline NV_STATUS vaspaceConstruct__DISPATCH(struct OBJVASPACE *pVAS, NvU32 classId, NvU32 vaspaceId, NvU64 vaStart, NvU64 vaLimit, NvU64 vaStartInternal, NvU64 vaLimitInternal, NvU32 flags) { return pVAS->__vaspaceConstruct___(pVAS, classId, vaspaceId, vaStart, vaLimit, vaStartInternal, vaLimitInternal, flags); } @@ -555,7 +557,17 @@ static inline NV_STATUS vaspaceSetPteInfo_DISPATCH(struct OBJVASPACE *pVAS, stru return pVAS->__vaspaceSetPteInfo__(pVAS, pGpu, pParams); } +static inline NV_STATUS vaspaceFreeV2_b7902c(struct OBJVASPACE *pVAS, NvU64 vAddr, NvU64 *pSize) { + NV_ASSERT_PRECOMP(((NvBool)(0 != 0))); + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS vaspaceFreeV2_DISPATCH(struct OBJVASPACE *pVAS, NvU64 vAddr, NvU64 *pSize) { + return pVAS->__vaspaceFreeV2__(pVAS, vAddr, pSize); +} + void vaspaceIncRefCnt_IMPL(struct OBJVASPACE *pVAS); + #ifdef __nvoc_vaspace_h_disabled static inline void vaspaceIncRefCnt(struct OBJVASPACE *pVAS) { NV_ASSERT_FAILED_PRECOMP("OBJVASPACE was disabled!"); @@ -565,6 +577,7 @@ static inline void vaspaceIncRefCnt(struct OBJVASPACE *pVAS) { #endif //__nvoc_vaspace_h_disabled void vaspaceDecRefCnt_IMPL(struct OBJVASPACE *pVAS); + #ifdef __nvoc_vaspace_h_disabled static inline void vaspaceDecRefCnt(struct OBJVASPACE *pVAS) { NV_ASSERT_FAILED_PRECOMP("OBJVASPACE was disabled!"); @@ -574,8 +587,10 @@ static inline void vaspaceDecRefCnt(struct OBJVASPACE *pVAS) { #endif //__nvoc_vaspace_h_disabled NV_STATUS vaspaceGetByHandleOrDeviceDefault_IMPL(struct RsClient *pClient, NvHandle hDeviceOrSubDevice, NvHandle hVASpace, struct OBJVASPACE **ppVAS); + #define vaspaceGetByHandleOrDeviceDefault(pClient, hDeviceOrSubDevice, hVASpace, ppVAS) vaspaceGetByHandleOrDeviceDefault_IMPL(pClient, hDeviceOrSubDevice, hVASpace, ppVAS) NV_STATUS vaspaceFillAllocParams_IMPL(struct OBJVASPACE *pVAS, const FB_ALLOC_INFO *pAllocInfo, NvU64 *pSize, NvU64 *pAlign, NvU64 *pRangeLo, NvU64 *pRangeHi, NvU64 *pPageSizeLockMask, VAS_ALLOC_FLAGS *pFlags); + #ifdef __nvoc_vaspace_h_disabled static inline NV_STATUS vaspaceFillAllocParams(struct OBJVASPACE *pVAS, const FB_ALLOC_INFO *pAllocInfo, NvU64 *pSize, NvU64 *pAlign, NvU64 *pRangeLo, NvU64 *pRangeHi, NvU64 *pPageSizeLockMask, VAS_ALLOC_FLAGS *pFlags) { NV_ASSERT_FAILED_PRECOMP("OBJVASPACE was disabled!"); diff --git a/src/nvidia/generated/g_vblank_callback_nvoc.c b/src/nvidia/generated/g_vblank_callback_nvoc.c index 47214af47..f718525c0 100644 --- a/src/nvidia/generated/g_vblank_callback_nvoc.c +++ b/src/nvidia/generated/g_vblank_callback_nvoc.c @@ -165,6 +165,10 @@ static NV_STATUS __nvoc_thunk_RsResource_vblcbUnmapFrom(struct VblankCallback *p return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_vblcbIsDuplicate(struct VblankCallback *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_vblcbControl_Epilogue(struct VblankCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RmResource.offset), pCallContext, pParams); } @@ -284,6 +288,8 @@ static void __nvoc_init_funcTable_VblankCallback_1(VblankCallback *pThis) { pThis->__vblcbUnmapFrom__ = &__nvoc_thunk_RsResource_vblcbUnmapFrom; + pThis->__vblcbIsDuplicate__ = &__nvoc_thunk_RsResource_vblcbIsDuplicate; + pThis->__vblcbControl_Epilogue__ = &__nvoc_thunk_RmResource_vblcbControl_Epilogue; pThis->__vblcbControlLookup__ = &__nvoc_thunk_RsResource_vblcbControlLookup; diff --git a/src/nvidia/generated/g_vblank_callback_nvoc.h b/src/nvidia/generated/g_vblank_callback_nvoc.h index d03e6fad6..20d9556ea 100644 --- a/src/nvidia/generated/g_vblank_callback_nvoc.h +++ b/src/nvidia/generated/g_vblank_callback_nvoc.h @@ -81,14 +81,15 @@ struct VblankCallback { NV_STATUS (*__vblcbInternalControlForward__)(struct VblankCallback *, NvU32, void *, NvU32); void (*__vblcbPreDestruct__)(struct VblankCallback *); NV_STATUS (*__vblcbUnmapFrom__)(struct VblankCallback *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__vblcbIsDuplicate__)(struct VblankCallback *, NvHandle, NvBool *); void (*__vblcbControl_Epilogue__)(struct VblankCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vblcbControlLookup__)(struct VblankCallback *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__vblcbMap__)(struct VblankCallback *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__vblcbAccessCallback__)(struct VblankCallback *, struct RsClient *, void *, RsAccessRight); VBLANKCALLBACK CallBack; OSVBLANKCALLBACKPROC pProc; - void *pParm1; - void *pParm2; + NvP64 pParm1; + NvP64 pParm2; NvU32 LogicalHead; }; @@ -139,6 +140,7 @@ NV_STATUS __nvoc_objCreate_VblankCallback(VblankCallback**, Dynamic*, NvU32, CAL #define vblcbInternalControlForward(pGpuResource, command, pParams, size) vblcbInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define vblcbPreDestruct(pResource) vblcbPreDestruct_DISPATCH(pResource) #define vblcbUnmapFrom(pResource, pParams) vblcbUnmapFrom_DISPATCH(pResource, pParams) +#define vblcbIsDuplicate(pResource, hMemory, pDuplicate) vblcbIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define vblcbControl_Epilogue(pResource, pCallContext, pParams) vblcbControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define vblcbControlLookup(pResource, pParams, ppEntry) vblcbControlLookup_DISPATCH(pResource, pParams, ppEntry) #define vblcbMap(pGpuResource, pCallContext, pParams, pCpuMapping) vblcbMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -221,6 +223,10 @@ static inline NV_STATUS vblcbUnmapFrom_DISPATCH(struct VblankCallback *pResource return pResource->__vblcbUnmapFrom__(pResource, pParams); } +static inline NV_STATUS vblcbIsDuplicate_DISPATCH(struct VblankCallback *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__vblcbIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void vblcbControl_Epilogue_DISPATCH(struct VblankCallback *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__vblcbControl_Epilogue__(pResource, pCallContext, pParams); } @@ -238,8 +244,10 @@ static inline NvBool vblcbAccessCallback_DISPATCH(struct VblankCallback *pResour } NV_STATUS vblcbConstruct_IMPL(struct VblankCallback *arg_pVblankCallback, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_vblcbConstruct(arg_pVblankCallback, arg_pCallContext, arg_pParams) vblcbConstruct_IMPL(arg_pVblankCallback, arg_pCallContext, arg_pParams) void vblcbDestruct_IMPL(struct VblankCallback *pVblankCallback); + #define __nvoc_vblcbDestruct(pVblankCallback) vblcbDestruct_IMPL(pVblankCallback) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_vgpuconfigapi_nvoc.c b/src/nvidia/generated/g_vgpuconfigapi_nvoc.c new file mode 100644 index 000000000..87b139091 --- /dev/null +++ b/src/nvidia/generated/g_vgpuconfigapi_nvoc.c @@ -0,0 +1,744 @@ +#define NVOC_VGPUCONFIGAPI_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_vgpuconfigapi_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0x4d560a = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_VgpuConfigApi; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RsResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResourceCommon; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_GpuResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_INotifier; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Notifier; + +void __nvoc_init_VgpuConfigApi(VgpuConfigApi*); +void __nvoc_init_funcTable_VgpuConfigApi(VgpuConfigApi*); +NV_STATUS __nvoc_ctor_VgpuConfigApi(VgpuConfigApi*, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +void __nvoc_init_dataField_VgpuConfigApi(VgpuConfigApi*); +void __nvoc_dtor_VgpuConfigApi(VgpuConfigApi*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_VgpuConfigApi; + +static const struct NVOC_RTTI __nvoc_rtti_VgpuConfigApi_VgpuConfigApi = { + /*pClassDef=*/ &__nvoc_class_def_VgpuConfigApi, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_VgpuConfigApi, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_VgpuConfigApi_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(VgpuConfigApi, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_VgpuConfigApi_RsResource = { + /*pClassDef=*/ &__nvoc_class_def_RsResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(VgpuConfigApi, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_VgpuConfigApi_RmResourceCommon = { + /*pClassDef=*/ &__nvoc_class_def_RmResourceCommon, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(VgpuConfigApi, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon), +}; + +static const struct NVOC_RTTI __nvoc_rtti_VgpuConfigApi_RmResource = { + /*pClassDef=*/ &__nvoc_class_def_RmResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(VgpuConfigApi, __nvoc_base_GpuResource.__nvoc_base_RmResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_VgpuConfigApi_GpuResource = { + /*pClassDef=*/ &__nvoc_class_def_GpuResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(VgpuConfigApi, __nvoc_base_GpuResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_VgpuConfigApi_INotifier = { + /*pClassDef=*/ &__nvoc_class_def_INotifier, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(VgpuConfigApi, __nvoc_base_Notifier.__nvoc_base_INotifier), +}; + +static const struct NVOC_RTTI __nvoc_rtti_VgpuConfigApi_Notifier = { + /*pClassDef=*/ &__nvoc_class_def_Notifier, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(VgpuConfigApi, __nvoc_base_Notifier), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_VgpuConfigApi = { + /*numRelatives=*/ 8, + /*relatives=*/ { + &__nvoc_rtti_VgpuConfigApi_VgpuConfigApi, + &__nvoc_rtti_VgpuConfigApi_Notifier, + &__nvoc_rtti_VgpuConfigApi_INotifier, + &__nvoc_rtti_VgpuConfigApi_GpuResource, + &__nvoc_rtti_VgpuConfigApi_RmResource, + &__nvoc_rtti_VgpuConfigApi_RmResourceCommon, + &__nvoc_rtti_VgpuConfigApi_RsResource, + &__nvoc_rtti_VgpuConfigApi_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_VgpuConfigApi = +{ + /*classInfo=*/ { + /*size=*/ sizeof(VgpuConfigApi), + /*classId=*/ classId(VgpuConfigApi), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "VgpuConfigApi", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_VgpuConfigApi, + /*pCastInfo=*/ &__nvoc_castinfo_VgpuConfigApi, + /*pExportInfo=*/ &__nvoc_export_info_VgpuConfigApi +}; + +static NvBool __nvoc_thunk_GpuResource_vgpuconfigapiShareCallback(struct VgpuConfigApi *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VgpuConfigApi_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RsResource_vgpuconfigapiMapTo(struct VgpuConfigApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuConfigApi_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Notifier_vgpuconfigapiGetOrAllocNotifShare(struct VgpuConfigApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { + return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_VgpuConfigApi_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); +} + +static NV_STATUS __nvoc_thunk_RmResource_vgpuconfigapiCheckMemInterUnmap(struct VgpuConfigApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VgpuConfigApi_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_GpuResource_vgpuconfigapiGetMapAddrSpace(struct VgpuConfigApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VgpuConfigApi_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static void __nvoc_thunk_Notifier_vgpuconfigapiSetNotificationShare(struct VgpuConfigApi *pNotifier, struct NotifShare *pNotifShare) { + notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_VgpuConfigApi_Notifier.offset), pNotifShare); +} + +static NvU32 __nvoc_thunk_RsResource_vgpuconfigapiGetRefCount(struct VgpuConfigApi *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuConfigApi_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_vgpuconfigapiAddAdditionalDependants(struct RsClient *pClient, struct VgpuConfigApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuConfigApi_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_vgpuconfigapiControl_Prologue(struct VgpuConfigApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuConfigApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_vgpuconfigapiGetRegBaseOffsetAndSize(struct VgpuConfigApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VgpuConfigApi_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NV_STATUS __nvoc_thunk_GpuResource_vgpuconfigapiInternalControlForward(struct VgpuConfigApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VgpuConfigApi_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_vgpuconfigapiUnmapFrom(struct VgpuConfigApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuConfigApi_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_vgpuconfigapiControl_Epilogue(struct VgpuConfigApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuConfigApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_vgpuconfigapiControlLookup(struct VgpuConfigApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuConfigApi_RsResource.offset), pParams, ppEntry); +} + +static NvHandle __nvoc_thunk_GpuResource_vgpuconfigapiGetInternalObjectHandle(struct VgpuConfigApi *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VgpuConfigApi_GpuResource.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_vgpuconfigapiControl(struct VgpuConfigApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VgpuConfigApi_GpuResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_vgpuconfigapiUnmap(struct VgpuConfigApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VgpuConfigApi_GpuResource.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_RmResource_vgpuconfigapiGetMemInterMapParams(struct VgpuConfigApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VgpuConfigApi_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_vgpuconfigapiGetMemoryMappingDescriptor(struct VgpuConfigApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VgpuConfigApi_RmResource.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_vgpuconfigapiControlFilter(struct VgpuConfigApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuConfigApi_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_Notifier_vgpuconfigapiUnregisterEvent(struct VgpuConfigApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { + return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_VgpuConfigApi_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); +} + +static NvBool __nvoc_thunk_RsResource_vgpuconfigapiCanCopy(struct VgpuConfigApi *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuConfigApi_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_vgpuconfigapiPreDestruct(struct VgpuConfigApi *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuConfigApi_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_vgpuconfigapiIsDuplicate(struct VgpuConfigApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuConfigApi_RsResource.offset), hMemory, pDuplicate); +} + +static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_vgpuconfigapiGetNotificationListPtr(struct VgpuConfigApi *pNotifier) { + return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_VgpuConfigApi_Notifier.offset)); +} + +static struct NotifShare *__nvoc_thunk_Notifier_vgpuconfigapiGetNotificationShare(struct VgpuConfigApi *pNotifier) { + return notifyGetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_VgpuConfigApi_Notifier.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_vgpuconfigapiMap(struct VgpuConfigApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { + return gpuresMap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VgpuConfigApi_GpuResource.offset), pCallContext, pParams, pCpuMapping); +} + +static NvBool __nvoc_thunk_RmResource_vgpuconfigapiAccessCallback(struct VgpuConfigApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuConfigApi_RmResource.offset), pInvokingClient, pAllocParams, accessRight); +} + +#if !defined(NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG) +#define NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(x) (0) +#endif + +static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_VgpuConfigApi[] = +{ + { /* [0] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) vgpuconfigapiCtrlCmdVgpuConfigSetInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa0810101u, + /*paramSize=*/ sizeof(NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_VgpuConfigApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "vgpuconfigapiCtrlCmdVgpuConfigSetInfo" +#endif + }, + { /* [1] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) vgpuconfigapiCtrlCmdVgpuConfigEnumerateVgpuPerPgpu_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa0810102u, + /*paramSize=*/ sizeof(NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_VgpuConfigApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "vgpuconfigapiCtrlCmdVgpuConfigEnumerateVgpuPerPgpu" +#endif + }, + { /* [2] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) vgpuconfigapiCtrlCmdVgpuConfigGetVgpuTypeInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa0810103u, + /*paramSize=*/ sizeof(NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_VgpuConfigApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "vgpuconfigapiCtrlCmdVgpuConfigGetVgpuTypeInfo" +#endif + }, + { /* [3] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) vgpuconfigapiCtrlCmdVgpuConfigGetSupportedVgpuTypes_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa0810104u, + /*paramSize=*/ sizeof(NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_VgpuConfigApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "vgpuconfigapiCtrlCmdVgpuConfigGetSupportedVgpuTypes" +#endif + }, + { /* [4] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) vgpuconfigapiCtrlCmdVgpuConfigGetCreatableVgpuTypes_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa0810105u, + /*paramSize=*/ sizeof(NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_VgpuConfigApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "vgpuconfigapiCtrlCmdVgpuConfigGetCreatableVgpuTypes" +#endif + }, + { /* [5] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) vgpuconfigapiCtrlCmdVgpuConfigEventSetNotification_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa0810106u, + /*paramSize=*/ sizeof(NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_VgpuConfigApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "vgpuconfigapiCtrlCmdVgpuConfigEventSetNotification" +#endif + }, + { /* [6] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) vgpuconfigapiCtrlCmdVgpuConfigNotifyStart_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa0810107u, + /*paramSize=*/ sizeof(NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_VgpuConfigApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "vgpuconfigapiCtrlCmdVgpuConfigNotifyStart" +#endif + }, + { /* [7] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) vgpuconfigapiCtrlCmdVgpuConfigMdevRegister_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa0810109u, + /*paramSize=*/ 0, + /*pClassInfo=*/ &(__nvoc_class_def_VgpuConfigApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "vgpuconfigapiCtrlCmdVgpuConfigMdevRegister" +#endif + }, + { /* [8] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) vgpuconfigapiCtrlCmdVgpuConfigSetVgpuInstanceEncoderCapacity_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa0810110u, + /*paramSize=*/ sizeof(NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_VgpuConfigApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "vgpuconfigapiCtrlCmdVgpuConfigSetVgpuInstanceEncoderCapacity" +#endif + }, + { /* [9] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) vgpuconfigapiCtrlCmdVgpuConfigGetVgpuFbUsage_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa0810111u, + /*paramSize=*/ sizeof(NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_VgpuConfigApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "vgpuconfigapiCtrlCmdVgpuConfigGetVgpuFbUsage" +#endif + }, + { /* [10] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) vgpuconfigapiCtrlCmdVgpuConfigGetMigrationCap_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa0810112u, + /*paramSize=*/ sizeof(NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_VgpuConfigApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "vgpuconfigapiCtrlCmdVgpuConfigGetMigrationCap" +#endif + }, + { /* [11] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) vgpuconfigapiCtrlCmdVgpuConfigGetHostFbReservation_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa0810113u, + /*paramSize=*/ sizeof(NVA081_CTRL_VGPU_CONFIG_GET_HOST_FB_RESERVATION_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_VgpuConfigApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "vgpuconfigapiCtrlCmdVgpuConfigGetHostFbReservation" +#endif + }, + { /* [12] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) vgpuconfigapiCtrlCmdVgpuConfigGetPgpuMetadataString_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa0810114u, + /*paramSize=*/ sizeof(NVA081_CTRL_VGPU_CONFIG_GET_PGPU_METADATA_STRING_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_VgpuConfigApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "vgpuconfigapiCtrlCmdVgpuConfigGetPgpuMetadataString" +#endif + }, + { /* [13] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) vgpuconfigapiCtrlCmdVgpuConfigGetDoorbellEmulationSupport_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa0810115u, + /*paramSize=*/ sizeof(NVA081_CTRL_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_VgpuConfigApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "vgpuconfigapiCtrlCmdVgpuConfigGetDoorbellEmulationSupport" +#endif + }, + { /* [14] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) vgpuconfigapiCtrlCmdVgpuConfigGetFreeSwizzId_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*flags=*/ 0x4u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa0810116u, + /*paramSize=*/ sizeof(NVA081_CTRL_VGPU_CONFIG_GET_FREE_SWIZZID_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_VgpuConfigApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "vgpuconfigapiCtrlCmdVgpuConfigGetFreeSwizzId" +#endif + }, + { /* [15] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) vgpuconfigapiCtrlCmdPgpuGetMultiVgpuSupportInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa0810117u, + /*paramSize=*/ sizeof(NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_VgpuConfigApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "vgpuconfigapiCtrlCmdPgpuGetMultiVgpuSupportInfo" +#endif + }, + { /* [16] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) vgpuconfigapiCtrlCmdGetVgpuDriversCaps_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa0810118u, + /*paramSize=*/ sizeof(NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_VgpuConfigApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "vgpuconfigapiCtrlCmdGetVgpuDriversCaps" +#endif + }, + { /* [17] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) vgpuconfigapiCtrlCmdVgpuConfigSetPgpuInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*flags=*/ 0x4u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa0810119u, + /*paramSize=*/ sizeof(NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_VgpuConfigApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "vgpuconfigapiCtrlCmdVgpuConfigSetPgpuInfo" +#endif + }, + +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_VgpuConfigApi = +{ + /*numEntries=*/ 18, + /*pExportEntries=*/ __nvoc_exported_method_def_VgpuConfigApi +}; + +void __nvoc_dtor_GpuResource(GpuResource*); +void __nvoc_dtor_Notifier(Notifier*); +void __nvoc_dtor_VgpuConfigApi(VgpuConfigApi *pThis) { + __nvoc_vgpuconfigapiDestruct(pThis); + __nvoc_dtor_GpuResource(&pThis->__nvoc_base_GpuResource); + __nvoc_dtor_Notifier(&pThis->__nvoc_base_Notifier); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_VgpuConfigApi(VgpuConfigApi *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_GpuResource(GpuResource* , struct CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); +NV_STATUS __nvoc_ctor_Notifier(Notifier* , struct CALL_CONTEXT *); +NV_STATUS __nvoc_ctor_VgpuConfigApi(VgpuConfigApi *pThis, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_GpuResource(&pThis->__nvoc_base_GpuResource, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_VgpuConfigApi_fail_GpuResource; + status = __nvoc_ctor_Notifier(&pThis->__nvoc_base_Notifier, arg_pCallContext); + if (status != NV_OK) goto __nvoc_ctor_VgpuConfigApi_fail_Notifier; + __nvoc_init_dataField_VgpuConfigApi(pThis); + + status = __nvoc_vgpuconfigapiConstruct(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_VgpuConfigApi_fail__init; + goto __nvoc_ctor_VgpuConfigApi_exit; // Success + +__nvoc_ctor_VgpuConfigApi_fail__init: + __nvoc_dtor_Notifier(&pThis->__nvoc_base_Notifier); +__nvoc_ctor_VgpuConfigApi_fail_Notifier: + __nvoc_dtor_GpuResource(&pThis->__nvoc_base_GpuResource); +__nvoc_ctor_VgpuConfigApi_fail_GpuResource: +__nvoc_ctor_VgpuConfigApi_exit: + + return status; +} + +static void __nvoc_init_funcTable_VgpuConfigApi_1(VgpuConfigApi *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__vgpuconfigapiCtrlCmdVgpuConfigSetInfo__ = &vgpuconfigapiCtrlCmdVgpuConfigSetInfo_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__vgpuconfigapiCtrlCmdVgpuConfigEnumerateVgpuPerPgpu__ = &vgpuconfigapiCtrlCmdVgpuConfigEnumerateVgpuPerPgpu_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__vgpuconfigapiCtrlCmdVgpuConfigGetVgpuTypeInfo__ = &vgpuconfigapiCtrlCmdVgpuConfigGetVgpuTypeInfo_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__vgpuconfigapiCtrlCmdVgpuConfigGetSupportedVgpuTypes__ = &vgpuconfigapiCtrlCmdVgpuConfigGetSupportedVgpuTypes_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__vgpuconfigapiCtrlCmdVgpuConfigGetCreatableVgpuTypes__ = &vgpuconfigapiCtrlCmdVgpuConfigGetCreatableVgpuTypes_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__vgpuconfigapiCtrlCmdVgpuConfigEventSetNotification__ = &vgpuconfigapiCtrlCmdVgpuConfigEventSetNotification_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__vgpuconfigapiCtrlCmdVgpuConfigNotifyStart__ = &vgpuconfigapiCtrlCmdVgpuConfigNotifyStart_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__vgpuconfigapiCtrlCmdVgpuConfigMdevRegister__ = &vgpuconfigapiCtrlCmdVgpuConfigMdevRegister_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__vgpuconfigapiCtrlCmdVgpuConfigSetVgpuInstanceEncoderCapacity__ = &vgpuconfigapiCtrlCmdVgpuConfigSetVgpuInstanceEncoderCapacity_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__vgpuconfigapiCtrlCmdVgpuConfigGetVgpuFbUsage__ = &vgpuconfigapiCtrlCmdVgpuConfigGetVgpuFbUsage_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__vgpuconfigapiCtrlCmdVgpuConfigGetMigrationCap__ = &vgpuconfigapiCtrlCmdVgpuConfigGetMigrationCap_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__vgpuconfigapiCtrlCmdVgpuConfigGetHostFbReservation__ = &vgpuconfigapiCtrlCmdVgpuConfigGetHostFbReservation_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__vgpuconfigapiCtrlCmdVgpuConfigGetPgpuMetadataString__ = &vgpuconfigapiCtrlCmdVgpuConfigGetPgpuMetadataString_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__vgpuconfigapiCtrlCmdVgpuConfigGetDoorbellEmulationSupport__ = &vgpuconfigapiCtrlCmdVgpuConfigGetDoorbellEmulationSupport_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + pThis->__vgpuconfigapiCtrlCmdVgpuConfigGetFreeSwizzId__ = &vgpuconfigapiCtrlCmdVgpuConfigGetFreeSwizzId_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__vgpuconfigapiCtrlCmdPgpuGetMultiVgpuSupportInfo__ = &vgpuconfigapiCtrlCmdPgpuGetMultiVgpuSupportInfo_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__vgpuconfigapiCtrlCmdGetVgpuDriversCaps__ = &vgpuconfigapiCtrlCmdGetVgpuDriversCaps_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + pThis->__vgpuconfigapiCtrlCmdVgpuConfigSetPgpuInfo__ = &vgpuconfigapiCtrlCmdVgpuConfigSetPgpuInfo_IMPL; +#endif + + pThis->__vgpuconfigapiShareCallback__ = &__nvoc_thunk_GpuResource_vgpuconfigapiShareCallback; + + pThis->__vgpuconfigapiMapTo__ = &__nvoc_thunk_RsResource_vgpuconfigapiMapTo; + + pThis->__vgpuconfigapiGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_vgpuconfigapiGetOrAllocNotifShare; + + pThis->__vgpuconfigapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_vgpuconfigapiCheckMemInterUnmap; + + pThis->__vgpuconfigapiGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_vgpuconfigapiGetMapAddrSpace; + + pThis->__vgpuconfigapiSetNotificationShare__ = &__nvoc_thunk_Notifier_vgpuconfigapiSetNotificationShare; + + pThis->__vgpuconfigapiGetRefCount__ = &__nvoc_thunk_RsResource_vgpuconfigapiGetRefCount; + + pThis->__vgpuconfigapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_vgpuconfigapiAddAdditionalDependants; + + pThis->__vgpuconfigapiControl_Prologue__ = &__nvoc_thunk_RmResource_vgpuconfigapiControl_Prologue; + + pThis->__vgpuconfigapiGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_vgpuconfigapiGetRegBaseOffsetAndSize; + + pThis->__vgpuconfigapiInternalControlForward__ = &__nvoc_thunk_GpuResource_vgpuconfigapiInternalControlForward; + + pThis->__vgpuconfigapiUnmapFrom__ = &__nvoc_thunk_RsResource_vgpuconfigapiUnmapFrom; + + pThis->__vgpuconfigapiControl_Epilogue__ = &__nvoc_thunk_RmResource_vgpuconfigapiControl_Epilogue; + + pThis->__vgpuconfigapiControlLookup__ = &__nvoc_thunk_RsResource_vgpuconfigapiControlLookup; + + pThis->__vgpuconfigapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_vgpuconfigapiGetInternalObjectHandle; + + pThis->__vgpuconfigapiControl__ = &__nvoc_thunk_GpuResource_vgpuconfigapiControl; + + pThis->__vgpuconfigapiUnmap__ = &__nvoc_thunk_GpuResource_vgpuconfigapiUnmap; + + pThis->__vgpuconfigapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_vgpuconfigapiGetMemInterMapParams; + + pThis->__vgpuconfigapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_vgpuconfigapiGetMemoryMappingDescriptor; + + pThis->__vgpuconfigapiControlFilter__ = &__nvoc_thunk_RsResource_vgpuconfigapiControlFilter; + + pThis->__vgpuconfigapiUnregisterEvent__ = &__nvoc_thunk_Notifier_vgpuconfigapiUnregisterEvent; + + pThis->__vgpuconfigapiCanCopy__ = &__nvoc_thunk_RsResource_vgpuconfigapiCanCopy; + + pThis->__vgpuconfigapiPreDestruct__ = &__nvoc_thunk_RsResource_vgpuconfigapiPreDestruct; + + pThis->__vgpuconfigapiIsDuplicate__ = &__nvoc_thunk_RsResource_vgpuconfigapiIsDuplicate; + + pThis->__vgpuconfigapiGetNotificationListPtr__ = &__nvoc_thunk_Notifier_vgpuconfigapiGetNotificationListPtr; + + pThis->__vgpuconfigapiGetNotificationShare__ = &__nvoc_thunk_Notifier_vgpuconfigapiGetNotificationShare; + + pThis->__vgpuconfigapiMap__ = &__nvoc_thunk_GpuResource_vgpuconfigapiMap; + + pThis->__vgpuconfigapiAccessCallback__ = &__nvoc_thunk_RmResource_vgpuconfigapiAccessCallback; +} + +void __nvoc_init_funcTable_VgpuConfigApi(VgpuConfigApi *pThis) { + __nvoc_init_funcTable_VgpuConfigApi_1(pThis); +} + +void __nvoc_init_GpuResource(GpuResource*); +void __nvoc_init_Notifier(Notifier*); +void __nvoc_init_VgpuConfigApi(VgpuConfigApi *pThis) { + pThis->__nvoc_pbase_VgpuConfigApi = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; + pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource; + pThis->__nvoc_pbase_RmResourceCommon = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon; + pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource; + pThis->__nvoc_pbase_GpuResource = &pThis->__nvoc_base_GpuResource; + pThis->__nvoc_pbase_INotifier = &pThis->__nvoc_base_Notifier.__nvoc_base_INotifier; + pThis->__nvoc_pbase_Notifier = &pThis->__nvoc_base_Notifier; + __nvoc_init_GpuResource(&pThis->__nvoc_base_GpuResource); + __nvoc_init_Notifier(&pThis->__nvoc_base_Notifier); + __nvoc_init_funcTable_VgpuConfigApi(pThis); +} + +NV_STATUS __nvoc_objCreate_VgpuConfigApi(VgpuConfigApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status; + Object *pParentObj; + VgpuConfigApi *pThis; + + pThis = portMemAllocNonPaged(sizeof(VgpuConfigApi)); + if (pThis == NULL) return NV_ERR_NO_MEMORY; + + portMemSet(pThis, 0, sizeof(VgpuConfigApi)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_VgpuConfigApi); + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_VgpuConfigApi(pThis); + status = __nvoc_ctor_VgpuConfigApi(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_objCreate_VgpuConfigApi_cleanup; + + *ppThis = pThis; + return NV_OK; + +__nvoc_objCreate_VgpuConfigApi_cleanup: + // do not call destructors here since the constructor already called them + portMemFree(pThis); + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_VgpuConfigApi(VgpuConfigApi **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + struct CALL_CONTEXT * arg_pCallContext = va_arg(args, struct CALL_CONTEXT *); + struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams = va_arg(args, struct RS_RES_ALLOC_PARAMS_INTERNAL *); + + status = __nvoc_objCreate_VgpuConfigApi(ppThis, pParent, createFlags, arg_pCallContext, arg_pParams); + + return status; +} + diff --git a/src/nvidia/generated/g_vgpuconfigapi_nvoc.h b/src/nvidia/generated/g_vgpuconfigapi_nvoc.h new file mode 100644 index 000000000..f1b3dde95 --- /dev/null +++ b/src/nvidia/generated/g_vgpuconfigapi_nvoc.h @@ -0,0 +1,424 @@ +#ifndef _G_VGPUCONFIGAPI_NVOC_H_ +#define _G_VGPUCONFIGAPI_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#include "g_vgpuconfigapi_nvoc.h" + +#ifndef _VGPUCONFIGAPI_H_ +#define _VGPUCONFIGAPI_H_ + +#include "core/core.h" +#include "class/cla081.h" +#include "rmapi/client.h" +#include "gpu/gpu_resource.h" +#include "rmapi/event.h" + +#include "ctrl/ctrla081.h" // rmcontrol params + +// +// Virtual GPU configuration information +// + +#ifdef NVOC_VGPUCONFIGAPI_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct VgpuConfigApi { + const struct NVOC_RTTI *__nvoc_rtti; + struct GpuResource __nvoc_base_GpuResource; + struct Notifier __nvoc_base_Notifier; + struct Object *__nvoc_pbase_Object; + struct RsResource *__nvoc_pbase_RsResource; + struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; + struct RmResource *__nvoc_pbase_RmResource; + struct GpuResource *__nvoc_pbase_GpuResource; + struct INotifier *__nvoc_pbase_INotifier; + struct Notifier *__nvoc_pbase_Notifier; + struct VgpuConfigApi *__nvoc_pbase_VgpuConfigApi; + NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigSetInfo__)(struct VgpuConfigApi *, NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS *); + NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigEnumerateVgpuPerPgpu__)(struct VgpuConfigApi *, NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS *); + NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigGetVgpuTypeInfo__)(struct VgpuConfigApi *, NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS *); + NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigGetSupportedVgpuTypes__)(struct VgpuConfigApi *, NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS *); + NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigGetCreatableVgpuTypes__)(struct VgpuConfigApi *, NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS *); + NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigEventSetNotification__)(struct VgpuConfigApi *, NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS *); + NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigNotifyStart__)(struct VgpuConfigApi *, NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS *); + NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigMdevRegister__)(struct VgpuConfigApi *); + NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigSetVgpuInstanceEncoderCapacity__)(struct VgpuConfigApi *, NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS *); + NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigGetVgpuFbUsage__)(struct VgpuConfigApi *, NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS *); + NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigGetMigrationCap__)(struct VgpuConfigApi *, NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS *); + NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigGetHostFbReservation__)(struct VgpuConfigApi *, NVA081_CTRL_VGPU_CONFIG_GET_HOST_FB_RESERVATION_PARAMS *); + NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigGetPgpuMetadataString__)(struct VgpuConfigApi *, NVA081_CTRL_VGPU_CONFIG_GET_PGPU_METADATA_STRING_PARAMS *); + NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigGetDoorbellEmulationSupport__)(struct VgpuConfigApi *, NVA081_CTRL_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT_PARAMS *); + NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigGetFreeSwizzId__)(struct VgpuConfigApi *, NVA081_CTRL_VGPU_CONFIG_GET_FREE_SWIZZID_PARAMS *); + NV_STATUS (*__vgpuconfigapiCtrlCmdPgpuGetMultiVgpuSupportInfo__)(struct VgpuConfigApi *, NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS *); + NV_STATUS (*__vgpuconfigapiCtrlCmdGetVgpuDriversCaps__)(struct VgpuConfigApi *, NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS *); + NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigSetPgpuInfo__)(struct VgpuConfigApi *, NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS *); + NvBool (*__vgpuconfigapiShareCallback__)(struct VgpuConfigApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__vgpuconfigapiMapTo__)(struct VgpuConfigApi *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__vgpuconfigapiGetOrAllocNotifShare__)(struct VgpuConfigApi *, NvHandle, NvHandle, struct NotifShare **); + NV_STATUS (*__vgpuconfigapiCheckMemInterUnmap__)(struct VgpuConfigApi *, NvBool); + NV_STATUS (*__vgpuconfigapiGetMapAddrSpace__)(struct VgpuConfigApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + void (*__vgpuconfigapiSetNotificationShare__)(struct VgpuConfigApi *, struct NotifShare *); + NvU32 (*__vgpuconfigapiGetRefCount__)(struct VgpuConfigApi *); + void (*__vgpuconfigapiAddAdditionalDependants__)(struct RsClient *, struct VgpuConfigApi *, RsResourceRef *); + NV_STATUS (*__vgpuconfigapiControl_Prologue__)(struct VgpuConfigApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__vgpuconfigapiGetRegBaseOffsetAndSize__)(struct VgpuConfigApi *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__vgpuconfigapiInternalControlForward__)(struct VgpuConfigApi *, NvU32, void *, NvU32); + NV_STATUS (*__vgpuconfigapiUnmapFrom__)(struct VgpuConfigApi *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__vgpuconfigapiControl_Epilogue__)(struct VgpuConfigApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__vgpuconfigapiControlLookup__)(struct VgpuConfigApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__vgpuconfigapiGetInternalObjectHandle__)(struct VgpuConfigApi *); + NV_STATUS (*__vgpuconfigapiControl__)(struct VgpuConfigApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__vgpuconfigapiUnmap__)(struct VgpuConfigApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__vgpuconfigapiGetMemInterMapParams__)(struct VgpuConfigApi *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__vgpuconfigapiGetMemoryMappingDescriptor__)(struct VgpuConfigApi *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__vgpuconfigapiControlFilter__)(struct VgpuConfigApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__vgpuconfigapiUnregisterEvent__)(struct VgpuConfigApi *, NvHandle, NvHandle, NvHandle, NvHandle); + NvBool (*__vgpuconfigapiCanCopy__)(struct VgpuConfigApi *); + void (*__vgpuconfigapiPreDestruct__)(struct VgpuConfigApi *); + NV_STATUS (*__vgpuconfigapiIsDuplicate__)(struct VgpuConfigApi *, NvHandle, NvBool *); + PEVENTNOTIFICATION *(*__vgpuconfigapiGetNotificationListPtr__)(struct VgpuConfigApi *); + struct NotifShare *(*__vgpuconfigapiGetNotificationShare__)(struct VgpuConfigApi *); + NV_STATUS (*__vgpuconfigapiMap__)(struct VgpuConfigApi *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); + NvBool (*__vgpuconfigapiAccessCallback__)(struct VgpuConfigApi *, struct RsClient *, void *, RsAccessRight); + NvU32 notifyActions[5]; +}; + +#ifndef __NVOC_CLASS_VgpuConfigApi_TYPEDEF__ +#define __NVOC_CLASS_VgpuConfigApi_TYPEDEF__ +typedef struct VgpuConfigApi VgpuConfigApi; +#endif /* __NVOC_CLASS_VgpuConfigApi_TYPEDEF__ */ + +#ifndef __nvoc_class_id_VgpuConfigApi +#define __nvoc_class_id_VgpuConfigApi 0x4d560a +#endif /* __nvoc_class_id_VgpuConfigApi */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_VgpuConfigApi; + +#define __staticCast_VgpuConfigApi(pThis) \ + ((pThis)->__nvoc_pbase_VgpuConfigApi) + +#ifdef __nvoc_vgpuconfigapi_h_disabled +#define __dynamicCast_VgpuConfigApi(pThis) ((VgpuConfigApi*)NULL) +#else //__nvoc_vgpuconfigapi_h_disabled +#define __dynamicCast_VgpuConfigApi(pThis) \ + ((VgpuConfigApi*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(VgpuConfigApi))) +#endif //__nvoc_vgpuconfigapi_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_VgpuConfigApi(VgpuConfigApi**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_VgpuConfigApi(VgpuConfigApi**, Dynamic*, NvU32, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +#define __objCreate_VgpuConfigApi(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ + __nvoc_objCreate_VgpuConfigApi((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) + +#define vgpuconfigapiCtrlCmdVgpuConfigSetInfo(pVgpuConfigApi, pParams) vgpuconfigapiCtrlCmdVgpuConfigSetInfo_DISPATCH(pVgpuConfigApi, pParams) +#define vgpuconfigapiCtrlCmdVgpuConfigEnumerateVgpuPerPgpu(pVgpuConfigApi, pParams) vgpuconfigapiCtrlCmdVgpuConfigEnumerateVgpuPerPgpu_DISPATCH(pVgpuConfigApi, pParams) +#define vgpuconfigapiCtrlCmdVgpuConfigGetVgpuTypeInfo(pVgpuConfigApi, pParams) vgpuconfigapiCtrlCmdVgpuConfigGetVgpuTypeInfo_DISPATCH(pVgpuConfigApi, pParams) +#define vgpuconfigapiCtrlCmdVgpuConfigGetSupportedVgpuTypes(pVgpuConfigApi, pParams) vgpuconfigapiCtrlCmdVgpuConfigGetSupportedVgpuTypes_DISPATCH(pVgpuConfigApi, pParams) +#define vgpuconfigapiCtrlCmdVgpuConfigGetCreatableVgpuTypes(pVgpuConfigApi, pParams) vgpuconfigapiCtrlCmdVgpuConfigGetCreatableVgpuTypes_DISPATCH(pVgpuConfigApi, pParams) +#define vgpuconfigapiCtrlCmdVgpuConfigEventSetNotification(pVgpuConfigApi, pSetEventParams) vgpuconfigapiCtrlCmdVgpuConfigEventSetNotification_DISPATCH(pVgpuConfigApi, pSetEventParams) +#define vgpuconfigapiCtrlCmdVgpuConfigNotifyStart(pVgpuConfigApi, pNotifyParams) vgpuconfigapiCtrlCmdVgpuConfigNotifyStart_DISPATCH(pVgpuConfigApi, pNotifyParams) +#define vgpuconfigapiCtrlCmdVgpuConfigMdevRegister(pVgpuConfigApi) vgpuconfigapiCtrlCmdVgpuConfigMdevRegister_DISPATCH(pVgpuConfigApi) +#define vgpuconfigapiCtrlCmdVgpuConfigSetVgpuInstanceEncoderCapacity(pVgpuConfigApi, pEncoderParams) vgpuconfigapiCtrlCmdVgpuConfigSetVgpuInstanceEncoderCapacity_DISPATCH(pVgpuConfigApi, pEncoderParams) +#define vgpuconfigapiCtrlCmdVgpuConfigGetVgpuFbUsage(pVgpuConfigApi, pParams) vgpuconfigapiCtrlCmdVgpuConfigGetVgpuFbUsage_DISPATCH(pVgpuConfigApi, pParams) +#define vgpuconfigapiCtrlCmdVgpuConfigGetMigrationCap(pVgpuConfigApi, pParams) vgpuconfigapiCtrlCmdVgpuConfigGetMigrationCap_DISPATCH(pVgpuConfigApi, pParams) +#define vgpuconfigapiCtrlCmdVgpuConfigGetHostFbReservation(pVgpuConfigApi, pParams) vgpuconfigapiCtrlCmdVgpuConfigGetHostFbReservation_DISPATCH(pVgpuConfigApi, pParams) +#define vgpuconfigapiCtrlCmdVgpuConfigGetPgpuMetadataString(pVgpuConfigApi, pGpuMetadataStringParams) vgpuconfigapiCtrlCmdVgpuConfigGetPgpuMetadataString_DISPATCH(pVgpuConfigApi, pGpuMetadataStringParams) +#define vgpuconfigapiCtrlCmdVgpuConfigGetDoorbellEmulationSupport(pVgpuConfigApi, pParams) vgpuconfigapiCtrlCmdVgpuConfigGetDoorbellEmulationSupport_DISPATCH(pVgpuConfigApi, pParams) +#define vgpuconfigapiCtrlCmdVgpuConfigGetFreeSwizzId(pVgpuConfigApi, pParams) vgpuconfigapiCtrlCmdVgpuConfigGetFreeSwizzId_DISPATCH(pVgpuConfigApi, pParams) +#define vgpuconfigapiCtrlCmdPgpuGetMultiVgpuSupportInfo(pVgpuConfigApi, pParams) vgpuconfigapiCtrlCmdPgpuGetMultiVgpuSupportInfo_DISPATCH(pVgpuConfigApi, pParams) +#define vgpuconfigapiCtrlCmdGetVgpuDriversCaps(pVgpuConfigApi, pParams) vgpuconfigapiCtrlCmdGetVgpuDriversCaps_DISPATCH(pVgpuConfigApi, pParams) +#define vgpuconfigapiCtrlCmdVgpuConfigSetPgpuInfo(pVgpuConfigApi, pParams) vgpuconfigapiCtrlCmdVgpuConfigSetPgpuInfo_DISPATCH(pVgpuConfigApi, pParams) +#define vgpuconfigapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) vgpuconfigapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define vgpuconfigapiMapTo(pResource, pParams) vgpuconfigapiMapTo_DISPATCH(pResource, pParams) +#define vgpuconfigapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) vgpuconfigapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +#define vgpuconfigapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) vgpuconfigapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define vgpuconfigapiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) vgpuconfigapiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define vgpuconfigapiSetNotificationShare(pNotifier, pNotifShare) vgpuconfigapiSetNotificationShare_DISPATCH(pNotifier, pNotifShare) +#define vgpuconfigapiGetRefCount(pResource) vgpuconfigapiGetRefCount_DISPATCH(pResource) +#define vgpuconfigapiAddAdditionalDependants(pClient, pResource, pReference) vgpuconfigapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define vgpuconfigapiControl_Prologue(pResource, pCallContext, pParams) vgpuconfigapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define vgpuconfigapiGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) vgpuconfigapiGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define vgpuconfigapiInternalControlForward(pGpuResource, command, pParams, size) vgpuconfigapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define vgpuconfigapiUnmapFrom(pResource, pParams) vgpuconfigapiUnmapFrom_DISPATCH(pResource, pParams) +#define vgpuconfigapiControl_Epilogue(pResource, pCallContext, pParams) vgpuconfigapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define vgpuconfigapiControlLookup(pResource, pParams, ppEntry) vgpuconfigapiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define vgpuconfigapiGetInternalObjectHandle(pGpuResource) vgpuconfigapiGetInternalObjectHandle_DISPATCH(pGpuResource) +#define vgpuconfigapiControl(pGpuResource, pCallContext, pParams) vgpuconfigapiControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define vgpuconfigapiUnmap(pGpuResource, pCallContext, pCpuMapping) vgpuconfigapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define vgpuconfigapiGetMemInterMapParams(pRmResource, pParams) vgpuconfigapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define vgpuconfigapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) vgpuconfigapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define vgpuconfigapiControlFilter(pResource, pCallContext, pParams) vgpuconfigapiControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define vgpuconfigapiUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) vgpuconfigapiUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define vgpuconfigapiCanCopy(pResource) vgpuconfigapiCanCopy_DISPATCH(pResource) +#define vgpuconfigapiPreDestruct(pResource) vgpuconfigapiPreDestruct_DISPATCH(pResource) +#define vgpuconfigapiIsDuplicate(pResource, hMemory, pDuplicate) vgpuconfigapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define vgpuconfigapiGetNotificationListPtr(pNotifier) vgpuconfigapiGetNotificationListPtr_DISPATCH(pNotifier) +#define vgpuconfigapiGetNotificationShare(pNotifier) vgpuconfigapiGetNotificationShare_DISPATCH(pNotifier) +#define vgpuconfigapiMap(pGpuResource, pCallContext, pParams, pCpuMapping) vgpuconfigapiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) +#define vgpuconfigapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) vgpuconfigapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigSetInfo_IMPL(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS *pParams); + +static inline NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigSetInfo_DISPATCH(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS *pParams) { + return pVgpuConfigApi->__vgpuconfigapiCtrlCmdVgpuConfigSetInfo__(pVgpuConfigApi, pParams); +} + +NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigEnumerateVgpuPerPgpu_IMPL(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS *pParams); + +static inline NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigEnumerateVgpuPerPgpu_DISPATCH(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS *pParams) { + return pVgpuConfigApi->__vgpuconfigapiCtrlCmdVgpuConfigEnumerateVgpuPerPgpu__(pVgpuConfigApi, pParams); +} + +NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigGetVgpuTypeInfo_IMPL(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS *pParams); + +static inline NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigGetVgpuTypeInfo_DISPATCH(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS *pParams) { + return pVgpuConfigApi->__vgpuconfigapiCtrlCmdVgpuConfigGetVgpuTypeInfo__(pVgpuConfigApi, pParams); +} + +NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigGetSupportedVgpuTypes_IMPL(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS *pParams); + +static inline NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigGetSupportedVgpuTypes_DISPATCH(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS *pParams) { + return pVgpuConfigApi->__vgpuconfigapiCtrlCmdVgpuConfigGetSupportedVgpuTypes__(pVgpuConfigApi, pParams); +} + +NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigGetCreatableVgpuTypes_IMPL(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS *pParams); + +static inline NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigGetCreatableVgpuTypes_DISPATCH(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS *pParams) { + return pVgpuConfigApi->__vgpuconfigapiCtrlCmdVgpuConfigGetCreatableVgpuTypes__(pVgpuConfigApi, pParams); +} + +NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigEventSetNotification_IMPL(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS *pSetEventParams); + +static inline NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigEventSetNotification_DISPATCH(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS *pSetEventParams) { + return pVgpuConfigApi->__vgpuconfigapiCtrlCmdVgpuConfigEventSetNotification__(pVgpuConfigApi, pSetEventParams); +} + +NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigNotifyStart_IMPL(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS *pNotifyParams); + +static inline NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigNotifyStart_DISPATCH(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS *pNotifyParams) { + return pVgpuConfigApi->__vgpuconfigapiCtrlCmdVgpuConfigNotifyStart__(pVgpuConfigApi, pNotifyParams); +} + +NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigMdevRegister_IMPL(struct VgpuConfigApi *pVgpuConfigApi); + +static inline NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigMdevRegister_DISPATCH(struct VgpuConfigApi *pVgpuConfigApi) { + return pVgpuConfigApi->__vgpuconfigapiCtrlCmdVgpuConfigMdevRegister__(pVgpuConfigApi); +} + +NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigSetVgpuInstanceEncoderCapacity_IMPL(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS *pEncoderParams); + +static inline NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigSetVgpuInstanceEncoderCapacity_DISPATCH(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS *pEncoderParams) { + return pVgpuConfigApi->__vgpuconfigapiCtrlCmdVgpuConfigSetVgpuInstanceEncoderCapacity__(pVgpuConfigApi, pEncoderParams); +} + +NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigGetVgpuFbUsage_IMPL(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS *pParams); + +static inline NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigGetVgpuFbUsage_DISPATCH(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS *pParams) { + return pVgpuConfigApi->__vgpuconfigapiCtrlCmdVgpuConfigGetVgpuFbUsage__(pVgpuConfigApi, pParams); +} + +NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigGetMigrationCap_IMPL(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS *pParams); + +static inline NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigGetMigrationCap_DISPATCH(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS *pParams) { + return pVgpuConfigApi->__vgpuconfigapiCtrlCmdVgpuConfigGetMigrationCap__(pVgpuConfigApi, pParams); +} + +NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigGetHostFbReservation_IMPL(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_GET_HOST_FB_RESERVATION_PARAMS *pParams); + +static inline NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigGetHostFbReservation_DISPATCH(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_GET_HOST_FB_RESERVATION_PARAMS *pParams) { + return pVgpuConfigApi->__vgpuconfigapiCtrlCmdVgpuConfigGetHostFbReservation__(pVgpuConfigApi, pParams); +} + +NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigGetPgpuMetadataString_IMPL(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_GET_PGPU_METADATA_STRING_PARAMS *pGpuMetadataStringParams); + +static inline NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigGetPgpuMetadataString_DISPATCH(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_GET_PGPU_METADATA_STRING_PARAMS *pGpuMetadataStringParams) { + return pVgpuConfigApi->__vgpuconfigapiCtrlCmdVgpuConfigGetPgpuMetadataString__(pVgpuConfigApi, pGpuMetadataStringParams); +} + +NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigGetDoorbellEmulationSupport_IMPL(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT_PARAMS *pParams); + +static inline NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigGetDoorbellEmulationSupport_DISPATCH(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT_PARAMS *pParams) { + return pVgpuConfigApi->__vgpuconfigapiCtrlCmdVgpuConfigGetDoorbellEmulationSupport__(pVgpuConfigApi, pParams); +} + +NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigGetFreeSwizzId_IMPL(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_GET_FREE_SWIZZID_PARAMS *pParams); + +static inline NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigGetFreeSwizzId_DISPATCH(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_GET_FREE_SWIZZID_PARAMS *pParams) { + return pVgpuConfigApi->__vgpuconfigapiCtrlCmdVgpuConfigGetFreeSwizzId__(pVgpuConfigApi, pParams); +} + +NV_STATUS vgpuconfigapiCtrlCmdPgpuGetMultiVgpuSupportInfo_IMPL(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS *pParams); + +static inline NV_STATUS vgpuconfigapiCtrlCmdPgpuGetMultiVgpuSupportInfo_DISPATCH(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS *pParams) { + return pVgpuConfigApi->__vgpuconfigapiCtrlCmdPgpuGetMultiVgpuSupportInfo__(pVgpuConfigApi, pParams); +} + +NV_STATUS vgpuconfigapiCtrlCmdGetVgpuDriversCaps_IMPL(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS *pParams); + +static inline NV_STATUS vgpuconfigapiCtrlCmdGetVgpuDriversCaps_DISPATCH(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS *pParams) { + return pVgpuConfigApi->__vgpuconfigapiCtrlCmdGetVgpuDriversCaps__(pVgpuConfigApi, pParams); +} + +NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigSetPgpuInfo_IMPL(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS *pParams); + +static inline NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigSetPgpuInfo_DISPATCH(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS *pParams) { + return pVgpuConfigApi->__vgpuconfigapiCtrlCmdVgpuConfigSetPgpuInfo__(pVgpuConfigApi, pParams); +} + +static inline NvBool vgpuconfigapiShareCallback_DISPATCH(struct VgpuConfigApi *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pGpuResource->__vgpuconfigapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS vgpuconfigapiMapTo_DISPATCH(struct VgpuConfigApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__vgpuconfigapiMapTo__(pResource, pParams); +} + +static inline NV_STATUS vgpuconfigapiGetOrAllocNotifShare_DISPATCH(struct VgpuConfigApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { + return pNotifier->__vgpuconfigapiGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); +} + +static inline NV_STATUS vgpuconfigapiCheckMemInterUnmap_DISPATCH(struct VgpuConfigApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__vgpuconfigapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS vgpuconfigapiGetMapAddrSpace_DISPATCH(struct VgpuConfigApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__vgpuconfigapiGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline void vgpuconfigapiSetNotificationShare_DISPATCH(struct VgpuConfigApi *pNotifier, struct NotifShare *pNotifShare) { + pNotifier->__vgpuconfigapiSetNotificationShare__(pNotifier, pNotifShare); +} + +static inline NvU32 vgpuconfigapiGetRefCount_DISPATCH(struct VgpuConfigApi *pResource) { + return pResource->__vgpuconfigapiGetRefCount__(pResource); +} + +static inline void vgpuconfigapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct VgpuConfigApi *pResource, RsResourceRef *pReference) { + pResource->__vgpuconfigapiAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS vgpuconfigapiControl_Prologue_DISPATCH(struct VgpuConfigApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__vgpuconfigapiControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS vgpuconfigapiGetRegBaseOffsetAndSize_DISPATCH(struct VgpuConfigApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__vgpuconfigapiGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NV_STATUS vgpuconfigapiInternalControlForward_DISPATCH(struct VgpuConfigApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__vgpuconfigapiInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS vgpuconfigapiUnmapFrom_DISPATCH(struct VgpuConfigApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__vgpuconfigapiUnmapFrom__(pResource, pParams); +} + +static inline void vgpuconfigapiControl_Epilogue_DISPATCH(struct VgpuConfigApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__vgpuconfigapiControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS vgpuconfigapiControlLookup_DISPATCH(struct VgpuConfigApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__vgpuconfigapiControlLookup__(pResource, pParams, ppEntry); +} + +static inline NvHandle vgpuconfigapiGetInternalObjectHandle_DISPATCH(struct VgpuConfigApi *pGpuResource) { + return pGpuResource->__vgpuconfigapiGetInternalObjectHandle__(pGpuResource); +} + +static inline NV_STATUS vgpuconfigapiControl_DISPATCH(struct VgpuConfigApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__vgpuconfigapiControl__(pGpuResource, pCallContext, pParams); +} + +static inline NV_STATUS vgpuconfigapiUnmap_DISPATCH(struct VgpuConfigApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__vgpuconfigapiUnmap__(pGpuResource, pCallContext, pCpuMapping); +} + +static inline NV_STATUS vgpuconfigapiGetMemInterMapParams_DISPATCH(struct VgpuConfigApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__vgpuconfigapiGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS vgpuconfigapiGetMemoryMappingDescriptor_DISPATCH(struct VgpuConfigApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__vgpuconfigapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +} + +static inline NV_STATUS vgpuconfigapiControlFilter_DISPATCH(struct VgpuConfigApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__vgpuconfigapiControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS vgpuconfigapiUnregisterEvent_DISPATCH(struct VgpuConfigApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { + return pNotifier->__vgpuconfigapiUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); +} + +static inline NvBool vgpuconfigapiCanCopy_DISPATCH(struct VgpuConfigApi *pResource) { + return pResource->__vgpuconfigapiCanCopy__(pResource); +} + +static inline void vgpuconfigapiPreDestruct_DISPATCH(struct VgpuConfigApi *pResource) { + pResource->__vgpuconfigapiPreDestruct__(pResource); +} + +static inline NV_STATUS vgpuconfigapiIsDuplicate_DISPATCH(struct VgpuConfigApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__vgpuconfigapiIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline PEVENTNOTIFICATION *vgpuconfigapiGetNotificationListPtr_DISPATCH(struct VgpuConfigApi *pNotifier) { + return pNotifier->__vgpuconfigapiGetNotificationListPtr__(pNotifier); +} + +static inline struct NotifShare *vgpuconfigapiGetNotificationShare_DISPATCH(struct VgpuConfigApi *pNotifier) { + return pNotifier->__vgpuconfigapiGetNotificationShare__(pNotifier); +} + +static inline NV_STATUS vgpuconfigapiMap_DISPATCH(struct VgpuConfigApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__vgpuconfigapiMap__(pGpuResource, pCallContext, pParams, pCpuMapping); +} + +static inline NvBool vgpuconfigapiAccessCallback_DISPATCH(struct VgpuConfigApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return pResource->__vgpuconfigapiAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); +} + +NV_STATUS vgpuconfigapiConstruct_IMPL(struct VgpuConfigApi *arg_pResource, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + +#define __nvoc_vgpuconfigapiConstruct(arg_pResource, arg_pCallContext, arg_pParams) vgpuconfigapiConstruct_IMPL(arg_pResource, arg_pCallContext, arg_pParams) +void vgpuconfigapiDestruct_IMPL(struct VgpuConfigApi *pResource); + +#define __nvoc_vgpuconfigapiDestruct(pResource) vgpuconfigapiDestruct_IMPL(pResource) +#undef PRIVATE_FIELD + + +void CliNotifyVgpuConfigEvent (OBJGPU *, NvU32); + +#endif // _VGPUCONFIGAPI_H_ + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_VGPUCONFIGAPI_NVOC_H_ diff --git a/src/nvidia/generated/g_video_mem_nvoc.c b/src/nvidia/generated/g_video_mem_nvoc.c index 3104aff19..c65e26c7d 100644 --- a/src/nvidia/generated/g_video_mem_nvoc.c +++ b/src/nvidia/generated/g_video_mem_nvoc.c @@ -150,22 +150,30 @@ static NV_STATUS __nvoc_thunk_RsResource_vidmemMapTo(struct VideoMemory *pResour return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RmResource_vidmemControl_Prologue(struct VideoMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RmResource.offset), pCallContext, pParams); -} - static NvBool __nvoc_thunk_StandardMemory_vidmemCanCopy(struct VideoMemory *pStandardMemory) { return stdmemCanCopy((struct StandardMemory *)(((unsigned char *)pStandardMemory) + __nvoc_rtti_VideoMemory_StandardMemory.offset)); } -static NV_STATUS __nvoc_thunk_Memory_vidmemIsReady(struct VideoMemory *pMemory) { - return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VideoMemory_Memory.offset)); +static NvBool __nvoc_thunk_Memory_vidmemIsGpuMapAllowed(struct VideoMemory *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VideoMemory_Memory.offset), pGpu); +} + +static NV_STATUS __nvoc_thunk_RmResource_vidmemControl_Prologue(struct VideoMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_vidmemIsReady(struct VideoMemory *pMemory, NvBool bCopyConstructorContext) { + return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VideoMemory_Memory.offset), bCopyConstructorContext); } static void __nvoc_thunk_RsResource_vidmemPreDestruct(struct VideoMemory *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_Memory_vidmemIsDuplicate(struct VideoMemory *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VideoMemory_Memory.offset), hMemory, pDuplicate); +} + static NV_STATUS __nvoc_thunk_RsResource_vidmemUnmapFrom(struct VideoMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RsResource.offset), pParams); } @@ -251,14 +259,18 @@ static void __nvoc_init_funcTable_VideoMemory_1(VideoMemory *pThis) { pThis->__vidmemMapTo__ = &__nvoc_thunk_RsResource_vidmemMapTo; - pThis->__vidmemControl_Prologue__ = &__nvoc_thunk_RmResource_vidmemControl_Prologue; - pThis->__vidmemCanCopy__ = &__nvoc_thunk_StandardMemory_vidmemCanCopy; + pThis->__vidmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_vidmemIsGpuMapAllowed; + + pThis->__vidmemControl_Prologue__ = &__nvoc_thunk_RmResource_vidmemControl_Prologue; + pThis->__vidmemIsReady__ = &__nvoc_thunk_Memory_vidmemIsReady; pThis->__vidmemPreDestruct__ = &__nvoc_thunk_RsResource_vidmemPreDestruct; + pThis->__vidmemIsDuplicate__ = &__nvoc_thunk_Memory_vidmemIsDuplicate; + pThis->__vidmemUnmapFrom__ = &__nvoc_thunk_RsResource_vidmemUnmapFrom; pThis->__vidmemControl_Epilogue__ = &__nvoc_thunk_RmResource_vidmemControl_Epilogue; diff --git a/src/nvidia/generated/g_video_mem_nvoc.h b/src/nvidia/generated/g_video_mem_nvoc.h index d07c59529..8ed8e8474 100644 --- a/src/nvidia/generated/g_video_mem_nvoc.h +++ b/src/nvidia/generated/g_video_mem_nvoc.h @@ -66,10 +66,12 @@ struct VideoMemory { void (*__vidmemAddAdditionalDependants__)(struct RsClient *, struct VideoMemory *, RsResourceRef *); NvU32 (*__vidmemGetRefCount__)(struct VideoMemory *); NV_STATUS (*__vidmemMapTo__)(struct VideoMemory *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__vidmemControl_Prologue__)(struct VideoMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__vidmemCanCopy__)(struct VideoMemory *); - NV_STATUS (*__vidmemIsReady__)(struct VideoMemory *); + NvBool (*__vidmemIsGpuMapAllowed__)(struct VideoMemory *, struct OBJGPU *); + NV_STATUS (*__vidmemControl_Prologue__)(struct VideoMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__vidmemIsReady__)(struct VideoMemory *, NvBool); void (*__vidmemPreDestruct__)(struct VideoMemory *); + NV_STATUS (*__vidmemIsDuplicate__)(struct VideoMemory *, NvHandle, NvBool *); NV_STATUS (*__vidmemUnmapFrom__)(struct VideoMemory *, RS_RES_UNMAP_FROM_PARAMS *); void (*__vidmemControl_Epilogue__)(struct VideoMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vidmemControlLookup__)(struct VideoMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); @@ -117,10 +119,12 @@ NV_STATUS __nvoc_objCreate_VideoMemory(VideoMemory**, Dynamic*, NvU32, CALL_CONT #define vidmemAddAdditionalDependants(pClient, pResource, pReference) vidmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define vidmemGetRefCount(pResource) vidmemGetRefCount_DISPATCH(pResource) #define vidmemMapTo(pResource, pParams) vidmemMapTo_DISPATCH(pResource, pParams) -#define vidmemControl_Prologue(pResource, pCallContext, pParams) vidmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define vidmemCanCopy(pStandardMemory) vidmemCanCopy_DISPATCH(pStandardMemory) -#define vidmemIsReady(pMemory) vidmemIsReady_DISPATCH(pMemory) +#define vidmemIsGpuMapAllowed(pMemory, pGpu) vidmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define vidmemControl_Prologue(pResource, pCallContext, pParams) vidmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define vidmemIsReady(pMemory, bCopyConstructorContext) vidmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define vidmemPreDestruct(pResource) vidmemPreDestruct_DISPATCH(pResource) +#define vidmemIsDuplicate(pMemory, hMemory, pDuplicate) vidmemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) #define vidmemUnmapFrom(pResource, pParams) vidmemUnmapFrom_DISPATCH(pResource, pParams) #define vidmemControl_Epilogue(pResource, pCallContext, pParams) vidmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define vidmemControlLookup(pResource, pParams, ppEntry) vidmemControlLookup_DISPATCH(pResource, pParams, ppEntry) @@ -176,22 +180,30 @@ static inline NV_STATUS vidmemMapTo_DISPATCH(struct VideoMemory *pResource, RS_R return pResource->__vidmemMapTo__(pResource, pParams); } -static inline NV_STATUS vidmemControl_Prologue_DISPATCH(struct VideoMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__vidmemControl_Prologue__(pResource, pCallContext, pParams); -} - static inline NvBool vidmemCanCopy_DISPATCH(struct VideoMemory *pStandardMemory) { return pStandardMemory->__vidmemCanCopy__(pStandardMemory); } -static inline NV_STATUS vidmemIsReady_DISPATCH(struct VideoMemory *pMemory) { - return pMemory->__vidmemIsReady__(pMemory); +static inline NvBool vidmemIsGpuMapAllowed_DISPATCH(struct VideoMemory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__vidmemIsGpuMapAllowed__(pMemory, pGpu); +} + +static inline NV_STATUS vidmemControl_Prologue_DISPATCH(struct VideoMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__vidmemControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS vidmemIsReady_DISPATCH(struct VideoMemory *pMemory, NvBool bCopyConstructorContext) { + return pMemory->__vidmemIsReady__(pMemory, bCopyConstructorContext); } static inline void vidmemPreDestruct_DISPATCH(struct VideoMemory *pResource) { pResource->__vidmemPreDestruct__(pResource); } +static inline NV_STATUS vidmemIsDuplicate_DISPATCH(struct VideoMemory *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return pMemory->__vidmemIsDuplicate__(pMemory, hMemory, pDuplicate); +} + static inline NV_STATUS vidmemUnmapFrom_DISPATCH(struct VideoMemory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return pResource->__vidmemUnmapFrom__(pResource, pParams); } @@ -213,10 +225,13 @@ static inline NvBool vidmemAccessCallback_DISPATCH(struct VideoMemory *pResource } NV_STATUS vidmemConstruct_IMPL(struct VideoMemory *arg_pVideoMemory, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_vidmemConstruct(arg_pVideoMemory, arg_pCallContext, arg_pParams) vidmemConstruct_IMPL(arg_pVideoMemory, arg_pCallContext, arg_pParams) void vidmemDestruct_IMPL(struct VideoMemory *pVideoMemory); + #define __nvoc_vidmemDestruct(pVideoMemory) vidmemDestruct_IMPL(pVideoMemory) struct Heap *vidmemGetHeap_IMPL(struct OBJGPU *pGpu, NvHandle hClient, NvBool bSubheap); + #define vidmemGetHeap(pGpu, hClient, bSubheap) vidmemGetHeap_IMPL(pGpu, hClient, bSubheap) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.h b/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.h new file mode 100644 index 000000000..946c03f26 --- /dev/null +++ b/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.h @@ -0,0 +1,345 @@ +#ifndef _G_VIDMEM_ACCESS_BIT_BUFFER_NVOC_H_ +#define _G_VIDMEM_ACCESS_BIT_BUFFER_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_vidmem_access_bit_buffer_nvoc.h" + +#ifndef VIDMEM_ACCESS_BIT_BUFFER_H +#define VIDMEM_ACCESS_BIT_BUFFER_H + +#include "gpu/gpu.h" +#include "gpu/gpu_resource.h" +#include "rmapi/event.h" +#include "ctrl/ctrlc763.h" + +typedef struct +{ + NvU8 entrySize; + NvU8 entryGranularity; + NvU8 trackMode; + NvU8 disableMode; + NvBool bEnabled; + NvBool bFloorswept; +}NV_VIDMEM_ACCESS_BIT_BUFFER_HW_ATTR; + + +#define NUM_MMU_TYPES 0x3 + +// This is used to make the conversion from the granularity enum to byte size more readable +#define NV_VAB_GRAN_SIZE(gran) NVBIT64(16 + (NvU64)(gran)) + +#define NV_VAB_SIZE_TO_BIT_COUNT(vabSize) ((vabSize)*8) +#define NV_VAB_SIZE_TO_NVU64_COUNT(vabSize) ((vabSize)/8) + + +/* + * Maximum length of access bit mask and access bit buffer in NvU64s. Legacy define used in the old interface. To be deleted once MODS transitions to V2. + */ +#define AMPERE_VIDMEM_BIT_BUF_SIZE 512 +#define NV_VAB_BUFFER_MAX_NVU64_COUNT NV_VAB_SIZE_TO_NVU64_COUNT(AMPERE_VIDMEM_BIT_BUF_SIZE) + +/* + * These values are returned from gmmuVidmemAccessBitBufferVersion_HAL to indicate + * the type of VAB interface supported on the current platform. + */ +#define NV_VAB_VERSION_NONE 0 +#define NV_VAB_VERSION_SINGLE_RANGE 1 +#define NV_VAB_VERSION_MULTI_RANGE 2 + +/*! + * RM internal class representing VIDMEM_ACCESS_BIT_BUFFER + */ +#ifdef NVOC_VIDMEM_ACCESS_BIT_BUFFER_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct VidmemAccessBitBuffer { + const struct NVOC_RTTI *__nvoc_rtti; + struct GpuResource __nvoc_base_GpuResource; + struct Notifier __nvoc_base_Notifier; + struct Object *__nvoc_pbase_Object; + struct RsResource *__nvoc_pbase_RsResource; + struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; + struct RmResource *__nvoc_pbase_RmResource; + struct GpuResource *__nvoc_pbase_GpuResource; + struct INotifier *__nvoc_pbase_INotifier; + struct Notifier *__nvoc_pbase_Notifier; + struct VidmemAccessBitBuffer *__nvoc_pbase_VidmemAccessBitBuffer; + NV_STATUS (*__vidmemAccessBitBufCopyConstruct__)(struct VidmemAccessBitBuffer *, CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); + NV_STATUS (*__vidmemAccessBitBufCtrlCmdVidmemAccessBitDump__)(struct VidmemAccessBitBuffer *, NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DUMP_PARAMS *); + NvBool (*__vidmemAccessBitBufShareCallback__)(struct VidmemAccessBitBuffer *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__vidmemAccessBitBufMapTo__)(struct VidmemAccessBitBuffer *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__vidmemAccessBitBufGetOrAllocNotifShare__)(struct VidmemAccessBitBuffer *, NvHandle, NvHandle, struct NotifShare **); + NV_STATUS (*__vidmemAccessBitBufCheckMemInterUnmap__)(struct VidmemAccessBitBuffer *, NvBool); + NV_STATUS (*__vidmemAccessBitBufGetMapAddrSpace__)(struct VidmemAccessBitBuffer *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + void (*__vidmemAccessBitBufSetNotificationShare__)(struct VidmemAccessBitBuffer *, struct NotifShare *); + NvU32 (*__vidmemAccessBitBufGetRefCount__)(struct VidmemAccessBitBuffer *); + void (*__vidmemAccessBitBufAddAdditionalDependants__)(struct RsClient *, struct VidmemAccessBitBuffer *, RsResourceRef *); + NV_STATUS (*__vidmemAccessBitBufControl_Prologue__)(struct VidmemAccessBitBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__vidmemAccessBitBufGetRegBaseOffsetAndSize__)(struct VidmemAccessBitBuffer *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__vidmemAccessBitBufInternalControlForward__)(struct VidmemAccessBitBuffer *, NvU32, void *, NvU32); + NV_STATUS (*__vidmemAccessBitBufUnmapFrom__)(struct VidmemAccessBitBuffer *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__vidmemAccessBitBufControl_Epilogue__)(struct VidmemAccessBitBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__vidmemAccessBitBufControlLookup__)(struct VidmemAccessBitBuffer *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__vidmemAccessBitBufGetInternalObjectHandle__)(struct VidmemAccessBitBuffer *); + NV_STATUS (*__vidmemAccessBitBufControl__)(struct VidmemAccessBitBuffer *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__vidmemAccessBitBufUnmap__)(struct VidmemAccessBitBuffer *, CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__vidmemAccessBitBufGetMemInterMapParams__)(struct VidmemAccessBitBuffer *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__vidmemAccessBitBufGetMemoryMappingDescriptor__)(struct VidmemAccessBitBuffer *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__vidmemAccessBitBufControlFilter__)(struct VidmemAccessBitBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__vidmemAccessBitBufUnregisterEvent__)(struct VidmemAccessBitBuffer *, NvHandle, NvHandle, NvHandle, NvHandle); + NvBool (*__vidmemAccessBitBufCanCopy__)(struct VidmemAccessBitBuffer *); + void (*__vidmemAccessBitBufPreDestruct__)(struct VidmemAccessBitBuffer *); + NV_STATUS (*__vidmemAccessBitBufIsDuplicate__)(struct VidmemAccessBitBuffer *, NvHandle, NvBool *); + PEVENTNOTIFICATION *(*__vidmemAccessBitBufGetNotificationListPtr__)(struct VidmemAccessBitBuffer *); + struct NotifShare *(*__vidmemAccessBitBufGetNotificationShare__)(struct VidmemAccessBitBuffer *); + NV_STATUS (*__vidmemAccessBitBufMap__)(struct VidmemAccessBitBuffer *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); + NvBool (*__vidmemAccessBitBufAccessCallback__)(struct VidmemAccessBitBuffer *, struct RsClient *, void *, RsAccessRight); +}; + +#ifndef __NVOC_CLASS_VidmemAccessBitBuffer_TYPEDEF__ +#define __NVOC_CLASS_VidmemAccessBitBuffer_TYPEDEF__ +typedef struct VidmemAccessBitBuffer VidmemAccessBitBuffer; +#endif /* __NVOC_CLASS_VidmemAccessBitBuffer_TYPEDEF__ */ + +#ifndef __nvoc_class_id_VidmemAccessBitBuffer +#define __nvoc_class_id_VidmemAccessBitBuffer 0xebb6da +#endif /* __nvoc_class_id_VidmemAccessBitBuffer */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_VidmemAccessBitBuffer; + +#define __staticCast_VidmemAccessBitBuffer(pThis) \ + ((pThis)->__nvoc_pbase_VidmemAccessBitBuffer) + +#ifdef __nvoc_vidmem_access_bit_buffer_h_disabled +#define __dynamicCast_VidmemAccessBitBuffer(pThis) ((VidmemAccessBitBuffer*)NULL) +#else //__nvoc_vidmem_access_bit_buffer_h_disabled +#define __dynamicCast_VidmemAccessBitBuffer(pThis) \ + ((VidmemAccessBitBuffer*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(VidmemAccessBitBuffer))) +#endif //__nvoc_vidmem_access_bit_buffer_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_VidmemAccessBitBuffer(VidmemAccessBitBuffer**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_VidmemAccessBitBuffer(VidmemAccessBitBuffer**, Dynamic*, NvU32, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +#define __objCreate_VidmemAccessBitBuffer(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ + __nvoc_objCreate_VidmemAccessBitBuffer((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) + +#define vidmemAccessBitBufCopyConstruct(pVidmemAccessBitBuffer, pCallContext, pParams) vidmemAccessBitBufCopyConstruct_DISPATCH(pVidmemAccessBitBuffer, pCallContext, pParams) +#define vidmemAccessBitBufCopyConstruct_HAL(pVidmemAccessBitBuffer, pCallContext, pParams) vidmemAccessBitBufCopyConstruct_DISPATCH(pVidmemAccessBitBuffer, pCallContext, pParams) +#define vidmemAccessBitBufCtrlCmdVidmemAccessBitDump(pVidmemAccessBitBuffer, pParams) vidmemAccessBitBufCtrlCmdVidmemAccessBitDump_DISPATCH(pVidmemAccessBitBuffer, pParams) +#define vidmemAccessBitBufShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) vidmemAccessBitBufShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define vidmemAccessBitBufMapTo(pResource, pParams) vidmemAccessBitBufMapTo_DISPATCH(pResource, pParams) +#define vidmemAccessBitBufGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) vidmemAccessBitBufGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +#define vidmemAccessBitBufCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) vidmemAccessBitBufCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define vidmemAccessBitBufGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) vidmemAccessBitBufGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define vidmemAccessBitBufSetNotificationShare(pNotifier, pNotifShare) vidmemAccessBitBufSetNotificationShare_DISPATCH(pNotifier, pNotifShare) +#define vidmemAccessBitBufGetRefCount(pResource) vidmemAccessBitBufGetRefCount_DISPATCH(pResource) +#define vidmemAccessBitBufAddAdditionalDependants(pClient, pResource, pReference) vidmemAccessBitBufAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define vidmemAccessBitBufControl_Prologue(pResource, pCallContext, pParams) vidmemAccessBitBufControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define vidmemAccessBitBufGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) vidmemAccessBitBufGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define vidmemAccessBitBufInternalControlForward(pGpuResource, command, pParams, size) vidmemAccessBitBufInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define vidmemAccessBitBufUnmapFrom(pResource, pParams) vidmemAccessBitBufUnmapFrom_DISPATCH(pResource, pParams) +#define vidmemAccessBitBufControl_Epilogue(pResource, pCallContext, pParams) vidmemAccessBitBufControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define vidmemAccessBitBufControlLookup(pResource, pParams, ppEntry) vidmemAccessBitBufControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define vidmemAccessBitBufGetInternalObjectHandle(pGpuResource) vidmemAccessBitBufGetInternalObjectHandle_DISPATCH(pGpuResource) +#define vidmemAccessBitBufControl(pGpuResource, pCallContext, pParams) vidmemAccessBitBufControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define vidmemAccessBitBufUnmap(pGpuResource, pCallContext, pCpuMapping) vidmemAccessBitBufUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define vidmemAccessBitBufGetMemInterMapParams(pRmResource, pParams) vidmemAccessBitBufGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define vidmemAccessBitBufGetMemoryMappingDescriptor(pRmResource, ppMemDesc) vidmemAccessBitBufGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define vidmemAccessBitBufControlFilter(pResource, pCallContext, pParams) vidmemAccessBitBufControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define vidmemAccessBitBufUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) vidmemAccessBitBufUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define vidmemAccessBitBufCanCopy(pResource) vidmemAccessBitBufCanCopy_DISPATCH(pResource) +#define vidmemAccessBitBufPreDestruct(pResource) vidmemAccessBitBufPreDestruct_DISPATCH(pResource) +#define vidmemAccessBitBufIsDuplicate(pResource, hMemory, pDuplicate) vidmemAccessBitBufIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define vidmemAccessBitBufGetNotificationListPtr(pNotifier) vidmemAccessBitBufGetNotificationListPtr_DISPATCH(pNotifier) +#define vidmemAccessBitBufGetNotificationShare(pNotifier) vidmemAccessBitBufGetNotificationShare_DISPATCH(pNotifier) +#define vidmemAccessBitBufMap(pGpuResource, pCallContext, pParams, pCpuMapping) vidmemAccessBitBufMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) +#define vidmemAccessBitBufAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) vidmemAccessBitBufAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +NV_STATUS vidmemAccessBitBufConstructHelper_KERNEL(struct VidmemAccessBitBuffer *pVidmem, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); + + +#ifdef __nvoc_vidmem_access_bit_buffer_h_disabled +static inline NV_STATUS vidmemAccessBitBufConstructHelper(struct VidmemAccessBitBuffer *pVidmem, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { + NV_ASSERT_FAILED_PRECOMP("VidmemAccessBitBuffer was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_vidmem_access_bit_buffer_h_disabled +#define vidmemAccessBitBufConstructHelper(pVidmem, pCallContext, pParams) vidmemAccessBitBufConstructHelper_KERNEL(pVidmem, pCallContext, pParams) +#endif //__nvoc_vidmem_access_bit_buffer_h_disabled + +#define vidmemAccessBitBufConstructHelper_HAL(pVidmem, pCallContext, pParams) vidmemAccessBitBufConstructHelper(pVidmem, pCallContext, pParams) + +static inline void vidmemAccessBitBufDestruct_b3696a(struct VidmemAccessBitBuffer *pVidmemAccessBitBuffer) { + return; +} + + +#define __nvoc_vidmemAccessBitBufDestruct(pVidmemAccessBitBuffer) vidmemAccessBitBufDestruct_b3696a(pVidmemAccessBitBuffer) +static inline NV_STATUS vidmemAccessBitBufCopyConstruct_56cd7a(struct VidmemAccessBitBuffer *pVidmemAccessBitBuffer, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { + return NV_OK; +} + +static inline NV_STATUS vidmemAccessBitBufCopyConstruct_DISPATCH(struct VidmemAccessBitBuffer *pVidmemAccessBitBuffer, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { + return pVidmemAccessBitBuffer->__vidmemAccessBitBufCopyConstruct__(pVidmemAccessBitBuffer, pCallContext, pParams); +} + +NV_STATUS vidmemAccessBitBufCtrlCmdVidmemAccessBitDump_IMPL(struct VidmemAccessBitBuffer *pVidmemAccessBitBuffer, NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DUMP_PARAMS *pParams); + +static inline NV_STATUS vidmemAccessBitBufCtrlCmdVidmemAccessBitDump_DISPATCH(struct VidmemAccessBitBuffer *pVidmemAccessBitBuffer, NVC763_CTRL_VIDMEM_ACCESS_BIT_BUFFER_DUMP_PARAMS *pParams) { + return pVidmemAccessBitBuffer->__vidmemAccessBitBufCtrlCmdVidmemAccessBitDump__(pVidmemAccessBitBuffer, pParams); +} + +static inline NvBool vidmemAccessBitBufShareCallback_DISPATCH(struct VidmemAccessBitBuffer *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pGpuResource->__vidmemAccessBitBufShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS vidmemAccessBitBufMapTo_DISPATCH(struct VidmemAccessBitBuffer *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__vidmemAccessBitBufMapTo__(pResource, pParams); +} + +static inline NV_STATUS vidmemAccessBitBufGetOrAllocNotifShare_DISPATCH(struct VidmemAccessBitBuffer *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { + return pNotifier->__vidmemAccessBitBufGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); +} + +static inline NV_STATUS vidmemAccessBitBufCheckMemInterUnmap_DISPATCH(struct VidmemAccessBitBuffer *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__vidmemAccessBitBufCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS vidmemAccessBitBufGetMapAddrSpace_DISPATCH(struct VidmemAccessBitBuffer *pGpuResource, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__vidmemAccessBitBufGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline void vidmemAccessBitBufSetNotificationShare_DISPATCH(struct VidmemAccessBitBuffer *pNotifier, struct NotifShare *pNotifShare) { + pNotifier->__vidmemAccessBitBufSetNotificationShare__(pNotifier, pNotifShare); +} + +static inline NvU32 vidmemAccessBitBufGetRefCount_DISPATCH(struct VidmemAccessBitBuffer *pResource) { + return pResource->__vidmemAccessBitBufGetRefCount__(pResource); +} + +static inline void vidmemAccessBitBufAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct VidmemAccessBitBuffer *pResource, RsResourceRef *pReference) { + pResource->__vidmemAccessBitBufAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS vidmemAccessBitBufControl_Prologue_DISPATCH(struct VidmemAccessBitBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__vidmemAccessBitBufControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS vidmemAccessBitBufGetRegBaseOffsetAndSize_DISPATCH(struct VidmemAccessBitBuffer *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__vidmemAccessBitBufGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NV_STATUS vidmemAccessBitBufInternalControlForward_DISPATCH(struct VidmemAccessBitBuffer *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__vidmemAccessBitBufInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS vidmemAccessBitBufUnmapFrom_DISPATCH(struct VidmemAccessBitBuffer *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__vidmemAccessBitBufUnmapFrom__(pResource, pParams); +} + +static inline void vidmemAccessBitBufControl_Epilogue_DISPATCH(struct VidmemAccessBitBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__vidmemAccessBitBufControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS vidmemAccessBitBufControlLookup_DISPATCH(struct VidmemAccessBitBuffer *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__vidmemAccessBitBufControlLookup__(pResource, pParams, ppEntry); +} + +static inline NvHandle vidmemAccessBitBufGetInternalObjectHandle_DISPATCH(struct VidmemAccessBitBuffer *pGpuResource) { + return pGpuResource->__vidmemAccessBitBufGetInternalObjectHandle__(pGpuResource); +} + +static inline NV_STATUS vidmemAccessBitBufControl_DISPATCH(struct VidmemAccessBitBuffer *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__vidmemAccessBitBufControl__(pGpuResource, pCallContext, pParams); +} + +static inline NV_STATUS vidmemAccessBitBufUnmap_DISPATCH(struct VidmemAccessBitBuffer *pGpuResource, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pGpuResource->__vidmemAccessBitBufUnmap__(pGpuResource, pCallContext, pCpuMapping); +} + +static inline NV_STATUS vidmemAccessBitBufGetMemInterMapParams_DISPATCH(struct VidmemAccessBitBuffer *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__vidmemAccessBitBufGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS vidmemAccessBitBufGetMemoryMappingDescriptor_DISPATCH(struct VidmemAccessBitBuffer *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__vidmemAccessBitBufGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +} + +static inline NV_STATUS vidmemAccessBitBufControlFilter_DISPATCH(struct VidmemAccessBitBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__vidmemAccessBitBufControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS vidmemAccessBitBufUnregisterEvent_DISPATCH(struct VidmemAccessBitBuffer *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { + return pNotifier->__vidmemAccessBitBufUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); +} + +static inline NvBool vidmemAccessBitBufCanCopy_DISPATCH(struct VidmemAccessBitBuffer *pResource) { + return pResource->__vidmemAccessBitBufCanCopy__(pResource); +} + +static inline void vidmemAccessBitBufPreDestruct_DISPATCH(struct VidmemAccessBitBuffer *pResource) { + pResource->__vidmemAccessBitBufPreDestruct__(pResource); +} + +static inline NV_STATUS vidmemAccessBitBufIsDuplicate_DISPATCH(struct VidmemAccessBitBuffer *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__vidmemAccessBitBufIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline PEVENTNOTIFICATION *vidmemAccessBitBufGetNotificationListPtr_DISPATCH(struct VidmemAccessBitBuffer *pNotifier) { + return pNotifier->__vidmemAccessBitBufGetNotificationListPtr__(pNotifier); +} + +static inline struct NotifShare *vidmemAccessBitBufGetNotificationShare_DISPATCH(struct VidmemAccessBitBuffer *pNotifier) { + return pNotifier->__vidmemAccessBitBufGetNotificationShare__(pNotifier); +} + +static inline NV_STATUS vidmemAccessBitBufMap_DISPATCH(struct VidmemAccessBitBuffer *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { + return pGpuResource->__vidmemAccessBitBufMap__(pGpuResource, pCallContext, pParams, pCpuMapping); +} + +static inline NvBool vidmemAccessBitBufAccessCallback_DISPATCH(struct VidmemAccessBitBuffer *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return pResource->__vidmemAccessBitBufAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); +} + +static inline NV_STATUS __nvoc_vidmemAccessBitBufConstruct(struct VidmemAccessBitBuffer *arg_pVidmemAccessBitBuffer, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams) { + return vidmemAccessBitBufConstructHelper(arg_pVidmemAccessBitBuffer, arg_pCallContext, arg_pParams); +} + +#undef PRIVATE_FIELD + + +#endif // VIDMEM_ACCESS_BIT_BUFFER_H + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _G_VIDMEM_ACCESS_BIT_BUFFER_NVOC_H_ diff --git a/src/nvidia/generated/g_virt_mem_allocator_nvoc.c b/src/nvidia/generated/g_virt_mem_allocator_nvoc.c index bed57b17e..4064f00a1 100644 --- a/src/nvidia/generated/g_virt_mem_allocator_nvoc.c +++ b/src/nvidia/generated/g_virt_mem_allocator_nvoc.c @@ -172,53 +172,31 @@ void __nvoc_init_dataField_VirtMemAllocator(VirtMemAllocator *pThis, RmHalspecOw PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // NVOC Property Hal field -- PDB_PROP_DMA_ENFORCE_32BIT_POINTER - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_DMA_ENFORCE_32BIT_POINTER, ((NvBool)(0 == 0))); } - // default - else - { - pThis->setProperty(pThis, PDB_PROP_DMA_ENFORCE_32BIT_POINTER, ((NvBool)(0 != 0))); - } // NVOC Property Hal field -- PDB_PROP_DMA_SHADER_ACCESS_SUPPORTED - if (0) - { - } // default - else { pThis->setProperty(pThis, PDB_PROP_DMA_SHADER_ACCESS_SUPPORTED, ((NvBool)(0 != 0))); } // NVOC Property Hal field -- PDB_PROP_DMA_IS_SUPPORTED_SPARSE_VIRTUAL - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->setProperty(pThis, PDB_PROP_DMA_IS_SUPPORTED_SPARSE_VIRTUAL, ((NvBool)(0 == 0))); } - // default - else - { - pThis->setProperty(pThis, PDB_PROP_DMA_IS_SUPPORTED_SPARSE_VIRTUAL, ((NvBool)(0 != 0))); - } // NVOC Property Hal field -- PDB_PROP_DMA_ENABLE_FULL_COMP_TAG_LINE - if (0) - { - } // default - else { pThis->setProperty(pThis, PDB_PROP_DMA_ENABLE_FULL_COMP_TAG_LINE, ((NvBool)(0 != 0))); } // NVOC Property Hal field -- PDB_PROP_DMA_MULTIPLE_VASPACES_SUPPORTED - if (0) - { - } // default - else { pThis->setProperty(pThis, PDB_PROP_DMA_MULTIPLE_VASPACES_SUPPORTED, ((NvBool)(0 == 0))); } @@ -255,7 +233,7 @@ static void __nvoc_init_funcTable_VirtMemAllocator_1(VirtMemAllocator *pThis, Rm pThis->__dmaStateInitLocked__ = &dmaStateInitLocked_IMPL; // Hal function -- dmaAllocBar1P2PMapping - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__dmaAllocBar1P2PMapping__ = &dmaAllocBar1P2PMapping_GH100; } @@ -266,7 +244,7 @@ static void __nvoc_init_funcTable_VirtMemAllocator_1(VirtMemAllocator *pThis, Rm } // Hal function -- dmaFreeBar1P2PMapping - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x08000000UL) )) /* ChipHal: GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { pThis->__dmaFreeBar1P2PMapping__ = &dmaFreeBar1P2PMapping_GH100; } @@ -277,13 +255,10 @@ static void __nvoc_init_funcTable_VirtMemAllocator_1(VirtMemAllocator *pThis, Rm } // Hal function -- dmaStatePostLoad - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0870ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { pThis->__dmaStatePostLoad__ = &dmaStatePostLoad_GM107; } - else if (0) - { - } pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_VirtMemAllocator_engstateConstructEngine; diff --git a/src/nvidia/generated/g_virt_mem_allocator_nvoc.h b/src/nvidia/generated/g_virt_mem_allocator_nvoc.h index 5613cc94d..c607e4e06 100644 --- a/src/nvidia/generated/g_virt_mem_allocator_nvoc.h +++ b/src/nvidia/generated/g_virt_mem_allocator_nvoc.h @@ -129,6 +129,7 @@ struct VirtMemAllocator { NvBool PDB_PROP_DMA_ENABLE_FULL_COMP_TAG_LINE; NvBool PDB_PROP_DMA_RESTRICT_VA_RANGE; NvBool PDB_PROP_DMA_MULTIPLE_VASPACES_SUPPORTED; + NvBool bMemoryMapperApiEnabled; NvU32 gpuGartCaps; NvU32 increaseRsvdPages; struct ENG_INFO_LINK_NODE *infoList; @@ -207,6 +208,7 @@ NV_STATUS __nvoc_objCreate_VirtMemAllocator(VirtMemAllocator**, Dynamic*, NvU32) #define dmaIsPresent(pGpu, pEngstate) dmaIsPresent_DISPATCH(pGpu, pEngstate) NV_STATUS dmaInit_GM107(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma); + #ifdef __nvoc_virt_mem_allocator_h_disabled static inline NV_STATUS dmaInit(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma) { NV_ASSERT_FAILED_PRECOMP("VirtMemAllocator was disabled!"); @@ -220,6 +222,11 @@ static inline NV_STATUS dmaInit(struct OBJGPU *pGpu, struct VirtMemAllocator *pD NV_STATUS dmaConstructHal_VGPUSTUB(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma); +static inline NV_STATUS dmaConstructHal_56cd7a(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma) { + return NV_OK; +} + + #ifdef __nvoc_virt_mem_allocator_h_disabled static inline NV_STATUS dmaConstructHal(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma) { NV_ASSERT_FAILED_PRECOMP("VirtMemAllocator was disabled!"); @@ -233,9 +240,11 @@ static inline NV_STATUS dmaConstructHal(struct OBJGPU *pGpu, struct VirtMemAlloc void dmaDestruct_GM107(struct VirtMemAllocator *pDma); + #define __nvoc_dmaDestruct(pDma) dmaDestruct_GM107(pDma) NV_STATUS dmaInitGart_GM107(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma); + #ifdef __nvoc_virt_mem_allocator_h_disabled static inline NV_STATUS dmaInitGart(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma) { NV_ASSERT_FAILED_PRECOMP("VirtMemAllocator was disabled!"); @@ -249,6 +258,7 @@ static inline NV_STATUS dmaInitGart(struct OBJGPU *pGpu, struct VirtMemAllocator NV_STATUS dmaAllocMapping_GM107(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, struct OBJVASPACE *arg0, MEMORY_DESCRIPTOR *arg1, NvU64 *arg2, NvU32 arg3, CLI_DMA_ALLOC_MAP_INFO *arg4, NvU32 arg5); + #ifdef __nvoc_virt_mem_allocator_h_disabled static inline NV_STATUS dmaAllocMapping(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, struct OBJVASPACE *arg0, MEMORY_DESCRIPTOR *arg1, NvU64 *arg2, NvU32 arg3, CLI_DMA_ALLOC_MAP_INFO *arg4, NvU32 arg5) { NV_ASSERT_FAILED_PRECOMP("VirtMemAllocator was disabled!"); @@ -262,6 +272,7 @@ static inline NV_STATUS dmaAllocMapping(struct OBJGPU *pGpu, struct VirtMemAlloc NV_STATUS dmaFreeMapping_GM107(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, struct OBJVASPACE *arg0, NvU64 arg1, MEMORY_DESCRIPTOR *arg2, NvU32 arg3, CLI_DMA_ALLOC_MAP_INFO *arg4); + #ifdef __nvoc_virt_mem_allocator_h_disabled static inline NV_STATUS dmaFreeMapping(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, struct OBJVASPACE *arg0, NvU64 arg1, MEMORY_DESCRIPTOR *arg2, NvU32 arg3, CLI_DMA_ALLOC_MAP_INFO *arg4) { NV_ASSERT_FAILED_PRECOMP("VirtMemAllocator was disabled!"); @@ -273,21 +284,23 @@ static inline NV_STATUS dmaFreeMapping(struct OBJGPU *pGpu, struct VirtMemAlloca #define dmaFreeMapping_HAL(pGpu, pDma, arg0, arg1, arg2, arg3, arg4) dmaFreeMapping(pGpu, pDma, arg0, arg1, arg2, arg3, arg4) -NV_STATUS dmaUpdateVASpace_GF100(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, struct OBJVASPACE *pVAS, MEMORY_DESCRIPTOR *pMemDesc, NvU8 *tgtPteMem, NvU64 vAddr, NvU64 vAddrLimit, NvU32 flags, DMA_PAGE_ARRAY *pPageArray, NvU32 overmapPteMod, COMPR_INFO *pComprInfo, NvU64 surfaceOffset, NvU32 valid, NvU32 aperture, NvU32 peer, NvU64 fabricAddr, NvU32 deferInvalidate, NvBool bSparse); +NV_STATUS dmaUpdateVASpace_GF100(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, struct OBJVASPACE *pVAS, MEMORY_DESCRIPTOR *pMemDesc, NvU8 *tgtPteMem, NvU64 vAddr, NvU64 vAddrLimit, NvU32 flags, DMA_PAGE_ARRAY *pPageArray, NvU32 overmapPteMod, COMPR_INFO *pComprInfo, NvU64 surfaceOffset, NvU32 valid, NvU32 aperture, NvU32 peer, NvU64 fabricAddr, NvU32 deferInvalidate, NvBool bSparse, NvU32 pageSize); + #ifdef __nvoc_virt_mem_allocator_h_disabled -static inline NV_STATUS dmaUpdateVASpace(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, struct OBJVASPACE *pVAS, MEMORY_DESCRIPTOR *pMemDesc, NvU8 *tgtPteMem, NvU64 vAddr, NvU64 vAddrLimit, NvU32 flags, DMA_PAGE_ARRAY *pPageArray, NvU32 overmapPteMod, COMPR_INFO *pComprInfo, NvU64 surfaceOffset, NvU32 valid, NvU32 aperture, NvU32 peer, NvU64 fabricAddr, NvU32 deferInvalidate, NvBool bSparse) { +static inline NV_STATUS dmaUpdateVASpace(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, struct OBJVASPACE *pVAS, MEMORY_DESCRIPTOR *pMemDesc, NvU8 *tgtPteMem, NvU64 vAddr, NvU64 vAddrLimit, NvU32 flags, DMA_PAGE_ARRAY *pPageArray, NvU32 overmapPteMod, COMPR_INFO *pComprInfo, NvU64 surfaceOffset, NvU32 valid, NvU32 aperture, NvU32 peer, NvU64 fabricAddr, NvU32 deferInvalidate, NvBool bSparse, NvU32 pageSize) { NV_ASSERT_FAILED_PRECOMP("VirtMemAllocator was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_virt_mem_allocator_h_disabled -#define dmaUpdateVASpace(pGpu, pDma, pVAS, pMemDesc, tgtPteMem, vAddr, vAddrLimit, flags, pPageArray, overmapPteMod, pComprInfo, surfaceOffset, valid, aperture, peer, fabricAddr, deferInvalidate, bSparse) dmaUpdateVASpace_GF100(pGpu, pDma, pVAS, pMemDesc, tgtPteMem, vAddr, vAddrLimit, flags, pPageArray, overmapPteMod, pComprInfo, surfaceOffset, valid, aperture, peer, fabricAddr, deferInvalidate, bSparse) +#define dmaUpdateVASpace(pGpu, pDma, pVAS, pMemDesc, tgtPteMem, vAddr, vAddrLimit, flags, pPageArray, overmapPteMod, pComprInfo, surfaceOffset, valid, aperture, peer, fabricAddr, deferInvalidate, bSparse, pageSize) dmaUpdateVASpace_GF100(pGpu, pDma, pVAS, pMemDesc, tgtPteMem, vAddr, vAddrLimit, flags, pPageArray, overmapPteMod, pComprInfo, surfaceOffset, valid, aperture, peer, fabricAddr, deferInvalidate, bSparse, pageSize) #endif //__nvoc_virt_mem_allocator_h_disabled -#define dmaUpdateVASpace_HAL(pGpu, pDma, pVAS, pMemDesc, tgtPteMem, vAddr, vAddrLimit, flags, pPageArray, overmapPteMod, pComprInfo, surfaceOffset, valid, aperture, peer, fabricAddr, deferInvalidate, bSparse) dmaUpdateVASpace(pGpu, pDma, pVAS, pMemDesc, tgtPteMem, vAddr, vAddrLimit, flags, pPageArray, overmapPteMod, pComprInfo, surfaceOffset, valid, aperture, peer, fabricAddr, deferInvalidate, bSparse) +#define dmaUpdateVASpace_HAL(pGpu, pDma, pVAS, pMemDesc, tgtPteMem, vAddr, vAddrLimit, flags, pPageArray, overmapPteMod, pComprInfo, surfaceOffset, valid, aperture, peer, fabricAddr, deferInvalidate, bSparse, pageSize) dmaUpdateVASpace(pGpu, pDma, pVAS, pMemDesc, tgtPteMem, vAddr, vAddrLimit, flags, pPageArray, overmapPteMod, pComprInfo, surfaceOffset, valid, aperture, peer, fabricAddr, deferInvalidate, bSparse, pageSize) NV_STATUS dmaXlateVAtoPAforChannel_GM107(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, struct KernelChannel *pKernelChannel, NvU64 vAddr, NvU64 *pAddr, NvU32 *memType); + #ifdef __nvoc_virt_mem_allocator_h_disabled static inline NV_STATUS dmaXlateVAtoPAforChannel(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, struct KernelChannel *pKernelChannel, NvU64 vAddr, NvU64 *pAddr, NvU32 *memType) { NV_ASSERT_FAILED_PRECOMP("VirtMemAllocator was disabled!"); @@ -301,6 +314,7 @@ static inline NV_STATUS dmaXlateVAtoPAforChannel(struct OBJGPU *pGpu, struct Vir NvU32 dmaGetPTESize_GM107(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma); + #ifdef __nvoc_virt_mem_allocator_h_disabled static inline NvU32 dmaGetPTESize(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma) { NV_ASSERT_FAILED_PRECOMP("VirtMemAllocator was disabled!"); @@ -314,6 +328,7 @@ static inline NvU32 dmaGetPTESize(struct OBJGPU *pGpu, struct VirtMemAllocator * NV_STATUS dmaMapBuffer_GM107(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, struct OBJVASPACE *pVAS, PMEMORY_DESCRIPTOR pMemDesc, NvU64 *pVaddr, NvU32 allocFlags, NvU32 mapFlags); + #ifdef __nvoc_virt_mem_allocator_h_disabled static inline NV_STATUS dmaMapBuffer(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, struct OBJVASPACE *pVAS, PMEMORY_DESCRIPTOR pMemDesc, NvU64 *pVaddr, NvU32 allocFlags, NvU32 mapFlags) { NV_ASSERT_FAILED_PRECOMP("VirtMemAllocator was disabled!"); @@ -327,6 +342,7 @@ static inline NV_STATUS dmaMapBuffer(struct OBJGPU *pGpu, struct VirtMemAllocato void dmaUnmapBuffer_GM107(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, struct OBJVASPACE *pVAS, NvU64 vaddr); + #ifdef __nvoc_virt_mem_allocator_h_disabled static inline void dmaUnmapBuffer(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, struct OBJVASPACE *pVAS, NvU64 vaddr) { NV_ASSERT_FAILED_PRECOMP("VirtMemAllocator was disabled!"); @@ -339,6 +355,7 @@ static inline void dmaUnmapBuffer(struct OBJGPU *pGpu, struct VirtMemAllocator * NvU64 dmaGetPfnFromPte_GP100(struct VirtMemAllocator *pDma, NvBool bSysMem, NvU64 pPteMem); + #ifdef __nvoc_virt_mem_allocator_h_disabled static inline NvU64 dmaGetPfnFromPte(struct VirtMemAllocator *pDma, NvBool bSysMem, NvU64 pPteMem) { NV_ASSERT_FAILED_PRECOMP("VirtMemAllocator was disabled!"); @@ -354,6 +371,7 @@ static inline struct OBJVASPACE *dmaGetPrivateVAS_fa6e19(struct VirtMemAllocator return ((void *)0); } + #ifdef __nvoc_virt_mem_allocator_h_disabled static inline struct OBJVASPACE *dmaGetPrivateVAS(struct VirtMemAllocator *pDma) { NV_ASSERT_FAILED_PRECOMP("VirtMemAllocator was disabled!"); @@ -399,10 +417,6 @@ static inline void dmaFreeBar1P2PMapping_DISPATCH(struct VirtMemAllocator *pDma, NV_STATUS dmaStatePostLoad_GM107(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, NvU32 arg0); -static inline NV_STATUS dmaStatePostLoad_56cd7a(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, NvU32 arg0) { - return NV_OK; -} - static inline NV_STATUS dmaStatePostLoad_DISPATCH(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, NvU32 arg0) { return pDma->__dmaStatePostLoad__(pGpu, pDma, arg0); } @@ -476,6 +490,7 @@ static inline NvBool dmaIsPresent_DISPATCH(POBJGPU pGpu, struct VirtMemAllocator } NV_STATUS dmaAllocMap_IMPL(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, struct OBJVASPACE *arg0, VirtualMemory *arg1, Memory *arg2, CLI_DMA_MAPPING_INFO *arg3); + #ifdef __nvoc_virt_mem_allocator_h_disabled static inline NV_STATUS dmaAllocMap(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, struct OBJVASPACE *arg0, VirtualMemory *arg1, Memory *arg2, CLI_DMA_MAPPING_INFO *arg3) { NV_ASSERT_FAILED_PRECOMP("VirtMemAllocator was disabled!"); @@ -486,6 +501,7 @@ static inline NV_STATUS dmaAllocMap(struct OBJGPU *pGpu, struct VirtMemAllocator #endif //__nvoc_virt_mem_allocator_h_disabled NV_STATUS dmaFreeMap_IMPL(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, struct OBJVASPACE *arg0, VirtualMemory *arg1, CLI_DMA_MAPPING_INFO *arg2, NvU32 flags); + #ifdef __nvoc_virt_mem_allocator_h_disabled static inline NV_STATUS dmaFreeMap(struct OBJGPU *pGpu, struct VirtMemAllocator *pDma, struct OBJVASPACE *arg0, VirtualMemory *arg1, CLI_DMA_MAPPING_INFO *arg2, NvU32 flags) { NV_ASSERT_FAILED_PRECOMP("VirtMemAllocator was disabled!"); @@ -495,16 +511,6 @@ static inline NV_STATUS dmaFreeMap(struct OBJGPU *pGpu, struct VirtMemAllocator #define dmaFreeMap(pGpu, pDma, arg0, arg1, arg2, flags) dmaFreeMap_IMPL(pGpu, pDma, arg0, arg1, arg2, flags) #endif //__nvoc_virt_mem_allocator_h_disabled -NvBool dmaUseCompTagLineUpperHalf_IMPL(struct VirtMemAllocator *pDma, NvU32 pteIndex, NvU32 pageSize); -#ifdef __nvoc_virt_mem_allocator_h_disabled -static inline NvBool dmaUseCompTagLineUpperHalf(struct VirtMemAllocator *pDma, NvU32 pteIndex, NvU32 pageSize) { - NV_ASSERT_FAILED_PRECOMP("VirtMemAllocator was disabled!"); - return NV_FALSE; -} -#else //__nvoc_virt_mem_allocator_h_disabled -#define dmaUseCompTagLineUpperHalf(pDma, pteIndex, pageSize) dmaUseCompTagLineUpperHalf_IMPL(pDma, pteIndex, pageSize) -#endif //__nvoc_virt_mem_allocator_h_disabled - #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_virt_mem_mgr_nvoc.h b/src/nvidia/generated/g_virt_mem_mgr_nvoc.h index 291303299..c7fa04262 100644 --- a/src/nvidia/generated/g_virt_mem_mgr_nvoc.h +++ b/src/nvidia/generated/g_virt_mem_mgr_nvoc.h @@ -94,6 +94,7 @@ NV_STATUS __nvoc_objCreate_OBJVMM(OBJVMM**, Dynamic*, NvU32); __nvoc_objCreate_OBJVMM((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) NV_STATUS vmmCreateVaspace_IMPL(struct OBJVMM *pVmm, NvU32 _class, NvU32 vaspaceId, NvU32 gpuMask, NvU64 vaStart, NvU64 vaLimit, NvU64 vaInternalStart, NvU64 vaInternalEnd, struct OBJVASPACE *pPteSpaceMap, NvU32 flags, struct OBJVASPACE **ppVAS); + #ifdef __nvoc_virt_mem_mgr_h_disabled static inline NV_STATUS vmmCreateVaspace(struct OBJVMM *pVmm, NvU32 _class, NvU32 vaspaceId, NvU32 gpuMask, NvU64 vaStart, NvU64 vaLimit, NvU64 vaInternalStart, NvU64 vaInternalEnd, struct OBJVASPACE *pPteSpaceMap, NvU32 flags, struct OBJVASPACE **ppVAS) { NV_ASSERT_FAILED_PRECOMP("OBJVMM was disabled!"); @@ -104,6 +105,7 @@ static inline NV_STATUS vmmCreateVaspace(struct OBJVMM *pVmm, NvU32 _class, NvU3 #endif //__nvoc_virt_mem_mgr_h_disabled void vmmDestroyVaspace_IMPL(struct OBJVMM *pVmm, struct OBJVASPACE *pVAS); + #ifdef __nvoc_virt_mem_mgr_h_disabled static inline void vmmDestroyVaspace(struct OBJVMM *pVmm, struct OBJVASPACE *pVAS) { NV_ASSERT_FAILED_PRECOMP("OBJVMM was disabled!"); @@ -113,6 +115,7 @@ static inline void vmmDestroyVaspace(struct OBJVMM *pVmm, struct OBJVASPACE *pVA #endif //__nvoc_virt_mem_mgr_h_disabled NV_STATUS vmmGetVaspaceFromId_IMPL(struct OBJVMM *pVmm, NvU32 vaspaceId, NvU32 classId, struct OBJVASPACE **ppVAS); + #ifdef __nvoc_virt_mem_mgr_h_disabled static inline NV_STATUS vmmGetVaspaceFromId(struct OBJVMM *pVmm, NvU32 vaspaceId, NvU32 classId, struct OBJVASPACE **ppVAS) { NV_ASSERT_FAILED_PRECOMP("OBJVMM was disabled!"); diff --git a/src/nvidia/generated/g_virt_mem_range_nvoc.c b/src/nvidia/generated/g_virt_mem_range_nvoc.c index a9734adba..bb47fc67d 100644 --- a/src/nvidia/generated/g_virt_mem_range_nvoc.c +++ b/src/nvidia/generated/g_virt_mem_range_nvoc.c @@ -159,12 +159,16 @@ static NvBool __nvoc_thunk_StandardMemory_vmrangeCanCopy(struct VirtualMemoryRan return stdmemCanCopy((struct StandardMemory *)(((unsigned char *)pStandardMemory) + __nvoc_rtti_VirtualMemoryRange_StandardMemory.offset)); } +static NvBool __nvoc_thunk_Memory_vmrangeIsGpuMapAllowed(struct VirtualMemoryRange *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), pGpu); +} + static NV_STATUS __nvoc_thunk_RmResource_vmrangeControl_Prologue(struct VirtualMemoryRange *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_Memory_vmrangeIsReady(struct VirtualMemoryRange *pMemory) { - return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset)); +static NV_STATUS __nvoc_thunk_Memory_vmrangeIsReady(struct VirtualMemoryRange *pMemory, NvBool bCopyConstructorContext) { + return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), bCopyConstructorContext); } static NV_STATUS __nvoc_thunk_VirtualMemory_vmrangeUnmapFrom(struct VirtualMemoryRange *pVirtualMemory, struct RS_RES_UNMAP_FROM_PARAMS *pParams) { @@ -175,6 +179,10 @@ static NV_STATUS __nvoc_thunk_Memory_vmrangeCheckCopyPermissions(struct VirtualM return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), pDstGpu, hDstClientNvBool); } +static NV_STATUS __nvoc_thunk_Memory_vmrangeIsDuplicate(struct VirtualMemoryRange *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RsResource_vmrangePreDestruct(struct VirtualMemoryRange *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RsResource.offset)); } @@ -257,6 +265,8 @@ static void __nvoc_init_funcTable_VirtualMemoryRange_1(VirtualMemoryRange *pThis pThis->__vmrangeCanCopy__ = &__nvoc_thunk_StandardMemory_vmrangeCanCopy; + pThis->__vmrangeIsGpuMapAllowed__ = &__nvoc_thunk_Memory_vmrangeIsGpuMapAllowed; + pThis->__vmrangeControl_Prologue__ = &__nvoc_thunk_RmResource_vmrangeControl_Prologue; pThis->__vmrangeIsReady__ = &__nvoc_thunk_Memory_vmrangeIsReady; @@ -265,6 +275,8 @@ static void __nvoc_init_funcTable_VirtualMemoryRange_1(VirtualMemoryRange *pThis pThis->__vmrangeCheckCopyPermissions__ = &__nvoc_thunk_Memory_vmrangeCheckCopyPermissions; + pThis->__vmrangeIsDuplicate__ = &__nvoc_thunk_Memory_vmrangeIsDuplicate; + pThis->__vmrangePreDestruct__ = &__nvoc_thunk_RsResource_vmrangePreDestruct; pThis->__vmrangeControl_Epilogue__ = &__nvoc_thunk_RmResource_vmrangeControl_Epilogue; diff --git a/src/nvidia/generated/g_virt_mem_range_nvoc.h b/src/nvidia/generated/g_virt_mem_range_nvoc.h index 840c21636..cfe4a92eb 100644 --- a/src/nvidia/generated/g_virt_mem_range_nvoc.h +++ b/src/nvidia/generated/g_virt_mem_range_nvoc.h @@ -70,10 +70,12 @@ struct VirtualMemoryRange { NvU32 (*__vmrangeGetRefCount__)(struct VirtualMemoryRange *); void (*__vmrangeAddAdditionalDependants__)(struct RsClient *, struct VirtualMemoryRange *, RsResourceRef *); NvBool (*__vmrangeCanCopy__)(struct VirtualMemoryRange *); + NvBool (*__vmrangeIsGpuMapAllowed__)(struct VirtualMemoryRange *, struct OBJGPU *); NV_STATUS (*__vmrangeControl_Prologue__)(struct VirtualMemoryRange *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__vmrangeIsReady__)(struct VirtualMemoryRange *); + NV_STATUS (*__vmrangeIsReady__)(struct VirtualMemoryRange *, NvBool); NV_STATUS (*__vmrangeUnmapFrom__)(struct VirtualMemoryRange *, struct RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__vmrangeCheckCopyPermissions__)(struct VirtualMemoryRange *, struct OBJGPU *, NvHandle); + NV_STATUS (*__vmrangeIsDuplicate__)(struct VirtualMemoryRange *, NvHandle, NvBool *); void (*__vmrangePreDestruct__)(struct VirtualMemoryRange *); void (*__vmrangeControl_Epilogue__)(struct VirtualMemoryRange *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vmrangeControlLookup__)(struct VirtualMemoryRange *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); @@ -121,10 +123,12 @@ NV_STATUS __nvoc_objCreate_VirtualMemoryRange(VirtualMemoryRange**, Dynamic*, Nv #define vmrangeGetRefCount(pResource) vmrangeGetRefCount_DISPATCH(pResource) #define vmrangeAddAdditionalDependants(pClient, pResource, pReference) vmrangeAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define vmrangeCanCopy(pStandardMemory) vmrangeCanCopy_DISPATCH(pStandardMemory) +#define vmrangeIsGpuMapAllowed(pMemory, pGpu) vmrangeIsGpuMapAllowed_DISPATCH(pMemory, pGpu) #define vmrangeControl_Prologue(pResource, pCallContext, pParams) vmrangeControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define vmrangeIsReady(pMemory) vmrangeIsReady_DISPATCH(pMemory) +#define vmrangeIsReady(pMemory, bCopyConstructorContext) vmrangeIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define vmrangeUnmapFrom(pVirtualMemory, pParams) vmrangeUnmapFrom_DISPATCH(pVirtualMemory, pParams) #define vmrangeCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) vmrangeCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) +#define vmrangeIsDuplicate(pMemory, hMemory, pDuplicate) vmrangeIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) #define vmrangePreDestruct(pResource) vmrangePreDestruct_DISPATCH(pResource) #define vmrangeControl_Epilogue(pResource, pCallContext, pParams) vmrangeControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define vmrangeControlLookup(pResource, pParams, ppEntry) vmrangeControlLookup_DISPATCH(pResource, pParams, ppEntry) @@ -178,12 +182,16 @@ static inline NvBool vmrangeCanCopy_DISPATCH(struct VirtualMemoryRange *pStandar return pStandardMemory->__vmrangeCanCopy__(pStandardMemory); } +static inline NvBool vmrangeIsGpuMapAllowed_DISPATCH(struct VirtualMemoryRange *pMemory, struct OBJGPU *pGpu) { + return pMemory->__vmrangeIsGpuMapAllowed__(pMemory, pGpu); +} + static inline NV_STATUS vmrangeControl_Prologue_DISPATCH(struct VirtualMemoryRange *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__vmrangeControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS vmrangeIsReady_DISPATCH(struct VirtualMemoryRange *pMemory) { - return pMemory->__vmrangeIsReady__(pMemory); +static inline NV_STATUS vmrangeIsReady_DISPATCH(struct VirtualMemoryRange *pMemory, NvBool bCopyConstructorContext) { + return pMemory->__vmrangeIsReady__(pMemory, bCopyConstructorContext); } static inline NV_STATUS vmrangeUnmapFrom_DISPATCH(struct VirtualMemoryRange *pVirtualMemory, struct RS_RES_UNMAP_FROM_PARAMS *pParams) { @@ -194,6 +202,10 @@ static inline NV_STATUS vmrangeCheckCopyPermissions_DISPATCH(struct VirtualMemor return pMemory->__vmrangeCheckCopyPermissions__(pMemory, pDstGpu, hDstClientNvBool); } +static inline NV_STATUS vmrangeIsDuplicate_DISPATCH(struct VirtualMemoryRange *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return pMemory->__vmrangeIsDuplicate__(pMemory, hMemory, pDuplicate); +} + static inline void vmrangePreDestruct_DISPATCH(struct VirtualMemoryRange *pResource) { pResource->__vmrangePreDestruct__(pResource); } @@ -215,6 +227,7 @@ static inline NvBool vmrangeAccessCallback_DISPATCH(struct VirtualMemoryRange *p } NV_STATUS vmrangeConstruct_IMPL(struct VirtualMemoryRange *arg_pVmRange, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_vmrangeConstruct(arg_pVmRange, arg_pCallContext, arg_pParams) vmrangeConstruct_IMPL(arg_pVmRange, arg_pCallContext, arg_pParams) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_virtual_mem_nvoc.c b/src/nvidia/generated/g_virtual_mem_nvoc.c index e648f8c8f..18d6798c3 100644 --- a/src/nvidia/generated/g_virtual_mem_nvoc.c +++ b/src/nvidia/generated/g_virtual_mem_nvoc.c @@ -150,16 +150,20 @@ static NvU32 __nvoc_thunk_RsResource_virtmemGetRefCount(struct VirtualMemory *pR return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RsResource.offset)); } -static NV_STATUS __nvoc_thunk_RmResource_virtmemControl_Prologue(struct VirtualMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RmResource.offset), pCallContext, pParams); -} - static NvBool __nvoc_thunk_StandardMemory_virtmemCanCopy(struct VirtualMemory *pStandardMemory) { return stdmemCanCopy((struct StandardMemory *)(((unsigned char *)pStandardMemory) + __nvoc_rtti_VirtualMemory_StandardMemory.offset)); } -static NV_STATUS __nvoc_thunk_Memory_virtmemIsReady(struct VirtualMemory *pMemory) { - return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemory_Memory.offset)); +static NvBool __nvoc_thunk_Memory_virtmemIsGpuMapAllowed(struct VirtualMemory *pMemory, struct OBJGPU *pGpu) { + return memIsGpuMapAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemory_Memory.offset), pGpu); +} + +static NV_STATUS __nvoc_thunk_RmResource_virtmemControl_Prologue(struct VirtualMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_virtmemIsReady(struct VirtualMemory *pMemory, NvBool bCopyConstructorContext) { + return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemory_Memory.offset), bCopyConstructorContext); } static NV_STATUS __nvoc_thunk_Memory_virtmemCheckCopyPermissions(struct VirtualMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { @@ -170,6 +174,10 @@ static void __nvoc_thunk_RsResource_virtmemPreDestruct(struct VirtualMemory *pRe resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_Memory_virtmemIsDuplicate(struct VirtualMemory *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemory_Memory.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_virtmemControl_Epilogue(struct VirtualMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RmResource.offset), pCallContext, pParams); } @@ -253,16 +261,20 @@ static void __nvoc_init_funcTable_VirtualMemory_1(VirtualMemory *pThis) { pThis->__virtmemGetRefCount__ = &__nvoc_thunk_RsResource_virtmemGetRefCount; - pThis->__virtmemControl_Prologue__ = &__nvoc_thunk_RmResource_virtmemControl_Prologue; - pThis->__virtmemCanCopy__ = &__nvoc_thunk_StandardMemory_virtmemCanCopy; + pThis->__virtmemIsGpuMapAllowed__ = &__nvoc_thunk_Memory_virtmemIsGpuMapAllowed; + + pThis->__virtmemControl_Prologue__ = &__nvoc_thunk_RmResource_virtmemControl_Prologue; + pThis->__virtmemIsReady__ = &__nvoc_thunk_Memory_virtmemIsReady; pThis->__virtmemCheckCopyPermissions__ = &__nvoc_thunk_Memory_virtmemCheckCopyPermissions; pThis->__virtmemPreDestruct__ = &__nvoc_thunk_RsResource_virtmemPreDestruct; + pThis->__virtmemIsDuplicate__ = &__nvoc_thunk_Memory_virtmemIsDuplicate; + pThis->__virtmemControl_Epilogue__ = &__nvoc_thunk_RmResource_virtmemControl_Epilogue; pThis->__virtmemControlLookup__ = &__nvoc_thunk_RsResource_virtmemControlLookup; diff --git a/src/nvidia/generated/g_virtual_mem_nvoc.h b/src/nvidia/generated/g_virtual_mem_nvoc.h index 4f71a4759..68d565c39 100644 --- a/src/nvidia/generated/g_virtual_mem_nvoc.h +++ b/src/nvidia/generated/g_virtual_mem_nvoc.h @@ -72,11 +72,13 @@ struct VirtualMemory { NV_STATUS (*__virtmemControlFilter__)(struct VirtualMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__virtmemAddAdditionalDependants__)(struct RsClient *, struct VirtualMemory *, RsResourceRef *); NvU32 (*__virtmemGetRefCount__)(struct VirtualMemory *); - NV_STATUS (*__virtmemControl_Prologue__)(struct VirtualMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__virtmemCanCopy__)(struct VirtualMemory *); - NV_STATUS (*__virtmemIsReady__)(struct VirtualMemory *); + NvBool (*__virtmemIsGpuMapAllowed__)(struct VirtualMemory *, struct OBJGPU *); + NV_STATUS (*__virtmemControl_Prologue__)(struct VirtualMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__virtmemIsReady__)(struct VirtualMemory *, NvBool); NV_STATUS (*__virtmemCheckCopyPermissions__)(struct VirtualMemory *, struct OBJGPU *, NvHandle); void (*__virtmemPreDestruct__)(struct VirtualMemory *); + NV_STATUS (*__virtmemIsDuplicate__)(struct VirtualMemory *, NvHandle, NvBool *); void (*__virtmemControl_Epilogue__)(struct VirtualMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__virtmemControlLookup__)(struct VirtualMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__virtmemMap__)(struct VirtualMemory *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); @@ -130,11 +132,13 @@ NV_STATUS __nvoc_objCreate_VirtualMemory(VirtualMemory**, Dynamic*, NvU32, CALL_ #define virtmemControlFilter(pResource, pCallContext, pParams) virtmemControlFilter_DISPATCH(pResource, pCallContext, pParams) #define virtmemAddAdditionalDependants(pClient, pResource, pReference) virtmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define virtmemGetRefCount(pResource) virtmemGetRefCount_DISPATCH(pResource) -#define virtmemControl_Prologue(pResource, pCallContext, pParams) virtmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define virtmemCanCopy(pStandardMemory) virtmemCanCopy_DISPATCH(pStandardMemory) -#define virtmemIsReady(pMemory) virtmemIsReady_DISPATCH(pMemory) +#define virtmemIsGpuMapAllowed(pMemory, pGpu) virtmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define virtmemControl_Prologue(pResource, pCallContext, pParams) virtmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define virtmemIsReady(pMemory, bCopyConstructorContext) virtmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define virtmemCheckCopyPermissions(pMemory, pDstGpu, hDstClientNvBool) virtmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, hDstClientNvBool) #define virtmemPreDestruct(pResource) virtmemPreDestruct_DISPATCH(pResource) +#define virtmemIsDuplicate(pMemory, hMemory, pDuplicate) virtmemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) #define virtmemControl_Epilogue(pResource, pCallContext, pParams) virtmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define virtmemControlLookup(pResource, pParams, ppEntry) virtmemControlLookup_DISPATCH(pResource, pParams, ppEntry) #define virtmemMap(pMemory, pCallContext, pParams, pCpuMapping) virtmemMap_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) @@ -191,16 +195,20 @@ static inline NvU32 virtmemGetRefCount_DISPATCH(struct VirtualMemory *pResource) return pResource->__virtmemGetRefCount__(pResource); } -static inline NV_STATUS virtmemControl_Prologue_DISPATCH(struct VirtualMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__virtmemControl_Prologue__(pResource, pCallContext, pParams); -} - static inline NvBool virtmemCanCopy_DISPATCH(struct VirtualMemory *pStandardMemory) { return pStandardMemory->__virtmemCanCopy__(pStandardMemory); } -static inline NV_STATUS virtmemIsReady_DISPATCH(struct VirtualMemory *pMemory) { - return pMemory->__virtmemIsReady__(pMemory); +static inline NvBool virtmemIsGpuMapAllowed_DISPATCH(struct VirtualMemory *pMemory, struct OBJGPU *pGpu) { + return pMemory->__virtmemIsGpuMapAllowed__(pMemory, pGpu); +} + +static inline NV_STATUS virtmemControl_Prologue_DISPATCH(struct VirtualMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__virtmemControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS virtmemIsReady_DISPATCH(struct VirtualMemory *pMemory, NvBool bCopyConstructorContext) { + return pMemory->__virtmemIsReady__(pMemory, bCopyConstructorContext); } static inline NV_STATUS virtmemCheckCopyPermissions_DISPATCH(struct VirtualMemory *pMemory, struct OBJGPU *pDstGpu, NvHandle hDstClientNvBool) { @@ -211,6 +219,10 @@ static inline void virtmemPreDestruct_DISPATCH(struct VirtualMemory *pResource) pResource->__virtmemPreDestruct__(pResource); } +static inline NV_STATUS virtmemIsDuplicate_DISPATCH(struct VirtualMemory *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return pMemory->__virtmemIsDuplicate__(pMemory, hMemory, pDuplicate); +} + static inline void virtmemControl_Epilogue_DISPATCH(struct VirtualMemory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__virtmemControl_Epilogue__(pResource, pCallContext, pParams); } @@ -228,10 +240,13 @@ static inline NvBool virtmemAccessCallback_DISPATCH(struct VirtualMemory *pResou } NV_STATUS virtmemConstruct_IMPL(struct VirtualMemory *arg_pVirtualMemory, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + #define __nvoc_virtmemConstruct(arg_pVirtualMemory, arg_pCallContext, arg_pParams) virtmemConstruct_IMPL(arg_pVirtualMemory, arg_pCallContext, arg_pParams) void virtmemDestruct_IMPL(struct VirtualMemory *pVirtualMemory); + #define __nvoc_virtmemDestruct(pVirtualMemory) virtmemDestruct_IMPL(pVirtualMemory) NV_STATUS virtmemReserveMempool_IMPL(struct VirtualMemory *pVirtualMemory, struct OBJGPU *arg0, NvHandle hDevice, NvU64 size, NvU32 pageSizeMask); + #ifdef __nvoc_virtual_mem_h_disabled static inline NV_STATUS virtmemReserveMempool(struct VirtualMemory *pVirtualMemory, struct OBJGPU *arg0, NvHandle hDevice, NvU64 size, NvU32 pageSizeMask) { NV_ASSERT_FAILED_PRECOMP("VirtualMemory was disabled!"); @@ -242,6 +257,7 @@ static inline NV_STATUS virtmemReserveMempool(struct VirtualMemory *pVirtualMemo #endif //__nvoc_virtual_mem_h_disabled NvBool virtmemMatchesVASpace_IMPL(struct VirtualMemory *pVirtualMemory, NvHandle hClient, NvHandle hVASpace); + #ifdef __nvoc_virtual_mem_h_disabled static inline NvBool virtmemMatchesVASpace(struct VirtualMemory *pVirtualMemory, NvHandle hClient, NvHandle hVASpace) { NV_ASSERT_FAILED_PRECOMP("VirtualMemory was disabled!"); @@ -252,8 +268,10 @@ static inline NvBool virtmemMatchesVASpace(struct VirtualMemory *pVirtualMemory, #endif //__nvoc_virtual_mem_h_disabled NV_STATUS virtmemGetByHandleAndDevice_IMPL(struct RsClient *pClient, NvHandle hMemory, NvHandle hDevice, struct VirtualMemory **ppVirtualMemory); + #define virtmemGetByHandleAndDevice(pClient, hMemory, hDevice, ppVirtualMemory) virtmemGetByHandleAndDevice_IMPL(pClient, hMemory, hDevice, ppVirtualMemory) void virtmemGetAddressAndSize_IMPL(struct VirtualMemory *arg0, NvU64 *pVAddr, NvU64 *pSize); + #define virtmemGetAddressAndSize(arg0, pVAddr, pSize) virtmemGetAddressAndSize_IMPL(arg0, pVAddr, pSize) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_zbc_api_nvoc.c b/src/nvidia/generated/g_zbc_api_nvoc.c index 486cdd9bf..b7484670c 100644 --- a/src/nvidia/generated/g_zbc_api_nvoc.c +++ b/src/nvidia/generated/g_zbc_api_nvoc.c @@ -165,6 +165,10 @@ static NV_STATUS __nvoc_thunk_RsResource_zbcapiUnmapFrom(struct ZbcApi *pResourc return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset), pParams); } +static NV_STATUS __nvoc_thunk_RsResource_zbcapiIsDuplicate(struct ZbcApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset), hMemory, pDuplicate); +} + static void __nvoc_thunk_RmResource_zbcapiControl_Epilogue(struct ZbcApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RmResource.offset), pCallContext, pParams); } @@ -408,6 +412,8 @@ static void __nvoc_init_funcTable_ZbcApi_1(ZbcApi *pThis, RmHalspecOwner *pRmhal pThis->__zbcapiUnmapFrom__ = &__nvoc_thunk_RsResource_zbcapiUnmapFrom; + pThis->__zbcapiIsDuplicate__ = &__nvoc_thunk_RsResource_zbcapiIsDuplicate; + pThis->__zbcapiControl_Epilogue__ = &__nvoc_thunk_RmResource_zbcapiControl_Epilogue; pThis->__zbcapiControlLookup__ = &__nvoc_thunk_RsResource_zbcapiControlLookup; diff --git a/src/nvidia/generated/g_zbc_api_nvoc.h b/src/nvidia/generated/g_zbc_api_nvoc.h index ddfd0084d..82829e7eb 100644 --- a/src/nvidia/generated/g_zbc_api_nvoc.h +++ b/src/nvidia/generated/g_zbc_api_nvoc.h @@ -81,6 +81,7 @@ struct ZbcApi { NV_STATUS (*__zbcapiInternalControlForward__)(struct ZbcApi *, NvU32, void *, NvU32); void (*__zbcapiPreDestruct__)(struct ZbcApi *); NV_STATUS (*__zbcapiUnmapFrom__)(struct ZbcApi *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__zbcapiIsDuplicate__)(struct ZbcApi *, NvHandle, NvBool *); void (*__zbcapiControl_Epilogue__)(struct ZbcApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__zbcapiControlLookup__)(struct ZbcApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__zbcapiMap__)(struct ZbcApi *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); @@ -141,6 +142,7 @@ NV_STATUS __nvoc_objCreate_ZbcApi(ZbcApi**, Dynamic*, NvU32, struct CALL_CONTEXT #define zbcapiInternalControlForward(pGpuResource, command, pParams, size) zbcapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define zbcapiPreDestruct(pResource) zbcapiPreDestruct_DISPATCH(pResource) #define zbcapiUnmapFrom(pResource, pParams) zbcapiUnmapFrom_DISPATCH(pResource, pParams) +#define zbcapiIsDuplicate(pResource, hMemory, pDuplicate) zbcapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define zbcapiControl_Epilogue(pResource, pCallContext, pParams) zbcapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define zbcapiControlLookup(pResource, pParams, ppEntry) zbcapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define zbcapiMap(pGpuResource, pCallContext, pParams, pCpuMapping) zbcapiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) @@ -149,6 +151,7 @@ static inline NV_STATUS zbcapiConstructHal_56cd7a(struct ZbcApi *pZbcApi, struct return NV_OK; } + #ifdef __nvoc_zbc_api_h_disabled static inline NV_STATUS zbcapiConstructHal(struct ZbcApi *pZbcApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { NV_ASSERT_FAILED_PRECOMP("ZbcApi was disabled!"); @@ -164,6 +167,7 @@ static inline void zbcapiDestruct_b3696a(struct ZbcApi *pZbcApi) { return; } + #define __nvoc_zbcapiDestruct(pZbcApi) zbcapiDestruct_b3696a(pZbcApi) NV_STATUS zbcapiCtrlCmdSetZbcColorClear_IMPL(struct ZbcApi *pZbcApi, NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS *pSetZBCClearParams); @@ -279,6 +283,10 @@ static inline NV_STATUS zbcapiUnmapFrom_DISPATCH(struct ZbcApi *pResource, RS_RE return pResource->__zbcapiUnmapFrom__(pResource, pParams); } +static inline NV_STATUS zbcapiIsDuplicate_DISPATCH(struct ZbcApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__zbcapiIsDuplicate__(pResource, hMemory, pDuplicate); +} + static inline void zbcapiControl_Epilogue_DISPATCH(struct ZbcApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { pResource->__zbcapiControl_Epilogue__(pResource, pCallContext, pParams); } diff --git a/src/nvidia/generated/rmconfig.h b/src/nvidia/generated/rmconfig.h index 1bb27cb29..ac6e822ba 100644 --- a/src/nvidia/generated/rmconfig.h +++ b/src/nvidia/generated/rmconfig.h @@ -5,7 +5,7 @@ // Profile: shipping-gpus-openrm // Template: templates/gt_rmconfig.h // -// Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, GH10X +// Chips: TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X // #ifndef _RMCFG_H_ @@ -81,6 +81,8 @@ #define RMCFG_CHIP_AD102 1 #define RMCFG_CHIP_AD103 1 #define RMCFG_CHIP_AD104 1 +#define RMCFG_CHIP_AD106 1 +#define RMCFG_CHIP_AD107 1 #define RMCFG_CHIP_GH100 1 @@ -218,32 +220,31 @@ #define RMCFG_FEATURE_PLATFORM_WINDOWS_VISTA 0 // aka PLATFORM_WINDOWS_LDDM #define RMCFG_FEATURE_PLATFORM_UNIX 1 // Running on Unix #define RMCFG_FEATURE_PLATFORM_DCE 0 // Running on Display Control Engine (DCE, an ARM Cortex R5 on Tegra) -#define RMCFG_FEATURE_PLATFORM_DOS 0 // Running on DOS/DJGPP #define RMCFG_FEATURE_PLATFORM_SIM 0 // Running on Simulator #define RMCFG_FEATURE_PLATFORM_MODS 0 // Running as part of MODS #define RMCFG_FEATURE_PLATFORM_GSP 0 // Running as part of GSP Firmware #define RMCFG_FEATURE_PLATFORM_MODS_WINDOWS 0 // Running as part of MODS on Windows #define RMCFG_FEATURE_PLATFORM_MODS_UNIX 0 // Running as part of MODS on UNIX -#define RMCFG_FEATURE_PLATFORM_MODS_DOS 0 // Running as part of MODS on DOS -#define RMCFG_FEATURE_PLATFORM_MODS_DJGPP 0 // Running as part of MODS on DJGPP #define RMCFG_FEATURE_ARCH_UNKNOWN 0 // unknown arch #define RMCFG_FEATURE_ARCH_X86 0 // Intel x86, 32bit #define RMCFG_FEATURE_ARCH_X64 0 // Intel 64bit #define RMCFG_FEATURE_ARCH_RISCV64 0 // RISCV, 64bit #define RMCFG_FEATURE_ARCH_AMD64 1 // AMD, 64bit -#define RMCFG_FEATURE_ARCH_IA64 0 // Itanium ia64 #define RMCFG_FEATURE_ARCH_PPC 0 // Power PC #define RMCFG_FEATURE_ARCH_PPC64LE 0 // 64-bit PPC little-endian #define RMCFG_FEATURE_ARCH_ARM 0 // ARM #define RMCFG_FEATURE_ARCH_ARM_V7 0 // ARM v7 #define RMCFG_FEATURE_ARCH_AARCH64 0 // AArch64 -#define RMCFG_FEATURE_ARCH_ARGON 0 // argon?? -#define RMCFG_FEATURE_ARCH_AM926 0 // am926?? #define RMCFG_FEATURE_RMCORE_BASE 1 // RMCORE Base -#define RMCFG_FEATURE_ORIN_PHYSICAL_RM 1 // Physical layer of RM, disabled only on Orin #define RMCFG_FEATURE_KERNEL_RM 1 // Kernel layer of RM -#define RMCFG_FEATURE_NOTEBOOK 0 // Notebook support +#define RMCFG_FEATURE_ORIN_PHYSICAL_RM 1 // Physical layer of RM, disabled only on Orin +#define RMCFG_FEATURE_LIBOS_3_X 1 // Enable Libos-3.x feature +#define RMCFG_FEATURE_NOTEBOOK 1 // Notebook support +#define RMCFG_FEATURE_EXTDEV 1 // Daughter boards connected to Quadro GPUs +#define RMCFG_FEATURE_EXTDEV_GSYNC 1 // Quadro Sync (QSYNC) board for Quadro GPUs +#define RMCFG_FEATURE_EXTDEV_GSYNC_P2060 1 // Quadro Sync (QSYNC) board version 3 #define RMCFG_FEATURE_MXM 0 // MXM Module Support (all versions) +#define RMCFG_FEATURE_NBSI 1 // NoteBook System Information Structure #define RMCFG_FEATURE_ONSEMI_NB7NQ621M 1 // ONSEMI_NB7NQ621M Redriver Support #define RMCFG_FEATURE_DCB_0X 1 // Fallback DCB routines #define RMCFG_FEATURE_DCB_4X 1 // DCB4x (used on G8x and later) @@ -251,14 +252,15 @@ #define RMCFG_FEATURE_RMAPI_GRAVEYARD 1 // Use RMAPI Graveyard to translate deprecated APIs #define RMCFG_FEATURE_HOTPLUG_POLLING 0 // HotPlug polling #define RMCFG_FEATURE_MULTI_GPU 1 // Multiple GPUs managed by same RM instance -#define RMCFG_FEATURE_RM_BASIC_LOCK_MODEL 1 // Support for Basic Lock Model in RM +#define RMCFG_FEATURE_RM_BASIC_LOCK_MODEL 1 // Support for Basic Lock Model in RM #define RMCFG_FEATURE_VIRTUALIZATION 0 // Detection and Guest RM Implementation within a Virtualization environment +#define RMCFG_FEATURE_VIRTUALIZATION_LEGACY 0 // aka VIRTUALIZATION #define RMCFG_FEATURE_PRESILICON 0 // For builds that can run on simulated or emulated GPU #define RMCFG_FEATURE_GSP_CLIENT_RM 1 // GSP client RM #define RMCFG_FEATURE_DCE_CLIENT_RM 0 // DCE client RM #define RMCFG_FEATURE_PROTOBUF 1 // Protobuf data encoding for OCA data dumps #define RMCFG_FEATURE_RELEASE_BUILD 1 // Release Build -#define RMCFG_FEATURE_VERIF_ONLY_CONTROLS 0 // Allow verify only control cmds to be used on verif builds(determined by this feature) +#define RMCFG_FEATURE_VERIF_ONLY_CONTROLS 0 // Allow verify only control cmds to be used on verif builds (determined by this feature) #define RMCFG_FEATURE_PAGE_RETIREMENT 1 // Offlining bad memory pages from the FB heap #define RMCFG_FEATURE_PMA 1 // Physical memory allocator #define RMCFG_FEATURE_DEVINIT_SCRIPT 0 // VBIOS scripting engine for sharing register sequences @@ -275,12 +277,15 @@ #define RMCFG_FEATURE_TILED_RESOURCE_COMPR 1 #define RMCFG_FEATURE_SYNC_GPU_BOOST 1 // Synchronized GPU Boost #define RMCFG_FEATURE_NVSR_ON_NVDISPLAY 1 // NVSR on Nvdisplay +#define RMCFG_FEATURE_MODS_FEATURES 0 // Flag for enabling MODS required features in RM #define RMCFG_FEATURE_MANUAL_TRIGGER_BA_DMA_MODE 0 // Support for manually actuated BA DMA mode data collection. #define RMCFG_FEATURE_RM_DRIVEN_BA_DMA_MODE 0 // Support for RM-driven BA DMA mode data collection. #define RMCFG_FEATURE_VBLANK_CALLBACK 1 // Vblank callback functionality within RM #define RMCFG_FEATURE_TEGRA_SOC_NVDISPLAY 0 // Tegra SOC NvDisplay Driver #define RMCFG_FEATURE_TEGRA_SOC_NVDISPLAY_MINIMAL 0 // Enable only those parts of display code which are needed for Tegra SOC NvDisplay Driver #define RMCFG_FEATURE_HEAD_REGIONAL_CRC 0 // Display Head Regional CRC support +#define RMCFG_FEATURE_MULTICAST_FABRIC 1 // Support for MULTICAST_FABRIC +#define RMCFG_FEATURE_NVLINK_ERROR_THRESHOLD 1 // Support for NVLINK_ERROR_THRESHOLD @@ -315,22 +320,25 @@ #define RMCFG_CLASS_NV01_MEMORY_VIRTUAL 1 #define RMCFG_CLASS_NV01_MEMORY_SYSTEM_DYNAMIC 1 // aka NV01_MEMORY_VIRTUAL #define RMCFG_CLASS_NV1_MEMORY_SYSTEM_DYNAMIC 1 // aka NV01_MEMORY_VIRTUAL +#define RMCFG_CLASS_NV_MEMORY_MAPPER 1 #define RMCFG_CLASS_NV01_MEMORY_LOCAL_PHYSICAL 1 #define RMCFG_CLASS_NV01_MEMORY_SYNCPOINT 0 #define RMCFG_CLASS_NV01_MEMORY_SYSTEM_OS_DESCRIPTOR 1 #define RMCFG_CLASS_NV01_MEMORY_DEVICELESS 1 #define RMCFG_CLASS_NV01_MEMORY_FRAMEBUFFER_CONSOLE 1 #define RMCFG_CLASS_NV01_MEMORY_HW_RESOURCES 1 -#define RMCFG_CLASS_NV01_MEMORY_LIST_SYSTEM 0 +#define RMCFG_CLASS_NV01_MEMORY_LIST_SYSTEM 1 +#define RMCFG_CLASS_NV01_MEMORY_LIST_FBMEM 1 +#define RMCFG_CLASS_NV01_MEMORY_LIST_OBJECT 1 +#define RMCFG_CLASS_NV_IMEX_SESSION 0 #define RMCFG_CLASS_NV01_MEMORY_FLA 1 -#define RMCFG_CLASS_NV01_MEMORY_FABRIC_EXPORT 0 #define RMCFG_CLASS_NV_MEMORY_FABRIC_EXPORT_V2 0 -#define RMCFG_CLASS_NV01_MEMORY_FABRIC_IMPORT 0 #define RMCFG_CLASS_NV_MEMORY_FABRIC 1 #define RMCFG_CLASS_NV_MEMORY_FABRIC_IMPORT_V2 0 #define RMCFG_CLASS_NV_MEMORY_FABRIC_EXPORTED_REF 0 #define RMCFG_CLASS_NV_MEMORY_FABRIC_IMPORTED_REF 0 #define RMCFG_CLASS_FABRIC_VASPACE_A 1 +#define RMCFG_CLASS_NV_MEMORY_MULTICAST_FABRIC 1 #define RMCFG_CLASS_IO_VASPACE_A 1 #define RMCFG_CLASS_NV01_NULL 1 #define RMCFG_CLASS_NV1_NULL 1 // aka NV01_NULL @@ -360,6 +368,7 @@ #define RMCFG_CLASS_HOPPER_CHANNEL_GPFIFO_A 1 #define RMCFG_CLASS_NV04_SOFTWARE_TEST 1 #define RMCFG_CLASS_NV4_SOFTWARE_TEST 1 // aka NV04_SOFTWARE_TEST +#define RMCFG_CLASS_NV30_GSYNC 1 #define RMCFG_CLASS_VOLTA_USERMODE_A 1 #define RMCFG_CLASS_TURING_USERMODE_A 1 #define RMCFG_CLASS_AMPERE_USERMODE_A 1 @@ -383,6 +392,7 @@ #define RMCFG_CLASS_NVC67B_WINDOW_IMM_CHANNEL_DMA 1 #define RMCFG_CLASS_NVC67D_CORE_CHANNEL_DMA 1 #define RMCFG_CLASS_NVC67E_WINDOW_CHANNEL_DMA 1 +#define RMCFG_CLASS_NVC77F_ANY_CHANNEL_DMA 1 #define RMCFG_CLASS_NVC770_DISPLAY 1 #define RMCFG_CLASS_NVC771_DISP_SF_USER 1 #define RMCFG_CLASS_NVC77D_CORE_CHANNEL_DMA 1 @@ -444,9 +454,12 @@ #define RMCFG_CLASS_HOPPER_A 1 // HopperA (Graphics) #define RMCFG_CLASS_HOPPER_COMPUTE_A 1 // HopperComputeA (Graphics Compute) #define RMCFG_CLASS_NV40_DEBUG_BUFFER 1 +#define RMCFG_CLASS_RM_USER_SHARED_DATA 1 #define RMCFG_CLASS_GT200_DEBUGGER 1 // CUDA Debugger support #define RMCFG_CLASS_NV40_I2C 1 // I2C operations #define RMCFG_CLASS_NV_E3_THREED 0 // Tegra 3D class +#define RMCFG_CLASS_NVA081_VGPU_CONFIG 1 // virtual gpu configuration +#define RMCFG_CLASS_NVA084_KERNEL_HOST_VGPU_DEVICE 1 // Kernel component of the host virtual gpu device #define RMCFG_CLASS_NV0060_SYNC_GPU_BOOST 1 // Synchronized GPU Boost Class. Defines a set of GPUs for Synchronized Boost #define RMCFG_CLASS_GP100_UVM_SW 1 // UVM SW class to support SW methods for fault cancel #define RMCFG_CLASS_NV_EVENT_BUFFER 1 // Event buffer class used to share event data with UMD @@ -464,7 +477,7 @@ #define RMCFG_MODULE_HOSTENG 1 // Base class for host engines #define RMCFG_MODULE_FLCNABLE 0 // Base class for engines requiring falcon #define RMCFG_MODULE_PMUCLIENT 0 // Base class for engines that use PMU engine -#define RMCFG_MODULE_INTRABLE 1 // Base class to generate and service top-level interrupts +#define RMCFG_MODULE_INTRABLE 0 // Base class to generate and service top-level interrupts #define RMCFG_MODULE_MUTEXABLE 0 // Base class for engines that implements mutex #define RMCFG_MODULE_GpuMutexMgr 0 // GPU Mutex Manager #define RMCFG_MODULE_GPUMUTEXMGR 0 // aka GpuMutexMgr @@ -547,7 +560,7 @@ #define RMCFG_MODULE_KERNEL_CE 1 // Kernel Copy Engine #define RMCFG_MODULE_PMU 0 // PMU peregrine core #define RMCFG_MODULE_KERNEL_PMU 1 // PMU peregrine core on Kernel(CPU) RM -#define RMCFG_MODULE_GPS 0 // GPU Performance Scaling +#define RMCFG_MODULE_PLATFORM_REQUEST_HANDLER 0 // Platform Request Handler on Kernel(CPU) RM #define RMCFG_MODULE_MSENC 0 // Video Encoder (MSENC) Engine #define RMCFG_MODULE_KERNEL_NVENC 1 #define RMCFG_MODULE_HDA 0 // High Definition Audio (HDA) Engine @@ -572,7 +585,7 @@ #define RMCFG_MODULE_OS 1 // OS Layer #define RMCFG_MODULE_GPUMGR 1 // GPU Manager object #define RMCFG_MODULE_HEAP 1 // Heap Engine Object -#define RMCFG_MODULE_BRIGHTC 0 // Backlight brightness control module +#define RMCFG_MODULE_BRIGHTC 1 // Backlight brightness control module #define RMCFG_MODULE_GSYNCMGR 0 // GSYNC Manager #define RMCFG_MODULE_OD 0 // Display component: Output Device #define RMCFG_MODULE_DFP 0 // Display component: Display Flat Panel @@ -588,6 +601,7 @@ #define RMCFG_MODULE_PSR 0 // Panel Self Refresh #define RMCFG_MODULE_UVM 1 // Unified Virtual Memory - provides interface to separate UVM and verification support #define RMCFG_MODULE_VGPUMGR 0 // Virtual GPU management +#define RMCFG_MODULE_KERNEL_VGPUMGR 1 // Virtual GPU management on Kernel(CPU) RM #define RMCFG_MODULE_SEC2 0 // New secure falcon #define RMCFG_MODULE_KERNEL_SEC2 1 // SEC2 on Kernel(CPU) RM. Used for booting Falcon cores. #define RMCFG_MODULE_PMS 0 // PMU ModeSet object @@ -597,7 +611,7 @@ #define RMCFG_MODULE_REFCNT 1 // Reference Counting #define RMCFG_MODULE_GPULOG 0 // Logger for logging GPU related data #define RMCFG_MODULE_FECS 0 // Front-end context switch -#define RMCFG_MODULE_HYPERVISOR 0 // Hypervisor object to support its native API +#define RMCFG_MODULE_HYPERVISOR 1 // Hypervisor object to support its native API #define RMCFG_MODULE_VRRMGR 0 // VRR Management object #define RMCFG_MODULE_GPCCS 0 // GPC context switch #define RMCFG_MODULE_MISSING 0 // MISSING (placeholder) Engine @@ -676,10 +690,6 @@ #define RMCFG_API_NV_ESC_RM_FREE 1 // aka NV01_FREE #define RMCFG_API_Nv01Free 1 // aka NV01_FREE #define RMCFG_API_NvRmFree 1 // aka NV01_FREE -#define RMCFG_API_NV04_UPDATE_CONTEXT_DMA 1 -#define RMCFG_API_NVOS37_PARAMETERS 1 // aka NV04_UPDATE_CONTEXT_DMA -#define RMCFG_API_NV_ESC_RM_UPDATE_CONTEXT_DMA 1 // aka NV04_UPDATE_CONTEXT_DMA -#define RMCFG_API_Nv03AllocChannelDma 1 // aka NV04_UPDATE_CONTEXT_DMA #define RMCFG_API_NV04_VID_HEAP_CONTROL 1 #define RMCFG_API_NVOS32_PARAMETERS 1 // aka NV04_VID_HEAP_CONTROL #define RMCFG_API_NV_ESC_RM_VID_HEAP_CONTROL 1 // aka NV04_VID_HEAP_CONTROL @@ -765,18 +775,6 @@ #define RMCFG_API_NV_ESC_RM_SHARE 1 // aka NV04_SHARE_OBJECT #define RMCFG_API_Nv04Share 1 // aka NV04_SHARE_OBJECT #define RMCFG_API_NvRmShare 1 // aka NV04_SHARE_OBJECT -#define RMCFG_API_NV04_GET_MEMORY_INFO 1 -#define RMCFG_API_NVOS58_PARAMETERS 1 // aka NV04_GET_MEMORY_INFO -#define RMCFG_API_NV_ESC_RM_GET_MEMORY_INFO 1 // aka NV04_GET_MEMORY_INFO -#define RMCFG_API_Nv04GetMemoryInfo 1 // aka NV04_GET_MEMORY_INFO -#define RMCFG_API_NV04_MAP_MEMORY_DMA_OFFSET 1 -#define RMCFG_API_NVOS59_PARAMETERS 1 // aka NV04_MAP_MEMORY_DMA_OFFSET -#define RMCFG_API_NV_ESC_RM_MAP_MEMORY_DMA_OFFSET 1 // aka NV04_MAP_MEMORY_DMA_OFFSET -#define RMCFG_API_Nv04MapMemoryDmaOffset 1 // aka NV04_MAP_MEMORY_DMA_OFFSET -#define RMCFG_API_NV04_UNMAP_MEMORY_DMA_OFFSET 1 -#define RMCFG_API_NVOS60_PARAMETERS 1 // aka NV04_UNMAP_MEMORY_DMA_OFFSET -#define RMCFG_API_NV_ESC_RM_UNMAP_MEMORY_DMA_OFFSET 1 // aka NV04_UNMAP_MEMORY_DMA_OFFSET -#define RMCFG_API_Nv04UnmapMemoryDmaOffset 1 // aka NV04_UNMAP_MEMORY_DMA_OFFSET #define RMCFG_API_NV04_ADD_VBLANK_CALLBACK 1 #define RMCFG_API_NVOS61_PARAMETERS 1 // aka NV04_ADD_VBLANK_CALLBACK #define RMCFG_API_NV_ESC_RM_ADD_VBLANK_CALLBACK 1 // aka NV04_ADD_VBLANK_CALLBACK diff --git a/src/nvidia/inc/kernel/core/locks.h b/src/nvidia/inc/kernel/core/locks.h index de6ab641f..2c373137c 100644 --- a/src/nvidia/inc/kernel/core/locks.h +++ b/src/nvidia/inc/kernel/core/locks.h @@ -110,8 +110,6 @@ typedef struct // Attempt acquire even if it potentially violates the locking order // But do not block in a way that could cause a deadlock #define GPU_LOCK_FLAGS_SAFE_LOCK_UPGRADE NVBIT(2) -// Old name alias -#define GPUS_LOCK_FLAGS_COND_ACQUIRE GPU_LOCK_FLAGS_COND_ACQUIRE // // RM Lock Related Functions @@ -189,17 +187,9 @@ void rmIntrMaskLockRelease(OBJGPU *pGpu, NvU64 oldIrql); #define rmInitLockMetering() #define rmDestroyLockMetering() -// -// RM API lock definitions are handled by the rmapi module. Providing legacy -// rmApiLockXxx interface for temporary compatibility. CORERM-1370 -// #include "rmapi/rmapi.h" #define API_LOCK_FLAGS_NONE RMAPI_LOCK_FLAGS_NONE #define API_LOCK_FLAGS_COND_ACQUIRE RMAPI_LOCK_FLAGS_COND_ACQUIRE -#define rmApiLockAcquire(flags, module) (rmapiLockAcquire(flags, module)) -static NV_INLINE NV_STATUS rmApiLockRelease(void) {rmapiLockRelease(); return NV_OK;} -#define rmApiLockIsOwner() (rmapiLockIsOwner()) - #endif // LOCKS_H diff --git a/src/nvidia/inc/kernel/gpu/ce/kernel_ce_private.h b/src/nvidia/inc/kernel/gpu/ce/kernel_ce_private.h index fb74ea0da..3804fe774 100644 --- a/src/nvidia/inc/kernel/gpu/ce/kernel_ce_private.h +++ b/src/nvidia/inc/kernel/gpu/ce/kernel_ce_private.h @@ -33,14 +33,19 @@ /*! * @brief Obtain relative CE index. * - * @param localEngType NV2080_ENGINE_TYPE_ for this CE, or partition-local engine type. + * @param rmEngineType RM_ENGINE_TYPE_ for this CE, or partition-local engine type. * @param ceIdx CE index in 0..GPU_MAX_CES-1 * * @return NV_OK if the conversion is successful. */ static NV_INLINE -NV_STATUS ceIndexFromType(OBJGPU *pGpu, NvHandle hClient, NvU32 localEngType, NvU32 *ceIdx) +NV_STATUS ceIndexFromType(OBJGPU *pGpu, NvHandle hClient, RM_ENGINE_TYPE rmEngineType, NvU32 *ceIdx) { + NV_STATUS status = NV_OK; + RM_ENGINE_TYPE localRmEngType = rmEngineType; + + *ceIdx = GPU_MAX_CES; + // // If MIG is enabled, client passes a logical engineId w.r.t its own partition // we need to convert this logical Id to a physical engine Id as we use it @@ -51,29 +56,24 @@ NV_STATUS ceIndexFromType(OBJGPU *pGpu, NvHandle hClient, NvU32 localEngType, Nv KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); MIG_INSTANCE_REF ref; - NV_CHECK_OK_OR_RETURN( - LEVEL_ERROR, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, - hClient, &ref)); + status = kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref); - NV_CHECK_OK_OR_RETURN( - LEVEL_ERROR, - kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, - localEngType, - ceIdx)); - } - else - { - *ceIdx = localEngType; + if (status != NV_OK) + return status; + + status = kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, rmEngineType, &localRmEngType); + + if (status != NV_OK) + return status; } - if (!NV2080_ENGINE_TYPE_IS_COPY(*ceIdx)) + if (!RM_ENGINE_TYPE_IS_COPY(localRmEngType)) { return NV_ERR_INVALID_ARGUMENT; } - *ceIdx = NV2080_ENGINE_TYPE_COPY_IDX(*ceIdx); - return NV_OK; + *ceIdx = RM_ENGINE_TYPE_COPY_IDX(localRmEngType); + return status; } #endif // KERNEL_CE_PRIVATE_H diff --git a/src/nvidia/inc/kernel/gpu/disp/kern_disp_type.h b/src/nvidia/inc/kernel/gpu/disp/kern_disp_type.h index 0497469eb..929ada517 100644 --- a/src/nvidia/inc/kernel/gpu/disp/kern_disp_type.h +++ b/src/nvidia/inc/kernel/gpu/disp/kern_disp_type.h @@ -29,6 +29,7 @@ * Defines display type enums that can be used in the KernelDisplay object. * ******************************************************************************/ +#define NV_PDISP_CHN_NUM_ANY 0x7F typedef enum { @@ -39,6 +40,7 @@ typedef enum dispChnClass_Ovly, dispChnClass_Winim, dispChnClass_Win, + dispChnClass_Any, dispChnClass_Supported } DISPCHNCLASS; @@ -49,4 +51,18 @@ enum DISPLAY_ICC_BW_CLIENT NUM_DISPLAY_ICC_BW_CLIENTS }; +typedef enum +{ + dispMemoryTarget_physNVM, + dispMemoryTarget_physPCI, + dispMemoryTarget_physPCICoherent +} DISPMEMORYTARGET; + +typedef struct +{ + NvU64 addr; + DISPMEMORYTARGET memTarget; + NvBool valid; +} VGAADDRDESC; + #endif // #ifndef KERN_DISP_TYPE_H diff --git a/src/nvidia/inc/kernel/gpu/external_device/dac_p2060.h b/src/nvidia/inc/kernel/gpu/external_device/dac_p2060.h new file mode 100644 index 000000000..0327b87e1 --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/external_device/dac_p2060.h @@ -0,0 +1,243 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef DAC_P2060_H +#define DAC_P2060_H + +/* ------------------------ Includes --------------------------------------- */ +#include "gpu/external_device/external_device.h" // DACEXTERNALDEVICE +#include "gpu/external_device/gsync.h" // GSYNCVIDEOMODE, GSYNCSYNCPOLARITY +#include "gpu/disp/kern_disp_max.h" + +/* ------------------------ Macros & Defines ------------------------------- */ + +// Display synchronization interface. (Framelock, Genlock, Swapready, etc) +#define NV_P2060_MAX_ASSOCIATED_GPUS 4 +#define NV_P2060_MAX_IFACES_PER_GSYNC 4 +#define NV_P2060_MAX_GPUS_PER_IFACE 1 +#define NV_P2060_MAX_HEADS_PER_GPU 4 +#define NV_P2060_MAX_MOSAIC_SLAVES 3 +#define NV_P2060_MAX_MOSAIC_GROUPS 2 + +#define NV_P2060_IFACE_ONE 0 +#define NV_P2060_IFACE_TWO 1 +#define NV_P2060_IFACE_THREE 2 +#define NV_P2060_IFACE_FOUR 3 + +#define NV_P2060_SYNC_SKEW_MAX_UNITS_FULL_SUPPORT 65535 // For FPGA with Rev >= 3. Refer Bug 1058215 +#define NV_P2060_SYNC_SKEW_MAX_UNITS_LIMITED_SUPPORT 1 // For FPGA with Rev < 3. +#define NV_P2060_SYNC_SKEW_RESOLUTION 977 +#define NV_P2060_START_DELAY_MAX_UNITS 65535 +#define NV_P2060_START_DELAY_RESOLUTION 7800 +#define NV_P2060_SYNC_INTERVAL_MAX_UNITS 7 + +#define NV_P2060_WATCHDOG_COUNT_DOWN_VALUE 60 // 1 minute, assuming watchdog time interval is 1 second. +#define NV_P2060_FRAME_COUNT_TIMER_INTERVAL 5000000000LL // 5 sec + +#define NV_P2060_MAX_GPU_FRAME_COUNT 65535 +#define NV_P2060_MAX_GSYNC_FRAME_COUNT 16777215 // 2^24.Gsync frame count is a 24 bit register +/* ------------------------ Types definitions ------------------------------ */ + +typedef struct EXTDEV_I2C_HANDLES +{ + //Internal handles per GPU + + NvHandle hClient; + NvHandle hDevice; + NvHandle hSubdevice; + NvHandle hSubscription; + NvU32 gpuId; +} EXTDEV_I2C_HANDLES; + +typedef struct +{ + NvU8 lossRegStatus; + NvU8 gainRegStatus; + NvU8 miscRegStatus; + DACEXTERNALDEVICE *pExtDevice; +}EXTDEV_INTR_DATA; + +// note: NV_P2060_MAX_ASSOCIATED_GPUS = NV_P2060_MAX_IFACES_PER_GSYNC * NV_P2060_MAX_GPUS_PER_IFACE + +struct DACP2060EXTERNALDEVICE +{ + //Must be at top of struct + DACEXTERNALDEVICE ExternalDevice; + + // Stuff for supporting the DisplaySync interface + NvU32 AssociatedCRTCs; // bit mask of crtcs ids associated. + GSYNCVIDEOMODE VideoMode; + GSYNCSYNCPOLARITY SyncPolarity; + NvU32 SyncStartDelay; + NvU32 SyncSkew; + NvU32 NSync; + NvU32 HouseSignal; + NvU32 UseHouseSync; + NvU32 Master; + NvU32 Slaves; + NvU32 EmitTestSignal; + NvU32 InterlaceMode; + NvU32 RefreshRate; // desired frame rate (units of .01Hz) + NvU32 DebugMask; + NvU32 gpuAttachMask; + NvU32 id; + NvU32 watchdogCountDownValue; + NvBool isNonFramelockInterruptEnabled; + NvU32 interruptEnabledInterface; + NvU32 tSwapRdyHi; /* Value of SWAP_LOCKOUT_START in accordance to the + * time in microseconds for which swap Rdy + * lines will remain high.(Provided via a regkey) + */ + NvU32 tSwapRdyHiLsrMinTime; /* Value of LSR_MIN_TIME in accordance to the time (in us) + * swap ready line will remain high.(Provided via a regkey) + */ + + struct { + NvU32 currentFrameCount; // gpu frame count register value for current user query + NvU32 previousFrameCount; // gpu frame count register value for previous user query + NvU32 totalFrameCount; // equals to cached gsync frame count = gpu frame count + difference. + NvU32 numberOfRollbacks; // Max value of N where (Gsync Frame Count > N * Gpu frame count) + NvU32 frameTime; // Time to render one frame. + NvU64 lastFrameCounterQueryTime; + NvS32 initialDifference; // Difference between Gsync frame count and (numberOfRollbacks * Gpu framecount) + NvU32 iface; + NvU32 head; + NvU32 vActive; // Vertical Resolution for which system is framelocked. + NvBool bReCheck; // Enabled to verify initialDifference 1 sec after initialization. + NvBool enableFrmCmpMatchIntSlave; // Enable the frmCmpMatchInt for slave, if this bit is set. + NvBool isFrmCmpMatchIntMasterEnabled; // To enable frmCmpMatchInt for master when gsync framecount exceeds (2^24 - 1000) + } FrameCountData; + + struct { + NvU32 Status1; + NvU64 lastSyncCheckTime; + NvU64 lastStereoToggleTime; + } Snapshot[NV_P2060_MAX_IFACES_PER_GSYNC]; + + // These arrays refer to the state of heads with respect to their sync + // source, and their usage can be kind of confusing. This table + // describes how they should be set/used: + // + // Head[i] --> Is Head[i] the frame lock master, or a slave + // SyncSrc --> Where is the sync timing actually coming from (the + // master head or a house sync signal) + + // + // Head[i] SyncSrc PM[i] PS[i] PSLS[i] + // -----------------------------------------+--------------------- + // Master Head[i] 1 0 0 + // Master House 1 1 0 + // Slave Head[!i] 0 0 1 + // Slave House 0 1 0 + // Slave External 0 1 0 + // Neither X 0 0 0 + // + // (the last row represents the case where the head has not been + // requested to lock). + + struct { + struct { + NvU32 Master [OBJ_MAX_HEADS]; + NvU32 Slaved [OBJ_MAX_HEADS]; + NvU32 LocalSlave[OBJ_MAX_HEADS]; + } Sync; + + struct { + NvU32 gpuId; + NvBool connected; + } GpuInfo; + + struct { + NvU32 OrigLsrMinTime[OBJ_MAX_HEADS]; + NvBool saved; + } DsiFliplock; + + struct { + NvU32 direction; + NvU32 mode; + NvBool saved; + } RasterSyncGpio; + + NvBool SwapReadyRequested; + NvBool skipSwapBarrierWar; + + NvU32 lastEventNotified; + NvU32 gainedSync; // Set when we gain sync after enabling framelock. + + } Iface[NV_P2060_MAX_IFACES_PER_GSYNC]; + + EXTDEV_I2C_HANDLES i2cHandles[NV_P2060_MAX_IFACES_PER_GSYNC]; + + struct { + NvU32 gpuTimingSource; + NvU32 gpuTimingSlaves[NV_P2060_MAX_MOSAIC_SLAVES]; + NvU32 slaveGpuCount; + NvBool enabledMosaic; + } MosaicGroup[NV_P2060_MAX_MOSAIC_GROUPS]; +}; + +PDACEXTERNALDEVICE extdevConstruct_P2060 (OBJGPU *, PDACEXTERNALDEVICE); +NvBool gsyncAttachExternalDevice_P2060 (OBJGPU *, PDACEXTERNALDEVICE*); +void extdevDestroy_P2060 (OBJGPU *, PDACEXTERNALDEVICE); +NvBool extdevGetDevice_P2060 (OBJGPU *, PDACEXTERNALDEVICE); +NvBool extdevInit_P2060 (OBJGPU *, PDACEXTERNALDEVICE); +void extdevDestroy_P2060 (OBJGPU *, PDACEXTERNALDEVICE); +void extdevService_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU8, NvU8, NvU8, NvBool); +NV_STATUS extdevWatchdog_P2060 (OBJGPU *, OBJTMR *, PDACEXTERNALDEVICE); // OBJTMR routine signature (TIMERPROC). +NvBool extdevSaveI2cHandles_P2060 (OBJGPU *, DACEXTERNALDEVICE *); +NV_STATUS gsyncFindGpuHandleLocation (DACEXTERNALDEVICE *, NvU32 , NvU32 *); + +// P2060 hal ifaces + +NvBool gsyncGpuCanBeMaster_P2060 (OBJGPU *, PDACEXTERNALDEVICE); +NV_STATUS gsyncGetSyncPolarity_P2060 (OBJGPU *, PDACEXTERNALDEVICE, GSYNCSYNCPOLARITY *); +NV_STATUS gsyncSetSyncPolarity_P2060 (OBJGPU *, PDACEXTERNALDEVICE, GSYNCSYNCPOLARITY); +NV_STATUS gsyncGetVideoMode_P2060 (OBJGPU *, PDACEXTERNALDEVICE, GSYNCVIDEOMODE *); +NV_STATUS gsyncSetVideoMode_P2060 (OBJGPU *, PDACEXTERNALDEVICE, GSYNCVIDEOMODE); +NV_STATUS gsyncGetNSync_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32 *); +NV_STATUS gsyncSetNSync_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32); +NV_STATUS gsyncGetSyncSkew_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32 *); +NV_STATUS gsyncSetSyncSkew_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32); +NV_STATUS gsyncGetUseHouse_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32 *); +NV_STATUS gsyncSetUseHouse_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32); +NV_STATUS gsyncGetSyncStartDelay_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32 *); +NV_STATUS gsyncSetSyncStartDelay_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32); +NV_STATUS gsyncRefSignal_P2060 (OBJGPU *, PDACEXTERNALDEVICE, REFTYPE, GSYNCSYNCSIGNAL, NvBool bRate, NvU32 *); +NV_STATUS gsyncRefMaster_P2060 (OBJGPU *, PDACEXTERNALDEVICE, REFTYPE, NvU32 *DisplayMask, NvU32 *Refresh, NvBool retainMaster, NvBool skipSwapBarrierWar); +NV_STATUS gsyncRefSlaves_P2060 (OBJGPU *, PDACEXTERNALDEVICE, REFTYPE, NvU32 *DisplayMask_s, NvU32 *Refresh); +NV_STATUS gsyncGetCplStatus_P2060 (OBJGPU *, PDACEXTERNALDEVICE, GSYNCSTATUS, NvU32 *); +NV_STATUS gsyncGetEmitTestSignal_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32 *); +NV_STATUS gsyncSetEmitTestSignal_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32); +NV_STATUS gsyncGetInterlaceMode_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32 *); +NV_STATUS gsyncSetInterlaceMode_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32); +NV_STATUS gsyncRefSwapBarrier_P2060 (OBJGPU *, PDACEXTERNALDEVICE, REFTYPE, NvBool *); +NV_STATUS gsyncGetWatchdog_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32 *); +NV_STATUS gsyncSetWatchdog_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32); +NV_STATUS gsyncGetRevision_P2060 (OBJGPU *, PDACEXTERNALDEVICE, GSYNCCAPSPARAMS *); +NV_STATUS gsyncOptimizeTimingParameters_P2060(OBJGPU *, GSYNCTIMINGPARAMS *); +NV_STATUS gsyncGetStereoLockMode_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32 *); +NV_STATUS gsyncSetStereoLockMode_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32); +NV_STATUS gsyncSetMosaic_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS *); +NV_STATUS gsyncConfigFlashGsync_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32); + +#endif diff --git a/src/nvidia/inc/kernel/gpu/external_device/dac_p2061.h b/src/nvidia/inc/kernel/gpu/external_device/dac_p2061.h new file mode 100644 index 000000000..b3c728045 --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/external_device/dac_p2061.h @@ -0,0 +1,35 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef DAC_P2061_H +#define DAC_P2061_H + +/* ------------------------ Macros & Defines ------------------------------- */ +// P2061 uses P2060's object. + +// P2061 hal ifaces +NV_STATUS gsyncGetHouseSyncMode_P2061 (OBJGPU *, PDACEXTERNALDEVICE, NvU8*); +NV_STATUS gsyncSetHouseSyncMode_P2061 (OBJGPU *, PDACEXTERNALDEVICE, NvU8); +NV_STATUS gsyncGetCplStatus_P2061 (OBJGPU *, PDACEXTERNALDEVICE, GSYNCSTATUS, NvU32 *); + +#endif // DAC_P2061_H diff --git a/src/nvidia/inc/kernel/gpu/external_device/external_device.h b/src/nvidia/inc/kernel/gpu/external_device/external_device.h new file mode 100644 index 000000000..b72a34cdd --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/external_device/external_device.h @@ -0,0 +1,132 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef EXTDEV_H_ +#define EXTDEV_H_ + +/* ------------------------ Includes --------------------------------------- */ +#include "Nvcm.h" +#include "sweng/dispsw.h" + +/* ------------------------ Types definitions ------------------------------ */ +typedef struct DACEXTERNALDEVICE DACEXTERNALDEVICE, *PDACEXTERNALDEVICE; +typedef struct DACEXTERNALDEVICEIFACE DACEXTERNALDEVICEIFACE, *PDACEXTERNALDEVICEIFACE; +typedef struct DACP2060EXTERNALDEVICE DACP2060EXTERNALDEVICE, *PDACP2060EXTERNALDEVICE; + +typedef enum _DAC_EXTERNAL_DEVICES +{ + DAC_EXTERNAL_DEVICE_NONE = 0, + DAC_EXTERNAL_DEVICE_P2060 = 0x2060, // NV30F1_CTRL_GSYNC_GET_CAPS_BOARD_ID_P2060 + DAC_EXTERNAL_DEVICE_P2061 = 0x2061, // NV30F1_CTRL_GSYNC_GET_CAPS_BOARD_ID_P2060 +} DAC_EXTERNAL_DEVICES; + +typedef enum _DAC_EXTERNAL_DEVICE_FPGA_REVS +{ + DAC_EXTERNAL_DEVICE_REV_0, + DAC_EXTERNAL_DEVICE_REV_1, + DAC_EXTERNAL_DEVICE_REV_2, + DAC_EXTERNAL_DEVICE_REV_3, + DAC_EXTERNAL_DEVICE_REV_4, + DAC_EXTERNAL_DEVICE_REV_5, + DAC_EXTERNAL_DEVICE_REV_6, + DAC_EXTERNAL_DEVICE_REV_7, + DAC_EXTERNAL_DEVICE_REV_MAX, + DAC_EXTERNAL_DEVICE_REV_NONE, +} DAC_EXTERNAL_DEVICE_REVS; + +typedef enum _DAC_EXTDEV_ACTIONS +{ + GET, + SET, +} DAC_EXTDEV_ACTIONS; + +// +// Not super-sure how "ExternalDevice" fits in with the model vs. say an +// external display encoder (tv, digital, DAC, etc). But perhaps those would +// instantiate one of these guys to become the "CommandChannel". As in an +// external display encoder would "know about" its associated ExternalDevice +// and use it to communicate... later... for now ExternalDevice is the base +// class for the extension boards. +// + +struct DACEXTERNALDEVICEIFACE +{ + NvBool (*GetDevice) (OBJGPU *, PDACEXTERNALDEVICE); // = 0 ( Pure virtual ) + NvBool (*Init) (OBJGPU *, PDACEXTERNALDEVICE); // = 0 ( Pure virtual ) + void (*Destroy) (OBJGPU *, PDACEXTERNALDEVICE); + NvBool (*Attach) (OBJGPU *, PDACEXTERNALDEVICE *); + NvBool (*Validate) (OBJGPU *, PDACEXTERNALDEVICE); // check if the config is valid + + void (*SetMode) (OBJGPU *, PDACEXTERNALDEVICE, NvU32); + + NvBool (*SetupVblankService)(OBJGPU *, PDACEXTERNALDEVICE, NvU32, NvBool); + void (*Service) (OBJGPU *, PDACEXTERNALDEVICE, NvU8, NvU8, NvU8, NvBool); + NV_STATUS (*Watchdog) (OBJGPU *, struct OBJTMR *, PDACEXTERNALDEVICE); // OBJTMR routine signature (TIMERPROC). + NvBool (*setI2cHandles)(OBJGPU *, DACEXTERNALDEVICE *); +}; + +struct DACEXTERNALDEVICE +{ + DACEXTERNALDEVICEIFACE *pI; + + NvU32 ReferenceCount; + + NvU8 I2CAddr; + NvU32 I2CPort; + NvU32 MaxGpus; + + NvU8 revId; + DAC_EXTERNAL_DEVICES deviceId; + DAC_EXTERNAL_DEVICE_REVS deviceRev; //device revision, also known as firmware major version + NvU8 deviceExRev; //device extended revision, also known as firmware minor version + + struct { + NvBool Scheduled; + NvU32 TimeOut; + } WatchdogControl; +}; + +typedef PDACEXTERNALDEVICE (*pfextdevConstruct) (OBJGPU *, PDACEXTERNALDEVICE); + +/* ------------------------ Macros & Defines ------------------------------- */ +#define NV_P2060_MIN_REV 0x2 + +void extdevGetBoundHeadsAndDisplayIds(OBJGPU *, NvU32 *); +PDACEXTERNALDEVICE extdevConstruct_Base (OBJGPU *, PDACEXTERNALDEVICE); +void extdevDestroy_Base (OBJGPU *, PDACEXTERNALDEVICE); +NvBool extdevValidate_Default (OBJGPU *, PDACEXTERNALDEVICE); +void extdevInvalidate_Default(OBJGPU *, PDACEXTERNALDEVICE); + +NV_STATUS i2c_extdeviceHelper(OBJGPU *, DACEXTERNALDEVICE *, NvU32, NvU8, NvU8 *,NvBool); +NV_STATUS writeregu008_extdevice(OBJGPU *, PDACEXTERNALDEVICE, NvU8, NvU8); +NV_STATUS writeregu008_extdeviceTargeted(OBJGPU *, PDACEXTERNALDEVICE, NvU8, NvU8); +NV_STATUS readregu008_extdevice(OBJGPU *, PDACEXTERNALDEVICE, NvU8, NvU8*); +NV_STATUS readregu008_extdeviceTargeted(OBJGPU *, PDACEXTERNALDEVICE, NvU8, NvU8*); + +void extdevDestroy (OBJGPU *); +NV_STATUS extdevScheduleWatchdog(OBJGPU *, PDACEXTERNALDEVICE); +NV_STATUS extdevCancelWatchdog (OBJGPU *, PDACEXTERNALDEVICE); +NV_STATUS extdevServiceWatchdog (OBJGPU *, struct OBJTMR *, void *); // OBJTMR routine signature (TIMERPROC). +void extdevGsyncService(OBJGPU *, NvU8, NvU8, NvU8, NvBool); + +#endif diff --git a/src/nvidia/inc/kernel/gpu/external_device/gsync.h b/src/nvidia/inc/kernel/gpu/external_device/gsync.h new file mode 100644 index 000000000..992b32eda --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/external_device/gsync.h @@ -0,0 +1,3 @@ + +#include "g_gsync_nvoc.h" + diff --git a/src/nvidia/inc/kernel/gpu/external_device/gsync_api.h b/src/nvidia/inc/kernel/gpu/external_device/gsync_api.h new file mode 100644 index 000000000..8de108606 --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/external_device/gsync_api.h @@ -0,0 +1,3 @@ + +#include "g_gsync_api_nvoc.h" + diff --git a/src/nvidia/inc/kernel/gpu/gpu_acpi_data.h b/src/nvidia/inc/kernel/gpu/gpu_acpi_data.h new file mode 100644 index 000000000..762276424 --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/gpu_acpi_data.h @@ -0,0 +1,107 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _GPU_ACPI_DATA_H_ +#define _GPU_ACPI_DATA_H_ + +#include "ctrl/ctrl0073/ctrl0073system.h" + +#include "nvctassert.h" +#include "acpigenfuncs.h" +#include "nvstatus.h" +#include "gpu/gpu_halspec.h" + +#define MAX_DSM_SUPPORTED_FUNCS_RTN_LEN 8 // # bytes to store supported functions + +typedef struct { + // supported function status and cache + NvU32 suppFuncStatus; + NvU8 suppFuncs[MAX_DSM_SUPPORTED_FUNCS_RTN_LEN]; + NvU32 suppFuncsLen; + NvBool bArg3isInteger; + // callback status and cache + NvU32 callbackStatus; + NvU32 callback; +} ACPI_DSM_CACHE; + +typedef struct { + + ACPI_DSM_CACHE dsm[ACPI_DSM_FUNCTION_COUNT]; + ACPI_DSM_FUNCTION dispStatusHotplugFunc; + ACPI_DSM_FUNCTION dispStatusConfigFunc; + ACPI_DSM_FUNCTION perfPostPowerStateFunc; + ACPI_DSM_FUNCTION stereo3dStateActiveFunc; + NvU32 dsmPlatCapsCache[ACPI_DSM_FUNCTION_COUNT]; + NvU32 MDTLFeatureSupport; + + // cache of generic func/subfunction remappings. + ACPI_DSM_FUNCTION dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_COUNT]; + NvU32 dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_COUNT]; + NvU32 dsmCurrentFuncSupport; + +} ACPI_DATA; + +typedef struct DOD_METHOD_DATA +{ + NV_STATUS status; + NvU32 acpiIdListLen; + NvU32 acpiIdList[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS]; +} DOD_METHOD_DATA; + +typedef struct JT_METHOD_DATA +{ + NV_STATUS status; + NvU16 jtRevId; + NvU32 jtCaps; +} JT_METHOD_DATA; + +typedef struct MUX_METHOD_DATA_ELEMENT +{ + NvU32 acpiId; + NvU32 mode; + NV_STATUS status; +} MUX_METHOD_DATA_ELEMENT; + +typedef struct MUX_METHOD_DATA +{ + NvU32 tableLen; + MUX_METHOD_DATA_ELEMENT acpiIdMuxModeTable[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS]; + MUX_METHOD_DATA_ELEMENT acpiIdMuxPartTable[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS]; +} MUX_METHOD_DATA; + +typedef struct CAPS_METHOD_DATA +{ + NV_STATUS status; + NvU32 optimusCaps; +} CAPS_METHOD_DATA; + +typedef struct ACPI_METHOD_DATA +{ + NvBool bValid; + DOD_METHOD_DATA dodMethodData; + JT_METHOD_DATA jtMethodData; + MUX_METHOD_DATA muxMethodData; + CAPS_METHOD_DATA capsMethodData; +} ACPI_METHOD_DATA; + +#endif // _GPU_ACPI_DATA_H_ diff --git a/src/nvidia/inc/kernel/gpu/gpu_child_list.h b/src/nvidia/inc/kernel/gpu/gpu_child_list.h index 30757c54c..632013158 100644 --- a/src/nvidia/inc/kernel/gpu/gpu_child_list.h +++ b/src/nvidia/inc/kernel/gpu/gpu_child_list.h @@ -94,7 +94,7 @@ GPU_CHILD_SINGLE_INST( OBJHSHUBMANAGER, GPU_GET_HSHUBMANAGER, 1, NV_FALSE, NV_FALSE, pHshMgr ) #endif #if GPU_CHILD_MODULE(HSHUB) - GPU_CHILD_MULTI_INST ( OBJHSHUB, GPU_GET_HSHUB, GPU_MAX_HSHUBS, NV_FALSE, NV_FALSE, pHshub ) + GPU_CHILD_MULTI_INST ( Hshub, GPU_GET_HSHUB, GPU_MAX_HSHUBS, NV_FALSE, NV_FALSE, pHshub ) #endif #if GPU_CHILD_MODULE(SEQ) GPU_CHILD_SINGLE_INST( OBJSEQ, GPU_GET_SEQ, 1, NV_FALSE, NV_TRUE, pSeq ) @@ -157,7 +157,7 @@ GPU_CHILD_SINGLE_INST( ClockManager, GPU_GET_CLK_MGR, 1, NV_FALSE, NV_FALSE, pClk ) #endif #if GPU_CHILD_MODULE(FAN) - GPU_CHILD_SINGLE_INST( OBJFAN, GPU_GET_FAN, 1, NV_FALSE, NV_FALSE, pFan ) + GPU_CHILD_SINGLE_INST( Fan, GPU_GET_FAN, 1, NV_FALSE, NV_FALSE, pFan ) #endif #if GPU_CHILD_MODULE(PERF) GPU_CHILD_SINGLE_INST( Perf, GPU_GET_PERF, 1, NV_FALSE, NV_FALSE, pPerf ) @@ -187,7 +187,7 @@ GPU_CHILD_SINGLE_INST( OBJVOLT, GPU_GET_VOLT, 1, NV_FALSE, NV_FALSE, pVolt ) #endif #if GPU_CHILD_MODULE(I2C) - GPU_CHILD_SINGLE_INST( OBJI2C, GPU_GET_I2C, 1, NV_FALSE, NV_TRUE, pI2c ) + GPU_CHILD_SINGLE_INST( I2c, GPU_GET_I2C, 1, NV_FALSE, NV_TRUE, pI2c ) #endif #if GPU_CHILD_MODULE(SPI) GPU_CHILD_SINGLE_INST( Spi, GPU_GET_SPI, 1, NV_FALSE, NV_TRUE, pSpi ) diff --git a/src/nvidia/inc/kernel/gpu/gpu_device_mapping.h b/src/nvidia/inc/kernel/gpu/gpu_device_mapping.h index 1a1835088..53bdc1c55 100644 --- a/src/nvidia/inc/kernel/gpu/gpu_device_mapping.h +++ b/src/nvidia/inc/kernel/gpu/gpu_device_mapping.h @@ -48,7 +48,7 @@ typedef enum SOC_DEV_MAPPING_DPAUX1, // Update NV_MAX_SOC_DPAUX_NUM_DEVICES if adding new DPAUX mappings SOC_DEV_MAPPING_HDACODEC, SOC_DEV_MAPPING_MIPICAL, - SOC_DEV_MAPPING_MAX // Keep this as last entry + SOC_DEV_MAPPING_MAX } SOC_DEV_MAPPING; #define GPU_MAX_DEVICE_MAPPINGS (60) diff --git a/src/nvidia/inc/kernel/gpu/gpu_engine_type.h b/src/nvidia/inc/kernel/gpu/gpu_engine_type.h new file mode 100644 index 000000000..d91daab95 --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/gpu_engine_type.h @@ -0,0 +1,137 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _GPU_ENGINE_TYPE_H_ +#define _GPU_ENGINE_TYPE_H_ + +#include "class/cl2080.h" +#include "nvrangetypes.h" +#include "utils/nvbitvector.h" + +typedef enum +{ + RM_ENGINE_TYPE_NULL = (0x00000000), + RM_ENGINE_TYPE_GR0 = (0x00000001), + RM_ENGINE_TYPE_GR1 = (0x00000002), + RM_ENGINE_TYPE_GR2 = (0x00000003), + RM_ENGINE_TYPE_GR3 = (0x00000004), + RM_ENGINE_TYPE_GR4 = (0x00000005), + RM_ENGINE_TYPE_GR5 = (0x00000006), + RM_ENGINE_TYPE_GR6 = (0x00000007), + RM_ENGINE_TYPE_GR7 = (0x00000008), + RM_ENGINE_TYPE_COPY0 = (0x00000009), + RM_ENGINE_TYPE_COPY1 = (0x0000000a), + RM_ENGINE_TYPE_COPY2 = (0x0000000b), + RM_ENGINE_TYPE_COPY3 = (0x0000000c), + RM_ENGINE_TYPE_COPY4 = (0x0000000d), + RM_ENGINE_TYPE_COPY5 = (0x0000000e), + RM_ENGINE_TYPE_COPY6 = (0x0000000f), + RM_ENGINE_TYPE_COPY7 = (0x00000010), + RM_ENGINE_TYPE_COPY8 = (0x00000011), + RM_ENGINE_TYPE_COPY9 = (0x00000012), + RM_ENGINE_TYPE_NVDEC0 = (0x0000001d), + RM_ENGINE_TYPE_NVDEC1 = (0x0000001e), + RM_ENGINE_TYPE_NVDEC2 = (0x0000001f), + RM_ENGINE_TYPE_NVDEC3 = (0x00000020), + RM_ENGINE_TYPE_NVDEC4 = (0x00000021), + RM_ENGINE_TYPE_NVDEC5 = (0x00000022), + RM_ENGINE_TYPE_NVDEC6 = (0x00000023), + RM_ENGINE_TYPE_NVDEC7 = (0x00000024), + RM_ENGINE_TYPE_NVENC0 = (0x00000025), + RM_ENGINE_TYPE_NVENC1 = (0x00000026), + RM_ENGINE_TYPE_NVENC2 = (0x00000027), + RM_ENGINE_TYPE_VP = (0x00000028), + RM_ENGINE_TYPE_ME = (0x00000029), + RM_ENGINE_TYPE_PPP = (0x0000002a), + RM_ENGINE_TYPE_MPEG = (0x0000002b), + RM_ENGINE_TYPE_SW = (0x0000002c), + RM_ENGINE_TYPE_TSEC = (0x0000002d), + RM_ENGINE_TYPE_VIC = (0x0000002e), + RM_ENGINE_TYPE_MP = (0x0000002f), + RM_ENGINE_TYPE_SEC2 = (0x00000030), + RM_ENGINE_TYPE_HOST = (0x00000031), + RM_ENGINE_TYPE_DPU = (0x00000032), + RM_ENGINE_TYPE_PMU = (0x00000033), + RM_ENGINE_TYPE_FBFLCN = (0x00000034), + RM_ENGINE_TYPE_NVJPEG0 = (0x00000035), + RM_ENGINE_TYPE_NVJPEG1 = (0x00000036), + RM_ENGINE_TYPE_NVJPEG2 = (0x00000037), + RM_ENGINE_TYPE_NVJPEG3 = (0x00000038), + RM_ENGINE_TYPE_NVJPEG4 = (0x00000039), + RM_ENGINE_TYPE_NVJPEG5 = (0x0000003a), + RM_ENGINE_TYPE_NVJPEG6 = (0x0000003b), + RM_ENGINE_TYPE_NVJPEG7 = (0x0000003c), + RM_ENGINE_TYPE_OFA = (0x0000003d), + RM_ENGINE_TYPE_LAST = (0x0000003e), +} RM_ENGINE_TYPE; + +// +// The duplicates in the RM_ENGINE_TYPE. Using define instead of putting them +// in the enum to make sure that each item in the enum has a unique number. +// +#define RM_ENGINE_TYPE_GRAPHICS RM_ENGINE_TYPE_GR0 +#define RM_ENGINE_TYPE_BSP RM_ENGINE_TYPE_NVDEC0 +#define RM_ENGINE_TYPE_MSENC RM_ENGINE_TYPE_NVENC0 +#define RM_ENGINE_TYPE_CIPHER RM_ENGINE_TYPE_TSEC +#define RM_ENGINE_TYPE_NVJPG RM_ENGINE_TYPE_NVJPEG0 + +#define RM_ENGINE_TYPE_COPY_SIZE 10 +#define RM_ENGINE_TYPE_NVENC_SIZE 3 +#define RM_ENGINE_TYPE_NVJPEG_SIZE 8 +#define RM_ENGINE_TYPE_NVDEC_SIZE 8 +#define RM_ENGINE_TYPE_GR_SIZE 8 + +// Indexed engines +#define RM_ENGINE_TYPE_COPY(i) (RM_ENGINE_TYPE_COPY0+(i)) +#define RM_ENGINE_TYPE_IS_COPY(i) (((i) >= RM_ENGINE_TYPE_COPY0) && ((i) < RM_ENGINE_TYPE_COPY(RM_ENGINE_TYPE_COPY_SIZE))) +#define RM_ENGINE_TYPE_COPY_IDX(i) ((i) - RM_ENGINE_TYPE_COPY0) + +#define RM_ENGINE_TYPE_NVENC(i) (RM_ENGINE_TYPE_NVENC0+(i)) +#define RM_ENGINE_TYPE_IS_NVENC(i) (((i) >= RM_ENGINE_TYPE_NVENC0) && ((i) < RM_ENGINE_TYPE_NVENC(RM_ENGINE_TYPE_NVENC_SIZE))) +#define RM_ENGINE_TYPE_NVENC_IDX(i) ((i) - RM_ENGINE_TYPE_NVENC0) + +#define RM_ENGINE_TYPE_NVDEC(i) (RM_ENGINE_TYPE_NVDEC0+(i)) +#define RM_ENGINE_TYPE_IS_NVDEC(i) (((i) >= RM_ENGINE_TYPE_NVDEC0) && ((i) < RM_ENGINE_TYPE_NVDEC(RM_ENGINE_TYPE_NVDEC_SIZE))) +#define RM_ENGINE_TYPE_NVDEC_IDX(i) ((i) - RM_ENGINE_TYPE_NVDEC0) + +#define RM_ENGINE_TYPE_NVJPEG(i) (RM_ENGINE_TYPE_NVJPEG0+(i)) +#define RM_ENGINE_TYPE_IS_NVJPEG(i) (((i) >= RM_ENGINE_TYPE_NVJPEG0) && ((i) < RM_ENGINE_TYPE_NVJPEG(RM_ENGINE_TYPE_NVJPEG_SIZE))) +#define RM_ENGINE_TYPE_NVJPEG_IDX(i) ((i) - RM_ENGINE_TYPE_NVJPEG0) + +#define RM_ENGINE_TYPE_GR(i) (RM_ENGINE_TYPE_GR0 + (i)) +#define RM_ENGINE_TYPE_IS_GR(i) (((i) >= RM_ENGINE_TYPE_GR0) && ((i) < RM_ENGINE_TYPE_GR(RM_ENGINE_TYPE_GR_SIZE))) +#define RM_ENGINE_TYPE_GR_IDX(i) ((i) - RM_ENGINE_TYPE_GR0) + +#define RM_ENGINE_TYPE_IS_VALID(i) (((i) > (RM_ENGINE_TYPE_NULL)) && ((i) < (RM_ENGINE_TYPE_LAST))) + +// Engine Range defines +#define RM_ENGINE_RANGE_GR() rangeMake(RM_ENGINE_TYPE_GR(0), RM_ENGINE_TYPE_GR(RM_ENGINE_TYPE_GR_SIZE - 1)) +#define RM_ENGINE_RANGE_COPY() rangeMake(RM_ENGINE_TYPE_COPY(0), RM_ENGINE_TYPE_COPY(RM_ENGINE_TYPE_COPY_SIZE - 1)) +#define RM_ENGINE_RANGE_NVDEC() rangeMake(RM_ENGINE_TYPE_NVDEC(0), RM_ENGINE_TYPE_NVDEC(RM_ENGINE_TYPE_NVDEC_SIZE - 1)) +#define RM_ENGINE_RANGE_NVENC() rangeMake(RM_ENGINE_TYPE_NVENC(0), RM_ENGINE_TYPE_NVENC(RM_ENGINE_TYPE_NVENC_SIZE - 1)) +#define RM_ENGINE_RANGE_NVJPEG() rangeMake(RM_ENGINE_TYPE_NVJPEG(0), RM_ENGINE_TYPE_NVJPEG(RM_ENGINE_TYPE_NVJPEG_SIZE - 1)) + +// Bit Vectors +MAKE_BITVECTOR(ENGTYPE_BIT_VECTOR, RM_ENGINE_TYPE_LAST); + +#endif //_GPU_ENGINE_TYPE_H_ diff --git a/src/nvidia/inc/kernel/gpu/gpu_fabric_probe.h b/src/nvidia/inc/kernel/gpu/gpu_fabric_probe.h new file mode 100644 index 000000000..880355394 --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/gpu_fabric_probe.h @@ -0,0 +1,60 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef GPU_FABRIC_PROBE_H +#define GPU_FABRIC_PROBE_H + + +#include "nvlink_inband_msg.h" + +#define GPU_FABRIC_PROBE_SEC_TO_NS 1000000000ULL + +#define GPU_FABRIC_PROBE_DEFAULT_DELAY 5 // 5 seconds + +#define GPU_FABRIC_PROBE_DEFAULT_PROBE_SLOWDOWN_THRESHOLD 10 + +typedef struct GPU_FABRIC_PROBE_INFO GPU_FABRIC_PROBE_INFO; + +NV_STATUS gpuFabricProbeStart(OBJGPU *pGpu, + GPU_FABRIC_PROBE_INFO **ppGpuFabricProbeInfo); +void gpuFabricProbeStop(GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo); + +void gpuFabricProbeSuspend(GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo); +NV_STATUS gpuFabricProbeResume(GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo); + +NV_STATUS gpuFabricProbeGetGpuFabricHandle(GPU_FABRIC_PROBE_INFO *pInfo, NvU64 *pHandle); +NV_STATUS gpuFabricProbeGetGfId(GPU_FABRIC_PROBE_INFO *pInfo, NvU32 *pGfId); +NV_STATUS gpuFabricProbeGetfmCaps(GPU_FABRIC_PROBE_INFO *pInfo, NvU64 *pFmCaps); +NV_STATUS gpuFabricProbeGetClusterUuid(GPU_FABRIC_PROBE_INFO *pInfo, NvUuid *pClusterUuid); +NV_STATUS gpuFabricProbeGetFabricPartitionId(GPU_FABRIC_PROBE_INFO *pInfo, NvU16 *pFabricPartitionId); +NV_STATUS gpuFabricProbeGetGpaAddress(GPU_FABRIC_PROBE_INFO *pInfo, NvU64 *pGpaAddress); +NV_STATUS gpuFabricProbeGetGpaAddressRange(GPU_FABRIC_PROBE_INFO *pInfo, NvU64 *pGpaAddressRange); +NV_STATUS gpuFabricProbeGetFlaAddress(GPU_FABRIC_PROBE_INFO *pInfo, NvU64 *pFlaAddress); +NV_STATUS gpuFabricProbeGetFlaAddressRange(GPU_FABRIC_PROBE_INFO *pInfo, NvU64 *pFlaAddressRange); +NV_STATUS gpuFabricProbeGetNumProbeReqs(GPU_FABRIC_PROBE_INFO *pInfo, NvU64 *numProbes); + +NvBool gpuFabricProbeIsReceived(GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo); +NvBool gpuFabricProbeIsSuccess(GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo); +NV_STATUS gpuFabricProbeGetFmStatus(GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo); +NvBool gpuFabricProbeIsSupported(OBJGPU *pGpu); +#endif // GPU_FABRIC_PROBE_H diff --git a/src/nvidia/inc/kernel/gpu/gpu_shared_data_map.h b/src/nvidia/inc/kernel/gpu/gpu_shared_data_map.h new file mode 100644 index 000000000..817b1ef23 --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/gpu_shared_data_map.h @@ -0,0 +1,50 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef GPU_SHARED_DATA_MAP_H +#define GPU_SHARED_DATA_MAP_H + +#include "core/core.h" +#include "gpu/mem_mgr/mem_desc.h" +#include "class/cl00de.h" + +// **************************************************************************** +// Type definitions +// **************************************************************************** + +typedef struct GpuSharedDataMap { + MEMORY_DESCRIPTOR *pMemDesc; + NvP64 pMapBuffer; + NvP64 pMapBufferPriv; + NvU32 processId; + + NV00DE_SHARED_DATA data; +} GpuSharedDataMap; + +// Start data write, returns data struct to write into +NV00DE_SHARED_DATA * gpushareddataWriteStart(OBJGPU *pGpu); +// Finish data write, pushes data cached by above into mapped data +void gpushareddataWriteFinish(OBJGPU *pGpu); + +#endif /* GPU_SHARED_DATA_MAP_H */ + diff --git a/src/nvidia/inc/kernel/gpu/gpu_user_shared_data.h b/src/nvidia/inc/kernel/gpu/gpu_user_shared_data.h new file mode 100644 index 000000000..c4e476322 --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/gpu_user_shared_data.h @@ -0,0 +1,3 @@ + +#include "g_gpu_user_shared_data_nvoc.h" + diff --git a/src/nvidia/inc/kernel/gpu/gr/kernel_graphics_context_buffers.h b/src/nvidia/inc/kernel/gpu/gr/kernel_graphics_context_buffers.h new file mode 100644 index 000000000..60ed630f1 --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/gr/kernel_graphics_context_buffers.h @@ -0,0 +1,66 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef KERNEL_GRAPHICS_CONTEXT_BUFFERS_H +#define KERNEL_GRAPHICS_CONTEXT_BUFFERS_H + +#include "utils/nv_enum.h" + +/* + * Global buffer types. These are shared between contexts + * each PF/VF context normally. A GraphicsContext may have + * a private allocation for security (VPR) or when + * graphics preemption is enabled. + * + * Not all buffer types are supported on every GPU. + */ +#define GR_GLOBALCTX_BUFFER_DEF(x) \ + NV_ENUM_ENTRY(x, GR_GLOBALCTX_BUFFER_BUNDLE_CB, 0x00000000) \ + NV_ENUM_ENTRY(x, GR_GLOBALCTX_BUFFER_PAGEPOOL, 0x00000001) \ + NV_ENUM_ENTRY(x, GR_GLOBALCTX_BUFFER_ATTRIBUTE_CB, 0x00000002) \ + NV_ENUM_ENTRY(x, GR_GLOBALCTX_BUFFER_RTV_CB, 0x00000003) \ + NV_ENUM_ENTRY(x, GR_GLOBALCTX_BUFFER_GFXP_POOL, 0x00000004) \ + NV_ENUM_ENTRY(x, GR_GLOBALCTX_BUFFER_GFXP_CTRL_BLK, 0x00000005) \ + NV_ENUM_ENTRY(x, GR_GLOBALCTX_BUFFER_FECS_EVENT, 0x00000006) \ + NV_ENUM_ENTRY(x, GR_GLOBALCTX_BUFFER_PRIV_ACCESS_MAP, 0x00000007) \ + NV_ENUM_ENTRY(x, GR_GLOBALCTX_BUFFER_UNRESTRICTED_PRIV_ACCESS_MAP, 0x00000008) \ + NV_ENUM_ENTRY(x, GR_GLOBAL_BUFFER_GLOBAL_PRIV_ACCESS_MAP, 0x00000009) + +NV_ENUM_DEF(GR_GLOBALCTX_BUFFER, GR_GLOBALCTX_BUFFER_DEF) +#define GR_GLOBALCTX_BUFFER_COUNT NV_ENUM_SIZE(GR_GLOBALCTX_BUFFER) + + +#define GR_CTX_BUFFER_DEF(x) \ + NV_ENUM_ENTRY(x, GR_CTX_BUFFER_MAIN, 0x00000000) \ + NV_ENUM_ENTRY(x, GR_CTX_BUFFER_ZCULL, 0x00000001) \ + NV_ENUM_ENTRY(x, GR_CTX_BUFFER_PM, 0x00000002) \ + NV_ENUM_ENTRY(x, GR_CTX_BUFFER_PREEMPT, 0x00000003) \ + NV_ENUM_ENTRY(x, GR_CTX_BUFFER_SPILL, 0x00000004) \ + NV_ENUM_ENTRY(x, GR_CTX_BUFFER_BETA_CB, 0x00000005) \ + NV_ENUM_ENTRY(x, GR_CTX_BUFFER_PAGEPOOL, 0x00000006) \ + NV_ENUM_ENTRY(x, GR_CTX_BUFFER_RTV_CB, 0x00000007) \ + NV_ENUM_ENTRY(x, GR_CTX_BUFFER_PATCH, 0x00000008) + +NV_ENUM_DEF(GR_CTX_BUFFER, GR_CTX_BUFFER_DEF) + +#endif // KERNEL_GRAPHICS_CONTEXT_BUFFERS_H diff --git a/src/nvidia/inc/kernel/gpu/gr/kernel_sm_debugger_exception.h b/src/nvidia/inc/kernel/gpu/gr/kernel_sm_debugger_exception.h new file mode 100644 index 000000000..25f313817 --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/gr/kernel_sm_debugger_exception.h @@ -0,0 +1,57 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef KERNEL_SM_DEBUGGER_EXCEPTION_H +#define KERNEL_SM_DEBUGGER_EXCEPTION_H + +#include "utils/nv_enum.h" +#include "nvctassert.h" +#include "nvmisc.h" + +#include "ctrl/ctrl83de.h" + +#define SMDBG_EXCEPTION_TYPE_DEF(x) \ + NV_ENUM_ENTRY(x, SMDBG_EXCEPTION_TYPE_FATAL, 0) \ + NV_ENUM_ENTRY(x, SMDBG_EXCEPTION_TYPE_TRAP, 1) \ + NV_ENUM_ENTRY(x, SMDBG_EXCEPTION_TYPE_SINGLE_STEP, 2) \ + NV_ENUM_ENTRY(x, SMDBG_EXCEPTION_TYPE_INT, 3) \ + NV_ENUM_ENTRY(x, SMDBG_EXCEPTION_TYPE_CILP, 4) \ + NV_ENUM_ENTRY(x, SMDBG_EXCEPTION_TYPE_PREEMPTION_STARTED, 5) + +NV_ENUM_DEF(SMDBG_EXCEPTION_TYPE, SMDBG_EXCEPTION_TYPE_DEF); +ct_assert(NV_ENUM_IS_CONTIGUOUS(SMDBG_EXCEPTION_TYPE)); + +ct_assert(NVBIT32(SMDBG_EXCEPTION_TYPE_FATAL) == + NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_FATAL); +ct_assert(NVBIT32(SMDBG_EXCEPTION_TYPE_TRAP) == + NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_TRAP); +ct_assert(NVBIT32(SMDBG_EXCEPTION_TYPE_SINGLE_STEP) == + NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_SINGLE_STEP); +ct_assert(NVBIT32(SMDBG_EXCEPTION_TYPE_INT) == + NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_INT); +ct_assert(NVBIT32(SMDBG_EXCEPTION_TYPE_CILP) == + NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_CILP); +ct_assert(NVBIT32(SMDBG_EXCEPTION_TYPE_PREEMPTION_STARTED) == + NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PREEMPTION_STARTED); + +#endif // KERNEL_SM_DEBUGGER_EXCEPTION_H diff --git a/src/nvidia/inc/kernel/gpu/gsp/gsp_init_args.h b/src/nvidia/inc/kernel/gpu/gsp/gsp_init_args.h index a0da69646..85f3d5c68 100644 --- a/src/nvidia/inc/kernel/gpu/gsp/gsp_init_args.h +++ b/src/nvidia/inc/kernel/gpu/gsp/gsp_init_args.h @@ -50,6 +50,7 @@ typedef struct { MESSAGE_QUEUE_INIT_ARGUMENTS messageQueueInitArguments; GSP_SR_INIT_ARGUMENTS srInitArguments; + NvU32 gpuInstance; } GSP_ARGUMENTS_CACHED; #endif // GSP_INIT_ARGS_H diff --git a/src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h b/src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h index e7767480d..816318b0f 100644 --- a/src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h +++ b/src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h @@ -35,11 +35,12 @@ #include "ctrl/ctrl2080/ctrl2080bios.h" #include "ctrl/ctrl2080/ctrl2080fb.h" #include "ctrl/ctrl2080/ctrl2080gpu.h" -#include "ctrl/ctrla083.h" #include "gpu/gpu.h" // COMPUTE_BRANDING_TYPE +#include "gpu/gpu_acpi_data.h" // ACPI_METHOD_DATA #include "vgpu/rpc_headers.h" // MAX_GPC_COUNT #include "platform/chipset/chipset.h" // BUSINFO +#include "gpu/nvbitmask.h" // NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX typedef struct GspSMInfo_t { @@ -69,7 +70,7 @@ typedef struct GspStaticConfigInfo_t NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS sriovCaps; NvU32 sriovMaxGfid; - NvU64 engineCaps; + NvU32 engineCaps[NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX]; GspSMInfo SM_info; @@ -96,6 +97,7 @@ typedef struct GspStaticConfigInfo_t NvBool bGeforceSmb; NvBool bIsTitan; NvBool bIsTesla; + NvBool bIsMobile; NvU64 bar1PdeBase; NvU64 bar2PdeBase; @@ -110,8 +112,8 @@ typedef struct GspStaticConfigInfo_t NvBool bClRootportNeedsNosnoopWAR; - NVA083_CTRL_VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS displaylessMaxHeads; - NVA083_CTRL_VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS displaylessMaxResolution; + VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS displaylessMaxHeads; + VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS displaylessMaxResolution; NvU64 displaylessMaxPixels; // Client handle for internal RMAPI control. @@ -142,7 +144,15 @@ typedef struct GspSystemInfo NvU8 oorArch; NvU64 clPdbProperties; NvU32 Chipset; + NvBool bGpuBehindBridge; + NvBool bUpstreamL0sUnsupported; + NvBool bUpstreamL1Unsupported; + NvBool bUpstreamL1PorSupported; + NvBool bUpstreamL1PorMobileOnly; + NvU8 upstreamAddressValid; BUSINFO FHBBusInfo; + BUSINFO chipsetIDInfo; + ACPI_METHOD_DATA acpiMethodData; } GspSystemInfo; diff --git a/src/nvidia/inc/kernel/gpu/intr/engine_idx.h b/src/nvidia/inc/kernel/gpu/intr/engine_idx.h index e4c616b0a..4f12aaab4 100644 --- a/src/nvidia/inc/kernel/gpu/intr/engine_idx.h +++ b/src/nvidia/inc/kernel/gpu/intr/engine_idx.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -44,99 +44,96 @@ #define MC_ENGINE_IDX_VIDEO 5 #define MC_ENGINE_IDX_MD 6 #define MC_ENGINE_IDX_BUS 7 -// UNUSED -#define MC_ENGINE_IDX_PMGR 9 -#define MC_ENGINE_IDX_VP2 10 -#define MC_ENGINE_IDX_CIPHER 11 -#define MC_ENGINE_IDX_BIF 12 -#define MC_ENGINE_IDX_PPP 13 -#define MC_ENGINE_IDX_PRIVRING 14 -#define MC_ENGINE_IDX_PMU 15 -#define MC_ENGINE_IDX_CE0 16 -#define MC_ENGINE_IDX_CE1 17 -#define MC_ENGINE_IDX_CE2 18 -#define MC_ENGINE_IDX_CE3 19 -#define MC_ENGINE_IDX_CE4 20 -#define MC_ENGINE_IDX_CE5 21 -#define MC_ENGINE_IDX_CE6 22 -#define MC_ENGINE_IDX_CE7 23 -#define MC_ENGINE_IDX_CE8 24 -#define MC_ENGINE_IDX_CE9 25 -#define MC_ENGINE_IDX_VIC 26 -#define MC_ENGINE_IDX_ISOHUB 27 -#define MC_ENGINE_IDX_VGPU 28 -#define MC_ENGINE_IDX_MSENC 29 -#define MC_ENGINE_IDX_MSENC1 30 -#define MC_ENGINE_IDX_MSENC2 31 -#define MC_ENGINE_IDX_C2C 32 -// UNUSED -#define MC_ENGINE_IDX_LTC 34 -#define MC_ENGINE_IDX_FBHUB 35 -#define MC_ENGINE_IDX_HDACODEC 36 -#define MC_ENGINE_IDX_GMMU 37 -#define MC_ENGINE_IDX_SEC2 38 -#define MC_ENGINE_IDX_FSP 39 -#define MC_ENGINE_IDX_NVLINK 40 -#define MC_ENGINE_IDX_GSP 41 -#define MC_ENGINE_IDX_NVJPG 42 +#define MC_ENGINE_IDX_PMGR 8 +#define MC_ENGINE_IDX_VP2 9 +#define MC_ENGINE_IDX_CIPHER 10 +#define MC_ENGINE_IDX_BIF 11 +#define MC_ENGINE_IDX_PPP 12 +#define MC_ENGINE_IDX_PRIVRING 13 +#define MC_ENGINE_IDX_PMU 14 +#define MC_ENGINE_IDX_CE0 15 +#define MC_ENGINE_IDX_CE1 16 +#define MC_ENGINE_IDX_CE2 17 +#define MC_ENGINE_IDX_CE3 18 +#define MC_ENGINE_IDX_CE4 19 +#define MC_ENGINE_IDX_CE5 20 +#define MC_ENGINE_IDX_CE6 21 +#define MC_ENGINE_IDX_CE7 22 +#define MC_ENGINE_IDX_CE8 23 +#define MC_ENGINE_IDX_CE9 24 +#define MC_ENGINE_IDX_VIC 35 +#define MC_ENGINE_IDX_ISOHUB 36 +#define MC_ENGINE_IDX_VGPU 37 +#define MC_ENGINE_IDX_MSENC 38 +#define MC_ENGINE_IDX_MSENC1 39 +#define MC_ENGINE_IDX_MSENC2 40 +#define MC_ENGINE_IDX_C2C 41 +#define MC_ENGINE_IDX_LTC 42 +#define MC_ENGINE_IDX_FBHUB 43 +#define MC_ENGINE_IDX_HDACODEC 44 +#define MC_ENGINE_IDX_GMMU 45 +#define MC_ENGINE_IDX_SEC2 46 +#define MC_ENGINE_IDX_FSP 47 +#define MC_ENGINE_IDX_NVLINK 48 +#define MC_ENGINE_IDX_GSP 49 +#define MC_ENGINE_IDX_NVJPG 50 #define MC_ENGINE_IDX_NVJPEG MC_ENGINE_IDX_NVJPG #define MC_ENGINE_IDX_NVJPEG0 MC_ENGINE_IDX_NVJPEG -#define MC_ENGINE_IDX_NVJPEG1 43 -#define MC_ENGINE_IDX_NVJPEG2 44 -#define MC_ENGINE_IDX_NVJPEG3 45 -#define MC_ENGINE_IDX_NVJPEG4 46 -#define MC_ENGINE_IDX_NVJPEG5 47 -#define MC_ENGINE_IDX_NVJPEG6 48 -#define MC_ENGINE_IDX_NVJPEG7 49 - -#define MC_ENGINE_IDX_REPLAYABLE_FAULT 50 -#define MC_ENGINE_IDX_ACCESS_CNTR 51 -#define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT 52 -#define MC_ENGINE_IDX_REPLAYABLE_FAULT_ERROR 53 -#define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT_ERROR 54 -#define MC_ENGINE_IDX_INFO_FAULT 55 -#define MC_ENGINE_IDX_BSP 56 +#define MC_ENGINE_IDX_NVJPEG1 51 +#define MC_ENGINE_IDX_NVJPEG2 52 +#define MC_ENGINE_IDX_NVJPEG3 53 +#define MC_ENGINE_IDX_NVJPEG4 54 +#define MC_ENGINE_IDX_NVJPEG5 55 +#define MC_ENGINE_IDX_NVJPEG6 56 +#define MC_ENGINE_IDX_NVJPEG7 57 +#define MC_ENGINE_IDX_REPLAYABLE_FAULT 58 +#define MC_ENGINE_IDX_ACCESS_CNTR 59 +#define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT 60 +#define MC_ENGINE_IDX_REPLAYABLE_FAULT_ERROR 61 +#define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT_ERROR 62 +#define MC_ENGINE_IDX_INFO_FAULT 63 +#define MC_ENGINE_IDX_BSP 64 #define MC_ENGINE_IDX_NVDEC MC_ENGINE_IDX_BSP #define MC_ENGINE_IDX_NVDEC0 MC_ENGINE_IDX_NVDEC -#define MC_ENGINE_IDX_NVDEC1 57 -#define MC_ENGINE_IDX_NVDEC2 58 -#define MC_ENGINE_IDX_NVDEC3 59 -#define MC_ENGINE_IDX_NVDEC4 60 -#define MC_ENGINE_IDX_NVDEC5 61 -#define MC_ENGINE_IDX_NVDEC6 62 -#define MC_ENGINE_IDX_NVDEC7 63 -#define MC_ENGINE_IDX_CPU_DOORBELL 64 -#define MC_ENGINE_IDX_PRIV_DOORBELL 65 -#define MC_ENGINE_IDX_MMU_ECC_ERROR 66 -#define MC_ENGINE_IDX_BLG 67 -#define MC_ENGINE_IDX_PERFMON 68 -#define MC_ENGINE_IDX_BUF_RESET 69 -#define MC_ENGINE_IDX_XBAR 70 -#define MC_ENGINE_IDX_ZPW 71 -#define MC_ENGINE_IDX_OFA0 72 -#define MC_ENGINE_IDX_TEGRA 73 -#define MC_ENGINE_IDX_GR 74 +#define MC_ENGINE_IDX_NVDEC1 65 +#define MC_ENGINE_IDX_NVDEC2 66 +#define MC_ENGINE_IDX_NVDEC3 67 +#define MC_ENGINE_IDX_NVDEC4 68 +#define MC_ENGINE_IDX_NVDEC5 69 +#define MC_ENGINE_IDX_NVDEC6 70 +#define MC_ENGINE_IDX_NVDEC7 71 +#define MC_ENGINE_IDX_CPU_DOORBELL 72 +#define MC_ENGINE_IDX_PRIV_DOORBELL 73 +#define MC_ENGINE_IDX_MMU_ECC_ERROR 74 +#define MC_ENGINE_IDX_BLG 75 +#define MC_ENGINE_IDX_PERFMON 76 +#define MC_ENGINE_IDX_BUF_RESET 77 +#define MC_ENGINE_IDX_XBAR 78 +#define MC_ENGINE_IDX_ZPW 79 +#define MC_ENGINE_IDX_OFA0 80 +#define MC_ENGINE_IDX_TEGRA 81 +#define MC_ENGINE_IDX_GR 82 #define MC_ENGINE_IDX_GR0 MC_ENGINE_IDX_GR -#define MC_ENGINE_IDX_GR1 75 -#define MC_ENGINE_IDX_GR2 76 -#define MC_ENGINE_IDX_GR3 77 -#define MC_ENGINE_IDX_GR4 78 -#define MC_ENGINE_IDX_GR5 79 -#define MC_ENGINE_IDX_GR6 80 -#define MC_ENGINE_IDX_GR7 81 -#define MC_ENGINE_IDX_ESCHED 82 +#define MC_ENGINE_IDX_GR1 83 +#define MC_ENGINE_IDX_GR2 84 +#define MC_ENGINE_IDX_GR3 85 +#define MC_ENGINE_IDX_GR4 86 +#define MC_ENGINE_IDX_GR5 87 +#define MC_ENGINE_IDX_GR6 88 +#define MC_ENGINE_IDX_GR7 89 +#define MC_ENGINE_IDX_ESCHED 90 #define MC_ENGINE_IDX_ESCHED__SIZE 64 -#define MC_ENGINE_IDX_GR_FECS_LOG 146 +#define MC_ENGINE_IDX_GR_FECS_LOG 154 #define MC_ENGINE_IDX_GR0_FECS_LOG MC_ENGINE_IDX_GR_FECS_LOG -#define MC_ENGINE_IDX_GR1_FECS_LOG 147 -#define MC_ENGINE_IDX_GR2_FECS_LOG 148 -#define MC_ENGINE_IDX_GR3_FECS_LOG 149 -#define MC_ENGINE_IDX_GR4_FECS_LOG 150 -#define MC_ENGINE_IDX_GR5_FECS_LOG 151 -#define MC_ENGINE_IDX_GR6_FECS_LOG 152 -#define MC_ENGINE_IDX_GR7_FECS_LOG 153 -#define MC_ENGINE_IDX_TMR_SWRL 154 -#define MC_ENGINE_IDX_MAX 155 // This must be kept as the max bit if +#define MC_ENGINE_IDX_GR1_FECS_LOG 155 +#define MC_ENGINE_IDX_GR2_FECS_LOG 156 +#define MC_ENGINE_IDX_GR3_FECS_LOG 157 +#define MC_ENGINE_IDX_GR4_FECS_LOG 158 +#define MC_ENGINE_IDX_GR5_FECS_LOG 159 +#define MC_ENGINE_IDX_GR6_FECS_LOG 160 +#define MC_ENGINE_IDX_GR7_FECS_LOG 161 +#define MC_ENGINE_IDX_TMR_SWRL 162 +#define MC_ENGINE_IDX_MAX 163 // This must be kept as the max bit if // we need to add more engines #define MC_ENGINE_IDX_INVALID 0xFFFFFFFF diff --git a/src/nvidia/inc/kernel/gpu/intrable/intrable.h b/src/nvidia/inc/kernel/gpu/intrable/intrable.h deleted file mode 100644 index aa87efbb5..000000000 --- a/src/nvidia/inc/kernel/gpu/intrable/intrable.h +++ /dev/null @@ -1,3 +0,0 @@ - -#include "g_intrable_nvoc.h" - diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/mem_mapper.h b/src/nvidia/inc/kernel/gpu/mem_mgr/mem_mapper.h new file mode 100644 index 000000000..bd69da301 --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/mem_mapper.h @@ -0,0 +1,3 @@ + +#include "g_mem_mapper_nvoc.h" + diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h index 9c6933689..9bddaf607 100644 --- a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h @@ -156,11 +156,20 @@ typedef struct _RANGELISTTYPE struct _RANGELISTTYPE *pNext; } RANGELISTTYPE, *PRANGELISTTYPE; +typedef enum +{ + MEMORY_PROTECTION_UNPROTECTED = 0, + MEMORY_PROTECTION_PROTECTED = 1 +} MEMORY_PROTECTION; + /*! * @brief Callbacks to UVM for eviction */ -typedef NV_STATUS (*pmaEvictPagesCb_t)(void *ctxPtr, NvU32 pageSize, NvU64 *pPages, NvU32 count, NvU64 physBegin, NvU64 physEnd); -typedef NV_STATUS (*pmaEvictRangeCb_t)(void *ctxPtr, NvU64 physBegin, NvU64 physEnd); +typedef NV_STATUS (*pmaEvictPagesCb_t)(void *ctxPtr, NvU32 pageSize, NvU64 *pPages, + NvU32 count, NvU64 physBegin, NvU64 physEnd, + MEMORY_PROTECTION prot); +typedef NV_STATUS (*pmaEvictRangeCb_t)(void *ctxPtr, NvU64 physBegin, NvU64 physEnd, + MEMORY_PROTECTION prot); /*! * @brief Pluggable data structure management. Currently we have regmap and address tree. diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.h b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.h index ec43669bb..23f013c63 100644 --- a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.h +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.h @@ -42,10 +42,11 @@ void pmaRegionPrint(PMA *pPma, PMA_REGION_DESCRIPTOR *pRegion, void *pMap); NvBool pmaStateCheck(PMA *pPma); // Temporary putting these here. TODO refactor them in the next CL. -NV_STATUS _pmaEvictContiguous(PMA *pPma, void *pMap, NvU64 evictStart, NvU64 evictEnd); +NV_STATUS _pmaEvictContiguous(PMA *pPma, void *pMap, NvU64 evictStart, NvU64 evictEnd, + MEMORY_PROTECTION prot); NV_STATUS _pmaEvictPages(PMA *pPma, void *pMap, NvU64 *evictPages, NvU64 evictPageCount, - NvU64 *allocPages, NvU64 allocPageCount, NvU32 pageSize, NvU64 physBegin, - NvU64 physEnd); + NvU64 *allocPages, NvU64 allocPageCount, NvU32 pageSize, + NvU64 physBegin, NvU64 physEnd, MEMORY_PROTECTION prot); void _pmaClearScrubBit(PMA *pPma, SCRUB_NODE *pPmaScrubList, NvU64 count); NV_STATUS _pmaCheckScrubbedPages(PMA *pPma, NvU64 chunkSize, NvU64 *pPages, NvU32 pageCount); NV_STATUS _pmaPredictOutOfMemory(PMA *pPma, NvLength allocationCount, NvU32 pageSize, diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/virt_mem_allocator_common.h b/src/nvidia/inc/kernel/gpu/mem_mgr/virt_mem_allocator_common.h index 779b608fa..7b1ea5342 100644 --- a/src/nvidia/inc/kernel/gpu/mem_mgr/virt_mem_allocator_common.h +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/virt_mem_allocator_common.h @@ -53,6 +53,7 @@ typedef struct EVENTNOTIFICATION EVENTNOTIFICATION; #define RM_PAGE_MASK 0x0FFF #define RM_PAGE_SHIFT 12 #define RM_PAGE_SHIFT_64K 16 +#define RM_PAGE_SHIFT_128K 17 // Huge page size is 2 MB #define RM_PAGE_SHIFT_HUGE 21 diff --git a/src/nvidia/inc/kernel/gpu/nvbitmask.h b/src/nvidia/inc/kernel/gpu/nvbitmask.h new file mode 100644 index 000000000..501dd151a --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/nvbitmask.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _NVBITMASK_H_ +#define _NVBITMASK_H_ + +#include "kernel/gpu/gpu_engine_type.h" + +// +// Engine Type capability mask bit-array helper MACROS to support on growing number of engine types +// The caps is defined as +// NvU32 caps[NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX] +// +#define NVGPU_ENGINE_CAPS_MASK_BITS 32 +#define NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX ((RM_ENGINE_TYPE_LAST-1)/NVGPU_ENGINE_CAPS_MASK_BITS + 1) +#define NVGPU_GET_ENGINE_CAPS_MASK(caps, id) (caps[(id)/NVGPU_ENGINE_CAPS_MASK_BITS] & NVBIT((id) % NVGPU_ENGINE_CAPS_MASK_BITS)) +#define NVGPU_SET_ENGINE_CAPS_MASK(caps, id) (caps[(id)/NVGPU_ENGINE_CAPS_MASK_BITS] |= NVBIT((id) % NVGPU_ENGINE_CAPS_MASK_BITS)) + +#endif //_NVBITMASK_H_ diff --git a/src/nvidia/inc/kernel/gpu/nvlink/common_nvlink.h b/src/nvidia/inc/kernel/gpu/nvlink/common_nvlink.h new file mode 100644 index 000000000..e4d4d1d90 --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/nvlink/common_nvlink.h @@ -0,0 +1,35 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef COMMON_NVLINK_H +#define COMMON_NVLINK_H + +#include "core/core.h" +#include "kernel/gpu/nvlink/kernel_nvlink.h" +#include "kernel/gpu/nvlink/kernel_ioctrl.h" + +#include "ctrl/ctrl2080/ctrl2080nvlink.h" // rmcontrol params + +NV_STATUS nvlinkCtrlCmdBusGetNvlinkCaps(OBJGPU *pGpu, NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS *pParams); + +#endif // COMMON_NVLINK_H diff --git a/src/nvidia/inc/kernel/gpu/perf/kern_perf_1hz.h b/src/nvidia/inc/kernel/gpu/perf/kern_perf_1hz.h deleted file mode 100644 index 16efbf1bc..000000000 --- a/src/nvidia/inc/kernel/gpu/perf/kern_perf_1hz.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef KERNEL_PERF_1HZ_H -#define KERNEL_PERF_1HZ_H - -/* ------------------------ Includes --------------------------------------- */ -#include "gpu/gpu_resource.h" -#include "objtmr.h" - -/* ------------------------ Macros ----------------------------------------- */ -/* ------------------------ Datatypes -------------------------------------- */ -/*! - * This structure represents data for managing 1HZ Callback timer - */ -typedef struct -{ - /*! - * NV_TRUE if 1Hz callback is in progress - */ - NvBool b1HzTimerCallback; - - /*! - * TRUE if AllowMaxPerf and not in Hibernate/Standby - */ - NvBool bEnableTimerUpdates; -} KERNEL_PERF_1HZ; - -/* -------------------- Function Prototypes -------------------------------- */ -/*! - * @brief Handle 1Hz timer callback from SW interrupts - * - * @param[in] pGpu OBJGPU pointer - * @param[in] pTmr OBJTMR pointer - * @param[in] *ptr timer callback ID - * - * @returns Always return NV_OK - * - */ -NV_STATUS kperfTimerProc(OBJGPU *pGpu, OBJTMR *pTmr, void *ptr); - -/*! - * Since the function tmrCancelCallback() needs a distinct value for POBJECT, - * we can not just use any value in the POBJECT field if we intend to use - * tmrCancelCallback() function. For scheduling Kernel Perf related callbacks we - * will use the unique value for the Kernel Perf by using the address of the function - * that will be called when timer elapses. - */ -#define TMR_POBJECT_KERNEL_PERF_1HZ ((void *)(kperfTimerProc)) - -#endif // KERNEL_PERF_1HZ_H diff --git a/src/nvidia/inc/kernel/gpu/subdevice/subdevice_ctrl_ccu_internal.h b/src/nvidia/inc/kernel/gpu/subdevice/subdevice_ctrl_ccu_internal.h index e60275949..69cc9e8ee 100644 --- a/src/nvidia/inc/kernel/gpu/subdevice/subdevice_ctrl_ccu_internal.h +++ b/src/nvidia/inc/kernel/gpu/subdevice/subdevice_ctrl_ccu_internal.h @@ -27,5 +27,9 @@ RMCTRL_EXPORT(NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP, RMCTRL_FLAGS(KERNEL_PRIVILEGED, ROUTE_TO_PHYSICAL, INTERNAL)) - NV_STATUS subdeviceCtrlCmdCcuUnmap(Subdevice *pSubdevice); + NV_STATUS subdeviceCtrlCmdCcuUnmap(Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS *pParams); + + RMCTRL_EXPORT(NV2080_CTRL_CMD_INTERNAL_CCU_SET_STREAM_STATE, + RMCTRL_FLAGS(KERNEL_PRIVILEGED, ROUTE_TO_PHYSICAL, INTERNAL)) + NV_STATUS subdeviceCtrlCmdCcuSetStreamState(Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS *pParams); diff --git a/src/nvidia/inc/kernel/mem_mgr/ctx_buf_pool.h b/src/nvidia/inc/kernel/mem_mgr/ctx_buf_pool.h index ad676aab4..65bdee084 100644 --- a/src/nvidia/inc/kernel/mem_mgr/ctx_buf_pool.h +++ b/src/nvidia/inc/kernel/mem_mgr/ctx_buf_pool.h @@ -37,6 +37,7 @@ #include "mem_mgr/vaspace.h" #include "mem_mgr/pool_alloc.h" #include "gpu/mem_mgr/virt_mem_allocator_common.h" +#include "kernel/gpu/gpu_engine_type.h" // state of context buffer pools struct CTX_BUF_POOL_INFO @@ -77,7 +78,7 @@ void ctxBufPoolRelease(CTX_BUF_POOL_INFO *pCtxBufPool); void ctxBufPoolDestroy(CTX_BUF_POOL_INFO **ppCtxBufPool); NvBool ctxBufPoolIsSupported(OBJGPU *pGpu); NV_STATUS ctxBufPoolGetSizeAndPageSize(CTX_BUF_POOL_INFO *pCtxBufPool, OBJGPU *pGpu, NvU64 alignment, RM_ATTR_PAGE_SIZE attr, NvBool bContig, NvU64 *pSize, NvU32 *pPageSize); -NV_STATUS ctxBufPoolGetGlobalPool(OBJGPU *pGpu, CTX_BUF_ID bufId, NvU32 engineType, CTX_BUF_POOL_INFO **ppCtxBufPool); +NV_STATUS ctxBufPoolGetGlobalPool(OBJGPU *pGpu, CTX_BUF_ID bufId, RM_ENGINE_TYPE rmEngineType, CTX_BUF_POOL_INFO **ppCtxBufPool); NvBool ctxBufPoolIsScrubSkipped(CTX_BUF_POOL_INFO *pCtxBufPool); void ctxBufPoolSetScrubSkip(CTX_BUF_POOL_INFO *pCtxBufPool, NvBool bSkipScrub); #endif // _CTX_BUF_POOL_H_ diff --git a/src/nvidia/inc/kernel/mem_mgr/mem_list.h b/src/nvidia/inc/kernel/mem_mgr/mem_list.h new file mode 100644 index 000000000..37a3d4902 --- /dev/null +++ b/src/nvidia/inc/kernel/mem_mgr/mem_list.h @@ -0,0 +1,45 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_mem_list_nvoc.h" + +#ifndef _MEMORY_LIST_H_ +#define _MEMORY_LIST_H_ + +#include "mem_mgr/mem.h" + +/*! + * These classes are used by the vGPU support to create memory objects for memory + * assigned to a guest VM. + */ +NVOC_PREFIX(memlist) class MemoryList : Memory +{ +public: + NV_STATUS memlistConstruct(MemoryList *pMemoryList, CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams) : + Memory(pCallContext, pParams); + + virtual NvBool memlistCanCopy(MemoryList *pMemoryList); +}; + +#endif diff --git a/src/nvidia/inc/kernel/mem_mgr/mem_multicast_fabric.h b/src/nvidia/inc/kernel/mem_mgr/mem_multicast_fabric.h new file mode 100644 index 000000000..fdbd98c12 --- /dev/null +++ b/src/nvidia/inc/kernel/mem_mgr/mem_multicast_fabric.h @@ -0,0 +1,3 @@ + +#include "g_mem_multicast_fabric_nvoc.h" + diff --git a/src/nvidia/inc/kernel/mem_mgr/vaddr_list.h b/src/nvidia/inc/kernel/mem_mgr/vaddr_list.h index 3aa6579d0..696a45370 100644 --- a/src/nvidia/inc/kernel/mem_mgr/vaddr_list.h +++ b/src/nvidia/inc/kernel/mem_mgr/vaddr_list.h @@ -31,10 +31,75 @@ #include "containers/map.h" #include "mem_mgr/vaspace.h" +#define FOR_EACH_IN_VADDR_LIST(pVaList, pVAS, vaddr) \ + { \ + VA_LIST_MAPIter it; \ + (pVAS) = NULL; \ + (vaddr) = 0; \ + if ((pVaList)->type == VA_LIST_SIMPLE) \ + { \ + (pVAS) = (pVaList)->impl.simple.entries[0].pVas; \ + (vaddr) = (pVaList)->impl.simple.entries[0].vAddr; \ + if ((pVAS) == NULL) \ + { \ + (pVAS) = (pVaList)->impl.simple.entries[1].pVas; \ + (vaddr) = (pVaList)->impl.simple.entries[1].vAddr; \ + } \ + } \ + else \ + { \ + it = mapIterAll(&(pVaList)->impl.map); \ + if (mapIterNext(&it)) \ + { \ + if (mapIterNext(&it)) \ + { \ + VA_INFO *pInfo = (VA_INFO *)it.pValue; \ + if (pInfo != NULL) \ + { \ + (vaddr) = pInfo->vAddr; \ + (pVAS) = ((OBJVASPACE *) NvP64_VALUE(mapKey(&(pVaList)->impl.map, pInfo))); \ + } \ + } \ + } \ + } \ + while ((pVAS) != NULL) \ + { + +#define FOR_EACH_IN_VADDR_LIST_END(pVaList, pVAS, vaddr) \ + if ((pVaList)->type == VA_LIST_SIMPLE) \ + { \ + if ((((pVAS) != (pVaList)->impl.simple.entries[1].pVas))) \ + { \ + (pVAS) = (pVaList)->impl.simple.entries[1].pVas; \ + (vaddr) = (pVaList)->impl.simple.entries[1].vAddr; \ + } \ + else \ + { \ + (pVAS) = NULL; \ + (vaddr) = 0; \ + } \ + } \ + else \ + { \ + (pVAS) = NULL; \ + (vaddr) = 0; \ + if (mapIterNext(&it)) \ + { \ + VA_INFO *pInfo = (VA_INFO *)it.pValue; \ + if (pInfo != NULL) \ + { \ + (vaddr) = pInfo->vAddr; \ + (pVAS) = ((OBJVASPACE *) NvP64_VALUE(mapKey(&(pVaList)->impl.map, pInfo))); \ + } \ + } \ + } \ + } \ + } + /*! * Map info */ -typedef struct +typedef struct VADDR_LIST_INFO { /*! * Indicate whether caller should release the VA. @@ -42,12 +107,12 @@ typedef struct * Use vaListSetManaged() to change the value. */ NvBool bRelease; -}VADDR_LIST_INFO; +} VADDR_LIST_INFO; /*! * Virtual memory info */ -typedef struct +typedef struct VA_INFO { /*! virtual address */ NvU64 vAddr; @@ -58,31 +123,82 @@ typedef struct * Key 0 (pVAS == NULL) is used to store this info */ VADDR_LIST_INFO *pVaListInfo; -}VA_INFO; +} VA_INFO; /*! * Dictionary that tracks active virtual memory mappings. * Indexed by the vaspace object pointer. */ -MAKE_MAP(VA_LIST, VA_INFO); +MAKE_MAP(VA_LIST_MAP, VA_INFO); + +typedef enum VA_LIST_TYPE +{ + VA_LIST_SIMPLE = 0, + VA_LIST_DICT = 1 +} VA_LIST_TYPE; + +/*! + * Data structure tracking virtual addresses assigned to virtual address spaces + * Structured to hold mappings for up to two VAS without heap allocation, and + * arbitrary mappings beyond that point using a dictionary. Once more than two + * mappings are added, the list will remain a dictionary until it is destroyed. + */ +typedef struct VA_LIST +{ + VA_LIST_TYPE type; + union VA_LIST_IMPL + { + // Simple list of up to 2 VAS + struct VA_LIST_SIMPLE + { + VADDR_LIST_INFO common; + struct VA_LIST_INLINE + { + OBJVASPACE *pVas; + NvU64 vAddr; + NvU64 refCnt; + } entries[2]; + } simple; + + // Dictionay mapping more than two VAS + VA_LIST_MAP map; + } impl; +} VA_LIST; /*! Init the tracker object */ NV_STATUS vaListInit(VA_LIST *); + +/*! remove all mappings */ +void vaListClear(VA_LIST *); + /*! Init the tracker object */ void vaListDestroy(VA_LIST *); + /*! * Set VA lifecycle property. * TRUE means caller should free the VA. e.g RM managed mappings * FALSE means caller shouldn't free the VA. e.g UVM or KMD managed mappings. */ NV_STATUS vaListSetManaged(VA_LIST *, NvBool bManaged); + NvBool vaListGetManaged(VA_LIST *); + /*! Add a vas mapping to the tracker */ NV_STATUS vaListAddVa(VA_LIST *, OBJVASPACE *, NvU64 vaddr); + /*! Remove a vas mapping to the tracker */ NV_STATUS vaListRemoveVa(VA_LIST *, OBJVASPACE *); + /*! Get the vas mapping */ NV_STATUS vaListFindVa(VA_LIST *, OBJVASPACE *, NvU64 *vaddr); + /*! Get the vas refCount */ NV_STATUS vaListGetRefCount(VA_LIST *, OBJVASPACE *, NvU64 *refCount); + +/*! Set the vas refCount */ +NV_STATUS vaListSetRefCount(VA_LIST *, OBJVASPACE *, NvU64 refCount); + +/*! Get the number of mappings */ +NvU32 vaListMapCount(VA_LIST *); + #endif // VADDR_LIST_H diff --git a/src/nvidia/inc/kernel/os/os_stub.h b/src/nvidia/inc/kernel/os/os_stub.h index 11132d417..66167bf38 100644 --- a/src/nvidia/inc/kernel/os/os_stub.h +++ b/src/nvidia/inc/kernel/os/os_stub.h @@ -52,6 +52,7 @@ OSSimEscapeWrite stubOsSimEscapeWrite; OSSimEscapeWriteBuffer stubOsSimEscapeWriteBuffer; OSSimEscapeRead stubOsSimEscapeRead; OSSimEscapeReadBuffer stubOsSimEscapeReadBuffer; +OSSetSurfaceName stubOsSetSurfaceName; OSCallACPI_MXMX stubOsCallACPI_MXMX; OSCallACPI_DSM stubOsCallACPI_DSM; OSCallACPI_DDC stubOsCallACPI_DDC; diff --git a/src/nvidia/inc/kernel/platform/acpi_common.h b/src/nvidia/inc/kernel/platform/acpi_common.h index 2b46703d8..fe0ae82d6 100644 --- a/src/nvidia/inc/kernel/platform/acpi_common.h +++ b/src/nvidia/inc/kernel/platform/acpi_common.h @@ -28,6 +28,9 @@ #include "core/core.h" #include "rmconfig.h" +#include "platform/nbsi/nbsi_read.h" +NV_STATUS getAcpiDsmObjectData(OBJGPU *, NvU8**, NvU32 *, ACPI_DSM_FUNCTION, NBSI_GLOB_TYPE, NBSI_VALIDATE); + NV_STATUS testIfDsmFuncSupported(OBJGPU *, ACPI_DSM_FUNCTION); NV_STATUS testIfDsmSubFunctionEnabled(OBJGPU *, ACPI_DSM_FUNCTION, NvU32); NV_STATUS remapDsmFunctionAndSubFunction(OBJGPU *, ACPI_DSM_FUNCTION *, NvU32 *); diff --git a/src/nvidia/inc/kernel/platform/nbsi/nbsi_read.h b/src/nvidia/inc/kernel/platform/nbsi/nbsi_read.h new file mode 100644 index 000000000..08803bf32 --- /dev/null +++ b/src/nvidia/inc/kernel/platform/nbsi/nbsi_read.h @@ -0,0 +1,104 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NBSI_READ_H +#define NBSI_READ_H + +#include "platform/nbsi/nbsi_table.h" + +typedef enum _NBSI_VALIDATE +{ + NBSI_VALIDATE_ALL = 0, // do CRC and all normal tests + NBSI_VALIDATE_IGNORE_CRC // normal tests, skip CRC +} NBSI_VALIDATE; + +typedef struct OBJGPU OBJGPU; + +NvU16 fnv1Hash16(const NvU8 * data, NvU32 dataLen); +NvU16 fnv1Hash16Unicode(const NvU16 * data, NvU32 dataLen); +NvU32 fnv32buf(const void *buf, NvU32 len, NvU32 hval, NvU32 prevPartHashLen); +NvU32 fnv32bufUnicode(const void *buf, NvU32 len, NvU32 hval, NvU32 prevPartHashLen); +void fnv1Hash20Array(const NvU8 *, NvU32, NvU32 * , NvU8); +void fnv1Hash20ArrayUnicode(const NvU16 *, NvU32, NvU32 * , NvU8); +NvU64 fnv1Hash64(const NvU8 * data, NvU32 dataLen); +NvU32 getNbsiValue (OBJGPU *, NvU32, NvU16, NvU8, NvU32*, NvU8*, NvU32*, NvU32*); +NV_STATUS initNbsiTable(OBJGPU *); +void freeNbsiTable(OBJGPU *); +NV_STATUS nbsiReadRegistryDword(OBJGPU *, const char *, NvU32 *); +NV_STATUS nbsiReadRegistryString(OBJGPU *, const char *, NvU8 *, NvU32 *); +NV_STATUS getNbsiObjByType(OBJGPU *, NvU16, NBSI_SOURCE_LOC *, NvU8 *, NvU32, NvU8 *, NvU32*, NvU32*, NvU32*, ACPI_DSM_FUNCTION, NBSI_VALIDATE); +void initNbsiObject(NBSI_OBJ *pNbsiObj); +NBSI_OBJ *getNbsiObject(void); + + +/* + * 32 bit magic FNV-0 and FNV-1 prime + */ +#define FNV_32_PRIME 0x01000193 // is 16777619. +#define MASK_20 0xfffff +#define MASK_16 0xffff +#define FNV1_32_INIT 0x811C9DC5 // is 2166136261. + +// State (undefined, open, bad or not present) of the nbsiTable +#define NBSI_TABLE_UNDEFINED 0 // nbsi table initialization not called so + // nbsiTableptr unallocated +#define NBSI_TABLE_INIT 1 // nbsi table being opened not yet ready +#define NBSI_TABLE_OPEN 2 // nbsi table ready for business +#define NBSI_TABLE_BAD 3 // nbsi table structure bad +#define NBSI_TABLE_NOTPRESENT 4 // nbsi table is not present + +#define NBSI_TABLE_FMT_UNKNOWN 0xff // Unknown format for NBSI table + +#define NBSI_REVISION_ID 0x00000101 +#define NVHG_NBSI_REVISION_ID 0x00000101 + +#define NBSI_FUNC_PLATCAPS 0x00000001 // Platform NBSI capabilities +#define NBSI_FUNC_PLATPOLICY 0x00000002 // Query/Set Platform Policy +#define NBSI_FUNC_DISPLAYSTATUS 0x00000003 // Query the Display Hot-Key +#define NBSI_FUNC_MDTL 0x00000004 // +#define NBSI_FUNC_CALLBACKS 0x00000005 // Get Callbacks +#define NBSI_FUNC_GETOBJBYTYPE 0x00000006 // Get an Object by Type +#define NBSI_FUNC_GETALLOBJS 0x00000007 // Get Driver Object + +// Return values for NBSI_FUNC_SUPPORT call. +#define NBSI_FUNC_PLATCAPS_SUPPORTED NVBIT(1) // Platform NBSI capabilities +#define NBSI_FUNC_PLATPOLICY_SUPPORTED NVBIT(2) // Query/Set Platform Policy +#define NBSI_FUNC_DISPLAYSTATUS_SUPPORTED NVBIT(3) // Query the Display Hot-Key +#define NBSI_FUNC_MDTL_SUPPORTED NVBIT(4) // +#define NBSI_FUNC_CALLBACKS_SUPPORTED NVBIT(5) // Get Callbacks +#define NBSI_FUNC_GETOBJBYTYPE_SUPPORTED NVBIT(6) // Get an Object by Type +#define NBSI_FUNC_GETALLOBJS_SUPPORTED NVBIT(7) // Get Driver Object + +#define NBSI_READ_SIZE (4*1024) // 4K as per spec +#define NBSI_INIT_TABLE_ALLOC_SIZE NBSI_READ_SIZE // must be larger than + // NBSI_READ_SIZE + +#define NBPB_FUNC_SUPPORT 0x00000000 // Function is supported? +#define NBPB_FUNC_GETOBJBYTYPE 0x00000010 // Fetch any specific Object by Type +#define NBPB_FUNC_GETALLOBJS 0x00000011 // Fetch all Objects +#define NBPB_FUNC_GETTHERMALBUDGET 0x00000020 // Get the current thermal budget +#define NBPB_FUNC_GETPSS 0x00000021 // Get the PSS table +#define NBPB_FUNC_SETPPC 0x00000022 // Set p-State Cap +#define NBPB_FUNC_GETPPC 0x00000023 // Get the last p-State cap set with _FUNC_SETPPC + +#endif // NBSI_READ_H diff --git a/src/nvidia/inc/kernel/platform/nbsi/nbsi_table.h b/src/nvidia/inc/kernel/platform/nbsi/nbsi_table.h new file mode 100644 index 000000000..a4a560ad1 --- /dev/null +++ b/src/nvidia/inc/kernel/platform/nbsi/nbsi_table.h @@ -0,0 +1,375 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NBSITBL_H +#define NBSITBL_H + +#include "ctrl/ctrl0000/ctrl0000system.h" // NV0000_SYSTEM_MAX_APPROVAL_COOKIE_STRING_LENGTH +#include "ctrl/ctrl2080/ctrl2080bios.h" // NV2080_CTRL_BIOS_NBSI_NUM_MODULES +#include "core/core.h" +#include "platform/pci_exp_table.h" + +// Maximum number of NBSI OS strings (including generic) +#define MAX_NBSI_OS 3 +#define MAX_NBSI_OS_STR_LEN 10 + +#define NBSI_SOURCE_LOC NvU16 + +typedef enum _NBSI_TBL_SOURCES // keep in sync with nvapi.spec +{ + NBSI_TBL_SOURCE_BEST_FIT = 0, + NBSI_TBL_SOURCE_REGISTRY = 1, + NBSI_TBL_SOURCE_VBIOS = 2, + NBSI_TBL_SOURCE_SBIOS = 8, + NBSI_TBL_SOURCE_ACPI = 0x10, + NBSI_TBL_SOURCE_UEFI = 0x20 +} NBSI_TBL_SOURCES, * PNBSI_TBL_SOURCES; +#define NBSI_TBL_SOURCE_MAX 6 // number of NBSI_TBL_SOURCES entries (not including BEST FIT) + +#define NBSI_TBL_SOURCE_ALL (NBSI_TBL_SOURCE_REGISTRY | \ + NBSI_TBL_SOURCE_VBIOS | \ + NBSI_TBL_SOURCE_SBIOS | \ + NBSI_TBL_SOURCE_ACPI | \ + NBSI_TBL_SOURCE_UEFI) +#define NBSI_TBL_SOURCE_NONE 0 + +typedef enum _NBSI_ACPI_METHOD +{ + NBSI_TBL_SOURCE_ACPI_UNKNOWN, + NBSI_TBL_SOURCE_ACPI_BY_OBJ_TYPE, + NBSI_TBL_SOURCE_ACPI_BY_ALL_OBJ, + NBSI_TBL_SOURCE_ACPI_BOTH_METHODS +} NBSI_ACPI_METHOD, *PNBSI_ACPI_METHOD; + +typedef struct _NBSI_CACHE_ENTRY_OBJ { + NvU16 globType; + NBSI_SOURCE_LOC globSource; + NvU8 globIndex; + NBSI_SOURCE_LOC altGlobSource; + NvU8 altGlobIndex; + NvU8 * pObj; +} NBSI_CACHE_ENTRY_OBJ, *PNBSI_CACHE_ENTRY_OBJ; + +typedef struct _NBSI_CACHE_OBJ { + // Number of entries we've found and cached. + NvU8 tblCacheNumEntries; + // Maximum entries we might have. + NvU8 tblCacheMaxNumEntries; + // Pointers to cache entries + PNBSI_CACHE_ENTRY_OBJ pCacheEntry[1]; +} NBSI_CACHE_OBJ, *PNBSI_CACHE_OBJ; + +// +// The following two structs (DRVR_VER0 and DRVR_VER) attempt to handle +// the driver version. +// Driver revision example: 7.15.11.7782 +// The format is: a.bb.1c.dddd +// where a represents the OS (7 for Vista/Vista64) +// bb represents the DX version (15 for DX10) +// the 1 in 1c is specified by MS +// c.dddd is the NV-specific driver version. +// old version of this structure had byte to hold minRev but the new +// version uses 20 bits. +// +typedef struct _DRVR_VER0 +{ + NvU8 majVer : 8; + NvU8 minVer : 8; + NvU8 majRev : 8; + NvU8 minRev : 8; +} DRVR_VER0, * PDRVR_VER0; + +typedef struct _DRVR_VER +{ + NvU32 Rev : 20; + NvU32 DX : 8; + NvU32 OS : 4; +} DRVR_VER, * PDRVR_VER; + +typedef struct _NBSI_OBJ { + // Setting for current maximum OS strings in use. + NvU8 curMaxNbsiOSes; + + // Default hash strings for OS strings (done once so to speed up the system) + NvU32 nbsiOSstrHash[MAX_NBSI_OS]; + + // Default string for a blank path hash (done once so to speed up the system) + NvU16 nbsiBlankPathHash; + + // Contains the OS strings. + NvU8 nbsiOSstr[MAX_NBSI_OS][MAX_NBSI_OS_STR_LEN+1]; + NvU32 nbsiOSstrLen[MAX_NBSI_OS]; + + // Currently available locations of NBSI directory + NBSI_SOURCE_LOC availDirLoc[NV_MAX_DEVICES]; + + // nbsi driver object save. + NvU8 * nbsiDrvrTable[NV_MAX_DEVICES]; + + // pointer to array of pointers (cache of tables) + PNBSI_CACHE_OBJ pTblCache[NV_MAX_DEVICES]; + + // pointer to override tables + NvU8 * regOverrideList[NV_MAX_DEVICES]; + + // Current Driver version for best fit check. + DRVR_VER DriverVer; + +} NBSI_OBJ, *PNBSI_OBJ; + + +#ifndef VARIABLE_SIZE_ARRAY +#define VARIABLE_SIZE_ARRAY 1 // The size of this array may vary. +#endif + +// For offsets which are present but not defined (an error case) have +// a predefined undefined link. This allows me to build a table which +// has all 12 module types defined, but valid links on only the ones I'm +// using... And I can fail the search if asked to search one that's not +// defined. +#define NBSI_UNDEFINED_OFFSET 0xffffffff + +typedef enum _NBSI_ELEMENT_TYPES +{ + NBSI_BYTE = 0, + NBSI_WORD, + NBSI_DWORD, + NBSI_QWORD, + NBSI_BYTE_ARRAY, + NBSI_BYTE_ARRAY_EXTENDED, + numNBSI_TYPES +} NBSI_ELEMENT_TYPES; + +// size of element header in bytes. 24 bits. +#define NBSI_ELEMENT_HDRSIZ 3 + +#pragma pack(1) +typedef struct _NBSI_ELEMENT +{ + struct ELEMENT_HDR_PARTA + { + NvU8 type: 4; + NvU8 lsnValueID: 4; + } hdrPartA; + struct ELEMENT_HDR_PARTB + { + NvU16 mswValueID; + } hdrPartB; + union ELEMENT_DATA + { + NvU8 dataByte; + NvU16 dataWord; + NvU32 dataDWord; + NvU64 dataQWord; + struct + { + NvU8 size; + NvU8 data[VARIABLE_SIZE_ARRAY]; + } ba; + struct + { + NvU16 size; + NvU8 data[VARIABLE_SIZE_ARRAY]; + } bax; + } data; +} NBSI_ELEMENT, *PNBSI_ELEMENT; +#pragma pack() + +#pragma pack(1) +typedef struct _NBSI_ELEMENTS +{ + NvU32 numElements; + NBSI_ELEMENT elements[VARIABLE_SIZE_ARRAY]; +} NBSI_ELEMENTS, *PNBSI_ELEMENTS; +#pragma pack() + +#pragma pack(1) +typedef struct _NBSI_SCOPE +{ + NvU16 pathID; + NvU32 offset; // Relative Offset from this member i.e. &ulOffset +} NBSI_SCOPE, *PNBSI_SCOPE; +#pragma pack() + +#pragma pack(1) +typedef struct _NBSI_SCOPES +{ + NvU32 numPaths; + NBSI_SCOPE paths[VARIABLE_SIZE_ARRAY]; +} NBSI_SCOPES, *PNBSI_SCOPES; +#pragma pack() + +#pragma pack(1) +typedef struct _NBSI_MODULE +{ + NvU16 moduleID; + NvU32 offset; // Relative Offset from this member i.e. &ulOffset +} NBSI_MODULE, *PNBSI_MODULE; +#pragma pack() + +// Maximum understood dir version +#define MAXNBSIDIRVER 1 + +#define NBSIDIRHDRSTRING (NvU32) (('N'<<24)+('B'<<16)+('S'<<8)+'I') +#define MXMHDRSTRING (NvU32) (('_'<<24)+('M'<<16)+('X'<<8)+'M') + +// A directory of globs +#pragma pack(1) +typedef union _NBSI_DIRECTORY +{ + struct OLD_FORMAT // Original version for Beta + { + NvU8 numGlobs; // number of globs + NvU8 dirVer; // dirVer + NvU16 globType[1]; // NBSI_GLOB_TYPE (placeholder) + } od; + struct NEW_FORMAT // Shipping version + { + NvU32 nbsiHeaderString; // header string NBSIDIRHDRSTRING + NvU32 size; // size of entire directory + NvU8 numGlobs; // number of globs + NvU8 dirVer; // dirVer + NvU16 globType[1]; // NBSI_GLOB_TYPE (placeholder + } d; +} NBSI_DIRECTORY, *PNBSI_DIRECTORY; +#pragma pack() + +#define nbsiobjtype(ch1,ch2) (NvU16) ((ch1<<8) + ch2) +typedef enum _NBSI_GLOB_TYPES +{ + NBSI_RSRVD_GLOB = 0, // Reserved Glob type + NBSI_DRIVER = nbsiobjtype('D','R'), // Driver Object + NBSI_VBIOS = nbsiobjtype('V','B'), // VBIOS Object + NBSI_HDCP = nbsiobjtype('H','K'), // HDCP Keys + NBSI_INFOROM = nbsiobjtype('I','R'), // InfoROM object + NBSI_HDD = nbsiobjtype('H','D'), // Storage Driver + NBSI_NONVOLATILE = nbsiobjtype('N','V'), // CMOS settings + NBSI_PLAT_INFO = nbsiobjtype('P','I'), // PlatformInfo Object + NBSI_PLAT_INFO_WAR = nbsiobjtype('I','P'), // PlatformInfo WAR Bug 986051 + NBSI_VALKEY = nbsiobjtype('V','K'), // Validation key + NBSI_TEGRA_INFO = nbsiobjtype('T','G'), // Tegra Info object + NBSI_TEGRA_DCB = nbsiobjtype('T','D'), // Tegra DCB object + NBSI_TEGRA_PANEL = nbsiobjtype('T','P'), // Tegra TPB object + NBSI_TEGRA_DSI = nbsiobjtype('T','S'), // Tegra DSI information + NBSI_SYS_INFO = nbsiobjtype('G','D'), // System Info object + NBSI_TEGRA_TMDS = nbsiobjtype('T','T'), // Tegra TMDS configuration block + NBSI_OPTIMUS_PLAT = nbsiobjtype('O','P'), // Optimus Platform key +} NBSI_GLOB_TYPE, * PNBSI_GLOB_TYPE; + +#pragma pack(1) +typedef struct _NBSI_UID0 +{ + NvU16 svid; // Sub-system Vendor ID + NvU16 ssid; // Sub-system Device ID + struct { + NvU16 vid; // Chip Vendor ID (NVIDIA) + NvU16 did; // Chip Device ID + NvU8 revId; // Chip RevID + } Chip; + DRVR_VER0 Driver; // Target Driver Version + struct { // Target BIOS Version + NvU8 minVer : 8; + NvU8 majVer : 8; + } VBIOS; + struct { // Platform Firmware Version + NvU8 minVer : 4; + NvU8 majVer : 4; + } Platform; +} NBSI_UID0, *PNBSI_UID0; +#pragma pack() + +#pragma pack(1) +typedef struct _NBSI_UID +{ + NvU16 svid; // Sub-system Vendor ID + NvU16 ssid; // Sub-system Device ID + struct { + NvU16 vid; // Chip Vendor ID (NVIDIA) + NvU16 did; // Chip Device ID + NvU8 revId; // Chip RevID + } Chip; + DRVR_VER Driver; // Target Driver Version + struct { // Target BIOS Version + NvU8 minVer : 8; + NvU8 majVer : 8; + } VBIOS; + struct { // Platform Firmware Version + NvU8 minVer : 4; + NvU8 majVer : 4; + } Platform; +} NBSI_UID, *PNBSI_UID; +#pragma pack() + +#pragma pack(1) +typedef struct _DSM_GEN_OBJ_HDR +{ + NvU64 sig; // Common hash signature + NvU16 globType; // NBSI_GLOB_TYPE (i.e. NBSI_HDCP, NBSI_VALKEY etc.) + NvU32 size; // Entire size in bytes object, including header and object data. + NvU16 majMinVer; // Version of Generic Object in Maj:Min format +} DSM_GEN_OBJ_HDR, *PDSM_GEN_OBJ_HDR; +#pragma pack() +#define DSM_GEN_HDR_SIZE (sizeof(DSM_GEN_OBJ_HDR)) + + +#pragma pack(1) +typedef struct _NBSI_GEN_OBJ +{ + DSM_GEN_OBJ_HDR objHdr; + // actual packed object data + NvU8 objData[VARIABLE_SIZE_ARRAY]; +} NBSI_GEN_OBJ, *PNBSI_GEN_OBJ; +#pragma pack() +#define NBSI_GEN_HDR_SIZE (sizeof(NBSI_GEN_OBJ)-VARIABLE_SIZE_ARRAY) + +#define NBSI_MAX_TABLE_SIZE (256*1024) // define some maximum size +#define NBSI_MIN_GEN_OBJ_SIZE NBSI_GEN_HDR_SIZE + +#define NBSI_DRIVERVER_0100 0x0100 +#pragma pack(1) +typedef struct _NBSI_DRIVER_OBJ0 +{ + DSM_GEN_OBJ_HDR objHdr; // object header. globType = NBSI_GLOB_TYPE ('DR') + NBSI_UID0 uid; // Platform UID + NvU32 numModules; + // num_modules may vary... this is placeholder + NBSI_MODULE modules[NV2080_CTRL_BIOS_NBSI_NUM_MODULES]; + // actual packed object data + NvU8 objData[VARIABLE_SIZE_ARRAY]; +} NBSI_DRIVER_OBJ0, *PNBSI_DRIVER_OBJ0; +#pragma pack() + +#pragma pack(1) +typedef struct _NBSI_DRIVER_OBJ +{ + DSM_GEN_OBJ_HDR objHdr; // object header. globType = NBSI_GLOB_TYPE ('DR') + NBSI_UID uid; // Platform UID + NvU32 numModules; + // num_modules may vary... this is placeholder + NBSI_MODULE modules[NV2080_CTRL_BIOS_NBSI_NUM_MODULES]; + // actual packed object data + NvU8 objData[VARIABLE_SIZE_ARRAY]; +} NBSI_DRIVER_OBJ, *PNBSI_DRIVER_OBJ; +#pragma pack() + +#endif // NBSITBL_H diff --git a/src/nvidia/inc/kernel/platform/platform_request_handler.h b/src/nvidia/inc/kernel/platform/platform_request_handler.h new file mode 100644 index 000000000..3af10707a --- /dev/null +++ b/src/nvidia/inc/kernel/platform/platform_request_handler.h @@ -0,0 +1,3 @@ + +#include "g_platform_request_handler_nvoc.h" + diff --git a/src/nvidia/inc/kernel/platform/platform_request_handler_utils.h b/src/nvidia/inc/kernel/platform/platform_request_handler_utils.h new file mode 100644 index 000000000..092e03fe1 --- /dev/null +++ b/src/nvidia/inc/kernel/platform/platform_request_handler_utils.h @@ -0,0 +1,281 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2011-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _PLATFORM_REQUEST_HANDLER_UTILS_H_ +#define _PLATFORM_REQUEST_HANDLER_UTILS_H_ + +//_PCONTROL +//_PCONTROL response from driver to SBIOS +#define NV_PB_PFM_REQ_HNDLR_PCTRL_RES 3:0 +#define NV_PB_PFM_REQ_HNDLR_PCTRL_RES_CHANGE_EVENT (0) +#define NV_PB_PFM_REQ_HNDLR_PCTRL_RES_VPSTATE_INFO (1) +#define NV_PB_PFM_REQ_HNDLR_PCTRL_RES_VPSTATE_SET (2) +#define NV_PB_PFM_REQ_HNDLR_PCTRL_RES_VPSTATE_UPDATE (3) +#define NV_PB_PFM_REQ_HNDLR_PCTRL_RESERVED 7:4 +#define NV_PB_PFM_REQ_HNDLR_PCTRL_RESERVED_BITS (0) +#define NV_PB_PFM_REQ_HNDLR_PCTRL_LAST_VPSTATE_LIMIT 15:8 +#define NV_PB_PFM_REQ_HNDLR_PCTRL_INDEX_PSTATE 15:8 +#define NV_PB_PFM_REQ_HNDLR_PCTRL_SLOW_EXT_VPSTATE 23:16 +#define NV_PB_PFM_REQ_HNDLR_PCTRL_FAST_VPSTATE 31:24 +#define NV_PB_PFM_REQ_HNDLR_PCTRL_MAPPING_VPSTATE 31:24 + +//_PCONTROL request from SBIOS to driver +#define NV_PB_PFM_REQ_HNDLR_PCTRL_REQ 3:0 +#define NV_PB_PFM_REQ_HNDLR_PCTRL_REQ_NO_ACTION (0) +#define NV_PB_PFM_REQ_HNDLR_PCTRL_REQ_VPSTATE_INFO (1) +#define NV_PB_PFM_REQ_HNDLR_PCTRL_REQ_VPSTATE_SET (2) +#define NV_PB_PFM_REQ_HNDLR_PCTRL_REQ_VPSTATE_UPDATE (3) +#define NV_PB_PFM_REQ_HNDLR_PCTRL_RESERVED1 7:4 +#define NV_PB_PFM_REQ_HNDLR_PCTRL_RESERVED1_BITS (0) +#define NV_PB_PFM_REQ_HNDLR_PCTRL_INDEX_PSTATE 15:8 +#define NV_PB_PFM_REQ_HNDLR_PCTRL_MAX_VPSTATE_LEVEL 15:8 +#define NV_PB_PFM_REQ_HNDLR_PCTRL_RESERVED2 30:16 +#define NV_PB_PFM_REQ_HNDLR_PCTRL_RESERVED2_BITS (0) +#define NV_PB_PFM_REQ_HNDLR_PCTRL_BIT_31 31:31 +#define NV_PB_PFM_REQ_HNDLR_PCTRL_BIT_31_ZERO (0) + + +/* + * NV0000_CTRL_PFM_REQ_HNDLR_PSHAREDATA + * + * This structure represents a block of PSHARE data from SBIOS + * + * status + * settings per spec + * ulVersion + * (Major(16 bits):Minor(16 bits), current v1.0) + * Little endian format 0x00, 0x00, 0x01, 0x00 + * tGpu + * GPU temperature (not provided by system) + * + * ctgp + * Configurable TGP limit + */ +typedef struct NV0000_CTRL_PFM_REQ_HNDLR_PSHAREDATA { +// Header to sensor structure + NvU32 status; + NvU32 ulVersion; + + NvU32 tGpu; + NvU32 ctgp; +} NV0000_CTRL_PFM_REQ_HNDLR_PSHAREDATA, *PNV0000_CTRL_PFM_REQ_HNDLR_PSHAREDATA; + +/* + * Begin defines for access to ACPI calls, these + * are used in the RM, so we'd like to get them + * in, even though the CTRL call is not ready. + * NV0000_CTRL_CMD_CALL_PFM_REQ_HNDLR_ACPI + * + * This command is used to send ACPI commands for PlatformRequestHandler compliant SBIOS + * to the RM to be executed by system BIOS. Results of those SBIOS + * command are returned through this interface. + * + * cmd + * NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_TYPE + * Gets system configuration Information. + * NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SUPPORT + * Gets bit mask of supported functions + * NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PCONTROL + * Sets GPU power control features. + * NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PSHARESTATUS + * Gets System PShare Status + * NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_GETPPL + * Execute ACPI GETPPL command. + * NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SETPPL + * Execute ACPI SETPPL command. + * NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PSHAREPARAMS + * Get sensor information and capabilities. + * input + * Used for single DWORD (32 bit) values as input to + * the requested ACPI call. + * + */ +typedef struct _NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CTRL +{ + NvU32 cmd; + NvU32 input; +} NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CTRL; + +/* + * NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_OUTPUT + * + * This structure represents the output from a single ACPI call. + * + * result + * The ACPI return code for the operation attempted. + * pBuffer + * This field returns a pointer the buffer of data requested. + * bufferSz + * This field returns the size of returned data in above pBuffer. + */ +typedef struct _NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_OUTPUT +{ + NvU32 result[2]; + NvU8 *pBuffer; + NvU16 bufferSz; +} NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_OUTPUT; + + +/* + * NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS + * + * This structure represents a parameter block of data to describe an + * ACPI request, and return it's output. + * + * ctrl + * The ACPI request for the operation attempted. + * output + * Output structure from the executed ACPI command. + */ +typedef struct _NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS +{ + NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CTRL ctrl; + NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_OUTPUT output; +} NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS; + +/* + * NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX + * + * Used for PPL and TRL calls, which have up to three input DWORDs and three + * output DWORDs. + */ +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX_MAX_SZ (3) + +typedef struct _NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX +{ + NvU32 pfmreqhndlrFunc; + NvU16 inSize; + NvU16 outSize; + NvU32 input[NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX_MAX_SZ]; + NvU32 output[NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX_MAX_SZ]; +} NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_PARAMS_EX; + +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_TYPE 8:0 +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SUPPORT (GPS_FUNC_SUPPORT) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PCONTROL (GPS_FUNC_PCONTROL) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PSHARESTATUS (GPS_FUNC_PSHARESTATUS) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_GETPPL (GPS_FUNC_GETPPL) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SETPPL (GPS_FUNC_SETPPL) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_GETTRL (GPS_FUNC_GETTRL) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SETTRL (GPS_FUNC_SETTRL) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_GETPPM (GPS_FUNC_GETPPM) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_SETPPM (GPS_FUNC_SETPPM) +#define NV0000_CTRL_PFM_REQ_HNDLR_CALL_ACPI_CMD_PSHAREPARAMS (GPS_FUNC_PSHAREPARAMS) + +// PFM_REQ_HNDLR_SUPPORT output +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_SUPPORT_AVAIL 0:0 +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_PCONTROL_AVAIL 28:28 +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_PSHARESTATUS_AVAIL 32:32 +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_GETPPL_AVAIL 36:36 +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_SETPPL_AVAIL 37:37 +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_GETTRL_AVAIL 38:38 +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_SETTRL_AVAIL 39:39 +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_GETPPM_AVAIL 40:40 +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_SETPPM_AVAIL 41:41 +#define NV0000_CTRL_PFM_REQ_HNDLR_SUPPORTED_PSHAREPARAMS_AVAIL 42:42 + +// PFM_REQ_HNDLR_PCONTROL +#define NV0000_CTRL_PFM_REQ_HNDLR_PCONTROL_REQ_TYPE 3:0 +#define NV0000_CTRL_PFM_REQ_HNDLR_PCONTROL_REQ_TYPE_EVENT_RESP (0x00) // input only +#define NV0000_CTRL_PFM_REQ_HNDLR_PCONTROL_REQ_TYPE_EVENT_DONE (0x00) // output only +#define NV0000_CTRL_PFM_REQ_HNDLR_PCONTROL_REQ_TYPE_VPSTATE_INFO (0x01) // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_PCONTROL_REQ_TYPE_NEW_VP_STATE (0x02) // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_PCONTROL_REQ_TYPE_UPDATE_VP_STATE (0x03) // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_PCONTROL_VPSTATE_LIMIT 15:8 // input request type 0, 2, or 3; output request type 2 +#define NV0000_CTRL_PFM_REQ_HNDLR_PCONTROL_PSTATE_IDX 15:8 // input request type 1; output request type 1 +#define NV0000_CTRL_PFM_REQ_HNDLR_PCONTROL_SLOWEST_VPSTATE 23:16 // input only +#define NV0000_CTRL_PFM_REQ_HNDLR_PCONTROL_FASTEST_VPSTATE 31:24 // input request type 0, 2, or 3 +#define NV0000_CTRL_PFM_REQ_HNDLR_PCONTROL_VPSTATE_MAPPING 31:24 // input request type 1 + +// PFM_REQ_HNDLR_PSHARESTATUS +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_UPDATE_LIMIT 0:0 // output only +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_UPDATE_LIMIT_NOT_PENDING (0) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_UPDATE_LIMIT_PENDING (1) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_DO_NOT_USE 19:1 +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLAT_USER_CONFIG_TGP_MODE_SUPPORT 20:20 // output only +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLAT_USER_CONFIG_TGP_MODE_SUPPORT_DISABLE (0) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_PLAT_USER_CONFIG_TGP_MODE_SUPPORT_ENABLE (1) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_EDPPEAK_LIMIT_UPDATE 21:21 // output only +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_EDPPEAK_LIMIT_UPDATE_FALSE (0) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_EDPPEAK_LIMIT_UPDATE_TRUE (1) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_USER_CONFIG_TGP_MODE 22:22 // output only +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_USER_CONFIG_TGP_MODE_DISABLE (0) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARESTATUS_USER_CONFIG_TGP_MODE_ENABLE (1) + + +// Shared by GETPPL, SETPPL +#define NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_COUNT (3) +#define NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_VERSION_IDX (0) +#define NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARG0_VERSION_MINOR 15:0 // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARG0_VERSION_MAJOR 31:16 // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARG0_VERSION_MAJOR_V1 (1) // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_LIMIT1_IDX (1) // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_PPL_ARGS_LIMIT2_IDX (2) // input & output + +// Shared by GETTRL, SETTRL +#define NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARGS_COUNT (2) +#define NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARGS_VERSION_IDX (0) +#define NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARG0_VERSION_MINOR 15:0 // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARG0_VERSION_MAJOR 31:16 // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARG0_VERSION_MAJOR_V1 (1) // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_TRL_ARGS_FREQ_MHZ_IDX (1) // input & output + +// Shared by GETPPM, SETPPM +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_COUNT (2) +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_VERSION_IDX (0) +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARG0_VERSION_MINOR 15:0 // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARG0_VERSION_MAJOR 31:16 // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARG0_VERSION_MAJOR_V1 (1) // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_IDX (1) // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_INDEX 7:0 // output +#define NV0000_CTRL_PFM_REQ_HNDLR_PPM_ARGS_AVAILABLE_MASK 15:8 // output + +// +// PFM_REQ_HNDLR_PSHARE_PARAMS +// status bits +// +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_QUERY_TYPE 3:0 // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_QUERY_TYPE_CURRENT_INFO (0x00) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_QUERY_TYPE_SUPPORTED_FIELDS (0x01) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_QUERY_TYPE_CURRENT_LIMITS (0x02) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_TGPU 8:8 // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_TGPU_FALSE (0) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_TGPU_TRUE (1) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_DO_NOT_USE 14:9 // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_CTGP 15:15 // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_CTGP_FALSE (0) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_CTGP_TRUE (1) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_PPMD 16:16 // input & output +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_PPMD_FALSE (0) +#define NV0000_CTRL_PFM_REQ_HNDLR_PSHARE_PARAMS_STATUS_PPMD_TRUE (1) + +// +// A mapping from ACPI DSM and SW support dsm version. +// The SW might emulate 1x based on other parameters +// +#define NV0000_CTRL_PFM_REQ_HNDLR_ACPI_REVISION_SW_1X (0x00000100) +#define NV0000_CTRL_PFM_REQ_HNDLR_ACPI_REVISION_SW_2X (0x00000200) + + +#endif // _PLATFORM_REQUEST_HANDLER_UTILS_H_ + diff --git a/src/nvidia/inc/kernel/rmapi/control.h b/src/nvidia/inc/kernel/rmapi/control.h index e95f57638..ef13988b1 100644 --- a/src/nvidia/inc/kernel/rmapi/control.h +++ b/src/nvidia/inc/kernel/rmapi/control.h @@ -34,6 +34,18 @@ struct NVOC_EXPORTED_METHOD_DEF; typedef RS_RES_CONTROL_PARAMS_INTERNAL RmCtrlParams; +// RMCTRL_API_COPPY_FLAGS is used to specify control api copy behavior. +#define RMCTRL_API_COPY_FLAGS_NONE 0x00000000 + +// skip memory copy in api copy in +#define RMCTRL_API_COPY_FLAGS_SKIP_COPYIN NVBIT(0) + +// set control cache on api copy out +#define RMCTRL_API_COPY_FLAGS_SET_CONTROL_CACHE NVBIT(1) + +// skip copy out even for controls with RMCTRL_FLAGS_COPYOUT_ON_ERROR +#define RMCTRL_API_COPY_FLAGS_FORCE_SKIP_COPYOUT_ON_ERROR NVBIT(2) + // // RmCtrlExecuteCookie // @@ -49,6 +61,9 @@ struct RS_CONTROL_COOKIE // Rmctrl Flags NvU32 ctrlFlags; + // API Copy Flags + NvU32 apiCopyFlags; + // Required Access Rights for this command const RS_ACCESS_MASK rightsRequired; @@ -248,6 +263,33 @@ NV_STATUS embeddedParamCopyOut(RMAPI_PARAM_COPY *pParamCopy, RmCtrlParams *pRmC // ?? #define RMCTRL_FLAGS_ALLOW_WITHOUT_SYSMEM_ACCESS 0x000010000 +// +// This flag specifies that the control can be run by an admin privileged +// client running in a full SRIOV, vGPU-GSP-ENABLED hypervisor environment. +// Overrides regular privilege level flags. +// +#define RMCTRL_FLAGS_CPU_PLUGIN_FOR_VGPU_GSP 0x000020000 + +// +// This flag specifies that the control can be run by an admin privileged +// client running in a full SRIOV, vGPU-GSP-DISABLED hypervisor environment. +// Overrides regular privilege level flags. +// +#define RMCTRL_FLAGS_CPU_PLUGIN_FOR_SRIOV 0x000040000 + +// +// This flag specifies that the control can be run by an admin privileged +// client running in a non-SRIOV or SRIOV-Heavy hypervisor environment. +// Overrides regular privilege level flags. +// +#define RMCTRL_FLAGS_CPU_PLUGIN_FOR_LEGACY 0x000080000 + +// +// This flag specifies that the control can be run by an unprivileged +// client running in GSP-RM when SRIOV and vGPU-GSP are ENABLED. +// Overrides regular privilege level flags. +// +#define RMCTRL_FLAGS_GSP_PLUGIN_FOR_VGPU_GSP 0x000100000 // // 'ACCESS_RIGHTS' Attribute diff --git a/src/nvidia/inc/kernel/rmapi/exports.h b/src/nvidia/inc/kernel/rmapi/exports.h index d1a96247d..2c7f06634 100644 --- a/src/nvidia/inc/kernel/rmapi/exports.h +++ b/src/nvidia/inc/kernel/rmapi/exports.h @@ -56,7 +56,6 @@ void Nv04VidHeapControl (NVOS32_PARAMETERS*); void Nv04IdleChannels (NVOS30_PARAMETERS*); void Nv04MapMemory (NVOS33_PARAMETERS*); void Nv04UnmapMemory (NVOS34_PARAMETERS*); -void Nv04UpdateContextDma (NVOS37_PARAMETERS*); void Nv04I2CAccess (NVOS_I2C_ACCESS_PARAMS*); void Nv04AllocContextDma (NVOS39_PARAMETERS*); void Nv04BindContextDma (NVOS49_PARAMETERS*); @@ -77,7 +76,6 @@ void Nv04VidHeapControlUser (NVOS32_PARAMETERS*); void Nv04IdleChannelsUser (NVOS30_PARAMETERS*); void Nv04MapMemoryUser (NVOS33_PARAMETERS*); void Nv04UnmapMemoryUser (NVOS34_PARAMETERS*); -void Nv04UpdateContextDmaUser (NVOS37_PARAMETERS*); void Nv04I2CAccessUser (NVOS_I2C_ACCESS_PARAMS*); void Nv04AllocContextDmaUser (NVOS39_PARAMETERS*); void Nv04BindContextDmaUser (NVOS49_PARAMETERS*); @@ -98,7 +96,6 @@ void Nv04VidHeapControlKernel (NVOS32_PARAMETERS*); void Nv04IdleChannelsKernel (NVOS30_PARAMETERS*); void Nv04MapMemoryKernel (NVOS33_PARAMETERS*); void Nv04UnmapMemoryKernel (NVOS34_PARAMETERS*); -void Nv04UpdateContextDmaKernel (NVOS37_PARAMETERS*); void Nv04I2CAccessKernel (NVOS_I2C_ACCESS_PARAMS*); void Nv04AllocContextDmaKernel (NVOS39_PARAMETERS*); void Nv04BindContextDmaKernel (NVOS49_PARAMETERS*); diff --git a/src/nvidia/inc/kernel/rmapi/mapping_list.h b/src/nvidia/inc/kernel/rmapi/mapping_list.h index 55bc5ec73..16edf1823 100644 --- a/src/nvidia/inc/kernel/rmapi/mapping_list.h +++ b/src/nvidia/inc/kernel/rmapi/mapping_list.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -29,7 +29,6 @@ #include "os/os.h" #include "rmapi/resource.h" -struct P2PApi; typedef struct VirtualMemory VirtualMemory; typedef struct Memory Memory; @@ -59,7 +58,7 @@ struct _def_client_dma_mapping_info NvU64 FbApertureLen[NV_MAX_SUBDEVICES]; // GPU aperture mapped lengths MEMORY_DESCRIPTOR *pMemDesc; // Subregion to be mapped NvU32 Flags; - struct P2PApi *pP2PInfo; + NvBool bP2P; NvU32 gpuMask; ADDRESS_TRANSLATION addressTranslation; MEMORY_DESCRIPTOR *pBar1P2PVirtMemDesc; // The peer GPU mapped BAR1 region diff --git a/src/nvidia/inc/kernel/rmapi/rmapi.h b/src/nvidia/inc/kernel/rmapi/rmapi.h index f36e283b5..a82ba6385 100644 --- a/src/nvidia/inc/kernel/rmapi/rmapi.h +++ b/src/nvidia/inc/kernel/rmapi/rmapi.h @@ -262,16 +262,21 @@ NV_STATUS RmConfigSetEx (NvHandle, NvHandle, NvU32, NvP64, NvU32, NvBool); /** * Control cache API. - * Every function except rmapiControlCacheInit and rmapiControlCacheFree is thread safe. */ -void rmapiControlCacheInit(void); -NvBool rmapiControlIsCacheable(NvU32 flags, NvBool isGSPClient); -void* rmapiControlCacheGet(NvHandle hClient, NvHandle hObject, NvU32 cmd); +NV_STATUS rmapiControlCacheInit(void); +NvBool rmapiControlIsCacheable(NvU32 flags, NvU32 accessRight, NvBool bAllowInternal); +NvBool rmapiCmdIsCacheable(NvU32 cmd, NvBool bAllowInternal); +NV_STATUS rmapiControlCacheGet(NvHandle hClient, NvHandle hObject, NvU32 cmd, + void* params, NvU32 paramsSize); NV_STATUS rmapiControlCacheSet(NvHandle hClient, NvHandle hObject, NvU32 cmd, - void* params, NvU32 paramsSize); + const void* params, NvU32 paramsSize); +NV_STATUS rmapiControlCacheSetGpuInstForObject(NvHandle hClient, NvHandle hObject, NvU32 gpuInst); +void rmapiControlCacheFreeAllCacheForGpu(NvU32 gpuInst); +void rmapiControlCacheSetMode(NvU32 mode); +NvU32 rmapiControlCacheGetMode(void); void rmapiControlCacheFree(void); -void rmapiControlCacheFreeClient(NvHandle hClient); -void rmapiControlCacheFreeObject(NvHandle hClient, NvHandle hObject); +void rmapiControlCacheFreeClientEntry(NvHandle hClient); +void rmapiControlCacheFreeObjectEntry(NvHandle hClient, NvHandle hObject); typedef struct _RM_API_CONTEXT { NvU32 gpuMask; @@ -362,7 +367,7 @@ rmapiInitLockInfo #define RM_LOCK_MODULES_TMR RM_LOCK_MODULE_VAL(0x000800, 0x04) #define RM_LOCK_MODULES_I2C RM_LOCK_MODULE_VAL(0x001000, 0x00) -#define RM_LOCK_MODULES_GPS RM_LOCK_MODULE_VAL(0x001000, 0x01) +#define RM_LOCK_MODULES_PFM_REQ_HNDLR RM_LOCK_MODULE_VAL(0x001000, 0x01) #define RM_LOCK_MODULES_SEC2 RM_LOCK_MODULE_VAL(0x001000, 0x02) #define RM_LOCK_MODULES_THERM RM_LOCK_MODULE_VAL(0x001000, 0x03) #define RM_LOCK_MODULES_INFOROM RM_LOCK_MODULE_VAL(0x001000, 0x04) diff --git a/src/nvidia/inc/kernel/rmapi/rmapi_utils.h b/src/nvidia/inc/kernel/rmapi/rmapi_utils.h index 2bb6df47f..56efc8290 100644 --- a/src/nvidia/inc/kernel/rmapi/rmapi_utils.h +++ b/src/nvidia/inc/kernel/rmapi/rmapi_utils.h @@ -55,4 +55,9 @@ rmapiutilFreeClientAndDeviceHandles // NvBool rmapiutilIsExternalClassIdInternalOnly(NvU32 externalClassId); +// +// Return the flags and access right associated with this RM control command +// +NV_STATUS rmapiutilGetControlInfo(NvU32 cmd, NvU32 *pFlags, NvU32 *pAccessRight); + #endif /* RMAPI_UTILS_H */ diff --git a/src/nvidia/inc/kernel/virtualization/common_vgpu_mgr.h b/src/nvidia/inc/kernel/virtualization/common_vgpu_mgr.h new file mode 100644 index 000000000..d0a907d3d --- /dev/null +++ b/src/nvidia/inc/kernel/virtualization/common_vgpu_mgr.h @@ -0,0 +1,98 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __common_vgpu_mgr_h__ +#define __common_vgpu_mgr_h__ + +#include "gpu/gpu.h" +#include "gpu/fifo/kernel_fifo.h" +#include "ctrl/ctrla081.h" + +#include "containers/list.h" + +#define MAX_VGPU_TYPES_PER_PGPU NVA081_MAX_VGPU_TYPES_PER_PGPU +#define VGPU_CONFIG_PARAMS_MAX_LENGTH 1024 +#define VGPU_STRING_BUFFER_SIZE NVA081_VGPU_STRING_BUFFER_SIZE +#define VGPU_UUID_SIZE NVA081_VM_UUID_SIZE +#define VGPU_MAX_GFID 64 +#define VGPU_SIGNATURE_SIZE NVA081_VGPU_SIGNATURE_SIZE +#define MAX_VGPU_DEVICES_PER_PGPU NVA081_MAX_VGPU_PER_PGPU + +/* This structure represents the vGPU type's attributes */ +typedef struct +{ + NvU32 vgpuTypeId; + NvU8 vgpuName[VGPU_STRING_BUFFER_SIZE]; + NvU8 vgpuClass[VGPU_STRING_BUFFER_SIZE]; + NvU8 license[NV_GRID_LICENSE_INFO_MAX_LENGTH]; + NvU8 licensedProductName[NV_GRID_LICENSE_INFO_MAX_LENGTH]; + NvU32 maxInstance; + NvU32 numHeads; + NvU32 maxResolutionX; + NvU32 maxResolutionY; + NvU32 maxPixels; + NvU32 frlConfig; + NvU32 cudaEnabled; + NvU32 eccSupported; + NvU32 gpuInstanceSize; + NvU32 multiVgpuSupported; + NvU64 vdevId NV_ALIGN_BYTES(8); + NvU64 pdevId NV_ALIGN_BYTES(8); + NvU64 profileSize NV_ALIGN_BYTES(8); + NvU64 fbLength NV_ALIGN_BYTES(8); + NvU64 gspHeapSize NV_ALIGN_BYTES(8); + NvU64 fbReservation NV_ALIGN_BYTES(8); + NvU64 mappableVideoSize NV_ALIGN_BYTES(8); + NvU32 encoderCapacity; + NvU64 bar1Length NV_ALIGN_BYTES(8); + NvU32 frlEnable; + NvU32 gpuDirectSupported; + NvU32 nvlinkP2PSupported; + NvU8 vgpuExtraParams[VGPU_CONFIG_PARAMS_MAX_LENGTH]; + NvU8 vgpuSignature[VGPU_SIGNATURE_SIZE]; +} VGPU_TYPE; + +MAKE_LIST(VGPU_TYPE_LIST, VGPU_TYPE); + +void +vgpuMgrFillVgpuType(NVA081_CTRL_VGPU_INFO *pVgpuInfo, VGPU_TYPE *pVgpuTypeNode); + +NV_STATUS +vgpuMgrReserveSystemChannelIDs(OBJGPU *pGpu, + VGPU_TYPE *vgpuTypeInfo, + NvU32 gfid, + NvU32 *pChidOffset, + NvHandle hClient, + NvU32 numChannels, + NvU32 engineFifoListNumEntries, + FIFO_ENGINE_LIST *engineFifoList); + +void +vgpuMgrFreeSystemChannelIDs(OBJGPU *pGpu, + NvU32 gfid, + NvU32 *pChidOffset, + NvHandle hClient, + NvU32 engineFifoListNumEntries, + FIFO_ENGINE_LIST *engineFifoList); + +#endif // __common_vgpu_mgr_h__ diff --git a/src/nvidia/inc/kernel/virtualization/kernel_hostvgpudeviceapi.h b/src/nvidia/inc/kernel/virtualization/kernel_hostvgpudeviceapi.h new file mode 100644 index 000000000..3d5d0c608 --- /dev/null +++ b/src/nvidia/inc/kernel/virtualization/kernel_hostvgpudeviceapi.h @@ -0,0 +1,3 @@ + +#include "g_kernel_hostvgpudeviceapi_nvoc.h" + diff --git a/src/nvidia/inc/kernel/virtualization/kernel_vgpu_mgr.h b/src/nvidia/inc/kernel/virtualization/kernel_vgpu_mgr.h new file mode 100644 index 000000000..ed6a5090a --- /dev/null +++ b/src/nvidia/inc/kernel/virtualization/kernel_vgpu_mgr.h @@ -0,0 +1,3 @@ + +#include "g_kernel_vgpu_mgr_nvoc.h" + diff --git a/src/nvidia/inc/kernel/virtualization/vgpuconfigapi.h b/src/nvidia/inc/kernel/virtualization/vgpuconfigapi.h new file mode 100644 index 000000000..cb5cb3d52 --- /dev/null +++ b/src/nvidia/inc/kernel/virtualization/vgpuconfigapi.h @@ -0,0 +1,3 @@ + +#include "g_vgpuconfigapi_nvoc.h" + diff --git a/src/nvidia/inc/libraries/mmu/gmmu_fmt.h b/src/nvidia/inc/libraries/mmu/gmmu_fmt.h index e513fc411..59d7bbb8f 100644 --- a/src/nvidia/inc/libraries/mmu/gmmu_fmt.h +++ b/src/nvidia/inc/libraries/mmu/gmmu_fmt.h @@ -23,6 +23,8 @@ #ifndef _NV_GMMU_FMT_H_ #define _NV_GMMU_FMT_H_ +#include + #ifdef __cplusplus extern "C" { #endif @@ -173,11 +175,6 @@ typedef struct GMMU_COMPR_INFO GMMU_COMPR_INFO; */ #define GMMU_FMT_MAX_ENTRY_SIZE 16 -/*! - * Maximum number of page levels across the supported formats. - */ -#define GMMU_FMT_MAX_LEVELS 6 - /*! * Default version specifier for API args to indicate no preference. * This is not a real version number and not part of the diff --git a/src/nvidia/inc/libraries/mmu/mmu_fmt.h b/src/nvidia/inc/libraries/mmu/mmu_fmt.h index 774cc3d28..c7c52c2fa 100644 --- a/src/nvidia/inc/libraries/mmu/mmu_fmt.h +++ b/src/nvidia/inc/libraries/mmu/mmu_fmt.h @@ -103,6 +103,17 @@ const MMU_FMT_LEVEL *mmuFmtGetNextLevel( const MMU_FMT_LEVEL *pLevelFmt, const MMU_FMT_LEVEL *pTargetFmt); +/*! + * Return a level description from the format. Used for Verif. + * + * @returns const char* string description of the level. + */ +const char* +mmuFmtConvertLevelIdToSuffix +( + const MMU_FMT_LEVEL *pLevelFmt +); + /*! * Bitmask of VA covered by a given level. * e.g. for the root level this is the maximum VAS limit. diff --git a/src/nvidia/inc/libraries/mmu/mmu_walk.h b/src/nvidia/inc/libraries/mmu/mmu_walk.h index 5a1f7400d..0c64027e4 100644 --- a/src/nvidia/inc/libraries/mmu/mmu_walk.h +++ b/src/nvidia/inc/libraries/mmu/mmu_walk.h @@ -509,6 +509,11 @@ struct MMU_MAP_TARGET * Callback to map the batch of entries. */ MmuWalkCBMapNextEntries *MapNextEntries; + + /*! + * Page array granularity of the physical target memory + */ + NvU32 pageArrayGranularity; }; /*----------------------------Public Interface--------------------------------*/ diff --git a/src/nvidia/inc/libraries/nvoc/runtime.h b/src/nvidia/inc/libraries/nvoc/runtime.h index 410493a89..bf59317e4 100644 --- a/src/nvidia/inc/libraries/nvoc/runtime.h +++ b/src/nvidia/inc/libraries/nvoc/runtime.h @@ -102,6 +102,7 @@ Dynamic *objFindAncestor_IMPL(Dynamic *pDynamic, NVOC_CLASS_ID classId); * This is a linear-time operation. */ const struct NVOC_EXPORTED_METHOD_DEF* objGetExportedMethodDef_IMPL(Dynamic* pObj, NvU32 methodId); +const struct NVOC_EXPORTED_METHOD_DEF* nvocGetExportedMethodDefFromMethodInfo_IMPL(const struct NVOC_EXPORT_INFO *pExportInfo, NvU32 methodId); /*! * @brief Dynamic cast by class id diff --git a/src/nvidia/inc/libraries/nvport/debug.h b/src/nvidia/inc/libraries/nvport/debug.h index 1390774e2..fe7a94d7a 100644 --- a/src/nvidia/inc/libraries/nvport/debug.h +++ b/src/nvidia/inc/libraries/nvport/debug.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -278,8 +278,6 @@ PORT_DEBUG_INLINE void portDbgExPrintfLevel(NvU32 level, const char *format, ... #include "nvport/inline/debug_qnx.h" #elif NVOS_IS_DCECORE #include "nvport/inline/debug_dcecore.h" -#elif defined(GSP_PLUGIN_BUILD) -#include "nvport/inline/debug_vgpu_gsp.h" #else #if PORT_IS_KERNEL_BUILD diff --git a/src/nvidia/inc/libraries/resserv/resserv.h b/src/nvidia/inc/libraries/resserv/resserv.h index 7407e1cc3..7085bf8a5 100644 --- a/src/nvidia/inc/libraries/resserv/resserv.h +++ b/src/nvidia/inc/libraries/resserv/resserv.h @@ -136,22 +136,16 @@ typedef void *PUID_TOKEN; /// Client handles must start at this base value #define RS_CLIENT_HANDLE_BASE 0xC1D00000 -/// -/// Internal Client handles must start at this base value -/// at either of these two bases -/// +/// Internal Client handles start at this base value #define RS_CLIENT_INTERNAL_HANDLE_BASE 0xC1E00000 -#define RS_CLIENT_INTERNAL_HANDLE_BASE_EX 0xC1F00000 - // // Print a warning if any client's resource count exceeds this // threshold. Unless this was intentional, this is likely a client bug. // #define RS_CLIENT_RESOURCE_WARNING_THRESHOLD 100000 - -/// 0xFFFF max client handles. +#define RS_CLIENT_HANDLE_MAX 0x100000 // Must be power of two #define RS_CLIENT_HANDLE_BUCKET_COUNT 0x400 // 1024 #define RS_CLIENT_HANDLE_BUCKET_MASK 0x3FF diff --git a/src/nvidia/inc/libraries/resserv/rs_client.h b/src/nvidia/inc/libraries/resserv/rs_client.h index f2a18d868..04a6ce76b 100644 --- a/src/nvidia/inc/libraries/resserv/rs_client.h +++ b/src/nvidia/inc/libraries/resserv/rs_client.h @@ -206,6 +206,19 @@ public: */ virtual NV_STATUS clientValidate(RsClient *pClient, const API_SECURITY_INFO * pSecInfo); + /** + * Stub virtual function + * @param[in] NvHandle hClient + */ + virtual RS_PRIV_LEVEL clientGetCachedPrivilege(RsClient *pClient); + + /** + * Stub virtual function + * @param[in] NvHandle hClient + * @param[in] RS_PRIV_LEVEL privLevel + */ + virtual NvBool clientIsAdmin(RsClient *pClient, RS_PRIV_LEVEL privLevel); + /** * Allocate a resource in RM for this client * @param[in] pClient This client diff --git a/src/nvidia/inc/libraries/resserv/rs_resource.h b/src/nvidia/inc/libraries/resserv/rs_resource.h index e44500356..eccebe706 100644 --- a/src/nvidia/inc/libraries/resserv/rs_resource.h +++ b/src/nvidia/inc/libraries/resserv/rs_resource.h @@ -233,6 +233,11 @@ public: */ virtual NvBool resCanCopy(RsResource *pResource); + /** + * Returns TRUE if the resources are duplicates + */ + virtual NV_STATUS resIsDuplicate(RsResource *pResource, NvHandle hMemory, NvBool *pDuplicate); + /** * Resource destructor * @param[in] pResource Resource object to destruct diff --git a/src/nvidia/inc/libraries/resserv/rs_server.h b/src/nvidia/inc/libraries/resserv/rs_server.h index 17c561cb7..55297898f 100644 --- a/src/nvidia/inc/libraries/resserv/rs_server.h +++ b/src/nvidia/inc/libraries/resserv/rs_server.h @@ -155,6 +155,10 @@ struct RsServer /// If true, control call param copies will be performed outside the top/api lock NvBool bUnlockedParamCopy; + // If true, calls annotated with ROUTE_TO_PHYISCAL will not grab global gpu locks + // (and the readonly API lock). + NvBool bRouteToPhysicalLockBypass; + /** * Setting this flag to false disables any attempts to * automatically acquire access rights or to control access to resources by @@ -173,6 +177,7 @@ struct RsServer RsShareList globalInternalSharePolicyList; NvU32 internalHandleBase; + NvU32 clientHandleBase; NvU32 activeClientCount; NvU64 activeResourceCount; @@ -340,6 +345,14 @@ RS_SHARE_ITERATOR serverShareIter(RsServer *pServer, NvU32 internalClassId); */ NvBool serverShareIterNext(RS_SHARE_ITERATOR*); +/** + * Set fixed client handle base in case clients wants to use a different + * base for client allocations + * @param[in] pServer + * @param[in] clientHandleBase + */ + NV_STATUS serverSetClientHandleBase(RsServer *pServer, NvU32 clientHandleBase); + /** * Allocate a resource. Assumes top-level lock has been taken. diff --git a/src/nvidia/interface/acpidsmguids.h b/src/nvidia/interface/acpidsmguids.h new file mode 100644 index 000000000..38b867a22 --- /dev/null +++ b/src/nvidia/interface/acpidsmguids.h @@ -0,0 +1,90 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2000-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef ACPIDSMGUIDS_H +#define ACPIDSMGUIDS_H + +#include "nvcd.h" + +// +// These guids are used in linux. +// The same guid values are defined in a windows way in guids.c +// These revision_ids are also defined in platform/nbsi/nbsi_read.h, nvmxm.h, nvhybridacpi.h, nbci.h. +// Those files should be changed and these used. +// +#define NBSI_DSM_GUID_STR { 0xA6, 0x69, 0x86, 0x99, 0xE9, 0x8B, 0xFB, 0x49, \ + 0xBD, 0xDB, 0x51, 0xA1, 0xEF, 0xE1, 0x9C, 0x3D } +#define NBSI_REVISION_ID 0x00000101 + +#define MXM_DSM_GUID_STR { 0x00, 0xA4, 0x04, 0x40, 0x7D, 0x91, 0xF2, 0x4C, \ + 0xB8, 0x9C, 0x79, 0xB6, 0x2F, 0xD5, 0x56, 0x65} +#define ACPI_MXM_REVISION_ID 0x00000300 + +#define NVHG_DSM_GUID_STR { 0xA0, 0xA0, 0x95, 0x9D, 0x60, 0x00, 0x48, 0x4d, \ + 0xB3, 0x4D, 0x7E, 0x5F, 0xEA, 0x12, 0x9F, 0xD4} +#define NVHG_REVISION_ID 0x00000102 + +#define NBCI_DSM_GUID_STR { 0x75, 0x0B, 0xA5, 0xD4, 0xC7, 0x65, 0xF7, 0x46, \ + 0xBF, 0xB7, 0x41, 0x51, 0x4C, 0xEA, 0x02, 0x44} +#define NBCI_REVISION_ID 0x00000102 + +#define NVOP_DSM_GUID_STR { 0xF8, 0xD8, 0x86, 0xA4, 0xDA, 0x0B, 0x1B, 0x47, \ + 0xA7, 0x2B, 0x60, 0x42, 0xA6, 0xB5, 0xBE, 0xE0} +#define NVOP_REVISION_ID 0x00000100 + +#define PCFG_DSM_GUID_STR { 0x7D, 0x14, 0xC6, 0x81, 0x5F, 0x73, 0xD9, 0x42, \ + 0x9E, 0x41, 0xB0, 0x02, 0xCB, 0xC6, 0x57, 0x1D} +#define PCFG_REVISION_ID 0x00000100 + +#define GPS_2X_REVISION_ID 0x00000200 + +#define GPS_DSM_GUID_STR { 0x01, 0x2D, 0x13, 0xA3, 0xDA, 0x8C, 0xBA, 0x49, \ + 0xA5, 0x2E, 0xBC, 0x9D, 0x46, 0xDF, 0x6B, 0x81}, +#define GPS_REVISION_ID 0x00000100 + +#define JT_DSM_GUID_STR { 0x51, 0xA3, 0xEC, 0xCB, 0x7B, 0x06, 0x24, 0x49, \ + 0x9C, 0xBD, 0xB4, 0x6B, 0x00, 0xB8, 0x6F, 0x34} +#define JT_REVISION_ID 0x00000103 + +// PEX_DSM_GUID {E5C937D0-3553-4D7A-9117-EA4D19C3434D} +#define PEX_DSM_GUID_STR { 0xD0, 0x37, 0xC9, 0xE5, 0x53, 0x35, 0x7A, 0x4D, \ + 0x91, 0x17, 0xEA, 0x4D, 0x19, 0xC3, 0x43, 0x4D} +#define PEX_REVISION_ID 0x00000002 + +#define NVPCF_ACPI_DSM_REVISION_ID 0x00000100 + +#define NVPCF_2X_ACPI_DSM_REVISION_ID 0x00000200 + +extern const GUID NBCI_DSM_GUID; +extern const GUID NBSI_DSM_GUID; +extern const GUID NVHG_DSM_GUID; +extern const GUID NVOP_DSM_GUID; +extern const GUID SPB_DSM_GUID; +extern const GUID DSM_MXM_GUID; +extern const GUID PCFG_DSM_GUID; +extern const GUID GPS_DSM_GUID; +extern const GUID PEX_DSM_GUID; +extern const GUID JT_DSM_GUID; +extern const GUID NVPCF_ACPI_DSM_GUID; + +#endif // ACPIDSMGUIDS_H diff --git a/src/nvidia/interface/acpigenfuncs.h b/src/nvidia/interface/acpigenfuncs.h index 54992f0bb..0e98fc909 100644 --- a/src/nvidia/interface/acpigenfuncs.h +++ b/src/nvidia/interface/acpigenfuncs.h @@ -29,7 +29,55 @@ #define NV_ACPI_DSM_READ_SIZE (4*1024) #define NV_ACPI_GENERIC_FUNC_START 0x0200 -#define NV_ACPI_GENERIC_FUNC_COUNT 9 +#define NV_ACPI_GENERIC_FUNC_COUNT 8 + +// Only use these when using the generic function ACPI_DSM_FUNCTION_CURRENT. +#define NV_ACPI_GENERIC_FUNC_DISPLAYSTATUS (NV_ACPI_GENERIC_FUNC_START+0x00) // Get Display & Hot-Key information +#define NV_ACPI_GENERIC_FUNC_MDTL (NV_ACPI_GENERIC_FUNC_START+0x01) // Display Toggle List +#define NV_ACPI_GENERIC_FUNC_GETOBJBYTYPE (NV_ACPI_GENERIC_FUNC_START+0x02) // Get the firmware object +#define NV_ACPI_GENERIC_FUNC_GETALLOBJS (NV_ACPI_GENERIC_FUNC_START+0x03) // Get the directory and all objects +#define NV_ACPI_GENERIC_FUNC_GETEVENTLIST (NV_ACPI_GENERIC_FUNC_START+0x04) // Get the List of required Event Notifiers and their meaning +#define NV_ACPI_GENERIC_FUNC_CALLBACKS (NV_ACPI_GENERIC_FUNC_START+0x05) // Get the list of system-required callbacks +#define NV_ACPI_GENERIC_FUNC_GETBACKLIGHT (NV_ACPI_GENERIC_FUNC_START+0x06) // Get the Backlight +#define NV_ACPI_GENERIC_FUNC_MSTL (NV_ACPI_GENERIC_FUNC_START+0x07) // Get Multiple Stream Topology Toggle info + +// structure used for NV_ACPI_GENERIC_FUNC_CTL_TESTSUBFUNCENABLED and NV_ACPI_GENERIC_FUNC_CTL_REMAPFUNC calls. +typedef struct +{ + ACPI_DSM_FUNCTION acpiDsmFunction; + NvU32 acpiDsmSubFunction; + NvU32 status; +} DSMTESTCTL, *PDSMTESTCTL; + +// when adding new generic functions, change NV_ACPI_GENERIC_FUNC_LAST_SUBFUNCTION to last entry. +#define NV_ACPI_GENERIC_FUNC_LAST_SUBFUNCTION (NV_ACPI_GENERIC_FUNC_MSTL) +ct_assert(NV_ACPI_GENERIC_FUNC_COUNT == ((NV_ACPI_GENERIC_FUNC_LAST_SUBFUNCTION-NV_ACPI_GENERIC_FUNC_START)+1)); + +// These are not DSM functions, but used by clients (such as DD) to choose special ctrl0073 processing related to DSM. +#define NV_ACPI_GENERIC_FUNC_CTL_START 0x0600 +#define NV_ACPI_GENERIC_FUNC_CTL_TESTSUBFUNCENABLED (NV_ACPI_GENERIC_FUNC_CTL_START+0x00) // exec testIfDsmSubFunctionEnabled +#define NV_ACPI_GENERIC_FUNC_CTL_REMAPFUNC (NV_ACPI_GENERIC_FUNC_CTL_START+0x01) // exec remapDsmFunctionAndSubFunction +#define NV_ACPI_GENERIC_FUNC_CTL_GETFUNCSUPPORT (NV_ACPI_GENERIC_FUNC_CTL_START+0x02) // get generic dsm supported functions + // +// when adding new control functions, change NV_ACPI_GENERIC_FUNC_CTL_LAST_SUBFUNCTION to last entry. +#define NV_ACPI_GENERIC_FUNC_CTL_LAST_SUBFUNCTION (NV_ACPI_GENERIC_FUNC_CTL_GETFUNCSUPPORT) +#define NV_ACPI_GENERIC_FUNC_CTL_COUNT ((NV_ACPI_GENERIC_FUNC_CTL_LAST_SUBFUNCTION-NV_ACPI_GENERIC_FUNC_CTL_START)+1) + +#define IS_GENERIC_DSM_FUNC_SUPPORTED(package, subfunc) (((package >> (subfunc-NV_ACPI_GENERIC_FUNC_START)) & NVBIT(0)) ? true : false) + +// status for dsm functions. +#define DSM_FUNC_STATUS_UNKNOWN 0 // untried +#define DSM_FUNC_STATUS_FAILED 1 // tried but failed +#define DSM_FUNC_STATUS_SUCCESS 2 // tried and successful +#define DSM_FUNC_STATUS_DISABLED 3 // disabled via regkey +#define DSM_FUNC_STATUS_OVERRIDE 4 // regkey or code hack override + +// +// common NV definitions used in ACPI dsm calls in particular. +// +#define NV_ACPI_ALL_FUNC_SUPPORT 0x00000000 // Common is supported subfunction. +#define NV_ACPI_ALL_FUNC_SUPPORTED NVBIT(NV_ACPI_ALL_FUNC_SUPPORT) // is common Function supported? +#define NV_ACPI_ALL_SUBFUNC_UNKNOWN 0xFFFFFFFF // Common define for unknown ACPI sub-function #endif // _ACPIGENFUNCS_H_ diff --git a/src/nvidia/interface/deprecated/rmapi_deprecated_allocmemory.c b/src/nvidia/interface/deprecated/rmapi_deprecated_allocmemory.c index 757961fc5..12bc7e0eb 100644 --- a/src/nvidia/interface/deprecated/rmapi_deprecated_allocmemory.c +++ b/src/nvidia/interface/deprecated/rmapi_deprecated_allocmemory.c @@ -410,6 +410,14 @@ _rmAllocMemoryList goto done; pageArrayBase = NvP64_PLUS_OFFSET(*pAddress, NV_OFFSETOF(Nv01MemoryList, pageNumber)); + + // Prevent integer overflow when calculating pageArraySize + if (pMemoryList->pageCount > NV_U32_MAX / sizeof(NvU64)) + { + status = NV_ERR_INVALID_ARGUMENT; + goto done; + } + pageArraySize = sizeof(NvU64) * pMemoryList->pageCount; status = pContext->CopyUser(pContext, RMAPI_DEPRECATED_COPYIN, RMAPI_DEPRECATED_BUFFER_ALLOCATE, diff --git a/src/nvidia/interface/deprecated/rmapi_deprecated_control.c b/src/nvidia/interface/deprecated/rmapi_deprecated_control.c index d66faaf31..e8b9de2d0 100644 --- a/src/nvidia/interface/deprecated/rmapi_deprecated_control.c +++ b/src/nvidia/interface/deprecated/rmapi_deprecated_control.c @@ -104,7 +104,8 @@ RmDeprecatedControlHandler RmDeprecatedGetControlHandler(NVOS54_PARAMETERS *pArg serverGetClientUnderLock(&g_resServ, pArgs->hClient, &pClient), return NULL); - gpuGetByHandle(pClient, pArgs->hObject, NULL, &pGpu); + // pGpu is expected to be NULL on some controls, addi ng a void to avoid coverity failure. + (void)gpuGetByHandle(pClient, pArgs->hObject, NULL, &pGpu); // search rmDeprecatedControlTable for handler for (i = 0; rmDeprecatedControlTable[i].cmd != 0; i++) @@ -740,3 +741,4 @@ done: return status; } + diff --git a/src/nvidia/interface/deprecated/rmapi_deprecated_misc.c b/src/nvidia/interface/deprecated/rmapi_deprecated_misc.c index 5d39ead76..9d70e68e6 100644 --- a/src/nvidia/interface/deprecated/rmapi_deprecated_misc.c +++ b/src/nvidia/interface/deprecated/rmapi_deprecated_misc.c @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ + +#include "nvport/nvport.h" #include "deprecated/rmapi_deprecated.h" #include "class/cl0070.h" // NV01_MEMORY_VIRTUAL/NV01_MEMORY_SYSTEM_DYNAMIC @@ -247,6 +249,7 @@ RmDeprecatedIdleChannels { NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS params = {0}; NV_STATUS status; + NvU32 handleBufferSize; void *phClients = 0; void *phDevices = 0; void *phChannels = 0; @@ -257,13 +260,19 @@ RmDeprecatedIdleChannels params.flags = pArgs->flags; params.timeout = pArgs->timeout; + if (!portSafeMulU32(pArgs->numChannels, sizeof(NvU32), &handleBufferSize)) + { + status = NV_ERR_INVALID_ARGUMENT; + goto done; + } + // XXX this should have a max - but copying old behavior for now if (DRF_VAL(OS30, _FLAGS, _CHANNEL, pArgs->flags) == NVOS30_FLAGS_CHANNEL_LIST && params.numChannels) { // Copy-in phClients status = pContext->CopyUser(pContext, RMAPI_DEPRECATED_COPYIN, RMAPI_DEPRECATED_BUFFER_ALLOCATE, - pArgs->phClients, pArgs->numChannels * sizeof(NvU32), &phClients); + pArgs->phClients, handleBufferSize, &phClients); if (status != NV_OK) goto done; @@ -271,7 +280,7 @@ RmDeprecatedIdleChannels // Copy-in phDevices status = pContext->CopyUser(pContext, RMAPI_DEPRECATED_COPYIN, RMAPI_DEPRECATED_BUFFER_ALLOCATE, - pArgs->phDevices, pArgs->numChannels * sizeof(NvU32), &phDevices); + pArgs->phDevices, handleBufferSize, &phDevices); if (status != NV_OK) goto done; @@ -279,7 +288,7 @@ RmDeprecatedIdleChannels // Copy-in phChannels status = pContext->CopyUser(pContext, RMAPI_DEPRECATED_COPYIN, RMAPI_DEPRECATED_BUFFER_ALLOCATE, - pArgs->phChannels, pArgs->numChannels * sizeof(NvU32), &phChannels); + pArgs->phChannels, handleBufferSize, &phChannels); if (status != NV_OK) goto done; @@ -295,19 +304,19 @@ done: if (phClients) { pContext->CopyUser(pContext, RMAPI_DEPRECATED_COPYRELEASE, RMAPI_DEPRECATED_BUFFER_ALLOCATE, - pArgs->phClients, pArgs->numChannels * sizeof(NvU32), &phClients); + pArgs->phClients, handleBufferSize, &phClients); } if (phDevices) { pContext->CopyUser(pContext, RMAPI_DEPRECATED_COPYRELEASE, RMAPI_DEPRECATED_BUFFER_ALLOCATE, - pArgs->phDevices, pArgs->numChannels * sizeof(NvU32), &phDevices); + pArgs->phDevices, handleBufferSize, &phDevices); } if (phChannels) { pContext->CopyUser(pContext, RMAPI_DEPRECATED_COPYRELEASE, RMAPI_DEPRECATED_BUFFER_ALLOCATE, - pArgs->phChannels, pArgs->numChannels * sizeof(NvU32), &phChannels); + pArgs->phChannels, handleBufferSize, &phChannels); } pArgs->status = status; } diff --git a/src/nvidia/interface/deprecated/rmapi_deprecated_utils.c b/src/nvidia/interface/deprecated/rmapi_deprecated_utils.c index 1e9110813..024a27495 100644 --- a/src/nvidia/interface/deprecated/rmapi_deprecated_utils.c +++ b/src/nvidia/interface/deprecated/rmapi_deprecated_utils.c @@ -28,7 +28,6 @@ #include "ctrl/ctrl0080/ctrl0080gpu.h" // NV0080_CTRL_CMD_GPU_FIND_SUBDEVICE_HANDLE #include "nvos.h" - NV_STATUS RmDeprecatedGetHandleParent ( diff --git a/src/nvidia/interface/nv_sriov_defines.h b/src/nvidia/interface/nv_sriov_defines.h new file mode 100644 index 000000000..3a60a1ecc --- /dev/null +++ b/src/nvidia/interface/nv_sriov_defines.h @@ -0,0 +1,72 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * @file nv_sriov_defines.h + * @brief Defines for doorbell tokens and scratch registers index. + * + * Define:- + * - VF scratch registers index used in VGPU-GSP RPC setup + * - VF scratch registers index used in FECS tracing support + * - Doorbell interrupt handles for Guest RM to GSP-Plugin communication + * - Doorbell interrupt handles for Host CPU-Plugin to GSP-Plugin communication + */ + +// +// Ring Doorbell register to setup GSP Notification interrupt +// We have total 4096 bits for notifications (128 notify leaf registers). +// Setup to use leaf register index 0 for all communications from Guest VM to GSP-Plugin +// bit index 0x0 to 0xF used for CPU-Plugin <----> GSP-Plugin communication +// bit index 0x10 to 0x1F used for Guest VM <----> GSP-Plugin communication +// bit index 0x10 in the gsp notify register is used for RPC setup request +// bit index 0x11 in the gsp notify register is used for sending RPC send request +// + +// These defines are applicable per VM i.e. replicated per VM. +#define NV_DOORBELL_NOTIFY_LEAF_VF_CPU_PLUGIN_REQUEST 1:1 +#define NV_DOORBELL_NOTIFY_LEAF_VF_CPU_PLUGIN_REQUEST_EN (0x1) +#define NV_DOORBELL_NOTIFY_LEAF_VF_CPU_PLUGIN_REQUEST_DIS (0x0) +#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_REQUEST 2:2 +#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_REQUEST_EN (0x1) +#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_REQUEST_DIS (0x0) +#define NV_DOORBELL_NOTIFY_LEAF_VF_RPC_SETUP_REQUEST 16:16 +#define NV_DOORBELL_NOTIFY_LEAF_VF_RPC_SETUP_REQUEST_EN (0x1) +#define NV_DOORBELL_NOTIFY_LEAF_VF_RPC_SETUP_REQUEST_DIS (0x0) +#define NV_DOORBELL_NOTIFY_LEAF_VF_RPC_MESSAGE_REQUEST 17:17 +#define NV_DOORBELL_NOTIFY_LEAF_VF_RPC_MESSAGE_REQUEST_EN (0x1) +#define NV_DOORBELL_NOTIFY_LEAF_VF_RPC_MESSAGE_REQUEST_DIS (0x0) + +#define NV_DOORBELL_NOTIFY_LEAF_VF_CPU_PLUGIN_HANDLE (0 ? NV_DOORBELL_NOTIFY_LEAF_VF_CPU_PLUGIN_REQUEST) +#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_HANDLE (0 ? NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_REQUEST) +#define NV_DOORBELL_NOTIFY_LEAF_VF_RPC_SETUP_HANDLE (0 ? NV_DOORBELL_NOTIFY_LEAF_VF_RPC_SETUP_REQUEST) +#define NV_DOORBELL_NOTIFY_LEAF_VF_RPC_MESSAGE_HANDLE (0 ? NV_DOORBELL_NOTIFY_LEAF_VF_RPC_MESSAGE_REQUEST) + +// current write offset of the FECS trace buffer +#define NV_VF_SCRATCH_REGISTER_FECS_TRACE_WR_RD_OFFSET 0x0 +// current read offset of the FECS trace buffer +#define NV_VF_SCRATCH_REGISTER_FECS_TRACE_RD_RD_OFFSET 0x1 + +// used in VGPU-GSP RPC setup +#define NV_VF_SCRATCH_REGISTER_GUEST_RPC_LO 0x2 +// used in VGPU-GSP RPC setup +#define NV_VF_SCRATCH_REGISTER_GUEST_RPC_HI 0x3 diff --git a/src/nvidia/interface/nv_uvm_types.h b/src/nvidia/interface/nv_uvm_types.h index dd114310f..800a8996b 100644 --- a/src/nvidia/interface/nv_uvm_types.h +++ b/src/nvidia/interface/nv_uvm_types.h @@ -868,6 +868,16 @@ typedef struct UvmGpuAccessCntrConfig_tag NvU32 threshold; } UvmGpuAccessCntrConfig; +// +// When modifying this enum, make sure they are compatible with the mirrored +// MEMORY_PROTECTION enum in phys_mem_allocator.h. +// +typedef enum UvmPmaGpuMemoryType_tag +{ + UVM_PMA_GPU_MEMORY_TYPE_UNPROTECTED = 0, + UVM_PMA_GPU_MEMORY_TYPE_PROTECTED = 1 +} UVM_PMA_GPU_MEMORY_TYPE; + typedef UvmGpuChannelInfo gpuChannelInfo; typedef UvmGpuChannelAllocParams gpuChannelAllocParams; typedef UvmGpuCaps gpuCaps; diff --git a/src/nvidia/interface/nvrm_registry.h b/src/nvidia/interface/nvrm_registry.h index 480940a3c..fac71309f 100644 --- a/src/nvidia/interface/nvrm_registry.h +++ b/src/nvidia/interface/nvrm_registry.h @@ -448,6 +448,9 @@ // Type DWORD (Boolean) // Override any other settings and disable GSP-RM offload. +#define NV_REG_STR_RM_GSP_STATUS_QUEUE_SIZE "RmGspStatusQueueSize" +// TYPE DWORD +// Set the GSP status queue size in KB (for GSP to CPU RPC status and event communication) #define NV_REG_STR_RM_MSG "RmMsg" // Type String: Set parameters for RM DBG_PRINTF. Only for builds with printfs enabled. @@ -693,14 +696,9 @@ #define NV_REG_STR_RM_READONLY_GPU_LOCK_MODULE_WORKITEM_ENABLE (0x00000001) -// Enable support for CACHEABLE rmapi control flag -// 0: never cache any controls -// 1 (default): cache only ROUTE_TO_PHYSICAL controls, and only if GSP-RM is running -// 2: cache all controls +// Mode for CACHEABLE rmapi control +// RMCTRL cache mode defined in ctrl0000system.h #define NV_REG_STR_RM_CACHEABLE_CONTROLS "RmEnableCacheableControls" -#define NV_REG_STR_RM_CACHEABLE_CONTROLS_DISABLE 0 -#define NV_REG_STR_RM_CACHEABLE_CONTROLS_GSP_ONLY 1 -#define NV_REG_STR_RM_CACHEABLE_CONTROLS_ENABLE 2 // Type DWORD // This regkey forces for Maxwell+ that on FB Unload we wait for FB pull before issuing the @@ -1073,6 +1071,14 @@ // Disable noncontig vidmem allocation // +// Type DWORD +// Encoding -- 0 -- Disable +// -- 1 -- Enable +// Enable MemoryMapper API (in-development). Currently disabled by default +#define NV_REG_ENABLE_MEMORY_MAPPER_API "RMEnableMemoryMapperApi" +#define NV_REG_ENABLE_MEMORY_MAPPER_API_FALSE 0 +#define NV_REG_ENABLE_MEMORY_MAPPER_API_TRUE 1 + #define NV_REG_STR_RM_FBSR_PAGED_DMA "RmFbsrPagedDMA" #define NV_REG_STR_RM_FBSR_PAGED_DMA_ENABLE 1 #define NV_REG_STR_RM_FBSR_PAGED_DMA_DISABLE 0 @@ -1485,6 +1491,10 @@ #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN5_DEFAULT (0x00000000) #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN5_ENABLE (0x00000001) #define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN5_DISABLE (0x00000002) +#define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN6 9:8 +#define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN6_DEFAULT (0x00000000) +#define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN6_ENABLE (0x00000001) +#define NV_REG_STR_RM_PCIE_LINK_SPEED_ALLOW_GEN6_DISABLE (0x00000002) #define NV_REG_STR_RM_PCIE_LINK_SPEED_LOCK_AT_LOAD 31:31 #define NV_REG_STR_RM_PCIE_LINK_SPEED_LOCK_AT_LOAD_DISABLE (0x00000000) #define NV_REG_STR_RM_PCIE_LINK_SPEED_LOCK_AT_LOAD_ENABLE (0x00000001) @@ -1580,6 +1590,18 @@ // 1 - Force Enable Gen2 (to invalidate PDB_PROP_CL_PCIE_GEN1_GEN2_SWITCH_CHIPSET_DISABLED) // +#define NV_REG_STR_RM_D3_FEATURE "RMD3Feature" +// Type DWORD +// This regkey controls D3 related features +#define NV_REG_STR_RM_D3_FEATURE_DRIVER_CFG_SPACE_RESTORE 1:0 +#define NV_REG_STR_RM_D3_FEATURE_DRIVER_CFG_SPACE_RESTORE_DEFAULT (0x00000000) +#define NV_REG_STR_RM_D3_FEATURE_DRIVER_CFG_SPACE_RESTORE_ENABLED (0x00000001) +#define NV_REG_STR_RM_D3_FEATURE_DRIVER_CFG_SPACE_RESTORE_DISABLED (0x00000002) +#define NV_REG_STR_RM_D3_FEATURE_DRIVER_CFG_SPACE_RESTORE_UNUSED (0x00000003) + +#define NV_REG_STR_EMULATED_NBSI_TABLE "RMemNBSItable" +// The emulated NBSI table + #define NV_REG_STR_RM_DISABLE_FSP "RmDisableFsp" #define NV_REG_STR_RM_DISABLE_FSP_NO (0x00000000) #define NV_REG_STR_RM_DISABLE_FSP_YES (0x00000001) @@ -1602,4 +1624,104 @@ // Not present suggests default value. A value 0xFFFFFFFF will leave the value unmodified (ie bios value). // All other values must be multiples of 8 +#define NV_REG_STR_RM_ENABLE_ROUTE_TO_PHYSICAL_LOCK_BYPASS "RmRouteToPhyiscalLockBypass" +// Type Bool +// Enable optimisation to only take API READ (not WRITE) lock when forwarding ROUTE_TO_PHYSICAL +// control calls to GSP-enabled GPUs. +// This will heavily improve multi-gpu-multi-process control call latency and throughput. +// This optimisation will only work when *all* GPUs in the system are in offload mode (GSP mode). + +#define NV_REG_STR_RM_GPU_FABRIC_PROBE "RmGpuFabricProbe" +#define NV_REG_STR_RM_GPU_FABRIC_PROBE_DELAY 7:0 +#define NV_REG_STR_RM_GPU_FABRIC_PROBE_SLOWDOWN_THRESHOLD 15:8 +// Type DWORD +// Enable GPU fabric probe +// +// When this option is enabled, the GPU will probe its fabric state over the +// NVLink inband channel. The fabric state includes the attributes to allow +// the GPU to participate in P2P over the NVLink fabric. +// +// This option is only honored on NVSwitch based systems. +// +// Encoding: +// _DELAY : Delay between consecutive probe retries (in sec) +// before the slowdown starts. (Default: 5 sec) +// _SLOWDOWN_THRESHOLD : Number of probes retries before the slowdown starts +// (Default: 10). The slowdown doubles the delay +// between every consecutive probe retries until success. +// + +// Enable plugin logs in ftrace buffer. +// 0 - Default +// 0 - Disabled +// 1 - Enabled +#define NV_REG_STR_RM_ENABLE_PLUGIN_IN_FTRACE_BUFFER "RmEnablePluginFtrace" +#define NV_REG_STR_RM_ENABLE_PLUGIN_IN_FTRACE_BUFFER_ENABLED 0x00000001 +#define NV_REG_STR_RM_ENABLE_PLUGIN_IN_FTRACE_BUFFER_DISABLED 0x00000000 +#define NV_REG_STR_RM_ENABLE_PLUGIN_IN_FTRACE_BUFFER_DEFAULT 0x00000000 + +// TYPE Dword +// Enable vGPU migration on KVM hyperivsor. +// 1 - (Default) Enable vGPU migration on KVM +// 0 - Disable vGPU migration on KVM hypervisor +// +#define NV_REG_STR_RM_ENABLE_KVM_VGPU_MIGRATION "RmEnableKvmVgpuMigration" +#define NV_REG_STR_RM_ENABLE_KVM_VGPU_MIGRATION_TRUE 0x00000001 +#define NV_REG_STR_RM_ENABLE_KVM_VGPU_MIGRATION_FALSE 0x00000000 +#define NV_REG_STR_RM_ENABLE_KVM_VGPU_MIGRATION_DEFAULT 0x00000001 + +#define NV_REG_STR_RM_QSYNC_FW_REV_CHECK "QuadroSyncFirmwareRevisionCheckDisable" +#define NV_REG_STR_RM_QSYNC_FW_REV_CHECK_DEFAULT 0x00000000 +#define NV_REG_STR_RM_QSYNC_FW_REV_CHECK_ENABLE 0x00000000 +#define NV_REG_STR_RM_QSYNC_FW_REV_CHECK_DISABLE 0x00000001 + +// Type DWORD +// Disable Quadro Sync Firmware Revision Checking, for testing new versions. +// + +// +// Type: Dword +// Encoding: +// 1 - SRIOV Enabled on supported GPU +// 0 - SRIOV Disabled on specific GPU +// +#define NV_REG_STR_RM_SET_SRIOV_MODE "RMSetSriovMode" +#define NV_REG_STR_RM_SET_SRIOV_MODE_DISABLED 0x00000000 +#define NV_REG_STR_RM_SET_SRIOV_MODE_ENABLED 0x00000001 + +#define NV_REG_STR_RM_SET_VGPU_VERSION_MIN "RMSetVGPUVersionMin" +// +// TYPE DWORD +// Set the minimum vGPU version enforced to support + +#define NV_REG_STR_RM_SET_VGPU_VERSION_MAX "RMSetVGPUVersionMax" +// +// TYPE DWORD +// Set the maximum vGPU version enforced to support + +#define NV_REG_STR_TIME_SWAP_RDY_HI_MODIFY_LSR_MIN_TIME "TSwapRdyHiLsrMinTime" +#define NV_REG_STR_TIME_SWAP_RDY_HI_MODIFY_LSR_MIN_TIME_DEFAULT 250 // 250 micro seconds +// Type: DWORD +// Encoding: +// To modify LSR_MIN_TIME parameter according to the time +// period for which swap lock window will remain HIGH for QSYNC III +// i.e. P2060 during swap barrier. + +#define NV_REG_STR_TIME_SWAP_RDY_HI_MODIFY_SWAP_LOCKOUT_START "TSwapRdyHiSwapLockoutStart" +#define NV_REG_STR_TIME_SWAP_RDY_HI_MODIFY_SWAP_LOCKOUT_START_DEFAULT 250 // 250 micro seconds +// Type: DWORD +// Encoding: +// To modify SWAP_LOCKOUT_START parameter according to the time +// period for which swap lock window will remain HIGH for QSYNC III. +// + +#define NV_REG_STR_RM_MULTICAST_FLA "RMEnableMulticastFla" +#define NV_REG_STR_RM_MULTICAST_FLA_DISABLED 0x00000000 +#define NV_REG_STR_RM_MULTICAST_FLA_ENABLED 0x00000001 +// +// Type: Dword +// Encoding: +// 1 - Multicast FLA Enabled on supported GPU +// 0 - Multicast FLA Disabled on specific GPU +// #endif // NVRM_REGISTRY_H diff --git a/src/nvidia/interface/rmapi/src/finn_rm_api.c b/src/nvidia/interface/rmapi/src/finn_rm_api.c index c6b1e97fd..27510fe68 100644 --- a/src/nvidia/interface/rmapi/src/finn_rm_api.c +++ b/src/nvidia/interface/rmapi/src/finn_rm_api.c @@ -13,6 +13,7 @@ #include "ctrl/ctrl2080/ctrl2080nvd.h" #include "ctrl/ctrl2080/ctrl2080perf.h" #include "ctrl/ctrl2080/ctrl2080rc.h" +#include "ctrl/ctrl208f/ctrl208fgpu.h" #include "ctrl/ctrl402c.h" #include "ctrl/ctrl83de/ctrl83dedebug.h" #include "ctrl/ctrlb06f.h" @@ -412,6 +413,9 @@ static NvU64 FinnNv20Subdevice0PerfGetUnserializedSize(NvU64 message); static NV_STATUS FinnNv20Subdevice0RcSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); static NV_STATUS FinnNv20Subdevice0RcDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_RC *dst, NvLength dst_size, NvBool deser_up); static NvU64 FinnNv20Subdevice0RcGetUnserializedSize(NvU64 message); +static NV_STATUS FinnNv20SubdeviceDiagGpuSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); +static NV_STATUS FinnNv20SubdeviceDiagGpuDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_DIAG_GPU *dst, NvLength dst_size, NvBool deser_up); +static NvU64 FinnNv20SubdeviceDiagGpuGetUnserializedSize(NvU64 message); static NV_STATUS FinnNv40I2cI2cSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); static NV_STATUS FinnNv40I2cI2cDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV40_I2C_I2C *dst, NvLength dst_size, NvBool deser_up); static NvU64 FinnNv40I2cI2cGetUnserializedSize(NvU64 message); @@ -460,6 +464,7 @@ static NV_STATUS Nv2080CtrlNvdGetDumpParamsSerialize(const NV2080_CTRL_NVD_GET_D static NV_STATUS Nv2080CtrlNvdGetDumpParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_NVD_GET_DUMP_PARAMS *dst, NvLength dst_size, NvBool deser_up); static NV_STATUS Nv2080CtrlRcReadVirtualMemParamsSerialize(const NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); static NV_STATUS Nv2080CtrlRcReadVirtualMemParamsDeserialize(finn_bit_pump_for_read *bp, NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *dst, NvLength dst_size, NvBool deser_up); + static NV_STATUS Nv402cCtrlI2cIndexedParamsSerialize(const NV402C_CTRL_I2C_INDEXED_PARAMS *src, finn_bit_pump_for_write *bp, NvBool seri_up); static NV_STATUS Nv402cCtrlI2cIndexedParamsDeserialize(finn_bit_pump_for_read *bp, NV402C_CTRL_I2C_INDEXED_PARAMS *dst, NvLength dst_size, NvBool deser_up); static NV_STATUS Nv402cCtrlI2cTransactionTypeCheckEnum(NV402C_CTRL_I2C_TRANSACTION_TYPE id); @@ -618,6 +623,8 @@ static NV_STATUS FinnRmApiSerializeInterface(NvU64 interface, NvU64 message, con return FinnNv20Subdevice0PerfSerializeMessage(message, src, bp, seri_up); case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_RC): return FinnNv20Subdevice0RcSerializeMessage(message, src, bp, seri_up); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_DIAG_GPU): + return FinnNv20SubdeviceDiagGpuSerializeMessage(message, src, bp, seri_up); case FINN_INTERFACE_ID(FINN_NV40_I2C_I2C): return FinnNv40I2cI2cSerializeMessage(message, src, bp, seri_up); case FINN_INTERFACE_ID(FINN_GT200_DEBUGGER_DEBUG): @@ -745,6 +752,8 @@ static NV_STATUS FinnRmApiDeserializeInterface(NvU64 interface, NvU64 message, f return FinnNv20Subdevice0PerfDeserializeMessage(message, bp, (FINN_NV20_SUBDEVICE_0_PERF *) dst, dst_size, deser_up); case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_RC): return FinnNv20Subdevice0RcDeserializeMessage(message, bp, (FINN_NV20_SUBDEVICE_0_RC *) dst, dst_size, deser_up); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_DIAG_GPU): + return FinnNv20SubdeviceDiagGpuDeserializeMessage(message, bp, (FINN_NV20_SUBDEVICE_DIAG_GPU *) dst, dst_size, deser_up); case FINN_INTERFACE_ID(FINN_NV40_I2C_I2C): return FinnNv40I2cI2cDeserializeMessage(message, bp, (FINN_NV40_I2C_I2C *) dst, dst_size, deser_up); case FINN_INTERFACE_ID(FINN_GT200_DEBUGGER_DEBUG): @@ -815,6 +824,8 @@ NvU64 FinnRmApiGetUnserializedSize(NvU64 interface, NvU64 message) return FinnNv20Subdevice0PerfGetUnserializedSize(message); case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_0_RC): return FinnNv20Subdevice0RcGetUnserializedSize(message); + case FINN_INTERFACE_ID(FINN_NV20_SUBDEVICE_DIAG_GPU): + return FinnNv20SubdeviceDiagGpuGetUnserializedSize(message); case FINN_INTERFACE_ID(FINN_NV40_I2C_I2C): return FinnNv40I2cI2cGetUnserializedSize(message); case FINN_INTERFACE_ID(FINN_GT200_DEBUGGER_DEBUG): @@ -1488,6 +1499,46 @@ static NvU64 FinnNv20Subdevice0RcGetUnserializedSize(NvU64 message) } } +static NV_STATUS FinnNv20SubdeviceDiagGpuSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) +{ + // Forward to message-specific routine. + switch (message) + { + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + +static NV_STATUS FinnNv20SubdeviceDiagGpuDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_DIAG_GPU *dst, NvLength dst_size, NvBool deser_up) +{ + // Forward to message-specific routine. + switch (message) + { + + // Everything else is unsupported. + default: + { + FINN_ERROR(NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + } +} + +static NvU64 FinnNv20SubdeviceDiagGpuGetUnserializedSize(NvU64 message) +{ + // Forward to message-specific routine. + switch (message) + { + default: + return 0; + } +} + static NV_STATUS FinnNv40I2cI2cSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up) { // Forward to message-specific routine. @@ -1664,7 +1715,14 @@ static NV_STATUS Nv0000CtrlNvdGetDumpParamsSerialize(const NV0000_CTRL_NVD_GET_D // Field bitmasks field_presence_mask = 0x7; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields // No range check for src->component @@ -1677,7 +1735,7 @@ static NV_STATUS Nv0000CtrlNvdGetDumpParamsSerialize(const NV0000_CTRL_NVD_GET_D } - if (src->size < 0 || src->size > NV0000_CTRL_NVD_MAX_DUMP_SIZE) + if (src->size > NV0000_CTRL_NVD_MAX_DUMP_SIZE) { status = NV_ERR_OUT_OF_RANGE; FINN_ERROR(NV_ERR_OUT_OF_RANGE); @@ -1695,7 +1753,12 @@ static NV_STATUS Nv0000CtrlNvdGetDumpParamsSerialize(const NV0000_CTRL_NVD_GET_D // Unbounded fields // Set data-presence indicator. - finn_write_buffer(bp, !!(src->pBuffer), 1); + if (finn_write_buffer(bp, !!(src->pBuffer), 1)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Skip if pointer is null. if (src->pBuffer) @@ -1704,7 +1767,12 @@ static NV_STATUS Nv0000CtrlNvdGetDumpParamsSerialize(const NV0000_CTRL_NVD_GET_D // Serialize each 1-byte NvU8 element. for (NvU64 j = 0; j < (src->size); ++j) { - finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pBuffer))[j], 1 * 8); + if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pBuffer))[j], 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } } // Free memory that was allocated during downward deserialization. @@ -1747,7 +1815,7 @@ static NV_STATUS Nv0000CtrlNvdGetDumpParamsDeserialize(finn_bit_pump_for_read *b // Deserialize 4-byte NvU32 object. dst->size = (NvU32) finn_read_buffer(bp, 4 * 8); - if (dst->size < 0 || dst->size > NV0000_CTRL_NVD_MAX_DUMP_SIZE) + if (dst->size > NV0000_CTRL_NVD_MAX_DUMP_SIZE) { status = NV_ERR_OUT_OF_RANGE; FINN_ERROR(NV_ERR_OUT_OF_RANGE); @@ -1809,7 +1877,14 @@ static NV_STATUS Nv0080CtrlDmaUpdatePde2PageTableParamsSerialize(const NV0080_CT // Field bitmasks field_presence_mask = 0x7; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields // No range check for src->physAddr @@ -1898,7 +1973,14 @@ static NV_STATUS Nv0080CtrlDmaUpdatePde2ParamsSerialize(const NV0080_CTRL_DMA_UP // Field bitmasks field_presence_mask = 0x3f; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields // No range check for src->pdeIndex @@ -1951,7 +2033,12 @@ static NV_STATUS Nv0080CtrlDmaUpdatePde2ParamsSerialize(const NV0080_CTRL_DMA_UP // Unbounded fields // Set data-presence indicator. - finn_write_buffer(bp, !!(src->pPdeBuffer), 1); + if (finn_write_buffer(bp, !!(src->pPdeBuffer), 1)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Skip if pointer is null. if (src->pPdeBuffer) @@ -1960,7 +2047,12 @@ static NV_STATUS Nv0080CtrlDmaUpdatePde2ParamsSerialize(const NV0080_CTRL_DMA_UP // Serialize each 8-byte NvU64 element. for (NvU64 j = 0; j < 1; ++j) { - finn_write_buffer(bp, ((NvU64 *) NvP64_VALUE(src->pPdeBuffer))[j], 8 * 8); + if (finn_write_buffer(bp, ((NvU64 *) NvP64_VALUE(src->pPdeBuffer))[j], 8 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } } // Free memory that was allocated during downward deserialization. @@ -2077,10 +2169,17 @@ static NV_STATUS Nv0080CtrlFbGetCapsParamsSerialize(const NV0080_CTRL_FB_GET_CAP // Field bitmasks field_presence_mask = 0x3; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields - if (src->capsTblSize < 0 || src->capsTblSize > NV0080_CTRL_FB_CAPS_TBL_SIZE) + if (src->capsTblSize > NV0080_CTRL_FB_CAPS_TBL_SIZE) { status = NV_ERR_OUT_OF_RANGE; FINN_ERROR(NV_ERR_OUT_OF_RANGE); @@ -2098,7 +2197,12 @@ static NV_STATUS Nv0080CtrlFbGetCapsParamsSerialize(const NV0080_CTRL_FB_GET_CAP // Unbounded fields // Set data-presence indicator. - finn_write_buffer(bp, !!(src->capsTbl), 1); + if (finn_write_buffer(bp, !!(src->capsTbl), 1)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Skip if pointer is null. if (src->capsTbl) @@ -2107,7 +2211,12 @@ static NV_STATUS Nv0080CtrlFbGetCapsParamsSerialize(const NV0080_CTRL_FB_GET_CAP // Serialize each 1-byte NvU8 element. for (NvU64 j = 0; j < (src->capsTblSize); ++j) { - finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->capsTbl))[j], 1 * 8); + if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->capsTbl))[j], 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } } // Free memory that was allocated during downward deserialization. @@ -2145,7 +2254,7 @@ static NV_STATUS Nv0080CtrlFbGetCapsParamsDeserialize(finn_bit_pump_for_read *bp // Statically sized fields // Deserialize 4-byte NvU32 object. dst->capsTblSize = (NvU32) finn_read_buffer(bp, 4 * 8); - if (dst->capsTblSize < 0 || dst->capsTblSize > NV0080_CTRL_FB_CAPS_TBL_SIZE) + if (dst->capsTblSize > NV0080_CTRL_FB_CAPS_TBL_SIZE) { status = NV_ERR_OUT_OF_RANGE; FINN_ERROR(NV_ERR_OUT_OF_RANGE); @@ -2207,10 +2316,17 @@ static NV_STATUS Nv0080CtrlFifoGetCapsParamsSerialize(const NV0080_CTRL_FIFO_GET // Field bitmasks field_presence_mask = 0x3; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields - if (src->capsTblSize < 0 || src->capsTblSize > NV0080_CTRL_FIFO_CAPS_TBL_SIZE) + if (src->capsTblSize > NV0080_CTRL_FIFO_CAPS_TBL_SIZE) { status = NV_ERR_OUT_OF_RANGE; FINN_ERROR(NV_ERR_OUT_OF_RANGE); @@ -2228,7 +2344,12 @@ static NV_STATUS Nv0080CtrlFifoGetCapsParamsSerialize(const NV0080_CTRL_FIFO_GET // Unbounded fields // Set data-presence indicator. - finn_write_buffer(bp, !!(src->capsTbl), 1); + if (finn_write_buffer(bp, !!(src->capsTbl), 1)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Skip if pointer is null. if (src->capsTbl) @@ -2237,7 +2358,12 @@ static NV_STATUS Nv0080CtrlFifoGetCapsParamsSerialize(const NV0080_CTRL_FIFO_GET // Serialize each 1-byte NvU8 element. for (NvU64 j = 0; j < (src->capsTblSize); ++j) { - finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->capsTbl))[j], 1 * 8); + if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->capsTbl))[j], 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } } // Free memory that was allocated during downward deserialization. @@ -2275,7 +2401,7 @@ static NV_STATUS Nv0080CtrlFifoGetCapsParamsDeserialize(finn_bit_pump_for_read * // Statically sized fields // Deserialize 4-byte NvU32 object. dst->capsTblSize = (NvU32) finn_read_buffer(bp, 4 * 8); - if (dst->capsTblSize < 0 || dst->capsTblSize > NV0080_CTRL_FIFO_CAPS_TBL_SIZE) + if (dst->capsTblSize > NV0080_CTRL_FIFO_CAPS_TBL_SIZE) { status = NV_ERR_OUT_OF_RANGE; FINN_ERROR(NV_ERR_OUT_OF_RANGE); @@ -2337,7 +2463,14 @@ static NV_STATUS Nv0080CtrlFifoChannelSerialize(const NV0080_CTRL_FIFO_CHANNEL * // Field bitmasks field_presence_mask = 0x1; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields // No range check for src->hChannel @@ -2396,12 +2529,19 @@ static NV_STATUS Nv0080CtrlFifoStartSelectedChannelsParamsSerialize(const NV0080 // Field bitmasks field_presence_mask = 0x7; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields - // No range check for src->fifoStartChannelListSize + // No range check for src->fifoStartChannelListCount // Deserialize 4-byte NvU32 object. - if (finn_write_buffer(bp, src->fifoStartChannelListSize, 4 * 8)) + if (finn_write_buffer(bp, src->fifoStartChannelListCount, 4 * 8)) { status = NV_ERR_BUFFER_TOO_SMALL; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); @@ -2424,12 +2564,17 @@ static NV_STATUS Nv0080CtrlFifoStartSelectedChannelsParamsSerialize(const NV0080 // Unbounded fields // Set data-presence indicator. - finn_write_buffer(bp, !!(src->fifoStartChannelList), 1); + if (finn_write_buffer(bp, !!(src->fifoStartChannelList), 1)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Skip if pointer is null. if (src->fifoStartChannelList) { - for (NvU64 i = 0; i < (src->fifoStartChannelListSize); ++i) + for (NvU64 i = 0; i < (src->fifoStartChannelListCount); ++i) { status = Nv0080CtrlFifoChannelSerialize(&(((const NV0080_CTRL_FIFO_CHANNEL *) (NvP64_VALUE(src->fifoStartChannelList)))[i]), bp, seri_up); @@ -2472,8 +2617,8 @@ static NV_STATUS Nv0080CtrlFifoStartSelectedChannelsParamsDeserialize(finn_bit_p // Statically sized fields // Deserialize 4-byte NvU32 object. - dst->fifoStartChannelListSize = (NvU32) finn_read_buffer(bp, 4 * 8); - // No range check for dst->fifoStartChannelListSize + dst->fifoStartChannelListCount = (NvU32) finn_read_buffer(bp, 4 * 8); + // No range check for dst->fifoStartChannelListCount for (NvU64 i = 0; i < (8); ++i) @@ -2493,8 +2638,8 @@ static NV_STATUS Nv0080CtrlFifoStartSelectedChannelsParamsDeserialize(finn_bit_p { // Data-presence indicator should be false if empty. // Check for integer overflow in the element size variable. - if ((dst->fifoStartChannelListSize) < 1 || - (sizeof(NV0080_CTRL_FIFO_CHANNEL) * (dst->fifoStartChannelListSize)) < sizeof(NV0080_CTRL_FIFO_CHANNEL)) + if ((dst->fifoStartChannelListCount) < 1 || + (sizeof(NV0080_CTRL_FIFO_CHANNEL) * (dst->fifoStartChannelListCount)) < sizeof(NV0080_CTRL_FIFO_CHANNEL)) { status = NV_ERR_BUFFER_TOO_SMALL; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); @@ -2503,7 +2648,7 @@ static NV_STATUS Nv0080CtrlFifoStartSelectedChannelsParamsDeserialize(finn_bit_p // Allocate memory and set pointer when deserializing down. // (Calling cods is expected to do so when deserializing up.) - dst->fifoStartChannelList = FINN_MALLOC((sizeof(NV0080_CTRL_FIFO_CHANNEL) * (dst->fifoStartChannelListSize))); + dst->fifoStartChannelList = FINN_MALLOC((sizeof(NV0080_CTRL_FIFO_CHANNEL) * (dst->fifoStartChannelListCount))); if (!dst->fifoStartChannelList) { status = NV_ERR_NO_MEMORY; @@ -2511,7 +2656,7 @@ static NV_STATUS Nv0080CtrlFifoStartSelectedChannelsParamsDeserialize(finn_bit_p goto exit; } - FINN_MEMZERO(dst->fifoStartChannelList, (sizeof(NV0080_CTRL_FIFO_CHANNEL) * (dst->fifoStartChannelListSize))); + FINN_MEMZERO(dst->fifoStartChannelList, (sizeof(NV0080_CTRL_FIFO_CHANNEL) * (dst->fifoStartChannelListCount))); } // Otherwise the pointer must be provided. @@ -2522,7 +2667,7 @@ static NV_STATUS Nv0080CtrlFifoStartSelectedChannelsParamsDeserialize(finn_bit_p goto exit; } - for (NvU64 i = 0; i < (dst->fifoStartChannelListSize); ++i) + for (NvU64 i = 0; i < (dst->fifoStartChannelListCount); ++i) { // Deserialize each element. status = Nv0080CtrlFifoChannelDeserialize(bp, &(((NV0080_CTRL_FIFO_CHANNEL *) (NvP64_VALUE(dst->fifoStartChannelList)))[i]), sizeof(NV0080_CTRL_FIFO_CHANNEL), deser_up); @@ -2552,7 +2697,14 @@ static NV_STATUS Nv0080CtrlFifoGetChannellistParamsSerialize(const NV0080_CTRL_F // Field bitmasks field_presence_mask = 0x7; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields // No range check for src->numChannels @@ -2567,7 +2719,12 @@ static NV_STATUS Nv0080CtrlFifoGetChannellistParamsSerialize(const NV0080_CTRL_F // Unbounded fields // Set data-presence indicator. - finn_write_buffer(bp, !!(src->pChannelHandleList), 1); + if (finn_write_buffer(bp, !!(src->pChannelHandleList), 1)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Skip if pointer is null. if (src->pChannelHandleList) @@ -2576,7 +2733,12 @@ static NV_STATUS Nv0080CtrlFifoGetChannellistParamsSerialize(const NV0080_CTRL_F // Serialize each 4-byte NvU32 element. for (NvU64 j = 0; j < (src->numChannels); ++j) { - finn_write_buffer(bp, ((NvU32 *) NvP64_VALUE(src->pChannelHandleList))[j], 4 * 8); + if (finn_write_buffer(bp, ((NvU32 *) NvP64_VALUE(src->pChannelHandleList))[j], 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } } // Free memory that was allocated during downward deserialization. @@ -2585,7 +2747,12 @@ static NV_STATUS Nv0080CtrlFifoGetChannellistParamsSerialize(const NV0080_CTRL_F } // Set data-presence indicator. - finn_write_buffer(bp, !!(src->pChannelList), 1); + if (finn_write_buffer(bp, !!(src->pChannelList), 1)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Skip if pointer is null. if (src->pChannelList) @@ -2594,7 +2761,12 @@ static NV_STATUS Nv0080CtrlFifoGetChannellistParamsSerialize(const NV0080_CTRL_F // Serialize each 4-byte NvU32 element. for (NvU64 j = 0; j < (src->numChannels); ++j) { - finn_write_buffer(bp, ((NvU32 *) NvP64_VALUE(src->pChannelList))[j], 4 * 8); + if (finn_write_buffer(bp, ((NvU32 *) NvP64_VALUE(src->pChannelList))[j], 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } } // Free memory that was allocated during downward deserialization. @@ -2727,7 +2899,14 @@ static NV_STATUS Nv0080CtrlGpuGetClasslistParamsSerialize(const NV0080_CTRL_GPU_ // Field bitmasks field_presence_mask = 0x3; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields // No range check for src->numClasses @@ -2742,7 +2921,12 @@ static NV_STATUS Nv0080CtrlGpuGetClasslistParamsSerialize(const NV0080_CTRL_GPU_ // Unbounded fields // Set data-presence indicator. - finn_write_buffer(bp, !!(src->classList), 1); + if (finn_write_buffer(bp, !!(src->classList), 1)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Skip if pointer is null. if (src->classList) @@ -2751,7 +2935,12 @@ static NV_STATUS Nv0080CtrlGpuGetClasslistParamsSerialize(const NV0080_CTRL_GPU_ // Serialize each 4-byte NvU32 element. for (NvU64 j = 0; j < (src->numClasses); ++j) { - finn_write_buffer(bp, ((NvU32 *) NvP64_VALUE(src->classList))[j], 4 * 8); + if (finn_write_buffer(bp, ((NvU32 *) NvP64_VALUE(src->classList))[j], 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } } // Free memory that was allocated during downward deserialization. @@ -2845,7 +3034,14 @@ static NV_STATUS Nv0080CtrlGrGetCapsParamsSerialize(const NV0080_CTRL_GR_GET_CAP // Field bitmasks field_presence_mask = 0x3; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields // No range check for src->capsTblSize @@ -2860,7 +3056,12 @@ static NV_STATUS Nv0080CtrlGrGetCapsParamsSerialize(const NV0080_CTRL_GR_GET_CAP // Unbounded fields // Set data-presence indicator. - finn_write_buffer(bp, !!(src->capsTbl), 1); + if (finn_write_buffer(bp, !!(src->capsTbl), 1)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Skip if pointer is null. if (src->capsTbl) @@ -2869,7 +3070,12 @@ static NV_STATUS Nv0080CtrlGrGetCapsParamsSerialize(const NV0080_CTRL_GR_GET_CAP // Serialize each 1-byte NvU8 element. for (NvU64 j = 0; j < (src->capsTblSize); ++j) { - finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->capsTbl))[j], 1 * 8); + if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->capsTbl))[j], 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } } // Free memory that was allocated during downward deserialization. @@ -2963,10 +3169,17 @@ static NV_STATUS Nv0080CtrlHostGetCapsParamsSerialize(const NV0080_CTRL_HOST_GET // Field bitmasks field_presence_mask = 0x3; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields - if (src->capsTblSize < 0 || src->capsTblSize > NV0080_CTRL_HOST_CAPS_TBL_SIZE) + if (src->capsTblSize > NV0080_CTRL_HOST_CAPS_TBL_SIZE) { status = NV_ERR_OUT_OF_RANGE; FINN_ERROR(NV_ERR_OUT_OF_RANGE); @@ -2984,7 +3197,12 @@ static NV_STATUS Nv0080CtrlHostGetCapsParamsSerialize(const NV0080_CTRL_HOST_GET // Unbounded fields // Set data-presence indicator. - finn_write_buffer(bp, !!(src->capsTbl), 1); + if (finn_write_buffer(bp, !!(src->capsTbl), 1)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Skip if pointer is null. if (src->capsTbl) @@ -2993,7 +3211,12 @@ static NV_STATUS Nv0080CtrlHostGetCapsParamsSerialize(const NV0080_CTRL_HOST_GET // Serialize each 1-byte NvU8 element. for (NvU64 j = 0; j < (src->capsTblSize); ++j) { - finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->capsTbl))[j], 1 * 8); + if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->capsTbl))[j], 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } } // Free memory that was allocated during downward deserialization. @@ -3031,7 +3254,7 @@ static NV_STATUS Nv0080CtrlHostGetCapsParamsDeserialize(finn_bit_pump_for_read * // Statically sized fields // Deserialize 4-byte NvU32 object. dst->capsTblSize = (NvU32) finn_read_buffer(bp, 4 * 8); - if (dst->capsTblSize < 0 || dst->capsTblSize > NV0080_CTRL_HOST_CAPS_TBL_SIZE) + if (dst->capsTblSize > NV0080_CTRL_HOST_CAPS_TBL_SIZE) { status = NV_ERR_OUT_OF_RANGE; FINN_ERROR(NV_ERR_OUT_OF_RANGE); @@ -3093,10 +3316,17 @@ static NV_STATUS Nv0080CtrlMsencGetCapsParamsSerialize(const NV0080_CTRL_MSENC_G // Field bitmasks field_presence_mask = 0x3; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields - if (src->capsTblSize < 0 || src->capsTblSize > NV0080_CTRL_MSENC_CAPS_TBL_SIZE) + if (src->capsTblSize > NV0080_CTRL_MSENC_CAPS_TBL_SIZE) { status = NV_ERR_OUT_OF_RANGE; FINN_ERROR(NV_ERR_OUT_OF_RANGE); @@ -3114,7 +3344,12 @@ static NV_STATUS Nv0080CtrlMsencGetCapsParamsSerialize(const NV0080_CTRL_MSENC_G // Unbounded fields // Set data-presence indicator. - finn_write_buffer(bp, !!(src->capsTbl), 1); + if (finn_write_buffer(bp, !!(src->capsTbl), 1)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Skip if pointer is null. if (src->capsTbl) @@ -3123,7 +3358,12 @@ static NV_STATUS Nv0080CtrlMsencGetCapsParamsSerialize(const NV0080_CTRL_MSENC_G // Serialize each 1-byte NvU8 element. for (NvU64 j = 0; j < (src->capsTblSize); ++j) { - finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->capsTbl))[j], 1 * 8); + if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->capsTbl))[j], 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } } // Free memory that was allocated during downward deserialization. @@ -3161,7 +3401,7 @@ static NV_STATUS Nv0080CtrlMsencGetCapsParamsDeserialize(finn_bit_pump_for_read // Statically sized fields // Deserialize 4-byte NvU32 object. dst->capsTblSize = (NvU32) finn_read_buffer(bp, 4 * 8); - if (dst->capsTblSize < 0 || dst->capsTblSize > NV0080_CTRL_MSENC_CAPS_TBL_SIZE) + if (dst->capsTblSize > NV0080_CTRL_MSENC_CAPS_TBL_SIZE) { status = NV_ERR_OUT_OF_RANGE; FINN_ERROR(NV_ERR_OUT_OF_RANGE); @@ -3223,7 +3463,14 @@ static NV_STATUS Nv2080CtrlCeGetCapsParamsSerialize(const NV2080_CTRL_CE_GET_CAP // Field bitmasks field_presence_mask = 0x7; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields // No range check for src->ceEngineType @@ -3236,7 +3483,7 @@ static NV_STATUS Nv2080CtrlCeGetCapsParamsSerialize(const NV2080_CTRL_CE_GET_CAP } - if (src->capsTblSize < 0 || src->capsTblSize > NV2080_CTRL_CE_CAPS_TBL_SIZE) + if (src->capsTblSize > NV2080_CTRL_CE_CAPS_TBL_SIZE) { status = NV_ERR_OUT_OF_RANGE; FINN_ERROR(NV_ERR_OUT_OF_RANGE); @@ -3254,7 +3501,12 @@ static NV_STATUS Nv2080CtrlCeGetCapsParamsSerialize(const NV2080_CTRL_CE_GET_CAP // Unbounded fields // Set data-presence indicator. - finn_write_buffer(bp, !!(src->capsTbl), 1); + if (finn_write_buffer(bp, !!(src->capsTbl), 1)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Skip if pointer is null. if (src->capsTbl) @@ -3263,7 +3515,12 @@ static NV_STATUS Nv2080CtrlCeGetCapsParamsSerialize(const NV2080_CTRL_CE_GET_CAP // Serialize each 1-byte NvU8 element. for (NvU64 j = 0; j < (src->capsTblSize); ++j) { - finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->capsTbl))[j], 1 * 8); + if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->capsTbl))[j], 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } } // Free memory that was allocated during downward deserialization. @@ -3306,7 +3563,7 @@ static NV_STATUS Nv2080CtrlCeGetCapsParamsDeserialize(finn_bit_pump_for_read *bp // Deserialize 4-byte NvU32 object. dst->capsTblSize = (NvU32) finn_read_buffer(bp, 4 * 8); - if (dst->capsTblSize < 0 || dst->capsTblSize > NV2080_CTRL_CE_CAPS_TBL_SIZE) + if (dst->capsTblSize > NV2080_CTRL_CE_CAPS_TBL_SIZE) { status = NV_ERR_OUT_OF_RANGE; FINN_ERROR(NV_ERR_OUT_OF_RANGE); @@ -3368,7 +3625,14 @@ static NV_STATUS Nv2080CtrlGpuGetEnginesParamsSerialize(const NV2080_CTRL_GPU_GE // Field bitmasks field_presence_mask = 0x3; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields // No range check for src->engineCount @@ -3383,7 +3647,12 @@ static NV_STATUS Nv2080CtrlGpuGetEnginesParamsSerialize(const NV2080_CTRL_GPU_GE // Unbounded fields // Set data-presence indicator. - finn_write_buffer(bp, !!(src->engineList), 1); + if (finn_write_buffer(bp, !!(src->engineList), 1)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Skip if pointer is null. if (src->engineList) @@ -3392,7 +3661,12 @@ static NV_STATUS Nv2080CtrlGpuGetEnginesParamsSerialize(const NV2080_CTRL_GPU_GE // Serialize each 4-byte NvU32 element. for (NvU64 j = 0; j < (src->engineCount); ++j) { - finn_write_buffer(bp, ((NvU32 *) NvP64_VALUE(src->engineList))[j], 4 * 8); + if (finn_write_buffer(bp, ((NvU32 *) NvP64_VALUE(src->engineList))[j], 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } } // Free memory that was allocated during downward deserialization. @@ -3486,7 +3760,14 @@ static NV_STATUS Nv2080CtrlGpuGetEngineClasslistParamsSerialize(const NV2080_CTR // Field bitmasks field_presence_mask = 0x7; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields // No range check for src->engineType @@ -3511,7 +3792,12 @@ static NV_STATUS Nv2080CtrlGpuGetEngineClasslistParamsSerialize(const NV2080_CTR // Unbounded fields // Set data-presence indicator. - finn_write_buffer(bp, !!(src->classList), 1); + if (finn_write_buffer(bp, !!(src->classList), 1)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Skip if pointer is null. if (src->classList) @@ -3520,7 +3806,12 @@ static NV_STATUS Nv2080CtrlGpuGetEngineClasslistParamsSerialize(const NV2080_CTR // Serialize each 4-byte NvU32 element. for (NvU64 j = 0; j < (src->numClasses); ++j) { - finn_write_buffer(bp, ((NvU32 *) NvP64_VALUE(src->classList))[j], 4 * 8); + if (finn_write_buffer(bp, ((NvU32 *) NvP64_VALUE(src->classList))[j], 4 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } } // Free memory that was allocated during downward deserialization. @@ -3619,7 +3910,14 @@ static NV_STATUS Nv2080CtrlGpumonSamplesSerialize(const NV2080_CTRL_GPUMON_SAMPL // Field bitmasks field_presence_mask = 0x1f; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields // No range check for src->bufSize @@ -3664,7 +3962,12 @@ static NV_STATUS Nv2080CtrlGpumonSamplesSerialize(const NV2080_CTRL_GPUMON_SAMPL // Unbounded fields // Set data-presence indicator. - finn_write_buffer(bp, !!(src->pSamples), 1); + if (finn_write_buffer(bp, !!(src->pSamples), 1)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Skip if pointer is null. if (src->pSamples) @@ -3673,7 +3976,12 @@ static NV_STATUS Nv2080CtrlGpumonSamplesSerialize(const NV2080_CTRL_GPUMON_SAMPL // Serialize each 1-byte NvU8 element. for (NvU64 j = 0; j < (src->bufSize); ++j) { - finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pSamples))[j], 1 * 8); + if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pSamples))[j], 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } } // Free memory that was allocated during downward deserialization. @@ -3782,7 +4090,14 @@ static NV_STATUS Nv2080CtrlI2cAccessParamsSerialize(const NV2080_CTRL_I2C_ACCESS // Field bitmasks field_presence_mask = 0x1ff; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields // No range check for src->token @@ -3835,7 +4150,7 @@ static NV_STATUS Nv2080CtrlI2cAccessParamsSerialize(const NV2080_CTRL_I2C_ACCESS } - if (src->dataBuffSize < 0 || src->dataBuffSize > NV2080_CTRL_I2C_MAX_ENTRIES) + if (src->dataBuffSize > NV2080_CTRL_I2C_MAX_ENTRIES) { status = NV_ERR_OUT_OF_RANGE; FINN_ERROR(NV_ERR_OUT_OF_RANGE); @@ -3873,7 +4188,12 @@ static NV_STATUS Nv2080CtrlI2cAccessParamsSerialize(const NV2080_CTRL_I2C_ACCESS // Unbounded fields // Set data-presence indicator. - finn_write_buffer(bp, !!(src->data), 1); + if (finn_write_buffer(bp, !!(src->data), 1)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Skip if pointer is null. if (src->data) @@ -3882,7 +4202,12 @@ static NV_STATUS Nv2080CtrlI2cAccessParamsSerialize(const NV2080_CTRL_I2C_ACCESS // Serialize each 1-byte NvU8 element. for (NvU64 j = 0; j < (src->dataBuffSize); ++j) { - finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->data))[j], 1 * 8); + if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->data))[j], 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } } // Free memory that was allocated during downward deserialization. @@ -3945,7 +4270,7 @@ static NV_STATUS Nv2080CtrlI2cAccessParamsDeserialize(finn_bit_pump_for_read *bp // Deserialize 4-byte NvU32 object. dst->dataBuffSize = (NvU32) finn_read_buffer(bp, 4 * 8); - if (dst->dataBuffSize < 0 || dst->dataBuffSize > NV2080_CTRL_I2C_MAX_ENTRIES) + if (dst->dataBuffSize > NV2080_CTRL_I2C_MAX_ENTRIES) { status = NV_ERR_OUT_OF_RANGE; FINN_ERROR(NV_ERR_OUT_OF_RANGE); @@ -4017,7 +4342,14 @@ static NV_STATUS Nv2080CtrlNvdGetDumpParamsSerialize(const NV2080_CTRL_NVD_GET_D // Field bitmasks field_presence_mask = 0x7; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields // No range check for src->component @@ -4042,7 +4374,12 @@ static NV_STATUS Nv2080CtrlNvdGetDumpParamsSerialize(const NV2080_CTRL_NVD_GET_D // Unbounded fields // Set data-presence indicator. - finn_write_buffer(bp, !!(src->pBuffer), 1); + if (finn_write_buffer(bp, !!(src->pBuffer), 1)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Skip if pointer is null. if (src->pBuffer) @@ -4051,7 +4388,12 @@ static NV_STATUS Nv2080CtrlNvdGetDumpParamsSerialize(const NV2080_CTRL_NVD_GET_D // Serialize each 1-byte NvU8 element. for (NvU64 j = 0; j < (src->size); ++j) { - finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pBuffer))[j], 1 * 8); + if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pBuffer))[j], 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } } // Free memory that was allocated during downward deserialization. @@ -4150,7 +4492,14 @@ static NV_STATUS Nv2080CtrlRcReadVirtualMemParamsSerialize(const NV2080_CTRL_RC_ // Field bitmasks field_presence_mask = 0xf; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields // No range check for src->virtAddress @@ -4185,7 +4534,12 @@ static NV_STATUS Nv2080CtrlRcReadVirtualMemParamsSerialize(const NV2080_CTRL_RC_ // Unbounded fields // Set data-presence indicator. - finn_write_buffer(bp, !!(src->bufferPtr), 1); + if (finn_write_buffer(bp, !!(src->bufferPtr), 1)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Skip if pointer is null. if (src->bufferPtr) @@ -4194,7 +4548,12 @@ static NV_STATUS Nv2080CtrlRcReadVirtualMemParamsSerialize(const NV2080_CTRL_RC_ // Serialize each 1-byte NvU8 element. for (NvU64 j = 0; j < (src->bufferSize); ++j) { - finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->bufferPtr))[j], 1 * 8); + if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->bufferPtr))[j], 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } } // Free memory that was allocated during downward deserialization. @@ -4298,7 +4657,14 @@ static NV_STATUS Nv402cCtrlI2cIndexedParamsSerialize(const NV402C_CTRL_I2C_INDEX // Field bitmasks field_presence_mask = 0xff; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields // No range check for src->flags @@ -4311,7 +4677,7 @@ static NV_STATUS Nv402cCtrlI2cIndexedParamsSerialize(const NV402C_CTRL_I2C_INDEX } - if (src->indexLength < 0 || src->indexLength > NV402C_CTRL_I2C_INDEX_LENGTH_MAX) + if (src->indexLength > NV402C_CTRL_I2C_INDEX_LENGTH_MAX) { status = NV_ERR_OUT_OF_RANGE; FINN_ERROR(NV_ERR_OUT_OF_RANGE); @@ -4382,7 +4748,12 @@ static NV_STATUS Nv402cCtrlI2cIndexedParamsSerialize(const NV402C_CTRL_I2C_INDEX // Unbounded fields // Set data-presence indicator. - finn_write_buffer(bp, !!(src->pMessage), 1); + if (finn_write_buffer(bp, !!(src->pMessage), 1)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Skip if pointer is null. if (src->pMessage) @@ -4391,7 +4762,12 @@ static NV_STATUS Nv402cCtrlI2cIndexedParamsSerialize(const NV402C_CTRL_I2C_INDEX // Serialize each 1-byte NvU8 element. for (NvU64 j = 0; j < (src->messageLength); ++j) { - finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pMessage))[j], 1 * 8); + if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pMessage))[j], 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } } // Free memory that was allocated during downward deserialization. @@ -4434,7 +4810,7 @@ static NV_STATUS Nv402cCtrlI2cIndexedParamsDeserialize(finn_bit_pump_for_read *b // Deserialize 4-byte NvU32 object. dst->indexLength = (NvU32) finn_read_buffer(bp, 4 * 8); - if (dst->indexLength < 0 || dst->indexLength > NV402C_CTRL_I2C_INDEX_LENGTH_MAX) + if (dst->indexLength > NV402C_CTRL_I2C_INDEX_LENGTH_MAX) { status = NV_ERR_OUT_OF_RANGE; FINN_ERROR(NV_ERR_OUT_OF_RANGE); @@ -4545,7 +4921,14 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusQuickRwSerialize(const NV402C_ // Field bitmasks field_presence_mask = 0x3; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields // No range check for src->warFlags @@ -4619,7 +5002,14 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataI2cByteRwSerialize(const NV402C_CTR // Field bitmasks field_presence_mask = 0x3; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields // No range check for src->bWrite @@ -4693,7 +5083,14 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBlockRwSerialize(const NV402C_CT // Field bitmasks field_presence_mask = 0x7; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields // No range check for src->messageLength @@ -4718,7 +5115,12 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBlockRwSerialize(const NV402C_CT // Unbounded fields // Set data-presence indicator. - finn_write_buffer(bp, !!(src->pMessage), 1); + if (finn_write_buffer(bp, !!(src->pMessage), 1)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Skip if pointer is null. if (src->pMessage) @@ -4727,7 +5129,12 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBlockRwSerialize(const NV402C_CT // Serialize each 1-byte NvU8 element. for (NvU64 j = 0; j < (src->messageLength); ++j) { - finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pMessage))[j], 1 * 8); + if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pMessage))[j], 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } } // Free memory that was allocated during downward deserialization. @@ -4826,7 +5233,14 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusByteRwSerialize(const NV402C_C // Field bitmasks field_presence_mask = 0x7; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields // No range check for src->bWrite @@ -4915,7 +5329,14 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusWordRwSerialize(const NV402C_C // Field bitmasks field_presence_mask = 0x7; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields // No range check for src->message @@ -5004,7 +5425,14 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBufferRwSerialize(const NV402C_C // Field bitmasks field_presence_mask = 0x1f; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields // No range check for src->warFlags @@ -5049,7 +5477,12 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBufferRwSerialize(const NV402C_C // Unbounded fields // Set data-presence indicator. - finn_write_buffer(bp, !!(src->pMessage), 1); + if (finn_write_buffer(bp, !!(src->pMessage), 1)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Skip if pointer is null. if (src->pMessage) @@ -5058,7 +5491,12 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBufferRwSerialize(const NV402C_C // Serialize each 1-byte NvU8 element. for (NvU64 j = 0; j < (src->messageLength); ++j) { - finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pMessage))[j], 1 * 8); + if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pMessage))[j], 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } } // Free memory that was allocated during downward deserialization. @@ -5167,7 +5605,14 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockRwSerialize(const NV402C_ // Field bitmasks field_presence_mask = 0xf; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields // No range check for src->messageLength @@ -5202,7 +5647,12 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockRwSerialize(const NV402C_ // Unbounded fields // Set data-presence indicator. - finn_write_buffer(bp, !!(src->pMessage), 1); + if (finn_write_buffer(bp, !!(src->pMessage), 1)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Skip if pointer is null. if (src->pMessage) @@ -5211,7 +5661,12 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockRwSerialize(const NV402C_ // Serialize each 1-byte NvU8 element. for (NvU64 j = 0; j < (src->messageLength); ++j) { - finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pMessage))[j], 1 * 8); + if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pMessage))[j], 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } } // Free memory that was allocated during downward deserialization. @@ -5315,7 +5770,14 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusProcessCallSerialize(const NV4 // Field bitmasks field_presence_mask = 0x7; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields // No range check for src->writeMessage @@ -5404,10 +5866,17 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockProcessCallSerialize(cons // Field bitmasks field_presence_mask = 0x1f; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields - if (src->writeMessageLength < 0 || src->writeMessageLength > NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX) + if (src->writeMessageLength > NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX) { status = NV_ERR_OUT_OF_RANGE; FINN_ERROR(NV_ERR_OUT_OF_RANGE); @@ -5423,7 +5892,7 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockProcessCallSerialize(cons } - if (src->readMessageLength < 0 || src->readMessageLength > NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX) + if (src->readMessageLength > NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX) { status = NV_ERR_OUT_OF_RANGE; FINN_ERROR(NV_ERR_OUT_OF_RANGE); @@ -5505,7 +5974,7 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockProcessCallDeserialize(fi // Statically sized fields // Deserialize 4-byte NvU32 object. dst->writeMessageLength = (NvU32) finn_read_buffer(bp, 4 * 8); - if (dst->writeMessageLength < 0 || dst->writeMessageLength > NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX) + if (dst->writeMessageLength > NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX) { status = NV_ERR_OUT_OF_RANGE; FINN_ERROR(NV_ERR_OUT_OF_RANGE); @@ -5516,7 +5985,7 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockProcessCallDeserialize(fi // Deserialize 4-byte NvU32 object. dst->readMessageLength = (NvU32) finn_read_buffer(bp, 4 * 8); - if (dst->readMessageLength < 0 || dst->readMessageLength > NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX) + if (dst->readMessageLength > NV402C_CTRL_I2C_BLOCK_PROCESS_PROTOCOL_MAX) { status = NV_ERR_OUT_OF_RANGE; FINN_ERROR(NV_ERR_OUT_OF_RANGE); @@ -5559,7 +6028,14 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwSerial // Field bitmasks field_presence_mask = 0x3f; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields // No range check for src->warFlags @@ -5572,7 +6048,7 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwSerial } - if (src->indexLength < 0 || src->indexLength > NV402C_CTRL_I2C_INDEX_LENGTH_MAX) + if (src->indexLength > NV402C_CTRL_I2C_INDEX_LENGTH_MAX) { status = NV_ERR_OUT_OF_RANGE; FINN_ERROR(NV_ERR_OUT_OF_RANGE); @@ -5623,7 +6099,12 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwSerial // Unbounded fields // Set data-presence indicator. - finn_write_buffer(bp, !!(src->pMessage), 1); + if (finn_write_buffer(bp, !!(src->pMessage), 1)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Skip if pointer is null. if (src->pMessage) @@ -5632,7 +6113,12 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwSerial // Serialize each 1-byte NvU8 element. for (NvU64 j = 0; j < (src->messageLength); ++j) { - finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pMessage))[j], 1 * 8); + if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pMessage))[j], 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } } // Free memory that was allocated during downward deserialization. @@ -5675,7 +6161,7 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwDeseri // Deserialize 4-byte NvU32 object. dst->indexLength = (NvU32) finn_read_buffer(bp, 4 * 8); - if (dst->indexLength < 0 || dst->indexLength > NV402C_CTRL_I2C_INDEX_LENGTH_MAX) + if (dst->indexLength > NV402C_CTRL_I2C_INDEX_LENGTH_MAX) { status = NV_ERR_OUT_OF_RANGE; FINN_ERROR(NV_ERR_OUT_OF_RANGE); @@ -5755,7 +6241,14 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataReadEdidDdcSerialize(const NV402C_C // Field bitmasks field_presence_mask = 0xf; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields // No range check for src->messageLength @@ -5790,7 +6283,12 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataReadEdidDdcSerialize(const NV402C_C // Unbounded fields // Set data-presence indicator. - finn_write_buffer(bp, !!(src->pMessage), 1); + if (finn_write_buffer(bp, !!(src->pMessage), 1)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Skip if pointer is null. if (src->pMessage) @@ -5799,7 +6297,12 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataReadEdidDdcSerialize(const NV402C_C // Serialize each 1-byte NvU8 element. for (NvU64 j = 0; j < (src->messageLength); ++j) { - finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pMessage))[j], 1 * 8); + if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pMessage))[j], 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } } // Free memory that was allocated during downward deserialization. @@ -5903,7 +6406,14 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSerialize(const NV402C_CTRL_I2C_TRA // Field bitmasks field_presence_mask = 0x7ff; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Field copying based on union selector switch (transType) @@ -6143,7 +6653,14 @@ static NV_STATUS Nv402cCtrlI2cTransactionParamsSerialize(const NV402C_CTRL_I2C_T // Field bitmasks field_presence_mask = 0x1f; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields // No range check for src->flags @@ -6265,7 +6782,14 @@ static NV_STATUS Nv83deCtrlDebugReadMemoryParamsSerialize(const NV83DE_CTRL_DEBU // Field bitmasks field_presence_mask = 0xf; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields // No range check for src->offset @@ -6300,7 +6824,12 @@ static NV_STATUS Nv83deCtrlDebugReadMemoryParamsSerialize(const NV83DE_CTRL_DEBU // Unbounded fields // Set data-presence indicator. - finn_write_buffer(bp, !!(src->buffer), 1); + if (finn_write_buffer(bp, !!(src->buffer), 1)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Skip if pointer is null. if (src->buffer) @@ -6309,7 +6838,12 @@ static NV_STATUS Nv83deCtrlDebugReadMemoryParamsSerialize(const NV83DE_CTRL_DEBU // Serialize each 1-byte NvU8 element. for (NvU64 j = 0; j < (src->length); ++j) { - finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->buffer))[j], 1 * 8); + if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->buffer))[j], 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } } // Free memory that was allocated during downward deserialization. @@ -6413,7 +6947,14 @@ static NV_STATUS Nv83deCtrlDebugWriteMemoryParamsSerialize(const NV83DE_CTRL_DEB // Field bitmasks field_presence_mask = 0xf; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields // No range check for src->offset @@ -6448,7 +6989,12 @@ static NV_STATUS Nv83deCtrlDebugWriteMemoryParamsSerialize(const NV83DE_CTRL_DEB // Unbounded fields // Set data-presence indicator. - finn_write_buffer(bp, !!(src->buffer), 1); + if (finn_write_buffer(bp, !!(src->buffer), 1)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Skip if pointer is null. if (src->buffer) @@ -6457,7 +7003,12 @@ static NV_STATUS Nv83deCtrlDebugWriteMemoryParamsSerialize(const NV83DE_CTRL_DEB // Serialize each 1-byte NvU8 element. for (NvU64 j = 0; j < (src->length); ++j) { - finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->buffer))[j], 1 * 8); + if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->buffer))[j], 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } } // Free memory that was allocated during downward deserialization. @@ -6561,7 +7112,14 @@ static NV_STATUS Nvb06fCtrlGetEngineCtxDataParamsSerialize(const NVB06F_CTRL_GET // Field bitmasks field_presence_mask = 0x7; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields // No range check for src->engineID @@ -6586,7 +7144,12 @@ static NV_STATUS Nvb06fCtrlGetEngineCtxDataParamsSerialize(const NVB06F_CTRL_GET // Unbounded fields // Set data-presence indicator. - finn_write_buffer(bp, !!(src->pEngineCtxBuff), 1); + if (finn_write_buffer(bp, !!(src->pEngineCtxBuff), 1)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Skip if pointer is null. if (src->pEngineCtxBuff) @@ -6595,7 +7158,12 @@ static NV_STATUS Nvb06fCtrlGetEngineCtxDataParamsSerialize(const NVB06F_CTRL_GET // Serialize each 1-byte NvU8 element. for (NvU64 j = 0; j < (src->size); ++j) { - finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pEngineCtxBuff))[j], 1 * 8); + if (finn_write_buffer(bp, ((NvU8 *) NvP64_VALUE(src->pEngineCtxBuff))[j], 1 * 8)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } } // Free memory that was allocated during downward deserialization. @@ -6694,7 +7262,14 @@ static NV_STATUS Nvb06fCtrlCmdMigrateEngineCtxDataFinnParamsSerialize(const NVB0 // Field bitmasks field_presence_mask = 0x1; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Unbounded fields status = Nvb06fCtrlGetEngineCtxDataParamsSerialize(&src->params, bp, seri_up); @@ -6746,7 +7321,14 @@ static NV_STATUS Nvb06fCtrlSaveEngineCtxDataParamsSerialize(const NVB06F_CTRL_SA // Field bitmasks field_presence_mask = 0x7; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Statically sized fields // No range check for src->engineID @@ -6841,7 +7423,14 @@ static NV_STATUS Nvb06fCtrlCmdRestoreEngineCtxDataFinnParamsSerialize(const NVB0 // Field bitmasks field_presence_mask = 0x1; - finn_write_buffer(bp, field_presence_mask, 64); + + // Write field-presence indicators. + if (finn_write_buffer(bp, field_presence_mask, 64)) + { + status = NV_ERR_BUFFER_TOO_SMALL; + FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); + goto exit; + } // Bounded nested fields status = Nvb06fCtrlSaveEngineCtxDataParamsSerialize(&src->params, bp, seri_up); diff --git a/src/nvidia/kernel/inc/dev_p2060.h b/src/nvidia/kernel/inc/dev_p2060.h new file mode 100644 index 000000000..75aa215cd --- /dev/null +++ b/src/nvidia/kernel/inc/dev_p2060.h @@ -0,0 +1,302 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef DEV_P2060_H +#define DEV_P2060_H + +#define NV_P2060_STATUS 0x00 /* R--1R */ +#define NV_P2060_STATUS_VAL 7:0 /* R-XVF */ +#define NV_P2060_STATUS_VCXO 1:0 /* R-XVF */ +#define NV_P2060_STATUS_VCXO_NOLOCK_TOO_FAST 0x00 /* R---V */ +#define NV_P2060_STATUS_VCXO_NOLOCK_TOO_SLOW 0x01 /* R---V */ +#define NV_P2060_STATUS_VCXO_LOCK 0x02 /* R---V */ +#define NV_P2060_STATUS_VCXO_NOT_SERVO 0x03 /* R---V */ +#define NV_P2060_STATUS_SYNC_LOSS 2:2 /* R-XVF */ +#define NV_P2060_STATUS_SYNC_LOSS_FALSE 0x00 /* R---V */ +#define NV_P2060_STATUS_SYNC_LOSS_TRUE 0x01 /* R---V */ +#define NV_P2060_STATUS_RESERVED1 3:3 /* RWXVF */ +#define NV_P2060_STATUS_GPU_STEREO 4:4 /* R-XVF */ +#define NV_P2060_STATUS_GPU_STEREO_NOT_ACTIVE 0x00 /* R---V */ +#define NV_P2060_STATUS_GPU_STEREO_ACTIVE 0x01 /* R---V */ +#define NV_P2060_STATUS_MSTR_STEREO 5:5 /* R-XVF */ +#define NV_P2060_STATUS_MSTR_STEREO_NOT_ACTIVE 0x00 /* R---V */ +#define NV_P2060_STATUS_MSTR_STEREO_ACTIVE 0x01 /* R---V */ +#define NV_P2060_STATUS_STEREO 6:6 /* R-XVF */ +#define NV_P2060_STATUS_STEREO_NOLOCK 0x00 /* R---V */ +#define NV_P2060_STATUS_STEREO_LOCK 0x01 /* R---V */ +#define NV_P2060_STATUS_RESERVED2 7:7 /* RWXVF */ + +#define NV_P2060_STATUS2 0x01 /* RW-1R */ +#define NV_P2060_STATUS2_VAL 7:0 /* R-XVF */ +#define NV_P2060_STATUS2_PORT0 0:0 /* RWIVF */ +#define NV_P2060_STATUS2_PORT0_INPUT 0x00 /* RWI-V */ +#define NV_P2060_STATUS2_PORT0_OUTPUT 0x01 /* RW--V */ +#define NV_P2060_STATUS2_PORT1 1:1 /* RWIVF */ +#define NV_P2060_STATUS2_PORT1_INPUT 0x00 /* RWI-V */ +#define NV_P2060_STATUS2_PORT1_OUTPUT 0x01 /* RW--V */ +#define NV_P2060_STATUS2_ETHER0_DETECTED 2:2 /* RWIVF */ +#define NV_P2060_STATUS2_ETHER0_DETECTED_FALSE 0x00 /* RWI-V */ +#define NV_P2060_STATUS2_ETHER0_DETECTED_TRUE 0x01 /* R---V */ +#define NV_P2060_STATUS2_ETHER1_DETECTED 3:3 /* RWIVF */ +#define NV_P2060_STATUS2_ETHER1_DETECTED_FALSE 0x00 /* RWI-V */ +#define NV_P2060_STATUS2_ETHER1_DETECTED_TRUE 0x01 /* R---V */ +#define NV_P2060_STATUS2_HS_DETECT 5:4 /* RWXVF */ +#define NV_P2060_STATUS2_HS_DETECT_NONE 0x00 /* R---V */ +#define NV_P2060_STATUS2_HS_DETECT_TTL 0x01 /* R---V */ +#define NV_P2060_STATUS2_HS_DETECT_COMPOSITE 0x02 /* R---V */ +#define NV_P2060_STATUS2_HS_DETECT_NOT_IN_USE 0x03 /* R---V */ +#define NV_P2060_STATUS2_GPU_PORT 7:6 /* R-XVF */ +#define NV_P2060_STATUS2_GPU_PORT_CONN0 0x00 /* R---V */ +#define NV_P2060_STATUS2_GPU_PORT_CONN1 0x01 /* R---V */ +#define NV_P2060_STATUS2_GPU_PORT_CONN2 0x02 /* R---V */ +#define NV_P2060_STATUS2_GPU_PORT_CONN3 0x03 /* R---V */ + +#define NV_P2060_STATUS3 0x02 /* RW-1R */ +#define NV_P2060_STATUS3_VAL 7:0 /* R-XVF */ +#define NV_P2060_STATUS3_RESERVED 0:0 /* R-XVF */ +#define NV_P2060_STATUS3_LB_INT_FAIL 1:1 /* R-XVF */ +#define NV_P2060_STATUS3_LB_INT_FAIL_FALSE 0x00 /* RW--V */ +#define NV_P2060_STATUS3_LB_INT_FAIL_TRUE 0x01 /* RW--V */ +#define NV_P2060_STATUS3_LB_VTGRST_FAIL 2:2 /* R-XVF */ +#define NV_P2060_STATUS3_LB_VTGRST_FAIL_FALSE 0x00 /* RW--V */ +#define NV_P2060_STATUS3_LB_VTGRST_FAIL_TRUE 0x01 /* RW--V */ +#define NV_P2060_STATUS3_LB_GSWPRDY_FAIL 3:3 /* R-XVF */ +#define NV_P2060_STATUS3_LB_GSWPRDY_FAIL_FALSE 0x00 /* RW--V */ +#define NV_P2060_STATUS3_LB_GSWPRDY_FAIL_TRUE 0x01 /* RW--V */ +#define NV_P2060_STATUS3_LB_SYNC_FAIL 4:4 /* RWXVF */ +#define NV_P2060_STATUS3_LB_SYNC_FAIL_FALSE 0x00 /* RW--V */ +#define NV_P2060_STATUS3_LB_SYNC_FAIL_TRUE 0x01 /* RW--V */ +#define NV_P2060_STATUS3_LB_STEREO_FAIL 5:5 /* RWXVF */ +#define NV_P2060_STATUS3_LB_STEREO_FAIL_FALSE 0x00 /* RW--V */ +#define NV_P2060_STATUS3_LB_STEREO_FAIL_TRUE 0x01 /* RW--V */ +#define NV_P2060_STATUS3_LB_SWPRDY_FAIL 6:6 /* RWXVF */ +#define NV_P2060_STATUS3_LB_SWPRDY_FAIL_FALSE 0x00 /* RW--V */ +#define NV_P2060_STATUS3_LB_SWPRDY_FAIL_TRUE 0x01 /* RW--V */ +#define NV_P2060_STATUS3_GENLOCKED 7:7 /* RWXVF */ +#define NV_P2060_STATUS3_GENLOCKED_FALSE 0x00 /* RW--V */ +#define NV_P2060_STATUS3_GENLOCKED_TRUE 0x01 /* RW--V */ + +#define NV_P2060_STATUS4 0x13 /* RW-1R */ +#define NV_P2060_STATUS4_VAL 7:0 /* R-XVF */ +#define NV_P2060_STATUS4_INT_GROUP 7:6 /* R-XVF */ +#define NV_P2060_STATUS4_INT_GROUP_LOSS 0x00 /* R-XVF */ +#define NV_P2060_STATUS4_INT_GROUP_GAIN 0x01 /* R-XVF */ +#define NV_P2060_STATUS4_INT_GROUP_MISC 0x02 /* R-XVF */ +#define NV_P2060_STATUS4_SYNC 0:0 /* R---V */ +#define NV_P2060_STATUS4_STEREO 1:1 /* R---V */ +#define NV_P2060_STATUS4_HS 2:2 /* R---V */ +#define NV_P2060_STATUS4_RJ45 3:3 /* R---V */ +#define NV_P2060_STATUS4_RESERVED_GRP01 5:4 /* R---V */ +//Value 1 in bits 0-5 indicate loss and gain depending on interrupt group 00/01 (bit 6-7) +#define NV_P2060_STATUS4_FRM_CNT_MATCH_INT 0:0 /* R-XVF */ +#define NV_P2060_STATUS4_FRM_CNT_MATCH_INT_CLEAR 0x00 /* R---V */ +#define NV_P2060_STATUS4_FRM_CNT_MATCH_INT_PENDING 0x01 /* R---V */ +#define NV_P2060_STATUS4_SWAPRDY_INT 1:1 /* R-XVF */ +#define NV_P2060_STATUS4_SWAPRDY_INT_CLEAR 0x00 /* R---V */ +#define NV_P2060_STATUS4_SWAPRDY_INT_PENDING 0x01 /* R---V */ +#define NV_P2060_STATUS4_ERROR_INT 2:2 /* R-XVF */ +#define NV_P2060_STATUS4_ERROR_INT_CLEAR 0x00 /* R---V */ +#define NV_P2060_STATUS4_ERROR_INT_PENDING 0x01 /* R---V */ +#define NV_P2060_STATUS4_FRM_CNT_ROLLOVER_INT 3:3 /* R-XVF */ +#define NV_P2060_STATUS4_FRM_CNT_ROLLOVER_INT_CLEAR 0x00 /* R---V */ +#define NV_P2060_STATUS4_FRM_CNT_ROLLOVER_INT_PENDING 0x01 /* R---V */ +#define NV_P2060_STATUS4_RESERVED_GRP10 5:4 /* R---V */ +//Value 1 in bits 0-5 indicate interrupt pending depending on interrupt group 10 (bit 6-7) + +#define NV_P2060_CONTROL 0x03 /* RW-1R */ +#define NV_P2060_CONTROL_I_AM 0:0 /* RWXVF */ +#define NV_P2060_CONTROL_I_AM_SLAVE 0x00 /* RWI-V */ +#define NV_P2060_CONTROL_I_AM_MASTER 0x01 /* RWI-V */ +#define NV_P2060_CONTROL_SYNC_POLARITY 2:1 /* RWXVF */ +#define NV_P2060_CONTROL_SYNC_POLARITY_RISING_EDGE 0x00 /* RW--V */ +#define NV_P2060_CONTROL_SYNC_POLARITY_FALLING_EDGE 0x01 /* RW--V */ +#define NV_P2060_CONTROL_SYNC_POLARITY_BOTH 0x02 /* RW--V */ +#define NV_P2060_CONTROL_TEST_MODE 3:3 /* RWXVF */ +#define NV_P2060_CONTROL_TEST_MODE_OFF 0x00 /* RW--V */ +#define NV_P2060_CONTROL_TEST_MODE_ON 0x01 /* RW--V */ +#define NV_P2060_CONTROL_SYNC_SRC 5:4 /* RWXVF */ +#define NV_P2060_CONTROL_SYNC_SRC_CONN0 0x00 /* RW--V */ +#define NV_P2060_CONTROL_SYNC_SRC_CONN1 0x01 /* RW--V */ +#define NV_P2060_CONTROL_SYNC_SRC_CONN2 0x02 /* RW--V */ +#define NV_P2060_CONTROL_SYNC_SRC_CONN3 0x03 /* RW--V */ +#define NV_P2060_CONTROL_INTERLACE_MODE 6:6 /* RWXVF */ +#define NV_P2060_CONTROL_INTERLACE_MODE_FALSE 0x00 /* RW--V */ +#define NV_P2060_CONTROL_INTERLACE_MODE_TRUE 0x01 /* RW--V */ +#define NV_P2060_CONTROL_SYNC_SELECT 7:7 /* RWXVF */ +#define NV_P2060_CONTROL_SYNC_SELECT_INTERNAL 0x00 /* RW--V */ +#define NV_P2060_CONTROL_SYNC_SELECT_HOUSE 0x01 /* RW--V */ + +#define NV_P2060_CONTROL2 0x04 /* RW-1R */ +#define NV_P2060_CONTROL2_LAMUX 1:0 /* RWXVF */ +#define NV_P2060_CONTROL2_LAMUX_0 0x00 /* RWI-V */ +#define NV_P2060_CONTROL2_FRAMERATE_RPT 3:2 /* RWXVF */ +#define NV_P2060_CONTROL2_FRAMERATE_RPT_LIVE 0x00 /* RW--V */ +#define NV_P2060_CONTROL2_FRAMERATE_RPT_MIN 0x02 /* RW--V */ +#define NV_P2060_CONTROL2_FRAMERATE_RPT_MAX 0x03 /* RW--V */ +#define NV_P2060_CONTROL2_RESET 4:4 /* RWXVF */ +#define NV_P2060_CONTROL2_RESET_FALSE 0x00 /* RW--V */ +#define NV_P2060_CONTROL2_RESET_TRUE 0x01 /* RW--V */ +#define NV_P2060_CONTROL2_SWAP_READY 5:5 /* RWXVF */ +#define NV_P2060_CONTROL2_SWAP_READY_DISABLE 0x00 /* RW--V */ +#define NV_P2060_CONTROL2_SWAP_READY_ENABLE 0x01 /* RW--V */ +#define NV_P2060_CONTROL2_RESERVED 6:6 /* RWXVF */ +#define NV_P2060_CONTROL2_LOOPBACK_MODE 7:7 /* RWXVF */ +#define NV_P2060_CONTROL2_LOOPBACK_MODE_OFF 0x00 /* RW--V */ +#define NV_P2060_CONTROL2_LOOPBACK_MODE_ON 0x01 /* RW--V */ + +#define NV_P2060_CONTROL3 0x05 /* RW-1R */ +#define NV_P2060_CONTROL3_INTERRUPT 6:0 /* RWXVF */ +#define NV_P2060_CONTROL3_INTERRUPT_DISABLE 0x00 /* RW--V */ +#define NV_P2060_CONTROL3_INTERRUPT_ON_STEREO_CHG 0x01 /* RW--V */ +#define NV_P2060_CONTROL3_INTERRUPT_ON_ERROR 0x02 /* RW--V */ +#define NV_P2060_CONTROL3_INTERRUPT_ON_FRAME_MATCH 0x04 /* RW--V */ +#define NV_P2060_CONTROL3_INTERRUPT_ON_HS_CHG 0x08 /* RW--V */ +#define NV_P2060_CONTROL3_INTERRUPT_ON_SYNC_CHG 0x10 /* RW--V */ +#define NV_P2060_CONTROL3_INTERRUPT_ON_RJ45_CHG 0x20 /* RW--V */ +#define NV_P2060_CONTROL3_INTERRUPT_ON_ALL 0x7f /* RW--V */ +#define NV_P2060_CONTROL3_RESYNC 7:7 /* RWXVF */ +#define NV_P2060_CONTROL3_RESYNC_OFF 0x00 /* RW--V */ +#define NV_P2060_CONTROL3_RESYNC_ON 0x01 /* RW--V */ + +#define NV_P2060_CONTROL4 0x06 /* RW-1R */ +#define NV_P2060_CONTROL4_SWPRDYINT_DELAY 2:0 /* RWXVF */ +#define NV_P2060_CONTROL4_STEREO_LOCK_MODE 3:3 /* RWXVF */ +#define NV_P2060_CONTROL4_STEREO_LOCK_MODE_OFF 0x00 /* RW--V */ +#define NV_P2060_CONTROL4_STEREO_LOCK_MODE_ON 0x01 /* RW--V */ +#define NV_P2060_CONTROL4_EXT_STEREO_SYNC 4:4 /* RWXVF */ +#define NV_P2060_CONTROL4_EXT_STEREO_SYNC_OFF 0x00 /* RW--V */ +#define NV_P2060_CONTROL4_EXT_STEREO_SYNC_ON 0x01 /* RW--V */ +#define NV_P2060_CONTROL4_EXT_STEREO_SYNC_POL 5:5 /* RWXVF */ +#define NV_P2060_CONTROL4_EXT_STEREO_SYNC_POL_LOW 0x00 /* RW--V */ +#define NV_P2060_CONTROL4_EXT_STEREO_SYNC_POL_HI 0x01 /* RW--V */ +#define NV_P2060_CONTROL4_RESERVED2 7:6 /* RWXVF */ + +#define NV_P2060_FPGA 0x07 /* R--1R */ +#define NV_P2060_FPGA_REV 3:0 /* R-XVF */ + +#define NV_P2060_FPGA_ID 7:4 /* R-XVF */ +#define NV_P2060_FPGA_ID_0 0x00 /* R---V */ +#define NV_P2060_FPGA_ID_5 0x05 /* R---V */ + +#define NV_P2061_FPGA_ID 7:4 /* R-XVF */ +#define NV_P2061_FPGA_ID_4 0x04 /* R---V */ + +#define NV_P2060_SYNC_SKEW_LOW 0x08 /* RW-1R */ +#define NV_P2060_SYNC_SKEW_LOW_VAL 7:0 /* RWIVF */ +#define NV_P2060_SYNC_SKEW_LOW_VAL_0 0x00 /* RWI-V */ + +#define NV_P2060_SYNC_SKEW_HIGH 0x09 /* RW-1R */ +#define NV_P2060_SYNC_SKEW_HIGH_VAL 7:0 /* RWIVF */ +#define NV_P2060_SYNC_SKEW_HIGH_VAL_0 0x00 /* RWI-V */ + +#define NV_P2060_START_DELAY_LOW 0x0A /* RW-1R */ +#define NV_P2060_START_DELAY_LOW_VAL 7:0 /* RWIVF */ +#define NV_P2060_START_DELAY_LOW_VAL_0 0x00 /* RWI-V */ + +#define NV_P2060_START_DELAY_HIGH 0x0B /* RW-1R */ +#define NV_P2060_START_DELAY_HIGH_VAL 7:0 /* RWIVF */ +#define NV_P2060_START_DELAY_HIGH_VAL_0 0x00 /* RWI-V */ + +#define NV_P2060_NSYNC 0x0C /* RW-1R */ +#define NV_P2060_NSYNC_FL 2:0 /* RWIVF */ +#define NV_P2060_NSYNC_GPU 6:4 /* RWIVF */ +#define NV_P2060_NSYNC_ALL 7:0 /* RWIVF */ + +#define NV_P2060_FRAMECNTR_LOW 0x0D /* R--1R */ +#define NV_P2060_FRAMECNTR_LOW_VAL 7:0 /* RWIVF */ +#define NV_P2060_FRAMECNTR_LOW_VAL_0 0x00 /* RWI-V */ + +#define NV_P2060_FRAMECNTR_MID 0x0E /* R--1R */ +#define NV_P2060_FRAMECNTR_MID_VAL 7:0 /* RWIVF */ +#define NV_P2060_FRAMECNTR_MID_VAL_0 0x00 /* RWI-V */ + +#define NV_P2060_FRAMECNTR_HIGH 0x0F /* R--1R */ +#define NV_P2060_FRAMECNTR_HIGH_VAL 7:0 /* RWIVF */ +#define NV_P2060_FRAMECNTR_HIGH_VAL_0 0x00 /* RWI-V */ + +#define NV_P2060_FRAMERATE_LOW 0x10 /* R--1R */ +#define NV_P2060_FRAMERATE_LOW_VAL 7:0 /* RWIVF */ +#define NV_P2060_FRAMERATE_LOW_VAL_0 0x00 /* RWI-V */ + +#define NV_P2060_FRAMERATE_MID 0x11 /* R--1R */ +#define NV_P2060_FRAMERATE_MID_VAL 7:0 /* RWIVF */ +#define NV_P2060_FRAMERATE_MID_VAL_0 0x00 /* RWI-V */ + +#define NV_P2060_FRAMERATE_HIGH 0x12 /* R--1R */ +#define NV_P2060_FRAMERATE_HIGH_VAL 7:0 /* RWIVF */ +#define NV_P2060_FRAMERATE_HIGH_VAL_0 0x00 /* RWI-V */ + +#define NV_P2060_FPGA_EXREV 0x17 /* R--1R */ +#define NV_P2060_FPGA_EXREV_VAL 7:0 /* RWIVF */ +#define NV_P2060_FPGA_EXREV_VAL_0 0x00 /* RWI-V */ + +#define NV_P2060_FPGA_ASGN_ID_0 0x18 /* R--1R */ +#define NV_P2060_FPGA_ASGN_ID_0_VAL 7:0 /* RWIVF */ +#define NV_P2060_FPGA_ASGN_ID_1 0x19 /* R--1R */ +#define NV_P2060_FPGA_ASGN_ID_1_VAL 7:0 /* RWIVF */ +#define NV_P2060_FPGA_ASGN_ID_2 0x1A /* R--1R */ +#define NV_P2060_FPGA_ASGN_ID_2_VAL 7:0 /* RWIVF */ +#define NV_P2060_FPGA_ASGN_ID_3 0x1B /* R--1R */ +#define NV_P2060_FPGA_ASGN_ID_3_VAL 7:0 /* RWIVF */ + +#define NV_P2060_FPGA_ASGN_ID(i) (0x18 + i) + +#define NV_P2060_FRAME_CMPR_LOW 0x1D /* R--1R */ +#define NV_P2060_FRAME_CMPR_LOW_VAL 7:0 /* RWIVF */ +#define NV_P2060_FRAME_CMPR_LOW_VAL_0 0x00 /* RWI-V */ + +#define NV_P2060_FRAME_CMPR_MID 0x1E /* R--1R */ +#define NV_P2060_FRAME_CMPR_MID_VAL 7:0 /* RWIVF */ +#define NV_P2060_FRAME_CMPR_MID_VAL_0 0x00 /* RWI-V */ + +#define NV_P2060_FRAME_CMPR_HIGH 0x1F /* R--1R */ +#define NV_P2060_FRAME_CMPR_HIGH_VAL 7:0 /* RWIVF */ +#define NV_P2060_FRAME_CMPR_HIGH_VAL_0 0x00 /* RWI-V */ + +#define NV_P2060_HS_FRAMERATE_LOW 0x20 /* R--1R */ +#define NV_P2060_HS_FRAMERATE_LOW_VAL 7:0 /* RWIVF */ +#define NV_P2060_HS_FRAMERATE_LOW_VAL_0 0x00 /* RWI-V */ + +#define NV_P2060_HS_FRAMERATE_MID 0x21 /* R--1R */ +#define NV_P2060_HS_FRAMERATE_MID_VAL 7:0 /* RWIVF */ +#define NV_P2060_HS_FRAMERATE_MID_VAL_0 0x00 /* RWI-V */ + +#define NV_P2060_HS_FRAMERATE_HIGH 0x22 /* R--1R */ +#define NV_P2060_HS_FRAMERATE_HIGH_VAL 7:0 /* RWIVF */ +#define NV_P2060_HS_FRAMERATE_HIGH_VAL_0 0x00 /* RWI-V */ + +#define NV_P2060_MOSAIC_MODE 0x23 /* RW-1R */ +#define NV_P2060_MOSAIC_MODE_TS 1:0 /* RWIVF */ +#define NV_P2060_MOSAIC_MODE_TS_CONN0 0x00 /* R---V */ +#define NV_P2060_MOSAIC_MODE_TS_CONN1 0x01 /* RW--V */ +#define NV_P2060_MOSAIC_MODE_TS_CONN2 0x02 /* RW--V */ +#define NV_P2060_MOSAIC_MODE_TS_CONN3 0x03 /* RW--V */ +#define NV_P2060_MOSAIC_MODE_GROUP 2:2 /* RWIVF */ +#define NV_P2060_MOSAIC_MODE_GROUP_ZERO 0x00 /* RW--V */ +#define NV_P2060_MOSAIC_MODE_GROUP_ONE 0x01 /* RW--V */ +#define NV_P2060_MOSAIC_MODE_ENABLE 3:3 /* RWIVF */ +#define NV_P2060_MOSAIC_MODE_ENABLE_FALSE 0x00 /* RW--V */ +#define NV_P2060_MOSAIC_MODE_ENABLE_TRUE 0x01 /* RW--V */ +#define NV_P2060_MOSAIC_MODE_RESERVED 7:4 /* RWIVF */ + +#endif //DEV_P2060_H diff --git a/src/nvidia/kernel/inc/dev_p2061.h b/src/nvidia/kernel/inc/dev_p2061.h new file mode 100644 index 000000000..5c8366a52 --- /dev/null +++ b/src/nvidia/kernel/inc/dev_p2061.h @@ -0,0 +1,37 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef DEV_P2061_H +#define DEV_P2061_H + +#define NV_P2061_CONTROL4 0x06 /* RW-1R */ +#define NV_P2061_CONTROL4_HOUSE_SYNC_MODE 6:6 /* RWXVF */ +#define NV_P2061_CONTROL4_HOUSE_SYNC_MODE_INPUT 0x0 /* RW--V */ +#define NV_P2061_CONTROL4_HOUSE_SYNC_MODE_OUTPUT 0x1 /* RW--V */ + +#define NV_P2061_STATUS6 0x2E /* RW-1R */ +#define NV_P2061_STATUS6_INT_PORT_DIRECTION 7:7 /* RWXVF */ +#define NV_P2061_STATUS6_INT_PORT_DIRECTION_INPUT 0 /* RWXVF */ +#define NV_P2061_STATUS6_INT_PORT_DIRECTION_OUTPUT 1 /* RWXVF */ + +#endif //DEV_P2061_H diff --git a/src/nvidia/kernel/inc/nvpcf.h b/src/nvidia/kernel/inc/nvpcf.h new file mode 100644 index 000000000..680044991 --- /dev/null +++ b/src/nvidia/kernel/inc/nvpcf.h @@ -0,0 +1,205 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVPCF_H +#define NVPCF_H + +#include "ctrl/ctrl0000/ctrl0000system.h" + +/* + * Definitions for the dynamic params table. + */ +#define NVPCF0100_CTRL_DYNAMIC_TABLE_1X_VERSION (0x10) +#define NVPCF0100_CTRL_DYNAMIC_TABLE_1X_ENTRY_SIZE (4U) +// +// This is set to 32UL in windows NVPCF driver. Set it to 2UL which is good +// enough for now to save space +// +#define NVPCF0100_CTRL_DYNAMIC_TABLE_1X_ENTRY_MAX (2UL) +#define NVPCF0100_CTRL_DYNAMIC_TABLE_1X_INPUT_CMD_GET_TPP (0x04) + +/* + * Dynamic Params Table Header, v1.x. + */ +typedef struct +{ + NvU8 version; + + NvU8 size; + + // + // Number of entries in the entire table. + // + NvU8 entryCnt; + + NvU8 reserved; + +} NVPCF0100_CTRL_DYNAMIC_TABLE_1X_HEADER, +*PNVPCF0100_CTRL_DYNAMIC_TABLE_1X_HEADER; + +/* + * Define the dynamic params table header and entries used by the ACPI call. + */ +typedef struct +{ + NVPCF0100_CTRL_DYNAMIC_TABLE_1X_HEADER header; + NvU32 entries[NVPCF0100_CTRL_DYNAMIC_TABLE_1X_ENTRY_MAX]; +} CONTROLLER_DYNAMIC_TABLE_1X_ACPI, +*PCONTROLLER_DYNAMIC_TABLE_1X_ACPI; + +/*! + * Config DSM NVPCF 2x version specific defines + */ +#define NVPCF_DYNAMIC_PARAMS_20_VERSION (0x20) +#define NVPCF_DYNAMIC_PARAMS_21_VERSION (0x21) +#define NVPCF_DYNAMIC_PARAMS_2X_HEADER_SIZE_05 (0x05U) +#define NVPCF_DYNAMIC_PARAMS_2X_HEADER_FMT_SIZE_05 ("5b") +#define NVPCF_DYNAMIC_PARAMS_2X_COMMON_SIZE_10 (0x10U) +#define NVPCF_DYNAMIC_PARAMS_2X_COMMON_FMT_SIZE_10 ("4d") +#define NVPCF_DYNAMIC_PARAMS_2X_ENTRY_SIZE_1C (0x1CU) +#define NVPCF_DYNAMIC_PARAMS_2X_ENTRY_FMT_SIZE_1C ("7d") +#define NVPCF_DYNAMIC_PARAMS_2X_ENTRY_MAX (8) + +// Power unit used, 125 milli-watts +#define NVPCF_DYNAMIC_PARAMS_2X_POWER_UNIT_MW (125) + +/*! + * Dynamic params header, unpacked. + */ +typedef struct +{ + /* + * Dynamic params table Version. + */ + NvU32 version; + + /* + * Size of dynamic params table header in bytes. + */ + NvU32 headerSize; + + /* + * Size of global/common entry in bytes. + */ + NvU32 commonSize; + + /* + * Size of each controller entry in bytes. + */ + NvU32 entrySize; + + /* + * Number of controller entries. + */ + NvU32 entryCount; +} DYNAMIC_PARAMS_HEADER_2X; + +/*! + * Dynamic params table global/common, unpacked. + */ +typedef struct +{ + NvU32 param0; + NvU32 param1; + NvU32 param2; + NvU32 param3; +} DYNAMIC_PARAMS_COMMON_2X; + +/*! + * Dynamic params table controller entry, unpacked. + */ +typedef struct +{ + NvU32 param0; + NvU32 param1; + NvU32 param2; + NvU32 param3; + NvU32 param4; + NvU32 param5; + NvU32 param6; +} DYNAMIC_PARAMS_ENTRY_2X; + +/*! + * Dynamic params table header, packed. + */ +typedef struct +{ + NvU8 version; + NvU8 headerSize; + NvU8 commonSize; + NvU8 entrySize; + NvU8 entryCount; +} DYNAMIC_PARAMS_HEADER_2X_PACKED; + +/*! + * Dynamic params table global/common, packed. + */ +typedef struct +{ + NvU32 param0; + NvU32 param1; + NvU32 param2; + NvU32 param3; +} DYNAMIC_PARAMS_COMMON_2X_PACKED; + +/*! + * Dynamic params table controller entry, packed. + */ +typedef struct +{ + NvU32 param0; + NvU32 param1; + NvU32 param2; + NvU32 param3; + NvU32 param4; + NvU32 param5; + NvU32 param6; +} DYNAMIC_PARAMS_ENTRY_2X_PACKED; + +// Input Commands (Input Param0) +#define NVPCF_DYNAMIC_PARAMS_COMMON_2X_INPUT_PARAM0_CMD 1:0 +#define NVPCF_DYNAMIC_PARAMS_COMMON_2X_INPUT_PARAM0_CMD_GET (0) +#define NVPCF_DYNAMIC_PARAMS_COMMON_2X_INPUT_PARAM0_CMD_SET (1) + +// +// Input Command 0 (Get Controller Parameters) +// +// Global/Common Entry, Output Param0 +#define NVPCF_DYNAMIC_PARAMS_COMMON_2X_OUTPUT_PARAM0_CMD0_CTGP_AC_OFFSET 15:0 +#define NVPCF_DYNAMIC_PARAMS_COMMON_2X_OUTPUT_PARAM0_CMD0_CTGP_DC_OFFSET 31:16 +// Controller Entry, Output Param0 +#define NVPCF_DYNAMIC_PARAMS_ENTRY_2X_OUTPUT_PARAM0_CMD0_IDX 7:0 +#define NVPCF_DYNAMIC_PARAMS_ENTRY_2X_OUTPUT_PARAM0_CMD0_DISABLE_AC 8:8 +#define NVPCF_DYNAMIC_PARAMS_ENTRY_2X_OUTPUT_PARAM0_CMD0_DISABLE_DC 9:9 +// Controller Entry, Output Params1 +#define NVPCF_DYNAMIC_PARAMS_ENTRY_2X_OUTPUT_PARAM1_CMD0_SIGNED0 15:0 +#define NVPCF_DYNAMIC_PARAMS_ENTRY_2X_OUTPUT_PARAM1_CMD0_SIGNED1 31:16 +// Controller Entry, Output Params2 +#define NVPCF_DYNAMIC_PARAMS_ENTRY_2X_OUTPUT_PARAM2_CMD0_SIGNED0 15:0 +#define NVPCF_DYNAMIC_PARAMS_ENTRY_2X_OUTPUT_PARAM2_CMD0_SIGNED1 31:16 +// Controller Entry, Output Params3 +#define NVPCF_DYNAMIC_PARAMS_ENTRY_2X_OUTPUT_PARAM3_CMD0_SIGNED0 15:0 +#define NVPCF_DYNAMIC_PARAMS_ENTRY_2X_OUTPUT_PARAM3_CMD0_SIGNED1 31:16 + +#endif // NVPCF_H + diff --git a/src/nvidia/kernel/inc/objrpc.h b/src/nvidia/kernel/inc/objrpc.h index 184a7d80c..d3bc6a654 100644 --- a/src/nvidia/kernel/inc/objrpc.h +++ b/src/nvidia/kernel/inc/objrpc.h @@ -45,6 +45,13 @@ typedef struct _object_vgpu OBJVGPU, *POBJVGPU; #include "g_rpc_hal.h" // For RPC_HAL_IFACES #include "g_rpc_odb.h" // For RPC_HAL_IFACES +#define RPC_HISTORY_DEPTH 8 +typedef struct RpcHistoryEntry +{ + NvU32 function; + NvU32 data[3]; +} RpcHistoryEntry; + struct OBJRPC{ OBJECT_BASE_DEFINITION(RPC); @@ -71,6 +78,9 @@ struct OBJRPC{ struct _message_queue_info *pMessageQueueInfo; RmPhysAddr messageQueuePhysMem; + RpcHistoryEntry rpcHistory[RPC_HISTORY_DEPTH]; + NvU32 rpcHistoryCurrent; + }; // diff --git a/src/nvidia/kernel/inc/vgpu/rpc.h b/src/nvidia/kernel/inc/vgpu/rpc.h index c95edf165..f2d104af6 100644 --- a/src/nvidia/kernel/inc/vgpu/rpc.h +++ b/src/nvidia/kernel/inc/vgpu/rpc.h @@ -108,7 +108,7 @@ static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { r \ root_alloc_params.hClient = hclient; \ \ - if (!IsT234D(pGpu)) \ + if (!IsT234DorBetter(pGpu)) \ { \ RmClient *pClient = NULL; \ \ @@ -165,7 +165,7 @@ static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { r && (!(IS_VIRTUAL_WITH_SRIOV(pGpu) && \ !gpuIsWarBug200577889SriovHeavyEnabled(pGpu) && \ !NV_IS_MODS))) { \ - if (IS_GSP_CLIENT(pGpu) && IsT234D(pGpu)) \ + if (IS_GSP_CLIENT(pGpu) && IsT234DorBetter(pGpu)) \ { \ RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); \ NV_MEMORY_LIST_ALLOCATION_PARAMS listAllocParams = {0}; \ diff --git a/src/nvidia/kernel/inc/vgpu/rpc_global_enums.h b/src/nvidia/kernel/inc/vgpu/rpc_global_enums.h index b5e0ec872..f520efebc 100644 --- a/src/nvidia/kernel/inc/vgpu/rpc_global_enums.h +++ b/src/nvidia/kernel/inc/vgpu/rpc_global_enums.h @@ -197,6 +197,14 @@ enum { X(RM, PMA_SCRUBBER_SHARED_BUFFER_GUEST_PAGES_OPERATION) //188 X(RM, CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK) //189 X(RM, SET_SYSMEM_DIRTY_PAGE_TRACKING_BUFFER) //190 + X(RM, CTRL_SUBDEVICE_GET_P2P_CAPS) // 191 + X(RM, CTRL_BUS_SET_P2P_MAPPING) // 192 + X(RM, CTRL_BUS_UNSET_P2P_MAPPING) // 193 + X(RM, CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK) // 194 + X(RM, CTRL_GPU_MIGRATABLE_OPS) // 195 + X(RM, CTRL_GET_TOTAL_HS_CREDITS) // 196 + X(RM, CTRL_GET_HS_CREDITS) // 197 + X(RM, CTRL_SET_HS_CREDITS) // 198 X(RM, NUM_FUNCTIONS) //END #ifdef DEFINING_X_IN_RPC_GLOBAL_ENUMS_H }; @@ -228,6 +236,15 @@ enum { E(PERF_BRIDGELESS_INFO_UPDATE) // 0x100f E(VGPU_CONFIG) // 0x1010 E(DISPLAY_MODESET) // 0x1011 + E(EXTDEV_INTR_SERVICE) // 0x1012 + E(NVLINK_INBAND_RECEIVED_DATA_256) // 0x1013 + E(NVLINK_INBAND_RECEIVED_DATA_512) // 0x1014 + E(NVLINK_INBAND_RECEIVED_DATA_1024) // 0x1015 + E(NVLINK_INBAND_RECEIVED_DATA_2048) // 0x1016 + E(NVLINK_INBAND_RECEIVED_DATA_4096) // 0x1017 + E(TIMED_SEMAPHORE_RELEASE) // 0x1018 + E(NVLINK_IS_GPU_DEGRADED) // 0x1019 + E(PFM_REQ_HNDLR_STATE_SYNC_CALLBACK) // 0x101a E(NUM_EVENTS) // END #ifdef DEFINING_E_IN_RPC_GLOBAL_ENUMS_H }; diff --git a/src/nvidia/kernel/inc/vgpu/rpc_headers.h b/src/nvidia/kernel/inc/vgpu/rpc_headers.h index 3a1826b74..bff16d54d 100644 --- a/src/nvidia/kernel/inc/vgpu/rpc_headers.h +++ b/src/nvidia/kernel/inc/vgpu/rpc_headers.h @@ -206,6 +206,19 @@ typedef enum UVM_PAGING_CHANNEL_VASPACE_FREE, } UVM_PAGING_CHANNEL_VASPACE_OPERATION; +typedef struct VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS +{ + NvU32 headIndex; + NvU32 maxHResolution; + NvU32 maxVResolution; +} VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS; + +typedef struct VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS +{ + NvU32 numHeads; + NvU32 maxNumHeads; +} VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS; + /* * Maximum guest pages that can be mapped for UVM method stream @@ -214,4 +227,10 @@ typedef enum #define PMA_SCRUBBER_SHARED_BUFFER_MAX_GUEST_PAGES_v1F_0C 500 +/* + * Maximum number of SMs that can be read in one RPC call to get error states + */ + +#define VGPU_RPC_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PER_RPC_v21_06 80 + #endif // __vgpu_rpc_nv_headers_h__ diff --git a/src/nvidia/kernel/inc/vgpu/sdk-structures.h b/src/nvidia/kernel/inc/vgpu/sdk-structures.h index bf64f0b0a..e40207ba1 100644 --- a/src/nvidia/kernel/inc/vgpu/sdk-structures.h +++ b/src/nvidia/kernel/inc/vgpu/sdk-structures.h @@ -26,7 +26,6 @@ #define _RPC_SDK_STRUCTURES_H_ #include -#include #include #include #include @@ -63,6 +62,7 @@ #include #include "rpc_headers.h" #include "nvctassert.h" +#include "nv_vgpu_types.h" @@ -110,6 +110,9 @@ typedef struct vmiopd_SM_info { #define NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v15_02 8 #define NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v1F_0D 9 +#define NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_v21_02 32 +#define VM_UUID_SIZE_v21_02 16 + #define NV2080_CTRL_FB_FS_INFO_MAX_QUERIES_v1A_1D 96 #define NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE_v1A_1D 24 #define NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES_v1A_1D 96 @@ -118,6 +121,7 @@ typedef struct vmiopd_SM_info { #define NV0080_CTRL_GR_INFO_MAX_SIZE_1B_04 (0x0000002C) #define NV0080_CTRL_GR_INFO_MAX_SIZE_1C_01 (0x00000030) #define NV0080_CTRL_GR_INFO_MAX_SIZE_1E_02 (0x00000032) +#define NV0080_CTRL_GR_INFO_MAX_SIZE_21_01 (0x00000033) #define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04 8 #define NV2080_CTRL_INTERNAL_GR_MAX_SM_v1B_05 256 #define NV2080_CTRL_INTERNAL_GR_MAX_SM_v1E_03 240 @@ -126,8 +130,13 @@ typedef struct vmiopd_SM_info { #define NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT_v1C_03 10 #define NV2080_CTRL_INTERNAL_GR_MAX_GPC_v1C_03 12 #define NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX_v1E_09 32 -#define NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL_v1F_0E 100 +#define NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL_v1F_0E 72 #define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE_v20_04 6 +#define NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX_v21_07 50 +#define NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08 63 +#define NV2080_CTRL_MAX_PCES_v21_0A 32 +#define NV2080_CTRL_CE_CAPS_TBL_SIZE_v21_0A 2 +#define NV2080_ENGINE_TYPE_COPY_SIZE_v21_0A 10 // Defined this intermediate RM-RPC structure for making RPC call from Guest as // we have the restriction of passing max 4kb of data to plugin and the diff --git a/src/nvidia/kernel/inc/vgpu/vgpu_events.h b/src/nvidia/kernel/inc/vgpu/vgpu_events.h index a0975213b..2ba9cb04c 100644 --- a/src/nvidia/kernel/inc/vgpu/vgpu_events.h +++ b/src/nvidia/kernel/inc/vgpu/vgpu_events.h @@ -35,14 +35,11 @@ #include "rmconfig.h" -#include "ctrl/ctrla083.h" -#include "ctrl/ctrlc637.h" #include "ctrl/ctrl2080/ctrl2080bios.h" #include "ctrl/ctrl2080/ctrl2080fb.h" #include "ctrl/ctrl2080/ctrl2080gpu.h" #include "ctrl/ctrl2080/ctrl2080gr.h" #include "ctrl/ctrl0080/ctrl0080nvjpg.h" - #include "vgpu/rpc_headers.h" #include "gpu/device/device.h" @@ -51,7 +48,8 @@ #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" typedef MC_ENGINE_BITVECTOR *PMC_ENGINE_BITVECTOR; -typedef struct HOST_VGPU_DEVICE HOST_VGPU_DEVICE, KERNEL_HOST_VGPU_DEVICE; +typedef struct HOST_VGPU_DEVICE HOST_VGPU_DEVICE; +typedef struct KERNEL_HOST_VGPU_DEVICE KERNEL_HOST_VGPU_DEVICE; typedef struct _object_vgpu OBJVGPU, *POBJVGPU; // Create and destroy OBJVGPU *object @@ -70,36 +68,18 @@ void vgpuInitRegistryOverWrite(OBJGPU *pGpu); // Get the device pointer from the calling context Device *vgpuGetCallingContextDevice(OBJGPU *pGpu); -// Stubs for virtualization-disabled builds -static inline NV_STATUS vgpuGetCallingContextHostVgpuDevice(OBJGPU *pGpu, HOST_VGPU_DEVICE **ppHostVgpuDevice) -{ - *ppHostVgpuDevice = NULL; - return NV_OK; -} +// Get the host VGPU device pointer from the calling context +NV_STATUS vgpuGetCallingContextHostVgpuDevice(OBJGPU *pGpu, HOST_VGPU_DEVICE **ppHostVgpuDevice); +NV_STATUS vgpuGetCallingContextKernelHostVgpuDevice(OBJGPU *pGpu, KERNEL_HOST_VGPU_DEVICE **ppKernelHostVgpuDevice); -static inline NV_STATUS vgpuGetCallingContextKernelHostVgpuDevice(OBJGPU *pGpu, KERNEL_HOST_VGPU_DEVICE **ppKernelHostVgpuDevice) -{ - *ppKernelHostVgpuDevice = NULL; - return NV_OK; -} +// Get the GFID for from the VGPU device of the calling context +NV_STATUS vgpuGetCallingContextGfid(OBJGPU *pGpu, NvU32 *pGfid); -static inline NV_STATUS vgpuGetCallingContextGfid(OBJGPU *pGpu, NvU32 *pGfid) -{ - *pGfid = GPU_GFID_PF; - return NV_OK; -} +// Check is the calling context if VGPU plugin +NV_STATUS vgpuIsCallingContextPlugin(OBJGPU *pGpu, NvBool *pIsCallingContextPlugin); -static inline NV_STATUS vgpuIsCallingContextPlugin(OBJGPU *pGpu, NvBool *pIsCallingContextPlugin) -{ - *pIsCallingContextPlugin = NV_FALSE; - return NV_OK; -} - -static inline NV_STATUS vgpuGetGfidFromDeviceInfo(OBJGPU *pGpu, Device *pDevice, NvU32 *pGfid) -{ - *pGfid = GPU_GFID_PF; - return NV_OK; -} +// Get the GFID from DeviceInfo +NV_STATUS vgpuGetGfidFromDeviceInfo(OBJGPU *pGpu, Device *pDevice, NvU32 *pGfid); // Update Interrupt using shared memory through vGPU void vgpuUpdateShmIntr(OBJGPU *pGpu, NvU32 offset, NvU32 value, THREAD_STATE_NODE *pThreadState); diff --git a/src/nvidia/kernel/inc/vgpu/vgpu_version.h b/src/nvidia/kernel/inc/vgpu/vgpu_version.h index 3e25eaea4..3f87dab30 100644 --- a/src/nvidia/kernel/inc/vgpu/vgpu_version.h +++ b/src/nvidia/kernel/inc/vgpu/vgpu_version.h @@ -30,12 +30,77 @@ #define RPC_VERSION_FROM_VGX_VERSION(major, minor) ( DRF_NUM(_RPC, _VERSION_NUMBER, _MAJOR, major) | \ DRF_NUM(_RPC, _VERSION_NUMBER, _MINOR, minor)) -#define VGX_MAJOR_VERSION_NUMBER 0x20 -#define VGX_MINOR_VERSION_NUMBER 0x04 +#define VGX_MAJOR_VERSION_NUMBER 0x21 +#define VGX_MINOR_VERSION_NUMBER 0x0A + + +#define VGX_MAJOR_VERSION_NUMBER_VGPU_12_0 0x1A +#define VGX_MINOR_VERSION_NUMBER_VGPU_12_0 0x18 +#define VGX_MAJOR_VERSION_NUMBER_VGPU_13_0 0x1C +#define VGX_MINOR_VERSION_NUMBER_VGPU_13_0 0x0A + +/** + * This macro have the mapping between internal (RPC) and external version + * and is required to be updated appropriately with every new internal version. + * + * In case a new external version is added, a new entry representing the mapping + * for the external version should be appended. Please note that the external + * version should be updated when both of the following are true: + * 1. The new RPC version update cause a break in migration compatibility. + * 2. This is the first break in migration compatibility after a release. + */ +#define NV_VGPU_GRIDSW_INTERNAL_TO_EXTERNAL_VERSION_MAPPING \ + {{0x21, 0x0}, {0x21, 0x0A}, {0x10, 0x1}}, \ + {{0x20, 0x0}, {0x20, 0x04}, {0xF, 0x1}}, \ + {{0x1F, 0x0}, {0x1F, 0xF}, {0xE, 0x1}}, \ + {{0x1E, 0x0}, {0x1E, 0xE}, {0xD, 0x1}}, \ + {{0x1D, 0x0}, {0x1D, 0x6}, {0xC, 0x1}}, \ + {{0x1C, 0x0}, {0x1C, 0xA}, {0xB, 0x1}}, \ + {{0x1C, 0xB}, {0x1C, 0xC}, {0xB, 0x2}}, \ + {{0x1B, 0x0}, {0x1B, 0x5}, {0xA, 0x1}}, \ + {{0x1A, 0x0}, {0x1A, 0x18}, {0x9, 0x1}}, \ + {{0x1A, 0x19}, {0x1A, 0x24}, {0x9, 0x2}}, \ + {{0x19, 0x0}, {0x19, 0x1}, {0x8, 0x1}}, \ + {{0x18, 0x0}, {0x18, 0x14},{0x7, 0x1}}, \ + {{0x18, 0x15}, {0x18, 0x16},{0x7, 0x2}}, \ + {{0x17, 0x0}, {0x17, 0x6}, {0x6, 0x1}}, \ + {{0x16, 0x0}, {0x16, 0x6}, {0x5, 0x1}}, \ + {{0x16, 0x7}, {0x16, 0x7}, {0x5, 0x2}} + +/* + * Internal Versioning + */ + +#define NV_VGPU_GRIDSW_NUMBER_INTERNAL_MAJOR 63:32 +#define NV_VGPU_GRIDSW_NUMBER_INTERNAL_MINOR 31:0 + +#define GRIDSW_VERSION_INTERNAL(major, minor) (DRF_NUM64(_VGPU, _GRIDSW_NUMBER_INTERNAL, _MAJOR, major) | \ + DRF_NUM64(_VGPU, _GRIDSW_NUMBER_INTERNAL, _MINOR, minor)) + // The NV_VGPU_GRIDSW_VERSION_MIN_SUPPORTED_INTERNAL macros are auto-generated using the value from rpc-structures.def file. #define AUTOGENERATE_RPC_MIN_SUPPORTED_VERSION_INFORMATION #include "g_rpc-structures.h" #undef AUTOGENERATE_RPC_MIN_SUPPORTED_VERSION_INFORMATION +/* + * Versioning exposed externally + */ +#define NV_VGPU_GRIDSW_NUMBER_EXTERNAL_MAJOR 31:16 +#define NV_VGPU_GRIDSW_NUMBER_EXTERNAL_MINOR 15:0 + +#define GRIDSW_VERSION_EXTERNAL(major, minor) (DRF_NUM(_VGPU, _GRIDSW_NUMBER_EXTERNAL, _MAJOR, major) | \ + DRF_NUM(_VGPU, _GRIDSW_NUMBER_EXTERNAL, _MINOR, minor)) + +/* WARNING: Should be updated with each vGPU release, if there is a break in + * migration compatibility during the development of that release. */ +#define NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR 0x10 +#define NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MINOR 0x1 + +/* WARNING: Should be updated with each vGPU release, if minimum supported + * version change on the host. + */ +#define NV_VGPU_MIN_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR 0x7 +#define NV_VGPU_MIN_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MINOR 0x1 + #endif // __vgpu_vgpu_version_h__ diff --git a/src/nvidia/kernel/vgpu/nv/objvgpu.c b/src/nvidia/kernel/vgpu/nv/objvgpu.c new file mode 100644 index 000000000..b4c44f5d1 --- /dev/null +++ b/src/nvidia/kernel/vgpu/nv/objvgpu.c @@ -0,0 +1,344 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "core/core.h" +#include "os/os.h" +#include "gpu/gpu.h" +#include "vgpu/vgpu_version.h" +#include "gpu/device/device.h" +#include "rmapi/rs_utils.h" +#include "virtualization/hypervisor/hypervisor.h" +#include "virtualization/kernel_vgpu_mgr.h" + +#include "nvRmReg.h" + +// Create vGpu object and initialize RPC infrastructure +NV_STATUS +vgpuCreateObject +( + OBJGPU *pGpu +) +{ + NV_STATUS rmStatus = NV_OK; + return rmStatus; +} + +// Free RPC infrastructure and vGpu object +void +vgpuDestructObject +( + OBJGPU *pGpu +) +{ +} + +// Overwrite registry keys +void +vgpuInitRegistryOverWrite +( + OBJGPU *pGpu +) +{ + NvU32 data; + + // if "RMFermiBigPageSize" regkey is set explicitly, then don't + // overwrite it. + if (NV_OK != osReadRegistryDword(pGpu, + NV_REG_STR_RM_DISABLE_BIG_PAGE_PER_ADDRESS_SPACE, + &data)) + { + NV_PRINTF(LEVEL_INFO, "Overwriting big page size to 64K\n"); + + osWriteRegistryDword(pGpu, + NV_REG_STR_FERMI_BIG_PAGE_SIZE, + NV_REG_STR_FERMI_BIG_PAGE_SIZE_64KB); + if (IS_VIRTUAL(pGpu)) + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_VGPU_BIG_PAGE_SIZE_64K, NV_TRUE); + } + } + + NvU32 min = 0, max = 0; + + /* Default user provided vGPU supported range is set to be the + * same as per the host */ + NvU32 user_min_supported_version + = GRIDSW_VERSION_EXTERNAL(NV_VGPU_MIN_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR, + NV_VGPU_MIN_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MINOR); + NvU32 user_max_supported_version + = GRIDSW_VERSION_EXTERNAL(NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR, + NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MINOR); + + if (NV_OK == osReadRegistryDword(pGpu, + NV_REG_STR_RM_SET_VGPU_VERSION_MAX, + &max)) + { + /* Override max vGPU supported version */ + user_max_supported_version = max; + } + + if (NV_OK == osReadRegistryDword(pGpu, + NV_REG_STR_RM_SET_VGPU_VERSION_MIN, + &min)) + { + /* Override min vGPU supported version */ + user_min_supported_version = min; + } + + /* Convey the vGPU range information to the vGPU manager */ + kvgpumgrSetHostVgpuVersion(user_min_supported_version, user_max_supported_version); +} + +/* + * @brief Gets the calling context's device pointer + * + * @param pGpu OBJGPU pointer + * + * @return Pointer to the calling context's device pointer + */ +Device * +vgpuGetCallingContextDevice +( + OBJGPU *pGpu +) +{ + RsResourceRef *pDeviceRef = NULL; + Device *pDevice = NULL; + + pDeviceRef = resservGetContextRefByType(classId(Device), NV_TRUE); + if (pDeviceRef != NULL) + { + pDevice = dynamicCast(pDeviceRef->pResource, Device); + } + + return pDevice; +} + +/* + * @brief Gets the calling context's Host VGPU device pointer + * + * @param pGpu OBJGPU pointer + * @param ppHostVgpuDevice Pointer to pointer to the calling + * context's Host VGPU device pointer + * + * @return Error code + */ +NV_STATUS +vgpuGetCallingContextHostVgpuDevice +( + OBJGPU *pGpu, + HOST_VGPU_DEVICE **ppHostVgpuDevice +) +{ + *ppHostVgpuDevice = NULL; + + if (IS_GSP_CLIENT(pGpu)) + return NV_ERR_NOT_SUPPORTED; + + return NV_OK; +} + +NV_STATUS +vgpuGetCallingContextKernelHostVgpuDevice +( + OBJGPU *pGpu, + KERNEL_HOST_VGPU_DEVICE **ppKernelHostVgpuDevice +) +{ + Device *pDevice; + + if (RMCFG_FEATURE_PLATFORM_GSP) + return NV_ERR_NOT_SUPPORTED; + + *ppKernelHostVgpuDevice = NULL; + + // This check is needed to handle cases where this function was called + // without client (for example, during adapter initialization). + if (resservGetTlsCallContext() == NULL) + { + return NV_OK; + } + + pDevice = vgpuGetCallingContextDevice(pGpu); + if (pDevice == NULL) + { + // There are several places where this function can be called without TLS call context + // in SRIOV-heavy mode. Return error only for SRIOV-full. + NV_ASSERT_OR_RETURN(!gpuIsSriovEnabled(pGpu) || IS_SRIOV_HEAVY(pGpu), NV_ERR_OBJECT_NOT_FOUND); + return NV_OK; + } + + *ppKernelHostVgpuDevice = pDevice->pKernelHostVgpuDevice; + + NV_ASSERT_OR_RETURN((pDevice->pKernelHostVgpuDevice != NULL) == + !!(pDevice->deviceAllocFlags & NV_DEVICE_ALLOCATION_FLAGS_HOST_VGPU_DEVICE), + NV_ERR_INVALID_STATE); + + return NV_OK; +} + +/* + * @brief Gets the calling context's GFID + * gsp-rm: when the vgpu plugin rpcs to gsp-rm, gfid is stored in an unused + * field, pProcessToken. + * cpu-rm: Retrieve from TLS a host vgpu device, and then gfid from it. + * + * @param pGpu OBJGPU pointer + * @param pGfid calling context's GFID pointer + * + * @return Error code + */ +NV_STATUS +vgpuGetCallingContextGfid +( + OBJGPU *pGpu, + NvU32 *pGfid +) +{ + GFID_ALLOC_STATUS gfidState; + + *pGfid = GPU_GFID_PF; + + if (!gpuIsSriovEnabled(pGpu)) + { + return NV_OK; + } + + if (RMCFG_FEATURE_PLATFORM_GSP) + { + CALL_CONTEXT *pTls = resservGetTlsCallContext(); + + if (pTls) + { + *pGfid = (NvU32)(NvU64)pTls->secInfo.pProcessToken; + } + } + else + { + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice; + + NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextKernelHostVgpuDevice(pGpu, &pKernelHostVgpuDevice)); + if (pKernelHostVgpuDevice != NULL) + { + *pGfid = pKernelHostVgpuDevice->gfid; + } + } + + // work around for bug 3432243 where this is called before setting gfid. + if (IS_GFID_PF(*pGfid)) + return NV_OK; + + NV_ASSERT_OK_OR_RETURN(gpuGetGfidState(pGpu, *pGfid, &gfidState)); + + // Allow invalidated state to be retreived as GFID is still active in system + NV_ASSERT_OR_RETURN((gfidState != GFID_FREE), NV_ERR_INVALID_STATE); + + return NV_OK; +} + +NV_STATUS +vgpuGetGfidFromDeviceInfo +( + OBJGPU *pGpu, + Device *pDevice, + NvU32 *pGfid +) +{ + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice; + + if (RMCFG_FEATURE_PLATFORM_GSP) + return NV_ERR_NOT_SUPPORTED; + + + *pGfid = GPU_GFID_PF; + + NV_ASSERT_OR_RETURN(pDevice != NULL, NV_ERR_INVALID_ARGUMENT); + + if (!gpuIsSriovEnabled(pGpu)) + { + return NV_OK; + } + + // TODO: fix the calling sites in VAB and P2P (GPUSWSEC-783) + NV_ASSERT_OR_RETURN(!RMCFG_FEATURE_PLATFORM_GSP, NV_ERR_NOT_SUPPORTED); + + // Get the HOST_VGPU_DEVICE from hClient + pKernelHostVgpuDevice = pDevice->pKernelHostVgpuDevice; + + NV_ASSERT_OR_RETURN((pKernelHostVgpuDevice != NULL) == + !!(pDevice->deviceAllocFlags & NV_DEVICE_ALLOCATION_FLAGS_HOST_VGPU_DEVICE), + NV_ERR_INVALID_STATE); + + if (pKernelHostVgpuDevice != NULL) + { + GFID_ALLOC_STATUS gfidState; + *pGfid = pKernelHostVgpuDevice->gfid; + NV_ASSERT_OK_OR_RETURN(gpuGetGfidState(pGpu, *pGfid, &gfidState)); + NV_ASSERT_OR_RETURN((gfidState != GFID_FREE), NV_ERR_INSUFFICIENT_RESOURCES); + } + + return NV_OK; +} + +NV_STATUS +vgpuIsCallingContextPlugin +( + OBJGPU *pGpu, + NvBool *pIsCallingContextPlugin +) +{ + Device *pDevice = NULL; + + *pIsCallingContextPlugin = NV_FALSE; + + if (!gpuIsSriovEnabled(pGpu)) + { + return NV_OK; + } + + // This check is needed to handle cases where this function was called + // without client (for example, during adapter initialization). + if (resservGetTlsCallContext() == NULL) + { + return NV_OK; + } + + pDevice = vgpuGetCallingContextDevice(pGpu); + if (pDevice == NULL) + { + // There are several places where this function can be called without TLS call context + // in SRIOV-heavy mode. Return error only for SRIOV-full. + NV_ASSERT_OR_RETURN(!gpuIsSriovEnabled(pGpu) || IS_SRIOV_HEAVY(pGpu), NV_ERR_OBJECT_NOT_FOUND); + return NV_OK; + } + + if (pDevice->deviceAllocFlags & NV_DEVICE_ALLOCATION_FLAGS_PLUGIN_CONTEXT) + { + if (!RMCFG_FEATURE_PLATFORM_GSP) + NV_ASSERT_OR_RETURN(pDevice->pKernelHostVgpuDevice, NV_ERR_INVALID_STATE); + + *pIsCallingContextPlugin = NV_TRUE; + } + + return NV_OK; +} diff --git a/src/nvidia/kernel/vgpu/nv/rpc.c b/src/nvidia/kernel/vgpu/nv/rpc.c index e53e4e646..7086c8f51 100644 --- a/src/nvidia/kernel/vgpu/nv/rpc.c +++ b/src/nvidia/kernel/vgpu/nv/rpc.c @@ -42,6 +42,7 @@ #include "resserv/rs_server.h" #include "rmapi/alloc_size.h" #include "rmapi/rs_utils.h" +#include "rmapi/rmapi_utils.h" #include "rmapi/client_resource.h" #include "gpu/gsp/kernel_gsp.h" #include "gpu/mem_mgr/mem_mgr.h" @@ -270,9 +271,9 @@ static NV_STATUS _issueRpcLarge // // Copy the initial buffer - // Temporary black magic WAR for bug 3594082: reducing the size by 1 + // Temporary black magic WAR for bug 3594082: reducing the size by 2 // - entryLength = NV_MIN(bufSize, pRpc->maxRpcSize - 1); + entryLength = NV_MIN(bufSize, pRpc->maxRpcSize - 2); if ((NvU8 *)vgpu_rpc_message_header_v != pBuf8) portMemCopy(vgpu_rpc_message_header_v, entryLength, pBuf8, entryLength); @@ -299,9 +300,9 @@ static NV_STATUS _issueRpcLarge // // Copy the remaining buffers - // Temporary black magic WAR for bug 3594082: reducing the size by 1 + // Temporary black magic WAR for bug 3594082: reducing the size by 2 // - entryLength = pRpc->maxRpcSize - sizeof(rpc_message_header_v) - 1; + entryLength = pRpc->maxRpcSize - sizeof(rpc_message_header_v) - 2; while (remainingSize != 0) { if (entryLength > remainingSize) @@ -651,14 +652,22 @@ NV_STATUS RmRpcSetGuestSystemInfo(OBJGPU *pGpu, OBJRPC *pRpc) NvS32 message_buffer_remaining; NvU32 data_len; + if (pGpuMgr->numGpuHandles == 0) + { + rpcVgxVersion.majorNum = 0; + rpcVgxVersion.minorNum = 0; + } + // // Skip RPC version handshake if we've already done it on one GPU. // // For GSP: Multi GPU setup can have pre-Turing GPUs // and GSP offload is disabled for all pre-Turing GPUs. - // Don't skip RPC version handshake if rpcVgxVersion.majorNum is not set + // Don't skip RPC version handshake for GSP_CLIENT or if VGPU-GSP plugin offload is enabled. + // There are different GSPs/plugins for different GPUs and we need to have a handshake with all of them. // - if (pGpuMgr->numGpuHandles > 1) + + if (pGpuMgr->numGpuHandles > 1 && !IS_GSP_CLIENT(pGpu) && !(IS_VIRTUAL(pGpu) && IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu))) { if (rpcVgxVersion.majorNum != 0) { @@ -667,7 +676,7 @@ NV_STATUS RmRpcSetGuestSystemInfo(OBJGPU *pGpu, OBJRPC *pRpc) gpuGetInstance(pGpu)); goto skip_ver_handshake; } - else if (!IS_GSP_CLIENT(pGpu)) + else { status = NV_ERR_GENERIC; NV_PRINTF(LEVEL_ERROR, @@ -677,9 +686,6 @@ NV_STATUS RmRpcSetGuestSystemInfo(OBJGPU *pGpu, OBJRPC *pRpc) } } - rpcVgxVersion.majorNum = 0; - rpcVgxVersion.minorNum = 0; - message_buffer_remaining = pRpc->maxRpcSize - (sizeof(rpc_message_header_v) + sizeof(rpc_set_guest_system_info_v)); @@ -783,6 +789,15 @@ NV_STATUS RmRpcSetGuestSystemInfo(OBJGPU *pGpu, OBJRPC *pRpc) if (status == NV_OK) { + if (rpcVgxVersion.majorNum != 0) + { + if (rpcVgxVersion.majorNum != rpc_message->set_guest_system_info_v.vgxVersionMajorNum || + rpcVgxVersion.minorNum != rpc_message->set_guest_system_info_v.vgxVersionMinorNum) + { + return NV_ERR_INVALID_STATE; + } + } + rpcVgxVersion.majorNum = rpc_message->set_guest_system_info_v.vgxVersionMajorNum; rpcVgxVersion.minorNum = rpc_message->set_guest_system_info_v.vgxVersionMinorNum; } @@ -1005,12 +1020,6 @@ NV_STATUS rpcGetStaticInfo_v20_01(OBJGPU *pGpu, OBJRPC *pRpc) return status; } -NV_STATUS rpcGetStaticInfo_v20_04(OBJGPU *pGpu, OBJRPC *pRpc) -{ - NV_STATUS status = NV_OK; - return status; -} - NV_STATUS rpcGetGspStaticInfo_v14_00(OBJGPU *pGpu, OBJRPC *pRpc) { NV_STATUS status = NV_ERR_NOT_SUPPORTED; @@ -1283,6 +1292,18 @@ NV_STATUS rpcGspSetSystemInfo_v17_00 { clSyncWithGsp(pCl, rpcInfo); } + + // Fill in the cached ACPI method data + rpcInfo->acpiMethodData = pGpu->acpiMethodData; + + // Fill in ASPM related GPU flags + rpcInfo->bGpuBehindBridge = pGpu->getProperty(pGpu, PDB_PROP_GPU_BEHIND_BRIDGE); + rpcInfo->bUpstreamL0sUnsupported = pGpu->getProperty(pGpu, PDB_PROP_GPU_UPSTREAM_PORT_L0S_UNSUPPORTED); + rpcInfo->bUpstreamL1Unsupported = pGpu->getProperty(pGpu, PDB_PROP_GPU_UPSTREAM_PORT_L1_UNSUPPORTED); + rpcInfo->bUpstreamL1PorSupported = pGpu->getProperty(pGpu, PDB_PROP_GPU_UPSTREAM_PORT_L1_POR_SUPPORTED); + rpcInfo->bUpstreamL1PorMobileOnly = pGpu->getProperty(pGpu, PDB_PROP_GPU_UPSTREAM_PORT_L1_POR_MOBILE_ONLY); + rpcInfo->upstreamAddressValid = pGpu->gpuClData.upstreamPort.addr.valid; + status = _issueRpcAsync(pGpu, pRpc); } @@ -1502,6 +1523,9 @@ NV_STATUS rpcRmApiControl_GSP NvU32 serializedSize = 0; NvU32 origParamsSize = paramsSize; NvU32 gpuMaskRelease = 0; + NvU32 ctrlFlags = 0; + NvU32 ctrlAccessRight = 0; + NvBool bCacheable; if (!rmDeviceGpuLockIsOwner(pGpu->gpuInstance)) { @@ -1513,6 +1537,9 @@ NV_STATUS rpcRmApiControl_GSP GPU_LOCK_FLAGS_SAFE_LOCK_UPGRADE, RM_LOCK_MODULES_RPC, &gpuMaskRelease)); } + rmapiutilGetControlInfo(cmd, &ctrlFlags, &ctrlAccessRight); + bCacheable = rmapiControlIsCacheable(ctrlFlags, ctrlAccessRight, NV_TRUE); + // Attempt to calculate the serialized size of the param struct using FINN. serializedSize = FinnRmApiGetSerializedSize(interface_id, message_id, pParamStructPtr); @@ -1522,6 +1549,14 @@ NV_STATUS rpcRmApiControl_GSP { // Allocate twice the amount to account for the return buffer paramsSize = 2 * serializedSize; + NV_ASSERT_OR_RETURN(!bCacheable, NV_ERR_INVALID_STATE); + } + + if (bCacheable) + { + status = rmapiControlCacheGet(hClient, hObject, cmd, pParamStructPtr, paramsSize); + if (status == NV_OK) + goto done; } // Initialize these values now that paramsSize is known @@ -1534,10 +1569,11 @@ NV_STATUS rpcRmApiControl_GSP rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_GSP_RM_CONTROL, rpc_params_size), done); - rpc_params->hClient = hClient; - rpc_params->hObject = hObject; - rpc_params->cmd = cmd; - rpc_params->paramsSize = paramsSize; + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + rpc_params->cmd = cmd; + rpc_params->paramsSize = paramsSize; + rpc_params->copyOutOnError = !!(ctrlFlags & RMCTRL_FLAGS_COPYOUT_ON_ERROR); // If we have a big payload control, we need to make a local copy... if (message_buffer_remaining < paramsSize) @@ -1619,8 +1655,20 @@ NV_STATUS rpcRmApiControl_GSP status = _issueRpcAndWait(pGpu, pRpc); } + // + // At this point we have: + // status: The status of the RPC transfer. If NV_OK, we got something back + // rpc_params->status: Status returned by the actual ctrl handler on GSP + // if (status == NV_OK) { + // Skip copyout if we got an error from the GSP control handler + if (rpc_params->status != NV_OK && !rpc_params->copyOutOnError) + { + status = rpc_params->status; + goto done; + } + // If FINN was used to serialize the params, they must be deserialized on the way back, // otherwise do a flat memcpy if (serializedSize != 0) @@ -1649,13 +1697,24 @@ NV_STATUS rpcRmApiControl_GSP if (rpc_params->status != NV_OK) status = rpc_params->status; + else if (bCacheable) + NV_ASSERT_OK(rmapiControlCacheSet(hClient, hObject, cmd, rpc_params->params, paramsSize)); } if (status != NV_OK) { - NV_PRINTF(LEVEL_WARNING, - "GspRmControl failed: hClient=0x%08x; hObject=0x%08x; cmd=0x%08x; paramsSize=0x%08x; paramsStatus=0x%08x; status=0x%08x\n", - hClient, hObject, cmd, paramsSize, rpc_params->status, status); + NvBool bSilentErrorReport = NV_FALSE; + switch (status) + { + case NV_ERR_NOT_SUPPORTED: + case NV_ERR_OBJECT_NOT_FOUND: + bSilentErrorReport = NV_TRUE; + break; + } + + NV_PRINTF_COND(bSilentErrorReport, LEVEL_INFO, LEVEL_WARNING, + "GspRmControl failed: hClient=0x%08x; hObject=0x%08x; cmd=0x%08x; paramsSize=0x%08x; paramsStatus=0x%08x; status=0x%08x\n", + hClient, hObject, cmd, paramsSize, rpc_params->status, status); } done: diff --git a/src/nvidia/src/kernel/compute/fabric.c b/src/nvidia/src/kernel/compute/fabric.c index 5e38729be..be7aae7ab 100644 --- a/src/nvidia/src/kernel/compute/fabric.c +++ b/src/nvidia/src/kernel/compute/fabric.c @@ -29,6 +29,209 @@ #include "os/os.h" #include "compute/fabric.h" +static NV_STATUS +_fabricCacheInsert +( + FabricCache *pCache, + NvU64 key1, + NvU64 key2, + NvU64 key3, + void *pData +) +{ + FabricCacheSubmap *pInsertedSubmap = NULL; + FabricCacheEntry *pInsertedEntry = NULL; + FabricCacheEntry *pEntry; + FabricCacheMapEntry *pMapEntry; + + pEntry = multimapFindItem(pCache, key1, key2); + if (pEntry != NULL) + goto insert; + + if (multimapFindSubmap(pCache, key1) == NULL) + { + pInsertedSubmap = multimapInsertSubmap(pCache, key1); + if (pInsertedSubmap == NULL) + goto fail; + } + + pInsertedEntry = multimapInsertItemNew(pCache, key1, key2); + if (pInsertedEntry == NULL) + goto fail; + + mapInit(&pInsertedEntry->map, portMemAllocatorGetGlobalNonPaged()); + pEntry = pInsertedEntry; + +insert: + pMapEntry = mapInsertNew(&pEntry->map, key3); + if (pMapEntry == NULL) + goto fail; + + pMapEntry->pData = pData; + + return NV_OK; + +fail: + if (pInsertedEntry != NULL) + { + mapDestroy(&pInsertedEntry->map); + multimapRemoveItem(pCache, pInsertedEntry); + } + + if (pInsertedSubmap != NULL) + multimapRemoveSubmap(pCache, pInsertedSubmap); + + return NV_ERR_INVALID_STATE; +} + +static void +_fabricCacheDelete +( + FabricCache *pCache, + NvU64 key1, + NvU64 key2, + NvU64 key3 +) +{ + FabricCacheSubmap *pSubmap; + FabricCacheEntry *pEntry; + + pEntry = multimapFindItem(pCache, key1, key2); + NV_ASSERT_OR_RETURN_VOID(pEntry != NULL); + + mapRemoveByKey(&pEntry->map, key3); + if (mapCount(&pEntry->map) > 0) + return; + + mapDestroy(&pEntry->map); + multimapRemoveItem(pCache, pEntry); + + pSubmap = multimapFindSubmap(pCache, key1); + NV_ASSERT_OR_RETURN_VOID(pSubmap != NULL); + + if (multimapCountSubmapItems(pCache, pSubmap) > 0) + return; + + multimapRemoveSubmap(pCache, pSubmap); +} + +static FabricCacheMapEntry* +_fabricCacheFind +( + FabricCache *pCache, + NvU64 key1, + NvU64 key2, + NvU64 key3 +) +{ + FabricCacheEntry *pEntry; + FabricCacheMapEntry *pMapEntry; + + pEntry = multimapFindItem(pCache, key1, key2); + if (pEntry == NULL) + return NULL; + + pMapEntry = mapFind(&pEntry->map, key3); + if (pMapEntry == NULL) + return NULL; + + return pMapEntry; +} + +void +fabricMulticastFabricOpsMutexAcquire_IMPL +( + Fabric *pFabric +) +{ + portSyncMutexAcquire(pFabric->pMulticastFabricOpsMutex); +} + +void +fabricMulticastFabricOpsMutexRelease_IMPL +( + Fabric *pFabric +) +{ + portSyncMutexRelease(pFabric->pMulticastFabricOpsMutex); +} + +NV_STATUS +fabricMulticastSetupCacheInsertUnderLock_IMPL +( + Fabric *pFabric, + NvU64 requestId, + void *pData +) +{ + return _fabricCacheInsert(&pFabric->fabricMulticastCache, + 0, requestId, 0, pData); +} + +void +fabricMulticastSetupCacheDeleteUnderLock_IMPL +( + Fabric *pFabric, + NvU64 requestId +) +{ + _fabricCacheDelete(&pFabric->fabricMulticastCache, + 0, requestId, 0); +} + +void* +fabricMulticastSetupCacheGetUnderLock_IMPL +( + Fabric *pFabric, + NvU64 requestId +) +{ + FabricCacheMapEntry *pMapEntry; + + pMapEntry = _fabricCacheFind(&pFabric->fabricMulticastCache, + 0, requestId, 0); + + return (pMapEntry == NULL ? NULL : pMapEntry->pData); +} + +NV_STATUS +fabricMulticastCleanupCacheInsertUnderLock_IMPL +( + Fabric *pFabric, + NvU64 requestId, + void *pData +) +{ + return _fabricCacheInsert(&pFabric->fabricMulticastCache, + 1, requestId, 0, pData); +} + +void +fabricMulticastCleanupCacheDeleteUnderLock_IMPL +( + Fabric *pFabric, + NvU64 requestId +) +{ + _fabricCacheDelete(&pFabric->fabricMulticastCache, + 1, requestId, 0); +} + +void* +fabricMulticastCleanupCacheGetUnderLock_IMPL +( + Fabric *pFabric, + NvU64 requestId +) +{ + FabricCacheMapEntry *pMapEntry; + + pMapEntry = _fabricCacheFind(&pFabric->fabricMulticastCache, + 1, requestId, 0); + + return (pMapEntry == NULL ? NULL : pMapEntry->pData); +} + void fabricSetFmSessionFlags_IMPL ( @@ -54,7 +257,24 @@ fabricConstruct_IMPL Fabric *pFabric ) { + NV_STATUS status = NV_OK; + + pFabric->pMulticastFabricOpsMutex = portSyncMutexCreate(portMemAllocatorGetGlobalNonPaged()); + if (pFabric->pMulticastFabricOpsMutex == NULL) + { + status = NV_ERR_NO_MEMORY; + goto fail; + } + + multimapInit(&pFabric->fabricMulticastCache, portMemAllocatorGetGlobalNonPaged()); + return NV_OK; + +//TODO: Remove the WAR to suppress unused label warning +goto fail; +fail: + fabricDestruct_IMPL(pFabric); + return status; } void @@ -63,4 +283,68 @@ fabricDestruct_IMPL Fabric *pFabric ) { + NV_ASSERT(multimapCountItems(&pFabric->fabricMulticastCache) == 0); + + multimapDestroy(&pFabric->fabricMulticastCache); + + if (pFabric->pMulticastFabricOpsMutex != NULL) + portSyncMutexDestroy(pFabric->pMulticastFabricOpsMutex); + +} + +NV_STATUS +fabricInitInbandMsgHdr +( + nvlink_inband_msg_header_t *pMsgHdr, + NvU32 type, + NvU32 len +) +{ + NV_STATUS status; + + portMemSet(pMsgHdr, 0, sizeof(*pMsgHdr)); + + status = osGetRandomBytes((NvU8 *)&pMsgHdr->requestId, + sizeof(pMsgHdr->requestId)); + if (status != NV_OK) + { + return status; + } + + pMsgHdr->magicId = NVLINK_INBAND_MSG_MAGIC_ID_FM; + pMsgHdr->type = type; + pMsgHdr->length = len; + + return NV_OK; +} + +void +fabricMulticastWaitOnTeamCleanupCallback +( + void *pCbData +) +{ + NvU64 inbandReqId = (NvU64)pCbData; + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + OS_WAIT_QUEUE *pWq; + + fabricMulticastFabricOpsMutexAcquire(pFabric); + + pWq = (OS_WAIT_QUEUE *)fabricMulticastCleanupCacheGetUnderLock_IMPL(pFabric, + inbandReqId); + fabricMulticastFabricOpsMutexRelease(pFabric); + + if (pWq == NULL) + return; + + osWaitInterruptible(pWq); + + fabricMulticastFabricOpsMutexAcquire(pFabric); + + fabricMulticastCleanupCacheDeleteUnderLock_IMPL(pFabric, + inbandReqId); + + fabricMulticastFabricOpsMutexRelease(pFabric); + + osFreeWaitQueue(pWq); } diff --git a/src/nvidia/src/kernel/core/hal/hals_all.c b/src/nvidia/src/kernel/core/hal/hals_all.c index 10feb000f..c15dc6735 100644 --- a/src/nvidia/src/kernel/core/hal/hals_all.c +++ b/src/nvidia/src/kernel/core/hal/hals_all.c @@ -21,7 +21,7 @@ * DEALINGS IN THE SOFTWARE. */ -/***************************** HW State Rotuines ***************************\ +/***************************** HW State Routines ***************************\ * * * Module: hals_all.c * * Hal interface init routines for files generated by rmconfig * diff --git a/src/nvidia/src/kernel/core/locks.c b/src/nvidia/src/kernel/core/locks.c index 669726446..626127445 100644 --- a/src/nvidia/src/kernel/core/locks.c +++ b/src/nvidia/src/kernel/core/locks.c @@ -188,7 +188,7 @@ rmGpuLockAlloc(NvU32 gpuInst) NV_ERR_INVALID_STATE); // TODO: RM-1492 MODS does not hold API lock when allocating GPUs. - NV_ASSERT(rmApiLockIsOwner()); + NV_ASSERT(rmapiLockIsOwner()); // allocate intr mask lock status = rmIntrMaskLockAlloc(gpuInst); @@ -294,7 +294,7 @@ rmGpuLockFree(NvU32 gpuInst) // validate gpuInst argument NV_ASSERT_OR_RETURN_VOID((gpuInst < NV_MAX_DEVICES)); // TODO: RM-1492 MODS does not hold API lock when allocating GPUs. - NV_ASSERT(rmApiLockIsOwner()); + NV_ASSERT(rmapiLockIsOwner()); pGpuLock = &rmGpuLockInfo.gpuLocks[gpuInst]; @@ -409,12 +409,20 @@ static void _gpuLocksAcquireDisableInterrupts(NvU32 gpuInst, NvU32 flags) if (osLockShouldToggleInterrupts(pGpu)) { Intr *pIntr = GPU_GET_INTR(pGpu); - NvBool isIsr = !!(flags & GPUS_LOCK_FLAGS_COND_ACQUIRE); + NvBool isIsr = !!(flags & GPU_LOCK_FLAGS_COND_ACQUIRE); NvBool bBcEnabled = gpumgrGetBcEnabledStatus(pGpu); // Always disable intrs for cond code gpumgrSetBcEnabledStatus(pGpu, NV_FALSE); + // Note: SWRL is enabled only for vGPU, and is disabled otherwise. + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_SWRL_GRANULAR_LOCKING)) + { + // Disable the RM callback timer interrupt + OBJTMR *pTmr = GPU_GET_TIMER(pGpu); + tmrRmCallbackIntrDisable(pTmr, pGpu); + } + osDisableInterrupts(pGpu, isIsr); if ((pIntr != NULL) && pIntr->getProperty(pIntr, PDB_PROP_INTR_USE_INTR_MASK_FOR_LOCKING) && @@ -477,7 +485,7 @@ _rmGpuLocksAcquire(NvU32 gpuMask, NvU32 flags, NvU32 module, void *ra, NvU32 *pG NvBool bLockAll = NV_FALSE; bHighIrql = (portSyncExSafeToSleep() == NV_FALSE); - bCondAcquireCheck = ((flags & GPUS_LOCK_FLAGS_COND_ACQUIRE) != 0); + bCondAcquireCheck = ((flags & GPU_LOCK_FLAGS_COND_ACQUIRE) != 0); if (pGpuLockedMask) *pGpuLockedMask = 0; @@ -894,8 +902,11 @@ rmGpuGroupLockAcquire { GPU_MASK deviceGpuMask = 0; rmGpuGroupLockGetMask(gpuInst, GPU_LOCK_GRP_DEVICE, &deviceGpuMask); + // // Verify that we actually locked *this* device, not all others. - if ((*pGpuMask & deviceGpuMask) != deviceGpuMask) + // Check *held* locks not *acquired* locks in case of SAFE_LOCK_UPGRADE. + // + if ((rmGpuLocksGetOwnedMask() & deviceGpuMask) != deviceGpuMask) { // // On Windows, at high IRQL we can't signal the semaphore. So we @@ -1119,6 +1130,22 @@ static void _gpuLocksReleaseEnableInterrupts(NvU32 gpuInst, NvU32 flags) } osEnableInterrupts(pGpu); + // Note: SWRL is enabled only for vGPU, and is disabled otherwise. + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_SWRL_GRANULAR_LOCKING)) + { + // Enable the alarm interrupt. Rearm MSI when timer interrupt is pending. + OBJTMR *pTmr = GPU_GET_TIMER(pGpu); + NvU32 retVal; + + tmrRmCallbackIntrEnable(pTmr, pGpu); + tmrGetIntrStatus_HAL(pGpu, pTmr, &retVal, NULL); + if (retVal != 0) + { + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + kbifCheckAndRearmMSI(pGpu, pKernelBif); + } + } + gpumgrSetBcEnabledStatus(pGpu, bBcEnabled); } } diff --git a/src/nvidia/src/kernel/core/locks_common.c b/src/nvidia/src/kernel/core/locks_common.c index 0f84bfe51..584075b39 100644 --- a/src/nvidia/src/kernel/core/locks_common.c +++ b/src/nvidia/src/kernel/core/locks_common.c @@ -91,7 +91,7 @@ rmLocksAcquireAll(NvU32 module) return NV_ERR_INVALID_LOCK_STATE; } - if (rmApiLockAcquire(API_LOCK_FLAGS_NONE, module) != NV_OK) + if (rmapiLockAcquire(API_LOCK_FLAGS_NONE, module) != NV_OK) { NV_PRINTF(LEVEL_ERROR, "Failed to acquire the API lock!\n"); osReleaseRmSema(pSys->pSema, NULL); @@ -101,7 +101,7 @@ rmLocksAcquireAll(NvU32 module) if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, module) != NV_OK) { NV_PRINTF(LEVEL_ERROR, "Failed to acquire the GPU lock!\n"); - rmApiLockRelease(); + rmapiLockRelease(); osReleaseRmSema(pSys->pSema, NULL); return NV_ERR_INVALID_LOCK_STATE; } @@ -118,7 +118,7 @@ rmLocksReleaseAll(void) OBJSYS *pSys = SYS_GET_INSTANCE(); rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); - rmApiLockRelease(); + rmapiLockRelease(); osReleaseRmSema(pSys->pSema, NULL); } @@ -155,7 +155,7 @@ workItemLocksAcquire(NvU32 gpuInstance, NvU32 flags, NvU32 *pReleaseLocks, NvU32 releaseFlags = OS_QUEUE_WORKITEM_FLAGS_LOCK_API_RO; } - status = rmApiLockAcquire(apiLockFlags, RM_LOCK_MODULES_WORKITEM); + status = rmapiLockAcquire(apiLockFlags, RM_LOCK_MODULES_WORKITEM); if (status != NV_OK) goto done; @@ -256,7 +256,7 @@ workItemLocksRelease(NvU32 releaseLocks, NvU32 gpuMask) if ((releaseLocks & OS_QUEUE_WORKITEM_FLAGS_LOCK_API_RW) || (releaseLocks & OS_QUEUE_WORKITEM_FLAGS_LOCK_API_RO)) { - rmApiLockRelease(); + rmapiLockRelease(); } if (releaseLocks & OS_QUEUE_WORKITEM_FLAGS_LOCK_SEMA) diff --git a/src/nvidia/src/kernel/core/system.c b/src/nvidia/src/kernel/core/system.c index bb86402c7..5b94bb0b2 100644 --- a/src/nvidia/src/kernel/core/system.c +++ b/src/nvidia/src/kernel/core/system.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,7 +21,7 @@ * DEALINGS IN THE SOFTWARE. */ -/***************************** HW State Rotuines ***************************\ +/***************************** HW State Routines ***************************\ * * * System Object Function Definitions. * * * @@ -47,8 +47,11 @@ #include "platform/cpu.h" #include "platform/platform.h" #include "diagnostics/gpu_acct.h" +#include "gpu/external_device/gsync.h" +#include "virtualization/kernel_vgpu_mgr.h" #include "mem_mgr/virt_mem_mgr.h" #include "diagnostics/journal.h" +#include "virtualization/hypervisor/hypervisor.h" #include "power/gpu_boost_mgr.h" #include "compute/fabric.h" #include "gpu_mgr/gpu_db.h" @@ -74,12 +77,15 @@ static sysChildObject sysChildObjects[] = { { NV_OFFSETOF(OBJSYS, pHalMgr), classInfo(OBJHALMGR), NV_TRUE }, { NV_OFFSETOF(OBJSYS, pPfm), classInfo(OBJPFM), NV_TRUE }, + { NV_OFFSETOF(OBJSYS, pHypervisor), classInfo(OBJHYPERVISOR), NV_TRUE }, { NV_OFFSETOF(OBJSYS, pOS), classInfo(OBJOS), NV_FALSE }, // OS: Wrapper macros must be enabled to use :CONSTRUCT. { NV_OFFSETOF(OBJSYS, pCl), classInfo(OBJCL), NV_TRUE }, { NV_OFFSETOF(OBJSYS, pGpuMgr), classInfo(OBJGPUMGR), NV_TRUE }, + { NV_OFFSETOF(OBJSYS, pGsyncMgr), classInfo(OBJGSYNCMGR), NV_TRUE }, { NV_OFFSETOF(OBJSYS, pGpuAcct), classInfo(GpuAccounting), NV_TRUE }, { NV_OFFSETOF(OBJSYS, pRcDB), classInfo(OBJRCDB), NV_TRUE }, { NV_OFFSETOF(OBJSYS, pVmm), classInfo(OBJVMM), NV_TRUE }, + { NV_OFFSETOF(OBJSYS, pKernelVgpuMgr), classInfo(KernelVgpuMgr), NV_TRUE }, { NV_OFFSETOF(OBJSYS, pGpuBoostMgr), classInfo(OBJGPUBOOSTMGR), NV_TRUE }, { NV_OFFSETOF(OBJSYS, pFabric), classInfo(Fabric), NV_TRUE }, { NV_OFFSETOF(OBJSYS, pGpuDb), classInfo(GpuDb), NV_TRUE }, @@ -111,6 +117,13 @@ sysConstruct_IMPL(OBJSYS *pSys) osGetCurrentTime(&sec, &uSec); pSys->rmInstanceId = (NvU64)sec * 1000000 + (NvU64)uSec; + { + // Using Hypervisor native interface to detect + OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys); + if (pHypervisor) + hypervisorDetection(pHypervisor, pOS); + } + if (!pOS->osRmInitRm(pOS)) { status = NV_ERR_GENERIC; @@ -448,7 +461,7 @@ coreShutdownRm(void) objDelete(pSys); // - // Deinitalize libraries used by RM + // Deinitialize libraries used by RM // nvAssertDestroy(); @@ -636,6 +649,15 @@ sysInitRegistryOverrides_IMPL pSys->setProperty(pSys, PDB_PROP_SYS_PRIORITY_THROTTLE_DELAY_US, data32); } + if (osReadRegistryDword(pGpu, NV_REG_STR_RM_MULTICAST_FLA, + &data32) == NV_OK) + { + if (data32 == NV_REG_STR_RM_MULTICAST_FLA_ENABLED) + { + pSys->bMulticastFlaEnabled = NV_TRUE; + } + } + _sysRegistryOverrideExternalFabricMgmt(pSys, pGpu); _sysRegistryOverrideResourceServer(pSys, pGpu); @@ -643,11 +665,18 @@ sysInitRegistryOverrides_IMPL { pSys->setProperty(pSys, PDB_PROP_SYS_BUGCHECK_ON_TIMEOUT, NV_TRUE); } + + if (osReadRegistryDword(pGpu, NV_REG_STR_RM_ENABLE_ROUTE_TO_PHYSICAL_LOCK_BYPASS, + &data32) == NV_OK) + { + pSys->setProperty(pSys, PDB_PROP_SYS_ROUTE_TO_PHYSICAL_LOCK_BYPASS, !!data32); + } } void sysApplyLockingPolicy_IMPL(OBJSYS *pSys) { + g_resServ.bRouteToPhysicalLockBypass = pSys->getProperty(pSys, PDB_PROP_SYS_ROUTE_TO_PHYSICAL_LOCK_BYPASS); g_resServ.roTopLockApiMask = pSys->apiLockMask; } diff --git a/src/nvidia/src/kernel/core/thread_state.c b/src/nvidia/src/kernel/core/thread_state.c index 5c081ff54..6da8d1b32 100644 --- a/src/nvidia/src/kernel/core/thread_state.c +++ b/src/nvidia/src/kernel/core/thread_state.c @@ -42,6 +42,7 @@ #include "gpu/gpu.h" #include "gpu/gpu_timeout.h" +#include "virtualization/hypervisor/hypervisor.h" #include "diagnostics/journal.h" THREAD_STATE_DB threadStateDatabase; @@ -326,6 +327,25 @@ static NV_STATUS _threadNodeInitTime(THREAD_STATE_NODE *pThreadNode) computeTimeoutMsecs = pThreadNode->timeout.overrideTimeoutMsecs; } + NvBool deviceInit = ((pThreadNode->flags & THREAD_STATE_FLAGS_DEVICE_INIT) != 0); + if (deviceInit && hypervisorIsType(OS_HYPERVISOR_HYPERV)) + { + // + // Hyper-V intercepts MMIO accesses to the GPU adding a lot of extra + // latency. This causes RM device init that is very heavy in MMIO + // accesses to take much longer than on baremetal. To WAR this, use a + // long 60 secs timeout for threads performing device init. This should + // leave us with a comfortable buffer as the longest init observed so + // far was 20 seconds on K80. + // + // See bug 1900927 for more details. + // + const NvU32 HYPER_V_INIT_TIMEOUT_MS = 60 * 1000; + + computeTimeoutMsecs = HYPER_V_INIT_TIMEOUT_MS; + nonComputeTimeoutMsecs = HYPER_V_INIT_TIMEOUT_MS; + } + _threadStateSetNextCpuYieldTime(pThreadNode); if (threadStateDatabase.timeout.flags & GPU_TIMEOUT_FLAGS_OSTIMER) @@ -1207,13 +1227,13 @@ NV_STATUS threadStateEnqueueCallbackOnFree { THREAD_STATE_FREE_CALLBACK *pCbListNode; - if (!(pThreadNode->flags & THREAD_STATE_FLAGS_STATE_FREE_CB_ENABLED)) - return NV_ERR_INVALID_OPERATION; - if ((pThreadNode == NULL) || (pCallback == NULL) || (pCallback->pCb == NULL)) return NV_ERR_INVALID_ARGUMENT; + if (!(pThreadNode->flags & THREAD_STATE_FLAGS_STATE_FREE_CB_ENABLED)) + return NV_ERR_INVALID_OPERATION; + // Add from tail to maintain FIFO semantics. pCbListNode = listAppendNew(&pThreadNode->cbList); if (pCbListNode == NULL) diff --git a/src/nvidia/src/kernel/diagnostics/gpu_acct.c b/src/nvidia/src/kernel/diagnostics/gpu_acct.c index 143d9ef4d..9087a720c 100644 --- a/src/nvidia/src/kernel/diagnostics/gpu_acct.c +++ b/src/nvidia/src/kernel/diagnostics/gpu_acct.c @@ -420,6 +420,27 @@ gpuacctFindProcEntryFromPidSubpid pidToSearch = 0; status = NV_OK; + if (subPid != 0) + { + NvU32 vmIndex; + + // It's a process running on VM, find data store for the VM. + for (vmIndex = 0; vmIndex < MAX_VGPU_DEVICES_PER_PGPU; ++vmIndex) + { + if (pGpuInstanceInfo->vmInstanceInfo[vmIndex].vmPId == pid) + { + break; + } + } + if (vmIndex == MAX_VGPU_DEVICES_PER_PGPU) + { + // Didn't find vm proc id on this GPU, return error. + return NV_ERR_INVALID_STATE; + } + pDS = &pGpuInstanceInfo->vmInstanceInfo[vmIndex].liveVMProcAcctInfo; + pidToSearch = subPid; + } + else { // It's a process running on GPU, return data store for GPU. pDS = &pGpuInstanceInfo->liveProcAcctInfo; @@ -526,11 +547,9 @@ gpuacctProcessGpuUtil { GPUACCT_PROC_ENTRY *pEntry; NV_STATUS status = NV_OK; - NvU64 maxTimeStamp; + NvU64 maxTimeStamp = 0; NvU32 index; - maxTimeStamp = 0; - for (index = 0; index < NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL; ++index) { if (pUtilSampleBuffer[index].base.timeStamp <= pGpuInstanceInfo->lastUpdateTimestamp) @@ -549,8 +568,10 @@ gpuacctProcessGpuUtil // If the PMU sample entry's pid or subpid is invalid, then we won't find the // pid-subpid entry in data store, so skip processing this PMU gr sample. + // When run on GSP, only process VF samples. if (pUtilSampleBuffer[index].gr.procId != NV2080_GPUMON_PID_INVALID && - pUtilSampleBuffer[index].gr.subProcessID != NV2080_GPUMON_PID_INVALID) + pUtilSampleBuffer[index].gr.subProcessID != NV2080_GPUMON_PID_INVALID + ) { // Find data store in which we should look up the PMU gr sample's pid/subpid. status = gpuacctFindProcEntryFromPidSubpid(pGpuInstanceInfo, @@ -573,8 +594,10 @@ gpuacctProcessGpuUtil // If the PMU sample entry's pid or subpid is invalid, then we won't find the // pid-subpid entry in data store, so skip processing this PMU fb sample. + // When run on GSP, only process VF samples. if (pUtilSampleBuffer[index].fb.procId != NV2080_GPUMON_PID_INVALID && - pUtilSampleBuffer[index].fb.subProcessID != NV2080_GPUMON_PID_INVALID) + pUtilSampleBuffer[index].fb.subProcessID != NV2080_GPUMON_PID_INVALID + ) { // If GR sample and FB sample are of same pid-subpid, no need to find the proc entry again. if (pUtilSampleBuffer[index].gr.procId != pUtilSampleBuffer[index].fb.procId || @@ -590,6 +613,7 @@ gpuacctProcessGpuUtil if (status == NV_OK && pEntry != NULL) { pEntry->sumFbUtil += pUtilSampleBuffer[index].fb.util; + } } } @@ -632,6 +656,7 @@ gpuacctStartGpuAccounting_IMPL NV_STATUS status = NV_OK; GPUACCT_PROC_ENTRY *pEntry = NULL; GPU_ACCT_PROC_DATA_STORE *pDS = NULL; + NvBool bVgpuOnGspEnabled; pGpu = gpumgrGetGpu(gpuInstance); NV_ASSERT_OR_RETURN(pGpu != NULL, NV_ERR_INVALID_STATE); @@ -639,7 +664,34 @@ gpuacctStartGpuAccounting_IMPL GPUACCT_GPU_INSTANCE_INFO *gpuInstanceInfo = &pGpuAcct->gpuInstanceInfo[gpuInstance]; vmIndex = NV_INVALID_VM_INDEX; - pDS = &gpuInstanceInfo->liveProcAcctInfo; + + bVgpuOnGspEnabled = IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && RMCFG_FEATURE_PLATFORM_GSP; + if ((hypervisorIsVgxHyper() || bVgpuOnGspEnabled) && IS_VALID_SUBPID(subPid)) + { + NvU32 i; + + for (i = 0; i < MAX_VGPU_DEVICES_PER_PGPU; i++) + { + if (pid == gpuInstanceInfo->vmInstanceInfo[i].vmPId) + { + // Check if accounting mode is enabled for this VM. + // If not, just return. + if (gpuInstanceInfo->vmInstanceInfo[i].isAccountingEnabled == + NV0000_CTRL_GPU_ACCOUNTING_STATE_DISABLED) + { + return status; + } + + // Accounting enabled, save the vmIndex and break out of loop. + vmIndex = i; + break; + } + } + } + + pDS = (vmIndex == NV_INVALID_VM_INDEX) ? + &gpuInstanceInfo->liveProcAcctInfo : + &gpuInstanceInfo->vmInstanceInfo[vmIndex].liveVMProcAcctInfo; NV_ASSERT_OR_RETURN(pDS != NULL, NV_ERR_INVALID_STATE); @@ -713,6 +765,7 @@ gpuacctStopGpuAccounting_IMPL NV_STATUS status; NvU32 searchPid; NvU32 vmIndex; + NvBool bVgpuOnGspEnabled; pGpu = gpumgrGetGpu(gpuInstance); NV_ASSERT_OR_RETURN(pGpu != NULL, NV_ERR_INVALID_STATE); @@ -721,6 +774,29 @@ gpuacctStopGpuAccounting_IMPL vmIndex = NV_INVALID_VM_INDEX; + bVgpuOnGspEnabled = IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && RMCFG_FEATURE_PLATFORM_GSP; + + // Find vmIndex, if subPid is passed. + if ((hypervisorIsVgxHyper() || bVgpuOnGspEnabled) && IS_VALID_SUBPID(subPid)) + { + NvBool bVMFound = NV_FALSE; + NvU32 i; + + for (i = 0; i < MAX_VGPU_DEVICES_PER_PGPU; i++) + { + if (pid == pGpuInstanceInfo->vmInstanceInfo[i].vmPId) + { + bVMFound = NV_TRUE; + vmIndex = i; + break; + } + } + if (bVMFound == NV_FALSE) + { + return NV_ERR_INVALID_STATE; + } + } + if (vmIndex == NV_INVALID_VM_INDEX) { // Delete the pid from live process list only if subpid is zero. @@ -733,6 +809,13 @@ gpuacctStopGpuAccounting_IMPL searchPid = pid; } + else + { + pLiveDS = &pGpuInstanceInfo->vmInstanceInfo[vmIndex].liveVMProcAcctInfo; + pDeadDS = &pGpuInstanceInfo->vmInstanceInfo[vmIndex].deadVMProcAcctInfo; + + searchPid = subPid; + } status = gpuacctLookupProcEntry(pLiveDS, searchPid, &pEntry); if (status != NV_OK) @@ -830,8 +913,35 @@ gpuacctUpdateProcPeakFbUsage_IMPL GPU_ACCT_PROC_DATA_STORE *pDS = NULL; NV_STATUS status; - pDS = &pGpuAcct->gpuInstanceInfo[gpuInstance].liveProcAcctInfo; - status = gpuacctLookupProcEntry(pDS, pid, &pEntry); + // Find live process data store for the VM if subpid was passed. + if (hypervisorIsVgxHyper() && IS_VALID_SUBPID(subPid)) + { + NvU32 vmIndex; + + for (vmIndex = 0; vmIndex < MAX_VGPU_DEVICES_PER_PGPU; vmIndex++) + { + if (pGpuAcct->gpuInstanceInfo[gpuInstance].vmInstanceInfo[vmIndex].vmPId == pid) + { + pDS = &pGpuAcct->gpuInstanceInfo[gpuInstance].vmInstanceInfo[vmIndex].liveVMProcAcctInfo; + break; + } + } + } + else + { + pDS = &pGpuAcct->gpuInstanceInfo[gpuInstance].liveProcAcctInfo; + } + + NV_ASSERT_OR_RETURN(pDS != NULL, NV_ERR_INVALID_STATE); + + if (hypervisorIsVgxHyper() && IS_VALID_SUBPID(subPid)) + { + status = gpuacctLookupProcEntry(pDS, subPid, &pEntry); + } + else + { + status = gpuacctLookupProcEntry(pDS, pid, &pEntry); + } if (status != NV_OK) { @@ -878,12 +988,45 @@ gpuacctSetProcType_IMPL NvU32 procType ) { + OBJGPU *pGpu; GPUACCT_PROC_ENTRY *pEntry; GPU_ACCT_PROC_DATA_STORE *pDS = NULL; NV_STATUS status; + NvBool bVgpuOnGspEnabled; - pDS = &pGpuAcct->gpuInstanceInfo[gpuInstance].liveProcAcctInfo; - status = gpuacctLookupProcEntry(pDS, pid, &pEntry); + pGpu = gpumgrGetGpu(gpuInstance); + NV_ASSERT_OR_RETURN(pGpu != NULL, NV_ERR_INVALID_STATE); + + bVgpuOnGspEnabled = IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu); + // If on VGX host and the call is for a guest process. + if ((hypervisorIsVgxHyper() || bVgpuOnGspEnabled) && IS_VALID_SUBPID(subPid)) + { + NvU32 vmIndex; + + for (vmIndex = 0; vmIndex < MAX_VGPU_DEVICES_PER_PGPU; vmIndex++) + { + if (pGpuAcct->gpuInstanceInfo[gpuInstance].vmInstanceInfo[vmIndex].vmPId == pid) + { + pDS = &pGpuAcct->gpuInstanceInfo[gpuInstance].vmInstanceInfo[vmIndex].liveVMProcAcctInfo; + break; + } + } + } + else + { + pDS = &pGpuAcct->gpuInstanceInfo[gpuInstance].liveProcAcctInfo; + } + + NV_ASSERT_OR_RETURN(pDS != NULL, NV_ERR_INVALID_STATE); + + if ((hypervisorIsVgxHyper() || bVgpuOnGspEnabled) && IS_VALID_SUBPID(subPid)) + { + status = gpuacctLookupProcEntry(pDS, subPid, &pEntry); + } + else + { + status = gpuacctLookupProcEntry(pDS, pid, &pEntry); + } if (status != NV_OK) { @@ -929,6 +1072,7 @@ gpuacctGetProcAcctInfo_IMPL GPUACCT_GPU_INSTANCE_INFO *pGpuInstanceInfo; NvU32 sampleCount; NvBool isLiveProcess; + NvBool bVgpuOnGspEnabled; NV_ASSERT_OR_RETURN(pParams != NULL, NV_ERR_INVALID_ARGUMENT); @@ -938,6 +1082,33 @@ gpuacctGetProcAcctInfo_IMPL pGpuInstanceInfo = &pGpuAcct->gpuInstanceInfo[pGpu->gpuInstance]; vmIndex = NV_INVALID_VM_INDEX; + bVgpuOnGspEnabled = IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && RMCFG_FEATURE_PLATFORM_GSP; + + // if subPid passed in, find the VM index. + if ((hypervisorIsVgxHyper() || bVgpuOnGspEnabled) && IS_VALID_SUBPID(pParams->subPid)) + { + NvBool bVMFound = NV_FALSE; + NvU32 i; + + if (pParams->pid != NV_INVALID_VM_PID) + { + for (i = 0; i < MAX_VGPU_DEVICES_PER_PGPU; i++) + { + if (pGpuInstanceInfo->vmInstanceInfo[i].vmPId == pParams->pid) + { + vmIndex = i; + bVMFound = NV_TRUE; + break; + } + } + // If call is for VM process and VM not found, cannot continue, return. + if (bVMFound == NV_FALSE) + { + return NV_ERR_INVALID_ARGUMENT; + } + } + } + isLiveProcess = NV_FALSE; // Try finding process entry in dead process list. @@ -945,6 +1116,10 @@ gpuacctGetProcAcctInfo_IMPL { pDS = &pGpuInstanceInfo->deadProcAcctInfo; } + else + { + pDS = &pGpuInstanceInfo->vmInstanceInfo[vmIndex].deadVMProcAcctInfo; + } NV_ASSERT_OR_RETURN(pDS != NULL, NV_ERR_INVALID_STATE); if (vmIndex == NV_INVALID_VM_INDEX) @@ -971,6 +1146,10 @@ gpuacctGetProcAcctInfo_IMPL { pDS = &pGpuInstanceInfo->liveProcAcctInfo; } + else + { + pDS = &pGpuInstanceInfo->vmInstanceInfo[vmIndex].liveVMProcAcctInfo; + } NV_ASSERT_OR_RETURN(pDS != NULL, NV_ERR_INVALID_STATE); if (vmIndex == NV_INVALID_VM_INDEX) @@ -1034,8 +1213,10 @@ gpuacctGetAcctPids_IMPL GPU_ACCT_PROC_LIST *pList; OBJGPU *pGpu; NvU32 count; + NvU32 vmPid; NvU32 vmIndex; GPUACCT_GPU_INSTANCE_INFO *pGpuInstanceInfo; + NvBool bVgpuOnGspEnabled; ct_assert((NV_MAX_LIVE_ACCT_PROCESS + NV_MAX_DEAD_ACCT_PROCESS) <= NV0000_GPUACCT_PID_MAX_COUNT); @@ -1050,10 +1231,44 @@ gpuacctGetAcctPids_IMPL count = 0; vmIndex = NV_INVALID_VM_INDEX; + bVgpuOnGspEnabled = IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && RMCFG_FEATURE_PLATFORM_GSP; + + // Set vmPid if we are on VGX host and pAcctPidsParams->pid is non zero. + // pAcctPidsParams->pid will be set when the RM control call is coming + // from VGPU plugin, otherwise will be 0. + vmPid = ((hypervisorIsVgxHyper() || bVgpuOnGspEnabled) && (pParams->pid != 0)) ? + pParams->pid : + NV_INVALID_VM_PID; + + // Find vmIndex if vmPid is provided. + if (vmPid != NV_INVALID_VM_PID) + { + NvU32 i; + NvBool bVMFound = NV_FALSE; + + for (i = 0; i < MAX_VGPU_DEVICES_PER_PGPU; i++) + { + if (pGpuInstanceInfo->vmInstanceInfo[i].vmPId == vmPid) + { + vmIndex = i; + bVMFound = NV_TRUE; + break; + } + } + if (bVMFound == NV_FALSE) + { + return NV_ERR_INVALID_ARGUMENT; + } + } + if (vmIndex == NV_INVALID_VM_INDEX) { pList = &pGpuInstanceInfo->deadProcAcctInfo.procList; } + else + { + pList = &pGpuInstanceInfo->vmInstanceInfo[vmIndex].deadVMProcAcctInfo.procList; + } NV_ASSERT_OR_RETURN(pList != NULL, NV_ERR_INVALID_STATE); GPU_ACCT_PROC_LISTIter iter = listIterAll(pList); @@ -1070,6 +1285,10 @@ gpuacctGetAcctPids_IMPL { pList = &pGpuInstanceInfo->liveProcAcctInfo.procList; } + else + { + pList = &pGpuInstanceInfo->vmInstanceInfo[vmIndex].liveVMProcAcctInfo.procList; + } NV_ASSERT_OR_RETURN(pList != NULL, NV_ERR_INVALID_STATE); iter = listIterAll(pList); @@ -1106,7 +1325,8 @@ gpuacctGetAccountingMode_IMPL ) { OBJGPU *pGpu; - NvU32 vmPid; + NvU32 vmPid = NV_INVALID_VM_PID; + NvBool bVgpuOnGspEnabled; NV_ASSERT_OR_RETURN(pGetAcctModeParams != NULL, NV_ERR_INVALID_ARGUMENT); @@ -1114,10 +1334,12 @@ gpuacctGetAccountingMode_IMPL if (pGpu == NULL) return NV_ERR_INVALID_ARGUMENT; + bVgpuOnGspEnabled = IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && RMCFG_FEATURE_PLATFORM_GSP; + // Set vmPid if we are on VGX host and pParams->pid is non zero. // pParams->pid will be set when the RM control call is coming // from VGPU plugin, otherwise will be 0. - vmPid = (hypervisorIsVgxHyper() && (pGetAcctModeParams->pid != 0)) ? + vmPid = ((hypervisorIsVgxHyper() || bVgpuOnGspEnabled) && (pGetAcctModeParams->pid != 0)) ? pGetAcctModeParams->pid : NV_INVALID_VM_PID; @@ -1127,6 +1349,27 @@ gpuacctGetAccountingMode_IMPL NV0000_CTRL_GPU_ACCOUNTING_STATE_ENABLED : NV0000_CTRL_GPU_ACCOUNTING_STATE_DISABLED; } + else + { + NvU32 vmIndex; + NvBool bVMFound; + + GPUACCT_GPU_INSTANCE_INFO *gpuInstanceInfo = &pGpuAcct->gpuInstanceInfo[pGpu->gpuInstance]; + bVMFound = NV_FALSE; + for (vmIndex = 0; vmIndex < MAX_VGPU_DEVICES_PER_PGPU; vmIndex++) + { + if (gpuInstanceInfo->vmInstanceInfo[vmIndex].vmPId == vmPid) + { + bVMFound = NV_TRUE; + pGetAcctModeParams->state = gpuInstanceInfo->vmInstanceInfo[vmIndex].isAccountingEnabled; + break; + } + } + if (bVMFound == NV_FALSE) + { + return NV_ERR_OBJECT_NOT_FOUND; + } + } return NV_OK; } @@ -1215,10 +1458,9 @@ gpuacctStopTimerCallbacks pGpuInstanceInfo->pTmrEvent = NULL; } +done: portMemFree(pGpuInstanceInfo->pSamplesParams); pGpuInstanceInfo->pSamplesParams = NULL; - - done: pGpu->setProperty(pGpu, PDB_PROP_GPU_ACCOUNTING_ON, NV_FALSE); } @@ -1243,6 +1485,8 @@ gpuacctEnableAccounting_IMPL OBJGPU *pGpu; GPUACCT_GPU_INSTANCE_INFO *pGpuInstanceInfo; NV_STATUS status = NV_OK; + NvU32 vmPid = NV_INVALID_VM_PID; + NvBool bVgpuOnGspEnabled; NV_ASSERT_OR_RETURN(pSetAcctModeParams != NULL, NV_ERR_INVALID_ARGUMENT); @@ -1258,10 +1502,12 @@ gpuacctEnableAccounting_IMPL if (IS_MIG_ENABLED(pGpu)) return NV_ERR_NOT_SUPPORTED; + bVgpuOnGspEnabled = IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && RMCFG_FEATURE_PLATFORM_GSP; + // Set vmPid if we are on VGX host and pParams->pid is non zero. // pParams->pid will be set when the RM control call is coming // from VGPU plugin, otherwise will be 0. - NvU32 vmPid = (hypervisorIsVgxHyper() && (pSetAcctModeParams->pid != 0)) ? + vmPid = ((hypervisorIsVgxHyper() || bVgpuOnGspEnabled) && (pSetAcctModeParams->pid != 0)) ? pSetAcctModeParams->pid : NV_INVALID_VM_PID; @@ -1273,6 +1519,24 @@ gpuacctEnableAccounting_IMPL if (status != NV_OK) return status; } + else + { + NvU32 vmIndex; + NvBool bVMFound = NV_FALSE; + for(vmIndex = 0; vmIndex < MAX_VGPU_DEVICES_PER_PGPU; vmIndex++) + { + if (pGpuInstanceInfo->vmInstanceInfo[vmIndex].vmPId == vmPid) + { + bVMFound = NV_TRUE; + pGpuInstanceInfo->vmInstanceInfo[vmIndex].isAccountingEnabled = NV0000_CTRL_GPU_ACCOUNTING_STATE_ENABLED; + break; + } + } + if (bVMFound == NV_FALSE) + { + return NV_ERR_OBJECT_NOT_FOUND; + } + } return status; } @@ -1298,8 +1562,9 @@ gpuacctDisableAccounting_IMPL { GPU_ACCT_PROC_DATA_STORE *pDS = NULL; OBJGPU *pGpu; - NvU32 vmPid; + NvU32 vmPid = NV_INVALID_VM_PID; GPUACCT_GPU_INSTANCE_INFO *pGpuInstanceInfo; + NvBool bVgpuOnGspEnabled; NV_ASSERT_OR_RETURN(pSetAcctModeParams != NULL, NV_ERR_INVALID_ARGUMENT); @@ -1307,10 +1572,12 @@ gpuacctDisableAccounting_IMPL if (pGpu == NULL) return NV_ERR_INVALID_ARGUMENT; + bVgpuOnGspEnabled = IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && RMCFG_FEATURE_PLATFORM_GSP; + // Set vmPid if we are on VGX host and pParams->pid is non zero. // pParams->pid will be set when the RM control call is coming // from VGPU plugin, otherwise will be 0. - vmPid = (hypervisorIsVgxHyper() && (pSetAcctModeParams->pid != 0)) ? + vmPid = ((hypervisorIsVgxHyper() || bVgpuOnGspEnabled) && (pSetAcctModeParams->pid != 0)) ? pSetAcctModeParams->pid : NV_INVALID_VM_PID; @@ -1318,7 +1585,7 @@ gpuacctDisableAccounting_IMPL // start gathering accounting data regardless of when guest comes and goes. // Don't allow user to disable accounting mode on VGX host. if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ACCOUNTING_ON) && - hypervisorIsVgxHyper() && (vmPid == NV_INVALID_VM_PID)) + (hypervisorIsVgxHyper() || bVgpuOnGspEnabled) && (vmPid == NV_INVALID_VM_PID)) { return NV_ERR_NOT_SUPPORTED; } @@ -1331,6 +1598,21 @@ gpuacctDisableAccounting_IMPL pDS = &pGpuInstanceInfo->liveProcAcctInfo; } + else + { + NvU32 i; + + for (i = 0; i < MAX_VGPU_DEVICES_PER_PGPU; i++) + { + if (pGpuInstanceInfo->vmInstanceInfo[i].vmPId == vmPid) + { + pGpuInstanceInfo->vmInstanceInfo[i].isAccountingEnabled = NV0000_CTRL_GPU_ACCOUNTING_STATE_DISABLED; + + pDS = &pGpuInstanceInfo->vmInstanceInfo[i].liveVMProcAcctInfo; + break; + } + } + } NV_ASSERT_OR_RETURN(pDS != NULL, NV_ERR_INVALID_STATE); // remove (stale) entries from live process data store. @@ -1358,15 +1640,21 @@ gpuacctClearAccountingData_IMPL NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS *pClearAcctDataParams ) { - NvU32 vmPid; + OBJGPU *pGpu; + NvU32 vmPid = NV_INVALID_VM_PID; GPUACCT_GPU_INSTANCE_INFO *gpuInstanceInfo = &pGpuAcct->gpuInstanceInfo[gpuInstance]; + NvBool bVgpuOnGspEnabled; + pGpu = gpumgrGetGpu(gpuInstance); + NV_ASSERT_OR_RETURN(pGpu != NULL, NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN(pClearAcctDataParams != NULL, NV_ERR_INVALID_ARGUMENT); + bVgpuOnGspEnabled = IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && RMCFG_FEATURE_PLATFORM_GSP; + // Set vmPid if we are on VGX host and pParams->pid is non zero. // pParams->pid will be set when the RM control call is coming // from VGPU plugin, otherwise will be 0. - vmPid = (hypervisorIsVgxHyper() && (pClearAcctDataParams->pid != 0)) ? + vmPid = ((hypervisorIsVgxHyper() || bVgpuOnGspEnabled) && (pClearAcctDataParams->pid != 0)) ? pClearAcctDataParams->pid : NV_INVALID_VM_PID; @@ -1374,6 +1662,19 @@ gpuacctClearAccountingData_IMPL { gpuacctCleanupDataStore(&gpuInstanceInfo->deadProcAcctInfo); } + else + { + NvU32 vmIndex; + + for (vmIndex = 0; vmIndex < MAX_VGPU_DEVICES_PER_PGPU; vmIndex++) + { + if (gpuInstanceInfo->vmInstanceInfo[vmIndex].vmPId == vmPid) + { + gpuacctCleanupDataStore(&gpuInstanceInfo->vmInstanceInfo[vmIndex].deadVMProcAcctInfo); + break; + } + } + } return NV_OK; } @@ -1397,3 +1698,154 @@ static NvU64 gpuacctGetCurrTime return currTime; } +/*! + * Destroys accounting data for the VM. + * + * @param[in] vmInstanceInfo VM instance. + */ +static void +_vmAcctDestroyDataStore(GPUACCT_VM_INSTANCE_INFO *pVMInstanceInfo) +{ + if (pVMInstanceInfo == NULL) + { + return; + } + + gpuacctDestroyDataStore(&pVMInstanceInfo->liveVMProcAcctInfo); + gpuacctDestroyDataStore(&pVMInstanceInfo->deadVMProcAcctInfo); +} + +/*! + * Initilizes data store for a VM + * + * @param[in] vmInstanceInfo VM instance. + * + * @return NV_OK + * @return NV_ERR_INVALID_ARGUMENT + * @return NV_ERR_INVALID_STATE + */ +static NV_STATUS +vmAcctInitDataStore(GPUACCT_VM_INSTANCE_INFO *vmInstanceInfo) +{ + NV_STATUS status; + + if (vmInstanceInfo == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + status = gpuacctInitDataStore(&vmInstanceInfo->deadVMProcAcctInfo); + if (status != NV_OK) + { + gpuacctDestroyDataStore(&vmInstanceInfo->deadVMProcAcctInfo); + return status; + } + + status = gpuacctInitDataStore(&vmInstanceInfo->liveVMProcAcctInfo); + if (status != NV_OK) + { + gpuacctDestroyDataStore(&vmInstanceInfo->deadVMProcAcctInfo); + gpuacctDestroyDataStore(&vmInstanceInfo->liveVMProcAcctInfo); + } + + return status; +} + +/*! + * Top level function to initiate VM data store creation. + * + * @param[in] pSys Pointer of Sys. + * @param[in] pGpu Pointer to physical gpu object. + * @param[in] vmPid VM/Plugin process id. +*/ +void +vmAcctInitState(OBJGPU *pGpu, NvU32 vmPid) +{ + NvU32 vmIndex; + NvU32 targetVMIndex; + NvBool vmInstanceFound; + + OBJSYS *pSys = SYS_GET_INSTANCE(); + GpuAccounting *pGpuAcct = SYS_GET_GPUACCT(pSys); + + if (pGpu && pGpuAcct) + { + GPUACCT_GPU_INSTANCE_INFO *gpuInstanceInfo = &pGpuAcct->gpuInstanceInfo[pGpu->gpuInstance]; + targetVMIndex = 0; + vmInstanceFound = NV_FALSE; + + // Check if we have data store for this VM pid. + // If found, delete those data store. + for (vmIndex = 0; vmIndex < MAX_VGPU_DEVICES_PER_PGPU; vmIndex++) + { + GPUACCT_VM_INSTANCE_INFO *vmInstanceInfo = &gpuInstanceInfo->vmInstanceInfo[vmIndex]; + + if (vmPid == vmInstanceInfo->vmPId) + { + vmInstanceFound = NV_TRUE; + targetVMIndex = vmIndex; + + _vmAcctDestroyDataStore(vmInstanceInfo); + + vmInstanceInfo->isAccountingEnabled = NV0000_CTRL_GPU_ACCOUNTING_STATE_DISABLED; + + break; + } + if ((vmInstanceFound == NV_FALSE) && (vmInstanceInfo->vmPId == 0)) + { + vmInstanceFound = NV_TRUE; + targetVMIndex = vmIndex; + } + } + + if (vmInstanceFound == NV_TRUE) + { + GPUACCT_VM_INSTANCE_INFO *vmInstanceInfo = &gpuInstanceInfo->vmInstanceInfo[targetVMIndex]; + + if (vmAcctInitDataStore(vmInstanceInfo) == NV_OK) + { + vmInstanceInfo->vmPId = vmPid; + vmInstanceInfo->isAccountingEnabled = NV0000_CTRL_GPU_ACCOUNTING_STATE_DISABLED; + } + else + { + NV_PRINTF(LEVEL_INFO, + "Failed to create process accounting data store for VM Pid : %d\n", + vmInstanceInfo->vmPId); + } + } + } +} + +/*! + * Top level function to destroy VM data store. + * + * @param[in] pSys Pointer of Sys. + * @param[in] vmPid VM/Plugin process id. + * @param[in] gpuPciId gpuid of the physical gpu associated with the VM. + */ +void +vmAcctDestructState(NvU32 vmPid, OBJGPU *pGpu) +{ + GpuAccounting *pGpuAcct; + NvU32 vmIndex; + + OBJSYS *pSys = SYS_GET_INSTANCE(); + pGpuAcct = SYS_GET_GPUACCT(pSys); + + if (pGpu && pGpuAcct) + { + for (vmIndex = 0; vmIndex < MAX_VGPU_DEVICES_PER_PGPU; vmIndex++) + { + GPUACCT_VM_INSTANCE_INFO *vmInstanceInfo = &pGpuAcct->gpuInstanceInfo[pGpu->gpuInstance].vmInstanceInfo[vmIndex]; + if (vmPid == vmInstanceInfo->vmPId) + { + _vmAcctDestroyDataStore(vmInstanceInfo); + vmInstanceInfo->vmPId = 0; + + break; + } + } + } +} + diff --git a/src/nvidia/src/kernel/diagnostics/journal.c b/src/nvidia/src/kernel/diagnostics/journal.c index 118c22c85..47d596115 100644 --- a/src/nvidia/src/kernel/diagnostics/journal.c +++ b/src/nvidia/src/kernel/diagnostics/journal.c @@ -44,6 +44,7 @@ #include "gpu/bus/kern_bus.h" #include "gpu/mem_mgr/mem_mgr.h" #include "nvdevid.h" +#include "nvop.h" @@ -204,6 +205,12 @@ rcdbConstruct_IMPL(Journal *pRcDB) NvU32 i; void *pBuffer; + // Time parameters + NvU32 sec, usec; + NvU64 timeStamp; + NvU64 systemTime; + NvU64 timeStampFreq; + _initJournal(pJournal, JOURNAL_BUFFER_SIZE_DEFAULT); portMemSet(pRingBufferColl, 0x00, sizeof(pRcDB->RingBufferColl)); @@ -262,6 +269,15 @@ rcdbConstruct_IMPL(Journal *pRcDB) NV_PRINTF(LEVEL_ERROR, "failed to allocate NOCAT Ring Buffer\n"); } + // Save params for timestamp conversion + timeStampFreq = osGetTimestampFreq(); + timeStamp = osGetTimestamp(); + osGetCurrentTime(&sec, &usec); + systemTime = ((NvU64)sec * 1000000) + (NvU64)usec; + + pRcDB->systemTimeReference = systemTime - ((timeStamp * 1000000) / timeStampFreq); + pRcDB->timeStampFreq = timeStampFreq; + return NV_OK; } @@ -1064,7 +1080,7 @@ rcdbDumpComponent_IMPL pNvDumpState->bDumpInProcess = NV_TRUE; pNvDumpState->bugCheckCode = 0; pNvDumpState->internalCode = NVD_ERROR_CODE(NVD_EXTERNALLY_GENERATED, 0); - pNvDumpState->bRMLock = rmApiLockIsOwner(); + pNvDumpState->bRMLock = rmapiLockIsOwner(); pNvDumpState->bGpuAccessible = NV_FALSE; pNvDumpState->initialbufferSize = pBuffer->size; pNvDumpState->nvDumpType = NVD_DUMP_TYPE_API; @@ -2048,7 +2064,7 @@ _rcdbAddRmGpuDumpCallback if (status == NV_OK) { // LOCK: acquire API lock - status = rmApiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DIAG); + status = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DIAG); if (status == NV_OK) { // LOCK: acquire GPUs lock @@ -2078,7 +2094,7 @@ _rcdbAddRmGpuDumpCallback NV_PRINTF(LEVEL_ERROR, "failed to acquire the GPU locks!\n"); } // UNLOCK: release API lock - rmApiLockRelease(); + rmapiLockRelease(); } else { @@ -2756,7 +2772,7 @@ rcdbAddRmGpuDump prbEnc.depth = 0; pNvDumpState->bDumpInProcess = NV_TRUE; pNvDumpState->nvDumpType = NVD_DUMP_TYPE_OCA; - pNvDumpState->bRMLock = rmApiLockIsOwner(); + pNvDumpState->bRMLock = rmapiLockIsOwner(); rcdbDumpInitGpuAccessibleFlag(pGpu, pRcDB); @@ -3065,6 +3081,13 @@ _rcdbNocatCollectContext(OBJGPU *pGpu, Journal* pRcdb, NV2080_NOCAT_JOURNAL_GPU_ if (!osIsRaisedIRQL()) { + NV_STATUS status = pGpu->acpiMethodData.capsMethodData.status; + if (status == NV_OK) + { + pContextCache->bOptimus = + FLD_TEST_DRF(OP_FUNC, _OPTIMUSCAPS, _OPTIMUS_CAPABILITIES, + _DYNAMIC_POWER_CONTROL, pGpu->acpiMethodData.capsMethodData.optimusCaps); + } pContextCache->bValid = NV_TRUE; } @@ -3753,7 +3776,9 @@ rcdbNocatInsertNocatError( #if(NOCAT_PROBE_FB_MEMORY) if ((bCheckFBState) && (pGpu != NULL) - && (pGpu->nocatGpuCache.pCpuPtr != NULL)) + && (pGpu->nocatGpuCache.pCpuPtr != NULL) + // If using Coherent CPU mapping instead of BAR2 do not call VerifyBar2 + && !pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING)) { switch (kbusVerifyBar2_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu), &pGpu->nocatGpuCache.fbTestMemDesc, pGpu->nocatGpuCache.pCpuPtr, 0, NOCAT_FBSIZETESTED)) diff --git a/src/nvidia/src/kernel/diagnostics/nv_debug_dump.c b/src/nvidia/src/kernel/diagnostics/nv_debug_dump.c index 83a830168..810fe9027 100644 --- a/src/nvidia/src/kernel/diagnostics/nv_debug_dump.c +++ b/src/nvidia/src/kernel/diagnostics/nv_debug_dump.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -448,6 +448,7 @@ nvdDumpDebugBuffers_IMPL NvP64 pUmdBuffer = NvP64_NULL; NvP64 priv = NvP64_NULL; NvU32 bufSize = 0; + NvU8 *dataBuffer = NULL; status = prbEncNestedStart(pPrbEnc, NVDEBUG_NVDUMP_DCL_MSG); if (status != NV_OK) @@ -463,8 +464,8 @@ nvdDumpDebugBuffers_IMPL if (status != NV_OK) break; - status = prbAppendSubMsg(pPrbEnc, pCurrent->tag, NvP64_VALUE(pUmdBuffer), bufSize); - + dataBuffer = NvP64_VALUE(pUmdBuffer); + status = prbAppendSubMsg(pPrbEnc, pCurrent->tag, dataBuffer, bufSize); // Unmap DebugBuffer address memdescUnmap(pCurrent->pMemDesc, NV_TRUE, // Kernel mapping? osGetCurrentProcess(), pUmdBuffer, priv); @@ -495,7 +496,7 @@ prbAppendSubMsg NvU8 *subAlloc = NULL; NV_STATUS status = NV_OK; NV_STATUS endStatus = NV_OK; - NvU32 subMsgLen = 0; + NvU16 subMsgLen = 0; NvU32 i; // Create field descriptor @@ -522,10 +523,10 @@ prbAppendSubMsg header = (NVDUMP_SUB_ALLOC_HEADER *)pCurrent; subAlloc = pCurrent + sizeof(NVDUMP_SUB_ALLOC_HEADER); + subMsgLen = header->end - header->start; // If valid, copy contents if (header->flags & NVDUMP_SUB_ALLOC_VALID) { - subMsgLen = header->end - header->start; status = prbEncStubbedAddBytes(pPrbEnc, subAlloc, subMsgLen); if (status != NV_OK) goto done; diff --git a/src/nvidia/src/kernel/diagnostics/nvlog.c b/src/nvidia/src/kernel/diagnostics/nvlog.c index 50638bf72..6f5492e31 100644 --- a/src/nvidia/src/kernel/diagnostics/nvlog.c +++ b/src/nvidia/src/kernel/diagnostics/nvlog.c @@ -574,6 +574,7 @@ nvlogNowrapBufferPush // Another thread has already expanded the buffer, bail out. // TODO: Maybe we could store the handle and then try again? portSyncSpinlockRelease(NvLogLogger.mainLock); + portMemFree(pNewBuffer); return NV_FALSE; } diff --git a/src/nvidia/src/kernel/gpu/arch/ada/kern_gpu_ad102.c b/src/nvidia/src/kernel/gpu/arch/ada/kern_gpu_ad102.c index 8cb1390e2..b24c0d53d 100644 --- a/src/nvidia/src/kernel/gpu/arch/ada/kern_gpu_ad102.c +++ b/src/nvidia/src/kernel/gpu/arch/ada/kern_gpu_ad102.c @@ -63,9 +63,9 @@ static const GPUCHILDPRESENT gpuChildrenPresent_AD102[] = {classId(KernelDisplay), 1}, {classId(VirtMemAllocator), 1}, {classId(OBJDPAUX), 1}, - {classId(OBJFAN), 1}, + {classId(Fan), 1}, {classId(OBJHSHUBMANAGER), 1}, - {classId(OBJHSHUB), 2 }, + {classId(Hshub), 2 }, {classId(MemorySystem), 1}, {classId(KernelMemorySystem), 1}, {classId(MemoryManager), 1}, diff --git a/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c b/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c index e4fe11c9c..5bffbc803 100644 --- a/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c +++ b/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c @@ -146,9 +146,9 @@ static const GPUCHILDPRESENT gpuChildrenPresent_GA100[] = { classId(KernelDisplay), 1 }, { classId(VirtMemAllocator), 1 }, { classId(OBJDPAUX), 1 }, - { classId(OBJFAN), 1 }, + { classId(Fan), 1 }, { classId(OBJHSHUBMANAGER), 1 }, - { classId(OBJHSHUB), 2 }, + { classId(Hshub), 2 }, { classId(MemorySystem), 1 }, { classId(KernelMemorySystem), 1 }, { classId(MemoryManager), 1 }, @@ -235,9 +235,9 @@ static const GPUCHILDPRESENT gpuChildrenPresent_GA102[] = {classId(KernelDisplay), 1}, {classId(VirtMemAllocator), 1}, {classId(OBJDPAUX), 1}, - {classId(OBJFAN), 1}, + {classId(Fan), 1}, {classId(OBJHSHUBMANAGER), 1 }, - {classId(OBJHSHUB), 2 }, + {classId(Hshub), 2 }, {classId(MemorySystem), 1}, {classId(KernelMemorySystem), 1}, {classId(MemoryManager), 1}, diff --git a/src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c b/src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c index ff1a0d72f..6d5fdae27 100644 --- a/src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c +++ b/src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c @@ -156,12 +156,56 @@ NvBool gpuIsAtsSupportedWithSmcMemPartitioning_GH100(OBJGPU *pGpu) } /*! - * @brief Handle SEC_FAULT + * @brief Read back device ID and subsystem ID * - * @param[in] pGpu GPU object pointer + * @note This function is designed to avoid OBJBIF dependence for the case that + * RM need to get device id and subsystem id early in the init process, + * before OBJBIF is initialized. + * + * @param[in] pGpu GPU object pointer + * @param[out] pDevId Return value of device ID + * @param[out] pSsId Return value of subsystem ID */ -static void -_gpuHandleSecFault_GH100(OBJGPU *pGpu) +void +gpuReadDeviceId_GH100 +( + OBJGPU *pGpu, + NvU32 *pDevId, + NvU32 *pSsId +) +{ + NvU32 deviceId; + NvU32 ssId; + + if (pDevId == NULL || pSsId == NULL) return; + + if (GPU_BUS_CFG_CYCLE_RD32(pGpu, NV_EP_PCFG_GPU_ID, &deviceId) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Unable to read NV_EP_PCFG_GPU_ID\n"); + return; + } + *pDevId = deviceId; + + if (GPU_BUS_CFG_CYCLE_RD32(pGpu, NV_EP_PCFG_GPU_SUBSYSTEM_ID, &ssId) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Unable to read NV_EP_PCFG_GPU_SUBSYSTEM_ID\n"); + return; + } + *pSsId = ssId; +} + +/*! + * @brief Handle SEC_FAULT + * + * @param[in] pGpu GPU object pointer + */ +void +gpuHandleSecFault_GH100 +( + OBJGPU *pGpu +) { NvU32 secDebug = 0; @@ -245,7 +289,7 @@ gpuHandleSanityCheckRegReadError_GH100 if ((value == NV_XAL_EP_SCPM_PRI_DUMMY_DATA_PATTERN_INIT) && (osGpuReadReg032(pGpu, NV_PMC_BOOT_0) == NV_XAL_EP_SCPM_PRI_DUMMY_DATA_PATTERN_INIT)) { - _gpuHandleSecFault_GH100(pGpu); + gpuHandleSecFault_HAL(pGpu); } else { @@ -329,9 +373,9 @@ static const GPUCHILDPRESENT gpuChildrenPresent_GH100[] = { classId(KernelDisplay), 1 }, { classId(VirtMemAllocator), 1 }, { classId(OBJDPAUX), 1 }, - { classId(OBJFAN), 1 }, + { classId(Fan), 1 }, { classId(OBJHSHUBMANAGER), 1 }, - { classId(OBJHSHUB), 5 }, + { classId(Hshub), 5 }, { classId(MemorySystem), 1 }, { classId(KernelMemorySystem), 1 }, { classId(MemoryManager), 1 }, diff --git a/src/nvidia/src/kernel/gpu/arch/maxwell/kern_gpu_gm107.c b/src/nvidia/src/kernel/gpu/arch/maxwell/kern_gpu_gm107.c index 75b5318e7..a852aa8cb 100644 --- a/src/nvidia/src/kernel/gpu/arch/maxwell/kern_gpu_gm107.c +++ b/src/nvidia/src/kernel/gpu/arch/maxwell/kern_gpu_gm107.c @@ -29,6 +29,25 @@ #include "published/maxwell/gm107/dev_nv_xve1.h" #include "published/maxwell/gm107/dev_fuse.h" +/*! + * @brief Returns SR-IOV capabilities + * + * @param[in] pGpu OBJGPU pointer + * @param[out] pParams Pointer for get_sriov_caps params + * + * @returns NV_OK always + */ +NV_STATUS +gpuGetSriovCaps_GM107 +( + OBJGPU *pGpu, + NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS *pParams +) +{ + pParams->bSriovEnabled = NV_FALSE; + return NV_OK; +} + /*! * @brief Read fuse for display supported status. * Some chips not marked displayless do not support display @@ -237,6 +256,20 @@ gpuWriteFunctionConfigRegEx_GM107 return NV_OK; } +void +gpuReadDeviceId_GM107 +( + OBJGPU *pGpu, + NvU32 *devId, + NvU32 *ssId +) +{ + if (devId == NULL || ssId == NULL) return; + + *devId = GPU_REG_RD32(pGpu, DEVICE_BASE(NV_PCFG) + NV_XVE_ID); + *ssId = GPU_REG_RD32(pGpu, DEVICE_BASE(NV_PCFG) + NV_XVE_SUBSYSTEM); +} + /*! * @brief Perform gpu-dependent error handling for error during register read sanity check * @@ -357,7 +390,7 @@ gpuChildOrderList_GM200[] = {classId(OBJTMR), GCO_ALL}, {classId(Therm), GCO_ALL}, {classId(OBJHSHUBMANAGER), GCO_ALL}, - {classId(OBJHSHUB), GCO_ALL}, + {classId(Hshub), GCO_ALL}, {classId(MemorySystem), GCO_ALL}, {classId(KernelMemorySystem), GCO_ALL}, {classId(MemoryManager), GCO_ALL}, @@ -385,12 +418,12 @@ gpuChildOrderList_GM200[] = {classId(OBJDISP), GCO_LIST_DESTROY}, {classId(KernelDisplay), GCO_LIST_DESTROY}, {classId(OBJHDA), GCO_LIST_DESTROY}, - {classId(OBJFAN), GCO_LIST_DESTROY}, + {classId(Fan), GCO_LIST_DESTROY}, {classId(VirtMemAllocator), GCO_ALL}, {classId(OBJDISP), GCO_LIST_INIT}, {classId(KernelDisplay), GCO_LIST_INIT}, {classId(OBJHDA), GCO_LIST_INIT}, - {classId(OBJFAN), GCO_LIST_INIT}, + {classId(Fan), GCO_LIST_INIT}, {classId(GraphicsManager), GCO_ALL}, {classId(MIGManager), GCO_ALL}, {classId(KernelMIGManager), GCO_ALL}, @@ -412,7 +445,7 @@ gpuChildOrderList_GM200[] = {classId(OBJDISP), GCO_LIST_LOAD | GCO_LIST_UNLOAD}, // LOAD Display is *after* cipher so that hdcp keys can be loaded . {classId(KernelDisplay), GCO_LIST_LOAD | GCO_LIST_UNLOAD}, // LOAD Display is *after* cipher so that hdcp keys can be loaded . {classId(OBJHDA), GCO_LIST_LOAD | GCO_LIST_UNLOAD}, - {classId(OBJFAN), GCO_LIST_LOAD | GCO_LIST_UNLOAD}, + {classId(Fan), GCO_LIST_LOAD | GCO_LIST_UNLOAD}, {classId(OBJCE), GCO_ALL}, {classId(KernelCE), GCO_ALL}, {classId(OBJMSENC), GCO_ALL}, @@ -469,9 +502,9 @@ static const GPUCHILDPRESENT gpuChildrenPresent_GM200[] = {classId(KernelDisplay), 1}, {classId(VirtMemAllocator), 1}, {classId(OBJDPAUX), 1}, - {classId(OBJFAN), 1}, + {classId(Fan), 1}, {classId(OBJHSHUBMANAGER), 1}, - {classId(OBJHSHUB), 1}, + {classId(Hshub), 1}, {classId(MemorySystem), 1}, {classId(KernelMemorySystem), 1}, {classId(MemoryManager), 1}, diff --git a/src/nvidia/src/kernel/gpu/arch/turing/kern_gpu_tu102.c b/src/nvidia/src/kernel/gpu/arch/turing/kern_gpu_tu102.c index 2af85cc01..0014e9feb 100644 --- a/src/nvidia/src/kernel/gpu/arch/turing/kern_gpu_tu102.c +++ b/src/nvidia/src/kernel/gpu/arch/turing/kern_gpu_tu102.c @@ -24,6 +24,46 @@ #include "published/turing/tu102/dev_vm.h" #include "published/turing/tu102/hwproject.h" +/*! + * @brief Returns SR-IOV capabilities + * + * @param[in] pGpu OBJGPU pointer + * @param[out] pParams Pointer for get_sriov_caps params + * + * @returns NV_OK always + */ +NV_STATUS +gpuGetSriovCaps_TU102 +( + OBJGPU *pGpu, + NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS *pParams +) +{ + if (!gpuIsSriovEnabled(pGpu)) + { + pParams->bSriovEnabled = NV_FALSE; + return NV_OK; + } + + pParams->bSriovEnabled = NV_TRUE; + pParams->totalVFs = pGpu->sriovState.totalVFs; + pParams->firstVfOffset = pGpu->sriovState.firstVFOffset; + pParams->FirstVFBar0Address = pGpu->sriovState.firstVFBarAddress[0]; + pParams->FirstVFBar1Address = pGpu->sriovState.firstVFBarAddress[1]; + pParams->FirstVFBar2Address = pGpu->sriovState.firstVFBarAddress[2]; + pParams->bar0Size = pGpu->sriovState.vfBarSize[0]; + pParams->bar1Size = pGpu->sriovState.vfBarSize[1]; + pParams->bar2Size = pGpu->sriovState.vfBarSize[2]; + pParams->b64bitBar0 = pGpu->sriovState.b64bitVFBar0; + pParams->b64bitBar1 = pGpu->sriovState.b64bitVFBar1; + pParams->b64bitBar2 = pGpu->sriovState.b64bitVFBar2; + pParams->bSriovHeavyEnabled = gpuIsWarBug200577889SriovHeavyEnabled(pGpu); + pParams->bEmulateVFBar0TlbInvalidationRegister = pGpu->getProperty(pGpu, PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE); + pParams->bClientRmAllocatedCtxBuffer = gpuIsClientRmAllocatedCtxBufferEnabled(pGpu); + + return NV_OK; +} + /*! * @brief determines whether this GPU mode needs to be initialized with an offset * to access the registers defined in dev_vm.ref. @@ -87,9 +127,9 @@ static const GPUCHILDPRESENT gpuChildrenPresent_TU102[] = {classId(KernelDisplay), 1}, {classId(VirtMemAllocator), 1}, {classId(OBJDPAUX), 1}, - {classId(OBJFAN), 1}, + {classId(Fan), 1}, {classId(OBJHSHUBMANAGER), 1}, - {classId(OBJHSHUB), 1}, + {classId(Hshub), 1}, {classId(MemorySystem), 1}, {classId(KernelMemorySystem), 1}, {classId(MemoryManager), 1}, @@ -155,9 +195,9 @@ static const GPUCHILDPRESENT gpuChildrenPresent_TU104[] = {classId(KernelDisplay), 1}, {classId(VirtMemAllocator), 1}, {classId(OBJDPAUX), 1}, - {classId(OBJFAN), 1}, + {classId(Fan), 1}, {classId(OBJHSHUBMANAGER), 1}, - {classId(OBJHSHUB), 1}, + {classId(Hshub), 1}, {classId(MemorySystem), 1}, {classId(KernelMemorySystem), 1}, {classId(MemoryManager), 1}, @@ -223,7 +263,7 @@ static const GPUCHILDPRESENT gpuChildrenPresent_TU106[] = {classId(KernelDisplay), 1}, {classId(VirtMemAllocator), 1}, {classId(OBJDPAUX), 1}, - {classId(OBJFAN), 1}, + {classId(Fan), 1}, {classId(MemorySystem), 1}, {classId(KernelMemorySystem), 1}, {classId(MemoryManager), 1}, diff --git a/src/nvidia/src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c b/src/nvidia/src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c index 4512200ee..126f7a2f8 100644 --- a/src/nvidia/src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c +++ b/src/nvidia/src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c @@ -666,7 +666,7 @@ kbifProbePcieReqAtomicCaps_GH100 /*! * @brief Enable PCIe atomics if PCIe hierarchy supports it * - * @param[in] Gpu GPU object pointer + * @param[in] pGpu GPU object pointer */ static void _kbifEnablePcieAtomics_GH100 diff --git a/src/nvidia/src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm107.c b/src/nvidia/src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm107.c index 08e503cd5..08b974659 100644 --- a/src/nvidia/src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm107.c +++ b/src/nvidia/src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm107.c @@ -26,6 +26,7 @@ #include "gpu/gpu.h" #include "gpu/bif/kernel_bif.h" #include "platform/chipset/chipset.h" +#include "nvdevid.h" #include "published/maxwell/gm107/dev_nv_xve.h" diff --git a/src/nvidia/src/kernel/gpu/bif/arch/turing/kernel_bif_tu102.c b/src/nvidia/src/kernel/gpu/bif/arch/turing/kernel_bif_tu102.c index b9c5514c8..0d2e9d2ef 100644 --- a/src/nvidia/src/kernel/gpu/bif/arch/turing/kernel_bif_tu102.c +++ b/src/nvidia/src/kernel/gpu/bif/arch/turing/kernel_bif_tu102.c @@ -26,6 +26,13 @@ #include "gpu/bif/kernel_bif.h" #include "gpu/gpu.h" +#define NV_VGPU_EMU 0x0000FFFF:0x0000F000 /* RW--D */ + +#include "virtualization/kernel_vgpu_mgr.h" +#include "virtualization/hypervisor/hypervisor.h" + +#define NUM_VF_SPARSE_MMAP_REGIONS 2 + #include "published/turing/tu102/dev_nv_xve.h" #include "published/turing/tu102/dev_vm.h" @@ -85,3 +92,137 @@ kbifDisableP2PTransactions_TU102 } } +/*! + * @brief Get the number of sparse mmap regions + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif BIF object pointer + * @param[out] numAreas Number of sparse mmap regions + * + * @returns NV_OK If all args are proper + * NV_ERR_INVALID_ARGUMENT In case of erroneous args + */ + +NV_STATUS +kbifGetNumVFSparseMmapRegions_TU102 +( + OBJGPU *pGpu, + KernelBif *pKernelBif, + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, + NvU32 *numAreas +) +{ + if (numAreas && pKernelHostVgpuDevice != NULL) + { + NvU32 maxInstance = 0; + NV_STATUS status; + + status = kvgpumgrGetMaxInstanceOfVgpu(pKernelHostVgpuDevice->vgpuType, &maxInstance); + if (status != NV_OK) + goto exit; + + if (maxInstance != 1 && pGpu->getProperty(pGpu, PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE)) + *numAreas = NUM_VF_SPARSE_MMAP_REGIONS + 1; // +1 for TLB invalidation + else + *numAreas = NUM_VF_SPARSE_MMAP_REGIONS; + + return NV_OK; + } + +exit: + return NV_ERR_INVALID_ARGUMENT; +} + +NV_STATUS +kbifGetVFSparseMmapRegions_TU102 +( + OBJGPU *pGpu, + KernelBif *pKernelBif, + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, + NvU64 os_page_size, + NvU64 *offsets, + NvU64 *sizes) +{ + NvBool bEmulateVfTlbInvalidation = pGpu->getProperty(pGpu, PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE); + + if (offsets && sizes && pKernelHostVgpuDevice != NULL) + { + NvU32 maxInstance = 0; + NV_STATUS status; + + status = kvgpumgrGetMaxInstanceOfVgpu(pKernelHostVgpuDevice->vgpuType, &maxInstance); + if (status != NV_OK) + return NV_ERR_INVALID_ARGUMENT; + + if (gpuIsWarBug200577889SriovHeavyEnabled(pGpu)) + { + // For SRIOV heavy trap BOOT_* and BAR setup registers in plugin + offsets[0] = 0 + os_page_size; // 0x1000 ==> 0x2FFF + if (maxInstance > 1 && bEmulateVfTlbInvalidation) + { + sizes[0] = NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO(0) - offsets[0]; + } + else + { + sizes[0] = DRF_BASE(NV_VGPU_EMU) - offsets[0]; + } + } + else + { + offsets[0] = 0; // 0x0000 => 0x2FFF + if (maxInstance > 1 && bEmulateVfTlbInvalidation) + { + sizes[0] = NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO(0); + } + else + { + sizes[0] = DRF_BASE(NV_VGPU_EMU); + } + } + + if (hypervisorIsType(OS_HYPERVISOR_HYPERV)) + { + // For Hyperv, we need to mitigate RPC page + if (maxInstance > 1 && bEmulateVfTlbInvalidation) + { + offsets[1] = NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO(0) + os_page_size; // 0x4000 ==> 0xEFFF + sizes[1] = DRF_BASE(NV_VGPU_EMU) - offsets[1]; + + offsets[2] = DRF_BASE(NV_VGPU_EMU) + os_page_size; // 0x10000 ==> 0x40000 + sizes[2] = pGpu->sriovState.vfBarSize[0] - offsets[2]; + } + else + { + offsets[1] = DRF_BASE(NV_VGPU_EMU) + os_page_size; // 0x10000 ==> 0x40000 + sizes[1] = pGpu->sriovState.vfBarSize[0] - offsets[1]; + } + } + else + { + if (maxInstance > 1 && bEmulateVfTlbInvalidation) + { + offsets[1] = NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO(0) + os_page_size; // 0x4000 ==> 0xEFFF + sizes[1] = DRF_BASE(NV_VGPU_EMU) - offsets[1]; + + offsets[2] = NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO(0) + os_page_size; // 0x11000 ==> 0x40000 + sizes[2] = pGpu->sriovState.vfBarSize[0] - offsets[2]; + } + else + { + offsets[1] = NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO(0) + os_page_size; // 0x11000 ==> 0x40000 + sizes[1] = pGpu->sriovState.vfBarSize[0] - offsets[1]; + } + + // Assert whenever the MSI-X table page is not immediately after + // the NV_VGPU_EMU page, as it will break the current assumption. + NV_ASSERT((DRF_BASE(NV_VGPU_EMU) + DRF_SIZE(NV_VGPU_EMU)) == + NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO(0)); + } + } + else + { + return NV_ERR_INVALID_ARGUMENT; + } + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/bif/kernel_bif.c b/src/nvidia/src/kernel/gpu/bif/kernel_bif.c index 9c1f48503..5d2de9ed0 100644 --- a/src/nvidia/src/kernel/gpu/bif/kernel_bif.c +++ b/src/nvidia/src/kernel/gpu/bif/kernel_bif.c @@ -779,7 +779,7 @@ kbifGetGpuLinkControlStatus static NvBool _doesBoardHaveMultipleGpusAndSwitch(OBJGPU *pGpu) { - if (((gpuIsMultiGpuBoard(pGpu, NULL, NULL)) || + if (((gpuIsMultiGpuBoard(pGpu, NULL)) || (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_GEMINI)))&& ((pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_PLX_PRESENT)) || (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_BR03_PRESENT)) || @@ -855,7 +855,12 @@ kbifControlGetPCIEInfo_IMPL else { temp = REF_VAL(NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED, temp); - if (temp == NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_32000MBPS) + if (temp == NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_64000MBPS) + { + data = FLD_SET_DRF(2080, _CTRL_BUS_INFO_PCIE_LINK_CAP, + _CURR_LEVEL, _GEN6, data); + } + else if (temp == NV2080_CTRL_BUS_INFO_PCIE_LINK_CTRL_STATUS_LINK_SPEED_32000MBPS) { data = FLD_SET_DRF(2080, _CTRL_BUS_INFO_PCIE_LINK_CAP, _CURR_LEVEL, _GEN5, data); @@ -892,7 +897,12 @@ kbifControlGetPCIEInfo_IMPL else { temp = REF_VAL(NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED, temp); - if (temp == NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_32000MBPS) + if (temp == NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_64000MBPS) + { + data = FLD_SET_DRF(2080, _CTRL_BUS_INFO_PCIE_LINK_CAP, + _GEN, _GEN6, data); + } + else if (temp == NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_32000MBPS) { data = FLD_SET_DRF(2080, _CTRL_BUS_INFO_PCIE_LINK_CAP, _GEN, _GEN5, data); diff --git a/src/nvidia/src/kernel/gpu/bus/arch/ampere/kern_bus_ga100.c b/src/nvidia/src/kernel/gpu/bus/arch/ampere/kern_bus_ga100.c index 7307650bd..eaa026abb 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/ampere/kern_bus_ga100.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/ampere/kern_bus_ga100.c @@ -39,6 +39,7 @@ #include "mem_mgr/vaspace.h" #include "mem_mgr/fabric_vaspace.h" #include "mem_mgr/virt_mem_mgr.h" +#include #include "published/ampere/ga100/dev_ram.h" // NV_RAMIN_ALLOC_SIZE #include "ctrl/ctrl2080/ctrl2080fla.h" // NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK @@ -46,20 +47,16 @@ #define NVLNK_FABRIC_ADDR_GRANULARITY 36 /*! - * @brief Sets up the FLA state for the GPU. This function will allocate a RM - * client, which will allocate the FERMI_VASPACE_A object, and binds the PDB - * to MMU. + * @brief Sets up the Legacy FLA state for the GPU. This function will allocate a RM + * client, which will allocate the FERMI_VASPACE_A object with LEGACY_FLA flag. * - * @param[in] pGpu - * @param[in] pKernelBus * @param[in] base VASpace base * @param[in] size VASpace size - * * @return NV_OK if successful */ NV_STATUS -kbusAllocateFlaVaspace_GA100 +kbusAllocateLegacyFlaVaspace_GA100 ( OBJGPU *pGpu, KernelBus *pKernelBus, @@ -67,35 +64,13 @@ kbusAllocateFlaVaspace_GA100 NvU64 size ) { - NV_STATUS status = NV_OK; - OBJVMM *pVmm = SYS_GET_VMM(SYS_GET_INSTANCE()); - KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); NV0080_ALLOC_PARAMETERS nv0080AllocParams = {0}; NV2080_ALLOC_PARAMETERS nv2080AllocParams = {0}; NV_VASPACE_ALLOCATION_PARAMETERS vaParams = {0}; - INST_BLK_INIT_PARAMS pInstblkParams = {0}; RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); - RsClient *pClient; NvBool bAcquireLock = NV_FALSE; - - NV_ASSERT_OR_RETURN(pGpu != NULL, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(size != 0, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(!pKernelBus->flaInfo.bFlaAllocated, NV_ERR_INVALID_ARGUMENT); - - pKernelBus->flaInfo.base = base; - pKernelBus->flaInfo.size = size; - - if (gpuIsSriovEnabled(pGpu)) - { - KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); - - if (pKernelNvlink != NULL && - knvlinkIsGpuConnectedToNvswitch(pGpu, pKernelNvlink)) - { - pKernelBus->flaInfo.bFlaRangeRegistered = NV_TRUE; - return status; - } - } + RsClient *pClient; + NV_STATUS status = NV_OK; //Allocate the client in RM which owns the FLAVASpace status = pRmApi->AllocWithHandle(pRmApi, NV01_NULL_OBJECT, NV01_NULL_OBJECT, NV01_NULL_OBJECT, @@ -179,6 +154,78 @@ kbusAllocateFlaVaspace_GA100 goto free_client; } + if (!(IS_VIRTUAL(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu))) + { + // Get the FLA VASpace associated with hFlaVASpace + status = vaspaceGetByHandleOrDeviceDefault(pClient, + pKernelBus->flaInfo.hDevice, + pKernelBus->flaInfo.hFlaVASpace, + &pKernelBus->flaInfo.pFlaVAS); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "failed getting the vaspace from handle, status=0x%x\n", + status); + goto free_client; + } + } + return NV_OK; + +free_client: + pRmApi->Free(pRmApi, pKernelBus->flaInfo.hClient, pKernelBus->flaInfo.hClient); + portMemSet(&pKernelBus->flaInfo, 0, sizeof(pKernelBus->flaInfo)); + + NV_PRINTF(LEVEL_ERROR, "failed allocating FLA VASpace status=0x%x\n", + status); + return status; +} + +/*! + * @brief Sets up the Fabric FLA state for the GPU. This function will allocate fabric VASpace, + * allocates PDB for both legacy and fabric VAS, allocates instance block and initialize with + * legacy VAS and binds the instance block to HW. + * + * @param[in] base VASpace base + * @param[in] size VASpace size + * + * @return NV_OK if successful + */ +NV_STATUS +kbusAllocateFlaVaspace_GA100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + NvU64 base, + NvU64 size +) +{ + NV_STATUS status = NV_OK; + OBJVMM *pVmm = SYS_GET_VMM(SYS_GET_INSTANCE()); + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + INST_BLK_INIT_PARAMS pInstblkParams = {0}; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + NV_ASSERT_OR_RETURN(pGpu != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(size != 0, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(!pKernelBus->flaInfo.bFlaAllocated, NV_ERR_INVALID_ARGUMENT); + + pKernelBus->flaInfo.base = base; + pKernelBus->flaInfo.size = size; + + if (gpuIsSriovEnabled(pGpu)) + { + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + + if (pKernelNvlink != NULL && + knvlinkIsGpuConnectedToNvswitch(pGpu, pKernelNvlink)) + { + pKernelBus->flaInfo.bFlaRangeRegistered = NV_TRUE; + return status; + } + } + + NV_ASSERT_OK_OR_RETURN(kbusAllocateLegacyFlaVaspace_HAL(pGpu, pKernelBus, base, size)); + // Allocate a FABRIC_VASPACE_A object status = vmmCreateVaspace(pVmm, FABRIC_VASPACE_A, pGpu->gpuId, gpumgrGetGpuMask(pGpu), base, base + size - 1, 0, 0, NULL, 0, @@ -198,6 +245,7 @@ kbusAllocateFlaVaspace_GA100 if (IS_VIRTUAL(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu)) { NV2080_CTRL_FLA_RANGE_PARAMS params = {0}; + RsClient *pClient; params.mode = NV2080_CTRL_FLA_RANGE_PARAMS_MODE_HOST_MANAGED_VAS_INITIALIZE; params.base = base; params.size = size; @@ -211,6 +259,8 @@ kbusAllocateFlaVaspace_GA100 goto free_client; } + serverGetClientUnderLock(&g_resServ, pKernelBus->flaInfo.hClient, &pClient); + status = vaspaceGetByHandleOrDeviceDefault(pClient, pKernelBus->flaInfo.hDevice, pKernelBus->flaInfo.hFlaVASpace, @@ -225,19 +275,6 @@ kbusAllocateFlaVaspace_GA100 } else { - // Get the FLA VASpace associated with hFlaVASpace - status = vaspaceGetByHandleOrDeviceDefault(pClient, - pKernelBus->flaInfo.hDevice, - pKernelBus->flaInfo.hFlaVASpace, - &pKernelBus->flaInfo.pFlaVAS); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "failed getting the vaspace from handle, status=0x%x\n", - status); - goto free_client; - } - // Pin the VASPACE page directory for pFlaVAS before writing the instance block status = vaspacePinRootPageDir(pKernelBus->flaInfo.pFlaVAS, pGpu); if (status != NV_OK) @@ -282,7 +319,15 @@ kbusAllocateFlaVaspace_GA100 goto free_instblk; } } - pKernelBus->flaInfo.bFlaAllocated = NV_TRUE; + pKernelBus->flaInfo.bFlaAllocated = NV_TRUE; + pKernelBus->flaInfo.bToggleBindPoint = NV_TRUE; + + if (pGpu->pFabricVAS != NULL) + { + NV_ASSERT_OK_OR_GOTO(status, fabricvaspaceInitUCRange( + dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE), pGpu, + base, size), free_instblk); + } // // For SRIOV PF/VF system, always check for P2P allocation to determine whether @@ -391,7 +436,7 @@ kbusAllocateHostManagedFlaVaspace_GA100 NV_ASSERT_OR_RETURN(pGpu != NULL, NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN(size != 0, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(IS_GFID_VF(pGpu), NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(IS_GFID_VF(gfid), NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN(hClient != NV01_NULL_OBJECT, NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN(hDevice != NV01_NULL_OBJECT, NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN(hSubdevice != NV01_NULL_OBJECT, NV_ERR_INVALID_ARGUMENT); @@ -466,6 +511,14 @@ kbusAllocateHostManagedFlaVaspace_GA100 } pKernelBus->flaInfo.bFlaAllocated = NV_TRUE; + pKernelBus->flaInfo.bToggleBindPoint = NV_TRUE; + + if (pGpu->pFabricVAS != NULL) + { + NV_ASSERT_OK_OR_GOTO(status, fabricvaspaceInitUCRange( + dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE), pGpu, + base, size), free_instblk); + } return status; @@ -495,18 +548,15 @@ cleanup: return status; } -/*! - * @brief Initialize the FLA data structure in OBJGPU +/*! + * Top level function to check if the platform supports FLA, and initialize if + * supported. This function gets called in all the platforms where Nvlink is enabled. * - * @param[in] pGpu - * @param[in] pKernelBus * @param[in] base VASpace base * @param[in] size VASpace size - * - * @return NV_OK if successful */ NV_STATUS -kbusInitFla_GA100 +kbusCheckFlaSupportedAndInit_GA100 ( OBJGPU *pGpu, KernelBus *pKernelBus, @@ -514,12 +564,8 @@ kbusInitFla_GA100 NvU64 size ) { - OBJSYS *pSys = SYS_GET_INSTANCE(); - KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); - NV_STATUS status = NV_OK; - KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); - NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS params; + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); portMemSet(&pKernelBus->flaInfo, 0, sizeof(pKernelBus->flaInfo)); @@ -552,6 +598,37 @@ kbusInitFla_GA100 if (RMCFG_FEATURE_PLATFORM_GSP) return NV_OK; + NV_ASSERT_OK_OR_RETURN(kbusDetermineFlaRangeAndAllocate_HAL(pGpu, pKernelBus, base, size)); + + return NV_OK; +} + +/*! + * @brief Determine FLA Base and Size for NvSwitch Virtualization systems + * from reading the scratch registers. This determines FLA base and size + * GA100 direct connected systems as well as skip allocation of FLA Vaspace + * for vgpu host. + * + * @param[in] base VASpace base + * @param[in] size VASpace size + * + * @return NV_OK if successful + */ +NV_STATUS +kbusDetermineFlaRangeAndAllocate_GA100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + NvU64 base, + NvU64 size +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + NV_STATUS status = NV_OK; + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + + NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS params; + if (pSys->getProperty(pSys, PDB_PROP_SYS_FABRIC_IS_EXTERNALLY_MANAGED)) { // Nvswitch virtualization enabled @@ -628,18 +705,7 @@ kbusDestroyFla_GA100 { if (IS_VIRTUAL(pGpu) || IS_GSP_CLIENT(pGpu)) { - NV_STATUS status = NV_OK; - NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS params = {0}; - - params.flaAction = NV2080_CTRL_FLA_ACTION_UNBIND; - - NV_RM_RPC_CONTROL(pGpu, pKernelBus->flaInfo.hClient, - pKernelBus->flaInfo.hSubDevice, - NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK, - ¶ms, sizeof(params), status); - - NV_ASSERT(status == NV_OK); - pKernelBus->flaInfo.bFlaBind = NV_FALSE; + kbusSetupUnbindFla_HAL(pGpu, pKernelBus); } } @@ -750,8 +816,6 @@ kbusDestroyHostManagedFlaVaspace_GA100 /*! * @brief This function will return the OBJVASPACE for the FLA VAS. * - * @param[in] pGpu - * @param[in] pKernelBus * @param[in/out] ppVAS OBJVASPACE double pointer * * @return NV_ERR_NOT_SUPPORTED, if FLA is not supported, @@ -819,8 +883,6 @@ kbusGetFlaVaspace_GA100 * @brief Constructor for the Instance Memory block for FLA VASpace. This will * allocate the memory descriptor for the IMB. * - * @param[in] pGpu - * @param[in] pKernelBus * * @return NV_OK, if successful */ @@ -876,8 +938,6 @@ kbusConstructFlaInstBlk_GA100 /*! * @brief Destruct the Instance memory block allocated for FLA VAS * - * @param[in] pGpu - * @param[in] pKernelBus */ void kbusDestructFlaInstBlk_GA100 @@ -898,8 +958,6 @@ kbusDestructFlaInstBlk_GA100 /*! * @brief Function to determine if the mapping can be direct mapped or BAR mapped * - * @param[in] pGpu - * @param[in] pKernelBus * @param[in] pMemDesc Memory Descriptor pointer * @param[in] mapFlags Flags used for mapping * @param[in] bDirectSysMappingAllowed boolean to return the result @@ -1061,8 +1119,6 @@ kbusGetNvlinkP2PPeerId_end: * reflected accesses. RM should select direct mapping for any accesses * other than FB * - * @param[in] pGpu - * @param[in] pKernelBus * @param[in] pMemDesc MEMORY_DESCRIPTOR pointer * @param[in/out] pbAllowDirectMap NvBool pointer * @@ -1091,8 +1147,6 @@ kbusUseDirectSysmemMap_GA100 /*! * @brief Validates FLA base address. * - * @param[in] pGpu - * @param[in] pKernelBus * @param flaBaseAddr * * @returns On success, NV_OK. @@ -1141,8 +1195,6 @@ kbusValidateFlaBaseAddress_GA100 * re-spawn at any point later. We don't do any client validation, since FM is * a privileged process managed by sysadmin. * - * @param[in] pGpu - * @param[in] pKernelBus * @param[in] flaBaseAddr NvU64 address * @param[in] flaSize NvU64 Size * @@ -1165,3 +1217,134 @@ kbusValidateFlaBaseAddress_GA100 NV_PRINTF(LEVEL_INFO, "FLA base: %llx, size: %llx is verified \n", flaBaseAddr, flaSize); return NV_TRUE; } + +/*! + * @brief Returns the NvSwitch peer ID + * + * + * @returns NvU32 bus peer number + */ +NvU32 +kbusGetNvSwitchPeerId_GA100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus +) +{ + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + NvU32 peerId = BUS_INVALID_PEER; + NvU32 i; + + if (pKernelNvlink == NULL) + return BUS_INVALID_PEER; + + if (!knvlinkIsGpuConnectedToNvswitch(pGpu, pKernelNvlink)) + return BUS_INVALID_PEER; + + for (i = 0; i < NV_MAX_DEVICES; i++) + { + peerId = pKernelBus->p2p.busNvlinkPeerNumberMask[i]; + + if (peerId == 0) + continue; + + LOWESTBITIDX_32(peerId); + + break; + } + + return peerId; +} + +/*! + * @brief Helper function to extract information from FLA data structure and + * to trigger RPC to Physical RM to BIND FLA VASpace + * + * @param[in] gfid GFID + * + * @return NV_OK if successful + */ +NV_STATUS +kbusSetupBindFla_GA100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + NvU32 gfid +) +{ + NV_STATUS status = NV_OK; + NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS params = {0}; + + if (!gpuIsWarBug200577889SriovHeavyEnabled(pGpu)) + { + MEMORY_DESCRIPTOR *pMemDesc; + RmPhysAddr imbPhysAddr; + NvU32 addrSpace; + + pMemDesc = pKernelBus->flaInfo.pInstblkMemDesc; + imbPhysAddr = memdescGetPhysAddr(pMemDesc, AT_GPU, 0); + addrSpace = memdescGetAddressSpace(pMemDesc); + NV2080_CTRL_FLA_ADDRSPACE paramAddrSpace = NV2080_CTRL_FLA_ADDRSPACE_FBMEM; + + switch(addrSpace) + { + case ADDR_FBMEM: + paramAddrSpace = NV2080_CTRL_FLA_ADDRSPACE_FBMEM; + break; + case ADDR_SYSMEM: + paramAddrSpace = NV2080_CTRL_FLA_ADDRSPACE_SYSMEM; + break; + } + params.imbPhysAddr = imbPhysAddr; + params.addrSpace = paramAddrSpace; + } + params.flaAction = NV2080_CTRL_FLA_ACTION_BIND; + + NV_RM_RPC_CONTROL(pGpu, pKernelBus->flaInfo.hClient, + pKernelBus->flaInfo.hSubDevice, + NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK, + ¶ms, sizeof(params), status); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "FLA bind failed, status: %x \n", status); + return status; + } + + // Since FLA state is tracked in the Guest, Guest RM needs to set it here + pKernelBus->flaInfo.bFlaBind = NV_TRUE; + pKernelBus->bFlaEnabled = NV_TRUE; + + return NV_OK; +} + +/*! + * @brief Helper function to trigger RPC to Physical RM to unbind FLA VASpace + * + * @return NV_OK if successful + */ +NV_STATUS +kbusSetupUnbindFla_GA100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus +) +{ + NV_STATUS status = NV_OK; + NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS params = { 0 }; + + if (!pKernelBus->flaInfo.bFlaBind) + return NV_OK; + + params.flaAction = NV2080_CTRL_FLA_ACTION_UNBIND; + + NV_RM_RPC_CONTROL(pGpu, pKernelBus->flaInfo.hClient, + pKernelBus->flaInfo.hSubDevice, + NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK, + ¶ms, sizeof(params), status); + + pKernelBus->flaInfo.bFlaBind = NV_FALSE; + pKernelBus->bFlaEnabled = NV_FALSE; + + return status; +} diff --git a/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c b/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c index 634f95e02..f44a66db1 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c @@ -23,28 +23,109 @@ #include "core/core.h" #include "gpu/gpu.h" + +#include // FABRIC_VASPACE_A #include "gpu/bus/kern_bus.h" #include "gpu/bus/p2p_api.h" #include "gpu/bif/kernel_bif.h" #include "gpu/mmu/kern_gmmu.h" #include "gpu/mem_mgr/mem_mgr.h" #include "gpu/mem_sys/kern_mem_sys.h" +#include "kernel/gpu/nvlink/kernel_nvlink.h" +#include "mem_mgr/fabric_vaspace.h" +#include "mem_mgr/virt_mem_mgr.h" +#include "vgpu/rpc.h" +#include "virtualization/hypervisor/hypervisor.h" #include "os/os.h" +#include "mem_mgr/mem_multicast_fabric.h" + +#include "gpu/gpu_fabric_probe.h" #include "published/hopper/gh100/dev_ram.h" #include "published/hopper/gh100/pri_nv_xal_ep.h" #include "published/hopper/gh100/pri_nv_xal_ep_p2p.h" #include "published/hopper/gh100/dev_vm.h" #include "published/hopper/gh100/dev_mmu.h" +#include "ctrl/ctrl2080/ctrl2080fla.h" // NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK #include "nvRmReg.h" // Defines for P2P #define HOPPER_WRITE_MAILBOX_SIZE ((NvU64)64 * 1024) -#define HOPPER_MAX_WRITE_MAILBOX_ADDR \ - ((HOPPER_WRITE_MAILBOX_SIZE << DRF_SIZE(NV_XAL_EP_P2P_WMBOX_ADDR_ADDR)) - \ +#define HOPPER_MAX_WRITE_MAILBOX_ADDR(pGpu) \ + ((HOPPER_WRITE_MAILBOX_SIZE << kbusGetP2PWriteMailboxAddressSize_HAL(pGpu)) - \ HOPPER_WRITE_MAILBOX_SIZE) +/*! + * @brief Gets the P2P write mailbox address size (NV_XAL_EP_P2P_WMBOX_ADDR_ADDR) + * + * @returns P2P write mailbox address size (NV_XAL_EP_P2P_WMBOX_ADDR_ADDR) + */ +NvU32 +kbusGetP2PWriteMailboxAddressSize_GH100(OBJGPU *pGpu) +{ + return DRF_SIZE(NV_XAL_EP_P2P_WMBOX_ADDR_ADDR); +} + +/*! + * @brief Writes NV_XAL_EP_BAR0_WINDOW_BASE + * + * @param[in] pGpu + * @param[in] pKernelBus + * @param[in] base base address to write + * + * @returns NV_OK + */ +NV_STATUS +kbusWriteBAR0WindowBase_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + NvU32 base +) +{ + GPU_FLD_WR_DRF_NUM(pGpu, _XAL_EP, _BAR0_WINDOW, _BASE, base); + return NV_OK; +} + +/*! + * @brief Reads NV_XAL_EP_BAR0_WINDOW_BASE + * + * @param[in] pGpu + * @param[in] pKernelBus + * + * @returns Contents of NV_XAL_EP_BAR0_WINDOW_BASE + */ +NvU32 +kbusReadBAR0WindowBase_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus +) +{ + return GPU_REG_RD_DRF(pGpu, _XAL_EP, _BAR0_WINDOW, _BASE); +} + +/*! + * @brief Validates that the given base fits within the width of the window base + * + * @param[in] pGpu + * @param[in] pKernelBus + * @param[in] base base offset to validate + * + * @returns Whether given base fits within the width of the window base. + */ +NvBool +kbusValidateBAR0WindowBase_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + NvU32 base +) +{ + return base <= DRF_MASK(NV_XAL_EP_BAR0_WINDOW_BASE); +} + NV_STATUS kbusSetBAR0WindowVidOffset_GH100 ( @@ -55,7 +136,7 @@ kbusSetBAR0WindowVidOffset_GH100 { NV_ASSERT((vidOffset & 0xffff)==0); - NV_ASSERT((vidOffset >> NV_XAL_EP_BAR0_WINDOW_BASE_SHIFT) <= DRF_MASK(NV_XAL_EP_BAR0_WINDOW_BASE)); + NV_ASSERT(kbusValidateBAR0WindowBase_HAL(pGpu, pKernelBus, vidOffset >> NV_XAL_EP_BAR0_WINDOW_BASE_SHIFT)); // // RM initialises cachedBar0WindowVidOffset with 0. Refresh its value with @@ -63,7 +144,7 @@ kbusSetBAR0WindowVidOffset_GH100 // if (pKernelBus->cachedBar0WindowVidOffset == 0) { - pKernelBus->cachedBar0WindowVidOffset = ((NvU64) GPU_REG_RD_DRF(pGpu, _XAL_EP, _BAR0_WINDOW, _BASE)) + pKernelBus->cachedBar0WindowVidOffset = ((NvU64) kbusReadBAR0WindowBase_HAL(pGpu, pKernelBus)) << NV_XAL_EP_BAR0_WINDOW_BASE_SHIFT; } @@ -75,7 +156,7 @@ kbusSetBAR0WindowVidOffset_GH100 NvU64_HI32(vidOffset), NvU64_LO32(vidOffset)); // _BAR0_WINDOW_TARGET field is removed. It's always VIDMEM - GPU_FLD_WR_DRF_NUM(pGpu, _XAL_EP, _BAR0_WINDOW, _BASE, NvU64_LO32(vidOffset >> 16)); + kbusWriteBAR0WindowBase_HAL(pGpu, pKernelBus, NvU64_LO32(vidOffset >> 16)); pKernelBus->cachedBar0WindowVidOffset = vidOffset; } @@ -98,7 +179,7 @@ kbusGetBAR0WindowVidOffset_GH100 // if (pKernelBus->cachedBar0WindowVidOffset == 0) { - pKernelBus->cachedBar0WindowVidOffset = ((NvU64) GPU_REG_RD_DRF(pGpu, _XAL_EP, _BAR0_WINDOW, _BASE)) + pKernelBus->cachedBar0WindowVidOffset = ((NvU64) kbusReadBAR0WindowBase_HAL(pGpu, pKernelBus)) << NV_XAL_EP_BAR0_WINDOW_BASE_SHIFT; } @@ -150,6 +231,8 @@ kbusVerifyBar2_GH100 NvU32 flagsClean = 0; NvU64 bar2VirtualAddr = 0; + NV_ASSERT_OR_RETURN(pGpu->getProperty(pGPU, PDB_PROP_GPU_COHERENT_CPU_MAPPING) == NV_FALSE, NV_ERR_INVALID_STATE); + // // kbusVerifyBar2 will test BAR0 against sysmem on Tegra; otherwise skip // the test if inst_in_sys is used @@ -244,7 +327,7 @@ kbusVerifyBar2_GH100 bar0Window = kbusGetBAR0WindowVidOffset_HAL(pGpu, pKernelBus); bar0TestAddr = memdescGetPhysAddr(pMemDesc, AT_GPU, 0); - GPU_FLD_WR_DRF_NUM(pGpu, _XAL_EP, _BAR0_WINDOW, _BASE, NvU64_LO32(bar0TestAddr >> 16)); + kbusWriteBAR0WindowBase_HAL(pGpu, pKernelBus, NvU64_LO32(bar0TestAddr >> 16)); testData = GPU_REG_RD32(pGpu, DRF_BASE(NV_PRAMIN) + NvU64_LO32(bar0TestAddr & 0xffff)); @@ -301,7 +384,7 @@ kbusVerifyBar2_GH100 "Bar0 window tests successfully\n"); GPU_REG_WR32(pGpu, DRF_BASE(NV_PRAMIN) + NvU64_LO32(bar0TestAddr & 0xffff), testData); - GPU_FLD_WR_DRF_NUM(pGpu, _XAL_EP, _BAR0_WINDOW, _BASE, NvU64_LO32(bar0Window >> 16)); + kbusWriteBAR0WindowBase_HAL(pGpu, pKernelBus, NvU64_LO32(bar0Window >> 16)); // ========================================================== // Does MMU's translation logic work? @@ -365,7 +448,7 @@ kbusVerifyBar2_GH100 // Readback through the bar0 window bar0Window = kbusGetBAR0WindowVidOffset_HAL(pGpu, pKernelBus); - GPU_FLD_WR_DRF_NUM(pGpu, _XAL_EP, _BAR0_WINDOW, _BASE, NvU64_LO32(testMemoryOffset >> 16)); + kbusWriteBAR0WindowBase_HAL(pGpu, pKernelBus, NvU64_LO32(testMemoryOffset >> 16)); NV_PRINTF(LEVEL_INFO, "bar0Window = 0x%llx, testMemoryOffset = 0x%llx, testAddrSpace = %d, " @@ -395,7 +478,7 @@ kbusVerifyBar2_GH100 GPU_REG_WR32(pGpu, temp + index, SAMPLEDATA + 0x10); } - GPU_FLD_WR_DRF_NUM(pGpu, _XAL_EP, _BAR0_WINDOW, _BASE, NvU64_LO32(bar0Window >> 16)); + kbusWriteBAR0WindowBase_HAL(pGpu, pKernelBus, NvU64_LO32(bar0Window >> 16)); status = kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY | BUS_FLUSH_USE_PCIE_READ); @@ -585,7 +668,7 @@ kbusGetP2PMailboxAttributes_GH100 { *pMailboxBar1MaxOffset64KB = NvU64_LO32( - (HOPPER_MAX_WRITE_MAILBOX_ADDR + HOPPER_WRITE_MAILBOX_SIZE) >> 16 + (HOPPER_MAX_WRITE_MAILBOX_ADDR(pGpu) + HOPPER_WRITE_MAILBOX_SIZE) >> 16 ); } @@ -822,8 +905,15 @@ kbusCreateP2PMappingForBar1P2P_GH100 NvU32 gpuInst0 = gpuGetInstance(pGpu0); NvU32 gpuInst1 = gpuGetInstance(pGpu1); - if (!kbusIsPcieBar1P2PMappingSupported_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1)) + if (IS_VIRTUAL(pGpu0) || IS_VIRTUAL(pGpu1)) + { return NV_ERR_NOT_SUPPORTED; + } + + if (!kbusIsPcieBar1P2PMappingSupported_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1)) + { + return NV_ERR_NOT_SUPPORTED; + } pKernelBus0->p2pPcieBar1.busBar1PeerRefcount[gpuInst1]++; pKernelBus1->p2pPcieBar1.busBar1PeerRefcount[gpuInst0]++; @@ -857,6 +947,11 @@ kbusRemoveP2PMappingForBar1P2P_GH100 { NvU32 gpuInst0, gpuInst1; + if (IS_VIRTUAL(pGpu0) || IS_VIRTUAL(pGpu1)) + { + return NV_ERR_NOT_SUPPORTED; + } + gpuInst0 = gpuGetInstance(pGpu0); gpuInst1 = gpuGetInstance(pGpu1); @@ -982,6 +1077,11 @@ kbusCreateP2PMappingForC2C_GH100 NvU32 c2cPeer1; NV_STATUS status; + if (IS_VIRTUAL(pGpu0) || IS_VIRTUAL(pGpu1)) + { + return NV_ERR_NOT_SUPPORTED; + } + if (peer0 == NULL || peer1 == NULL) { return NV_ERR_INVALID_ARGUMENT; @@ -1083,6 +1183,12 @@ _kbusRemoveC2CPeerMapping ) { NV_STATUS status = NV_OK; + + if (IS_VIRTUAL(pGpu0) || IS_VIRTUAL(pGpu1)) + { + return NV_ERR_NOT_SUPPORTED; + } + return status; } @@ -1141,3 +1247,351 @@ kbusWriteP2PWmbTag_GH100 GPU_REG_WR32(pGpu, NV_XAL_EP_P2P_WREQMB_H(remote2Local), NvU64_HI32(p2pWmbTag)); } +/*! + * @brief Determine FLA Base and Size for direct-connected and NvSwitch systems. + * + * @param[in] base VASpace base + * @param[in] size VASpace size + * + * @return NV_OK if successful + */ +NV_STATUS +kbusDetermineFlaRangeAndAllocate_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + NvU64 base, + NvU64 size +) +{ + NV_STATUS status = NV_OK; + + OBJSYS *pSys = SYS_GET_INSTANCE(); + + if ((pSys->getProperty(pSys, PDB_PROP_SYS_NVSWITCH_IS_PRESENT) || + GPU_IS_NVSWITCH_DETECTED(pGpu)) && !gpuFabricProbeIsSupported(pGpu)) + { + return kbusDetermineFlaRangeAndAllocate_GA100(pGpu, pKernelBus, base, size); + } + + NV_ASSERT_OK_OR_RETURN(kbusAllocateFlaVaspace_HAL(pGpu, pKernelBus, 0x0, NVBIT64(52))); + + return status; +} + +/*! + * @brief Sets up the Fabric FLA state for the GPU. This function will allocate fabric VASpace, + * allocates PDB for fabric VAS, allocates instance block and initialize with + * fabric VAS and binds the instance block to HW. + * + * @param[in] base VASpace base + * @param[in] size VASpace size + * + * @return NV_OK if successful + */ +NV_STATUS +kbusAllocateFlaVaspace_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + NvU64 base, + NvU64 size +) +{ + NV_STATUS status = NV_OK; + OBJVMM *pVmm = SYS_GET_VMM(SYS_GET_INSTANCE()); + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + INST_BLK_INIT_PARAMS pInstblkParams = {0}; + FABRIC_VASPACE *pFabricVAS; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + NV_ASSERT_OR_RETURN(pGpu != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(size != 0, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(!pKernelBus->flaInfo.bFlaAllocated, NV_ERR_INVALID_ARGUMENT); + + pKernelBus->flaInfo.base = base; + pKernelBus->flaInfo.size = size; + + OBJSYS *pSys = SYS_GET_INSTANCE(); + + if ((pSys->getProperty(pSys, PDB_PROP_SYS_NVSWITCH_IS_PRESENT) || + GPU_IS_NVSWITCH_DETECTED(pGpu)) && !gpuFabricProbeIsSupported(pGpu)) + { + return kbusAllocateFlaVaspace_GA100(pGpu, pKernelBus, base, size); + } + + // TODO: Remove allocating legaccy FLA Vaspace once CUDA removes the dependency + NV_ASSERT_OK_OR_RETURN(kbusAllocateLegacyFlaVaspace_HAL(pGpu, pKernelBus, base, size)); + + // Allocate a FABRIC_VASPACE_A object + status = vmmCreateVaspace(pVmm, FABRIC_VASPACE_A, pGpu->gpuId, gpumgrGetGpuMask(pGpu), + base, base + size - 1, 0, 0, NULL, 0, + &pGpu->pFabricVAS); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "failed allocating fabric vaspace, status=0x%x\n", + status); + goto cleanup; + } + + // Pin the VASPACE page directory for pFabricVAS before writing the instance block + status = vaspacePinRootPageDir(pGpu->pFabricVAS, pGpu); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "failed pinning down fabric vaspace, status=0x%x\n", + status); + goto cleanup; + } + + // Construct instance block + status = kbusConstructFlaInstBlk_HAL(pGpu, pKernelBus, GPU_GFID_PF); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "failed constructing instblk for FLA, status=0x%x\n", + status); + goto unpin_rootpagedir; + } + + pFabricVAS = dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); + + // Instantiate Inst Blk for pFlaVAS + status = kgmmuInstBlkInit(pKernelGmmu, + pKernelBus->flaInfo.pInstblkMemDesc, + pFabricVAS->pGVAS, FIFO_PDB_IDX_BASE, + &pInstblkParams); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "failed instantiating instblk for FLA, status=0x%x\n", + status); + goto free_instblk; + } + + // + // For SRIOV PF/VF system, always check for P2P allocation to determine whether + // this function is allowed to bind FLA + // + if (gpuIsSriovEnabled(pGpu) || IS_VIRTUAL(pGpu)) + { + if (gpuCheckIsP2PAllocated_HAL(pGpu)) + { + status = kbusSetupBindFla(pGpu, pKernelBus, pGpu->sriovState.pP2PInfo->gfid); + } + else + { + NV_PRINTF(LEVEL_INFO, "Skipping binding FLA, because no P2P GFID is" + " validated yet\n"); + } + } + else + { + status = kbusSetupBindFla(pGpu, pKernelBus, GPU_GFID_PF); + } + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "failed binding instblk for FLA, status=0x%x\n", status); + goto free_instblk; + } + if (GPU_GET_KERNEL_NVLINK(pGpu) != NULL) + { + NVLINK_INBAND_MSG_CALLBACK inbandMsgCbParams; + + inbandMsgCbParams.messageType = NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_RSP; + inbandMsgCbParams.pCallback = &memorymulticastfabricTeamSetupResponseCallback; + + // + // Update this such that it indicates that Gpu lock shouldn't be taken + // when the callback is invoked + // + inbandMsgCbParams.wqItemFlags = 0; + + status = knvlinkRegisterInbandCallback(pGpu, + GPU_GET_KERNEL_NVLINK(pGpu), + &inbandMsgCbParams); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "GPU (ID: %d) Registering Inband Cb failed\n", + gpuGetInstance(pGpu)); + goto free_instblk; + } + + } + + // setup Unicast FLA range in Fabric VAS object + if (!GPU_IS_NVSWITCH_DETECTED(pGpu)) + { + size = gpuGetFlaVasSize_HAL(pGpu, NV_FALSE); + base = pGpu->gpuInstance * size; + + NV_ASSERT_OK_OR_GOTO(status, fabricvaspaceInitUCRange( + dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE), pGpu, + base, size), free_instblk); + } + + pKernelBus->flaInfo.bFlaAllocated = NV_TRUE; + + return NV_OK; + +free_instblk: + kbusDestructFlaInstBlk_HAL(pGpu, pKernelBus); + +unpin_rootpagedir: + if (pGpu->pFabricVAS != NULL) + { + vaspaceUnpinRootPageDir(pGpu->pFabricVAS, pGpu); + } + +cleanup: + if (pGpu->pFabricVAS != NULL) + { + vmmDestroyVaspace(pVmm, pGpu->pFabricVAS); + pGpu->pFabricVAS = NULL; + } + + // TODO: remove this once legacy FLA VAS support is removed. + pRmApi->Free(pRmApi, pKernelBus->flaInfo.hClient, pKernelBus->flaInfo.hClient); + + pKernelBus->flaInfo.bFlaAllocated = NV_FALSE; + + NV_PRINTF(LEVEL_ERROR, "failed allocating FLA VASpace status=0x%x\n", + status); + + return status; +} + +void +kbusDestroyFla_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJVMM *pVmm = SYS_GET_VMM(pSys); + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + if (pGpu->pFabricVAS != NULL) + { + if (pKernelBus->flaInfo.bFlaBind) + { + if (IS_VIRTUAL(pGpu) || IS_GSP_CLIENT(pGpu)) + { + kbusSetupUnbindFla_HAL(pGpu, pKernelBus); + } + } + + if (pKernelBus->flaInfo.bFlaAllocated) + { + vaspaceUnpinRootPageDir(pGpu->pFabricVAS, pGpu);\ + kbusDestructFlaInstBlk_HAL(pGpu, pKernelBus); + vmmDestroyVaspace(pVmm, pGpu->pFabricVAS); + + pGpu->pFabricVAS = NULL; + // TODO: Remove this once legacy FLA VAS support is deprecated + pRmApi->Free(pRmApi, pKernelBus->flaInfo.hClient, pKernelBus->flaInfo.hClient); + portMemSet(&pKernelBus->flaInfo, 0, sizeof(pKernelBus->flaInfo)); + if (GPU_GET_KERNEL_NVLINK(pGpu) != NULL) + { + // Unregister the receive callback + NV_ASSERT_OK(knvlinkUnregisterInbandCallback(pGpu, GPU_GET_KERNEL_NVLINK(pGpu), + NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_RSP)); + } + } + } +} + +/*! + * @brief Helper function to extract information from FLA data structure and + * to trigger RPC to Physical RM to BIND FLA VASpace + * + * @param[in] gfid GFID + * + * @return NV_OK if successful + */ +NV_STATUS +kbusSetupBindFla_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + NvU32 gfid +) +{ + NV_STATUS status = NV_OK; + NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS params = {0}; + MEMORY_DESCRIPTOR *pMemDesc; + RM_API *pRmApi = IS_GSP_CLIENT(pGpu) ? GPU_GET_PHYSICAL_RMAPI(pGpu) + : rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + pMemDesc = pKernelBus->flaInfo.pInstblkMemDesc; + + switch( memdescGetAddressSpace(pMemDesc)) + { + case ADDR_FBMEM: + params.addrSpace = NV2080_CTRL_FLA_ADDRSPACE_FBMEM; + break; + case ADDR_SYSMEM: + params.addrSpace = NV2080_CTRL_FLA_ADDRSPACE_SYSMEM; + break; + } + params.imbPhysAddr = memdescGetPhysAddr(pMemDesc, AT_GPU, 0); + params.flaAction = NV2080_CTRL_FLA_ACTION_BIND; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK, + ¶ms, + sizeof(params)); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "FLA bind failed, status: %x \n", status); + return status; + } + + // Since FLA state is tracked in the Guest, Guest RM needs to set it here + pKernelBus->flaInfo.bFlaBind = NV_TRUE; + pKernelBus->bFlaEnabled = NV_TRUE; + + return status; +} + +/*! + * @brief Helper function to trigger RPC to Physical RM to unbind FLA VASpace + * + * @return NV_OK if successful + */ +NV_STATUS +kbusSetupUnbindFla_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus +) +{ + NV_STATUS status = NV_OK; + NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS params = { 0 }; + RM_API *pRmApi = IS_GSP_CLIENT(pGpu) ? GPU_GET_PHYSICAL_RMAPI(pGpu) + : rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + if (!pKernelBus->flaInfo.bFlaBind) + return NV_OK; + + params.flaAction = NV2080_CTRL_FLA_ACTION_UNBIND; + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK, + ¶ms, + sizeof(params)); + + pKernelBus->flaInfo.bFlaBind = NV_FALSE; + pKernelBus->bFlaEnabled = NV_FALSE; + + return status; +} + diff --git a/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c b/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c index 2b8ddb65b..26ac0d909 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c @@ -291,8 +291,11 @@ kbusStateInitLockedKernel_GM107 // NV_ASSERT_OK_OR_RETURN(kbusInitBar2_HAL(pGpu, pKernelBus, GPU_GFID_PF)); - // Verify that BAR2 and the MMU actually works - (void) kbusVerifyBar2_HAL(pGpu, pKernelBus, NULL, NULL, 0, 0); + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING)) + { + // Verify that BAR2 and the MMU actually works + NV_ASSERT_OK_OR_RETURN(kbusVerifyBar2_HAL(pGpu, pKernelBus, NULL, NULL, 0, 0)); + } if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && IS_VIRTUAL_WITH_SRIOV(pGpu)) { @@ -333,6 +336,61 @@ kbusStateInitLocked_IMPL(OBJGPU *pGpu, KernelBus *pKernelBus) return NV_OK; } +NV_STATUS +kbusStateLoad_GM107 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + NvU32 flags +) +{ + + if (flags & GPU_STATE_FLAGS_PRESERVING) + { + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + // FB address space may not be available on Tegra (see fbInitFbRegions) + if (pMemoryManager->Ram.fbAddrSpaceSizeMb != 0) + { + // Bind the BAR0 window to its default location + // note: we can't move the window for all intents and purposes since VBIOS + // will also use the window at arbitrary locations (eg during an SMI event + NvU64 offsetBar0 = (pMemoryManager->Ram.fbAddrSpaceSizeMb << 20) - DRF_SIZE(NV_PRAMIN); + kbusSetBAR0WindowVidOffset_HAL(pGpu, pKernelBus, offsetBar0); + } + else + { + NV_ASSERT(IsTEGRA(pGpu)); + } + + if (!(flags & GPU_STATE_FLAGS_GC6_TRANSITION)) + { + if (NULL == pKernelBus->virtualBar2[GPU_GFID_PF].pCpuMapping) + { + NV_ASSERT_OK_OR_RETURN(kbusSetupBar2CpuAperture_HAL(pGpu, pKernelBus, GPU_GFID_PF)); + } + } + NV_ASSERT_OK_OR_RETURN(kbusCommitBar2_HAL(pGpu, pKernelBus, flags)); + + // + // If we are exiting GC6 and the SKIP_BAR2_TEST_GC6 is set for the + // chip, then don't verify BAR2. The time taken to verify causes a + // a hit on the GC6 exit times, so this verif only feature does not + // come for free. + // + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING) && + !(IS_GPU_GC6_STATE_EXITING(pGpu) && pKernelBus->bSkipBar2TestOnGc6Exit)) + { + // Verify that BAR2 and the MMU actually works + NV_ASSERT_OK_OR_RETURN(kbusVerifyBar2_HAL(pGpu, pKernelBus, NULL, NULL, 0, 0)); + + // Fail to set this status meaning kbusVerifyBar2_HAL() failed + } + } + + return NV_OK; +} + NV_STATUS kbusStatePostLoad_GM107 ( @@ -495,7 +553,7 @@ kbusInitBar1_GM107(OBJGPU *pGpu, KernelBus *pKernelBus, NvU32 gfid) vaflags |= VASPACE_FLAGS_ALLOW_ZERO_ADDRESS; // BAR1 requires a zero VAS base. vaflags |= VASPACE_FLAGS_ENABLE_VMM; -#if defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS) +#if defined(DEVELOP) || defined(DEBUG) || RMCFG_FEATURE_MODS_FEATURES { NvU32 data32 = 0; // @@ -521,7 +579,7 @@ kbusInitBar1_GM107(OBJGPU *pGpu, KernelBus *pKernelBus, NvU32 gfid) } } } -#endif // defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS) +#endif // defined(DEVELOP) || defined(DEBUG) || RMCFG_FEATURE_MODS_FEATURES switch (vaSpaceBigPageSize) { @@ -1365,6 +1423,8 @@ kbusSetupBar2GpuVaSpace_GM107 userCtx.pGpu = pGpu; userCtx.gfid = gfid; + NV_ASSERT_OR_RETURN(pWalk != NULL, NV_ERR_INVALID_STATE); + // Pre-reserve and init 4K tables through BAR0 window (bBootstrap) mode. mmuWalkSetUserCtx(pWalk, &userCtx); @@ -2251,6 +2311,34 @@ OBJVASPACE *kbusGetBar1VASpace_GM107(OBJGPU *pGpu, KernelBus *pKernelBus) return pKernelBus->bar1[gfid].pVAS; } +static NV_STATUS +_kbusUpdateDebugStatistics(OBJGPU *pGpu) +{ + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + OBJVASPACE *pBar1VAS = kbusGetBar1VASpace_HAL(pGpu, pKernelBus); + OBJEHEAP *pVASHeap; + NV00DE_SHARED_DATA *pSharedData = gpushareddataWriteStart(pGpu); + NV_RANGE bar1VARange = NV_RANGE_EMPTY; + + pVASHeap = vaspaceGetHeap(pBar1VAS); + bar1VARange = rangeMake(vaspaceGetVaStart(pBar1VAS), vaspaceGetVaLimit(pBar1VAS)); + + pSharedData->bar1Size = (NvU32)(rangeLength(bar1VARange) / 1024); + pSharedData->bar1AvailSize = 0; + + if (pVASHeap != NULL) + { + NvU64 freeSize = 0; + + pVASHeap->eheapInfoForRange(pVASHeap, bar1VARange, NULL, NULL, NULL, &freeSize); + pSharedData->bar1AvailSize = (NvU32)(freeSize / 1024); + } + + gpushareddataWriteFinish(pGpu); + + return NV_OK; +} + NV_STATUS kbusMapFbAperture_GM107 ( @@ -2333,6 +2421,7 @@ kbusMapFbAperture_GM107 if (rmStatus == NV_OK) { + _kbusUpdateDebugStatistics(pGpu); return rmStatus; } @@ -2418,6 +2507,8 @@ kbusUnmapFbAperture_GM107 } SLI_LOOP_END + _kbusUpdateDebugStatistics(pGpu); + if (rmStatus == NV_OK) { NV_PRINTF(LEVEL_INFO, @@ -3131,7 +3222,8 @@ kbusGetSizeOfBar2PageTables_GM107 } // Get the @ref GMMU_FMT for this chip - NV_ASSERT_OR_RETURN(NULL != (pFmt = kgmmuFmtGet(pKernelGmmu, GMMU_FMT_VERSION_DEFAULT, 0)), 0); + pFmt = kgmmuFmtGet(pKernelGmmu, GMMU_FMT_VERSION_DEFAULT, 0); + NV_ASSERT_OR_RETURN(NULL != pFmt, 0); // Get 4K page size Page Table pPgTbl = mmuFmtFindLevelWithPageShift(pFmt->pRoot, RM_PAGE_SHIFT); @@ -3594,7 +3686,7 @@ NV_STATUS kbusSetBarsApertureSize_GM107 // keep the code path the same for emulation. With a 8MB BAR2 we do // not expect instance memory to evict a cached mapping. // - if ((IS_SIM_MODS(GPU_GET_OS(pGpu)) && IS_SILICON(pGpu) == 0) || (!RMCFG_FEATURE_PLATFORM_MODS && IS_SIMULATION(pGpu))) + if ((IS_SIM_MODS(GPU_GET_OS(pGpu)) && IS_SILICON(pGpu) == 0) || (!RMCFG_FEATURE_MODS_FEATURES && IS_SIMULATION(pGpu))) { pKernelBus->bar2[gfid].rmApertureLimit = ((BUS_BAR2_RM_APERTURE_MB >> 1) << 20) - 1; // 8MB pKernelBus->bar2[gfid].cpuVisibleLimit = pKernelBus->bar2[gfid].rmApertureLimit; // No VESA space @@ -3677,7 +3769,8 @@ NvU32 kbusGetSizeOfBar2PageDirs_GM107 } // Get the @ref GMMU_FMT for this chip - NV_ASSERT_OR_RETURN(NULL != (pFmt = kgmmuFmtGet(pKernelGmmu, GMMU_FMT_VERSION_DEFAULT, 0)), 0); + pFmt = kgmmuFmtGet(pKernelGmmu, GMMU_FMT_VERSION_DEFAULT, 0); + NV_ASSERT_OR_RETURN(NULL != pFmt, 0); pLevel = pFmt->pRoot; // Cache the size of the root Page Dir, once. diff --git a/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm200.c b/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm200.c index a13f56a74..9a7f381b5 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm200.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm200.c @@ -212,17 +212,11 @@ kbusDestroyPeerAccess_GM200 NvU32 peerNum ) { - if (pKernelBus->p2pPcie.busPeer[peerNum].pRemoteWMBoxMemDesc != NULL) - { - memdescDestroy(pKernelBus->p2pPcie.busPeer[peerNum].pRemoteWMBoxMemDesc); - pKernelBus->p2pPcie.busPeer[peerNum].pRemoteWMBoxMemDesc = NULL; - } + memdescDestroy(pKernelBus->p2pPcie.busPeer[peerNum].pRemoteWMBoxMemDesc); + pKernelBus->p2pPcie.busPeer[peerNum].pRemoteWMBoxMemDesc = NULL; - if (pKernelBus->p2pPcie.busPeer[peerNum].pRemoteP2PDomMemDesc != NULL) - { - memdescDestroy(pKernelBus->p2pPcie.busPeer[peerNum].pRemoteP2PDomMemDesc); - pKernelBus->p2pPcie.busPeer[peerNum].pRemoteP2PDomMemDesc = NULL; - } + memdescDestroy(pKernelBus->p2pPcie.busPeer[peerNum].pRemoteP2PDomMemDesc); + pKernelBus->p2pPcie.busPeer[peerNum].pRemoteP2PDomMemDesc = NULL; } /*! @@ -362,6 +356,11 @@ kbusCreateP2PMappingForMailbox_GM200 NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS params; NvU32 gpuInst0, gpuInst1; + if (IS_VIRTUAL(pGpu0) || IS_VIRTUAL(pGpu1)) + { + return NV_ERR_NOT_SUPPORTED; + } + if (peer0 == NULL || peer1 == NULL) { return NV_ERR_INVALID_ARGUMENT; @@ -669,6 +668,11 @@ kbusRemoveP2PMappingForMailbox_GM200 NvU32 gpuInst0 = gpuGetInstance(pGpu0); NvU32 gpuInst1 = gpuGetInstance(pGpu1); + if (IS_VIRTUAL(pGpu0) || IS_VIRTUAL(pGpu1)) + { + return NV_ERR_NOT_SUPPORTED; + } + // a non-existent mapping if(peer0 == BUS_INVALID_PEER || peer1 == BUS_INVALID_PEER) diff --git a/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c b/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c index 6ce1d6306..7c88800ad 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c @@ -69,6 +69,111 @@ kbusCreateP2PMapping_GP100 return NV_ERR_NOT_SUPPORTED; } +// Grab GPU locks before RPCing into GSP-RM for NVLink RPCs +static NV_STATUS +_kbusExecGspRmRpcForNvlink +( + OBJGPU *pGpu, + NvU32 cmd, + void *paramAddr, + NvU32 paramSize +) +{ + NvU32 gpuMaskRelease = 0; + NvU32 gpuMaskInitial = rmGpuLocksGetOwnedMask(); + NvU32 gpuMask = gpuMaskInitial | NVBIT(pGpu->gpuInstance); + NV_STATUS status = NV_OK; + + // + // XXX Bug 1795328: Fix P2P path to acquire locks for the GPU + // Due to platform differences in the P2P path, the GPU lock is not + // consistently held at this point in the call stack. This function + // requires exclusive access to RM/PMU data structures to update HSHUB, + // and therefore requires the GPU lock to be held at this point. + // This check should be removed once the P2P paths have been updated to + // acquire the GPU locks consistently for all platforms. + // + if (IS_GSP_CLIENT(pGpu)) + { + if (!rmGpuGroupLockIsOwner(pGpu->gpuInstance, GPU_LOCK_GRP_MASK, &gpuMask)) + { + status = rmGpuGroupLockAcquire(pGpu->gpuInstance, + GPU_LOCK_GRP_MASK, + GPU_LOCK_FLAGS_SAFE_LOCK_UPGRADE, + RM_LOCK_MODULES_NVLINK, + &gpuMask); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to acquire locks for gpumask 0x%x\n", gpuMask); + return status; + } + + gpuMaskRelease = (gpuMask & (~gpuMaskInitial)); + } + } + + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + cmd, paramAddr, paramSize); + if (gpuMaskRelease) + { + rmGpuGroupLockRelease(gpuMaskRelease, GPUS_LOCK_FLAGS_NONE); + } + + return status; +} + +/*! + * @brief Create NVLink mapping to a given peer GPU + * + * @param[in] pGpu0 (Local) + * @param[in] pKernelBus0 (Local) + * @param[in] pGpu1 (Remote) + * @param[in] peerId peerID + * @param[in] attributes P2PApi attributes + * + * return NV_OK on success + */ +static NV_STATUS +_kbusCreateNvlinkPeerMapping +( + OBJGPU *pGpu0, + KernelBus *pKernelBus0, + OBJGPU *pGpu1, + NvU32 peerId, + NvU32 attributes +) +{ + NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS params; + NV_STATUS status = NV_OK; + OBJSYS *pSys = SYS_GET_INSTANCE(); + + NV_ASSERT_OK_OR_RETURN(osAcquireRmSema(pSys->pSema)); + + portMemSet(¶ms, 0, sizeof(params)); + params.connectionType = NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_NVLINK; + params.peerId = peerId; + params.bUseUuid = NV_FALSE; + params.remoteGpuId = pGpu1->gpuId; + params.bSpaAccessOnly = FLD_TEST_DRF(_P2PAPI, _ATTRIBUTES, _LINK_TYPE, _SPA, attributes); + + _kbusExecGspRmRpcForNvlink(pGpu0, NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING, + ¶ms, sizeof(params)); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "GPU%d NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING failed for peer%d\n", + gpuGetInstance(pGpu0), peerId); + } + + osReleaseRmSema(pSys->pSema, NULL); + + return status; +} + /*! * @brief Create a P2P mapping to a given peer GPU * @@ -97,14 +202,10 @@ kbusCreateP2PMappingForNvlink_GP100 NvU32 gpu0Instance = gpuGetInstance(pGpu0); NvU32 gpu1Instance = gpuGetInstance(pGpu1); NvBool bLoopback = (pGpu0 == pGpu1); - KernelNvlink *pKernelNvlink0 = GPU_GET_KERNEL_NVLINK(pGpu0); - KernelNvlink *pKernelNvlink1 = GPU_GET_KERNEL_NVLINK(pGpu1); NV_STATUS status = NV_OK; NvU32 nvlinkPeer0 = BUS_INVALID_PEER; NvU32 nvlinkPeer1 = BUS_INVALID_PEER; - NV2080_CTRL_NVLINK_ENABLE_NVLINK_PEER_PARAMS params; - if (peer0 == NULL || peer1 == NULL) { return NV_ERR_INVALID_ARGUMENT; @@ -126,8 +227,7 @@ kbusCreateP2PMappingForNvlink_GP100 return status; } - if ((pKernelNvlink0 == NULL) || (pKernelNvlink1 == NULL) || - (nvlinkPeer0 == BUS_INVALID_PEER) || (nvlinkPeer1 == BUS_INVALID_PEER)) + if (nvlinkPeer0 == BUS_INVALID_PEER || nvlinkPeer1 == BUS_INVALID_PEER) { return NV_ERR_INVALID_REQUEST; } @@ -244,45 +344,64 @@ kbusCreateP2PMappingForNvlink_GP100 "added NVLink P2P mapping between GPU%u (peer %u) and GPU%u (peer %u)\n", gpu0Instance, *peer0, gpu1Instance, *peer1); - portMemSet(¶ms, 0, sizeof(params)); - params.peerMask = NVBIT(*peer0); - params.bEnable = NV_TRUE; - - // Set the NVLink USE_NVLINK_PEER fields in the LTCS registers for GPU0 - status = knvlinkExecGspRmRpc(pGpu0, pKernelNvlink0, - NV2080_CTRL_CMD_NVLINK_ENABLE_NVLINK_PEER, - (void *)¶ms, sizeof(params)); - if (status != NV_OK) + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu0)) { - NV_PRINTF(LEVEL_ERROR, - "GPU%d Failed to ENABLE USE_NVLINK_PEER for peer%d\n", - gpuGetInstance(pGpu0), *peer0); + NV_ASSERT_OK_OR_RETURN(_kbusCreateNvlinkPeerMapping(pGpu0, pKernelBus0, pGpu1, *peer0, attributes)); + NV_ASSERT_OK_OR_RETURN(_kbusCreateNvlinkPeerMapping(pGpu1, pKernelBus1, pGpu0, *peer1, attributes)); return status; } - - portMemSet(¶ms, 0, sizeof(params)); - params.peerMask = NVBIT(*peer1); - params.bEnable = NV_TRUE; - - // Set the NVLink USE_NVLINK_PEER fields in the LTCS registers for GPU1 - status = knvlinkExecGspRmRpc(pGpu1, pKernelNvlink1, - NV2080_CTRL_CMD_NVLINK_ENABLE_NVLINK_PEER, - (void *)¶ms, sizeof(params)); - if (status != NV_OK) + else { - NV_PRINTF(LEVEL_ERROR, - "GPU%d Failed to ENABLE USE_NVLINK_PEER for peer%d\n", - gpuGetInstance(pGpu1), *peer1); + KernelNvlink *pKernelNvlink0 = GPU_GET_KERNEL_NVLINK(pGpu0); + KernelNvlink *pKernelNvlink1 = GPU_GET_KERNEL_NVLINK(pGpu1); + NV2080_CTRL_NVLINK_ENABLE_NVLINK_PEER_PARAMS params; - return status; + if (pKernelNvlink0 == NULL || pKernelNvlink1 == NULL) + { + return NV_ERR_INVALID_REQUEST; + } + + portMemSet(¶ms, 0, sizeof(params)); + params.peerMask = NVBIT(*peer0); + params.bEnable = NV_TRUE; + + // Set the NVLink USE_NVLINK_PEER fields in the LTCS registers for GPU0 + status = knvlinkExecGspRmRpc(pGpu0, pKernelNvlink0, + NV2080_CTRL_CMD_NVLINK_ENABLE_NVLINK_PEER, + (void *)¶ms, sizeof(params)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "GPU%d Failed to ENABLE USE_NVLINK_PEER for peer%d\n", + gpuGetInstance(pGpu0), *peer0); + + return status; + } + + portMemSet(¶ms, 0, sizeof(params)); + params.peerMask = NVBIT(*peer1); + params.bEnable = NV_TRUE; + + // Set the NVLink USE_NVLINK_PEER fields in the LTCS registers for GPU1 + status = knvlinkExecGspRmRpc(pGpu1, pKernelNvlink1, + NV2080_CTRL_CMD_NVLINK_ENABLE_NVLINK_PEER, + (void *)¶ms, sizeof(params)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "GPU%d Failed to ENABLE USE_NVLINK_PEER for peer%d\n", + gpuGetInstance(pGpu1), *peer1); + + return status; + } + + // Enable the peer configuration in the HSHUB config registers + knvlinkSetupPeerMapping_HAL(pGpu0, pKernelNvlink0, pGpu1, *peer0); + knvlinkSetupPeerMapping_HAL(pGpu1, pKernelNvlink1, pGpu0, *peer1); + + return NV_OK; } - - // Enable the peer configuration in the HSHUB config registers - knvlinkSetupPeerMapping_HAL(pGpu0, pKernelNvlink0, pGpu1, *peer0); - knvlinkSetupPeerMapping_HAL(pGpu1, pKernelNvlink1, pGpu0, *peer1); - - return NV_OK; } /*! @@ -295,8 +414,8 @@ kbusCreateP2PMappingForNvlink_GP100 * * return NV_OK on success */ -NV_STATUS -kbusRemoveNvlinkPeerMapping_GP100 +static NV_STATUS +_kbusRemoveNvlinkPeerMapping ( OBJGPU *pGpu0, KernelBus *pKernelBus0, @@ -305,12 +424,9 @@ kbusRemoveNvlinkPeerMapping_GP100 NvU32 attributes ) { - NV_STATUS status = NV_OK; - NvU32 peerGpuInst = gpuGetInstance(pGpu1); - KernelNvlink *pKernelNvlink0 = GPU_GET_KERNEL_NVLINK(pGpu0); - NvBool bLoopback = (pGpu0 == pGpu1); - - NV_ASSERT_OR_RETURN(pKernelNvlink0 != NULL, NV_ERR_NOT_SUPPORTED); + NV_STATUS status = NV_OK; + NvU32 peerGpuInst = gpuGetInstance(pGpu1); + NvBool bBufferReady = NV_FALSE; // If no peer mapping exists between the GPUs, return NV_WARN_NOTHING_TO_DO if ((pKernelBus0->p2p.busNvlinkPeerNumberMask[peerGpuInst] & NVBIT(peerId)) == 0) @@ -326,38 +442,28 @@ kbusRemoveNvlinkPeerMapping_GP100 return NV_ERR_INVALID_STATE; } - if (pKernelNvlink0->getProperty(pKernelNvlink0, PDB_PROP_KNVLINK_UNSET_NVLINK_PEER_REFCNT) || - (bLoopback == NV_TRUE) || - (knvlinkIsGpuConnectedToNvswitch(pGpu0, pKernelNvlink0))) + // Decrement the mapping refcount associated with the peerID + pKernelBus0->p2p.busNvlinkMappingRefcountPerPeerId[peerId]--; + + // Decrement the mapping refcount for the given remote GPU1 + pKernelBus0->p2p.busNvlinkMappingRefcountPerGpu[peerGpuInst]--; + + if (FLD_TEST_DRF(_P2PAPI, _ATTRIBUTES, _LINK_TYPE, _SPA, attributes)) { - // - // WAR 3740439 : Since this code fails for loopback, when we reuse peer ID and not destroy P2P - // objects, we will follow legacy code for loopback and nvswitch and unblock DVT while we debug - // - - // Decrement the mapping refcount associated with the peerID pKernelBus0->p2p.busNvlinkMappingRefcountPerPeerId[peerId]--; + } - // Decrement the mapping refcount for the given remote GPU1 - pKernelBus0->p2p.busNvlinkMappingRefcountPerGpu[peerGpuInst]--; + // + // If mapping refcount to remote GPU1 is 0, this implies the peerID is no + // longer used for P2P from GPU0 to GPU1. Update busNvlinkPeerNumberMask + // + if (pKernelBus0->p2p.busNvlinkMappingRefcountPerGpu[peerGpuInst] == 0) + { + NV_PRINTF(LEVEL_INFO, + "Removing mapping for GPU%u peer %u (GPU%u)\n", + gpuGetInstance(pGpu0), peerId, peerGpuInst); - if (FLD_TEST_DRF(_P2PAPI, _ATTRIBUTES, _LINK_TYPE, _SPA, attributes)) - { - pKernelBus0->p2p.busNvlinkMappingRefcountPerPeerId[peerId]--; - } - - // - // If mapping refcount to remote GPU1 is 0, this implies the peerID is no - // longer used for P2P from GPU0 to GPU1. Update busNvlinkPeerNumberMask - // - if (pKernelBus0->p2p.busNvlinkMappingRefcountPerGpu[peerGpuInst] == 0) - { - NV_PRINTF(LEVEL_INFO, - "Removing mapping for GPU%u peer %u (GPU%u)\n", - gpuGetInstance(pGpu0), peerId, peerGpuInst); - - pKernelBus0->p2p.busNvlinkPeerNumberMask[peerGpuInst] &= ~NVBIT(peerId); - } + pKernelBus0->p2p.busNvlinkPeerNumberMask[peerGpuInst] &= ~NVBIT(peerId); } // @@ -366,57 +472,97 @@ kbusRemoveNvlinkPeerMapping_GP100 // if (pKernelBus0->p2p.busNvlinkMappingRefcountPerPeerId[peerId] == 0) { + NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS params; + OBJSYS *pSys = SYS_GET_INSTANCE(); + NV_ASSERT(pKernelBus0->p2p.busNvlinkMappingRefcountPerPeerId[peerId] == 0); NV_PRINTF(LEVEL_INFO, "PeerID %u is not being used for P2P from GPU%d to any other " "remote GPU. Can be freed\n", peerId, gpuGetInstance(pGpu0)); - if (pKernelNvlink0->getProperty(pKernelNvlink0, - PDB_PROP_KNVLINK_DECONFIG_HSHUB_ON_NO_MAPPING)) + if (pKernelBus0->getProperty(pKernelBus0, + PDB_PROP_KBUS_NVLINK_DECONFIG_HSHUB_ON_NO_MAPPING)) { // Before removing the NVLink peer mapping in HSHUB flush both ends kbusFlush_HAL(pGpu0, pKernelBus0, BUS_FLUSH_VIDEO_MEMORY | BUS_FLUSH_USE_PCIE_READ); kbusFlush_HAL(pGpu1, GPU_GET_KERNEL_BUS(pGpu1), BUS_FLUSH_VIDEO_MEMORY | BUS_FLUSH_USE_PCIE_READ); } - NV2080_CTRL_NVLINK_ENABLE_NVLINK_PEER_PARAMS params; - portMemSet(¶ms, 0, sizeof(params)); - params.peerMask = NVBIT(peerId); - params.bEnable = NV_FALSE; - - // Unset the NVLink USE_NVLINK_PEER fields in the LTCS registers for GPU0 - status = knvlinkExecGspRmRpc(pGpu0, pKernelNvlink0, - NV2080_CTRL_CMD_NVLINK_ENABLE_NVLINK_PEER, - (void *)¶ms, sizeof(params)); - if (status != NV_OK) + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu0)) { - NV_PRINTF(LEVEL_ERROR, - "GPU%d Failed to UNSET USE_NVLINK_PEER for peer%d\n", - gpuGetInstance(pGpu0), peerId); + NV_ASSERT_OK_OR_RETURN(osAcquireRmSema(pSys->pSema)); - return status; + portMemSet(¶ms, 0, sizeof(params)); + params.connectionType = NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_NVLINK; + params.peerId = peerId; + params.bUseUuid = NV_FALSE; + params.remoteGpuId = pGpu1->gpuId; + + _kbusExecGspRmRpcForNvlink(pGpu0, NV2080_CTRL_CMD_BUS_UNSET_P2P_MAPPING, + ¶ms, sizeof(params)); + + osReleaseRmSema(pSys->pSema, NULL); } - - // Disable the peer configuration in the HSHUB config registers - if ((pKernelNvlink0->getProperty(pKernelNvlink0, - PDB_PROP_KNVLINK_DECONFIG_HSHUB_ON_NO_MAPPING)) && - (!knvlinkIsForcedConfig(pGpu0, pKernelNvlink0))) + else { - status = knvlinkRemoveMapping_HAL(pGpu0, pKernelNvlink0, NV_FALSE, NVBIT(peerId), - NV_FALSE /* bL2Entry */); + KernelNvlink *pKernelNvlink0 = GPU_GET_KERNEL_NVLINK(pGpu0); + NV2080_CTRL_NVLINK_ENABLE_NVLINK_PEER_PARAMS params; + + NV_ASSERT_OR_RETURN(pKernelNvlink0 != NULL, NV_ERR_NOT_SUPPORTED); + + portMemSet(¶ms, 0, sizeof(params)); + params.peerMask = NVBIT(peerId); + params.bEnable = NV_FALSE; + + // Unset the NVLink USE_NVLINK_PEER fields in the LTCS registers for GPU0 + status = knvlinkExecGspRmRpc(pGpu0, pKernelNvlink0, + NV2080_CTRL_CMD_NVLINK_ENABLE_NVLINK_PEER, + (void *)¶ms, sizeof(params)); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, - "GPU%d Failed to remove hshub mapping for peer%d\n", + "GPU%d Failed to UNSET USE_NVLINK_PEER for peer%d\n", gpuGetInstance(pGpu0), peerId); return status; } - } - // Call knvlinkUpdateCurrentConfig to flush settings to the registers - status = knvlinkUpdateCurrentConfig(pGpu0, pKernelNvlink0); + // Disable the peer configuration in the HSHUB config registers + if ((pKernelBus0->getProperty(pKernelBus0, + PDB_PROP_KBUS_NVLINK_DECONFIG_HSHUB_ON_NO_MAPPING)) && + (!knvlinkIsForcedConfig(pGpu0, pKernelNvlink0))) + { + status = knvlinkRemoveMapping_HAL(pGpu0, pKernelNvlink0, NV_FALSE, NVBIT(peerId), + NV_FALSE /* bL2Entry */); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "GPU%d Failed to remove hshub mapping for peer%d\n", + gpuGetInstance(pGpu0), peerId); + + return status; + } + } + + // + // Call knvlinkUpdateCurrentConfig to flush settings to the registers + // Skip this call if buffer ready is set and CONFIG_REQUIRE_INITIALIZED is true + // + status = knvlinkSyncLinkMasksAndVbiosInfo(pGpu0, pKernelNvlink0); + if (status != NV_OK) + { + NV_ASSERT(status == NV_OK); + return status; + } + + bBufferReady = ((pKernelNvlink0->initializedLinks & pKernelNvlink0->peerLinkMasks[peerId]) != 0) ? NV_TRUE : NV_FALSE; + if (!pKernelNvlink0->getProperty(pKernelNvlink0, PDB_PROP_KNVLINK_CONFIG_REQUIRE_INITIALIZED_LINKS_CHECK) || + !bBufferReady) + { + status = knvlinkUpdateCurrentConfig(pGpu0, pKernelNvlink0); + } + } } return status; @@ -486,21 +632,18 @@ kbusRemoveP2PMappingForNvlink_GP100 NvU32 attributes ) { - KernelNvlink *pKernelNvlink0 = GPU_GET_KERNEL_NVLINK(pGpu0); - KernelNvlink *pKernelNvlink1 = GPU_GET_KERNEL_NVLINK(pGpu1); NV_STATUS status = NV_OK; // If there's no NVLink mapping, fall back to PCIe - if ((pKernelNvlink0 == NULL) || (pKernelNvlink1 == NULL) || - ((pKernelBus0->p2p.busNvlinkPeerNumberMask[pGpu1->gpuInstance] & NVBIT(peer0)) == 0) || - ((pKernelBus1->p2p.busNvlinkPeerNumberMask[pGpu0->gpuInstance] & NVBIT(peer1)) == 0)) + if ((pKernelBus0->p2p.busNvlinkPeerNumberMask[pGpu1->gpuInstance] & NVBIT(peer0)) == 0 || + (pKernelBus1->p2p.busNvlinkPeerNumberMask[pGpu0->gpuInstance] & NVBIT(peer1)) == 0) { return NV_ERR_INVALID_STATE; } // NVLink mapping exists, remove the NVLink mapping - NV_ASSERT_OK_OR_RETURN(kbusRemoveNvlinkPeerMapping_HAL(pGpu0, pKernelBus0, pGpu1, peer0, attributes)); - NV_ASSERT_OK_OR_RETURN(kbusRemoveNvlinkPeerMapping_HAL(pGpu1, pKernelBus1, pGpu0, peer1, attributes)); + NV_ASSERT_OK_OR_RETURN(_kbusRemoveNvlinkPeerMapping(pGpu0, pKernelBus0, pGpu1, peer0, attributes)); + NV_ASSERT_OK_OR_RETURN(_kbusRemoveNvlinkPeerMapping(pGpu1, pKernelBus1, pGpu0, peer1, attributes)); // // The P2P mapping for both the GPUs have been destroyed. If the mapping refcount @@ -508,7 +651,7 @@ kbusRemoveP2PMappingForNvlink_GP100 // if ((pKernelBus0->p2p.busNvlinkMappingRefcountPerPeerId[peer0] == 0) && - pKernelNvlink0->getProperty(pKernelNvlink0, PDB_PROP_KNVLINK_DECONFIG_HSHUB_ON_NO_MAPPING)) + pKernelBus0->getProperty(pKernelBus0, PDB_PROP_KBUS_NVLINK_DECONFIG_HSHUB_ON_NO_MAPPING)) { // Free the reserved peer ID since its no longer used status = kbusUnreserveP2PPeerIds_HAL(pGpu0, pKernelBus0, NVBIT(peer0)); @@ -522,7 +665,7 @@ kbusRemoveP2PMappingForNvlink_GP100 } if ((pKernelBus1->p2p.busNvlinkMappingRefcountPerPeerId[peer1] == 0) && - pKernelNvlink1->getProperty(pKernelNvlink1, PDB_PROP_KNVLINK_DECONFIG_HSHUB_ON_NO_MAPPING)) + pKernelBus1->getProperty(pKernelBus1, PDB_PROP_KBUS_NVLINK_DECONFIG_HSHUB_ON_NO_MAPPING)) { // Free the reserved peer ID since its no longer used status = kbusUnreserveP2PPeerIds_HAL(pGpu1, pKernelBus1, NVBIT(peer1)); diff --git a/src/nvidia/src/kernel/gpu/bus/arch/volta/kern_bus_gv100.c b/src/nvidia/src/kernel/gpu/bus/arch/volta/kern_bus_gv100.c index 52ce2e50e..62ac954ae 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/volta/kern_bus_gv100.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/volta/kern_bus_gv100.c @@ -28,6 +28,9 @@ #include "gpu/mem_sys/kern_mem_sys.h" #include "os/os.h" +// @ref busMigrateBarMapping_GV100 to see how FB region is organized +#define COHERENT_CPU_MAPPING_WPR COHERENT_CPU_MAPPING_REGION_0 + /*! * @brief Sets up a memdesc and a CPU pointer to the bottom * of FB that will be used for issuing reads in order @@ -71,9 +74,9 @@ kbusSetupCpuPointerForBusFlush_GV100 // Please note this is a long-lived BAR2 mapping by design. // The mapping is used for flushing all future vidmem writes on BAR2. // - pKernelBus->pReadToFlush = memmgrMemDescBeginTransfer(GPU_GET_MEMORY_MANAGER(pGpu), - pKernelBus->pFlushMemDesc, - TRANSFER_FLAGS_PERSISTENT_CPU_MAPPING); + pKernelBus->pReadToFlush = memdescMapInternal(pGpu, + pKernelBus->pFlushMemDesc, + TRANSFER_FLAGS_PERSISTENT_CPU_MAPPING); if (pKernelBus->pReadToFlush == NULL) { status = NV_ERR_INSUFFICIENT_RESOURCES; @@ -104,9 +107,9 @@ kbusDestroyCpuPointerForBusFlush_GV100 { if (pKernelBus->pReadToFlush != NULL) { - memmgrMemDescEndTransfer(GPU_GET_MEMORY_MANAGER(pGpu), - pKernelBus->pFlushMemDesc, - TRANSFER_FLAGS_DEFER_FLUSH); + memdescUnmapInternal(pGpu, + pKernelBus->pFlushMemDesc, + TRANSFER_FLAGS_DEFER_FLUSH); pKernelBus->pReadToFlush = NULL; } @@ -141,7 +144,7 @@ kbusMapCoherentCpuMapping_GV100 RmPhysAddr offset = 0; NvU32 i = 0; - for (i = COHERENT_CPU_MAPPING_WPR; i < pKernelBus->coherentCpuMapping.nrMapping; ++i) + for (i = COHERENT_CPU_MAPPING_REGION_0; i < pKernelBus->coherentCpuMapping.nrMapping; ++i) { // Check if requested mem in the mappings. rangeStart = pKernelBus->coherentCpuMapping.physAddr[i]; @@ -190,7 +193,7 @@ kbusUnmapCoherentCpuMapping_GV100 NV_ASSERT(pMemDesc->_flags & MEMDESC_FLAGS_PHYSICALLY_CONTIGUOUS); - for (i = COHERENT_CPU_MAPPING_WPR; i < pKernelBus->coherentCpuMapping.nrMapping; ++i) + for (i = COHERENT_CPU_MAPPING_REGION_0; i < pKernelBus->coherentCpuMapping.nrMapping; ++i) { RmPhysAddr rangeStart = pKernelBus->coherentCpuMapping.physAddr[i]; RmPhysAddr rangeEnd = pKernelBus->coherentCpuMapping.physAddr[i] + @@ -268,7 +271,7 @@ kbusTeardownCoherentCpuMapping_GV100 if (!pKernelBus->coherentCpuMapping.bCoherentCpuMapping) return; - for (i = COHERENT_CPU_MAPPING_WPR; i < pKernelBus->coherentCpuMapping.nrMapping; ++i) + for (i = COHERENT_CPU_MAPPING_REGION_0; i < pKernelBus->coherentCpuMapping.nrMapping; ++i) { NV_ASSERT_OR_RETURN_VOID(pKernelBus->coherentCpuMapping.refcnt[i] == 0); diff --git a/src/nvidia/src/kernel/gpu/bus/kern_bus.c b/src/nvidia/src/kernel/gpu/bus/kern_bus.c index 393e1b1d2..fbc383934 100644 --- a/src/nvidia/src/kernel/gpu/bus/kern_bus.c +++ b/src/nvidia/src/kernel/gpu/bus/kern_bus.c @@ -28,11 +28,12 @@ #include "mem_mgr/gpu_vaspace.h" #include "gpu/mmu/kern_gmmu.h" #include "gpu/bus/kern_bus.h" -#include "gpu/nvlink/kernel_nvlink.h" #include "kernel/gpu/mem_mgr/mem_mgr.h" #include "kernel/gpu/mem_sys/kern_mem_sys.h" +#include "kernel/gpu/nvbitmask.h" #include "platform/chipset/chipset.h" #include "rmapi/client.h" +#include "nvdevid.h" #include "gpu/subdevice/subdevice.h" #include "gpu/gsp/gsp_static_config.h" @@ -744,95 +745,6 @@ kbusPatchBar2Pdb_GSPCLIENT return NV_OK; } -/*! - * @brief Helper function to trigger RPC to Physical RM to unbind FLA VASpace - * - * @param[in] pGpu - * @param[in] pKernelBus - * - * @return NV_OK if successful - */ -NV_STATUS -kbusSetupUnbindFla_KERNEL -( - OBJGPU *pGpu, - KernelBus *pKernelBus -) -{ - NV_STATUS status = NV_OK; - NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS params = { 0 }; - - if (!pKernelBus->flaInfo.bFlaBind) - return NV_OK; - - params.flaAction = NV2080_CTRL_FLA_ACTION_UNBIND; - - NV_RM_RPC_CONTROL(pGpu, pKernelBus->flaInfo.hClient, - pKernelBus->flaInfo.hSubDevice, - NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK, - ¶ms, sizeof(params), status); - - pKernelBus->flaInfo.bFlaBind = NV_FALSE; - pKernelBus->bFlaEnabled = NV_FALSE; - - return status; -} - -/*! - * @brief Helper function to extract information from FLA data structure and - * to trigger RPC to Physical RM to BIND FLA VASpace - * - * @param[in] pGpu - * @param[in] pKernelBus - * @param[in] gfid GFID - * - * @return NV_OK if successful - */ -NV_STATUS -kbusSetupBindFla_KERNEL -( - OBJGPU *pGpu, - KernelBus *pKernelBus, - NvU32 gfid -) -{ - NV_STATUS status = NV_OK; - NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS params = {0}; - - if (!gpuIsWarBug200577889SriovHeavyEnabled(pGpu)) - { - MEMORY_DESCRIPTOR *pMemDesc; - RmPhysAddr imbPhysAddr; - NvU32 addrSpace; - - pMemDesc = pKernelBus->flaInfo.pInstblkMemDesc; - imbPhysAddr = memdescGetPhysAddr(pMemDesc, AT_GPU, 0); - addrSpace = memdescGetAddressSpace(pMemDesc); - NV2080_CTRL_FLA_ADDRSPACE paramAddrSpace = NV2080_CTRL_FLA_ADDRSPACE_FBMEM; - - switch(addrSpace) - { - case ADDR_FBMEM: - paramAddrSpace = NV2080_CTRL_FLA_ADDRSPACE_FBMEM; - break; - case ADDR_SYSMEM: - paramAddrSpace = NV2080_CTRL_FLA_ADDRSPACE_SYSMEM; - break; - } - params.imbPhysAddr = imbPhysAddr; - params.addrSpace = paramAddrSpace; - } - params.flaAction = NV2080_CTRL_FLA_ACTION_BIND; - NV_RM_RPC_CONTROL(pGpu, pKernelBus->flaInfo.hClient, - pKernelBus->flaInfo.hSubDevice, - NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK, - ¶ms, sizeof(params), status); - // Since FLA state is tracked in the Guest, Guest RM needs to set it here - pKernelBus->flaInfo.bFlaBind = NV_TRUE; - pKernelBus->bFlaEnabled = NV_TRUE; - - return status; -} /*! * @brief Checks whether an engine is available or not. @@ -861,21 +773,29 @@ kbusCheckEngine_KERNEL ENGDESCRIPTOR engDesc ) { - NvU64 engineList; - NvBool bSupported; - - if (!RMCFG_FEATURE_VIRTUALIZATION && !RMCFG_FEATURE_GSP_CLIENT_RM) - return NV_TRUE; + NvU32 rmEngineCaps[NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX] = {0}; + NvU32 nv2080EngineCaps[NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX] = {0}; + NvBool bSupported; + NV_STATUS status; { + NvU32 i; GspStaticConfigInfo *pGSCI = GPU_GET_GSP_STATIC_INFO(pGpu); if (pGSCI == NULL) { return NV_FALSE; } - engineList = pGSCI->engineCaps; + + for (i=0; iengineCaps[i]; + } } + NV_CHECK_OK_OR_ELSE(status, LEVEL_ERROR, + gpuGetRmEngineTypeCapMask(nv2080EngineCaps, NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX, rmEngineCaps), + return NV_FALSE); + switch (engDesc) { case ENG_LSFM: @@ -913,68 +833,67 @@ kbusCheckEngine_KERNEL return NV_TRUE; case ENG_CE(0): - return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_COPY0))) ? NV_TRUE: NV_FALSE); + return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_COPY0) ? NV_TRUE: NV_FALSE); case ENG_CE(1): - return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_COPY1))) ? NV_TRUE: NV_FALSE); + return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_COPY1) ? NV_TRUE: NV_FALSE); case ENG_CE(2): - return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_COPY2))) ? NV_TRUE: NV_FALSE); + return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_COPY2) ? NV_TRUE: NV_FALSE); case ENG_CE(3): - return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_COPY3))) ? NV_TRUE: NV_FALSE); + return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_COPY3) ? NV_TRUE: NV_FALSE); case ENG_CE(4): - return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_COPY4))) ? NV_TRUE: NV_FALSE); + return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_COPY4) ? NV_TRUE: NV_FALSE); case ENG_CE(5): - return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_COPY5))) ? NV_TRUE: NV_FALSE); + return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_COPY5) ? NV_TRUE: NV_FALSE); case ENG_CE(6): - return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_COPY6))) ? NV_TRUE: NV_FALSE); + return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_COPY6) ? NV_TRUE: NV_FALSE); case ENG_CE(7): - return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_COPY7))) ? NV_TRUE: NV_FALSE); + return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_COPY7) ? NV_TRUE: NV_FALSE); case ENG_CE(8): - return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_COPY8))) ? NV_TRUE: NV_FALSE); + return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_COPY8) ? NV_TRUE: NV_FALSE); case ENG_CE(9): - return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_COPY9))) ? NV_TRUE: NV_FALSE); + return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_COPY9) ? NV_TRUE: NV_FALSE); case ENG_MSENC(0): - return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_NVENC0))) ? NV_TRUE: NV_FALSE); + return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVENC0) ? NV_TRUE: NV_FALSE); case ENG_MSENC(1): - return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_NVENC1))) ? NV_TRUE: NV_FALSE); + return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVENC1) ? NV_TRUE: NV_FALSE); case ENG_MSENC(2): - return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_NVENC2))) ? NV_TRUE: NV_FALSE); + return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVENC2) ? NV_TRUE: NV_FALSE); case ENG_SEC2: - return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_SEC2))) ? NV_TRUE: NV_FALSE); + return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_SEC2) ? NV_TRUE: NV_FALSE); case ENG_NVDEC(0): - return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_NVDEC0))) ? NV_TRUE: NV_FALSE); + return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVDEC0) ? NV_TRUE: NV_FALSE); case ENG_NVDEC(1): - return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_NVDEC1))) ? NV_TRUE: NV_FALSE); + return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVDEC1) ? NV_TRUE: NV_FALSE); case ENG_NVDEC(2): - return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_NVDEC2))) ? NV_TRUE: NV_FALSE); + return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVDEC2) ? NV_TRUE: NV_FALSE); case ENG_OFA: - return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_OFA))) ? NV_TRUE: NV_FALSE); + return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_OFA) ? NV_TRUE: NV_FALSE); case ENG_NVDEC(3): - return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_NVDEC3))) ? NV_TRUE: NV_FALSE); + return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVDEC3) ? NV_TRUE: NV_FALSE); case ENG_NVDEC(4): - return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_NVDEC4))) ? NV_TRUE: NV_FALSE); + return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVDEC4) ? NV_TRUE: NV_FALSE); case ENG_NVDEC(5): - return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_NVDEC5))) ? NV_TRUE: NV_FALSE); + return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVDEC5) ? NV_TRUE: NV_FALSE); case ENG_NVDEC(6): - return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_NVDEC6))) ? NV_TRUE: NV_FALSE); + return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVDEC6) ? NV_TRUE: NV_FALSE); case ENG_NVDEC(7): - return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_NVDEC7))) ? NV_TRUE: NV_FALSE); + return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVDEC7) ? NV_TRUE: NV_FALSE); case ENG_NVJPEG(0): - return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_NVJPEG0))) ? NV_TRUE: NV_FALSE); + return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVJPEG0) ? NV_TRUE: NV_FALSE); case ENG_NVJPEG(1): - return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_NVJPEG1))) ? NV_TRUE: NV_FALSE); + return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVJPEG1) ? NV_TRUE: NV_FALSE); case ENG_NVJPEG(2): - return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_NVJPEG2))) ? NV_TRUE: NV_FALSE); + return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVJPEG2) ? NV_TRUE: NV_FALSE); case ENG_NVJPEG(3): - return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_NVJPEG3))) ? NV_TRUE: NV_FALSE); + return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVJPEG3) ? NV_TRUE: NV_FALSE); case ENG_NVJPEG(4): - return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_NVJPEG4))) ? NV_TRUE: NV_FALSE); + return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVJPEG4) ? NV_TRUE: NV_FALSE); case ENG_NVJPEG(5): - return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_NVJPEG5))) ? NV_TRUE: NV_FALSE); + return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVJPEG5) ? NV_TRUE: NV_FALSE); case ENG_NVJPEG(6): - return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_NVJPEG6))) ? NV_TRUE: NV_FALSE); + return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVJPEG6) ? NV_TRUE: NV_FALSE); case ENG_NVJPEG(7): - return ((engineList & (NVBIT64(NV2080_ENGINE_TYPE_NVJPEG7))) ? NV_TRUE: NV_FALSE); - + return (NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVJPEG7) ? NV_TRUE: NV_FALSE); case ENG_GR(1): case ENG_GR(2): case ENG_GR(3): @@ -1272,6 +1191,41 @@ kbusSendBusInfo_IMPL return status; } +/*! + * @brief Returns the Nvlink peer ID from pGpu0 to pGpu1 + * + * @param[in] pGpu0 (local GPU) + * @param[in] pKernelBus0 (local GPU) + * @param[in] pGpu1 (remote GPU) + * @param[in] pKernelBus1 (remote GPU) + * @param[out] nvlinkPeer NvU32 pointer + * + * return NV_OK on success + */ +NV_STATUS +kbusGetNvlinkP2PPeerId_VGPU +( + OBJGPU *pGpu0, + KernelBus *pKernelBus0, + OBJGPU *pGpu1, + KernelBus *pKernelBus1, + NvU32 *nvlinkPeer +) +{ + *nvlinkPeer = kbusGetUnusedPeerId_HAL(pGpu0, pKernelBus0); + + // If could not find a free peer ID, return error + if (*nvlinkPeer == BUS_INVALID_PEER) + { + NV_PRINTF(LEVEL_WARNING, + "GPU%d: peerID not available for NVLink P2P\n", + pGpu0->gpuInstance); + return NV_ERR_GENERIC; + } + // Reserve the peer ID for NVLink use + return kbusReserveP2PPeerIds_HAL(pGpu0, pKernelBus0, NVBIT(*nvlinkPeer)); +} + /** * @brief Check for any P2P references in to remote GPUs * which are still have a P2P api object alive. @@ -1287,4 +1241,4 @@ kbusIsGpuP2pAlive_IMPL ) { return (pKernelBus->totalP2pObjectsAliveRefCount > 0); -} \ No newline at end of file +} diff --git a/src/nvidia/src/kernel/gpu/bus/kern_bus_ctrl.c b/src/nvidia/src/kernel/gpu/bus/kern_bus_ctrl.c index 7075d63f6..36a22da9c 100644 --- a/src/nvidia/src/kernel/gpu/bus/kern_bus_ctrl.c +++ b/src/nvidia/src/kernel/gpu/bus/kern_bus_ctrl.c @@ -238,25 +238,32 @@ subdeviceCtrlCmdBusGetNvlinkPeerIdMask_IMPL NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS *pParams ) { - OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); - NvU32 gfid; - - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); - - // This control call should always run in context of a VF. - NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &gfid)); - if (IS_GFID_PF(gfid)) + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && RMCFG_FEATURE_PLATFORM_GSP) { return NV_ERR_NOT_SUPPORTED; } + else + { + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + NvU32 gfid; - portMemCopy((void *)pParams->nvlinkPeerIdMask, - sizeof(pParams->nvlinkPeerIdMask), - (void *)pKernelBus->p2p.busNvlinkPeerNumberMask, - sizeof(pParams->nvlinkPeerIdMask)); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); - return NV_OK; + // This control call should always run in context of a VF. + NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &gfid)); + if (IS_GFID_PF(gfid)) + { + return NV_ERR_NOT_SUPPORTED; + } + + portMemCopy((void *)pParams->nvlinkPeerIdMask, + sizeof(pParams->nvlinkPeerIdMask), + (void *)pKernelBus->p2p.busNvlinkPeerNumberMask, + sizeof(pParams->nvlinkPeerIdMask)); + + return NV_OK; + } } static NV_STATUS @@ -468,12 +475,12 @@ getBusInfos(OBJGPU *pGpu, NV2080_CTRL_BUS_INFO *pBusInfos, NvU32 busInfoListSize } case NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE: { - pBusInfos[i].data = (NvU32)(pKernelGmmu->maxVASize >> 20); + pBusInfos[i].data = (NvU32)(kgmmuGetMaxVASize(pKernelGmmu) >> 20); break; } case NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_SIZE_HI: { - pBusInfos[i].data = (NvU32)((pKernelGmmu->maxVASize >> 20) >> 32); + pBusInfos[i].data = (NvU32)((kgmmuGetMaxVASize(pKernelGmmu) >> 20) >> 32); break; } case NV2080_CTRL_BUS_INFO_INDEX_GPU_GART_FLAGS: diff --git a/src/nvidia/src/kernel/gpu/bus/kern_bus_vbar2.c b/src/nvidia/src/kernel/gpu/bus/kern_bus_vbar2.c index 0b98044a3..bcb736818 100644 --- a/src/nvidia/src/kernel/gpu/bus/kern_bus_vbar2.c +++ b/src/nvidia/src/kernel/gpu/bus/kern_bus_vbar2.c @@ -338,7 +338,10 @@ kbusFlushVirtualBar2_VBAR2(OBJGPU *pGpu, KernelBus *pKernelBus, NvBool shutdown, return; } - // Enforce RM unmapping up all BAR2 mappings + // + // There should be no there are no active BAR2 mappings on shutdown. Failure indicates + // there is a missing unmap BAR2 call somewhere in RM. + // NV_ASSERT(listCount(&pKernelBus->virtualBar2[gfid].usedMapList) == 0); // There should be no unreleased mappings at shutdown @@ -688,7 +691,7 @@ kbusMapBar2ApertureCached_VBAR2 if (pKernelBus->virtualBar2[GPU_GFID_PF].pCpuMapping == NULL || (!KBUS_BAR2_TUNNELLED(pKernelBus) && NV_OK != kbusUpdateRmAperture_HAL(pGpu, pKernelBus, pMemDesc, vAddr, - pMemDesc->PageCount * RM_PAGE_SIZE, + pMemDesc->PageCount * pMemDesc->pageArrayGranularity, UPDATE_RM_APERTURE_FLAGS_INVALIDATE))) { pVASpaceHeap->eheapFree(pVASpaceHeap, vAddr); @@ -862,6 +865,7 @@ kbusMapBar2Aperture_SCRATCH NvU32 flags ) { + return portMemAllocNonPaged((NvU32)pMemDesc->Size); } @@ -998,23 +1002,18 @@ kbusUnmapBar2ApertureWithFlags_VBAR2 NvU32 flags ) { - if (API_GPU_IN_RESET_SANITY_CHECK(pGpu)) + // + // Free the dummy data we allocated for handling a reset GPU. + // Let a map created before the reset go through the normal path + // to clear out the memory. + // + if (memdescGetFlag(pMemDesc, MEMDESC_FLAGS_GPU_IN_RESET)) { - // Free the dummy data we allocated earlier. - if (memdescGetFlag(pMemDesc, MEMDESC_FLAGS_GPU_IN_RESET)) - { - kbusUnmapBar2ApertureWithFlags_SCRATCH(pGpu, pKernelBus, pMemDesc, pCpuPtr, flags); - memdescSetFlag(pMemDesc, MEMDESC_FLAGS_GPU_IN_RESET, NV_FALSE); - return; - } - // - // Let a map created before the reset go through the normal path - // to clear out the memory. - // + kbusUnmapBar2ApertureWithFlags_SCRATCH(pGpu, pKernelBus, pMemDesc, pCpuPtr, flags); + memdescSetFlag(pMemDesc, MEMDESC_FLAGS_GPU_IN_RESET, NV_FALSE); + return; } - NV_ASSERT(!memdescGetFlag(pMemDesc, MEMDESC_FLAGS_GPU_IN_RESET)); - // Call the lower-level routine kbusUnmapBar2ApertureCached_VBAR2(pGpu, pKernelBus, pMemDesc, flags); } @@ -1141,7 +1140,7 @@ NV_STATUS kbusMapCpuInvisibleBar2Aperture_VBAR2 } status = kbusUpdateRmAperture_HAL(pGpu, pKernelBus, pMemDesc, *pVaddr, - pMemDesc->PageCount * RM_PAGE_SIZE, UPDATE_RM_APERTURE_FLAGS_INVALIDATE | + pMemDesc->PageCount * pMemDesc->pageArrayGranularity, UPDATE_RM_APERTURE_FLAGS_INVALIDATE | UPDATE_RM_APERTURE_FLAGS_CPU_INVISIBLE_RANGE); if (IS_GFID_VF(gfid) && (pKernelBus->virtualBar2[gfid].pPageLevels != NULL)) diff --git a/src/nvidia/src/kernel/gpu/bus/p2p.c b/src/nvidia/src/kernel/gpu/bus/p2p.c index 85117c6f2..693404736 100644 --- a/src/nvidia/src/kernel/gpu/bus/p2p.c +++ b/src/nvidia/src/kernel/gpu/bus/p2p.c @@ -22,6 +22,7 @@ */ #include "core/core.h" +#include "core/locks.h" #include #include "gpu/gpu.h" #include "gpu/mem_sys/kern_mem_sys.h" @@ -62,20 +63,17 @@ NV_STATUS RmP2PValidateSubDevice * @brief frees given third party p2p memory extent */ static -NV_STATUS _freeMappingExtentInfo +void _freeMappingExtentInfo ( PCLI_THIRD_PARTY_P2P_MAPPING_EXTENT_INFO pExtentInfo ) { if (pExtentInfo == NULL) - return NV_OK; + return; - if (pExtentInfo->pMemDesc != NULL) - memdescDestroy(pExtentInfo->pMemDesc); + memdescDestroy(pExtentInfo->pMemDesc); portMemFree(pExtentInfo); - - return NV_OK; } /*! @@ -202,11 +200,12 @@ NV_STATUS _createThirdPartyP2PMappingExtent 0, &fbApertureOffset, status); } - else + else if ((status = rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK) { status = kbusMapFbAperture_HAL(pGpu, pKernelBus, (*ppExtentInfo)->pMemDesc, 0, - &fbApertureOffset, &fbApertureMapLength, - BUS_MAP_FB_FLAGS_MAP_UNICAST, hClient); + &fbApertureOffset, &fbApertureMapLength, + BUS_MAP_FB_FLAGS_MAP_UNICAST, hClient); + rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); } if (status != NV_OK) { @@ -247,13 +246,14 @@ out: 0, fbApertureOffset, tmpStatus); } - else + else if ((tmpStatus = rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK) { tmpStatus = kbusUnmapFbAperture_HAL(pGpu, pKernelBus, (*ppExtentInfo)->pMemDesc, fbApertureOffset, fbApertureMapLength, BUS_MAP_FB_FLAGS_MAP_UNICAST); + rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); } NV_ASSERT(tmpStatus == NV_OK); } @@ -377,13 +377,14 @@ NV_STATUS RmThirdPartyP2PMappingFree 0, pExtentInfo->fbApertureOffset, status); } - else + else if ((status = rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK) { - status = kbusUnmapFbAperture_HAL(pGpu, pKernelBus, - pExtentInfo->pMemDesc, - pExtentInfo->fbApertureOffset, - pExtentInfo->length, - BUS_MAP_FB_FLAGS_MAP_UNICAST); + status = kbusUnmapFbAperture_HAL(pGpu, pKernelBus, + pExtentInfo->pMemDesc, + pExtentInfo->fbApertureOffset, + pExtentInfo->length, + BUS_MAP_FB_FLAGS_MAP_UNICAST); + rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); } NV_ASSERT(status == NV_OK); diff --git a/src/nvidia/src/kernel/gpu/bus/p2p_api.c b/src/nvidia/src/kernel/gpu/bus/p2p_api.c index 46708b689..8a18fe10c 100644 --- a/src/nvidia/src/kernel/gpu/bus/p2p_api.c +++ b/src/nvidia/src/kernel/gpu/bus/p2p_api.c @@ -36,62 +36,6 @@ #include "class/cl503b.h" #include //FERMI_VASPACE_A -/*! - * @brief Binds local BFID for SR-IOV P2P requests - * - * NOTE: This call will be dispatched to the Physical RM of the - * GPU represented by pGpu. Be sure to pass the GPU - * you are intending to program (local or remote). - * - * @param[in] pGpu GPU to dispatch the bind call to - * @param[in] gfid GFID to bind in the P2P source GPU - * @param[in] peerId Peer ID of the P2P destination GPU - */ -static NV_STATUS -s_p2papiBindLocalGfid(OBJGPU *pGpu, NvU32 gfid, NvU32 peerId) -{ - NV_STATUS status; - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - - NV2080_CTRL_INTERNAL_BUS_BIND_LOCAL_GFID_FOR_P2P_PARAMS params = {0}; - - params.localGfid = gfid; - params.peerId = peerId; - - status = pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, - NV2080_CTRL_CMD_INTERNAL_BUS_BIND_LOCAL_GFID_FOR_P2P, - ¶ms, sizeof(params)); - return status; -} - -/*! - * @brief Binds remote GFID for SR-IOV P2P requests - * - * NOTE: This call will be dispatched to the Physical RM of the - * GPU represented by pGpu. Be sure to pass the GPU - * you are intending to program (local or remote). - * - * @param[in] pGpu GPU to dispatch the bind call to - * @param[in] gfid GFID to bind in the P2P destination GPU - */ -static NV_STATUS -s_p2papiBindRemoteGfid(OBJGPU *pGpu, NvU32 gfid) -{ - - NV_STATUS status; - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - - NV2080_CTRL_INTERNAL_BUS_BIND_REMOTE_GFID_FOR_P2P_PARAMS params = {0}; - - params.remoteGfid = gfid; - - status = pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, - NV2080_CTRL_CMD_INTERNAL_BUS_BIND_REMOTE_GFID_FOR_P2P, - ¶ms, sizeof(params)); - return status; -} - - NV_STATUS p2papiConstruct_IMPL ( @@ -101,7 +45,6 @@ p2papiConstruct_IMPL ) { NvHandle hClient; - NvHandle hP2P; Subdevice *pSubDevice; Subdevice *pPeerSubDevice; NvU32 subDevicePeerIdMask; @@ -113,7 +56,6 @@ p2papiConstruct_IMPL NvHandle hPeerDevice; NvHandle hSubDevice; NvHandle hPeerSubDevice; - PNODE pNode; OBJGPU *pGpu; OBJGPU *pLocalGpu; KernelBus *pLocalKernelBus; @@ -122,20 +64,17 @@ p2papiConstruct_IMPL KernelBus *pRemoteKernelBus; KernelNvlink *pRemoteKernelNvlink; NV_STATUS status; - NvU32 gpuMask; NvBool bP2PWriteCapable = NV_FALSE; NvBool bP2PReadCapable = NV_FALSE; NV503B_ALLOC_PARAMETERS *pNv503bAllocParams = pParams->pAllocParams; - NvU32 gfid; - Device *pLocalDevice; - NvBool bRegisteredP2P = NV_FALSE; - NvBool bRegisteredPeerP2P = NV_FALSE; NvU32 flags = pNv503bAllocParams->flags; NvBool bSpaAccessOnly = FLD_TEST_DRF(503B, _FLAGS, _P2P_TYPE, _SPA, flags); P2P_CONNECTIVITY p2pConnectionType = P2P_CONNECTIVITY_UNKNOWN; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS *pP2pCapsParams; + NvU32 p2pCaps; hClient = pParams->hClient; - hP2P = pParams->hResource; subDevicePeerIdMask = pNv503bAllocParams->subDevicePeerIdMask; peerSubDevicePeerIdMask = pNv503bAllocParams->peerSubDevicePeerIdMask; @@ -217,15 +156,57 @@ p2papiConstruct_IMPL pLocalKernelBus = GPU_GET_KERNEL_BUS(pLocalGpu); pRemoteKernelBus = GPU_GET_KERNEL_BUS(pRemoteGpu); + pP2pCapsParams = portMemAllocStackOrHeap(sizeof(*pP2pCapsParams)); + if (pP2pCapsParams == NULL) + { + return NV_ERR_NO_MEMORY; + } + + portMemSet(pP2pCapsParams, 0, sizeof(*pP2pCapsParams)); + + pP2pCapsParams->gpuCount = 2; + pP2pCapsParams->gpuIds[0] = pLocalGpu->gpuId; + pP2pCapsParams->gpuIds[1] = pRemoteGpu->gpuId; + + NV_CHECK_OK_OR_ELSE(status, LEVEL_ERROR, + pRmApi->Control(pRmApi, hClient, hClient, + NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2, + pP2pCapsParams, sizeof(*pP2pCapsParams)), + portMemFreeStackOrHeap(pP2pCapsParams); + return status); + + bP2PWriteCapable = REF_VAL(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED, pP2pCapsParams->p2pCaps); + bP2PReadCapable = REF_VAL(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED, pP2pCapsParams->p2pCaps); + + p2pCaps = pP2pCapsParams->p2pCaps; + + portMemFreeStackOrHeap(pP2pCapsParams); + + if (REF_VAL(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED, p2pCaps)) + p2pConnectionType = P2P_CONNECTIVITY_C2C; + // It's impossible to detect P2P_CONNECTIVITY_NVLINK_INDIRECT connectivity. + // There is no difference between NVLINK and NVLINK_INDIRECT in P2PApi creation path, + // so always use P2P_CONNECTIVITY_NVLINK. + else if (REF_VAL(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED, p2pCaps)) + p2pConnectionType = P2P_CONNECTIVITY_NVLINK; + else if (REF_VAL(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED, p2pCaps)) + p2pConnectionType = P2P_CONNECTIVITY_PCIE_BAR1; + else if (REF_VAL(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED, p2pCaps)) + p2pConnectionType = P2P_CONNECTIVITY_PCIE; + else + { + NV_PRINTF(LEVEL_ERROR, "Unknown connection type\n"); + return NV_ERR_NOT_SUPPORTED; + } + // // Allocate P2P PCIE Mailbox areas if all of the following conditions occur: // - P2P reads or/and writes are supported // - The P2P connection is PCIE Mailbox based // - gpuMask = NVBIT(pLocalGpu->gpuInstance) | NVBIT(pRemoteGpu->gpuInstance); - if ((p2pGetCaps(gpuMask, &bP2PWriteCapable, &bP2PReadCapable, &p2pConnectionType) == NV_OK) && - (bP2PWriteCapable || bP2PReadCapable) && - (p2pConnectionType == P2P_CONNECTIVITY_PCIE)) + + if ((bP2PWriteCapable || bP2PReadCapable) && + p2pConnectionType == P2P_CONNECTIVITY_PCIE) { status = kbusSetP2PMailboxBar1Area_HAL(pLocalGpu, pLocalKernelBus, pNv503bAllocParams->mailboxBar1Addr, @@ -294,57 +275,51 @@ p2papiConstruct_IMPL } // check to see if a p2p mapping between these two subdevices already exist - if (NV_OK == btreeSearch(hPeerSubDevice, &pNode, - pSubDevice->pP2PMappingList) && - !IsGP100orBetter(pLocalGpu)) + if (!IsGP100orBetter(pLocalGpu)) { - NV_PRINTF(LEVEL_INFO, - "Mapping already exists between the two subdevices (0x%08x), (0x%08x). " - "Multiple mappings not supported on pre-PASCAL GPUs\n", - hSubDevice, hPeerSubDevice); - return NV_ERR_INVALID_ARGUMENT; + RS_ORDERED_ITERATOR iter; + P2PApi *pOtherP2PApi = NULL; + + iter = clientRefOrderedIter(pCallContext->pClient, NULL /*pScoreRef*/, + classId(P2PApi), NV_TRUE /*bExactMatch*/); + while (clientRefOrderedIterNext(iter.pClient, &iter)) + { + pOtherP2PApi = dynamicCast(iter.pResourceRef->pResource, P2PApi); + if (pOtherP2PApi == NULL) + return NV_ERR_INVALID_OBJECT_HANDLE; + + if (pP2PApi != pOtherP2PApi && + ((pLocalGpu == pOtherP2PApi->peer1 && pRemoteGpu == pOtherP2PApi->peer2) || + (pLocalGpu == pOtherP2PApi->peer2 && pRemoteGpu == pOtherP2PApi->peer1))) + { + NV_PRINTF(LEVEL_INFO, + "Mapping already exists between the two subdevices (0x%08x), (0x%08x). " + "Multiple mappings not supported on pre-PASCAL GPUs\n", + hSubDevice, hPeerSubDevice); + return NV_ERR_INVALID_ARGUMENT; + } + } } - pP2PApi->Node.keyStart = hP2P; - pP2PApi->Node.keyEnd = hP2P; - pP2PApi->Node.Data = pP2PApi; - pP2PApi->peer1 = pSubDevice; - pP2PApi->peer2 = pPeerSubDevice; + pP2PApi->peer1 = pLocalGpu; + pP2PApi->peer2 = pRemoteGpu; pP2PApi->attributes = DRF_NUM(_P2PAPI, _ATTRIBUTES, _CONNECTION_TYPE, p2pConnectionType); pP2PApi->attributes |= bSpaAccessOnly ? DRF_DEF(_P2PAPI, _ATTRIBUTES, _LINK_TYPE, _SPA) : DRF_DEF(_P2PAPI, _ATTRIBUTES, _LINK_TYPE, _GPA); - mapInit(&pP2PApi->dmaMappingMap, portMemAllocatorGetGlobalNonPaged()); - // store away the p2pinfo within subdevice info for easy retrieval - status = subdeviceAddP2PApi(pSubDevice, pP2PApi); - if (NV_OK != status) - goto fail; - - bRegisteredP2P = NV_TRUE; - - // for loopback on same subdevice, we only need to store it once - if (hSubDevice != hPeerSubDevice) - { - status = subdeviceAddP2PApi(pPeerSubDevice, pP2PApi); - if (NV_OK != status) - goto fail; - - bRegisteredPeerP2P = NV_TRUE; - } - - if (!IS_VIRTUAL(pLocalGpu)) + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pLocalGpu) || !IS_VIRTUAL(pLocalGpu)) { // setup the p2p resources - status = kbusCreateP2PMapping_HAL(pLocalGpu, pLocalKernelBus, pRemoteGpu, - pRemoteKernelBus, &peer1, &peer2, - pP2PApi->attributes); - if (NV_OK != status) - goto fail; + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kbusCreateP2PMapping_HAL(pLocalGpu, pLocalKernelBus, pRemoteGpu, + pRemoteKernelBus, &peer1, &peer2, + pP2PApi->attributes)); } pGpu = pLocalGpu; - if (IS_VIRTUAL_WITH_SRIOV(pGpu) && + if (!IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && + IS_VIRTUAL_WITH_SRIOV(pGpu) && gpuIsSplitVasManagementServerClientRmEnabled(pGpu)) { NvU32 gpu0Instance = gpuGetInstance(pLocalGpu); @@ -378,18 +353,12 @@ p2papiConstruct_IMPL NV_PRINTF(LEVEL_ERROR, "GPU%d: peerID not available for NVLink P2P\n", gpu0Instance); - status = NV_ERR_GENERIC; - goto fail; + return NV_ERR_GENERIC; } // Reserve the peer ID for NVLink use - status = kbusReserveP2PPeerIds_HAL(pLocalGpu, pLocalKernelBus, NVBIT(peer1)); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "Failed to reserve peer1, status=0x%x\n", status); - goto fail; - } + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kbusReserveP2PPeerIds_HAL(pLocalGpu, pLocalKernelBus, NVBIT(peer1))); // Get the peer ID pGpu1 should use for P2P over NVLINK to pGpu0 peer2 = kbusGetUnusedPeerId_HAL(pRemoteGpu, pRemoteKernelBus); @@ -399,25 +368,18 @@ p2papiConstruct_IMPL NV_PRINTF(LEVEL_ERROR, "GPU%d: peerID not available for NVLink P2P\n", gpu1Instance); - status = NV_ERR_GENERIC; - goto fail; + return NV_ERR_GENERIC; } // Reserve the peer ID for NVLink use - status = kbusReserveP2PPeerIds_HAL(pRemoteGpu, pRemoteKernelBus, NVBIT(peer2)); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "Failed to reserve peer2, status=0x%x\n", status); - goto fail; - } + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kbusReserveP2PPeerIds_HAL(pRemoteGpu, pRemoteKernelBus, NVBIT(peer2))); } else { NV_PRINTF(LEVEL_ERROR, "Unexpected state, either of the peer ID is invalid \n"); - status = NV_ERR_GENERIC; - goto fail; + return NV_ERR_GENERIC; } update_mask: @@ -502,8 +464,10 @@ update_params: pP2PApi->peerId1 = peer1; pP2PApi->peerId2 = peer2; + pP2PApi->localGfid = GPU_GFID_PF; + pP2PApi->remoteGfid = GPU_GFID_PF; - if (IS_VIRTUAL(pLocalGpu)) + if (!IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pLocalGpu) && IS_VIRTUAL(pLocalGpu)) { NV_RM_RPC_ALLOC_OBJECT(pLocalGpu, pParams->hClient, @@ -513,61 +477,7 @@ update_params: pNv503bAllocParams, status); if (status != NV_OK) - goto fail; - } - - // - // program the GFID for HSHUB when, - // 1. In hypervisor mode, - // 2. SRIOV is enabled - // - if (!IS_VIRTUAL(pLocalGpu)) - { - NV_ASSERT_OK(deviceGetByHandle(pClient, hDevice, &pLocalDevice)); - NV_ASSERT_OK_OR_RETURN(vgpuGetGfidFromDeviceInfo(pLocalGpu, pLocalDevice, &gfid)); - - { - if (!bSpaAccessOnly) - { - if (gpuIsSriovEnabled(pLocalGpu)) - { - NV_PRINTF(LEVEL_INFO, "Trying to register GPU:%x gfid: %x for P2P access with peerId: %x\n", - pLocalGpu->deviceInstance, gfid, peer1); - NV_ASSERT_OK_OR_RETURN(s_p2papiBindLocalGfid(pLocalGpu, gfid, peer1)); - if (hSubDevice != hPeerSubDevice) - { - NV_PRINTF(LEVEL_INFO, "Trying to register GPU:%x gfid: %x for remote access \n", - pLocalGpu->deviceInstance, gfid); - - NV_ASSERT_OK_OR_RETURN(s_p2papiBindRemoteGfid(pLocalGpu, gfid)); - } - } - - if (gpuIsSriovEnabled(pRemoteGpu)) - { - if (hDevice != hPeerDevice) - { - Device *pRemoteDevice; - - NV_ASSERT_OK(deviceGetByHandle(pClient, hPeerDevice, &pRemoteDevice)); - NV_ASSERT_OK_OR_RETURN(vgpuGetGfidFromDeviceInfo(pRemoteGpu, pRemoteDevice, &gfid)); - } - - if (hSubDevice != hPeerSubDevice) - { - NV_PRINTF(LEVEL_INFO, "Trying to register GPU:%x gfid: %x for P2P access with peerId: %x\n", - pRemoteGpu->deviceInstance, gfid, peer2); - - NV_ASSERT_OK_OR_RETURN(s_p2papiBindLocalGfid(pRemoteGpu, gfid, peer2)); - } - - NV_PRINTF(LEVEL_INFO, "Trying to register GPU:%x gfid: %x for remote access \n", - pRemoteGpu->deviceInstance, gfid); - - NV_ASSERT_OK_OR_RETURN(s_p2papiBindRemoteGfid(pRemoteGpu, gfid)); - } - } - } + return status; } // @@ -580,17 +490,8 @@ update_params: { goto remote_fla_bind; } - NV_ASSERT_OK(deviceGetByHandle(pClient, hDevice, &pLocalDevice)); - NV_ASSERT_OK_OR_RETURN(vgpuGetGfidFromDeviceInfo(pLocalGpu, pLocalDevice, &gfid)); - - status = kbusSetupBindFla_HAL(pLocalGpu, pLocalKernelBus, gfid); - - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "failed binding instblk for FLA, status=0x%x\n", status); - goto fail; - } + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kbusSetupBindFla_HAL(pLocalGpu, pLocalKernelBus, pP2PApi->localGfid)); } remote_fla_bind: @@ -603,21 +504,18 @@ remote_fla_bind: { return status; } - Device *pRemoteDevice; - NV_ASSERT_OK(deviceGetByHandle(pClient, hPeerDevice, &pRemoteDevice)); - NV_ASSERT_OK_OR_RETURN(vgpuGetGfidFromDeviceInfo(pRemoteGpu, pRemoteDevice, &gfid)); - - status = kbusSetupBindFla_HAL(pRemoteGpu, pRemoteKernelBus, gfid); - - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "failed binding instblk for FLA, status=0x%x\n", status); - goto fail; - } + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kbusSetupBindFla_HAL(pRemoteGpu, pRemoteKernelBus, pP2PApi->remoteGfid)); } } + // Adding P2PApi as a dependant of 2 Subdevices, P2PApi must be destroyed before OBJGPU destruction + NV_ASSERT_OK_OR_RETURN(refAddDependant(RES_GET_REF(pSubDevice), pCallContext->pResourceRef)); + if (hDevice != hPeerDevice) + { + NV_ASSERT_OK_OR_RETURN(refAddDependant(RES_GET_REF(pPeerSubDevice), pCallContext->pResourceRef)); + } + if (status == NV_OK) { NV_CHECK_OR_RETURN(LEVEL_ERROR, pLocalKernelBus->totalP2pObjectsAliveRefCount < NV_U32_MAX, NV_ERR_INSUFFICIENT_RESOURCES); @@ -626,16 +524,6 @@ remote_fla_bind: pRemoteKernelBus->totalP2pObjectsAliveRefCount++; } return status; - -fail: - - if (bRegisteredPeerP2P) - subdeviceDelP2PApi(pPeerSubDevice, pP2PApi); - - if (bRegisteredP2P) - subdeviceDelP2PApi(pSubDevice, pP2PApi); - - return status; } void @@ -647,167 +535,24 @@ p2papiDestruct_IMPL CALL_CONTEXT *pCallContext; RS_RES_FREE_PARAMS_INTERNAL *pParams; NvHandle hClient; + OBJGPU *pLocalGpu; + KernelBus *pLocalKernelBus; + OBJGPU *pRemoteGpu; + KernelBus *pRemoteKernelBus; + RsClient *pClient; + NV_STATUS status = NV_OK; resGetFreeParams(staticCast(pP2PApi, RsResource), &pCallContext, &pParams); hClient = pParams->hClient; - // remove any resources associated with this P2P object before freeing it - pParams->status = CliInvalidateP2PInfo(hClient, pP2PApi); -} + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + serverGetClientUnderLock(&g_resServ, hClient, &pClient), end); -NV_STATUS CliAddP2PDmaMappingInfo -( - NvHandle hClient, - NvHandle hDevice, - NvU32 subDeviceInst, - NvHandle hPeerDevice, - NvU32 peerSubDeviceInst, - PCLI_DMA_MAPPING_INFO pDmaMapping -) -{ - PNODE pNode; - NV_STATUS status; - PCLI_P2P_INFO pP2PInfo = NULL; - Subdevice *pSubDevice; - Subdevice *pPeerSubDevice; - PCLI_P2P_DMA_MAPPING_INFO pP2PDmaMappingInfo; - NvHandle hSubDevice, hPeerSubDevice; - RsClient *pClient; + if (NULL == pP2PApi->peer1 || NULL == pP2PApi->peer2) + return; - if (NV_OK != serverGetClientUnderLock(&g_resServ, hClient, &pClient)) - return NV_ERR_INVALID_CLIENT; - - if (NULL == pDmaMapping) - return NV_ERR_INVALID_ARGUMENT; - - // Find the subdevices for local and peer devices - status = subdeviceGetByInstance(pClient, - hDevice, - subDeviceInst, - &pSubDevice); - if ((NV_OK != status) || (NULL == pSubDevice)) - return status; - - hSubDevice = RES_GET_HANDLE(pSubDevice); - - status = subdeviceGetByInstance(pClient, - hPeerDevice, - peerSubDeviceInst, - &pPeerSubDevice); - if ((NV_OK != status) || (NULL == pPeerSubDevice)) - return status; - - hPeerSubDevice = RES_GET_HANDLE(pPeerSubDevice); - - // - // Find a P2P object that maps the two subdevices in question, just use the - // first available. If no such object exists, then this dmaMapping cannot - // be made. - // - status = btreeSearch(hPeerSubDevice, &pNode, pSubDevice->pP2PMappingList); - if (status == NV_OK) - { - PCLI_P2P_INFO_LIST *pP2PInfoList = pNode->Data; - - NV_ASSERT(listHead(pP2PInfoList) != NULL); - pP2PInfo = *listHead(pP2PInfoList); - } - - if (pP2PInfo == NULL) - { - NV_PRINTF(LEVEL_ERROR, - "No P2P mapping between subdevices (0x%08x)and (0x%08x) on the client (0x%08x)\n", - hSubDevice, hPeerSubDevice, hClient); - return status; - } - - pNode = NULL; - - // - // It may happen that subdevices on both sides of P2P object will try - // to map the same virtual address value. We handle this by using - // CLI_P2P_DMA_MAPPING_INFO to store references to each DMA mapping at the - // address. - // - pP2PDmaMappingInfo = mapFind(&pP2PInfo->dmaMappingMap, pDmaMapping->DmaOffset); - - if (pP2PDmaMappingInfo == NULL) - { - pP2PDmaMappingInfo = mapInsertNew(&pP2PInfo->dmaMappingMap, pDmaMapping->DmaOffset); - if (pP2PDmaMappingInfo == NULL) - { - return NV_ERR_INSUFFICIENT_RESOURCES; - } - portMemSet(pP2PDmaMappingInfo, 0, sizeof(CLI_P2P_DMA_MAPPING_INFO)); - } - else - { - if (pP2PDmaMappingInfo->pPeer1Info != NULL && - pP2PDmaMappingInfo->pPeer2Info != NULL) - { - NV_PRINTF(LEVEL_ERROR, "P2P DMA mapping is already allocated!\n"); - return NV_ERR_INVALID_REQUEST; - } - } - - if (pSubDevice == pP2PInfo->peer1) - { - pP2PDmaMappingInfo->pPeer1Info = pDmaMapping; - } - else - { - NV_ASSERT(pSubDevice == pP2PInfo->peer2); - pP2PDmaMappingInfo->pPeer2Info = pDmaMapping; - } - - pDmaMapping->pP2PInfo = pP2PInfo; - return NV_OK; -} - -NV_STATUS CliInvalidateP2PInfo -( - NvHandle hClient, - PCLI_P2P_INFO pP2PInfo -) -{ - OBJGPU *pLocalGpu; - KernelBus *pLocalKernelBus; - OBJGPU *pRemoteGpu; - KernelBus *pRemoteKernelBus; - RsClient *pClient; - NvHandle hSubDevice; - NvHandle hPeerSubDevice; - NvHandle hDevice; - NvHandle hPeerDevice; - NV_STATUS status = NV_OK; - - if (NV_OK != serverGetClientUnderLock(&g_resServ, hClient, &pClient)) - return NV_ERR_INVALID_CLIENT; - - if (NULL == pP2PInfo) - return NV_ERR_INVALID_OBJECT_HANDLE; - - if (NULL == pP2PInfo->peer1 || NULL == pP2PInfo->peer2) - return NV_OK; - - hSubDevice = RES_GET_HANDLE(pP2PInfo->peer1); - hPeerSubDevice = RES_GET_HANDLE(pP2PInfo->peer2); - - // Find the gpu for the subdevices of this P2P object - if (CliSetSubDeviceContext(hClient, hSubDevice, &hDevice, &pLocalGpu) != NV_OK || - NULL == pLocalGpu) - { - NV_PRINTF(LEVEL_ERROR, "Failed to find GPU for hSubDevice (0x%08x)\n", - hSubDevice); - return NV_ERR_INVALID_DEVICE; - } - if (CliSetSubDeviceContext(hClient, hPeerSubDevice, &hPeerDevice, &pRemoteGpu) != NV_OK || - NULL == pRemoteGpu) - { - NV_PRINTF(LEVEL_ERROR, "Failed to find GPU for hSubDevice (0x%08x)\n", - hPeerSubDevice); - return NV_ERR_INVALID_DEVICE; - } + pLocalGpu = pP2PApi->peer1; + pRemoteGpu = pP2PApi->peer2; pLocalKernelBus = GPU_GET_KERNEL_BUS(pLocalGpu); pRemoteKernelBus = GPU_GET_KERNEL_BUS(pRemoteGpu); @@ -820,154 +565,21 @@ NV_STATUS CliInvalidateP2PInfo if (pRemoteKernelBus->totalP2pObjectsAliveRefCount > 0) pRemoteKernelBus->totalP2pObjectsAliveRefCount--; - if (!IS_VIRTUAL(pLocalGpu)) + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pLocalGpu) || !IS_VIRTUAL(pLocalGpu)) { - // remove any mailbox resources associated with this mapping + // remove any resources associated with this mapping status = kbusRemoveP2PMapping_HAL(pLocalGpu, pLocalKernelBus, pRemoteGpu, pRemoteKernelBus, - pP2PInfo->peerId1, pP2PInfo->peerId2, - pP2PInfo->attributes); + pP2PApi->peerId1, pP2PApi->peerId2, + pP2PApi->attributes); } - subdeviceDelP2PApi(pP2PInfo->peer1, pP2PInfo); - if (hSubDevice != hPeerSubDevice) - { - subdeviceDelP2PApi(pP2PInfo->peer2, pP2PInfo); - } - - pP2PInfo->peer1 = NULL; - pP2PInfo->peer2 = NULL; - mapDestroy(&pP2PInfo->dmaMappingMap); + pP2PApi->peer1 = NULL; + pP2PApi->peer2 = NULL; kbusUnsetP2PMailboxBar1Area_HAL(pLocalGpu, pLocalKernelBus); kbusUnsetP2PMailboxBar1Area_HAL(pRemoteGpu, pRemoteKernelBus); - return status; -} - -NV_STATUS CliDelP2PDmaMappingInfo -( - NvHandle hClient, - PCLI_DMA_MAPPING_INFO pDmaMapping -) -{ - PCLI_P2P_INFO pP2PInfo; - PCLI_P2P_DMA_MAPPING_INFO pP2PDmaMappingInfo; - - NV_ASSERT_OR_RETURN(pDmaMapping != NULL, NV_ERR_INVALID_ARGUMENT); - - pP2PInfo = pDmaMapping->pP2PInfo; - if (NULL == pP2PInfo || mapCount(&pP2PInfo->dmaMappingMap) == 0) - return NV_ERR_INVALID_ARGUMENT; - - pP2PDmaMappingInfo = mapFind(&pP2PInfo->dmaMappingMap, pDmaMapping->DmaOffset); - if (pP2PDmaMappingInfo != NULL) - { - if (pP2PDmaMappingInfo->pPeer1Info == pDmaMapping) - { - pP2PDmaMappingInfo->pPeer1Info = NULL; - } - else if (pP2PDmaMappingInfo->pPeer2Info == pDmaMapping) - { - pP2PDmaMappingInfo->pPeer2Info = NULL; - } - - if (pP2PDmaMappingInfo->pPeer1Info == NULL && - pP2PDmaMappingInfo->pPeer2Info == NULL) - { - mapRemove(&pP2PInfo->dmaMappingMap, pP2PDmaMappingInfo); - } - } - - pDmaMapping->pP2PInfo = NULL; - return NV_OK; -} - -NV_STATUS CliUpdateP2PDmaMappingInList -( - NvHandle hClient, - PCLI_DMA_MAPPING_INFO pDmaMapping, - NvU64 dmaOffset -) -{ - PCLI_P2P_INFO pP2PInfo; - PCLI_P2P_DMA_MAPPING_INFO pP2PDmaMappingInfo; - PCLI_P2P_DMA_MAPPING_INFO pNewP2PDmaMappingInfo; - PCLI_DMA_MAPPING_INFO pPeer1Info = NULL; - PCLI_DMA_MAPPING_INFO pPeer2Info = NULL; - - NV_ASSERT_OR_RETURN(pDmaMapping != NULL, NV_ERR_INVALID_ARGUMENT); - - pP2PInfo = pDmaMapping->pP2PInfo; - if (NULL == pP2PInfo || mapCount(&pP2PInfo->dmaMappingMap) == 0) - return NV_ERR_INVALID_ARGUMENT; - - pP2PDmaMappingInfo = mapFind(&pP2PInfo->dmaMappingMap, pDmaMapping->DmaOffset); - if (pP2PDmaMappingInfo != NULL) - { - // Cache the old values - pPeer1Info = pP2PDmaMappingInfo->pPeer1Info; - pPeer2Info = pP2PDmaMappingInfo->pPeer2Info; - - // free the old dma mapping Info - mapRemove(&pP2PInfo->dmaMappingMap, pP2PDmaMappingInfo); - - // allocate the new object and insert in the list - pNewP2PDmaMappingInfo = mapInsertNew(&pP2PInfo->dmaMappingMap, dmaOffset); - if (pNewP2PDmaMappingInfo == NULL) - { - if (mapFind(&pP2PInfo->dmaMappingMap, dmaOffset) != NULL) - { - return NV_ERR_INSERT_DUPLICATE_NAME; - } - else - { - return NV_ERR_INSUFFICIENT_RESOURCES; - } - } - portMemSet(pNewP2PDmaMappingInfo, 0, sizeof(CLI_P2P_DMA_MAPPING_INFO)); - pNewP2PDmaMappingInfo->pPeer1Info = pPeer1Info; - pNewP2PDmaMappingInfo->pPeer2Info = pPeer2Info; - - } - - return NV_OK; -} - -NV_STATUS CliFreeSubDeviceP2PList -( - Subdevice *pSubdevice, - CALL_CONTEXT *pCallContext -) -{ - RsClient *pRsClient = pCallContext->pClient; - RsResourceRef *pResourceRef = pCallContext->pResourceRef; - PNODE pNode; - NV_STATUS status; - RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); - - if (pResourceRef == NULL) - return NV_OK; - - while (NULL != (pNode = pSubdevice->pP2PMappingList)) - { - PCLI_P2P_INFO_LIST *pP2PInfoList = pNode->Data; - PCLI_P2P_INFO *ppP2PInfo; - PCLI_P2P_INFO *ppP2PInfoNext; - - for (ppP2PInfo = listHead(pP2PInfoList); - ppP2PInfo != NULL; - ppP2PInfo = ppP2PInfoNext) - { - ppP2PInfoNext = listNext(pP2PInfoList, ppP2PInfo); - - status = pRmApi->Free(pRmApi, pRsClient->hClient, (NvHandle)(*ppP2PInfo)->Node.keyStart); - if (NV_OK != status) - { - return status; - } - } - } - - return NV_OK; +end: + pParams->status = status; } diff --git a/src/nvidia/src/kernel/gpu/bus/third_party_p2p.c b/src/nvidia/src/kernel/gpu/bus/third_party_p2p.c index 05753cea1..0b5667dd4 100644 --- a/src/nvidia/src/kernel/gpu/bus/third_party_p2p.c +++ b/src/nvidia/src/kernel/gpu/bus/third_party_p2p.c @@ -22,6 +22,7 @@ */ #include "core/core.h" +#include "core/locks.h" #include "gpu/gpu.h" #include "gpu/bus/third_party_p2p.h" #include "platform/p2p/p2p_caps.h" @@ -937,13 +938,14 @@ static NV_STATUS _thirdpartyp2pDelMappingInfoByKey 0, pExtentInfo->fbApertureOffset, status); } - else + else if ((status = rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK) { status = kbusUnmapFbAperture_HAL(pGpu, pKernelBus, pExtentInfo->pMemDesc, pExtentInfo->fbApertureOffset, pExtentInfo->length, BUS_MAP_FB_FLAGS_MAP_UNICAST); + rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); } NV_ASSERT(status == NV_OK); diff --git a/src/nvidia/src/kernel/gpu/ccu/arch/hopper/kernel_ccu_gh100.c b/src/nvidia/src/kernel/gpu/ccu/arch/hopper/kernel_ccu_gh100.c new file mode 100644 index 000000000..284aab4a1 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/ccu/arch/hopper/kernel_ccu_gh100.c @@ -0,0 +1,104 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +/********************* Chip Specific HAL CCU Routines *********************\ + * * + * The HOPPER specific HAL CCU routines reside in this file. * + * * +\**************************************************************************/ + +#include "kernel/gpu/ccu/kernel_ccu.h" + +/*! + * Assign CCU shared buffer to mig inst + * +* @param[in] pGpu GPU object pointer +* @param[in] pKernelCcu KernelCcu object pointer +* @param[in] bMigEnabled Mig enabled + * + * @return NV_OK + * @return NV_ERR_INSUFFICIENT_RESOURCES + */ +NV_STATUS +kccuMigShrBufHandler_GH100 +( + OBJGPU *pGpu, + KernelCcu *pKernelCcu, + NvBool bMigEnabled +) +{ + NV_STATUS status = NV_OK; + + NV_PRINTF(LEVEL_INFO, "Create/delete CCU shared buffers for mig (migEnabled:%u)\n", + bMigEnabled); + + if (bMigEnabled) + { + if (!pKernelCcu->bMigShrBufAllocated) + { + status = kccuInitMigSharedBuffer(pGpu, pKernelCcu); + if (status == NV_OK) + { + pKernelCcu->bMigShrBufAllocated = NV_TRUE; + kccuShrBufInfoToCcu(pGpu, pKernelCcu, CCU_MIG_SHRBUF_ID_START); + } + } + + return status; + } + + if (pKernelCcu->bMigShrBufAllocated) + { + NvU32 i = 0; + NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS params = { 0 }; + + // Internal RM api ctrl call to physical RM to unmap shared buffer memdesc + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + params.bMigShrBuf = NV_TRUE; + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP, + ¶ms, + sizeof(params)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "CCU mig memdesc unmap request failed with status: 0x%x\n", status); + } + + // Free mig shared buffer + for (i = CCU_MIG_SHRBUF_ID_START; i < CCU_SHRBUF_COUNT_MAX; i++) + { + if (pKernelCcu->pMemDesc[i] != NULL) + { + kccuShrBufIdxCleanup(pGpu, pKernelCcu, i); + } + } + + pKernelCcu->bMigShrBufAllocated = NV_FALSE; + } + + return status; +} diff --git a/src/nvidia/src/kernel/gpu/ccu/kernel_ccu.c b/src/nvidia/src/kernel/gpu/ccu/kernel_ccu.c index e37770f12..cd79d3b87 100644 --- a/src/nvidia/src/kernel/gpu/ccu/kernel_ccu.c +++ b/src/nvidia/src/kernel/gpu/ccu/kernel_ccu.c @@ -106,7 +106,7 @@ _kccuAllocMemory if (pKernelCcu->shrBuf[idx].pCounterDstInfo == NULL || pKernelCcu->shrBuf[idx].pKernelMapInfo == NULL) { status = NV_ERR_NO_MEMORY; - NV_PRINTF(LEVEL_ERROR, "CCU port mem alloc failed for(%u) with status: 0x%x \r\n", idx, status); + NV_PRINTF(LEVEL_ERROR, "CCU port mem alloc failed for(%u) with status: 0x%x\n", idx, status); goto free_alloc; } portMemSet(pKernelCcu->shrBuf[idx].pCounterDstInfo, 0, sizeof(CCU_SHRBUF_INFO)); @@ -118,14 +118,14 @@ _kccuAllocMemory MEMDESC_FLAGS_USER_READ_ONLY); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "CCU memdescCreate failed for(%u) with status: 0x%x \r\n", idx, status); + NV_PRINTF(LEVEL_ERROR, "CCU memdescCreate failed for(%u) with status: 0x%x\n", idx, status); goto free_alloc; } pMemDesc = pKernelCcu->pMemDesc[idx]; if (pMemDesc == NULL) { - NV_PRINTF(LEVEL_ERROR, "CCU memdescCreate failed. memdesc for(%u) is NULL\r\n", idx); + NV_PRINTF(LEVEL_ERROR, "CCU memdescCreate failed. memdesc for(%u) is NULL\n", idx); goto free_alloc; } @@ -133,7 +133,7 @@ _kccuAllocMemory status = memdescAlloc(pMemDesc); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "CCU memdescAlloc failed for(%u) with status: 0x%x \r\n", idx, status); + NV_PRINTF(LEVEL_ERROR, "CCU memdescAlloc failed for(%u) with status: 0x%x\n", idx, status); memdescDestroy(pMemDesc); goto free_alloc; } @@ -144,7 +144,7 @@ _kccuAllocMemory &pKernelCcu->shrBuf[idx].pKernelMapInfo->priv); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "CCU memdescMap failed for(%u)with status: 0x%x \r\n", idx, status); + NV_PRINTF(LEVEL_ERROR, "CCU memdescMap failed for(%u)with status: 0x%x\n", idx, status); memdescFree(pMemDesc); memdescDestroy(pMemDesc); goto free_alloc; @@ -160,31 +160,63 @@ _kccuAllocMemory (NvU64 *)((NvUPtr)pKernelCcu->shrBuf[idx].pCounterDstInfo->pCounterBlock + counterBlockSize); pKernelCcu->shrBuf[idx].pCounterDstInfo->pSwizzId = (NvU8 *)((NvUPtr)pKernelCcu->shrBuf[idx].pCounterDstInfo->pTailTimeStamp + CCU_TIMESTAMP_SIZE); + pKernelCcu->shrBuf[idx].pCounterDstInfo->pComputeId = + (NvU8 *)((NvUPtr)pKernelCcu->shrBuf[idx].pCounterDstInfo->pSwizzId + CCU_MIG_SWIZZID_SIZE); pKernelCcu->shrBuf[idx].pCounterDstInfo->counterBlockSize = counterBlockSize; - // Set mig swizz-id to invalid - if (!NV_IS_MODS) + // Set mig swizz-id and compute-inst id to invalid + if (!RMCFG_FEATURE_MODS_FEATURES) { *pKernelCcu->shrBuf[idx].pCounterDstInfo->pSwizzId = CCU_MIG_INVALID_SWIZZID; + *pKernelCcu->shrBuf[idx].pCounterDstInfo->pComputeId = CCU_MIG_INVALID_COMPUTEID; } return NV_OK; free_alloc: - if (pKernelCcu->shrBuf[idx].pCounterDstInfo) - { - portMemFree(pKernelCcu->shrBuf[idx].pCounterDstInfo); - } - if (pKernelCcu->shrBuf[idx].pKernelMapInfo) - { - portMemFree(pKernelCcu->shrBuf[idx].pKernelMapInfo); - } + portMemFree(pKernelCcu->shrBuf[idx].pCounterDstInfo); + portMemFree(pKernelCcu->shrBuf[idx].pKernelMapInfo); return status; } /*! - * Free memory desc, shared buffer and class member memory + * Cleanup shared buffer and class member memory for given shared buffer index * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelCcu KernelCcu object pointer + * @param[in] idx MIG inst/for non-mig case idx is "0" + * + */ +void +kccuShrBufIdxCleanup_IMPL +( + OBJGPU *pGpu, + KernelCcu *pKernelCcu, + NvU32 idx +) +{ + MEMORY_DESCRIPTOR *pMemDesc = pKernelCcu->pMemDesc[idx]; + + NV_PRINTF(LEVEL_INFO, "Shared buffer unmap & free for idx(%u).\n", idx); + + memdescUnmap(pMemDesc, NV_TRUE, osGetCurrentProcess(), + pKernelCcu->shrBuf[idx].pKernelMapInfo->addr, + pKernelCcu->shrBuf[idx].pKernelMapInfo->priv); + memdescFree(pMemDesc); + memdescDestroy(pMemDesc); + + // Free class member memory + portMemFree(pKernelCcu->shrBuf[idx].pCounterDstInfo); + portMemFree(pKernelCcu->shrBuf[idx].pKernelMapInfo); + pKernelCcu->shrBuf[idx].pCounterDstInfo = NULL; + pKernelCcu->shrBuf[idx].pKernelMapInfo = NULL; + pKernelCcu->pMemDesc[idx] = NULL; +} + +/*! + * Unmap & free memory desc, shared buffer and class member memory + * + * @param[in] pGpu GPU object pointer * @param[in] pKernelCcu KernelCcu object pointer * */ @@ -197,49 +229,86 @@ _kccuUnmapAndFreeMemory { NvU32 i = 0; NV_STATUS status = NV_OK; + NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS params = { 0 }; NV_PRINTF(LEVEL_INFO, "KernelCcu: Unmap and free shared buffer\n"); - // Internal RM api ctrl call to physical RM to unmap shared buffer memdesc + // Internal RM api ctrl call to physical RM to unmap dev & mig shared buffer memdesc RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + params.bDevShrBuf = NV_TRUE; + params.bMigShrBuf = NV_TRUE; status = pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP, - NULL, - 0); + ¶ms, + sizeof(params)); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "CCU memdesc unmap request failed with status: 0x%x \r\n", status); + NV_PRINTF(LEVEL_ERROR, "CCU memdesc unmap request failed with status: 0x%x\n", status); } // Unmap & free mem desc for (i = 0; i < CCU_SHRBUF_COUNT_MAX; i++) { - MEMORY_DESCRIPTOR *pMemDesc = pKernelCcu->pMemDesc[i]; - - if (pMemDesc == NULL) - continue; - - memdescUnmap(pMemDesc, NV_TRUE, osGetCurrentProcess(), - pKernelCcu->shrBuf[i].pKernelMapInfo->addr, - pKernelCcu->shrBuf[i].pKernelMapInfo->priv); - memdescFree(pMemDesc); - memdescDestroy(pMemDesc); - - // Free class member memory - portMemFree(pKernelCcu->shrBuf[i].pCounterDstInfo); - portMemFree(pKernelCcu->shrBuf[i].pKernelMapInfo); - pKernelCcu->shrBuf[i].pCounterDstInfo = NULL; - pKernelCcu->shrBuf[i].pKernelMapInfo = NULL; + if (pKernelCcu->pMemDesc[i] != NULL) + { + kccuShrBufIdxCleanup(pGpu, pKernelCcu, i); + } } - - return; } /*! - * Create shared buffer for counter data + * Send shared buffer info to phy-RM/gsp + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelCcu KernelCcu object pointer + * @param[in] shrBufStartIdx Shared buffer start idx + * + * @return NV_OK on success, specific error code on failure. + */ +NV_STATUS +kccuShrBufInfoToCcu_IMPL +( + OBJGPU *pGpu, + KernelCcu *pKernelCcu, + NvU32 shrBufStartIdx +) +{ + NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS inParams = { 0 }; + NV_STATUS status = NV_OK; + NvU32 idx = 0; + + NV_PRINTF(LEVEL_INFO, "Send shared buffer info to phyRM/gsp to map.\n"); + + for (idx = shrBufStartIdx; idx < CCU_SHRBUF_COUNT_MAX; idx++) + { + if (pKernelCcu->pMemDesc[idx] != NULL) + { + inParams.phyAddr[idx] = memdescGetPhysAddr(pKernelCcu->pMemDesc[idx], AT_GPU, 0); + } + } + + // Internal RM api ctrl call to physical RM to map shared buffer memdesc + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_CCU_MAP, + &inParams, + sizeof(inParams)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "CCU memdesc map request failed with status: 0x%x\n", status); + } + + return status; +} + +/*! + * Create shared buffer for device counters * * @param[in] pGpu GPU object pointer * @param[in] pKernelCcu KernelCcu object pointer @@ -247,7 +316,37 @@ _kccuUnmapAndFreeMemory * @return NV_OK on success, specific error code on failure. */ static NV_STATUS -_kccuInitSharedBuffer +_kccuInitDevSharedBuffer +( + OBJGPU *pGpu, + KernelCcu *pKernelCcu +) +{ + NV_STATUS status = NV_OK; + + NV_PRINTF(LEVEL_INFO, "Init shared buffer for device counters.\n"); + + // Allocate shared buffer for device counters + status = _kccuAllocMemory(pGpu, pKernelCcu, CCU_DEV_SHRBUF_ID, CCU_GPU_SHARED_BUFFER_SIZE_MAX, + CCU_PER_GPU_COUNTER_Q_SIZE); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "CCU memory allocation failed with status: 0x%x\n", status); + } + + return status; +} + +/*! + * Create shared buffer for mig counters + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelCcu KernelCcu object pointer + * + * @return NV_OK on success, specific error code on failure. + */ +NV_STATUS +kccuInitMigSharedBuffer_IMPL ( OBJGPU *pGpu, KernelCcu *pKernelCcu @@ -256,20 +355,7 @@ _kccuInitSharedBuffer NV_STATUS status = NV_OK; NvU32 idx; - if (IS_VIRTUAL(pGpu)) - { - return NV_ERR_NOT_SUPPORTED; - } - - // Allocate shared buffer for device counters - - status = _kccuAllocMemory(pGpu, pKernelCcu, CCU_DEV_SHRBUF_ID, CCU_GPU_SHARED_BUFFER_SIZE_MAX, - CCU_PER_GPU_COUNTER_Q_SIZE); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "CCU memory allocation failed with status: 0x%x \r\n", status); - return status; - } + NV_PRINTF(LEVEL_INFO, "Init shared buffer for mig counters.\n"); // Allocate shared buffer for each mig gpu instance for (idx = CCU_MIG_SHRBUF_ID_START; idx < CCU_SHRBUF_COUNT_MAX; idx++) @@ -278,7 +364,7 @@ _kccuInitSharedBuffer CCU_MIG_INST_COUNTER_Q_SIZE); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "CCU memory allocation failed for idx(%u) with status: 0x%x \r\n", + NV_PRINTF(LEVEL_ERROR, "CCU memory allocation failed for idx(%u) with status: 0x%x\n", idx, status); // Free shared buffer & mem desc, for earlier mig inst & device @@ -308,44 +394,37 @@ NV_STATUS kccuStateLoad_IMPL NvU32 flags ) { - NvU32 idx = 0; NV_STATUS status = NV_OK; - NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS inParams = { 0 }; NV_PRINTF(LEVEL_INFO, "KernelCcu: State load \n"); - // Create shared buffer - status = _kccuInitSharedBuffer(pGpu, pKernelCcu); + if (IS_VIRTUAL(pGpu)) + { + return NV_ERR_NOT_SUPPORTED; + } + + // Create device shared buffer + status = _kccuInitDevSharedBuffer(pGpu, pKernelCcu); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "Failed to init shared buffer(status: %u) \n", status); + NV_PRINTF(LEVEL_ERROR, "Failed to init device shared buffer(status: %u) \n", status); return status; } - for (idx = 0; idx < CCU_SHRBUF_COUNT_MAX; idx++) + // Create mig shared buffer + if (IS_MIG_ENABLED(pGpu)) { - if (pKernelCcu->pMemDesc[idx] != NULL) + status = kccuInitMigSharedBuffer(pGpu, pKernelCcu); + if (status != NV_OK) { - inParams.phyAddr[idx] = memdescGetPhysAddr(pKernelCcu->pMemDesc[idx], AT_GPU, 0); + NV_PRINTF(LEVEL_ERROR, "Failed to init mig shared buffer(status: %u) \n", status); + return status; } + pKernelCcu->bMigShrBufAllocated = NV_TRUE; } - // Internal RM api ctrl call to physical RM to map shared buffer memdesc - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - - status = pRmApi->Control(pRmApi, - pGpu->hInternalClient, - pGpu->hInternalSubdevice, - NV2080_CTRL_CMD_INTERNAL_CCU_MAP, - &inParams, - sizeof(inParams)); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "CCU memdesc map request failed with status: 0x%x \r\n", status); - return status; - } - - return status; + // Send shared buffer info to gsp + return (kccuShrBufInfoToCcu(pGpu, pKernelCcu, CCU_DEV_SHRBUF_ID)); } /*! @@ -368,9 +447,14 @@ NV_STATUS kccuStateUnload_IMPL NV_STATUS status = NV_OK; NV_PRINTF(LEVEL_INFO, "KernelCcu: State unload \n"); + // Disable ccu stream state + pKernelCcu->bStreamState = CCU_STREAM_STATE_DISABLE; + // Free shared buffer & mem desc _kccuUnmapAndFreeMemory(pGpu, pKernelCcu); + pKernelCcu->bMigShrBufAllocated = NV_FALSE; + return status; } @@ -402,7 +486,7 @@ NV_STATUS kccuMemDescGetForShrBufId_IMPL if (idx >= CCU_SHRBUF_COUNT_MAX) { - NV_PRINTF(LEVEL_ERROR, "CCU memdesc get failed for input idx(%u). Invalid index.\r\n", + NV_PRINTF(LEVEL_ERROR, "CCU memdesc get failed for input idx(%u). Invalid index.\n", idx); return NV_ERR_INVALID_ARGUMENT; @@ -450,7 +534,7 @@ NV_STATUS kccuMemDescGetForSwizzId_IMPL if (idx >= CCU_SHRBUF_COUNT_MAX) { - NV_PRINTF(LEVEL_ERROR, "KernelCcu: memdesc get failed for input swizzId(%u) \r\n", + NV_PRINTF(LEVEL_ERROR, "KernelCcu: memdesc get failed for input swizzId(%u)\n", swizzId); return NV_ERR_INVALID_ARGUMENT; @@ -484,3 +568,147 @@ NvU32 kccuCounterBlockSizeGet_IMPL return CCU_MIG_INST_COUNTER_Q_SIZE; } + +/*! + * Set ccu stream state + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelCcu KernelCcu object pointer + * @param[in] pParams Ccu stream state param + * + * @return NV_OK + * @return NV_ERR_INVALID_ARGUMENT + */ +NV_STATUS kccuStreamStateSet_IMPL +( + OBJGPU *pGpu, + KernelCcu *pKernelCcu, + NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS *pParams +) +{ + NV_STATUS status = NV_OK; + NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS ccuParams = { 0 }; + + NV_PRINTF(LEVEL_INFO, "KernelCcu: Set ccu stream \n"); + + if (pParams == NULL || (pParams->bStreamState != CCU_STREAM_STATE_ENABLE && + pParams->bStreamState != CCU_STREAM_STATE_DISABLE)) + { + NV_PRINTF(LEVEL_ERROR, "KernelCcu: Invalid input params\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + if (pKernelCcu->bStreamState == pParams->bStreamState) + { + NV_PRINTF(LEVEL_INFO, "KernelCcu: CCU stream state is already (%s)\n", + pKernelCcu->bStreamState ? "ENABLED" : "DISABLED"); + return NV_OK; + } + + ccuParams.bStreamState = pParams->bStreamState; + + // RM api ctrl call to physical RM to set ccu stream state + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_CCU_SET_STREAM_STATE, + &ccuParams, + sizeof(ccuParams)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "CCU stream state set failed with status: 0x%x\n", status); + return status; + } + + pKernelCcu->bStreamState = ccuParams.bStreamState; + + // Clear the shared buffer, when stream state is disabled + if (pKernelCcu->bStreamState == CCU_STREAM_STATE_DISABLE) + { + NvU32 i; + for (i = 0; i < CCU_SHRBUF_COUNT_MAX; i++) + { + MEMORY_DESCRIPTOR *pMemDesc = pKernelCcu->pMemDesc[i]; + + if (pMemDesc == NULL) + continue; + + portMemSet(pKernelCcu->shrBuf[i].pKernelMapInfo->addr, 0, memdescGetSize(pMemDesc)); + } + } + + return NV_OK; +} + +/*! + * Get ccu stream state + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelCcu KernelCcu object pointer + * + * @return CCU stream state + */ +NvBool kccuStreamStateGet_IMPL +( + OBJGPU *pGpu, + KernelCcu *pKernelCcu +) +{ + NV_PRINTF(LEVEL_INFO, "KernelCcu: Get ccu stream \n"); + + return pKernelCcu->bStreamState; +} + +/*! + * Get the shared buffer memory descriptor for compute inst with + * swizz id and compute id + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelCcu KernelCcu object pointer + * @param[in] swizzId Mig inst swizz-id + * @param[in] computeId Compute inst id + * @param[out] MEMORY_DESCRIPTOR Location of pMemDesc + * + * @return NV_OK + * @return NV_ERR_NOT_SUPPORTED + * @return NV_ERR_INVALID_ARGUMENT + */ +NV_STATUS kccuMemDescGetForComputeInst_IMPL +( + OBJGPU *pGpu, + KernelCcu *pKernelCcu, + NvU8 swizzId, + NvU8 computeId, + MEMORY_DESCRIPTOR **ppMemDesc +) +{ + NvU32 idx; + + if (IS_VIRTUAL(pGpu)) + { + return NV_ERR_NOT_SUPPORTED; + } + + for (idx = CCU_MIG_SHRBUF_ID_START; idx < CCU_SHRBUF_COUNT_MAX; idx++) + { + if (*pKernelCcu->shrBuf[idx].pCounterDstInfo->pSwizzId == swizzId && + *pKernelCcu->shrBuf[idx].pCounterDstInfo->pComputeId == computeId) + { + *ppMemDesc = pKernelCcu->pMemDesc[idx]; + break; + } + } + + if (idx >= CCU_SHRBUF_COUNT_MAX) + { + NV_PRINTF(LEVEL_ERROR, "KernelCcu: memdesc get failed for input swizzId(%u), computeInst(%u)\n", + swizzId, computeId); + + return NV_ERR_INVALID_ARGUMENT; + } + + return NV_OK; +} + diff --git a/src/nvidia/src/kernel/gpu/ccu/kernel_ccu_api.c b/src/nvidia/src/kernel/gpu/ccu/kernel_ccu_api.c index 27deca510..a759782fc 100644 --- a/src/nvidia/src/kernel/gpu/ccu/kernel_ccu_api.c +++ b/src/nvidia/src/kernel/gpu/ccu/kernel_ccu_api.c @@ -67,8 +67,6 @@ _kccuapiMemdescGet { MIG_INSTANCE_REF ref; NV_STATUS status = NV_OK; - NvU32 ciGpcCount = 0; - NvU32 giGpcCount = 0; OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelCcuApi); KernelCcu *pKernelCcu = GPU_GET_KERNEL_CCU(pGpu); KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); @@ -99,20 +97,14 @@ _kccuapiMemdescGet return NV_ERR_INSUFFICIENT_PERMISSIONS; } - giGpcCount = ref.pKernelMIGGpuInstance ? ref.pKernelMIGGpuInstance->resourceAllocation.gpcCount : 0; - ciGpcCount = ref.pMIGComputeInstance ? ref.pMIGComputeInstance->resourceAllocation.gpcCount : 0; - - // Check if Gpu inst's gpc-count is valid - NV_ASSERT_OR_RETURN(giGpcCount != 0, NV_ERR_INVALID_DATA); - - if (giGpcCount == ciGpcCount) + if ((ref.pKernelMIGGpuInstance == NULL) || (ref.pMIGComputeInstance == NULL)) { - // Fetch the shared buffer memdesc for the swizzId - return kccuMemDescGetForSwizzId(pGpu, pKernelCcu, ref.pKernelMIGGpuInstance->swizzId, pMemDesc); + return NV_ERR_INVALID_POINTER; } - // Permission denied - return NV_ERR_INSUFFICIENT_PERMISSIONS; + // Fetch the shared buffer memdesc for the computeId + return kccuMemDescGetForComputeInst(pGpu, pKernelCcu, ref.pKernelMIGGpuInstance->swizzId, + ref.pMIGComputeInstance->id, pMemDesc); } NV_STATUS @@ -351,3 +343,49 @@ kccuapiCtrlCmdUnsubscribe_IMPL return NV_OK; } +NV_STATUS +kccuapiCtrlCmdSetStreamState_IMPL +( + KernelCcuApi *pKernelCcuApi, + NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelCcuApi); + KernelCcu *pKernelCcu = GPU_GET_KERNEL_CCU(pGpu); + + NV_PRINTF(LEVEL_INFO, "Kernel Ccu Api: CCU set stream state request\n"); + + if (pKernelCcu == NULL) + { + return NV_ERR_INVALID_OBJECT; + } + + // Set counter collection unit stream state + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kccuStreamStateSet(pGpu, pKernelCcu, pParams)); + + return NV_OK; +} + +NV_STATUS +kccuapiCtrlCmdGetStreamState_IMPL +( + KernelCcuApi *pKernelCcuApi, + NV_COUNTER_COLLECTION_UNIT_STREAM_STATE_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelCcuApi); + KernelCcu *pKernelCcu = GPU_GET_KERNEL_CCU(pGpu); + + NV_PRINTF(LEVEL_INFO, "Kernel Ccu Api: CCU get stream state request\n"); + + if (pKernelCcu == NULL) + { + return NV_ERR_INVALID_OBJECT; + } + + // Get counter collection unit stream state + pParams->bStreamState = kccuStreamStateGet(pGpu, pKernelCcu); + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/ce/arch/ampere/kernel_ce_ga100.c b/src/nvidia/src/kernel/gpu/ce/arch/ampere/kernel_ce_ga100.c index cb29e7acf..0cb4ff43a 100644 --- a/src/nvidia/src/kernel/gpu/ce/arch/ampere/kernel_ce_ga100.c +++ b/src/nvidia/src/kernel/gpu/ce/arch/ampere/kernel_ce_ga100.c @@ -79,25 +79,6 @@ static NVLINK_CE_AUTO_CONFIG_TABLE nvLinkCeAutoConfigTable_GA100[] = 0xF,0xF,0xF,0xF,0xF,0xF,0xF,0x2,0x3}, {0xF,0xF}, 0xF} }; -/*! - * @brief Returns the size of the GRCE_CONFIG register array - * - * - * @param[in] pGpu OBJGPU pointer - * @param[in] pKCe KernelCE pointer - * - * @return NV_CE_GRCE_CONFIG__SIZE_1 - * - */ -NvU32 -kceGetGrceConfigSize1_GA100 -( - KernelCE * pKCe -) -{ - return NV_CE_GRCE_CONFIG__SIZE_1; -} - /*! * @brief Returns the size of the PCE2LCE register array * @@ -838,6 +819,13 @@ kceMapPceLceForNvlinkPeers_GA100 peerAvailableLceMask &= (~(NVBIT32(lceIndex))); peerLinkMask = knvlinkGetLinkMaskToPeer(pGpu, pKernelNvlink, pRemoteGpu); + + if (peerLinkMask == 0) + { + NV_PRINTF(LEVEL_INFO, "GPU%d has nvlink disabled. Skip programming\n", pRemoteGpu->gpuInstance); + continue; + } + numPcePerLink = NV_CE_MIN_PCE_PER_PEER_LINK; prevHshubId = 0xFF; diff --git a/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c b/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c index 993a919fd..2dc28bb4a 100644 --- a/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c +++ b/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c @@ -133,7 +133,7 @@ _ceGetAlgorithmPceIndex } *pceIndex = CE_GET_LOWEST_AVAILABLE_IDX(pceAvailableMaskPerHshub[i]); - if (NVBIT32(*pceIndex) & pceAvailableMaskPerHshub[*pHshubId]) { + if (NVBIT32(*pceIndex) & pceAvailableMaskPerHshub[i]) { break; } } @@ -441,6 +441,11 @@ kceMapPceLceForNvlinkPeers_GH100 NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS params; + if (pKernelNvlink == NULL) + { + return NV_WARN_NOTHING_TO_DO; + } + peerAvailableLceMask = kceGetNvlinkPeerSupportedLceMask_HAL(pGpu, pKCe, peerAvailableLceMask); pKCe->nvlinkNumPeers = 0; @@ -497,6 +502,11 @@ kceMapPceLceForNvlinkPeers_GH100 peerAvailableLceMask &= (~(NVBIT32(lceIndex))); peerLinkMask = knvlinkGetLinkMaskToPeer(pGpu, pKernelNvlink, pRemoteGpu); + if (peerLinkMask == 0) + { + NV_PRINTF(LEVEL_INFO, "GPU%d has nvlink disabled. Skip programming\n", pRemoteGpu->gpuInstance); + continue; + } portMemSet(¶ms, 0, sizeof(params)); params.linkMask = peerLinkMask; diff --git a/src/nvidia/src/kernel/gpu/ce/arch/pascal/kernel_ce_gp100.c b/src/nvidia/src/kernel/gpu/ce/arch/pascal/kernel_ce_gp100.c index bde9f9032..20df8f45f 100644 --- a/src/nvidia/src/kernel/gpu/ce/arch/pascal/kernel_ce_gp100.c +++ b/src/nvidia/src/kernel/gpu/ce/arch/pascal/kernel_ce_gp100.c @@ -30,26 +30,20 @@ NV_STATUS kceStateLoad_GP100(OBJGPU *pGpu, KernelCE *pKCe, NvU32 flags) { - if (!IS_VIRTUAL(pGpu) && !pGpu->bIsKCeMapInitialized) + KernelCE *pKCeShim; + + // Mark first CE to load as the owner + if (kceFindShimOwner(pGpu, pKCe, &pKCeShim) != NV_OK) + pKCe->bShimOwner = NV_TRUE; + + if (!IS_VIRTUAL(pGpu) && pKCe->bShimOwner) { NV_ASSERT_OK_OR_RETURN(kceTopLevelPceLceMappingsUpdate(pGpu, pKCe)); - pGpu->bIsKCeMapInitialized = NV_TRUE; } return NV_OK; } -NV_STATUS kceStateUnload_GP100(OBJGPU *pGpu, KernelCE *pKCe, NvU32 flags) -{ - // Apply mappings again at resume, bug 3456067 - pGpu->bIsKCeMapInitialized = NV_FALSE; - - // On vgpu, sync with the mappings of PF at resume - pGpu->bIsCeMapInitialized = NV_FALSE; - - return NV_OK; -} - /*! * Determine if CE should be used for sysmem read * @param[in] pGpu OBJGPU pointer diff --git a/src/nvidia/src/kernel/gpu/ce/arch/volta/kernel_ce_gv100.c b/src/nvidia/src/kernel/gpu/ce/arch/volta/kernel_ce_gv100.c index 66eef162f..0fd9d4f40 100644 --- a/src/nvidia/src/kernel/gpu/ce/arch/volta/kernel_ce_gv100.c +++ b/src/nvidia/src/kernel/gpu/ce/arch/volta/kernel_ce_gv100.c @@ -89,10 +89,9 @@ NV_STATUS kceGetP2PCes_GV100(KernelCE *pKCe, OBJGPU *pGpu, NvU32 gpuMask, NvU32 return NV_OK; } - for (NvU32 i = NVLINK_MIN_P2P_LCE; i < gpuGetNumCEs(pGpu); i++) - { - pKCeLoop = GPU_GET_KCE(pGpu, i); - if (pKCeLoop == NULL || pKCeLoop->bStubbed) + + KCE_ITER_ALL_BEGIN(pGpu, pKCeLoop, NVLINK_MIN_P2P_LCE) + if (pKCeLoop->bStubbed) { continue; } @@ -145,7 +144,7 @@ NV_STATUS kceGetP2PCes_GV100(KernelCE *pKCe, OBJGPU *pGpu, NvU32 gpuMask, NvU32 pKCeSubMatch = (pKCeSubMatch == NULL) ? pKCeLoop : pKCeSubMatch; } } - } + KCE_ITER_END // // Prioritize an unused LCE with numPce to numLink match @@ -251,14 +250,9 @@ kceClearAssignedNvlinkPeerMasks_GV100 KernelCE *pKCe ) { - KernelCE *pCeLoop = NULL; - NvU32 i; + KernelCE *pKCeLoop = NULL; - for (i = NVLINK_MIN_P2P_LCE; i < gpuGetNumCEs(pGpu); i++) - { - pCeLoop = GPU_GET_KCE(pGpu, i); - - if (pCeLoop) - pCeLoop->nvlinkPeerMask = 0; - } + KCE_ITER_ALL_BEGIN(pGpu, pKCeLoop, NVLINK_MIN_P2P_LCE) + pKCeLoop->nvlinkPeerMask = 0; + KCE_ITER_END } diff --git a/src/nvidia/src/kernel/gpu/ce/kernel_ce.c b/src/nvidia/src/kernel/gpu/ce/kernel_ce.c index 860eccf19..dd47d7306 100644 --- a/src/nvidia/src/kernel/gpu/ce/kernel_ce.c +++ b/src/nvidia/src/kernel/gpu/ce/kernel_ce.c @@ -29,6 +29,7 @@ #include "gpu_mgr/gpu_mgr.h" #include "kernel/gpu/intr/intr_service.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" +#include "kernel/gpu/nvlink/common_nvlink.h" #include "nvRmReg.h" NV_STATUS kceConstructEngine_IMPL(OBJGPU *pGpu, KernelCE *pKCe, ENGDESCRIPTOR engDesc) @@ -40,6 +41,8 @@ NV_STATUS kceConstructEngine_IMPL(OBJGPU *pGpu, KernelCE *pKCe, ENGDESCRIPTOR en NV_PRINTF(LEVEL_INFO, "KernelCE: thisPublicID = %d\n", thisPublicID); pKCe->publicID = thisPublicID; + pKCe->bShimOwner = NV_FALSE; + pKCe->bIsAutoConfigEnabled = NV_TRUE; pKCe->bUseGen4Mapping = NV_FALSE; @@ -64,16 +67,16 @@ NV_STATUS kceConstructEngine_IMPL(OBJGPU *pGpu, KernelCE *pKCe, ENGDESCRIPTOR en return NV_OK; } -NvBool kceIsPresent_IMPL(OBJGPU *pGpu, KernelCE *kce) +NvBool kceIsPresent_IMPL(OBJGPU *pGpu, KernelCE *pKCe) { // Use bus/fifo to detemine if LCE(i) is present. KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); NvBool present = NV_FALSE; NV_ASSERT_OR_RETURN(pKernelBus != NULL, NV_FALSE); - present = kbusCheckEngine_HAL(pGpu, pKernelBus, ENG_CE(kce->publicID)); + present = kbusCheckEngine_HAL(pGpu, pKernelBus, ENG_CE(pKCe->publicID)); - NV_PRINTF(LEVEL_INFO, "KCE %d / %d: present=%d\n", kce->publicID, + NV_PRINTF(LEVEL_INFO, "KCE %d / %d: present=%d\n", pKCe->publicID, pGpu->numCEs > 0 ? pGpu->numCEs - 1 : pGpu->numCEs, present); return present; @@ -84,9 +87,10 @@ NvBool kceIsNewMissingEngineRemovalSequenceEnabled_IMPL(OBJGPU *pGpu, KernelCE * return NV_TRUE; } -static void printCaps(KernelCE *pKCe, NvU32 engineType, const NvU8 *capsTbl) +static void printCaps(OBJGPU *pGpu, KernelCE *pKCe, RM_ENGINE_TYPE rmEngineType, const NvU8 *capsTbl) { - NV_PRINTF(LEVEL_INFO, "LCE%d caps (engineType = %d)\n", pKCe->publicID, engineType); + NV_PRINTF(LEVEL_INFO, "LCE%d caps (engineType = %d (%d))\n", pKCe->publicID, + gpuGetNv2080EngineType(rmEngineType), rmEngineType); #define PRINT_CAP(cap) NV_PRINTF(LEVEL_INFO, #cap ":%d\n", (RMCTRL_GET_CAP(capsTbl, NV2080_CTRL_CE_CAPS, cap) != 0) ? 1 : 0) PRINT_CAP(_CE_GRCE); @@ -105,7 +109,7 @@ static void printCaps(KernelCE *pKCe, NvU32 engineType, const NvU8 *capsTbl) static void kceGetNvlinkCaps(OBJGPU *pGpu, KernelCE *pKCe, NvU8 *pKCeCaps) { if (kceIsCeSysmemRead_HAL(pGpu, pKCe)) - RMCTRL_SET_CAP(pKCeCaps, NV2080_CTRL_CE_CAPS, _CE_SYSMEM_READ); + RMCTRL_SET_CAP(pKCeCaps, NV2080_CTRL_CE_CAPS, _CE_SYSMEM_READ); if (kceIsCeSysmemWrite_HAL(pGpu, pKCe)) RMCTRL_SET_CAP(pKCeCaps, NV2080_CTRL_CE_CAPS, _CE_SYSMEM_WRITE); @@ -114,7 +118,7 @@ static void kceGetNvlinkCaps(OBJGPU *pGpu, KernelCE *pKCe, NvU8 *pKCeCaps) RMCTRL_SET_CAP(pKCeCaps, NV2080_CTRL_CE_CAPS, _CE_NVLINK_P2P); } -NV_STATUS kceGetDeviceCaps_IMPL(OBJGPU *pGpu, KernelCE *pKCe, NvU32 engineType, NvU8 *pKCeCaps) +NV_STATUS kceGetDeviceCaps_IMPL(OBJGPU *pGpu, KernelCE *pKCe, RM_ENGINE_TYPE rmEngineType, NvU8 *pKCeCaps) { if (pKCe->bStubbed) { @@ -158,7 +162,7 @@ NV_STATUS kceGetDeviceCaps_IMPL(OBJGPU *pGpu, KernelCE *pKCe, NvU32 engineType, if (pKernelNvlink != NULL) kceGetNvlinkCaps(pGpu, pKCe, pKCeCaps); - printCaps(pKCe, engineType, pKCeCaps); + printCaps(pGpu, pKCe, rmEngineType, pKCeCaps); return NV_OK; } @@ -170,9 +174,9 @@ subdeviceCtrlCmdCeGetAllCaps_IMPL NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *pCeCapsParams ) { - OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - KernelMIGManager *pKernelMIGManager = NULL; - MIG_INSTANCE_REF migRef; + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + KernelCE *pKCe; ct_assert(ENG_CE__SIZE_1 <= sizeof(pCeCapsParams->capsTbl) / sizeof(pCeCapsParams->capsTbl[0])); @@ -188,18 +192,7 @@ subdeviceCtrlCmdCeGetAllCaps_IMPL knvlinkCoreGetRemoteDeviceInfo(pGpu, pKernelNvlink); } - if (IS_MIG_IN_USE(pGpu)) - { - KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); - - NV_CHECK_OK_OR_RETURN( - LEVEL_ERROR, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, - hClient, &migRef)); - } - - portMemSet(pCeCapsParams, 0, sizeof(pCeCapsParams)); + portMemSet(pCeCapsParams, 0, sizeof(*pCeCapsParams)); RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, @@ -209,29 +202,17 @@ subdeviceCtrlCmdCeGetAllCaps_IMPL pCeCapsParams, sizeof(*pCeCapsParams))); - for (NvU32 i = 0; i < ENG_CE__SIZE_1; i++) - { - KernelCE *pKCe = GPU_GET_KCE(pGpu, i); - if (pKCe == NULL || pKCe->bStubbed) - { - NV_PRINTF(LEVEL_INFO, "Skipping missing or stubbed CE %d\n", i); + KCE_ITER_CLIENT_BEGIN(pGpu, pKCe, hClient) + if (pKCe->bStubbed) continue; - } - if (IS_MIG_IN_USE(pGpu) && - !kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, NV2080_ENGINE_TYPE_COPY(i), migRef)) - { - NV_PRINTF(LEVEL_INFO, "Skipping CE%d not that is not in the MIG instance\n", i); - continue; - } + pCeCapsParams->present |= BIT(kceInst); - pCeCapsParams->present |= BIT(i); - - NvU8 *pKCeCaps = pCeCapsParams->capsTbl[i]; + NvU8 *pKCeCaps = pCeCapsParams->capsTbl[kceInst]; if (pKernelNvlink != NULL) kceGetNvlinkCaps(pGpu, pKCe, pKCeCaps); - } + KCE_ITER_END return NV_OK; } @@ -265,7 +246,7 @@ kceGetCeFromNvlinkConfig_IMPL gpuCount = gpumgrGetSubDeviceCount(gpuMask); NV_CHECK_OR_RETURN(LEVEL_ERROR, !IsGP100(pGpu) || gpuCount <= 2, NV_ERR_INVALID_STATE); - rmStatus = knvlinkCtrlCmdBusGetNvlinkCaps(pGpu, &nvlinkCapsParams); + rmStatus = nvlinkCtrlCmdBusGetNvlinkCaps(pGpu, &nvlinkCapsParams); NV_ASSERT_OK_OR_RETURN(rmStatus); nvlinkCaps = (NvU8*)&nvlinkCapsParams.capsTbl; @@ -300,31 +281,26 @@ NV_STATUS kceUpdateClassDB_KERNEL(OBJGPU *pGpu, KernelCE *pKCe) NV_ASSERT_OK_OR_RETURN(status); // For each LCE, check if it is stubbed out in GSP-RM - for (NvU32 i = 0; i < gpuGetNumCEs(pGpu); i++) - { - KernelCE *pKCe = GPU_GET_KCE(pGpu, i); + KCE_ITER_ALL_BEGIN(pGpu, pKCe, 0) + NvBool stubbed = ((BIT(kceInst) & params.stubbedCeMask)) != 0; - if (pKCe) + // If this CE has no PCEs assigned, remove it from classDB + if (stubbed) { - NvBool stubbed = ((BIT(i) & params.stubbedCeMask)) != 0; - // If this CE has no PCEs assigned, remove it from classDB - if (stubbed) - { - NV_PRINTF(LEVEL_INFO, "Stubbing CE %d\n", i); - pKCe->bStubbed = NV_TRUE; + NV_PRINTF(LEVEL_INFO, "Stubbing CE %d\n", kceInst); + pKCe->bStubbed = NV_TRUE; - status = gpuDeleteClassFromClassDBByEngTag(pGpu, ENG_CE(i)); - } - else - { - // If a new CE needs to be added because of the new mappings - NV_PRINTF(LEVEL_INFO, "Unstubbing CE %d\n", i); - pKCe->bStubbed = NV_FALSE; - - status = gpuAddClassToClassDBByEngTag(pGpu, ENG_CE(i)); - } + status = gpuDeleteClassFromClassDBByEngTag(pGpu, ENG_CE(kceInst)); } - } + else + { + // If a new CE needs to be added because of the new mappings + NV_PRINTF(LEVEL_INFO, "Unstubbing CE %d\n", kceInst); + pKCe->bStubbed = NV_FALSE; + + status = gpuAddClassToClassDBByEngTag(pGpu, ENG_CE(kceInst)); + } + KCE_ITER_END NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, gpuUpdateEngineTable(pGpu)); @@ -375,7 +351,7 @@ kceServiceNotificationInterrupt_IMPL kceNonstallIntrCheckAndClear_HAL(pGpu, pKCe, pParams->pThreadState); // Wake up channels waiting on this event - engineNonStallIntrNotify(pGpu, NV2080_ENGINE_TYPE_COPY(pKCe->publicID)); + engineNonStallIntrNotify(pGpu, RM_ENGINE_TYPE_COPY(pKCe->publicID)); return NV_OK; } @@ -540,3 +516,43 @@ kceGetAvailableHubPceMask_IMPL return NV_OK; } + +/*! + * @brief return first non-NULL KCE instance + */ +NV_STATUS +kceFindFirstInstance_IMPL(OBJGPU *pGpu, KernelCE **ppKCe) +{ + KernelCE *pKCe = NULL; + + KCE_ITER_ALL_BEGIN(pGpu, pKCe, 0) + *ppKCe = pKCe; + return NV_OK; + KCE_ITER_END + + return NV_ERR_INSUFFICIENT_RESOURCES; +} + +/*! + * @brief Find shim owner KernelCE object + */ +NV_STATUS +kceFindShimOwner_IMPL +( + OBJGPU *pGpu, + KernelCE *pKCe, + KernelCE **ppShimKCe +) +{ + KernelCE *pKCeLoop; + + KCE_ITER_ALL_BEGIN(pGpu, pKCeLoop, 0) + if (pKCeLoop->bShimOwner) + { + *ppShimKCe = pKCeLoop; + return NV_OK; + } + KCE_ITER_END + + return NV_ERR_INSUFFICIENT_RESOURCES; +} diff --git a/src/nvidia/src/kernel/gpu/ce/kernel_ce_context.c b/src/nvidia/src/kernel/gpu/ce/kernel_ce_context.c index e86a4692f..58d2561fc 100644 --- a/src/nvidia/src/kernel/gpu/ce/kernel_ce_context.c +++ b/src/nvidia/src/kernel/gpu/ce/kernel_ce_context.c @@ -57,12 +57,14 @@ ENGDESCRIPTOR kceGetEngineDescFromAllocParams(OBJGPU *pGpu, NvU32 externalClassId, void *pAllocParams) { CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); - NvU32 engineInstance = 0; + NvU32 engineIndex = 0; NV_ASSERT(pAllocParams); if (IsAMODEL(pGpu)) { + RM_ENGINE_TYPE rmEngineType; + // On AMODEL CopyEngine is allocated using OBJGR if (IS_MIG_IN_USE(pGpu)) { @@ -76,9 +78,9 @@ kceGetEngineDescFromAllocParams(OBJGPU *pGpu, NvU32 externalClassId, void *pAllo NV_ASSERT_OK( kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, - NV2080_ENGINE_TYPE_GR(0), - &engineInstance)); - return ENG_GR(NV2080_ENGINE_TYPE_GR_IDX(engineInstance)); + RM_ENGINE_TYPE_GR(0), + &rmEngineType)); + return ENG_GR(RM_ENGINE_TYPE_GR_IDX(rmEngineType)); } return ENG_GR(0); } @@ -104,7 +106,9 @@ kceGetEngineDescFromAllocParams(OBJGPU *pGpu, NvU32 externalClassId, void *pAllo NV_PRINTF(LEVEL_INFO, "Version = 0, using engineType (=%d) as CE instance\n", pNvA0b5CreateParms->engineType); - engineInstance = pNvA0b5CreateParms->engineType; + + // The engineType in VERSION_0 is actually an index + engineIndex = pNvA0b5CreateParms->engineType; break; } @@ -113,17 +117,17 @@ kceGetEngineDescFromAllocParams(OBJGPU *pGpu, NvU32 externalClassId, void *pAllo NvU32 i; // Loop over supported engines - for (i = 0; i < NV2080_ENGINE_TYPE_COPY_SIZE; i++) + for (i = 0; i < RM_ENGINE_TYPE_COPY_SIZE; i++) { - if (pNvA0b5CreateParms->engineType == NV2080_ENGINE_TYPE_COPY(i)) + if (gpuGetRmEngineType(pNvA0b5CreateParms->engineType) == RM_ENGINE_TYPE_COPY(i)) { - engineInstance = i; + engineIndex = i; break; } } // Make sure we found something we support - if (i == NV2080_ENGINE_TYPE_COPY_SIZE) + if (i == RM_ENGINE_TYPE_COPY_SIZE) { NV_PRINTF(LEVEL_ERROR, "Unknown engine type %d requested\n", @@ -155,11 +159,11 @@ kceGetEngineDescFromAllocParams(OBJGPU *pGpu, NvU32 externalClassId, void *pAllo } NV_STATUS status = ceIndexFromType(pGpu, pCallContext->pClient->hClient, - NV2080_ENGINE_TYPE_COPY(engineInstance), &engineInstance); + RM_ENGINE_TYPE_COPY(engineIndex), &engineIndex); if (status == NV_OK) { - NV_PRINTF(LEVEL_INFO, "Class %d, CE%d\n", externalClassId, engineInstance); - return ENG_CE(engineInstance); + NV_PRINTF(LEVEL_INFO, "Class %d, CE%d\n", externalClassId, engineIndex); + return ENG_CE(engineIndex); } else NV_PRINTF(LEVEL_ERROR, "Failed to determine CE number\n"); diff --git a/src/nvidia/src/kernel/gpu/ce/kernel_ce_ctrl.c b/src/nvidia/src/kernel/gpu/ce/kernel_ce_ctrl.c index f13039e51..51d49efcc 100644 --- a/src/nvidia/src/kernel/gpu/ce/kernel_ce_ctrl.c +++ b/src/nvidia/src/kernel/gpu/ce/kernel_ce_ctrl.c @@ -52,8 +52,9 @@ subdeviceCtrlCmdCeGetCaps_IMPL KernelCE *pKCe; NvU32 ceNumber; NV_STATUS status = NV_OK; + RM_ENGINE_TYPE rmEngineType; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); // sanity check array size if (pCeCapsParams->capsTblSize != NV2080_CTRL_CE_CAPS_TBL_SIZE) @@ -63,6 +64,8 @@ subdeviceCtrlCmdCeGetCaps_IMPL return NV_ERR_INVALID_ARGUMENT; } + rmEngineType = gpuGetRmEngineType(pCeCapsParams->ceEngineType); + // // vGPU: // @@ -95,7 +98,7 @@ subdeviceCtrlCmdCeGetCaps_IMPL return status; } - NV_ASSERT_OK_OR_RETURN(ceIndexFromType(pGpu, RES_GET_CLIENT_HANDLE(pSubdevice), pCeCapsParams->ceEngineType, &ceNumber)); + NV_ASSERT_OK_OR_RETURN(ceIndexFromType(pGpu, RES_GET_CLIENT_HANDLE(pSubdevice), rmEngineType, &ceNumber)); pKCe = GPU_GET_KCE(pGpu, ceNumber); @@ -107,64 +110,5 @@ subdeviceCtrlCmdCeGetCaps_IMPL } // now fill in caps for this CE - return kceGetDeviceCaps(pGpu, pKCe, pCeCapsParams->ceEngineType, NvP64_VALUE(pCeCapsParams->capsTbl)); -} - -// -// Lock Requirements: -// Assert that API lock held on entry -// -NV_STATUS -subdeviceCtrlCmdCeGetCapsV2_IMPL -( - Subdevice *pSubdevice, - NV2080_CTRL_CE_GET_CAPS_V2_PARAMS *pCeCapsParams -) -{ - OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - KernelCE *pKCe; - NvU32 ceNumber; - NV_STATUS status = NV_OK; - - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); - - NV_PRINTF(LEVEL_INFO, "NV2080_CTRL_CE_GET_CAPS_V2 ceEngineType = %d\n", pCeCapsParams->ceEngineType); - - // - // vGPU: - // - // Since vGPU does all real hardware management in the - // host, if we are in guest OS (where IS_VIRTUAL(pGpu) is true), - // do an RPC to the host to get blacklist information from host RM - // - if (IS_VIRTUAL(pGpu)) - { - CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); - RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; - - NV_RM_RPC_CONTROL(pGpu, - pRmCtrlParams->hClient, - pRmCtrlParams->hObject, - pRmCtrlParams->cmd, - pRmCtrlParams->pParams, - pRmCtrlParams->paramsSize, - status); - - return status; - } - - NV_ASSERT_OK_OR_RETURN(ceIndexFromType(pGpu, RES_GET_CLIENT_HANDLE(pSubdevice), pCeCapsParams->ceEngineType, &ceNumber)); - - pKCe = GPU_GET_KCE(pGpu, ceNumber); - - // Return an unsupported error for not present or stubbed CEs as they are - // not supposed to be user visible and cannot be allocated anyway. - if (!pKCe) - { - NV_PRINTF(LEVEL_INFO, "Skipping stubbed CE %d\n", ceNumber); - return NV_ERR_NOT_SUPPORTED; - } - - // now fill in caps for this CE - return kceGetDeviceCaps(pGpu, pKCe, pCeCapsParams->ceEngineType, NvP64_VALUE(pCeCapsParams->capsTbl)); -} + return kceGetDeviceCaps(pGpu, pKCe, rmEngineType, NvP64_VALUE(pCeCapsParams->capsTbl)); +} \ No newline at end of file diff --git a/src/nvidia/src/kernel/gpu/ce/kernel_ce_shared.c b/src/nvidia/src/kernel/gpu/ce/kernel_ce_shared.c index 4aceef1d9..4ca3a2c18 100644 --- a/src/nvidia/src/kernel/gpu/ce/kernel_ce_shared.c +++ b/src/nvidia/src/kernel/gpu/ce/kernel_ce_shared.c @@ -21,26 +21,31 @@ * DEALINGS IN THE SOFTWARE. */ +#include "core/locks.h" +#include "vgpu/rpc.h" #include "gpu/gpu.h" #include "gpu_mgr/gpu_mgr.h" +#include "kernel/gpu/subdevice/subdevice.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "kernel/gpu/fifo/kernel_fifo.h" #include "gpu/bus/kern_bus.h" +#include "gpu/ce/kernel_ce.h" +#include "gpu/ce/kernel_ce_private.h" -NvBool ceIsCeGrce(OBJGPU *pGpu, NvU32 ceEngineType) +NvBool ceIsCeGrce(OBJGPU *pGpu, RM_ENGINE_TYPE rmCeEngineType) { NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS partnerParams = {0}; KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); - if (IsAMODEL(pGpu) || IsT234D(pGpu)) + if (IsAMODEL(pGpu) || IsT234DorBetter(pGpu)) return NV_FALSE; - NV_ASSERT_OR_RETURN(NV2080_ENGINE_TYPE_IS_COPY(ceEngineType), NV_FALSE); + NV_ASSERT_OR_RETURN(RM_ENGINE_TYPE_IS_COPY(rmCeEngineType), NV_FALSE); NvU32 i; NV_STATUS status = NV_OK; - partnerParams.engineType = ceEngineType; + partnerParams.engineType = gpuGetNv2080EngineType(rmCeEngineType); partnerParams.numPartners = 0; // See if the hal wants to handle this @@ -73,9 +78,10 @@ NvBool ceIsCeGrce(OBJGPU *pGpu, NvU32 ceEngineType) for (i = 0; i < pGpu->engineDB.size; i++) { // Skip the engine handed in - if (pGpu->engineDB.pType[i] != partnerParams.engineType ) + if (pGpu->engineDB.pType[i] != rmCeEngineType ) { - partnerParams.partnerList[partnerParams.numPartners++] = pGpu->engineDB.pType[i]; + partnerParams.partnerList[partnerParams.numPartners++] = + gpuGetNv2080EngineType(pGpu->engineDB.pType[i]); } } } @@ -110,7 +116,7 @@ NvU32 ceCountGrCe(OBJGPU *pGpu) for (engIdx = 0; engIdx < GPU_MAX_CES; ++engIdx) { if (kbusCheckEngine_HAL(pGpu, pKernelBus, ENG_CE(engIdx)) && - ceIsCeGrce(pGpu, NV2080_ENGINE_TYPE_COPY(engIdx))) + ceIsCeGrce(pGpu, RM_ENGINE_TYPE_COPY(engIdx))) { grCeCount++; } @@ -118,3 +124,40 @@ NvU32 ceCountGrCe(OBJGPU *pGpu) return grCeCount; } + +// +// Lock Requirements: +// Assert that API lock held on entry +// +NV_STATUS +subdeviceCtrlCmdCeGetCapsV2_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_CE_GET_CAPS_V2_PARAMS *pCeCapsParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + NvU32 ceNumber; + RM_ENGINE_TYPE rmEngineType = gpuGetRmEngineType(pCeCapsParams->ceEngineType); + + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); + + NV_PRINTF(LEVEL_INFO, "NV2080_CTRL_CE_GET_CAPS_V2 ceEngineType = %d\n", pCeCapsParams->ceEngineType); + + NV_ASSERT_OK_OR_RETURN(ceIndexFromType(pGpu, RES_GET_CLIENT_HANDLE(pSubdevice), rmEngineType, &ceNumber)); + + { + KernelCE *pKCe = GPU_GET_KCE(pGpu, ceNumber); + + // Return an unsupported error for not present or stubbed CEs as they are + // not supposed to be user visible and cannot be allocated anyway. + if (pKCe == NULL) + { + NV_PRINTF(LEVEL_INFO, "Skipping stubbed CE %d\n", ceNumber); + return NV_ERR_NOT_SUPPORTED; + } + + // now fill in caps for this CE + return kceGetDeviceCaps(pGpu, pKCe, rmEngineType, NvP64_VALUE(pCeCapsParams->capsTbl)); + } +} diff --git a/src/nvidia/src/kernel/gpu/deferred_api.c b/src/nvidia/src/kernel/gpu/deferred_api.c index 7a09a5642..7c916dc0f 100644 --- a/src/nvidia/src/kernel/gpu/deferred_api.c +++ b/src/nvidia/src/kernel/gpu/deferred_api.c @@ -22,30 +22,70 @@ */ #include "kernel/gpu/deferred_api.h" -#include "mem_mgr/vaspace.h" -#include "class/cl5080.h" -#include "ctrl/ctrl2080.h" -#include "vgpu/rpc.h" -#include "rmapi/control.h" -#include "core/locks.h" -#include "virtualization/hypervisor/hypervisor.h" -#include "gpu/device/device.h" -#include "gpu/subdevice/subdevice.h" -#include "rmapi/rs_utils.h" -#include "resserv/rs_server.h" -// Support Routines -static NV_STATUS Class5080AddDeferredApi( - PDEFERRED_API_OBJECT pDeferredApiObject, - NvHandle hClient, - NvHandle hDeferredApi, +#include "kernel/core/locks.h" +#include "kernel/gpu/device/device.h" +#include "kernel/gpu/subdevice/subdevice.h" +#include "kernel/mem_mgr/vaspace.h" +#include "kernel/rmapi/control.h" +#include "kernel/rmapi/rs_utils.h" +#include "kernel/virtualization/hypervisor/hypervisor.h" +#include "kernel/gpu/fifo/kernel_channel.h" + +#include "class/cl5080.h" + +#include "ctrl/ctrl2080.h" + +#include "libraries/resserv/rs_server.h" +#include "vgpu/rpc.h" + + +static NV_STATUS _Class5080DelDeferredApi(DeferredApiObject *pDeferredApiObject, + NvHandle hDeferredApi); + +static NV_STATUS _class5080DeferredApiV2(OBJGPU *pGpu, + ChannelDescendant *Object, + METHOD *pMethod, + NvU32 Offset, + NvU32 Data); + +static NV_STATUS +_Class5080UpdateTLBFlushState(DeferredApiObject *pDeferredApiObject); + +static NV_STATUS +_Class5080GetDeferredApiInfo(DeferredApiObject *pDeferredApiObject, + NvHandle hDeferredApi, + DEFERRED_API_INFO **ppCliDeferredApi); + +static NV_STATUS +_Class5080AddDeferredApi(DeferredApiObject *pDeferredApiObject, + NvHandle hClient, + NvHandle hDeferredApi, + NV5080_CTRL_DEFERRED_API_PARAMS *pDeferredApi, + NvU32 size, + NvBool bUserModeArgs); + +static NV_STATUS +_Class5080AddDeferredApiV2(DeferredApiObject *pDeferredApiObject, + NvHandle hClient, + NvHandle hDeferredApi, + NV5080_CTRL_DEFERRED_API_V2_PARAMS *pDeferredApi, + NvU32 size); + + +static NV_STATUS +_Class5080AddDeferredApi +( + DeferredApiObject *pDeferredApiObject, + NvHandle hClient, + NvHandle hDeferredApi, NV5080_CTRL_DEFERRED_API_PARAMS *pDeferredApi, - NvU32 size, - NvBool bUserModeArgs + NvU32 size, + NvBool bUserModeArgs ) { NV_STATUS rmStatus = NV_OK; - PDEFERRED_API_INFO pCliDeferredApi; + DEFERRED_API_INFO *pCliDeferredApi; CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); NV_ASSERT_OR_RETURN(pCallContext != NULL, NV_ERR_INVALID_STATE); @@ -86,19 +126,21 @@ static NV_STATUS Class5080AddDeferredApi( return NV_ERR_NO_MEMORY; return rmStatus; +} -} // end of Class5080AddDeferredApi() -static NV_STATUS Class5080AddDeferredApiV2( - PDEFERRED_API_OBJECT pDeferredApiObject, - NvHandle hClient, - NvHandle hDeferredApi, +static NV_STATUS +_Class5080AddDeferredApiV2 +( + DeferredApiObject *pDeferredApiObject, + NvHandle hClient, + NvHandle hDeferredApi, NV5080_CTRL_DEFERRED_API_V2_PARAMS *pDeferredApi, - NvU32 size + NvU32 size ) { NV_STATUS rmStatus = NV_OK; - PDEFERRED_API_INFO pCliDeferredApi; + DEFERRED_API_INFO *pCliDeferredApi; CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); NV_ASSERT_OR_RETURN(pCallContext != NULL, NV_ERR_INVALID_STATE); @@ -112,7 +154,7 @@ static NV_STATUS Class5080AddDeferredApiV2( return NV_ERR_INVALID_OBJECT_HANDLE; } - rmStatus = Class5080GetDeferredApiInfo(pDeferredApiObject, hDeferredApi, &pCliDeferredApi); + rmStatus = _Class5080GetDeferredApiInfo(pDeferredApiObject, hDeferredApi, &pCliDeferredApi); // Object already exists if (NV_OK == rmStatus) @@ -148,16 +190,18 @@ static NV_STATUS Class5080AddDeferredApiV2( return NV_ERR_NO_MEMORY; return rmStatus; +} -} // end of Class5080AddDeferredApiV2() -NV_STATUS Class5080GetDeferredApiInfo( - PDEFERRED_API_OBJECT pDeferredApiObject, - NvHandle hDeferredApi, - PDEFERRED_API_INFO * ppCliDeferredApi +static NV_STATUS +_Class5080GetDeferredApiInfo +( + DeferredApiObject *pDeferredApiObject, + NvHandle hDeferredApi, + DEFERRED_API_INFO **ppCliDeferredApi ) { - PNODE pNode; + NODE *pNode; if (btreeSearch(hDeferredApi, &pNode, pDeferredApiObject->DeferredApiList) == NV_OK) { @@ -167,20 +211,22 @@ NV_STATUS Class5080GetDeferredApiInfo( return NV_ERR_INVALID_DATA; -} // end of Class5080GetDeferredApiInfo() +} -static NV_STATUS Class5080DelDeferredApi( - PDEFERRED_API_OBJECT pDeferredApiObject, - NvHandle hDeferredApi + +static NV_STATUS _Class5080DelDeferredApi +( + DeferredApiObject *pDeferredApiObject, + NvHandle hDeferredApi ) { - PDEFERRED_API_INFO pDeferredApi = NULL; - NV_STATUS status; - PNODE pNode; + DEFERRED_API_INFO *pDeferredApi = NULL; + NV_STATUS status; + NODE *pNode; // remove the event from the client database - if (NV_OK == Class5080GetDeferredApiInfo(pDeferredApiObject, - hDeferredApi, &pDeferredApi)) + if (NV_OK == _Class5080GetDeferredApiInfo(pDeferredApiObject, + hDeferredApi, &pDeferredApi)) { status = btreeSearch(hDeferredApi, &pNode, pDeferredApiObject->DeferredApiList); if (status != NV_OK) @@ -215,15 +261,16 @@ static NV_STATUS Class5080DelDeferredApi( } return NV_ERR_GENERIC; +} -} // end of Class5080DelDeferredApi() -static NV_STATUS _Class5080UpdateTLBFlushState( - PDEFERRED_API_OBJECT pDeferredApiObject +static NV_STATUS _Class5080UpdateTLBFlushState +( + DeferredApiObject *pDeferredApiObject ) { - PNODE pNode; - PDEFERRED_API_INFO pCliDeferredApi; + NODE *pNode; + DEFERRED_API_INFO *pCliDeferredApi; NV5080_CTRL_DEFERRED_API_PARAMS *pDeferredApi; btreeEnumStart(0, &pNode, pDeferredApiObject->DeferredApiList); @@ -250,7 +297,7 @@ static NV_STATUS _Class5080UpdateTLBFlushState( if (DRF_VAL(5080_CTRL, _CMD_DEFERRED_API, _FLAGS_DELETE, pDeferredApi->flags) == NV5080_CTRL_CMD_DEFERRED_API_FLAGS_DELETE_IMPLICIT) { - Class5080DelDeferredApi(pDeferredApiObject, pCliDeferredApi->Handle); + _Class5080DelDeferredApi(pDeferredApiObject, pCliDeferredApi->Handle); } continue; } @@ -259,8 +306,8 @@ static NV_STATUS _Class5080UpdateTLBFlushState( } return NV_OK; +} -} // end of Class5080UpdateTLBFlushState() //--------------------------------------------------------------------------- // @@ -296,8 +343,8 @@ defapiDestruct_IMPL ) { ChannelDescendant *pChannelDescendant = staticCast(pDeferredApi, ChannelDescendant); - PNODE pNode; - PDEFERRED_API_INFO pCliDeferredApi; + NODE *pNode; + DEFERRED_API_INFO *pCliDeferredApi; chandesIsolateOnDestruct(pChannelDescendant); @@ -308,7 +355,7 @@ defapiDestruct_IMPL pCliDeferredApi = pNode->Data; btreeEnumNext(&pNode, pDeferredApi->DeferredApiList); - Class5080DelDeferredApi(pDeferredApi, pCliDeferredApi->Handle); + _Class5080DelDeferredApi(pDeferredApi, pCliDeferredApi->Handle); } } @@ -342,12 +389,12 @@ defapiCtrlCmdDeferredApi_IMPL return status; } - return Class5080AddDeferredApi(pDeferredApiObj, - RES_GET_CLIENT_HANDLE(pDeferredApiObj), - pDeferredApi->hApiHandle, - pDeferredApi, - sizeof(NV5080_CTRL_DEFERRED_API_PARAMS), - (pCallContext->secInfo.paramLocation != PARAM_LOCATION_KERNEL)); + return _Class5080AddDeferredApi(pDeferredApiObj, + RES_GET_CLIENT_HANDLE(pDeferredApiObj), + pDeferredApi->hApiHandle, + pDeferredApi, + sizeof(NV5080_CTRL_DEFERRED_API_PARAMS), + (pCallContext->secInfo.paramLocation != PARAM_LOCATION_KERNEL)); } NV_STATUS @@ -379,11 +426,11 @@ defapiCtrlCmdDeferredApiV2_IMPL return status; } - return Class5080AddDeferredApiV2(pDeferredApiObj, - RES_GET_CLIENT_HANDLE(pDeferredApiObj), - pDeferredApi->hApiHandle, - pDeferredApi, - sizeof(NV5080_CTRL_DEFERRED_API_V2_PARAMS)); + return _Class5080AddDeferredApiV2(pDeferredApiObj, + RES_GET_CLIENT_HANDLE(pDeferredApiObj), + pDeferredApi->hApiHandle, + pDeferredApi, + sizeof(NV5080_CTRL_DEFERRED_API_V2_PARAMS)); } NV_STATUS @@ -413,8 +460,8 @@ defapiCtrlCmdRemoveApi_IMPL return status; } - return Class5080DelDeferredApi(pDeferredApiObj, - pRemoveApi->hApiHandle); + return _Class5080DelDeferredApi(pDeferredApiObj, + pRemoveApi->hApiHandle); } static NV_STATUS @@ -422,21 +469,21 @@ _class5080DeferredApiV2 ( OBJGPU *pGpu, ChannelDescendant *Object, - PMETHOD Method, + METHOD *pMethod, NvU32 Offset, NvU32 Data ) { - PDEFERRED_API_OBJECT pDeferredApiObject = dynamicCast(Object, DeferredApiObject); - PDEFERRED_API_INFO pCliDeferredApi = NULL; + DeferredApiObject *pDeferredApiObject = dynamicCast(Object, DeferredApiObject); + DEFERRED_API_INFO *pCliDeferredApi = NULL; NV5080_CTRL_DEFERRED_API_PARAMS *pDeferredApi; NV_STATUS rmStatus = NV_OK; NvU32 paramSize = 0; NvHandle hDevice; NvBool bIsCtrlCall = NV_TRUE; - rmStatus = Class5080GetDeferredApiInfo(pDeferredApiObject, - Data, &pCliDeferredApi); + rmStatus = _Class5080GetDeferredApiInfo(pDeferredApiObject, + Data, &pCliDeferredApi); if (rmStatus == NV_OK) { pDeferredApi = pCliDeferredApi->pDeferredApiInfo; @@ -540,6 +587,8 @@ _class5080DeferredApiV2 const struct NVOC_EXPORTED_METHOD_DEF *pEntry; LOCK_ACCESS_TYPE access; NvU32 releaseFlags = 0; + CALL_CONTEXT callContext; + CALL_CONTEXT *pOldContext = NULL; portMemSet(&rmCtrlParams, 0, sizeof(RmCtrlParams)); rmCtrlParams.hClient = pCliDeferredApi->Client; @@ -590,22 +639,28 @@ _class5080DeferredApiV2 // Initialize the execution cookie serverControl_InitCookie(pEntry, &rmCtrlExecuteCookie); + // Set the call context as we use that to validate call permissions + // in some cases + portMemSet(&callContext, 0, sizeof(callContext)); + callContext.pResourceRef = RES_GET_REF(pSubdevice); + callContext.pClient = pRsClient; + callContext.secInfo = rmCtrlParams.secInfo; + callContext.pServer = &g_resServ; + callContext.pControlParams = &rmCtrlParams; + callContext.pLockInfo = rmCtrlParams.pLockInfo; + + if (RMCFG_FEATURE_PLATFORM_GSP && IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + { + NvU32 gfid = kchannelGetGfid(Object->pKernelChannel); + callContext.secInfo.pProcessToken = (void *)(NvU64) gfid; + } + + resservSwapTlsCallContext(&pOldContext, &callContext); + rmStatus = serverControl_Prologue(&g_resServ, &rmCtrlParams, &access, &releaseFlags); if (rmStatus == NV_OK) { - CALL_CONTEXT callContext; - CALL_CONTEXT *pOldContext = NULL; - - portMemSet(&callContext, 0, sizeof(callContext)); - callContext.pResourceRef = RES_GET_REF(pSubdevice); - callContext.pClient = pRsClient; - callContext.secInfo = rmCtrlParams.secInfo; - callContext.pServer = &g_resServ; - callContext.pControlParams = &rmCtrlParams; - callContext.pLockInfo = rmCtrlParams.pLockInfo; - resservSwapTlsCallContext(&pOldContext, &callContext); - if (pEntry->paramSize == 0) { typedef NV_STATUS (*CONTROL_EXPORT_FNPTR_NO_PARAMS)(void*); @@ -618,10 +673,9 @@ _class5080DeferredApiV2 CONTROL_EXPORT_FNPTR pFunc = ((CONTROL_EXPORT_FNPTR) pEntry->pFunc); rmStatus = pFunc((void*)pSubdevice, rmCtrlParams.pParams); } - - resservRestoreTlsCallContext(pOldContext); } + resservRestoreTlsCallContext(pOldContext); rmStatus = serverControl_Epilogue(&g_resServ, &rmCtrlParams, access, &releaseFlags, rmStatus); } @@ -640,7 +694,7 @@ cleanup: } else { - Class5080DelDeferredApi(pDeferredApiObject, Data); + _Class5080DelDeferredApi(pDeferredApiObject, Data); } } } @@ -656,9 +710,9 @@ static METHOD Nv50DeferredApi[] = NV_STATUS defapiGetSwMethods_IMPL ( - DeferredApiObject *pDeferredApi, - METHOD **ppMethods, - NvU32 *pNumMethods + DeferredApiObject *pDeferredApi, + METHOD **ppMethods, + NvU32 *pNumMethods ) { *ppMethods = Nv50DeferredApi; @@ -672,11 +726,12 @@ NvBool defapiIsSwMethodStalling_IMPL NvU32 hDeferredApi ) { - PDEFERRED_API_INFO pCliDeferredApi = NULL; - NV5080_CTRL_DEFERRED_API_PARAMS * pDeferredApiParams; + DEFERRED_API_INFO *pCliDeferredApi = NULL; + NV5080_CTRL_DEFERRED_API_PARAMS *pDeferredApiParams; - NV_STATUS rmStatus = Class5080GetDeferredApiInfo(pDeferredApi, - hDeferredApi, &pCliDeferredApi); + NV_STATUS rmStatus = _Class5080GetDeferredApiInfo(pDeferredApi, + hDeferredApi, + &pCliDeferredApi); if (rmStatus == NV_OK) { pDeferredApiParams = pCliDeferredApi->pDeferredApiInfo; diff --git a/src/nvidia/src/kernel/gpu/device.c b/src/nvidia/src/kernel/gpu/device.c index 0eedc106e..7974f6f76 100644 --- a/src/nvidia/src/kernel/gpu/device.c +++ b/src/nvidia/src/kernel/gpu/device.c @@ -344,7 +344,6 @@ deviceInit_IMPL pDevice->hTargetClient = hTargetClient; pDevice->hTargetDevice = hTargetDevice; - pDevice->pHostVgpuDevice = NULL; pDevice->pKernelHostVgpuDevice = NULL; pDevice->deviceInst = deviceInst; @@ -382,6 +381,12 @@ deviceInit_IMPL } } + if (allocFlags & NV_DEVICE_ALLOCATION_FLAGS_PLUGIN_CONTEXT) + { + NV_ASSERT_OR_RETURN(allocFlags & NV_DEVICE_ALLOCATION_FLAGS_HOST_VGPU_DEVICE, + NV_ERR_INVALID_ARGUMENT); + } + done: if (status != NV_OK) { diff --git a/src/nvidia/src/kernel/gpu/device_ctrl.c b/src/nvidia/src/kernel/gpu/device_ctrl.c index 0dc6915ad..b1b911318 100644 --- a/src/nvidia/src/kernel/gpu/device_ctrl.c +++ b/src/nvidia/src/kernel/gpu/device_ctrl.c @@ -54,7 +54,7 @@ deviceCtrlCmdGpuGetClasslist_IMPL { OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); return gpuGetClassList(pGpu, &pClassListParams->numClasses, NvP64_VALUE(pClassListParams->classList), ENG_INVALID); @@ -76,7 +76,7 @@ deviceCtrlCmdGpuGetClasslistV2_IMPL { OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); pClassListParams->numClasses = NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE; @@ -222,6 +222,25 @@ deviceCtrlCmdGpuGetVirtualizationMode_IMPL return NV_OK; } +/*! + * @brief This Command is used to get GPU SRIOV capabilities + * + * @return NV_OK + */ +NV_STATUS +deviceCtrlCmdGpuGetSriovCaps_IMPL +( + Device *pDevice, + NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); + + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + return gpuGetSriovCaps_HAL(pGpu, pParams); +} + /*! * @brief This command is used to find a subdevice handle by subdeviceinst */ @@ -277,7 +296,7 @@ deviceCtrlCmdGpuGetSparseTextureComputeMode_IMPL NV_STATUS status; OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); status = gpuGetSparseTextureComputeMode(pGpu, &pModeParams->defaultSetting, @@ -313,7 +332,7 @@ deviceCtrlCmdGpuSetSparseTextureComputeMode_IMPL NV_STATUS status = NV_ERR_NOT_SUPPORTED; OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); // // In SLI, both GPUs will have the same setting for sparse texture/compute @@ -364,7 +383,7 @@ deviceCtrlCmdGpuSetVgpuVfBar1Size_IMPL ) { OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); return gpuSetVFBarSizes_HAL(pGpu, pParams); } diff --git a/src/nvidia/src/kernel/gpu/device_share.c b/src/nvidia/src/kernel/gpu/device_share.c index 9b09f4caa..b74dae8e2 100644 --- a/src/nvidia/src/kernel/gpu/device_share.c +++ b/src/nvidia/src/kernel/gpu/device_share.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -243,6 +243,17 @@ deviceInitClientShare { flags |= VASPACE_FLAGS_PTETABLE_PMA_MANAGED; } + + // + // For RM unlinked SLI: the fixed offset requirement is enforced at the OBJGVASPACE + // level during allocations and mappings, so the Device flag must be converted + // into the internal VASPACE flag. + // + if (deviceAllocFlags & NV_DEVICE_ALLOCATION_FLAGS_VASPACE_REQUIRE_FIXED_OFFSET) + { + flags |= VASPACE_FLAGS_REQUIRE_FIXED_OFFSET; + } + status = vmmCreateVaspace(pVmm, vaspaceClass, 0, gpuMask, 0, vaLimit, pDevice->vaStartInternal, pDevice->vaLimitInternal, NULL, flags, &pVAS); diff --git a/src/nvidia/src/kernel/gpu/disp/arch/v02/kern_disp_0207.c b/src/nvidia/src/kernel/gpu/disp/arch/v02/kern_disp_0207.c new file mode 100644 index 000000000..050019c4d --- /dev/null +++ b/src/nvidia/src/kernel/gpu/disp/arch/v02/kern_disp_0207.c @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#define RM_STRICT_CONFIG_EMIT_DISP_ENGINE_DEFINITIONS 0 + +#include "gpu/gpu.h" +#include "gpu/disp/kern_disp.h" + +/*! + * @brief - Compute the value LSR_MIN_TIME to be set for swap barrier + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelDisplay KernelDisplay pointer + * @param[in] head head number + * @param[in] swapRdyHiLsrMinTime effective time in micro seconds for which + * SWAPRDY will be asserted. + * @param[out] computedLsrMinTime computed LsrMinTime to be set. + */ +NV_STATUS +kdispComputeLsrMinTimeValue_v02_07 +( + OBJGPU *pGpu, + KernelDisplay *pKernelDisplay, + NvU32 head, + NvU32 swapRdyHiLsrMinTime, + NvU32 *computedLsrMinTime +) +{ + // + // For Pascal and onwards LSR_MIN_TIME has been moved to static clock + //in ns from dispclock. Thus just send the swapRdyHiTime in ns. + // + *computedLsrMinTime = swapRdyHiLsrMinTime * 1000; + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/disp/arch/v03/kern_disp_0300.c b/src/nvidia/src/kernel/gpu/disp/arch/v03/kern_disp_0300.c index cd935a2c7..bc0dfe199 100644 --- a/src/nvidia/src/kernel/gpu/disp/arch/v03/kern_disp_0300.c +++ b/src/nvidia/src/kernel/gpu/disp/arch/v03/kern_disp_0300.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -32,6 +32,7 @@ #include "gpu/gpu.h" #include "gpu/disp/kern_disp.h" +#include "gpu/external_device/gsync.h" #include "disp/v03_00/dev_disp.h" @@ -108,6 +109,13 @@ kdispGetChannelNum_v03_00 } break; + case dispChnClass_Any: + // Assert incase of physical RM, Any channel is kernel only channel. + NV_ASSERT_OR_RETURN(RMCFG_FEATURE_KERNEL_RM, NV_ERR_INVALID_CHANNEL); + *pChannelNum = NV_PDISP_CHN_NUM_ANY; + status = NV_OK; + break; + default: NV_PRINTF(LEVEL_ERROR, "Unknown channel class %x\n", channelClass); status = NV_ERR_INVALID_CHANNEL; @@ -270,3 +278,105 @@ kdispSelectClass_v03_00_KERNEL return NV_OK; } + +/*! + * @brief Read line count and frame count from RG_DPCA. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelDisplay KernelDisplay pointer + * @param[in] head head index + * @param[out] pLineCount line count + * @param[out] pFrameCount frame count + * + * @return NV_STATUS + */ +NV_STATUS +kdispReadRgLineCountAndFrameCount_v03_00_KERNEL +( + OBJGPU *pGpu, + KernelDisplay *pKernelDisplay, + NvU32 head, + NvU32 *pLineCount, + NvU32 *pFrameCount +) +{ + NvU32 data32; + + if (head >= kdispGetNumHeads(pKernelDisplay)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + data32 = GPU_REG_RD32(pGpu,NV_PDISP_RG_DPCA(head)); + + *pLineCount = DRF_VAL(_PDISP, _RG_DPCA, _LINE_CNT, data32); + *pFrameCount = DRF_VAL(_PDISP, _RG_DPCA, _FRM_CNT, data32); + + return NV_OK; +} + +/*! + * @brief - restore original LSR_MIN_TIME + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelDisplay KernelDisplay pointer + * @param[in] head head number + * @param[out] oriLsrMinTime original LSR_MIN_TIME value + */ +void +kdispRestoreOriginalLsrMinTime_v03_00 +( + OBJGPU *pGpu, + KernelDisplay *pKernelDisplay, + NvU32 head, + NvU32 origLsrMinTime +) +{ + NvU32 feFliplock; + + feFliplock = GPU_REG_RD32(pGpu, NV_PDISP_FE_FLIPLOCK); + + feFliplock = FLD_SET_DRF_NUM(_PDISP, _FE_FLIPLOCK, _LSR_MIN_TIME, + origLsrMinTime, feFliplock); + + GPU_REG_WR32(pGpu, NV_PDISP_FE_FLIPLOCK, feFliplock); +} + +/*! + * @brief - Set LSR_MIN_TIME for swap barrier + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelDisplay KernelDisplay pointer + * @param[in] head head number + * @param[out] pOriLsrMinTime pointer to original LSR_MIN_TIME value + * @param[in] pNewLsrMinTime new LSR_MIN_TIME value to be set. If this is 0 + * use default LSR_MIN_TIME value of respective gpu. + */ +void +kdispSetSwapBarrierLsrMinTime_v03_00 +( + OBJGPU *pGpu, + KernelDisplay *pKernelDisplay, + NvU32 head, + NvU32 *pOrigLsrMinTime, + NvU32 newLsrMinTime +) +{ + NvU32 dsiFliplock; + + dsiFliplock = GPU_REG_RD32(pGpu, NV_PDISP_FE_FLIPLOCK); + *pOrigLsrMinTime = DRF_VAL(_PDISP, _FE_FLIPLOCK, _LSR_MIN_TIME, dsiFliplock); + + if (newLsrMinTime == 0) + { + dsiFliplock = FLD_SET_DRF_NUM(_PDISP, _FE_FLIPLOCK, _LSR_MIN_TIME, + FLIPLOCK_LSR_MIN_TIME_FOR_SAWP_BARRIER_V02, dsiFliplock); + } + else + { + dsiFliplock = FLD_SET_DRF_NUM(_PDISP, _FE_FLIPLOCK, _LSR_MIN_TIME, + newLsrMinTime, dsiFliplock); + } + + GPU_REG_WR32(pGpu, NV_PDISP_FE_FLIPLOCK, dsiFliplock); +} diff --git a/src/nvidia/src/kernel/gpu/disp/disp_channel.c b/src/nvidia/src/kernel/gpu/disp/disp_channel.c index 167cd57be..e24f07499 100644 --- a/src/nvidia/src/kernel/gpu/disp/disp_channel.c +++ b/src/nvidia/src/kernel/gpu/disp/disp_channel.c @@ -159,6 +159,17 @@ dispchnConstruct_IMPL if (rmStatus != NV_OK) return rmStatus; + if (internalDispChnClass == dispChnClass_Any) + { + // + // Any channel is kernel only channel, Physical RM doesn't need ANY channel information. + // return from here as ANY channel is constructed. + // + pDispChannel->DispClass = internalDispChnClass; + pDispChannel->InstanceNumber = channelInstance; + return NV_OK; + } + API_GPU_FULL_POWER_SANITY_CHECK(pGpu, NV_TRUE, NV_FALSE); SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY); { diff --git a/src/nvidia/src/kernel/gpu/disp/disp_common_ctrl_acpi.c b/src/nvidia/src/kernel/gpu/disp/disp_common_ctrl_acpi.c new file mode 100644 index 000000000..2112260ad --- /dev/null +++ b/src/nvidia/src/kernel/gpu/disp/disp_common_ctrl_acpi.c @@ -0,0 +1,650 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + /** + * This file implements rmctrls which + * (a) are declared in disp_common_ctrl_acpi.h; i.e. + * (i) are dispcmnCtrlCmd* functions + * (ii) which are not used by Tegra SOC NVDisplay and/or OS layer; and + * (b) are ACPI feature related + */ + +#include "gpu/disp/disp_objs.h" +#include "mxm_spec.h" +#include "nvacpitypes.h" +#include "nbci.h" +#include "nvhybridacpi.h" +#include "acpigenfuncs.h" +#include "platform/platform.h" +#include "gpu/disp/kern_disp.h" + +NV_STATUS +dispcmnCtrlCmdSpecificSetAcpiIdMapping_IMPL +( + DispCommon *pDispCommon, + NV0073_CTRL_SPECIFIC_SET_ACPI_ID_MAPPING_PARAMS *pParams +) +{ + OBJGPU *pGpu = DISPAPI_GET_GPU(pDispCommon); + OBJGPU *pOrigGpu = pGpu; + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJPFM *pPfm = SYS_GET_PFM(pSys); + NvU32 acpiIdx,index; + NvBool bcState = gpumgrGetBcEnabledStatus(pGpu); + NV_STATUS status = NV_OK; + + // index into the RM mapping table + index = 0; + for (acpiIdx = 0; acpiIdx < NV0073_CTRL_SPECIFIC_MAX_ACPI_DEVICES; ++acpiIdx) + { + // client gave us a subdevice number: get right pGpu for it + status = dispapiSetUnicastAndSynchronize_HAL( + staticCast(pDispCommon, DisplayApi), + DISPAPI_GET_GPUGRP(pDispCommon), + &pGpu, + pParams->mapTable[acpiIdx].subDeviceInstance); + if (status != NV_OK) + return status; + + if ((pParams->mapTable[acpiIdx].displayId) && + !((pParams->mapTable[acpiIdx].displayId) & (pParams->mapTable[acpiIdx].displayId - 1))) + { + // update the mapping table + pfmUpdateAcpiIdMapping(pPfm, + pGpu, + pParams->mapTable[acpiIdx].acpiId, + pParams->mapTable[acpiIdx].displayId, + pParams->mapTable[acpiIdx].dodIndex, + index); + // increment the index into the RM-side table only if we have a valid entry + ++index; + } + else + { + continue; + } + } + + if (gpumgrGetBcEnabledStatus(pGpu)) + { + // Grab the parent ... + pGpu = gpumgrGetDisplayParent(pGpu); + } + + pGpu = pOrigGpu; + gpumgrSetBcEnabledStatus(pGpu, bcState); + + return status; +} + +// +// This rmctrl MUST NOT touch hw since it's tagged as NO_GPUS_ACCESS in ctrl0073.def +// RM allow this type of rmctrl to go through when GPU is not available. +// +NV_STATUS +dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL +( + DispCommon *pDispCommon, + NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS *pAcpiMethodParams +) +{ + OBJGPU *pGpu = DISPAPI_GET_GPU(pDispCommon); + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJPFM *pPfm = SYS_GET_PFM(pSys); + OBJOS *pOS = GPU_GET_OS(pGpu); + NvU32 method = (NvU32)pAcpiMethodParams->method; + NvU32 outStatus = 0; + NvU16 inDataSize; // NOTE: must be NvU16, see below + NvU16 outDataSize; // NOTE: must be NvU16, see below + void *pInOutData = NULL; + NvU32 inOutDataSize; + NvBool bDoCopyOut = NV_FALSE; + NvU32 acpiId = 0; + NvU32 displayMask = 0; + NV_STATUS status = NV_OK; + + // + // Logically a single input/output buffer, but with 2 ptrs & 2 sizes. + // We have to do our own copyout + // Messing with output size at every level of the code + // + + inDataSize = pAcpiMethodParams->inDataSize; + outDataSize = pAcpiMethodParams->outDataSize; + inOutDataSize = (NvU32) NV_MAX(inDataSize, outDataSize); + + // Verify size + if ((outDataSize == 0) || + (pAcpiMethodParams->inData == NvP64_NULL) || + (pAcpiMethodParams->outData == NvP64_NULL)) + { + NV_PRINTF(LEVEL_ERROR, + "ERROR: NV0073_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD: Parameter " + "validation failed: outDataSize=%d inDataSize=%ud method = %ud\n", + (NvU32)outDataSize, (NvU32)inDataSize, method); + + return NV_ERR_INVALID_ARGUMENT; + } + + // Allocate memory for the combined in/out buffer + pInOutData = portMemAllocNonPaged(inOutDataSize); + if (pInOutData == NULL) + { + status = NV_ERR_NO_MEMORY; + NV_PRINTF(LEVEL_ERROR, + "ERROR: NV0073_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD: mem alloc failed\n"); + goto done; + } + + if (inDataSize) + { + portMemCopy(pInOutData, inDataSize, NvP64_VALUE(pAcpiMethodParams->inData), inDataSize); + } + + // jump to the method to be executed + switch (method) + { + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMX: + { + // + // get display mask from input buffer + // display mask is 4 byte long and available at byte 1 + // of the input buffer. + // byte 0 of the input buffer communicates the function (acquire(0)/release(1)) + // + portMemCopy((NvU8*) &displayMask, + sizeof(NvU32), + ((NvU8*) pInOutData) + NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMX_DISP_MASK_OFFSET, + sizeof(NvU32)); + + // get acpi id + acpiId = pfmFindAcpiId(pPfm, pGpu, displayMask); + + outStatus = pOS->osCallACPI_MXMX(pGpu, acpiId, pInOutData); + break; + + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUON: + { + outStatus = pOS->osCallACPI_NVHG_GPUON(pGpu, (NvU32*) pInOutData); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUOFF: + { + outStatus = pOS->osCallACPI_NVHG_GPUOFF(pGpu, (NvU32*) pInOutData); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUSTA: + { + outStatus = pOS->osCallACPI_NVHG_GPUSTA(pGpu, (NvU32*) pInOutData); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXDS: + { + // + // get acpi id from input buffer + // acpi id is 4 byte long and available at byte 4 + // of the input buffer. + // byte 0 of the input buffer communicates the function (Get Mux state(0)/Set display to active(1)) + // + portMemCopy(&acpiId, + sizeof(NvU32), + ((NvU8*) pInOutData) + NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXDS_DISP_MASK_OFFSET, + sizeof(NvU32)); + + outStatus = pOS->osCallACPI_NVHG_MXDS(pGpu, acpiId, (NvU32*) pInOutData); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDS: + { + // + // get acpi id from input buffer + // acpi id is 4 byte long and available at byte 4 + // of the input buffer. + // byte 0 of the input buffer communicates the function + // + portMemCopy(&acpiId, + sizeof(NvU32), + ((NvU8*) pInOutData) + NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDS_DISP_MASK_OFFSET, + sizeof(NvU32)); + + outStatus = pOS->osCallACPI_MXDS(pGpu, acpiId, (NvU32*) pInOutData); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDM: + { + // + // get acpi id from input buffer + // acpi id is 4 byte long and available at byte 4 + // of the input buffer. + // byte 0 of the input buffer communicates the function + // + portMemCopy(&acpiId, + sizeof(NvU32), + ((NvU8*) pInOutData) + NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDM_DISP_MASK_OFFSET, + sizeof(NvU32)); + + outStatus = pOS->osCallACPI_MXDM(pGpu, acpiId, (NvU32*) pInOutData); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXID: + { + // get acpi id from input buffer + portMemCopy(&acpiId, + sizeof(NvU32), + ((NvU8*) pInOutData) + NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXID_DISP_MASK_OFFSET, + sizeof(NvU32)); + outStatus = pOS->osCallACPI_MXID(pGpu, acpiId, (NvU32*) pInOutData); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_LRST: + { + portMemCopy(&acpiId, + sizeof(NvU32), + ((NvU8*) pInOutData) + NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_LRST_DISP_MASK_OFFSET, + sizeof(NvU32)); + + outStatus = pOS->osCallACPI_LRST(pGpu, acpiId, (NvU32*) pInOutData); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DDC_EDID: + { + portMemCopy(&acpiId, + sizeof(NvU32), + ((NvU8*) pInOutData) + NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DDC_EDID_DISP_MASK_OFFSET, + sizeof(NvU32)); + + NvU32 outSize = outDataSize; + outStatus = pOS->osCallACPI_DDC(pGpu, acpiId, (NvU8*) pInOutData, + &outSize, NV_TRUE /*bReadMultiBlock*/); + outDataSize = (NvU16) outSize; + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NVHG_MXMX: + { + // + // get acpi id from input buffer + // acpi id is 4 byte long and available at byte 4 + // of the input buffer. + // byte 0 of the input buffer communicates the function (acquire(0)/release(1)/get mux state(2)) + // + portMemCopy(&acpiId, + sizeof(NvU32), + ((NvU8*) pInOutData) + NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NVHG_MXMX_DISP_MASK_OFFSET, + sizeof(NvU32)); + + // get acpi id + acpiId = pfmFindAcpiId(pPfm, pGpu, displayMask); + + outStatus = pOS->osCallACPI_NVHG_MXMX(pGpu, acpiId, (NvU32*) pInOutData); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOS: + { + // + // get acpi id from input buffer + // acpi id is 4 byte long and available at byte 4 + // of the input buffer. + // byte 0 of the input buffer communicates the function (by ACPI spec) + // + portMemCopy(&acpiId, + sizeof(NvU32), + ((NvU8*) pInOutData) + NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOS_DISP_MASK_OFFSET, + sizeof(NvU32)); + + // get acpi id + acpiId = pfmFindAcpiId(pPfm, pGpu, displayMask); + + outStatus = pOS->osCallACPI_NVHG_DOS(pGpu, acpiId, (NvU32*) pInOutData); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_ROM: + { + outStatus = pGpu->pOS->osCallACPI_NVHG_ROM(pGpu, (NvU32*) pInOutData, (NvU32*) pInOutData); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DCS: + { + // get display mask from input buffer + portMemCopy(&acpiId, sizeof(NvU32), pInOutData, sizeof(NvU32)); + + outStatus = pOS->osCallACPI_NVHG_DCS(pGpu, acpiId, (NvU32*) pInOutData); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOD: + { + NvU32 size32 = inOutDataSize; + outStatus = pOS->osCallACPI_DOD(pGpu, (NvU32*) pInOutData, &size32); + outDataSize = (NvU16) size32; + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_SUPPORT: + { + outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_SUPPORT, (NvU32*) pInOutData, &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HYBRIDCAPS: + { + outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HYBRIDCAPS, (NvU32*) pInOutData, &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_POLICYSELECT: + { + outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_POLICYSELECT, (NvU32*) pInOutData, &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_POWERCONTROL: + { + + outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_POWERCONTROL, (NvU32*) pInOutData, &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_PLATPOLICY: + { + outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_PLATPOLICY, (NvU32*) pInOutData, &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_DISPLAYSTATUS: + { + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_MXM_3X)) + outStatus = pGpu->pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MXDP, (NvU32*)pInOutData, &outDataSize); + else + outStatus = pGpu->pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_DISPLAYSTATUS, (NvU32*)pInOutData, &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MDTL: + { + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_MXM_3X)) + outStatus = pGpu->pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MDTL, (NvU32*)pInOutData, &outDataSize); + else + outStatus = pGpu->pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_MDTL, (NvU32*)pInOutData, &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSMBLIST: + { + outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCSMBLIST, (NvU32*) pInOutData, &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSMBADDR: + { + outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCSMBADDR, (NvU32*) pInOutData, &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCREADBYTE: + { + outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCREADBYTE, (NvU32*) pInOutData, &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCSENDBYTE: + { + outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCSENDBYTE, (NvU32*) pInOutData, &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCGETSTATUS: + { + outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCGETSTATUS, (NvU32*) pInOutData, &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCTRIGDDC: + { + outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCTRIGDDC, (NvU32*) pInOutData, &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_HCGETDDC: + { + outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_HCGETDDC, (NvU32*) pInOutData, &outDataSize); + break; + } + + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXSS: + { + outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MXSS, (NvU32*) pInOutData, &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXMI: + { + outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MXMI, (NvU32*) pInOutData, &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXMS: + { + outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MXMS, (NvU32*) pInOutData, &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXPP: + { + outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MXPP, (NvU32*) pInOutData, &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXDP: + { + outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MXDP, (NvU32*) pInOutData, &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MDTL: + { + outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_MDTL, (NvU32*) pInOutData, &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_MXCB: + { + outStatus = kdispDsmMxmMxcbExecuteAcpi_HAL(pGpu, pKernelDisplay, pInOutData, &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_MXM_GETEVENTLIST: + { + outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_MXM, NV_ACPI_DSM_MXM_FUNC_GETEVENTLIST, (NvU32*) pInOutData, &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETMEMTABLE: + { + outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_GETMEMTABLE, (NvU32*) pInOutData, &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETMEMCFG: + { + outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_GETMEMCFG, (NvU32*) pInOutData, &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETOBJBYTYPE: + { + outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_GETOBJBYTYPE, (NvU32*) pInOutData, &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GETALLOBJS: + { + outStatus = pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVHG, NVHG_FUNC_GETALLOBJS, (NvU32*) pInOutData, &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_CTL_GETSUPPORTEDFUNC: + { + if (outDataSize >= sizeof(pGpu->acpi.dsmCurrentFuncSupport)) + { + outDataSize = sizeof(pGpu->acpi.dsmCurrentFuncSupport); + portMemCopy(pInOutData, outDataSize, &pGpu->acpi.dsmCurrentFuncSupport, outDataSize); + outStatus = NV_OK; + } + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_DISPLAYSTATUS: + { + outStatus = pOS->osCallACPI_DSM(pGpu, + pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_DISPLAYSTATUS-NV_ACPI_GENERIC_FUNC_START], + pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_DISPLAYSTATUS-NV_ACPI_GENERIC_FUNC_START], + (NvU32*) pInOutData, + &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_MDTL: + { + outStatus = pOS->osCallACPI_DSM(pGpu, + pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_MDTL-NV_ACPI_GENERIC_FUNC_START], + pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_MDTL-NV_ACPI_GENERIC_FUNC_START], + (NvU32*) pInOutData, + &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_MSTL: + { + outStatus = pOS->osCallACPI_DSM(pGpu, + pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_MSTL-NV_ACPI_GENERIC_FUNC_START], + pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_MSTL-NV_ACPI_GENERIC_FUNC_START], + (NvU32*) pInOutData, + &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETOBJBYTYPE: + { + outStatus = pOS->osCallACPI_DSM(pGpu, + pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_GETOBJBYTYPE-NV_ACPI_GENERIC_FUNC_START], + pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_GETOBJBYTYPE-NV_ACPI_GENERIC_FUNC_START], + (NvU32*) pInOutData, + &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETALLOBJS: + { + outStatus = pOS->osCallACPI_DSM(pGpu, + pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_GETALLOBJS-NV_ACPI_GENERIC_FUNC_START], + pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_GETALLOBJS-NV_ACPI_GENERIC_FUNC_START], + (NvU32*) pInOutData, + &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETEVENTLIST: + { + outStatus = pOS->osCallACPI_DSM(pGpu, + pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_GETEVENTLIST-NV_ACPI_GENERIC_FUNC_START], + pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_GETEVENTLIST-NV_ACPI_GENERIC_FUNC_START], + (NvU32*) pInOutData, + &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETBACKLIGHT: + { + outStatus = pOS->osCallACPI_DSM(pGpu, + pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_GETBACKLIGHT-NV_ACPI_GENERIC_FUNC_START], + pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_GETBACKLIGHT-NV_ACPI_GENERIC_FUNC_START], + (NvU32*) pInOutData, + &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_GENERIC_GETCALLBACKS: + { + outStatus = pOS->osCallACPI_DSM(pGpu, + pGpu->acpi.dsmCurrentFunc[NV_ACPI_GENERIC_FUNC_CALLBACKS-NV_ACPI_GENERIC_FUNC_START], + pGpu->acpi.dsmCurrentSubFunc[NV_ACPI_GENERIC_FUNC_CALLBACKS-NV_ACPI_GENERIC_FUNC_START], + (NvU32*) pInOutData, + &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NBCI_SUPPORTFUNCS: + { + outStatus = pOS->osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_NBCI, + NV_NBCI_FUNC_SUPPORT, + (NvU32*) pInOutData, + &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NBCI_PLATCAPS: + { + outStatus = pOS->osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_NBCI, + NV_NBCI_FUNC_PLATCAPS, + (NvU32*) pInOutData, + &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NBCI_PLATPOLICY: + { + outStatus = pOS->osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_NBCI, + NV_NBCI_FUNC_PLATPOLICY, + (NvU32*) pInOutData, + &outDataSize); + break; + } + case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_WMMX_NVOP_GPUON: + { + outStatus = pOS->osCallACPI_OPTM_GPUON(pGpu); + break; + } + default: + { + NV_PRINTF(LEVEL_ERROR, + "ERROR: NV0073_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD: Unrecognized Api Code: 0x%x\n", + method); + + status = NV_ERR_INVALID_ARGUMENT; + goto done; + } + } + + if (outStatus != NV_OK) + { + NV_PRINTF(LEVEL_INFO, + "ERROR: NV0073_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD: Execution failed " + "for method: 0x%x, status=0x%x\n", method, outStatus); + + // if it was a command we tried return the real status. + if (status == NV_OK) + status = outStatus; + + // do we need: status = outStatus; //XXX64 integration question + pAcpiMethodParams->outStatus = outStatus; + goto done; + } + + // NOTE: 'outDataSize' may have changed above. + if (outDataSize > pAcpiMethodParams->outDataSize) + { + NV_PRINTF(LEVEL_ERROR, + "ERROR: NV0073_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD: output buffer is " + "smaller then expected!\n"); + + //pAcpiMethodParams->outStatus = outStatus; //XXX64 check + //status = outStatus; //XXX64 check + status = NV_ERR_BUFFER_TOO_SMALL; + goto done; + } + + // all ok - so copy 'outdata' back to client + bDoCopyOut = NV_TRUE; + +done: + + // pass data out to client's output buffer + if (bDoCopyOut) + { + pAcpiMethodParams->outDataSize = outDataSize; + + portMemCopy(NvP64_VALUE(pAcpiMethodParams->outData), outDataSize, pInOutData, outDataSize); + } + + // release client's input buffer + portMemFree(pInOutData); + + return status; +} diff --git a/src/nvidia/src/kernel/gpu/disp/disp_common_kern_ctrl_minimal.c b/src/nvidia/src/kernel/gpu/disp/disp_common_kern_ctrl_minimal.c index 92a8bd6b8..0499ec19e 100644 --- a/src/nvidia/src/kernel/gpu/disp/disp_common_kern_ctrl_minimal.c +++ b/src/nvidia/src/kernel/gpu/disp/disp_common_kern_ctrl_minimal.c @@ -34,6 +34,7 @@ #include "os/os.h" #include "gpu/gpu.h" #include "gpu/disp/kern_disp.h" +#include "gpu/disp/head/kernel_head.h" #include "gpu/disp/disp_objs.h" #include "rmapi/rs_utils.h" #include "rmapi/rmapi.h" @@ -208,3 +209,34 @@ dispcmnCtrlCmdDpGenerateFakeInterrupt_IMPL return NV_OK; } + +NV_STATUS +dispcmnCtrlCmdSystemGetVblankCounter_IMPL +( + DispCommon *pDispCommon, + NV0073_CTRL_SYSTEM_GET_VBLANK_COUNTER_PARAMS *pVBCounterParams +) +{ + KernelDisplay *pKernelDisplay; + KernelHead *pKernelHead; + + pKernelDisplay = GPU_GET_KERNEL_DISPLAY(DISPAPI_GET_GPU(pDispCommon)); + if (pVBCounterParams->head >= kdispGetNumHeads(pKernelDisplay)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + pKernelHead = KDISP_GET_HEAD(pKernelDisplay, pVBCounterParams->head); + NV_ASSERT(pKernelHead); + + // + // Add a callback to start the vblank interrupt + // which will update the counter. + // + kheadSetVblankGatherInfo(DISPAPI_GET_GPU(pDispCommon), pKernelHead, NV_TRUE); + pVBCounterParams->verticalBlankCounter = + kheadGetVblankNormLatencyCounter_HAL(pKernelHead); + + return NV_OK; +} + diff --git a/src/nvidia/src/kernel/gpu/disp/disp_objs.c b/src/nvidia/src/kernel/gpu/disp/disp_objs.c index 0fb4c6143..b67d83765 100644 --- a/src/nvidia/src/kernel/gpu/disp/disp_objs.c +++ b/src/nvidia/src/kernel/gpu/disp/disp_objs.c @@ -63,7 +63,7 @@ dispapiConstruct_IMPL NvBool bBcResource; NvU32 i; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); // Use gpuGetByRef instead of GpuResource because it will work even if resource // isn't a GpuResource. diff --git a/src/nvidia/src/kernel/gpu/disp/arch/v04/kernel_head_gpu.c b/src/nvidia/src/kernel/gpu/disp/head/arch/v04/kernel_head_gpu_0400.c similarity index 89% rename from src/nvidia/src/kernel/gpu/disp/arch/v04/kernel_head_gpu.c rename to src/nvidia/src/kernel/gpu/disp/head/arch/v04/kernel_head_gpu_0400.c index 0d3e5558f..3988906e3 100644 --- a/src/nvidia/src/kernel/gpu/disp/arch/v04/kernel_head_gpu.c +++ b/src/nvidia/src/kernel/gpu/disp/head/arch/v04/kernel_head_gpu_0400.c @@ -30,13 +30,7 @@ void kheadResetPendingVblank_v04_00_KERNEL(OBJGPU *pGpu, KernelHead *pKernelHead writeIntr = DRF_DEF(_PDISP, _FE_EVT_STAT_HEAD_TIMING, _LAST_DATA, _RESET); - GPU_REG_WR32(pGpu, NV_PDISP_FE_EVT_STAT_HEAD_TIMING(pKernelHead->PublicId), - writeIntr); -} - -void kheadResetPendingVblankForKernel_v04_00_KERNEL(OBJGPU *pGpu, KernelHead *pKernelHead, THREAD_STATE_NODE *pThreadState) -{ - kheadResetPendingVblank_HAL(pGpu, pKernelHead, pThreadState); + GPU_REG_WR32(pGpu, NV_PDISP_FE_EVT_STAT_HEAD_TIMING(pKernelHead->PublicId), writeIntr); } NvU32 kheadReadPendingVblank_v04_00_KERNEL(OBJGPU *pGpu, KernelHead *pKernelHead, NvU32 headIntrMask) @@ -45,7 +39,9 @@ NvU32 kheadReadPendingVblank_v04_00_KERNEL(OBJGPU *pGpu, KernelHead *pKernelHead NvU32 intr = GPU_REG_RD32(pGpu, NV_PDISP_FE_RM_INTR_DISPATCH); if (!FLD_IDX_TEST_DRF(_PDISP, _FE_RM_INTR_DISPATCH, _HEAD_TIMING, pKernelHead->PublicId, _PENDING, intr)) + { return headIntrMask; + } intr = GPU_REG_RD32(pGpu, NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING(pKernelHead->PublicId)); diff --git a/src/nvidia/src/kernel/gpu/disp/head/kernel_head_gpu.c b/src/nvidia/src/kernel/gpu/disp/head/kernel_head_gpu.c new file mode 100644 index 000000000..a06c58276 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/disp/head/kernel_head_gpu.c @@ -0,0 +1,126 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gpu/disp/head/kernel_head.h" +#include "gpu/disp/kern_disp.h" +#include "objtmr.h" + +// Callback proc for vblank info gathering +static NV_STATUS +_kheadSetVblankGatherInfoCallback +( + POBJGPU pGpu, + void *Object, + NvU32 param1, + NvV32 BuffNum, + NV_STATUS Status +) +{ + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + // We get the head from param1. Beware that this is what we told the vblank support to tell us. + KernelHead *pKernelHead = KDISP_GET_HEAD(pKernelDisplay, param1); + NvU32 Timeout = 0; + + Timeout = kheadTickVblankInfo(pGpu, pKernelHead); + + if (Timeout == 0) + { + // Time to kill off our persistence. The vblank service will remove us when we clear the persitent flag durring a callback. + pKernelHead->Vblank.Callback.gatherInfo.Flags &= ~VBLANK_CALLBACK_FLAG_PERSISTENT; + } + + return NV_OK; +} + +void +kheadSetVblankGatherInfo_IMPL +( + OBJGPU *pGpu, + KernelHead *pKernelHead, + NvBool enable +) +{ + if(enable) + { + // + // Update the timeout member to some number of seconds worth of callbacks. + // Note we're assuming 60 Hz here which doesn't really matter since + // that's what headAddVblankCallback assumes as well. + // + pKernelHead->Vblank.Info.Timeout = 60 * VBLANK_INFO_GATHER_KEEPALIVE_SECONDS; + + // + // Schedule a persistent vblank callback to handle the updates. + // This will enable vblank IRQs if not already running. + // + pKernelHead->Vblank.Callback.gatherInfo.Proc = _kheadSetVblankGatherInfoCallback; + pKernelHead->Vblank.Callback.gatherInfo.pObject = NULL; + pKernelHead->Vblank.Callback.gatherInfo.bObjectIsChannelDescendant = NV_FALSE; + pKernelHead->Vblank.Callback.gatherInfo.Param1 = pKernelHead->PublicId; + pKernelHead->Vblank.Callback.gatherInfo.Param2 = 0; + pKernelHead->Vblank.Callback.gatherInfo.Status = NV_OK; + pKernelHead->Vblank.Callback.gatherInfo.Flags = VBLANK_CALLBACK_FLAG_SPECIFIED_VBLANK_NEXT | VBLANK_CALLBACK_FLAG_PERSISTENT; + + kheadAddVblankCallback(pGpu, pKernelHead, &pKernelHead->Vblank.Callback.gatherInfo); + + NV_PRINTF(LEVEL_INFO, "VBlank Gather Info requested,\n" + " vblank service scheduled on head %d.\n", + pKernelHead->PublicId); + } + else + { + kheadDeleteVblankCallback(pGpu, pKernelHead, &pKernelHead->Vblank.Callback.gatherInfo); + } +} + +NvU32 +kheadTickVblankInfo_IMPL +( + OBJGPU *pGpu, + KernelHead *pKernelHead +) +{ + OBJTMR *pTmr = GPU_GET_TIMER(pGpu); + NvU64 Time; + NvU32 Delta; + NvU32 Average; + + // Get current time. + Time = tmrGetTime_HAL(pGpu, pTmr); + + pKernelHead->Vblank.Info.Time.Current = Time; + if (pKernelHead->Vblank.Info.Count > 2) + { + Delta = NvU64_LO32(pKernelHead->Vblank.Info.Time.Current - pKernelHead->Vblank.Info.Time.Last); + + Average = pKernelHead->Vblank.Info.Time.Average; + Average = (((Average << 2) - Average) + Delta) >> 2; + pKernelHead->Vblank.Info.Time.Average = Average; + } + pKernelHead->Vblank.Info.Count++; + pKernelHead->Vblank.Info.Time.Last = Time; + + pKernelHead->Vblank.Info.Timeout--; + + return pKernelHead->Vblank.Info.Timeout; +} diff --git a/src/nvidia/src/kernel/gpu/disp/inst_mem/arch/v03/disp_inst_mem_0300.c b/src/nvidia/src/kernel/gpu/disp/inst_mem/arch/v03/disp_inst_mem_0300.c index 7c2373559..0bc361d1d 100644 --- a/src/nvidia/src/kernel/gpu/disp/inst_mem/arch/v03/disp_inst_mem_0300.c +++ b/src/nvidia/src/kernel/gpu/disp/inst_mem/arch/v03/disp_inst_mem_0300.c @@ -102,8 +102,6 @@ instmemHashFunc_v03_00 { NV_ASSERT_OR_RETURN(pResult, NV_ERR_INVALID_ARGUMENT); - // channel id is the range of 0-80 (as defined by the NV_PDISP_CHN_NUM_*) - NV_ASSERT(!(dispChannelNum >> 7)); // // The hash function for display will be: diff --git a/src/nvidia/src/kernel/gpu/disp/inst_mem/disp_inst_mem.c b/src/nvidia/src/kernel/gpu/disp/inst_mem/disp_inst_mem.c index 99cb36616..6cc52a4b2 100644 --- a/src/nvidia/src/kernel/gpu/disp/inst_mem/disp_inst_mem.c +++ b/src/nvidia/src/kernel/gpu/disp/inst_mem/disp_inst_mem.c @@ -21,7 +21,7 @@ * DEALINGS IN THE SOFTWARE. */ -/**************************** Instmem Rotuines *****************************\ +/**************************** Instmem Routines *****************************\ * * * Display instance memory object function Definitions. * * * @@ -339,17 +339,12 @@ instmemDestroy ) { // Free up the inst mem descriptors - if (pInstMem->pInstMemDesc != NULL) - { - memdescDestroy(pInstMem->pInstMemDesc); - pInstMem->pInstMemDesc = NULL; - } - if (pInstMem->pAllocedInstMemDesc != NULL) - { - memdescFree(pInstMem->pAllocedInstMemDesc); - memdescDestroy(pInstMem->pAllocedInstMemDesc); - pInstMem->pAllocedInstMemDesc = NULL; - } + memdescDestroy(pInstMem->pInstMemDesc); + pInstMem->pInstMemDesc = NULL; + + memdescFree(pInstMem->pAllocedInstMemDesc); + memdescDestroy(pInstMem->pAllocedInstMemDesc); + pInstMem->pAllocedInstMemDesc = NULL; if (pInstMem->pInstHeap != NULL) { @@ -764,7 +759,9 @@ _instmemProbeHashEntry limit = hash + pInstMem->nHashTableEntries; // loop over whole table - for (i = hash; i < limit; i++) { NvU32 htEntry = i & (pInstMem->nHashTableEntries - 1); + for (i = hash; i < limit; i++) + { + NvU32 htEntry = i & (pInstMem->nHashTableEntries - 1); if ((pInstMem->pHashTable[htEntry].pDispChannel == pDispChannel) && (pInstMem->pHashTable[htEntry].pContextDma == pContextDma)) diff --git a/src/nvidia/src/kernel/gpu/disp/kern_disp.c b/src/nvidia/src/kernel/gpu/disp/kern_disp.c index 1c949b81b..4dc8703c7 100644 --- a/src/nvidia/src/kernel/gpu/disp/kern_disp.c +++ b/src/nvidia/src/kernel/gpu/disp/kern_disp.c @@ -44,6 +44,8 @@ #include "gpu_mgr/gpu_mgr.h" #include "objtmr.h" #include "core/locks.h" +#include "ctrl/ctrl402c.h" +#include "platform/acpi_common.h" #include "kernel/gpu/intr/engine_idx.h" @@ -73,6 +75,7 @@ #include "class/clc67b.h" #include "class/clc67d.h" #include "class/clc67e.h" +#include "class/clc77f.h" //NVC77F_ANY_CHANNEL_DMA #include "class/clc77d.h" @@ -159,11 +162,8 @@ kdispDestructInstMem_IMPL KernelDisplay *pKernelDisplay ) { - if (pKernelDisplay->pInst != NULL) - { - objDelete(pKernelDisplay->pInst); - pKernelDisplay->pInst = NULL; - } + objDelete(pKernelDisplay->pInst); + pKernelDisplay->pInst = NULL; } /*! Constructor for Kernel head */ @@ -202,11 +202,8 @@ kdispDestructKhead_IMPL for (headIdx = 0; headIdx < OBJ_MAX_HEADS; headIdx++) { - if (pKernelDisplay->pKernelHead[headIdx] != NULL) - { - objDelete(pKernelDisplay->pKernelHead[headIdx]); - pKernelDisplay->pKernelHead[headIdx] = NULL; - } + objDelete(pKernelDisplay->pKernelHead[headIdx]); + pKernelDisplay->pKernelHead[headIdx] = NULL; } } @@ -240,6 +237,42 @@ kdispStatePreInitLocked_IMPL(OBJGPU *pGpu, return status; } +NV_STATUS +kdispInitBrightcStateLoad_IMPL(OBJGPU *pGpu, + KernelDisplay *pKernelDisplay) +{ + NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS *pBrightcInfo = NULL; + NvU32 status = NV_ERR_NOT_SUPPORTED; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + pBrightcInfo = portMemAllocNonPaged(sizeof(NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS)); + if (pBrightcInfo == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Could not allocate memory for pBrightcInfo\n"); + return NV_ERR_NO_MEMORY; + } + portMemSet(pBrightcInfo, 0, sizeof(*pBrightcInfo)); + + pBrightcInfo->status = status; + if ((pKernelDisplay != NULL) && (pKernelDisplay->pStaticInfo->internalDispActiveMask != 0)) + { + // Fill in the Backlight Method Data. + pBrightcInfo->backLightDataSize = sizeof(pBrightcInfo->backLightData); + status = pGpu->pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_CURRENT, NV_ACPI_GENERIC_FUNC_GETBACKLIGHT, + (NvU32 *)(pBrightcInfo->backLightData), + &pBrightcInfo->backLightDataSize); + pBrightcInfo->status = status; + } + + status = pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD, + pBrightcInfo, sizeof(*pBrightcInfo)); + + portMemFree(pBrightcInfo); + + return status; +} + NV_STATUS kdispStateInitLocked_IMPL(OBJGPU *pGpu, KernelDisplay *pKernelDisplay) @@ -264,14 +297,42 @@ kdispStateInitLocked_IMPL(OBJGPU *pGpu, exit); pKernelDisplay->pStaticInfo = pStaticInfo; + pKernelDisplay->numHeads = pStaticInfo->numHeads; pStaticInfo = NULL; + // Initiate Brightc module state load + status = kdispInitBrightcStateLoad_HAL(pGpu, pKernelDisplay); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "rmapi control call for brightc state load failed\n"); + goto exit; + } + if (pKernelDisplay->pInst != NULL) { NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, instmemStateInitLocked(pGpu, pKernelDisplay->pInst), exit); } + // Initialize any external daughterboards that + // might be out there. + + pGpu->i2cPortForExtdev = NV402C_CTRL_NUM_I2C_PORTS; + + if (pKernelDisplay->pStaticInfo->i2cPort == NV402C_CTRL_NUM_I2C_PORTS) + { + NV_PRINTF(LEVEL_INFO, "Error in getting valid I2Cport for Extdevice or extdevice doesn't exist\n"); + } + else + { + pGpu->i2cPortForExtdev = pKernelDisplay->pStaticInfo->i2cPort; + + if (NV_OK != gpuExtdevConstruct_HAL(pGpu)) + { + NV_PRINTF(LEVEL_INFO, "gpuExtdevConstruct() failed or not supported\n"); + } + } + if (pKernelDisplay->getProperty(pKernelDisplay, PDB_PROP_KDISP_IMP_ENABLE)) { // NOTE: Fills IMP parameters and populate those to disp object in Tegra @@ -422,6 +483,12 @@ kdispGetIntChnClsForHwCls_IMPL *pDispChnClass = dispChnClass_Win; break; + case NVC77F_ANY_CHANNEL_DMA: + // Assert incase of physical RM, Any channel is kernel only channel. + NV_ASSERT_OR_RETURN(RMCFG_FEATURE_KERNEL_RM, NV_ERR_INVALID_CHANNEL); + *pDispChnClass = dispChnClass_Any; + break; + default: NV_PRINTF(LEVEL_ERROR, "Unknown channel class %x\n", hwClass); return NV_ERR_INVALID_ARGUMENT; @@ -875,11 +942,6 @@ kdispServiceVblank_KERNEL // DPC/BottomHalf/whatever to service the rest of the // vblank callback queues // - for(i=0; i< OBJ_MAX_HEADS; i++) - { - pKernelHead = KDISP_GET_HEAD(pKernelDisplay, i); - kheadResetPendingVblankForKernel_HAL(pGpu, pKernelHead, pThreadState); - } } else { diff --git a/src/nvidia/src/kernel/gpu/external_device/arch/kepler/kern_external_device_gk104.c b/src/nvidia/src/kernel/gpu/external_device/arch/kepler/kern_external_device_gk104.c new file mode 100644 index 000000000..da08da205 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/external_device/arch/kepler/kern_external_device_gk104.c @@ -0,0 +1,105 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gpu/external_device/gsync.h" +#include "gpu/external_device/external_device.h" +#include "os/os.h" +#include "ctrl/ctrl402c.h" + +#include "gpu/external_device/dac_p2060.h" +#include "dev_p2060.h" + +NV_STATUS +gpuExtdevConstruct_GK104(OBJGPU *pGpu) +{ + NvU32 index; + NvBool foundDevice = NV_FALSE; + + pfextdevConstruct pConstruct[] = + { + extdevConstruct_P2060, + 0 // terminates list + }; + + union + { + DACP2060EXTERNALDEVICE P2060; + DACEXTERNALDEVICE ExtDevice; + } *pExtDeviceTest = NULL; + + pExtDeviceTest = portMemAllocNonPaged(sizeof(*pExtDeviceTest)); + if (pExtDeviceTest == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Out of memory.\n"); + return NV_ERR_NO_MEMORY; + } + + if (!(IS_EMULATION(pGpu))) + { + for (index = 0; pConstruct[index]; index++) + { + portMemSet(pExtDeviceTest, 0, sizeof(*pExtDeviceTest)); + + // + // Map this extdev i2c port to pGpu. + // It will be needed to detect external device/access extdev registers. + // + + if ((pConstruct[index])(pGpu, &pExtDeviceTest->ExtDevice)) + { + if (pExtDeviceTest->ExtDevice.pI->setI2cHandles(pGpu, &pExtDeviceTest->ExtDevice)) + { + if (pExtDeviceTest->ExtDevice.pI->GetDevice(pGpu, &pExtDeviceTest->ExtDevice)) + { + NV_PRINTF(LEVEL_INFO, + "EXTDEV: device is connecting\n"); + if (pExtDeviceTest->ExtDevice.pI->Attach(pGpu, (PDACEXTERNALDEVICE *) &pExtDeviceTest)) + { + if (pExtDeviceTest->ExtDevice.pI->Init(pGpu, &pExtDeviceTest->ExtDevice)) + { + foundDevice = NV_TRUE; + break; + } + } + } + } + + if (!foundDevice) + { + pExtDeviceTest->ExtDevice.pI->Destroy(pGpu, &pExtDeviceTest->ExtDevice); + } + } + } + } + + if (!foundDevice) + { + portMemFree(pExtDeviceTest); + + // Set back extdev i2c to default value. + pGpu->i2cPortForExtdev = NV402C_CTRL_NUM_I2C_PORTS; + } + + return NV_OK; +} + diff --git a/src/nvidia/src/kernel/gpu/external_device/arch/kepler/kern_gsync_p2060.c b/src/nvidia/src/kernel/gpu/external_device/arch/kepler/kern_gsync_p2060.c new file mode 100644 index 000000000..e9c1ba7c8 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/external_device/arch/kepler/kern_gsync_p2060.c @@ -0,0 +1,5463 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvrm_registry.h" +#include "objtmr.h" +#include "gpu/external_device/gsync.h" +#include "dev_p2060.h" +#include "gpu/external_device/dac_p2060.h" +#include "gpu_mgr/gpu_mgr.h" +#include "gpu/disp/kern_disp.h" +#include "rmapi/rmapi_utils.h" +#include "class/cl402c.h" // NV40_I2C +#include "kernel/gpu/i2c/i2c_api.h" +/* + * statics + */ + +static NvBool GpuIsP2060Master (OBJGPU *, PDACP2060EXTERNALDEVICE); +static NvBool GpuIsP2060Connected(OBJGPU *, PDACP2060EXTERNALDEVICE); +static NvBool GpuIsMosaicTimingSlave(OBJGPU *, PDACP2060EXTERNALDEVICE); +static NvBool GpuIsConnectedToMasterViaBridge(OBJGPU *, PDACP2060EXTERNALDEVICE); + +static OBJGPU* GetP2060MasterableGpu (OBJGPU *, PDACP2060EXTERNALDEVICE); +static OBJGPU* GetP2060WatchdogGpu (OBJGPU *, PDACP2060EXTERNALDEVICE); + +static NV_STATUS GetP2060GpuLocation (OBJGPU *, PDACP2060EXTERNALDEVICE, NvU32*); +static NV_STATUS GetP2060ConnectorIndexFromGpu (OBJGPU *, PDACP2060EXTERNALDEVICE, NvU32*); +static NvU32 GetP2060GpuSnapshot (OBJGPU *, PDACP2060EXTERNALDEVICE); + +static void gsyncProgramFramelockEnable_P2060(OBJGPU *, PDACP2060EXTERNALDEVICE, NvU32, NvBool); +static NvBool gsyncIsStereoEnabled_p2060 (OBJGPU *, PDACEXTERNALDEVICE); +static NV_STATUS gsyncProgramExtStereoPolarity_P2060 (OBJGPU *, PDACEXTERNALDEVICE); + +static NV_STATUS gsyncProgramSlaves_P2060(OBJGPU *, PDACP2060EXTERNALDEVICE, NvU32); +static NvU32 gsyncReadSlaves_P2060(OBJGPU *, PDACP2060EXTERNALDEVICE); +static NV_STATUS gsyncProgramMaster_P2060(OBJGPU *, PDACP2060EXTERNALDEVICE, NvU32, NvBool, NvBool); +static NvU32 gsyncReadMaster_P2060(OBJGPU *, PDACP2060EXTERNALDEVICE); + +static NV_STATUS gsyncUpdateGsyncStatusSnapshot_P2060(OBJGPU *, PDACEXTERNALDEVICE); + +static void gsyncCancelWatchdog_P2060(PDACP2060EXTERNALDEVICE); +static NV_STATUS gsyncDisableFrameLockInterrupt_P2060(PDACEXTERNALDEVICE); +static NV_STATUS gsyncEnableFramelockInterrupt_P2060(PDACEXTERNALDEVICE); +static NV_STATUS gsyncDisableNonFramelockInterrupt_P2060(OBJGPU *, PDACEXTERNALDEVICE); +static NV_STATUS gsyncEnableNonFramelockInterrupt_P2060(OBJGPU *, PDACEXTERNALDEVICE); +static void gsyncResetMosaicData_P2060(NvU32, PDACP2060EXTERNALDEVICE); +static NV_STATUS gsyncUpdateSwapRdyConnectionForGpu_P2060(OBJGPU *, PDACP2060EXTERNALDEVICE, NvBool); + +static NvBool gsyncIsFrameLocked_P2060(PDACP2060EXTERNALDEVICE); +static NvBool gsyncIsOnlyFrameLockMaster_P2060(PDACP2060EXTERNALDEVICE); +static NvBool gsyncIsFrameLockMaster_P2060(PDACP2060EXTERNALDEVICE); +static NvBool gsyncIsP2060MasterBoard(OBJGPU *, PDACP2060EXTERNALDEVICE); + +static NV_STATUS gsyncSetLsrMinTime(OBJGPU *, PDACEXTERNALDEVICE, NvU32); + +static NV_STATUS gsyncUpdateFrameCount_P2060(PDACP2060EXTERNALDEVICE, OBJGPU *); +static NvU32 gsyncGetNumberOfGpuFrameCountRollbacks_P2060(NvU32, NvU32, NvU32); +static NV_STATUS gsyncFrameCountTimerService_P2060(OBJGPU *, OBJTMR *, void *); +static NV_STATUS gsyncResetFrameCountData_P2060(OBJGPU *, PDACP2060EXTERNALDEVICE); + +static NV_STATUS gsyncGpuStereoHeadSync(OBJGPU *, NvU32, PDACEXTERNALDEVICE, NvU32); +static NvBool supportsLargeSyncSkew(PDACEXTERNALDEVICE); +static NvBool needsMasterBarrierWar(PDACEXTERNALDEVICE); +static NvBool isFirmwareRevMismatch(OBJGPU *, DAC_EXTERNAL_DEVICE_REVS); + +static NvBool isBoardWithNvlinkQsyncContention(POBJGPU); +static void _extdevService(NvU32 , void *); + +NvBool +extdevGetDevice_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExternalDevice +) +{ + NvU8 revId; + NvU8 data; + DAC_EXTERNAL_DEVICES externalDeviceId; + DAC_EXTERNAL_DEVICE_REVS externalDeviceRev; + NV_STATUS status; + + if (!RMCFG_FEATURE_EXTDEV_GSYNC_P2060 || + IS_EMULATION(pGpu) || IS_SIMULATION(pGpu)) + { + return NV_FALSE; + } + + // Read the FPGA revision register + status = readregu008_extdevice(pGpu, pExternalDevice, (NvU8)NV_P2060_FPGA, &data); + if (status != NV_OK) + { + return NV_FALSE; + } + revId = data; + + // Decode the register value into device ID + if (DRF_VAL(_P2060, _FPGA, _ID, data) == NV_P2060_FPGA_ID_5) + { + externalDeviceId = DAC_EXTERNAL_DEVICE_P2060; + } + else if (DRF_VAL(_P2061, _FPGA, _ID, data) == NV_P2061_FPGA_ID_4) + { + externalDeviceId = DAC_EXTERNAL_DEVICE_P2061; + } + else + { + return NV_FALSE; + } + + // Decode the register value into device revision (major revision) + externalDeviceRev = DRF_VAL(_P2060, _FPGA, _REV, data); + + // Read device extended revision (minor revision) + status = readregu008_extdevice(pGpu, pExternalDevice, (NvU8)NV_P2060_FPGA_EXREV, &data); + if (status != NV_OK) + { + return NV_FALSE; + } + + // Caching revId, device ID, device revision, and device extended revision + pExternalDevice->revId = revId; + pExternalDevice->deviceId = externalDeviceId; + pExternalDevice->deviceRev = externalDeviceRev; + pExternalDevice->deviceExRev = data; + + return NV_TRUE; +} + +/* + * Return Extdev with setting of the data structures and + * function pointers for P2060. + */ +PDACEXTERNALDEVICE +extdevConstruct_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExternalDevice +) +{ + DACP2060EXTERNALDEVICE *pThis = (PDACP2060EXTERNALDEVICE)pExternalDevice; + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + NvU32 iface, head, i; + NvU32 numHeads = kdispGetNumHeads(pKernelDisplay); + + if ( !extdevConstruct_Base(pGpu, pExternalDevice) ) + { + return 0; + } + + // Setup interfaces + pThis->ExternalDevice.pI->Destroy = extdevDestroy_P2060; + pThis->ExternalDevice.pI->Attach = gsyncAttachExternalDevice_P2060; + + pThis->ExternalDevice.pI->GetDevice = extdevGetDevice_P2060; + pThis->ExternalDevice.pI->Init = extdevInit_P2060; + + pThis->ExternalDevice.pI->Service = extdevService_P2060; + pThis->ExternalDevice.pI->Watchdog = extdevWatchdog_P2060; + pThis->ExternalDevice.pI->setI2cHandles = extdevSaveI2cHandles_P2060; + + + // Init data members + pThis->ExternalDevice.I2CAddr = 0x20; + pThis->ExternalDevice.I2CPort = pGpu->i2cPortForExtdev; + pThis->ExternalDevice.MaxGpus = NV_P2060_MAX_IFACES_PER_GSYNC * NV_P2060_MAX_GPUS_PER_IFACE; + + pThis->gpuAttachMask = 0; + pThis->id = 0; + pThis->watchdogCountDownValue = 0; + pThis->isNonFramelockInterruptEnabled = NV_FALSE; + pThis->interruptEnabledInterface = 0; + pThis->tSwapRdyHi = 0; + pThis->tSwapRdyHiLsrMinTime = 0; + + //init FrameCountData + pThis->FrameCountData.totalFrameCount = 0; + pThis->FrameCountData.currentFrameCount = 0; + pThis->FrameCountData.initialDifference = 0; + pThis->FrameCountData.numberOfRollbacks = 0; + pThis->FrameCountData.previousFrameCount = 0; + pThis->FrameCountData.lastFrameCounterQueryTime = 0; + pThis->FrameCountData.bReCheck = 0; + pThis->FrameCountData.vActive = 0; + pThis->FrameCountData.isFrmCmpMatchIntMasterEnabled = NV_FALSE; + pThis->FrameCountData.enableFrmCmpMatchIntSlave = NV_FALSE; + pThis->FrameCountData.head = NV_P2060_MAX_HEADS_PER_GPU; + pThis->FrameCountData.iface = NV_P2060_MAX_IFACES_PER_GSYNC; + + for (iface = 0; iface < NV_P2060_MAX_IFACES_PER_GSYNC; iface++) + { + pThis->Iface[iface].GpuInfo.gpuId = NV0000_CTRL_GPU_INVALID_ID; + pThis->Iface[iface].GpuInfo.connected = NV_FALSE; + + pThis->Iface[iface].RasterSyncGpio.saved = NV_FALSE; + pThis->Iface[iface].DsiFliplock.saved = NV_FALSE; + + for (head = 0; head < numHeads; head++) + { + pThis->Iface[iface].Sync.Master[head] = 0; + pThis->Iface[iface].Sync.Slaved[head] = 0; + pThis->Iface[iface].Sync.LocalSlave[head] = 0; + } + + pThis->Iface[iface].lastEventNotified = 0; + pThis->Iface[iface].gainedSync = 0; + + pThis->i2cHandles[iface].hClient = 0; + pThis->i2cHandles[iface].hDevice = 0; + pThis->i2cHandles[iface].hSubdevice = 0; + pThis->i2cHandles[iface].hSubscription = 0; + pThis->i2cHandles[iface].gpuId = 0; + } + + //init MosaicData + for (i = 0; i < NV_P2060_MAX_MOSAIC_GROUPS; i++) + { + gsyncResetMosaicData_P2060(i, pThis); + } + + return pExternalDevice; +} + +/* + * setup device registers + */ +static void +_externalDeviceInit_P2060 +( + OBJGPU *pGpu, + NvBool bExtDevFound +) +{ + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NvU32 hClient = pGpu->hInternalClient; + NvU32 hSubdevice = pGpu->hInternalSubdevice; + NV_STATUS status = NV_OK; + NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS ctrlParams = {0}; + + ctrlParams.bExtDevFound = bExtDevFound; + + status = pRmApi->Control(pRmApi, hClient, hSubdevice, + NV2080_CTRL_CMD_INTERNAL_GSYNC_ATTACH_AND_INIT, + &ctrlParams, sizeof(ctrlParams)); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Extdev GPIO interrupt enable failed\n"); + } + else + { + pKernelDisplay->bExtdevIntrSupported = NV_TRUE; + } + + return; +} + +NV_STATUS +gsyncFindGpuHandleLocation +( + DACEXTERNALDEVICE *pExternalDevice, + NvU32 gpuId, + NvU32 *iface +) +{ + DACP2060EXTERNALDEVICE *pThis = (PDACP2060EXTERNALDEVICE)pExternalDevice; + NvU32 tempIface; + NV_STATUS rmStatus = NV_ERR_GENERIC; + + for (tempIface = 0; tempIface < NV_P2060_MAX_IFACES_PER_GSYNC; tempIface++) + { + if (pThis->i2cHandles[tempIface].gpuId == gpuId) + { + *iface = tempIface; + rmStatus = NV_OK; + } + } + + return rmStatus; +} + +static NV_STATUS +gsyncFindFreeHandleLocation +( + DACP2060EXTERNALDEVICE *pThis, + NvU32 *iface +) +{ + NvU32 tempIface; + NV_STATUS rmStatus = NV_ERR_GENERIC; + + for (tempIface = 0; tempIface < NV_P2060_MAX_IFACES_PER_GSYNC; tempIface++) + { + if (pThis->i2cHandles[tempIface].gpuId == 0) + { + *iface = tempIface; + rmStatus = NV_OK; + } + } + + return rmStatus; +} + +NvBool +extdevSaveI2cHandles_P2060 +( + OBJGPU *pGpu, + DACEXTERNALDEVICE *pExternalDevice +) +{ + DACP2060EXTERNALDEVICE *pThis = (PDACP2060EXTERNALDEVICE)pExternalDevice; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NvHandle hClient; + NvHandle hDevice; + NvHandle hSubdevice; + NvHandle hSubscription = NV01_NULL_OBJECT; + NvU32 iface; + NV_STATUS rmStatus; + + rmStatus = gsyncFindFreeHandleLocation(pThis, &iface); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Maximum number of GPUs have been attached\n"); + return NV_FALSE; + } + + rmStatus = rmapiutilAllocClientAndDeviceHandles(pRmApi, + pGpu, &hClient, &hDevice, &hSubdevice); + NV_ASSERT_OR_RETURN(rmStatus == NV_OK, NV_FALSE); + + rmStatus = pRmApi->Alloc(pRmApi, hClient, hSubdevice, + &hSubscription, NV40_I2C, NULL); + + NV_ASSERT_OR_RETURN(rmStatus == NV_OK, NV_FALSE); + + pThis->i2cHandles[iface].hClient = hClient; + pThis->i2cHandles[iface].hDevice = hDevice; + pThis->i2cHandles[iface].hSubdevice = hSubdevice; + pThis->i2cHandles[iface].hSubscription = hSubscription; + pThis->i2cHandles[iface].gpuId = pGpu->gpuId; + + return NV_TRUE; +} + +NV_STATUS +i2c_extdeviceHelper +( + OBJGPU *pGpu, + DACEXTERNALDEVICE *pExternalDevice, + NvU32 i2cPort, + NvU8 SubAdr, + NvU8 *pData, + NvBool write +) +{ + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + DACP2060EXTERNALDEVICE *pThis = (PDACP2060EXTERNALDEVICE)pExternalDevice; + NV_STATUS status = NV_ERR_GENERIC; + NvU32 iface; + NV402C_CTRL_I2C_TRANSACTION_PARAMS *pParams; + + pParams = portMemAllocNonPaged(sizeof(*pParams)); + if (pParams == NULL) + { + return NV_ERR_NO_MEMORY; + } + + status = gsyncFindGpuHandleLocation(pExternalDevice, pGpu->gpuId, &iface); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Couldn't find saved GPU entry, check saved i2chandles. \n"); + return status; + } + + portMemSet(pParams, 0, sizeof(*pParams)); + + pParams->portId = (NvU8)i2cPort; + pParams->transType = NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW; + pParams->deviceAddress = (NvU16)pExternalDevice->I2CAddr; + + pParams->transData.smbusByteData.bWrite = write; + pParams->transData.smbusByteData.registerAddress = SubAdr; + if (write) + { + pParams->transData.smbusByteData.message = *pData; + } + + status = pRmApi->Control(pRmApi, pThis->i2cHandles[iface].hClient, + pThis->i2cHandles[iface].hSubscription, + NV402C_CTRL_CMD_I2C_TRANSACTION, + pParams, sizeof(*pParams)); + + if (!write) + { + *pData = pParams->transData.smbusByteData.message; + } + + portMemFree(pParams); + + return status; +} + +/* + * Initialize P2060 for all GPUs in loop. + */ +NvBool +extdevInit_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExternalDevice +) +{ + OBJGPU *pGpuTemp; + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNC *pGsyncTemp = NULL; + NvU32 gpuAttachCnt, gpuAttachMask, gpuInstance; + NvU32 data; + + if (!GpuIsP2060Connected(pGpu, (PDACP2060EXTERNALDEVICE)pExternalDevice)) + { + return NV_FALSE; + } + + if (NV_OK != gsyncProgramExtStereoPolarity_P2060(pGpu, pExternalDevice)) + { + return NV_FALSE; + } + + // Check regkeys + if (NV_OK == osReadRegistryDword(pGpu, NV_REG_STR_RM_QSYNC_FW_REV_CHECK, &data)) + { + if (NV_REG_STR_RM_QSYNC_FW_REV_CHECK_DISABLE == data) + { + pSys->setProperty(pSys, PDB_PROP_SYS_IS_QSYNC_FW_REVISION_CHECK_DISABLED, NV_TRUE); + } + } + + // Initialize SyncPolarity to FALLING_EDGE. Refer Bug 1035880 + if (NV_OK != gsyncSetSyncPolarity_P2060(pGpu, pExternalDevice, gsync_SyncPolarity_FallingEdge)) + { + return NV_FALSE; + } + + // get count of all other gpus in the system + gpumgrGetGpuAttachInfo(&gpuAttachCnt, &gpuAttachMask); + + // loop over + gpuInstance = 0; + while ((pGpuTemp = gpumgrGetNextGpu(gpuAttachMask, &gpuInstance)) != NULL) + { + pGsyncTemp = gsyncmgrGetGsync(pGpuTemp); + + if (!pGsyncTemp || !pGsyncTemp->pExtDev) + continue; + + _externalDeviceInit_P2060(pGpuTemp, (pGpu == pGpuTemp)); + } + + return NV_TRUE; +} + +static NV_STATUS +gsyncReadBoardId_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExternalDevice, + NvU32 *uniqueId +) +{ + NvU8 i, id = 0; + NV_STATUS rmStatus = NV_OK; + + *uniqueId = 0; + for (i = 0; i < 4; i++) + { + rmStatus = readregu008_extdeviceTargeted(pGpu, pExternalDevice, + NV_P2060_FPGA_ASGN_ID(i), &id); + if (rmStatus != NV_OK) + { + return rmStatus; + } + *uniqueId |= id << (i * 8); + } + return NV_OK; +} + +/* + * Attach P2060 to GPU on correct connector index. + */ +NvBool +gsyncAttachExternalDevice_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE *ppExtdevs +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync = NULL; + OBJGPU *pOtherGpu = NULL; + DACP2060EXTERNALDEVICE *pThis, *pExt2060Temp; + NvU8 i, id = 0, regCtrl2 = 0; + NvU32 iface, connector, uniqueId = 0, pOtherGpuId = 0, bSkipResetForVM = 0, index = 0; + NvU32 tempIface; + NvBool bExtDevFound = NV_FALSE; + NV_STATUS rmStatus = NV_OK; + NvU8 ctrl = 0; + + rmStatus = gsyncReadBoardId_P2060(pGpu, *ppExtdevs, &uniqueId); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "failed to read P2060 device Id.\n"); + return NV_FALSE; + } + + if (uniqueId != 0x0) + { + // HW says another GPU has been here first. Confirm this from SW. + for (i = 0; i < NV30F1_MAX_GSYNCS; i++) + { + if (pGsyncMgr->gsyncTable[i].gpuCount) + { + pGsync = &pGsyncMgr->gsyncTable[i]; + if (pGsync->pExtDev) + { + pThis = (PDACP2060EXTERNALDEVICE) pGsync->pExtDev; + if (pThis->id == uniqueId) + { + pOtherGpuId = pGsync->gpus[0].gpuId; + bExtDevFound = NV_TRUE; + } + } + } + + if (bExtDevFound) + { + break; + } + } + + if (!bExtDevFound) + { + if ((IS_PASSTHRU(pGpu))) + { + // look for master board + rmStatus = readregu008_extdeviceTargeted(pGpu, *ppExtdevs, + (NvU8)NV_P2060_CONTROL, &ctrl); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to read Ctrl data.\n"); + return NV_FALSE; + } + + pThis = (PDACP2060EXTERNALDEVICE)*ppExtdevs; + bSkipResetForVM = FLD_TEST_DRF(_P2060, _CONTROL, _I_AM, _MASTER, (NvU32)ctrl); + rmStatus = GetP2060ConnectorIndexFromGpu(pGpu, pThis, &index); + + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to get connector index for Gpu.\n"); + return NV_FALSE; + } + + // Look for SYNC source gpu. + bSkipResetForVM = bSkipResetForVM && !(DRF_VAL(_P2060, _CONTROL, _SYNC_SRC, (NvU32)ctrl) == index); + } + + if (!bSkipResetForVM) + { + // ExtDev is not preset in pGsyncMgr. Issue RESET to P2060 HW. + regCtrl2 = FLD_SET_DRF_NUM(_P2060, _CONTROL2, _RESET, NV_TRUE, regCtrl2); + writeregu008_extdeviceTargeted(pGpu, *ppExtdevs, + NV_P2060_CONTROL2, regCtrl2); + + osDelay(5); // Add delay of 5ms before I2C read as board is in reset phase. + + rmStatus = gsyncReadBoardId_P2060(pGpu, *ppExtdevs, &uniqueId); + if ((rmStatus != NV_OK) || (uniqueId != 0)) + { + NV_PRINTF(LEVEL_ERROR, + "failed to read P2060 device Id after reset.\n"); + return NV_FALSE; + } + } + } + else + { + pOtherGpu = gpumgrGetGpuFromId(pOtherGpuId); + pGsync = gsyncmgrGetGsync(pOtherGpu); + + if (!pGsync || !pGsync->pExtDev) + { + NV_ASSERT(0); + return NV_FALSE; + } + + NV_ASSERT(pGsync->pExtDev != *ppExtdevs); + + pThis = (PDACP2060EXTERNALDEVICE)*ppExtdevs; + pExt2060Temp = (PDACP2060EXTERNALDEVICE)(pGsync->pExtDev); + + rmStatus = gsyncFindFreeHandleLocation(pExt2060Temp, &iface); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to free index for new GPU entry. \n"); + return NV_FALSE; + } + + rmStatus = gsyncFindGpuHandleLocation(*ppExtdevs, pGpu->gpuId, &tempIface); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Couldn't find saved GPU entry, check extdevSaveI2cHandles. \n"); + return NV_FALSE; + } + + pExt2060Temp->i2cHandles[iface].gpuId = pThis->i2cHandles[tempIface].gpuId; + pExt2060Temp->i2cHandles[iface].hClient = pThis->i2cHandles[tempIface].hClient; + pExt2060Temp->i2cHandles[iface].hDevice = pThis->i2cHandles[tempIface].hDevice; + pExt2060Temp->i2cHandles[iface].hSubdevice = pThis->i2cHandles[tempIface].hSubdevice; + pExt2060Temp->i2cHandles[iface].hSubscription = pThis->i2cHandles[tempIface].hSubscription; + + pThis->ExternalDevice.pI->Destroy(pGpu, *ppExtdevs); + + // Free our current pointer and replace it + portMemFree(*ppExtdevs); + *ppExtdevs = pGsync->pExtDev; + } + } + + pThis = (PDACP2060EXTERNALDEVICE)*ppExtdevs; + + if (uniqueId == 0x0) + { + // Use pGpu->gpuId as unique value. + uniqueId = pGpu->gpuId; + + for (i = 0; i < 4; i++) + { + id = (NvU8)(uniqueId >> (i * 8)); + rmStatus = writeregu008_extdeviceTargeted(pGpu, *ppExtdevs, + NV_P2060_FPGA_ASGN_ID(i), + id); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "failed to update P2060 device Id.\n"); + return NV_FALSE; + } + } + pThis->id = uniqueId; + } + + rmStatus = GetP2060ConnectorIndexFromGpu(pGpu, pThis, &iface); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "failed to find P2060 connector.\n"); + return NV_FALSE; + } + + // + // Add 1 to index we got from status2 register read beacuse connector + // NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_ONE start with value 1. + // + connector = iface + 1; + + // + // If adding a check before the gsyncAttachGpu call and returning before + // that please add the following code: + // pThis->gpuAttachMask &= ~NVBIT(pGpu->gpuInstance); + // (*ppExtdevs)->ReferenceCount--; + // before returning NV_FALSE so that the caller can destroy the + // ext device structure. The destroy funciton only decrements the ref count + // if the gpu has already been attached. + // + (*ppExtdevs)->ReferenceCount++; + pThis->gpuAttachMask |= NVBIT(pGpu->gpuInstance); + + pThis->Iface[iface].GpuInfo.gpuId = pGpu->gpuId; + pThis->Iface[iface].GpuInfo.connected = NV_TRUE; + + rmStatus = gsyncAttachGpu(*ppExtdevs, pGpu, connector, NULL, (*ppExtdevs)->deviceId); + + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "failed to attach P2060 gsync to gpu.\n"); + return NV_FALSE; + } + + if (pThis->ExternalDevice.deviceId == DAC_EXTERNAL_DEVICE_P2061) + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_QSYNC_II_ATTACHED, NV_TRUE); + } + else + { + NV_ASSERT(pThis->ExternalDevice.deviceId == DAC_EXTERNAL_DEVICE_P2060); + pGpu->setProperty(pGpu, PDB_PROP_GPU_GSYNC_III_ATTACHED, NV_TRUE); + } + + if (!pThis->isNonFramelockInterruptEnabled) + { + rmStatus = gsyncEnableNonFramelockInterrupt_P2060(pGpu, *ppExtdevs); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to enable non-framelock interrupts on gsync GPU.\n"); + return NV_FALSE; + } + pThis->isNonFramelockInterruptEnabled = NV_TRUE; + pThis->interruptEnabledInterface = iface; + } + + return NV_TRUE; +} + +/* + * Destroy the device P2060. + */ +void +extdevDestroy_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExternalDevice +) +{ + DACP2060EXTERNALDEVICE *pThis = (PDACP2060EXTERNALDEVICE)pExternalDevice; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + NvU32 iface, head; + NvU32 numHeads = kdispGetNumHeads(pKernelDisplay); + NvU8 ctrl2 = 0; + NV_STATUS rmStatus; + + for (iface = 0; iface < NV_P2060_MAX_IFACES_PER_GSYNC; iface++) + { + if (pThis->Iface[iface].GpuInfo.gpuId == pGpu->gpuId) + { + pThis->gpuAttachMask &= ~NVBIT(pGpu->gpuInstance); + pExternalDevice->ReferenceCount--; + + if (pThis->Iface[iface].GpuInfo.connected) + { + if (pExternalDevice->ReferenceCount == 0) + { + // clear id for this gsync device. + pThis->id = 0; + + // reset the gsync hw + ctrl2 = FLD_SET_DRF_NUM(_P2060, _CONTROL2, _RESET, NV_TRUE, ctrl2); + writeregu008_extdeviceTargeted(pGpu, pExternalDevice, + NV_P2060_CONTROL2, ctrl2); + } + } + + // Restore saved swap lockout window values that may not have + // been restored by disabling swap barriers. + if (pThis->Iface[iface].DsiFliplock.saved == NV_TRUE) + { + for (head = 0; head < numHeads; head++) + { + kdispRestoreOriginalLsrMinTime_HAL(pGpu, pKernelDisplay, head, + pThis->Iface[iface].DsiFliplock.OrigLsrMinTime[head]); + } + pThis->Iface[iface].DsiFliplock.saved = NV_FALSE; + } + + gsyncRemoveGpu(pGpu); + + pThis->Iface[iface].GpuInfo.gpuId = NV0000_CTRL_GPU_INVALID_ID; + pThis->Iface[iface].GpuInfo.connected = NV_FALSE; + + pGpu->setProperty(pGpu, PDB_PROP_GPU_GSYNC_III_ATTACHED, NV_FALSE); + pGpu->setProperty(pGpu, PDB_PROP_GPU_QSYNC_II_ATTACHED, NV_FALSE); + + rmStatus = gsyncFindGpuHandleLocation(pExternalDevice, pGpu->gpuId, &iface); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Couldn't find saved GPU entry, check saved i2chandles. \n"); + goto cleanup; + } + + rmapiutilFreeClientAndDeviceHandles(pRmApi, + &pThis->i2cHandles[iface].hClient, + &pThis->i2cHandles[iface].hDevice, + &pThis->i2cHandles[iface].hSubdevice); + + pThis->i2cHandles[iface].hClient = 0; + pThis->i2cHandles[iface].hDevice = 0; + pThis->i2cHandles[iface].hSubdevice = 0; + pThis->i2cHandles[iface].hSubscription = 0; + pThis->i2cHandles[iface].gpuId = 0; + + break; + } + } + +cleanup: + if (pExternalDevice->ReferenceCount == 0) + { + // And continue the chain running. + extdevDestroy_Base(pGpu, pExternalDevice); + } +} + +/* + * Handles the loss/gain of sync and other interrupts. + */ +void +extdevService_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU8 lossRegStatus, + NvU8 gainRegStatus, + NvU8 miscRegStatus, + NvBool rmStatus +) +{ + OBJOS *pOS = GPU_GET_OS(pGpu); + EXTDEV_INTR_DATA intrData; + + if (!rmStatus) + { + return; + } + + intrData.lossRegStatus = lossRegStatus; + intrData.gainRegStatus = gainRegStatus; + intrData.miscRegStatus = miscRegStatus; + intrData.pExtDevice = pExtDev; + + if (IS_GSP_CLIENT(pGpu)) + { + EXTDEV_INTR_DATA *workerThreadData = NULL; + + workerThreadData = portMemAllocNonPaged(sizeof(EXTDEV_INTR_DATA)); + if (NULL != workerThreadData) + { + *workerThreadData = intrData; + } + else + { + NV_PRINTF(LEVEL_ERROR, "Memalloc failed\n"); + } + + // Attempt to queue a work item. + if (NV_OK != pOS->osQueueWorkItemWithFlags(pGpu, + _extdevService, + (void *)workerThreadData, + OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW)) + { + portMemFree((void *)workerThreadData); + } + } + else + { + _extdevService(gpuGetInstance(pGpu), (void *)&intrData); + } +} + +static void +_extdevService +( + NvU32 gpuInstance, + void *workerThreadData +) +{ + OBJGPU *pGpu = gpumgrGetGpu(gpuInstance); + NV_STATUS rmStatus; + + EXTDEV_INTR_DATA intrData = *(EXTDEV_INTR_DATA *)workerThreadData; + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)intrData.pExtDevice; + NvU32 iface, ifaceEvents[NV_P2060_MAX_IFACES_PER_GSYNC]; + + rmStatus = gsyncUpdateGsyncStatusSnapshot_P2060(pGpu, intrData.pExtDevice); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Couldn't raad the register status physical RMs.\n"); + return; + } + rmStatus = GetP2060GpuLocation(pGpu, pThis, &iface); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Cannot get P2060 Gpu location for serving interrupt.\n"); + return; + } + + ifaceEvents[iface] = 0x00; + + if (intrData.lossRegStatus) //lost signal interrupts + { + if (DRF_VAL(_P2060, _STATUS4, _SYNC, (NvU32)intrData.lossRegStatus)) + { + ifaceEvents[iface] |= NVBIT(NV30F1_GSYNC_NOTIFIERS_SYNC_LOSS(iface)); + } + if (DRF_VAL(_P2060, _STATUS4, _STEREO, (NvU32)intrData.lossRegStatus)) + { + ifaceEvents[iface] |= NVBIT(NV30F1_GSYNC_NOTIFIERS_STEREO_LOSS(iface)); + } + if (DRF_VAL(_P2060, _STATUS4, _HS, (NvU32)intrData.lossRegStatus)) + { + ifaceEvents[iface] |= NVBIT(NV30F1_GSYNC_NOTIFIERS_HOUSE_LOSS); + } + if (DRF_VAL(_P2060, _STATUS4, _RJ45, (NvU32)intrData.lossRegStatus)) + { + ifaceEvents[iface] |= NVBIT(NV30F1_GSYNC_NOTIFIERS_RJ45_LOSS); + } + + // + // Enable the watchdog again if we got any loss events. + // Otherise sync gain tracking and stereo sync won't work as desired. + // + if (ifaceEvents[iface]) + { + extdevScheduleWatchdog(pGpu, (PDACEXTERNALDEVICE)pThis); + if (!gsyncIsOnlyFrameLockMaster_P2060(pThis)) + { + pThis->watchdogCountDownValue = NV_P2060_WATCHDOG_COUNT_DOWN_VALUE; + } + } + + if (ifaceEvents[iface] && (pThis->Iface[iface].lastEventNotified != ifaceEvents[iface])) + { + gsyncSignalServiceRequested(gsyncGetGsyncInstance(pGpu), ifaceEvents[iface], iface); + pThis->Iface[iface].lastEventNotified = ifaceEvents[iface]; + } + } + + if (intrData.gainRegStatus) //Gain signal interrupts + { + if (DRF_VAL(_P2060, _STATUS4, _SYNC, (NvU32)intrData.gainRegStatus)) + { + ifaceEvents[iface] |= NVBIT(NV30F1_GSYNC_NOTIFIERS_SYNC_GAIN(iface)); + } + if (DRF_VAL(_P2060, _STATUS4, _STEREO, (NvU32)intrData.gainRegStatus)) + { + ifaceEvents[iface] |= NVBIT(NV30F1_GSYNC_NOTIFIERS_STEREO_GAIN(iface)); + } + if (DRF_VAL(_P2060, _STATUS4, _HS, (NvU32)intrData.gainRegStatus)) + { + ifaceEvents[iface] |= NVBIT(NV30F1_GSYNC_NOTIFIERS_HOUSE_GAIN); + } + if (DRF_VAL(_P2060, _STATUS4, _RJ45, (NvU32)intrData.gainRegStatus)) + { + ifaceEvents[iface] |= NVBIT(NV30F1_GSYNC_NOTIFIERS_RJ45_GAIN); + } + + if (ifaceEvents[iface] && (pThis->Iface[iface].lastEventNotified != ifaceEvents[iface])) + { + gsyncSignalServiceRequested(gsyncGetGsyncInstance(pGpu), ifaceEvents[iface], iface); + pThis->Iface[iface].lastEventNotified = ifaceEvents[iface]; + } + } + + if (intrData.miscRegStatus) //Other interrupts + { + if (FLD_TEST_DRF(_P2060, _STATUS4, _FRM_CNT_MATCH_INT, _PENDING, (NvU32)intrData.miscRegStatus)) + { + // + // To enable frameCountTimerService callback to verify the cached difference 1 second + // after the test signal is received. + // + pThis->FrameCountData.bReCheck = 1; + + // + // Reset framecountData.Therefore whenever user queries after frame compare + // interrupt, gsync and gpu frame count register are read and difference is cached again. + // + // This will also disable frame compare match interrupt, which will be then enabled + // frame compare match interrupt in the next user query or in FrameCountTimerService. + // This is required to clear frmCmpInt bit of status1 register. A read to status1 + // register should clear it, but it is possible that the read to status1 register by + // calling gsyncUpdateGsyncStatusSnapshot_P2060() function above may happen in the same + // frame and this would result interrupt to come back again setting frmCmpint bit. + // + rmStatus |= gsyncResetFrameCountData_P2060(pGpu, pThis); + + if (rmStatus == NV_OK) + { + // + // Set enableFrmCmpMatchInt flag NV_TRUE and return. This indicates + // that the frame compare match interrupt for slave needs to be + // enabled, which is done in the next user query or in + // FrameCountTimerService callback. + // + pThis->FrameCountData.enableFrmCmpMatchIntSlave = NV_TRUE; + } + } + + if (FLD_TEST_DRF(_P2060, _STATUS4, _ERROR_INT, _PENDING, (NvU32)intrData.miscRegStatus)) + { + // Some error condition observed. Update snapshot + rmStatus = gsyncUpdateGsyncStatusSnapshot_P2060(pGpu, intrData.pExtDevice); + if (rmStatus != NV_OK) + { + return; + } + } + } +} + +/* + * waits for hardware to (re-)establish sync. + * once sync obtains, the watchdog enables interrupt, de-sechedules + * itself, and waits for an interrupt to go off before running again. + */ +NV_STATUS +extdevWatchdog_P2060 +( + OBJGPU *pGpu, + OBJTMR *pTmr, + PDACEXTERNALDEVICE pExtDev +) +{ + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; + NvU32 iface, head; + NvBool bStereoLocked; + NV_STATUS rmStatus = NV_OK; + NvBool bStereoEnabled[NV_P2060_MAX_IFACES_PER_GSYNC]; + NvU32 numHeads = kdispGetNumHeads(pKernelDisplay); + + if (pThis->watchdogCountDownValue) + pThis->watchdogCountDownValue--; + + // we now can trust our selection of GPU + pGpu = GetP2060WatchdogGpu(pGpu, pThis); + NV_ASSERT(pGpu); + + // schedule the next callback. we can cancel, if it's not needed. + extdevScheduleWatchdog(pGpu, (PDACEXTERNALDEVICE)pThis); + + rmStatus = gsyncUpdateGsyncStatusSnapshot_P2060(pGpu, pExtDev); + + if (!gsyncIsFrameLocked_P2060(pThis)) + { + gsyncCancelWatchdog_P2060(pThis); + rmStatus = gsyncDisableFrameLockInterrupt_P2060((PDACEXTERNALDEVICE)pThis); + return rmStatus; + } + + for (iface = 0; iface < NV_P2060_MAX_IFACES_PER_GSYNC; iface++) + { + OBJGPU *pTmpGpu = NULL; + if (pThis->Iface[iface].GpuInfo.gpuId == NV0000_CTRL_GPU_INVALID_ID) + { + continue; + } + pTmpGpu = gpumgrGetGpuFromId(pThis->Iface[iface].GpuInfo.gpuId); + + NV_ASSERT(pTmpGpu); + + // figure out if stereo is enabled + bStereoEnabled[iface] = gsyncIsStereoEnabled_p2060(pTmpGpu, pExtDev); + + // loop over the heads of the current gpu on this interface + for ( head = 0; head < numHeads; head++ ) + { + if (pThis->Iface[iface].Sync.Slaved[head] || + pThis->Iface[iface].Sync.LocalSlave[head]) + { + bStereoLocked = FLD_TEST_DRF(_P2060, _STATUS, _STEREO, _LOCK, + (NvU32)pThis->Snapshot[iface].Status1); + + // check for sync and locks, noting that all heads share the status + if ((pThis->Iface[iface].gainedSync) && + (!bStereoEnabled[iface] || bStereoLocked)) + { + break; + } + else + { + return NV_ERR_GENERIC; // hope things are better, on next watchdog run + } + } + } + } + + if ( NV_OK == rmStatus && pKernelDisplay->bExtdevIntrSupported + && !pThis->watchdogCountDownValue) + { + NV_PRINTF(LEVEL_INFO, "P2060[%d] extdevCancelWatchdog.\n", iface); + + // disable the watchdog, + extdevCancelWatchdog(pGpu, (PDACEXTERNALDEVICE)pThis); + + // enable the framelock interrupt, if either Master or Slaves are desired + gsyncEnableFramelockInterrupt_P2060((PDACEXTERNALDEVICE)pThis); + } + + return NV_OK; +} + +static NV_STATUS +gsyncApplyStereoPinAlwaysHiWar +( + POBJGPU pGpu, + PDACEXTERNALDEVICE pExtDev +) +{ + + return NV_OK; + +} + +static NV_STATUS +gsyncUnApplyStereoPinAlwaysHiWar +( + POBJGPU pGpu +) +{ + + return NV_OK; + +} + +// +// gsyncReadUniversalFrameCount_P2060() +// +// When user queries for the first time or after 10 seconds, Gsync and Gpu +// hardware framecount are read and then the difference between them is cached. +// For rest of the instances whenever user queries for frame count, gpu +// frame count is read, and software framecount is updated accordingly based +// on previous cached values. +// +static NV_STATUS +gsyncReadUniversalFrameCount_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 *pFrameCount +) +{ + OBJGPU *pTmpGpu = NULL; + KernelDisplay *pKernelDisplay = NULL; + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE) pExtDev; + NV_STATUS rmStatus = NV_OK; + NvU32 lineCount; + NvU32 frameCount; + NvS32 calculatedDiff; + NvU64 currentTime = 0; + NvU64 queryTimeDiff; + OBJTMR *pTmpTmr = NULL; + OBJTMR *pTmr = GPU_GET_TIMER(pGpu); + + if (!(pThis->FrameCountData.iface == NV_P2060_MAX_IFACES_PER_GSYNC)) + { + // + // pThis->FrameCountData.iface exists. + // Thus deriving pTmpGpu from it, and to maintain consistency reading the time from it. + // + pTmpGpu = gpumgrGetGpuFromId(pThis->Iface[pThis->FrameCountData.iface].GpuInfo.gpuId); + + if (pTmpGpu) + { + pTmpTmr = GPU_GET_TIMER(pTmpGpu); + currentTime = tmrGetTime_HAL(pTmpGpu, pTmpTmr); + } + } + + if (currentTime == 0) + { + // pTmpGpu doesn't exists, so getting the time from pGpu. + currentTime = tmrGetTime_HAL(pGpu, pTmr); + } + + if (NV_P2060_STATUS_SYNC_LOSS_TRUE == DRF_VAL(_P2060, _STATUS, _SYNC_LOSS, GetP2060GpuSnapshot(pGpu,pThis))) + { + // don't increment the frame counter in case of sync loss + *pFrameCount = pThis->FrameCountData.totalFrameCount; + pThis->FrameCountData.lastFrameCounterQueryTime = currentTime; + + return NV_OK; + } + + queryTimeDiff = currentTime - pThis->FrameCountData.lastFrameCounterQueryTime; + + // + // If user queries for the first time or after 10 secs then read gsync and + // gpu frame count registers and update software frame count and cached + //difference. Also enable the frmCmpMatchInt if not enabled. + // + if ((!pThis->FrameCountData.lastFrameCounterQueryTime) || + (queryTimeDiff > 2 * NV_P2060_FRAME_COUNT_TIMER_INTERVAL)) + { + // + // P2060 refreshrate is in 0.00001 Hz, so divide by 10000 to get Hz. + // divide 1000000 by refreshRate to get the frame time in us. + // + pThis->FrameCountData.frameTime = 1000000 / (pThis->RefreshRate/10000); //in us + + // + // Enable FrameCountTimerService to verify FrameCountData.initialDifference. + // + pThis->FrameCountData.bReCheck = 1; + + rmStatus = gsyncUpdateFrameCount_P2060(pThis, pGpu); + *pFrameCount = pThis->FrameCountData.totalFrameCount; + + // enable frame count match interrupt if not master + if (!gsyncIsFrameLockMaster_P2060(pThis)) + { + NvU8 regCtrl3; + + // set frame count match value 1 + rmStatus |= writeregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE)pThis, + (NvU8)NV_P2060_FRAME_CMPR_LOW, 0x1); + rmStatus |= writeregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE)pThis, + (NvU8)NV_P2060_FRAME_CMPR_MID, 0x0); + rmStatus |= writeregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE)pThis, + (NvU8)NV_P2060_FRAME_CMPR_HIGH, 0x0); + + // + // Enable frame count match interrupt for the first time. For rest of the + // instances when, TEST_SIGNAL is received, interrupt is enable in + // gsyncUpdateFrameCount_P2060() based on enableFrmCmpMatchIntSlave bit. + // + rmStatus |= readregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE)pThis, + NV_P2060_CONTROL3, ®Ctrl3); + + if (rmStatus == NV_OK) + { + regCtrl3 |= DRF_DEF(_P2060, _CONTROL3, _INTERRUPT, _ON_FRAME_MATCH); + rmStatus = writeregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE)pThis, + NV_P2060_CONTROL3, regCtrl3); + } + } + + if (rmStatus != NV_OK) + { + rmStatus |= gsyncResetFrameCountData_P2060(pGpu, pThis); + return rmStatus; + } + + pThis->FrameCountData.lastFrameCounterQueryTime = currentTime; + } + + // Update software framecount throught gpu frame count register. + else + { + // + // To avoid any inconsistency, linecount and framecount should always + // be read from one specific Gpu head. Its value is stored in pThis->FrameCountData. + // + NV_ASSERT_OR_RETURN(pTmpGpu, NV_ERR_INVALID_DEVICE); + + pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pTmpGpu); + + // Read the GPU frame count and line count + rmStatus = kdispReadRgLineCountAndFrameCount_HAL(pTmpGpu, pKernelDisplay, + pThis->FrameCountData.head, &lineCount, &frameCount); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to read RG_DPCA.\n"); + return rmStatus; + } + + // + // Check to ensure previousFrameCount != currentGpuFrmCnt. If this is not ensured, + // it is possible to miss rollover condition. + // + if (pThis->FrameCountData.currentFrameCount != frameCount) + { + pThis->FrameCountData.previousFrameCount = pThis->FrameCountData.currentFrameCount; + pThis->FrameCountData.currentFrameCount = frameCount; + + // If rollback for gpu framecount has occured. + if (pThis->FrameCountData.previousFrameCount > pThis->FrameCountData.currentFrameCount) + { + pThis->FrameCountData.numberOfRollbacks++; + } + } + + calculatedDiff = pThis->FrameCountData.initialDifference + + pThis->FrameCountData.numberOfRollbacks * (NV_P2060_MAX_GPU_FRAME_COUNT + 1); + + pThis->FrameCountData.totalFrameCount = pThis->FrameCountData.currentFrameCount + + calculatedDiff; + + // + // To keep sync between the sw framecount and gsync framecount. + // + // Gpu framecount increments after VTotal scanout lines whereas Gsync + // increments after VActive scanout lines. Thus it is necessary to + // mitigate this difference of 1 when linecount > VActive. + // + if (lineCount > pThis->FrameCountData.vActive) + { + pThis->FrameCountData.totalFrameCount++; + } + + *pFrameCount = pThis->FrameCountData.totalFrameCount; + + pThis->FrameCountData.lastFrameCounterQueryTime = currentTime; + } + + // + // Enable the frame compare match interrupt in master gsync, to detect if + // rollover has occured. So that gsync and gpu frame count can be cached + // again and difference between them is verified. + // + if ((!pThis->FrameCountData.isFrmCmpMatchIntMasterEnabled) && + (pThis->FrameCountData.totalFrameCount > (NV_P2060_MAX_GSYNC_FRAME_COUNT - 1000))) + { + if (gsyncIsOnlyFrameLockMaster_P2060(pThis)) + { + NvU8 regCtrl3; + + // enable frame count match interrupt + rmStatus = readregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE)pThis, NV_P2060_CONTROL3, ®Ctrl3); + + regCtrl3 |= DRF_DEF(_P2060, _CONTROL3, _INTERRUPT, _ON_FRAME_MATCH); + rmStatus |= writeregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE)pThis, NV_P2060_CONTROL3, regCtrl3); + + pThis->FrameCountData.isFrmCmpMatchIntMasterEnabled = NV_TRUE; + + if (rmStatus != NV_OK) + { + rmStatus |= gsyncResetFrameCountData_P2060(pGpu, pThis); + } + } + } + return rmStatus; +} + +/* + * Read Frame Rate register and calculate Framerate. + */ +static NV_STATUS +gsyncReadFrameRate_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 *pFrameRate +) +{ + NvU8 FrameCountLow, FrameCountMid, FrameCountHigh; + NvU32 FrameCount; + NV_STATUS rmStatus = NV_OK; + + rmStatus |= readregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_FRAMERATE_LOW, &FrameCountLow); + rmStatus |= readregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_FRAMERATE_MID, &FrameCountMid); + rmStatus |= readregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_FRAMERATE_HIGH, &FrameCountHigh); + + if ( NV_OK == rmStatus ) + { + NvU32 divisor; + + FrameCount = ( ( (((NvU32)FrameCountHigh) & DRF_MASK(NV_P2060_FRAMERATE_HIGH_VAL)) << 16 ) | + ( (((NvU32)FrameCountMid) & DRF_MASK(NV_P2060_FRAMERATE_MID_VAL )) << 8 ) | + ( (((NvU32)FrameCountLow) & DRF_MASK(NV_P2060_FRAMERATE_LOW_VAL )) ) ); + + divisor = FrameCount + 2; // FPGA divider is 1 + *pFrameRate = FrameCount ? OVERFLOW_CAREFUL_MUL_DIV(160000000, 2048, divisor) : 0; + *pFrameRate += 5; // take back one kadam, to honor the Extdev god, + *pFrameRate -= *pFrameRate % 10; // whose GSync board this is... + } + return rmStatus; +} + +/* + * Read House Sync Frame Rate register and calculate Framerate. + */ +static NV_STATUS +gsyncReadHouseSyncFrameRate_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 *pFrameRate +) +{ + NvU8 FrameCountLow, FrameCountMid, FrameCountHigh; + NvU32 FrameCount; + NV_STATUS rmStatus = NV_OK; + + rmStatus |= readregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_HS_FRAMERATE_LOW, &FrameCountLow); + rmStatus |= readregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_HS_FRAMERATE_MID, &FrameCountMid); + rmStatus |= readregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_HS_FRAMERATE_HIGH, &FrameCountHigh); + + if ( NV_OK == rmStatus ) + { + NvU32 divisor; + + FrameCount = ( ( (((NvU32)FrameCountHigh) & DRF_MASK(NV_P2060_HS_FRAMERATE_HIGH_VAL)) << 16 ) | + ( (((NvU32)FrameCountMid) & DRF_MASK(NV_P2060_HS_FRAMERATE_MID_VAL )) << 8 ) | + ( (((NvU32)FrameCountLow) & DRF_MASK(NV_P2060_HS_FRAMERATE_LOW_VAL )) ) ); + + divisor = FrameCount + 2; // FPGA divider is 1 + *pFrameRate = FrameCount ? OVERFLOW_CAREFUL_MUL_DIV(160000000, 2048, divisor) : 0; + *pFrameRate += 5; // take back one kadam, to honor the Extdev god, + *pFrameRate -= *pFrameRate % 10; // whose GSync board this is... + } + return rmStatus; +} + +NV_STATUS +gsyncOptimizeTimingParameters_P2060 +( + OBJGPU *pGpu, + GSYNCTIMINGPARAMS *pParams +) +{ + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NvU32 hClient = pGpu->hInternalClient; + NvU32 hSubdevice = pGpu->hInternalSubdevice; + NV_STATUS status = NV_OK; + NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS ctrlParams = {0}; + + ctrlParams.timingParameters = *pParams; + + status = pRmApi->Control(pRmApi, hClient, hSubdevice, + NV2080_CTRL_CMD_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS, + &ctrlParams, sizeof(ctrlParams)); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "OptimizeTimingParameters control call has failed! \n"); + } + else + { + *pParams = ctrlParams.timingParameters; + } + + return status; +} + +/* + * Program External Stereo Polarity to High side of master stereo + */ +static NV_STATUS +gsyncProgramExtStereoPolarity_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExternalDevice +) +{ + NV_STATUS rmStatus = NV_OK; + NvU8 ctrl4 = 0x00; + + rmStatus = readregu008_extdeviceTargeted(pGpu, pExternalDevice, + NV_P2060_CONTROL4, &ctrl4); + if (rmStatus != NV_OK) + { + return rmStatus; + } + + // This bit controls stereo polarity relative to an external sync. + ctrl4 = (NvU8) FLD_SET_DRF(_P2060, _CONTROL4, _EXT_STEREO_SYNC_POL, _HI, (NvU32)ctrl4); + + rmStatus = writeregu008_extdeviceTargeted(pGpu, pExternalDevice, + NV_P2060_CONTROL4, ctrl4); + return rmStatus; +} + +NV_STATUS +gsyncSetStereoLockMode_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 enable +) +{ + NvU8 ctrl4; + NV_STATUS rmStatus; + + rmStatus = readregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_CONTROL4, &ctrl4); + + if (rmStatus != NV_OK) + { + return rmStatus; + } + + if (enable) + { + ctrl4 = FLD_SET_DRF(_P2060, _CONTROL4, _STEREO_LOCK_MODE, _ON, ctrl4); + } + else + { + ctrl4 = FLD_SET_DRF(_P2060, _CONTROL4, _STEREO_LOCK_MODE, _OFF, ctrl4); + } + + rmStatus = writeregu008_extdeviceTargeted(pGpu, pExtDev, NV_P2060_CONTROL4, ctrl4); + + return rmStatus; +} + +NV_STATUS +gsyncGetStereoLockMode_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 *enable +) +{ + NvU8 ctrl4; + NV_STATUS rmStatus; + + rmStatus = readregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_CONTROL4, &ctrl4); + + if (NV_OK == rmStatus) + { + *enable = FLD_TEST_DRF(_P2060, _CONTROL4, _STEREO_LOCK_MODE, _ON, ctrl4); + } + + return rmStatus; +} + +NV_STATUS +gsyncSetVideoMode_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + GSYNCVIDEOMODE VideoMode +) +{ + return NV_OK; +} + +NV_STATUS +gsyncGetVideoMode_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + GSYNCVIDEOMODE *pVideoMode +) +{ + NvU8 videoMode; + NV_STATUS rmStatus; + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; + + NV_ASSERT_OR_RETURN(pGpu, NV_ERR_GENERIC); + + rmStatus = readregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_STATUS2, &videoMode); + + if ( NV_OK == rmStatus ) + { + *pVideoMode = DRF_VAL(_P2060, _STATUS2, _HS_DETECT, videoMode); + if (*pVideoMode == 0x02) + { + // reported videoMode is composite. Convert it to RMAPI exported value. + *pVideoMode = gsync_VideoMode_COMPOSITE; + } + } + + // update p2060 object + pThis->VideoMode = *pVideoMode; + + return rmStatus; +} + +NV_STATUS +gsyncSetEmitTestSignal_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 bEmitTestSignal +) +{ + NvU8 ctrl; + NV_STATUS rmStatus; + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; + + // update p2060 object + pThis->EmitTestSignal = bEmitTestSignal; + + if (!gsyncIsFrameLockMaster_P2060(pThis)) + { + return NV_ERR_INVALID_DEVICE; + } + + pGpu = GetP2060MasterableGpu(pGpu, (PDACP2060EXTERNALDEVICE)pExtDev); + NV_ASSERT_OR_RETURN(pGpu, NV_ERR_GENERIC); + + rmStatus = readregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_CONTROL, &ctrl); + + if ( bEmitTestSignal ) + { + ctrl = FLD_SET_DRF(_P2060, _CONTROL, _TEST_MODE, _ON, ctrl); + } + else + { + ctrl = FLD_SET_DRF(_P2060, _CONTROL, _TEST_MODE, _OFF, ctrl); + + // + // To enable frameCountTimerService callback which verifies + // the cache difference 1 second after sending the test signal + // + pThis->FrameCountData.bReCheck = 1; + + // + // Reset framecountData.Therefore whenever user queries after TEST_MODE_OFF, + // gsync and gpu frame count register are read and difference is cached again. + // + rmStatus |= gsyncResetFrameCountData_P2060(pGpu, pThis); + } + + rmStatus |= writeregu008_extdeviceTargeted(pGpu, pExtDev, NV_P2060_CONTROL, ctrl); + + // + // Add some OS delay between test mode transitions. This is also + // necessary for proper propogation of test signal to other slaves. + // + { + NvU32 refreshTime = 0; + // + // The test mode detection logic will return the previous value until the + // next frame. Although only the master will only manipulate test mode, + // we may transition to slave while test mode is still on due to this. + // So delay for a couple of frames to make sure the value transitions + // correctly. Fix for bug #82809, back in the day. + // + // P2060 refreshrate is in 0.00001 Hz, so divide by 10000 to get Hz. + // + if ((pThis->RefreshRate/10000) > 0) + { + refreshTime = 1000 / (pThis->RefreshRate/10000); + } + NV_ASSERT(refreshTime != 0); + + // Only wait a maximum amount of time. + refreshTime = NV_MIN(refreshTime, 35); + osDelay(2*refreshTime /* ms */); + } + + return rmStatus; +} + +NV_STATUS +gsyncGetEmitTestSignal_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 *pVal +) +{ + NvU8 ctrl; + NV_STATUS rmStatus; + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; + + rmStatus = readregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_CONTROL, &ctrl); + + if ( NV_OK == rmStatus ) + { + *pVal = FLD_TEST_DRF(_P2060, _CONTROL, _TEST_MODE, _ON, ctrl); + } + + // update p2060 object + pThis->EmitTestSignal = *pVal; + + return rmStatus; +} + +NV_STATUS +gsyncSetInterlaceMode_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 InterlaceMode +) +{ + NvU8 ctrl; + NV_STATUS rmStatus; + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; + + // update p2060 object + pThis->InterlaceMode = InterlaceMode; + + pGpu = GetP2060MasterableGpu(pGpu, (PDACP2060EXTERNALDEVICE)pExtDev); + NV_ASSERT_OR_RETURN(pGpu, NV_ERR_GENERIC); + + rmStatus = readregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_CONTROL, &ctrl); + + if ( rmStatus == NV_OK ) + { + ctrl = FLD_SET_DRF_NUM(_P2060, _CONTROL, _INTERLACE_MODE, (NvU8)InterlaceMode, ctrl); + rmStatus = writeregu008_extdeviceTargeted(pGpu, pExtDev, NV_P2060_CONTROL, ctrl); + } + + return rmStatus; +} + +NV_STATUS +gsyncGetInterlaceMode_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 *pVal +) +{ + NvU8 ctrl; + NV_STATUS rmStatus; + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; + + pGpu = GetP2060MasterableGpu(pGpu, (PDACP2060EXTERNALDEVICE)pExtDev); + NV_ASSERT_OR_RETURN(pGpu, NV_ERR_GENERIC); + + rmStatus = readregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_CONTROL, &ctrl); + + if ( NV_OK == rmStatus ) + { + *pVal = FLD_TEST_DRF(_P2060, _CONTROL, _INTERLACE_MODE, _TRUE, ctrl); + } + + // update p2060 object + pThis->InterlaceMode = *pVal; + + return rmStatus; +} + +NV_STATUS +gsyncSetUseHouse_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 UseHouseSync +) +{ + NvU8 ctrl; + NV_STATUS rmStatus = NV_OK; + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; + + // update p2060 object + pThis->UseHouseSync = UseHouseSync; + + pGpu = GetP2060MasterableGpu(pGpu, (PDACP2060EXTERNALDEVICE)pExtDev); + NV_ASSERT_OR_RETURN(pGpu, NV_ERR_GENERIC); + + rmStatus = readregu008_extdeviceTargeted(pGpu, pExtDev, NV_P2060_CONTROL, &ctrl); + + if (NV_OK == rmStatus) + { + ctrl = FLD_SET_DRF_NUM(_P2060, _CONTROL, _SYNC_SELECT, (NvU8)UseHouseSync, ctrl); + rmStatus = writeregu008_extdeviceTargeted(pGpu, pExtDev, NV_P2060_CONTROL, ctrl); + } + + return rmStatus; +} + +NV_STATUS +gsyncGetUseHouse_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 *val +) +{ + NvU8 ctrl; + NV_STATUS rmStatus = NV_OK; + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; + + rmStatus = readregu008_extdeviceTargeted(pGpu, pExtDev, NV_P2060_CONTROL, &ctrl); + + if (NV_OK == rmStatus) + { + *val = FLD_TEST_DRF(_P2060, _CONTROL, _SYNC_SELECT, _HOUSE, ctrl); + + // update p2060 object + pThis->UseHouseSync = *val; + } + + return rmStatus; +} + +NV_STATUS +gsyncSetSyncPolarity_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + GSYNCSYNCPOLARITY SyncPolarity +) +{ + NvU8 ctrl; + NV_STATUS rmStatus; + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; + GSYNCSYNCPOLARITY currentSyncPolarity; + + // update p2060 object + pThis->SyncPolarity = SyncPolarity; + + pGpu = GetP2060MasterableGpu(pGpu, (PDACP2060EXTERNALDEVICE)pExtDev); + NV_ASSERT_OR_RETURN(pGpu, NV_ERR_GENERIC); + + rmStatus = readregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_CONTROL, &ctrl); + + if ( NV_OK == rmStatus ) + { + currentSyncPolarity = DRF_VAL(_P2060, _CONTROL, _SYNC_POLARITY, ctrl); + + if (currentSyncPolarity != SyncPolarity) + { + NvU32 frameTime = 0; + + ctrl = FLD_SET_DRF_NUM(_P2060, _CONTROL, _SYNC_POLARITY, (NvU8)SyncPolarity, ctrl); + rmStatus = writeregu008_extdeviceTargeted(pGpu, pExtDev, NV_P2060_CONTROL, ctrl); + + if ((pThis->RefreshRate/10000) > 0) + { + frameTime = 1000 / (pThis->RefreshRate/10000); + } + + // + // Wait for max of 10 frames or 100 ms so that hardware can collect + // the new house sync frame rate. + // + frameTime = NV_MAX(frameTime, 10); + osDelay(10 * frameTime /* ms */); + } + } + + return rmStatus; +} + +NV_STATUS +gsyncGetSyncPolarity_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + GSYNCSYNCPOLARITY *pSyncPolarity +) +{ + NvU8 ctrl; + NV_STATUS rmStatus; + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; + + rmStatus = readregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_CONTROL, &ctrl); + + if ( NV_OK == rmStatus ) + { + *pSyncPolarity = DRF_VAL(_P2060, _CONTROL, _SYNC_POLARITY, ctrl); + } + + // update p2060 object + pThis->SyncPolarity = *pSyncPolarity; + + return rmStatus; +} + +NV_STATUS +gsyncSetNSync_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 NSync +) +{ + NvU8 regNSync; + NV_STATUS rmStatus; + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; + + // update p2060 object + pThis->NSync = NSync; + + rmStatus = readregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_NSYNC, ®NSync); + + if ( NV_OK == rmStatus ) + { + regNSync = FLD_SET_DRF_NUM(_P2060, _NSYNC, _FL, (NvU8)NSync, regNSync); + rmStatus = writeregu008_extdeviceTargeted(pGpu, pExtDev, NV_P2060_NSYNC, regNSync); + } + + return rmStatus; +} + +NV_STATUS +gsyncGetNSync_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 *pNSync +) +{ + NvU8 regNSync; + NV_STATUS rmStatus; + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; + + rmStatus = readregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_NSYNC, ®NSync); + + if ( NV_OK == rmStatus ) + { + *pNSync = DRF_VAL(_P2060, _NSYNC, _FL, regNSync); + } + + // update p2060 object + pThis->NSync = *pNSync; + + return rmStatus; +} + +NV_STATUS +gsyncSetSyncSkew_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 SyncSkew +) +{ + NvU8 SyncSkewLow, SyncSkewHigh; + NV_STATUS rmStatus = NV_OK; + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; + + // update p2060 object + pThis->SyncSkew = SyncSkew; + + if (supportsLargeSyncSkew(pExtDev)) + { + SyncSkewLow = (NvU8)((SyncSkew ) & DRF_MASK(NV_P2060_SYNC_SKEW_LOW_VAL )); + SyncSkewHigh = (NvU8)((SyncSkew >> 8) & DRF_MASK(NV_P2060_SYNC_SKEW_HIGH_VAL)); + } + else + { + if ((SyncSkew != 0) && (SyncSkew != 1)) + { + return NV_ERR_NOT_SUPPORTED; + } + else + { + SyncSkewLow = (NvU8)SyncSkew; + SyncSkewHigh = 0x00; + } + } + + rmStatus |= writeregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_SYNC_SKEW_LOW, SyncSkewLow); + rmStatus |= writeregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_SYNC_SKEW_HIGH, SyncSkewHigh); + + return rmStatus; + +} + +NV_STATUS +gsyncGetSyncSkew_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 *pSyncSkew +) +{ + NvU8 SyncSkewLow, SyncSkewHigh; + NV_STATUS rmStatus = NV_OK; + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; + + rmStatus |= readregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_SYNC_SKEW_LOW, &SyncSkewLow); + rmStatus |= readregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_SYNC_SKEW_HIGH, &SyncSkewHigh); + + if ( NV_OK == rmStatus ) + { + *pSyncSkew = + ( ((((NvU32)SyncSkewHigh) & DRF_MASK(NV_P2060_SYNC_SKEW_HIGH_VAL)) << 8 ) | + ((((NvU32)SyncSkewLow ) & DRF_MASK(NV_P2060_SYNC_SKEW_LOW_VAL )) ) ) ; + } + + // update p2060 object + pThis->SyncSkew = *pSyncSkew; + + return rmStatus; +} + +NV_STATUS +gsyncSetSyncStartDelay_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 StartDelay +) +{ + NvU8 StartDelayLow, StartDelayHigh; + NV_STATUS rmStatus = NV_OK; + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; + + // update p2060 object + pThis->SyncStartDelay = StartDelay; + + StartDelayLow = (NvU8)((StartDelay ) & DRF_MASK(NV_P2060_START_DELAY_LOW_VAL )); + StartDelayHigh= (NvU8)((StartDelay >> 8) & DRF_MASK(NV_P2060_START_DELAY_HIGH_VAL)); + + rmStatus |= writeregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_START_DELAY_LOW, StartDelayLow); + rmStatus |= writeregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_START_DELAY_HIGH, StartDelayHigh); + + return rmStatus; +} + +NV_STATUS +gsyncGetSyncStartDelay_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 *pStartDelay +) +{ + NvU8 StartDelayLow, StartDelayHigh; + NV_STATUS rmStatus = NV_OK; + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; + + rmStatus |= readregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_START_DELAY_LOW, &StartDelayLow); + rmStatus |= readregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_START_DELAY_HIGH, &StartDelayHigh); + + if ( NV_OK == rmStatus ) + { + *pStartDelay = + ( ((((NvU32)StartDelayHigh) & DRF_MASK(NV_P2060_START_DELAY_HIGH_VAL)) << 8 ) | + ((((NvU32)StartDelayLow ) & DRF_MASK(NV_P2060_START_DELAY_LOW_VAL )) ) ); + } + + // update p2060 object + pThis->SyncStartDelay = *pStartDelay; + + return rmStatus; +} + +/* + * check if housesync is present or not. + */ +static NV_STATUS +gsyncReadHouseSignalPresent_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvBool bTestSyncLoss, + NvU32 *pVal +) +{ + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; + NvU8 regStatus2; + NvU32 regStatus = GetP2060GpuSnapshot(pGpu,pThis); + NV_STATUS rmStatus = NV_OK; + + NV_ASSERT_OR_RETURN(pGpu, NV_ERR_GENERIC); + + if (bTestSyncLoss && FLD_TEST_DRF(_P2060, _STATUS, _SYNC_LOSS, _TRUE, (NvU32)regStatus)) + { + rmStatus |= gsyncUpdateGsyncStatusSnapshot_P2060(pGpu, pExtDev); + + if ( NV_OK != rmStatus ) + return rmStatus; + + if (FLD_TEST_DRF(_P2060, _STATUS, _SYNC_LOSS, _TRUE, GetP2060GpuSnapshot(pGpu,pThis))) + { + *pVal = 0; // bTestSyncLoss and (SYNC_LOSS == NV_TRUE) + } + } + else + { + rmStatus = readregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE)pThis, + (NvU8)NV_P2060_STATUS2, ®Status2); + if ( NV_OK != rmStatus ) + return rmStatus; + + *pVal = !!(DRF_VAL(_P2060, _STATUS2, _HS_DETECT, (NvU32)regStatus2)); + } + + return rmStatus; +} + +/* + * This function returns whether there is a sync source present. + * + * SYNC_LOSS bit in STATUS register is true by default, i.e when there + * is no incoming sync source. This bit is unset when a stable sync + * source is detected. + * + * Whenever framelock is enabled, NV_TRUE is returned only when the incoming + * sync source is stable. Therefore it is sent based on the software state. + * + * When framelock is not enabled, return value totally depends on the value + * of the gsync STATUS register. + */ +static NV_STATUS +gsyncReadIsSyncDetected_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 *pVal +) +{ + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; + NV_STATUS rmStatus = NV_OK; + NvU32 iface; + + NV_ASSERT_OR_RETURN(pGpu, NV_ERR_GENERIC); + + if (!gsyncIsFrameLocked_P2060(pThis)) + { + NvU8 regStatus; + + // framelock is not enabled, read the NV_P2060_STATUS register to get the SYNC status + rmStatus = readregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE)pThis, (NvU8)NV_P2060_STATUS, ®Status); + + if (rmStatus == NV_OK) + { + *pVal = (NV_P2060_STATUS_SYNC_LOSS_TRUE != DRF_VAL(_P2060, _STATUS, _SYNC_LOSS, regStatus)); + } + } + else + { + rmStatus = GetP2060GpuLocation(pGpu, pThis, &iface); + if (NV_OK != rmStatus) + { + return rmStatus; + } + + // + // Sync gain should only be derived from our internal tracking variable. + // The gsync status variables are reporting more transient data than desired. + // + *pVal = pThis->Iface[iface].gainedSync; + } + + return rmStatus; +} + +/* + * Check if stereo is locked or not. + * + * stereo is locked means + * - a framelock master signal is available as reference + * - sync to this master signal has been gained + * - master and local gpu both have either stereo enabled or disabled + * - master and local stereo signal is in phase (in case it's enabled) + */ +static NV_STATUS +gsyncReadStereoLocked_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 *pVal +) +{ + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; + NV_STATUS rmStatus = NV_ERR_GENERIC; + + if (pVal) + { + NvU32 iface; + + // Default return is stereo not locked. + *pVal = 0; + + // which gpu's interface are we talking to? + rmStatus = GetP2060GpuLocation(pGpu, pThis, &iface); + + if (NV_OK == rmStatus) + { + // stereo status reporting only makes sense if we've gained sync. + if (pThis->Iface[iface].gainedSync) + { + NvU32 regStatus = GetP2060GpuSnapshot(pGpu,pThis); + + if ((NV_P2060_STATUS_MSTR_STEREO_NOT_ACTIVE == + DRF_VAL(_P2060, _STATUS, _MSTR_STEREO, regStatus)) && + (NV_P2060_STATUS_GPU_STEREO_NOT_ACTIVE == + DRF_VAL(_P2060, _STATUS, _GPU_STEREO, regStatus))) + { + // + // If neither local nor master stereo is enabled + // stereo is locked. + // + *pVal = 1; + } + else + { + // + // If local or master stereo signals are present, + // return back P358s stereo_lock reporting. + // + *pVal = (NV_P2060_STATUS_STEREO_LOCK == + DRF_VAL(_P2060, _STATUS, _STEREO, regStatus)); + } + } + } + } + + return rmStatus; +} + +/* + * Check if VCXO is locked or not. + */ +static NV_STATUS +gsyncReadVCXOLocked_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 *pVal +) +{ + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; + NV_STATUS rmStatus = NV_OK; + NvU32 regStatus = GetP2060GpuSnapshot(pGpu,pThis); + + // Status1 only needs to be read if the shapshot shows recent error or no vcxo lock + if (!FLD_TEST_DRF(_P2060, _STATUS, _VCXO, _LOCK, regStatus)) + { + rmStatus = gsyncUpdateGsyncStatusSnapshot_P2060(pGpu, pExtDev); + if ( NV_OK == rmStatus ) + { + *pVal = FLD_TEST_DRF(_P2060, _STATUS, _VCXO, _LOCK, GetP2060GpuSnapshot(pGpu,pThis)); + } + } + else + { + *pVal = 1; //VCXO is locked. + } + + return rmStatus; +} + +/* + * Check if timing is present or not. + */ +static NV_STATUS +gsyncReadIsTiming_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 *pVal +) +{ + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; + NV_STATUS rmStatus = NV_OK; + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + NvU32 numHeads = kdispGetNumHeads(pKernelDisplay); + NvU32 bHouse, bLock = 0, bSync; + NvU32 iface, head, tempIface, tempHead; + + rmStatus = GetP2060GpuLocation(pGpu, pThis, &iface); + if (NV_OK != rmStatus) + { + return rmStatus; + } + + // assume no, unless we find something below + *pVal = (NvU32)NV_FALSE; + + for (head = 0; head < numHeads; head++) + { + // check if we're slaved to another master head in the same system + if (pThis->Iface[iface].Sync.LocalSlave[head]) + { + for (tempIface = 0; tempIface < NV_P2060_MAX_IFACES_PER_GSYNC; tempIface++) + { + for (tempHead = 0; tempHead < numHeads; tempHead++) + { + if (pThis->Iface[tempIface].Sync.Master[tempHead]) + { + // assume that if we're slaved to another local head + // that we're in sync. there's no easy way to verify + // this, short of trying to compare raster scanlines + *pVal = (NvU32)NV_TRUE; + } + } + } + break; + } + + // check if we have a master, connected to a house sync + if (pThis->Iface[iface].Sync.Master[head] && pThis->Iface[iface].Sync.Slaved[head]) + { + rmStatus |= gsyncReadHouseSignalPresent_P2060(pGpu, pExtDev, NV_TRUE, &bHouse); + if ( NV_OK == rmStatus ) + { + *pVal = (NvU32)(bHouse); + } + break; + } + + // check if we have a master head, not connected to house sync + if (pThis->Iface[iface].Sync.Master[head]) + { + // a master is by definition always in sync + *pVal = (NvU32)NV_TRUE; + break; + } + + if (pThis->Iface[iface].Sync.Slaved[head]) + { + rmStatus |= gsyncReadIsSyncDetected_P2060(pGpu, pExtDev, &bSync); + rmStatus |= gsyncReadVCXOLocked_P2060(pGpu, pExtDev, &bLock); + if ( NV_OK == rmStatus ) + { + *pVal = (NvU32)(bSync && bLock); + } + break; + } + } + return rmStatus; +} + + +/* + * Program P2060 Master for Framelock. + */ +static NV_STATUS +gsyncProgramMaster_P2060 +( + OBJGPU *pGpu, + PDACP2060EXTERNALDEVICE pThis, + NvU32 Master, + NvBool bRetainMaster, + NvBool skipSwapBarrierWar +) +{ + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + NvU32 DisplayIds[OBJ_MAX_HEADS]; + NvU32 iface, head, index; + NvU8 ctrl = 0; + NvBool bTestModePresent; + NvBool bHouseSelect, bEnableMaster = (0 != Master); + NvBool bGPUAlreadyMaster; + NvBool bQSyncAlreadyMaster; + NV_STATUS rmStatus = NV_OK; + NvU32 numHeads = kdispGetNumHeads(pKernelDisplay); + + if ( Master && bRetainMaster) + { + for (iface = 0; iface < NV_P2060_MAX_IFACES_PER_GSYNC; iface++) + { + for ( head = 0; head < numHeads; head++ ) + { + if ( pThis->Iface[iface].Sync.Master[head] ) + { + pThis->Iface[iface].Sync.Master[head] = 0; + pThis->Iface[iface].Sync.Slaved[head] = 0; + pThis->Iface[iface].Sync.LocalSlave[head] = 0; + } + } + } + return rmStatus; + } + + // This utility fn returns display id's associated with each head. + extdevGetBoundHeadsAndDisplayIds(pGpu, DisplayIds); + + // which gpu's are we talking to? + rmStatus = GetP2060GpuLocation(pGpu, pThis, &iface); + if (NV_OK != rmStatus) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to get Gpu location. Can not program Master.\n"); + return rmStatus; + } + + // no failure allowed! + rmStatus = readregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE)pThis, + (NvU8)NV_P2060_CONTROL, &ctrl); + if ((NV_OK != rmStatus)) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to read Ctrl data. Can not program Master.\n"); + return rmStatus; + } + + // Check if TEST MODE present + bTestModePresent = FLD_TEST_DRF(_P2060, _CONTROL, _TEST_MODE, _ON, (NvU32)ctrl); + + // Check for House sync select as sync source + bHouseSelect = FLD_TEST_DRF(_P2060, _CONTROL, _SYNC_SELECT, _HOUSE, (NvU32)ctrl); + + rmStatus = GetP2060ConnectorIndexFromGpu(pGpu, pThis, &index); + if (NV_OK != rmStatus) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to get connector index for Gpu. Can not program Master.\n"); + return rmStatus; + } + // + // For P2060, Already Mastership based on FPGA -> I_AM_MASTER + GPU -> TIMING SOURCE. + // First check for display is already Master or not i.e. GPU is TS or not. + // Then check for FPGA board is already Master or not. + // + bGPUAlreadyMaster = (DRF_VAL(_P2060, _CONTROL, _SYNC_SRC, (NvU32)ctrl) == index); + bQSyncAlreadyMaster = FLD_TEST_DRF(_P2060, _CONTROL, _I_AM, _MASTER, (NvU32)ctrl); + + // In case of Passthru mode, Qsync board can be shared across multiple VMs. + // If Qsync board is already master, then only TS Gpu should be allowed to change it's mastership. + // Bail out if non TS GPU tries to change it. + if (IS_PASSTHRU(pGpu) && (bQSyncAlreadyMaster & !bGPUAlreadyMaster)) + { + return rmStatus; + } + + if (bQSyncAlreadyMaster != bEnableMaster) + { + if (pThis->ExternalDevice.deviceRev == DAC_EXTERNAL_DEVICE_REV_NONE) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to read NV_P2060_FPGA. Can not program Master.\n"); + return rmStatus; + } + + if (bEnableMaster) + { + rmStatus = gsyncApplyStereoPinAlwaysHiWar(pGpu, (PDACEXTERNALDEVICE)pThis); + + if (NV_OK != rmStatus) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to drive stereo output pin for bug3362661.\n"); + } + // + // GPU will now be TS - Mark sync source for GPU on derived index. + // This needs to be done first as only TS can write I_AM_MASTER bit. + // + ctrl = FLD_SET_DRF_NUM(_P2060, _CONTROL, _SYNC_SRC, (NvU8)index, ctrl); + rmStatus |= writeregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE) pThis, + (NvU8)NV_P2060_CONTROL, ctrl); + if (NV_OK != rmStatus) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to write SYNC_SRC. Can not program Master.\n"); + return rmStatus; + } + } + + if (bTestModePresent) + { + // Clear the TEST mode bit before handling enable/disable master. + ctrl = FLD_SET_DRF(_P2060, _CONTROL, _TEST_MODE, _OFF, ctrl); + + if (!bEnableMaster) + { + // + // Clear the TEST mode bit before disabling master as TEST mode + // can only be modified by the GPU TS under FPGA master mode. + // + rmStatus |= writeregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE) pThis, + (NvU8)NV_P2060_CONTROL, ctrl); + osDelay(30); // Add delay of 30 ms as we are turning OFF TEST mode. + } + } + + // Gsync/FPGA card will be master or not based on bEnableMaster. + ctrl = FLD_SET_DRF_NUM(_P2060, _CONTROL, _I_AM, (NvU8)bEnableMaster, ctrl); + rmStatus |= writeregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE) pThis, + (NvU8)NV_P2060_CONTROL, ctrl); + if (NV_OK != rmStatus) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to write I_AM_MSTR. Can not program Master.\n"); + return rmStatus; + } + + // + // Now we have updated Master status of Gsync board, wait for some time. This will allow FPGA to + // reflect state-change in other registers e.g portStat, Frame Rate etc. Refer Bug 1053022. + // + osDelay(200); + + if (bEnableMaster) + { + // Remember the desired skipSwapBarrierWar setting for enable master calls. + pThis->Iface[iface].skipSwapBarrierWar = skipSwapBarrierWar; + } + else + { + // Fetch the real skipSwapBarrierWar value from cache in case of an unsync call. + skipSwapBarrierWar = pThis->Iface[iface].skipSwapBarrierWar; + // And reset the cached value. + pThis->Iface[iface].skipSwapBarrierWar = NV_FALSE; + } + + // + // Fpga revisions <= 5 need to sw the swapbarrier on the framelock master + // to drive the swap_rdy signal. This can be overridden by skipSwapBarrierWar. + // + if ((!skipSwapBarrierWar) && + needsMasterBarrierWar(&pThis->ExternalDevice)) + { + // enable/disable SwapRdy for GPU during enable/disable of Framelock Master. + rmStatus = gsyncUpdateSwapRdyConnectionForGpu_P2060(pGpu, pThis, bEnableMaster); + if (NV_OK != rmStatus) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to update SwapRdyEnable. Can not program Master.\n"); + return rmStatus; + } + } + } + + // now we're ready to let the software know about it. + for ( head = 0; head < numHeads; head++ ) + { + // is this head the desired master, or are we are disabling mastership? + // If mastership is currently disabled, don't touch cache as this could destroy slave values.0 + if ((Master & DisplayIds[head]) || (!bEnableMaster && bQSyncAlreadyMaster)) + { + pThis->Iface[iface].Sync.Master[head] = (bEnableMaster); + pThis->Iface[iface].Sync.Slaved[head] = (bEnableMaster && bHouseSelect); + + gsyncProgramFramelockEnable_P2060(pGpu, pThis, iface, bEnableMaster); + } + else + { + // we are setting a master, but it's not on this head, so just to be safe: + pThis->Iface[iface].Sync.Master[head] = 0; + } + } + + if (!bEnableMaster && !gsyncIsFrameLocked_P2060(pThis)) + { + // Disable Framelock interrupts as board is not framelocked now. + gsyncDisableFrameLockInterrupt_P2060((PDACEXTERNALDEVICE)pThis); + + rmStatus = gsyncUnApplyStereoPinAlwaysHiWar(pGpu); + + if (NV_OK != rmStatus) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to drive stereo output pin for bug3362661.\n"); + } + } + + if (!IsSLIEnabled(pGpu)) + { + NvU32 otherGpuId; + OBJGPU *pOtherGpu; + RM_API *pRmApi; + NvU32 hClient; + NvU32 hSubdevice; + NvU32 Slaves, drOut, drIn; + NvU32 tempIface; + NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS ctrlParams = {0}; + + for (tempIface = 0; tempIface < NV_P2060_MAX_IFACES_PER_GSYNC; tempIface++) + { + if (tempIface == iface) + { + continue; + } + + otherGpuId = pThis->Iface[tempIface].GpuInfo.gpuId; + if (otherGpuId == NV0000_CTRL_GPU_INVALID_ID) + { + continue; + } + + pOtherGpu = gpumgrGetGpuFromId(otherGpuId); + NV_ASSERT(pOtherGpu); + + if (gpumgrGetGpuLockAndDrPorts(pGpu, pOtherGpu, &drOut, &drIn) != NV_OK) + { + continue; + } + // + // If this is the master gpu, we need to disable the raster sync + // gpio on the other P2060 GPU that's connected to master over + // Video bridge. Otherwise, if the video bridge is connected, + // the raster sync signals from the two cards will interfere, + // giving us an unreliable sync signal. + // + pRmApi = GPU_GET_PHYSICAL_RMAPI(pOtherGpu); + hClient = pOtherGpu->hInternalClient; + hSubdevice = pOtherGpu->hInternalSubdevice; + + ctrlParams.bEnableMaster = bEnableMaster; + ctrlParams.bRasterSyncGpioSaved = pThis->Iface[tempIface].RasterSyncGpio.saved; + ctrlParams.bRasterSyncGpioDirection = pThis->Iface[tempIface].RasterSyncGpio.direction; + + rmStatus = pRmApi->Control(pRmApi, hClient, hSubdevice, + NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC, + &ctrlParams, sizeof(ctrlParams)); + + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Extdev control call to save/restore GPIO direction is failed!\n"); + } + else + { + if (bEnableMaster && !pThis->Iface[tempIface].RasterSyncGpio.saved) + { + pThis->Iface[tempIface].RasterSyncGpio.direction = ctrlParams.bRasterSyncGpioDirection; + pThis->Iface[tempIface].RasterSyncGpio.saved = NV_TRUE; + } + else if (!bEnableMaster && pThis->Iface[tempIface].RasterSyncGpio.saved) + { + pThis->Iface[tempIface].RasterSyncGpio.saved = NV_FALSE; + } + } + + Slaves = gsyncReadSlaves_P2060(pOtherGpu, pThis); + if (Slaves) + { + rmStatus = gsyncProgramSlaves_P2060(pOtherGpu, pThis, Slaves); + if (NV_OK != rmStatus) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to program SLI slaves. Can not program Master.\n"); + return rmStatus; + } + } + } + } + + // Reset the frame count data and also disable frame compare match interrupt. + if (!bEnableMaster) + { + iface = pThis->FrameCountData.iface; + head = pThis->FrameCountData.head; + + if ((iface < NV_P2060_MAX_IFACES_PER_GSYNC) && (head < numHeads)) + { + rmStatus |= gsyncResetFrameCountData_P2060(pGpu, pThis); + } + } + return rmStatus; +} + +/* + * Read Framelock Master P2060. + */ +static NvU32 +gsyncReadMaster_P2060 +( + OBJGPU *pGpu, + PDACP2060EXTERNALDEVICE pThis +) +{ + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + NvU32 DisplayIds[OBJ_MAX_HEADS]; + NvU32 iface, head; + NvU32 Master = 0; + NV_STATUS status; + NvU32 numHeads = kdispGetNumHeads(pKernelDisplay); + + extdevGetBoundHeadsAndDisplayIds(pGpu, DisplayIds); + + status = GetP2060GpuLocation(pGpu, pThis, &iface); + if (NV_OK != status) + return 0; + + for ( head = 0; head < numHeads; head++ ) + { + if (pThis->Iface[iface].Sync.Master[head]) + { + Master |= DisplayIds[head]; + } + } + + // check hardware's opinion on the Master Gsync and Timing source GPU. + if (gsyncIsP2060MasterBoard(pGpu, pThis) && + GpuIsP2060Master(pGpu, pThis)) + { + if (Master) + { + return Master; + } + else + { + // HW is set to be master, but SW isn't treating it as master? + // we must be on external sync, so no one display is associated... + return ~0; + } + } + else + { + // if HW says it's not the master, SW's opinion doesn't count. + return 0; + } +} + +/* + * Program P2060 Slave for framelock. + */ +static NV_STATUS +gsyncProgramSlaves_P2060 +( + OBJGPU *pGpu, + PDACP2060EXTERNALDEVICE pThis, + NvU32 Slaves +) +{ + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + NvU32 DisplayIds[OBJ_MAX_HEADS]; + NvU32 iface, head, index; + NvU8 ctrl = 0, ctrl3 = 0; + NvBool bCoupled, bHouseSelect, bLocalMaster, bEnableSlaves = (0 != Slaves); + NV_STATUS rmStatus = NV_OK; + NvU32 numHeads = kdispGetNumHeads(pKernelDisplay); + + // This utility fn returns display id's associated with each head. + extdevGetBoundHeadsAndDisplayIds(pGpu, DisplayIds); + + // which gpu's are we talking to? + rmStatus = GetP2060GpuLocation(pGpu, pThis, &iface); + if (NV_OK != rmStatus) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to get Gpu location. Can not program Slave.\n"); + return rmStatus; + } + + rmStatus = readregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE)pThis, + (NvU8)NV_P2060_CONTROL, &ctrl); + if (NV_OK != rmStatus) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to read ctrl register. Can not program slave.\n"); + return rmStatus; // ouch + } + + // Check for House sync select as sync source and FPGA board is master or not + bHouseSelect = FLD_TEST_DRF(_P2060, _CONTROL, _SYNC_SELECT, _HOUSE, (NvU32)ctrl); + bLocalMaster = FLD_TEST_DRF(_P2060, _CONTROL, _I_AM, _MASTER, (NvU32)ctrl); + + if (bEnableSlaves || bLocalMaster) + { + rmStatus = gsyncApplyStereoPinAlwaysHiWar(pGpu, (PDACEXTERNALDEVICE)pThis); + + if (NV_OK != rmStatus) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to drive stereo output pin for bug3362661.\n"); + } + } + + if (bHouseSelect && bEnableSlaves && bLocalMaster) + { + rmStatus = readregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE)pThis, + (NvU8)NV_P2060_CONTROL3, &ctrl3); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to read ctrl3 register. Can not program slave.\n"); + return rmStatus; + } + ctrl3 |= (NvU8) FLD_SET_DRF(_P2060, _CONTROL3, _RESYNC, _ON, (NvU32)ctrl3); + writeregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE)pThis, + (NvU8)NV_P2060_CONTROL3, ctrl3); + } + + // + // No need to check for every gpu connected to this gsync board. If gsync board + // is not master/server, none of the gpu connected to it will have master head. + // + + if (bEnableSlaves && !bLocalMaster) + { + // + // Sync source should be taken from GPU connected to Gsync board. + // Get index of current GPU and make it sync source. + // No idea is this safe or not. Adding TODO for future check. + // + rmStatus = GetP2060ConnectorIndexFromGpu(pGpu, pThis, &index); + if (NV_OK != rmStatus) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to get connector index for Gpu. Can not program slave.\n"); + return rmStatus; + } + + ctrl = FLD_SET_DRF_NUM(_P2060, _CONTROL, _SYNC_SRC, (NvU8)index, ctrl); + + rmStatus = writeregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE) pThis, + (NvU8)NV_P2060_CONTROL, ctrl); + if (NV_OK != rmStatus) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to write SYNC_SRC. Can not program slave.\n"); + return rmStatus; + } + } + + // + // With House sync enabled the crashlocking still need some investigations. + // So filter out Housesyced systems before doing local crashlocks. + // + if ((!bHouseSelect) && bEnableSlaves && bLocalMaster) + { + rmStatus = readregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE)pThis, + (NvU8)NV_P2060_CONTROL3, &ctrl3); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to read ctrl3 register. Can not program slave.\n"); + return rmStatus; + } + ctrl3 |= (NvU8) FLD_SET_DRF(_P2060, _CONTROL3, _RESYNC, _ON, (NvU32)ctrl3); + writeregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE)pThis, + (NvU8)NV_P2060_CONTROL3, ctrl3); + } + + // + // If we on the same gpu as the framelock master, the P2060 will + // not servo, so we must rely on the gpu to get our timing... + // unless house sync is expected, in which case we get it back. + // + bCoupled = (!bLocalMaster) || (bHouseSelect); + + // disable all existing slaves before enabling new slaves. + if (bEnableSlaves) + { + for ( head = 0; head < numHeads; head++ ) + { + pThis->Iface[iface].Sync.Slaved[head] = 0; + pThis->Iface[iface].Sync.LocalSlave[head] = 0; + } + } + + for ( head = 0; head < numHeads; head++ ) + { + // is this head to be slaved, or are we freeing all slaves? + if ((Slaves & DisplayIds[head]) || !bEnableSlaves) + { + pThis->Iface[iface].Sync.Slaved[head] = (bEnableSlaves && bCoupled); + pThis->Iface[iface].Sync.LocalSlave[head] = (bEnableSlaves && !bCoupled); + + gsyncProgramFramelockEnable_P2060(pGpu, pThis, iface, bEnableSlaves); + } + else + { + // we are setting a slave, but it's not on this head, so nothing needs doing. + } + } + + if (!bEnableSlaves && !gsyncIsFrameLocked_P2060(pThis)) + { + // Disable Framelock interrupts as board is not framelocked now. + gsyncDisableFrameLockInterrupt_P2060((PDACEXTERNALDEVICE)pThis); + + rmStatus = gsyncUnApplyStereoPinAlwaysHiWar(pGpu); + + if (NV_OK != rmStatus) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to drive stereo output pin for bug3362661.\n"); + } + } + + // Reset FrameCountData and disable frame compare match interrupt. + if (iface == pThis->FrameCountData.iface) + { + if (!(Slaves & DisplayIds[pThis->FrameCountData.head])) + { + if (pThis->Iface[iface].GpuInfo.gpuId != NV0000_CTRL_GPU_INVALID_ID) + { + rmStatus |= gsyncResetFrameCountData_P2060(pGpu, pThis); + } + } + } + return rmStatus; +} + +/* + * Read P2060 slave for framelock. + */ +static NvU32 +gsyncReadSlaves_P2060 +( + OBJGPU *pGpu, + PDACP2060EXTERNALDEVICE pThis +) +{ + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + NvU32 DisplayIds[OBJ_MAX_HEADS]; + NvU32 iface, head; + NvU32 Slaves = 0; + NV_STATUS status; + NvU32 numHeads = kdispGetNumHeads(pKernelDisplay); + + extdevGetBoundHeadsAndDisplayIds(pGpu, DisplayIds); + + status = GetP2060GpuLocation(pGpu, pThis, &iface); + if (NV_OK != status) + return 0; + + for ( head = 0; head < numHeads; head++ ) + { + if (!pThis->Iface[iface].Sync.Master[head] && + (pThis->Iface[iface].Sync.Slaved[head] || pThis->Iface[iface].Sync.LocalSlave[head])) + { + Slaves |= DisplayIds[head]; + } + } + return Slaves; +} + +static NV_STATUS +gsyncProgramSwapBarrier_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvBool bEnable +) +{ + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE) pExtDev; + NvU32 iface; + NvU8 ctrl2 = 0; + NV_STATUS status = NV_OK; + + status = GetP2060GpuLocation(pGpu, pThis, &iface); + if (NV_OK != status) + { + if (!IsSLIEnabled(pGpu)) + { + // + // If not in SLI, this function must only be called on GPUs connected + // to the framelock board. + // + return status; + } + else + { + // + // In SLI, we will try to add all GPUs in a topology to a swap + // barrier, but not all of the GPUs actually have to be connected to + // the framelock board, so we can return NV_OK to let the caller continue + // on to the next GPU. + // + NV_PRINTF(LEVEL_INFO, + "Ignoring GPU %u not connected to the framelock board.\n", + gpumgrGetSubDeviceInstanceFromGpu(pGpu)); + return NV_OK; + } + } + + // Each connected GPU accesses it's own version of CONTROL2, on P2060 + if (GpuIsP2060Connected(pGpu, pThis)) + { + status = readregu008_extdeviceTargeted(pGpu, pExtDev, + NV_P2060_CONTROL2, &ctrl2); + if (status != NV_OK) + { + return status; + } + + if (pExtDev->deviceRev >= DAC_EXTERNAL_DEVICE_REV_MAX) + { + return NV_ERR_INVALID_STATE; + } + } + + if (pThis->Iface[iface].SwapReadyRequested == bEnable) + { + // + // The SwapReadyRequested boolean keeps tracks of the current + // requested state for this GPU. Skip the WAR algorithm if it's + // already taken this GPU's state into account. + // + return NV_OK; + } + + if (bEnable) // Enable Swap_rdy + { + ctrl2 = FLD_SET_DRF(_P2060, _CONTROL2, _SWAP_READY, _ENABLE, ctrl2); + + if (pThis->tSwapRdyHiLsrMinTime == 0) + { + NvU32 data = 0; + + // store Swap Lockout Window in pThis. + pThis->tSwapRdyHiLsrMinTime = NV_REG_STR_TIME_SWAP_RDY_HI_MODIFY_LSR_MIN_TIME_DEFAULT; + if (osReadRegistryDword(pGpu, + NV_REG_STR_TIME_SWAP_RDY_HI_MODIFY_LSR_MIN_TIME, &data) == NV_OK) + { + pThis->tSwapRdyHiLsrMinTime = data; + } + } + + NV_ASSERT(pThis->tSwapRdyHiLsrMinTime != 0); + + if (pThis->Iface[iface].DsiFliplock.saved == NV_FALSE) + { + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + NvU32 numHeads = kdispGetNumHeads(pKernelDisplay); + NvU32 head ; + + for (head = 0; head < numHeads; head++) + { + NvU32 newLsrMinTime; + if ((status = kdispComputeLsrMinTimeValue_HAL(pGpu, pKernelDisplay, head, + pThis->tSwapRdyHiLsrMinTime, &newLsrMinTime)) == NV_OK) + { + NvU32 origLsrMinTime; + kdispSetSwapBarrierLsrMinTime_HAL(pGpu, pKernelDisplay, head, &origLsrMinTime, + newLsrMinTime); + + pThis->Iface[iface].DsiFliplock.OrigLsrMinTime[head] = origLsrMinTime; + } + else + { + NV_PRINTF(LEVEL_ERROR, + "Error occured while computing LSR_MIN_TIME for Swap Barrier\n"); + NV_ASSERT(0); + } + } + pThis->Iface[iface].DsiFliplock.saved = NV_TRUE; + } + + // The swapbarrier on master war is assumed to be fixed with fpga rev > 5. + if ((!pThis->Iface[iface].skipSwapBarrierWar) && + needsMasterBarrierWar(&pThis->ExternalDevice)) + { + if (gsyncIsP2060MasterBoard(pGpu, pThis) && GpuIsP2060Master(pGpu, pThis)) + { + // + // Swap Rdy signal on Master + TS GPU will enabled or disabled during + // Enable/Disable of Master i.e. gsyncProgramMaster_P2060 + // + pThis->Iface[iface].SwapReadyRequested = bEnable; + return NV_OK; + } + } + + if (GpuIsConnectedToMasterViaBridge(pGpu, pThis) && + (gpumgrGetGpuBridgeType() == SLI_BT_VIDLINK || isBoardWithNvlinkQsyncContention(pGpu))) + { + // + // Do not enable swapRdy Connection of pGpu. pGpu will take swap Rdy signal + // from Master + TS GPU via SLI (MIO) bridge + // + pThis->Iface[iface].SwapReadyRequested = bEnable; + return status; //NV_OK + } + } + else + { + ctrl2 = FLD_SET_DRF(_P2060, _CONTROL2, _SWAP_READY, _DISABLE, ctrl2); // Disable Swap_rdy + + if (pThis->Iface[iface].DsiFliplock.saved == NV_TRUE) + { + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + NvU32 numHeads = kdispGetNumHeads(pKernelDisplay); + NvU32 head ; + + for (head = 0; head < numHeads; head++) + { + kdispRestoreOriginalLsrMinTime_HAL(pGpu, pKernelDisplay, head, + pThis->Iface[iface].DsiFliplock.OrigLsrMinTime[head]); + } + pThis->Iface[iface].DsiFliplock.saved = NV_FALSE; + } + + // The swapbarrier on master war is assumed to be fixed with fpga rev > 5. + if ((!pThis->Iface[iface].skipSwapBarrierWar) && + needsMasterBarrierWar(&pThis->ExternalDevice)) + { + if (gsyncIsP2060MasterBoard(pGpu, pThis) && GpuIsP2060Master(pGpu, pThis)) + { + // + // Swap Rdy signal on Master + TS GPU will enabled or disabled during + // Enable/Disable of Master i.e. gsyncProgramMaster_P2060 + // + pThis->Iface[iface].SwapReadyRequested = bEnable; + return NV_OK; + } + } + } + + // Save the requested state for this GPU + pThis->Iface[iface].SwapReadyRequested = bEnable; + + // Each connected GPU accesses it's own version of CONTROL2, on P2060 + if (GpuIsP2060Connected(pGpu, pThis)) + { + status = writeregu008_extdeviceTargeted(pGpu, pExtDev, + NV_P2060_CONTROL2, ctrl2); + } + + return status; +} + + +static NV_STATUS +gsyncReadSwapBarrier_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvBool *bEnable +) +{ + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE) pExtDev; + NvU32 iface; + NV_STATUS status = NV_OK; + + status = GetP2060GpuLocation(pGpu, pThis, &iface); + if (NV_OK != status) + { + if (!IsSLIEnabled(pGpu)) + { + // + // If not in SLI, this function must only be called on GPUs connected + // to the framelock board. + // + return status; + } + else + { + // + // In SLI, we will try to read the swap barrier info from all GPUs in a + // topology, but not all of the GPUs actually have to be connected to + // the framelock board, so we can return NV_OK to let the caller continue + // on to the next GPU. + // + NV_PRINTF(LEVEL_INFO, + "Ignoring GPU %u not connected to the framelock board.\n", + gpumgrGetSubDeviceInstanceFromGpu(pGpu)); + return NV_OK; + } + } + + if (gsyncIsP2060MasterBoard(pGpu, pThis) && GpuIsP2060Master(pGpu, pThis)) + { + // Read swapRdy of Master + TS GPU. + *bEnable = pThis->Iface[iface].SwapReadyRequested; + return status; //NV_OK + } + + if (GpuIsConnectedToMasterViaBridge(pGpu, pThis) && + (gpumgrGetGpuBridgeType() == SLI_BT_VIDLINK || isBoardWithNvlinkQsyncContention(pGpu))) + { + // Read swapRdy of pGpu connected to Master + TS GPU via SLI (MIO) bridge. + *bEnable = pThis->Iface[iface].SwapReadyRequested; + return status; //NV_OK + } + + // Each connected GPU accesses it's own version of CONTROL2, on P2060 + if (GpuIsP2060Connected(pGpu, pThis)) + { + NvU8 ctrl2 = 0; + status = readregu008_extdeviceTargeted(pGpu, + pExtDev, NV_P2060_CONTROL2, &ctrl2); + if (status != NV_OK) + { + return status; + } + *bEnable = (NV_P2060_CONTROL2_SWAP_READY_ENABLE == + DRF_VAL(_P2060, _CONTROL2, _SWAP_READY, (NvU32)ctrl2)); + } + + return status; +} + +static NV_STATUS +gsyncSetLsrMinTime +( + OBJGPU *pSourceGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 enable +) +{ + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; + NV_STATUS rmStatus = NV_OK; + NvU32 index; + + // Get Mosaic Timing Source GPU Connector Index. + if (NV_OK != GetP2060ConnectorIndexFromGpu(pSourceGpu, pThis, &index)) + { + return NV_ERR_GENERIC; + } + + if (enable) + { + // Set LSR_MIN_TIME + if (pThis->tSwapRdyHiLsrMinTime == 0) + { + NvU32 data = 0; + + // store Swap Lockout Window in pThis. + pThis->tSwapRdyHiLsrMinTime = NV_REG_STR_TIME_SWAP_RDY_HI_MODIFY_LSR_MIN_TIME_DEFAULT; + + if (osReadRegistryDword(pSourceGpu, + NV_REG_STR_TIME_SWAP_RDY_HI_MODIFY_LSR_MIN_TIME, &data) == NV_OK) + { + pThis->tSwapRdyHiLsrMinTime = data; + } + } + + if (pThis->Iface[index].DsiFliplock.saved == NV_FALSE) + { + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pSourceGpu); + NvU32 numHeads = kdispGetNumHeads(pKernelDisplay); + NvU32 head; + + // Do we need to loop over numHeads? + for (head = 0; head < numHeads; head++) + { + NvU32 newLsrMinTime; + + if ((rmStatus = kdispComputeLsrMinTimeValue_HAL(pSourceGpu, pKernelDisplay, head, + pThis->tSwapRdyHiLsrMinTime, &newLsrMinTime)) == NV_OK) + { + NvU32 origLsrMinTime; + + kdispSetSwapBarrierLsrMinTime_HAL(pSourceGpu, pKernelDisplay, head, &origLsrMinTime, + newLsrMinTime); + + pThis->Iface[index].DsiFliplock.OrigLsrMinTime[head] = origLsrMinTime; + } + else + { + NV_PRINTF(LEVEL_ERROR, + "Error occured while computing LSR_MIN_TIME for Swap Barrier\n"); + NV_ASSERT(0); + } + } + + pThis->Iface[index].DsiFliplock.saved = NV_TRUE; + } + } + else + { + if (pThis->Iface[index].DsiFliplock.saved == NV_TRUE) + { + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pSourceGpu); + NvU32 numHeads = kdispGetNumHeads(pKernelDisplay); + NvU32 head; + + for (head = 0; head < numHeads; head++) + { + kdispRestoreOriginalLsrMinTime_HAL(pSourceGpu, pKernelDisplay, head, + pThis->Iface[index].DsiFliplock.OrigLsrMinTime[head]); + } + + pThis->Iface[index].DsiFliplock.saved = NV_FALSE; + } + } + + return rmStatus; +} + +NV_STATUS +gsyncSetMosaic_P2060 +( + OBJGPU *pSourceGpu, + PDACEXTERNALDEVICE pExtDev, + NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS *pParams +) +{ + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; + NV_STATUS rmStatus = NV_OK; + OBJGPU *pTempGpu = NULL; + NvU8 mosaicReg, i; + NvU32 mosaicGroup = pParams->mosaicGroupNumber; + + if (mosaicGroup >= NV_P2060_MAX_MOSAIC_GROUPS) + { + NV_PRINTF(LEVEL_ERROR, + "mosaicGroup equaling/extending NV_P2060_MAX_MOSAIC_GROUPS.\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + if (pParams->slaveGpuCount > NV_P2060_MAX_MOSAIC_SLAVES) + { + NV_PRINTF(LEVEL_ERROR, + "mosaic slaveGpuCount extending NV_P2060_MAX_MOSAIC_SLAVES.\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + if (pParams->enableMosaic) { + + NvU32 index; + if (pThis->MosaicGroup[mosaicGroup].enabledMosaic) + { + // mosaic is already enabled for this group, + // client should disable it first and re-query for this group. + NV_PRINTF(LEVEL_ERROR, + "trying to enable mosaicGroup which is already enabled.\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + // Get Mosaic Timing Source GPU Connector Index. + if ( NV_OK != GetP2060ConnectorIndexFromGpu(pSourceGpu, pThis, &index)) + { + return NV_ERR_GENERIC; + } + + pThis->MosaicGroup[mosaicGroup].slaveGpuCount = pParams->slaveGpuCount; + pThis->MosaicGroup[mosaicGroup].gpuTimingSource = pThis->Iface[index].GpuInfo.gpuId; + + for (i = 0; i < pThis->MosaicGroup[mosaicGroup].slaveGpuCount; i++) + { + pThis->MosaicGroup[mosaicGroup].gpuTimingSlaves[i] = pParams->gpuTimingSlaves[i]; + + pTempGpu = gpumgrGetGpuFromId(pParams->gpuTimingSlaves[i]); + NV_ASSERT_OR_RETURN(pTempGpu, NV_ERR_GENERIC); + + // Update register of mosaic timing slaves first + mosaicReg = 0; + mosaicReg = FLD_SET_DRF_NUM(_P2060, _MOSAIC_MODE, _TS, (NvU8)index, mosaicReg); + mosaicReg = FLD_SET_DRF_NUM(_P2060, _MOSAIC_MODE, _GROUP, (NvU8)mosaicGroup, mosaicReg); + mosaicReg = FLD_SET_DRF(_P2060, _MOSAIC_MODE, _ENABLE, _TRUE, mosaicReg); + + rmStatus |= writeregu008_extdeviceTargeted(pTempGpu, + (PDACEXTERNALDEVICE)pThis, NV_P2060_MOSAIC_MODE, mosaicReg); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to write P2060 mosaic slave register.\n"); + return NV_ERR_GENERIC; + } + + // Set LSR_MIN_TIME + gsyncSetLsrMinTime(pTempGpu, pExtDev, pParams->enableMosaic); + } + + gsyncSetLsrMinTime(pSourceGpu, pExtDev, pParams->enableMosaic); + + // Update registers of mosaic timing source. + mosaicReg = 0; + mosaicReg = FLD_SET_DRF_NUM(_P2060, _MOSAIC_MODE, _TS, (NvU8)index, mosaicReg); + mosaicReg = FLD_SET_DRF_NUM(_P2060, _MOSAIC_MODE, _GROUP, (NvU8)mosaicGroup, mosaicReg); + mosaicReg = FLD_SET_DRF(_P2060, _MOSAIC_MODE, _ENABLE, _TRUE, mosaicReg); + + rmStatus |= writeregu008_extdeviceTargeted(pSourceGpu, + (PDACEXTERNALDEVICE)pThis, NV_P2060_MOSAIC_MODE, mosaicReg); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to write P2060 mosaic Source register.\n"); + return NV_ERR_GENERIC; + } + + // Mark as Mosaic enabled for specified group + pThis->MosaicGroup[mosaicGroup].enabledMosaic = NV_TRUE; + } + else + { + if (!pThis->MosaicGroup[mosaicGroup].enabledMosaic) + { + // mosaicgroup is not enabled, so can not disable + NV_PRINTF(LEVEL_ERROR, + "trying to disable mosaicGroup which is not enabled.\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + for (i = 0; i < pThis->MosaicGroup[mosaicGroup].slaveGpuCount; i++) + { + pTempGpu = gpumgrGetGpuFromId(pThis->MosaicGroup[mosaicGroup].gpuTimingSlaves[i]); + NV_ASSERT_OR_RETURN(pTempGpu, NV_ERR_GENERIC); + + rmStatus |= writeregu008_extdeviceTargeted(pTempGpu, + (PDACEXTERNALDEVICE)pThis, NV_P2060_MOSAIC_MODE, 0x00); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to write P2060 mosaic slave register.\n"); + return NV_ERR_GENERIC; + } + + // Reset LSR_MIN_TIME + gsyncSetLsrMinTime(pTempGpu, pExtDev, pParams->enableMosaic); + } + + gsyncSetLsrMinTime(pSourceGpu, pExtDev, pParams->enableMosaic); + + rmStatus |= writeregu008_extdeviceTargeted(pSourceGpu, + (PDACEXTERNALDEVICE)pThis, NV_P2060_MOSAIC_MODE, 0x00); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to write P2060 mosaic Source register.\n"); + return NV_ERR_GENERIC; + } + + // reset structure for specified group + gsyncResetMosaicData_P2060(mosaicGroup, pThis); + } + + return rmStatus; +} + +#ifdef DEBUG +/* + * Helper function to printout the most relevant P2060_status + * register informations in a human readable form. + */ +static void +DbgPrintP2060StatusRegister(NvU32 DebugLevel, NvU32 regStatus) +{ + if (DRF_VAL(_P2060, _STATUS, _SYNC_LOSS, regStatus)) + NV_PRINTF_EX(NV_PRINTF_MODULE, DebugLevel, "SYNC_LOSS "); + if (DRF_VAL(_P2060, _STATUS, _STEREO, regStatus)) + NV_PRINTF_EX(NV_PRINTF_MODULE, DebugLevel, "STEREO_LOCK "); + if (NV_P2060_STATUS_VCXO_LOCK == DRF_VAL(_P2060, _STATUS, _VCXO, regStatus)) + NV_PRINTF_EX(NV_PRINTF_MODULE, DebugLevel, "VCXO_LOCK "); + if (NV_P2060_STATUS_VCXO_NOLOCK_TOO_FAST == DRF_VAL(_P2060, _STATUS, _VCXO, regStatus)) + NV_PRINTF_EX(NV_PRINTF_MODULE, DebugLevel, "VCXO_NOLOCK_TOO_FAST "); + if (NV_P2060_STATUS_VCXO_NOLOCK_TOO_SLOW == DRF_VAL(_P2060, _STATUS, _VCXO, regStatus)) + NV_PRINTF_EX(NV_PRINTF_MODULE, DebugLevel, "VCXO_NOLOCK_TOO_SLOW "); + if (NV_P2060_STATUS_VCXO_NOT_SERVO == DRF_VAL(_P2060, _STATUS, _VCXO, regStatus)) + NV_PRINTF_EX(NV_PRINTF_MODULE, DebugLevel, "VCXO_NOT_SERVO "); +} +#else +#define DbgPrintP2060StatusRegister(DebugLevel, regStatus) +#endif + +static NV_STATUS +gsyncGpuStereoHeadSync(OBJGPU *pGpu, NvU32 iface, PDACEXTERNALDEVICE pExtDev, NvU32 status1) +{ + DACP2060EXTERNALDEVICE *pThis = (PDACP2060EXTERNALDEVICE)pExtDev; + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NvU32 hClient = pGpu->hInternalClient; + NvU32 hSubdevice = pGpu->hInternalSubdevice; + NV_STATUS status = NV_OK; + NvU32 numHeads = kdispGetNumHeads(pKernelDisplay); + NvU32 headIdx; + NV2080_CTRL_INTERNAL_GSYNC_SET_STREO_SYNC_PARAMS ctrlParams = {0}; + + for (headIdx = 0; headIdx < numHeads; headIdx++) + { + ctrlParams.slave[headIdx] = pThis->Iface[iface].Sync.Slaved[headIdx]; + ctrlParams.localSlave[headIdx] = pThis->Iface[iface].Sync.LocalSlave[headIdx]; + ctrlParams.master[headIdx] = pThis->Iface[iface].Sync.Master[headIdx]; + } + + ctrlParams.regStatus = status1; + status = pRmApi->Control(pRmApi, hClient, hSubdevice, + NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_STREO_SYNC, + &ctrlParams, sizeof(ctrlParams)); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Stereo headsync failed\n"); + } + + return status; +} + +/* + * Update the status register snapshot and + * send loss/gain events to client if any. + */ +static NV_STATUS +gsyncUpdateGsyncStatusSnapshot_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev +) +{ + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; + NvU32 iface; + NvU8 regStatus = 0; + NV_STATUS rmStatus = NV_OK; + NvU32 ifaceEvents[NV_P2060_MAX_IFACES_PER_GSYNC]; + + // Only read status variables if the board is framelocked at all. + if (!gsyncIsFrameLocked_P2060(pThis)) + { + return rmStatus; + } + + for (iface = 0; iface < NV_P2060_MAX_IFACES_PER_GSYNC; iface++) + { + NvU32 diffStatus = 0x00; + NvU32 oldStatus = 0x00; + NvU32 newStatus = 0x00; + ifaceEvents[iface] = 0x00; + + // get status update for each interface + if (pThis->Iface[iface].GpuInfo.gpuId != NV0000_CTRL_GPU_INVALID_ID) + { + int updateSnapshot = 1; + int localMaster = 0; + + // Take care of tracking state of connected gpu, not per incoming. + OBJGPU *pIfaceGpu = gpumgrGetGpuFromId(pThis->Iface[iface].GpuInfo.gpuId); + + NV_ASSERT(pIfaceGpu); + + rmStatus = readregu008_extdeviceTargeted(pIfaceGpu, pExtDev, (NvU8)NV_P2060_STATUS, ®Status); + if ( NV_OK != rmStatus ) + { + return NV_ERR_GENERIC; + } + + oldStatus = pThis->Snapshot[iface].Status1; + newStatus = (NvU32)regStatus; + + // Check for a local master which generates the sync so it's always synched. + if ( (NV_P2060_STATUS_VCXO_NOT_SERVO == DRF_VAL(_P2060, _STATUS, _VCXO, newStatus)) && + (NV_P2060_STATUS_SYNC_LOSS_FALSE == DRF_VAL(_P2060, _STATUS, _SYNC_LOSS, newStatus))) + { + localMaster = 1; + if (!pThis->Iface[iface].gainedSync) + { + NV_PRINTF(LEVEL_INFO, + "P2060[%d] is local master => GAINED SYNC\n", + iface); + pThis->Iface[iface].gainedSync = 1; + } + } + else + { + // For slaves or masters driven by housesync we need to wait for a sync. + + // 1st wait for syncgain before doing anything else. + if ((!pThis->Iface[iface].gainedSync) && + (NV_P2060_STATUS_VCXO_LOCK == DRF_VAL(_P2060, _STATUS, _VCXO, newStatus))) + { + OBJTMR *pTmr = GPU_GET_TIMER(pIfaceGpu); + NvU64 timeDiff; + NvU64 currentTime; + + // get the current time + currentTime = tmrGetTime_HAL(pIfaceGpu, pTmr); + + // + // Initialize waittime. + // We're using a threshold of 10 seconds before we're accepting sync gain. + // + if (0 == pThis->Snapshot[iface].lastSyncCheckTime) + { + pThis->Snapshot[iface].lastSyncCheckTime = currentTime; + } + + // calculate the time difference from last change. + timeDiff = ((currentTime - pThis->Snapshot[iface].lastSyncCheckTime) / 1000000); // time in ms + + NV_PRINTF(LEVEL_INFO, + "P2060[%d] snapshot timeDiff is %d ms\n", iface, + (NvU32)timeDiff); + + // + // Update settings if we got no lock or if lock has settled long enough. + // This is currently selected to 5 seconds by experiments with syncing + // with stereo enabled. + // + if (timeDiff >= 5000) + { + NV_PRINTF(LEVEL_INFO, "P2060[%d] GAINED SYNC\n", + iface); + + pThis->Iface[iface].gainedSync = 1; + + // We've gained sync, right time to also sync the stereo phase. + if (FLD_TEST_DRF(_P2060, _STATUS, _GPU_STEREO, _ACTIVE, newStatus)) + { + gsyncGpuStereoHeadSync(pIfaceGpu, iface, pExtDev, newStatus); + // Reset toggle time to wait some time before checking stereo sync again. + pThis->Snapshot[iface].lastStereoToggleTime = 0; + } + } + else + { + // + // We haven't reached the settle down time for a sync, + // so don't update the snapshot this time. + // + updateSnapshot = 0; + } + } + } + + // Take over new status and send events only if desired. + if (updateSnapshot) + { + // + // If we lost sync again reestablish syncwait mechanism. + // Local master can't loose sync per definition. + // + if ((NV_P2060_STATUS_VCXO_LOCK != DRF_VAL(_P2060, _STATUS, _VCXO, newStatus)) && + (!localMaster)) + { + pThis->Iface[iface].gainedSync = 0; + pThis->Snapshot[iface].lastSyncCheckTime = 0; + } + + NV_PRINTF(LEVEL_INFO, "Update P2060[%d] settled from 0x%x ( ", + iface, oldStatus); + DbgPrintP2060StatusRegister(LEVEL_INFO, oldStatus); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, ") to 0x%x ( ", newStatus); + DbgPrintP2060StatusRegister(LEVEL_INFO, newStatus); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, ")\n"); + + diffStatus = (oldStatus ^ newStatus); + + pThis->Snapshot[iface].Status1 = newStatus; + } + } + else + { + continue; + } + + if ((DRF_VAL(_P2060, _STATUS, _VCXO, diffStatus)) || + (DRF_VAL(_P2060, _STATUS, _SYNC_LOSS, diffStatus)) ) // diff state: sync or lock + { + if (FLD_TEST_DRF(_P2060, _STATUS, _SYNC_LOSS, _FALSE, newStatus) && + (FLD_TEST_DRF(_P2060, _STATUS, _VCXO, _LOCK, newStatus) || + FLD_TEST_DRF(_P2060, _STATUS, _VCXO, _NOT_SERVO, newStatus))) + { + ifaceEvents[iface] |= NVBIT(NV30F1_GSYNC_NOTIFIERS_SYNC_GAIN(iface)); + } + else + { + ifaceEvents[iface] |= NVBIT(NV30F1_GSYNC_NOTIFIERS_SYNC_LOSS(iface)); + } + } + + // Only track stereo diff states when we are VCXO locked or NOT SERVO. + if ((FLD_TEST_DRF(_P2060, _STATUS, _VCXO, _LOCK, newStatus) || + FLD_TEST_DRF(_P2060, _STATUS, _VCXO, _NOT_SERVO, newStatus)) && + DRF_VAL(_P2060, _STATUS, _STEREO, diffStatus)) // diff state: stereo + { + if (FLD_TEST_DRF(_P2060, _STATUS, _STEREO, _LOCK, newStatus)) + { + ifaceEvents[iface] |= NVBIT(NV30F1_GSYNC_NOTIFIERS_STEREO_GAIN(iface)); + } + else + { + ifaceEvents[iface] |= NVBIT(NV30F1_GSYNC_NOTIFIERS_STEREO_LOSS(iface)); + } + } + } + + for (iface = 0; iface < NV_P2060_MAX_IFACES_PER_GSYNC; iface++) + { + // Only check stereo phase if we've gained sync. + if (pThis->Iface[iface].gainedSync) + { + // Only check and adjust stereo phase if stereo is enabled on this system. + if (FLD_TEST_DRF(_P2060, _STATUS, _GPU_STEREO, _ACTIVE, pThis->Snapshot[iface].Status1)) + { + // + // gsyncGpuStereoHeadSync() works without any gsync board interaction + // with gpu register access only. In addition it will also sync heads + // which are not driving the stereo pin and can't be monitored by the + // gsync board. + // So don't look at the gsync stereolock status as this doesn't cover + // all heads. + // Take care of tracking state of connected gpu, not per incoming. + // + OBJGPU *pIfaceGpu = gpumgrGetGpuFromId(pThis->Iface[iface].GpuInfo.gpuId); + OBJTMR *pIfaceTmr; + NvU32 timeDiff; + NvU64 currentTime; + + NV_ASSERT(pIfaceGpu); + + pIfaceTmr = GPU_GET_TIMER(pIfaceGpu); + + currentTime = tmrGetTime_HAL(pIfaceGpu, pIfaceTmr); // get the current time + + if (pThis->Snapshot[iface].lastStereoToggleTime == 0) + { + pThis->Snapshot[iface].lastStereoToggleTime = currentTime; + } + timeDiff = (NvU32)((currentTime - pThis->Snapshot[iface].lastStereoToggleTime) / 1000000); // time in ms + + // toggle stereo if it is not locked more than 5 sec. + if (timeDiff >= 5000) + { + gsyncGpuStereoHeadSync(pIfaceGpu, iface, pExtDev, pThis->Snapshot[iface].Status1); + pThis->Snapshot[iface].lastStereoToggleTime = currentTime; + } + + // Only report stereo loss if stereo is not in phase. + if (!(FLD_TEST_DRF(_P2060, _STATUS, _STEREO, _LOCK, pThis->Snapshot[iface].Status1))) + { + ifaceEvents[iface] |= NVBIT(NV30F1_GSYNC_NOTIFIERS_STEREO_LOSS(iface)); // report loss this time. + } + } + } + } + + for (iface = 0; iface < NV_P2060_MAX_IFACES_PER_GSYNC; iface++) + { + if (ifaceEvents[iface] && (pThis->Iface[iface].lastEventNotified != ifaceEvents[iface])) + { + NV_PRINTF(LEVEL_INFO, "Event P2060[%d]: 0x%x (", iface, + ifaceEvents[iface]); + gsyncDbgPrintGsyncEvents(LEVEL_INFO, ifaceEvents[iface], iface); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, ")\n"); + + // notify clients that something has happened! + gsyncSignalServiceRequested(gsyncGetGsyncInstance(pGpu), ifaceEvents[iface], iface); + pThis->Iface[iface].lastEventNotified = ifaceEvents[iface]; + } + } + + return NV_OK; +} + + +/* + * Handle Get and Set queries related to signals. + */ +NV_STATUS +gsyncRefSignal_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + REFTYPE rType, + GSYNCSYNCSIGNAL Signal, + NvBool bRate, + NvU32 *pPresence +) +{ + NV_STATUS status = NV_OK; + NvU32 rate; + NvU32 value = 0; + NvU32 bMaster; // Is this Gsync in Master mode + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; + + if (!bRate) + { + return NV_OK; + } + + // + // Is any display on this P2060 a master, or are we using an ext + // sync to be master. + // + bMaster = !!gsyncReadMaster_P2060(pGpu, pThis); + + switch ( rType ) + { + case refFetchGet: + if (gsync_Signal_RJ45_0 == Signal || gsync_Signal_RJ45_1 == Signal) + { + // Relevant only if this port is an input + NvU32 port0Direction, expectedPort0Direction; + NvU32 port1Direction, expectedPort1Direction; + + status = gsyncReadFrameRate_P2060(pGpu, pExtDev, &rate); + if (NV_OK != status) + return status; + + status = readregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_STATUS2, (NvU8*)&value); + if (NV_OK != status) + return status; + + port0Direction = DRF_VAL(_P2060, _STATUS2, _PORT0, value); + port1Direction = DRF_VAL(_P2060, _STATUS2, _PORT1, value); + + if (gsync_Signal_RJ45_0 == Signal) + { + expectedPort0Direction = NV_P2060_STATUS2_PORT0_INPUT; + expectedPort1Direction = NV_P2060_STATUS2_PORT1_OUTPUT; + } + else + { + expectedPort0Direction = NV_P2060_STATUS2_PORT0_OUTPUT; + expectedPort1Direction = NV_P2060_STATUS2_PORT1_INPUT; + } + if (port0Direction == expectedPort0Direction && port1Direction == expectedPort1Direction) + { + if (bMaster) + { + *pPresence = ~0; + } + else + { + *pPresence = rate; + } + } + else + { + *pPresence = 0; + } + } + else if (gsync_Signal_House == Signal) + { + status = gsyncReadHouseSignalPresent_P2060(pGpu, pExtDev, NV_FALSE, &value); + + if (value && NV_OK == status) + { + status = gsyncReadHouseSyncFrameRate_P2060(pGpu, pExtDev, &rate); + if (NV_OK != status) + return status; + + if (bMaster) + { + *pPresence = rate; + } + else + { + *pPresence = ~0; + } + } + else + { + *pPresence = 0; + } + } + else + { + return NV_ERR_GENERIC; + } + break; + + case refRead: + break; + default: + return NV_ERR_GENERIC; + } + + return status; +} + +/* + * Handle Get and Set queries related to Master. + */ +NV_STATUS +gsyncRefMaster_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + REFTYPE rType, + NvU32 *pDisplayMask, + NvU32 *pRefresh, + NvBool retainMaster, + NvBool skipSwapBarrierWar +) +{ + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; + NvU32 Master = pThis->Master; + NvU32 RefreshRate = pThis->RefreshRate; + NV_STATUS status = NV_OK; + + switch ( rType ) + { + case refSetCommit: + if (!retainMaster) + { + Master = pThis->Master = *pDisplayMask; + } + RefreshRate = pThis->RefreshRate = *pRefresh; + break; + default: + break; + } + + switch ( rType ) + { + case refSetCommit: + // Only masterable gpus can be set to master, but either can be set to non-master. + if (Master && (!gsyncGpuCanBeMaster_P2060(pGpu, (PDACEXTERNALDEVICE)pThis))) + { + NV_PRINTF(LEVEL_INFO, "P2060 GPU can not be Framelock Master.\n"); + return NV_ERR_GENERIC; + } + + if (GpuIsMosaicTimingSlave(pGpu, pThis)) + { + NV_PRINTF(LEVEL_INFO, + "P2060 GPU is mosaic timing slave. Can not set Framelock Master.\n"); + return NV_ERR_GENERIC; + } + + status = gsyncProgramMaster_P2060(pGpu, pThis, Master, retainMaster, skipSwapBarrierWar); + break; + + case refFetchGet: + case refRead: + Master = gsyncReadMaster_P2060(pGpu, pThis); + break; + default: + break; + } + + switch ( rType ) + { + case refFetchGet: + pThis->Master = Master; + /*NOBREAK*/ + case refRead: + *pDisplayMask = Master; + *pRefresh = RefreshRate; + break; + + default: + break; + } + + return status; +} + +/* + * Handle Get and Set queries related to Slaves. + */ +NV_STATUS +gsyncRefSlaves_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + REFTYPE rType, + NvU32 *pDisplayMasks, + NvU32 *pRefresh +) +{ + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; + NV_STATUS status = NV_OK; + NvU32 Slaves = pThis->Slaves; + NvU32 RefreshRate = pThis->RefreshRate; + + switch ( rType ) + { + case refSetCommit: + pThis->Slaves = *pDisplayMasks; + pThis->RefreshRate = *pRefresh; + Slaves = pThis->Slaves; + RefreshRate = pThis->RefreshRate; + break; + default: + break; + } + + switch ( rType ) + { + case refSetCommit: + status = gsyncProgramSlaves_P2060(pGpu, pThis, Slaves); + break; + + case refFetchGet: + case refRead: + Slaves = gsyncReadSlaves_P2060(pGpu, pThis); + break; + default: + break; + } + + switch ( rType ) + { + case refFetchGet: + pThis->Slaves = Slaves; + /*NOBREAK*/ + case refRead: + *pDisplayMasks = Slaves; + *pRefresh = RefreshRate; + break; + + default: + break; + } + return status; +} + +/* + * Handle Get queries related to CPL status. + */ +NV_STATUS +gsyncGetCplStatus_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + GSYNCSTATUS CplStatus, + NvU32 *pVal +) +{ + NV_STATUS status = NV_OK; + NvU8 regStatus2; + + *pVal = 0; // A little safety for those that do not check return codes + + switch (CplStatus) + { + case gsync_Status_Refresh: + // Read GSYNC Framerate value. + status = gsyncReadFrameRate_P2060(pGpu, pExtDev, pVal); + break; + + case gsync_Status_HouseSyncIncoming: + *pVal = 0; + status = gsyncReadHouseSignalPresent_P2060(pGpu, pExtDev, NV_FALSE, pVal); + if (NV_OK == status && *pVal) + { + // Read HS Framerate value. + status = gsyncReadHouseSyncFrameRate_P2060(pGpu, pExtDev, pVal); + } + break; + + case gsync_Status_bSyncReady: + status = gsyncReadIsSyncDetected_P2060(pGpu, pExtDev, pVal); + break; + + case gsync_Status_bSwapReady: + *pVal = 0; // counters should exist in P2060? + break; + + case gsync_Status_bTiming: + status = gsyncReadIsTiming_P2060(pGpu, pExtDev, pVal); + break; + + case gsync_Status_bStereoSync: + status = gsyncReadStereoLocked_P2060(pGpu, pExtDev, pVal); + break; + + case gsync_Status_bHouseSync: + status = gsyncReadHouseSignalPresent_P2060(pGpu, pExtDev, NV_FALSE, pVal); + break; + + case gsync_Status_bPort0Input: + status = readregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_STATUS2, ®Status2); + if ( NV_OK == status ) + { + *pVal = FLD_TEST_DRF(_P2060, _STATUS2, _PORT0, _INPUT, (NvU32)regStatus2); + } + break; + + case gsync_Status_bPort1Input: + status = readregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_STATUS2, ®Status2); + if ( NV_OK == status ) + { + *pVal = FLD_TEST_DRF(_P2060, _STATUS2, _PORT1, _INPUT, (NvU32)regStatus2); + } + break; + + case gsync_Status_bPort0Ethernet: + status = readregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_STATUS2, ®Status2); + if ( NV_OK == status ) + { + *pVal = FLD_TEST_DRF(_P2060, _STATUS2, _ETHER0_DETECTED, _TRUE, (NvU32)regStatus2); + } + break; + + case gsync_Status_bPort1Ethernet: + status = readregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_STATUS2, ®Status2); + if ( NV_OK == status ) + { + *pVal = FLD_TEST_DRF(_P2060, _STATUS2, _ETHER1_DETECTED, _TRUE, (NvU32)regStatus2); + } + break; + + case gsync_Status_UniversalFrameCount: + status = gsyncReadUniversalFrameCount_P2060(pGpu, pExtDev, pVal); + break; + + default: + status = NV_ERR_GENERIC; + } + + return status; +} + +/* + * Handle Get and Set queries related to Watchdog. + */ +NV_STATUS +gsyncSetWatchdog_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 pVal +) +{ + OBJGPU *pTempGpu = NULL; + PDACP2060EXTERNALDEVICE pP2060 = (PDACP2060EXTERNALDEVICE)pExtDev; + NV_STATUS status = NV_OK; + + NV_ASSERT_OR_RETURN(pGpu && pP2060, NV_ERR_INVALID_DEVICE); + + if (pVal) + { + gsyncCancelWatchdog_P2060(pP2060); + pTempGpu = GetP2060WatchdogGpu(pGpu, pP2060); + + extdevScheduleWatchdog(pTempGpu, (PDACEXTERNALDEVICE)pP2060); + if (!gsyncIsOnlyFrameLockMaster_P2060(pP2060)) + { + pP2060->watchdogCountDownValue = NV_P2060_WATCHDOG_COUNT_DOWN_VALUE; + } + } + + return status; +} + +/* + * Handle Get and Set queries related to board revision. + */ +NV_STATUS +gsyncGetRevision_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + GSYNCCAPSPARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + NV_STATUS status = NV_OK; + DAC_EXTERNAL_DEVICES deviceId = pExtDev->deviceId; + DAC_EXTERNAL_DEVICE_REVS deviceRev = pExtDev->deviceRev; + + if (!pGpu) + { + return NV_ERR_GENERIC; // something more descriptive, perhaps? + } + + pParams->revId = (NvU32)pExtDev->revId; + pParams->boardId = (NvU32)deviceId; + pParams->revision = (NvU32)deviceRev; + pParams->extendedRevision = (NvU32)pExtDev->deviceExRev; + + if ((deviceRev != DAC_EXTERNAL_DEVICE_REV_NONE) && + (deviceId == DAC_EXTERNAL_DEVICE_P2060 || + deviceId == DAC_EXTERNAL_DEVICE_P2061)) + { + pParams->capFlags = NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_FREQ_ACCURACY_3DPS; + + if (!pSys->getProperty(pSys, PDB_PROP_SYS_IS_QSYNC_FW_REVISION_CHECK_DISABLED)) + { + pParams->isFirmwareRevMismatch = isFirmwareRevMismatch(pGpu, deviceRev); + } + else + { + pParams->isFirmwareRevMismatch = NV_FALSE; + } + + if (supportsLargeSyncSkew(pExtDev)) + { + pParams->maxSyncSkew = NV_P2060_SYNC_SKEW_MAX_UNITS_FULL_SUPPORT; + } + else + { + pParams->maxSyncSkew = NV_P2060_SYNC_SKEW_MAX_UNITS_LIMITED_SUPPORT; + } + + pParams->syncSkewResolution = NV_P2060_SYNC_SKEW_RESOLUTION; + pParams->maxStartDelay = NV_P2060_START_DELAY_MAX_UNITS; + pParams->startDelayResolution = NV_P2060_START_DELAY_RESOLUTION; + pParams->maxSyncInterval = NV_P2060_SYNC_INTERVAL_MAX_UNITS; + + // let client know which events we support + pParams->capFlags |= NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_SYNC_LOCK_EVENT; + pParams->capFlags |= NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_HOUSE_SYNC_EVENT; + + // all connectors are capable of generating events + pParams->capFlags |= NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_ALL_CONNECTOR_EVENT; + + // clients can only request (i.e. not SET) for video mode at BNC connector. + pParams->capFlags |= NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_ONLY_GET_VIDEO_MODE; + + // Fpga revisions <= 5 need to have the swapbarrier set on framelock masters + // to drive (pull up) the swap_rdy line of the whole framelock setup. + // This is a behaviour with unwanted side effects which needs drivers wars + // for certain configs. + if (needsMasterBarrierWar(pExtDev)) + { + pParams->capFlags |= NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_NEED_MASTER_BARRIER_WAR; + } + } + else + { + pParams->boardId = DAC_EXTERNAL_DEVICE_NONE; + } + + return status; +} + +/* + * Handle Get and Set queries related to Swap barrier. + */ +NV_STATUS +gsyncRefSwapBarrier_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + REFTYPE rType, + NvBool *bEnable +) +{ + NV_STATUS status = NV_OK; + + switch (rType) + { + case refSetCommit: + status = gsyncProgramSwapBarrier_P2060(pGpu, pExtDev, *bEnable); + break; + case refFetchGet: + case refRead: + status = gsyncReadSwapBarrier_P2060(pGpu, pExtDev, bEnable); + break; + default: + break; + } + + return status; +} + +/* + * Configure GSYNC registers for pre-flash and post-flash operations. + */ +NV_STATUS +gsyncConfigFlashGsync_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 preFlash +) +{ + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE) pExtDev; + NvU32 iface; + NV_STATUS rmStatus = NV_OK; + + if (preFlash) + { + if (pThis->isNonFramelockInterruptEnabled == NV_FALSE) + { + // Non-Framelock interrupts are already disabled. + return NV_OK; + } + + // Disable non-Framelock interrupts for given gpu + for (iface = 0; iface < NV_P2060_MAX_IFACES_PER_GSYNC; iface++) + { + if (pThis->Iface[iface].GpuInfo.gpuId != NV0000_CTRL_GPU_INVALID_ID && + pThis->interruptEnabledInterface == iface) + { + OBJGPU *pTmpGpu = gpumgrGetGpuFromId(pThis->Iface[iface].GpuInfo.gpuId); + + NV_ASSERT(pTmpGpu); + + rmStatus = gsyncDisableNonFramelockInterrupt_P2060(pTmpGpu, (PDACEXTERNALDEVICE)pThis); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to disable non-framelock interrupts on gsync GPU.\n"); + return rmStatus; + } + break; + } + } + pThis->isNonFramelockInterruptEnabled = NV_FALSE; + } + else + { + if (pThis->isNonFramelockInterruptEnabled == NV_FALSE) + { + // Enable non-Framelock interrupts for given gpu + rmStatus = GetP2060ConnectorIndexFromGpu(pGpu, pThis, &iface); + if (NV_OK != rmStatus) + { + NV_PRINTF(LEVEL_ERROR, + "failed to find P2060 connector of the GPU.\n"); + return rmStatus; + } + + rmStatus = gsyncEnableNonFramelockInterrupt_P2060(pGpu, (PDACEXTERNALDEVICE)pThis); + if (NV_OK != rmStatus) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to enable non-framelock interrupts on gsync GPU.\n"); + return rmStatus; + } + pThis->isNonFramelockInterruptEnabled = NV_TRUE; + pThis->interruptEnabledInterface = iface; + } + + // Program External Stereo Sync Polarity for all attached gpus. + for (iface = 0; iface < NV_P2060_MAX_IFACES_PER_GSYNC; iface++) + { + if (pThis->Iface[iface].GpuInfo.gpuId != NV0000_CTRL_GPU_INVALID_ID) + { + OBJGPU *pTmpGpu = gpumgrGetGpuFromId(pThis->Iface[iface].GpuInfo.gpuId); + + NV_ASSERT(pTmpGpu); + + rmStatus = gsyncProgramExtStereoPolarity_P2060(pTmpGpu, (PDACEXTERNALDEVICE)pThis); + if (NV_OK != rmStatus) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to Program External Stereo Polarity for GPU.\n"); + return rmStatus; + } + } + } + } + return rmStatus; +} + +/* + * Return snapshot of status1 register. + */ +static NvU32 +GetP2060GpuSnapshot +( + OBJGPU *pGpu, + PDACP2060EXTERNALDEVICE pThis +) +{ + NvU32 iface; + NV_STATUS status; + + status = GetP2060GpuLocation(pGpu, pThis, &iface); + if (NV_OK != status) + return 0; + + return pThis->Snapshot[iface].Status1; +} + +/* + * Return NV_TRUE if pGpu is Timing Source else return NV_FALSE. + */ +static NvBool +GpuIsP2060Master +( + OBJGPU *pGpu, + PDACP2060EXTERNALDEVICE pThis +) +{ + NvU8 regControl; + NvU32 index; + NvBool bIsMasterGpu; + NV_STATUS rmStatus; + + if (!pGpu || !GpuIsP2060Connected(pGpu, pThis)) + { + return NV_FALSE; + } + + // Get the connector index and check if it is master + if ( NV_OK != GetP2060ConnectorIndexFromGpu(pGpu, pThis, &index)) + { + return NV_FALSE; + } + + rmStatus = readregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE)pThis, (NvU8)NV_P2060_CONTROL, ®Control); + if (NV_OK != rmStatus) + { + return NV_FALSE; + } + + bIsMasterGpu = (DRF_VAL(_P2060, _CONTROL, _SYNC_SRC, (NvU32)regControl) == index); + return bIsMasterGpu; +} + +/* + * Return whether pGpu is connected to pThis or not. + */ +static NvBool +GpuIsP2060Connected +( + OBJGPU *pGpu, + PDACP2060EXTERNALDEVICE pThis +) +{ + NvU32 iface; + + if (NV_OK == GetP2060GpuLocation(pGpu, pThis, &iface)) + { + return pThis->Iface[iface].GpuInfo.connected; + } + + return NV_FALSE; +} + +/* + * Return Masterable(TS) Gpu for pthis. + */ +static OBJGPU* +GetP2060MasterableGpu +( + OBJGPU *pGpu, + PDACP2060EXTERNALDEVICE pThis +) +{ + OBJGPU *tempGpu; + NvU32 iface; + + for (iface = 0; iface < NV_P2060_MAX_IFACES_PER_GSYNC; iface++) + { + if (pThis->Iface[iface].GpuInfo.gpuId != NV0000_CTRL_GPU_INVALID_ID) + { + tempGpu = gpumgrGetGpuFromId(pThis->Iface[iface].GpuInfo.gpuId); + + NV_ASSERT(tempGpu); + + if (gsyncGpuCanBeMaster_P2060(tempGpu, (PDACEXTERNALDEVICE)pThis)) + { + return tempGpu; + } + } + } + + return NULL; +} + +/* + * Return connector index for given pGpu. + */ +static NV_STATUS +GetP2060ConnectorIndexFromGpu +( + OBJGPU *pGpu, + PDACP2060EXTERNALDEVICE pThis, + NvU32 *index +) +{ + NV_STATUS rmStatus = NV_OK; + NvU8 regStatus2; + + rmStatus = readregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE)pThis, (NvU8)NV_P2060_STATUS2, ®Status2); + if (NV_OK == rmStatus) + { + *index = DRF_VAL(_P2060, _STATUS2, _GPU_PORT, (NvU32)regStatus2); + } + + return rmStatus; +} + +/* + * Return location of pGpu attached to P2060. + */ +static NV_STATUS +GetP2060GpuLocation +( + OBJGPU *pGpu, + PDACP2060EXTERNALDEVICE pThis, + NvU32 *iface +) +{ + NvU32 tempIface; + + for (tempIface = 0; tempIface < NV_P2060_MAX_IFACES_PER_GSYNC; tempIface++) + { + if (pThis->Iface[tempIface].GpuInfo.gpuId == pGpu->gpuId) + { + *iface = tempIface; + + return NV_OK; + } + } + + return NV_ERR_GENERIC; +} + +static void +gsyncProgramFramelockEnable_P2060 +( + OBJGPU *pGpu, + PDACP2060EXTERNALDEVICE pThis, + NvU32 iface, + NvBool bEnable +) +{ + // + // Key here is to force the status register snapshot + // to unsynched and setting back the timeout for + // syncgain. To ensure that the eventhandling won't + // filter away any gain, send a syncloss event. + // also track overall framelock state (on off) now. + // + NV_PRINTF(LEVEL_INFO, + "P2060[%d]:%s snapshot reset to _SYNC_LOSS_TRUE _VCXO_NOT_SERVO _STEREO_NOLOCK\n", + iface, bEnable ? "ON" : "OFF"); + + pThis->Snapshot[iface].Status1 = + DRF_DEF(_P2060, _STATUS, _SYNC_LOSS, _TRUE) | + DRF_DEF(_P2060, _STATUS, _VCXO, _NOT_SERVO) | + DRF_DEF(_P2060, _STATUS, _STEREO, _NOLOCK); + + pThis->Snapshot[iface].lastStereoToggleTime = 0; + + // Also reload delayed updates. + pThis->Snapshot[iface].lastSyncCheckTime = 0; + + // We will waiting for a syncgain. + pThis->Iface[iface].gainedSync = 0; + + if (bEnable) + { + gsyncSignalServiceRequested(gsyncGetGsyncInstance(pGpu), + NVBIT(NV30F1_GSYNC_NOTIFIERS_SYNC_LOSS(iface)), iface); + pThis->Iface[iface].lastEventNotified = + NVBIT(NV30F1_GSYNC_NOTIFIERS_SYNC_LOSS(iface)); + } +} + +static NvBool +GpuIsMosaicTimingSlave +( + OBJGPU *pGpu, + PDACP2060EXTERNALDEVICE pThis +) +{ + OBJGPU *pTempGpu = NULL; + NvU8 i, j; + + for (i = 0; i < NV_P2060_MAX_MOSAIC_GROUPS; i++) + { + if (pThis->MosaicGroup[i].enabledMosaic) + { + for (j = 0; j < NV_P2060_MAX_MOSAIC_SLAVES; j++) + { + pTempGpu = gpumgrGetGpuFromId(pThis->MosaicGroup[i].gpuTimingSlaves[j]); + NV_ASSERT(pTempGpu); + + if (pTempGpu == pGpu) + { + return NV_TRUE; + } + } + } + } + return NV_FALSE; +} + +/* + * Return NV_TRUE if pGpu can be master(TS) i.e. no other pGpu + * attached to pThis is master. + */ +NvBool +gsyncGpuCanBeMaster_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev +) +{ + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; + OBJGPU *pTempGpu; + NvU32 iface, tempIface; + NV_STATUS status; + + // If FPGA board in not master, Any GPU attached to board can be master. + if (!gsyncIsP2060MasterBoard(pGpu, pThis)) + { + return NV_TRUE; + } + + // Board is master, only TS GPU will be master. + status = GetP2060GpuLocation(pGpu, pThis, &iface); + if (NV_OK != status) + { + return NV_FALSE; + } + + for (tempIface = 0; tempIface < NV_P2060_MAX_IFACES_PER_GSYNC; tempIface++) + { + if (tempIface == iface) + { + continue; + } + + if (pThis->Iface[tempIface].GpuInfo.gpuId == NV0000_CTRL_GPU_INVALID_ID) + { + continue; + } + + pTempGpu = gpumgrGetGpuFromId(pThis->Iface[tempIface].GpuInfo.gpuId); + + NV_ASSERT(pTempGpu); + + if (GpuIsP2060Master(pTempGpu, pThis)) + { + return NV_FALSE; + } + } + + return NV_TRUE; +} + + +static POBJGPU +GetP2060Gpu +( + OBJGPU *pGpu, + PDACP2060EXTERNALDEVICE pThis +) +{ + NvU32 iface; + for (iface = 0; iface < NV_P2060_MAX_IFACES_PER_GSYNC; iface++) + { + if (pThis->Iface[iface].GpuInfo.gpuId != NV0000_CTRL_GPU_INVALID_ID) + { + OBJGPU *pTmpGpu = gpumgrGetGpuFromId(pThis->Iface[iface].GpuInfo.gpuId); + + NV_ASSERT(pTmpGpu); + + return pTmpGpu; + } + } + return NULL; +} + +static OBJGPU* +GetP2060WatchdogGpu +( + OBJGPU *pGpu, + PDACP2060EXTERNALDEVICE pThis +) +{ + return GetP2060Gpu(pGpu, pThis); +} + +/* + * Return NV_TRUE if either GPU stereo or MASTER stereo or + * both are enabled else return NV_FALSE. + */ +static NvBool +gsyncIsStereoEnabled_p2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev +) +{ + NvU8 regStatus; + NV_STATUS rmStatus; + + rmStatus = readregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2060_STATUS, ®Status); + + if (rmStatus == NV_OK) + { + if (FLD_TEST_DRF(_P2060, _STATUS, _GPU_STEREO, _ACTIVE, regStatus) || + FLD_TEST_DRF(_P2060, _STATUS, _MSTR_STEREO, _ACTIVE, regStatus)) + { + // stereo is enabled on the client or the server or both + return NV_TRUE; + } + } + return NV_FALSE; +} + +/* + * Cancel the Watchdog for P2060. + */ +static void +gsyncCancelWatchdog_P2060 +( + PDACP2060EXTERNALDEVICE pThis +) +{ + NvU32 iface; + OBJGPU *pTempGpu = NULL; + + pThis->watchdogCountDownValue = 0; + + // Cancel callbacks on all gpus + for (iface = 0; iface < NV_P2060_MAX_IFACES_PER_GSYNC; iface++) + { + if (pThis->Iface[iface].GpuInfo.gpuId == NV0000_CTRL_GPU_INVALID_ID) + continue; + + pTempGpu = gpumgrGetGpuFromId(pThis->Iface[iface].GpuInfo.gpuId); + NV_ASSERT(pTempGpu); + + NV_PRINTF(LEVEL_INFO, "P2060[%d] extdevCancelWatchdog.\n", iface); + + extdevCancelWatchdog(pTempGpu, (PDACEXTERNALDEVICE)pThis); + } + + return; +} + +/* + * Enable FrameLock Interrupts for P2060. + */ +static NV_STATUS +gsyncEnableFramelockInterrupt_P2060 +( + PDACEXTERNALDEVICE pExtDev +) +{ + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE) pExtDev; + NvU8 regCtrl3; + NvU32 iface; + NV_STATUS status = NV_OK; + + // Turn ON the interrupts + for (iface = 0; iface < NV_P2060_MAX_IFACES_PER_GSYNC; iface++) + { + if (pThis->Iface[iface].GpuInfo.gpuId != NV0000_CTRL_GPU_INVALID_ID) + { + OBJGPU *pTmpGpu = gpumgrGetGpuFromId(pThis->Iface[iface].GpuInfo.gpuId); + NV_ASSERT(pTmpGpu); + + if (gsyncReadMaster_P2060(pTmpGpu, pThis) || gsyncReadSlaves_P2060(pTmpGpu, pThis)) + { + status = readregu008_extdeviceTargeted(pTmpGpu, + (PDACEXTERNALDEVICE)pThis, NV_P2060_CONTROL3, ®Ctrl3); + + if (gsyncIsStereoEnabled_p2060(pTmpGpu, pExtDev)) + { + regCtrl3 |= DRF_DEF(_P2060, _CONTROL3, _INTERRUPT, _ON_STEREO_CHG); + } + regCtrl3 |= DRF_DEF(_P2060, _CONTROL3, _INTERRUPT, _ON_SYNC_CHG); + + status |= writeregu008_extdeviceTargeted(pTmpGpu, + (PDACEXTERNALDEVICE)pThis, NV_P2060_CONTROL3, regCtrl3); + + NV_PRINTF(LEVEL_INFO, "P2060[%d] enabled interrupt\n", iface); + } + } + } + return status; +} + +/* + * Disable FrameLock Interrupts for P2060. + */ +static NV_STATUS +gsyncDisableFrameLockInterrupt_P2060 +( + PDACEXTERNALDEVICE pExtDev +) +{ + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE) pExtDev; + NvU8 regCtrl3; + NvU32 iface; + NV_STATUS status = NV_OK; + + // Turn Off the interrupts + for (iface = 0; iface < NV_P2060_MAX_IFACES_PER_GSYNC; iface++) + { + if (pThis->Iface[iface].GpuInfo.gpuId != NV0000_CTRL_GPU_INVALID_ID) + { + OBJGPU *pTmpGpu = gpumgrGetGpuFromId(pThis->Iface[iface].GpuInfo.gpuId); + + NV_ASSERT(pTmpGpu); + + status = readregu008_extdeviceTargeted(pTmpGpu, + (PDACEXTERNALDEVICE)pThis, NV_P2060_CONTROL3, ®Ctrl3); + + regCtrl3 &= ~DRF_DEF(_P2060, _CONTROL3, _INTERRUPT, _ON_STEREO_CHG); + regCtrl3 &= ~DRF_DEF(_P2060, _CONTROL3, _INTERRUPT, _ON_SYNC_CHG); + + status |= writeregu008_extdeviceTargeted(pTmpGpu, + (PDACEXTERNALDEVICE)pThis, NV_P2060_CONTROL3, regCtrl3); + + NV_PRINTF(LEVEL_INFO, "P2060[%d] disabled interrupt\n", iface); + } + } + + return status; +} + +/* + * Enable Non-FrameLock Interrupts for P2060. + */ +static NV_STATUS +gsyncEnableNonFramelockInterrupt_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev +) +{ + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE) pExtDev; + NvU8 regCtrl3 = 0x00; + NV_STATUS rmStatus = NV_OK; + + rmStatus = readregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE)pThis, NV_P2060_CONTROL3, ®Ctrl3); + + // Enable Non-Framelock interrupts on given gsync attached gpu. + regCtrl3 |= DRF_DEF(_P2060, _CONTROL3, _INTERRUPT, _ON_HS_CHG); + regCtrl3 |= DRF_DEF(_P2060, _CONTROL3, _INTERRUPT, _ON_RJ45_CHG); + + rmStatus = writeregu008_extdeviceTargeted(pGpu,(PDACEXTERNALDEVICE)pThis, NV_P2060_CONTROL3, regCtrl3); + + return rmStatus; +} + +/* + * Disable Non-FrameLock Interrupts for P2060. + */ +static NV_STATUS +gsyncDisableNonFramelockInterrupt_P2060 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev +) +{ + PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE) pExtDev; + NvU8 regCtrl3 = 0x00; + NV_STATUS rmStatus = NV_OK; + + rmStatus = readregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE)pThis, NV_P2060_CONTROL3, ®Ctrl3); + + // Disable Non-Framelock interrupts on given gsync attached gpu. + regCtrl3 &= ~DRF_DEF(_P2060, _CONTROL3, _INTERRUPT, _ON_HS_CHG); + regCtrl3 &= ~DRF_DEF(_P2060, _CONTROL3, _INTERRUPT, _ON_RJ45_CHG); + + rmStatus = writeregu008_extdeviceTargeted(pGpu,(PDACEXTERNALDEVICE)pThis, NV_P2060_CONTROL3, regCtrl3); + + return rmStatus; +} + +static void +gsyncResetMosaicData_P2060 +( + NvU32 mosaicGroup, + PDACP2060EXTERNALDEVICE pThis +) +{ + NvU8 i; + + if (!pThis) + { + return; + } + + pThis->MosaicGroup[mosaicGroup].gpuTimingSource = NV0000_CTRL_GPU_INVALID_ID; + + for (i = 0; i < NV_P2060_MAX_MOSAIC_SLAVES; i++) + { + pThis->MosaicGroup[mosaicGroup].gpuTimingSlaves[i] = NV0000_CTRL_GPU_INVALID_ID; + } + + pThis->MosaicGroup[mosaicGroup].slaveGpuCount = 0; + pThis->MosaicGroup[mosaicGroup].enabledMosaic = NV_FALSE; + +} + +/* + * Enable/Disable SwapRdy Connection For GPU + */ +static NV_STATUS +gsyncUpdateSwapRdyConnectionForGpu_P2060 +( + OBJGPU *pGpu, + PDACP2060EXTERNALDEVICE pThis, + NvBool bEnable +) +{ + NV_STATUS rmStatus = NV_OK; + NvU8 ctrl2 = 0x00; + + rmStatus = readregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE)pThis, + NV_P2060_CONTROL2, &ctrl2); + if (rmStatus != NV_OK) + { + return rmStatus; + } + + ctrl2 = FLD_SET_DRF_NUM(_P2060, _CONTROL2, _SWAP_READY, (NvU8)bEnable, ctrl2); + + rmStatus = writeregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE)pThis, + NV_P2060_CONTROL2, ctrl2); + + return rmStatus; +} + +/* + * returns true if there is a framelock master on this P2060. + * otherwise returns false. + */ +static NvBool +gsyncIsFrameLockMaster_P2060 +( + PDACP2060EXTERNALDEVICE pThis +) +{ + NvU32 iface; + + for (iface = 0; iface < NV_P2060_MAX_IFACES_PER_GSYNC; iface++) + { + if (pThis->Iface[iface].GpuInfo.gpuId != NV0000_CTRL_GPU_INVALID_ID) + { + OBJGPU *pTmpGpu = gpumgrGetGpuFromId(pThis->Iface[iface].GpuInfo.gpuId); + + NV_ASSERT(pTmpGpu); + + if (gsyncReadMaster_P2060(pTmpGpu, pThis)) + { + return NV_TRUE; + } + } + } + + return NV_FALSE; +} + +/* + * returns NV_TRUE if this gsync device is framelocked. + */ +static NvBool +gsyncIsFrameLocked_P2060 +( + PDACP2060EXTERNALDEVICE pThis +) +{ + NvU32 iface; + + for (iface = 0; iface < NV_P2060_MAX_IFACES_PER_GSYNC; iface++) + { + if (pThis->Iface[iface].GpuInfo.gpuId != NV0000_CTRL_GPU_INVALID_ID) + { + OBJGPU *pTmpGpu = gpumgrGetGpuFromId(pThis->Iface[iface].GpuInfo.gpuId); + NV_ASSERT(pTmpGpu); + + if (gsyncReadMaster_P2060(pTmpGpu, pThis) || + gsyncReadSlaves_P2060(pTmpGpu, pThis)) + { + return NV_TRUE; + } + } + } + + return NV_FALSE; +} + +/* + * returns NV_TRUE if this gsync device is only framelock master. + */ +static NvBool +gsyncIsOnlyFrameLockMaster_P2060 +( + PDACP2060EXTERNALDEVICE pThis +) +{ + NvU32 iface, numHeads, head; + KernelDisplay *pKernelDisplay; + OBJGPU *pGpu; + NvBool bIsMaster = NV_FALSE; + + for (iface = 0; iface < NV_P2060_MAX_IFACES_PER_GSYNC; iface++) + { + if (pThis->Iface[iface].GpuInfo.gpuId != NV0000_CTRL_GPU_INVALID_ID) + { + pGpu = gpumgrGetGpuFromId(pThis->Iface[iface].GpuInfo.gpuId); + NV_ASSERT_OR_RETURN(pGpu, NV_FALSE); + + pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + numHeads = kdispGetNumHeads(pKernelDisplay); + + for (head = 0; head < numHeads; head++) + { + if (pThis->Iface[iface].Sync.Master[head]) + bIsMaster = NV_TRUE; + + if (pThis->Iface[iface].Sync.Slaved[head] || + pThis->Iface[iface].Sync.LocalSlave[head]) + { + return NV_FALSE; + } + } + } + } + + return bIsMaster; +} + +/* + * return NV_TRUE if HW is OK with board as Framelock Master. + */ +static NvBool +gsyncIsP2060MasterBoard +( + OBJGPU *pGpu, + PDACP2060EXTERNALDEVICE pThis +) +{ + NvU8 ctrl; + NvBool bIsMasterBoard; + NV_STATUS rmStatus; + + if (!pGpu || !GpuIsP2060Connected(pGpu, pThis)) + { + return NV_FALSE; + } + + rmStatus = readregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE)pThis, (NvU8)NV_P2060_CONTROL, &ctrl); + if (NV_OK != rmStatus) + { + return NV_FALSE; + } + + // Check HW opinion on Mastership of board. + bIsMasterBoard = FLD_TEST_DRF(_P2060, _CONTROL, _I_AM, _MASTER, (NvU32)ctrl); + + return bIsMasterBoard; +} +/* + * return NV_TRUE if pGpu is connected to Master + TS GPU via SLI bridge + */ +static NvBool +GpuIsConnectedToMasterViaBridge +( + OBJGPU *pGpu, + PDACP2060EXTERNALDEVICE pThis +) +{ + OBJGPU *pOtherGpu = NULL; + NvU32 gpuMask, gpuIndex, tempIface; + NvU32 drOut, drIn; + + gpumgrGetGpuAttachInfo(NULL, &gpuMask); + gpuIndex = 0; + while ((pOtherGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex)) != NULL) + { + if ((pGpu == pOtherGpu) || gpumgrGetGpuLockAndDrPorts(pGpu, pOtherGpu, &drOut, &drIn) != NV_OK) + { + continue; + } + + if (GetP2060GpuLocation(pOtherGpu, pThis, &tempIface) == NV_OK) + { + if (gsyncIsP2060MasterBoard(pOtherGpu, pThis) && GpuIsP2060Master(pOtherGpu, pThis)) + { + // pGpu is connected to pOtherGpu via SLI bridge. + // Both GPUs are connected to same P2060. + return NV_TRUE; + } + } + } + return NV_FALSE; +} + +// +// gsyncFrameCountTimerService_P2060() +// +// frame count timer callback service. +// this function will read the actual gsync and gpu frame count value +// and adjust the cached difference between them if required. +// +// this function is added to prevent any deviation of cached difference +// between gpu and gsync hw frame count values from the actual. +// As all the heads are framelocked, it is expected that cached +// framecount value to be same on the master as well as slave +// system. But during experiment, it is found that reading the hw gsync and +// gpu frame count values immediately after the test signal is sent/received +// may lead to inconsistent cached difference. Therefore the difference is +// reverified after FRAME_COUNT_TIMER_INTERVAL period. +// +static +NV_STATUS gsyncFrameCountTimerService_P2060 +( + OBJGPU *pGpu, + OBJTMR *pTmr, + void *pComponent +) +{ + PDACP2060EXTERNALDEVICE pThis = NULL; + NV_STATUS status; + OBJGSYNC *pGsync = NULL; + + pGsync = gsyncmgrGetGsync(pGpu); + + NV_ASSERT_OR_RETURN((pGsync && pGsync->pExtDev), NV_ERR_INVALID_DEVICE); + + pThis = (PDACP2060EXTERNALDEVICE)pGsync->pExtDev; + + // disable the timer callback + status = tmrCancelCallback(pTmr, (void *)&pThis->FrameCountData); + + if (status != NV_OK) + { + return status; + } + + // + // read the gsync and gpu frame count values.Cache the difference between them. + // + status = gsyncUpdateFrameCount_P2060(pThis, pGpu); + + return status; +} +/* + * Reset the FrameCount Data structure. + */ +// +// gsyncResetFrameCountData_P2060() +// +// this function resets the FrameCountDate structure. +// +static NV_STATUS +gsyncResetFrameCountData_P2060 +( + OBJGPU *pGpu, + PDACP2060EXTERNALDEVICE pThis +) +{ + + NvU8 regCtrl3; + NV_STATUS rmStatus; + + if (!pThis) + { + return NV_ERR_INVALID_ARGUMENT; + } + + pThis->FrameCountData.totalFrameCount = 0; + pThis->FrameCountData.currentFrameCount = 0; + pThis->FrameCountData.initialDifference = 0; + pThis->FrameCountData.numberOfRollbacks = 0; + pThis->FrameCountData.previousFrameCount = 0; + pThis->FrameCountData.lastFrameCounterQueryTime = 0; + pThis->FrameCountData.bReCheck = 0; + pThis->FrameCountData.vActive = 0; + pThis->FrameCountData.isFrmCmpMatchIntMasterEnabled = NV_FALSE; + pThis->FrameCountData.enableFrmCmpMatchIntSlave = NV_FALSE; + pThis->FrameCountData.head = NV_P2060_MAX_HEADS_PER_GPU; + pThis->FrameCountData.iface = NV_P2060_MAX_IFACES_PER_GSYNC; + + // disable frame count match interrupt + rmStatus = readregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE)pThis, + NV_P2060_CONTROL3, ®Ctrl3); + regCtrl3 &= ~DRF_DEF(_P2060, _CONTROL3, _INTERRUPT, _ON_FRAME_MATCH); + rmStatus |= writeregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE)pThis, + NV_P2060_CONTROL3, regCtrl3); + return rmStatus; +} + +// +// gsyncUpdateFrameCount_P2060() +// +// For all heads in a framelocked state gpu framecount is equal.This also +// implies for gsync frame count.i.e. gsync frame count = (gpu frame count + difference) +// Therefore to reduce the i2c reads to access gsync frame count, +// (gpu frame count + difference) can be returned. This is done by caching the +// difference between the gpu and gsync framecount. +// +// FrameCountTimerService (1 second callback) is also enabled here to verify +// the cache difference. +// +static NV_STATUS +gsyncUpdateFrameCount_P2060 +( + PDACP2060EXTERNALDEVICE pThis, + OBJGPU *pGpu +) +{ + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + RM_API *pRmApi; + NvU32 hClient; + NvU32 hSubdevice; + NvU8 FrameCountLow; + NvU8 FrameCountMid; + NvU8 FrameCountHigh; + NvU8 regCtrl3; + NvU32 rawGsyncFrameCount; + NvU32 iface; + NvU32 head = 0; + NvU32 numHeads; + NvU32 modGsyncFrameCount; + NvU32 lineCount; + NvU32 frameCount; + RMTIMEOUT timeout; + NvU32 safeRegionUpperLimit; + NvU32 safeRegionLowerLimit; + NV_STATUS rmStatus = NV_OK; + NV2080_CTRL_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES_PARAMS ctrlParams = {0}; + + numHeads = kdispGetNumHeads(pKernelDisplay); + + // get any framelocked head + for (iface = 0; iface < NV_P2060_MAX_IFACES_PER_GSYNC; iface++) + { + if (pThis->Iface[iface].GpuInfo.gpuId == NV0000_CTRL_GPU_INVALID_ID) + { + continue; + } + + for (head = 0; head < numHeads; head++) + { + if (pThis->Iface[iface].Sync.Master[head] || + pThis->Iface[iface].Sync.Slaved[head] || + pThis->Iface[iface].Sync.LocalSlave[head]) + { + // Update pThis->FrameCountData with iface and head + pThis->FrameCountData.iface = iface; + pThis->FrameCountData.head = head; + + // Get out of for loop + iface = NV_P2060_MAX_IFACES_PER_GSYNC; + break; + } + } + } + + if (head == numHeads) + { + return NV_ERR_GENERIC; + } + + pGpu = gpumgrGetGpuFromId(pThis->Iface[pThis->FrameCountData.iface].GpuInfo.gpuId); + NV_ASSERT_OR_RETURN(pGpu, NV_ERR_INVALID_DEVICE); + + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + hClient = pGpu->hInternalClient; + hSubdevice = pGpu->hInternalSubdevice; + + // Re-fetch pDisp as pGpu might have changed. + pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + NV_ASSERT_OR_RETURN(pKernelDisplay != NULL, NV_ERR_INVALID_DEVICE); + NV_ASSERT_OR_RETURN(head < kdispGetNumHeads(pKernelDisplay), NV_ERR_INVALID_DEVICE); + + ctrlParams.headIdx = head; + + rmStatus = pRmApi->Control(pRmApi, hClient, hSubdevice, + NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_VERTICAL_ACTIVE_LINES, + &ctrlParams, sizeof(ctrlParams)); + + if (rmStatus != NV_OK) + { + return rmStatus; + } + + pThis->FrameCountData.vActive = ctrlParams.vActiveLines; + + // + // To read Gpu framecount, line count should be in between 5-70% of VVisible. + // + safeRegionUpperLimit = (pThis->FrameCountData.vActive * 7) / 10; + safeRegionLowerLimit = pThis->FrameCountData.vActive / 20; + + // Read the GPU frame count and line count + rmStatus = kdispReadRgLineCountAndFrameCount_HAL(pGpu, pKernelDisplay, + pThis->FrameCountData.head, &lineCount, &frameCount); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to read RG_DPCA.\n"); + return rmStatus; + } + + // + // Wait for a safe region i.e. 5-70 percent of the VActive. Then read the + // gsync framecount. This is done to ensure that both gsync and gpu + // registers are read in the safe zone otherwise there will be -/+ 1 + // frame inconsistency ( if read during the transition from frame N to + // frame N + 1 i.e linecount > vActive) + // + if ((lineCount >= safeRegionUpperLimit) || (lineCount <= safeRegionLowerLimit)) + { + // + // timeout of one frameTime(in nano seconds), to avoid going into an infinite + // loop in case linecount is stuck to some value. + // + gpuSetTimeout(pGpu, (pThis->FrameCountData.frameTime * 1000), &timeout, 0); + + // Read the linecount until we are in the safe region i.e taken as 5%-70% of VActive. + while (((lineCount >= safeRegionUpperLimit) || (lineCount <= safeRegionLowerLimit)) && + (gpuCheckTimeout(pGpu, &timeout) != NV_ERR_TIMEOUT)) + { + rmStatus = kdispReadRgLineCountAndFrameCount_HAL(pGpu, pKernelDisplay, + pThis->FrameCountData.head, &lineCount, &frameCount); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to read RG_DPCA.\n"); + return rmStatus; + } + } + + if ((lineCount >= safeRegionUpperLimit) || (lineCount <= safeRegionLowerLimit)) + { + return NV_ERR_TIMEOUT; + } + } + + rmStatus |= readregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE) pThis, (NvU8)NV_P2060_FRAMECNTR_LOW, &FrameCountLow); + rmStatus |= readregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE) pThis, (NvU8)NV_P2060_FRAMECNTR_MID, &FrameCountMid); + rmStatus |= readregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE) pThis, (NvU8)NV_P2060_FRAMECNTR_HIGH, &FrameCountHigh); + + if (rmStatus != NV_OK) + { + return rmStatus; + } + + rawGsyncFrameCount = ( + ((((NvU32)FrameCountHigh) & DRF_MASK(NV_P2060_FRAMECNTR_HIGH_VAL))<< 16 ) | + ((((NvU32)FrameCountMid) & DRF_MASK(NV_P2060_FRAMECNTR_MID_VAL)) << 8 ) | + ((((NvU32)FrameCountLow) & DRF_MASK(NV_P2060_FRAMECNTR_LOW_VAL)))); + + pThis->FrameCountData.currentFrameCount = frameCount; + + // + // Gsync frame count is 24 bit register whereas Gpu frame count register is 16 bit. + // Therefore number of rollovers of Gpu frame count register is required. + // Else gsync frame count and (gpu frame count + difference) can be off by (2^16*N). + // where maximum value of N can be 256. << gsync frame count 2^24 = 256* 2^16. + // + pThis->FrameCountData.numberOfRollbacks = gsyncGetNumberOfGpuFrameCountRollbacks_P2060(rawGsyncFrameCount, 0, 256); + modGsyncFrameCount = rawGsyncFrameCount - (pThis->FrameCountData.numberOfRollbacks * (NV_P2060_MAX_GPU_FRAME_COUNT + 1)); + pThis->FrameCountData.initialDifference = modGsyncFrameCount - pThis->FrameCountData.currentFrameCount; + pThis->FrameCountData.previousFrameCount = 0; + + pThis->FrameCountData.totalFrameCount = pThis->FrameCountData.currentFrameCount + + pThis->FrameCountData.initialDifference + + pThis->FrameCountData.numberOfRollbacks * (NV_P2060_MAX_GPU_FRAME_COUNT + 1); + + if (pThis->FrameCountData.enableFrmCmpMatchIntSlave) + { + pThis->FrameCountData.enableFrmCmpMatchIntSlave = NV_FALSE; + + // enable frame count match interrupt + rmStatus |= readregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE)pThis, + NV_P2060_CONTROL3, ®Ctrl3); + + if (rmStatus == NV_OK) + { + regCtrl3 |= DRF_DEF(_P2060, _CONTROL3, _INTERRUPT, _ON_FRAME_MATCH); + rmStatus = writeregu008_extdeviceTargeted(pGpu, (PDACEXTERNALDEVICE)pThis, + NV_P2060_CONTROL3, regCtrl3); + } + } + + // + // Schedule 1 second timer callback, to verify initialDifference. + // + if (pThis->FrameCountData.bReCheck) + { + + NV_STATUS status = NV_OK; + OBJTMR *pTmr = GPU_GET_TIMER(pGpu); + + status = tmrScheduleCallbackRel( + pTmr, + gsyncFrameCountTimerService_P2060, + (void *)&pThis->FrameCountData, + (NV_P2060_FRAME_COUNT_TIMER_INTERVAL / 5), + TMR_FLAG_RECUR, + 0); + + if (status == NV_OK) + { + pThis->FrameCountData.bReCheck = 0; + } + + } + return rmStatus; +} + +// +// gsyncGetNumberOfGpuFrameCountRollbacks_P2060 +// +// Get N where N is the maximum value for gsync framecount > N*(Gpu frame count) +// +static NvU32 +gsyncGetNumberOfGpuFrameCountRollbacks_P2060 +( + NvU32 FrameCount, + NvU32 low, + NvU32 high +) +{ + NvU32 mid = (low + high) / 2; + + if (FrameCount >= (high * NV_P2060_MAX_GPU_FRAME_COUNT)) + { + return high; + } + else if ((FrameCount >= (mid * NV_P2060_MAX_GPU_FRAME_COUNT)) && + (FrameCount < ((mid+1) * NV_P2060_MAX_GPU_FRAME_COUNT))) + { + return mid; + } + else if ((FrameCount > (NV_P2060_MAX_GPU_FRAME_COUNT * low)) && (FrameCount < (mid * NV_P2060_MAX_GPU_FRAME_COUNT))) + { + return gsyncGetNumberOfGpuFrameCountRollbacks_P2060(FrameCount, low, mid); + } + else if ((FrameCount > (NV_P2060_MAX_GPU_FRAME_COUNT * mid)) && (FrameCount < (high * NV_P2060_MAX_GPU_FRAME_COUNT))) + { + return gsyncGetNumberOfGpuFrameCountRollbacks_P2060(FrameCount, mid+1, high); + } + else + { + return 0; + } +} + +// Return NV_TRUE if the current Qsync revision supports large sync skew +static NvBool +supportsLargeSyncSkew +( + PDACEXTERNALDEVICE pExtdev +) +{ + if (pExtdev->deviceId == DAC_EXTERNAL_DEVICE_P2061) + { + // All p2061 revisions support sync skew > 1. + return NV_TRUE; + } + else + { + // + // P2060 FPGA (revision < 3) does not support SyncSkew more than 1 us(HW limitation). + // If set to value more than 1 us, we observe screen flashing. Refer bug 1058215 + // + NV_ASSERT(pExtdev->deviceId == DAC_EXTERNAL_DEVICE_P2060); + return (pExtdev->deviceRev >= DAC_EXTERNAL_DEVICE_REV_3); + } +} + +// Return NV_TRUE if the current Qsync revision needs the Swapbarrier WAR on master +static NvBool +needsMasterBarrierWar +( + PDACEXTERNALDEVICE pExtdev +) +{ + if (pExtdev->deviceId == DAC_EXTERNAL_DEVICE_P2061) + { + // All p2061 revisions do not need the WAR. + return NV_FALSE; + } + else + { + // + // P2060 Fpga (revision <= 5) needs to have the swapbarrier set on framelock masters + // to drive (pull up) the swap_rdy line of the whole framelock setup. + // This is a behaviour with unwanted side effects which needs drivers wars + // for certain configs. + // + NV_ASSERT(pExtdev->deviceId == DAC_EXTERNAL_DEVICE_P2060); + return (pExtdev->deviceRev <= DAC_EXTERNAL_DEVICE_REV_5); + } +} + +// Return NV_TRUE if the Qsync revision is not compatible with GPU +static NvBool +isFirmwareRevMismatch +( + OBJGPU *pGpu, + DAC_EXTERNAL_DEVICE_REVS currentRev +) +{ + if (IsKEPLER(pGpu)) + { + return ((currentRev < NV_P2060_MIN_REV) || + (currentRev == DAC_EXTERNAL_DEVICE_REV_5) || + (currentRev == DAC_EXTERNAL_DEVICE_REV_6)); + } + else if (IsMAXWELL(pGpu)) + { + return (currentRev < NV_P2060_MIN_REV); + } + else + { + return NV_FALSE; + } +} + +/* + * Nvlink and QSync can both transmit inter-GPU Display sync signals. + * Contention in these signals is observed on some boards, if both Nvlink and + * QSync are present between the boards. + * + * Returns TRUE if contention in transmission of sync signals possible on the + * given GPU board if both mediums (QSync and Nvlink) are present between GPUs + */ + +static NvBool +isBoardWithNvlinkQsyncContention +( + POBJGPU pGpu +) +{ + NvU16 devIds[] = { + 0x2230, // Nvidia RTX A6000 (PG133 SKU 500) + 0x2231, // Nvidia RTX A5000 (PG132 SKU 500) + 0x2233 // Nvidia RTX A5500 (PG132 SKU 520) + }; + + NvU16 thisDevId = (NvU16)(((pGpu->idInfo.PCIDeviceID) >> 16) & 0x0000FFFF); + NvU32 i; + + for (i=0; i < (sizeof(devIds)/sizeof(devIds[0])); i++) + { + if (thisDevId == devIds[i]) + { + return NV_TRUE; + } + } + + return NV_FALSE; +} diff --git a/src/nvidia/src/kernel/gpu/external_device/arch/pascal/kern_gsync_p2061.c b/src/nvidia/src/kernel/gpu/external_device/arch/pascal/kern_gsync_p2061.c new file mode 100644 index 000000000..11045b57c --- /dev/null +++ b/src/nvidia/src/kernel/gpu/external_device/arch/pascal/kern_gsync_p2061.c @@ -0,0 +1,142 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "dev_p2060.h" +#include "dev_p2061.h" +#include "gpu/external_device/dac_p2060.h" +#include "gpu/external_device/dac_p2061.h" + +/* + * Get the house sync mode (input/output). + */ +NV_STATUS +gsyncGetHouseSyncMode_P2061 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU8* houseSyncMode +) +{ + NvU8 regCtrl4; + NV_STATUS status; + + status = readregu008_extdeviceTargeted(pGpu, pExtDev, + (NvU8)NV_P2061_CONTROL4, ®Ctrl4); + *houseSyncMode = DRF_VAL(_P2061, _CONTROL4, _HOUSE_SYNC_MODE, regCtrl4); + + return status; +} + +/* + * Set the house sync mode (input/output). + */ +NV_STATUS +gsyncSetHouseSyncMode_P2061 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU8 houseSyncMode +) +{ + NvU8 regStatus2; + NvU8 regCtrl4; + NV_STATUS status; + + if (houseSyncMode != NV_P2061_CONTROL4_HOUSE_SYNC_MODE_INPUT && + houseSyncMode != NV_P2061_CONTROL4_HOUSE_SYNC_MODE_OUTPUT) + { + return NV_ERR_INVALID_ARGUMENT; + } + + status = readregu008_extdeviceTargeted(pGpu, pExtDev, + (NvU8)NV_P2060_STATUS2, ®Status2); + + status = readregu008_extdeviceTargeted(pGpu, pExtDev, + (NvU8)NV_P2061_CONTROL4, ®Ctrl4); + + // + // Bailing out when the following 3 conditions are satisfied: + // 1. house sync mode is currently set as input, and + // 2. there is a BNC signal detected, and + // 3. client wants to switch house sync mode to output. + // + // This helps avoid the case that user is trying to toggle the mode to output + // when p2061 is inputting from a house sync device. + // + if (FLD_TEST_DRF(_P2061, _CONTROL4, _HOUSE_SYNC_MODE, _INPUT, regCtrl4) && + !FLD_TEST_DRF(_P2060, _STATUS2, _HS_DETECT, _NONE, regStatus2) && + houseSyncMode == NV_P2061_CONTROL4_HOUSE_SYNC_MODE_OUTPUT) + { + return NV_ERR_INVALID_STATE; + } + + regCtrl4 = FLD_SET_DRF_NUM(_P2061, _CONTROL4, _HOUSE_SYNC_MODE, houseSyncMode, regCtrl4); + status |= writeregu008_extdeviceTargeted(pGpu, pExtDev, + (NvU8)NV_P2061_CONTROL4, regCtrl4); + + return status; +} + +/* + * Handle Get and Set queries related to CPL status. + */ +NV_STATUS +gsyncGetCplStatus_P2061 +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + GSYNCSTATUS CplStatus, + NvU32 *pVal +) +{ + NV_STATUS status = NV_OK; + NvU8 regStatus2; + NvU8 regStatus6; + + switch (CplStatus) + { + // p2061-specific cases + case gsync_Status_bInternalSlave: + status = readregu008_extdeviceTargeted(pGpu, pExtDev, + (NvU8)NV_P2060_STATUS2, ®Status2); + if (status != NV_OK) + { + break; + } + status = readregu008_extdeviceTargeted(pGpu, pExtDev, + (NvU8)NV_P2061_STATUS6, ®Status6); + if (status == NV_OK) + { + *pVal = FLD_TEST_DRF(_P2060, _STATUS2, _PORT0, _OUTPUT, (NvU32)regStatus2) && + FLD_TEST_DRF(_P2060, _STATUS2, _PORT1, _OUTPUT, (NvU32)regStatus2) && + FLD_TEST_DRF(_P2061, _STATUS6, _INT_PORT_DIRECTION, _INPUT, (NvU32)regStatus6); + } + break; + // common cases shared by both p2060 and p2061 + default: + status = gsyncGetCplStatus_P2060(pGpu, pExtDev, CplStatus, pVal); + } + + return status; +} + diff --git a/src/nvidia/src/kernel/gpu/external_device/gsync.c b/src/nvidia/src/kernel/gpu/external_device/gsync.c new file mode 100644 index 000000000..498ff9a12 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/external_device/gsync.c @@ -0,0 +1,2630 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2008-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/***************************** HW State Routines ***************************\ +* * +* Gsync module * +* * +\***************************************************************************/ + +#include "core/core.h" + +// The "ONLY_IF => 'EXTDEV_GSYNC'," condition in sources.def is ignored! + +#include "nvRmReg.h" +#include "core/system.h" +#include "core/locks.h" +#include "gpu_mgr/gpu_mgr.h" +#include "gpu/external_device/gsync.h" +#include "os/os.h" +#include "rmapi/control.h" +#include "gpu/external_device/gsync_api.h" + +#include "gpu/external_device/dac_p2060.h" +#include "gpu/external_device/dac_p2061.h" + +#include "ctrl/ctrl0000/ctrl0000gsync.h" +#include "ctrl/ctrl30f1.h" + +#include "class/cl30f1.h" + +// local static funcs +static NV_STATUS gsyncSetupNullProvider (OBJGSYNCMGR *pGsyncMgr, NvU32); + +static OBJGPU *gsyncGetMasterableGpu(OBJGSYNC *); +static NvBool gsyncIsAnyHeadFramelocked(OBJGSYNC *); + +static NV_STATUS gsyncGetGpuTopology(OBJGSYNC *, + NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PARAMS*); +static NV_STATUS gsyncGetStatusSignals(OBJGSYNC *, + NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_PARAMS*); +static NV_STATUS gsyncGetStatusParams(OBJGSYNC *, + NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS*); +static NV_STATUS gsyncSetControlParams(OBJGSYNC *, + NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS*); +static NV_STATUS gsyncGetStatusCaps(OBJGSYNC *, + NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS*); +static NV_STATUS gsyncGetControlSync(OBJGSYNC *, + NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS*); +static NV_STATUS gsyncSetControlSync(OBJGSYNC *, + NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_PARAMS*); +static NV_STATUS gsyncSetControlUnsync(OBJGSYNC *, + NV30F1_CTRL_GSYNC_SET_CONTROL_UNSYNC_PARAMS*); +static NV_STATUS gsyncGetStatusSync(OBJGSYNC *pGsync, + NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_PARAMS* pParams); +static NV_STATUS gsyncGetStatus(OBJGSYNC *, + NV30F1_CTRL_GSYNC_GET_STATUS_PARAMS*); +static NV_STATUS gsyncGetControlTesting(OBJGSYNC *, + NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS*); +static NV_STATUS gsyncSetControlTesting(OBJGSYNC *, + NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS*); +static NV_STATUS gsyncSetControlWatchdog(OBJGSYNC *, + NV30F1_CTRL_GSYNC_SET_CONTROL_WATCHDOG_PARAMS*); +static NV_STATUS gsyncGetControlInterlaceMode(OBJGSYNC *, + NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS*); +static NV_STATUS gsyncSetControlInterlaceMode(OBJGSYNC *, + NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS*); +static NV_STATUS gsyncGetControlSwapBarrier(OBJGSYNC *, OBJGPU *, + NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_BARRIER_PARAMS*); +static NV_STATUS gsyncSetControlSwapBarrier(OBJGSYNC *, OBJGPU *, + NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS*); +static NV_STATUS gsyncGetControlSwapLockWindow(OBJGSYNC *, + NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS*); +static NV_STATUS gsyncGetOptimizedTiming(OBJGSYNC *pGsync, + NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS* pParams); +static NV_STATUS gsyncGetControlStereoLockMode(OBJGSYNC *, + NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS*); +static NV_STATUS gsyncSetControlStereoLockMode(OBJGSYNC *, + NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS*); +static NV_STATUS gsyncReadRegister(OBJGSYNC *, + NV30F1_CTRL_GSYNC_READ_REGISTER_PARAMS *); +static NV_STATUS gsyncWriteRegister(OBJGSYNC *, + NV30F1_CTRL_GSYNC_WRITE_REGISTER_PARAMS *); +static NV_STATUS gsyncSetLocalSync(OBJGSYNC *, + NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS*); +static NV_STATUS gsyncConfigFlash(OBJGSYNC *, + NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH_PARAMS*); +static NV_STATUS gsyncGetHouseSyncMode(OBJGSYNC *pGsync, + NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS*); +static NV_STATUS gsyncSetHouseSyncMode(OBJGSYNC *pGsync, + NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS*); + +NV_STATUS +gsyncmgrConstruct_IMPL(OBJGSYNCMGR *pGsyncMgr) +{ + NvU32 i; + + NV_PRINTF(LEVEL_INFO, "\n"); + + pGsyncMgr->gsyncCount = 0; + + for (i = 0; i < NV30F1_MAX_GSYNCS; i++) + { + portMemSet(&pGsyncMgr->gsyncTable[i], 0, sizeof (OBJGSYNC)); + gsyncSetupNullProvider(pGsyncMgr, i); + pGsyncMgr->gsyncTable[i].gsyncId = NV0000_CTRL_GSYNC_INVALID_ID; + // Automatic watchdog scheduling is enabled until 1st manual call. + pGsyncMgr->gsyncTable[i].bAutomaticWatchdogScheduling = NV_TRUE; + pGsyncMgr->gsyncTable[i].bDoEventFiltering = NV_FALSE; + } + + return NV_OK; +} + +// Destructor +void +gsyncmgrDestruct_IMPL(OBJGSYNCMGR *pGsyncMgr) +{ + OBJGSYNC *pGsync; + NvU32 i; + + NV_PRINTF(LEVEL_INFO, "\n"); + + for (i = 0; i < NV30F1_MAX_GSYNCS; i++) + { + pGsync = &pGsyncMgr->gsyncTable[i]; + + // NULL everything + portMemSet(pGsync, 0, sizeof (OBJGSYNC)); + } +} + +// +// gsyncGetMasterableGpuByInstance +// Return a gpu that can be timing master for the specified gsync instance. +// +POBJGPU +gsyncGetMasterableGpuByInstance(NvU32 gsyncInst) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + + if (gsyncInst >= NV30F1_MAX_GSYNCS) + return NULL; + + NV_ASSERT(pGsyncMgr->gsyncTable[gsyncInst].gpuCount > 0); + + return gsyncGetMasterableGpu(&pGsyncMgr->gsyncTable[gsyncInst]); + +} + +static OBJGPU *gsyncGetMasterableGpu(OBJGSYNC *pGsync) +{ + NvU32 i; + + for (i = 0; i < pGsync->gpuCount; i++) + { + if ((pGsync->masterableGpuConnectors & (1 << i)) && + (pGsync->gpus[i].connector != gsync_Connector_None)) + { + return gpumgrGetGpuFromId(pGsync->gpus[i].gpuId); + } + } + + NV_PRINTF(LEVEL_ERROR, "Invalid gsync state\n"); + + return NULL; +} + +/* + * Set up the function pointers for p2060 gsync object. + */ +static NV_STATUS +gsyncP2060StartupProvider(OBJGSYNC *pGsync) +{ + + // All four GPU connectors are masterable on P2060 + pGsync->masterableGpuConnectors = ((1 << NV30F1_GSYNC_CONNECTOR_ONE) | + (1 << NV30F1_GSYNC_CONNECTOR_TWO) | + (1 << NV30F1_GSYNC_CONNECTOR_THREE) | + (1 << NV30F1_GSYNC_CONNECTOR_FOUR)); + + pGsync->connectorCount = NV_P2060_MAX_IFACES_PER_GSYNC; + + pGsync->gsyncHal.gsyncGpuCanBeMaster = gsyncGpuCanBeMaster_P2060; + pGsync->gsyncHal.gsyncOptimizeTiming = gsyncOptimizeTimingParameters_P2060; + + pGsync->gsyncHal.gsyncRefSignal = gsyncRefSignal_P2060; + pGsync->gsyncHal.gsyncRefMaster = gsyncRefMaster_P2060; + pGsync->gsyncHal.gsyncRefSlaves = gsyncRefSlaves_P2060; + pGsync->gsyncHal.gsyncGetCplStatus = gsyncGetCplStatus_P2060; + pGsync->gsyncHal.gsyncSetWatchdog = gsyncSetWatchdog_P2060; + pGsync->gsyncHal.gsyncGetRevision = gsyncGetRevision_P2060; + + // Get and Set + pGsync->gsyncHal.gsyncGetUseHouse = gsyncGetUseHouse_P2060; + pGsync->gsyncHal.gsyncSetUseHouse = gsyncSetUseHouse_P2060; + pGsync->gsyncHal.gsyncGetSyncPolarity = gsyncGetSyncPolarity_P2060; + pGsync->gsyncHal.gsyncSetSyncPolarity = gsyncSetSyncPolarity_P2060; + pGsync->gsyncHal.gsyncGetVideoMode = gsyncGetVideoMode_P2060; + pGsync->gsyncHal.gsyncSetVideoMode = gsyncSetVideoMode_P2060; + pGsync->gsyncHal.gsyncGetNSync = gsyncGetNSync_P2060; + pGsync->gsyncHal.gsyncSetNSync = gsyncSetNSync_P2060; + pGsync->gsyncHal.gsyncGetSyncSkew = gsyncGetSyncSkew_P2060; + pGsync->gsyncHal.gsyncSetSyncSkew = gsyncSetSyncSkew_P2060; + pGsync->gsyncHal.gsyncGetSyncStartDelay = gsyncGetSyncStartDelay_P2060; + pGsync->gsyncHal.gsyncSetSyncStartDelay = gsyncSetSyncStartDelay_P2060; + pGsync->gsyncHal.gsyncGetEmitTestSignal = gsyncGetEmitTestSignal_P2060; + pGsync->gsyncHal.gsyncSetEmitTestSignal = gsyncSetEmitTestSignal_P2060; + pGsync->gsyncHal.gsyncGetInterlaceMode = gsyncGetInterlaceMode_P2060; + pGsync->gsyncHal.gsyncSetInterlaceMode = gsyncSetInterlaceMode_P2060; + pGsync->gsyncHal.gsyncGetStereoLockMode = gsyncGetStereoLockMode_P2060; + pGsync->gsyncHal.gsyncSetStereoLockMode = gsyncSetStereoLockMode_P2060; + + pGsync->gsyncHal.gsyncRefSwapBarrier = gsyncRefSwapBarrier_P2060; + pGsync->gsyncHal.gsyncSetMosaic = gsyncSetMosaic_P2060; + pGsync->gsyncHal.gsyncConfigFlashGsync = gsyncConfigFlashGsync_P2060; + + return NV_OK; +} + +/* + * Set up the function pointers for p2061 gsync object. + */ +static NV_STATUS +gsyncP2061StartupProvider(OBJGSYNC *pGsync) +{ + NV_STATUS status; + // Call P2060 startup provider for setting up those HALs that + // are identical to P2060. + status = gsyncP2060StartupProvider(pGsync); + + // Hals differ between p2060 and p2061, apply override + pGsync->gsyncHal.gsyncGetCplStatus = gsyncGetCplStatus_P2061; + + // HALs for P2061 specifically + pGsync->gsyncHal.gsyncGetHouseSyncMode = gsyncGetHouseSyncMode_P2061; + pGsync->gsyncHal.gsyncSetHouseSyncMode = gsyncSetHouseSyncMode_P2061; + + return status; +} + +/* + * This is the general entrance for setting up interfaces for different objects. + * We will direct it to a specific start-up provider based on board ID. + */ +static NV_STATUS +gsyncStartupProvider +( + OBJGSYNC *pGsync, + DAC_EXTERNAL_DEVICES externalDevice +) +{ + switch (externalDevice) + { + default: + case DAC_EXTERNAL_DEVICE_NONE: + return NV_OK; + case DAC_EXTERNAL_DEVICE_P2060: + return gsyncP2060StartupProvider(pGsync); + case DAC_EXTERNAL_DEVICE_P2061: + return gsyncP2061StartupProvider(pGsync); + } +} + +// +// gsyncAttachGpu +// +// Associate this gpu with this gsync. Some gsyncs have primary +// and secondary connectors, and it's important to keep track of +// that because the primary can talk to the device, whereas the +// secondary can only listen. Also, only a display on the primary +// connector can be a frame lock master. +// +NV_STATUS +gsyncAttachGpu(PDACEXTERNALDEVICE pExtDev, OBJGPU *pGpu, + GSYNCCONNECTOR connector, OBJGPU *pProxyGpu, + DAC_EXTERNAL_DEVICES externalDevice) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync = NULL; + NvU32 i, j; + + NV_ASSERT(rmGpuLockIsOwner()); + + // Check to see if we've already attached this gpu + for (i = 0; i < NV30F1_MAX_GSYNCS; i++) + { + for (j = 0; j < pGsyncMgr->gsyncTable[i].gpuCount; j++) + { + if (pGsyncMgr->gsyncTable[i].gpus[j].gpuId == pGpu->gpuId) + { + NV_PRINTF(LEVEL_ERROR, "gpu is %d already attached!\n", + pGpu->gpuId); + + return NV_ERR_INVALID_ARGUMENT; + } + } + } + + // try to match this external device + for (i = 0; i < NV30F1_MAX_GSYNCS; i++) + { + if (pGsyncMgr->gsyncTable[i].pExtDev == pExtDev) + break; + } + + // allocate new entry in gsync table if extdev not found + if (i == NV30F1_MAX_GSYNCS) + { + for (i = 0; i < NV30F1_MAX_GSYNCS; i++) + { + if (pGsyncMgr->gsyncTable[i].gpuCount == 0) + { + pGsyncMgr->gsyncCount++; + break; + } + } + } + + if ((i == NV30F1_MAX_GSYNCS) || + (pGsyncMgr->gsyncTable[i].gpuCount == NV30F1_CTRL_MAX_GPUS_PER_GSYNC)) + { + NV_PRINTF(LEVEL_ERROR, "gsync table full!\n"); + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + pGsync = &pGsyncMgr->gsyncTable[i]; + + pGsync->pExtDev = pExtDev; + pGsync->gpus[pGsync->gpuCount].gpuId = pGpu->gpuId; + pGsync->gpus[pGsync->gpuCount].connector = connector; + pGsync->gpus[pGsync->gpuCount].proxyGpuId = + (pProxyGpu != NULL) ? pProxyGpu->gpuId : NV30F1_CTRL_GPU_INVALID_ID; + + if (pGsync->gsyncId == NV30F1_CTRL_GPU_INVALID_ID) + { + // If invalid, GSYNC gsyncId will be any of attached GPU gpuId. + pGsync->gsyncId = pGpu->gpuId; + } + + pGsync->gpuCount++; + + pSys->setProperty(pSys, PDB_PROP_SYS_IS_GSYNC_ENABLED, NV_TRUE); + + return gsyncStartupProvider(pGsync, externalDevice); +} + +// +// gsyncRemoveGpu +// +// Remove a gpu from this gsync +// +NV_STATUS +gsyncRemoveGpu(OBJGPU *pGpu) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync; + NvU32 i, j; + + NV_ASSERT(rmGpuLockIsOwner()); + + for (i = 0; i < NV30F1_MAX_GSYNCS; i++) + { + pGsync = &pGsyncMgr->gsyncTable[i]; + + for (j = 0; j < pGsync->gpuCount; j++) + { + if (pGpu->gpuId == pGsync->gpus[j].gpuId) + { + // Careful here: we are modifying one of the test conditions + // for this for loop. + pGsync->gpuCount--; + + if (j != pGsync->gpuCount) + { + // copy the last gpu in the array over this one (if this + // isn't already the last element) + portMemCopy(&pGsync->gpus[j], + sizeof(pGsync->gpus[j]), + &pGsync->gpus[pGsync->gpuCount], + sizeof(pGsync->gpus[j])); + } + + // zero out the element (which we may have just copied) + portMemSet(&pGsync->gpus[pGsync->gpuCount], 0, + sizeof(pGsync->gpus[pGsync->gpuCount])); + + if (pGsync->gpuCount == 0) + { + pGsyncMgr->gsyncCount--; + pGsync->gsyncId = NV0000_CTRL_GSYNC_INVALID_ID; + gsyncSetupNullProvider(pGsyncMgr, i); + } + + if (pGsyncMgr->gsyncCount == 0) + { + pSys->setProperty(pSys, PDB_PROP_SYS_IS_GSYNC_ENABLED, NV_FALSE); + } + // If we ever support multiple gsyncs per + // gpu, need to make sure we handle this correctly since we + // are modifying one of our test conditions inside the 'for' + // loop. For now just return from here. + return NV_OK; + } + } + } + + NV_PRINTF(LEVEL_INFO, "GPU was not found in gsync object\n"); + + return NV_OK; +} + +// +// gsyncmgrGetGsync +// +// This routine returns a OBJGSYNC object associated with this GPU. +// +POBJGSYNC +gsyncmgrGetGsync(OBJGPU *pGpu) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = NULL; + OBJGSYNC *pGsync = NULL; + NvU32 i, j; + + if (!RMCFG_FEATURE_EXTDEV_GSYNC) + return NULL; + + if (!pGpu) + return NULL; + + pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + + for (i = 0; i < NV30F1_MAX_GSYNCS; i++) + { + pGsync = &pGsyncMgr->gsyncTable[i]; + + for (j = 0; j < pGsync->gpuCount; j++) + { + if (pGpu->gpuId == pGsync->gpus[j].gpuId) + { + return pGsync; + } + } + } + + return NULL; +} + +// +// gsyncGetAttachedIds +// +// This routine services the NV0000_CTRL_GSYNC_GET_ATTACHED_IDS command. +// The passed in gsync table is filled in with the unique gsync value +// for each attached gsync. Any remaining entries in the table +// are set to the invalid id value. +// +NV_STATUS +gsyncGetAttachedIds(NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS *pGsyncIdsParams) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + NvU32 *pGsyncIds = &pGsyncIdsParams->gsyncIds[0]; + NvU32 i, cnt; + + // fill the table w/valid entries + for (cnt = 0, i = 0; i < NV30F1_MAX_GSYNCS; i++) + { + if (pGsyncMgr->gsyncTable[i].gpuCount > 0) + { + pGsyncIds[cnt++] = pGsyncMgr->gsyncTable[i].gsyncId; + } + } + + // invalidate rest of the entries + while (cnt < NV30F1_MAX_GSYNCS) + pGsyncIds[cnt++] = NV0000_CTRL_GSYNC_INVALID_ID; + + return NV_OK; +} + +// +// gsyncGetIdInfo +// +// Special purpose routine that handles NV0000_CTRL_CMD_GSYNC_GET_ID_INFO +// requests from clients. +// +NV_STATUS +gsyncGetIdInfo(NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS *pGsyncInfo) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + NvU32 i; + + // fill the table w/valid entries + for (i = 0; i < NV30F1_MAX_GSYNCS; i++) + { + if (pGsyncMgr->gsyncTable[i].gpuCount > 0) + if (pGsyncInfo->gsyncId == pGsyncMgr->gsyncTable[i].gsyncId) + break; + } + + if (i == NV30F1_MAX_GSYNCS) + return NV_ERR_INVALID_ARGUMENT; + + pGsyncInfo->gsyncInstance = i; + pGsyncInfo->gsyncFlags = 0; + + return NV_OK; +} + +// +// gsyncGetGsyncId +// +// Return the associated gsyncId for the specified gpu. +// +NvU32 +gsyncGetGsyncInstance(OBJGPU *pGpu) +{ + + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync; + NvU32 i, j; + + for (i = 0; i < NV30F1_MAX_GSYNCS; i++) + { + pGsync = &pGsyncMgr->gsyncTable[i]; + + for (j = 0; j < pGsync->gpuCount; j++) + { + if (pGpu->gpuId == pGsync->gpus[j].gpuId) + return i; + } + } + + return NV30F1_MAX_GSYNCS; +} + +NvBool +gsyncAreAllGpusInConfigAttachedToSameGsyncBoard(OBJGPU **pGpus, NvU32 gpuCount) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync = NULL; + NvBool bIsGpuFoundInGsync = NV_FALSE; + NvU32 gsyncCount = 0, i, j; + + while(gsyncCount < pGsyncMgr->gsyncCount) + { + pGsync = &pGsyncMgr->gsyncTable[gsyncCount++]; + if (pGsync == NULL) + { + continue; + } + + for (i = 0; i < gpuCount; i++) + { + // Take any gpu form given pGpus + OBJGPU *pGpu = pGpus[i]; + bIsGpuFoundInGsync = NV_FALSE; + + for (j = 0; j < pGsync->gpuCount; j++) + { + if (pGpu->gpuId == pGsync->gpus[j].gpuId) + { + bIsGpuFoundInGsync = NV_TRUE; + } + } + + if (!bIsGpuFoundInGsync) + { + // pGpu is not present under this gsync. + break; + } + } + + if (bIsGpuFoundInGsync) + { + // All `gpu form given pGpus are attached to same gysnc + return NV_TRUE; + } + } + return NV_FALSE; +} + +NV_STATUS +gsyncapiCtrlCmdGsyncGetVersion_IMPL +( + GSyncApi *pGsyncApi, + NV30F1_CTRL_GSYNC_GET_VERSION_PARAMS *pGsyncGetVersionParams +) +{ + pGsyncGetVersionParams->version = NV30F1_CTRL_GSYNC_API_VER; + pGsyncGetVersionParams->revision = NV30F1_CTRL_GSYNC_API_REV; + + return NV_OK; +} + +NV_STATUS +gsyncapiCtrlCmdGetGsyncGpuTopology_IMPL +( + GSyncApi *pGsyncApi, + NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync = &pGsyncMgr->gsyncTable[pGsyncApi->instance]; + + return gsyncGetGpuTopology(pGsync, pParams); +} + +NV_STATUS +gsyncapiCtrlCmdGsyncGetStatusSignals_IMPL +( + GSyncApi *pGsyncApi, + NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync = &pGsyncMgr->gsyncTable[pGsyncApi->instance]; + + return gsyncGetStatusSignals(pGsync, pParams); +} + +NV_STATUS +gsyncapiCtrlCmdGsyncGetControlParams_IMPL +( + GSyncApi *pGsyncApi, + NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync = &pGsyncMgr->gsyncTable[pGsyncApi->instance]; + + return gsyncGetStatusParams(pGsync, pParams); +} + +NV_STATUS +gsyncapiCtrlCmdGsyncSetControlParams_IMPL +( + GSyncApi *pGsyncApi, + NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync = &pGsyncMgr->gsyncTable[pGsyncApi->instance]; + + return gsyncSetControlParams(pGsync, pParams); +} + +NV_STATUS +gsyncapiCtrlCmdGsyncGetControlSync_IMPL +( + GSyncApi *pGsyncApi, + NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync = &pGsyncMgr->gsyncTable[pGsyncApi->instance]; + + return gsyncGetControlSync(pGsync, pParams); +} + +NV_STATUS +gsyncapiCtrlCmdGsyncSetControlSync_IMPL +( + GSyncApi *pGsyncApi, + NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync = &pGsyncMgr->gsyncTable[pGsyncApi->instance]; + + return gsyncSetControlSync(pGsync, pParams); +} + +NV_STATUS +gsyncapiCtrlCmdGsyncSetControlUnsync_IMPL +( + GSyncApi *pGsyncApi, + NV30F1_CTRL_GSYNC_SET_CONTROL_UNSYNC_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync = &pGsyncMgr->gsyncTable[pGsyncApi->instance]; + + return gsyncSetControlUnsync(pGsync, pParams); +} + +NV_STATUS +gsyncapiCtrlCmdGsyncGetStatusSync_IMPL +( + GSyncApi *pGsyncApi, + NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync = &pGsyncMgr->gsyncTable[pGsyncApi->instance]; + + return gsyncGetStatusSync(pGsync, pParams); +} + +NV_STATUS +gsyncapiCtrlCmdGsyncGetStatus_IMPL +( + GSyncApi *pGsyncApi, + NV30F1_CTRL_GSYNC_GET_STATUS_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync = &pGsyncMgr->gsyncTable[pGsyncApi->instance]; + + return gsyncGetStatus(pGsync, pParams); +} + +NV_STATUS +gsyncapiCtrlCmdGsyncGetControlTesting_IMPL +( + GSyncApi *pGsyncApi, + NV30F1_CTRL_GSYNC_GET_CONTROL_TESTING_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync = &pGsyncMgr->gsyncTable[pGsyncApi->instance]; + + return gsyncGetControlTesting(pGsync, pParams); +} + +NV_STATUS +gsyncapiCtrlCmdGsyncSetControlTesting_IMPL +( + GSyncApi *pGsyncApi, + NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync = &pGsyncMgr->gsyncTable[pGsyncApi->instance]; + + return gsyncSetControlTesting(pGsync, pParams); +} + +NV_STATUS +gsyncapiCtrlCmdGsyncSetControlWatchdog_IMPL +( + GSyncApi *pGsyncApi, + NV30F1_CTRL_GSYNC_SET_CONTROL_WATCHDOG_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync = &pGsyncMgr->gsyncTable[pGsyncApi->instance]; + + return gsyncSetControlWatchdog(pGsync, pParams); +} + +NV_STATUS +gsyncapiCtrlCmdGsyncGetControlInterlaceMode_IMPL +( + GSyncApi *pGsyncApi, + NV30F1_CTRL_GSYNC_GET_CONTROL_INTERLACE_MODE_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync = &pGsyncMgr->gsyncTable[pGsyncApi->instance]; + + return gsyncGetControlInterlaceMode(pGsync, pParams); +} + +NV_STATUS +gsyncapiCtrlCmdGsyncSetControlInterlaceMode_IMPL +( + GSyncApi *pGsyncApi, + NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync = &pGsyncMgr->gsyncTable[pGsyncApi->instance]; + + return gsyncSetControlInterlaceMode(pGsync, pParams); +} + +NV_STATUS +gsyncapiCtrlCmdGsyncGetControlSwapBarrier_IMPL +( + GSyncApi *pGsyncApi, + NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_BARRIER_PARAMS *pParams +) +{ + NV_STATUS status = NV_ERR_INVALID_STATE; + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync = &pGsyncMgr->gsyncTable[pGsyncApi->instance]; + OBJGPU *pGpu = gpumgrGetGpuFromId(pParams->gpuId); + + if (pGpu == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + SLI_LOOP_START(SLI_LOOP_FLAGS_NONE) + { + status = gsyncGetControlSwapBarrier(pGsync, pGpu, pParams); + if (status != NV_OK) + { + SLI_LOOP_BREAK; + } + } + SLI_LOOP_END + + return status; +} + +NV_STATUS +gsyncapiCtrlCmdGsyncSetControlSwapBarrier_IMPL +( + GSyncApi *pGsyncApi, + NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS *pParams +) +{ + NV_STATUS status = NV_ERR_INVALID_STATE; + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync = &pGsyncMgr->gsyncTable[pGsyncApi->instance]; + OBJGPU *pGpu = gpumgrGetGpuFromId(pParams->gpuId); + + if (pGpu == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + SLI_LOOP_START(SLI_LOOP_FLAGS_NONE) + { + status = gsyncSetControlSwapBarrier(pGsync, pGpu, pParams); + if (status != NV_OK) + { + SLI_LOOP_BREAK; + } + } + SLI_LOOP_END + + return status; +} + +NV_STATUS +gsyncapiCtrlCmdGsyncGetControlSwapLockWindow_IMPL +( + GSyncApi *pGsyncApi, + NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync = &pGsyncMgr->gsyncTable[pGsyncApi->instance]; + + return gsyncGetControlSwapLockWindow(pGsync, pParams); +} + +NV_STATUS +gsyncapiCtrlCmdGsyncGetCaps_IMPL +( + GSyncApi *pGsyncApi, + NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync = &pGsyncMgr->gsyncTable[pGsyncApi->instance]; + + return gsyncGetStatusCaps(pGsync, pParams); +} + +NV_STATUS +gsyncapiCtrlCmdGsyncGetOptimizedTiming_IMPL +( + GSyncApi *pGsyncApi, + NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync = &pGsyncMgr->gsyncTable[pGsyncApi->instance]; + + return gsyncGetOptimizedTiming(pGsync, pParams); +} + +NV_STATUS +gsyncapiCtrlCmdGsyncSetLocalSync_IMPL +( + GSyncApi *pGsyncApi, + NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync = &pGsyncMgr->gsyncTable[pGsyncApi->instance]; + + return gsyncSetLocalSync(pGsync, pParams); +} + +NV_STATUS +gsyncapiCtrlCmdGsyncConfigFlash_IMPL +( + GSyncApi *pGsyncApi, + NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync = &pGsyncMgr->gsyncTable[pGsyncApi->instance]; + + return gsyncConfigFlash(pGsync, pParams); +} + +NV_STATUS +gsyncapiCtrlCmdGsyncSetEventNotification_IMPL +( + GSyncApi *pGsyncApi, + NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_PARAMS *pSetEventParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync = &pGsyncMgr->gsyncTable[pGsyncApi->instance]; + NV_STATUS status = NV_OK; + + if (NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_DISABLE == pSetEventParams->action) + { + pGsyncApi->notifyAction = pSetEventParams->action; + } + else + { + Notifier *pNotifier = staticCast(pGsyncApi, Notifier); + PEVENTNOTIFICATION *ppEventNotifications = NULL; + + // NV01_EVENT must have been plugged in + if (pNotifier->pNotifierShare == NULL) + return NV_ERR_INVALID_STATE; + + ppEventNotifications = inotifyGetNotificationListPtr(staticCast(pNotifier, INotifier)); + if (*ppEventNotifications == NULL) + return NV_ERR_INVALID_STATE; + + if (NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_ALL & pSetEventParams->action) + { + NvU32 eventNum = 0, tempMask = pSetEventParams->action; + + // If more than one bit is set, the highest on is choosen. + // This is a fallback, we should only be called with one bit set. + NV_ASSERT(ONEBITSET(tempMask)); + + // convert mask to array index + while (tempMask >>= 1) + { + eventNum++; + } + + if (eventNum < NV30F1_CTRL_GSYNC_EVENT_TYPES) + { + NV_ASSERT_OR_RETURN(pGsyncApi->pEventByType[eventNum] == NULL, NV_ERR_INVALID_STATE); + + // pull event off of queue, put in the slot we calculated + pGsyncApi->pEventByType[eventNum] = *ppEventNotifications; + *ppEventNotifications = (*ppEventNotifications)->Next; + pGsyncApi->pEventByType[eventNum]->Next = NULL; + + // add to the master mask + pGsyncApi->notifyAction |= pSetEventParams->action; + } + pGsyncApi->oldEventNotification = NV_TRUE; + pGsync->bDoEventFiltering = NV_TRUE; + } + else + { + status = NV_ERR_INVALID_ARGUMENT; + } + } + return status; + +} + +NV_STATUS +gsyncapiCtrlCmdGsyncGetControlStereoLockMode_IMPL +( + GSyncApi *pGsyncApi, + NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync = &pGsyncMgr->gsyncTable[pGsyncApi->instance]; + + return gsyncGetControlStereoLockMode(pGsync, pParams); +} + +NV_STATUS +gsyncapiCtrlCmdGsyncSetControlStereoLockMode_IMPL +( + GSyncApi *pGsyncApi, + NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync = &pGsyncMgr->gsyncTable[pGsyncApi->instance]; + + return gsyncSetControlStereoLockMode(pGsync, pParams); +} + +NV_STATUS +gsyncapiCtrlCmdGsyncReadRegister_IMPL +( + GSyncApi *pGsyncApi, + NV30F1_CTRL_GSYNC_READ_REGISTER_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync = &pGsyncMgr->gsyncTable[pGsyncApi->instance]; + + return gsyncReadRegister(pGsync, pParams); +} + +NV_STATUS +gsyncapiCtrlCmdGsyncWriteRegister_IMPL +( + GSyncApi *pGsyncApi, + NV30F1_CTRL_GSYNC_WRITE_REGISTER_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync = &pGsyncMgr->gsyncTable[pGsyncApi->instance]; + + return gsyncWriteRegister(pGsync, pParams); +} + +NV_STATUS +gsyncapiCtrlCmdGsyncGetHouseSyncMode_IMPL +( + GSyncApi *pGsyncApi, + NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync = &pGsyncMgr->gsyncTable[pGsyncApi->instance]; + + return gsyncGetHouseSyncMode(pGsync, pParams); +} + +NV_STATUS +gsyncapiCtrlCmdGsyncSetHouseSyncMode_IMPL +( + GSyncApi *pGsyncApi, + NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync = &pGsyncMgr->gsyncTable[pGsyncApi->instance]; + + return gsyncSetHouseSyncMode(pGsync, pParams); +} + +NV_STATUS +gsyncGetGpuTopology(OBJGSYNC *pGsync, + NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PARAMS* pParams) +{ + NvU32 i; + + for (i = 0; i < NV30F1_CTRL_MAX_GPUS_PER_GSYNC; i++) + { + if (i < pGsync->gpuCount && + pGsync->gpus[i].connector <= NV30F1_GSYNC_CONNECTOR_COUNT) + { + pParams->gpus[i].gpuId = pGsync->gpus[i].gpuId; + pParams->gpus[i].connector = pGsync->gpus[i].connector; + pParams->gpus[i].proxyGpuId = pGsync->gpus[i].proxyGpuId; + } + else + { + pParams->gpus[i].gpuId = NV30F1_CTRL_GPU_INVALID_ID; + } + } + pParams->connectorCount = pGsync->connectorCount; + + return NV_OK; +} + +// +// gsyncIsAnyHeadFramelocked +// +// Returns NV_TRUE if any of the heads attached to any of the gpus +// attached to the gsync object is framelocked. NV_FALSE otherwise. +NvBool +gsyncIsAnyHeadFramelocked(OBJGSYNC *pGsync) +{ + if (pGsync && pGsync->pExtDev) + { + OBJGPU *pGpu = NULL; + NvU32 i; + NvU32 refresh, assigned; + + // Loop over all gpus of the gsync object. + for (i = 0; i < pGsync->gpuCount; i++) + { + pGpu = gpumgrGetGpuFromId(pGsync->gpus[i].gpuId); + + if (pGpu) + { + // Check if assigned slaves displays are there. + if ((NV_OK == pGsync->gsyncHal.gsyncRefSlaves(pGpu, + pGsync->pExtDev, refRead, &assigned, &refresh)) && + (assigned != 0)) + { + return NV_TRUE; + } + // Check if assigned master displays are there. + if ((NV_OK == pGsync->gsyncHal.gsyncRefMaster(pGpu, + pGsync->pExtDev, refRead, &assigned, &refresh, NV_FALSE, NV_FALSE)) && + (assigned != 0)) + { + return NV_TRUE; + } + } + } + } + + return NV_FALSE; +} + +NV_STATUS +gsyncGetStatusSignals(OBJGSYNC *pGsync, + NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_PARAMS* pParams) +{ + NvBool bRate; // whether or not to test the rate. + NV_STATUS status = NV_OK; + OBJGPU *pGpu = NULL; + REFTYPE rType = refFetchGet; + + NV_ASSERT_OR_RETURN(pGsync && pGsync->pExtDev, NV_ERR_INVALID_DEVICE); + + pGpu = gsyncGetMasterableGpu(pGsync); + + bRate = !! (pParams->rate & NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_RJ45_0); + status |= pGsync->gsyncHal.gsyncRefSignal(pGpu, pGsync->pExtDev, rType, + gsync_Signal_RJ45_0, bRate, &pParams->RJ45[0]); + + bRate = !! (pParams->rate & NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_RJ45_1); + status |= pGsync->gsyncHal.gsyncRefSignal(pGpu, pGsync->pExtDev, rType, + gsync_Signal_RJ45_1, bRate, &pParams->RJ45[1]); + + bRate = !! (pParams->rate & NV30F1_CTRL_GSYNC_GET_SIGNALS_HOUSE); + status |= pGsync->gsyncHal.gsyncRefSignal(pGpu, pGsync->pExtDev, rType, + gsync_Signal_House, bRate, &pParams->house); + + return status; +} + +NV_STATUS +gsyncGetStatusParams(OBJGSYNC *pGsync, + NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS* pParams) +{ + OBJGPU *pGpu = NULL; + GSYNCSYNCPOLARITY SyncPolarity = pParams->syncPolarity; + GSYNCVIDEOMODE VideoMode = pParams->syncVideoMode; + NV_STATUS status = NV_OK; + + NV_ASSERT_OR_RETURN(pGsync && pGsync->pExtDev, NV_ERR_INVALID_DEVICE); + + pGpu = gsyncGetMasterableGpu(pGsync); + + if ( pParams->which & NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_POLARITY ) + { + status |= pGsync->gsyncHal.gsyncGetSyncPolarity(pGpu, pGsync->pExtDev, &SyncPolarity); + pParams->syncPolarity = (NvU32)SyncPolarity; + } + + if ( pParams->which & NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE ) + { + status |= pGsync->gsyncHal.gsyncGetVideoMode(pGpu, pGsync->pExtDev, &VideoMode); + pParams->syncVideoMode = (NvU32)VideoMode; + } + + if ( pParams->which & NV30F1_CTRL_GSYNC_GET_CONTROL_NSYNC ) + { + status |= pGsync->gsyncHal.gsyncGetNSync(pGpu, pGsync->pExtDev, &pParams->nSync); + } + + if ( pParams->which & NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_SKEW ) + { + status |= pGsync->gsyncHal.gsyncGetSyncSkew(pGpu, pGsync->pExtDev, &pParams->syncSkew); + } + + if ( pParams->which & NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_START_DELAY ) + { + status |= pGsync->gsyncHal.gsyncGetSyncStartDelay(pGpu, pGsync->pExtDev, &pParams->syncStartDelay); + } + + if ( pParams->which & NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_USE_HOUSE ) + { + status |= pGsync->gsyncHal.gsyncGetUseHouse(pGpu, pGsync->pExtDev, &pParams->useHouseSync); + } + + return status; +} + +NV_STATUS +gsyncSetControlParams(OBJGSYNC *pGsync, + NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS* pParams) +{ + OBJGPU *pGpu = NULL; + GSYNCSYNCPOLARITY SyncPolarity = pParams->syncPolarity; + GSYNCVIDEOMODE VideoMode = pParams->syncVideoMode; + NV_STATUS status = NV_OK; + + NV_ASSERT_OR_RETURN(pGsync && pGsync->pExtDev, NV_ERR_INVALID_DEVICE); + + pGpu = gsyncGetMasterableGpu(pGsync); + + if ( pParams->which & NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY ) + { + status |= pGsync->gsyncHal.gsyncSetSyncPolarity(pGpu, pGsync->pExtDev, SyncPolarity); + pParams->syncPolarity = (NvU32)SyncPolarity; + } + + if ( pParams->which & NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE ) + { + status |= pGsync->gsyncHal.gsyncSetVideoMode(pGpu, pGsync->pExtDev, VideoMode); + pParams->syncVideoMode = (NvU32)VideoMode; + } + + if ( pParams->which & NV30F1_CTRL_GSYNC_SET_CONTROL_NSYNC ) + { + status |= pGsync->gsyncHal.gsyncSetNSync(pGpu, pGsync->pExtDev, pParams->nSync); + } + + if ( pParams->which & NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_SKEW ) + { + status |= pGsync->gsyncHal.gsyncSetSyncSkew(pGpu, pGsync->pExtDev, pParams->syncSkew); + } + + if ( pParams->which & NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_START_DELAY ) + { + status |= pGsync->gsyncHal.gsyncSetSyncStartDelay(pGpu, pGsync->pExtDev, pParams->syncStartDelay); + } + + if ( pParams->which & NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_USE_HOUSE ) + { + status |= pGsync->gsyncHal.gsyncSetUseHouse(pGpu, pGsync->pExtDev, pParams->useHouseSync); + } + + return status; +} + +NV_STATUS gsyncGetStatusCaps(OBJGSYNC *pGsync, + NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS* pParams) +{ + OBJGPU *pGpu = NULL; + NV_STATUS status = NV_OK; + + NV_ASSERT_OR_RETURN(pGsync && pGsync->pExtDev, NV_ERR_INVALID_DEVICE); + + pGpu = gsyncGetMasterableGpu(pGsync); + + status |= pGsync->gsyncHal.gsyncGetRevision(pGpu, pGsync->pExtDev, pParams); + + return status; +} + +static NvBool +gsyncIsGpuInGsync(OBJGPU *pGpu, OBJGSYNC *pGsync) +{ + NvU32 gpuCount; + + if (!pGpu || !pGsync) + { + return NV_FALSE; + } + + for (gpuCount = 0; gpuCount < NV30F1_CTRL_MAX_GPUS_PER_GSYNC; gpuCount++) + { + if (pGpu->gpuId == pGsync->gpus[gpuCount].gpuId) + { + return NV_TRUE; + } + } + + return NV_FALSE; +} + +NV_STATUS +gsyncSetLocalSync(OBJGSYNC *pGsync, + NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS* pParams) +{ + OBJGPU *pSourceGpu = NULL; + OBJGPU *pTempGpu = NULL; + NvU8 i; + NV_STATUS status = NV_OK; + + NV_ASSERT_OR_RETURN(pGsync && pGsync->pExtDev, NV_ERR_INVALID_DEVICE); + + pSourceGpu = gpumgrGetGpuFromId(pParams->gpuTimingSource); + if (pSourceGpu == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if(!gsyncIsGpuInGsync(pSourceGpu, pGsync)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if (pParams->slaveGpuCount > NV30F1_CTRL_MAX_GPUS_PER_GSYNC) + { + return NV_ERR_INVALID_ARGUMENT; + } + + for (i = 0; i < pParams->slaveGpuCount; i++) + { + pTempGpu = gpumgrGetGpuFromId(pParams->gpuTimingSlaves[i]); + if (pTempGpu == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if(!gsyncIsGpuInGsync(pTempGpu, pGsync)) + { + return NV_ERR_INVALID_ARGUMENT; + } + } + + status |= pGsync->gsyncHal.gsyncSetMosaic(pSourceGpu, pGsync->pExtDev, pParams); + + return status; +} + +NV_STATUS +gsyncConfigFlash(OBJGSYNC *pGsync, + NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH_PARAMS* pParams) +{ + OBJGPU *pGpu = NULL; + NV_STATUS status = NV_OK; + + NV_ASSERT_OR_RETURN(pGsync && pGsync->pExtDev, NV_ERR_INVALID_DEVICE); + + pGpu = gpumgrGetGpuFromId(pParams->gpuId); + if (pGpu == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if(!gsyncIsGpuInGsync(pGpu, pGsync)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + status |= pGsync->gsyncHal.gsyncConfigFlashGsync(pGpu, pGsync->pExtDev, + pParams->preFlash); + + return status; +} + +NV_STATUS +gsyncGetControlSync(OBJGSYNC *pGsync, + NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS* pParams) +{ + OBJGPU *pGpu = NULL; + NV_STATUS status = NV_OK; + + NV_ASSERT_OR_RETURN(pGsync && pGsync->pExtDev, NV_ERR_INVALID_DEVICE); + + pGpu = gpumgrGetGpuFromId(pParams->gpuId); + if (pGpu == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if(!gsyncIsGpuInGsync(pGpu, pGsync)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if ( pParams->displays == 0 ) + { + // This is the case where we want to query what is current. + if ( pParams->master ) + { + status |= pGsync->gsyncHal.gsyncRefMaster(pGpu, pGsync->pExtDev, refFetchGet, + &pParams->displays, &pParams->refresh, NV_FALSE, NV_FALSE); + } + else + { + status |= pGsync->gsyncHal.gsyncRefSlaves(pGpu, pGsync->pExtDev, refFetchGet, + &pParams->displays, &pParams->refresh); + } + } + else + { + // This is where we want to see if the given Display is assignable + // to this DisplaySync unit under the current conditions (mode, etc). + // If there is no mode then this is definitely a failure. + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NvU32 hClient = pGpu->hInternalClient; + NvU32 hSubdevice = pGpu->hInternalSubdevice; + NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS ctrlParams = {0}; + + ctrlParams.displays = pParams->displays; + status = pRmApi->Control(pRmApi, hClient, hSubdevice, + NV2080_CTRL_CMD_INTERNAL_GSYNC_IS_DISPLAYID_VALID, + &ctrlParams, sizeof(ctrlParams)); + + if (status != NV_OK) + { + pParams->displays = 0; // Signals failure to start with. + // If we find a head with this as its currenty bound + // display then we'll signal success. + NV_PRINTF(LEVEL_ERROR, "Extdev display IDs for the display doesn't exist!\n"); + } + else + { + // Also check if this display is capable of being server + pParams->master = pGsync->gsyncHal.gsyncGpuCanBeMaster(pGpu, pGsync->pExtDev); + pParams->displays = ctrlParams.displayId; + } + } + + return status; +} + +NV_STATUS +gsyncSetControlSync(OBJGSYNC *pGsync, + NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_PARAMS* pParams) +{ + OBJGPU *pGpu = NULL; + NV_STATUS status = NV_OK; + NvU32 assigned, refresh; + + NV_ASSERT_OR_RETURN(pGsync && pGsync->pExtDev, NV_ERR_INVALID_DEVICE); + + pGpu = gpumgrGetGpuFromId(pParams->gpuId); + if (pGpu == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if(!gsyncIsGpuInGsync(pGpu, pGsync)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if (pParams->refresh == 0) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if (pParams->master) + { + NvBool skipSwapBarrierWar = !!(pParams->configFlags & + NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_CONFIG_FLAGS_KEEP_MASTER_SWAPBARRIER_DISABLED); + + status |= pGsync->gsyncHal.gsyncRefMaster(pGpu, pGsync->pExtDev, + refRead, &assigned, &refresh, NV_FALSE, NV_FALSE); + pParams->displays |= assigned; + status |= pGsync->gsyncHal.gsyncRefMaster(pGpu, pGsync->pExtDev, + refSetCommit, &pParams->displays, &pParams->refresh, NV_FALSE, skipSwapBarrierWar); + } + else + { + status |= pGsync->gsyncHal.gsyncRefSlaves(pGpu, pGsync->pExtDev, + refRead, &assigned, &refresh); + pParams->displays |= assigned; + status |= pGsync->gsyncHal.gsyncRefSlaves(pGpu, pGsync->pExtDev, + refSetCommit, &pParams->displays, &pParams->refresh); + } + + // Update watchdog here. + // Only do that is client doesn't take care. + if ((pGsync->bAutomaticWatchdogScheduling) && (NV_OK == status) && + (0 != pParams->displays)) + { + NvU32 enable = 1; + if (NV_OK != pGsync->gsyncHal.gsyncSetWatchdog(pGpu, pGsync->pExtDev, enable)) + { + // Only assert as the master/slave assignment has succeded. + NV_ASSERT(0); + } + } + + return status; +} + +NV_STATUS +gsyncSetControlUnsync(OBJGSYNC *pGsync, + NV30F1_CTRL_GSYNC_SET_CONTROL_UNSYNC_PARAMS* pParams) +{ + OBJGPU *pGpu = NULL; + NV_STATUS status = NV_OK; + NvU32 assigned, refresh; + + NV_ASSERT_OR_RETURN(pGsync && pGsync->pExtDev, NV_ERR_INVALID_DEVICE); + + pGpu = gpumgrGetGpuFromId(pParams->gpuId); + if (pGpu == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if(!gsyncIsGpuInGsync(pGpu, pGsync)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if (pParams->master) + { + status |= pGsync->gsyncHal.gsyncRefMaster(pGpu, pGsync->pExtDev, + refRead, &assigned, &refresh, NV_FALSE, NV_FALSE); + pParams->displays = assigned & ~pParams->displays; + status |= pGsync->gsyncHal.gsyncRefMaster(pGpu, pGsync->pExtDev, + refSetCommit, &pParams->displays, &refresh, !!pParams->retainMaster, NV_FALSE); + } + else + { + status |= pGsync->gsyncHal.gsyncRefSlaves(pGpu, pGsync->pExtDev, + refRead, &assigned, &refresh); + pParams->displays = assigned & ~pParams->displays; + status |= pGsync->gsyncHal.gsyncRefSlaves(pGpu, pGsync->pExtDev, + refSetCommit, &pParams->displays, &refresh); + } + + // Update watchdog here: if no master or slave is + // remaining on the gsync device, disable watchdog. + // Only do that is client doesn't take care. + if ((pGsync->bAutomaticWatchdogScheduling) && + (NV_OK == status) && (0 == pParams->displays) && + (!(gsyncIsAnyHeadFramelocked(pGsync)))) + { + NvU32 enable = 0; + // Only print erromessages as the + if (NV_OK != pGsync->gsyncHal.gsyncSetWatchdog(pGpu, pGsync->pExtDev, enable)) + { + // Only assert as the master/slave unassignment has succeded. + NV_ASSERT(0); + } + } + + return status; +} + +NV_STATUS +gsyncGetStatusSync(OBJGSYNC *pGsync, NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_PARAMS* pParams) +{ + OBJGPU *pGpu = NULL; + NV_STATUS status = NV_OK; + + NV_ASSERT_OR_RETURN(pGsync && pGsync->pExtDev, NV_ERR_INVALID_DEVICE); + + pGpu = gpumgrGetGpuFromId(pParams->gpuId); + if (pGpu == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if(!gsyncIsGpuInGsync(pGpu, pGsync)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + status |= pGsync->gsyncHal.gsyncGetCplStatus(pGpu, pGsync->pExtDev, + gsync_Status_bTiming, &pParams->bTiming); + + status |= pGsync->gsyncHal.gsyncGetCplStatus(pGpu, pGsync->pExtDev, + gsync_Status_bStereoSync, &pParams->bStereoSync); + + status |= pGsync->gsyncHal.gsyncGetCplStatus(pGpu, pGsync->pExtDev, + gsync_Status_bSyncReady, &pParams->bSyncReady); + + return status; +} + + +NV_STATUS +gsyncGetStatus(OBJGSYNC *pGsync, NV30F1_CTRL_GSYNC_GET_STATUS_PARAMS* pParams) +{ + OBJGPU *pGpu = NULL; + NV_STATUS status = NV_OK; + + NV_ASSERT_OR_RETURN(pGsync && pGsync->pExtDev, NV_ERR_INVALID_DEVICE); + + pGpu = gsyncGetMasterableGpu(pGsync); + + if (pParams->which & NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_POLARITY) + { + GSYNCSYNCPOLARITY SyncPolarity = gsync_SyncPolarity_RisingEdge; + + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_INFO, + pGsync->gsyncHal.gsyncGetSyncPolarity(pGpu, pGsync->pExtDev, + &SyncPolarity)); + + if (status == NV_OK) + { + pParams->bLeadingEdge = (SyncPolarity == gsync_SyncPolarity_BothEdges || + SyncPolarity == gsync_SyncPolarity_RisingEdge); + + pParams->bFallingEdge = (SyncPolarity == gsync_SyncPolarity_BothEdges || + SyncPolarity == gsync_SyncPolarity_FallingEdge); + } + } + + if (pParams->which & NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_DELAY) + { + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_INFO, + pGsync->gsyncHal.gsyncGetSyncStartDelay(pGpu, pGsync->pExtDev, + &pParams->syncDelay)); + } + + if (pParams->which & NV30F1_CTRL_GSYNC_GET_STATUS_REFRESH) + { + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_INFO, + pGsync->gsyncHal.gsyncGetCplStatus(pGpu, pGsync->pExtDev, + gsync_Status_Refresh, &pParams->refresh)); + } + + if (pParams->which & NV30F1_CTRL_GSYNC_GET_STATUS_HOUSE_SYNC_INCOMING) + { + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_INFO, + pGsync->gsyncHal.gsyncGetCplStatus(pGpu, pGsync->pExtDev, + gsync_Status_HouseSyncIncoming, &pParams->houseSyncIncoming)); + } + + if (pParams->which & NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_INTERVAL) + { + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_INFO, + pGsync->gsyncHal.gsyncGetNSync(pGpu, pGsync->pExtDev, + &pParams->syncInterval)); + } + + if (pParams->which & NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_READY) + { + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_INFO, + pGsync->gsyncHal.gsyncGetCplStatus(pGpu, pGsync->pExtDev, + gsync_Status_bSyncReady, &pParams->bSyncReady)); + } + + if (pParams->which & NV30F1_CTRL_GSYNC_GET_STATUS_SWAP_READY) + { + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_INFO, + pGsync->gsyncHal.gsyncGetCplStatus(pGpu, pGsync->pExtDev, + gsync_Status_bSwapReady, &pParams->bSwapReady)); + } + + if (pParams->which & NV30F1_CTRL_GSYNC_GET_STATUS_HOUSE_SYNC) + { + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_INFO, + pGsync->gsyncHal.gsyncGetCplStatus(pGpu, pGsync->pExtDev, + gsync_Status_bHouseSync, &pParams->bHouseSync)); + } + + if (pParams->which & NV30F1_CTRL_GSYNC_GET_STATUS_PORT_INPUT) + { + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_INFO, + pGsync->gsyncHal.gsyncGetCplStatus(pGpu, pGsync->pExtDev, + gsync_Status_bPort0Input, &pParams->bPort0Input)); + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_INFO, + pGsync->gsyncHal.gsyncGetCplStatus(pGpu, pGsync->pExtDev, + gsync_Status_bPort1Input, &pParams->bPort1Input)); + } + + if (pParams->which & NV30F1_CTRL_GSYNC_GET_STATUS_PORT_ETHERNET) + { + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_INFO, + pGsync->gsyncHal.gsyncGetCplStatus(pGpu, pGsync->pExtDev, + gsync_Status_bPort0Ethernet, &pParams->bPort0Ethernet)); + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_INFO, + pGsync->gsyncHal.gsyncGetCplStatus(pGpu, pGsync->pExtDev, + gsync_Status_bPort1Ethernet, &pParams->bPort1Ethernet)); + } + + if (pParams->which & NV30F1_CTRL_GSYNC_GET_STATUS_UNIVERSAL_FRAME_COUNT) + { + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_INFO, + pGsync->gsyncHal.gsyncGetCplStatus(pGpu, pGsync->pExtDev, + gsync_Status_UniversalFrameCount, &pParams->universalFrameCount)); + } + + if (pParams->which & NV30F1_CTRL_GSYNC_GET_STATUS_INTERNAL_SLAVE) + { + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_INFO, + pGsync->gsyncHal.gsyncGetCplStatus(pGpu, pGsync->pExtDev, + gsync_Status_bInternalSlave, &pParams->bInternalSlave)); + } + + return status; +} + +NV_STATUS +gsyncGetControlTesting(OBJGSYNC *pGsync, + NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS* pParams) +{ + OBJGPU *pGpu = NULL; + NV_STATUS status = NV_OK; + + NV_ASSERT_OR_RETURN(pGsync && pGsync->pExtDev, NV_ERR_INVALID_DEVICE); + + pGpu = gsyncGetMasterableGpu(pGsync); + + status = pGsync->gsyncHal.gsyncGetEmitTestSignal(pGpu, pGsync->pExtDev, + &pParams->bEmitTestSignal); + + return status; +} + +NV_STATUS +gsyncSetControlTesting(OBJGSYNC *pGsync, + NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS* pParams) +{ + OBJGPU *pGpu = NULL; + NV_STATUS status = NV_OK; + + NV_ASSERT_OR_RETURN(pGsync && pGsync->pExtDev, NV_ERR_INVALID_DEVICE); + + pGpu = gsyncGetMasterableGpu(pGsync); + + status = pGsync->gsyncHal.gsyncSetEmitTestSignal(pGpu, pGsync->pExtDev, + pParams->bEmitTestSignal); + + return status; +} + +NV_STATUS +gsyncSetControlWatchdog(OBJGSYNC *pGsync, + NV30F1_CTRL_GSYNC_SET_CONTROL_WATCHDOG_PARAMS* pParams) +{ + OBJGPU *pGpu = NULL; + NV_STATUS status = NV_OK; + + NV_ASSERT_OR_RETURN(pGsync && pGsync->pExtDev, NV_ERR_INVALID_DEVICE); + + pGpu = gsyncGetMasterableGpu(pGsync); + + // Client indicates it's taking care + // and doesn't want any automatic solution. + pGsync->bAutomaticWatchdogScheduling = NV_FALSE; + + status = pGsync->gsyncHal.gsyncSetWatchdog(pGpu, pGsync->pExtDev, + pParams->enable); + + return status; +} + +NV_STATUS +gsyncGetControlInterlaceMode(OBJGSYNC *pGsync, + NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS* pParams) +{ + OBJGPU *pGpu = NULL; + NV_STATUS status = NV_OK; + + NV_ASSERT_OR_RETURN(pGsync && pGsync->pExtDev, NV_ERR_INVALID_DEVICE); + + pGpu = gsyncGetMasterableGpu(pGsync); + + status = pGsync->gsyncHal.gsyncGetInterlaceMode(pGpu, pGsync->pExtDev, + &pParams->enable); + + return status; +} + +NV_STATUS +gsyncSetControlInterlaceMode(OBJGSYNC *pGsync, + NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS* pParams) +{ + OBJGPU *pGpu = NULL; + NV_STATUS status = NV_OK; + + NV_ASSERT_OR_RETURN(pGsync && pGsync->pExtDev, NV_ERR_INVALID_DEVICE); + + pGpu = gsyncGetMasterableGpu(pGsync); + + status = pGsync->gsyncHal.gsyncSetInterlaceMode(pGpu, pGsync->pExtDev, + pParams->enable); + + return status; +} + +NV_STATUS +gsyncGetControlSwapBarrier(OBJGSYNC *pGsync, OBJGPU *pGpu, + NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_BARRIER_PARAMS* pParams) +{ + REFTYPE rType = refFetchGet; + NV_STATUS status = NV_OK; + + NV_ASSERT_OR_RETURN(pGsync && pGsync->pExtDev, NV_ERR_INVALID_DEVICE); + + status = pGsync->gsyncHal.gsyncRefSwapBarrier(pGpu, pGsync->pExtDev, + rType, &pParams->enable); + + return status; +} + +NV_STATUS +gsyncSetControlSwapBarrier(OBJGSYNC *pGsync, OBJGPU *pGpu, + NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS* pParams) +{ + REFTYPE rType = refSetCommit; + NV_STATUS status = NV_OK; + + NV_ASSERT_OR_RETURN(pGsync && pGsync->pExtDev, NV_ERR_INVALID_DEVICE); + + status = pGsync->gsyncHal.gsyncRefSwapBarrier(pGpu, pGsync->pExtDev, + rType, &pParams->enable); + + return status; +} + +NV_STATUS +gsyncGetControlSwapLockWindow(OBJGSYNC *pGsync, + NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS* pParams) +{ + OBJGPU *pGpu = NULL; + NvU32 data = 0; + NV_STATUS status = NV_OK; + + NV_ASSERT_OR_RETURN(pGsync && pGsync->pExtDev, NV_ERR_INVALID_DEVICE); + + pGpu = gsyncGetMasterableGpu(pGsync); + if (pGpu == NULL) + { + return NV_ERR_GENERIC; + } + + if (osReadRegistryDword(pGpu, + NV_REG_STR_TIME_SWAP_RDY_HI_MODIFY_SWAP_LOCKOUT_START, &data) != NV_OK) + { + // Bug 967618 - default value for tSwapRdyHi is 250 micro seconds. + pParams->tSwapRdyHi = + NV_REG_STR_TIME_SWAP_RDY_HI_MODIFY_SWAP_LOCKOUT_START_DEFAULT; + } + else + { + // regkey added value for tSwapRdyHi i.e. swap lock window. + pParams->tSwapRdyHi = data; + } + + return status; +} + +NV_STATUS +gsyncGetOptimizedTiming(OBJGSYNC *pGsync, + NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS* pParams) +{ + OBJGPU *pGpu = NULL; + + NV_STATUS status = NV_OK; + + NV_ASSERT_OR_RETURN(pGsync && pGsync->pExtDev, NV_ERR_INVALID_DEVICE); + + pGpu = gpumgrGetGpuFromId(pParams->gpuId); + if (pGpu == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + status |= pGsync->gsyncHal.gsyncOptimizeTiming(pGpu, pParams); + + return status; +} + +NV_STATUS +gsyncGetControlStereoLockMode(OBJGSYNC *pGsync, + NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS *pParams) +{ + OBJGPU *pGpu = NULL; + NV_ASSERT_OR_RETURN(pGsync && pGsync->pExtDev, NV_ERR_INVALID_DEVICE); + + pGpu = gpumgrGetGpuFromId(pParams->gpuId); + if (pGpu == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + return pGsync->gsyncHal.gsyncGetStereoLockMode(pGpu, pGsync->pExtDev, + &pParams->enable); +} + +NV_STATUS +gsyncSetControlStereoLockMode(OBJGSYNC *pGsync, + NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS *pParams) +{ + OBJGPU *pGpu = NULL; + NV_ASSERT_OR_RETURN(pGsync && pGsync->pExtDev, NV_ERR_INVALID_DEVICE); + + pGpu = gpumgrGetGpuFromId(pParams->gpuId); + if (pGpu == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + return pGsync->gsyncHal.gsyncSetStereoLockMode(pGpu, pGsync->pExtDev, + pParams->enable); +} + +static NV_STATUS +gsyncReadRegister(OBJGSYNC *pGsync, + NV30F1_CTRL_GSYNC_READ_REGISTER_PARAMS *pParams) +{ + OBJGPU *pGpu = NULL; + NvU32 i; + + NV_ASSERT_OR_RETURN(pGsync && pGsync->pExtDev, NV_ERR_INVALID_DEVICE); + + for (i = 0; i < NV30F1_CTRL_MAX_GPUS_PER_GSYNC && i < pGsync->gpuCount; i++) + { + if (pParams->gpuId == pGsync->gpus[i].gpuId) + { + pGpu = gpumgrGetGpuFromId(pGsync->gpus[i].gpuId); + break; + } + } + + if (!pGpu) + { + return NV_ERR_INVALID_ARGUMENT; + } + + return readregu008_extdeviceTargeted(pGpu, + pGsync->pExtDev, + pParams->reg, + &pParams->data); +} + +static NV_STATUS +gsyncWriteRegister(OBJGSYNC *pGsync, + NV30F1_CTRL_GSYNC_WRITE_REGISTER_PARAMS *pParams) +{ + OBJGPU *pGpu = NULL; + NvU32 i; + + NV_ASSERT_OR_RETURN(pGsync && pGsync->pExtDev, NV_ERR_INVALID_DEVICE); + + for (i = 0; i < NV30F1_CTRL_MAX_GPUS_PER_GSYNC && i < pGsync->gpuCount; i++) + { + if (pParams->gpuId == pGsync->gpus[i].gpuId) + { + pGpu = gpumgrGetGpuFromId(pGsync->gpus[i].gpuId); + break; + } + } + + if (!pGpu) + { + return NV_ERR_INVALID_ARGUMENT; + } + + return writeregu008_extdeviceTargeted(pGpu, + pGsync->pExtDev, + pParams->reg, + pParams->data); +} + +NvBool +gsyncIsInstanceValid(NvU32 gsyncInstance) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync; + OBJGPU *pGpu; + DACEXTERNALDEVICE *pExtDev; + + if (gsyncInstance >= NV30F1_MAX_GSYNCS) + return NV_FALSE; + + pGsync = &pGsyncMgr->gsyncTable[gsyncInstance]; + + if (pGsync->gpuCount == 0) + return NV_FALSE; + + pGpu = gsyncGetMasterableGpu(pGsync); + // make sure we don't dereference a NULL ptr if the primary gpu + // was already freed. + if (pGpu == NULL) + return NV_FALSE; + + pExtDev = pGsync->pExtDev; + + return pExtDev->pI->Validate(pGpu,pExtDev); +} + + +// +// gsyncSignalServiceRequested +// +// Something has happened on this Gsync. Signal interested clients. +// +NV_STATUS +gsyncSignalServiceRequested(NvU32 gsyncInst, NvU32 eventFlags, NvU32 iface) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys); + OBJGSYNC *pGsync; + + if (gsyncInst >= NV30F1_MAX_GSYNCS) + return NV_ERR_GENERIC; + + pGsync = &pGsyncMgr->gsyncTable[gsyncInst]; + + if (pGsync->gpuCount == 0) + return NV_ERR_GENERIC; + + if (pGsync->bDoEventFiltering) + { + eventFlags = gsyncFilterEvents(eventFlags, iface); + } + + CliNotifyGsyncEvent(gsyncInst, eventFlags); + + return NV_OK; +} + +static NV_STATUS +gsyncGetHouseSyncMode(OBJGSYNC *pGsync, + NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS *pParams) +{ + OBJGPU *pGpu = NULL; + + NV_ASSERT_OR_RETURN(pGsync && pGsync->pExtDev, NV_ERR_INVALID_DEVICE); + + pGpu = gsyncGetMasterableGpu(pGsync); + + return pGsync->gsyncHal.gsyncGetHouseSyncMode(pGpu, pGsync->pExtDev, + &pParams->houseSyncMode); +} + +static NV_STATUS +gsyncSetHouseSyncMode(OBJGSYNC *pGsync, + NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS *pParams) +{ + OBJGPU *pGpu = NULL; + + NV_ASSERT_OR_RETURN(pGsync && pGsync->pExtDev, NV_ERR_INVALID_DEVICE); + + pGpu = gsyncGetMasterableGpu(pGsync); + + return pGsync->gsyncHal.gsyncSetHouseSyncMode(pGpu, pGsync->pExtDev, + pParams->houseSyncMode); +} + +static NvBool +gsyncNullGpuCanBeMaster +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev +) +{ + return NV_FALSE; +} + +static NV_STATUS +gsyncNullOptimizeTimingParameters +( + OBJGPU *pGpu, + GSYNCTIMINGPARAMS *pParams +) +{ + return NV_ERR_GENERIC; +} + +static NV_STATUS +gsyncNullGetStereoLockMode +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 *val +) +{ + return NV_ERR_GENERIC; +} + +static NV_STATUS +gsyncNullSetStereoLockMode +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 val +) +{ + return NV_ERR_GENERIC; +} + +static NV_STATUS +gsyncNullGetSyncPolarity +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + GSYNCSYNCPOLARITY *polarity +) +{ + return NV_ERR_GENERIC; +} + +static NV_STATUS +gsyncNullSetSyncPolarity +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + GSYNCSYNCPOLARITY polarity +) +{ + return NV_ERR_GENERIC; +} + +static NV_STATUS +gsyncNullGetVideoMode +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + GSYNCVIDEOMODE *videoMode +) +{ + return NV_ERR_GENERIC; +} + +static NV_STATUS +gsyncNullSetVideoMode +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + GSYNCVIDEOMODE videoMode +) +{ + return NV_ERR_GENERIC; +} + +static NV_STATUS +gsyncNullGetNSync +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 *count +) +{ + return NV_ERR_GENERIC; +} + +static NV_STATUS +gsyncNullSetNSync +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 count +) +{ + return NV_ERR_GENERIC; +} + +static NV_STATUS +gsyncNullGetSyncSkew +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 *skew +) +{ + return NV_ERR_GENERIC; +} + +static NV_STATUS +gsyncNullSetSyncSkew +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 skew +) +{ + return NV_ERR_GENERIC; +} + +static NV_STATUS +gsyncNullGetUseHouse +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 *val +) +{ + return NV_ERR_GENERIC; +} + +static NV_STATUS +gsyncNullSetUseHouse +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 val +) +{ + return NV_ERR_GENERIC; +} + +static NV_STATUS +gsyncNullGetSyncStartDelay +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 *delay +) +{ + return NV_ERR_GENERIC; +} + +static NV_STATUS +gsyncNullSetSyncStartDelay +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 delay +) +{ + return NV_ERR_GENERIC; +} + +static NV_STATUS +gsyncNullGetEmitTestSignal +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 *val +) +{ + return NV_ERR_GENERIC; +} + +static NV_STATUS +gsyncNullSetEmitTestSignal +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 val +) +{ + return NV_ERR_GENERIC; +} + +static NV_STATUS +gsyncNullGetInterlaceMode +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 *mode +) +{ + return NV_ERR_GENERIC; +} + +static NV_STATUS +gsyncNullSetInterlaceMode +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 mode +) +{ + return NV_ERR_GENERIC; +} + +static NV_STATUS +gsyncNullRefSwapBarrier +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + REFTYPE rType, + NvBool *enable +) +{ + return NV_ERR_GENERIC; +} + +static NV_STATUS +gsyncNullRefSignal +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + REFTYPE rType, + GSYNCSYNCSIGNAL Signal, + NvBool bRate, + NvU32 *pPresence +) +{ + return NV_ERR_GENERIC; +} + +static NV_STATUS +gsyncNullRefMaster +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + REFTYPE rType, + NvU32 *pDisplayMask, + NvU32 *pRefresh, + NvBool retainMaster, + NvBool skipSwapBarrierWar +) +{ + return NV_ERR_GENERIC; +} + +static NV_STATUS +gsyncNullRefSlaves +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + REFTYPE rType, + NvU32 *pDisplayMasks, + NvU32 *pRefresh +) +{ + return NV_ERR_GENERIC; +} + +static NV_STATUS +gsyncNullGetCplStatus +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + GSYNCSTATUS status, + NvU32 *pVal +) +{ + return NV_ERR_GENERIC; +} + +static NV_STATUS +gsyncNullSetWatchdog +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 pVal +) +{ + return NV_ERR_GENERIC; +} + +static NV_STATUS +gsyncNullGetRevision +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + GSYNCCAPSPARAMS *pParams +) +{ + return NV_ERR_GENERIC; +} + +static NV_STATUS +gsyncNullSetMosaic +( + OBJGPU *pSourceGpu, + PDACEXTERNALDEVICE pExtDev, + NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS *pParams +) +{ + return NV_ERR_GENERIC; +} + +static NV_STATUS +gsyncNullConfigFlashGsync +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU32 preFlash +) +{ + return NV_ERR_GENERIC; +} + +static NV_STATUS +gsyncNullGetHouseSyncMode +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU8* mode +) +{ + return NV_ERR_GENERIC; +} + +static NV_STATUS +gsyncNullSetHouseSyncMode +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDev, + NvU8 mode +) +{ + return NV_ERR_GENERIC; +} + +static NV_STATUS +gsyncSetupNullProvider(OBJGSYNCMGR *pGsyncMgr, NvU32 gsyncInst) +{ + OBJGSYNC *pGsync; + NV_STATUS status = NV_OK; + + NV_ASSERT(gsyncInst < NV30F1_MAX_GSYNCS); + + pGsync = &pGsyncMgr->gsyncTable[gsyncInst]; + + pGsync->connectorCount = 0; + + pGsync->gsyncHal.gsyncGpuCanBeMaster = gsyncNullGpuCanBeMaster; + pGsync->gsyncHal.gsyncOptimizeTiming = gsyncNullOptimizeTimingParameters; + pGsync->gsyncHal.gsyncGetStereoLockMode = gsyncNullGetStereoLockMode; + pGsync->gsyncHal.gsyncSetStereoLockMode = gsyncNullSetStereoLockMode; + + pGsync->gsyncHal.gsyncGetSyncPolarity = gsyncNullGetSyncPolarity; + pGsync->gsyncHal.gsyncSetSyncPolarity = gsyncNullSetSyncPolarity; + pGsync->gsyncHal.gsyncGetVideoMode = gsyncNullGetVideoMode; + pGsync->gsyncHal.gsyncSetVideoMode = gsyncNullSetVideoMode; + pGsync->gsyncHal.gsyncGetNSync = gsyncNullGetNSync; + pGsync->gsyncHal.gsyncSetNSync = gsyncNullSetNSync; + pGsync->gsyncHal.gsyncGetSyncSkew = gsyncNullGetSyncSkew; + pGsync->gsyncHal.gsyncSetSyncSkew = gsyncNullSetSyncSkew; + pGsync->gsyncHal.gsyncGetUseHouse = gsyncNullGetUseHouse; + pGsync->gsyncHal.gsyncSetUseHouse = gsyncNullSetUseHouse; + pGsync->gsyncHal.gsyncGetSyncStartDelay = gsyncNullGetSyncStartDelay; + pGsync->gsyncHal.gsyncSetSyncStartDelay = gsyncNullSetSyncStartDelay; + pGsync->gsyncHal.gsyncGetEmitTestSignal = gsyncNullGetEmitTestSignal; + pGsync->gsyncHal.gsyncSetEmitTestSignal = gsyncNullSetEmitTestSignal; + pGsync->gsyncHal.gsyncGetInterlaceMode = gsyncNullGetInterlaceMode; + pGsync->gsyncHal.gsyncSetInterlaceMode = gsyncNullSetInterlaceMode; + pGsync->gsyncHal.gsyncRefSwapBarrier = gsyncNullRefSwapBarrier; + pGsync->gsyncHal.gsyncRefSignal = gsyncNullRefSignal; + pGsync->gsyncHal.gsyncRefMaster = gsyncNullRefMaster; + pGsync->gsyncHal.gsyncRefSlaves = gsyncNullRefSlaves; + pGsync->gsyncHal.gsyncGetCplStatus = gsyncNullGetCplStatus; + pGsync->gsyncHal.gsyncSetWatchdog = gsyncNullSetWatchdog; + pGsync->gsyncHal.gsyncGetRevision = gsyncNullGetRevision; + pGsync->gsyncHal.gsyncSetMosaic = gsyncNullSetMosaic; + pGsync->gsyncHal.gsyncConfigFlashGsync = gsyncNullConfigFlashGsync; + pGsync->gsyncHal.gsyncGetHouseSyncMode = gsyncNullGetHouseSyncMode; + pGsync->gsyncHal.gsyncSetHouseSyncMode = gsyncNullSetHouseSyncMode; + + return status; +} + +// +// gsyncFilterEvents +// +// Perform event filtering. +// 1. Report stereo sync loss if both stereo sync loss and sync gain +// happen at the same time. +// 2. Report sync loss if both stereo sync loss and sync loss +// happen at the same time. +// 3. Report sync gain if both stero sync gain and sync gain +// happen at the same time. (Bug 580086) +// +NvU32 +gsyncFilterEvents +( + NvU32 eventFlags, + NvU32 iface +) +{ + if ((eventFlags & NVBIT(NV30F1_GSYNC_NOTIFIERS_SYNC_GAIN(iface))) && + (eventFlags & NVBIT(NV30F1_GSYNC_NOTIFIERS_STEREO_LOSS(iface)))) + { + // report only stereo sync loss + eventFlags &= ~NVBIT(NV30F1_GSYNC_NOTIFIERS_SYNC_GAIN(iface)); + } + + if ((eventFlags & NVBIT(NV30F1_GSYNC_NOTIFIERS_SYNC_LOSS(iface))) && + (eventFlags & NVBIT(NV30F1_GSYNC_NOTIFIERS_STEREO_LOSS(iface)))) + { + // report only sync loss + eventFlags &= ~NVBIT(NV30F1_GSYNC_NOTIFIERS_STEREO_LOSS(iface)); + } + + if ((eventFlags & NVBIT(NV30F1_GSYNC_NOTIFIERS_SYNC_GAIN(iface))) && + (eventFlags & NVBIT(NV30F1_GSYNC_NOTIFIERS_STEREO_GAIN(iface)))) + { + // report sync gain (bug 580086) + eventFlags &= ~NVBIT(NV30F1_GSYNC_NOTIFIERS_STEREO_GAIN(iface)); + } + + return eventFlags; +} + +// +// gsyncConvertNewEventToOldEventNum +// +// contevert new event numbers to old event numbers. +// +NvU32 +gsyncConvertNewEventToOldEventNum +( + NvU32 eventFlags +) +{ + NvU32 eventNum = 0; + NvU32 isEventOccured = 0; + NvU32 connectorCount; + + // SYNC_LOSS events + for (connectorCount = 0; connectorCount < NV30F1_GSYNC_CONNECTOR_COUNT; connectorCount++) + { + isEventOccured |= (eventFlags & NVBIT(NV30F1_GSYNC_NOTIFIERS_SYNC_LOSS(connectorCount))); + } + if (isEventOccured) + { + eventNum = eventNum | NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_SYNC_LOSS; + } + + // SYNC_GAIN events + isEventOccured = 0; + for (connectorCount = 0; connectorCount < NV30F1_GSYNC_CONNECTOR_COUNT; connectorCount++) + { + isEventOccured |= (eventFlags & NVBIT(NV30F1_GSYNC_NOTIFIERS_SYNC_GAIN(connectorCount))); + } + if (isEventOccured) + { + eventNum = eventNum | NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_SYNC_GAIN; + } + + // STEREO_GAIN events + isEventOccured = 0; + for (connectorCount = 0; connectorCount < NV30F1_GSYNC_CONNECTOR_COUNT; connectorCount++) + { + isEventOccured |= (eventFlags & NVBIT(NV30F1_GSYNC_NOTIFIERS_STEREO_GAIN(connectorCount))); + } + if (isEventOccured) + { + eventNum = eventNum | NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_STEREO_GAIN; + } + + // STEREO_LOSS events + isEventOccured = 0; + for (connectorCount = 0; connectorCount < NV30F1_GSYNC_CONNECTOR_COUNT; connectorCount++) + { + isEventOccured |= (eventFlags & NVBIT(NV30F1_GSYNC_NOTIFIERS_STEREO_LOSS(connectorCount))); + } + if (isEventOccured) + { + eventNum = eventNum | NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_STEREO_LOSS; + } + + // HOUSE_GAIN events + if (eventFlags & NVBIT(NV30F1_GSYNC_NOTIFIERS_HOUSE_GAIN)) + { + eventNum = eventNum | NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_HOUSE_GAIN; + } + + // HOUSE_LOSS events + if (eventFlags & NVBIT(NV30F1_GSYNC_NOTIFIERS_HOUSE_LOSS)) + { + eventNum = eventNum | NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_HOUSE_LOSS; + } + + // RJ45_GAIN events + if (eventFlags & NVBIT(NV30F1_GSYNC_NOTIFIERS_RJ45_GAIN)) + { + eventNum = eventNum | NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_RJ45_GAIN; + } + + // RJ45_LOSS events + if (eventFlags & NVBIT(NV30F1_GSYNC_NOTIFIERS_RJ45_LOSS)) + { + eventNum = eventNum | NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_RJ45_LOSS; + } + + return eventNum; +} + +#ifdef DEBUG +void +gsyncDbgPrintGsyncEvents(NvU32 DebugLevel, NvU32 events, NvU32 iface) +{ + if (events & NVBIT(NV30F1_GSYNC_NOTIFIERS_SYNC_LOSS(iface))) + NV_PRINTF_EX(NV_PRINTF_MODULE, DebugLevel, "SYNC_LOSS "); + if (events & NVBIT(NV30F1_GSYNC_NOTIFIERS_SYNC_GAIN(iface))) + NV_PRINTF_EX(NV_PRINTF_MODULE, DebugLevel, "SYNC_GAIN "); + if (events & NVBIT(NV30F1_GSYNC_NOTIFIERS_STEREO_LOSS(iface))) + NV_PRINTF_EX(NV_PRINTF_MODULE, DebugLevel, "STEREO_LOSS "); + if (events & NVBIT(NV30F1_GSYNC_NOTIFIERS_STEREO_GAIN(iface))) + NV_PRINTF_EX(NV_PRINTF_MODULE, DebugLevel, "STEREO_GAIN "); + if (events & NVBIT(NV30F1_GSYNC_NOTIFIERS_HOUSE_GAIN)) + NV_PRINTF_EX(NV_PRINTF_MODULE, DebugLevel, "HOUSE_GAIN "); + if (events & NVBIT(NV30F1_GSYNC_NOTIFIERS_HOUSE_LOSS)) + NV_PRINTF_EX(NV_PRINTF_MODULE, DebugLevel, "HOUSE LOSS "); + if (events & NVBIT(NV30F1_GSYNC_NOTIFIERS_RJ45_GAIN)) + NV_PRINTF_EX(NV_PRINTF_MODULE, DebugLevel, "RJ45 GAIN "); + if (events & NVBIT(NV30F1_GSYNC_NOTIFIERS_RJ45_LOSS)) + NV_PRINTF_EX(NV_PRINTF_MODULE, DebugLevel, "RJ45 LOSS "); +} +#endif // DEBUG + diff --git a/src/nvidia/src/kernel/gpu/external_device/gsync_api.c b/src/nvidia/src/kernel/gpu/external_device/gsync_api.c new file mode 100644 index 000000000..d2508e45c --- /dev/null +++ b/src/nvidia/src/kernel/gpu/external_device/gsync_api.c @@ -0,0 +1,264 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "core/core.h" + +#include "os/os.h" +#include "gpu/external_device/gsync.h" + +#include "gpu/external_device/gsync_api.h" +#include "rmapi/rs_utils.h" +#include "resserv/rs_client.h" + +NV_STATUS +gsyncapiConstruct_IMPL +( + GSyncApi *pGSyncApi, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + NV_STATUS status = NV_OK; + NV30F1_ALLOC_PARAMETERS *pNv30f1AllocParams = pParams->pAllocParams; + RmClient *pClient = dynamicCast(pCallContext->pClient, RmClient); + NvU32 eventNum = 0; + + RMCFG_FEATURE_ENABLED_OR_BAIL(EXTDEV_GSYNC); + + if (pClient == NULL) + { + return NV_ERR_INVALID_CLIENT; + } + + // validate gsync instance + if ( ! gsyncIsInstanceValid(pNv30f1AllocParams->gsyncInstance)) + return NV_ERR_INVALID_ARGUMENT; + + // init the gsync + pGSyncApi->instance = pNv30f1AllocParams->gsyncInstance; + pGSyncApi->classNum = NV30_GSYNC; + pGSyncApi->notifyAction = NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_DISABLE; + pGSyncApi->lastEventNotified = NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_SYNC_LOSS; + pGSyncApi->oldEventNotification = NV_FALSE; + + for (eventNum = 0; eventNum < NV30F1_CTRL_GSYNC_EVENT_TYPES; eventNum++) + { + pGSyncApi->pEventByType[eventNum] = NULL; + } + + return status; +} + +NV_STATUS +gsyncapiControl_IMPL +( + GSyncApi *pGSyncApi, + CALL_CONTEXT *pCallContext, + RS_RES_CONTROL_PARAMS_INTERNAL *pParams +) +{ + RMCFG_FEATURE_ENABLED_OR_BAIL(EXTDEV_GSYNC); + + if (gsyncIsInstanceValid(pGSyncApi->instance) == NV_FALSE) + return NV_ERR_INVALID_ARGUMENT; + + return resControl_IMPL(staticCast(pGSyncApi, RsResource), pCallContext, pParams->pLegacyParams); +} + +void +CliNotifyGsyncEvent +( + NvU32 gsyncInst, + NvU32 eventFlags +) +{ + RS_SHARE_ITERATOR it = serverutilShareIter(classId(NotifShare)); + + // RMCONFIG: is GYSNC enabled? + if ( ! RMCFG_FEATURE_EXTDEV_GSYNC) + { + NV_ASSERT(RMCFG_FEATURE_EXTDEV_GSYNC); + return; + } + + + // search notifiers with events hooked up for this gpu + while (serverutilShareIterNext(&it)) + { + RsShared *pShared = it.pShared; + GSyncApi *pGSyncApi; + INotifier *pNotifier; + NotifShare *pNotifierShare = dynamicCast(pShared, NotifShare); + PEVENTNOTIFICATION pEventNotification; + + if ((pNotifierShare == NULL) || (pNotifierShare->pNotifier == NULL)) + continue; + + pNotifier = pNotifierShare->pNotifier; + pGSyncApi = dynamicCast(pNotifier, GSyncApi); + + if (pGSyncApi == NULL) + continue; + + // If this is the gsync instance we're looking for and + // it's marked in use and the user has bound an event + // to it and the user has enabled event notification for + // it, then we're ready to signal the event... + // + // ...unless we're doing smart filtering, in which case + // we only notify if the event intersects the action mask, + // and is different from the last event we sent. + // + + if (pGSyncApi->instance != gsyncInst) + continue; + + pEventNotification = inotifyGetNotificationList(pNotifier); + + if (pGSyncApi->oldEventNotification) + { + // client is using old api + OBJGPU *pMasterableGpu = gsyncGetMasterableGpuByInstance(gsyncInst); + NvU32 oldEventFlags = gsyncConvertNewEventToOldEventNum(eventFlags); + NvU32 tempMask = oldEventFlags; + NvU32 eventNum = 0; + + // convert mask to array index (only one bit should be set) + while (tempMask >>= 1) + { + eventNum++; + } + + // now, look for an event to trigger + if (eventNum < NV30F1_CTRL_GSYNC_EVENT_TYPES) + { + pEventNotification = pGSyncApi->pEventByType[eventNum]; + } + + // + // Syncloss could also be a notifcation to reset the + // event notification tracking when enabling framelock. + // + if ((NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_SYNC_LOSS == oldEventFlags) && + (pEventNotification == NULL)) + { + // update smart event notification tracking when + // client is NOT registered for SYNC_LOSS + // Ref. CL 14042432 and bug 200668208 for details + pGSyncApi->lastEventNotified = oldEventFlags; + } + + if (pMasterableGpu && pEventNotification && + (pGSyncApi->notifyAction & oldEventFlags) && + (pGSyncApi->lastEventNotified != oldEventFlags)) + { + NV_PRINTF(LEVEL_INFO, + "gsync instance 0x%0x has had a status change: 0x%0x\n", + gsyncInst, oldEventFlags); + + osEventNotification( + pMasterableGpu, + pEventNotification, + OS_EVENT_NOTIFICATION_INDEX_ALL, + NULL, + 0); + + // update smart event notification tracking + pGSyncApi->lastEventNotified = oldEventFlags; + continue; + } + } + else + { + OBJGPU *pMasterableGpu = gsyncGetMasterableGpuByInstance(gsyncInst); + + if (pEventNotification == NULL) + continue; + + // + // Allowing NV30F1_GSYNC_NOTIFIERS_ALL to handle for all event types to make the + // interface generic. Though for Windows, NV01_EVENT_OS_EVENT can only signal an + // event but not handle over any information. + // + if (pEventNotification->NotifyType == NV01_EVENT_KERNEL_CALLBACK || + (pEventNotification->NotifyIndex == NV30F1_GSYNC_NOTIFIERS_ALL)) + { + NvNotification eventData; + portMemSet((void *)&eventData, 0, sizeof(NvNotification)); + eventData.info32 = eventFlags; + + NV_PRINTF(LEVEL_INFO, + "gsync instance 0x%0x has had a status change: 0x%0x\n", + gsyncInst, eventFlags); + + osEventNotification( + pMasterableGpu, + pEventNotification, + OS_EVENT_NOTIFICATION_INDEX_ALL, + (void *)&eventData, + sizeof(eventData)); + } + else + { + NvU32 notifyIndex; + + NV_ASSERT((pEventNotification->NotifyType == NV01_EVENT_KERNEL_CALLBACK_EX) || + (pEventNotification->NotifyType == NV01_EVENT_OS_EVENT)); + + for (notifyIndex = 0; eventFlags >> notifyIndex; notifyIndex++) + { + if (eventFlags & NVBIT(notifyIndex)) + { + NV_PRINTF(LEVEL_INFO, + "gsync instance 0x%0x has had a status change: %d\n", + gsyncInst, notifyIndex); + + if (pEventNotification->NotifyType == NV01_EVENT_OS_EVENT) + { + osObjectEventNotification( + pNotifierShare->hNotifierClient, + pNotifierShare->hNotifierResource, + pGSyncApi->classNum, pEventNotification, notifyIndex, NULL, 0); + } + else + { + NvNotification eventData; + portMemSet((void *)&eventData, 0, sizeof(NvNotification)); + eventData.info32 = notifyIndex; + + NV_ASSERT(pEventNotification->NotifyType == NV01_EVENT_KERNEL_CALLBACK_EX); + + osEventNotification( + pMasterableGpu, + pEventNotification, + notifyIndex, + (void *)&eventData, + sizeof(eventData)); + } + } + } + } + } + } +} + diff --git a/src/nvidia/src/kernel/gpu/external_device/kern_external_device.c b/src/nvidia/src/kernel/gpu/external_device/kern_external_device.c new file mode 100644 index 000000000..f9b11a8bd --- /dev/null +++ b/src/nvidia/src/kernel/gpu/external_device/kern_external_device.c @@ -0,0 +1,382 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "objtmr.h" +#include "gpu/external_device/gsync.h" + +#include "gpu/external_device/external_device.h" +#include "gpu_mgr/gpu_mgr.h" +#include "kernel/gpu/i2c/i2c_api.h" + +static +PDACEXTERNALDEVICE extdevGetExtDev +( + OBJGPU *pGpu +) +{ + if (RMCFG_FEATURE_EXTDEV_GSYNC) + { + OBJGSYNC *pGsync = gsyncmgrGetGsync(pGpu); + if (pGsync) + { + return pGsync->pExtDev; + } + } + + return NULL; +} + +// +// RMCONFIG: when the EXTDEV feature is disabled there are #defines in +// extdev.h that stub this routine out. +// +void extdevDestroy_Base(OBJGPU *pGpu, PDACEXTERNALDEVICE pExternalDevice) +{ + portMemFree(pExternalDevice->pI); +} + +static NvBool dacAttachExternalDevice_Base(OBJGPU *pGpu, PDACEXTERNALDEVICE *ppExtdevs) +{ + return NV_FALSE; +} + +PDACEXTERNALDEVICE +extdevConstruct_Base +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pThis +) +{ + // + // Alloc or find interface. + // Not being able to do so is fatal. + // + { + pThis->pI = portMemAllocNonPaged(sizeof(DACEXTERNALDEVICEIFACE)); + if (pThis->pI == NULL) + { + return 0; + } + portMemSet(pThis->pI, 0, sizeof(DACEXTERNALDEVICEIFACE)); + } + + // No parent constructor to call, we're the base class! + + // Setup interface(s) + { + pThis->pI->Destroy = extdevDestroy_Base; + pThis->pI->Attach = dacAttachExternalDevice_Base; + + pThis->pI->GetDevice = 0; + pThis->pI->Init = 0; + + pThis->pI->Validate = extdevValidate_Default; + } + + // Init data members + { + pThis->MaxGpus = 1; // default, only connect to 1 gpu + + pThis->WatchdogControl.Scheduled = NV_FALSE; + pThis->WatchdogControl.TimeOut = 1000000000; // 1 second in ns + } + + return pThis; +} + +void +extdevDestroy(OBJGPU *pGpu) +{ + OBJGSYNC *pGsync = NULL; + + if (RMCFG_FEATURE_EXTDEV_GSYNC) + { + // destroy gsync object if any + pGsync = gsyncmgrGetGsync(pGpu); + if (pGsync && pGsync->pExtDev) + { + pGsync->pExtDev->pI->Destroy(pGpu, pGsync->pExtDev); + if (pGsync->pExtDev->ReferenceCount == 0) + { + portMemFree(pGsync->pExtDev); + pGsync->pExtDev = NULL; + } + } + } +} + +// Schedule Watchdog +NV_STATUS extdevScheduleWatchdog +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDevice +) +{ + OBJTMR *pTmr = GPU_GET_TIMER(pGpu); + NV_STATUS rmStatus = NV_ERR_GENERIC; + + // make sure it isn't already scheduled + if (!pExtDevice->WatchdogControl.Scheduled) + { + pExtDevice->WatchdogControl.Scheduled = NV_TRUE; + + rmStatus = tmrScheduleCallbackRel( + pTmr, + extdevServiceWatchdog, + pExtDevice, + pExtDevice->WatchdogControl.TimeOut, + TMR_FLAG_RECUR, + 0); + + if (NV_OK != rmStatus) + { + pExtDevice->WatchdogControl.Scheduled = NV_FALSE; + } + } + + return rmStatus; +} + +// deSchedule Watchdog +NV_STATUS extdevCancelWatchdog +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDevice +) +{ + OBJTMR *pTmr = GPU_GET_TIMER(pGpu); + NV_STATUS rmStatus; + + // cancel first... + rmStatus = tmrCancelCallback(pTmr, pExtDevice); + + // ... then lower the flag! + pExtDevice->WatchdogControl.Scheduled = NV_FALSE; + + return rmStatus; +} + +// Service the Watchdog +NV_STATUS extdevServiceWatchdog +( + OBJGPU *pGpu, + OBJTMR *pTmr, + void *_pComponent +) +{ + PDACEXTERNALDEVICE pExtDevice = NULL; + PDACEXTERNALDEVICEIFACE pdsif = NULL; + + pExtDevice = extdevGetExtDev(pGpu); + + // No gsync and no gvo, return NV_ERR_GENERIC + if (!pExtDevice) + { + return NV_ERR_GENERIC; + } + + pdsif = pExtDevice->pI; + + // lower the flag, since it's no longer waiting to run + pExtDevice->WatchdogControl.Scheduled = NV_FALSE; + + return pdsif->Watchdog(pGpu, pTmr, pExtDevice); +} + +// Trivial validation +NvBool extdevValidate_Default +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pExtDevice +) +{ + if (!pExtDevice) + { + return NV_FALSE; + } + + return NV_TRUE; +} + +NV_STATUS +writeregu008_extdevice +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pThis, + NvU8 SubAdr, + NvU8 Data +) +{ + + NV_STATUS status = NV_ERR_GENERIC; + + NvU32 i2cPort = (pGpu->i2cPortForExtdev < NV402C_CTRL_NUM_I2C_PORTS) ? pGpu->i2cPortForExtdev : pThis->I2CPort; + status = i2c_extdeviceHelper(pGpu, pThis, i2cPort, SubAdr, &Data, NV_TRUE); + + return status; +} + +// +// This is a wrapper function for writeregu008_extdevice to be used when a +// specific GPU is to be targeted (rather than an SLI abstraction). For +// example, a P294 framelock board has two connectors to gpus, one for a +// primary gpu and one for a secondary gpu. It is only valid to read and +// write registers over i2c connected to the primary gpu. If the MC_PARENT +// is not the same gpu as the primary, the ThisGpuFromHal macro at the +// beginning of writeregu008_extdevice will return the secondary gpu unless +// the primary gpu is specifically loaded beforehand. +// This wrapper does that loading. +// +NV_STATUS +writeregu008_extdeviceTargeted +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pThis, + NvU8 SubAdr, + NvU8 Data +) +{ + NV_STATUS status = NV_ERR_GENERIC; + NvBool bcState; + + if (!pGpu) + { + return status; + } + + bcState = gpumgrGetBcEnabledStatus(pGpu); + + gpumgrSetBcEnabledStatus(pGpu, NV_FALSE); + status = writeregu008_extdevice(pGpu, pThis, SubAdr, Data); + gpumgrSetBcEnabledStatus(pGpu, bcState); + + return status; +} + +NV_STATUS +readregu008_extdevice +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pThis, + NvU8 SubAdr, + NvU8 *pData +) +{ + + NV_STATUS status = NV_ERR_GENERIC; + + NvU32 i2cPort = (pGpu->i2cPortForExtdev < NV402C_CTRL_NUM_I2C_PORTS) ? pGpu->i2cPortForExtdev : pThis->I2CPort; + status = i2c_extdeviceHelper(pGpu, pThis, i2cPort, SubAdr, pData, NV_FALSE); + + return status; +} + +// +// This is a wrapper function for readregu008_extdevice to be used when a +// specific GPU is to be targeted (rather than an SLI abstraction). For +// example, a P294 framelock board has two connectors to gpus, one for a +// primary gpu and one for a secondary gpu. It is only valid to read and +// write registers over i2c connected to the primary gpu. If the MC_PARENT +// is not the same gpu as the primary, the ThisGpuFromHal macro at the +// beginning of readregu008_extdevice will return the secondary gpu unless +// the primary gpu is specifically loaded beforehand. +// This wrapper does that loading. +// +NV_STATUS +readregu008_extdeviceTargeted +( + OBJGPU *pGpu, + PDACEXTERNALDEVICE pThis, + NvU8 SubAdr, + NvU8 *pData +) +{ + NV_STATUS status = NV_ERR_GENERIC; + NvBool bcState; + + if (!pGpu) + { + return status; + } + + bcState = gpumgrGetBcEnabledStatus(pGpu); + + gpumgrSetBcEnabledStatus(pGpu, NV_FALSE); + status = readregu008_extdevice(pGpu, pThis, SubAdr, pData); + gpumgrSetBcEnabledStatus(pGpu, bcState); + + return status; +} + +void +extdevGsyncService +( + OBJGPU *pGpu, + NvU8 lossRegStatus, + NvU8 gainRegStatus, + NvU8 miscRegStatus, + NvBool rmStatus +) +{ + PDACEXTERNALDEVICE pExtDevice = NULL; + PDACEXTERNALDEVICEIFACE pdsif = NULL; + + pExtDevice = extdevGetExtDev(pGpu); + if (!pExtDevice) + return; + + pdsif = pExtDevice->pI; + + pdsif->Service(pGpu, pExtDevice, lossRegStatus, gainRegStatus, miscRegStatus, rmStatus); +} + +void +extdevGetBoundHeadsAndDisplayIds +( + OBJGPU *pGpu, + NvU32 *pDisplayId +) +{ + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NvU32 hClient = pGpu->hInternalClient; + NvU32 hSubdevice = pGpu->hInternalSubdevice; + NV_STATUS status = NV_OK; + NV2080_CTRL_INTERNAL_GSYNC_GET_DISPLAY_IDS_PARAMS ctrlParams = {0}; + + portMemSet(pDisplayId, 0, OBJ_MAX_HEADS * sizeof(NvU32)); + + status = pRmApi->Control(pRmApi, hClient, hSubdevice, + NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_DISPLAY_IDS, + &ctrlParams, sizeof(ctrlParams)); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Extdev getting display IDs have failed!\n"); + } + else + { + portMemCopy(pDisplayId, OBJ_MAX_HEADS * sizeof(NvU32), ctrlParams.displayIds, + OBJ_MAX_HEADS * sizeof(NvU32)); + } +} + diff --git a/src/nvidia/src/kernel/gpu/falcon/kernel_falcon.c b/src/nvidia/src/kernel/gpu/falcon/kernel_falcon.c index 1f31038e2..fb2d1fcca 100644 --- a/src/nvidia/src/kernel/gpu/falcon/kernel_falcon.c +++ b/src/nvidia/src/kernel/gpu/falcon/kernel_falcon.c @@ -184,7 +184,7 @@ static NV_STATUS _kflcnPromoteContext RsClient *pClient = RES_GET_CLIENT(pKernelChannel); Subdevice *pSubdevice; NvU64 addr; - NvU32 engineType; + RM_ENGINE_TYPE rmEngineType; ENGINE_CTX_DESCRIPTOR *pEngCtx; NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS rmCtrlParams = {0}; @@ -197,14 +197,14 @@ static NV_STATUS _kflcnPromoteContext NV_ASSERT_OK_OR_RETURN(kfifoEngineInfoXlate_HAL(pGpu, GPU_GET_KERNEL_FIFO(pGpu), ENGINE_INFO_TYPE_ENG_DESC, pKernelFalcon->physEngDesc, - ENGINE_INFO_TYPE_NV2080, &engineType)); + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, (NvU32 *)&rmEngineType)); rmCtrlParams.hClient = pClient->hClient; rmCtrlParams.hObject = RES_GET_HANDLE(pKernelChannel); rmCtrlParams.hChanClient = pClient->hClient; rmCtrlParams.virtAddress = addr; rmCtrlParams.size = pKernelFalcon->ctxBufferSize; - rmCtrlParams.engineType = engineType; + rmCtrlParams.engineType = gpuGetNv2080EngineType(rmEngineType); rmCtrlParams.ChID = pKernelChannel->ChID; NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, pClient->hClient, RES_GET_HANDLE(pSubdevice), @@ -332,33 +332,37 @@ void gkflcnRegisterIntrService_IMPL(OBJGPU *pGpu, GenericKernelFalcon *pGenericK NV_STATUS gkflcnServiceNotificationInterrupt_IMPL(OBJGPU *pGpu, GenericKernelFalcon *pGenericKernelFalcon, IntrServiceServiceNotificationInterruptArguments *pParams) { NvU32 idxMc = pParams->engineIdx; - NvU32 idx2080 = NV2080_ENGINE_TYPE_NULL; + RM_ENGINE_TYPE rmEngineType = RM_ENGINE_TYPE_NULL; NV_PRINTF(LEVEL_INFO, "nonstall intr for MC 0x%x\n", idxMc); if (MC_ENGINE_IDX_NVDECn(0) <= idxMc && - idxMc < MC_ENGINE_IDX_NVDECn(NV2080_ENGINE_TYPE_NVDEC_SIZE)) + idxMc < MC_ENGINE_IDX_NVDECn(RM_ENGINE_TYPE_NVDEC_SIZE)) { NvU32 nvdecIdx = idxMc - MC_ENGINE_IDX_NVDECn(0); - idx2080 = NV2080_ENGINE_TYPE_NVDEC(nvdecIdx); - } else if (idxMc == MC_ENGINE_IDX_OFA0) - idx2080 = NV2080_ENGINE_TYPE_OFA; + rmEngineType = RM_ENGINE_TYPE_NVDEC(nvdecIdx); + } + else if (idxMc == MC_ENGINE_IDX_OFA0) + { + rmEngineType = RM_ENGINE_TYPE_OFA; + } else if (MC_ENGINE_IDX_NVJPEGn(0) <= idxMc && - idxMc < MC_ENGINE_IDX_NVJPEGn(NV2080_ENGINE_TYPE_NVJPEG_SIZE)) + idxMc < MC_ENGINE_IDX_NVJPEGn(RM_ENGINE_TYPE_NVJPEG_SIZE)) { NvU32 nvjpgIdx = idxMc - MC_ENGINE_IDX_NVJPEGn(0); - idx2080 = NV2080_ENGINE_TYPE_NVJPEG(nvjpgIdx); - } else if (MC_ENGINE_IDX_MSENCn(0) <= idxMc && - idxMc < MC_ENGINE_IDX_MSENCn(NV2080_ENGINE_TYPE_NVENC_SIZE)) + rmEngineType = RM_ENGINE_TYPE_NVJPEG(nvjpgIdx); + } + else if (MC_ENGINE_IDX_MSENCn(0) <= idxMc && + idxMc < MC_ENGINE_IDX_MSENCn(RM_ENGINE_TYPE_NVENC_SIZE)) { NvU32 msencIdx = idxMc - MC_ENGINE_IDX_MSENCn(0); - idx2080 = NV2080_ENGINE_TYPE_NVENC(msencIdx); + rmEngineType = RM_ENGINE_TYPE_NVENC(msencIdx); } - NV_ASSERT_OR_RETURN(idx2080 != NV2080_ENGINE_TYPE_NULL, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(rmEngineType != RM_ENGINE_TYPE_NULL, NV_ERR_INVALID_STATE); // Wake up channels waiting on this event - engineNonStallIntrNotify(pGpu, idx2080); + engineNonStallIntrNotify(pGpu, rmEngineType); return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/ampere/kernel_fifo_ga100.c b/src/nvidia/src/kernel/gpu/fifo/arch/ampere/kernel_fifo_ga100.c index a756011cf..445946e56 100644 --- a/src/nvidia/src/kernel/gpu/fifo/arch/ampere/kernel_fifo_ga100.c +++ b/src/nvidia/src/kernel/gpu/fifo/arch/ampere/kernel_fifo_ga100.c @@ -86,22 +86,23 @@ kfifoEngineInfoXlate_GA100 { subctxId = inVal - baseGrFaultId; NV_ASSERT_OK_OR_RETURN(kgrmgrGetGrIdxForVeid(pGpu, pKernelGraphicsManager, subctxId, &grIdx)); - inVal = NV2080_ENGINE_TYPE_GR(grIdx); - inType = ENGINE_INFO_TYPE_NV2080; + inVal = RM_ENGINE_TYPE_GR(grIdx); + inType = ENGINE_INFO_TYPE_RM_ENGINE_TYPE; } } if (outType == ENGINE_INFO_TYPE_MMU_FAULT_ID) { - NvU32 engineId, grIdx, startSubctxId; + NvU32 grIdx, startSubctxId; + RM_ENGINE_TYPE rmEngineType; NV_ASSERT_OK_OR_RETURN(kfifoEngineInfoXlate_GV100(pGpu, pKernelFifo, inType, inVal, - ENGINE_INFO_TYPE_NV2080, &engineId)); + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, (NvU32 *)&rmEngineType)); - // check if engineId corresponding to input is GR - if (NV2080_ENGINE_TYPE_IS_GR(engineId)) + // check if rmEngineType corresponding to input is GR + if (RM_ENGINE_TYPE_IS_GR(rmEngineType)) { - grIdx = NV2080_ENGINE_TYPE_GR_IDX(engineId); + grIdx = RM_ENGINE_TYPE_GR_IDX(rmEngineType); NV_ASSERT_OK_OR_RETURN(kgrmgrGetVeidBaseForGrIdx(pGpu, pKernelGraphicsManager, grIdx, &startSubctxId)); *pOutVal = baseGrFaultId + startSubctxId; return NV_OK; @@ -135,10 +136,9 @@ kfifoChannelGroupGetLocalMaxSubcontext_GA100 NV_ASSERT_OR_RETURN(pKernelChannelGroup != NULL, NV_ERR_INVALID_ARGUMENT); if (IS_MIG_IN_USE(pGpu) && !bLegacyMode && - NV2080_ENGINE_TYPE_IS_GR(pKernelChannelGroup->engineType)) + RM_ENGINE_TYPE_IS_GR(pKernelChannelGroup->engineType)) { - NvU32 grIdx = NV2080_ENGINE_TYPE_GR_IDX( - pKernelChannelGroup->engineType); + NvU32 grIdx = RM_ENGINE_TYPE_GR_IDX(pKernelChannelGroup->engineType); return nvPopCount64(pKernelGraphicsManager->grIdxVeidMask[grIdx]); } @@ -238,9 +238,10 @@ kfifoGenerateWorkSubmitToken_GA100 chId = pKernelChannel->ChID; - if (!RMCFG_FEATURE_PLATFORM_GSP) + NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &gfId)); + + if (!RMCFG_FEATURE_PLATFORM_GSP || (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && IS_GFID_VF(gfId))) { - NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &gfId)); // TODO: Remove check on Ampere. Bug 200606706. if (!bUsedForHost && IS_GFID_VF(gfId)) @@ -330,7 +331,7 @@ kfifoGetMaxCeChannelGroups_GA100 // All GR CE use the same pool as GR if ((eng == ENG_GR(0)) || (IS_CE(eng) && - (!ceIsCeGrce(pGpu, pEngineInfo->engineInfoList[deviceIndex].engineData[ENGINE_INFO_TYPE_NV2080])))) + (!ceIsCeGrce(pGpu, pEngineInfo->engineInfoList[deviceIndex].engineData[ENGINE_INFO_TYPE_RM_ENGINE_TYPE])))) { maxCeChannels += kfifoRunlistQueryNumChannels_HAL(pGpu, pKernelFifo, 0); } diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/hopper/kernel_fifo_gh100.c b/src/nvidia/src/kernel/gpu/fifo/arch/hopper/kernel_fifo_gh100.c index 7dc36150f..cd534d93b 100644 --- a/src/nvidia/src/kernel/gpu/fifo/arch/hopper/kernel_fifo_gh100.c +++ b/src/nvidia/src/kernel/gpu/fifo/arch/hopper/kernel_fifo_gh100.c @@ -112,28 +112,3 @@ kfifoGetMmioUsermodeSize_GH100 { return bPriv ? DRF_SIZE(NV_VIRTUAL_FUNCTION_PRIV) : DRF_SIZE(NV_VIRTUAL_FUNCTION); } - -/** - * @brief Returns the maximum possible number of runlists. - * - * Returns a number which represents the limit of any runlistId indexed - * registers in hardware. Does not necessarily return how many runlists are - * active. In the range of 0..kfifoGetMaxNumRunlists() there may be runlists - * that are not used. - * - * @param pGpu - * @param pKernelFifo - */ -NvU32 -kfifoGetMaxNumRunlists_GH100 -( - OBJGPU *pGpu, - KernelFifo *pKernelFifo) -{ - const ENGINE_INFO *pEngineInfo = kfifoGetEngineInfo(pKernelFifo); - - // We use bit-masks of these values - NV_ASSERT(pEngineInfo->maxNumRunlists <= 36); - - return pEngineInfo->maxNumRunlists; -} diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/hopper/usermode_api_gh100.c b/src/nvidia/src/kernel/gpu/fifo/arch/hopper/usermode_api_gh100.c index 4a1348bcf..43f8ea451 100644 --- a/src/nvidia/src/kernel/gpu/fifo/arch/hopper/usermode_api_gh100.c +++ b/src/nvidia/src/kernel/gpu/fifo/arch/hopper/usermode_api_gh100.c @@ -102,6 +102,8 @@ usrmodeConstructHal_GH100 status = memCreateMemDesc(pGpu, &pMemDesc, bBar1Mapping ? ADDR_SYSMEM : ADDR_REGMEM, offset, size, attr, attr2); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, status); + if (bBar1Mapping) { memdescSetPteKind(pMemDesc, memmgrGetMessageKind_HAL(pGpu, pMemoryManager)); diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_channel_gm107.c b/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_channel_gm107.c index 57bddbefe..50a2f4ebe 100644 --- a/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_channel_gm107.c +++ b/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_channel_gm107.c @@ -27,6 +27,7 @@ #include "kernel/mem_mgr/mem.h" #include "kernel/gpu/mem_sys/kern_mem_sys.h" #include "gpu/mem_mgr/mem_mgr.h" +#include "gpu/mem_mgr/mem_desc.h" #include "class/cl906f.h" @@ -52,7 +53,7 @@ kchannelGetClassEngineID_GM107 NvHandle handle, NvU32 *pClassEngineID, NvU32 *pClassID, - NvU32 *pEngineID + RM_ENGINE_TYPE *pRmEngineID ) { NV_STATUS status = NV_OK; @@ -84,7 +85,7 @@ kchannelGetClassEngineID_GM107 return NV_ERR_OBJECT_NOT_FOUND; } - status = gpuXlateEngDescToClientEngineId(pGpu, halEngineTag, pEngineID); + status = gpuXlateEngDescToClientEngineId(pGpu, halEngineTag, pRmEngineID); if (status == NV_OK) { @@ -282,6 +283,7 @@ NV_STATUS kchannelAllocMem_GM107 SLI_LOOP_BREAK; } + memdescSetName(pGpu, pInstanceBlock->pInstanceBlockDesc, NV_RM_SURF_NAME_INSTANCE_BLOCK, NULL); } else { @@ -399,11 +401,8 @@ kchannelDestroyMem_GM107 } // Remove USERD memDescs - if (pKernelChannel->pInstSubDeviceMemDesc[subdevInst] != NULL) - { - memdescDestroy(pKernelChannel->pInstSubDeviceMemDesc[subdevInst]); - pKernelChannel->pInstSubDeviceMemDesc[subdevInst] = NULL; - } + memdescDestroy(pKernelChannel->pInstSubDeviceMemDesc[subdevInst]); + pKernelChannel->pInstSubDeviceMemDesc[subdevInst] = NULL; SLI_LOOP_END diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_channel_group_gm107.c b/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_channel_group_gm107.c index c19669ca9..eb536beda 100644 --- a/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_channel_group_gm107.c +++ b/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_channel_group_gm107.c @@ -42,12 +42,12 @@ kchangrpGetDefaultRunlist_GM107 NvU32 runlistId = INVALID_RUNLIST_ID; ENGDESCRIPTOR engDesc = ENG_GR(0); - if (NV2080_ENGINE_TYPE_IS_VALID(pKernelChannelGroup->engineType)) + if (RM_ENGINE_TYPE_IS_VALID(pKernelChannelGroup->engineType)) { // if translation fails, default is GR0 NV_ASSERT_OK(kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, - ENGINE_INFO_TYPE_NV2080, - pKernelChannelGroup->engineType, + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, + (NvU32)pKernelChannelGroup->engineType, ENGINE_INFO_TYPE_ENG_DESC, &engDesc)); } diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_fifo_gm107.c b/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_fifo_gm107.c index 1695a4b83..311ee6414 100644 --- a/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_fifo_gm107.c +++ b/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_fifo_gm107.c @@ -362,25 +362,25 @@ kfifoGetInstBlkSizeAlign_GM107 * * @param[in] pGpu * @param[in] pKernelFifo - * @param[in] engineType - Engine type of the channel to retrieve default runlist id for + * @param[in] rmEngineType - Engine type of the channel to retrieve default runlist id for */ NvU32 kfifoGetDefaultRunlist_GM107 ( OBJGPU *pGpu, KernelFifo *pKernelFifo, - NvU32 engineType + RM_ENGINE_TYPE rmEngineType ) { NvU32 runlistId = INVALID_RUNLIST_ID; ENGDESCRIPTOR engDesc = ENG_GR(0); - if (NV2080_ENGINE_TYPE_IS_VALID(engineType)) + if (RM_ENGINE_TYPE_IS_VALID(rmEngineType)) { // if translation fails, defualt is ENG_GR(0) NV_ASSERT_OK( kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, - ENGINE_INFO_TYPE_NV2080, engineType, + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, (NvU32)rmEngineType, ENGINE_INFO_TYPE_ENG_DESC, &engDesc)); } @@ -622,7 +622,7 @@ kfifoConvertInstToKernelChannel_GM107 NV_MMU_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY); memdescCreateExisting(&instMemDesc, pGpu, NV_RAMIN_ALLOC_SIZE, - ADDR_UNKNOWN, NV_MEMORY_UNCACHED, + instAperture, NV_MEMORY_UNCACHED, MEMDESC_FLAGS_OWNED_BY_CURRENT_DEVICE); memdescDescribe(&instMemDesc, instAperture, pInst->address, NV_RAMIN_ALLOC_SIZE); @@ -869,9 +869,6 @@ kfifoGetMaxNumRunlists_GM107 { const ENGINE_INFO *pEngineInfo = kfifoGetEngineInfo(pKernelFifo); - // We use bit-masks of these values - NV_ASSERT(pEngineInfo->maxNumRunlists <= 32); - return pEngineInfo->maxNumRunlists; } @@ -941,7 +938,6 @@ kfifoGetEnginePartnerList_GM107 NvU32 i; NvU32 srcRunlist; NvU32 runlist; - NvU32 nv2080type; NvU32 *pSrcPbdmaIds; NvU32 numSrcPbdmaIds; NvU32 srcPbdmaId; @@ -949,19 +945,20 @@ kfifoGetEnginePartnerList_GM107 NvU32 numPbdmaIds; NvU32 numClasses = 0; ENGDESCRIPTOR engDesc; + RM_ENGINE_TYPE rmEngineType = gpuGetRmEngineType(pPartnerListParams->engineType); if (pPartnerListParams->runqueue >= kfifoGetNumRunqueues_HAL(pGpu, pKernelFifo)) return NV_ERR_INVALID_ARGUMENT; NV_ASSERT_OK_OR_RETURN(kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, - ENGINE_INFO_TYPE_NV2080, - pPartnerListParams->engineType, + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, + (NvU32)rmEngineType, ENGINE_INFO_TYPE_RUNLIST, &srcRunlist)); NV_ASSERT_OK_OR_RETURN(kfifoGetEnginePbdmaIds_HAL(pGpu, pKernelFifo, - ENGINE_INFO_TYPE_NV2080, - pPartnerListParams->engineType, + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, + (NvU32)rmEngineType, &pSrcPbdmaIds, &numSrcPbdmaIds)); @@ -1000,6 +997,7 @@ kfifoGetEnginePartnerList_GM107 if (runlist == srcRunlist) { NvU32 j; + RM_ENGINE_TYPE localRmEngineType; NV_ASSERT_OK_OR_RETURN(kfifoGetEnginePbdmaIds_HAL(pGpu, pKernelFifo, ENGINE_INFO_TYPE_INVALID, i, @@ -1011,12 +1009,13 @@ kfifoGetEnginePartnerList_GM107 { NV_ASSERT_OK_OR_RETURN(kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, ENGINE_INFO_TYPE_INVALID, i, - ENGINE_INFO_TYPE_NV2080, &nv2080type)); + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, (NvU32 *)&localRmEngineType)); // Don't include input in output list - if (nv2080type != pPartnerListParams->engineType) + if (localRmEngineType != rmEngineType) { - pPartnerListParams->partnerList[pPartnerListParams->numPartners++] = nv2080type; + pPartnerListParams->partnerList[pPartnerListParams->numPartners++] = + gpuGetNv2080EngineType(localRmEngineType); if (pPartnerListParams->numPartners >= NV2080_CTRL_GPU_MAX_ENGINE_PARTNERS) return NV_ERR_INVALID_ARGUMENT; diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_group_gv100.c b/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_group_gv100.c index 8a735c55d..9051685d5 100644 --- a/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_group_gv100.c +++ b/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_group_gv100.c @@ -24,6 +24,7 @@ #include "kernel/gpu/fifo/kernel_channel_group.h" #include "kernel/gpu/mem_mgr/mem_mgr.h" #include "kernel/virtualization/hypervisor/hypervisor.h" +#include "gpu/mem_mgr/mem_desc.h" #include "nvRmReg.h" @@ -119,6 +120,8 @@ kchangrpAllocFaultMethodBuffers_GV100 goto fail; } + memdescSetName(pGpu, pFaultMthdBuf->pMemDesc, NV_RM_SURF_NAME_CE_FAULT_METHOD_BUFFER, NULL); + // Map the buffer to RM pRmMapAddr = kbusMapRmAperture_HAL(pGpu, pFaultMthdBuf->pMemDesc); if (!pRmMapAddr) diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_gv100.c b/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_gv100.c index 79b31c7d8..4188a9ff2 100644 --- a/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_gv100.c +++ b/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_gv100.c @@ -97,7 +97,7 @@ kchannelCreateUserdMemDescBc_GV100 "User provided memory info for index %d is NULL\n", iter); NV_PRINTF(LEVEL_ERROR, - "NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS needs to have all subdevice info\n"); + "NV_CHANNEL_ALLOC_PARAMS needs to have all subdevice info\n"); hUserdMemory = phUserdMemory[0]; userdOffset = pUserdOffset[0]; @@ -269,7 +269,7 @@ kchannelCreateUserdMemDesc_GV100 * @brief Delete the memory descriptors for userd memory allocated * by client */ -NV_STATUS +void kchannelDestroyUserdMemDesc_GV100 ( OBJGPU *pGpu, @@ -278,11 +278,6 @@ kchannelDestroyUserdMemDesc_GV100 { NvU32 subdevInst = gpumgrGetSubDeviceInstanceFromGpu(pGpu); - if (pKernelChannel->pUserdSubDeviceMemDesc[subdevInst]) - { - memdescDestroy(pKernelChannel->pUserdSubDeviceMemDesc[subdevInst]); - pKernelChannel->pUserdSubDeviceMemDesc[subdevInst] = NULL; - } - - return NV_OK; + memdescDestroy(pKernelChannel->pUserdSubDeviceMemDesc[subdevInst]); + pKernelChannel->pUserdSubDeviceMemDesc[subdevInst] = NULL; } diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/volta/usermode_api_gv100.c b/src/nvidia/src/kernel/gpu/fifo/arch/volta/usermode_api_gv100.c index ee1c88bbe..5d30b7d4e 100644 --- a/src/nvidia/src/kernel/gpu/fifo/arch/volta/usermode_api_gv100.c +++ b/src/nvidia/src/kernel/gpu/fifo/arch/volta/usermode_api_gv100.c @@ -55,6 +55,8 @@ usrmodeConstructHal_GV100 status = memCreateMemDesc(pGpu, &pMemDesc, ADDR_REGMEM, offset, size, attr, attr2); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, status); + memdescSetFlag(pMemDesc, MEMDESC_FLAGS_SKIP_REGMEM_PRIV_CHECK, NV_TRUE); status = memConstructCommon(pMemory, NV01_MEMORY_LOCAL_PRIVILEGED, diff --git a/src/nvidia/src/kernel/gpu/fifo/channel_descendant.c b/src/nvidia/src/kernel/gpu/fifo/channel_descendant.c index 5af82ca56..12d00f0c5 100644 --- a/src/nvidia/src/kernel/gpu/fifo/channel_descendant.c +++ b/src/nvidia/src/kernel/gpu/fifo/channel_descendant.c @@ -62,7 +62,7 @@ chandesConstruct_IMPL // Bad class creation can happen when GPU is in low power because class DB is invalid NV_ASSERT(gpuIsGpuFullPower(pGpu)); - NV_ASSERT(rmApiLockIsOwner() && rmGpuLockIsOwner()); + NV_ASSERT(rmapiLockIsOwner() && rmGpuLockIsOwner()); // // If debug mode is enabled on this GPU, check if the GPU is occupied by a @@ -83,7 +83,7 @@ chandesConstruct_IMPL // engineType set in channel // if (kfifoIsPerRunlistChramEnabled(pKernelFifo) && - (kchannelGetEngineType(pKernelChannel) == NV2080_ENGINE_TYPE_NULL)) + (!RM_ENGINE_TYPE_IS_VALID(kchannelGetEngineType(pKernelChannel)))) { NV_PRINTF(LEVEL_ERROR, "Channel should have engineType associated with it\n"); @@ -99,7 +99,7 @@ chandesConstruct_IMPL // be removed once we move to per engine chid management. // if (kfifoIsHostEngineExpansionSupported(pKernelFifo) && - NV2080_ENGINE_TYPE_IS_VALID(kchannelGetEngineType(pKernelChannel)) && + RM_ENGINE_TYPE_IS_VALID(kchannelGetEngineType(pKernelChannel)) && (gpuIsCCorApmFeatureEnabled(pGpu) || bMIGInUse)) { if (rmapiutilIsExternalClassIdInternalOnly(pParams->externalClassId)) @@ -114,7 +114,7 @@ chandesConstruct_IMPL // NV_ASSERT_OK_OR_RETURN( kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, - ENGINE_INFO_TYPE_NV2080, kchannelGetEngineType(pKernelChannel), + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, (NvU32)kchannelGetEngineType(pKernelChannel), ENGINE_INFO_TYPE_ENG_DESC, &engDesc)); portMemSet(&internalClassDescriptor, 0, sizeof(internalClassDescriptor)); internalClassDescriptor.externalClassId = pParams->externalClassId; @@ -128,26 +128,26 @@ chandesConstruct_IMPL if ((status != NV_OK) || (pClassDescriptor->engDesc != ENG_SW)) { NvU32 engDesc; - NvU32 engineId = kchannelGetEngineType(pKernelChannel); + RM_ENGINE_TYPE rmEngineType = kchannelGetEngineType(pKernelChannel); // detect the GRCE case where we may be allocating a CE object on GR channel - if ((status == NV_OK) && IS_CE(pClassDescriptor->engDesc) && NV2080_ENGINE_TYPE_IS_GR(engineId)) + if ((status == NV_OK) && IS_CE(pClassDescriptor->engDesc) && RM_ENGINE_TYPE_IS_GR(rmEngineType)) { // // Get the partner CE of GR engine based on runqueue of this channel // Use this partner CE alongside externalClassId to fetch the correct class descriptor // NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS partnerParams = {0}; - partnerParams.engineType = engineId; + partnerParams.engineType = gpuGetNv2080EngineType(rmEngineType); partnerParams.runqueue = kchannelGetRunqueue(pKernelChannel); NV_ASSERT_OK_OR_RETURN(kfifoGetEnginePartnerList_HAL(pGpu, pKernelFifo, &partnerParams)); NV_ASSERT_OR_RETURN(partnerParams.numPartners == 1, NV_ERR_INVALID_STATE); - engineId = partnerParams.partnerList[0]; + rmEngineType = gpuGetRmEngineType(partnerParams.partnerList[0]); } // Get the engDesc from engineType NV_ASSERT_OK_OR_RETURN(kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, - ENGINE_INFO_TYPE_NV2080, - engineId, + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, + (NvU32)rmEngineType, ENGINE_INFO_TYPE_ENG_DESC, &engDesc)); diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_channel.c b/src/nvidia/src/kernel/gpu/fifo/kernel_channel.c index 7d70e096e..028f9bfd2 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_channel.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_channel.c @@ -82,15 +82,15 @@ static NV_STATUS _kchannelAllocHalData(OBJGPU *pGpu, KernelChannel *pKernelChann static void _kchannelFreeHalData(OBJGPU *pGpu, KernelChannel *pKernelChannel); static NV_STATUS _kchannelAllocOrDescribeInstMem( KernelChannel *pKernelChannel, - NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS *pChannelGpfifoParams); + NV_CHANNEL_ALLOC_PARAMS *pChannelGpfifoParams); static NV_STATUS _kchannelDescribeMemDescsFromParams( OBJGPU *pGpu, KernelChannel *pKernelChannel, - NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS *pChannelGpfifoParams); + NV_CHANNEL_ALLOC_PARAMS *pChannelGpfifoParams); static NV_STATUS _kchannelDescribeMemDescsHeavySriov(OBJGPU *pGpu, KernelChannel *pKernelChannel); static NV_STATUS _kchannelSendChannelAllocRpc( KernelChannel *pKernelChannel, - NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS *pChannelGpfifoParams, + NV_CHANNEL_ALLOC_PARAMS *pChannelGpfifoParams, KernelChannelGroup *pKernelChannelGroup, NvBool bFullSriov); @@ -138,7 +138,7 @@ kchannelConstruct_IMPL RM_API *pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL); NvHandle hClient = pRsClient->hClient; NvHandle hParent = pResourceRef->pParentRef->hResource; - NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS *pChannelGpfifoParams = pParams->pAllocParams; + NV_CHANNEL_ALLOC_PARAMS *pChannelGpfifoParams = pParams->pAllocParams; RsResourceRef *pChanGrpRef = NULL; KernelChannelGroupApi *pKernelChannelGroupApi = NULL; NvHandle hKernelCtxShare = pChannelGpfifoParams->hContextShare; @@ -149,7 +149,7 @@ kchannelConstruct_IMPL KernelChannelGroup *pKernelChannelGroup = NULL; NvU32 chID = ~0; NvU32 flags = pChannelGpfifoParams->flags; - NvU32 globalEngineType = NV2080_ENGINE_TYPE_NULL; + RM_ENGINE_TYPE globalRmEngineType = RM_ENGINE_TYPE_NULL; NvU32 verifFlags2 = 0; NvBool bChidAllocated = NV_FALSE; NvBool bLockAcquired = NV_FALSE; @@ -159,7 +159,6 @@ kchannelConstruct_IMPL NvBool bRpcAllocated = NV_FALSE; NvBool bFullSriov = IS_VIRTUAL_WITH_SRIOV(pGpu) && !gpuIsWarBug200577889SriovHeavyEnabled(pGpu); NvBool bAddedToGroup = NV_FALSE; - NvU64 errContextMemDescFlags = 0; NvU32 callingContextGfid; // We only support physical channels. @@ -169,13 +168,12 @@ kchannelConstruct_IMPL pKernelChannel->refCount = 1; pKernelChannel->bIsContextBound = NV_FALSE; pKernelChannel->nextObjectClassID = 0; - pKernelChannel->hVASpace = pChannelGpfifoParams->hVASpace; pKernelChannel->subctxId = 0; pKernelChannel->bSkipCtxBufferAlloc = FLD_TEST_DRF(OS04, _FLAGS, _SKIP_CTXBUFFER_ALLOC, _TRUE, flags); pKernelChannel->cid = portAtomicIncrementU32(&pSys->currentCid); pKernelChannel->runqueue = DRF_VAL(OS04, _FLAGS, _GROUP_CHANNEL_RUNQUEUE, flags); - pKernelChannel->engineType = NV2080_ENGINE_TYPE_NULL; + pKernelChannel->engineType = RM_ENGINE_TYPE_NULL; pChannelGpfifoParams->cid = pKernelChannel->cid; NV_ASSERT_OK_OR_GOTO(status, refFindAncestorOfType(pResourceRef, classId(Device), &pDeviceRef), cleanup); NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &callingContextGfid)); @@ -244,7 +242,7 @@ kchannelConstruct_IMPL } // Context share and vaspace handles can't be active at the same time. - if ((hKernelCtxShare != NV01_NULL_OBJECT) && (pKernelChannel->hVASpace != NV01_NULL_OBJECT)) + if ((hKernelCtxShare != NV01_NULL_OBJECT) && (pChannelGpfifoParams->hVASpace != NV01_NULL_OBJECT)) { NV_PRINTF(LEVEL_ERROR, "Both context share and vaspace handles can't be valid at the same time\n"); @@ -308,7 +306,7 @@ kchannelConstruct_IMPL goto cleanup; } - tsgParams.hVASpace = pKernelChannel->hVASpace; + tsgParams.hVASpace = pChannelGpfifoParams->hVASpace; tsgParams.engineType = pChannelGpfifoParams->engineType; // vGpu plugin context flag should only be set if context is plugin if (gpuIsSriovEnabled(pGpu)) @@ -360,7 +358,7 @@ kchannelConstruct_IMPL pKernelChannelGroup = pKernelChannelGroupApi->pKernelChannelGroup; // TSG channel should specify a context share object, rather than vaspace directly - if (pKernelChannel->hVASpace != NV01_NULL_OBJECT) + if (pChannelGpfifoParams->hVASpace != NV01_NULL_OBJECT) { NV_PRINTF(LEVEL_ERROR, "TSG channels can't use an explicit vaspace\n"); @@ -527,51 +525,7 @@ kchannelConstruct_IMPL pKernelChannel->eccErrorContextType, pChannelGpfifoParams->internalFlags); } - else if (RMCFG_FEATURE_PLATFORM_GSP) - { - pKernelChannel->errorContextType = DRF_VAL(_KERNELCHANNEL_ALLOC, - _INTERNALFLAGS, _ERROR_NOTIFIER_TYPE, - pChannelGpfifoParams->internalFlags); - pKernelChannel->eccErrorContextType = DRF_VAL(_KERNELCHANNEL_ALLOC, - _INTERNALFLAGS, _ECC_ERROR_NOTIFIER_TYPE, - pChannelGpfifoParams->internalFlags); - if (pKernelChannel->errorContextType != ERROR_NOTIFIER_TYPE_NONE) - { - NV_ASSERT_OK_OR_GOTO(status, - memdescCreate(&pKernelChannel->pErrContextMemDesc, - pGpu, - pChannelGpfifoParams->errorNotifierMem.size, - 1 /* Alignment */, - NV_TRUE /* PhysicallyContiguous */, - ADDR_UNKNOWN, - NV_MEMORY_UNCACHED, - errContextMemDescFlags), - cleanup); - memdescDescribe(pKernelChannel->pErrContextMemDesc, - pChannelGpfifoParams->errorNotifierMem.addressSpace, - pChannelGpfifoParams->errorNotifierMem.base, - pChannelGpfifoParams->errorNotifierMem.size); - } - - if (pKernelChannel->eccErrorContextType != ERROR_NOTIFIER_TYPE_NONE) - { - NV_ASSERT_OK_OR_GOTO(status, - memdescCreate(&pKernelChannel->pEccErrContextMemDesc, - pGpu, - pChannelGpfifoParams->eccErrorNotifierMem.size, - 1 /* Alignment */, - NV_TRUE /* PhysicallyContiguous */, - ADDR_UNKNOWN, - NV_MEMORY_UNCACHED, - errContextMemDescFlags), - cleanup); - memdescDescribe(pKernelChannel->pEccErrContextMemDesc, - pChannelGpfifoParams->eccErrorNotifierMem.addressSpace, - pChannelGpfifoParams->eccErrorNotifierMem.base, - pChannelGpfifoParams->eccErrorNotifierMem.size); - } - } // // The error context types should be set on all RM configurations // (GSP/baremetal/CPU-GSP client) @@ -580,34 +534,59 @@ kchannelConstruct_IMPL NV_ASSERT(pKernelChannel->eccErrorContextType != ERROR_NOTIFIER_TYPE_UNKNOWN); - // Get KernelCtxShare (supplied or legacy) - if (hKernelCtxShare) + + if ((pKernelChannelGroup->chanCount != 0) && + (( pKernelChannelGroup->bLegacyMode && (hKernelCtxShare != NV01_NULL_OBJECT)) || + (!pKernelChannelGroup->bLegacyMode && (hKernelCtxShare == NV01_NULL_OBJECT)))) { // - // Get object pointers from supplied hKernelCtxShare. - // If hKernelCtxShare is nonzero, the ChannelGroup is not internal either, - // so it should have the same parent as hParent. + // Check if this channnel allocation specifying (or not) a user + // allocated context share matches with previous channel allocations (if + // any) in this group specifiying (or not) a user allocated context + // share. // - NV_ASSERT_OR_ELSE(!pKernelChannelGroup->bLegacyMode, - status = NV_ERR_INVALID_STATE; - goto cleanup); + // A channel group cannot have a mix of channels with some of them + // specifying a user allocated context share and some having RM + // allocated context share. + // + NV_PRINTF(LEVEL_NOTICE, + "All channels in a channel group must specify a CONTEXT_SHARE if any one of them specifies it\n"); + status = NV_ERR_INVALID_ARGUMENT; + goto cleanup; + } + // Get KernelCtxShare (supplied or legacy) + if (hKernelCtxShare != NV01_NULL_OBJECT) + { + // Get object pointers from supplied hKernelCtxShare. NV_ASSERT_OK_OR_GOTO(status, - clientGetResourceRefByType(pRsClient, hKernelCtxShare, classId(KernelCtxShareApi), &pKernelCtxShareRef), - cleanup); + clientGetResourceRefByType(pRsClient, + hKernelCtxShare, + classId(KernelCtxShareApi), + &pKernelCtxShareRef), + cleanup); - // Check that the parent matches - NV_ASSERT_OR_ELSE((pKernelCtxShareRef->pParentRef) && (pKernelCtxShareRef->pParentRef->hResource == hParent), - status = NV_ERR_INVALID_OBJECT_PARENT; goto cleanup); + // + // If hKernelCtxShare is nonzero, the ChannelGroup is not internal + // either, so it should have the same parent as hParent. + // + NV_ASSERT_OR_ELSE( + pKernelCtxShareRef->pParentRef != NULL && + pKernelCtxShareRef->pParentRef->hResource == hParent, + status = NV_ERR_INVALID_OBJECT_PARENT; + goto cleanup); } else { NvU32 subctxFlag; NvHandle hLegacyKernelCtxShare; - // Set this ChannelGroup to legacy mode and get the KernelCtxShare from it. if (!pKernelChannelGroup->bLegacyMode) { + // + // Set this ChannelGroup to legacy mode and get the KernelCtxShare + // from it. + // NV_ASSERT_OK_OR_GOTO(status, kchangrpapiSetLegacyMode(pKernelChannelGroupApi, pGpu, pKernelFifo, hClient), @@ -619,12 +598,13 @@ kchannelConstruct_IMPL NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_SYNC) ? pKernelChannelGroupApi->hLegacykCtxShareSync : pKernelChannelGroupApi->hLegacykCtxShareAsync; + NV_ASSERT_OK_OR_GOTO(status, - clientGetResourceRefByType(pRsClient, - hLegacyKernelCtxShare, - classId(KernelCtxShareApi), - &pKernelCtxShareRef), - cleanup); + clientGetResourceRefByType(pRsClient, + hLegacyKernelCtxShare, + classId(KernelCtxShareApi), + &pKernelCtxShareRef), + cleanup); } pKernelChannel->pKernelCtxShareApi = dynamicCast(pKernelCtxShareRef->pResource, KernelCtxShareApi); @@ -636,17 +616,17 @@ kchannelConstruct_IMPL if (kfifoIsPerRunlistChramSupportedInHw(pKernelFifo)) { // TSG should always have a valid engine Id. - if (!NV2080_ENGINE_TYPE_IS_VALID(pKernelChannelGroup->engineType)) + if (!RM_ENGINE_TYPE_IS_VALID(pKernelChannelGroup->engineType)) { NV_ASSERT( - NV2080_ENGINE_TYPE_IS_VALID(pKernelChannelGroup->engineType)); + RM_ENGINE_TYPE_IS_VALID(pKernelChannelGroup->engineType)); status = NV_ERR_INVALID_STATE; goto cleanup; } if (NV2080_ENGINE_TYPE_IS_VALID(pChannelGpfifoParams->engineType)) { - globalEngineType = pChannelGpfifoParams->engineType; + globalRmEngineType = gpuGetRmEngineType(pChannelGpfifoParams->engineType); // Convert it to global engine id if MIG is enabled if (bMIGInUse) { @@ -662,17 +642,19 @@ kchannelConstruct_IMPL status, LEVEL_ERROR, kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, - pChannelGpfifoParams->engineType, - &globalEngineType), + globalRmEngineType, + &globalRmEngineType), cleanup); } // Throw an error if TSG engine Id does NOT match with channel engine Id - if (globalEngineType != pKernelChannelGroup->engineType) + if (globalRmEngineType != pKernelChannelGroup->engineType) { NV_PRINTF(LEVEL_ERROR, - "Engine type of channel = 0x%x not compatible with engine type of TSG = 0x%x\n", + "Engine type of channel = 0x%x (0x%x) not compatible with engine type of TSG = 0x%x (0x%x)\n", + gpuGetNv2080EngineType(pChannelGpfifoParams->engineType), pChannelGpfifoParams->engineType, + gpuGetNv2080EngineType(pKernelChannelGroup->engineType), pKernelChannelGroup->engineType); status = NV_ERR_INVALID_ARGUMENT; @@ -688,7 +670,7 @@ kchannelConstruct_IMPL pKernelChannel->runlistId = kfifoGetDefaultRunlist_HAL(pGpu, pKernelFifo, pKernelChannel->engineType); // Set TLS state and BAR0 window if we are working with Gr - if (bMIGInUse && NV2080_ENGINE_TYPE_IS_GR(pKernelChannel->engineType)) + if (bMIGInUse && RM_ENGINE_TYPE_IS_GR(pKernelChannel->engineType)) { NV_ASSERT_OK(kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, pRsClient->hClient, &pKernelChannel->partitionRef)); @@ -858,11 +840,11 @@ kchannelConstruct_IMPL } // We depend on VASpace if it was provided - if (pKernelChannel->hVASpace != NV01_NULL_OBJECT) + if (pChannelGpfifoParams->hVASpace != NV01_NULL_OBJECT) { RsResourceRef *pVASpaceRef = NULL; - NV_ASSERT_OK_OR_GOTO(status, clientGetResourceRef(pRsClient, pKernelChannel->hVASpace, &pVASpaceRef), cleanup); + NV_ASSERT_OK_OR_GOTO(status, clientGetResourceRef(pRsClient, pChannelGpfifoParams->hVASpace, &pVASpaceRef), cleanup); NV_ASSERT_OR_ELSE(pVASpaceRef != NULL, status = NV_ERR_INVALID_OBJECT; goto cleanup); NV_ASSERT_OK_OR_GOTO(status, refAddDependant(pVASpaceRef, pResourceRef), cleanup); @@ -902,6 +884,9 @@ kchannelConstruct_IMPL cleanup); } + // Cache the hVASpace for this channel in the KernelChannel object + pKernelChannel->hVASpace = pKernelChannel->pKernelCtxShareApi->hVASpace; + cleanup: if (bLockAcquired) rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); @@ -1555,7 +1540,7 @@ kchannelNotifyRc_IMPL ) { OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelChannel); - NvU32 engineID = NV2080_ENGINE_TYPE_NULL; + RM_ENGINE_TYPE rmEngineType = RM_ENGINE_TYPE_NULL; NV_STATUS rmStatus = NV_OK; if (IS_GFID_VF(kchannelGetGfid(pKernelChannel))) @@ -1573,14 +1558,14 @@ kchannelNotifyRc_IMPL return NV_OK; } - if (NV2080_ENGINE_TYPE_IS_VALID(kchannelGetEngineType(pKernelChannel))) + if (RM_ENGINE_TYPE_IS_VALID(kchannelGetEngineType(pKernelChannel))) { - engineID = kchannelGetEngineType(pKernelChannel); + rmEngineType = kchannelGetEngineType(pKernelChannel); } rmStatus = krcErrorSetNotifier(pGpu, GPU_GET_KERNEL_RC(pGpu), pKernelChannel, ROBUST_CHANNEL_PREEMPTIVE_REMOVAL, - engineID, + rmEngineType, RC_NOTIFIER_SCOPE_CHANNEL); if (rmStatus != NV_OK) { @@ -1874,7 +1859,7 @@ kchannelIsSchedulable_IMPL ) { OBJGVASPACE *pGVAS = NULL; - NvU32 engineId = 0; + NvU32 engineDesc = 0; NvU32 gfId; gfId = kchannelGetGfid(pKernelChannel); @@ -1894,9 +1879,9 @@ kchannelIsSchedulable_IMPL // NV_ASSERT_OR_RETURN(pGVAS != NULL || IS_MODS_AMODEL(pGpu), NV_FALSE); - NV_ASSERT_OR_RETURN(kchannelGetEngine_HAL(pGpu, pKernelChannel, &engineId) == NV_OK, NV_FALSE); + NV_ASSERT_OR_RETURN(kchannelGetEngine_HAL(pGpu, pKernelChannel, &engineDesc) == NV_OK, NV_FALSE); - if (pGVAS != NULL && gvaspaceIsExternallyOwned(pGVAS) && IS_GR(engineId) && !pKernelChannel->bIsContextBound) + if (pGVAS != NULL && gvaspaceIsExternallyOwned(pGVAS) && IS_GR(engineDesc) && !pKernelChannel->bIsContextBound) { NV_PRINTF(LEVEL_ERROR, "Cannot schedule externally-owned channel with unbound allocations :0x%x!\n", @@ -1961,7 +1946,7 @@ static NvU32 _kchannelgetVerifFlags ( OBJGPU *pGpu, - NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS *pChannelGpfifoParams + NV_CHANNEL_ALLOC_PARAMS *pChannelGpfifoParams ) { NvU32 verifFlags = 0; @@ -1974,7 +1959,7 @@ static NV_STATUS _kchannelAllocOrDescribeInstMem ( KernelChannel *pKernelChannel, - NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS *pChannelGpfifoParams + NV_CHANNEL_ALLOC_PARAMS *pChannelGpfifoParams ) { OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelChannel); @@ -2102,7 +2087,7 @@ _kchannelDescribeMemDescsFromParams ( OBJGPU *pGpu, KernelChannel *pKernelChannel, - NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS *pChannelGpfifoParams + NV_CHANNEL_ALLOC_PARAMS *pChannelGpfifoParams ) { NV_STATUS status = NV_OK; @@ -2131,7 +2116,8 @@ _kchannelDescribeMemDescsFromParams // Create memory descriptor for the instance memory status = memdescCreate(&pInstanceBlock->pInstanceBlockDesc, pGpu, pChannelGpfifoParams->instanceMem.size, 1 , NV_TRUE, - ADDR_UNKNOWN, pChannelGpfifoParams->instanceMem.cacheAttrib, + pChannelGpfifoParams->instanceMem.addressSpace, + pChannelGpfifoParams->instanceMem.cacheAttrib, MEMDESC_FLAGS_OWNED_BY_CURRENT_DEVICE); if (status != NV_OK) @@ -2148,7 +2134,8 @@ _kchannelDescribeMemDescsFromParams // Create memory descriptor for the ramfc status = memdescCreate(&pInstanceBlock->pRamfcDesc, pGpu, pChannelGpfifoParams->ramfcMem.size, 1 , NV_TRUE, - ADDR_UNKNOWN, pChannelGpfifoParams->ramfcMem.cacheAttrib, + pChannelGpfifoParams->ramfcMem.addressSpace, + pChannelGpfifoParams->ramfcMem.cacheAttrib, MEMDESC_FLAGS_OWNED_BY_CURRENT_DEVICE); if (status != NV_OK) @@ -2164,7 +2151,8 @@ _kchannelDescribeMemDescsFromParams // Create userd memory descriptor status = memdescCreate(&pKernelChannel->pUserdSubDeviceMemDesc[subDevInst], pGpu, pChannelGpfifoParams->userdMem.size, 1 , NV_TRUE, - ADDR_UNKNOWN, pChannelGpfifoParams->userdMem.cacheAttrib, + pChannelGpfifoParams->userdMem.addressSpace, + pChannelGpfifoParams->userdMem.cacheAttrib, MEMDESC_FLAGS_OWNED_BY_CURRENT_DEVICE); if (status != NV_OK) @@ -2207,7 +2195,7 @@ _kchannelDescribeMemDescsFromParams pChannelGpfifoParams->mthdbufMem.size, 1, NV_TRUE, - ADDR_UNKNOWN, + pChannelGpfifoParams->mthdbufMem.addressSpace, pChannelGpfifoParams->mthdbufMem.cacheAttrib, MEMDESC_FLAGS_OWNED_BY_CURRENT_DEVICE); @@ -2330,7 +2318,7 @@ _kchannelDescribeMemDescsHeavySriov status = memdescCreate(&pInstanceBlock->pInstanceBlockDesc, pGpu, memInfoParams.chMemInfo.inst.size, 1 , NV_TRUE, - ADDR_UNKNOWN, NV_MEMORY_UNCACHED, MEMDESC_FLAGS_OWNED_BY_CURRENT_DEVICE); + apert, NV_MEMORY_UNCACHED, MEMDESC_FLAGS_OWNED_BY_CURRENT_DEVICE); if (status != NV_OK) { @@ -2362,13 +2350,13 @@ static NV_STATUS _kchannelSendChannelAllocRpc ( KernelChannel *pKernelChannel, - NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS *pChannelGpfifoParams, + NV_CHANNEL_ALLOC_PARAMS *pChannelGpfifoParams, KernelChannelGroup *pKernelChannelGroup, NvBool bFullSriov ) { OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelChannel); - NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS *pRpcParams; + NV_CHANNEL_ALLOC_PARAMS *pRpcParams; NV_STATUS status = NV_OK; pRpcParams = portMemAllocNonPaged(sizeof(*pRpcParams)); @@ -2530,7 +2518,7 @@ cleanup: NV_STATUS kchannelBindToRunlist_IMPL ( KernelChannel *pKernelChannel, - NvU32 localEngineType, + RM_ENGINE_TYPE localRmEngineType, ENGDESCRIPTOR engineDesc ) { @@ -2557,7 +2545,7 @@ NV_STATUS kchannelBindToRunlist_IMPL { NVA06F_CTRL_BIND_PARAMS params; - params.engineType = localEngineType; + params.engineType = gpuGetNv2080EngineType(localRmEngineType); NV_RM_RPC_CONTROL(pGpu, RES_GET_CLIENT_HANDLE(pKernelChannel), @@ -2663,6 +2651,7 @@ kchannelCtrlCmdGetClassEngineid_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelChannel); KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); NV_STATUS status = NV_OK; + RM_ENGINE_TYPE rmEngineType; // // MODS uses hObject 0 to figure out if this call is supported or not. @@ -2695,13 +2684,15 @@ kchannelCtrlCmdGetClassEngineid_IMPL kchannelGetClassEngineID_HAL(pGpu, pKernelChannel, pParams->hObject, &pParams->classEngineID, &pParams->classID, - &pParams->engineID)); + &rmEngineType)); + + pParams->engineID = gpuGetNv2080EngineType(rmEngineType); if (IS_MIG_IN_USE(pGpu) && - kmigmgrIsEnginePartitionable(pGpu, pKernelMIGManager, pParams->engineID)) + kmigmgrIsEnginePartitionable(pGpu, pKernelMIGManager, rmEngineType)) { MIG_INSTANCE_REF ref; - NvU32 localEngineType; + RM_ENGINE_TYPE localRmEngineType; NV_ASSERT_OK_OR_RETURN( kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, @@ -2710,12 +2701,13 @@ kchannelCtrlCmdGetClassEngineid_IMPL NV_ASSERT_OK_OR_RETURN( kmigmgrGetGlobalToLocalEngineType(pGpu, pKernelMIGManager, ref, - pParams->engineID, - &localEngineType)); + rmEngineType, + &localRmEngineType)); - NV_PRINTF(LEVEL_INFO, "Overriding global engine type 0x%x to local engine type 0x%x due to MIG\n", - pParams->engineID, localEngineType); - pParams->engineID = localEngineType; + NV_PRINTF(LEVEL_INFO, "Overriding global engine type 0x%x to local engine type 0x%x (0x%x) due to MIG\n", + pParams->engineID, gpuGetNv2080EngineType(localRmEngineType), localRmEngineType); + + pParams->engineID = gpuGetNv2080EngineType(localRmEngineType); } return status; @@ -2903,8 +2895,8 @@ kchannelCtrlCmdBind_IMPL NVA06F_CTRL_BIND_PARAMS *pParams ) { - NvU32 globalEngineType; - NvU32 localEngineType; + RM_ENGINE_TYPE globalRmEngineType; + RM_ENGINE_TYPE localRmEngineType; OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelChannel); NvHandle hClient = RES_GET_CLIENT_HANDLE(pKernelChannel); NvBool bMIGInUse = IS_MIG_IN_USE(pGpu); @@ -2927,7 +2919,7 @@ kchannelCtrlCmdBind_IMPL pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup->grpID); } - localEngineType = globalEngineType = pParams->engineType; + localRmEngineType = globalRmEngineType = gpuGetRmEngineType(pParams->engineType); if (bMIGInUse) { @@ -2938,22 +2930,22 @@ kchannelCtrlCmdBind_IMPL kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, localEngineType, - &globalEngineType)); + kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, localRmEngineType, + &globalRmEngineType)); } NV_PRINTF(LEVEL_INFO, "Binding Channel %d to Engine %d\n", - kchannelGetDebugTag(pKernelChannel), globalEngineType); + kchannelGetDebugTag(pKernelChannel), globalRmEngineType); - // Translate globalEnginetype -> enginedesc + // Translate globalRmEngineType -> enginedesc NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(rmStatus, - gpuXlateClientEngineIdToEngDesc(pGpu, globalEngineType, &engineDesc)); + gpuXlateClientEngineIdToEngDesc(pGpu, globalRmEngineType, &engineDesc)); if (rmStatus == NV_OK) { NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(rmStatus, - kchannelBindToRunlist(pKernelChannel, localEngineType, engineDesc)); + kchannelBindToRunlist(pKernelChannel, localRmEngineType, engineDesc)); } return rmStatus; @@ -3017,7 +3009,9 @@ kchannelCtrlCmdGpfifoGetWorkSubmitToken_IMPL CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; NvBool bIsMIGEnabled = IS_MIG_ENABLED(pGpu); - NvBool bIsModsVgpu = IS_VIRTUAL(pGpu) && NV_IS_MODS; + + NvBool bIsModsVgpu = NV_FALSE; + NvBool bIsVgpuRpcNeeded = bIsModsVgpu || (IS_VIRTUAL(pGpu) && !(IS_VIRTUAL_WITH_SRIOV(pGpu) && !bIsMIGEnabled && kfifoIsPerRunlistChramEnabled(pKernelFifo))); @@ -3044,8 +3038,12 @@ kchannelCtrlCmdGpfifoGetWorkSubmitToken_IMPL // GSP FW is not able to perform the notification, nor is MODS vGPU host, // so it still needs to be handled by the client/guest outside the RPC. // - if (rmStatus != NV_OK || - (IS_VIRTUAL(pGpu) && !NV_IS_MODS)) + if (rmStatus != NV_OK) + { + return rmStatus; + } + + if (IS_VIRTUAL(pGpu)) { return rmStatus; } @@ -3078,11 +3076,6 @@ kchannelCtrlCmdGpfifoSetWorkSubmitTokenNotifIndex_IMPL { NV_STATUS rmStatus = NV_OK; OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelChannel); - KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); - NvBool bIsMIGEnabled = IS_MIG_ENABLED(pGpu); - NvBool bIsVgpuRpcNeeded = IS_VIRTUAL(pGpu) && - !(IS_VIRTUAL_WITH_SRIOV(pGpu) && !bIsMIGEnabled && - kfifoIsPerRunlistChramEnabled(pKernelFifo)); // // vGPU: @@ -3095,7 +3088,12 @@ kchannelCtrlCmdGpfifoSetWorkSubmitTokenNotifIndex_IMPL // // Notification is done in CPU-RM, so RPC is not made to FW-RM. // - if (!NV_IS_MODS && bIsVgpuRpcNeeded) + KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + NvBool bIsMIGEnabled = IS_MIG_ENABLED(pGpu); + NvBool bIsVgpuRpcNeeded = IS_VIRTUAL(pGpu) && + !(IS_VIRTUAL_WITH_SRIOV(pGpu) && !bIsMIGEnabled && + kfifoIsPerRunlistChramEnabled(pKernelFifo)); + if (bIsVgpuRpcNeeded) { CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; @@ -3376,53 +3374,24 @@ _kchannelClearVAList NvBool bUnmap ) { - VA_LISTIter it; - NV_STATUS status; - // // Subcontext handling // We need to unmap the mappings on all the subcontext, since the this call will be made only on one of the TSG channels. // - it = mapIterAll(pVaList); - while (mapIterNext(&it)) + if (bUnmap) { - OBJVASPACE *pVAS = (OBJVASPACE *) NvP64_VALUE(mapKey(pVaList, it.pValue)); - VA_INFO *pVaInfo; - NvU64 vaddr = 0, vaddrCached = 0; + OBJVASPACE *pVas; + NvU64 vAddr; - if (pVAS == NULL) + FOR_EACH_IN_VADDR_LIST(pVaList, pVas, vAddr) { - // Ignore the special node - continue; - } - - pVaInfo = (VA_INFO *)it.pValue; - vaddrCached = pVaInfo->vAddr; - - pVaInfo->refCnt = 1; - - status = vaListRemoveVa(pVaList, pVAS); - NV_ASSERT(status == NV_OK); - - status = vaListFindVa(pVaList, pVAS, &vaddr); - if (status != NV_OK) - { - if (status == NV_ERR_OBJECT_NOT_FOUND) - status = NV_OK; - else - { - NV_PRINTF(LEVEL_ERROR, "vaListFindVa failed with unexpected status = 0x%x\n", status); - NV_ASSERT(0); - } - it = mapIterAll(pVaList); - - if (bUnmap) - { - dmaUnmapBuffer_HAL(pGpu, GPU_GET_DMA(pGpu), pVAS, vaddrCached); - } + dmaUnmapBuffer_HAL(pGpu, GPU_GET_DMA(pGpu), pVas, vAddr); } + FOR_EACH_IN_VADDR_LIST_END(pVaList, pVas, vAddr); } + vaListClear(pVaList); + return NV_OK; } @@ -3434,7 +3403,7 @@ _kchannelClearVAList * * @param[in] pGpu * @param[in] pKernelChannel - * @param[in] engine + * @param[in] engDesc * @param[in] pMemDesc the new memdesc to assign, or NULL to clear * * Returns: status @@ -3444,7 +3413,7 @@ kchannelSetEngineContextMemDesc_IMPL ( OBJGPU *pGpu, KernelChannel *pKernelChannel, - NvU32 engine, + NvU32 engDesc, MEMORY_DESCRIPTOR *pMemDesc ) { @@ -3453,12 +3422,12 @@ kchannelSetEngineContextMemDesc_IMPL KernelChannelGroup *pKernelChannelGroup = pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup; NV_PRINTF(LEVEL_INFO, - "ChID %x engine 0x%x pMemDesc %p\n", - kchannelGetDebugTag(pKernelChannel), engine, pMemDesc); + "ChID %x engDesc 0x%x pMemDesc %p\n", + kchannelGetDebugTag(pKernelChannel), engDesc, pMemDesc); - NV_ASSERT_OR_RETURN(engine != ENG_FIFO, NV_ERR_INVALID_PARAMETER); + NV_ASSERT_OR_RETURN(engDesc != ENG_FIFO, NV_ERR_INVALID_PARAMETER); - if (IS_GR(engine)) + if (IS_GR(engDesc)) { NV_ASSERT_OK_OR_RETURN(kchannelCheckBcStateCurrent(pGpu, pKernelChannel)); } @@ -3476,7 +3445,7 @@ kchannelSetEngineContextMemDesc_IMPL if (pEngCtxDesc != NULL) { - // Cleanup for the engine context that existed before + // Cleanup for the engDesc context that existed before if (pEngCtxDesc->pMemDesc != NULL) { memdescFree(pEngCtxDesc->pMemDesc); @@ -3499,7 +3468,7 @@ kchannelSetEngineContextMemDesc_IMPL // Other cases where this is exercised are special cases like golden image init where ctx buffers are swapped, // control calls which force ctx buffer unmap, re-initializing of virtual ctxs, evicting a ctx, fifoStateDestroy etc. // - if(IS_GR(engine)) + if(IS_GR(engDesc)) { status = kchangrpFreeGrSubcontextHdrs_HAL(pGpu, pKernelChannelGroup); } @@ -3537,7 +3506,7 @@ kchannelSetEngineContextMemDesc_IMPL // Assign the memdesc (or NULL) pEngCtxDesc->pMemDesc = pMemDesc; - pEngCtxDesc->engDesc = engine; + pEngCtxDesc->engDesc = engDesc; SLI_LOOP_END @@ -3550,7 +3519,7 @@ fail: * * @param[in] pGpu * @param[in] pKernelChannel - * @param[in] engine + * @param[in] engDesc * * Returns: status */ @@ -3559,19 +3528,19 @@ kchannelUnmapEngineCtxBuf_IMPL ( OBJGPU *pGpu, KernelChannel *pKernelChannel, - NvU32 engine + NvU32 engDesc ) { NV_STATUS status = NV_OK; ENGINE_CTX_DESCRIPTOR *pEngCtxDesc; NV_PRINTF(LEVEL_INFO, - "ChID %x engine 0x%x\n", - kchannelGetDebugTag(pKernelChannel), engine); + "ChID %x engDesc 0x%x\n", + kchannelGetDebugTag(pKernelChannel), engDesc); - NV_ASSERT_OR_RETURN(engine != ENG_FIFO, NV_ERR_INVALID_PARAMETER); + NV_ASSERT_OR_RETURN(engDesc != ENG_FIFO, NV_ERR_INVALID_PARAMETER); - if (IS_GR(engine)) + if (IS_GR(engDesc)) { NV_ASSERT_OK_OR_RETURN(kchannelCheckBcStateCurrent(pGpu, pKernelChannel)); } @@ -3641,7 +3610,7 @@ kchannelMapEngineCtxBuf_IMPL ( OBJGPU *pGpu, KernelChannel *pKernelChannel, - NvU32 engine + NvU32 engDesc ) { OBJVASPACE *pVAS = NULL; @@ -3652,17 +3621,17 @@ kchannelMapEngineCtxBuf_IMPL OBJGVASPACE *pGVAS; KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); - NV_ASSERT_OR_RETURN(engine != ENG_FIFO, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(engDesc != ENG_FIFO, NV_ERR_INVALID_ARGUMENT); - if (IS_GR(engine)) + if (IS_GR(engDesc)) { NV_ASSERT_OK_OR_RETURN(kchannelCheckBcStateCurrent(pGpu, pKernelChannel)); } - NV_PRINTF(LEVEL_INFO, "ChID %d engine %s (0x%x) \n", + NV_PRINTF(LEVEL_INFO, "ChID %d engDesc %s (0x%x) \n", kchannelGetDebugTag(pKernelChannel), - kfifoGetEngineName_HAL(GPU_GET_KERNEL_FIFO(pGpu), ENGINE_INFO_TYPE_ENG_DESC, engine), - engine); + kfifoGetEngineName_HAL(GPU_GET_KERNEL_FIFO(pGpu), ENGINE_INFO_TYPE_ENG_DESC, engDesc), + engDesc); pVAS = pKernelChannel->pVAS; pGVAS = dynamicCast(pVAS, OBJGVASPACE); @@ -3698,15 +3667,15 @@ kchannelMapEngineCtxBuf_IMPL goto fail; } - kfifoGetCtxBufferMapFlags_HAL(pGpu, pKernelFifo, engine, &flags); + kfifoGetCtxBufferMapFlags_HAL(pGpu, pKernelFifo, engDesc, &flags); status = dmaMapBuffer_HAL(pGpu, GPU_GET_DMA(pGpu), pVAS, pTempMemDesc, &addr, flags, DMA_UPDATE_VASPACE_FLAGS_NONE); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, - "Could not map context buffer for engine 0x%x\n", - engine); + "Could not map context buffer for engDesc 0x%x\n", + engDesc); goto fail; } else @@ -3756,6 +3725,7 @@ kchannelUpdateWorkSubmitTokenNotifIndex_IMPL Memory *pMemory; ContextDma *pContextDma; NvU32 addressSpace; + NvU64 notificationBufferSize; NV_STATUS status; hNotifier = pKernelChannel->hErrorContext; @@ -3764,6 +3734,8 @@ kchannelUpdateWorkSubmitTokenNotifIndex_IMPL NV_CHECK_OR_RETURN(LEVEL_INFO, index != NV_CHANNELGPFIFO_NOTIFICATION_TYPE_ERROR, NV_ERR_INVALID_ARGUMENT); + notificationBufferSize = (index + 1) * sizeof(NvNotification); + status = deviceGetByInstance(pClient, gpuGetDeviceInstance(pGpu), &pDevice); if (status != NV_OK) return NV_ERR_INVALID_DEVICE; @@ -3772,7 +3744,7 @@ kchannelUpdateWorkSubmitTokenNotifIndex_IMPL { addressSpace = memdescGetAddressSpace(pMemory->pMemDesc); - NV_CHECK_OR_RETURN(LEVEL_INFO, pMemory->Length >= ((index + 1) * sizeof(NvNotification)), + NV_CHECK_OR_RETURN(LEVEL_INFO, pMemory->Length >= notificationBufferSize, NV_ERR_OUT_OF_RANGE); switch (addressSpace) { @@ -3790,7 +3762,7 @@ kchannelUpdateWorkSubmitTokenNotifIndex_IMPL &pDmaMappingInfo), NV_ERR_GENERIC); - NV_CHECK_OR_RETURN(LEVEL_INFO, pDmaMappingInfo->pMemDesc->Size >= ((index + 1) * sizeof(NvNotification)), + NV_CHECK_OR_RETURN(LEVEL_INFO, pDmaMappingInfo->pMemDesc->Size >= notificationBufferSize, NV_ERR_OUT_OF_RANGE); break; } @@ -3805,7 +3777,7 @@ kchannelUpdateWorkSubmitTokenNotifIndex_IMPL } else if (NV_OK == ctxdmaGetByHandle(pClient, hNotifier, &pContextDma)) { - NV_CHECK_OR_RETURN(LEVEL_INFO, pContextDma->Limit >= (((index + 1) * sizeof(NvNotification)) - 1), + NV_CHECK_OR_RETURN(LEVEL_INFO, pContextDma->Limit >= (notificationBufferSize - 1), NV_ERR_OUT_OF_RANGE); } else diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group.c b/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group.c index 09eb708f3..d01c66245 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group.c @@ -158,7 +158,7 @@ kchangrpInit_IMPL // NV_ASSERT_OK_OR_RETURN( kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, - ENGINE_INFO_TYPE_NV2080, + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, pKernelChannelGroup->engineType, ENGINE_INFO_TYPE_RUNLIST, &runlistId)); @@ -371,7 +371,7 @@ kchangrpDestroy_IMPL // NV_ASSERT_OK_OR_RETURN( kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, - ENGINE_INFO_TYPE_NV2080, + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, pKernelChannelGroup->engineType, ENGINE_INFO_TYPE_RUNLIST, &runlistId)); diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group_api.c b/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group_api.c index c1f81836a..b0e36d038 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group_api.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group_api.c @@ -69,6 +69,7 @@ kchangrpapiConstruct_IMPL RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); KernelChannelGroup *pKernelChannelGroup = NULL; NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS *pAllocParams = NULL; + RM_ENGINE_TYPE rmEngineType; NV_PRINTF(LEVEL_INFO, "hClient: 0x%x, hParent: 0x%x, hObject:0x%x, hClass: 0x%x\n", @@ -129,6 +130,7 @@ kchangrpapiConstruct_IMPL goto failed; } + pKernelChannelGroupApi->hVASpace = hVASpace; rmStatus = serverGetClientUnderLock(&g_resServ, pParams->hClient, &pClient); if (rmStatus != NV_OK) @@ -149,9 +151,11 @@ kchangrpapiConstruct_IMPL pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); bMIGInUse = IS_MIG_IN_USE(pGpu); + rmEngineType = gpuGetRmEngineType(pAllocParams->engineType); + if (kfifoIsPerRunlistChramSupportedInHw(pKernelFifo)) { - if (!NV2080_ENGINE_TYPE_IS_VALID(pAllocParams->engineType)) + if (!RM_ENGINE_TYPE_IS_VALID(rmEngineType)) { NV_PRINTF(LEVEL_NOTICE, "Valid engine Id must be specified while allocating TSGs or bare channels!\n"); rmStatus = NV_ERR_INVALID_ARGUMENT; @@ -166,7 +170,7 @@ kchangrpapiConstruct_IMPL // corresponding to that engine to be chosen in // kchangrpGetDefaultRunlist_HAL. // - pKernelChannelGroup->engineType = pAllocParams->engineType; + pKernelChannelGroup->engineType = rmEngineType; } // @@ -176,10 +180,8 @@ kchangrpapiConstruct_IMPL // if (bMIGInUse) { - NvU32 engineId; - // Engine type must be valid for MIG - NV_CHECK_OR_ELSE(LEVEL_NOTICE, NV2080_ENGINE_TYPE_IS_VALID(pKernelChannelGroup->engineType), + NV_CHECK_OR_ELSE(LEVEL_NOTICE, RM_ENGINE_TYPE_IS_VALID(pKernelChannelGroup->engineType), rmStatus = NV_ERR_INVALID_STATE; goto failed); NV_CHECK_OK_OR_GOTO( @@ -192,12 +194,12 @@ kchangrpapiConstruct_IMPL rmStatus, LEVEL_ERROR, kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, - pAllocParams->engineType, - &engineId), + rmEngineType, + &rmEngineType), failed); // Rewrite the engineType with the global engine type - pKernelChannelGroup->engineType = engineId; + pKernelChannelGroup->engineType = rmEngineType; pHeap = ref.pKernelMIGGpuInstance->pMemoryPartitionHeap; } @@ -275,9 +277,9 @@ kchangrpapiConstruct_IMPL kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, pKernelChannelGroup->engineType, ref)) { // GR Buffers - if (NV2080_ENGINE_TYPE_IS_GR(pKernelChannelGroup->engineType)) + if (RM_ENGINE_TYPE_IS_GR(pKernelChannelGroup->engineType)) { - KernelGraphics *pKernelGraphics = GPU_GET_KERNEL_GRAPHICS(pGpu, NV2080_ENGINE_TYPE_GR_IDX(pKernelChannelGroup->engineType)); + KernelGraphics *pKernelGraphics = GPU_GET_KERNEL_GRAPHICS(pGpu, RM_ENGINE_TYPE_GR_IDX(pKernelChannelGroup->engineType)); NvU32 bufId; portMemSet(&bufInfoList[0], 0, sizeof(CTX_BUF_INFO) * NV_ENUM_SIZE(GR_CTX_BUFFER)); bufCount = 0; @@ -325,19 +327,21 @@ kchangrpapiConstruct_IMPL bufInfoList[0].align = RM_PAGE_SIZE; bufInfoList[0].attr = RM_ATTR_PAGE_SIZE_4KB; bufInfoList[0].bContig = NV_TRUE; - NV_PRINTF(LEVEL_INFO, "Reserving 0x%llx bytes for engineType %u flcn ctx buffer\n", - bufInfoList[0].size, pKernelChannelGroup->engineType); + NV_PRINTF(LEVEL_INFO, "Reserving 0x%llx bytes for engineType %d (%d) flcn ctx buffer\n", + bufInfoList[0].size, gpuGetNv2080EngineType(pKernelChannelGroup->engineType), + pKernelChannelGroup->engineType); bufCount++; } else { - NV_PRINTF(LEVEL_INFO, "No buffer reserved for engineType %u in ctx_buf_pool\n", + NV_PRINTF(LEVEL_INFO, "No buffer reserved for engineType %d (%d) in ctx_buf_pool\n", + gpuGetNv2080EngineType(pKernelChannelGroup->engineType), pKernelChannelGroup->engineType); } } } - if ((!bMIGInUse || NV2080_ENGINE_TYPE_IS_GR(pKernelChannelGroup->engineType)) + if ((!bMIGInUse || RM_ENGINE_TYPE_IS_GR(pKernelChannelGroup->engineType)) && !IsT234D(pGpu)) { NV_ASSERT_OK_OR_GOTO(rmStatus, @@ -548,7 +552,8 @@ kchangrpapiDestruct_IMPL goto done; } - kchangrpSetRealtime_HAL(pGpu, pKernelChannelGroup, NV_FALSE); + if (pKernelChannelGroup != NULL) + kchangrpSetRealtime_HAL(pGpu, pKernelChannelGroup, NV_FALSE); // If channels still exist in this group, free them // RS-TODO this can be removed after re-parenting support is added @@ -579,9 +584,9 @@ kchangrpapiDestruct_IMPL ctxBufPoolRelease(pKernelChannelGroup->pChannelBufPool); ctxBufPoolDestroy(&pKernelChannelGroup->pChannelBufPool); } - } - listClear(&pKernelChannelGroup->apiObjList); + listClear(&pKernelChannelGroup->apiObjList); + } done: serverFreeShare(&g_resServ, pShared); @@ -1134,14 +1139,14 @@ kchangrpapiCtrlCmdBind_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelChannelGroupApi); NvHandle hClient = RES_GET_CLIENT_HANDLE(pKernelChannelGroupApi); CHANNEL_NODE *pChanNode; - NvU32 localEngineType; - NvU32 globalEngineType; + RM_ENGINE_TYPE localEngineType; + RM_ENGINE_TYPE globalEngineType; ENGDESCRIPTOR engineDesc; NvBool bMIGInUse = IS_MIG_IN_USE(pGpu); NV_ASSERT_OR_RETURN(pParams != NULL, NV_ERR_INVALID_ARGUMENT); - localEngineType = globalEngineType = pParams->engineType; + localEngineType = globalEngineType = gpuGetRmEngineType(pParams->engineType); if (bMIGInUse) { @@ -1158,9 +1163,9 @@ kchangrpapiCtrlCmdBind_IMPL } NV_PRINTF(LEVEL_INFO, - "Binding TSG %d to Engine %d\n", + "Binding TSG %d to Engine %d (%d)\n", pKernelChannelGroupApi->pKernelChannelGroup->grpID, - globalEngineType); + gpuGetNv2080EngineType(globalEngineType), globalEngineType); // Translate globalEnginetype -> enginedesc NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(rmStatus, diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_ctxshare.c b/src/nvidia/src/kernel/gpu/fifo/kernel_ctxshare.c index 65909c657..b67d5f3c6 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_ctxshare.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_ctxshare.c @@ -115,11 +115,15 @@ kctxshareapiConstruct_IMPL NV_PRINTF(LEVEL_INFO, "Constructing Legacy Context Share\n"); NV_ASSERT(hVASpace == NV01_NULL_OBJECT); pVAS = pKernelChannelGroup->pVAS; + + pKernelCtxShareApi->hVASpace = pKernelChannelGroupApi->hVASpace; } else { NV_PRINTF(LEVEL_INFO, "Constructing Client Allocated Context Share\n"); rmStatus = vaspaceGetByHandleOrDeviceDefault(pClient, hDevice, hVASpace, &pVAS); + + pKernelCtxShareApi->hVASpace = hVASpace; } NV_ASSERT_OR_RETURN((rmStatus == NV_OK), rmStatus); @@ -578,8 +582,6 @@ kctxshareDestroyCommon_IMPL kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &grRouteInfo, &pKernelGraphics); - kgrctxReleaseSubctxResources_HAL(pGpu, pKernelGraphicsContext, pKernelGraphics, pKernelCtxShare->pVAS, pKernelCtxShare->subctxId); - pEngCtxDesc = pKernelChannelGroup->ppEngCtxDesc[subDevInst]; if (pEngCtxDesc != NULL) { diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c b/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c index 9d33143db..56e94a648 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -26,8 +26,10 @@ #include "kernel/gpu/fifo/kernel_channel_group.h" #include "kernel/gpu/fifo/kernel_channel_group_api.h" #include "kernel/gpu/fifo/kernel_sched_mgr.h" +#include "virtualization/kernel_vgpu_mgr.h" #include "rmapi/rs_utils.h" #include "rmapi/client.h" +#include "gpu/subdevice/subdevice.h" #include "kernel/core/locks.h" #include "lib/base_utils.h" @@ -228,11 +230,6 @@ _kfifoChidMgrAllocVChidHeapPointers return NV_OK; } - if (IS_GSP_CLIENT(pGpu)) - { - return NV_OK; - } - if (gpuIsSriovEnabled(pGpu)) { // @@ -331,7 +328,7 @@ _kfifoChidMgrAllocChidHeaps pChidMgr->pGlobalChIDHeap, NV_FALSE, RM_PAGE_SIZE / userdBar1Size); - #if (defined(_WIN32) || defined(_WIN64) || defined(NV_UNIX)) && !defined(NV_MODS) + #if (defined(_WIN32) || defined(_WIN64) || defined(NV_UNIX)) && !RMCFG_FEATURE_MODS_FEATURES NV_PRINTF(LEVEL_INFO, "Sub Process channel isolation disabled by vGPU plugin\n"); #endif @@ -484,6 +481,36 @@ _kfifoUserdOwnerComparator } } +/* + * @brief Returns the number of vGPU plugin channels. + * + * Depending on whether this code is executed on the CPU RM or the Physical RM, + * different structures are used to retrieve the number. + * On the CPU RM or the monolithic RM, KERNEL_HOST_VGPU_DEVICE::numPluginChannels is used, + * whereas on the physical RM it's HOST_VGPU_DEVICE::numPluginChannels. + */ +static NV_STATUS +_kfifoGetVgpuPluginChannelsCount +( + OBJGPU *pGpu, + NvU32 *pNumPluginChannels +) +{ + NV_ASSERT_OR_RETURN(pNumPluginChannels != NULL, NV_ERR_INVALID_ARGUMENT); + + if (!RMCFG_FEATURE_PLATFORM_GSP) + { + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice = NULL; + + NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextKernelHostVgpuDevice(pGpu, &pKernelHostVgpuDevice)); + NV_ASSERT_OR_RETURN(pKernelHostVgpuDevice != NULL, NV_ERR_OBJECT_NOT_FOUND); + + *pNumPluginChannels = pKernelHostVgpuDevice->numPluginChannels; + } + + return NV_OK; +} + /*! * @brief Allocates one Channel ID on heap * @@ -567,6 +594,90 @@ kfifoChidMgrAllocChid_IMPL NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &gfid)); + // SRIOV: In guest plugin context allocate the chid. + // In guest RM context allocate the same chid as guest + if (IS_GFID_VF(gfid)) + { + NvU32 numPluginChannels; + NvU64 rangeLo, rangeHi, base, size; + + NV_ASSERT_OR_RETURN(pChidMgr->ppVirtualChIDHeap[gfid], + NV_ERR_INVALID_STATE); + + NV_ASSERT_OK_OR_RETURN(_kfifoGetVgpuPluginChannelsCount(pGpu, &numPluginChannels)); + + pChidMgr->ppVirtualChIDHeap[gfid]->eheapGetBase( + pChidMgr->ppVirtualChIDHeap[gfid], + &base); + pChidMgr->ppVirtualChIDHeap[gfid]->eheapGetSize( + pChidMgr->ppVirtualChIDHeap[gfid], + &size); + + rangeLo = base; + rangeHi = base + size - 1; + + // Route plugin channels to be allocated at the top + NV_ASSERT_OR_RETURN(numPluginChannels < size, + NV_ERR_INVALID_PARAMETER); + if (pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup->bIsCallingContextVgpuPlugin && + numPluginChannels > 0) + { + rangeLo = rangeHi - numPluginChannels + 1; + } + else + { + rangeHi = rangeHi - numPluginChannels; + } + + status = pChidMgr->ppVirtualChIDHeap[gfid]->eheapSetAllocRange( + pChidMgr->ppVirtualChIDHeap[gfid], + rangeLo, + rangeHi); + + NV_ASSERT_OK_OR_RETURN(status); + + if (bForceUserdPage) + { + NV_ASSERT_OR_RETURN(!bForceInternalIdx, NV_ERR_INVALID_STATE); + ChID64 = ((NvU64)userdPageIdx) * + pChidMgr->ppVirtualChIDHeap[gfid]->ownerGranularity + + internalIdx; + chFlag |= NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE; + } + else if (bForceInternalIdx) + { + chFlag |= NVOS32_ALLOC_FLAGS_FORCE_INTERNAL_INDEX; + offsetAlign = internalIdx; + } + + if (chFlag & NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE) + NV_ASSERT_OR_RETURN((ChID64 <= rangeHi) && (ChID64 >= rangeLo), + NV_ERR_INVALID_PARAMETER); + + // We'll allocate from the VirtualChIdHeap for the guest + status = pChidMgr->ppVirtualChIDHeap[gfid]->eheapAlloc( + pChidMgr->ppVirtualChIDHeap[gfid], // This Heap + KFIFO_EHEAP_OWNER, // owner + &chFlag, // Alloc Flags + &ChID64, // Alloc Offset + &chSize, // Size + offsetAlign, // offsetAlign + 1, // sizeAlign + NULL, // Allocated mem block + NULL, // Isolation ID + NULL // Fifo defined ownership comparator + ); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to allocate Channel ID 0x%llx %d on heap \n", + ChID64, + chIdFlag); + DBG_BREAKPOINT(); + goto fail; + } + } + else { // // Legacy / SRIOV vGPU Host, SRIOV guest, baremetal CPU RM, GSP FW, GSP @@ -866,6 +977,207 @@ kfifoChidMgrFreeChid_IMPL return kfifoChidMgrReleaseChid(pGpu, pKernelFifo, pChidMgr, ChID); } +/** + * @brief Reserve a contiguous set of SCHIDs from the end of our CHID heap for + * the given GFID + * + + * @param[in] pChidMgr CHID_MGR pointer + * @param[in] numChannels Number of SCHIDs to reserve + * @param[in] pHostVgpuDevice HOST_VGPU_DEVICE + * + * @return NV_OK if success + */ +NV_STATUS +kfifoChidMgrReserveSystemChids_IMPL +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo, + CHID_MGR *pChidMgr, + NvU32 numChannels, + NvU32 flags, + NvU32 gfid, + NvU32 *pChidOffset, + NvHandle hMigClient, + NvU32 engineFifoListNumEntries, + FIFO_ENGINE_LIST *pEngineFifoList +) +{ + NV_STATUS status = NV_OK; + NvU64 chSize; + NvU64 offset = 0; + PFIFO_ISOLATIONID pIsolationID = NULL; + PEMEMBLOCK pIsolationIdBlock; + NvU32 userdBar1Size; + + if (IS_VIRTUAL(pGpu)) + { + // Not supported on guest or when SRIOV is disabled + return NV_ERR_NOT_SUPPORTED; + } + + pIsolationID = portMemAllocNonPaged(sizeof(FIFO_ISOLATIONID)); + NV_ASSERT_OR_RETURN((pIsolationID != NULL), NV_ERR_NO_MEMORY); + portMemSet(pIsolationID, 0, sizeof(FIFO_ISOLATIONID)); + + chSize = numChannels; + + status = pChidMgr->pGlobalChIDHeap->eheapAlloc( + pChidMgr->pGlobalChIDHeap, // This Heap + KFIFO_EHEAP_OWNER, // owner + &flags, // Alloc Flags + &offset, // Alloc Offset + &chSize, // Size + 1, // offsetAlign + 1, // sizeAlign + NULL, // Allocated mem block + pIsolationID, // IsolationID + _kfifoUserdOwnerComparator // Fifo defined ownership comparator + ); + + if(status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to reserve channel IDs. Status = 0x%x\n", status); + DBG_BREAKPOINT(); + + // + // Free the allocated memory and return early. After this, all failure + // points can goto the common cleanup label + // + portMemFree(pIsolationID); + return status; + } + + pIsolationIdBlock = pChidMgr->pGlobalChIDHeap->eheapGetBlock( + pChidMgr->pGlobalChIDHeap, + offset, + NV_FALSE); + if (pIsolationIdBlock == NULL) + { + // Something bad happened. This should not fail if allocation succeeded + NV_PRINTF(LEVEL_ERROR, "Could not fetch block from eheap\n"); + DBG_BREAKPOINT(); + goto cleanup; + } + pIsolationIdBlock->pData = pIsolationID; + + status = kfifoSetChidOffset(pGpu, pKernelFifo, pChidMgr, (NvU32)offset, + numChannels, gfid, pChidOffset, hMigClient, + engineFifoListNumEntries, pEngineFifoList); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to program the CHID table\n"); + goto cleanup; + } + + pChidMgr->ppVirtualChIDHeap[gfid] = portMemAllocNonPaged(sizeof(OBJEHEAP)); + if (pChidMgr->ppVirtualChIDHeap[gfid] == NULL) + { + status = NV_ERR_NO_MEMORY; + NV_PRINTF(LEVEL_ERROR, "Error allocating memory for virtual " + "channel ID heap\n"); + goto cleanup; + } + + // + // Construct heap using low as offset and size of numChannels. This heap + // will be used for guest channel ID allocations, but will be in the + // system channel ID space, hence it only manages IDs from offset to + // (offset + numChannels). + // + constructObjEHeap(pChidMgr->ppVirtualChIDHeap[gfid], offset, + (offset + numChannels), 0, 0); + + kfifoGetUserdSizeAlign_HAL(pKernelFifo, &userdBar1Size, NULL); + pChidMgr->ppVirtualChIDHeap[gfid]->eheapSetOwnerIsolation( + pChidMgr->ppVirtualChIDHeap[gfid], + NV_FALSE, + RM_PAGE_SIZE/userdBar1Size); + + return status; + +cleanup: + portMemFree(pChidMgr->ppVirtualChIDHeap[gfid]); + NV_ASSERT(kfifoSetChidOffset(pGpu, pKernelFifo, pChidMgr, 0, 0, + gfid, pChidOffset, hMigClient, + engineFifoListNumEntries, pEngineFifoList) == NV_OK); + NV_ASSERT(pChidMgr->pGlobalChIDHeap->eheapFree(pChidMgr->pGlobalChIDHeap, offset) == NV_OK); + portMemFree(pIsolationID); + return status; +} + +/*! Frees a block of contiguous SCHIDs previously reserved for the given GFID */ +NV_STATUS +kfifoChidMgrFreeSystemChids_IMPL +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo, + CHID_MGR *pChidMgr, + NvU32 gfid, + NvU32 *pChidOffset, + NvHandle hMigClient, + NvU32 engineFifoListNumEntries, + FIFO_ENGINE_LIST *pEngineFifoList +) +{ + NV_STATUS status, tmpStatus; + NvU64 chId; + + if (IS_VIRTUAL(pGpu)) + { + // Not supported on guest or when SRIOV is disabled + return NV_ERR_NOT_SUPPORTED; + } + + // Get the schid base + pChidMgr->ppVirtualChIDHeap[gfid]->eheapGetBase( + pChidMgr->ppVirtualChIDHeap[gfid], + &chId); + + status = _kfifoChidMgrFreeIsolationId(pChidMgr, (NvU32)chId); + if(status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to free IsolationId. Status = 0x%x\n", + status); + DBG_BREAKPOINT(); + return status; + } + + status = pChidMgr->pGlobalChIDHeap->eheapFree(pChidMgr->pGlobalChIDHeap, chId); + if(status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to free channel IDs. Status = 0x%x\n", + status); + DBG_BREAKPOINT(); + + // + // March on anyway to program the ChId table. We'll return an error + // if we get here though. + // + } + + tmpStatus = kfifoSetChidOffset(pGpu, pKernelFifo, pChidMgr, 0, 0, + gfid, pChidOffset, hMigClient, + engineFifoListNumEntries, pEngineFifoList); + if (tmpStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to program the CHID table\n"); + DBG_BREAKPOINT(); + return tmpStatus; + } + + pChidMgr->ppVirtualChIDHeap[gfid]->eheapDestruct(pChidMgr->ppVirtualChIDHeap[gfid]); + portMemFree(pChidMgr->ppVirtualChIDHeap[gfid]); + pChidMgr->ppVirtualChIDHeap[gfid] = NULL; + + return status; +} + NvU32 kfifoChidMgrGetNumChannels_IMPL ( @@ -1073,7 +1385,7 @@ kfifoGetChidMgrFromType_IMPL ( OBJGPU *pGpu, KernelFifo *pKernelFifo, - NvU32 engineType, + NvU32 engineInfoType, NvU32 val, CHID_MGR **ppChidMgr ) @@ -1087,7 +1399,7 @@ kfifoGetChidMgrFromType_IMPL *ppChidMgr = NULL; status = kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, - engineType, val, + engineInfoType, val, ENGINE_INFO_TYPE_RUNLIST, &runlistId); NV_CHECK_OR_RETURN(LEVEL_INFO, NV_OK == status, status); @@ -1271,8 +1583,7 @@ kfifoChannelGroupSetTimeslice_IMPL NV_PRINTF(LEVEL_INFO, "Setting TSG %d Timeslice to %lldus\n", pKernelChannelGroup->grpID, timesliceUs); - if (!RMCFG_FEATURE_PLATFORM_MODS && - (timesliceUs < kfifoRunlistGetMinTimeSlice_HAL(pKernelFifo))) + if (timesliceUs < kfifoRunlistGetMinTimeSlice_HAL(pKernelFifo)) { NV_PRINTF(LEVEL_ERROR, "Setting Timeslice to %lldus not allowed. Min value is %lldus\n", @@ -1420,6 +1731,82 @@ NV_STATUS kfifoGetNextKernelChannel_IMPL return NV_ERR_OBJECT_NOT_FOUND; } +/*! + * @brief Localize the engine info received from the host + * + * The host and the guest can run in different version of drivers, the guest driver + * can not directly use the raw MC_ENGINE_IDX values from the host. + * RM does not guarantee those values are consistent cross branches. + * + * To keep the compatibility between different version of branches, this function reconstructs + * of RM_ENGINE_TYPE, MC_ENGINE_IDX values based on NV2080_ENGINE_TYPE + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pFifo KernelFifo pointer + * @param[in/out] pEngine Pointer to engine info table to update + * + */ +static void +_kfifoLocalizeGuestEngineData +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo, + ENGINE_INFO *pEngineInfo +) +{ + const FIFO_GUEST_ENGINE_TABLE *guestEngineTable; + NvU32 guestEngineTableSz; + NvU32 nv2080EngineType; + NvU32 engineIdx; + NvU32 newEngineIdx; + NvU32 guestTableIdx; + + // This function should only be called in a vgpu guest RM + NV_ASSERT_OR_RETURN_VOID(IS_VIRTUAL(pGpu)); + + guestEngineTable = kfifoGetGuestEngineLookupTable(&guestEngineTableSz); + + newEngineIdx = 0; + + for (engineIdx = 0; engineIdx < pEngineInfo->engineInfoListSize; engineIdx++) + { + FIFO_ENGINE_LIST *pEngine = &pEngineInfo->engineInfoList[engineIdx]; + + // The actual data in engineData[ENGINE_INFO_TYPE_RM_ENGINE_TYPE] is NV2080 ENGINE TYPE. + nv2080EngineType = pEngine->engineData[ENGINE_INFO_TYPE_RM_ENGINE_TYPE]; + + for (guestTableIdx = 0; guestTableIdx < guestEngineTableSz; guestTableIdx++) + { + // Find the engine type supported by the guest + if (guestEngineTable[guestTableIdx].nv2080EngineType == nv2080EngineType) + break; + } + + if (guestTableIdx < guestEngineTableSz) + { + // Update the MC for the guest + pEngine->engineData[ENGINE_INFO_TYPE_MC] = guestEngineTable[guestTableIdx].mcIdx; + + // Update it with correct engine type + pEngine->engineData[ENGINE_INFO_TYPE_RM_ENGINE_TYPE] = gpuGetRmEngineType(nv2080EngineType); + + if (newEngineIdx != engineIdx) + { + // + // Move the engine info up to make sure the engine info table only contains data for + // guest supported engine types. + // + portMemCopy(&pEngineInfo->engineInfoList[newEngineIdx], sizeof(FIFO_ENGINE_LIST), + &pEngineInfo->engineInfoList[engineIdx], sizeof(FIFO_ENGINE_LIST)); + } + + newEngineIdx++; + } + } + + pEngineInfo->engineInfoListSize = newEngineIdx; +} + /*! * @brief Performs an RPC into Host RM to read its device info table. * @@ -1442,7 +1829,8 @@ kfifoGetHostDeviceInfoTable_KERNEL ( OBJGPU *pGpu, KernelFifo *pKernelFifo, - ENGINE_INFO *pEngineInfo + ENGINE_INFO *pEngineInfo, + NvHandle hMigClient ) { NV_STATUS status = NV_OK; @@ -1470,8 +1858,20 @@ kfifoGetHostDeviceInfoTable_KERNEL // RPC call for GSP will throw INVALID_CLIENT error with NULL handles if (IS_GSP_CLIENT(pGpu)) { - hClient = pGpu->hInternalClient; - hObject = pGpu->hInternalSubdevice; + if (!IS_MIG_IN_USE(pGpu)) + { + hClient = pGpu->hInternalClient; + hObject = pGpu->hInternalSubdevice; + } + else + { + hClient = hMigClient; + if ((status = CliGetSubDeviceHandleFromGpu(hClient, pGpu, &hObject)) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Unable to get subdevice handle.\n"); + return NV_ERR_INVALID_STATE; + } + } } // Allocate pHostEntries and params on the heap to avoid stack overflow @@ -1585,6 +1985,11 @@ kfifoGetHostDeviceInfoTable_KERNEL } } + if (IS_VIRTUAL(pGpu)) + { + _kfifoLocalizeGuestEngineData(pGpu, pKernelFifo, pEngineInfo); + } + // // Host RM sends back a copy of their devinfo table, which includes the SW // engine. This engine has no runlist, so decrement the runlist count. @@ -1632,7 +2037,7 @@ kfifoConstructEngineList_KERNEL NV_ASSERT_OK_OR_RETURN(gpuConstructDeviceInfoTable_HAL(pGpu)); } - NV_ASSERT_OK_OR_RETURN(kfifoGetHostDeviceInfoTable_HAL(pGpu, pKernelFifo, pEngineInfo)); + NV_ASSERT_OK_OR_RETURN(kfifoGetHostDeviceInfoTable_HAL(pGpu, pKernelFifo, pEngineInfo, 0)); return NV_OK; } @@ -1843,7 +2248,7 @@ kfifoChannelListDestroy_IMPL * * @param[IN] pGpu OBJGPU * @param[IN] pKernelFifo KernelFifo - * @param[IN] pEngines Which engines to check (NV2080_ENGINE_TYPE_***) + * @param[IN] pEngines Which engines to check (RM_ENGINE_TYPE_***) * @param[IN] engineCount Number of engines to check * * @return Returns NV_TRUE if any provided engines are active @@ -1853,7 +2258,7 @@ kfifoEngineListHasChannel_IMPL ( OBJGPU *pGpu, KernelFifo *pKernelFifo, - NvU32 *pEngines, + RM_ENGINE_TYPE *pEngines, NvU32 engineCount ) { @@ -1868,9 +2273,9 @@ kfifoEngineListHasChannel_IMPL while (kchannelGetNextKernelChannel(pGpu, &it, &pKernelChannel) == NV_OK) { NV_ASSERT_OR_ELSE(pKernelChannel != NULL, continue); - + // If the client supplied the engine type, directly check it - if (NV2080_ENGINE_TYPE_IS_VALID(kchannelGetEngineType(pKernelChannel))) + if (RM_ENGINE_TYPE_IS_VALID(kchannelGetEngineType(pKernelChannel))) { for (i = 0; i < engineCount; ++i) { @@ -1901,7 +2306,7 @@ kfifoEngineListHasChannel_IMPL for (i = 0; i < engineCount; ++i) { NV_ASSERT_OR_RETURN((kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, - ENGINE_INFO_TYPE_NV2080, pEngines[i], + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, (NvU32)pEngines[i], ENGINE_INFO_TYPE_RUNLIST, &runlistId) == NV_OK), NV_TRUE); if (kchannelGetRunlistId(pKernelChannel) == runlistId) { @@ -1935,10 +2340,10 @@ kfifoGetRunlistBufPool_IMPL ( OBJGPU *pGpu, KernelFifo *pKernelFifo, - NvU32 engineType + RM_ENGINE_TYPE rmEngineType ) { - return pKernelFifo->pRunlistBufPool[engineType]; + return pKernelFifo->pRunlistBufPool[rmEngineType]; } /** @@ -2128,10 +2533,10 @@ kfifoRunlistAllocBuffers_IMPL // If flag is set then allocate runlist from ctx buf pool if (allocFlags & MEMDESC_FLAGS_OWNED_BY_CTX_BUF_POOL) { - NvU32 engineType; + RM_ENGINE_TYPE rmEngineType; CTX_BUF_POOL_INFO *pCtxBufPool = NULL; status = kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, ENGINE_INFO_TYPE_RUNLIST, - runlistId, ENGINE_INFO_TYPE_NV2080, &engineType); + runlistId, ENGINE_INFO_TYPE_RM_ENGINE_TYPE, (NvU32 *)&rmEngineType); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, @@ -2139,11 +2544,12 @@ kfifoRunlistAllocBuffers_IMPL DBG_BREAKPOINT(); goto failed; } - status = ctxBufPoolGetGlobalPool(pGpu, CTX_BUF_ID_RUNLIST, engineType, &pCtxBufPool); + status = ctxBufPoolGetGlobalPool(pGpu, CTX_BUF_ID_RUNLIST, rmEngineType, &pCtxBufPool); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, - "Failed to get ctx buf pool for engine type 0x%x\n", engineType); + "Failed to get ctx buf pool for engine type 0x%x (0x%x)\n", + gpuGetNv2080EngineType(rmEngineType), rmEngineType); DBG_BREAKPOINT(); goto failed; } @@ -2612,12 +3018,73 @@ kfifoGetVChIdForSChId_FWCLIENT NvU32 *pVChid ) { + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice = NULL; + NV_ASSERT_OR_RETURN(pVChid != NULL, NV_ERR_INVALID_ARGUMENT); *pVChid = sChId; + NV_CHECK_OR_RETURN(LEVEL_INFO, IS_GFID_VF(gfid), NV_OK); + NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextKernelHostVgpuDevice(pGpu, &pKernelHostVgpuDevice)); + NV_ASSERT_OR_RETURN(pKernelHostVgpuDevice->gfid == gfid, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(engineId < (sizeof(pKernelHostVgpuDevice->chidOffset) / sizeof(pKernelHostVgpuDevice->chidOffset[0])), + NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(pKernelHostVgpuDevice->chidOffset[engineId] != 0, NV_ERR_INVALID_STATE); + + NV_ASSERT_OR_RETURN(sChId >= pKernelHostVgpuDevice->chidOffset[engineId], NV_ERR_INVALID_ARGUMENT); + + *pVChid = sChId - pKernelHostVgpuDevice->chidOffset[engineId]; + return NV_OK; } +/** + * @brief cache vChid <-> sChid offset + */ +NV_STATUS +kfifoSetChidOffset_IMPL +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo, + CHID_MGR *pChidMgr, + NvU32 offset, + NvU32 numChannels, + NvU32 gfid, + NvU32 *pChidOffset, + NvU32 hMigClient, + NvU32 engineFifoListNumEntries, + FIFO_ENGINE_LIST *pEngineFifoList +) +{ + NV_STATUS status = NV_OK; + RM_ENGINE_TYPE *pEngineIds = NULL; + NvU32 maxEngines = kfifoGetNumEngines_HAL(pGpu, pKernelFifo); + NvU32 numEngines, i; + + NV_ASSERT_OR_RETURN(pChidMgr != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pChidOffset != NULL, NV_ERR_INVALID_ARGUMENT); + + pEngineIds = portMemAllocNonPaged(sizeof(RM_ENGINE_TYPE) * maxEngines); + NV_ASSERT_OR_RETURN((pEngineIds != NULL), NV_ERR_NO_MEMORY); + portMemSet(pEngineIds, 0, sizeof(RM_ENGINE_TYPE) * maxEngines); + + NV_ASSERT_OK_OR_GOTO(status, kfifoGetEngineListForRunlist(pGpu, pKernelFifo, pChidMgr->runlistId, pEngineIds, &numEngines), cleanup) + + for (i = 0; i < numEngines; i++) + { + NV_ASSERT_OR_ELSE(NV2080_ENGINE_TYPE_IS_VALID(pEngineIds[i]), status = NV_ERR_INVALID_STATE; goto cleanup); + pChidOffset[pEngineIds[i]] = offset; + } + + NV_ASSERT_OK_OR_GOTO(status, kfifoProgramChIdTable_HAL(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, + hMigClient, engineFifoListNumEntries, pEngineFifoList), cleanup); + +cleanup: + + portMemFree(pEngineIds); + + return status; +} + /* * @brief Gets a list of engine ids that use this runlist * @@ -2631,7 +3098,7 @@ kfifoGetEngineListForRunlist_IMPL OBJGPU *pGpu, KernelFifo *pKernelFifo, NvU32 runlistId, - NvU32 *pOutEngineIds, + RM_ENGINE_TYPE *pOutEngineIds, NvU32 *pNumEngines ) { @@ -2648,7 +3115,7 @@ kfifoGetEngineListForRunlist_IMPL for (i = 0; i < numEngines; i++) { - NvU32 engineType; + RM_ENGINE_TYPE rmEngineType; NvU32 thisRunlistId; NV_ASSERT_OK_OR_GOTO(status, @@ -2663,13 +3130,13 @@ kfifoGetEngineListForRunlist_IMPL kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, ENGINE_INFO_TYPE_INVALID, i, - ENGINE_INFO_TYPE_NV2080, - &engineType), done); - pOutEngineIds[(*pNumEngines)++] = engineType; + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, + (NvU32 *)&rmEngineType), done); + pOutEngineIds[(*pNumEngines)++] = rmEngineType; NV_PRINTF(LEVEL_INFO, "Engine name: %s\n", - kfifoGetEngineName_HAL(pKernelFifo, ENGINE_INFO_TYPE_NV2080, - engineType)); + kfifoGetEngineName_HAL(pKernelFifo, ENGINE_INFO_TYPE_RM_ENGINE_TYPE, + (NvU32)rmEngineType)); } } done: @@ -2682,41 +3149,84 @@ done: } /** - * @brief Return bitmask of currently allocated channels. + * @brief Return bitmask of currently allocated channels for a given runlist + * + * @param[in] bitMaskSize @p pBitMask size in bytes * - * TODO: Deprecate this later */ -NvU32 +NV_STATUS kfifoGetAllocatedChannelMask_IMPL ( OBJGPU *pGpu, - KernelFifo *pKernelFifo + KernelFifo *pKernelFifo, + NvU32 runlistId, + NvU32 *pBitMask, + NvLength bitMaskSize ) { - CHID_MGR *pChidMgr = NULL; - KernelChannel *pKernelChannel = NULL; - NvU32 i; - NvU32 val; - NvU32 numChannels; + CHID_MGR *pChidMgr; + NvU32 chId; + NvU32 numChannels; - // Return 0 if using the new channel structure - if (kfifoIsPerRunlistChramEnabled(pKernelFifo)) + NV_ASSERT(pBitMask != NULL); + portMemSet(pBitMask, 0, bitMaskSize); + + NV_ASSERT_OR_RETURN(bitMaskSize % sizeof(NvU32) == 0, + NV_ERR_INVALID_ARGUMENT); + + if (!kfifoIsPerRunlistChramEnabled(pKernelFifo)) { - NV_PRINTF(LEVEL_ERROR, "not supported with per-runlist channel RAM\n"); - return 0; + if (runlistId > 0) + { + return NV_ERR_OUT_OF_RANGE; + } + else + { + runlistId = CHIDMGR_RUNLIST_ID_LEGACY; + } + } + else + { + if (!(runlistId < kfifoGetMaxNumRunlists_HAL(pGpu, pKernelFifo))) + { + return NV_ERR_OUT_OF_RANGE; + } } - pChidMgr = kfifoGetChidMgr(pGpu, pKernelFifo, CHIDMGR_RUNLIST_ID_LEGACY); - numChannels = kfifoChidMgrGetNumChannels(pGpu, pKernelFifo, pChidMgr); - - // Build bitmask of allocated channels - for (i = 0, val = 0; i < numChannels; i++) + pChidMgr = kfifoGetChidMgr(pGpu, pKernelFifo, runlistId); + if (pChidMgr == NULL) { - pKernelChannel = kfifoChidMgrGetKernelChannel(pGpu, pKernelFifo, pChidMgr, i); - val |= ((pKernelChannel != NULL) ? 1 << i : 0); + // + // This runlist is not valid. This is not an error since it might be + // possible for some runlists between [0, maxRunlists) to be invalid. + // Simply return that it has no channels to simplify clients iterating + // over all runlists. + // + numChannels = 0; + } + else + { + numChannels = kfifoChidMgrGetNumChannels(pGpu, pKernelFifo, pChidMgr); } - return val; + if (((numChannels + 7) / 8) > bitMaskSize) + { + return NV_ERR_BUFFER_TOO_SMALL; + } + + for (chId = 0; chId < numChannels; chId++) + { + KernelChannel *pKernelChannel; + pKernelChannel = kfifoChidMgrGetKernelChannel(pGpu, pKernelFifo, + pChidMgr, + chId); + if (pKernelChannel != NULL) + { + NV_BITMASK32_SET(pBitMask, chId); + } + } + + return NV_OK; } /*! @@ -2759,3 +3269,82 @@ kfifoGetChannelClassId_IMPL portMemFree(pClassList); return class; } + +/** + * @brief Return the FIFO_GUEST_ENGINE_TABLE + * + * @param[out] pEngLookupTblSize To get the table size + * + * @return a pointer to FIFO_GUEST_ENGINE_TABLE + * + */ +const FIFO_GUEST_ENGINE_TABLE * +kfifoGetGuestEngineLookupTable_IMPL +( + NvU32 *pEngLookupTblSize +) +{ + // + // This table is used for a guest RM to reconstruct the engine list data + // received from the host RM. The host and guest RM can be running on + // different versions. + // + // This table does not need to be HALified. It need to match NV2080_ENGINE_TYPE + // defined in cl2080_notification.h + // + const static FIFO_GUEST_ENGINE_TABLE guestEngineLookupTable[] = + { + // nv2080EngineType mcIdx + {NV2080_ENGINE_TYPE_GR0, MC_ENGINE_IDX_GR0}, + {NV2080_ENGINE_TYPE_GR1, MC_ENGINE_IDX_GR1}, + {NV2080_ENGINE_TYPE_GR2, MC_ENGINE_IDX_GR2}, + {NV2080_ENGINE_TYPE_GR3, MC_ENGINE_IDX_GR3}, + {NV2080_ENGINE_TYPE_GR4, MC_ENGINE_IDX_GR4}, + {NV2080_ENGINE_TYPE_GR5, MC_ENGINE_IDX_GR5}, + {NV2080_ENGINE_TYPE_GR6, MC_ENGINE_IDX_GR6}, + {NV2080_ENGINE_TYPE_GR7, MC_ENGINE_IDX_GR7}, + {NV2080_ENGINE_TYPE_COPY0, MC_ENGINE_IDX_CE0}, + {NV2080_ENGINE_TYPE_COPY1, MC_ENGINE_IDX_CE1}, + {NV2080_ENGINE_TYPE_COPY2, MC_ENGINE_IDX_CE2}, + {NV2080_ENGINE_TYPE_COPY3, MC_ENGINE_IDX_CE3}, + {NV2080_ENGINE_TYPE_COPY4, MC_ENGINE_IDX_CE4}, + {NV2080_ENGINE_TYPE_COPY5, MC_ENGINE_IDX_CE5}, + {NV2080_ENGINE_TYPE_COPY6, MC_ENGINE_IDX_CE6}, + {NV2080_ENGINE_TYPE_COPY7, MC_ENGINE_IDX_CE7}, + {NV2080_ENGINE_TYPE_COPY8, MC_ENGINE_IDX_CE8}, + {NV2080_ENGINE_TYPE_COPY9, MC_ENGINE_IDX_CE9}, + {NV2080_ENGINE_TYPE_NVENC0, MC_ENGINE_IDX_MSENC}, + {NV2080_ENGINE_TYPE_NVENC1, MC_ENGINE_IDX_MSENC1}, + {NV2080_ENGINE_TYPE_NVENC2, MC_ENGINE_IDX_MSENC2}, + {NV2080_ENGINE_TYPE_NVDEC0, MC_ENGINE_IDX_NVDEC0}, + {NV2080_ENGINE_TYPE_NVDEC1, MC_ENGINE_IDX_NVDEC1}, + {NV2080_ENGINE_TYPE_NVDEC2, MC_ENGINE_IDX_NVDEC2}, + {NV2080_ENGINE_TYPE_NVDEC3, MC_ENGINE_IDX_NVDEC3}, + {NV2080_ENGINE_TYPE_NVDEC4, MC_ENGINE_IDX_NVDEC4}, + {NV2080_ENGINE_TYPE_NVDEC5, MC_ENGINE_IDX_NVDEC5}, + {NV2080_ENGINE_TYPE_NVDEC6, MC_ENGINE_IDX_NVDEC6}, + {NV2080_ENGINE_TYPE_NVDEC7, MC_ENGINE_IDX_NVDEC7}, + {NV2080_ENGINE_TYPE_SW, MC_ENGINE_IDX_NULL}, + {NV2080_ENGINE_TYPE_SEC2, MC_ENGINE_IDX_SEC2}, + {NV2080_ENGINE_TYPE_NVJPEG0, MC_ENGINE_IDX_NVJPEG0}, + {NV2080_ENGINE_TYPE_NVJPEG1, MC_ENGINE_IDX_NVJPEG1}, + {NV2080_ENGINE_TYPE_NVJPEG2, MC_ENGINE_IDX_NVJPEG2}, + {NV2080_ENGINE_TYPE_NVJPEG3, MC_ENGINE_IDX_NVJPEG3}, + {NV2080_ENGINE_TYPE_NVJPEG4, MC_ENGINE_IDX_NVJPEG4}, + {NV2080_ENGINE_TYPE_NVJPEG5, MC_ENGINE_IDX_NVJPEG5}, + {NV2080_ENGINE_TYPE_NVJPEG6, MC_ENGINE_IDX_NVJPEG6}, + {NV2080_ENGINE_TYPE_NVJPEG7, MC_ENGINE_IDX_NVJPEG7}, + {NV2080_ENGINE_TYPE_OFA, MC_ENGINE_IDX_OFA0}, + }; + + // + // To trap NV2080_ENGINE_TYPE expansions. + // Please update the table guestEngineLookupTable if this assertion is triggered. + // + ct_assert(NV2080_ENGINE_TYPE_LAST == 0x0000003e); + + *pEngLookupTblSize = NV_ARRAY_ELEMENTS(guestEngineLookupTable); + + return guestEngineLookupTable; +}; + diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_ctrl.c b/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_ctrl.c index 349bdb415..9fa61353f 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_ctrl.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_ctrl.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -28,6 +28,7 @@ #include "kernel/gpu/subdevice/subdevice.h" #include "kernel/gpu/subdevice/subdevice_diag.h" #include "kernel/gpu/mem_mgr/mem_mgr.h" +#include "kernel/virtualization/hypervisor/hypervisor.h" #include "kernel/core/locks.h" #include "lib/base_utils.h" @@ -61,7 +62,7 @@ deviceCtrlCmdFifoGetChannelList_IMPL NvU32 *pChannelList = NvP64_VALUE(pChannelParams->pChannelList); NvU32 counter; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); // Validate input / Size / Args / Copy args if (pChannelParams->numChannels == 0) @@ -220,7 +221,7 @@ subdeviceCtrlCmdFifoGetInfo_IMPL NvU32 i; NvU32 data; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); // error checck if (pFifoInfoParams->fifoInfoTblSize > NV2080_CTRL_FIFO_GET_INFO_MAX_ENTRIES) @@ -258,6 +259,26 @@ subdeviceCtrlCmdFifoGetInfo_IMPL // data = kfifoGetMaxSubcontext_HAL(pGpu, pKernelFifo, NV_FALSE); break; + case NV2080_CTRL_FIFO_INFO_INDEX_BAR1_USERD_START_OFFSET: + { + NvU64 userdAddr; + NvU32 userdSize; + NvU32 gfid; + + NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &gfid)); + if (hypervisorIsVgxHyper() && IS_GFID_PF(gfid)) + { + status = kfifoGetUserdBar1MapInfo_HAL(pGpu, pKernelFifo, &userdAddr, &userdSize); + if (status == NV_OK) + data = (NvU32)(userdAddr >> NV2080_CTRL_FIFO_GET_INFO_USERD_OFFSET_SHIFT); + } + else + { + data = 0; + status = NV_ERR_INVALID_REQUEST; + } + break; + } case NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE: { NvU64 timeslice = kfifoChannelGroupGetDefaultTimeslice_HAL(pKernelFifo); @@ -271,15 +292,18 @@ subdeviceCtrlCmdFifoGetInfo_IMPL case NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS_PER_ENGINE: // Get runlist ID for Engine type. NV_ASSERT_OK_OR_RETURN(kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, - ENGINE_INFO_TYPE_NV2080, pFifoInfoParams->engineType, - ENGINE_INFO_TYPE_RUNLIST, &runlistId)); + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, + gpuGetRmEngineType(pFifoInfoParams->engineType), + ENGINE_INFO_TYPE_RUNLIST, + &runlistId)); pChidMgr = kfifoGetChidMgr(pGpu, pKernelFifo, runlistId); data = kfifoChidMgrGetNumChannels(pGpu, pKernelFifo, pChidMgr); break; case NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE_PER_ENGINE: // Get runlist ID for Engine type. NV_ASSERT_OK_OR_RETURN(kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, - ENGINE_INFO_TYPE_NV2080, pFifoInfoParams->engineType, + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, + gpuGetRmEngineType(pFifoInfoParams->engineType), ENGINE_INFO_TYPE_RUNLIST, &runlistId)); data = kfifoGetRunlistChannelGroupsInUse(pGpu, pKernelFifo, runlistId); break; @@ -299,6 +323,40 @@ subdeviceCtrlCmdFifoGetInfo_IMPL return status; } + +/*! + * @brief Get bitmask of allocated channels + */ +NV_STATUS subdeviceCtrlCmdFifoGetAllocatedChannels_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS *pParams +) +{ + KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(GPU_RES_GET_GPU(pSubdevice)); + NV_STATUS status; + + status = kfifoGetAllocatedChannelMask(GPU_RES_GET_GPU(pSubdevice), + pKernelFifo, + pParams->runlistId, + pParams->bitMask, + sizeof pParams->bitMask); + switch(status) + { + case NV_ERR_BUFFER_TOO_SMALL: + case NV_ERR_INVALID_ARGUMENT: + // + // Update the ctrl call structure to have sufficient space for 1 bit per + // possible channels in a runlist. This is a driver bug. + // + NV_ASSERT_OK(status); + return NV_ERR_NOT_SUPPORTED; + default: + return status; + } +} + + /*! * @brief subdeviceCtrlCmdFifoGetUserdLocation * @@ -320,7 +378,7 @@ subdeviceCtrlCmdFifoGetUserdLocation_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); rmStatus = deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice); if (rmStatus != NV_OK) @@ -396,7 +454,7 @@ subdeviceCtrlCmdFifoGetChannelMemInfo_IMPL MEMORY_DESCRIPTOR *pMemDesc = NULL; NV2080_CTRL_FIFO_CHANNEL_MEM_INFO chMemInfo; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); rmStatus = deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice); if (rmStatus != NV_OK) @@ -632,7 +690,7 @@ deviceCtrlCmdFifoGetCaps_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); NvU8 *pKfifoCaps = NvP64_VALUE(pKfifoCapsParams->capsTbl); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); // sanity check array size if (pKfifoCapsParams->capsTblSize != NV0080_CTRL_FIFO_CAPS_TBL_SIZE) @@ -663,7 +721,7 @@ deviceCtrlCmdFifoGetCapsV2_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); NvU8 *pKfifoCaps = pKfifoCapsParams->capsTbl; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); // now accumulate caps for entire device return _kfifoGetCaps(pGpu, pKfifoCaps); @@ -702,7 +760,7 @@ subdeviceCtrlCmdFifoDisableChannels_IMPL pRmCtrlParams->paramsSize, status); } - // Send internal control call to actually disable channels + // Send internal control call to actually disable channels else { status = NV_ERR_NOT_SUPPORTED; diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_init.c b/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_init.c index 262ce3e59..66ee7c582 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_init.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_init.c @@ -50,7 +50,7 @@ kfifoConstructEngine_IMPL portMemSet((void *)&pKernelFifo->userdInfo, 0, sizeof(PREALLOCATED_USERD_INFO)); - for (i = 0; i < NV2080_ENGINE_TYPE_LAST; i++) + for (i = 0; i < RM_ENGINE_TYPE_LAST; i++) { pKernelFifo->pRunlistBufPool[i] = NULL; } @@ -108,11 +108,8 @@ kfifoDestruct_IMPL listDestroy(&pKernelFifo->postSchedulingEnableHandlerList); listDestroy(&pKernelFifo->preSchedulingDisableHandlerList); - if (pKernelFifo->pKernelSchedMgr != NULL) - { - objDelete(pKernelFifo->pKernelSchedMgr); - pKernelFifo->pKernelSchedMgr = NULL; - } + objDelete(pKernelFifo->pKernelSchedMgr); + pKernelFifo->pKernelSchedMgr = NULL; portMemFree(pEngineInfo->engineInfoList); pEngineInfo->engineInfoList = NULL; @@ -173,14 +170,14 @@ kfifoStateDestroy_IMPL kfifoGetChannelIterator(pGpu, pKernelFifo, &chanIt); while ((kfifoGetNextKernelChannel(pGpu, pKernelFifo, &chanIt, &pKernelChannel) == NV_OK)) { - NvU32 engineType; + RM_ENGINE_TYPE rmEngineType; - engineType = kchannelGetEngineType(pKernelChannel); + rmEngineType = kchannelGetEngineType(pKernelChannel); - if (NV2080_ENGINE_TYPE_IS_GR(engineType)) + if (RM_ENGINE_TYPE_IS_GR(rmEngineType)) { MEMORY_DESCRIPTOR *grCtxBufferMemDesc = NULL; - NvU32 grIdx = NV2080_ENGINE_TYPE_GR_IDX(engineType); + NvU32 grIdx = RM_ENGINE_TYPE_GR_IDX(rmEngineType); NV_ASSERT_OK( kchangrpGetEngineContextMemDesc(pGpu, diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_sched_mgr.c b/src/nvidia/src/kernel/gpu/fifo/kernel_sched_mgr.c index ae2e0b5b7..4ec3822a5 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_sched_mgr.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_sched_mgr.c @@ -53,34 +53,12 @@ _kschedmgrGetSchedulerPolicy NvU32 *pSchedPolicy ) { - NvBool bSupportSwScheduler = NV_FALSE; NvU32 schedPolicy = SCHED_POLICY_DEFAULT; - // - // Disable OBJSCHED_SW_ENABLE when GPU is older than Pascal. - // This is true for WDDM and vGPU scheduling - if (!IsPASCALorBetter(pGpu)) - { - bSupportSwScheduler = NV_FALSE; - } - - // Disable OBJSCHED_SW_ENABLE when mig is enabled. - if (bSupportSwScheduler && IS_MIG_ENABLED(pGpu)) - { - bSupportSwScheduler = NV_FALSE; - portDbgPrintf("NVRM: Software Scheduler is not supported in MIG mode\n"); - } - *pSchedPolicy = schedPolicy; switch (schedPolicy) { - case SCHED_POLICY_VGPU_RELATIVE: - return "EQUAL_SHARE"; - case SCHED_POLICY_PGPU_SHARE: - return "FIXED_SHARE"; - case SCHED_POLICY_GFN_LSTT: - return "GFN_LSTT"; default: if (hypervisorIsVgxHyper()) return "BEST_EFFORT"; @@ -107,7 +85,7 @@ kschedmgrConstructPolicy_IMPL schedPolicyName = _kschedmgrGetSchedulerPolicy(pKernelSchedMgr, pGpu, &pKernelSchedMgr->configSchedPolicy); // PVMRL is disabled when GPU is older than Pascal - if (hypervisorIsVgxHyper() && IsPASCALorBetter(pGpu)) + if (((RMCFG_FEATURE_PLATFORM_GSP && IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) || hypervisorIsVgxHyper()) && IsPASCALorBetter(pGpu)) { pKernelSchedMgr->bIsSchedSwEnabled = (pKernelSchedMgr->configSchedPolicy != SCHED_POLICY_DEFAULT); @@ -126,8 +104,8 @@ kschedmgrConstructPolicy_IMPL schedPolicyName); } - // Enabled SWRL Granular locking only if SWRL is enabled on hypervisor. - if (hypervisorIsVgxHyper() && pKernelSchedMgr->bIsSchedSwEnabled) + // Enabled SWRL Granular locking only if SWRL is enabled on hypervisor or VGPU_GSP_PLUGIN_OFFLOAD is enabled + if (((RMCFG_FEATURE_PLATFORM_GSP && IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) || hypervisorIsVgxHyper()) && pKernelSchedMgr->bIsSchedSwEnabled) { pGpu->setProperty(pGpu, PDB_PROP_GPU_SWRL_GRANULAR_LOCKING, NV_TRUE); } diff --git a/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c b/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c index f3e542916..38ca138fe 100644 --- a/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c +++ b/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c @@ -47,7 +47,6 @@ #include "objflcnable.h" #endif - /*! * @brief Update command queue head and tail pointers * @@ -638,7 +637,7 @@ kfspWaitForSecureBoot_GH100 /*! * @brief Check if GSP-FMC Inst_in_sys ucode needs to be booted. - * + * * @param[in] pGpu OBJGPU pointer * @param[in] pKernelFsp KernelFsp pointer * @@ -667,29 +666,32 @@ kfspGetGspUcodeArchive if (pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_GSP_MODE_GSPRM)) { NV_PRINTF(LEVEL_ERROR, "Loading GSP-RM image using FSP.\n"); + if (kgspIsDebugModeEnabled_HAL(pGpu, pKernelGsp)) { - return kgspGetBinArchiveGspRmCcGfwDebugSigned_HAL(pKernelGsp); + { + return kgspGetBinArchiveGspRmFmcGfwDebugSigned_HAL(pKernelGsp); + } } else { - return kgspGetBinArchiveGspRmCcGfwProdSigned_HAL(pKernelGsp); - } + return kgspGetBinArchiveGspRmFmcGfwProdSigned_HAL(pKernelGsp); + } } #if RMCFG_MODULE_ENABLED (GSP) else { Gsp *pGsp = GPU_GET_GSP(pGpu); - NV_PRINTF(LEVEL_INFO, "Loading GSP image for monolithic RM using FSP.\n"); + // Intentional error print so that we know which mode RM is loaded with + NV_PRINTF(LEVEL_ERROR, "Loading GSP image for monolithic RM using FSP.\n"); if (gspIsDebugModeEnabled_HAL(pGpu, pGsp)) { if (kfspCheckGspSecureScratch_HAL(pGpu, pKernelFsp)) { - return gspGetBinArchiveGspCcInstInSysGfwDebugSigned_HAL(pGsp); + return gspGetBinArchiveGspFmcInstInSysGfwDebugSigned_HAL(pGsp); } - - if (pGsp->getProperty(pGsp, PDB_PROP_GSP_DISABLE_RESIDENT_IMAGE)) + else { // // Non Resident (GspCcGfw)Image will have just the FMC in it. @@ -698,29 +700,24 @@ kfspGetGspUcodeArchive // into to the FMC. FMC will then boot the RM Proxy. // NV_ASSERT_OR_RETURN(gspSetupRMProxyImage(pGpu, pGsp) == NV_OK, NULL); - return gspGetBinArchiveGspCcGfwDebugSigned_HAL(pGsp); - } - else - { - return gspGetBinArchiveGspCcResidentGfwDebugSigned_HAL(pGsp); + + { + return gspGetBinArchiveGspFmcGfwDebugSigned_HAL(pGsp); + } } } else { if (kfspCheckGspSecureScratch_HAL(pGpu, pKernelFsp)) { - return gspGetBinArchiveGspCcInstInSysGfwProdSigned_HAL(pGsp); - } - - if (!pGsp->getProperty(pGsp, PDB_PROP_GSP_DISABLE_RESIDENT_IMAGE)) - { - return gspGetBinArchiveGspCcResidentGfwProdSigned_HAL(pGsp); + return gspGetBinArchiveGspFmcInstInSysGfwProdSigned_HAL(pGsp); } else { - // There is no production signed non-resident image yet - NV_PRINTF(LEVEL_ERROR, "Cannot load GSP non-resident prod image on monolithic RM.\n"); - return NULL; + NV_ASSERT_OR_RETURN(gspSetupRMProxyImage(pGpu, pGsp) == NV_OK, NULL); + { + return gspGetBinArchiveGspFmcGfwProdSigned_HAL(pGsp); + } } } } @@ -789,6 +786,7 @@ kfspSetupGspImages pBinArchive = kfspGetGspUcodeArchive(pGpu, pKernelFsp); if (pBinArchive == NULL) { + NV_PRINTF(LEVEL_ERROR, "Cannot find correct ucode archive for booting!\n"); status = NV_ERR_OBJECT_NOT_FOUND; goto failed; } @@ -847,11 +845,8 @@ kfspSetupGspImages return NV_OK; failed: - if (pKernelFsp->pGspFmcMemdesc != NULL) - { - memdescDestroy(pKernelFsp->pGspFmcMemdesc); - pKernelFsp->pGspFmcMemdesc = NULL; - } + memdescDestroy(pKernelFsp->pGspFmcMemdesc); + pKernelFsp->pGspFmcMemdesc = NULL; return status; } @@ -874,7 +869,7 @@ _kfspCheckGspBootStatus // In Inst_in_sys mode GSP-FMC will write status to NV_PGSP_MAILBOX(0). if (kfspCheckGspSecureScratch_HAL(pGpu, pKernelFsp)) { - gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, GPU_TIMEOUT_FLAGS_OSTIMER | GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE); while(FLD_TEST_DRF_NUM(_PGSP, _MAILBOX, _DATA, GSP_INST_IN_SYS_COMPLETION_STATUS_IN_PROGRESS , GPU_REG_RD32(pGpu, NV_PGSP_MAILBOX(0)))) { status = gpuCheckTimeout(pGpu, &timeout); @@ -896,7 +891,7 @@ _kfspCheckGspBootStatus } // Ensure priv lockdown is released before polling interrupts - gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, GPU_TIMEOUT_FLAGS_OSTIMER | GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE); do { if (flcnIsRiscvLockdownReleased_HAL(pGpu, pFlcn)) @@ -1002,12 +997,12 @@ kfspSendBootCommands_GH100 ) { NV_STATUS status = NV_OK; + NV_STATUS statusBoot = NV_OK; NvU32 frtsSize = 0; NVDM_PAYLOAD_COT *pCotPayload = NULL; NvP64 pVaKernel = NULL; NvP64 pPrivKernel = NULL; - if (!IS_EMULATION(pGpu) && !IS_SILICON(pGpu)) { // @@ -1036,11 +1031,12 @@ kfspSendBootCommands_GH100 } // Confirm FSP secure boot partition is done - status = kfspWaitForSecureBoot_HAL(pGpu, pKernelFsp); - if (status != NV_OK) + statusBoot = kfspWaitForSecureBoot_HAL(pGpu, pKernelFsp); + + if (statusBoot != NV_OK) { NV_PRINTF(LEVEL_ERROR, "FSP secure boot partition timed out.\n"); - return status; + return statusBoot; } // Enforce GSP-FMC can only be booted by FSP on silicon. @@ -1123,6 +1119,7 @@ kfspSendBootCommands_GH100 status = kfspSetupGspImages(pGpu, pKernelFsp, pCotPayload); if (status!= NV_OK) { + NV_PRINTF(LEVEL_ERROR, "Ucode image preparation failed!\n"); goto failed; } @@ -1141,7 +1138,6 @@ kfspSendBootCommands_GH100 pCotPayload->frtsVidmemOffset, pCotPayload->frtsVidmemSize); NV_PRINTF(LEVEL_ERROR, "gspBootArgsSysmemOffset=0x%llx\n", pCotPayload->gspBootArgsSysmemOffset); - goto failed; } @@ -1166,11 +1162,8 @@ failed: NV_PRINTF(LEVEL_ERROR, "FSP boot cmds failed. RM cannot boot.\n"); kfspDumpDebugState_HAL(pGpu, pKernelFsp); - if (pKernelFsp->pSysmemFrtsMemdesc != NULL) - { - memdescDestroy(pKernelFsp->pSysmemFrtsMemdesc); - pKernelFsp->pSysmemFrtsMemdesc = NULL; - } + memdescDestroy(pKernelFsp->pSysmemFrtsMemdesc); + pKernelFsp->pSysmemFrtsMemdesc = NULL; portMemFree(pCotPayload); @@ -1201,3 +1194,17 @@ kfspErrorCode2NvStatusMap_GH100 return NV_ERR_GENERIC; } } + +/*! + * Size of extra memory required to be reserved after FRTS region + */ +NvU64 +kfspGetExtraReservedMemorySize_GH100 +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp +) +{ + // Bug: 3763996 + return 4 * 1024; +} diff --git a/src/nvidia/src/kernel/gpu/fsp/kern_fsp.c b/src/nvidia/src/kernel/gpu/fsp/kern_fsp.c index 1d37587dd..19dc79c50 100644 --- a/src/nvidia/src/kernel/gpu/fsp/kern_fsp.c +++ b/src/nvidia/src/kernel/gpu/fsp/kern_fsp.c @@ -148,11 +148,8 @@ kfspStateDestroy_IMPL KernelFsp *pKernelFsp ) { - if (pKernelFsp->pCotPayload != NULL) - { - portMemFree(pKernelFsp->pCotPayload); - pKernelFsp->pCotPayload = NULL; - } + portMemFree(pKernelFsp->pCotPayload); + pKernelFsp->pCotPayload = NULL; if (pKernelFsp->pSysmemFrtsMemdesc != NULL) { @@ -249,7 +246,7 @@ kfspPollForQueueEmpty_IMPL { RMTIMEOUT timeout; - gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, GPU_TIMEOUT_FLAGS_OSTIMER | GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE); while (!kfspIsQueueEmpty(pGpu, pKernelFsp)) { @@ -315,7 +312,7 @@ kfspPollForResponse_IMPL NV_STATUS status = NV_OK; // Poll for message queue to wait for FSP's reply - gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, GPU_TIMEOUT_FLAGS_OSTIMER | GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE); while (kfspIsMsgQueueEmpty(pGpu, pKernelFsp)) { if (gpuCheckTimeout(pGpu, &timeout) == NV_ERR_TIMEOUT) diff --git a/src/nvidia/src/kernel/gpu/gpu.c b/src/nvidia/src/kernel/gpu/gpu.c index ec7dfc61d..4497142a6 100644 --- a/src/nvidia/src/kernel/gpu/gpu.c +++ b/src/nvidia/src/kernel/gpu/gpu.c @@ -46,6 +46,9 @@ #include "rmapi/rmapi_utils.h" #include "core/hal_mgr.h" #include "vgpu/rpc.h" +#include "gpu/gpu_fabric_probe.h" + +#include "vgpu/vgpu_events.h" #include @@ -60,6 +63,17 @@ #include "diagnostics/gpu_acct.h" +#include "nvop.h" + +#include "virtualization/hypervisor/hypervisor.h" +#include "kernel/virtualization/kernel_vgpu_mgr.h" + +#include "gpu/bus/kern_bus.h" + +static void gpuSetupVirtualGuestOwnedHW(OBJHYPERVISOR *, OBJGPU *); + +static NV_STATUS gpuDetermineVirtualMode(OBJGPU *); + #include "g_odb.h" typedef struct GPUCHILDINFO *PGPUCHILDINFO; @@ -90,7 +104,6 @@ static NV_STATUS gpuStatePostUnload(OBJGPU *, NvU32); static void gpuXlateHalImplToArchImpl(OBJGPU *, HAL_IMPLEMENTATION, NvU32 *, NvU32 *); static NvBool gpuSatisfiesTemporalOrder(OBJGPU *, HAL_IMPLEMENTATION); static NvBool gpuSatisfiesTemporalOrderMaskRev(OBJGPU *, HAL_IMPLEMENTATION, NvU32, NvU32, NvU32); -static NvBool gpuIsT124ImplementationOrBetter(OBJGPU *); static NvBool gpuShouldCreateObject(PGPUCHILDINFO, PENGDESCRIPTOR, NvU32); static void gpuDestroyMissingEngine(OBJGPU *, OBJENGSTATE *); @@ -168,14 +181,60 @@ static Dynamic **gpuGetChildPtr(OBJGPU *pGpu, NvU32 gpuChildPtrOffset); #define GPU_NUM_CHILD_TYPES \ ((sizeof(gpuChildTypeList) / sizeof(GPUCHILDTYPE))) -/*! - * GFID allocation state - */ -typedef enum _gfid_alloc_state +static void +_gpuDetectNvswitchSupport +( + OBJGPU *pGpu +) { - GFID_FREE = 0, - GFID_ALLOCATED = 1 -} GFID_ALLOC_STATUS; + NvU32 data32; + + // + // Slowdown Threshold 0 leads to driver crash with DIVIDE ERROR + // Hence setting it to 1 + // + pGpu->fabricProbeRetryDelay = 0; + pGpu->fabricProbeSlowdownThreshold = 1; + pGpu->nvswitchSupport = NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_SUPPORTED; + + { + NvU32 status = NV_OK; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV2080_CTRL_PMGR_MODULE_INFO_PARAMS moduleInfoParams = {0}; + NV_CHECK_OK(status, LEVEL_ERROR, + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_PMGR_GET_MODULE_INFO, + &moduleInfoParams, + sizeof(moduleInfoParams))); + + if (status == NV_OK) + { + pGpu->moduleId = moduleInfoParams.moduleId; + pGpu->nvswitchSupport = moduleInfoParams.nvswitchSupport; + if (GPU_IS_NVSWITCH_DETECTED(pGpu)) + { + pGpu->fabricProbeRetryDelay = GPU_FABRIC_PROBE_DEFAULT_DELAY; + pGpu->fabricProbeSlowdownThreshold = + GPU_FABRIC_PROBE_DEFAULT_PROBE_SLOWDOWN_THRESHOLD; + } + } + } + + if (osReadRegistryDword(pGpu, NV_REG_STR_RM_GPU_FABRIC_PROBE, &data32) == NV_OK) + { + pGpu->fabricProbeSlowdownThreshold = + NV_MAX(DRF_VAL(_REG_STR, _RM_GPU_FABRIC_PROBE, _SLOWDOWN_THRESHOLD, data32), 1); + pGpu->fabricProbeRetryDelay = + DRF_VAL(_REG_STR, _RM_GPU_FABRIC_PROBE, _DELAY, data32); + + if (pGpu->fabricProbeRetryDelay) + { + pGpu->nvswitchSupport = NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_SUPPORTED; + } + } +} // // Generate a 32-bit id from domain, bus and device tuple. @@ -205,6 +264,12 @@ NvU32 gpuGenerate32BitId(NvU32 domain, NvU8 bus, NvU8 device) return id; } +NvU32 gpuGenerate32BitIdFromPhysAddr(RmPhysAddr addr) +{ + NvU32 id = NvU64_LO32(addr>>RM_PAGE_SHIFT); + return id; +} + void gpuChangeComputeModeRefCount_IMPL(OBJGPU *pGpu, NvU32 command) { switch(command) @@ -286,6 +351,14 @@ gpuPostConstruct_IMPL NV_ASSERT_OK_OR_RETURN(gpuPrivSecInitRegistryOverrides(pGpu)); + // check if RM is running in a virtualization mode + // This function needs to be called before we use IS_VIRTUAL macro. + // Because IS_VIRTUAL macro relies on this function to determine Virtual mode. + // eg. gpuCreateChildObjects->...->xxxHalIfacesSetup_xxx relies on IS_VIRTUAL macro. + rmStatus = gpuDetermineVirtualMode(pGpu); + if (rmStatus != NV_OK) + return rmStatus; + // // gpuDetermineVirtualMode inits hPci but only for virtualization case. So if // it does not init it, do here for using it for non-virtualization as well @@ -340,6 +413,16 @@ gpuPostConstruct_IMPL pGpu->bTwoStageRcRecoveryEnabled = NV_TRUE; } + if (hypervisorIsVgxHyper() || IS_VIRTUAL(pGpu)) + { + vgpuInitRegistryOverWrite(pGpu); + } + + if (hypervisorIsVgxHyper()) + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VGPU, NV_TRUE); + } + // create core objects (i.e. bif) rmStatus = gpuCreateChildObjects(pGpu, /* bConstructEarly */ NV_TRUE); if (rmStatus != NV_OK) @@ -669,7 +752,7 @@ static NV_STATUS _gpuAllocateInternalObjects if (IS_GSP_CLIENT(pGpu)) { - if (IsT234D(pGpu)) + if (IsT234DorBetter(pGpu)) { // // NOTE: We add +1 to the client base because DCE-RM will also @@ -688,6 +771,14 @@ static NV_STATUS _gpuAllocateInternalObjects pGpu->hInternalDevice = pGSCI->hInternalDevice; pGpu->hInternalSubdevice = pGSCI->hInternalSubdevice; } + + rmapiControlCacheSetGpuInstForObject(pGpu->hInternalClient, + pGpu->hInternalSubdevice, + pGpu->gpuInstance); + + rmapiControlCacheSetGpuInstForObject(pGpu->hInternalClient, + pGpu->hInternalDevice, + pGpu->gpuInstance); } else { @@ -701,6 +792,8 @@ static NV_STATUS _gpuAllocateInternalObjects &pGpu->pCachedSubdevice), done); } + NV_PRINTF(LEVEL_INFO, "GPU-%d allocated hInternalClient=0x%08x\n", pGpu->gpuInstance, pGpu->hInternalClient); + done: if (status != NV_OK) { @@ -715,7 +808,12 @@ static void _gpuFreeInternalObjects OBJGPU *pGpu ) { - if (!IS_GSP_CLIENT(pGpu)) + if (IS_GSP_CLIENT(pGpu)) + { + rmapiControlCacheFreeObjectEntry(pGpu->hInternalClient, pGpu->hInternalSubdevice); + rmapiControlCacheFreeObjectEntry(pGpu->hInternalClient, pGpu->hInternalDevice); + } + else { RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); @@ -1082,47 +1180,6 @@ gpuGetNextEngstate_IMPL(OBJGPU *pGpu, ENGSTATE_ITER *pIt, OBJENGSTATE **ppEngsta return NV_FALSE; } -/*! - * @brief Iterates over pGpu's child engstates that implement INTRABLE. - * Returns NV_FALSE when there are no more. - * - * @param[in] pGpu OBJGPU pointer - * @param[in,out] pIt Iterator - * @param[out] ppPmuclient The next PMU client - * - * @return NV_TRUE if ppPmuclient is valid, NV_FALSE if no more found - */ -NvBool -gpuGetNextStaticIntrable_IMPL(OBJGPU *pGpu, GPU_CHILD_ITER *pIt, OBJINTRABLE **ppIntrable) -{ - ENGDESCRIPTOR engDesc; - OBJHOSTENG *pHostEng; - OBJINTRABLE *pIntrable; - Dynamic **ppChild; - - while (gpuGetNextPossibleEngDescriptor(pIt, &engDesc)) - { - ppChild = gpuGetChildPtr(pGpu, pIt->gpuChildPtrOffset); - if (*ppChild != NULL) - { - pHostEng = dynamicCast(*ppChild, OBJHOSTENG); - - // Exclude host engines for now, as we only want static units - if (pHostEng == NULL) - { - pIntrable = dynamicCast(*ppChild, OBJINTRABLE); - if (pIntrable != NULL) - { - *ppIntrable = pIntrable; - return NV_TRUE; - } - } - } - } - - return NV_FALSE; -} - /*! * @brief Returns the hosteng for the child object with the given engine descriptor * @@ -1231,7 +1288,8 @@ gpuDestruct_IMPL Dynamic **pChildPtr; // Call gpuacctDisableAccounting if accounting is enabled since it does some memory deallocation - if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ACCOUNTING_ON)) + if (hypervisorIsVgxHyper() || + pGpu->getProperty(pGpu, PDB_PROP_GPU_ACCOUNTING_ON)) { GpuAccounting *pGpuAcct = SYS_GET_GPUACCT(SYS_GET_INSTANCE()); NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS params; @@ -1284,11 +1342,8 @@ gpuDestruct_IMPL pChildPtr = gpuGetChildPtr(pGpu, childInfoCur.gpuChildPtrOffset); - if (*pChildPtr) - { - objDelete(*pChildPtr); - *pChildPtr = NULL; - } + objDelete(*pChildPtr); + *pChildPtr = NULL; } } @@ -1466,11 +1521,11 @@ gpuGetGpuMask_IMPL static NV_STATUS gspSupportsEngine(OBJGPU *pGpu, ENGDESCRIPTOR engdesc, NvBool *supports) { + RM_ENGINE_TYPE clientEngineId = 0; + if (!IS_GSP_CLIENT(pGpu)) return NV_WARN_NOTHING_TO_DO; - NvU32 clientEngineId = 0; - if (gpuXlateEngDescToClientEngineId(pGpu, engdesc, &clientEngineId) != NV_OK) { NV_PRINTF(LEVEL_INFO, "Failed to xlate engdesc 0x%x\n", engdesc); @@ -1501,7 +1556,7 @@ static NV_STATUS gspSupportsEngine(OBJGPU *pGpu, ENGDESCRIPTOR engdesc, NvBool * NvU32 i; for (i = 0; i < pGpu->gspSupportedEngines->engineCount; i++) { - if (pGpu->gspSupportedEngines->engineList[i] == clientEngineId) + if (gpuGetRmEngineType(pGpu->gspSupportedEngines->engineList[i]) == clientEngineId) { *supports = NV_TRUE; return NV_OK; @@ -1850,6 +1905,9 @@ gpuStatePreInit_IMPL // Quadro, Geforce SMB, Tesla, VGX, Titan GPU detection gpuInitBranding(pGpu); + // Set PDB properties as per data from GSP. + gpuInitProperties(pGpu); + LOCK_ASSERT_AND_RETURN(rmGpuLockIsOwner()); NV_ASSERT_OK_OR_RETURN(_gpuAllocateInternalObjects(pGpu)); @@ -1927,6 +1985,8 @@ gpuStatePreInit_IMPL } } + gpuInitOptimusSettings(pGpu); + return rmStatus; } @@ -2091,6 +2151,8 @@ gpuStateLoad_IMPL pGpu->registerAccess.regReadCount = pGpu->registerAccess.regWriteCount = 0; RMTRACE_ENGINE_PROFILE_EVENT("gpuStateLoadStart", pGpu->gpuId, pGpu->registerAccess.regReadCount, pGpu->registerAccess.regWriteCount); + _gpuDetectNvswitchSupport(pGpu); + // Initialize SRIOV specific members of OBJGPU status = gpuInitSriov_HAL(pGpu); if (status != NV_OK) @@ -2192,6 +2254,34 @@ gpuStateLoad_IMPL } +{ + NvBool bVgpuOnGspEnabled = IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && RMCFG_FEATURE_PLATFORM_GSP; + if ((hypervisorIsVgxHyper() || bVgpuOnGspEnabled) && + !pGpu->getProperty(pGpu, PDB_PROP_GPU_ACCOUNTING_ON)) + { + OBJSYS *pSys = SYS_GET_INSTANCE(); + GpuAccounting *pGpuAcct = SYS_GET_GPUACCT(pSys); + NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS params; + NV_STATUS gpuacctStatus; + + // If VGX host, enable per process accounting by default. + params.gpuId = pGpu->gpuId; + params.pid = 0; + params.newState = NV0000_CTRL_GPU_ACCOUNTING_STATE_ENABLED; + + gpuacctStatus = gpuacctEnableAccounting(pGpuAcct, pGpu->gpuInstance, ¶ms); + + // Don't return this error since GPU accounting is just a reporting feature, we don't + // want to halt execution as a result of it failing + if (gpuacctStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "gpuacctEnableAccounting failed with error %d on GPU ID %d\n", + gpuacctStatus, pGpu->gpuId); + } + } +} + // Clear indicator that we are running state load pGpu->bStateLoading = NV_FALSE; @@ -2204,6 +2294,210 @@ gpuStateLoad_exit: return rmStatus; } +static NV_STATUS +_gpuRemoveP2pCapsFromPeerGpus +( + OBJGPU *pGpu +) +{ + OBJGPU *pPeerGpu = NULL; + NV_STATUS status = NV_OK; + NvU32 attachMask; + NvU32 gpuCount; + NvU32 gpuIndex; + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + gpumgrGetGpuAttachInfo(&gpuCount, &attachMask)); + gpuIndex = 0; + while ((pPeerGpu = gpumgrGetNextGpu(attachMask, &gpuIndex)) != NULL) + { + RM_API *pPeerRmApi = GPU_GET_PHYSICAL_RMAPI(pPeerGpu); + NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS removeP2PCapsParams = {0}; + + removeP2PCapsParams.peerGpuIdCount = 1; + removeP2PCapsParams.peerGpuIds[0] = pGpu->gpuId; + + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, + LEVEL_ERROR, + pPeerRmApi->Control(pPeerRmApi, + pPeerGpu->hInternalClient, + pPeerGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS, + &removeP2PCapsParams, + sizeof(removeP2PCapsParams))); + } + + return status; +} + +static NV_STATUS +_gpuPropagateP2PCapsToAllGpus +( + OBJGPU *pAttachedGpu +) +{ + NV_STATUS status = NV_OK; + NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS *pSetP2PCapsParams = NULL; + OBJGPU *pGpu = NULL; + NvU32 *peerGpuIds = NULL; + NvU32 *peerGpuInstances = NULL; + NvU32 attachMask; + NvU32 gpuCount; + NvU32 gpuIndex; + NvU32 failingGpuIndex; + NvU32 i; + + pSetP2PCapsParams = portMemAllocNonPaged(sizeof(*pSetP2PCapsParams)); + NV_CHECK_OR_RETURN(LEVEL_ERROR, + pSetP2PCapsParams != NULL, + NV_ERR_NO_MEMORY); + + peerGpuIds = portMemAllocNonPaged(sizeof(*peerGpuIds) * + NV_ARRAY_ELEMENTS32(pSetP2PCapsParams->peerGpuInfos)); + NV_CHECK_OR_ELSE(LEVEL_ERROR, + peerGpuIds != NULL, + status = NV_ERR_NO_MEMORY; goto exit); + + peerGpuInstances = portMemAllocNonPaged(sizeof(*peerGpuInstances) * + NV_ARRAY_ELEMENTS32(pSetP2PCapsParams->peerGpuInfos)); + NV_CHECK_OR_ELSE(LEVEL_ERROR, + peerGpuInstances != NULL, + status = NV_ERR_NO_MEMORY; goto exit); + + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + gpumgrGetGpuAttachInfo(&gpuCount, &attachMask), + exit); + + gpuIndex = 0; + while ((pGpu = gpumgrGetNextGpu(attachMask, &gpuIndex)) != NULL) + { + RM_API *pPeerRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + portMemSet(pSetP2PCapsParams, 0, sizeof(*pSetP2PCapsParams)); + + // The newly attached GPU needs to be informed of all of the current GPUs caps, + // whereas all the others need to be informed of the attached GPU only. + if (pGpu == pAttachedGpu) + { + NvU32 peerGpuIndex = 0; + OBJGPU *pPeerGpu = NULL; + + i = 0; + while ((pPeerGpu = gpumgrGetNextGpu(attachMask, &peerGpuIndex)) != NULL) + { + peerGpuIds[i] = pPeerGpu->gpuId; + peerGpuInstances[i] = gpuGetInstance(pPeerGpu); + i++; + } + + pSetP2PCapsParams->peerGpuCount = i; + } + else + { + pSetP2PCapsParams->peerGpuCount = 1; + + peerGpuIds[0] = pAttachedGpu->gpuId; + peerGpuInstances[0] = gpuGetInstance(pAttachedGpu); + } + + for (i = 0; i < pSetP2PCapsParams->peerGpuCount; i++) + { + NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO *pPeerInfo = NULL; + + pPeerInfo = &pSetP2PCapsParams->peerGpuInfos[i]; + pPeerInfo->gpuId = peerGpuIds[i]; + pPeerInfo->gpuInstance = peerGpuInstances[i]; + + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + CliGetSystemP2pCaps((NvU32[]) { pGpu->gpuId, pPeerInfo->gpuId }, + (pGpu->gpuId == pPeerInfo->gpuId) ? 1 : 2, + &pPeerInfo->p2pCaps, + &pPeerInfo->p2pOptimalReadCEs, + &pPeerInfo->p2pOptimalWriteCEs, + pPeerInfo->p2pCapsStatus, + &pPeerInfo->busPeerId), + fail); + } + + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + pPeerRmApi->Control(pPeerRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_SET_P2P_CAPS, + pSetP2PCapsParams, sizeof(*pSetP2PCapsParams)), + fail); + } + + goto exit; + +fail: + // Remove the caps from the successfully processed peer GPUs + failingGpuIndex = gpuIndex; + gpuIndex = 0; + while (((pGpu = gpumgrGetNextGpu(attachMask, &gpuIndex)) != NULL) && + (gpuIndex != failingGpuIndex)) + { + RM_API *pPeerRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS removeP2PCapsParams = {0}; + NV_STATUS ignoredStatus; + + if (pGpu == pAttachedGpu) + { + NvU32 peerGpuIndex = 0; + OBJGPU *pPeerGpu = NULL; + + while ((pPeerGpu = gpumgrGetNextGpu(attachMask, &peerGpuIndex)) != NULL) + { + removeP2PCapsParams.peerGpuIds[removeP2PCapsParams.peerGpuIdCount] = pPeerGpu->gpuId; + removeP2PCapsParams.peerGpuIdCount++; + } + } + else + { + removeP2PCapsParams.peerGpuIdCount = 1; + removeP2PCapsParams.peerGpuIds[0] = pAttachedGpu->gpuId; + } + + NV_CHECK_OK(ignoredStatus, + LEVEL_ERROR, + pPeerRmApi->Control(pPeerRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_REMOVE_P2P_CAPS, + &removeP2PCapsParams, sizeof(removeP2PCapsParams))); + } + +exit: + portMemFree(pSetP2PCapsParams); + pSetP2PCapsParams = NULL; + + portMemFree(peerGpuIds); + peerGpuIds = NULL; + + portMemFree(peerGpuInstances); + peerGpuInstances = NULL; + + return status; +} + +static NV_STATUS +_gpuSetVgpuMgrConfig +( + OBJGPU *pGpu +) +{ + RM_API *pPeerRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS params = {0}; + + if (osIsVgpuVfioPresent() != NV_OK) + return NV_OK; + + params.bSupportHeterogeneousTimeSlicedVgpuTypes = (osIsVgpuVfioPresent() == NV_OK); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + pPeerRmApi->Control(pPeerRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG, + ¶ms, sizeof(params))); + + return NV_OK; +} + /*! * @brief Top level post-load routine * @@ -2275,6 +2569,24 @@ gpuStatePostLoad goto gpuStatePostLoad_exit; } + NV_CHECK_OK_OR_GOTO(rmStatus, + LEVEL_ERROR, + _gpuSetVgpuMgrConfig(pGpu), + gpuStatePostLoad_exit); + + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && IS_GSP_CLIENT(pGpu)) + { + NV_CHECK_OK_OR_GOTO(rmStatus, + LEVEL_ERROR, + _gpuPropagateP2PCapsToAllGpus(pGpu), + gpuStatePostLoad_exit); + + NV_CHECK_OK_OR_GOTO(rmStatus, + LEVEL_ERROR, + kvgpumgrSendAllVgpuTypesToGsp(pGpu), + gpuStatePostLoad_exit); + } + pGpu->boardInfo = portMemAllocNonPaged(sizeof(*pGpu->boardInfo)); if (pGpu->boardInfo) { @@ -2294,6 +2606,8 @@ gpuStatePostLoad pGpu->boardInfo = NULL; } } + NV_ASSERT_OR_GOTO(gpuFabricProbeStart(pGpu, &pGpu->pGpuFabricProbeInfo) == NV_OK, + gpuStatePostLoad_exit); gpuStatePostLoad_exit: return rmStatus; @@ -2330,6 +2644,10 @@ gpuStatePreUnload NvU32 curEngDescIdx; NV_STATUS rmStatus = NV_OK; + rmapiControlCacheFreeAllCacheForGpu(pGpu->gpuInstance); + + gpuFabricProbeStop(pGpu->pGpuFabricProbeInfo); + portMemFree(pGpu->boardInfo); pGpu->boardInfo = NULL; @@ -2588,6 +2906,11 @@ gpuStatePostUnload gpuServiceInterruptsAllGpus(pGpu); } + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && IS_GSP_CLIENT(pGpu)) + { + NV_ASSERT_OK(_gpuRemoveP2pCapsFromPeerGpus(pGpu)); + } + return rmStatus; } @@ -2663,6 +2986,8 @@ gpuStateDestroy_IMPL pGpu->bFullyConstructed = NV_FALSE; + gpuDeinitOptimusSettings(pGpu); + return rmStatus; } @@ -2698,6 +3023,131 @@ gpuIsImplementation_IMPL return result; } +/*! + * @brief Initialize SBIOS settings for Optimus GOLD to driver loaded state. + * + * @param[in] pGpu GPU object pointer + * + * @return NV_OK + */ +NV_STATUS +gpuInitOptimusSettings_IMPL(OBJGPU *pGpu) +{ + OBJOS *pOS = GPU_GET_OS(pGpu); + NV_STATUS status; + NvU32 inOut; + NvU32 data32; + NvU16 rtnSize; + + // Check regkey settings + if (osReadRegistryDword(pGpu, NV_REG_STR_RM_D3_FEATURE, + &data32) == NV_OK) + { + // Enabled by default + if (FLD_TEST_DRF(_REG_STR_RM, _D3_FEATURE, _DRIVER_CFG_SPACE_RESTORE, _DISABLED, data32)) + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_OPTIMUS_GOLD_CFG_SPACE_RESTORE, NV_FALSE); + + // return early so we do not change SBIOS behaviour + return NV_OK; + } + } + + // + // For Optimus GOLD + GC6 systems, the _OFF and _ON ACPI methods are shared + // between normal GOLD entry and exit and GC6 TDR recovery paths. + // + // Previously SBIOS has saved and restored the GPU config space within + // the _OFF and _ON methods, but for GC6 TDR recovery this + // will not work and we need to restore config space in driver instead. + // + // To support both old and new configurations we query the SBIOS + // capabilities to indicate to SBIOS that driver supports the config + // space restore. If SBIOS also supports this, then it will indicate + // to driver that driver has the ownership. Otherwise SBIOS will fallback + // to owning the save and restore itself. + // + // This behavior is summarized by the following table: + // +============+=======+==========+========+========+=================+ + // | DRIVER | SBIOS | WR_EN | TARGET | ACTUAL | GC6 TDR Support | + // +============+=======+==========+========+========+=================+ + // | X | OLD | X | X | SBIOS | NO | + // | OLD | NEW | FALSE | X | SBIOS | NO | + // | NEW-LOAD | NEW | TRUE | DRIVER | DRIVER | YES | + // | NEW-UNLOAD | NEW | TRUE | SBIOS | SBIOS | NO DRIVER | + // +------------+------------------+--------+--------+-----------------+ + // + // NEW-LOAD and NEW-UNLOAD represent the states when a new driver loads + // and unloads. It is important for new drivers to restore the ownership back + // to SBIOS in case an old driver is loaded without a cold reboot. + // + rtnSize = (NvU16)sizeof(inOut); + inOut = 0; + inOut = FLD_SET_DRF(OP_FUNC, _OPTIMUSCAPS, _CFG_SPACE_OWNER_WR_EN, _TRUE, inOut); + inOut = FLD_SET_DRF(OP_FUNC, _OPTIMUSCAPS, _CFG_SPACE_OWNER_TARGET, _DRIVER, inOut); + + // + // It doesn't matter if this was not successful as we will enable the driver side + // save restore anyway. This call is to save some work for the SBIOS if possible. + // + status = pOS->osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_NVOP, + NVOP_FUNC_OPTIMUSCAPS, + &inOut, + &rtnSize); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "SBIOS did not acknowledge cfg space owner change\n"); + } + + return NV_OK; +} + +/*! + * @brief Restore SBIOS settings for Optimus GOLD to driver unloaded state. + * + * @param[in] pGpu GPU object pointer + * + * @return NV_OK if successful + * @return NV_ERR_INVALID_STATE if SBIOS failed to acknowledge the restore request + * @return Bubbles up error codes on ACPI call failure + */ +NV_STATUS +gpuDeinitOptimusSettings_IMPL(OBJGPU *pGpu) +{ + OBJOS *pOS = GPU_GET_OS(pGpu); + NV_STATUS status; + NvU32 inOut; + NvU16 rtnSize; + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_OPTIMUS_GOLD_CFG_SPACE_RESTORE)) + { + rtnSize = (NvU16)sizeof(inOut); + inOut = 0; + inOut = FLD_SET_DRF(OP_FUNC, _OPTIMUSCAPS, _CFG_SPACE_OWNER_WR_EN, _TRUE, inOut); + inOut = FLD_SET_DRF(OP_FUNC, _OPTIMUSCAPS, _CFG_SPACE_OWNER_TARGET, _SBIOS, inOut); + + status = pOS->osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_NVOP, + NVOP_FUNC_OPTIMUSCAPS, + &inOut, + &rtnSize); + // NV_ASSERT_OR_RETURN(status == NV_OK, status); + // NV_ASSERT_OR_RETURN(FLD_TEST_DRF(OP_FUNC, _OPTIMUSCAPS, _CFG_SPACE_OWNER_ACTUAL, + // _SBIOS, inOut), + // NV_ERR_INVALID_STATE); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_INFO, + "SBIOS did not acknowledge cfg space owner change\n"); + } + } + + return NV_OK; +} + // Check the software state to decide if we are in full power mode or not. NvBool gpuIsGpuFullPower_IMPL @@ -2741,6 +3191,55 @@ gpuIsGpuFullPowerForPmResume_IMPL return retVal; } +static NV_STATUS +gpuDetermineVirtualMode +( + OBJGPU *pGpu +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJOS *pOS = SYS_GET_OS(pSys); + OBJGPU *pGpuTemp; + OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys); + NvU32 gpuAttachMask, gpuInstance; + NvBool bIsVirtual = NV_FALSE; + + if (pGpu->bIsSOC || pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY)) + { + return NV_OK; + } + + // Using Hypervisor native interface to detect + if (pHypervisor && (!pHypervisor->bDetected)) + hypervisorDetection(pHypervisor, pOS); + + gpumgrGetGpuAttachInfo(NULL, &gpuAttachMask); + gpuInstance = 0; + + gpuSetupVirtualGuestOwnedHW(pHypervisor, pGpu); + + // Checking if the VM is already vGPU enabled. + // NMOS and vGPU cannot be simultaneously enabled on a VM. + if (pGpu->bIsPassthru) + { + while ((pGpuTemp = gpumgrGetNextGpu(gpuAttachMask, &gpuInstance)) != NULL) + { + if (IS_VIRTUAL(pGpuTemp)) + { + NV_PRINTF(LEVEL_ERROR, + "vGPU and Passthrough not supported simultaneously on the same VM.\n"); + pGpu->bIsPassthru = NV_FALSE; + return NV_ERR_NOT_SUPPORTED; + } + } + } + + // Early detection at GPU creation time should be consistent to the real detection + NV_ASSERT_OR_RETURN(pGpu->isVirtual == bIsVirtual, NV_ERR_INVALID_STATE); + + return NV_OK; +} + NvBool gpuIsImplementationOrBetter_IMPL ( @@ -3029,6 +3528,20 @@ gpuXlateHalImplToArchImpl break; } + case HAL_IMPL_AD106: + { + *gpuArch = GPU_ARCHITECTURE_ADA; + *gpuImpl = GPU_IMPLEMENTATION_AD106; + break; + } + + case HAL_IMPL_AD107: + { + *gpuArch = GPU_ARCHITECTURE_ADA; + *gpuImpl = GPU_IMPLEMENTATION_AD107; + break; + } + case HAL_IMPL_GH100: { *gpuArch = GPU_ARCHITECTURE_HOPPER; @@ -3066,17 +3579,6 @@ gpuSatisfiesTemporalOrder switch (halImpl) { - // - // Comparison of Tegra series isn't straightforward with the chip ids - // following different formats and so we can't use them - // to figure out the relative ordering of chips. - // T12X, T13X use 0x40, 0x13. - // - case HAL_IMPL_T124: - { - result = gpuIsT124ImplementationOrBetter(pGpu); - break; - } default: { HAL_IMPLEMENTATION chipImpl = pGpu->halImpl; @@ -3091,45 +3593,72 @@ gpuSatisfiesTemporalOrder return result; } -/*! - * @brief Checks if current GPU is T124OrBetter - * - * T124+ corresponds to BIG-GPU tegra chips that - * are either T124 or beyond. - * ChipArch which the generic implementation relies - * on doesn't give the hierarchy of chips - * accurately. Hence the explicit check for chips - * below. - * - * @param[in] pGpu GPU object pointer - * - * @returns NV_TRUE if T124 or any later big-gpu tegra chip, - * NV_FALSE otherwise - */ -static NvBool -gpuIsT124ImplementationOrBetter +static void +gpuSetupVirtualGuestOwnedHW ( + OBJHYPERVISOR *pHypervisor, OBJGPU *pGpu ) { - NvU32 chipArch = gpuGetChipArch(pGpu); - NvU32 chipImpl = gpuGetChipImpl(pGpu); + if (RMCFG_FEATURE_PLATFORM_MODS || IS_SIMULATION(pGpu)) + { + // platform lacks method to issue PCI config read cycles (so, not detected). + return; + } - // - // All Big-gpu chips like T124, T132 or later satisy the condition. - // This makes the assumption that starting from T186, there are no - // AURORA chips. - // - return (((chipArch == GPU_ARCHITECTURE_T12X) && (chipImpl == GPU_IMPLEMENTATION_T124)) || - ((chipArch == GPU_ARCHITECTURE_T13X) && (chipImpl == GPU_IMPLEMENTATION_T132)) || - ((chipArch == GPU_ARCHITECTURE_T21X) && (chipImpl == GPU_IMPLEMENTATION_T210)) || - ((chipArch == GPU_ARCHITECTURE_T19X) && (chipImpl == GPU_IMPLEMENTATION_T194)) || - ((chipArch == GPU_ARCHITECTURE_T23X) && (chipImpl == GPU_IMPLEMENTATION_T234D)) || - ((chipArch == GPU_ARCHITECTURE_T23X) && (chipImpl == GPU_IMPLEMENTATION_T234)) || - ((chipArch >= GPU_ARCHITECTURE_T18X) && (chipImpl == GPU_IMPLEMENTATION_T186))); + NvU32 cfgBaseAddressLow, domain; + NvU8 bus = 0, device = 0; + void *handle = NULL; + + if (!pHypervisor || !pHypervisor->bDetected || !pHypervisor->bIsHVMGuest) + return; + + domain = gpuGetDomain(pGpu); + bus = gpuGetBus(pGpu); + device = gpuGetDevice(pGpu); + + handle = osPciInitHandle(domain, bus, device, 0, NULL, NULL); + + _setPlatformNoHostbridgeDetect((handle == NULL) ? NV_FALSE : NV_TRUE); + + if (handle == NULL) + { + return; + } + + pGpu->hPci = handle; + + if (!IS_VIRTUAL_WITH_SRIOV(pGpu) && !IS_VIRTUAL(pGpu)) + { + cfgBaseAddressLow = osPciReadDword(handle, NV_CONFIG_PCI_NV_5); + + if (!IS_BAR_64(cfgBaseAddressLow)) + { + if (osPciReadDword(handle, NV_CONFIG_PCI_NV_6) != 0) + { + // We can access the BAR2 from 0x18, so the BAR2 is moved by host. + pGpu->bBar2MovedByVtd = NV_TRUE; + NV_PRINTF(LEVEL_WARNING, "VT-d moved BAR2 to 0x18!\n"); + } + else + { + NV_PRINTF(LEVEL_WARNING, "VT-d still keeps BAR2 at 0x1C!\n"); + } + } + else + { + pGpu->bBar1Is64Bit = NV_TRUE; + NV_PRINTF(LEVEL_WARNING, "VT-d is using a 64bit BAR1!\n"); + } + + pGpu->bIsPassthru = NV_TRUE; + + NV_PRINTF(LEVEL_WARNING, + "GPU at domain: %d bus: %d, device: %d is virtual (HW passthrough mode).\n", + domain, bus, device); + } } - // // default Logic: If arch = requested AND impl = requested AND // maskRev is >= requested --> NV_TRUE @@ -3156,7 +3685,7 @@ gpuSatisfiesTemporalOrderMaskRev // =============== Engine Database ============================== typedef struct { - NvU32 clientEngineId; + RM_ENGINE_TYPE clientEngineId; NVOC_CLASS_ID class; NvU32 instance; NvBool bHostEngine; @@ -3164,51 +3693,51 @@ typedef struct { static const EXTERN_TO_INTERNAL_ENGINE_ID rmClientEngineTable[] = { - { NV2080_ENGINE_TYPE_GR0, classId(Graphics) , 0, NV_TRUE }, - { NV2080_ENGINE_TYPE_GR1, classId(Graphics) , 1, NV_TRUE }, - { NV2080_ENGINE_TYPE_GR2, classId(Graphics) , 2, NV_TRUE }, - { NV2080_ENGINE_TYPE_GR3, classId(Graphics) , 3, NV_TRUE }, - { NV2080_ENGINE_TYPE_GR4, classId(Graphics) , 4, NV_TRUE }, - { NV2080_ENGINE_TYPE_GR5, classId(Graphics) , 5, NV_TRUE }, - { NV2080_ENGINE_TYPE_GR6, classId(Graphics) , 6, NV_TRUE }, - { NV2080_ENGINE_TYPE_GR7, classId(Graphics) , 7, NV_TRUE }, - { NV2080_ENGINE_TYPE_COPY0, classId(OBJCE) , 0, NV_TRUE }, - { NV2080_ENGINE_TYPE_COPY1, classId(OBJCE) , 1, NV_TRUE }, - { NV2080_ENGINE_TYPE_COPY2, classId(OBJCE) , 2, NV_TRUE }, - { NV2080_ENGINE_TYPE_COPY3, classId(OBJCE) , 3, NV_TRUE }, - { NV2080_ENGINE_TYPE_COPY4, classId(OBJCE) , 4, NV_TRUE }, - { NV2080_ENGINE_TYPE_COPY5, classId(OBJCE) , 5, NV_TRUE }, - { NV2080_ENGINE_TYPE_COPY6, classId(OBJCE) , 6, NV_TRUE }, - { NV2080_ENGINE_TYPE_COPY7, classId(OBJCE) , 7, NV_TRUE }, - { NV2080_ENGINE_TYPE_COPY8, classId(OBJCE) , 8, NV_TRUE }, - { NV2080_ENGINE_TYPE_COPY9, classId(OBJCE) , 9, NV_TRUE }, - { NV2080_ENGINE_TYPE_NVDEC0, classId(OBJBSP) , 0, NV_TRUE }, - { NV2080_ENGINE_TYPE_NVDEC1, classId(OBJBSP) , 1, NV_TRUE }, - { NV2080_ENGINE_TYPE_NVDEC2, classId(OBJBSP) , 2, NV_TRUE }, - { NV2080_ENGINE_TYPE_NVDEC3, classId(OBJBSP) , 3, NV_TRUE }, - { NV2080_ENGINE_TYPE_NVDEC4, classId(OBJBSP) , 4, NV_TRUE }, - { NV2080_ENGINE_TYPE_NVDEC5, classId(OBJBSP) , 5, NV_TRUE }, - { NV2080_ENGINE_TYPE_NVDEC6, classId(OBJBSP) , 6, NV_TRUE }, - { NV2080_ENGINE_TYPE_NVDEC7, classId(OBJBSP) , 7, NV_TRUE }, - { NV2080_ENGINE_TYPE_CIPHER, classId(OBJCIPHER) , 0, NV_TRUE }, - { NV2080_ENGINE_TYPE_NVENC0, classId(OBJMSENC) , 0, NV_TRUE }, - { NV2080_ENGINE_TYPE_NVENC1, classId(OBJMSENC) , 1, NV_TRUE }, - { NV2080_ENGINE_TYPE_NVENC2, classId(OBJMSENC) , 2, NV_TRUE }, - { NV2080_ENGINE_TYPE_SW, classId(OBJSWENG) , 0, NV_TRUE }, - { NV2080_ENGINE_TYPE_SEC2, classId(OBJSEC2) , 0, NV_TRUE }, - { NV2080_ENGINE_TYPE_NVJPEG0, classId(OBJNVJPG) , 0, NV_TRUE }, - { NV2080_ENGINE_TYPE_NVJPEG1, classId(OBJNVJPG) , 1, NV_TRUE }, - { NV2080_ENGINE_TYPE_NVJPEG2, classId(OBJNVJPG) , 2, NV_TRUE }, - { NV2080_ENGINE_TYPE_NVJPEG3, classId(OBJNVJPG) , 3, NV_TRUE }, - { NV2080_ENGINE_TYPE_NVJPEG4, classId(OBJNVJPG) , 4, NV_TRUE }, - { NV2080_ENGINE_TYPE_NVJPEG5, classId(OBJNVJPG) , 5, NV_TRUE }, - { NV2080_ENGINE_TYPE_NVJPEG6, classId(OBJNVJPG) , 6, NV_TRUE }, - { NV2080_ENGINE_TYPE_NVJPEG7, classId(OBJNVJPG) , 7, NV_TRUE }, - { NV2080_ENGINE_TYPE_OFA, classId(OBJOFA) , 0, NV_TRUE }, - { NV2080_ENGINE_TYPE_DPU, classId(OBJDPU) , 0, NV_FALSE }, - { NV2080_ENGINE_TYPE_PMU, classId(Pmu) , 0, NV_FALSE }, - { NV2080_ENGINE_TYPE_FBFLCN, classId(OBJFBFLCN) , 0, NV_FALSE }, - { NV2080_ENGINE_TYPE_HOST, classId(KernelFifo) , 0, NV_FALSE }, + { RM_ENGINE_TYPE_GR0, classId(Graphics) , 0, NV_TRUE }, + { RM_ENGINE_TYPE_GR1, classId(Graphics) , 1, NV_TRUE }, + { RM_ENGINE_TYPE_GR2, classId(Graphics) , 2, NV_TRUE }, + { RM_ENGINE_TYPE_GR3, classId(Graphics) , 3, NV_TRUE }, + { RM_ENGINE_TYPE_GR4, classId(Graphics) , 4, NV_TRUE }, + { RM_ENGINE_TYPE_GR5, classId(Graphics) , 5, NV_TRUE }, + { RM_ENGINE_TYPE_GR6, classId(Graphics) , 6, NV_TRUE }, + { RM_ENGINE_TYPE_GR7, classId(Graphics) , 7, NV_TRUE }, + { RM_ENGINE_TYPE_COPY0, classId(OBJCE) , 0, NV_TRUE }, + { RM_ENGINE_TYPE_COPY1, classId(OBJCE) , 1, NV_TRUE }, + { RM_ENGINE_TYPE_COPY2, classId(OBJCE) , 2, NV_TRUE }, + { RM_ENGINE_TYPE_COPY3, classId(OBJCE) , 3, NV_TRUE }, + { RM_ENGINE_TYPE_COPY4, classId(OBJCE) , 4, NV_TRUE }, + { RM_ENGINE_TYPE_COPY5, classId(OBJCE) , 5, NV_TRUE }, + { RM_ENGINE_TYPE_COPY6, classId(OBJCE) , 6, NV_TRUE }, + { RM_ENGINE_TYPE_COPY7, classId(OBJCE) , 7, NV_TRUE }, + { RM_ENGINE_TYPE_COPY8, classId(OBJCE) , 8, NV_TRUE }, + { RM_ENGINE_TYPE_COPY9, classId(OBJCE) , 9, NV_TRUE }, + { RM_ENGINE_TYPE_NVDEC0, classId(OBJBSP) , 0, NV_TRUE }, + { RM_ENGINE_TYPE_NVDEC1, classId(OBJBSP) , 1, NV_TRUE }, + { RM_ENGINE_TYPE_NVDEC2, classId(OBJBSP) , 2, NV_TRUE }, + { RM_ENGINE_TYPE_NVDEC3, classId(OBJBSP) , 3, NV_TRUE }, + { RM_ENGINE_TYPE_NVDEC4, classId(OBJBSP) , 4, NV_TRUE }, + { RM_ENGINE_TYPE_NVDEC5, classId(OBJBSP) , 5, NV_TRUE }, + { RM_ENGINE_TYPE_NVDEC6, classId(OBJBSP) , 6, NV_TRUE }, + { RM_ENGINE_TYPE_NVDEC7, classId(OBJBSP) , 7, NV_TRUE }, + { RM_ENGINE_TYPE_CIPHER, classId(OBJCIPHER) , 0, NV_TRUE }, + { RM_ENGINE_TYPE_NVENC0, classId(OBJMSENC) , 0, NV_TRUE }, + { RM_ENGINE_TYPE_NVENC1, classId(OBJMSENC) , 1, NV_TRUE }, + { RM_ENGINE_TYPE_NVENC2, classId(OBJMSENC) , 2, NV_TRUE }, + { RM_ENGINE_TYPE_SW, classId(OBJSWENG) , 0, NV_TRUE }, + { RM_ENGINE_TYPE_SEC2, classId(OBJSEC2) , 0, NV_TRUE }, + { RM_ENGINE_TYPE_NVJPEG0, classId(OBJNVJPG) , 0, NV_TRUE }, + { RM_ENGINE_TYPE_NVJPEG1, classId(OBJNVJPG) , 1, NV_TRUE }, + { RM_ENGINE_TYPE_NVJPEG2, classId(OBJNVJPG) , 2, NV_TRUE }, + { RM_ENGINE_TYPE_NVJPEG3, classId(OBJNVJPG) , 3, NV_TRUE }, + { RM_ENGINE_TYPE_NVJPEG4, classId(OBJNVJPG) , 4, NV_TRUE }, + { RM_ENGINE_TYPE_NVJPEG5, classId(OBJNVJPG) , 5, NV_TRUE }, + { RM_ENGINE_TYPE_NVJPEG6, classId(OBJNVJPG) , 6, NV_TRUE }, + { RM_ENGINE_TYPE_NVJPEG7, classId(OBJNVJPG) , 7, NV_TRUE }, + { RM_ENGINE_TYPE_OFA, classId(OBJOFA) , 0, NV_TRUE }, + { RM_ENGINE_TYPE_DPU, classId(OBJDPU) , 0, NV_FALSE }, + { RM_ENGINE_TYPE_PMU, classId(Pmu) , 0, NV_FALSE }, + { RM_ENGINE_TYPE_FBFLCN, classId(OBJFBFLCN) , 0, NV_FALSE }, + { RM_ENGINE_TYPE_HOST, classId(KernelFifo) , 0, NV_FALSE }, }; NV_STATUS gpuConstructEngineTable_IMPL @@ -3216,7 +3745,7 @@ NV_STATUS gpuConstructEngineTable_IMPL OBJGPU *pGpu ) { - NvU32 engineId = 0; + NvU32 engineIdx = 0; // Alloc engine DB pGpu->engineDB.bValid = NV_FALSE; @@ -3233,11 +3762,11 @@ NV_STATUS gpuConstructEngineTable_IMPL // of the engineDB // Initialize per-GPU per-engine list of non-stall interrupt event nodes. - for (engineId = 0; engineId < NV2080_ENGINE_TYPE_LAST; engineId++) + for (engineIdx = 0; engineIdx < (NvU32)RM_ENGINE_TYPE_LAST; engineIdx++) { - pGpu->engineNonstallIntr[engineId].pEventNode = NULL; - pGpu->engineNonstallIntr[engineId].pSpinlock = portSyncSpinlockCreate(portMemAllocatorGetGlobalNonPaged()); - if (pGpu->engineNonstallIntr[engineId].pSpinlock == NULL) + pGpu->engineNonstallIntr[engineIdx].pEventNode = NULL; + pGpu->engineNonstallIntr[engineIdx].pSpinlock = portSyncSpinlockCreate(portMemAllocatorGetGlobalNonPaged()); + if (pGpu->engineNonstallIntr[engineIdx].pSpinlock == NULL) return NV_ERR_INSUFFICIENT_RESOURCES; } @@ -3292,7 +3821,7 @@ NV_STATUS gpuUpdateEngineTable_IMPL } void gpuDestroyEngineTable_IMPL(OBJGPU *pGpu) { - NvU32 engineId = 0; + NvU32 engineIdx = 0; if (pGpu->engineDB.pType) { @@ -3302,13 +3831,13 @@ void gpuDestroyEngineTable_IMPL(OBJGPU *pGpu) pGpu->engineDB.bValid = NV_FALSE; } - for (engineId = 0; engineId < NV2080_ENGINE_TYPE_LAST; engineId++) + for (engineIdx = 0; engineIdx < (NvU32)RM_ENGINE_TYPE_LAST; engineIdx++) { - NV_ASSERT(pGpu->engineNonstallIntr[engineId].pEventNode == NULL); + NV_ASSERT(pGpu->engineNonstallIntr[engineIdx].pEventNode == NULL); - if (pGpu->engineNonstallIntr[engineId].pSpinlock != NULL) + if (pGpu->engineNonstallIntr[engineIdx].pSpinlock != NULL) { - portSyncSpinlockDestroy(pGpu->engineNonstallIntr[engineId].pSpinlock); + portSyncSpinlockDestroy(pGpu->engineNonstallIntr[engineIdx].pSpinlock); } } } @@ -3316,21 +3845,21 @@ void gpuDestroyEngineTable_IMPL(OBJGPU *pGpu) NvBool gpuCheckEngineTable_IMPL ( OBJGPU *pGpu, - NvU32 engType + RM_ENGINE_TYPE engType ) { - NvU32 engineId; + NvU32 engineIdx; if (!IS_MODS_AMODEL(pGpu)) { NV_ASSERT_OR_RETURN(pGpu->engineDB.bValid, NV_FALSE); } - NV_ASSERT_OR_RETURN(engType < NV2080_ENGINE_TYPE_LAST, NV_FALSE); + NV_ASSERT_OR_RETURN(engType < RM_ENGINE_TYPE_LAST, NV_FALSE); - for (engineId = 0; engineId < pGpu->engineDB.size; engineId++) + for (engineIdx = 0; engineIdx < pGpu->engineDB.size; engineIdx++) { - if (engType == pGpu->engineDB.pType[engineId]) + if (engType == pGpu->engineDB.pType[engineIdx]) { return NV_TRUE; } @@ -3343,7 +3872,7 @@ NV_STATUS gpuXlateClientEngineIdToEngDesc_IMPL ( OBJGPU *pGpu, - NvU32 clientEngineID, + RM_ENGINE_TYPE clientEngineID, ENGDESCRIPTOR *pEngDesc ) @@ -3367,7 +3896,7 @@ gpuXlateEngDescToClientEngineId_IMPL ( OBJGPU *pGpu, ENGDESCRIPTOR engDesc, - NvU32 *pClientEngineID + RM_ENGINE_TYPE *pClientEngineID ) { NvU32 counter; @@ -3388,7 +3917,7 @@ NV_STATUS gpuGetFlcnFromClientEngineId_IMPL ( OBJGPU *pGpu, - NvU32 clientEngineId, + RM_ENGINE_TYPE clientEngineId, Falcon **ppFlcn ) { @@ -3745,11 +4274,8 @@ void gpuDestroyGenericKernelFalconList_IMPL(OBJGPU *pGpu) NvU32 i; for (i = 0; i < NV_ARRAY_ELEMENTS(pGpu->genericKernelFalcons); i++) { - if (pGpu->genericKernelFalcons[i] != NULL) - { - objDelete(pGpu->genericKernelFalcons[i]); - pGpu->genericKernelFalcons[i] = NULL; - } + objDelete(pGpu->genericKernelFalcons[i]); + pGpu->genericKernelFalcons[i] = NULL; } pGpu->numGenericKernelFalcons = 0; } @@ -3812,17 +4338,19 @@ gpuFindChildPresent(const GPUCHILDPRESENT *pChildPresentList, NvU32 numChildPres } /*! - * @brief Sanity checks on given gfid + * @brief Get GFID State * * @param[in] pGpu OBJGPU pointer * @param[in] gfid GFID to be validated - * @param[in] bInUse NV_TRUE if GFID is being set for use + * @param[out] Current state of GFID */ NV_STATUS -gpuSanityCheckGfid_IMPL(OBJGPU *pGpu, NvU32 gfid, NvBool bInUse) +gpuGetGfidState(OBJGPU *pGpu, NvU32 gfid, GFID_ALLOC_STATUS *pState) { - // Error if pAllocatedGfids - if (pGpu->sriovState.pAllocatedGfids == NULL) + if (!gpuIsSriovEnabled(pGpu)) + return NV_OK; + + if (pGpu->sriovState.pAllocatedGfids == NULL || pState == NULL) { return NV_ERR_INVALID_ADDRESS; } @@ -3832,14 +4360,8 @@ gpuSanityCheckGfid_IMPL(OBJGPU *pGpu, NvU32 gfid, NvBool bInUse) { return NV_ERR_OUT_OF_RANGE; } - else if((bInUse == NV_TRUE) && (pGpu->sriovState.pAllocatedGfids[gfid] == GFID_ALLOCATED)) - { - return NV_ERR_IN_USE; - } - else if((bInUse == NV_FALSE) && (pGpu->sriovState.pAllocatedGfids[gfid] == GFID_FREE)) - { - return NV_ERR_INSUFFICIENT_RESOURCES; - } + + *pState = (GFID_ALLOC_STATUS)pGpu->sriovState.pAllocatedGfids[gfid]; return NV_OK; } @@ -3862,6 +4384,20 @@ gpuSetGfidUsage_IMPL(OBJGPU *pGpu, NvU32 gfid, NvBool bInUse) pGpu->sriovState.pAllocatedGfids[gfid] = GFID_FREE; } +/*! + * @brief Set pAllocatedGfids allocated status as being invalidated + * + * @param[in] pGpu OBJGPU pointer + * @param[in] gfid GFID to be set/unset (Assumes GFID is sanity checked before calling this function) + */ +void +gpuSetGfidInvalidated_IMPL(OBJGPU *pGpu, NvU32 gfid) +{ + NV_ASSERT_OR_RETURN_VOID(pGpu->sriovState.pAllocatedGfids != NULL); + + pGpu->sriovState.pAllocatedGfids[gfid] = GFID_INVALIDATED; +} + /** * @brief Iterates over the engine ordering list * @@ -4071,13 +4607,13 @@ gpuGetDmaEndAddress_IMPL(OBJGPU *pGpu) return dmaWindowStartAddr + (1ULL << numPhysAddrBits) - 1; } -void *gpuGetStaticInfo(OBJGPU *pGpu) +VGPU_STATIC_INFO *gpuGetStaticInfo(OBJGPU *pGpu) { return NULL; } -void *gpuGetGspStaticInfo(OBJGPU *pGpu) +GspStaticConfigInfo *gpuGetGspStaticInfo(OBJGPU *pGpu) { return &(GPU_GET_KERNEL_GSP(pGpu)->gspStaticInfo); } diff --git a/src/nvidia/src/kernel/gpu/gpu_engine_type.c b/src/nvidia/src/kernel/gpu/gpu_engine_type.c new file mode 100644 index 000000000..663766543 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/gpu_engine_type.c @@ -0,0 +1,280 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * @file + * @brief ENGINE_TYPE controls + */ + + +#include "kernel/gpu/gpu.h" +#include "kernel/gpu/nvbitmask.h" + +ct_assert(RM_ENGINE_TYPE_LAST == NV2080_ENGINE_TYPE_LAST); + +/*! + * @brief Convert NV2080 engine type to Rm internal engine type + * + * Rm internally uses RM engine type instead of NV2080 engine types. + * Some clients, like VGPU and CUDA, need have the cross-branch compatibility, we need to keep + * NV2080_ENGINE_TYPE consistent. When we add new ENGINE TYPEs, especially to increase the engine + * number on an existing ENGINE groups, we can not insert number in the middle. It will change the number + * of the rest of NV2080_ENGINE_TYPEs. But RM need to group the same type of ENGINE_TYPE together. + * So the solution is the separate RM and NV2080 engine types. When ENGINE_TYPE cross RM boundary, + * through control calls or RPC calls, we will need to convert the engine types. + * + * @param[in] index NV2080_ENGINE_TYPE number + * + * @returns RM_ENGINE_TYPE number + * RM_ENGINE_TYPE_LAST if the index is invalid + */ +RM_ENGINE_TYPE gpuGetRmEngineType_IMPL(NvU32 index) +{ + NV_ASSERT_OR_RETURN(index < NV2080_ENGINE_TYPE_LAST, RM_ENGINE_TYPE_LAST); + + switch (index) + { + case NV2080_ENGINE_TYPE_NULL: return RM_ENGINE_TYPE_NULL; + case NV2080_ENGINE_TYPE_GR0: return RM_ENGINE_TYPE_GR0; + case NV2080_ENGINE_TYPE_GR1: return RM_ENGINE_TYPE_GR1; + case NV2080_ENGINE_TYPE_GR2: return RM_ENGINE_TYPE_GR2; + case NV2080_ENGINE_TYPE_GR3: return RM_ENGINE_TYPE_GR3; + case NV2080_ENGINE_TYPE_GR4: return RM_ENGINE_TYPE_GR4; + case NV2080_ENGINE_TYPE_GR5: return RM_ENGINE_TYPE_GR5; + case NV2080_ENGINE_TYPE_GR6: return RM_ENGINE_TYPE_GR6; + case NV2080_ENGINE_TYPE_GR7: return RM_ENGINE_TYPE_GR7; + case NV2080_ENGINE_TYPE_COPY0: return RM_ENGINE_TYPE_COPY0; + case NV2080_ENGINE_TYPE_COPY1: return RM_ENGINE_TYPE_COPY1; + case NV2080_ENGINE_TYPE_COPY2: return RM_ENGINE_TYPE_COPY2; + case NV2080_ENGINE_TYPE_COPY3: return RM_ENGINE_TYPE_COPY3; + case NV2080_ENGINE_TYPE_COPY4: return RM_ENGINE_TYPE_COPY4; + case NV2080_ENGINE_TYPE_COPY5: return RM_ENGINE_TYPE_COPY5; + case NV2080_ENGINE_TYPE_COPY6: return RM_ENGINE_TYPE_COPY6; + case NV2080_ENGINE_TYPE_COPY7: return RM_ENGINE_TYPE_COPY7; + case NV2080_ENGINE_TYPE_COPY8: return RM_ENGINE_TYPE_COPY8; + case NV2080_ENGINE_TYPE_COPY9: return RM_ENGINE_TYPE_COPY9; + case NV2080_ENGINE_TYPE_NVDEC0: return RM_ENGINE_TYPE_NVDEC0; + case NV2080_ENGINE_TYPE_NVDEC1: return RM_ENGINE_TYPE_NVDEC1; + case NV2080_ENGINE_TYPE_NVDEC2: return RM_ENGINE_TYPE_NVDEC2; + case NV2080_ENGINE_TYPE_NVDEC3: return RM_ENGINE_TYPE_NVDEC3; + case NV2080_ENGINE_TYPE_NVDEC4: return RM_ENGINE_TYPE_NVDEC4; + case NV2080_ENGINE_TYPE_NVDEC5: return RM_ENGINE_TYPE_NVDEC5; + case NV2080_ENGINE_TYPE_NVDEC6: return RM_ENGINE_TYPE_NVDEC6; + case NV2080_ENGINE_TYPE_NVDEC7: return RM_ENGINE_TYPE_NVDEC7; + case NV2080_ENGINE_TYPE_NVENC0: return RM_ENGINE_TYPE_NVENC0; + case NV2080_ENGINE_TYPE_NVENC1: return RM_ENGINE_TYPE_NVENC1; + case NV2080_ENGINE_TYPE_NVENC2: return RM_ENGINE_TYPE_NVENC2; + case NV2080_ENGINE_TYPE_VP: return RM_ENGINE_TYPE_VP; + case NV2080_ENGINE_TYPE_ME: return RM_ENGINE_TYPE_ME; + case NV2080_ENGINE_TYPE_PPP: return RM_ENGINE_TYPE_PPP; + case NV2080_ENGINE_TYPE_MPEG: return RM_ENGINE_TYPE_MPEG; + case NV2080_ENGINE_TYPE_SW: return RM_ENGINE_TYPE_SW; + case NV2080_ENGINE_TYPE_TSEC: return RM_ENGINE_TYPE_TSEC; + case NV2080_ENGINE_TYPE_VIC: return RM_ENGINE_TYPE_VIC; + case NV2080_ENGINE_TYPE_MP: return RM_ENGINE_TYPE_MP; + case NV2080_ENGINE_TYPE_SEC2: return RM_ENGINE_TYPE_SEC2; + case NV2080_ENGINE_TYPE_HOST: return RM_ENGINE_TYPE_HOST; + case NV2080_ENGINE_TYPE_DPU: return RM_ENGINE_TYPE_DPU; + case NV2080_ENGINE_TYPE_PMU: return RM_ENGINE_TYPE_PMU; + case NV2080_ENGINE_TYPE_FBFLCN: return RM_ENGINE_TYPE_FBFLCN; + case NV2080_ENGINE_TYPE_NVJPEG0: return RM_ENGINE_TYPE_NVJPEG0; + case NV2080_ENGINE_TYPE_NVJPEG1: return RM_ENGINE_TYPE_NVJPEG1; + case NV2080_ENGINE_TYPE_NVJPEG2: return RM_ENGINE_TYPE_NVJPEG2; + case NV2080_ENGINE_TYPE_NVJPEG3: return RM_ENGINE_TYPE_NVJPEG3; + case NV2080_ENGINE_TYPE_NVJPEG4: return RM_ENGINE_TYPE_NVJPEG4; + case NV2080_ENGINE_TYPE_NVJPEG5: return RM_ENGINE_TYPE_NVJPEG5; + case NV2080_ENGINE_TYPE_NVJPEG6: return RM_ENGINE_TYPE_NVJPEG6; + case NV2080_ENGINE_TYPE_NVJPEG7: return RM_ENGINE_TYPE_NVJPEG7; + case NV2080_ENGINE_TYPE_OFA: return RM_ENGINE_TYPE_OFA; + default: break; + } + + return RM_ENGINE_TYPE_NULL; +} + +/*! + * @brief Convert RM engine type to NV2080 engine type + * + * Refer to the comments of gpuGetRmEngineType_IMPL + * + * @param[in] index RM_ENGINE_TYPE number + * + * @returns NV2080_ENGINE_TYPE number + * NV2080_ENGINE_TYPE_LAST if the index is invalid + */ +NvU32 gpuGetNv2080EngineType_IMPL(RM_ENGINE_TYPE index) +{ + NV_ASSERT_OR_RETURN(index < RM_ENGINE_TYPE_LAST, NV2080_ENGINE_TYPE_LAST); + + switch (index) + { + case RM_ENGINE_TYPE_NULL: return NV2080_ENGINE_TYPE_NULL; + case RM_ENGINE_TYPE_GR0: return NV2080_ENGINE_TYPE_GR0; + case RM_ENGINE_TYPE_GR1: return NV2080_ENGINE_TYPE_GR1; + case RM_ENGINE_TYPE_GR2: return NV2080_ENGINE_TYPE_GR2; + case RM_ENGINE_TYPE_GR3: return NV2080_ENGINE_TYPE_GR3; + case RM_ENGINE_TYPE_GR4: return NV2080_ENGINE_TYPE_GR4; + case RM_ENGINE_TYPE_GR5: return NV2080_ENGINE_TYPE_GR5; + case RM_ENGINE_TYPE_GR6: return NV2080_ENGINE_TYPE_GR6; + case RM_ENGINE_TYPE_GR7: return NV2080_ENGINE_TYPE_GR7; + case RM_ENGINE_TYPE_COPY0: return NV2080_ENGINE_TYPE_COPY0; + case RM_ENGINE_TYPE_COPY1: return NV2080_ENGINE_TYPE_COPY1; + case RM_ENGINE_TYPE_COPY2: return NV2080_ENGINE_TYPE_COPY2; + case RM_ENGINE_TYPE_COPY3: return NV2080_ENGINE_TYPE_COPY3; + case RM_ENGINE_TYPE_COPY4: return NV2080_ENGINE_TYPE_COPY4; + case RM_ENGINE_TYPE_COPY5: return NV2080_ENGINE_TYPE_COPY5; + case RM_ENGINE_TYPE_COPY6: return NV2080_ENGINE_TYPE_COPY6; + case RM_ENGINE_TYPE_COPY7: return NV2080_ENGINE_TYPE_COPY7; + case RM_ENGINE_TYPE_COPY8: return NV2080_ENGINE_TYPE_COPY8; + case RM_ENGINE_TYPE_COPY9: return NV2080_ENGINE_TYPE_COPY9; + case RM_ENGINE_TYPE_NVDEC0: return NV2080_ENGINE_TYPE_NVDEC0; + case RM_ENGINE_TYPE_NVDEC1: return NV2080_ENGINE_TYPE_NVDEC1; + case RM_ENGINE_TYPE_NVDEC2: return NV2080_ENGINE_TYPE_NVDEC2; + case RM_ENGINE_TYPE_NVDEC3: return NV2080_ENGINE_TYPE_NVDEC3; + case RM_ENGINE_TYPE_NVDEC4: return NV2080_ENGINE_TYPE_NVDEC4; + case RM_ENGINE_TYPE_NVDEC5: return NV2080_ENGINE_TYPE_NVDEC5; + case RM_ENGINE_TYPE_NVDEC6: return NV2080_ENGINE_TYPE_NVDEC6; + case RM_ENGINE_TYPE_NVDEC7: return NV2080_ENGINE_TYPE_NVDEC7; + case RM_ENGINE_TYPE_NVENC0: return NV2080_ENGINE_TYPE_NVENC0; + case RM_ENGINE_TYPE_NVENC1: return NV2080_ENGINE_TYPE_NVENC1; + case RM_ENGINE_TYPE_NVENC2: return NV2080_ENGINE_TYPE_NVENC2; + case RM_ENGINE_TYPE_VP: return NV2080_ENGINE_TYPE_VP; + case RM_ENGINE_TYPE_ME: return NV2080_ENGINE_TYPE_ME; + case RM_ENGINE_TYPE_PPP: return NV2080_ENGINE_TYPE_PPP; + case RM_ENGINE_TYPE_MPEG: return NV2080_ENGINE_TYPE_MPEG; + case RM_ENGINE_TYPE_SW: return NV2080_ENGINE_TYPE_SW; + case RM_ENGINE_TYPE_TSEC: return NV2080_ENGINE_TYPE_TSEC; + case RM_ENGINE_TYPE_VIC: return NV2080_ENGINE_TYPE_VIC; + case RM_ENGINE_TYPE_MP: return NV2080_ENGINE_TYPE_MP; + case RM_ENGINE_TYPE_SEC2: return NV2080_ENGINE_TYPE_SEC2; + case RM_ENGINE_TYPE_HOST: return NV2080_ENGINE_TYPE_HOST; + case RM_ENGINE_TYPE_DPU: return NV2080_ENGINE_TYPE_DPU; + case RM_ENGINE_TYPE_PMU: return NV2080_ENGINE_TYPE_PMU; + case RM_ENGINE_TYPE_FBFLCN: return NV2080_ENGINE_TYPE_FBFLCN; + case RM_ENGINE_TYPE_NVJPEG0: return NV2080_ENGINE_TYPE_NVJPEG0; + case RM_ENGINE_TYPE_NVJPEG1: return NV2080_ENGINE_TYPE_NVJPEG1; + case RM_ENGINE_TYPE_NVJPEG2: return NV2080_ENGINE_TYPE_NVJPEG2; + case RM_ENGINE_TYPE_NVJPEG3: return NV2080_ENGINE_TYPE_NVJPEG3; + case RM_ENGINE_TYPE_NVJPEG4: return NV2080_ENGINE_TYPE_NVJPEG4; + case RM_ENGINE_TYPE_NVJPEG5: return NV2080_ENGINE_TYPE_NVJPEG5; + case RM_ENGINE_TYPE_NVJPEG6: return NV2080_ENGINE_TYPE_NVJPEG6; + case RM_ENGINE_TYPE_NVJPEG7: return NV2080_ENGINE_TYPE_NVJPEG7; + case RM_ENGINE_TYPE_OFA: return NV2080_ENGINE_TYPE_OFA; + default: break; + } + + return NV2080_ENGINE_TYPE_NULL; +} + +/*! + * @brief Convert a list of RM engine type to a list of NV2080 engine type + * + * Refer to the comments of gpuGetRmEngineType_IMPL + * + * @param[in] pRmEngineList A list in order of RM_ENGINE_TYPE + * @param[in] engineCount Engine numbers + * @param[out] pNv2080EngineList Output list in order of NV2080_ENGINE_TYPE + * + * @returns void + */ +void gpuGetNv2080EngineTypeList_IMPL +( + RM_ENGINE_TYPE *pRmEngineList, + NvU32 engineCount, + NvU32 *pNv2080EngineList +) +{ + NV_ASSERT_OR_RETURN_VOID(engineCount < RM_ENGINE_TYPE_LAST); + + NvU32 i; + for (i = 0; i < engineCount; i++) + { + pNv2080EngineList[i] = gpuGetNv2080EngineType(pRmEngineList[i]); + } +} + +/*! + * @brief Convert a list NV2080 engine type of to a list of RM engine type + * + * @param[in] pNv2080EngineList A list in order of NV2080_ENGINE_TYPE + * @param[in] engineCount Engine numbers + * @param[out] pRmEngineList Output list in order of RM_ENGINE_TYPE + * + * @returns void + */ +void gpuGetRmEngineTypeList_IMPL +( + NvU32 *pNv2080EngineList, + NvU32 engineCount, + RM_ENGINE_TYPE *pRmEngineList +) +{ + NV_ASSERT_OR_RETURN_VOID(engineCount < RM_ENGINE_TYPE_LAST); + + NvU32 i; + for (i = 0; i < engineCount; i++) + { + pRmEngineList[i] = gpuGetRmEngineType(pNv2080EngineList[i]); + } +} + +/*! + * @brief Convert a capability mask of NV2080 engine type to the RM engine type capability mask. + * + * Refer to the comments of gpuGetRmEngineType_IMPL + * + * @param[in] pNV2080EngineTypeCap NV2080 engine type capability mask + * @param[in] capSize Cap size in dword + * @param[out] pRmEngineTypeCap RM engine type capability mask + * + * @returns NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +NV_STATUS gpuGetRmEngineTypeCapMask_IMPL +( + NvU32 *pNV2080EngineTypeCap, + NvU32 capSize, + NvU32 *pRmEngineTypeCap +) +{ + NvU32 i; + + NV_ASSERT_OR_RETURN(capSize == NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pRmEngineTypeCap != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pNV2080EngineTypeCap != NULL, NV_ERR_INVALID_ARGUMENT); + + for (i = 0; i < capSize; i++) + { + pRmEngineTypeCap[i] = 0; + } + + for (i = 0; i < NV2080_ENGINE_TYPE_LAST; i++) + { + if (NVGPU_GET_ENGINE_CAPS_MASK(pNV2080EngineTypeCap, i)) + { + NVGPU_SET_ENGINE_CAPS_MASK(pRmEngineTypeCap, gpuGetRmEngineType(i)); + } + } + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/gpu_fabric_probe.c b/src/nvidia/src/kernel/gpu/gpu_fabric_probe.c new file mode 100644 index 000000000..f509a5466 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/gpu_fabric_probe.c @@ -0,0 +1,824 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * @file + * @brief GPU Fabric Probe handling + */ + + +#include "gpu/gpu.h" +#include "os/os.h" +#include "objtmr.h" +#include "utils/nvprintf.h" +#include "kernel/gpu/nvlink/kernel_nvlink.h" +#include "ctrl/ctrl2080/ctrl2080pmgr.h" +#include "gpu/gpu_fabric_probe.h" +#include "compute/fabric.h" +#include "nvlink_inband_msg.h" +#include "kernel/mem_mgr/fabric_vaspace.h" + +// Structure to hold gpu probe information +typedef struct GPU_FABRIC_PROBE_INFO +{ + NvU64 probeRetryDelay; + NvBool bProbeRespRcvd; + NvU64 numProbes; + + OBJGPU *pGpu; + + TMR_EVENT *pTmrEvent; + + NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS sendDataParams; + nvlink_inband_gpu_probe_rsp_msg_t probeResponseMsg; + +} GPU_FABRIC_PROBE_INFO; + + +static NV_STATUS +_gpuFabricProbeFullSanityCheck +( + GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo +) +{ + if (pGpuFabricProbeInfo == NULL) + { + return NV_ERR_NOT_SUPPORTED; + } + + LOCK_ASSERT_AND_RETURN(rmDeviceGpuLockIsOwner( + gpuGetInstance(pGpuFabricProbeInfo->pGpu))); + + if (!gpuFabricProbeIsReceived(pGpuFabricProbeInfo)) + { + return NV_ERR_NOT_READY; + } + + if (!gpuFabricProbeIsSuccess(pGpuFabricProbeInfo)) + { + return pGpuFabricProbeInfo->probeResponseMsg.msgHdr.status; + } + + return NV_OK; +} + +NV_STATUS +gpuFabricProbeGetGpuFabricHandle +( + GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo, + NvU64 *pHandle +) +{ + NV_STATUS status; + + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfo); + + NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); + + *pHandle = pGpuFabricProbeInfo->probeResponseMsg.probeRsp.gpuHandle; + + return status; +} + +NV_STATUS +gpuFabricProbeGetGfId +( + GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo, + NvU32 *pGfId +) +{ + NV_STATUS status; + + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfo); + + NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); + + *pGfId = pGpuFabricProbeInfo->probeResponseMsg.probeRsp.gfId; + + return status; +} + +NV_STATUS +gpuFabricProbeGetfmCaps +( + GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo, + NvU64 *pFmCaps +) +{ + NV_STATUS status; + + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfo); + + NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); + + *pFmCaps = pGpuFabricProbeInfo->probeResponseMsg.probeRsp.fmCaps; + + return status; +} + +NV_STATUS +gpuFabricProbeGetClusterUuid +( + GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo, + NvUuid *pClusterUuid +) +{ + NV_STATUS status; + + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfo); + + NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); + + portMemCopy(&pClusterUuid->uuid[0], + sizeof(pClusterUuid->uuid), + &pGpuFabricProbeInfo->probeResponseMsg.probeRsp.clusterUuid.uuid[0], + sizeof(pGpuFabricProbeInfo->probeResponseMsg.probeRsp.clusterUuid.uuid)); + + return status; +} + +NV_STATUS +gpuFabricProbeGetFabricPartitionId +( + GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo, + NvU16 *pFabricPartitionId +) +{ + NV_STATUS status; + + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfo); + + NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); + + *pFabricPartitionId = pGpuFabricProbeInfo->probeResponseMsg.probeRsp.fabricPartitionId; + + return status; +} + +NV_STATUS +gpuFabricProbeGetGpaAddress +( + GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo, + NvU64 *pGpaAddress +) +{ + NV_STATUS status; + + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfo); + + NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); + + *pGpaAddress = pGpuFabricProbeInfo->probeResponseMsg.probeRsp.gpaAddress; + + return status; +} + +NV_STATUS +gpuFabricProbeGetGpaAddressRange +( + GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo, + NvU64 *pGpaAddressRange +) +{ + NV_STATUS status; + + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfo); + + NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); + + *pGpaAddressRange = pGpuFabricProbeInfo->probeResponseMsg.probeRsp.gpaAddressRange; + + return status; +} + +NV_STATUS +gpuFabricProbeGetFlaAddress +( + GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo, + NvU64 *pFlaAddress +) +{ + NV_STATUS status; + + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfo); + + NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); + + *pFlaAddress = pGpuFabricProbeInfo->probeResponseMsg.probeRsp.flaAddress; + + return status; +} + +NV_STATUS +gpuFabricProbeGetFlaAddressRange +( + GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo, + NvU64 *pFlaAddressRange +) +{ + NV_STATUS status; + + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfo); + + NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); + + *pFlaAddressRange = pGpuFabricProbeInfo->probeResponseMsg.probeRsp.flaAddressRange; + + return status; +} + +NV_STATUS +gpuFabricProbeGetNumProbeReqs +( + GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo, + NvU64 *numProbes +) +{ + if (pGpuFabricProbeInfo == NULL) + { + return NV_ERR_NOT_SUPPORTED; + } + + LOCK_ASSERT_AND_RETURN(rmDeviceGpuLockIsOwner( + gpuGetInstance(pGpuFabricProbeInfo->pGpu))); + + *numProbes = pGpuFabricProbeInfo->numProbes; + + return NV_OK; +} + +NvBool +gpuFabricProbeIsReceived +( + GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo +) +{ + if (pGpuFabricProbeInfo == NULL) + { + return NV_FALSE; + } + + LOCK_ASSERT_AND_RETURN_BOOL(rmDeviceGpuLockIsOwner( + gpuGetInstance(pGpuFabricProbeInfo->pGpu)), + NV_FALSE); + + return pGpuFabricProbeInfo->bProbeRespRcvd; +} + +NvBool +gpuFabricProbeIsSuccess +( + GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo +) +{ + nvlink_inband_gpu_probe_rsp_msg_t *pProbeResponseMsg; + nvlink_inband_msg_header_t *pProbeRespMsgHdr; + + if (pGpuFabricProbeInfo == NULL) + { + return NV_FALSE; + } + + LOCK_ASSERT_AND_RETURN_BOOL(rmDeviceGpuLockIsOwner(gpuGetInstance( + pGpuFabricProbeInfo->pGpu)), + NV_FALSE); + + pProbeResponseMsg = &pGpuFabricProbeInfo->probeResponseMsg; + pProbeRespMsgHdr = &pProbeResponseMsg->msgHdr; + + return pProbeRespMsgHdr->status == NV_OK; +} + +NV_STATUS +gpuFabricProbeGetFmStatus +( + GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo +) +{ + if (pGpuFabricProbeInfo == NULL) + { + return NV_ERR_NOT_SUPPORTED; + } + + LOCK_ASSERT_AND_RETURN(rmDeviceGpuLockIsOwner( + gpuGetInstance(pGpuFabricProbeInfo->pGpu))); + + return pGpuFabricProbeInfo->probeResponseMsg.msgHdr.status; +} + +static void +_gpuFabricProbeForceCompletionError +( + GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo, + NV_STATUS status +) +{ + NV_ASSERT(!pGpuFabricProbeInfo->bProbeRespRcvd); + pGpuFabricProbeInfo->bProbeRespRcvd = NV_TRUE; + pGpuFabricProbeInfo->probeResponseMsg.msgHdr.status = status; +} + +static NV_STATUS +_gpuFabricProbeSchedule +( + GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo +) +{ + NV_STATUS status; + OBJGPU *pGpu = pGpuFabricProbeInfo->pGpu; + OBJTMR *pTmr = GPU_GET_TIMER(pGpu); + + NV_ASSERT(pGpuFabricProbeInfo->pTmrEvent != NULL); + + status = tmrEventScheduleRel(pTmr, pGpuFabricProbeInfo->pTmrEvent, + pGpuFabricProbeInfo->probeRetryDelay); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "GPU (ID: %d) tmrEventScheduleRel failed\n", + gpuGetInstance(pGpu)); + return status; + } + + pGpuFabricProbeInfo->numProbes++; + + if ((pGpuFabricProbeInfo->numProbes % + pGpu->fabricProbeSlowdownThreshold) == 0) + { + pGpuFabricProbeInfo->probeRetryDelay += pGpuFabricProbeInfo->probeRetryDelay; + } + + NV_PRINTF(LEVEL_INFO, "GPU (ID: %d) Num retried probes %lld \n", + gpuGetInstance(pGpu), pGpuFabricProbeInfo->numProbes); + + return NV_OK; +} + +static NV_STATUS +_gpuFabricProbeConstructReq +( + nvlink_inband_gpu_probe_req_t *pProbeReq, + OBJGPU *pGpu +) +{ + NV_STATUS status; + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + NvU8 *pUuid; + NvU32 uuidLength, flags = 0; + + portMemSet(pProbeReq, 0, sizeof(*pProbeReq)); + + flags = FLD_SET_DRF_NUM(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _TYPE, + NV2080_GPU_CMD_GPU_GET_GID_FLAGS_TYPE_SHA1, flags); + flags = FLD_SET_DRF_NUM(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _FORMAT, + NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_BINARY, flags); + status = gpuGetGidInfo(pGpu, &pUuid, &uuidLength, flags); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "GPU (ID: %d) Failed to update GPU UUID\n", + gpuGetInstance(pGpu)); + return status; + } + portMemCopy(&pProbeReq->gpuUuid.uuid[0], uuidLength, pUuid, uuidLength); + portMemFree(pUuid); + + pProbeReq->pciInfo = gpuGetDBDF(pGpu); + pProbeReq->moduleId = pGpu->moduleId; + pProbeReq->discoveredLinkMask = pKernelNvlink->discoveredLinks; + pProbeReq->enabledLinkMask = pKernelNvlink->enabledLinks; + pProbeReq->gpuCapMask = (IS_VIRTUAL_WITH_SRIOV(pGpu)) ? + NVLINK_INBAND_GPU_PROBE_CAPS_SRIOV_ENABLED : 0; + return status; +} + +static NV_STATUS +_gpuFabricProbeSend +( + OBJGPU *pGpu, + OBJTMR *pTmr, + TMR_EVENT *pEvent +) +{ + NV_STATUS status; + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo = + (GPU_FABRIC_PROBE_INFO *)pEvent->pUserData; + + if (pKernelNvlink->bIsGpuDegraded || + (pKernelNvlink->discoveredLinks == 0)) + { + NV_PRINTF(LEVEL_ERROR, + "GPU (ID: %d) Degraded. Not sending probe\n", + gpuGetInstance(pGpu)); + _gpuFabricProbeForceCompletionError(pGpuFabricProbeInfo, NV_ERR_NOT_SUPPORTED); + return NV_ERR_NOT_SUPPORTED; + } + + if (pGpuFabricProbeInfo->bProbeRespRcvd) + { + NV_PRINTF(LEVEL_INFO, + "GPU (ID: %d) Probe Resp rcvd. Not sending probe\n", + gpuGetInstance(pGpu)); + return NV_OK; + } + + status = knvlinkSendInbandData(pGpu, + pKernelNvlink, + &pGpuFabricProbeInfo->sendDataParams); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "GPU (ID: %d) Send Inband data failed\n", + gpuGetInstance(pGpu)); + // + // Deliberately ignoring return value as we want probes to be + // retried until success + // + } + + status = _gpuFabricProbeSchedule(pGpuFabricProbeInfo); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "GPU (ID: %d) Schedule Probe failed\n", + gpuGetInstance(pGpu)); + _gpuFabricProbeForceCompletionError(pGpuFabricProbeInfo, NV_ERR_OPERATING_SYSTEM); + return status; + } + + return status; +} + + +static void +_gpuFabricProbeSetupGpaRange +( + OBJGPU *pGpu, + GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo +) +{ + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + // setup GPA based system + if (pKernelNvlink != NULL) + { + NvU64 gpaAddress; + NvU64 gpaAddressSize; + + NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, + gpuFabricProbeGetGpaAddress(pGpuFabricProbeInfo, + &gpaAddress) == NV_OK); + + NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, + gpuFabricProbeGetGpaAddressRange(pGpuFabricProbeInfo, + &gpaAddressSize) == NV_OK); + + //pKernelNvlink->fabricBaseAddr = gpaAddress; + NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, + knvlinkSetUniqueFabricBaseAddress_HAL(pGpu, + pKernelNvlink, + gpaAddress) == NV_OK); + } +} + +static void +_gpuFabricProbeSetupFlaRange +( + OBJGPU *pGpu, + GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo +) +{ + if (pGpu->pFabricVAS != NULL) + { + NvU64 flaBaseAddress; + NvU64 flaSize; + + NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, + gpuFabricProbeGetFlaAddress(pGpuFabricProbeInfo, &flaBaseAddress) == NV_OK); + + NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, + gpuFabricProbeGetFlaAddressRange(pGpuFabricProbeInfo, &flaSize) == NV_OK); + + NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, + fabricvaspaceInitUCRange(dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE), + pGpu, flaBaseAddress, flaSize) == NV_OK); + } +} + +void +_gpuFabricProbeReceive +( + OBJGPU *pGpu, + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pInbandRcvParams +) +{ + nvlink_inband_gpu_probe_rsp_msg_t *pProbeRespMsg; + GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo; + nvlink_inband_gpu_probe_req_msg_t *pProbeReqMsg = NULL; + NvU8 *pRsvd = NULL; + OBJSYS *pSys = SYS_GET_INSTANCE(); + + NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); + + NV_ASSERT(pInbandRcvParams != NULL); + + pGpuFabricProbeInfo = pGpu->pGpuFabricProbeInfo; + + pProbeReqMsg = (nvlink_inband_gpu_probe_req_msg_t *)&pGpuFabricProbeInfo-> + sendDataParams.buffer[0]; + pProbeRespMsg = (nvlink_inband_gpu_probe_rsp_msg_t *)&pInbandRcvParams->data[0]; + + if (pProbeRespMsg->msgHdr.requestId != pProbeReqMsg->msgHdr.requestId) + { + NV_PRINTF(LEVEL_INFO, + "GPU (ID: %d) Probe resp invalid reqId %lld respId %lld\n", + gpuGetInstance(pGpu), + pProbeReqMsg->msgHdr.requestId, + pProbeRespMsg->msgHdr.requestId); + return; + } + + // Assert reserved in probeResponse are zero + pRsvd = &pProbeRespMsg->probeRsp.reserved[0]; + NV_ASSERT((pRsvd[0] == 0) && portMemCmp(pRsvd, pRsvd + 1, + sizeof(pProbeRespMsg->probeRsp.reserved) - 1) == 0); + + portMemCopy(&pGpuFabricProbeInfo->probeResponseMsg, + sizeof(pGpuFabricProbeInfo->probeResponseMsg), + pProbeRespMsg, + sizeof(*pProbeRespMsg)); + + // + // TODO - Add additional check with versioning to continue with the + // timer and send lower version requests + // + pGpuFabricProbeInfo->bProbeRespRcvd = NV_TRUE; + + NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, + _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfo) == NV_OK); + _gpuFabricProbeSetupGpaRange(pGpu, pGpuFabricProbeInfo); + _gpuFabricProbeSetupFlaRange(pGpu, pGpuFabricProbeInfo); + + // if MC FLA is disabled, reset the fmCaps + if (!pSys->bMulticastFlaEnabled) + { + pGpuFabricProbeInfo->probeResponseMsg.probeRsp.fmCaps &= + ~NVLINK_INBAND_FM_CAPS_MC_TEAM_SETUP_V1; + pGpuFabricProbeInfo->probeResponseMsg.probeRsp.fmCaps &= + ~NVLINK_INBAND_FM_CAPS_MC_TEAM_RELEASE_V1; + } +} + +void +gpuFabricProbeSuspend +( + GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo +) +{ + OBJGPU *pGpu; + OBJTMR *pTmr; + + if (pGpuFabricProbeInfo == NULL) + { + return; + } + + pGpu = pGpuFabricProbeInfo->pGpu; + + NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); + + pTmr = GPU_GET_TIMER(pGpu); + + NV_ASSERT(pGpuFabricProbeInfo->pTmrEvent != NULL); + + if (!gpuFabricProbeIsReceived(pGpuFabricProbeInfo)) + { + tmrEventCancel(pTmr, pGpuFabricProbeInfo->pTmrEvent); + } +} + +NV_STATUS +gpuFabricProbeResume +( + GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo +) +{ + OBJGPU *pGpu; + OBJTMR *pTmr; + NV_STATUS status = NV_OK; + + if (pGpuFabricProbeInfo == NULL) + { + return NV_ERR_NOT_SUPPORTED; + } + + pGpu = pGpuFabricProbeInfo->pGpu; + + NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); + + pTmr = GPU_GET_TIMER(pGpu); + + NV_ASSERT(pGpuFabricProbeInfo->pTmrEvent != NULL); + + if (!gpuFabricProbeIsReceived(pGpuFabricProbeInfo)) + { + status = _gpuFabricProbeSend(pGpu, pTmr, pGpuFabricProbeInfo->pTmrEvent); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "GPU (ID: %d) Resume and Sending probe request failed\n", + gpuGetInstance(pGpu)); + } + } + + return status; +} + +NV_STATUS +gpuFabricProbeStart +( + OBJGPU *pGpu, + GPU_FABRIC_PROBE_INFO **ppGpuFabricProbeInfo +) +{ + NV_STATUS status; + OBJTMR *pTmr = GPU_GET_TIMER(pGpu); + nvlink_inband_gpu_probe_req_msg_t *pProbeReqMsg = NULL; + GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo; + NVLINK_INBAND_MSG_CALLBACK inbandMsgCbParams; + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + + LOCK_ASSERT_AND_RETURN(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); + + // + // TODO - probe versioning + // After retrying the latest version probe for a few times, if GPU + // doesn't receive any response, GPU fallsback to the previous + // version of probe request. This process continues until it + // reaches the lowest possible probe request version + // + + // Check if NVSwitch based system. If not return without doing anything + if (!gpuFabricProbeIsSupported(pGpu)) + { + return NV_OK; + } + + *ppGpuFabricProbeInfo = portMemAllocNonPaged(sizeof(*pGpuFabricProbeInfo)); + NV_ASSERT_OR_RETURN(*ppGpuFabricProbeInfo != NULL, NV_ERR_NO_MEMORY); + + pGpuFabricProbeInfo = *ppGpuFabricProbeInfo; + + portMemSet(pGpuFabricProbeInfo, 0, sizeof(*pGpuFabricProbeInfo)); + + pGpuFabricProbeInfo->pGpu = pGpu; + + status = tmrEventCreate(pTmr, &pGpuFabricProbeInfo->pTmrEvent, + _gpuFabricProbeSend, pGpuFabricProbeInfo, + TMR_FLAGS_NONE); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "GPU (ID: %d) Timer create failure\n", + gpuGetInstance(pGpu)); + goto fail; + } + + pGpuFabricProbeInfo->probeRetryDelay = + pGpu->fabricProbeRetryDelay * GPU_FABRIC_PROBE_SEC_TO_NS; + + ct_assert(sizeof(nvlink_inband_gpu_probe_req_msg_t) <= + sizeof(pGpuFabricProbeInfo->sendDataParams.buffer)); + + pProbeReqMsg = (nvlink_inband_gpu_probe_req_msg_t *)&pGpuFabricProbeInfo-> + sendDataParams.buffer[0]; + + status = _gpuFabricProbeConstructReq(&pProbeReqMsg->probeReq, pGpu); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "GPU (ID: %d) Init Probe request failed\n", + gpuGetInstance(pGpu)); + goto fail; + } + + status = fabricInitInbandMsgHdr(&pProbeReqMsg->msgHdr, + NVLINK_INBAND_MSG_TYPE_GPU_PROBE_REQ, + sizeof(pProbeReqMsg->probeReq)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "GPU (ID: %d) Init of Inband msg hdr failed\n", + gpuGetInstance(pGpu)); + goto fail; + } + + pGpuFabricProbeInfo->sendDataParams.dataSize = sizeof(*pProbeReqMsg); + + // Register the receive callback + inbandMsgCbParams.messageType = NVLINK_INBAND_MSG_TYPE_GPU_PROBE_RSP; + inbandMsgCbParams.pCallback = _gpuFabricProbeReceive; + inbandMsgCbParams.wqItemFlags = (OS_QUEUE_WORKITEM_FLAGS_LOCK_SEMA | + OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW); + status = knvlinkRegisterInbandCallback(pGpu, + pKernelNvlink, + &inbandMsgCbParams); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "GPU (ID: %d) Registering Inband Cb failed\n", + gpuGetInstance(pGpu)); + goto fail; + } + + status = _gpuFabricProbeSend(pGpu, pTmr, pGpuFabricProbeInfo->pTmrEvent); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "GPU (ID: %d) Sending probe request failed\n", + gpuGetInstance(pGpu)); + goto fail; + } + + return NV_OK; + +fail: + if (pGpuFabricProbeInfo->pTmrEvent != NULL) + { + tmrEventDestroy(pTmr, pGpuFabricProbeInfo->pTmrEvent); + } + + portMemFree(pGpuFabricProbeInfo); + pGpu->pGpuFabricProbeInfo = NULL; + + return status; +} + +void +gpuFabricProbeStop +( + GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo +) +{ + OBJGPU *pGpu; + OBJTMR *pTmr; + KernelNvlink *pKernelNvlink; + + if (pGpuFabricProbeInfo == NULL) + { + return; + } + + pGpu = pGpuFabricProbeInfo->pGpu; + + NV_ASSERT_OR_RETURN_VOID(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); + + pTmr = GPU_GET_TIMER(pGpu); + pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + + NV_ASSERT(pKernelNvlink != NULL); + + // Unregister the receive callback + NV_ASSERT_OK(knvlinkUnregisterInbandCallback(pGpu, pKernelNvlink, + NVLINK_INBAND_MSG_TYPE_GPU_PROBE_RSP)); + + if (pGpuFabricProbeInfo->pTmrEvent != NULL) + { + tmrEventDestroy(pTmr, pGpuFabricProbeInfo->pTmrEvent); + } + + portMemFree(pGpuFabricProbeInfo); + + pGpu->pGpuFabricProbeInfo = NULL; +} + +NvBool +gpuFabricProbeIsSupported +( + OBJGPU *pGpu +) +{ + if (pGpu->fabricProbeRetryDelay == 0) + { + NV_PRINTF(LEVEL_INFO, "GPU (ID: %d) Probe handling is disabled\n", + gpuGetInstance(pGpu)); + return NV_FALSE; + } + + if (GPU_GET_KERNEL_NVLINK(pGpu) == NULL) + { + return NV_FALSE; + } + + return NV_TRUE; +} diff --git a/src/nvidia/src/kernel/gpu/gpu_gspclient.c b/src/nvidia/src/kernel/gpu/gpu_gspclient.c index d757b723b..bad647402 100644 --- a/src/nvidia/src/kernel/gpu/gpu_gspclient.c +++ b/src/nvidia/src/kernel/gpu/gpu_gspclient.c @@ -204,6 +204,12 @@ NvBool gpuIsGlobalPoisonFuseEnabled_FWCLIENT(OBJGPU *pGpu) return pGSCI->poisonFuseEnabled; } +void gpuInitProperties_FWCLIENT(OBJGPU *pGpu) +{ + GspStaticConfigInfo *pGSCI = GPU_GET_GSP_STATIC_INFO(pGpu); + pGpu->setProperty(pGpu, PDB_PROP_GPU_IS_MOBILE, pGSCI->bIsMobile); +} + /*! * @brief These functions are used on CPU RM when pGpu is a GSP client. * Data is fetched from GSP using subdeviceCtrlCmdInternalGetChipInfo and cached, diff --git a/src/nvidia/src/kernel/gpu/gpu_register_access_map.c b/src/nvidia/src/kernel/gpu/gpu_register_access_map.c index 2d8474597..d3bba1a52 100644 --- a/src/nvidia/src/kernel/gpu/gpu_register_access_map.c +++ b/src/nvidia/src/kernel/gpu/gpu_register_access_map.c @@ -28,6 +28,7 @@ #include "lib/base_utils.h" #include "lib/zlib/inflate.h" #include "nvRmReg.h" +#include "virtualization/hypervisor/hypervisor.h" /** * @brief Changes the user-space permissions for a given register address range @@ -173,6 +174,15 @@ gpuGetUserRegisterAccessPermissions_IMPL(OBJGPU *pGpu, NvU32 offset) static NvBool _getIsProfilingPrivileged(OBJGPU *pGpu) { + // On a vGPU Host, RmProfilingAdminOnly is always set to 1 + if (hypervisorIsVgxHyper()) + { + // + // Setting the value at this point to make the behavior same for + // debug/develop/release drivers on vGPU host. + // + return NV_TRUE; + } #if defined(DEBUG) || defined(DEVELOP) return NV_FALSE; #else diff --git a/src/nvidia/src/kernel/gpu/gpu_registry.c b/src/nvidia/src/kernel/gpu/gpu_registry.c index 26a42d825..616a76125 100644 --- a/src/nvidia/src/kernel/gpu/gpu_registry.c +++ b/src/nvidia/src/kernel/gpu/gpu_registry.c @@ -27,9 +27,15 @@ #include "gpu/gpu_timeout.h" #include "gpu/gpu_access.h" #include "core/thread_state.h" - +#include "nvdevid.h" #include "nvrm_registry.h" +#include "virtualization/hypervisor/hypervisor.h" + +#define __VGPU_SRIOV_ENABLED_SKUS__ +#include "g_vgpu_resman_specific.h" // isSriovEnabledSKU +#undef __VGPU_SRIOV_ENABLED_SKUS__ + static void _gpuInitGlobalSurfaceOverride(OBJGPU *pGpu); /*! @@ -99,6 +105,47 @@ gpuInitRegistryOverrides_KERNEL } } + if (pGpu->bSriovCapable) + { + if (osReadRegistryDword(pGpu, NV_REG_STR_RM_SET_SRIOV_MODE, &data32) == NV_OK) + { + NV_PRINTF(LEVEL_INFO, "Overriding SRIOV Mode to %u\n", + (data32 == NV_REG_STR_RM_SET_SRIOV_MODE_ENABLED)); + + pGpu->bSriovEnabled = (data32 == NV_REG_STR_RM_SET_SRIOV_MODE_ENABLED); + } + else + { + if (hypervisorIsVgxHyper() && !RMCFG_FEATURE_PLATFORM_GSP) + { + NvU32 devID = 0; + NvU32 ssID = 0; + + gpuReadDeviceId_HAL(pGpu, &devID, &ssID); + + devID = DRF_VAL(_PCI, _DEVID, _DEVICE, devID); + ssID = DRF_VAL(_PCI, _DEVID, _DEVICE, ssID); + + if (isSriovEnabledSKU(devID, ssID)) + { + pGpu->bSriovEnabled = NV_TRUE; + + // + // Set the registry key for GSP-RM to consume without having + // to evaluate hypervisor support + // + osWriteRegistryDword(pGpu, NV_REG_STR_RM_SET_SRIOV_MODE, + NV_REG_STR_RM_SET_SRIOV_MODE_ENABLED); + } + } + } + } + + if (pGpu->bSriovEnabled && (IS_GSP_CLIENT(pGpu) || RMCFG_FEATURE_PLATFORM_GSP)) + { + pGpu->bVgpuGspPluginOffloadEnabled = NV_TRUE; + } + if (osReadRegistryDword(pGpu, NV_REG_STR_RM_CLIENT_RM_ALLOCATED_CTX_BUFFER, &data32) == NV_OK) { pGpu->bClientRmAllocatedCtxBuffer = (data32 == NV_REG_STR_RM_CLIENT_RM_ALLOCATED_CTX_BUFFER_ENABLED); @@ -110,7 +157,7 @@ gpuInitRegistryOverrides_KERNEL { pGpu->bClientRmAllocatedCtxBuffer = NV_TRUE; } - else if ( NV_IS_MODS || !(pGpu->bSriovEnabled || IS_VIRTUAL(pGpu)) ) + else if ( RMCFG_FEATURE_MODS_FEATURES || !(pGpu->bSriovEnabled || IS_VIRTUAL(pGpu)) ) { // TODO : enable this feature on mods pGpu->bClientRmAllocatedCtxBuffer = NV_FALSE; diff --git a/src/nvidia/src/kernel/gpu/gpu_resource.c b/src/nvidia/src/kernel/gpu/gpu_resource.c index 577d4ba2c..2623be964 100644 --- a/src/nvidia/src/kernel/gpu/gpu_resource.c +++ b/src/nvidia/src/kernel/gpu/gpu_resource.c @@ -41,6 +41,7 @@ #include "gpu/device/device.h" #include "gpu/subdevice/subdevice.h" #include "gpu_mgr/gpu_mgr.h" +#include "virtualization/hypervisor/hypervisor.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" @@ -215,6 +216,11 @@ gpuresShareCallback_IMPL // case NV01_MEMORY_LOCAL_USER: case NV01_MEMORY_SYSTEM: + // + // We also exempt this check for cases when KernelHostVgpuDeviceApi(NVA084_KERNEL_HOST_VGPU_DEVICE) is being duped + // by plugins under every client it creates for itself or guest. + // + case NVA084_KERNEL_HOST_VGPU_DEVICE: return NV_TRUE; // // We exempt this check for cases when a kernel client is trying to dup AMPERE_SMC_PARTITION_REF object. @@ -224,14 +230,14 @@ gpuresShareCallback_IMPL { RmClient *pRmClient = dynamicCast(pInvokingClient, RmClient); RS_PRIV_LEVEL privLevel = RS_PRIV_LEVEL_USER; + NvBool bOverrideDupAllow = NV_FALSE; if (pRmClient != NULL) { privLevel = rmclientGetCachedPrivilege(pRmClient); } - if ((privLevel >= RS_PRIV_LEVEL_KERNEL) - ) + if ((privLevel >= RS_PRIV_LEVEL_KERNEL) || bOverrideDupAllow) return NV_TRUE; break; diff --git a/src/nvidia/src/kernel/gpu/gpu_rmapi.c b/src/nvidia/src/kernel/gpu/gpu_rmapi.c index 6a848c642..a5143fb33 100644 --- a/src/nvidia/src/kernel/gpu/gpu_rmapi.c +++ b/src/nvidia/src/kernel/gpu/gpu_rmapi.c @@ -36,6 +36,7 @@ #include "rmapi/client.h" #include "rmapi/resource_fwd_decls.h" #include "core/thread_state.h" +#include "virtualization/kernel_hostvgpudeviceapi.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "kernel/gpu/fifo/kernel_channel.h" @@ -310,8 +311,8 @@ _gpuFilterSubDeviceEventInfo MIG_INSTANCE_REF ref; NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice->pDevice); NvU32 engineIdx; - NvU32 engineType; - NvU32 localType; + RM_ENGINE_TYPE rmEngineType; + RM_ENGINE_TYPE localRmEngineType; NvU32 localIdx; NV_STATUS status = NV_OK; KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); @@ -361,107 +362,107 @@ _gpuFilterSubDeviceEventInfo if (ROBUST_CHANNEL_IS_CE_ERROR(*pInfo32)) { engineIdx = ROBUST_CHANNEL_CE_ERROR_IDX(*pInfo32); - engineType = NV2080_ENGINE_TYPE_COPY(engineIdx); + rmEngineType = RM_ENGINE_TYPE_COPY(engineIdx); - if (!kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, engineType, ref)) + if (!kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, rmEngineType, ref)) return NV_ERR_OBJECT_NOT_FOUND; NV_ASSERT_OK_OR_RETURN( kmigmgrGetGlobalToLocalEngineType(pGpu, pKernelMIGManager, ref, - engineType, - &localType)); - localIdx = NV2080_ENGINE_TYPE_COPY_IDX(localType); + rmEngineType, + &localRmEngineType)); + localIdx = RM_ENGINE_TYPE_COPY_IDX(localRmEngineType); *pInfo32 = ROBUST_CHANNEL_CE_ERROR(localIdx); } else if (ROBUST_CHANNEL_IS_NVDEC_ERROR(*pInfo32)) { engineIdx = ROBUST_CHANNEL_NVDEC_ERROR_IDX(*pInfo32); - engineType = NV2080_ENGINE_TYPE_NVDEC(engineIdx); + rmEngineType = RM_ENGINE_TYPE_NVDEC(engineIdx); - if (!kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, engineType, ref)) + if (!kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, rmEngineType, ref)) return NV_ERR_OBJECT_NOT_FOUND; NV_ASSERT_OK_OR_RETURN( kmigmgrGetGlobalToLocalEngineType(pGpu, pKernelMIGManager, ref, - engineType, - &localType)); - localIdx = NV2080_ENGINE_TYPE_NVDEC_IDX(localType); + rmEngineType, + &localRmEngineType)); + localIdx = RM_ENGINE_TYPE_NVDEC_IDX(localRmEngineType); *pInfo32 = ROBUST_CHANNEL_NVDEC_ERROR(localIdx); } else if (ROBUST_CHANNEL_IS_NVENC_ERROR(*pInfo32)) { engineIdx = ROBUST_CHANNEL_NVENC_ERROR_IDX(*pInfo32); - engineType = NV2080_ENGINE_TYPE_NVENC(engineIdx); + rmEngineType = RM_ENGINE_TYPE_NVENC(engineIdx); - if (!kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, engineType, ref)) + if (!kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, rmEngineType, ref)) return NV_ERR_OBJECT_NOT_FOUND; NV_ASSERT_OK_OR_RETURN( kmigmgrGetGlobalToLocalEngineType(pGpu, pKernelMIGManager, ref, - engineType, - &localType)); - localIdx = NV2080_ENGINE_TYPE_NVENC_IDX(localType); + rmEngineType, + &localRmEngineType)); + localIdx = RM_ENGINE_TYPE_NVENC_IDX(localRmEngineType); *pInfo32 = ROBUST_CHANNEL_NVENC_ERROR(localIdx); } } else if (NV2080_NOTIFIER_TYPE_IS_GR(*pNotifyType)) { engineIdx = NV2080_NOTIFIERS_GR_IDX(*pNotifyType); - engineType = NV2080_ENGINE_TYPE_GR(engineIdx); + rmEngineType = RM_ENGINE_TYPE_GR(engineIdx); - if (!kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, engineType, ref)) + if (!kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, rmEngineType, ref)) return NV_ERR_OBJECT_NOT_FOUND; NV_ASSERT_OK_OR_RETURN( kmigmgrGetGlobalToLocalEngineType(pGpu, pKernelMIGManager, ref, - engineType, - &localType)); - localIdx = NV2080_ENGINE_TYPE_GR_IDX(localType); + rmEngineType, + &localRmEngineType)); + localIdx = RM_ENGINE_TYPE_GR_IDX(localRmEngineType); *pNotifyType = NV2080_NOTIFIERS_GR(localIdx); } else if (NV2080_NOTIFIER_TYPE_IS_CE(*pNotifyType)) { engineIdx = NV2080_NOTIFIERS_CE_IDX(*pNotifyType); - engineType = NV2080_ENGINE_TYPE_COPY(engineIdx); + rmEngineType = RM_ENGINE_TYPE_COPY(engineIdx); - if (!kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, engineType, ref)) + if (!kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, rmEngineType, ref)) return NV_ERR_OBJECT_NOT_FOUND; NV_ASSERT_OK_OR_RETURN( kmigmgrGetGlobalToLocalEngineType(pGpu, pKernelMIGManager, ref, - engineType, - &localType)); - localIdx = NV2080_ENGINE_TYPE_COPY_IDX(localType); + rmEngineType, + &localRmEngineType)); + localIdx = RM_ENGINE_TYPE_COPY_IDX(localRmEngineType); *pNotifyType = NV2080_NOTIFIERS_CE(localIdx); } else if (NV2080_NOTIFIER_TYPE_IS_NVDEC(*pNotifyType)) { engineIdx = NV2080_NOTIFIERS_NVDEC_IDX(*pNotifyType); - engineType = NV2080_ENGINE_TYPE_NVDEC(engineIdx); + rmEngineType = RM_ENGINE_TYPE_NVDEC(engineIdx); - if (!kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, engineType, ref)) + if (!kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, rmEngineType, ref)) return NV_ERR_OBJECT_NOT_FOUND; NV_ASSERT_OK_OR_RETURN( kmigmgrGetGlobalToLocalEngineType(pGpu, pKernelMIGManager, ref, - engineType, - &localType)); - localIdx = NV2080_ENGINE_TYPE_NVDEC_IDX(localType); + rmEngineType, + &localRmEngineType)); + localIdx = RM_ENGINE_TYPE_NVDEC_IDX(localRmEngineType); *pNotifyType = NV2080_NOTIFIERS_NVDEC(localIdx); } else if (NV2080_NOTIFIER_TYPE_IS_NVENC(*pNotifyType)) { engineIdx = NV2080_NOTIFIERS_NVENC_IDX(*pNotifyType); - engineType = NV2080_ENGINE_TYPE_NVENC(engineIdx); + rmEngineType = RM_ENGINE_TYPE_NVENC(engineIdx); - if (!kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, engineType, ref)) + if (!kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, rmEngineType, ref)) return NV_ERR_OBJECT_NOT_FOUND; NV_ASSERT_OK_OR_RETURN( kmigmgrGetGlobalToLocalEngineType(pGpu, pKernelMIGManager, ref, - engineType, - &localType)); - localIdx = NV2080_ENGINE_TYPE_NVENC_IDX(localType); + rmEngineType, + &localRmEngineType)); + localIdx = RM_ENGINE_TYPE_NVENC_IDX(localRmEngineType); *pNotifyType = NV2080_NOTIFIERS_NVENC(localIdx); } return NV_OK; @@ -558,6 +559,59 @@ gpuNotifySubDeviceEvent_IMPL } } +// +// For a particular gpu, find all the clients waiting for a particular event, +// fill in the notifier if allocated, and raise an event to the client if registered. +// +void +gpuGspPluginTriggeredEvent_IMPL +( + OBJGPU *pGpu, + NvU32 gfid, + NvU32 notifyIndex +) +{ + PEVENTNOTIFICATION pEventNotification; + RS_SHARE_ITERATOR it = serverutilShareIter(classId(NotifShare)); + + NV_ASSERT_OR_RETURN_VOID(notifyIndex < NVA084_NOTIFIERS_MAXCOUNT); + + // search notifiers with events hooked up for this gpu + while (serverutilShareIterNext(&it)) + { + RsShared *pShared = it.pShared; + KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi; + INotifier *pNotifier; + NotifShare *pNotifierShare = dynamicCast(pShared, NotifShare); + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice; + + if ((pNotifierShare == NULL) || (pNotifierShare->pNotifier == NULL)) + continue; + + pNotifier = pNotifierShare->pNotifier; + pKernelHostVgpuDeviceApi = dynamicCast(pNotifier, KernelHostVgpuDeviceApi); + + // Only notify matching GPUs + if ((pKernelHostVgpuDeviceApi == NULL) || (GPU_RES_GET_GPU(pKernelHostVgpuDeviceApi) != pGpu)) + continue; + GPU_RES_SET_THREAD_BC_STATE(pKernelHostVgpuDeviceApi); + + pKernelHostVgpuDevice = pKernelHostVgpuDeviceApi->pShared->pDevice; + + // Only notify matching GFID + if (pKernelHostVgpuDevice == NULL || (gfid != pKernelHostVgpuDevice->gfid)) + continue; + + pEventNotification = inotifyGetNotificationList(pNotifier); + if (pEventNotification != NULL) + { + // ping any events on the list of type notifyIndex + osEventNotification(pGpu, pEventNotification, notifyIndex, + NULL, 0); + } + } +} + // // Searches the Pid Array to see if the process this client belongs to is already @@ -686,6 +740,15 @@ gpuGetProcWithObject_IMPL break; } + case (classId(KernelHostVgpuDeviceApi)): + { + KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi = dynamicCast(pResourceRef->pResource, KernelHostVgpuDeviceApi); + if (pKernelHostVgpuDeviceApi->pShared->pDevice->vgpuGuest) + { + elementInClient = NV_TRUE; + } + break; + } case (classId(Device)): case (classId(Subdevice)): { diff --git a/src/nvidia/src/kernel/gpu/gpu_suspend.c b/src/nvidia/src/kernel/gpu/gpu_suspend.c new file mode 100644 index 000000000..7c8078cb4 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/gpu_suspend.c @@ -0,0 +1,349 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2000-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/****************************************************************************** +* +* Description: +* This file contains the implementations for Suspend to RAM ("Standby") +* and Suspend to Disk ("Hibernate") +* +******************************************************************************/ + +#include "platform/platform.h" +#include "platform/chipset/chipset.h" +#include "gpu/mem_mgr/mem_mgr.h" +#include "gpu/mem_mgr/fbsr.h" +#include "gpu/gsp/gsp_init_args.h" +#include "gpu/gsp/kernel_gsp.h" +#include "gpu/pmu/kern_pmu.h" +#include "rmgspseq.h" +#include "core/thread_state.h" +#include "vgpu/rpc.h" +#include "gpu/mem_sys/kern_mem_sys.h" + +// +// Helper functions +// +static NV_STATUS gpuPowerManagementEnter(OBJGPU *, NvU32 newLevel, NvU32 flags); +static NV_STATUS gpuPowerManagementResume(OBJGPU *, NvU32 oldLevel, NvU32 flags); + +// XXX Needs to be further cleaned up. No new code should be placed in this +// routine. Please use the per-engine StateLoad() and StateUnload() routines +// instead +static NV_STATUS +gpuPowerManagementEnter(OBJGPU *pGpu, NvU32 newLevel, NvU32 flags) +{ + NV_STATUS status = NV_OK; + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + // This is a no-op in CPU-RM + NV_ASSERT_OK_OR_GOTO(status, gpuPowerManagementEnterPreUnloadPhysical(pGpu), done); + + NV_ASSERT_OK_OR_GOTO(status, gpuStateUnload(pGpu, + IS_GPU_GC6_STATE_ENTERING(pGpu) ? + GPU_STATE_FLAGS_PRESERVING | GPU_STATE_FLAGS_PM_TRANSITION | GPU_STATE_FLAGS_GC6_TRANSITION : + GPU_STATE_FLAGS_PRESERVING | GPU_STATE_FLAGS_PM_TRANSITION), done); + + pGpu->setProperty(pGpu, PDB_PROP_GPU_VGA_ENABLED, NV_TRUE); + + // This is a no-op in CPU-RM + NV_ASSERT_OK_OR_GOTO(status, gpuPowerManagementEnterPostUnloadPhysical(pGpu, newLevel), done); + + if (IS_GSP_CLIENT(pGpu)) + { + NV_ASSERT_OK_OR_GOTO(status, memmgrSavePowerMgmtState(pGpu, pMemoryManager), done); + + NV_RM_RPC_UNLOADING_GUEST_DRIVER(pGpu, status, NV_TRUE, IS_GPU_GC6_STATE_ENTERING(pGpu), newLevel); + if (status != NV_OK) + goto done; + + kpmuFreeLibosLoggingStructures(pGpu, GPU_GET_KERNEL_PMU(pGpu)); + + } + +done: + if (status != NV_OK) + { + memmgrFreeFbsrMemory(pGpu, pMemoryManager); + } + + return status; +} + +#ifdef DEBUG +int g_BreakOnResume = 0; +#endif + +// XXX Needs to be further cleaned up. No new code should be placed in this +// routine. Please use the per-engine StateLoad() and StateUnload() routines +// instead +static NV_STATUS +gpuPowerManagementResume(OBJGPU *pGpu, NvU32 oldLevel, NvU32 flags) +{ + NV_STATUS status = NV_OK; + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJCL *pCl = SYS_GET_CL(pSys); + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + +#ifdef DEBUG + // + // This is useful for windbg debugging as it frequently doesn't reconnect to the + // target system until after the majority of the resume code has been ran. + // Placing an int 3 at the entrypoint to S/R resume code causes the target to + // halt until the debugger reconnects and the user is then able to place + // breakpoints / step through code. + // + if (g_BreakOnResume) + { + DBG_BREAKPOINT(); + } +#endif + + if (pCl != NULL) + { + status = clResumeBridge(pCl); + NV_ASSERT(status == NV_OK); + } + + if (IS_GSP_CLIENT(pGpu)) + { + // + // GSP-RM expects sysmem flush buffer address to be programmed by Kernel-RM. + // As this buffer is used to perform a system flush while resetting Gpu Falcons. + // + kmemsysProgramSysmemFlushBuffer_HAL(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)); + + KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); + + status = kpmuInitLibosLoggingStructures(pGpu, GPU_GET_KERNEL_PMU(pGpu)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "cannot init libOS PMU logging structures: 0x%x\n", status); + goto done; + } + + GSP_SR_INIT_ARGUMENTS gspSrInitArgs; + + gspSrInitArgs.oldLevel = oldLevel; + gspSrInitArgs.flags = flags; + gspSrInitArgs.bInPMTransition = NV_TRUE; + + kgspPopulateGspRmInitArgs(pGpu, pKernelGsp, &gspSrInitArgs); + + // + // GSP-TODO - Remove following line after the following is implemented + // JIRA CORERM-4274 - Open RM - Suspend & Resume - GSP Heap and FW save/restore + // + // Reset timeout due to long memmgrRestorePowerMgmtState() through BAR0 Window + // + threadStateResetTimeout(pGpu); + + status = kgspExecuteSequencerCommand_HAL(pGpu, pKernelGsp, GSP_SEQ_BUF_OPCODE_CORE_RESUME, NULL, 0); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "cannot resume riscv/gsp: 0x%x\n", status); + goto done; + } + + status = kgspWaitForRmInitDone(pGpu, pKernelGsp); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "State load at resume for riscv/gsp failed: 0x%x\n", status); + goto done; + } + } + + // This is a no-op in CPU-RM + NV_ASSERT_OK_OR_GOTO(status, gpuPowerManagementResumePreLoadPhysical(pGpu, oldLevel, flags), done); + + pGpu->setProperty(pGpu, PDB_PROP_GPU_VGA_ENABLED, NV_FALSE); + + NV_ASSERT_OK_OR_GOTO(status, gpuStateLoad(pGpu, + IS_GPU_GC6_STATE_EXITING(pGpu) ? + GPU_STATE_FLAGS_PRESERVING | GPU_STATE_FLAGS_PM_TRANSITION | GPU_STATE_FLAGS_GC6_TRANSITION : + GPU_STATE_FLAGS_PRESERVING | GPU_STATE_FLAGS_PM_TRANSITION), done); + + // This is a no-op in CPU-RM + NV_ASSERT_OK_OR_GOTO(status, gpuPowerManagementResumePostLoadPhysical(pGpu), done); + + NV_PRINTF(LEVEL_NOTICE, "Adapter now in D0 state\n"); + +done: + memmgrFreeFbsrMemory(pGpu, pMemoryManager); + + return status; +} + +NV_STATUS +gpuEnterStandby_IMPL(OBJGPU *pGpu) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + POBJPFM pPfm = SYS_GET_PFM(pSys); + NV_STATUS suspendStatus; + + if ((pPfm != NULL) && pPfm->getProperty(pPfm, PDB_PROP_PFM_SUPPORTS_ACPI)) + { + NV_PRINTF(LEVEL_INFO, + "gpuPowerState NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_3 Requested\n"); + NV_PRINTF(LEVEL_NOTICE, "Beginning transition from D0 to %s\n", + IS_GPU_GC6_STATE_ENTERING(pGpu) ? "GC6" : "D3"); + } + else + { + NV_PRINTF(LEVEL_INFO, + "gpuPowerState NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_4 Requested\n"); + NV_PRINTF(LEVEL_NOTICE, "Beginning transition to %s\n", + IS_GPU_GC6_STATE_ENTERING(pGpu) ? "GC6" : "APM Suspend"); + } + + pGpu->setProperty(pGpu, PDB_PROP_GPU_IN_PM_CODEPATH, NV_TRUE); + + suspendStatus = gpuPowerManagementEnter(pGpu, NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_3, GPU_STATE_FLAGS_PM_SUSPEND); + + pGpu->setProperty(pGpu, PDB_PROP_GPU_IN_STANDBY, NV_TRUE); + pGpu->bInD3Cold = NV_TRUE; + + if ((pPfm !=NULL) && pPfm->getProperty(pPfm, PDB_PROP_PFM_SUPPORTS_ACPI)) + { + NV_PRINTF(LEVEL_NOTICE, "Ending transition from D0 to %s\n", + IS_GPU_GC6_STATE_ENTERING(pGpu) ? "GC6" : "D3"); + } + else + { + NV_PRINTF(LEVEL_NOTICE, "Ending transition to %s\n", + IS_GPU_GC6_STATE_ENTERING(pGpu) ? "GC6" : "APM Suspend"); + } + + return suspendStatus; +} + +NV_STATUS +gpuResumeFromStandby_IMPL(OBJGPU *pGpu) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + POBJPFM pPfm = SYS_GET_PFM(pSys); + NV_STATUS resumeStatus; + NvU32 state = 0; + + if ((pPfm != NULL) && pPfm->getProperty(pPfm, PDB_PROP_PFM_SUPPORTS_ACPI)) + { + state = NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_3; + NV_PRINTF(LEVEL_INFO, + "gpuPowerState Transitioning from NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_3\n"); + NV_PRINTF(LEVEL_NOTICE, "Beginning transition from %s to D0\n", + IS_GPU_GC6_STATE_EXITING(pGpu) ? "GC6" : "D3"); + } + else + { + state = NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_4; + NV_PRINTF(LEVEL_INFO, + "gpuPowerState Transitioning from NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_4\n"); + NV_PRINTF(LEVEL_NOTICE, "Beginning resume from %s\n", + IS_GPU_GC6_STATE_EXITING(pGpu) ? "GC6" : "APM Suspend"); + } + + pGpu->setProperty(pGpu, PDB_PROP_GPU_IN_PM_RESUME_CODEPATH, NV_TRUE); + + resumeStatus = gpuPowerManagementResume(pGpu, state, GPU_STATE_FLAGS_PM_SUSPEND); + + pGpu->setProperty(pGpu, PDB_PROP_GPU_IN_STANDBY, NV_FALSE); + pGpu->bInD3Cold = NV_FALSE; + pGpu->setProperty(pGpu, PDB_PROP_GPU_IN_PM_CODEPATH, NV_FALSE); + pGpu->setProperty(pGpu, PDB_PROP_GPU_IN_PM_RESUME_CODEPATH, NV_FALSE); + + if ((pPfm != NULL) && pPfm->getProperty(pPfm, PDB_PROP_PFM_SUPPORTS_ACPI)) + { + NV_PRINTF(LEVEL_NOTICE, "Ending transition from %s to D0\n", + IS_GPU_GC6_STATE_EXITING(pGpu) ? "GC6" : "D3"); + } + else + { + NV_PRINTF(LEVEL_NOTICE, "Ending resume from %s\n", + IS_GPU_GC6_STATE_EXITING(pGpu) ? "GC6" : "APM Suspend"); + } + + return resumeStatus; +} + +NV_STATUS gpuEnterHibernate_IMPL(OBJGPU *pGpu) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + POBJPFM pPfm = SYS_GET_PFM(pSys); + NV_STATUS suspendStatus; + + if ((pPfm != NULL) && pPfm->getProperty(pPfm, PDB_PROP_PFM_SUPPORTS_ACPI)) + { + NV_PRINTF(LEVEL_INFO, + "gpuPowerState NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_7 Requested\n"); + NV_PRINTF(LEVEL_NOTICE, "Beginning transition from D0 to D4\n"); + } + else + { + NV_PRINTF(LEVEL_INFO, + "gpuPowerState NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_4 Requested\n"); + NV_PRINTF(LEVEL_NOTICE, "Beginning APM Suspend\n"); + } + + pGpu->setProperty(pGpu, PDB_PROP_GPU_IN_PM_CODEPATH, NV_TRUE); + + suspendStatus = gpuPowerManagementEnter(pGpu, NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_7, GPU_STATE_FLAGS_PM_HIBERNATE); + + NV_PRINTF(LEVEL_INFO, + "gpuPowerState Saving clocks and throttling them down\n"); + + pGpu->setProperty(pGpu, PDB_PROP_GPU_IN_HIBERNATE, NV_TRUE); + + NV_PRINTF(LEVEL_NOTICE, "Ending transition from D0 to D4\n"); + + return suspendStatus; +} + +NV_STATUS gpuResumeFromHibernate_IMPL(OBJGPU *pGpu) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + POBJPFM pPfm = SYS_GET_PFM(pSys); + NV_STATUS resumeStatus; + + NV_PRINTF(LEVEL_INFO, + "gpuPowerState Transitioning from NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_7\n"); + NV_PRINTF(LEVEL_NOTICE, "Beginning transition from D4 to D0\n"); + + pGpu->setProperty(pGpu, PDB_PROP_GPU_IN_PM_RESUME_CODEPATH, NV_TRUE); + + resumeStatus = gpuPowerManagementResume(pGpu, NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_7, GPU_STATE_FLAGS_PM_HIBERNATE); + + pGpu->setProperty(pGpu, PDB_PROP_GPU_IN_HIBERNATE, NV_FALSE); + pGpu->setProperty(pGpu, PDB_PROP_GPU_IN_PM_CODEPATH, NV_FALSE); + pGpu->setProperty(pGpu, PDB_PROP_GPU_IN_PM_RESUME_CODEPATH, NV_FALSE); + + if ((pPfm != NULL) && pPfm->getProperty(pPfm, PDB_PROP_PFM_SUPPORTS_ACPI)) + { + NV_PRINTF(LEVEL_NOTICE, "Ending transition from D4 to D0\n"); + } + else + { + NV_PRINTF(LEVEL_NOTICE, "End resuming from APM Suspend\n"); + } + + return resumeStatus; +} diff --git a/src/nvidia/src/kernel/gpu/gpu_user_shared_data.c b/src/nvidia/src/kernel/gpu/gpu_user_shared_data.c new file mode 100644 index 000000000..29161c337 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/gpu_user_shared_data.c @@ -0,0 +1,247 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gpu/gpu_user_shared_data.h" +#include "gpu/gpu.h" +#include "gpu/subdevice/subdevice.h" +#include "os/os.h" +#include "rmapi/client.h" +#include "rmapi/rmapi.h" +#include "class/cl00de.h" + +NV_STATUS +gpushareddataConstruct_IMPL +( + GpuUserSharedData *pData, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + NV_STATUS status = NV_OK; + OBJGPU *pGpu = GPU_RES_GET_GPU(pData); + MEMORY_DESCRIPTOR *pMemDesc = NULL; + NV00DE_SHARED_DATA *pSharedData; + + if (pGpu->userSharedData.pMemDesc == NULL) + { + // Create a kernel-side mapping for writing the data if one is not already present + status = memdescCreate(&pMemDesc, pGpu, sizeof(NV00DE_SHARED_DATA), 0, NV_TRUE, ADDR_SYSMEM, + NV_MEMORY_WRITECOMBINED, MEMDESC_FLAGS_USER_READ_ONLY); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "memdescCreate failed - status=0x%08x\n", status); + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + status = memdescAlloc(pMemDesc); + if (status != NV_OK) + { + memdescDestroy(pMemDesc); + NV_PRINTF(LEVEL_ERROR, "memdescAlloc failed - status=0x%08x\n", status); + return status; + } + + status = memdescMap(pMemDesc, 0, pMemDesc->Size, + NV_TRUE, NV_PROTECT_READABLE, + &pGpu->userSharedData.pMapBuffer, + &pGpu->userSharedData.pMapBufferPriv); + if (status != NV_OK) + { + memdescFree(pMemDesc); + memdescDestroy(pMemDesc); + NV_PRINTF(LEVEL_ERROR, "memdescMap failed - status=0x%08x\n", status); + return status; + } + + pGpu->userSharedData.pMemDesc = pMemDesc; + + pSharedData = (NV00DE_SHARED_DATA*)(pGpu->userSharedData.pMapBuffer); + portMemSet(pSharedData, 0, sizeof(*pSharedData)); + + // Initial write from cached data + gpushareddataWriteFinish(pGpu); + } + + memdescAddRef(pGpu->userSharedData.pMemDesc); + + return NV_OK; +} + +void +gpushareddataDestruct_IMPL +( + GpuUserSharedData *pData +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pData); + MEMORY_DESCRIPTOR *pMemDesc = pGpu->userSharedData.pMemDesc; + + memdescRemoveRef(pMemDesc); + + if (pMemDesc->RefCount == 1) + { + // Clean up kernel-side mapping if this is the last mapping for this GPU + memdescUnmap(pMemDesc, + NV_TRUE, + pGpu->userSharedData.processId, + pGpu->userSharedData.pMapBuffer, + pGpu->userSharedData.pMapBufferPriv); + + memdescFree(pMemDesc); + memdescDestroy(pMemDesc); + pGpu->userSharedData.pMemDesc = NULL; + pGpu->userSharedData.pMapBuffer = NULL; + pGpu->userSharedData.pMapBufferPriv = NULL; + } +} + +NV_STATUS +gpushareddataMap_IMPL +( + GpuUserSharedData *pData, + CALL_CONTEXT *pCallContext, + RS_CPU_MAP_PARAMS *pParams, + RsCpuMapping *pCpuMapping +) +{ + NV_STATUS status; + NvBool bKernel; + RmClient *pClient = dynamicCast(pCallContext->pClient, RmClient); + OBJGPU *pGpu = GPU_RES_GET_GPU(pData); + + status = rmapiValidateKernelMapping(rmclientGetCachedPrivilege(pClient), + pCpuMapping->flags, + &bKernel); + if (status != NV_OK) + return status; + + // Only support read-only, fail early if writeable + if (pCpuMapping->pPrivate->protect & NV_PROTECT_WRITEABLE) + return NV_ERR_INVALID_PARAMETER; + + pCpuMapping->processId = osGetCurrentProcess(); + + // Map entire buffer (no offsets supported) + status = memdescMap(pGpu->userSharedData.pMemDesc, + 0, + pGpu->userSharedData.pMemDesc->Size, + NV_FALSE, + pCpuMapping->pPrivate->protect, + &pCpuMapping->pLinearAddress, + &pCpuMapping->pPrivate->pPriv); + + return status; +} + +NV_STATUS +gpushareddataUnmap_IMPL +( + GpuUserSharedData *pData, + CALL_CONTEXT *pCallContext, + RsCpuMapping *pCpuMapping +) +{ + NV_STATUS status; + NvBool bKernel; + RmClient *pClient = dynamicCast(pCallContext->pClient, RmClient); + OBJGPU *pGpu = GPU_RES_GET_GPU(pData); + + if (pGpu->userSharedData.pMemDesc == NULL) + return NV_ERR_INVALID_OBJECT; + + status = rmapiValidateKernelMapping(rmclientGetCachedPrivilege(pClient), + pCpuMapping->flags, + &bKernel); + if (status != NV_OK) + return status; + + memdescUnmap(pGpu->userSharedData.pMemDesc, + bKernel, + pCpuMapping->processId, + pCpuMapping->pLinearAddress, + pCpuMapping->pPrivate->pPriv); + + return NV_OK; +} + +NV_STATUS +gpushareddataGetMapAddrSpace_IMPL +( + GpuUserSharedData *pData, + CALL_CONTEXT *pCallContext, + NvU32 mapFlags, + NV_ADDRESS_SPACE *pAddrSpace +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pData); + NV_ADDRESS_SPACE addrSpace; + + if (pGpu->userSharedData.pMemDesc == NULL) + return NV_ERR_INVALID_OBJECT; + + NV_ASSERT_OK_OR_RETURN(rmapiGetEffectiveAddrSpace(pGpu, pGpu->userSharedData.pMemDesc, mapFlags, &addrSpace)); + + if (pAddrSpace != NULL) + *pAddrSpace = addrSpace; + + return NV_OK; +} + +NV_STATUS +gpushareddataGetMemoryMappingDescriptor_IMPL +( + GpuUserSharedData *pData, + MEMORY_DESCRIPTOR **ppMemDesc +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pData); + + *ppMemDesc = pGpu->userSharedData.pMemDesc; + + return NV_OK; +} + +NV00DE_SHARED_DATA * gpushareddataWriteStart(OBJGPU *pGpu) +{ + return &pGpu->userSharedData.data; +} + +void gpushareddataWriteFinish(OBJGPU *pGpu) +{ + NV00DE_SHARED_DATA *pSharedData = (NV00DE_SHARED_DATA*)(pGpu->userSharedData.pMapBuffer); + const NvU32 data_offset = sizeof(pSharedData->seq); + const NvU32 data_size = sizeof(NV00DE_SHARED_DATA) - data_offset; + + if (pSharedData == NULL) + return; + + portAtomicIncrementU32(&pSharedData->seq); + portAtomicMemoryFenceStore(); + + // Push cached data to mapped buffer + portMemCopy((NvU8*)pSharedData + data_offset, data_size, + (NvU8*)&pGpu->userSharedData.data + data_offset, data_size); + + portAtomicMemoryFenceStore(); + portAtomicIncrementU32(&pSharedData->seq); +} diff --git a/src/nvidia/src/kernel/gpu/gr/arch/maxwell/kgraphics_gm200.c b/src/nvidia/src/kernel/gpu/gr/arch/maxwell/kgraphics_gm200.c index 70943a441..cd29b7773 100644 --- a/src/nvidia/src/kernel/gpu/gr/arch/maxwell/kgraphics_gm200.c +++ b/src/nvidia/src/kernel/gpu/gr/arch/maxwell/kgraphics_gm200.c @@ -129,7 +129,7 @@ kgraphicsAllocGrGlobalCtxBuffers_GM200 pCtxAttr = pKernelGraphics->globalCtxBuffersInfo.globalCtxAttr; NV_ASSERT_OK_OR_RETURN( ctxBufPoolGetGlobalPool(pGpu, CTX_BUF_ID_GR_GLOBAL, - NV2080_ENGINE_TYPE_GR(pKernelGraphics->instance), + RM_ENGINE_TYPE_GR(pKernelGraphics->instance), &pCtxBufPool)); } @@ -142,7 +142,8 @@ kgraphicsAllocGrGlobalCtxBuffers_GM200 flags |= MEMDESC_FLAGS_OWNED_BY_CURRENT_DEVICE; } - if (pCtxBufPool != NULL) + // Don't use context buffer pool for VF allocations managed by host RM. + if (ctxBufPoolIsSupported(pGpu) && (pCtxBufPool != NULL)) { cbAllocFlags |= MEMDESC_FLAGS_OWNED_BY_CTX_BUF_POOL; flags |= MEMDESC_FLAGS_OWNED_BY_CTX_BUF_POOL; @@ -206,6 +207,7 @@ kgraphicsAllocGrGlobalCtxBuffers_GM200 memdescSetGpuCacheAttrib(*ppMemDesc, NV_MEMORY_CACHED); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, memdescAllocList(*ppMemDesc, pCtxAttr[GR_GLOBALCTX_BUFFER_ATTRIBUTE_CB].pAllocList)); + memdescSetName(pGpu, *ppMemDesc, NV_RM_SURF_NAME_GR_CIRCULAR_BUFFER, NULL); } // we do not want/need a priv access map allocated per-channel, so skip allocating diff --git a/src/nvidia/src/kernel/gpu/gr/arch/pascal/kgraphics_gp100.c b/src/nvidia/src/kernel/gpu/gr/arch/pascal/kgraphics_gp100.c index b162fee75..7655876b4 100644 --- a/src/nvidia/src/kernel/gpu/gr/arch/pascal/kgraphics_gp100.c +++ b/src/nvidia/src/kernel/gpu/gr/arch/pascal/kgraphics_gp100.c @@ -125,10 +125,11 @@ kgraphicsAllocGrGlobalCtxBuffers_GP100 { pCtxBuffers = &pKernelGraphics->globalCtxBuffersInfo.pGlobalCtxBuffers[gfid]; NV_ASSERT_OK_OR_RETURN(ctxBufPoolGetGlobalPool(pGpu, CTX_BUF_ID_GR_GLOBAL, - NV2080_ENGINE_TYPE_GR(pKernelGraphics->instance), &pCtxBufPool)); + RM_ENGINE_TYPE_GR(pKernelGraphics->instance), &pCtxBufPool)); } - if (pCtxBufPool != NULL) + // Don't use context buffer pool for VF allocations managed by host RM. + if (ctxBufPoolIsSupported(pGpu) && (pCtxBufPool != NULL)) { allocFlags |= MEMDESC_FLAGS_OWNED_BY_CTX_BUF_POOL; } @@ -170,7 +171,7 @@ kgraphicsAllocGlobalCtxBuffers_GP100 NV_ASSERT_OK_OR_RETURN( ctxBufPoolGetGlobalPool(pGpu, CTX_BUF_ID_GR_GLOBAL, - NV2080_ENGINE_TYPE_GR(pKernelGraphics->instance), + RM_ENGINE_TYPE_GR(pKernelGraphics->instance), &pCtxBufPool)); if (pCtxBufPool != NULL) @@ -223,8 +224,6 @@ kgraphicsAllocGlobalCtxBuffers_GP100 memdescAllocList(*ppMemDesc, pCtxAttr[GR_GLOBALCTX_BUFFER_FECS_EVENT].pAllocList)); } - pCtxBuffers->bFecsBufferAllocated = NV_TRUE; - return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/gr/fecs_event_list.c b/src/nvidia/src/kernel/gpu/gr/fecs_event_list.c index 404619dda..336445f49 100644 --- a/src/nvidia/src/kernel/gpu/gr/fecs_event_list.c +++ b/src/nvidia/src/kernel/gpu/gr/fecs_event_list.c @@ -42,6 +42,7 @@ #include "kernel/gpu/bus/kern_bus.h" #include "kernel/gpu/mem_mgr/mem_mgr.h" #include "kernel/gpu/fifo/kernel_channel.h" +#include "kernel/virtualization/hypervisor/hypervisor.h" #include "rmapi/client.h" #include "class/cl90cdtypes.h" @@ -60,7 +61,6 @@ typedef struct #define NV_FECS_TRACE_MAX_TIMESTAMPS 5 #define NV_FECS_TRACE_MAGIC_INVALIDATED 0xdededede // magic number for entries that have been read -#define NV_FECS_TRACE_MAGIC_PENDING 0xfefefefe // magic number for new entries that have been detected /*! Opaque pointer to private data */ typedef struct VGPU_FECS_TRACE_STAGING_BUFFER VGPU_FECS_TRACE_STAGING_BUFFER; @@ -683,10 +683,8 @@ fecsBufferChanged pPeekRecord = (FECS_EVENT_RECORD*)(pFecsBufferMapping + (pFecsTraceInfo->fecsTraceRdOffset * fecsRecordSize)); - if ((pPeekRecord->magic_lo != NV_FECS_TRACE_MAGIC_INVALIDATED) && - (pPeekRecord->magic_lo != NV_FECS_TRACE_MAGIC_PENDING)) + if (pPeekRecord->magic_lo != NV_FECS_TRACE_MAGIC_INVALIDATED) { - pPeekRecord->magic_lo = NV_FECS_TRACE_MAGIC_PENDING; return NV_TRUE; } @@ -905,7 +903,19 @@ fecsAddBindpoint bSelectLOD = NV_TRUE; #endif - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); + + // On a hypervisor or VM: bail-out early if admin is required + if (IS_VIRTUAL(pGpu) || hypervisorIsVgxHyper()) + { + if (pGpu->bRmProfilingPrivileged && !bAdmin) + { + if (pReasonCode != NULL) + *pReasonCode = NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_ADMIN; + + return NV_ERR_NOT_SUPPORTED; + } + } if (bSelectLOD) { diff --git a/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c b/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c index b76724104..08d79e062 100644 --- a/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c +++ b/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c @@ -385,7 +385,7 @@ NvBool kgraphicsIsPresent_IMPL return NV_TRUE; return kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, - ENGINE_INFO_TYPE_NV2080, NV2080_ENGINE_TYPE_GR(pKernelGraphics->instance), + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, (NvU32)RM_ENGINE_TYPE_GR(pKernelGraphics->instance), ENGINE_INFO_TYPE_INVALID, &unused) == NV_OK; } @@ -404,7 +404,7 @@ kgraphicsStatePostLoad_IMPL if ((!IS_VIRTUAL(pGpu)) && (pKernelGraphicsStaticInfo != NULL) && (pKernelGraphicsStaticInfo->pContextBuffersInfo != NULL) && - (!pKernelGraphics->globalCtxBuffersInfo.pGlobalCtxBuffers[GPU_GFID_PF].bFecsBufferAllocated)) + (kgraphicsGetGlobalCtxBuffers(pGpu, pKernelGraphics, GPU_GFID_PF)->memDesc[GR_GLOBALCTX_BUFFER_FECS_EVENT] == NULL)) { NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kgraphicsAllocGlobalCtxBuffers_HAL(pGpu, pKernelGraphics, GPU_GFID_PF)); @@ -592,6 +592,14 @@ kgraphicsInitializeDeferredStaticData_IMPL gfid = GPU_GFID_PF; } + // + // Most of GR is stub'd so context related things are not needed in AMODEL. + // But this function can be called in some MODS test, so return OK directly + // to avoid failing the test. + // + if (IS_MODS_AMODEL(pGpu)) + return NV_OK; + // Not ready if (!pPrivate->bInitialized) return NV_OK; @@ -615,7 +623,7 @@ kgraphicsInitializeDeferredStaticData_IMPL NV_ASSERT_OK_OR_RETURN( kmigmgrGetMIGReferenceFromEngineType(pGpu, pKernelMIGManager, - NV2080_ENGINE_TYPE_GR(pKernelGraphics->instance), &ref)); + RM_ENGINE_TYPE_GR(pKernelGraphics->instance), &ref)); swizzId = ref.pKernelMIGGpuInstance->swizzId; } @@ -636,7 +644,7 @@ kgraphicsInitializeDeferredStaticData_IMPL if (IS_MIG_IN_USE(pGpu)) { MIG_INSTANCE_REF ref; - NvU32 localEngineType; + RM_ENGINE_TYPE localRmEngineType; // Physical RM will fill with local indices, so localize the index NV_CHECK_OK_OR_GOTO( @@ -648,10 +656,10 @@ kgraphicsInitializeDeferredStaticData_IMPL status, LEVEL_ERROR, kmigmgrGetGlobalToLocalEngineType(pGpu, pKernelMIGManager, ref, - NV2080_ENGINE_TYPE_GR(grIdx), - &localEngineType), + RM_ENGINE_TYPE_GR(grIdx), + &localRmEngineType), cleanup); - grIdx = NV2080_ENGINE_TYPE_GR_IDX(localEngineType); + grIdx = RM_ENGINE_TYPE_GR_IDX(localRmEngineType); } pParams = portMemAllocNonPaged(sizeof(*pParams)); @@ -776,7 +784,7 @@ kgraphicsLoadStaticInfo_KERNEL { KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); MIG_INSTANCE_REF ref; - NvU32 localEngineType; + RM_ENGINE_TYPE localRmEngineType; // Physical RM will fill with local indices, so localize the index NV_CHECK_OK_OR_GOTO( @@ -788,10 +796,10 @@ kgraphicsLoadStaticInfo_KERNEL status, LEVEL_ERROR, kmigmgrGetGlobalToLocalEngineType(pGpu, pKernelMIGManager, ref, - NV2080_ENGINE_TYPE_GR(grIdx), - &localEngineType), + RM_ENGINE_TYPE_GR(grIdx), + &localRmEngineType), cleanup); - grIdx = NV2080_ENGINE_TYPE_GR_IDX(localEngineType); + grIdx = RM_ENGINE_TYPE_GR_IDX(localRmEngineType); } // GR Caps @@ -1310,7 +1318,7 @@ kgraphicsAllocKgraphicsBuffers_KERNEL // Allocate global context buffers for this gfid, if they haven't been // already // - if (!pKernelGraphics->globalCtxBuffersInfo.pGlobalCtxBuffers[gfid].bFecsBufferAllocated) + if (kgraphicsGetGlobalCtxBuffers(pGpu, pKernelGraphics, gfid)->memDesc[GR_GLOBALCTX_BUFFER_FECS_EVENT] == NULL) { NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kgraphicsAllocGlobalCtxBuffers_HAL(pGpu, pKernelGraphics, gfid)); @@ -1318,7 +1326,7 @@ kgraphicsAllocKgraphicsBuffers_KERNEL if (kgraphicsIsCtxswLoggingSupported(pGpu, pKernelGraphics) && !pKernelGraphics->globalCtxBuffersInfo.pGlobalCtxBuffers[gfid].bFecsTraceUnsupportedInGuest && - pKernelGraphics->globalCtxBuffersInfo.pGlobalCtxBuffers[gfid].bFecsBufferAllocated) + (kgraphicsGetGlobalCtxBuffers(pGpu, pKernelGraphics, gfid)->memDesc[GR_GLOBALCTX_BUFFER_FECS_EVENT] != NULL)) { if (!gvaspaceIsExternallyOwned(pGVAS) && !IS_VIRTUAL_WITHOUT_SRIOV(pGpu)) { @@ -1461,11 +1469,7 @@ kgraphicsMapCtxBuffer_IMPL // If subcontext is supported, create an identity mapping to the existing one. // - // Get the first node after the dummy node - VA_INFO *pVaInfo = mapFind(pVaList, 0); - NV_ASSERT_OR_RETURN(pVaInfo != NULL, NV_ERR_INVALID_STATE); - pVaInfo = mapNext(pVaList, pVaInfo); - if (pVaInfo == NULL) + if (vaListMapCount(pVaList) == 0) { status = dmaMapBuffer_HAL(pGpu, GPU_GET_DMA(pGpu), pVAS, pMemDesc, @@ -1475,7 +1479,16 @@ kgraphicsMapCtxBuffer_IMPL } else { + OBJVASPACE *pVas; NvU32 mapFlags = 0x0; + NvU64 vaddrCached; + + FOR_EACH_IN_VADDR_LIST(pVaList, pVas, vaddr) + { + // Find the first virtual address in any VAS + break; + } + FOR_EACH_IN_VADDR_LIST_END(pVaList, pVas, vaddr); if (bIsReadOnly) { @@ -1486,7 +1499,7 @@ kgraphicsMapCtxBuffer_IMPL mapFlags = FLD_SET_DRF(OS46, _FLAGS, _DMA_OFFSET_FIXED, _TRUE, mapFlags); NV_ASSERT(!bAlignSize); // TODO: Add support for size align - vaddr = pVaInfo->vAddr; + vaddrCached = vaddr; NV_ASSERT_OK_OR_ELSE(status, dmaAllocMapping_HAL(pGpu, GPU_GET_DMA(pGpu), pVAS, pMemDesc, &vaddr, @@ -1494,7 +1507,7 @@ kgraphicsMapCtxBuffer_IMPL NULL, KMIGMGR_SWIZZID_INVALID), /* do nothing on error, but make sure we overwrite status */;); - NV_ASSERT(vaddr == pVaInfo->vAddr); + NV_ASSERT(vaddr == vaddrCached); } } @@ -1657,7 +1670,7 @@ kgraphicsCreateGoldenImageChannel_IMPL NvU32 sliLoopReentrancy; NV_VASPACE_ALLOCATION_PARAMETERS vaParams; NV_MEMORY_ALLOCATION_PARAMS memAllocParams; - NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS channelGPFIFOAllocParams; + NV_CHANNEL_ALLOC_PARAMS channelGPFIFOAllocParams; NvU32 classNum; // XXX This should be removed when braodcast SLI support is deprecated @@ -1714,7 +1727,7 @@ kgraphicsCreateGoldenImageChannel_IMPL // Get swizzId for this GR NV_ASSERT_OK_OR_GOTO(status, kmigmgrGetMIGReferenceFromEngineType(pGpu, pKernelMIGManager, - NV2080_ENGINE_TYPE_GR(pKernelGraphics->instance), &ref), + RM_ENGINE_TYPE_GR(pKernelGraphics->instance), &ref), cleanup); portMemSet(&nvC637AllocParams, 0, sizeof(NVC637_ALLOCATION_PARAMETERS)); @@ -1845,7 +1858,7 @@ kgraphicsCreateGoldenImageChannel_IMPL NV_ASSERT_OR_GOTO(classNum != 0, cleanup); // Allocate a bare channel - portMemSet(&channelGPFIFOAllocParams, 0, sizeof(NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS)); + portMemSet(&channelGPFIFOAllocParams, 0, sizeof(NV_CHANNEL_ALLOC_PARAMS)); channelGPFIFOAllocParams.hVASpace = hVASpace; channelGPFIFOAllocParams.hObjectBuffer = hPBVirtMemId; channelGPFIFOAllocParams.gpFifoEntries = gpFifoEntries; @@ -1863,21 +1876,21 @@ kgraphicsCreateGoldenImageChannel_IMPL if (bNeedMIGWar) { MIG_INSTANCE_REF ref; - NvU32 localEngineType; + RM_ENGINE_TYPE localRmEngineType; NV_ASSERT_OK_OR_GOTO(status, kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClientId, &ref), cleanup); NV_ASSERT_OK_OR_GOTO(status, - kmigmgrGetGlobalToLocalEngineType(pGpu, pKernelMIGManager, ref, NV2080_ENGINE_TYPE_GR(pKernelGraphics->instance), &localEngineType), + kmigmgrGetGlobalToLocalEngineType(pGpu, pKernelMIGManager, ref, RM_ENGINE_TYPE_GR(pKernelGraphics->instance), &localRmEngineType), cleanup); - channelGPFIFOAllocParams.engineType = localEngineType; + channelGPFIFOAllocParams.engineType = gpuGetNv2080EngineType(localRmEngineType); } else { - channelGPFIFOAllocParams.engineType = NV2080_ENGINE_TYPE_GR0; + channelGPFIFOAllocParams.engineType = gpuGetNv2080EngineType(RM_ENGINE_TYPE_GR0); } NV_ASSERT_OK_OR_GOTO(status, @@ -1981,6 +1994,7 @@ void kgraphicsFreeGlobalCtxBuffers_IMPL KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); GR_GLOBALCTX_BUFFERS *pCtxBuffers; GR_GLOBALCTX_BUFFER buff; + NvBool bEvict = NV_FALSE; NV_ASSERT(!gpumgrGetBcEnabledStatus(pGpu)); @@ -1989,12 +2003,11 @@ void kgraphicsFreeGlobalCtxBuffers_IMPL pCtxBuffers = &pKernelGraphics->globalCtxBuffersInfo.pGlobalCtxBuffers[gfid]; - // no ctx buffers allocated, so get out early - if (!pCtxBuffers->bAllocated && !pCtxBuffers->bFecsBufferAllocated) - return; - FOR_EACH_IN_ENUM(GR_GLOBALCTX_BUFFER, buff) { + if (pCtxBuffers->memDesc[buff] != NULL) + bEvict = NV_TRUE; + memdescFree(pCtxBuffers->memDesc[buff]); memdescDestroy(pCtxBuffers->memDesc[buff]); pCtxBuffers->memDesc[buff] = NULL; @@ -2003,10 +2016,10 @@ void kgraphicsFreeGlobalCtxBuffers_IMPL FOR_EACH_IN_ENUM_END; pCtxBuffers->bAllocated = NV_FALSE; - pCtxBuffers->bFecsBufferAllocated = NV_FALSE; // make sure all L2 cache lines using CB buffers are clear after we free them - NV_ASSERT_OK(kmemsysCacheOp_HAL(pGpu, pKernelMemorySystem, NULL, FB_CACHE_VIDEO_MEMORY, FB_CACHE_EVICT)); + if (bEvict) + NV_ASSERT_OK(kmemsysCacheOp_HAL(pGpu, pKernelMemorySystem, NULL, FB_CACHE_VIDEO_MEMORY, FB_CACHE_EVICT)); } NV_STATUS @@ -2085,7 +2098,7 @@ kgraphicsServiceNotificationInterrupt_IMPL MODS_ARCH_REPORT(NV_ARCH_EVENT_NONSTALL_GR, "%s", "processing GR nonstall interrupt\n"); kgraphicsNonstallIntrCheckAndClear_HAL(pGpu, pKernelGraphics, pParams->pThreadState); - engineNonStallIntrNotify(pGpu, NV2080_ENGINE_TYPE_GR(pKernelGraphics->instance)); + engineNonStallIntrNotify(pGpu, RM_ENGINE_TYPE_GR(pKernelGraphics->instance)); return NV_OK; } @@ -2111,7 +2124,7 @@ deviceCtrlCmdKGrGetCaps_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); NvBool bCapsPopulated = NV_FALSE; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); if (IsDFPGA(pGpu)) { @@ -2160,7 +2173,7 @@ deviceCtrlCmdKGrGetCapsV2_IMPL { OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); if (IsDFPGA(pGpu)) { @@ -2275,7 +2288,7 @@ deviceCtrlCmdKGrGetInfo_IMPL NvU32 grInfoListSize = NV_MIN(pParams->grInfoListSize, NV0080_CTRL_GR_INFO_MAX_SIZE); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); NV_CHECK_OR_RETURN(LEVEL_ERROR, pGrInfos != NULL, NV_ERR_INVALID_ARGUMENT); @@ -2308,7 +2321,7 @@ deviceCtrlCmdKGrGetInfoV2_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); NvHandle hClient = RES_GET_CLIENT_HANDLE(pDevice); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, _kgraphicsCtrlCmdGrGetInfoV2(pGpu, hClient, pParams)); @@ -2342,7 +2355,7 @@ subdeviceCtrlCmdKGrGetCapsV2_IMPL NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, RES_GET_CLIENT_HANDLE(pSubdevice), &grRouteInfo, &pKernelGraphics)); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); if (pKernelGraphicsStaticInfo == NULL) @@ -2390,7 +2403,7 @@ subdeviceCtrlCmdKGrGetInfo_IMPL KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); NV_CHECK_OR_RETURN(LEVEL_ERROR, pKernelGraphicsManager != NULL, NV_ERR_NOT_SUPPORTED); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); NV_CHECK_OR_RETURN(LEVEL_ERROR, pGrInfos != NULL, NV_ERR_INVALID_ARGUMENT); @@ -2424,7 +2437,7 @@ subdeviceCtrlCmdKGrGetInfoV2_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, _kgraphicsCtrlCmdGrGetInfoV2(pGpu, hClient, pParams)); @@ -2453,7 +2466,7 @@ subdeviceCtrlCmdKGrGetSmToGpcTpcMappings_IMPL const KGRAPHICS_STATIC_INFO *pStaticInfo; NvU32 i; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); if (kmigmgrIsClientUsingDeviceProfiling(pGpu, pKernelMIGManager, hClient)) { @@ -2464,6 +2477,7 @@ subdeviceCtrlCmdKGrGetSmToGpcTpcMappings_IMPL NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &pParams->grRouteInfo, &pKernelGraphics)); } + // Verify static info is available pStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); NV_ASSERT_OR_RETURN(pStaticInfo != NULL, NV_ERR_INVALID_STATE); @@ -2499,7 +2513,7 @@ subdeviceCtrlCmdKGrGetGlobalSmOrder_IMPL const KGRAPHICS_STATIC_INFO *pStaticInfo; NvU32 i; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); if (kmigmgrIsClientUsingDeviceProfiling(pGpu, pKernelMIGManager, hClient)) { @@ -2555,7 +2569,7 @@ subdeviceCtrlCmdKGrGetSmIssueRateModifier_IMPL const KGRAPHICS_STATIC_INFO *pStaticInfo; KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); if (kmigmgrIsClientUsingDeviceProfiling(pGpu, pKernelMIGManager, hClient)) { @@ -2614,7 +2628,7 @@ subdeviceCtrlCmdKGrGetGpcMask_IMPL const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); if (!IS_MIG_IN_USE(pGpu) || kmigmgrIsClientUsingDeviceProfiling(pGpu, pKernelMIGManager, hClient)) @@ -2661,7 +2675,7 @@ subdeviceCtrlCmdKGrGetTpcMask_IMPL KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); NvU32 gpcCount; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); if (!IS_MIG_IN_USE(pGpu) || kmigmgrIsClientUsingDeviceProfiling(pGpu, pKernelMIGManager, hClient)) @@ -2743,7 +2757,7 @@ subdeviceCtrlCmdKGrGetPpcMask_IMPL const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); if (kmigmgrIsClientUsingDeviceProfiling(pGpu, pKernelMIGManager, hClient)) { @@ -2793,7 +2807,7 @@ subdeviceCtrlCmdKGrFecsBindEvtbufForUid_IMPL NvHandle hNotifier = RES_GET_HANDLE(pSubdevice); NvBool bMIGInUse = IS_MIG_IN_USE(pGpu); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); NV_ASSERT_OK_OR_RETURN( serverutilGetResourceRefWithType(hClient, pParams->hEventBuffer, classId(EventBuffer), &pEventBufferRef)); @@ -2837,7 +2851,7 @@ subdeviceCtrlCmdKGrFecsBindEvtbufForUidV2_IMPL NvHandle hNotifier = RES_GET_HANDLE(pSubdevice); pParams->reasonCode = NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NONE; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); NV_ASSERT_OK_OR_RETURN( serverutilGetResourceRefWithType(hClient, pParams->hEventBuffer, classId(EventBuffer), &pEventBufferRef)); @@ -2876,7 +2890,7 @@ subdeviceCtrlCmdKGrGetPhysGpcMask_IMPL KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); NvU32 grIdx = 0; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); if (!IS_MIG_ENABLED(pGpu)) { @@ -2897,7 +2911,7 @@ subdeviceCtrlCmdKGrGetPhysGpcMask_IMPL else { MIG_INSTANCE_REF ref; - NvU32 localEngineType; + RM_ENGINE_TYPE localRmEngineType; // // Get the relevant subscription and see if provided physicalId is @@ -2910,8 +2924,8 @@ subdeviceCtrlCmdKGrGetPhysGpcMask_IMPL NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kmigmgrGetGlobalToLocalEngineType(pGpu, pKernelMIGManager, ref, - NV2080_ENGINE_TYPE_GR(pParams->physSyspipeId), - &localEngineType)); + RM_ENGINE_TYPE_GR(pParams->physSyspipeId), + &localRmEngineType)); // Not failing above means physSyspipeId is valid in GPU instance grIdx = pParams->physSyspipeId; } @@ -2947,7 +2961,7 @@ subdeviceCtrlCmdKGrGetZcullMask_IMPL const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); if (kmigmgrIsClientUsingDeviceProfiling(pGpu, pKernelMIGManager, hClient)) { @@ -3002,7 +3016,7 @@ subdeviceCtrlCmdKGrGetZcullInfo_IMPL KernelGraphics *pKernelGraphics; const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); if (pKernelGraphicsManager == NULL) { @@ -3044,7 +3058,7 @@ subdeviceCtrlCmdKGrCtxswPmMode_IMPL KernelGraphicsContext *pKernelGraphicsContext; RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); if (pParams->pmMode != NV2080_CTRL_CTXSW_PM_MODE_NO_CTXSW) { @@ -3100,7 +3114,7 @@ subdeviceCtrlCmdKGrGetROPInfo_IMPL KernelGraphics *pKernelGraphics; const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); portMemSet(&grRouteInfo, 0, sizeof(grRouteInfo)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, @@ -3141,7 +3155,7 @@ subdeviceCtrlCmdKGrGetAttributeBufferSize_IMPL NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); NvU32 engineId; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); portMemSet(&grRouteInfo, 0, sizeof(grRouteInfo)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, @@ -3187,7 +3201,7 @@ subdeviceCtrlCmdKGrGetEngineContextProperties_IMPL NvU32 alignment = RM_PAGE_SIZE; NvU32 engineId; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); engineId = DRF_VAL(0080_CTRL_FIFO, _GET_ENGINE_CONTEXT_PROPERTIES, _ENGINE_ID, pParams->engineId); @@ -3259,7 +3273,7 @@ subdeviceCtrlCmdKGrGetCtxBufferSize_IMPL NvU64 prevAlignment; NvU32 i; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); // // vGPU: @@ -3364,7 +3378,7 @@ subdeviceCtrlCmdKGrGetCtxBufferInfo_IMPL KernelChannel *pKernelChannel; KernelGraphicsContext *pKernelGraphicsContext; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); // // vGPU: @@ -3434,7 +3448,7 @@ subdeviceCtrlCmdKGrGetCtxBufferPtes_IMPL KernelChannel *pKernelChannel; KernelGraphicsContext *pKernelGraphicsContext; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); // // Currently, ROUTE_TO_VGPU_HOST instructs resource server to call the RPC @@ -3512,7 +3526,7 @@ subdeviceCtrlCmdKGrGetGfxGpcAndTpcInfo_IMPL const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &pParams->grRouteInfo, &pKernelGraphics)); diff --git a/src/nvidia/src/kernel/gpu/gr/kernel_graphics_context.c b/src/nvidia/src/kernel/gpu/gr/kernel_graphics_context.c index df36c5104..510478207 100644 --- a/src/nvidia/src/kernel/gpu/gr/kernel_graphics_context.c +++ b/src/nvidia/src/kernel/gpu/gr/kernel_graphics_context.c @@ -558,7 +558,44 @@ NV_STATUS kgrctxGetUnicast_IMPL return NV_OK; } -NV_STATUS kgrctxLookupMmuFault_IMPL +/*! + * @brief Query the details of MMU faults caused by this context + */ +NV_STATUS +kgrctxLookupMmuFaultInfo_IMPL +( + OBJGPU *pGpu, + KernelGraphicsContext *pKernelGraphicsContext, + NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS *pParams +) +{ + KernelGraphicsContextUnicast *pKernelGraphicsContextUnicast; + const NvU32 size = NV_ARRAY_ELEMENTS(pKernelGraphicsContextUnicast->mmuFault.mmuFaultInfoList); + NvU32 i; + + NV_ASSERT_OK_OR_RETURN( + kgrctxGetUnicast(pGpu, pKernelGraphicsContext, &pKernelGraphicsContextUnicast)); + + NV_ASSERT_OR_RETURN(pKernelGraphicsContextUnicast->mmuFault.head < size, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(pKernelGraphicsContextUnicast->mmuFault.tail < size, NV_ERR_INVALID_STATE); + + pParams->count = 0; + for (i = pKernelGraphicsContextUnicast->mmuFault.tail; + i != pKernelGraphicsContextUnicast->mmuFault.head; + i = (i + 1) % size) + { + pParams->mmuFaultInfoList[pParams->count] = pKernelGraphicsContextUnicast->mmuFault.mmuFaultInfoList[i]; + pParams->count++; + } + + return NV_OK; +} + +/*! + * @brief Query the details of MMU faults caused by this context + */ +NV_STATUS +kgrctxLookupMmuFault_IMPL ( OBJGPU *pGpu, KernelGraphicsContext *pKernelGraphicsContext, @@ -570,11 +607,15 @@ NV_STATUS kgrctxLookupMmuFault_IMPL NV_ASSERT_OK_OR_RETURN( kgrctxGetUnicast(pGpu, pKernelGraphicsContext, &pKernelGraphicsContextUnicast)); - *pMmuFaultInfo = pKernelGraphicsContextUnicast->mmuFaultInfo; + *pMmuFaultInfo = pKernelGraphicsContextUnicast->mmuFault.mmuFaultInfo; return NV_OK; } -NV_STATUS kgrctxClearMmuFault_IMPL +/*! + * @brief clear the details of MMU faults caused by this context + */ +NV_STATUS +kgrctxClearMmuFault_IMPL ( OBJGPU *pGpu, KernelGraphicsContext *pKernelGraphicsContext @@ -585,16 +626,23 @@ NV_STATUS kgrctxClearMmuFault_IMPL NV_ASSERT_OK_OR_RETURN( kgrctxGetUnicast(pGpu, pKernelGraphicsContext, &pKernelGraphicsContextUnicast)); - pKernelGraphicsContextUnicast->mmuFaultInfo.valid = NV_FALSE; - pKernelGraphicsContextUnicast->mmuFaultInfo.faultInfo = 0; + pKernelGraphicsContextUnicast->mmuFault.mmuFaultInfo.valid = NV_FALSE; + pKernelGraphicsContextUnicast->mmuFault.mmuFaultInfo.faultInfo = 0; return NV_OK; } -void kgrctxRecordMmuFault_IMPL +/*! + * @brief Record the details of an MMU fault caused by this context + */ +void +kgrctxRecordMmuFault_IMPL ( OBJGPU *pGpu, KernelGraphicsContext *pKernelGraphicsContext, - NvU32 mmuFaultInfo + NvU32 mmuFaultInfo, + NvU64 mmuFaultAddress, + NvU32 mmuFaultType, + NvU32 mmuFaultAccessType ) { KernelGraphicsContextUnicast *pKernelGraphicsContextUnicast; @@ -604,8 +652,22 @@ void kgrctxRecordMmuFault_IMPL kgrctxGetUnicast(pGpu, pKernelGraphicsContext, &pKernelGraphicsContextUnicast), return;); - pKernelGraphicsContextUnicast->mmuFaultInfo.valid = NV_TRUE; - pKernelGraphicsContextUnicast->mmuFaultInfo.faultInfo = mmuFaultInfo; + pKernelGraphicsContextUnicast->mmuFault.mmuFaultInfo.valid = NV_TRUE; + pKernelGraphicsContextUnicast->mmuFault.mmuFaultInfo.faultInfo = mmuFaultInfo; + + { + const NvU32 size = NV_ARRAY_ELEMENTS(pKernelGraphicsContextUnicast->mmuFault.mmuFaultInfoList); + + NV_ASSERT_OR_RETURN_VOID(pKernelGraphicsContextUnicast->mmuFault.head < size); + NV_ASSERT_OR_RETURN_VOID(pKernelGraphicsContextUnicast->mmuFault.tail < size); + + pKernelGraphicsContextUnicast->mmuFault.mmuFaultInfoList[pKernelGraphicsContextUnicast->mmuFault.head].faultAddress = mmuFaultAddress; + pKernelGraphicsContextUnicast->mmuFault.mmuFaultInfoList[pKernelGraphicsContextUnicast->mmuFault.head].faultType = mmuFaultType; + pKernelGraphicsContextUnicast->mmuFault.mmuFaultInfoList[pKernelGraphicsContextUnicast->mmuFault.head].accessType = mmuFaultAccessType; + pKernelGraphicsContextUnicast->mmuFault.head = (pKernelGraphicsContextUnicast->mmuFault.head + 1) % size; + if (pKernelGraphicsContextUnicast->mmuFault.head == pKernelGraphicsContextUnicast->mmuFault.tail) + pKernelGraphicsContextUnicast->mmuFault.tail = (pKernelGraphicsContextUnicast->mmuFault.tail + 1) % size; + } } /*! @@ -690,19 +752,19 @@ kgrctxGetCtxBuffers_IMPL // Get context patch buffer memdesc. NV_CHECK_OR_RETURN(LEVEL_SILENT, - pKernelGraphicsContextUnicast->ctxPatchBuffer.memDesc != NULL, + pKernelGraphicsContextUnicast->ctxPatchBuffer.pMemDesc != NULL, NV_ERR_INVALID_STATE); NV_CHECK_OR_RETURN(LEVEL_INFO, bufferCountOut < bufferCount, NV_ERR_INVALID_ARGUMENT); pCtxBufferType[bufferCountOut] = NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PATCH; - ppBuffers[bufferCountOut++] = pKernelGraphicsContextUnicast->ctxPatchBuffer.memDesc; + ppBuffers[bufferCountOut++] = pKernelGraphicsContextUnicast->ctxPatchBuffer.pMemDesc; // Add PM ctxsw buffer if it's allocated. - if (pKernelGraphicsContextUnicast->pmCtxswBuffer.memDesc != NULL) + if (pKernelGraphicsContextUnicast->pmCtxswBuffer.pMemDesc != NULL) { NV_CHECK_OR_RETURN(LEVEL_INFO, bufferCountOut < bufferCount, NV_ERR_INVALID_ARGUMENT); pCtxBufferType[bufferCountOut] = NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PM; - ppBuffers[bufferCountOut++] = pKernelGraphicsContextUnicast->pmCtxswBuffer.memDesc; + ppBuffers[bufferCountOut++] = pKernelGraphicsContextUnicast->pmCtxswBuffer.pMemDesc; } if (pFirstGlobalBuffer != NULL) @@ -1080,7 +1142,7 @@ kgrctxAllocPatchBuffer_IMPL pCtxBufPool = pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup->pCtxBufPool; } - ppMemDesc = &pKernelGraphicsContextUnicast->ctxPatchBuffer.memDesc; + ppMemDesc = &pKernelGraphicsContextUnicast->ctxPatchBuffer.pMemDesc; size = pStaticInfo->pContextBuffersInfo->engine[NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PATCH].size; NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, memdescCreate(ppMemDesc, pGpu, size, RM_PAGE_SIZE, NV_TRUE, @@ -1161,7 +1223,7 @@ kgrctxAllocPmBuffer_IMPL flags |= MEMDESC_FLAGS_OWNED_BY_CURRENT_DEVICE; } - ppMemDesc = &pKernelGraphicsContextUnicast->pmCtxswBuffer.memDesc; + ppMemDesc = &pKernelGraphicsContextUnicast->pmCtxswBuffer.pMemDesc; NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, memdescCreate(ppMemDesc, pGpu, size, @@ -1251,7 +1313,7 @@ kgrctxAllocCtxBuffers_IMPL // will be used to override settings in the context after it is restored, things // like the global ctx buffer addresses, etc. // - if (pKernelGraphicsContextUnicast->ctxPatchBuffer.memDesc == NULL) + if (pKernelGraphicsContextUnicast->ctxPatchBuffer.pMemDesc == NULL) { NV_ASSERT_OK_OR_RETURN( kgrctxAllocPatchBuffer(pGpu, pKernelGraphicsContext, pKernelGraphics, pKernelChannel)); @@ -1486,24 +1548,14 @@ kgrctxMapCtxBuffers_IMPL kgrmgrGetGrObjectType(classNum, &objType); NV_ASSERT_OK_OR_RETURN( - kgraphicsMapCtxBuffer(pGpu, pKernelGraphics, pKernelGraphicsContextUnicast->ctxPatchBuffer.memDesc, pKernelChannel->pVAS, + kgraphicsMapCtxBuffer(pGpu, pKernelGraphics, pKernelGraphicsContextUnicast->ctxPatchBuffer.pMemDesc, pKernelChannel->pVAS, &pKernelGraphicsContextUnicast->ctxPatchBuffer.vAddrList, NV_FALSE, NV_FALSE)); - // TODO: Check if this can be moved to subcontext allocation time - if (kgraphicsIsPerSubcontextContextHeaderSupported(pGpu, pKernelGraphics) && - (pKernelGraphicsContextUnicast->pmCtxswBuffer.memDesc != NULL)) + if (pKernelGraphicsContextUnicast->pmCtxswBuffer.pMemDesc != NULL) { - NvU64 vaddr = 0; - - if (vaListFindVa(&pKernelGraphicsContextUnicast->pmCtxswBuffer.vAddrList, pKernelChannel->pVAS, &vaddr) != NV_OK) - { - if (vaListGetManaged(&pKernelGraphicsContextUnicast->pmCtxswBuffer.vAddrList)) - { - NV_ASSERT_OK_OR_RETURN( - kgraphicsMapCtxBuffer(pGpu, pKernelGraphics, pKernelGraphicsContextUnicast->pmCtxswBuffer.memDesc, pKernelChannel->pVAS, - &pKernelGraphicsContextUnicast->pmCtxswBuffer.vAddrList, NV_FALSE, NV_FALSE)); - } - } + NV_ASSERT_OK_OR_RETURN( + kgraphicsMapCtxBuffer(pGpu, pKernelGraphics, pKernelGraphicsContextUnicast->pmCtxswBuffer.pMemDesc, pKernelChannel->pVAS, + &pKernelGraphicsContextUnicast->pmCtxswBuffer.vAddrList, NV_FALSE, NV_FALSE)); } if (kgraphicsDoesUcodeSupportPrivAccessMap(pGpu, pKernelGraphics)) @@ -1590,17 +1642,17 @@ kgrctxPrepareInitializeCtxBuffer_IMPL if (pKernelGraphicsContextUnicast->bKGrPmCtxBufferInitialized) return NV_OK; - if (pKernelGraphicsContextUnicast->pmCtxswBuffer.memDesc == NULL) + if (pKernelGraphicsContextUnicast->pmCtxswBuffer.pMemDesc == NULL) return NV_OK; - pMemDesc = pKernelGraphicsContextUnicast->pmCtxswBuffer.memDesc; + pMemDesc = pKernelGraphicsContextUnicast->pmCtxswBuffer.pMemDesc; break; case NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PATCH: if (pKernelGraphicsContextUnicast->bKGrPatchCtxBufferInitialized) return NV_OK; - NV_ASSERT(pKernelGraphicsContextUnicast->ctxPatchBuffer.memDesc != NULL); - pMemDesc = pKernelGraphicsContextUnicast->ctxPatchBuffer.memDesc; + NV_ASSERT(pKernelGraphicsContextUnicast->ctxPatchBuffer.pMemDesc != NULL); + pMemDesc = pKernelGraphicsContextUnicast->ctxPatchBuffer.pMemDesc; break; case NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_BUFFER_BUNDLE_CB: // fall-through @@ -1928,10 +1980,10 @@ kgrctxSetupDeferredPmBuffer_IMPL // buffers being allocated at channel allocation time and are not going to work for a buffer // created later with an rm ctrl // - NV_ASSERT_OR_RETURN(pKernelGraphicsContextUnicast->pmCtxswBuffer.memDesc != NULL, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(pKernelGraphicsContextUnicast->pmCtxswBuffer.pMemDesc != NULL, NV_ERR_INVALID_STATE); return NV_OK; } - else if (pKernelGraphicsContextUnicast->pmCtxswBuffer.memDesc != NULL) + else if (pKernelGraphicsContextUnicast->pmCtxswBuffer.pMemDesc != NULL) { return NV_OK; } @@ -1945,93 +1997,109 @@ kgrctxSetupDeferredPmBuffer_IMPL // !!! // - if (kgraphicsIsPerSubcontextContextHeaderSupported(pGpu, pKernelGraphics)) { RS_ORDERED_ITERATOR it; RsResourceRef *pScopeRef = RES_GET_REF(pKernelChannel); // Iterate over all channels in this TSG and map the new buffer - if (!pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup->bAllocatedByRm) + if (!pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup->bAllocatedByRm && + kgraphicsIsPerSubcontextContextHeaderSupported(pGpu, pKernelGraphics)) + { pScopeRef = RES_GET_REF(pKernelChannel->pKernelChannelGroupApi); + } it = kchannelGetIter(RES_GET_CLIENT(pKernelChannel), pScopeRef); while (clientRefOrderedIterNext(it.pClient, &it)) { - pKernelChannel = dynamicCast(it.pResourceRef->pResource, KernelChannel); - NV_ASSERT_OR_ELSE(pKernelChannel != NULL, + NvU64 vaddr; + KernelChannel *pLoopKernelChannel = dynamicCast(it.pResourceRef->pResource, KernelChannel); + + NV_ASSERT_OR_ELSE(pLoopKernelChannel != NULL, status = NV_ERR_INVALID_STATE; goto failed;); - NV_ASSERT_OK_OR_GOTO(status, - kgraphicsMapCtxBuffer(pGpu, pKernelGraphics, - pKernelGraphicsContextUnicast->pmCtxswBuffer.memDesc, - pKernelChannel->pVAS, - &pKernelGraphicsContextUnicast->pmCtxswBuffer.vAddrList, - NV_FALSE, - NV_FALSE), - failed); - } - } + if ((vaListFindVa(&pKernelGraphicsContextUnicast->ctxPatchBuffer.vAddrList, pLoopKernelChannel->pVAS, &vaddr) == NV_OK) && + (vaListFindVa(&pKernelGraphicsContextUnicast->pmCtxswBuffer.vAddrList, pLoopKernelChannel->pVAS, &vaddr) != NV_OK)) + { + NvU64 refCount; + NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS params; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NvBool bInitialize; + NvBool bPromote; - { - NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS params; - RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); - NvBool bInitialize; - NvBool bPromote; + NV_ASSERT_OK_OR_GOTO(status, + kgraphicsMapCtxBuffer(pGpu, pKernelGraphics, + pKernelGraphicsContextUnicast->pmCtxswBuffer.pMemDesc, + pLoopKernelChannel->pVAS, + &pKernelGraphicsContextUnicast->pmCtxswBuffer.vAddrList, + NV_FALSE, + NV_FALSE), + failed); - portMemSet(¶ms, 0, sizeof(params)); + // Promote the vaddr for each unique VAS + portMemSet(¶ms, 0, sizeof(params)); - // Setup parameters to initialize the PA if necessary - NV_ASSERT_OK_OR_GOTO(status, - kgrctxPrepareInitializeCtxBuffer(pGpu, - pKernelGraphicsContext, - pKernelGraphics, - pKernelChannel, - NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PM, - ¶ms.promoteEntry[0], - &bInitialize), - failed); + // Setup parameters to initialize the PA if necessary + NV_ASSERT_OK_OR_GOTO(status, + kgrctxPrepareInitializeCtxBuffer(pGpu, + pKernelGraphicsContext, + pKernelGraphics, + pKernelChannel, + NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PM, + ¶ms.promoteEntry[0], + &bInitialize), + failed); - // Setup parameters to promote the VA if necessary - NV_ASSERT_OK_OR_GOTO(status, - kgrctxPreparePromoteCtxBuffer(pGpu, - pKernelGraphicsContext, - pKernelChannel, - NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PM, - ¶ms.promoteEntry[0], - &bPromote), - failed); + // Setup parameters to promote the VA if necessary + NV_ASSERT_OK_OR_GOTO(status, + kgrctxPreparePromoteCtxBuffer(pGpu, + pKernelGraphicsContext, + pKernelChannel, + NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PM, + ¶ms.promoteEntry[0], + &bPromote), + failed); - NV_ASSERT_OR_ELSE(bInitialize && bPromote, - status = NV_ERR_INVALID_STATE; - goto failed;); + NV_ASSERT_OR_ELSE(bInitialize || bPromote, + status = NV_ERR_INVALID_STATE; + goto failed;); - params.engineType = NV2080_ENGINE_TYPE_GR(kgraphicsGetInstance(pGpu, pKernelGraphics)); - params.hChanClient = RES_GET_CLIENT_HANDLE(pKernelChannel); - params.hObject = RES_GET_HANDLE(pKernelChannel); - params.entryCount = 1; + params.engineType = NV2080_ENGINE_TYPE_GR(kgraphicsGetInstance(pGpu, pKernelGraphics)); + params.hChanClient = RES_GET_CLIENT_HANDLE(pKernelChannel); + params.hObject = RES_GET_HANDLE(pKernelChannel); + params.entryCount = 1; - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - pRmApi->Control(pRmApi, - RES_GET_CLIENT_HANDLE(pSubdevice), - RES_GET_HANDLE(pSubdevice), - NV2080_CTRL_CMD_GPU_PROMOTE_CTX, - ¶ms, - sizeof(params)), - failed); + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + pRmApi->Control(pRmApi, + RES_GET_CLIENT_HANDLE(pSubdevice), + RES_GET_HANDLE(pSubdevice), + NV2080_CTRL_CMD_GPU_PROMOTE_CTX, + ¶ms, + sizeof(params)), + failed); - // - // If we successfully promoted the PA, flip a flag to ensure we don't - // try to promote it again. The VA_LIST should already track this for - // VA, but we can't rely on it for PA due to UVM. - // - if (params.promoteEntry[0].bInitialize) - { - kgrctxMarkCtxBufferInitialized(pGpu, - pKernelGraphicsContext, - pKernelGraphics, - pKernelChannel, - params.promoteEntry[0].bufferId); + // + // If we successfully promoted the PA, flip a flag to ensure we don't + // try to promote it again. The VA_LIST should already track this for + // VA, but we can't rely on it for PA due to UVM. + // + if (params.promoteEntry[0].bInitialize) + { + kgrctxMarkCtxBufferInitialized(pGpu, + pKernelGraphicsContext, + pKernelGraphics, + pKernelChannel, + params.promoteEntry[0].bufferId); + } + + // Update the refcount for this buffer now that we've promoted it + NV_ASSERT_OK_OR_GOTO(status, + vaListGetRefCount(&pKernelGraphicsContextUnicast->ctxPatchBuffer.vAddrList, pLoopKernelChannel->pVAS, &refCount), + failed); + NV_ASSERT_OK_OR_GOTO(status, + vaListSetRefCount(&pKernelGraphicsContextUnicast->pmCtxswBuffer.vAddrList, pLoopKernelChannel->pVAS, refCount), + failed); + } } } @@ -2045,19 +2113,26 @@ failed: RsResourceRef *pScopeRef = RES_GET_REF(pKernelChannel); // Iterate over all channels in this TSG and try to unmap the PM ctx buffer - if (!pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup->bAllocatedByRm) + if (!pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup->bAllocatedByRm && + kgraphicsIsPerSubcontextContextHeaderSupported(pGpu, pKernelGraphics)) + { pScopeRef = RES_GET_REF(pKernelChannel->pKernelChannelGroupApi); + } it = kchannelGetIter(RES_GET_CLIENT(pKernelChannel), pScopeRef); while (clientRefOrderedIterNext(it.pClient, &it)) { - pKernelChannel = dynamicCast(it.pResourceRef->pResource, KernelChannel); - if (pKernelChannel == NULL) + NvU64 vaddr; + KernelChannel *pLoopKernelChannel = dynamicCast(it.pResourceRef->pResource, KernelChannel); + if (pLoopKernelChannel == NULL) continue; - kgraphicsUnmapCtxBuffer(pGpu, pKernelGraphics, - pKernelChannel->pVAS, - &pKernelGraphicsContextUnicast->pmCtxswBuffer.vAddrList); + while (vaListFindVa(&pKernelGraphicsContextUnicast->pmCtxswBuffer.vAddrList, pLoopKernelChannel->pVAS, &vaddr) == NV_OK) + { + kgraphicsUnmapCtxBuffer(pGpu, pKernelGraphics, + pLoopKernelChannel->pVAS, + &pKernelGraphicsContextUnicast->pmCtxswBuffer.vAddrList); + } } } @@ -2078,7 +2153,6 @@ kgrctxUnmapCtxPmBuffer_IMPL OBJVASPACE *pVAS ) { - MEMORY_DESCRIPTOR *pMemDesc; KernelGraphicsContextUnicast *pKernelGraphicsContextUnicast; NV_STATUS status; @@ -2088,17 +2162,86 @@ kgrctxUnmapCtxPmBuffer_IMPL kgrctxGetUnicast(pGpu, pKernelGraphicsContext, &pKernelGraphicsContextUnicast), return;); - pMemDesc = pKernelGraphicsContextUnicast->pmCtxswBuffer.memDesc; + kgraphicsUnmapCtxBuffer(pGpu, pKernelGraphics, pVAS, &pKernelGraphicsContextUnicast->pmCtxswBuffer.vAddrList); +} + +/** + * @brief unmap the memory for the zcull context buffer + */ +void +kgrctxUnmapCtxZcullBuffer_IMPL +( + OBJGPU *pGpu, + KernelGraphicsContext *pKernelGraphicsContext, + KernelGraphics *pKernelGraphics, + OBJVASPACE *pVAS +) +{ + KernelGraphicsContextUnicast *pKernelGraphicsContextUnicast; + MEMORY_DESCRIPTOR *pMemDesc; + VA_LIST *pVaList; + NvU64 vaddr; + NV_STATUS status; + + NV_ASSERT_OK_OR_ELSE(status, + kgrctxGetUnicast(pGpu, pKernelGraphicsContext, &pKernelGraphicsContextUnicast), + return;); + + NV_ASSERT(!gpumgrGetBcEnabledStatus(pGpu)); + + pMemDesc = pKernelGraphicsContextUnicast->zcullCtxswBuffer.pMemDesc; + pVaList = &pKernelGraphicsContextUnicast->zcullCtxswBuffer.vAddrList; if (pMemDesc != NULL) { // // This func assumes that the buffer was not allocated per subdevice, - // and will leak any mappings performed by the secondary. + // and will leak any mappings performed by the secondaries. // NV_ASSERT(!memdescHasSubDeviceMemDescs(pMemDesc)); - kgraphicsUnmapCtxBuffer(pGpu, pKernelGraphics, pVAS, &pKernelGraphicsContextUnicast->pmCtxswBuffer.vAddrList); + if (vaListFindVa(pVaList, pVAS, &vaddr) == NV_OK) + { + dmaUnmapBuffer_HAL(pGpu, GPU_GET_DMA(pGpu), pVAS, vaddr); + vaListRemoveVa(pVaList, pVAS); + } } + else if (vaListFindVa(pVaList, pVAS, &vaddr) == NV_OK) + { + // Zcull buffer mapped by client. Remove the VA here + vaListRemoveVa(pVaList, pVAS); + } +} + +/** + * @brief unmap the memory for the preemption context buffers + */ +void +kgrctxUnmapCtxPreemptionBuffers_IMPL +( + OBJGPU *pGpu, + KernelGraphicsContext *pKernelGraphicsContext, + KernelGraphics *pKernelGraphics, + OBJVASPACE *pVAS +) +{ + KernelGraphicsContextUnicast *pKernelGraphicsContextUnicast; + NV_STATUS status; + + NV_ASSERT(!gpumgrGetBcEnabledStatus(pGpu)); + + NV_ASSERT_OK_OR_ELSE(status, + kgrctxGetUnicast(pGpu, pKernelGraphicsContext, &pKernelGraphicsContextUnicast), + return;); + + kgraphicsUnmapCtxBuffer(pGpu, pKernelGraphics, pVAS, &pKernelGraphicsContextUnicast->preemptCtxswBuffer.vAddrList); + + kgraphicsUnmapCtxBuffer(pGpu, pKernelGraphics, pVAS, &pKernelGraphicsContextUnicast->spillCtxswBuffer.vAddrList); + + kgraphicsUnmapCtxBuffer(pGpu, pKernelGraphics, pVAS, &pKernelGraphicsContextUnicast->betaCBCtxswBuffer.vAddrList); + + kgraphicsUnmapCtxBuffer(pGpu, pKernelGraphics, pVAS, &pKernelGraphicsContextUnicast->pagepoolCtxswBuffer.vAddrList); + + kgraphicsUnmapCtxBuffer(pGpu, pKernelGraphics, pVAS, &pKernelGraphicsContextUnicast->rtvCbCtxswBuffer.vAddrList); } /** @@ -2120,9 +2263,10 @@ kgrctxUnmapAssociatedCtxBuffers_IMPL ) { KernelGraphicsContextUnicast *pKernelGraphicsContextUnicast; - NvBool bRelease3d = NV_FALSE; - NvU32 gfid = kchannelGetGfid(pKernelChannel); - NvU32 status; + NvBool bRelease3d = NV_FALSE; + NvU32 gfid = kchannelGetGfid(pKernelChannel); + NvU32 status; + NvU64 refCount; NV_ASSERT(!gpumgrGetBcEnabledStatus(pGpu)); @@ -2155,6 +2299,21 @@ kgrctxUnmapAssociatedCtxBuffers_IMPL kgrctxUnmapGlobalCtxBuffers(pGpu, pKernelGraphicsContext, pKernelGraphics, pKernelChannel->pVAS, gfid); } + // Only unmap once the last channel using this VAS has gone + if ((kgraphicsGetGlobalCtxBuffers(pGpu, pKernelGraphics, gfid)->memDesc[GR_GLOBALCTX_BUFFER_FECS_EVENT] != NULL) && + (vaListGetRefCount(&pKernelGraphicsContextUnicast->globalCtxBufferVaList[GR_GLOBALCTX_BUFFER_FECS_EVENT], pKernelChannel->pVAS, &refCount) == NV_OK) && + (refCount == 1)) + { + kgrctxUnmapGlobalCtxBuffer(pGpu, pKernelGraphicsContext, pKernelGraphics, pKernelChannel->pVAS, GR_GLOBALCTX_BUFFER_FECS_EVENT); + } + + if ((pKernelGraphicsContextUnicast->pmCtxswBuffer.pMemDesc != NULL) && + (vaListGetRefCount(&pKernelGraphicsContextUnicast->pmCtxswBuffer.vAddrList, pKernelChannel->pVAS, &refCount) == NV_OK) && + (refCount == 1)) + { + kgrctxUnmapCtxPmBuffer(pGpu, pKernelGraphicsContext, pKernelGraphics, pKernelChannel->pVAS); + } + // // When sharing contexts across channels we need to defer this until all // objects have been freed. @@ -2162,7 +2321,7 @@ kgrctxUnmapAssociatedCtxBuffers_IMPL NV_CHECK_OR_RETURN_VOID(LEVEL_SILENT, pKernelGraphicsContextUnicast->channelObjects == 0); - if (pKernelGraphicsContextUnicast->ctxPatchBuffer.memDesc != NULL) + if (pKernelGraphicsContextUnicast->ctxPatchBuffer.pMemDesc != NULL) { // // Delay freeing the patch buffer until the last channel free. @@ -2171,13 +2330,10 @@ kgrctxUnmapAssociatedCtxBuffers_IMPL kgraphicsUnmapCtxBuffer(pGpu, pKernelGraphics, pKernelChannel->pVAS, &pKernelGraphicsContextUnicast->ctxPatchBuffer.vAddrList); } - kgrctxUnmapCtxPmBuffer(pGpu, pKernelGraphicsContext, pKernelGraphics, pKernelChannel->pVAS); - - // if we have a zcull ctxsw buffer, this will free it up - kgrctxFreeZcullBuffer(pGpu, pKernelGraphicsContext, pKernelChannel->pVAS); + kgrctxUnmapCtxZcullBuffer(pGpu, pKernelGraphicsContext, pKernelGraphics, pKernelChannel->pVAS); // Release all preemption buffers if they were allocated - kgrctxFreeCtxPreemptionBuffers(pGpu, pKernelGraphicsContext, pKernelChannel->pVAS); + kgrctxUnmapCtxPreemptionBuffers(pGpu, pKernelGraphicsContext, pKernelGraphics, pKernelChannel->pVAS); kgrctxUnmapMainCtxBuffer(pGpu, pKernelGraphicsContext, pKernelGraphics, pKernelChannel); } @@ -2219,7 +2375,7 @@ NvBool kgrctxShouldPreAllocPmBuffer_PF pGVAS = dynamicCast(pKernelChannel->pVAS, OBJGVASPACE); // Do not allocate the buffer, if already allocated - if (pKernelGraphicsContextUnicast->pmCtxswBuffer.memDesc != NULL) + if (pKernelGraphicsContextUnicast->pmCtxswBuffer.pMemDesc != NULL) { return NV_FALSE; } @@ -2258,7 +2414,7 @@ kgrctxShouldPreAllocPmBuffer_VF &pKernelGraphicsContextUnicast)); // Do not allocate the buffer, if already allocated - if (pKernelGraphicsContextUnicast->pmCtxswBuffer.memDesc != NULL) + if (pKernelGraphicsContextUnicast->pmCtxswBuffer.pMemDesc != NULL) { return NV_FALSE; } @@ -2470,20 +2626,17 @@ kgrctxFreeMainCtxBuffer_IMPL } /** - * @brief unmap and free the memory for the zcull context buffer + * @brief free the memory for the zcull context buffer */ void kgrctxFreeZcullBuffer_IMPL ( OBJGPU *pGpu, - KernelGraphicsContext *pKernelGraphicsContext, - OBJVASPACE *pVAS + KernelGraphicsContext *pKernelGraphicsContext ) { KernelGraphicsContextUnicast *pKernelGraphicsContextUnicast; MEMORY_DESCRIPTOR *pMemDesc; - VA_LIST *pVaList; - NvU64 vaddr; NV_STATUS status; NV_ASSERT_OK_OR_ELSE(status, @@ -2492,51 +2645,29 @@ kgrctxFreeZcullBuffer_IMPL NV_ASSERT(!gpumgrGetBcEnabledStatus(pGpu)); - pMemDesc = pKernelGraphicsContextUnicast->zcullCtxswBuffer.memDesc; - pVaList = &pKernelGraphicsContextUnicast->zcullCtxswBuffer.vAddrList; - if (pMemDesc != NULL) - { - // - // This func assumes that the buffer was not allocated per subdevice, - // and will leak any mappings performed by the secondaries. - // - NV_ASSERT(!memdescHasSubDeviceMemDescs(pMemDesc)); - - // TODO separate unmapping from free - NV_ASSERT_OK(vaListFindVa(pVaList, pVAS, &vaddr)); - dmaUnmapBuffer_HAL(pGpu, GPU_GET_DMA(pGpu), pVAS, vaddr); - vaListRemoveVa(pVaList, pVAS); - - // buffer can be shared and refcounted -- released on final free - memdescFree(pMemDesc); - memdescDestroy(pMemDesc); - } - else if (vaListFindVa(pVaList, pVAS, &vaddr) == NV_OK) - { - // Zcull buffer mapped by client. Remove the VA here - vaListRemoveVa(pVaList, pVAS); - } - else + pMemDesc = pKernelGraphicsContextUnicast->zcullCtxswBuffer.pMemDesc; + if (pMemDesc == NULL) { NV_PRINTF(LEVEL_INFO, "call to free zcull ctx buffer not RM managed, skipped!\n"); } - pKernelGraphicsContextUnicast->zcullCtxswBuffer.memDesc = NULL; + // buffer can be shared and refcounted -- released on final free + memdescFree(pMemDesc); + memdescDestroy(pMemDesc); + pKernelGraphicsContextUnicast->zcullCtxswBuffer.pMemDesc = NULL; } /** - * @brief unmap and free the memory for the preemption context buffers + * @brief free the memory for the preemption context buffers */ void kgrctxFreeCtxPreemptionBuffers_IMPL ( OBJGPU *pGpu, - KernelGraphicsContext *pKernelGraphicsContext, - OBJVASPACE *pVAS + KernelGraphicsContext *pKernelGraphicsContext ) { - VirtMemAllocator *pDma = GPU_GET_DMA(pGpu); KernelGraphicsContextUnicast *pKernelGraphicsContextUnicast; NV_STATUS status; @@ -2546,65 +2677,25 @@ kgrctxFreeCtxPreemptionBuffers_IMPL kgrctxGetUnicast(pGpu, pKernelGraphicsContext, &pKernelGraphicsContextUnicast), return;); - if (pKernelGraphicsContextUnicast->preemptCtxswBuffer.pMemDesc != NULL) - { - dmaUnmapBuffer_HAL(pGpu, pDma, pVAS, - pKernelGraphicsContextUnicast->preemptCtxswBuffer.virtualAddr); - - memdescFree(pKernelGraphicsContextUnicast->preemptCtxswBuffer.pMemDesc); - memdescDestroy(pKernelGraphicsContextUnicast->preemptCtxswBuffer.pMemDesc); - } - - if (pKernelGraphicsContextUnicast->spillCtxswBuffer.pMemDesc != NULL) - { - dmaUnmapBuffer_HAL(pGpu, pDma, pVAS, - pKernelGraphicsContextUnicast->spillCtxswBuffer.virtualAddr); - - memdescFree(pKernelGraphicsContextUnicast->spillCtxswBuffer.pMemDesc); - memdescDestroy(pKernelGraphicsContextUnicast->spillCtxswBuffer.pMemDesc); - } - - if (pKernelGraphicsContextUnicast->betaCBCtxswBuffer.pMemDesc != NULL) - { - dmaUnmapBuffer_HAL(pGpu, pDma, pVAS, - pKernelGraphicsContextUnicast->betaCBCtxswBuffer.virtualAddr); - - memdescFree(pKernelGraphicsContextUnicast->betaCBCtxswBuffer.pMemDesc); - memdescDestroy(pKernelGraphicsContextUnicast->betaCBCtxswBuffer.pMemDesc); - } - - if (pKernelGraphicsContextUnicast->pagepoolCtxswBuffer.pMemDesc != NULL) - { - dmaUnmapBuffer_HAL(pGpu, pDma, pVAS, - pKernelGraphicsContextUnicast->pagepoolCtxswBuffer.virtualAddr); - - memdescFree(pKernelGraphicsContextUnicast->pagepoolCtxswBuffer.pMemDesc); - memdescDestroy(pKernelGraphicsContextUnicast->pagepoolCtxswBuffer.pMemDesc); - } - - if (pKernelGraphicsContextUnicast->rtvCbCtxswBuffer.pMemDesc != NULL) - { - dmaUnmapBuffer_HAL(pGpu, pDma, pVAS, - pKernelGraphicsContextUnicast->rtvCbCtxswBuffer.virtualAddr); - - memdescFree(pKernelGraphicsContextUnicast->rtvCbCtxswBuffer.pMemDesc); - memdescDestroy(pKernelGraphicsContextUnicast->rtvCbCtxswBuffer.pMemDesc); - } - + memdescFree(pKernelGraphicsContextUnicast->preemptCtxswBuffer.pMemDesc); + memdescDestroy(pKernelGraphicsContextUnicast->preemptCtxswBuffer.pMemDesc); pKernelGraphicsContextUnicast->preemptCtxswBuffer.pMemDesc = NULL; - pKernelGraphicsContextUnicast->preemptCtxswBuffer.virtualAddr = 0; + memdescFree(pKernelGraphicsContextUnicast->spillCtxswBuffer.pMemDesc); + memdescDestroy(pKernelGraphicsContextUnicast->spillCtxswBuffer.pMemDesc); pKernelGraphicsContextUnicast->spillCtxswBuffer.pMemDesc = NULL; - pKernelGraphicsContextUnicast->spillCtxswBuffer.virtualAddr = 0; + memdescFree(pKernelGraphicsContextUnicast->betaCBCtxswBuffer.pMemDesc); + memdescDestroy(pKernelGraphicsContextUnicast->betaCBCtxswBuffer.pMemDesc); pKernelGraphicsContextUnicast->betaCBCtxswBuffer.pMemDesc = NULL; - pKernelGraphicsContextUnicast->betaCBCtxswBuffer.virtualAddr = 0; + memdescFree(pKernelGraphicsContextUnicast->pagepoolCtxswBuffer.pMemDesc); + memdescDestroy(pKernelGraphicsContextUnicast->pagepoolCtxswBuffer.pMemDesc); pKernelGraphicsContextUnicast->pagepoolCtxswBuffer.pMemDesc = NULL; - pKernelGraphicsContextUnicast->pagepoolCtxswBuffer.virtualAddr = 0; + memdescFree(pKernelGraphicsContextUnicast->rtvCbCtxswBuffer.pMemDesc); + memdescDestroy(pKernelGraphicsContextUnicast->rtvCbCtxswBuffer.pMemDesc); pKernelGraphicsContextUnicast->rtvCbCtxswBuffer.pMemDesc = NULL; - pKernelGraphicsContextUnicast->rtvCbCtxswBuffer.virtualAddr = 0; } /*! @@ -2626,17 +2717,17 @@ kgrctxFreePatchBuffer_IMPL &pKernelGraphicsContextUnicast), return;); - if (pKernelGraphicsContextUnicast->ctxPatchBuffer.memDesc == NULL) + if (pKernelGraphicsContextUnicast->ctxPatchBuffer.pMemDesc == NULL) { NV_PRINTF(LEVEL_INFO, "Attempt to free null ctx patch buffer pointer, skipped!\n"); return; } - memdescFree(pKernelGraphicsContextUnicast->ctxPatchBuffer.memDesc); - memdescDestroy(pKernelGraphicsContextUnicast->ctxPatchBuffer.memDesc); + memdescFree(pKernelGraphicsContextUnicast->ctxPatchBuffer.pMemDesc); + memdescDestroy(pKernelGraphicsContextUnicast->ctxPatchBuffer.pMemDesc); - pKernelGraphicsContextUnicast->ctxPatchBuffer.memDesc = NULL; + pKernelGraphicsContextUnicast->ctxPatchBuffer.pMemDesc = NULL; pKernelGraphicsContextUnicast->bKGrPatchCtxBufferInitialized = NV_FALSE; } @@ -2662,7 +2753,7 @@ kgrctxFreePmBuffer_IMPL &pKernelGraphicsContextUnicast), return;); - pMemDesc = pKernelGraphicsContextUnicast->pmCtxswBuffer.memDesc; + pMemDesc = pKernelGraphicsContextUnicast->pmCtxswBuffer.pMemDesc; if (pMemDesc != NULL) { // @@ -2680,7 +2771,7 @@ kgrctxFreePmBuffer_IMPL "Attempt to free null pm ctx buffer pointer??\n"); } - pKernelGraphicsContextUnicast->pmCtxswBuffer.memDesc = NULL; + pKernelGraphicsContextUnicast->pmCtxswBuffer.pMemDesc = NULL; pKernelGraphicsContextUnicast->bKGrPmCtxBufferInitialized = NV_FALSE; } @@ -2762,6 +2853,12 @@ void kgrctxFreeAssociatedCtxBuffers_IMPL // if we have a PM ctxsw buffer, this will free it up kgrctxFreePmBuffer(pGpu, pKernelGraphicsContext); + // if we have a zcull buffer, this will free it up + kgrctxFreeZcullBuffer(pGpu, pKernelGraphicsContext); + + // If we have preemption buffers, this will free them up + kgrctxFreeCtxPreemptionBuffers(pGpu, pKernelGraphicsContext); + // Release all common buffers used as part of the gr context. kgrctxFreeLocalGlobalCtxBuffers(pGpu, pKernelGraphicsContext); @@ -2788,6 +2885,7 @@ kgrctxUnmapCtxBuffers_IMPL NvBool bRelease3d = NV_FALSE; NvU32 objType; NvU32 gfid; + NvU64 refCount; NV_PRINTF(LEVEL_INFO, "gpu:%d isBC=%d\n", pGpu->gpuInstance, gpumgrGetBcEnabledStatus(pGpu)); @@ -2817,7 +2915,7 @@ kgrctxUnmapCtxBuffers_IMPL } if ((pKernelGraphicsContextUnicast->channelObjects != 0) && - (pKernelGraphicsContextUnicast->ctxPatchBuffer.memDesc != NULL)) + (pKernelGraphicsContextUnicast->ctxPatchBuffer.pMemDesc != NULL)) { // // Delay freeing the patch buffer until the last channel free. @@ -2826,6 +2924,14 @@ kgrctxUnmapCtxBuffers_IMPL kgraphicsUnmapCtxBuffer(pGpu, pKernelGraphics, pKernelChannel->pVAS, &pKernelGraphicsContextUnicast->ctxPatchBuffer.vAddrList); } + // Defer releasing mapping if this would cause the buffer to be unmapped + if ((pKernelGraphicsContextUnicast->pmCtxswBuffer.pMemDesc != NULL) && + (vaListGetRefCount(&pKernelGraphicsContextUnicast->pmCtxswBuffer.vAddrList, pKernelChannel->pVAS, &refCount) == NV_OK) && + (refCount > 1)) + { + kgrctxUnmapCtxPmBuffer(pGpu, pKernelGraphicsContext, pKernelGraphics, pKernelChannel->pVAS); + } + if (kgraphicsDoesUcodeSupportPrivAccessMap(pGpu, pKernelGraphics)) { kgrctxUnmapGlobalCtxBuffer(pGpu, @@ -2835,6 +2941,14 @@ kgrctxUnmapCtxBuffers_IMPL kgrctxGetRegisterAccessMapId_HAL(pGpu, pKernelGraphicsContext, pChannelDescendant->pKernelChannel)); } + // Defer releasing mapping if this would cause the buffer to be unmapped + if ((kgraphicsGetGlobalCtxBuffers(pGpu, pKernelGraphics, gfid)->memDesc[GR_GLOBALCTX_BUFFER_FECS_EVENT] != NULL) && + (vaListGetRefCount(&pKernelGraphicsContextUnicast->globalCtxBufferVaList[GR_GLOBALCTX_BUFFER_FECS_EVENT], pKernelChannel->pVAS, &refCount) == NV_OK) && + (refCount > 1)) + { + kgrctxUnmapGlobalCtxBuffer(pGpu, pKernelGraphicsContext, pKernelGraphics, pKernelChannel->pVAS, GR_GLOBALCTX_BUFFER_FECS_EVENT); + } + // // Condition for releasing 3d context buffer mappings: // For non-TSG & legacy TSG mode, always unmap as long as its not the last @@ -2867,73 +2981,6 @@ kgrctxUnmapCtxBuffers_IMPL return NV_OK; } -/** - * @brief Release subcontext GR resources. - * - * To free GR resources (per-subcontext mappings) where refcouning doesn't work. - * For e.g, PM buffer can be enabled at any time. - * We also free CTXSW logging buffer here since since it is mapped unconditionally for - * all objects but can't be unmapped unconditionally as FECS may try to access this buffer - * even after all objects are freed and may hit page faults. - * We free them when subcontext is freed by calling this function. - */ -NV_STATUS -kgrctxReleaseSubctxResources_IMPL -( - OBJGPU *pGpu, - KernelGraphicsContext *pKernelGraphicsContext, - KernelGraphics *pKernelGraphics, - OBJVASPACE *pVAS, - NvU32 veid -) -{ - KernelGraphicsContextUnicast *pKernelGraphicsContextUnicast; - NvU64 vaddr; - NvU32 gfid; - NvBool bCallingContextPlugin; - GR_GLOBALCTX_BUFFERS *pGlobalCtxBuffers; - - NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &gfid)); - NV_ASSERT_OK_OR_RETURN(vgpuIsCallingContextPlugin(pGpu, &bCallingContextPlugin)); - - pGlobalCtxBuffers = kgraphicsGetGlobalCtxBuffers(pGpu, pKernelGraphics, gfid); - - if (bCallingContextPlugin) - { - gfid = GPU_GFID_PF; - } - - NV_ASSERT(!gpumgrGetBcEnabledStatus(pGpu)); - - NV_ASSERT_OK_OR_RETURN( - kgrctxGetUnicast(pGpu, pKernelGraphicsContext, &pKernelGraphicsContextUnicast)); - - while (vaListFindVa(&pKernelGraphicsContextUnicast->pmCtxswBuffer.vAddrList, pVAS, &vaddr) == NV_OK) - { - kgraphicsUnmapCtxBuffer(pGpu, pKernelGraphics, pVAS, &pKernelGraphicsContextUnicast->pmCtxswBuffer.vAddrList); - } - - if (kgraphicsIsCtxswLoggingSupported(pGpu, pKernelGraphics)) - { - MEMORY_DESCRIPTOR *pMemDesc = pGlobalCtxBuffers->memDesc[GR_GLOBALCTX_BUFFER_FECS_EVENT]; - if (pMemDesc == NULL) - goto done; - - while (vaListFindVa(&pKernelGraphicsContextUnicast->globalCtxBufferVaList[GR_GLOBALCTX_BUFFER_FECS_EVENT], pVAS, &vaddr) == NV_OK) - { - NV_PRINTF(LEVEL_INFO, - "Unmapping CTXSW Buffer PA @ 0x%llx VA @ 0x%llx of Size 0x%llx for VEID = %d\n", - memdescGetPhysAddr(memdescGetMemDescFromGpu(pMemDesc, pGpu), AT_GPU, 0), - vaddr, pMemDesc->Size, veid); - - kgraphicsUnmapCtxBuffer(pGpu, pKernelGraphics, pVAS, &pKernelGraphicsContextUnicast->globalCtxBufferVaList[GR_GLOBALCTX_BUFFER_FECS_EVENT]); - } - } - -done: - return NV_OK; -} - /*! * Function to increment the GR channel object count */ @@ -3073,7 +3120,7 @@ kgrctxGetRegisterAccessMapId_PF // Using cached privilege because this function is called at a raised IRQL. if ((privLevel >= RS_PRIV_LEVEL_USER_ROOT) - ) + && !hypervisorIsVgxHyper() && IS_GFID_PF(kchannelGetGfid(pKernelChannel))) { return GR_GLOBALCTX_BUFFER_UNRESTRICTED_PRIV_ACCESS_MAP; } @@ -3090,7 +3137,7 @@ kgrctxCtrlGetTpcPartitionMode_IMPL { OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelGraphicsContext); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); if (IS_VIRTUAL(pGpu) || IS_GSP_CLIENT(pGpu)) { @@ -3124,7 +3171,7 @@ kgrctxCtrlSetTpcPartitionMode_IMPL { OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelGraphicsContext); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); if (IS_VIRTUAL(pGpu) || IS_GSP_CLIENT(pGpu)) { @@ -3158,7 +3205,7 @@ kgrctxCtrlGetMMUDebugMode_IMPL { OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelGraphicsContext); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); if (IS_VIRTUAL(pGpu) || IS_GSP_CLIENT(pGpu)) { @@ -3192,7 +3239,7 @@ kgrctxCtrlProgramVidmemPromote_IMPL { OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelGraphicsContext); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); if (IS_VIRTUAL(pGpu) || IS_GSP_CLIENT(pGpu)) { @@ -3314,6 +3361,12 @@ shrkgrctxConstructUnicast_IMPL NV_ASSERT_OK_OR_RETURN(vaListInit(&pKernelGraphicsContextUnicast->pmCtxswBuffer.vAddrList)); NV_ASSERT_OK_OR_RETURN(vaListInit(&pKernelGraphicsContextUnicast->zcullCtxswBuffer.vAddrList)); + NV_ASSERT_OK_OR_RETURN(vaListInit(&pKernelGraphicsContextUnicast->preemptCtxswBuffer.vAddrList)); + NV_ASSERT_OK_OR_RETURN(vaListInit(&pKernelGraphicsContextUnicast->spillCtxswBuffer.vAddrList)); + NV_ASSERT_OK_OR_RETURN(vaListInit(&pKernelGraphicsContextUnicast->betaCBCtxswBuffer.vAddrList)); + NV_ASSERT_OK_OR_RETURN(vaListInit(&pKernelGraphicsContextUnicast->pagepoolCtxswBuffer.vAddrList)); + NV_ASSERT_OK_OR_RETURN(vaListInit(&pKernelGraphicsContextUnicast->rtvCbCtxswBuffer.vAddrList)); + pKernelGraphicsContextUnicast->bSupportsPerSubctxHeader = kgraphicsIsPerSubcontextContextHeaderSupported(pGpu, pKernelGraphics); @@ -3381,6 +3434,12 @@ shrkgrctxDestructUnicast_IMPL vaListDestroy(&pKernelGraphicsContextUnicast->ctxPatchBuffer.vAddrList); vaListDestroy(&pKernelGraphicsContextUnicast->pmCtxswBuffer.vAddrList); vaListDestroy(&pKernelGraphicsContextUnicast->zcullCtxswBuffer.vAddrList); + + vaListDestroy(&pKernelGraphicsContextUnicast->preemptCtxswBuffer.vAddrList); + vaListDestroy(&pKernelGraphicsContextUnicast->spillCtxswBuffer.vAddrList); + vaListDestroy(&pKernelGraphicsContextUnicast->betaCBCtxswBuffer.vAddrList); + vaListDestroy(&pKernelGraphicsContextUnicast->pagepoolCtxswBuffer.vAddrList); + vaListDestroy(&pKernelGraphicsContextUnicast->rtvCbCtxswBuffer.vAddrList); } /*! @@ -3394,8 +3453,27 @@ void shrkgrctxDetach_IMPL KernelChannel *pKernelChannel ) { + RM_ENGINE_TYPE rmEngineType = kchannelGetEngineType(pKernelChannel); - if (NV2080_ENGINE_TYPE_IS_GR(kchannelGetEngineType(pKernelChannel))) + // pre-Ampere chips can have NULL engine types. Find the engine type based on runlistId if set + if (!RM_ENGINE_TYPE_IS_VALID(rmEngineType)) + { + if (kchannelIsRunlistSet(pGpu, pKernelChannel)) + { + KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + + NV_ASSERT_OK( + kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, + ENGINE_INFO_TYPE_RUNLIST, kchannelGetRunlistId(pKernelChannel), + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, (NvU32 *)&rmEngineType)); + } + else + { + NV_PRINTF(LEVEL_INFO, "Channel destroyed but never bound, scheduled, or had a descendant object created\n"); + } + } + + if (RM_ENGINE_TYPE_IS_GR(rmEngineType)) { OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelChannel); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); diff --git a/src/nvidia/src/kernel/gpu/gr/kernel_graphics_manager.c b/src/nvidia/src/kernel/gpu/gr/kernel_graphics_manager.c index 095c348b2..102a41ed5 100644 --- a/src/nvidia/src/kernel/gpu/gr/kernel_graphics_manager.c +++ b/src/nvidia/src/kernel/gpu/gr/kernel_graphics_manager.c @@ -428,15 +428,15 @@ kgrmgrCtrlRouteKGR_IMPL { NvU32 localGrIdx = DRF_VAL64(2080_CTRL_GR, _ROUTE_INFO_DATA, _ENGID, grRouteInfo.route); - NvU32 globalEngType; + RM_ENGINE_TYPE globalRmEngType; NV_CHECK_OK_OR_RETURN( LEVEL_ERROR, kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, - NV2080_ENGINE_TYPE_GR(localGrIdx), - &globalEngType)); - NV_ASSERT_OR_RETURN(NV2080_ENGINE_TYPE_IS_GR(globalEngType), NV_ERR_INVALID_STATE); - grIdx = NV2080_ENGINE_TYPE_GR_IDX(globalEngType); + RM_ENGINE_TYPE_GR(localGrIdx), + &globalRmEngType)); + NV_ASSERT_OR_RETURN(RM_ENGINE_TYPE_IS_GR(globalRmEngType), NV_ERR_INVALID_STATE); + grIdx = RM_ENGINE_TYPE_GR_IDX(globalRmEngType); break; } @@ -444,7 +444,7 @@ kgrmgrCtrlRouteKGR_IMPL case NV2080_CTRL_GR_ROUTE_INFO_FLAGS_TYPE_CHANNEL: { KernelChannel *pKernelChannel; - NvU32 engineType; + RM_ENGINE_TYPE rmEngineType; NvHandle hChannel = DRF_VAL64(2080_CTRL_GR, _ROUTE_INFO_DATA, _CHANNEL_HANDLE, grRouteInfo.route); @@ -480,25 +480,25 @@ kgrmgrCtrlRouteKGR_IMPL NV_PRINTF(LEVEL_INFO, "Found TSG with given handle 0x%08x, using this to determine GR engine ID\n", hChannel); - engineType = pKernelChannelGroup->engineType; + rmEngineType = pKernelChannelGroup->engineType; } else { NV_PRINTF(LEVEL_INFO, "Found channel with given handle 0x%08x, using this to determine GR engine ID\n", hChannel); - engineType = kchannelGetEngineType(pKernelChannel); + rmEngineType = kchannelGetEngineType(pKernelChannel); } - if (!NV2080_ENGINE_TYPE_IS_GR(engineType)) + if (!RM_ENGINE_TYPE_IS_GR(rmEngineType)) { NV_PRINTF(LEVEL_ERROR, - "Failed to route GR using non-GR engine type 0x%x\n", - engineType); + "Failed to route GR using non-GR engine type 0x%x (0x%x)\n", + gpuGetNv2080EngineType(rmEngineType), rmEngineType); return NV_ERR_INVALID_ARGUMENT; } - grIdx = NV2080_ENGINE_TYPE_GR_IDX(engineType); + grIdx = RM_ENGINE_TYPE_GR_IDX(rmEngineType); break; } default: @@ -612,7 +612,8 @@ kgrmgrGetLegacyZcullMask_IMPL * @param[IN] pGpu * @param[IN] pKernelGraphicsManager * @param[IN] grIdx phys gr idx - * @param[IN] gpcCount Total GPCs connected to this GR engine + * @param[IN] veidSpanOffset Offset of spans localized to a GPU instance to make the VEID request from + * @param[IN] veidCount Total VEIDs connected to this GR engine * @param[IN] pKernelMIGGPUInstance */ NV_STATUS @@ -621,20 +622,18 @@ kgrmgrAllocVeidsForGrIdx_IMPL OBJGPU *pGpu, KernelGraphicsManager *pKernelGraphicsManager, NvU32 grIdx, - NvU32 gpcCount, + NvU32 veidSpanOffset, + NvU32 veidCount, KERNEL_MIG_GPU_INSTANCE *pKernelMIGGPUInstance ) { NvU32 maxVeidsPerGpc; - NvU32 maxVeidsForThisGr; NvU32 veidStart = 0; NvU32 veidEnd = 0; NvU32 GPUInstanceVeidEnd; NvU64 GPUInstanceVeidMask; NvU64 GPUInstanceFreeVeidMask; - NvU64 grVeidMask; NvU64 reqVeidMask; - NvU32 i; // This GR should not be already configured to use any VEIDs NV_ASSERT_OR_RETURN(pKernelGraphicsManager->grIdxVeidMask[grIdx] == 0, NV_ERR_INVALID_STATE); @@ -643,8 +642,24 @@ kgrmgrAllocVeidsForGrIdx_IMPL kgrmgrGetMaxVeidsPerGpc(pGpu, pKernelGraphicsManager, &maxVeidsPerGpc)); // We statically assign VEIDs to a GR based on the number of GPCs connected to it - maxVeidsForThisGr = maxVeidsPerGpc * gpcCount; - reqVeidMask = DRF_SHIFTMASK64((maxVeidsForThisGr - 1):0); + if (veidCount % maxVeidsPerGpc != 0) + { + NV_PRINTF(LEVEL_ERROR, "veidCount %d is not aligned to maxVeidsPerGpc=%d\n", veidCount, maxVeidsPerGpc); + return NV_ERR_INVALID_ARGUMENT; + } + + NV_ASSERT_OR_RETURN(veidSpanOffset != KMIGMGR_SPAN_OFFSET_INVALID, NV_ERR_INVALID_ARGUMENT); + + veidStart = (veidSpanOffset * maxVeidsPerGpc) + pKernelMIGGPUInstance->resourceAllocation.veidOffset; + veidEnd = veidStart + veidCount - 1; + + NV_ASSERT_OR_RETURN(veidStart < veidEnd, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(veidStart < 64, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(veidEnd < 64, NV_ERR_INVALID_ARGUMENT); + + reqVeidMask = DRF_SHIFTMASK64(veidEnd:veidStart); + + NV_ASSERT_OR_RETURN(reqVeidMask != 0x0, NV_ERR_INVALID_STATE); // Create a mask for VEIDs associated with this GPU instance GPUInstanceVeidEnd = pKernelMIGGPUInstance->resourceAllocation.veidOffset + pKernelMIGGPUInstance->resourceAllocation.veidCount - 1; @@ -652,31 +667,15 @@ kgrmgrAllocVeidsForGrIdx_IMPL NV_ASSERT_OR_RETURN(GPUInstanceVeidMask != 0x0, NV_ERR_INVALID_STATE); - GPUInstanceFreeVeidMask = ~pKernelGraphicsManager->veidInUseMask & GPUInstanceVeidMask; - - for (i = pKernelMIGGPUInstance->resourceAllocation.veidOffset; i <= GPUInstanceVeidEnd; i += maxVeidsPerGpc) - { - // See if requested slots are available within this range - if (((GPUInstanceFreeVeidMask >> i) & reqVeidMask) == reqVeidMask) - { - veidStart = i; - veidEnd = veidStart + maxVeidsForThisGr - 1; - break; - } - } - - NV_CHECK_OR_RETURN(LEVEL_SILENT, i <= GPUInstanceVeidEnd, - NV_ERR_INSUFFICIENT_RESOURCES); - - grVeidMask = DRF_SHIFTMASK64(veidEnd:veidStart); - NV_ASSERT_OR_RETURN(grVeidMask != 0x0, NV_ERR_INVALID_STATE); + GPUInstanceFreeVeidMask = ~(pKernelGraphicsManager->veidInUseMask) & GPUInstanceVeidMask; // VEID range should not overlap with existing VEIDs in use - NV_ASSERT_OR_RETURN((pKernelGraphicsManager->veidInUseMask & grVeidMask) == 0, NV_ERR_STATE_IN_USE); + NV_ASSERT_OR_RETURN((pKernelGraphicsManager->veidInUseMask & reqVeidMask) == 0, NV_ERR_STATE_IN_USE); + NV_ASSERT_OR_RETURN((GPUInstanceFreeVeidMask & reqVeidMask) == reqVeidMask, NV_ERR_INSUFFICIENT_RESOURCES); // mark each VEID in the range as "in use" - pKernelGraphicsManager->veidInUseMask |= grVeidMask; - pKernelGraphicsManager->grIdxVeidMask[grIdx] |= grVeidMask; + pKernelGraphicsManager->veidInUseMask |= reqVeidMask; + pKernelGraphicsManager->grIdxVeidMask[grIdx] |= reqVeidMask; return NV_OK; } @@ -800,6 +799,14 @@ kgrmgrDiscoverMaxLocalCtxBufInfo_IMPL const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); NvU32 bufId; + // + // Most of GR is stub'd so context related things are not needed in AMODEL. + // But this function can be called in some MODS test, so return OK directly + // to avoid failing the test. + // + if (IS_MODS_AMODEL(pGpu)) + return NV_OK; + NV_CHECK_OR_RETURN(LEVEL_SILENT, kmigmgrIsMemoryPartitioningNeeded_HAL(pGpu, pKernelMIGManager, swizzId), NV_OK); @@ -899,6 +906,14 @@ kgrmgrDiscoverMaxGlobalCtxBufSizes_IMPL const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; GR_GLOBALCTX_BUFFER bufId; + // + // Most of GR is stub'd so context related things are not needed in AMODEL. + // But this function can be called in some MODS test, so return OK directly + // to avoid failing the test. + // + if (IS_MODS_AMODEL(pGpu)) + return NV_OK; + NV_ASSERT_OR_RETURN(!IS_MIG_IN_USE(pGpu), NV_ERR_INVALID_STATE); // @@ -969,3 +984,97 @@ kgrmgrGetLegacyGpcTpcCount_IMPL return pKernelGraphicsManager->legacyKgraphicsStaticInfo.floorsweepingMasks.tpcCount[gpcId]; } +/*! + * @brief Function to Alloc VEIDs with either a specific placement or first-fit placement + * depending upon the value passed into pSpanStart + * + * @param[IN] pGpu + * @param[IN] pKernelGraphicsManager + * @param[IN/OUT] pInUseMask Mask of VEIDs in-use, updated with newly set VEIDs + * @param[IN] veidCount Total VEIDs connected to this GR engine + * @param[IN/OUT] pSpanStart GPU Instance local span offset to begin assigning VEIDs from + * @param[IN] pKernelMIGGPUInstance + */ +NV_STATUS +kgrmgrCheckVeidsRequest_IMPL +( + OBJGPU *pGpu, + KernelGraphicsManager *pKernelGraphicsManager, + NvU64 *pInUseMask, + NvU32 veidCount, + NvU32 *pSpanStart, + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGPUInstance +) +{ + NvU32 maxVeidsPerGpc; + NvU32 veidStart = 0; + NvU32 veidEnd = 0; + NvU32 GPUInstanceVeidEnd; + NvU64 GPUInstanceVeidMask; + NvU64 GPUInstanceFreeVeidMask; + NvU64 veidMask; + + NV_ASSERT_OK_OR_RETURN( + kgrmgrGetMaxVeidsPerGpc(pGpu, pKernelGraphicsManager, &maxVeidsPerGpc)); + + NV_ASSERT_OR_RETURN(pSpanStart != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pInUseMask != NULL, NV_ERR_INVALID_ARGUMENT); + + // We statically assign VEIDs to a GR based on the number of GPCs connected to it + if (veidCount % maxVeidsPerGpc != 0) + { + NV_PRINTF(LEVEL_ERROR, "veidCount %d is not aligned to maxVeidsPerGpc=%d\n", veidCount, maxVeidsPerGpc); + return NV_ERR_INVALID_ARGUMENT; + } + + // Create a mask for VEIDs associated with this GPU instance + GPUInstanceVeidEnd = pKernelMIGGPUInstance->resourceAllocation.veidOffset + pKernelMIGGPUInstance->resourceAllocation.veidCount - 1; + GPUInstanceVeidMask = DRF_SHIFTMASK64(GPUInstanceVeidEnd:pKernelMIGGPUInstance->resourceAllocation.veidOffset); + + NV_ASSERT_OR_RETURN(GPUInstanceVeidMask != 0x0, NV_ERR_INVALID_STATE); + + GPUInstanceFreeVeidMask = ~(*pInUseMask) & GPUInstanceVeidMask; + + if (*pSpanStart != KMIGMGR_SPAN_OFFSET_INVALID) + { + veidStart = (*pSpanStart * maxVeidsPerGpc) + pKernelMIGGPUInstance->resourceAllocation.veidOffset; + veidEnd = veidStart + veidCount - 1; + + NV_ASSERT_OR_RETURN(veidStart < veidEnd, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(veidStart < 64, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(veidEnd < 64, NV_ERR_INVALID_ARGUMENT); + } + else + { + NvU64 reqVeidMask = DRF_SHIFTMASK64(veidCount - 1:0); + NvU32 i; + + for (i = pKernelMIGGPUInstance->resourceAllocation.veidOffset; i <= GPUInstanceVeidEnd; i += maxVeidsPerGpc) + { + // See if requested slots are available within this range + if (((GPUInstanceFreeVeidMask >> i) & reqVeidMask) == reqVeidMask) + { + veidStart = i; + veidEnd = veidStart + veidCount - 1; + break; + } + } + + NV_CHECK_OR_RETURN(LEVEL_SILENT, i <= GPUInstanceVeidEnd, + NV_ERR_INSUFFICIENT_RESOURCES); + } + + veidMask = DRF_SHIFTMASK64(veidEnd:veidStart); + NV_ASSERT_OR_RETURN(veidMask != 0x0, NV_ERR_INVALID_STATE); + + NV_CHECK_OR_RETURN(LEVEL_ERROR, (GPUInstanceVeidMask & veidMask) == veidMask, NV_ERR_INSUFFICIENT_RESOURCES); + + // VEID range should not overlap with existing VEIDs in use + NV_ASSERT_OR_RETURN((*pInUseMask & veidMask) == 0, NV_ERR_STATE_IN_USE); + + NV_ASSERT(veidStart >= pKernelMIGGPUInstance->resourceAllocation.veidOffset); + + *pSpanStart = (veidStart - pKernelMIGGPUInstance->resourceAllocation.veidOffset) / maxVeidsPerGpc; + *pInUseMask |= veidMask; + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session.c b/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session.c index f45d40d4a..65ec7fc53 100644 --- a/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session.c +++ b/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session.c @@ -233,6 +233,12 @@ ksmdbgssnConstruct_IMPL hClass3dObject = pNv83deAllocParams->hClass3dObject; hKernelSMDebuggerSession = pParams->hResource; + // If given a zero hAppClient, assume the client meant to target the calling hClient. + if (hAppClient == NV01_NULL_OBJECT) + { + hAppClient = pParams->hClient; + } + // Validate + lookup the application client NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, serverGetClientUnderLock(&g_resServ, hAppClient, &pAppClient)); diff --git a/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session_ctrl.c b/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session_ctrl.c index e31aee377..7a3f95c18 100644 --- a/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session_ctrl.c +++ b/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session_ctrl.c @@ -154,7 +154,7 @@ _nv8deCtrlCmdReadWriteSurface NvU32 i; NV_STATUS status = NV_OK; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); if (count > MAX_ACCESS_OPS) return NV_ERR_INVALID_ARGUMENT; @@ -301,7 +301,7 @@ ksmdbgssnCtrlCmdGetMappings_IMPL MMU_TRACE_ARG traceArg = {0}; MMU_TRACE_PARAM mmuParams = {0}; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); // Attempt to retrieve the VAS pointer NV_ASSERT_OK_OR_RETURN( @@ -725,7 +725,6 @@ ksmdbgssnCtrlCmdDebugReadBatchMemory_IMPL { NV_STATUS localStatus = NV_OK; NvP64 pData = (NvP64)(((NvU8 *)pParams->pData) + pParams->entries[i].dataOffset); - NV_CHECK_OR_ELSE(LEVEL_ERROR, pParams->entries[i].dataOffset < pParams->dataLength, localStatus = NV_ERR_INVALID_OFFSET; @@ -766,9 +765,8 @@ ksmdbgssnCtrlCmdDebugWriteBatchMemory_IMPL { NV_STATUS localStatus = NV_OK; NvP64 pData = (NvP64)(((NvU8 *)pParams->pData) + pParams->entries[i].dataOffset); - NV_CHECK_OR_ELSE(LEVEL_ERROR, - (pParams->entries[i].dataOffset + pParams->entries[i].length) <= pParams->dataLength, + pParams->entries[i].dataOffset + pParams->entries[i].length <= pParams->dataLength, localStatus = NV_ERR_INVALID_OFFSET; goto updateStatus; ); @@ -802,7 +800,7 @@ ksmdbgssnCtrlCmdDebugReadAllSmErrorStates_IMPL NV_STATUS rmStatus = NV_OK; OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelSMDebuggerSession); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); if (IS_VIRTUAL(pGpu)) { @@ -848,7 +846,7 @@ ksmdbgssnCtrlCmdDebugClearAllSmErrorStates_IMPL NV_STATUS rmStatus = NV_OK; OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelSMDebuggerSession); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); if (IS_VIRTUAL(pGpu)) { @@ -881,3 +879,45 @@ ksmdbgssnCtrlCmdDebugClearAllSmErrorStates_IMPL return NV_ERR_NOT_SUPPORTED; } +NV_STATUS +ksmdbgssnCtrlCmdDebugReadMMUFaultInfo_IMPL +( + KernelSMDebuggerSession *pKernelSMDebuggerSession, + NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelSMDebuggerSession); + + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + // + // SR-IOV vGPU + // + // MMU fault info is to be managed from within the guest, since host is + // not aware of MMU fault info about the VF. + // SM exception info is still fetched from host via the RPC above. + // + if (IS_GSP_CLIENT(pGpu) || IS_VIRTUAL_WITHOUT_SRIOV(pGpu)) + { + NV_STATUS status = NV_OK; + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; + + NV_RM_RPC_CONTROL(pGpu, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->cmd, + pRmCtrlParams->pParams, + pRmCtrlParams->paramsSize, + status); + return status; + } + + NV_ASSERT_OK_OR_RETURN( + kgrctxLookupMmuFaultInfo(pGpu, + pKernelSMDebuggerSession->pObject->pKernelGraphicsContext, + pParams)); + + return NV_OK; +} + diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c b/src/nvidia/src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c index ac899b0db..72d8c7046 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c @@ -323,6 +323,8 @@ kgspExecuteSequencerCommand_GA102 { KernelFalcon *pKernelSec2Falcon = staticCast(GPU_GET_KERNEL_SEC2(pGpu), KernelFalcon); + pKernelGsp->bLibosLogsPollingEnabled = NV_FALSE; + NV_ASSERT_OK_OR_RETURN(_kgspResetIntoRiscv(pGpu, pKernelGsp)); kgspProgramLibosBootArgsAddr_HAL(pGpu, pKernelGsp); @@ -342,6 +344,8 @@ kgspExecuteSequencerCommand_GA102 DBG_BREAKPOINT(); return NV_ERR_TIMEOUT; } + + pKernelGsp->bLibosLogsPollingEnabled = NV_TRUE; } // Program FALCON_OS diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c b/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c index 45613742e..09b628f7e 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c @@ -37,6 +37,17 @@ #define RISCV_BR_ADDR_ALIGNMENT (8) +const char* +kgspGetSignatureSectionNamePrefix_GH100 +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp +) +{ + return GSP_SIGNATURE_SECTION_NAME_PREFIX; +} + + /*! * Helper Function for kgspResetHw_GH100 * @@ -135,7 +146,7 @@ kgspAllocBootArgs_GH100 // Allocate GSP-FMC arguments NV_ASSERT_OK_OR_GOTO(nvStatus, memdescCreate(&pKernelGsp->pGspFmcArgumentsDescriptor, - pGpu, sizeof(GSP_CC_BOOT_PARAMS), 0x1000, + pGpu, sizeof(GSP_FMC_BOOT_PARAMS), 0x1000, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, MEMDESC_FLAGS_NONE), _kgspAllocBootArgs_exit_cleanup); @@ -151,7 +162,7 @@ kgspAllocBootArgs_GH100 &pVa, &pPriv), _kgspAllocBootArgs_exit_cleanup); - pKernelGsp->pGspFmcArgumentsCached = (GSP_CC_BOOT_PARAMS *)NvP64_VALUE(pVa); + pKernelGsp->pGspFmcArgumentsCached = (GSP_FMC_BOOT_PARAMS *)NvP64_VALUE(pVa); pKernelGsp->pGspFmcArgumentsMappingPriv = pPriv; return kgspAllocBootArgs_TU102(pGpu, pKernelGsp); @@ -267,7 +278,7 @@ kgspCalculateFbLayout_GH100 memdescGetPhysAddr(pKernelGsp->pGspRmBootUcodeMemdesc, AT_GPU, 0); // Physical address and size of GSP-RM firmware in system memory - pWprMeta->sizeOfRadix3Elf = pGspFw->size; + pWprMeta->sizeOfRadix3Elf = pGspFw->imageSize; pWprMeta->sysmemAddrOfRadix3Elf = memdescGetPhysAddr(pKernelGsp->pGspUCodeRadix3Descriptor, AT_GPU, 0); @@ -289,7 +300,7 @@ kgspCalculateFbLayout_GH100 // The WPR heap size (gspFwHeapSize) is variable to also get any padding needed // in the carveout to align the WPR start. We specify a minimum size here. // - pWprMeta->gspFwHeapSize = 64 * 1024 * 1024; + pWprMeta->gspFwHeapSize = kgspGetWprHeapSize(pGpu, pKernelGsp); // Fill in the meta-metadata pWprMeta->revision = GSP_FW_WPR_META_REVISION; @@ -329,14 +340,15 @@ kgspSetupGspFmcArgs_GH100 NV_ASSERT_OR_RETURN(IS_GSP_CLIENT(pGpu), NV_ERR_NOT_SUPPORTED); NV_ASSERT_OR_RETURN(pKernelGsp->pGspFmcArgumentsCached != NULL, NV_ERR_INVALID_STATE); - GSP_CC_BOOT_PARAMS *pGspCcBootParams = pKernelGsp->pGspFmcArgumentsCached; + GSP_FMC_BOOT_PARAMS *pGspFmcBootParams = pKernelGsp->pGspFmcArgumentsCached; - pGspCcBootParams->bootGspRmParams.gspRmDescOffset = memdescGetPhysAddr(pKernelGsp->pWprMetaDescriptor, AT_GPU, 0); - pGspCcBootParams->bootGspRmParams.gspRmDescSize = sizeof(*pKernelGsp->pWprMeta); - pGspCcBootParams->bootGspRmParams.target = _kgspMemdescToDmaTarget(pKernelGsp->pWprMetaDescriptor); + pGspFmcBootParams->bootGspRmParams.gspRmDescOffset = memdescGetPhysAddr(pKernelGsp->pWprMetaDescriptor, AT_GPU, 0); + pGspFmcBootParams->bootGspRmParams.gspRmDescSize = sizeof(*pKernelGsp->pWprMeta); + pGspFmcBootParams->bootGspRmParams.target = _kgspMemdescToDmaTarget(pKernelGsp->pWprMetaDescriptor); + pGspFmcBootParams->bootGspRmParams.bIsGspRmBoot = NV_TRUE; - pGspCcBootParams->gspRmParams.bootArgsOffset = memdescGetPhysAddr(pKernelGsp->pLibosInitArgumentsDescriptor, AT_GPU, 0); - pGspCcBootParams->gspRmParams.target = _kgspMemdescToDmaTarget(pKernelGsp->pLibosInitArgumentsDescriptor); + pGspFmcBootParams->gspRmParams.bootArgsOffset = memdescGetPhysAddr(pKernelGsp->pLibosInitArgumentsDescriptor, AT_GPU, 0); + pGspFmcBootParams->gspRmParams.target = _kgspMemdescToDmaTarget(pKernelGsp->pLibosInitArgumentsDescriptor); return NV_OK; } @@ -361,10 +373,14 @@ _kgspIsLockdownReleased } /*! - * Determine if PRIV target mask is unlocked for GSP. - * This is temporary WAR for bug 3640831 until we have notification protocol in - * place (there is no HW mechanism for CPU to check if GSP is open other than + * Determine if PRIV target mask is unlocked for GSP and BAR0 Decoupler allows GSP access. + * + * This is temporary WAR for the PRIV target mask bug 3640831 until we have notification + * protocol in place (there is no HW mechanism for CPU to check if GSP is open other than * reading 0xBADF41YY code). + * + * Until the programmed BAR0 decoupler settings are cleared, GSP access is blocked from + * the CPU so all reads will return 0. */ static NvBool _kgspIsTargetMaskReleased @@ -386,9 +402,10 @@ _kgspIsTargetMaskReleased reg = osDevReadReg032(pGpu, gpuGetDeviceMapping(pGpu, DEVICE_INDEX_GPU, 0), pKernelFalcon->registerBase + NV_PFALCON_FALCON_HWCFG2); - return (reg & privErrTargetLockedMask) != privErrTargetLocked; + return ((reg != 0) && ((reg & privErrTargetLockedMask) != privErrTargetLocked)); } + static void _kgspBootstrapGspFmc_GH100 ( @@ -554,10 +571,12 @@ kgspBootstrapRiscvOSEarly_GH100 kflcnRegRead_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_MAILBOX0)); NV_PRINTF(LEVEL_ERROR, "NV_PGSP_FALCON_MAILBOX1 = 0x%x\n", kflcnRegRead_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_MAILBOX1)); - return status; } + // Start polling for libos logs now that lockdown is released + pKernelGsp->bLibosLogsPollingEnabled = NV_TRUE; + // Program FALCON_OS RM_RISCV_UCODE_DESC *pRiscvDesc = pKernelGsp->pGspRmBootUcodeDesc; kflcnRegWrite_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_OS, pRiscvDesc->appVersion); @@ -590,3 +609,15 @@ exit: return status; } + +void +kgspGetGspRmBootUcodeStorage_GH100 +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp, + BINDATA_STORAGE **ppBinStorageImage, + BINDATA_STORAGE **ppBinStorageDesc +) +{ + kgspGetGspRmBootUcodeStorage_GA102(pGpu, pKernelGsp, ppBinStorageImage, ppBinStorageDesc); +} diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_booter_tu102.c b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_booter_tu102.c index d41f6e615..1d64717d9 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_booter_tu102.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_booter_tu102.c @@ -58,10 +58,14 @@ s_executeBooterUcode_TU102 NV_PRINTF(LEVEL_INFO, "starting Booter with mailbox0 0x%08x, mailbox1 0x%08x\n", mailbox0, mailbox1); + pKernelGsp->bLibosLogsPollingEnabled = NV_FALSE; + status = kgspExecuteHsFalcon_HAL(pGpu, pKernelGsp, pBooterUcode, pKernelFlcn, &mailbox0, &mailbox1); + pKernelGsp->bLibosLogsPollingEnabled = NV_TRUE; + NV_PRINTF(LEVEL_INFO, "after Booter mailbox0 0x%08x, mailbox1 0x%08x\n", mailbox0, mailbox1); if (status != NV_OK) diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c index 5fe47ca01..5b8ddc94b 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c @@ -463,13 +463,15 @@ kgspGetGspRmBootUcodeStorage_TU102 * | GSP FW ELF | * ---------------------------- <- gspFwOffset * | GSP FW (WPR) HEAP | - * ---------------------------- <- gspFwHeapOffset + * ---------------------------- <- gspFwHeapOffset** * | Booter-placed metadata | * | (struct GspFwWprMeta) | * ---------------------------- <- gspFwWprStart (128K aligned) * | GSP FW (non-WPR) HEAP | * ---------------------------- <- nonWprHeapOffset, gspFwRsvdStart * + * gspFwHeapOffset** contains the RM/Libos Heap. First 16 Mb are for Libos heap + * rest is for GSP-RM * @param pGpu GPU object pointer * @param pKernelGsp KernelGsp object pointer * @param pGspFw Pointer to GSP-RM fw image. @@ -545,7 +547,7 @@ kgspCalculateFbLayout_TU102 pWprMeta->bootBinOffset = NV_ALIGN_DOWN64(pWprMeta->frtsOffset - pWprMeta->sizeOfBootloader, 0x1000); // Compute GSP firmware image size - pWprMeta->sizeOfRadix3Elf = pGspFw->size; + pWprMeta->sizeOfRadix3Elf = pGspFw->imageSize; // // Compute the start of the ELF. Align to 64K to avoid issues with @@ -554,15 +556,15 @@ kgspCalculateFbLayout_TU102 // pWprMeta->gspFwOffset = NV_ALIGN_DOWN64(pWprMeta->bootBinOffset - pWprMeta->sizeOfRadix3Elf, 0x10000); -#define GSP_HEAP_SIZE (64 * 1024 * 1024) + NvU64 wprHeapSize = kgspGetWprHeapSize(pGpu, pKernelGsp); - // Start of WPR region (128KB aligned) + // Start of WPR region (1Mb aligned) pWprMeta->gspFwWprStart = - NV_ALIGN_UP64(pWprMeta->gspFwOffset - GSP_HEAP_SIZE, 0x20000); + NV_ALIGN_DOWN64(pWprMeta->gspFwOffset - wprHeapSize, 0x100000); - // GSP-RM heap in WPR - pWprMeta->gspFwHeapOffset = NV_ALIGN_UP64(pWprMeta->gspFwWprStart + sizeof *pWprMeta, 0x1000); - pWprMeta->gspFwHeapSize = pWprMeta->gspFwOffset - pWprMeta->gspFwHeapOffset; + // GSP-RM heap in WPR, align to 1Mb + pWprMeta->gspFwHeapOffset = NV_ALIGN_UP64(pWprMeta->gspFwWprStart + sizeof *pWprMeta, 0x100000); + pWprMeta->gspFwHeapSize = NV_ALIGN_DOWN64(pWprMeta->gspFwOffset - pWprMeta->gspFwHeapOffset, 0x100000); // Non WPR heap pWprMeta->nonWprHeapSize = kgspGetNonWprHeapSize(pGpu, pKernelGsp); @@ -667,7 +669,7 @@ kgspExecuteSequencerCommand_TU102 // Wait for reload to be completed. status = gpuTimeoutCondWait(pGpu, _kgspIsReloadCompleted, NULL, NULL); - // Check SEC mailbox. + // Check SEC mailbox. secMailbox0 = kflcnRegRead_HAL(pGpu, pKernelSec2Falcon, NV_PFALCON_FALCON_MAILBOX0); if ((status != NV_OK) || (secMailbox0 != NV_OK)) @@ -756,6 +758,9 @@ kgspHealthCheck_TU102 GPU_REG_WR32(pGpu, NV_PGSP_MAILBOX(0), 0); + NV_PRINTF(LEVEL_NOTICE, + "********************************* GSP Failure **********************************\n"); + nvErrorLog_va((void*)pGpu, GSP_ERROR, "GSP Error: Task %d raised error code 0x%x for reason 0x%x at 0x%x (%d more errors skipped)", DRF_VAL(_GSP, _ERROR, _TASK, mb0), @@ -763,6 +768,9 @@ kgspHealthCheck_TU102 DRF_VAL(_GSP, _ERROR, _REASON, mb0), mb1, DRF_VAL(_GSP, _ERROR, _SKIPPED, mb0)); + + NV_PRINTF(LEVEL_NOTICE, + "********************************************************************************\n"); } } @@ -859,7 +867,6 @@ kgspWaitForProcessorSuspend_TU102 return gpuTimeoutCondWait(pGpu, _kgspIsProcessorSuspended, pKernelGsp, NULL); } - #define FWSECLIC_PROG_START_TIMEOUT 50000 // 50ms #define FWSECLIC_PROG_COMPLETE_TIMEOUT 2000000 // 2s @@ -870,10 +877,15 @@ kgspWaitForGfwBootOk_TU102 KernelGsp *pKernelGsp ) { - NvU32 elapsed = 0; - NvU32 timeoutMs = FWSECLIC_PROG_START_TIMEOUT + FWSECLIC_PROG_COMPLETE_TIMEOUT; + NvU32 timeoutUs = FWSECLIC_PROG_START_TIMEOUT + FWSECLIC_PROG_COMPLETE_TIMEOUT; + RMTIMEOUT timeout; + NV_STATUS status = NV_OK; - while (1) + // Use the OS timer since the GPU timer is not ready yet + gpuSetTimeout(pGpu, gpuScaleTimeout(pGpu, timeoutUs), &timeout, + GPU_TIMEOUT_FLAGS_OSTIMER); + + while (status == NV_OK) { // // Before reading the actual GFW_BOOT status register, @@ -897,14 +909,14 @@ kgspWaitForGfwBootOk_TU102 return NV_OK; } } - if (elapsed < timeoutMs) + + status = gpuCheckTimeout(pGpu, &timeout); + if (status == NV_ERR_TIMEOUT) { - osDelay(100); - elapsed += 100; - } - else - { - return NV_ERR_TIMEOUT; + NV_PRINTF(LEVEL_ERROR, + "Timeout waiting for GFW_BOOT to complete\n"); } } + + return status; } diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_vbios_tu102.c b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_vbios_tu102.c index 14a4a1473..30053fb3d 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_vbios_tu102.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_vbios_tu102.c @@ -33,6 +33,7 @@ */ #include "gpu/gsp/kernel_gsp.h" +#include "gpu/pmu/kern_pmu.h" #include "platform/pci_exp_table.h" // PCI_EXP_ROM_* #include "gpu/gpu.h" @@ -54,6 +55,38 @@ typedef struct RomImgSrc OBJGPU *pGpu; } RomImgSrc; +/*! + * Equivalent to GPU_REG_RD08(pGpu, NV_PROM_DATA(offset)), but use raw OS read + * to avoid the 0xbadf sanity checking done by the usual register read + * utilities. + */ +static inline NvU8 +s_promRead08 +( + OBJGPU *pGpu, + NvU32 offset +) +{ + return osDevReadReg008(pGpu, gpuGetDeviceMapping(pGpu, DEVICE_INDEX_GPU, 0), + NV_PROM_DATA(offset)); +} + +/*! + * Equivalent to GPU_REG_RD32(pGpu, NV_PROM_DATA(offset)), but use raw OS read + * to avoid the 0xbadf sanity checking done by the usual register read + * utilities. + */ +static inline NvU32 +s_promRead32 +( + OBJGPU *pGpu, + NvU32 offset +) +{ + return osDevReadReg032(pGpu, gpuGetDeviceMapping(pGpu, DEVICE_INDEX_GPU, 0), + NV_PROM_DATA(offset)); +} + /*! * Read unaligned data from PROM (e.g. VBIOS ROM image) using 32-bit accesses. * @@ -120,14 +153,11 @@ s_romImgReadGeneric NV_ASSERT(pSrc->pGpu != NULL); - // Offset is in NV_PROM. - offset = NV_PROM_DATA(offset); - // Read bios image as aligned 32-bit word(s). - buf.word[0] = GPU_REG_RD32(pSrc->pGpu, offset); + buf.word[0] = s_promRead32(pSrc->pGpu, offset); if (bReadWord1) { - buf.word[1] = GPU_REG_RD32(pSrc->pGpu, offset + sizeof(NvU32)); + buf.word[1] = s_promRead32(pSrc->pGpu, offset + sizeof(NvU32)); } // Combine bytes into number. @@ -422,6 +452,7 @@ kgspExtractVbiosFromRom_TU102 NV_STATUS status = NV_OK; KernelGspVbiosImg *pVbiosImg = NULL; + KernelPmu *pKernelPmu = GPU_GET_KERNEL_PMU(pGpu); RomImgSrc src; NvU32 romSig; @@ -448,6 +479,17 @@ kgspExtractVbiosFromRom_TU102 src.maxOffset = biosSize; src.pGpu = pGpu; + if (pKernelPmu != NULL) + { + status = kpmuPreOsGlobalErotGrantRequest_HAL(pGpu, pKernelPmu); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "ERoT Req/Grant for EEPROM access failed, status=%u\n", + status); + return status; + } + } + // Find ROM start romSig = s_romImgRead16(&src, OFFSETOF_PCI_EXP_ROM_SIG, &status); NV_ASSERT_OK_OR_GOTO(status, status, out); @@ -500,13 +542,13 @@ kgspExtractVbiosFromRom_TU102 biosSizeAligned = biosSize & (~0x3); for (i = 0; i < biosSizeAligned; i += 4) { - pImageDwords[i >> 2] = GPU_REG_RD32(pGpu, pciOffset + NV_PROM_DATA(i)); + pImageDwords[i >> 2] = s_promRead32(pGpu, pciOffset + i); } for (; i < biosSize; i++) { // Finish for non-32-bit-aligned biosSize - ((NvU8 *) pImageDwords)[i] = GPU_REG_RD08(pGpu, pciOffset + NV_PROM_DATA(i)); + ((NvU8 *) pImageDwords)[i] = s_promRead08(pGpu, pciOffset + i); } pVbiosImg->pImage = (NvU8 *) pImageDwords; diff --git a/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c b/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c index 07e60c743..6e540b3bf 100644 --- a/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c +++ b/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c @@ -31,18 +31,26 @@ #include "kernel/gpu/mem_mgr/heap.h" #include "kernel/gpu/mem_mgr/mem_mgr.h" #include "kernel/gpu/rc/kernel_rc.h" +#include "kernel/gpu/nvlink/kernel_nvlink.h" +#include "virtualization/vgpuconfigapi.h" #include "kernel/gpu/disp/kern_disp.h" +#include "gpu/external_device/external_device.h" #include "class/cl2080.h" // NV20_SUBDEVICE_0 -#include "logdecode.h" +#include "liblogdecode.h" +#include "libelf.h" #include "nverror.h" +#include "nv-firmware.h" +#include "nv-firmware-chip-family-select.h" #include "nvtypes.h" +#include "nvVer.h" #include "objrpc.h" #include "objtmr.h" #include "os/os.h" #include "rmgspseq.h" #include "sweng/dispsw.h" +#include "kernel/gpu/timed_sema.h" #include "vgpu/rpc.h" #include "kernel/gpu/pmu/kern_pmu.h" #include "gpu/perf/kern_perf.h" @@ -61,8 +69,6 @@ #undef RPC_MESSAGE_GENERIC_UNION #include "gpu/gsp/message_queue_priv.h" -#include "elf.h" - #define RPC_HDR ((rpc_message_header_v*)(pRpc->message_buffer)) @@ -97,12 +103,66 @@ static void _kgspFreeBootBinaryImage(OBJGPU *pGpu, KernelGsp *pKernelGsp); static NV_STATUS _kgspPrepareGspRmBinaryImage(OBJGPU *pGpu, KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw); -static NV_STATUS _kgspGetAndClearSignatureFromBinary(OBJGPU *pGpu, KernelGsp *pKernelGsp, - GSP_FIRMWARE *pGspFw, MEMORY_DESCRIPTOR **ppSignatureMemdesc); - static NV_STATUS _kgspCreateRadix3(OBJGPU *pGpu, MEMORY_DESCRIPTOR **ppMemdescRadix3, MEMORY_DESCRIPTOR *pMemdescData, const void *pData, NvU64 size); +static NV_STATUS _kgspCreateSignatureMemdesc(OBJGPU *pGpu, KernelGsp *pKernelGsp, + GSP_FIRMWARE *pGspFw); + +static NV_STATUS _kgspFwContainerVerifyVersion(OBJGPU *pGpu, KernelGsp *pKernelGsp, + const void *pElfData, NvU64 elfDataSize, + const char *pNameInMsg); + +static NV_STATUS _kgspFwContainerGetSection(OBJGPU *pGpu, KernelGsp *pKernelGsp, + const void *pElfData, NvU64 elfDataSize, + const char *pSectionName, + const void **ppSectionData, NvU64 *pSectionSize); + +static NV_STATUS _kgspGetSectionNameForPrefix(OBJGPU *pGpu, KernelGsp *pKernelGsp, + char *pSectionNameBuf, NvLength sectionNameBufSize, + const char *pSectionPrefix); + +static void +_kgspGetActiveRpcDebugData +( + OBJRPC *pRpc, + NvU32 function, + NvU32 *data0, + NvU32 *data1 +) +{ + switch (function) + { + case NV_VGPU_MSG_FUNCTION_GSP_RM_CONTROL: + { + rpc_gsp_rm_control_v03_00 *rpc_params = &rpc_message->gsp_rm_control_v03_00; + *data0 = rpc_params->cmd; + *data1 = rpc_params->paramsSize; + break; + } + case NV_VGPU_MSG_FUNCTION_GSP_RM_ALLOC: + { + rpc_gsp_rm_alloc_v03_00 *rpc_params = &rpc_message->gsp_rm_alloc_v03_00; + *data0 = rpc_params->hClass; + *data1 = rpc_params->paramsSize; + break; + } + case NV_VGPU_MSG_FUNCTION_FREE: + { + rpc_free_v03_00 *rpc_params = &rpc_message->free_v03_00; + *data0 = rpc_params->params.hObjectOld; + *data1 = rpc_params->params.hObjectParent; + break; + } + default: + { + *data0 = 0; + *data1 = 0; + break; + } + } +} + /*! * GSP client RM RPC send routine */ @@ -117,8 +177,10 @@ _kgspRpcSendMessage KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); NV_ASSERT(rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); - nvStatus = GspMsgQueueSendCommand(pRpc->pMessageQueueInfo, pGpu); + NV_ASSERT_OR_RETURN(!osIsGpuShutdown(pGpu), NV_ERR_GPU_IS_LOST); + + nvStatus = GspMsgQueueSendCommand(pRpc->pMessageQueueInfo, pGpu); if (nvStatus != NV_OK) { NV_PRINTF(LEVEL_ERROR, "GspMsgQueueSendCommand failed: 0x%x\n", nvStatus); @@ -128,6 +190,21 @@ _kgspRpcSendMessage // GSPRM TODO: Use this call to pass the actual index. kgspSetCmdQueueHead_HAL(pGpu, pKernelGsp, 0, 0); + // Add RPC history entry + { + NvU32 func = vgpu_rpc_message_header_v->function; + NvU32 entry; + + entry = pRpc->rpcHistoryCurrent = (pRpc->rpcHistoryCurrent + 1) % RPC_HISTORY_DEPTH; + + portMemSet(&pRpc->rpcHistory[entry], 0, sizeof(pRpc->rpcHistory[0])); + pRpc->rpcHistory[entry].function = func; + + _kgspGetActiveRpcDebugData(pRpc, func, + &pRpc->rpcHistory[entry].data[0], + &pRpc->rpcHistory[entry].data[1]); + } + return NV_OK; } @@ -257,13 +334,14 @@ _kgspRpcRCTriggered KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); CHID_MGR *pChidMgr; NvU32 status = NV_OK; + RM_ENGINE_TYPE rmEngineType = gpuGetRmEngineType(rpc_params->nv2080EngineType); // check if there's a PCI-E error pending either in device status or in AER krcCheckBusError_HAL(pGpu, pKernelRc); status = kfifoGetChidMgrFromType(pGpu, pKernelFifo, - ENGINE_INFO_TYPE_NV2080, - rpc_params->nv2080EngineType, + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, + (NvU32)rmEngineType, &pChidMgr); if (status != NV_OK) return status; @@ -277,7 +355,7 @@ _kgspRpcRCTriggered return krcErrorSendEventNotifications_HAL(pGpu, pKernelRc, pKernelChannel, - rpc_params->nv2080EngineType, // unused on kernel side + rmEngineType, // unused on kernel side rpc_params->exceptType, rpc_params->scope, rpc_params->partitionAttributionId); @@ -340,8 +418,18 @@ _kgspRpcGpuacctPerfmonUtilSamples NvU32 i; dest = pGpuInstanceInfo->pSamplesParams; - portMemSet(dest, 0, sizeof(*dest)); + if (dest == NULL) + { + // This RPC event can be received even when the RM hasn't fully started. + // For instance, CPU RM can take longer than usual to initialize, + // but the GSP RM sampling timer (a 1 sec interval) is about to tick. + // In that case, pSamplesParams can not even be allocated by that time. + // Ignore this RPC event if pSamplesParams has not been allocated yet. + // See GPUSWSEC-1543 for more info. + return; + } + portMemSet(dest, 0, sizeof(*dest)); dest->type = src->type; dest->bufSize = src->bufSize; dest->count = src->count; @@ -418,6 +506,93 @@ _kgspRpcPerfBridgelessInfoUpdate kPerfGpuBoostSyncBridgelessUpdateInfo(pGpu, rpc_params->bBridgeless); } +static void +_kgspRpcNvlinkInbandReceivedData256Callback +( + OBJGPU *pGpu, + OBJRPC *pRpc +) +{ + RPC_PARAMS(nvlink_inband_received_data_256, _v17_00); + + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v17_00 *dest = &rpc_params->params; + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + + NV_ASSERT(NV_OK == knvlinkInbandMsgCallbackDispatcher(pGpu, pKernelNvlink, dest->dataSize, dest->data)); +} + +static void +_kgspRpcNvlinkInbandReceivedData512Callback +( + OBJGPU *pGpu, + OBJRPC *pRpc +) +{ + RPC_PARAMS(nvlink_inband_received_data_512, _v17_00); + + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_512_PARAMS_v17_00 *dest = &rpc_params->params; + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + + NV_ASSERT(NV_OK == knvlinkInbandMsgCallbackDispatcher(pGpu, pKernelNvlink, dest->dataSize, dest->data)); +} + +static void +_kgspRpcNvlinkInbandReceivedData1024Callback +( + OBJGPU *pGpu, + OBJRPC *pRpc +) +{ + RPC_PARAMS(nvlink_inband_received_data_1024, _v17_00); + + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_1024_PARAMS_v17_00 *dest = &rpc_params->params; + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + + NV_ASSERT(NV_OK == knvlinkInbandMsgCallbackDispatcher(pGpu, pKernelNvlink, dest->dataSize, dest->data)); +} + +static void +_kgspRpcNvlinkInbandReceivedData2048Callback +( + OBJGPU *pGpu, + OBJRPC *pRpc +) +{ + RPC_PARAMS(nvlink_inband_received_data_2048, _v17_00); + + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_2048_PARAMS_v17_00 *dest = &rpc_params->params; + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + + NV_ASSERT(NV_OK == knvlinkInbandMsgCallbackDispatcher(pGpu, pKernelNvlink, dest->dataSize, dest->data)); +} + +static void +_kgspRpcNvlinkInbandReceivedData4096Callback +( + OBJGPU *pGpu, + OBJRPC *pRpc +) +{ + RPC_PARAMS(nvlink_inband_received_data_4096, _v17_00); + + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_4096_PARAMS_v17_00 *dest = &rpc_params->params; + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + + NV_ASSERT(NV_OK == knvlinkInbandMsgCallbackDispatcher(pGpu, pKernelNvlink, dest->dataSize, dest->data)); +} + +/*! + * CPU-RM: Receive GPU Degraded status from GSP + */ +static void +_kgspRpcEventIsGpuDegradedCallback +( + OBJGPU *pGpu, + OBJRPC *pRpc +) +{ +} + /*! * Receive MMU fault queue notification from GSP-RM. * @@ -510,6 +685,24 @@ _kgspRpcSemaphoreScheduleCallback( rpc_params->hEvent); } +static NV_STATUS +_kgspRpcTimedSemaphoreRelease( + OBJGPU *pGpu, + OBJRPC *pRpc +) +{ + RPC_PARAMS(timed_semaphore_release, _v01_00); + + return tsemaRelease_HAL(pGpu, + rpc_params->semaphoreVA, + rpc_params->notifierVA, + rpc_params->hVASpace, + rpc_params->releaseValue, + rpc_params->completionStatus, + rpc_params->hClient); +} + + static NV_STATUS _kgspRpcUcodeLibosPrint ( @@ -538,6 +731,22 @@ _kgspRpcUcodeLibosPrint } } +static NV_STATUS +_kgspRpcVgpuGspPluginTriggered +( + OBJGPU *pGpu, + OBJRPC *pRpc +) +{ + RPC_PARAMS(vgpu_gsp_plugin_triggered, _v17_00); + + if (!IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + return NV_ERR_NOT_SUPPORTED; + + gpuGspPluginTriggeredEvent(pGpu, rpc_params->gfid, rpc_params->notifyIndex); + return NV_OK; +} + static NV_STATUS _kgspRpcGspVgpuConfig ( @@ -545,7 +754,28 @@ _kgspRpcGspVgpuConfig OBJRPC *pRpc ) { - return NV_ERR_NOT_SUPPORTED; + RPC_PARAMS(vgpu_config_event, _v17_00); + + NV_ASSERT_OR_RETURN(rpc_params->notifyIndex < NVA081_NOTIFIERS_MAXCOUNT, + NV_ERR_INVALID_ARGUMENT); + + CliNotifyVgpuConfigEvent(pGpu, rpc_params->notifyIndex); + + return NV_OK; +} + +static NV_STATUS +_kgspRpcGspExtdevIntrService +( + OBJGPU *pGpu, + OBJRPC *pRpc +) +{ + RPC_PARAMS(extdev_intr_service, _v17_00); + + extdevGsyncService(pGpu, rpc_params->lossRegStatus, rpc_params->gainRegStatus, rpc_params->miscRegStatus, rpc_params->rmStatus); + + return NV_OK; } static NV_STATUS @@ -565,6 +795,45 @@ _kgspRpcRgLineIntr return NV_OK; } +static NV_STATUS +_kgspRpcEventPlatformRequestHandlerStateSyncCallback +( + OBJGPU* pGpu, + OBJRPC* pRpc +) +{ + return NV_OK; +} + +static +const char *_getRpcName +( + NvU32 id +) +{ + static const char *rpcName[] = + { + #define X(UNIT, a) #a, + #define E(a) #a, + #undef _RPC_GLOBAL_ENUMS_H_ + #include "vgpu/rpc_global_enums.h" + #undef X + #undef E + }; + + if (id < NV_VGPU_MSG_FUNCTION_NUM_FUNCTIONS) + { + return rpcName[id]; + } + else if ((id > NV_VGPU_MSG_EVENT_FIRST_EVENT) && (id < NV_VGPU_MSG_EVENT_NUM_EVENTS)) + { + NvU32 index = id - (NV_VGPU_MSG_EVENT_FIRST_EVENT - NV_VGPU_MSG_FUNCTION_NUM_FUNCTIONS) + 1; + return rpcName[index]; + } + + return "Unknown"; +} + /*! * GSP client process RPC events */ @@ -578,8 +847,8 @@ _kgspProcessRpcEvent rpc_message_header_v *pMsgHdr = RPC_HDR; NV_STATUS nvStatus = NV_OK; - NV_PRINTF(LEVEL_INFO, "received event %d: status: %d size: %d\n", - pMsgHdr->function, pMsgHdr->rpc_result, pMsgHdr->length); + NV_PRINTF(LEVEL_INFO, "received event: 0x%x (%s) status: 0x%x size: %d\n", + pMsgHdr->function, _getRpcName(pMsgHdr->function), pMsgHdr->rpc_result, pMsgHdr->length); switch(pMsgHdr->function) { @@ -627,6 +896,34 @@ _kgspProcessRpcEvent _kgspRpcSemaphoreScheduleCallback(pGpu, pRpc); break; + case NV_VGPU_MSG_EVENT_TIMED_SEMAPHORE_RELEASE: + _kgspRpcTimedSemaphoreRelease(pGpu, pRpc); + break; + + case NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_256: + _kgspRpcNvlinkInbandReceivedData256Callback(pGpu, pRpc); + break; + + case NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_512: + _kgspRpcNvlinkInbandReceivedData512Callback(pGpu, pRpc); + break; + + case NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_1024: + _kgspRpcNvlinkInbandReceivedData1024Callback(pGpu, pRpc); + break; + + case NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_2048: + _kgspRpcNvlinkInbandReceivedData2048Callback(pGpu, pRpc); + break; + + case NV_VGPU_MSG_EVENT_NVLINK_INBAND_RECEIVED_DATA_4096: + _kgspRpcNvlinkInbandReceivedData4096Callback(pGpu, pRpc); + break; + + case NV_VGPU_MSG_EVENT_NVLINK_IS_GPU_DEGRADED : + _kgspRpcEventIsGpuDegradedCallback(pGpu, pRpc); + break; + case NV_VGPU_MSG_EVENT_RG_LINE_INTR: _kgspRpcRgLineIntr(pGpu, pRpc); break; @@ -635,10 +932,22 @@ _kgspProcessRpcEvent nvStatus = _kgspRpcUcodeLibosPrint(pGpu, pRpc); break; + case NV_VGPU_MSG_EVENT_VGPU_GSP_PLUGIN_TRIGGERED: + nvStatus = _kgspRpcVgpuGspPluginTriggered(pGpu, pRpc); + break; + case NV_VGPU_MSG_EVENT_VGPU_CONFIG: nvStatus = _kgspRpcGspVgpuConfig(pGpu, pRpc); break; + case NV_VGPU_MSG_EVENT_EXTDEV_INTR_SERVICE: + nvStatus = _kgspRpcGspExtdevIntrService(pGpu, pRpc); + break; + + case NV_VGPU_MSG_EVENT_PFM_REQ_HNDLR_STATE_SYNC_CALLBACK: + nvStatus = _kgspRpcEventPlatformRequestHandlerStateSyncCallback(pGpu, pRpc); + break; + case NV_VGPU_MSG_EVENT_GSP_INIT_DONE: // Handled by _kgspRpcRecvPoll. default: // @@ -647,7 +956,8 @@ _kgspProcessRpcEvent // for the timeout has already happened, and returning an error here // causes subsequent messages to fail. So return NV_OK. // - NV_PRINTF(LEVEL_ERROR, "Unexpected RPC function 0x%x\n", pMsgHdr->function); + NV_PRINTF(LEVEL_ERROR, "Unexpected RPC event 0x%x (%s)\n", + pMsgHdr->function, _getRpcName(pMsgHdr->function)); break; } @@ -691,8 +1001,8 @@ _kgspRpcDrainOneEvent if (nvStatus != NV_OK) { NV_PRINTF(LEVEL_ERROR, - "Failed to process received event %d: status=0x%x\n", - pMsgHdr->function, nvStatus); + "Failed to process received event 0x%x (%s): status=0x%x\n", + pMsgHdr->function, _getRpcName(pMsgHdr->function), nvStatus); } } @@ -743,27 +1053,6 @@ _kgspRpcDrainEvents return nvStatus; } -static -const char *_getRpcName -( - NvU32 func -) -{ - static const char *rpcName[] = - { - #define X(UNIT, a) #a, - #define E(a) #a, - #undef _RPC_GLOBAL_ENUMS_H_ - #include "vgpu/rpc_global_enums.h" - #undef X - #undef E - }; - - NV_ASSERT_OR_RETURN(func < NV_VGPU_MSG_FUNCTION_NUM_FUNCTIONS, ""); - - return rpcName[func]; -} - /*! * Log Xid 119 - GSP RPC Timeout */ @@ -775,32 +1064,67 @@ _kgspLogXid119 NvU32 expectedFunc ) { - NvU32 data[2] = {0}; + KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); + NvU32 historyEntry = pRpc->rpcHistoryCurrent; + NvU32 activeData[2]; - NV_ASSERT(expectedFunc == vgpu_rpc_message_header_v->function); + if (!pKernelGsp->bXid119Printed) + { + NV_PRINTF(LEVEL_NOTICE, + "********************************* GSP Failure **********************************\n"); + } - if (expectedFunc == NV_VGPU_MSG_FUNCTION_GSP_RM_CONTROL) - { - rpc_gsp_rm_control_v03_00 *rpc_params = &rpc_message->gsp_rm_control_v03_00; - data[0] = rpc_params->cmd; - data[1] = rpc_params->paramsSize; - } - else - if (expectedFunc == NV_VGPU_MSG_FUNCTION_GSP_RM_ALLOC) - { - rpc_gsp_rm_alloc_v03_00 *rpc_params = &rpc_message->gsp_rm_alloc_v03_00; - data[0] = rpc_params->hClass; - data[1] = rpc_params->paramsSize; - } + NV_ASSERT(expectedFunc == pRpc->rpcHistory[historyEntry].function); + + _kgspGetActiveRpcDebugData(pRpc, expectedFunc, + &activeData[0], &activeData[1]); nvErrorLog_va((void*)pGpu, GSP_RPC_TIMEOUT, - "Timeout waiting for RPC from GSP! Expected function %s (0x%x 0x%x).", + "Timeout waiting for RPC from GSP! Expected function %d (%s) (0x%x 0x%x).", + expectedFunc, _getRpcName(expectedFunc), - data[0], data[1]); -#if defined(DEVELOP) || defined(DEBUG) - // dump the stack - osAssertFailed(); -#endif + pRpc->rpcHistory[historyEntry].data[0], + pRpc->rpcHistory[historyEntry].data[1]); + + if (!pKernelGsp->bXid119Printed) + { + NvU32 historyIndex; + + if ((expectedFunc != vgpu_rpc_message_header_v->function) || + (pRpc->rpcHistory[historyEntry].data[0] != activeData[0]) || + (pRpc->rpcHistory[historyEntry].data[1] != activeData[1])) + { + NV_PRINTF(LEVEL_ERROR, + "Current RPC function %d (%s) or data (0x%x 0x%x) does not match expected function %d (%s) or data (0x%x 0x%x).\n", + vgpu_rpc_message_header_v->function, _getRpcName(vgpu_rpc_message_header_v->function), + activeData[0], activeData[1], + expectedFunc, _getRpcName(expectedFunc), + pRpc->rpcHistory[historyEntry].data[0], + pRpc->rpcHistory[historyEntry].data[1]); + } + + NV_PRINTF(LEVEL_ERROR, "RPC history (CPU -> GSP):\n"); + NV_PRINTF(LEVEL_ERROR, "\tentry\tfunc\t\t\t\tdata\n"); + for (historyIndex = 0; historyIndex < RPC_HISTORY_DEPTH; historyIndex++) + { + historyEntry = (pRpc->rpcHistoryCurrent + RPC_HISTORY_DEPTH - historyIndex) % RPC_HISTORY_DEPTH; + NV_PRINTF(LEVEL_ERROR, "\t%c%-2d\t%2d %-22s\t0x%08x 0x%08x\n", + ((historyIndex == 0) ? ' ' : '-'), + historyIndex, + pRpc->rpcHistory[historyEntry].function, + _getRpcName(pRpc->rpcHistory[historyEntry].function), + pRpc->rpcHistory[historyEntry].data[0], + pRpc->rpcHistory[historyEntry].data[1]); + } + + NV_PRINTF(LEVEL_ERROR, "Dumping stack:\n"); + osAssertFailed(); + + NV_PRINTF(LEVEL_NOTICE, + "********************************************************************************\n"); + } + + pKernelGsp->bXid119Printed = NV_TRUE; } /*! @@ -821,6 +1145,19 @@ _kgspRpcRecvPoll NvBool bSlowGspRpc = IS_EMULATION(pGpu) || IS_SIMULATION(pGpu); // + // We do not allow recursive polling. This can happen if e.g. + // 1. CPU-RM issues RPC-A to GSP and polls waiting for it to finish + // 2. While servicing RPC-A, GSP emits an async event back to CPU-RM + // 3. CPU-RM services the async event and sends another synchronous RPC-B + // 4. RPC-A response will come first, but CPU-RM is now waiting on RPC-B + // + // We don't have a good way to handle this and should just be deferring the + // second RPC until the first one is done, via e.g. osQueueWorkItem(). + // This assert is meant to catch and loudly fail such cases. + // + NV_ASSERT_OR_RETURN(!pKernelGsp->bPollingForRpcResponse, NV_ERR_INVALID_STATE); + pKernelGsp->bPollingForRpcResponse = NV_TRUE; + // GSP-RM init in emulation/simulation environment is extremely slow, // so need to increment timeout. // Apply the timeout extension to other RPCs as well, mostly so that @@ -854,12 +1191,13 @@ _kgspRpcRecvPoll switch (nvStatus) { case NV_WARN_MORE_PROCESSING_REQUIRED: - return NV_OK; + nvStatus = NV_OK; + goto done; case NV_OK: // Check timeout and continue outer loop. break; default: - return nvStatus; + goto done; } osSpinLoop(); @@ -868,10 +1206,19 @@ _kgspRpcRecvPoll if (nvStatus == NV_ERR_TIMEOUT) { _kgspLogXid119(pGpu, pRpc, expectedFunc); - return nvStatus; + goto done; + } + + if (osIsGpuShutdown(pGpu)) + { + nvStatus = NV_ERR_GPU_IS_LOST; + goto done; } } +done: + pKernelGsp->bPollingForRpcResponse = NV_FALSE; + if (bSlowGspRpc) { // Avoid cumulative timeout due to slow RPC @@ -902,6 +1249,9 @@ _kgspInitRpcInfrastructure OBJRPC *pRpc = pKernelGsp->pRpc; + portMemSet(&pRpc->rpcHistory, 0, sizeof(pRpc->rpcHistory)); + pRpc->rpcHistoryCurrent = RPC_HISTORY_DEPTH - 1; + pRpc->pMessageQueueInfo = NULL; nvStatus = GspMsgQueueInit(pGpu, &pRpc->pMessageQueueInfo); @@ -1031,13 +1381,16 @@ _kgspInitLibosLoggingStructures const char *szMemoryId; const char *szPrefix; NvU32 size; + const char *elfSectionName; } logInitValues[] = { - {"LOGINIT", "INIT", 0x10000}, // 64KB for stack traces + {"LOGINIT", "INIT", 0x10000, ".fwlogging_init"}, // 64KB for stack traces #if defined(DEVELOP) || defined(DEBUG) - {"LOGRM", "RM", 0x40000} // 256KB RM debug log on develop/debug builds + {"LOGVGPU", "VGPU", 0x40000, ".fwlogging_vgpu"}, // 256KB VGPU debug log on develop/debug builds + {"LOGRM", "RM", 0x40000, ".fwlogging_rm"} // 256KB RM debug log on develop/debug builds #else - {"LOGRM", "RM", 0x10000} // 64KB RM debug log on release builds + {"LOGVGPU", "VGPU", 0x10000, ".fwlogging_vgpu"}, // 64KB VGPU debug log on release builds + {"LOGRM", "RM", 0x10000, ".fwlogging_rm"} // 64KB RM debug log on release builds #endif }; ct_assert(NV_ARRAY_ELEMENTS(logInitValues) <= LIBOS_LOG_MAX_LOGS); @@ -1092,27 +1445,53 @@ _kgspInitLibosLoggingStructures pLog->id8 = _kgspGenerateInitArgId(logInitValues[idx].szMemoryId); - libosLogAddLog(&pKernelGsp->logDecode, + libosLogAddLogEx(&pKernelGsp->logDecode, pLog->pTaskLogBuffer, memdescGetSize(pLog->pTaskLogDescriptor), pGpu->gpuInstance, - logInitValues[idx].szPrefix); + (gpuGetChipArch(pGpu) >> GPU_ARCH_SHIFT), + gpuGetChipImpl(pGpu), + logInitValues[idx].szPrefix, + logInitValues[idx].elfSectionName); } // Setup symbol decoder if (pGspFw->pLogElf) { - pKernelGsp->pLogElf = portMemAllocNonPaged(pGspFw->logElfSize); + const void *pLogData = NULL; + NvU64 logSize = 0; + + NV_ASSERT_OK_OR_GOTO( + nvStatus, + _kgspFwContainerVerifyVersion(pGpu, pKernelGsp, + pGspFw->pLogElf, + pGspFw->logElfSize, + "GSP firmware log"), + error_cleanup); + + NV_ASSERT_OK_OR_GOTO( + nvStatus, + _kgspFwContainerGetSection(pGpu, pKernelGsp, + pGspFw->pLogElf, + pGspFw->logElfSize, + GSP_LOGGING_SECTION_NAME, + &pLogData, + &logSize), + error_cleanup); + + pKernelGsp->pLogElf = portMemAllocNonPaged(logSize); if (pKernelGsp->pLogElf == NULL) { NV_PRINTF(LEVEL_ERROR, "Failed to allocate memory for log elf"); nvStatus = NV_ERR_NO_MEMORY; goto error_cleanup; } - portMemCopy(pKernelGsp->pLogElf, pGspFw->logElfSize, pGspFw->pLogElf, pGspFw->logElfSize); + portMemCopy(pKernelGsp->pLogElf, logSize, pLogData, logSize); if (pKernelGsp->pLogElf) - libosLogInit(&pKernelGsp->logDecode, pKernelGsp->pLogElf); + { + libosLogInit(&pKernelGsp->logDecode, pKernelGsp->pLogElf, logSize); + } } error_cleanup: @@ -1434,6 +1813,7 @@ done: { rmGpuGroupLockRelease(gpusLockedMask, GPUS_LOCK_FLAGS_NONE); } + return status; } @@ -1567,8 +1947,16 @@ kgspDumpGspLogs_IMPL NvBool bSyncNvLog ) { + if (!IS_GSP_CLIENT(pGpu)) + { + return; + } + if (pKernelGsp->bInInit || pKernelGsp->pLogElf || bSyncNvLog) + { libosExtractLogs(&pKernelGsp->logDecode, bSyncNvLog); + } + } /*! @@ -1605,6 +1993,8 @@ kgspPopulateGspRmInitArgs_IMPL pSrInitArgs->oldLevel = pGspInitArgs->oldLevel; pSrInitArgs->flags = pGspInitArgs->flags; } + + pGspArgs->gpuInstance = pGpu->gpuInstance; } /*! @@ -1722,7 +2112,7 @@ _kgspFreeBootBinaryImage } static NV_STATUS -_kgspPrepareGspRmBinaryImage +_kgspCreateSignatureMemdesc ( OBJGPU *pGpu, KernelGsp *pKernelGsp, @@ -1730,20 +2120,190 @@ _kgspPrepareGspRmBinaryImage ) { NV_STATUS status = NV_OK; + NvU8 *pSignatureVa = NULL; - // Get signature from gsp.bin and zero out the signature sections - status = - _kgspGetAndClearSignatureFromBinary(pGpu, pKernelGsp, - pGspFw, &pKernelGsp->pSignatureMemdesc); + // NOTE: align to 256 because that's the alignment needed for Booter DMA + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + memdescCreate(&pKernelGsp->pSignatureMemdesc, pGpu, + NV_ALIGN_UP(pGspFw->signatureSize, 256), 256, + NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, MEMDESC_FLAGS_NONE)); + + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + memdescAlloc(pKernelGsp->pSignatureMemdesc), fail_create); + + pSignatureVa = memdescMapInternal(pGpu, pKernelGsp->pSignatureMemdesc, TRANSFER_FLAGS_NONE); + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + (pSignatureVa != NULL) ? NV_OK : NV_ERR_INSUFFICIENT_RESOURCES, + fail_alloc); + + portMemCopy(pSignatureVa, memdescGetSize(pKernelGsp->pSignatureMemdesc), + pGspFw->pSignatureData, pGspFw->signatureSize); + + memdescUnmapInternal(pGpu, pKernelGsp->pSignatureMemdesc, 0); + pSignatureVa = NULL; + + return status; + +fail_alloc: + memdescFree(pKernelGsp->pSignatureMemdesc); + +fail_create: + memdescDestroy(pKernelGsp->pSignatureMemdesc); + pKernelGsp->pSignatureMemdesc = NULL; + + return status; +} + +/*! + * Verify that the version embedded in the .fwversion section of the ELF given + * by pElfData and elfDataSize matches our NV_VERSION_STRING. + */ +static NV_STATUS +_kgspFwContainerVerifyVersion +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp, + const void *pElfData, + NvU64 elfDataSize, + const char *pNameInMsg +) +{ + const char *pFwversion; + NvU64 fwversionSize; + NvU64 expectedVersionLength = portStringLength(NV_VERSION_STRING); - if ((status != NV_OK) && (status != NV_ERR_NOT_SUPPORTED)) { - return status; + const void *pFwversionRaw; + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + _kgspFwContainerGetSection(pGpu, pKernelGsp, + pElfData, + elfDataSize, + GSP_VERSION_SECTION_NAME, + &pFwversionRaw, + &fwversionSize)); + + pFwversion = (const char *) pFwversionRaw; } - NV_ASSERT_OK_OR_RETURN( + // Check that text in .fwversion section of ELF matches our NV_VERSION_STRING + if ((fwversionSize != expectedVersionLength + 1) || + (portStringCompare(pFwversion, NV_VERSION_STRING, expectedVersionLength) != 0)) + { + // Sanity check .fwversion before attempting to print it in the error message + if ((fwversionSize > 0) && + (fwversionSize < 64) && + (pFwversion[fwversionSize - 1] == '\0')) + { + NV_PRINTF(LEVEL_ERROR, "%s version mismatch: got version %s, expected version %s\n", + pNameInMsg, pFwversion, NV_VERSION_STRING); + } + else + { + NV_PRINTF(LEVEL_ERROR, "%s version unknown or malformed, expected version %s\n", + pNameInMsg, NV_VERSION_STRING); + } + return NV_ERR_INVALID_DATA; + } + + return NV_OK; +} + +/*! + * Get the name of the section corresponding to the given section name + * prefix and the current chip. + */ +static NV_STATUS +_kgspGetSectionNameForPrefix +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp, + char *pSectionNameBuf, // out + NvLength sectionNameBufSize, + const char *pSectionPrefix +) +{ + NvLength sectionPrefixLength; + + nv_firmware_chip_family_t chipFamily; + const char *pChipFamilyName; + NvLength chipFamilyNameLength; + + NvLength totalSize; + + NV_ASSERT_OR_RETURN(pSectionNameBuf != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(sectionNameBufSize > 0, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pSectionPrefix != NULL, NV_ERR_INVALID_ARGUMENT); + + chipFamily = nv_firmware_get_chip_family(gpuGetChipArch(pGpu), + gpuGetChipImpl(pGpu)); + NV_ASSERT_OR_RETURN(chipFamily != NV_FIRMWARE_CHIP_FAMILY_NULL, + NV_ERR_INVALID_STATE); + + pChipFamilyName = nv_firmware_chip_family_to_string(chipFamily); + NV_ASSERT_OR_RETURN(pChipFamilyName != NULL, NV_ERR_INVALID_STATE); + + sectionPrefixLength = portStringLength(pSectionPrefix); + chipFamilyNameLength = portStringLength(pChipFamilyName); + + totalSize = sectionPrefixLength + chipFamilyNameLength + 1; + NV_ASSERT_OR_RETURN(sectionNameBufSize >= sectionPrefixLength + 1, + NV_ERR_BUFFER_TOO_SMALL); + NV_ASSERT_OR_RETURN(sectionNameBufSize >= totalSize, + NV_ERR_BUFFER_TOO_SMALL); + + portStringCopy(pSectionNameBuf, sectionNameBufSize, + pSectionPrefix, sectionPrefixLength + 1); + portStringCat(pSectionNameBuf, sectionNameBufSize, + pChipFamilyName, chipFamilyNameLength + 1); + + return NV_OK; +} + +static NV_STATUS +_kgspPrepareGspRmBinaryImage +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp, + GSP_FIRMWARE *pGspFw +) +{ + char signatureSectionName[32]; + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + _kgspFwContainerVerifyVersion(pGpu, pKernelGsp, + pGspFw->pBuf, + pGspFw->size, + "GSP firmware image")); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + _kgspFwContainerGetSection(pGpu, pKernelGsp, + pGspFw->pBuf, + pGspFw->size, + GSP_IMAGE_SECTION_NAME, + &pGspFw->pImageData, + &pGspFw->imageSize)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + _kgspGetSectionNameForPrefix(pGpu, pKernelGsp, + signatureSectionName, sizeof(signatureSectionName), + kgspGetSignatureSectionNamePrefix_HAL(pGpu, pKernelGsp))); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + _kgspFwContainerGetSection(pGpu, pKernelGsp, + pGspFw->pBuf, + pGspFw->size, + signatureSectionName, + &pGspFw->pSignatureData, + &pGspFw->signatureSize)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + _kgspCreateSignatureMemdesc(pGpu, pKernelGsp, + pGspFw)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, _kgspCreateRadix3(pGpu, &pKernelGsp->pGspUCodeRadix3Descriptor, - NULL, pGspFw->pBuf, pGspFw->size)); + NULL, pGspFw->pImageData, pGspFw->imageSize)); return NV_OK; } @@ -1898,60 +2458,44 @@ error_ret: return status; } -/*! - * Process gsp.bin elf buffer and extract the corresponding signature. - * - * All signatures will also be cleared (set to 0) because the binary was signed - * before the signatures were inserted. - * - * @param[in] pGpu GPU object pointer - * @param[in] pKernelGsp KernelGsp object pointer - * @param[inout] pGspFw GSP firmware structure pointer, sections - * whose names start with the signature - * section name prefix will be cleared - * @param[out] ppSignatureMemdesc Memdesc to store the signature. If - * return code is NV_OK, the memdesc must - * be freed by caller - */ static NV_STATUS -_kgspGetAndClearSignatureFromBinary +_kgspFwContainerGetSection ( OBJGPU *pGpu, KernelGsp *pKernelGsp, - GSP_FIRMWARE *pGspFw, - MEMORY_DESCRIPTOR **ppSignatureMemdesc + const void *pElfData, + NvU64 elfDataSize, + const char *pSectionName, + const void **ppSectionData, + NvU64 *pSectionSize ) { - NV_STATUS status = NV_OK; - NvU8 *pGspBuf = (NvU8*) pGspFw->pBuf; - const elf64_header *pElfHeader; - const elf64_shdr *pElfSectionHeader; + const NvU8 *pGspBuf = pElfData; + const LibosElf64Header *pElfHeader; + const LibosElf64SectionHeader *pElfSectionHeader; NvU64 elfSectionHeaderTableLength; NvU64 elfSectionHeaderMaxIdx; NvU64 elfSectionNamesTableOffset; NvU64 elfSectionNamesTableSize; NvU64 elfSectionNamesTableMaxIdx; - NvU64 elfSectionMaxIdx; static const NvU32 elfMagicNumber = 0x464C457F; static const NvU8 elfClass64 = 0x2; static const NvU8 elfLittleEndian = 0x1; - const char *pSignatureSectionName = kgspGetSignatureSectionName_HAL(pGpu, pKernelGsp); - NvLength signatureSectionNameLength; - NvLength signaturePrefixLength; - NvU8 *pSignatureVa = NULL; + const char *pCurrentSectionName; + NvLength sectionNameLength; NvS16 idx; - NvBool signatureSectionFound = NV_FALSE; - NV_ASSERT_OR_RETURN(ppSignatureMemdesc != NULL, NV_ERR_INVALID_PARAMETER); - NV_CHECK_OR_RETURN(LEVEL_ERROR, pSignatureSectionName != NULL, NV_ERR_NOT_SUPPORTED); - NV_CHECK_OR_RETURN(LEVEL_ERROR, pGspFw->size >= sizeof(elf64_header), NV_ERR_INVALID_DATA); + NV_CHECK_OR_RETURN(LEVEL_ERROR, pElfData != NULL, NV_ERR_INVALID_ARGUMENT); + NV_CHECK_OR_RETURN(LEVEL_ERROR, elfDataSize > 0, NV_ERR_INVALID_ARGUMENT); + NV_CHECK_OR_RETURN(LEVEL_ERROR, pSectionName != NULL, NV_ERR_INVALID_ARGUMENT); + NV_CHECK_OR_RETURN(LEVEL_ERROR, ppSectionData != NULL, NV_ERR_INVALID_ARGUMENT); + NV_CHECK_OR_RETURN(LEVEL_ERROR, pSectionSize != NULL, NV_ERR_INVALID_ARGUMENT); - signatureSectionNameLength = portStringLength(pSignatureSectionName); - signaturePrefixLength = portStringLength(SIGNATURE_SECTION_NAME_PREFIX); + NV_CHECK_OR_RETURN(LEVEL_ERROR, elfDataSize >= sizeof(LibosElf64Header), NV_ERR_INVALID_DATA); - *ppSignatureMemdesc = NULL; + sectionNameLength = portStringLength(pSectionName); - pElfHeader = (const elf64_header*) pGspBuf; + pElfHeader = (const LibosElf64Header*) pGspBuf; // Check for the elf identifier at the beginning of the file NV_CHECK_OR_RETURN(LEVEL_ERROR, *(NvU32*)&pElfHeader->ident == elfMagicNumber, NV_ERR_INVALID_DATA); @@ -1961,83 +2505,55 @@ _kgspGetAndClearSignatureFromBinary NV_CHECK_OR_RETURN(LEVEL_ERROR, pElfHeader->ident[4] == elfClass64, NV_ERR_INVALID_DATA); // Make sure that the elf section header table is valid - NV_CHECK_OR_RETURN(LEVEL_ERROR, pElfHeader->shentsize == sizeof(elf64_shdr), NV_ERR_INVALID_DATA); + NV_CHECK_OR_RETURN(LEVEL_ERROR, pElfHeader->shentsize == sizeof(LibosElf64SectionHeader), NV_ERR_INVALID_DATA); NV_CHECK_OR_RETURN(LEVEL_ERROR, portSafeMulU64(pElfHeader->shentsize, pElfHeader->shnum, &elfSectionHeaderTableLength), NV_ERR_INVALID_DATA); NV_CHECK_OR_RETURN(LEVEL_ERROR, portSafeAddU64(pElfHeader->shoff, elfSectionHeaderTableLength - 1, &elfSectionHeaderMaxIdx), NV_ERR_INVALID_DATA); - NV_CHECK_OR_RETURN(LEVEL_ERROR, pGspFw->size >= elfSectionHeaderMaxIdx, NV_ERR_INVALID_DATA); + NV_CHECK_OR_RETURN(LEVEL_ERROR, elfDataSize >= elfSectionHeaderMaxIdx, NV_ERR_INVALID_DATA); NV_CHECK_OR_RETURN(LEVEL_ERROR, pElfHeader->shstrndx <= pElfHeader->shnum, NV_ERR_INVALID_DATA); // Get the offset and size of the table that holds the section names and make sure they are valid - pElfSectionHeader = (const elf64_shdr*) &pGspBuf[pElfHeader->shoff + (pElfHeader->shstrndx * pElfHeader->shentsize)]; + pElfSectionHeader = (const LibosElf64SectionHeader*) &pGspBuf[pElfHeader->shoff + (pElfHeader->shstrndx * pElfHeader->shentsize)]; elfSectionNamesTableOffset = pElfSectionHeader->offset; elfSectionNamesTableSize = pElfSectionHeader->size; NV_CHECK_OR_RETURN(LEVEL_ERROR, portSafeAddU64(elfSectionNamesTableOffset, elfSectionNamesTableSize - 1, &elfSectionNamesTableMaxIdx), NV_ERR_INVALID_DATA); - NV_CHECK_OR_RETURN(LEVEL_ERROR, pGspFw->size >= elfSectionNamesTableMaxIdx, NV_ERR_INVALID_DATA); + NV_CHECK_OR_RETURN(LEVEL_ERROR, elfDataSize >= elfSectionNamesTableMaxIdx, NV_ERR_INVALID_DATA); // Iterate through all of the section headers to find the signatures - pElfSectionHeader = (const elf64_shdr*) &pGspBuf[elfSectionHeaderMaxIdx + 1 - sizeof(*pElfSectionHeader)]; + pElfSectionHeader = (const LibosElf64SectionHeader*) &pGspBuf[elfSectionHeaderMaxIdx + 1 - sizeof(*pElfSectionHeader)]; for (idx = pElfHeader->shnum - 1; idx >= 0; idx--, pElfSectionHeader--) { + NvU64 currentSectionNameMaxLength; + NvU64 elfSectionMaxIdx; + // Make sure the header name index fits within the section names table - NV_CHECK_OR_GOTO(LEVEL_ERROR, elfSectionNamesTableSize - 1 >= pElfSectionHeader->name, fail_invalid_data); + NV_CHECK_OR_RETURN(LEVEL_ERROR, elfSectionNamesTableSize - 1 >= pElfSectionHeader->name, NV_ERR_INVALID_DATA); + currentSectionNameMaxLength = elfSectionNamesTableSize - pElfSectionHeader->name - 1; + pCurrentSectionName = (const char *) &pGspBuf[elfSectionNamesTableOffset + pElfSectionHeader->name]; - // Check whether the section name matches the signature prefix. All signature binaries need to be - // cleared from the elf because the gsp binary was signed with them empty - if (portStringCompare((const char *)&pGspBuf[elfSectionNamesTableOffset + pElfSectionHeader->name], - SIGNATURE_SECTION_NAME_PREFIX, - signaturePrefixLength) == 0) + // Make sure the elf section size and offset are valid + if (pElfSectionHeader->size > 0) { - signatureSectionFound = NV_TRUE; - - // Make sure the elf section size and offset are valid - NV_CHECK_OR_GOTO(LEVEL_ERROR, portSafeAddU64(pElfSectionHeader->offset, pElfSectionHeader->size - 1, &elfSectionMaxIdx), fail_invalid_data); - NV_CHECK_OR_GOTO(LEVEL_ERROR, pGspFw->size >= elfSectionMaxIdx, fail_invalid_data); - - // Check whether the section name matches the current chip signature - if (portStringCompare((const char *)&pGspBuf[elfSectionNamesTableOffset + pElfSectionHeader->name + signaturePrefixLength], - pSignatureSectionName + signaturePrefixLength, - signatureSectionNameLength - signaturePrefixLength + 1) == 0) - { - // NOTE: align to 256 because that's the alignment needed for Booter DMA - NV_ASSERT_OK_OR_GOTO(status, - memdescCreate(ppSignatureMemdesc, pGpu, - NV_ALIGN_UP(pElfSectionHeader->size, 256), 256, - NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, MEMDESC_FLAGS_NONE), - fail); - NV_ASSERT_OK_OR_GOTO(status, memdescAlloc(*ppSignatureMemdesc), fail); - pSignatureVa = memdescMapInternal(pGpu, *ppSignatureMemdesc, TRANSFER_FLAGS_NONE); - if (pSignatureVa == NULL) - { - status = NV_ERR_INSUFFICIENT_RESOURCES; - goto fail; - } - portMemCopy(pSignatureVa, memdescGetSize(*ppSignatureMemdesc), - &pGspBuf[pElfSectionHeader->offset], pElfSectionHeader->size); - memdescUnmapInternal(pGpu, *ppSignatureMemdesc, 0); - pSignatureVa = NULL; - } - - // Clear the signature binary - portMemSet(&pGspBuf[pElfSectionHeader->offset], 0, pElfSectionHeader->size); + NV_CHECK_OR_RETURN(LEVEL_ERROR, portSafeAddU64(pElfSectionHeader->offset, pElfSectionHeader->size - 1, &elfSectionMaxIdx), NV_ERR_INVALID_DATA); } - // We assume that all signature sections are grouped together sequentially - else if (signatureSectionFound == NV_TRUE) + else { - break; + elfSectionMaxIdx = pElfSectionHeader->offset; + } + NV_CHECK_OR_RETURN(LEVEL_ERROR, elfDataSize >= elfSectionMaxIdx, NV_ERR_INVALID_DATA); + + // Check whether the section name matches the expected section name + if ((sectionNameLength <= currentSectionNameMaxLength) && + (portStringCompare(pCurrentSectionName, pSectionName, sectionNameLength) == 0) && + (pCurrentSectionName[sectionNameLength] == '\0')) + { + *ppSectionData = &pGspBuf[pElfSectionHeader->offset]; + *pSectionSize = pElfSectionHeader->size; + + return NV_OK; } } - return status; - -fail_invalid_data: - status = NV_ERR_INVALID_DATA; -fail: - if (pSignatureVa != NULL) - memdescUnmapInternal(pGpu, *ppSignatureMemdesc, 0); - memdescFree(*ppSignatureMemdesc); - memdescDestroy(*ppSignatureMemdesc); - *ppSignatureMemdesc = NULL; - return status; + return NV_ERR_OBJECT_NOT_FOUND; } /*! diff --git a/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c b/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c index 76f53f618..fd8ff0c7a 100644 --- a/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c +++ b/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c @@ -50,6 +50,7 @@ #include "gpu/gsp/message_queue_priv.h" #include "msgq/msgq_priv.h" #include "gpu/gsp/kernel_gsp.h" +#include "nvrm_registry.h" ct_assert(GSP_MSG_QUEUE_HEADER_SIZE > sizeof(msgqTxHeader) + sizeof(msgqRxHeader)); @@ -64,11 +65,11 @@ _getMsgQueueParams NvU32 numPtes; const NvLength defaultCommandQueueSize = 0x40000; // 256 KB const NvLength defaultStatusQueueSize = 0x40000; // 256 KB + NvU32 regStatusQueueSize; if (IS_SILICON(pGpu)) { pMQI->commandQueueSize = defaultCommandQueueSize; - pMQI->statusQueueSize = defaultStatusQueueSize; } else { @@ -77,6 +78,18 @@ _getMsgQueueParams // the VBIOS image via RPC. // pMQI->commandQueueSize = defaultCommandQueueSize * 6; + } + + // Check for status queue size overried + if (osReadRegistryDword(pGpu, NV_REG_STR_RM_GSP_STATUS_QUEUE_SIZE, ®StatusQueueSize) == NV_OK) + { + regStatusQueueSize *= 1024; // to bytes + regStatusQueueSize = NV_MAX(GSP_MSG_QUEUE_ELEMENT_SIZE_MAX, regStatusQueueSize); + regStatusQueueSize = NV_ALIGN_UP(regStatusQueueSize, 1 << GSP_MSG_QUEUE_ALIGN); + pMQI->statusQueueSize = regStatusQueueSize; + } + else + { pMQI->statusQueueSize = defaultStatusQueueSize; } diff --git a/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_sriov_tu102.c b/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_sriov_tu102.c new file mode 100644 index 000000000..c5783e898 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_sriov_tu102.c @@ -0,0 +1,125 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "core/core.h" +#include "kernel/gpu/intr/intr.h" +#include "gpu/gpu.h" +#include "os/os.h" + +#include "published/turing/tu102/dev_ctrl.h" +#include "published/turing/tu102/dev_vm.h" + +// +// Turing HAL routines required for hypervisor/guest support +// + +/*! + * @brief Enables virtual interrupts to be sent from a virtual function with + * the specified GFID. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pIntr Intr pointer + * @param[in] gfid GFID assigned to the virtual function + */ +NV_STATUS +intrEnableVirtualIntrLeaf_TU102 +( + OBJGPU *pGpu, + Intr *pIntr, + NvU32 gfid +) +{ + GFID_ALLOC_STATUS gfidState; + NvU32 reg = gfid / (DRF_SIZE(NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET_VALUE)); + NvU32 bit = gfid % (DRF_SIZE(NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET_VALUE)); + + NV_ASSERT_OK_OR_RETURN(gpuGetGfidState(pGpu, gfid, &gfidState)); + if (gfidState == GFID_FREE) + { + NV_PRINTF(LEVEL_ERROR, "Invalid GFID 0x%x\n", gfid); + DBG_BREAKPOINT(); + return NV_ERR_INVALID_ARGUMENT; + } + + if (reg >= NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET__SIZE_1) + { + NV_PRINTF(LEVEL_ERROR, "Computed register index exceeds valid available " + "range of NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET. reg idx = 0x%x\n", reg); + DBG_BREAKPOINT(); + return NV_ERR_INVALID_ARGUMENT; + } + + GPU_REG_WR32(pGpu, NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET(reg), + (NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET_VECTOR_ENABLE << bit)); + return NV_OK; +} + +/*! + * @brief Services virtual interrupts, i.e. interrupts triggered by PRIV_DOORBELL + * writes from virtual functions + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pIntr Intr pointer + */ +void +intrServiceVirtual_TU102 +( + OBJGPU *pGpu, + Intr *pIntr +) +{ + NvU32 i; + + // For now, servicing only involves clearing interrupts from all GFIDs + for (i = 0; i < NV_CTRL_VIRTUAL_INTR_LEAF__SIZE_1; i++) + { + NvU32 val = GPU_REG_RD32(pGpu, NV_CTRL_VIRTUAL_INTR_LEAF(i)); + if (val != 0) + { + GPU_REG_WR32(pGpu, NV_CTRL_VIRTUAL_INTR_LEAF(i), val); + } + } +} + +/*! + * @brief Trigger the PRIV doorbell + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pIntr Intr pointer + * @param[in] handle Handle to pass along with the interrupt + */ +NV_STATUS +intrTriggerPrivDoorbell_TU102 +( + OBJGPU *pGpu, + Intr *pIntr, + NvU32 handle +) +{ + if (!gpuIsSriovEnabled(pGpu)) + return NV_ERR_NOT_SUPPORTED; + + GPU_VREG_WR32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_DOORBELL, handle); + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_tu102.c b/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_tu102.c index 5e8d0bd9c..36742ebe9 100644 --- a/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_tu102.c +++ b/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_tu102.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -203,7 +203,6 @@ intrCacheIntrFields_TU102 ) { NV_STATUS status = NV_OK; - OBJDISP *pDisp = GPU_GET_DISP(pGpu); NvU32 leafEnHi, leafEnLo; NvU32 uvmSharedLeafIdxStart = NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(NV_CPU_INTR_UVM_SHARED_SUBTREE_START); NvU32 uvmSharedLeafIdxEnd = NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(NV_CPU_INTR_UVM_SHARED_SUBTREE_LAST); @@ -229,12 +228,21 @@ intrCacheIntrFields_TU102 // for (i = NV_CPU_INTR_STALL_SUBTREE_START; i <= stallSubtreeLast; i++) { - pIntr->cpuTopEnMask |= NVBIT(i); + pIntr->intrTopEnMask |= NVBIT(i); } + OBJDISP *pDisp = GPU_GET_DISP(pGpu); + // Cache client owned, shared interrupt, and display vectors for ease of use later - pIntr->replayableFaultIntrVector = intrGetVectorFromEngineId(pGpu, pIntr, MC_ENGINE_IDX_REPLAYABLE_FAULT, NV_FALSE); pIntr->accessCntrIntrVector = intrGetVectorFromEngineId(pGpu, pIntr, MC_ENGINE_IDX_ACCESS_CNTR, NV_FALSE); + if (!gpuIsCCFeatureEnabled(pGpu)) + { + pIntr->replayableFaultIntrVector = intrGetVectorFromEngineId(pGpu, pIntr, MC_ENGINE_IDX_REPLAYABLE_FAULT, NV_FALSE); + } + else + { + pIntr->replayableFaultIntrVector = NV_INTR_VECTOR_INVALID; + } if (pDisp != NULL) { pIntr->displayIntrVector = intrGetVectorFromEngineId(pGpu, pIntr, MC_ENGINE_IDX_DISP, NV_FALSE); @@ -249,14 +257,17 @@ intrCacheIntrFields_TU102 // now so we don't have to check later in latency critical paths where this // is assumed to be true) // - if (NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(pIntr->replayableFaultIntrVector) != NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(pIntr->accessCntrIntrVector)) + if (pIntr->replayableFaultIntrVector != NV_INTR_VECTOR_INVALID && pIntr->accessCntrIntrVector != NV_INTR_VECTOR_INVALID) { - NV_PRINTF(LEVEL_ERROR, "UVM interrupt vectors for replayable fault 0x%x " - "and access counter 0x%x are in different CPU_INTR_LEAF registers\n", - pIntr->replayableFaultIntrVector, pIntr->accessCntrIntrVector); - DBG_BREAKPOINT(); - status = NV_ERR_GENERIC; - goto exit; + if (NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(pIntr->replayableFaultIntrVector) != NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(pIntr->accessCntrIntrVector)) + { + NV_PRINTF(LEVEL_ERROR, "UVM interrupt vectors for replayable fault 0x%x " + "and access counter 0x%x are in different CPU_INTR_LEAF registers\n", + pIntr->replayableFaultIntrVector, pIntr->accessCntrIntrVector); + DBG_BREAKPOINT(); + status = NV_ERR_GENERIC; + goto exit; + } } // @@ -264,18 +275,19 @@ intrCacheIntrFields_TU102 // don't have to check later in latency critical paths where this is assumed // to be true) // - if (NV_CTRL_INTR_GPU_VECTOR_TO_SUBTREE(pIntr->replayableFaultIntrVector) != NV_CPU_INTR_UVM_SUBTREE_START) + if (NV_CTRL_INTR_GPU_VECTOR_TO_SUBTREE(pIntr->accessCntrIntrVector) != NV_CPU_INTR_UVM_SUBTREE_START) { NV_PRINTF(LEVEL_ERROR, "UVM interrupt vectors for replayable fault and " "access counter are in an unexpected subtree. Expected = 0x%x, actual = 0x%x\n", NV_CPU_INTR_UVM_SUBTREE_START, - NV_CTRL_INTR_GPU_VECTOR_TO_SUBTREE(pIntr->replayableFaultIntrVector)); + NV_CTRL_INTR_GPU_VECTOR_TO_SUBTREE(pIntr->accessCntrIntrVector)); DBG_BREAKPOINT(); status = NV_ERR_GENERIC; goto exit; } exit: + return status; } @@ -434,7 +446,7 @@ _intrEnableStall_TU102 // level. // val = _intrGetUvmLeafMask_TU102(pGpu, pIntr); - idx = NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(pIntr->replayableFaultIntrVector); + idx = NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(pIntr->accessCntrIntrVector); if (val != 0) { intrWriteRegLeafEnSet_HAL(pGpu, pIntr, idx, val, pThreadState); @@ -496,10 +508,12 @@ _intrDisableStall_TU102 THREAD_STATE_NODE *pThreadState ) { - NvU32 idx, val; + NvU32 idx; + + NvU32 val; // 1. Disable the UVM interrupts that RM currently owns at INTR_LEAF level - idx = NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(pIntr->replayableFaultIntrVector); + idx = NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(pIntr->accessCntrIntrVector); val = _intrGetUvmLeafMask_TU102(pGpu, pIntr); if (val != 0) { @@ -572,9 +586,9 @@ _intrDisableStall_TU102 // // 3. Disable some interrupt subtrees at top level (information about which - // ones to disable is cached in pIntr->cpuTopEnMask) + // ones to disable is cached in pIntr->intrTopEnMask) // - intrWriteRegTopEnClear_HAL(pGpu, pIntr, 0, pIntr->cpuTopEnMask, pThreadState); + intrWriteRegTopEnClear_HAL(pGpu, pIntr, 0, pIntr->intrTopEnMask, pThreadState); } /*! @@ -648,7 +662,7 @@ _intrGetUvmLeafMask_TU102 NvBool bRmOwnsReplayableFault = !!(pKernelGmmu->uvmSharedIntrRmOwnsMask & RM_UVM_SHARED_INTR_MASK_MMU_REPLAYABLE_FAULT_NOTIFY); NvBool bRmOwnsAccessCntr = !!(pKernelGmmu->uvmSharedIntrRmOwnsMask & RM_UVM_SHARED_INTR_MASK_HUB_ACCESS_COUNTER_NOTIFY); - if (bRmOwnsReplayableFault) + if (bRmOwnsReplayableFault && !gpuIsCCFeatureEnabled(pGpu)) { val |= NVBIT(NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(pIntr->replayableFaultIntrVector)); } @@ -831,7 +845,7 @@ intrGetPendingStallEngines_TU102 // Add non replayable fault engine if there is something in the shadow buffer, // as the interrupt itself is cleared earlier. // - if (portAtomicOrS32(&pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].fatalFaultIntrPending, 0)) + if (portAtomicOrS32(kgmmuGetFatalFaultIntrPendingState(pKernelGmmu, GPU_GFID_PF), 0)) { bitVectorSet(pEngines, MC_ENGINE_IDX_NON_REPLAYABLE_FAULT); } diff --git a/src/nvidia/src/kernel/gpu/intr/intr.c b/src/nvidia/src/kernel/gpu/intr/intr.c index fb1e3a874..abce1b9b1 100644 --- a/src/nvidia/src/kernel/gpu/intr/intr.c +++ b/src/nvidia/src/kernel/gpu/intr/intr.c @@ -63,36 +63,38 @@ intrServiceStall_IMPL(OBJGPU *pGpu, Intr *pIntr) NV_STATUS status; NvBool bPending; NvU16 nextEngine; - NvU32 regReadValue; - // - // If the GPU is off the BUS or surprise removed during servicing DPC for ISRs - // we wont know about GPU state until after we start processing DPCs for every - // pending engine. This is because, the reg read to determine pending engines - // return 0xFFFFFFFF due to GPU being off the bus. To prevent further processing, - // reading PMC_BOOT_0 register to check if the GPU was surprise removed/ off the bus - // and setting PDB_PROP_GPU_SECONDARY_BUS_RESET_PENDING to attempt Secondary Bus reset - // at lower IRQL later to attempt recover the GPU and avoid all ISR DPC processing till - // GPU is recovered. - // - - regReadValue = GPU_REG_RD32(pGpu, NV_PMC_BOOT_0); - - if (regReadValue == GPU_REG_VALUE_INVALID) + if (!RMCFG_FEATURE_PLATFORM_GSP) { - NV_PRINTF(LEVEL_ERROR, - "Failed GPU reg read : 0x%x. Check whether GPU is present on the bus\n", - regReadValue); - } + // + // If the GPU is off the BUS or surprise removed during servicing DPC for ISRs + // we wont know about GPU state until after we start processing DPCs for every + // pending engine. This is because, the reg read to determine pending engines + // return 0xFFFFFFFF due to GPU being off the bus. To prevent further processing, + // reading PMC_BOOT_0 register to check if the GPU was surprise removed/ off the bus + // and setting PDB_PROP_GPU_SECONDARY_BUS_RESET_PENDING to attempt Secondary Bus reset + // at lower IRQL later to attempt recover the GPU and avoid all ISR DPC processing till + // GPU is recovered. + // - if (!API_GPU_ATTACHED_SANITY_CHECK(pGpu)) - { - goto exit; - } + NvU32 regReadValue = GPU_REG_RD32(pGpu, NV_PMC_BOOT_0); - if (API_GPU_IN_RESET_SANITY_CHECK(pGpu)) - { - goto exit; + if (regReadValue == GPU_REG_VALUE_INVALID) + { + NV_PRINTF(LEVEL_ERROR, + "Failed GPU reg read : 0x%x. Check whether GPU is present on the bus\n", + regReadValue); + } + + if (!API_GPU_ATTACHED_SANITY_CHECK(pGpu)) + { + goto exit; + } + + if (API_GPU_IN_RESET_SANITY_CHECK(pGpu)) + { + goto exit; + } } portMemSet(stuckIntr, 0, sizeof(stuckIntr)); @@ -186,20 +188,20 @@ subdeviceCtrlCmdMcServiceInterrupts_IMPL // GPU instance GR engines // grCount = kmigmgrCountEnginesOfType(&ref.pKernelMIGGpuInstance->resourceAllocation.engines, - NV2080_ENGINE_TYPE_GR(0)); + RM_ENGINE_TYPE_GR(0)); } for (i = 0; i < grCount; ++i) { - NvU32 globalEngineType; + RM_ENGINE_TYPE globalRmEngineType; NvU32 grIdx; NV_ASSERT_OK( kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, - NV2080_ENGINE_TYPE_GR(i), - &globalEngineType)); + RM_ENGINE_TYPE_GR(i), + &globalRmEngineType)); - grIdx = NV2080_ENGINE_TYPE_GR_IDX(globalEngineType); + grIdx = RM_ENGINE_TYPE_GR_IDX(globalRmEngineType); bitVectorSet(&engines, MC_ENGINE_IDX_GRn(grIdx)); } } @@ -246,7 +248,7 @@ intrGetGmmuInterrupts_IMPL // Check if any fault was copied only if any other interrupt on GMMU is not pending. if (!bitVectorTest(pEngines, MC_ENGINE_IDX_GMMU)) { - if (portAtomicOrS32(&pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].fatalFaultIntrPending, 0)) + if (portAtomicOrS32(kgmmuGetFatalFaultIntrPendingState(pKernelGmmu, GPU_GFID_PF), 0)) { bitVectorSet(pEngines, MC_ENGINE_IDX_GMMU); } @@ -1008,7 +1010,7 @@ _intrInitServiceTable { ENGSTATE_ITER iter = gpuGetEngstateIter(pGpu); OBJENGSTATE *pEngstate; - + portMemSet(pIntr->intrServiceTable, 0, sizeof(pIntr->intrServiceTable)); while (gpuGetNextEngstate(pGpu, &iter, &pEngstate)) @@ -1078,7 +1080,7 @@ NV_STATUS intrServiceNotificationRecords_IMPL NV_ASSERT_FAILED("Missing notification interrupt handler"); return NV_ERR_GENERIC; } - + status = intrservServiceNotificationInterrupt(pGpu, pIntrService, ¶ms); if (status != NV_OK) { @@ -1086,14 +1088,14 @@ NV_STATUS intrServiceNotificationRecords_IMPL "Could not service notification interrupt for engine idx %d; returned NV_STATUS = 0x%x\n", engineIdx, status); NV_ASSERT_FAILED("Could not service notification interrupt"); - return NV_ERR_GENERIC; + return NV_ERR_GENERIC; } // // On Turing onwards, all non-stall interrupts, including the ones from // PBDMA, have moved to reporting on the runlist that is served by the // PBDMA. There are still some clients that use the PBDMA interrupts - // but currently register for a notifier of type NV2080_ENGINE_TYPE_HOST. + // but currently register for a notifier of type RM_ENGINE_TYPE_HOST. // Until those clients change to using the new notifiers, RM will fire // the host notifier for all non-stall interrupts from host-driven // engines. See bug 1866491. @@ -1102,9 +1104,9 @@ NV_STATUS intrServiceNotificationRecords_IMPL pGpu->activeFifoEventMthdNotifiers != 0 && !pIntr->intrServiceTable[engineIdx].bFifoWaiveNotify) { - engineNonStallIntrNotify(pGpu, NV2080_ENGINE_TYPE_HOST); + engineNonStallIntrNotify(pGpu, RM_ENGINE_TYPE_HOST); } - + return NV_OK; } @@ -1530,7 +1532,6 @@ intrServiceStallList_IMPL MC_ENGINE_BITVECTOR exactEngines; NvBool bPending; CALL_CONTEXT *pOldContext = NULL; - NvU32 regReadValue; if (gpumgrGetBcEnabledStatus(pGpu)) { @@ -1543,30 +1544,33 @@ intrServiceStallList_IMPL kgspDumpGspLogs(pGpu, pKernelGsp, NV_FALSE); } - // - // If the GPU is off the BUS or surprise removed during servicing DPC for ISRs - // we wont know about GPU state until after we start processing DPCs for every - // pending engine. This is because, the reg read to determine pending engines - // return 0xFFFFFFFF due to GPU being off the bus. To prevent further processing, - // reading PMC_BOOT_0 register to check if the GPU was surprise removed/ off the bus - // and setting PDB_PROP_GPU_SECONDARY_BUS_RESET_PENDING to attempt Secondary Bus reset - // at lower IRQL later to attempt recover the GPU and avoid all ISR DPC processing till - // GPU is recovered. - // - - regReadValue = GPU_REG_RD32(pGpu, NV_PMC_BOOT_0); - - if (regReadValue == GPU_REG_VALUE_INVALID) + if (!RMCFG_FEATURE_PLATFORM_GSP) { - NV_PRINTF(LEVEL_ERROR, - "Failed GPU reg read : 0x%x. Check whether GPU is present on the bus\n", - regReadValue); - } + // + // If the GPU is off the BUS or surprise removed during servicing DPC for ISRs + // we wont know about GPU state until after we start processing DPCs for every + // pending engine. This is because, the reg read to determine pending engines + // return 0xFFFFFFFF due to GPU being off the bus. To prevent further processing, + // reading PMC_BOOT_0 register to check if the GPU was surprise removed/ off the bus + // and setting PDB_PROP_GPU_SECONDARY_BUS_RESET_PENDING to attempt Secondary Bus reset + // at lower IRQL later to attempt recover the GPU and avoid all ISR DPC processing till + // GPU is recovered. + // - // Dont service interrupts if GPU is surprise removed - if (!API_GPU_ATTACHED_SANITY_CHECK(pGpu) || API_GPU_IN_RESET_SANITY_CHECK(pGpu)) - { - return; + NvU32 regReadValue = GPU_REG_RD32(pGpu, NV_PMC_BOOT_0); + + if (regReadValue == GPU_REG_VALUE_INVALID) + { + NV_PRINTF(LEVEL_ERROR, + "Failed GPU reg read : 0x%x. Check whether GPU is present on the bus\n", + regReadValue); + } + + // Dont service interrupts if GPU is surprise removed + if (!API_GPU_ATTACHED_SANITY_CHECK(pGpu) || API_GPU_IN_RESET_SANITY_CHECK(pGpu)) + { + return; + } } resservSwapTlsCallContext(&pOldContext, NULL); diff --git a/src/nvidia/src/kernel/gpu/intrable/intrable.c b/src/nvidia/src/kernel/gpu/intrable/intrable.c deleted file mode 100644 index 63c27c449..000000000 --- a/src/nvidia/src/kernel/gpu/intrable/intrable.c +++ /dev/null @@ -1,255 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2019-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "gpu/gpu.h" -#include "kernel/gpu/intrable/intrable.h" -#include "kernel/gpu/intr/intr.h" - -/*! - * @brief Intrable object constructor - * - * @param[in] pIntrable OBJINTRABLE pointer - * - * @return NV_OK - */ -NV_STATUS -intrableConstruct_IMPL -( - OBJINTRABLE *pIntrable -) -{ - pIntrable->partitionAssignedNotificationVector = NV_INTR_VECTOR_INVALID; - pIntrable->originalNotificationIntrVector = NV_INTR_VECTOR_INVALID; - - return NV_OK; -} - -/*! - * @brief Placeholder function to return error - * - * Inheriting classes should override and return the notification interrupt vector - * - * @param[in] pGpu OBJGPU pointer - * @param[in] pIntrable OBJINTRABLE pointer - * @param[in] maxIntrs max interrupt vectors to return - * @param[out] pIntrVectors table of interrupt vectors - * @param[out] pMcEngineIdxs table of MC_ENGINE_IDXs. Only required for non-engines - * @param[out] pCount how many interrupt vectors were found - * - * @return NV_ERR_NOT_SUPPORTED - */ -NV_STATUS -intrableGetPhysicalIntrVectors_IMPL -( - OBJGPU *pGpu, - OBJINTRABLE *pIntrable, - NvU32 maxIntrs, - NvU32 *pIntrVectors, - NvU32 *pMcEngineIdxs, - NvU32 *pCount -) -{ - return NV_ERR_NOT_SUPPORTED; -} - -/*! - * @brief Placeholder function to return error - * - * Inheriting classes should override and return the notification interrupt vector - * - * @param[in] pGpu OBJGPU pointer - * @param[in] pIntrable OBJINTRABLE pointer - * @param[in] maxIntrs max interrupt vectors to return - * @param[out] pIntrVectors table of interrupt vectors - * @param[out] pMcEngineIdxs table of MC_ENGINE_IDXs. Only required for non-engines - * @param[out] pCount how many interrupt vectors were found - * - * @return NV_ERR_NOT_SUPPORTED - */ -NV_STATUS -intrableGetKernelIntrVectors_IMPL -( - OBJGPU *pGpu, - OBJINTRABLE *pIntrable, - NvU32 maxIntrs, - NvU32 *pIntrVectors, - NvU32 *pMcEngineIdxs, - NvU32 *pCount -) -{ - return NV_ERR_NOT_SUPPORTED; -} - -/*! - * @brief Placeholder function to return error - * - * Inheriting classes should override and return the notification interrupt vector - * - * @param[in] pGpu OBJGPU pointer - * @param[in] pIntrable OBJINTRABLE pointer - * @param[in] pIntrVector Pointer to store the interrupt vector - * - * @return NV_ERR_NOT_SUPPORTED - */ -NV_STATUS -intrableGetNotificationIntrVector_IMPL -( - OBJGPU *pGpu, - OBJINTRABLE *pIntrable, - NvU32 *pIntrVector -) -{ - // Should never be called - DBG_BREAKPOINT(); - return NV_ERR_NOT_SUPPORTED; -} - -/*! - * @brief Placeholder function to return error - * - * Inheriting classes should override and set the notification interrupt vector # here - * - * @param[in] pGpu OBJGPU pointer - * @param[in] pIntrable OBJINTRABLE pointer - * @param[in] intrVector the interrupt vector - * - * @return NV_ERR_NOT_SUPPORTED - */ -NV_STATUS -intrableSetNotificationIntrVector_IMPL -( - OBJGPU *pGpu, - OBJINTRABLE *pIntrable, - NvU32 intrVector -) -{ - return NV_ERR_NOT_SUPPORTED; -} - -/*! - * @brief Cache (and then write to HW) the partition assigned notification - * intr vector - * - * @param[in] pGpu OBJGPU pointer - * @param[in] pIntrable OBJINTRABLE pointer - * @param[in] intrVector the interrupt vector - * - * @return NV_STATUS - */ -NV_STATUS -intrableCacheAndSetPartitionNotificationIntrVector_IMPL -( - OBJGPU *pGpu, - OBJINTRABLE *pIntrable, - NvU32 intrVector -) -{ - if (pIntrable->originalNotificationIntrVector == NV_INTR_VECTOR_INVALID) - { - // Remember the initial HW value before we overwrite it - NV_ASSERT_OK_OR_RETURN(intrableGetNotificationIntrVector(pGpu, pIntrable, - &pIntrable->originalNotificationIntrVector)); - } - - pIntrable->partitionAssignedNotificationVector = intrVector; - return intrableSetNotificationIntrVector(pGpu, pIntrable, intrVector); -} - -/*! - * @brief Write the cached partition assigned notification interrupt vector - * to HW again - * - * If the partition value is default, do nothing. - * Else write it to HW again. - * - * @param[in] pGpu OBJGPU pointer - * @param[in] pIntrable OBJINTRABLE pointer - * - * @return NV_STATUS - */ -NV_STATUS -intrableSetPartitionNotificationIntrVector_IMPL -( - OBJGPU *pGpu, - OBJINTRABLE *pIntrable -) -{ - if (pIntrable->partitionAssignedNotificationVector == NV_INTR_VECTOR_INVALID) - { - // No-op if this has not been configured - return NV_OK; - } - - return intrableSetNotificationIntrVector( - pGpu, pIntrable, pIntrable->partitionAssignedNotificationVector); -} - -/*! - * @brief Returns the partition assigned notification interrupt vector - * - * @param[in] pGpu OBJGPU pointer - * @param[in] pIntrable OBJINTRABLE pointer - * - * @return partitionAssignedNotificationVector - */ -NvU32 -intrableGetPartitionNotificationIntrVector_IMPL -( - OBJGPU *pGpu, - OBJINTRABLE *pIntrable -) -{ - return pIntrable->partitionAssignedNotificationVector; -} - -/*! - * @brief Return the notification interrupt vector to HW's original value, if - * is is not at its default value - * - * @param[in] pGpu OBJGPU pointer - * @param[in] pIntrable OBJINTRABLE pointer - * - * @return NV_STATUS - */ -NV_STATUS -intrableRevertNotificationIntrVector_IMPL -( - OBJGPU *pGpu, - OBJINTRABLE *pIntrable -) -{ - if (pIntrable->originalNotificationIntrVector == NV_INTR_VECTOR_INVALID) - { - // Don't expect to revert when there is nothing to revert to - return NV_ERR_INVALID_STATE; - } - - // - // Forget the partition assigned vector so that it does not get written - // again - // - pIntrable->partitionAssignedNotificationVector = NV_INTR_VECTOR_INVALID; - - return intrableSetNotificationIntrVector( - pGpu, pIntrable, pIntrable->originalNotificationIntrVector); -} diff --git a/src/nvidia/src/kernel/gpu/mc/kernel_mc.c b/src/nvidia/src/kernel/gpu/mc/kernel_mc.c index fa43770de..63df160b4 100644 --- a/src/nvidia/src/kernel/gpu/mc/kernel_mc.c +++ b/src/nvidia/src/kernel/gpu/mc/kernel_mc.c @@ -124,6 +124,11 @@ subdeviceCtrlCmdMcChangeReplayableFaultOwnership_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + if (gpuIsCCFeatureEnabled(pGpu)) + { + return NV_ERR_NOT_SUPPORTED; + } + if (pKernelGmmu != NULL) { kgmmuChangeReplayableFaultOwnership_HAL(pGpu, pKernelGmmu, pReplayableFaultOwnrshpParams->bOwnedByRm); diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/mem_mgr_ga100.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/mem_mgr_ga100.c index facef5ff3..467823ec0 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/mem_mgr_ga100.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/mem_mgr_ga100.c @@ -34,6 +34,7 @@ #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "gpu/subdevice/subdevice.h" #include "vgpu/vgpu_events.h" +#include "nvdevid.h" #include "published/ampere/ga100/dev_mmu.h" #include "published/ampere/ga100/dev_fb.h" diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/hopper/virt_mem_allocator_gh100.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/hopper/virt_mem_allocator_gh100.c index 9c6fe8779..0cccdb1c0 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/hopper/virt_mem_allocator_gh100.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/hopper/virt_mem_allocator_gh100.c @@ -79,9 +79,6 @@ dmaAllocBar1P2PMapping_GH100 bar1ApertureLen = params->length; - // Setup special PTE type for this memory - memdescSetPteKind(pBar1P2PPhysMemDesc, NV_MMU_PTE_KIND_GENERIC_MEMORY); - // // Step 2: // Create BAR1 mapping with MAP_BAR1_P2P flag on the target GPU. @@ -121,8 +118,8 @@ dmaAllocBar1P2PMapping_GH100 memdescSetPageSize(pBar1P2PVirtMemDesc, VAS_ADDRESS_TRANSLATION(params->pVas), memdescGetPageSize(pBar1P2PPhysMemDesc, VAS_ADDRESS_TRANSLATION(params->pVas))); - // Set the PTE kind to be the peer mem PTE kind - memdescSetPteKind(pBar1P2PVirtMemDesc, memdescGetPteKind(pBar1P2PPhysMemDesc)); + // Setup GMK PTE type for this memory + memdescSetPteKind(pBar1P2PVirtMemDesc, NV_MMU_PTE_KIND_GENERIC_MEMORY); // Set the memory address and memory type as a SYSMEM memdescDescribe(pBar1P2PVirtMemDesc, ADDR_SYSMEM, (RmPhysAddr)bar1PhyAddr, bar1ApertureLen); @@ -158,15 +155,9 @@ cleanup: BUS_MAP_FB_FLAGS_MAP_UNICAST); } - if (pBar1P2PPhysMemDesc) - { - memdescDestroy(pBar1P2PPhysMemDesc); - } + memdescDestroy(pBar1P2PPhysMemDesc); - if (pBar1P2PVirtMemDesc) - { - memdescDestroy(pBar1P2PVirtMemDesc); - } + memdescDestroy(pBar1P2PVirtMemDesc); NV_PRINTF(LEVEL_ERROR, "Failed to create bar1p2p mapping\n"); diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/fbsr_gm107.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/fbsr_gm107.c index d3a487d8d..ce94d7440 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/fbsr_gm107.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/fbsr_gm107.c @@ -98,6 +98,88 @@ // #define MAX_FILE_COPY_SIZE_WITHIN_DEFAULT_THREAD_TIMEOUT (64 * 1024 * 1024) +static NV_STATUS _fbsrInitGsp +( + OBJGPU *pGpu, + OBJFBSR *pFbsr +) +{ + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + NvHandle hSysMem = NV01_NULL_OBJECT; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS params; + + // Register sysmem memdesc with GSP. This creates memlist object + NV_ASSERT_OK_OR_RETURN(memdescSendMemDescToGSP(pGpu, pFbsr->pSysMemDesc, &hSysMem)); + + params.fbsrType = pFbsr->type; + params.numRegions = pFbsr->numRegions; + params.hClient = pMemoryManager->hClient; + params.hSysMem = hSysMem; + params.gspFbAllocsSysOffset = pFbsr->gspFbAllocsSysOffset; + + // Send S/R init information to GSP + NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_FBSR_INIT, + ¶ms, + sizeof(params))); + + // Free memlist object + pRmApi->Free(pRmApi, pMemoryManager->hClient, hSysMem); + + // + // Clear numRegions for next S/R sequence + // Needed only to tell GSP how many regions + // + pFbsr->numRegions = 0; + + return NV_OK; +} + +static NV_STATUS _fbsrMemoryCopy +( + OBJGPU *pGpu, + OBJFBSR *pFbsr, + MEMORY_DESCRIPTOR *pDstMemDesc, + NvU64 dstOffset, + MEMORY_DESCRIPTOR *pSrcMemDesc, + NvU64 srcOffset, + NvU64 size +) +{ + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + NvHandle hVidMem = NV01_NULL_OBJECT; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS params; + + // Register vidmem memdesc with GSP. This creates memlist object + NV_ASSERT_OK_OR_RETURN(memdescSendMemDescToGSP(pGpu, pSrcMemDesc, &hVidMem)); + + portMemSet(¶ms, 0, sizeof(params)); + + params.fbsrType = pFbsr->type; + params.hClient = pMemoryManager->hClient; + params.hVidMem = hVidMem; + params.vidOffset = srcOffset; + params.sysOffset = dstOffset; + params.size = size; + + // Send region information to GSP + NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_FBSR_SEND_REGION_INFO, + ¶ms, + sizeof(params))); + + // Free memlist object + pRmApi->Free(pRmApi, pMemoryManager->hClient, hVidMem); + + return NV_OK; +} + /*! * Init * @@ -256,7 +338,309 @@ fbsrDestroy_GM107(OBJGPU *pGpu, OBJFBSR *pFbsr) NV_STATUS fbsrBegin_GM107(OBJGPU *pGpu, OBJFBSR *pFbsr, FBSR_OP_TYPE op) { - return NV_ERR_NOT_SUPPORTED; + NV_STATUS status = NV_OK; + + pFbsr->op = op; + pFbsr->bOperationFailed = NV_FALSE; + if (op != FBSR_OP_SIZE_BUF && op != FBSR_OP_DESTROY) + { + if (IS_GSP_CLIENT(pGpu)) + { + pFbsr->pCe = NULL; + } + + NV_PRINTF(LEVEL_INFO, "%s %lld bytes of data\n", + pFbsr->op == FBSR_OP_SAVE ? "saving" : "restoring", + pFbsr->length); + } + + if (op == FBSR_OP_SAVE) + { + switch (pFbsr->type) + { + case FBSR_TYPE_PAGED_DMA: + case FBSR_TYPE_DMA: + // + // Check if system memory is pre-allocated for DMA type FBSR + // and use the same for performing FBSR. + // + if (pFbsr->pSysReservedMemDesc) + { + // + // Validate if reserved system memory size is sufficient, + // Otherwise generate the assert and free the + // pre-allocated reserved system memory + // + if (pFbsr->pSysReservedMemDesc->Size >= pFbsr->length) + { + pFbsr->pSysMemDesc = pFbsr->pSysReservedMemDesc; + // + // The reference to the reserved memory is transferred + // and the pSysMemDesc pointer will be used for actual + // FBSR operations. The actual object will be freed + // during FBSR_OP_RESTORE operation. + // + pFbsr->pSysReservedMemDesc = NULL; + break; + } + + NV_ASSERT(pFbsr->pSysReservedMemDesc->Size >= pFbsr->length); + memdescFree(pFbsr->pSysReservedMemDesc); + memdescDestroy(pFbsr->pSysReservedMemDesc); + pFbsr->pSysReservedMemDesc = NULL; + status = NV_ERR_GENERIC; + break; + } + + if (pFbsr->length) + { + if (pFbsr->type == FBSR_TYPE_DMA) + { + // This buffer is never touched by the CPU, so it can be uncached. + status = memdescCreate(&pFbsr->pSysMemDesc, pGpu, + pFbsr->length, 0, NV_FALSE, + ADDR_SYSMEM, NV_MEMORY_UNCACHED, + MEMDESC_FLAGS_NONE); + } + else if (pFbsr->type == FBSR_TYPE_PAGED_DMA) + { + // On Windows, pageable memory is also cacheable. + status = memdescCreate(&pFbsr->pSysMemDesc, pGpu, + pFbsr->length, 0, NV_FALSE, + ADDR_SYSMEM, NV_MEMORY_CACHED, + MEMDESC_FLAGS_PAGED_SYSMEM); + } + if (status != NV_OK) + { + NV_ASSERT(status == NV_OK); + break; + } + + status = memdescAlloc(pFbsr->pSysMemDesc); + if (status != NV_OK) + { + NV_ASSERT(status == NV_OK); + memdescDestroy(pFbsr->pSysMemDesc); + pFbsr->pSysMemDesc = NULL; + break; + } + + if (pFbsr->type == FBSR_TYPE_PAGED_DMA) + { + status = memdescLock(pFbsr->pSysMemDesc); + if (status != NV_OK) + { + NV_ASSERT(status == NV_OK); + memdescFree(pFbsr->pSysMemDesc); + memdescDestroy(pFbsr->pSysMemDesc); + pFbsr->pSysMemDesc = NULL; + break; + } + } + } + + break; + + case FBSR_TYPE_WDDM_FAST_DMA_DEFERRED_NONPAGED: + { + NvBool bIommuEnabled = pGpu->getProperty(pGpu, PDB_PROP_GPU_ENABLE_IOMMU_SUPPORT); + + if (pFbsr->length > pFbsr->pagedBufferInfo.maxLength) + { + status = NV_ERR_GENERIC; + break; + } + + if(bIommuEnabled) + { + status = osSrPinSysmem(pGpu->pOsGpuInfo, + pFbsr->length, + &pFbsr->pagedBufferInfo.pMdl); + + if (status != NV_OK) + break; + + NV_ASSERT(pFbsr->pagedBufferInfo.pMdl); + status = osCreateMemFromOsDescriptorInternal(pGpu, + pFbsr->pagedBufferInfo.pMdl, + 0, + pFbsr->length, + &pFbsr->pSysMemDesc, + NV_TRUE, + RS_PRIV_LEVEL_KERNEL + ); + if (status != NV_OK) + (void) osSrUnpinSysmem(pGpu->pOsGpuInfo); + } + else + { + pFbsr->pagedBufferInfo.sysAddr = 0; + status = osMapViewToSection(pGpu->pOsGpuInfo, + pFbsr->pagedBufferInfo.sectionHandle, + (void **) (&pFbsr->pagedBufferInfo.sysAddr), + pFbsr->length, 0, bIommuEnabled); + NV_ASSERT(pFbsr->pagedBufferInfo.sysAddr); + if (status != NV_OK) + break; + + status = osCreateMemFromOsDescriptorInternal(pGpu, + NvP64_VALUE(pFbsr->pagedBufferInfo.sysAddr), + 0, + pFbsr->length, + &pFbsr->pSysMemDesc, + NV_TRUE, + RS_PRIV_LEVEL_KERNEL); + // would return error + if (status != NV_OK) + { + NV_ASSERT(osUnmapViewFromSection(pGpu->pOsGpuInfo, + NvP64_VALUE(pFbsr->pagedBufferInfo.sysAddr), + bIommuEnabled) == NV_OK); + } + } + } + break; + + case FBSR_TYPE_WDDM_SLOW_CPU_PAGED: + if (pFbsr->length > pFbsr->pagedBufferInfo.maxLength || + (!pGpu->getProperty(pGpu, PDB_PROP_GPU_ENABLE_IOMMU_SUPPORT) && + !pFbsr->pagedBufferInfo.sectionHandle)) + { + status = NV_ERR_GENERIC; + break; + } + pFbsr->pagedBufferInfo.avblViewSz = 0; + // fallthrough + case FBSR_TYPE_CPU: + if (!pFbsr->pSysMemDesc) + { + status = NV_ERR_GENERIC; + } + + break; + case FBSR_TYPE_PERSISTENT: + break; + case FBSR_TYPE_FILE: + // XXX can this condition ever evaluate to true? + if (!pFbsr->pSysMemDesc) + { + status = NV_ERR_GENERIC; + break; + } + + // Open a temporary file for writing + status = osOpenTemporaryFile(&pFbsr->pagedBufferInfo.sectionHandle); + if (status != NV_OK) + break; + + pFbsr->pagedBufferInfo.avblViewSz = 0; + break; + default: + status = NV_ERR_GENERIC; + NV_ASSERT(0); + break; + } + + // Initialize FBSR on GSP + if (IS_GSP_CLIENT(pGpu) && (pFbsr->pSysMemDesc != NULL)) + { + NV_ASSERT_OK_OR_RETURN(_fbsrInitGsp(pGpu, pFbsr)); + } + } + else if (pFbsr->op == FBSR_OP_RESTORE || pFbsr->op == FBSR_OP_DESTROY) + { + switch (pFbsr->type) + { + case FBSR_TYPE_PAGED_DMA: + status = memdescLock(pFbsr->pSysMemDesc); + NV_ASSERT(status == NV_OK); + break; + case FBSR_TYPE_FILE: + if (!pFbsr->pagedBufferInfo.sectionHandle) + { + status = NV_ERR_GENERIC; + break; + } + pFbsr->pagedBufferInfo.avblViewSz = 0; + break; + case FBSR_TYPE_WDDM_SLOW_CPU_PAGED: + if (pFbsr->length > pFbsr->pagedBufferInfo.maxLength || + (!pGpu->getProperty(pGpu, PDB_PROP_GPU_ENABLE_IOMMU_SUPPORT) && + !pFbsr->pagedBufferInfo.sectionHandle)) + { + status = NV_ERR_GENERIC; + break; + } + pFbsr->pagedBufferInfo.avblViewSz = 0; + break; + case FBSR_TYPE_WDDM_FAST_DMA_DEFERRED_NONPAGED: + { + NvBool bIommuEnabled = pGpu->getProperty(pGpu, PDB_PROP_GPU_ENABLE_IOMMU_SUPPORT); + // Error checked during SAVE + if (pFbsr->length > pFbsr->pagedBufferInfo.maxLength) + { + status = NV_ERR_GENERIC; + break; + } + if(bIommuEnabled) + { + status = osSrPinSysmem(pGpu->pOsGpuInfo, + pFbsr->length, + &pFbsr->pagedBufferInfo.pMdl); + + if (status != NV_OK) + break; + + NV_ASSERT(pFbsr->pagedBufferInfo.pMdl); + status = osCreateMemFromOsDescriptorInternal(pGpu, + pFbsr->pagedBufferInfo.pMdl, + 0, + pFbsr->length, + &pFbsr->pSysMemDesc, + NV_TRUE, + RS_PRIV_LEVEL_KERNEL + ); + if (status != NV_OK) + (void) osSrUnpinSysmem(pGpu->pOsGpuInfo); + } + else + { + pFbsr->pagedBufferInfo.sysAddr = 0; + status = osMapViewToSection(pGpu->pOsGpuInfo, + pFbsr->pagedBufferInfo.sectionHandle, + (void **)(&pFbsr->pagedBufferInfo.sysAddr), + pFbsr->length, 0, bIommuEnabled); + + if (status != NV_OK) + break; + + NV_ASSERT(pFbsr->pagedBufferInfo.sysAddr); + status = osCreateMemFromOsDescriptorInternal(pGpu, + NvP64_VALUE(pFbsr->pagedBufferInfo.sysAddr), + 0, + pFbsr->length, + &pFbsr->pSysMemDesc, + NV_TRUE, + RS_PRIV_LEVEL_KERNEL); + // would return error + if (status != NV_OK) + { + NV_ASSERT(osUnmapViewFromSection(pGpu->pOsGpuInfo, + NvP64_VALUE(pFbsr->pagedBufferInfo.sysAddr), + bIommuEnabled) == NV_OK); + } + } + } + + break; + } + } + + pFbsr->pSysMemNodeCurrent = pFbsr->pSysMemNodeHead; + pFbsr->length = 0; + pFbsr->sysOffset = 0; + + return status; } /*! @@ -411,7 +795,362 @@ fbsrEnd_GM107(OBJGPU *pGpu, OBJFBSR *pFbsr) void fbsrCopyMemoryMemDesc_GM107(OBJGPU *pGpu, OBJFBSR *pFbsr, MEMORY_DESCRIPTOR *pVidMemDesc) { + NV_STATUS status = NV_OK; + + NV_ASSERT(!gpumgrGetBcEnabledStatus(pGpu)); + + pVidMemDesc = memdescGetMemDescFromGpu(pVidMemDesc, pGpu); + + if (pFbsr->bOperationFailed) + { + // If we hit a failure igonre the rest of the copy requests + return; + } + + pFbsr->length += pVidMemDesc->Size; + + // We should have nothing reserved when FB is broken + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_BROKEN_FB)) + { + NV_ASSERT(pVidMemDesc->Size == 0); + NV_PRINTF(LEVEL_WARNING, "return early since FB is broken!\n"); + return; + } + + if (pFbsr->op == FBSR_OP_SIZE_BUF) + { + pFbsr->numRegions++; + + switch (pFbsr->type) + { + case FBSR_TYPE_CPU: + { + PFBSR_NODE pNode; + + pNode = portMemAllocNonPaged( + sizeof(FBSR_NODE) + (NvU32)pVidMemDesc->Size - sizeof(pNode->data)); + + if (pNode == NULL) + { + NV_ASSERT(0); + pFbsr->bOperationFailed = NV_TRUE; + return; + } + + pNode->pNext = NULL; + + // Insert node + if (!pFbsr->pSysMemNodeHead) + { + pFbsr->pSysMemNodeHead = pNode; + } + else + { + pFbsr->pSysMemNodeCurrent->pNext = pNode; + } + + pFbsr->pSysMemNodeCurrent = pNode; + + break; + } + case FBSR_TYPE_PERSISTENT: + { + MEMORY_DESCRIPTOR *pStandbyBuffer; + + if (memdescGetStandbyBuffer(pVidMemDesc) == NULL) + { + status = memdescCreate(&pStandbyBuffer, pGpu, + pVidMemDesc->Size, 0, NV_FALSE, + ADDR_SYSMEM, + NV_MEMORY_WRITECOMBINED, + MEMDESC_FLAGS_NONE); + if (status == NV_OK) + { + status = memdescAlloc(pStandbyBuffer); + if (status != NV_OK ) + { + memdescDestroy(pStandbyBuffer); + pFbsr->bOperationFailed = NV_TRUE; + break; + } + memdescSetStandbyBuffer(pVidMemDesc, pStandbyBuffer); + } + else + { + pFbsr->bOperationFailed = NV_TRUE; + } + } + break; + } + default: + break; + } + } + else + { + NV_PRINTF(LEVEL_INFO, "%s allocation %llx-%llx [%s]\n", + pFbsr->op == FBSR_OP_SAVE ? "saving" : "restoring", + memdescGetPhysAddr(pVidMemDesc, AT_GPU, 0), + memdescGetPhysAddr(pVidMemDesc, AT_GPU, 0) + pVidMemDesc->Size - 1, + pFbsr->type == FBSR_TYPE_DMA ? "DMA" : "CPU"); + + switch (pFbsr->type) + { + case FBSR_TYPE_WDDM_FAST_DMA_DEFERRED_NONPAGED: + case FBSR_TYPE_PAGED_DMA: + case FBSR_TYPE_DMA: + { + if (pFbsr->op == FBSR_OP_RESTORE) + { + } + else + { + if (IS_GSP_CLIENT(pGpu)) + { + _fbsrMemoryCopy(pGpu, pFbsr, pFbsr->pSysMemDesc, + pFbsr->sysOffset, pVidMemDesc, 0, + pVidMemDesc->Size); + } + } + break; + } + case FBSR_TYPE_PERSISTENT: + { + if (pFbsr->op == FBSR_OP_RESTORE) + { + } + else + { + } + break; + } + case FBSR_TYPE_WDDM_SLOW_CPU_PAGED: + { + NvU64 totalCopySize = pVidMemDesc->Size; + NvU64 vidOffset = 0; + NvU64 copySize, i; + NvU32 *cpuCopyOffset = 0; + NvBool bIommuEnabled = pGpu->getProperty(pGpu, PDB_PROP_GPU_ENABLE_IOMMU_SUPPORT); + + // Saves/restores a fbregion at memdesc granularity + while(totalCopySize) + { + // Backing system buffer (paged VA) is 64k and only map new 64k section + // when backing buffer is consumed. + if (pFbsr->pagedBufferInfo.avblViewSz == 0) + { + NV_ASSERT(((pFbsr->sysOffset + vidOffset)& 0xffff) == 0); + pFbsr->pagedBufferInfo.avblViewSz = CPU_MAX_PINNED_BUFFER_SIZE; + pFbsr->pagedBufferInfo.sysAddr = 0; + + // Get VA to a 64K view in the section at the offset sysOffset + vidOffset + // sysOffset tracks across memdesc, vidOffset tracks the 4k copy + status = osMapViewToSection(pGpu->pOsGpuInfo, + pFbsr->pagedBufferInfo.sectionHandle, + (void **)(&pFbsr->pagedBufferInfo.sysAddr), + pFbsr->pagedBufferInfo.avblViewSz, + pFbsr->sysOffset + vidOffset, + bIommuEnabled); + if (status != NV_OK) + { + pFbsr->bOperationFailed = NV_TRUE; + NV_ASSERT(0); + break; + } + } + // Compute the cpuOffset to copy to / from + cpuCopyOffset = KERNEL_POINTER_FROM_NvP64(NvU32*, NvP64_PLUS_OFFSET(pFbsr->pagedBufferInfo.sysAddr, + ((NvU64) CPU_MAX_PINNED_BUFFER_SIZE - pFbsr->pagedBufferInfo.avblViewSz))); + copySize = NV_MIN(pFbsr->pagedBufferInfo.avblViewSz, totalCopySize); + + if (pFbsr->op == FBSR_OP_RESTORE) + { + // pPinnedBuffer is the 64K scratch buffer + // cpuCopyOffset is the mapped paged CPU VA + // Restore from the backing store to the pinned 64k scratch buffer + // We copy the region in 4byte granularity + for (i = 0; i < (copySize / 4); i++) + { + pFbsr->pPinnedBuffer[i] = cpuCopyOffset[i]; + } + } + + if (pFbsr->op == FBSR_OP_RESTORE) + { + } + else + { + } + + if (pFbsr->op == FBSR_OP_SAVE) + { + // Copy from the scratch buffer to the sysmem backing store + for (i = 0; i < (copySize / 4); i++) + { + cpuCopyOffset[i] = pFbsr->pPinnedBuffer[i]; + } + } + + vidOffset += copySize; + totalCopySize -= copySize; + pFbsr->pagedBufferInfo.avblViewSz -= copySize; + if (pFbsr->pagedBufferInfo.avblViewSz == 0) + { + status = osUnmapViewFromSection(pGpu->pOsGpuInfo, + NvP64_VALUE(pFbsr->pagedBufferInfo.sysAddr), + bIommuEnabled); + if (status != NV_OK) + { + pFbsr->bOperationFailed = NV_TRUE; + NV_ASSERT(0); + break; + } + } + } + } + break; + case FBSR_TYPE_FILE: + { + NvU64 totalCopySize = pVidMemDesc->Size; + NvU64 vidOffset = 0; + NvU64 copySize; + NvU64 threadTimeoutCopySize = 0; + + // + // File based operation can take longer time in completion, if the + // FB usage is high. Also, the File read/write time is + // system dependent (the temporary file location, Free + // system RAM, secondary storage type, etc.). Reset the thread + // timeout at the starting and at the end to prevent GPU + // thread timeout errors. Also, keep track of file copy size + // since last threadStateResetTimeout() in variable + // threadTimeoutCopySize. When this copy size go above certain + // threshold, then also reset the thread timeout and + // threadTimeoutCopySize variable. + // + NV_ASSERT_OK(threadStateResetTimeout(pGpu)); + + // Saves/restores a fbregion at memdesc granularity + while (totalCopySize) + { + // Backing system buffer (paged VA) is 64k and only map new 64k section + // when backing buffer is consumed. + if (pFbsr->pagedBufferInfo.avblViewSz == 0) + { + NV_ASSERT(((pFbsr->sysOffset + vidOffset) & (CPU_MAX_PINNED_BUFFER_SIZE - 1)) == 0); + pFbsr->pagedBufferInfo.avblViewSz = CPU_MAX_PINNED_BUFFER_SIZE; + } + + copySize = NV_MIN(pFbsr->pagedBufferInfo.avblViewSz, totalCopySize); + + if (threadTimeoutCopySize >= MAX_FILE_COPY_SIZE_WITHIN_DEFAULT_THREAD_TIMEOUT) + { + NV_ASSERT_OK(threadStateResetTimeout(pGpu)); + threadTimeoutCopySize = 0; + } + + threadTimeoutCopySize += copySize; + + if (pFbsr->op == FBSR_OP_RESTORE) + { + // pPinnedBuffer is the 64K scratch buffer + // cpuCopyOffset is the mapped paged CPU VA + // Restore from the backing store to the pinned 64k scratch buffer + // We copy the region in 4byte granularity + // replace this with file read + status = osReadFromFile(pFbsr->pagedBufferInfo.sectionHandle, + &pFbsr->pDmaBuffer[0], + copySize, + pFbsr->sysOffset + vidOffset); + if (status != NV_OK) + { + pFbsr->bOperationFailed = NV_TRUE; + NV_ASSERT(0); + break; + } + } + + if (pFbsr->op == FBSR_OP_RESTORE) + { + } + else + { + } + + if (pFbsr->op == FBSR_OP_SAVE) + { + status = osWriteToFile(pFbsr->pagedBufferInfo.sectionHandle, + &pFbsr->pDmaBuffer[0], + copySize, + pFbsr->sysOffset + vidOffset); + if (status != NV_OK) + { + pFbsr->bOperationFailed = NV_TRUE; + NV_ASSERT(0); + break; + } + } + + vidOffset += copySize; + totalCopySize -= copySize; + pFbsr->pagedBufferInfo.avblViewSz -= copySize; + } + } + + NV_ASSERT_OK(threadStateResetTimeout(pGpu)); + break; + case FBSR_TYPE_CPU: + { + PFBSR_NODE pNode = pFbsr->pSysMemNodeCurrent; + NvU64 vidOffset = 0; + NvU64 copySize; + NvU64 size = pVidMemDesc->Size; + NvU64 i; + + NV_ASSERT(pNode); + NV_ASSERT((pFbsr->sysOffset & 3) == 0); + + while (size) + { + copySize = NV_MIN(CPU_PINNED_BUFFER_SIZE, size); + + if (pFbsr->op == FBSR_OP_RESTORE) + { + for (i = 0; i < (copySize / 4); i++) + { + pFbsr->pPinnedBuffer[i] = pNode->data[i]; + } + } + + if (pFbsr->op == FBSR_OP_RESTORE) + { + } + else + { + } + + if (pFbsr->op == FBSR_OP_SAVE) + { + for (i = 0; i < (copySize / 4); i++) + { + pNode->data[i] = pFbsr->pPinnedBuffer[i]; + } + } + + vidOffset += copySize; + size -= copySize; + } + + pFbsr->pSysMemNodeCurrent = pFbsr->pSysMemNodeCurrent->pNext; + } + + break; + } + + pFbsr->sysOffset += pVidMemDesc->Size; + } } #ifdef DEBUG #endif + diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c index 178db5206..b02833b03 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c @@ -62,7 +62,6 @@ memmgrChooseKindCompressC_GM107 NvU32 attrdepth = DRF_VAL(OS32, _ATTR, _DEPTH, pFbAllocPageFormat->attr); NvU32 aasamples = DRF_VAL(OS32, _ATTR, _AA_SAMPLES, pFbAllocPageFormat->attr); NvBool prefer_zbc = !FLD_TEST_DRF(OS32, _ATTR2, _ZBC, _PREFER_NO_ZBC, pFbAllocPageFormat->attr2); - NvU32 ssampling = 0; // TODO switch (attrdepth) { @@ -84,7 +83,7 @@ memmgrChooseKindCompressC_GM107 case NVOS32_ATTR_AA_SAMPLES_4_ROTATED: case NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_8: case NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_16: - kind = prefer_zbc? (ssampling? NV_MMU_PTE_KIND_C32_MS4_2CBA : NV_MMU_PTE_KIND_C32_MS4_2CBR) : NV_MMU_PTE_KIND_C32_MS4_2BRA; + kind = prefer_zbc? NV_MMU_PTE_KIND_C32_MS4_2CBR : NV_MMU_PTE_KIND_C32_MS4_2BRA; break; case NVOS32_ATTR_AA_SAMPLES_8: case NVOS32_ATTR_AA_SAMPLES_16: @@ -107,7 +106,7 @@ memmgrChooseKindCompressC_GM107 case NVOS32_ATTR_AA_SAMPLES_4_ROTATED: case NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_8: case NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_16: - kind = prefer_zbc? (ssampling? NV_MMU_PTE_KIND_C64_MS4_2CBA : NV_MMU_PTE_KIND_C64_MS4_2CBR) : NV_MMU_PTE_KIND_C64_MS4_2BRA; + kind = prefer_zbc? NV_MMU_PTE_KIND_C64_MS4_2CBR : NV_MMU_PTE_KIND_C64_MS4_2BRA; break; case NVOS32_ATTR_AA_SAMPLES_8: case NVOS32_ATTR_AA_SAMPLES_16: @@ -324,7 +323,7 @@ memmgrAllocHal_GM107 if ( // Tiling is not supported in nv50+ (tiledAttr == NVOS32_ATTR_TILED_REQUIRED) || - (tiledAttr == 0x3) || + (tiledAttr == NVOS32_ATTR_TILED_DEFERRED) || // check the value of compression attribute // attributes verification for compressed surfaces !(memmgrVerifyComprAttrs_HAL(pMemoryManager, type, format, comprAttr)) || @@ -806,6 +805,7 @@ memmgrInitReservedMemory_GM107 NvU32 rsvdRegion = 0; NvU64 rsvdTopOfMem = 0; NvU64 rsvdAlignment = 0; + NvBool bMemoryProtectionEnabled = NV_FALSE; const MEMORY_SYSTEM_STATIC_CONFIG *pMemorySystemConfig = kmemsysGetStaticConfig(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)); @@ -852,8 +852,11 @@ memmgrInitReservedMemory_GM107 for (i = 0; i < pMemoryManager->Ram.numFBRegions; i++) { if (pMemoryManager->Ram.fbRegion[i].bRsvdRegion || - pMemoryManager->Ram.fbRegion[i].bProtected) + (bMemoryProtectionEnabled && !pMemoryManager->Ram.fbRegion[i].bProtected) || + (!bMemoryProtectionEnabled && pMemoryManager->Ram.fbRegion[i].bProtected)) + { continue; + } bRsvdRegionIsValid = NV_TRUE; rsvdRegion = i; @@ -942,7 +945,7 @@ memmgrInitReservedMemory_GM107 rsvdFbRegion.bSupportCompressed = NV_FALSE; rsvdFbRegion.bSupportISO = NV_FALSE; rsvdFbRegion.rsvdSize = pMemoryManager->rsvdMemorySize; - rsvdFbRegion.bProtected = NV_FALSE; + rsvdFbRegion.bProtected = bMemoryProtectionEnabled; rsvdFbRegion.bInternalHeap = NV_TRUE; memmgrInsertFbRegion(pGpu, pMemoryManager, &rsvdFbRegion); diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_utils_gm107.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_utils_gm107.c index 2cc940241..acf354922 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_utils_gm107.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_utils_gm107.c @@ -1031,7 +1031,7 @@ memmgrMemUtilsScrubInitScheduleChannel NVA06F_CTRL_BIND_PARAMS bindParams; portMemSet(&bindParams, 0, sizeof(bindParams)); - bindParams.engineType = pChannel->engineType; + bindParams.engineType = gpuGetNv2080EngineType(pChannel->engineType); rmStatus = pRmApi->Control(pRmApi, pChannel->hClient, @@ -1073,7 +1073,8 @@ memmgrMemUtilsCopyEngineInitialize_GM107 OBJCHANNEL *pChannel ) { - NvU32 classID, engineID; + NvU32 classID; + RM_ENGINE_TYPE engineID; NV_STATUS rmStatus; KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); KernelChannel *pFifoKernelChannel = NULL; @@ -1168,25 +1169,15 @@ static NV_STATUS _memUtilsGetCe_GM107 { NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, gpuUpdateEngineTable(pGpu)); - for (ceInst = 0; ceInst < ENG_CE__SIZE_1; ceInst++) - { - pKCe = GPU_GET_KCE(pGpu, ceInst); - if (pKCe == NULL) - { - continue; - } - + KCE_ITER_ALL_BEGIN(pGpu, pKCe, 0) if (kbusCheckEngine_HAL(pGpu, pKernelBus, ENG_CE(pKCe->publicID)) && - !ceIsCeGrce(pGpu, NV2080_ENGINE_TYPE_COPY(pKCe->publicID)) && - gpuCheckEngineTable(pGpu, NV2080_ENGINE_TYPE_COPY(pKCe->publicID))) + !ceIsCeGrce(pGpu, RM_ENGINE_TYPE_COPY(pKCe->publicID)) && + gpuCheckEngineTable(pGpu, RM_ENGINE_TYPE_COPY(pKCe->publicID))) { + ceInst = kceInst; break; } - } - if (ceInst == ENG_CE__SIZE_1) - { - status = NV_ERR_INSUFFICIENT_RESOURCES; - } + KCE_ITER_END_OR_RETURN_ERROR } NV_ASSERT_OK_OR_RETURN(status); @@ -1218,7 +1209,7 @@ static NV_STATUS _memUtilsAllocCe_GM107 createParams.engineType = NV2080_ENGINE_TYPE_COPY(pKCe->publicID); memmgrMemUtilsGetCopyEngineClass_HAL(pGpu, pMemoryManager, &pChannel->hTdCopyClass); - pChannel->engineType = createParams.engineType; + pChannel->engineType = gpuGetRmEngineType(createParams.engineType); if (!pChannel->hTdCopyClass) { @@ -1333,7 +1324,7 @@ _memUtilsAllocateChannel OBJCHANNEL *pChannel ) { - NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS channelGPFIFOAllocParams; + NV_CHANNEL_ALLOC_PARAMS channelGPFIFOAllocParams; NV_STATUS rmStatus = NV_OK; NvU32 hClass; RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); @@ -1343,7 +1334,7 @@ _memUtilsAllocateChannel NV_ASSERT_OK_OR_RETURN(_memUtilsGetCe_GM107(pGpu, hClientId, &pKCe)); NV_ASSERT_OR_RETURN((pKCe != NULL), NV_ERR_INVALID_STATE); - portMemSet(&channelGPFIFOAllocParams, 0, sizeof(NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS)); + portMemSet(&channelGPFIFOAllocParams, 0, sizeof(NV_CHANNEL_ALLOC_PARAMS)); channelGPFIFOAllocParams.hObjectError = hObjectError; channelGPFIFOAllocParams.hObjectBuffer = hObjectBuffer; channelGPFIFOAllocParams.gpFifoOffset = pChannel->pbGpuVA + pChannel->channelPbSize; @@ -1360,16 +1351,16 @@ _memUtilsAllocateChannel { KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); MIG_INSTANCE_REF ref; - NvU32 localCe; + RM_ENGINE_TYPE localCe; NV_ASSERT_OK_OR_RETURN( kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClientId, &ref)); // Clear the Compute instance portion, if present ref = kmigmgrMakeGIReference(ref.pKernelMIGGpuInstance); NV_ASSERT_OK_OR_RETURN( kmigmgrGetGlobalToLocalEngineType(pGpu, pKernelMIGManager, ref, - NV2080_ENGINE_TYPE_COPY(pKCe->publicID), + RM_ENGINE_TYPE_COPY(pKCe->publicID), &localCe)); - channelGPFIFOAllocParams.engineType = localCe; + channelGPFIFOAllocParams.engineType = gpuGetNv2080EngineType(localCe); } else { diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c index 458650147..c0085172c 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c @@ -217,11 +217,12 @@ dmaAllocMapping_GM107 NvBool bCallingContextPlugin; const MEMORY_SYSTEM_STATIC_CONFIG *pMemorySystemConfig = kmemsysGetStaticConfig(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)); + OBJGVASPACE *pGVAS = NULL; struct { NvU32 pteCount; - NvU32 pageCount4k; + NvU32 pageCount; NvU32 overMap; NvU64 vaLo; NvU64 vaHi; @@ -262,6 +263,8 @@ dmaAllocMapping_GM107 MEMORY_DESCRIPTOR *pRootMemDesc; MEMORY_DESCRIPTOR *pTempMemDesc; Memory *pMemory; + NvU32 pageArrayGranularity; + NvU8 pageShift; } *pLocals = portMemAllocNonPaged(sizeof(*pLocals)); // Heap Allocate to avoid stack overflow @@ -328,7 +331,7 @@ dmaAllocMapping_GM107 if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "Failed to get the adjusted memdesc for the fabric memdesc\n"); - return status; + goto cleanup; } } @@ -336,6 +339,9 @@ dmaAllocMapping_GM107 pLocals->pTempMemDesc = memdescGetMemDescFromGpu(pAdjustedMemDesc, pGpu); pLocals->pageSize = memdescGetPageSize(pLocals->pTempMemDesc, addressTranslation); + // Get pte granularity + pLocals->pageArrayGranularity = pLocals->pTempMemDesc->pageArrayGranularity; + if (memdescGetFlag(pLocals->pTempMemDesc, MEMDESC_FLAGS_DEVICE_READ_ONLY)) { NV_ASSERT_OR_ELSE((pLocals->readOnly == DMA_UPDATE_VASPACE_FLAGS_READ_ONLY), @@ -387,10 +393,12 @@ dmaAllocMapping_GM107 } } + pLocals->pageShift = BIT_IDX_32(pLocals->pageArrayGranularity); + // Get mapping params on current gpu memdesc pLocals->pageOffset = memdescGetPhysAddr(pLocals->pTempMemDesc, addressTranslation, 0) & (pLocals->pageSize - 1); pLocals->mapLength = RM_ALIGN_UP(pLocals->pageOffset + pLocals->pTempMemDesc->Size, pLocals->pageSize); - pLocals->pageCount4k = NvU64_LO32(pLocals->mapLength >> RM_PAGE_SHIFT); + pLocals->pageCount = NvU64_LO32(pLocals->mapLength >> pLocals->pageShift); pLocals->bIsMemContiguous = memdescGetContiguity(pLocals->pTempMemDesc, addressTranslation); pLocals->kind = NV_MMU_PTE_KIND_PITCH; @@ -450,7 +458,7 @@ dmaAllocMapping_GM107 { // FIXME: This is broken for page size > 4KB and page offset // that crosses a page boundary (can overrun pPteArray). - pLocals->pteCount = pLocals->pageCount4k; + pLocals->pteCount = pLocals->pageCount; } // Disable PLC Compression for FLA->PA Mapping because of the HW Bug: 3046774 @@ -488,11 +496,11 @@ dmaAllocMapping_GM107 if (pLocals->bIsMemContiguous) { - pLocals->overMap = pLocals->pageCount4k + NvU64_LO32((pLocals->pageOffset + RM_PAGE_MASK) / RM_PAGE_SIZE); + pLocals->overMap = pLocals->pageCount + NvU64_LO32((pLocals->pageOffset + (pLocals->pageArrayGranularity - 1)) / pLocals->pageArrayGranularity); } else { - pLocals->overMap = pLocals->pageCount4k; + pLocals->overMap = pLocals->pageCount; } NV_ASSERT_OK_OR_GOTO(status, vgpuGetCallingContextGfid(pGpu, &gfid), cleanup); @@ -541,7 +549,7 @@ dmaAllocMapping_GM107 targetSpaceLength = targetSpaceLimit - targetSpaceBase + 1; } - if (pLocals->pteCount > ((targetSpaceLength + (RM_PAGE_SIZE-1)) / RM_PAGE_SIZE)) + if (pLocals->pteCount > ((targetSpaceLength + (pLocals->pageArrayGranularity - 1)) / pLocals->pageArrayGranularity)) { NV_ASSERT(0); status = NV_ERR_INVALID_ARGUMENT; @@ -653,6 +661,23 @@ dmaAllocMapping_GM107 allocFlags.bReverse = FLD_TEST_DRF(OS46, _FLAGS, _DMA_OFFSET_GROWS, _DOWN, flags); + // + // Feature requested for RM unlinked SLI: + // Clients can pass an allocation flag to the device or VA space constructor + // so that mappings and allocations will fail without an explicit address. + // + pGVAS = dynamicCast(pVAS, OBJGVASPACE); + if (pGVAS != NULL) + { + if ((pGVAS->flags & VASPACE_FLAGS_REQUIRE_FIXED_OFFSET) && + !FLD_TEST_DRF(OS46, _FLAGS, _DMA_OFFSET_FIXED, _TRUE, flags)) + { + status = NV_ERR_INVALID_ARGUMENT; + NV_PRINTF(LEVEL_ERROR, "The VA space requires all allocations to specify a fixed address\n"); + goto cleanup; + } + } + status = vaspaceAlloc(pVAS, vaSize, vaAlign, pLocals->vaRangeLo, pLocals->vaRangeHi, pageSizeLockMask, allocFlags, &pLocals->vaLo); if (NV_OK != status) @@ -830,7 +855,8 @@ dmaAllocMapping_GM107 pLocals->aperture = NV_MMU_PTE_APERTURE_VIDEO_MEMORY; } } - else if ((memdescGetAddressSpace(pLocals->pTempMemDesc) == ADDR_FABRIC) || + else if ( + (memdescGetAddressSpace(pLocals->pTempMemDesc) == ADDR_FABRIC_MC) || (memdescGetAddressSpace(pLocals->pTempMemDesc) == ADDR_FABRIC_V2)) { OBJGPU *pMappingGpu = pGpu; @@ -857,6 +883,15 @@ dmaAllocMapping_GM107 pLocals->aperture = NV_MMU_PTE_APERTURE_PEER_MEMORY; + if (!memIsGpuMapAllowed(pLocals->pMemory, pMappingGpu)) + { + NV_PRINTF(LEVEL_ERROR, + "Mapping Gpu is not attached to the given memory object\n"); + status = NV_ERR_INVALID_STATE; + DBG_BREAKPOINT(); + SLI_LOOP_BREAK; + } + if (pPeerGpu != NULL) { KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pMappingGpu); @@ -868,6 +903,11 @@ dmaAllocMapping_GM107 pPeerGpu); } } + else + { + pLocals->peerNumber = kbusGetNvSwitchPeerId_HAL(pMappingGpu, + GPU_GET_KERNEL_BUS(pMappingGpu)); + } if (pLocals->peerNumber == BUS_INVALID_PEER) { @@ -918,10 +958,11 @@ dmaAllocMapping_GM107 } // - // ADDR_FABRIC/ADDR_FABRIC_V2 memory descriptors are pre-encoded with the fabric base address + // Fabric memory descriptors are pre-encoded with the fabric base address // use NVLINK_INVALID_FABRIC_ADDR to avoid encoding twice // - if (pLocals->bFlaImport || (memdescGetAddressSpace(pLocals->pTempMemDesc) == ADDR_FABRIC) || + if (pLocals->bFlaImport || + (memdescGetAddressSpace(pLocals->pTempMemDesc) == ADDR_FABRIC_MC) || (memdescGetAddressSpace(pLocals->pTempMemDesc) == ADDR_FABRIC_V2)) { pLocals->fabricAddr = NVLINK_INVALID_FABRIC_ADDR; @@ -953,7 +994,8 @@ dmaAllocMapping_GM107 pLocals->peerNumber, pLocals->fabricAddr, pLocals->deferInvalidate, - NV_FALSE); + NV_FALSE, + pLocals->pageSize); if (NV_OK != status) { NV_PRINTF(LEVEL_ERROR, @@ -1100,19 +1142,26 @@ dmaFreeMapping_GM107 return status; } - dmaUpdateVASpace_HAL(pGpu, pDma, - pVAS, - pTempMemDesc, - NULL, - vaLo, vaHi, - DMA_UPDATE_VASPACE_FLAGS_UPDATE_VALID, // only change validity - NULL, 0, - NULL, 0, - NV_MMU_PTE_VALID_FALSE, - kgmmuGetHwPteApertureFromMemdesc(GPU_GET_KERNEL_GMMU(pGpu), pTempMemDesc), 0, - NVLINK_INVALID_FABRIC_ADDR, - deferInvalidate, - NV_FALSE); + status = dmaUpdateVASpace_HAL(pGpu, pDma, + pVAS, + pTempMemDesc, + NULL, + vaLo, vaHi, + DMA_UPDATE_VASPACE_FLAGS_UPDATE_VALID, // only change validity + NULL, 0, + NULL, 0, + NV_MMU_PTE_VALID_FALSE, + kgmmuGetHwPteApertureFromMemdesc(GPU_GET_KERNEL_GMMU(pGpu), pTempMemDesc), 0, + NVLINK_INVALID_FABRIC_ADDR, + deferInvalidate, + NV_FALSE, + pageSize); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "error updating VA space.\n"); + vaspaceFree(pVAS, vaLo); + return status; + } } SLI_LOOP_END } @@ -1388,13 +1437,13 @@ _gmmuWalkCBMapNextEntries_Direct if (pMemorySystemConfig->bUseRawModeComptaglineAllocation && pMemorySystemConfig->bDisablePlcForCertainOffsetsBug3046774 && !memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_DISALLOW_PLC, pIter->comprInfo.kind) && - !kmemsysIsPagePLCable_HAL(pGpu, pKernelMemorySystem, (pIter->surfaceOffset + pIter->currIdx * RM_PAGE_SIZE), pageSize)) + !kmemsysIsPagePLCable_HAL(pGpu, pKernelMemorySystem, (pIter->surfaceOffset + pIter->currIdx * pTarget->pageArrayGranularity), pageSize)) { bIsWarApplied = NV_TRUE; memmgrGetDisablePlcKind_HAL(pMemoryManager, &pIter->comprInfo.kind); } kgmmuFieldSetKindCompTags(GPU_GET_KERNEL_GMMU(pGpu), pIter->pFmt, pLevelFmt, &pIter->comprInfo, pIter->physAddr, - pIter->surfaceOffset + pIter->currIdx * RM_PAGE_SIZE, + pIter->surfaceOffset + pIter->currIdx * pTarget->pageArrayGranularity, i, entry.v8); // // restore the kind to PLC if changd, since kind is associated with entire surface, and the WAR applies to @@ -1440,8 +1489,10 @@ _gmmuWalkCBMapNextEntries_Direct // // pPageArray deals in 4K pages. // So increment by the ratio of mapping page size to 4K + // -- + // The above assumption will be invalid upon implementation of memdesc dynamic page arrays // - pIter->currIdx += (NvU32)(pageSize / RM_PAGE_SIZE); + pIter->currIdx += (NvU32)(pageSize / pTarget->pageArrayGranularity); } *pProgress = entryIndexHi - entryIndexLo + 1; @@ -1540,7 +1591,8 @@ dmaUpdateVASpace_GF100 NvU32 peer, NvU64 fabricAddr, NvU32 deferInvalidate, - NvBool bSparse + NvBool bSparse, + NvU32 pageSize ) { KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); @@ -1554,7 +1606,6 @@ dmaUpdateVASpace_GF100 NvU32 priv; NvU32 writeDisable; NvU32 readDisable; - NvU32 pageSize = 0; NvU32 vaSpaceBigPageSize = 0; const MEMORY_SYSTEM_STATIC_CONFIG *pMemorySystemConfig = kmemsysGetStaticConfig(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)); @@ -1751,17 +1802,18 @@ dmaUpdateVASpace_GF100 } // MMU_MAP_CTX - mapTarget.pLevelFmt = mmuFmtFindLevelWithPageShift(pFmt->pRoot, + mapTarget.pLevelFmt = mmuFmtFindLevelWithPageShift(pFmt->pRoot, BIT_IDX_32(pageSize)); - mapTarget.pIter = &mapIter; - mapTarget.MapNextEntries = _gmmuWalkCBMapNextEntries_RmAperture; + mapTarget.pIter = &mapIter; + mapTarget.MapNextEntries = _gmmuWalkCBMapNextEntries_RmAperture; + mapTarget.pageArrayGranularity = pMemDesc->pageArrayGranularity; //MMU_MAP_ITER - mapIter.pFmt = pFmt; - mapIter.pPageArray = pPageArray; - mapIter.surfaceOffset = surfaceOffset; - mapIter.comprInfo = *pComprInfo; - mapIter.overMapModulus = overmapPteMod; + mapIter.pFmt = pFmt; + mapIter.pPageArray = pPageArray; + mapIter.surfaceOffset = surfaceOffset; + mapIter.comprInfo = *pComprInfo; + mapIter.overMapModulus = overmapPteMod; mapIter.bReadPtes = readPte; mapIter.kindNoCompr = kindNoCompression; mapIter.bCompr = memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_COMPRESSIBLE, pComprInfo->kind); @@ -1804,6 +1856,10 @@ dmaUpdateVASpace_GF100 ptePcfSw |= readOnly ? (1 << SW_MMU_PCF_RO_IDX) : 0; ptePcfSw |= tlbLock ? (1 << SW_MMU_PCF_NOATOMIC_IDX) : 0; ptePcfSw |= !priv ? (1 << SW_MMU_PCF_REGULAR_IDX) : 0; + if ((memdescGetAddressSpace(pMemDesc) == ADDR_FABRIC_MC)) + { + ptePcfSw |= (1 << SW_MMU_PCF_ACE_IDX); + } } else { @@ -2194,7 +2250,8 @@ dmaMapBuffer_GM107 NV_MMU_PTE_VALID_TRUE, aperture, 0, NVLINK_INVALID_FABRIC_ADDR, - NV_FALSE, NV_FALSE); + NV_FALSE, NV_FALSE, + pageSize); if (status != NV_OK) { diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/dma.c b/src/nvidia/src/kernel/gpu/mem_mgr/dma.c index 1f83f3020..0b67bf81c 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/dma.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/dma.c @@ -31,7 +31,6 @@ #include "core/core.h" #include "gpu/gpu.h" #include "gpu/mem_mgr/virt_mem_allocator.h" -#include "lib/base_utils.h" #include "rmapi/control.h" #include "gpu/mem_mgr/virt_mem_allocator_common.h" #include "os/os.h" @@ -48,6 +47,7 @@ #include "ctrl/ctrl208f/ctrl208fdma.h" #include "vgpu/rpc.h" #include "core/locks.h" +#include "virtualization/kernel_hostvgpudeviceapi.h" #include "gpu/subdevice/subdevice_diag.h" #include "gpu/device/device.h" #include "gpu/subdevice/subdevice.h" @@ -96,10 +96,12 @@ dmaAllocMap_IMPL p2p = DRF_VAL(OS46, _FLAGS, _P2P_ENABLE, pDmaMappingInfo->Flags); // - // By default ADDR_FABRIC_V2 should be mapped as peer memory. So, don't honor + // By default any fabric memory should be mapped as peer memory. So, don't honor // any P2P flags. // - if (memdescGetAddressSpace(pDmaMappingInfo->pMemDesc) == ADDR_FABRIC_V2) + if ( + (memdescGetAddressSpace(pDmaMappingInfo->pMemDesc) == ADDR_FABRIC_MC) || + (memdescGetAddressSpace(pDmaMappingInfo->pMemDesc) == ADDR_FABRIC_V2)) { p2p = 0; } @@ -262,7 +264,7 @@ deviceCtrlCmdDmaGetPteInfo_IMPL CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams->pLegacyParams; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); NV_CHECK_OK_OR_RETURN(LEVEL_WARNING, vaspaceGetByHandleOrDeviceDefault(RES_GET_CLIENT(pDevice), pRmCtrlParams->hObject, @@ -296,12 +298,11 @@ deviceCtrlCmdDmaUpdatePde2_IMPL NvBool bBcState = NV_TRUE; CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); - if ( - (pCallContext->secInfo.privLevel < RS_PRIV_LEVEL_KERNEL)) + if (pCallContext->secInfo.privLevel < RS_PRIV_LEVEL_KERNEL) { - return NV_ERR_INSUFFICIENT_PERMISSIONS; + return NV_ERR_INSUFFICIENT_PERMISSIONS; } if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu)) @@ -365,7 +366,7 @@ deviceCtrlCmdDmaSetVASpaceSize_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); OBJVASPACE *pVAS = NULL; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); NV_CHECK_OK_OR_RETURN(LEVEL_WARNING, vaspaceGetByHandleOrDeviceDefault(RES_GET_CLIENT(pDevice), RES_GET_HANDLE(pDevice), @@ -424,7 +425,7 @@ deviceCtrlCmdDmaSetPageDirectory_IMPL NV_STATUS status = NV_OK; NvBool bBcState = NV_FALSE; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); if (IS_VIRTUAL(pGpu) || IS_GSP_CLIENT(pGpu)) { @@ -522,7 +523,7 @@ deviceCtrlCmdDmaUnsetPageDirectory_IMPL NvBool bBcState = NV_FALSE; NV_STATUS status = NV_OK; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu)) { @@ -607,7 +608,7 @@ deviceCtrlCmdDmaSetPteInfo_IMPL OBJVASPACE *pVAS = NULL; NV_STATUS status = NV_OK; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); NV_CHECK_OK_OR_RETURN(LEVEL_WARNING, vaspaceGetByHandleOrDeviceDefault(RES_GET_CLIENT(pDevice), RES_GET_HANDLE(pDevice), @@ -642,7 +643,7 @@ deviceCtrlCmdDmaFlush_IMPL FB_CACHE_OP cacheOp = FB_CACHE_OP_UNDEFINED; NV_STATUS status = NV_OK; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); NV_PRINTF(LEVEL_INFO, "Flush op invoked with target Unit 0x%x\n", flushParams->targetUnit); @@ -714,7 +715,7 @@ deviceCtrlCmdDmaAdvSchedGetVaCaps_IMPL const MEMORY_SYSTEM_STATIC_CONFIG *pMemorySystemConfig = kmemsysGetStaticConfig(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); NV_CHECK_OK_OR_RETURN(LEVEL_WARNING, vaspaceGetByHandleOrDeviceDefault(RES_GET_CLIENT(pDevice), RES_GET_HANDLE(pDevice), @@ -748,7 +749,7 @@ deviceCtrlCmdDmaGetPdeInfo_IMPL CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams->pLegacyParams; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); // // vGPU: @@ -793,7 +794,7 @@ deviceCtrlCmdDmaSetDefaultVASpace_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); NV_STATUS status = NV_OK; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); NV_ASSERT_OK_OR_RETURN( deviceSetDefaultVASpace( @@ -883,7 +884,7 @@ subdeviceCtrlCmdDmaGetInfo_IMPL NvU32 i; NvU32 data; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); // error checck if (pDmaInfoParams->dmaInfoTblSize > NV2080_CTRL_DMA_GET_INFO_MAX_ENTRIES) @@ -933,7 +934,7 @@ deviceCtrlCmdDmaInvalidateTLB_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); OBJVASPACE *pVAS = NULL; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); // // vGPU: @@ -995,7 +996,7 @@ deviceCtrlCmdDmaGetCaps_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); VirtMemAllocator *pDma = GPU_GET_DMA(pGpu); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); // sanity check array size if (pDmaCapsParams->capsTblSize != NV0080_CTRL_DMA_CAPS_TBL_SIZE) @@ -1041,7 +1042,7 @@ deviceCtrlCmdDmaEnablePrivilegedRange_IMPL NV0080_CTRL_DMA_ENABLE_PRIVILEGED_RANGE_PARAMS *pParams ) { - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); if (pParams->hVASpace != NV01_NULL_OBJECT) { @@ -1186,47 +1187,3 @@ dmaPageArrayGetPhysAddr return addr; } - -/*! - * Determine if the upper half for the comptag can be used for this page. - * - * @param[in] pDma VirtMemAllocator object pointer - * @param[in] pteIndex PTE index - * @param[in] pageSize Page size - * - * @returns Whether the upper half can be used or not. - */ -NvBool -dmaUseCompTagLineUpperHalf_IMPL(VirtMemAllocator *pDma, NvU32 pteIndex, NvU32 pageSize) -{ - NvBool bUseUpperHalf = NV_FALSE; - OBJGPU *pGpu = ENG_GET_GPU(pDma); - const MEMORY_SYSTEM_STATIC_CONFIG *pMemorySystemConfig = - kmemsysGetStaticConfig(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)); - - if (pDma->getProperty(pDma, PDB_PROP_DMA_ENABLE_FULL_COMP_TAG_LINE)) - { - NvU32 subIndexShift; - - if (pMemorySystemConfig->comprPageShift >= NvU64_LO32(nvLogBase2(pageSize))) - { - subIndexShift = pMemorySystemConfig->comprPageShift - NvU64_LO32(nvLogBase2(pageSize)); - } - else - { - NV_ASSERT_OR_RETURN(0, NV_FALSE); - } - - // - // (SubIndexShift - 1) is half the compression page size (64 KB). - // Shifting by that gives the number of PTEs that span a 64 KB page. - // The 0th bit gives comptag subindex. - // - if (subIndexShift) - { - bUseUpperHalf = !!((pteIndex >> (subIndexShift - 1)) & 1); - } - } - - return bUseUpperHalf; -} diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/fbsr.c b/src/nvidia/src/kernel/gpu/mem_mgr/fbsr.c index cf1c6cffc..5d3e354e8 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/fbsr.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/fbsr.c @@ -33,6 +33,10 @@ fbsrObjectInit_IMPL(OBJFBSR *pFbsr, NvU32 type) pFbsr->type = type; pFbsr->bValid = NV_FALSE; pFbsr->bInitialized = NV_FALSE; + pFbsr->pRegionRecords = NULL; + pFbsr->numRegions = 0; + pFbsr->regionRecordIndex = 0; + return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/heap.c b/src/nvidia/src/kernel/gpu/mem_mgr/heap.c index db4c2ce3a..501085d45 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/heap.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/heap.c @@ -301,7 +301,8 @@ static NV_STATUS heapReserveRegion NvU64 offset, NvU64 size, MEMORY_DESCRIPTOR **ppMemDesc, - NvBool isRmRsvdRegion + NvBool isRmRsvdRegion, + NvBool bProtected ) { NV_STATUS rmStatus = NV_OK; @@ -335,6 +336,9 @@ static NV_STATUS heapReserveRegion allocData.size = NV_MIN(size, (heapSize - offset)); allocData.offset = offset; + if (bProtected) + allocData.flags |= NVOS32_ALLOC_FLAGS_PROTECTED; + pFbAllocInfo = portMemAllocNonPaged(sizeof(FB_ALLOC_INFO)); NV_ASSERT_TRUE_OR_GOTO(rmStatus, pFbAllocInfo != NULL, NV_ERR_NO_MEMORY, done); @@ -612,7 +616,8 @@ NV_STATUS heapInitInternal_IMPL fbRegionBase, (pFbRegion->limit - fbRegionBase + 1), &pMemDesc, - pFbRegion->bRsvdRegion); + pFbRegion->bRsvdRegion, + pFbRegion->bProtected); if (status != NV_OK || pMemDesc == NULL) { @@ -650,13 +655,16 @@ NV_STATUS heapInitInternal_IMPL (memmgrIsPmaInitialized(pMemoryManager))) { MEMORY_DESCRIPTOR *pMemDesc = NULL; + NvBool bProtected = NV_FALSE; + status = heapReserveRegion( pMemoryManager, pHeap, base, size, &pMemDesc, - NV_FALSE); + NV_FALSE, + bProtected); if (status != NV_OK || pMemDesc == NULL) { @@ -771,10 +779,7 @@ heapDestruct_IMPL if (pHeap->heapType == HEAP_TYPE_PHYS_MEM_SUBALLOCATOR) { pPmsaMemDesc = ((PHYS_MEM_SUBALLOCATOR_DATA *)(pHeap->pHeapTypeSpecificData))->pMemDesc; - if (pPmsaMemDesc != NULL) - { - memdescDestroy(pPmsaMemDesc); - } + memdescDestroy(pPmsaMemDesc); } portMemFree(pHeap->pHeapTypeSpecificData); pHeap->pHeapTypeSpecificData = NULL; @@ -3156,7 +3161,7 @@ NV_STATUS heapHwAlloc_IMPL *pAttr2 = pFbAllocInfo->retAttr2; failed: - portMemFree(pFbAllocInfo->pageFormat); + portMemFree(pFbAllocPageFormat); portMemFree(pFbAllocInfo); return status; @@ -4664,7 +4669,7 @@ heapAddRef_IMPL if (pHeap == NULL) return 0; - return (NvU32)portAtomicIncrementS32((NvS32*)&(pHeap->refCount)); + return portAtomicExIncrementU64(&pHeap->refCount); } /*! @@ -4681,12 +4686,12 @@ heapRemoveRef_IMPL Heap *pHeap ) { - NvU32 refCount = 0; + NvU64 refCount = 0; if (pHeap == NULL) return 0; - refCount = (NvU32)portAtomicDecrementS32((NvS32*)&(pHeap->refCount)); + refCount = portAtomicExDecrementU64(&pHeap->refCount); if (refCount == 0) { objDelete(pHeap); diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_ctrl.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_ctrl.c index 4f8ef92b6..6b6d5a89c 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_ctrl.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_ctrl.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2004-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -88,19 +88,6 @@ memCtrlCmdGetSurfaceCompressionCoverageLvm_IMPL return status; } -NV_STATUS -memCtrlCmdGetSurfacePartitionStrideLvm_IMPL -( - Memory *pMemory, - NV0041_CTRL_GET_SURFACE_PARTITION_STRIDE_PARAMS *pParams -) -{ - // Only partitionStride == 256B is supported by RM. - pParams->partitionStride = 256; - - return NV_OK; -} - NV_STATUS memCtrlCmdGetSurfaceInfoLvm_IMPL ( @@ -132,15 +119,23 @@ memCtrlCmdGetSurfaceInfoLvm_IMPL { case NV0041_CTRL_SURFACE_INFO_INDEX_ATTRS: { - if (pMemory->pHwResource->attr & DRF_DEF(OS32, _ATTR, _COMPR, _REQUIRED)) + if ((pMemory->pHwResource != NULL) && + pMemory->pHwResource->attr & DRF_DEF(OS32, _ATTR, _COMPR, _REQUIRED)) data |= NV0041_CTRL_SURFACE_INFO_ATTRS_COMPR; - if (pMemory->pHwResource->attr & DRF_DEF(OS32, _ATTR, _ZCULL, _REQUIRED)) + if ((pMemory->pHwResource != NULL) && + pMemory->pHwResource->attr & DRF_DEF(OS32, _ATTR, _ZCULL, _REQUIRED)) data |= NV0041_CTRL_SURFACE_INFO_ATTRS_ZCULL; break; } case NV0041_CTRL_SURFACE_INFO_INDEX_COMPR_COVERAGE: { - if (pMemory->pHwResource->attr & DRF_DEF(OS32, _ATTR, _COMPR, _REQUIRED)) + // + // adding check for pHwResource, since host managed HW resource + // gets allocated only when ATTR is set to COMPR_REQUIRED + // + if ((pMemory->pHwResource != NULL) && + pMemory->pHwResource->attr & + DRF_DEF(OS32, _ATTR, _COMPR, _REQUIRED)) { zero = 0; status = memmgrGetSurfacePhysAttr_HAL(pGpu, pMemoryManager, @@ -169,7 +164,8 @@ memCtrlCmdGetSurfaceInfoLvm_IMPL } case NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_ATTR: { - data = pMemory->pHwResource->attr & (DRF_SHIFTMASK(NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE) | DRF_SHIFTMASK(NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY)); + if (pMemory->pHwResource != NULL) + data = pMemory->pHwResource->attr & (DRF_SHIFTMASK(NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE) | DRF_SHIFTMASK(NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY)); break; } case NV0041_CTRL_SURFACE_INFO_INDEX_ADDR_SPACE_TYPE: diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c index cf9135261..cd834937c 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c @@ -118,6 +118,8 @@ static NV_STATUS _memdescSetSubAllocatorFlag NvBool bSet ) { + NV_ASSERT_OR_RETURN(pGpu != NULL, NV_ERR_INVALID_ARGUMENT); + if (!bSet) { NV_PRINTF(LEVEL_ERROR, @@ -133,10 +135,17 @@ static NV_STATUS _memdescSetSubAllocatorFlag { Heap *pHeap = pMemDesc->pHeap; + NvBool bForceSubheap = NV_FALSE; NV_ASSERT(pHeap == NULL || pHeap->heapType == HEAP_TYPE_PHYS_MEM_SUBALLOCATOR); + + if (pMemDesc->_flags & MEMDESC_FLAGS_FORCE_ALLOC_FROM_SUBHEAP) + { + bForceSubheap = NV_TRUE; + } + if (pHeap == NULL) - pHeap = memmgrGetDeviceSuballocator(GPU_GET_MEMORY_MANAGER(pGpu), NV_FALSE); + pHeap = memmgrGetDeviceSuballocator(GPU_GET_MEMORY_MANAGER(pGpu), bForceSubheap); if (pHeap->heapType == HEAP_TYPE_PHYS_MEM_SUBALLOCATOR) { @@ -158,6 +167,20 @@ static NV_STATUS _memdescSetGuestAllocatedFlag NvBool bSet ) { +// for VGPU header scrubbing in Open Orin package + + NV_ASSERT_OR_RETURN(pGpu != NULL, NV_ERR_INVALID_ARGUMENT); + + if (!bSet) + { + NV_PRINTF(LEVEL_ERROR, + "Unsetting MEMDESC_FLAGS_GUEST_ALLOCATED not supported\n"); + NV_ASSERT(0); + return NV_ERR_INVALID_ARGUMENT; + } + + NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &pMemDesc->gfid)); + pMemDesc->_flags |= MEMDESC_FLAGS_GUEST_ALLOCATED; return NV_OK; } @@ -203,6 +226,8 @@ memdescCreate MEMORY_DESCRIPTOR *pMemDesc; NvU64 allocSize, MdSize, PageCount; NvU32 gpuCacheAttrib = NV_MEMORY_UNCACHED; + NV_STATUS status = NV_OK; + allocSize = Size; @@ -232,7 +257,7 @@ memdescCreate } } - if (RMCFG_FEATURE_PLATFORM_MODS) + if (RMCFG_FEATURE_PLATFORM_MODS || IsT194(pGpu)) { if ( (AddressSpace == ADDR_FBMEM) && !(Flags & MEMDESC_ALLOC_FLAGS_PROTECTED) && @@ -259,7 +284,7 @@ memdescCreate } // - // Must allocate a larger buffer to store the PTEs for noncontiguous memory + // // Note that we allocate one extra PTE, since we don't know what the PteAdjust // is yet; if the PteAdjust is zero, we simply won't use it. This is in the // MEMORY_DESCRIPTOR structure definition. @@ -339,6 +364,12 @@ memdescCreate pMemDesc->bUsingSuballocator = NV_FALSE; pMemDesc->bDeferredFree = NV_FALSE; + pMemDesc->libosRegionHandle = 0; + pMemDesc->baseVirtualAddress = 0; + + // parameter to determine page granularity + pMemDesc->pageArrayGranularity = RM_PAGE_SIZE; + memdescSetCpuCacheAttrib(pMemDesc, CpuCacheAttrib); // Set any additional flags @@ -356,18 +387,29 @@ memdescCreate } else if (Flags & MEMDESC_FLAGS_OWNED_BY_CURRENT_DEVICE) { - NV_ASSERT_OK_OR_RETURN(_memdescSetSubAllocatorFlag(pGpu, pMemDesc, NV_TRUE)); + NV_ASSERT_OK_OR_GOTO(status, _memdescSetSubAllocatorFlag(pGpu, pMemDesc, NV_TRUE), failed); } // In case of guest allocated memory, just initialize GFID if (Flags & MEMDESC_FLAGS_GUEST_ALLOCATED) { - NV_ASSERT_OK_OR_RETURN(_memdescSetGuestAllocatedFlag(pGpu, pMemDesc, NV_TRUE)); + NV_ASSERT_OK_OR_GOTO(status, _memdescSetGuestAllocatedFlag(pGpu, pMemDesc, NV_TRUE), failed); } - *ppMemDesc = pMemDesc; +failed: + if (status != NV_OK) + { + if (!(Flags & MEMDESC_FLAGS_PRE_ALLOCATED)) + { + portMemFree(pMemDesc); + } + } + else + { + *ppMemDesc = pMemDesc; + } - return NV_OK; + return status; } /*! @@ -698,7 +740,8 @@ _memdescAllocInternal // 1625121). For now they are parallel, and only one will be // used. // - if (!memdescGetFlag(pMemDesc, MEMDESC_FLAGS_CPU_ONLY)) + if (!memdescGetFlag(pMemDesc, MEMDESC_FLAGS_CPU_ONLY) && + !memdescGetFlag(pMemDesc, MEMDESC_FLAGS_SKIP_IOMMU_MAPPING)) { status = memdescMapIommu(pMemDesc, pGpu->busInfo.iovaspaceId); if (status != NV_OK) @@ -731,7 +774,7 @@ _memdescAllocInternal if (offset) { - NV_ASSERT((pMemDesc->PageCount * RM_PAGE_SIZE - pMemDesc->Size) >= offset); + NV_ASSERT((pMemDesc->PageCount * pMemDesc->pageArrayGranularity - pMemDesc->Size) >= offset); NV_ASSERT(pMemDesc->PteAdjust == 0); pMemDesc->PteAdjust += NvU64_LO32(pMemDesc->Alignment - offset); } @@ -874,7 +917,8 @@ _memdescAllocInternal // depend on this. In the future we will have the PageCount be accurate. // pMemDesc->Size = requestedSize; - pMemDesc->PageCount = ((pMemDesc->Size + pMemDesc->PteAdjust + RM_PAGE_SIZE - 1) >> RM_PAGE_SHIFT); + pMemDesc->PageCount = ((pMemDesc->Size + pMemDesc->PteAdjust + pMemDesc->pageArrayGranularity - 1) >> + BIT_IDX_32(pMemDesc->pageArrayGranularity)); } // We now have the memory pMemDesc->Allocated = 1; @@ -938,7 +982,7 @@ memdescAlloc // TO DO: Make this an error once existing allocations are cleaned up. // After that pHeap selection can be moved to memdescAllocInternal() // - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_WARNING, "WARNING sysmem alloc on GSP firmware\n"); pMemDesc->_addressSpace = ADDR_FBMEM; pMemDesc->pHeap = GPU_GET_HEAP(pGpu); @@ -969,7 +1013,14 @@ memdescAlloc } else if (pMemDesc->_flags & MEMDESC_FLAGS_OWNED_BY_CURRENT_DEVICE) { - pMemDesc->pHeap = memmgrGetDeviceSuballocator(GPU_GET_MEMORY_MANAGER(pGpu), NV_FALSE); + NvBool bForceSubheap = NV_FALSE; + + if (pMemDesc->_flags & MEMDESC_FLAGS_FORCE_ALLOC_FROM_SUBHEAP) + { + bForceSubheap = NV_TRUE; + } + + pMemDesc->pHeap = memmgrGetDeviceSuballocator(GPU_GET_MEMORY_MANAGER(pGpu), bForceSubheap); } else if (GPU_GET_MEMORY_MANAGER(pGpu) != NULL && RMCFG_MODULE_HEAP && @@ -1292,8 +1343,8 @@ _memdescFreeInternal SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) { KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); - NV_ASSERT_OK(kmemsysCacheOp_HAL(pGpu, pKernelMemorySystem, pMemDesc, - FB_CACHE_SYSTEM_MEMORY, + NV_ASSERT_OK(kmemsysCacheOp_HAL(pGpu, pKernelMemorySystem, pMemDesc, + FB_CACHE_SYSTEM_MEMORY, FB_CACHE_INVALIDATE)); } SLI_LOOP_END @@ -1306,12 +1357,12 @@ _memdescFreeInternal oldSize = pMemDesc->Size; pMemDesc->Size = pMemDesc->ActualSize; - pMemDesc->PageCount = ((pMemDesc->ActualSize + RM_PAGE_SIZE-1) >> RM_PAGE_SHIFT); + pMemDesc->PageCount = ((pMemDesc->ActualSize + pMemDesc->pageArrayGranularity - 1) >> BIT_IDX_64(pMemDesc->pageArrayGranularity)); osFreePages(pMemDesc); pMemDesc->Size = oldSize; - pMemDesc->PageCount = ((oldSize + RM_PAGE_SIZE-1) >> RM_PAGE_SHIFT); + pMemDesc->PageCount = ((oldSize + pMemDesc->pageArrayGranularity - 1) >> BIT_IDX_64(pMemDesc->pageArrayGranularity)); break; @@ -1401,7 +1452,7 @@ memdescFree // The memdesc is being freed so destroy all of its IOMMU mappings. _memdescFreeIommuMappings(pMemDesc); } - + if (pMemDesc->_addressSpace != ADDR_FBMEM && pMemDesc->_addressSpace != ADDR_SYSMEM) { @@ -2432,7 +2483,7 @@ memdescCreateSubMem // remove the need for several hacks, including this one. // NV_ASSERT(i > 0); - pMemDescNew->_pteArray[i] = pMemDescNew->_pteArray[i - 1] + RM_PAGE_SIZE; + pMemDescNew->_pteArray[i] = pMemDescNew->_pteArray[i - 1] + pMemDescNew->pageArrayGranularity; } } } @@ -2440,7 +2491,8 @@ memdescCreateSubMem if ((pMemDesc->_addressSpace == ADDR_SYSMEM) && !memdescGetFlag(memdescGetMemDescFromGpu(pMemDesc, pGpu), MEMDESC_FLAGS_CPU_ONLY) && - !memdescGetFlag(memdescGetMemDescFromGpu(pMemDesc, pGpu), MEMDESC_FLAGS_MAP_SYSCOH_OVER_BAR1)) + !memdescGetFlag(memdescGetMemDescFromGpu(pMemDesc, pGpu), MEMDESC_FLAGS_MAP_SYSCOH_OVER_BAR1) && + !memdescGetFlag(memdescGetMemDescFromGpu(pMemDesc, pGpu), MEMDESC_FLAGS_SKIP_IOMMU_MAPPING)) { // // For different IOVA spaces, the IOMMU mapping will often not be a @@ -2515,6 +2567,114 @@ _memIsSriovMappingsEnabled (pMemDesc->_flags & MEMDESC_FLAGS_GUEST_ALLOCATED)); } +/*! + * Fills pGpaEntries with numEntries GPAs from pMemDesc->_pteArray starting at + * the given starting index. For physically contiguous memdescs, fills with + * RM_PAGE_SIZE strides. + */ +static void +_memdescFillGpaEntriesForSpaTranslation +( + PMEMORY_DESCRIPTOR pMemDesc, + RmPhysAddr *pGpaEntries, + NvU32 start, + NvU32 numEntries +) +{ + if (pMemDesc->_flags & MEMDESC_FLAGS_PHYSICALLY_CONTIGUOUS) + { + NvU32 i; + + for (i = 0; i < numEntries; i++) + { + pGpaEntries[i] = pMemDesc->_pteArray[0] + (((RmPhysAddr) (start + i)) * pMemDesc->pageArrayGranularity); + } + } + else + { + portMemCopy(&pGpaEntries[0], numEntries * sizeof(pGpaEntries[0]), + &pMemDesc->_pteArray[start], numEntries * sizeof(pGpaEntries[0])); + } +} + +/*! + * This function translates GPA -> SPA for a given memdesc and updates pPteSpaMappings with list of SPA addresses. + * If memdesc is contiguous and if the translated SPA count > 1, this function fails for now. + */ +NV_STATUS +_memdescUpdateSpaArray +( + PMEMORY_DESCRIPTOR pMemDesc +) +{ + NV_STATUS status = NV_OK; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pMemDesc->pGpu); + NvU32 allocCnt; + NvU32 i; + NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS *pParams = NULL; + + if ((pMemDesc->pPteSpaMappings) || (!pMemDesc->PageCount)) + { + status = NV_OK; + goto _memUpdateSpArray_exit; + } + + allocCnt = memdescGetPteArraySize(pMemDesc, AT_PA); + + // Allocate the array to hold pages up to PageCount + pMemDesc->pPteSpaMappings = portMemAllocNonPaged(sizeof(RmPhysAddr) * allocCnt); + if (pMemDesc->pPteSpaMappings == NULL) + { + status = NV_ERR_NO_MEMORY; + goto _memUpdateSpArray_exit; + } + + pParams = portMemAllocStackOrHeap(sizeof(*pParams)); + if (pParams == NULL) + { + status = NV_ERR_NO_MEMORY; + goto _memUpdateSpArray_exit; + } + portMemSet(pParams, 0, sizeof(*pParams)); + + pParams->gfid = pMemDesc->gfid; + + for (i = 0; i < allocCnt; i += NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES) + { + NvU32 numEntries = NV_MIN(allocCnt - i, NV2080_CTRL_INTERNAL_VMMU_MAX_SPA_FOR_GPA_ENTRIES); + pParams->numEntries = numEntries; + + _memdescFillGpaEntriesForSpaTranslation(pMemDesc, &pParams->gpaEntries[0], + i, numEntries); + + status = pRmApi->Control(pRmApi, + pMemDesc->pGpu->hInternalClient, + pMemDesc->pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES, + pParams, + sizeof(*pParams)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Getting SPA for GPA failed: GFID=%u, GPA=0x%llx\n", + pMemDesc->gfid, pMemDesc->_pteArray[i]); + goto _memUpdateSpArray_exit; + } + + portMemCopy(&pMemDesc->pPteSpaMappings[i], numEntries * sizeof(pParams->spaEntries[0]), + &pParams->spaEntries[0], numEntries * sizeof(pParams->spaEntries[0])); + } + +_memUpdateSpArray_exit: + if (status != NV_OK) + { + portMemFree(pMemDesc->pPteSpaMappings); + pMemDesc->pPteSpaMappings = NULL; + } + portMemFreeStackOrHeap(pParams); + + return status; +} + /*! * @brief Return the physical addresses of pMemdesc * @@ -2541,6 +2701,7 @@ void memdescGetPhysAddrsForGpu(MEMORY_DESCRIPTOR *pMemDesc, // MMU context. (see bug 1625121) // NvU64 i; + NvU64 pageIndex; RmPhysAddr *pteArray = memdescGetPteArrayForGpu(pMemDesc, pGpu, addressTranslation); const NvBool contiguous = (memdescGetPteArraySize(pMemDesc, addressTranslation) == 1); @@ -2555,8 +2716,8 @@ void memdescGetPhysAddrsForGpu(MEMORY_DESCRIPTOR *pMemDesc, } else { - NvU32 PageIndex = (NvU32)(offset >> RM_PAGE_SHIFT); - pAddresses[i] = pteArray[PageIndex] + (offset & RM_PAGE_MASK); + pageIndex = offset >> RM_PAGE_SHIFT; + pAddresses[i] = pteArray[pageIndex] + (offset & RM_PAGE_MASK); } offset += stride; @@ -2747,6 +2908,19 @@ memdescGetPteArrayForGpu case AT_VALUE(AT_PA): { + if (pGpu != NULL) + { + if (pMemDesc->_addressSpace == ADDR_FBMEM) + { + if (_memIsSriovMappingsEnabled(pMemDesc)) + { + if (!pMemDesc->pPteSpaMappings) + _memdescUpdateSpaArray(pMemDesc); + + return pMemDesc->pPteSpaMappings; + } + } + } } case AT_VALUE(AT_GPU): { @@ -3645,7 +3819,7 @@ NvBool memdescCheckContiguity(PMEMORY_DESCRIPTOR pMemDesc, ADDRESS_TRANSLATION a { for (i = 0; i < (pMemDesc->PageCount - 1); i++) { - if ((memdescGetPte(pMemDesc, addressTranslation, i) + RM_PAGE_SIZE) != + if ((memdescGetPte(pMemDesc, addressTranslation, i) + pMemDesc->pageArrayGranularity) != memdescGetPte(pMemDesc, addressTranslation, i + 1)) return NV_FALSE; } @@ -3950,7 +4124,7 @@ NV_STATUS memdescMapIommu { physAddr = memdescGetPte(pMemDesc, AT_GPU, i); if ((physAddr < dmaWindowStartAddr) || - (physAddr + (RM_PAGE_SIZE - 1) > dmaWindowEndAddr)) + (physAddr + (pMemDesc->pageArrayGranularity - 1) > dmaWindowEndAddr)) { NV_PRINTF(LEVEL_ERROR, "0x%llx is not addressable by GPU 0x%x [0x%llx-0x%llx]\n", @@ -4222,6 +4396,7 @@ memdescRegisterToGSP Memory *pMemory = NULL; RsResourceRef *pMemoryRef = NULL; MEMORY_DESCRIPTOR *pMemDesc = NULL; + NvU32 hClass; // Nothing to do without GSP if (!IS_GSP_CLIENT(pGpu)) @@ -4247,10 +4422,13 @@ memdescRegisterToGSP !memdescHasSubDeviceMemDescs(pMemDesc), NV_ERR_INVALID_STATE); - // Check: SYSMEM only - NV_CHECK_OR_RETURN(LEVEL_ERROR, - memdescGetAddressSpace(pMemDesc) == ADDR_SYSMEM, - NV_ERR_INVALID_STATE); + // Check: SYSMEM or FBMEM only + if (memdescGetAddressSpace(pMemDesc) == ADDR_FBMEM) + hClass = NV01_MEMORY_LIST_FBMEM; + else if (memdescGetAddressSpace(pMemDesc) == ADDR_SYSMEM) + hClass = NV01_MEMORY_LIST_SYSTEM; + else + return NV_ERR_INVALID_STATE; NvU32 os02Flags = 0; @@ -4258,12 +4436,12 @@ memdescRegisterToGSP RmDeprecatedConvertOs32ToOs02Flags(pMemory->Attr, pMemory->Attr2, pMemory->Flags, - &os02Flags)); + &os02Flags)); NV_RM_RPC_ALLOC_MEMORY(pGpu, hClient, hParent, hMemory, - NV01_MEMORY_SYSTEM_OS_DESCRIPTOR, + hClass, os02Flags, pMemDesc, status); @@ -4339,3 +4517,93 @@ memdescDeregisterFromGSP return status; } + +void +memdescSetName(OBJGPU *pGpu, MEMORY_DESCRIPTOR *pMemDesc, const char *name, const char* suffix) +{ + return; +} + +NV_STATUS +memdescSendMemDescToGSP(OBJGPU *pGpu, MEMORY_DESCRIPTOR *pMemDesc, NvHandle *pHandle) +{ + NV_STATUS status = NV_OK; + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + NvU32 flags = 0; + NvU32 index = 0; + NvU32 hClass; + NvU64 *pageNumberList = NULL; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NV_MEMORY_LIST_ALLOCATION_PARAMS listAllocParams = {0}; + + switch (memdescGetAddressSpace(pMemDesc)) + { + + case ADDR_FBMEM: + hClass = NV01_MEMORY_LIST_FBMEM; + break; + + case ADDR_SYSMEM: + hClass = NV01_MEMORY_LIST_SYSTEM; + break; + + default: + return NV_ERR_NOT_SUPPORTED; + } + + // Initialize parameters with pMemDesc information + listAllocParams.pteAdjust = pMemDesc->PteAdjust; + listAllocParams.format = memdescGetPteKind(pMemDesc); + listAllocParams.size = pMemDesc->Size; + listAllocParams.hClient = NV01_NULL_OBJECT; + listAllocParams.hParent = NV01_NULL_OBJECT; + listAllocParams.hObject = NV01_NULL_OBJECT; + listAllocParams.limit = pMemDesc->Size - 1; + listAllocParams.flagsOs02 = (DRF_DEF(OS02,_FLAGS,_MAPPING,_NO_MAP) | + (flags & DRF_SHIFTMASK(NVOS02_FLAGS_COHERENCY))); + + // Handle pageCount based on pMemDesc contiguity + if (!memdescGetContiguity(pMemDesc, AT_GPU)) + { + listAllocParams.flagsOs02 |= DRF_DEF(OS02,_FLAGS,_PHYSICALITY,_NONCONTIGUOUS); + listAllocParams.pageCount = pMemDesc->PageCount; + } + else + { + listAllocParams.pageCount = 1; + } + + + // Initialize pageNumberList + pageNumberList = portMemAllocNonPaged(sizeof(NvU64) * listAllocParams.pageCount); + for (index = 0; index < listAllocParams.pageCount; index++) + pageNumberList[index] = memdescGetPte(pMemDesc, AT_GPU, index) >> RM_PAGE_SHIFT; + listAllocParams.pageNumberList = pageNumberList; + + // Create MemoryList object + NV_ASSERT_OK_OR_GOTO(status, + pRmApi->Alloc(pRmApi, + pMemoryManager->hClient, + pMemoryManager->hSubdevice, + pHandle, + hClass, + &listAllocParams), + end); + + // Register MemoryList object to GSP + NV_ASSERT_OK_OR_GOTO(status, + memdescRegisterToGSP(pGpu, + pMemoryManager->hClient, + pMemoryManager->hSubdevice, + *pHandle), + end); + +end: + if ((status != NV_OK) && (*pHandle != NV01_NULL_OBJECT)) + pRmApi->Free(pRmApi, pMemoryManager->hClient, *pHandle); + + if (pageNumberList != NULL) + portMemFree(pageNumberList); + + return status; +} diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mapper.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mapper.c new file mode 100644 index 000000000..91b7e131d --- /dev/null +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mapper.c @@ -0,0 +1,48 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gpu/mem_mgr/mem_mapper.h" +#include "gpu/gpu.h" +#include "os/os.h" + +NV_STATUS +memmapperConstruct_IMPL +( + MemoryMapper *pMemoryMapper, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + // if (!GPU_GET_DMA(GPU_RES_GET_GPU(pMemoryMapper))->bMemoryMapperApiEnabled) + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +memmapperCtrlCmdSubmitPagingOperations_IMPL +( + MemoryMapper *pMemoryMapper, + NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS *pParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c index ee1e517fc..2c83f83d3 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c @@ -30,6 +30,7 @@ #include "gpu/mmu/kern_gmmu.h" #include "gpu/bus/kern_bus.h" #include "core/locks.h" +#include "virtualization/kernel_vgpu_mgr.h" #include "vgpu/rpc.h" #include "core/thread_state.h" #include "nvRmReg.h" @@ -91,18 +92,12 @@ memmgrDestruct_IMPL for (i = 0; i < NUM_FBSR_TYPES; i++) { - if (pMemoryManager->pFbsr[i]) - { - objDelete(pMemoryManager->pFbsr[i]); - pMemoryManager->pFbsr[i] = NULL; - } + objDelete(pMemoryManager->pFbsr[i]); + pMemoryManager->pFbsr[i] = NULL; } - if (pMemoryManager->pHeap != NULL) - { - objDelete(pMemoryManager->pHeap); - pMemoryManager->pHeap = NULL; - } + objDelete(pMemoryManager->pHeap); + pMemoryManager->pHeap = NULL; pMemoryManager->MIGMemoryPartitioningInfo.partitionableMemoryRange = NV_RANGE_EMPTY; } @@ -132,7 +127,7 @@ _memmgrInitRegistryOverrides(OBJGPU *pGpu, MemoryManager *pMemoryManager) { pMemoryManager->bScrubOnFreeEnabled = NV_FALSE; } - + if ((osReadRegistryDword(pGpu, NV_REG_STR_RM_DISABLE_FAST_SCRUBBER, &data32) == NV_OK) && data32) { @@ -489,6 +484,32 @@ memmgrStateDestroy_IMPL // RMCONFIG: only if FBSR engine is enabled if (RMCFG_MODULE_FBSR) { + // Cleanup fbsrReservedRanges + if (pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_BEFORE_BAR2PTE] != NULL) + memdescDestroy(pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_BEFORE_BAR2PTE]); + + if (pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_AFTER_BAR2PTE] != NULL) + memdescDestroy(pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_AFTER_BAR2PTE]); + + if (pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_GSP_HEAP] != NULL) + memdescDestroy(pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_GSP_HEAP]); + + if (pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_GSP_NON_WPR] != NULL) + memdescDestroy(pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_GSP_NON_WPR]); + + if (pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_GSP_WPR] != NULL) + memdescDestroy(pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_GSP_WPR]); + + if (pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_VGA_WORKSPACE] != NULL) + memdescDestroy(pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_VGA_WORKSPACE]); + + pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_BEFORE_BAR2PTE] = NULL; + pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_AFTER_BAR2PTE] = NULL; + pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_GSP_HEAP] = NULL; + pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_GSP_NON_WPR] = NULL; + pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_GSP_WPR] = NULL; + pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_VGA_WORKSPACE] = NULL; + for (i = 0; i < NUM_FBSR_TYPES; i++) { fbsrDestroy_HAL(pGpu, pMemoryManager->pFbsr[i]); @@ -580,7 +601,7 @@ memmgrCreateHeap_IMPL pMemoryManager->pHeap = newHeap; - if (memmgrIsPmaEnabled(pMemoryManager) && + if (memmgrIsPmaEnabled(pMemoryManager) && memmgrIsPmaSupportedOnPlatform(pMemoryManager)) { portMemSet(&pMemoryManager->pHeap->pmaObject, 0, sizeof(pMemoryManager->pHeap->pmaObject)); @@ -1308,13 +1329,13 @@ memmgrAllocateConsoleRegion_IMPL NV_STATUS status = NV_OK; NvU32 consoleRegionId = 0x0; - NvU64 regionSize; - + NvU64 regionSize; + if (pMemoryManager->Ram.ReservedConsoleDispMemSize > 0) { - pConsoleFbRegion->base = pMemoryManager->Ram.fbRegion[consoleRegionId].base; + pConsoleFbRegion->base = pMemoryManager->Ram.fbRegion[consoleRegionId].base; pConsoleFbRegion->limit = pMemoryManager->Ram.fbRegion[consoleRegionId].limit; - + regionSize = pConsoleFbRegion->limit - pConsoleFbRegion->base + 1; // Once the console is reserved, we don't expect to reserve it again @@ -1975,7 +1996,16 @@ memmgrGetKindComprForGpu_KERNEL } else { - memmgrFillComprInfoUncompressed(pMemoryManager, kind, pComprInfo); + if (ctagId == FB_HWRESID_CTAGID_VAL_FERMI(0xcdcdcdcd)) + { + portMemSet(pComprInfo, 0, sizeof(*pComprInfo)); + + pComprInfo->kind = memmgrGetUncompressedKind_HAL(pMappingGpu, pMemoryManager, kind, NV_TRUE); + } + else + { + memmgrFillComprInfoUncompressed(pMemoryManager, kind, pComprInfo); + } } *pKind = pComprInfo->kind; @@ -2472,7 +2502,7 @@ memmgrPmaInitialize_IMPL NV_STATUS status = NV_OK; NvBool bNumaEnabled = osNumaOnliningEnabled(pGpu->pOsGpuInfo); - NV_ASSERT(memmgrIsPmaEnabled(pMemoryManager) && + NV_ASSERT(memmgrIsPmaEnabled(pMemoryManager) && memmgrIsPmaSupportedOnPlatform(pMemoryManager)); if (memmgrIsPmaForcePersistence(pMemoryManager)) @@ -2517,12 +2547,12 @@ memmgrPmaInitialize_IMPL { if (numaSkipReclaimVal > NV_REG_STR_RM_NUMA_ALLOC_SKIP_RECLAIM_PERCENTAGE_MAX) { - numaSkipReclaimVal = NV_REG_STR_RM_NUMA_ALLOC_SKIP_RECLAIM_PERCENTAGE_MAX; + numaSkipReclaimVal = NV_REG_STR_RM_NUMA_ALLOC_SKIP_RECLAIM_PERCENTAGE_MAX; } } pmaNumaSetReclaimSkipThreshold(pPma, numaSkipReclaimVal); } - + return NV_OK; } @@ -3012,7 +3042,7 @@ memmgrReserveMemoryForFsp_IMPL // // If we sent FSP commands to boot ACR, we need to allocate the surfaces // used by FSP and ACR as WPR/FRTS here from the reserved heap - // + // if (pKernelFsp && (!pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_DISABLE_FRTS_VIDMEM) && (pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_BOOT_COMMAND_OK)))) { @@ -3026,3 +3056,25 @@ memmgrReserveMemoryForFsp_IMPL } return NV_OK; } + +NvU64 +memmgrGetVgpuHostRmReservedFb_KERNEL +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager, + NvU32 vgpuTypeId +) +{ + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS params = {0}; + + params.vgpuTypeId = vgpuTypeId; + // Send to GSP to get amount of FB reserved for the host + NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB, + ¶ms, + sizeof(params))); + return params.hostReservedFb; +} \ No newline at end of file diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_ctrl.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_ctrl.c index 1fb67cefc..4c0260b28 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_ctrl.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_ctrl.c @@ -203,7 +203,7 @@ deviceCtrlCmdFbGetCaps_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); NvU8 *pFbCaps = NvP64_VALUE(pFbCapsParams->capsTbl); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); // sanity check array size if (pFbCapsParams->capsTblSize != NV0080_CTRL_FB_CAPS_TBL_SIZE) @@ -234,7 +234,7 @@ deviceCtrlCmdFbGetCapsV2_IMPL NvU8 *pFbCaps = pFbCapsParams->capsTbl; NV_STATUS rmStatus; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); // now accumulate caps for entire device rmStatus = memmgrGetFbCaps(pGpu, pFbCaps); @@ -262,7 +262,7 @@ subdeviceCtrlCmdFbGetBar1Offset_IMPL RsCpuMapping *pCpuMapping = NULL; NV_STATUS status; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); // Get the device handle status = deviceGetByInstance(RES_GET_CLIENT(pSubdevice), @@ -299,7 +299,7 @@ subdeviceCtrlCmdFbIsKind_IMPL NV_STATUS status = NV_OK; NvBool rmResult; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); // perform appropriate RM operation based on the supported sdk operations switch (pIsKindParams->operation) @@ -644,7 +644,7 @@ subdeviceCtrlCmdFbGetFBRegionInfo_IMPL ct_assert(NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES >= NVOS32_NUM_MEM_TYPES); ct_assert(NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES >= MAX_FB_REGIONS); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); memmgrCalcReservedFbSpace(pGpu, pMemoryManager); @@ -726,6 +726,21 @@ subdeviceCtrlCmdFbGetFBRegionInfo_IMPL return status; } +NV_STATUS +subdeviceCtrlCmdInternalMemmgrGetVgpuHostRmReservedFb_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + pParams->hostReservedFb = memmgrGetVgpuHostRmReservedFb_HAL(pGpu, pMemoryManager, pParams->vgpuTypeId); + + return NV_OK; +} + /*! * @brief This command gets the offset into FB that ECC asynchronous scrubber * has completed up to. As well as if the scrubber has finished its job. diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_pwr_mgmt.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_pwr_mgmt.c new file mode 100644 index 000000000..3198a7775 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_pwr_mgmt.c @@ -0,0 +1,692 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gpu/mem_mgr/mem_mgr.h" +#include "gpu/mem_mgr/heap.h" +#include "gpu/mem_mgr/fbsr.h" +#include "gpu/bus/kern_bus.h" +#include "vgpu/rpc.h" +#include "os/nv_memory_type.h" +#include "gpu/gsp/kernel_gsp.h" + +static NV_STATUS _memmgrWalkHeap(OBJGPU *pGpu, MemoryManager *pMemoryManager, OBJFBSR *pFbsr); +static NV_STATUS _memmgrAllocFbsrReservedRanges(OBJGPU *pGpu, MemoryManager *pMemoryManager); + +/*! + * Save video memory + */ +NV_STATUS +memmgrSavePowerMgmtState_KERNEL +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager +) +{ + NvU32 fbsrStartMode = pMemoryManager->fbsrStartMode; + NvBool bGcOffState = NV_FALSE; + NvU32 i; + OBJFBSR *pFbsr; + NV_STATUS rmStatus = NV_OK; + + if (pMemoryManager->pActiveFbsr) + { + NV_PRINTF(LEVEL_ERROR, "!!!!! Calling Suspend on a suspended GPU or "); + NV_PRINTF(LEVEL_ERROR, + "the previous Resume call might have failed !!!!!!\n"); + NV_PRINTF(LEVEL_ERROR, "!!!!! Trying a suspend anyway !!!!!!\n"); + } + + // + // N.B. there are multiple mechanisms available for this operation. We start + // with the highest performance approach -- DMA -- and if this fails we fallback + // to the slower but less intensive CPU approach. A reason why the DMA approach + // might fail is not enough non-paged memory available. + // + pMemoryManager->pActiveFbsr = NULL; + // + // Iterate the heap at top level to avoid inconsistent between + // several pFbsr instance. + // + + rmStatus = memmgrAddMemNodes(pGpu, pMemoryManager, bGcOffState); + + if ((rmStatus == NV_OK) && + memmgrIsPmaInitialized(pMemoryManager)) + { + Heap *pHeap = GPU_GET_HEAP(pGpu); + RANGELISTTYPE *pSaveList = NULL; + RANGELISTTYPE *pSaveCurr; + + if (bGcOffState) + { + rmStatus = pmaBuildAllocatedBlocksList(&pHeap->pmaObject, &pSaveList); + } + else + { + rmStatus = pmaBuildPersistentList(&pHeap->pmaObject, &pSaveList); + } + + if (rmStatus == NV_OK) + { + pSaveCurr = pSaveList; + while (pSaveCurr) + { + MEMORY_DESCRIPTOR *pMemDescPma; + + // Create memdescs & describe the block + rmStatus = memdescCreate(&pMemDescPma, pGpu, RM_PAGE_SIZE, PMA_GRANULARITY, NV_TRUE, ADDR_FBMEM, NV_MEMORY_UNCACHED, MEMDESC_FLAGS_NONE); + if (rmStatus != NV_OK) + { + break; + } + memdescDescribe(pMemDescPma, ADDR_FBMEM, pSaveCurr->base, pSaveCurr->limit - pSaveCurr->base + 1); + + // Memory descriptor will be freed during restore + rmStatus = memmgrAddMemNode(pGpu, pMemoryManager, pMemDescPma, NV_TRUE); + if (rmStatus != NV_OK) + { + break; + } + + pSaveCurr = pSaveCurr->pNext; + } + } + + if (bGcOffState) + { + pmaFreeAllocatedBlocksList(&pHeap->pmaObject, &pSaveList); + } + else + { + pmaFreePersistentList(&pHeap->pmaObject, &pSaveList); + } + } + + if (rmStatus != NV_OK) + { + memmgrRemoveMemNodes(pGpu, pMemoryManager); + return rmStatus; + } + + for (i = fbsrStartMode; i < NUM_FBSR_TYPES; i++) + { + if ((pMemoryManager->fixedFbsrModesMask != 0) && + !(NVBIT(i) & pMemoryManager->fixedFbsrModesMask)) + { + continue; + } + + pFbsr = pMemoryManager->pFbsr[i]; + + if (!pFbsr) + { + continue; + } + + if (!pFbsr->bInitialized) + { + continue; + } + + // + // Determine size of buffer needed + // + if (fbsrBegin_HAL(pGpu, pFbsr, FBSR_OP_SIZE_BUF) != NV_OK) + { + continue; + } + + if (_memmgrWalkHeap(pGpu, pMemoryManager, pFbsr) != NV_OK) + { + continue; + } + + if (fbsrEnd_HAL(pGpu, pFbsr) != NV_OK) + { + continue; + } + + // + // Perform the copy + // + if (fbsrBegin_HAL(pGpu, pFbsr, FBSR_OP_SAVE) != NV_OK) + { + continue; + } + + if (_memmgrWalkHeap(pGpu, pMemoryManager, pFbsr) != NV_OK) + { + continue; + } + + if (fbsrEnd_HAL(pGpu, pFbsr) != NV_OK) + { + continue; + } + + pFbsr->bValid = NV_TRUE; + pMemoryManager->pActiveFbsr = pFbsr; // Restore will restore from active fbsr. + break; + } + + if (rmStatus != NV_OK) + { + memmgrFreeFbsrMemory_HAL(pGpu, pMemoryManager); + } + + return rmStatus; +} + +/*! + * Restore video memory + */ +static volatile NvS32 concurrentfbRestorePowerMgmtStateAccess[NV_MAX_DEVICES] = { 0 }; +NV_STATUS +memmgrRestorePowerMgmtState_KERNEL +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager +) +{ + OBJFBSR *pFbsr = pMemoryManager->pActiveFbsr; + NV_STATUS status = NV_OK; + NvBool bIsGpuLost = NV_FALSE; + + if (portAtomicIncrementS32(&concurrentfbRestorePowerMgmtStateAccess[pGpu->gpuInstance]) != 1) + { + NV_PRINTF(LEVEL_INFO, "Concurrent access"); + return NV_OK; + } + + if (!pFbsr || !pFbsr->bValid) + { + NV_PRINTF(LEVEL_ERROR, "!!!!! Calling Resume on an active GPU or " + "the previous Suspend call might have failed !!!!!!\n"); + NV_PRINTF(LEVEL_ERROR, + "!!!!! So ignoring the resume request !!!!!!\n"); + return NV_ERR_INVALID_STATE; + } + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_LOST)) + { + bIsGpuLost = NV_TRUE; + } + + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + fbsrBegin_HAL(pGpu, pFbsr, bIsGpuLost ? FBSR_OP_DESTROY : FBSR_OP_RESTORE), + done); + if (!bIsGpuLost) + { + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + _memmgrWalkHeap(pGpu, pMemoryManager, pFbsr), done); + } + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, fbsrEnd_HAL(pGpu, pFbsr), done); + +done: + + // Cleanup + memmgrFreeFbsrMemory_HAL(pGpu, pMemoryManager); + pFbsr->bValid = NV_FALSE; + + portAtomicDecrementS32(&concurrentfbRestorePowerMgmtStateAccess[pGpu->gpuInstance]); + + return status; +} + +/* + * FB regions with LostOnSuspend set to NV_TRUE are expected to be grouped together towards the end of FB + * First region to have this property set would be the end of save area for Suspend. + * TODO: Handle LostOnSuspend for non-consequetive regions + */ +static NvU64 +_memmgrGetFbEndExcludingLostOnSuspendRegions +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager +) +{ + NvU32 i = 0; + + for (i = 0; i < pMemoryManager->Ram.numFBRegions; i++) + { + if (pMemoryManager->Ram.fbRegion[i].bLostOnSuspend == NV_TRUE) + { + return pMemoryManager->Ram.fbRegion[i].base; + } + } + + return (pMemoryManager->Ram.fbAddrSpaceSizeMb << 20); +} + +static NV_STATUS +_memmgrAllocFbsrReservedRanges +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager +) +{ + NvU64 size = 0; + NV_STATUS status = NV_OK; + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + + // Alloc the Memory descriptors for Fbsr Reserved regions, if not allocated. + if (pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_BEFORE_BAR2PTE] == NULL) + { + // Allocate Vid Mem descriptor for RM INSTANCE memory from start to BAR2PTE + size = memdescGetPhysAddr(pKernelBus->virtualBar2[GPU_GFID_PF].pPTEMemDesc, AT_GPU, 0) - pMemoryManager->rsvdMemoryBase; + NV_ASSERT_OK_OR_GOTO(status, + memdescCreate(&pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_BEFORE_BAR2PTE], + pGpu, size, 0, NV_TRUE, ADDR_FBMEM, + NV_MEMORY_UNCACHED, MEMDESC_FLAGS_NONE), + fail); + // Describe the MemDescriptor for RM Instance Memory from start to BAR2PTE + memdescDescribe(pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_BEFORE_BAR2PTE], + ADDR_FBMEM, pMemoryManager->rsvdMemoryBase, size); + } + + if (pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_AFTER_BAR2PTE] == NULL) + { + // Allocate Mem descriptors for AFTER_BAR2PTE, GSP HEAP, WPR, NON WPR and VGA Workspace regions + if (IS_GSP_CLIENT(pGpu)) + { + KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); + RmPhysAddr afterBar2PteRegionStart = memdescGetPhysAddr(pKernelBus->virtualBar2[GPU_GFID_PF].pPTEMemDesc, AT_GPU, 0) + + pKernelBus->virtualBar2[GPU_GFID_PF].pPTEMemDesc->Size; + NvU64 afterBar2PteRegionEnd = pMemoryManager->rsvdMemoryBase + pMemoryManager->rsvdMemorySize; + NvU64 afterBar2PteRegionSize = afterBar2PteRegionEnd - afterBar2PteRegionStart; + NvU64 gspHeapRegionStart = afterBar2PteRegionEnd; + NvU64 gspHeapRegionSize = pKernelGsp->pWprMeta->gspFwRsvdStart - gspHeapRegionStart; + NvU64 gspNonWprRegionSize = pKernelGsp->pWprMeta->gspFwWprStart - pKernelGsp->pWprMeta->gspFwRsvdStart; + + // Create memdesc of AFTER BAR2PTE, GSP HEAP, GSP NON WPR and VGA Workspace regions + NV_ASSERT_OK_OR_GOTO(status, + memdescCreate(&pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_AFTER_BAR2PTE], + pGpu, afterBar2PteRegionSize, 0, NV_TRUE, + ADDR_FBMEM, NV_MEMORY_UNCACHED, MEMDESC_FLAGS_NONE), + fail); + NV_ASSERT_OK_OR_GOTO(status, + memdescCreate(&pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_GSP_HEAP], + pGpu, gspHeapRegionSize, 0, NV_TRUE, + ADDR_FBMEM, NV_MEMORY_UNCACHED, MEMDESC_FLAGS_NONE), + fail); + NV_ASSERT_OK_OR_GOTO(status, + memdescCreate(&pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_GSP_NON_WPR], + pGpu, gspNonWprRegionSize, 0, NV_TRUE, + ADDR_FBMEM, NV_MEMORY_UNCACHED, MEMDESC_FLAGS_NONE), + fail); + NV_ASSERT_OK_OR_GOTO(status, + memdescCreate(&pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_VGA_WORKSPACE], + pGpu, pKernelGsp->pWprMeta->vgaWorkspaceSize, 0, NV_TRUE, + ADDR_FBMEM, NV_MEMORY_UNCACHED, MEMDESC_FLAGS_NONE), + fail); + + // Describe memdesc of AFTER BAR2PTE, GSP HEAP, GSP NON WPR and VGA Workspace regions + memdescDescribe(pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_AFTER_BAR2PTE], + ADDR_FBMEM, + afterBar2PteRegionStart, + afterBar2PteRegionSize); + memdescDescribe(pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_GSP_HEAP], + ADDR_FBMEM, + gspHeapRegionStart, + gspHeapRegionSize); + memdescDescribe(pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_GSP_NON_WPR], + ADDR_FBMEM, + pKernelGsp->pWprMeta->gspFwRsvdStart, + gspNonWprRegionSize); + memdescDescribe(pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_VGA_WORKSPACE], + ADDR_FBMEM, + pKernelGsp->pWprMeta->vgaWorkspaceOffset, + pKernelGsp->pWprMeta->vgaWorkspaceSize); + + } + // Allocate Vid Mem descriptor for RM INSTANCE memory, specific to VGA i.e. after BAR2PTE to end. + else + { + NvU64 fbAddrSpaceSize = _memmgrGetFbEndExcludingLostOnSuspendRegions(pGpu, pMemoryManager); + size = (fbAddrSpaceSize) - memdescGetPhysAddr(pKernelBus->virtualBar2[GPU_GFID_PF].pPTEMemDesc, AT_GPU, 0) - pKernelBus->virtualBar2[GPU_GFID_PF].pPTEMemDesc->Size; + + NV_ASSERT_OK_OR_GOTO(status, + memdescCreate(&pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_AFTER_BAR2PTE], + pGpu, size, 0, NV_TRUE, ADDR_FBMEM, + NV_MEMORY_UNCACHED, MEMDESC_FLAGS_NONE), + fail); + memdescDescribe(pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_AFTER_BAR2PTE], + ADDR_FBMEM, + memdescGetPhysAddr(pKernelBus->virtualBar2[GPU_GFID_PF].pPTEMemDesc, AT_GPU, 0) + pKernelBus->virtualBar2[GPU_GFID_PF].pPTEMemDesc->Size, size); + + } + } + return status; + +fail: + NV_PRINTF(LEVEL_ERROR, "Failure during allocation of FBSR Reserved ranges: %d\n", status); + + // Cleanup fbsrReservedRanges + if (pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_BEFORE_BAR2PTE] != NULL) + memdescDestroy(pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_BEFORE_BAR2PTE]); + + if (pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_AFTER_BAR2PTE] != NULL) + memdescDestroy(pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_AFTER_BAR2PTE]); + + if (pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_GSP_HEAP] != NULL) + memdescDestroy(pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_GSP_HEAP]); + + if (pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_GSP_NON_WPR] != NULL) + memdescDestroy(pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_GSP_NON_WPR]); + + if (pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_GSP_WPR] != NULL) + memdescDestroy(pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_GSP_WPR]); + + if (pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_VGA_WORKSPACE] != NULL) + memdescDestroy(pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_VGA_WORKSPACE]); + + pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_BEFORE_BAR2PTE] = NULL; + pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_AFTER_BAR2PTE] = NULL; + pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_GSP_HEAP] = NULL; + pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_GSP_NON_WPR] = NULL; + pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_GSP_WPR] = NULL; + pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_VGA_WORKSPACE] = NULL; + + return status; +} + +/*! + * Accessor for list of video memory regions that need to be preserved. This + * routine calls POBJFBSR::fbsrCopyMemory[|MemDesc] per-region. + * + * @param[in] pFbsr OBJFBSR pointer + * + * @returns None + */ +static NV_STATUS +_memmgrWalkHeap(OBJGPU *pGpu, MemoryManager *pMemoryManager, OBJFBSR *pFbsr) +{ + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + FB_MEM_NODE *pMemNode = pMemoryManager->pMemHeadNode; + NvU64 size = 0; + NV_STATUS status = NV_OK; + + // + // Walk the heap and preserve any allocations marked as non-volatile. N.B. if + // walking this list turns out to be expensive the heap could be changed to keep + // a separate list for preserved allocations. + // + while (pMemNode) + { + fbsrCopyMemoryMemDesc_HAL(pGpu, pFbsr, pMemNode->pMemDesc); + pMemNode = pMemNode->pNext; + } + + // Save reserved memory region + if (memdescGetAddressSpace(pKernelBus->virtualBar2[GPU_GFID_PF].pPTEMemDesc) == ADDR_FBMEM) + { + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + _memmgrAllocFbsrReservedRanges(pGpu, pMemoryManager), done); + + fbsrCopyMemoryMemDesc_HAL(pGpu, pFbsr, + pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_BEFORE_BAR2PTE]); + fbsrCopyMemoryMemDesc_HAL(pGpu, pFbsr, + pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_AFTER_BAR2PTE]); + + if (IS_GSP_CLIENT(pGpu)) + { + // + // FBSR_OP_SIZE_BUF increments pFbsr->numRegions and updates pFbsr->Length to add sysmem for allocations + // FBSR_OP_SAVE sends memdesc info to GSP for CE save + // + // Handle both FBSR_OP_SIZE_BUF and FBSR_OP_SAVE for GSP NON WPR regions + // to allocate sysmem for the regions and to use CE to save/restore the region + // + fbsrCopyMemoryMemDesc_HAL(pGpu, pFbsr, + pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_GSP_NON_WPR]); + + // + // Handle only FBSR_OP_SIZE_BUF for GSP HEAP, GSP WPR and VGA workspace regions + // to allocate sysmem for these regions + // Use Bus copy to save/restore the GSP WPR region if allocated + // + if (pFbsr->op == FBSR_OP_SIZE_BUF) + { + // SysOffset for GSP memory allocations is the AFTER BAR2PTE region's sysoffset + pFbsr->gspFbAllocsSysOffset = pFbsr->length; + + fbsrCopyMemoryMemDesc_HAL(pGpu, pFbsr, + pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_GSP_HEAP]); + fbsrCopyMemoryMemDesc_HAL(pGpu, pFbsr, + pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_VGA_WORKSPACE]); + pFbsr->numRegions -= 2; + + // GSP WPR memdesc is not NULL when using unauthenticated GSP boot and bus copy + if (pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_GSP_WPR] != NULL) + { + fbsrCopyMemoryMemDesc_HAL(pGpu, pFbsr, + pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_GSP_WPR]); + pFbsr->numRegions--; + } + } + + } + } + else + { + // Alloc the Memory descriptors for Fbsr Reserved regions, if not allocated. + if (pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_BEFORE_BAR2PTE] == NULL) + { + // Allocate Vid Mem descriptor for RM INSTANCE memory from start to BAR2PTE + size = pMemoryManager->rsvdMemorySize; + NV_ASSERT_OK_OR_GOTO(status, + memdescCreate(&pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_BEFORE_BAR2PTE], + pGpu, size, 0, NV_TRUE, ADDR_FBMEM, NV_MEMORY_UNCACHED, MEMDESC_FLAGS_NONE), + done); + + // Describe the MemDescriptor for RM Instance Memory from start to BAR2PTE + memdescDescribe(pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_BEFORE_BAR2PTE], + ADDR_FBMEM, pMemoryManager->rsvdMemoryBase, size); + } + + // Save all reserved memory + fbsrCopyMemoryMemDesc_HAL(pGpu, pFbsr, + pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_BEFORE_BAR2PTE]); + } +done: + return status; +} + +/*! + * @brief Construct memory descriptor list + * + * @param[in] pGpu GPU object pointer + * @param[in] bFreeDescriptor NV_TRUE to free descriptor when done + * + * @returns NV_OK on success. + * Error otherwise. + */ +NV_STATUS +memmgrAddMemNode +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager, + MEMORY_DESCRIPTOR *pMemDesc, + NvBool bFreeDescriptor +) +{ + FB_MEM_NODE *pNode = NULL; + NV_STATUS rmStatus = NV_OK; + + pNode = portMemAllocNonPaged(sizeof(FB_MEM_NODE)); + if (pNode == NULL) + { + rmStatus = NV_ERR_NO_MEMORY; + NV_PRINTF(LEVEL_WARNING, "can't allocate FB_MEM_NODE, err:0x%x!\n", rmStatus); + NV_ASSERT_OK_OR_RETURN(rmStatus); + } + + pNode->pNext = NULL; + pNode->pMemDesc = pMemDesc; + pNode->bFreeDescriptor = bFreeDescriptor; + // + // Hold this memory descriptor till we fully restore all GPUs. + // This is needed for a few RM allocations to prevent them from + // being freed after adding them to this list + // Note: Allocated flag is set only for RM internal allocations. + // + if (pMemDesc->Allocated) + { + memdescAddRef(pMemDesc); + pMemDesc->Allocated++; + } + + if (pMemoryManager->pMemHeadNode == NULL) + { + pMemoryManager->pMemHeadNode = pNode; + pMemoryManager->pMemTailNode = pNode; + } + else + { + pMemoryManager->pMemTailNode->pNext = pNode; + pMemoryManager->pMemTailNode = pNode; + } + + return rmStatus; +} + +NV_STATUS +memmgrAddMemNodes_IMPL(OBJGPU *pGpu, MemoryManager *pMemoryManager, NvBool bSaveAllRmAllocations) +{ + NV_STATUS status = NV_OK; + Heap *pHeap = GPU_GET_HEAP(pGpu); + MEMORY_DESCRIPTOR *pAllocMemDesc; + MEM_BLOCK *block; + + block = pHeap->pBlockList; + do + { + pAllocMemDesc = block->pMemDesc; + + // + // TODO: Bug 1778161: Let memory descriptor lost on suspend be default, + // use MEMDESC_FLAGS_PRESERVE_CONTENT_ON_SUSPEND explicitly to preserve + // content of memory descriptor, remove MEMDESC_FLAGS_LOST_ON_SUSPEND + // flag. + // + if ((pAllocMemDesc != NULL) && + (((block->owner == HEAP_OWNER_RM_RESERVED_REGION) && + (bSaveAllRmAllocations || + memdescGetFlag(pAllocMemDesc, MEMDESC_FLAGS_PRESERVE_CONTENT_ON_SUSPEND))) || + (((block->owner == HEAP_OWNER_RM_CHANNEL_CTX_BUFFER) || + (block->owner == HEAP_OWNER_RM_KERNEL_CLIENT)) && + (bSaveAllRmAllocations || + (!memdescGetFlag(pAllocMemDesc, MEMDESC_FLAGS_LOST_ON_SUSPEND)))))) + { + if ((memdescGetAddressSpace(pAllocMemDesc) == ADDR_FBMEM) || + (memdescGetAddressSpace(pAllocMemDesc) == ADDR_SYSMEM)) + { + NV_CHECK_OK_OR_GOTO(status, + LEVEL_ERROR, + memmgrAddMemNode(pGpu, pMemoryManager, pAllocMemDesc, NV_FALSE), + done); + } + } + + block = block->next; + } while (block != pHeap->pBlockList); + +done: + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failure during memmgrAddMemNodes: %d\n", status); + memmgrRemoveMemNodes(pGpu, pMemoryManager); + } + + return status; +} + +void memmgrRemoveMemNodes_IMPL +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager +) +{ + FB_MEM_NODE *pMemNode = pMemoryManager->pMemHeadNode; + FB_MEM_NODE *pMemNodeTmp = NULL; + + while (pMemNode) + { + pMemNodeTmp = pMemNode; + pMemNode = pMemNode->pNext; + // + // We hold a refcount on saved RM allocations during suspend + // to prevent them from being freed till resume completes + // Free such allocations now to avoid leaks + // + if (pMemNodeTmp->pMemDesc->Allocated) + { + memdescFree(pMemNodeTmp->pMemDesc); + memdescDestroy(pMemNodeTmp->pMemDesc); + } + else if (pMemNodeTmp->bFreeDescriptor) + { + // Temporary descriptor -- free it + memdescDestroy(pMemNodeTmp->pMemDesc); + } + portMemFree(pMemNodeTmp); + } + + pMemoryManager->pMemHeadNode = NULL; + pMemoryManager->pMemTailNode = NULL; + + return; +} + +void +memmgrFreeFbsrMemory_KERNEL +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager +) +{ + OBJFBSR *pFbsr = pMemoryManager->pActiveFbsr; + + // Cleanup memory list + memmgrRemoveMemNodes(pGpu, pMemoryManager); + + // Free sysmem allocated for S/R + if ((pFbsr != NULL) && (pFbsr->pSysMemDesc != NULL)) + { + // + // Free memory only for FBSR_TYPE_DMA and FBSR_TYPE_PAGED_DMA + // Other types like FBSR_TYPE_CPU rely on fixed sysmem allocation + // done during fbsrInit and require its sysmem to be freed + // only during fbsrDestroy + // + if ((pFbsr->type == FBSR_TYPE_PAGED_DMA) || + (pFbsr->type == FBSR_TYPE_DMA)) + { + memdescFree(pFbsr->pSysMemDesc); + memdescDestroy(pFbsr->pSysMemDesc); + pFbsr->pSysMemDesc = NULL; + } + } + + pMemoryManager->pActiveFbsr = NULL; +} diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_scrub.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_scrub.c index 3cd8674a4..2b00a4dbb 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_scrub.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_scrub.c @@ -512,6 +512,7 @@ scrubSubmitPages NvU64 freeEntriesInList = 0; NvU64 scrubCount = 0; NvU64 numPagesToScrub = pageCount; + NV_STATUS status = NV_OK; portSyncMutexAcquire(pScrubber->pScrubberMutex); *pSize = 0; @@ -519,58 +520,64 @@ scrubSubmitPages NV_PRINTF(LEVEL_INFO, "submitting pages, pageCount:%llx\n", pageCount); - freeEntriesInList = _scrubGetFreeEntries(pScrubber); - if (freeEntriesInList < pageCount) - { - pScrubList = (PSCRUB_NODE) - portMemAllocNonPaged((NvLength)(sizeof(SCRUB_NODE) * (pageCount - freeEntriesInList))); + freeEntriesInList = _scrubGetFreeEntries(pScrubber); + if (freeEntriesInList < pageCount) + { + pScrubList = (PSCRUB_NODE) + portMemAllocNonPaged((NvLength)(sizeof(SCRUB_NODE) * (pageCount - freeEntriesInList))); + + while (freeEntriesInList < pageCount) + { + if (pageCount > MAX_SCRUB_ITEMS) + { + pagesToScrubCheck = (NvLength)(MAX_SCRUB_ITEMS - freeEntriesInList); + scrubCount = MAX_SCRUB_ITEMS; + } + else + { + pagesToScrubCheck = (NvLength)(pageCount - freeEntriesInList); + scrubCount = pageCount; + } - while (freeEntriesInList < pageCount) - { - if (pageCount > MAX_SCRUB_ITEMS) - { - pagesToScrubCheck = (NvLength)(MAX_SCRUB_ITEMS - freeEntriesInList); - scrubCount = MAX_SCRUB_ITEMS; - } - else - { - pagesToScrubCheck = (NvLength)(pageCount - freeEntriesInList); - scrubCount = pageCount; - } + numFinished = _scrubCheckAndSubmit(pScrubber, chunkSize, &pPages[totalSubmitted], + scrubCount, &pScrubList[curPagesSaved], + pagesToScrubCheck); - numFinished = _scrubCheckAndSubmit(pScrubber, chunkSize, &pPages[totalSubmitted], - scrubCount, &pScrubList[curPagesSaved], - pagesToScrubCheck); + pageCount -= numFinished; + curPagesSaved += pagesToScrubCheck; + totalSubmitted += numFinished; + freeEntriesInList = _scrubGetFreeEntries(pScrubber); + } - pageCount -= numFinished; - curPagesSaved += pagesToScrubCheck; - totalSubmitted += numFinished; - freeEntriesInList = _scrubGetFreeEntries(pScrubber); - } + *ppList = pScrubList; + *pSize = curPagesSaved; + } + else + { + totalSubmitted = _scrubCheckAndSubmit(pScrubber, chunkSize, pPages, + pageCount, NULL, + 0); + *ppList = NULL; + *pSize = 0; + } - *ppList = pScrubList; - *pSize = curPagesSaved; - } - else - { + portSyncMutexRelease(pScrubber->pScrubberMutex); - totalSubmitted = _scrubCheckAndSubmit(pScrubber, chunkSize, pPages, - pageCount, NULL, - 0); - *ppList = NULL; - *pSize = 0; - } + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, status); - portSyncMutexRelease(pScrubber->pScrubberMutex); - if (totalSubmitted == numPagesToScrub) - return NV_OK; - else - { + if (totalSubmitted == numPagesToScrub) + { + status = NV_OK; + } + else + { NV_PRINTF(LEVEL_FATAL, "totalSubmitted :%llx != pageCount: %llx\n", totalSubmitted, pageCount); DBG_BREAKPOINT(); - return NV_ERR_GENERIC; - } + status = NV_ERR_GENERIC; + } + + return status; } /** diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_utils.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_utils.c index 750712300..8caa66380 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_utils.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_utils.c @@ -30,6 +30,9 @@ #include "gpu/bus/kern_bus.h" +// Memory copy block size for if we need to cut up a mapping +#define MEMORY_COPY_BLOCK_SIZE 1024 * 1024 + /* ------------------------ Private functions --------------------------------------- */ /*! @@ -158,6 +161,89 @@ memmgrMemSetWithTransferType return NV_OK; } +/*! + * @brief This function is used to map the appropriate memory descriptor, + * copy the memory from the given buffer, and then unmap. + * + * @param[in] pMemDesc Memory descriptor of buffer to write + * @param[in] pBuf Buffer allocated by caller + * @param[in] offset Offset of buffer to write + * @param[in] size Size in bytes of the buffer + * @param[in] flags Flags + */ +static NV_STATUS +memmgrMemWriteMapAndCopy +( + MemoryManager *pMemoryManager, + MEMORY_DESCRIPTOR *pMemDesc, + void *pBuf, + NvU64 offset, + NvU64 size, + NvU32 flags +) +{ + NvU8 *pDst = NULL; + OBJGPU *pGpu = ENG_GET_GPU(pMemoryManager); + + pDst = memdescMapInternal(pGpu, pMemDesc, TRANSFER_FLAGS_NONE); + NV_CHECK_OR_RETURN(LEVEL_SILENT, pDst != NULL, NV_ERR_INSUFFICIENT_RESOURCES); + + portMemCopy(pDst + offset, size, pBuf, size); + memdescUnmapInternal(pGpu, pMemDesc, flags); + + return NV_OK; +} + +/*! + * @brief This function is used for writing data placed in a caller passed buffer + * to a given memory region while only mapping regions as large as the given + * block size. + * + * @param[in] pMemDesc Memory descriptor of buffer to write + * @param[in] pBuf Buffer allocated by caller + * @param[in] baseOffset Offset of entire buffer to write + * @param[in] size Size in bytes of the buffer + * @param[in] flags Flags + * @param[in] blockSize Maximum size of a mapping to use + */ +static NV_STATUS +memmgrMemWriteInBlocks +( + MemoryManager *pMemoryManager, + MEMORY_DESCRIPTOR *pMemDesc, + void *pBuf, + NvU64 baseOffset, + NvU64 size, + NvU32 flags, + NvU32 blockSize +) +{ + NV_STATUS status = NV_OK; + OBJGPU *pGpu = ENG_GET_GPU(pMemoryManager); + NvU64 remaining = size; + NvU64 offset = 0; + + while ((remaining > 0) && (status == NV_OK)) + { + MEMORY_DESCRIPTOR *pSubMemDesc = NULL; + NvU32 mapSize = NV_MIN(blockSize, remaining); + + NV_CHECK_OK_OR_RETURN(LEVEL_SILENT, memdescCreateSubMem(&pSubMemDesc, pMemDesc, pGpu, offset + baseOffset, mapSize)); + + // Set the offset to 0, as the sub descriptor already starts at the offset + status = memmgrMemWriteMapAndCopy(pMemoryManager, pSubMemDesc, (NvU8 *)pBuf + offset, + 0, mapSize, flags); + + memdescFree(pSubMemDesc); + memdescDestroy(pSubMemDesc); + + offset += mapSize; + remaining -= mapSize; + } + + return status; +} + /*! * @brief This function is used for writing data placed in a caller passed buffer * to a given memory region using the specified memory transfer technique @@ -179,9 +265,7 @@ memmgrMemWriteWithTransferType NvU32 flags ) { - OBJGPU *pGpu = ENG_GET_GPU(pMemoryManager); - NvU8 *pDst; - NvU8 *pMapping = memdescGetKernelMapping(pDstInfo->pMemDesc); + NvU8 *pMapping = memdescGetKernelMapping(pDstInfo->pMemDesc); // Sanitize the input NV_ASSERT_OR_RETURN(pDstInfo != NULL, NV_ERR_INVALID_ARGUMENT); @@ -199,12 +283,12 @@ memmgrMemWriteWithTransferType switch (transferType) { case TRANSFER_TYPE_PROCESSOR: - pDst = memdescMapInternal(pGpu, pDstInfo->pMemDesc, TRANSFER_FLAGS_NONE); - NV_ASSERT_OR_RETURN(pDst != NULL, NV_ERR_INSUFFICIENT_RESOURCES); - - portMemCopy(pDst + pDstInfo->offset, size, pBuf, size); - - memdescUnmapInternal(pGpu, pDstInfo->pMemDesc, flags); + if (memmgrMemWriteMapAndCopy(pMemoryManager, pDstInfo->pMemDesc, pBuf, pDstInfo->offset, size, flags) != NV_OK) + { + // If we fail to map a block large enough for the entire transfer, split up the mapping. + NV_ASSERT_OK_OR_RETURN(memmgrMemWriteInBlocks(pMemoryManager, pDstInfo->pMemDesc, pBuf, + pDstInfo->offset, size, flags, MEMORY_COPY_BLOCK_SIZE)); + } break; case TRANSFER_TYPE_GSP_DMA: NV_PRINTF(LEVEL_INFO, "Add call to GSP DMA task\n"); diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/method_notification.c b/src/nvidia/src/kernel/gpu/mem_mgr/method_notification.c index f0559e2cd..12e512f37 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/method_notification.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/method_notification.c @@ -570,7 +570,12 @@ NV_STATUS semaphoreFillGPUVATimestamp if (status != NV_OK) return status; - semaphoreGPUVA = SemaphoreGPUVABase + (Index * sizeof(NvGpuSemaphore)); + if (!portSafeAddU64(SemaphoreGPUVABase, + (NvU64) (Index * sizeof(NvGpuSemaphore)), + &semaphoreGPUVA)) + { + return NV_ERR_INVALID_ARGUMENT; + } bFound = CliGetDmaMappingInfo(hClient, RES_GET_HANDLE(pDevice), diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/objheap.c b/src/nvidia/src/kernel/gpu/mem_mgr/objheap.c index ae5f5791b..82591e810 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/objheap.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/objheap.c @@ -20,7 +20,7 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ -/***************************** Heap Rotuines *******************************\ +/***************************** Heap Routines *******************************\ * Heap object function definitions. * \***************************************************************************/ diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.c b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.c index d8d900b9e..6aae2f42d 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.c @@ -848,6 +848,8 @@ _pmaAddrtreeScanContiguous // This requirement is ensured in PMA NV_ASSERT(alignment >= pageSize && portUtilIsPowerOfTwo(alignment)); + *numPagesAlloc = 0; + // Only focus on the level above the pageSize level. Children are ignored. level = addrtreeGetTreeLevel(pageSize); if (level == 0) @@ -885,8 +887,6 @@ _pmaAddrtreeScanContiguous return NV_OK; } - *numPagesAlloc = 0; - if (bSkipEvict) { return NV_ERR_NO_MEMORY; @@ -1941,4 +1941,3 @@ void pmaAddrtreeSetEvictingFrames(void *pMap, NvU64 frameEvictionsInProcess) { ((PMA_ADDRTREE *)pMap)->frameEvictionsInProcess = frameEvictionsInProcess; } - diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/numa.c b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/numa.c index 04b6714c5..58e09cc7e 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/numa.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/numa.c @@ -264,11 +264,14 @@ scrub_exit: { void *pMap = NULL; NvU32 regId; + MEMORY_PROTECTION prot; NV_ASSERT((evictEnd - evictStart + 1) == actualSize); status = NV_ERR_NO_MEMORY; regId = findRegionID(pPma, evictStart); pMap = pPma->pRegions[regId]; + prot = pPma->pRegDescriptors[regId]->bProtected ? MEMORY_PROTECTION_PROTECTED : + MEMORY_PROTECTION_UNPROTECTED; if (pMap != NULL) { @@ -279,7 +282,7 @@ scrub_exit: // i.e., region evictStart to evictEnd is marked as 'ATTRIB_EVICTING' and will not // be returned to OS. // - status = _pmaEvictContiguous(pPma, pMap, evictStart, evictEnd); + status = _pmaEvictContiguous(pPma, pMap, evictStart, evictEnd, prot); if (status == NV_ERR_NO_MEMORY) { @@ -413,6 +416,7 @@ scrub_exit: NvU32 regId; NvU64 addrBase, addrLimit; void *pMap = NULL; + MEMORY_PROTECTION prot; if (validRegionList[regionIdx] == -1) { @@ -424,11 +428,13 @@ scrub_exit: addrBase = pPma->pRegDescriptors[regId]->base; addrLimit = pPma->pRegDescriptors[regId]->limit; + prot = pPma->pRegDescriptors[regId]->bProtected ? MEMORY_PROTECTION_PROTECTED : + MEMORY_PROTECTION_UNPROTECTED; status = _pmaEvictPages(pPma, pMap, &pPages[i], (NvU32)(allocationCount - i), &pPages[0], i, - pageSize, addrBase, addrLimit); + pageSize, addrBase, addrLimit, prot); if (status != NV_ERR_NO_MEMORY) { diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.c b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.c index b6a6764c4..72c74f8ec 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.c @@ -748,6 +748,8 @@ pmaAllocatePages_retry: for (regionIdx = 0; regionIdx < pPma->regSize; regionIdx++) { + MEMORY_PROTECTION prot; + if (regionList[regionIdx] == -1) { status = NV_ERR_NO_MEMORY; @@ -760,6 +762,8 @@ pmaAllocatePages_retry: addrBase = pPma->pRegDescriptors[regId]->base; addrLimit = pPma->pRegDescriptors[regId]->limit; + prot = pPma->pRegDescriptors[regId]->bProtected ? MEMORY_PROTECTION_PROTECTED : + MEMORY_PROTECTION_UNPROTECTED; // // If the start address of the range is less than the region's base @@ -889,7 +893,7 @@ pmaAllocatePages_retry: (evictStart - addrBase) >> PMA_PAGE_SHIFT, (evictEnd - addrBase) >> PMA_PAGE_SHIFT); - status = _pmaEvictContiguous(pPma, pMap, evictStart, evictEnd); + status = _pmaEvictContiguous(pPma, pMap, evictStart, evictEnd, prot); } else { @@ -920,7 +924,8 @@ pmaAllocatePages_retry: (evictPhysEnd - addrBase) >> PMA_PAGE_SHIFT); status = _pmaEvictPages(pPma, pMap, curPages, numPagesLeftToAllocate, - pPages, numPagesAllocatedSoFar, pageSize, evictPhysBegin, evictPhysEnd); + pPages, numPagesAllocatedSoFar, pageSize, + evictPhysBegin, evictPhysEnd, prot); } if (status == NV_OK) diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.c b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.c index b1847c5ba..c7f4fe7f6 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.c @@ -402,10 +402,11 @@ _pmaCleanupNumaReusePages NV_STATUS _pmaEvictContiguous ( - PMA *pPma, - void *pMap, - NvU64 evictStart, - NvU64 evictEnd + PMA *pPma, + void *pMap, + NvU64 evictStart, + NvU64 evictEnd, + MEMORY_PROTECTION prot ) { NV_STATUS status; @@ -429,7 +430,7 @@ _pmaEvictContiguous PSCRUB_NODE pPmaScrubList = NULL; portSyncMutexRelease(pPma->pAllocLock); - status = pPma->evictRangeCb(pPma->evictCtxPtr, evictStart, evictEnd); + status = pPma->evictRangeCb(pPma->evictCtxPtr, evictStart, evictEnd, prot); portSyncMutexAcquire(pPma->pAllocLock); @@ -477,7 +478,7 @@ scrub_exit: } else { - status = pPma->evictRangeCb(pPma->evictCtxPtr, evictStart, evictEnd); + status = pPma->evictRangeCb(pPma->evictCtxPtr, evictStart, evictEnd, prot); NV_PRINTF(LEVEL_INFO, "evictRangeCb returned with status %llx\n", (NvU64)status); } @@ -512,15 +513,16 @@ exit: NV_STATUS _pmaEvictPages ( - PMA *pPma, - void *pMap, - NvU64 *evictPages, - NvU64 evictPageCount, - NvU64 *allocPages, - NvU64 allocPageCount, - NvU32 pageSize, - NvU64 physBegin, - NvU64 physEnd + PMA *pPma, + void *pMap, + NvU64 *evictPages, + NvU64 evictPageCount, + NvU64 *allocPages, + NvU64 allocPageCount, + NvU32 pageSize, + NvU64 physBegin, + NvU64 physEnd, + MEMORY_PROTECTION prot ) { NvU64 i; @@ -550,7 +552,7 @@ _pmaEvictPages portSyncMutexRelease(pPma->pAllocLock); status = pPma->evictPagesCb(pPma->evictCtxPtr, pageSize, evictPages, - (NvU32)evictPageCount, physBegin, physEnd); + (NvU32)evictPageCount, physBegin, physEnd, prot); portSyncMutexAcquire(pPma->pAllocLock); NV_PRINTF(LEVEL_INFO, "evictPagesCb returned with status %llx\n", (NvU64)status); @@ -584,7 +586,7 @@ scrub_exit: else { status = pPma->evictPagesCb(pPma->evictCtxPtr, pageSize, evictPages, - (NvU32)evictPageCount, physBegin, physEnd); + (NvU32)evictPageCount, physBegin, physEnd, prot); NV_PRINTF(LEVEL_INFO, "evictPagesCb returned with status %llx\n", (NvU64)status); } @@ -861,7 +863,7 @@ _pmaPredictOutOfMemory /*! * @brief Internal function to intermittently free the blacklisted pages in the * range of allocation request. This will enable PMA to allow OS to manage those - * blacklisted pages after being allocated. + * blacklisted pages after being allocated. * * @param[in] pPma PMA Object * @param[in] regId PMA Region ID , where the allocation falls into diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/vaspace_api.c b/src/nvidia/src/kernel/gpu/mem_mgr/vaspace_api.c index 83df1a5d0..576262a54 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/vaspace_api.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/vaspace_api.c @@ -94,7 +94,7 @@ vaspaceapiConstruct_IMPL gpuMaskInitial = rmGpuLocksGetOwnedMask(); NvU32 lockFlag = (gpuMaskInitial == 0) ? GPUS_LOCK_FLAGS_NONE - : GPUS_LOCK_FLAGS_COND_ACQUIRE; + : GPU_LOCK_FLAGS_COND_ACQUIRE; NV_ASSERT_OK_OR_RETURN(rmGpuGroupLockAcquire(pGpu->gpuInstance, GPU_LOCK_GRP_ALL, @@ -663,6 +663,10 @@ static NV_STATUS translateAllocFlagsToVASpaceFlags(NvU32 allocFlags, NvU32 *tran { flags |= VASPACE_FLAGS_OPTIMIZE_PTETABLE_MEMPOOL_USAGE; } + if (allocFlags & NV_VASPACE_ALLOCATION_FLAGS_REQUIRE_FIXED_OFFSET) + { + flags |= VASPACE_FLAGS_REQUIRE_FIXED_OFFSET; + } flags |= VASPACE_FLAGS_ENABLE_VMM; // Validate the flag combinations diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/virt_mem_allocator.c b/src/nvidia/src/kernel/gpu/mem_mgr/virt_mem_allocator.c index 83e6d96a6..096f212e3 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/virt_mem_allocator.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/virt_mem_allocator.c @@ -21,7 +21,7 @@ * DEALINGS IN THE SOFTWARE. */ -/***************************** HW State Rotuines ***************************\ +/***************************** HW State Routines ***************************\ * * * VirtMemAllocator Object Function Definitions. * * * @@ -30,7 +30,7 @@ #include "core/core.h" #include "core/hal.h" #include "core/info_block.h" -#include "nvRmReg.h" +#include "nvrm_registry.h" #include "os/os.h" #include "vgpu/rpc.h" #include "gpu/gpu.h" @@ -72,6 +72,13 @@ static NV_STATUS dmaInitRegistryOverrides(OBJGPU *pGpu, VirtMemAllocator *pDma) { NV_STATUS rmStatus = NV_OK; + NvU32 data32; + + if (osReadRegistryDword(pGpu, NV_REG_ENABLE_MEMORY_MAPPER_API, &data32) == NV_OK && + data32 == NV_REG_ENABLE_MEMORY_MAPPER_API_TRUE) + { + pDma->bMemoryMapperApiEnabled = NV_TRUE; + } return rmStatus; } diff --git a/src/nvidia/src/kernel/gpu/mem_sys/arch/ampere/kern_mem_sys_ga100.c b/src/nvidia/src/kernel/gpu/mem_sys/arch/ampere/kern_mem_sys_ga100.c index 0631db7e3..eda94d20f 100644 --- a/src/nvidia/src/kernel/gpu/mem_sys/arch/ampere/kern_mem_sys_ga100.c +++ b/src/nvidia/src/kernel/gpu/mem_sys/arch/ampere/kern_mem_sys_ga100.c @@ -51,7 +51,7 @@ kmemsysProgramSysmemFlushBuffer_GA100 NV_ASSERT(pKernelMemorySystem->sysmemFlushBuffer != 0); - alignedSysmemFlushBufferAddr = pKernelMemorySystem->sysmemFlushBuffer >> NV_PFB_NISO_FLUSH_SYSMEM_ADDR_SHIFT; + alignedSysmemFlushBufferAddr = pKernelMemorySystem->sysmemFlushBuffer >> kmemsysGetFlushSysmemBufferAddrShift_HAL(pGpu, pKernelMemorySystem); alignedSysmemFlushBufferAddrHi = DRF_VAL(_PFB, _NISO_FLUSH_SYSMEM_ADDR_HI, _ADR_63_40, NvU64_HI32(alignedSysmemFlushBufferAddr)); @@ -99,7 +99,7 @@ kmemsysInitFlushSysmemBuffer_GA100 // status = memdescCreate(&pKernelMemorySystem->pSysmemFlushBufferMemDesc, pGpu, RM_PAGE_SIZE, - (1 << NV_PFB_NISO_FLUSH_SYSMEM_ADDR_SHIFT), + 1 << kmemsysGetFlushSysmemBufferAddrShift_HAL(pGpu, pKernelMemorySystem), NV_TRUE, ADDR_SYSMEM, NV_MEMORY_UNCACHED, diff --git a/src/nvidia/src/kernel/gpu/mem_sys/arch/hopper/kern_mem_sys_gh100.c b/src/nvidia/src/kernel/gpu/mem_sys/arch/hopper/kern_mem_sys_gh100.c index 5a79675cd..ef7a768f2 100644 --- a/src/nvidia/src/kernel/gpu/mem_sys/arch/hopper/kern_mem_sys_gh100.c +++ b/src/nvidia/src/kernel/gpu/mem_sys/arch/hopper/kern_mem_sys_gh100.c @@ -381,65 +381,6 @@ kmemsysProgramSysmemFlushBuffer_GH100 GPU_FLD_WR_DRF_NUM(pGpu, _PFB, _FBHUB_PCIE_FLUSH_SYSMEM_ADDR_LO, _ADR, alignedSysmemFlushBufferAddr); } -/* - * @brief Initialize the sysmem flush buffer - * - * Setting up the sysmem flush buffer needs to be done very early in some cases - * as it's required for the GPU to perform a system flush. One such case is - * resetting GPU FALCONs and in particular resetting the PMU as part of VBIOS - * init. - * - * @returns NV_OK if all is okay. Otherwise an error-specific value. - */ -NV_STATUS -kmemsysInitFlushSysmemBuffer_GH100 -( - OBJGPU *pGpu, - KernelMemorySystem *pKernelMemorySystem -) -{ - NV_STATUS status; - - // - // In case of suspend/resume, the buffer might be already allocated, but - // the HW still needs to be programmed below. - // - if (pKernelMemorySystem->pSysmemFlushBufferMemDesc == NULL) - { - // - // Sysmem flush buffer - // The sysmembar flush does a zero byte read of sysmem if there was a - // sysmem write since the last flush. The actual memory does have - // to be valid and allocated at all times because an actual read may - // be issued (observed on e.g. GF108). - // - status = memdescCreate(&pKernelMemorySystem->pSysmemFlushBufferMemDesc, - pGpu, RM_PAGE_SIZE, - (1 << NV_PFB_NISO_FLUSH_SYSMEM_ADDR_SHIFT), - NV_TRUE, - ADDR_SYSMEM, - NV_MEMORY_UNCACHED, - MEMDESC_FLAGS_NONE); - if (status != NV_OK) - return status; - - status = memdescAlloc(pKernelMemorySystem->pSysmemFlushBufferMemDesc); - - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "Could not allocate sysmem flush buffer: %x\n", status); - DBG_BREAKPOINT(); - return status; - } - - pKernelMemorySystem->sysmemFlushBuffer = memdescGetPhysAddr(pKernelMemorySystem->pSysmemFlushBufferMemDesc, AT_GPU, 0); - } - - kmemsysProgramSysmemFlushBuffer_HAL(pGpu, pKernelMemorySystem); - return NV_OK; -} - /*! * @brief Validate the sysmemFlushBuffer val and assert * diff --git a/src/nvidia/src/kernel/gpu/mem_sys/arch/maxwell/kern_mem_sys_gm107.c b/src/nvidia/src/kernel/gpu/mem_sys/arch/maxwell/kern_mem_sys_gm107.c index 7e79748fa..d7c8886ae 100644 --- a/src/nvidia/src/kernel/gpu/mem_sys/arch/maxwell/kern_mem_sys_gm107.c +++ b/src/nvidia/src/kernel/gpu/mem_sys/arch/maxwell/kern_mem_sys_gm107.c @@ -232,7 +232,7 @@ kmemsysInitFlushSysmemBuffer_GM107 // status = memdescCreate(&pKernelMemorySystem->pSysmemFlushBufferMemDesc, pGpu, RM_PAGE_SIZE, - (1 << NV_PFB_NISO_FLUSH_SYSMEM_ADDR_SHIFT), + (1 << kmemsysGetFlushSysmemBufferAddrShift_HAL(pGpu, pKernelMemorySystem)), NV_TRUE, ADDR_SYSMEM, NV_MEMORY_UNCACHED, @@ -267,7 +267,7 @@ kmemsysInitFlushSysmemBuffer_GM107 if (!bTryAgain) { GPU_FLD_WR_DRF_NUM(pGpu, _PFB, _NISO_FLUSH_SYSMEM_ADDR, _ADR_39_08, - NvU64_LO32(pKernelMemorySystem->sysmemFlushBuffer >> NV_PFB_NISO_FLUSH_SYSMEM_ADDR_SHIFT)); + NvU64_LO32(pKernelMemorySystem->sysmemFlushBuffer >> kmemsysGetFlushSysmemBufferAddrShift_HAL(pGpu, pKernelMemorySystem))); return NV_OK; } @@ -277,7 +277,7 @@ kmemsysInitFlushSysmemBuffer_GM107 status = memdescCreate(&pKernelMemorySystem->pSysmemFlushBufferMemDesc, pGpu, RM_PAGE_SIZE, - (1 << NV_PFB_NISO_FLUSH_SYSMEM_ADDR_SHIFT), + (1 << kmemsysGetFlushSysmemBufferAddrShift_HAL(pGpu, pKernelMemorySystem)), NV_TRUE, ADDR_SYSMEM, NV_MEMORY_UNCACHED, @@ -345,10 +345,6 @@ kmemsysInitFlushSysmemBuffer_GM107 // MODS on DGX-2 is hitting this. Make it non-fatal for now with // the proper WAR implementation tracked in bug 2403630. // - if (RMCFG_FEATURE_PLATFORM_MODS) - { - bMakeItFatal = NV_FALSE; - } // // Windows on greater than 2 TB systems is hitting this. Making it @@ -369,7 +365,7 @@ kmemsysInitFlushSysmemBuffer_GM107 NV_ASSERT(pKernelMemorySystem->sysmemFlushBuffer != 0); GPU_FLD_WR_DRF_NUM(pGpu, _PFB, _NISO_FLUSH_SYSMEM_ADDR, _ADR_39_08, - NvU64_LO32(pKernelMemorySystem->sysmemFlushBuffer >> NV_PFB_NISO_FLUSH_SYSMEM_ADDR_SHIFT)); + NvU64_LO32(pKernelMemorySystem->sysmemFlushBuffer >> kmemsysGetFlushSysmemBufferAddrShift_HAL(pGpu, pKernelMemorySystem))); return NV_OK; } @@ -398,7 +394,7 @@ kmemsysProgramSysmemFlushBuffer_GM107 // A: Because on power management resume, this value should be restored too. // GPU_FLD_WR_DRF_NUM(pGpu, _PFB, _NISO_FLUSH_SYSMEM_ADDR, _ADR_39_08, - NvU64_LO32(pKernelMemorySystem->sysmemFlushBuffer >> NV_PFB_NISO_FLUSH_SYSMEM_ADDR_SHIFT)); + NvU64_LO32(pKernelMemorySystem->sysmemFlushBuffer >> kmemsysGetFlushSysmemBufferAddrShift_HAL(pGpu, pKernelMemorySystem))); } /*! @@ -418,3 +414,13 @@ kmemsysAssertSysmemFlushBufferValid_GM107 { NV_ASSERT(GPU_REG_RD_DRF(pGpu, _PFB, _NISO_FLUSH_SYSMEM_ADDR, _ADR_39_08) != 0); } + +NvU32 +kmemsysGetFlushSysmemBufferAddrShift_GM107 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem +) +{ + return NV_PFB_NISO_FLUSH_SYSMEM_ADDR_SHIFT; +} diff --git a/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c b/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c index 83cb36924..268644cd3 100644 --- a/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c +++ b/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c @@ -33,28 +33,6 @@ #include "nvRmReg.h" #include "gpu/gsp/gsp_static_config.h" -NV_STATUS -kmemsysConstructEngine_IMPL -( - OBJGPU *pGpu, - KernelMemorySystem *pKernelMemorySystem, - ENGDESCRIPTOR engDesc -) -{ - pKernelMemorySystem->memPartitionNumaInfo = NULL; - - if (IS_GSP_CLIENT(pGpu)) - { - // Setting up the sysmem flush buffer needs to be done very early in some cases - // as it's required for the GPU to perform a system flush. One such case is - // resetting GPU FALCONs and in particular resetting the PMU as part of VBIOS - // init. - NV_ASSERT_OK_OR_RETURN(kmemsysInitFlushSysmemBuffer_HAL(pGpu, pKernelMemorySystem)); - } - - return NV_OK; -} - static void kmemsysInitRegistryOverrides ( @@ -74,6 +52,30 @@ kmemsysInitRegistryOverrides } } +NV_STATUS +kmemsysConstructEngine_IMPL +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem, + ENGDESCRIPTOR engDesc +) +{ + pKernelMemorySystem->memPartitionNumaInfo = NULL; + + kmemsysInitRegistryOverrides(pGpu, pKernelMemorySystem); + + if (IS_GSP_CLIENT(pGpu)) + { + // Setting up the sysmem flush buffer needs to be done very early in some cases + // as it's required for the GPU to perform a system flush. One such case is + // resetting GPU FALCONs and in particular resetting the PMU as part of VBIOS + // init. + NV_ASSERT_OK_OR_RETURN(kmemsysInitFlushSysmemBuffer_HAL(pGpu, pKernelMemorySystem)); + } + + return NV_OK; +} + /* * Initialize the Kernel Memory System state. * @@ -95,7 +97,7 @@ NV_STATUS kmemsysStateInitLocked_IMPL pStaticConfig = portMemAllocNonPaged(sizeof(*pStaticConfig)); NV_CHECK_OR_RETURN(LEVEL_ERROR, pStaticConfig != NULL, NV_ERR_INSUFFICIENT_RESOURCES); - portMemSet(pStaticConfig, 0, sizeof(pStaticConfig)); + portMemSet(pStaticConfig, 0, sizeof(*pStaticConfig)); NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, kmemsysInitStaticConfig_HAL(pGpu, pKernelMemorySystem, pStaticConfig), @@ -103,8 +105,6 @@ NV_STATUS kmemsysStateInitLocked_IMPL pKernelMemorySystem->pStaticConfig = pStaticConfig; - kmemsysInitRegistryOverrides(pGpu, pKernelMemorySystem); - fail: if (status != NV_OK) { @@ -209,6 +209,8 @@ kmemsysAllocComprResources_KERNEL { if (!(IS_SIMULATION(pGpu) || IsDFPGA(pGpu) || (IS_EMULATION(pGpu) && RMCFG_FEATURE_PLATFORM_MODS) ||(RMCFG_FEATURE_PLATFORM_WINDOWS && !pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_TCC_MODE)) + ||hypervisorIsVgxHyper() + ||IS_GFID_VF(gfid) ||(IsSLIEnabled(pGpu) && !(RMCFG_FEATURE_PLATFORM_WINDOWS && !pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_TCC_MODE)))) ) @@ -581,7 +583,7 @@ kmemsysSetupCoherentCpuLink_IMPL NvU64 numaOnlineBase = 0; NvU64 numaOnlineSize = 0; NvU32 data32; - NvBool bCpuMapping; + NvBool bCpuMapping = NV_TRUE; // Default enable { NV_ASSERT_OK_OR_RETURN(kmemsysGetFbNumaInfo_HAL(pGpu, pKernelMemorySystem, @@ -603,7 +605,6 @@ kmemsysSetupCoherentCpuLink_IMPL } } - // ATS mappings are currently not supported in mods if ((osReadRegistryDword(pGpu, NV_REG_STR_OVERRIDE_GPU_NUMA_NODE_ID, &data32)) == NV_OK) { @@ -612,9 +613,6 @@ kmemsysSetupCoherentCpuLink_IMPL pGpu->numaNodeId); } - // Default enable - bCpuMapping = NV_TRUE; - // Parse regkey here if ((osReadRegistryDword(pGpu, NV_REG_STR_RM_FORCE_BAR_PATH, &data32) == NV_OK) && @@ -630,6 +628,7 @@ kmemsysSetupCoherentCpuLink_IMPL { return NV_OK; } + NV_ASSERT_OK_OR_RETURN(kbusCreateCoherentCpuMapping_HAL(pGpu, pKernelBus, bFlush)); // Switch the toggle for coherent link mapping only if migration is successful diff --git a/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys_ctrl.c b/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys_ctrl.c index 2d86fc763..ab356cfef 100644 --- a/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys_ctrl.c +++ b/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys_ctrl.c @@ -703,7 +703,7 @@ subdeviceCtrlCmdFbGetInfo_IMPL NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); NvHandle hObject = RES_GET_HANDLE(pSubdevice); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); if ((pFbInfoParams->fbInfoListSize == 0) || (NvP64_VALUE(pFbInfoParams->fbInfoList) == NULL)) @@ -731,7 +731,7 @@ subdeviceCtrlCmdFbGetInfoV2_IMPL NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); NvHandle hObject = RES_GET_HANDLE(pSubdevice); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); if ((pFbInfoParams->fbInfoListSize > NV2080_CTRL_FB_INFO_MAX_LIST_SIZE) || (pFbInfoParams->fbInfoListSize == 0)) @@ -756,7 +756,7 @@ subdeviceCtrlCmdFbGetCarveoutAddressInfo_IMPL ) { - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); pParams->StartAddr = 0x0; pParams->SpaceSize = 0x0; @@ -799,7 +799,7 @@ subdeviceCtrlCmdFbGetGpuCacheAllocPolicy_IMPL { NV_STATUS status = NV_ERR_NOT_SUPPORTED; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); pGpuCacheAllocPolicyParams->allocPolicy = 0; @@ -847,7 +847,7 @@ subdeviceCtrlCmdFbGetGpuCacheAllocPolicyV2_IMPL { NV_STATUS status = NV_ERR_NOT_SUPPORTED; - NV_ASSERT_OR_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner(), NV_ERR_INVALID_LOCK_STATE); + NV_ASSERT_OR_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner(), NV_ERR_INVALID_LOCK_STATE); NV_PRINTF(LEVEL_ERROR, "Failed to get alloc policy.\n"); return status; @@ -879,7 +879,7 @@ subdeviceCtrlCmdFbGetCliManagedOfflinedPages_IMPL NvU32 pageSize; NvU32 numChunks = 0; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); if (!IsSLIEnabled(pGpu)) { if (memmgrIsPmaInitialized(pMemoryManager)) @@ -946,7 +946,7 @@ subdeviceCtrlCmdFbUpdateNumaStatus_IMPL if (!RMCFG_FEATURE_PMA) return NV_ERR_NOT_SUPPORTED; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); if (pParams->bOnline) { @@ -992,7 +992,7 @@ subdeviceCtrlCmdFbGetNumaInfo_IMPL const MEMORY_SYSTEM_STATIC_CONFIG *pMemorySystemConfig = kmemsysGetStaticConfig(pGpu, pKernelMemorySystem); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); if (pParams->numaOfflineAddressesCount > NV_ARRAY_ELEMENTS(pParams->numaOfflineAddresses)) @@ -1135,7 +1135,7 @@ subdeviceCtrlCmdFbFlushGpuCache_IMPL NvBool bWriteback = NV_FALSE; NvBool bInvalidate = NV_FALSE; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); // Either WriteBack or Invalidate are required for Cache Ops if (FLD_TEST_DRF(2080, _CTRL_FB_FLUSH_GPU_CACHE_FLAGS, _WRITE_BACK, diff --git a/src/nvidia/src/kernel/gpu/mig_mgr/arch/ampere/kmigmgr_ga100.c b/src/nvidia/src/kernel/gpu/mig_mgr/arch/ampere/kmigmgr_ga100.c index 41a566352..3b90601e6 100644 --- a/src/nvidia/src/kernel/gpu/mig_mgr/arch/ampere/kmigmgr_ga100.c +++ b/src/nvidia/src/kernel/gpu/mig_mgr/arch/ampere/kmigmgr_ga100.c @@ -25,6 +25,7 @@ #include "kernel/gpu/mem_mgr/heap.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "kernel/gpu/fifo/kernel_fifo.h" +#include "gpu/bus/kern_bus.h" #include "published/ampere/ga100/dev_bus.h" #include "published/ampere/ga100/dev_bus_addendum.h" @@ -63,7 +64,7 @@ kmigmgrCreateGPUInstanceCheck_GA100 { Heap *pHeap; KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); - NvU32 engines[NV2080_ENGINE_TYPE_LAST]; + RM_ENGINE_TYPE engines[RM_ENGINE_TYPE_LAST]; NvU32 engineCount; NvU32 i; NvU64 largestFreeSize; @@ -87,14 +88,14 @@ kmigmgrCreateGPUInstanceCheck_GA100 // partitioning isn't really a destructive operation anyway, so // skip checking for copy engines // - if (NV2080_ENGINE_TYPE_IS_COPY(pGpu->engineDB.pType[i]) && + if (RM_ENGINE_TYPE_IS_COPY(pGpu->engineDB.pType[i]) && !bMemoryPartitioningNeeded) { continue; } - if (NV2080_ENGINE_TYPE_IS_GR(pGpu->engineDB.pType[i]) && - (NV2080_ENGINE_TYPE_GR_IDX(pGpu->engineDB.pType[i]) > 0)) + if (RM_ENGINE_TYPE_IS_GR(pGpu->engineDB.pType[i]) && + (RM_ENGINE_TYPE_GR_IDX(pGpu->engineDB.pType[i]) > 0)) { // // This check is used during GPU instance creation, prior to which @@ -111,6 +112,19 @@ kmigmgrCreateGPUInstanceCheck_GA100 // Make sure there are no channels alive on any of these engines if (kfifoEngineListHasChannel(pGpu, pKernelFifo, engines, engineCount)) return NV_ERR_STATE_IN_USE; + + // + // Check for any alive P2P references to this GPU. P2P objects must + // be re-created after disabling MIG. If it is allowed for MIG to + // continue enablement without all P2P objects torn down, there is + // the possibility that P2P mappings and state will never be updated. + // + if (bMemoryPartitioningNeeded || !kmigmgrIsMIGNvlinkP2PSupportOverridden(pGpu, pKernelMIGManager)) + { + NV_CHECK_OR_RETURN(LEVEL_ERROR, + !kbusIsGpuP2pAlive(pGpu, GPU_GET_KERNEL_BUS(pGpu)), + NV_ERR_STATE_IN_USE); + } pHeap = GPU_GET_HEAP(pGpu); if (!memmgrIsPmaInitialized(pMemoryManager)) @@ -173,6 +187,7 @@ kmigmgrIsGPUInstanceFlagValid_GA100 case NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF: case NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF: case NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER: + case NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_QUARTER: case NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH: break; default: @@ -209,7 +224,8 @@ kmigmgrIsGPUInstanceCombinationValid_GA100 { if (kmigmgrIsA100ReducedConfig(pGpu, pKernelMIGManager)) { - if (computeSizeFlag != NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER) + if ((computeSizeFlag != NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF) && + (computeSizeFlag != NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER)) { return NV_FALSE; } @@ -221,7 +237,8 @@ kmigmgrIsGPUInstanceCombinationValid_GA100 } if (kmigmgrIsA100ReducedConfig(pGpu, pKernelMIGManager) && - computeSizeFlag == NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF) + ((computeSizeFlag == NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF) || + (computeSizeFlag == NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_QUARTER))) { return NV_FALSE; } @@ -244,6 +261,10 @@ kmigmgrIsGPUInstanceCombinationValid_GA100 NV_CHECK_OR_RETURN(LEVEL_SILENT, memSizeFlag == NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_QUARTER, NV_FALSE); break; + case NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_QUARTER: + NV_CHECK_OR_RETURN(LEVEL_SILENT, memSizeFlag == NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_QUARTER, + NV_FALSE); + break; case NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH: NV_CHECK_OR_RETURN(LEVEL_SILENT, memSizeFlag == NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_EIGHTH, NV_FALSE); @@ -344,4 +365,3 @@ kmigmgrIsMemoryPartitioningNeeded_GA100 // Memory partitioning is needed for non-zero swizzIds return (swizzId != 0); } - diff --git a/src/nvidia/src/kernel/gpu/mig_mgr/arch/hopper/kmigmgr_gh100.c b/src/nvidia/src/kernel/gpu/mig_mgr/arch/hopper/kmigmgr_gh100.c index 3b84ae462..76540847c 100644 --- a/src/nvidia/src/kernel/gpu/mig_mgr/arch/hopper/kmigmgr_gh100.c +++ b/src/nvidia/src/kernel/gpu/mig_mgr/arch/hopper/kmigmgr_gh100.c @@ -48,7 +48,6 @@ kmigmgrIsGPUInstanceFlagValid_GH100 _MEMORY_SIZE, gpuInstanceFlag); NvU32 computeSizeFlag = DRF_VAL(2080_CTRL_GPU, _PARTITION_FLAG, _COMPUTE_SIZE, gpuInstanceFlag); - switch (memSizeFlag) { case NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL: @@ -76,7 +75,6 @@ kmigmgrIsGPUInstanceFlagValid_GH100 computeSizeFlag); return NV_FALSE; } - return NV_TRUE; } @@ -128,8 +126,8 @@ kmigmgrIsGPUInstanceCombinationValid_GH100 NV_FALSE); break; case NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_QUARTER: - // TODO: Add in extra check once NVML supports MINI_QUARTER being broadcast - return NV_FALSE; + NV_CHECK_OR_RETURN(LEVEL_SILENT, memSizeFlag == NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_QUARTER, + NV_FALSE); break; case NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH: NV_CHECK_OR_RETURN(LEVEL_SILENT, memSizeFlag == NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_EIGHTH, diff --git a/src/nvidia/src/kernel/gpu/mig_mgr/gpu_instance_subscription.c b/src/nvidia/src/kernel/gpu/mig_mgr/gpu_instance_subscription.c index 763dcd7e9..9def54ebe 100644 --- a/src/nvidia/src/kernel/gpu/mig_mgr/gpu_instance_subscription.c +++ b/src/nvidia/src/kernel/gpu/mig_mgr/gpu_instance_subscription.c @@ -126,8 +126,8 @@ gisubscriptionConstruct_IMPL } // - // Root-SwizzID is a special swizzID which doesn't have any GPU instance - // associated with it. It can be subscribed to even without GPU instances + // Root-SwizzID is a special swizzID which doesn't have any GPU instance + // associated with it. It can be subscribed to even without GPU instances // if (swizzId == NVC637_DEVICE_PROFILING_SWIZZID) { @@ -231,7 +231,7 @@ gisubscriptionCopyConstruct_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pGPUInstanceSubscription); { - // non kernel clients are not allowed to dup GPU instances + // non kernel clients are not allowed to dup GPU instances NV_CHECK_OR_RETURN(LEVEL_SILENT, pCallContext->secInfo.privLevel >= RS_PRIV_LEVEL_KERNEL, NV_ERR_NOT_SUPPORTED); } @@ -360,7 +360,7 @@ gisubscriptionCtrlCmdExecPartitionsCreate_IMPL KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance = pGPUInstanceSubscription->pKernelMIGGpuInstance; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); { CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); @@ -405,13 +405,13 @@ gisubscriptionCtrlCmdExecPartitionsCreate_IMPL { .type = KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS_TYPE_REQUEST, .inst.request.count = pParams->execPartCount, - .inst.request.pReqComputeInstanceInfo = pParams->execPartInfo + .inst.request.pReqComputeInstanceInfo = pParams->execPartInfo, + .inst.request.requestFlags = pParams->flags }; - if (hypervisorIsVgxHyper() && - FLD_TEST_REF(NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_WITH_PART_ID, _TRUE, pParams->flags)) + if (!hypervisorIsVgxHyper()) { - request.type = KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS_TYPE_REQUEST_WITH_IDS; + request.inst.request.requestFlags = FLD_SET_DRF(C637_CTRL, _DMA_EXEC_PARTITIONS_CREATE_REQUEST, _WITH_PART_ID, _FALSE, request.inst.request.requestFlags); } if (IS_VIRTUAL(pGpu)) @@ -439,7 +439,7 @@ gisubscriptionCtrlCmdExecPartitionsCreate_IMPL KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS restore = { .type = KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS_TYPE_RESTORE, - .inst.restore.pComputeInstanceSave = &save, + .inst.restore.pComputeInstanceSave = &save, }; portMemSet(&export, 0, sizeof(export)); export.id = pParams->execPartId[i]; @@ -465,7 +465,7 @@ gisubscriptionCtrlCmdExecPartitionsCreate_IMPL } // - // Generate a subdevice event stating something has changed in GPU instance + // Generate a subdevice event stating something has changed in GPU instance // config. Clients currently do not care about changes and their scope // if (!pParams->bQuery) @@ -495,7 +495,7 @@ gisubscriptionCtrlCmdExecPartitionsDelete_IMPL KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance = pGPUInstanceSubscription->pKernelMIGGpuInstance; NvU32 execPartIdx; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); { CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); @@ -522,7 +522,7 @@ gisubscriptionCtrlCmdExecPartitionsDelete_IMPL // Check for trivial arguments NV_CHECK_OR_RETURN(LEVEL_SILENT, pParams->execPartCount > 0, NV_WARN_NOTHING_TO_DO); - // Check that the passed indices are valid compute instances + // Check that the passed indices are valid compute instances for (execPartIdx = 0; execPartIdx < pParams->execPartCount; ++execPartIdx) { NvU32 execPartId = pParams->execPartId[execPartIdx]; @@ -551,7 +551,7 @@ gisubscriptionCtrlCmdExecPartitionsDelete_IMPL } // - // Generate a subdevice event stating something has changed in GPU instance + // Generate a subdevice event stating something has changed in GPU instance // config. Clients currently do not care about changes and their scope // gpuNotifySubDeviceEvent(pGpu, NV2080_NOTIFIERS_SMC_CONFIG_UPDATE, NULL, 0, 0, 0); @@ -592,17 +592,21 @@ gisubscriptionCtrlCmdExecPartitionsGet_IMPL NvU32 ciIdx; NvHandle hClient = RES_GET_CLIENT_HANDLE(pGPUInstanceSubscription); CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + NvBool bEnumerateAll = NV_FALSE; NV_ASSERT_OR_RETURN(pCallContext != NULL, NV_ERR_INVALID_STATE); - NV_ASSERT_OR_RETURN(RMCFG_FEATURE_KERNEL_RM, NV_ERR_NOT_SUPPORTED); - NvBool bEnumerateAll = rmclientIsCapableOrAdminByHandle(hClient, - NV_RM_CAP_SYS_SMC_CONFIG, - pCallContext->secInfo.privLevel); + // Capability checks shouldn't be done on + if (!RMCFG_FEATURE_PLATFORM_GSP) + { + bEnumerateAll = rmclientIsCapableOrAdminByHandle(hClient, + NV_RM_CAP_SYS_SMC_CONFIG, + pCallContext->secInfo.privLevel); + } MIG_COMPUTE_INSTANCE *pTargetComputeInstanceInfo = NULL; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); NV_ASSERT_OR_RETURN(pGpu->getProperty(pGpu, PDB_PROP_GPU_MIG_SUPPORTED), NV_ERR_NOT_SUPPORTED); @@ -612,7 +616,6 @@ gisubscriptionCtrlCmdExecPartitionsGet_IMPL (void)cisubscriptionGetComputeInstanceSubscription(RES_GET_CLIENT(pGPUInstanceSubscription), RES_GET_HANDLE(pGPUInstanceSubscription), &pComputeInstanceSubscription); if (pComputeInstanceSubscription != NULL) { - bEnumerateAll = NV_FALSE; pTargetComputeInstanceInfo = pComputeInstanceSubscription->pMIGComputeInstance; } else if (!bEnumerateAll) @@ -642,17 +645,20 @@ gisubscriptionCtrlCmdExecPartitionsGet_IMPL pOutInfo->gpcCount = pMIGComputeInstance->resourceAllocation.gpcCount; pOutInfo->veidCount = pMIGComputeInstance->resourceAllocation.veidCount; pOutInfo->ceCount = kmigmgrCountEnginesOfType(&pMIGComputeInstance->resourceAllocation.engines, - NV2080_ENGINE_TYPE_COPY(0)); + RM_ENGINE_TYPE_COPY(0)); pOutInfo->nvEncCount = kmigmgrCountEnginesOfType(&pMIGComputeInstance->resourceAllocation.engines, - NV2080_ENGINE_TYPE_NVENC(0)); + RM_ENGINE_TYPE_NVENC(0)); pOutInfo->nvDecCount = kmigmgrCountEnginesOfType(&pMIGComputeInstance->resourceAllocation.engines, - NV2080_ENGINE_TYPE_NVDEC(0)); + RM_ENGINE_TYPE_NVDEC(0)); pOutInfo->nvJpgCount = kmigmgrCountEnginesOfType(&pMIGComputeInstance->resourceAllocation.engines, - NV2080_ENGINE_TYPE_NVJPG); + RM_ENGINE_TYPE_NVJPG); pOutInfo->ofaCount = kmigmgrCountEnginesOfType(&pMIGComputeInstance->resourceAllocation.engines, - NV2080_ENGINE_TYPE_OFA); + RM_ENGINE_TYPE_OFA); pOutInfo->sharedEngFlag = pMIGComputeInstance->sharedEngFlag; pOutInfo->veidStartOffset = pMIGComputeInstance->resourceAllocation.veidOffset; + pOutInfo->smCount = pMIGComputeInstance->resourceAllocation.smCount; + pOutInfo->computeSize = pMIGComputeInstance->computeSize; + pOutInfo->spanStart = pMIGComputeInstance->spanStart; } return status; @@ -676,7 +682,7 @@ gisubscriptionCtrlCmdExecPartitionsGetActiveIds_IMPL KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance = pGPUInstanceSubscription->pKernelMIGGpuInstance; NvU32 ciIdx; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); NV_ASSERT_OR_RETURN(pGpu->getProperty(pGpu, PDB_PROP_GPU_MIG_SUPPORTED), NV_ERR_NOT_SUPPORTED); @@ -774,6 +780,10 @@ gisubscriptionCtrlCmdExecPartitionsExport_IMPL pParams->info.sharedEngFlags = pMIGComputeInstance->sharedEngFlag; pParams->info.veidOffset = pMIGComputeInstance->resourceAllocation.veidOffset; pParams->info.veidCount = pMIGComputeInstance->resourceAllocation.veidCount; + pParams->info.smCount = pMIGComputeInstance->resourceAllocation.smCount; + pParams->info.spanStart = pMIGComputeInstance->spanStart; + pParams->info.computeSize = pMIGComputeInstance->computeSize; + for (gpcIdx = 0; gpcIdx < pMIGComputeInstance->resourceAllocation.gpcCount; ++gpcIdx) { pParams->info.gpcMask |= NVBIT32(pMIGComputeInstance->resourceAllocation.gpcIds[gpcIdx]); @@ -840,7 +850,7 @@ gisubscriptionCtrlCmdExecPartitionsImport_IMPL KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS restore = { .type = KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS_TYPE_RESTORE, - .inst.restore.pComputeInstanceSave = &save, + .inst.restore.pComputeInstanceSave = &save, }; portMemSet(&save, 0, sizeof(save)); @@ -879,7 +889,7 @@ cleanup_rpc: RES_GET_HANDLE(pGPUInstanceSubscription), NVC637_CTRL_CMD_EXEC_PARTITIONS_DELETE, ¶ms, - sizeof(params))); + sizeof(params))); } return status; @@ -1006,3 +1016,152 @@ done: return; } +NV_STATUS +gisubscriptionCtrlCmdExecPartitionsGetProfileCapacity_IMPL +( + GPUInstanceSubscription *pGPUInstanceSubscription, + NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pGPUInstanceSubscription); + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance = pGPUInstanceSubscription->pKernelMIGGpuInstance; + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + NvBool bCtsRequired = kmigmgrIsCTSAlignmentRequired(pGpu, pKernelMIGManager); + + NV_CHECK_OR_RETURN(LEVEL_ERROR, + pParams->computeSize < NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE, + NV_ERR_INVALID_ARGUMENT); + + if (bCtsRequired) + { + NV_RANGE totalRange = kmigmgrComputeProfileSizeToCTSIdRange(pParams->computeSize); + NvU32 slotBasisComputeSize = kmigmgrSmallestComputeProfileSize(pGpu, pKernelMIGManager); + NvU64 slotBasisMask; + NvU64 validQueryMask; + NvU64 inUseIdMask; + NvU64 ctsId; + NvU32 totalSpanCount; + NvU32 availableSpanCount; + NV_RANGE slotBasisIdRange; + + NV_CHECK_OR_RETURN(LEVEL_ERROR, slotBasisComputeSize != KMIGMGR_COMPUTE_SIZE_INVALID, NV_ERR_INVALID_STATE); + + slotBasisIdRange = kmigmgrComputeProfileSizeToCTSIdRange(slotBasisComputeSize); + + NV_CHECK_OR_RETURN(LEVEL_ERROR, !rangeIsEmpty(totalRange), NV_ERR_INVALID_ARGUMENT); + NV_CHECK_OR_RETURN(LEVEL_ERROR, !rangeIsEmpty(slotBasisIdRange), NV_ERR_INVALID_ARGUMENT); + + slotBasisMask = DRF_SHIFTMASK64(slotBasisIdRange.hi:slotBasisIdRange.lo); + validQueryMask = DRF_SHIFTMASK64(totalRange.hi:totalRange.lo) & pKernelMIGGpuInstance->pProfile->validCTSIdMask; + + // Find mask of un-usable IDs due to current in-use CTS Ids + inUseIdMask = 0x0; + FOR_EACH_INDEX_IN_MASK(64, ctsId, pKernelMIGGpuInstance->ctsIdsInUseMask) + { + NvU64 invalidMask; + + NV_ASSERT_OK(kmigmgrGetInvalidCTSIdMask(pGpu, pKernelMIGManager, ctsId, &invalidMask)); + + inUseIdMask |= invalidMask; + } + FOR_EACH_INDEX_IN_MASK_END; + + // + // The slot basis defines the smallest divison of the GPU instance. + // CTS IDs from this range are used as a means to specify span placements + // for compute profiles. + // + totalSpanCount = 0; + availableSpanCount = 0; + + FOR_EACH_INDEX_IN_MASK(64, ctsId, validQueryMask) + { + NvU64 invalidMask; + + NV_ASSERT_OK(kmigmgrGetInvalidCTSIdMask(pGpu, pKernelMIGManager, ctsId, &invalidMask)); + + invalidMask &= slotBasisMask; + pParams->totalSpans[totalSpanCount].lo = portUtilCountTrailingZeros64(invalidMask) - slotBasisIdRange.lo; + pParams->totalSpans[totalSpanCount].hi = nvPopCount64(invalidMask) + pParams->totalSpans[totalSpanCount].lo - 1; + + if (!(NVBIT64(ctsId) & inUseIdMask)) + { + pParams->availableSpans[availableSpanCount].lo = pParams->totalSpans[totalSpanCount].lo; + pParams->availableSpans[availableSpanCount].hi = pParams->totalSpans[totalSpanCount].hi; + availableSpanCount++; + } + totalSpanCount++; + } + FOR_EACH_INDEX_IN_MASK_END; + + pParams->totalSpansCount = totalSpanCount; + pParams->totalProfileCount = totalSpanCount; + pParams->availableSpansCount = availableSpanCount; + pParams->profileCount = availableSpanCount; + } + else + { + KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); + NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE profile; + NvU64 veidMask; + NvU32 GPUInstanceVeidEnd; + NvU64 GPUInstanceVeidMask; + NvU64 GPUInstanceFreeVeidMask; + NvU64 GPUInstancePseudoMask; + NvU32 availableSpanCount; + NvU32 totalSpanCount; + NvU32 veidStepSize; + NvU32 veidSlotCount; + NvU32 count; + NvU32 i; + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kmigmgrGetComputeProfileFromSize(pGpu, pKernelMIGManager, pParams->computeSize, &profile)); + NV_ASSERT_OK_OR_RETURN( + kgrmgrGetMaxVeidsPerGpc(pGpu, pKernelGraphicsManager, &veidStepSize)); + + // Create a mask for VEIDs associated with this GPU instance + veidMask = DRF_SHIFTMASK64(profile.veidCount - 1:0); + GPUInstanceVeidEnd = pKernelMIGGpuInstance->resourceAllocation.veidOffset + pKernelMIGGpuInstance->resourceAllocation.veidCount - 1; + GPUInstanceVeidMask = DRF_SHIFTMASK64(GPUInstanceVeidEnd:pKernelMIGGpuInstance->resourceAllocation.veidOffset); + GPUInstanceFreeVeidMask = GPUInstanceVeidMask & ~pKernelGraphicsManager->veidInUseMask; + GPUInstancePseudoMask = GPUInstanceFreeVeidMask; + veidSlotCount = 0; + availableSpanCount = 0; + totalSpanCount = 0; + count = 0; + for (i = pKernelMIGGpuInstance->resourceAllocation.veidOffset; i < GPUInstanceVeidEnd; i += veidStepSize) + { + // Determine max correctly sized VEID segments + if (((GPUInstanceFreeVeidMask >> i) & veidMask) == veidMask) + { + pParams->availableSpans[availableSpanCount].lo = count; + pParams->availableSpans[availableSpanCount].hi = count + (profile.veidCount / veidStepSize) - 1; + availableSpanCount++; + } + + // Determine max correctly sized VEID segments + if (((GPUInstanceVeidMask >> i) & veidMask) == veidMask) + { + pParams->totalSpans[totalSpanCount].lo = count; + pParams->totalSpans[totalSpanCount].hi = count + (profile.veidCount / veidStepSize) - 1; + totalSpanCount++; + } + + // Determine max correctly sized VEID segments + if (((GPUInstancePseudoMask >> i) & veidMask) == veidMask) + { + veidSlotCount++; + GPUInstancePseudoMask &= ~(veidMask << i); + } + count++; + } + pParams->totalProfileCount = NV_MIN(pKernelMIGGpuInstance->pProfile->virtualGpcCount / profile.gpcCount, + pKernelMIGGpuInstance->pProfile->veidCount / profile.veidCount); + pParams->totalSpansCount = totalSpanCount; + pParams->profileCount = veidSlotCount; + pParams->availableSpansCount = availableSpanCount; + } + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c b/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c index 1ea0f871a..b33971318 100644 --- a/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c +++ b/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c @@ -34,6 +34,8 @@ #include "kernel/gpu/mmu/kern_gmmu.h" #include "kernel/gpu/mem_mgr/heap.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" +#include "kernel/gpu/gpu_engine_type.h" +#include "kernel/gpu/gpu_fabric_probe.h" #include "rmapi/client.h" #include "rmapi/rs_utils.h" #include "rmapi/rmapi_utils.h" @@ -42,9 +44,11 @@ #include "kernel/gpu/gr/kernel_graphics_manager.h" #include "kernel/gpu/gr/kernel_graphics.h" #include "kernel/core/locks.h" +#include "class/cl503b.h" #include "nv_ref.h" #include "nvRmReg.h" -#include "class/cl503b.h" + +#include "kernel/gpu/ccu/kernel_ccu.h" struct KERNEL_MIG_MANAGER_PRIVATE_DATA { @@ -185,34 +189,34 @@ kmigmgrAreMIGReferencesSame_IMPL * @brief Count set bits within range indicated by given base type in bitvector * * @param[in] pEngines Bitvector to count - * @param[in] engineType 0th index NV2080_ENGINE_TYPE, only partitionable engines supported + * @param[in] rmEngineType 0th index RM_ENGINE_TYPE, only partitionable engines supported */ NvU32 kmigmgrCountEnginesOfType_IMPL ( const ENGTYPE_BIT_VECTOR *pEngines, - NvU32 engineType + RM_ENGINE_TYPE rmEngineType ) { - NV_RANGE range = rangeMake(engineType, engineType); + NV_RANGE range = rangeMake(rmEngineType, rmEngineType); ENGTYPE_BIT_VECTOR mask; if (pEngines == NULL) return 0; - if (!NV2080_ENGINE_TYPE_IS_VALID(engineType)) + if (!RM_ENGINE_TYPE_IS_VALID(rmEngineType)) return 0; - if (NV2080_ENGINE_TYPE_IS_GR(engineType)) - range = NV2080_ENGINE_RANGE_GR(); - else if (NV2080_ENGINE_TYPE_IS_COPY(engineType)) - range = NV2080_ENGINE_RANGE_COPY(); - else if (NV2080_ENGINE_TYPE_IS_NVDEC(engineType)) - range = NV2080_ENGINE_RANGE_NVDEC(); - else if (NV2080_ENGINE_TYPE_IS_NVENC(engineType)) - range = NV2080_ENGINE_RANGE_NVENC(); - else if (NV2080_ENGINE_TYPE_IS_NVJPEG(engineType)) - range = NV2080_ENGINE_RANGE_NVJPEG(); + if (RM_ENGINE_TYPE_IS_GR(rmEngineType)) + range = RM_ENGINE_RANGE_GR(); + else if (RM_ENGINE_TYPE_IS_COPY(rmEngineType)) + range = RM_ENGINE_RANGE_COPY(); + else if (RM_ENGINE_TYPE_IS_NVDEC(rmEngineType)) + range = RM_ENGINE_RANGE_NVDEC(); + else if (RM_ENGINE_TYPE_IS_NVENC(rmEngineType)) + range = RM_ENGINE_RANGE_NVENC(); + else if (RM_ENGINE_TYPE_IS_NVJPEG(rmEngineType)) + range = RM_ENGINE_RANGE_NVJPEG(); bitVectorClrAll(&mask); bitVectorSetRange(&mask, range); @@ -275,13 +279,13 @@ NV_STATUS kmigmgrEngineTypeXlate_IMPL ( ENGTYPE_BIT_VECTOR *pSrc, - NvU32 srcEngineType, + RM_ENGINE_TYPE srcEngineType, ENGTYPE_BIT_VECTOR *pDst, - NvU32 *pDstEngineType + RM_ENGINE_TYPE *pDstEngineType ) { - NvU32 tempSrcEngineType; - NvU32 tempDstEngineType; + RM_ENGINE_TYPE tempSrcEngineType; + RM_ENGINE_TYPE tempDstEngineType; NvBool bFound; NV_ASSERT_OR_RETURN(pSrc != NULL, NV_ERR_INVALID_ARGUMENT); @@ -311,18 +315,18 @@ kmigmgrEngineTypeXlate_IMPL // // below algorithm depends on contiguity of all partitionable engine values -// in NV2080_ENGINE_TYPE, so add asserts here. +// in RM_ENGINE_TYPE, so add asserts here. // Note - this only checks the first and last ID, a proper check would account // for all entries, but that's not possible at this time. // -ct_assert((NV2080_ENGINE_TYPE_GR(NV2080_ENGINE_TYPE_GR_SIZE - 1) - - NV2080_ENGINE_TYPE_GR(0)) == (NV2080_ENGINE_TYPE_GR_SIZE - 1)); -ct_assert((NV2080_ENGINE_TYPE_COPY(NV2080_ENGINE_TYPE_COPY_SIZE - 1) - - NV2080_ENGINE_TYPE_COPY(0)) == (NV2080_ENGINE_TYPE_COPY_SIZE - 1)); -ct_assert((NV2080_ENGINE_TYPE_NVDEC(NV2080_ENGINE_TYPE_NVDEC_SIZE - 1) - - NV2080_ENGINE_TYPE_NVDEC(0)) == (NV2080_ENGINE_TYPE_NVDEC_SIZE - 1)); -ct_assert((NV2080_ENGINE_TYPE_NVENC(NV2080_ENGINE_TYPE_NVENC_SIZE - 1) - - NV2080_ENGINE_TYPE_NVENC(0)) == (NV2080_ENGINE_TYPE_NVENC_SIZE - 1)); +ct_assert((RM_ENGINE_TYPE_GR(RM_ENGINE_TYPE_GR_SIZE - 1) - + RM_ENGINE_TYPE_GR(0)) == (RM_ENGINE_TYPE_GR_SIZE - 1)); +ct_assert((RM_ENGINE_TYPE_COPY(RM_ENGINE_TYPE_COPY_SIZE - 1) - + RM_ENGINE_TYPE_COPY(0)) == (RM_ENGINE_TYPE_COPY_SIZE - 1)); +ct_assert((RM_ENGINE_TYPE_NVDEC(RM_ENGINE_TYPE_NVDEC_SIZE - 1) - + RM_ENGINE_TYPE_NVDEC(0)) == (RM_ENGINE_TYPE_NVDEC_SIZE - 1)); +ct_assert((RM_ENGINE_TYPE_NVENC(RM_ENGINE_TYPE_NVENC_SIZE - 1) - + RM_ENGINE_TYPE_NVENC(0)) == (RM_ENGINE_TYPE_NVENC_SIZE - 1)); /*! * @brief Chooses the engines of the given type to allocate. Supports @@ -350,7 +354,7 @@ kmigmgrAllocateInstanceEngines_IMPL { NvU32 allocated = 0; ENGTYPE_BIT_VECTOR engines; - NvU32 engineType; + RM_ENGINE_TYPE rmEngineType; NvU32 localIdx; // If using shared engines, allocate as many from existing shared engines as possible @@ -360,13 +364,13 @@ kmigmgrAllocateInstanceEngines_IMPL bitVectorSetRange(&engines, engTypeRange); bitVectorAnd(&engines, &engines, pSourceEngines); localIdx = 0; - FOR_EACH_IN_BITVECTOR(&engines, engineType) + FOR_EACH_IN_BITVECTOR(&engines, rmEngineType) { if (allocated == reqEngCount) break; // Skip engines that aren't in the shared pool already - if (!bitVectorTest(pSharedEngines, engineType)) + if (!bitVectorTest(pSharedEngines, rmEngineType)) { localIdx++; continue; @@ -386,21 +390,21 @@ kmigmgrAllocateInstanceEngines_IMPL bitVectorSetRange(&engines, engTypeRange); bitVectorAnd(&engines, &engines, pSourceEngines); localIdx = 0; - FOR_EACH_IN_BITVECTOR(&engines, engineType) + FOR_EACH_IN_BITVECTOR(&engines, rmEngineType) { if (allocated == reqEngCount) break; // Skip in-use engines - if (bitVectorTest(pSharedEngines, engineType) || - bitVectorTest(pExclusiveEngines, engineType)) + if (bitVectorTest(pSharedEngines, rmEngineType) || + bitVectorTest(pExclusiveEngines, rmEngineType)) { localIdx++; continue; } // Add the engine to the appropriate in-use pool - bitVectorSet((bShared ? pSharedEngines : pExclusiveEngines), engineType); + bitVectorSet((bShared ? pSharedEngines : pExclusiveEngines), rmEngineType); // Assign the engine bitVectorSet(pOutEngines, engTypeRange.lo + localIdx); @@ -431,44 +435,44 @@ kmigmgrGetLocalEngineMask_IMPL NvU32 count; bitVectorClrAll(pLocalEngineMask); - count = kmigmgrCountEnginesOfType(pPhysicalEngineMask, NV2080_ENGINE_TYPE_GR(0)); + count = kmigmgrCountEnginesOfType(pPhysicalEngineMask, RM_ENGINE_TYPE_GR(0)); if (count > 0) { - range = rangeMake(NV2080_ENGINE_TYPE_GR(0), NV2080_ENGINE_TYPE_GR(count - 1)); + range = rangeMake(RM_ENGINE_TYPE_GR(0), RM_ENGINE_TYPE_GR(count - 1)); bitVectorSetRange(pLocalEngineMask, range); } - count = kmigmgrCountEnginesOfType(pPhysicalEngineMask, NV2080_ENGINE_TYPE_COPY(0)); + count = kmigmgrCountEnginesOfType(pPhysicalEngineMask, RM_ENGINE_TYPE_COPY(0)); if (count > 0) { - range = rangeMake(NV2080_ENGINE_TYPE_COPY(0), NV2080_ENGINE_TYPE_COPY(count - 1)); + range = rangeMake(RM_ENGINE_TYPE_COPY(0), RM_ENGINE_TYPE_COPY(count - 1)); bitVectorSetRange(pLocalEngineMask, range); } - count = kmigmgrCountEnginesOfType(pPhysicalEngineMask, NV2080_ENGINE_TYPE_NVDEC(0)); + count = kmigmgrCountEnginesOfType(pPhysicalEngineMask, RM_ENGINE_TYPE_NVDEC(0)); if (count > 0) { - range = rangeMake(NV2080_ENGINE_TYPE_NVDEC(0), NV2080_ENGINE_TYPE_NVDEC(count - 1)); + range = rangeMake(RM_ENGINE_TYPE_NVDEC(0), RM_ENGINE_TYPE_NVDEC(count - 1)); bitVectorSetRange(pLocalEngineMask, range); } - count = kmigmgrCountEnginesOfType(pPhysicalEngineMask, NV2080_ENGINE_TYPE_NVENC(0)); + count = kmigmgrCountEnginesOfType(pPhysicalEngineMask, RM_ENGINE_TYPE_NVENC(0)); if (count > 0) { - range = rangeMake(NV2080_ENGINE_TYPE_NVENC(0), NV2080_ENGINE_TYPE_NVENC(count - 1)); + range = rangeMake(RM_ENGINE_TYPE_NVENC(0), RM_ENGINE_TYPE_NVENC(count - 1)); bitVectorSetRange(pLocalEngineMask, range); } - count = kmigmgrCountEnginesOfType(pPhysicalEngineMask, NV2080_ENGINE_TYPE_NVJPEG(0)); + count = kmigmgrCountEnginesOfType(pPhysicalEngineMask, RM_ENGINE_TYPE_NVJPEG(0)); if (count > 0) { - range = rangeMake(NV2080_ENGINE_TYPE_NVJPEG(0), NV2080_ENGINE_TYPE_NVJPEG(count - 1)); + range = rangeMake(RM_ENGINE_TYPE_NVJPEG(0), RM_ENGINE_TYPE_NVJPEG(count - 1)); bitVectorSetRange(pLocalEngineMask, range); } - count = kmigmgrCountEnginesOfType(pPhysicalEngineMask, NV2080_ENGINE_TYPE_OFA); + count = kmigmgrCountEnginesOfType(pPhysicalEngineMask, RM_ENGINE_TYPE_OFA); if (count > 0) - bitVectorSet(pLocalEngineMask, NV2080_ENGINE_TYPE_OFA); + bitVectorSet(pLocalEngineMask, RM_ENGINE_TYPE_OFA); } /*! @@ -606,8 +610,6 @@ kmigmgrDestruct_IMPL NvU32 GIIdx; NvU32 CIIdx; - portMemFree(pKernelMIGManager->pPrivate->staticInfo.pPartitionableEngines); - pKernelMIGManager->pPrivate->staticInfo.pPartitionableEngines = NULL; portMemFree(pKernelMIGManager->pPrivate->staticInfo.pProfiles); pKernelMIGManager->pPrivate->staticInfo.pProfiles = NULL; portMemFree(pKernelMIGManager->pPrivate->staticInfo.pSwizzIdFbMemPageRanges); @@ -696,18 +698,19 @@ _kmigmgrHandlePostSchedulingEnableCallback NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, memmgrSetPartitionableMem_HAL(pGpu, pMemoryManager)); - if (!IS_MIG_ENABLED(pGpu) && !IS_VIRTUAL(pGpu) && gpumgrIsSystemMIGEnabled(gpuGetDBDF(pGpu)) && - pGpu->getProperty(pGpu, PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED)) + if ((pKernelMIGManager == NULL) || !kmigmgrIsMIGSupported(pGpu, pKernelMIGManager)) + { + NV_PRINTF(LEVEL_INFO, "MIG not supported on this GPU.\n"); + return NV_ERR_NOT_SUPPORTED; + } + + if (!IS_MIG_ENABLED(pGpu) && !IS_VIRTUAL(pGpu) && + pGpu->getProperty(pGpu, PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED) && + (gpumgrIsSystemMIGEnabled(gpuGetDBDF(pGpu)) || pKernelMIGManager->bMIGAutoOnlineEnabled)) { RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS params; - if ((pKernelMIGManager == NULL) || !kmigmgrIsMIGSupported(pGpu, pKernelMIGManager)) - { - NV_PRINTF(LEVEL_INFO, "MIG not supported on this GPU.\n"); - return NV_ERR_NOT_SUPPORTED; - } - portMemSet(¶ms, 0x0, sizeof(params)); params.partitioningMode = NV2080_CTRL_GPU_SET_PARTITIONING_MODE_REPARTITIONING_FAST_RECONFIG; NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, @@ -954,13 +957,6 @@ kmigmgrIsMIGSupported_IMPL KernelMIGManager *pKernelMIGManager ) { - // MIG is not supported on platforms that support ATS over NVLink. - if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ATS_SUPPORTED)) - { - NV_ASSERT(!pGpu->getProperty(pGpu, PDB_PROP_GPU_MIG_SUPPORTED)); - return NV_FALSE; - } - return pGpu->getProperty(pGpu, PDB_PROP_GPU_MIG_SUPPORTED); } @@ -1066,6 +1062,8 @@ kmigmgrLoadStaticInfo_KERNEL KERNEL_MIG_MANAGER_PRIVATE_DATA *pPrivate = (KERNEL_MIG_MANAGER_PRIVATE_DATA *)pKernelMIGManager->pPrivate; RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); NV_STATUS status; + NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS params = {0}; + NvU32 nv2080EngineMask[NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX]; NV_ASSERT_OR_RETURN(pPrivate != NULL, NV_ERR_INVALID_STATE); @@ -1079,20 +1077,26 @@ kmigmgrLoadStaticInfo_KERNEL // pPrivate->bInitialized = NV_TRUE; - pPrivate->staticInfo.pPartitionableEngines = portMemAllocNonPaged(sizeof(*pPrivate->staticInfo.pPartitionableEngines)); - NV_CHECK_OR_ELSE(LEVEL_ERROR, - pPrivate->staticInfo.pPartitionableEngines != NULL, - status = NV_ERR_NO_MEMORY; - goto failed;); - portMemSet(pPrivate->staticInfo.pPartitionableEngines, 0x0, sizeof(*pPrivate->staticInfo.pPartitionableEngines)); + portMemSet(pPrivate->staticInfo.partitionableEngineMask, 0x0, sizeof(pPrivate->staticInfo.partitionableEngineMask)); NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES, - pPrivate->staticInfo.pPartitionableEngines, - sizeof(*pPrivate->staticInfo.pPartitionableEngines)), + ¶ms, + sizeof(params)), + failed); + + ct_assert(NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX == 2); + + nv2080EngineMask[0] = NvU64_LO32(params.engineMask); + nv2080EngineMask[1] = NvU64_HI32(params.engineMask); + + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + gpuGetRmEngineTypeCapMask(nv2080EngineMask, + NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX, + pPrivate->staticInfo.partitionableEngineMask), failed); pPrivate->staticInfo.pSkylineInfo = portMemAllocNonPaged(sizeof(*pPrivate->staticInfo.pSkylineInfo)); @@ -1111,6 +1115,22 @@ kmigmgrLoadStaticInfo_KERNEL sizeof(*pPrivate->staticInfo.pSkylineInfo)), failed); + pPrivate->staticInfo.pCIProfiles = portMemAllocNonPaged(sizeof(*pPrivate->staticInfo.pCIProfiles)); + NV_CHECK_OR_ELSE(LEVEL_ERROR, + pPrivate->staticInfo.pCIProfiles != NULL, + status = NV_ERR_NO_MEMORY; + goto failed;); + portMemSet(pPrivate->staticInfo.pCIProfiles, 0x0, sizeof(*pPrivate->staticInfo.pCIProfiles)); + + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES, + pPrivate->staticInfo.pCIProfiles, + sizeof(*pPrivate->staticInfo.pCIProfiles)), + failed); + pPrivate->staticInfo.pProfiles = portMemAllocNonPaged(sizeof(*pPrivate->staticInfo.pProfiles)); NV_CHECK_OR_ELSE(LEVEL_ERROR, pPrivate->staticInfo.pProfiles != NULL, @@ -1153,27 +1173,9 @@ kmigmgrLoadStaticInfo_KERNEL NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, status, failed); } - pPrivate->staticInfo.pCIProfiles = portMemAllocNonPaged(sizeof(*pPrivate->staticInfo.pCIProfiles)); - NV_CHECK_OR_ELSE(LEVEL_ERROR, - pPrivate->staticInfo.pCIProfiles != NULL, - status = NV_ERR_NO_MEMORY; - goto failed;); - portMemSet(pPrivate->staticInfo.pCIProfiles, 0x0, sizeof(*pPrivate->staticInfo.pCIProfiles)); - - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - pRmApi->Control(pRmApi, - pGpu->hInternalClient, - pGpu->hInternalSubdevice, - NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES, - pPrivate->staticInfo.pCIProfiles, - sizeof(*pPrivate->staticInfo.pCIProfiles)), - failed); - return status; failed: - portMemFree(pPrivate->staticInfo.pPartitionableEngines); - pPrivate->staticInfo.pPartitionableEngines = NULL; portMemFree(pPrivate->staticInfo.pProfiles); pPrivate->staticInfo.pProfiles = NULL; portMemFree(pPrivate->staticInfo.pSwizzIdFbMemPageRanges); @@ -1443,34 +1445,34 @@ kmigmgrIsEngineInUse_IMPL ( OBJGPU *pGpu, KernelMIGManager *pKernelMIGManager, - NvU32 engineType + RM_ENGINE_TYPE rmEngineType ) { - return bitVectorTest(&pKernelMIGManager->partitionableEnginesInUse, engineType); + return bitVectorTest(&pKernelMIGManager->partitionableEnginesInUse, rmEngineType); } /* - * @brief Determines whether NV2080_ENGINE_TYPE can be partitioned + * @brief Determines whether RM_ENGINE_TYPE can be partitioned */ NvBool kmigmgrIsEnginePartitionable_IMPL ( OBJGPU *pGpu, KernelMIGManager *pKernelMIGManager, - NvU32 engineType + RM_ENGINE_TYPE rmEngineType ) { return kmigmgrIsMIGSupported(pGpu, pKernelMIGManager) && - (NV2080_ENGINE_TYPE_IS_COPY(engineType) || - NV2080_ENGINE_TYPE_IS_GR(engineType) || - NV2080_ENGINE_TYPE_IS_NVDEC(engineType) || - NV2080_ENGINE_TYPE_IS_NVENC(engineType) || - NV2080_ENGINE_TYPE_IS_NVJPEG(engineType) || - (engineType == NV2080_ENGINE_TYPE_OFA)); + (RM_ENGINE_TYPE_IS_COPY(rmEngineType) || + RM_ENGINE_TYPE_IS_GR(rmEngineType) || + RM_ENGINE_TYPE_IS_NVDEC(rmEngineType) || + RM_ENGINE_TYPE_IS_NVENC(rmEngineType) || + RM_ENGINE_TYPE_IS_NVJPEG(rmEngineType) || + (rmEngineType == RM_ENGINE_TYPE_OFA)); } /*! - * @brief Function to determine whether global NV2080_ENGINE_TYPE belongs to given + * @brief Function to determine whether global RM_ENGINE_TYPE belongs to given * gpu/compute instance. * * @return NV_TRUE if this engine falls within the given instance. NV_FALSE @@ -1481,13 +1483,13 @@ kmigmgrIsEngineInInstance_IMPL ( OBJGPU *pGpu, KernelMIGManager *pKernelMIGManager, - NvU32 globalEngType, + RM_ENGINE_TYPE globalRmEngType, MIG_INSTANCE_REF ref ) { - NvU32 unused; + RM_ENGINE_TYPE unused; return kmigmgrGetGlobalToLocalEngineType(pGpu, pKernelMIGManager, ref, - globalEngType, + globalRmEngType, &unused) == NV_OK; } @@ -1500,7 +1502,7 @@ kmigmgrIsEngineInInstance_IMPL * @param[IN] pGpu * @param[IN] pKernerlMIGManager * @param[IN] engineCount Number of engines requested - * @param[IN] engineRange Range of acceptable NV2080_ENGINE_TYPE to allocate + * @param[IN] engineRange Range of acceptable RM_ENGINE_TYPE to allocate * @param[IN/OUT] pInstanceEngines Bitmask tracking engines owned by MIG instance */ NV_STATUS @@ -1517,10 +1519,9 @@ kmigmgrGetFreeEngines_IMPL ENGTYPE_BIT_VECTOR partitionableEngines; ENGTYPE_BIT_VECTOR availableEngines; NvU32 numAllocated; - NvU32 engineType; + RM_ENGINE_TYPE rmEngineType; NV_ASSERT_OR_RETURN(pStaticInfo != NULL, NV_ERR_INVALID_STATE); - NV_ASSERT_OR_RETURN(pStaticInfo->pPartitionableEngines != NULL, NV_ERR_INVALID_STATE); NV_ASSERT_OR_RETURN(!rangeIsEmpty(engineRange), NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN(pInstanceEngines != NULL, NV_ERR_INVALID_ARGUMENT); @@ -1530,8 +1531,8 @@ kmigmgrGetFreeEngines_IMPL } bitVectorFromRaw(&partitionableEngines, - &pStaticInfo->pPartitionableEngines->engineMask, - sizeof(pStaticInfo->pPartitionableEngines->engineMask)); + &pStaticInfo->partitionableEngineMask, + sizeof(pStaticInfo->partitionableEngineMask)); NV_ASSERT_OR_RETURN(!bitVectorTestAllCleared(&partitionableEngines), NV_ERR_INVALID_STATE); @@ -1547,12 +1548,12 @@ kmigmgrGetFreeEngines_IMPL } numAllocated = 0; - FOR_EACH_IN_BITVECTOR(&availableEngines, engineType) + FOR_EACH_IN_BITVECTOR(&availableEngines, rmEngineType) { if (numAllocated == engineCount) break; - bitVectorSet(pInstanceEngines, engineType); + bitVectorSet(pInstanceEngines, rmEngineType); numAllocated++; } FOR_EACH_IN_BITVECTOR_END(); @@ -1571,7 +1572,7 @@ kmigmgrTrimInstanceRunlistBufPools_IMPL KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance ) { - NvU32 engineType; + RM_ENGINE_TYPE rmEngineType; KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); if (!kmigmgrIsMemoryPartitioningNeeded_HAL(pGpu, pKernelMIGManager, pKernelMIGGpuInstance->swizzId)) @@ -1580,18 +1581,18 @@ kmigmgrTrimInstanceRunlistBufPools_IMPL if (!ctxBufPoolIsSupported(pGpu)) return; - for (engineType = 0; engineType < NV2080_ENGINE_TYPE_LAST; engineType++) + for (rmEngineType = 0; rmEngineType < RM_ENGINE_TYPE_LAST; rmEngineType++) { - if (!NV2080_ENGINE_TYPE_IS_VALID(engineType) || - !kmigmgrIsEnginePartitionable(pGpu, pKernelMIGManager, engineType) || - !kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, engineType, kmigmgrMakeGIReference(pKernelMIGGpuInstance))) + if (!RM_ENGINE_TYPE_IS_VALID(rmEngineType) || + !kmigmgrIsEnginePartitionable(pGpu, pKernelMIGManager, rmEngineType) || + !kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, rmEngineType, kmigmgrMakeGIReference(pKernelMIGGpuInstance))) { continue; } - if (kfifoGetRunlistBufPool(pGpu, pKernelFifo, engineType) != NULL) + if (kfifoGetRunlistBufPool(pGpu, pKernelFifo, rmEngineType) != NULL) { - ctxBufPoolTrim(kfifoGetRunlistBufPool(pGpu, pKernelFifo, engineType)); + ctxBufPoolTrim(kfifoGetRunlistBufPool(pGpu, pKernelFifo, rmEngineType)); } } } @@ -1611,7 +1612,7 @@ kmigmgrCreateGPUInstanceRunlists_FWCLIENT KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); NvU32 index; NvU32 runlistId; - NvU32 engineType; + RM_ENGINE_TYPE rmEngineType; NvU32 engDesc; NV_STATUS status = NV_OK; NvU32 numEngines = kfifoGetNumEngines_HAL(pGpu, pKernelFifo); @@ -1656,7 +1657,7 @@ kmigmgrCreateGPUInstanceRunlists_FWCLIENT NV_ASSERT_OK_OR_GOTO(status, kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, ENGINE_INFO_TYPE_RUNLIST, runlistId, - ENGINE_INFO_TYPE_NV2080, &engineType), + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, (NvU32 *)&rmEngineType), failed); NV_ASSERT_OK_OR_GOTO(status, @@ -1666,13 +1667,13 @@ kmigmgrCreateGPUInstanceRunlists_FWCLIENT failed); // Check if this is a partitionable engine. Non-partitionable engine runlists can stay in RM reserved memory - if (!kmigmgrIsEnginePartitionable(pGpu, pKernelMIGManager, engineType)) + if (!kmigmgrIsEnginePartitionable(pGpu, pKernelMIGManager, rmEngineType)) { continue; } // if partitionable engine doesn't belong to this GPU instance then nothing to do - if (!kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, engineType, kmigmgrMakeGIReference(pKernelMIGGpuInstance))) + if (!kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, rmEngineType, kmigmgrMakeGIReference(pKernelMIGGpuInstance))) { continue; } @@ -2108,6 +2109,8 @@ kmigmgrInitGPUInstanceInfo_IMPL pKernelMIGGpuInstance->pMIGGpuInstance = NULL; pKernelMIGGpuInstance->pOsRmCaps = NULL; pKernelMIGGpuInstance->pProfile = NULL; + + portMemSet(&pKernelMIGGpuInstance->resourceAllocation, 0x0, sizeof(pKernelMIGGpuInstance->resourceAllocation)); } /*! @@ -2183,7 +2186,7 @@ kmigmgrIsClientUsingDeviceProfiling_IMPL subdeviceGetByGpu(pRsClient, pGpu, &pSubdevice), return NV_FALSE; ); - NV_CHECK_OK_OR_ELSE(status, LEVEL_SILENT, + NV_CHECK_OK_OR_ELSE(status, LEVEL_ERROR, gisubscriptionGetGPUInstanceSubscription(pRsClient, RES_GET_HANDLE(pSubdevice), &pGPUInstanceSubscription), return NV_FALSE; ); @@ -2202,7 +2205,6 @@ kmigmgrEnableAllLCEs_IMPL ) { KernelCE *pKCe = NULL; - NvU32 i; // // AMODEL support of CEs is faked. No actual work needs to be done for @@ -2210,15 +2212,7 @@ kmigmgrEnableAllLCEs_IMPL // NV_CHECK_OR_RETURN(LEVEL_SILENT, !IsAMODEL(pGpu), NV_OK); - for (i = 0; i < ENG_CE__SIZE_1; ++i) - { - pKCe = GPU_GET_KCE(pGpu, i); - - if (pKCe != NULL) - break; - } - - NV_ASSERT_OR_RETURN(pKCe, NV_ERR_INSUFFICIENT_RESOURCES); + NV_ASSERT_OK_OR_RETURN(kceFindFirstInstance(pGpu, &pKCe)); if (bEnableAllLCEs) NV_ASSERT_OK_OR_RETURN(kceUpdateClassDB_HAL(pGpu, pKCe)); @@ -2260,7 +2254,7 @@ kmigmgrGetInstanceRefFromClient_IMPL NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, subdeviceGetByGpu(pRsClient, pGpu, &pSubdevice)); - NV_CHECK_OK_OR_RETURN(LEVEL_SILENT, + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, gisubscriptionGetGPUInstanceSubscription(pRsClient, RES_GET_HANDLE(pSubdevice), &pGPUInstanceSubscription)); @@ -2375,17 +2369,17 @@ kmigmgrPrintGPUInstanceInfo_IMPL NV_RANGE partitionableMemoryRange = memmgrGetMIGPartitionableMemoryRange(pGpu, pMemoryManager); NvU32 grCount = kmigmgrCountEnginesOfType(&pKernelMIGGpuInstance->resourceAllocation.engines, - NV2080_ENGINE_TYPE_GR(0)); + RM_ENGINE_TYPE_GR(0)); NvU32 ceCount = kmigmgrCountEnginesOfType(&pKernelMIGGpuInstance->resourceAllocation.engines, - NV2080_ENGINE_TYPE_COPY(0)); + RM_ENGINE_TYPE_COPY(0)); NvU32 decCount = kmigmgrCountEnginesOfType(&pKernelMIGGpuInstance->resourceAllocation.engines, - NV2080_ENGINE_TYPE_NVDEC(0)); + RM_ENGINE_TYPE_NVDEC(0)); NvU32 encCount = kmigmgrCountEnginesOfType(&pKernelMIGGpuInstance->resourceAllocation.engines, - NV2080_ENGINE_TYPE_NVENC(0)); + RM_ENGINE_TYPE_NVENC(0)); NvU32 jpgCount = kmigmgrCountEnginesOfType(&pKernelMIGGpuInstance->resourceAllocation.engines, - NV2080_ENGINE_TYPE_NVJPG); + RM_ENGINE_TYPE_NVJPG); NvU32 ofaCount = kmigmgrCountEnginesOfType(&pKernelMIGGpuInstance->resourceAllocation.engines, - NV2080_ENGINE_TYPE_OFA); + RM_ENGINE_TYPE_OFA); #define PADDING_STR "-----------------------------------------------------------------" @@ -2592,8 +2586,8 @@ kmigmgrGetGPUInstanceInfo_IMPL } /*! - * @brief Function to convert local NV2080_ENGINE_TYPE to global - * NV2080_ENGINE_TYPE for partitionable engines + * @brief Function to convert local RM_ENGINE_TYPE to global + * RM_ENGINE_TYPE for partitionable engines * Currently It support GR, CE, NVDEC, NVENC, NVJPG */ NV_STATUS @@ -2602,12 +2596,12 @@ kmigmgrGetLocalToGlobalEngineType_IMPL OBJGPU *pGpu, KernelMIGManager *pKernelMIGManager, MIG_INSTANCE_REF ref, - NvU32 localEngType, - NvU32 *pGlobalEngType + RM_ENGINE_TYPE localEngType, + RM_ENGINE_TYPE *pGlobalEngType ) { NV_ASSERT_OR_RETURN(kmigmgrIsMIGReferenceValid(&ref), NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(NV2080_ENGINE_TYPE_IS_VALID(localEngType), + NV_ASSERT_OR_RETURN(RM_ENGINE_TYPE_IS_VALID(localEngType), NV_ERR_INVALID_ARGUMENT); if (!kmigmgrIsEnginePartitionable(pGpu, pKernelMIGManager, localEngType)) @@ -2648,8 +2642,8 @@ kmigmgrGetLocalToGlobalEngineType_IMPL } /*! - * @brief Function to convert global NV2080_ENGINE_TYPE to local - * NV2080_ENGINE_TYPE for partitionable engines + * @brief Function to convert global RM_ENGINE_TYPE to local + * RM_ENGINE_TYPE for partitionable engines * Currently it supports GR, CE, NVDEC, NVENC, NVJPG */ NV_STATUS @@ -2658,19 +2652,19 @@ kmigmgrGetGlobalToLocalEngineType_IMPL OBJGPU *pGpu, KernelMIGManager *pKernelMIGManager, MIG_INSTANCE_REF ref, - NvU32 globalEngType, - NvU32 *pLocalEngType + RM_ENGINE_TYPE globalEngType, + RM_ENGINE_TYPE *pLocalEngType ) { NV_ASSERT_OR_RETURN(kmigmgrIsMIGReferenceValid(&ref), NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(NV2080_ENGINE_TYPE_IS_VALID(globalEngType), + NV_ASSERT_OR_RETURN(RM_ENGINE_TYPE_IS_VALID(globalEngType), NV_ERR_INVALID_ARGUMENT); if (!kmigmgrIsEnginePartitionable(pGpu, pKernelMIGManager, globalEngType)) { // // Return same engineId as global if called for non-partitioned - // 2080type engines like host engines, PMU SEC etc. + // rm engine types like host engines, PMU SEC etc. // *pLocalEngType = globalEngType; return NV_OK; @@ -2727,7 +2721,7 @@ kmigmgrFilterEngineList_IMPL OBJGPU *pGpu, KernelMIGManager *pKernelMIGManager, Subdevice *pSubdevice, - NvU32 *pEngineTypes, + RM_ENGINE_TYPE *pEngineTypes, NvU32 *pEngineCount ) { @@ -2744,17 +2738,17 @@ kmigmgrFilterEngineList_IMPL *pEngineCount = 0; for (i = 0; i < pGpu->engineDB.size; ++i) { - NvU32 engineType = pGpu->engineDB.pType[i]; - NvU32 newEngineType = engineType; + RM_ENGINE_TYPE rmEngineType = pGpu->engineDB.pType[i]; + RM_ENGINE_TYPE newEngineType = rmEngineType; NvBool bAddEngine = NV_TRUE; if (bMIGInUse) { - if (kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, engineType, ref)) + if (kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, rmEngineType, ref)) { // Override the engine type with the local engine idx NV_ASSERT_OK(kmigmgrGetGlobalToLocalEngineType(pGpu, pKernelMIGManager, ref, - engineType, + rmEngineType, &newEngineType)); } else @@ -2762,8 +2756,8 @@ kmigmgrFilterEngineList_IMPL bAddEngine = NV_FALSE; } } - else if (NV2080_ENGINE_TYPE_IS_GR(engineType) && - (0 != NV2080_ENGINE_TYPE_GR_IDX(engineType))) + else if (RM_ENGINE_TYPE_IS_GR(rmEngineType) && + (0 != RM_ENGINE_TYPE_GR_IDX(rmEngineType))) { bAddEngine = NV_FALSE; } @@ -2815,9 +2809,9 @@ kmigmgrFilterEnginePartnerList_IMPL for (i = 0; i < pPartnerListParams->numPartners; ++i) { - NvU32 engineType = pPartnerListParams->partnerList[i]; + RM_ENGINE_TYPE rmEngineType = pPartnerListParams->partnerList[i]; - if (!kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, engineType, ref)) + if (!kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, rmEngineType, ref)) { // Filter this entry from the partner list for (j = i; j < pPartnerListParams->numPartners - 1; ++j) @@ -2923,6 +2917,7 @@ kmigmgrSetPartitioningMode_IMPL { RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS params; + KernelCcu *pKccu = GPU_GET_KERNEL_CCU(pGpu); portMemSet(¶ms, 0x0, sizeof(params)); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, @@ -2963,6 +2958,10 @@ kmigmgrSetPartitioningMode_IMPL NV_ASSERT_OK_OR_RETURN(kmemsysPopulateMIGGPUInstanceMemConfig_HAL(pGpu, pKernelMemorySystem)); } + if (pKccu) + { + kccuMigShrBufHandler_HAL(pGpu, pKccu, pKernelMIGManager->bMIGEnabled); + } return NV_OK; } @@ -2975,7 +2974,7 @@ kmigmgrGetMIGReferenceFromEngineType_IMPL ( OBJGPU *pGpu, KernelMIGManager *pKernelMIGManager, - NvU32 engineType, + RM_ENGINE_TYPE rmEngineType, MIG_INSTANCE_REF *pRef ) { @@ -2995,17 +2994,17 @@ kmigmgrGetMIGReferenceFromEngineType_IMPL // if this happens to be an RM internal channel not bound to an engine, // attribute it to no instance // - if (!NV2080_ENGINE_TYPE_IS_VALID(engineType)) + if (!RM_ENGINE_TYPE_IS_VALID(rmEngineType)) return NV_ERR_INVALID_ARGUMENT; // Engine is not partitionable, attribute to no instance - if (!kmigmgrIsEnginePartitionable(pGpu, pKernelMIGManager, engineType)) + if (!kmigmgrIsEnginePartitionable(pGpu, pKernelMIGManager, rmEngineType)) return NV_ERR_INVALID_ARGUMENT; pKernelMIGGPUInstance = NULL; FOR_EACH_VALID_GPU_INSTANCE(pGpu, pKernelMIGManager, pKernelMIGGPUInstance) { - if (kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, engineType, + if (kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, rmEngineType, kmigmgrMakeGIReference(pKernelMIGGPUInstance))) { break; @@ -3029,7 +3028,7 @@ kmigmgrGetMIGReferenceFromEngineType_IMPL if (!pMIGComputeInstance->bValid) continue; - if (kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, engineType, + if (kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, rmEngineType, kmigmgrMakeCIReference(pKernelMIGGPUInstance, pMIGComputeInstance))) { break; @@ -3055,13 +3054,10 @@ kmigmgrDetectReducedConfig_KERNEL const KERNEL_MIG_MANAGER_STATIC_INFO *pStaticInfo = kmigmgrGetStaticInfo(pGpu, pKernelMIGManager); NvU32 i; - for (i = 0; i < pStaticInfo->pProfiles->count; ++i) + for (i = 0; i < pStaticInfo->pCIProfiles->profileCount; ++i) { - NvU32 computeSize = DRF_VAL(2080_CTRL_GPU, _PARTITION_FLAG, _COMPUTE_SIZE, - pStaticInfo->pProfiles->table[i].partitionFlag); - // Reduced config A100 does not support 1/8 compute size - if (computeSize == NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH) + if (pStaticInfo->pCIProfiles->profiles[i].computeSize == NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH) { return; } @@ -3094,13 +3090,13 @@ kmigmgrGetGPUInstanceScrubberCe_IMPL kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref)); bitVectorClrAll(&ces); - bitVectorSetRange(&ces, NV2080_ENGINE_RANGE_COPY()); + bitVectorSetRange(&ces, RM_ENGINE_RANGE_COPY()); bitVectorAnd(&ces, &ces, &ref.pKernelMIGGpuInstance->resourceAllocation.engines); NV_ASSERT_OR_RETURN(!bitVectorTestAllCleared(&ces), NV_ERR_INSUFFICIENT_RESOURCES); // Pick the first CE in the instance - *ceInst = NV2080_ENGINE_TYPE_COPY_IDX(bitVectorCountTrailingZeros(&ces)); + *ceInst = RM_ENGINE_TYPE_COPY_IDX(bitVectorCountTrailingZeros(&ces)); return NV_OK; } @@ -3228,6 +3224,9 @@ kmigmgrSaveComputeInstances_IMPL } pComputeInstanceSave->ciInfo.veidOffset = pMIGComputeInstance->resourceAllocation.veidOffset; pComputeInstanceSave->ciInfo.veidCount = pMIGComputeInstance->resourceAllocation.veidCount; + pComputeInstanceSave->ciInfo.smCount = pMIGComputeInstance->resourceAllocation.smCount; + pComputeInstanceSave->ciInfo.spanStart = pMIGComputeInstance->spanStart; + pComputeInstanceSave->ciInfo.computeSize = pMIGComputeInstance->computeSize; portMemCopy(pComputeInstanceSave->ciInfo.uuid, sizeof(pComputeInstanceSave->ciInfo.uuid), pMIGComputeInstance->uuid.uuid, sizeof(pMIGComputeInstance->uuid.uuid)); @@ -3299,6 +3298,9 @@ kmigmgrSwizzIdToResourceAllocation_IMPL pResourceAllocation->veidOffset = info.veidOffset; pResourceAllocation->virtualGpcCount = info.virtualGpcCount; + // Use profile SM count for filling the resource allocation + pResourceAllocation->smCount = pKernelMIGGpuInstance->pProfile->smCount; + bitVectorFromRaw(&pResourceAllocation->engines, info.enginesMask, sizeof(info.enginesMask)); // Cache the local engine mask for this instance @@ -3384,14 +3386,18 @@ kmigmgrCreateComputeInstances_VF NvU32 count; ENGTYPE_BIT_VECTOR shadowExclusiveEngMask; ENGTYPE_BIT_VECTOR shadowSharedEngMask; - MIG_COMPUTE_INSTANCE computeInstanceInfo[KMIGMGR_MAX_COMPUTE_INSTANCES]; + MIG_COMPUTE_INSTANCE *pComputeInstanceInfo; NvU32 CIIdx; NvU32 freeSlots; NvU32 createdInstances; NvU32 inUseGpcCount; NvU32 remainingGpcCount; NvU32 i; + NvU64 shadowCTSInUseMask; + NvU64 shadowVeidInUseMask; KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); + KMIGMGR_CONFIGURE_INSTANCE_REQUEST *pConfigRequestPerCi = NULL; + NvBool bIsCTSRequired = kmigmgrIsCTSAlignmentRequired_HAL(pGpu, pKernelMIGManager); NV_ASSERT_OR_RETURN(pKernelMIGGpuInstance != NULL, NV_ERR_INVALID_ARGUMENT); @@ -3401,7 +3407,17 @@ kmigmgrCreateComputeInstances_VF NV_CHECK_OR_RETURN(LEVEL_SILENT, count != 0, NV_ERR_INVALID_ARGUMENT); - portMemSet(computeInstanceInfo, 0, sizeof(computeInstanceInfo)); + pComputeInstanceInfo = portMemAllocNonPaged(sizeof(*pComputeInstanceInfo) * + KMIGMGR_MAX_COMPUTE_INSTANCES); + NV_CHECK_OR_RETURN(LEVEL_NOTICE, pComputeInstanceInfo != NULL, NV_ERR_NO_MEMORY); + + portMemSet(pComputeInstanceInfo, 0, sizeof(*pComputeInstanceInfo) * + KMIGMGR_MAX_COMPUTE_INSTANCES); + + pConfigRequestPerCi = portMemAllocStackOrHeap(sizeof(*pConfigRequestPerCi) * KMIGMGR_MAX_COMPUTE_INSTANCES); + NV_ASSERT_OR_ELSE(pConfigRequestPerCi != NULL, status = NV_ERR_NO_MEMORY; goto done;); + + portMemSet(pConfigRequestPerCi, 0, sizeof(*pConfigRequestPerCi) * KMIGMGR_MAX_COMPUTE_INSTANCES); // Check that there's enough open compute instance slots, and count used GPCs freeSlots = 0; @@ -3413,20 +3429,32 @@ kmigmgrCreateComputeInstances_VF MIG_COMPUTE_INSTANCE *pMIGComputeInstance = &pKernelMIGGpuInstance->MIGComputeInstance[CIIdx]; if (pMIGComputeInstance->bValid) - inUseGpcCount += pMIGComputeInstance->resourceAllocation.gpcCount; + { + NvU32 smCount = pMIGComputeInstance->resourceAllocation.smCount; + NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE ciProfile; + + NV_CHECK_OK_OR_ELSE(status, LEVEL_ERROR, + kmigmgrGetComputeProfileFromSmCount(pGpu, pKernelMIGManager, smCount, &ciProfile), + goto done; ); + + inUseGpcCount += ciProfile.gpcCount; + } else + { freeSlots++; + } } - NV_CHECK_OR_RETURN(LEVEL_SILENT, freeSlots >= count, NV_ERR_INSUFFICIENT_RESOURCES); + NV_CHECK_OR_ELSE(LEVEL_SILENT, freeSlots >= count, + status = NV_ERR_INSUFFICIENT_RESOURCES; goto done); // // Check that we have enough spare GPCs. We're going to reuse the GPU Instance // configuration logic later on to do the actual allocation, so for now just // check the count. // - NV_ASSERT_OR_RETURN(pKernelMIGGpuInstance->resourceAllocation.gpcCount >= inUseGpcCount, - NV_ERR_INVALID_STATE); - remainingGpcCount = pKernelMIGGpuInstance->resourceAllocation.gpcCount - inUseGpcCount; + NV_ASSERT_OR_ELSE(pKernelMIGGpuInstance->resourceAllocation.virtualGpcCount >= inUseGpcCount, + status = NV_ERR_INVALID_STATE; goto done); + remainingGpcCount = pKernelMIGGpuInstance->resourceAllocation.virtualGpcCount - inUseGpcCount; // // Cache local copies of the resource pools, we'll commit them later if we @@ -3434,20 +3462,24 @@ kmigmgrCreateComputeInstances_VF // bitVectorCopy(&shadowExclusiveEngMask, &pKernelMIGGpuInstance->exclusiveEngMask); bitVectorCopy(&shadowSharedEngMask, &pKernelMIGGpuInstance->sharedEngMask); + shadowCTSInUseMask = pKernelMIGGpuInstance->ctsIdsInUseMask; + shadowVeidInUseMask = pKernelGraphicsManager->veidInUseMask; for (CIIdx = 0; CIIdx < count; ++CIIdx) { - MIG_COMPUTE_INSTANCE *pMIGComputeInstance = &computeInstanceInfo[CIIdx]; + NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE *pCIProfile; + MIG_COMPUTE_INSTANCE *pMIGComputeInstance = &pComputeInstanceInfo[CIIdx]; MIG_RESOURCE_ALLOCATION *pResourceAllocation = &pMIGComputeInstance->resourceAllocation; + NvU32 smCount = + (params.type == KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS_TYPE_REQUEST) + ? params.inst.request.pReqComputeInstanceInfo[CIIdx].smCount + : params.inst.restore.pComputeInstanceSave->ciInfo.smCount; NvU32 gpcCount = - ((params.type == KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS_TYPE_REQUEST) || - (params.type == KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS_TYPE_REQUEST_WITH_IDS)) + (params.type == KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS_TYPE_REQUEST) ? params.inst.request.pReqComputeInstanceInfo[CIIdx].gpcCount : nvPopCount32(params.inst.restore.pComputeInstanceSave->ciInfo.gpcMask); - pMIGComputeInstance->bValid = NV_TRUE; pMIGComputeInstance->sharedEngFlag = - ((params.type == KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS_TYPE_REQUEST) || - (params.type == KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS_TYPE_REQUEST_WITH_IDS)) + (params.type == KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS_TYPE_REQUEST) ? params.inst.request.pReqComputeInstanceInfo[CIIdx].sharedEngFlag : params.inst.restore.pComputeInstanceSave->ciInfo.sharedEngFlags; NvU32 grCount; @@ -3456,19 +3488,111 @@ kmigmgrCreateComputeInstances_VF NvU32 encCount; NvU32 jpgCount; NvU32 ofaCount; + NvU32 spanStart; + NvU32 ctsId; - // Check to see if we have enough GPCs left to satisfy this request - if (remainingGpcCount < gpcCount) + if (params.type == KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS_TYPE_REQUEST) { - NV_PRINTF(LEVEL_ERROR, - "Not enough remaining GPCs (%d) for compute instance request (%d).\n", - remainingGpcCount, gpcCount); - return NV_ERR_INSUFFICIENT_RESOURCES; + spanStart = + (FLD_TEST_REF(NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_AT_SPAN, _TRUE, params.inst.request.requestFlags)) + ? params.inst.request.pReqComputeInstanceInfo[CIIdx].spanStart + : KMIGMGR_SPAN_OFFSET_INVALID; + } + else + { + spanStart = params.inst.restore.pComputeInstanceSave->ciInfo.spanStart; } - remainingGpcCount -= gpcCount; - if ((params.type == KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS_TYPE_REQUEST) || - (params.type == KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS_TYPE_REQUEST_WITH_IDS)) + pConfigRequestPerCi[CIIdx].veidSpanStart = spanStart; + pCIProfile = &pConfigRequestPerCi[CIIdx].profile; + ctsId = KMIGMGR_CTSID_INVALID; + if ((kmigmgrGetComputeProfileFromSmCount(pGpu, pKernelMIGManager, smCount, pCIProfile) == NV_OK) || + (kmigmgrGetComputeProfileFromGpcCount(pGpu, pKernelMIGManager, gpcCount, pCIProfile) == NV_OK)) + { + // CTS and Span allocation is done early to help prevent spurious requests + if (bIsCTSRequired) + { + if (spanStart != KMIGMGR_SPAN_OFFSET_INVALID) + { + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kmigmgrXlateSpanStartToCTSId(pGpu, pKernelMIGManager, + pCIProfile->computeSize, + spanStart, + &ctsId), + done); + + NV_CHECK_OR_ELSE(LEVEL_ERROR, + kmigmgrIsCTSIdAvailable(pGpu, pKernelMIGManager, + pKernelMIGGpuInstance->pProfile->validCTSIdMask, + shadowCTSInUseMask, + ctsId), + status = NV_ERR_STATE_IN_USE; goto done; ); + + shadowCTSInUseMask |= NVBIT64(ctsId); + } + else + { + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kmigmgrGetFreeCTSId(pGpu, pKernelMIGManager, + &ctsId, + pKernelMIGGpuInstance->pProfile->validCTSIdMask, + shadowCTSInUseMask, + pCIProfile->computeSize), + done); + } + + pConfigRequestPerCi[CIIdx].veidSpanStart = kmigmgrGetSpanStartFromCTSId(pGpu, pKernelMIGManager, ctsId); + shadowCTSInUseMask |= NVBIT64(ctsId); + } + } + else + { + NvU32 maxVeidsPerGpc; + + NV_ASSERT_OK_OR_GOTO(status, + kgrmgrGetMaxVeidsPerGpc(pGpu, pKernelGraphicsManager, &maxVeidsPerGpc), + done); + + // If no CI profile was available. Populate one with bare-necessities + pCIProfile->computeSize = KMIGMGR_COMPUTE_SIZE_INVALID; + pCIProfile->gpcCount = gpcCount; + pCIProfile->smCount = gpcCount * (pKernelMIGGpuInstance->pProfile->smCount / pKernelMIGGpuInstance->pProfile->gpcCount); + pCIProfile->veidCount = maxVeidsPerGpc * gpcCount; + + // Force non-profile requests to go through VEID allocator + pConfigRequestPerCi[CIIdx].veidSpanStart = KMIGMGR_SPAN_OFFSET_INVALID; + } + + pConfigRequestPerCi[CIIdx].ctsId = ctsId; + + // Perform VEID request checks or use the best fit allocator to find a slot + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kgrmgrCheckVeidsRequest(pGpu, pKernelGraphicsManager, + &shadowVeidInUseMask, + pCIProfile->veidCount, + &pConfigRequestPerCi[CIIdx].veidSpanStart, + pKernelMIGGpuInstance), + done); + + // Perform checks and VEID allocation + if (!bIsCTSRequired) + { + // + // Only perform explicit GPC checks if CTS alignment isn't required. A similar case + // is covered by CTS requirements. + // + if (remainingGpcCount < pCIProfile->gpcCount) + { + NV_PRINTF(LEVEL_ERROR, + "Not enough remaining GPCs (%d) for compute instance request (%d).\n", + remainingGpcCount, pCIProfile->gpcCount); + status = NV_ERR_INSUFFICIENT_RESOURCES; + goto done; + } + remainingGpcCount -= pCIProfile->gpcCount; + } + + if (params.type == KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS_TYPE_REQUEST) { grCount = 1; ceCount = params.inst.request.pReqComputeInstanceInfo[CIIdx].ceCount; @@ -3486,22 +3610,22 @@ kmigmgrCreateComputeInstances_VF sizeof(params.inst.restore.pComputeInstanceSave->ciInfo.enginesMask)); grCount = kmigmgrCountEnginesOfType(&engines, - NV2080_ENGINE_TYPE_GR(0)); + RM_ENGINE_TYPE_GR(0)); ceCount = kmigmgrCountEnginesOfType(&engines, - NV2080_ENGINE_TYPE_COPY(0)); + RM_ENGINE_TYPE_COPY(0)); decCount = kmigmgrCountEnginesOfType(&engines, - NV2080_ENGINE_TYPE_NVDEC(0)); + RM_ENGINE_TYPE_NVDEC(0)); encCount = kmigmgrCountEnginesOfType(&engines, - NV2080_ENGINE_TYPE_NVENC(0)); + RM_ENGINE_TYPE_NVENC(0)); jpgCount = kmigmgrCountEnginesOfType(&engines, - NV2080_ENGINE_TYPE_NVJPEG(0)); + RM_ENGINE_TYPE_NVJPEG(0)); ofaCount = kmigmgrCountEnginesOfType(&engines, - NV2080_ENGINE_TYPE_OFA); + RM_ENGINE_TYPE_OFA); NV_ASSERT(grCount == 1); } @@ -3509,70 +3633,70 @@ kmigmgrCreateComputeInstances_VF bitVectorClrAll(&pResourceAllocation->engines); // Allocate the GR engines for this compute instance - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, kmigmgrAllocateInstanceEngines(&pKernelMIGGpuInstance->resourceAllocation.engines, ((pMIGComputeInstance->sharedEngFlag & NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NONE) != 0x0), - NV2080_ENGINE_RANGE_GR(), + RM_ENGINE_RANGE_GR(), grCount, &pResourceAllocation->engines, &shadowExclusiveEngMask, - &shadowSharedEngMask)); + &shadowSharedEngMask), done); // Allocate the Copy engines for this compute instance - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, kmigmgrAllocateInstanceEngines(&pKernelMIGGpuInstance->resourceAllocation.engines, ((pMIGComputeInstance->sharedEngFlag & NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_CE) != 0x0), - NV2080_ENGINE_RANGE_COPY(), + RM_ENGINE_RANGE_COPY(), ceCount, &pResourceAllocation->engines, &shadowExclusiveEngMask, - &shadowSharedEngMask)); + &shadowSharedEngMask), done); // Allocate the NVDEC engines for this compute instance - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, kmigmgrAllocateInstanceEngines(&pKernelMIGGpuInstance->resourceAllocation.engines, ((pMIGComputeInstance->sharedEngFlag & NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NVDEC) != 0x0), - NV2080_ENGINE_RANGE_NVDEC(), + RM_ENGINE_RANGE_NVDEC(), decCount, &pResourceAllocation->engines, &shadowExclusiveEngMask, - &shadowSharedEngMask)); + &shadowSharedEngMask), done); // Allocate the NVENC engines for this compute instance - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, kmigmgrAllocateInstanceEngines(&pKernelMIGGpuInstance->resourceAllocation.engines, ((pMIGComputeInstance->sharedEngFlag & NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NVENC) != 0x0), - NV2080_ENGINE_RANGE_NVENC(), + RM_ENGINE_RANGE_NVENC(), encCount, &pResourceAllocation->engines, &shadowExclusiveEngMask, - &shadowSharedEngMask)); + &shadowSharedEngMask), done); // Allocate the NVJPG engines for this compute instance - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, kmigmgrAllocateInstanceEngines(&pKernelMIGGpuInstance->resourceAllocation.engines, ((pMIGComputeInstance->sharedEngFlag & NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NVJPG) != 0x0), - NV2080_ENGINE_RANGE_NVJPEG(), + RM_ENGINE_RANGE_NVJPEG(), jpgCount, &pResourceAllocation->engines, &shadowExclusiveEngMask, - &shadowSharedEngMask)); + &shadowSharedEngMask), done); // Allocate the NVOFA engines for this compute instance - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, kmigmgrAllocateInstanceEngines(&pKernelMIGGpuInstance->resourceAllocation.engines, ((pMIGComputeInstance->sharedEngFlag & NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_OFA) != 0x0), - rangeMake(NV2080_ENGINE_TYPE_OFA, NV2080_ENGINE_TYPE_OFA), + rangeMake(RM_ENGINE_TYPE_OFA, RM_ENGINE_TYPE_OFA), ofaCount, &pResourceAllocation->engines, &shadowExclusiveEngMask, - &shadowSharedEngMask)); + &shadowSharedEngMask), done); // Cache local mask of engine IDs for this compute instance @@ -3584,22 +3708,16 @@ kmigmgrCreateComputeInstances_VF if (!bQuery) { NvU32 swizzId = pKernelMIGGpuInstance->swizzId; - NvU32 gpcCountPerGr[8]; NvU32 updateEngMask; // Populate configure GPU instance parameters with compute instance info updateEngMask = 0x0; - portMemSet(gpcCountPerGr, 0, sizeof(gpcCountPerGr)); + for (CIIdx = 0; CIIdx < count; ++CIIdx) { - MIG_COMPUTE_INSTANCE *pMIGComputeInstance = &computeInstanceInfo[CIIdx]; + MIG_COMPUTE_INSTANCE *pMIGComputeInstance = &pComputeInstanceInfo[CIIdx]; MIG_RESOURCE_ALLOCATION *pComputeResourceAllocation = &pMIGComputeInstance->resourceAllocation; - NvU32 localEngineType; - NvU32 gpcCount = - ((params.type == KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS_TYPE_REQUEST) || - (params.type == KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS_TYPE_REQUEST_WITH_IDS)) - ? params.inst.request.pReqComputeInstanceInfo[CIIdx].gpcCount - : nvPopCount32(params.inst.restore.pComputeInstanceSave->ciInfo.gpcMask); + RM_ENGINE_TYPE localEngineType; // // Xlate from CI-local GR 0 to GI-local GR idx @@ -3607,28 +3725,27 @@ kmigmgrCreateComputeInstances_VF // compute instances aren't committed yet // NV_ASSERT_OK( - kmigmgrEngineTypeXlate(&pComputeResourceAllocation->localEngines, NV2080_ENGINE_TYPE_GR(0), + kmigmgrEngineTypeXlate(&pComputeResourceAllocation->localEngines, RM_ENGINE_TYPE_GR(0), &pComputeResourceAllocation->engines, &localEngineType)); - updateEngMask |= NVBIT32(NV2080_ENGINE_TYPE_GR_IDX(localEngineType)); - gpcCountPerGr[NV2080_ENGINE_TYPE_GR_IDX(localEngineType)] = gpcCount; + updateEngMask |= NVBIT32(RM_ENGINE_TYPE_GR_IDX(localEngineType)); } // Configure the GR engines for each compute instance status = kmigmgrConfigureGPUInstance(pGpu, pKernelMIGManager, swizzId, - gpcCountPerGr, + pConfigRequestPerCi, updateEngMask); // Do our best to deconfigure the engines we configured so far, then bail if (status != NV_OK) { - portMemSet(gpcCountPerGr, 0, sizeof(gpcCountPerGr)); + portMemSet(pConfigRequestPerCi, 0x0, sizeof(*pConfigRequestPerCi) * KMIGMGR_MAX_COMPUTE_INSTANCES); // Quash status. This is best-effort cleanup (void)kmigmgrConfigureGPUInstance(pGpu, pKernelMIGManager, swizzId, - gpcCountPerGr, + pConfigRequestPerCi, updateEngMask); - return status; + goto done; } // Update the GI pools with the result of this allocation @@ -3639,10 +3756,10 @@ kmigmgrCreateComputeInstances_VF for (CIIdx = 0; CIIdx < count; ++CIIdx) { MIG_RESOURCE_ALLOCATION *pResourceAllocation = &pKernelMIGGpuInstance->resourceAllocation; - MIG_COMPUTE_INSTANCE *pMIGComputeInstance = &computeInstanceInfo[CIIdx]; + MIG_COMPUTE_INSTANCE *pMIGComputeInstance = &pComputeInstanceInfo[CIIdx]; MIG_RESOURCE_ALLOCATION *pComputeResourceAllocation = &pMIGComputeInstance->resourceAllocation; - NvU32 gpcCount; - NvU32 globalEngineType; + NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE *pCIProfile; + RM_ENGINE_TYPE globalEngineType; NvU32 globalGrIdx; // @@ -3651,23 +3768,33 @@ kmigmgrCreateComputeInstances_VF // compute instances aren't committed yet // NV_ASSERT_OK( - kmigmgrEngineTypeXlate(&pComputeResourceAllocation->localEngines, NV2080_ENGINE_TYPE_GR(0), + kmigmgrEngineTypeXlate(&pComputeResourceAllocation->localEngines, RM_ENGINE_TYPE_GR(0), &pComputeResourceAllocation->engines, &globalEngineType)); - gpcCount = gpcCountPerGr[NV2080_ENGINE_TYPE_GR_IDX(globalEngineType)]; - NV_ASSERT_OK( kmigmgrEngineTypeXlate(&pResourceAllocation->localEngines, globalEngineType, &pResourceAllocation->engines, &globalEngineType)); - globalGrIdx = NV2080_ENGINE_TYPE_GR_IDX(globalEngineType); + globalGrIdx = RM_ENGINE_TYPE_GR_IDX(globalEngineType); + pCIProfile = &pConfigRequestPerCi[CIIdx].profile; - pComputeResourceAllocation->gpcCount = gpcCount; + pComputeResourceAllocation->gpcCount = pCIProfile->gpcCount; + pComputeResourceAllocation->smCount = pCIProfile->smCount; + if (pCIProfile->computeSize != KMIGMGR_COMPUTE_SIZE_INVALID) + { + pComputeResourceAllocation->veidCount = pCIProfile->veidCount; + } + else + { + pComputeResourceAllocation->veidCount = (pResourceAllocation->veidCount / pResourceAllocation->gpcCount) * + pComputeResourceAllocation->virtualGpcCount; + } + + pMIGComputeInstance->spanStart = pConfigRequestPerCi[CIIdx].veidSpanStart; + pMIGComputeInstance->computeSize = pConfigRequestPerCi[CIIdx].profile.computeSize; kgrmgrGetVeidBaseForGrIdx(pGpu, pKernelGraphicsManager, globalGrIdx, &pComputeResourceAllocation->veidOffset); pComputeResourceAllocation->veidOffset = pComputeResourceAllocation->veidOffset - pResourceAllocation->veidOffset; - - pComputeResourceAllocation->veidCount = nvPopCount64(pKernelGraphicsManager->grIdxVeidMask[globalGrIdx]); } // Copy over the local cached compute instance info @@ -3685,7 +3812,7 @@ kmigmgrCreateComputeInstances_VF continue; } - if ((params.type == KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS_TYPE_REQUEST_WITH_IDS) && + if (FLD_TEST_REF(NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_WITH_PART_ID, _TRUE, params.inst.request.requestFlags) && (pCIIDs[0] != CIIdx)) { continue; @@ -3696,7 +3823,7 @@ kmigmgrCreateComputeInstances_VF portMemCopy(&pKernelMIGGpuInstance->MIGComputeInstance[CIIdx], sizeof(pKernelMIGGpuInstance->MIGComputeInstance[CIIdx]), - &computeInstanceInfo[createdInstances], + &pComputeInstanceInfo[createdInstances], sizeof(pKernelMIGGpuInstance->MIGComputeInstance[CIIdx])); pKernelMIGGpuInstance->MIGComputeInstance[CIIdx].id = CIIdx; @@ -3712,7 +3839,7 @@ kmigmgrCreateComputeInstances_VF MIG_RESOURCE_ALLOCATION *pResourceAllocation; MIG_RESOURCE_ALLOCATION *pComputeResourceAllocation; MIG_COMPUTE_INSTANCE *pMIGComputeInstance; - NvU32 globalEngineType; + RM_ENGINE_TYPE globalEngineType; NvU32 globalGrIdx; // @@ -3727,12 +3854,12 @@ kmigmgrCreateComputeInstances_VF pComputeResourceAllocation = &pMIGComputeInstance->resourceAllocation; NV_ASSERT_OK( - kmigmgrEngineTypeXlate(&pComputeResourceAllocation->localEngines, NV2080_ENGINE_TYPE_GR(0), + kmigmgrEngineTypeXlate(&pComputeResourceAllocation->localEngines, RM_ENGINE_TYPE_GR(0), &pComputeResourceAllocation->engines, &globalEngineType)); NV_ASSERT_OK( kmigmgrEngineTypeXlate(&pResourceAllocation->localEngines, globalEngineType, &pResourceAllocation->engines, &globalEngineType)); - globalGrIdx = NV2080_ENGINE_TYPE_GR_IDX(globalEngineType); + globalGrIdx = RM_ENGINE_TYPE_GR_IDX(globalEngineType); NV_ASSERT(pMIGComputeInstance->id == CIIdx); @@ -3783,7 +3910,8 @@ kmigmgrCreateComputeInstances_VF } } - return NV_OK; + status = NV_OK; + goto done; cleanup_created_instances: for (i = 0; i < createdInstances; ++i) @@ -3792,6 +3920,10 @@ cleanup_created_instances: pCIIDs[i], NV_FALSE); } +done: + portMemFree(pComputeInstanceInfo); + portMemFreeStackOrHeap(pConfigRequestPerCi); + return status; } @@ -3818,6 +3950,7 @@ kmigmgrCreateComputeInstances_FWCLIENT NvBool bCreateCap ) { + KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); NV_STATUS status = NV_OK; KernelGraphics *pKernelGraphics; MIG_COMPUTE_INSTANCE *pMIGComputeInstance; @@ -3826,27 +3959,64 @@ kmigmgrCreateComputeInstances_FWCLIENT NVC637_CTRL_EXEC_PARTITIONS_EXPORTED_INFO info; NvU32 CIIdx = pCIIDs[0]; NvU32 tempGpcMask; - NvU32 gpcCountPerGr[8]; - NvU32 localEngineType; - NvU32 globalEngineType; + KMIGMGR_CONFIGURE_INSTANCE_REQUEST *pConfigRequestPerCi; + RM_ENGINE_TYPE localEngineType; + RM_ENGINE_TYPE globalEngineType; NvU32 globalGrIdx; + NvU32 maxVeidsPerGpc; + NvU64 shadowVeidInUseMask; NV_ASSERT_OR_RETURN(pKernelMIGGpuInstance != NULL, NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN(params.type == KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS_TYPE_RESTORE, NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN(params.inst.restore.pComputeInstanceSave != NULL, NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN(params.inst.restore.pComputeInstanceSave->bValid, NV_ERR_INVALID_ARGUMENT); + // CPU-RM will always restore the CI state created by GSP-RM, so will always be commit operation NV_ASSERT_OR_RETURN(!bQuery, NV_ERR_INVALID_ARGUMENT); + pMIGComputeInstance = portMemAllocNonPaged(sizeof(*pMIGComputeInstance)); + NV_CHECK_OR_RETURN(LEVEL_NOTICE, pMIGComputeInstance != NULL, NV_ERR_NO_MEMORY); + + portMemSet(pMIGComputeInstance, 0, sizeof(*pMIGComputeInstance)); + pResourceAllocation = &pKernelMIGGpuInstance->resourceAllocation; - pMIGComputeInstance = &pKernelMIGGpuInstance->MIGComputeInstance[CIIdx]; pComputeResourceAllocation = &pMIGComputeInstance->resourceAllocation; NV_ASSERT_OR_RETURN(!pMIGComputeInstance->bValid, NV_ERR_INVALID_STATE); - NV_ASSERT(pMIGComputeInstance->id == KMIGMGR_COMPUTE_INSTANCE_ID_INVALID); + + pConfigRequestPerCi = portMemAllocStackOrHeap(sizeof(*pConfigRequestPerCi) * KMIGMGR_MAX_COMPUTE_INSTANCES); + NV_ASSERT_OR_RETURN(pConfigRequestPerCi != NULL, NV_ERR_NO_MEMORY); + + portMemSet(pConfigRequestPerCi, 0x0, sizeof(*pConfigRequestPerCi) * KMIGMGR_MAX_COMPUTE_INSTANCES); + + NV_ASSERT_OK_OR_GOTO(status, + kgrmgrGetMaxVeidsPerGpc(pGpu, GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu), &maxVeidsPerGpc), + done); info = params.inst.restore.pComputeInstanceSave->ciInfo; + if (kmigmgrIsCTSAlignmentRequired_HAL(pGpu, pKernelMIGManager)) + { + + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kmigmgrXlateSpanStartToCTSId(pGpu, pKernelMIGManager, + info.computeSize, + info.spanStart, + &pConfigRequestPerCi[0].ctsId), + done); + + NV_CHECK_OR_ELSE(LEVEL_ERROR, + kmigmgrIsCTSIdAvailable(pGpu, pKernelMIGManager, + pKernelMIGGpuInstance->pProfile->validCTSIdMask, + pKernelMIGGpuInstance->ctsIdsInUseMask, + pConfigRequestPerCi[0].ctsId), + status = NV_ERR_STATE_IN_USE; goto done; ); + } + else + { + pConfigRequestPerCi[0].ctsId = KMIGMGR_CTSID_INVALID; + } + portMemCopy(pMIGComputeInstance->uuid.uuid, sizeof(pMIGComputeInstance->uuid.uuid), info.uuid, sizeof(info.uuid)); pMIGComputeInstance->sharedEngFlag = info.sharedEngFlags; @@ -3862,6 +4032,8 @@ kmigmgrCreateComputeInstances_FWCLIENT pComputeResourceAllocation->veidCount = info.veidCount; pComputeResourceAllocation->veidOffset = info.veidOffset; + pComputeResourceAllocation->smCount = info.smCount; + pMIGComputeInstance->computeSize = info.computeSize; bitVectorFromRaw(&pComputeResourceAllocation->engines, info.enginesMask, sizeof(info.enginesMask)); @@ -3872,7 +4044,6 @@ kmigmgrCreateComputeInstances_FWCLIENT pMIGComputeInstance->id = CIIdx; // Populate configure GPU instance parameters with compute instance info - portMemSet(gpcCountPerGr, 0, sizeof(gpcCountPerGr)); // // Xlate from CI-local GR 0 to GI-local GR idx @@ -3880,28 +4051,51 @@ kmigmgrCreateComputeInstances_FWCLIENT // compute instances aren't committed yet // NV_ASSERT_OK( - kmigmgrEngineTypeXlate(&pComputeResourceAllocation->localEngines, NV2080_ENGINE_TYPE_GR(0), + kmigmgrEngineTypeXlate(&pComputeResourceAllocation->localEngines, RM_ENGINE_TYPE_GR(0), &pComputeResourceAllocation->engines, &localEngineType)); - gpcCountPerGr[NV2080_ENGINE_TYPE_GR_IDX(localEngineType)] = pComputeResourceAllocation->gpcCount; + // Create a pseduo-profile based upon info retrieved from GSP-RM + pConfigRequestPerCi[0].profile.computeSize = info.computeSize; + pConfigRequestPerCi[0].profile.smCount = pComputeResourceAllocation->smCount; + pConfigRequestPerCi[0].profile.gpcCount = pComputeResourceAllocation->gpcCount; + pConfigRequestPerCi[0].profile.veidCount = pComputeResourceAllocation->veidCount; + pConfigRequestPerCi[0].veidSpanStart = info.spanStart; + + shadowVeidInUseMask = pKernelGraphicsManager->veidInUseMask; + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kgrmgrCheckVeidsRequest(pGpu, pKernelGraphicsManager, + &shadowVeidInUseMask, + pConfigRequestPerCi[0].profile.veidCount, + &pConfigRequestPerCi[0].veidSpanStart, + pKernelMIGGpuInstance), + done); // Configure the GR engines for each compute instance status = kmigmgrConfigureGPUInstance(pGpu, pKernelMIGManager, pKernelMIGGpuInstance->swizzId, - gpcCountPerGr, - NVBIT32(NV2080_ENGINE_TYPE_GR_IDX(localEngineType))); + pConfigRequestPerCi, + NVBIT32(RM_ENGINE_TYPE_GR_IDX(localEngineType))); // Do our best to deconfigure the engines we configured so far, then bail if (status != NV_OK) { - portMemSet(gpcCountPerGr, 0, sizeof(gpcCountPerGr)); + portMemSet(pConfigRequestPerCi, 0x0, sizeof(*pConfigRequestPerCi) * KMIGMGR_MAX_COMPUTE_INSTANCES); // Quash status. This is best-effort cleanup (void)kmigmgrConfigureGPUInstance(pGpu, pKernelMIGManager, pKernelMIGGpuInstance->swizzId, - gpcCountPerGr, - NVBIT32(NV2080_ENGINE_TYPE_GR_IDX(localEngineType))); + pConfigRequestPerCi, + NVBIT32(RM_ENGINE_TYPE_GR_IDX(localEngineType))); - return status; + goto done; } + NV_ASSERT(pKernelMIGGpuInstance->MIGComputeInstance[CIIdx].id == KMIGMGR_COMPUTE_INSTANCE_ID_INVALID); + + pMIGComputeInstance->spanStart = pConfigRequestPerCi[0].veidSpanStart; + + portMemCopy(&pKernelMIGGpuInstance->MIGComputeInstance[CIIdx], + sizeof(pKernelMIGGpuInstance->MIGComputeInstance[CIIdx]), + pMIGComputeInstance, + sizeof(*pMIGComputeInstance)); + // // Register instance with the capability framework only if it explicitly // requested. Otherwise, we rely on the persistent state. @@ -3911,47 +4105,53 @@ kmigmgrCreateComputeInstances_FWCLIENT // Register compute instance with the capability framework NV_ASSERT_OK_OR_GOTO(status, osRmCapRegisterSmcExecutionPartition(pKernelMIGGpuInstance->pOsRmCaps, - &pMIGComputeInstance->pOsRmCaps, - pMIGComputeInstance->id), + &pKernelMIGGpuInstance->MIGComputeInstance[CIIdx].pOsRmCaps, + pKernelMIGGpuInstance->MIGComputeInstance[CIIdx].id), cleanup_created_instances); } // Allocate RsShared for the instance NV_ASSERT_OK_OR_GOTO(status, serverAllocShare(&g_resServ, classInfo(RsShared), - &pMIGComputeInstance->pShare), + &pKernelMIGGpuInstance->MIGComputeInstance[CIIdx].pShare), cleanup_created_instances); // Allocate subscribed handles for this instance - NV_ASSERT_OK_OR_GOTO(status, - kmigmgrAllocComputeInstanceHandles(pGpu, pKernelMIGManager, pKernelMIGGpuInstance, pMIGComputeInstance), + if (!IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + { + NV_ASSERT_OK_OR_GOTO(status, + kmigmgrAllocComputeInstanceHandles(pGpu, pKernelMIGManager, pKernelMIGGpuInstance, &pKernelMIGGpuInstance->MIGComputeInstance[CIIdx]), cleanup_created_instances); - NV_ASSERT_OK( - kmigmgrEngineTypeXlate(&pComputeResourceAllocation->localEngines, NV2080_ENGINE_TYPE_GR(0), - &pComputeResourceAllocation->engines, &globalEngineType)); - NV_ASSERT_OK( - kmigmgrEngineTypeXlate(&pResourceAllocation->localEngines, globalEngineType, - &pResourceAllocation->engines, &globalEngineType)); - globalGrIdx = NV2080_ENGINE_TYPE_GR_IDX(globalEngineType); + NV_ASSERT_OK( + kmigmgrEngineTypeXlate(&pComputeResourceAllocation->localEngines, RM_ENGINE_TYPE_GR(0), + &pComputeResourceAllocation->engines, &globalEngineType)); + NV_ASSERT_OK( + kmigmgrEngineTypeXlate(&pResourceAllocation->localEngines, globalEngineType, + &pResourceAllocation->engines, &globalEngineType)); + globalGrIdx = RM_ENGINE_TYPE_GR_IDX(globalEngineType); - pKernelGraphics = GPU_GET_KERNEL_GRAPHICS(pGpu, globalGrIdx); - fecsSetRoutingInfo(pGpu, - pKernelGraphics, - pMIGComputeInstance->instanceHandles.hClient, - pMIGComputeInstance->instanceHandles.hSubdevice, - 0); + pKernelGraphics = GPU_GET_KERNEL_GRAPHICS(pGpu, globalGrIdx); + fecsSetRoutingInfo(pGpu, + pKernelGraphics, + pKernelMIGGpuInstance->MIGComputeInstance[CIIdx].instanceHandles.hClient, + pKernelMIGGpuInstance->MIGComputeInstance[CIIdx].instanceHandles.hSubdevice, + 0); - NV_ASSERT_OK_OR_GOTO(status, - kgraphicsCreateGoldenImageChannel(pGpu, pKernelGraphics), - cleanup_created_instances); + NV_ASSERT_OK_OR_GOTO(status, + kgraphicsCreateGoldenImageChannel(pGpu, pKernelGraphics), + cleanup_created_instances); + } - return NV_OK; + status = NV_OK; + goto done; cleanup_created_instances: (void)kmigmgrDeleteComputeInstance(pGpu, pKernelMIGManager, pKernelMIGGpuInstance, CIIdx, NV_FALSE); - +done: + portMemFreeStackOrHeap(pConfigRequestPerCi); + portMemFree(pMIGComputeInstance); return status; } @@ -3989,8 +4189,8 @@ kmigmgrReleaseComputeInstanceEngines_IMPL MIG_COMPUTE_INSTANCE *pMIGComputeInstance ) { - NvU32 globalEngineType; - NvU32 localEngineType; + RM_ENGINE_TYPE globalEngineType; + RM_ENGINE_TYPE localEngineType; ENGTYPE_BIT_VECTOR *pGlobalMask; ENGTYPE_BIT_VECTOR *pLocalMask; @@ -4068,8 +4268,9 @@ kmigmgrDeleteComputeInstance_IMPL MIG_RESOURCE_ALLOCATION *pComputeResourceAllocation; ENGTYPE_BIT_VECTOR grEngines; NvU32 swizzId; - NvU32 gpcCountPerGr[KGRMGR_MAX_GPC]; + KMIGMGR_CONFIGURE_INSTANCE_REQUEST *pConfigRequestPerCi; NvU32 updateEngMask; + NV_STATUS status = NV_OK; NV_ASSERT_OR_RETURN(pKernelMIGGpuInstance != NULL, NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN(CIID < NV_ARRAY_ELEMENTS(pKernelMIGGpuInstance->MIGComputeInstance), @@ -4111,32 +4312,38 @@ kmigmgrDeleteComputeInstance_IMPL // Deconfigure the GR engine for this compute instance swizzId = pKernelMIGGpuInstance->swizzId; - portMemSet(gpcCountPerGr, 0, sizeof(gpcCountPerGr)); + + pConfigRequestPerCi = portMemAllocStackOrHeap(sizeof(*pConfigRequestPerCi) * KMIGMGR_MAX_COMPUTE_INSTANCES); + NV_ASSERT_OR_RETURN(pConfigRequestPerCi != NULL, NV_ERR_NO_MEMORY); + + portMemSet(pConfigRequestPerCi, 0x0, sizeof(*pConfigRequestPerCi) * KMIGMGR_MAX_COMPUTE_INSTANCES); bitVectorClrAll(&grEngines); - bitVectorSetRange(&grEngines, NV2080_ENGINE_RANGE_GR()); + bitVectorSetRange(&grEngines, RM_ENGINE_RANGE_GR()); bitVectorAnd(&grEngines, &grEngines, &pComputeResourceAllocation->engines); - NV_ASSERT_OR_RETURN(!bitVectorTestAllCleared(&grEngines), NV_ERR_INVALID_STATE); - updateEngMask = NVBIT32(NV2080_ENGINE_TYPE_GR_IDX(bitVectorCountTrailingZeros(&grEngines))); - NV_ASSERT_OK_OR_RETURN( - kmigmgrConfigureGPUInstance(pGpu, pKernelMIGManager, swizzId, gpcCountPerGr, updateEngMask)); + NV_ASSERT_OR_ELSE(!bitVectorTestAllCleared(&grEngines), status = NV_ERR_INVALID_STATE; goto done;); + updateEngMask = NVBIT32(RM_ENGINE_TYPE_GR_IDX(bitVectorCountTrailingZeros(&grEngines))); + NV_ASSERT_OK_OR_GOTO(status, + kmigmgrConfigureGPUInstance(pGpu, pKernelMIGManager, swizzId, pConfigRequestPerCi, updateEngMask), + done); { - NvU32 globalEngType; + RM_ENGINE_TYPE globalRmEngType; MIG_INSTANCE_REF ref = kmigmgrMakeCIReference(pKernelMIGGpuInstance, pMIGComputeInstance); - NV_ASSERT_OK_OR_RETURN( + NV_ASSERT_OK_OR_GOTO(status, kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, - NV2080_ENGINE_TYPE_GR(0), - &globalEngType)); + RM_ENGINE_TYPE_GR(0), + &globalRmEngType), + done); // Free up the internal handles for this compute instance kmigmgrFreeComputeInstanceHandles(pGpu, pKernelMIGManager, pKernelMIGGpuInstance, pMIGComputeInstance); fecsSetRoutingInfo(pGpu, - GPU_GET_KERNEL_GRAPHICS(pGpu, NV2080_ENGINE_TYPE_GR_IDX(globalEngType)), + GPU_GET_KERNEL_GRAPHICS(pGpu, RM_ENGINE_TYPE_GR_IDX(globalRmEngType)), pKernelMIGGpuInstance->instanceHandles.hClient, pKernelMIGGpuInstance->instanceHandles.hSubdevice, - NV2080_ENGINE_TYPE_GR_IDX(bitVectorCountTrailingZeros(&grEngines))); + RM_ENGINE_TYPE_GR_IDX(bitVectorCountTrailingZeros(&grEngines))); if (pMIGComputeInstance->pShare != NULL) { @@ -4157,7 +4364,10 @@ kmigmgrDeleteComputeInstance_IMPL pMIGComputeInstance->pOsRmCaps = NULL; - return NV_OK; +done: + portMemFreeStackOrHeap(pConfigRequestPerCi); + + return status; } /*! @@ -4173,7 +4383,7 @@ _kmigmgrPrintComputeInstances { #if NV_PRINTF_LEVEL_ENABLED(LEVEL_INFO) #define PADDING_STR "----------------------------------------------------" - NvU32 engineType; + RM_ENGINE_TYPE rmEngineType; NvU32 CIIdx; NV_PRINTF(LEVEL_INFO, "\n"); @@ -4185,7 +4395,7 @@ _kmigmgrPrintComputeInstances NV_PRINTF(LEVEL_INFO, "%s\n", PADDING_STR); NV_PRINTF(LEVEL_INFO, "| %14d | %14d | %14d |\n", pKernelMIGGpuInstance->swizzId, - kmigmgrCountEnginesOfType(&pKernelMIGGpuInstance->resourceAllocation.engines, NV2080_ENGINE_TYPE_GR(0)), + kmigmgrCountEnginesOfType(&pKernelMIGGpuInstance->resourceAllocation.engines, RM_ENGINE_TYPE_GR(0)), pKernelMIGGpuInstance->resourceAllocation.gpcCount); for (CIIdx = 0; @@ -4202,8 +4412,8 @@ _kmigmgrPrintComputeInstances pComputeResourceAllocation = &pKernelMIGGpuInstance->MIGComputeInstance[CIIdx].resourceAllocation; NV_ASSERT_OK( - kmigmgrEngineTypeXlate(&pComputeResourceAllocation->localEngines, NV2080_ENGINE_TYPE_GR(0), - &pComputeResourceAllocation->engines, &engineType)); + kmigmgrEngineTypeXlate(&pComputeResourceAllocation->localEngines, RM_ENGINE_TYPE_GR(0), + &pComputeResourceAllocation->engines, &rmEngineType)); NV_PRINTF(LEVEL_INFO, "%s\n", PADDING_STR); if (IS_GSP_CLIENT(pGpu)) @@ -4219,7 +4429,7 @@ _kmigmgrPrintComputeInstances "Gr Engine IDX", "GPC Mask"); NV_PRINTF(LEVEL_INFO, "| %23d | %23X |\n", - NV2080_ENGINE_TYPE_GR_IDX(engineType), + RM_ENGINE_TYPE_GR_IDX(rmEngineType), gpcMask); } else @@ -4229,7 +4439,7 @@ _kmigmgrPrintComputeInstances "Gr Engine IDX", "GPC Count"); NV_PRINTF(LEVEL_INFO, "| %23d | %23X |\n", - NV2080_ENGINE_TYPE_GR_IDX(engineType), + RM_ENGINE_TYPE_GR_IDX(rmEngineType), pComputeResourceAllocation->gpcCount); } } @@ -4262,7 +4472,7 @@ kmigmgrConfigureGPUInstance_IMPL OBJGPU *pGpu, KernelMIGManager *pKernelMIGManager, NvU32 swizzId, - NvU32 *pGpcCountPerGr, + const KMIGMGR_CONFIGURE_INSTANCE_REQUEST *pConfigRequestsPerCi, NvU32 updateEngMask ) { @@ -4272,10 +4482,12 @@ kmigmgrConfigureGPUInstance_IMPL NvU32 j; KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance = NULL; NvBool bAssigning; - NvU32 checkGrs[NV2080_ENGINE_TYPE_GR_SIZE]; + RM_ENGINE_TYPE checkGrs[RM_ENGINE_TYPE_GR_SIZE]; NvU32 checkGrCount = 0; - NvU32 engineType; + RM_ENGINE_TYPE rmEngineType; KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); + NvBool bIsCTSRequired = kmigmgrIsCTSAlignmentRequired_HAL(pGpu, pKernelMIGManager); + NvU32 localIdx; // Sanity check the GPU instance requested to be configured if (!kmigmgrIsSwizzIdInUse(pGpu, pKernelMIGManager, swizzId)) @@ -4291,13 +4503,14 @@ kmigmgrConfigureGPUInstance_IMPL portMemSet(checkGrs, 0, sizeof(checkGrs)); i = 0; - FOR_EACH_IN_BITVECTOR(&pKernelMIGGpuInstance->resourceAllocation.engines, engineType) + localIdx = 0; + FOR_EACH_IN_BITVECTOR(&pKernelMIGGpuInstance->resourceAllocation.engines, rmEngineType) { NvU32 engineIdx; - if (!NV2080_ENGINE_TYPE_IS_GR(engineType)) + if (!RM_ENGINE_TYPE_IS_GR(rmEngineType)) continue; - engineIdx = NV2080_ENGINE_TYPE_GR_IDX(engineType); + engineIdx = RM_ENGINE_TYPE_GR_IDX(rmEngineType); // Skip over invalid entries if (!(updateEngMask & NVBIT32(i))) @@ -4306,20 +4519,30 @@ kmigmgrConfigureGPUInstance_IMPL continue; } - // Make sure no requested GPC count is greater than instance GPC count - if (pGpcCountPerGr[i] > pKernelMIGGpuInstance->resourceAllocation.gpcCount) + // Resource checks are verified by CTS ID assignment when required, else use GPC count + if (bIsCTSRequired) { - NV_PRINTF(LEVEL_ERROR, - "Invalid GPC count - %d requested for GrIdx - %d.\n", - pGpcCountPerGr[i], - engineIdx); - return NV_ERR_INVALID_ARGUMENT; + NV_CHECK_OR_RETURN(LEVEL_ERROR, + pConfigRequestsPerCi[localIdx].ctsId != KMIGMGR_CTSID_INVALID, + NV_ERR_INSUFFICIENT_RESOURCES); + } + else + { + // Make sure no requested GPC count is greater than instance GPC count + if (pConfigRequestsPerCi[localIdx].profile.gpcCount > pKernelMIGGpuInstance->resourceAllocation.gpcCount) + { + NV_PRINTF(LEVEL_ERROR, + "Invalid GPC count - %d requested for GrIdx - %d.\n", + pConfigRequestsPerCi[localIdx].profile.gpcCount, + engineIdx); + return NV_ERR_INVALID_ARGUMENT; + } } - bAssigning = bAssigning || pGpcCountPerGr[i] > 0; - - checkGrs[checkGrCount++] = engineType; + bAssigning = bAssigning || pConfigRequestsPerCi[localIdx].profile.gpcCount > 0; + checkGrs[checkGrCount++] = rmEngineType; + localIdx++; i++; } FOR_EACH_IN_BITVECTOR_END(); @@ -4336,14 +4559,14 @@ kmigmgrConfigureGPUInstance_IMPL { // Invalidate targeted engines i = 0; - FOR_EACH_IN_BITVECTOR(&pKernelMIGGpuInstance->resourceAllocation.engines, engineType) + FOR_EACH_IN_BITVECTOR(&pKernelMIGGpuInstance->resourceAllocation.engines, rmEngineType) { NvU32 engineIdx; - if (!NV2080_ENGINE_TYPE_IS_GR(engineType)) + if (!RM_ENGINE_TYPE_IS_GR(rmEngineType)) continue; - engineIdx = NV2080_ENGINE_TYPE_GR_IDX(engineType); + engineIdx = RM_ENGINE_TYPE_GR_IDX(rmEngineType); if (updateEngMask & NVBIT32(i)) { @@ -4364,36 +4587,37 @@ kmigmgrConfigureGPUInstance_IMPL // set GPCs as requested // i = 0; - FOR_EACH_IN_BITVECTOR(&pKernelMIGGpuInstance->resourceAllocation.engines, engineType) + localIdx = 0; + FOR_EACH_IN_BITVECTOR(&pKernelMIGGpuInstance->resourceAllocation.engines, rmEngineType) { - NvU32 virtualGpcCount; NvU32 engineIdx; - NvU32 gpcCount = pGpcCountPerGr[i]; + NvU32 gpcCount = pConfigRequestsPerCi[localIdx].profile.gpcCount; - if (!NV2080_ENGINE_TYPE_IS_GR(engineType)) + if (!RM_ENGINE_TYPE_IS_GR(rmEngineType)) continue; - engineIdx = NV2080_ENGINE_TYPE_GR_IDX(engineType); + engineIdx = RM_ENGINE_TYPE_GR_IDX(rmEngineType); - if (!(updateEngMask & NVBIT32(i)) || (0 == gpcCount)) + if (!(updateEngMask & NVBIT32(i))) { i++; continue; } - // - // The virtualGpcCount here really specifies the numer of GPCs guarnateed - // to be present for a CI/GI. We limit the number of GPCs a CI can request - // VEIDs for to the GI's guarnatteed GPC count. - // - virtualGpcCount = NV_MIN(gpcCount, pKernelMIGGpuInstance->resourceAllocation.virtualGpcCount); + if (gpcCount == 0) + { + localIdx++; + i++; + continue; + } // Update the GR to VEID mapping NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, kgrmgrAllocVeidsForGrIdx(pGpu, pKernelGraphicsManager, engineIdx, - virtualGpcCount, + pConfigRequestsPerCi[localIdx].veidSpanStart, + pConfigRequestsPerCi[localIdx].profile.veidCount, pKernelMIGGpuInstance), cleanup); @@ -4404,23 +4628,34 @@ kmigmgrConfigureGPUInstance_IMPL _kmigmgrPrintComputeInstances(pGpu, pKernelMIGManager, pKernelMIGGpuInstance); i = 0; - FOR_EACH_IN_BITVECTOR(&pKernelMIGGpuInstance->resourceAllocation.engines, engineType) + localIdx = 0; + FOR_EACH_IN_BITVECTOR(&pKernelMIGGpuInstance->resourceAllocation.engines, rmEngineType) { NvU32 engineIdx; - NvU32 gpcCount = pGpcCountPerGr[i]; + NvU32 gpcCount = pConfigRequestsPerCi[localIdx].profile.gpcCount; KernelGraphics *pKGr; - if (!NV2080_ENGINE_TYPE_IS_GR(engineType)) + if (!RM_ENGINE_TYPE_IS_GR(rmEngineType)) continue; - engineIdx = NV2080_ENGINE_TYPE_GR_IDX(engineType); + engineIdx = RM_ENGINE_TYPE_GR_IDX(rmEngineType); - if (!(updateEngMask & NVBIT32(i)) || (0 == gpcCount)) + if (!(updateEngMask & NVBIT32(i))) { i++; continue; } + if (gpcCount == 0) + { + localIdx++; + i++; + continue; + } + + if (bIsCTSRequired) + kmigmgrSetCTSIdInUse(pKernelMIGGpuInstance, pConfigRequestsPerCi[localIdx].ctsId, engineIdx, NV_TRUE); + pKGr = GPU_GET_KERNEL_GRAPHICS(pGpu, engineIdx); // Re-pull public static data for kernel graphics status = kgraphicsLoadStaticInfo_HAL(pGpu, pKGr, pKernelMIGGpuInstance->swizzId); @@ -4441,7 +4676,7 @@ kmigmgrConfigureGPUInstance_IMPL cleanup: j = 0; - FOR_EACH_IN_BITVECTOR(&pKernelMIGGpuInstance->resourceAllocation.engines, engineType) + FOR_EACH_IN_BITVECTOR(&pKernelMIGGpuInstance->resourceAllocation.engines, rmEngineType) { NvU32 engineIdx; @@ -4449,10 +4684,10 @@ cleanup: if (j == i) break; - if (!NV2080_ENGINE_TYPE_IS_GR(engineType)) + if (!RM_ENGINE_TYPE_IS_GR(rmEngineType)) continue; - engineIdx = NV2080_ENGINE_TYPE_GR_IDX(engineType); + engineIdx = RM_ENGINE_TYPE_GR_IDX(rmEngineType); if (updateEngMask & NVBIT32(j)) { @@ -4493,6 +4728,10 @@ kmigmgrInvalidateGrGpcMapping_IMPL gfid = GPU_GFID_PF; } + // Release CTS-ID fields + if (kmigmgrIsCTSAlignmentRequired_HAL(pGpu, pKernelMIGManager)) + kmigmgrSetCTSIdInUse(pKernelMIGGpuInstance, KMIGMGR_CTSID_INVALID, grIdx, NV_FALSE); + // Free global ctx buffers, this will need to be regenerated pKernelGraphics = GPU_GET_KERNEL_GRAPHICS(pGpu, grIdx); fecsBufferTeardown(pGpu, pKernelGraphics); @@ -4551,7 +4790,7 @@ kmigmgrInvalidateGPUInstance_IMPL MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance = NULL; NvU32 i; - NvU32 engineType; + RM_ENGINE_TYPE rmEngineType; KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); // Sanity checks @@ -4603,15 +4842,15 @@ kmigmgrInvalidateGPUInstance_IMPL } // Remove GR->GPC mappings in GPU instance Info - FOR_EACH_IN_BITVECTOR(&pKernelMIGGpuInstance->resourceAllocation.engines, engineType) + FOR_EACH_IN_BITVECTOR(&pKernelMIGGpuInstance->resourceAllocation.engines, rmEngineType) { NvU32 engineIdx; KernelGraphics *pKernelGraphics; - if (!NV2080_ENGINE_TYPE_IS_GR(engineType)) + if (!RM_ENGINE_TYPE_IS_GR(rmEngineType)) continue; - engineIdx = NV2080_ENGINE_TYPE_GR_IDX(engineType); + engineIdx = RM_ENGINE_TYPE_GR_IDX(rmEngineType); NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(rmStatus, kmigmgrInvalidateGr(pGpu, pKernelMIGManager, pKernelMIGGpuInstance, engineIdx)); @@ -4734,22 +4973,22 @@ kmigmgrDestroyGPUInstanceGrBufPools_IMPL KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance ) { - NvU32 engineType; + RM_ENGINE_TYPE rmEngineType; if (!ctxBufPoolIsSupported(pGpu)) return; NV_ASSERT(pKernelMIGGpuInstance != NULL); - FOR_EACH_IN_BITVECTOR(&pKernelMIGGpuInstance->resourceAllocation.engines, engineType) + FOR_EACH_IN_BITVECTOR(&pKernelMIGGpuInstance->resourceAllocation.engines, rmEngineType) { NvU32 engineIdx; KernelGraphics *pKernelGraphics; - if (!NV2080_ENGINE_TYPE_IS_GR(engineType)) + if (!RM_ENGINE_TYPE_IS_GR(rmEngineType)) continue; - engineIdx = NV2080_ENGINE_TYPE_GR_IDX(engineType); + engineIdx = RM_ENGINE_TYPE_GR_IDX(rmEngineType); pKernelGraphics = GPU_GET_KERNEL_GRAPHICS(pGpu, engineIdx); kgraphicsDestroyCtxBufPool(pGpu, pKernelGraphics); @@ -4806,7 +5045,7 @@ kmigmgrDestroyGPUInstanceRunlistBufPools_IMPL KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance ) { - NvU32 engineType; + RM_ENGINE_TYPE rmEngineType; KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); if (!kmigmgrIsMemoryPartitioningNeeded_HAL(pGpu, pKernelMIGManager, pKernelMIGGpuInstance->swizzId)) @@ -4815,19 +5054,19 @@ kmigmgrDestroyGPUInstanceRunlistBufPools_IMPL if (!ctxBufPoolIsSupported(pGpu)) return; - for (engineType = 0; engineType < NV2080_ENGINE_TYPE_LAST; engineType++) + for (rmEngineType = 0; rmEngineType < RM_ENGINE_TYPE_LAST; rmEngineType++) { - if (!NV2080_ENGINE_TYPE_IS_VALID(engineType) || - !kmigmgrIsEnginePartitionable(pGpu, pKernelMIGManager, engineType) || - !kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, engineType, kmigmgrMakeGIReference(pKernelMIGGpuInstance))) + if (!RM_ENGINE_TYPE_IS_VALID(rmEngineType) || + !kmigmgrIsEnginePartitionable(pGpu, pKernelMIGManager, rmEngineType) || + !kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, rmEngineType, kmigmgrMakeGIReference(pKernelMIGGpuInstance))) { continue; } - if (pKernelFifo->pRunlistBufPool[engineType] != NULL) + if (pKernelFifo->pRunlistBufPool[rmEngineType] != NULL) { - ctxBufPoolRelease(pKernelFifo->pRunlistBufPool[engineType]); - ctxBufPoolDestroy(&pKernelFifo->pRunlistBufPool[engineType]); + ctxBufPoolRelease(pKernelFifo->pRunlistBufPool[rmEngineType]); + ctxBufPoolDestroy(&pKernelFifo->pRunlistBufPool[rmEngineType]); } } } @@ -4930,7 +5169,6 @@ kmigmgrSetMIGState_FWCLIENT ) { KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); - KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); NV_STATUS rmStatus = NV_OK; KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); @@ -4948,39 +5186,6 @@ kmigmgrSetMIGState_FWCLIENT kmigmgrDisableWatchdog(pGpu, pKernelMIGManager), cleanup_disableWatchdog); - // Ensure NVLINK is shutdown before enabling MIG - if (!kmigmgrIsMIGNvlinkP2PSupportOverridden(pGpu, pKernelMIGManager) || - (bMemoryPartitioningNeeded)) - { - // - // Check for any alive P2P references to this GPU. P2P objects must - // be re-created after disabling MIG. If it is allowed for MIG to - // continue enablement without all P2P objects torn down, there is - // the possibility that P2P mappings and state will never be updated. - // - NV_CHECK_OR_ELSE(LEVEL_ERROR, - !kbusIsGpuP2pAlive(pGpu, GPU_GET_KERNEL_BUS(pGpu)), - rmStatus = NV_ERR_INVALID_STATE; - goto cleanup_disableWatchdog;); - - if ((pKernelNvlink != NULL) && pKernelNvlink->bEnableAli) - { - // Allow RM to continue even if the above functionality is not supported - rmStatus = knvlinkPrepareForXVEReset(pGpu, pKernelNvlink, NV_TRUE); - if ((rmStatus != NV_OK) && (rmStatus != NV_ERR_NOT_SUPPORTED)) - goto cleanup_disableNvlink; - - // Reset status to NV_OK for when NV_ERR_NOT_SUPPORTED was returned - rmStatus = NV_OK; - } - - NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(rmStatus, - gpuDeleteClassFromClassDBByClassId(pGpu, NV50_P2P)); - - if (rmStatus != NV_OK) - goto cleanup_disableNvlink; - } - // Before enabling MIG, deconfigure GR0 in legacy mode kgraphicsInvalidateStaticInfo(pGpu, pKGr); @@ -5009,6 +5214,47 @@ kmigmgrSetMIGState_FWCLIENT kmigmgrCreateGPUInstanceCheck_HAL(pGpu, pKernelMIGManager, bMemoryPartitioningNeeded), cleanup_createPartitionCheck); + // On Nvswitch based systems, suspend gpu fabric probe on nvlink inband + gpuFabricProbeSuspend(pGpu->pGpuFabricProbeInfo); + + // Ensure NVLINK is shutdown before enabling MIG + if (!kmigmgrIsMIGNvlinkP2PSupportOverridden(pGpu, pKernelMIGManager) || + bMemoryPartitioningNeeded) + { +#if (defined(DEBUG) || defined(DEVELOP)) + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + + if (pKernelNvlink != NULL) + { + NvU32 linkId; + + //TODO: Remove below code once a more robust SRT is available to test for this condition + FOR_EACH_INDEX_IN_MASK(32, linkId, pKernelNvlink->enabledLinks) + { + NV2080_CTRL_NVLINK_CORE_CALLBACK_PARAMS params; + + params.linkId = linkId; + params.callbackType.type = NV2080_CTRL_NVLINK_CALLBACK_TYPE_GET_DL_LINK_MODE; + NV_CHECK_OK(rmStatus, LEVEL_ERROR, + knvlinkExecGspRmRpc(pGpu, pKernelNvlink, + NV2080_CTRL_CMD_NVLINK_CORE_CALLBACK, + (void *)¶ms, sizeof(params))); + + if ((params.callbackType.callbackParams.getDlLinkMode.mode != NV2080_NVLINK_CORE_LINK_STATE_SLEEP) || + (params.callbackType.callbackParams.getDlLinkMode.mode != NV2080_NVLINK_CORE_LINK_STATE_OFF)) + { + NV_PRINTF(LEVEL_ERROR, "Nvlink %d is not asleep upon enteing MIG mode!\n", linkId); + } + } + FOR_EACH_INDEX_IN_MASK_END + } + rmStatus = NV_OK; +#endif + NV_ASSERT_OK_OR_GOTO(rmStatus, + gpuDeleteClassFromClassDBByClassId(pGpu, NV50_P2P), + cleanup_disableNvlink); + } + // Enable ctx buf pool before allocating any resources that uses it. if (bMemoryPartitioningNeeded) { @@ -5104,6 +5350,20 @@ cleanup_addClassToClassDB: kmigmgrEnableAllLCEs(pGpu, pKernelMIGManager, NV_FALSE)); } +cleanup_disableNvlink: + // Add P2P class back to class DB as memory partitioning is disabled + NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(rmStatus, + gpuAddClassToClassDBByClassId(pGpu, NV50_P2P)); + + // + // On Nvswitch based systems, resume the gpu fabric probe + // request on nvlink inband to register the GPU with the nvswitch fabric + // + if (pGpu->pGpuFabricProbeInfo != NULL) + { + NV_ASSERT_OK(gpuFabricProbeResume(pGpu->pGpuFabricProbeInfo)); + } + cleanup_createPartitionCheck: if (!bUnload) { @@ -5125,13 +5385,8 @@ cleanup_destroyTopLevelScrubber: kgraphicsLoadStaticInfo(pGpu, pKGr, KMIGMGR_SWIZZID_INVALID)); NV_ASSERT_OK( kmigmgrRestoreWatchdog(pGpu, pKernelMIGManager)); - } - // Add P2P class back to class DB as memory partitioning is disabled - NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(rmStatus, - gpuAddClassToClassDBByClassId(pGpu, NV50_P2P)); - // // Restore previous kmigmgr MIG state. kmigmgrSetMIGState should not // permanently modify bMIGEnabled. Restore the value to whatever was @@ -5139,22 +5394,17 @@ cleanup_destroyTopLevelScrubber: // pKernelMIGManager->bMIGEnabled = bPrevMIGState; -cleanup_disableNvlink: - if ((pKernelNvlink != NULL) && pKernelNvlink->bEnableAli) - { - // Bring Nvlinks back online before re-programming hshub - NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(rmStatus, - knvlinkPreTrainLinksToActiveAli(pGpu, pKernelNvlink, pKernelNvlink->enabledLinks, NV_FALSE)); - - NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(rmStatus, - knvlinkTrainLinksToActiveAli(pGpu, pKernelNvlink, pKernelNvlink->enabledLinks, NV_FALSE)); - } - cleanup_disableWatchdog: goto done; } done: + // + // Restore previous kmigmgr MIG state. kmigmgrSetMIGState should not + // permanently modify bMIGEnabled. Restore the value to whatever was + // present on entry to this function. + // + pKernelMIGManager->bMIGEnabled = bPrevMIGState; return rmStatus; } @@ -5186,7 +5436,7 @@ kmigmgrCreateGPUInstance_IMPL { KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance = NULL; KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); - NvU32 engineType; + RM_ENGINE_TYPE rmEngineType; // // Determine SwizzID for this gpu instance. If this isn't a restore, this @@ -5233,23 +5483,23 @@ kmigmgrCreateGPUInstance_IMPL NV_ASSERT_OK_OR_GOTO(rmStatus, kmemsysInitMIGMemoryPartitionTable_HAL(pGpu, pKernelMemorySystem), invalidate); - FOR_EACH_IN_BITVECTOR(&pKernelMIGGpuInstance->resourceAllocation.engines, engineType) + FOR_EACH_IN_BITVECTOR(&pKernelMIGGpuInstance->resourceAllocation.engines, rmEngineType) { NvU32 engineIdx; KernelGraphics *pKernelGraphics; - NvU32 localEngineType; + RM_ENGINE_TYPE localEngineType; - if (!NV2080_ENGINE_TYPE_IS_GR(engineType)) + if (!RM_ENGINE_TYPE_IS_GR(rmEngineType)) continue; - engineIdx = NV2080_ENGINE_TYPE_GR_IDX(engineType); + engineIdx = RM_ENGINE_TYPE_GR_IDX(rmEngineType); pKernelGraphics = GPU_GET_KERNEL_GRAPHICS(pGpu, engineIdx); NV_ASSERT_OK_OR_GOTO(rmStatus, kmigmgrGetGlobalToLocalEngineType(pGpu, pKernelMIGManager, kmigmgrMakeGIReference(pKernelMIGGpuInstance), - engineType, + rmEngineType, &localEngineType), invalidate); @@ -5257,7 +5507,7 @@ kmigmgrCreateGPUInstance_IMPL pKernelGraphics, pKernelMIGGpuInstance->instanceHandles.hClient, pKernelMIGGpuInstance->instanceHandles.hSubdevice, - NV2080_ENGINE_TYPE_GR_IDX(localEngineType)); + RM_ENGINE_TYPE_GR_IDX(localEngineType)); } FOR_EACH_IN_BITVECTOR_END(); @@ -5398,7 +5648,7 @@ kmigmgrInitGPUInstanceRunlistBufPools_IMPL KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance ) { - NvU32 engineType; + RM_ENGINE_TYPE rmEngineType; KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); CTX_BUF_INFO runlistBufInfo[NUM_BUFFERS_PER_RUNLIST] = {0}; NvU64 rlSize; @@ -5416,18 +5666,18 @@ kmigmgrInitGPUInstanceRunlistBufPools_IMPL if (!kmigmgrIsMemoryPartitioningNeeded_HAL(pGpu, pKernelMIGManager, swizzId)) return NV_OK; - for (engineType = 0; engineType < NV2080_ENGINE_TYPE_LAST; engineType++) + for (rmEngineType = 0; rmEngineType < RM_ENGINE_TYPE_LAST; rmEngineType++) { - if (!NV2080_ENGINE_TYPE_IS_VALID(engineType) || - !kmigmgrIsEnginePartitionable(pGpu, pKernelMIGManager, engineType) || - !kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, engineType, kmigmgrMakeGIReference(pKernelMIGGpuInstance))) + if (!RM_ENGINE_TYPE_IS_VALID(rmEngineType) || + !kmigmgrIsEnginePartitionable(pGpu, pKernelMIGManager, rmEngineType) || + !kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, rmEngineType, kmigmgrMakeGIReference(pKernelMIGGpuInstance))) { continue; } // Get runlist ID for Engine type. NV_ASSERT_OK_OR_RETURN(kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, - ENGINE_INFO_TYPE_NV2080, engineType, + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, (NvU32)rmEngineType, ENGINE_INFO_TYPE_RUNLIST, &runlistId)); // @@ -5444,15 +5694,15 @@ kmigmgrInitGPUInstanceRunlistBufPools_IMPL runlistBufInfo[i].bContig = NV_TRUE; } - NV_ASSERT_OK_OR_RETURN(ctxBufPoolInit(pGpu, pHeap, &pKernelFifo->pRunlistBufPool[engineType])); - NV_ASSERT_OR_RETURN(pKernelFifo->pRunlistBufPool[engineType] != NULL, NV_ERR_INVALID_STATE); + NV_ASSERT_OK_OR_RETURN(ctxBufPoolInit(pGpu, pHeap, &pKernelFifo->pRunlistBufPool[rmEngineType])); + NV_ASSERT_OR_RETURN(pKernelFifo->pRunlistBufPool[rmEngineType] != NULL, NV_ERR_INVALID_STATE); // // Skip scrubber for runlist buffer alloctions since gpu instance scrubber is not setup yet // and it will be destroyed before deleting the runlist buffer pool. // - ctxBufPoolSetScrubSkip(pKernelFifo->pRunlistBufPool[engineType], NV_TRUE); - NV_ASSERT_OK_OR_RETURN(ctxBufPoolReserve(pGpu, pKernelFifo->pRunlistBufPool[engineType], &runlistBufInfo[0], NUM_BUFFERS_PER_RUNLIST)); + ctxBufPoolSetScrubSkip(pKernelFifo->pRunlistBufPool[rmEngineType], NV_TRUE); + NV_ASSERT_OK_OR_RETURN(ctxBufPoolReserve(pGpu, pKernelFifo->pRunlistBufPool[rmEngineType], &runlistBufInfo[0], NUM_BUFFERS_PER_RUNLIST)); } return NV_OK; @@ -5476,7 +5726,7 @@ kmigmgrInitGPUInstanceGrBufPools_IMPL CTX_BUF_INFO globalCtxBufInfo[GR_GLOBALCTX_BUFFER_COUNT]; Heap *pHeap = NULL; NV_STATUS rmStatus = NV_OK; - NvU32 engineType; + RM_ENGINE_TYPE rmEngineType; NV_ASSERT_OR_RETURN(pKernelMIGGpuInstance != NULL, NV_ERR_INVALID_ARGUMENT); pHeap = pKernelMIGGpuInstance->pMemoryPartitionHeap; @@ -5510,16 +5760,16 @@ kmigmgrInitGPUInstanceGrBufPools_IMPL } FOR_EACH_IN_ENUM_END; - FOR_EACH_IN_BITVECTOR(&pKernelMIGGpuInstance->resourceAllocation.engines, engineType) + FOR_EACH_IN_BITVECTOR(&pKernelMIGGpuInstance->resourceAllocation.engines, rmEngineType) { NvU32 engineIdx; KernelGraphics *pKernelGraphics; CTX_BUF_POOL_INFO *pGrCtxBufPool; - if (!NV2080_ENGINE_TYPE_IS_GR(engineType)) + if (!RM_ENGINE_TYPE_IS_GR(rmEngineType)) continue; - engineIdx = NV2080_ENGINE_TYPE_GR_IDX(engineType); + engineIdx = RM_ENGINE_TYPE_GR_IDX(rmEngineType); pKernelGraphics = GPU_GET_KERNEL_GRAPHICS(pGpu, engineIdx); NV_ASSERT_OK_OR_GOTO(rmStatus, @@ -5629,7 +5879,7 @@ subdeviceCtrlCmdGpuGetActivePartitionIds_IMPL ct_assert(NV2080_CTRL_GPU_MAX_PARTITIONS == KMIGMGR_MAX_GPU_INSTANCES); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); if ((pKernelMIGManager == NULL) || !pGpu->getProperty(pGpu, PDB_PROP_GPU_MIG_SUPPORTED)) { @@ -5677,7 +5927,7 @@ subdeviceCtrlCmdGpuGetPartitionCapacity_IMPL KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); NV_CHECK_OR_RETURN(LEVEL_INFO, IS_MIG_ENABLED(pGpu), NV_ERR_NOT_SUPPORTED); @@ -5760,7 +6010,7 @@ subdeviceCtrlCmdGpuDescribePartitions_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_MIG_SUPPORTED)) { @@ -5792,7 +6042,7 @@ subdeviceCtrlCmdGpuSetPartitioningMode_IMPL KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); if (IS_VIRTUAL(pGpu)) { @@ -5973,7 +6223,7 @@ subdeviceCtrlCmdGpuSetPartitions_IMPL KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); NV_ASSERT_OR_RETURN(pCallContext != NULL, NV_ERR_INVALID_STATE); @@ -6058,12 +6308,17 @@ subdeviceCtrlCmdGpuGetPartitions_IMPL MIG_INSTANCE_REF ref; NvU64 validSwizzIdMask; NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); - NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS rpcParams = *pParams; + NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS *pRpcParams = NULL; ct_assert(NV2080_CTRL_GPU_MAX_PARTITIONS == KMIGMGR_MAX_GPU_INSTANCES); ct_assert(NV2080_CTRL_GPU_MAX_GPC_PER_SMC == KGRMGR_MAX_GPC); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + pRpcParams = portMemAllocNonPaged(sizeof(*pRpcParams)); + NV_CHECK_OR_RETURN(LEVEL_INFO, pRpcParams != NULL, NV_ERR_NO_MEMORY); + + *pRpcParams = *pParams; if (!IS_VIRTUAL(pGpu)) { @@ -6072,19 +6327,20 @@ subdeviceCtrlCmdGpuGetPartitions_IMPL RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - NV_CHECK_OK_OR_RETURN(LEVEL_WARNING, + NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_WARNING, pRmApi->Control(pRmApi, pRmCtrlParams->hClient, pRmCtrlParams->hObject, NV2080_CTRL_CMD_INTERNAL_MIGMGR_GET_GPU_INSTANCES, - &rpcParams, - sizeof(rpcParams))); + pRpcParams, + sizeof(*pRpcParams)), done); } if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_MIG_SUPPORTED)) { NV_PRINTF(LEVEL_INFO, "MIG not supported on this GPU.\n"); - return NV_ERR_NOT_SUPPORTED; + rmStatus = NV_ERR_NOT_SUPPORTED; + goto done; } if (!IS_MIG_ENABLED(pGpu)) @@ -6094,7 +6350,8 @@ subdeviceCtrlCmdGpuGetPartitions_IMPL { // set the valid gpu instance count to "0" and return pParams->validPartitionCount = 0; - return NV_OK; + rmStatus = NV_OK; + goto done; } // See if all gpu instances are requested and get info for all gpu instance @@ -6102,7 +6359,8 @@ subdeviceCtrlCmdGpuGetPartitions_IMPL { CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); - NV_ASSERT_OR_RETURN(pCallContext != NULL, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_ELSE(pCallContext != NULL, + rmStatus = NV_ERR_INVALID_STATE; goto done); if (!rmclientIsCapableOrAdminByHandle(hClient, NV_RM_CAP_SYS_SMC_CONFIG, @@ -6110,7 +6368,8 @@ subdeviceCtrlCmdGpuGetPartitions_IMPL { NV_PRINTF(LEVEL_ERROR, "Non privileged client requesting global gpu instance info\n"); - return NV_ERR_INSUFFICIENT_PERMISSIONS; + rmStatus = NV_ERR_INSUFFICIENT_PERMISSIONS; + goto done; } // Take all swizzId's for consideration @@ -6123,7 +6382,8 @@ subdeviceCtrlCmdGpuGetPartitions_IMPL { // set the valid gpu instance count to "0" and return pParams->validPartitionCount = 0; - return NV_OK; + rmStatus = NV_OK; + goto done; } validSwizzIdMask = NVBIT64(ref.pKernelMIGGpuInstance->swizzId); @@ -6135,7 +6395,7 @@ subdeviceCtrlCmdGpuGetPartitions_IMPL MIG_RESOURCE_ALLOCATION *pResourceAllocation; NvU32 swizzId = portUtilCountTrailingZeros64(validSwizzIdMask); NvU32 j; - NvU32 engineType; + RM_ENGINE_TYPE rmEngineType; rmStatus = kmigmgrGetGPUInstanceInfo(pGpu, pKernelMIGManager, swizzId, &ref.pKernelMIGGpuInstance); if (rmStatus != NV_OK) @@ -6143,7 +6403,7 @@ subdeviceCtrlCmdGpuGetPartitions_IMPL NV_PRINTF(LEVEL_ERROR, "Unable to get gpu instance info for swizzId - %d\n", swizzId); - return rmStatus; + goto done; } pResourceAllocation = &ref.pKernelMIGGpuInstance->resourceAllocation; @@ -6151,48 +6411,50 @@ subdeviceCtrlCmdGpuGetPartitions_IMPL pParams->queryPartitionInfo[i].partitionFlag = ref.pKernelMIGGpuInstance->partitionFlag; pParams->queryPartitionInfo[i].swizzId = ref.pKernelMIGGpuInstance->swizzId; pParams->queryPartitionInfo[i].grEngCount = - kmigmgrCountEnginesOfType(&pResourceAllocation->engines, NV2080_ENGINE_TYPE_GR(0)); + kmigmgrCountEnginesOfType(&pResourceAllocation->engines, RM_ENGINE_TYPE_GR(0)); pParams->queryPartitionInfo[i].smCount = ref.pKernelMIGGpuInstance->pProfile->smCount; pParams->queryPartitionInfo[i].veidCount = pResourceAllocation->veidCount; pParams->queryPartitionInfo[i].ceCount = - kmigmgrCountEnginesOfType(&pResourceAllocation->engines, NV2080_ENGINE_TYPE_COPY(0)); + kmigmgrCountEnginesOfType(&pResourceAllocation->engines, RM_ENGINE_TYPE_COPY(0)); pParams->queryPartitionInfo[i].gpcCount = pResourceAllocation->gpcCount; pParams->queryPartitionInfo[i].virtualGpcCount = pResourceAllocation->virtualGpcCount; pParams->queryPartitionInfo[i].nvDecCount = - kmigmgrCountEnginesOfType(&pResourceAllocation->engines, NV2080_ENGINE_TYPE_NVDEC(0)); + kmigmgrCountEnginesOfType(&pResourceAllocation->engines, RM_ENGINE_TYPE_NVDEC(0)); pParams->queryPartitionInfo[i].nvEncCount = - kmigmgrCountEnginesOfType(&pResourceAllocation->engines, NV2080_ENGINE_TYPE_NVENC(0)); + kmigmgrCountEnginesOfType(&pResourceAllocation->engines, RM_ENGINE_TYPE_NVENC(0)); pParams->queryPartitionInfo[i].nvJpgCount = - kmigmgrCountEnginesOfType(&pResourceAllocation->engines, NV2080_ENGINE_TYPE_NVJPG); + kmigmgrCountEnginesOfType(&pResourceAllocation->engines, RM_ENGINE_TYPE_NVJPG); pParams->queryPartitionInfo[i].nvOfaCount = - kmigmgrCountEnginesOfType(&pResourceAllocation->engines, NV2080_ENGINE_TYPE_OFA); + kmigmgrCountEnginesOfType(&pResourceAllocation->engines, RM_ENGINE_TYPE_OFA); pParams->queryPartitionInfo[i].memSize = rangeLength(ref.pKernelMIGGpuInstance->memRange); + pParams->queryPartitionInfo[i].validCTSIdMask = ref.pKernelMIGGpuInstance->pProfile->validCTSIdMask; pParams->queryPartitionInfo[i].bValid = NV_TRUE; { - NV_ASSERT_OR_RETURN(rpcParams.queryPartitionInfo[i].bValid, NV_ERR_INVALID_STATE); - NV_ASSERT_OR_RETURN( - pParams->queryPartitionInfo[i].swizzId == rpcParams.queryPartitionInfo[i].swizzId, - NV_ERR_INVALID_STATE); + NV_ASSERT_OR_ELSE(pRpcParams->queryPartitionInfo[i].bValid, + rmStatus = NV_ERR_INVALID_STATE; goto done); + NV_ASSERT_OR_ELSE( + pParams->queryPartitionInfo[i].swizzId == pRpcParams->queryPartitionInfo[i].swizzId, + rmStatus = NV_ERR_INVALID_STATE; goto done); // Fill GPCs associated with every GR j = 0; - FOR_EACH_IN_BITVECTOR(&pResourceAllocation->engines, engineType) + FOR_EACH_IN_BITVECTOR(&pResourceAllocation->engines, rmEngineType) { - if (!NV2080_ENGINE_TYPE_IS_GR(engineType)) + if (!RM_ENGINE_TYPE_IS_GR(rmEngineType)) continue; - pParams->queryPartitionInfo[i].gpcsPerGr[j] = rpcParams.queryPartitionInfo[i].gpcsPerGr[j]; - pParams->queryPartitionInfo[i].veidsPerGr[j] = rpcParams.queryPartitionInfo[i].veidsPerGr[j]; - pParams->queryPartitionInfo[i].virtualGpcsPerGr[j] = rpcParams.queryPartitionInfo[i].virtualGpcsPerGr[j]; + pParams->queryPartitionInfo[i].gpcsPerGr[j] = pRpcParams->queryPartitionInfo[i].gpcsPerGr[j]; + pParams->queryPartitionInfo[i].veidsPerGr[j] = pRpcParams->queryPartitionInfo[i].veidsPerGr[j]; + pParams->queryPartitionInfo[i].virtualGpcsPerGr[j] = pRpcParams->queryPartitionInfo[i].virtualGpcsPerGr[j]; j++; } FOR_EACH_IN_BITVECTOR_END(); // Take the value provided by physical - pParams->queryPartitionInfo[i].bPartitionError = rpcParams.queryPartitionInfo[i].bPartitionError; - pParams->queryPartitionInfo[i].span = rpcParams.queryPartitionInfo[i].span; + pParams->queryPartitionInfo[i].bPartitionError = pRpcParams->queryPartitionInfo[i].bPartitionError; + pParams->queryPartitionInfo[i].span = pRpcParams->queryPartitionInfo[i].span; } ++pParams->validPartitionCount; @@ -6204,6 +6466,9 @@ subdeviceCtrlCmdGpuGetPartitions_IMPL } } +done: + portMemFree(pRpcParams); + return rmStatus; } @@ -6361,10 +6626,10 @@ subdeviceCtrlCmdGpuGetComputeProfiles_IMPL MIG_INSTANCE_REF ref; NvU32 entryCount; NvU32 i; - + if (!IS_MIG_ENABLED(pGpu)) return NV_ERR_INVALID_STATE; - + // // Grab MIG partition reference if available. The profile's SM count is used // to filter out compute profiles which wouldn't fit on the GI anyway. This @@ -6383,13 +6648,22 @@ subdeviceCtrlCmdGpuGetComputeProfiles_IMPL entryCount = 0; for (i = 0; i < pStaticInfo->pCIProfiles->profileCount; i++) { - if (pStaticInfo->pCIProfiles->profiles[i].smCount > maxSmCount) continue; + // If there are any duplicate compute profiles (i.e. same GPC and SM counts), skip broadcasting the + // profile out. + if ((entryCount > 0) && + (pParams->profiles[entryCount - 1].gfxGpcCount == pStaticInfo->pCIProfiles->profiles[i].gfxGpcCount) && + (pParams->profiles[entryCount - 1].gpcCount == pStaticInfo->pCIProfiles->profiles[i].gpcCount) && + (pParams->profiles[entryCount - 1].smCount == pStaticInfo->pCIProfiles->profiles[i].smCount)) + { + continue; + } + pParams->profiles[entryCount].computeSize = pStaticInfo->pCIProfiles->profiles[i].computeSize; pParams->profiles[entryCount].gfxGpcCount = pStaticInfo->pCIProfiles->profiles[i].gfxGpcCount; - pParams->profiles[entryCount].gpcCount = pStaticInfo->pCIProfiles->profiles[i].gpcCount; + pParams->profiles[entryCount].gpcCount = pStaticInfo->pCIProfiles->profiles[i].physicalSlots; pParams->profiles[entryCount].smCount = pStaticInfo->pCIProfiles->profiles[i].smCount; pParams->profiles[entryCount].veidCount = pStaticInfo->pCIProfiles->profiles[i].veidCount; entryCount++; @@ -6397,3 +6671,721 @@ subdeviceCtrlCmdGpuGetComputeProfiles_IMPL pParams->profileCount = entryCount; return NV_OK; } + +/*! + * @brief Function to get the next computeSize flag either larger or smaller than + * the passed in flag. + * + * @param[IN] bGetNextSmallest Flag controlling whether the next largest or smallest + * compute size is returned + * @param[IN] computeSize Base computeSize to lookup + * + * @return Input is the original compute size + * a.) If compute size input is KMIGMGR_COMPUTE_SIZE_INVALID, out is: + * 1.) NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL if bGetNextSmallest + * 2.) NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH if !bGetNextSmallest + * b.) Else output is next largest/smallest based upon bGetNextSmallest + */ +NvU32 +kmigmgrGetNextComputeSize_IMPL +( + NvBool bGetNextSmallest, + NvU32 computeSize +) +{ + const NvU32 computeSizeFlags[] = + { + KMIGMGR_COMPUTE_SIZE_INVALID, + NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL, + NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF, + NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF, + NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER, + NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_QUARTER, + NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH, + KMIGMGR_COMPUTE_SIZE_INVALID + }; + + NV_ASSERT_OR_RETURN(computeSize <= KMIGMGR_COMPUTE_SIZE_INVALID, KMIGMGR_COMPUTE_SIZE_INVALID); + + if (computeSize == KMIGMGR_COMPUTE_SIZE_INVALID) + { + return (bGetNextSmallest) ? computeSizeFlags[1] : computeSizeFlags[NV_ARRAY_ELEMENTS(computeSizeFlags) - 2]; + } + else + { + NvU32 i; + + for (i = 1; i < NV_ARRAY_ELEMENTS(computeSizeFlags) - 1; i++) + if (computeSizeFlags[i] == computeSize) + break; + + return (bGetNextSmallest) ? computeSizeFlags[i + 1] : computeSizeFlags[i - 1]; + } +} + +/*! + * @brief Function to lookup a skyline for a given compute size + * + * @param[IN] pGpu + * @param[IN] pKernelMIGManager + * @param[IN] computeSize Compute size to find skyline for + * @param[OUT] pSkyline Pointer to NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO struct filled with + * a copy of the skyline info associated with the gpc count + */ +NV_STATUS +kmigmgrGetSkylineFromSize_IMPL +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager, + NvU32 computeSize, + const NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO **ppSkyline +) +{ + const KERNEL_MIG_MANAGER_STATIC_INFO *pStaticInfo = kmigmgrGetStaticInfo(pGpu, pKernelMIGManager); + NvU32 i; + + NV_ASSERT_OR_RETURN(ppSkyline != NULL, NV_ERR_INVALID_ARGUMENT); + NV_CHECK_OR_RETURN(LEVEL_ERROR, pStaticInfo != NULL, NV_ERR_OBJECT_NOT_FOUND); + NV_CHECK_OR_RETURN(LEVEL_WARNING, pStaticInfo->pSkylineInfo != NULL, NV_ERR_OBJECT_NOT_FOUND); + + for (i = 0; i < pStaticInfo->pSkylineInfo->validEntries; i++) + { + if (pStaticInfo->pSkylineInfo->skylineTable[i].computeSizeFlag == computeSize) + { + *ppSkyline = &pStaticInfo->pSkylineInfo->skylineTable[i]; + return NV_OK; + } + } + NV_PRINTF(LEVEL_INFO, "No skyline for with compute size %d\n", computeSize); + return NV_ERR_OBJECT_NOT_FOUND; +} + +/*! + * @brief Function to lookup a compute profile for a given compute size + * + * @param[IN] pGpu + * @param[IN] pKernelMIGManager + * @param[IN] computeSize Compute size to find skyline for + * @param[OUT] pProfile Pointer to NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE struct filled with + * a copy of the compute profile info associated with the gpc count + */ +NV_STATUS +kmigmgrGetComputeProfileFromSize_IMPL +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager, + NvU32 computeSize, + NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE *pProfile +) +{ + const KERNEL_MIG_MANAGER_STATIC_INFO *pStaticInfo = kmigmgrGetStaticInfo(pGpu, pKernelMIGManager); + NvU32 i; + + NV_ASSERT_OR_RETURN(pProfile != NULL, NV_ERR_INVALID_ARGUMENT); + NV_CHECK_OR_RETURN(LEVEL_ERROR, pStaticInfo != NULL, NV_ERR_OBJECT_NOT_FOUND); + NV_CHECK_OR_RETURN(LEVEL_WARNING, pStaticInfo->pCIProfiles != NULL, NV_ERR_OBJECT_NOT_FOUND); + + for (i = 0; i < pStaticInfo->pCIProfiles->profileCount; i++) + { + if (pStaticInfo->pCIProfiles->profiles[i].computeSize == computeSize) + { + portMemCopy(pProfile, sizeof(*pProfile), &pStaticInfo->pCIProfiles->profiles[i], sizeof(pStaticInfo->pCIProfiles->profiles[i])); + return NV_OK; + } + } + NV_PRINTF(LEVEL_INFO, "Found no Compute Profile for computeSize=%d\n", computeSize); + return NV_ERR_OBJECT_NOT_FOUND; +} + +/*! + * @brief Function to lookup a compute profile for a given SM count + * + * @param[IN] pGpu + * @param[IN] pKernelMIGManager + * @param[IN] smCount SM Count to look up the associated compute profile + * @param[OUT] pProfile Pointer to NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE struct filled with + * a copy of the compute profile info associated with the SM count + */ +NV_STATUS +kmigmgrGetComputeProfileFromSmCount_IMPL +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager, + NvU32 smCount, + NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE *pProfile +) +{ + const KERNEL_MIG_MANAGER_STATIC_INFO *pStaticInfo = kmigmgrGetStaticInfo(pGpu, pKernelMIGManager); + NvU32 i; + + NV_ASSERT_OR_RETURN(pProfile != NULL, NV_ERR_INVALID_ARGUMENT); + NV_CHECK_OR_RETURN(LEVEL_ERROR, pStaticInfo != NULL, NV_ERR_OBJECT_NOT_FOUND); + NV_CHECK_OR_RETURN(LEVEL_WARNING, pStaticInfo->pCIProfiles != NULL, NV_ERR_OBJECT_NOT_FOUND); + + for (i = 0; i < pStaticInfo->pCIProfiles->profileCount; i++) + { + if (pStaticInfo->pCIProfiles->profiles[i].smCount == smCount) + { + portMemCopy(pProfile, sizeof(*pProfile), &pStaticInfo->pCIProfiles->profiles[i], sizeof(pStaticInfo->pCIProfiles->profiles[i])); + return NV_OK; + } + } + NV_PRINTF(LEVEL_ERROR, "Found no Compute Profile for smCount=%d\n", smCount); + return NV_ERR_OBJECT_NOT_FOUND; +} + + +/*! + * @brief Function to lookup a compute profile for a given GPC count. This function converts + * the provided gpcCount into a COMPUTE_SIZE partition flag which is then looked up + * in the static info compute profile list. + * + * @param[IN] pGpu + * @param[IN] pKernelMIGManager + * @param[IN] gpcCount GPC Count to look up the associated compute profile + * @param[OUT] pProfile Pointer to NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE struct filled with + * a copy of the compute profile info associated with the GPC count + */ +NV_STATUS +kmigmgrGetComputeProfileFromGpcCount_IMPL +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager, + NvU32 gpcCount, + NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE *pProfile +) +{ + KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); + const KERNEL_MIG_MANAGER_STATIC_INFO *pStaticInfo = kmigmgrGetStaticInfo(pGpu, pKernelMIGManager); + NvBool bReducedConfig = kmigmgrIsA100ReducedConfig(pGpu, pKernelMIGManager); + NvU32 compSize; + NvU32 maxGpc; + NvU32 i; + + NV_ASSERT_OR_RETURN(pProfile != NULL, NV_ERR_INVALID_ARGUMENT); + NV_CHECK_OR_RETURN(LEVEL_ERROR, pStaticInfo != NULL, NV_ERR_OBJECT_NOT_FOUND); + NV_CHECK_OR_RETURN(LEVEL_WARNING, pStaticInfo->pCIProfiles != NULL, NV_ERR_OBJECT_NOT_FOUND); + + maxGpc = pKernelGraphicsManager->legacyKgraphicsStaticInfo.pGrInfo->infoList[NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS].data; + if (bReducedConfig) + maxGpc /= 2; + + if (gpcCount <= (maxGpc / 8)) + compSize = NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH; + else if (gpcCount <= (maxGpc / 4)) + compSize = NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER; + else if (gpcCount <= ((maxGpc / 2) - 1)) + compSize = NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF; + else if (gpcCount <= (maxGpc / 2)) + compSize = NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF; + else + compSize = NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL; + + for (i = 0; i < pStaticInfo->pCIProfiles->profileCount; i++) + { + if (pStaticInfo->pCIProfiles->profiles[i].computeSize == compSize) + { + portMemCopy(pProfile, sizeof(*pProfile), &pStaticInfo->pCIProfiles->profiles[i], sizeof(pStaticInfo->pCIProfiles->profiles[i])); + return NV_OK; + } + } + + return NV_ERR_OBJECT_NOT_FOUND; +} + +/*! + * @brief Function to lookup a compute profile for a given cts ID + * + * @param[IN] pGpu + * @param[IN] pKernelMIGManager + * @param[IN] ctsId CTS ID to find compute profile for + * @param[OUT] pProfile Pointer to NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE struct filled with + * a copy of the compute profile info associated with the gpc count + */ +NV_STATUS +kmigmgrGetComputeProfileFromCTSId_IMPL +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager, + NvU32 ctsId, + NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE *pProfile +) +{ + const KERNEL_MIG_MANAGER_STATIC_INFO *pStaticInfo = kmigmgrGetStaticInfo(pGpu, pKernelMIGManager); + NvU32 computeSize; + + NV_ASSERT_OR_RETURN(pProfile != NULL, NV_ERR_INVALID_ARGUMENT); + NV_CHECK_OR_RETURN(LEVEL_ERROR, pStaticInfo != NULL, NV_ERR_OBJECT_NOT_FOUND); + NV_CHECK_OR_RETURN(LEVEL_WARNING, pStaticInfo->pCIProfiles != NULL, NV_ERR_OBJECT_NOT_FOUND); + + computeSize = kmigmgrGetComputeSizeFromCTSId(ctsId); + return kmigmgrGetComputeProfileFromSize(pGpu, pKernelMIGManager, computeSize, pProfile); +} + +/*! + * @brief Function which returns a mask of CTS IDs which are not usable when the input CTS + * ID is in-use. + * + * @param[IN] pGpu + * @param[IN] pKernelMIGManager + * @param[IN] ctsId Input CTS ID to look-up invalid mask for + * @param[OUT] pInvalidCTSIdMask Output mask of CTS IDs not useable with input ID + */ +NV_STATUS +kmigmgrGetInvalidCTSIdMask_IMPL +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager, + NvU32 ctsId, + NvU64 *pInvalidCTSIdMask +) +{ + // + // +---------------------------------------+ + // | 0 | + // +-------------------+-------------------+ + // | 1 | 2 | + // +-------------------+-------------------+ + // | 3 | 4 | + // +---------+---------+---------+---------+ + // | 5 | 6 | 7 | 8 | + // +---------+---------+---------+---------+ + // | 9 | 10 | 11 | 12 | + // +----+----+----+----+----+----+----+----+ + // | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | + // +----+----+----+----+----+----+----+----+ + // + NvU64 gpcSlot[KGRMGR_MAX_GR] = + { + (NVBIT64(0) | NVBIT64(1) | NVBIT64(3) | NVBIT64(5) | NVBIT64(9) | NVBIT64(13)), + (NVBIT64(0) | NVBIT64(1) | NVBIT64(3) | NVBIT64(5) | NVBIT64(9) | NVBIT64(14)), + (NVBIT64(0) | NVBIT64(1) | NVBIT64(3) | NVBIT64(6) | NVBIT64(10) | NVBIT64(15)), + (NVBIT64(0) | NVBIT64(1) | NVBIT64(3) | NVBIT64(6) | NVBIT64(10) | NVBIT64(16)), + (NVBIT64(0) | NVBIT64(2) | NVBIT64(4) | NVBIT64(7) | NVBIT64(11) | NVBIT64(17)), + (NVBIT64(0) | NVBIT64(2) | NVBIT64(4) | NVBIT64(7) | NVBIT64(11) | NVBIT64(18)), + (NVBIT64(0) | NVBIT64(2) | NVBIT64(4) | NVBIT64(8) | NVBIT64(12) | NVBIT64(19)), + (NVBIT64(0) | NVBIT64(2) | NVBIT64(4) | NVBIT64(8) | NVBIT64(12) | NVBIT64(20)) + }; + NvU64 i; + + NV_ASSERT_OR_RETURN(NULL != pInvalidCTSIdMask, NV_ERR_INVALID_ARGUMENT); + + // All bits corresponding to nonexistent CTS ids are invalid + *pInvalidCTSIdMask = DRF_SHIFTMASK64(63:KMIGMGR_MAX_GPU_CTSID); + + for (i = 0; i < KGRMGR_MAX_GR; ++i) + { + if (0 != (gpcSlot[i] & NVBIT64(ctsId))) + { + *pInvalidCTSIdMask |= gpcSlot[i]; + } + } + + return NV_OK; +} + +/*! + * @brief Returns the range of possible CTS IDs for a given compute size flag + */ +NV_RANGE +kmigmgrComputeProfileSizeToCTSIdRange_IMPL +( + NvU32 computeSize +) +{ + switch (computeSize) + { + case NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL: + return rangeMake(0,0); + + case NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF: + return rangeMake(1,2); + + case NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF: + return rangeMake(3,4); + + case NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER: + return rangeMake(5,8); + + case NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_QUARTER: + return rangeMake(9,12); + + case NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH: + return rangeMake(13,20); + + default: + return NV_RANGE_EMPTY; + } +} + +/*! + * @brief Function to get next free CTS ID + * + * @param[IN] pGpu + * @param[IN] pMIGManager + * @param[OUT] pCtsId CTS ID to be used if NV_OK returned + * @param[IN] globalValidCtsMask Mask of CTS IDs which could possibly be allocated + * @param[IN] ctsIdsInUseMask Mask of CTS IDs currently in use + * @param[IN] profileSize Profile size to get a CTS ID for + * + * @return Returns NV_STATUS + * NV_OK + * NV_ERR_INVALID_ARGUMENT If un-supported partition size is + * requested + * NV_ERR_INSUFFICIENT_RESOURCES If a CTS ID cannot be assigned + */ +NV_STATUS +kmigmgrGetFreeCTSId_IMPL +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager, + NvU32 *pCtsId, + NvU64 globalValidCtsMask, + NvU64 ctsIdsInUseMask, + NvU32 profileSize +) +{ + NV_RANGE ctsRange = kmigmgrComputeProfileSizeToCTSIdRange(profileSize); + NvU64 validMask; + NvU32 maxRemainingCapacity; + NvU32 idealCTSId; + NvU32 ctsId; + NvU64 shadowValidCTSIdMask; + + NV_CHECK_OR_RETURN(LEVEL_WARNING, !rangeIsEmpty(ctsRange), NV_ERR_INSUFFICIENT_RESOURCES); + NV_ASSERT_OR_RETURN(pCtsId != NULL, NV_ERR_INVALID_ARGUMENT); + + // construct a mask of all non-floorswept ctsIds + validMask = globalValidCtsMask; + + // Remove all ctsIds with slices currently in use + FOR_EACH_INDEX_IN_MASK(64, ctsId, ctsIdsInUseMask) + { + NvU64 invalidMask; + + NV_ASSERT_OK(kmigmgrGetInvalidCTSIdMask(pGpu, pKernelMIGManager, ctsId, &invalidMask)); + + validMask &= ~invalidMask; + } + FOR_EACH_INDEX_IN_MASK_END; + + // compute valid ctsIds for this request that can still be assigned + shadowValidCTSIdMask = validMask; + validMask &= DRF_SHIFTMASK64(ctsRange.hi:ctsRange.lo); + + // If there are no valid, open ctsIds, then bail here + NV_CHECK_OR_RETURN(LEVEL_SILENT, validMask != 0x0, NV_ERR_INSUFFICIENT_RESOURCES); + + // Determine which available CTS ids will reduce the remaining capacity the least + maxRemainingCapacity = 0; + idealCTSId = portUtilCountTrailingZeros64(validMask); + FOR_EACH_INDEX_IN_MASK(64, ctsId, validMask) + { + NvU64 invalidMask; + NV_ASSERT_OK(kmigmgrGetInvalidCTSIdMask(pGpu, pKernelMIGManager, ctsId, &invalidMask)); + + NvU32 remainingCapacity = nvPopCount64(shadowValidCTSIdMask & ~invalidMask); + + if (remainingCapacity > maxRemainingCapacity) + { + maxRemainingCapacity = remainingCapacity; + idealCTSId = ctsId; + } + } + FOR_EACH_INDEX_IN_MASK_END; + + *pCtsId = idealCTSId; + return NV_OK; +} + +/*! @brief This function determines whether or not CTS alignment and slot requirements are needed. + * For PF, this is determined by whether or not a MINI_QUARTER skyline exists. + */ +NvBool +kmigmgrIsCTSAlignmentRequired_PF +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager +) +{ + const NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO *pUnused; + + // CTS alignment is always required when a unique MINI_QUARTER is present + return (kmigmgrGetSkylineFromSize(pGpu, pKernelMIGManager, + NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_QUARTER, &pUnused) == NV_OK); +} + +/*! @brief This function determines whether or not CTS alignment and slot requirements are needed. + * For VF, this is determined by whether or not a MINI_QUARTER compute profile exists. + */ +NvBool +kmigmgrIsCTSAlignmentRequired_VF +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager +) +{ + NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE unused; + + // CTS alignment is always required when a unique MINI_QUARTER is present + return (kmigmgrGetComputeProfileFromSize(pGpu, pKernelMIGManager, + NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_QUARTER, &unused) == NV_OK); +} + +/*! + * @brief Returns the computeSize flag of a given CTS ID + */ +NvU32 +kmigmgrGetComputeSizeFromCTSId_IMPL +( + NvU32 ctsId +) +{ + NvU32 computeSize = kmigmgrGetNextComputeSize(NV_TRUE, KMIGMGR_COMPUTE_SIZE_INVALID); + + while (computeSize != KMIGMGR_COMPUTE_SIZE_INVALID) + { + NV_RANGE range = kmigmgrComputeProfileSizeToCTSIdRange(computeSize); + if ((range.lo <= ctsId) && (ctsId <= range.hi)) + break; + computeSize = kmigmgrGetNextComputeSize(NV_TRUE, computeSize); + } + + return computeSize; +} + +/*! + * @brief Returns Compute size of the smallest supported compute profile + */ +NvU32 +kmigmgrSmallestComputeProfileSize_IMPL +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager +) +{ + NvU32 computeSize = kmigmgrGetNextComputeSize(NV_FALSE, KMIGMGR_COMPUTE_SIZE_INVALID); + + while (computeSize != KMIGMGR_COMPUTE_SIZE_INVALID) + { + NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE unused; + if (kmigmgrGetComputeProfileFromSize(pGpu, pKernelMIGManager, computeSize, &unused) == NV_OK) + break; + computeSize = kmigmgrGetNextComputeSize(NV_FALSE, computeSize); + } + + return computeSize; +} + +/*! + * @brief Sets/resets various CTS tracking structures in a GPU instance + * based upon whether bInUse is set + * + * @param[IN] pKernelMIGGpuInstance + * @param[IN] ctsId CTS ID to be set/reset + * @param[IN] grId Global GR engine targeted for CTS ID + * @param[IN] bInUse Flag indicating to set/reset cts tracking structures + * + */ +void +kmigmgrSetCTSIdInUse_IMPL +( + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance, + NvU32 ctsId, + NvU32 grId, + NvBool bInUse +) +{ + NV_ASSERT_OR_RETURN_VOID(pKernelMIGGpuInstance != NULL); + + if (bInUse) + { + pKernelMIGGpuInstance->grCtsIdMap[grId] = ctsId; + + // Nothing to set in ctsIdInUseMask if KMIGMGR_CTSID_INVALID passed in + NV_ASSERT_OR_RETURN_VOID(ctsId != KMIGMGR_CTSID_INVALID); + + pKernelMIGGpuInstance->ctsIdsInUseMask |= NVBIT64(ctsId); + } + else + { + // + // Take CTS ID directly from gr mapping array to ensure both structures + // remain in-sync. + // + ctsId = pKernelMIGGpuInstance->grCtsIdMap[grId]; + + // Nothing to do if nothing was set + NV_CHECK_OR_RETURN_VOID(LEVEL_WARNING, ctsId != KMIGMGR_CTSID_INVALID); + + pKernelMIGGpuInstance->ctsIdsInUseMask &= ~NVBIT64(ctsId); + pKernelMIGGpuInstance->grCtsIdMap[grId] = KMIGMGR_CTSID_INVALID; + } +} + +/*! + * @brief Translates a spanStart and computeSize to the corresponding CTS ID. + * When an invalid compute size is passed in, this function will still + * return NV_OK, but populates an invalid CTS ID for use. + * + * @param[IN] pGpu + * @param[IN] pKernelMIGManager + * @param[IN] computeSize Compute size of CTS to get span offset of + * @param[IN] spanStart spanStart requested + * @param[OUT] pCtsId Output CTS ID in computeSize's range + * + */ +NV_STATUS +kmigmgrXlateSpanStartToCTSId_IMPL +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager, + NvU32 computeSize, + NvU32 spanStart, + NvU32 *pCtsId +) +{ + NV_RANGE computeSizeIdRange; + NvU64 computeSizeIdMask; + NvU64 slotBasisMask; + NvU32 slotsPerCTS; + + NV_ASSERT_OR_RETURN(pCtsId != NULL, NV_ERR_INVALID_ARGUMENT); + + // + // Initialize output to invalid CTS ID, as KMIGMGR_COMPUTE_SIZE_INVALID may have been passed in + // which is ok. It Is the callers rsponsibility to check for the CTS ID validitiy. + // + *pCtsId = KMIGMGR_CTSID_INVALID; + + NV_CHECK_OR_RETURN(LEVEL_WARNING, computeSize != KMIGMGR_COMPUTE_SIZE_INVALID, NV_OK); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kmigmgrGetSlotBasisMask(pGpu, pKernelMIGManager, &slotBasisMask)); + + // Validate that the spanStart does not exceed the basis slot count (which constitutes the acceptable span range) + NV_CHECK_OR_RETURN(LEVEL_ERROR, spanStart < nvPopCount64(slotBasisMask), NV_ERR_INVALID_ARGUMENT); + + computeSizeIdRange = kmigmgrComputeProfileSizeToCTSIdRange(computeSize); + + // Grab the first CTS ID for computeSize, as it doesn't really mater which one we choose here. + NV_ASSERT_OK(kmigmgrGetInvalidCTSIdMask(pGpu, pKernelMIGManager, computeSizeIdRange.lo, &computeSizeIdMask)); + + // slots per CTSID is number of basis IDs marked in the invalid mask for this ID + slotsPerCTS = nvPopCount64(computeSizeIdMask & slotBasisMask); + + if ((spanStart % slotsPerCTS) != 0) + { + NV_PRINTF(LEVEL_ERROR, "Compute span start of %d is not aligned\n", spanStart); + return NV_ERR_INVALID_ARGUMENT; + } + + *pCtsId = computeSizeIdRange.lo + (spanStart / slotsPerCTS); + + // The ID returned should be within the computeSize's range at this point + NV_ASSERT((computeSizeIdRange.lo <= *pCtsId) && (*pCtsId <= computeSizeIdRange.hi)); + + return NV_OK; +} + +/*! + * @brief Retrievies the mask of CTS IDs which are used to derive other properties + * such as spans, offsets, and capacities. + * + * @param[IN] pGpu + * @param[IN] pKernelMIGManager + * @param[OUT] computeSize Mask of all CTS IDs part of the profile slot basis + */ +NV_STATUS +kmigmgrGetSlotBasisMask_IMPL +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager, + NvU64 *pMask +) +{ + NV_RANGE slotBasisIdRange; + NvU32 slotBasisComputeSize; + + NV_CHECK_OR_RETURN(LEVEL_ERROR, pMask != NULL, NV_ERR_INVALID_ARGUMENT); + + slotBasisComputeSize = kmigmgrSmallestComputeProfileSize(pGpu, pKernelMIGManager); + slotBasisIdRange = kmigmgrComputeProfileSizeToCTSIdRange(slotBasisComputeSize); + + NV_ASSERT_OR_RETURN(!rangeIsEmpty(slotBasisIdRange), NV_ERR_INVALID_STATE); + + *pMask = DRF_SHIFTMASK64(slotBasisIdRange.hi:slotBasisIdRange.lo); + + return NV_OK; +} + +/*! + * @brief Translates a CTS ID to the corresponding spanStart of the CTS + * + * @param[IN] pGpu + * @param[IN] pKernelMIGManager + * @param[IN] ctsId + * + */ +NvU32 +kmigmgrGetSpanStartFromCTSId_IMPL +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager, + NvU32 ctsId +) +{ + NvU32 computeSize = kmigmgrGetComputeSizeFromCTSId(ctsId); + NV_RANGE computeSizeIdRange; + NvU64 computeSizeIdMask; + NvU64 slotBasisMask; + NvU32 slotsPerCTS; + + NV_CHECK_OR_RETURN(LEVEL_WARNING, computeSize != KMIGMGR_COMPUTE_SIZE_INVALID, 0); + + computeSizeIdRange = kmigmgrComputeProfileSizeToCTSIdRange(computeSize); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kmigmgrGetSlotBasisMask(pGpu, pKernelMIGManager, &slotBasisMask)); + + // Grab the first CTS ID for computeSize, as it doesn't really mater which one we choose here. + NV_ASSERT_OK(kmigmgrGetInvalidCTSIdMask(pGpu, pKernelMIGManager, computeSizeIdRange.lo, &computeSizeIdMask)); + + // slots per CTSID is number of basis IDs marked in the invalid mask for this ID + slotsPerCTS = nvPopCount64(computeSizeIdMask & slotBasisMask); + + return (ctsId - computeSizeIdRange.lo) * slotsPerCTS; +} + +/*! + * @brief Function checking whether the passed-in ctsId is available given the + * current states of ctsIdValidMask and ctsIdInUseMask + * + * @param[IN] pGpu + * @param[IN] pKernelMIGManager + * @param[IN] ctsIdValidMask Valid CTS ID mask to compare against + * @param[IN] ctsIdInUseMask Mask of CTS IDs which are marked as being used + * @param[IN] ctsid CTS ID to check + */ +NvBool +kmigmgrIsCTSIdAvailable_IMPL +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager, + NvU64 ctsIdValidMask, + NvU64 ctsIdInUseMask, + NvU32 ctsId +) +{ + NvU64 invalidMask = 0x0; + NvU32 i; + + FOR_EACH_INDEX_IN_MASK(64, i, ctsIdInUseMask) + { + NvU64 mask; + + NV_ASSERT_OK(kmigmgrGetInvalidCTSIdMask(pGpu, pKernelMIGManager, i, &mask)); + + invalidMask |= mask; + } + FOR_EACH_INDEX_IN_MASK_END; + return !!((ctsIdValidMask & ~invalidMask) & NVBIT64(ctsId)); +} + diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/ampere/kern_gmmu_fmt_ga10x.c b/src/nvidia/src/kernel/gpu/mmu/arch/ampere/kern_gmmu_fmt_ga10x.c index 449eff421..7b656e1a1 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/ampere/kern_gmmu_fmt_ga10x.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/ampere/kern_gmmu_fmt_ga10x.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERN_GMMU_H_PRIVATE_ACCESS_ALLOWED + #include "gpu/mmu/kern_gmmu.h" #include "mmu/gmmu_fmt.h" diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/ampere/kern_gmmu_ga100.c b/src/nvidia/src/kernel/gpu/mmu/arch/ampere/kern_gmmu_ga100.c index a3cf631d8..a6abc17fb 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/ampere/kern_gmmu_ga100.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/ampere/kern_gmmu_ga100.c @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERN_GMMU_H_PRIVATE_ACCESS_ALLOWED + #include "gpu/mmu/kern_gmmu.h" #include "gpu/mem_mgr/mem_mgr.h" #include "gpu/mem_mgr/mem_utils.h" diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_fmt_gh10x.c b/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_fmt_gh10x.c index 3a24501b8..31a24888c 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_fmt_gh10x.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_fmt_gh10x.c @@ -21,6 +21,7 @@ * DEALINGS IN THE SOFTWARE. */ #if !defined(SRT_BUILD) +#define NVOC_KERN_GMMU_H_PRIVATE_ACCESS_ALLOWED #include "gpu/mmu/kern_gmmu.h" #endif #include "mmu/gmmu_fmt.h" @@ -59,54 +60,61 @@ void kgmmuFmtInitLevels_GH10X(KernelGmmu *pKernelGmmu, NV_ASSERT_OR_RETURN_VOID(numLevels >= 7); // Page directory 4 (root). - pLevels[0].virtAddrBitHi = 56; - pLevels[0].virtAddrBitLo = 56; - pLevels[0].entrySize = NV_MMU_VER3_PDE__SIZE; - pLevels[0].numSubLevels = 1; - pLevels[0].subLevels = pLevels + 1; + pLevels[0].virtAddrBitHi = 56; + pLevels[0].virtAddrBitLo = 56; + pLevels[0].entrySize = NV_MMU_VER3_PDE__SIZE; + pLevels[0].numSubLevels = 1; + pLevels[0].subLevels = pLevels + 1; + pLevels[0].pageLevelIdTag = MMU_FMT_PT_SURF_ID_PD0; // Page directory 3. - pLevels[1].virtAddrBitHi = 55; - pLevels[1].virtAddrBitLo = 47; - pLevels[1].entrySize = NV_MMU_VER3_PDE__SIZE; - pLevels[1].numSubLevels = 1; - pLevels[1].subLevels = pLevels + 2; + pLevels[1].virtAddrBitHi = 55; + pLevels[1].virtAddrBitLo = 47; + pLevels[1].entrySize = NV_MMU_VER3_PDE__SIZE; + pLevels[1].numSubLevels = 1; + pLevels[1].subLevels = pLevels + 2; + pLevels[1].pageLevelIdTag = MMU_FMT_PT_SURF_ID_PD1; // Page directory 2. - pLevels[2].virtAddrBitHi = 46; - pLevels[2].virtAddrBitLo = 38; - pLevels[2].entrySize = NV_MMU_VER3_PDE__SIZE; - pLevels[2].numSubLevels = 1; - pLevels[2].subLevels = pLevels + 3; + pLevels[2].virtAddrBitHi = 46; + pLevels[2].virtAddrBitLo = 38; + pLevels[2].entrySize = NV_MMU_VER3_PDE__SIZE; + pLevels[2].numSubLevels = 1; + pLevels[2].subLevels = pLevels + 3; + pLevels[2].pageLevelIdTag = MMU_FMT_PT_SURF_ID_PD2; // Page directory 1. - pLevels[3].virtAddrBitHi = 37; - pLevels[3].virtAddrBitLo = 29; - pLevels[3].entrySize = NV_MMU_VER3_PDE__SIZE; - pLevels[3].numSubLevels = 1; - pLevels[3].subLevels = pLevels + 4; + pLevels[3].virtAddrBitHi = 37; + pLevels[3].virtAddrBitLo = 29; + pLevels[3].entrySize = NV_MMU_VER3_PDE__SIZE; + pLevels[3].numSubLevels = 1; + pLevels[3].subLevels = pLevels + 4; // Page directory 1 can hold a PTE pointing to a 512MB Page - pLevels[3].bPageTable = NV_TRUE; + pLevels[3].bPageTable = NV_TRUE; + pLevels[3].pageLevelIdTag = MMU_FMT_PT_SURF_ID_PD3; // Page directory 0. - pLevels[4].virtAddrBitHi = 28; - pLevels[4].virtAddrBitLo = 21; - pLevels[4].entrySize = NV_MMU_VER3_DUAL_PDE__SIZE; - pLevels[4].numSubLevels = 2; - pLevels[4].bPageTable = NV_TRUE; - pLevels[4].subLevels = pLevels + 5; + pLevels[4].virtAddrBitHi = 28; + pLevels[4].virtAddrBitLo = 21; + pLevels[4].entrySize = NV_MMU_VER3_DUAL_PDE__SIZE; + pLevels[4].numSubLevels = 2; + pLevels[4].bPageTable = NV_TRUE; + pLevels[4].subLevels = pLevels + 5; + pLevels[4].pageLevelIdTag = MMU_FMT_PT_SURF_ID_PD4; // Big page table. - pLevels[5].virtAddrBitHi = 20; - pLevels[5].virtAddrBitLo = (NvU8)bigPageShift; - pLevels[5].entrySize = NV_MMU_VER3_PTE__SIZE; - pLevels[5].bPageTable = NV_TRUE; + pLevels[5].virtAddrBitHi = 20; + pLevels[5].virtAddrBitLo = (NvU8)bigPageShift; + pLevels[5].entrySize = NV_MMU_VER3_PTE__SIZE; + pLevels[5].bPageTable = NV_TRUE; + pLevels[5].pageLevelIdTag = MMU_FMT_PT_SURF_ID_PT_BIG; // Small page table. - pLevels[6].virtAddrBitHi = 20; - pLevels[6].virtAddrBitLo = 12; - pLevels[6].entrySize = NV_MMU_VER3_PTE__SIZE; - pLevels[6].bPageTable = NV_TRUE; + pLevels[6].virtAddrBitHi = 20; + pLevels[6].virtAddrBitLo = 12; + pLevels[6].entrySize = NV_MMU_VER3_PTE__SIZE; + pLevels[6].bPageTable = NV_TRUE; + pLevels[5].pageLevelIdTag = MMU_FMT_PT_SURF_ID_PT_4K; } void kgmmuFmtInitPdeMulti_GH10X(KernelGmmu *pKernelGmmu, diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_gh100.c b/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_gh100.c index 1c5e0dafd..bb47d1d37 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_gh100.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_gh100.c @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERN_GMMU_H_PRIVATE_ACCESS_ALLOWED + #include "gpu/mmu/kern_gmmu.h" #include "gpu/mem_mgr/mem_mgr.h" diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_fmt_gm10x.c b/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_fmt_gm10x.c index dc2e34550..8b90d81f8 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_fmt_gm10x.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_fmt_gm10x.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -22,6 +22,7 @@ */ #if !defined(SRT_BUILD) +#define NVOC_KERN_GMMU_H_PRIVATE_ACCESS_ALLOWED #include "gpu/mmu/kern_gmmu.h" #endif #include "mmu/gmmu_fmt.h" @@ -57,23 +58,26 @@ void kgmmuFmtInitLevels_GM10X(KernelGmmu *pKernelGmmu, NV_ASSERT_OR_RETURN_VOID(bigPageShift == 16 || bigPageShift == 17); // Page directory (root). - pLevels[0].virtAddrBitHi = 39; - pLevels[0].virtAddrBitLo = (NvU8)bigPageShift + 10; - pLevels[0].entrySize = NV_MMU_PDE__SIZE; - pLevels[0].numSubLevels = 2; - pLevels[0].subLevels = pLevels + 1; + pLevels[0].virtAddrBitHi = 39; + pLevels[0].virtAddrBitLo = (NvU8)bigPageShift + 10; + pLevels[0].entrySize = NV_MMU_PDE__SIZE; + pLevels[0].numSubLevels = 2; + pLevels[0].subLevels = pLevels + 1; + pLevels[0].pageLevelIdTag = MMU_FMT_PT_SURF_ID_PD0; // Big page table. - pLevels[1].virtAddrBitHi = pLevels[0].virtAddrBitLo - 1; - pLevels[1].virtAddrBitLo = (NvU8)bigPageShift; - pLevels[1].entrySize = NV_MMU_PTE__SIZE; - pLevels[1].bPageTable = NV_TRUE; + pLevels[1].virtAddrBitHi = pLevels[0].virtAddrBitLo - 1; + pLevels[1].virtAddrBitLo = (NvU8)bigPageShift; + pLevels[1].entrySize = NV_MMU_PTE__SIZE; + pLevels[1].bPageTable = NV_TRUE; + pLevels[1].pageLevelIdTag = MMU_FMT_PT_SURF_ID_PT_BIG; // Small page table. - pLevels[2].virtAddrBitHi = pLevels[0].virtAddrBitLo - 1; - pLevels[2].virtAddrBitLo = 12; - pLevels[2].entrySize = NV_MMU_PTE__SIZE; - pLevels[2].bPageTable = NV_TRUE; + pLevels[2].virtAddrBitHi = pLevels[0].virtAddrBitLo - 1; + pLevels[2].virtAddrBitLo = 12; + pLevels[2].entrySize = NV_MMU_PTE__SIZE; + pLevels[2].bPageTable = NV_TRUE; + pLevels[2].pageLevelIdTag = MMU_FMT_PT_SURF_ID_PT_4K; } void kgmmuFmtInitPdeMulti_GM10X(KernelGmmu *pKernelGmmu, diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_fmt_gm20x.c b/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_fmt_gm20x.c index 51eda1ee6..adc634fc1 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_fmt_gm20x.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_fmt_gm20x.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -22,6 +22,7 @@ */ #if !defined(SRT_BUILD) +#define NVOC_KERN_GMMU_H_PRIVATE_ACCESS_ALLOWED #include "gpu/mmu/kern_gmmu.h" #endif #include "mmu/gmmu_fmt.h" diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm107.c b/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm107.c index b346639a2..478f61930 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm107.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm107.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERN_GMMU_H_PRIVATE_ACCESS_ALLOWED + #include "gpu/mmu/kern_gmmu.h" #include "gpu/bus/kern_bus.h" @@ -313,9 +315,11 @@ kgmmuGetHwPteApertureFromMemdesc_GM107 aperture = NV_MMU_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY; } break; - case ADDR_FBMEM: - case ADDR_FABRIC: case ADDR_FABRIC_V2: + case ADDR_FABRIC_MC: + aperture = NV_MMU_PTE_APERTURE_PEER_MEMORY; + break; + case ADDR_FBMEM: aperture = NV_MMU_PTE_APERTURE_VIDEO_MEMORY; break; default: diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm200.c b/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm200.c index 139ac6c10..26d561536 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm200.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm200.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERN_GMMU_H_PRIVATE_ACCESS_ALLOWED + #include "gpu/mmu/kern_gmmu.h" /*! diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/pascal/kern_gmmu_fmt_gp10x.c b/src/nvidia/src/kernel/gpu/mmu/arch/pascal/kern_gmmu_fmt_gp10x.c index f790df91c..3008b99a3 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/pascal/kern_gmmu_fmt_gp10x.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/pascal/kern_gmmu_fmt_gp10x.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -22,6 +22,7 @@ */ #if !defined(SRT_BUILD) +#define NVOC_KERN_GMMU_H_PRIVATE_ACCESS_ALLOWED #include "gpu/mmu/kern_gmmu.h" #endif #include "mmu/gmmu_fmt.h" @@ -55,45 +56,52 @@ void kgmmuFmtInitLevels_GP10X(KernelGmmu *pKernelGmmu, NV_ASSERT_OR_RETURN_VOID(bigPageShift == 16 || bigPageShift == 17); // Page directory 3 (root). - pLevels[0].virtAddrBitHi = 48; - pLevels[0].virtAddrBitLo = 47; - pLevels[0].entrySize = NV_MMU_VER2_PDE__SIZE; - pLevels[0].numSubLevels = 1; - pLevels[0].subLevels = pLevels + 1; + pLevels[0].virtAddrBitHi = 48; + pLevels[0].virtAddrBitLo = 47; + pLevels[0].entrySize = NV_MMU_VER2_PDE__SIZE; + pLevels[0].numSubLevels = 1; + pLevels[0].subLevels = pLevels + 1; + pLevels[0].pageLevelIdTag = MMU_FMT_PT_SURF_ID_PD0; // Page directory 2. - pLevels[1].virtAddrBitHi = 46; - pLevels[1].virtAddrBitLo = 38; - pLevels[1].entrySize = NV_MMU_VER2_PDE__SIZE; - pLevels[1].numSubLevels = 1; - pLevels[1].subLevels = pLevels + 2; + pLevels[1].virtAddrBitHi = 46; + pLevels[1].virtAddrBitLo = 38; + pLevels[1].entrySize = NV_MMU_VER2_PDE__SIZE; + pLevels[1].numSubLevels = 1; + pLevels[1].subLevels = pLevels + 2; + pLevels[1].pageLevelIdTag = MMU_FMT_PT_SURF_ID_PD1; // Page directory 1. - pLevels[2].virtAddrBitHi = 37; - pLevels[2].virtAddrBitLo = 29; - pLevels[2].entrySize = NV_MMU_VER2_PDE__SIZE; - pLevels[2].numSubLevels = 1; - pLevels[2].subLevels = pLevels + 3; + pLevels[2].virtAddrBitHi = 37; + pLevels[2].virtAddrBitLo = 29; + pLevels[2].entrySize = NV_MMU_VER2_PDE__SIZE; + pLevels[2].numSubLevels = 1; + pLevels[2].subLevels = pLevels + 3; + pLevels[2].pageLevelIdTag = MMU_FMT_PT_SURF_ID_PD2; // Page directory 0. - pLevels[3].virtAddrBitHi = 28; - pLevels[3].virtAddrBitLo = 21; - pLevels[3].entrySize = NV_MMU_VER2_DUAL_PDE__SIZE; - pLevels[3].numSubLevels = 2; - pLevels[3].bPageTable = NV_TRUE; - pLevels[3].subLevels = pLevels + 4; + pLevels[3].virtAddrBitHi = 28; + pLevels[3].virtAddrBitLo = 21; + pLevels[3].entrySize = NV_MMU_VER2_DUAL_PDE__SIZE; + pLevels[3].numSubLevels = 2; + pLevels[3].bPageTable = NV_TRUE; + pLevels[3].subLevels = pLevels + 4; + pLevels[3].pageLevelIdTag = MMU_FMT_PT_SURF_ID_PD3; + // Big page table. - pLevels[4].virtAddrBitHi = 20; - pLevels[4].virtAddrBitLo = (NvU8)bigPageShift; - pLevels[4].entrySize = NV_MMU_VER2_PTE__SIZE; - pLevels[4].bPageTable = NV_TRUE; + pLevels[4].virtAddrBitHi = 20; + pLevels[4].virtAddrBitLo = (NvU8)bigPageShift; + pLevels[4].entrySize = NV_MMU_VER2_PTE__SIZE; + pLevels[4].bPageTable = NV_TRUE; + pLevels[4].pageLevelIdTag = MMU_FMT_PT_SURF_ID_PT_BIG; // Small page table. - pLevels[5].virtAddrBitHi = 20; - pLevels[5].virtAddrBitLo = 12; - pLevels[5].entrySize = NV_MMU_VER2_PTE__SIZE; - pLevels[5].bPageTable = NV_TRUE; + pLevels[5].virtAddrBitHi = 20; + pLevels[5].virtAddrBitLo = 12; + pLevels[5].entrySize = NV_MMU_VER2_PTE__SIZE; + pLevels[5].bPageTable = NV_TRUE; + pLevels[5].pageLevelIdTag = MMU_FMT_PT_SURF_ID_PT_4K; } void kgmmuFmtInitPdeMulti_GP10X(KernelGmmu *pKernelGmmu, diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/pascal/kern_gmmu_gp100.c b/src/nvidia/src/kernel/gpu/mmu/arch/pascal/kern_gmmu_gp100.c index 659027e99..0c03b582e 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/pascal/kern_gmmu_gp100.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/pascal/kern_gmmu_gp100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERN_GMMU_H_PRIVATE_ACCESS_ALLOWED + #include "gpu/mmu/kern_gmmu.h" #include "gpu/gpu.h" diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_fmt_tu10x.c b/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_fmt_tu10x.c index e4033fe83..4952a5809 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_fmt_tu10x.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_fmt_tu10x.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -22,6 +22,7 @@ */ #if !defined(SRT_BUILD) +#define NVOC_KERN_GMMU_H_PRIVATE_ACCESS_ALLOWED #include "gpu/mmu/kern_gmmu.h" #endif #include "mmu/gmmu_fmt.h" diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_tu102.c b/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_tu102.c index d5ce373c1..045c5ce0e 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_tu102.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_tu102.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -26,6 +26,8 @@ * @brief TURING specific HAL MMU routines reside in this file */ +#define NVOC_KERN_GMMU_H_PRIVATE_ACCESS_ALLOWED + #include "gpu/mmu/kern_gmmu.h" #include "gpu/gpu.h" #include "kernel/gpu/intr/intr.h" @@ -373,14 +375,16 @@ kgmmuReadFaultBufferPutPtr_TU102 OBJGPU *pGpu, KernelGmmu *pKernelGmmu, NvU32 index, - NvU32 *pPutOffset + NvU32 *pPutOffset, + THREAD_STATE_NODE *pThreadState ) { NvU32 val; NV_ASSERT_OR_RETURN((index < NUM_FAULT_BUFFERS), NV_ERR_INVALID_ARGUMENT); - val = GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_PUT(index)); + val = GPU_VREG_RD32_EX(pGpu, NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_PUT(index), pThreadState); *pPutOffset = DRF_VAL(_VIRTUAL_FUNCTION_PRIV, _MMU_FAULT_BUFFER_PUT, _PTR, val); + return NV_OK; } @@ -404,3 +408,22 @@ kgmmuIsNonReplayableFaultPending_TU102 NvU32 pending = GPU_VREG_RD32_EX(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF(reg), NULL /* threadstate */); return pending & NVBIT(bit); } + +/*! + * @brief Clear non replayable fault interrupt. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelGmmu KernelGmmu pointer + * @param[in] pThreadState THREAD_STATE_NODE pointer + */ +void +kgmmuClearNonReplayableFaultIntr_TU102 +( + POBJGPU pGpu, + KernelGmmu *pKernelGmmu, + THREAD_STATE_NODE *pThreadState +) +{ + Intr *pIntr = GPU_GET_INTR(pGpu); + intrClearLeafVector_HAL(pGpu, pIntr, NV_PFB_PRI_MMU_INT_VECTOR_FAULT_NOTIFY_NON_REPLAYABLE, pThreadState); +} diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/volta/kern_gmmu_gv100.c b/src/nvidia/src/kernel/gpu/mmu/arch/volta/kern_gmmu_gv100.c index d06daf970..c55e75202 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/volta/kern_gmmu_gv100.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/volta/kern_gmmu_gv100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERN_GMMU_H_PRIVATE_ACCESS_ALLOWED + #include "gpu/mmu/kern_gmmu.h" #include "gpu/gpu.h" #include "kernel/gpu/rc/kernel_rc.h" @@ -399,7 +401,7 @@ kgmmuReportFaultBufferOverflow_GV100 faultBufferGet = DRF_VAL(_PFB_PRI, _MMU_FAULT_BUFFER_GET, _PTR, faultBufferGet); kgmmuReadFaultBufferPutPtr_HAL(pGpu, pKernelGmmu, NON_REPLAYABLE_FAULT_BUFFER, - &faultBufferPut); + &faultBufferPut, NULL); faultBufferPut = DRF_VAL(_PFB_PRI, _MMU_FAULT_BUFFER_PUT, _PTR, faultBufferPut); faultBufferSize = kgmmuReadMmuFaultBufferSize_HAL(pGpu, pKernelGmmu, NON_REPLAYABLE_FAULT_BUFFER, GPU_GFID_PF); diff --git a/src/nvidia/src/kernel/gpu/mmu/fault_buffer_ctrl.c b/src/nvidia/src/kernel/gpu/mmu/fault_buffer_ctrl.c index 20b753ca2..037c9cfe5 100644 --- a/src/nvidia/src/kernel/gpu/mmu/fault_buffer_ctrl.c +++ b/src/nvidia/src/kernel/gpu/mmu/fault_buffer_ctrl.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERN_GMMU_H_PRIVATE_ACCESS_ALLOWED + #include "core/core.h" #include "gpu/mmu/kern_gmmu.h" diff --git a/src/nvidia/src/kernel/gpu/mmu/gmmu_trace.c b/src/nvidia/src/kernel/gpu/mmu/gmmu_trace.c index 1f57ba860..19df2a333 100644 --- a/src/nvidia/src/kernel/gpu/mmu/gmmu_trace.c +++ b/src/nvidia/src/kernel/gpu/mmu/gmmu_trace.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERN_GMMU_H_PRIVATE_ACCESS_ALLOWED + #include "mmu/gmmu_fmt.h" #include "gpu/mmu/kern_gmmu.h" @@ -280,7 +282,8 @@ _gmmuPrintPde PRINT_FIELD_32("PdePcf=%d", pFmtPde, PdePcf, pGmmuEntry); pdePcfHw = nvFieldGet32(&pFmtPde->fldPdePcf, pGmmuEntry->v8); - NV_ASSERT(kgmmuTranslatePdePcfFromHw_HAL(GPU_GET_KERNEL_GMMU(pGpu), + NV_CHECK(LEVEL_INFO, + kgmmuTranslatePdePcfFromHw_HAL(GPU_GET_KERNEL_GMMU(pGpu), pdePcfHw, aperture, &pdePcfSw) == NV_OK); diff --git a/src/nvidia/src/kernel/gpu/mmu/gmmu_walk.c b/src/nvidia/src/kernel/gpu/mmu/gmmu_walk.c index 1a93c164f..af0ccc56e 100644 --- a/src/nvidia/src/kernel/gpu/mmu/gmmu_walk.c +++ b/src/nvidia/src/kernel/gpu/mmu/gmmu_walk.c @@ -26,6 +26,7 @@ #include "mem_mgr/gpu_vaspace.h" #include "gpu/mmu/kern_gmmu.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" +#include "gpu/mem_mgr/mem_desc.h" #include "nvRmReg.h" // NV_REG_STR_RM_* #include "mmu/gmmu_fmt.h" @@ -350,6 +351,7 @@ _gmmuWalkCBLevelAlloc status = _gmmuScrubMemDesc(pGpu, pMemDescTemp); } + memdescSetName(pGpu, pMemDescTemp, NV_RM_SURF_NAME_PAGE_TABLE, mmuFmtConvertLevelIdToSuffix(pLevelFmt)); break; } j++; diff --git a/src/nvidia/src/kernel/gpu/mmu/kern_gmmu.c b/src/nvidia/src/kernel/gpu/mmu/kern_gmmu.c index 232a6dfac..0919c390a 100644 --- a/src/nvidia/src/kernel/gpu/mmu/kern_gmmu.c +++ b/src/nvidia/src/kernel/gpu/mmu/kern_gmmu.c @@ -28,6 +28,8 @@ * ******************************************************************************/ +#define NVOC_KERN_GMMU_H_PRIVATE_ACCESS_ALLOWED + #include "gpu/bif/kernel_bif.h" #include "gpu/mmu/kern_gmmu.h" #include "gpu/bus/kern_bus.h" @@ -162,7 +164,7 @@ fail: /* * Initialize the Kernel GMMU state. - * + * * @param pGpu * @param pKernelGmmu */ @@ -186,10 +188,72 @@ NV_STATUS kgmmuStateInitLocked_IMPL return status; } +static NV_STATUS +_kgmmuCreateGlobalVASpace +( + POBJGPU pGpu, + KernelGmmu *pKernelGmmu, + NvU32 flags +) +{ + NvU32 constructFlags = VASPACE_FLAGS_NONE; + POBJVASPACE pGlobalVAS = NULL; + NV_STATUS rmStatus; + POBJGPUGRP pGpuGrp = NULL; + + // Bail out early on sleep/suspend cases + if (flags & GPU_STATE_FLAGS_PRESERVING) + return NV_OK; + if (!gpumgrIsParentGPU(pGpu)) + return NV_OK; + + // + // We create the device vaspace at this point. Assemble the flags needed + // for construction. + // + + // Allow PTE in SYS + constructFlags |= VASPACE_FLAGS_RETRY_PTE_ALLOC_IN_SYS; + + constructFlags |= VASPACE_FLAGS_DEFAULT_PARAMS; + constructFlags |= VASPACE_FLAGS_DEFAULT_SIZE; + constructFlags |= DRF_DEF(_VASPACE, _FLAGS, _BIG_PAGE_SIZE, _DEFAULT); + + pGpuGrp = gpumgrGetGpuGrpFromGpu(pGpu); + NV_ASSERT_OR_RETURN(pGpuGrp != NULL, NV_ERR_INVALID_DATA); + + rmStatus = gpugrpCreateGlobalVASpace(pGpuGrp, pGpu, + FERMI_VASPACE_A, + 0, 0, + constructFlags, + &pGlobalVAS); + NV_ASSERT_OR_RETURN((NV_OK == rmStatus), rmStatus); + + return NV_OK; +} + +static NV_STATUS +_kgmmuDestroyGlobalVASpace +( + POBJGPU pGpu, + KernelGmmu *pKernelGmmu, + NvU32 flags +) +{ + POBJGPUGRP pGpuGrp = NULL; + + if (flags & GPU_STATE_FLAGS_PRESERVING) + return NV_OK; + + pGpuGrp = gpumgrGetGpuGrpFromGpu(pGpu); + return gpugrpDestroyGlobalVASpace(pGpuGrp, pGpu); +} + /* - * State Post Load + * Helper function to enable ComputePeerMode */ -NV_STATUS kgmmuStatePostLoad_IMPL +NV_STATUS +kgmmuEnableComputePeerAddressing_IMPL ( OBJGPU *pGpu, KernelGmmu *pKernelGmmu, @@ -222,12 +286,72 @@ NV_STATUS kgmmuStatePostLoad_IMPL status = pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, - NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR, + NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR, NULL, 0); } return status; } +/* + * State Post Load + */ +NV_STATUS kgmmuStatePostLoad_IMPL +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvU32 flags +) +{ + NV_STATUS status = NV_OK; + + status = _kgmmuCreateGlobalVASpace(pGpu, pKernelGmmu, flags); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to create GVASpace, status:%x\n", + status); + return status; + } + + status = kgmmuEnableComputePeerAddressing(pGpu, pKernelGmmu, flags); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to enable compute peer addressing, status:%x\n", + status); + return status; + } + + return status; +} + +/* + * State Pre Unload + */ +NV_STATUS +kgmmuStatePreUnload_IMPL +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvU32 flags +) +{ + NV_STATUS status = NV_OK; + + status = _kgmmuDestroyGlobalVASpace(pGpu, pKernelGmmu, flags); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to destory GVASpace, status:%x\n", + status); + return status; + } + return status; +} + /*! * KernelGmmu destructor * @@ -364,6 +488,7 @@ _kgmmuInitRegistryOverrides(OBJGPU *pGpu, KernelGmmu *pKernelGmmu) data); pKernelGmmu->setProperty(pKernelGmmu, PDB_PROP_KGMMU_FAULT_BUFFER_DISABLED, data); } + } GMMU_APERTURE @@ -488,7 +613,7 @@ kgmmuGetStaticInfo_IMPL * * @param pGpu * @param pKernelGmmu - * @param[out] pStaticInfo pointer to the static info init on Physical driver. + * @param[out] pStaticInfo pointer to the static info init on Physical driver. */ NV_STATUS kgmmuInitStaticInfo_KERNEL @@ -559,10 +684,10 @@ kgmmuFmtIsBigPageSizeSupported_IMPL(KernelGmmu *pKernelGmmu, NvU64 bigPageSize) /*! * @bried Returns the latest supported MMU fmt. - * + * * @param[in] pGpu OBJGPU pointer * @param[in] pKernelGmmu KernelGmmu pointer - * + * * @returns const GMMU_FMT* */ const GMMU_FMT* @@ -923,6 +1048,7 @@ kgmmuFaultBufferAlloc_IMPL NV_STATUS status; MEMORY_DESCRIPTOR *pMemDesc = NULL; struct HW_FAULT_BUFFER *pFaultBuffer; + const char *name = (index == REPLAYABLE_FAULT_BUFFER ? NV_RM_SURF_NAME_REPLAYABLE_FAULT_BUFFER : NV_RM_SURF_NAME_NONREPLAYABLE_FAULT_BUFFER); NV_ASSERT_OR_RETURN((index < NUM_FAULT_BUFFERS), NV_ERR_INVALID_ARGUMENT); @@ -945,6 +1071,8 @@ kgmmuFaultBufferAlloc_IMPL return status; } + memdescSetName(pGpu, pMemDesc, name, NULL); + pFaultBuffer->faultBufferSize = faultBufferSize; pFaultBuffer->pFaultBufferMemDesc = pMemDesc; @@ -1046,7 +1174,7 @@ kgmmuFaultBufferReplayableAllocate_IMPL pGpu->hInternalSubdevice, NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_FAULT_BUFFER, pParams, sizeof(*pParams)); - + portMemFree(pParams); if (status != NV_OK) { @@ -1757,7 +1885,7 @@ kgmmuInstBlkInit_IMPL if (!pInstBlkParams->bDeferFlush) { - kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_USE_PCIE_READ + kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_USE_PCIE_READ | kbusGetFlushAperture(pKernelBus, memdescGetAddressSpace(pInstBlkDesc))); } @@ -1774,8 +1902,8 @@ kgmmuGetExternalAllocAperture_IMPL { case ADDR_FBMEM: return GMMU_APERTURE_VIDEO; - case ADDR_FABRIC: case ADDR_FABRIC_V2: + case ADDR_FABRIC_MC: return GMMU_APERTURE_PEER; case ADDR_SYSMEM: case ADDR_VIRTUAL: @@ -1825,12 +1953,12 @@ kgmmuRegisterIntrService_IMPL ) { NvU32 engineIdx; - + static NvU16 engineIdxList[] = { MC_ENGINE_IDX_REPLAYABLE_FAULT, MC_ENGINE_IDX_REPLAYABLE_FAULT_ERROR, }; - + for (NvU32 tableIdx = 0; tableIdx < NV_ARRAY_ELEMENTS32(engineIdxList); tableIdx++) { engineIdx = engineIdxList[tableIdx]; @@ -1903,7 +2031,6 @@ kgmmuServiceInterrupt_IMPL * * @returns none */ - void kgmmuExtractPteInfo_IMPL ( @@ -2090,3 +2217,24 @@ kgmmuExtractPteInfo_IMPL pPteInfo->pteFlags = FLD_SET_DRF(0080_CTRL, _DMA_PTE_INFO, _PARAMS_FLAGS_COMPTAGS, _NONE, pPteInfo->pteFlags); } } + +NvS32* +kgmmuGetFatalFaultIntrPendingState_IMPL +( + KernelGmmu *pKernelGmmu, + NvU8 gfid +) +{ + return &pKernelGmmu->mmuFaultBuffer[gfid].fatalFaultIntrPending; +} + +struct HW_FAULT_BUFFER* +kgmmuGetHwFaultBufferPtr_IMPL +( + KernelGmmu *pKernelGmmu, + NvU8 gfid, + NvU8 faultBufferIndex +) +{ + return &pKernelGmmu->mmuFaultBuffer[gfid].hwFaultBuffers[faultBufferIndex]; +} diff --git a/src/nvidia/src/kernel/gpu/mmu/mmu_fault_buffer.c b/src/nvidia/src/kernel/gpu/mmu/mmu_fault_buffer.c index f7b5ef303..438ebfc02 100644 --- a/src/nvidia/src/kernel/gpu/mmu/mmu_fault_buffer.c +++ b/src/nvidia/src/kernel/gpu/mmu/mmu_fault_buffer.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2010-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERN_GMMU_H_PRIVATE_ACCESS_ALLOWED + #include "core/core.h" #include "os/os.h" #include "gpu/mmu/kern_gmmu.h" diff --git a/src/nvidia/src/kernel/gpu/mmu/mmu_fault_buffer_ctrl.c b/src/nvidia/src/kernel/gpu/mmu/mmu_fault_buffer_ctrl.c index cc5e27da7..d9a7197f4 100644 --- a/src/nvidia/src/kernel/gpu/mmu/mmu_fault_buffer_ctrl.c +++ b/src/nvidia/src/kernel/gpu/mmu/mmu_fault_buffer_ctrl.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ +#define NVOC_KERN_GMMU_H_PRIVATE_ACCESS_ALLOWED + #include "core/core.h" #include "gpu/mmu/kern_gmmu.h" diff --git a/src/nvidia/src/kernel/gpu/mmu/mmu_trace.c b/src/nvidia/src/kernel/gpu/mmu/mmu_trace.c index a46bb718a..9b2b6fc89 100644 --- a/src/nvidia/src/kernel/gpu/mmu/mmu_trace.c +++ b/src/nvidia/src/kernel/gpu/mmu/mmu_trace.c @@ -21,7 +21,7 @@ * DEALINGS IN THE SOFTWARE. */ -/***************************** HW State Rotuines ***************************\ +/***************************** HW State Routines ***************************\ * * * Memory Manager Object Function Definitions. * * * diff --git a/src/nvidia/src/kernel/gpu/nvdec/kernel_nvdec_engdesc.c b/src/nvidia/src/kernel/gpu/nvdec/kernel_nvdec_engdesc.c index c1e01389e..f28662306 100644 --- a/src/nvidia/src/kernel/gpu/nvdec/kernel_nvdec_engdesc.c +++ b/src/nvidia/src/kernel/gpu/nvdec/kernel_nvdec_engdesc.c @@ -96,6 +96,7 @@ nvdecGetEngineDescFromAllocParams { KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); MIG_INSTANCE_REF ref; + RM_ENGINE_TYPE rmEngineType; NV_ASSERT_OK( kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, @@ -103,9 +104,9 @@ nvdecGetEngineDescFromAllocParams NV_ASSERT_OK( kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, - NV2080_ENGINE_TYPE_NVDEC(engineInstance), - &engineInstance)); - return ENG_NVDEC(NV2080_ENGINE_TYPE_NVDEC_IDX(engineInstance)); + RM_ENGINE_TYPE_NVDEC(engineInstance), + &rmEngineType)); + return ENG_NVDEC(RM_ENGINE_TYPE_NVDEC_IDX(rmEngineType)); } // Get the right class as per engine instance. diff --git a/src/nvidia/src/kernel/gpu/nvenc/kernel_nvenc_engdesc.c b/src/nvidia/src/kernel/gpu/nvenc/kernel_nvenc_engdesc.c index e95a4726c..cbd600c81 100644 --- a/src/nvidia/src/kernel/gpu/nvenc/kernel_nvenc_engdesc.c +++ b/src/nvidia/src/kernel/gpu/nvenc/kernel_nvenc_engdesc.c @@ -84,6 +84,7 @@ msencGetEngineDescFromAllocParams(OBJGPU *pGpu, NvU32 externalClassId, void *pAl { KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); MIG_INSTANCE_REF ref; + RM_ENGINE_TYPE rmEngineType; NV_ASSERT_OK( kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, @@ -91,9 +92,9 @@ msencGetEngineDescFromAllocParams(OBJGPU *pGpu, NvU32 externalClassId, void *pAl NV_ASSERT_OK( kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, - NV2080_ENGINE_TYPE_NVENC(engineInstance), - &engineInstance)); - return ENG_MSENC(NV2080_ENGINE_TYPE_NVENC_IDX(engineInstance)); + RM_ENGINE_TYPE_NVENC(engineInstance), + &rmEngineType)); + return ENG_MSENC(RM_ENGINE_TYPE_NVENC_IDX(rmEngineType)); } // Get the right class as per engine instance. diff --git a/src/nvidia/src/kernel/gpu/nvjpg/kernel_nvjpg_engdesc.c b/src/nvidia/src/kernel/gpu/nvjpg/kernel_nvjpg_engdesc.c index 7be2d38ae..8eb375c68 100644 --- a/src/nvidia/src/kernel/gpu/nvjpg/kernel_nvjpg_engdesc.c +++ b/src/nvidia/src/kernel/gpu/nvjpg/kernel_nvjpg_engdesc.c @@ -81,6 +81,7 @@ nvjpgGetEngineDescFromAllocParams { KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); MIG_INSTANCE_REF ref; + RM_ENGINE_TYPE rmEngineType; NV_ASSERT_OK( kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, @@ -88,9 +89,9 @@ nvjpgGetEngineDescFromAllocParams NV_ASSERT_OK( kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, - NV2080_ENGINE_TYPE_NVJPEG(engineInstance), - &engineInstance)); - return ENG_NVJPEG(NV2080_ENGINE_TYPE_NVJPEG_IDX(engineInstance)); + RM_ENGINE_TYPE_NVJPEG(engineInstance), + &rmEngineType)); + return ENG_NVJPEG(RM_ENGINE_TYPE_NVJPEG_IDX(rmEngineType)); } // Get the right class as per engine instance. diff --git a/src/nvidia/src/kernel/gpu/nvlink/arch/ampere/kernel_nvlink_ga100.c b/src/nvidia/src/kernel/gpu/nvlink/arch/ampere/kernel_nvlink_ga100.c index e706aaaa7..f747c7f9f 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/arch/ampere/kernel_nvlink_ga100.c +++ b/src/nvidia/src/kernel/gpu/nvlink/arch/ampere/kernel_nvlink_ga100.c @@ -132,6 +132,8 @@ knvlinkRemoveMapping_GA100 ) { NV_STATUS status = NV_OK; + NvU32 peerId; + NvBool bBufferReady; NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS params; portMemSet(¶ms, 0, sizeof(params)); @@ -161,7 +163,35 @@ knvlinkRemoveMapping_GA100 // the MUX registers and the connection config registers. So, we have // to call nvlinkCurrentConfig instead of nvlinkUpdateHshubConfigRegs // - return knvlinkUpdateCurrentConfig(pGpu, pKernelNvlink); + status = knvlinkSyncLinkMasksAndVbiosInfo(pGpu, pKernelNvlink); + if (status != NV_OK) + { + NV_ASSERT(status == NV_OK); + return status; + } + + if (pKernelNvlink->getProperty(pKernelNvlink, PDB_PROP_KNVLINK_CONFIG_REQUIRE_INITIALIZED_LINKS_CHECK)) + { + FOR_EACH_INDEX_IN_MASK(32, peerId, peerMask) + { + if (pKernelNvlink->initializedLinks & pKernelNvlink->peerLinkMasks[peerId]) + { + bBufferReady = NV_TRUE; + break; + } + } FOR_EACH_INDEX_IN_MASK_END; + + if (!bBufferReady) + { + status = knvlinkUpdateCurrentConfig(pGpu, pKernelNvlink); + } + } + else + { + status = knvlinkUpdateCurrentConfig(pGpu, pKernelNvlink); + } + + return status; } /*! @@ -184,6 +214,7 @@ knvlinkValidateFabricBaseAddress_GA100 { MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); NvU64 fbSizeBytes; + NvU64 fbUpperLimit; fbSizeBytes = pMemoryManager->Ram.fbTotalMemSizeMb << 20; @@ -202,8 +233,11 @@ knvlinkValidateFabricBaseAddress_GA100 // Align fbSize to mapslot size. fbSizeBytes = RM_ALIGN_UP(fbSizeBytes, NVBIT64(36)); + + fbUpperLimit = fabricBaseAddr + fbSizeBytes; + // Make sure the address range doesn't go beyond the limit, (2K * 64GB). - if ((fabricBaseAddr + fbSizeBytes) > NVBIT64(47)) + if (fbUpperLimit > NVBIT64(47)) { return NV_ERR_INVALID_ARGUMENT; } diff --git a/src/nvidia/src/kernel/gpu/nvlink/arch/hopper/kernel_nvlink_gh100.c b/src/nvidia/src/kernel/gpu/nvlink/arch/hopper/kernel_nvlink_gh100.c index a46dfe7a1..f447e9160 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/arch/hopper/kernel_nvlink_gh100.c +++ b/src/nvidia/src/kernel/gpu/nvlink/arch/hopper/kernel_nvlink_gh100.c @@ -26,6 +26,7 @@ #include "kernel/gpu/nvlink/kernel_ioctrl.h" #include "gpu/gpu.h" #include "gpu/mem_mgr/mem_mgr.h" +#include "nverror.h" /*! * @brief Check if ALI is supported for the given device @@ -248,3 +249,165 @@ knvlinkDiscoverPostRxDetLinks_GH100 return status; } + +NV_STATUS +knvlinkLogAliDebugMessages_GH100 +( + OBJGPU *pGpu, + KernelNvlink *pKernelNvlink +) +{ + NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS *nvlinkErrInfoParams = portMemAllocNonPaged(sizeof(NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS)); + portMemSet(nvlinkErrInfoParams, 0, sizeof(NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS)); + nvlinkErrInfoParams->ErrInfoFlags |= NV2080_CTRL_NVLINK_ERR_INFO_FLAGS_ALI_STATUS; + NvU32 i; + // This is a Physical, Hopper specific HAL for debug purposes. + NV_STATUS status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, + NV2080_CTRL_CMD_NVLINK_GET_ERR_INFO, + (void *)nvlinkErrInfoParams, + sizeof(NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Error getting debug info for link training!\n"); + return status; + } + + FOR_EACH_INDEX_IN_MASK(32, i, pKernelNvlink->postRxDetLinkMask) + { + nvErrorLog_va((void *)pGpu, ALI_TRAINING_FAIL, + "NVLink: Link training failed for link %u", + "(0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x)", + i, + nvlinkErrInfoParams->linkErrInfo[i].NVLIPTLnkCtrlLinkStateRequest, + nvlinkErrInfoParams->linkErrInfo[i].NVLDLRxSlsmErrCntl, + nvlinkErrInfoParams->linkErrInfo[i].NVLDLTopLinkState, + nvlinkErrInfoParams->linkErrInfo[i].NVLDLTopIntr, + nvlinkErrInfoParams->linkErrInfo[i].DLStatMN00, + nvlinkErrInfoParams->linkErrInfo[i].DLStatUC01, + nvlinkErrInfoParams->linkErrInfo[i].MinionNvlinkLinkIntr); + + if (pKernelNvlink->bLinkTrainingDebugSpew) + NV_PRINTF(LEVEL_ERROR,"ALI Error for GPU %d::linkId %d:" + "\nNVLIPT:\n\tCTRL_LINK_STATE_REQUEST_STATUS = %X\n" + "\nNVLDL :\n\tNV_NVLDL_RXSLSM_ERR_CNTL = %X\n" + "\n\tNV_NVLDL_TOP_LINK_STATE = %X\n" + "\n\tNV_NVLDL_TOP_INTR = %X\n" + "\nMINION DLSTAT:\n\tDLSTAT MN00 = %X\n" + "\n\tDLSTAT UC01 = %X\n" + "\n\tNV_MINION_NVLINK_LINK_INTR = %X\n", + pGpu->gpuInstance, i, + nvlinkErrInfoParams->linkErrInfo[i].NVLIPTLnkCtrlLinkStateRequest, + nvlinkErrInfoParams->linkErrInfo[i].NVLDLRxSlsmErrCntl, + nvlinkErrInfoParams->linkErrInfo[i].NVLDLTopLinkState, + nvlinkErrInfoParams->linkErrInfo[i].NVLDLTopIntr, + nvlinkErrInfoParams->linkErrInfo[i].DLStatMN00, + nvlinkErrInfoParams->linkErrInfo[i].DLStatUC01, + nvlinkErrInfoParams->linkErrInfo[i].MinionNvlinkLinkIntr); + } + FOR_EACH_INDEX_IN_MASK_END; + portMemFree(nvlinkErrInfoParams); + return NV_OK; +} + +/*! + * @brief Set unique fabric address for NVSwitch enabled systems. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelNvlink KernelNvlink pointer + * @param[in] fabricBaseAddr Fabric Address to set + * + * @returns On success, sets unique fabric address and returns NV_OK. + * On failure, returns NV_ERR_XXX. + */ +NV_STATUS +knvlinkSetUniqueFabricBaseAddress_GH100 +( + OBJGPU *pGpu, + KernelNvlink *pKernelNvlink, + NvU64 fabricBaseAddr +) +{ + NV_STATUS status = NV_OK; + + status = knvlinkValidateFabricBaseAddress_HAL(pGpu, pKernelNvlink, + fabricBaseAddr); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Fabric addr validation failed for GPU %x\n", + pGpu->gpuInstance); + return status; + } + + if (IsSLIEnabled(pGpu)) + { + NV_PRINTF(LEVEL_ERROR, + "Operation is unsupported on SLI enabled GPU %x\n", + pGpu->gpuInstance); + return NV_ERR_NOT_SUPPORTED; + } + + if (pKernelNvlink->fabricBaseAddr == fabricBaseAddr) + { + NV_PRINTF(LEVEL_INFO, + "The same fabric addr is being re-assigned to GPU %x\n", + pGpu->gpuInstance); + return NV_OK; + } + + if (pKernelNvlink->fabricBaseAddr != NVLINK_INVALID_FABRIC_ADDR) + { + NV_PRINTF(LEVEL_ERROR, "Fabric addr is already assigned to GPU %x\n", + pGpu->gpuInstance); + return NV_ERR_STATE_IN_USE; + } + + pKernelNvlink->fabricBaseAddr = fabricBaseAddr; + + NV_PRINTF(LEVEL_INFO, "Fabric base addr %llx is assigned to GPU %x\n", + pKernelNvlink->fabricBaseAddr, pGpu->gpuInstance); + + return NV_OK; +} + +/*! + * @brief Check if floorsweeping is needed for this particular chip + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelNvlink KernelNvlink pointer + * + * @returns On success, sets unique fabric address and returns NV_OK. + * On failure, returns NV_ERR_XXX. + */ +NvBool +knvlinkIsFloorSweepingNeeded_GH100 +( + OBJGPU *pGpu, + KernelNvlink *pKernelNvlink, + NvU32 numActiveLinksPerIoctrl, + NvU32 numLinksPerIoctrl +) +{ + + // + // Only floorsweep down the given GPU if the following conditions are met: + // 1. The number of active links allowed for the IOCTRL is less then the + // total number of links for the IOCTRL. No reason to spend time in code + // if the exectution of it will be a NOP + // + // 2. If the GPU has never been floorswept. An optimization to make sure RM + // doesn't burn cycles repeatedly running running code that will be a NOP + // + // 3. (temporary) Run only on Silicon chips. Fmodel currently doesn't support + // this feature + // + + if (numActiveLinksPerIoctrl < numLinksPerIoctrl && + !pKernelNvlink->bFloorSwept && + IS_SILICON(pGpu)) + { + return NV_TRUE; + } + + return NV_FALSE; +} + diff --git a/src/nvidia/src/kernel/gpu/nvlink/arch/pascal/kernel_nvlink_gp100.c b/src/nvidia/src/kernel/gpu/nvlink/arch/pascal/kernel_nvlink_gp100.c index fb1786e57..6491cb398 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/arch/pascal/kernel_nvlink_gp100.c +++ b/src/nvidia/src/kernel/gpu/nvlink/arch/pascal/kernel_nvlink_gp100.c @@ -203,28 +203,17 @@ knvlinkGetP2POptimalCEs_GP100 NvU32 *p2pOptimalWriteCEs ) { - KernelCE *kce = NULL; - NvU32 maxCes = 0; + KernelCE *pKCe = NULL; NvU32 sysmemReadCE = 0; NvU32 sysmemWriteCE = 0; NvU32 nvlinkP2PCeMask = 0; - NvU32 i; - maxCes = gpuGetNumCEs(pGpu); - - for (i = 0; i < maxCes; i++) - { - kce = GPU_GET_KCE(pGpu, i); - if (kce) - { - kceGetCeFromNvlinkConfig(pGpu, kce, - gpuMask, - &sysmemReadCE, - &sysmemWriteCE, - &nvlinkP2PCeMask); - break; - } - } + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kceFindFirstInstance(pGpu, &pKCe)); + kceGetCeFromNvlinkConfig(pGpu, pKCe, + gpuMask, + &sysmemReadCE, + &sysmemWriteCE, + &nvlinkP2PCeMask); if (sysmemOptimalReadCEs != NULL) { diff --git a/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_nvlink_gv100.c b/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_nvlink_gv100.c index 6425ecff7..1db8e82f6 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_nvlink_gv100.c +++ b/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_nvlink_gv100.c @@ -455,7 +455,9 @@ knvlinkStatePostLoadHal_GV100 } } - if (knvlinkIsNvswitchProxyPresent(pGpu, pKernelNvlink) || pKernelNvlink->bOverrideComputePeerMode) + if (knvlinkIsNvswitchProxyPresent(pGpu, pKernelNvlink) || + pKernelNvlink->bOverrideComputePeerMode || + GPU_IS_NVSWITCH_DETECTED(pGpu)) { status = kgmmuEnableNvlinkComputePeerAddressing_HAL(pKernelGmmu); if (status != NV_OK) @@ -524,3 +526,108 @@ knvlinkValidateFabricBaseAddress_GV100 return NV_OK; } + +/*! + * @brief Set unique fabric address for NVSwitch enabled systems. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelNvlink KernelNvlink pointer + * @param[in] fabricBaseAddr Fabric Address to set + * + * @returns On success, sets unique fabric address and returns NV_OK. + * On failure, returns NV_ERR_XXX. + */ +NV_STATUS +knvlinkSetUniqueFabricBaseAddress_GV100 +( + OBJGPU *pGpu, + KernelNvlink *pKernelNvlink, + NvU64 fabricBaseAddr +) +{ + NV_STATUS status = NV_OK; + + if (!knvlinkIsForcedConfig(pGpu, pKernelNvlink)) + { + knvlinkCoreGetRemoteDeviceInfo(pGpu, pKernelNvlink); + + status = knvlinkEnableLinksPostTopology_HAL(pGpu, pKernelNvlink, + pKernelNvlink->enabledLinks); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Nvlink post topology links setup failed on GPU %x\n", + pGpu->gpuInstance); + return status; + } + } + + if (!knvlinkIsGpuConnectedToNvswitch(pGpu, pKernelNvlink)) + { + NV_PRINTF(LEVEL_ERROR, + "Operation failed due to no NVSwitch connectivity to the " + "GPU %x\n", pGpu->gpuInstance); + return NV_ERR_INVALID_STATE; + } + + status = knvlinkValidateFabricBaseAddress_HAL(pGpu, pKernelNvlink, + fabricBaseAddr); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Fabric addr validation failed for GPU %x\n", + pGpu->gpuInstance); + return status; + } + + if (IsSLIEnabled(pGpu)) + { + NV_PRINTF(LEVEL_ERROR, + "Operation is unsupported on SLI enabled GPU %x\n", + pGpu->gpuInstance); + return NV_ERR_NOT_SUPPORTED; + } + + if (pKernelNvlink->fabricBaseAddr == fabricBaseAddr) + { + NV_PRINTF(LEVEL_INFO, + "The same fabric addr is being re-assigned to GPU %x\n", + pGpu->gpuInstance); + return NV_OK; + } + + if (pKernelNvlink->fabricBaseAddr != NVLINK_INVALID_FABRIC_ADDR) + { + NV_PRINTF(LEVEL_ERROR, "Fabric addr is already assigned to GPU %x\n", + pGpu->gpuInstance); + return NV_ERR_STATE_IN_USE; + } + + // + // Update GMMU peer field descriptor. + // We can safely defer reinitialization of peer field descriptor to this + // call because RM doesn't allow any P2P operations until FM assigns fabric + // addresses. + // + NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS params; + + portMemSet(¶ms, 0, sizeof(params)); + params.bGet = NV_FALSE; + params.addr = fabricBaseAddr; + + status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, + NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR, + (void *)¶ms, sizeof(params)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to stash fabric address for GPU %x\n", + pGpu->gpuInstance); + return status; + } + + pKernelNvlink->fabricBaseAddr = fabricBaseAddr; + + NV_PRINTF(LEVEL_ERROR, "Fabric base addr %llx is assigned to GPU %x\n", + pKernelNvlink->fabricBaseAddr, pGpu->gpuInstance); + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/nvlink/common_nvlinkapi.c b/src/nvidia/src/kernel/gpu/nvlink/common_nvlinkapi.c new file mode 100644 index 000000000..6c8fe73d9 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/nvlink/common_nvlinkapi.c @@ -0,0 +1,767 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gpu/gpu.h" +#include "gpu/subdevice/subdevice.h" +#include "vgpu/rpc.h" + +#include "kernel/gpu/nvlink/kernel_nvlink.h" +#include "kernel/gpu/nvlink/kernel_ioctrl.h" +#include "kernel/gpu/nvlink/common_nvlink.h" + +typedef struct +{ + NvU32 laneRxdetStatusMask; + NvBool bConnected; + NvU32 remoteLinkNumber; + NvU64 remoteDeviceType; + NvU64 remoteChipSid; + NvU32 remoteDomain; + NvU8 remoteBus; + NvU8 remoteDevice; + NvU8 remoteFunction; + NvU32 remotePciDeviceId; + NvBool bLoopbackSupported; +} NvlinkLinkStatus; + +// +// subdeviceCtrlCmdBusGetNvlinkCaps +// Get the Nvlink global capabilities +// +NV_STATUS +subdeviceCtrlCmdBusGetNvlinkCaps_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + + return nvlinkCtrlCmdBusGetNvlinkCaps(pGpu, pParams); +} + +static void _calculateNvlinkCaps +( + OBJGPU *pGpu, + NvU32 bridgeSensableLinks, + NvU32 bridgedLinks, + NvU32 ipVerNvlink, + NvBool bMIGNvLinkP2PSupported, + NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS *pParams +) +{ + NvU8 tempCaps[NV2080_CTRL_NVLINK_CAPS_TBL_SIZE]; + portMemSet(tempCaps, 0, NV2080_CTRL_NVLINK_CAPS_TBL_SIZE); + + // With MIG memory partitioning, NvLink P2P or sysmem accesses are not allowed + if (bMIGNvLinkP2PSupported) + { + RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _SUPPORTED); + RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _SYSMEM_ACCESS); + RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _P2P_SUPPORTED); + RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _P2P_ATOMICS); + + // + // This GPU supports SLI bridge sensing if any of the links + // support bridge sensing. + // + if (bridgeSensableLinks != 0) + { + RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _SLI_BRIDGE_SENSABLE); + } + + // This GPU has an SLI bridge if any of the links are bridged + if (bridgedLinks != 0) + { + RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _SLI_BRIDGE); + } + + // NVLink versions beyond the first support sysmem atomics + if (ipVerNvlink != NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_1_0) + { + RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _SYSMEM_ATOMICS); + } + } + + switch (ipVerNvlink) + { + case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0: + { + pParams->lowestNvlinkVersion = NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0; + pParams->highestNvlinkVersion = NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0; + pParams->lowestNciVersion = NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_4_0; + pParams->highestNciVersion = NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_4_0; + + // Supported power states + RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _POWER_STATE_L0); + RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _POWER_STATE_L1); + break; + } + case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1: + { + pParams->lowestNvlinkVersion = NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1; + pParams->highestNvlinkVersion = NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1; + pParams->lowestNciVersion = NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_1; + pParams->highestNciVersion = NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_1; + + // Supported power states + RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _POWER_STATE_L0); + RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _POWER_STATE_L2); + break; + } + case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_0: + { + pParams->lowestNvlinkVersion = NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_0; + pParams->highestNvlinkVersion = NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_0; + pParams->lowestNciVersion = NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_0; + pParams->highestNciVersion = NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_0; + + // Supported power states + RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _POWER_STATE_L0); + RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _POWER_STATE_L2); + break; + } + case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_2: + { + pParams->lowestNvlinkVersion = NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_2; + pParams->highestNvlinkVersion = NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_2; + pParams->lowestNciVersion = NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_2; + pParams->highestNciVersion = NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_2; + + // Supported power states + RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _POWER_STATE_L0); + RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _POWER_STATE_L2); + break; + } + case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_0: + { + pParams->lowestNvlinkVersion = NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_0; + pParams->highestNvlinkVersion = NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_0; + pParams->lowestNciVersion = NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_0; + pParams->highestNciVersion = NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_0; + + // Supported power states + RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _POWER_STATE_L0); + break; + } + default: + { + pParams->lowestNvlinkVersion = NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_1_0; + pParams->highestNvlinkVersion = NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_1_0; + pParams->lowestNciVersion = NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_1_0; + pParams->highestNciVersion = NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_1_0; + + // Supported power states + RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _POWER_STATE_L0); + break; + } + } + + portMemCopy(&pParams->capsTbl, NV2080_CTRL_NVLINK_CAPS_TBL_SIZE, tempCaps, NV2080_CTRL_NVLINK_CAPS_TBL_SIZE); +} + +// +// knvlinkCtrlCmdBusGetNvlinkCaps +// Inner function of subdeviceCtrlCmdBusGetNvlinkCaps for internal RM direct function call +// Get the Nvlink global capabilities +// +NV_STATUS +nvlinkCtrlCmdBusGetNvlinkCaps +( + OBJGPU *pGpu, + NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS *pParams +) +{ + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + NvBool bMIGNvLinkP2PSupported = ((pKernelMIGManager != NULL) && + kmigmgrIsMIGNvlinkP2PSupported(pGpu, pKernelMIGManager)); + // + // vGPU: + // + // Since vGPU does all real hardware management in the + // host, if we are in guest OS (where IS_VIRTUAL(pGpu) is true), + // do an RPC to the host to get blacklist information from host RM + // + if (IS_VIRTUAL(pGpu)) + { + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; + NV_STATUS status = NV_OK; + + NV_RM_RPC_CONTROL(pGpu, pRmCtrlParams->hClient, pRmCtrlParams->hObject, pRmCtrlParams->cmd, + pRmCtrlParams->pParams, pRmCtrlParams->paramsSize, status); + return status; + } + + // Initialize link masks to 0 + pParams->enabledLinkMask = 0; + pParams->discoveredLinkMask = 0; + + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && RMCFG_FEATURE_PLATFORM_GSP) + { + return NV_ERR_NOT_SUPPORTED; + } + else + { + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + if (pKernelNvlink == NULL) + { + NV_PRINTF(LEVEL_INFO, "Kernel NVLink is unavailable. Returning.\n"); + return NV_OK; + } + // With MIG memory partitioning, NvLink P2P or sysmem accesses are not allowed + if (bMIGNvLinkP2PSupported) + { + // + // Some links might have passed receiver detect (bridge is present), + // but might have failed to transition to safe mode (marginal links) + // Update connectedLinks and bridgedLinks mask for these links + // + knvlinkFilterBridgeLinks_HAL(pGpu, pKernelNvlink); + } + _calculateNvlinkCaps(pGpu, pKernelNvlink->bridgeSensableLinks, pKernelNvlink->bridgedLinks, pKernelNvlink->ipVerNvlink, bMIGNvLinkP2PSupported, pParams); + + pParams->discoveredLinkMask = knvlinkGetDiscoveredLinkMask(pGpu, pKernelNvlink); + pParams->enabledLinkMask = knvlinkGetEnabledLinkMask(pGpu, pKernelNvlink); + } + + return NV_OK; +} + +void +static _getNvlinkStatus +( + OBJGPU *pGpu, + NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS *nvlinkLinkAndClockInfoParams, + NvU32 bridgeSensableLinks, + NvU32 bridgedLinks, + NvU32 ipVerNvlink, + NvlinkLinkStatus nvlinkLinks[NVLINK_MAX_LINKS_SW], + NvBool bNvlinkEnabled, + NvBool bL2PowerStateEnabled, + NvBool bForcedConfig, + NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *pParams +) +{ + NvU8 i = 0; + NvU8 tempCaps[NV2080_CTRL_NVLINK_CAPS_TBL_SIZE]; + NvU32 r = 0; + OBJGPU *remotePeer0 = NULL; + NvBool bPeerLink, bSysmemLink, bSwitchLink; + + r = pParams->enabledLinkMask; + while (r >>= 1 ) i++; + + NV_ASSERT(i <= NV2080_CTRL_NVLINK_MAX_LINKS); + + FOR_EACH_INDEX_IN_MASK(32, i, pParams->enabledLinkMask) + { + bPeerLink = NV_FALSE; + bSysmemLink = NV_FALSE; + bSwitchLink = NV_FALSE; + NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_VALUES *pLinkAndClockValues; + + pLinkAndClockValues = &nvlinkLinkAndClockInfoParams->linkInfo[i]; + + portMemSet(tempCaps, 0, NV2080_CTRL_NVLINK_CAPS_TBL_SIZE); + + if (bNvlinkEnabled) + { + RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _VALID); + } + + if (pLinkAndClockValues->bLinkConnectedToSystem) + { + // Tag as a Sysmem link + bSysmemLink = NV_TRUE; + + RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _SYSMEM_ACCESS); + + // NVLink versions beyond the first support sysmem atomics + if (ipVerNvlink != NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_1_0 ) + { + RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _SYSMEM_ATOMICS); + } + } + + if (pLinkAndClockValues->bLinkConnectedToPeer) + { + // Tag as Peer link + bPeerLink = NV_TRUE; + + RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _P2P_SUPPORTED); + RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _P2P_ATOMICS); + } + + // Indicate per-link bridge sense status + if (bridgeSensableLinks & NVBIT(i)) + { + RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _SLI_BRIDGE_SENSABLE); + } + + // Indicate per-link bridge status + if (bridgedLinks & NVBIT(i)) + { + RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _SLI_BRIDGE); + } + + // Set the power states caps + switch (ipVerNvlink) + { + case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_0: + RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _POWER_STATE_L0); + break; + + case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0: + case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1: + case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_0: + case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_2: + RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _POWER_STATE_L0); + if (bL2PowerStateEnabled) + { + RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _POWER_STATE_L2); + } + break; + + default: + RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _POWER_STATE_L0); + break; + } + + portMemCopy(&pParams->linkInfo[i].capsTbl, NV2080_CTRL_NVLINK_CAPS_TBL_SIZE, tempCaps, NV2080_CTRL_NVLINK_CAPS_TBL_SIZE); + + pParams->linkInfo[i].phyType = NV2080_CTRL_NVLINK_STATUS_PHY_NVHS; + pParams->linkInfo[i].subLinkWidth = pLinkAndClockValues->subLinkWidth; + pParams->linkInfo[i].linkState = pLinkAndClockValues->linkState; + pParams->linkInfo[i].txSublinkStatus = (NvU8) pLinkAndClockValues->txSublinkState; + pParams->linkInfo[i].rxSublinkStatus = (NvU8) pLinkAndClockValues->rxSublinkState; + + // Initialize the lane reversal state information for the link + pParams->linkInfo[i].bLaneReversal = pLinkAndClockValues->bLaneReversal; + + switch (ipVerNvlink) + { + case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0: + pParams->linkInfo[i].nvlinkVersion = NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_4_0; + pParams->linkInfo[i].nciVersion = NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_4_0; + break; + case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1: + pParams->linkInfo[i].nvlinkVersion = NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_1; + pParams->linkInfo[i].nciVersion = NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_1; + break; + case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_0: + pParams->linkInfo[i].nvlinkVersion = NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_0; + pParams->linkInfo[i].nciVersion = NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_0; + break; + case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_2: + pParams->linkInfo[i].nvlinkVersion = NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_2; + pParams->linkInfo[i].nciVersion = NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_2_2; + break; + case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_0: + pParams->linkInfo[i].nvlinkVersion = NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_0; + pParams->linkInfo[i].nciVersion = NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_2_0; + break; + default: + pParams->linkInfo[i].nvlinkVersion = NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_1_0; + pParams->linkInfo[i].nciVersion = NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_1_0; + break; + } + pParams->linkInfo[i].phyVersion = NV2080_CTRL_NVLINK_STATUS_NVHS_VERSION_1_0; + + // Initialize the connection information for the link + pParams->linkInfo[i].connected = NV2080_CTRL_NVLINK_STATUS_CONNECTED_FALSE; + pParams->linkInfo[i].remoteDeviceLinkNumber = NV2080_CTRL_NVLINK_STATUS_REMOTE_LINK_NUMBER_INVALID; + pParams->linkInfo[i].remoteDeviceInfo.deviceType = NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NONE; + pParams->linkInfo[i].localDeviceLinkNumber = i; + pParams->linkInfo[i].laneRxdetStatusMask = nvlinkLinks[i].laneRxdetStatusMask; + + // Set the device information for the local end of the link + pParams->linkInfo[i].localDeviceInfo.domain = gpuGetDomain(pGpu); + pParams->linkInfo[i].localDeviceInfo.bus = gpuGetBus(pGpu); + pParams->linkInfo[i].localDeviceInfo.device = gpuGetDevice(pGpu); + pParams->linkInfo[i].localDeviceInfo.function = 0; + pParams->linkInfo[i].localDeviceInfo.pciDeviceId = pGpu->idInfo.PCIDeviceID; + pParams->linkInfo[i].localDeviceInfo.deviceType = NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU; + + // Record the local end of the link's deviceIdFlags + if(pGpu->idInfo.PCIDeviceID) + { + pParams->linkInfo[i].localDeviceInfo.deviceIdFlags = + FLD_SET_DRF(2080_CTRL_NVLINK, _DEVICE_INFO, _DEVICE_ID_FLAGS, _PCI, + pParams->linkInfo[i].localDeviceInfo.deviceIdFlags); + } + + // + // Get clock related state + // NOTE: to be depricated HW terminology conforming versions + // + pParams->linkInfo[i].nvlinkLinkClockKHz = pLinkAndClockValues->nvlinkLinkClockKHz; + pParams->linkInfo[i].nvlinkRefClkSpeedKHz = nvlinkLinkAndClockInfoParams->nvlinkRefClkSpeedKHz; + pParams->linkInfo[i].nvlinkCommonClockSpeedKHz = pParams->linkInfo[i].nvlinkLinkClockKHz / 16; + + pParams->linkInfo[i].nvlinkCommonClockSpeedMhz = pParams->linkInfo[i].nvlinkCommonClockSpeedKHz / 1000; + + // Clock speed and Data rate info conforming with HW terminology + pParams->linkInfo[i].nvlinkLineRateMbps = pLinkAndClockValues->nvlinkLineRateMbps; + pParams->linkInfo[i].nvlinkLinkClockMhz = pLinkAndClockValues->nvlinkLinkClockMhz; + pParams->linkInfo[i].nvlinkLinkDataRateKiBps = pLinkAndClockValues->nvlinkLinkDataRateKiBps; + pParams->linkInfo[i].nvlinkRefClkType = pLinkAndClockValues->nvlinkRefClkType; + pParams->linkInfo[i].nvlinkRefClkSpeedMhz = pLinkAndClockValues->nvlinkReqLinkClockMhz; + + if (nvlinkLinks[i].bConnected) + { + pParams->linkInfo[i].connected = NV2080_CTRL_NVLINK_STATUS_CONNECTED_TRUE; + pParams->linkInfo[i].remoteDeviceLinkNumber = (NvU8) nvlinkLinks[i].remoteLinkNumber; + pParams->linkInfo[i].remoteLinkSid = nvlinkLinks[i].remoteChipSid; + + // Set the device information for the remote end of the link + pParams->linkInfo[i].remoteDeviceInfo.domain = nvlinkLinks[i].remoteDomain; + pParams->linkInfo[i].remoteDeviceInfo.bus = nvlinkLinks[i].remoteBus; + pParams->linkInfo[i].remoteDeviceInfo.device = nvlinkLinks[i].remoteDevice; + pParams->linkInfo[i].remoteDeviceInfo.function = nvlinkLinks[i].remoteFunction; + pParams->linkInfo[i].remoteDeviceInfo.pciDeviceId = nvlinkLinks[i].remotePciDeviceId; + pParams->linkInfo[i].remoteDeviceInfo.deviceType = nvlinkLinks[i].remoteDeviceType; + + // Update the device Id flags for PCI + if (nvlinkLinks[i].remotePciDeviceId) + { + pParams->linkInfo[i].remoteDeviceInfo.deviceIdFlags |= + FLD_SET_DRF(2080_CTRL_NVLINK, _DEVICE_INFO, _DEVICE_ID_FLAGS, _PCI, + pParams->linkInfo[i].remoteDeviceInfo.deviceIdFlags); + } + + // Check the PCI dbdf values to confirm the device on remote end + if (NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_PCI & pParams->linkInfo[i].remoteDeviceInfo.deviceIdFlags) + { + if (!nvlinkLinks[i].bLoopbackSupported) + { + pParams->linkInfo[i].loopProperty = NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_NONE; + continue; + } + } + + pParams->linkInfo[i].loopProperty = pParams->linkInfo[i].remoteDeviceLinkNumber == i ? + NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPBACK : + NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPOUT; + } + + if (!(IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && RMCFG_FEATURE_PLATFORM_GSP)) + { + // Per-link ForceConfig handling (non-legacy Arch ForceConfig only) + if (bForcedConfig) + { + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_EMULATION)) + { + pParams->linkInfo[i].linkState = NV2080_CTRL_NVLINK_STATUS_LINK_STATE_ACTIVE; + pParams->linkInfo[i].rxSublinkStatus = NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_HIGH_SPEED_1; + pParams->linkInfo[i].txSublinkStatus = NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_HIGH_SPEED_1; + } + + pParams->linkInfo[i].connected = NV_TRUE; + pParams->linkInfo[i].loopProperty = NV_FALSE; + pParams->linkInfo[i].remoteDeviceLinkNumber = i; + if (!pParams->linkInfo[i].nvlinkLinkClockMhz) + pParams->linkInfo[i].nvlinkLinkClockMhz = pLinkAndClockValues->nvlinkReqLinkClockMhz; + + // Expose remote device as EBRIDGE if forced only sysmem + if (bSysmemLink && !bPeerLink && !bSwitchLink) + { + pParams->linkInfo[i].remoteDeviceInfo.domain = 0; + pParams->linkInfo[i].remoteDeviceInfo.bus = FORCED_SYSMEM_PCI_BUS; + pParams->linkInfo[i].remoteDeviceInfo.device = 0; + pParams->linkInfo[i].remoteDeviceInfo.function = i; + pParams->linkInfo[i].remoteDeviceInfo.pciDeviceId = FORCED_SYSMEM_DEVICE_ID; + pParams->linkInfo[i].remoteDeviceInfo.deviceType = FORCED_SYSMEM_DEVICE_TYPE; + + pParams->linkInfo[i].remoteDeviceInfo.deviceIdFlags |= + FLD_SET_DRF(2080_CTRL_NVLINK, _DEVICE_INFO, _DEVICE_ID_FLAGS, _PCI, + pParams->linkInfo[i].remoteDeviceInfo.deviceIdFlags); + } + + // Expose remote device as GPU if forced only peer + if (bPeerLink && !bSysmemLink && !bSwitchLink) + { + remotePeer0 = gpumgrGetGpu(pGpu->gpuInstance == 0 ? 1 : 0); + if (NULL == remotePeer0) + { + remotePeer0 = pGpu; + } + + // + // Ensure the remote is actually a GPU that supports NVLink. + // If it is not, we should stick with the current GPU as + // this is likely a loopback config. See Bug 1786206. + // + if (remotePeer0 != pGpu) + { + KernelNvlink *pRemoteKernelNvlink = GPU_GET_KERNEL_NVLINK(remotePeer0); + if (pRemoteKernelNvlink) + { + if (pRemoteKernelNvlink->discoveredLinks == 0) + { + // There are no links on this remote, fall back to loopback. + remotePeer0 = pGpu; + } + } + else + { + // NVLink not present on this remote, fall back to loopback. + remotePeer0 = pGpu; + } + } + + pParams->linkInfo[i].remoteDeviceInfo.domain = gpuGetDomain(remotePeer0); + pParams->linkInfo[i].remoteDeviceInfo.bus = gpuGetBus(remotePeer0); + pParams->linkInfo[i].remoteDeviceInfo.device = gpuGetDevice(remotePeer0); + pParams->linkInfo[i].remoteDeviceInfo.function = 0; + pParams->linkInfo[i].remoteDeviceInfo.pciDeviceId = remotePeer0->idInfo.PCIDeviceID; + pParams->linkInfo[i].remoteDeviceInfo.deviceType = NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU; + + // This config is either in loopback or real 1/1 P2P, nothing else. + if (gpuGetDBDF(remotePeer0) == gpuGetDBDF(pGpu)) + { + pParams->linkInfo[i].loopProperty = NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPBACK; + } + + pParams->linkInfo[i].remoteDeviceInfo.deviceIdFlags |= + FLD_SET_DRF(2080_CTRL_NVLINK, _DEVICE_INFO, _DEVICE_ID_FLAGS, _PCI, + pParams->linkInfo[i].remoteDeviceInfo.deviceIdFlags); + } + + // + // Expose remote device as Switch if requested + // Requested can be either forced sysmem and peer or + // if either and requested as switch + // + if ( (bSysmemLink && bPeerLink) || + ((bSysmemLink || bPeerLink) && bSwitchLink)) + { + pParams->linkInfo[i].remoteDeviceInfo.domain = 0; + pParams->linkInfo[i].remoteDeviceInfo.bus = FORCED_SWITCH_PCI_BUS; + pParams->linkInfo[i].remoteDeviceInfo.device = 0; + pParams->linkInfo[i].remoteDeviceInfo.function = i; + pParams->linkInfo[i].remoteDeviceInfo.pciDeviceId = FORCED_SWITCH_DEVICE_ID; + pParams->linkInfo[i].remoteDeviceInfo.deviceType = NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_SWITCH; + + pParams->linkInfo[i].remoteDeviceInfo.deviceIdFlags |= + FLD_SET_DRF(2080_CTRL_NVLINK, _DEVICE_INFO, _DEVICE_ID_FLAGS, _PCI, + pParams->linkInfo[i].remoteDeviceInfo.deviceIdFlags); + } + } + } + } + FOR_EACH_INDEX_IN_MASK_END; +} + +// +// subdeviceCtrlCmdBusGetNvlinkStatus +// Get the Nvlink per link capabilities +// +NV_STATUS +subdeviceCtrlCmdBusGetNvlinkStatus_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + NvBool bMIGNvLinkP2PSupported = ((pKernelMIGManager != NULL) && + kmigmgrIsMIGNvlinkP2PSupported(pGpu, pKernelMIGManager)); + NV_STATUS status = NV_OK; + NvU8 i = 0; + struct + { + NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS nvlinkLinkAndClockInfoParams; + NvlinkLinkStatus nvlinkLinks[NVLINK_MAX_LINKS_SW]; + } *pTmpData = NULL; + + // + // vGPU: + // + // Since vGPU does all real hardware management in the + // host, if we are in guest OS (where IS_VIRTUAL(pGpu) is true), + // do an RPC to the host to get blacklist information from host RM + // + if (IS_VIRTUAL(pGpu)) + { + // RPC for this RmCtrl was implemented as an effort of enabling NVLINK P2P + // on vGPU. As NVLINK P2P is supported Pascal+ onwards, we return NOT_SUPPORTED + // pre-Pascal. + if (IsPASCALorBetter(pGpu)) + { + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; + + NV_RM_RPC_CONTROL(pGpu, pRmCtrlParams->hClient, pRmCtrlParams->hObject, pRmCtrlParams->cmd, + pRmCtrlParams->pParams, pRmCtrlParams->paramsSize, status); + + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + { + FOR_EACH_INDEX_IN_MASK(32, i, pParams->enabledLinkMask) + { + NV2080_CTRL_NVLINK_DEVICE_INFO *pDeviceInfo = &pParams->linkInfo[i].remoteDeviceInfo; + OBJGPU *pLoopGpu = gpumgrGetGpuFromUuid(pDeviceInfo->deviceUUID, + DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _TYPE, _SHA1) | + DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _FORMAT, _BINARY)); + + // Clear output if no gpu on the other end + if (pLoopGpu == NULL) + { + portMemSet(&pParams->linkInfo[i], 0, sizeof(NV2080_CTRL_NVLINK_LINK_STATUS_INFO)); + } + else + { + pDeviceInfo->domain = (pLoopGpu->gpuId >> 16) & 0xffff; + pDeviceInfo->bus = (pLoopGpu->gpuId >> 8) & 0xff; + pDeviceInfo->device = pLoopGpu->gpuId & 0xff; + + // Clear UUID + portMemSet(pDeviceInfo->deviceUUID, 0, sizeof(pDeviceInfo->deviceUUID)); + } + } + FOR_EACH_INDEX_IN_MASK_END; + } + + return status; + } + else + { + return NV_ERR_NOT_SUPPORTED; + } + } + + // Initialize link mask to 0 + pParams->enabledLinkMask = 0; + + if (!bMIGNvLinkP2PSupported) + { + NV_PRINTF(LEVEL_ERROR, "MIG NVLink P2P is not supported.\n"); + status = NV_OK; + return status; + } + + pTmpData = portMemAllocNonPaged(sizeof(*pTmpData)); + + if (pTmpData == NULL) + { + return NV_ERR_NO_MEMORY; + } + portMemSet(pTmpData, 0, sizeof(*pTmpData)); + + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && RMCFG_FEATURE_PLATFORM_GSP) + { + status = NV_ERR_NOT_SUPPORTED; + goto done; + } + else + { + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + + if (pKernelNvlink == NULL) + { + NV_PRINTF(LEVEL_INFO, "Kernel NVLink is unavailable. Returning.\n"); + status = NV_OK; + goto done; + } + + // Get the remote ends of the links from the nvlink core + if (!knvlinkIsForcedConfig(pGpu, pKernelNvlink) && + !(IS_RTLSIM(pGpu) && !pKernelNvlink->bForceEnableCoreLibRtlsims)) + { + // + // Get the nvlink connections for this device from the core + // If the function fails then the corelib doesn't have enough + // info to validate connectivity so we should mark the API call + // as not ready + // + status = knvlinkCoreGetRemoteDeviceInfo(pGpu, pKernelNvlink); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_INFO, "Nvlink is not ready yet!\n"); + return NV_ERR_NOT_READY; + } + } + + // + // Some links might have passed receiver detect (bridge is present), + // but might have failed to transition to safe mode (marginal links) + // Update connectedLinks and bridgedLinks mask for these links + // + knvlinkFilterBridgeLinks_HAL(pGpu, pKernelNvlink); + + pParams->enabledLinkMask = pKernelNvlink->enabledLinks; + + pTmpData->nvlinkLinkAndClockInfoParams.linkMask = pParams->enabledLinkMask; + pTmpData->nvlinkLinkAndClockInfoParams.bSublinkStateInst = pParams->bSublinkStateInst; + + status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, + NV2080_CTRL_CMD_NVLINK_GET_LINK_AND_CLOCK_INFO, + (void *)&pTmpData->nvlinkLinkAndClockInfoParams, + sizeof(pTmpData->nvlinkLinkAndClockInfoParams)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to collect nvlink status info!\n"); + goto done; + } + + FOR_EACH_INDEX_IN_MASK(32, i, pParams->enabledLinkMask) + { + pTmpData->nvlinkLinks[i].laneRxdetStatusMask = pKernelNvlink->nvlinkLinks[i].laneRxdetStatusMask; + +#if defined(INCLUDE_NVLINK_LIB) + pTmpData->nvlinkLinks[i].bConnected = pKernelNvlink->nvlinkLinks[i].remoteEndInfo.bConnected; + pTmpData->nvlinkLinks[i].remoteLinkNumber = pKernelNvlink->nvlinkLinks[i].remoteEndInfo.linkNumber; + pTmpData->nvlinkLinks[i].remoteDeviceType = pKernelNvlink->nvlinkLinks[i].remoteEndInfo.deviceType; + pTmpData->nvlinkLinks[i].remoteChipSid = pKernelNvlink->nvlinkLinks[i].remoteEndInfo.chipSid; + pTmpData->nvlinkLinks[i].remoteDomain = pKernelNvlink->nvlinkLinks[i].remoteEndInfo.domain; + pTmpData->nvlinkLinks[i].remoteBus = pKernelNvlink->nvlinkLinks[i].remoteEndInfo.bus; + pTmpData->nvlinkLinks[i].remoteDevice = pKernelNvlink->nvlinkLinks[i].remoteEndInfo.device; + pTmpData->nvlinkLinks[i].remoteFunction = pKernelNvlink->nvlinkLinks[i].remoteEndInfo.function; + pTmpData->nvlinkLinks[i].remotePciDeviceId = pKernelNvlink->nvlinkLinks[i].remoteEndInfo.pciDeviceId; + pTmpData->nvlinkLinks[i].bLoopbackSupported = knvlinkIsP2pLoopbackSupportedPerLink(pGpu, pKernelNvlink, i); + + if (pKernelNvlink->nvlinkLinks[i].core_link) + { + pParams->linkInfo[i].localLinkSid = pKernelNvlink->nvlinkLinks[i].core_link->localSid; + } +#endif + } + FOR_EACH_INDEX_IN_MASK_END; + + _getNvlinkStatus(pGpu, + &pTmpData->nvlinkLinkAndClockInfoParams, + pKernelNvlink->bridgeSensableLinks, + pKernelNvlink->bridgedLinks, + pKernelNvlink->ipVerNvlink, + pTmpData->nvlinkLinks, + pKernelNvlink->getProperty(pKernelNvlink, PDB_PROP_KNVLINK_ENABLED), + pKernelNvlink->getProperty(pKernelNvlink, PDB_PROP_KNVLINK_L2_POWER_STATE_ENABLED), + knvlinkIsForcedConfig(pGpu, pKernelNvlink), + pParams); + } +done: + portMemFree(pTmpData); + + return status; +} diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c index 8f51d738b..15976e289 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c @@ -334,6 +334,24 @@ knvlinkGetP2pConnectionStatus_IMPL return NV_ERR_INVALID_ARGUMENT; } + if(pKernelNvlink0->bIsGpuDegraded) + { + NV_PRINTF(LEVEL_INFO, + "NVLink P2P is NOT supported between GPU%d and GPU%d\n", + gpuGetInstance(pGpu0), gpuGetInstance(pGpu1)); + + return NV_ERR_NOT_SUPPORTED; + } + + if(pKernelNvlink1->bIsGpuDegraded) + { + NV_PRINTF(LEVEL_INFO, + "NVLink P2P is NOT supported between GPU%d and GPU%d\n", + gpuGetInstance(pGpu0), gpuGetInstance(pGpu1)); + + return NV_ERR_NOT_SUPPORTED; + } + if ((IS_RTLSIM(pGpu0) && !pKernelNvlink0->bForceEnableCoreLibRtlsims) || knvlinkIsForcedConfig(pGpu0, pKernelNvlink0)) { @@ -360,6 +378,27 @@ knvlinkGetP2pConnectionStatus_IMPL } numPeerLinks = knvlinkGetNumLinksToPeer(pGpu0, pKernelNvlink0, pGpu1); + + // + // Maybe knvlinkCoreGetRemoteDeviceInfo was never called on pGpu1. + // This can happen on systems where FM doesn't configure GPUs + // using RM control calls explicitly. + // + if ((numPeerLinks == 0) && gpuFabricProbeIsSupported(pGpu1)) + { + knvlinkCoreGetRemoteDeviceInfo(pGpu1, pKernelNvlink1); + + // Post topology link enable on links of remote GPU + status = knvlinkEnableLinksPostTopology_HAL(pGpu1, pKernelNvlink1, + pKernelNvlink1->enabledLinks); + if (status != NV_OK) + { + return status; + } + + numPeerLinks = knvlinkGetNumLinksToPeer(pGpu0, pKernelNvlink0, pGpu1); + } + if (numPeerLinks > 0) { if (knvlinkGetNumLinksToPeer(pGpu1, pKernelNvlink1, pGpu0) != numPeerLinks) @@ -422,7 +461,6 @@ knvlinkUpdateCurrentConfig_IMPL KernelCE *pKCe = NULL; NvBool bOwnsLock = NV_FALSE; NV_STATUS status = NV_OK; - NvU32 i; if (osAcquireRmSema(pSys->pSema) == NV_OK) { @@ -480,17 +518,13 @@ knvlinkUpdateCurrentConfig_IMPL pGpu->setProperty(pGpu, PDB_PROP_GPU_NVLINK_SYSMEM, params.bNvlinkSysmemEnabled); // Update the PCE-LCE mappings - for (i = 0; i < ENG_CE__SIZE_1; i++) + status = kceFindFirstInstance(pGpu, &pKCe); + if (status == NV_OK) { - pKCe = GPU_GET_KCE(pGpu, i); - if (pKCe) + status = kceTopLevelPceLceMappingsUpdate(pGpu, pKCe); + if (status != NV_OK) { - status = kceTopLevelPceLceMappingsUpdate(pGpu, pKCe); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "Failed to update PCE-LCE mappings\n"); - } - break; + NV_PRINTF(LEVEL_ERROR, "Failed to update PCE-LCE mappings\n"); } } @@ -506,6 +540,172 @@ fail: return status; } +/*! + * @brief Clients to register their callback functions for inband data + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelNvlink KernelNvlink pointer + * @param[in] params callback functions + */ +NV_STATUS +knvlinkRegisterInbandCallback_IMPL +( + OBJGPU *pGpu, + KernelNvlink *pKernelNvlink, + NVLINK_INBAND_MSG_CALLBACK *params +) +{ + if (params->messageType >= NVLINK_INBAND_MSG_TYPE_MAX) + { + NV_PRINTF(LEVEL_ERROR, "Wrong msgType. Not registering\n"); + return NV_ERR_INVALID_PARAMETER; + } + + if (pKernelNvlink->inbandCallback[params->messageType].pCallback != NULL) + { + NV_PRINTF(LEVEL_ERROR, "Callback has been already registered" + "for msgType %d\n", params->messageType); + return NV_ERR_IN_USE; + } + + pKernelNvlink->inbandCallback[params->messageType].pCallback = params->pCallback; + pKernelNvlink->inbandCallback[params->messageType].wqItemFlags = params->wqItemFlags; + + return NV_OK; +} + +/*! + * @brief Clients to unregister their callback functions for inband data + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelNvlink KernelNvlink pointer + * @param[in] msgType Inband Message type + */ +NV_STATUS +knvlinkUnregisterInbandCallback_IMPL +( + OBJGPU *pGpu, + KernelNvlink *pKernelNvlink, + NvU16 msgType +) +{ + if (msgType >= NVLINK_INBAND_MSG_TYPE_MAX) + { + NV_PRINTF(LEVEL_ERROR, "Wrong msgType. Not unregistering\n"); + return NV_ERR_INVALID_PARAMETER; + } + + pKernelNvlink->inbandCallback[msgType].pCallback = NULL; + pKernelNvlink->inbandCallback[msgType].wqItemFlags = 0; + + return NV_OK; +} + +void +knvlinkInbandMsgCallbackDispatcher_WORKITEM +( + NvU32 gpuInstance, + void *pData +) +{ + OBJGPU *pGpu = NULL; + nvlink_inband_msg_header_t *pHeader; + KernelNvlink *pKernelNvlink; + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pMessage = pData; + NvU8 *pRsvd = NULL; + + pGpu = gpumgrGetGpu(gpuInstance); + if (pGpu == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Invalid GPU\n"); + return; + } + + pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + if (pKernelNvlink == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Invalid NVLink state\n"); + return; + } + + pHeader = (nvlink_inband_msg_header_t *)pMessage->data; + + // Assert reserved in msgHdr are zero + pRsvd = &pHeader->reserved[0]; + NV_ASSERT((pRsvd[0] == 0) && portMemCmp(pRsvd, pRsvd + 1, + sizeof(pHeader->reserved) - 1) == 0); + + pKernelNvlink->inbandCallback[pHeader->type].pCallback(pGpu, pData); +} + +NV_STATUS +knvlinkInbandMsgCallbackDispatcher_IMPL +( + OBJGPU *pGpu, + KernelNvlink *pKernelNvlink, + NvU32 dataSize, + NvU8 *pMessage +) +{ + NV_STATUS status; + nvlink_inband_msg_header_t *pHeader; + NVLINK_INBAND_MSG_CALLBACK *pParams; + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pData = NULL; + OBJOS *pOS = GPU_GET_OS(pGpu); + + pHeader = (nvlink_inband_msg_header_t *)pMessage; + + if (pHeader->type >= NVLINK_INBAND_MSG_TYPE_MAX) + { + NV_PRINTF(LEVEL_ERROR, "Message type received is Out of Bounds. Dropping the msg\n"); + return NV_ERR_INVALID_REQUEST; + } + + pParams = &pKernelNvlink->inbandCallback[pHeader->type]; + if (pParams->pCallback == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Callback not registered for the message type %d\n", pHeader->type); + return NV_ERR_INVALID_REQUEST; + } + + pData = portMemAllocNonPaged(sizeof(NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS)); + if (pData == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Out of memory, Dropping message\n"); + return NV_ERR_NO_MEMORY; + } + + pData->dataSize = dataSize; + portMemCopy(pData->data, pData->dataSize, pMessage, dataSize); + + status = pOS->osQueueWorkItemWithFlags(pGpu, knvlinkInbandMsgCallbackDispatcher_WORKITEM, pData, + pParams->wqItemFlags); + if (status != NV_OK) + { + portMemFree(pData); + return status; + } + + return NV_OK; +} + +NV_STATUS +knvlinkSendInbandData_IMPL +( + OBJGPU *pGpu, + KernelNvlink *pKernelNvlink, + NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS *pParams +) +{ + NV_STATUS status; + + status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, + NV2080_CTRL_CMD_NVLINK_INBAND_SEND_DATA, + (void *)pParams, + sizeof(*pParams)); + + return status; +} /*! * @brief Return the mask of links enabled on the system * @@ -609,6 +809,27 @@ knvlinkGetLinkMaskToPeer_IMPL ) { NvU32 peerLinkMask = 0; + KernelNvlink *pKernelNvlink1 = NULL; + + pKernelNvlink1 = GPU_GET_KERNEL_NVLINK(pGpu1); + + if (pKernelNvlink1 == NULL) + { + NV_PRINTF(LEVEL_ERROR, + "on GPU%d NVLink is disabled.\n", gpuGetInstance(pGpu1)); + + return 0; + } + + if(pKernelNvlink0->bIsGpuDegraded) + { + return peerLinkMask; + } + + if(pKernelNvlink1->bIsGpuDegraded) + { + return peerLinkMask; + } if (!knvlinkIsForcedConfig(pGpu0, pKernelNvlink0)) { @@ -807,8 +1028,8 @@ knvlinkPrepareForXVEReset_IMPL // Remove all NVLink mappings in HSHUB config registers to init values if (!API_GPU_IN_RESET_SANITY_CHECK(pGpu) && !pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_LOST)) - status = knvlinkRemoveMapping_HAL(pGpu, pKernelNvlink, NV_TRUE, ((1 << NVLINK_MAX_PEERS_SW) - 1), - NV_FALSE /* bL2Entry */); + status = knvlinkRemoveMapping_HAL(pGpu, pKernelNvlink, NV_TRUE, ((1 << NVLINK_MAX_PEERS_SW) - 1), + NV_FALSE /* bL2Entry */); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, @@ -902,7 +1123,7 @@ knvlinkSetPowerFeatures_IMPL (pKernelNvlink->bDisableSingleLaneMode ? NV_FALSE : NV_TRUE)); // NVLink L2 is supported only on MODS and Windows LDDM - if (RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM || RMCFG_FEATURE_PLATFORM_MODS) + if (RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM || RMCFG_FEATURE_MODS_FEATURES) { pKernelNvlink->setProperty(pKernelNvlink, PDB_PROP_KNVLINK_L2_POWER_STATE_ENABLED, (pKernelNvlink->bDisableL2Mode ? NV_FALSE : NV_TRUE)); @@ -945,7 +1166,8 @@ knvlinkDetectNvswitchProxy_IMPL pKernelNvlink->fabricBaseAddr = NVLINK_INVALID_FABRIC_ADDR; if (pSys->getProperty(pSys, PDB_PROP_SYS_NVSWITCH_IS_PRESENT) || - pSys->getProperty(pSys, PDB_PROP_SYS_FABRIC_MANAGER_IS_REGISTERED)) + pSys->getProperty(pSys, PDB_PROP_SYS_FABRIC_MANAGER_IS_REGISTERED) || + GPU_IS_NVSWITCH_DETECTED(pGpu)) { return; } @@ -1209,9 +1431,16 @@ knvlinkUpdateLinkConnectionStatus_IMPL #if defined(INCLUDE_NVLINK_LIB) - params.bConnected = pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.bConnected; + params.bConnected = pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.bConnected; params.remoteDeviceType = pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.deviceType; params.remoteLinkNumber = pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.linkNumber; + params.remoteChipSid = pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.chipSid; + params.remoteDomain = pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.domain; + params.remoteBus = pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.bus; + params.remoteDevice = pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.device; + params.remoteFunction = pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.function; + params.remotePciDeviceId = pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.pciDeviceId; + params.laneRxdetStatusMask = pKernelNvlink->nvlinkLinks[linkId].laneRxdetStatusMask; #endif @@ -1608,104 +1837,6 @@ knvlinkSyncLaneShutdownProps_IMPL return NV_OK; } -/*! - * @brief Set unique fabric address for NVSwitch enabled systems. - * - * @param[in] pGpu OBJGPU pointer - * @param[in] pKernelNvlink KernelNvlink pointer - * @param[in] fabricBaseAddr Fabric Address to set - * - * @returns On success, sets unique fabric address and returns NV_OK. - * On failure, returns NV_ERR_XXX. - */ -NV_STATUS -knvlinkSetUniqueFabricBaseAddress_IMPL -( - OBJGPU *pGpu, - KernelNvlink *pKernelNvlink, - NvU64 fabricBaseAddr -) -{ - NV_STATUS status = NV_OK; - - if (!knvlinkIsForcedConfig(pGpu, pKernelNvlink)) - { - knvlinkCoreGetRemoteDeviceInfo(pGpu, pKernelNvlink); - - knvlinkEnableLinksPostTopology_HAL(pGpu, pKernelNvlink, - pKernelNvlink->enabledLinks); - } - - if (!knvlinkIsGpuConnectedToNvswitch(pGpu, pKernelNvlink)) - { - NV_PRINTF(LEVEL_ERROR, - "Operation failed due to no NVSwitch connectivity to the " - "GPU %x\n", pGpu->gpuInstance); - return NV_ERR_INVALID_STATE; - } - - status = knvlinkValidateFabricBaseAddress_HAL(pGpu, pKernelNvlink, - fabricBaseAddr); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "Fabric addr validation failed for GPU %x\n", - pGpu->gpuInstance); - return status; - } - - if (IsSLIEnabled(pGpu)) - { - NV_PRINTF(LEVEL_ERROR, - "Operation is unsupported on SLI enabled GPU %x\n", - pGpu->gpuInstance); - return NV_ERR_NOT_SUPPORTED; - } - - if (pKernelNvlink->fabricBaseAddr == fabricBaseAddr) - { - NV_PRINTF(LEVEL_INFO, - "The same fabric addr is being re-assigned to GPU %x\n", - pGpu->gpuInstance); - return NV_OK; - } - - if (pKernelNvlink->fabricBaseAddr != NVLINK_INVALID_FABRIC_ADDR) - { - NV_PRINTF(LEVEL_ERROR, "Fabric addr is already assigned to GPU %x\n", - pGpu->gpuInstance); - return NV_ERR_STATE_IN_USE; - } - - // - // Update GMMU peer field descriptor. - // We can safely defer reinitialization of peer field descriptor to this - // call because RM doesn't allow any P2P operations until FM assigns fabric - // addresses. - // - NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS params; - - portMemSet(¶ms, 0, sizeof(params)); - params.bGet = NV_FALSE; - params.addr = fabricBaseAddr; - - status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, - NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR, - (void *)¶ms, sizeof(params)); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "Failed to stash fabric address for GPU %x\n", - pGpu->gpuInstance); - return status; - } - - pKernelNvlink->fabricBaseAddr = fabricBaseAddr; - - NV_PRINTF(LEVEL_ERROR, "Fabric base addr %llx is assigned to GPU %x\n", - pKernelNvlink->fabricBaseAddr, pGpu->gpuInstance); - - return NV_OK; -} - /*! * @brief Get the number of active links allowed per IOCTRL * @@ -1724,9 +1855,7 @@ knvlinkGetNumActiveLinksPerIoctrl_IMPL { NV_STATUS status; NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL_PARAMS params; - portMemSet(¶ms, 0, sizeof(params)); - status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, NV2080_CTRL_INTERNAL_NVLINK_GET_NUM_ACTIVE_LINK_PER_IOCTRL, (void *)¶ms, sizeof(params)); @@ -1735,7 +1864,6 @@ knvlinkGetNumActiveLinksPerIoctrl_IMPL NV_PRINTF(LEVEL_ERROR, "Failed to get the number of active links per IOCTRL\n"); return 0; } - return params.numActiveLinksPerIoctrl; } @@ -1757,9 +1885,7 @@ knvlinkGetTotalNumLinksPerIoctrl_IMPL { NV_STATUS status; NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS params; - portMemSet(¶ms, 0, sizeof(params)); - status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL, (void *)¶ms, sizeof(params)); @@ -1768,7 +1894,6 @@ knvlinkGetTotalNumLinksPerIoctrl_IMPL NV_PRINTF(LEVEL_ERROR, "Failed to get the total number of links per IOCTRL\n"); return 0; } - return params.numLinksPerIoctrl; } diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkapi.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkapi.c index 7b8743832..d2e1d760e 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkapi.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkapi.c @@ -33,598 +33,6 @@ #include "vgpu/rpc.h" #include "nvRmReg.h" -// -// subdeviceCtrlCmdBusGetNvlinkCaps -// Get the Nvlink global capabilities -// -NV_STATUS -subdeviceCtrlCmdBusGetNvlinkCaps_IMPL -( - Subdevice *pSubdevice, - NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS *pParams -) -{ - OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - - return knvlinkCtrlCmdBusGetNvlinkCaps(pGpu, pParams); -} - -// -// knvlinkCtrlCmdBusGetNvlinkCaps -// Inner function of subdeviceCtrlCmdBusGetNvlinkCaps for internal RM direct function call -// Get the Nvlink global capabilities -// -NV_STATUS -knvlinkCtrlCmdBusGetNvlinkCaps -( - OBJGPU *pGpu, - NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS *pParams -) -{ - KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); - KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); - NV_STATUS status = NV_OK; - NvBool bMIGNvLinkP2PSupported = ((pKernelMIGManager != NULL) && - kmigmgrIsMIGNvlinkP2PSupported(pGpu, pKernelMIGManager)); - NvU8 tempCaps[NV2080_CTRL_NVLINK_CAPS_TBL_SIZE]; - - // - // vGPU: - // - // Since vGPU does all real hardware management in the - // host, if we are in guest OS (where IS_VIRTUAL(pGpu) is true), - // do an RPC to the host to get blacklist information from host RM - // - if (IS_VIRTUAL(pGpu)) - { - CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); - RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; - - NV_RM_RPC_CONTROL(pGpu, pRmCtrlParams->hClient, pRmCtrlParams->hObject, pRmCtrlParams->cmd, - pRmCtrlParams->pParams, pRmCtrlParams->paramsSize, status); - return status; - } - - portMemSet(tempCaps, 0, NV2080_CTRL_NVLINK_CAPS_TBL_SIZE); - - // Initialize link masks to 0 - pParams->enabledLinkMask = 0; - pParams->discoveredLinkMask = 0; - - if (pKernelNvlink == NULL) - { - NV_PRINTF(LEVEL_INFO, "NVLink is unavailable. Returning.\n"); - status = NV_OK; - return status; - } - - // With MIG memory partitioning, NvLink P2P or sysmem accesses are not allowed - if (bMIGNvLinkP2PSupported) - { - RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _SUPPORTED); - RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _SYSMEM_ACCESS); - RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _P2P_SUPPORTED); - RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _P2P_ATOMICS); - - // - // Some links might have passed receiver detect (bridge is present), - // but might have failed to transition to safe mode (marginal links) - // Update connectedLinks and bridgedLinks mask for these links - // - knvlinkFilterBridgeLinks_HAL(pGpu, pKernelNvlink); - - // - // This GPU supports SLI bridge sensing if any of the links - // support bridge sensing. - // - if (pKernelNvlink->bridgeSensableLinks) - { - RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _SLI_BRIDGE_SENSABLE); - } - - // This GPU has an SLI bridge if any of the links are bridged - if (pKernelNvlink->bridgedLinks) - { - RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _SLI_BRIDGE); - } - - // NVLink versions beyond the first support sysmem atomics - if (pKernelNvlink->ipVerNvlink != NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_1_0) - { - RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _SYSMEM_ATOMICS); - } - } - - switch (pKernelNvlink->ipVerNvlink) - { - case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0: - { - pParams->lowestNvlinkVersion = NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0; - pParams->highestNvlinkVersion = NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0; - pParams->lowestNciVersion = NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_4_0; - pParams->highestNciVersion = NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_4_0; - - // Supported power states - RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _POWER_STATE_L0); - RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _POWER_STATE_L1); - break; - } - case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1: - { - pParams->lowestNvlinkVersion = NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1; - pParams->highestNvlinkVersion = NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1; - pParams->lowestNciVersion = NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_1; - pParams->highestNciVersion = NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_1; - - // Supported power states - RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _POWER_STATE_L0); - RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _POWER_STATE_L2); - break; - } - case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_0: - { - pParams->lowestNvlinkVersion = NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_0; - pParams->highestNvlinkVersion = NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_0; - pParams->lowestNciVersion = NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_0; - pParams->highestNciVersion = NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_0; - - // Supported power states - RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _POWER_STATE_L0); - RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _POWER_STATE_L2); - break; - } - case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_2: - { - pParams->lowestNvlinkVersion = NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_2; - pParams->highestNvlinkVersion = NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_2; - pParams->lowestNciVersion = NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_2; - pParams->highestNciVersion = NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_2; - - // Supported power states - RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _POWER_STATE_L0); - RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _POWER_STATE_L2); - break; - } - case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_0: - { - pParams->lowestNvlinkVersion = NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_0; - pParams->highestNvlinkVersion = NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_0; - pParams->lowestNciVersion = NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_0; - pParams->highestNciVersion = NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_2_0; - - // Supported power states - RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _POWER_STATE_L0); - break; - } - default: - { - pParams->lowestNvlinkVersion = NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_1_0; - pParams->highestNvlinkVersion = NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_1_0; - pParams->lowestNciVersion = NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_1_0; - pParams->highestNciVersion = NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_1_0; - - // Supported power states - RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _POWER_STATE_L0); - break; - } - } - - portMemCopy(&pParams->capsTbl, NV2080_CTRL_NVLINK_CAPS_TBL_SIZE, tempCaps, NV2080_CTRL_NVLINK_CAPS_TBL_SIZE); - - pParams->discoveredLinkMask = knvlinkGetDiscoveredLinkMask(pGpu, pKernelNvlink); - pParams->enabledLinkMask = knvlinkGetEnabledLinkMask(pGpu, pKernelNvlink); - - return status; -} - -// -// subdeviceCtrlCmdBusGetNvlinkStatus -// Get the Nvlink per link capabilities -// -NV_STATUS -subdeviceCtrlCmdBusGetNvlinkStatus_IMPL -( - Subdevice *pSubdevice, - NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *pParams -) -{ - OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); - KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); - - NvBool bMIGNvLinkP2PSupported = ((pKernelMIGManager != NULL) && - kmigmgrIsMIGNvlinkP2PSupported(pGpu, pKernelMIGManager)); - OBJGPU *remotePeer0 = NULL; - NV_STATUS status = NV_OK; - NvU8 i = 0; - NvU8 tempCaps[NV2080_CTRL_NVLINK_CAPS_TBL_SIZE]; - NvU32 r = 0; - NvBool bPeerLink, bSysmemLink, bSwitchLink; - NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS nvlinkLinkAndClockInfoParams; - - // - // vGPU: - // - // Since vGPU does all real hardware management in the - // host, if we are in guest OS (where IS_VIRTUAL(pGpu) is true), - // do an RPC to the host to get blacklist information from host RM - // - if (IS_VIRTUAL(pGpu)) - { - // RPC for this RmCtrl was implemented as an effort of enabling NVLINK P2P - // on vGPU. As NVLINK P2P is supported Pascal+ onwards, we return NOT_SUPPORTED - // pre-Pascal. - if (IsPASCALorBetter(pGpu)) - { - CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); - RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; - - NV_RM_RPC_CONTROL(pGpu, pRmCtrlParams->hClient, pRmCtrlParams->hObject, pRmCtrlParams->cmd, - pRmCtrlParams->pParams, pRmCtrlParams->paramsSize, status); - return status; - } - else - { - return NV_ERR_NOT_SUPPORTED; - } - } - - // Initialize link mask to 0 - pParams->enabledLinkMask = 0; - - if ((pKernelNvlink == NULL) || !bMIGNvLinkP2PSupported) - { - NV_PRINTF(LEVEL_INFO, "NVLink is unavailable. Returning.\n"); - status = NV_OK; - return status; - } - - portMemSet(tempCaps, 0, NV2080_CTRL_NVLINK_CAPS_TBL_SIZE); - - // Get the remote ends of the links from the nvlink core - if (!knvlinkIsForcedConfig(pGpu, pKernelNvlink) && - !(IS_RTLSIM(pGpu) && !pKernelNvlink->bForceEnableCoreLibRtlsims)) - { - // Get the nvlink connections for this device from the core - knvlinkCoreGetRemoteDeviceInfo(pGpu, pKernelNvlink); - } - - pParams->enabledLinkMask = pKernelNvlink->enabledLinks; - - r = pParams->enabledLinkMask; - while (r >>= 1 ) i++; - - NV_ASSERT(i <= NV2080_CTRL_NVLINK_MAX_LINKS); - - // - // Some links might have passed receiver detect (bridge is present), - // but might have failed to transition to safe mode (marginal links) - // Update connectedLinks and bridgedLinks mask for these links - // - knvlinkFilterBridgeLinks_HAL(pGpu, pKernelNvlink); - - portMemSet(&nvlinkLinkAndClockInfoParams, 0, sizeof(nvlinkLinkAndClockInfoParams)); - - nvlinkLinkAndClockInfoParams.linkMask = pParams->enabledLinkMask; - nvlinkLinkAndClockInfoParams.bSublinkStateInst = pParams->bSublinkStateInst; - - status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, - NV2080_CTRL_CMD_NVLINK_GET_LINK_AND_CLOCK_INFO, - (void *)&nvlinkLinkAndClockInfoParams, - sizeof(nvlinkLinkAndClockInfoParams)); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "Failed to collect nvlink status info!\n"); - return status; - } - - FOR_EACH_INDEX_IN_MASK(32, i, pParams->enabledLinkMask) - { - bPeerLink = NV_FALSE; - bSysmemLink = NV_FALSE; - bSwitchLink = NV_FALSE; - NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_VALUES *pLinkAndClockValues; - - pLinkAndClockValues = &nvlinkLinkAndClockInfoParams.linkInfo[i]; - - portMemSet(tempCaps, 0, NV2080_CTRL_NVLINK_CAPS_TBL_SIZE); - - (pKernelNvlink->getProperty(pKernelNvlink, PDB_PROP_KNVLINK_ENABLED)) ? - (RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _VALID)) : 0; - - if (pLinkAndClockValues->bLinkConnectedToSystem) - { - // Tag as a Sysmem link - bSysmemLink = NV_TRUE; - - RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _SYSMEM_ACCESS); - - // NVLink versions beyond the first support sysmem atomics - if (pKernelNvlink->ipVerNvlink != NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_1_0 ) - { - RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _SYSMEM_ATOMICS); - } - } - - if (pLinkAndClockValues->bLinkConnectedToPeer) - { - // Tag as Peer link - bPeerLink = NV_TRUE; - - RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _P2P_SUPPORTED); - RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _P2P_ATOMICS); - } - - // Indicate per-link bridge sense status - if (pKernelNvlink->bridgeSensableLinks & NVBIT(i)) - { - RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _SLI_BRIDGE_SENSABLE); - } - - // Indicate per-link bridge status - if (pKernelNvlink->bridgedLinks & NVBIT(i)) - { - RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _SLI_BRIDGE); - } - - // Set the power states caps - switch (pKernelNvlink->ipVerNvlink) - { - case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_0: - RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _POWER_STATE_L0); - break; - - case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0: - case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1: - case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_0: - case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_2: - RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _POWER_STATE_L0); - if (pKernelNvlink->getProperty(pKernelNvlink, PDB_PROP_KNVLINK_L2_POWER_STATE_ENABLED)) - { - RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _POWER_STATE_L2); - } - break; - - default: - RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _POWER_STATE_L0); - break; - } - - portMemCopy(&pParams->linkInfo[i].capsTbl, NV2080_CTRL_NVLINK_CAPS_TBL_SIZE, tempCaps, NV2080_CTRL_NVLINK_CAPS_TBL_SIZE); - - pParams->linkInfo[i].phyType = NV2080_CTRL_NVLINK_STATUS_PHY_NVHS; - pParams->linkInfo[i].subLinkWidth = pLinkAndClockValues->subLinkWidth; - pParams->linkInfo[i].linkState = pLinkAndClockValues->linkState; - pParams->linkInfo[i].txSublinkStatus = (NvU8) pLinkAndClockValues->txSublinkState; - pParams->linkInfo[i].rxSublinkStatus = (NvU8) pLinkAndClockValues->rxSublinkState; - - // Initialize the lane reversal state information for the link - pParams->linkInfo[i].bLaneReversal = pLinkAndClockValues->bLaneReversal; - - switch (pKernelNvlink->ipVerNvlink) - { - case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0: - pParams->linkInfo[i].nvlinkVersion = NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_4_0; - pParams->linkInfo[i].nciVersion = NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_4_0; - break; - case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1: - pParams->linkInfo[i].nvlinkVersion = NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_1; - pParams->linkInfo[i].nciVersion = NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_1; - break; - case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_0: - pParams->linkInfo[i].nvlinkVersion = NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_0; - pParams->linkInfo[i].nciVersion = NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_0; - break; - case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_2: - pParams->linkInfo[i].nvlinkVersion = NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_2; - pParams->linkInfo[i].nciVersion = NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_2_2; - break; - case NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_0: - pParams->linkInfo[i].nvlinkVersion = NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_0; - pParams->linkInfo[i].nciVersion = NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_2_0; - break; - default: - pParams->linkInfo[i].nvlinkVersion = NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_1_0; - pParams->linkInfo[i].nciVersion = NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_1_0; - break; - } - pParams->linkInfo[i].phyVersion = NV2080_CTRL_NVLINK_STATUS_NVHS_VERSION_1_0; - - // Initialize the connection information for the link - pParams->linkInfo[i].connected = NV2080_CTRL_NVLINK_STATUS_CONNECTED_FALSE; - pParams->linkInfo[i].remoteDeviceLinkNumber = NV2080_CTRL_NVLINK_STATUS_REMOTE_LINK_NUMBER_INVALID; - pParams->linkInfo[i].remoteDeviceInfo.deviceType = NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NONE; - pParams->linkInfo[i].localDeviceLinkNumber = i; - pParams->linkInfo[i].laneRxdetStatusMask = pKernelNvlink->nvlinkLinks[i].laneRxdetStatusMask; - - // Set the device information for the local end of the link - pParams->linkInfo[i].localDeviceInfo.domain = gpuGetDomain(pGpu); - pParams->linkInfo[i].localDeviceInfo.bus = gpuGetBus(pGpu); - pParams->linkInfo[i].localDeviceInfo.device = gpuGetDevice(pGpu); - pParams->linkInfo[i].localDeviceInfo.function = 0; - pParams->linkInfo[i].localDeviceInfo.pciDeviceId = pGpu->idInfo.PCIDeviceID; - pParams->linkInfo[i].localDeviceInfo.deviceType = NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU; -#if defined(INCLUDE_NVLINK_LIB) - if (pKernelNvlink->nvlinkLinks[i].core_link) - { - pParams->linkInfo[i].localLinkSid = pKernelNvlink->nvlinkLinks[i].core_link->localSid; - } -#endif - - // Record the local end of the link's deviceIdFlags - if(pGpu->idInfo.PCIDeviceID) - { - pParams->linkInfo[i].localDeviceInfo.deviceIdFlags = - FLD_SET_DRF(2080_CTRL_NVLINK, _DEVICE_INFO, _DEVICE_ID_FLAGS, _PCI, - pParams->linkInfo[i].localDeviceInfo.deviceIdFlags); - } - - // - // Get clock related state - // NOTE: to be depricated HW terminology conforming versions - // - pParams->linkInfo[i].nvlinkLinkClockKHz = pLinkAndClockValues->nvlinkLinkClockKHz; - pParams->linkInfo[i].nvlinkRefClkSpeedKHz = nvlinkLinkAndClockInfoParams.nvlinkRefClkSpeedKHz; - pParams->linkInfo[i].nvlinkCommonClockSpeedKHz = pParams->linkInfo[i].nvlinkLinkClockKHz / 16; - - pParams->linkInfo[i].nvlinkCommonClockSpeedMhz = pParams->linkInfo[i].nvlinkCommonClockSpeedKHz / 1000; - - // Clock speed and Data rate info conforming with HW terminology - pParams->linkInfo[i].nvlinkLineRateMbps = pLinkAndClockValues->nvlinkLineRateMbps; - pParams->linkInfo[i].nvlinkLinkClockMhz = pLinkAndClockValues->nvlinkLinkClockMhz; - pParams->linkInfo[i].nvlinkLinkDataRateKiBps = pLinkAndClockValues->nvlinkLinkDataRateKiBps; - pParams->linkInfo[i].nvlinkRefClkType = pLinkAndClockValues->nvlinkRefClkType; - pParams->linkInfo[i].nvlinkRefClkSpeedMhz = pLinkAndClockValues->nvlinkReqLinkClockMhz; - - -#if defined(INCLUDE_NVLINK_LIB) - - if (pKernelNvlink->nvlinkLinks[i].remoteEndInfo.bConnected) - { - pParams->linkInfo[i].connected = NV2080_CTRL_NVLINK_STATUS_CONNECTED_TRUE; - pParams->linkInfo[i].remoteDeviceLinkNumber = (NvU8) pKernelNvlink->nvlinkLinks[i].remoteEndInfo.linkNumber; - pParams->linkInfo[i].remoteLinkSid = pKernelNvlink->nvlinkLinks[i].remoteEndInfo.chipSid; - - // Set the device information for the remote end of the link - pParams->linkInfo[i].remoteDeviceInfo.domain = pKernelNvlink->nvlinkLinks[i].remoteEndInfo.domain; - pParams->linkInfo[i].remoteDeviceInfo.bus = pKernelNvlink->nvlinkLinks[i].remoteEndInfo.bus; - pParams->linkInfo[i].remoteDeviceInfo.device = pKernelNvlink->nvlinkLinks[i].remoteEndInfo.device; - pParams->linkInfo[i].remoteDeviceInfo.function = pKernelNvlink->nvlinkLinks[i].remoteEndInfo.function; - pParams->linkInfo[i].remoteDeviceInfo.pciDeviceId = pKernelNvlink->nvlinkLinks[i].remoteEndInfo.pciDeviceId; - pParams->linkInfo[i].remoteDeviceInfo.deviceType = pKernelNvlink->nvlinkLinks[i].remoteEndInfo.deviceType; - - // Update the device Id flags for PCI - if (pKernelNvlink->nvlinkLinks[i].remoteEndInfo.pciDeviceId) - { - pParams->linkInfo[i].remoteDeviceInfo.deviceIdFlags |= - FLD_SET_DRF(2080_CTRL_NVLINK, _DEVICE_INFO, _DEVICE_ID_FLAGS, _PCI, - pParams->linkInfo[i].remoteDeviceInfo.deviceIdFlags); - } - - // Check the PCI dbdf values to confirm the device on remote end - if (NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_PCI & pParams->linkInfo[i].remoteDeviceInfo.deviceIdFlags) - { - if (!knvlinkIsP2pLoopbackSupportedPerLink(pGpu, pKernelNvlink, i)) - { - pParams->linkInfo[i].loopProperty = NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_NONE; - continue; - } - } - - pParams->linkInfo[i].loopProperty = pParams->linkInfo[i].remoteDeviceLinkNumber == i ? - NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPBACK : - NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPOUT; - } -#endif - - // Per-link ForceConfig handling (non-legacy Arch ForceConfig only) - if (knvlinkIsForcedConfig(pGpu, pKernelNvlink)) - { - if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_EMULATION)) - { - pParams->linkInfo[i].linkState = NV2080_CTRL_NVLINK_STATUS_LINK_STATE_ACTIVE; - pParams->linkInfo[i].rxSublinkStatus = NV2080_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_HIGH_SPEED_1; - pParams->linkInfo[i].txSublinkStatus = NV2080_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_HIGH_SPEED_1; - } - - pParams->linkInfo[i].connected = NV_TRUE; - pParams->linkInfo[i].loopProperty = NV_FALSE; - pParams->linkInfo[i].remoteDeviceLinkNumber = i; - if (!pParams->linkInfo[i].nvlinkLinkClockMhz) - pParams->linkInfo[i].nvlinkLinkClockMhz = pLinkAndClockValues->nvlinkReqLinkClockMhz; - - // Expose remote device as EBRIDGE if forced only sysmem - if (bSysmemLink && !bPeerLink && !bSwitchLink) - { - pParams->linkInfo[i].remoteDeviceInfo.domain = 0; - pParams->linkInfo[i].remoteDeviceInfo.bus = FORCED_SYSMEM_PCI_BUS; - pParams->linkInfo[i].remoteDeviceInfo.device = 0; - pParams->linkInfo[i].remoteDeviceInfo.function = i; - pParams->linkInfo[i].remoteDeviceInfo.pciDeviceId = FORCED_SYSMEM_DEVICE_ID; - pParams->linkInfo[i].remoteDeviceInfo.deviceType = FORCED_SYSMEM_DEVICE_TYPE; - - pParams->linkInfo[i].remoteDeviceInfo.deviceIdFlags |= - FLD_SET_DRF(2080_CTRL_NVLINK, _DEVICE_INFO, _DEVICE_ID_FLAGS, _PCI, - pParams->linkInfo[i].remoteDeviceInfo.deviceIdFlags); - } - - // Expose remote device as GPU if forced only peer - if (bPeerLink && !bSysmemLink && !bSwitchLink) - { - remotePeer0 = gpumgrGetGpu(pGpu->gpuInstance == 0 ? 1 : 0); - if (NULL == remotePeer0) - { - remotePeer0 = pGpu; - } - - // - // Ensure the remote is actually a GPU that supports NVLink. - // If it is not, we should stick with the current GPU as - // this is likely a loopback config. See Bug 1786206. - // - if (remotePeer0 != pGpu) - { - KernelNvlink *pRemoteKernelNvlink = GPU_GET_KERNEL_NVLINK(remotePeer0); - if (pRemoteKernelNvlink) - { - if (pRemoteKernelNvlink->discoveredLinks == 0) - { - // There are no links on this remote, fall back to loopback. - remotePeer0 = pGpu; - } - } - else - { - // NVLink not present on this remote, fall back to loopback. - remotePeer0 = pGpu; - } - } - - pParams->linkInfo[i].remoteDeviceInfo.domain = gpuGetDomain(remotePeer0); - pParams->linkInfo[i].remoteDeviceInfo.bus = gpuGetBus(remotePeer0); - pParams->linkInfo[i].remoteDeviceInfo.device = gpuGetDevice(remotePeer0); - pParams->linkInfo[i].remoteDeviceInfo.function = 0; - pParams->linkInfo[i].remoteDeviceInfo.pciDeviceId = remotePeer0->idInfo.PCIDeviceID; - pParams->linkInfo[i].remoteDeviceInfo.deviceType = NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU; - - // This config is either in loopback or real 1/1 P2P, nothing else. - if (gpuGetDBDF(remotePeer0) == gpuGetDBDF(pGpu)) - { - pParams->linkInfo[i].loopProperty = NV2080_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPBACK; - } - - pParams->linkInfo[i].remoteDeviceInfo.deviceIdFlags |= - FLD_SET_DRF(2080_CTRL_NVLINK, _DEVICE_INFO, _DEVICE_ID_FLAGS, _PCI, - pParams->linkInfo[i].remoteDeviceInfo.deviceIdFlags); - } - - // - // Expose remote device as Switch if requested - // Requested can be either forced sysmem and peer or - // if either and requested as switch - // - if ( (bSysmemLink && bPeerLink) || - ((bSysmemLink || bPeerLink) && bSwitchLink)) - { - pParams->linkInfo[i].remoteDeviceInfo.domain = 0; - pParams->linkInfo[i].remoteDeviceInfo.bus = FORCED_SWITCH_PCI_BUS; - pParams->linkInfo[i].remoteDeviceInfo.device = 0; - pParams->linkInfo[i].remoteDeviceInfo.function = i; - pParams->linkInfo[i].remoteDeviceInfo.pciDeviceId = FORCED_SWITCH_DEVICE_ID; - pParams->linkInfo[i].remoteDeviceInfo.deviceType = NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_SWITCH; - - pParams->linkInfo[i].remoteDeviceInfo.deviceIdFlags |= - FLD_SET_DRF(2080_CTRL_NVLINK, _DEVICE_INFO, _DEVICE_ID_FLAGS, _PCI, - pParams->linkInfo[i].remoteDeviceInfo.deviceIdFlags); - } - } - } - FOR_EACH_INDEX_IN_MASK_END; - - return status; -} - - /* * @brief Get the number of successful error recoveries */ diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelib.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelib.c index 23d5d869d..b04dd5a85 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelib.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelib.c @@ -211,7 +211,7 @@ knvlinkCoreAddDevice_IMPL dev->numIoctrls = nvPopCount32(pKernelNvlink->ioctrlMask); dev->numActiveLinksPerIoctrl = knvlinkGetNumActiveLinksPerIoctrl(pGpu, pKernelNvlink); dev->numLinksPerIoctrl = knvlinkGetTotalNumLinksPerIoctrl(pGpu, pKernelNvlink); - + // Register the GPU in nvlink core if (nvlink_lib_register_device(dev) != 0) { diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c index 7db9dc4c4..484445bb8 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c @@ -75,16 +75,13 @@ knvlinkCoreGetRemoteDeviceInfo_IMPL #if defined(INCLUDE_NVLINK_LIB) - OBJSYS *pSys = SYS_GET_INSTANCE(); - NvU32 flags = NVLINK_STATE_CHANGE_SYNC; - NvBool bNvswitchProxyPresent = NV_FALSE; - NvBool bUpdateConnStatus = NV_FALSE; - NvBool bCheckDegradedMode = NV_FALSE; - NvU32 linkId; - NvU32 tmpDisabledLinkMask = 0; - NvU32 tmpEnabledLinkMask = 0; + OBJSYS *pSys = SYS_GET_INSTANCE(); + NvU32 flags = NVLINK_STATE_CHANGE_SYNC; + NvBool bNvswitchProxyPresent = NV_FALSE; + NvBool bUpdateConnStatus = NV_FALSE; + NvBool bCheckDegradedMode = NV_FALSE; nvlink_conn_info conn_info; - + NvU32 linkId; NvU32 numActiveLinksPerIoctrl = 0; NvU32 numLinksPerIoctrl = 0; @@ -94,17 +91,6 @@ knvlinkCoreGetRemoteDeviceInfo_IMPL // if (!knvlinkPoweredUpForD3_HAL(pGpu, pKernelNvlink)) { - if (pKernelNvlink->bEnableAli) - { - // Update the post Rx Det link Mask for the GPU - knvlinkUpdatePostRxDetectLinkMask(pGpu, pKernelNvlink); - } - - if (pKernelNvlink->ipVerNvlink >= NVLINK_VERSION_40) - { - numActiveLinksPerIoctrl = knvlinkGetNumActiveLinksPerIoctrl(pGpu, pKernelNvlink); - numLinksPerIoctrl = knvlinkGetTotalNumLinksPerIoctrl(pGpu, pKernelNvlink); - } // // Optimization: Check for nvlink proxy only when system fabric is externally @@ -115,20 +101,16 @@ knvlinkCoreGetRemoteDeviceInfo_IMPL bNvswitchProxyPresent = knvlinkIsNvswitchProxyPresent(pGpu, pKernelNvlink); } - // - // If on Nvlink4.0+ then before topology discovery is performed then - // first enter the corelib floorsweeping function to floorsweep down - // the GPU if requested. - // This path does not cache connection info since its main purpose is to - // edit the connection information before RM tries to cache and update itself - // + if (pKernelNvlink->bEnableAli) + { + // Update the post Rx Det link Mask for the GPU + knvlinkUpdatePostRxDetectLinkMask(pGpu, pKernelNvlink); + } + if (pKernelNvlink->ipVerNvlink >= NVLINK_VERSION_40 && !bNvswitchProxyPresent && !pSys->getProperty(pSys, PDB_PROP_SYS_FABRIC_IS_EXTERNALLY_MANAGED) && - pKernelNvlink->pNvlinkDev != NULL && - !pKernelNvlink->bFloorSwept && - IS_SILICON(pGpu) && - numActiveLinksPerIoctrl < numLinksPerIoctrl) + pKernelNvlink->pNvlinkDev != NULL) { // The path here is important not getting the connection info FOR_EACH_INDEX_IN_MASK(32, linkId, pKernelNvlink->enabledLinks) @@ -138,93 +120,16 @@ knvlinkCoreGetRemoteDeviceInfo_IMPL } FOR_EACH_INDEX_IN_MASK_END; - // floorsweeping in corelib will update connection info that RM qill query below - (void)nvlink_lib_powerdown_floorswept_links_to_off(pKernelNvlink->pNvlinkDev); + numLinksPerIoctrl = knvlinkGetTotalNumLinksPerIoctrl(pGpu, pKernelNvlink); + status = knvlinkFloorSweep_IMPL(pGpu, pKernelNvlink, + numLinksPerIoctrl, &numActiveLinksPerIoctrl); - // - // If a link in the enabledLinkMask is not trained after floorsweeping then - // then add it to a tmp disabled linkMask - // - - // Get the link train status for the enabled link masks - NV2080_CTRL_NVLINK_ARE_LINKS_TRAINED_PARAMS linkTrainedParams; - - portMemSet(&linkTrainedParams, 0, sizeof(linkTrainedParams)); - linkTrainedParams.linkMask = pKernelNvlink->enabledLinks; - linkTrainedParams.bActiveOnly = NV_TRUE; - - // Reset timeout to clear any accumulated timeouts from link init - if (IS_GSP_CLIENT(pGpu)) - { - threadStateResetTimeout(pGpu); - } - - status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, - NV2080_CTRL_CMD_NVLINK_ARE_LINKS_TRAINED, - (void *)&linkTrainedParams, - sizeof(linkTrainedParams)); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "Failed to get the link train status for links\n"); - return status; - } - - // - // Create a temporary mask of all links that are now enabled: - // classified as a link in active - // - FOR_EACH_INDEX_IN_MASK(32, linkId, pKernelNvlink->enabledLinks) - { - if (linkTrainedParams.bIsLinkActive[linkId]) - { - tmpEnabledLinkMask |= BIT(linkId); + NV_PRINTF(LEVEL_ERROR, "Failed to floorsweep valid nvlink config!\n"); + return NV_ERR_NOT_READY; } - else - { - tmpDisabledLinkMask |= BIT(linkId); } - } - FOR_EACH_INDEX_IN_MASK_END; - - // Redo linkMasks based on the search above being the ground truth - pKernelNvlink->enabledLinks = tmpEnabledLinkMask; - - // - // remove any links not in active in the tmpEnabledLinkMask from all - // other link masks as these have been floorswept by the corelib - // - pKernelNvlink->disconnectedLinkMask = tmpEnabledLinkMask; - pKernelNvlink->initDisabledLinksMask = tmpDisabledLinkMask; - - - status = knvlinkProcessInitDisabledLinks(pGpu, pKernelNvlink); - if (status != NV_OK) - { - NV_ASSERT(status == NV_OK); - return status; - } - - // Re-sync the link masks with GSP - status = knvlinkSyncLinkMasksAndVbiosInfo(pGpu, pKernelNvlink); - if (status != NV_OK) - { - NV_ASSERT(status == NV_OK); - return status; - } - - - NV_PRINTF(LEVEL_INFO, - "Post Floorsweeping: discoveredLinks: 0x%x; enabledLinks:0x%x; disconnectedLinks:0x%x; initDisabledLinksMask:0x%x\n", - pKernelNvlink->discoveredLinks, pKernelNvlink->enabledLinks, pKernelNvlink->disconnectedLinkMask, pKernelNvlink->initDisabledLinksMask); - pKernelNvlink->bFloorSwept = NV_TRUE; - - // - // Assert that the number of links in active is always less then - // or equal to the number of active links on the chips - // - NV_ASSERT_OR_ELSE_STR((nvPopCount32(tmpEnabledLinkMask) <= numActiveLinksPerIoctrl * nvPopCount32(pKernelNvlink->ioctrlMask)), - "Mismatch between links in active and #of links supported!\n", return NV_ERR_INVALID_STATE); - } // We only need to look at links that are still considered disconnected FOR_EACH_INDEX_IN_MASK(32, linkId, pKernelNvlink->disconnectedLinkMask) @@ -247,8 +152,22 @@ knvlinkCoreGetRemoteDeviceInfo_IMPL // Call the core library to get the remote end information if (pSys->getProperty(pSys, PDB_PROP_SYS_FABRIC_IS_EXTERNALLY_MANAGED)) { - nvlink_lib_get_remote_conn_info( + if (gpuFabricProbeIsSupported(pGpu)) + { + // + // If FM doesn't talk to NVLink driver using control calls + // (i.e. uses NVLink inband comm instread) such as + // IOCTL CTRL_NVLINK_DISCOVER_INTRANODE_CONNS, + // discover remote information explicitly. + // + nvlink_lib_discover_and_get_remote_conn_info( + pKernelNvlink->nvlinkLinks[linkId].core_link, &conn_info, 0); + } + else + { + nvlink_lib_get_remote_conn_info( pKernelNvlink->nvlinkLinks[linkId].core_link, &conn_info); + } // // nvlink_lib_get_remote_conn_info could fail to return connection info if @@ -256,7 +175,9 @@ knvlinkCoreGetRemoteDeviceInfo_IMPL // can't see NVSwitches. In that case, examine the NVLink scratch register // for connectivity information. // - if (!conn_info.bConnected && bNvswitchProxyPresent) + if (!conn_info.bConnected && + (bNvswitchProxyPresent || + GPU_IS_NVSWITCH_DETECTED(pGpu))) { conn_info.bConnected = NV_TRUE; conn_info.deviceType = NVLINK_DEVICE_TYPE_NVSWITCH; @@ -540,10 +461,8 @@ knvlinkCheckTrainingIsComplete_IMPL // If the return code is non-zero, links are still training if (nvlink_lib_check_training_complete(pLinks, count) != 0) { - if (pKernelNvlink0->bLinkTrainingDebugSpew) - { - NV_PRINTF(LEVEL_INFO, "Links aren't fully trained yet!\n"); - } + NV_PRINTF(LEVEL_INFO, "Links aren't fully trained yet!\n"); + knvlinkLogAliDebugMessages(pGpu0, pKernelNvlink0); return NV_ERR_GENERIC; } @@ -597,11 +516,8 @@ knvlinkCheckTrainingIsComplete_IMPL // If the return code is non-zero, links are still training if (nvlink_lib_check_training_complete(pLinks, count) != 0) { - if (pKernelNvlink1->bLinkTrainingDebugSpew) - { - NV_PRINTF(LEVEL_INFO, "Links aren't fully trained yet!\n"); - } - + NV_PRINTF(LEVEL_INFO, "Links aren't fully trained yet!\n"); + knvlinkLogAliDebugMessages(pGpu1, pKernelNvlink1); return NV_ERR_GENERIC; } @@ -1383,6 +1299,131 @@ knvlinkRetrainLink_IMPL return status; } +/*! + * @brief Floorsweep the nvlink config for the chip + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelNvlink KernelNvlink pointer + * @param[in] numLinksPerIp number of total links found in discovery + * @param[out] pNumLinkActive number of links needed to be active + * + * @returns On success, sets unique fabric address and returns NV_OK. + * On failure, returns NV_ERR_XXX. + */ +NV_STATUS +knvlinkFloorSweep_IMPL +( + OBJGPU *pGpu, + KernelNvlink *pKernelNvlink, + NvU32 numLinksPerIoctrl, + NvU32 *pNumActiveLinksPerIoctrl +) +{ + +#if defined(INCLUDE_NVLINK_LIB) + NV_STATUS status = NV_OK; + NvU32 linkId; + NvU32 tmpDisabledLinkMask = 0; + NvU32 tmpEnabledLinkMask = 0; + + *pNumActiveLinksPerIoctrl = knvlinkGetNumActiveLinksPerIoctrl(pGpu, pKernelNvlink); + if (!knvlinkIsFloorSweepingNeeded_HAL(pGpu, pKernelNvlink, *pNumActiveLinksPerIoctrl, numLinksPerIoctrl)) + { + return NV_OK; + } + + // floorsweeping in corelib will update connection info that RM qill query below + (void)nvlink_lib_powerdown_floorswept_links_to_off(pKernelNvlink->pNvlinkDev); + + // + // If a link in the enabledLinkMask is not trained after floorsweeping then + // then add it to a tmp disabled linkMask + // + + // Get the link train status for the enabled link masks + NV2080_CTRL_NVLINK_ARE_LINKS_TRAINED_PARAMS linkTrainedParams; + + portMemSet(&linkTrainedParams, 0, sizeof(linkTrainedParams)); + linkTrainedParams.linkMask = pKernelNvlink->enabledLinks; + linkTrainedParams.bActiveOnly = NV_TRUE; + + // Reset timeout to clear any accumulated timeouts from link init + if (IS_GSP_CLIENT(pGpu)) + { + threadStateResetTimeout(pGpu); + } + + status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, + NV2080_CTRL_CMD_NVLINK_ARE_LINKS_TRAINED, + (void *)&linkTrainedParams, + sizeof(linkTrainedParams)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to get the link train status for links\n"); + return status; + } + + // + // Create a temporary mask of all links that are now enabled: + // classified as a link in active + // + FOR_EACH_INDEX_IN_MASK(32, linkId, pKernelNvlink->enabledLinks) + { + if (linkTrainedParams.bIsLinkActive[linkId]) + { + tmpEnabledLinkMask |= BIT(linkId); + } + else + { + tmpDisabledLinkMask |= BIT(linkId); + } + } + FOR_EACH_INDEX_IN_MASK_END; + + // Redo linkMasks based on the search above being the ground truth + pKernelNvlink->enabledLinks = tmpEnabledLinkMask; + + // + // remove any links not in active in the tmpEnabledLinkMask from all + // other link masks as these have been floorswept by the corelib + // + pKernelNvlink->disconnectedLinkMask = tmpEnabledLinkMask; + pKernelNvlink->initDisabledLinksMask = tmpDisabledLinkMask; + + + status = knvlinkProcessInitDisabledLinks(pGpu, pKernelNvlink); + if (status != NV_OK) + { + NV_ASSERT(status == NV_OK); + return status; + } + + // Re-sync the link masks with GSP + status = knvlinkSyncLinkMasksAndVbiosInfo(pGpu, pKernelNvlink); + if (status != NV_OK) + { + NV_ASSERT(status == NV_OK); + return status; + } + + // + // Assert that the number of links in active is always less then + // or equal to the number of active links on the chips + // + if(!(nvPopCount32(tmpEnabledLinkMask) <= *pNumActiveLinksPerIoctrl * nvPopCount32(pKernelNvlink->ioctrlMask))) + { + NV_PRINTF(LEVEL_INFO, + "Floorsweeping didn't work! enabledMaskCount: 0x%x and numActiveLinksTotal: 0x%x. Current link info cached in SW: discoveredLinks: 0x%x; enabledLinks:0x%x; disconnectedLinks:0x%x; initDisabledLinksMask:0x%x\n", + nvPopCount32(tmpEnabledLinkMask), *pNumActiveLinksPerIoctrl * nvPopCount32(pKernelNvlink->ioctrlMask), pKernelNvlink->discoveredLinks, pKernelNvlink->enabledLinks, pKernelNvlink->disconnectedLinkMask, pKernelNvlink->initDisabledLinksMask); + + return NV_ERR_NOT_READY; + } + + pKernelNvlink->bFloorSwept = NV_TRUE; +#endif //INCLUDE_NVLINK_LIB + return NV_OK; +} + /*! * @brief Retrain the link from OFF state * diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkstate.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkstate.c index 7ac0cf748..e43ed049e 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkstate.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkstate.c @@ -193,6 +193,12 @@ knvlinkConstructEngine_IMPL return status; } + // + // When GSP inform about link error occurs on this GPU + // it will updated to NV_TRUE + // + pKernelNvlink->bIsGpuDegraded = NV_FALSE; + // // Create MAX KernelIoctrl objects. // Later in knvlinkStatePreInit_IMPL, we will remove the objects for @@ -545,6 +551,10 @@ knvlinkStateLoad_IMPL sysEnableExternalFabricMgmt(pSys); sysForceInitFabricManagerState(pSys); } + if (GPU_IS_NVSWITCH_DETECTED(pGpu)) + { + sysEnableExternalFabricMgmt(pSys); + } // // WAR Bug# 3261027: Sync-up External Fabric Management status with GSP-RM. @@ -562,6 +572,7 @@ knvlinkStateLoad_IMPL // If we are running on CPU-RM or monolithic, process SYSMEM links, if present // on the system. // + status = _knvlinkProcessSysmemLinks(pGpu, pKernelNvlink, (preInitializedLinks != pKernelNvlink->initializedLinks)); if (status != NV_OK) @@ -578,7 +589,7 @@ knvlinkStateLoad_IMPL // if (!(flags & GPU_STATE_FLAGS_PRESERVING)) { - if ((status = kbusInitFla_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu), 0, 0)) != NV_OK) + if ((status = kbusCheckFlaSupportedAndInit_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu), 0, 0)) != NV_OK) { NV_PRINTF(LEVEL_ERROR, "Init FLA failed, status:0x%x\n", status); NV_ASSERT(status == NV_OK); @@ -852,7 +863,8 @@ knvlinkStatePostUnload_IMPL // platforms (in discussion with ARCH for non-NVSwitch platforms). // if (pSys->getProperty(pSys, PDB_PROP_SYS_NVSWITCH_IS_PRESENT) || - knvlinkIsNvswitchProxyPresent(pGpu, pKernelNvlink)) + knvlinkIsNvswitchProxyPresent(pGpu, pKernelNvlink) || + (GPU_IS_NVSWITCH_DETECTED(pGpu))) { knvlinkRemoveMapping_HAL(pGpu, pKernelNvlink, NV_FALSE, ((1 << NVLINK_MAX_PEERS_SW) - 1), @@ -903,6 +915,7 @@ knvlinkStatePostUnload_IMPL if (!API_GPU_IN_RESET_SANITY_CHECK(pRemoteGpu)) { KernelNvlink *pRemoteKernelNvlink = GPU_GET_KERNEL_NVLINK(pRemoteGpu); + pRemoteKernelNvlink->disconnectedLinkMask |= NVBIT(pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.linkNumber); } } @@ -1000,15 +1013,94 @@ _knvlinkPurgeState_end: } // Destroy the chiplib configuration memory - if (pKernelNvlink->pLinkConnection) - { - portMemFree(pKernelNvlink->pLinkConnection); - pKernelNvlink->pLinkConnection = NULL; - } + portMemFree(pKernelNvlink->pLinkConnection); + pKernelNvlink->pLinkConnection = NULL; return NV_OK; } +/*! + * @brief Degraded Mode will be set if other end of the linkId + * is not degraded. + * Once degraded destroy the RM NVLink SW state + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelNvlink KernelNvlink pointer + * @param[in] linkId linkId of the error link + * + */ +void +knvlinkSetDegradedMode_IMPL +( + OBJGPU *pGpu, + KernelNvlink *pKernelNvlink, + NvU32 linkId +) +{ + NvU32 status = NV_ERR_GENERIC; + NvU32 gpuInstance; + OBJGPU *pRemoteGpu = NULL; + KernelNvlink *pRemoteKernelNvlink = NULL; + + if (!pKernelNvlink) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to get Local Nvlink info for linkId %d to update Degraded GPU%d status\n", + linkId, pGpu->gpuInstance); + + return; + } + + if(pKernelNvlink->bIsGpuDegraded) + { + return; + } + + //Find the remote GPU/NVLink attached to this link, if any + for (gpuInstance = 0; gpuInstance < NV_MAX_DEVICES; gpuInstance++) + { + if (pKernelNvlink->peerLinkMasks[gpuInstance] & NVBIT(linkId)) + { + pRemoteGpu = gpumgrGetGpu(gpuInstance); + break; + } + } + + if (pRemoteGpu == NULL) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to get Remote GPU info for linkId %d to update Degraded GPU%d status\n", + linkId, pGpu->gpuInstance); + + return; + } + + pRemoteKernelNvlink = GPU_GET_KERNEL_NVLINK(pRemoteGpu); + if (!pRemoteKernelNvlink) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to get Remote Nvlink info for linkId %d to update Degraded GPU%d status\n", + linkId, pGpu->gpuInstance); + + return; + } + + if (pRemoteKernelNvlink->bIsGpuDegraded == NV_FALSE) + { + pKernelNvlink->bIsGpuDegraded = NV_TRUE; + + // shutdown all the links on this GPU + status = knvlinkCoreShutdownDeviceLinks(pGpu, pKernelNvlink, NV_TRUE); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "failed to shutdown links on degraded GPU%d\n", pGpu->gpuInstance); + } + } + + return; +} + void knvlinkDestruct_IMPL ( diff --git a/src/nvidia/src/kernel/gpu/perf/kern_perf.c b/src/nvidia/src/kernel/gpu/perf/kern_perf.c index 48922838c..387ddf29d 100644 --- a/src/nvidia/src/kernel/gpu/perf/kern_perf.c +++ b/src/nvidia/src/kernel/gpu/perf/kern_perf.c @@ -30,9 +30,10 @@ /* ------------------------ Includes --------------------------------------- */ #include "gpu/perf/kern_perf.h" -#include "gpu/perf/kern_perf_1hz.h" #include "gpu/perf/kern_perf_boost.h" #include "objtmr.h" +#include "platform/platform_request_handler.h" +#include "platform/chipset/chipset.h" /* ------------------------ Global Variables ------------------------------- */ /* ------------------------ Static Function Prototypes --------------------- */ @@ -53,11 +54,19 @@ kperfConstructEngine_IMPL(OBJGPU *pGpu, KernelPerf *pKernelPerf, ENGDESCRIPTOR e NV_STATUS kperfStateInitLocked_IMPL(OBJGPU *pGpu, KernelPerf *pKernelPerf) { + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); NV_STATUS status = NV_OK; // Initialize SW state corresponding to SLI GPU Boost synchronization. status = kperfGpuBoostSyncStateInit(pGpu, pKernelPerf); + // Initialize PFM_REQ_HNDLR module which is a child of OBJSYS + if (RMCFG_MODULE_PLATFORM_REQUEST_HANDLER && pPlatformRequestHandler != NULL) + { + pfmreqhndlrStateInit(pPlatformRequestHandler); + } + return status; } @@ -67,15 +76,20 @@ kperfStateInitLocked_IMPL(OBJGPU *pGpu, KernelPerf *pKernelPerf) NV_STATUS kperfStateLoad_IMPL(OBJGPU *pGpu, KernelPerf *pKernelPerf, NvU32 flags) { - OBJTMR *pTmr = GPU_GET_TIMER(pGpu); - - pKernelPerf->timer1HzCallback.bEnableTimerUpdates = NV_TRUE; - - tmrScheduleCallbackRelSec(pTmr, kperfTimerProc, TMR_POBJECT_KERNEL_PERF_1HZ, 1, TMR_FLAG_RECUR, 0); + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJCL *pCl = SYS_GET_CL(pSys); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); // Initialize SW state corresponding to SLI GPU Boost synchronization. kperfGpuBoostSyncStateInit(pGpu, pKernelPerf); + // Load PFM_REQ_HNDLR module which is a child of OBJSYS + // Skip pfmreqhndlrStateLoad on eGPU + if (!(pCl->getProperty(pCl, PDB_PROP_CL_IS_EXTERNAL_GPU)) && RMCFG_MODULE_PLATFORM_REQUEST_HANDLER && (pPlatformRequestHandler != NULL)) + { + pfmreqhndlrStateLoad(pPlatformRequestHandler); + } + return NV_OK; } @@ -90,15 +104,38 @@ kperfStateUnload_IMPL NvU32 flags ) { - OBJTMR *pTmr = GPU_GET_TIMER(pGpu); + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); - pKernelPerf->timer1HzCallback.bEnableTimerUpdates = NV_FALSE; - - tmrCancelCallback(pTmr, TMR_POBJECT_KERNEL_PERF_1HZ); + if (RMCFG_MODULE_PLATFORM_REQUEST_HANDLER && (pPlatformRequestHandler != NULL)) + { + // Unload PFM_REQ_HNDLR module which is a child of OBJSYS + pfmreqhndlrStateUnload(pPlatformRequestHandler); + } return NV_OK; } +/*! + * @copydoc kperfStateDestroy +*/ +void +kperfStateDestroy_IMPL +( + OBJGPU *pGpu, + KernelPerf *pKernelPerf +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + PlatformRequestHandler *pPlatformRequestHandler = SYS_GET_PFM_REQ_HNDLR(pSys); + + // destroy PFM_REQ_HNDLR module state + if (RMCFG_MODULE_PLATFORM_REQUEST_HANDLER && (pPlatformRequestHandler != NULL)) + { + pfmreqhndlrStateDestroy(pPlatformRequestHandler); + } +} + /*! * @copydoc kperfReentrancy * diff --git a/src/nvidia/src/kernel/gpu/perf/kern_perf_1hz.c b/src/nvidia/src/kernel/gpu/perf/kern_perf_1hz.c deleted file mode 100644 index 9e7788d1c..000000000 --- a/src/nvidia/src/kernel/gpu/perf/kern_perf_1hz.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -/* ------------------------ Includes --------------------------------------- */ -#include "gpu/perf/kern_perf.h" -#include "gpu/perf/kern_perf_1hz.h" -#include "objtmr.h" - -/* ------------------------ Global Variables ------------------------------- */ -/* ------------------------ Static Function Prototypes --------------------- */ -/* ------------------------ Macros ----------------------------------------- */ -/* ------------------------ Public Functions ------------------------------- */ -/*! - * @copydoc kperfTimerProc - */ -NV_STATUS -kperfTimerProc(OBJGPU *pGpu, OBJTMR *pTmr, void *ptr) -{ - KernelPerf *pKernelPerf = GPU_GET_KERNEL_PERF(pGpu); - - // Request next callback. call with Flags = TMR_FLAG_RECUR, since self-rescheduling - if (ptr == TMR_POBJECT_KERNEL_PERF_1HZ) - { - pKernelPerf->timer1HzCallback.b1HzTimerCallback = NV_TRUE; - tmrScheduleCallbackRelSec(pTmr, kperfTimerProc, TMR_POBJECT_KERNEL_PERF_1HZ, 1, TMR_FLAG_RECUR, 0); - } - - kperfTimer1HzCallback(pGpu, pKernelPerf); - - return NV_OK; -} - -/*! - * @copydoc kperfTimer1HzCallback - */ -void -kperfTimer1HzCallback_IMPL(OBJGPU *pGpu, KernelPerf *pKernelPerf) -{ - NvBool bBcState = gpumgrGetBcEnabledStatus(pGpu); - gpumgrSetBcEnabledStatus(pGpu, NV_FALSE); - - // - // If GPU is in full power, timer updates are enabled and we are not breaking the - // reentrancy rules. - // - if ((gpuIsGpuFullPower(pGpu)) && - (pKernelPerf->timer1HzCallback.bEnableTimerUpdates) && - (kperfReentrancy(pGpu, pKernelPerf, KERNEL_PERF_REENTRANCY_TIMER_1HZ_CALLBACK, NV_TRUE) == NV_OK)) - { - // If this function is called as a result of a 1HZ callback, do the Boost Hint callback - if (pKernelPerf->timer1HzCallback.b1HzTimerCallback) - { - pKernelPerf->timer1HzCallback.b1HzTimerCallback = NV_FALSE; - } - - // Release the reentrancy flag for this specific routine - kperfReentrancy(pGpu, pKernelPerf, KERNEL_PERF_REENTRANCY_TIMER_1HZ_CALLBACK, NV_FALSE); - } - - gpumgrSetBcEnabledStatus(pGpu, bBcState); - -} - -/* ------------------------- Private Functions ------------------------------ */ diff --git a/src/nvidia/src/kernel/gpu/perf/kern_perf_boost.c b/src/nvidia/src/kernel/gpu/perf/kern_perf_boost.c index 38aae2449..d840c4c0b 100644 --- a/src/nvidia/src/kernel/gpu/perf/kern_perf_boost.c +++ b/src/nvidia/src/kernel/gpu/perf/kern_perf_boost.c @@ -66,24 +66,19 @@ kperfBoostSet_3x ) { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); NV_STATUS status = NV_OK; NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_2X boostParams2x = {0}; boostParams2x.flags = pBoostParams->flags; boostParams2x.duration = pBoostParams->duration; - // - // This should always be GSP CLIENT. - // - NV_ASSERT(IS_GSP_CLIENT(pGpu)); - - NV_RM_RPC_CONTROL(pGpu, - RES_GET_CLIENT_HANDLE(pSubdevice), - RES_GET_HANDLE(pSubdevice), - NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_2X, - &boostParams2x, - sizeof(boostParams2x), - status); + status = pRmApi->Control(pRmApi, + RES_GET_CLIENT_HANDLE(pSubdevice), + RES_GET_HANDLE(pSubdevice), + NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_2X, + &boostParams2x, + sizeof(boostParams2x)); return status; } diff --git a/src/nvidia/src/kernel/gpu/perf/kern_perf_gpuboostsync.c b/src/nvidia/src/kernel/gpu/perf/kern_perf_gpuboostsync.c index d3d69315b..93dec2a6f 100644 --- a/src/nvidia/src/kernel/gpu/perf/kern_perf_gpuboostsync.c +++ b/src/nvidia/src/kernel/gpu/perf/kern_perf_gpuboostsync.c @@ -148,6 +148,8 @@ kperfDoSyncGpuBoostLimits_IMPL return status; } + NV_CHECK_OR_RETURN(LEVEL_ERROR, (pKernelPerf != NULL), NV_ERR_INVALID_POINTER); + for (i = 0; i < NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_NUM; i++) { pKernelPerf->sliGpuBoostSync.limits[i] = pParams->currLimits[i]; diff --git a/src/nvidia/src/kernel/gpu/perf/kern_perf_pwr.c b/src/nvidia/src/kernel/gpu/perf/kern_perf_pwr.c index 24f0b81f2..7a9cb511d 100644 --- a/src/nvidia/src/kernel/gpu/perf/kern_perf_pwr.c +++ b/src/nvidia/src/kernel/gpu/perf/kern_perf_pwr.c @@ -94,4 +94,153 @@ subdeviceCtrlCmdPerfRatedTdpSetControl_KERNEL return status; } +/*! + * @brief Send ACPI callback function to notify SBIOS of our power state change + * + * @param pGpu OBJGPU pointer + * @param pKernelPerf KernelPerf pointer + * + * @return No return value from this function. + */ +static void +_kperfSendPostPowerStateCallback +( + OBJGPU *pGpu, + KernelPerf *pKernelPerf +) +{ + NvU32 inOutData = 0; + NvU16 outDataSize = sizeof(inOutData); + OBJOS *pOS = GPU_GET_OS(pGpu); + NV_STATUS status = NV_OK; + ACPI_DSM_FUNCTION func = gpuGetPerfPostPowerStateFunc(pGpu); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS ctrlParams = { 0 }; + + // Bail out early if ACPI callback is not supported. + if (func == ACPI_DSM_FUNCTION_COUNT) + { + return; + } + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_PERF_GET_AUX_POWER_STATE, + &ctrlParams, + sizeof(ctrlParams)); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Error getting Aux Power State:0x%x\n", status); + } + + // Setup the argument to send + inOutData = FLD_SET_DRF(_ACPI, _CALLBACKS_ARG, _POSTPOWERSTATE, _NOTIFY, + inOutData); + inOutData = FLD_SET_DRF_NUM(_ACPI, _CALLBACKS_ARG, _CURRENTPOWERSTATE, + ctrlParams.powerState, inOutData); + + status = pOS->osCallACPI_DSM(pGpu, func, + NV_ACPI_GENERIC_FUNC_CALLBACKS, + &inOutData, &outDataSize); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "PostPState callback error:0x%x\n", status); + } +} + +NV_STATUS +subdeviceCtrlCmdPerfSetAuxPowerState_KERNEL +( + Subdevice *pSubdevice, + NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS *pPowerStateParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + KernelPerf *pKernelPerf = GPU_GET_KERNEL_PERF(pGpu); + NV_STATUS status; + + NV_CHECK_OR_RETURN(LEVEL_INFO, (pKernelPerf != NULL), NV_ERR_NOT_SUPPORTED); + + NV_ASSERT_OR_RETURN(pPowerStateParams->powerState < NV2080_CTRL_PERF_AUX_POWER_STATE_COUNT, + NV_ERR_INVALID_ARGUMENT); + + // Redirect to Physical RM. + status = pRmApi->Control(pRmApi, + RES_GET_CLIENT_HANDLE(pSubdevice), + RES_GET_HANDLE(pSubdevice), + NV2080_CTRL_CMD_PERF_SET_AUX_POWER_STATE, + pPowerStateParams, + sizeof(*pPowerStateParams)); + + if (status != NV_OK) + { + NV_ASSERT(0); + } + + _kperfSendPostPowerStateCallback(pGpu, pKernelPerf); + + return status; +} + +NV_STATUS +subdeviceCtrlCmdPerfSetPowerstate_KERNEL +( + Subdevice *pSubdevice, + NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS *pPowerInfoParams +) +{ + POBJGPU pGpu = GPU_RES_GET_GPU(pSubdevice); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + KernelPerf *pKernelPerf = GPU_GET_KERNEL_PERF(pGpu); + NV_STATUS status = NV_OK; + NvBool bSwitchToAC = (pPowerInfoParams->powerStateInfo.powerState == + NV2080_CTRL_PERF_POWER_SOURCE_AC); + + NV_CHECK_OR_RETURN(LEVEL_INFO, (pKernelPerf != NULL), NV_ERR_NOT_SUPPORTED); + + if ((pPowerInfoParams->powerStateInfo.powerState != NV2080_CTRL_PERF_POWER_SOURCE_AC) && + (pPowerInfoParams->powerStateInfo.powerState != NV2080_CTRL_PERF_POWER_SOURCE_BATTERY)) + { + status = NV_ERR_INVALID_ARGUMENT; + } + else if(!gpuIsGpuFullPower(pGpu)) + { + NV_PRINTF(LEVEL_ERROR, + "NV2080_CTRL_CMD_PERF_SET_POWERSTATE called in power down state.\n"); + NV_PRINTF(LEVEL_ERROR, " Returning NV_ERR_GPU_NOT_FULL_POWER.\n"); + status = NV_ERR_GPU_NOT_FULL_POWER; + } + + if (status != NV_OK) + return status; + + // Redirect to Physical RM. + status = pRmApi->Control(pRmApi, + RES_GET_CLIENT_HANDLE(pSubdevice), + RES_GET_HANDLE(pSubdevice), + NV2080_CTRL_CMD_PERF_SET_POWERSTATE, + pPowerInfoParams, + sizeof(*pPowerInfoParams)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "NV2080_CTRL_CMD_PERF_SET_POWERSTATE RPC failed\n"); + } + + // If callback was registered, update platform with the current Auxpower state(Dx) + _kperfSendPostPowerStateCallback(pGpu, pKernelPerf); + + Nv2080PowerEventNotification powerEventNotificationParams = {0}; + + // Notify clients about AC/DC switch + powerEventNotificationParams.bSwitchToAC = bSwitchToAC; + powerEventNotificationParams.bGPUCapabilityChanged = 0; + powerEventNotificationParams.displayMaskAffected = 0; + gpuNotifySubDeviceEvent(pGpu, NV2080_NOTIFIERS_POWER_EVENT, + &powerEventNotificationParams, sizeof(powerEventNotificationParams), 0, 0); + + return status; +} /* ------------------------- Private Functions ------------------------------ */ diff --git a/src/nvidia/src/kernel/gpu/pmu/arch/ada/kern_pmu_ad102.c b/src/nvidia/src/kernel/gpu/pmu/arch/ada/kern_pmu_ad102.c new file mode 100644 index 000000000..b7755d6b3 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/pmu/arch/ada/kern_pmu_ad102.c @@ -0,0 +1,88 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "os/os.h" +#include "gpu/pmu/kern_pmu.h" + +#include "published/ada/ad102/dev_bus.h" +#include "published/ada/ad102/dev_bus_addendum.h" + +static NvBool _kpmuPreOsCheckErotGrantAllowed_AD102(OBJGPU *pGpu, void *pVoid); + +/*! + * Signals preOs to have eRoT hand over control of EEPROM to RM + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelPmu KernelPmu pointer + * + * @returns NV_OK if RM has control of the EEPROM + * @returns NV_ERR_TIMEOUT if preOs fails to hand over control of the EEPROM + * + */ +NV_STATUS +kpmuPreOsGlobalErotGrantRequest_AD102 +( + OBJGPU *pGpu, + KernelPmu *pKernelPmu +) +{ + NV_STATUS status = NV_OK; + RMTIMEOUT timeout; + NvU32 reg = GPU_REG_RD32(pGpu, NV_PBUS_SW_GLOBAL_EROT_GRANT); + + // Invalid value suggests that there is no ERoT + if (FLD_TEST_DRF(_PBUS, _SW_GLOBAL_EROT_GRANT, _VALID, _NO, reg)) + { + return status; + } + + // Check if grant has already been allowed + if (_kpmuPreOsCheckErotGrantAllowed_AD102(pGpu, NULL)) + { + return status; + } + + reg = FLD_SET_DRF(_PBUS, _SW_GLOBAL_EROT_GRANT, _REQUEST, _SET, reg); + GPU_REG_WR32(pGpu, NV_PBUS_SW_GLOBAL_EROT_GRANT, reg); + + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + status = gpuTimeoutCondWait(pGpu, _kpmuPreOsCheckErotGrantAllowed_AD102, NULL, &timeout); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Timed out waiting for preOs to grant access to EEPROM\n"); + } + + return status; +} + +static NvBool +_kpmuPreOsCheckErotGrantAllowed_AD102 +( + OBJGPU *pGpu, + void *pVoid +) +{ + NvU32 reg = GPU_REG_RD32(pGpu, NV_PBUS_SW_GLOBAL_EROT_GRANT); + + return FLD_TEST_DRF(_PBUS, _SW_GLOBAL_EROT_GRANT, _ALLOW, _YES, reg); +} diff --git a/src/nvidia/src/kernel/gpu/pmu/kern_pmu.c b/src/nvidia/src/kernel/gpu/pmu/kern_pmu.c index aa6011c7f..8f7ee0d03 100644 --- a/src/nvidia/src/kernel/gpu/pmu/kern_pmu.c +++ b/src/nvidia/src/kernel/gpu/pmu/kern_pmu.c @@ -58,7 +58,9 @@ kpmuInitLibosLoggingStructures_IMPL NV_STATUS nvStatus = NV_OK; if (!IS_GSP_CLIENT(pGpu)) + { return NV_OK; + } NV_ASSERT_OR_RETURN(pKernelPmu->pPrintBuf == NULL, NV_ERR_INVALID_STATE); @@ -74,10 +76,10 @@ kpmuInitLibosLoggingStructures_IMPL // Add PMU log buffer (use a fake "task name" - NVRISCV) libosLogAddLogEx(&pKernelPmu->logDecode, pKernelPmu->pPrintBuf, pKernelPmu->printBufSize, pGpu->gpuInstance, (gpuGetChipArch(pGpu) >> GPU_ARCH_SHIFT), gpuGetChipImpl(pGpu), - "NVRISCV"); + "NVRISCV", NULL); // Finish PMU log init (setting the lossless-print flag and resolve-pointers flag) - libosLogInitEx(&pKernelPmu->logDecode, pKernelPmu->pLogElf, NV_TRUE, NV_TRUE); + libosLogInitEx(&pKernelPmu->logDecode, pKernelPmu->pLogElf, NV_TRUE, NV_TRUE, pKernelPmu->logElfSize); if (nvStatus != NV_OK) kpmuFreeLibosLoggingStructures(pGpu, pKernelPmu); @@ -95,7 +97,9 @@ kpmuFreeLibosLoggingStructures_IMPL ) { if (!IS_GSP_CLIENT(pGpu)) + { return; + } // Destroy PMU log libosLogDestroy(&pKernelPmu->logDecode); @@ -123,3 +127,13 @@ kpmuLogBuf_IMPL pBuf, bufSize); libosExtractLogs(&pKernelPmu->logDecode, NV_FALSE); } + +NV_STATUS kpmuStateInitLocked_IMPL +( + OBJGPU *pGpu, + KernelPmu *pKernelPmu +) +{ + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/rc/kernel_rc.c b/src/nvidia/src/kernel/gpu/rc/kernel_rc.c index 0aafba2c9..59c60310a 100644 --- a/src/nvidia/src/kernel/gpu/rc/kernel_rc.c +++ b/src/nvidia/src/kernel/gpu/rc/kernel_rc.c @@ -282,6 +282,7 @@ krcReportXid_IMPL NvU16 gpuPartitionId; NvU16 computeInstanceId; KernelChannel *pKernelChannel = krcGetChannelInError(pKernelRc); + char *current_procname = NULL; // Channels are populated with osGetCurrentProcessName() and pid of // their process at creation-time. If no channel was found, mark unknown @@ -289,8 +290,8 @@ krcReportXid_IMPL char pid_string[12] = "''"; // - // Get PID of channel creator if available, otherwise default to - // whatever the kernel can tell us at the moment (likely pid 0) + // Get PID of channel creator if available, or get the current PID for + // exception types that never have an associated channel // if (pKernelChannel != NULL) { @@ -299,6 +300,19 @@ krcReportXid_IMPL procname = pRmClient->name; nvDbgSnprintf(pid_string, sizeof(pid_string), "%u", pKernelChannel->ProcessID); } + else if (exceptType == GSP_RPC_TIMEOUT) + { + NvU32 current_pid = osGetCurrentProcess(); + + nvDbgSnprintf(pid_string, sizeof(pid_string), "%u", current_pid); + + current_procname = portMemAllocNonPaged(NV_PROC_NAME_MAX_LENGTH); + if (current_procname != NULL) + { + osGetCurrentProcessName(current_procname, NV_PROC_NAME_MAX_LENGTH); + procname = current_procname; + } + } _krcLogUuidOnce(pGpu, pKernelRc); @@ -342,6 +356,8 @@ krcReportXid_IMPL procname, pMsg != NULL ? pMsg : ""); } + + portMemFree(current_procname); } } diff --git a/src/nvidia/src/kernel/gpu/rc/kernel_rc_callback.c b/src/nvidia/src/kernel/gpu/rc/kernel_rc_callback.c index 5826691b3..99824d1fd 100644 --- a/src/nvidia/src/kernel/gpu/rc/kernel_rc_callback.c +++ b/src/nvidia/src/kernel/gpu/rc/kernel_rc_callback.c @@ -55,7 +55,7 @@ _vgpuRcResetCallback if (osCondAcquireRmSema(pSys->pSema) == NV_OK) { - if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_COND_ACQUIRE, + if (rmGpuLocksAcquire(GPU_LOCK_FLAGS_COND_ACQUIRE, RM_LOCK_MODULES_RC) == NV_OK) { THREAD_STATE_NODE threadState; @@ -167,16 +167,17 @@ krcResetCallback status = NV_ERR_INVALID_STATE; goto error_cleanup); - if (IS_GSP_CLIENT(pRcErrorContext->pGpu)) { NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS params = {0}; - NV_RM_RPC_CONTROL(pRcErrorContext->pGpu, - RES_GET_CLIENT_HANDLE(pKernelChannel), - RES_GET_HANDLE(pKernelChannel), - NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL, - ¶ms, - sizeof params, - status); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pRcErrorContext->pGpu); + + // Client lock is already obtained above. + status = pRmApi->Control(pRmApi, + RES_GET_CLIENT_HANDLE(pKernelChannel), + RES_GET_HANDLE(pKernelChannel), + NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL, + ¶ms, + sizeof params); } threadStateFreeISRAndDeferredIntHandler( @@ -223,7 +224,7 @@ krcErrorInvokeCallback_IMPL FIFO_MMU_EXCEPTION_DATA *pMmuExceptionData, NvU32 exceptType, NvU32 exceptLevel, - NvU32 engineId, + RM_ENGINE_TYPE rmEngineType, NvU32 rcDiagRecStart ) { @@ -234,7 +235,7 @@ krcErrorInvokeCallback_IMPL RmClient *pClient = NULL; RsClient *pRsClient; RC_CALLBACK_STATUS clientAction; - NvU32 localEngineId = engineId; + RM_ENGINE_TYPE localRmEngineType = rmEngineType; NvU32 rcDiagRecOwner = RCDB_RCDIAG_DEFAULT_OWNER; NV_STATUS status; NvBool bReturn = NV_TRUE; @@ -256,8 +257,8 @@ krcErrorInvokeCallback_IMPL // If SMC is enabled, RM need to notify partition local engineIds. // Convert global ID to partition local // - if (IS_MIG_IN_USE(pGpu) && NV2080_ENGINE_TYPE_IS_VALID(engineId) && - kmigmgrIsEnginePartitionable(pGpu, pKernelMigManager, engineId)) + if (IS_MIG_IN_USE(pGpu) && RM_ENGINE_TYPE_IS_VALID(rmEngineType) && + kmigmgrIsEnginePartitionable(pGpu, pKernelMigManager, rmEngineType)) { MIG_INSTANCE_REF ref; status = kmigmgrGetInstanceRefFromClient(pGpu, @@ -267,13 +268,11 @@ krcErrorInvokeCallback_IMPL if (status != NV_OK) return bReturn; - if (!kmigmgrIsEngineInInstance(pGpu, pKernelMigManager, engineId, ref)) + if (!kmigmgrIsEngineInInstance(pGpu, pKernelMigManager, rmEngineType, ref)) { // Notifier is requested for an unsupported engine - NV_PRINTF( - LEVEL_ERROR, - "RcErroCallback requested for an unsupported engine (0x%x)\n", - localEngineId); + NV_PRINTF(LEVEL_ERROR, "RcErroCallback requested for an unsupported engine 0x%x (0x%x)\n", + gpuGetNv2080EngineType(rmEngineType), rmEngineType); return bReturn; } @@ -281,8 +280,8 @@ krcErrorInvokeCallback_IMPL status = kmigmgrGetGlobalToLocalEngineType(pGpu, pKernelMigManager, ref, - engineId, - &localEngineId); + rmEngineType, + &localRmEngineType); if (status != NV_OK) return bReturn; } @@ -319,7 +318,7 @@ krcErrorInvokeCallback_IMPL pRcErrorContext->secChId = 0xFFFFFFFF; pRcErrorContext->sechClient = RES_GET_CLIENT_HANDLE(pKernelChannel); pRcErrorContext->exceptType = exceptType; - pRcErrorContext->EngineId = localEngineId; + pRcErrorContext->EngineId = gpuGetNv2080EngineType(localRmEngineType); pRcErrorContext->subdeviceInstance = pGpu->subdeviceInstance; if (pMmuExceptionData != NULL) diff --git a/src/nvidia/src/kernel/gpu/rc/kernel_rc_notification.c b/src/nvidia/src/kernel/gpu/rc/kernel_rc_notification.c index a541f6784..c58f3d997 100644 --- a/src/nvidia/src/kernel/gpu/rc/kernel_rc_notification.c +++ b/src/nvidia/src/kernel/gpu/rc/kernel_rc_notification.c @@ -46,7 +46,7 @@ _krcErrorWriteNotifierCpuMemHelper Memory *pMemory, NvHandle hClient, NvU32 exceptType, - NvU32 localEngineType, + RM_ENGINE_TYPE localRmEngineType, NV_STATUS notifierStatus ) { @@ -60,7 +60,7 @@ _krcErrorWriteNotifierCpuMemHelper RES_GET_HANDLE(pMemory), memdescGetPhysAddr(pMemory->pMemDesc, AT_GPU_VA, 0), exceptType, - (NvU16)localEngineType, + (NvU16)gpuGetNv2080EngineType(localRmEngineType), notifierStatus, 0 /* Index */); break; @@ -70,7 +70,7 @@ _krcErrorWriteNotifierCpuMemHelper notifyFillNotifierMemory(pGpu, pMemory, exceptType, - (NvU16)localEngineType, + (NvU16)gpuGetNv2080EngineType(localRmEngineType), notifierStatus, 0 /* Index */ ); break; @@ -95,7 +95,7 @@ krcErrorWriteNotifier_CPU KernelRc *pKernelRc, KernelChannel *pKernelChannel, NvU32 exceptType, - NvU32 localEngineType, + RM_ENGINE_TYPE localRmEngineType, NV_STATUS notifierStatus, NvU32 *pFlushFlags ) @@ -136,7 +136,7 @@ krcErrorWriteNotifier_CPU notifyFillNotifier(pGpu, pContextDma, exceptType, - (NvU16)localEngineType, + (NvU16)gpuGetNv2080EngineType(localRmEngineType), notifierStatus); } else if ((status = memGetByHandleAndDevice( @@ -149,7 +149,7 @@ krcErrorWriteNotifier_CPU pMemory, RES_GET_CLIENT_HANDLE(pKernelChannel), exceptType, - localEngineType, + localRmEngineType, notifierStatus); } @@ -177,7 +177,7 @@ krcErrorWriteNotifier_CPU notifyFillNotifier(pGpu, pContextDma, exceptType, - (NvU16)localEngineType, + (NvU16)gpuGetNv2080EngineType(localRmEngineType), notifierStatus); NV_PRINTF(LEVEL_INFO, "notified channel %d\n", kchannelGetDebugTag(pKernelChannel)); @@ -201,7 +201,7 @@ krcErrorWriteNotifier_CPU pMemory, RES_GET_CLIENT_HANDLE(pKernelChannel), exceptType, - localEngineType, + localRmEngineType, notifierStatus); if (status == NV_OK) { @@ -230,7 +230,7 @@ krcErrorWriteNotifier_CPU * * @param[in] pKernelChannel Channel * @param[in] exceptType Exception type written to notifier - * @param[in] nv2080EngineType Engine ID written to notifier + * @param[in] rmEngineType RM Engine ID written to notifier * @param[in] scope If we should notify every channel in the TSG * * @returns NV_OK if successful @@ -244,7 +244,7 @@ NV_STATUS krcErrorSetNotifier_IMPL KernelRc *pKernelRc, KernelChannel *pKernelChannel, NvU32 exceptType, - NvU32 nv2080EngineType, + RM_ENGINE_TYPE rmEngineType, RC_NOTIFIER_SCOPE scope ) { @@ -285,7 +285,7 @@ NV_STATUS krcErrorSetNotifier_IMPL for (pChanNode = pChanList->pHead; pChanNode; pChanNode = pChanNode->pNext) { - NvU32 localEngineType; + RM_ENGINE_TYPE localRmEngineType; KernelChannel *pKernelChannel = pChanNode->pKernelChannel; // @@ -293,9 +293,9 @@ NV_STATUS krcErrorSetNotifier_IMPL // Convert global ID to partition local if client has filled proper // engineIDs // - localEngineType = nv2080EngineType; + localRmEngineType = rmEngineType; if (IS_MIG_IN_USE(pGpu) && - nv2080EngineType > NV2080_ENGINE_TYPE_NULL) + RM_ENGINE_TYPE_IS_VALID(rmEngineType)) { KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); MIG_INSTANCE_REF ref; @@ -306,11 +306,11 @@ NV_STATUS krcErrorSetNotifier_IMPL if (status != NV_OK) goto Error; - if (!kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, nv2080EngineType, ref)) + if (!kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, rmEngineType, ref)) { NV_PRINTF(LEVEL_ERROR, - "Notifier requested for an unsupported engine (0x%x)\n", - nv2080EngineType); + "Notifier requested for an unsupported engine 0x%x (0x%x)\n", + gpuGetNv2080EngineType(rmEngineType), rmEngineType); status = NV_ERR_INVALID_ARGUMENT; goto Error; } @@ -318,8 +318,8 @@ NV_STATUS krcErrorSetNotifier_IMPL // Override the engine type with the local engine idx status = kmigmgrGetGlobalToLocalEngineType(pGpu, pKernelMIGManager, ref, - nv2080EngineType, - &localEngineType); + rmEngineType, + &localRmEngineType); if (status != NV_OK) goto Error; } @@ -328,7 +328,7 @@ NV_STATUS krcErrorSetNotifier_IMPL krcErrorWriteNotifier_HAL(pGpu, pKernelRc, pKernelChannel, exceptType, - localEngineType, + localRmEngineType, 0xffff /* notifierStatus */, &flushFlags), Error) @@ -438,7 +438,7 @@ krcErrorSendEventNotifications_KERNEL OBJGPU *pGpu, KernelRc *pKernelRc, KernelChannel *pKernelChannel, - NvU32 engineId, // unused + RM_ENGINE_TYPE rmEngineType, // unused NvU32 exceptType, RC_NOTIFIER_SCOPE scope, NvU16 partitionAttributionId diff --git a/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog.c b/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog.c index 7a6af11d9..5ee59b8a0 100644 --- a/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog.c +++ b/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog.c @@ -459,7 +459,7 @@ krcWatchdogInit_IMPL { NV0080_ALLOC_PARAMETERS nv0080; NV2080_ALLOC_PARAMETERS nv2080; - NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS channelGPFifo; + NV_CHANNEL_ALLOC_PARAMS channelGPFifo; NV_CONTEXT_DMA_ALLOCATION_PARAMS ctxDma; NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS virtual; NV_MEMORY_ALLOCATION_PARAMS mem; @@ -859,7 +859,7 @@ krcWatchdogInit_IMPL } { - NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS *pChannelGPFifo = + NV_CHANNEL_ALLOC_PARAMS *pChannelGPFifo = &pParams->channelGPFifo; // @@ -876,7 +876,7 @@ krcWatchdogInit_IMPL pChannelGPFifo->gpFifoEntries = WATCHDOG_GPFIFO_ENTRIES; // 2d object is only suppported on GR0 - pChannelGPFifo->engineType = NV2080_ENGINE_TYPE_GR0; + pChannelGPFifo->engineType = RM_ENGINE_TYPE_GR0; if (bClientUserd) pChannelGPFifo->hUserdMemory[0] = WATCHDOG_USERD_PHYS_MEM_ID; @@ -996,7 +996,7 @@ krcWatchdogInit_IMPL { NvU32 classID; - NvU32 engineID; + RM_ENGINE_TYPE engineID; status = kchannelGetClassEngineID_HAL(pGpu, pKernelChannel, WATCHDOG_GROBJ_ID, diff --git a/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog_callback.c b/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog_callback.c index b5784855e..e503c6617 100644 --- a/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog_callback.c +++ b/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog_callback.c @@ -22,6 +22,9 @@ */ #include "kernel/gpu/rc/kernel_rc.h" +#include "kernel/diagnostics/journal.h" +#include "kernel/gpu/disp/head/kernel_head.h" +#include "kernel/gpu/disp/kern_disp.h" #include "kernel/gpu/fifo/kernel_channel.h" #include "kernel/gpu/fifo/kernel_fifo.h" #include "kernel/gpu/gpu.h" @@ -29,6 +32,8 @@ #include "ctrl/ctrl906f.h" +#include "nverror.h" + // Seconds before watchdog tries to reset itself #define WATCHDOG_RESET_SECONDS 4 @@ -139,7 +144,7 @@ void krcWatchdogTimerProc KernelRc *pKernelRc = GPU_GET_KERNEL_RC(pGpu); krcWatchdog_HAL(pGpu, pKernelRc); - krcWatchdogCallbackVblankRecovery_HAL(pGpu, pKernelRc); + krcWatchdogCallbackVblankRecovery(pGpu, pKernelRc); krcWatchdogCallbackPerf_HAL(pGpu, pKernelRc); } } @@ -350,3 +355,94 @@ krcWatchdogRecovery_KERNEL NULL, 0); } + + +/*! + * @brief Recover VBlank callbacks that may have missed due to missing VBlank + */ +void krcWatchdogCallbackVblankRecovery_IMPL +( + OBJGPU *pGpu, + KernelRc *pKernelRc +) +{ + NvU32 head; + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + + if (!pKernelRc->bRobustChannelsEnabled || + (pKernelRc->watchdog.flags & WATCHDOG_FLAGS_DISABLED) || + !gpuIsGpuFullPower(pGpu) || (pKernelDisplay == NULL)) + { + return; + } + + for (head = 0; head < kdispGetNumHeads(pKernelDisplay); head++) + { + KernelHead *pKernelHead = KDISP_GET_HEAD(pKernelDisplay, head); + + if (kheadReadVblankIntrState(pGpu, pKernelHead) != + NV_HEAD_VBLANK_INTR_ENABLED) + { + continue; + } + + // + // Sliding windows -- we expect some failures around mode switches + // since vblank and watchdog are async to each other. This will + // dispose of these. + // + if (pKernelRc->watchdog.oldVblank[head] == + kheadGetVblankTotalCounter_HAL(pKernelHead)) + { + // VBlank Failed to Advance + pKernelRc->watchdog.vblankFailureCount[head]++; + + if (pKernelRc->watchdog.vblankFailureCount[head] > + pKernelRc->watchdogPersistent.timeoutSecs) + { + Journal *pRcDB = SYS_GET_RCDB(SYS_GET_INSTANCE()); + SYS_ERROR_INFO *pSysErrorInfo = &pRcDB->ErrorInfo; + + if (pKernelRc->bLogEvents && + pSysErrorInfo->LogCount < MAX_ERROR_LOG_COUNT) + { + pSysErrorInfo->LogCount++; + nvErrorLog_va((void *)pGpu, + ROBUST_CHANNEL_VBLANK_CALLBACK_TIMEOUT, + "Head %08x Count %08x", + head, + pKernelRc->watchdog.oldVblank[head]); + } + + NV_PRINTF(LEVEL_ERROR, + "NVRM-RC: RM has detected that %x Seconds without a Vblank Counter Update on head:%c%d\n", + pKernelRc->watchdogPersistent.timeoutSecs, + 'A' + head, + gpuGetInstance(pGpu)); + + // + // Have the VBlank Service run through in IMMEDIATE mode and + // process all queues + // + kdispServiceVblank_HAL(pGpu, pKernelDisplay, + NVBIT(head), + (VBLANK_STATE_PROCESS_IMMEDIATE | + VBLANK_STATE_PROCESS_ALL_CALLBACKS), + NULL /* threadstate */); + + pKernelRc->watchdog.vblankFailureCount[head] = 0; + } + } + else + { + if (pKernelRc->watchdog.vblankFailureCount[head] > 0) + { + pKernelRc->watchdog.vblankFailureCount[head]--; + } + } + + pKernelRc->watchdog.oldVblank[head] = kheadGetVblankTotalCounter_HAL( + pKernelHead); + } +} + diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice.c index 609297449..87f1a54f8 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/subdevice.c +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice.c @@ -129,13 +129,38 @@ subdeviceConstruct_IMPL return status; } +// +// subdeviceUnsetDynamicBoostLimit_IMPL +// +// Unset Dynamic Boost limit when nvidia-powerd is terminated +// +NV_STATUS +subdeviceUnsetDynamicBoostLimit_IMPL +( + Subdevice *pSubdevice +) +{ + if (!pSubdevice->bUpdateTGP) + return NV_OK; + + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + return pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_PMGR_UNSET_DYNAMIC_BOOST_LIMIT, + NULL, + 0); +} + void subdevicePreDestruct_IMPL ( Subdevice *pSubdevice ) { - subdeviceResetTGP(pSubdevice); + subdeviceUnsetDynamicBoostLimit(pSubdevice); } void @@ -160,13 +185,6 @@ subdeviceDestruct_IMPL // TODO - Call context lookup in dtor can likely be phased out now that we have RES_GET_CLIENT resGetFreeParams(staticCast(pSubdevice, RsResource), &pCallContext, NULL); - // free P2P objects associated with this subDevice - // can't rely on resource server to clean up since object exists in both lists - if (NULL != pSubdevice->pP2PMappingList) - { - CliFreeSubDeviceP2PList(pSubdevice, pCallContext); - } - // check for any pending client's timer notification for this subdevice if (pSubdevice->notifyActions[NV2080_NOTIFIERS_TIMER] != NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE) { @@ -232,119 +250,6 @@ subdeviceControlFilter_IMPL(Subdevice *pSubdevice, return NV_OK; } -NV_STATUS -subdeviceAddP2PApi_IMPL -( - Subdevice *pSubdevice, - P2PApi *pP2PApi -) -{ - PNODE pNode; - NvHandle hPeerSubDevice; - NV_STATUS status; - PCLI_P2P_INFO_LIST *pP2PInfoList; - NvHandle hSubDevice = RES_GET_HANDLE(pSubdevice); - - if (NULL == pP2PApi || NULL == pP2PApi->peer1 || NULL == pP2PApi->peer2) - { - return NV_ERR_INVALID_ARGUMENT; - } - - // - // in case of loopback, both handles are the same and this will not matter - // otherwise we need the peer subdevice handle - // - hPeerSubDevice = (RES_GET_HANDLE(pP2PApi->peer1) == hSubDevice) ? - RES_GET_HANDLE(pP2PApi->peer2) : - RES_GET_HANDLE(pP2PApi->peer1); - - if (NV_OK != btreeSearch(hPeerSubDevice, &pNode, - pSubdevice->pP2PMappingList)) - { - pP2PInfoList = portMemAllocNonPaged(sizeof(PCLI_P2P_INFO_LIST)); - if (pP2PInfoList == NULL) - { - status = NV_ERR_INSUFFICIENT_RESOURCES; - goto failed; - } - - listInit(pP2PInfoList, portMemAllocatorGetGlobalNonPaged()); - - pNode = portMemAllocNonPaged(sizeof(NODE)); - if (pNode == NULL) - { - status = NV_ERR_INSUFFICIENT_RESOURCES; - goto failed; - } - - portMemSet(pNode, 0, sizeof(NODE)); - pNode->keyStart = hPeerSubDevice; - pNode->keyEnd = hPeerSubDevice; - pNode->Data = pP2PInfoList; - - status = btreeInsert(pNode, &pSubdevice->pP2PMappingList); -failed: - if (NV_OK != status) - { - portMemFree(pNode); - portMemFree(pP2PInfoList); - return status; - } - } - else - { - pP2PInfoList = pNode->Data; - } - - listAppendValue(pP2PInfoList, &pP2PApi); - - return NV_OK; -} - -NV_STATUS -subdeviceDelP2PApi_IMPL -( - Subdevice *pSubdevice, - P2PApi *pP2PApi -) -{ - PCLI_P2P_INFO_LIST *pP2PInfoList; - PNODE pNode; - NV_STATUS status; - NvHandle hPeerSubDevice; - NvHandle hSubDevice = RES_GET_HANDLE(pSubdevice); - - // - // in case of loopback, both handles are the same and this will not matter - // otherwise we need the peer subdevice handle - // - hPeerSubDevice = (RES_GET_HANDLE(pP2PApi->peer1) == hSubDevice) ? - RES_GET_HANDLE(pP2PApi->peer2) : - RES_GET_HANDLE(pP2PApi->peer1); - - if (NV_OK != (status = btreeSearch(hPeerSubDevice, &pNode, pSubdevice->pP2PMappingList))) - return status; - - pP2PInfoList = pNode->Data; - - listRemoveFirstByValue(pP2PInfoList, &pP2PApi); - if (listCount(pP2PInfoList) == 0) - { - if (NV_OK != (status = btreeUnlink(pNode, &pSubdevice->pP2PMappingList))) - { - return status; - } - - pNode->Data = NULL; - portMemFree(pNode); - pNode = NULL; - portMemFree(pP2PInfoList); - pP2PInfoList = NULL; - } - - return NV_OK; -} - NV_STATUS subdeviceGetByHandle_IMPL ( diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_event_kernel.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_event_kernel.c index 7df4194f6..6379cfd6f 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_event_kernel.c +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_event_kernel.c @@ -69,7 +69,7 @@ subdeviceCtrlCmdEventSetTriggerFifo_IMPL { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - engineNonStallIntrNotifyEvent(pGpu, NV2080_ENGINE_TYPE_HOST, + engineNonStallIntrNotifyEvent(pGpu, RM_ENGINE_TYPE_HOST, pTriggerFifoParams->hEvent); return NV_OK; diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_fla.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_fla.c index 21148bb8a..0789112c9 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_fla.c +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_fla.c @@ -182,7 +182,7 @@ subdeviceCtrlCmdFlaRange_IMPL NV_ASSERT_OR_RETURN(pCallContext != NULL, NV_ERR_INVALID_STATE); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); if (!rmclientIsCapableOrAdminByHandle(hClient, NV_RM_CAP_EXT_FABRIC_MGMT, @@ -242,17 +242,6 @@ subdeviceCtrlCmdFlaRange_IMPL return status; } -// Control call to manage FLA range in RM -NV_STATUS -subdeviceCtrlCmdFlaSetupInstanceMemBlock_IMPL -( - Subdevice *pSubdevice, - NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS *pParams -) -{ - return NV_ERR_NOT_SUPPORTED; -} - // Control call to manage FLA range in RM NV_STATUS subdeviceCtrlCmdFlaGetRange_IMPL @@ -275,7 +264,7 @@ subdeviceCtrlCmdFlaGetFabricMemStats_IMPL FABRIC_VASPACE *pFabricVAS = NULL; NV_STATUS status = NV_OK; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); if (pGpu->pFabricVAS == NULL) { @@ -299,8 +288,8 @@ subdeviceCtrlCmdFlaGetFabricMemStats_IMPL return status; } - pParams->totalSize = fabricvaspaceGetVaLimit(pFabricVAS) - - fabricvaspaceGetVaStart(pFabricVAS) + 1; + pParams->totalSize = fabricvaspaceGetUCFlaLimit(pFabricVAS) - + fabricvaspaceGetUCFlaStart(pFabricVAS) + 1; return fabricvaspaceGetFreeHeap(pFabricVAS, &pParams->freeSize); } diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c index 754beb2a2..477d137bf 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c @@ -42,6 +42,7 @@ #include "kernel/gpu/intr/intr.h" #include "kernel/gpu/mc/kernel_mc.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" +#include "gpu/gpu_fabric_probe.h" #include "objtmr.h" #include "platform/chipset/chipset.h" #include "kernel/gpu/gr/kernel_graphics.h" @@ -60,7 +61,6 @@ - static NV_STATUS getGpuInfos(Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pParams, NvBool bCanAccessHw) { @@ -185,7 +185,7 @@ getGpuInfos(Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pParams, RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS params; - + if (IS_VIRTUAL(pGpu)) { data = IS_MIG_ENABLED(pGpu) ? @@ -675,7 +675,7 @@ subdeviceCtrlCmdGpuGetEncoderCapacity_IMPL { NV_STATUS rmStatus = NV_OK; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); if ((pEncoderCapacityParams->queryType != NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264) && (pEncoderCapacityParams->queryType != NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC)) @@ -781,7 +781,7 @@ subdeviceCtrlCmdGpuGetSdm_IMPL { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); pSdmParams->subdeviceMask = gpuGetSubdeviceMask(pGpu); @@ -804,7 +804,7 @@ subdeviceCtrlCmdGpuSetSdm_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); NvU32 subdeviceInstance; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); if (!ONEBITSET(pSdmParams->subdeviceMask)) { @@ -844,7 +844,7 @@ subdeviceCtrlCmdGpuGetSimulationInfo_IMPL { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); if (IS_SILICON(pGpu)) { @@ -875,7 +875,7 @@ subdeviceCtrlCmdGpuGetEngines_IMPL NvU32 *pKernelEngineList = NvP64_VALUE(pParams->engineList); NV_STATUS status = NV_OK; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); portMemSet(&getEngineParamsV2, 0, sizeof(getEngineParamsV2)); @@ -913,7 +913,7 @@ subdeviceCtrlCmdGpuGetEnginesV2_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); NV_STATUS status = NV_OK; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); // Update the engine Database NV_ASSERT_OK_OR_RETURN(gpuUpdateEngineTable(pGpu)); @@ -933,12 +933,22 @@ subdeviceCtrlCmdGpuGetEnginesV2_IMPL KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); if (pKernelMIGManager != NULL) { + RM_ENGINE_TYPE rmEngineTypeList[NV2080_GPU_MAX_ENGINES_LIST_SIZE]; + // Filter engines based on current partitioning scheme status = kmigmgrFilterEngineList(pGpu, pKernelMIGManager, pSubdevice, - pEngineParams->engineList, + rmEngineTypeList, &pEngineParams->engineCount); + + if (status == NV_OK) + { + // Convert the RM_ENGINE_TYPE list to NV2080_ENGINE_TYPE list + gpuGetNv2080EngineTypeList(rmEngineTypeList, + pEngineParams->engineCount, + pEngineParams->engineList); + } } } @@ -962,9 +972,9 @@ subdeviceCtrlCmdGpuGetEngineClasslist_IMPL ENGDESCRIPTOR engDesc; NV_STATUS status = NV_OK; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); - status = gpuXlateClientEngineIdToEngDesc(pGpu, pClassParams->engineType, &engDesc); + status = gpuXlateClientEngineIdToEngDesc(pGpu, gpuGetRmEngineType(pClassParams->engineType), &engDesc); NV_ASSERT(status == NV_OK); if (status != NV_OK) @@ -1004,18 +1014,21 @@ subdeviceCtrlCmdGpuGetEnginePartnerList_IMPL NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); ENGDESCRIPTOR engDesc; - NvU32 localType; + NvU32 localNv2080EngineType; + RM_ENGINE_TYPE rmEngineType; NvU32 i; PCLASSDESCRIPTOR pClass; NV_STATUS status = NV_OK; pPartnerListParams->numPartners = 0; - status = gpuXlateClientEngineIdToEngDesc(pGpu, pPartnerListParams->engineType, &engDesc); + rmEngineType = gpuGetRmEngineType(pPartnerListParams->engineType); + + status = gpuXlateClientEngineIdToEngDesc(pGpu, rmEngineType, &engDesc); if (NV_OK != status) { - NV_PRINTF(LEVEL_ERROR, "Invalid engine ID 0x%x\n", - pPartnerListParams->engineType); + NV_PRINTF(LEVEL_ERROR, "Invalid engine ID 0x%x (0x%x)\n", + pPartnerListParams->engineType, rmEngineType); return status; } @@ -1037,8 +1050,9 @@ subdeviceCtrlCmdGpuGetEnginePartnerList_IMPL return NV_ERR_NOT_SUPPORTED; } + localNv2080EngineType = pPartnerListParams->engineType; + // Translate the instance-local engine type to the global engine type in MIG mode - localType = pPartnerListParams->engineType; if (IS_MIG_IN_USE(pGpu)) { MIG_INSTANCE_REF ref; @@ -1049,8 +1063,11 @@ subdeviceCtrlCmdGpuGetEnginePartnerList_IMPL NV_CHECK_OK_OR_RETURN( LEVEL_ERROR, - kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, localType, - &pPartnerListParams->engineType)); + kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, + rmEngineType, + &rmEngineType)); + + pPartnerListParams->engineType = gpuGetNv2080EngineType(rmEngineType); } // See if the hal wants to handle this @@ -1058,7 +1075,7 @@ subdeviceCtrlCmdGpuGetEnginePartnerList_IMPL status = kfifoGetEnginePartnerList_HAL(pGpu, pKernelFifo, pPartnerListParams); // Restore the client's passed engineType - pPartnerListParams->engineType = localType; + pPartnerListParams->engineType = localNv2080EngineType; if (NV_OK == status) { @@ -1085,10 +1102,12 @@ subdeviceCtrlCmdGpuGetEnginePartnerList_IMPL // Copy over all of the engines except the target for (i = 0; i < pGpu->engineDB.size; i++) { + localNv2080EngineType = gpuGetNv2080EngineType(pGpu->engineDB.pType[i]); + // Skip the engine handed in - if (pGpu->engineDB.pType[i] != pPartnerListParams->engineType ) + if (localNv2080EngineType != pPartnerListParams->engineType ) { - pPartnerListParams->partnerList[pPartnerListParams->numPartners++] = pGpu->engineDB.pType[i]; + pPartnerListParams->partnerList[pPartnerListParams->numPartners++] = localNv2080EngineType; } } @@ -1120,9 +1139,9 @@ subdeviceCtrlCmdGpuGetEngineFaultInfo_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); NV_STATUS status = NV_OK; - NvU32 engineType = pParams->engineType; + RM_ENGINE_TYPE rmEngineType = gpuGetRmEngineType(pParams->engineType); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); // // When MIG is enabled, clients pass in their instance-specific engineId @@ -1140,14 +1159,14 @@ subdeviceCtrlCmdGpuGetEngineFaultInfo_IMPL NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, - pParams->engineType, - &engineType)); + rmEngineType, + &rmEngineType)); } // Populate HW info for SW engine entry - status = kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, ENGINE_INFO_TYPE_NV2080, - engineType, ENGINE_INFO_TYPE_MMU_FAULT_ID, - &pParams->mmuFaultId); + status = kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, ENGINE_INFO_TYPE_RM_ENGINE_TYPE, + (NvU32)rmEngineType, ENGINE_INFO_TYPE_MMU_FAULT_ID, + &pParams->mmuFaultId); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, @@ -1156,7 +1175,7 @@ subdeviceCtrlCmdGpuGetEngineFaultInfo_IMPL } // Only GR engine supports subcontext faulting on Volta+ chips - pParams->bSubcontextSupported = (NV2080_ENGINE_TYPE_IS_GR(engineType) && + pParams->bSubcontextSupported = (RM_ENGINE_TYPE_IS_GR(rmEngineType) && kfifoIsSubcontextSupported(pKernelFifo)); return status; @@ -1183,7 +1202,7 @@ subdeviceCtrlCmdGpuGetFermiGpcInfo_IMPL NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); NvHandle hSubdevice = RES_GET_HANDLE(pSubdevice); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmDeviceGpuLockIsOwner(GPU_RES_GET_GPU(pSubdevice)->gpuInstance)); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(GPU_RES_GET_GPU(pSubdevice)->gpuInstance)); portMemSet(&gpcMaskParams, 0, sizeof(gpcMaskParams)); @@ -1218,7 +1237,7 @@ subdeviceCtrlCmdGpuGetFermiTpcInfo_IMPL NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); NvHandle hSubdevice = RES_GET_HANDLE(pSubdevice); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmDeviceGpuLockIsOwner(GPU_RES_GET_GPU(pSubdevice)->gpuInstance)); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(GPU_RES_GET_GPU(pSubdevice)->gpuInstance)); portMemSet(&tpcMaskParams, 0, sizeof(tpcMaskParams)); tpcMaskParams.gpcId = pParams->gpcId; @@ -1256,7 +1275,7 @@ subdeviceCtrlCmdGpuGetFermiZcullInfo_IMPL NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); NvHandle hSubdevice = RES_GET_HANDLE(pSubdevice); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); portMemSet(&zcullMaskParams, 0, sizeof(zcullMaskParams)); zcullMaskParams.gpcId = pParams->gpcId; @@ -1301,7 +1320,7 @@ subdeviceCtrlCmdGpuGetPesInfo_IMPL // This ctrl call is due for deprecation and should not be used. // - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); NV_ASSERT_OK_OR_RETURN( serverGetClientUnderLock(&g_resServ, hClient, &pRsClient)); @@ -1344,7 +1363,7 @@ subdeviceCtrlCmdGpuQueryMode_IMPL { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); switch (gpuGetMode(pGpu)) { @@ -1398,7 +1417,7 @@ subdeviceCtrlCmdGpuSetComputeModeRules_IMPL { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); if (IS_GSP_CLIENT(pGpu)) { @@ -1475,7 +1494,7 @@ subdeviceCtrlCmdGpuQueryComputeModeRules_IMPL { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); { pQueryRulesParams->rules = pGpu->computeModeRules; @@ -1493,7 +1512,7 @@ subdeviceCtrlCmdGpuAcquireComputeModeReservation_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); //TODO Bug 2718406 will extend compute mode support for MIG if (IS_MIG_ENABLED(pGpu)) @@ -1556,7 +1575,7 @@ subdeviceCtrlCmdGpuReleaseComputeModeReservation_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); //TODO Bug 2718406 will extend compute mode support for MIG if (IS_MIG_ENABLED(pGpu)) @@ -1593,7 +1612,7 @@ subdeviceCtrlCmdGpuGetId_IMPL { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); pIdParams->gpuId = pGpu->gpuId; @@ -1620,7 +1639,7 @@ subdeviceCtrlCmdGpuGetPids_IMPL NV_ASSERT_OR_RETURN(RMCFG_FEATURE_KERNEL_RM, NV_ERR_NOT_SUPPORTED); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); switch (pGetPidsParams->idType) { @@ -1642,9 +1661,10 @@ subdeviceCtrlCmdGpuGetPids_IMPL } case (NV2080_CTRL_GPU_GET_PIDS_ID_TYPE_VGPU_GUEST): { - internalClassId = classId(HostVgpuDeviceApi); + internalClassId = classId(KernelHostVgpuDeviceApi); break; } + default: return NV_ERR_INVALID_ARGUMENT; } @@ -1706,7 +1726,7 @@ subdeviceCtrlCmdGpuGetPidInfo_IMPL NV_ASSERT_OR_RETURN(RMCFG_FEATURE_KERNEL_RM, NV_ERR_NOT_SUPPORTED); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); if ((pGetPidInfoParams->pidInfoListCount <= 0) || (pGetPidInfoParams->pidInfoListCount > @@ -1787,7 +1807,7 @@ subdeviceCtrlCmdGpuGetEngineRunlistPriBase_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); if (!kfifoIsHostEngineExpansionSupported(pKernelFifo)) { @@ -1797,7 +1817,7 @@ subdeviceCtrlCmdGpuGetEngineRunlistPriBase_IMPL for (i = 0; i < NV2080_GPU_MAX_ENGINES_LIST_SIZE; i++) { - NvU32 engineId; + RM_ENGINE_TYPE rmEngineType; // Check if input is NULL or a SW engine; return a NULL value since SW engine does not have a runlist pri base // and this should not be returned as an error @@ -1807,6 +1827,8 @@ subdeviceCtrlCmdGpuGetEngineRunlistPriBase_IMPL continue; } + rmEngineType = gpuGetRmEngineType(pParams->engineList[i]); + // // See if MIG is enabled. If yes, then we have to convert instanceLocal // engine to global engine before moving ahead @@ -1826,16 +1848,12 @@ subdeviceCtrlCmdGpuGetEngineRunlistPriBase_IMPL NV_CHECK_OK_OR_RETURN( LEVEL_ERROR, kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, - pParams->engineList[i], - &engineId)); - } - else - { - engineId = pParams->engineList[i]; + rmEngineType, + &rmEngineType)); } - tmpStatus = kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, ENGINE_INFO_TYPE_NV2080, - engineId, ENGINE_INFO_TYPE_RUNLIST_PRI_BASE, + tmpStatus = kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, ENGINE_INFO_TYPE_RM_ENGINE_TYPE, + rmEngineType, ENGINE_INFO_TYPE_RUNLIST_PRI_BASE, &pParams->runlistPriBase[i]); if (tmpStatus != NV_OK) @@ -1861,7 +1879,7 @@ subdeviceCtrlCmdGpuGetHwEngineId_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); if (!kfifoIsHostEngineExpansionSupported(pKernelFifo)) { @@ -1871,7 +1889,7 @@ subdeviceCtrlCmdGpuGetHwEngineId_IMPL for (i = 0; i < NV2080_GPU_MAX_ENGINES_LIST_SIZE; i++) { - NvU32 engineId; + RM_ENGINE_TYPE rmEngineType; // Check if input is NULL or a SW engine; return a NULL value since SW engine does not have a runlist pri base // and this should not be returned as an error @@ -1881,6 +1899,8 @@ subdeviceCtrlCmdGpuGetHwEngineId_IMPL continue; } + rmEngineType = gpuGetRmEngineType(pParams->engineList[i]); + // // See if MIG is enabled. If yes, then we have to convert instanceLocal // engine to global engine before moving ahead @@ -1900,16 +1920,12 @@ subdeviceCtrlCmdGpuGetHwEngineId_IMPL NV_CHECK_OK_OR_RETURN( LEVEL_ERROR, kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, - pParams->engineList[i], - &engineId)); - } - else - { - engineId = pParams->engineList[i]; + rmEngineType, + &rmEngineType)); } - tmpStatus = kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, ENGINE_INFO_TYPE_NV2080, - engineId, + tmpStatus = kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, ENGINE_INFO_TYPE_RM_ENGINE_TYPE, + (NvU32)rmEngineType, ENGINE_INFO_TYPE_FIFO_TAG, &pParams->hwEngineID[i]); @@ -1932,7 +1948,7 @@ subdeviceCtrlCmdGpuGetMaxSupportedPageSize_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); NV_STATUS status = NV_OK; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); // Default to minimal page size (4k) pParams->maxSupportedPageSize = RM_PAGE_SIZE; @@ -1964,7 +1980,7 @@ subdeviceCtrlCmdGpuGetMaxSupportedPageSize_IMPL return status; } -#if (defined(DEBUG) || defined(DEVELOP) || defined(NV_MODS)) && RMCFG_MODULE_KERNEL_GRAPHICS +#if (defined(DEBUG) || defined(DEVELOP) || RMCFG_FEATURE_MODS_FEATURES) && RMCFG_MODULE_KERNEL_GRAPHICS NV_STATUS subdeviceCtrlCmdGpuGetNumMmusPerGpc_IMPL ( @@ -2031,7 +2047,7 @@ subdeviceCtrlCmdGpuSetComputePolicyConfig_IMPL NvU32 gidFlags; NV_STATUS status = NV_OK; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); switch(pParams->config.type) { @@ -2107,7 +2123,7 @@ subdeviceCtrlCmdGpuGetComputePolicyConfig_IMPL NvU32 gidFlags; NV_STATUS status = NV_OK; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); gidFlags = DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _TYPE, _SHA1) | DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _FORMAT, _BINARY); @@ -2211,7 +2227,7 @@ NV_STATUS subdeviceCtrlCmdValidateMemMapRequest_IMPL NvU32 bar0MapSize; NvU64 bar0MapOffset; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); pParams->protection = NV_PROTECT_READ_WRITE; @@ -2276,6 +2292,167 @@ NV_STATUS subdeviceCtrlCmdValidateMemMapRequest_IMPL return NV_ERR_PROTECTION_FAULT; } +/*! + * @brief Computes the GFID (GPU Function ID) for a given SR-IOV + * Virtual Function (VF) of the physical GPU based on the + * BDF parameters provided by the caller. + * + * Lock Requirements: + * Assert that API and GPUs lock held on entry + * + * @param[in] pSubdevice + * @param[in] pParams pointer to control parameters + * + * Possible status values returned are: + * NV_OK on successful computation of a valid GFID + * NV_ERR_NOT_SUPPORTED if ctrl call is made when + * SRIOV is not enabled OR + * caller is not FM from Host RM + * NV_ERR_INVALID_STATE if computed GFID is greater than + * max GFID that is expected/allowed + */ +NV_STATUS +subdeviceCtrlCmdGpuGetGfid_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_GPU_GET_GFID_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + NvU32 pciFunction, gfid; + + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + if (!gpuIsSriovEnabled(pGpu)) + return NV_ERR_NOT_SUPPORTED; + + // Host RM && FM + if ((!IS_VIRTUAL(pGpu)) && + (pSys->getProperty(pSys, PDB_PROP_SYS_FABRIC_IS_EXTERNALLY_MANAGED))) + { + // + // In unix based systems, OS uses lspci format which is "ssss:bb:dd.f", + // so device is 5 bits and function 3 bits. + // for SR-IOV when ARI is enabled, device and function gets combined and + // we need to consider 8 bits function. + // + pciFunction = (pParams->device << 3) | pParams->func; + gfid = (pciFunction - pGpu->sriovState.firstVFOffset) + 1; + + if (gfid > pGpu->sriovState.maxGfid) + { + NV_PRINTF(LEVEL_ERROR, "Computed GFID %d greater than max supported GFID\n", gfid); + return NV_ERR_INVALID_STATE; + } + + pParams->gfid = gfid; + // Also set the mask for max gfid supported currently in the driver + pParams->gfidMask = (pGpu->sriovState.maxGfid - 1); + } + else + { + return NV_ERR_NOT_SUPPORTED; + } + + return NV_OK; +} + +/*! + * @brief Sets or unsets the SW state to inform the GPU driver that the GPU instance + * associated with input GFID has been activated or de-activated respectively. + * + * Lock Requirements: + * Assert that API and GPUs lock held on entry + * + * @param[in] pSubdevice + * @param[in] pParams pointer to control parameters + * + * Possible status values returned are: + * NV_OK on success + * NV_ERR_INVALID_STATE if SRIOV state for P2P in driver is not setup + * NV_ERR_INVALID_ARGUMENT if input GFID is greater than the max GFID allowed + * NV_ERR_NOT_SUPPORTED if ctrl call is made when + * SRIOV is not enabled OR + * caller is not FM from Host RM + * NV_ERR_IN_USE If MAX_NUM_P2P_GFIDS have already been enabled for P2P + */ +NV_STATUS +subdeviceCtrlCmdUpdateGfidP2pCapability_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + PSRIOV_P2P_INFO pP2PInfo = pGpu->sriovState.pP2PInfo; + NvBool bSetP2PAccess = NV_FALSE; + NvU32 idx; + + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + if (!gpuIsSriovEnabled(pGpu)) + return NV_ERR_NOT_SUPPORTED; + + NV_ASSERT_OR_RETURN(pP2PInfo != NULL, NV_ERR_INVALID_STATE); + + // Ctrl call should only be called by the FM from Host RM + if ((!IS_VIRTUAL(pGpu)) && + (pSys->getProperty(pSys, PDB_PROP_SYS_FABRIC_IS_EXTERNALLY_MANAGED))) + { + if (pParams->gfid > pGpu->sriovState.maxGfid) + { + NV_PRINTF(LEVEL_ERROR, "Input GFID %d greater than max allowed GFID\n", pParams->gfid); + return NV_ERR_INVALID_ARGUMENT; + } + + for (idx = 0; idx < pGpu->sriovState.maxP2pGfid; idx++) + { + // + // Check if Host RM is already using a GFID for P2P, + // Since only "MAX_NUM_P2P_GFIDS" GFID(s) is(are) allowed to do P2P at any time, + // we should fail here if a GFID greater than supported number is being enabled + // + if (pParams->bEnable) + { + if (pP2PInfo[idx].gfid == INVALID_P2P_GFID) + { + pP2PInfo[idx].gfid = pParams->gfid; + bSetP2PAccess = NV_TRUE; + break; + } + } + else + { + if (pP2PInfo[idx].gfid == pParams->gfid) + { + pP2PInfo[idx].gfid = INVALID_P2P_GFID; + bSetP2PAccess = NV_TRUE; + break; + } + } + } + + if (bSetP2PAccess == NV_TRUE) + { + pP2PInfo[idx].bAllowP2pAccess = pParams->bEnable; + } + else + { + // Some other GFID(s) has already been enabled to do P2P + // Fail the call + return NV_ERR_IN_USE; + } + } + else + { + return NV_ERR_NOT_SUPPORTED; + } + + return NV_OK; +} + /*! * @brief: This command returns the load time (latency) of each engine, * implementing NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES control call. @@ -2340,7 +2517,7 @@ subdeviceCtrlCmdGpuSetFabricAddr_IMPL NV_ASSERT_OR_RETURN(RMCFG_FEATURE_KERNEL_RM, NV_ERR_NOT_SUPPORTED); NV_ASSERT_OR_RETURN(pCallContext != NULL, NV_ERR_INVALID_STATE); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); if (!rmclientIsCapableOrAdminByHandle(hClient, NV_RM_CAP_EXT_FABRIC_MGMT, @@ -2357,3 +2534,93 @@ subdeviceCtrlCmdGpuSetFabricAddr_IMPL return knvlinkSetUniqueFabricBaseAddress(pGpu, pKernelNvlink, pParams->fabricBaseAddr); } + +static NvU64 +_convertGpuFabricProbeInfoCaps +( + NvU64 fmCaps +) +{ + NvU64 fabricCaps = 0; + NvU32 i = 0; + + FOR_EACH_INDEX_IN_MASK(64, i, fmCaps) + { + switch (NVBIT64(i)) + { + case NVLINK_INBAND_FM_CAPS_MC_TEAM_SETUP_V1: + case NVLINK_INBAND_FM_CAPS_MC_TEAM_RELEASE_V1: + { + fabricCaps |= NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_SUPPORTED; + break; + } + default: + { + break; + } + } + } + FOR_EACH_INDEX_IN_MASK_END; + + return fabricCaps; +} + +NV_STATUS +subdeviceCtrlCmdGetGpuFabricProbeInfo_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + NV_STATUS status; + NvU64 numProbeReqs = 0; + NvU64 fmCaps = 0; + NvUuid *pClusterUuid = (NvUuid*) pParams->clusterUuid; + + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && + rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); + + if (pGpu->pGpuFabricProbeInfo == NULL) + { + pParams->state = NV2080_CTRL_GPU_FABRIC_PROBE_STATE_UNSUPPORTED; + return NV_OK; + } + + status = gpuFabricProbeGetNumProbeReqs(pGpu->pGpuFabricProbeInfo, + &numProbeReqs); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Error while retrieving numProbeReqs\n"); + return status; + } + + pParams->state = (numProbeReqs == 0) ? + NV2080_CTRL_GPU_FABRIC_PROBE_STATE_NOT_STARTED : + NV2080_CTRL_GPU_FABRIC_PROBE_STATE_IN_PROGRESS; + + if (gpuFabricProbeIsReceived(pGpu->pGpuFabricProbeInfo)) + { + pParams->state = NV2080_CTRL_GPU_FABRIC_PROBE_STATE_COMPLETE; + pParams->status = gpuFabricProbeGetFmStatus(pGpu->pGpuFabricProbeInfo); + if (pParams->status != NV_OK) + { + // Nothing needs to be done as probe response status is not success + return NV_OK; + } + + ct_assert(NV2080_GPU_FABRIC_CLUSTER_UUID_LEN == NV_UUID_LEN); + + NV_ASSERT_OK(gpuFabricProbeGetClusterUuid(pGpu->pGpuFabricProbeInfo, + pClusterUuid)); + + NV_ASSERT_OK(gpuFabricProbeGetFabricPartitionId(pGpu->pGpuFabricProbeInfo, + &pParams->fabricPartitionId)); + + NV_ASSERT_OK(gpuFabricProbeGetfmCaps(pGpu->pGpuFabricProbeInfo, &fmCaps)); + + pParams->fabricCaps = _convertGpuFabricProbeInfoCaps(fmCaps); + } + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_regops.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_regops.c index 27979c20e..33f2d4b3d 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_regops.c +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_regops.c @@ -72,6 +72,11 @@ gpuValidateRegOps { regStatus = NV2080_CTRL_GPU_REG_OP_STATUS_SUCCESS; + if (isClientGspPlugin) + { + return NV_ERR_INVALID_ARGUMENT; + } + else { NV_STATUS status; @@ -104,6 +109,7 @@ subdeviceCtrlCmdGpuExecRegOps_cmn NvU32 bNonTransactional, NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, NV2080_CTRL_GPU_REG_OP *pRegOps, + NvU32 *pOpSmIds, NvU32 regOpCount, NvBool isClientGspPlugin ) @@ -112,8 +118,9 @@ subdeviceCtrlCmdGpuExecRegOps_cmn NV_STATUS status = NV_OK; CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; + NvBool bUseMigratableOps; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); NV_PRINTF(LEVEL_INFO, "client 0x%x channel 0x%x\n", hClientTarget, hChannelTarget); @@ -138,6 +145,12 @@ subdeviceCtrlCmdGpuExecRegOps_cmn return NV_ERR_INVALID_PARAM_STRUCT; } + // + // pOpSmIds should will only be non-NULL when this code path is being + // used by the migratable ops function. + // + bUseMigratableOps = (pOpSmIds != NULL); + // init once, only in monolithic-rm or the cpu-rm, or gsp-rm if the call // is from the gsp plugin if (!RMCFG_FEATURE_PLATFORM_GSP || isClientGspPlugin) @@ -154,12 +167,29 @@ subdeviceCtrlCmdGpuExecRegOps_cmn if (IS_GSP_CLIENT(pGpu)) { + // + // If this function is being used by a MIGRATABLE_OPS call, + // we route the GSP call to normal DMA controller + // + if (bUseMigratableOps) + { + NV_RM_RPC_CONTROL(pGpu, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->cmd, + pRmCtrlParams->pParams, + pRmCtrlParams->paramsSize, + status); + } + else + { NV_RM_RPC_GPU_EXEC_REG_OPS(pGpu, pRmCtrlParams->hClient, pRmCtrlParams->hObject, pRmCtrlParams->pParams, pRegOps, status); + } return status; } @@ -185,6 +215,38 @@ subdeviceCtrlCmdGpuExecRegOps_IMPL pRegParams->bNonTransactional, pRegParams->grRouteInfo, pRegParams->regOps, + NULL, + pRegParams->regOpCount, + NV_FALSE); +} + +// +// subdeviceCtrlCmdGpuMigratableOps +// +// Lock Requirements: +// Assert that API lock and GPUs lock held on entry +// +NV_STATUS +subdeviceCtrlCmdGpuMigratableOps_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS *pRegParams +) +{ + if (pRegParams->regOpCount > NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX) + { + NV_PRINTF(LEVEL_ERROR, "Invalid regOpCount: %ud\n", + pRegParams->regOpCount); + return NV_ERR_INVALID_PARAM_STRUCT; + } + + return subdeviceCtrlCmdGpuExecRegOps_cmn(pSubdevice, + pRegParams->hClientTarget, + pRegParams->hChannelTarget, + pRegParams->bNonTransactional, + pRegParams->grRouteInfo, + pRegParams->regOps, + pRegParams->smIds, pRegParams->regOpCount, NV_FALSE); } diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_timer_kernel.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_timer_kernel.c index 74e931e9e..e40d1e45a 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_timer_kernel.c +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_timer_kernel.c @@ -54,7 +54,7 @@ subdeviceCtrlCmdTimerCancel_IMPL OBJGPU *pGpu; OBJTMR *pTmr; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); if (pSubdevice == NULL) { @@ -202,7 +202,7 @@ subdeviceCtrlCmdTimerSchedule_IMPL } else { - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); } return timerSchedule(pSubdevice, pParams); @@ -238,7 +238,7 @@ subdeviceCtrlCmdTimerGetTime_IMPL } else { - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); } tmrGetCurrentTime(pTmr, &pParams->time_nsec); @@ -262,7 +262,7 @@ subdeviceCtrlCmdTimerGetRegisterOffset_IMPL { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); return gpuGetRegBaseOffset_HAL(pGpu, NV_REG_BASE_TIMER, &pTimerRegOffsetParams->tmr_offset); } @@ -290,7 +290,7 @@ subdeviceCtrlCmdTimerGetGpuCpuTimeCorrelationInfo_IMPL NvU8 i; NvU32 sec, usec; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); NV_ASSERT_OR_RETURN((pParams->sampleCount <= NV2080_CTRL_TIMER_GPU_CPU_TIME_MAX_SAMPLES), @@ -442,7 +442,7 @@ subdeviceCtrlCmdTimerSetGrTickFreq_IMPL OBJREFCNT *pRefcnt; NvHandle hSubDevice; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); if (pSubdevice == NULL || pTmr == NULL) { diff --git a/src/nvidia/src/kernel/gpu/timed_semaphore.c b/src/nvidia/src/kernel/gpu/timed_semaphore.c index a5f828682..84ae13585 100644 --- a/src/nvidia/src/kernel/gpu/timed_semaphore.c +++ b/src/nvidia/src/kernel/gpu/timed_semaphore.c @@ -116,35 +116,17 @@ _9074TimedSemRelease NV_STATUS status; NV_STATUS overallStatus = NV_OK; - status = semaphoreFillGPUVATimestamp(pGpu, - hClient, - pObject->pKernelChannel->hVASpace, - semaphoreGPUVA, - releaseValue, - 0, /* Index */ - NV_TRUE, - time); + status = tsemaRelease_HAL(pGpu, + semaphoreGPUVA, + notifierGPUVA, + pObject->pKernelChannel->hVASpace, + releaseValue, + notifierStatus, + hClient); + + // timedSemaphoreRelease_HAL will print errors on its own if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "Semaphore fill failed, error 0x%x\n", status); - - if (overallStatus == NV_OK) - overallStatus = status; - } - - status = notifyFillNotifierGPUVATimestamp(pGpu, - hClient, - pObject->pKernelChannel->hVASpace, - notifierGPUVA, - 0, /* Info32 */ - 0, /* Info16 */ - notifierStatus, - 0, /* Index */ - time); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "Notifier fill failed, error 0x%x\n", status); - if (overallStatus == NV_OK) overallStatus = status; } @@ -642,3 +624,57 @@ NV_STATUS tsemaGetSwMethods_IMPL return NV_OK; } +NV_STATUS +tsemaRelease_KERNEL +( + OBJGPU *pGpu, + NvU64 semaphoreVA, + NvU64 notifierVA, + NvU32 hVASpace, + NvU32 releaseValue, + NvU32 completionStatus, + NvHandle hClient +) +{ + OBJTMR *pTmr = GPU_GET_TIMER(pGpu); + NvU64 currentTime; + NV_STATUS status; + NV_STATUS overallStatus = NV_OK; + + tmrGetCurrentTime(pTmr, ¤tTime); + + status = semaphoreFillGPUVATimestamp(pGpu, + hClient, + hVASpace, + semaphoreVA, + releaseValue, + 0, /* Index */ + NV_TRUE, + currentTime); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Semaphore fill failed, error 0x%x\n", status); + + if (overallStatus == NV_OK) + overallStatus = status; + } + + status = notifyFillNotifierGPUVATimestamp(pGpu, + hClient, + hVASpace, + notifierVA, + 0, /* Info32 */ + 0, /* Info16 */ + completionStatus, + 0, /* Index */ + currentTime); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Notifier fill failed, error 0x%x\n", status); + + if (overallStatus == NV_OK) + overallStatus = status; + } + + return overallStatus; +} diff --git a/src/nvidia/src/kernel/gpu/timer/arch/hopper/timer_gh100.c b/src/nvidia/src/kernel/gpu/timer/arch/hopper/timer_gh100.c index f9a5c6d1f..127515e36 100644 --- a/src/nvidia/src/kernel/gpu/timer/arch/hopper/timer_gh100.c +++ b/src/nvidia/src/kernel/gpu/timer/arch/hopper/timer_gh100.c @@ -43,7 +43,6 @@ * @param[in] pTmr- Timer Object pointer * * @return NV_OK - * @return NV_ERR_PRIV_SEC_VIOLATION - PTIMER_TIME is read-only. */ NV_STATUS tmrSetCurrentTime_GH100 ( @@ -51,37 +50,22 @@ NV_STATUS tmrSetCurrentTime_GH100 OBJTMR *pTmr ) { - NV_STATUS status; + NvU64 ns; + NvU32 seconds; + NvU32 useconds; - // We can only set the time if level 0 is allowed to write - if (GPU_FLD_TEST_DRF_DEF(pGpu, _PTIMER, _TIME_PRIV_LEVEL_MASK, _WRITE_PROTECTION_LEVEL0, _ENABLE)) - { - NvU64 ns; - NvU32 seconds; - NvU32 useconds; + osGetCurrentTime(&seconds, &useconds); - osGetCurrentTime(&seconds, &useconds); + NV_PRINTF(LEVEL_INFO, + "osGetCurrentTime returns 0x%x seconds, 0x%x useconds\n", + seconds, useconds); - NV_PRINTF(LEVEL_INFO, - "osGetCurrentTime returns 0x%x seconds, 0x%x useconds\n", - seconds, useconds); + ns = ((NvU64)seconds * 1000000 + useconds) * 1000; - ns = ((NvU64)seconds * 1000000 + useconds) * 1000; + GPU_REG_WR32(pGpu, NV_PGC6_SCI_SYS_TIMER_OFFSET_1, NvU64_HI32(ns)); + GPU_REG_WR32(pGpu, NV_PGC6_SCI_SYS_TIMER_OFFSET_0, NvU64_LO32(ns)); - GPU_REG_WR32(pGpu, NV_PGC6_SCI_SYS_TIMER_OFFSET_1, NvU64_HI32(ns)); - GPU_REG_WR32(pGpu, NV_PGC6_SCI_SYS_TIMER_OFFSET_0, NvU64_LO32(ns)); - - status = NV_OK; - } - else - { - NV_PRINTF(LEVEL_ERROR, - "ERROR: Write to PTIMER attempted even though Level 0 PLM is disabled.\n"); - NV_ASSERT(0); - status = NV_ERR_PRIV_SEC_VIOLATION; - } - - return status; + return NV_OK; } NV_STATUS diff --git a/src/nvidia/src/kernel/gpu/timer/timer.c b/src/nvidia/src/kernel/gpu/timer/timer.c index 341e224ec..d4d66a156 100644 --- a/src/nvidia/src/kernel/gpu/timer/timer.c +++ b/src/nvidia/src/kernel/gpu/timer/timer.c @@ -191,11 +191,8 @@ tmrDestruct_IMPL(OBJTMR *pTmr) pTmr->pTmrSwrlLock = NULL; } - if (pTmr->pGrTickFreqRefcnt != NULL) - { - objDelete(pTmr->pGrTickFreqRefcnt); - pTmr->pGrTickFreqRefcnt = NULL; - } + objDelete(pTmr->pGrTickFreqRefcnt); + pTmr->pGrTickFreqRefcnt = NULL; osDestroy1HzCallbacks(pTmr); } @@ -238,7 +235,8 @@ NV_STATUS tmrEventCreate_IMPL (*ppEventPublic)->pUserData = pUserData; (*ppEventPublic)->flags = flags; - if (pTmr->getProperty(pTmr, PDB_PROP_TMR_USE_OS_TIMER_FOR_CALLBACKS)) + if (pTmr->getProperty(pTmr, PDB_PROP_TMR_USE_OS_TIMER_FOR_CALLBACKS) || + (flags & TMR_FLAG_USE_OS_TIMER)) { status = tmrEventCreateOSTimer_HAL(pTmr, *ppEventPublic); if (status != NV_OK) @@ -341,7 +339,8 @@ void tmrEventCancel_IMPL pEvent->bInUse = NV_FALSE; - if (pTmr->getProperty(pTmr, PDB_PROP_TMR_USE_OS_TIMER_FOR_CALLBACKS)) + if (pTmr->getProperty(pTmr, PDB_PROP_TMR_USE_OS_TIMER_FOR_CALLBACKS) || + (pEventPublic->flags & TMR_FLAG_USE_OS_TIMER)) { NV_STATUS status = NV_OK; status = tmrEventCancelOSTimer_HAL(pTmr, pEventPublic); @@ -399,7 +398,8 @@ void tmrEventDestroy_IMPL if (pEvent != NULL) { NV_ASSERT(!pEvent->bLegacy); - if (pTmr->getProperty(pTmr, PDB_PROP_TMR_USE_OS_TIMER_FOR_CALLBACKS)) + if (pTmr->getProperty(pTmr, PDB_PROP_TMR_USE_OS_TIMER_FOR_CALLBACKS) || + (pEventPublic->flags & TMR_FLAG_USE_OS_TIMER)) { // OS timer destroying will cancel the timer tmrEventDestroyOSTimer_HAL(pTmr, pEventPublic); @@ -552,7 +552,8 @@ NV_STATUS tmrEventScheduleRel_IMPL if (rmStatus != NV_OK) return rmStatus; - if (pTmr->getProperty(pTmr, PDB_PROP_TMR_USE_OS_TIMER_FOR_CALLBACKS)) + if (pTmr->getProperty(pTmr, PDB_PROP_TMR_USE_OS_TIMER_FOR_CALLBACKS) || + (pEvent->flags & TMR_FLAG_USE_OS_TIMER)) { /*HR timer scheduled in relative mode*/ /*TBD : This condition needs to be moved to OS timer handling functions */ @@ -837,7 +838,8 @@ NV_STATUS tmrEventScheduleAbs_IMPL NV_STATUS rmStatus = NV_OK; PTMR_EVENT_PVT pEvent = (PTMR_EVENT_PVT)pEventPublic; - if (pTmr->getProperty(pTmr, PDB_PROP_TMR_USE_OS_TIMER_FOR_CALLBACKS)) + if (pTmr->getProperty(pTmr, PDB_PROP_TMR_USE_OS_TIMER_FOR_CALLBACKS) || + (pEventPublic->flags & TMR_FLAG_USE_OS_TIMER)) { NV_CHECK_OK(rmStatus, LEVEL_ERROR, tmrEventScheduleAbsOSTimer_HAL(pTmr, pEventPublic, Time)); diff --git a/src/nvidia/src/kernel/gpu/uvm/arch/turing/uvm_tu102.c b/src/nvidia/src/kernel/gpu/uvm/arch/turing/uvm_tu102.c index 3448b316e..799e7cfb1 100644 --- a/src/nvidia/src/kernel/gpu/uvm/arch/turing/uvm_tu102.c +++ b/src/nvidia/src/kernel/gpu/uvm/arch/turing/uvm_tu102.c @@ -31,7 +31,6 @@ #include "ctrl/ctrlc365.h" #include "published/turing/tu102/dev_access_counter.h" #include "published/turing/tu102/dev_vm.h" -#include "published/turing/tu102/dev_fb.h" NV_STATUS uvmReadAccessCntrBufferPutPtr_TU102 @@ -147,7 +146,7 @@ uvmReadAccessCntrBufferFullPtr_TU102 NvU32 fullPtrValue; fullPtrValue = GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO); - if (fullPtrValue & NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_FULL_TRUE) + if (fullPtrValue & NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_FULL_TRUE) { *fullFlag = NV_TRUE; } @@ -225,46 +224,46 @@ uvmAccessCntrSetGranularity_TU102(POBJGPU pGpu, POBJUVM pUvm, ACCESS_CNTR_TYPE a } void -uvmWriteAccessCntrBufferHiReg_TU102 +uvmProgramWriteAccessCntrBufferAddress_TU102 ( - POBJGPU pGpu, - POBJUVM pUvm, - NvU32 hiVal + OBJGPU *pGpu, + OBJUVM *pUvm, + NvU64 addr ) { - GPU_VREG_WR32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI, hiVal); + GPU_VREG_WR32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI, NvU64_HI32(addr)); + GPU_VREG_WR32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO, NvU64_LO32(addr)); } void -uvmWriteAccessCntrBufferLoReg_TU102 +uvmProgramAccessCntrBufferEnabled_TU102 ( - POBJGPU pGpu, - POBJUVM pUvm, - NvU32 loVal + OBJGPU *pGpu, + OBJUVM *pUvm, + NvBool bEn ) { - - GPU_VREG_WR32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO, loVal); + GPU_VREG_FLD_WR_DRF_NUM(pGpu, _VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO, _EN, bEn); } -NvU32 -uvmReadAccessCntrBufferLoReg_TU102 +NvBool +uvmIsAccessCntrBufferEnabled_TU102 ( - POBJGPU pGpu, - POBJUVM pUvm + OBJGPU *pGpu, + OBJUVM *pUvm ) { - return GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO); + return (NvBool) GPU_VREG_RD_DRF(pGpu, _VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO, _EN); } -NvU32 -uvmReadAccessCntrBufferInfoReg_TU102 +NvBool +uvmIsAccessCntrBufferPushed_TU102 ( - POBJGPU pGpu, - POBJUVM pUvm + OBJGPU *pGpu, + OBJUVM *pUvm ) { - return GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO); + return GPU_VREG_FLD_TEST_DRF_DEF(pGpu, _VIRTUAL_FUNCTION, _PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO, _PUSHED, _TRUE); } NV_STATUS diff --git a/src/nvidia/src/kernel/gpu/uvm/arch/volta/uvm_gv100.c b/src/nvidia/src/kernel/gpu/uvm/arch/volta/uvm_gv100.c index 7c58dd98b..457f79b11 100644 --- a/src/nvidia/src/kernel/gpu/uvm/arch/volta/uvm_gv100.c +++ b/src/nvidia/src/kernel/gpu/uvm/arch/volta/uvm_gv100.c @@ -33,6 +33,7 @@ #include "gpu/uvm/uvm.h" #include "os/os.h" #include "gpu/mem_mgr/mem_mgr.h" +#include "gpu/mem_mgr/mem_desc.h" #include "gpu/bus/kern_bus.h" #include "rmapi/event.h" @@ -48,8 +49,6 @@ uvmSetupAccessCntrBuffer_GV100 ) { KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); - NvU32 accessCntrBufferHi = 0; - NvU32 accessCntrBufferLo = 0; NvU64 vaddr; NV_STATUS status = NV_OK; @@ -73,11 +72,8 @@ uvmSetupAccessCntrBuffer_GV100 } pUvm->accessCntrBuffer.bar2UvmAccessCntrBufferAddr = vaddr; - accessCntrBufferHi = NvU64_HI32(pUvm->accessCntrBuffer.bar2UvmAccessCntrBufferAddr); - accessCntrBufferLo = NvU64_LO32(pUvm->accessCntrBuffer.bar2UvmAccessCntrBufferAddr); - - uvmWriteAccessCntrBufferHiReg_HAL(pGpu, pUvm, accessCntrBufferHi); - uvmWriteAccessCntrBufferLoReg_HAL(pGpu, pUvm, accessCntrBufferLo); + uvmProgramWriteAccessCntrBufferAddress_HAL(pGpu, pUvm, vaddr); + uvmProgramAccessCntrBufferEnabled_HAL(pGpu, pUvm, NV_FALSE); return NV_OK; } @@ -107,9 +103,7 @@ uvmDisableAccessCntr_GV100 bIsErrorRecovery = NV_TRUE; } - uvmWriteAccessCntrBufferLoReg_HAL(pGpu, pUvm, - FLD_SET_DRF( _PFB_NISO, _ACCESS_COUNTER_NOTIFY_BUFFER_LO, _EN, _FALSE, - uvmReadAccessCntrBufferLoReg_HAL(pGpu, pUvm))); + uvmProgramAccessCntrBufferEnabled_HAL(pGpu, pUvm, NV_FALSE); // // Check for any pending notifications which might be pending in pipe to ensure @@ -119,11 +113,9 @@ uvmDisableAccessCntr_GV100 // bit to show up for all packets and then reset the buffer // gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); - if (FLD_TEST_DRF(_PFB_NISO, _ACCESS_COUNTER_NOTIFY_BUFFER_LO, _EN, _FALSE, - uvmReadAccessCntrBufferLoReg_HAL(pGpu, pUvm))) + if (!uvmIsAccessCntrBufferEnabled_HAL(pGpu, pUvm)) { - while (FLD_TEST_DRF(_PFB_NISO, _ACCESS_COUNTER_NOTIFY_BUFFER_INFO, _PUSHED, _FALSE, - uvmReadAccessCntrBufferInfoReg_HAL(pGpu, pUvm))) + while (!uvmIsAccessCntrBufferPushed_HAL(pGpu, pUvm)) { if (gpuCheckTimeout(pGpu, &timeout) == NV_ERR_TIMEOUT) { @@ -319,6 +311,7 @@ uvmInitAccessCntrBuffer_GV100(OBJGPU *pGpu, OBJUVM *pUvm) return status; } + memdescSetName(pGpu, pUvmAccessCntrBufferDesc, NV_RM_SURF_NAME_ACCESS_COUNTER_BUFFER, NULL); memmgrSetMemDescPageSize_HAL(pGpu, pMemoryManager, pUvmAccessCntrBufferDesc, AT_GPU, RM_ATTR_PAGE_SIZE_4KB); status = memdescMap(pUvmAccessCntrBufferDesc, 0, diff --git a/src/nvidia/src/kernel/gpu_mgr/gpu_group.c b/src/nvidia/src/kernel/gpu_mgr/gpu_group.c index 7f1ae1e7f..d0af0c213 100644 --- a/src/nvidia/src/kernel/gpu_mgr/gpu_group.c +++ b/src/nvidia/src/kernel/gpu_mgr/gpu_group.c @@ -21,7 +21,7 @@ * DEALINGS IN THE SOFTWARE. */ -/***************************** HW State Rotuines ***************************\ +/***************************** HW State Routines ***************************\ * * * GpuGrp Object Function Definitions. * * * @@ -217,14 +217,14 @@ gpugrpCreateGlobalVASpace_IMPL gpumgrSetBcEnabledStatus(pGpu, NV_TRUE); vaspaceFlags |= VASPACE_FLAGS_ENABLE_VMM; rmStatus = vmmCreateVaspace(pVmm, vaspaceClass, 0x0, gpuMask, vaStart, - vaLimit, 0, 0, NULL, vaspaceFlags, ppGlobalVASpace); + vaLimit, 0, 0, NULL, vaspaceFlags, &pGpuGrp->pGlobalVASpace); gpumgrSetBcEnabledStatus(pGpu, bcState); if (NV_OK != rmStatus) { - *ppGlobalVASpace = NULL; + pGpuGrp->pGlobalVASpace = NULL; return rmStatus; } - pGpuGrp->pGlobalVASpace = (*ppGlobalVASpace); + *ppGlobalVASpace = pGpuGrp->pGlobalVASpace ; return rmStatus; } diff --git a/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c b/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c index 379d3cd71..5958e0aff 100644 --- a/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c +++ b/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c @@ -37,7 +37,7 @@ #include "nvlimits.h" #include "kernel/gpu/intr/intr.h" -#include "platform/platform.h" +#include "virtualization/hypervisor/hypervisor.h" #include "platform/chipset/chipset.h" #include "published/pcie_switch/pcie_switch_ref.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" @@ -96,8 +96,9 @@ _gpumgrRegisterRmCapsForGpu(OBJGPU *pGpu) { PROBEDGPU *pProbedGpu = &pGpuMgr->probedGpus[i]; - if (pProbedGpu->gpuDomainBusDevice == gpuGetDBDF(pGpu) && - pProbedGpu->gpuId != NV0000_CTRL_GPU_INVALID_ID) + if (((pProbedGpu->gpuDomainBusDevice == 0) && pGpu->bIsSOC) || + (pProbedGpu->gpuDomainBusDevice == gpuGetDBDF(pGpu) && + pProbedGpu->gpuId != NV0000_CTRL_GPU_INVALID_ID)) { if (pProbedGpu->pOsRmCaps == NULL) { @@ -254,10 +255,7 @@ _gpumgrDestroyGpu(NvU32 gpuInstance) pGpu = gpumgrGetGpu(gpuInstance); - if (pGpu != NULL) - { - objDelete(pGpu); - } + objDelete(pGpu); for (i = 0; i < pGpuMgr->numGpuHandles; i++) { @@ -270,10 +268,6 @@ _gpumgrDestroyGpu(NvU32 gpuInstance) } } - // Destroy pointers of blob data if it is created - OBJPFM *pPfm = SYS_GET_PFM(pSys); - pfmBlobDataDestroy(pPfm); - osSyncWithGpuDestroy(NV_FALSE); } @@ -714,19 +708,26 @@ gpumgrGetGpuHalFactorOfVirtual(NvBool *pIsVirtual, GPUATTACHARG *pAttachArg) *pIsVirtual = NV_FALSE; } -#define NV_PMC_BOOT_42_ARCHITECTURE_TU100 0x00000016 static NvBool _gpumgrIsRmFirmwareCapableChip(NvU32 pmcBoot42) { return (DRF_VAL(_PMC, _BOOT_42, _ARCHITECTURE, pmcBoot42) >= NV_PMC_BOOT_42_ARCHITECTURE_TU100); } -#undef NV_PMC_BOOT_42_ARCHITECTURE_TU100 -#define NV_PMC_BOOT_42_ARCHITECTURE_GH100 0x00000018 +static NvBool _gpumgrIsVgxRmFirmwareCapableChip(NvU32 pmcBoot42) +{ + return (DRF_VAL(_PMC, _BOOT_42, _ARCHITECTURE, pmcBoot42) >= NV_PMC_BOOT_42_ARCHITECTURE_GA100) && + (DRF_VAL(_PMC, _BOOT_42, _CHIP_ID, pmcBoot42) > NV_PMC_BOOT_42_CHIP_ID_GA100); +} + static NvBool _gpumgrIsRmFirmwareDefaultChip(NvU32 pmcBoot42) { return (DRF_VAL(_PMC, _BOOT_42, _ARCHITECTURE, pmcBoot42) == NV_PMC_BOOT_42_ARCHITECTURE_GH100); } -#undef NV_PMC_BOOT_42_ARCHITECTURE_GH100 + +static NvBool _gpumgrIsVgxRmFirmwareDefaultChip(NvU32 pmcBoot42) +{ + return NV_FALSE; +} NvBool gpumgrIsDeviceRmFirmwareCapable ( @@ -758,20 +759,34 @@ NvBool gpumgrIsDeviceRmFirmwareCapable 0x2236, // A10 SKU215 Pris-24 0x2237, // A10G SKU215 Pris-24 0x25B6, // A16 + 0x20F5, // A800-80 + 0x20F6, // A800-40 + + 0x26B5, // L40 + 0x26B8, // L40G + 0x26F5, // L40-CNX + 0x27B8, // L4 (both SKUs) }; NvU32 count = NV_ARRAY_ELEMENTS(defaultGspRmGpus); NvU32 i; *pbEnabledByDefault = NV_FALSE; - if (!_gpumgrIsRmFirmwareCapableChip(pmcBoot42)) + if (!hypervisorIsVgxHyper() && !_gpumgrIsRmFirmwareCapableChip(pmcBoot42)) + return NV_FALSE; + else if (hypervisorIsVgxHyper() && !_gpumgrIsVgxRmFirmwareCapableChip(pmcBoot42)) return NV_FALSE; - if (_gpumgrIsRmFirmwareDefaultChip(pmcBoot42)) + if (!hypervisorIsVgxHyper() && _gpumgrIsRmFirmwareDefaultChip(pmcBoot42)) { *pbEnabledByDefault = NV_TRUE; } - else + else if (hypervisorIsVgxHyper() && _gpumgrIsVgxRmFirmwareDefaultChip(pmcBoot42)) + { + *pbEnabledByDefault = NV_TRUE; + } + + if (!hypervisorIsVgxHyper() || RMCFG_FEATURE_PLATFORM_GSP) { for (i = 0; i < count; i++) { @@ -979,7 +994,7 @@ gpumgrAttachGpu(NvU32 gpuInstance, GPUATTACHARG *pAttachArg) OBJGPU *pGpu = NULL; NV_STATUS status; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); // create the new OBJGPU if ((status = _gpumgrCreateGpu(gpuInstance, pAttachArg)) != NV_OK) @@ -1056,6 +1071,9 @@ gpumgrAttachGpu(NvU32 gpuInstance, GPUATTACHARG *pAttachArg) // Add entry into system partition topo array gpumgrAddSystemMIGInstanceTopo(pAttachArg->nvDomainBusDeviceFunc); + if (!IS_GSP_CLIENT(pGpu)) + pGpuMgr->gpuMonolithicRmMask |= NVBIT(gpuInstance); + return status; gpumgrAttach_error_and_exit: @@ -1089,7 +1107,7 @@ gpumgrDetachGpu(NvU32 gpuInstance) OBJGPU *pGpu = gpumgrGetGpu(gpuInstance); NvBool bDelClientResourcesFromGpuMask = !pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_TIMEOUT_RECOVERY); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); // Mark for deletion the stale clients related to the GPU mask if (bDelClientResourcesFromGpuMask) @@ -1111,6 +1129,7 @@ gpumgrDetachGpu(NvU32 gpuInstance) rmapiDelPendingClients(); } + pGpuMgr->gpuMonolithicRmMask &= ~NVBIT(gpuInstance); NV_ASSERT(pGpuMgr->gpuAttachMask & NVBIT(gpuInstance)); pGpuMgr->gpuAttachMask &= ~NVBIT(gpuInstance); pGpuMgr->gpuAttachCount--; @@ -1321,6 +1340,7 @@ gpumgrSetAttachInfo(OBJGPU *pGpu, GPUATTACHARG *pAttachArg) if (pAttachArg->socDeviceArgs.specified) { NvU32 idx; + NvU32 maxIdx; // This path is taken for T234D+ SOC devices. // @@ -1331,15 +1351,18 @@ gpumgrSetAttachInfo(OBJGPU *pGpu, GPUATTACHARG *pAttachArg) // See JIRA TDS-5101 for more details. // pGpu->bIsSOC = NV_TRUE; + maxIdx = SOC_DEV_MAPPING_MAX; - for (idx = 0; idx < SOC_DEV_MAPPING_MAX; idx++) + for (idx = 0; idx < maxIdx; idx++) { pGpu->deviceMappings[idx] = pAttachArg->socDeviceArgs.deviceMapping[idx]; } pGpu->busInfo.iovaspaceId = pAttachArg->socDeviceArgs.iovaspaceId; - pGpu->busInfo.gpuPhysAddr = pGpu->deviceMappings[SOC_DEV_MAPPING_DISP].gpuNvPAddr; - pGpu->gpuDeviceMapCount = 1; + { + pGpu->busInfo.gpuPhysAddr = pGpu->deviceMappings[SOC_DEV_MAPPING_DISP].gpuNvPAddr; + pGpu->gpuDeviceMapCount = 1; + } // // TODO bug 2100708: a fake DBDF is used on SOC to opt out of some @@ -1356,7 +1379,7 @@ gpumgrSetAttachInfo(OBJGPU *pGpu, GPUATTACHARG *pAttachArg) pGpu->idInfo.PCIDeviceID = pAttachArg->socId; pGpu->idInfo.PCISubDeviceID = pAttachArg->socSubId; pGpu->busInfo.iovaspaceId = pAttachArg->iovaspaceId; - if (RMCFG_FEATURE_PLATFORM_MODS) + if (RMCFG_FEATURE_PLATFORM_MODS || RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM) { NV_ASSERT(sizeof(pGpu->deviceMappings) == sizeof(pAttachArg->socDeviceMappings)); portMemCopy(pGpu->deviceMappings, sizeof(pGpu->deviceMappings), pAttachArg->socDeviceMappings, sizeof(pGpu->deviceMappings)); @@ -1416,7 +1439,11 @@ gpumgrSetAttachInfo(OBJGPU *pGpu, GPUATTACHARG *pAttachArg) } } - gpuId = gpuGenerate32BitId(gpuGetDomain(pGpu), gpuGetBus(pGpu), gpuGetDevice(pGpu)); + // Generate GPU ID using end-point address for PCIe devices, otherwise use MMIO address + gpuId = (!RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM || !pGpu->bIsSOC) + ? gpuGenerate32BitId(gpuGetDomain(pGpu), gpuGetBus(pGpu), gpuGetDevice(pGpu)) + : gpuGenerate32BitIdFromPhysAddr(pAttachArg->devPhysAddr); + if (gpuId != NV0000_CTRL_GPU_INVALID_ID) { gpumgrSetGpuId(pGpu, gpuId); @@ -2784,17 +2811,17 @@ gpumgrGetSystemNvlinkTopo_IMPL pTopoParams->numPeers = pGpuMgr->nvlinkTopologyInfo[i].params.numPeers; pTopoParams->bSwitchConfig = pGpuMgr->nvlinkTopologyInfo[i].params.bSwitchConfig; // Ampere+ - for (idx = 0; idx < NV_CE_PCE2LCE_CONFIG__SIZE_1_MAX; idx++) + for (idx = 0; idx < NV2080_CTRL_MAX_PCES; idx++) { pTopoParams->maxPceLceMap[idx] = pGpuMgr->nvlinkTopologyInfo[i].params.maxPceLceMap[idx]; } - for (idx = 0; idx < NV_CE_GRCE_CONFIG__SIZE_1; idx++) + for (idx = 0; idx < NV2080_CTRL_MAX_GRCES; idx++) { pTopoParams->maxGrceConfig[idx] = pGpuMgr->nvlinkTopologyInfo[i].params.maxGrceConfig[idx]; } pTopoParams->maxExposeCeMask = pGpuMgr->nvlinkTopologyInfo[i].params.maxExposeCeMask; pTopoParams->maxTopoIdx = pGpuMgr->nvlinkTopologyInfo[i].params.maxTopoIdx; - for (idx = 0; idx < NV_CE_MAX_HSHUBS; idx++) + for (idx = 0; idx < NV2080_CTRL_CE_MAX_HSHUBS; idx++) { pTopoParams->pceAvailableMaskPerHshub[idx] = pGpuMgr->nvlinkTopologyInfo[i].params.pceAvailableMaskPerHshub[idx]; } @@ -2839,17 +2866,17 @@ gpumgrUpdateSystemNvlinkTopo_IMPL pGpuMgr->nvlinkTopologyInfo[i].params.bSymmetric = pTopoParams->bSymmetric; pGpuMgr->nvlinkTopologyInfo[i].params.bSwitchConfig = pTopoParams->bSwitchConfig; // Ampere + only - for (idx = 0; idx < NV_CE_PCE2LCE_CONFIG__SIZE_1_MAX; idx++) + for (idx = 0; idx < NV2080_CTRL_MAX_PCES; idx++) { pGpuMgr->nvlinkTopologyInfo[i].params.maxPceLceMap[idx] = pTopoParams->maxPceLceMap[idx]; } - for (idx = 0; idx < NV_CE_GRCE_CONFIG__SIZE_1; idx++) + for (idx = 0; idx < NV2080_CTRL_MAX_GRCES; idx++) { pGpuMgr->nvlinkTopologyInfo[i].params.maxGrceConfig[idx] = pTopoParams->maxGrceConfig[idx]; } pGpuMgr->nvlinkTopologyInfo[i].params.maxExposeCeMask = pTopoParams->maxExposeCeMask; pGpuMgr->nvlinkTopologyInfo[i].params.maxTopoIdx = pTopoParams->maxTopoIdx; - for (idx = 0; idx < NV_CE_MAX_HSHUBS; idx++) + for (idx = 0; idx < NV2080_CTRL_CE_MAX_HSHUBS; idx++) { pGpuMgr->nvlinkTopologyInfo[i].params.pceAvailableMaskPerHshub[idx] = pTopoParams->pceAvailableMaskPerHshub[idx]; } @@ -3014,7 +3041,7 @@ gpumgrAddSystemMIGInstanceTopo_IMPL { pGpuMgr->MIGTopologyInfo[i].bValid = NV_TRUE; pGpuMgr->MIGTopologyInfo[i].domainBusDevice = domainBusDevice; - + // Set MIG enablement to disabled by default pGpuMgr->MIGTopologyInfo[i].bMIGEnabled = NV_FALSE; break; @@ -3069,6 +3096,7 @@ gpumgrGetSystemMIGInstanceTopo_IMPL return NV_FALSE; } + /*! * @brief Retrieves the entry in the system partition topology save for the given GPU * ID and returns value of bMIGEnabled. @@ -3484,3 +3512,10 @@ gpumgrRemovePcieP2PCapsFromCache_IMPL portSyncMutexRelease(pGpuMgr->pcieP2PCapsInfoLock); } +NvBool gpumgrAreAllGpusInOffloadMode(void) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + + return pGpuMgr->gpuMonolithicRmMask == 0; +} diff --git a/src/nvidia/src/kernel/mem_mgr/ctx_buf_pool.c b/src/nvidia/src/kernel/mem_mgr/ctx_buf_pool.c index 4b9a656e7..b25fc57b6 100644 --- a/src/nvidia/src/kernel/mem_mgr/ctx_buf_pool.c +++ b/src/nvidia/src/kernel/mem_mgr/ctx_buf_pool.c @@ -57,6 +57,8 @@ ctxBufPoolIsSupported { MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); NvBool bCallingContextPlugin; + NvU32 gfid = GPU_GFID_PF; + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_MOVE_CTX_BUFFERS_TO_PMA)) { NV_PRINTF(LEVEL_INFO, "Ctx buffers not supported in PMA\n"); @@ -76,12 +78,12 @@ ctxBufPoolIsSupported } // - // In virtualized env, host RM we will continue to use subheap for all allocations it makes on behalf - // of guest RM. Ctx buffer allocations made by host RM for plugins(plugin channel inst block, runlists etc) - // will come from host RM's PMA(partition PMA) + // In virtualized env, host RM should use CtxBuffer for all allocations made + // on behalf of plugin or for PF usages // NV_ASSERT_OR_RETURN(vgpuIsCallingContextPlugin(pGpu, &bCallingContextPlugin) == NV_OK, NV_FALSE); - if (hypervisorIsVgxHyper() && !bCallingContextPlugin) + NV_ASSERT_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &gfid) == NV_OK, NV_FALSE); + if (hypervisorIsVgxHyper() && !bCallingContextPlugin && IS_GFID_VF(gfid)) { NV_PRINTF(LEVEL_INFO, "ctx buffers in PMA not supported for allocations host RM makes on behalf of guest\n"); return NV_FALSE; @@ -494,7 +496,7 @@ ctxBufPoolFree } else { - portMemSet(pMem, 0, pMemDesc->ActualSize); + portMemSet(pMem, 0, (pMemDesc->PageCount * RM_PAGE_SIZE)); kbusUnmapRmAperture_HAL(pGpu, pMemDesc, &pMem, NV_TRUE); } } @@ -509,7 +511,7 @@ ctxBufPoolFree * * @param[in] pGpu OBJGPU pointer * @param[in] bufId Id to identify the buffer - * @param[in] engineType NV2080 engine type + * @param[in] rmEngineType RM Engine Type * @param[out] ppCtxBufPool Pointer to context buffer pool * * @return NV_STATUS @@ -519,7 +521,7 @@ ctxBufPoolGetGlobalPool ( OBJGPU *pGpu, CTX_BUF_ID bufId, - NvU32 engineType, + RM_ENGINE_TYPE rmEngineType, CTX_BUF_POOL_INFO **ppCtxBufPool ) { @@ -527,17 +529,17 @@ ctxBufPoolGetGlobalPool CTX_BUF_POOL_INFO *pCtxBufPool = NULL; NV_ASSERT_OR_RETURN(ppCtxBufPool != NULL, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(NV2080_ENGINE_TYPE_IS_VALID(engineType), NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(RM_ENGINE_TYPE_IS_VALID(rmEngineType), NV_ERR_INVALID_ARGUMENT); switch (bufId) { case CTX_BUF_ID_RUNLIST: - pCtxBufPool = kfifoGetRunlistBufPool(pGpu, pKernelFifo, engineType); + pCtxBufPool = kfifoGetRunlistBufPool(pGpu, pKernelFifo, rmEngineType); break; case CTX_BUF_ID_GR_GLOBAL: { - KernelGraphics *pKernelGraphics = GPU_GET_KERNEL_GRAPHICS(pGpu, NV2080_ENGINE_TYPE_GR_IDX(engineType)); - NV_ASSERT_OR_RETURN(NV2080_ENGINE_TYPE_IS_GR(engineType), NV_ERR_INVALID_ARGUMENT); + KernelGraphics *pKernelGraphics = GPU_GET_KERNEL_GRAPHICS(pGpu, RM_ENGINE_TYPE_GR_IDX(rmEngineType)); + NV_ASSERT_OR_RETURN(RM_ENGINE_TYPE_IS_GR(rmEngineType), NV_ERR_INVALID_ARGUMENT); pCtxBufPool = kgraphicsGetCtxBufPool(pGpu, pKernelGraphics); break; } @@ -600,11 +602,11 @@ ctxBufPoolGetSizeAndPageSize break; case RM_ATTR_PAGE_SIZE_HUGE: retAttr = FLD_SET_DRF(OS32, _ATTR, _PAGE_SIZE, _HUGE, retAttr); - retAttr2 = FLD_SET_DRF(OS32, _ATTR2, _PAGE_SIZE_HUGE, _2MB, retAttr); + retAttr2 = FLD_SET_DRF(OS32, _ATTR2, _PAGE_SIZE_HUGE, _2MB, retAttr2); break; case RM_ATTR_PAGE_SIZE_512MB: retAttr = FLD_SET_DRF(OS32, _ATTR, _PAGE_SIZE, _HUGE, retAttr); - retAttr2 = FLD_SET_DRF(OS32, _ATTR2, _PAGE_SIZE_HUGE, _512MB, retAttr); + retAttr2 = FLD_SET_DRF(OS32, _ATTR2, _PAGE_SIZE_HUGE, _512MB, retAttr2); break; default: NV_PRINTF(LEVEL_ERROR, "unsupported page size attr\n"); diff --git a/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c b/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c index a09d174dc..0cfc56059 100644 --- a/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c +++ b/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c @@ -22,7 +22,7 @@ */ -/***************************** HW State Rotuines ***************************\ +/***************************** HW State Routines ***************************\ * * * Fabric Virtual Address Space Function Definitions. * * * @@ -31,10 +31,10 @@ #include "gpu/mmu/kern_gmmu.h" #include "mem_mgr/vaspace.h" #include "mem_mgr/fabric_vaspace.h" +#include "gpu/mem_mgr/mem_mgr.h" #include "mem_mgr/gpu_vaspace.h" #include "gpu/mem_mgr/virt_mem_allocator_common.h" #include "os/os.h" -#include "gpu/mem_mgr/mem_desc.h" #include "gpu/bus/kern_bus.h" #include "kernel/gpu/fifo/kernel_fifo.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" @@ -51,6 +51,8 @@ #include "vgpu/vgpu_events.h" #include "mem_mgr/virt_mem_mgr.h" +#include "published/ampere/ga100/dev_mmu.h" + // @@ -73,6 +75,11 @@ _fabricvaspaceBindInstBlk INST_BLK_INIT_PARAMS instblkParams; + if (!pKernelBus->flaInfo.bToggleBindPoint) + { + return NV_OK; + } + if (gvaspaceIsInUse(dynamicCast(pKernelBus->flaInfo.pFlaVAS, OBJGVASPACE))) { NV_PRINTF(LEVEL_ERROR, @@ -156,6 +163,11 @@ _fabricvaspaceUnbindInstBlk KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); INST_BLK_INIT_PARAMS instblkParams = {0}; + if (!pKernelBus->flaInfo.bToggleBindPoint) + { + return; + } + // // Check if there are any pending allocations for the fabric vaspace. // If there are pending allocations, skip restore and return NV_OK. @@ -346,10 +358,10 @@ fabricvaspaceAlloc_IMPL // // Allocate VA space of the size and alignment requested. - // RM_PAGE_SIZE_HUGE is passed since FLA->PA page size is 2MB. + // RM_PAGE_SIZE_HUGE is passed since FLA->PA page size is 2MB or 512MB. // status = vaspaceAlloc(pFabricVAS->pGVAS, size, align, rangeLo, rangeHi, - RM_PAGE_SIZE_HUGE, flags, pAddr); + RM_PAGE_SIZE_HUGE | RM_PAGE_SHIFT_512M, flags, pAddr); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "Failed to allocate vaspace\n"); @@ -359,6 +371,9 @@ fabricvaspaceAlloc_IMPL // Assert that the address returned is pageSize aligned NV_ASSERT(NV_IS_ALIGNED64(*pAddr, pageSize)); + pFabricVAS->ucFabricFreeSize -= size; + pFabricVAS->ucFabricInUseSize += size; + return NV_OK; failed: @@ -456,6 +471,11 @@ fabricvaspaceAllocNonContiguous_IMPL (*ppAddr)[0] = addr; *pNumAddr = 1; } + else if (flags.bForceContig) + { + NV_PRINTF(LEVEL_ERROR, "Failed to allocate contig vaspace\n"); + goto failed; + } } // @@ -485,6 +505,9 @@ fabricvaspaceAllocNonContiguous_IMPL } } + pFabricVAS->ucFabricFreeSize -= size; + pFabricVAS->ucFabricInUseSize += size; + return NV_OK; failed: @@ -507,10 +530,15 @@ fabricvaspaceFree_IMPL OBJVASPACE *pVAS = staticCast(pFabricVAS, OBJVASPACE); OBJGPU *pGpu = gpumgrGetGpu(gpumgrGetDefaultPrimaryGpu(pVAS->gpuMask)); KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + NvU64 blockSize; + NvBool bUcFla; NV_ASSERT_OR_RETURN(pFabricVAS->pGVAS != NULL, NV_ERR_OBJECT_NOT_FOUND); - NV_ASSERT(vaspaceFree(pFabricVAS->pGVAS, vAddr) == NV_OK); + bUcFla = (vAddr >= fabricvaspaceGetUCFlaStart(pFabricVAS) && + vAddr < fabricvaspaceGetUCFlaLimit(pFabricVAS)); + + NV_ASSERT(vaspaceFreeV2(pFabricVAS->pGVAS, vAddr, &blockSize) == NV_OK); kbusFlush_HAL(pGpu, pKernelBus, (BUS_FLUSH_VIDEO_MEMORY | BUS_FLUSH_SYSTEM_MEMORY | @@ -520,6 +548,12 @@ fabricvaspaceFree_IMPL _fabricvaspaceUnbindInstBlk(pFabricVAS); + if (bUcFla) + { + pFabricVAS->ucFabricFreeSize += blockSize; + pFabricVAS->ucFabricInUseSize -= blockSize; + } + return NV_OK; } @@ -606,8 +640,8 @@ fabricvaspaceGetFreeHeap_IMPL NV_ASSERT_OR_RETURN(pFabricVAS->pGVAS != NULL, NV_ERR_OBJECT_NOT_FOUND); NV_ASSERT_OR_RETURN(freeSize != NULL, NV_ERR_INVALID_ARGUMENT); - return gvaspaceGetFreeHeap(dynamicCast(pFabricVAS->pGVAS, OBJGVASPACE), - freeSize); + *freeSize = pFabricVAS->ucFabricFreeSize; + return NV_OK; } void @@ -622,15 +656,24 @@ fabricvaspaceBatchFree_IMPL OBJVASPACE *pVAS = staticCast(pFabricVAS, OBJVASPACE); OBJGPU *pGpu = gpumgrGetGpu(gpumgrGetDefaultPrimaryGpu(pVAS->gpuMask)); KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); - + NvU64 totalFreeSize = 0; + NvU64 freeSize; NvU32 count = 0; NvU32 idx = 0; + NvBool bUcFla; + for (count = 0; count < numAddr; count++) { - NV_ASSERT(vaspaceFree(pFabricVAS->pGVAS, pAddr[idx]) == NV_OK); + bUcFla = (pAddr[idx] >= fabricvaspaceGetUCFlaStart(pFabricVAS) && + pAddr[idx] < fabricvaspaceGetUCFlaLimit(pFabricVAS)); + + NV_ASSERT(vaspaceFreeV2(pFabricVAS->pGVAS, pAddr[idx], &freeSize) == NV_OK); idx += stride; + + if (bUcFla) + totalFreeSize += freeSize; } kbusFlush_HAL(pGpu, pKernelBus, (BUS_FLUSH_VIDEO_MEMORY | @@ -640,6 +683,9 @@ fabricvaspaceBatchFree_IMPL fabricvaspaceInvalidateTlb(pFabricVAS, pGpu, PTE_DOWNGRADE); _fabricvaspaceUnbindInstBlk(pFabricVAS); + + pFabricVAS->ucFabricFreeSize += totalFreeSize; + pFabricVAS->ucFabricInUseSize -= totalFreeSize; } void @@ -683,8 +729,8 @@ fabricvaspaceGetGpaMemdesc_IMPL RmPhysAddr *pteArray = memdescGetPteArray(pRootMemDesc, AT_GPU); // Check if pteArray[0] is within the VAS range for the mapping GPU. - if ((pteArray[0] < vaspaceGetVaStart(staticCast(pFabricVAS, OBJVASPACE))) || - (pteArray[0] > vaspaceGetVaLimit(staticCast(pFabricVAS, OBJVASPACE)))) + if ((pteArray[0] < fabricvaspaceGetUCFlaStart(pFabricVAS)) || + (pteArray[0] > fabricvaspaceGetUCFlaLimit(pFabricVAS))) { *ppAdjustedMemdesc = pFabricMemdesc; return NV_OK; @@ -787,3 +833,385 @@ fabricvaspaceVaToGpaMapInsert_IMPL return NV_OK; } + +NV_STATUS +fabricvaspaceAllocMulticast_IMPL +( + FABRIC_VASPACE *pFabricVAS, + NvU64 pageSize, + NvU64 alignment, + VAS_ALLOC_FLAGS flags, + NvU64 base, + NvU64 size +) +{ + NvU64 rangeLo; + NvU64 rangeHi; + NvU64 addr = 0; + NV_STATUS status; + + NV_ASSERT_OR_RETURN(pFabricVAS->pGVAS != NULL, NV_ERR_OBJECT_NOT_FOUND); + NV_ASSERT_OR_RETURN(pageSize >= RM_PAGE_SIZE_HUGE, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(alignment != 0, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(size != 0, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(NV_IS_ALIGNED64(alignment, pageSize), NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(NV_IS_ALIGNED64(base, pageSize), NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(NV_IS_ALIGNED64(size, pageSize), NV_ERR_INVALID_ARGUMENT); + + rangeLo = base; + rangeHi = base + size - 1; + + status = vaspaceAlloc(pFabricVAS->pGVAS, size, alignment, rangeLo, + rangeHi, pageSize, flags, &addr); + + NV_ASSERT(addr == base); + + return status; +} + +static NV_STATUS +_fabricVaspaceValidateMapAttrs +( + NvU64 fabricOffset, + NvU64 fabricAllocSize, + NvU32 fabricPageSize, + NvU64 physMapOffset, + NvU64 physMapLength, + NvU64 physAllocSize, + NvU32 physPageSize +) +{ + // Fabric mem offset should be at least phys page size aligned. + if (!NV_IS_ALIGNED64(fabricOffset, physPageSize) || + (fabricOffset >= fabricAllocSize)) + { + NV_PRINTF(LEVEL_ERROR, + "Invalid offset passed for the fabric handle\n"); + + return NV_ERR_INVALID_OFFSET; + } + + if (!NV_IS_ALIGNED64(physMapOffset, physPageSize) || + (physMapOffset >= physAllocSize)) + { + NV_PRINTF(LEVEL_ERROR, + "Invalid offset passed for the physmem handle\n"); + + return NV_ERR_INVALID_OFFSET; + } + + if ((physMapLength == 0) || + (!NV_IS_ALIGNED64(physMapLength, physPageSize)) || + (physMapLength > (physAllocSize - physMapOffset)) || + (physMapLength > (fabricAllocSize - fabricOffset))) + { + NV_PRINTF(LEVEL_ERROR, + "Invalid map length passed for the physmem handle\n"); + + return NV_ERR_INVALID_ARGUMENT; + } + + return NV_OK; +} + +typedef struct FABRIC_VASPACE_MAPPING_REGION +{ + NvU64 offset; + NvU64 length; +} FABRIC_VASPACE_MAPPING_REGION; + +// +// In worst case, we can have three regions to map. Two partially filled fabric +// pages and one (or more) fully filled fabric page(s). +// +#define FABRIC_VASPACE_MAPPING_REGIONS_MAX 3 + +typedef struct FABRIC_VASPACE_MAPPING_REGIONS +{ + FABRIC_VASPACE_MAPPING_REGION r[FABRIC_VASPACE_MAPPING_REGIONS_MAX]; +} FABRIC_VASPACE_MAPPING_REGIONS; + +static void +_fabricvaspaceGetMappingRegions +( + NvU64 fabricOffset, + NvU64 fabricPageSize, + NvU64 physMapLength, + FABRIC_VASPACE_MAPPING_REGIONS *pRegions, + NvU32 *pNumRegions +) +{ + NvU64 fabricOffsetAligned = NV_ALIGN_UP64(fabricOffset, fabricPageSize); + NvU64 mapLengthAligned = NV_ALIGN_DOWN64(physMapLength, fabricPageSize); + + *pNumRegions = 0; + + if ((fabricOffset < fabricOffsetAligned) && + (physMapLength >= (fabricOffsetAligned - fabricOffset))) + { + pRegions->r[*pNumRegions].offset = fabricOffset; + pRegions->r[*pNumRegions].length = fabricOffsetAligned - fabricOffset; + + fabricOffset += pRegions->r[*pNumRegions].length; + physMapLength -= pRegions->r[*pNumRegions].length; + mapLengthAligned = NV_ALIGN_DOWN64(physMapLength, fabricPageSize); + + (*pNumRegions)++; + } + + if (physMapLength == 0) + return; + + if ((fabricOffset == fabricOffsetAligned) && + (mapLengthAligned >= fabricPageSize)) + { + pRegions->r[*pNumRegions].offset = fabricOffset; + pRegions->r[*pNumRegions].length = mapLengthAligned; + + fabricOffset += pRegions->r[*pNumRegions].length; + physMapLength -= pRegions->r[*pNumRegions].length; + + (*pNumRegions)++; + } + + if (physMapLength == 0) + return; + + pRegions->r[*pNumRegions].offset = fabricOffset; + pRegions->r[*pNumRegions].length = physMapLength; + + (*pNumRegions)++; +} + +void +fabricvaspaceUnmapPhysMemdesc_IMPL +( + FABRIC_VASPACE *pFabricVAS, + MEMORY_DESCRIPTOR *pFabricMemDesc, + NvU64 fabricOffset, + MEMORY_DESCRIPTOR *pPhysMemDesc, + NvU64 physMapLength +) +{ + OBJGPU *pGpu = pPhysMemDesc->pGpu; + NvU32 fabricPageCount; + NvU64 fabricAddr; + NvU64 fabricPageSize; + NvU32 i, j; + NvU64 mapLength; + FABRIC_VASPACE_MAPPING_REGIONS regions; + NvU32 numRegions; + + fabricPageSize = memdescGetPageSize(pFabricMemDesc, AT_GPU); + + NV_ASSERT_OR_RETURN_VOID(dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE) == \ + pFabricVAS); + + _fabricvaspaceGetMappingRegions(fabricOffset, fabricPageSize, physMapLength, + ®ions, &numRegions); + NV_ASSERT_OR_RETURN_VOID(numRegions != 0); + + for (i = 0; i < numRegions; i++) + { + fabricPageCount = ((memdescGetPteArraySize(pFabricMemDesc, AT_GPU) == 1) || + (regions.r[i].length < fabricPageSize)) ? \ + 1 : (regions.r[i].length / fabricPageSize); + mapLength = (fabricPageCount == 1) ? regions.r[i].length : fabricPageSize; + fabricOffset = regions.r[i].offset; + + for (j = 0; j < fabricPageCount; j++) + { + if (fabricPageCount == 1) + { + fabricAddr = pFabricMemDesc->_pteArray[0] + fabricOffset; + } + else + { + fabricAddr = pFabricMemDesc->_pteArray[fabricOffset / pFabricMemDesc->pageArrayGranularity]; + } + + vaspaceUnmap(pFabricVAS->pGVAS, pPhysMemDesc->pGpu, fabricAddr, \ + fabricAddr + mapLength - 1); + + fabricOffset = fabricOffset + mapLength; + } + } + + fabricvaspaceInvalidateTlb(pFabricVAS, pPhysMemDesc->pGpu, PTE_DOWNGRADE); +} + +NV_STATUS +fabricvaspaceMapPhysMemdesc_IMPL +( + FABRIC_VASPACE *pFabricVAS, + MEMORY_DESCRIPTOR *pFabricMemDesc, + NvU64 fabricOffset, + MEMORY_DESCRIPTOR *pPhysMemDesc, + NvU64 physOffset, + NvU64 physMapLength, + NvU32 flags +) +{ + OBJGPU *pGpu = pPhysMemDesc->pGpu; + VirtMemAllocator *pDma = GPU_GET_DMA(pGpu); + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + NV_STATUS status; + DMA_PAGE_ARRAY pageArray; + NvU32 kind; + COMPR_INFO comprInfo; + NvU32 mapFlags = DMA_UPDATE_VASPACE_FLAGS_UPDATE_ALL | + DMA_UPDATE_VASPACE_FLAGS_SKIP_4K_PTE_CHECK; + NvU32 fabricPageCount; + NvU64 fabricAddr; + NvU32 physPageSize; + NvU64 fabricPageSize; + NvU64 physAddr; + NvU32 i, j; + NvU64 mapLength; + NvBool bReadOnly = !!(flags & FABRIC_VASPACE_MAP_FLAGS_READ_ONLY); + FABRIC_VASPACE_MAPPING_REGIONS regions; + NvU32 numRegions; + MEMORY_DESCRIPTOR *pTempMemdesc; + + NV_ASSERT_OR_RETURN(pFabricMemDesc != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pPhysMemDesc != NULL, NV_ERR_INVALID_ARGUMENT); + + mapFlags |= bReadOnly ? DMA_UPDATE_VASPACE_FLAGS_READ_ONLY : 0; + + NV_ASSERT_OR_RETURN(dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE) == pFabricVAS, + NV_ERR_INVALID_ARGUMENT); + + physPageSize = memdescGetPageSize(pPhysMemDesc, AT_GPU); + fabricPageSize = memdescGetPageSize(pFabricMemDesc, AT_GPU); + + status = _fabricVaspaceValidateMapAttrs(fabricOffset, + memdescGetSize(pFabricMemDesc), + fabricPageSize, + physOffset, + physMapLength, + memdescGetSize(pPhysMemDesc), + physPageSize); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, status); + + if (pFabricVAS->bRpcAlloc) + return NV_OK; + + status = memmgrGetKindComprFromMemDesc(pMemoryManager, pPhysMemDesc, + physOffset, &kind, &comprInfo); + NV_ASSERT_OK_OR_RETURN(status); + + _fabricvaspaceGetMappingRegions(fabricOffset, fabricPageSize, physMapLength, + ®ions, &numRegions); + NV_ASSERT_OR_RETURN(numRegions != 0, NV_ERR_INVALID_ARGUMENT); + + for (i = 0; i < numRegions; i++) + { + fabricPageCount = ((memdescGetPteArraySize(pFabricMemDesc, AT_GPU) == 1) || + (regions.r[i].length < fabricPageSize)) ? \ + 1 : (regions.r[i].length / fabricPageSize); + mapLength = (fabricPageCount == 1) ? regions.r[i].length : fabricPageSize; + fabricOffset = regions.r[i].offset; + + portMemSet(&pageArray, 0, sizeof(DMA_PAGE_ARRAY)); + pageArray.count = (memdescGetPteArraySize(pPhysMemDesc, AT_GPU) == 1) ? \ + 1 : (mapLength / pPhysMemDesc->pageArrayGranularity); + + for (j = 0; j < fabricPageCount; j++) + { + if (fabricPageCount == 1) + { + fabricAddr = pFabricMemDesc->_pteArray[0] + fabricOffset; + } + else + { + fabricAddr = pFabricMemDesc->_pteArray[fabricOffset / pFabricMemDesc->pageArrayGranularity]; + } + + if (pageArray.count == 1) + { + physAddr = pPhysMemDesc->_pteArray[0] + physOffset; + pageArray.pData = &physAddr; + } + else + { + pageArray.pData = &pPhysMemDesc->_pteArray[physOffset / pPhysMemDesc->pageArrayGranularity]; + } + + // + // When physPageSize is greater than fabricPageSize, to avoid fabric + // VAs getting aligned using physPageSize by dmaUpdateVASpace_HAL, + // create a tempMemdesc and override its pageSize. + // + if (fabricPageSize < physPageSize) + { + status = memdescCreateSubMem(&pTempMemdesc, pPhysMemDesc, + pPhysMemDesc->pGpu, + physOffset, mapLength); + if (status != NV_OK) + goto fail; + + memdescSetPageSize(pTempMemdesc, AT_GPU, fabricPageSize); + } + else + { + pTempMemdesc = pPhysMemDesc; + } + + // Map the memory fabric object at the given physical memory offset. + status = dmaUpdateVASpace_HAL(pGpu, pDma, pFabricVAS->pGVAS, pTempMemdesc, + NULL, fabricAddr, fabricAddr + mapLength - 1, + mapFlags, &pageArray, 0, &comprInfo, 0, + NV_MMU_PTE_VALID_TRUE, + NV_MMU_PTE_APERTURE_VIDEO_MEMORY, + BUS_INVALID_PEER, NVLINK_INVALID_FABRIC_ADDR, + DMA_DEFER_TLB_INVALIDATE, NV_FALSE, fabricPageSize); + + if (pTempMemdesc != pPhysMemDesc) + memdescDestroy(pTempMemdesc); + + if (status != NV_OK) + goto fail; + + physOffset = physOffset + mapLength; + fabricOffset = fabricOffset + mapLength; + } + } + + fabricvaspaceInvalidateTlb(pFabricVAS, pPhysMemDesc->pGpu, PTE_UPGRADE); + + return NV_OK; + +fail: + for (j = 0; j < i; j++) + fabricvaspaceUnmapPhysMemdesc(pFabricVAS, pFabricMemDesc, + regions.r[j].offset, pPhysMemDesc, + regions.r[j].length); + + return status; +} + +NV_STATUS +fabricvaspaceInitUCRange_IMPL +( + FABRIC_VASPACE *pFabricVAS, + OBJGPU *pGpu, + NvU64 fabricBase, + NvU64 fabricSize +) +{ + if (fabricvaspaceGetUCFlaLimit(pFabricVAS) != 0) + return NV_ERR_IN_USE; + + if (fabricSize != 0) + { + NV_PRINTF(LEVEL_INFO, "Setting UC Base: %llx, size: %llx \n", + fabricBase, fabricSize); + pFabricVAS->ucFabricBase = fabricBase; + pFabricVAS->ucFabricLimit = fabricBase + fabricSize - 1; + pFabricVAS->ucFabricInUseSize = 0; + pFabricVAS->ucFabricFreeSize = fabricSize; + } + + return NV_OK; +} + diff --git a/src/nvidia/src/kernel/mem_mgr/fla_mem.c b/src/nvidia/src/kernel/mem_mgr/fla_mem.c index 16802a344..c7cb8f062 100644 --- a/src/nvidia/src/kernel/mem_mgr/fla_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/fla_mem.c @@ -368,10 +368,7 @@ delete_memory: memDestructCommon(pMemory); done_fbmem: - if (pMemDesc != NULL) - { - memdescDestroy(pMemDesc); - } + memdescDestroy(pMemDesc); // free the duped memory if (!bLoopback && pAllocParams->hExportHandle) diff --git a/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c b/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c index 542f51ca6..56d26245a 100644 --- a/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c +++ b/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c @@ -22,7 +22,7 @@ */ -/***************************** HW State Rotuines ***************************\ +/***************************** HW State Routines ***************************\ * * * GPU Virtual Address Space Function Definitions. * * * @@ -206,6 +206,14 @@ _gvaspaceForceFreePageLevelInstances GVAS_GPU_STATE *pGpuState ); +static NV_STATUS +_gvaspacePopulatePDEentries +( + OBJGVASPACE *pGVAS, + OBJGPU *pGpu, + NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS *pPdeCopyParams +); + static NV_STATUS _gvaspaceBar1VaSpaceConstructFW ( @@ -399,8 +407,8 @@ done: return status; } -static NV_STATUS -_gvaspaceReserveSplitVaSpace +NV_STATUS +gvaspaceReserveSplitVaSpace_IMPL ( OBJGVASPACE *pGVAS, OBJGPU *pGpu @@ -633,7 +641,7 @@ gvaspaceConstruct__IMPL NV_ASSERT_OK_OR_GOTO(status, vgpuIsCallingContextPlugin(pGpu, &bCallingContextPlugin), catch); if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) || !bCallingContextPlugin) { - status = _gvaspaceReserveSplitVaSpace(pGVAS, pGpu); + status = gvaspaceReserveSplitVaSpace(pGVAS, pGpu); NV_ASSERT_OR_GOTO(NV_OK == status, catch); } } @@ -720,7 +728,7 @@ gvaspaceConstruct__IMPL // // An alternative approach is to pick the partial PDEs dynamically, // for example the first N PDEs used. - // However this signicantly complicates VA heap allocation, + // However this significantly complicates VA heap allocation, // especially for grow down requests (think about it). // The original RM VAS code used this approach, but it was // proved to cause stuttering in allocation-heavy apps due to the @@ -1760,14 +1768,14 @@ catch: return status; } -NV_STATUS -gvaspaceFree_IMPL +static NV_STATUS +_gvaspaceInternalFree ( OBJGVASPACE *pGVAS, - NvU64 vAddr + NvU64 vAddr, + EMEMBLOCK *pMemBlock ) { - PEMEMBLOCK pMemBlock; PGVAS_BLOCK pVASBlock; GVAS_MAPPING *pMapNode; OBJVASPACE *pVAS = staticCast(pGVAS, OBJVASPACE); @@ -1779,8 +1787,6 @@ gvaspaceFree_IMPL return NV_ERR_INVALID_STATE; } - pMemBlock = pGVAS->pHeap->eheapGetBlock(pGVAS->pHeap, vAddr, 0); - NV_ASSERT_OR_RETURN(NULL != pMemBlock, NV_ERR_INVALID_ARGUMENT); pVASBlock = (PGVAS_BLOCK)pMemBlock->pData; if (pMemBlock->refCount > 1) @@ -1865,6 +1871,19 @@ gvaspaceFree_IMPL return NV_OK; } +NV_STATUS +gvaspaceFree_IMPL +( + OBJGVASPACE *pGVAS, + NvU64 vAddr +) +{ + EMEMBLOCK *pMemBlock = pGVAS->pHeap->eheapGetBlock(pGVAS->pHeap, vAddr, 0); + NV_ASSERT_OR_RETURN(NULL != pMemBlock, NV_ERR_INVALID_ARGUMENT); + + return _gvaspaceInternalFree(pGVAS, vAddr, pMemBlock); +} + NV_STATUS gvaspaceApplyDefaultAlignment_IMPL ( @@ -3307,11 +3326,8 @@ catch: vaInternalLo, vaInternalHi); } } - if (NULL != pRootMemNew) - { - memdescDestroy(pRootMemNew); - pRootMemNew = NULL; - } + memdescDestroy(pRootMemNew); + pRootMemNew = NULL; } // Release MMU walker user context. gvaspaceWalkUserCtxRelease(pGVAS, &userCtx); @@ -3345,11 +3361,8 @@ gvaspaceExternalRootDirRevoke_IMPL // get the PDB pExternalPDB = vaspaceGetPageDirBase(pVAS, pGpu); - if (NULL != pExternalPDB) - { - memdescDestroy(pExternalPDB); - pExternalPDB = NULL; - } + memdescDestroy(pExternalPDB); + pExternalPDB = NULL; status = _gvaspaceSetExternalPageDirBase(pGVAS, pGpu, pExternalPDB); return status; } @@ -4075,17 +4088,19 @@ gvaspaceCopyServerRmReservedPdesToServerRm_IMPL return NV_OK; } + NvHandle hClient; + NvBool bFreeNeeded = NV_FALSE; + NvHandle hDevice; + NvHandle hVASpace; + POBJGPUGRP pGpuGrp = gpumgrGetGpuGrpFromGpu(pGpu); + if (NULL != pContext) { - NvHandle hClient = pContext->pClient->hClient; + NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS pdeCopyParams; RsResourceRef *pResourceRef = pContext->pResourceRef; RsResourceRef *pDeviceRef = NULL; - NvBool bFreeNeeded = NV_FALSE; - NvHandle hDevice; - NvHandle hVASpace; - NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS pdeInfo; - NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS pdeCopyParams; - NvU32 i; + + hClient = pContext->pClient->hClient; if (pResourceRef->internalClassId == classId(VaSpaceApi)) { @@ -4137,32 +4152,9 @@ gvaspaceCopyServerRmReservedPdesToServerRm_IMPL bFreeNeeded = NV_TRUE; } - portMemSet(&pdeInfo, 0, sizeof(NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS)); - portMemSet(&pdeCopyParams, 0, sizeof(NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS)); - - // Populate the input params. - pdeInfo.pageSize = NVBIT32(GMMU_PD1_VADDR_BIT_LO); - pdeInfo.virtAddress = pGVAS->vaStartServerRMOwned; - - // Fetch the details of the PDEs backing server RM's VA range. - status = gvaspaceGetPageLevelInfo(pGVAS, pGpu, &pdeInfo); + status = _gvaspacePopulatePDEentries(pGVAS, pGpu, &pdeCopyParams); NV_ASSERT_OR_GOTO(NV_OK == status, done); - // Populate the input params. - for (i = 0; i < pdeInfo.numLevels; i++) - { - pdeCopyParams.levels[i].pageShift = pdeInfo.levels[i].levelFmt.virtAddrBitLo; - pdeCopyParams.levels[i].physAddress = pdeInfo.levels[i].physAddress; - pdeCopyParams.levels[i].aperture = pdeInfo.levels[i].aperture; - pdeCopyParams.levels[i].size = pdeInfo.levels[i].size; - } - - pdeCopyParams.numLevelsToCopy = pdeInfo.numLevels; - pdeCopyParams.subDeviceId = gpumgrGetSubDeviceInstanceFromGpu(pGpu); - pdeCopyParams.pageSize = NVBIT32(GMMU_PD1_VADDR_BIT_LO); - pdeCopyParams.virtAddrLo = pGVAS->vaStartServerRMOwned; - pdeCopyParams.virtAddrHi = pdeCopyParams.virtAddrLo + - SPLIT_VAS_SERVER_RM_MANAGED_VA_SIZE - 1; // // RPC the details of these reserved PDEs to server RM so that server RM can // mirror these PDEs in its mmu walker state. Any lower level PDEs/PTEs @@ -4180,6 +4172,22 @@ done: NV_ASSERT_OR_RETURN(NV_OK == tmpStatus, tmpStatus); } } + //check to ensure server reserved PDEs are copied when global va space is created + else if(!IS_VIRTUAL(pGpu) && pGpuGrp->pGlobalVASpace == dynamicCast(pGVAS, OBJVASPACE)) + { + NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS globalCopyParams; + + NV_ASSERT_OK_OR_RETURN(_gvaspacePopulatePDEentries(pGVAS, pGpu, &globalCopyParams.PdeCopyParams)); + + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER, + &globalCopyParams, + sizeof(NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS))); + } return status; } @@ -4412,18 +4420,31 @@ vaspaceapiCtrlCmdVaspaceCopyServerReservedPdes_IMPL ) { OBJGVASPACE *pGVAS = NULL; - OBJVASPACE *pVAS = NULL; OBJGPU *pGpu = NULL; + + NV_ASSERT_OK_OR_RETURN( + _gvaspaceControl_Prolog(pVaspaceApi, pCopyServerReservedPdesParams->hSubDevice, + pCopyServerReservedPdesParams->subDeviceId, &pGVAS, &pGpu)); + + return gvaspaceCopyServerReservedPdes(pGVAS, pGpu, pCopyServerReservedPdesParams); +} + +NV_STATUS +gvaspaceCopyServerReservedPdes_IMPL +( + OBJGVASPACE *pGVAS, + OBJGPU *pGpu, + NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS *pCopyServerReservedPdesParams +) +{ + + OBJVASPACE *pVAS = NULL; KernelGmmu *pKernelGmmu = NULL; NV_STATUS status = NV_OK; MMU_WALK_USER_CTX userCtx = {0}; GVAS_GPU_STATE *pGpuState; NvS32 i; - NV_ASSERT_OK_OR_RETURN( - _gvaspaceControl_Prolog(pVaspaceApi, pCopyServerReservedPdesParams->hSubDevice, - pCopyServerReservedPdesParams->subDeviceId, &pGVAS, &pGpu)); - pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); pVAS = staticCast(pGVAS, OBJVASPACE); @@ -5109,6 +5130,49 @@ _gvaspaceForceFreePageLevelInstances gvaspaceWalkUserCtxRelease(pGVAS, &userCtx); } +static NV_STATUS +_gvaspacePopulatePDEentries +( + OBJGVASPACE *pGVAS, + OBJGPU *pGpu, + NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS *pPdeCopyParams +) +{ + NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS pdeInfo; + NvU32 i; + NV_STATUS status = NV_OK; + + portMemSet(&pdeInfo, 0, sizeof(NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS)); + portMemSet(pPdeCopyParams, 0, sizeof(NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS)); + + // Populate the input params. + pdeInfo.pageSize = NVBIT32(GMMU_PD1_VADDR_BIT_LO); + pdeInfo.virtAddress = pGVAS->vaStartServerRMOwned; + + // Fetch the details of the PDEs backing server RM's VA range. + status = gvaspaceGetPageLevelInfo(pGVAS, pGpu, &pdeInfo); + NV_ASSERT_OR_RETURN(NV_OK == status, status); + + // Populate the input params. + for (i = 0; i < pdeInfo.numLevels; i++) + { + pPdeCopyParams->levels[i].pageShift = pdeInfo.levels[i].levelFmt.virtAddrBitLo; + pPdeCopyParams->levels[i].physAddress = pdeInfo.levels[i].physAddress; + pPdeCopyParams->levels[i].aperture = pdeInfo.levels[i].aperture; + pPdeCopyParams->levels[i].size = pdeInfo.levels[i].size; + } + + pPdeCopyParams->numLevelsToCopy = pdeInfo.numLevels; + pPdeCopyParams->subDeviceId = gpumgrGetSubDeviceInstanceFromGpu(pGpu); + pPdeCopyParams->pageSize = NVBIT32(GMMU_PD1_VADDR_BIT_LO); + pPdeCopyParams->virtAddrLo = pGVAS->vaStartServerRMOwned; + pPdeCopyParams->virtAddrHi = pPdeCopyParams->virtAddrLo + + SPLIT_VAS_SERVER_RM_MANAGED_VA_SIZE - 1; + + return status; +} + + /*! * @brief Reserve mempool for page levels. * @@ -5244,3 +5308,18 @@ gvaspaceIsInUse_IMPL return (totalSize != freeSize); } + +NV_STATUS +gvaspaceFreeV2_IMPL +( + OBJGVASPACE *pGVAS, + NvU64 vAddr, + NvU64 *pSize +) +{ + EMEMBLOCK *pMemBlock = pGVAS->pHeap->eheapGetBlock(pGVAS->pHeap, vAddr, 0); + NV_ASSERT_OR_RETURN(NULL != pMemBlock, NV_ERR_INVALID_ARGUMENT); + + *pSize = pMemBlock->end - pMemBlock->begin +1; + return _gvaspaceInternalFree(pGVAS, vAddr, pMemBlock); +} diff --git a/src/nvidia/src/kernel/mem_mgr/io_vaspace.c b/src/nvidia/src/kernel/mem_mgr/io_vaspace.c index bf38bbbc2..8b8e1c543 100644 --- a/src/nvidia/src/kernel/mem_mgr/io_vaspace.c +++ b/src/nvidia/src/kernel/mem_mgr/io_vaspace.c @@ -22,7 +22,7 @@ */ -/***************************** HW State Rotuines ***************************\ +/***************************** HW State Routines ***************************\ * * * IOMMU Virtual Address Space Function Definitions. * * * @@ -208,7 +208,7 @@ iovaspaceGetVaLimit_IMPL(OBJIOVASPACE *pIOVAS) return NVBIT64(32) - 1; } -#if (RMCFG_FEATURE_PLATFORM_UNIX || RMCFG_FEATURE_PLATFORM_MODS) && !NVCPU_IS_ARM +#if (RMCFG_FEATURE_PLATFORM_UNIX || RMCFG_FEATURE_MODS_FEATURES) && !NVCPU_IS_ARM static PIOVAMAPPING _iovaspaceCreateMappingDataFromMemDesc ( @@ -601,4 +601,4 @@ void iovaMappingDestroy(PIOVAMAPPING pIovaMapping) iovaspaceDestroyMapping(pIOVAS, pIovaMapping); } -#endif // (RMCFG_FEATURE_PLATFORM_UNIX || RMCFG_FEATURE_PLATFORM_MODS) && !NVCPU_IS_ARM +#endif // (RMCFG_FEATURE_PLATFORM_UNIX || RMCFG_FEATURE_MODS_FEATURES) && !NVCPU_IS_ARM diff --git a/src/nvidia/src/kernel/mem_mgr/mem.c b/src/nvidia/src/kernel/mem_mgr/mem.c index 0b9def1bb..582befdcc 100644 --- a/src/nvidia/src/kernel/mem_mgr/mem.c +++ b/src/nvidia/src/kernel/mem_mgr/mem.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -69,7 +69,7 @@ memConstruct_IMPL pMemory->pDevice = dynamicCast(pGrandParentRef->pResource, Device); if (pMemory->pDevice == NULL) - return NV_ERR_INVALID_OBJECT_HANDLE; + return NV_ERR_INVALID_OBJECT_HANDLE; } // If child of device, we have a pGpu @@ -78,6 +78,8 @@ memConstruct_IMPL // NOTE: pGpu and pDevice be NULL for NoDeviceMemory pMemory->pGpu = CliGetGpuFromContext(pResourceRef, &pMemory->bBcResource); + NV_ASSERT_OR_RETURN(pMemory->pGpu != NULL, NV_ERR_INVALID_ARGUMENT); + // Set thread BC state gpuSetThreadBcState(pMemory->pGpu, pMemory->bBcResource); } @@ -254,7 +256,7 @@ memCreateKernelMapping_IMPL { NV_STATUS status; - NV_CHECK_OK_OR_RETURN(LEVEL_INFO, memIsReady(pMemory)); + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, memIsReady(pMemory, NV_FALSE)); if (pMemory->KernelVAddr == NvP64_NULL) { @@ -476,7 +478,7 @@ memConstructCommon_IMPL done: if (status != NV_OK) { - if (pMemory != NULL && pMemory->pHwResource != NULL) + if (pMemory->pHwResource != NULL) { portMemFree(pMemory->pHwResource); } @@ -489,6 +491,21 @@ done: return status; } +static NvBool +_memCheckHostVgpuDeviceExists +( + OBJGPU *pGpu +) +{ + NV_STATUS status; + + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice = NULL; + + NV_ASSERT_OK_OR_ELSE(status, vgpuGetCallingContextKernelHostVgpuDevice(pGpu, &pKernelHostVgpuDevice), return NV_FALSE); + + return (pKernelHostVgpuDevice != NULL); +} + static void _memDestructCommonWithDevice ( @@ -542,7 +559,7 @@ _memDestructCommonWithDevice if (--pMemory->pHwResource->refCount == 0) { MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); - NvBool bHostVgpuDeviceExists = NV_FALSE; + NvBool bHostVgpuDeviceExists = _memCheckHostVgpuDeviceExists(pGpu); if ((pMemory->categoryClassId == NV01_MEMORY_SYSTEM && memmgrComprSupported(pMemoryManager, ADDR_SYSMEM)) || (bHostVgpuDeviceExists && (pMemory->pHwResource->isGuestAllocated))) @@ -693,7 +710,7 @@ memGetByHandle_IMPL if (*ppMemory == NULL) return NV_ERR_INVALID_OBJECT_HANDLE; - NV_CHECK_OK_OR_RETURN(LEVEL_INFO, memIsReady(*ppMemory)); + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, memIsReady(*ppMemory, NV_FALSE)); return NV_OK; } @@ -721,7 +738,8 @@ memGetByHandleAndGroupedGpu_IMPL NV_STATUS memIsReady_IMPL ( - Memory *pMemory + Memory *pMemory, + NvBool bCopyConstructorContext ) { if (pMemory->pMemDesc == NULL) @@ -740,7 +758,7 @@ memControl_IMPL { RmCtrlParams *pRmCtrlParams = pParams->pLegacyParams; - NV_CHECK_OK_OR_RETURN(LEVEL_INFO, memIsReady(pMemory)); + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, memIsReady(pMemory, NV_FALSE)); if (!pMemory->pGpu) return NV_ERR_INVALID_OBJECT_PARENT; @@ -787,7 +805,7 @@ memCopyConstruct_IMPL NV_ASSERT_OR_RETURN(pDstParentRef != NULL, NV_ERR_INVALID_OBJECT_PARENT); NV_ASSERT_OR_RETURN(pMemorySrc != NULL, NV_ERR_INVALID_OBJECT_HANDLE); - NV_CHECK_OK_OR_RETURN(LEVEL_INFO, memIsReady(pMemorySrc)); + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, memIsReady(pMemorySrc, NV_TRUE)); // // Must return early when parent is Client. @@ -945,7 +963,7 @@ memGetMemInterMapParams_IMPL NvHandle hMemoryDevice = 0; OBJGPU *pSrcGpu = pGpu; - NV_CHECK_OK_OR_RETURN(LEVEL_INFO, memIsReady(pMemory)); + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, memIsReady(pMemory, NV_FALSE)); if (pMemoryRef->pParentRef != NULL) { @@ -1014,7 +1032,7 @@ memGetMemoryMappingDescriptor_IMPL MEMORY_DESCRIPTOR **ppMemDesc ) { - NV_CHECK_OK_OR_RETURN(LEVEL_INFO, memIsReady(pMemory)); + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, memIsReady(pMemory, NV_FALSE)); if (pMemory->pGpu != NULL) { *ppMemDesc = memdescGetMemDescFromGpu(pMemory->pMemDesc, pMemory->pGpu); @@ -1026,3 +1044,29 @@ memGetMemoryMappingDescriptor_IMPL return NV_OK; } +NV_STATUS +memIsDuplicate_IMPL +( + Memory *pMemory, + NvHandle hMemory, + NvBool *pDuplicate +) +{ + RsClient *pClient = RES_GET_CLIENT(pMemory); + Memory *pMemory1; + + NV_CHECK_OK_OR_RETURN(LEVEL_SILENT, + memIsReady(pMemory, NV_FALSE)); + + NV_CHECK_OK_OR_RETURN(LEVEL_SILENT, + memGetByHandle(pClient, hMemory, &pMemory1)); + + // + // Do not dereference pMemdesc here. We only take RMAPI RO lock and + // client lock in this context. + // + + *pDuplicate = (pMemory->pMemDesc == pMemory1->pMemDesc); + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/mem_mgr/mem_fabric.c b/src/nvidia/src/kernel/mem_mgr/mem_fabric.c index 3b4061616..4b4167bee 100644 --- a/src/nvidia/src/kernel/mem_mgr/mem_fabric.c +++ b/src/nvidia/src/kernel/mem_mgr/mem_fabric.c @@ -54,8 +54,6 @@ #include "kernel/gpu/nvlink/kernel_nvlink.h" #include "ctrl/ctrl0041.h" -#include "published/ampere/ga100/dev_mmu.h" - static NvU32 _memoryfabricMemDescGetNumAddr ( @@ -81,6 +79,214 @@ _memoryfabricMemDescGetNumAddr return (memdescGetSize(pMemDesc) / pageSize); } +static NV_STATUS +_memoryfabricValidatePhysMem +( + NvHandle hClient, + NvHandle hPhysMem, + OBJGPU *pOwnerGpu, + MEMORY_DESCRIPTOR **ppPhysMemDesc +) +{ + RsResourceRef *pPhysmemRef; + MEMORY_DESCRIPTOR *pPhysMemDesc; + NvU32 physPageSize; + NV_STATUS status; + + if (hPhysMem == 0) + { + NV_PRINTF(LEVEL_ERROR, "Invalid physmem handle\n"); + + return NV_ERR_INVALID_ARGUMENT; + } + + status = serverutilGetResourceRef(hClient, hPhysMem, &pPhysmemRef); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to get resource in resserv for physmem handle\n"); + + return status; + } + + pPhysMemDesc = (dynamicCast(pPhysmemRef->pResource, Memory))->pMemDesc; + + if ((memdescGetAddressSpace(pPhysMemDesc) != ADDR_FBMEM) || + (pOwnerGpu != pPhysMemDesc->pGpu)) + { + NV_PRINTF(LEVEL_ERROR, "Invalid physmem handle passed\n"); + + return NV_ERR_INVALID_ARGUMENT; + } + + physPageSize = memdescGetPageSize(pPhysMemDesc, AT_GPU); + if ((physPageSize != NV_MEMORY_FABRIC_PAGE_SIZE_2M) && + (physPageSize != NV_MEMORY_FABRIC_PAGE_SIZE_512M)) + { + NV_PRINTF(LEVEL_ERROR, "Physmem page size should be 2MB\n"); + + return NV_ERR_INVALID_ARGUMENT; + } + + *ppPhysMemDesc = pPhysMemDesc; + + return NV_OK; +} + +static NV_STATUS +_memoryFabricDetachMem +( + MEMORY_DESCRIPTOR *pFabricMemDesc, + NvU64 offset +) +{ + NV_STATUS status; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + FABRIC_ATTCH_MEM_INFO_NODE *pAttachMemInfoNode; + NODE *pNode = NULL; + FABRIC_VASPACE *pFabricVAS; + MEMORY_DESCRIPTOR *pPhysMemDesc; + FABRIC_MEMDESC_DATA *pMemdescData; + + pMemdescData = (FABRIC_MEMDESC_DATA *)memdescGetMemData(pFabricMemDesc); + + status = btreeSearch(offset, &pNode, pMemdescData->pAttachMemInfoTree); + if (status != NV_OK) + return status; + + pAttachMemInfoNode = (FABRIC_ATTCH_MEM_INFO_NODE *)pNode->Data; + pPhysMemDesc = pAttachMemInfoNode->pPhysMemDesc; + pFabricVAS = dynamicCast(pPhysMemDesc->pGpu->pFabricVAS, FABRIC_VASPACE); + + fabricvaspaceUnmapPhysMemdesc(pFabricVAS, pFabricMemDesc, offset, + pPhysMemDesc, + pAttachMemInfoNode->physMapLength); + + NV_ASSERT_OK(pRmApi->Free(pRmApi, pFabricVAS->hClient, + pAttachMemInfoNode->hDupedPhysMem)); + + btreeUnlink(&pAttachMemInfoNode->node, &pMemdescData->pAttachMemInfoTree); + + portMemFree(pAttachMemInfoNode); + + return NV_OK; +} + +static void +_memoryFabricBatchDetachMem +( + MEMORY_DESCRIPTOR *pFabricMemDesc +) +{ + FABRIC_MEMDESC_DATA *pMemdescData; + NODE *pNode = NULL; + NvU64 offset; + pMemdescData = (FABRIC_MEMDESC_DATA *)memdescGetMemData(pFabricMemDesc); + + if (pMemdescData == NULL) + return; + + btreeEnumStart(0, &pNode, pMemdescData->pAttachMemInfoTree); + while (pNode != NULL) + { + offset = pNode->keyStart; + btreeEnumNext(&pNode, pMemdescData->pAttachMemInfoTree); + NV_ASSERT_OK(_memoryFabricDetachMem(pFabricMemDesc, offset)); + } +} + +static NV_STATUS +_memoryFabricAttachMem +( + MemoryFabric *pMemoryFabric, + NV00F8_CTRL_ATTACH_MEM_INFO *pAttachInfo +) +{ + NV_STATUS status; + Memory *pMemory = staticCast(pMemoryFabric, Memory); + OBJGPU *pGpu = pMemory->pGpu; + MEMORY_DESCRIPTOR *pPhysMemDesc; + MEMORY_DESCRIPTOR *pFabricMemDesc = pMemory->pMemDesc; + FABRIC_MEMDESC_DATA *pMemdescData; + NvHandle hDupedPhysMem = 0; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + FABRIC_VASPACE *pFabricVAS = dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); + FABRIC_ATTCH_MEM_INFO_NODE *pNode; + + pMemdescData = (FABRIC_MEMDESC_DATA *)memdescGetMemData(pFabricMemDesc); + + if (!(pMemdescData->allocFlags & NV00F8_ALLOC_FLAGS_FLEXIBLE_FLA)) + { + NV_PRINTF(LEVEL_ERROR, "Unsupported fabric memory type\n"); + return NV_ERR_NOT_SUPPORTED; + } + + status = _memoryfabricValidatePhysMem(RES_GET_CLIENT_HANDLE(pMemory), + pAttachInfo->hMemory, + pGpu, &pPhysMemDesc); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, status); + + status = pRmApi->DupObject(pRmApi, pFabricVAS->hClient, pFabricVAS->hDevice, + &hDupedPhysMem, RES_GET_CLIENT_HANDLE(pMemory), + pAttachInfo->hMemory, 0); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to dup physmem handle\n"); + return status; + } + + status = fabricvaspaceMapPhysMemdesc(pFabricVAS, + pFabricMemDesc, + pAttachInfo->offset, + pPhysMemDesc, + pAttachInfo->mapOffset, + pAttachInfo->mapLength, + 0); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to map FLA\n"); + goto freeDupedMem; + } + + pNode = portMemAllocNonPaged(sizeof(*pNode)); + if (pNode == NULL) + { + status = NV_ERR_NO_MEMORY; + goto unmapVas; + } + + portMemSet(pNode, 0, sizeof(*pNode)); + + pNode->node.keyStart = pAttachInfo->offset; + pNode->node.keyEnd = pAttachInfo->offset; + pNode->physMapLength = pAttachInfo->mapLength; + pNode->pPhysMemDesc = pPhysMemDesc; + pNode->hDupedPhysMem = hDupedPhysMem; + pNode->node.Data = pNode; + + status = btreeInsert(&pNode->node, &pMemdescData->pAttachMemInfoTree); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to track attach mem info\n"); + goto freeNode; + } + + return NV_OK; + +freeNode: + portMemFree(pNode); + +unmapVas: + fabricvaspaceUnmapPhysMemdesc(pFabricVAS, pFabricMemDesc, pAttachInfo->offset, + pPhysMemDesc, pAttachInfo->mapLength); + +freeDupedMem: + NV_ASSERT_OK(pRmApi->Free(pRmApi, pFabricVAS->hClient, hDupedPhysMem)); + + return status; +} + static void _memoryfabricMemDescDestroyCallback ( @@ -89,24 +295,28 @@ _memoryfabricMemDescDestroyCallback MEMORY_DESCRIPTOR *pMemDesc ) { - RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); - FABRIC_VASPACE *pFabricVAS = dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + FABRIC_VASPACE *pFabricVAS; + RmPhysAddr *pteArray; + FABRIC_MEMDESC_DATA *pMemdescData; + NvU32 numAddr; + NvU32 pageSize; - FABRIC_MEMDESC_DATA *pMemdescData = - (FABRIC_MEMDESC_DATA *)memdescGetMemData(pMemDesc); - - RmPhysAddr *pteArray = memdescGetPteArrayForGpu(pMemDesc, pGpu, - VAS_ADDRESS_TRANSLATION(pGpu->pFabricVAS)); - - NvU32 numAddr = _memoryfabricMemDescGetNumAddr(pMemDesc); + NV_ASSERT_OR_RETURN_VOID(pGpu->pFabricVAS != NULL); + pFabricVAS = dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); + pMemdescData = (FABRIC_MEMDESC_DATA *)memdescGetMemData(pMemDesc); + pteArray = memdescGetPteArrayForGpu(pMemDesc, pGpu, VAS_ADDRESS_TRANSLATION(pGpu->pFabricVAS)); + numAddr = _memoryfabricMemDescGetNumAddr(pMemDesc); // Get the page size from the memory descriptor. - NvU32 pageSize = memdescGetPageSize(pMemDesc, - VAS_ADDRESS_TRANSLATION(pGpu->pFabricVAS)); + pageSize = memdescGetPageSize(pMemDesc, VAS_ADDRESS_TRANSLATION(pGpu->pFabricVAS)); // Remove the fabric memory allocations from the map. fabricvaspaceVaToGpaMapRemove(pFabricVAS, pteArray[0]); + // Detach any pending memory... + _memoryFabricBatchDetachMem(pMemDesc); + if (!pFabricVAS->bRpcAlloc) { // @@ -117,108 +327,21 @@ _memoryfabricMemDescDestroyCallback fabricvaspaceBatchFree(pFabricVAS, pteArray, numAddr, (pageSize >> RM_PAGE_SHIFT)); } - // Destroy the duped physical video memory handle. - if ((pMemdescData != NULL) && (pMemdescData->hDupedVidmem != 0)) + if (pMemdescData != NULL) { - NV_ASSERT(pRmApi->Free(pRmApi, pFabricVAS->hClient, - pMemdescData->hDupedVidmem) == NV_OK); + if (pMemdescData->hDupedPhysMem != 0) + { + NV_ASSERT(pRmApi->Free(pRmApi, pFabricVAS->hClient, + pMemdescData->hDupedPhysMem) == NV_OK); + } portMemFree(pMemDesc->_pMemData); + memdescSetMemData(pMemDesc, NULL, NULL); } portMemFree(pObject); } -static NV_STATUS -_memoryfabricMapPhysicalMemory -( - NvU64 *vAddr, - NvU32 numAddr, - NvU64 allocSize, - NvU32 pageSize, - MEMORY_DESCRIPTOR *pVidMemDesc, - NvU64 offset, - NvBool bReadOnly -) -{ - OBJGPU *pGpu = pVidMemDesc->pGpu; - VirtMemAllocator *pDma = GPU_GET_DMA(pGpu); - MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); - NV_STATUS status = NV_OK; - DMA_PAGE_ARRAY pageArray; - NvU64 mapLength; - NvU32 kind; - COMPR_INFO comprInfo; - NvU32 vidmemPteArraySize; - RmPhysAddr addr; - NvU32 i; - FABRIC_VASPACE *pFabricVAS; - NvU32 mapFlags = DMA_UPDATE_VASPACE_FLAGS_UPDATE_ALL | - DMA_UPDATE_VASPACE_FLAGS_SKIP_4K_PTE_CHECK; - - NV_ASSERT_OR_RETURN(vAddr != NULL, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(pVidMemDesc != NULL, NV_ERR_INVALID_ARGUMENT); - - mapFlags |= bReadOnly ? DMA_UPDATE_VASPACE_FLAGS_READ_ONLY : 0; - - pFabricVAS = dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); - - if (pFabricVAS->bRpcAlloc) - return NV_OK; - - // Get compression attributes for the vidmem memdesc. - status = memmgrGetKindComprFromMemDesc(pMemoryManager, pVidMemDesc, offset, &kind, &comprInfo); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "Failed to get the compression attributes for the vidmem memdesc\n"); - return status; - } - - portMemSet(&pageArray, 0, sizeof(DMA_PAGE_ARRAY)); - - // Get the vidmem pteArray size. - vidmemPteArraySize = memdescGetPteArraySize(pVidMemDesc, AT_GPU); - - // Get the fabric addr range to map. - mapLength = (numAddr == 1 ? allocSize : pageSize); - pageArray.count = (vidmemPteArraySize == 1 ? 1 : (mapLength / RM_PAGE_SIZE)); - - for (i = 0; i < numAddr; i++) - { - if (pageArray.count == 1) - { - addr = pVidMemDesc->_pteArray[0] + offset; - pageArray.pData = &addr; - } - else - { - pageArray.pData = &pVidMemDesc->_pteArray[offset / RM_PAGE_SIZE]; - } - - // Map the memory fabric object at the given physical video memory offset. - status = dmaUpdateVASpace_HAL(pGpu, pDma, pFabricVAS->pGVAS, pVidMemDesc, - NULL, vAddr[i], vAddr[i] + mapLength - 1, - mapFlags, &pageArray, 0, &comprInfo, 0, - NV_MMU_PTE_VALID_TRUE, - NV_MMU_PTE_APERTURE_VIDEO_MEMORY, - BUS_INVALID_PEER, NVLINK_INVALID_FABRIC_ADDR, - DMA_DEFER_TLB_INVALIDATE, NV_FALSE); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "Failed to map fabric addrs starting at 0x%llx\n", vAddr[i]); - return status; - } - - offset = offset + mapLength; - } - - fabricvaspaceInvalidateTlb(pFabricVAS, pVidMemDesc->pGpu, PTE_UPGRADE); - - return NV_OK; -} - static void _memoryfabricFreeFabricVa_VGPU ( @@ -353,8 +476,6 @@ _memoryfabricAllocFabricVa NvU32 *pNumAddr ) { - OBJVASPACE *pOBJVASPACE = staticCast(pFabricVAS, OBJVASPACE); - if (pFabricVAS->bRpcAlloc) { return _memoryfabricAllocFabricVa_VGPU(pGpu, pParams, @@ -366,8 +487,8 @@ _memoryfabricAllocFabricVa return fabricvaspaceAllocNonContiguous(pFabricVAS, pAllocParams->allocSize, pAllocParams->alignment, - vaspaceGetVaStart(pOBJVASPACE), - vaspaceGetVaLimit(pOBJVASPACE), + fabricvaspaceGetUCFlaStart(pFabricVAS), + fabricvaspaceGetUCFlaLimit(pFabricVAS), pAllocParams->pageSize, flags, ppAddr, pNumAddr); } @@ -387,8 +508,7 @@ memoryfabricConstruct_IMPL NV00F8_ALLOCATION_PARAMETERS *pAllocParams = pParams->pAllocParams; RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); - RsResourceRef *pVidmemRef = NULL; - MEMORY_DESCRIPTOR *pVidMemDesc = NULL; + MEMORY_DESCRIPTOR *pPhysMemDesc = NULL; NV_STATUS status = NV_OK; MEMORY_DESCRIPTOR *pMemDesc = NULL; FABRIC_MEMDESC_DATA *pMemdescData = NULL; @@ -398,6 +518,9 @@ memoryfabricConstruct_IMPL NvU32 numAddr = 0; NvU32 pteKind = 0; NvBool bReadOnly = NV_FALSE; + NvHandle hPhysMem; + NvBool bFlexible = NV_FALSE; + NvU32 mapFlags = 0; if (RS_IS_COPY_CTOR(pParams)) { @@ -406,6 +529,23 @@ memoryfabricConstruct_IMPL pParams); } + hPhysMem = pAllocParams->map.hVidMem; + + // Check if fabric vaspace is valid. + if (pFabricVAS == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Fabric vaspace object not available\n"); + + return NV_ERR_NOT_SUPPORTED; + } + + // initialize Fabric VAS Unicast range if not already setup + if (fabricvaspaceGetUCFlaLimit(pFabricVAS) == 0) + { + NV_PRINTF(LEVEL_ERROR, "UC FLA ranges should be initialized by this time!\n"); + return NV_ERR_INVALID_STATE; + } + // Only page size 512MB and 2MB supported. if ((pAllocParams->pageSize != NV_MEMORY_FABRIC_PAGE_SIZE_512M) && (pAllocParams->pageSize != NV_MEMORY_FABRIC_PAGE_SIZE_2M)) @@ -434,8 +574,10 @@ memoryfabricConstruct_IMPL return NV_ERR_INVALID_ARGUMENT; } + bFlexible = !!(pAllocParams->allocFlags & NV00F8_ALLOC_FLAGS_FLEXIBLE_FLA); + // We don't support flexible mappings yet. - if (pAllocParams->allocFlags & NV00F8_ALLOC_FLAGS_FLEXIBLE_FLA) + if (bFlexible) { NV_PRINTF(LEVEL_ERROR, "Only sticky mappings are supported\n"); @@ -445,7 +587,7 @@ memoryfabricConstruct_IMPL if (pAllocParams->allocFlags & NV00F8_ALLOC_FLAGS_READ_ONLY) { -#if !defined(DEVELOP) && !defined(DEBUG) && !defined(NV_MODS) +#if !defined(DEVELOP) && !defined(DEBUG) && !RMCFG_FEATURE_MODS_FEATURES NV_PRINTF(LEVEL_ERROR, "RO mappings are only supported on non-release builds\n"); @@ -455,68 +597,20 @@ memoryfabricConstruct_IMPL #endif } - // For sticky mappings, physical video memory handle is needed. - if (pAllocParams->map.hVidMem == 0) + if (bFlexible && (hPhysMem != 0)) { NV_PRINTF(LEVEL_ERROR, - "Physical vidmem handle needed for sticky mappings\n"); - - return NV_ERR_INVALID_ARGUMENT; - } - - status = serverutilGetResourceRef(pCallContext->pClient->hClient, - pAllocParams->map.hVidMem, &pVidmemRef); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "Failed to get resource in resserv for vidmem handle\n"); - return status; - } - - pVidMemDesc = (dynamicCast(pVidmemRef->pResource, Memory))->pMemDesc; - - if ((memdescGetAddressSpace(pVidMemDesc) != ADDR_FBMEM) || - (pGpu != pVidMemDesc->pGpu)) - { - NV_PRINTF(LEVEL_ERROR, "Invalid physical vidmem handle passed\n"); - - return NV_ERR_INVALID_ARGUMENT; - } - - if (memdescGetPageSize(pVidMemDesc, AT_GPU) != NV_MEMORY_FABRIC_PAGE_SIZE_2M) - { - NV_PRINTF(LEVEL_ERROR, "Physical vidmem page size should be 2MB\n"); - - return NV_ERR_INVALID_ARGUMENT; - } - - if ((pAllocParams->map.offset >= pVidMemDesc->Size) || - !NV_IS_ALIGNED64(pAllocParams->map.offset, NV_MEMORY_FABRIC_PAGE_SIZE_2M)) - { - NV_PRINTF(LEVEL_ERROR, - "Invalid offset passed for the physical vidmem handle\n"); - - return NV_ERR_INVALID_OFFSET; - } - - // hVidmem should be big enough to cover allocSize, starting from offset. - if (pAllocParams->allocSize > - (memdescGetSize(pVidMemDesc) - pAllocParams->map.offset)) - { - NV_PRINTF(LEVEL_ERROR, - "Insufficient physical video memory to map the requested " - "memory fabric allocation\n"); - - return NV_ERR_INVALID_ARGUMENT; - } - - // Check if fabric vaspace is valid. - if (pFabricVAS == NULL) - { - NV_PRINTF(LEVEL_ERROR, "Fabric vaspace object not available\n"); + "Physmem can't be provided during flexible object alloc\n"); return NV_ERR_NOT_SUPPORTED; } + else if (!bFlexible) + { + status = _memoryfabricValidatePhysMem(pCallContext->pClient->hClient, + hPhysMem, pGpu, &pPhysMemDesc); + if (status != NV_OK) + return status; + } // Set the vaspace alloc flags. flags.bSkipTlbInvalidateOnFree = NV_TRUE; @@ -536,8 +630,8 @@ memoryfabricConstruct_IMPL "VA Space alloc failed! Status Code: 0x%x Size: 0x%llx " "RangeLo: 0x%llx, RangeHi: 0x%llx, page size: 0x%x\n", status, pAllocParams->allocSize, - vaspaceGetVaStart(pGpu->pFabricVAS), - vaspaceGetVaLimit(pGpu->pFabricVAS), + fabricvaspaceGetUCFlaStart(pFabricVAS), + fabricvaspaceGetUCFlaLimit(pFabricVAS), pAllocParams->pageSize); return status; @@ -617,19 +711,25 @@ memoryfabricConstruct_IMPL memdescAddDestroyCallback(pMemDesc, pCallback); - // Dup the physical video memory handle and cache it in memfabric memdesc. - status = pRmApi->DupObject(pRmApi, pFabricVAS->hClient, pFabricVAS->hDevice, - &pMemdescData->hDupedVidmem, pCallContext->pClient->hClient, - pAllocParams->map.hVidMem, 0); - - if (status != NV_OK) + // + // In case of flexible mappings, we don't support: + // + // 1. Caching attributes of physical memory + // 2. FLA to GPA tracking to allow FLA object to be mapped as local memory + // + if (hPhysMem != 0) { - NV_PRINTF(LEVEL_ERROR, "Failed to dup physical video memory handle\n"); - goto freeCallback; - } + // Dup the physical memory handle and cache it in memfabric memdesc. + status = pRmApi->DupObject(pRmApi, pFabricVAS->hClient, pFabricVAS->hDevice, + &pMemdescData->hDupedPhysMem, pCallContext->pClient->hClient, + hPhysMem, 0); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to dup physmem handle\n"); + goto freeCallback; + } - if (!(pAllocParams->allocFlags & NV00F8_ALLOC_FLAGS_FLEXIBLE_FLA)) - { NV0041_CTRL_SURFACE_INFO surfaceInfo[2] = {0}; NV0041_CTRL_GET_SURFACE_INFO_PARAMS surfaceInfoParam = {0}; @@ -640,34 +740,46 @@ memoryfabricConstruct_IMPL status = pRmApi->Control(pRmApi, pFabricVAS->hClient, - pMemdescData->hDupedVidmem, + pMemdescData->hDupedPhysMem, NV0041_CTRL_CMD_GET_SURFACE_INFO, &surfaceInfoParam, sizeof(surfaceInfoParam)); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "Failed to query physical video memory info\n"); + NV_PRINTF(LEVEL_ERROR, "Failed to query physmem info\n"); goto freeDupedMem; } pMemdescData->physAttrs.addressSpace = surfaceInfo[0].data; pMemdescData->physAttrs.compressionCoverage = surfaceInfo[1].data; - } - status = fabricvaspaceVaToGpaMapInsert(pFabricVAS, pAddr[0], pVidMemDesc, - pAllocParams->map.offset); - if (status != NV_OK) - goto freeDupedMem; + mapFlags |= bReadOnly ? FABRIC_VASPACE_MAP_FLAGS_READ_ONLY : 0; - // Map the memory fabric object at the given physical video memory offset. - status = _memoryfabricMapPhysicalMemory(pAddr, numAddr, pAllocParams->allocSize, - pAllocParams->pageSize, pVidMemDesc, - pAllocParams->map.offset, bReadOnly); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "Failed to map FLA at the given physical vidmem offset\n"); - goto memFabricRemoveVaToGpaMap; + // + // Sticky FLA object should be mapped completely, so pass + // pAllocParams->allocSize.as mapLength. + // + status = fabricvaspaceMapPhysMemdesc(pFabricVAS, + pMemDesc, 0, + pPhysMemDesc, + pAllocParams->map.offset, + pAllocParams->allocSize, + mapFlags); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to map FLA at the given physmem offset\n"); + goto freeDupedMem; + } + + // + // No need to unmap on failure. Unmap happens implicitly when fabric VA + // would be freed. + // + status = fabricvaspaceVaToGpaMapInsert(pFabricVAS, pAddr[0], pPhysMemDesc, + pAllocParams->map.offset); + if (status != NV_OK) + goto freeDupedMem; } pMemdescData->allocFlags = pAllocParams->allocFlags; @@ -677,13 +789,10 @@ memoryfabricConstruct_IMPL return NV_OK; -memFabricRemoveVaToGpaMap: - fabricvaspaceVaToGpaMapRemove(pFabricVAS, pAddr[0]); - freeDupedMem: - // Free the duped vidmem handle. + // Free the duped physmem handle. NV_ASSERT(pRmApi->Free(pRmApi, pFabricVAS->hClient, - pMemdescData->hDupedVidmem) == NV_OK); + pMemdescData->hDupedPhysMem) == NV_OK); freeCallback: // Destroy the memdesc destroy callback. @@ -754,30 +863,6 @@ memoryfabricCopyConstruct_IMPL return NV_OK; } -NvBool -memoryfabricCanExport_IMPL -( - MemoryFabric *pMemoryFabric -) -{ - Memory *pMemory = staticCast(pMemoryFabric, Memory); - FABRIC_MEMDESC_DATA *pMemdescData; - - if (pMemory->pMemDesc == NULL) - return NV_ERR_INVALID_ARGUMENT; - - pMemdescData = (FABRIC_MEMDESC_DATA *)memdescGetMemData(pMemory->pMemDesc); - - // - // Check if FLA->PA mappings are present. Only then allow export. - // FLA->PA mappings are guaranteed for STICKY FLA mappings, which is only - // what we support currently. - // TODO: Re-visit this function when support for FLEXIBLE FLA mappings is - // added. - // - return !(pMemdescData->allocFlags & NV00F8_ALLOC_FLAGS_FLEXIBLE_FLA); -} - NV_STATUS memoryfabricControl_IMPL ( @@ -827,5 +912,111 @@ memoryfabricCtrlCmdDescribe_IMPL NV00F8_CTRL_DESCRIBE_PARAMS *pParams ) { - return NV_ERR_NOT_SUPPORTED; + Memory *pMemory = staticCast(pMemoryFabric, Memory); + NvU64 *pFabricArray; + NvU64 offset; + NvU64 pageSize; + NvU32 i; + + if (pMemory->pMemDesc == NULL) + return NV_ERR_INVALID_ARGUMENT; + + pageSize = memdescGetPageSize(pMemory->pMemDesc, AT_GPU); + + if (memdescGetContiguity(pMemory->pMemDesc, AT_GPU)) + pParams->totalPfns = 1; + else + pParams->totalPfns = memdescGetSize(pMemory->pMemDesc) / pageSize; + + if (pParams->offset >= pParams->totalPfns) + { + NV_PRINTF(LEVEL_ERROR, "offset: %llx is out of range: %llx \n", pParams->offset, + pParams->totalPfns); + return NV_ERR_OUT_OF_RANGE; + } + + pParams->numPfns = NV_MIN(pParams->totalPfns - pParams->offset, + NV00F8_CTRL_DESCRIBE_PFN_ARRAY_SIZE); + + pFabricArray = portMemAllocNonPaged(sizeof(NvU64) * pParams->numPfns); + + if (pFabricArray == NULL) + return NV_ERR_NO_MEMORY; + + offset = pParams->offset * pageSize; + memdescGetPhysAddrsForGpu(pMemory->pMemDesc, pMemory->pMemDesc->pGpu, AT_GPU, offset, + pageSize, pParams->numPfns, + pFabricArray); + + for (i = 0; i < pParams->numPfns; i++) + { + pParams->pfnArray[i] = (NvU32)(pFabricArray[i] >> RM_PAGE_SHIFT_HUGE); + } + + portMemFree(pFabricArray); + + return NV_OK; +} + +NV_STATUS +memoryfabricCtrlAttachMem_IMPL +( + MemoryFabric *pMemoryFabric, + NV00F8_CTRL_ATTACH_MEM_PARAMS *pParams +) +{ + NvU32 i; + NV_STATUS status; + + pParams->numAttached = 0; + + if (pParams->flags != 0) + return NV_ERR_INVALID_ARGUMENT; + + if ((pParams->numMemInfos == 0) || + (pParams->numMemInfos > NV00F8_MAX_ATTACHABLE_MEM_INFOS)) + return NV_ERR_INVALID_ARGUMENT; + + for (i = 0; i < pParams->numMemInfos; i++) + { + status = _memoryFabricAttachMem(pMemoryFabric, &pParams->memInfos[i]); + if (status != NV_OK) + return status; + + pParams->numAttached++; + } + + return NV_OK; +} + +NV_STATUS +memoryfabricCtrlDetachMem_IMPL +( + MemoryFabric *pMemoryFabric, + NV00F8_CTRL_DETACH_MEM_PARAMS *pParams +) +{ + NvU32 i; + NV_STATUS status; + Memory *pMemory = staticCast(pMemoryFabric, Memory); + + pParams->numDetached = 0; + + if (pParams->flags != 0) + return NV_ERR_INVALID_ARGUMENT; + + if ((pParams->numOffsets == 0) || + pParams->numOffsets > NV00F8_MAX_DETACHABLE_OFFSETS) + return NV_ERR_INVALID_ARGUMENT; + + for (i = 0; i < pParams->numOffsets; i++) + { + status = _memoryFabricDetachMem(pMemory->pMemDesc, pParams->offsets[i]); + if (status != NV_OK) + return status; + + pParams->numDetached++; + } + + return NV_OK; } diff --git a/src/nvidia/src/kernel/mem_mgr/mem_list.c b/src/nvidia/src/kernel/mem_mgr/mem_list.c new file mode 100644 index 000000000..0188ccc4f --- /dev/null +++ b/src/nvidia/src/kernel/mem_mgr/mem_list.c @@ -0,0 +1,790 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "mem_mgr_internal.h" +#include "mem_mgr/mem_list.h" +#include "deprecated/rmapi_deprecated.h" + +#include "mem_mgr/video_mem.h" +#include "gpu/mem_mgr/mem_desc.h" +#include "gpu/device/device.h" +#include "gpu/mem_mgr/mem_mgr.h" +#include "gpu/mem_sys/kern_mem_sys.h" +#include "gpu/mmu/kern_gmmu.h" +#include "gpu/bus/kern_bus.h" +#include "vgpu/vgpu_events.h" +#include "virtualization/hypervisor/hypervisor.h" +#include "gpu/mem_mgr/heap.h" +#include "os/os.h" +#include "rmapi/client.h" + +#include "class/cl003e.h" // NV01_MEMORY_SYSTEM +#include "class/cl84a0.h" // NV01_MEMORY_LIST_XXX +#include "class/cl0040.h" // NV01_MEMORY_LOCAL_USER + +NV_STATUS +memlistConstruct_IMPL +( + MemoryList *pMemoryList, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ +#define CLEAR_HAL_ATTR(a) \ + a = (a & ~(DRF_SHIFTMASK(NVOS32_ATTR_COMPR) | \ + DRF_SHIFTMASK(NVOS32_ATTR_TILED) | \ + DRF_SHIFTMASK(NVOS32_ATTR_ZCULL))); + +#define CLEAR_HAL_ATTR2(a) \ + a = (a & ~(DRF_SHIFTMASK(NVOS32_ATTR2_ZBC) | \ + DRF_SHIFTMASK(NVOS32_ATTR2_GPU_CACHEABLE))); + + NV_MEMORY_LIST_ALLOCATION_PARAMS *pAllocParams; + RsResourceRef *pResourceRef = pCallContext->pResourceRef; + NvHandle hClient = pCallContext->pClient->hClient; + NvHandle hParent = pResourceRef->pParentRef->hResource; + NvU32 externalClassId = pResourceRef->externalClassId; + Memory *pMemory = staticCast(pMemoryList, Memory); + OBJGPU *pGpu = pMemory->pGpu; + NvBool bUserModeArgs = (pCallContext->secInfo.paramLocation == PARAM_LOCATION_USER); + MEMORY_DESCRIPTOR *pMemDesc = NULL; + NV_STATUS status = NV_OK; + NvU64 memSize; + NvU32 i; + Memory *pMemoryInfo = NULL; // TODO: This needs a more descriptive name (MemoryInfo for what?) + NV_ADDRESS_SPACE addressSpace = ADDR_UNKNOWN; + NvU32 Cache = 0; + MEMORY_DESCRIPTOR *src_pMemDesc = NULL; + NvU32 src_hClient; + NvU32 src_hParent; + OBJGPU *src_pGpu; + RmPhysAddr *pPteArray = NULL; + NvBool bContig; + NvU32 src_hHwResClient; + NvU32 src_hHwResDevice; + NvU32 src_hHwResHandle; + NvU32 result; + RS_PRIV_LEVEL privLevel = pCallContext->secInfo.privLevel; + + // Copy-construction has already been done by the base Memory class + if (RS_IS_COPY_CTOR(pParams)) + return NV_OK; + + pAllocParams = pParams->pAllocParams; + + // + // We use memory list support in the GSP/DCE firmware RM so we want + // to bypass the hypervisor check here. + // + if (!hypervisorIsVgxHyper()) + { + if (IS_VIRTUAL(pGpu) && privLevel >= RS_PRIV_LEVEL_KERNEL) + { + goto continue_alloc_object; + } + if (IS_GSP_CLIENT(pGpu)) + { + goto continue_alloc_object; + } + return NV_ERR_NOT_SUPPORTED; + } +continue_alloc_object: + + // + // These classes are used by the vGPU support to create memory objects for memory + // assigned to a guest VM. The NV01_MEMORY_LIST_OBJECT case creates an object + // whose pages are based on another object's pages. + // + if ((externalClassId == NV01_MEMORY_LIST_FBMEM) || (externalClassId == NV01_MEMORY_LIST_OBJECT)) + { + if (!(rmclientIsAdminByHandle(hClient, privLevel) || hypervisorCheckForObjectAccess(hClient))) + return NV_ERR_INSUFFICIENT_PERMISSIONS; + } + else + { + if (!rmclientIsAdminByHandle(hClient, privLevel)) + return NV_ERR_INSUFFICIENT_PERMISSIONS; + } + + if (DRF_VAL(OS02, _FLAGS, _COHERENCY, pAllocParams->flagsOs02) == NVOS02_FLAGS_COHERENCY_UNCACHED) + Cache = NV_MEMORY_UNCACHED; + else if (DRF_VAL(OS02, _FLAGS, _COHERENCY, pAllocParams->flagsOs02) == NVOS02_FLAGS_COHERENCY_CACHED) + Cache = NV_MEMORY_CACHED; + else if (DRF_VAL(OS02, _FLAGS, _COHERENCY, pAllocParams->flagsOs02) == NVOS02_FLAGS_COHERENCY_WRITE_COMBINE) + Cache = NV_MEMORY_WRITECOMBINED; + else if (DRF_VAL(OS02, _FLAGS, _COHERENCY, pAllocParams->flagsOs02) == NVOS02_FLAGS_COHERENCY_WRITE_THROUGH) + Cache = NV_MEMORY_CACHED; + else if (DRF_VAL(OS02, _FLAGS, _COHERENCY, pAllocParams->flagsOs02) == NVOS02_FLAGS_COHERENCY_WRITE_PROTECT) + Cache = NV_MEMORY_CACHED; + else if (DRF_VAL(OS02, _FLAGS, _COHERENCY, pAllocParams->flagsOs02) == NVOS02_FLAGS_COHERENCY_WRITE_BACK) + Cache = NV_MEMORY_CACHED; + + src_hClient = pAllocParams->hClient; + src_hParent = pAllocParams->hParent; + src_hHwResClient = pAllocParams->hHwResClient; + src_hHwResDevice = pAllocParams->hHwResDevice; + src_hHwResHandle = pAllocParams->hHwResHandle; + + if (src_hClient == NV01_NULL_OBJECT) + { + src_hClient = hClient; + if (src_hParent != NV01_NULL_OBJECT) + { + return NV_ERR_INVALID_OBJECT_PARENT; + } + src_hParent = hParent; + src_pGpu = pGpu; + } + else + { + RsClient *pClient; + + status = serverGetClientUnderLock(&g_resServ, src_hClient, &pClient); + if (status != NV_OK) + return status; + + status = gpuGetByHandle(pClient, src_hParent, NULL, &src_pGpu); + if (status != NV_OK) + return status; + + if (src_pGpu != pGpu) + return NV_ERR_INVALID_OBJECT_PARENT; + } + + if (externalClassId == NV01_MEMORY_LIST_OBJECT) + { + if (pAllocParams->hObject == NV01_NULL_OBJECT) + { + return NV_ERR_INVALID_ARGUMENT; + } + } + else + { + if (pAllocParams->hObject != NV01_NULL_OBJECT) + { + return NV_ERR_INVALID_ARGUMENT; + } + } + if (pAllocParams->reserved_0 || (pAllocParams->pteAdjust >= RM_PAGE_SIZE)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + NV_ASSERT_OR_RETURN(!(pAllocParams->flags & NVOS32_ALLOC_FLAGS_VIRTUAL), NV_ERR_NOT_SUPPORTED); + + switch (externalClassId) + { + case NV01_MEMORY_LIST_SYSTEM: + addressSpace = ADDR_SYSMEM; + break; + case NV01_MEMORY_LIST_FBMEM: + addressSpace = ADDR_FBMEM; + if (src_hHwResHandle != 0) + { + RsClient *pHwResClient; + + status = serverGetClientUnderLock(&g_resServ, src_hHwResClient, &pHwResClient); + if (status == NV_OK) + { + status = memGetByHandleAndDevice(pHwResClient, src_hHwResHandle, + src_hHwResDevice, &pMemoryInfo); + } + if (status != NV_OK) + { + src_hHwResHandle = 0; + } + } + break; + case NV01_MEMORY_LIST_OBJECT: + { + RsClient *pClient; + + pMemoryInfo = NULL; + + status = serverGetClientUnderLock(&g_resServ, src_hClient, &pClient); + if (status != NV_OK) + { + return NV_ERR_INVALID_CLIENT; + } + + status = memGetByHandle(pClient, pAllocParams->hObject, &pMemoryInfo); + if (status != NV_OK) + { + return status; + } + src_pMemDesc = pMemoryInfo->pMemDesc; + + if (src_pMemDesc == NULL) + { + return NV_ERR_INVALID_CLASS; + } + + addressSpace = memdescGetAddressSpace(src_pMemDesc); + switch (addressSpace) + { + case ADDR_SYSMEM: + case ADDR_FBMEM: + break; + default: + return NV_ERR_INVALID_OBJECT; + } + + if (!memdescGetContiguity(src_pMemDesc, AT_GPU) && + ((src_pMemDesc->PageCount << RM_PAGE_SHIFT) < src_pMemDesc->Size)) + { + return NV_ERR_BUFFER_TOO_SMALL; + } + + /* + * get the client device memory info reference which will be used to + * retrieve the associated hardware resource information (pHwResource) + * for Win VMs + */ + if (src_hHwResHandle != 0) + { + RsClient *pHwResClient; + + status = serverGetClientUnderLock(&g_resServ, src_hHwResClient, &pHwResClient); + if (status == NV_OK) + { + status = memGetByHandleAndDevice(pHwResClient, src_hHwResHandle, + src_hHwResDevice, &pMemoryInfo); + } + if (status != NV_OK) + { + src_hHwResHandle = 0; + } + } + break; + } + default: + break; + } + + bContig = FLD_TEST_DRF(OS02, _FLAGS, _PHYSICALITY, _CONTIGUOUS, pAllocParams->flagsOs02); + memSize = pAllocParams->limit + 1; + + if (addressSpace == ADDR_SYSMEM) + { + NvU32 attr2 = 0; + + if ((src_pMemDesc != NULL) || bContig) + { + NV_ASSERT(0); + return NV_ERR_NOT_SUPPORTED; + } + + status = memdescCreate(&pMemDesc, pGpu, memSize, 0, + bContig, addressSpace, Cache, + MEMDESC_FLAGS_SKIP_RESOURCE_COMPUTE); + if (status != NV_OK) + { + return status; + } + + memdescSetFlag(pMemDesc, MEMDESC_FLAGS_GUEST_ALLOCATED, NV_TRUE); + + pMemDesc->PteAdjust = pAllocParams->pteAdjust; + memdescSetPteKind(pMemDesc, pAllocParams->format); + memdescSetGuestId(pMemDesc, pAllocParams->guestId); + + pPteArray = memdescGetPteArray(pMemDesc, AT_GPU); + + if (!portSafeMulU32(sizeof(NvU64), pAllocParams->pageCount, &result)) + { + memdescDestroy(pMemDesc); + return NV_ERR_INVALID_ARGUMENT; + } + + // copy in the pages + status = rmapiParamsCopyIn(NULL, + pPteArray, + pAllocParams->pageNumberList, + result, + bUserModeArgs); + if (status != NV_OK) + { + memdescDestroy(pMemDesc); + return status; + } + + if (RMCFG_MODULE_KERNEL_BUS) + { + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + + for (i = 0; i < pKernelBus->totalPciBars; ++i) + { + RmPhysAddr barOffset = pKernelBus->pciBars[i]; + NvU64 barSize = pKernelBus->pciBarSizes[i]; + + if ((pPteArray[0] >= barOffset >> RM_PAGE_SHIFT) && + (pPteArray[0] < (barOffset + barSize) >> RM_PAGE_SHIFT)) + { + /* + * For SYSMEM address space when creating descriptor for + * physical BAR range, mark the descriptor as CPU only. This + * access is generally done when NvWatch is enabled and we want + * to map physical BAR range in CPU addressable memory and + * these addresses are not used for DMA. + */ + memdescSetFlag(pMemDesc, MEMDESC_FLAGS_CPU_ONLY, NV_TRUE); + + if (i == 0) + memdescSetFlag(pMemDesc, MEMDESC_FLAGS_BAR0_REFLECT, NV_TRUE); + else if (i == 1) + memdescSetFlag(pMemDesc, MEMDESC_FLAGS_BAR1_REFLECT, NV_TRUE); + + break; + } + } + } + + // reformat the pages to addresses + for (i = pAllocParams->pageCount; i > 0;) + { + i--; + memdescSetPte(pMemDesc, AT_GPU, i, + pPteArray[i] << RM_PAGE_SHIFT); + } + + // this will fake a memory allocation at + // the OS driver interface level - and also set pMemDesc->Allocated + status = memdescAlloc(pMemDesc); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "*** Cannot fake guest sysmem allocation. status =0x%x\n", + status); + + memdescDestroy(pMemDesc); + return status; + } + + NvU32 os32Flags = 0; + NvU32 attr = 0; + NvBool bUseOs02flag = NV_FALSE; + + if (bUseOs02flag == NV_FALSE) + { + status = RmDeprecatedConvertOs02ToOs32Flags(pAllocParams->flagsOs02, &attr, &attr2, &os32Flags); + if (status != NV_OK) + { + memdescDestroy(pMemDesc); + return status; + } + + status = memConstructCommon(pMemory, NV01_MEMORY_SYSTEM, os32Flags, pMemDesc, + 0, NULL, attr, attr2, 0, 0, + NVOS32_MEM_TAG_NONE, (HWRESOURCE_INFO *)NULL); + } + else + { + if (FLD_TEST_DRF(OS02, _FLAGS, _ALLOC_USER_READ_ONLY, _YES, pAllocParams->flagsOs02)) + attr2 |= DRF_DEF(OS32, _ATTR2, _PROTECTION_USER, _READ_ONLY); + + status = memConstructCommon(pMemory, NV01_MEMORY_SYSTEM, 0, pMemDesc, + 0, NULL, 0, attr2, 0, 0, NVOS32_MEM_TAG_NONE, (HWRESOURCE_INFO *)NULL); + } + + if (status != NV_OK) + { + memdescDestroy(pMemDesc); + } + } + else if (addressSpace == ADDR_FBMEM) + { + NvU64 newBase; + NvU64 baseOffset = 0; + NvU64 trueLength; + NvU32 hwResId = 0; + NvU32 pageSize = 0; + RM_ATTR_PAGE_SIZE pageSizeAttr; + FB_ALLOC_INFO *pFbAllocInfo = NULL; + FB_ALLOC_PAGE_FORMAT *pFbAllocPageFormat = NULL; + HWRESOURCE_INFO *pHwResource = NULL; + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + Heap *pHeap = vidmemGetHeap(pGpu, hClient, NV_FALSE); + NvBool bCallingContextPlugin; + + // + // When guest RM client doesn't subscribe to MIG partition and requests for vidmem allocation + // vidmemGetHeap() returns NULL for heap. Hence, add below assert for validation. + // + NV_ASSERT_OR_RETURN((pHeap != NULL), NV_ERR_INVALID_STATE); + + // Must be of valid type, in FBMEM, one page for contig. + if ((pAllocParams->type >= NVOS32_NUM_MEM_TYPES) || + (bContig && (pAllocParams->pageCount > 1)) || + (!FLD_TEST_DRF(OS32, _ATTR, _LOCATION, _VIDMEM, pAllocParams->attr)) || + (pAllocParams->flags & (NVOS32_ALLOC_FLAGS_TURBO_CIPHER_ENCRYPTED | + NVOS32_ALLOC_FLAGS_ALIGNMENT_HINT | + NVOS32_ALLOC_FLAGS_ALIGNMENT_FORCE | + NVOS32_ALLOC_FLAGS_BANK_FORCE))) + { + return NV_ERR_INVALID_ARGUMENT; + } + + pAllocParams->flags |= (NVOS32_ALLOC_FLAGS_MEMORY_HANDLE_PROVIDED | + NVOS32_ALLOC_FLAGS_IGNORE_BANK_PLACEMENT); + + pFbAllocInfo = portMemAllocNonPaged(sizeof(FB_ALLOC_INFO)); + if (pFbAllocInfo == NULL) + { + NV_ASSERT(0); + status = NV_ERR_NO_MEMORY; + goto done_fbmem; + } + + pFbAllocPageFormat = portMemAllocNonPaged(sizeof(FB_ALLOC_PAGE_FORMAT)); + if (pFbAllocPageFormat == NULL) { + NV_ASSERT(0); + status = NV_ERR_NO_MEMORY; + goto done_fbmem; + } + + portMemSet(pFbAllocInfo, 0, sizeof(FB_ALLOC_INFO)); + portMemSet(pFbAllocPageFormat, 0, sizeof(FB_ALLOC_PAGE_FORMAT)); + pFbAllocInfo->pageFormat = pFbAllocPageFormat; + + if (src_pMemDesc != NULL) + { + trueLength = (src_pMemDesc->PteAdjust + + src_pMemDesc->Size); + baseOffset = memdescGetPhysAddr(src_pMemDesc, AT_GPU, 0); + } + else + { + NvU64 base = 0; + heapGetSize(pHeap, &trueLength); + heapGetBase(pHeap, &base); + trueLength = base + trueLength; + } + + // pAllocParams->hHwResHandle can be non-zero only for Win VMs and + // at least one of NVOS32_ATTR_COMPR or NVOS32_ATTR_ZCULL can be + // set in pAllocParams->attr only for Linux VMs + NV_ASSERT((pAllocParams->hHwResHandle == 0) || + !(pAllocParams->attr & (DRF_SHIFTMASK(NVOS32_ATTR_COMPR) | + DRF_SHIFTMASK(NVOS32_ATTR_ZCULL)))); + + status = memdescCreate(&pMemDesc, pGpu, memSize, 0, bContig, addressSpace, + Cache, MEMDESC_FLAGS_ALLOC_PER_SUBDEVICE_FB_BC_ONLY(pGpu, addressSpace)); + if (status != NV_OK) + { + goto done_fbmem; + } + pPteArray = memdescGetPteArray(pMemDesc, AT_GPU); + // copy in the pages + // copy in the pages + status = rmapiParamsCopyIn(NULL, + pPteArray, + pAllocParams->pageNumberList, + sizeof(NvU64) * pAllocParams->pageCount, + bUserModeArgs); + + if (status != NV_OK) + { + goto done_fbmem; + } + + if (bContig) + { + newBase = (pPteArray[0] << RM_PAGE_SHIFT) + pAllocParams->pteAdjust; + + if ((newBase + memSize) > trueLength) + { + NV_PRINTF(LEVEL_ERROR, + "Out of range contig memory at 0x%016llx of size 0x%016llx\n", + newBase, memSize); + status = NV_ERR_INVALID_ARGUMENT; + goto done_fbmem; + } + } + + // reformat the pages to addresses + for (i = pAllocParams->pageCount; i > 0;) + { + i--; + newBase = (pPteArray[i] << RM_PAGE_SHIFT); + if ((newBase + RM_PAGE_SIZE) > trueLength) + { + NV_PRINTF(LEVEL_ERROR, + "Out of range page address 0x%016llx\n", newBase); + status = NV_ERR_BUFFER_TOO_SMALL; + goto done_fbmem; + } + memdescSetPte(pMemDesc, AT_GPU, i, newBase + baseOffset); + } + + NV_ASSERT_OK_OR_GOTO(status, vgpuIsCallingContextPlugin(pMemDesc->pGpu, &bCallingContextPlugin), done_fbmem); + if (!bCallingContextPlugin) + memdescSetFlag(pMemDesc, MEMDESC_FLAGS_GUEST_ALLOCATED, NV_TRUE); + + memdescSetFlag(pMemDesc, MEMDESC_FLAGS_LIST_MEMORY, NV_TRUE); + + if (pAllocParams->attr & (DRF_SHIFTMASK(NVOS32_ATTR_COMPR) | + DRF_SHIFTMASK(NVOS32_ATTR_ZCULL))) + { + // + // Request any chip-specific resources for memory of this + // pAllocParams->type (e.g. tiles). This call may adjust size, pPitch + // and alignment as necessary. + // + pFbAllocInfo->pageFormat->type = pAllocParams->type; + pFbAllocInfo->hwResId = hwResId; + pFbAllocInfo->pad = 0; + pFbAllocInfo->alignPad = 0; + pFbAllocInfo->height = pAllocParams->height; + pFbAllocInfo->width = pAllocParams->width; + pFbAllocInfo->pitch = pAllocParams->pitch; + pFbAllocInfo->size = pAllocParams->size; + pFbAllocInfo->origSize = pAllocParams->size; + pFbAllocInfo->offset = ~0; + pFbAllocInfo->pageFormat->flags = pAllocParams->flags; + pFbAllocInfo->internalflags = 0; + pFbAllocInfo->pageFormat->attr = pAllocParams->attr; + pFbAllocInfo->retAttr = pAllocParams->attr; + pFbAllocInfo->pageFormat->attr2 = pAllocParams->attr2; + pFbAllocInfo->retAttr2 = pAllocParams->attr2; + pFbAllocInfo->format = pAllocParams->format; + pFbAllocInfo->comprCovg = pAllocParams->comprcovg; + pFbAllocInfo->zcullCovg = 0; + pFbAllocInfo->ctagOffset = pAllocParams->ctagOffset; + pFbAllocInfo->hClient = hClient; + pFbAllocInfo->hDevice = hParent; /* device */ + pFbAllocInfo->bIsKernelAlloc = NV_FALSE; + + // only a kernel client can request for a protected allocation + if (pFbAllocInfo->pageFormat->flags & NVOS32_ALLOC_FLAGS_ALLOCATE_KERNEL_PRIVILEGED) + { + pFbAllocInfo->bIsKernelAlloc = NV_TRUE; + } + + if ((pAllocParams->flags & NVOS32_ALLOC_FLAGS_ALIGNMENT_HINT) || + (pAllocParams->flags & NVOS32_ALLOC_FLAGS_ALIGNMENT_FORCE)) + { + pFbAllocInfo->align = pAllocParams->align; + } + else + { + pFbAllocInfo->align = RM_PAGE_SIZE; + } + + // Fetch RM page size + pageSize = memmgrDeterminePageSize(pMemoryManager, pFbAllocInfo->hClient, pFbAllocInfo->size, + pFbAllocInfo->format, pFbAllocInfo->pageFormat->flags, + &pFbAllocInfo->retAttr, &pFbAllocInfo->retAttr2); + + if (pageSize == 0) + { + status = NV_ERR_INVALID_STATE; + NV_PRINTF(LEVEL_ERROR, "memmgrDeterminePageSize failed\n"); + goto done_fbmem; + } + + // Fetch memory alignment + status = memmgrAllocDetermineAlignment_HAL(pGpu, pMemoryManager, &pFbAllocInfo->size, &pFbAllocInfo->align, + pFbAllocInfo->alignPad, pFbAllocInfo->pageFormat->flags, + pFbAllocInfo->retAttr, pFbAllocInfo->retAttr2, 0); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "memmgrAllocDetermineAlignment failed\n"); + goto done_fbmem; + } + + // + // Call into HAL to reserve any hardware resources for + // the specified memory type. + // If the alignment was changed due to a HW limitation, and the + // flag NVOS32_ALLOC_FLAGS_ALIGNMENT_FORCE is set, bad_argument + // will be passed back from the HAL + // + status = memmgrAllocHwResources(pGpu, pMemoryManager, pFbAllocInfo); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "memmgrAllocHwResources failure!\n"); + goto done_fbmem; + } + + // No need to check format if comptag allocation is not requested + if (!(pAllocParams->flags & NVOS32_ALLOC_FLAGS_SKIP_RESOURCE_ALLOC)) + { + NV_ASSERT(pFbAllocInfo->format == pAllocParams->format); + } + + NV_PRINTF(LEVEL_INFO, "fbAlloc for comptag successful!\n"); + + /* Create hwResource from pFbAllocInfo */ + pHwResource = portMemAllocNonPaged(sizeof(HWRESOURCE_INFO)); + if (pHwResource == NULL) + { + (void)memmgrFreeHwResources(pGpu, pMemoryManager, pFbAllocInfo); + status = NV_ERR_NO_MEMORY; + goto done_fbmem; + } + + portMemSet(pHwResource, 0x0, sizeof(HWRESOURCE_INFO)); + pHwResource->attr = pFbAllocInfo->retAttr; + pHwResource->attr2 = pFbAllocInfo->retAttr2; + pHwResource->comprCovg = pFbAllocInfo->comprCovg; + pHwResource->ctagOffset = pFbAllocInfo->ctagOffset; + pHwResource->hwResId = pFbAllocInfo->hwResId; + + NV_PRINTF(LEVEL_INFO, "memmgrAllocHwResources result\n"); + NV_PRINTF(LEVEL_INFO, " Attr:0x%x\n", + pFbAllocInfo->retAttr); + NV_PRINTF(LEVEL_INFO, " Attr2:0x%x\n", + pFbAllocInfo->retAttr2); + NV_PRINTF(LEVEL_INFO, " comprCovg:0x%x\n", + pFbAllocInfo->comprCovg); + NV_PRINTF(LEVEL_INFO, " zcullCovg:0x%x\n", + pFbAllocInfo->zcullCovg); + NV_PRINTF(LEVEL_INFO, " ctagOffset:0x%x\n", + pFbAllocInfo->ctagOffset); + NV_PRINTF(LEVEL_INFO, " hwResId:0x%x\n", + pFbAllocInfo->hwResId); + + hwResId = pFbAllocInfo->hwResId; + + // + // For Linux Guest, we allocate hardware resources on the host through + // NV01_MEMORY_LIST_OBJECT or NV01_MEMORY_LIST_FBMEM class objects. + // isGuestAllocated flag when set TRUE indicates that hardware resource + // is allocated for Linux Guest and we will free it in + // memDestructCommon. + // + pHwResource->isGuestAllocated = NV_TRUE; + } + else if (src_hHwResHandle != 0) + { + // obtaining hardware resources info for Win VMs + pHwResource = pMemoryInfo->pHwResource; + hwResId = pHwResource->hwResId; + } + + + pageSizeAttr = dmaNvos32ToPageSizeAttr(pAllocParams->attr, pAllocParams->attr2); + + switch (pageSizeAttr) + { + case RM_ATTR_PAGE_SIZE_4KB: + memdescSetPageSize(pMemDesc, AT_GPU, RM_PAGE_SIZE); + break; + case RM_ATTR_PAGE_SIZE_BIG: + memdescSetPageSize(pMemDesc, AT_GPU, RM_PAGE_SIZE_64K); + break; + case RM_ATTR_PAGE_SIZE_HUGE: + if (!kgmmuIsHugePageSupported(pKernelGmmu)) + { + NV_ASSERT(0); + status = NV_ERR_INVALID_ARGUMENT; + goto done_fbmem; + } + memdescSetPageSize(pMemDesc, AT_GPU, RM_PAGE_SIZE_HUGE); + break; + case RM_ATTR_PAGE_SIZE_512MB: + if (!kgmmuIsPageSize512mbSupported(pKernelGmmu)) + { + NV_ASSERT(0); + status = NV_ERR_INVALID_ARGUMENT; + goto done_fbmem; + } + memdescSetPageSize(pMemDesc, AT_GPU, RM_PAGE_SIZE_512M); + break; + case RM_ATTR_PAGE_SIZE_DEFAULT: + NV_PRINTF(LEVEL_INFO, "page size default doesn't have any impact \n"); + break; + case RM_ATTR_PAGE_SIZE_INVALID: + NV_PRINTF(LEVEL_INFO, "unexpected pageSizeAttr = 0x%x\n", pageSizeAttr); + status = NV_ERR_INVALID_STATE; + goto done_fbmem; + } + + status = memConstructCommon(pMemory, + NV01_MEMORY_LOCAL_USER, + 0, // flags + pMemDesc, + 0, // heapOwner + pHeap, + pAllocParams->attr, + pAllocParams->attr2, + 0, // pitch + pAllocParams->type, // type + NVOS32_MEM_TAG_NONE, + pHwResource); // pHwResource + if (status != NV_OK) + { + goto done_fbmem; + } + + if ((pHwResource != NULL) && (src_hHwResHandle == 0)) + { + portMemFree(pHwResource); + pHwResource = NULL; + } + + memdescSetPteKind(pMemory->pMemDesc, pAllocParams->format); + memdescSetHwResId(pMemory->pMemDesc, hwResId); + +done_fbmem: + if (status != NV_OK) + { + memdescDestroy(pMemDesc); + + if (src_hHwResHandle == 0) + { + portMemFree(pHwResource); + + /* release hwResId resources */ + portMemSet(pFbAllocInfo, 0, sizeof(FB_ALLOC_INFO)); + portMemSet(pFbAllocPageFormat, 0, sizeof(FB_ALLOC_PAGE_FORMAT)); + pFbAllocInfo->pageFormat = pFbAllocPageFormat; + pFbAllocInfo->pageFormat->type = pAllocParams->type; + pFbAllocInfo->hwResId = hwResId; + pFbAllocInfo->size = memSize; + + memmgrFreeHwResources(pGpu, pMemoryManager, pFbAllocInfo); + } + } + + portMemFree(pFbAllocPageFormat); + portMemFree(pFbAllocInfo); + } + else + { + status = NV_ERR_INVALID_CLASS; + } + return status; +} + +NvBool +memlistCanCopy_IMPL +( + MemoryList *pMemoryList +) +{ + return NV_TRUE; +} diff --git a/src/nvidia/src/kernel/mem_mgr/mem_multicast_fabric.c b/src/nvidia/src/kernel/mem_mgr/mem_multicast_fabric.c new file mode 100644 index 000000000..3cc184366 --- /dev/null +++ b/src/nvidia/src/kernel/mem_mgr/mem_multicast_fabric.c @@ -0,0 +1,1576 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/****************************************************************************** + * + * Description: + * This file contains the functions managing the memory multicast fabric + * + *****************************************************************************/ +#include "os/os.h" +#include "core/locks.h" +#include "nvport/nvport.h" +#include "rmapi/rs_utils.h" +#include "rmapi/rmapi_utils.h" +#include "compute/fabric.h" +#include "gpu/gpu.h" +#include "gpu/bus/kern_bus.h" +#include "gpu/mem_mgr/mem_desc.h" +#include "gpu/mem_mgr/mem_mgr.h" +#include "gpu/subdevice/subdevice.h" +#include "kernel/gpu/nvlink/kernel_nvlink.h" +#include "mem_mgr/fabric_vaspace.h" +#include "mem_mgr/mem_multicast_fabric.h" +#include "published/hopper/gh100/dev_mmu.h" + +#include "gpu/gpu_fabric_probe.h" + +static +NV_STATUS +_memMulticastFabricValidateAllocParams +( + NV00FD_ALLOCATION_PARAMETERS *pAllocParams +) +{ + // Only page size 512MB is supported + if (pAllocParams->pageSize != NV_MEMORY_MULTICAST_FABRIC_PAGE_SIZE_512M) + { + NV_PRINTF(LEVEL_ERROR, + "Unsupported pageSize: 0x%x. Only 512MB pagesize is supported\n", + pAllocParams->pageSize); + return NV_ERR_INVALID_ARGUMENT; + } + + // Alignment should be pageSize aligned + if (!NV_IS_ALIGNED64(pAllocParams->alignment, pAllocParams->pageSize)) + { + NV_PRINTF(LEVEL_ERROR, + "Alignment should be pageSize aligned\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + // AllocSize should be page size aligned + if (!NV_IS_ALIGNED64(pAllocParams->allocSize, pAllocParams->pageSize)) + { + NV_PRINTF(LEVEL_ERROR, + "AllocSize should be pageSize aligned\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + if (pAllocParams->numGpus == 0) + { + NV_PRINTF(LEVEL_ERROR, + "Number of GPUs to attach must be non-zero\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + // Allocation flags must be zero + if (pAllocParams->allocFlags != 0) + { + NV_PRINTF(LEVEL_ERROR, "allocFlags must be zero\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + return NV_OK; +} + +static +MEM_MULTICAST_FABRIC_DESCRIPTOR* +_memMulticastFabricDescriptorAllocUnderLock +( + MemoryMulticastFabric *pMemoryMulticastFabric, + NV00FD_ALLOCATION_PARAMETERS *pAllocParams +) +{ + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc; + + pMulticastFabricDesc = portMemAllocNonPaged(sizeof(MEM_MULTICAST_FABRIC_DESCRIPTOR)); + if (pMulticastFabricDesc == NULL) + return NULL; + + portMemSet(pMulticastFabricDesc, 0, sizeof(MEM_MULTICAST_FABRIC_DESCRIPTOR)); + + portAtomicExSetU64(&pMulticastFabricDesc->refCount, 1); + + listInit(&pMulticastFabricDesc->waitingClientsList, + portMemAllocatorGetGlobalNonPaged()); + + listInit(&pMulticastFabricDesc->attachMemInfoList, + portMemAllocatorGetGlobalNonPaged()); + + listInit(&pMulticastFabricDesc->gpuOsInfoList, + portMemAllocatorGetGlobalNonPaged()); + + portAtomicSetU32(&pMulticastFabricDesc->mcTeamStatus, NV_ERR_NOT_READY); + + portAtomicSetU32(&pMulticastFabricDesc->attachedGpusMask, 0); + + pMulticastFabricDesc->alignment = pAllocParams->alignment; + pMulticastFabricDesc->allocSize = pAllocParams->allocSize; + pMulticastFabricDesc->pageSize = pAllocParams->pageSize; + pMulticastFabricDesc->allocFlags = pAllocParams->allocFlags; + pMulticastFabricDesc->numMaxGpus = pAllocParams->numGpus; + + return pMulticastFabricDesc; +} + +static void +_memMulticastFabricDescriptorFlushClientsUnderLock +( + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc +) +{ + MEM_MULTICAST_FABRIC_CLIENT_INFO *pNode; + + while ((pNode = listHead(&pMulticastFabricDesc->waitingClientsList)) != NULL) + { + if (pNode->pOsEvent != NULL) + { + osSetEvent(NULL, pNode->pOsEvent); + NV_ASSERT_OK(osDereferenceObjectCount(pNode->pOsEvent)); + } + + listRemove(&pMulticastFabricDesc->waitingClientsList, pNode); + } + + return; +} + +static NV_STATUS +_memMulticastFabricDescriptorEnqueueWaitUnderLock +( + NvHandle hClient, + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, + NvP64 pOsEvent, + Memory *pMemory +) +{ + MEM_MULTICAST_FABRIC_CLIENT_INFO *pNode; + NvP64 pValidatedOsEvent = NULL; + NV_STATUS status; + + if (pOsEvent != NULL) + { + status = osUserHandleToKernelPtr(hClient, pOsEvent, &pValidatedOsEvent); + if (status != NV_OK) + return status; + } + + pNode = listAppendNew(&pMulticastFabricDesc->waitingClientsList); + if (pNode == NULL) + { + if (pOsEvent != NULL) + osDereferenceObjectCount(pValidatedOsEvent); + + return NV_ERR_NO_MEMORY; + } + + pNode->pOsEvent = pValidatedOsEvent; + pNode->pMemory = pMemory; + + // In case the multicast object's memdesc is ready, unblock clients waiting on it + if (pMulticastFabricDesc->bMemdescInstalled) + _memMulticastFabricDescriptorFlushClientsUnderLock(pMulticastFabricDesc); + + return NV_OK; +} + +static void +_memMulticastFabricDescriptorDequeueWaitUnderLock +( + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, + Memory *pMemory +) +{ + MEM_MULTICAST_FABRIC_CLIENT_INFO *pNode; + MEM_MULTICAST_FABRIC_CLIENT_INFO *pNodeNext; + + pNode = listHead(&pMulticastFabricDesc->waitingClientsList); + + // There can be multiple events per memory object, so delete all. + while (pNode != NULL) + { + pNodeNext = listNext(&pMulticastFabricDesc->waitingClientsList, pNode); + + if (pNode->pMemory == pMemory) + { + if (pNode->pOsEvent != NULL) + osDereferenceObjectCount(pNode->pOsEvent); + + listRemove(&pMulticastFabricDesc->waitingClientsList, pNode); + } + + pNode = pNodeNext; + } +} + +NV_STATUS +_memMulticastFabricGpuOsInfoAddUnderLock +( + MemoryMulticastFabric *pMemoryMulticastFabric, + RS_RES_CONTROL_PARAMS_INTERNAL *pParams +) +{ + NV00FD_CTRL_ATTACH_MEM_PARAMS *pAttachParams = pParams->pParams; + Subdevice *pSubdevice = NULL; + MEM_MULTICAST_FABRIC_GPU_OS_INFO *pNode; + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = \ + pMemoryMulticastFabric->pMulticastFabricDesc; + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + subdeviceGetByHandle(RES_GET_CLIENT(pMemoryMulticastFabric), + pAttachParams->hSubdevice, &pSubdevice)); + + if(!osMatchGpuOsInfo(GPU_RES_GET_GPU(pSubdevice), + pParams->secInfo.gpuOsInfo)) + { + return NV_ERR_INVALID_DEVICE; + } + + pNode = listAppendNew(&pMulticastFabricDesc->gpuOsInfoList); + if (pNode == NULL) + { + return NV_ERR_NO_MEMORY; + } + + pNode->gpuOsInfo = pParams->secInfo.gpuOsInfo; + + return NV_OK; +} + +static void +_memMulticastFabricGpuOsInfoRemoveUnderLock +( + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc +) +{ + MEM_MULTICAST_FABRIC_GPU_OS_INFO *pNode = NULL; + THREAD_STATE_NODE *pThreadNode = NULL; + THREAD_STATE_FREE_CALLBACK freeCallback; + + NV_ASSERT_OK(threadStateGetCurrent(&pThreadNode, NULL)); + + while ((pNode = listHead(&pMulticastFabricDesc->gpuOsInfoList)) != NULL) + { + freeCallback.pCb = osReleaseGpuOsInfo; + freeCallback.pCbData = (void *)pNode->gpuOsInfo; + + NV_ASSERT_OK(threadStateEnqueueCallbackOnFree(pThreadNode, &freeCallback)); + listRemove(&pMulticastFabricDesc->gpuOsInfoList, pNode); + } +} + +// +// The caller must have acquired the pMulticastFabricOpsMutex lock. +// GPU lock is acquired as needed. +// +static void +_memMulticastFabricRemoveFabricMapping +( + OBJGPU *pGpu, + MEMORY_DESCRIPTOR *pMemDesc +) +{ + FABRIC_VASPACE *pFabricVAS = dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); + NvU64 mcAddressBase = pMemDesc->_pteArray[0]; + + NV_ASSERT_OK(rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_MEM_FLA)); + + fabricvaspaceBatchFree(pFabricVAS, &mcAddressBase, 1, 1); + + rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); +} + +static void +_memMulticastFabricBatchRemoveFabricMappingUnderLock +( + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, + MEMORY_DESCRIPTOR *pMemDesc, + MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO *pEndNode +) +{ + MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO *pNode = NULL; + + for (pNode = listHead(&pMulticastFabricDesc->attachMemInfoList); + pNode != NULL; + pNode = listNext(&pMulticastFabricDesc->attachMemInfoList, pNode)) + { + if (pNode == pEndNode) + return; + + _memMulticastFabricRemoveFabricMapping(pNode->pGpu, pMemDesc); + } +} + +static void +_memMulticastFabricAttachMemInfoRemoveUnderLock +( + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, + MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO *pNode +) +{ + pMulticastFabricDesc->numAttachedGpus--; + + portAtomicAndU32(&pMulticastFabricDesc->attachedGpusMask, + ~(NVBIT32(pNode->pGpu->gpuInstance))); + + listRemove(&pMulticastFabricDesc->attachMemInfoList, pNode); +} + +static void +_memMulticastFabricDetachMemInfoUnderLock +( + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, + MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO *pNode +) +{ + RM_API *pRmApi; + OBJGPU *pGpu = pNode->pGpu; + FABRIC_VASPACE *pFabricVAS = \ + dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); + NvHandle hDupedPhysMem; + + pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + hDupedPhysMem = pNode->hDupedPhysMem; + + _memMulticastFabricAttachMemInfoRemoveUnderLock(pMulticastFabricDesc, pNode); + + NV_ASSERT_OK(pRmApi->Free(pRmApi, pFabricVAS->hClient, hDupedPhysMem)); +} + +// +// The caller must have acquired the pMulticastFabricOpsMutex lock. +// GPU lock is acquired as needed. +// +static void +_memMulticastFabricBatchDetachMemInfo +( + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc +) +{ + MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO *pNode = NULL; + + NV_ASSERT_OK(rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_MEM_FLA)); + + // + // _memMulticastFabricDetachMemInfoUnderLock internally trims down the + // attachMemInfoList where pNode is freed up + // + while ((pNode = listHead(&pMulticastFabricDesc->attachMemInfoList)) != NULL) + { + _memMulticastFabricDetachMemInfoUnderLock(pMulticastFabricDesc, pNode); + } + + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); +} + +NV_STATUS +_memMulticastFabricSendInbandTeamSetupRequestV1UnderLock +( + OBJGPU *pGpu, + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc +) +{ + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS *sendDataParams; + nvlink_inband_mc_team_setup_req_msg_t *pMcTeamSetupReqMsg = NULL; + nvlink_inband_mc_team_setup_req_t *pMcTeamSetupReq = NULL; + MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO *pNode; + NvU64 requestId; + NvU32 idx = 0; + NvU32 payloadSize; + NvU32 sendDataSize; + NV_STATUS status = NV_OK; + + sendDataParams = \ + (NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS *)portMemAllocNonPaged(sizeof(NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS)); + + if (sendDataParams == NULL) + return NV_ERR_NO_MEMORY; + + pMcTeamSetupReqMsg = \ + (nvlink_inband_mc_team_setup_req_msg_t *)&sendDataParams->buffer[0]; + + pMcTeamSetupReq = \ + (nvlink_inband_mc_team_setup_req_t *)&pMcTeamSetupReqMsg->mcTeamSetupReq; + + payloadSize = (NvU32)(sizeof(nvlink_inband_mc_team_setup_req_t) + \ + (sizeof(pMcTeamSetupReq->gpuHandles[0]) * pMulticastFabricDesc->numMaxGpus)); + + sendDataSize = (NvU32)(sizeof(nvlink_inband_msg_header_t) + payloadSize); + + NV_ASSERT((NvU32)sendDataSize <= sizeof(sendDataParams->buffer)); + + portMemSet(sendDataParams, 0, sendDataSize); + + pMcTeamSetupReq->mcAllocSize = pMulticastFabricDesc->allocSize; + pMcTeamSetupReq->numGpuHandles = pMulticastFabricDesc->numMaxGpus; + + for (pNode = listHead(&pMulticastFabricDesc->attachMemInfoList); + pNode != NULL; + pNode = listNext(&pMulticastFabricDesc->attachMemInfoList, pNode)) + pMcTeamSetupReq->gpuHandles[idx++] = pNode->gpuProbeHandle; + + NV_ASSERT(idx == pMcTeamSetupReq->numGpuHandles); + + sendDataParams->dataSize = sendDataSize; + + status = fabricInitInbandMsgHdr(&pMcTeamSetupReqMsg->msgHdr, + NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_REQ, + payloadSize); + + if (status != NV_OK) + goto done; + + requestId = pMcTeamSetupReqMsg->msgHdr.requestId; + + status = fabricMulticastSetupCacheInsertUnderLock_IMPL(pFabric, + requestId, + pMulticastFabricDesc); + if (status != NV_OK) + goto done; + + status = knvlinkSendInbandData(pGpu, GPU_GET_KERNEL_NVLINK(pGpu), sendDataParams); + if (status != NV_OK) + { + fabricMulticastSetupCacheDeleteUnderLock_IMPL(pFabric, requestId); + goto done; + } + + pMulticastFabricDesc->bInbandReqInProgress = NV_TRUE; + pMulticastFabricDesc->inbandReqId = requestId; + +done: + portMemFree(sendDataParams); + + return status; +} + +NV_STATUS +_memMulticastFabricSendInbandTeamReleaseRequestV1UnderLock +( + OBJGPU *pGpu, + NvU64 mcTeamHandle +) +{ + NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS *sendDataParams; + nvlink_inband_mc_team_release_req_msg_t *pMcTeamReleaseReqMsg = NULL; + nvlink_inband_mc_team_release_req_t *pMcTeamReleaseReq = NULL; + NvU32 payloadSize; + NvU32 sendDataSize; + NV_STATUS status = NV_OK; + + sendDataParams = \ + (NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS *)portMemAllocNonPaged(sizeof(NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS)); + + if (sendDataParams == NULL) + return NV_ERR_NO_MEMORY; + + pMcTeamReleaseReqMsg = \ + (nvlink_inband_mc_team_release_req_msg_t *)&sendDataParams->buffer[0]; + + pMcTeamReleaseReq = \ + (nvlink_inband_mc_team_release_req_t *)&pMcTeamReleaseReqMsg->mcTeamReleaseReq; + + payloadSize = (NvU32)(sizeof(nvlink_inband_mc_team_release_req_t)); + + sendDataSize = (NvU32)(sizeof(nvlink_inband_msg_header_t) + payloadSize); + + portMemSet(sendDataParams, 0, sendDataSize); + + pMcTeamReleaseReq->mcTeamHandle = mcTeamHandle; + + status = fabricInitInbandMsgHdr(&pMcTeamReleaseReqMsg->msgHdr, + NVLINK_INBAND_MSG_TYPE_MC_TEAM_RELEASE_REQ, + payloadSize); + if (status != NV_OK) + goto done; + + sendDataParams->dataSize = sendDataSize; + + status = knvlinkSendInbandData(pGpu, GPU_GET_KERNEL_NVLINK(pGpu), sendDataParams); + +done: + portMemFree(sendDataParams); + + return status; +} + +// +// The caller must have acquired the pMulticastFabricOpsMutex lock. +// GPU lock is acquired as needed. +// +NV_STATUS +_memMulticastFabricSendInbandTeamSetupRequest +( + OBJGPU *pGpu, + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc +) +{ + NvU64 fmCaps; + NV_STATUS status = NV_OK; + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_MEM_FLA)); + + status = gpuFabricProbeGetfmCaps(pGpu->pGpuFabricProbeInfo, &fmCaps); + if (status != NV_OK) + goto done; + + if (!(fmCaps & NVLINK_INBAND_FM_CAPS_MC_TEAM_SETUP_V1)) + { + status = NV_ERR_NOT_SUPPORTED; + goto done; + } + + status = _memMulticastFabricSendInbandTeamSetupRequestV1UnderLock(pGpu, + pMulticastFabricDesc); + +done: + rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); + + return status; +} + +NV_STATUS +_memMulticastFabricSendInbandTeamReleaseRequest +( + OBJGPU *pGpu, + NvU64 mcTeamHandle +) +{ + NvU64 fmCaps; + NV_STATUS status = NV_OK; + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_MEM_FLA)); + + status = gpuFabricProbeGetfmCaps(pGpu->pGpuFabricProbeInfo, &fmCaps); + if (status != NV_OK) + goto done; + + if (!(fmCaps & NVLINK_INBAND_FM_CAPS_MC_TEAM_RELEASE_V1)) + { + status = NV_ERR_NOT_SUPPORTED; + goto done; + } + + status = _memMulticastFabricSendInbandTeamReleaseRequestV1UnderLock(pGpu, + mcTeamHandle); + +done: + rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); + + return status; +} + +NV_STATUS +_memMulticastFabricSendInbandRequestUnderLock +( + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, + MEM_MULTICAST_FABRIC_REQUEST_TYPE requestType +) +{ + NV_STATUS status = NV_OK; + OBJGPU *pGpu; + + // + // TODO: Implement the randomization of pGpu to be used for the inband + // communication. Currently we pick the first pGpu in the attachMemInfoList + // to send the inband request. + // + + pGpu = listHead(&pMulticastFabricDesc->attachMemInfoList)->pGpu; + + switch (requestType) + { + case MEM_MULTICAST_FABRIC_TEAM_SETUP_REQUEST: + status = _memMulticastFabricSendInbandTeamSetupRequest(pGpu, + pMulticastFabricDesc); + break; + case MEM_MULTICAST_FABRIC_TEAM_RELEASE_REQUEST: + status = _memMulticastFabricSendInbandTeamReleaseRequest(pGpu, + pMulticastFabricDesc->mcTeamHandle); + break; + default: + status = NV_ERR_NOT_SUPPORTED; + break; + } + + return status; +} + +static void +_memMulticastFabricDescriptorFreeUnderLock +( + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc +) +{ + if (pMulticastFabricDesc == NULL) + return; + + if (portAtomicExDecrementU64(&pMulticastFabricDesc->refCount) == 0) + { + if (pMulticastFabricDesc->pMemDesc != NULL) + { + NV_ASSERT(pMulticastFabricDesc->bMemdescInstalled); + + _memMulticastFabricBatchRemoveFabricMappingUnderLock(pMulticastFabricDesc, + pMulticastFabricDesc->pMemDesc, + NULL); + _memMulticastFabricSendInbandRequestUnderLock(pMulticastFabricDesc, + MEM_MULTICAST_FABRIC_TEAM_RELEASE_REQUEST); + } + + if (pMulticastFabricDesc->bInbandReqInProgress) + { + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + OS_WAIT_QUEUE *pWq; + THREAD_STATE_NODE *pThreadNode = NULL; + THREAD_STATE_FREE_CALLBACK freeCallback; + + fabricMulticastSetupCacheDeleteUnderLock_IMPL(pFabric, + pMulticastFabricDesc->inbandReqId); + + NV_ASSERT_OK(osAllocWaitQueue(&pWq)); + + if (pWq != NULL) + { + NV_ASSERT_OK(fabricMulticastCleanupCacheInsertUnderLock_IMPL(pFabric, + pMulticastFabricDesc->inbandReqId, + pWq)); + + NV_ASSERT_OK(threadStateGetCurrent(&pThreadNode, NULL)); + + freeCallback.pCb = fabricMulticastWaitOnTeamCleanupCallback; + freeCallback.pCbData = (void *)pMulticastFabricDesc->inbandReqId; + + NV_ASSERT_OK(threadStateEnqueueCallbackOnFree(pThreadNode, &freeCallback)); + } + } + + _memMulticastFabricGpuOsInfoRemoveUnderLock(pMulticastFabricDesc); + + NV_ASSERT(listCount(&pMulticastFabricDesc->gpuOsInfoList) == 0); + listDestroy(&pMulticastFabricDesc->gpuOsInfoList); + + _memMulticastFabricBatchDetachMemInfo(pMulticastFabricDesc); + + NV_ASSERT(pMulticastFabricDesc->numAttachedGpus == 0); + NV_ASSERT(portAtomicOrU32(&pMulticastFabricDesc->attachedGpusMask, 0) == 0); + NV_ASSERT(listCount(&pMulticastFabricDesc->attachMemInfoList) == 0); + listDestroy(&pMulticastFabricDesc->attachMemInfoList); + + NV_ASSERT(listCount(&pMulticastFabricDesc->waitingClientsList) == 0); + listDestroy(&pMulticastFabricDesc->waitingClientsList); + + memdescDestroy(pMulticastFabricDesc->pMemDesc); + + portMemFree(pMulticastFabricDesc); + } +} + +NV_STATUS +_memMulticastFabricConstructUnderLock +( + MemoryMulticastFabric *pMemoryMulticastFabric, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + Memory *pMemory = staticCast(pMemoryMulticastFabric, Memory); + NV00FD_ALLOCATION_PARAMETERS *pAllocParams = pParams->pAllocParams; + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc; + NV_STATUS status = NV_OK; + + pMulticastFabricDesc = _memMulticastFabricDescriptorAllocUnderLock(pMemoryMulticastFabric, + pAllocParams); + + if (pMulticastFabricDesc == NULL) + return NV_ERR_NO_MEMORY; + + status = _memMulticastFabricDescriptorEnqueueWaitUnderLock(pParams->hClient, + pMulticastFabricDesc, + pAllocParams->pOsEvent, + pMemory); + if (status != NV_OK) + goto fail; + + pMemoryMulticastFabric->pMulticastFabricDesc = pMulticastFabricDesc; + + return NV_OK; + +fail: + _memMulticastFabricDescriptorFreeUnderLock(pMulticastFabricDesc); + + return status; +} + +NV_STATUS +_memMulticastFabricAttachMemInfoAddUnderLock +( + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, + OBJGPU *pGpu, + NV00FD_CTRL_ATTACH_MEM_PARAMS *pParams, + MEMORY_DESCRIPTOR *pPhysMemDesc, + NvHandle hDupedPhysMem, + NvU64 gpuProbeHandle, + MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO **pAttachMemNode +) +{ + MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO *pNode; + MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO *pNodeItr; + + for (pNodeItr = listHead(&pMulticastFabricDesc->attachMemInfoList); + pNodeItr != NULL; + pNodeItr = listNext(&pMulticastFabricDesc->attachMemInfoList, pNodeItr)) + { + if (pNodeItr->pGpu == pGpu) + { + NV_PRINTF(LEVEL_ERROR, "GPU %x has already attached to this multicast object\n", + pGpu->gpuInstance); + return NV_ERR_IN_USE; + } + } + + pNode = listAppendNew(&pMulticastFabricDesc->attachMemInfoList); + if (pNode == NULL) + return NV_ERR_NO_MEMORY; + + pNode->offset = pParams->offset; + pNode->mapOffset = pParams->mapOffset; + pNode->mapLength = pParams->mapLength; + pNode->flags = pParams->flags; + pNode->pGpu = pGpu; + pNode->pPhysMemDesc = pPhysMemDesc; + pNode->hDupedPhysMem = hDupedPhysMem; + pNode->gpuProbeHandle = gpuProbeHandle; + + portAtomicOrU32(&pMulticastFabricDesc->attachedGpusMask, + NVBIT32(pGpu->gpuInstance)); + + pMulticastFabricDesc->numAttachedGpus++; + + *pAttachMemNode = pNode; + + return NV_OK; +} + +// +// The caller must have acquired the pMulticastFabricOpsMutex lock. +// GPU lock is acquired as needed. +// +NV_STATUS +_memMulticastFabricSetupFabricMapping +( + OBJGPU *pGpu, + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, + MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO *pAttachMemInfo, + MEMORY_DESCRIPTOR *pMemDesc +) +{ + FABRIC_VASPACE *pFabricVAS = NULL; + VAS_ALLOC_FLAGS flags = {0}; + NV_STATUS status = NV_OK; + NvU64 physMemPageSize; + NvU64 mcAddressBase = pMemDesc->_pteArray[0]; + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_MEM_FLA)); + + pFabricVAS = dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); + + physMemPageSize = memdescGetPageSize(pAttachMemInfo->pPhysMemDesc, AT_GPU); + + status = fabricvaspaceAllocMulticast(pFabricVAS, physMemPageSize, + pMulticastFabricDesc->alignment, + flags, + mcAddressBase, + pMulticastFabricDesc->allocSize); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Fabric VA space alloc failed! for GPU %x\n", + pGpu->gpuInstance); + goto releaseGpuLock; + } + + // + // For now MCFLA code assumes zero fabric offset. When a non-zero fabric + // offset supported, revisit map/unmap paths. + // + status = fabricvaspaceMapPhysMemdesc(pFabricVAS, + pMemDesc, + 0, + pAttachMemInfo->pPhysMemDesc, + pAttachMemInfo->mapOffset, + pAttachMemInfo->mapLength, + 0); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to map MC FLA at the given physical offset for GPU %x\n", + pGpu->gpuInstance); + goto freeFabricVa; + } + + // + // TODO: Handle the case to map remaining MC FLA range + // to dummy pages when physMemSize < mcAllocSize + // + + rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); + + return NV_OK; + +freeFabricVa: + fabricvaspaceBatchFree(pFabricVAS, &mcAddressBase, 1, 1); + +releaseGpuLock: + rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); + + return status; +} + +NV_STATUS +_memMulticastFabricBatchSetupFabricMappingUnderLock +( + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, + MEMORY_DESCRIPTOR *pMemDesc +) +{ + MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO *pNode = NULL; + NV_STATUS status = NV_OK; + + for (pNode = listHead(&pMulticastFabricDesc->attachMemInfoList); + pNode != NULL; + pNode = listNext(&pMulticastFabricDesc->attachMemInfoList, pNode)) + { + status = _memMulticastFabricSetupFabricMapping(pNode->pGpu, pMulticastFabricDesc, + pNode, pMemDesc); + if (status != NV_OK) + goto batchRemoveMapping; + } + + return NV_OK; + +batchRemoveMapping: + _memMulticastFabricBatchRemoveFabricMappingUnderLock(pMulticastFabricDesc, + pMemDesc, pNode); + + return status; +} + +NV_STATUS +_memMulticastFabricCreateMemDescUnderLock +( + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, + NvU64 mcAddressBase, + MEMORY_DESCRIPTOR **ppMemDesc +) +{ + NV_STATUS status; + MEMORY_DESCRIPTOR *pTempMemDesc = NULL; + + status = memdescCreate(&pTempMemDesc, NULL, pMulticastFabricDesc->allocSize, + 0, NV_TRUE, ADDR_FABRIC_MC, NV_MEMORY_UNCACHED, + MEMDESC_FLAGS_NONE); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to allocate memory descriptor for multicast object\n"); + return status; + } + + memdescSetPte(pTempMemDesc, AT_GPU, 0, mcAddressBase); + + memdescSetPageSize(pTempMemDesc, AT_GPU, pMulticastFabricDesc->pageSize); + + pTempMemDesc->_pteKind = NV_MMU_PTE_KIND_SMSKED_MESSAGE; + + memdescSetFlag(pTempMemDesc, MEMDESC_FLAGS_SET_KIND, NV_TRUE); + + memdescSetGpuCacheAttrib(pTempMemDesc, NV_MEMORY_UNCACHED); + + *ppMemDesc = pTempMemDesc; + + return NV_OK; +} + +void +_memMulticastFabricInstallMemDescUnderLock +( + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, + MEMORY_DESCRIPTOR *pMemDesc, + NvU64 mcTeamHandle, + NV_STATUS status +) +{ + NV_ASSERT(pMulticastFabricDesc->pMemDesc == NULL); + + pMulticastFabricDesc->pMemDesc = pMemDesc; + pMulticastFabricDesc->bMemdescInstalled = NV_TRUE; + pMulticastFabricDesc->mcTeamHandle = mcTeamHandle; + + portAtomicMemoryFenceStore(); + + portAtomicSetU32(&pMulticastFabricDesc->mcTeamStatus, status); + + portAtomicMemoryFenceStore(); + + _memMulticastFabricDescriptorFlushClientsUnderLock(pMulticastFabricDesc); +} + +// +// TODO: This function will be invoked as part of the FM inband +// response handling once inband integration is complete. +// +NV_STATUS +_memMulticastFabricAttachMemPostProcessorUnderLock +( + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, + NV_STATUS mcTeamStatus, + NvU64 mcTeamHandle, + NvU64 mcAddressBase, + NvU64 mcAddressSize +) +{ + NV_STATUS status = mcTeamStatus; + MEMORY_DESCRIPTOR *pMemDesc = NULL; + + // + // FM is never expected to return NV_ERR_NOT_READY + // as part of the inband response. + // + NV_ASSERT(mcTeamStatus != NV_ERR_NOT_READY); + + if (mcTeamStatus != NV_OK) + goto installMemDesc; + + if (mcAddressSize < pMulticastFabricDesc->allocSize) + { + NV_PRINTF(LEVEL_ERROR, + "Insufficient mcAddressSize returned from Fabric Manager\n"); + status = NV_ERR_INSUFFICIENT_RESOURCES; + goto installMemDesc; + } + + if (!NV_IS_ALIGNED64(mcAddressBase, NV_MEMORY_MULTICAST_FABRIC_PAGE_SIZE_512M)) + { + NV_PRINTF(LEVEL_ERROR, + "Insufficient mcAddressSize returned from Fabric Manager\n"); + status = NV_ERR_INVALID_ADDRESS; + goto installMemDesc; + } + + status = _memMulticastFabricCreateMemDescUnderLock(pMulticastFabricDesc, + mcAddressBase, &pMemDesc); + if (status != NV_OK) + goto installMemDesc; + + status = _memMulticastFabricBatchSetupFabricMappingUnderLock(pMulticastFabricDesc, + pMemDesc); + if (status != NV_OK) + goto cleanupMemdesc; + + goto installMemDesc; + +cleanupMemdesc: + memdescDestroy(pMemDesc); + pMemDesc = NULL; + +installMemDesc: + _memMulticastFabricInstallMemDescUnderLock(pMulticastFabricDesc, + pMemDesc, + mcTeamHandle, + status); + if ((status != NV_OK) && (mcTeamStatus == NV_OK)) + _memMulticastFabricSendInbandRequestUnderLock(pMulticastFabricDesc, + MEM_MULTICAST_FABRIC_TEAM_RELEASE_REQUEST); + + return status; +} + +void +_memorymulticastfabricDestructUnderLock +( + MemoryMulticastFabric *pMemoryMulticastFabric +) +{ + Memory *pMemory = staticCast(pMemoryMulticastFabric, Memory); + + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = \ + pMemoryMulticastFabric->pMulticastFabricDesc; + + memDestructCommon(pMemory); + + _memMulticastFabricDescriptorDequeueWaitUnderLock(pMulticastFabricDesc, pMemory); + + _memMulticastFabricDescriptorFreeUnderLock(pMulticastFabricDesc); +} + +void memorymulticastfabricTeamSetupResponseCallback +( + OBJGPU *pGpu, + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pInbandRcvParams +) +{ + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + nvlink_inband_mc_team_setup_rsp_msg_t *pMcTeamSetupRspMsg; + nvlink_inband_mc_team_setup_rsp_t *pMcTeamSetupRsp; + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc; + NvU64 requestId; + NV_STATUS mcTeamStatus; + NvU64 mcTeamHandle = 0; + NvU64 mcAddressBase = 0; + NvU64 mcAddressSize = 0; + NvU8 *pRsvd = NULL; + + NV_ASSERT(pInbandRcvParams != NULL); + + pMcTeamSetupRspMsg = \ + (nvlink_inband_mc_team_setup_rsp_msg_t *)&pInbandRcvParams->data[0]; + + pMcTeamSetupRsp = \ + (nvlink_inband_mc_team_setup_rsp_t *)&pMcTeamSetupRspMsg->mcTeamSetupRsp; + + requestId = pMcTeamSetupRspMsg->msgHdr.requestId; + + mcTeamStatus = pMcTeamSetupRspMsg->msgHdr.status; + + if (mcTeamStatus == NV_OK) + { + mcTeamHandle = pMcTeamSetupRsp->mcTeamHandle; + mcAddressBase = pMcTeamSetupRsp->mcAddressBase; + mcAddressSize = pMcTeamSetupRsp->mcAddressSize; + + // Make sure that the reserved fields are initialized to 0 + pRsvd = &pMcTeamSetupRsp->reserved[0]; + + NV_ASSERT((pRsvd[0] == 0) && portMemCmp(pRsvd, pRsvd + 1, + (sizeof(pMcTeamSetupRsp->reserved) - 1)) == 0); + } + + fabricMulticastFabricOpsMutexAcquire(pFabric); + + pMulticastFabricDesc = \ + fabricMulticastSetupCacheGetUnderLock_IMPL(pFabric, requestId); + + if (pMulticastFabricDesc != NULL) + { + pMulticastFabricDesc->bInbandReqInProgress = NV_FALSE; + + pMulticastFabricDesc->inbandReqId = 0; + + fabricMulticastSetupCacheDeleteUnderLock_IMPL(pFabric, requestId); + + (void)_memMulticastFabricAttachMemPostProcessorUnderLock(pMulticastFabricDesc, + mcTeamStatus, + mcTeamHandle, + mcAddressBase, + mcAddressSize); + } + else + { + OS_WAIT_QUEUE *pWq; + + if (mcTeamStatus == NV_OK) + (void)_memMulticastFabricSendInbandTeamReleaseRequest(pGpu, + mcTeamHandle); + + // + // Check if there is any thread waiting for team release and + // wake it up. + // + // The multicast fabric descriptor could have undergone the + // destruct sequence while an inband team setup request was in + // progress with FM. + // + // In such a scenario the last thread to free the multicast + // descriptor is put to sleep until the team setup response + // is received and a subsequent team release request is sent. + // + + pWq = (OS_WAIT_QUEUE *)fabricMulticastCleanupCacheGetUnderLock_IMPL(pFabric, + requestId); + + if (pWq != NULL) + osWakeUp(pWq); + } + + fabricMulticastFabricOpsMutexRelease(pFabric); +} + +NV_STATUS +memorymulticastfabricConstruct_IMPL +( + MemoryMulticastFabric *pMemoryMulticastFabric, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + NV00FD_ALLOCATION_PARAMETERS *pAllocParams = pParams->pAllocParams; + NV_STATUS status = NV_OK; + OBJSYS *pSys = SYS_GET_INSTANCE(); + + if (!pSys->bMulticastFlaEnabled) + return NV_ERR_NOT_SUPPORTED; + + if (RS_IS_COPY_CTOR(pParams)) + { + return memorymulticastfabricCopyConstruct_IMPL(pMemoryMulticastFabric, + pCallContext, + pParams); + } + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, _memMulticastFabricValidateAllocParams(pAllocParams)); + + fabricMulticastFabricOpsMutexAcquire(pFabric); + + status = _memMulticastFabricConstructUnderLock(pMemoryMulticastFabric, + pCallContext, + pParams); + + fabricMulticastFabricOpsMutexRelease(pFabric); + + return status; +} + +NV_STATUS +memorymulticastfabricCtrlAttachMem_IMPL +( + MemoryMulticastFabric *pMemoryMulticastFabric, + NV00FD_CTRL_ATTACH_MEM_PARAMS *pParams +) +{ + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = \ + pMemoryMulticastFabric->pMulticastFabricDesc; + NV_STATUS status = NV_OK; + NvHandle hClient = RES_GET_CLIENT_HANDLE(pMemoryMulticastFabric); + RsResourceRef *pPhysMemRef = NULL; + MEMORY_DESCRIPTOR *pPhysMemDesc = NULL; + Subdevice *pSubdevice = NULL; + OBJGPU *pGpu = NULL; + FABRIC_VASPACE *pFabricVAS = NULL; + RM_API *pRmApi; + NvHandle hDupedPhysMem = 0; + NvU64 physMemPageSize; + NvU64 physMemSize; + MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO *pAttachMemNode = NULL; + NvU64 gpuProbeHandle = 0; + + // Check if the Multicast FLA object has any additional slots for GPUs + if (pMulticastFabricDesc->numAttachedGpus == pMulticastFabricDesc->numMaxGpus) + { + NV_PRINTF(LEVEL_ERROR, + "Max no. of GPUs for this multicast object have already attached!\n"); + return NV_ERR_INVALID_OPERATION; + } + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + subdeviceGetByHandle(RES_GET_CLIENT(pMemoryMulticastFabric), + pParams->hSubdevice, &pSubdevice)); + + pGpu = GPU_RES_GET_GPU(pSubdevice); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_MEM_FLA)); + + pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + if (RMCFG_FEATURE_PLATFORM_WINDOWS || + IS_VIRTUAL(pGpu)) + { + NV_PRINTF(LEVEL_ERROR, + "Multicast attach not supported on Windows/CC/vGPU modes\n"); + status = NV_ERR_NOT_SUPPORTED; + goto fail; + } + + status = gpuFabricProbeGetGpuFabricHandle(pGpu->pGpuFabricProbeInfo, &gpuProbeHandle); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Attaching GPU does not have a valid probe handle\n"); + goto fail; + } + + status = serverutilGetResourceRef(hClient, pParams->hMemory, &pPhysMemRef); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to get resource in resserv for physmem handle\n"); + goto fail; + } + + pFabricVAS = dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); + if (pFabricVAS == NULL) + { + NV_PRINTF(LEVEL_ERROR, + "Fabric vaspace object not available for GPU %x\n", + pGpu->gpuInstance); + status = NV_ERR_NOT_SUPPORTED; + goto fail; + } + + pPhysMemDesc = (dynamicCast(pPhysMemRef->pResource, Memory))->pMemDesc; + + if ((memdescGetAddressSpace(pPhysMemDesc) != ADDR_FBMEM) || + (pGpu != pPhysMemDesc->pGpu)) + { + NV_PRINTF(LEVEL_ERROR, "Invalid physical physmem handle passed\n"); + status = NV_ERR_INVALID_ARGUMENT; + goto fail; + } + + physMemPageSize = memdescGetPageSize(pPhysMemDesc, AT_GPU); + + physMemSize = memdescGetSize(pPhysMemDesc); + + if (physMemPageSize != RM_PAGE_SIZE_HUGE) + { + NV_PRINTF(LEVEL_ERROR, "Physical physmem page size should be 2MB\n"); + status = NV_ERR_INVALID_ARGUMENT; + goto fail; + } + + if ((!NV_IS_ALIGNED64(pParams->mapOffset, physMemPageSize)) || + (!NV_IS_ALIGNED64(pParams->mapLength, physMemPageSize)) || + (pParams->mapOffset >= physMemSize) || + (pParams->mapLength > (physMemSize - pParams->mapOffset))) + { + NV_PRINTF(LEVEL_ERROR, + "Invalid mapOffset passed for the physical physmem handle\n"); + status = NV_ERR_INVALID_OFFSET; + goto fail; + } + + if (pParams->offset != 0) + { + NV_PRINTF(LEVEL_ERROR, "offset passed for attach mem must be zero\n"); + status = NV_ERR_INVALID_OFFSET; + goto fail; + } + + if (pParams->mapLength == 0) + { + NV_PRINTF(LEVEL_ERROR, "Invalid mapLength passed\n"); + status = NV_ERR_INVALID_ARGUMENT; + goto fail; + } + + if ((pParams->offset >= pMulticastFabricDesc->allocSize) || + (pParams->mapLength > (pMulticastFabricDesc->allocSize - pParams->offset))) + { + NV_PRINTF(LEVEL_ERROR, "Invalid multicast offset passed\n"); + status = NV_ERR_INVALID_OFFSET; + goto fail; + } + + if (pParams->flags != 0) + { + NV_PRINTF(LEVEL_ERROR, "flags passed for attach mem must be zero\n"); + status = NV_ERR_INVALID_ARGUMENT; + goto fail; + } + + status = pRmApi->DupObject(pRmApi, pFabricVAS->hClient, pFabricVAS->hDevice, + &hDupedPhysMem, hClient, pParams->hMemory, 0); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to dup physical physical memory handle\n"); + goto fail; + } + + status = _memMulticastFabricAttachMemInfoAddUnderLock(pMulticastFabricDesc, + pGpu, pParams, pPhysMemDesc, hDupedPhysMem, gpuProbeHandle, + &pAttachMemNode); + + rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); + + if (status != NV_OK) + goto addInfoFail; + + if (pMulticastFabricDesc->numAttachedGpus == pMulticastFabricDesc->numMaxGpus) + { + status = _memMulticastFabricSendInbandRequestUnderLock(pMulticastFabricDesc, + MEM_MULTICAST_FABRIC_TEAM_SETUP_REQUEST); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Inband request submission to FM for Multicast Team Setup failed!\n"); + goto inbandFail; + } + } + + return NV_OK; + +goto inbandFail; +inbandFail: + _memMulticastFabricAttachMemInfoRemoveUnderLock(pMulticastFabricDesc, pAttachMemNode); + +addInfoFail: + // Take all GPU lock. This is enforced by the vidmem class + NV_ASSERT_OK(rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_MEM_FLA)); + NV_ASSERT(pRmApi->Free(pRmApi, pFabricVAS->hClient, hDupedPhysMem) == NV_OK); + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + +fail: + if (rmDeviceGpuLockIsOwner(pGpu->gpuInstance)) + rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); + + return status; +} + +void +memorymulticastfabricDestruct_IMPL +( + MemoryMulticastFabric *pMemoryMulticastFabric +) +{ + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + + fabricMulticastFabricOpsMutexAcquire(pFabric); + + _memorymulticastfabricDestructUnderLock(pMemoryMulticastFabric); + + fabricMulticastFabricOpsMutexRelease(pFabric); +} + +NvBool +memorymulticastfabricCanCopy_IMPL +( + MemoryMulticastFabric *pMemoryMulticastFabric +) +{ + return NV_TRUE; +} + +// +// memorymulticastfabricCopyConstruct_IMPL does not take +// the multicast fabric mutex lock as it can be invoked +// with the GPU locks held which would result in a lock +// inversion. Hence we resort to portAtomics here. +// +NV_STATUS +memorymulticastfabricCopyConstruct_IMPL +( + MemoryMulticastFabric *pMemoryMulticastFabric, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc; + + MemoryMulticastFabric *pSourceMemoryMulticastFabric = + dynamicCast(pParams->pSrcRef->pResource, MemoryMulticastFabric); + + pMulticastFabricDesc = pSourceMemoryMulticastFabric->pMulticastFabricDesc; + + pMemoryMulticastFabric->pMulticastFabricDesc = pMulticastFabricDesc; + + portAtomicExIncrementU64(&pMulticastFabricDesc->refCount); + + return NV_OK; +} + +NV_STATUS +memorymulticastfabricCtrlGetInfo_IMPL +( + MemoryMulticastFabric *pMemoryMulticastFabric, + NV00FD_CTRL_GET_INFO_PARAMS *pParams +) +{ + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc; + + pMulticastFabricDesc = pMemoryMulticastFabric->pMulticastFabricDesc; + + pParams->alignment = pMulticastFabricDesc->alignment; + pParams->allocSize = pMulticastFabricDesc->allocSize; + pParams->pageSize = pMulticastFabricDesc->pageSize; + pParams->numMaxGpus = pMulticastFabricDesc->numMaxGpus; + pParams->numAttachedGpus = pMulticastFabricDesc->numAttachedGpus; + + return NV_OK; +} + +// +// memorymulticastfabricIsReady_IMPL does not take +// the multicast fabric mutex lock as it can be invoked +// with the GPU locks held which would result in a lock +// inversion. Hence we resort to portAtomics here. +// +NV_STATUS +memorymulticastfabricIsReady_IMPL +( + MemoryMulticastFabric *pMemoryMulticastFabric, + NvBool bCopyConstructorContext +) +{ + Memory *pMemory = staticCast(pMemoryMulticastFabric, Memory); + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc; + NV_STATUS mcTeamStatus; + + pMulticastFabricDesc = pMemoryMulticastFabric->pMulticastFabricDesc; + + mcTeamStatus = portAtomicOrU32(&pMulticastFabricDesc->mcTeamStatus, 0); + + if (bCopyConstructorContext && (mcTeamStatus == NV_ERR_NOT_READY)) + return NV_OK; + + if (pMemory->pMemDesc != pMulticastFabricDesc->pMemDesc) + { + // This function only initializes pMemory so it should never fail. + NV_ASSERT_OK(memConstructCommon(pMemory, + NV_MEMORY_MULTICAST_FABRIC, + 0, pMulticastFabricDesc->pMemDesc, + 0, NULL, 0, 0, 0, 0, + NVOS32_MEM_TAG_NONE, NULL)); + } + + return mcTeamStatus; +} + +NV_STATUS +memorymulticastfabricCtrlRegisterEvent_IMPL +( + MemoryMulticastFabric *pMemoryMulticastFabric, + NV00FD_CTRL_REGISTER_EVENT_PARAMS *pParams +) +{ + Memory *pMemory = staticCast(pMemoryMulticastFabric, Memory); + NvHandle hClient = RES_GET_CLIENT_HANDLE(pMemoryMulticastFabric); + + return _memMulticastFabricDescriptorEnqueueWaitUnderLock(hClient, + pMemoryMulticastFabric->pMulticastFabricDesc, + pParams->pOsEvent, pMemory); +} + +NV_STATUS +memorymulticastfabricControl_Prologue_IMPL +( + MemoryMulticastFabric *pMemoryMulticastFabric, + CALL_CONTEXT *pCallContext, + RS_RES_CONTROL_PARAMS_INTERNAL *pParams +) +{ + RmResource *pResource = staticCast(pMemoryMulticastFabric, RmResource); + + // Other control calls, nothing to be validated. + if (pParams->cmd != NV00FD_CTRL_CMD_ATTACH_MEM) + return rmresControl_Prologue_IMPL(pResource, pCallContext, pParams); + + return _memMulticastFabricGpuOsInfoAddUnderLock(pMemoryMulticastFabric, pParams); +} + +NV_STATUS +memorymulticastfabricControl_IMPL +( + MemoryMulticastFabric *pMemoryMulticastFabric, + CALL_CONTEXT *pCallContext, + RS_RES_CONTROL_PARAMS_INTERNAL *pParams +) +{ + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + NV_STATUS status = NV_OK; + + if (pParams->cmd != NV00FD_CTRL_CMD_ATTACH_MEM) + { + status = memorymulticastfabricIsReady(pMemoryMulticastFabric, NV_FALSE); + } + + // + // If clients try to register when the multicast object + // is ready, then there is nothing left to do as the memory + // descriptor is already installed. + // + // If the status is NV_ERR_NOT_READY then we are yet to + // receive the inband reponse and we register the event. + // + if (pParams->cmd == NV00FD_CTRL_CMD_REGISTER_EVENT) + { + if (status == NV_OK) + return NV_WARN_NOTHING_TO_DO; + + if (status != NV_ERR_NOT_READY) + return status; + } + else + { + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, status); + } + + fabricMulticastFabricOpsMutexAcquire(pFabric); + + status = resControl_IMPL(staticCast(pMemoryMulticastFabric, RsResource), + pCallContext, pParams); + + fabricMulticastFabricOpsMutexRelease(pFabric); + + return status; +} + +// +// memorymulticastfabricIsGpuMapAllowed_IMPL does not take +// the multicast fabric mutex lock as it can be invoked +// with the GPU locks held which would result in a lock +// inversion. Hence we resort to portAtomics here. +// +NvBool +memorymulticastfabricIsGpuMapAllowed_IMPL +( + MemoryMulticastFabric *pMemoryMulticastFabric, + OBJGPU *pGpu +) +{ + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc; + NvU32 attachedGpusMask; + + pMulticastFabricDesc = pMemoryMulticastFabric->pMulticastFabricDesc; + + attachedGpusMask = portAtomicOrU32(&pMulticastFabricDesc->attachedGpusMask, 0); + + return ((attachedGpusMask & NVBIT32(pGpu->gpuInstance)) != 0U); +} + +NV_STATUS +memorymulticastfabricGetMapAddrSpace_IMPL +( + MemoryMulticastFabric *pMemoryMulticastFabric, + CALL_CONTEXT *pCallContext, + NvU32 mapFlags, + NV_ADDRESS_SPACE *pAddrSpace +) +{ + *pAddrSpace = ADDR_FABRIC_MC; + return NV_OK; +} diff --git a/src/nvidia/src/kernel/mem_mgr/os_desc_mem.c b/src/nvidia/src/kernel/mem_mgr/os_desc_mem.c index e1ac1a85d..42dd00ca2 100644 --- a/src/nvidia/src/kernel/mem_mgr/os_desc_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/os_desc_mem.c @@ -178,29 +178,6 @@ osdescConstruct_IMPL // RM support for MODS PTE kind in external allocations // bug 1858656 // - if (status == NV_OK && NV_IS_MODS) - { - MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); - NvU32 kind; - FB_ALLOC_PAGE_FORMAT fbAllocPageFormat = {0}; - - NV_ASSERT_OR_RETURN( - DRF_VAL(OS32, _ATTR, _COMPR, pUserParams->attr) == - NVOS32_ATTR_COMPR_NONE, NV_ERR_NOT_SUPPORTED); - - fbAllocPageFormat.flags = pUserParams->flags; - fbAllocPageFormat.type = pUserParams->type; - fbAllocPageFormat.attr = pUserParams->attr; - fbAllocPageFormat.attr2 = pUserParams->attr2; - - // memmgrChooseKind will select kind based on format - status = memmgrChooseKind_HAL(pGpu, pMemoryManager, &fbAllocPageFormat, - DRF_VAL(OS32, _ATTR, _COMPR, pUserParams->attr), &kind); - if (status == NV_OK) - { - memdescSetPteKind(pMemDesc, kind); - } - } // failure case if (status != NV_OK) diff --git a/src/nvidia/src/kernel/mem_mgr/phys_mem.c b/src/nvidia/src/kernel/mem_mgr/phys_mem.c index 79df657b7..c43d0aaab 100644 --- a/src/nvidia/src/kernel/mem_mgr/phys_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/phys_mem.c @@ -168,6 +168,9 @@ physmemConstruct_IMPL } status = memCreateMemDesc(pGpu, &pMemDesc, ADDR_FBMEM, 0, trueLength, attr, attr2); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, status); + memdescDescribe(pMemDesc, ADDR_FBMEM, heapBase, trueLength); if (status == NV_OK) diff --git a/src/nvidia/src/kernel/mem_mgr/standard_mem.c b/src/nvidia/src/kernel/mem_mgr/standard_mem.c index 8c50b03f2..932ea2c5d 100644 --- a/src/nvidia/src/kernel/mem_mgr/standard_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/standard_mem.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -100,6 +100,14 @@ NV_STATUS stdmemValidateParams // if (FLD_TEST_DRF(OS32, _ATTR2, _PAGE_OFFLINING, _OFF, pAllocData->attr2)) { + if (hypervisorIsVgxHyper()) + { + if (!(rmclientIsAdminByHandle(hClient, privLevel) || hypervisorCheckForObjectAccess(hClient))) + { + return NV_ERR_INSUFFICIENT_PERMISSIONS; + } + } + else { // if the client requesting is not kernel mode, return early #if defined(DEBUG) || defined(DEVELOP) || defined(NV_VERIF_FEATURES) @@ -145,6 +153,7 @@ NV_STATUS stdmemValidateParams { NV_CHECK_OR_RETURN(LEVEL_ERROR, FLD_TEST_DRF(OS32, _ATTR, _LOCATION, _VIDMEM, pAllocData->attr), NV_ERR_INVALID_ARGUMENT); + return NV_ERR_INVALID_ARGUMENT; } return NV_OK; diff --git a/src/nvidia/src/kernel/mem_mgr/vaddr_list.c b/src/nvidia/src/kernel/mem_mgr/vaddr_list.c index 7567a405e..6a4be2396 100644 --- a/src/nvidia/src/kernel/mem_mgr/vaddr_list.c +++ b/src/nvidia/src/kernel/mem_mgr/vaddr_list.c @@ -28,227 +28,642 @@ #include "mem_mgr/vaddr_list.h" - /** - * @brief Init map tracker object - * - * @param[in] pVaList tracker object pointer - * - * @return NV_TRUE if tracker object is initialized successfully, NV_FALSE if not +/*! + * @brief Permanently converts a VA_LIST_SIMPLE into a VA_LIST_DICT */ -NV_STATUS vaListInit(VA_LIST *pVaList) +NV_STATUS +vaListInitMap(VA_LIST *pVaList) { - VADDR_LIST_INFO *pVaListInfo = NULL; - VA_INFO *pVaInfo = NULL; + NV_STATUS status; + VADDR_LIST_INFO *pVaListInfo; + VA_INFO *pVaInfo; + struct VA_LIST_INLINE vaCache[2]; - NV_ASSERT_OR_RETURN(pVaList, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pVaList != NULL, NV_ERR_INVALID_ARGUMENT); - mapInit(pVaList, portMemAllocatorGetGlobalNonPaged()); - - pVaListInfo = (VADDR_LIST_INFO *)portMemAllocNonPaged(sizeof(VADDR_LIST_INFO)); + // Save the data in the simple list + pVaListInfo = portMemAllocNonPaged(sizeof(*pVaListInfo)); if (pVaListInfo == NULL) { - mapDestroy(pVaList); return NV_ERR_INSUFFICIENT_RESOURCES; } - portMemSet(pVaListInfo, 0, sizeof(VADDR_LIST_INFO)); - pVaListInfo->bRelease = NV_TRUE; + *pVaListInfo = pVaList->impl.simple.common; + vaCache[0] = pVaList->impl.simple.entries[0]; + vaCache[1] = pVaList->impl.simple.entries[1]; - pVaInfo = mapInsertNew(pVaList, 0); + // Initialize the new map + portMemSet(pVaList, 0, sizeof(*pVaList)); + mapInit(&pVaList->impl.map, portMemAllocatorGetGlobalNonPaged()); + + // Insert the common info into the map + pVaInfo = mapInsertNew(&pVaList->impl.map, 0); if (pVaInfo == NULL) { - mapDestroy(pVaList); + mapDestroy(&pVaList->impl.map); portMemFree(pVaListInfo); return NV_ERR_INSUFFICIENT_RESOURCES; } pVaInfo->pVaListInfo = pVaListInfo; + pVaList->type = VA_LIST_DICT; + + // Safe to use vaListDestroy from this point + + // Add the cached va into the map + status = vaListAddVa(pVaList, vaCache[0].pVas, vaCache[0].vAddr); + if (status != NV_OK) + { + vaListDestroy(pVaList); + return status; + } + + // Add the cached va into the map + status = vaListAddVa(pVaList, vaCache[1].pVas, vaCache[1].vAddr); + if (status != NV_OK) + { + vaListDestroy(pVaList); + return status; + } + + // Update the refcount from the cache + pVaInfo = mapFind(&pVaList->impl.map, (NvU64)NV_PTR_TO_NvP64(vaCache[0].pVas)); + if (pVaInfo == NULL) + { + vaListDestroy(pVaList); + return NV_ERR_INVALID_STATE; + } + pVaInfo->refCnt = vaCache[0].refCnt; + + // Update the refcount from the cache + pVaInfo = mapFind(&pVaList->impl.map, (NvU64)NV_PTR_TO_NvP64(vaCache[1].pVas)); + if (pVaInfo == NULL) + { + vaListDestroy(pVaList); + return NV_ERR_INVALID_STATE; + } + pVaInfo->refCnt = vaCache[1].refCnt; return NV_OK; } -/** - * @brief Destroy map tracker object +/*! + * @brief Return number of unique addresses in this map + */ +NvU32 +vaListMapCount(VA_LIST *pVaList) +{ + NvU32 count; + + NV_ASSERT_OR_RETURN(pVaList != NULL, 0); + + count = 0; + switch (pVaList->type) + { + case VA_LIST_SIMPLE: + { + if (pVaList->impl.simple.entries[0].pVas != NULL) + count++; + + if (pVaList->impl.simple.entries[1].pVas != NULL) + count++; + + break; + } + case VA_LIST_DICT: + { + count += mapCount(&pVaList->impl.map); + // Account for the extra node + if (count > 0) + count--; + + break; + } + } + + return count; +} + +/*! + * @brief Init map tracker object * * @param[in] pVaList tracker object pointer - * - * @return NV_TRUE if tracker object is initialized successfully, NV_FALSE if not */ -void vaListDestroy(VA_LIST *pVaList) +NV_STATUS +vaListInit(VA_LIST *pVaList) { - VA_INFO *pVaInfo = NULL; + NV_ASSERT_OR_RETURN(pVaList != NULL, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN_VOID(pVaList); + portMemSet(pVaList, 0, sizeof(*pVaList)); + pVaList->type = VA_LIST_SIMPLE; + pVaList->impl.simple.common.bRelease = NV_TRUE; + return NV_OK; +} - pVaInfo = mapFind(pVaList, 0); - if (pVaInfo) +/*! + * @brief Remove all mappings from the list + */ +void +vaListClear(VA_LIST *pVaList) +{ + NvBool bManaged = vaListGetManaged(pVaList); + + NV_ASSERT_OR_RETURN_VOID(pVaList != NULL); + + switch (pVaList->type) { - NV_ASSERT(pVaInfo->vAddr == 0); - NV_ASSERT(pVaInfo->refCnt == 0); - NV_ASSERT(pVaInfo->pVaListInfo); + case VA_LIST_SIMPLE: + { + break; + } + case VA_LIST_DICT: + { + VA_INFO *pVaInfo = mapFind(&pVaList->impl.map, 0); - portMemFree(pVaInfo->pVaListInfo); - pVaInfo->pVaListInfo = NULL; + // Delete the dummy state node + if (pVaInfo != NULL) + portMemFree(pVaInfo->pVaListInfo); - mapRemove(pVaList, pVaInfo); - } - else - { - DBG_BREAKPOINT(); + // Remove all of the map nodes and delete the map + mapDestroy(&pVaList->impl.map); + + break; + } } + portMemSet(pVaList, 0, sizeof(*pVaList)); + pVaList->type = VA_LIST_SIMPLE; + pVaList->impl.simple.common.bRelease = bManaged; +} + +/*! + * @brief Destroy map tracker object + */ +void +vaListDestroy(VA_LIST *pVaList) +{ + NV_ASSERT_OR_RETURN_VOID(pVaList != NULL); + // // Skip DBG_BREAKPOINT when we are in Physical RM. // DBG_BREAKPOINT is the result of the lack of eviction of the context buffers from client RM. // - if (!RMCFG_FEATURE_PLATFORM_GSP && mapCount(pVaList) != 0) + if (vaListMapCount(pVaList) != 0) { NV_PRINTF(LEVEL_ERROR, "non-zero mapCount(pVaList): 0x%x\n", - mapCount(pVaList)); + vaListMapCount(pVaList)); DBG_BREAKPOINT(); } - mapDestroy(pVaList); + switch (pVaList->type) + { + case VA_LIST_SIMPLE: + { + portMemSet(pVaList, 0, sizeof(*pVaList)); + + break; + } + case VA_LIST_DICT: + { + VA_INFO *pVaInfo = mapFind(&pVaList->impl.map, 0); + if (pVaInfo != NULL) + { + NV_ASSERT(pVaInfo->vAddr == 0); + NV_ASSERT(pVaInfo->refCnt == 0); + NV_ASSERT(pVaInfo->pVaListInfo); + + portMemFree(pVaInfo->pVaListInfo); + pVaInfo->pVaListInfo = NULL; + + mapRemove(&pVaList->impl.map, pVaInfo); + } + else + { + DBG_BREAKPOINT(); + } + + mapDestroy(&pVaList->impl.map); + + break; + } + } } -NV_STATUS vaListSetManaged(VA_LIST *pVaList, NvBool bManaged) +/*! + * @brief Indicate that this list tracks addresses mapped by RM + * The mode may only be changed when the list is empty. + * + * @param pVaList + * @param bManaged NV_FALSE to indicate addresses not mapped by RM + * + * @return NV_ERR_INVALID_STATE if list is not empty and mode is changing + */ +NV_STATUS +vaListSetManaged(VA_LIST *pVaList, NvBool bManaged) { - VA_INFO *pVaInfo = NULL; - - NV_ASSERT_OR_RETURN(pVaList, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pVaList != NULL, NV_ERR_INVALID_ARGUMENT); // We can change the prop only when no active maps - pVaInfo = mapFind(pVaList, 0); - NV_ASSERT_OR_RETURN(pVaInfo, NV_ERR_INVALID_STATE); - NV_ASSERT_OR_RETURN((mapCount(pVaList) == 1) || - (pVaInfo->pVaListInfo->bRelease == !!bManaged), - NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN((vaListMapCount(pVaList) == 0) || + (vaListGetManaged(pVaList) == bManaged), + NV_ERR_INVALID_STATE); - pVaInfo->pVaListInfo->bRelease = bManaged; + switch (pVaList->type) + { + case VA_LIST_SIMPLE: + { + pVaList->impl.simple.common.bRelease = bManaged; + + break; + } + case VA_LIST_DICT: + { + VA_INFO *pVaInfo = mapFind(&pVaList->impl.map, 0); + + NV_ASSERT_OR_RETURN(pVaInfo != NULL, NV_ERR_INVALID_STATE); + + pVaInfo->pVaListInfo->bRelease = bManaged; + + break; + } + } return NV_OK; } -NvBool vaListGetManaged(VA_LIST *pVaList) +/*! + * @brief returns NV_TRUE if the addresses tracked by this list are mapped by RM + */ +NvBool +vaListGetManaged(VA_LIST *pVaList) { - VA_INFO *pVaInfo = NULL; + NvBool bRelease = NV_TRUE; + NV_ASSERT_OR_RETURN(pVaList != NULL, NV_FALSE); - NV_ASSERT_OR_RETURN(pVaList, NV_FALSE); + switch (pVaList->type) + { + case VA_LIST_SIMPLE: + { + bRelease = pVaList->impl.simple.common.bRelease; - pVaInfo = mapFind(pVaList, 0); - NV_ASSERT_OR_RETURN(pVaInfo, NV_FALSE); - return pVaInfo->pVaListInfo->bRelease; + break; + } + case VA_LIST_DICT: + { + VA_INFO *pVaInfo = mapFind(&pVaList->impl.map, 0); + + NV_ASSERT_OR_RETURN(pVaInfo != NULL, NV_FALSE); + + bRelease = pVaInfo->pVaListInfo->bRelease; + + break; + } + } + + return bRelease; } -NV_STATUS vaListAddVa(VA_LIST *pVaList, OBJVASPACE *pVAS, NvU64 vAddr) -{ - NV_STATUS status = NV_OK; - VA_INFO *pVaInfo = NULL; - - NV_ASSERT_OR_RETURN(pVaList, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(pVAS, NV_ERR_INVALID_ARGUMENT); - - pVaInfo = mapFind(pVaList, (NvU64)NV_PTR_TO_NvP64(pVAS)); - if (pVaInfo) - { - NV_ASSERT_OR_RETURN(pVaInfo->refCnt, NV_ERR_INVALID_STATE); - - if (pVaInfo->vAddr == vAddr) - { - pVaInfo->refCnt++; - } - else - { - DBG_BREAKPOINT(); - status = NV_ERR_INVALID_STATE; - } - } - else - { - pVaInfo = mapInsertNew(pVaList, (NvU64)NV_PTR_TO_NvP64(pVAS)); - if (pVaInfo) - { - pVaInfo->vAddr = vAddr; - pVaInfo->refCnt = 1; - } - else - { - DBG_BREAKPOINT(); - status = NV_ERR_INSUFFICIENT_RESOURCES; - } - } - - return status; -} - -NV_STATUS vaListRemoveVa(VA_LIST *pVaList, OBJVASPACE *pVAS) -{ - NV_STATUS status = NV_OK; - VA_INFO *pVaInfo = NULL; - - NV_ASSERT_OR_RETURN(pVaList, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(pVAS, NV_ERR_INVALID_ARGUMENT); - - pVaInfo = mapFind(pVaList, (NvU64)NV_PTR_TO_NvP64(pVAS)); - if (pVaInfo) - { - NV_ASSERT_OR_RETURN(pVaInfo->refCnt, NV_ERR_INVALID_STATE); - - pVaInfo->refCnt--; - - if (pVaInfo->refCnt == 0) - { - mapRemove(pVaList, pVaInfo); - } - } - else - { - status = NV_ERR_OBJECT_NOT_FOUND; - } - - return status; -} - -NV_STATUS vaListFindVa(VA_LIST *pVaList, OBJVASPACE *pVAS, NvU64 *pVaddr) -{ - NV_STATUS status = NV_OK; - VA_INFO *pVaInfo = NULL; - - NV_ASSERT_OR_RETURN(pVaList, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(pVAS, NV_ERR_INVALID_ARGUMENT); - - pVaInfo = mapFind(pVaList, (NvU64)NV_PTR_TO_NvP64(pVAS)); - if (pVaInfo) - { - NV_ASSERT_OR_RETURN(pVaInfo->refCnt, NV_ERR_INVALID_STATE); - *pVaddr = pVaInfo->vAddr; - } - else - { - status = NV_ERR_OBJECT_NOT_FOUND; - } - - return status; -} - -NV_STATUS vaListGetRefCount(VA_LIST *pVaList, OBJVASPACE *pVAS, NvU64 *refCount) +/*! + * @brief Add a new VAS / vAddr pair to the list + * If the pair already exists, increase its refcount + * + * @param pVaList + * @param pVas OBJVASPACE this vaddr belongs to + * @param vAddr Virtual address being tracked + */ +NV_STATUS +vaListAddVa(VA_LIST *pVaList, OBJVASPACE *pVAS, NvU64 vAddr) +{ + NV_STATUS status = NV_OK; + NV_ASSERT_OR_RETURN(pVaList != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pVAS != NULL, NV_ERR_INVALID_ARGUMENT); + + switch (pVaList->type) + { + case VA_LIST_SIMPLE: + { + if (pVaList->impl.simple.entries[0].pVas == pVAS) + { + NV_ASSERT_OR_RETURN(pVaList->impl.simple.entries[0].refCnt > 0, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(pVaList->impl.simple.entries[0].refCnt < NV_U64_MAX, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(pVaList->impl.simple.entries[0].vAddr == vAddr, NV_ERR_INVALID_STATE); + pVaList->impl.simple.entries[0].refCnt++; + + break; + } + else if (pVaList->impl.simple.entries[1].pVas == pVAS) + { + NV_ASSERT_OR_RETURN(pVaList->impl.simple.entries[1].refCnt > 0, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(pVaList->impl.simple.entries[1].refCnt < NV_U64_MAX, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(pVaList->impl.simple.entries[1].vAddr == vAddr, NV_ERR_INVALID_STATE); + pVaList->impl.simple.entries[1].refCnt++; + + break; + } + + if (vaListMapCount(pVaList) == 2) + { + // Convert the SIMPLE list into a MAP + status = vaListInitMap(pVaList); + if (status != NV_OK) + return status; + + return vaListAddVa(pVaList, pVAS, vAddr); + } + + if (pVaList->impl.simple.entries[0].pVas == NULL) + { + pVaList->impl.simple.entries[0].pVas = pVAS; + pVaList->impl.simple.entries[0].vAddr = vAddr; + pVaList->impl.simple.entries[0].refCnt = 1; + } + else if (pVaList->impl.simple.entries[1].pVas == NULL) + { + pVaList->impl.simple.entries[1].pVas = pVAS; + pVaList->impl.simple.entries[1].vAddr = vAddr; + pVaList->impl.simple.entries[1].refCnt = 1; + } + else + { + // Should never be reached. Should've converted to map + NV_ASSERT_FAILED("Simple va list full"); + return NV_ERR_INVALID_STATE; + } + + break; + } + case VA_LIST_DICT: + { + VA_INFO *pVaInfo = mapFind(&pVaList->impl.map, (NvU64)NV_PTR_TO_NvP64(pVAS)); + + if (pVaInfo != NULL) + { + NV_ASSERT_OR_RETURN(pVaInfo->refCnt > 0, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(pVaInfo->refCnt < NV_U64_MAX, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(pVaInfo->vAddr == vAddr, NV_ERR_INVALID_STATE); + pVaInfo->refCnt++; + } + else + { + pVaInfo = mapInsertNew(&pVaList->impl.map, (NvU64)NV_PTR_TO_NvP64(pVAS)); + NV_ASSERT_OR_RETURN(pVaInfo != NULL, NV_ERR_INSUFFICIENT_RESOURCES); + pVaInfo->vAddr = vAddr; + pVaInfo->refCnt = 1; + } + + break; + } + } + + return status; +} + +/*! + * @brief Remove mapping associated with VAS from tracking + * + * @param pVaList + * @param pVAS OBJVASPACE to remove + * + * @return NV_ERR_OBJECT_NOT_FOUND if VAS not in list + */ +NV_STATUS +vaListRemoveVa(VA_LIST *pVaList, OBJVASPACE *pVAS) { NV_STATUS status = NV_OK; - VA_INFO *pVaInfo; NV_ASSERT_OR_RETURN(pVaList != NULL, NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN(pVAS != NULL, NV_ERR_INVALID_ARGUMENT); - pVaInfo = mapFind(pVaList, (NvU64)NV_PTR_TO_NvP64(pVAS)); - if (pVaInfo != NULL) + switch (pVaList->type) { - NV_ASSERT_OR_RETURN(pVaInfo->refCnt, NV_ERR_INVALID_STATE); - *refCount = pVaInfo->refCnt; - } - else - { - status = NV_ERR_OBJECT_NOT_FOUND; + case VA_LIST_SIMPLE: + { + if (pVaList->impl.simple.entries[0].pVas == pVAS) + { + NV_ASSERT_OR_RETURN(pVaList->impl.simple.entries[0].refCnt > 0, NV_ERR_INVALID_STATE); + + pVaList->impl.simple.entries[0].refCnt--; + if (pVaList->impl.simple.entries[0].refCnt == 0) + { + pVaList->impl.simple.entries[0].pVas = NULL; + pVaList->impl.simple.entries[0].vAddr = 0; + } + } + else if (pVaList->impl.simple.entries[1].pVas == pVAS) + { + NV_ASSERT_OR_RETURN(pVaList->impl.simple.entries[1].refCnt > 0, NV_ERR_INVALID_STATE); + + pVaList->impl.simple.entries[1].refCnt--; + if (pVaList->impl.simple.entries[1].refCnt == 0) + { + pVaList->impl.simple.entries[1].pVas = NULL; + pVaList->impl.simple.entries[1].vAddr = 0; + } + } + else + { + status = NV_ERR_OBJECT_NOT_FOUND; + } + + break; + } + case VA_LIST_DICT: + { + VA_INFO *pVaInfo = mapFind(&pVaList->impl.map, (NvU64)NV_PTR_TO_NvP64(pVAS)); + if (pVaInfo != NULL) + { + NV_ASSERT_OR_RETURN(pVaInfo->refCnt > 0, NV_ERR_INVALID_STATE); + + pVaInfo->refCnt--; + + if (pVaInfo->refCnt == 0) + { + mapRemove(&pVaList->impl.map, pVaInfo); + } + } + else + { + status = NV_ERR_OBJECT_NOT_FOUND; + } + + break; + } } return status; } + +/*! + * @brief Find virtual address associated with given OBJVASPACE + * + * @param pVaList + * @param pVAS OBJVASPACE to remove + * @param pVaddr address associated with VAS + * + * @return NV_ERR_OBJECT_NOT_FOUND if VAS not in list + */ +NV_STATUS +vaListFindVa(VA_LIST *pVaList, OBJVASPACE *pVAS, NvU64 *pVaddr) +{ + NV_STATUS status = NV_OK; + + NV_ASSERT_OR_RETURN(pVaList != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pVAS != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pVaddr != NULL, NV_ERR_INVALID_ARGUMENT); + + switch (pVaList->type) + { + case VA_LIST_SIMPLE: + { + if (pVaList->impl.simple.entries[0].pVas == pVAS) + { + NV_ASSERT_OR_RETURN(pVaList->impl.simple.entries[0].refCnt > 0, NV_ERR_INVALID_STATE); + *pVaddr = pVaList->impl.simple.entries[0].vAddr; + } + else if (pVaList->impl.simple.entries[1].pVas == pVAS) + { + NV_ASSERT_OR_RETURN(pVaList->impl.simple.entries[1].refCnt > 0, NV_ERR_INVALID_STATE); + *pVaddr = pVaList->impl.simple.entries[1].vAddr; + } + else + { + status = NV_ERR_OBJECT_NOT_FOUND; + } + + break; + } + case VA_LIST_DICT: + { + VA_INFO *pVaInfo = mapFind(&pVaList->impl.map, (NvU64)NV_PTR_TO_NvP64(pVAS)); + if (pVaInfo != NULL) + { + NV_ASSERT_OR_RETURN(pVaInfo->refCnt > 0, NV_ERR_INVALID_STATE); + *pVaddr = pVaInfo->vAddr; + } + else + { + status = NV_ERR_OBJECT_NOT_FOUND; + } + + break; + } + } + + return status; +} + +/*! + * @brief Get refcount of OBJVASPACE in list + * + * @param pVaList + * @param pVAS OBJVASPACE to check + * @param pRefCount refcount associated with VAS + * + * @return NV_ERR_OBJECT_NOT_FOUND if VAS not in list + */ +NV_STATUS +vaListGetRefCount(VA_LIST *pVaList, OBJVASPACE *pVAS, NvU64 *pRefCount) +{ + NV_STATUS status = NV_OK; + + NV_ASSERT_OR_RETURN(pVaList != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pVAS != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pRefCount != NULL, NV_ERR_INVALID_ARGUMENT); + + switch (pVaList->type) + { + case VA_LIST_SIMPLE: + { + if (pVaList->impl.simple.entries[0].pVas == pVAS) + { + NV_ASSERT_OR_RETURN(pVaList->impl.simple.entries[0].refCnt > 0, NV_ERR_INVALID_STATE); + *pRefCount = pVaList->impl.simple.entries[0].refCnt; + } + else if (pVaList->impl.simple.entries[1].pVas == pVAS) + { + NV_ASSERT_OR_RETURN(pVaList->impl.simple.entries[1].refCnt > 0, NV_ERR_INVALID_STATE); + *pRefCount = pVaList->impl.simple.entries[1].refCnt; + } + else + { + status = NV_ERR_OBJECT_NOT_FOUND; + } + + break; + } + case VA_LIST_DICT: + { + VA_INFO *pVaInfo = mapFind(&pVaList->impl.map, (NvU64)NV_PTR_TO_NvP64(pVAS)); + if (pVaInfo != NULL) + { + NV_ASSERT_OR_RETURN(pVaInfo->refCnt > 0, NV_ERR_INVALID_STATE); + *pRefCount = pVaInfo->refCnt; + } + else + { + status = NV_ERR_OBJECT_NOT_FOUND; + } + + break; + } + } + + return status; +} + +/*! + * @brief Set refcount of OBJVASPACE in list + * + * @param pVaList + * @param pVAS OBJVASPACE to check + * @param refCount refcount associated with VAS + * + * @return NV_ERR_OBJECT_NOT_FOUND if VAS not in list + */ +NV_STATUS +vaListSetRefCount(VA_LIST *pVaList, OBJVASPACE *pVAS, NvU64 refCount) +{ + NV_STATUS status = NV_OK; + + NV_ASSERT_OR_RETURN(pVaList != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pVAS != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(refCount != 0, NV_ERR_INVALID_ARGUMENT); + + switch (pVaList->type) + { + case VA_LIST_SIMPLE: + { + if (pVaList->impl.simple.entries[0].pVas == pVAS) + { + pVaList->impl.simple.entries[0].refCnt = refCount; + } + else if (pVaList->impl.simple.entries[1].pVas == pVAS) + { + pVaList->impl.simple.entries[1].refCnt = refCount; + } + else + { + status = NV_ERR_OBJECT_NOT_FOUND; + } + + break; + } + case VA_LIST_DICT: + { + VA_INFO *pVaInfo = mapFind(&pVaList->impl.map, (NvU64)NV_PTR_TO_NvP64(pVAS)); + if (pVaInfo != NULL) + { + pVaInfo->refCnt = refCount; + } + else + { + status = NV_ERR_OBJECT_NOT_FOUND; + } + + break; + } + } + + return status; +} + diff --git a/src/nvidia/src/kernel/mem_mgr/vaspace.c b/src/nvidia/src/kernel/mem_mgr/vaspace.c index f1963a18f..232967284 100644 --- a/src/nvidia/src/kernel/mem_mgr/vaspace.c +++ b/src/nvidia/src/kernel/mem_mgr/vaspace.c @@ -21,7 +21,7 @@ * DEALINGS IN THE SOFTWARE. */ -/***************************** HW State Rotuines ***************************\ +/***************************** HW State Routines ***************************\ * Virtual Address Space Function Definitions. * \***************************************************************************/ diff --git a/src/nvidia/src/kernel/mem_mgr/video_mem.c b/src/nvidia/src/kernel/mem_mgr/video_mem.c index 0ad341d06..1fd1c0984 100644 --- a/src/nvidia/src/kernel/mem_mgr/video_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/video_mem.c @@ -164,12 +164,9 @@ _vidmemPmaAllocate // Get the page size returned by RM. pageSize = stdmemQueryPageSize(pMemoryManager, pAllocRequest->hClient, pAllocData); + NV_ASSERT_OR_RETURN(pageSize != 0, NV_ERR_INVALID_STATE); - if (pageSize == 0) - { - status = NV_ERR_INVALID_STATE; - } - else if (pageSize == RM_PAGE_SIZE) + if (pageSize == RM_PAGE_SIZE) { // // TODO Remove this after the suballocator is in place @@ -547,7 +544,7 @@ vidmemConstruct_IMPL // Scrub-on-free is not supported by heap. Make sure clients don't get unscrubbed allocations NV_CHECK_OR_RETURN(LEVEL_WARNING, - !memmgrIsScrubOnFreeEnabled(pMemoryManager) || RMCFG_FEATURE_PLATFORM_MODS || bIsPmaAlloc || bSubheap, + !memmgrIsScrubOnFreeEnabled(pMemoryManager) || bIsPmaAlloc || bSubheap, NV_ERR_INVALID_STATE); // Get the allocation from PMA if enabled. @@ -1096,6 +1093,15 @@ vidmemAllocResources { pFbAllocInfo->offset = pMemDesc->_pteArray[0]; + if (pMemoryManager->bEnableDynamicGranularityPageArrays == NV_TRUE) + { + // + // set pagearray granularity if dynamic memdesc pagesize is enabled + // this ensures consistency in calculation of page count + // + pMemDesc->pageArrayGranularity = pAllocRequest->pPmaAllocInfo[subdeviceInst]->pageSize; + } + if (bContig) { NV_PRINTF(LEVEL_INFO, "---> PMA Path taken contiguous\n"); diff --git a/src/nvidia/src/kernel/mem_mgr/virt_mem_mgr.c b/src/nvidia/src/kernel/mem_mgr/virt_mem_mgr.c index 7e4e172b8..4722b268e 100644 --- a/src/nvidia/src/kernel/mem_mgr/virt_mem_mgr.c +++ b/src/nvidia/src/kernel/mem_mgr/virt_mem_mgr.c @@ -21,7 +21,7 @@ * DEALINGS IN THE SOFTWARE. */ -/***************************** HW State Rotuines ***************************\ +/***************************** HW State Routines ***************************\ * * * Virtual Memory Manager Object Function Definitions. * * * diff --git a/src/nvidia/src/kernel/mem_mgr/virt_mem_range.c b/src/nvidia/src/kernel/mem_mgr/virt_mem_range.c index faa5ff677..7026b93d8 100644 --- a/src/nvidia/src/kernel/mem_mgr/virt_mem_range.c +++ b/src/nvidia/src/kernel/mem_mgr/virt_mem_range.c @@ -71,12 +71,12 @@ vmrangeConstruct_IMPL // if (pAllocData->hVASpace == 0) { - NV_ASSERT_OR_RETURN(pKernelGmmu->maxVASize, NV_ERR_INVALID_STATE); - maxVA = pKernelGmmu->maxVASize; + NV_ASSERT_OR_RETURN(kgmmuGetMaxVASize(pKernelGmmu), NV_ERR_INVALID_STATE); + maxVA = kgmmuGetMaxVASize(pKernelGmmu); } else if (pAllocData->hVASpace == NV_MEMORY_VIRTUAL_SYSMEM_DYNAMIC_HVASPACE) { - NV_ASSERT_OR_RETURN(pKernelGmmu->maxVASize, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(kgmmuGetMaxVASize(pKernelGmmu), NV_ERR_INVALID_STATE); maxVA = 1ULL << 40; } else diff --git a/src/nvidia/src/kernel/mem_mgr/virtual_mem.c b/src/nvidia/src/kernel/mem_mgr/virtual_mem.c index 2e7f84a15..8459fedc0 100644 --- a/src/nvidia/src/kernel/mem_mgr/virtual_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/virtual_mem.c @@ -36,6 +36,7 @@ #include "gpu/mem_mgr/mem_utils.h" #include "gpu/bus/kern_bus.h" #include "gpu/bus/p2p_api.h" +#include "mem_mgr/gpu_vaspace.h" #include "class/cl0070.h" // NV01_MEMORY_VIRTUAL #include "class/cl50a0.h" // NV50_MEMORY_VIRTUAL @@ -333,7 +334,7 @@ virtmemConstruct_IMPL gpuMaskInitial = rmGpuLocksGetOwnedMask(); NvU32 lockFlag = (gpuMaskInitial == 0) ? GPUS_LOCK_FLAGS_NONE - : GPUS_LOCK_FLAGS_COND_ACQUIRE; + : GPU_LOCK_FLAGS_COND_ACQUIRE; NV_ASSERT_OK_OR_RETURN(rmGpuGroupLockAcquire(pGpu->gpuInstance, GPU_LOCK_GRP_ALL, @@ -813,6 +814,7 @@ virtmemAllocResources gpuIsSplitVasManagementServerClientRmEnabled(pGpu)) { OBJVASPACE *pVAS = NULL; + OBJGVASPACE *pGVAS = NULL; NvU64 align = pFbAllocInfo->align + 1; VAS_ALLOC_FLAGS flags = {0}; NvU64 pageSizeLockMask = 0; @@ -824,6 +826,23 @@ virtmemAllocResources if (NV_OK != status) goto failed; + // + // Feature requested for RM unlinked SLI: + // Clients can pass an allocation flag to the device or VA space constructor + // so that mappings and allocations will fail without an explicit address. + // + pGVAS = dynamicCast(pVAS, OBJGVASPACE); + if (pGVAS != NULL) + { + if ((pGVAS->flags & VASPACE_FLAGS_REQUIRE_FIXED_OFFSET) && + !(pVidHeapAlloc->flags & NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE)) + { + status = NV_ERR_INVALID_ARGUMENT; + NV_PRINTF(LEVEL_ERROR, "The VA space requires all allocations to specify a fixed address\n"); + goto failed; + } + } + status = vaspaceFillAllocParams(pVAS, pFbAllocInfo, &pFbAllocInfo->size, &align, &pVidHeapAlloc->rangeLo, &pVidHeapAlloc->rangeHi, @@ -1208,7 +1227,6 @@ virtmemMapTo_IMPL MEMORY_DESCRIPTOR *pSrcMemDesc = pParams->pSrcMemDesc; NvU64 *pDmaOffset = pParams->pDmaOffset; // return VirtualMemory offset CLI_DMA_MAPPING_INFO *pDmaMappingInfo = NULL; - CLI_DMA_MAPPING_INFO *pDmaMappingInfo_old = NULL; OBJVASPACE *pVas = NULL; Memory *pSrcMemory = dynamicCast(pMemoryRef->pResource, Memory); @@ -1295,7 +1313,9 @@ virtmemMapTo_IMPL bDmaMapNeeded = NV_FALSE; } - if (tgtAddressSpace == ADDR_FABRIC || tgtAddressSpace == ADDR_FABRIC_V2) + if ( + (tgtAddressSpace == ADDR_FABRIC_MC) || + (tgtAddressSpace == ADDR_FABRIC_V2)) { // IOMMU mapping not needed for GPU P2P accesses on FB pages. bDmaMapNeeded = NV_FALSE; @@ -1304,7 +1324,9 @@ virtmemMapTo_IMPL // Different cases for vidmem & system memory/fabric memory. bIsSysmem = (tgtAddressSpace == ADDR_SYSMEM); - if (bIsSysmem || (tgtAddressSpace == ADDR_FABRIC) || (tgtAddressSpace == ADDR_FABRIC_V2)) + if (bIsSysmem || + (tgtAddressSpace == ADDR_FABRIC_MC) || + (tgtAddressSpace == ADDR_FABRIC_V2)) { // offset needs to be 0 when reusing a mapping. if ((DRF_VAL(OS46, _FLAGS, _DMA_UNICAST_REUSE_ALLOC, flags) == NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_TRUE) && @@ -1494,9 +1516,6 @@ virtmemMapTo_IMPL !bFlaMapping && (bBar1P2P || DRF_VAL(OS46, _FLAGS, _P2P_ENABLE, pDmaMappingInfo->Flags) == NVOS46_FLAGS_P2P_ENABLE_NOSLI)) { - NvU32 subDevIdSrc; - NvU32 subDevIdTgt; - // // if we are on SLI and trying to map peer memory between two GPUs // on the same device, we don't rely on dynamic p2p mailbox setup. @@ -1508,26 +1527,7 @@ virtmemMapTo_IMPL goto vgpu_send_rpc; } - subDevIdSrc = DRF_VAL(OS46, _FLAGS, _P2P_SUBDEV_ID_SRC, pDmaMappingInfo->Flags); - subDevIdTgt = DRF_VAL(OS46, _FLAGS, _P2P_SUBDEV_ID_TGT, pDmaMappingInfo->Flags); - - status = CliAddP2PDmaMappingInfo(hClient, - hBroadcastDevice, subDevIdTgt, - hMemoryDevice, subDevIdSrc, - pDmaMappingInfo); - if (NV_OK != status) - { - dmaFreeMap(pGpu, pDma, pVas, - pVirtualMemory, pDmaMappingInfo, - DRF_DEF(OS47, _FLAGS, _DEFER_TLB_INVALIDATION, _FALSE)); - - intermapDelDmaMapping(pClient, hBroadcastDevice, hVirtualMem, *pDmaOffset, gpuMask, NULL); - pDmaMappingInfo = NULL; - return status; - } - - // cache the pointer - pDmaMappingInfo_old = pDmaMappingInfo; + pDmaMappingInfo->bP2P = NV_TRUE; } vgpu_send_rpc: @@ -1551,14 +1551,6 @@ vgpu_send_rpc: // NV_ASSERT(!IsSLIEnabled(pGpu)); - // delete the old copy - if (RMCFG_CLASS_NV50_P2P && - (pDmaMappingInfo_old != NULL)) - { - status = CliUpdateP2PDmaMappingInList(hClient, pDmaMappingInfo, *pDmaOffset); - NV_ASSERT(status == NV_OK); - } - pDmaMappingInfo->DmaOffset = *pDmaOffset; status = intermapRegisterDmaMapping(pClient, hBroadcastDevice, hVirtualMem, pDmaMappingInfo, @@ -1732,10 +1724,8 @@ virtmemUnmapFrom_IMPL } // if this was peer mapped context dma, remove it from P2P object - if (RMCFG_CLASS_NV50_P2P && (pDmaMappingInfo->pP2PInfo != NULL)) + if (RMCFG_CLASS_NV50_P2P && pDmaMappingInfo->bP2P) { - CliDelP2PDmaMappingInfo(hClient, pDmaMappingInfo); - dmaFreeBar1P2PMapping_HAL(GPU_GET_DMA(pGpu), pDmaMappingInfo); } diff --git a/src/nvidia/src/kernel/os/os_init.c b/src/nvidia/src/kernel/os/os_init.c index 0663ccd5e..d6ca0211e 100644 --- a/src/nvidia/src/kernel/os/os_init.c +++ b/src/nvidia/src/kernel/os/os_init.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,7 +21,7 @@ * DEALINGS IN THE SOFTWARE. */ -/***************************** HW State Rotuines ***************************\ +/***************************** HW State Routines ***************************\ * * * Common Operating System Object Function Pointer Initializations. * * All the function pointers in the OS object are initialized here. * @@ -48,8 +48,7 @@ #include "gpu/bif/kernel_bif.h" #include "kernel/gpu/rc/kernel_rc.h" - -#include "g_os_private.h" +#include "platform/nbsi/nbsi_read.h" // // Functions to fill function stubs @@ -637,6 +636,10 @@ NV_STATUS osReadRegistryDword NV_ASSERT_OR_RETURN(pData != NULL, NV_ERR_INVALID_ARGUMENT); status = osReadRegistryDwordBase(pGpu, pRegParmStr, pData); + if (status != NV_OK) + { + status = nbsiReadRegistryDword(pGpu, pRegParmStr, pData); + } return status; } @@ -667,6 +670,10 @@ NV_STATUS osReadRegistryString NV_ASSERT_OR_RETURN(!(*pCbLen != 0 && pData == NULL), NV_ERR_INVALID_ARGUMENT); status = osReadRegistryStringBase(pGpu, pRegParmStr, pData, pCbLen); + if (status != NV_OK) + { + status = nbsiReadRegistryString(pGpu, pRegParmStr, pData, pCbLen); + } return status; } diff --git a/src/nvidia/src/kernel/os/os_sanity.c b/src/nvidia/src/kernel/os/os_sanity.c index 48a201725..127def6e5 100644 --- a/src/nvidia/src/kernel/os/os_sanity.c +++ b/src/nvidia/src/kernel/os/os_sanity.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -36,8 +36,6 @@ #include #include -#include "g_os_private.h" - /*! * @brief Wait for interrupt * @@ -111,7 +109,7 @@ NV_STATUS osSanityTestIsr( osWaitForInterrupt(pGpu, &serviced); - return (serviced) ? NV_OK : NV_ERR_GENERIC; + return (serviced) ? NV_OK : NV_ERR_INVALID_STATE; } // @@ -123,10 +121,8 @@ static NV_STATUS _osVerifyInterrupts( OBJGPU *pGpu ) { -#if !defined(NV_UNIX) || defined(NV_MODS) - OBJTMR *pTmr = GPU_GET_TIMER(pGpu); -#endif Intr *pIntr = GPU_GET_INTR(pGpu); + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); OBJGPU *pGpuSaved = pGpu; NvU32 *pIntrEn0, *pIntrEn1; MC_ENGINE_BITVECTOR intrMask; @@ -243,6 +239,7 @@ static NV_STATUS _osVerifyInterrupts( osDelay(50); Bailout += 50 * 1000; #else + OBJTMR *pTmr = GPU_GET_TIMER(pGpu); tmrDelay(pTmr, 5 * 1000); Bailout += 5; #endif @@ -254,7 +251,6 @@ static NV_STATUS _osVerifyInterrupts( // Message Signalled Interrupt (MSI) support // This call checks if MSI is enabled and if it is, we need re-arm it. // - KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); kbifCheckAndRearmMSI(pGpu, pKernelBif); pGpu->testIntr = NV_FALSE; diff --git a/src/nvidia/src/kernel/os/os_stubs.c b/src/nvidia/src/kernel/os/os_stubs.c index 126c14e68..83d81f7d0 100644 --- a/src/nvidia/src/kernel/os/os_stubs.c +++ b/src/nvidia/src/kernel/os/os_stubs.c @@ -378,6 +378,83 @@ NV_STATUS osTegraSocGpioSetPinInterrupt( { return NV_ERR_NOT_SUPPORTED; } + +NV_STATUS +osTegraSocResetMipiCal +( + OS_GPU_INFO *pOsGpuInfo +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS osGetValidWindowHeadMask +( + OS_GPU_INFO *pArg1, + NvU64 *pWindowHeadMask +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NvBool +osTegraSocIsDsiPanelConnected +( + OS_GPU_INFO *pOsGpuInfo +) +{ + return NV_FALSE; +} + +NV_STATUS +osTegraSocDsiParsePanelProps +( + OS_GPU_INFO *pOsGpuInfo, + void *dsiPanelInfo +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +osTegraSocDsiPanelEnable +( + OS_GPU_INFO *pOsGpuInfo, + void *dsiPanelInfo +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +osTegraSocDsiPanelReset +( + OS_GPU_INFO *pOsGpuInfo, + void *dsiPanelInfo +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +void +osTegraSocDsiPanelDisable +( + OS_GPU_INFO *pOsGpuInfo, + void *dsiPanelInfo +) +{ + return; +} + +void +osTegraSocDsiPanelCleanup +( + OS_GPU_INFO *pOsGpuInfo, + void *dsiPanelInfo +) +{ + return; +} #endif NV_STATUS @@ -538,6 +615,13 @@ NV_STATUS osDeferredIsr( return NV_OK; } +void osSetSurfaceName( + void *pDescriptor, + char *name +) +{ +} + NV_STATUS osGetAcpiTable( NvU32 tableSignature, void **ppTable, @@ -603,68 +687,6 @@ stubOsGetUefiVariable return NV_ERR_NOT_SUPPORTED; } -#if !RMCFG_FEATURE_PLATFORM_UNIX || \ - (RMCFG_FEATURE_PLATFORM_UNIX && !RMCFG_FEATURE_TEGRA_SOC_NVDISPLAY) -NV_STATUS -osTegraSocResetMipiCal -( - OS_GPU_INFO *pOsGpuInfo -) -{ - return NV_FALSE; -} - -NV_STATUS -osTegraSocDsiParsePanelProps -( - OS_GPU_INFO *pOsGpuInfo, - void *dsiPanelInfo -) -{ - return NV_ERR_NOT_SUPPORTED; -} - -NV_STATUS -osTegraSocDsiPanelEnable -( - OS_GPU_INFO *pOsGpuInfo, - void *dsiPanelInfo -) -{ - return NV_ERR_NOT_SUPPORTED; -} - -NV_STATUS -osTegraSocDsiPanelReset -( - OS_GPU_INFO *pOsGpuInfo, - void *dsiPanelInfo -) -{ - return NV_ERR_NOT_SUPPORTED; -} - -void -osTegraSocDsiPanelDisable -( - OS_GPU_INFO *pOsGpuInfo, - void *dsiPanelInfo -) -{ - return; -} - -void -osTegraSocDsiPanelCleanup -( - OS_GPU_INFO *pOsGpuInfo, - void *dsiPanelInfo -) -{ - return; -} -#endif - NvU32 osGetDynamicPowerSupportMask(void) { return 0; @@ -804,15 +826,6 @@ osTegraSocPmUnpowergate } #endif -NvBool -osTegraSocIsDsiPanelConnected -( - OS_GPU_INFO *pOsGpuInfo -) -{ - return NV_FALSE; -} - #if !(RMCFG_FEATURE_PLATFORM_UNIX) || \ (RMCFG_FEATURE_PLATFORM_UNIX && !RMCFG_FEATURE_TEGRA_SOC_NVDISPLAY) NvU32 @@ -820,5 +833,18 @@ osTegraSocFuseRegRead(NvU32 addr) { return 0; } + +NV_STATUS +osTegraSocDpUphyPllInit(OS_GPU_INFO *pOsGpuInfo, NvU32 link_rate, NvU32 lanes) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +osTegraSocDpUphyPllDeInit(OS_GPU_INFO *pOsGpuInfo) +{ + return NV_ERR_NOT_SUPPORTED; +} + #endif diff --git a/src/nvidia/src/kernel/os/os_timer.c b/src/nvidia/src/kernel/os/os_timer.c index db4dc9078..5a0614437 100644 --- a/src/nvidia/src/kernel/os/os_timer.c +++ b/src/nvidia/src/kernel/os/os_timer.c @@ -232,7 +232,7 @@ osRun1HzCallbacksNow // LOCK: try to acquire GPU lock if (rmGpuGroupLockAcquire(pGpu->gpuInstance, GPU_LOCK_GRP_DEVICE, - GPUS_LOCK_FLAGS_COND_ACQUIRE, RM_LOCK_MODULES_TMR, + GPU_LOCK_FLAGS_COND_ACQUIRE, RM_LOCK_MODULES_TMR, &lockedGpus) != NV_OK) { // Out of conflicting thread diff --git a/src/nvidia/src/kernel/platform/acpi_common.c b/src/nvidia/src/kernel/platform/acpi_common.c new file mode 100644 index 000000000..b69e64f50 --- /dev/null +++ b/src/nvidia/src/kernel/platform/acpi_common.c @@ -0,0 +1,1281 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2000-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * @file + * @brief ACPI common routines - non OS dependant + */ + +#include "os/os.h" +#include "platform/acpi_common.h" +#include "acpidsmguids.h" +#include "nvhybridacpi.h" +#include "nbci.h" +#include "gps.h" +#include "nvop.h" +#include "nvhybridacpi.h" +#include "jt.h" +#include "pex.h" +#include "mxm_spec.h" +#include "gpu/gsp/gsp_static_config.h" +#include "platform/nbsi/nbsi_read.h" + +// +// DSM ACPI Routines common routines for Linux +// +// these are debug strings for printing which DSM subfunction didn't work. +// These map directly to the ACPI_DSM_FUNCTION enum in \interface\nvacpitypes.h. +// +#if NV_PRINTF_ENABLED +const char * const DSMCalls[] = {"NBSI","NVHG","MXM","NBCI","NVOP","PFCG","GPS_2X","JT","PEX","NVPCF_2X","GPS","NVPCF","UNKNOWN","CURRENT"}; +#endif + +/* + * @_isDsmError returns status if the return data is an error indicator. + * ACPI returns a dword such as 0x80000002 to indicate a failure. Note there + * is a possibility that if a subfunction returns the same data this could be + * confused. + * + * @param[in] status NV_STATUS return status from ACPI call + * @param[in] rtnSize NvU16 number of bytes at rtnvalue + * @param[in] rtnvalue NvU32 * pointer to returned value/status. + * + * @returns NV_TRUE if an error was found + * NV_FALSE if an error wasn't found + */ +static NvBool +_isDsmError +( + NV_STATUS status, + NvU16 rtnSize, + NvU32 *rtnvalue +) +{ + if (status != NV_OK) + { + return NV_TRUE; + } + else if (rtnSize == sizeof(NvU32)) + { + if ((*rtnvalue >= NVHG_ERROR_UNSPECIFIED) && + (*rtnvalue <= NVHG_ERROR_PARM_INVALID)) + { + return NV_TRUE; + } + } + return NV_FALSE; +} + +/* + * @cacheDsmSupportedFunction caches the return from the DSM get supported + * functions call. Used later to determine whether to call again. + * + * @param[in] pGpu OBJGPU + * @param[in] acpiDsmFunction ACPI_DSM_FUNCTION DSM call indicator + * @param[in] subfunction NvU32 subfunction number + * @param[in] pInOut NvU32 * pointer to get supported return data. + * @param[in] inOutSize NvU32 size of data in pInOut + * + * @returns void + */ +void +cacheDsmSupportedFunction +( + OBJGPU *pGpu, + ACPI_DSM_FUNCTION acpiDsmFunction, + NvU32 acpiDsmSubFunction, + NvU32 *pInOut, + NvU32 inOutSize +) +{ + if ((acpiDsmSubFunction == NV_ACPI_ALL_FUNC_SUPPORT) && + (inOutSize > 0) && + (inOutSize <= sizeof(pGpu->acpi.dsm[acpiDsmFunction].suppFuncs))) + { + if (_isDsmError(NV_OK, (NvU16) inOutSize, pInOut)) + { + NV_PRINTF(LEVEL_INFO, + "%s DSM functions not available.\n", + DSMFuncStr(acpiDsmFunction)); + return; + } + + // cache return from get supported function list + portMemCopy((NvU8 *)pGpu->acpi.dsm[acpiDsmFunction].suppFuncs, + inOutSize, + (NvU8 *)pInOut, + inOutSize); + + pGpu->acpi.dsm[acpiDsmFunction].suppFuncsLen = inOutSize; + + // if bit 0 of get supported function is set, indicate success + if (pGpu->acpi.dsm[acpiDsmFunction].suppFuncs[NV_ACPI_ALL_FUNC_SUPPORT/8] & NV_ACPI_ALL_FUNC_SUPPORTED) + { + pGpu->acpi.dsm[acpiDsmFunction].suppFuncStatus = DSM_FUNC_STATUS_SUCCESS; + } + +#ifdef NV_PRINTF_ENABLED + if (inOutSize == 8) + { + NV_PRINTF(LEVEL_INFO, + "%s DSM get supported subfunction returned 0x%08x size=%d suppStatus=%d\n", + DSMFuncStr(acpiDsmFunction), *pInOut, + inOutSize, + pGpu->acpi.dsm[acpiDsmFunction].suppFuncStatus); + } + else + { + NV_PRINTF(LEVEL_INFO, + "%s DSM get supported subfunction returned 0x%04x size=%d suppStatus=%d\n", + DSMFuncStr(acpiDsmFunction), *pInOut, + inOutSize, + pGpu->acpi.dsm[acpiDsmFunction].suppFuncStatus); + } +#endif + } +} + +/* + * @testIfDsmSubFunctionEnabled tests if a DSM subfunction is enabled. + * + * @param[in] pGpu OBJGPU + * @param[in] acpiDsmFunction ACPI_DSM_FUNCTION DSM call indicator + * @param[in] subfunction NvU32 subfunction number + * + * @returns NV_STATUS of + * NV_OK when the subfunction is enabled/supported. + * NV_ERR_NOT_SUPPORTED when the subfunction is not supported. + * NV_ERR_OPERATING_SYSTEM when get supported list was tried and failed. + * NV_ERR_OBJECT_NOT_FOUND when get supportee list hasn't been tried. + */ +NV_STATUS +testIfDsmSubFunctionEnabled +( + OBJGPU *pGpu, + ACPI_DSM_FUNCTION acpiDsmFunction, + NvU32 acpiDsmSubFunction +) +{ + NvU32 idx; + NvU32 bitToTest; + + NV_ASSERT_OR_RETURN((acpiDsmFunction < ACPI_DSM_FUNCTION_COUNT) || (acpiDsmFunction == ACPI_DSM_FUNCTION_CURRENT), + NV_ERR_INVALID_ARGUMENT); + + if (remapDsmFunctionAndSubFunction(pGpu, &acpiDsmFunction, &acpiDsmSubFunction) != NV_OK) + { + return NV_ERR_NOT_SUPPORTED; + } + + NV_ASSERT_OR_RETURN(acpiDsmFunction < ACPI_DSM_FUNCTION_COUNT, NV_ERR_INVALID_ARGUMENT); + + idx = acpiDsmSubFunction / 8; + bitToTest = NVBIT(acpiDsmSubFunction % 8); + + // Caller asked for a subfunction... do we support it + switch (pGpu->acpi.dsm[acpiDsmFunction].suppFuncStatus) + { + case DSM_FUNC_STATUS_OVERRIDE: + case DSM_FUNC_STATUS_SUCCESS: + // confirm the supported subfunction bit is set in. + if (idx > pGpu->acpi.dsm[acpiDsmFunction].suppFuncsLen) + { + return NV_ERR_NOT_SUPPORTED; + } + if (!(pGpu->acpi.dsm[acpiDsmFunction].suppFuncs[idx] & bitToTest)) + { + return NV_ERR_NOT_SUPPORTED; + } + return NV_OK; + break; + + case DSM_FUNC_STATUS_FAILED: + // the get supported function failed... assume all subfunctions won't work. + return NV_ERR_OPERATING_SYSTEM; + break; + + default: + case DSM_FUNC_STATUS_UNKNOWN: + // + // Somebody forgot to call _acpiDsmSupportedFuncCacheInit before trying + // the dsm subfunction itself. This should be fixed! + // + NV_PRINTF(LEVEL_ERROR, + "%s ACPI DSM called before _acpiDsmSupportedFuncCacheInit subfunction = %x.\n", + DSMFuncStr(acpiDsmFunction), + acpiDsmSubFunction); + // DBG_BREAKPOINT(); + return NV_ERR_OBJECT_NOT_FOUND; + } +} + +/* + * @testIfDsmFuncSupported returns if a DSM function is supported. + * This checks the status of the previously cached copy of the supported + * functions list. + * + * @param[in] pGpu OBJGPU + * @param[in] acpiDsmFunction ACPI_DSM_FUNCTION DSM function + * + * @returns NV_STATUS of + * NV_ERR_INVALID_STATE if the pGpu pointer is NULL + * NV_ERR_NOT_SUPPORTED if the the get supported functions call + * succeedes but the specific DSM subfunction + * is not supported. + * NV_WARN_MORE_PROCESSING_REQUIRED if the get supported subfunctions + * list call hasn't been done yet. + * NV_OK if the DSM function is supported. + */ +NV_STATUS +testIfDsmFuncSupported +( + OBJGPU *pGpu, + ACPI_DSM_FUNCTION acpiDsmFunction +) +{ + if (pGpu == NULL) + { + return NV_ERR_INVALID_STATE; + } + + // no generic functions allowed + NV_ASSERT_OR_RETURN(acpiDsmFunction < ACPI_DSM_FUNCTION_COUNT, NV_ERR_INVALID_ARGUMENT); + + // should only be called after the cache is inited. + NV_ASSERT_OR_RETURN((pGpu->acpi.dsm[acpiDsmFunction].suppFuncStatus == DSM_FUNC_STATUS_SUCCESS) || + (pGpu->acpi.dsm[acpiDsmFunction].suppFuncStatus == DSM_FUNC_STATUS_OVERRIDE) || + (pGpu->acpi.dsm[acpiDsmFunction].suppFuncStatus == DSM_FUNC_STATUS_FAILED), + NV_ERR_INVALID_ARGUMENT); + + switch (pGpu->acpi.dsm[acpiDsmFunction].suppFuncStatus) + { + case DSM_FUNC_STATUS_OVERRIDE: + case DSM_FUNC_STATUS_SUCCESS: + return NV_OK; + case DSM_FUNC_STATUS_FAILED: + return NV_ERR_NOT_SUPPORTED; + default: + case DSM_FUNC_STATUS_UNKNOWN: + // just in case... should be asserted. + // NV_ASSERT(0); + return NV_WARN_MORE_PROCESSING_REQUIRED; + } +} + +// +// This table defines the generic subfunction remapping. +// +// At driver startup the following occurs. +// 1) The get supported subfunctions (0) subfunction call is used for each of +// the acpi functions guids. +// 2) For each of the generic subfunctions, the return data from the get supported +// subfunction list is used to determine which GUID supports that function. +// The order is based on the dsmOrderOfPrecedenceList below. +// Example: +// For NV_ACPI_GENERIC_FUNC_HYBRIDCAPS we look at the following (in the +// following order. +// ACPI_DSM_FUNCTION_NVOP - ignored no compatible subfunction +// ACPI_DSM_FUNCTION_NBCI/NV_NBCI_FUNC_PLATCAPS +// ACPI_DSM_FUNCTION_MXM - ignored no compatible subfunction +// ACPI_DSM_FUNCTION_NVHG/NVHG_FUNC_HYBRIDCAPS +// ACPI_DSM_FUNCTION_NBSI/NBSI_FUNC_PLATCAPS +// The first subfunction which is supported in the above list is saved +// and used whenever a call to +// ACPI_DSM_FUNCTION_CURRENT/NV_ACPI_GENERIC_FUNC_HYBRIDCAPS is used. +// So if ACPI_DSM_FUNCTION_NBCI/NV_NBCI_FUNC_PLATCAPS is not supported but +// ACPI_DSM_FUNCTION_NVHG/NVHG_FUNC_HYBRIDCAPS is. Then the NVHG GUID will +// be used. +// +static const NvU32 genDsmSubFuncRemapTable[] = +{ + // generic function + // ACPI_DSM_FUNCTION_CURRENT , ACPI_DSM_FUNCTION_NBSI , ACPI_DSM_FUNCTION_NVHG , ACPI_DSM_FUNCTION_MXM , ACPI_DSM_FUNCTION_NBCI , ACPI_DSM_FUNCTION_NVOP , ACPI_DSM_FUNCTION_PCFG , ACPI_DSM_FUNCTION_GPS_2X , ACPI_DSM_FUNCTION_JT , ACPI_DSM_FUNCTION_PEX , ACPI_DSM_FUNCTION_NVPCF_2X, ACPI_DSM_FUNCTION_GPS , ACPI_DSM_FUNCTION_NVPCF, + NV_ACPI_GENERIC_FUNC_DISPLAYSTATUS , NBSI_FUNC_DISPLAYSTATUS , NVHG_FUNC_DISPLAYSTATUS , NV_ACPI_DSM_MXM_FUNC_MXDP , NV_NBCI_FUNC_DISPLAYSTATUS, NVOP_FUNC_DISPLAYSTATUS, 0 , 0 , JT_FUNC_DISPLAYSTATUS , 0 , 0 , 0 , 0 , + NV_ACPI_GENERIC_FUNC_MDTL , NBSI_FUNC_MDTL , NVHG_FUNC_MDTL , NV_ACPI_DSM_MXM_FUNC_MDTL , NV_NBCI_FUNC_MDTL , NVOP_FUNC_MDTL , 0 , 0 , JT_FUNC_MDTL , 0 , 0 , 0 , 0 , + NV_ACPI_GENERIC_FUNC_GETOBJBYTYPE , NBSI_FUNC_GETOBJBYTYPE , NVHG_FUNC_GETOBJBYTYPE , 0 , NV_NBCI_FUNC_GETOBJBYTYPE , NVOP_FUNC_GETOBJBYTYPE , 0 , GPS_FUNC_GETOBJBYTYPE , 0 , 0 , 0 , GPS_FUNC_GETOBJBYTYPE , 0 , + NV_ACPI_GENERIC_FUNC_GETALLOBJS , NBSI_FUNC_GETALLOBJS , NVHG_FUNC_GETALLOBJS , 0 , NV_NBCI_FUNC_GETALLOBJS , NVOP_FUNC_GETALLOBJS , 0 , GPS_FUNC_GETALLOBJS , 0 , 0 , 0 , GPS_FUNC_GETALLOBJS , 0 , + NV_ACPI_GENERIC_FUNC_GETEVENTLIST , 0 , NVHG_FUNC_GETEVENTLIST , NV_ACPI_DSM_MXM_FUNC_GETEVENTLIST , NV_NBCI_FUNC_GETEVENTLIST , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , + NV_ACPI_GENERIC_FUNC_CALLBACKS , NBSI_FUNC_CALLBACKS , NVHG_FUNC_CALLBACKS , NV_ACPI_DSM_MXM_FUNC_MXCB , NV_NBCI_FUNC_CALLBACKS , 0 , 0 , GPS_FUNC_GETCALLBACKS , 0 , 0 , 0 , GPS_FUNC_GETCALLBACKS , 0 , + NV_ACPI_GENERIC_FUNC_GETBACKLIGHT , 0 , NVHG_FUNC_GETBACKLIGHT , 0 , NV_NBCI_FUNC_GETBACKLIGHT , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , + NV_ACPI_GENERIC_FUNC_MSTL , 0 , 0 , 0 , NV_NBCI_FUNC_MSTL , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , +}; + +/* + * @_getRemappedDsmSubfunction takes as input either a generic DSM subfunction + * or a NBSI subfunction number and returns the subfunction number as appropriate + * for the DSM function desired. + * + * @param[in] acpiDsmFunction ACPI_DSM_FUNCTION DSM call indicator (specific) + * @param[in] acpiDsmSubFunction NvU32 subfunction number (generic) + * @param[out] pRemappedDsmSubFunction NvU32 * pointer to return remapped subfunction number + * + * @returns NV_STATUS of + * NV_ERR_NOT_SUPPORTED if unknown acpi DSM function or the subfunction + * could not be remapped + * NV_OK if subfunction number was remapped + */ + +static NV_STATUS +_getRemappedDsmSubfunction +( + ACPI_DSM_FUNCTION acpiDsmFunction, + NvU32 acpiDsmSubFunction, + NvU32 *pRemappedDsmSubFunction +) +{ + NvU32 i; + + NV_ASSERT_OR_RETURN(pRemappedDsmSubFunction, NV_ERR_INVALID_ARGUMENT); + + // only specific dsm functions are allowed to remap. + NV_ASSERT_OR_RETURN(!isGenericDsmFunction(acpiDsmFunction), NV_ERR_INVALID_ARGUMENT); + + // confirm the acpiDsmSubFunction is a generic acpiDsmSubFunction + NV_ASSERT_OR_RETURN(isGenericDsmSubFunction(acpiDsmSubFunction), NV_ERR_INVALID_ARGUMENT); + + // + // confirm entry rows matches number of DSM functions + // Use NV_ASSERT_OR_ELSE_STR for embedded %. + // + NV_ASSERT_OR_ELSE_STR( + !(NV_ARRAY_ELEMENTS32(genDsmSubFuncRemapTable) % (ACPI_DSM_FUNCTION_COUNT + 1)), + "!(NV_ARRAY_ELEMENTS32(genDsmSubFuncRemapTable) %% (ACPI_DSM_FUNCTION_COUNT + 1))", + return NV_ERR_INVALID_ARGUMENT); + + // find the event in the table + i = 0; + while (i <= (NV_ARRAY_ELEMENTS32(genDsmSubFuncRemapTable) - ACPI_DSM_FUNCTION_COUNT - 1)) + { + if (acpiDsmSubFunction == genDsmSubFuncRemapTable[i]) + { + if (genDsmSubFuncRemapTable[i + acpiDsmFunction + 1]) + { + *pRemappedDsmSubFunction = genDsmSubFuncRemapTable[i + acpiDsmFunction + 1]; + return NV_OK; + } + else + { + // Found the entry in the table. But that function doesn't support that acpiDsmSubFunction. + return NV_ERR_NOT_SUPPORTED; + } + } + i += ACPI_DSM_FUNCTION_COUNT + 1; + } + + // + // someone called us with a generic acpiDsmSubFunction which isn't the table. + // Either add it to the table, or don't use a generic acpiDsmSubFunction. + // + DBG_BREAKPOINT(); + return NV_ERR_OBJECT_NOT_FOUND; +} + +// +// This table defines the order of acpi function GUIDs in which generic +// subfunctions are searched for. +// top priority is first (NVOP). Lowest priority is last (NVPCF). +// +static const ACPI_DSM_FUNCTION dsmOrderOfPrecedenceList[] = + {ACPI_DSM_FUNCTION_NVOP, + ACPI_DSM_FUNCTION_NBCI, + ACPI_DSM_FUNCTION_MXM, + ACPI_DSM_FUNCTION_NVHG, + ACPI_DSM_FUNCTION_NBSI, + ACPI_DSM_FUNCTION_PCFG, + ACPI_DSM_FUNCTION_GPS_2X, + ACPI_DSM_FUNCTION_GPS, + ACPI_DSM_FUNCTION_JT, + ACPI_DSM_FUNCTION_PEX, + ACPI_DSM_FUNCTION_NVPCF_2X, + ACPI_DSM_FUNCTION_NVPCF}; + +/* + * @remapDsmFunctionAndSubFunction remaps generic DSM functions and subfunctions. + * When the function and subfunction are generic, this returns the + * function/subfunction which is enabled in SBIOS ASL for that subfunction. + * When the function is specific and the subfunction is generic it remaps + * the generic subfunction to the matching function number (whether the + * subfunction is enabled or not). + * + * @param[in] pGpu OBJGPU + * @param[in/out] pAcpiDsmFunction ACPI_DSM_FUNCTION * DSM function to remap + * @param[in/out] pRemappedDsmSubFunction NvU32 * subfunction to remap + * + * @returns NV_STATUS of + * NV_ERR_NOT_SUPPORTED if unknown acpi DSM function or the subfunction + * could not be remapped + * NV_OK if subfunction number was remapped + */ +NV_STATUS +remapDsmFunctionAndSubFunction +( + OBJGPU *pGpu, + ACPI_DSM_FUNCTION *pAcpiDsmFunction, + NvU32 *pRemappedDsmSubFunction +) +{ + NvU32 testDSMfuncIndex; + NvU32 remappedDSMSubFunction; + NvU32 dsmIndex; + + NV_ASSERT_OR_RETURN(pAcpiDsmFunction, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pRemappedDsmSubFunction, NV_ERR_INVALID_ARGUMENT); + + NV_PRINTF(LEVEL_INFO, + "ACPI DSM remapping function = %x Subfunction = %x\n", + *pAcpiDsmFunction, *pRemappedDsmSubFunction); + + if (!isGenericDsmFunction(*pAcpiDsmFunction)) + { + // if only subfunction is generic remap it. + if (isGenericDsmSubFunction(*pRemappedDsmSubFunction)) + { + if ((_getRemappedDsmSubfunction(*pAcpiDsmFunction, *pRemappedDsmSubFunction, pRemappedDsmSubFunction)) != NV_OK) + { + return NV_ERR_NOT_SUPPORTED; + } + } + return NV_OK; + } + + // + // Caller asked to use the DSM GUID that supports this subfunction. + // I need generic subfunction numbers so I can remap them to each DSM GUID in the loop. + // + NV_ASSERT_OR_RETURN(isGenericDsmSubFunction(*pRemappedDsmSubFunction), NV_ERR_INVALID_ARGUMENT); + + // If we've done this before and cached the result, return it. + dsmIndex = *pRemappedDsmSubFunction-NV_ACPI_GENERIC_FUNC_START; + if (pGpu->acpi.dsmCurrentFuncSupport & NVBIT(dsmIndex)) + { + *pAcpiDsmFunction = pGpu->acpi.dsmCurrentFunc[dsmIndex]; + *pRemappedDsmSubFunction = pGpu->acpi.dsmCurrentSubFunc[dsmIndex]; + return NV_OK; + } + + // Loop through (in precendence order) to find the GUID/subfunction until we find one that supports the call. + testDSMfuncIndex = 0; + while(testDSMfuncIndex < sizeof(dsmOrderOfPrecedenceList)/sizeof(dsmOrderOfPrecedenceList[0])) + { + // remap the generic subfunction number of the one that matches this function. + if ((_getRemappedDsmSubfunction(dsmOrderOfPrecedenceList[testDSMfuncIndex], *pRemappedDsmSubFunction, &remappedDSMSubFunction)) == NV_OK) + { + // Does this DSM support this subfunction? + if (testIfDsmSubFunctionEnabled(pGpu, dsmOrderOfPrecedenceList[testDSMfuncIndex], remappedDSMSubFunction) == NV_OK) + { + NV_PRINTF(LEVEL_INFO, + "ACPI DSM remap (func=%s/subfunc=0x%x) remapped to (func=%s/subfunc=0x%x).\n", + DSMFuncStr(*pAcpiDsmFunction), + *pRemappedDsmSubFunction, + DSMFuncStr(dsmOrderOfPrecedenceList[testDSMfuncIndex]), + remappedDSMSubFunction); + + // This DSM does support this subfunction. Use it. + *pAcpiDsmFunction = dsmOrderOfPrecedenceList[testDSMfuncIndex]; + *pRemappedDsmSubFunction = remappedDSMSubFunction; + + return NV_OK; + } + } + testDSMfuncIndex++; + } + + return NV_ERR_NOT_SUPPORTED; +} + +/* + * @getDsmGetObjectSubfunction This returns the subfunction numbers for + * the get object by type and get all object calls based on the dsm function + * requested. + * + * @param[in] pGpu OBJGPU + * @param[in/out] pAcpiDsmFunction ACPI_DSM_FUNCTION * DSM function to use/remap + * if generic then will return first function that + * supports get object by type/get all objects. + * @param[out] pGetObjByTypeSubFunction NvU32 * get object by type subfunction. + * @param[out] pGetAllObjsSubFunction NvU32 * get all objs subfunction. + * + * @returns NV_STATUS of + * NV_ERR_NOT_SUPPORTED if unknown acpi DSM function or the subfunction + * could not be remapped + * NV_OK if subfunction number was remapped + */ +NV_STATUS +getDsmGetObjectSubfunction +( + OBJGPU *pGpu, + ACPI_DSM_FUNCTION *pAcpiDsmFunction, + NvU32 *pGetObjByTypeSubFunction, + NvU32 *pGetAllObjsSubFunction +) +{ + NV_STATUS rmStatus = NV_ERR_NOT_SUPPORTED; + NvU32 testDSMfuncIndex; + ACPI_DSM_FUNCTION curFuncForGetObjByType; + ACPI_DSM_FUNCTION curFuncForGetAllObjects; + NvU32 dummySubFunc; + + NV_PRINTF(LEVEL_INFO, "entry *pAcpiDsmFunction = %x\n", + *pAcpiDsmFunction); + + if (*pAcpiDsmFunction == ACPI_DSM_FUNCTION_CURRENT) + { + // determine the function that supports getobjbytype and/or getallobjects + curFuncForGetObjByType = ACPI_DSM_FUNCTION_CURRENT; + dummySubFunc = NV_ACPI_GENERIC_FUNC_GETOBJBYTYPE; + if (remapDsmFunctionAndSubFunction(pGpu, &curFuncForGetObjByType, &dummySubFunc) == NV_OK) + { + // get object by type supported for at least one guid... default to it. + *pAcpiDsmFunction = curFuncForGetObjByType; + + // test get all objects to see if it's higher priority. + curFuncForGetAllObjects = ACPI_DSM_FUNCTION_CURRENT; + dummySubFunc = NV_ACPI_GENERIC_FUNC_GETALLOBJS; + if (remapDsmFunctionAndSubFunction(pGpu, &curFuncForGetAllObjects, &dummySubFunc) == NV_OK) + { + testDSMfuncIndex = 0; + while(testDSMfuncIndex < sizeof(dsmOrderOfPrecedenceList)/sizeof(dsmOrderOfPrecedenceList[0])) + { + if (dsmOrderOfPrecedenceList[testDSMfuncIndex] == curFuncForGetObjByType) + { + // found get object by type first. break now... it's already the default + break; + } else if (dsmOrderOfPrecedenceList[testDSMfuncIndex] == curFuncForGetAllObjects) + { + // found get all objects at higher priority than get object by type... use it. + *pAcpiDsmFunction = curFuncForGetAllObjects; + break; + } + testDSMfuncIndex++; + } + } + } + else + { + curFuncForGetAllObjects = ACPI_DSM_FUNCTION_CURRENT; + dummySubFunc = NV_ACPI_GENERIC_FUNC_GETALLOBJS; + if (remapDsmFunctionAndSubFunction(pGpu, &curFuncForGetAllObjects, &dummySubFunc) != NV_OK) + { + return NV_ERR_NOT_SUPPORTED; + } + // get all objects supported for at least one guid. + *pAcpiDsmFunction = curFuncForGetAllObjects; + } + } + + // determine the get object subfunction numbers for this acpi dsm function. + switch (*pAcpiDsmFunction) + { + case ACPI_DSM_FUNCTION_NBSI: + *pGetObjByTypeSubFunction = NBSI_FUNC_GETOBJBYTYPE; + *pGetAllObjsSubFunction = NBSI_FUNC_GETALLOBJS; + rmStatus = NV_OK; + break; + + case ACPI_DSM_FUNCTION_NVHG: + *pGetObjByTypeSubFunction = NVHG_FUNC_GETOBJBYTYPE; + *pGetAllObjsSubFunction = NVHG_FUNC_GETALLOBJS; + rmStatus = NV_OK; + break; + + case ACPI_DSM_FUNCTION_NBCI: + *pGetObjByTypeSubFunction = NV_NBCI_FUNC_GETOBJBYTYPE; + *pGetAllObjsSubFunction = NV_NBCI_FUNC_GETALLOBJS; + rmStatus = NV_OK; + break; + + case ACPI_DSM_FUNCTION_NVOP: + *pGetObjByTypeSubFunction = NVOP_FUNC_GETOBJBYTYPE; + *pGetAllObjsSubFunction = NVOP_FUNC_GETALLOBJS; + rmStatus = NV_OK; + break; + + case ACPI_DSM_FUNCTION_GPS_2X: /* fallthrough */ + case ACPI_DSM_FUNCTION_GPS: + *pGetObjByTypeSubFunction = GPS_FUNC_GETOBJBYTYPE; + *pGetAllObjsSubFunction = GPS_FUNC_GETALLOBJS; + rmStatus = NV_OK; + break; + + case ACPI_DSM_FUNCTION_PCFG: + case ACPI_DSM_FUNCTION_PEX: + default: + rmStatus = NV_ERR_NOT_SUPPORTED; + break; + } + + NV_PRINTF(LEVEL_INFO, + "exit *pAcpiDsmFunction = 0x%x *pGetObjByTypeSubFunction=0x%x, status=%x\n", + *pAcpiDsmFunction, *pGetObjByTypeSubFunction, + rmStatus); + + return rmStatus; +} + +/* + * @checkDsmCall checks if the function/subfunction call should be performed + * Generic function/subfunctions are remapped to real/current functions and + * subfunctions. + * + * Notes on handling the Get supported functions list cache. + * 1) Initially the cache status is set to DSM_FUNC_STATUS_UNKNOWN. + * 2) First time osCallACPI_DSM is called for get supported functions list + * 2A) The cache status is DSM_FUNC_STATUS_UNKNOWN so it changes the cache + * state to DSM_FUNC_STATUS_FAILED and + * returns NV_WARN_MORE_PROCESSING_REQUIRED so + * osCallACPI_DSM will do the actual call. + * 2B) after doing the actual call osCallACPI_DSM calls + * cacheDsmSupportedFunction which caches (on success) the return data + * and changes the cache state to DSM_FUNC_STATUS_SUCCESS. + * If the call failed, the cache state is left at DSM_FUNC_STATUS_FAILED. + * 3) Later calls from osCallACPI_DSM to get supported functions list. + * 3A) If the cache status is DSM_FUNC_STATUS_SUCCESS... return cache and + * status NV_OK. + * 3B) If the cache status is DSM_FUNC_STATUS_FAILED... return status + * NV_ERR_OPERATING_SYSTEM + * + * The return status when subfunction is get supported functions list is either + * 1) NV_OK status... pInOut has cached copy... no more processing required. + * 2) NV_WARN_MORE_PROCESSING_REQUIRED status... osCallACPI_DSM should + * continue on and try the subfunction. + * 3) NV_ERR_OPERATING_SYSTEM status... if the call previously failed. + * 4) NV_ERR_BUFFER_TOO_SMALL status... if the buffer is too small. + * + * For subfunctions other than get supported subfunction return options are: + * 1) If the subfunction should be tried it returns NV_WARN_MORE_PROCESSING_REQUIRED. + * 2) If the subfunction should not be tried it returns NV_ERR_NOT_SUPPORTED + * + * @param[in] pGpu OBJGPU + * @param[in/out] pAcpiDsmFunction ACPI_DSM_FUNCTION * DSM function + * on return this may be remapped if + * current/generic function was input. + * @param[in/out] pAcpiDsmSubFunction NvU32 * DSM subfunction to use. + * on return this may be remapped if + * current/generic subfunction was input. + * @param[out] pInOut NvU32 * pointer to return get supported return + * data previously cached (if requested). + * @param[in/out] pSize NvU32 * size of data in pInOut. On input is + * size of pInOut. On output is size of data + * returned if get supported subfunction call is + * used. + * + * @returns NV_STATUS of + * NV_OK all processing is complete. Used when returning the cached + * copy of get supported functions list. + * NV_WARN_MORE_PROCESSING_REQUIRED call to subfunction should be + * performed. + * NV_ERR_NOT_SUPPORTED Unable to remap function/subfunction. + * NV_ERR_BUFFER_TOO_SMALL pInOut is too small to return cached data. + * NV_ERR_OPERATING_SYSTEM subfunction is not enabled. + */ +NV_STATUS +checkDsmCall +( + OBJGPU *pGpu, + ACPI_DSM_FUNCTION *pAcpiDsmFunction, + NvU32 *pAcpiDsmSubFunction, + NvU32 *pInOut, + NvU16 *pSize +) +{ + NV_STATUS rmStatus = NV_ERR_NOT_SUPPORTED; + + NV_ASSERT_OR_RETURN(pAcpiDsmFunction, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pAcpiDsmSubFunction, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pInOut, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pSize, NV_ERR_INVALID_ARGUMENT); + + // Do any remapping of subfunction if function is current + if (remapDsmFunctionAndSubFunction(pGpu, pAcpiDsmFunction, pAcpiDsmSubFunction) != NV_OK) + { + return NV_ERR_NOT_SUPPORTED; + } + + NV_ASSERT_OR_RETURN(*pAcpiDsmFunction < ACPI_DSM_FUNCTION_COUNT, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(*pAcpiDsmSubFunction < NV_ACPI_GENERIC_FUNC_START, NV_ERR_INVALID_ARGUMENT); + + if (isDsmGetSuppFuncListCached(pGpu, *pAcpiDsmFunction)) + { + if (*pAcpiDsmSubFunction == NV_ACPI_ALL_FUNC_SUPPORT) + { + if (*pSize < pGpu->acpi.dsm[*pAcpiDsmFunction].suppFuncsLen) + { + return NV_ERR_BUFFER_TOO_SMALL; + } + else + { + // Return the cached values. + *pSize = (NvU16) pGpu->acpi.dsm[*pAcpiDsmFunction].suppFuncsLen; + portMemCopy((NvU8 *)pInOut, + *pSize, + (NvU8 *)pGpu->acpi.dsm[*pAcpiDsmFunction].suppFuncs, + *pSize); + return NV_OK; + } + } + else + { + // not subfunction 0... check cached supported functions list + rmStatus = testIfDsmSubFunctionEnabled(pGpu, *pAcpiDsmFunction, *pAcpiDsmSubFunction); + if (rmStatus != NV_OK) + { + // subfunction is not enabled in get supported subfunction list. + return rmStatus; + } + } + } + else + { + // haven't cached get supported functions yet... or it's failed. + if (isDsmGetSuppFuncListFailed(pGpu, *pAcpiDsmFunction)) + { + // get supported subfunctions call failed before. Don't try again. + return NV_ERR_OPERATING_SYSTEM; + } + + // assert if subfunction 0 is not the first one called. + NV_ASSERT_OR_RETURN(*pAcpiDsmSubFunction == NV_ACPI_ALL_FUNC_SUPPORT, NV_ERR_INVALID_ARGUMENT); + } + + if (*pAcpiDsmSubFunction == NV_ACPI_ALL_FUNC_SUPPORT) + { + pGpu->acpi.dsm[*pAcpiDsmFunction].suppFuncStatus = DSM_FUNC_STATUS_FAILED; + } + + // indicate we can go ahead and read it. + return NV_WARN_MORE_PROCESSING_REQUIRED; +} + +static void +_acpiDsmSupportedFuncCacheInit +( + OBJGPU *pGpu +) +{ + ACPI_DSM_FUNCTION func; + NV_STATUS status = NV_OK; + NvU16 rtnSize; + NvU8 supportFuncs[MAX_DSM_SUPPORTED_FUNCS_RTN_LEN]; + + // Just checking to make sure this is correct! + NV_ASSERT_OR_RETURN_VOID(0 == ACPI_DSM_FUNCTION_NBSI); + + // + // loop through all guids. The read will cache the subfunction list (if + // available) + // + for(func = ACPI_DSM_FUNCTION_NBSI; func < ACPI_DSM_FUNCTION_COUNT; func++) + { + if ((func == ACPI_DSM_FUNCTION_GPS) && + (pGpu->acpi.dsm[ACPI_DSM_FUNCTION_GPS_2X].suppFuncStatus == DSM_FUNC_STATUS_SUCCESS)) + { + // + // If GPS_2X is supported, skip checking leagacy GPS 1X. + // + continue; + } + + // + // Skip over non-NBCI since we don't want to waste boot time here on Tegra + // Remove this if we want to support other ACPI functions. + // + if (IsTEGRA(pGpu) && (func != ACPI_DSM_FUNCTION_NBCI)) + { + if (pGpu->acpi.dsm[func].suppFuncStatus == DSM_FUNC_STATUS_UNKNOWN) + { + pGpu->acpi.dsm[func].suppFuncStatus = DSM_FUNC_STATUS_FAILED; + } + } + + if ((pGpu->acpi.dsm[func].suppFuncStatus == DSM_FUNC_STATUS_OVERRIDE) || + (pGpu->acpi.dsm[func].suppFuncStatus == DSM_FUNC_STATUS_FAILED)) + { + // + // skip reading the supported functions if + // it's been over-ridden or previously failed. + // + continue; + } + + + // try package type for argument 3. + pGpu->acpi.dsm[func].bArg3isInteger = NV_FALSE; + rtnSize = sizeof(supportFuncs); + status = pGpu->pOS->osCallACPI_DSM(pGpu, + func, + NV_ACPI_ALL_FUNC_SUPPORT, + (NvU32 *) &supportFuncs, + &rtnSize); + if (status != NV_OK) + { + if (status == NV_ERR_INVALID_ARGUMENT) + { + // maybe an older SBIOS, try integer type for argument 3. + pGpu->acpi.dsm[func].bArg3isInteger = NV_TRUE; + rtnSize = sizeof(supportFuncs); + status = pGpu->pOS->osCallACPI_DSM(pGpu, + func, + NV_ACPI_ALL_FUNC_SUPPORT, + (NvU32 *) &supportFuncs, + &rtnSize); + } + } + if (_isDsmError(status, rtnSize, (NvU32 *) &supportFuncs)) + { + NV_PRINTF(LEVEL_INFO, + "%s DSM function not present in ASL.\n", + DSMFuncStr(func)); + // + // If the call didn't set the failed status force it now. + // This might be because the call is stubbed out. + // + pGpu->acpi.dsm[func].suppFuncStatus = DSM_FUNC_STATUS_FAILED; + } + + } +} + +static void +_acpiDsmCallbackInit +( + OBJGPU *pGpu +) +{ + ACPI_DSM_FUNCTION func; + NV_STATUS status = NV_OK; + NvU32 callbacks; + NvU16 rtnSize; + NvU32 testDSMfuncIndex; + // lowest priority is first entry, highest priority is last entry + + // this list only includes GUIDS with callbacks. + ACPI_DSM_FUNCTION callbackOrderOfPrecedenceList[] = + { + ACPI_DSM_FUNCTION_NBCI, + ACPI_DSM_FUNCTION_NVHG, + ACPI_DSM_FUNCTION_MXM, + ACPI_DSM_FUNCTION_GPS_2X, + ACPI_DSM_FUNCTION_GPS, + }; + + // Initialize these now. + pGpu->acpi.dispStatusHotplugFunc = ACPI_DSM_FUNCTION_COUNT; + pGpu->acpi.dispStatusConfigFunc = ACPI_DSM_FUNCTION_COUNT; + pGpu->acpi.perfPostPowerStateFunc = ACPI_DSM_FUNCTION_COUNT; + pGpu->acpi.stereo3dStateActiveFunc = ACPI_DSM_FUNCTION_COUNT; + + // Loop through the list of GUIDs that support callbacks in priority order + for (testDSMfuncIndex = 0; + testDSMfuncIndex < (sizeof(callbackOrderOfPrecedenceList)/sizeof(callbackOrderOfPrecedenceList[0])); + testDSMfuncIndex++) + { + func = callbackOrderOfPrecedenceList[testDSMfuncIndex]; + pGpu->acpi.dsm[func].callbackStatus = DSM_FUNC_STATUS_FAILED; + + rtnSize = sizeof(callbacks); + callbacks = 0; + + if ((func == ACPI_DSM_FUNCTION_GPS) && + (pGpu->acpi.dsm[ACPI_DSM_FUNCTION_GPS_2X].callbackStatus == DSM_FUNC_STATUS_SUCCESS)) + { + // + // If GPS_2X has enabled callback, skip leagacy GPS 1X. + // + continue; + } + + if (testIfDsmSubFunctionEnabled(pGpu, func, NV_ACPI_GENERIC_FUNC_CALLBACKS) == NV_OK) + { + status = pGpu->pOS->osCallACPI_DSM(pGpu, + func, + NV_ACPI_GENERIC_FUNC_CALLBACKS, + &callbacks, + &rtnSize); + + if (_isDsmError(status, rtnSize, &callbacks)) + { + NV_PRINTF(LEVEL_ERROR, + "SBIOS suggested %s supports function %d, but the call failed!\n", + DSMFuncStr(func), + NV_ACPI_GENERIC_FUNC_CALLBACKS); + } + else + { + pGpu->acpi.dsm[func].callback = callbacks; + pGpu->acpi.dsm[func].callbackStatus = DSM_FUNC_STATUS_SUCCESS; + + // replace lower priority hotplug callback. + if (FLD_TEST_DRF(_ACPI, _CALLBACKS_RET, _HOTPLUG, _NOTIFY, pGpu->acpi.dsm[func].callback)) + { + pGpu->acpi.dispStatusHotplugFunc = func; + } + + // replace lower priority status config callback. + if (FLD_TEST_DRF(_ACPI, _CALLBACKS_RET, _CONFIG, _NOTIFY, pGpu->acpi.dsm[func].callback)) + { + pGpu->acpi.dispStatusConfigFunc = func; + } + + // replace lower priority status config callback. + if (FLD_TEST_DRF(_ACPI, _CALLBACKS_RET, _POSTPOWERSTATE, _NOTIFY, pGpu->acpi.dsm[func].callback)) + { + pGpu->acpi.perfPostPowerStateFunc = func; + } + + // replace 3D stereo active state callback. + if (FLD_TEST_DRF(_ACPI, _CALLBACKS_RET, _3DSTEREOSTATE_ACTIVE, _NOTIFY, pGpu->acpi.dsm[func].callback)) + { + pGpu->acpi.stereo3dStateActiveFunc = func; + } + + } + } + } +} + + +/* + * @brief Initialize the ACPI DSM caps related information + * + * @param[in] pGpu OBJGPU pointer + * + * @returns + */ +static void +_acpiDsmCapsInit +( + OBJGPU *pGpu +) +{ + ACPI_DSM_FUNCTION func; + NV_STATUS status = NV_OK; + NvU32 platCaps; + NvU16 rtnSize; + NvU32 asmDsmSubFunction; + + // handle the NBCI specific platcaps init. + func = ACPI_DSM_FUNCTION_NBCI; + asmDsmSubFunction = NV_NBCI_FUNC_PLATCAPS; + if (testIfDsmSubFunctionEnabled(pGpu, func, asmDsmSubFunction) == NV_OK) + { + rtnSize = sizeof(platCaps); + status = pGpu->pOS->osCallACPI_DSM(pGpu, + func, + asmDsmSubFunction, + &platCaps, + &rtnSize); + + if (_isDsmError(status, rtnSize, &platCaps)) + { + NV_PRINTF(LEVEL_ERROR, + "SBIOS suggested %s supports function %d, but the call failed!\n", + DSMFuncStr(func), asmDsmSubFunction); + } + else + { + // cache for later retrieval + pGpu->acpi.dsmPlatCapsCache[func] = platCaps; + + } + } +} + +/* + * @brief Initialize the cache of generic function/subfunctions + * + * @param[in] pGpu OBJGPU pointer + * + * @returns + */ +static void +_acpiGenFuncCacheInit +( + OBJGPU *pGpu +) +{ + NvU32 testGenSubFunc; + NvU32 dsmIndex; + NV_STATUS status = NV_OK; + + // create a bitwise list of generic dsm supported functions available. + pGpu->acpi.dsmCurrentFuncSupport = 0; + + // Loop through each generic subfunction, determine which is active available. + for (testGenSubFunc = NV_ACPI_GENERIC_FUNC_START; testGenSubFunc <= NV_ACPI_GENERIC_FUNC_LAST_SUBFUNCTION; testGenSubFunc++) + { + dsmIndex = testGenSubFunc-NV_ACPI_GENERIC_FUNC_START; + + pGpu->acpi.dsmCurrentFunc[dsmIndex] = ACPI_DSM_FUNCTION_CURRENT; + pGpu->acpi.dsmCurrentSubFunc[dsmIndex] = testGenSubFunc; + + // + // This remaps the generic function/subfunction if it can. + // If not available it leaves it as ACPI_DSM_FUNCTION_CURRENT and the generic subfunction. + // + + status = remapDsmFunctionAndSubFunction(pGpu, &pGpu->acpi.dsmCurrentFunc[dsmIndex], &pGpu->acpi.dsmCurrentSubFunc[dsmIndex]); + if (status == NV_OK) + { + if (pGpu->acpi.dsmCurrentFunc[dsmIndex] == ACPI_DSM_FUNCTION_CURRENT) + { + NV_PRINTF(LEVEL_INFO, + "DSM Generic subfunction 0x%x is not supported. Leaving entry at func %s subfunction 0x%x.\n", + testGenSubFunc, + DSMFuncStr(pGpu->acpi.dsmCurrentFunc[dsmIndex]), + pGpu->acpi.dsmCurrentSubFunc[dsmIndex]); + } + else + { + // set the bit indicating we do support this generic dsm subfunction. + pGpu->acpi.dsmCurrentFuncSupport |= NVBIT(dsmIndex); + NV_PRINTF(LEVEL_INFO, + "DSM Generic subfunction 0x%x supported. Mapping to func %s subfunction 0x%x\n", + testGenSubFunc, + DSMFuncStr(pGpu->acpi.dsmCurrentFunc[dsmIndex]), + pGpu->acpi.dsmCurrentSubFunc[dsmIndex]); + } + } + else + { + NV_PRINTF(LEVEL_INFO, + "DSM Test generic subfunction 0x%x is not supported. Indicates possible table corruption.\n", + testGenSubFunc); + } + } +} + +/* + * @brief Initialize the ACPI DSM features such as mdtl support. + * + * @param[in] pGpu OBJGPU pointer + * + * @returns + */ +static void +_acpiDsmFeatureInit +( + OBJGPU *pGpu +) +{ + if (pGpu->acpi.MDTLFeatureSupport == DSM_FUNC_STATUS_UNKNOWN) + { + // + // The mdtl feature requires both mdtl and displaystatus subfunctions supported. + // We could add verify more validity checks like... + // 1) Read in the MDTL table and confirming the contents are valid + // 2) Try the displaystatus status command and see it returns valid data. + // For now, we trust the SBIOS ASL. If it tells us this is supported then + // the rest will work as well. + // + if ((testIfDsmSubFunctionEnabled(pGpu, ACPI_DSM_FUNCTION_CURRENT, NV_ACPI_GENERIC_FUNC_MDTL) == NV_OK) && + (testIfDsmSubFunctionEnabled(pGpu, ACPI_DSM_FUNCTION_CURRENT, NV_ACPI_GENERIC_FUNC_DISPLAYSTATUS) == NV_OK)) + { + pGpu->acpi.MDTLFeatureSupport = DSM_FUNC_STATUS_SUCCESS; + } + else + { + pGpu->acpi.MDTLFeatureSupport = DSM_FUNC_STATUS_FAILED; + } + } +} + +static void +_acpiCacheMethodData +( + OBJGPU *pGpu +) +{ + NV_STATUS status; + OBJOS *pOs = GPU_GET_OS(pGpu); + NvU32 inOut = 0; + NvU16 rtnSize = sizeof(inOut); + NvU32 tableLen = 0, acpiidIndex = 0, mode = 0, muxPartId = 0; + + // This bit is used for checking if pGpu::acpiMethodData need to be used or not. + pGpu->acpiMethodData.bValid = NV_TRUE; + + // Fill in the DOD Method Data. + pGpu->acpiMethodData.dodMethodData.acpiIdListLen = sizeof(pGpu->acpiMethodData.dodMethodData.acpiIdList); + + status = pOs->osCallACPI_DOD(pGpu, pGpu->acpiMethodData.dodMethodData.acpiIdList, &pGpu->acpiMethodData.dodMethodData.acpiIdListLen); + + pGpu->acpiMethodData.dodMethodData.status = status; + + // Fill in the JT Method Data. + status = pOs->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_JT, JT_FUNC_CAPS, &inOut, &rtnSize); + + pGpu->acpiMethodData.jtMethodData.status = status; + pGpu->acpiMethodData.jtMethodData.jtCaps = inOut; + pGpu->acpiMethodData.jtMethodData.jtRevId = (NvU16)DRF_VAL(_JT_FUNC, _CAPS, _REVISION_ID, inOut); + + // Fill in the MUX Method Data. + portMemSet(pGpu->acpiMethodData.muxMethodData.acpiIdMuxModeTable, 0, sizeof(pGpu->acpiMethodData.muxMethodData.acpiIdMuxModeTable)); + portMemSet(pGpu->acpiMethodData.muxMethodData.acpiIdMuxPartTable, 0, sizeof(pGpu->acpiMethodData.muxMethodData.acpiIdMuxPartTable)); + if (pGpu->acpiMethodData.dodMethodData.status == NV_OK) + { + tableLen = pGpu->acpiMethodData.dodMethodData.acpiIdListLen / sizeof(NvU32); + pGpu->acpiMethodData.muxMethodData.tableLen = tableLen; + for (acpiidIndex = 0; acpiidIndex < tableLen; acpiidIndex++) + { + status = pOs->osCallACPI_MXDM(pGpu, pGpu->acpiMethodData.dodMethodData.acpiIdList[acpiidIndex], &mode); + pGpu->acpiMethodData.muxMethodData.acpiIdMuxModeTable[acpiidIndex].acpiId = pGpu->acpiMethodData.dodMethodData.acpiIdList[acpiidIndex]; + pGpu->acpiMethodData.muxMethodData.acpiIdMuxModeTable[acpiidIndex].mode = mode; + pGpu->acpiMethodData.muxMethodData.acpiIdMuxModeTable[acpiidIndex].status = status; + + status = pOs->osCallACPI_MXID(pGpu, pGpu->acpiMethodData.dodMethodData.acpiIdList[acpiidIndex], &muxPartId); + pGpu->acpiMethodData.muxMethodData.acpiIdMuxPartTable[acpiidIndex].acpiId = pGpu->acpiMethodData.dodMethodData.acpiIdList[acpiidIndex]; + pGpu->acpiMethodData.muxMethodData.acpiIdMuxPartTable[acpiidIndex].mode = muxPartId; + pGpu->acpiMethodData.muxMethodData.acpiIdMuxPartTable[acpiidIndex].status = status; + mode = muxPartId = 0; + } + } + + // Fill in the Optimus caps Method Data. + status = pGpu->pOS->osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_NVOP, NVOP_FUNC_OPTIMUSCAPS, + &pGpu->acpiMethodData.capsMethodData.optimusCaps, &rtnSize); + pGpu->acpiMethodData.capsMethodData.status = status; +} + +/* + * @brief Initialize the ACPI Device Specific Methods + * + * @param[in] pGpu OBJGPU pointer + * + * @returns + */ + +void acpiDsmInit +( + OBJGPU *pGpu +) +{ + // initialize the cache of the supported Functions list. + _acpiDsmSupportedFuncCacheInit(pGpu); + _acpiGenFuncCacheInit(pGpu); + _acpiDsmCallbackInit(pGpu); + _acpiDsmCapsInit(pGpu); + _acpiDsmFeatureInit(pGpu); + _acpiCacheMethodData(pGpu); +} + +/*! + * @brief Get NBSI object data accordingly by global source through ACPI function + * + * @param[in] pGpu OBJGPU pointer + * @param[out] pNbsiObjData NBSI object data + * @param[in] pSzOfpNbsiObjData Size of NBSI object data + * @param[in] acpiFunction ACPI function + * @param[in] objType NBSI global object type + * @param[in] validateOption NBSI valitation option + * + * @returns NV_OK All processing is complete. + * @returns NV_ERR_NOT_SUPPORTED NBSI function not supported. + * @returns NV_ERR_BUFFER_TOO_SMALL pNbsiObjData is too small to return cached data. + * @returns NV_ERR_GENERIC Otherwise. + */ +NV_STATUS +getAcpiDsmObjectData +( + OBJGPU *pGpu, + NvU8 **pNbsiObjData, + NvU32 *pSzOfpNbsiObjData, + ACPI_DSM_FUNCTION acpiFunction, + NBSI_GLOB_TYPE objType, + NBSI_VALIDATE validateOption +) +{ + NV_STATUS status; + NvU32 rtnStatus; + NBSI_SOURCE_LOC globSrc; + NvU8 globIdx; + NvU32 totalGlobSize; + + NV_ASSERT(pNbsiObjData); + NV_ASSERT(pSzOfpNbsiObjData); + + // read best fit, but leave size 0 so it returns the size. + globIdx = 0; + if ((acpiFunction == ACPI_DSM_FUNCTION_NBSI) || + (acpiFunction == ACPI_DSM_FUNCTION_NBCI) || + (acpiFunction == ACPI_DSM_FUNCTION_CURRENT)) + { + globSrc = 0; // scan all NBSI/NBCI sources + } + else + { + globSrc = NBSI_TBL_SOURCE_ACPI; + } + + status = getNbsiObjByType(pGpu, objType, &globSrc, &globIdx, 0, *pNbsiObjData, pSzOfpNbsiObjData, &totalGlobSize, &rtnStatus, acpiFunction, validateOption); + if (status == NV_OK) + { + status = NV_ERR_GENERIC; + + // got it + if (rtnStatus == NV2080_CTRL_BIOS_GET_NBSI_SUCCESS) + { + status = NV_OK; + } + + // almost got it but a bad hash was found. + if (rtnStatus == NV2080_CTRL_BIOS_GET_NBSI_BAD_HASH) + { + NV_PRINTF(LEVEL_INFO, + "ACPI DSM object (type=0x%x) signature check failed!\n", + objType); + status = NV_ERR_GENERIC; + return status; + } + + // couldn't fit it + if (rtnStatus == NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE) + { + // return the actual size needed + *pSzOfpNbsiObjData = totalGlobSize; + status = NV_ERR_BUFFER_TOO_SMALL; + } + } + + return status; +} + +/* + * Clear DSM function cache status + * + * @param[in] pGpu OBJGPU + * @param[in] acpiDsmFunction ACPI_DSM_FUNCTION DSM function + * @param[in] acpiDsmSubFunction NvU32 + */ +void uncacheDsmFuncStatus +( + OBJGPU *pGpu, + ACPI_DSM_FUNCTION acpiDsmFunction, + NvU32 acpiDsmSubFunction +) +{ + if (acpiDsmSubFunction == NV_ACPI_ALL_FUNC_SUPPORT) + { + pGpu->acpi.dsm[acpiDsmFunction].suppFuncsLen = 0; + pGpu->acpi.dsm[acpiDsmFunction].suppFuncStatus = DSM_FUNC_STATUS_UNKNOWN; + } +} diff --git a/src/nvidia/src/kernel/platform/chipset/chipset.c b/src/nvidia/src/kernel/platform/chipset/chipset.c index e3e9f4fc3..ce73e6864 100644 --- a/src/nvidia/src/kernel/platform/chipset/chipset.c +++ b/src/nvidia/src/kernel/platform/chipset/chipset.c @@ -22,7 +22,7 @@ */ -/***************************** HW State Rotuines ***************************\ +/***************************** HW State Routines ***************************\ * Core Logic Object Function Definitions. * \***************************************************************************/ @@ -133,6 +133,9 @@ clInitMappingPciBusDevice_IMPL NvU16 vendorID, deviceID; NvBool bFoundDevice = NV_FALSE; + if (IsT194(pGpu)) + return NV0000_CTRL_GPU_INVALID_ID; + // do we already know our domain/bus/device? if (gpuGetDBDF(pGpu) == 0) { @@ -791,5 +794,6 @@ void clSyncWithGsp_IMPL(OBJCL *pCl, GspSystemInfo *pGSI) pGSI->Chipset = pCl->Chipset; pGSI->FHBBusInfo = pCl->FHBBusInfo; + pGSI->chipsetIDInfo = pCl->chipsetIDInfo; } diff --git a/src/nvidia/src/kernel/platform/chipset/chipset_info.c b/src/nvidia/src/kernel/platform/chipset/chipset_info.c index 6091a0c44..fcd531cd3 100644 --- a/src/nvidia/src/kernel/platform/chipset/chipset_info.c +++ b/src/nvidia/src/kernel/platform/chipset/chipset_info.c @@ -32,6 +32,7 @@ #include "core/system.h" #include "os/os.h" #include "nvpcie.h" +#include "nvdevid.h" #include "nvcst.h" @@ -1261,18 +1262,6 @@ Fujitsu_A64FX_setupFunc return NV_OK; } -// Phytium FT2000 Setup Function -static NV_STATUS -Phytium_FT2000_setupFunc -( - OBJCL *pCl -) -{ - // TODO Need to check if any more PDB properties should be set - pCl->setProperty(pCl, PDB_PROP_CL_IS_CHIPSET_IO_COHERENT, NV_TRUE); - return NV_OK; -} - // Ampere Quicksilver Setup Function static NV_STATUS Ampere_Altra_setupFunc diff --git a/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c b/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c index d1bdc063d..757d26fdd 100644 --- a/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c +++ b/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c @@ -47,6 +47,7 @@ #include "core/thread_state.h" #include "nveGPUConfig.h" #include "Nvcm.h" +#include "nvdevid.h" #include "published/maxwell/gm107/dev_nv_xve.h" // NV_XVE_VCCAP_CTRL0* #include "published/pcie_switch/pcie_switch_ref.h" @@ -854,7 +855,7 @@ clUpdatePcieConfig_IMPL(OBJGPU *pGpu, OBJCL *pCl) // A dagwood board would not have bIsGemini flag set but would have // bIsMultiGpu flag set. // - bIsMultiGpu = gpuIsMultiGpuBoard(pGpu, NULL, &bIsGemini); + bIsMultiGpu = gpuIsMultiGpuBoard(pGpu, &bIsGemini); if (bIsGemini) { pGpu->setProperty(pGpu, PDB_PROP_GPU_IS_GEMINI, NV_TRUE); @@ -1916,7 +1917,7 @@ clCountBR_IMPL // // clSearchBR04() returns the bus, revision of the BR04s in the system, // and their count. -// It ignores the BR04s located in GX2 boards. +// It ignores the BR04s located in Gemini boards. // It includes BR04s located on the motherboard, or on a riser board. // void @@ -1954,7 +1955,7 @@ clSearchBR04_IMPL // // Look at the devices connected to this BR04. - // If it is a GX2 GPU, then skip. + // If it is a Gemini GPU, then skip. // BR04 has one upstream port and 2 to 4 downstream ports. // We look at the downstream ports of BR04. // We explicitely look for at least 2 BR04 downstream ports. @@ -1968,7 +1969,7 @@ clSearchBR04_IMPL { // // We have one potential downstream port - // Look to if a GX2 GPU is connected to this BR04 + // Look to if a Gemini GPU is connected to this BR04 // pBusTopologyInfoBR04GPU = pCl->pBusTopologyInfo; while (pBusTopologyInfoBR04GPU) @@ -2262,7 +2263,6 @@ clFindBR_IMPL NvU32 regValue = 0; NvU32 gpuBrNot3rdPartyCount = 0, gpuBrCount = 0; NvBool bGpuIsMultiGpuBoard = NV_FALSE; - NvBool bIsGX2 = NV_FALSE; NvBool bIsGemini = NV_FALSE; NvU32 gpuBR04Count = 0; NvU8 BR03Bus = 0xFF; @@ -2280,7 +2280,7 @@ clFindBR_IMPL &vendorIDUp, &deviceIDUp, &downstreamPortBus1); - bGpuIsMultiGpuBoard = gpuIsMultiGpuBoard(pGpu, &bIsGX2, &bIsGemini); + bGpuIsMultiGpuBoard = gpuIsMultiGpuBoard(pGpu, &bIsGemini); // Traverse the pci tree while (handleUp) @@ -2334,9 +2334,9 @@ clFindBR_IMPL &funcUp, &vendorIDUp, &deviceIDUp); } - if ((bIsGX2 || bIsGemini) && gpuBR04Count) + if (bIsGemini && gpuBR04Count) { - // Ignore one BR04 in case of GX2 or Gemini + // Ignore one BR04 in case of Gemini gpuBR04Count--; } if (gpuBR04Count) @@ -3341,6 +3341,7 @@ NV_STATUS AMD_RP1630_setupFunc(OBJGPU *pGpu, OBJCL *pCl) return NV_OK; } + static NV_STATUS objClGpuIs3DController(OBJGPU *pGpu) { @@ -3461,9 +3462,6 @@ clAreGpusBehindSameBridge_IMPL * Pulls the devid info out of the pGpu to pass to gpuDevIdIsMultiGpuBoard(). * * @param[in] pGpu OBJGPU pointer - * @param[out] pbIsGX2 NvBool pointer in which to store whether GPU an an SLI - * mutliboard config. May be NULL if caller does not - * care to receive this information. * @parma[out] pbIsGemini NvBool pointer in which to store whether GPU is a * Gemini multiboard config. May be NULL if caller does * not care to receive this information. @@ -3474,13 +3472,10 @@ NvBool gpuIsMultiGpuBoard ( OBJGPU *pGpu, - NvBool *pbIsGX2, NvBool *pbIsGemini ) { - if (pbIsGX2 != NULL) - *pbIsGX2 = NV_FALSE; if (pbIsGemini != NULL) *pbIsGemini = NV_FALSE; @@ -4415,6 +4410,7 @@ clChipsetAspmPublicControl_IMPL NvU32 linkControlRegOffset = PCIECapPtr + 0x10; NvU32 regVal; + // sanity check if (aspmState > CL_PCIE_LINK_CTRL_STATUS_ASPM_MASK) { NV_PRINTF(LEVEL_ERROR, "Invalid ASPM state passed.\n"); @@ -4526,3 +4522,774 @@ NvBool clRootportNeedsNosnoopWAR_FWCLIENT(OBJGPU *pGpu, OBJCL *pCl) return pSCI->bClRootportNeedsNosnoopWAR; } + +/*! + * @brief determine the size of the specified PCI capability on the specified device. + * + * @param[in] deviceHandle handle to the device whose capability we are getting the size for + * @param[in] capId the ID of the capacity we want to get the size for + * @param[in] capOffset the offset in the PCIE configuration space where the capacity is located + * + * @return NvU16 size of the requested capacity. + * + */ +static NvU16 _clPcieGetPcieCapSize(void *deviceHandle, NvU16 capType, NvU16 capId, NvU16 capOffset) +{ + NvU16 capSize = 0; + NvU32 tempDword; + NvU16 count; + NvU16 idx; + + if (deviceHandle == NULL) + { + return 0; + } + switch (capType) + { + case RM_PCIE_DC_CAP_TYPE_PCI: + switch (capId) + { + case CAP_ID_NULL: + capSize = CAP_NULL_SIZE; + break; + + case CAP_ID_PMI: + capSize = CAP_PMI_SIZE; + break; + + case CAP_ID_VPD: + capSize = CAP_VPD_SIZE; + break; + + case CAP_ID_MSI: + capSize = PCI_MSI_BASE_SIZE; + tempDword = osPciReadWord(deviceHandle, capOffset + PCI_MSI_CONTROL); + + if (FLD_TEST_REF(PCI_MSI_CONTROL_64BIT_CAPABLE, _TRUE, tempDword)) + { + capSize += PCI_MSI_64BIT_ADDR_CAPABLE_ADJ_SIZE; + } + if (FLD_TEST_REF(PCI_MSI_CONTROL_PVM_CAPABLE, _TRUE, tempDword)) + { + capSize += PCI_MSI_PVM_CAPABLE_ADJ_SIZE; + } + break; + + case CAP_ID_PCI_EXPRESS: + capSize = CAP_PCI_EXPRESS_SIZE; + break; + + case CAP_ID_MSI_X: + capSize = PCI_MSI_X_BASE_SIZE; + // todo: add table collection + break; + + case CAP_ID_ENHANCED_ALLOCATION: + tempDword = osPciReadByte(deviceHandle, PCI_HEADER_TYPE0_HEADER_TYPE); + switch (tempDword) + { + case PCI_HEADER_TYPE0_HEADER_TYPE_0: + capSize = PCI_ENHANCED_ALLOCATION_TYPE_0_BASE_SIZE; + break; + + case PCI_HEADER_TYPE0_HEADER_TYPE_1: + capSize = PCI_ENHANCED_ALLOCATION_TYPE_0_BASE_SIZE; + break; + + default: + break; + } + // get the entry count. + if (capSize != 0) + { + tempDword = osPciReadDword(deviceHandle, capOffset + PCI_ENHANCED_ALLOCATION_FIRST_DW); + count = REF_VAL(PCI_ENHANCED_ALLOCATION_FIRST_DW_NUM_ENTRIES, tempDword); + for (idx = 0; idx < count; ++idx) + { + tempDword = osPciReadDword(deviceHandle, capOffset + capSize + PCI_ENHANCED_ALLOCATION_ENTRY_HEADER); + tempDword = REF_VAL(PCI_ENHANCED_ALLOCATION_ENTRY_HEADER_ENTRY_SIZE, tempDword); + capSize += (NvU16)((tempDword + 1) * NV_SIZEOF32(NvU32)); + } + } + break; + + case CAP_ID_FPB: + capSize = CAP_FPB_SIZE; + break; + + case CAP_ID_AF: + capSize = CAP_AF_SIZE; + break; + + case CAP_ID_SUBSYSTEM_ID: + capSize = CAP_SUBSYSTEM_ID_SIZE; + break; + + case CAP_ID_AGP: + case CAP_ID_SLOT_ID: + case CAP_ID_HOT_SWAP: + case CAP_ID_PCI_X: + case CAP_ID_HYPER_TRANSPORT: + case CAP_ID_DEBUG_PORT: + case CAP_ID_CRC: + case CAP_ID_HOT_PLUG: + case CAP_ID_AGP8X: + case CAP_ID_SECURE: + // don't know the sizes of these capabilities right now so just grab 32 bytes; + capSize = 32; + break; + + default: + // this is an unrecognized capability. + // Assume it is a Vendor Specific capability + tempDword = osPciReadDword(deviceHandle, capOffset + PCI_VENDOR_SPECIFIC_CAP_HEADER); + capSize = REF_VAL(PCI_VENDOR_SPECIFIC_CAP_HEADER_LENGTH, tempDword); + break; + } + break; + + case RM_PCIE_DC_CAP_TYPE_PCIE: + switch (capId) + { + case PCIE_CAP_ID_SECONDARY_PCIE_CAPABILITY: + capSize = PCIE_CAP_SECONDARY_PCIE_SIZE; + break; + + case PCIE_CAP_ID_DATA_LINK: + capSize = PCIE_CAP_DATA_LINK_SIZE; + break; + + case PCIE_CAP_ID_PHYSLAYER_16_GT: + capSize = PCIE_CAP_PHYSLAYER_16_GT_SIZE; + break; + + case PCIE_CAP_ID_PHYSLAYER_32_GT: + capSize = PCIE_CAP_PHYSLAYER_32_GT_SIZE; + break; + + case PCIE_CAP_ID_PHYSLAYER_64_GT: + capSize = PCIE_CAP_PHYSLAYER_64_GT_SIZE; + break; + + case PCIE_CAP_ID_FLT_LOGGING: + capSize = PCIE_CAP_FLT_LOGGING_SIZE; + break; + + case PCIE_CAP_ID_DEVICE_3: + capSize = PCIE_CAP_DEVICE_3_SIZE; + break; + + case PCIE_CAP_ID_LANE_MARGINING_AT_RECEVER: + capSize = PCIE_CAP_LANE_MARGINING_AT_RECEVER_SIZE; + break; + + case PCIE_CAP_ID_ACS: + capSize = PCIE_CAP_ACS_SIZE; + break; + + case PCIE_CAP_ID_POWER: + capSize = PCIE_CAP_POWER_SIZE; + break; + + case PCIE_CAP_ID_LATENCY_TOLERANCE: + capSize = PCIE_CAP_LATENCY_TOLERANCE_SIZE; + break; + + case PCIE_CAP_ID_L1_PM_SUBSTATES: + capSize = PCIE_CAP_L1_PM_SUBSTATE_SIZE; + break; + + case PCIE_CAP_ID_ERROR: + capSize = PCIE_CAP_ERROR_SIZE; + break; + + case PCIE_CAP_ID_RESIZABLE_BAR: + capSize = PCIE_CAP_RESIZABLE_BAR_SIZE; + break; + + case PCIE_CAP_ID_VF_RESIZABLE_BAR: + capSize = PCIE_CAP_VF_RESIZABLE_BAR_SIZE; + break; + + case PCIE_CAP_ID_ARI: + capSize = PCIE_CAP_ARI_SIZE; + break; + + case PCIE_CAP_ID_PASID: + capSize = PCIE_CAP_PASID_SIZE; + break; + + case PCIE_CAP_ID_FRS_QUEUING: + capSize = PCIE_CAP_FRS_QUEUING_SIZE; + break; + + case PCIE_CAP_ID_FLIT_PERF_MEASURMENT: + capSize = PCIE_CAP_FLIT_PERF_MEASURMENT_SIZE; + break; + + case PCIE_CAP_ID_FLIT_ERROR_INJECTION: + capSize = PCIE_CAP_FLIT_ERROR_INJECTION_SIZE; + break; + + case PCIE_CAP_ID_VC: + capSize = PCIE_VIRTUAL_CHANNELS_BASE_SIZE; + tempDword = osPciReadDword(deviceHandle, capOffset + PCIE_VC_REGISTER_1); + count = REF_VAL(PCIE_VC_REGISTER_1_EXTENDED_VC_COUNT, tempDword); + capSize += count * PCIE_VIRTUAL_CHANNELS_EXTENDED_VC_ENTRY_SIZE; + // to do: add arbitration tables. + break; + + case PCIE_CAP_ID_PCIE_CAP_ID_MFVC: + capSize = PCIE_PCIE_CAP_ID_MFVC_BASE_SIZE; + tempDword = osPciReadDword(deviceHandle, capOffset + PCIE_MFVC_REGISTER_1); + count = REF_VAL(PCIE_MFVC_REGISTER_1_EXTENDED_VC_COUNT, tempDword); + capSize += count * PCIE_PCIE_CAP_ID_MFVC_EXTENDED_VC_ENTRY_SIZE; + // to do: add arbitration tables. + break; + + case PCIE_CAP_ID_SERIAL: + capSize = PCIE_CAP_DEV_SERIAL_SIZE; + break; + + case PCIE_CAP_ID_VENDOR_SPECIFIC: + tempDword = osPciReadDword(deviceHandle, capOffset + PCIE_VENDOR_SPECIFIC_HEADER_1); + capSize = REF_VAL(PCIE_VENDOR_SPECIFIC_HEADER_1_LENGTH, tempDword); + break; + + case PCIE_CAP_ID_RCRB: + capSize = PCIE_CAP_RCRB_SIZE; + break; + + case PCIE_CAP_ID_ROOT_COMPLEX: + capSize = PCIE_ROOT_COMPLEX_BASE_SIZE; + tempDword = osPciReadDword(deviceHandle, capOffset + PCIE_ROOT_COMPLEX_SELF_DESC_REGISTER); + count = REF_VAL(PCIE_ROOT_COMPLEX_SELF_DESC_REGISTER_NUM_LINK_ENTRIES, tempDword); + capSize += count * PCIE_ROOT_COMPLEX_LINK_ENTRY_SIZE; + break; + + case PCIE_CAP_ID_ROOT_COMPLEX_INTERNAL_LINK_CTRL: + capSize = PCIE_CAP_ROOT_COMPLEX_INTERNAL_LINK_CTRL_SIZE; + break; + + case PCIE_CAP_ID_ROOT_COMPLEX_EVENT_COLLECTOR_ENDPOINT: + capSize = PCIE_CAP_ROOT_COMPLEX_EVENT_COLLECTOR_ENDPOINT_SIZE; + break; + + case PCIE_CAP_ID_MULTICAST: + capSize = PCIE_CAP_MULTICAST_SIZE; + break; + + case PCIE_CAP_ID_DYNAMIC_POWER_ALLOCATION: + capSize = PCIE_CAP_DYNAMIC_POWER_ALLOCATION_SIZE; + break; + + case PCIE_CAP_ID_TPH: + capSize = PCIE_TPH_BASE_SIZE; + tempDword = osPciReadDword(deviceHandle, capOffset + PCIE_TPH_REQUESTOR_REGISTER); + count = REF_VAL(PCIE_TPH_REQUESTOR_REGISTER_ST_TABLE_SIZE, tempDword); + capSize += count * PCIE_TPH_ST_ENTRY_SIZE; + break; + + case PCIE_CAP_ID_DPC: + capSize = PCIE_CAP_DPC_SIZE; + break; + + case PCIE_CAP_ID_PTM: + capSize = PCIE_CAP_PTM_SIZE; + break; + + case PCIE_CAP_ID_READINESS_TIME_REPORTING: + capSize = PCIE_CAP_READINESS_TIME_REPORTING_SIZE; + break; + + case PCIE_CAP_ID_HIERARCHY_ID: + capSize = PCIE_CAP_HIERARCHY_ID_SIZE; + break; + + case PCIE_CAP_ID_NPEM: + capSize = PCIE_CAP_NPEM_SIZE; + break; + + case PCIE_CAP_ID_ALTERNATE_PROTOCOL: + capSize = PCIE_CAP_ALTERNATE_PROTOCOL_SIZE; + break; + + case PCIE_CAP_ID_SFI: + capSize = PCIE_CAP_SFI_SIZE; + break; + + case PCIE_CAP_ID_DATA_OBJECT_EXCHANGE: + capSize = PCIE_CAP_DATA_OBJECT_EXCHANGE_SIZE; + break; + + case PCIE_CAP_ID_SHADOW_FUNCTIONS: + capSize = PCIE_CAP_SHADOW_FUNCTIONS_SIZE; + break; + + case PCIE_CAP_ID_IDE: + capSize = PCIE_CAP_IDE_SIZE; + break; + + case PCIE_CAP_ID_NULL: + capSize = PCIE_CAP_NULL_SIZE; + break; + + default: + // this is an unrecognized capability. + // so just grab the header so we can try to figure out what it is + // (unlike PCI Capabilities PCIE has a specific ID for vendor specific capabilities, + // so any unrecognized capability is something we do not support) + capSize = PCIE_CAP_HEADER_SIZE; + break; + } + break; + } + return capSize; +} + +/*! + * @brief create a map of the locations of the capabilities of the specified type of the specified type. + * + * @param[in] deviceHandle handle to the device whose capability we are getting the size for + * @param[in] type the type of capabilities we are mapping (PCI vs PCIE) + * @param[out] capMap a map of the capabilities found in the configuration space + * + * @return NvU16 size of the requested capacity. + */ +static NvU16 _clPciePopulateCapMap(void * pDeviceHandle, NvU16 type, CL_PCIE_DC_CAPABILITY_MAP * pCapMap) +{ + NvU32 tempDword; + NvU16 blkOffset = 0; + + if (pCapMap == NULL) + { + return 0; + } + // clear the capability map. + portMemSet(pCapMap, 0, NV_SIZEOF32(*pCapMap)); + + // if there is not a valid device handle, we are done. + if (pDeviceHandle == NULL) + { + return 0; + } + + // get the offset to the first block depending on type + switch (type) + { + case RM_PCIE_DC_CAP_TYPE_PCI: + blkOffset = osPciReadByte(pDeviceHandle, PCI_HEADER_TYPE0_CAP_PTR); + break; + case RM_PCIE_DC_CAP_TYPE_PCIE: + blkOffset = PCIE_CAPABILITY_BASE; + break; + default: + return 0; + break; + } + // run thru the capabilities until we run out of capabilities, + // or run out of space + while (blkOffset != 0) + { + // save the offset of the capability + pCapMap->entries[pCapMap->count].blkOffset = blkOffset; + + // get the capability id & location of next capability + switch (type) + { + case RM_PCIE_DC_CAP_TYPE_PCI: + // read the capability header + tempDword = osPciReadWord(pDeviceHandle, blkOffset); + + // extract the capability id + pCapMap->entries[pCapMap->count].id = REF_VAL(PCI_CAP_HEADER_ID, tempDword); + + // extract the offset for the next capability + blkOffset = REF_VAL(PCI_CAP_HEADER_NEXT, tempDword); + break; + + case RM_PCIE_DC_CAP_TYPE_PCIE: + // read the capability header + tempDword = osPciReadDword(pDeviceHandle, blkOffset); + + // extract the capability id + pCapMap->entries[pCapMap->count].id = REF_VAL(PCIE_CAP_HEADER_ID, tempDword); + + // extract the offset for the next capability + blkOffset = REF_VAL(PCIE_CAP_HEADER_NEXT, tempDword); + break; + } + // move on to the next entry. + pCapMap->count++; + + if (pCapMap->count >= NV_ARRAY_ELEMENTS(pCapMap->entries)) + { + // we've run out of space + break; + } + } + return pCapMap->count; +} + +/*! + * @brief copy a block of data from the PCI config space to a buffer. + * + * @param[out] pBuffer a pointer to the buffer that the collected data will be copied to + * @param[out] bufferSz the size of the buffer the data will be stored in + * @param[in] deviceHandle handle to the device whose data is being collected + * @param[in] base the offset of the data to be collected in config space + * @param[out] blockSz size of the data to be collected. + * + * @return NvU16 size of the collected. + */ +static NvU16 _clPcieCopyConfigSpaceDiagData(NvU8* pBuffer, NvU32 bufferSz, void *pDeviceHandle, NvU32 base, NvU32 blockSz) +{ + NvU32 offset = base; + NvU16 dataSz = 0; + + if ((pBuffer == NULL) || (bufferSz == 0) || (pDeviceHandle == NULL) || blockSz > (bufferSz)) + { + return 0; + } + + // switch on the boundary we are at so we can do whatever we need to reach a dword boundary. + switch (offset & 0x03) + { + case 0: // we are at a dword boundary. move on to the DWORD copies + break; + + case 1: // we are on a byte boundary, read a byte to get us to a word boundary + case 3: + *pBuffer = osPciReadByte(pDeviceHandle, offset); + pBuffer += 1; + offset += 1; + dataSz += 1; + + // did we reach a dword boundary? + if ((offset & 0x03) == 0) + { + break; + } + // fall thru to read next word & bring us to a DWORD boundary; + + case 2: // we are on a word boundary, + // if we need at least a word of data, + // read another word to get us to a dword boundary + // if we need less than a word, we will pick it up below. + if ((blockSz - dataSz) > 1) + { + *((NvU16*)pBuffer) = osPciReadWord(pDeviceHandle, offset); + pBuffer += 2; + offset += 2; + dataSz += 2; + } + break; + } + + // do all the full dword reads + for (; (blockSz - dataSz) >= sizeof(NvU32); dataSz += NV_SIZEOF32(NvU32)) + { + // read a dword of data + *((NvU32*)pBuffer) = osPciReadDword(pDeviceHandle, offset); + + // update the references to the next data to be read/written. + pBuffer += NV_SIZEOF32(NvU32); + offset += NV_SIZEOF32(NvU32); + } + + // we are at the nearest dword boundary to the end of the block. + // read any remaining data. + switch (blockSz - dataSz) + { + default: // something is wrong, we shouldn't have more than 3 bytes to get. + break; + + case 0: // we have everything we want. + break; + + case 2: // we have at least a word left, read the word. + case 3: + *((NvU16*)pBuffer) = osPciReadWord(pDeviceHandle, offset); + pBuffer += 2; + offset += 2; + dataSz += 2; + // did we get everything? + if ((blockSz - dataSz) == 0) + { + break; + } + // fall thru to grab the last byte. + + case 1: // we have 1 byte left, read it as a byte. + *pBuffer = osPciReadByte(pDeviceHandle, offset); + dataSz += 1; + break; + } + return dataSz; +} + +/*! + * @brief Save the header & data for a diagnostic block + * + * @param[in] pDeviceHandle handle of device we are collecting data from + * if NULL data will not be collected from config space + * @param[in] pScriptEntry pointer to collection script entry we are collecting data for + * may be NULL in which case only the data is transferred + * @param[in] blkOffset offset in PCIE config space we are collecting + * @param[in] blkSize size of the block in config space we are collecting + * @param[out] pBuffer pointer to diagnostic output buffer + * @param[in] bufferSize size of diagnostic output buffer + * + * @return NvU16 size of diagnostic data collected. + */ +NvU16 _clPcieSavePcieDiagnosticBlock(void *pDeviceHandle, CL_PCIE_DC_DIAGNOSTIC_COLLECTION_ENTRY *pScriptEntry, NvU16 blkOffset, NvU16 blkSize, void * pBuffer, NvU32 size) +{ + CL_PCIE_DC_DIAGNOSTIC_COLLECTION_ENTRY *pBlkHeader; + NvU16 collectedDataSize = 0; + + // do some parameter checks + if ((pBuffer == NULL) + || ((blkOffset + NV_SIZEOF32(*pBlkHeader) + blkSize) > PCI_EXTENDED_CONFIG_SPACE_LENGTH) + || ((NV_SIZEOF32(*pBlkHeader) + blkSize) > size)) + { + return 0; + } + if (pScriptEntry != NULL) + { + // copy the block header & update the size + pBlkHeader = (CL_PCIE_DC_DIAGNOSTIC_COLLECTION_ENTRY*)pBuffer; + *pBlkHeader = *pScriptEntry; + collectedDataSize += NV_SIZEOF32(*pBlkHeader); + } + if((pDeviceHandle != NULL) + && (0 < blkSize) + && (pBuffer != NULL)) + { + // get the data block + collectedDataSize += _clPcieCopyConfigSpaceDiagData(&(((NvU8*)pBuffer)[collectedDataSize]), size - collectedDataSize, + pDeviceHandle, + blkOffset, blkSize); + } + return collectedDataSize; +} + +/*! + * @brief Retrieve diagnostic information to be used to identify the cause of errors based on a provided script + * + * @param[in] pGpu GPU object pointer + * @param[in] pScript pointer to collection script + * @param[in] count number of entries in the collection script + * @param[out] pBuffer pointer to diagnostic output buffer + * @param[in] bufferSize size of diagnostic output buffer + * + * @return NvU16 size of diagnostic data collected. + */ +NvU16 _clPcieGetDiagnosticData(OBJGPU *pGpu, CL_PCIE_DC_DIAGNOSTIC_COLLECTION_ENTRY *pScript, NvU16 count, NvU8 * pBuffer, NvU32 size) +{ + static volatile NvS32 capMapWriteLock = 0; + static volatile NvBool capMapInitialized = NV_FALSE; + static CL_PCIE_DC_CAPABILITY_MAP + capMap[RM_PCIE_DEVICE_COUNT][RM_PCIE_DC_CAP_TYPE_COUNT]; + NBADDR *pUpstreamPort = NULL; + NvU32 domain = 0; + NvU8 bus = 0; + NvU8 device = 0; + NvU16 vendorId, deviceId; + void *pPCIeHandles[RM_PCIE_DEVICE_COUNT]; + NvU16 collectedDataSize = 0; + NvU16 idx; + NvU16 idx2; + CL_PCIE_DC_CAPABILITY_MAP + *pActiveMap = NULL; + CL_PCIE_DC_DIAGNOSTIC_COLLECTION_ENTRY + blkHeader; + NvU16 capType; + NvBool bCollectAll; + + if ((pGpu == NULL) || (pBuffer == NULL) || (size == 0) || IS_RTLSIM(pGpu)) + { + return 0; + } + portMemSet(pPCIeHandles, 0, NV_SIZEOF32(pPCIeHandles)); + + // get PCIE Handles. + pUpstreamPort = &pGpu->gpuClData.upstreamPort.addr; + pPCIeHandles[RM_PCIE_DEVICE_TYPE_UPSTREAM_BRIDGE] = osPciInitHandle(pUpstreamPort->domain, + pUpstreamPort->bus, + pUpstreamPort->device, + 0, + &vendorId, + &deviceId); + if (osGpuReadReg032(pGpu, PCI_HEADER_TYPE0_VENDOR_ID) == pGpu->chipId0) + { + domain = gpuGetDomain(pGpu); + bus = gpuGetBus(pGpu); + device = gpuGetDevice(pGpu); + pPCIeHandles[RM_PCIE_DEVICE_TYPE_GPU] = osPciInitHandle(domain, bus, device, 0, &vendorId, &deviceId); + } + + // run thru the collection script entries. + for (idx = 0; idx < count; idx++) + { + blkHeader = pScript[idx]; + // verify there is space, & we can access the device. + if ((size - collectedDataSize) < (NV_SIZEOF32(blkHeader) + blkHeader.length)) + { + // if this block doesn't fit, skip it but continue because another block might. + continue; + } + if (pPCIeHandles[blkHeader.deviceType] == NULL) + { + continue; + } + switch (blkHeader.action) + { + case RM_PCIE_ACTION_NOP: + break; + + case RM_PCIE_ACTION_COLLECT_CONFIG_SPACE: + collectedDataSize += _clPcieSavePcieDiagnosticBlock(pPCIeHandles[blkHeader.deviceType], + &blkHeader, + blkHeader.locator, blkHeader.length, + &pBuffer[collectedDataSize], size - collectedDataSize); + break; + + case RM_PCIE_ACTION_COLLECT_PCI_CAP_STRUCT: + case RM_PCIE_ACTION_COLLECT_PCIE_CAP_STRUCT: + case RM_PCIE_ACTION_COLLECT_ALL_PCI_CAPS: + case RM_PCIE_ACTION_COLLECT_ALL_PCIE_CAPS: + + if (portAtomicIncrementS32(&capMapWriteLock) == 1) + { + if (!capMapInitialized) + { + // map out all the capabilities + for (idx = 0; idx < NV_ARRAY_ELEMENTS(capMap); idx++) + { + for (idx2 = 0; idx2 < NV_ARRAY_ELEMENTS(capMap[0]); idx2++) + { + _clPciePopulateCapMap(pPCIeHandles[idx], idx2, &capMap[idx][idx2]); + } + } + capMapInitialized = NV_TRUE; + } + } + portAtomicDecrementS32(&capMapWriteLock); + + if (!capMapInitialized) + { + break; + } + // figure out which map to use. + switch (blkHeader.action) + { + case RM_PCIE_ACTION_COLLECT_PCI_CAP_STRUCT: + case RM_PCIE_ACTION_COLLECT_ALL_PCI_CAPS: + capType = RM_PCIE_DC_CAP_TYPE_PCI; + break; + + case RM_PCIE_ACTION_COLLECT_PCIE_CAP_STRUCT: + case RM_PCIE_ACTION_COLLECT_ALL_PCIE_CAPS: + capType = RM_PCIE_DC_CAP_TYPE_PCIE; + break; + default: + // will never happen, but having this default handling + // deals with Linux compiler capType may not be initialized before use warning. + capType = RM_PCIE_DC_CAP_TYPE_NONE; + break; + } + + // even if I don't think it can happen, need to check for it. + if (capType == RM_PCIE_DC_CAP_TYPE_NONE) + { + break; + } + pActiveMap = &capMap[blkHeader.deviceType][capType]; + + // collect the data using the map determined above + switch (blkHeader.action) + { + default: // default needed to satisfy Linux compiler. + case RM_PCIE_ACTION_COLLECT_PCI_CAP_STRUCT: + case RM_PCIE_ACTION_COLLECT_PCIE_CAP_STRUCT: + bCollectAll = NV_FALSE; + break; + + case RM_PCIE_ACTION_COLLECT_ALL_PCI_CAPS: + case RM_PCIE_ACTION_COLLECT_ALL_PCIE_CAPS: + bCollectAll = NV_TRUE; + break; + } + // find the requested capability within the specified type + for (idx2 = 0; idx2 < pActiveMap->count; idx2++) + { + if (bCollectAll || (pActiveMap->entries[idx2].id == blkHeader.locator)) + { + blkHeader.locator = pActiveMap->entries[idx2].id; + + // determine the size of the capability + blkHeader.length = + _clPcieGetPcieCapSize(pPCIeHandles[blkHeader.deviceType], + capType, blkHeader.locator, pActiveMap->entries[idx2].blkOffset); + collectedDataSize += _clPcieSavePcieDiagnosticBlock(pPCIeHandles[blkHeader.deviceType], + &blkHeader, + pActiveMap->entries[idx2].blkOffset, blkHeader.length, + &pBuffer[collectedDataSize], size - collectedDataSize); + } + } + break; + + case RM_PCIE_ACTION_REPORT_PCI_CAPS_COUNT: + blkHeader.length = capMap[blkHeader.deviceType][RM_PCIE_DC_CAP_TYPE_PCI].count; + collectedDataSize += _clPcieSavePcieDiagnosticBlock(NULL, + &blkHeader, + 0, 0, + &pBuffer[collectedDataSize], size - collectedDataSize); + break; + + case RM_PCIE_ACTION_REPORT_PCIE_CAPS_COUNT: + blkHeader.length = capMap[blkHeader.deviceType][RM_PCIE_DC_CAP_TYPE_PCIE].count; + collectedDataSize += _clPcieSavePcieDiagnosticBlock(NULL, + &blkHeader, + 0, 0, + &pBuffer[collectedDataSize], size - collectedDataSize); + break; + + case RM_PCIE_ACTION_EOS: + idx = count; + break; + + default: + break; + } + } + return collectedDataSize; +} + +/*! + * @brief Retrieve diagnostic information to be used to identify the cause of GPU Lost + * + * @param[in] pGpu GPU object pointer + * @param[in] pBif BIF object pointer + * @param[out] pBuffer pointer to diagnostic output buffer + * @param[in] bufferSize size of diagnostic output buffer + * + * @return NvU32 size of diagnostic data collected. + */ +NvU16 clPcieGetGpuLostDiagnosticData_IMPL(OBJGPU *pGpu, OBJCL *pCl, NvU8 * pBuffer, NvU32 size) +{ + static CL_PCIE_DC_DIAGNOSTIC_COLLECTION_ENTRY gpuLostCollectionScript[] = + { + { RM_PCIE_ACTION_COLLECT_CONFIG_SPACE, RM_PCIE_DEVICE_TYPE_UPSTREAM_BRIDGE, 0x000, 0x40 }, + { RM_PCIE_ACTION_COLLECT_CONFIG_SPACE, RM_PCIE_DEVICE_TYPE_GPU, 0x000, 0x40 }, + { RM_PCIE_ACTION_COLLECT_ALL_PCI_CAPS, RM_PCIE_DEVICE_TYPE_GPU, 0, 0 }, + { RM_PCIE_ACTION_COLLECT_ALL_PCIE_CAPS, RM_PCIE_DEVICE_TYPE_GPU, 0, 0 }, + { RM_PCIE_ACTION_COLLECT_ALL_PCI_CAPS, RM_PCIE_DEVICE_TYPE_UPSTREAM_BRIDGE, 0, 0 }, + { RM_PCIE_ACTION_COLLECT_ALL_PCIE_CAPS, RM_PCIE_DEVICE_TYPE_UPSTREAM_BRIDGE, 0, 0 }, + { RM_PCIE_ACTION_EOS, RM_PCIE_DEVICE_TYPE_NONE, 0, 0 } + }; + + return _clPcieGetDiagnosticData(pGpu, + gpuLostCollectionScript, NV_ARRAY_ELEMENTS32(gpuLostCollectionScript), + pBuffer, size); +} diff --git a/src/nvidia/src/kernel/platform/cpu.c b/src/nvidia/src/kernel/platform/cpu.c index 779a33648..ce8854d26 100644 --- a/src/nvidia/src/kernel/platform/cpu.c +++ b/src/nvidia/src/kernel/platform/cpu.c @@ -159,9 +159,6 @@ void RmInitCpuInfo(void) case AARCH64_VENDOR_PART(NVIDIA, DENVER_2): pSys->cpuInfo.type = NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_2_0; break; - case AARCH64_VENDOR_PART(NVIDIA, ESTES_1): - pSys->cpuInfo.type = NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC; - break; case AARCH64_VENDOR_PART(NVIDIA, CARMEL): pSys->cpuInfo.type = NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC; diff --git a/src/nvidia/src/kernel/platform/cpu_arm_def.h b/src/nvidia/src/kernel/platform/cpu_arm_def.h index 42e028a7f..dfa8da2a5 100644 --- a/src/nvidia/src/kernel/platform/cpu_arm_def.h +++ b/src/nvidia/src/kernel/platform/cpu_arm_def.h @@ -74,7 +74,6 @@ extern void CP_WRITE_CSSELR_REGISTER(NvU32 val); #define CP_MIDR_PRIMARY_PART_NUM_DENVER_1 0x0 #define CP_MIDR_PRIMARY_PART_NUM_DENVER_2 0x3 #define CP_MIDR_PRIMARY_PART_NUM_CARMEL 0x4 -#define CP_MIDR_PRIMARY_PART_NUM_ESTES_1 0x9 #define CP_MIDR_PRIMARY_PART_NUM_XGENE 0x0 #define CP_MIDR_PRIMARY_PART_NUM_CORTEX_A57 0xd07 diff --git a/src/nvidia/src/kernel/platform/guids.c b/src/nvidia/src/kernel/platform/guids.c new file mode 100644 index 000000000..aff58a98b --- /dev/null +++ b/src/nvidia/src/kernel/platform/guids.c @@ -0,0 +1,96 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/** + * @file + * @brief This module defines several guids. + */ + +#include "nvcd.h" + +#define DECLSPEC_SELECTANY + +// Special GUID definition to get around pre-compiled header definition +// We need to define the GUID value here and not just generate a reference +#define GUID_CONST(name, l, w1, w2, b1, b2, b3, b4, b5, b6, b7, b8) \ + const GUID DECLSPEC_SELECTANY name \ + = { l, w1, w2, { b1, b2, b3, b4, b5, b6, b7, b8 } } + + +// _DSM NVHG GUID {9D95A0A0-0060-4d48-B34D-7E5FEA129FD4} +GUID_CONST (NVHG_DSM_GUID, + 0x9D95A0A0L, 0x0060, 0x4d48, 0xB3, 0x4D, 0x7E, 0x5F, 0xEA, 0x12, 0x9F, 0xD4); +// Buffer(0x10){0xA0, 0xA0, 0x95, 0x9D, 0x60, 0x00, 0x48, 0x4d, 0xB3, 0x4D, 0x7E, 0x5F, 0xEA, 0x12, 0x9F, 0xD4}, + +// _DSM NBSI NVHG GUID {998669A6-8BE9-49FB-BDDB-51A1EFE19C3D} +GUID_CONST (NBSI_DSM_GUID, + 0x998669A6L, 0x8BE9, 0x49FB, 0xBD, 0xDB, 0x51, 0xA1, 0xEF, 0xE1, 0x9C, 0x3D); +// Buffer(0x10){0xA6, 0x69, 0x86, 0x99, 0xE9, 0x8B, 0xFB, 0x49, 0xBD, 0xDB, 0x51, 0xA1, 0xEF, 0xE1, 0x9C, 0x3D}, + +// _DSM SPB GUID {95DB88FD-940A-4253-A446-70CE0504AEDF} +GUID_CONST (SPB_DSM_GUID, + 0x95DB88FDL, 0x940A, 0x4253, 0xA4, 0x46, 0x70, 0xCE, 0x05, 0x04, 0xAE, 0xDF); +// Buffer(0x10){0xFD, 0x88, 0xDB, 0x95, 0x0A, 0x94, 0x53, 0x42, 0xA4, 0x46, 0x70, 0xCE, 0x05, 0x04, 0xAE, 0xDF}, + +// _DSM NBCI GUID {D4A50B75-65C7-46F7-BFB7-41514CEA0244} +GUID_CONST (NBCI_DSM_GUID, + 0xD4A50B75L, 0x65C7, 0x46F7, 0xBF, 0xB7, 0x41, 0x51, 0x4C, 0xEA, 0x02, 0x44); +// Buffer(0x10){0x75, 0x0B, 0xA5, 0xD4, 0xC7, 0x65, 0xF7, 0x46, 0xBF, 0xB7, 0x41, 0x51, 0x4C, 0xEA, 0x02, 0x44}, + +// _DSM NVOP GUID {A486D8F8-0BDA-471B-A72B-6042A6B5BEE0} +GUID_CONST (NVOP_DSM_GUID, + 0xA486D8F8L, 0x0BDA, 0x471B, 0xA7, 0x2B, 0x60, 0x42, 0xA6, 0xB5, 0xBE, 0xE0); +// Buffer(0x10){0xF8, 0xD8, 0x86, 0xA4, 0xDA, 0x0B, 0x1B, 0x47, 0xA7, 0x2B, 0x60, 0x42, 0xA6, 0xB5, 0xBE, 0xE0}, + +// _DSM PCFG GUID {81C6147D-735F-42D9-9E41-B002CBC6571D} +GUID_CONST (PCFG_DSM_GUID, + 0x81C6147DL, 0x735F, 0x42D9, 0x9E, 0x41, 0xB0, 0x02, 0xCB, 0xC6, 0x57, 0x1D); +// Buffer(0x10){0x7D, 0x14, 0C6, 0x81, 0x5F, 0x73, 0xD9, 0x42, 0x9E, 0x41, 0xB0, 0x02, 0xCB, 0xC6, 0x57, 0x1D}, + +// _DSM GPS GUID {A3132D01-8CDA-49BA-A52E-BC9D46DF6B81} +GUID_CONST (GPS_DSM_GUID, + 0xA3132D01L, 0x8CDA, 0x49BA, 0xA5, 0x2E, 0xBC, 0x9D, 0x46, 0xDF, 0x6B, 0x81); + +// _DSM_ JT GUID {CBECA351-067B-4924-9CBD-B46B00B86F34} +GUID_CONST (JT_DSM_GUID, + 0xCBECA351L, 0x067B, 0x4924, 0x9C, 0xBD, 0xB4, 0x6B, 0x00, 0xB8, 0x6F, 0x34); + +// PCI Express DSM GUID + +// _DSM_ PEX GUID {E5C937D0-3553-4D7A-9117-EA4D19C3434D} +GUID_CONST (PEX_DSM_GUID, + 0xE5C937D0L, 0x3553, 0x4D7A, 0x91, 0x17, 0xEA, 0x4D, 0x19, 0xC3, 0x43, 0x4D); + +// NVPCF GUID +GUID_CONST (NVPCF_ACPI_DSM_GUID, + 0x36B49710L, 0x2483, 0x11E7, 0x95, 0x98, 0x08, 0x00, 0x20, 0x0C, 0x9A, 0x66); + +// UEFI variables +GUID_CONST (NV_GUID_UEFI_VARIABLE, + 0x7a09bc55L, 0x83e8, 0x4d4d, 0x93, 0xb0, 0x89, 0xd8, 0x0e, 0xed, 0xb7, 0x20); + +// _DSM MXM GUID {4004A400-917D-4cf2-B89C-79B62FD55665} +GUID_CONST (DSM_MXM_GUID, + 0x4004A400L, 0x917D, 0x4cf2, 0xB8, 0x9C, 0x79, 0xB6, 0x2F, 0xD5, 0x56, 0x65); +// Buffer(0x10){0x00, 0xA4, 0x04, 0x40, 0x7D, 0x91, 0xF2, 0x4C, 0xB8, 0x9C, 0x79, 0xB6, 0x2F, 0xD5, 0x56, 0x65}, + diff --git a/src/nvidia/src/kernel/platform/nbsi/nbsi_getv.c b/src/nvidia/src/kernel/platform/nbsi/nbsi_getv.c new file mode 100644 index 000000000..821229b18 --- /dev/null +++ b/src/nvidia/src/kernel/platform/nbsi/nbsi_getv.c @@ -0,0 +1,452 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * @file + * @brief NBSI table initialization, search and hash routines. + */ + +#include "os/os.h" +#include "platform/nbsi/nbsi_table.h" +#include "platform/nbsi/nbsi_read.h" +#include "nvlimits.h" +#include "gpu/gpu.h" + +//---------------------------------------------------------------------------- +// NV_STATUS rtnNbsiElement(n, moduleID, thisPathHash, thisElementHash, +// pNbsiElement, * pRetBuf, * pRetSize, * pErrorCode) + +// This function searches the nbsi registry entry of the matching element. +// +// Input parameters: +// n - index into element array (for debug output) +// thisPathHash - pathHash (for debug output) +// thisElementHash - element hash (for debug output) +// pNbsiElement - pointer to this Element +// pRetBuf - pointer to return buffer +// pRetSize - pointer to return size +// pErrorCode - pointer to return error code +// +// Returns NV_STATUS of NV_OK or NV_ERR_GENERIC. +// NV_OK: The table is present and no table integrity issues found +// NV_ERR_GENERIC: The table is not present or a table integrity issue was +// found. +// +// Output parameters: +// pRetSize - If the element is found in the table pRetSize contains +// the size of the element (4 for byte/word/dword) or +// the array size. If the element size is larger than +// the pRetBuf size, the element is not copied but the size +// is updated. +// pErrorCode - status of search (when status = NV_OK) +// NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND: element not present in table +// NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE: element larger than pRetSize +// NV2080_CTRL_BIOS_GET_NBSI_SUCCESS: element was found and placed +// at pRetBuf, pRetSize updated to size of element. +// Note: byte, word and dword entries in the table are all +// converted to a dword. +// +//---------------------------------------------------------------------------- +static NV_STATUS rtnNbsiElement +( + NvU32 n, + NvU32 moduleID, + NvU16 thisPathHash, + NvU32 thisElementHash, + PNBSI_ELEMENT pNbsiElement, + NvU8 * pRetBuf, + NvU32 * pRetSize, + NvU32 * pErrorCode +) +{ + NvU32 elementSize; + NvU32 rtnData; + NvU16 nullTerm = 0; + NvU8 * pRetBufEnd; + + NV_ASSERT(pErrorCode); + NV_ASSERT(pRetSize); + NV_ASSERT(!(*pRetSize != 0 && pRetBuf == NULL)); + // + // We've found the element. Default return status to incomplete + // to indicate entry doesn't fit return location. Later we'll + // change that when we find out it does fit (and make the + // successfull copy). + // + *pErrorCode = NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE; + switch (pNbsiElement->hdrPartA.type) + { + case NBSI_BYTE_ARRAY: + elementSize = pNbsiElement->data.ba.size; + if (*pRetSize >= elementSize) + { + portMemCopy(pRetBuf, elementSize, &pNbsiElement->data.ba.data[0], elementSize); + *pErrorCode = NV2080_CTRL_BIOS_GET_NBSI_SUCCESS; + + // + // Null term strings but keep length same + // Note: RM calls expect null termination (at least on + // strings). Calls from NvAPI via rm control + // apparently don't use the NULL. + // So NULL terminate if they have room to be + // fully compatible + // + if (*pRetSize >= elementSize+sizeof(nullTerm)) + { + pRetBufEnd = pRetBuf + elementSize; + portMemCopy(pRetBufEnd, nullTerm, &nullTerm, nullTerm); + } + } + else + { + *pRetSize = elementSize + sizeof(nullTerm); + *pErrorCode = NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE; + return NV_OK; + } + break; + case NBSI_BYTE_ARRAY_EXTENDED: + elementSize = pNbsiElement->data.bax.size; + if (*pRetSize >= elementSize) + { + portMemCopy(pRetBuf, elementSize, &pNbsiElement->data.bax.data[0], elementSize); + *pErrorCode = NV2080_CTRL_BIOS_GET_NBSI_SUCCESS; + // + // Null term strings but keep length same + // Note: RM calls expect null termination (at least on + // strings). Calls from NvAPI via rm control + // apparently don't use the NULL. + // So NULL terminate if they have room to be + // fully compatible + // + if (*pRetSize > elementSize+sizeof(nullTerm)) + { + pRetBufEnd = pRetBuf + elementSize; + portMemCopy(pRetBufEnd, nullTerm, &nullTerm, nullTerm); + } + } + else + { + *pRetSize = elementSize + sizeof(nullTerm); + *pErrorCode = NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE; + return NV_OK; + } + break; + case NBSI_BYTE: + elementSize = 4; + if (*pRetSize >= elementSize) + { + // assign byte to dword for proper fill of upper 3 bytes + rtnData = pNbsiElement->data.dataByte; + portMemCopy(pRetBuf, elementSize, &rtnData, elementSize); + *pErrorCode = NV2080_CTRL_BIOS_GET_NBSI_SUCCESS; + } + break; + case NBSI_WORD: + elementSize = 4; + if (*pRetSize >= elementSize) + { + // assign word to dword for proper fill of upper word + rtnData = pNbsiElement->data.dataWord; + portMemCopy(pRetBuf, elementSize, &rtnData, elementSize); + *pErrorCode = NV2080_CTRL_BIOS_GET_NBSI_SUCCESS; + } + break; + case NBSI_DWORD: + elementSize = 4; + if (*pRetSize >= elementSize) + { + portMemCopy(pRetBuf, elementSize, &pNbsiElement->data.dataDWord, elementSize); + *pErrorCode = NV2080_CTRL_BIOS_GET_NBSI_SUCCESS; + } + break; + case NBSI_QWORD: + elementSize = 8; + if (*pRetSize >= elementSize) + { + portMemCopy(pRetBuf, elementSize, &pNbsiElement->data.dataQWord, elementSize); + *pErrorCode = NV2080_CTRL_BIOS_GET_NBSI_SUCCESS; + } + break; + default: + *pErrorCode = NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND; + NV_PRINTF(LEVEL_ERROR, + "Invalid NBSI table entry (2)\n"); + NV_PRINTF(LEVEL_ERROR, + "Mod/Path/Elem=%x/%x/%x, ndx=%d, type = %d.\n", + moduleID, thisPathHash, thisElementHash, + n, pNbsiElement->hdrPartA.type); + DBG_BREAKPOINT(); + return NV_ERR_GENERIC; + } + // + // on success or failure, return the correct size so caller can + // know how big it is (or needed to be). + // + *pRetSize = elementSize; + return NV_OK; +} + +//---------------------------------------------------------------------------- +// NV_STATUS getNbsiValue(pGpu, moduleID, PathHash, elementHash, +// pElementHashArray, pRetBuf, +// pRetSize, pErrorCode); +// +// This function searches the nbsi registry table for an matching element. +// +// Input parameters: +// pGpu - Gpu pointer +// moduleID - module ID for module match +// PathHash - 16 bit hash for path match +// pElementHashArray - array of 20 bit hashes for search, ndx 0 is count +// pRetBuf - pointer to return buffer +// pRetSize - pointer to size of return buffer storage. +// +// Returns NV_STATUS of NV_OK, NV_ERR_NOT_SUPPORTED, or NV_ERR_GENERIC. +// NV_OK: The table is present and no table integrity issues found +// NV_ERR_NOT_SUPPORTED: The table is not present +// NV_ERR_GENERIC: A table integrity issue was found. +// +// Output parameters: +// pRetSize - If the element is found in the table pRetSize contains +// the size of the element (4 for byte/word/dword) or +// the array size. If the element size is larger than +// the pRetBuf size, the element is not copied but the size +// is updated. +// pErrorCode - status of search (when status = NV_OK) +// NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND: element not present in table +// NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE: element larger than pRetSize +// NV2080_CTRL_BIOS_GET_NBSI_SUCCESS: element was found and placed +// at pRetBuf, pRetSize updated to size of element. +// Note: byte, word and dword entries in the table are all +// converted to a dword. +// +//---------------------------------------------------------------------------- + +NV_STATUS getNbsiValue +( + OBJGPU *pGpu, + NvU32 moduleID, + NvU16 pathHash, + NvU8 numElementHashes, + NvU32 * pElementHash, + NvU8 * pRetBuf, + NvU32 * pRetSize, + NvU32 * pErrorCode +) +{ + NBSI_OBJ *pNbsiObj = getNbsiObject(); + NBSI_DRIVER_OBJ *pNbsiDriverObj; + NBSI_MODULE *pNbsiModule; + NBSI_SCOPES *pNbsiScopes = NULL; + NBSI_ELEMENTS *pNbsiElements = NULL; + NBSI_ELEMENT *pNbsiElement; + NBSI_ELEMENT *pNbsiElementFound[MAX_NBSI_OS]; + NV_STATUS status = NV_OK; + NvU16 n; + NvBool bFound; + NvU32 elementSize; + NvU32 idx; + NvU8 i; + NvU8 j; + NvU32 valueID; + NvU8 * tPtr; + + NV_ASSERT(pErrorCode); + NV_ASSERT(pRetSize); + NV_ASSERT(!(*pRetSize != 0 && pRetBuf == NULL)); + + *pErrorCode = NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND; + + if (pGpu == NULL) + { + return NV_ERR_GENERIC; + } + + idx = gpuGetInstance(pGpu); + + if (idx >= NV_MAX_DEVICES) + { + NV_PRINTF(LEVEL_ERROR, + "Invalid gpu index %d. Aborting nbsi get value.\n", + idx); + return NV_ERR_GENERIC; + } + + if (pNbsiObj->nbsiDrvrTable[idx] == NULL) + { + return NV_ERR_NOT_SUPPORTED; + } + + pNbsiDriverObj = (PNBSI_DRIVER_OBJ) pNbsiObj->nbsiDrvrTable[idx]; + if (pNbsiDriverObj->objHdr.globType == NBSI_DRIVER) + { + // + // match the input moduleID with those in the table... if found, set + // pointers to resultant module and scopes emtries. + // + n = 0; + while ((pNbsiScopes == NULL) && (n < pNbsiDriverObj->numModules)) + { + if (pNbsiDriverObj->modules[n].moduleID == moduleID) + { + pNbsiModule = &pNbsiDriverObj->modules[n]; + + // Ignore link if the offset is special undefined offset. + if (pNbsiModule->offset != NBSI_UNDEFINED_OFFSET) + { + tPtr = (NvU8 *) &pNbsiModule->offset; + tPtr = &tPtr[pNbsiModule->offset]; + pNbsiScopes = (PNBSI_SCOPES) tPtr; + NV_ASSERT(pNbsiScopes); + } + } + n++; + } + } + if (pNbsiScopes == NULL) + { + return NV_OK; + } + + // Search through the scopes array to find a matching Scope (path) hash. + n = 0; + while ((pNbsiElements == NULL) && (n < pNbsiScopes->numPaths)) + { + if (pNbsiScopes->paths[n].pathID == pathHash) + { + tPtr = (NvU8 *) &pNbsiScopes->paths[n].offset; + tPtr = &tPtr[pNbsiScopes->paths[n].offset]; + pNbsiElements = (PNBSI_ELEMENTS) tPtr; + NV_ASSERT(pNbsiElements); + } + n++; + } + if (pNbsiElements == NULL) + { + return NV_OK; + } + + // Now find the element they want. + bFound = NV_FALSE; + n = 0; + pNbsiElement = &pNbsiElements->elements[0]; + for (i = 0; i < numElementHashes; i++) + { + pNbsiElementFound[i] = NULL; + } + + while (!bFound && (n < pNbsiElements->numElements)) + { + valueID = pNbsiElement->hdrPartA.lsnValueID | + ((pNbsiElement->hdrPartB.mswValueID) << 4); + // + // Now check for a match of the Element hashes sent to us. + // If multiple hashes are sent, index 0 holds the least specific. + // Highest index is most specific ie. 2=Vista64, 1=Vista 0=generic + // When multiple OSes drop out of loop on most specific now. + // If only one OS is specified (or we know to use the generic + // caller can reduce the count to search to 1. + // + for (i = 0; i < numElementHashes; i++) + { + if (valueID == pElementHash[i]) + { + pNbsiElementFound[i] = pNbsiElement; + if (i == numElementHashes-1) + { + // Fall out if a match on most specific hash. + bFound = NV_TRUE; + break; + } + } + } + + if (!bFound) + { + // + // current element is not the one we want so move to the next one. + // First calculate how large the current element is. + // + switch (pNbsiElement->hdrPartA.type) + { + case NBSI_BYTE: + elementSize = 1; + break; + case NBSI_WORD: + elementSize = 2; + break; + case NBSI_DWORD: + elementSize = 4; + break; + case NBSI_QWORD: + elementSize = 8; + break; + case NBSI_BYTE_ARRAY: + elementSize = pNbsiElement->data.ba.size + 1; + break; + case NBSI_BYTE_ARRAY_EXTENDED: + elementSize = pNbsiElement->data.bax.size + 2; + break; + default: + *pErrorCode = NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND; + NV_PRINTF(LEVEL_ERROR, + "Invalid NBSI table entry (1).\n"); + NV_PRINTF(LEVEL_ERROR, + "Mod/Path/El=%x/%x/%x n/hash/typ=%d/%x/%d.\n", + moduleID, pathHash, + pElementHash[0], n, valueID, + pNbsiElement->hdrPartA.type); + DBG_BREAKPOINT(); + return NV_ERR_GENERIC; + } + tPtr = (NvU8 *) pNbsiElement; + tPtr = &tPtr[elementSize + NBSI_ELEMENT_HDRSIZ]; + pNbsiElement = (PNBSI_ELEMENT) tPtr; + NV_ASSERT(pNbsiElement); + } + n++; + } + + // Check if item was found (bFound set only if first OS) + for (i = 0; i < numElementHashes; i++) + { + // Search for match from most specific up. + j = numElementHashes - i - 1; + if (pNbsiElementFound[j] != NULL) + { + status = rtnNbsiElement( + n, + moduleID, + pathHash, + pElementHash[j], + pNbsiElementFound[j], + pRetBuf, + pRetSize, + pErrorCode); + break; + } + } + + return status; +} + diff --git a/src/nvidia/src/kernel/platform/nbsi/nbsi_init.c b/src/nvidia/src/kernel/platform/nbsi/nbsi_init.c new file mode 100644 index 000000000..ab3efc67d --- /dev/null +++ b/src/nvidia/src/kernel/platform/nbsi/nbsi_init.c @@ -0,0 +1,3372 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * @file + * @brief NBSI table initialization routines. + */ + +#include "os/os.h" +#include "platform/acpi_common.h" +#include "platform/nbsi/nbsi_read.h" +#include "platform/platform.h" +#include "nbci.h" +#include "nvRmReg.h" +#include "gpu/gpu.h" +#include "nvhybridacpi.h" +#include "nvlimits.h" + +// Template to use to read in emulated nbsi table from registry. + +#define NBSI_ROM_CODE_SIZE (256*1024) // allocate amt for ROMs to be read into + +extern const GUID NV_GUID_UEFI_VARIABLE; + +//---------------------------------------------------------------------------- +// NvU32 setNbsiOSstring(* data, data_len, nbsiOSndx, maxNbsiOS) +// +// This function computes the global nbsiOShash so that future 20 bit +// fnv hash calculations can start with this hash value. +// +// Input parameters: +// *data - Byte array +// dataLen - length of Byte array +// nbsiOSndx - index to place this hash to (0 based) +// maxNbsiOS - maximum supported OS. +// +// Example usage to set up searching for Vista64 first, then Vista generic +// then blank: +// setNbsiOSstring("Vista64",7,2,3); +// setNbsiOSstring("Vista",5,1,3); +// setNbsiOSstring("",0,0,3); +// Note: The highest OS index is searched first and the lowest (0) is last. +// +// Returns the current number of OSes supported. +// +//---------------------------------------------------------------------------- +static NvU32 setNbsiOSstring +( + const void * data_v, + NvU32 dataLen, + NvU8 nbsiOSndx, + NvU8 maxNbsiOS +) +{ + NBSI_OBJ *pNbsiObj = getNbsiObject(); + NvU32 hash; + NvU8 i; + NvU8 nullPathStr[1] = {0}; + const NvU8 * data = (const NvU8 *)data_v; + + NV_ASSERT(data); + NV_ASSERT(nbsiOSndx < MAX_NBSI_OS); + NV_ASSERT(maxNbsiOS < MAX_NBSI_OS+1); + + if (maxNbsiOS <= MAX_NBSI_OS) + { + pNbsiObj->curMaxNbsiOSes = maxNbsiOS; + } + else + { + pNbsiObj->curMaxNbsiOSes = 1; + nbsiOSndx = 0; + } + + if (dataLen > MAX_NBSI_OS_STR_LEN) + { + NV_PRINTF(LEVEL_ERROR, + "NBSI OS string length %d too long for OS ndx %d.\n", + dataLen, nbsiOSndx); + dataLen = MAX_NBSI_OS_STR_LEN; + } + + // Copy the new string in. + for (i = 0; i < dataLen; i++) + { + pNbsiObj->nbsiOSstr[nbsiOSndx][i] = data[i]; + } + pNbsiObj->nbsiOSstr[nbsiOSndx][dataLen] = 0; + pNbsiObj->nbsiOSstrLen[nbsiOSndx] = dataLen; + + // + // Compute the hash for this OS string. Used in the cases where + // the elements are blank and only the OS string is needed. + // Apparently a surprisingly common event for modes. + // + hash = fnv32buf(&pNbsiObj->nbsiOSstr[nbsiOSndx][0], + pNbsiObj->nbsiOSstrLen[nbsiOSndx], + FNV1_32_INIT, + 0); + pNbsiObj->nbsiOSstrHash[nbsiOSndx] = ((hash>>20) ^ hash) & MASK_20; + + // precompute a null Path hash + pNbsiObj->nbsiBlankPathHash = fnv1Hash16(&nullPathStr[0], 0); + + return pNbsiObj->curMaxNbsiOSes; +} + +//---------------------------------------------------------------------------- +// NV_STATUS testObjectHash(pGpu, PNBSI_GEN_OBJ) +// +// This function checks the hash of an object +// +// Input parameters: +// pGpu pointer to gpu object +// PNBSI_GEN_OBJ pointer to generic object +// +// Output parameters: +// NV_STATUS: NV_OK if the hash is valid +// +//---------------------------------------------------------------------------- +static NV_STATUS testObjectHash +( + OBJGPU *pGpu, + PNBSI_GEN_OBJ pNbsiGenObj +) +{ + NV_STATUS status; + NvU64 tableHash; + NvU8 * hashStart; + NvU32 hashLen; + + NV_ASSERT(pNbsiGenObj!=NULL); + + status = NV_OK; + // validate the hash using Fnv1 CRC + hashStart = (NvU8 *) pNbsiGenObj; + hashStart = &hashStart[sizeof(pNbsiGenObj->objHdr.sig)]; + hashLen = pNbsiGenObj->objHdr.size - sizeof(pNbsiGenObj->objHdr.sig); + tableHash = fnv1Hash64(hashStart, hashLen); + if (tableHash != pNbsiGenObj->objHdr.sig) + { + status = NV_ERR_INVALID_DATA; + NV_PRINTF(LEVEL_ERROR, + "NBSI tbl computed hash %llx != hash %llx\n", + tableHash, pNbsiGenObj->objHdr.sig); + } + + return status; +} + +//---------------------------------------------------------------------------- +// NV_STATUS isGlobTypeInNbsiDir(pNbsiDir, wantedGlobType, +// *pCntOfGlobsWithThisGlobType, *pNumGlobs) +// +// This function counts the number of globs in the directory of the +// wanted type and the total number of globs. +// +// Input parameters: +// pNbsiDir pointer to nbsi directory object +// wantedGlobType wanted glob type (to count) +// +// Output parameters: +// NV_STATUS: NV_OK if the directory version is okay +// pCntOfGlobsWithThisGlobType pointer to count of wantedGlobs found +// pNumGlobs pointer to number of globs in directory +// found +// +//---------------------------------------------------------------------------- + +static NV_STATUS isGlobTypeInNbsiDir +( + PNBSI_DIRECTORY pNbsiDir, + NBSI_GLOB_TYPE wantedGlobType, + NvU8 * pCntOfGlobsWithThisGlobType, + NvU8 * pNumGlobs +) +{ + NvU8 curGlob; + NvU16 * pGlobType = NULL; + + NV_ASSERT(pNbsiDir); + NV_ASSERT(pCntOfGlobsWithThisGlobType); + NV_ASSERT(pNumGlobs); + + if (pNbsiDir->d.nbsiHeaderString == NBSIDIRHDRSTRING) + { + *pNumGlobs = pNbsiDir->d.numGlobs; + pGlobType = pNbsiDir->d.globType; + } + else + { + *pNumGlobs = pNbsiDir->od.numGlobs; + pGlobType = pNbsiDir->od.globType; + } + + if (wantedGlobType == (NBSI_GLOB_TYPE) GLOB_TYPE_GET_NBSI_DIR) + { + *pCntOfGlobsWithThisGlobType = *pNumGlobs; + } + else + { + *pCntOfGlobsWithThisGlobType = 0; + for (curGlob = 0; curGlob < *pNumGlobs; curGlob++) + { + if (wantedGlobType == pGlobType[curGlob]) + { + *pCntOfGlobsWithThisGlobType += 1; + } + } + } + return NV_OK; +} + +//---------------------------------------------------------------------------- +// NV_STATUS getNbsiDirSize( pGpu, idx, pNbsiDir, +// pRtnDirSize, tblSource); +// +// This function tests the integrity of the NBSI dir object +// +// Input parameters: +// pGpu pointer to gpu object +// idx index number of gpu +// pNbsiDir pointer to nbsi directory object +// pRtnDirSize pointer to return size of dir header +// (including globs types) +// tblSource indicator where the table came from. +// +// Output parameters: +// NV_STATUS: NV_OK if the directory version is okay and +// the directory fits in the allocated mem. +// +//---------------------------------------------------------------------------- + +static NV_STATUS getNbsiDirSize +( + OBJGPU *pGpu, + NvU32 idx, + PNBSI_DIRECTORY pNbsiDir, + NvU32 * pRtnDirSize, + NvU16 tblSource +) +{ + NvU8 nbsiDirVer; + + NV_ASSERT(pNbsiDir); + NV_ASSERT(pRtnDirSize); + + if (pNbsiDir->d.nbsiHeaderString == NBSIDIRHDRSTRING) + { + nbsiDirVer = pNbsiDir->d.dirVer; + *pRtnDirSize = + sizeof(pNbsiDir->d.nbsiHeaderString) + + sizeof(pNbsiDir->d.size) + + sizeof(pNbsiDir->d.numGlobs) + + sizeof(pNbsiDir->d.dirVer) + + (pNbsiDir->d.numGlobs * sizeof(pNbsiDir->d.globType[0])); + } + else + { + nbsiDirVer = pNbsiDir->od.dirVer; + *pRtnDirSize = + sizeof(pNbsiDir->od.numGlobs) + + sizeof(pNbsiDir->od.dirVer) + + (pNbsiDir->od.numGlobs * sizeof(pNbsiDir->od.globType[0])); + } + + if (nbsiDirVer > MAXNBSIDIRVER) + { + NV_PRINTF(LEVEL_ERROR, + "GPU%d, source %d, NBSI dir ver %d > max ver %d.\n", + idx, tblSource, nbsiDirVer, MAXNBSIDIRVER); + return NV_ERR_GENERIC; + } + + return NV_OK; +} + +//---------------------------------------------------------------------------- +// NV_STATUS testNbsiDir( pGpu, idx, pNbsiDir, allocSize, tblSource) +// +// This function tests the integrity of the NBSI dir object +// +// Input parameters: +// pGpu pointer to gpu object +// idx index number of gpu +// pNbsiDir pointer to nbsi directory object +// allocSize size of memory allocated for dir (for +// testing) +// tblSource location of table (for error messages) +// +// Output parameters: +// NV_STATUS: NV_OK if the directory version is okay and +// the directory fits in the allocated mem. +// +//---------------------------------------------------------------------------- + +static NV_STATUS testNbsiDir +( + OBJGPU *pGpu, + NvU32 idx, + PNBSI_DIRECTORY pNbsiDir, + NvU32 allocSize, + NvU16 tblSource +) +{ + NvU32 testDirSize; + NV_STATUS status; + + NV_ASSERT(pNbsiDir); + + // Get the NBSI dir size (Varies with directory header). + status = getNbsiDirSize(pGpu, + idx, + pNbsiDir, + &testDirSize, + tblSource); + if (status != NV_OK) + { + return status; + } + + if (testDirSize > allocSize) + { + NV_PRINTF(LEVEL_ERROR, + "GPU%d, source %d, Size of NBSI dir %x > alloc mem %x.\n", + idx, tblSource, testDirSize, allocSize); + return NV_ERR_GENERIC; + } + + if (pNbsiDir->d.nbsiHeaderString == NBSIDIRHDRSTRING) + { + NV_PRINTF(LEVEL_INFO, + "nbsi dir (new fmt) entries=%x, source=%x\n", + pNbsiDir->d.numGlobs, tblSource); + } + else + { + NV_PRINTF(LEVEL_INFO, + "nbsi dir (old fmt) entries=%x, source=%x\n", + pNbsiDir->od.numGlobs, tblSource); + } + + return NV_OK; +} + +// useful defines to make calls to testNbsiTable more readable. +#define TEST_NBSI_TABLE_DO_ALLOC_SIZE_CHECK NV_TRUE +#define TEST_NBSI_TABLE_SKIP_ALLOC_SIZE_CHECK NV_FALSE +#define TEST_NBSI_TABLE_DO_HASH_CHECK NV_TRUE +#define TEST_NBSI_TABLE_SKIP_HASH_CHECK NV_FALSE +#define TEST_NBSI_TABLE_DO_GLOBTYPE_CHECK NV_TRUE +#define TEST_NBSI_TABLE_SKIP_GLOBTYPE_CHECK NV_FALSE + +//---------------------------------------------------------------------------- +// NV_STATUS testNbsiTable( pGpu, pNbsiGenObj, wantedGlobType, +// i, idx, tableLoc, allocSize, +// bDoAllocSzCk, bDoHashCk, bGlobTypeCk ) +// +// This function tests an existing NBSI table. +// +// Input parameters: +// pGpu Current pGpu object +// pNbsiGenObj Current driver object to sanity check +// wantedGlobType glob type that we want +// i index within directory. +// idx GPU instance / index +// tableLoc indicator on the source of the table. +// allocSize memory allocated for table +// bDoAllocSzCk flag indicating to do allocated mem vs table test +// bDoHashCk flag indicating to do hash check test +// bGlobTypeCk flag indicating to do globtype test +// +// Output parameters: +// NV_STATUS: NV_OK if there were no operational issues +// NV_ERR_GENERIC if no table is present or table is bad. +// +//---------------------------------------------------------------------------- + +static NV_STATUS testNbsiTable +( + OBJGPU *pGpu, + PNBSI_GEN_OBJ pNbsiGenObj, + NvU16 wantedGlobType, + NvU32 i, + NvU32 idx, + NvU16 tableLoc, + NvU32 allocSize, + NvBool bDoAllocSzCk, + NvBool bDoHashCk, + NvBool bGlobTypeCk +) +{ + NV_STATUS status = NV_ERR_GENERIC; + PNBSI_DRIVER_OBJ pNbsiDriverObj = (PNBSI_DRIVER_OBJ) pNbsiGenObj; + + NV_ASSERT(pNbsiGenObj); + NV_ASSERT(allocSize); + + if (pNbsiGenObj && allocSize) + { + status = NV_OK; + + // Sanity check 1 for globSize... must be larger than NBSI_MIN_GEN_OBJ_SIZE + if (pNbsiGenObj->objHdr.size < NBSI_MIN_GEN_OBJ_SIZE) + { + NV_PRINTF(LEVEL_ERROR, + "NBSI Gpu%d Tloc=%d/Glob=%d table size 0x%x < min 0x%x\n", + idx, tableLoc, i, + pNbsiGenObj->objHdr.size, (NvU32)NBSI_MIN_GEN_OBJ_SIZE); + status = NV_ERR_GENERIC; + } + + // Sanity check 2 for globSize... must be less than maximum + if (pNbsiGenObj->objHdr.size > NBSI_MAX_TABLE_SIZE) + { + NV_PRINTF(LEVEL_ERROR, + "NBSI Gpu%d Tloc=%d/Glob=%d tbl size 0x%x > max 0x%x\n", + idx, tableLoc, i, + pNbsiGenObj->objHdr.size, NBSI_MAX_TABLE_SIZE); + status = NV_ERR_GENERIC; + } + + // Sanity check 3 for globSize... must be less than allocated size + if (bDoAllocSzCk & (pNbsiGenObj->objHdr.size > allocSize)) + { + NV_PRINTF(LEVEL_ERROR, + "NBSI Gpu%d Tloc=%d/Glob=%d table size 0x%x > alloc 0x%x\n", + idx, tableLoc, i, + pNbsiGenObj->objHdr.size, allocSize); + status = NV_ERR_GENERIC; + } + + // Sanity check for number of modules... must be less than max + if ((pNbsiGenObj->objHdr.globType == NBSI_DRIVER) && + (pNbsiDriverObj->numModules > NV2080_CTRL_BIOS_NBSI_NUM_MODULES)) + { + NV_PRINTF(LEVEL_ERROR, + "NBSI Gpu%d Tloc=%d/Glob=%d numModules %d > max %d\n", + idx, tableLoc, i, + pNbsiDriverObj->numModules, + NV2080_CTRL_BIOS_NBSI_NUM_MODULES); + status = NV_ERR_GENERIC; + } + + // Sanity check globType matches the one we wanted. + if ((pNbsiGenObj->objHdr.globType != wantedGlobType) && bGlobTypeCk) + + { + NV_PRINTF(LEVEL_ERROR, + "NBSI Gpu%d Tloc=%d/Glob=%d wantedGlobType = %04x != returned globtype = %04x\n", + idx, tableLoc, i, wantedGlobType, + pNbsiGenObj->objHdr.globType); + + // + // BUG 986051 Regression... Adding the globtype confirmation to + // prevent a BSOD, exposed an ASL problem in the C89 SBIOS, where + // the SBIOS returned the Platform Info Object with a reversed + // globtype (PI vs IP). Since we won't likely get a fixed SBIOS... + // allow this exception. + // + + if ((wantedGlobType != NBSI_PLAT_INFO) || + ((wantedGlobType == NBSI_PLAT_INFO) && (pNbsiGenObj->objHdr.globType != NBSI_PLAT_INFO_WAR))) + { + status = NV_ERR_GENERIC; + } + } + + // Now bail if we've found any errors before the hash calc. + if (status == NV_OK && bDoHashCk) + { + status = testObjectHash(pGpu, pNbsiGenObj); + if (status != NV_OK) + { + // bad hash error message occurred in testObjectHash + NV_PRINTF(LEVEL_ERROR, + "NBSI Gpu%d TLoc=%d/globType=%x bad hash\n", + idx, tableLoc, + pNbsiGenObj->objHdr.globType); + } + } + } + + return status; +} + +//---------------------------------------------------------------------------- +// NvU8 checkUidMatch(pGpu, pNbsiGenObj, idx, tableLoc, globNdx, +// pDriverVersion) +// +// This function tests if the table matches our platform/device and +// returns a score of matching. 0 matches nothing, 5 matches all. +// Search qualifiers are: +// - First UID matching the Platform SVID/SSID and Chipset VID/DID/Rev +// - First UID matching the Platform SVID and Chipset VID/DID/Rev +// - First matching Chipset VID/DID/Rev +// - First matching Chipset VID/DID +// - First matching Chipset VID +// +// Input parameters: +// pGpu Current pGpu object +// pNbsiGenObj nbsi driver object to test (NULL for dbg print) +// idx GPU instance / index +// tableLoc indicator on the source of the table. +// globNdx index of glob (note if using get object by type +// this is index of driver objects NOT all object +// types. +// pDriverVersion pointer to return version (if best fit > 0) +// +// Output parameters: +// NvU8 Score 0..5 5 is best fit, 0 is least fit +// NvU32 Driver version is returned if score > 0. +// +//---------------------------------------------------------------------------- +static NvU8 checkUidMatch +( + OBJGPU *pGpu, + PNBSI_DRIVER_OBJ pNbsiGenObj, + NvU32 idx, + NvU16 tableLoc, + NvU8 globNdx, + NvU32 * pDriverVersion +) +{ + PNBSI_DRIVER_OBJ0 pNbsiGenObj0 = (PNBSI_DRIVER_OBJ0) pNbsiGenObj; + NBSI_OBJ *pNbsiObj = getNbsiObject(); + NvU8 score = 0; + NvU16 ssid = (NvU16) (pGpu->idInfo.PCISubDeviceID >> 16) & 0xffff; + NvU16 svid = (NvU16) pGpu->idInfo.PCISubDeviceID & 0xffff; + NvU16 cdid = (NvU16) (pGpu->idInfo.PCIDeviceID >> 16) & 0xffff; + NvU16 cvid = (NvU16) pGpu->idInfo.PCIDeviceID & 0xffff; + NvU8 crev = (NvU8) pGpu->idInfo.PCIRevisionID & 0xff; + NvU32 tRev = pNbsiObj->DriverVer.Rev; + NvU32 tDX = pNbsiObj->DriverVer.DX; + NvU32 tOS = pNbsiObj->DriverVer.OS; + NvBool pTestVersionOnVer0100 = NV_FALSE; + + if (pDriverVersion != NULL) + { + *pDriverVersion = 0; + } + + if (pNbsiGenObj == NULL) + { + NV_PRINTF(LEVEL_INFO, + "NBSI current driver version: %d.%d.1%d.%d\n", + pNbsiObj->DriverVer.OS, + pNbsiObj->DriverVer.DX, + pNbsiObj->DriverVer.Rev / 10000, + pNbsiObj->DriverVer.Rev % 10000); + + NV_PRINTF(LEVEL_INFO, + "NBSI Gpu%d ID info: svid=%x, ssid=%x, cvid=%x, cdid=%x, crev=%x\n", + idx, svid, ssid, cvid, cdid, crev); + } + else + { + if (pNbsiGenObj0->objHdr.majMinVer == NBSI_DRIVERVER_0100) + { + // + // check driver rev. If specified can be greater or equal to to use. + // if value was 0, assume current version. + // Driver revision example: 6.14.11.7782 + // The format is: a.bb.1c.dddd a is OS, bb is DX, Rev is cdddd + // + if (pNbsiGenObj0->uid.Driver.majVer) + { + tOS = pNbsiGenObj0->uid.Driver.majVer; + } + if (pNbsiGenObj0->uid.Driver.minVer) + { + tDX = pNbsiGenObj0->uid.Driver.minVer; + } + if (pNbsiGenObj0->uid.Driver.majRev) + { + // + // this doesn't work correctly since the size is wrong + // fixed in v 0x101 of header + // + tRev = (pNbsiGenObj0->uid.Driver.majRev * 100) + + pNbsiGenObj0->uid.Driver.minRev; + } + if ((pTestVersionOnVer0100) && + ((tOS != pNbsiObj->DriverVer.OS) || + (tDX != pNbsiObj->DriverVer.DX) || + (tRev < pNbsiObj->DriverVer.Rev))) + { + score = 0; + tRev = 0; + } + else + { + if ((pNbsiGenObj0->uid.svid && + (pNbsiGenObj0->uid.svid == svid)) && + (pNbsiGenObj0->uid.ssid && + (pNbsiGenObj0->uid.ssid == ssid)) && + (pNbsiGenObj0->uid.Chip.vid && + (pNbsiGenObj0->uid.Chip.vid == cvid)) && + (pNbsiGenObj0->uid.Chip.did && + (pNbsiGenObj0->uid.Chip.did == cdid)) && + (pNbsiGenObj0->uid.Chip.revId && + (pNbsiGenObj0->uid.Chip.revId == crev))) + { + score = 5; + } + else if ((pNbsiGenObj0->uid.svid == svid) && + (pNbsiGenObj0->uid.Chip.vid == cvid) && + (pNbsiGenObj0->uid.Chip.did == cdid) && + (pNbsiGenObj0->uid.Chip.revId == crev)) + { + score = 4; + } + else if ((pNbsiGenObj0->uid.Chip.vid == cvid) && + (pNbsiGenObj0->uid.Chip.did == cdid) && + (pNbsiGenObj0->uid.Chip.revId == crev)) + { + score = 3; + } + else if ((pNbsiGenObj0->uid.Chip.vid == cvid) && + (pNbsiGenObj0->uid.Chip.did == cdid)) + { + score = 2; + } + else if (pNbsiGenObj0->uid.Chip.vid == cvid) + { + score = 1; + } + } + } + else + { + // + // check driver rev. If specified can be greater or equal to to use. + // if value was 0, assume current version. + // Driver revision example: 6.14.11.7782 + // The format is: a.bb.1c.dddd a is OS, bb is DX, Rev is cdddd + // + if (pNbsiGenObj->uid.Driver.OS) + { + tOS = pNbsiGenObj->uid.Driver.OS; + } + if (pNbsiGenObj->uid.Driver.DX) + { + tDX = pNbsiGenObj->uid.Driver.DX; + } + if (pNbsiGenObj->uid.Driver.Rev) + { + tRev = pNbsiGenObj->uid.Driver.Rev; + } + if ((tOS != pNbsiObj->DriverVer.OS) || + (tDX != pNbsiObj->DriverVer.DX) || + (tRev < pNbsiObj->DriverVer.Rev)) + { + score = 0; + tRev = 0; + } + else + { + if (pDriverVersion != NULL) + { + *pDriverVersion = tRev; + } + + if ((pNbsiGenObj->uid.svid && + (pNbsiGenObj->uid.svid == svid)) && + (pNbsiGenObj->uid.ssid && + (pNbsiGenObj->uid.ssid == ssid)) && + (pNbsiGenObj->uid.Chip.vid && + (pNbsiGenObj->uid.Chip.vid == cvid)) && + (pNbsiGenObj->uid.Chip.did && + (pNbsiGenObj->uid.Chip.did == cdid)) && + (pNbsiGenObj->uid.Chip.revId && + (pNbsiGenObj->uid.Chip.revId == crev))) + { + score = 5; + } + else if ((pNbsiGenObj->uid.svid == svid) && + (pNbsiGenObj->uid.Chip.vid == cvid) && + (pNbsiGenObj->uid.Chip.did == cdid) && + (pNbsiGenObj->uid.Chip.revId == crev)) + { + score = 4; + } + else if ((pNbsiGenObj->uid.Chip.vid == cvid) && + (pNbsiGenObj->uid.Chip.did == cdid) && + (pNbsiGenObj->uid.Chip.revId == crev)) + { + score = 3; + } + else if ((pNbsiGenObj->uid.Chip.vid == cvid) && + (pNbsiGenObj->uid.Chip.did == cdid)) + { + score = 2; + } + else if (pNbsiGenObj->uid.Chip.vid == cvid) + { + score = 1; + } + } + } + + NV_PRINTF(LEVEL_ERROR, + "NBSI Gpu%d Tloc=%d/Glob=%d object match score/ver = (%x/%d)\n", + idx, tableLoc, globNdx, score, tRev); + } + + return score; +} + +//---------------------------------------------------------------------------- +// NV_STATUS extractNBSIObjFromDir(pGpu, idx, +// pNbsiDir, nbsiDirSize, tableLoc, +// wantedGlobType, wantedGlobIndex, +// * pActualGlobIdx, +// * pRtnObj, * pRtnObjSize, * pbFound) +// +// This function extracts an NBSI object from a memory based (as opposed +// to ACPI) NBSI directory. +// +// Input parameters: +// pGpu Current pGpu object +// idx GPU instance / index +// pNbsiDir pointer to nbsi directory +// nbsiDirSize size of nbsiDir +// tableLoc See NBSI_TABLE_LOC_xxxx defines (for debug) +// wantedGlobType wanted Glob Type +// wantedGlobIndex index of glob type desired (0=best fit) +// pActualGlobIdx pointer to actual glob index glob found at +// +// Output parameters: +// NV_STATUS NV_ERR_GENERIC if table structure is bad. +// NV_OK if table structure is good. +// pRtnObj pointer to memory to hold return object +// pRtnObjSize size of memory holding return object +// pbFound pointer to NvBool indicating object found. +// +//---------------------------------------------------------------------------- + +static NV_STATUS extractNBSIObjFromDir +( + OBJGPU *pGpu, + NvU32 idx, + PNBSI_DIRECTORY pNbsiDir, + NvU32 nbsiDirSize, + NvU16 tableLoc, + NBSI_GLOB_TYPE wantedGlobType, + NvU8 wantedGlobIdx, + NvU8 * pActualGlobIdx, + PNBSI_GEN_OBJ * pRtnObj, + NvU32 * pRtnObjSize, + NBSI_VALIDATE validationOption, + NvBool * pbFound +) +{ + NV_STATUS status; + PNBSI_GEN_OBJ pNbsiGenObj; + NvU8 numGlobs; + NvU8 curGlob; + NvU8 cntOfGlobsWithWantedGlobType; + NvBool bMyFound; + NvU8 cntOfMatchingGlobTypes; + NvU8 thisScore; + NvU8 bestDriverObjectMatchScore = 0; + PNBSI_GEN_OBJ pBestDriverObjectMatch = NULL; + NvU8 bestDriverObjectMatchGlob = 0; + NvU8 * tPtr; + NvU32 testDirSize; + NvU32 driverVersion = 0; + NvU32 bestFitDriverVersion = 0; + NvBool bCheckCRC = NV_TRUE; + + NV_ASSERT(pNbsiDir); + NV_ASSERT(pbFound); + NV_ASSERT(pRtnObjSize); + NV_ASSERT(pRtnObj); + NV_ASSERT(pActualGlobIdx); + + *pbFound = NV_FALSE; + + // test the directory structure integrity + status = testNbsiDir(pGpu, + idx, + pNbsiDir, + nbsiDirSize, + tableLoc); + if (status != NV_OK) + { + return status; + } + + if (wantedGlobType == (NBSI_GLOB_TYPE) GLOB_TYPE_GET_NBSI_DIR) + { + // they want it all. + *pbFound = NV_TRUE; + *pRtnObj = (PNBSI_GEN_OBJ) pNbsiDir; + *pRtnObjSize = nbsiDirSize; + *pActualGlobIdx = 1; + return NV_OK; + } + + // Check if the glob type we want is in the directory + status = isGlobTypeInNbsiDir(pNbsiDir, + wantedGlobType, + &cntOfMatchingGlobTypes, + &numGlobs); + if (status != NV_OK) + { + return status; + } + + if (cntOfMatchingGlobTypes == 0) + { + return NV_OK; + } + + // Get the NBSI dir size (Varies with directory header). + status = getNbsiDirSize(pGpu, + idx, + pNbsiDir, + &testDirSize, + tableLoc); + if (status != NV_OK) + { + return status; + } + + // point at the first object in the directory to start + tPtr = (NvU8 *) pNbsiDir; + tPtr = &tPtr[testDirSize]; + pNbsiGenObj = (PNBSI_GEN_OBJ) tPtr; + + curGlob = 0; + cntOfGlobsWithWantedGlobType = 0; + bMyFound = NV_FALSE; + while ((status == NV_OK) && + !bMyFound && + (curGlob < numGlobs) && + (cntOfGlobsWithWantedGlobType < cntOfMatchingGlobTypes)) + { + + if (validationOption == NBSI_VALIDATE_IGNORE_CRC) + { + bCheckCRC = NV_FALSE; + } + + // Sanity check this object entry + status = testNbsiTable(pGpu, + (PNBSI_GEN_OBJ) pNbsiGenObj, + wantedGlobType, + curGlob, + idx, + tableLoc, + nbsiDirSize, + TEST_NBSI_TABLE_DO_ALLOC_SIZE_CHECK, + bCheckCRC, + TEST_NBSI_TABLE_SKIP_GLOBTYPE_CHECK); + + if (status != NV_OK) + { + // Bad table format. Get out now. + return status; + } + + if (pNbsiGenObj->objHdr.globType == wantedGlobType) + { + cntOfGlobsWithWantedGlobType++; + if (!wantedGlobIdx || + (cntOfGlobsWithWantedGlobType == wantedGlobIdx)) + { + // if wantedGlobIdx == 0 and driver object do best match + if (!wantedGlobIdx && (pNbsiGenObj->objHdr.globType == NBSI_DRIVER)) + { + // Check the match score for this table + thisScore = checkUidMatch(pGpu, + (PNBSI_DRIVER_OBJ) pNbsiGenObj, + idx, + tableLoc, + curGlob, + &driverVersion); + + // Keep track of the best match + if ((thisScore > 0) && + ((thisScore > bestDriverObjectMatchScore) || + ((thisScore == bestDriverObjectMatchScore) && + (driverVersion > bestFitDriverVersion)))) + { + pBestDriverObjectMatch = pNbsiGenObj; + bestDriverObjectMatchGlob = curGlob; + bestDriverObjectMatchScore = thisScore; + bestFitDriverVersion = driverVersion; + } + } + else + { + bMyFound = NV_TRUE; + } + } + } + + // if not found yet move to the next object + if (!bMyFound) + { + tPtr = (NvU8 *) pNbsiGenObj; + tPtr = &tPtr[pNbsiGenObj->objHdr.size]; + pNbsiGenObj = (PNBSI_GEN_OBJ) tPtr; + curGlob++; + } + } + + if ((status == NV_OK) && + (pBestDriverObjectMatch != NULL) && + (wantedGlobType == NBSI_DRIVER) && + !wantedGlobIdx) + { + // replace last checked with best fit driver glob + pNbsiGenObj = pBestDriverObjectMatch; + curGlob = bestDriverObjectMatchGlob; + bMyFound = NV_TRUE; + NV_PRINTF(LEVEL_ERROR, + "NBSI Gpu%d Tloc=%d/Glob=%d best fit (score/ver = (%x/%d))\n", + idx, tableLoc, bestDriverObjectMatchGlob, + bestDriverObjectMatchScore, bestFitDriverVersion); + } + + if ((status == NV_OK) && bMyFound) + { + *pbFound = bMyFound; + *pRtnObj = pNbsiGenObj; + *pRtnObjSize = pNbsiGenObj->objHdr.size; + *pActualGlobIdx = curGlob; + } + + return status; +} + +//---------------------------------------------------------------------------- +// NV_STATUS allocNbsiCache(pGpu, idx, cacheEntries) +// +// This function allocates a cache table (array) to hold the nbsi object cache +// +// Input parameters: +// pGpu Current pGpu object +// idx GPU instance / index +// cacheEntries Number of entries to allow +// +// Output parameters: +// NV_STATUS NV_ERR_GENERIC if unable to allocate memory +// NV_OK if memory is allocated for cache table. +// +//---------------------------------------------------------------------------- + +#define NBSI_INITCACHEENTRYCNT 5 +static NV_STATUS allocNbsiCache +( + OBJGPU *pGpu, + NvU32 idx, + NvU8 cacheEntries +) +{ + NvU32 cacheSize; + NBSI_CACHE_OBJ cacheObj; + PNBSI_CACHE_OBJ pCacheObj; + PNBSI_CACHE_ENTRY_OBJ pCacheEntryObj; + NBSI_OBJ *pNbsiObj = getNbsiObject(); + NvU8 i; + + NV_ASSERT(pNbsiObj->pTblCache[idx] == NULL); + + cacheSize = sizeof(cacheObj) + + (sizeof(pCacheEntryObj) * (cacheEntries - 1)); + pNbsiObj->pTblCache[idx] = portMemAllocNonPaged(cacheSize); + if (pNbsiObj->pTblCache[idx] == NULL) + { + NV_PRINTF(LEVEL_ERROR, + "Unable to allocate 0x%x memory for NBSI cache.\n", + cacheSize); + return NV_ERR_NO_MEMORY; + } + pCacheObj = pNbsiObj->pTblCache[idx]; + pCacheObj->tblCacheNumEntries = 0; + pCacheObj->tblCacheMaxNumEntries = cacheEntries; + for (i = 0; i < cacheEntries; i++) + { + pCacheObj->pCacheEntry[i] = NULL; + } + return NV_OK; +} + +//---------------------------------------------------------------------------- +// NV_STATUS addNbsiCacheEntry(pGpu, idx, pTestObj, testObjSize, +// testObjIndex, actualGlobIdx, +// wantedGlobSource, globSource) +// +// This function allocates memory to hold a cached copy of an nbsi object. +// +// Input parameters: +// pGpu Current pGpu object +// idx GPU instance / index +// pTestObj pointer to object to add to the cache +// testObjSize size of object to add to the cache. +// testObjIndex index the object was found in table. +// actualGlobIdx actual glob idx for glob (when testObjIndex=0) +// wantedGlobSource Original desired source directory +// globSource Source of the object +// +// Output parameters: +// NV_STATUS NV_ERR_GENERIC if unable to allocate memory +// NV_OK if memory is allocated for cache table. +// +// Note: If there is not enough room in the cache, the add is skipped. +// This could be changed in the future (by allocating new larger cache +// table, copying the existing table to new larger cache table and +// increase the entry count. Then releasing the previous memory). +// +//---------------------------------------------------------------------------- + +static NV_STATUS addNbsiCacheEntry +( + OBJGPU *pGpu, + NvU32 idx, + PNBSI_GEN_OBJ pTestObj, + NvU32 testObjSize, + NBSI_SOURCE_LOC wantedGlobSource, + NvU8 wantedObjIndex, + NBSI_SOURCE_LOC actualGlobSource, + NvU8 actualGlobIdx +) +{ + NvU8 cacheNdx; + PNBSI_CACHE_OBJ pCacheObj; + NBSI_CACHE_ENTRY_OBJ cacheEntry; + NBSI_OBJ *pNbsiObj = getNbsiObject(); + NvU16 szOfCacheEntry = sizeof(cacheEntry); + + NV_ASSERT(pTestObj); + + if (pNbsiObj->pTblCache[idx] != NULL) + { + pCacheObj = pNbsiObj->pTblCache[idx]; + cacheNdx = pCacheObj->tblCacheNumEntries; + + // + // in the future we may allow growing the table dynamically + // but for now just limit it. + // + if (cacheNdx < pCacheObj->tblCacheMaxNumEntries) + { + // Allocate memory for the new cache entry + pCacheObj->pCacheEntry[cacheNdx] = portMemAllocNonPaged(szOfCacheEntry); + + if (pCacheObj->pCacheEntry[cacheNdx] == NULL) + { + NV_PRINTF(LEVEL_ERROR, + "Unable to alloc 0x%x mem for NBSI cache entry\n", + szOfCacheEntry); + return NV_ERR_NO_MEMORY; + } + + // Allocate memory for the new cache entry object + pCacheObj->pCacheEntry[cacheNdx]->pObj = portMemAllocNonPaged(testObjSize); + + if (pCacheObj->pCacheEntry[cacheNdx]->pObj == NULL) + { + NV_PRINTF(LEVEL_ERROR, + "Unable to alloc 0x%x mem for NBSI cache entry\n", + testObjSize); + return NV_ERR_NO_MEMORY; + } + portMemCopy(pCacheObj->pCacheEntry[cacheNdx]->pObj, testObjSize, pTestObj, testObjSize); + + pCacheObj->pCacheEntry[cacheNdx]->globType = pTestObj->objHdr.globType; + pCacheObj->pCacheEntry[cacheNdx]->globSource = wantedGlobSource; + pCacheObj->pCacheEntry[cacheNdx]->globIndex = wantedObjIndex; + pCacheObj->pCacheEntry[cacheNdx]->altGlobSource = + actualGlobSource; + pCacheObj->pCacheEntry[cacheNdx]->altGlobIndex = actualGlobIdx; + cacheNdx++; + pCacheObj->tblCacheNumEntries = cacheNdx; + } + } + return NV_OK; +} + +//---------------------------------------------------------------------------- +// NV_STATUS freeNbsiCache(pGpu, idx) +// +// This function frees the memory used for the cache entries and the cache +// table. +// +// Input parameters: +// pGpu Current pGpu object +// idx GPU instance / index +// +// Output parameters: +// NV_STATUS NV_OK +// +//---------------------------------------------------------------------------- + +static NV_STATUS freeNbsiCache +( + OBJGPU *pGpu, + NvU32 idx +) +{ + NBSI_OBJ *pNbsiObj = getNbsiObject(); + PNBSI_CACHE_OBJ pCacheObj; + NvU8 i; + + if (pNbsiObj->nbsiDrvrTable[idx] != NULL) + { + // + // the nbsiDrvrTable is just a copy of a pointer in the cache, so we + // just clear the pointer here, and release it with the rest of the + // cache entries + // + + pNbsiObj->nbsiDrvrTable[idx] = NULL; + } + + // free the memory for the cache entries + if (pNbsiObj->pTblCache[idx] != NULL) + { + pCacheObj = pNbsiObj->pTblCache[idx]; + for (i = 0; i < pCacheObj->tblCacheNumEntries; i++) + { + portMemFree(pCacheObj->pCacheEntry[i]->pObj); + pCacheObj->pCacheEntry[i]->pObj = NULL; + + portMemFree(pCacheObj->pCacheEntry[i]); + pCacheObj->pCacheEntry[i] = NULL; + } + + // release the memory for the cache table. + pCacheObj->tblCacheNumEntries = 0; + portMemFree(pNbsiObj->pTblCache[idx]); + pNbsiObj->pTblCache[idx] = NULL; + } + return NV_OK; +} + +//---------------------------------------------------------------------------- +// NV_STATUS getNbsiCacheInfoForGlobType(pGpu, idx, +// globType, +// *pWantedGlobSource, *pWantedGlobIndex, +// *pNbsiDir, *pNbsiDirSize, *pCurTbl) +// +// This function checks if an object with the globType is in the cache and +// if it is, returns it's info. +// +// Input parameters: +// pGpu Current pGpu object +// idx GPU instance / index +// globType wanted globtype for cache entry. +// pWantedGlobIndex wanted glob index +// pWantedGlobSource wanted glob source +// +// Output parameters: +// NV_STATUS NV_OK if object was found in the cache +// NV_ERR_GENERIC if the object was not found in the cache +// pNbsiDir pointer to object +// pNbsiDirSize size of object found +// pCurTbl index of cache object entry in table +// +//---------------------------------------------------------------------------- + +static NV_STATUS getNbsiCacheInfoForGlobType +( + OBJGPU *pGpu, + NvU32 idx, + NBSI_GLOB_TYPE globType, + NBSI_SOURCE_LOC * pWantedGlobSource, + NvU8 * pWantedGlobIndex, + PNBSI_GEN_OBJ * pNbsiDir, + NvU32 * pNbsiDirSize, + NvU8 * pCurTbl +) +{ + NBSI_OBJ *pNbsiObj = getNbsiObject(); + PNBSI_CACHE_OBJ pCacheObj; + PNBSI_GEN_OBJ pGenObj; + NvU8 curTbl; + + NV_ASSERT(pWantedGlobSource); + NV_ASSERT(pWantedGlobIndex); + NV_ASSERT(pNbsiDir); + NV_ASSERT(pNbsiDirSize); + NV_ASSERT(pCurTbl); + + if (pNbsiObj->pTblCache[idx] == NULL) + { + return NV_ERR_GENERIC; + } + pCacheObj = pNbsiObj->pTblCache[idx]; + // Check if a cache entry for this globType/wanted idx table exists + *pCurTbl = 0; + + for (curTbl = 0; curTbl < pCacheObj->tblCacheNumEntries; curTbl++) + { + if ((pCacheObj->pCacheEntry[curTbl]->globType == globType) && + ((pCacheObj->pCacheEntry[curTbl]->pObj != NULL))) + { + // + // This matches what we want if the globType is correct (dugh) and + // either we want to catch the case where they ask for best fit and + // later ask for the actual source/index we don't want to + // duplicate this entry. The cached entry saves 1) whether this was + // a best fit request in the beginning and it's index + // first check for best fit request. + if ((pCacheObj->pCacheEntry[curTbl]->globSource == + *pWantedGlobSource) && + (pCacheObj->pCacheEntry[curTbl]->globIndex == + *pWantedGlobIndex)) + { + pGenObj = (PNBSI_GEN_OBJ) pCacheObj->pCacheEntry[curTbl]->pObj; + *pNbsiDir = pGenObj; + *pNbsiDirSize = pGenObj->objHdr.size; + if (pCacheObj->pCacheEntry[curTbl]->globSource == 0) + { + *pWantedGlobSource = + pCacheObj->pCacheEntry[curTbl]->altGlobSource; + *pWantedGlobIndex = + pCacheObj->pCacheEntry[curTbl]->altGlobIndex; + } + else + { + *pWantedGlobSource = + pCacheObj->pCacheEntry[curTbl]->globSource; + *pWantedGlobIndex = + pCacheObj->pCacheEntry[curTbl]->globIndex; + } + *pCurTbl = curTbl; + return NV_OK; + } + + if ((pCacheObj->pCacheEntry[curTbl]->altGlobSource == + *pWantedGlobSource) && + (pCacheObj->pCacheEntry[curTbl]->altGlobIndex == + *pWantedGlobIndex)) + { + pGenObj = (PNBSI_GEN_OBJ) pCacheObj->pCacheEntry[curTbl]->pObj; + *pNbsiDir = pGenObj; + *pNbsiDirSize = pGenObj->objHdr.size; + *pWantedGlobSource = + pCacheObj->pCacheEntry[curTbl]->altGlobSource; + *pWantedGlobIndex = + pCacheObj->pCacheEntry[curTbl]->altGlobIndex; + *pCurTbl = curTbl; + return NV_OK; + } + } + } + return NV_ERR_GENERIC; +} + +//---------------------------------------------------------------------------- +// NV_STATUS getNbsiObjFromCache(pGpu, idx, globType, +// *pWantedGlobSource, *pWantedGlobIdx +// *pRtnObj, *pRtnObjSize, *globTypeRtnStatus +// +// This function returns an object from the cache to the callers memory (if +// it's large enough). If the object is present but the return memory is not +// large enough to hold it, it returns it's size and sets the rtn status to +// incomplete. +// +// Input parameters: +// pGpu Current pGpu object +// idx GPU instance / index +// globType wanted globtype +// pWantedGlobSource wanted glob source / returned glob source +// pWantedGlobIdx wanted glob index +// +// Output parameters: +// NV_STATUS NV_OK if object was found in the cache +// NV_ERR_GENERIC if the object was not found in the cache +// pRtnObj pointer to memory to hold object +// pRtnObjSize pointer to size of memory allocated for object +// pTotalObjSize pointer to return total object size +// globTypeRtnStatus pointer to return status for extra return info. +// NV2080_CTRL_BIOS_GET_NBSI_SUCCESS indicates +// object fit in the pRtnObjSize +// NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE indicates +// object was found in cache but is too large for +// allocated memory (as per pRtnObjSize). The +// required pRtnObjSize to hold the object is +// returned. +// +//---------------------------------------------------------------------------- + +static NV_STATUS getNbsiObjFromCache +( + OBJGPU *pGpu, + NvU32 idx, + NBSI_GLOB_TYPE globType, + NBSI_SOURCE_LOC * pWantedGlobSource, + NvU8 * pWantedGlobIdx, + NvU32 rtnObjOffset, + PNBSI_GEN_OBJ pRtnObj, + NvU32 * pRtnObjSize, + NvU32 * pTotalObjSize, + NvU32 * globTypeRtnStatus +) +{ + NvU8 curTbl; + PNBSI_GEN_OBJ pTempGlob = NULL; + NvU32 tempGlobSize; + NV_STATUS status; + NvU8 * bufPtr; + + NV_ASSERT(pWantedGlobSource); + NV_ASSERT(pWantedGlobIdx); + NV_ASSERT(pRtnObjSize); + NV_ASSERT(!(*pRtnObjSize != 0 && pRtnObj == NULL)); + NV_ASSERT(pTotalObjSize); + NV_ASSERT(globTypeRtnStatus); + + // Check if the a cache entry for this NBSI_DRIVER table exists + status = getNbsiCacheInfoForGlobType(pGpu, + idx, + globType, + pWantedGlobSource, + pWantedGlobIdx, + &pTempGlob, + &tempGlobSize, + &curTbl); + + // If we found it in cache... return it (if they have enough room) + if (status == NV_OK) + { + // return the full table size + *pTotalObjSize = tempGlobSize; + + // is rtnsize larger than remaining part of table? + if (*pRtnObjSize >= (*pTotalObjSize - rtnObjOffset)) + { + // then we can return it all this time. + *pRtnObjSize = *pTotalObjSize - rtnObjOffset; + *globTypeRtnStatus = NV2080_CTRL_BIOS_GET_NBSI_SUCCESS; + } + else + { + // return what we can and indicate incomplete. + *globTypeRtnStatus = NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE; + } + + if (*pRtnObjSize > 0) + { + bufPtr = (NvU8 *) pTempGlob; + bufPtr = &bufPtr[rtnObjOffset]; + portMemCopy(pRtnObj, *pRtnObjSize, bufPtr, *pRtnObjSize); + } + } + return status; +} + + +//---------------------------------------------------------------------------- +// NV_STATUS getNbsiDirFromRegistry(pGpu, idx, +// pNbsiDir, pNbsiDirSize) +// +// This function determines if an emulated NBSI table exists in the registry +// and reads it. +// +// Input parameters: +// pGpu Current pGpu object +// idx GPU instance / index +// +// Output parameters: +// NV_STATUS: NV_OK if there were no operational issues +// (such as memory allocation failure) +// looking for the table... or no registry +// entry exists. +// pNbsiDir pointer to directory object. +// pNbsiDirSize size of directory object found. +// +//---------------------------------------------------------------------------- + +static NV_STATUS getNbsiDirFromRegistry +( + OBJGPU *pGpu, + NvU32 idx, + PNBSI_DIRECTORY * pNbsiDir, + NvU32 * rtnNbsiDirSize +) +{ + NV_STATUS status; + NvU32 nbsiDirSize; + + NV_ASSERT_OR_RETURN( pNbsiDir, NV_ERR_INVALID_POINTER ); + NV_ASSERT_OR_RETURN( rtnNbsiDirSize, NV_ERR_INVALID_POINTER ); + + // Check if the key is in the registry... and it's size + nbsiDirSize = 0; + status = osReadRegistryStringBase(pGpu, + NV_REG_STR_EMULATED_NBSI_TABLE, + (NvU8 *) *pNbsiDir, + &nbsiDirSize); + + // size returned is non 0 so key is present. + if (nbsiDirSize) + { + // do some minimal testing of first block? + if (nbsiDirSize > NBSI_MAX_TABLE_SIZE) + { + NV_PRINTF(LEVEL_ERROR, + "Emulated NBSI table too big. 0x%x > than 0x%x!\n", + nbsiDirSize, NBSI_MAX_TABLE_SIZE); + return NV_ERR_GENERIC; + } + + // Allocate memory for the directory + *pNbsiDir = portMemAllocNonPaged(nbsiDirSize); + if (*pNbsiDir == NULL) + { + NV_PRINTF(LEVEL_ERROR, + "Can't allocate 0x%x mem for emulated NBSI table.\n", + nbsiDirSize); + return NV_ERR_NO_MEMORY; + } + + // read the table in. + status = osReadRegistryBinary(pGpu, + NV_REG_STR_EMULATED_NBSI_TABLE, + (NvU8 *) *pNbsiDir, + &nbsiDirSize); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Unable to read emulated NBSI table from reg.\n"); + portMemFree((void*)pNbsiDir); + pNbsiDir = NULL; + return status; + } + + *rtnNbsiDirSize = nbsiDirSize; + return NV_OK; + } + + return NV_ERR_GENERIC; +} + +//---------------------------------------------------------------------------- +// NV_STATUS determineACPIAccess(pGpu, idx, pRtnMethod, acpiFunction) +// +// This function checks if we have ACPI access to the NBSI table +// +// Input parameters: +// pGpu Current pGpu object +// idx GPU instance / index +// pRtnMethod status for methods available. +// acpiFunction selector for acpi function (nbsi vs hybrid) +// +// Output parameters: +// NV_STATUS: NV_OK if we have access +// !NV_OK if we do not have ACPI access +// +//---------------------------------------------------------------------------- + +static NV_STATUS determineACPIAccess +( + OBJGPU *pGpu, + NvU32 idx, + PNBSI_ACPI_METHOD pRtnMethod, + ACPI_DSM_FUNCTION acpiFunction +) +{ + NV_STATUS status = NV_ERR_NOT_SUPPORTED; + NV_STATUS statusByType = NV_ERR_NOT_SUPPORTED; + NV_STATUS statusAllObj = NV_ERR_NOT_SUPPORTED; + NvU32 getObjectByTypeSubfunction = NV_ACPI_GENERIC_FUNC_GETOBJBYTYPE; + NvU32 getAllObjectsSubfunction = NV_ACPI_GENERIC_FUNC_GETALLOBJS; + + NV_ASSERT(pRtnMethod); + *pRtnMethod = NBSI_TBL_SOURCE_ACPI_UNKNOWN; + + // Determine the subfunctions for getobjectbytype and getallobjects + status = getDsmGetObjectSubfunction(pGpu, &acpiFunction, &getObjectByTypeSubfunction, &getAllObjectsSubfunction); + if (status != NV_OK) + { + return status; + } + + status = testIfDsmSubFunctionEnabled(pGpu, acpiFunction, NV_ACPI_ALL_FUNC_SUPPORT); + if (status != NV_OK) + { + return status; + } + + statusByType = testIfDsmSubFunctionEnabled(pGpu, acpiFunction, getObjectByTypeSubfunction); + statusAllObj = testIfDsmSubFunctionEnabled(pGpu, acpiFunction, getAllObjectsSubfunction); + if ((statusByType != NV_OK) && (statusAllObj != NV_OK)) + { + // return if both subfunctions are not supported get out + return NV_ERR_NOT_SUPPORTED; + } + else + { + // one or both should work... indicate which + if ((statusByType == NV_OK) && (statusAllObj == NV_OK)) + { + *pRtnMethod = NBSI_TBL_SOURCE_ACPI_BOTH_METHODS; + } + else if (statusByType == NV_OK) + { + *pRtnMethod = NBSI_TBL_SOURCE_ACPI_BY_OBJ_TYPE; + } + else if (statusAllObj == NV_OK) + { + *pRtnMethod = NBSI_TBL_SOURCE_ACPI_BY_ALL_OBJ; + } + status = NV_OK; + } + + return status; +} + +//---------------------------------------------------------------------------- +// NV_STATUS getNbsiDirectory(pGpu, idx, +// searchDir, *pNbsiDir, *pNbsiDirSize, +// curSource, +// *pbFreeDirMemRequired, +// *pAcpiMethod, +// acpiFunction) +// +// This function gets the NBSI directory (in all but ACPI and UEFI cases) +// +// Input parameters: +// pGpu Current pGpu object +// idx GPU instance / index +// curSource source for the NBSI dir +// acpiFunction selector for acpi function (nbsi vs hybrid) +// +// Output parameters: +// NV_STATUS NV_OK +// *pNbsiDir pointer to return directory found. +// *activeDir bitmap of directory found to search. +// *pNbsiDirSize pointer to the size of the NBSI dir. +// *pbFreeDirMemRequired pointer to NvBool indicating if the directory +// being returned is in newly allocated memory (or +// just a pointer to existing memory ie VBIOS) +// *pAcpiMethod for ACPI based tables, access method(s) +// +//---------------------------------------------------------------------------- + +static NV_STATUS getNbsiDirectory +( + OBJGPU *pGpu, + NvU32 idx, + PNBSI_DIRECTORY * pNbsiDir, + NvU32 * pNbsiDirSize, + NBSI_SOURCE_LOC curSource, + NvBool * pbFreeDirMemRequired, + PNBSI_ACPI_METHOD pAcpiMethod, + ACPI_DSM_FUNCTION acpiFunction +) +{ + NV_STATUS status; + + NV_ASSERT(pNbsiDir); + NV_ASSERT(pNbsiDirSize); + NV_ASSERT(pbFreeDirMemRequired); + NV_ASSERT(pAcpiMethod); + + *pNbsiDir = NULL; + *pNbsiDirSize = 0; + *pbFreeDirMemRequired = NV_FALSE; + + status = NV_ERR_GENERIC; + if (curSource & NBSI_TBL_SOURCE_REGISTRY) + { + status = getNbsiDirFromRegistry(pGpu, + idx, + pNbsiDir, + pNbsiDirSize); + if (status == NV_OK) + { + *pbFreeDirMemRequired = NV_TRUE; + } + } + else if (curSource & NBSI_TBL_SOURCE_VBIOS) + { + return NV_ERR_NOT_SUPPORTED; + } + else if (curSource & NBSI_TBL_SOURCE_SBIOS) + { + return NV_ERR_NOT_SUPPORTED; + } + else if (curSource & NBSI_TBL_SOURCE_ACPI) + { + status = determineACPIAccess(pGpu, idx, pAcpiMethod, acpiFunction); + } + else if (curSource & NBSI_TBL_SOURCE_UEFI) + { + status = NV_OK; + } + + return status; +} + +//---------------------------------------------------------------------------- +// NV_STATUS nbsiObjTypeCallAcpi(pGpu, +// acpiFunction, +// inOutData, inOutDataSz, +// outBuffer, outBufferSz, globTypeWanted, +// curGlob, * sizeToRead) +// +// This function retrieves an ACPI based object. +// +// Input parameters: +// pGpu Current pGpu object +// acpiFunction selector for acpi function (nbsi vs hybrid) +// inOutData ACPI inout buffer +// inOutDataSz ACPI inout buffer size +// outBuffer output buffer +// outBufferSz output buffer size +// globTypeWanted desired object Type +// curGlob glob index +// *sizeToRead size to read +// +// Output parameters: +// NV_STATUS: NV_OK if there were no operational issues +// Such as bad parameters or failed read. +// rtnSize set to amount read (always set to inOutDataSz) +// +//---------------------------------------------------------------------------- +static NV_STATUS nbsiObjTypeCallAcpi +( + OBJGPU *pGpu, + ACPI_DSM_FUNCTION acpiFunction, + NvU8 * inOutData, + NvU32 inOutDataSz, + NvU8 * outBuffer, + NvU32 outBufferSz, + NBSI_GLOB_TYPE globTypeWanted, + NvU8 curGlob, + NvU32 * sizeToRead +) +{ + NV_STATUS status = NV_OK; + NvU32 leftToRead; + NvU16 rtnSize; + NvU16 acpiRtnSize = (NvU16) inOutDataSz; + + // curGlob fits in 15:12... so make sure we don't ask for anything higher (can happen if the SBIOS keeps sending us the same one). + NV_ASSERT_OR_RETURN((curGlob < 16), NV_ERR_INVALID_ARGUMENT); + + leftToRead = *sizeToRead; + *sizeToRead = 0; + while ((status == NV_OK) && (leftToRead)) + { + // 31:16 object type, 15:12 object instance, 11:0 page offset + *(NvU32 *) inOutData = (globTypeWanted & 0xffff) << 16 | + (curGlob & 0xf) << 12 | + ((*sizeToRead/inOutDataSz) & 0xfff); + status = pGpu->pOS->osCallACPI_DSM(pGpu, + acpiFunction, + NV_ACPI_GENERIC_FUNC_GETOBJBYTYPE, + (NvU32 *)inOutData, + (NvU16 *)&acpiRtnSize); + + if ((acpiRtnSize == 0) || + ((status == NV_OK) && + (acpiRtnSize==4) && + ((*(NvU32*)inOutData >= NVHG_ERROR_UNSPECIFIED) && + (*(NvU32*)inOutData <= 0x80000005) ))) + { + status = NV_ERR_GENERIC; + } + + if (status == NV_OK) + { + rtnSize = NV_MIN((NvU16) leftToRead, (NvU16) acpiRtnSize); + NV_ASSERT((*sizeToRead+rtnSize)<=outBufferSz); + portMemCopy(&outBuffer[*sizeToRead], rtnSize, inOutData, rtnSize); + leftToRead -= rtnSize; + *sizeToRead += rtnSize; + } + } + return status; +} + +//---------------------------------------------------------------------------- +// NV_STATUS nbsiObjTypeCallUefi(pGpu, +// inOutData, inOutDataSz, +// outBuffer, outBufferSz, globTypeWanted, +// curGlob, * sizeToRead) +// +// This function retrieves an UEFI based object. +// +// Input parameters: +// pGpu Current pGpu object +// inOutData inout buffer +// inOutDataSz inout buffer size +// outBuffer output buffer +// outBufferSz output buffer size +// globTypeWanted desired object Type +// curGlob glob index +// *sizeToRead size to read +// +// Output parameters: +// NV_STATUS: NV_OK if there were no operational issues +// Such as bad parameters or failed read. +// rtnSize set to amount read (always set to inOutDataSz) +// +//---------------------------------------------------------------------------- +static NV_STATUS nbsiObjTypeCallUefi +( + OBJGPU *pGpu, + NvU8 * inOutData, + NvU32 inOutDataSz, + NvU8 * outBuffer, + NvU32 outBufferSz, + NBSI_GLOB_TYPE globTypeWanted, + NvU8 curGlob, + NvU32 * sizeToRead +) +{ + NV_STATUS status = NV_OK; + NvU32 uefiRtnSize = inOutDataSz; + char uefiVariableName[] = "NBSI_GLOB_000"; + + NV_ASSERT_OR_RETURN(curGlob < 16, NV_ERR_INVALID_ARGUMENT); + + // Per Matt's recommendation, only support glob type "OP" for now. + if (globTypeWanted != NBSI_OPTIMUS_PLAT) + { + return NV_ERR_NOT_SUPPORTED; + } + + // Change 000 in variable name to glob type and instance hex digit. + uefiVariableName[10] = (globTypeWanted & 0xFF00) >> 8; + uefiVariableName[11] = globTypeWanted & 0xFF; + uefiVariableName[12] = curGlob + (curGlob < 10 ? '0' : 'A' - 10); + + status = pGpu->pOS->osGetUefiVariable(pGpu, + uefiVariableName, + (LPGUID)&NV_GUID_UEFI_VARIABLE, + inOutData, + &uefiRtnSize, + NULL); + + if (status == NV_OK) + { + portMemCopy(outBuffer, uefiRtnSize, inOutData, uefiRtnSize); + *sizeToRead = uefiRtnSize; + } + return status; +} + +//---------------------------------------------------------------------------- +// NV_STATUS getTableDataUsingObjTypeCall(pGpu, +// curDir, acpiFunction, +// inOutData, inOutDataSz, +// outBuffer, outBufferSz, globTypeWanted, +// curGlob, * sizeToRead) +// +// This function retrieves an ACPI based object. +// With RID 61791, also supports objects as UEFI runtime variables. +// +// Input parameters: +// pGpu Current pGpu object +// curDir table source (acpi vs uefi) +// acpiFunction selector for acpi function (nbsi vs hybrid) +// inOutData ACPI inout buffer +// inOutDataSz ACPI inout buffer size +// outBuffer output buffer +// outBufferSz output buffer size +// globTypeWanted desired object Type +// curGlob glob index +// *sizeToRead size to read +// +// Output parameters: +// NV_STATUS: NV_OK if there were no operational issues +// Such as bad parameters or failed read. +// rtnSize set to amount read (always set to inOutDataSz) +// +//---------------------------------------------------------------------------- +static NV_STATUS getTableDataUsingObjTypeCall +( + OBJGPU *pGpu, + NvU16 curDir, + ACPI_DSM_FUNCTION acpiFunction, + NvU8 * inOutData, + NvU32 inOutDataSz, + NvU8 * outBuffer, + NvU32 outBufferSz, + NBSI_GLOB_TYPE globTypeWanted, + NvU8 curGlob, + NvU32 * sizeToRead +) +{ + NV_STATUS status = NV_OK; + + NV_ASSERT(inOutData); + NV_ASSERT(outBuffer); + NV_ASSERT(sizeToRead); + NV_ASSERT(!(*sizeToRead > outBufferSz)); + + if (*sizeToRead > outBufferSz) + { + return NV_ERR_GENERIC; + } + + if (curDir == NBSI_TBL_SOURCE_ACPI) + { + status = nbsiObjTypeCallAcpi(pGpu, + acpiFunction, + inOutData, + inOutDataSz, + outBuffer, + outBufferSz, + globTypeWanted, + curGlob, + sizeToRead); + } + else if (curDir == NBSI_TBL_SOURCE_UEFI) + { + status = nbsiObjTypeCallUefi(pGpu, + inOutData, + inOutDataSz, + outBuffer, + outBufferSz, + globTypeWanted, + curGlob, + sizeToRead); + } + else + { + status = NV_ERR_INVALID_ARGUMENT; + } + return status; +} + +//---------------------------------------------------------------------------- +// NV_STATUS getTableUsingObjTypeCall(pGpu, idx, +// curDir, +// acpiFunction, validationOption, +// wantedGlobType, pActualGlobIdx, +// inOutData, inOutDataSz, tmpBuffer, tmpBufferSz) +// +// This function queries for the ACPI based NBSI table and checks the headers. +// With RID 67191, also supports querying via UEFI runtime variables. +// +// Input parameters: +// pGpu Current pGpu object +// idx index to current gpu +// curDir table source (acpi vs uefi) +// acpiFunction selector for acpi function (nbsi vs hybrid) +// validationOption test validation option +// wantedGlobType glob type wanted +// wantedGlobIdx glob type index wanted +// pActualGlobIdx pointer to actual index found +// inOutData acpi inout buffer for reads +// inOutDataSz size of acpi inout buffer +// tmpBuffer temporary buffer for data manipulation +// (should be equal to inOutDataSz) +// tmpBufferSz size of temporary buffer +// +// Output parameters: +// pRtnObj pointer to return object +// pRtnObjSize pointer to return object size +// pbFound pointer to NvBool indicating object was found +// status == NV_OK no issues in looking for object (although +// object may or may not be present... see +// pbFound) +// status != NV_OK if error occurred while getting the object +// +//---------------------------------------------------------------------------- + +static NV_STATUS getTableUsingObjTypeCall +( + OBJGPU *pGpu, + NvU32 idx, + NvU16 curDir, + ACPI_DSM_FUNCTION acpiFunction, + NBSI_VALIDATE validationOption, + NBSI_GLOB_TYPE wantedGlobType, + NvU8 wantedGlobIdx, + NvU8 * pActualGlobIdx, + PNBSI_GEN_OBJ * pRtnObj, + NvU32 * pRtnObjSize, + NvBool * pbFound, + NvU8 * inOutData, + NvU32 inOutDataSz, + NvU8 * tmpBuffer, + NvU32 tmpBufferSz +) +{ + NV_STATUS status = NV_OK; + PNBSI_DRIVER_OBJ pNbsiDrvrObj; + NBSI_DRIVER_OBJ nbsiDriverObj; + NvU32 drvrObjHdrSize = sizeof(nbsiDriverObj) - + sizeof(nbsiDriverObj.objData); + NvU8 curGlob; + NvU32 curGlobSize; + NvU32 rtnSize; + NvU8 thisScore; + NvBool bMyFound; + NvU8 bestDriverObjectMatchScore = 0; + NvU8 bestDriverObjectMatchGlob = 0; + NvU32 bestDriverObjectMatchSize = 0; + NvU32 driverVersion = 0; + NvU32 bestFitDriverVersion = 0; + NvBool bCheckCRC = NV_TRUE; + + NV_ASSERT(pRtnObj); + NV_ASSERT(pRtnObjSize); + NV_ASSERT(pbFound); + NV_ASSERT(pActualGlobIdx); + NV_ASSERT(inOutData); + NV_ASSERT(tmpBuffer); + + *pbFound = NV_FALSE; + + if (wantedGlobType == (NBSI_GLOB_TYPE) GLOB_TYPE_GET_NBSI_DIR) + { + // shouldn't get here... we can't handle this with get obj type call + return NV_ERR_GENERIC; + } + + if (wantedGlobIdx) + { + curGlob = wantedGlobIdx; + } + else + { + curGlob = 0; + } + + bMyFound = NV_FALSE; + curGlobSize = 0; + while ((status == NV_OK) && !bMyFound) + { + // try to read curGlobHeader for this type + rtnSize = drvrObjHdrSize; + status = getTableDataUsingObjTypeCall(pGpu, + curDir, + acpiFunction, + inOutData, + inOutDataSz, + tmpBuffer, + tmpBufferSz, + wantedGlobType, + curGlob, + &rtnSize); + + if (status != NV_OK) + { + // error returned on get, must be no more globs + break; + } + + // Confirm this glob header looks okay. + pNbsiDrvrObj = (PNBSI_DRIVER_OBJ) tmpBuffer; + status = testNbsiTable(pGpu, + (PNBSI_GEN_OBJ) pNbsiDrvrObj, + wantedGlobType, + curGlob, + idx, + NBSI_TBL_SOURCE_ACPI_BY_OBJ_TYPE, + tmpBufferSz, + TEST_NBSI_TABLE_SKIP_ALLOC_SIZE_CHECK, + TEST_NBSI_TABLE_SKIP_HASH_CHECK, + TEST_NBSI_TABLE_DO_GLOBTYPE_CHECK); + if (status != NV_OK) + { + // bad table format + // pNbsiObj->nbsiTableState[idx][objt] = NBSI_TABLE_BAD; + return status; + } + + // if they wanted a specific glob index we're done + if (wantedGlobIdx || (wantedGlobType != NBSI_DRIVER)) + { + // we've got the header for the glob we want + curGlobSize = pNbsiDrvrObj->objHdr.size; + bMyFound = NV_TRUE; + } + else + { + // we need to find the best fit NBSI_DRIVER + // Check the match score for this table + thisScore = checkUidMatch(pGpu, + (PNBSI_DRIVER_OBJ) pNbsiDrvrObj, + idx, + NBSI_TBL_SOURCE_ACPI_BY_OBJ_TYPE, + curGlob, + &driverVersion); + + // Keep track of the best match + if ((thisScore > 0) && + ((thisScore > bestDriverObjectMatchScore) || + ((thisScore == bestDriverObjectMatchScore) && + (driverVersion > bestFitDriverVersion)))) + { + bestDriverObjectMatchGlob = curGlob; + bestDriverObjectMatchScore = thisScore; + bestDriverObjectMatchSize = pNbsiDrvrObj->objHdr.size; + bestFitDriverVersion = driverVersion; + } + } + if (!bMyFound) + { + curGlob++; + } + } + + if (bestDriverObjectMatchSize && + (wantedGlobType == NBSI_DRIVER) && + !wantedGlobIdx) + { + // replace last checked with best fit driver glob + curGlob = bestDriverObjectMatchGlob; + curGlobSize = bestDriverObjectMatchSize; + bMyFound = NV_TRUE; + NV_PRINTF(LEVEL_ERROR, + "NBSI Gpu%d Tloc=%d/Glob=%d best fit (score/ver = (%x/%d))\n", + idx, NBSI_TBL_SOURCE_ACPI_BY_OBJ_TYPE, + bestDriverObjectMatchGlob, bestDriverObjectMatchScore, + bestFitDriverVersion); + } + + if (bMyFound) + { + // we know which glob number we want to get the entire glob for + // allocate memory to return the entire glob in + pNbsiDrvrObj = portMemAllocNonPaged(curGlobSize); + if (pNbsiDrvrObj == NULL) + { + NV_PRINTF(LEVEL_ERROR, + "Can't alloc 0x%x bytes for ACPI NBSI table.\n", + curGlobSize); + return NV_ERR_GENERIC; + } + + // read all of the current glob in + rtnSize = curGlobSize; + status = getTableDataUsingObjTypeCall(pGpu, + curDir, + acpiFunction, + inOutData, + inOutDataSz, + (NvU8 *) pNbsiDrvrObj, + curGlobSize, + wantedGlobType, + curGlob, + &rtnSize); + + if (status != NV_OK) + { + // this shouldn't happen since we did this once before + portMemFree(pNbsiDrvrObj); + pNbsiDrvrObj = NULL; + return status; + } + + if (validationOption == NBSI_VALIDATE_IGNORE_CRC) + { + bCheckCRC = NV_FALSE; + } + + // Confirm this glob header looks okay. + status = testNbsiTable(pGpu, + (PNBSI_GEN_OBJ) pNbsiDrvrObj, + wantedGlobType, + curGlob, + idx, + NBSI_TBL_SOURCE_ACPI_BY_OBJ_TYPE, + curGlobSize, + TEST_NBSI_TABLE_DO_ALLOC_SIZE_CHECK, + bCheckCRC, + TEST_NBSI_TABLE_DO_GLOBTYPE_CHECK); + if (status != NV_OK) + { + // bad table format (most likely hash test failure) + portMemFree(pNbsiDrvrObj); + pNbsiDrvrObj = NULL; + return status; + } + + *pRtnObj = (PNBSI_GEN_OBJ) pNbsiDrvrObj; + *pRtnObjSize = pNbsiDrvrObj->objHdr.size; + *pActualGlobIdx = curGlob; + *pbFound = NV_TRUE; + } + return status; +} + +//---------------------------------------------------------------------------- +// NV_STATUS getTableDataUsingAllObjectCall(pGpu, acpiFunction, +// inOutData, inOutDataSz, +// outBuffer, outBufferSz, +// curOffset, *sizeToRead) +// +// This function queries for the ACPI based NBSI table. +// +// Input parameters: +// pGpu Current pGpu object +// acpiFunction selector for acpi function (nbsi vs hybrid) +// inOutData ACPI inout buffer +// inOutDataSz ACPI inout buffer size +// outBuffer output buffer +// outBufferSz output buffer size +// *curOffset offset to read from +// *sizeToRead size to read +// +// Output parameters: +// NV_STATUS: NV_OK if there were no operational issues +// Such as bad parameters or failed read. +// curOffset set to original offset plus rtnsize +// rtnSize set to amount read. +// +//---------------------------------------------------------------------------- + +static NV_STATUS getTableDataUsingAllObjectCall +( + OBJGPU *pGpu, + ACPI_DSM_FUNCTION acpiFunction, + NvU8 * inOutData, + NvU32 inOutDataSz, + NvU8 * outBuffer, + NvU32 outBufferSz, + NvU32 curOffset, + NvU32 * sizeToRead +) +{ + NV_STATUS status = NV_OK; + NvU32 leftToRead; + NvU32 bufferOffset; + NvU32 rtnSize = 0; + NvU16 acpiRtnSize = (NvU16) inOutDataSz; + + NV_ASSERT(inOutData); + NV_ASSERT(outBuffer); + NV_ASSERT(sizeToRead); + NV_ASSERT(!(*sizeToRead > outBufferSz)); + + if (*sizeToRead > outBufferSz) + { + return NV_ERR_GENERIC; + } + + leftToRead = *sizeToRead; + *sizeToRead = 0; + while ((status == NV_OK) && (leftToRead)) + { + // get page the data is in. + *(NvU32 *) inOutData = curOffset / inOutDataSz; + status = pGpu->pOS->osCallACPI_DSM(pGpu, + acpiFunction, + NV_ACPI_GENERIC_FUNC_GETALLOBJS, + (NvU32 *)inOutData, + (NvU16 *)&rtnSize); + if ((acpiRtnSize == 0) || + ((status == NV_OK) && + (acpiRtnSize==4) && + ((*(NvU32*)inOutData >= NVHG_ERROR_UNSPECIFIED) && + (*(NvU32*)inOutData <= 0x80000005) ))) + { + status = NV_ERR_GENERIC; + } + + if (status == NV_OK) + { + bufferOffset = curOffset % inOutDataSz; + if ((bufferOffset + leftToRead) > acpiRtnSize) + { + rtnSize = acpiRtnSize - bufferOffset; + } + else + { + rtnSize = leftToRead; + } + NV_ASSERT((*sizeToRead+rtnSize)<=outBufferSz); + portMemCopy(&outBuffer[*sizeToRead], rtnSize, &inOutData[curOffset % inOutDataSz], rtnSize); + leftToRead -= rtnSize; + *sizeToRead += rtnSize; + curOffset += rtnSize; + } + } + return status; +} + +//---------------------------------------------------------------------------- +// NV_STATUS getTableUsingAllObjectCall(pGpu, idx, +// acpiFunction, validationOption, +// wantedGlobType, wantedGlobIdx, +// *pActualGlobIdx, +// *pRtnObj, *pRtnObjSize, *pbFound, +// inOutData, inOutDataSz, tmpBuffer, +// tmpBufferSz) +// +// This function queries for the ACPI based NBSI table. +// +// Input parameters: +// pGpu Current pGpu object +// idx index to current gpu +// acpiFunction selector for acpi function (nbsi vs hybrid) +// validationOption test validation option +// wantedGlobType desired glob type +// wantedGlobIdx desired glob index +// pActualGlobIdx pointer to actual index wanted object is at +// inOutData acpi inout buffer for reads +// inOutDataSz size of acpi inout buffer +// tmpBuffer temporary buffer for data manipulation +// (should be equal to inOutDataSz) +// tmpBufferSz size of temporary buffer +// +// Output parameters: +// pRtnObj pointer to return object +// pRtnObjSize pointer to return object size +// pbFound pointer to NvBool indicating object was found +// status == NV_OK no issues in looking for object (although +// object may or may not be present... see +// pbFound) +// status != NV_OK if error occurred while getting the object +// +//---------------------------------------------------------------------------- + +static NV_STATUS getTableUsingAllObjectCall +( + OBJGPU *pGpu, + NvU32 idx, + ACPI_DSM_FUNCTION acpiFunction, + NBSI_VALIDATE validationOption, + NBSI_GLOB_TYPE wantedGlobType, + NvU8 wantedGlobIdx, + NvU8 * pActualGlobIdx, + PNBSI_GEN_OBJ * pRtnObj, + NvU32 * pRtnObjSize, + NvBool * pbFound, + NvU8 * inOutData, + NvU32 inOutDataSz, + NvU8 * tmpBuffer, + NvU32 tmpBufferSz +) +{ + NV_STATUS status = NV_OK; + PNBSI_DIRECTORY pNbsiDir; + NvU32 nbsiDirSize; + PNBSI_DRIVER_OBJ pNbsiDrvrObj; + NBSI_DRIVER_OBJ nbsiDrvrObj; + NvU8 numGlobs; + NvU8 curGlob; + NvU32 curGlobSize; + NvU8 cntOfGlobsWithWantedGlobType; + NvU8 cntOfMatchingGlobTypes; + NvU32 rtnSize; + NvU8 thisScore; + NvBool bMyFound; + NvU8 bestDriverObjectMatchScore = 0; + NvU32 bestDriverObjectMatchOffset = 0; + NvU32 bestDriverObjectMatchSize = 0; + NvU8 bestDriverObjectIndex = 0; + NvU32 curOffset; + NvU32 dirContentsSize = 0; + NvU32 driverVersion = 0; + NvU32 bestFitDriverVersion = 0; + NvBool bCheckCRC = NV_TRUE; + + NV_ASSERT(pRtnObj); + NV_ASSERT(pRtnObjSize); + NV_ASSERT(pActualGlobIdx); + NV_ASSERT(pbFound); + NV_ASSERT(inOutData); + NV_ASSERT(tmpBuffer); + + *pbFound = NV_FALSE; + + // read in the directory (assume new format and one globtype entry) + nbsiDirSize = sizeof(pNbsiDir->d); + rtnSize = nbsiDirSize; + curOffset = 0; + status = getTableDataUsingAllObjectCall(pGpu, + acpiFunction, + inOutData, + inOutDataSz, + tmpBuffer, + tmpBufferSz, + curOffset, + &rtnSize); + if (status != NV_OK) + { + // error returned on get, must be no more globs + return status; + } + + // determine the size of the directory + pNbsiDir = (PNBSI_DIRECTORY) tmpBuffer; + status = getNbsiDirSize(pGpu, + idx, + pNbsiDir, + &nbsiDirSize, + NBSI_TBL_SOURCE_ACPI_BY_ALL_OBJ); + if (status != NV_OK) + { + // error returned on get, must be no more globs + return status; + } + + // read all of the directory this time + curOffset = 0; + rtnSize = nbsiDirSize; + status = getTableDataUsingAllObjectCall(pGpu, + acpiFunction, + inOutData, + inOutDataSz, + tmpBuffer, + tmpBufferSz, + curOffset, + &rtnSize); + if (status != NV_OK) + { + // error returned on get, must be no more globs + return status; + } + + status = testNbsiDir(pGpu, + idx, + pNbsiDir, + nbsiDirSize, + NBSI_TBL_SOURCE_ACPI_BY_ALL_OBJ); + if (status != NV_OK) + { + return status; + } + + status = isGlobTypeInNbsiDir(pNbsiDir, + wantedGlobType, + &cntOfMatchingGlobTypes, + &numGlobs); + if (status != NV_OK) + { + return status; + } + + if (cntOfMatchingGlobTypes == 0) + { + return NV_OK; + } + + // point at the first object in the directory + curOffset += nbsiDirSize; + + curGlob = 0; + cntOfGlobsWithWantedGlobType = 0; + curGlobSize = 0; + bMyFound = NV_FALSE; + while ((status == NV_OK) && + !bMyFound && + (curGlob < numGlobs) && + (cntOfGlobsWithWantedGlobType < cntOfMatchingGlobTypes)) + { + // read the generic object so we can test. + rtnSize = sizeof(nbsiDrvrObj) - sizeof(nbsiDrvrObj.objData); + status = getTableDataUsingAllObjectCall(pGpu, + acpiFunction, + inOutData, + inOutDataSz, + tmpBuffer, + tmpBufferSz, + curOffset, + &rtnSize); + if (status != NV_OK) + { + // error returned on get, must be no more globs + break; + } + + // Confirm this glob header looks okay. + pNbsiDrvrObj = (PNBSI_DRIVER_OBJ) tmpBuffer; + status = testNbsiTable(pGpu, + (PNBSI_GEN_OBJ) pNbsiDrvrObj, + wantedGlobType, + curGlob, + idx, + NBSI_TBL_SOURCE_ACPI_BY_ALL_OBJ, + tmpBufferSz, + TEST_NBSI_TABLE_SKIP_ALLOC_SIZE_CHECK, + TEST_NBSI_TABLE_SKIP_HASH_CHECK, + TEST_NBSI_TABLE_SKIP_GLOBTYPE_CHECK); + if (status != NV_OK) + { + // bad table format + // pNbsiObj->nbsiTableState[idx][objt] = NBSI_TABLE_BAD; + return status; + } + + curGlob++; + if (wantedGlobType == (NBSI_GLOB_TYPE) GLOB_TYPE_GET_NBSI_DIR) + { + dirContentsSize += pNbsiDrvrObj->objHdr.size; + } + else + { + if (pNbsiDrvrObj->objHdr.globType == wantedGlobType) + { + cntOfGlobsWithWantedGlobType++; + // if want best fit (wantedGlobIdx==0) or we are at real one + if (!wantedGlobIdx || + (cntOfGlobsWithWantedGlobType == wantedGlobIdx)) + { + curGlobSize = pNbsiDrvrObj->objHdr.size; + // if wantedGlobIdx == 0 and driver object use best match + if (!wantedGlobIdx && + (pNbsiDrvrObj->objHdr.globType == NBSI_DRIVER)) + { + // Check the match score for this table + thisScore = + checkUidMatch(pGpu, + (PNBSI_DRIVER_OBJ) pNbsiDrvrObj, + idx, + NBSI_TBL_SOURCE_ACPI_BY_ALL_OBJ, + curGlob, + &driverVersion); + + // Keep track of the best match + if ((thisScore > 0) && + ((thisScore > bestDriverObjectMatchScore) || + ((thisScore == bestDriverObjectMatchScore) && + (driverVersion > bestFitDriverVersion)))) + { + bestDriverObjectMatchSize = pNbsiDrvrObj->objHdr.size; + bestDriverObjectMatchOffset = curOffset; + bestDriverObjectMatchScore = thisScore; + bestDriverObjectIndex = + cntOfGlobsWithWantedGlobType; + bestFitDriverVersion = driverVersion; + } + } + else + { + bestDriverObjectIndex = cntOfGlobsWithWantedGlobType; + bMyFound = NV_TRUE; + } + } + } + } + + // if not found yet move to the next object + if (!bMyFound) + { + curOffset = curOffset + pNbsiDrvrObj->objHdr.size; + } + } + + if ((status == NV_OK) && + bestDriverObjectMatchSize && + (wantedGlobType == NBSI_DRIVER) && + !wantedGlobIdx) + { + // replace last checked with best fit driver glob + curOffset = bestDriverObjectMatchOffset; + curGlobSize = bestDriverObjectMatchSize; + bMyFound = NV_TRUE; + NV_PRINTF(LEVEL_ERROR, + "NBSI Gpu%d Tloc=%d/Glob=%d best fit (score/ver = (%x/%d))\n", + idx, NBSI_TBL_SOURCE_ACPI_BY_ALL_OBJ, + bestDriverObjectIndex, bestDriverObjectMatchScore, + bestFitDriverVersion); + } + + if ((wantedGlobType == (NBSI_GLOB_TYPE) GLOB_TYPE_GET_NBSI_DIR) && + ((nbsiDirSize + dirContentsSize) > 0) && + (status == NV_OK)) + { + curOffset = 0; + curGlob = 0; + bestDriverObjectIndex = 0; + curGlobSize = nbsiDirSize + dirContentsSize; + bMyFound = NV_TRUE; + } + + if ((status == NV_OK) && bMyFound) + { + // we know which glob number we want to get the entire glob for + // allocate memory to return the entire glob in + pNbsiDrvrObj = portMemAllocNonPaged(curGlobSize); + if (pNbsiDrvrObj == NULL) + { + NV_PRINTF(LEVEL_ERROR, + "Can't alloc 0x%x bytes for ACPI NBSI table.\n", + curGlobSize); + return NV_ERR_GENERIC; + } + + // read all of the current glob in + rtnSize = curGlobSize; + status = getTableDataUsingAllObjectCall(pGpu, + acpiFunction, + inOutData, + inOutDataSz, + (NvU8 *) pNbsiDrvrObj, + curGlobSize, + curOffset, + &rtnSize); + if (status != NV_OK) + { + // this shouldn't happen since we did this once before + portMemFree(pNbsiDrvrObj); + pNbsiDrvrObj = NULL; + return status; + } + + if (wantedGlobType != (NBSI_GLOB_TYPE) GLOB_TYPE_GET_NBSI_DIR) + { + if (validationOption == NBSI_VALIDATE_IGNORE_CRC) + { + bCheckCRC = NV_FALSE; + } + + // Confirm this glob header looks okay. + status = testNbsiTable(pGpu, + (PNBSI_GEN_OBJ) pNbsiDrvrObj, + wantedGlobType, + curGlob, + idx, + NBSI_TBL_SOURCE_ACPI_BY_ALL_OBJ, + curGlobSize, + TEST_NBSI_TABLE_DO_ALLOC_SIZE_CHECK, + bCheckCRC, + TEST_NBSI_TABLE_DO_GLOBTYPE_CHECK); + if (status != NV_OK) + { + // bad table format (most likely hash test failure) + portMemFree(pNbsiDrvrObj); + pNbsiDrvrObj = NULL; + return status; + } + } + + *pRtnObj = (PNBSI_GEN_OBJ) pNbsiDrvrObj; + if (wantedGlobType == (NBSI_GLOB_TYPE) GLOB_TYPE_GET_NBSI_DIR) + { + *pRtnObjSize = curGlobSize; + *pActualGlobIdx = curGlob; + } + else + { + *pRtnObjSize = pNbsiDrvrObj->objHdr.size; + *pActualGlobIdx = bestDriverObjectIndex; + } + *pbFound = NV_TRUE; + } + return status; +} + +//---------------------------------------------------------------------------- +// NV_STATUS _extractNBSIObjFromACPIDir(pGpu, idx, +// curDir, +// acpiFunction, validationOption, acpiMethod, +// wantedGlobType, wantedGlobIdx, +// pActualGlobIdx, +// *pRtnObj, *pRtnObjSize, *pbFound) +// +// This extracts an NBSI from an ACPI directory. +// With RID 67191, also supports BY_OBJ_TYPE retrieval via UEFI runtime +// variables. +// +// Input parameters: +// pGpu Current pGpu object +// idx GPU instance / index +// curDir table source (acpi or uefi) +// acpiFunction selector for acpi function (nbsi vs hybrid) +// validationOption test validation option +// acpiMethod Acpi method(s) available to access table +// wantedGlobType desired globtype +// wantedGlobIdx desired glob index +// pActualGlobIdx rtn actual index. +// pRtnObj pointer to memory allocated for return object +// (or NULL if pRtnObjSize is 0) +// pRtnObjSize pointer to return object size (use 0 to query +// for object presence and size. (query will cache +// if globIdx is 0 and room is available in cache) +// pbFound pointer to NvBool for return status. +// +// Output parameters: +// NV_STATUS: NV_OK if there were no operational issues +// (such as memory allocation failure) +// looking for the table. +// *pRtnObj pointer to return object (if pbFound=NV_TRUE) +// *pRtnObjSize pointer to return object size. +// *pbFound pointer to NvBool set to NV_TRUE if object was found +// +//---------------------------------------------------------------------------- + +static NV_STATUS _extractNBSIObjFromACPIDir +( + OBJGPU *pGpu, + NvU32 idx, + NvU16 curDir, + ACPI_DSM_FUNCTION acpiFunction, + NBSI_VALIDATE validationOption, + NBSI_ACPI_METHOD acpiMethod, + NBSI_GLOB_TYPE wantedGlobType, + NvU8 wantedGlobIdx, + NvU8 * pActualGlobIdx, + PNBSI_GEN_OBJ * pRtnObj, + NvU32 * pRtnObjSize, + NvBool * pbFound +) +{ + NV_STATUS status = NV_ERR_GENERIC; + void* inOutData = NULL; + NvU32 inOutDataSz = NV_ACPI_DSM_READ_SIZE; + void* tmpBuffer = NULL; + NvU32 tmpBufferSz = NV_ACPI_DSM_READ_SIZE; + + NV_ASSERT(pActualGlobIdx); + NV_ASSERT(pRtnObj); + NV_ASSERT(pRtnObjSize); + NV_ASSERT(pbFound); + + if ((curDir != NBSI_TBL_SOURCE_ACPI) && + (curDir != NBSI_TBL_SOURCE_UEFI)) + { + // Function only supports ACPI and UEFI sources. + return NV_ERR_INVALID_ARGUMENT; + } + + if ((curDir == NBSI_TBL_SOURCE_UEFI) || + (acpiMethod == NBSI_TBL_SOURCE_ACPI_BY_OBJ_TYPE) || + (acpiMethod == NBSI_TBL_SOURCE_ACPI_BY_ALL_OBJ) || + (acpiMethod == NBSI_TBL_SOURCE_ACPI_BOTH_METHODS)) + { + // Allocate memory for the ACPI inout parameter buffer + inOutData = portMemAllocNonPaged(inOutDataSz); + if (inOutData == NULL) + { + NV_PRINTF(LEVEL_ERROR, + "Unable to allocate 0x%x bytes for ACPI parm memory.\n", + inOutDataSz); + status = NV_ERR_NO_MEMORY; + goto failed; + } + + // Allocate memory for the temporary/local collection buffer + tmpBuffer = portMemAllocNonPaged(tmpBufferSz); + if (tmpBuffer == NULL) + { + NV_PRINTF(LEVEL_ERROR, + "Unable to allocate 0x%x bytes for ACPI parm memory.\n", + tmpBufferSz); + status = NV_ERR_NO_MEMORY; + goto failed; + } + + // + // Access types. + // UEFI only supports GetByObjType. + // ACPI supports both GetByObjType and GetAllObjs. + // ACPI requires sub-function support. + // + status = NV_ERR_INVALID_ACCESS_TYPE; + if (((curDir == NBSI_TBL_SOURCE_UEFI) || + (acpiMethod == NBSI_TBL_SOURCE_ACPI_BY_OBJ_TYPE) || + (acpiMethod == NBSI_TBL_SOURCE_ACPI_BOTH_METHODS)) && + (wantedGlobType != (NBSI_GLOB_TYPE) GLOB_TYPE_GET_NBSI_DIR)) + { + status = getTableUsingObjTypeCall(pGpu, + idx, + curDir, + acpiFunction, + validationOption, + wantedGlobType, + wantedGlobIdx, + pActualGlobIdx, + pRtnObj, + pRtnObjSize, + pbFound, + inOutData, + inOutDataSz, + tmpBuffer, + tmpBufferSz); + } + else if (curDir == NBSI_TBL_SOURCE_ACPI) + { + if ((acpiMethod == NBSI_TBL_SOURCE_ACPI_BY_ALL_OBJ) || + ((wantedGlobType == (NBSI_GLOB_TYPE) GLOB_TYPE_GET_NBSI_DIR) && + (acpiMethod == NBSI_TBL_SOURCE_ACPI_BOTH_METHODS))) + { + status = getTableUsingAllObjectCall(pGpu, + idx, + acpiFunction, + validationOption, + wantedGlobType, + wantedGlobIdx, + pActualGlobIdx, + pRtnObj, + pRtnObjSize, + pbFound, + inOutData, + inOutDataSz, + tmpBuffer, + tmpBufferSz); + } + } + } + +failed: + if (inOutData != NULL) + portMemFree((void*)inOutData); + if (tmpBuffer != NULL) + portMemFree((void*)tmpBuffer); + + return status; +} + +//---------------------------------------------------------------------------- +// NV_STATUS getNbsiObjByType(pGpu, globType, +// *pWantedGlobIdx, *pWantedGlobSource, +// rtnObjOffset, +// *pRtnObj, *pRtnObjSize, +// *pTotalObjSize, *pRtnGlobStatus, +// acpiFunction, validateOption) +// +// This function gets an object with globType (and wantedGlobIdx) from the +// NBSI table. If wantedGlobIdx is 0, it will cache the object in the nbsi +// cache for future reads. +// If the object exists and will fit in the users memory it returns success +// in pRtnGlobStatus, otherwise it sets this to incomplete +// +// Input parameters: +// pGpu Current pGpu object +// idx GPU instance / index +// globType desired globtype +// wantedGlobIdx desired glob index +// pWantedGlobSource in/out directory source of directory wanted +// rtnObjOffset offset into object to be returned (0=start) +// pRtnObj pointer to memory allocated for return object +// (or NULL if pRtnObjSize is 0) +// pRtnObjSize pointer to return object size (use 0 to query +// for object presence and size. (query will cache +// if globIdx is 0 and room is available in cache) +// pTotalObjSize total size of object being retrieved. +// pRtnGlobStatus pointer to return status +// acpiFunction selector for acpi function (nbsi vs hybrid) +// validationOption object validation option +// +// Output parameters: +// NV_STATUS: NV_OK if there were no operational issues +// (such as memory allocation failure) +// looking for the table. +// *pRtnObj pointer to memory for return object +// *pRtnObjSize pointer to return object size. +// *pRtnGlobStatus +// NV2080_CTRL_BIOS_GET_NBSI_NO_TABLE - no NBSI table found +// NV2080_CTRL_BIOS_GET_NBSI_BAD_TABLE - corrupted NBSI table found +// NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE - object was found but it's size +// is larger than pRtnObjSize. pRtnObjSize is +// set to actual size of object. +// NV2080_CTRL_BIOS_GET_NBSI_SUCCESS - object found and copied to +// pRtnObj and pRtnObjSize set to actual size +// NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND - NBSI table present, but object +// was not found matching globType and globTypeIdx +// +//---------------------------------------------------------------------------- + +NV_STATUS getNbsiObjByType +( + OBJGPU *pGpu, + NvU16 globType, + NBSI_SOURCE_LOC * pWantedGlobSource, + NvU8 * pWantedGlobIdx, + NvU32 wantedRtnObjOffset, + NvU8 * pRtnObj, + NvU32 * pRtnObjSize, + NvU32 * pTotalObjSize, + NvU32 * pRtnGlobStatus, + ACPI_DSM_FUNCTION acpiFunction, + NBSI_VALIDATE validationOption +) +{ + NvU32 idx; + NV_STATUS status = NV_ERR_GENERIC; + PNBSI_DIRECTORY pNbsiDir = NULL; + NvU32 nbsiDirSize = 0; + NvBool bFound; + NvBool bFreeDirMemRequired; + NvBool bFreeTestObjRequired; + NBSI_GEN_OBJ *pTestObj; + NvU32 testObjSize; + NvU8 actualGlobIdx = 0; + NvU8 * bufPtr; + NvU16 curDir; + NvU16 dirList; + NvU16 searchDirNdx = 0; + NBSI_SOURCE_LOC nbsiDirLocs[] = {NBSI_TBL_SOURCE_REGISTRY, + NBSI_TBL_SOURCE_VBIOS, + NBSI_TBL_SOURCE_SBIOS, + NBSI_TBL_SOURCE_ACPI, + NBSI_TBL_SOURCE_UEFI, + 0}; + NBSI_ACPI_METHOD acpiMethod = NBSI_TBL_SOURCE_ACPI_UNKNOWN; + NBSI_OBJ *pNbsiObj = getNbsiObject(); + + NV_ASSERT(pWantedGlobSource); + NV_ASSERT(pWantedGlobIdx); + NV_ASSERT(pTotalObjSize); + NV_ASSERT(pRtnGlobStatus); + NV_ASSERT(!(*pRtnObjSize != 0 && pRtnObj == NULL)); + + if (pGpu == NULL) + { + return NV_ERR_GENERIC; + } + + idx = gpuGetInstance(pGpu); + if (idx >= NV_MAX_DEVICES) + { + NV_PRINTF(LEVEL_ERROR, + "Invalid gpu index %d. Aborting NBSI get object.\n", + idx); + return NV_ERR_GENERIC; + } + + if (globType == GLOB_TYPE_GET_NBSI_ACPI_RAW) + { + NvU16 rtnSize; + // + // (IN) wantedRtnObjOffset = acpi function, + // (IN/OUT) inoutdata to data (always use 4K!) + // (IN/OUT) pSizeOfData In = size of inoutdata, Out = size returned + // + rtnSize = (NvU16) (*pRtnObjSize & 0xffff); + status = pGpu->pOS->osCallACPI_DSM(pGpu, + acpiFunction, + wantedRtnObjOffset, + (NvU32 *)pRtnObj, + (NvU16 *)&rtnSize); + + *pRtnObjSize = rtnSize; + *pWantedGlobSource = (NBSI_SOURCE_LOC) status; + return NV_OK; + } + + if ((globType != NBSI_DRIVER) && (*pWantedGlobIdx==1)) + { + // + // object types other than NBSI_DRIVER have best fit index of 1 + // So if they ask for best fit (0) or 1 it's the same object. + // If they ask for 0 it gets in the cache as 0 or 1. + // If they ask for 1 first, need to allow 0 as well. + // + *pWantedGlobIdx = 0; + } + + // Currently only NBSI and NBCI objects are cached... + if ((acpiFunction == ACPI_DSM_FUNCTION_NBSI) || + (acpiFunction == ACPI_DSM_FUNCTION_NBCI)) + { + status = getNbsiObjFromCache( pGpu, + idx, + globType, + pWantedGlobSource, + pWantedGlobIdx, + wantedRtnObjOffset, + (PNBSI_GEN_OBJ) pRtnObj, + pRtnObjSize, + pTotalObjSize, + pRtnGlobStatus); + if (status == NV_OK) + { + // It's in the cache, it may or may not fit. + return status; + } + } + + // always assume the registry may be present... even if it wasn't before + pNbsiObj->availDirLoc[idx] |= NBSI_TBL_SOURCE_REGISTRY; + + // + // Since multiple DSM functions may contain getobject/getallobect subfunctions... + // declaring all ACPI functions as invalid is no longer true. + // So we'll always renable the acpi option. + // Also now that there's generic functions/subfunctions and a cache of dsm + // supported subfunctions this should prevent alot of re-attempts on acpi + // calls that won't work. + // + pNbsiObj->availDirLoc[idx] |= NBSI_TBL_SOURCE_ACPI; + + // + // loop through each possible table source until we find the object we're + // looking for + // + if (*pWantedGlobSource == 0) + { + if ((acpiFunction == ACPI_DSM_FUNCTION_NBSI) || + (acpiFunction == ACPI_DSM_FUNCTION_NBCI) || + (acpiFunction == ACPI_DSM_FUNCTION_CURRENT)) + { + dirList = pNbsiObj->availDirLoc[idx]; + } + else + { + dirList = NBSI_TBL_SOURCE_ACPI; + } + } + else + { + if ((acpiFunction == ACPI_DSM_FUNCTION_NBSI) || + (acpiFunction == ACPI_DSM_FUNCTION_NBCI) || + (acpiFunction == ACPI_DSM_FUNCTION_CURRENT)) + { + dirList = *pWantedGlobSource & pNbsiObj->availDirLoc[idx]; + } + else + { + dirList = *pWantedGlobSource; + } + } + + bFound = NV_FALSE; + *pRtnGlobStatus = NV2080_CTRL_BIOS_GET_NBSI_NOT_FOUND; + searchDirNdx = 0; + while (!bFound && nbsiDirLocs[searchDirNdx]) + { + curDir = nbsiDirLocs[searchDirNdx] & dirList; + if (curDir == 0) + { + searchDirNdx++; + } + else + { + // Not in the cache so get it from the directory + status = getNbsiDirectory(pGpu, + idx, + &pNbsiDir, + &nbsiDirSize, + curDir, + &bFreeDirMemRequired, + &acpiMethod, + acpiFunction); + + if (status != NV_OK) + { + // remove any directories not found. + pNbsiObj->availDirLoc[idx] &= ~curDir; + + // bump to next possible. + searchDirNdx++; + // check if searched all directory sources and come up empty. + if (nbsiDirLocs[searchDirNdx] == 0) + { + *pRtnGlobStatus = NV2080_CTRL_BIOS_GET_NBSI_NO_TABLE; + if (bFreeDirMemRequired) + { + portMemFree((void*)pNbsiDir); + } + return status; + } + } + else + { + testObjSize = 0; + pTestObj = NULL; + bFreeTestObjRequired = NV_FALSE; + if ((curDir & NBSI_TBL_SOURCE_ACPI) || + (curDir & NBSI_TBL_SOURCE_UEFI)) + { + status = _extractNBSIObjFromACPIDir(pGpu, + idx, + curDir, + acpiFunction, + validationOption, + acpiMethod, + globType, + *pWantedGlobIdx, + &actualGlobIdx, + &pTestObj, + &testObjSize, + &bFound); + if (pTestObj) + { + // pTestObj was allocated and needs to be released. + bFreeTestObjRequired = NV_TRUE; + } + } + else + { + status = extractNBSIObjFromDir(pGpu, + idx, + pNbsiDir, + nbsiDirSize, + curDir, + globType, + *pWantedGlobIdx, + &actualGlobIdx, + &pTestObj, + &testObjSize, + validationOption, + &bFound); + } + + if (bFound == NV_TRUE) + { + // Currently only NBSI and NBCI objects are cached... + if ((acpiFunction == ACPI_DSM_FUNCTION_NBSI) || + (acpiFunction == ACPI_DSM_FUNCTION_NBCI)) + { + if ((globType != NBSI_DRIVER) && (actualGlobIdx==1)) + { + // + // object types other than NBSI_DRIVER have best fit + // index of 1. + // So if they ask for best fit (0) or 1 it's the same + // object. + // If they ask for 0 it gets in the cache as 0 or 1. + // If they ask for 1 first, need to allow 0 as well. + // + *pWantedGlobIdx = 0; + } + // Cache everything (until we run out of cache entries) + if (globType != GLOB_TYPE_GET_NBSI_DIR) + { + addNbsiCacheEntry(pGpu, + idx, + pTestObj, + testObjSize, + *pWantedGlobSource, + *pWantedGlobIdx, + curDir, + actualGlobIdx); + } + } + + // return the full table size + *pTotalObjSize = testObjSize; + + // is rtnsize larger than remaining part of table? + if (*pRtnObjSize >= (*pTotalObjSize - wantedRtnObjOffset)) + { + // then we can return it all this time. + *pRtnObjSize = *pTotalObjSize - wantedRtnObjOffset; + *pRtnGlobStatus = NV2080_CTRL_BIOS_GET_NBSI_SUCCESS; + } + else + { + // return what we can and indicate incomplete. + *pRtnGlobStatus = NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE; + } + + if (*pRtnObjSize > 0) + { + bufPtr = (NvU8 *) pTestObj; + bufPtr = &bufPtr[wantedRtnObjOffset]; + portMemCopy(pRtnObj, *pRtnObjSize, bufPtr, *pRtnObjSize); + } + } + else + { + if (status == NV_ERR_INVALID_DATA) + { + *pRtnGlobStatus = NV2080_CTRL_BIOS_GET_NBSI_BAD_HASH; + } + + searchDirNdx++; + // + // check if we've searched all directory sources and + // come up empty. + // + if (nbsiDirLocs[searchDirNdx] == 0) + { + if (*pRtnGlobStatus != NV2080_CTRL_BIOS_GET_NBSI_BAD_HASH) + { + *pRtnGlobStatus = + NV2080_CTRL_BIOS_GET_NBSI_NO_TABLE; + } + + // release any memory allocated. + if (bFreeTestObjRequired && pTestObj) + { + portMemFree((void*)pTestObj); + } + + // check to released memory temp allocated for the directory + if (bFreeDirMemRequired) + { + portMemFree((void*)pNbsiDir); + } + return status; + } + } + + if (bFreeTestObjRequired && pTestObj) + { + portMemFree((void*)pTestObj); + pTestObj = NULL; + } + } + + // check to released memory temp allocated for the directory + if (bFreeDirMemRequired) + { + portMemFree((void*)pNbsiDir); + pNbsiDir = NULL; + } + } + } + return status; +} + +//---------------------------------------------------------------------------- +// NV_STATUS initNbsiTable(pGpu) +// +// This function finds, allocates and intializes the nbsi table. +// +// Input parameters: +// pGpu pointer to this pGpu object +// none +// +// Output parameters: +// NV_STATUS: NV_OK if there were no operational issues +// (such as memory allocation failure) +// looking for the table. +//---------------------------------------------------------------------------- + +NV_STATUS initNbsiTable(OBJGPU *pGpu) +{ + NvU32 idx; + NV_STATUS status; + NvU32 globTypeRtnStatus; + NBSI_GEN_OBJ *pNbsiDir = NULL; + NvU32 nbsiDirSize; + NvU32 totalObjSize; + NvU8 curTbl; + NBSI_SOURCE_LOC nbsiDriverSource; + NvU8 nbsiDriverIndex; + NBSI_OBJ *pNbsiObj = getNbsiObject(); + + if (pGpu == NULL) + { + return NV_ERR_GENERIC; + } + + idx = gpuGetInstance(pGpu); + if (idx >= NV_MAX_DEVICES) + { + NV_PRINTF(LEVEL_ERROR, "Invalid gpu index %d. Aborting NBSI init.\n", idx); + return NV_ERR_GENERIC; + } + + if (pNbsiObj->nbsiDrvrTable[idx] != NULL) + { + NV_PRINTF(LEVEL_ERROR, "NBSI table already initialized for GPU index %d. Aborting NBSI init.\n", idx); + return NV_WARN_NOTHING_TO_DO; + } + + NV_PRINTF(LEVEL_INFO, "Initializing NBSI tables for gpu %d\n", idx); + + status = allocNbsiCache(pGpu, idx, NBSI_INITCACHEENTRYCNT); + if (status != NV_OK) + { + return status; + } + // driver version - filled in in nbsiinit.c + pNbsiObj->DriverVer.OS = 0; // a (7=vista, 6=nt) + pNbsiObj->DriverVer.DX = 0; // bb (15=vista, 14=others) +#ifdef NV_DRIVER_VERSION_NUMBER + pNbsiObj->DriverVer.Rev = NV_DRIVER_VERSION_NUMBER; // cdddd +#else + pNbsiObj->DriverVer.Rev = 0; // cdddd +#endif + + if (NVOS_IS_WINDOWS) + { + if (NVCPU_IS_64_BITS) + { + setNbsiOSstring("Vista64",7,2,3); + setNbsiOSstring("Vista",5,1,3); + setNbsiOSstring("",0,0,3); + } + else + { + setNbsiOSstring("Vista",5,1,2); + setNbsiOSstring("",0,0,2); + } + pNbsiObj->DriverVer.OS = 7; + pNbsiObj->DriverVer.DX = 15; + } + else + { + setNbsiOSstring("",0,0,1); + } + + // print debug info. + checkUidMatch(pGpu, NULL, idx, 0, 0, NULL); + + // By asking how big the NBSI_DRIVER is, it caches it (if found) + nbsiDirSize = 0; + nbsiDriverSource = 0; + nbsiDriverIndex = 0; + status = getNbsiObjByType(pGpu, + NBSI_DRIVER, + &nbsiDriverSource, + &nbsiDriverIndex, + 0, // offset + NULL, + &nbsiDirSize, + &totalObjSize, + &globTypeRtnStatus, + ACPI_DSM_FUNCTION_NBCI, + NBSI_VALIDATE_ALL); + + // If we didn't find it. + if (status != NV_OK) + { + // if NBCI failed, lets try NBSI... + nbsiDirSize = 0; + nbsiDriverSource = 0; + nbsiDriverIndex = 0; + status = getNbsiObjByType(pGpu, + NBSI_DRIVER, + &nbsiDriverSource, + &nbsiDriverIndex, + 0, // offset + NULL, + &nbsiDirSize, + &totalObjSize, + &globTypeRtnStatus, + ACPI_DSM_FUNCTION_NBSI, + NBSI_VALIDATE_ALL); + } + + if ((status == NV_OK) && + (globTypeRtnStatus == NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE)) + { + // Now since it's cached find what memory location it's at and save it. + nbsiDriverSource = 0; + nbsiDriverIndex = 0; + status = getNbsiCacheInfoForGlobType(pGpu, + idx, + NBSI_DRIVER, + &nbsiDriverSource, + &nbsiDriverIndex, + &pNbsiDir, + &nbsiDirSize, + &curTbl); + if (status == NV_OK) + { + // make a copy of the pointer for easy access... no duplicate mem + pNbsiObj->nbsiDrvrTable[idx] = (NvU8 *) pNbsiDir; + } + } + + // + // even if the nbsi driver object is not found, the nbsi table could hold + // other objects. So we'll assume success for now. + // + status = NV_OK; + if (nbsiDriverSource == 0) + { + NV_PRINTF(LEVEL_INFO, "No NBSI table for gpu %d found.\n", idx); + } + else if (nbsiDriverSource & NBSI_TBL_SOURCE_REGISTRY) + { + NV_PRINTF(LEVEL_INFO, + "Using NBSI driver object for gpu %d from registry.\n", + idx); + } + else if (nbsiDriverSource & NBSI_TBL_SOURCE_VBIOS) + { + NV_PRINTF(LEVEL_INFO, + "Using NBSI driver object for gpu %d from VBIOS.\n", + idx); + } + else if (nbsiDriverSource & NBSI_TBL_SOURCE_SBIOS) + { + NV_PRINTF(LEVEL_INFO, + "Using NBSI driver object for gpu %d from SBIOS.\n", + idx); + } + else if (nbsiDriverSource & NBSI_TBL_SOURCE_ACPI) + { + NV_PRINTF(LEVEL_INFO, + "Using NBSI driver object for gpu %d from ACPI table.\n", + idx); + } + else + { + NV_PRINTF(LEVEL_INFO, + "Using NBSI driver object for gpu %d from unknown source.\n", + idx); + } + + return status; +} + +//---------------------------------------------------------------------------- +// NV_STATUS freeNbsiTable(pGpu) +// +// This function frees up the nbsi cache table +// +// Input parameters: +// pGpu pointer to this GPU object +// +// Output parameters: +// none +// +//---------------------------------------------------------------------------- + +void freeNbsiTable(OBJGPU *pGpu) +{ + NvU32 idx = gpuGetInstance(pGpu); + NBSI_OBJ *pNbsiObj = getNbsiObject(); + + if (idx >= NV_MAX_DEVICES) + { + NV_PRINTF(LEVEL_ERROR, + "Invalid gpu index %d. Aborting free NBSI table.\n", + idx); + return; + } + + // free up memory used by all cache entries + freeNbsiCache( pGpu, idx); + + // Free up the nbsi reg override list. + portMemFree(pNbsiObj->regOverrideList[idx]); + pNbsiObj->regOverrideList[idx] = NULL; +} + +void initNbsiObject(NBSI_OBJ *pNbsiObj) +{ + NvU32 i; + for (i = 0; i < MAX_NBSI_OS; i++) + { + pNbsiObj->nbsiOSstr[i][0] = 0; + pNbsiObj->nbsiOSstrLen[i] = 0; + pNbsiObj->nbsiOSstrHash[i] = FNV1_32_INIT; + } + pNbsiObj->curMaxNbsiOSes = 1; + + // driver version a.bb.1c.dddd + pNbsiObj->DriverVer.OS = 0; // a + pNbsiObj->DriverVer.DX = 0; // bb + pNbsiObj->DriverVer.Rev = 0; // cdddd + + for (i = 0; i < NV_MAX_DEVICES; i++) + { + pNbsiObj->availDirLoc[i] = NBSI_TBL_SOURCE_ALL; + pNbsiObj->pTblCache[i] = NULL; + pNbsiObj->nbsiDrvrTable[i] = NULL; + pNbsiObj->regOverrideList[i] = NULL; + } +} + +NBSI_OBJ *getNbsiObject() +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJPFM *pPfm = SYS_GET_PFM(pSys); + return &pPfm->nbsi; +} diff --git a/src/nvidia/src/kernel/platform/nbsi/nbsi_osrg.c b/src/nvidia/src/kernel/platform/nbsi/nbsi_osrg.c new file mode 100644 index 000000000..b74fe3936 --- /dev/null +++ b/src/nvidia/src/kernel/platform/nbsi/nbsi_osrg.c @@ -0,0 +1,244 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * @file + * @brief NBSI table initialization, search and hash routines. + */ + +#include "os/os.h" +#include "platform/nbsi/nbsi_table.h" +#include "platform/nbsi/nbsi_read.h" +#include "gpu/gpu.h" + +/*! + * The following code pulled from nvString.c which is in drivers/common/src + * but apparently not built so the rm can use them. + * + */ +static NvU16 _nvStrLen(const char *szStr) +{ + NvU16 dwLen = 0; + // next statements on one line so easier to step over in debugger + while (*szStr != '\0') { dwLen ++; szStr ++; } + return (dwLen); +} + +/*! + * NV_STATUS nbsiReadRegistryDword(pGpu, pRegParmStr, pData); + * + * This function searches both the nbsi table and the os registry table and + * returns the best result. + * + * Input parameters: + * pGpu - OBJGPU pointer + * pRegParmStr - registry element string + * pData - registry value + * + * Returns NV_STATUS: + * NV_OK: key was found and data returned in pData + * !NV_OK: key was not found in either nbsi table or os registry + * found. + * + * Output parameters: + * pData - registry value (if NV_STATUS is NV_OK) + * + */ +NV_STATUS nbsiReadRegistryDword +( + OBJGPU *pGpu, + const char *pRegParmStr, + NvU32 *pData +) +{ + NBSI_OBJ *pNbsiObj = getNbsiObject(); + NvU32 nbsiDword; + NvU16 pathHash; + NvU8 *pRetBuf; + NvU32 retSize; + NvU32 errorCode; + NvU16 module = NV2080_CTRL_BIOS_NBSI_MODULE_RM; + NV_STATUS status; + NvU32 elementHashArray[MAX_NBSI_OS]; + NvU8 maxOSndx; + + NV_ASSERT_OR_RETURN(pRegParmStr != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pData != NULL, NV_ERR_INVALID_ARGUMENT); + + if ((pGpu == NULL) || (pNbsiObj == NULL)) + { + return NV_ERR_INVALID_OBJECT; + } + + // Check to make sure we are not in the power management code path + if ((pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_PM_CODEPATH)) +#if defined(DEBUG) + && (!pGpu->getProperty(pGpu, PDB_PROP_GPU_DO_NOT_CHECK_REG_ACCESS_IN_PM_CODEPATH)) +#endif + ) + { + // + // Registry reads should only be done during boot and in the corresponding + // engine *initRegistryOverrides function where possible. See bug 649189. + // + NV_PRINTF(LEVEL_ERROR, + "osReadRegistryDword called in Sleep path can cause excessive delays!\n"); + + NV_ASSERT(0); + return NV_ERR_INVALID_REQUEST; + } + + pathHash = pNbsiObj->nbsiBlankPathHash; + maxOSndx = pNbsiObj->curMaxNbsiOSes; + + // The RM module uses a blank (relative path) so just do element. + fnv1Hash20Array((const NvU8 *) pRegParmStr, + _nvStrLen(pRegParmStr), + elementHashArray, + maxOSndx); + + retSize = sizeof(nbsiDword); + pRetBuf = (NvU8 *) &nbsiDword; + + // + // Read from both NBSI table and os reg tables... then decide what + // to return. + // + status = getNbsiValue(pGpu, + module, + pathHash, + maxOSndx, + elementHashArray, + pRetBuf, + &retSize, + &errorCode); + if (status == NV_OK) + { + if (errorCode == NV2080_CTRL_BIOS_GET_NBSI_SUCCESS) + { + *pData = nbsiDword; + } + else + { + // + // assert if we didn't have enough room to hold the returned data. + // Since we define the return as a dword here, this could only be + // because the registry has the key but it's defined longer than a + // dword. i.e. byte array or extended byte array. + // + NV_ASSERT(errorCode != NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE); + status = NV_ERR_GENERIC; + } + } + + return status; +} + +/*! + * NV_STATUS nbsiReadRegistryString(pGpu, pRegParmStr, pData, pCbLen); + * + * This function searches both the nbsi table and the os registry table and + * returns the best result. + * + * Input parameters: + * pGpu - OBJGPU pointer + * pRegParmStr - registry element string + * pData - registry value + * pCbLen - size of registry in bytes + * + * Returns NV_STATUS: + * NV_OK: key was found and data returned in pData + * !NV_OK: key was not found in either nbsi table or os registry + * found. + * + * Output parameters: + * pData - registry value (if NV_STATUS is NV_OK) + * pCbLen - size of registry in bytes (if NV_STATUS is NV_OK) + * + */ +NV_STATUS nbsiReadRegistryString +( + OBJGPU *pGpu, + const char *pRegParmStr, + NvU8 *pData, + NvU32 *pCbLen +) +{ + NBSI_OBJ *pNbsiObj = getNbsiObject(); + NvU16 pathHash; + NvU8 *pRetBuf; + NvU32 retSize; + NvU32 errorCode; + NvU16 module = NV2080_CTRL_BIOS_NBSI_MODULE_RM; + NV_STATUS status; + NvU32 elementHashArray[MAX_NBSI_OS]; + NvU8 maxOSndx; + + NV_ASSERT_OR_RETURN(pRegParmStr != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pCbLen != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(!(*pCbLen != 0 && pData == NULL), NV_ERR_INVALID_ARGUMENT); + + if ((pGpu == NULL) || (pNbsiObj == NULL)) + { + return NV_ERR_INVALID_OBJECT; + } + + pathHash = pNbsiObj->nbsiBlankPathHash; + maxOSndx = pNbsiObj->curMaxNbsiOSes; + + // The RM module uses a blank (relative path) so just do element. + fnv1Hash20Array((const NvU8 *)pRegParmStr, + _nvStrLen(pRegParmStr), + elementHashArray, + maxOSndx); + + // save the original length... to be used later if doing the NBSI read + retSize = (NvU32) *pCbLen; + pRetBuf = pData; + + // Read from NBSI and os reg tables... then decide what to return. + status = getNbsiValue(pGpu, + module, + pathHash, + maxOSndx, + elementHashArray, + pRetBuf, + &retSize, + &errorCode); + if (status == NV_OK) + { + if (errorCode == NV2080_CTRL_BIOS_GET_NBSI_SUCCESS) + { + *pCbLen = retSize; + } + else + { + // assert if we didn't have enough room to hold the returned data + NV_ASSERT(errorCode != NV2080_CTRL_BIOS_GET_NBSI_INCOMPLETE); + status = NV_ERR_GENERIC; + } + } + + + return status; +} diff --git a/src/nvidia/src/kernel/platform/p2p/p2p_caps.c b/src/nvidia/src/kernel/platform/p2p/p2p_caps.c index 0a997a58e..4f703c109 100644 --- a/src/nvidia/src/kernel/platform/p2p/p2p_caps.c +++ b/src/nvidia/src/kernel/platform/p2p/p2p_caps.c @@ -28,10 +28,15 @@ #include "kernel/gpu/bif/kernel_bif.h" #include "gpu/subdevice/subdevice.h" #include "gpu/gpu.h" +#include "vgpu/rpc.h" +#include "vgpu/vgpu_events.h" #include "platform/chipset/chipset.h" #include "platform/p2p/p2p_caps.h" #include "nvRmReg.h" #include "nvlimits.h" +#include "nvdevid.h" + +ct_assert(NV2080_GET_P2P_CAPS_UUID_LEN == NV_GPU_UUID_LEN); /** * @brief Determines if the GPUs are P2P compatible @@ -305,12 +310,24 @@ _kp2pCapsCheckStatusOverridesForPcie return NV_FALSE; } +/** + * @brief Check GPU Pcie mailbox P2P capability + * + * @param[in] pGpu OBJGPU pointer + * @param[out] pP2PWriteCapStatus Pointer to get the P2P write capability + * @param[out] pP2PReadCapStatus Pointer to get the P2P read capability + * @param[out] pbCommonPciSwitch To return if GPUs are on a common PCIE switch + * + * @returns NV_OK, if successfully + * The write and read capability status are in the pP2PWriteCapStatus and pP2PReadCapStatus + */ static NV_STATUS _kp2pCapsGetStatusOverPcie ( NvU32 gpuMask, NvU8 *pP2PWriteCapStatus, - NvU8 *pP2PReadCapStatus + NvU8 *pP2PReadCapStatus, + NvBool *pbCommonPciSwitch ) { OBJGPU *pGpu = NULL; @@ -418,7 +435,7 @@ _kp2pCapsGetStatusOverPcie } } - // Check if GPUs have the HW P2P implementation + // Check if GPUs have the HW P2P implementation // Only lock for GSP_CLIENT. Get one GPU. if (pFirstGpu == NULL) @@ -477,7 +494,7 @@ _kp2pCapsGetStatusOverPcie // if (*pP2PReadCapStatus == NV0000_P2P_CAPS_STATUS_OK) *pP2PReadCapStatus = (p2pCapsParams.p2pReadCapsStatus == NV0000_P2P_CAPS_STATUS_OK ? gpuP2PReadCapsStatus : p2pCapsParams.p2pReadCapsStatus); - if (*pP2PWriteCapStatus == NV0000_P2P_CAPS_STATUS_OK) + if (*pP2PWriteCapStatus == NV0000_P2P_CAPS_STATUS_OK) *pP2PWriteCapStatus = (p2pCapsParams.p2pWriteCapsStatus == NV0000_P2P_CAPS_STATUS_OK ? gpuP2PWriteCapsStatus : p2pCapsParams.p2pWriteCapsStatus); // No need to continue if P2P is not supported @@ -506,6 +523,11 @@ done: } } + if (pbCommonPciSwitch != NULL) + { + *pbCommonPciSwitch = bCommonPciSwitchFound; + } + // // Not fatal if failing, effect would be perf degradation as we would not hit the cache. // So just assert. @@ -519,17 +541,93 @@ done: return status; } +/** + * @brief Check the host system BAR1 P2P capability + * + * @param[in] pGpu OBJGPU pointer + * @param[out] pP2PWriteCapStatus Pointer to get the P2P write capability + * @param[out] pP2PReadCapStatus Pointer to get the P2P read capability + * @param[out] bCommonPciSwitchFound To indicate if GPUs are on a common PCIE switch + * + * @returns NV_OK + */ +static NV_STATUS +_p2pCapsGetHostSystemStatusOverPcieBar1 +( + OBJGPU *pGpu, + NvU8 *pP2PWriteCapStatus, + NvU8 *pP2PReadCapStatus, + NvBool bCommonPciSwitchFound +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + NvU32 cpuFamily = DRF_VAL(0000_CTRL, _SYSTEM, _CPU_FAMILY, pSys->cpuInfo.family); + + if (bCommonPciSwitchFound) + { + // Both of GPUs are on the same PCIE switch + *pP2PWriteCapStatus = NV0000_P2P_CAPS_STATUS_OK; + *pP2PReadCapStatus = NV0000_P2P_CAPS_STATUS_OK; + + NV_PRINTF(LEVEL_INFO, "A common switch detected\n"); + } + else if (cpuFamily == NV0000_CTRL_SYSTEM_CPU_ID_AMD_FAMILY) + { + *pP2PWriteCapStatus = NV0000_P2P_CAPS_STATUS_OK; + + if (pSys->cpuInfo.type == NV0000_CTRL_SYSTEM_CPU_TYPE_RYZEN) + *pP2PReadCapStatus = NV0000_P2P_CAPS_STATUS_OK; + else + *pP2PReadCapStatus = NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED; + + NV_PRINTF(LEVEL_INFO, "AMD CPU detected\n"); + } + else if (cpuFamily == NV0000_CTRL_SYSTEM_CPU_ID_INTEL_FAMILY) + { + *pP2PWriteCapStatus = NV0000_P2P_CAPS_STATUS_OK; + *pP2PReadCapStatus = NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED; + + NV_PRINTF(LEVEL_INFO, "Intel CPU detected\n"); + } + else + { + *pP2PWriteCapStatus = NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED; + *pP2PReadCapStatus = NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED; + + NV_PRINTF(LEVEL_INFO, "Unsupported HW config\n"); + } + + NV_PRINTF(LEVEL_INFO, "WriteCap 0x%x ReadCap 0x%x\n", *pP2PWriteCapStatus, *pP2PReadCapStatus); + + return NV_OK; +} + +/** + * @brief Check GPU Pcie BAR1 P2P capability + * + * @param[in] pGpu OBJGPU pointer + * @param[out] pP2PWriteCapStatus Pointer to get the P2P write capability + * @param[out] pP2PReadCapStatus Pointer to get the P2P read capability + * @param[out] bCommonPciSwitchFound To indicate if GPUs are on a common PCIE switch + * + * @returns NV_OK, if GPUs at least support read or write + * NV_ERR_NOT_SUPPORTED, if GPUs does not support read and write + */ static NV_STATUS _kp2pCapsGetStatusOverPcieBar1 ( - NvU32 gpuMask + NvU32 gpuMask, + NvU8 *pP2PWriteCapStatus, + NvU8 *pP2PReadCapStatus, + NvBool bCommonPciSwitchFound ) { OBJGPU *pGpuPeer = NULL; NvU32 gpuInstance = 0; OBJGPU *pFirstGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance); KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pFirstGpu); - NV_STATUS status = NV_OK; + NvU8 writeCapStatus = *pP2PWriteCapStatus; + NvU8 readCapStatus = *pP2PReadCapStatus; if ((pKernelBif->forceP2PType != NV_REG_STR_RM_FORCE_P2P_TYPE_BAR1P2P)) { @@ -547,12 +645,27 @@ _kp2pCapsGetStatusOverPcieBar1 if (!kbusIsPcieBar1P2PMappingSupported_HAL(pFirstGpu, GPU_GET_KERNEL_BUS(pFirstGpu), pGpuPeer, GPU_GET_KERNEL_BUS(pGpuPeer))) { - status = NV_ERR_NOT_SUPPORTED; - break; + return NV_ERR_NOT_SUPPORTED; } } - return status; + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + _p2pCapsGetHostSystemStatusOverPcieBar1(pFirstGpu, &writeCapStatus, + &readCapStatus, bCommonPciSwitchFound)); + + if (*pP2PWriteCapStatus == NV0000_P2P_CAPS_STATUS_OK) + *pP2PWriteCapStatus = writeCapStatus; + if (*pP2PReadCapStatus == NV0000_P2P_CAPS_STATUS_OK) + *pP2PReadCapStatus = readCapStatus; + + if ((*pP2PReadCapStatus != NV0000_P2P_CAPS_STATUS_OK) && + (*pP2PWriteCapStatus != NV0000_P2P_CAPS_STATUS_OK)) + { + // return not supported if it does not support any operation + return NV_ERR_NOT_SUPPORTED; + } + + return NV_OK; } NV_STATUS @@ -568,6 +681,7 @@ p2pGetCapsStatus KernelNvlink *pKernelNvlink = NULL; OBJGPU *pGpu = NULL; NvU32 gpuInstance = 0; + NvBool bCommonSwitchFound = NV_FALSE; if ((pP2PWriteCapStatus == NULL) || (pP2PReadCapStatus == NULL) || @@ -625,7 +739,8 @@ p2pGetCapsStatus pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); if (pKernelNvlink != NULL && pKernelNvlink->discoveredLinks != 0 && (pSys->getProperty(pSys, PDB_PROP_SYS_NVSWITCH_IS_PRESENT) || - knvlinkIsNvswitchProxyPresent(pGpu, pKernelNvlink))) + knvlinkIsNvswitchProxyPresent(pGpu, pKernelNvlink) || + GPU_IS_NVSWITCH_DETECTED(pGpu))) { *pP2PReadCapStatus = NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED; *pP2PWriteCapStatus = NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED; @@ -650,18 +765,26 @@ p2pGetCapsStatus // // We can control P2P connectivity for PCI-E peers using regkeys, hence // if either read or write is supported, return success. See - // _p2pCapsCheckStatusOverridesForPcie for details. + // _kp2pCapsCheckStatusOverridesForPcie for details. // if (_kp2pCapsGetStatusOverPcie(gpuMask, pP2PWriteCapStatus, - pP2PReadCapStatus) == NV_OK) + pP2PReadCapStatus, &bCommonSwitchFound) == NV_OK) { if ((*pP2PWriteCapStatus == NV0000_P2P_CAPS_STATUS_OK) || (*pP2PReadCapStatus == NV0000_P2P_CAPS_STATUS_OK)) { - if (_kp2pCapsGetStatusOverPcieBar1(gpuMask) == NV_OK) + NvU8 bar1P2PWriteCapStatus = *pP2PWriteCapStatus; + NvU8 bar1P2PReadCapStatus = *pP2PReadCapStatus; + + *pConnectivity = P2P_CONNECTIVITY_PCIE; + + if (_kp2pCapsGetStatusOverPcieBar1(gpuMask, &bar1P2PWriteCapStatus, + &bar1P2PReadCapStatus, bCommonSwitchFound) == NV_OK) + { + *pP2PWriteCapStatus = bar1P2PWriteCapStatus; + *pP2PReadCapStatus = bar1P2PReadCapStatus; *pConnectivity = P2P_CONNECTIVITY_PCIE_BAR1; - else - *pConnectivity = P2P_CONNECTIVITY_PCIE; + } return NV_OK; } @@ -670,3 +793,300 @@ p2pGetCapsStatus return NV_OK; } +static NV_STATUS +_removeP2PPeerGpuCapsByGpuId +( + OBJGPU *pGpu, + NvU32 peerGpuId +) +{ + GPU_P2P_PEER_GPU_CAPS *pLocalPeerCaps = NULL; + + pLocalPeerCaps = gpuFindP2PPeerGpuCapsByGpuId(pGpu, peerGpuId); + NV_CHECK_OR_RETURN(LEVEL_WARNING, pLocalPeerCaps != NULL, NV_ERR_OBJECT_NOT_FOUND); + + // Swap the target element with the last element and remove the last. + // pLocalPeerCaps points to an item in the pGpu->P2PPeerGpuCaps array. + NV_ASSERT(pGpu->P2PPeerGpuCount != 0); + pGpu->P2PPeerGpuCount--; + + portMemMove(pLocalPeerCaps, + sizeof(GPU_P2P_PEER_GPU_CAPS), + &pGpu->P2PPeerGpuCaps[pGpu->P2PPeerGpuCount], + sizeof(GPU_P2P_PEER_GPU_CAPS)); + + return NV_OK; +} + +NV_STATUS +subdeviceCtrlCmdInternalSetP2pCaps_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PARAMS *pParams +) +{ + NV_STATUS status = NV_OK; + NvU32 i; + NvU32 failingIndex; + OBJGPU *pGpu = gpumgrGetGpuFromSubDeviceInst(pSubdevice->deviceInst, + pSubdevice->subDeviceInst); + + // TODO: GPUSWSEC-1433 remove this check to enable this control for baremetal + if (!IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + return NV_ERR_NOT_SUPPORTED; + + NV_CHECK_OR_RETURN(LEVEL_ERROR, + pParams->peerGpuCount <= NV_ARRAY_ELEMENTS32(pGpu->P2PPeerGpuCaps), + NV_ERR_INVALID_ARGUMENT); + + for (i = 0; i < pParams->peerGpuCount; i++) + { + NV2080_CTRL_INTERNAL_SET_P2P_CAPS_PEER_INFO *pParamsPeerInfo = &pParams->peerGpuInfos[i]; + GPU_P2P_PEER_GPU_CAPS *pLocalPeerCaps = NULL; + + // Try to find the existing entry + pLocalPeerCaps = gpuFindP2PPeerGpuCapsByGpuId(pGpu, pParamsPeerInfo->gpuId); + + // If no entry has been found, add a new one instead + if (pLocalPeerCaps == NULL) + { + NV_CHECK_OR_ELSE(LEVEL_ERROR, + pGpu->P2PPeerGpuCount < NV_ARRAY_ELEMENTS32(pGpu->P2PPeerGpuCaps), + status = NV_ERR_INSUFFICIENT_RESOURCES; goto fail); + + pLocalPeerCaps = &pGpu->P2PPeerGpuCaps[pGpu->P2PPeerGpuCount]; + pLocalPeerCaps->peerGpuId = pParamsPeerInfo->gpuId; + + pGpu->P2PPeerGpuCount++; + } + + pLocalPeerCaps->peerGpuInstance = pParamsPeerInfo->gpuInstance; + pLocalPeerCaps->p2pCaps = pParamsPeerInfo->p2pCaps; + pLocalPeerCaps->p2pOptimalReadCEs = pParamsPeerInfo->p2pOptimalReadCEs; + pLocalPeerCaps->p2pOptimalWriteCEs = pParamsPeerInfo->p2pOptimalWriteCEs; + pLocalPeerCaps->busPeerId = pParamsPeerInfo->busPeerId; + + portMemCopy(pLocalPeerCaps->p2pCapsStatus, + sizeof(pLocalPeerCaps->p2pCapsStatus), + pParamsPeerInfo->p2pCapsStatus, + sizeof(pParamsPeerInfo->p2pCapsStatus)); + } + + goto done; + +fail: + // Remove the successfully set caps + failingIndex = i; + for (i = 0; i < failingIndex; i++) + { + NV_STATUS ignoredStatus; + NV_CHECK_OK(ignoredStatus, LEVEL_ERROR, + _removeP2PPeerGpuCapsByGpuId(pGpu, pParams->peerGpuInfos[i].gpuId)); + } + +done: + return status; +} + +NV_STATUS +subdeviceCtrlCmdInternalRemoveP2pCaps_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS *pParams +) +{ + NV_STATUS status = NV_OK; + NvU32 i; + OBJGPU *pGpu = gpumgrGetGpuFromSubDeviceInst(pSubdevice->deviceInst, + pSubdevice->subDeviceInst); + + // TODO: GPUSWSEC-1433 remove this check to enable this control for baremetal + if (!IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + return NV_ERR_NOT_SUPPORTED; + + NV_CHECK_OR_RETURN(LEVEL_ERROR, + pParams->peerGpuIdCount <= NV_ARRAY_ELEMENTS32(pGpu->P2PPeerGpuCaps), + NV_ERR_INVALID_ARGUMENT); + + for (i = 0; i < pParams->peerGpuIdCount; i++) + { + // Capture only the first error here, as trying to remove all caps + // is the best effort here. + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_ERROR, + _removeP2PPeerGpuCapsByGpuId(pGpu, pParams->peerGpuIds[i])); + } + + return status; +} + +static NV_STATUS +subdeviceGetP2pCaps_VIRTUAL +( + OBJGPU *pGpu, + NV2080_CTRL_GET_P2P_CAPS_PARAMS *pParams +) +{ + NvU32 i; + NV_STATUS status = NV_OK; + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + RS_RES_CONTROL_PARAMS_INTERNAL *pControlParams = pCallContext->pControlParams; + NV2080_CTRL_GET_P2P_CAPS_PARAMS *pShimParams = + portMemAllocNonPaged(sizeof *pShimParams); + + NV_CHECK_OR_RETURN(LEVEL_INFO, pShimParams != NULL, NV_ERR_NO_MEMORY); + + portMemCopy(pShimParams, sizeof *pShimParams, pParams, sizeof *pParams); + + if (!pShimParams->bAllCaps) + { + // Must translate Guest GpuIds to Guest UUIDs + for (i = 0; i < pShimParams->peerGpuCount; i++) + { + NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO *pParamsPeerInfo = &pShimParams->peerGpuCaps[i]; + POBJGPU pRemoteGpu = gpumgrGetGpuFromId(pParamsPeerInfo->gpuId); + + NV_CHECK_OR_ELSE(LEVEL_INFO, pRemoteGpu != NULL, + status = NV_ERR_INVALID_ARGUMENT; goto done); + + portMemCopy(pParamsPeerInfo->gpuUuid, + sizeof(pParamsPeerInfo->gpuUuid), + pRemoteGpu->gpuUuid.uuid, + sizeof(pRemoteGpu->gpuUuid.uuid)); + } + } + + pShimParams->bUseUuid = 1; + + NV_RM_RPC_CONTROL(pGpu, + pControlParams->hClient, + pControlParams->hObject, + pControlParams->cmd, + pShimParams, + sizeof *pShimParams, + status); + if (status != NV_OK) + { + goto done; + } + + // If bAllCaps, transfer additional output gpuIds and peerGpuCount + if (pParams->bAllCaps) + { + pParams->peerGpuCount = pShimParams->peerGpuCount; + + for (i = 0; i < pParams->peerGpuCount; ++i) + { + // Use UUID to compute corresponding Guest GPU ID + OBJGPU *pRemoteGpu = gpumgrGetGpuFromUuid(pShimParams->peerGpuCaps[i].gpuUuid, + DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _TYPE, _SHA1) | + DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _FORMAT, _BINARY)); + + NV_CHECK_OR_ELSE(LEVEL_INFO, pRemoteGpu != NULL, + status = NV_ERR_GPU_UUID_NOT_FOUND; goto done); + + pParams->peerGpuCaps[i].gpuId = pRemoteGpu->gpuId; + } + } + + // Transfer output values from shimParams to user params. + for (i = 0; i < pParams->peerGpuCount; ++i) + { + pParams->peerGpuCaps[i].p2pCaps = pShimParams->peerGpuCaps[i].p2pCaps; + pParams->peerGpuCaps[i].p2pOptimalReadCEs = pShimParams->peerGpuCaps[i].p2pOptimalReadCEs; + pParams->peerGpuCaps[i].p2pOptimalWriteCEs = pShimParams->peerGpuCaps[i].p2pOptimalWriteCEs; + portMemCopy(pParams->peerGpuCaps[i].p2pCapsStatus, + sizeof(pParams->peerGpuCaps[i].p2pCapsStatus), + pShimParams->peerGpuCaps[i].p2pCapsStatus, + sizeof(pShimParams->peerGpuCaps[i].p2pCapsStatus)); + pParams->peerGpuCaps[i].busPeerId = pShimParams->peerGpuCaps[i].busPeerId; + } + +done: + portMemFree(pShimParams); + + return status; +} + +NV_STATUS +subdeviceCtrlCmdGetP2pCaps_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_GET_P2P_CAPS_PARAMS *pParams +) +{ + NvU32 i; + NvU32 gfid = GPU_GFID_PF; + OBJGPU *pGpu = gpumgrGetGpuFromSubDeviceInst(pSubdevice->deviceInst, + pSubdevice->subDeviceInst); + + // TODO: GPUSWSEC-1433 remove this check to enable this control for baremetal + if (!IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + return NV_ERR_NOT_SUPPORTED; + + NV_CHECK_OR_RETURN(LEVEL_ERROR, pGpu != NULL, NV_ERR_INVALID_STATE); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, vgpuGetCallingContextGfid(pGpu, &gfid)); + + NV_CHECK_OR_RETURN(LEVEL_ERROR, + (pParams->bAllCaps || + (pParams->peerGpuCount <= NV_ARRAY_ELEMENTS32(pGpu->P2PPeerGpuCaps))), + NV_ERR_INVALID_ARGUMENT); + + NV_CHECK_OR_RETURN(LEVEL_ERROR, (pParams->bUseUuid == NV_FALSE), NV_ERR_NOT_SUPPORTED); + + if (IS_VIRTUAL(pGpu)) + { + return subdeviceGetP2pCaps_VIRTUAL(pGpu, pParams); + } + + NV_CHECK_OR_RETURN(LEVEL_ERROR, RMCFG_FEATURE_PLATFORM_GSP, NV_ERR_NOT_SUPPORTED); + + if (pParams->bAllCaps) + { + pParams->peerGpuCount = pGpu->P2PPeerGpuCount; + + for (i = 0; i < pParams->peerGpuCount; i++) + { + pParams->peerGpuCaps[i].gpuId = pGpu->P2PPeerGpuCaps[i].peerGpuId; + } + } + + for (i = 0; i < pParams->peerGpuCount; i++) + { + NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO *pParamsPeerInfo = &pParams->peerGpuCaps[i]; + GPU_P2P_PEER_GPU_CAPS *pLocalPeerCaps = NULL; + + pLocalPeerCaps = gpuFindP2PPeerGpuCapsByGpuId(pGpu, pParamsPeerInfo->gpuId); + NV_CHECK_OR_RETURN(LEVEL_ERROR, pLocalPeerCaps != NULL, NV_ERR_OBJECT_NOT_FOUND); + + // + // TODO: Currently, vGPU-GSP Guest only supports NVLINK DIRECT so unset caps for other modes. + // May remove once vGPU adds support for other modes. + // + if (IS_GFID_VF(gfid) && + !REF_VAL(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED, pLocalPeerCaps->p2pCaps)) + { + pParamsPeerInfo->p2pCaps = 0; + pParamsPeerInfo->p2pOptimalReadCEs = 0; + pParamsPeerInfo->p2pOptimalWriteCEs = 0; + pParamsPeerInfo->busPeerId = NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER; + + portMemSet(pParamsPeerInfo->p2pCapsStatus, + NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED, + sizeof(pParamsPeerInfo->p2pCapsStatus)); + } + else + { + pParamsPeerInfo->p2pCaps = pLocalPeerCaps->p2pCaps; + pParamsPeerInfo->p2pOptimalReadCEs = pLocalPeerCaps->p2pOptimalReadCEs; + pParamsPeerInfo->p2pOptimalWriteCEs = pLocalPeerCaps->p2pOptimalWriteCEs; + pParamsPeerInfo->busPeerId = pLocalPeerCaps->busPeerId; + + portMemCopy(pParamsPeerInfo->p2pCapsStatus, + sizeof(pParamsPeerInfo->p2pCapsStatus), + pLocalPeerCaps->p2pCapsStatus, + sizeof(pLocalPeerCaps->p2pCapsStatus)); + } + } + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/platform/platform.c b/src/nvidia/src/kernel/platform/platform.c index f1e824b6b..f298dcf54 100644 --- a/src/nvidia/src/kernel/platform/platform.c +++ b/src/nvidia/src/kernel/platform/platform.c @@ -21,7 +21,7 @@ * DEALINGS IN THE SOFTWARE. */ -/***************************** HW State Rotuines ***************************\ +/***************************** HW State Routines ***************************\ * Platform object function definitions. * \***************************************************************************/ @@ -30,6 +30,7 @@ #include "core/system.h" #include "os/os.h" +#include "platform/nbsi/nbsi_read.h" #include "gpu/gpu.h" #include "gpu_mgr/gpu_mgr.h" @@ -38,19 +39,10 @@ //! OBJPFM's constructor NV_STATUS pfmConstruct_IMPL(OBJPFM *pPfm) { + initNbsiObject(&pPfm->nbsi); return NV_OK; } -void -pfmBlobDataDestroy_IMPL -( - OBJPFM *pPfm -) -{ - // if blob data cache is allocated, free the memory - portMemFree(pPfm->blobData.pEntry); -} - void pfmUpdateAcpiIdMapping_IMPL ( diff --git a/src/nvidia/src/kernel/power/gpu_boost_mgr.c b/src/nvidia/src/kernel/power/gpu_boost_mgr.c index d76959b63..14f222fee 100644 --- a/src/nvidia/src/kernel/power/gpu_boost_mgr.c +++ b/src/nvidia/src/kernel/power/gpu_boost_mgr.c @@ -38,6 +38,7 @@ #include "gpu/gsp/gsp_static_config.h" #include "vgpu/vgpu_events.h" #include "gpu/perf/kern_perf_gpuboostsync.h" +#include "nvdevid.h" /*-----------------------Static Private Method Prototypes---------------------*/ static NV_STATUS _gpuboostmgrApplyPolicyFilters(NV0000_SYNC_GPU_BOOST_GROUP_CONFIG *); diff --git a/src/nvidia/src/kernel/rmapi/alloc_free.c b/src/nvidia/src/kernel/rmapi/alloc_free.c index cc0d324ec..e0fb32169 100644 --- a/src/nvidia/src/kernel/rmapi/alloc_free.c +++ b/src/nvidia/src/kernel/rmapi/alloc_free.c @@ -32,6 +32,8 @@ #include "gpu/disp/disp_channel.h" #include "nvsecurityinfo.h" +#include "kernel/gpu/mig_mgr/kernel_mig_manager.h" + #include "gpu/device/device.h" #include "class/cl0005.h" // NV01_EVENT @@ -250,7 +252,7 @@ serverTopLock_Prologue if (access == LOCK_ACCESS_READ) flags |= RMAPI_LOCK_FLAGS_READ; - if ((status = rmApiLockAcquire(flags, RM_LOCK_MODULES_CLIENT)) != NV_OK) + if ((status = rmapiLockAcquire(flags, RM_LOCK_MODULES_CLIENT)) != NV_OK) { return status; } @@ -259,7 +261,7 @@ serverTopLock_Prologue } else { - if (!rmApiLockIsOwner()) + if (!rmapiLockIsOwner()) { NV_ASSERT(0); return NV_ERR_INVALID_LOCK_STATE; @@ -283,7 +285,7 @@ serverTopLock_Epilogue if (*pReleaseFlags & RM_LOCK_RELEASE_API_LOCK) { - rmApiLockRelease(); + rmapiLockRelease(); pLockInfo->state &= ~RM_LOCK_STATES_API_LOCK_ACQUIRED; *pReleaseFlags &= ~RM_LOCK_RELEASE_API_LOCK; } @@ -369,9 +371,21 @@ serverResLock_Prologue if (pGpuResource == NULL) { - NV_ASSERT(0); - status = NV_ERR_INVALID_OBJECT_PARENT; - goto done; + // + // If parent is not a GpuResource, we might still be a NV0080_DEVICE + // so check and handle that case before reporting an error.. + // + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + if (pCallContext != NULL && pCallContext->pResourceRef != NULL) + { + pGpuResource = dynamicCast(pCallContext->pResourceRef->pResource, GpuResource); + } + if (pGpuResource == NULL) + { + NV_ASSERT_FAILED("Attempting to lock per-GPU lock for a non-GpuResource"); + status = NV_ERR_INVALID_OBJECT_PARENT; + goto done; + } } pParentGpu = GPU_RES_GET_GPU(pGpuResource); @@ -973,8 +987,6 @@ rmapiFreeResourcePrologue NV_ASSERT_OR_RETURN(pResourceRef, NV_ERR_INVALID_OBJECT_HANDLE); - rmapiControlCacheFreeObject(pRmFreeParams->hClient, pRmFreeParams->hResource); - // // Use gpuGetByRef instead of GpuResource because gpuGetByRef will work even // if resource isn't a GpuResource (e.g.: Memory which can be allocated @@ -1070,7 +1082,7 @@ rmapiAllocWithSecInfo rmapiInitLockInfo(pRmApi, hClient, pLockInfo); // RS-TODO: Fix calls that use RMAPI_GPU_LOCK_INTERNAL without holding the API lock - if (pRmApi->bGpuLockInternal && !rmApiLockIsOwner()) + if (pRmApi->bGpuLockInternal && !rmapiLockIsOwner()) { NV_PRINTF(LEVEL_ERROR, "RMAPI_GPU_LOCK_INTERNAL alloc requested without holding the RMAPI lock\n"); pLockInfo->flags |= RM_LOCK_FLAGS_NO_API_LOCK; @@ -1210,6 +1222,16 @@ resservResourceFactory if (pResource == NULL) return NV_ERR_INSUFFICIENT_RESOURCES; + if (pResDesc->internalClassId == classId(Subdevice) || pResDesc->internalClassId == classId(Device)) + { + pGpu = GPU_RES_GET_GPU(dynamicCast(pDynamic, GpuResource)); + + if (pGpu && !IS_MIG_IN_USE(pGpu)) + { + rmapiControlCacheSetGpuInstForObject(pParams->hClient, pParams->hResource, pGpu->gpuInstance); + } + } + *ppResource = pResource; return status; @@ -1285,7 +1307,7 @@ rmapiFreeWithSecInfo rmapiInitLockInfo(pRmApi, hClient, &lockInfo); // RS-TODO: Fix calls that use RMAPI_GPU_LOCK_INTERNAL without holding the API lock - if (pRmApi->bGpuLockInternal && !rmApiLockIsOwner()) + if (pRmApi->bGpuLockInternal && !rmapiLockIsOwner()) { NV_PRINTF(LEVEL_ERROR, "RMAPI_GPU_LOCK_INTERNAL free requested without holding the RMAPI lock\n"); lockInfo.flags |= RM_LOCK_FLAGS_NO_API_LOCK; @@ -1299,6 +1321,8 @@ rmapiFreeWithSecInfo freeParams.freeFlags = flags; freeParams.pSecInfo = pSecInfo; + rmapiControlCacheFreeObjectEntry(hClient, hObject); + status = serverFreeResourceTree(&g_resServ, &freeParams); rmapiEpilogue(pRmApi, &rmApiContext); @@ -1367,6 +1391,7 @@ rmapiFreeClientListWithSecInfo NV_STATUS status; OBJSYS *pSys = SYS_GET_INSTANCE(); NvU32 lockState = 0; + NvU32 i; NV_PRINTF(LEVEL_INFO, "Nv01FreeClientList: numClients: %d\n", numClients); @@ -1379,6 +1404,9 @@ rmapiFreeClientListWithSecInfo if (pRmApi->bGpuLockInternal) lockState |= RM_LOCK_STATES_ALLOW_RECURSIVE_LOCKS; + for (i = 0; i < numClients; ++i) + rmapiControlCacheFreeClientEntry(phClientList[i]); + status = serverFreeClientList(&g_resServ, phClientList, numClients, lockState, pSecInfo); if (!pRmApi->bRmSemaInternal) diff --git a/src/nvidia/src/kernel/rmapi/client.c b/src/nvidia/src/kernel/rmapi/client.c index f17666a94..86ab377b6 100644 --- a/src/nvidia/src/kernel/rmapi/client.c +++ b/src/nvidia/src/kernel/rmapi/client.c @@ -34,8 +34,10 @@ #include "resource_desc.h" #include "gpu_mgr/gpu_mgr.h" #include "gpu/gpu.h" +#include "gpu/mmu/kern_gmmu.h" #include "gpu/bus/third_party_p2p.h" +#include "virtualization/hypervisor/hypervisor.h" UserInfoList g_userInfoList; RmClientList g_clientListBehindGpusLock; // RS-TODO remove this WAR @@ -59,13 +61,40 @@ rmclientConstruct_IMPL RsClient *pRsClient = staticCast(pClient, RsClient); NvBool bReleaseLock = NV_FALSE; API_SECURITY_INFO *pSecInfo = pParams->pSecInfo; + OBJGPU *pGpu = NULL; + + if (RMCFG_FEATURE_PLATFORM_GSP) + { + pGpu = gpumgrGetSomeGpu(); + + if (pGpu == NULL) + { + NV_PRINTF(LEVEL_ERROR, "GPU is not found\n"); + return NV_ERR_INVALID_STATE; + } + } pClient->bIsRootNonPriv = (pParams->externalClassId == NV01_ROOT_NON_PRIV); - pClient->ProcID = osGetCurrentProcess(); pClient->pUserInfo = NULL; pClient->pSecurityToken = NULL; pClient->pOSInfo = pSecInfo->clientOSInfo; + // TODO: Revisit in M2, see GPUSWSEC-1176 + if (RMCFG_FEATURE_PLATFORM_GSP && IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + { + if (pSecInfo->pProcessToken != NULL && ((NvU64) pSecInfo->pProcessToken) < VMMU_MAX_GFID) + { + // Trunc to NvU32 to fit ProcID (VMMU_MAX_GFID << MAX_INT) + pClient->ProcID = (NvU32)((NvU64)pSecInfo->pProcessToken); + + NV_PRINTF(LEVEL_INFO, "Client allocation with GFID = %u\n", (NvU32)((NvU64)pSecInfo->pProcessToken)); + } + } + else + { + pClient->ProcID = osGetCurrentProcess(); + } + pClient->cachedPrivilege = pSecInfo->privLevel; // Set user-friendly client name from current process @@ -77,6 +106,29 @@ rmclientConstruct_IMPL NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE; } + // + // Enabling this on MODS to avoid clash of client handles. This path gets executed on both + // guest & host RM for MODs platform, pGPU handle isnt available here to check for IS_VIRTUAL. + // Later code paths will override this for guest RM. + // This change affects non-SRIOV case as well, there is no good way to detect SRIOV without pGPU. + // + if (hypervisorIsVgxHyper() || NV_IS_MODS) + { + // + // Set RM allocated resource handle range for host RM. This minimize clash of guest RM handles with host RM + // during VM migration. + // + status = clientSetHandleGenerator(pRsClient, + (RS_UNIQUE_HANDLE_BASE + RS_UNIQUE_HANDLE_RANGE/2), + RS_UNIQUE_HANDLE_RANGE/2); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_WARNING, + "NVRM_RPC: Failed to set host client resource handle range %x\n", status); + return status; + } + } + // Prevent kernel clients from requesting handles in the FW handle generator range status = clientSetRestrictedRange(pRsClient, RS_FW_UNIQUE_HANDLE_BASE, RS_UNIQUE_HANDLE_RANGE); @@ -107,27 +159,32 @@ rmclientConstruct_IMPL if (pSys->getProperty(pSys, PDB_PROP_SYS_VALIDATE_CLIENT_HANDLE) && ((pParams->pSecInfo->privLevel < RS_PRIV_LEVEL_KERNEL) || pClient->bIsRootNonPriv)) { - PSECURITY_TOKEN pSecurityToken; + PSECURITY_TOKEN pSecurityToken = (pClient->bIsClientVirtualMode ? + pSecInfo->pProcessToken : osGetSecurityToken()); PUID_TOKEN pUidToken = osGetCurrentUidToken(); UserInfo *pUserInfo = NULL; - pSecurityToken = (pClient->bIsClientVirtualMode ? - pSecInfo->pProcessToken : osGetSecurityToken()); - - // pUserInfo takes ownership of pUidToken upon successful registration - status = _registerUserInfo(&pUidToken, &pUserInfo); - - if (status == NV_OK) + if (RMCFG_FEATURE_PLATFORM_GSP && IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) { - pClient->pUserInfo = pUserInfo; pClient->pSecurityToken = pSecurityToken; } else { - portMemFree(pUidToken); + // pUserInfo takes ownership of pUidToken upon successful registration + status = _registerUserInfo(&pUidToken, &pUserInfo); - if (pSecurityToken != NULL && !pClient->bIsClientVirtualMode) - portMemFree(pSecurityToken); + if (status == NV_OK) + { + pClient->pUserInfo = pUserInfo; + pClient->pSecurityToken = pSecurityToken; + } + else + { + portMemFree(pUidToken); + + if (pSecurityToken != NULL && !pClient->bIsClientVirtualMode) + portMemFree(pSecurityToken); + } } } @@ -168,8 +225,6 @@ rmclientDestruct_IMPL // Free any association of the client with existing third-party p2p object CliUnregisterFromThirdPartyP2P(pClient); - rmapiControlCacheFreeClient(hClient); - // // Free all of the devices of the client (do it in reverse order to // facilitate tear down of things like ctxdmas, etc) diff --git a/src/nvidia/src/kernel/rmapi/client_resource.c b/src/nvidia/src/kernel/rmapi/client_resource.c index f74a3bee2..1a4b819f7 100644 --- a/src/nvidia/src/kernel/rmapi/client_resource.c +++ b/src/nvidia/src/kernel/rmapi/client_resource.c @@ -1,3 +1,4 @@ + /* * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT @@ -28,20 +29,27 @@ #include "rmapi/client_resource.h" #include "rmapi/param_copy.h" #include "rmapi/rs_utils.h" +#include "rmapi/rmapi.h" #include "gpu/gpu.h" #include "gpu/device/device.h" +#include "gpu/gpu_uuid.h" #include "gpu_mgr/gpu_mgr.h" #include "resserv/rs_client.h" #include "resserv/rs_server.h" #include "resserv/rs_access_map.h" #include "nvBldVer.h" #include "nvVer.h" +#include "nvpcf.h" #include "mem_mgr/mem.h" #include "nvsecurityinfo.h" #include "kernel/gpu/rc/kernel_rc.h" #include "resource_desc.h" #include "mem_mgr/fla_mem.h" + +#include "vgpu/vgpu_version.h" +#include "virtualization/kernel_vgpu_mgr.h" + #include "platform/chipset/chipset_info.h" #include "platform/chipset/chipset.h" #include "platform/cpu.h" @@ -50,7 +58,10 @@ #include "platform/acpi_common.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" #include "vgpu/rpc.h" +#include "jt.h" +#include "nvop.h" #include "diagnostics/gpu_acct.h" +#include "gpu/external_device/gsync.h" #include "mem_mgr/virt_mem_mgr.h" #include "diagnostics/journal.h" #include "ctrl/ctrl0000/ctrl0000nvd.h" @@ -300,7 +311,7 @@ CliGetSystemP2pCaps NV_STATUS rmStatus = NV_OK; P2P_CONNECTIVITY connectivity; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); if ((gpuCount == 0) || (gpuCount > NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS)) { @@ -394,8 +405,8 @@ CliGetSystemP2pCaps p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_ATOMICS] = NV0000_P2P_CAPS_STATUS_OK; } - // Get the optimal CEs for P2P read/write for 2 gpu masks only - if (gpuCount == 2) + // Get the optimal CEs for P2P read/write for 1 or 2 gpu masks only + if (gpuCount <= 2) { knvlinkGetP2POptimalCEs_HAL(pGpuLocal, pLocalKernelNvlink, gpuMask, NULL, NULL, @@ -534,6 +545,160 @@ done: return rmStatus; } +// static functions used by NVPCF controls +static void +_configCalculateSizes +( + const char *pFormat, + NvU32 *pPackedSize, + NvU32 *pUnpackedSize +) +{ + NvU32 unpkdSize = 0; + NvU32 pkdSize = 0; + NvU32 count; + char fmt; + + while ((fmt = *pFormat++)) + { + count = 0; + while ((fmt >= '0') && (fmt <= '9')) + { + count *= 10; + count += fmt - '0'; + fmt = *pFormat++; + } + if (count == 0) + count = 1; + + switch (fmt) + { + case 'b': + pkdSize += count * 1; + unpkdSize += count * sizeof(NvU32); + break; + + case 's': // signed byte + pkdSize += count * 1; + unpkdSize += count * sizeof(NvU32); + break; + + case 'w': + pkdSize += count * 2; + unpkdSize += count * sizeof(NvU32); + break; + + case 'd': + pkdSize += count * 4; + unpkdSize += count * sizeof(NvU32); + break; + } + } + + if (pPackedSize != NULL) + *pPackedSize = pkdSize; + + if (pUnpackedSize != NULL) + *pUnpackedSize = unpkdSize; +} + + +static NV_STATUS +_configUnpackStructure +( + const char *pFormat, + const NvU8 *pPackedData, + NvU32 *pUnpackedData, + NvU32 *pUnpackedSize, + NvU32 *pFieldsCount +) +{ + NvU32 unpkdSize = 0; + NvU32 fields = 0; + NvU32 count; + NvU32 data; + char fmt; + + while ((fmt = *pFormat++)) + { + count = 0; + while ((fmt >= '0') && (fmt <= '9')) + { + count *= 10; + count += fmt - '0'; + fmt = *pFormat++; + } + if (count == 0) + count = 1; + + while (count--) + { + switch (fmt) + { + case 'b': + data = *pPackedData++; + unpkdSize += 1; + break; + + case 's': // signed byte + data = *pPackedData++; + if (data & 0x80) + data |= ~0xff; + unpkdSize += 1; + break; + + case 'w': + data = *pPackedData++; + data |= *pPackedData++ << 8; + unpkdSize += 2; + break; + + case 'd': + data = *pPackedData++; + data |= *pPackedData++ << 8; + data |= *pPackedData++ << 16; + data |= *pPackedData++ << 24; + unpkdSize += 4; + break; + + default: + return NV_ERR_GENERIC; + } + *pUnpackedData++ = data; + fields++; + } + } + + if (pUnpackedSize != NULL) + *pUnpackedSize = unpkdSize; + + if (pFieldsCount != NULL) + *pFieldsCount = fields; + + return NV_OK; +} + +static NV_STATUS +configReadStructure + ( + NvU8 *pData, + void *pStructure, + NvU32 offset, + const char *pFormat + ) + { + NvU32 packed_size; + NvU8 *pPacked_data; + NvU32 unpacked_bytes; + + // calculate the size of the data as indicated by its packed format. + _configCalculateSizes(pFormat, &packed_size, &unpacked_bytes); + pPacked_data = &pData[offset]; + + return _configUnpackStructure(pFormat, pPacked_data, pStructure, + &unpacked_bytes, NULL); +} + // **************************************************************************** // Other functions // **************************************************************************** @@ -557,7 +722,7 @@ cliresCtrlCmdSystemGetFeatures_IMPL NV_ASSERT_OR_RETURN(pSys != NULL, NV_ERR_INVALID_STATE); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); if (pSys->getProperty(pSys, PDB_PROP_SYS_IS_UEFI)) { @@ -591,7 +756,7 @@ cliresCtrlCmdSystemGetBuildVersionV2_IMPL NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS *pParams ) { - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); ct_assert(sizeof(NV_VERSION_STRING) <= sizeof(pParams->driverVersionBuffer)); ct_assert(sizeof(NV_BUILD_BRANCH_VERSION) <= sizeof(pParams->versionBuffer)); @@ -610,6 +775,168 @@ cliresCtrlCmdSystemGetBuildVersionV2_IMPL return NV_OK; } +/*! + * @brief Allows clients to execute ACPI methods for various purpose + * + * @return if the client request support: + * NV_OK if the ACPI method is executed successfully + * NV_ERR_INVALID_ARGUMENT if the arguments are not proper + * NV_ERR_BUFFER_TOO_SMALL if the output buffer is smaller than expected + */ +NV_STATUS +cliresCtrlCmdSystemExecuteAcpiMethod_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS *pAcpiMethodParams +) +{ + OBJGPU *pGpu = NULL; + NvU32 method = (NvU32) pAcpiMethodParams->method; + NvU32 outStatus = 0; + NvU32 inOutDataSize; + NvU16 inDataSize; + NvU16 outDataSize; + NvBool bDoCopyOut = NV_FALSE; + void* pInOutData = NULL; + NV_STATUS status = NV_OK; + OBJOS *pOS = NULL; + + pGpu = gpumgrGetSomeGpu(); + if (pGpu == NULL) + { + return NV_ERR_INVALID_REQUEST; + } + pOS = GPU_GET_OS(pGpu); + + inDataSize = pAcpiMethodParams->inDataSize; + outDataSize = pAcpiMethodParams->outDataSize; + inOutDataSize = (NvU32) NV_MAX(inDataSize, outDataSize); + + // Verify size + if ((outDataSize == 0) || + (pAcpiMethodParams->inData == NvP64_NULL) || + (pAcpiMethodParams->outData == NvP64_NULL)) + { + + NV_PRINTF(LEVEL_WARNING, + "ERROR: NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD: Parameter validation failed: outDataSize=%d method = %ud\n", + (NvU32)outDataSize, method); + + return NV_ERR_INVALID_ARGUMENT; + } + + // Allocate memory for the combined in/out buffer + pInOutData = portMemAllocNonPaged(inOutDataSize); + if (pInOutData == NULL) + { + status = NV_ERR_NO_MEMORY; + NV_PRINTF(LEVEL_WARNING, + "ERROR: NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD: mem alloc failed\n"); + goto done; + } + + if (inDataSize) + { + portMemCopy(pInOutData, inDataSize, NvP64_VALUE(pAcpiMethodParams->inData), inDataSize); + } + + // jump to the method to be executed + switch (method) + { + case NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSCAPS: + { + outStatus = pOS->osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_NVOP, + NVOP_FUNC_OPTIMUSCAPS, + (NvU32*) pInOutData, + &outDataSize); + break; + } + case NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_NVOP_OPTIMUSFLAG: + { + outStatus = pOS->osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_NVOP, + NVOP_FUNC_OPTIMUSFLAG, + (NvU32*) pInOutData, + (NvU16*) &outDataSize); + break; + } + case NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_CAPS: + { + outStatus = pOS->osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_JT, + JT_FUNC_CAPS, + (NvU32*) pInOutData, + (NvU16*) &outDataSize); + break; + } + case NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DSM_JT_PLATPOLICY: + { + outStatus = pOS->osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_JT, + JT_FUNC_PLATPOLICY, + (NvU32*) pInOutData, + (NvU16*) &outDataSize); + break; + } + default: + { + NV_PRINTF(LEVEL_WARNING, + "ERROR: NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD: Unrecognized Api Code: 0x%x\n", + method); + + status = NV_ERR_INVALID_ARGUMENT; + goto done; + } + } + + if (outStatus != NV_OK) + { + NV_PRINTF(LEVEL_INFO, + "ERROR: NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD: Execution failed for method: 0x%x, status=0x%x\n", + method, outStatus); + + // if it was a command we tried to return the real status. + if (status == NV_OK) + { + status = outStatus; + } + + pAcpiMethodParams->outStatus = outStatus; + goto done; + } + + // NOTE: 'outDataSize' may have changed above. + if (outDataSize > pAcpiMethodParams->outDataSize) + { + NV_PRINTF(LEVEL_WARNING, + "ERROR: NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD: output buffer is smaller then expected!\n"); + + // pAcpiMethodParams->outStatus = outStatus; //XXX64 check + // status = outStatus; //XXX64 check + status = NV_ERR_BUFFER_TOO_SMALL; + goto done; + } + + // all ok - so copy 'outdata' back to client + bDoCopyOut = NV_TRUE; + +done: + + // pass data out to client's output buffer + if (bDoCopyOut) + { + pAcpiMethodParams->outDataSize = outDataSize; + + portMemCopy(NvP64_VALUE(pAcpiMethodParams->outData), outDataSize, pInOutData, outDataSize); + } + + // release client's input buffer + portMemFree(pInOutData); + + return status; +} + // // cliresCtrlCmdSystemGetCpuInfo // @@ -626,7 +953,7 @@ cliresCtrlCmdSystemGetCpuInfo_IMPL { OBJSYS *pSys = SYS_GET_INSTANCE(); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); pCpuInfoParams->type = pSys->cpuInfo.type; pCpuInfoParams->capabilities = pSys->cpuInfo.caps; @@ -640,6 +967,7 @@ cliresCtrlCmdSystemGetCpuInfo_IMPL pCpuInfoParams->family = pSys->cpuInfo.family; pCpuInfoParams->model = pSys->cpuInfo.model; pCpuInfoParams->stepping = pSys->cpuInfo.stepping; + pCpuInfoParams->bSEVEnabled = (sysGetStaticConfig(pSys))->bOsSevEnabled; portMemCopy(pCpuInfoParams->name, sizeof (pCpuInfoParams->name), pSys->cpuInfo.name, sizeof (pCpuInfoParams->name)); @@ -664,7 +992,7 @@ cliresCtrlCmdSystemGetChipsetInfo_IMPL OBJSYS *pSys = SYS_GET_INSTANCE(); OBJCL *pCl = SYS_GET_CL(pSys); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); pChipsetInfo->flags = 0; @@ -737,7 +1065,7 @@ cliresCtrlCmdSystemSetMemorySize_IMPL OBJSYS *pSys = SYS_GET_INSTANCE(); OBJOS *pOS = SYS_GET_OS(pSys); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); pOS->SystemMemorySize = pParams->memorySize; @@ -793,7 +1121,7 @@ cliresCtrlCmdSystemGetClassList_IMPL { NV_STATUS status; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); status = classGetSystemClasses(pParams); @@ -860,7 +1188,7 @@ cliresCtrlCmdSystemGetPlatformType_IMPL OBJSYS *pSys = SYS_GET_INSTANCE(); OBJPFM *pPfm = SYS_GET_PFM(pSys); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); if (pPfm->getProperty(pPfm, PDB_PROP_PFM_IS_TOSHIBA_MOBILE)) { @@ -956,7 +1284,7 @@ cliresCtrlCmdGpuGetAttachedIds_IMPL NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS *pGpuAttachedIds ) { - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); return gpumgrGetAttachedGpuIds(pGpuAttachedIds); } @@ -974,7 +1302,7 @@ cliresCtrlCmdGpuGetIdInfo_IMPL NV0000_CTRL_GPU_GET_ID_INFO_PARAMS *pGpuIdInfoParams ) { - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); return gpumgrGetGpuIdInfo(pGpuIdInfoParams); } @@ -986,7 +1314,7 @@ cliresCtrlCmdGpuGetIdInfoV2_IMPL NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS *pGpuIdInfoParams ) { - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); return gpumgrGetGpuIdInfoV2(pGpuIdInfoParams); } @@ -1005,7 +1333,7 @@ cliresCtrlCmdGpuGetInitStatus_IMPL NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS *pGpuInitStatusParams ) { - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); return gpumgrGetGpuInitStatus(pGpuInitStatusParams); } @@ -1024,7 +1352,7 @@ cliresCtrlCmdGpuGetDeviceIds_IMPL NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS *pDeviceIdsParams ) { - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); pDeviceIdsParams->deviceIds = gpumgrGetDeviceInstanceMask(); @@ -1048,7 +1376,7 @@ cliresCtrlCmdGpuGetPciInfo_IMPL NV_STATUS status; NvU64 gpuDomainBusDevice; - NV_ASSERT(rmApiLockIsOwner()); + NV_ASSERT(rmapiLockIsOwner()); status = gpumgrGetProbedGpuDomainBusDevice(pPciInfoParams->gpuId, &gpuDomainBusDevice); if (status != NV_OK) @@ -1075,7 +1403,7 @@ cliresCtrlCmdGpuGetProbedIds_IMPL NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS *pGpuProbedIds ) { - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); return gpumgrGetProbedGpuIds(pGpuProbedIds); } @@ -1098,7 +1426,7 @@ cliresCtrlCmdGpuAttachIds_IMPL NvU32 i, j; NV_STATUS status = NV_OK; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); if (pGpuAttachIds->gpuIds[0] == NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS) { @@ -1162,7 +1490,7 @@ cliresCtrlCmdGpuDetachIds_IMPL NvU32 i, j; NV_STATUS status = NV_OK; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); if (pGpuDetachIds->gpuIds[0] == NV0000_CTRL_GPU_DETACH_ALL_ATTACHED_IDS) { @@ -1244,14 +1572,7 @@ cliresCtrlCmdGsyncGetAttachedIds_IMPL NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS *pGsyncAttachedIds ) { - NvU32 i; - - for (i = 0; i < NV_ARRAY_ELEMENTS32(pGsyncAttachedIds->gsyncIds); i++) - { - pGsyncAttachedIds->gsyncIds[i] = NV0000_CTRL_GSYNC_INVALID_ID; - } - - return NV_OK; + return gsyncGetAttachedIds(pGsyncAttachedIds); } NV_STATUS @@ -1261,7 +1582,7 @@ cliresCtrlCmdGsyncGetIdInfo_IMPL NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS *pGsyncIdInfoParams ) { - return NV_ERR_NOT_SUPPORTED; + return gsyncGetIdInfo(pGsyncIdInfoParams); } NV_STATUS @@ -1295,11 +1616,14 @@ cliresCtrlCmdGpuAcctGetProcAccountingInfo_IMPL NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS *pAcctInfoParams ) { - OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJSYS *pSys = SYS_GET_INSTANCE(); GpuAccounting *pGpuAcct = SYS_GET_GPUACCT(pSys); - OBJGPU *pGpu; + OBJGPU *pGpu; + NV_STATUS status = NV_OK; + CALL_CONTEXT *pCallContext; + RmCtrlParams *pRmCtrlParams; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); pGpu = gpumgrGetGpuFromId(pAcctInfoParams->gpuId); if (pGpu == NULL) @@ -1307,6 +1631,36 @@ cliresCtrlCmdGpuAcctGetProcAccountingInfo_IMPL return NV_ERR_INVALID_ARGUMENT; } + if (IS_VIRTUAL(pGpu)) + { + pCallContext = resservGetTlsCallContext(); + pRmCtrlParams = pCallContext->pControlParams->pLegacyParams; + + NV_RM_RPC_GET_ENGINE_UTILIZATION(pGpu, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->cmd, + pAcctInfoParams, + sizeof(NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS), + status); + return status; + } + else if (IS_GSP_CLIENT(pGpu) && IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && + (pAcctInfoParams->subPid != 0)) + { + pCallContext = resservGetTlsCallContext(); + pRmCtrlParams = pCallContext->pControlParams; + + NV_RM_RPC_CONTROL(pGpu, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->cmd, + pRmCtrlParams->pParams, + pRmCtrlParams->paramsSize, + status); + return status; + } + return gpuacctGetProcAcctInfo(pGpuAcct, pAcctInfoParams); } @@ -1317,10 +1671,12 @@ cliresCtrlCmdGpuAcctSetAccountingState_IMPL NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS *pParams ) { - OBJGPU *pGpu = NULL; - NV_STATUS status = NV_OK; + OBJGPU *pGpu = NULL; + NV_STATUS status = NV_OK; + CALL_CONTEXT *pCallContext; + RmCtrlParams *pRmCtrlParams; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); pGpu = gpumgrGetGpuFromId(pParams->gpuId); if (pGpu == NULL) @@ -1331,10 +1687,24 @@ cliresCtrlCmdGpuAcctSetAccountingState_IMPL OBJSYS *pSys = SYS_GET_INSTANCE(); GpuAccounting *pGpuAcct = SYS_GET_GPUACCT(pSys); - if (IS_GSP_CLIENT(pGpu)) + if (IS_VIRTUAL(pGpu)) { - CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); - RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; + pCallContext = resservGetTlsCallContext(); + pRmCtrlParams = pCallContext->pControlParams->pLegacyParams; + + NV_RM_RPC_GET_ENGINE_UTILIZATION(pGpu, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->cmd, + pParams, + sizeof(NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS), + status); + return status; + } + else if (IS_GSP_CLIENT(pGpu)) + { + pCallContext = resservGetTlsCallContext(); + pRmCtrlParams = pCallContext->pControlParams; NV_RM_RPC_CONTROL(pGpu, pRmCtrlParams->hClient, @@ -1372,11 +1742,14 @@ cliresCtrlCmdGpuAcctClearAccountingData_IMPL NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS *pParams ) { - OBJSYS *pSys = SYS_GET_INSTANCE(); - GpuAccounting *pGpuAcct = SYS_GET_GPUACCT(pSys); - OBJGPU *pGpu = NULL; + OBJSYS *pSys = SYS_GET_INSTANCE(); + GpuAccounting *pGpuAcct = SYS_GET_GPUACCT(pSys); + OBJGPU *pGpu = NULL; + CALL_CONTEXT *pCallContext; + RmCtrlParams *pRmCtrlParams; + NV_STATUS status = NV_OK; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); pGpu = gpumgrGetGpuFromId(pParams->gpuId); if (pGpu == NULL) @@ -1384,6 +1757,35 @@ cliresCtrlCmdGpuAcctClearAccountingData_IMPL return NV_ERR_INVALID_ARGUMENT; } + if (IS_VIRTUAL(pGpu)) + { + pCallContext = resservGetTlsCallContext(); + pRmCtrlParams = pCallContext->pControlParams->pLegacyParams; + + NV_RM_RPC_GET_ENGINE_UTILIZATION(pGpu, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->cmd, + &pParams, + sizeof(NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS), + status); + return status; + } + else if (IS_GSP_CLIENT(pGpu) && IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && (pParams->pid != 0)) + { + pCallContext = resservGetTlsCallContext(); + pRmCtrlParams = pCallContext->pControlParams; + + NV_RM_RPC_CONTROL(pGpu, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->cmd, + pRmCtrlParams->pParams, + pRmCtrlParams->paramsSize, + status); + return status; + } + return gpuacctClearAccountingData(pGpuAcct, pGpu->gpuInstance, pParams); } @@ -1394,11 +1796,14 @@ cliresCtrlCmdGpuAcctGetAccountingState_IMPL NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS *pParams ) { - OBJSYS *pSys = SYS_GET_INSTANCE(); - GpuAccounting *pGpuAcct = SYS_GET_GPUACCT(pSys); - OBJGPU *pGpu = NULL; + OBJSYS *pSys = SYS_GET_INSTANCE(); + GpuAccounting *pGpuAcct = SYS_GET_GPUACCT(pSys); + OBJGPU *pGpu = NULL; + CALL_CONTEXT *pCallContext; + RmCtrlParams *pRmCtrlParams; + NV_STATUS status = NV_OK; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); pGpu = gpumgrGetGpuFromId(pParams->gpuId); if (pGpu == NULL) @@ -1406,6 +1811,35 @@ cliresCtrlCmdGpuAcctGetAccountingState_IMPL return NV_ERR_INVALID_ARGUMENT; } + if (IS_VIRTUAL(pGpu)) + { + pCallContext = resservGetTlsCallContext(); + pRmCtrlParams = pCallContext->pControlParams->pLegacyParams; + + NV_RM_RPC_GET_ENGINE_UTILIZATION(pGpu, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->cmd, + pParams, + sizeof(NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS), + status); + return status; + } + else if (IS_GSP_CLIENT(pGpu) && IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && (pParams->pid != 0)) + { + pCallContext = resservGetTlsCallContext(); + pRmCtrlParams = pCallContext->pControlParams; + + NV_RM_RPC_CONTROL(pGpu, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->cmd, + pRmCtrlParams->pParams, + pRmCtrlParams->paramsSize, + status); + return status; + } + return gpuacctGetAccountingMode(pGpuAcct, pGpu->gpuInstance, pParams); } @@ -1416,11 +1850,14 @@ cliresCtrlCmdGpuAcctGetAccountingPids_IMPL NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS *pAcctPidsParams ) { - OBJSYS *pSys = SYS_GET_INSTANCE(); - GpuAccounting *pGpuAcct = SYS_GET_GPUACCT(pSys); - OBJGPU *pGpu; + OBJSYS *pSys = SYS_GET_INSTANCE(); + GpuAccounting *pGpuAcct = SYS_GET_GPUACCT(pSys); + OBJGPU *pGpu; + CALL_CONTEXT *pCallContext; + RmCtrlParams *pRmCtrlParams; + NV_STATUS status = NV_OK; - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); pGpu = gpumgrGetGpuFromId(pAcctPidsParams->gpuId); if (pGpu == NULL) @@ -1428,10 +1865,281 @@ cliresCtrlCmdGpuAcctGetAccountingPids_IMPL return NV_ERR_INVALID_ARGUMENT; } + if (IS_VIRTUAL(pGpu)) + { + pCallContext = resservGetTlsCallContext(); + pRmCtrlParams = pCallContext->pControlParams->pLegacyParams; + + NV_RM_RPC_GET_ENGINE_UTILIZATION(pGpu, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->cmd, + pAcctPidsParams, + sizeof(NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS), + status); + return status; + } + else if (IS_GSP_CLIENT(pGpu) && IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && + (pAcctPidsParams->pid != 0)) + { + pCallContext = resservGetTlsCallContext(); + pRmCtrlParams = pCallContext->pControlParams; + + NV_RM_RPC_CONTROL(pGpu, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->cmd, + pRmCtrlParams->pParams, + pRmCtrlParams->paramsSize, + status); + return status; + } + return gpuacctGetAcctPids(pGpuAcct, pAcctPidsParams); } +NV_STATUS +cliresCtrlCmdSystemNVPCFGetPowerModeInfo_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS *pParams +) +{ + OBJSYS *pSys = NULL; + OBJOS *pOS = NULL; + NvU32 rc = NV_OK; + OBJGPU *pGpu = NULL; + NV_STATUS status = NV_OK; + NvU16 dsmDataSize; + ACPI_DSM_FUNCTION acpiDsmFunction = ACPI_DSM_FUNCTION_NVPCF_2X; + NvU32 acpiDsmSubFunction = NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED; + + if (pParams == NULL) + { + return NV_ERR_INVALID_REQUEST; + } + + pSys = SYS_GET_INSTANCE(); + if (pSys == NULL) + { + NV_ASSERT(pSys); + return NV_ERR_INVALID_REQUEST; + } + + pOS = SYS_GET_OS(pSys); + if (pOS == NULL) + { + NV_ASSERT(pOS); + return NV_ERR_INVALID_REQUEST; + } + + pGpu = gpumgrGetGpuFromId(pParams->gpuId); + + if (pGpu == NULL) + { + NV_ASSERT(pGpu); + return NV_ERR_INVALID_REQUEST; + } + + switch (pParams->subFunc) + { + case NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED_CASE: + acpiDsmFunction = ACPI_DSM_FUNCTION_NVPCF; + acpiDsmSubFunction = NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED; + /* fallthrough */ + case NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED_CASE: + { + NvU32 supportedFuncs; + dsmDataSize = sizeof(supportedFuncs); + + if ((rc = pOS->osCallACPI_DSM(pGpu, + acpiDsmFunction, + acpiDsmSubFunction, + &supportedFuncs, + &dsmDataSize)) != NV_OK) + { + NV_PRINTF(LEVEL_WARNING, + "Unable to retrieve NVPCF supported functions. Possibly not supported by SBIOS " + "rc = %x\n", rc); + status = NV_ERR_NOT_SUPPORTED; + } + else + { + if ((FLD_TEST_DRF(PCF0100, _CTRL_CONFIG_DSM, + _FUNC_GET_SUPPORTED_IS_SUPPORTED, _NO, supportedFuncs)) || + (dsmDataSize != sizeof(supportedFuncs))) + { + NV_PRINTF(LEVEL_WARNING, + " NVPCF FUNC_GET_SUPPORTED is not supported" + "rc = %x\n", rc); + status = NV_ERR_NOT_SUPPORTED; + } + } + break; + + } + + case NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_CASE: + { + CONTROLLER_DYNAMIC_TABLE_1X_ACPI dynamicTable_1x; + portMemSet(&dynamicTable_1x, 0, sizeof(dynamicTable_1x)); + + dynamicTable_1x.header.version = NVPCF0100_CTRL_DYNAMIC_TABLE_1X_VERSION; + dynamicTable_1x.header.size = sizeof(NVPCF0100_CTRL_DYNAMIC_TABLE_1X_HEADER); + dynamicTable_1x.header.entryCnt = 2; + dynamicTable_1x.header.reserved = 0; + + dynamicTable_1x.entries[0] = NVPCF0100_CTRL_DYNAMIC_TABLE_1X_INPUT_CMD_GET_TPP; + dsmDataSize = sizeof(dynamicTable_1x); + + if ((rc = pOS->osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_NVPCF, + NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS, + (NvU32*)(&dynamicTable_1x), + &dsmDataSize)) != NV_OK) + { + NV_PRINTF(LEVEL_WARNING, + "Unable to retrieve NVPCF dynamic data. Possibly not supported by SBIOS " + "rc = %x\n", rc); + status = NV_ERR_NOT_SUPPORTED; + } + else + { + // bit [0:15] is TPP, bit [16:31] is rated TGP + pParams->tpp = dynamicTable_1x.entries[1] & 0xFFFF; + pParams->ratedTgp = (dynamicTable_1x.entries[1] & 0xFFFF0000) >> 16; + } + + break; + } + + case NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_CASE: + { + NvU8 *pData = NULL; + DYNAMIC_PARAMS_HEADER_2X_PACKED header = {0}; + DYNAMIC_PARAMS_COMMON_2X_PACKED common = {0}; + DYNAMIC_PARAMS_ENTRY_2X_PACKED entries[NVPCF_DYNAMIC_PARAMS_2X_ENTRY_MAX]= {0}; + + NvU16 dataSize = sizeof(header) + sizeof(common) + sizeof(entries); + pData = portMemAllocNonPaged(dataSize); + + portMemSet(&header, 0, sizeof(header)); + + header.version = NVPCF_DYNAMIC_PARAMS_20_VERSION; + header.headerSize = NVPCF_DYNAMIC_PARAMS_2X_HEADER_SIZE_05; + header.commonSize = NVPCF_DYNAMIC_PARAMS_2X_COMMON_SIZE_10; + header.entrySize = NVPCF_DYNAMIC_PARAMS_2X_ENTRY_SIZE_1C; + header.entryCount = 0; + + common.param0 = FLD_SET_DRF(PCF_DYNAMIC_PARAMS_COMMON_2X, + _INPUT_PARAM0, _CMD, _GET, common.param0); + + portMemCopy(pData, sizeof(header), &header, sizeof(header)); + portMemCopy(pData + sizeof(header), sizeof(common), &common, sizeof(common)); + portMemCopy(pData + sizeof(header) + sizeof(common), sizeof(entries), entries, sizeof(entries)); + + if ((rc = pOS->osCallACPI_DSM(pGpu, + ACPI_DSM_FUNCTION_NVPCF_2X, + NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_PARAMS, + (NvU32 *)pData, + &dataSize)) != NV_OK) + { + NV_PRINTF(LEVEL_WARNING, + "Unable to retrieve NVPCF dynamic data. Possibly not supported by SBIOS" + "rc = %x\n", rc); + status = NV_ERR_NOT_SUPPORTED; + goto nvpcf2xGetDynamicParams_exit; + } + + if (dataSize < (sizeof(header) + sizeof(common))) + { + status = NV_ERR_INVALID_DATA; + goto nvpcf2xGetDynamicParams_exit; + } + + DYNAMIC_PARAMS_HEADER_2X headerOut = { 0 }; + DYNAMIC_PARAMS_COMMON_2X commonOut = { 0 }; + DYNAMIC_PARAMS_ENTRY_2X entriesOut = { 0 }; + NvU8 idx; + + const char *pSzHeaderFmt = + NVPCF_DYNAMIC_PARAMS_2X_HEADER_FMT_SIZE_05; + const char *pSzCommonFmt = + NVPCF_DYNAMIC_PARAMS_2X_COMMON_FMT_SIZE_10; + const char *pSzEntryFmt = + NVPCF_DYNAMIC_PARAMS_2X_ENTRY_FMT_SIZE_1C; + + // Unpack the header part + configReadStructure(pData, (void *)&headerOut, 0, pSzHeaderFmt); + + if ((headerOut.headerSize != NVPCF_DYNAMIC_PARAMS_2X_HEADER_SIZE_05) || + (headerOut.commonSize != NVPCF_DYNAMIC_PARAMS_2X_COMMON_SIZE_10) || + (headerOut.entrySize != NVPCF_DYNAMIC_PARAMS_2X_ENTRY_SIZE_1C)) + { + status = NV_ERR_INVALID_DATA; + goto nvpcf2xGetDynamicParams_exit; + } + + // Check total size + if (dataSize < ( + NVPCF_DYNAMIC_PARAMS_2X_HEADER_SIZE_05 + + NVPCF_DYNAMIC_PARAMS_2X_COMMON_SIZE_10 + + (headerOut.entryCount * NVPCF_DYNAMIC_PARAMS_2X_ENTRY_SIZE_1C))) + { + status = NV_ERR_INVALID_DATA; + goto nvpcf2xGetDynamicParams_exit; + } + + // Unpack the common part + configReadStructure(pData, (void *)&commonOut, + NVPCF_DYNAMIC_PARAMS_2X_HEADER_SIZE_05, pSzCommonFmt); + + for (idx = 0; idx < headerOut.entryCount; idx++) + { + NvU32 dataOffset; + + dataOffset = NVPCF_DYNAMIC_PARAMS_2X_HEADER_SIZE_05 + + NVPCF_DYNAMIC_PARAMS_2X_COMMON_SIZE_10 + + (idx * NVPCF_DYNAMIC_PARAMS_2X_ENTRY_SIZE_1C); + + // Unpack the controller entry + configReadStructure(pData, (void *)&entriesOut, + dataOffset, pSzEntryFmt); + + // Configurable TGP is from common + pParams->ctgpOffsetmW = (NvS32)NVPCF_DYNAMIC_PARAMS_2X_POWER_UNIT_MW * + (NvS16)DRF_VAL(PCF_DYNAMIC_PARAMS_COMMON_2X, + _OUTPUT_PARAM0, _CMD0_CTGP_AC_OFFSET, commonOut.param0); + + // Rest of AC DB params + pParams->targetTppOffsetmW = (NvS32)NVPCF_DYNAMIC_PARAMS_2X_POWER_UNIT_MW * + (NvS16)DRF_VAL(PCF_DYNAMIC_PARAMS_ENTRY_2X, + _OUTPUT_PARAM1, _CMD0_SIGNED0, entriesOut.param1); + pParams->maxOutputOffsetmW = (NvS32)NVPCF_DYNAMIC_PARAMS_2X_POWER_UNIT_MW * + (NvS16)DRF_VAL(PCF_DYNAMIC_PARAMS_ENTRY_2X, + _OUTPUT_PARAM2, _CMD0_SIGNED0, entriesOut.param2); + pParams->minOutputOffsetmW = (NvS32)NVPCF_DYNAMIC_PARAMS_2X_POWER_UNIT_MW * + (NvS16)DRF_VAL(PCF_DYNAMIC_PARAMS_ENTRY_2X, + _OUTPUT_PARAM2, _CMD0_SIGNED0, entriesOut.param3); + + } + +nvpcf2xGetDynamicParams_exit: + portMemFree(pData); + break; + } + default: + { + NV_PRINTF(LEVEL_INFO, "Inavlid NVPCF subFunc : 0x%x\n", pParams->subFunc); + status = NV_ERR_NOT_SUPPORTED; + } + + } + return status; + +} + static void getHwbcInfo ( @@ -1765,6 +2473,12 @@ cliresCtrlCmdSystemGetP2pCaps_IMPL { OBJGPU *pGpu; + if (RMCFG_FEATURE_PLATFORM_GSP) + { + // Unsupported in GSP-RM; use NV2080_CTRL_CMD_GET_P2P_CAPS directly. + return NV_ERR_NOT_SUPPORTED; + } + if ((pP2PParams->gpuCount == 0) || (pP2PParams->gpuCount > NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS)) { return NV_ERR_INVALID_ARGUMENT; @@ -1779,9 +2493,9 @@ cliresCtrlCmdSystemGetP2pCaps_IMPL return CliGetSystemP2pCaps(pP2PParams->gpuIds, pP2PParams->gpuCount, - &pP2PParams->p2pCaps, - &pP2PParams->p2pOptimalReadCEs, - &pP2PParams->p2pOptimalWriteCEs, + &pP2PParams->p2pCaps, + &pP2PParams->p2pOptimalReadCEs, + &pP2PParams->p2pOptimalWriteCEs, NvP64_VALUE(pP2PParams->p2pCapsStatus), NvP64_VALUE(pP2PParams->busPeerIds)); } @@ -1795,6 +2509,12 @@ cliresCtrlCmdSystemGetP2pCapsV2_IMPL { OBJGPU *pGpu; + if (RMCFG_FEATURE_PLATFORM_GSP) + { + // Unsupported in GSP-RM; use NV2080_CTRL_CMD_GET_P2P_CAPS directly. + return NV_ERR_NOT_SUPPORTED; + } + if ((pP2PParams->gpuCount == 0) || (pP2PParams->gpuCount > NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS)) { return NV_ERR_INVALID_ARGUMENT; @@ -1830,6 +2550,12 @@ cliresCtrlCmdSystemGetP2pCapsMatrix_IMPL NvU32 *groupB = NULL; OBJGPU *pGpu; + if (RMCFG_FEATURE_PLATFORM_GSP) + { + // Unsupported in GSP-RM; use NV2080_CTRL_CMD_GET_P2P_CAPS directly. + return NV_ERR_NOT_SUPPORTED; + } + if (pP2PParams->grpACount == 0 || pP2PParams->grpACount > NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS || pP2PParams->grpBCount > NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS) @@ -1874,7 +2600,7 @@ cliresCtrlCmdSystemGetP2pCapsMatrix_IMPL // Get the A-to-B directional caps status = CliGetSystemP2pCaps((NvU32[]){groupA[grpAIdx], groupB[grpBIdx]}, - 2, + (groupA[grpAIdx] == groupB[grpBIdx]) ? 1 : 2, &pP2PParams->p2pCaps[grpAIdx][grpBIdx], &pP2PParams->a2bOptimalReadCes[grpAIdx][grpBIdx], &pP2PParams->a2bOptimalWriteCes[grpAIdx][grpBIdx], @@ -1898,7 +2624,7 @@ cliresCtrlCmdSystemGetP2pCapsMatrix_IMPL // Get the B-to-A (asymmetric) CEs, skipping (symmetric) p2pCaps status = CliGetSystemP2pCaps((NvU32[]){groupB[grpBIdx], groupA[grpAIdx]}, - 2, + (groupA[grpAIdx] == groupB[grpBIdx]) ? 1 : 2, NULL, // Skip p2pCaps &pP2PParams->b2aOptimalReadCes[grpAIdx][grpBIdx], &pP2PParams->b2aOptimalWriteCes[grpAIdx][grpBIdx], @@ -2291,7 +3017,7 @@ cliresCtrlCmdSyncGpuBoostInfo_IMPL OBJGPUBOOSTMGR *pBoostMgr = SYS_GET_GPUBOOSTMGR(pSys); NV_ASSERT_OR_RETURN(NULL != pParams, NV_ERR_INVALID_ARGUMENT); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); if (NULL == pBoostMgr) { @@ -2322,7 +3048,7 @@ cliresCtrlCmdSyncGpuBoostGroupCreate_IMPL OBJGPUBOOSTMGR *pBoostMgr = SYS_GET_GPUBOOSTMGR(pSys); NV_ASSERT_OR_RETURN(NULL != pParams, NV_ERR_INVALID_ARGUMENT); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); // Start off with invalid boost group ID pParams->boostConfig.boostGroupId = NV0000_SYNC_GPU_BOOST_INVALID_GROUP_ID; @@ -2350,7 +3076,7 @@ cliresCtrlCmdSyncGpuBoostGroupDestroy_IMPL OBJGPUBOOSTMGR *pBoostMgr = SYS_GET_GPUBOOSTMGR(pSys); NV_ASSERT_OR_RETURN(NULL != pParams, NV_ERR_INVALID_ARGUMENT); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); // Destroy the boost group status = gpuboostmgrDestroyGroup(pBoostMgr, pParams->boostGroupId); @@ -2374,13 +3100,86 @@ cliresCtrlCmdSyncGpuBoostGroupInfo_IMPL OBJGPUBOOSTMGR *pBoostMgr = SYS_GET_GPUBOOSTMGR(pSys); NV_ASSERT_OR_RETURN(NULL != pParams, NV_ERR_INVALID_ARGUMENT); - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); status = gpuboostmgrQueryGroups(pBoostMgr, pParams); NV_ASSERT(NV_OK == status); return status; } +NV_STATUS +cliresCtrlCmdVgpuGetStartData_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_VGPU_GET_START_DATA_PARAMS *pVgpuStartParams +) +{ + NV_STATUS status = NV_OK; + NvHandle hClient = RES_GET_CLIENT_HANDLE(pRmCliRes); + NvU32 event, eventStatus; + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + REQUEST_VGPU_INFO_NODE *pRequestVgpu = NULL; + + status = CliGetSystemEventStatus(hClient, &event, &eventStatus); + if (status != NV_OK) + return status; + + if (event != NV0000_NOTIFIERS_VM_START) + return NV_ERR_INVALID_EVENT; + + for (pRequestVgpu = listHead(&pKernelVgpuMgr->listRequestVgpuHead); + pRequestVgpu != NULL; + pRequestVgpu = listNext(&pKernelVgpuMgr->listRequestVgpuHead, pRequestVgpu)) + { + if (pRequestVgpu->deviceState == NV_VGPU_DEV_OPENED) + { + portMemCopy(pVgpuStartParams->mdevUuid, VGPU_UUID_SIZE, pRequestVgpu->mdevUuid, VGPU_UUID_SIZE); + portMemCopy(pVgpuStartParams->configParams, VGPU_CONFIG_PARAMS_MAX_LENGTH, pRequestVgpu->configParams, VGPU_CONFIG_PARAMS_MAX_LENGTH); + pVgpuStartParams->gpuPciId = pRequestVgpu->gpuPciId; + pVgpuStartParams->qemuPid = pRequestVgpu->qemuPid; + pVgpuStartParams->vgpuId = pRequestVgpu->vgpuId; + pVgpuStartParams->gpuPciBdf = pRequestVgpu->gpuPciBdf; + return NV_OK; + } + } + + return NV_ERR_OBJECT_NOT_FOUND; +} + +NV_STATUS +cliresCtrlCmdVgpuGetVgpuVersion_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS *vgpuVersionInfo +) +{ + vgpuVersionInfo->host_min_supported_version + = GRIDSW_VERSION_EXTERNAL(NV_VGPU_MIN_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR, + NV_VGPU_MIN_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MINOR); + vgpuVersionInfo->host_max_supported_version + = GRIDSW_VERSION_EXTERNAL(NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR, + NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MINOR); + + NV_PRINTF(LEVEL_INFO, "User enforced vGPU version = (0x%x, 0x%x)\n", + vgpuVersionInfo->user_min_supported_version, + vgpuVersionInfo->user_max_supported_version); + + return (kvgpumgrGetHostVgpuVersion(&(vgpuVersionInfo->user_min_supported_version), + &(vgpuVersionInfo->user_max_supported_version))); +} + +NV_STATUS +cliresCtrlCmdVgpuSetVgpuVersion_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS *vgpuVersionInfo +) +{ + return (kvgpumgrSetHostVgpuVersion(vgpuVersionInfo->min_version, + vgpuVersionInfo->max_version)); +} + NV_STATUS cliresCtrlCmdClientGetAddrSpaceType_IMPL ( @@ -2408,10 +3207,10 @@ cliresCtrlCmdClientGetAddrSpaceType_IMPL { NV_ASSERT_OK_OR_RETURN(memGetMapAddrSpace(pMemory, &callContext, pParams->mapFlags, &memType)); - // Soon FlaMemory will be moved to ADDR_FABRIC. For now, this WAR. + // Soon FlaMemory is deprecated. This is just a hack to keep compatibility. if ((memType == ADDR_FBMEM) && (dynamicCast(pMemory, FlaMemory) != NULL)) { - memType = ADDR_FABRIC; + memType = ADDR_FABRIC_V2; } } else @@ -2438,10 +3237,17 @@ cliresCtrlCmdClientGetAddrSpaceType_IMPL case ADDR_REGMEM: pParams->addrSpaceType = NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_REGMEM; break; - case ADDR_FABRIC: case ADDR_FABRIC_V2: pParams->addrSpaceType = NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC; break; + case ADDR_FABRIC_MC: +#ifdef NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC_MC + pParams->addrSpaceType = NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_FABRIC_MC; + break; +#else + NV_ASSERT(0); + return NV_ERR_INVALID_ARGUMENT; +#endif case ADDR_VIRTUAL: NV_PRINTF(LEVEL_ERROR, "VIRTUAL (0x%x) is not a valid NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE\n", @@ -2622,6 +3428,26 @@ cliresCtrlCmdClientGetChildHandle_IMPL return status; } +NV_STATUS +cliresCtrlCmdObjectsAreDuplicates_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS *pParams +) +{ + RsResourceRef *pResRef; + RsClient *pClient = RES_GET_CLIENT(pRmCliRes); + + NV_CHECK_OK_OR_RETURN(LEVEL_SILENT, + clientGetResourceRef(pClient, pParams->hObject1, &pResRef)); + + NV_CHECK_OK_OR_RETURN(LEVEL_SILENT, + resIsDuplicate(pResRef->pResource, pParams->hObject2, + &pParams->bDuplicates)); + + return NV_OK; +} + NV_STATUS cliresCtrlCmdGpuGetMemOpEnable_IMPL ( @@ -2717,6 +3543,11 @@ cliresCtrlCmdNvdGetRcerrRpt_IMPL if (IS_GSP_CLIENT(pGpu)) { + NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS *pLocalParams = + portMemAllocNonPaged(sizeof *pLocalParams); + + NV_CHECK_OR_RETURN(LEVEL_INFO, pLocalParams != NULL, NV_ERR_NO_MEMORY); + // // Pre-GSP, RcDiagRec from all GPUs were stored in kernel sysmem in a // single RING_BUFFER_LOG. @@ -2730,19 +3561,19 @@ cliresCtrlCmdNvdGetRcerrRpt_IMPL for (; pGpu != NULL ; pGpu = gpumgrGetNextGpu(gpuMask, &gpuIdx)) { RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS localParams = {0}; - localParams.reqIdx = pParams->reqIdx; - localParams.owner = pParams->owner; - localParams.processId = pParams->processId; + portMemSet(pLocalParams, 0, sizeof(*pLocalParams)); + pLocalParams->reqIdx = pParams->reqIdx; + pLocalParams->owner = pParams->owner; + pLocalParams->processId = pParams->processId; status = pRmApi->Control(pRmApi, RES_GET_CLIENT_HANDLE(pRmCliRes), RES_GET_HANDLE(pRmCliRes), NV0000_CTRL_CMD_NVD_GET_RCERR_RPT, - &localParams, - sizeof localParams); + pLocalParams, + sizeof *pLocalParams); if (status == NV_OK && - (localParams.flags & + (pLocalParams->flags & NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_DATA_VALID)) { // @@ -2757,12 +3588,12 @@ cliresCtrlCmdNvdGetRcerrRpt_IMPL // NvU16 indexOffset = gpuIdx * MAX_RCDB_RCDIAG_WRAP_BUFF; - *pParams = localParams; + *pParams = *pLocalParams; pParams->startIdx += indexOffset; pParams->endIdx += indexOffset; pParams->rptIdx += indexOffset; - return NV_OK; + break; } if (status == NV_ERR_BUSY_RETRY) @@ -2773,9 +3604,12 @@ cliresCtrlCmdNvdGetRcerrRpt_IMPL // BUSY_RETRY on one of the Gpus (which might have contained the // record). // - return status; + break; } } + + portMemFree(pLocalParams); + pLocalParams = NULL; } return status; @@ -2879,6 +3713,72 @@ NV_STATUS cliresCtrlCmdSystemGetClientDatabaseInfo_IMPL return NV_OK; } +/*! + * @brief Used to push the GSP ucode into RM. This function is used only on + * VMware + * + * @return + * NV_OK The sent data is stored successfully + * NV_ERR_INVALID_ARGUMENT if the arguments are not proper + * NV_ERR_NO_MEMORY if memory allocation failed + * NV_ERR_NOT_SUPPORTED if function is invoked on non-GSP setup or any + * setup other than VMware host + */ +NV_STATUS cliresCtrlCmdPushGspUcode_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS *pParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS cliresCtrlCmdSystemRmctrlCacheModeCtrl_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_PARAMS *pParams +) +{ + switch (pParams->cmd) + { + case NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_SET: + rmapiControlCacheSetMode(pParams->mode); + break; + case NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_CMD_GET: + pParams->mode = rmapiControlCacheGetMode(); + break; + default: + return NV_ERR_INVALID_ARGUMENT; + } + return NV_OK; +} + +NV_STATUS +cliresCtrlCmdSystemPfmreqhndlrGetPerfSensorCounters_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS *pParams +) +{ + NV_STATUS status = NV_OK; + portMemSet(pParams, 0, sizeof(*pParams)); + return status; +} + +NV_STATUS +cliresCtrlCmdSystemPfmreqhndlrGetExtendedPerfSensorCounters_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_GET_PERF_SENSOR_COUNTERS_PARAMS *pParams +) +{ + NV_STATUS status = NV_OK; + portMemSet(pParams, 0, sizeof(*pParams)); + return status; +} + +// GPS HOSUNGK DELETE after KMD, NvAPI changes are made + NV_STATUS cliresCtrlCmdSystemGetPerfSensorCounters_IMPL ( @@ -2886,9 +3786,7 @@ cliresCtrlCmdSystemGetPerfSensorCounters_IMPL NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS *pParams ) { - NV_STATUS status = NV_OK; - portMemSet(pParams, 0, sizeof(*pParams)); - return status; + return NV_OK; } NV_STATUS @@ -2898,7 +3796,5 @@ cliresCtrlCmdSystemGetExtendedPerfSensorCounters_IMPL NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS *pParams ) { - NV_STATUS status = NV_OK; - portMemSet(pParams, 0, sizeof(*pParams)); - return status; + return NV_OK; } diff --git a/src/nvidia/src/kernel/rmapi/control.c b/src/nvidia/src/kernel/rmapi/control.c index 19cefeeb5..49e8e3c1a 100644 --- a/src/nvidia/src/kernel/rmapi/control.c +++ b/src/nvidia/src/kernel/rmapi/control.c @@ -28,12 +28,14 @@ #include "diagnostics/tracer.h" #include "core/locks.h" #include "core/thread_state.h" +#include "virtualization/hypervisor/hypervisor.h" #include "gpu/device/device.h" #include "entry_points.h" #include "resserv/rs_access_map.h" #include "gpu/gpu.h" #include "gpu/subdevice/subdevice.h" +#include "rmapi/rmapi_utils.h" #include "ctrl/ctrl0000/ctrl0000client.h" // NV0000_CTRL_CMD_CLIENT_* #include "ctrl/ctrl0000/ctrl0000gpu.h" // NV0000_CTRL_CMD_GPU_* @@ -46,6 +48,7 @@ #include "ctrl/ctrlc370/ctrlc370chnc.h" // NVC370_CTRL_CMD_* #include "ctrl/ctrl9010.h" //NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION #include "ctrl/ctrl2080/ctrl2080tmr.h" // NV2080_CTRL_CMD_TIMER_* +#include "ctrl/ctrl0000/ctrl0000gpuacct.h" // NV0000_CTRL_CMD_GPUACCT_* static NV_STATUS releaseDeferRmCtrlBuffer(RmCtrlDeferredCmd* pRmCtrlDeferredCmd) @@ -205,7 +208,7 @@ _rmControlDeferred(RmCtrlParams *pRmCtrlParams, NvP64 pUserParams, NvU32 paramsS // flag is set and after this rmctrl failed to acquire lock. // LOCK: try to acquire GPUs lock - if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_COND_ACQUIRE, + if (rmGpuLocksAcquire(GPU_LOCK_FLAGS_COND_ACQUIRE, RM_LOCK_MODULES_CLIENT) == NV_OK) { if (osCondAcquireRmSema(pSys->pSema) == NV_OK) @@ -257,7 +260,10 @@ serverControlApiCopyIn pUserParams = NV_PTR_TO_NvP64(pRmCtrlParams->pParams); paramsSize = pRmCtrlParams->paramsSize; - RMAPI_PARAM_COPY_INIT(*pParamCopy, pRmCtrlParams->pParams, pUserParams, paramsSize, 1); + RMAPI_PARAM_COPY_INIT(*pParamCopy, pRmCtrlParams->pParams, pUserParams, 1, paramsSize); + + if (pCookie->apiCopyFlags & RMCTRL_API_COPY_FLAGS_SKIP_COPYIN) + pParamCopy->flags |= RMAPI_PARAM_COPY_FLAGS_SKIP_COPYIN; rmStatus = rmapiParamsAcquire(pParamCopy, (pRmCtrlParams->secInfo.paramLocation == PARAM_LOCATION_USER)); if (rmStatus != NV_OK) @@ -289,6 +295,16 @@ serverControlApiCopyOut NvBool bFreeParamCopy; NV_ASSERT_OR_RETURN(pCookie != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pRmCtrlParams != NULL, NV_ERR_INVALID_ARGUMENT); + + if ((pCookie->apiCopyFlags & RMCTRL_API_COPY_FLAGS_SET_CONTROL_CACHE) && rmStatus == NV_OK) + { + rmapiControlCacheSet(pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->cmd, + pRmCtrlParams->pParams, + pRmCtrlParams->paramsSize); + } pParamCopy = &pCookie->paramCopy; pEmbeddedParamCopies = pCookie->embeddedParamCopies; @@ -296,7 +312,9 @@ serverControlApiCopyOut bFreeParamCopy = pCookie->bFreeParamCopy; bFreeEmbeddedCopy = pCookie->bFreeEmbeddedCopy; - if ((rmStatus != NV_OK) && !(pCookie->ctrlFlags & RMCTRL_FLAGS_COPYOUT_ON_ERROR)) + if ((rmStatus != NV_OK) && + (!(pCookie->ctrlFlags & RMCTRL_FLAGS_COPYOUT_ON_ERROR) || + (pCookie->apiCopyFlags & RMCTRL_API_COPY_FLAGS_FORCE_SKIP_COPYOUT_ON_ERROR))) { pParamCopy->flags |= RMAPI_PARAM_COPY_FLAGS_SKIP_COPYOUT; @@ -526,7 +544,7 @@ _rmapiRmControl(NvHandle hClient, NvHandle hObject, NvU32 cmd, NvP64 pUserParams // LOCK: try to acquire GPUs lock if (osCondAcquireRmSema(pSys->pSema) == NV_OK) { - if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_COND_ACQUIRE, RM_LOCK_MODULES_CLIENT) == NV_OK) + if (rmGpuLocksAcquire(GPU_LOCK_FLAGS_COND_ACQUIRE, RM_LOCK_MODULES_CLIENT) == NV_OK) { lockInfo.state |= RM_LOCK_STATES_GPUS_LOCK_ACQUIRED; lockInfo.flags |= RM_LOCK_FLAGS_NO_API_LOCK | @@ -535,7 +553,7 @@ _rmapiRmControl(NvHandle hClient, NvHandle hObject, NvU32 cmd, NvP64 pUserParams rmStatus = serverControl(&g_resServ, &rmCtrlParams); // UNLOCK: release GPUs lock - rmGpuLocksRelease(GPUS_LOCK_FLAGS_COND_ACQUIRE, osIsISR() ? rmCtrlParams.pGpu : NULL); + rmGpuLocksRelease(GPU_LOCK_FLAGS_COND_ACQUIRE, osIsISR() ? rmCtrlParams.pGpu : NULL); } else { @@ -556,6 +574,27 @@ _rmapiRmControl(NvHandle hClient, NvHandle hObject, NvU32 cmd, NvP64 pUserParams // Normal rmctrl request. // + if (rmapiCmdIsCacheable(cmd, NV_FALSE)) + { + rmCtrlParams.pCookie->apiCopyFlags |= RMCTRL_API_COPY_FLAGS_SKIP_COPYIN; + rmCtrlParams.pCookie->apiCopyFlags |= RMCTRL_API_COPY_FLAGS_FORCE_SKIP_COPYOUT_ON_ERROR; + + serverControlApiCopyIn(&g_resServ, &rmCtrlParams, rmCtrlParams.pCookie); + rmStatus = rmapiControlCacheGet(hClient, hObject, cmd, rmCtrlParams.pParams, paramsSize); + serverControlApiCopyOut(&g_resServ, &rmCtrlParams, rmCtrlParams.pCookie, rmStatus); + + if (rmStatus == NV_OK) + { + goto done; + } + else + { + // reset cookie if cache get failed + portMemSet(rmCtrlParams.pCookie, 0, sizeof(RS_CONTROL_COOKIE)); + rmCtrlParams.pCookie->apiCopyFlags |= RMCTRL_API_COPY_FLAGS_SET_CONTROL_CACHE; + } + } + RM_API_CONTEXT rmApiContext = {0}; rmStatus = rmapiPrologue(pRmApi, &rmApiContext); if (rmStatus != NV_OK) @@ -571,6 +610,47 @@ done: return rmStatus; } +static NvBool +serverControl_ValidateVgpu +( + OBJGPU *pGpu, + NvU32 cmd, + RS_PRIV_LEVEL privLevel, + const NvU32 cookieFlags +) +{ + NvBool bPermissionGranted = NV_FALSE; + + // Check if context is already sufficiently admin privileged + if (cookieFlags & RMCTRL_FLAGS_PRIVILEGED) + { + if (privLevel >= RS_PRIV_LEVEL_USER_ROOT) + { + bPermissionGranted = NV_TRUE; + } + } + + // + // If context is not privileged enough, check whether this + // control call is allowed in current hypervisor environment + // + if (!bPermissionGranted) + { + { + // For non-NV0000, identify current hypervisor environment and check for allow flag + if + ( + (IS_SRIOV_WITH_VGPU_GSP_ENABLED(pGpu) && (cookieFlags & RMCTRL_FLAGS_CPU_PLUGIN_FOR_VGPU_GSP)) + ) + { + bPermissionGranted = NV_TRUE; + } + } + } + + return bPermissionGranted; +} + // validate rmctrl flags NV_STATUS serverControl_ValidateCookie ( @@ -578,7 +658,19 @@ NV_STATUS serverControl_ValidateCookie RS_CONTROL_COOKIE *pRmCtrlExecuteCookie ) { - NV_STATUS status; + NV_STATUS status; + OBJGPU *pGpu; + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + + if (RMCFG_FEATURE_PLATFORM_GSP) + { + pGpu = gpumgrGetSomeGpu(); + if (pGpu == NULL) + { + NV_PRINTF(LEVEL_ERROR, "GPU is not found\n"); + return NV_ERR_INVALID_STATE; + } + } if (g_resServ.bRsAccessEnabled) { @@ -621,34 +713,68 @@ NV_STATUS serverControl_ValidateCookie return NV_ERR_NOT_SUPPORTED; } - if (pRmCtrlExecuteCookie->ctrlFlags & RMCTRL_FLAGS_PRIVILEGED) + // + // Narrow down usecase as much as possible to CPU-plugin. + // Must be running in hypervisor, at least cached privileged, not a kernel context and + // accessing a privileged or kernel privileged control call. + // + if (hypervisorIsVgxHyper() && + clientIsAdmin(pCallContext->pClient, clientGetCachedPrivilege(pCallContext->pClient)) && + (pRmCtrlParams->secInfo.privLevel != RS_PRIV_LEVEL_KERNEL) && + !(pRmCtrlExecuteCookie->ctrlFlags & RMCTRL_FLAGS_NON_PRIVILEGED)) { - // - // Calls originating from usermode require admin perms while calls - // originating from other kernel drivers are always allowed. - // - if ((pRmCtrlParams->secInfo.privLevel < RS_PRIV_LEVEL_USER_ROOT) - ) + // VGPU CPU-Plugin (Legacy Non-SRIOV, SRIOV-HYPERV, SRIOV-LEGACY, SRIOV-Offload), and Admin or kernel clients running in hypervisor + NvBool bPermissionGranted = serverControl_ValidateVgpu(pRmCtrlParams->pGpu, + pRmCtrlParams->cmd, + pRmCtrlParams->secInfo.privLevel, + pRmCtrlExecuteCookie->ctrlFlags); + if (!bPermissionGranted) { NV_PRINTF(LEVEL_WARNING, - "hClient: 0x%08x, hObject 0x%08x, cmd 0x%08x: non-privileged context issued privileged cmd\n", + "hClient: 0x%08x, hObject 0x%08x, cmd 0x%08x: non-privileged hypervisor context issued privileged cmd\n", pRmCtrlParams->hClient, pRmCtrlParams->hObject, pRmCtrlParams->cmd); return NV_ERR_INSUFFICIENT_PERMISSIONS; } } - - // permissions check for KERNEL_PRIVILEGED (default) unless NON_PRIVILEGED, PRIVILEGED or INTERNAL is specified - if ( !(pRmCtrlExecuteCookie->ctrlFlags & (RMCTRL_FLAGS_NON_PRIVILEGED | RMCTRL_FLAGS_PRIVILEGED | RMCTRL_FLAGS_INTERNAL))) + else { - if ((pRmCtrlParams->secInfo.privLevel < RS_PRIV_LEVEL_KERNEL) - ) + // + // Non-Hypervisor clients + // PF clients + // Unprivileged processes running in Hypervisor + // Privileged processes running in Hypervisor, executing an unprivileged control call. + // Kernel privileged processes running in Hypervisor + // + + // permissions check for PRIVILEGED controls + if (pRmCtrlExecuteCookie->ctrlFlags & RMCTRL_FLAGS_PRIVILEGED) { - NV_PRINTF(LEVEL_WARNING, - "hClient: 0x%08x, hObject 0x%08x, cmd 0x%08x: non-kernel client issued kernel-only cmd\n", - pRmCtrlParams->hClient, pRmCtrlParams->hObject, - pRmCtrlParams->cmd); - return NV_ERR_INSUFFICIENT_PERMISSIONS; + // + // Calls originating from usermode require admin perms while calls + // originating from other kernel drivers are always allowed. + // + if (pRmCtrlParams->secInfo.privLevel < RS_PRIV_LEVEL_USER_ROOT) + { + NV_PRINTF(LEVEL_WARNING, + "hClient: 0x%08x, hObject 0x%08x, cmd 0x%08x: non-privileged context issued privileged cmd\n", + pRmCtrlParams->hClient, pRmCtrlParams->hObject, + pRmCtrlParams->cmd); + return NV_ERR_INSUFFICIENT_PERMISSIONS; + } + } + + // permissions check for KERNEL_PRIVILEGED (default) unless NON_PRIVILEGED, PRIVILEGED or INTERNAL is specified + if (!(pRmCtrlExecuteCookie->ctrlFlags & (RMCTRL_FLAGS_NON_PRIVILEGED | RMCTRL_FLAGS_PRIVILEGED | RMCTRL_FLAGS_INTERNAL))) + { + if (pRmCtrlParams->secInfo.privLevel < RS_PRIV_LEVEL_KERNEL) + { + NV_PRINTF(LEVEL_WARNING, + "hClient: 0x%08x, hObject 0x%08x, cmd 0x%08x: non-kernel client issued kernel-only cmd\n", + pRmCtrlParams->hClient, pRmCtrlParams->hObject, + pRmCtrlParams->cmd); + return NV_ERR_INSUFFICIENT_PERMISSIONS; + } } } @@ -681,6 +807,36 @@ serverControlLookupLockFlags LOCK_ACCESS_TYPE *pAccess ) { + // + // Calls with LOCK_TOP doesn't fill in the cookie param correctly. + // This is just a WAR for this. Since the optimisation that depends on this + // flag only works in full GSP offload mode, it's gated to that. + // + NvBool areAllGpusInOffloadMode = gpumgrAreAllGpusInOffloadMode(); + NvU32 controlFlags = pRmCtrlExecuteCookie->ctrlFlags; + if (controlFlags == 0 && !RMCFG_FEATURE_PLATFORM_GSP && areAllGpusInOffloadMode) + { + NV_STATUS status = rmapiutilGetControlInfo(pRmCtrlParams->cmd, &controlFlags, NULL); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_INFO, + "rmapiutilGetControlInfo(cmd=0x%x, out flags=0x%x, NULL) = status=0x%x\n", + pRmCtrlParams->cmd, controlFlags, status); + } + } + + // + // If the control is ROUTE_TO_PHYSICAL, and we're in GSP offload mode, + // we can use a more relaxed locking mode: + // 1. Only lock the single device and not all GPUs + // 2. Take the API lock for READ instead of WRITE. + // Unfortunately, at this point we don't have the pGpu yet to check if it + // is in offload mode or not. So, instead, these optimizations are only + // done if *all* GPUs in the system are in offload mode. + // + NvBool bUseGspLockingMode = areAllGpusInOffloadMode && + (controlFlags & RMCTRL_FLAGS_ROUTE_TO_PHYSICAL); + if (pAccess == NULL) return NV_ERR_INVALID_ARGUMENT; @@ -695,7 +851,18 @@ serverControlLookupLockFlags } if (pRmCtrlExecuteCookie->ctrlFlags & RMCTRL_FLAGS_API_LOCK_READONLY) + { *pAccess = LOCK_ACCESS_READ; + } + + // + // ROUTE_TO_PHYSICAL controls always take the READ API lock. This only applies + // to GSP clients: Only there can we guarantee per-gpu execution of commands. + // + if (g_resServ.bRouteToPhysicalLockBypass && bUseGspLockingMode) + { + *pAccess = LOCK_ACCESS_READ; + } return NV_OK; } @@ -719,7 +886,8 @@ serverControlLookupLockFlags } else { - if (pRmCtrlExecuteCookie->ctrlFlags & RMCTRL_FLAGS_GPU_LOCK_DEVICE_ONLY) + if ((pRmCtrlExecuteCookie->ctrlFlags & RMCTRL_FLAGS_GPU_LOCK_DEVICE_ONLY) || + (g_resServ.bRouteToPhysicalLockBypass && bUseGspLockingMode)) { pLockInfo->flags |= RM_LOCK_FLAGS_NO_GPUS_LOCK; pLockInfo->flags |= RM_LOCK_FLAGS_GPU_GROUP_LOCK; diff --git a/src/nvidia/src/kernel/rmapi/embedded_param_copy.c b/src/nvidia/src/kernel/rmapi/embedded_param_copy.c index b7768eae6..ee00f88ca 100644 --- a/src/nvidia/src/kernel/rmapi/embedded_param_copy.c +++ b/src/nvidia/src/kernel/rmapi/embedded_param_copy.c @@ -52,7 +52,6 @@ #include "ctrl/ctrl0073.h" #include "ctrl/ctrlb06f.h" #include "ctrl/ctrl83de.h" -#include "ctrl/ctrla083.h" #ifdef USE_AMAPLIB #include "amap_v1.h" #endif @@ -314,6 +313,27 @@ NV_STATUS embeddedParamCopyIn(RMAPI_PARAM_COPY *paramCopies, RmCtrlParams *pRmCt break; } + case NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD: + { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS); + + RMAPI_PARAM_COPY_INIT(paramCopies[0], + ((NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS*)pParams)->inData, + ((NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS*)pParams)->inData, + ((NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS*)pParams)->inDataSize, 1); + paramCopies[0].flags |= RMAPI_PARAM_COPY_FLAGS_SKIP_COPYOUT; + + RMAPI_PARAM_COPY_INIT(paramCopies[1], + ((NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS*)pParams)->outData, + ((NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS*)pParams)->outData, + ((NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS*)pParams)->outDataSize, 1); + paramCopies[1].flags |= RMAPI_PARAM_COPY_FLAGS_SKIP_COPYIN; + paramCopies[1].flags |= RMAPI_PARAM_COPY_FLAGS_ZERO_BUFFER; + + paramsCnt++; + + break; + } case NV0080_CTRL_CMD_HOST_GET_CAPS: { CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV0080_CTRL_HOST_GET_CAPS_PARAMS); @@ -351,6 +371,32 @@ NV_STATUS embeddedParamCopyIn(RMAPI_PARAM_COPY *paramCopies, RmCtrlParams *pRmCt sizeof(NV2080_CTRL_BIOS_INFO)); break; } + case NV2080_CTRL_CMD_BIOS_GET_NBSI: + { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV2080_CTRL_BIOS_GET_NBSI_PARAMS); + + RMAPI_PARAM_COPY_INIT(paramCopies[0], + ((NV2080_CTRL_BIOS_GET_NBSI_PARAMS*)pParams)->retBuf, + ((NV2080_CTRL_BIOS_GET_NBSI_PARAMS*)pParams)->retBuf, + ((NV2080_CTRL_BIOS_GET_NBSI_PARAMS*)pParams)->retSize, 1); + paramCopies[0].flags |= RMAPI_PARAM_COPY_FLAGS_SKIP_COPYIN; + paramCopies[0].flags |= RMAPI_PARAM_COPY_FLAGS_ZERO_BUFFER; + + break; + } + case NV2080_CTRL_CMD_BIOS_GET_NBSI_OBJ: + { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS); + + RMAPI_PARAM_COPY_INIT(paramCopies[0], + ((NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS*)pParams)->retBuf, + ((NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS*)pParams)->retBuf, + ((NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS*)pParams)->retSize, 1); + paramCopies[0].flags |= RMAPI_PARAM_COPY_FLAGS_SKIP_COPYIN; + paramCopies[0].flags |= RMAPI_PARAM_COPY_FLAGS_ZERO_BUFFER; + + break; + } case NV0080_CTRL_CMD_GR_GET_INFO: { CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV0080_CTRL_GR_GET_INFO_PARAMS); @@ -369,7 +415,7 @@ NV_STATUS embeddedParamCopyIn(RMAPI_PARAM_COPY *paramCopies, RmCtrlParams *pRmCt RMAPI_PARAM_COPY_INIT(paramCopies[0], ((NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS*)pParams)->fifoStartChannelList, ((NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS*)pParams)->fifoStartChannelList, - ((NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS*)pParams)->fifoStartChannelListSize, + ((NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS*)pParams)->fifoStartChannelListCount, sizeof(NV0080_CTRL_FIFO_CHANNEL)); break; } @@ -655,6 +701,7 @@ NV_STATUS embeddedParamCopyIn(RMAPI_PARAM_COPY *paramCopies, RmCtrlParams *pRmCt ((NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS*)pParams)->pPdeBuffer, ((NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS*)pParams)->pPdeBuffer, 1, 0x8/*NV_MMU_VER2_PDE__SIZE*/); + paramCopies[0].flags |= RMAPI_PARAM_COPY_FLAGS_SKIP_COPYIN; paramCopies[0].flags |= RMAPI_PARAM_COPY_FLAGS_ZERO_BUFFER; @@ -706,24 +753,32 @@ NV_STATUS embeddedParamCopyOut(RMAPI_PARAM_COPY *paramCopies, RmCtrlParams *pRmC { case NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS); + status = rmapiParamsRelease(¶mCopies[0]); ((NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS*)pParams)->sessionInfoTbl = paramCopies[0].pUserParams; break; } case NV2080_CTRL_CMD_GPU_GET_ENGINES: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV2080_CTRL_GPU_GET_ENGINES_PARAMS); + status = rmapiParamsRelease(¶mCopies[0]); ((NV2080_CTRL_GPU_GET_ENGINES_PARAMS*)pParams)->engineList = paramCopies[0].pUserParams; break; } case NV2080_CTRL_CMD_BUS_GET_INFO: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV2080_CTRL_BUS_GET_INFO_PARAMS); + status = rmapiParamsRelease(¶mCopies[0]); ((NV2080_CTRL_BUS_GET_INFO_PARAMS*)pParams)->busInfoList = paramCopies[0].pUserParams; break; } case NV2080_CTRL_CMD_FB_GET_INFO: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV2080_CTRL_FB_GET_INFO_PARAMS); + status = rmapiParamsRelease(¶mCopies[0]); ((NV2080_CTRL_FB_GET_INFO_PARAMS*)pParams)->fbInfoList = paramCopies[0].pUserParams; break; @@ -732,6 +787,9 @@ NV_STATUS embeddedParamCopyOut(RMAPI_PARAM_COPY *paramCopies, RmCtrlParams *pRmC case NV2080_CTRL_CMD_FB_GET_AMAP_CONF: { NV_STATUS status2; + + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS); + NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS *pParamsUser = (NV2080_CTRL_CMD_FB_GET_AMAP_CONF_PARAMS *) pParams; @@ -747,12 +805,16 @@ NV_STATUS embeddedParamCopyOut(RMAPI_PARAM_COPY *paramCopies, RmCtrlParams *pRmC #endif case NV2080_CTRL_CMD_CE_GET_CAPS: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV2080_CTRL_CE_GET_CAPS_PARAMS); + status = rmapiParamsRelease(¶mCopies[0]); ((NV2080_CTRL_CE_GET_CAPS_PARAMS*)pParams)->capsTbl = paramCopies[0].pUserParams; break; } case NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS); + NV_STATUS handleListParamStatus = rmapiParamsRelease(¶mCopies[0]); ((NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS*)pParams)->pChannelHandleList = paramCopies[0].pUserParams; @@ -764,96 +826,163 @@ NV_STATUS embeddedParamCopyOut(RMAPI_PARAM_COPY *paramCopies, RmCtrlParams *pRmC break; } + case NV0000_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD: + { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS); + + NV_STATUS inParamsStatus = rmapiParamsRelease(¶mCopies[0]); + ((NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS*)pParams)->inData = paramCopies[0].pUserParams; + + status = rmapiParamsRelease(¶mCopies[1]); + ((NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS*)pParams)->outData = paramCopies[1].pUserParams; + + if (inParamsStatus != NV_OK) + status = inParamsStatus; + break; + } case NV83DE_CTRL_CMD_DEBUG_READ_MEMORY: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS); + status = rmapiParamsRelease(¶mCopies[0]); ((NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS*)pRmCtrlParams->pParams)->buffer = paramCopies[0].pUserParams; break; } case NV83DE_CTRL_CMD_DEBUG_WRITE_MEMORY: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS); + status = rmapiParamsRelease(¶mCopies[0]); ((NV83DE_CTRL_DEBUG_WRITE_MEMORY_PARAMS*)pRmCtrlParams->pParams)->buffer = paramCopies[0].pUserParams; break; } case NV83DE_CTRL_CMD_DEBUG_READ_BATCH_MEMORY: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS); + status = rmapiParamsRelease(¶mCopies[0]); ((NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS*)pRmCtrlParams->pParams)->pData = paramCopies[0].pUserParams; break; } case NV83DE_CTRL_CMD_DEBUG_WRITE_BATCH_MEMORY: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS); + status = rmapiParamsRelease(¶mCopies[0]); ((NV83DE_CTRL_DEBUG_ACCESS_MEMORY_PARAMS*)pRmCtrlParams->pParams)->pData = paramCopies[0].pUserParams; break; } case NV0080_CTRL_CMD_HOST_GET_CAPS: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV0080_CTRL_HOST_GET_CAPS_PARAMS); + status = rmapiParamsRelease(¶mCopies[0]); ((NV0080_CTRL_HOST_GET_CAPS_PARAMS*)pParams)->capsTbl = paramCopies[0].pUserParams; break; } case NV0080_CTRL_CMD_MSENC_GET_CAPS: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV0080_CTRL_MSENC_GET_CAPS_PARAMS); + status = rmapiParamsRelease(¶mCopies[0]); ((NV0080_CTRL_MSENC_GET_CAPS_PARAMS*)pParams)->capsTbl = paramCopies[0].pUserParams; break; } case NV2080_CTRL_CMD_BIOS_GET_INFO: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV2080_CTRL_BIOS_GET_INFO_PARAMS); + status = rmapiParamsRelease(¶mCopies[0]); ((NV2080_CTRL_BIOS_GET_INFO_PARAMS*)pParams)->biosInfoList = paramCopies[0].pUserParams; break; } + case NV2080_CTRL_CMD_BIOS_GET_NBSI: + { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV2080_CTRL_BIOS_GET_NBSI_PARAMS); + + status = rmapiParamsRelease(¶mCopies[0]); + ((NV2080_CTRL_BIOS_GET_NBSI_PARAMS*)pParams)->retBuf = paramCopies[0].pUserParams; + break; + } + case NV2080_CTRL_CMD_BIOS_GET_NBSI_OBJ: + { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS); + + if (((NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS*)pParams)->retSize == 0) + { + paramCopies[0].flags |= RMAPI_PARAM_COPY_FLAGS_SKIP_COPYOUT; + } + + status = rmapiParamsRelease(¶mCopies[0]); + ((NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS*)pParams)->retBuf = paramCopies[0].pUserParams; + break; + } case NV0080_CTRL_CMD_GR_GET_INFO: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV0080_CTRL_GR_GET_INFO_PARAMS); + status = rmapiParamsRelease(¶mCopies[0]); ((NV0080_CTRL_GR_GET_INFO_PARAMS*)pParams)->grInfoList = paramCopies[0].pUserParams; break; } case NV0080_CTRL_CMD_FIFO_START_SELECTED_CHANNELS: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS); + status = rmapiParamsRelease(¶mCopies[0]); ((NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS*)pParams)->fifoStartChannelList = paramCopies[0].pUserParams; break; } case NV0080_CTRL_CMD_FIFO_GET_CAPS: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV0080_CTRL_FIFO_GET_CAPS_PARAMS); + status = rmapiParamsRelease(¶mCopies[0]); ((NV0080_CTRL_FIFO_GET_CAPS_PARAMS*)pParams)->capsTbl = paramCopies[0].pUserParams; break; } case NV402C_CTRL_CMD_I2C_INDEXED: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV402C_CTRL_I2C_INDEXED_PARAMS); + status = rmapiParamsRelease(¶mCopies[0]); ((NV402C_CTRL_I2C_INDEXED_PARAMS*)pParams)->pMessage = paramCopies[0].pUserParams; break; } case NV402C_CTRL_CMD_I2C_TRANSACTION: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV402C_CTRL_I2C_TRANSACTION_PARAMS); + return i2cTransactionCopyOut(paramCopies, pRmCtrlParams); } case NV2080_CTRL_CMD_GPU_EXEC_REG_OPS: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS); + status = rmapiParamsRelease(¶mCopies[0]); ((NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS*)pParams)->regOps = paramCopies[0].pUserParams; break; } case NV2080_CTRL_CMD_NVD_GET_DUMP: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV2080_CTRL_NVD_GET_DUMP_PARAMS); + status = rmapiParamsRelease(¶mCopies[0]); ((NV2080_CTRL_NVD_GET_DUMP_PARAMS*)pParams)->pBuffer = paramCopies[0].pUserParams; break; } case NV0000_CTRL_CMD_NVD_GET_DUMP: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV0000_CTRL_NVD_GET_DUMP_PARAMS); + status = rmapiParamsRelease(¶mCopies[0]); ((NV0000_CTRL_NVD_GET_DUMP_PARAMS*)pParams)->pBuffer = paramCopies[0].pUserParams; break; } case NV0041_CTRL_CMD_GET_SURFACE_INFO: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV0041_CTRL_GET_SURFACE_INFO_PARAMS); + status = rmapiParamsRelease(¶mCopies[0]); ((NV0041_CTRL_GET_SURFACE_INFO_PARAMS*)pParams)->surfaceInfoList = paramCopies[0].pUserParams; break; @@ -862,6 +991,8 @@ NV_STATUS embeddedParamCopyOut(RMAPI_PARAM_COPY *paramCopies, RmCtrlParams *pRmC // Not defined on all platforms case NV0000_CTRL_CMD_OS_GET_CAPS: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV0000_CTRL_OS_GET_CAPS_PARAMS); + status = rmapiParamsRelease(¶mCopies[0]); ((NV0000_CTRL_OS_GET_CAPS_PARAMS*)pParams)->capsTbl = paramCopies[0].pUserParams; break; @@ -869,66 +1000,88 @@ NV_STATUS embeddedParamCopyOut(RMAPI_PARAM_COPY *paramCopies, RmCtrlParams *pRmC #endif case NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS); + status = rmapiParamsRelease(¶mCopies[0]); ((NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS*)pParams)->busPeerIds = paramCopies[0].pUserParams; break; } case NV0080_CTRL_CMD_FB_GET_CAPS: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV0080_CTRL_FB_GET_CAPS_PARAMS); + status = rmapiParamsRelease(¶mCopies[0]); ((NV0080_CTRL_FB_GET_CAPS_PARAMS*)pParams)->capsTbl = paramCopies[0].pUserParams; break; } case NV0080_CTRL_CMD_GPU_GET_CLASSLIST: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS); + status = rmapiParamsRelease(¶mCopies[0]); ((NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS*)pParams)->classList = paramCopies[0].pUserParams; break; } case NV2080_CTRL_CMD_GPU_GET_ENGINE_CLASSLIST: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS); + status = rmapiParamsRelease(¶mCopies[0]); ((NV2080_CTRL_GPU_GET_ENGINE_CLASSLIST_PARAMS*)pParams)->classList = paramCopies[0].pUserParams; break; } case NV0080_CTRL_CMD_GR_GET_CAPS: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV0080_CTRL_GR_GET_CAPS_PARAMS); + status = rmapiParamsRelease(¶mCopies[0]); ((NV0080_CTRL_GR_GET_CAPS_PARAMS*)pParams)->capsTbl = paramCopies[0].pUserParams; break; } case NV2080_CTRL_CMD_I2C_ACCESS: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV2080_CTRL_I2C_ACCESS_PARAMS); + status = rmapiParamsRelease(¶mCopies[0]); ((NV2080_CTRL_I2C_ACCESS_PARAMS*)pParams)->data = paramCopies[0].pUserParams; break; } case NV2080_CTRL_CMD_GR_GET_INFO: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV2080_CTRL_GR_GET_INFO_PARAMS); + status = rmapiParamsRelease(¶mCopies[0]); ((NV2080_CTRL_GR_GET_INFO_PARAMS*)pParams)->grInfoList = paramCopies[0].pUserParams; break; } case NVB06F_CTRL_CMD_MIGRATE_ENGINE_CTX_DATA: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NVB06F_CTRL_MIGRATE_ENGINE_CTX_DATA_PARAMS); + status = rmapiParamsRelease(¶mCopies[0]); ((NVB06F_CTRL_MIGRATE_ENGINE_CTX_DATA_PARAMS*)pParams)->pEngineCtxBuff = paramCopies[0].pUserParams; break; } case NVB06F_CTRL_CMD_GET_ENGINE_CTX_DATA: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS); + status = rmapiParamsRelease(¶mCopies[0]); ((NVB06F_CTRL_GET_ENGINE_CTX_DATA_PARAMS*)pParams)->pEngineCtxBuff = paramCopies[0].pUserParams; break; } case NV2080_CTRL_CMD_RC_READ_VIRTUAL_MEM: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS); + status = rmapiParamsRelease(¶mCopies[0]); ((NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS*)pRmCtrlParams->pParams)->bufferPtr = paramCopies[0].pUserParams; break; } case NV0080_CTRL_CMD_DMA_UPDATE_PDE_2: { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS); + status = rmapiParamsRelease(¶mCopies[0]); ((NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS*)pParams)->pPdeBuffer = paramCopies[0].pUserParams; diff --git a/src/nvidia/src/kernel/rmapi/entry_points.c b/src/nvidia/src/kernel/rmapi/entry_points.c index 5a2da8ac5..43414c877 100644 --- a/src/nvidia/src/kernel/rmapi/entry_points.c +++ b/src/nvidia/src/kernel/rmapi/entry_points.c @@ -53,12 +53,8 @@ static void _nv01AllocObject(NVOS05_PARAMETERS *pArgs, NvBool bUserModeArgs) static void _nv04AddVblankCallback(NVOS61_PARAMETERS *pArgs, NvBool bUserModeArgs) { RMAPI_DEPRECATED(RmDeprecatedAddVblankCallback, pArgs, bUserModeArgs); } static void _nv04AllocContextDma(NVOS39_PARAMETERS *pArgs, NvBool bUserModeArgs) { RMAPI_DEPRECATED(RmDeprecatedAllocContextDma, pArgs, bUserModeArgs); } static void _nv04BindContextDma(NVOS49_PARAMETERS *pArgs, NvBool bUserModeArgs) { RMAPI_DEPRECATED(RmDeprecatedBindContextDma, pArgs, bUserModeArgs); } -static void _nv04GetMemoryInfo(NVOS58_PARAMETERS *pArgs, NvBool bUserModeArgs) { RMAPI_NOT_SUPPORTED(pArgs); } static void _nv04I2CAccess(NVOS_I2C_ACCESS_PARAMS *pArgs, NvBool bUserModeArgs) { RMAPI_DEPRECATED(RmDeprecatedI2CAccess, pArgs, bUserModeArgs); } static void _nv04IdleChannels(NVOS30_PARAMETERS *pArgs, NvBool bUserModeArgs) { RMAPI_DEPRECATED(RmDeprecatedIdleChannels, pArgs, bUserModeArgs); } -static void _nv04MapMemoryDmaOffset(NVOS59_PARAMETERS *pArgs, NvBool bUserModeArgs) { RMAPI_NOT_SUPPORTED(pArgs); } -static void _nv04UnmapMemoryDmaOffset(NVOS60_PARAMETERS *pArgs, NvBool bUserModeArgs) { RMAPI_NOT_SUPPORTED(pArgs); } -static void _nv04UpdateContextDma(NVOS37_PARAMETERS *pArgs, NvBool bUserModeArgs) { RMAPI_NOT_SUPPORTED(pArgs); } static void _nv04VidHeapControl(NVOS32_PARAMETERS *pArgs, NvBool bUserModeArgs) { RMAPI_DEPRECATED(RmDeprecatedVidHeapControl, pArgs, bUserModeArgs); } static void _nv04AllocWithSecInfo(NVOS21_PARAMETERS*, API_SECURITY_INFO); @@ -94,16 +90,12 @@ void Nv04BindContextDma(NVOS49_PARAMETERS *pArgs) { _nv04BindC void Nv04Control(NVOS54_PARAMETERS *pArgs) { _nv04Control(pArgs, NV_TRUE, NV_FALSE); } void Nv04DupObject(NVOS55_PARAMETERS *pArgs) { _nv04DupObject(pArgs, NV_TRUE); } void Nv04Share(NVOS57_PARAMETERS *pArgs) { _nv04Share(pArgs, NV_TRUE); } -void Nv04GetMemoryInfo(NVOS58_PARAMETERS *pArgs) { _nv04GetMemoryInfo(pArgs, NV_TRUE); } void Nv04I2CAccess(NVOS_I2C_ACCESS_PARAMS *pArgs) { _nv04I2CAccess(pArgs, NV_TRUE); } void Nv04IdleChannels(NVOS30_PARAMETERS *pArgs) { _nv04IdleChannels(pArgs, NV_TRUE); } void Nv04MapMemory(NVOS33_PARAMETERS *pArgs) { _nv04MapMemory(pArgs, NV_TRUE, NV_FALSE); } void Nv04MapMemoryDma(NVOS46_PARAMETERS *pArgs) { _nv04MapMemoryDma(pArgs, NV_TRUE); } -void Nv04MapMemoryDmaOffset (NVOS59_PARAMETERS *pArgs) { _nv04MapMemoryDmaOffset(pArgs, NV_TRUE); } void Nv04UnmapMemory(NVOS34_PARAMETERS *pArgs) { _nv04UnmapMemory(pArgs, NV_TRUE, NV_FALSE); } void Nv04UnmapMemoryDma(NVOS47_PARAMETERS *pArgs) { _nv04UnmapMemoryDma(pArgs, NV_TRUE); } -void Nv04UnmapMemoryDmaOffset(NVOS60_PARAMETERS *pArgs) { _nv04UnmapMemoryDmaOffset(pArgs, NV_TRUE); } -void Nv04UpdateContextDma(NVOS37_PARAMETERS *pArgs) { _nv04UpdateContextDma(pArgs, NV_TRUE); } void Nv04VidHeapControl(NVOS32_PARAMETERS *pArgs) { _nv04VidHeapControl(pArgs, NV_TRUE); } void Nv01AllocMemoryUser(NVOS02_PARAMETERS *pArgs) { _nv01AllocMemory(pArgs, NV_TRUE); } @@ -117,16 +109,12 @@ void Nv04BindContextDmaUser(NVOS49_PARAMETERS *pArgs) { _nv04BindC void Nv04ControlUser(NVOS54_PARAMETERS *pArgs) { _nv04Control(pArgs, NV_TRUE, NV_FALSE); } void Nv04DupObjectUser(NVOS55_PARAMETERS *pArgs) { _nv04DupObject(pArgs, NV_TRUE); } void Nv04ShareUser(NVOS57_PARAMETERS *pArgs) { _nv04Share(pArgs, NV_TRUE); } -void Nv04GetMemoryInfoUser(NVOS58_PARAMETERS *pArgs) { _nv04GetMemoryInfo(pArgs, NV_TRUE); } void Nv04I2CAccessUser(NVOS_I2C_ACCESS_PARAMS *pArgs) { _nv04I2CAccess(pArgs, NV_TRUE); } void Nv04IdleChannelsUser(NVOS30_PARAMETERS *pArgs) { _nv04IdleChannels(pArgs, NV_TRUE); } void Nv04MapMemoryUser(NVOS33_PARAMETERS *pArgs) { _nv04MapMemory(pArgs, NV_TRUE, NV_FALSE); } void Nv04MapMemoryDmaUser(NVOS46_PARAMETERS *pArgs) { _nv04MapMemoryDma(pArgs, NV_TRUE); } -void Nv04MapMemoryDmaOffsetUser(NVOS59_PARAMETERS *pArgs) { _nv04MapMemoryDmaOffset(pArgs, NV_TRUE); } void Nv04UnmapMemoryUser(NVOS34_PARAMETERS *pArgs) { _nv04UnmapMemory(pArgs, NV_TRUE, NV_FALSE); } void Nv04UnmapMemoryDmaUser(NVOS47_PARAMETERS *pArgs) { _nv04UnmapMemoryDma(pArgs, NV_TRUE); } -void Nv04UnmapMemoryDmaOffsetUser(NVOS60_PARAMETERS *pArgs) { _nv04UnmapMemoryDmaOffset(pArgs, NV_TRUE); } -void Nv04UpdateContextDmaUser(NVOS37_PARAMETERS *pArgs) { _nv04UpdateContextDma(pArgs, NV_TRUE); } void Nv04VidHeapControlUser(NVOS32_PARAMETERS *pArgs) { _nv04VidHeapControl(pArgs, NV_TRUE); } void Nv01AllocMemoryKernel(NVOS02_PARAMETERS *pArgs) { _nv01AllocMemory(pArgs, NV_FALSE); } @@ -140,16 +128,12 @@ void Nv04BindContextDmaKernel(NVOS49_PARAMETERS *pArgs) { _nv04BindC void Nv04ControlKernel(NVOS54_PARAMETERS *pArgs) { _nv04Control(pArgs, NV_FALSE, NV_FALSE); } void Nv04DupObjectKernel(NVOS55_PARAMETERS *pArgs) { _nv04DupObject(pArgs, NV_FALSE); } void Nv04ShareKernel(NVOS57_PARAMETERS *pArgs) { _nv04Share(pArgs, NV_FALSE); } -void Nv04GetMemoryInfoKernel(NVOS58_PARAMETERS *pArgs) { _nv04GetMemoryInfo(pArgs, NV_FALSE); } void Nv04I2CAccessKernel(NVOS_I2C_ACCESS_PARAMS *pArgs) { _nv04I2CAccess(pArgs, NV_FALSE); } void Nv04IdleChannelsKernel(NVOS30_PARAMETERS *pArgs) { _nv04IdleChannels(pArgs, NV_FALSE); } void Nv04MapMemoryKernel(NVOS33_PARAMETERS *pArgs) { _nv04MapMemory(pArgs, NV_FALSE, NV_FALSE); } void Nv04MapMemoryDmaKernel(NVOS46_PARAMETERS *pArgs) { _nv04MapMemoryDma(pArgs, NV_FALSE); } -void Nv04MapMemoryDmaOffsetKernel(NVOS59_PARAMETERS *pArgs) { _nv04MapMemoryDmaOffset(pArgs, NV_FALSE); } void Nv04UnmapMemoryKernel(NVOS34_PARAMETERS *pArgs) { _nv04UnmapMemory(pArgs, NV_FALSE, NV_FALSE); } void Nv04UnmapMemoryDmaKernel(NVOS47_PARAMETERS *pArgs) { _nv04UnmapMemoryDma(pArgs, NV_FALSE); } -void Nv04UnmapMemoryDmaOffsetKernel(NVOS60_PARAMETERS *pArgs) { _nv04UnmapMemoryDmaOffset(pArgs, NV_FALSE); } -void Nv04UpdateContextDmaKernel(NVOS37_PARAMETERS *pArgs) { _nv04UpdateContextDma(pArgs, NV_FALSE); } void Nv04VidHeapControlKernel(NVOS32_PARAMETERS *pArgs) { _nv04VidHeapControl(pArgs, NV_FALSE); } // MODS-specific API functions which ignore RM locking model diff --git a/src/nvidia/src/kernel/rmapi/event.c b/src/nvidia/src/kernel/rmapi/event.c index 95b347d94..c444b2796 100644 --- a/src/nvidia/src/kernel/rmapi/event.c +++ b/src/nvidia/src/kernel/rmapi/event.c @@ -29,6 +29,10 @@ #include "core/locks.h" #include "rmapi/rs_utils.h" +#include "virtualization/kernel_hostvgpudeviceapi.h" + +#include "gpu/external_device/gsync_api.h" + #include "resserv/rs_client.h" #include "class/cl0005.h" @@ -56,6 +60,16 @@ eventConstruct_IMPL OBJGPU *pGpu = NULL; RS_PRIV_LEVEL privLevel = pParams->pSecInfo->privLevel; NvBool bUserOsEventHandle = NV_FALSE; + NvHandle hParentClient = pNv0050AllocParams->hParentClient; + + // + // Allow hParentClient being zero to imply the allocating client should be + // the parent client of this event. + // + if (hParentClient == NV01_NULL_OBJECT) + { + hParentClient = pRsClient->hClient; + } // never allow user mode/non-root clients to create ring0 callbacks as // we can not trust the function pointer (encoded in data). @@ -76,12 +90,12 @@ eventConstruct_IMPL } #if (!NV_RM_STUB_RPC) - if (_eventRpcForType(pNv0050AllocParams->hParentClient, pNv0050AllocParams->hSrcResource)) + if (_eventRpcForType(hParentClient, pNv0050AllocParams->hSrcResource)) { RsResourceRef *pSrcRef; NV_STATUS tmpStatus; - tmpStatus = serverutilGetResourceRef(pNv0050AllocParams->hParentClient, + tmpStatus = serverutilGetResourceRef(hParentClient, pNv0050AllocParams->hSrcResource, &pSrcRef); @@ -105,7 +119,7 @@ eventConstruct_IMPL // add event to client and parent object rmStatus = eventInit(pEvent, pCallContext, - pNv0050AllocParams->hParentClient, + hParentClient, pNv0050AllocParams->hSrcResource, &ppEventNotification); if (rmStatus == NV_OK) @@ -130,12 +144,13 @@ eventConstruct_IMPL if (IS_GSP_CLIENT(pGpu)) { NV_ASSERT_OK_OR_RETURN( - serverutilGetResourceRef(pNv0050AllocParams->hParentClient, + serverutilGetResourceRef(hParentClient, pNv0050AllocParams->hSrcResource, &pSourceRef)); } if ( + !(IS_GSP_CLIENT(pGpu) && (pSourceRef->internalClassId == classId(KernelHostVgpuDeviceApi))) && (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || (IS_GSP_CLIENT(pGpu) && pSourceRef->internalClassId != classId(ContextDma)) || (IS_VIRTUAL_WITH_SRIOV(pGpu) && !(pNv0050AllocParams->notifyIndex & NV01_EVENT_NONSTALL_INTR)))) @@ -301,6 +316,28 @@ NV_STATUS notifyUnregisterEvent_IMPL } + // Gsync needs special event handling (ugh). + // + GSyncApi *pGSyncApi = dynamicCast(pNotifier, GSyncApi); + if (pGSyncApi != NULL) + { + NvU32 eventNum; + + // check all events bound to this gsync object + for (eventNum = 0; eventNum < NV30F1_CTRL_GSYNC_EVENT_TYPES; eventNum++) + { + if ((pGSyncApi->pEventByType[eventNum]) && + (pGSyncApi->pEventByType[eventNum]->hEventClient == hEventClient) && + (pGSyncApi->pEventByType[eventNum]->hEvent == hEvent)) + { + unregisterEventNotification(&pGSyncApi->pEventByType[eventNum], + hEventClient, + hNotifierResource, + hEvent); + } + } + } + return status; } @@ -619,6 +656,7 @@ _eventRpcForType(NvHandle hClient, NvHandle hObject) } if (objDynamicCastById(pResourceRef->pResource, classId(Subdevice)) || + objDynamicCastById(pResourceRef->pResource, classId(KernelHostVgpuDeviceApi)) || objDynamicCastById(pResourceRef->pResource, classId(ChannelDescendant)) || objDynamicCastById(pResourceRef->pResource, classId(ContextDma)) || objDynamicCastById(pResourceRef->pResource, classId(DispChannel)) || diff --git a/src/nvidia/src/kernel/rmapi/event_notification.c b/src/nvidia/src/kernel/rmapi/event_notification.c index 6ff69b172..a5f3c726a 100644 --- a/src/nvidia/src/kernel/rmapi/event_notification.c +++ b/src/nvidia/src/kernel/rmapi/event_notification.c @@ -37,9 +37,12 @@ #include "gpu/subdevice/subdevice.h" #include "rmapi/rs_utils.h" #include "mem_mgr/mem.h" +#include "kernel/gpu/gpu_engine_type.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" +#include "virtualization/hypervisor/hypervisor.h" + static NV_STATUS _insertEventNotification ( PEVENTNOTIFICATION *ppEventNotification, @@ -70,7 +73,7 @@ static NV_STATUS _removeEventNotification static NV_STATUS engineNonStallEventOp ( OBJGPU *pGpu, - NvU32 engineId, + RM_ENGINE_TYPE rmEngineId, PEVENTNOTIFICATION pEventNotify, Memory *pMemory, NvBool bInsert @@ -87,30 +90,30 @@ static NV_STATUS engineNonStallEventOp return NV_ERR_NO_MEMORY; // Acquire engine list spinlock before adding to engine event list - portSyncSpinlockAcquire(pGpu->engineNonstallIntr[engineId].pSpinlock); - pTempNode->pNext = pGpu->engineNonstallIntr[engineId].pEventNode; + portSyncSpinlockAcquire(pGpu->engineNonstallIntr[rmEngineId].pSpinlock); + pTempNode->pNext = pGpu->engineNonstallIntr[rmEngineId].pEventNode; pTempNode->pEventNotify = pEventNotify; pTempNode->pMemory = pMemory; - pGpu->engineNonstallIntr[engineId].pEventNode = pTempNode; + pGpu->engineNonstallIntr[rmEngineId].pEventNode = pTempNode; // Release engine list spinlock - portSyncSpinlockRelease(pGpu->engineNonstallIntr[engineId].pSpinlock); + portSyncSpinlockRelease(pGpu->engineNonstallIntr[rmEngineId].pSpinlock); } else { ENGINE_EVENT_NODE *pEngNode, *pPrevNode = NULL; // Acquire engine list spinlock before traversing engine event list - portSyncSpinlockAcquire(pGpu->engineNonstallIntr[engineId].pSpinlock); + portSyncSpinlockAcquire(pGpu->engineNonstallIntr[rmEngineId].pSpinlock); - pEngNode = pGpu->engineNonstallIntr[engineId].pEventNode; + pEngNode = pGpu->engineNonstallIntr[rmEngineId].pEventNode; while (pEngNode) { if (pEngNode->pEventNotify == pEventNotify) { if (pPrevNode == NULL) - pGpu->engineNonstallIntr[engineId].pEventNode = pEngNode->pNext; + pGpu->engineNonstallIntr[rmEngineId].pEventNode = pEngNode->pNext; else pPrevNode->pNext = pEngNode->pNext; @@ -126,7 +129,7 @@ static NV_STATUS engineNonStallEventOp } // Release engine list spinlock - portSyncSpinlockRelease(pGpu->engineNonstallIntr[engineId].pSpinlock); + portSyncSpinlockRelease(pGpu->engineNonstallIntr[rmEngineId].pSpinlock); if (bFound) { @@ -142,7 +145,7 @@ static NV_STATUS engineNonStallEventOp return NV_OK; } -static NV_STATUS _engineNonStallIntrNotifyImpl(OBJGPU *pGpu, NvU32 engineId, NvHandle hEvent) +static NV_STATUS _engineNonStallIntrNotifyImpl(OBJGPU *pGpu, RM_ENGINE_TYPE rmEngineId, NvHandle hEvent) { ENGINE_EVENT_NODE *pTempHead; Memory *pSemMemory; @@ -155,9 +158,9 @@ static NV_STATUS _engineNonStallIntrNotifyImpl(OBJGPU *pGpu, NvU32 engineId, NvH // is called without holding locks from ISR for Linux. This spinlock is used // to protect per GPU per engine event node list. // - portSyncSpinlockAcquire(pGpu->engineNonstallIntr[engineId].pSpinlock); + portSyncSpinlockAcquire(pGpu->engineNonstallIntr[rmEngineId].pSpinlock); - pTempHead = pGpu->engineNonstallIntr[engineId].pEventNode; + pTempHead = pGpu->engineNonstallIntr[rmEngineId].pEventNode; while (pTempHead) { if (!pTempHead->pEventNotify) @@ -191,12 +194,33 @@ static NV_STATUS _engineNonStallIntrNotifyImpl(OBJGPU *pGpu, NvU32 engineId, NvH pSemMemory->vgpuNsIntr.nsSemValue = semValue; + { + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys); + + if (pHypervisor != NULL) + { + NV_STATUS intrStatus = hypervisorInjectInterrupt(pHypervisor, &pSemMemory->vgpuNsIntr); + + // + // If we have successfully inject MSI into guest, + // then we can jump to the next semaphore location, + // otherwise, we need to call osNotifyEvent below to + // wake up plugin + // + if (intrStatus == NV_OK) + { + pTempHead = pTempHead->pNext; + continue; + } + } + } } if (osNotifyEvent(pGpu, pTempHead->pEventNotify, 0, 0, NV_OK) != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "failed to notify event for engine 0x%x\n", - engineId); + NV_PRINTF(LEVEL_ERROR, "failed to notify event for engine 0x%x (0x%x)\n", + gpuGetNv2080EngineType(rmEngineId), rmEngineId); NV_ASSERT(0); rmStatus = NV_ERR_INVALID_STATE; break; @@ -206,166 +230,166 @@ static NV_STATUS _engineNonStallIntrNotifyImpl(OBJGPU *pGpu, NvU32 engineId, NvH pTempHead = pTempHead->pNext; } - portSyncSpinlockRelease(pGpu->engineNonstallIntr[engineId].pSpinlock); + portSyncSpinlockRelease(pGpu->engineNonstallIntr[rmEngineId].pSpinlock); return rmStatus; } NV_STATUS -engineNonStallIntrNotify(OBJGPU *pGpu, NvU32 engineId) +engineNonStallIntrNotify(OBJGPU *pGpu, RM_ENGINE_TYPE rmEngineId) { - return _engineNonStallIntrNotifyImpl(pGpu, engineId, 0); + return _engineNonStallIntrNotifyImpl(pGpu, rmEngineId, 0); } NV_STATUS -engineNonStallIntrNotifyEvent(OBJGPU *pGpu, NvU32 engineId, NvHandle hEvent) +engineNonStallIntrNotifyEvent(OBJGPU *pGpu, RM_ENGINE_TYPE rmEngineId, NvHandle hEvent) { - return _engineNonStallIntrNotifyImpl(pGpu, engineId, hEvent); + return _engineNonStallIntrNotifyImpl(pGpu, rmEngineId, hEvent); } static NV_STATUS eventGetEngineTypeFromSubNotifyIndex ( NvU32 notifyIndex, - NvU32 *engineIdx + RM_ENGINE_TYPE *pRmEngineId ) { - NV_ASSERT_OR_RETURN(engineIdx, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pRmEngineId, NV_ERR_INVALID_ARGUMENT); - *engineIdx = NV2080_ENGINE_TYPE_NULL; + *pRmEngineId = RM_ENGINE_TYPE_NULL; switch (notifyIndex) { case NV2080_NOTIFIERS_FIFO_EVENT_MTHD: - *engineIdx = NV2080_ENGINE_TYPE_HOST; + *pRmEngineId = RM_ENGINE_TYPE_HOST; break; case NV2080_NOTIFIERS_CE0: - *engineIdx = NV2080_ENGINE_TYPE_COPY0; + *pRmEngineId = RM_ENGINE_TYPE_COPY0; break; case NV2080_NOTIFIERS_CE1: - *engineIdx = NV2080_ENGINE_TYPE_COPY1; + *pRmEngineId = RM_ENGINE_TYPE_COPY1; break; case NV2080_NOTIFIERS_CE2: - *engineIdx = NV2080_ENGINE_TYPE_COPY2; + *pRmEngineId = RM_ENGINE_TYPE_COPY2; break; case NV2080_NOTIFIERS_CE3: - *engineIdx = NV2080_ENGINE_TYPE_COPY3; + *pRmEngineId = RM_ENGINE_TYPE_COPY3; break; case NV2080_NOTIFIERS_CE4: - *engineIdx = NV2080_ENGINE_TYPE_COPY4; + *pRmEngineId = RM_ENGINE_TYPE_COPY4; break; case NV2080_NOTIFIERS_CE5: - *engineIdx = NV2080_ENGINE_TYPE_COPY5; + *pRmEngineId = RM_ENGINE_TYPE_COPY5; break; case NV2080_NOTIFIERS_CE6: - *engineIdx = NV2080_ENGINE_TYPE_COPY6; + *pRmEngineId = RM_ENGINE_TYPE_COPY6; break; case NV2080_NOTIFIERS_CE7: - *engineIdx = NV2080_ENGINE_TYPE_COPY7; + *pRmEngineId = RM_ENGINE_TYPE_COPY7; break; case NV2080_NOTIFIERS_CE8: - *engineIdx = NV2080_ENGINE_TYPE_COPY8; + *pRmEngineId = RM_ENGINE_TYPE_COPY8; break; case NV2080_NOTIFIERS_CE9: - *engineIdx = NV2080_ENGINE_TYPE_COPY9; + *pRmEngineId = RM_ENGINE_TYPE_COPY9; break; case NV2080_NOTIFIERS_GR0: - *engineIdx = NV2080_ENGINE_TYPE_GR0; + *pRmEngineId = RM_ENGINE_TYPE_GR0; break; case NV2080_NOTIFIERS_GR1: - *engineIdx = NV2080_ENGINE_TYPE_GR1; + *pRmEngineId = RM_ENGINE_TYPE_GR1; break; case NV2080_NOTIFIERS_GR2: - *engineIdx = NV2080_ENGINE_TYPE_GR2; + *pRmEngineId = RM_ENGINE_TYPE_GR2; break; case NV2080_NOTIFIERS_GR3: - *engineIdx = NV2080_ENGINE_TYPE_GR3; + *pRmEngineId = RM_ENGINE_TYPE_GR3; break; case NV2080_NOTIFIERS_GR4: - *engineIdx = NV2080_ENGINE_TYPE_GR4; + *pRmEngineId = RM_ENGINE_TYPE_GR4; break; case NV2080_NOTIFIERS_GR5: - *engineIdx = NV2080_ENGINE_TYPE_GR5; + *pRmEngineId = RM_ENGINE_TYPE_GR5; break; case NV2080_NOTIFIERS_GR6: - *engineIdx = NV2080_ENGINE_TYPE_GR6; + *pRmEngineId = RM_ENGINE_TYPE_GR6; break; case NV2080_NOTIFIERS_GR7: - *engineIdx = NV2080_ENGINE_TYPE_GR7; + *pRmEngineId = RM_ENGINE_TYPE_GR7; break; case NV2080_NOTIFIERS_PPP: - *engineIdx = NV2080_ENGINE_TYPE_PPP; + *pRmEngineId = RM_ENGINE_TYPE_PPP; break; case NV2080_NOTIFIERS_NVDEC0: - *engineIdx = NV2080_ENGINE_TYPE_NVDEC0; + *pRmEngineId = RM_ENGINE_TYPE_NVDEC0; break; case NV2080_NOTIFIERS_NVDEC1: - *engineIdx = NV2080_ENGINE_TYPE_NVDEC1; + *pRmEngineId = RM_ENGINE_TYPE_NVDEC1; break; case NV2080_NOTIFIERS_NVDEC2: - *engineIdx = NV2080_ENGINE_TYPE_NVDEC2; + *pRmEngineId = RM_ENGINE_TYPE_NVDEC2; break; case NV2080_NOTIFIERS_NVDEC3: - *engineIdx = NV2080_ENGINE_TYPE_NVDEC3; + *pRmEngineId = RM_ENGINE_TYPE_NVDEC3; break; case NV2080_NOTIFIERS_NVDEC4: - *engineIdx = NV2080_ENGINE_TYPE_NVDEC4; + *pRmEngineId = RM_ENGINE_TYPE_NVDEC4; break; case NV2080_NOTIFIERS_NVDEC5: - *engineIdx = NV2080_ENGINE_TYPE_NVDEC5; + *pRmEngineId = RM_ENGINE_TYPE_NVDEC5; break; case NV2080_NOTIFIERS_NVDEC6: - *engineIdx = NV2080_ENGINE_TYPE_NVDEC6; + *pRmEngineId = RM_ENGINE_TYPE_NVDEC6; break; case NV2080_NOTIFIERS_NVDEC7: - *engineIdx = NV2080_ENGINE_TYPE_NVDEC7; + *pRmEngineId = RM_ENGINE_TYPE_NVDEC7; break; case NV2080_NOTIFIERS_PDEC: - *engineIdx = NV2080_ENGINE_TYPE_VP; + *pRmEngineId = RM_ENGINE_TYPE_VP; break; case NV2080_NOTIFIERS_MSENC: NV_ASSERT(NV2080_NOTIFIERS_MSENC == NV2080_NOTIFIERS_NVENC0); - NV_ASSERT(NV2080_ENGINE_TYPE_MSENC == NV2080_ENGINE_TYPE_NVENC0); - *engineIdx = NV2080_ENGINE_TYPE_MSENC; + NV_ASSERT(RM_ENGINE_TYPE_MSENC == RM_ENGINE_TYPE_NVENC0); + *pRmEngineId = RM_ENGINE_TYPE_MSENC; break; case NV2080_NOTIFIERS_NVENC1: - *engineIdx = NV2080_ENGINE_TYPE_NVENC1; + *pRmEngineId = RM_ENGINE_TYPE_NVENC1; break; case NV2080_NOTIFIERS_NVENC2: - *engineIdx = NV2080_ENGINE_TYPE_NVENC2; + *pRmEngineId = RM_ENGINE_TYPE_NVENC2; break; case NV2080_NOTIFIERS_SEC2: - *engineIdx = NV2080_ENGINE_TYPE_SEC2; + *pRmEngineId = RM_ENGINE_TYPE_SEC2; break; case NV2080_NOTIFIERS_NVJPEG0: - *engineIdx = NV2080_ENGINE_TYPE_NVJPEG0; + *pRmEngineId = RM_ENGINE_TYPE_NVJPEG0; break; case NV2080_NOTIFIERS_NVJPEG1: - *engineIdx = NV2080_ENGINE_TYPE_NVJPEG1; + *pRmEngineId = RM_ENGINE_TYPE_NVJPEG1; break; case NV2080_NOTIFIERS_NVJPEG2: - *engineIdx = NV2080_ENGINE_TYPE_NVJPEG2; + *pRmEngineId = RM_ENGINE_TYPE_NVJPEG2; break; case NV2080_NOTIFIERS_NVJPEG3: - *engineIdx = NV2080_ENGINE_TYPE_NVJPEG3; + *pRmEngineId = RM_ENGINE_TYPE_NVJPEG3; break; case NV2080_NOTIFIERS_NVJPEG4: - *engineIdx = NV2080_ENGINE_TYPE_NVJPEG4; + *pRmEngineId = RM_ENGINE_TYPE_NVJPEG4; break; case NV2080_NOTIFIERS_NVJPEG5: - *engineIdx = NV2080_ENGINE_TYPE_NVJPEG5; + *pRmEngineId = RM_ENGINE_TYPE_NVJPEG5; break; case NV2080_NOTIFIERS_NVJPEG6: - *engineIdx = NV2080_ENGINE_TYPE_NVJPEG6; + *pRmEngineId = RM_ENGINE_TYPE_NVJPEG6; break; case NV2080_NOTIFIERS_NVJPEG7: - *engineIdx = NV2080_ENGINE_TYPE_NVJPEG7; + *pRmEngineId = RM_ENGINE_TYPE_NVJPEG7; break; case NV2080_NOTIFIERS_OFA: - *engineIdx = NV2080_ENGINE_TYPE_OFA; + *pRmEngineId = RM_ENGINE_TYPE_OFA; break; default: NV_PRINTF(LEVEL_WARNING, - "engine 0x%x doesn't use the fast non-stall interrupt path!\n", + "notifier 0x%x doesn't use the fast non-stall interrupt path!\n", notifyIndex); NV_ASSERT(0); return NV_ERR_NOT_SUPPORTED; @@ -391,7 +415,7 @@ NV_STATUS registerEventNotification NV_STATUS rmStatus = NV_OK, rmTmpStatus = NV_OK; OBJGPU *pGpu; NvBool bNonStallIntrEvent = NV_FALSE; - NvU32 engineId; + RM_ENGINE_TYPE rmEngineId; NvHandle hDevice; RsResourceRef *pResourceRef; Memory *pSemMemory = NULL; @@ -427,7 +451,7 @@ NV_STATUS registerEventNotification } rmStatus = eventGetEngineTypeFromSubNotifyIndex( - DRF_VAL(0005, _NOTIFY_INDEX, _INDEX, NotifyIndex), &engineId); + DRF_VAL(0005, _NOTIFY_INDEX, _INDEX, NotifyIndex), &rmEngineId); if (rmStatus != NV_OK) goto free_entry; @@ -435,7 +459,7 @@ NV_STATUS registerEventNotification if (IS_MIG_IN_USE(pGpu)) { KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); - NvU32 globalEngineId = engineId; + RM_ENGINE_TYPE globalRmEngineId = rmEngineId; MIG_INSTANCE_REF ref; NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_ERROR, @@ -443,10 +467,10 @@ NV_STATUS registerEventNotification free_entry); NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_ERROR, - kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, engineId, &globalEngineId), + kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, rmEngineId, &globalRmEngineId), free_entry); - engineId = globalEngineId; + rmEngineId = globalRmEngineId; } if (pSubDevice->hSemMemory != NV01_NULL_OBJECT) @@ -458,7 +482,7 @@ NV_STATUS registerEventNotification free_entry); } - rmStatus = engineNonStallEventOp(pGpu, engineId, + rmStatus = engineNonStallEventOp(pGpu, rmEngineId, *ppEventNotification, pSemMemory, NV_TRUE); if (rmStatus != NV_OK) @@ -607,7 +631,7 @@ NV_STATUS unregisterEventNotificationWithData Subdevice *pSubDevice; RsResourceRef *pResourceRef; NvHandle hDevice; - NvU32 engineId; + RM_ENGINE_TYPE rmEngineId; OBJGPU *pGpu; rmStatus = _removeEventNotification(ppEventNotification, hEventClient, @@ -638,7 +662,7 @@ NV_STATUS unregisterEventNotificationWithData goto free_entry; } - rmStatus = eventGetEngineTypeFromSubNotifyIndex(pTargetEvent->NotifyIndex, &engineId); + rmStatus = eventGetEngineTypeFromSubNotifyIndex(pTargetEvent->NotifyIndex, &rmEngineId); if (rmStatus != NV_OK) goto free_entry; @@ -646,7 +670,7 @@ NV_STATUS unregisterEventNotificationWithData if (IS_MIG_IN_USE(pGpu)) { KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); - NvU32 globalEngineId = engineId; + RM_ENGINE_TYPE globalRmEngineId = rmEngineId; MIG_INSTANCE_REF ref; NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_ERROR, @@ -654,13 +678,13 @@ NV_STATUS unregisterEventNotificationWithData free_entry); NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_ERROR, - kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, engineId, &globalEngineId), + kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, rmEngineId, &globalRmEngineId), free_entry); - engineId = globalEngineId; + rmEngineId = globalRmEngineId; } - rmStatus = engineNonStallEventOp(pGpu, engineId, + rmStatus = engineNonStallEventOp(pGpu, rmEngineId, pTargetEvent, NULL, NV_FALSE); } diff --git a/src/nvidia/src/kernel/rmapi/mapping_cpu.c b/src/nvidia/src/kernel/rmapi/mapping_cpu.c index 682feae1c..98d784479 100644 --- a/src/nvidia/src/kernel/rmapi/mapping_cpu.c +++ b/src/nvidia/src/kernel/rmapi/mapping_cpu.c @@ -189,6 +189,8 @@ memMap_IMPL NvBool bBroadcast; NvU64 mapLimit; NvBool bIsSysmem = NV_FALSE; + NvBool bSkipSizeCheck = (DRF_VAL(OS33, _FLAGS, _SKIP_SIZE_CHECK, pMapParams->flags) == + NVOS33_FLAGS_SKIP_SIZE_CHECK_ENABLE); NV_ASSERT_OR_RETURN(RMCFG_FEATURE_KERNEL_RM, NV_ERR_NOT_SUPPORTED); @@ -255,9 +257,8 @@ memMap_IMPL // actual allocation size (to PAGE_SIZE+1) because of a buggy ms function so // skip the allocation size sanity check so the map operation still succeeds. // - if ((DRF_VAL(OS33, _FLAGS, _SKIP_SIZE_CHECK, pMapParams->flags) == NVOS33_FLAGS_SKIP_SIZE_CHECK_DISABLE) && - (!portSafeAddU64(pMapParams->offset, pMapParams->length, &mapLimit) || - (mapLimit > pMemoryInfo->Length))) + if (!bSkipSizeCheck && (!portSafeAddU64(pMapParams->offset, pMapParams->length, &mapLimit) || + (mapLimit > pMemoryInfo->Length))) { return NV_ERR_INVALID_LIMIT; } @@ -437,6 +438,7 @@ memMap_IMPL { busMapFbFlags |= BUS_MAP_FB_FLAGS_DISABLE_ENCRYPTION; } + switch (pMapParams->protect) { case NV_PROTECT_READABLE: @@ -449,6 +451,13 @@ memMap_IMPL pMemDesc = memdescGetMemDescFromGpu(pMemDesc, pGpu); + // WAR for Bug 3564398, need to allocate doorbell for windows differently + if (RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM && + memdescGetFlag(pMemDesc, MEMDESC_FLAGS_MAP_SYSCOH_OVER_BAR1)) + { + busMapFbFlags |= BUS_MAP_FB_FLAGS_MAP_DOWNWARDS; + } + rmStatus = kbusMapFbAperture_HAL(pGpu, pKernelBus, pMemDesc, pMapParams->offset, &gpuVirtAddr, &gpuMapLength, diff --git a/src/nvidia/src/kernel/rmapi/mapping_list.c b/src/nvidia/src/kernel/rmapi/mapping_list.c index a7d834928..3e93bd79c 100644 --- a/src/nvidia/src/kernel/rmapi/mapping_list.c +++ b/src/nvidia/src/kernel/rmapi/mapping_list.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -151,7 +151,7 @@ intermapCreateDmaMapping portMemSet(pDmaMapping, 0, sizeof(CLI_DMA_MAPPING_INFO)); pDmaMapping->hDevice = hDevice; pDmaMapping->DmaOffset = 0; - pDmaMapping->pP2PInfo = NULL; + pDmaMapping->bP2P = NV_FALSE; pDmaMapping->Flags = flags; // NV0S46_* pDmaMapping->addressTranslation = VAS_ADDRESS_TRANSLATION(pVAS); diff --git a/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c b/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c index c97007f67..df2247db7 100644 --- a/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c +++ b/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c @@ -65,9 +65,9 @@ #include #include #include -#include -#include -#include +#include // HOPPER_USERMODE_A +#include // HOPPER_DMA_COPY_A +#include // HOPPER_COMPUTE_A #include #include @@ -125,7 +125,6 @@ #include - #define NV_GPU_OPS_NUM_GPFIFO_ENTRIES_DEFAULT 1024 #define NV_GPU_SMALL_PAGESIZE (4 * 1024) @@ -270,7 +269,7 @@ struct gpuChannel UVM_GPU_CHANNEL_ENGINE_TYPE engineType; // If engineType is CE, engineIndex is a zero-based offset from - // NV2080_ENGINE_TYPE_COPY0. If engineType is GR, engineIndex is a + // RM_ENGINE_TYPE_COPY0. If engineType is GR, engineIndex is a // zero-based offset from NV2080_ENGINE_TYPE_GR0. NvU32 engineIndex; struct gpuAddressSpace *vaSpace; @@ -337,7 +336,7 @@ struct allocFlags struct ChannelAllocInfo { - NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS gpFifoAllocParams; + NV_CHANNEL_ALLOC_PARAMS gpFifoAllocParams; gpuAllocInfo gpuAllocInfo; }; @@ -457,7 +456,7 @@ static void _nvGpuOpsLocksRelease(nvGpuOpsLockSet *acquiredLocks) if (acquiredLocks->isRmLockAcquired == NV_TRUE) { - rmApiLockRelease(); + rmapiLockRelease(); acquiredLocks->isRmLockAcquired = NV_FALSE; } @@ -499,7 +498,7 @@ static NV_STATUS _nvGpuOpsLocksAcquire(NvU32 rmApiLockFlags, } acquiredLocks->isRmSemaAcquired = NV_TRUE; - status = rmApiLockAcquire(rmApiLockFlags, RM_LOCK_MODULES_GPU_OPS); + status = rmapiLockAcquire(rmApiLockFlags, RM_LOCK_MODULES_GPU_OPS); if (status != NV_OK) { _nvGpuOpsLocksRelease(acquiredLocks); @@ -1012,14 +1011,17 @@ static void gpuDeviceRmSubDeviceDeinitEcc(struct gpuDevice *device) static NV_STATUS gpuDeviceRmSubDeviceInitEcc(struct gpuDevice *device) { NV_STATUS status = NV_OK; - int i = 0; + NvU32 i = 0; int tempPtr = 0; - NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS eccStatusParams; - NV90E6_CTRL_MASTER_GET_ECC_INTR_OFFSET_MASK_PARAMS eccMaskParams = {0}; - NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS errContIntrMaskParams = {0}; - NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS eventDbeParams = {0}; - NV0005_ALLOC_PARAMETERS allocDbeParams = {0}; + struct + { + NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS eccStatus; + NV90E6_CTRL_MASTER_GET_ECC_INTR_OFFSET_MASK_PARAMS eccMask; + NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS errContIntrMask; + NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS eventDbe; + NV0005_ALLOC_PARAMETERS allocDbe; + } *pParams = NULL; OBJGPU *pGpu = NULL; NvBool supportedOnAnyUnits = NV_FALSE; subDeviceDesc *rmSubDevice = device->rmSubDevice; @@ -1036,8 +1038,6 @@ static NV_STATUS gpuDeviceRmSubDeviceInitEcc(struct gpuDevice *device) if (status != NV_OK) return status; - portMemSet(&eccStatusParams, 0, sizeof(eccStatusParams)); - rmSubDevice->eccOffset = 0; rmSubDevice->eccMask = 0; rmSubDevice->eccReadLocation = NULL; @@ -1051,23 +1051,32 @@ static NV_STATUS gpuDeviceRmSubDeviceInitEcc(struct gpuDevice *device) if (IS_MIG_IN_USE(pGpu) && rmSubDevice->smcPartition.info == NULL) return NV_OK; + pParams = portMemAllocNonPaged(sizeof(*pParams)); + if (pParams == NULL) + { + return NV_ERR_NO_MEMORY; + } + + portMemSet(pParams, 0, sizeof(*pParams)); + // Check ECC before doing anything here status = pRmApi->Control(pRmApi, device->session->handle, device->subhandle, NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS, - &eccStatusParams, - sizeof(eccStatusParams)); + &pParams->eccStatus, + sizeof(pParams->eccStatus)); if (status == NV_ERR_NOT_SUPPORTED) { // Nothing to do if ECC not supported rmSubDevice->bEccEnabled = NV_FALSE; - goto success; + status = NV_OK; + goto done; } else if (status != NV_OK) { - return status; + goto done; } // @@ -1079,10 +1088,10 @@ static NV_STATUS gpuDeviceRmSubDeviceInitEcc(struct gpuDevice *device) for (i = 0; i < NV2080_CTRL_GPU_ECC_UNIT_COUNT; i++) { // Check the ECC status only on the units supported by HW - if (eccStatusParams.units[i].supported) + if (pParams->eccStatus.units[i].supported) { supportedOnAnyUnits = NV_TRUE; - if (!eccStatusParams.units[i].enabled) + if (!pParams->eccStatus.units[i].enabled) rmSubDevice->bEccEnabled = NV_FALSE; } } @@ -1093,7 +1102,8 @@ static NV_STATUS gpuDeviceRmSubDeviceInitEcc(struct gpuDevice *device) if (!rmSubDevice->bEccEnabled) { // ECC not enabled, early-out - goto success; + status = NV_OK; + goto done; } //Allocate memory for interrupt tree @@ -1104,7 +1114,7 @@ static NV_STATUS gpuDeviceRmSubDeviceInitEcc(struct gpuDevice *device) GF100_SUBDEVICE_MASTER, &tempPtr); if (status != NV_OK) - goto error; + goto done; if (isDeviceTuringPlus(device)) { @@ -1113,13 +1123,13 @@ static NV_STATUS gpuDeviceRmSubDeviceInitEcc(struct gpuDevice *device) device->session->handle, rmSubDevice->eccMasterHandle, NV90E6_CTRL_CMD_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK, - &errContIntrMaskParams, - sizeof(errContIntrMaskParams)); + &pParams->errContIntrMask, + sizeof(pParams->errContIntrMask)); if (status != NV_OK) - goto error; + goto done; rmSubDevice->eccOffset = GPU_GET_VREG_OFFSET(pGpu, NV_VIRTUAL_FUNCTION_ERR_CONT); - rmSubDevice->eccMask = errContIntrMaskParams.eccMask; + rmSubDevice->eccMask = pParams->errContIntrMask.eccMask; } else { @@ -1132,7 +1142,7 @@ static NV_STATUS gpuDeviceRmSubDeviceInitEcc(struct gpuDevice *device) (void **)(&rmSubDevice->eccReadLocation), DRF_DEF(OS33, _FLAGS, _ACCESS, _READ_ONLY)); if (status != NV_OK) - goto error; + goto done; NV_ASSERT(rmSubDevice->eccReadLocation); @@ -1140,53 +1150,55 @@ static NV_STATUS gpuDeviceRmSubDeviceInitEcc(struct gpuDevice *device) device->session->handle, rmSubDevice->eccMasterHandle, NV90E6_CTRL_CMD_MASTER_GET_ECC_INTR_OFFSET_MASK, - (void *)&eccMaskParams, - sizeof(eccMaskParams)); + &pParams->eccMask, + sizeof(pParams->eccMask)); if (status != NV_OK) - goto error; + goto done; // Fill the mask and offset which has been read from control call - rmSubDevice->eccOffset = eccMaskParams.offset; - rmSubDevice->eccMask = eccMaskParams.mask; + rmSubDevice->eccOffset = pParams->eccMask.offset; + rmSubDevice->eccMask = pParams->eccMask.mask; } // Setup callback for ECC DBE rmSubDevice->eccDbeCallback.func = eccErrorCallback; rmSubDevice->eccDbeCallback.arg = rmSubDevice; - allocDbeParams.hParentClient = device->session->handle; - allocDbeParams.hClass = NV01_EVENT_KERNEL_CALLBACK_EX; - allocDbeParams.notifyIndex = NV2080_NOTIFIERS_ECC_DBE; - allocDbeParams.data = NV_PTR_TO_NvP64(&rmSubDevice->eccDbeCallback); + pParams->allocDbe.hParentClient = device->session->handle; + pParams->allocDbe.hClass = NV01_EVENT_KERNEL_CALLBACK_EX; + pParams->allocDbe.notifyIndex = NV2080_NOTIFIERS_ECC_DBE; + pParams->allocDbe.data = NV_PTR_TO_NvP64(&rmSubDevice->eccDbeCallback); rmSubDevice->eccCallbackHandle = NV01_NULL_OBJECT; status = pRmApi->Alloc(pRmApi, device->session->handle, device->subhandle, &rmSubDevice->eccCallbackHandle, NV01_EVENT_KERNEL_CALLBACK_EX, - &allocDbeParams); + &pParams->allocDbe); if (status != NV_OK) - goto error; + goto done; - eventDbeParams.event = NV2080_NOTIFIERS_ECC_DBE; - eventDbeParams.action = NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE; + pParams->eventDbe.event = NV2080_NOTIFIERS_ECC_DBE; + pParams->eventDbe.action = NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE; status = pRmApi->Control(pRmApi, device->session->handle, device->subhandle, NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION, - (void *)&eventDbeParams, - sizeof(eventDbeParams)); + &pParams->eventDbe, + sizeof(pParams->eventDbe)); if (status != NV_OK) - goto error; + goto done; -success: - rmSubDevice->bEccInitialized = NV_TRUE; - return NV_OK; +done: + portMemFree(pParams); + + if (status == NV_OK) + rmSubDevice->bEccInitialized = NV_TRUE; + else + gpuDeviceRmSubDeviceDeinitEcc(device); -error: - gpuDeviceRmSubDeviceDeinitEcc(device); return status; } @@ -1568,6 +1580,8 @@ static NV_STATUS getPCIELinkRateMBps(struct gpuDevice *device, NvU32 *pcieLinkRa const NvU32 PCIE_4_ENCODING_RATIO_EFFECTIVE = 128; const NvU32 PCIE_5_ENCODING_RATIO_TOTAL = 130; const NvU32 PCIE_5_ENCODING_RATIO_EFFECTIVE = 128; + const NvU32 PCIE_6_ENCODING_RATIO_TOTAL = 130; + const NvU32 PCIE_6_ENCODING_RATIO_EFFECTIVE = 128; RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); NV2080_CTRL_BUS_INFO busInfo = {0}; @@ -1617,6 +1631,10 @@ static NV_STATUS getPCIELinkRateMBps(struct gpuDevice *device, NvU32 *pcieLinkRa linkRate = ((32000 * lanes * PCIE_5_ENCODING_RATIO_EFFECTIVE) / PCIE_5_ENCODING_RATIO_TOTAL) / 8; break; + case NV2080_CTRL_BUS_INFO_PCIE_LINK_CAP_MAX_SPEED_64000MBPS: + linkRate = ((64000 * lanes * PCIE_6_ENCODING_RATIO_EFFECTIVE) + / PCIE_6_ENCODING_RATIO_TOTAL) / 8; + break; default: status = NV_ERR_INVALID_STATE; NV_PRINTF(LEVEL_ERROR, "Unknown PCIe speed\n"); @@ -2800,7 +2818,8 @@ static GMMU_APERTURE nvGpuOpsGetExternalAllocAperture(PMEMORY_DESCRIPTOR pMemDes return GMMU_APERTURE_VIDEO; } - else if ((memdescGetAddressSpace(pMemDesc) == ADDR_FABRIC) || + else if ( + (memdescGetAddressSpace(pMemDesc) == ADDR_FABRIC_MC) || (memdescGetAddressSpace(pMemDesc) == ADDR_FABRIC_V2)) { return GMMU_APERTURE_PEER; @@ -3137,6 +3156,11 @@ nvGpuOpsBuildExternalAllocPtes ptePcfSw |= !atomic ? (1 << SW_MMU_PCF_NOATOMIC_IDX) : 0; ptePcfSw |= !privileged ? (1 << SW_MMU_PCF_REGULAR_IDX) : 0; + if ((memdescGetAddressSpace(pMemDesc) == ADDR_FABRIC_MC)) + { + ptePcfSw |= (1 << SW_MMU_PCF_ACE_IDX); + } + NV_CHECK_OR_RETURN(LEVEL_ERROR, (kgmmuTranslatePtePcfFromSw_HAL(pKernelGmmu, ptePcfSw, &ptePcfHw) == NV_OK), NV_ERR_INVALID_ARGUMENT); @@ -3184,11 +3208,12 @@ nvGpuOpsBuildExternalAllocPtes FlaMemory* pFlaMemory = dynamicCast(pMemory, FlaMemory); nvFieldSet32(&pPteFmt->fldPeerIndex, peerId, pte.v8); - if ((memdescGetAddressSpace(pMemDesc) == ADDR_FABRIC) || + if ( + (memdescGetAddressSpace(pMemDesc) == ADDR_FABRIC_MC) || (memdescGetAddressSpace(pMemDesc) == ADDR_FABRIC_V2) || pFlaMemory) { // - // ADDR_FABRIC/ADDR_FABRIC_V2 memory descriptors are pre-encoded with the fabric base address + // Any fabric memory descriptors are pre-encoded with the fabric base address // use NVLINK_INVALID_FABRIC_ADDR to avoid encoding twice // fabricBaseAddress = NVLINK_INVALID_FABRIC_ADDR; @@ -3404,7 +3429,7 @@ NV_STATUS nvGpuOpsGetExternalAllocPtes(struct gpuAddressSpace *vaSpace, // Do not support mapping on anything other than sysmem/vidmem/fabric! if ((memdescGetAddressSpace(pMemDesc) != ADDR_SYSMEM) && (memdescGetAddressSpace(pMemDesc) != ADDR_FBMEM) && - (memdescGetAddressSpace(pMemDesc) != ADDR_FABRIC) && + (memdescGetAddressSpace(pMemDesc) != ADDR_FABRIC_MC) && (memdescGetAddressSpace(pMemDesc) != ADDR_FABRIC_V2)) { status = NV_ERR_NOT_SUPPORTED; @@ -3428,7 +3453,8 @@ NV_STATUS nvGpuOpsGetExternalAllocPtes(struct gpuAddressSpace *vaSpace, } // Check if P2P supported - if ((memdescGetAddressSpace(pAdjustedMemDesc) == ADDR_FABRIC) || + if ( + (memdescGetAddressSpace(pAdjustedMemDesc) == ADDR_FABRIC_MC) || (memdescGetAddressSpace(pAdjustedMemDesc) == ADDR_FABRIC_V2)) { KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pMappingGpu); @@ -3437,6 +3463,14 @@ NV_STATUS nvGpuOpsGetExternalAllocPtes(struct gpuAddressSpace *vaSpace, pPeerGpu = pAdjustedMemDesc->pGpu; peerId = BUS_INVALID_PEER; + if (!memIsGpuMapAllowed(pMemory, pMappingGpu)) + { + NV_PRINTF(LEVEL_ERROR, + "Mapping Gpu is not attached to the given memory object\n"); + status = NV_ERR_INVALID_STATE; + goto freeGpaMemdesc; + } + if (pPeerGpu != NULL) { if ((pKernelNvlink != NULL) && @@ -3445,6 +3479,11 @@ NV_STATUS nvGpuOpsGetExternalAllocPtes(struct gpuAddressSpace *vaSpace, peerId = kbusGetPeerId_HAL(pMappingGpu, GPU_GET_KERNEL_BUS(pMappingGpu), pPeerGpu); } } + else + { + peerId = kbusGetNvSwitchPeerId_HAL(pMappingGpu, + GPU_GET_KERNEL_BUS(pMappingGpu)); + } if (peerId == BUS_INVALID_PEER) { @@ -4340,14 +4379,14 @@ static void channelReleaseDummyAlloc(struct gpuChannel *channel) } } -static NvU32 channelEngineType(const struct gpuChannel *channel) +static RM_ENGINE_TYPE channelEngineType(const struct gpuChannel *channel) { if (channel->engineType == UVM_GPU_CHANNEL_ENGINE_TYPE_CE) - return NV2080_ENGINE_TYPE_COPY(channel->engineIndex); + return RM_ENGINE_TYPE_COPY(channel->engineIndex); else if (channel->engineType == UVM_GPU_CHANNEL_ENGINE_TYPE_SEC2) - return NV2080_ENGINE_TYPE_SEC2; + return RM_ENGINE_TYPE_SEC2; else - return NV2080_ENGINE_TYPE_GR(channel->engineIndex); + return RM_ENGINE_TYPE_GR(channel->engineIndex); } static NV_STATUS channelAllocate(struct gpuAddressSpace *vaSpace, @@ -4554,7 +4593,7 @@ static NV_STATUS channelAllocate(struct gpuAddressSpace *vaSpace, pAllocInfo->gpFifoAllocParams.gpFifoEntries = channel->fifoEntries; // If zero then it will attach to the device address space pAllocInfo->gpFifoAllocParams.hVASpace = vaSpace->handle; - pAllocInfo->gpFifoAllocParams.engineType = channelEngineType(channel); + pAllocInfo->gpFifoAllocParams.engineType = gpuGetNv2080EngineType(channelEngineType(channel)); if (isDeviceVoltaPlus(device)) { @@ -4599,8 +4638,8 @@ static NV_STATUS channelAllocate(struct gpuAddressSpace *vaSpace, pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); status = kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, - ENGINE_INFO_TYPE_NV2080, - channelEngineType(channel), + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, + (NvU32)channelEngineType(channel), ENGINE_INFO_TYPE_RUNLIST, &channel->hwRunlistId); if (status != NV_OK) @@ -5863,7 +5902,7 @@ static NV_STATUS dupMemory(struct gpuDevice *device, if (memdescGetAddressSpace(pAdjustedMemDesc) != ADDR_FBMEM && memdescGetAddressSpace(pAdjustedMemDesc) != ADDR_SYSMEM && - memdescGetAddressSpace(pAdjustedMemDesc) != ADDR_FABRIC && + memdescGetAddressSpace(pAdjustedMemDesc) != ADDR_FABRIC_MC && memdescGetAddressSpace(pAdjustedMemDesc) != ADDR_FABRIC_V2) { status = NV_ERR_NOT_SUPPORTED; @@ -5915,8 +5954,12 @@ static NV_STATUS dupMemory(struct gpuDevice *device, } else if (dynamicCast(pParentRef->pResource, RsClientResource)) { - NV_ASSERT((memdescGetAddressSpace(pAdjustedMemDesc) == ADDR_FABRIC) || - (memdescGetAddressSpace(pAdjustedMemDesc) == ADDR_FABRIC_V2)); + NvBool bAssert = ( + (memdescGetAddressSpace(pAdjustedMemDesc) == ADDR_FABRIC_MC) || + (memdescGetAddressSpace(pAdjustedMemDesc) == ADDR_FABRIC_V2)); + + NV_ASSERT(bAssert); + hParent = session->handle; } else @@ -7239,7 +7282,8 @@ static NV_STATUS nvGpuOpsGetChannelEngineType(OBJGPU *pGpu, UVM_GPU_CHANNEL_ENGINE_TYPE *engineType) { KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); - NvU32 engDesc, engineType2080; + NvU32 engDesc; + RM_ENGINE_TYPE rmEngineType; NV_STATUS status; NV_ASSERT_OR_RETURN(pKernelChannel != NULL, NV_ERR_INVALID_ARGUMENT); @@ -7252,14 +7296,14 @@ static NV_STATUS nvGpuOpsGetChannelEngineType(OBJGPU *pGpu, pKernelFifo, ENGINE_INFO_TYPE_ENG_DESC, engDesc, - ENGINE_INFO_TYPE_NV2080, - &engineType2080); + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, + (NvU32 *)&rmEngineType); if (status != NV_OK) return status; - if (NV2080_ENGINE_TYPE_IS_GR(engineType2080)) + if (RM_ENGINE_TYPE_IS_GR(rmEngineType)) *engineType = UVM_GPU_CHANNEL_ENGINE_TYPE_GR; - else if (engineType2080 == NV2080_ENGINE_TYPE_SEC2) + else if (rmEngineType == RM_ENGINE_TYPE_SEC2) *engineType = UVM_GPU_CHANNEL_ENGINE_TYPE_SEC2; else *engineType = UVM_GPU_CHANNEL_ENGINE_TYPE_CE; @@ -7404,7 +7448,7 @@ static NV_STATUS nvGpuOpsGetChannelSmcInfo(gpuRetainedChannel *retainedChannel, NvU32 grFaultId; NvU32 grMmuFaultEngId; - const NvU32 grIdx = NV2080_ENGINE_TYPE_GR_IDX(kchannelGetEngineType(pKernelChannel)); + const NvU32 grIdx = RM_ENGINE_TYPE_GR_IDX(kchannelGetEngineType(pKernelChannel)); NV_ASSERT_OK_OR_RETURN(kfifoEngineInfoXlate_HAL(pGpu, GPU_GET_KERNEL_FIFO(pGpu), @@ -7823,7 +7867,7 @@ _shadowMemdescCreateFlcn(gpuRetainedChannel *retainedChannel, if (_memDescFindAndRetain(retainedChannel, pBufferHandle, ppMemDesc)) return status; - memdescCreate(&pMemDesc, + status = memdescCreate(&pMemDesc, retainedChannel->pGpu, pCtxBufferInfo->size, pCtxBufferInfo->alignment, @@ -7856,7 +7900,7 @@ _shadowMemdescCreate(gpuRetainedChannel *retainedChannel, NvU32 numBufferPages = NV_ROUNDUP(pCtxBufferInfo->size, pageSize) / pageSize; MEMORY_DESCRIPTOR *pMemDesc = NULL; MEMORY_DESCRIPTOR *pBufferHandle = (MEMORY_DESCRIPTOR *) pCtxBufferInfo->bufferHandle; - NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS params = { 0 }; + NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS *pParams = NULL; NvU64 *pPages = NULL; NV_STATUS status = NV_OK; KernelChannel *pKernelChannel; @@ -7878,42 +7922,51 @@ _shadowMemdescCreate(gpuRetainedChannel *retainedChannel, goto done; } - params.hUserClient = RES_GET_CLIENT_HANDLE(pKernelChannel); - params.hChannel = RES_GET_HANDLE(pKernelChannel); - params.bufferType = pCtxBufferInfo->bufferType; + pParams = portMemAllocNonPaged(sizeof(*pParams)); + if (pParams == NULL) + { + status = NV_ERR_NO_MEMORY; + goto done; + } + + portMemSet(pParams, 0, sizeof(*pParams)); + + pParams->hUserClient = RES_GET_CLIENT_HANDLE(pKernelChannel); + pParams->hChannel = RES_GET_HANDLE(pKernelChannel); + pParams->bufferType = pCtxBufferInfo->bufferType; pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); for (j = 0; j < numBufferPages;) { - params.firstPage = j; + pParams->firstPage = j; status = pRmApi->Control(pRmApi, retainedChannel->session->handle, retainedChannel->rmSubDevice->subDeviceHandle, NV2080_CTRL_CMD_KGR_GET_CTX_BUFFER_PTES, - ¶ms, - sizeof(params)); + pParams, + sizeof(*pParams)); if (status != NV_OK) { goto done; } - NV_ASSERT(j + params.numPages <= numBufferPages); + NV_ASSERT(j + pParams->numPages <= numBufferPages); if (pCtxBufferInfo->bIsContigous) { - pPages[0] = (NvU64)params.physAddrs[0]; + pPages[0] = (NvU64)pParams->physAddrs[0]; break; } - portMemCopy(&pPages[j], params.numPages * sizeof(*pPages), - params.physAddrs, params.numPages * sizeof(*pPages)); - j += params.numPages; + portMemCopy(&pPages[j], pParams->numPages * sizeof(*pPages), + pParams->physAddrs, pParams->numPages * sizeof(*pPages)); + j += pParams->numPages; } - NV_ASSERT(params.bNoMorePages); + NV_ASSERT(pParams->bNoMorePages); - memdescCreate(&pMemDesc, + status = memdescCreate(&pMemDesc, retainedChannel->pGpu, pCtxBufferInfo->size, pCtxBufferInfo->alignment, @@ -7922,6 +7975,11 @@ _shadowMemdescCreate(gpuRetainedChannel *retainedChannel, NV_MEMORY_CACHED, MEMDESC_FLAGS_NONE ); + if (status != NV_OK) + { + goto done; + } + memdescSetPageSize(pMemDesc, 0, pCtxBufferInfo->pageSize); @@ -7940,6 +7998,7 @@ _shadowMemdescCreate(gpuRetainedChannel *retainedChannel, *ppMemDesc = pMemDesc; done: + portMemFree(pParams); portMemFree(pPages); return status; } @@ -8235,6 +8294,8 @@ NV_STATUS nvGpuOpsBindChannelResources(gpuRetainedChannel *retainedChannel, // Unregister channel resources. CE channels have 0 resources, so they skip this step if (retainedChannel->resourceCount != 0) { + RM_ENGINE_TYPE rmEngineType; + pParams = portMemAllocNonPaged(sizeof(*pParams)); if (pParams == NULL) { @@ -8254,13 +8315,16 @@ NV_STATUS nvGpuOpsBindChannelResources(gpuRetainedChannel *retainedChannel, GPU_GET_KERNEL_FIFO(retainedChannel->pGpu), ENGINE_INFO_TYPE_RUNLIST, retainedChannel->runlistId, - ENGINE_INFO_TYPE_NV2080, - &(pParams->engineType)); + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, + (NvU32 *)&rmEngineType); + + pParams->engineType = gpuGetNv2080EngineType(rmEngineType); for (i = 0; i < retainedChannel->resourceCount; i++) { - if (NV2080_ENGINE_TYPE_IS_GR(pParams->engineType)) + if (RM_ENGINE_TYPE_IS_GR(rmEngineType)) pParams->promoteEntry[i].bufferId = channelResourceBindParams[i].resourceId; + pParams->promoteEntry[i].gpuVirtAddr = channelResourceBindParams[i].resourceVa; } @@ -8782,7 +8846,6 @@ void nvGpuOpsPagingChannelsUnmap(struct gpuAddressSpace *srcVaSpace, return; } - status = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_GPU_OPS); NV_ASSERT(status == NV_OK); if (status != NV_OK) diff --git a/src/nvidia/src/kernel/rmapi/resource.c b/src/nvidia/src/kernel/rmapi/resource.c index 7d018d773..de1900722 100644 --- a/src/nvidia/src/kernel/rmapi/resource.c +++ b/src/nvidia/src/kernel/rmapi/resource.c @@ -238,16 +238,6 @@ rmresControl_Prologue_IMPL if (pGpu == NULL) return NV_OK; - if (rmapiControlIsCacheable(pParams->pCookie->ctrlFlags, IS_GSP_CLIENT(pGpu))) - { - void* cached = rmapiControlCacheGet(pParams->hClient, pParams->hObject, pParams->cmd); - if (cached) - { - portMemCopy(pParams->pParams, pParams->paramsSize, cached, pParams->paramsSize); - return NV_WARN_NOTHING_TO_DO; - } - } - if ((IS_VIRTUAL(pGpu) && (pParams->pCookie->ctrlFlags & RMCTRL_FLAGS_ROUTE_TO_VGPU_HOST)) || (IS_GSP_CLIENT(pGpu) && (pParams->pCookie->ctrlFlags & RMCTRL_FLAGS_ROUTE_TO_PHYSICAL))) { @@ -293,19 +283,4 @@ rmresControl_Epilogue_IMPL RS_RES_CONTROL_PARAMS_INTERNAL *pParams ) { - OBJGPU *pGpu = gpumgrGetGpu(pResource->rpcGpuInstance); - - if (pGpu == NULL) - return; - - if (rmapiControlIsCacheable(pParams->pCookie->ctrlFlags, IS_GSP_CLIENT(pGpu))) - { - void* cached = rmapiControlCacheGet(pParams->hClient, pParams->hObject, pParams->cmd); - if (!cached) - { - NV_PRINTF(LEVEL_INFO, "rmControl: caching cmd 0x%x params\n", pParams->cmd); - NV_ASSERT_OK(rmapiControlCacheSet(pParams->hClient, pParams->hObject, pParams->cmd, - NvP64_VALUE(pParams->pParams), pParams->paramsSize)); - } - } } diff --git a/src/nvidia/src/kernel/rmapi/resource_desc.c b/src/nvidia/src/kernel/rmapi/resource_desc.c index d04d7cb25..e4230a985 100644 --- a/src/nvidia/src/kernel/rmapi/resource_desc.c +++ b/src/nvidia/src/kernel/rmapi/resource_desc.c @@ -26,9 +26,8 @@ // Need the full header for the class allocation param structure. #define SDK_ALL_CLASSES_INCLUDE_FULL_HEADER #include "g_allclasses.h" -// Not a class header, but contains an allocation struct used by several classes -#include "class/clb0b5sw.h" -#include "nvos.h" + +#include "resource_list_required_includes.h" #include "rmapi/alloc_size.h" #include "rmapi/resource_fwd_decls.h" diff --git a/src/nvidia/src/kernel/rmapi/resource_list.h b/src/nvidia/src/kernel/rmapi/resource_list.h index 752774de7..45adf1fda 100644 --- a/src/nvidia/src/kernel/rmapi/resource_list.h +++ b/src/nvidia/src/kernel/rmapi/resource_list.h @@ -25,6 +25,10 @@ // No include guards - this file is included multiple times, each time with a // different definition for RS_ENTRY // +// Some of those definitions of RS_ENTRY may depend on declarations in various +// other header files. Include "resource_list_required_includes.h" to pull them +// in. +// // // Table describing all RsResource subclasses. @@ -166,6 +170,16 @@ RS_ENTRY( /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) +RS_ENTRY( + /* External Class */ NV30_GSYNC, + /* Internal Class */ GSyncApi, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(RmClientResource)), + /* Alloc Param Info */ RS_REQUIRED(NV30F1_ALLOC_PARAMETERS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Required Access Rights */ RS_ACCESS_NONE +) RS_ENTRY( /* External Class */ GF100_PROFILER, /* Internal Class */ Profiler, @@ -213,7 +227,7 @@ RS_ENTRY( /* Internal Class */ KernelChannel, /* Multi-Instance */ NV_TRUE, /* Parents */ RS_LIST(classId(Device), classId(KernelChannelGroupApi)), - /* Alloc Param Info */ RS_REQUIRED(NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS), + /* Alloc Param Info */ RS_REQUIRED(NV_CHANNEL_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE @@ -223,7 +237,7 @@ RS_ENTRY( /* Internal Class */ KernelChannel, /* Multi-Instance */ NV_TRUE, /* Parents */ RS_LIST(classId(Device), classId(KernelChannelGroupApi)), - /* Alloc Param Info */ RS_REQUIRED(NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS), + /* Alloc Param Info */ RS_REQUIRED(NV_CHANNEL_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE @@ -233,7 +247,7 @@ RS_ENTRY( /* Internal Class */ KernelChannel, /* Multi-Instance */ NV_TRUE, /* Parents */ RS_LIST(classId(Device), classId(KernelChannelGroupApi)), - /* Alloc Param Info */ RS_REQUIRED(NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS), + /* Alloc Param Info */ RS_REQUIRED(NV_CHANNEL_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE @@ -243,7 +257,7 @@ RS_ENTRY( /* Internal Class */ KernelChannel, /* Multi-Instance */ NV_TRUE, /* Parents */ RS_LIST(classId(Device), classId(KernelChannelGroupApi)), - /* Alloc Param Info */ RS_REQUIRED(NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS), + /* Alloc Param Info */ RS_REQUIRED(NV_CHANNEL_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE @@ -253,7 +267,7 @@ RS_ENTRY( /* Internal Class */ KernelChannel, /* Multi-Instance */ NV_TRUE, /* Parents */ RS_LIST(classId(Device), classId(KernelChannelGroupApi)), - /* Alloc Param Info */ RS_REQUIRED(NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS), + /* Alloc Param Info */ RS_REQUIRED(NV_CHANNEL_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE @@ -263,7 +277,7 @@ RS_ENTRY( /* Internal Class */ KernelChannel, /* Multi-Instance */ NV_TRUE, /* Parents */ RS_LIST(classId(Device), classId(KernelChannelGroupApi)), - /* Alloc Param Info */ RS_REQUIRED(NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS), + /* Alloc Param Info */ RS_REQUIRED(NV_CHANNEL_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE @@ -273,7 +287,7 @@ RS_ENTRY( /* Internal Class */ KernelChannel, /* Multi-Instance */ NV_TRUE, /* Parents */ RS_LIST(classId(Device), classId(KernelChannelGroupApi)), - /* Alloc Param Info */ RS_REQUIRED(NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS), + /* Alloc Param Info */ RS_REQUIRED(NV_CHANNEL_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE @@ -283,7 +297,7 @@ RS_ENTRY( /* Internal Class */ KernelChannel, /* Multi-Instance */ NV_TRUE, /* Parents */ RS_LIST(classId(Device), classId(KernelChannelGroupApi)), - /* Alloc Param Info */ RS_REQUIRED(NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS), + /* Alloc Param Info */ RS_REQUIRED(NV_CHANNEL_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE @@ -293,7 +307,7 @@ RS_ENTRY( /* Internal Class */ KernelChannel, /* Multi-Instance */ NV_TRUE, /* Parents */ RS_LIST(classId(Device), classId(KernelChannelGroupApi)), - /* Alloc Param Info */ RS_REQUIRED(NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS), + /* Alloc Param Info */ RS_REQUIRED(NV_CHANNEL_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE @@ -428,6 +442,16 @@ RS_ENTRY( /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) +RS_ENTRY( + /* External Class */ NV_MEMORY_MAPPER, + /* Internal Class */ MemoryMapper, + /* Multi-Instance */ NV_FALSE, + /* Parents */ RS_LIST(classId(Subdevice)), + /* Alloc Param Info */ RS_REQUIRED(NV_MEMORY_MAPPER_ALLOCATION_PARAMS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Required Access Rights */ RS_ACCESS_NONE +) RS_ENTRY( /* External Class */ NV01_MEMORY_SYSTEM_OS_DESCRIPTOR, /* Internal Class */ OsDescMemory, @@ -468,6 +492,36 @@ RS_ENTRY( /* Flags */ RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) +RS_ENTRY( + /* External Class */ NV01_MEMORY_LIST_SYSTEM, + /* Internal Class */ MemoryList, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(Device), classId(Subdevice)), + /* Alloc Param Info */ RS_REQUIRED(NV_MEMORY_LIST_ALLOCATION_PARAMS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Required Access Rights */ RS_ACCESS_NONE +) +RS_ENTRY( + /* External Class */ NV01_MEMORY_LIST_FBMEM, + /* Internal Class */ MemoryList, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(Device), classId(Subdevice)), + /* Alloc Param Info */ RS_REQUIRED(NV_MEMORY_LIST_ALLOCATION_PARAMS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Required Access Rights */ RS_ACCESS_NONE +) +RS_ENTRY( + /* External Class */ NV01_MEMORY_LIST_OBJECT, + /* Internal Class */ MemoryList, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(Device), classId(Subdevice)), + /* Alloc Param Info */ RS_REQUIRED(NV_MEMORY_LIST_ALLOCATION_PARAMS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Required Access Rights */ RS_ACCESS_NONE +) RS_ENTRY( /* External Class */ NV01_MEMORY_FLA, /* Internal Class */ FlaMemory, @@ -497,8 +551,38 @@ RS_ENTRY( /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE +) +RS_ENTRY( + /* External Class */ NV_MEMORY_MULTICAST_FABRIC, + /* Internal Class */ MemoryMulticastFabric, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(RmClientResource)), + /* Alloc Param Info */ RS_REQUIRED(NV00FD_ALLOCATION_PARAMETERS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Required Access Rights */ RS_ACCESS_NONE ) /* Subdevice Children: */ +RS_ENTRY( + /* External Class */ NVA081_VGPU_CONFIG, + /* Internal Class */ VgpuConfigApi, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(Subdevice)), + /* Alloc Param Info */ RS_NONE, + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Required Access Rights */ RS_ACCESS_NONE +) +RS_ENTRY( + /* External Class */ NVA084_KERNEL_HOST_VGPU_DEVICE, + /* Internal Class */ KernelHostVgpuDeviceApi, + /* Multi-Instance */ NV_FALSE, + /* Parents */ RS_LIST(classId(Subdevice)), + /* Alloc Param Info */ RS_REQUIRED(NVA084_ALLOC_PARAMETERS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Required Access Rights */ RS_ACCESS_NONE +) RS_ENTRY( /* External Class */ NV50_THIRD_PARTY_P2P, /* Internal Class */ ThirdPartyP2P, @@ -552,7 +636,7 @@ RS_ENTRY( RS_ENTRY( /* External Class */ GF100_ZBC_CLEAR, /* Internal Class */ ZbcApi, - /* Multi-Instance */ NV_FALSE, + /* Multi-Instance */ NV_TRUE, /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, @@ -569,6 +653,16 @@ RS_ENTRY( /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) +RS_ENTRY( + /* External Class */ RM_USER_SHARED_DATA, + /* Internal Class */ GpuUserSharedData, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(Subdevice)), + /* Alloc Param Info */ RS_REQUIRED(NV00DE_ALLOC_PARAMETERS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK, + /* Required Access Rights */ RS_ACCESS_NONE +) RS_ENTRY( /* External Class */ VOLTA_USERMODE_A, /* Internal Class */ UserModeApi, @@ -851,6 +945,16 @@ RS_ENTRY( /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( NVC77D_CORE_CHANNEL_DMA, DispChannelDma, NV_TRUE, RS_LIST(classId(NvDispApi)), RS_REQUIRED(NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS), RS_FREE_PRIORITY_DEFAULT, RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, RS_ACCESS_NONE ) +RS_ENTRY( + /* External Class */ NVC77F_ANY_CHANNEL_DMA, + /* Internal Class */ DispChannelDma, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(NvDispApi)), + /* Alloc Param Info */ RS_REQUIRED(NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Required Access Rights */ RS_ACCESS_NONE +) RS_ENTRY( /* External Class */ NVC67E_WINDOW_CHANNEL_DMA, /* Internal Class */ DispChannelDma, diff --git a/src/nvidia/src/kernel/rmapi/resource_list_required_includes.h b/src/nvidia/src/kernel/rmapi/resource_list_required_includes.h new file mode 100644 index 000000000..de4aef8b0 --- /dev/null +++ b/src/nvidia/src/kernel/rmapi/resource_list_required_includes.h @@ -0,0 +1,72 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef RESOURCE_LIST_REQUIRED_INCLUDES_H +#define RESOURCE_LIST_REQUIRED_INCLUDES_H 1 + +// +// This file must be included wherever resource_list.h is included. It provides +// declarations for types that resource_list.h may depend on while honoring +// RMCFG at the same time. +// +// We cannot include the required files right above the RS_ENTRY definitions in +// resource_list.h because resource_list.h may be included in places that don't +// allow some declarations (example typedefs in an enum). +// + + + +// +// CORERM-3604 +// A lot of declarations are in nvos.h +// These can be assumed to not require RMCFG. These should be eventually split +// into individual files and nvos.h should be deprecated. +// +#include "nvos.h" + + +#if RMCFG_CLASS_GF100_CHANNEL_GPFIFO || \ + RMCFG_CLASS_KEPLER_CHANNEL_GPFIFO_A || \ + RMCFG_CLASS_KEPLER_CHANNEL_GPFIFO_B || \ + RMCFG_CLASS_KEPLER_CHANNEL_GPFIFO_C || \ + RMCFG_CLASS_MAXWELL_CHANNEL_GPFIFO_A || \ + RMCFG_CLASS_PASCAL_CHANNEL_GPFIFO_A || \ + RMCFG_CLASS_VOLTA_CHANNEL_GPFIFO_A || \ + RMCFG_CLASS_TURING_CHANNEL_GPFIFO_A || \ + RMCFG_CLASS_AMPERE_CHANNEL_GPFIFO_A || \ + RMCFG_CLASS_HOPPER_CHANNEL_GPFIFO_A +#include "alloc/alloc_channel.h" +#endif + +#if RMCFG_CLASS_MAXWELL_DMA_COPY_A || \ + RMCFG_CLASS_PASCAL_DMA_COPY_A || \ + RMCFG_CLASS_PASCAL_DMA_COPY_B || \ + RMCFG_CLASS_VOLTA_DMA_COPY_A || \ + RMCFG_CLASS_TURING_DMA_COPY_A || \ + RMCFG_CLASS_AMPERE_DMA_COPY_A || \ + RMCFG_CLASS_AMPERE_DMA_COPY_B || \ + RMCFG_CLASS_HOPPER_DMA_COPY_A +#include "class/clb0b5sw.h" +#endif + +#endif /* ifndef RESOURCE_LIST_REQUIRED_INCLUDES_H */ diff --git a/src/nvidia/src/kernel/rmapi/rmapi.c b/src/nvidia/src/kernel/rmapi/rmapi.c index a07481dbc..10b3ad6c6 100644 --- a/src/nvidia/src/kernel/rmapi/rmapi.c +++ b/src/nvidia/src/kernel/rmapi/rmapi.c @@ -76,7 +76,14 @@ rmapiInitialize if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "*** Cannot allocate rmapi locks\n"); - return status; + goto failed; + } + + status = rmapiControlCacheInit(); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "*** Cannot initialize rmapi cache\n"); + goto failed_free_lock; } RsResInfoInitialize(); @@ -85,11 +92,10 @@ rmapiInitialize if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "*** Cannot initialize resource server\n"); - _rmapiLockFree(); - return status; + goto failed_free_cache; } - rmapiControlCacheInit(); + serverSetClientHandleBase(&g_resServ, RS_CLIENT_HANDLE_BASE); listInit(&g_clientListBehindGpusLock, g_resServ.pAllocator); listInit(&g_userInfoList, g_resServ.pAllocator); @@ -107,6 +113,13 @@ rmapiInitialize g_bResServInit = NV_TRUE; + return NV_OK; + +failed_free_cache: + rmapiControlCacheFree(); +failed_free_lock: + _rmapiLockFree(); +failed: return status; } diff --git a/src/nvidia/src/kernel/rmapi/rmapi_cache.c b/src/nvidia/src/kernel/rmapi/rmapi_cache.c index 8ec5b04ef..621af9ed2 100644 --- a/src/nvidia/src/kernel/rmapi/rmapi_cache.c +++ b/src/nvidia/src/kernel/rmapi/rmapi_cache.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -23,87 +23,242 @@ #include "containers/map.h" #include "containers/multimap.h" #include "nvctassert.h" +#include "nvmisc.h" #include "nvport/sync.h" #include "nvrm_registry.h" #include "os/os.h" #include "rmapi/control.h" #include "rmapi/rmapi.h" +#include "rmapi/rmapi_utils.h" +#include "ctrl/ctrl0000/ctrl0000system.h" typedef struct { void* params; } RmapiControlCacheEntry; -MAKE_MULTIMAP(CachedCallParams, RmapiControlCacheEntry); +// +// Stores the mapping of client object to the corresponding GPU instance +// The key is generated by _handlesToGpuInstKey with client and object handle +// The value is the instance of the GPU (pGpu->gpuInstance) the object is linked to +// +MAKE_MAP(ObjectToGpuInstMap, NvU64); + +// +// Stores the cached control value. +// Each submap in the multimap stores the cached control value for one GPU. +// The key to find a submap is GPU Instance stored in ObjectToGpuInstMap +// +// The key inside the submap is the control command +// The value inside the submap is the cached control value for the command +// +MAKE_MULTIMAP(GpusControlCache, RmapiControlCacheEntry); ct_assert(sizeof(NvHandle) <= 4); #define CLIENT_KEY_SHIFT (sizeof(NvHandle) * 8) -static NvHandle keyToClient(NvU64 key) +static NvBool _isCmdSystemWide(NvU32 cmd) +{ + return DRF_VAL(XXXX, _CTRL_CMD, _CLASS, cmd) == NV01_ROOT; +} + +static NvHandle _gpuInstKeyToClient(NvU64 key) { return (key >> CLIENT_KEY_SHIFT); } -static NvU64 handlesToKey(NvHandle hClient, NvHandle hObject) +static NvU64 _handlesToGpuInstKey(NvHandle hClient, NvHandle hObject) { return ((NvU64)hClient << CLIENT_KEY_SHIFT) | hObject; } static struct { /* NOTE: Size unbounded for now */ - CachedCallParams cachedCallParams; + GpusControlCache gpusControlCache; + ObjectToGpuInstMap objectToGpuInstMap; NvU32 mode; - PORT_MUTEX *mtx; + PORT_RWLOCK *pLock; } RmapiControlCache; -NvBool rmapiControlIsCacheable(NvU32 flags, NvBool isGSPClient) +NvBool rmapiControlIsCacheable(NvU32 flags, NvU32 accessRight, NvBool bAllowInternal) { - if (RmapiControlCache.mode == NV_REG_STR_RM_CACHEABLE_CONTROLS_ENABLE) + if (RmapiControlCache.mode == NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_DISABLE) + return NV_FALSE; + + if (!(flags & RMCTRL_FLAGS_CACHEABLE)) + return NV_FALSE; + + // + // RMCTRL with access right requires access right check. + // We need resource ref and client object to check the access right, both not + // available here. Do not cache RMCTRLs with access right. + // + if (accessRight != 0) + return NV_FALSE; + + // Allow internal RMCTRL of all privilege with bAllowInternal flag + if (flags & RMCTRL_FLAGS_INTERNAL) + return bAllowInternal; + + // + // For non-internal calls, allow cache only for non-privileged RMCTRL since + // we don't have the client object to validate client. + // + if (!(flags & RMCTRL_FLAGS_NON_PRIVILEGED)) { - return !!(flags & RMCTRL_FLAGS_CACHEABLE); + NV_PRINTF(LEVEL_WARNING, "Do not allow cache for priviliged ctrls\n"); + return NV_FALSE; } - if (RmapiControlCache.mode == NV_REG_STR_RM_CACHEABLE_CONTROLS_GSP_ONLY) - { - return (flags & RMCTRL_FLAGS_CACHEABLE) && - (flags & RMCTRL_FLAGS_ROUTE_TO_PHYSICAL) && - isGSPClient; - } - return NV_FALSE; + + return NV_TRUE; } -void rmapiControlCacheInit() +NvBool rmapiCmdIsCacheable(NvU32 cmd, NvBool bAllowInternal) { - RmapiControlCache.mode = NV_REG_STR_RM_CACHEABLE_CONTROLS_GSP_ONLY; + NvU32 flags; + NvU32 accessRight; - osReadRegistryDword(NULL, NV_REG_STR_RM_CACHEABLE_CONTROLS, &RmapiControlCache.mode); + if (rmapiutilGetControlInfo(cmd, &flags, &accessRight) != NV_OK) + return NV_FALSE; + + return rmapiControlIsCacheable(flags, accessRight, bAllowInternal); +} + +NV_STATUS rmapiControlCacheInit() +{ +#if defined(DEBUG) + RmapiControlCache.mode = NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY; +#else + RmapiControlCache.mode = NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_ENABLE; +#endif + + NvU32 mode; + + if (osReadRegistryDword(NULL, NV_REG_STR_RM_CACHEABLE_CONTROLS, &mode) == NV_OK) + { + RmapiControlCache.mode = mode; + } NV_PRINTF(LEVEL_INFO, "using cache mode %d\n", RmapiControlCache.mode); - if (RmapiControlCache.mode) + multimapInit(&RmapiControlCache.gpusControlCache, portMemAllocatorGetGlobalNonPaged()); + mapInit(&RmapiControlCache.objectToGpuInstMap, portMemAllocatorGetGlobalNonPaged()); + RmapiControlCache.pLock = portSyncRwLockCreate(portMemAllocatorGetGlobalNonPaged()); + if (RmapiControlCache.pLock == NULL) { - multimapInit(&RmapiControlCache.cachedCallParams, portMemAllocatorGetGlobalNonPaged()); - RmapiControlCache.mtx = portSyncMutexCreate(portMemAllocatorGetGlobalNonPaged()); - if (!RmapiControlCache.mtx) - { - NV_PRINTF(LEVEL_ERROR, "failed to create mutex"); - RmapiControlCache.mode = NV_REG_STR_RM_CACHEABLE_CONTROLS_DISABLE; - } + NV_PRINTF(LEVEL_ERROR, "failed to create rw lock\n"); + multimapDestroy(&RmapiControlCache.gpusControlCache); + mapDestroy(&RmapiControlCache.objectToGpuInstMap); + return NV_ERR_NO_MEMORY; + } + return NV_OK; +} + +NV_STATUS rmapiControlCacheSetGpuInstForObject +( + NvHandle hClient, + NvHandle hObject, + NvU32 gpuInst +) +{ + NV_STATUS status = NV_OK; + NvU64 *entry; + + if (gpuInst >= NV_MAX_DEVICES) + return NV_ERR_INVALID_PARAMETER; + + NV_PRINTF(LEVEL_INFO, "gpu inst set for 0x%x 0x%x: 0x%x\n", hClient, hObject, gpuInst); + + portSyncRwLockAcquireWrite(RmapiControlCache.pLock); + entry = mapFind(&RmapiControlCache.objectToGpuInstMap, _handlesToGpuInstKey(hClient, hObject)); + + if (entry != NULL) + { + // set happens in object allocation, should not exist in cache already + NV_PRINTF(LEVEL_WARNING, + "set existing gpu inst 0x%x 0x%x was 0x%llx is 0x%x\n", + hClient, hObject, *entry, gpuInst); + status = NV_ERR_INVALID_PARAMETER; + goto done; + } + + entry = mapInsertNew(&RmapiControlCache.objectToGpuInstMap, _handlesToGpuInstKey(hClient, hObject)); + + if (entry == NULL) + { + status = NV_ERR_NO_MEMORY; + goto done; + } + + *entry = gpuInst; + +done: + portSyncRwLockReleaseWrite(RmapiControlCache.pLock); + return status; +} + +// Need to hold rmapi control cache read/write lock +static NV_STATUS _rmapiControlCacheGetGpuInstForObject +( + NvHandle hClient, + NvHandle hObject, + NvU32 *pGpuInst +) +{ + NV_STATUS status = NV_ERR_OBJECT_NOT_FOUND; + NvU64* entry = mapFind(&RmapiControlCache.objectToGpuInstMap, _handlesToGpuInstKey(hClient, hObject)); + + NV_PRINTF(LEVEL_INFO, "cached gpu inst lookup for 0x%x 0x%x\n", hClient, hObject); + + if (entry != NULL) + { + NV_PRINTF(LEVEL_INFO, "cached gpu inst for 0x%x 0x%x: 0x%llx\n", hClient, hObject, *entry); + *pGpuInst = *entry; + status = NV_OK; + } + + return status; +} + +// Need to hold rmapi control cache write lock +static void _rmapiControlCacheFreeGpuInstForObject +( + NvHandle hClient, + NvHandle hObject +) +{ + const NvU64 key = _handlesToGpuInstKey(hClient, hObject); + NvU64* entry = mapFind(&RmapiControlCache.objectToGpuInstMap, key); + + if (entry != NULL) + { + mapRemove(&RmapiControlCache.objectToGpuInstMap, entry); + NV_PRINTF(LEVEL_INFO, "Gpu Inst entry with key 0x%llx freed\n", key); } } -void* rmapiControlCacheGet(NvHandle hClient, NvHandle hObject, NvU32 cmd) +// Need to hold rmapi control cache write lock +static void _rmapiControlCacheFreeGpuInstForClient(NvHandle hClient) { - NV_PRINTF(LEVEL_INFO, "cache lookup for 0x%x 0x%x 0x%x\n", hClient, hObject, cmd); - portSyncMutexAcquire(RmapiControlCache.mtx); - RmapiControlCacheEntry* entry = multimapFindItem(&RmapiControlCache.cachedCallParams, handlesToKey(hClient, hObject), cmd); - portSyncMutexRelease(RmapiControlCache.mtx); - NV_PRINTF(LEVEL_INFO, "cache entry for 0x%x 0x%x 0x%x: entry 0x%p\n", hClient, hObject, cmd, entry); - if (entry) - return entry->params; - return NULL; + while (NV_TRUE) + { + NvU64* entry = mapFindGEQ(&RmapiControlCache.objectToGpuInstMap, _handlesToGpuInstKey(hClient, 0)); + NvU64 key; + + if (entry == NULL) + break; + + key = mapKey(&RmapiControlCache.objectToGpuInstMap, entry); + + if (_gpuInstKeyToClient(key) != hClient) + break; + + mapRemove(&RmapiControlCache.objectToGpuInstMap, entry); + NV_PRINTF(LEVEL_INFO, "Gpu Inst entry with key 0x%llx freed\n", key); + } } -NV_STATUS rmapiControlCacheSet +NV_STATUS rmapiControlCacheGet ( NvHandle hClient, NvHandle hObject, @@ -112,143 +267,229 @@ NV_STATUS rmapiControlCacheSet NvU32 paramsSize ) { - portSyncMutexAcquire(RmapiControlCache.mtx); + RmapiControlCacheEntry *entry; + NvU32 gpuInst; NV_STATUS status = NV_OK; - RmapiControlCacheEntry* entry = multimapFindItem(&RmapiControlCache.cachedCallParams, handlesToKey(hClient, hObject), cmd); - CachedCallParamsSubmap* insertedSubmap = NULL; - if (!entry) + if (RmapiControlCache.mode == NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY) + return NV_ERR_OBJECT_NOT_FOUND; + + NV_PRINTF(LEVEL_INFO, "control cache lookup for 0x%x 0x%x 0x%x\n", hClient, hObject, cmd); + portSyncRwLockAcquireRead(RmapiControlCache.pLock); + + if (_isCmdSystemWide(cmd)) { - if (!multimapFindSubmap(&RmapiControlCache.cachedCallParams, handlesToKey(hClient, hObject))) + gpuInst = NV_MAX_DEVICES; + } + else + { + status = _rmapiControlCacheGetGpuInstForObject(hClient, hObject, &gpuInst); + if (status != NV_OK) + goto done; + } + + entry = multimapFindItem(&RmapiControlCache.gpusControlCache, gpuInst, cmd); + if (entry == NULL || entry->params == NULL) + { + status = NV_ERR_OBJECT_NOT_FOUND; + goto done; + } + + portMemCopy(params, paramsSize, entry->params, paramsSize); + NV_PRINTF(LEVEL_INFO, "control cache for 0x%x 0x%x 0x%x: entry %p\n", hClient, hObject, cmd, entry); +done: + portSyncRwLockReleaseRead(RmapiControlCache.pLock); + return status; +} + +NV_STATUS rmapiControlCacheSet +( + NvHandle hClient, + NvHandle hObject, + NvU32 cmd, + const void* params, + NvU32 paramsSize +) +{ + NV_STATUS status = NV_OK; + RmapiControlCacheEntry* entry = NULL; + GpusControlCacheSubmap* insertedSubmap = NULL; + NvU32 gpuInst; + + NV_PRINTF(LEVEL_INFO, "control cache set for 0x%x 0x%x 0x%x\n", hClient, hObject, cmd); + + portSyncRwLockAcquireWrite(RmapiControlCache.pLock); + + if (_isCmdSystemWide(cmd)) + { + gpuInst = NV_MAX_DEVICES; + } + else + { + status = _rmapiControlCacheGetGpuInstForObject(hClient, hObject, &gpuInst); + if (status != NV_OK) + goto done; + } + + entry = multimapFindItem(&RmapiControlCache.gpusControlCache, gpuInst, cmd); + + if (entry == NULL) + { + if (multimapFindSubmap(&RmapiControlCache.gpusControlCache, gpuInst) == NULL) { - insertedSubmap = multimapInsertSubmap(&RmapiControlCache.cachedCallParams, handlesToKey(hClient, hObject)); - if (!insertedSubmap) + insertedSubmap = multimapInsertSubmap(&RmapiControlCache.gpusControlCache, gpuInst); + if (insertedSubmap == NULL) { status = NV_ERR_NO_MEMORY; goto done; } } - entry = multimapInsertItemNew(&RmapiControlCache.cachedCallParams, handlesToKey(hClient, hObject), cmd); + entry = multimapInsertItemNew(&RmapiControlCache.gpusControlCache, gpuInst, cmd); } - if (!entry) + if (entry == NULL) { status = NV_ERR_NO_MEMORY; goto done; } + // + // Skip duplicated cache insertion. Duplicated cache set happens when + // 1. Parallel controls call into RM before first cache set. + // All threads will attempt cache set after the control calls. + // 2. Cache already set by RPC to GSP path + // 3. Cache in verify only mode + // + if (entry->params != NULL) + { + if (RmapiControlCache.mode == NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY) + { + NV_ASSERT(portMemCmp(entry->params, params, paramsSize) == 0); + } + status = NV_OK; + goto done; + } + entry->params = portMemAllocNonPaged(paramsSize); - if (!entry->params) + if (entry->params == NULL) { status = NV_ERR_NO_MEMORY; goto done; } portMemCopy(entry->params, paramsSize, params, paramsSize); + NV_PRINTF(LEVEL_INFO, + "control cache set for 0x%x 0x%x 0x%x succeed, entry: %p\n", + hClient, hObject, cmd, entry); done: if (status != NV_OK) { /* To avoid leaking memory, remove the newly inserted empty submap and entry */ - if (entry) + if (entry != NULL) { portMemFree(entry->params); - multimapRemoveItem(&RmapiControlCache.cachedCallParams, entry); + multimapRemoveItem(&RmapiControlCache.gpusControlCache, entry); } - if (insertedSubmap) - multimapRemoveSubmap(&RmapiControlCache.cachedCallParams, insertedSubmap); + if (insertedSubmap != NULL) + multimapRemoveSubmap(&RmapiControlCache.gpusControlCache, insertedSubmap); } - portSyncMutexRelease(RmapiControlCache.mtx); + portSyncRwLockReleaseWrite(RmapiControlCache.pLock); return status; } -static void freeSubmap(CachedCallParamsSubmap* submap) +// Need to hold rmapi control cache write lock +static void _freeSubmap(GpusControlCacheSubmap* submap) { /* (Sub)map modification invalidates the iterator, so we have to restart */ while (NV_TRUE) { - CachedCallParamsIter it = multimapSubmapIterItems(&RmapiControlCache.cachedCallParams, submap); + GpusControlCacheIter it = multimapSubmapIterItems(&RmapiControlCache.gpusControlCache, submap); if (multimapItemIterNext(&it)) { RmapiControlCacheEntry* entry = it.pValue; portMemFree(entry->params); - multimapRemoveItem(&RmapiControlCache.cachedCallParams, entry); + multimapRemoveItem(&RmapiControlCache.gpusControlCache, entry); } else { break; } } - multimapRemoveSubmap(&RmapiControlCache.cachedCallParams, submap); + multimapRemoveSubmap(&RmapiControlCache.gpusControlCache, submap); } -void rmapiControlCacheFreeClient(NvHandle hClient) +void rmapiControlCacheFreeAllCacheForGpu +( + NvU32 gpuInst +) { - if (!RmapiControlCache.mode) - return; + GpusControlCacheSubmap* submap; - portSyncMutexAcquire(RmapiControlCache.mtx); - while (NV_TRUE) + portSyncRwLockAcquireWrite(RmapiControlCache.pLock); + submap = multimapFindSubmap(&RmapiControlCache.gpusControlCache, gpuInst); + + if (submap != NULL) + _freeSubmap(submap); + + portSyncRwLockReleaseWrite(RmapiControlCache.pLock); +} + +void rmapiControlCacheFreeClientEntry(NvHandle hClient) +{ + portSyncRwLockAcquireWrite(RmapiControlCache.pLock); + _rmapiControlCacheFreeGpuInstForClient(hClient); + portSyncRwLockReleaseWrite(RmapiControlCache.pLock); +} + +void rmapiControlCacheFreeObjectEntry(NvHandle hClient, NvHandle hObject) +{ + if (hClient == hObject) { - CachedCallParamsSubmap* start = multimapFindSubmapGEQ(&RmapiControlCache.cachedCallParams, handlesToKey(hClient, 0)); - CachedCallParamsSubmap* end = multimapFindSubmapLEQ(&RmapiControlCache.cachedCallParams, handlesToKey(hClient, NV_U32_MAX)); - - if (!start || !end || - keyToClient(multimapSubmapKey(&RmapiControlCache.cachedCallParams, start)) != hClient || - keyToClient(multimapSubmapKey(&RmapiControlCache.cachedCallParams, end)) != hClient) - { - break; - } - - CachedCallParamsSupermapIter it = multimapSubmapIterRange(&RmapiControlCache.cachedCallParams, start, end); - - if (multimapSubmapIterNext(&it)) - { - CachedCallParamsSubmap* submap = it.pValue; - freeSubmap(submap); - } - else - { - break; - } + rmapiControlCacheFreeClientEntry(hClient); + return; } - portSyncMutexRelease(RmapiControlCache.mtx); + + portSyncRwLockAcquireWrite(RmapiControlCache.pLock); + _rmapiControlCacheFreeGpuInstForObject(hClient, hObject); + portSyncRwLockReleaseWrite(RmapiControlCache.pLock); } -void rmapiControlCacheFreeObject(NvHandle hClient, NvHandle hObject) +void rmapiControlCacheFree(void) { - CachedCallParamsSubmap* submap; + GpusControlCacheIter it; - if (!RmapiControlCache.mode) - return; - - portSyncMutexAcquire(RmapiControlCache.mtx); - - submap = multimapFindSubmap(&RmapiControlCache.cachedCallParams, handlesToKey(hClient, hObject)); - if (submap) - freeSubmap(submap); - - portSyncMutexRelease(RmapiControlCache.mtx); -} - -void rmapiControlCacheFree(void) { - CachedCallParamsIter it; - - if (!RmapiControlCache.mode) - return; - - it = multimapItemIterAll(&RmapiControlCache.cachedCallParams); + it = multimapItemIterAll(&RmapiControlCache.gpusControlCache); while (multimapItemIterNext(&it)) { RmapiControlCacheEntry* entry = it.pValue; portMemFree(entry->params); } - multimapDestroy(&RmapiControlCache.cachedCallParams); - portSyncMutexDestroy(RmapiControlCache.mtx); + multimapDestroy(&RmapiControlCache.gpusControlCache); + mapDestroy(&RmapiControlCache.objectToGpuInstMap); + portSyncRwLockDestroy(RmapiControlCache.pLock); } + +// +// Changing cache mode cause race conditions on cacheability check and cache get/set. +// When the race condition happens, we may +// 1. Skip cache access when cache enabled +// 2. Access cache when cache disabled +// In the current design, these do not cause any error to the control data. +// +void rmapiControlCacheSetMode(NvU32 mode) +{ + NV_PRINTF(LEVEL_INFO, "Set rmapi control cache mode to 0x%x\n", mode); + RmapiControlCache.mode = mode; +} + +NvU32 rmapiControlCacheGetMode(void) +{ + return RmapiControlCache.mode; +} \ No newline at end of file diff --git a/src/nvidia/src/kernel/rmapi/rmapi_utils.c b/src/nvidia/src/kernel/rmapi/rmapi_utils.c index 7090b1dfb..750533508 100644 --- a/src/nvidia/src/kernel/rmapi/rmapi_utils.c +++ b/src/nvidia/src/kernel/rmapi/rmapi_utils.c @@ -23,6 +23,7 @@ #include "rmapi/rmapi_utils.h" #include "rmapi/rs_utils.h" #include "resource_desc.h" +#include "nvoc/rtti.h" #include "gpu/gpu.h" #include "gpu_mgr/gpu_mgr.h" @@ -145,3 +146,37 @@ rmapiutilIsExternalClassIdInternalOnly NV_ASSERT_OR_RETURN(pResDesc != NULL, NV_FALSE); return (pResDesc->flags & RS_FLAGS_INTERNAL_ONLY) != 0x0; } + +NV_STATUS +rmapiutilGetControlInfo +( + NvU32 cmd, + NvU32 *pFlags, + NvU32 *pAccessRight +) +{ + RS_RESOURCE_DESC *pResourceDesc = RsResInfoByExternalClassId(DRF_VAL(XXXX, _CTRL_CMD, _CLASS, cmd)); + + if (pResourceDesc != NULL) + { + struct NVOC_CLASS_DEF *pClassDef = (void*)pResourceDesc->pClassInfo; + if (pClassDef != NULL) + { + const struct NVOC_EXPORTED_METHOD_DEF *pMethodDef = + nvocGetExportedMethodDefFromMethodInfo_IMPL(pClassDef->pExportInfo, cmd); + + if (pMethodDef != NULL) + { + if (pFlags != NULL) + *pFlags = pMethodDef->flags; + + if (pAccessRight != NULL) + *pAccessRight = pMethodDef->accessRight; + + return NV_OK; + } + } + } + + return NV_ERR_OBJECT_NOT_FOUND; +} diff --git a/src/nvidia/src/kernel/rmapi/rpc_common.c b/src/nvidia/src/kernel/rmapi/rpc_common.c index 705b77452..399138feb 100644 --- a/src/nvidia/src/kernel/rmapi/rpc_common.c +++ b/src/nvidia/src/kernel/rmapi/rpc_common.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -32,6 +32,8 @@ #include "vgpu/rpc.h" #include "os/os.h" +#include "virtualization/kernel_vgpu_mgr.h" + #include "vgpu/vgpu_version.h" #include "gpu/gsp/kernel_gsp.h" @@ -112,6 +114,22 @@ NV_STATUS rpcWriteCommonHeader(OBJGPU *pGpu, OBJRPC *pRpc, NvU32 func, NvU32 par vgpu_rpc_message_header_v->signature = NV_VGPU_MSG_SIGNATURE_VALID; vgpu_rpc_message_header_v->rpc_result = NV_VGPU_MSG_RESULT_RPC_PENDING; vgpu_rpc_message_header_v->rpc_result_private = NV_VGPU_MSG_RESULT_RPC_PENDING; + if (gpuIsSriovEnabled(pGpu) && IS_GSP_CLIENT(pGpu)) + { + // rpcWriteCommonHeader can be called by NV_RM_RPC_ALLOC_SHARE_DEVICE. + // In that moment we have Device with NV_DEVICE_ALLOCATION_FLAGS_HOST_VGPU_DEVICE flag + // but without HOST_VGPU_DEVICE pointer. Get GFID from pDevice manually + // to avoid HOST_VGPU_DEVICE check in vgpuGetCallingContextHostVgpuDevice. + Device *pDevice = vgpuGetCallingContextDevice(pGpu); + + vgpu_rpc_message_header_v->u.cpuRmGfid = 0; + if (pDevice != NULL) + { + if (pDevice->pKernelHostVgpuDevice != NULL) + vgpu_rpc_message_header_v->u.cpuRmGfid = pDevice->pKernelHostVgpuDevice->gfid; + } + } + else { vgpu_rpc_message_header_v->u.spare = NV_VGPU_MSG_UNION_INIT; } diff --git a/src/nvidia/src/kernel/rmapi/rs_utils.c b/src/nvidia/src/kernel/rmapi/rs_utils.c index da5bb7550..533601adf 100644 --- a/src/nvidia/src/kernel/rmapi/rs_utils.c +++ b/src/nvidia/src/kernel/rmapi/rs_utils.c @@ -255,7 +255,7 @@ serverutilGenResourceHandle RmClient *pClient; // LOCK TEST: we should have the API lock here - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); if (NV_OK != serverutilGetClientUnderLock(hClient, &pClient)) return NV_ERR_INVALID_CLIENT; @@ -356,7 +356,7 @@ serverutilAcquireClient RmClient *pClient; // LOCK TEST: we should have the API lock here - LOCK_ASSERT_AND_RETURN(rmApiLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); if (NV_OK != serverAcquireClient(&g_resServ, hClient, access, &pRsClient)) return NV_ERR_INVALID_CLIENT; diff --git a/src/nvidia/src/kernel/virtualization/common_vgpu_mgr.c b/src/nvidia/src/kernel/virtualization/common_vgpu_mgr.c new file mode 100644 index 000000000..a6abaf64d --- /dev/null +++ b/src/nvidia/src/kernel/virtualization/common_vgpu_mgr.c @@ -0,0 +1,59 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "virtualization/common_vgpu_mgr.h" +#include "ctrl/ctrl2080/ctrl2080gpu.h" + +void +vgpuMgrFillVgpuType(NVA081_CTRL_VGPU_INFO *pVgpuInfo, VGPU_TYPE *pVgpuTypeNode) +{ +} + +NV_STATUS +vgpuMgrReserveSystemChannelIDs +( + OBJGPU *pGpu, + VGPU_TYPE *vgpuTypeInfo, + NvU32 gfid, + NvU32 *pChidOffset, + NvHandle hClient, + NvU32 numChannels, + NvU32 engineFifoListNumEntries, + FIFO_ENGINE_LIST *engineFifoList +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +void +vgpuMgrFreeSystemChannelIDs +( + OBJGPU *pGpu, + NvU32 gfid, + NvU32 *pChidOffset, + NvHandle hClient, + NvU32 engineFifoListNumEntries, + FIFO_ENGINE_LIST *engineFifoList +) +{ +} diff --git a/src/nvidia/src/kernel/virtualization/hypervisor/hyperv/hyperv.c b/src/nvidia/src/kernel/virtualization/hypervisor/hyperv/hyperv.c new file mode 100644 index 000000000..727ec9427 --- /dev/null +++ b/src/nvidia/src/kernel/virtualization/hypervisor/hyperv/hyperv.c @@ -0,0 +1,82 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * @file + * @brief MS Hyper-V hypervisor support + */ + +#include "virtualization/hypervisor/hypervisor.h" +#include "os/os.h" + +static NvBool _dummyHypervIsP2PSupported(NvU32 gpuMask) +{ + return NV_FALSE; +} + +// +// For hypervisors like HyperV we need to identify whether we are running in +// non-root partition. +// If we are running in Child partition, then only we enable NMOS code path. +// +#define FEATURE_IDENTIFICATION_LEAF 0x40000003 +#define IMPLEMENTATION_RECOMMENDATIONS_LEAF 0x40000004 +static NV_STATUS _childPartitionDetection(OBJOS *pOS, NvBool *result) +{ + NvU32 eax = 0, ebx = 0; + NvU32 dummyRegister = 0; // This is placeholder reg to pass as an argument + // to read registers values we don't care + + NV_ASSERT(result != NULL); + *result = NV_FALSE; + // See if we are in parent/child partition + if ((pOS->osNv_cpuid(pOS, FEATURE_IDENTIFICATION_LEAF, 0, &dummyRegister, &ebx, &dummyRegister, &dummyRegister) == 0) || + (pOS->osNv_cpuid(pOS, IMPLEMENTATION_RECOMMENDATIONS_LEAF, 0, &eax, &dummyRegister, &dummyRegister, &dummyRegister) == 0)) + { + NV_PRINTF(LEVEL_WARNING, "CPUID is NOT supported!\n"); + return NV_ERR_NOT_SUPPORTED; + } + + // See if CreatePartitions is set (which is 0th bit in ebx), + // which determines if we are in parent/root partition. + // or + // when nested virtualization is enabled, CreatePartitions is set. + // Hence see if 12th bit of eax is set which indicates if the hypervisor + // is nested within a Hyper-V partition. + if(!(ebx & 0x1) || (eax & 0x1000)) + { + // We are in child partition + *result = NV_TRUE; + } + + return NV_OK; +} + +HYPERVISOR_OPS hypervHypervisorOps = +{ + SFINIT(.hypervisorName, "HyperV"), + SFINIT(.hypervisorSig, "Microsoft Hv"), + SFINIT(.hypervisorPostDetection, _childPartitionDetection), + SFINIT(.hypervisorIsPcieP2PSupported, _dummyHypervIsP2PSupported), +}; + diff --git a/src/nvidia/src/kernel/virtualization/hypervisor/hypervisor.c b/src/nvidia/src/kernel/virtualization/hypervisor/hypervisor.c new file mode 100644 index 000000000..418198564 --- /dev/null +++ b/src/nvidia/src/kernel/virtualization/hypervisor/hypervisor.c @@ -0,0 +1,230 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * @file + * @brief Hypervisor interface for RM + */ + +#include "gpu/gpu.h" +#include "virtualization/hypervisor/hypervisor.h" +#include "os/os.h" +#include "nvRmReg.h" + +static HYPERVISOR_OPS _hypervisorOps[OS_HYPERVISOR_UNKNOWN]; + +static NV_STATUS _hypervisorDetection_HVM(OBJHYPERVISOR *, OBJOS *, NvU32 *); +static NvBool _hypervisorCheckVirtualPcieP2PApproval(OBJHYPERVISOR *, NvU32); + +// Because M$ compiler doesn't support C99 we have to initialize +// the struct array in this C function, ugly. + +static void _hypervisorLoad(void) +{ + _hypervisorOps[OS_HYPERVISOR_XEN] = xenHypervisorOps; + _hypervisorOps[OS_HYPERVISOR_KVM] = kvmHypervisorOps; + _hypervisorOps[OS_HYPERVISOR_HYPERV] = hypervHypervisorOps; + _hypervisorOps[OS_HYPERVISOR_VMWARE] = vmwareHypervisorOps; +} + +void hypervisorDestruct_IMPL(OBJHYPERVISOR *pHypervisor) +{ + pHypervisor->type = OS_HYPERVISOR_UNKNOWN; +} + +NV_STATUS hypervisorConstruct_IMPL(OBJHYPERVISOR *pHypervisor) +{ + _hypervisorLoad(); + + pHypervisor->type = OS_HYPERVISOR_UNKNOWN; + + pHypervisor->bDetected = NV_FALSE; + + return NV_OK; +} + +static NvU32 _leaf; + +NvBool hypervisorPcieP2pDetection_IMPL +( + OBJHYPERVISOR *pHypervisor, + NvU32 gpuMask +) +{ + if (_hypervisorCheckVirtualPcieP2PApproval(pHypervisor, gpuMask)) + return NV_TRUE; + + if (hypervisorIsVgxHyper()) + return NV_FALSE; + + return _hypervisorOps[pHypervisor->type].hypervisorIsPcieP2PSupported(gpuMask); +} + +NV_STATUS hypervisorDetection_IMPL +( + OBJHYPERVISOR *pHypervisor, + OBJOS *pOS +) +{ + NV_STATUS rmStatus = NV_OK; + + if (hypervisorIsVgxHyper()) + goto found_one; + + if ((rmStatus = _hypervisorDetection_HVM(pHypervisor, pOS, &_leaf)) != NV_OK) + return rmStatus; + + if ((rmStatus = _hypervisorOps[pHypervisor->type].hypervisorPostDetection(pOS, &pHypervisor->bIsHVMGuest)) != NV_OK) + return rmStatus; + + if (pHypervisor->type == OS_HYPERVISOR_HYPERV && !pHypervisor->bIsHVMGuest) + { + pHypervisor->bIsHypervHost = NV_TRUE; + } + +found_one: + pHypervisor->bDetected = NV_TRUE; + + if (pHypervisor->bIsHVMGuest) + { + NV_PRINTF(LEVEL_WARNING, + "Found HVM kernel running on hypervisor:%s!\n", + _hypervisorOps[pHypervisor->type].hypervisorName); + } + else if (hypervisorIsVgxHyper()) + { + NV_PRINTF(LEVEL_WARNING, + "Found PV kernel running with vGPU hypervisor!\n"); + } + + return NV_OK; +} + +static NV_STATUS _hypervisorDetection_HVM +( + OBJHYPERVISOR *pHypervisor, + OBJOS *pOS, + NvU32 *pLeaf +) +{ + NvU32 i = 0, base, eax = 0; + NvU32 vmmSignature[3]; + + NV_ASSERT_OR_RETURN(pLeaf, NV_ERR_INVALID_ARGUMENT); + *pLeaf = 0; + + for (base = 0x40000000; base < 0x40001000; base += 0x100) + { + if (pOS->osNv_cpuid(pOS, base, 0, &eax, + &vmmSignature[0], &vmmSignature[1], &vmmSignature[2]) == 0) + { + NV_PRINTF(LEVEL_WARNING, "CPUID is NOT supported!\n"); + + return NV_ERR_NOT_SUPPORTED; + } + + // + // Looking for the highest leaf as the official hypervisor + // For example: Xen will implement Viridian at 0x40000000 but + // push himself to 0x40000100 + // + for (i = 0; i < OS_HYPERVISOR_UNKNOWN; i++) + { + if (!portMemCmp(_hypervisorOps[i].hypervisorSig, + vmmSignature, sizeof(vmmSignature))) + { + if (base > *pLeaf) + { + *pLeaf = base; + pHypervisor->type = i; + } + } + } + } + + return *pLeaf ? NV_OK : NV_ERR_NOT_SUPPORTED; +} + +HYPERVISOR_TYPE hypervisorGetHypervisorType_IMPL(OBJHYPERVISOR *pHypervisor) +{ + if (pHypervisor) + return pHypervisor->type; + return OS_HYPERVISOR_UNKNOWN; +} + +static NvBool _hypervisorCheckVirtualPcieP2PApproval +( + OBJHYPERVISOR *pHypervisor, + NvU32 gpuMask +) +{ + OBJGPU *pGpu; + NvU32 gpuInstance = 0; + NvU8 peerCliqueId = 0xFF; + + // + // We provide a way for any hypervisor (either within and without NVIDIA) + // to indicate peer-to-peer capability among GPUs by specifying a peer + // "clique" ID for each GPU in its PCI configuration space. This value is + // read during GPU initialization for virtual GPUs, and GPUs in the same + // clique are then assumed by the RM to be capable of PCI-E P2P. + // + // By specifying a peer clique ID for a GPU, the hypervisor warrants that + // PCI-E P2P has been tested and works correctly between all GPUs with the + // same clique ID on the bare-metal platform under the virtual machine we + // are currently in. + // + while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) + { + if (!pGpu->pciePeerClique.bValid) + { + return NV_FALSE; + } + + if (peerCliqueId == 0xFF) + { + peerCliqueId = pGpu->pciePeerClique.id; + } + else if (peerCliqueId != pGpu->pciePeerClique.id) + { + return NV_FALSE; + } + } + + // + // All GPUs in gpuMask are in the same peer clique as identified by the + // hypervisor, so allow P2P. + // + return NV_TRUE; +} + +NvBool hypervisorIsType_IMPL(HYPERVISOR_TYPE hyperType) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys); + + if (!pHypervisor) + return NV_FALSE; + + return (pHypervisor->type == hyperType); +} diff --git a/src/common/sdk/nvidia/inc/class/cla297.h b/src/nvidia/src/kernel/virtualization/hypervisor/hypervisor_access.c similarity index 78% rename from src/common/sdk/nvidia/inc/class/cla297.h rename to src/nvidia/src/kernel/virtualization/hypervisor/hypervisor_access.c index 6280e5366..0db1f01dc 100644 --- a/src/common/sdk/nvidia/inc/class/cla297.h +++ b/src/nvidia/src/kernel/virtualization/hypervisor/hypervisor_access.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,14 +21,20 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _cl_kepler_c_h_ -#define _cl_kepler_c_h_ -/* AUTO GENERATED FILE -- DO NOT EDIT */ -/* Command: ../../class/bin/sw_header.pl kepler_c */ +#include "core/core.h" -#include "nvtypes.h" +#include "rmapi/client.h" +#include "rmapi/rs_utils.h" +#include "virtualization/hypervisor/hypervisor.h" -#define KEPLER_C 0xA297 +NvBool +hypervisorCheckForObjectAccess_IMPL +( + NvHandle hClient +) +{ + NvBool bGrantAccess = NV_FALSE; -#endif /* _cl_kepler_c_h_ */ + return bGrantAccess; +} diff --git a/src/nvidia/src/kernel/virtualization/hypervisor/kvm/kvm.c b/src/nvidia/src/kernel/virtualization/hypervisor/kvm/kvm.c new file mode 100644 index 000000000..91ffd4b71 --- /dev/null +++ b/src/nvidia/src/kernel/virtualization/hypervisor/kvm/kvm.c @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * @file + * @brief KVM hypervisor support + */ + +#include "virtualization/hypervisor/hypervisor.h" + +static NvBool _dummyKvmIsP2PSupported(NvU32 gpuMask) +{ + return NV_FALSE; +} + +// +// For hypervisors other than HyperV we support, we do not need special detection +// for identification of Child partition. Just to keep consistency in +// _hypervisor_ops structure, we keep this function which always returns true +// for Child partition. +// +static NV_STATUS _dummyKvmChildPartitionDetection(OBJOS *pOS, NvBool *result) +{ + *result = NV_TRUE; + return NV_OK; +} + +HYPERVISOR_OPS kvmHypervisorOps = +{ + SFINIT(.hypervisorName, "KVM"), + SFINIT(.hypervisorSig, "KVMKVMKVM\0\0\0"), + SFINIT(.hypervisorPostDetection, _dummyKvmChildPartitionDetection), + SFINIT(.hypervisorIsPcieP2PSupported, _dummyKvmIsP2PSupported), +}; + diff --git a/src/nvidia/src/kernel/virtualization/hypervisor/vmware/vmware.c b/src/nvidia/src/kernel/virtualization/hypervisor/vmware/vmware.c new file mode 100644 index 000000000..27a47ff87 --- /dev/null +++ b/src/nvidia/src/kernel/virtualization/hypervisor/vmware/vmware.c @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * @file + * @brief VMWare hypervisor support + */ + +#include "virtualization/hypervisor/hypervisor.h" + +static NvBool _dummyVmwareIsP2PSupported(NvU32 gpuMask) +{ + return NV_FALSE; +} + +// +// For hypervisors other than HyperV we support, we do not need special detection +// for identification of Child partition. Just to keep consistency in +// _hypervisor_ops structure, we keep this function which always returns true +// for Child partition. +// +static NV_STATUS _dummyVmwareChildPartitionDetection(OBJOS *pOS, NvBool *result) +{ + *result = NV_TRUE; + return NV_OK; +} + +HYPERVISOR_OPS vmwareHypervisorOps = +{ + SFINIT(.hypervisorName, "VMWare"), + SFINIT(.hypervisorSig, "VMwareVMware"), + SFINIT(.hypervisorPostDetection, _dummyVmwareChildPartitionDetection), + SFINIT(.hypervisorIsPcieP2PSupported, _dummyVmwareIsP2PSupported), +}; diff --git a/src/nvidia/src/kernel/virtualization/hypervisor/xen/xen.c b/src/nvidia/src/kernel/virtualization/hypervisor/xen/xen.c new file mode 100644 index 000000000..3294a7fdc --- /dev/null +++ b/src/nvidia/src/kernel/virtualization/hypervisor/xen/xen.c @@ -0,0 +1,56 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * @file + * @brief Xen hypervisor support + */ + +#include "os/os.h" +#include "virtualization/hypervisor/hypervisor.h" + +static NvBool _dummyXenIsP2PSupported(NvU32 gpuMask) +{ + return NV_FALSE; +} + +// +// For hypervisors other than HyperV we support, we do not need special detection +// for identification of Child partition. Just to keep consistency in +// _hypervisor_ops structure, we keep this function which always returns true +// for Child partition. +// +static NV_STATUS _dummyXenPostDetection(OBJOS *pOS, NvBool *result) +{ + *result = NV_TRUE; + return NV_OK; +} + +HYPERVISOR_OPS xenHypervisorOps = +{ + SFINIT(.hypervisorName, "Xen"), + SFINIT(.hypervisorSig, "XenVMMXenVMM"), + SFINIT(.hypervisorPostDetection, _dummyXenPostDetection), + SFINIT(.hypervisorIsPcieP2PSupported, _dummyXenIsP2PSupported), +}; + diff --git a/src/nvidia/src/kernel/virtualization/kernel_hostvgpudeviceapi.c b/src/nvidia/src/kernel/virtualization/kernel_hostvgpudeviceapi.c new file mode 100644 index 000000000..bcfb13910 --- /dev/null +++ b/src/nvidia/src/kernel/virtualization/kernel_hostvgpudeviceapi.c @@ -0,0 +1,199 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#include "ctrl/ctrl2080.h" +#include "virtualization/kernel_hostvgpudeviceapi.h" +#include "virtualization/vgpuconfigapi.h" + +NV_STATUS +kernelhostvgpudeviceshrConstruct_IMPL +( + KernelHostVgpuDeviceShr *pKernelHostVgpuDeviceShr +) +{ + return NV_OK; +} + +void +kernelhostvgpudeviceshrDestruct_IMPL +( + KernelHostVgpuDeviceShr *pKernelHostVgpuDeviceShr +) +{ +} + +NV_STATUS +kernelhostvgpudeviceapiConstruct_IMPL +( + KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NvBool +kernelhostvgpudeviceapiCanCopy_IMPL +( + KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi +) +{ + return NV_TRUE; +} + +NV_STATUS +kernelhostvgpudeviceapiCopyConstruct_IMPL +( + KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +void +destroyKernelHostVgpuDeviceShare(OBJGPU *pGpu, KernelHostVgpuDeviceShr* pShare) +{ +} + +void +kernelhostvgpudeviceapiDestruct_IMPL +( + KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi +) +{ +} + +NV_STATUS +kernelhostvgpudeviceapiCtrlCmdSetVgpuDeviceInfo_IMPL +( + KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, + NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS *pParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +kernelhostvgpudeviceapiCtrlCmdSetVgpuGuestLifeCycleState_IMPL +( + KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, + NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE_PARAMS *pParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +kernelhostvgpudeviceapiCtrlCmdVfConfigSpaceAccess_IMPL +( + KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, + NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_VF_CONFIG_SPACE_ACCESS_PARAMS *pParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +kernelhostvgpudeviceapiCtrlCmdBindFecsEvtbuf_IMPL +( + KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, + NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BIND_FECS_EVTBUF_PARAMS *pParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +kernelhostvgpudeviceapiCtrlCmdSetOfflinedPagePatchInfo_IMPL +( + KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, + NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO_PARAMS *pParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +kernelhostvgpudeviceGetGuestFbInfo +( + OBJGPU *pGpu, + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, + VGPU_DEVICE_GUEST_FB_INFO *pFbInfo +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +kernelhostvgpudeviceSetGuestFbInfo +( + OBJGPU *pGpu, + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, + NvU64 offset, + NvU64 length +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +kernelhostvgpudeviceapiCtrlCmdTriggerPrivDoorbell_IMPL +( + KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, + NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL_PARAMS *pParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +kernelhostvgpudeviceapiCtrlCmdEventSetNotification_IMPL +( + KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, + NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION_PARAMS *pSetEventParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +kernelhostvgpudeviceapiCtrlCmdSetSriovState_IMPL +( + KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, + NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_SRIOV_STATE_PARAMS *pSetSriovStateParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +kernelhostvgpudeviceapiCtrlCmdSetGuestId_IMPL +( + KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, + NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS *pParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} diff --git a/src/nvidia/src/kernel/virtualization/kernel_vgpu_mgr.c b/src/nvidia/src/kernel/virtualization/kernel_vgpu_mgr.c new file mode 100644 index 000000000..4d6145610 --- /dev/null +++ b/src/nvidia/src/kernel/virtualization/kernel_vgpu_mgr.c @@ -0,0 +1,320 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "ctrl/ctrla081.h" +#include "class/clc637.h" // for AMPERE_SMC_PARTITION_REF +#include "virtualization/kernel_hostvgpudeviceapi.h" + +// +// ODB functions +// + +NV_STATUS +kvgpumgrConstruct_IMPL(KernelVgpuMgr *pKernelVgpuMgr) +{ + return NV_OK; +} + +void +kvgpumgrDestruct_IMPL(KernelVgpuMgr *pKernelVgpuMgr) +{ +} + +// +// Get max instance for a vgpu profile. +// +NV_STATUS +kvgpumgrGetMaxInstanceOfVgpu(NvU32 vgpuTypeId, NvU32 *maxInstanceVgpu) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +kvgpumgrGetPgpuIndex(KernelVgpuMgr *pKernelVgpuMgr, NvU32 gpuPciId, NvU32* index) +{ + return NV_ERR_OBJECT_NOT_FOUND; +} + +NvBool +kvgpumgrIsHeterogeneousVgpuSupported(void) +{ + return NV_FALSE; +} + +NV_STATUS +kvgpumgrCheckVgpuTypeCreatable(KERNEL_PHYS_GPU_INFO *pPhysGpuInfo, VGPU_TYPE *vgpuTypeInfo) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +kvgpumgrGetCreatableVgpuTypes(OBJGPU *pGpu, KernelVgpuMgr *pKernelVgpuMgr, NvU32 pgpuIndex, NvU32* numVgpuTypes, NvU32* vgpuTypes) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +kvgpumgrGetVgpuTypeInfo(NvU32 vgpuTypeId, VGPU_TYPE **vgpuType) +{ + return NV_ERR_OBJECT_NOT_FOUND; +} + +NV_STATUS +kvgpumgrSendAllVgpuTypesToGsp(OBJGPU *pGpu) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +kvgpumgrPgpuAddVgpuType +( + OBJGPU *pGpu, + NvBool discardVgpuTypes, + NVA081_CTRL_VGPU_INFO *pVgpuInfo +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +kvgpumgrAttachGpu(NvU32 gpuPciId) +{ + return NV_OK; +} + +NV_STATUS +kvgpumgrDetachGpu(NvU32 gpuPciId) +{ + return NV_OK; +} + +/* + * @brief Sets Guest(VM) ID for the requested hostvgpudevice + * + * @param pParams NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS Pointer + * @param pKernelHostVgpuDevice Device for which Vm ID need to be set + * @param pGpu OBJGPU pointer + * + * @return NV_STATUS + */ +NV_STATUS +kvgpumgrRegisterGuestId(NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_GUEST_ID_PARAMS *pParams, + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, OBJGPU *pGpu) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +kvgpumgrGuestRegister(OBJGPU *pGpu, + NvU32 gfid, + NvU32 vgpuType, + NvU32 vmPid, + VM_ID_TYPE vmIdType, + VM_ID guestVmId, + NvHandle hPluginFBAllocationClient, + NvU32 numChannels, + NvU32 numPluginChannels, + NvU32 swizzId, + NvU32 vgpuDeviceInstanceId, + NvBool bDisableDefaultSmcExecPartRestore, + KERNEL_HOST_VGPU_DEVICE **ppKernelHostVgpuDevice) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +kvgpumgrGuestUnregister(OBJGPU *pGpu, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice) +{ + return NV_ERR_NOT_SUPPORTED; +} + +// +// Helper function to check if pGPU is live migration capable. +// +NvBool +kvgpumgrCheckPgpuMigrationSupport(OBJGPU *pGpu) +{ + return NV_FALSE; +} + +NvU32 kvgpumgrGetPgpuDevIdEncoding(OBJGPU *pGpu, NvU8 *pgpuString, + NvU32 strSize) +{ + return NV_U32_MAX; +} + +NvU32 kvgpumgrGetPgpuSubdevIdEncoding(OBJGPU *pGpu, NvU8 *pgpuString, + NvU32 strSize) +{ + return NV_U32_MAX; +} + +NvU32 kvgpumgrGetPgpuFSEncoding(OBJGPU *pGpu, NvU8 *pgpuString, + NvU32 strSize) +{ + return NV_U32_MAX; +} + +// +// A 32-bit variable is used to consolidate various GPU capabilities like +// ECC, SRIOV etc. The function sets the capabilities in the variable and +// converted to an ascii-encoded format. +// +NvU32 kvgpumgrGetPgpuCapEncoding(OBJGPU *pGpu, NvU8 *pgpuString, NvU32 strSize) +{ + return NV_U32_MAX; +} + +/* + * Get the user provide vGPU version range + */ +NV_STATUS +kvgpumgrGetHostVgpuVersion(NvU32 *user_min_supported_version, + NvU32 *user_max_supported_version) +{ + return NV_ERR_NOT_SUPPORTED; +} + +/* + * Set the user provide vGPU version range + */ +NV_STATUS +kvgpumgrSetHostVgpuVersion(NvU32 user_min_supported_version, + NvU32 user_max_supported_version) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +kvgpumgrGetSwizzId(OBJGPU *pGpu, + KERNEL_PHYS_GPU_INFO *pPhysGpuInfo, + NvU32 partitionFlag, + NvU32 *swizzId) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +kvgpumgrGetPartitionFlag(NvU32 vgpuTypeId, NvU32 *partitionFlag) +{ + return NV_ERR_INVALID_ARGUMENT; +} + +/* + * Add or remove VF info to pgpuInfo of its PF + * @param[in] gpuPciId PCI ID of target PF + * @param[in] cmd + * 0/VGPU_CMD_PROCESS_VF_INFO.NV_VGPU_SAVE_VF_INFO = Add VF info to VF list of target PF + * 1/VGPU_CMD_PROCESS_VF_INFO.NV_VGPU_REMOVE_VF_INFO = Remove VF info from VF list of target PF + * @param[in] domain Domain of VF to be stored + * @param[in] bus Bus no. of VF to be stored + * @param[in] slot Slot no. of VF to be stored + * @param[in] function Function of VF to be stored + * @param[in] isMdevAttached Flag to indicate if VF is registered with mdev + * @param[out]vfPciInfo Array of PCI information of VFs + */ +NV_STATUS +kvgpumgrProcessVfInfo(NvU32 gpuPciId, NvU8 cmd, NvU32 domain, NvU32 bus, NvU32 slot, NvU32 function, NvBool isMdevAttached, vgpu_vf_pci_info *vfPciInfo) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +kvgpumgrEnumerateVgpuPerPgpu(OBJGPU *pGpu, NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS *pParams) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +kvgpumgrClearGuestVmInfo(OBJGPU *pGpu, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +kvgpumgrGetVgpuFbUsage(OBJGPU *pGpu, NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS *pParams) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +kvgpumgrSetVgpuEncoderCapacity(OBJGPU *pGpu, NvU8 *vgpuUuid, NvU32 encoderCapacity) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +kvgpumgrStart(const NvU8 *pMdevUuid, void *waitQueue, NvS32 *returnStatus, + NvU8 *vmName, NvU32 qemuPid) +{ + return NV_ERR_OBJECT_NOT_FOUND; +} + +// +// Add vGPU info received on mdev_create sysfs call to REQUEST_VGPU_INFO_NODE +// list. REQUEST_VGPU_INFO_NODE is currently used only for vGPU on KVM. +// +// This funtion first checks whether the vGPU type is supported or not as +// only homegeneous vGPU types are supported currently. Also, this function +// only creates REQUEST_VGPU_INFO_NODE entry, actual vGPU will be created later +// +NV_STATUS +kvgpumgrCreateRequestVgpu(NvU32 gpuPciId, const NvU8 *pMdevUuid, + NvU32 vgpuTypeId, NvU16 *vgpuId, NvU32 gpuPciBdf) +{ + return NV_ERR_NOT_SUPPORTED; +} + +// +// Delete REQUEST_VGPU_INFO_NODE structure from list. +// REQUEST_VGPU_INFO_NODE is currently used only for vGPU on KVM. +// +NV_STATUS +kvgpumgrDeleteRequestVgpu(const NvU8 *pMdevUuid, NvU16 vgpuId) +{ + return NV_ERR_OBJECT_NOT_FOUND; +} + +NV_STATUS +kvgpumgrGetHostVgpuDeviceFromMdevUuid(NvU32 gpuPciId, const NvU8 *pMdevUuid, + KERNEL_HOST_VGPU_DEVICE **ppKernelHostVgpuDevice) +{ + return NV_ERR_OBJECT_NOT_FOUND; +} + +NV_STATUS +kvgpumgrGetHostVgpuDeviceFromVmId(NvU32 gpuPciId, VM_ID guestVmId, + KERNEL_HOST_VGPU_DEVICE **ppKernelHostVgpuDevice, + VM_ID_TYPE vmIdType) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +kvgpumgrGetConfigEventInfoFromDb(NvHandle hClient, + NvHandle hVgpuConfig, + VGPU_CONFIG_EVENT_INFO_NODE **ppVgpuConfigEventInfoNode, + NvU32 pgpuIndex) +{ + return NV_ERR_OBJECT_NOT_FOUND; +} diff --git a/src/nvidia/src/kernel/virtualization/vgpuconfigapi.c b/src/nvidia/src/kernel/virtualization/vgpuconfigapi.c new file mode 100644 index 000000000..4446f3ea1 --- /dev/null +++ b/src/nvidia/src/kernel/virtualization/vgpuconfigapi.c @@ -0,0 +1,233 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "virtualization/vgpuconfigapi.h" + +NV_STATUS +vgpuconfigapiConstruct_IMPL +( + VgpuConfigApi *pVgpuConfigApi, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +void +vgpuconfigapiDestruct_IMPL +( + VgpuConfigApi *pVgpuConfigApi +) +{ +} + +void +CliNotifyVgpuConfigEvent +( + OBJGPU *pGpu, + NvU32 notifyIndex +) +{ +} + +NV_STATUS +vgpuconfigapiCtrlCmdVgpuConfigSetInfo_IMPL +( + VgpuConfigApi *pVgpuConfigApi, + NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS *pParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +vgpuconfigapiCtrlCmdVgpuConfigGetVgpuFbUsage_IMPL +( + VgpuConfigApi *pVgpuConfigApi, + NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS *pParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +vgpuconfigapiCtrlCmdVgpuConfigEnumerateVgpuPerPgpu_IMPL +( + VgpuConfigApi *pVgpuConfigApi, + NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS *pParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +vgpuconfigapiCtrlCmdVgpuConfigGetVgpuTypeInfo_IMPL +( + VgpuConfigApi *pVgpuConfigApi, + NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS *pParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +vgpuconfigapiCtrlCmdVgpuConfigGetSupportedVgpuTypes_IMPL +( + VgpuConfigApi *pVgpuConfigApi, + NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS *pParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +vgpuconfigapiCtrlCmdVgpuConfigGetCreatableVgpuTypes_IMPL +( + VgpuConfigApi *pVgpuConfigApi, + NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS *pParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +vgpuconfigapiCtrlCmdVgpuConfigEventSetNotification_IMPL +( + VgpuConfigApi *pVgpuConfigApi, + NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS *pSetEventParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +vgpuconfigapiCtrlCmdVgpuConfigNotifyStart_IMPL +( + VgpuConfigApi *pVgpuConfigApi, + NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS *pNotifyParams +) +{ + return NV_ERR_OBJECT_NOT_FOUND; +} + +NV_STATUS +vgpuconfigapiCtrlCmdVgpuConfigMdevRegister_IMPL +( + VgpuConfigApi *pVgpuConfigApi +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +vgpuconfigapiCtrlCmdVgpuConfigSetVgpuInstanceEncoderCapacity_IMPL +( + VgpuConfigApi *pVgpuConfigApi, + NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS *pEncoderParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +vgpuconfigapiCtrlCmdVgpuConfigGetMigrationCap_IMPL +( + VgpuConfigApi *pVgpuConfigApi, + NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS *pMigrationCapParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +vgpuconfigapiCtrlCmdVgpuConfigGetPgpuMetadataString_IMPL +( + VgpuConfigApi *pVgpuConfigApi, + NVA081_CTRL_VGPU_CONFIG_GET_PGPU_METADATA_STRING_PARAMS *pGpuMetadataStringParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +vgpuconfigapiCtrlCmdVgpuConfigGetHostFbReservation_IMPL +( + VgpuConfigApi *pVgpuConfigApi, + NVA081_CTRL_VGPU_CONFIG_GET_HOST_FB_RESERVATION_PARAMS *pParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +vgpuconfigapiCtrlCmdVgpuConfigGetDoorbellEmulationSupport_IMPL +( + VgpuConfigApi *pVgpuConfigApi, + NVA081_CTRL_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT_PARAMS *pParams +) +{ + + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +vgpuconfigapiCtrlCmdVgpuConfigGetFreeSwizzId_IMPL +( + VgpuConfigApi *pVgpuConfigApi, + NVA081_CTRL_VGPU_CONFIG_GET_FREE_SWIZZID_PARAMS *pParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +vgpuconfigapiCtrlCmdPgpuGetMultiVgpuSupportInfo_IMPL +( + VgpuConfigApi *pVgpuConfigApi, + NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS *pParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +vgpuconfigapiCtrlCmdGetVgpuDriversCaps_IMPL +( + VgpuConfigApi *pVgpuConfigApi, + NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS *pParams +) +{ + pParams->heterogeneousMultiVgpuSupported = NV_FALSE; + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +vgpuconfigapiCtrlCmdVgpuConfigSetPgpuInfo_IMPL +( + VgpuConfigApi *pVgpuConfigApi, + NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS *pParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} diff --git a/src/nvidia/src/lib/zlib/inflate.c b/src/nvidia/src/lib/zlib/inflate.c index f1f6ba970..f7214c256 100644 --- a/src/nvidia/src/lib/zlib/inflate.c +++ b/src/nvidia/src/lib/zlib/inflate.c @@ -116,7 +116,7 @@ #include #include -#define osMemCopy memcpy +#define portMemCopy(p1, s1, p2, s2) memcpy(p1, p2, ((s1) > (s2)) ? (s2) : (s1)) #define portMemSet memset #define portMemAllocNonPaged malloc #define portMemFree free diff --git a/src/nvidia/src/libraries/fnv_hash/fnv_hash.c b/src/nvidia/src/libraries/fnv_hash/fnv_hash.c new file mode 100644 index 000000000..2eeb9eb98 --- /dev/null +++ b/src/nvidia/src/libraries/fnv_hash/fnv_hash.c @@ -0,0 +1,423 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * @file + * @brief NBSI table initialization, search and hash routines. + */ + +#include "nvacpitypes.h" +#include "platform/nbsi/nbsi_read.h" + +/*** + * + * Fowler/Noll/Vo- hash + * + * The basis of this hash algorithm was taken from an idea sent + * as reviewer comments to the IEEE POSIX P1003.2 committee by: + * + * Phong Vo (https://www.research.att.com/info/kpv/) + * Glenn Fowler (https://www.research.att.com/~gsf/) + * + * In a subsequent ballot round: + * + * Landon Curt Noll (https://www.isthe.com/chongo/) + * + * improved on their algorithm. Some people tried this hash + * and found that it worked rather well. In an EMail message + * to Landon, they named it the ``Fowler/Noll/Vo'' or FNV hash. + * + * FNV hashes are designed to be fast while maintaining a low + * collision rate. The FNV speed allows one to quickly hash lots + * of data while maintaining a reasonable collision rate. See: + * + * https://www.isthe.com/chongo/tech/comp/fnv/index.html + * + * for more details as well as other forms of the FNV hash. + * + *** + ... more stuff here from the fnv.h header that I deleted to keep the + ... size down. + *** + * + * Please do not copyright this code. This code is in the public domain. + * + * LANDON CURT NOLL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO + * EVENT SHALL LANDON CURT NOLL BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF + * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + * + * By: + * chongo /\oo/\ + * https://www.isthe.com/chongo/ + * + * Share and Enjoy! :-) + */ + +// This code from hash_32.c + +/* + * fnv_32_buf - perform a 32 bit Fowler/Noll/Vo hash on a buffer + * + * input: + * buf - start of buffer to hash + * len - length of buffer in octets + * hval - previous hash value or 0 if first call + * prevPartHashLen - previous partial hash dataLen + * + * returns: + * 32 bit hash as a static hash type + * + * NOTE: To use the 32 bit FNV-0 historic hash, use FNV0_32_INIT as the hval + * argument on the first call to either fnv_32_buf() or fnv_32_str(). + * + * NOTE: To use the recommended 32 bit FNV-1 hash, use FNV1_32_INIT as the hval + * argument on the first call to either fnv_32_buf() or fnv_32_str(). + */ +NvU32 fnv32buf(const void *buf, NvU32 len, NvU32 hval, NvU32 prevPartHashLen) +{ + const NvU8 *bp = (const NvU8 *)buf; /* start of buffer */ + const NvU8 *be = bp + len; /* beyond end of buffer */ + NvU8 counter = (NvU8) (prevPartHashLen & 1); + + /* + * FNV-1a hash each octet in the buffer + */ + while (bp < be) { + + /* xor the bottom with the current octet */ + // + // The true FNV1 algorithm doesn't xor the 7th bit based on bit 0 + // of the position counter... + // This was done because we had a collision in NBSI string hashes. + // + hval ^= (((NvU32)(NV_TO_UPPER(*bp))) ^ ((counter++ & 0x1) << 7)); + bp++; + + /* multiply by the 32 bit FNV magic prime mod 2^32 */ + hval += (hval<<1) + (hval<<4) + (hval<<7) + (hval<<8) + (hval<<24); + + } + + /* return our new hash value */ + return hval; +} + +//---------------------------------------------------------------------------- +// NvU16 fnv32bufUnicode(* data, data_len, hval, prevPartHashLen) +// +// This function computes a 16 bit hash using the Fowler/Noll/Vo hash method +// The self described public domain code was copied and modifed to fit into +// our system and in this case changed from byte array to unicode array with +// the upper bytes of the unicode character being ignored. +// +// Input parameters: +// *data - Byte array +// dataLen - length of Byte array +// hval - initial hash value +// prevPartHashLen - previous partial hash dataLen +// +// Returns the 16 bit hash. +// +//---------------------------------------------------------------------------- + +NvU32 fnv32bufUnicode(const void *buf, NvU32 len, NvU32 hval, NvU32 prevPartHashLen) +{ + const NvU16 *bp = (const NvU16 *)buf; /* start of buffer */ + const NvU16 *be = bp + len; /* beyond end of buffer */ + NvU8 counter = (NvU8) (prevPartHashLen & 1); + + /* + * FNV-1a hash each octet in the buffer + */ + while (bp < be) { + + /* xor the bottom with the current octet */ + // + // The true FNV1 algorithm doesn't xor the 7th bit based on bit 0... + // This was done because we had a collision in NBSI string hashes. + // + + hval ^= (((NvU32)(NV_TO_UPPER(*bp))) ^ ((counter++ & 0x1) << 7)); + bp++; + + /* multiply by the 32 bit FNV magic prime mod 2^32 */ + hval += (hval<<1) + (hval<<4) + (hval<<7) + (hval<<8) + (hval<<24); + + } + + /* return our new hash value */ + return hval; +} + +//---------------------------------------------------------------------------- +// NvU16 fnv1Hash16(* data, data_len) +// +// This function computes a 16 bit hash using the Fowler/Noll/Vo hash method +// The self described public domain code was copied and modifed to fit into +// our system. +// +// Input parameters: +// *data - Byte array +// dataLen - length of Byte array +// +// Returns the 16 bit hash. +// +//---------------------------------------------------------------------------- + +NvU16 fnv1Hash16(const NvU8 * data, NvU32 dataLen) +{ + NvU32 hash; + + NV_ASSERT(data); + + hash = fnv32buf(data, dataLen, FNV1_32_INIT, 0); + hash = (hash>>16) ^ (hash & MASK_16); + return (NvU16) hash; +} + +//---------------------------------------------------------------------------- +// NvU16 fnv1Hash16Unicode(* data, data_len) +// +// This function computes a 16 bit hash using the Fowler/Noll/Vo hash method +// The self described public domain code was copied and modifed to fit into +// our system. +// +// Input parameters: +// *data - Unicode array +// dataLen - length of Byte array +// +// Returns the 16 bit hash. +// +//---------------------------------------------------------------------------- + +NvU16 fnv1Hash16Unicode(const NvU16 * data, NvU32 dataLen) +{ + NvU32 hash; + + NV_ASSERT(data); + + hash = fnv32bufUnicode(data, dataLen, FNV1_32_INIT, 0); + hash = (hash>>16) ^ (hash & MASK_16); + return (NvU16) hash; +} + +//---------------------------------------------------------------------------- +// NvU32 fnv1Hash20Array(* data, data_len, * rtnHashArray, numOSes) +// +// This function computes a 20 bit hash for each possible OS to search for +// +// Input parameters: +// *data - Byte array +// dataLen - length of Byte array +// *rtnHashArray - array to return the computed hashes +// numOSes - Count of OSes to compute. 1 means generic. +// +// Output: +// rtnHashArray - filled in. +// +//---------------------------------------------------------------------------- + +void fnv1Hash20Array +( + const NvU8 * data, + NvU32 dataLen, + NvU32 * rtnHashArray, + NvU8 numOSes +) +{ + NvU32 baseHash; + NvU32 hash; + NvU8 i; + NBSI_OBJ *pNbsiObj = getNbsiObject(); + + NV_ASSERT(data); + NV_ASSERT(rtnHashArray); + NV_ASSERT(numOSes <= pNbsiObj->curMaxNbsiOSes); + NV_ASSERT(pNbsiObj->curMaxNbsiOSes <= MAX_NBSI_OS); + + if (dataLen == 0) + { + // If element is empty just copy the predone os hashes + for (i = 0; i < numOSes; i++) + { + rtnHashArray[i] = pNbsiObj->nbsiOSstrHash[i]; + } + } + else + { + // Compute the base element hash. + baseHash = fnv32buf(data, dataLen, FNV1_32_INIT, 0); + rtnHashArray[0] = ((baseHash>>20) ^ baseHash) & MASK_20; + + // Now for each OS string, compute the other hashes + for (i = 1; i < numOSes; i++) + { + // start the hash with the original elements 32 bit hash + hash = fnv32buf(&pNbsiObj->nbsiOSstr[i][0], + pNbsiObj->nbsiOSstrLen[i], + baseHash, + dataLen); + rtnHashArray[i] = ((hash>>20) ^ hash) & MASK_20; + } + } + return; +} + +//---------------------------------------------------------------------------- +// NvU32 fnv1Hash20ArrayUnicode(* data, data_len, * rtnHashArray, numOSes) +// +// This function computes a 20 bit hash for each possible OS to search for +// +// Input parameters: +// *data - Byte array +// dataLen - length of Byte array +// *rtnHashArray - array to return the computed hashes +// numOSes - Count of OSes to compute. 1 means generic. +// +// Output: +// rtnHashArray - filled in. +// +//---------------------------------------------------------------------------- + +void fnv1Hash20ArrayUnicode +( + const NvU16 * data, + NvU32 dataLen, + NvU32 * rtnHashArray, + NvU8 numOSes +) +{ + NvU32 baseHash; + NvU32 hash; + NvU8 i; + NBSI_OBJ *pNbsiObj = getNbsiObject(); + + NV_ASSERT(data); + NV_ASSERT(rtnHashArray); + NV_ASSERT(numOSes <= pNbsiObj->curMaxNbsiOSes); + NV_ASSERT(pNbsiObj->curMaxNbsiOSes <= MAX_NBSI_OS); + + if (dataLen == 0) + { + // If element is empty just copy the predone os hashes + for (i = 0; i < numOSes; i++) + { + rtnHashArray[i] = pNbsiObj->nbsiOSstrHash[i]; + } + } + else + { + // Compute the base element hash. + baseHash = fnv32bufUnicode(data, dataLen, FNV1_32_INIT, 0); + rtnHashArray[0] = ((baseHash>>20) ^ baseHash) & MASK_20; + + // + // Now for each OS string, compute the other hashes + // Note these are stored in ascii not unicode + // + for (i = 1; i < numOSes; i++) + { + // start with the hash with the original elements 32 bit hash + hash = fnv32buf(&pNbsiObj->nbsiOSstr[i][0], + pNbsiObj->nbsiOSstrLen[i], + baseHash, + dataLen); + rtnHashArray[i] = ((hash>>20) ^ hash) & MASK_20; + } + } + return; +} + +#define FNV1_64_INIT ((NvU64) 0xCBF29CE484222325ULL) + // ((u_int64_t)14695981039346656037) +#define FNV1_64_PRIME ((NvU64) 0x100000001B3) + // ((u_int64_t)1099511628211) +/* + * fnv_64_buf - perform a 64 bit Fowler/Noll/Vo hash on a buffer + * + * input: + * buf - start of buffer to hash + * len - length of buffer in octets + * hval - previous hash value or 0 if first call + * + * returns: + * 64 bit hash as a static hash type + * + * NOTE: To use the 64 bit FNV-0 historic hash, use FNV0_64_INIT as the hval + * argument on the first call to either fnv_64_buf() or fnv_64_str(). + * + * NOTE: To use the recommended 64 bit FNV-1 hash, use FNV1_64_INIT as the hval + * argument on the first call to either fnv_64_buf() or fnv_64_str(). + */ +static NvU64 fnv64buf(const NvU8 *buf, NvU32 len, NvU64 hval) +{ + const NvU8 *bp = buf; /* start of buffer */ + const NvU8 *be = bp + len; /* beyond end of buffer */ + + /* + * FNV-1a hash each octet in the buffer + */ + while (bp < be) { + + /* xor the bottom with the current octet */ + hval ^= ((NvU64)*bp++); + + /* multiply by the 64 bit FNV magic prime mod 2^64 */ + hval += (hval << 1) + (hval << 4) + (hval << 5) + + (hval << 7) + (hval << 8) + (hval << 40); + } + + /* return our new hash value */ + return hval; +} + +//---------------------------------------------------------------------------- +// NvU64 fnv1Hash64(* data, data_len) +// +// This function computes a 64 bit hash using the Fowler/Noll/Vo hash method +// The self described public domain code was copied and modifed to fit into +// our system. +// +// Input parameters: +// *data - Byte array +// dataLen - length of Byte array +// +// Returns the 64 bit hash. +// +//---------------------------------------------------------------------------- + +NvU64 fnv1Hash64(const NvU8 * data, NvU32 dataLen) +{ + NvU64 hash; + + NV_ASSERT(data); + + hash = fnv64buf(data, dataLen, FNV1_64_INIT); + return hash; +} + + diff --git a/src/nvidia/src/libraries/mmu/mmu_fmt.c b/src/nvidia/src/libraries/mmu/mmu_fmt.c index d8c9f68de..b619409b8 100644 --- a/src/nvidia/src/libraries/mmu/mmu_fmt.c +++ b/src/nvidia/src/libraries/mmu/mmu_fmt.c @@ -132,3 +132,31 @@ mmuFmtGetNextLevel } return NULL; } + +const char* +mmuFmtConvertLevelIdToSuffix +( + const MMU_FMT_LEVEL *pLevelFmt +) +{ + switch (pLevelFmt->pageLevelIdTag) + { + case MMU_FMT_PT_SURF_ID_PD0: + return "_pd0"; + case MMU_FMT_PT_SURF_ID_PD1: + return "_pd1"; + case MMU_FMT_PT_SURF_ID_PD2: + return "_pd2"; + case MMU_FMT_PT_SURF_ID_PD3: + return "_pd3"; + case MMU_FMT_PT_SURF_ID_PD4: + return "_pd4"; + case MMU_FMT_PT_SURF_ID_PT_4K: + return "_pt_4k"; + case MMU_FMT_PT_SURF_ID_PT_BIG: + return "_pt_big"; + default: + return NULL; + } +} + diff --git a/src/nvidia/src/libraries/mmu/mmu_walk_migrate.c b/src/nvidia/src/libraries/mmu/mmu_walk_migrate.c index 3dce6eb53..4dfe54b2a 100644 --- a/src/nvidia/src/libraries/mmu/mmu_walk_migrate.c +++ b/src/nvidia/src/libraries/mmu/mmu_walk_migrate.c @@ -58,7 +58,7 @@ mmuWalkModifyLevelInstance NV_ASSERT_OR_RETURN(NULL != pLevel, NV_ERR_INVALID_ARGUMENT); // Lookup level instance. - btreeSearch(vaBase, (NODE**)&pLevelInst, &pLevel->pInstances->node); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, btreeSearch(vaBase, (NODE**)&pLevelInst, &pLevel->pInstances->node)); NV_ASSERT_OR_RETURN(NULL != pLevelInst, NV_ERR_INVALID_ARGUMENT); // Temp old memory. @@ -128,7 +128,7 @@ mmuWalkModifyLevelInstance const NvU32 entryIndex = mmuFmtVirtAddrToEntryIndex(pParent->pFmt, vaBase); // Lookup parent instance. - btreeSearch(vaBase, (NODE**)&pParentInst, &pParent->pInstances->node); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, btreeSearch(vaBase, (NODE**)&pParentInst, &pParent->pInstances->node)); NV_ASSERT(NULL != pParentInst); // Collect sub-level memory. @@ -145,7 +145,7 @@ mmuWalkModifyLevelInstance else { MMU_WALK_LEVEL_INST *pOtherInst = NULL; - btreeSearch(vaBase, (NODE**)&pOtherInst, &pSubLevel->pInstances->node); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, btreeSearch(vaBase, (NODE**)&pOtherInst, &pSubLevel->pInstances->node)); if (NULL != pOtherInst) { pSubMemDescs[i] = pOtherInst->pMemDesc; diff --git a/src/nvidia/src/libraries/mmu/mmu_walk_reserve.c b/src/nvidia/src/libraries/mmu/mmu_walk_reserve.c index 8a2ae4e49..3d34d8aa8 100644 --- a/src/nvidia/src/libraries/mmu/mmu_walk_reserve.c +++ b/src/nvidia/src/libraries/mmu/mmu_walk_reserve.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/src/libraries/nvoc/src/runtime.c b/src/nvidia/src/libraries/nvoc/src/runtime.c index d4df6aed7..8e4714494 100644 --- a/src/nvidia/src/libraries/nvoc/src/runtime.c +++ b/src/nvidia/src/libraries/nvoc/src/runtime.c @@ -256,6 +256,41 @@ void __nvoc_destructFromBase(Dynamic *pDynamic) pDerivedObj->__nvoc_rtti->dtor(pDerivedObj); } +const struct NVOC_EXPORTED_METHOD_DEF* nvocGetExportedMethodDefFromMethodInfo_IMPL(const struct NVOC_EXPORT_INFO *pExportInfo, NvU32 methodId) +{ + NvU32 exportLength; + const struct NVOC_EXPORTED_METHOD_DEF *exportArray; + + if (pExportInfo == NULL) + return NULL; + + exportLength = pExportInfo->numEntries; + exportArray = pExportInfo->pExportEntries; + + if (exportArray != NULL && exportLength > 0) + { + // The export array is sorted by methodId, so we can binary search it + NvU32 low = 0; + NvU32 high = exportLength; + while (1) + { + NvU32 mid = (low + high) / 2; + + if (exportArray[mid].methodId == methodId) + return &exportArray[mid]; + + if (high == mid || low == mid) + break; + + if (exportArray[mid].methodId > methodId) + high = mid; + else + low = mid; + } + } + + return NULL; +} const struct NVOC_EXPORTED_METHOD_DEF *objGetExportedMethodDef_IMPL(Dynamic *pObj, NvU32 methodId) { @@ -264,41 +299,11 @@ const struct NVOC_EXPORTED_METHOD_DEF *objGetExportedMethodDef_IMPL(Dynamic *pOb const struct NVOC_RTTI *const *relatives = pCastInfo->relatives; NvU32 i; - for (i = 0; i < numRelatives; i++) { - const struct NVOC_RTTI *relative; - const struct NVOC_EXPORT_INFO* exportData; - NvU32 exportLength; - const struct NVOC_EXPORTED_METHOD_DEF *exportArray; - - relative = relatives[i]; - - exportData = relative->pClassDef->pExportInfo; - exportLength = exportData->numEntries; - exportArray = exportData->pExportEntries; - - if (exportArray != NULL && exportLength > 0) - { - // The export array is sorted by methodId, so we can binary search it - NvU32 low = 0; - NvU32 high = exportLength; - while (1) - { - NvU32 mid = (low + high) / 2; - - if (exportArray[mid].methodId == methodId) - return &exportArray[mid]; - - if (high == mid || low == mid) - break; - - if (exportArray[mid].methodId > methodId) - high = mid; - else - low = mid; - } - } + const void *pDef = nvocGetExportedMethodDefFromMethodInfo_IMPL(relatives[i]->pClassDef->pExportInfo, methodId); + if (pDef != NULL) + return pDef; } return NULL; diff --git a/src/nvidia/src/libraries/nvport/memory/memory_tracking.c b/src/nvidia/src/libraries/nvport/memory/memory_tracking.c index 4af26f0d9..e161a9649 100644 --- a/src/nvidia/src/libraries/nvport/memory/memory_tracking.c +++ b/src/nvidia/src/libraries/nvport/memory/memory_tracking.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -439,7 +439,7 @@ static void *_portMemAllocatorAllocNonPagedWrapper(PORT_MEM_ALLOCATOR *pAlloc, N static void _portMemAllocatorFreeWrapper(PORT_MEM_ALLOCATOR *pAlloc, void *pMem); static void _portMemAllocatorReleaseWrapper(PORT_MEM_ALLOCATOR *pAlloc); -static PORT_MEM_ALLOCATOR *_portMemAllocatorCreateOnExistingBlock(void *pAlloc, NvLength blockSizeBytes, void *pSpinlock); +static PORT_MEM_ALLOCATOR *_portMemAllocatorCreateOnExistingBlock(void *pAlloc, NvLength blockSizeBytes, void *pSpinlock PORT_MEM_CALLERINFO_COMMA_TYPE_PARAM); static void *_portMemAllocatorAllocExistingWrapper(PORT_MEM_ALLOCATOR *pAlloc, NvLength length); static void _portMemAllocatorFreeExistingWrapper(PORT_MEM_ALLOCATOR *pAlloc, void *pMem); @@ -560,7 +560,7 @@ portMemShutdown(NvBool bForceSilent) { portMemPrintTrackingInfo(NULL); } -#endif +#endif PORT_MEM_LOG_DESTROY(); if (PORT_MEM_TRACK_USE_FENCEPOSTS) @@ -586,6 +586,9 @@ portMemAllocPaged PORT_MEM_CALLERINFO_COMMA_TYPE_PARAM ) { +#if defined(__COVERITY__) + return __coverity_alloc__(length); +#endif PORT_MEM_ALLOCATOR *pAlloc = portMemAllocatorGetGlobalPaged(); return _portMemAllocatorAlloc(pAlloc, length PORT_MEM_CALLERINFO_COMMA_PARAM); } @@ -597,6 +600,9 @@ portMemAllocNonPaged PORT_MEM_CALLERINFO_COMMA_TYPE_PARAM ) { +#if defined(__COVERITY__) + return __coverity_alloc__(length); +#endif PORT_MEM_ALLOCATOR *pAlloc = portMemAllocatorGetGlobalNonPaged(); return _portMemAllocatorAlloc(pAlloc, length PORT_MEM_CALLERINFO_COMMA_PARAM); } @@ -640,7 +646,7 @@ portMemAllocatorCreatePaged(PORT_MEM_CALLERINFO_TYPE_PARAM) portMemInitializeAllocatorTracking(pAllocator, &pAllocator->pImpl->tracking PORT_MEM_CALLERINFO_COMMA_PARAM); - PORT_MEM_PRINT_INFO("Acquired paged allocator %p", pAllocator); + PORT_MEM_PRINT_INFO("Acquired paged allocator %p ", pAllocator); PORT_MEM_PRINT_INFO(PORT_MEM_CALLERINFO_PRINT_ARGS(PORT_MEM_CALLERINFO_PARAM)); return pAllocator; @@ -663,7 +669,7 @@ portMemAllocatorCreateNonPaged(PORT_MEM_CALLERINFO_TYPE_PARAM) portMemInitializeAllocatorTracking(pAllocator, &pAllocator->pImpl->tracking PORT_MEM_CALLERINFO_COMMA_PARAM); - PORT_MEM_PRINT_INFO("Acquired nonpaged allocator %p", pAllocator); + PORT_MEM_PRINT_INFO("Acquired nonpaged allocator %p ", pAllocator); PORT_MEM_PRINT_INFO(PORT_MEM_CALLERINFO_PRINT_ARGS(PORT_MEM_CALLERINFO_PARAM)); return pAllocator; } @@ -678,7 +684,7 @@ portMemAllocatorCreateOnExistingBlock ) { return _portMemAllocatorCreateOnExistingBlock(pPreallocatedBlock, blockSizeBytes, - NULL); + NULL PORT_MEM_CALLERINFO_COMMA_PARAM); } PORT_MEM_ALLOCATOR * @@ -691,7 +697,7 @@ portMemExAllocatorCreateLockedOnExistingBlock ) { return _portMemAllocatorCreateOnExistingBlock(pPreallocatedBlock, blockSizeBytes, - pSpinlock); + pSpinlock PORT_MEM_CALLERINFO_COMMA_PARAM); } void @@ -1029,7 +1035,7 @@ portMemExTrackingGetNext pHead = _portMemListGetHeader(pList); - // Advance itertator + // Advance iterator if (pList->pNext == pTracking->pFirstAlloc) *pIterator = NULL; else @@ -1174,6 +1180,7 @@ _portMemAllocatorCreateOnExistingBlock void *pPreallocatedBlock, NvLength blockSizeBytes, void *pSpinlock + PORT_MEM_CALLERINFO_COMMA_TYPE_PARAM ) { PORT_MEM_ALLOCATOR *pAllocator = (PORT_MEM_ALLOCATOR *)pPreallocatedBlock; @@ -1225,7 +1232,7 @@ _portMemAllocatorCreateOnExistingBlock } portMemSet(pBitVector->bits, 0, bitVectorSize); - PORT_MEM_PRINT_INFO("Acquired preallocated block allocator %p (%llu bytes)", pAllocator, (NvU64)blockSizeBytes); + PORT_MEM_PRINT_INFO("Acquired preallocated block allocator %p (%llu bytes) ", pAllocator, (NvU64)blockSizeBytes); PORT_MEM_PRINT_INFO(PORT_MEM_CALLERINFO_PRINT_ARGS(PORT_MEM_CALLERINFO_PARAM)); return pAllocator; } diff --git a/src/nvidia/src/libraries/nvport/sync/inc/sync_unix_kernel_os_def.h b/src/nvidia/src/libraries/nvport/sync/inc/sync_unix_kernel_os_def.h index a28201d84..b12c4ad35 100644 --- a/src/nvidia/src/libraries/nvport/sync/inc/sync_unix_kernel_os_def.h +++ b/src/nvidia/src/libraries/nvport/sync/inc/sync_unix_kernel_os_def.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -51,4 +51,10 @@ struct PORT_SEMAPHORE PORT_MEM_ALLOCATOR *pAllocator; }; +struct PORT_RWLOCK +{ + void *rwlock; + PORT_MEM_ALLOCATOR *pAllocator; +}; + #endif diff --git a/src/nvidia/src/libraries/nvport/sync/sync_rwlock.c b/src/nvidia/src/libraries/nvport/sync/sync_rwlock.c deleted file mode 100644 index f33144526..000000000 --- a/src/nvidia/src/libraries/nvport/sync/sync_rwlock.c +++ /dev/null @@ -1,178 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2014-2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -/** - * @file - * @brief Readers-writer lock implementation using PORT_SEMAPHORE and ATOMIC - * module. - */ -#define PORT_SYNC_IMPL -#include "nvport/nvport.h" - - -#if !PORT_IS_MODULE_SUPPORTED(atomic) -#error "NvPort SYNC RWLock implementation requires ATOMIC module to be present." -#endif - -#include "inc/sync_rwlock_def.h" - -NV_STATUS -portSyncRwLockInitialize -( - PORT_RWLOCK *pLock -) -{ - PORT_MEM_ALLOCATOR *pAllocator = portMemAllocatorGetGlobalNonPaged(); - if (pLock == NULL) - { - return NV_ERR_INVALID_POINTER; - } - - pLock->pSemRead = portSyncSemaphoreCreate(pAllocator, 1); - if (pLock->pSemRead == NULL) - { - return NV_ERR_NO_MEMORY; - } - pLock->pSemWrite = portSyncSemaphoreCreate(pAllocator, 1); - if (pLock->pSemWrite == NULL) - { - portSyncSemaphoreDestroy(pLock->pSemRead); - return NV_ERR_NO_MEMORY; - } - - pLock->numReaders = 0; - pLock->pAllocator = NULL; - - return NV_OK; -} - - -void -portSyncRwLockAcquireRead -( - PORT_RWLOCK *pLock -) -{ - PORT_ASSERT_CHECKED(pLock != NULL); - portSyncSemaphoreAcquire(pLock->pSemRead); - if (portAtomicIncrementS32(&pLock->numReaders) == 1) - { - portSyncSemaphoreAcquire(pLock->pSemWrite); - } - portSyncSemaphoreRelease(pLock->pSemRead); -} - -NvBool -portSyncRwLockAcquireReadConditional -( - PORT_RWLOCK *pLock -) -{ - NvBool bAcquired; - PORT_ASSERT_CHECKED(pLock != NULL); - bAcquired = portSyncSemaphoreAcquireConditional(pLock->pSemRead); - if (!bAcquired) - { - return NV_FALSE; - } - if (portAtomicIncrementS32(&pLock->numReaders) == 1) - { - bAcquired = portSyncSemaphoreAcquireConditional(pLock->pSemWrite); - if (!bAcquired) - { - portAtomicDecrementS32(&pLock->numReaders); - } - } - portSyncSemaphoreRelease(pLock->pSemRead); - return bAcquired; -} - -void -portSyncRwLockAcquireWrite -( - PORT_RWLOCK *pLock -) -{ - PORT_ASSERT_CHECKED(pLock != NULL); - portSyncSemaphoreAcquire(pLock->pSemRead); - portSyncSemaphoreAcquire(pLock->pSemWrite); - portSyncSemaphoreRelease(pLock->pSemRead); -} - -NvBool -portSyncRwLockAcquireWriteConditional -( - PORT_RWLOCK *pLock -) -{ - NvBool bAcquired; - PORT_ASSERT_CHECKED(pLock != NULL); - bAcquired = portSyncSemaphoreAcquireConditional(pLock->pSemRead); - if (bAcquired) - { - bAcquired = portSyncSemaphoreAcquireConditional(pLock->pSemWrite); - portSyncSemaphoreRelease(pLock->pSemRead); - } - return bAcquired; -} - -void -portSyncRwLockReleaseRead -( - PORT_RWLOCK *pLock -) -{ - PORT_ASSERT_CHECKED(pLock != NULL); - if (portAtomicDecrementS32(&pLock->numReaders) == 0) - { - portSyncSemaphoreRelease(pLock->pSemWrite); - } -} - -void -portSyncRwLockReleaseWrite -( - PORT_RWLOCK *pLock -) -{ - PORT_ASSERT_CHECKED(pLock != NULL); - portSyncSemaphoreRelease(pLock->pSemWrite); -} - -void -portSyncRwLockDestroy -( - PORT_RWLOCK *pLock -) -{ - PORT_ASSERT_CHECKED(pLock != NULL); - portSyncSemaphoreDestroy(pLock->pSemRead); - portSyncSemaphoreDestroy(pLock->pSemWrite); - if (pLock->pAllocator != NULL) - { - PORT_FREE(pLock->pAllocator, pLock); - } -} - -// Include implementations common for all platforms -#define PORT_SYNC_COMMON_DEFINE_RWLOCK -#include "sync_common.h" diff --git a/src/nvidia/src/libraries/nvport/sync/sync_unix_kernel_os.c b/src/nvidia/src/libraries/nvport/sync/sync_unix_kernel_os.c index fbe60e805..c7ac0097b 100644 --- a/src/nvidia/src/libraries/nvport/sync/sync_unix_kernel_os.c +++ b/src/nvidia/src/libraries/nvport/sync/sync_unix_kernel_os.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -41,7 +41,6 @@ #include "os-interface.h" #include "inc/sync_unix_kernel_os_def.h" -#include "inc/sync_rwlock_def.h" NV_STATUS portSyncSpinlockInitialize @@ -221,6 +220,101 @@ portSyncSemaphoreRelease } +NV_STATUS +portSyncRwLockInitialize +( + PORT_RWLOCK *pRwLock +) +{ + if (pRwLock == NULL) + { + return NV_ERR_INVALID_POINTER; + } + pRwLock->pAllocator = NULL; + pRwLock->rwlock = os_alloc_rwlock(); + return (pRwLock->rwlock != NULL) ? NV_OK : NV_ERR_NO_MEMORY; +} + +void +portSyncRwLockDestroy +( + PORT_RWLOCK *pRwLock +) +{ + PORT_ASSERT_CHECKED(pRwLock != NULL); + os_free_rwlock(pRwLock->rwlock); + if (pRwLock->pAllocator != NULL) + { + PORT_FREE(pRwLock->pAllocator, pRwLock); + } +} + +void +portSyncRwLockAcquireRead +( + PORT_RWLOCK *pRwLock +) +{ + NV_STATUS status; + PORT_ASSERT_CHECKED(pRwLock != NULL); + PORT_ASSERT_CHECKED(portSyncExSafeToSleep()); + status = os_acquire_rwlock_read(pRwLock->rwlock); + PORT_ASSERT(status == NV_OK); +} + +NvBool +portSyncRwLockAcquireReadConditional +( + PORT_RWLOCK *pRwLock +) +{ + PORT_ASSERT_CHECKED(pRwLock != NULL); + return os_cond_acquire_rwlock_read(pRwLock->rwlock) == NV_OK; +} + +void +portSyncRwLockAcquireWrite +( + PORT_RWLOCK *pRwLock +) +{ + NV_STATUS status; + PORT_ASSERT_CHECKED(pRwLock != NULL); + PORT_ASSERT_CHECKED(portSyncExSafeToSleep()); + status = os_acquire_rwlock_write(pRwLock->rwlock); + PORT_ASSERT(status == NV_OK); +} + +NvBool +portSyncRwLockAcquireWriteConditional +( + PORT_RWLOCK *pRwLock +) +{ + PORT_ASSERT_CHECKED(pRwLock != NULL); + return os_cond_acquire_rwlock_write(pRwLock->rwlock) == NV_OK; +} + +void +portSyncRwLockReleaseRead +( + PORT_RWLOCK *pRwLock +) +{ + PORT_ASSERT_CHECKED(pRwLock != NULL); + os_release_rwlock_read(pRwLock->rwlock); +} + +void +portSyncRwLockReleaseWrite +( + PORT_RWLOCK *pRwLock +) +{ + PORT_ASSERT_CHECKED(pRwLock != NULL); + os_release_rwlock_write(pRwLock->rwlock); +} + NvBool portSyncExSafeToSleep() { return os_semaphore_may_sleep(); @@ -238,5 +332,6 @@ NvU64 portSyncExGetInterruptLevel() #define PORT_SYNC_COMMON_DEFINE_SPINLOCK #define PORT_SYNC_COMMON_DEFINE_MUTEX #define PORT_SYNC_COMMON_DEFINE_SEMAPHORE +#define PORT_SYNC_COMMON_DEFINE_RWLOCK #define PORT_SYNC_COMMON_DEFINE_SYNC_INIT #include "sync_common.h" diff --git a/src/nvidia/src/libraries/resserv/src/rs_client.c b/src/nvidia/src/libraries/resserv/src/rs_client.c index c4950049b..a8a02b035 100644 --- a/src/nvidia/src/libraries/resserv/src/rs_client.c +++ b/src/nvidia/src/libraries/resserv/src/rs_client.c @@ -467,6 +467,27 @@ clientValidate_IMPL return NV_OK; } +RS_PRIV_LEVEL +clientGetCachedPrivilege_IMPL +( + RsClient *pClient +) +{ + // Non-functional, base class stubs + return RS_PRIV_LEVEL_USER; +} + +NvBool +clientIsAdmin_IMPL +( + RsClient *pClient, + RS_PRIV_LEVEL privLevel +) +{ + // Non-functional, base class stubs + return NV_FALSE; +} + NV_STATUS clientAllocResource_IMPL ( diff --git a/src/nvidia/src/libraries/resserv/src/rs_resource.c b/src/nvidia/src/libraries/resserv/src/rs_resource.c index 81f5ed412..87e7e3402 100644 --- a/src/nvidia/src/libraries/resserv/src/rs_resource.c +++ b/src/nvidia/src/libraries/resserv/src/rs_resource.c @@ -312,6 +312,17 @@ resCanCopy_IMPL return NV_FALSE; } +NV_STATUS +resIsDuplicate_IMPL +( + RsResource *pResource, + NvHandle hMemory, + NvBool *pDuplicate +) +{ + return NV_ERR_NOT_SUPPORTED; +} + NvBool resAccessCallback_IMPL ( diff --git a/src/nvidia/src/libraries/resserv/src/rs_server.c b/src/nvidia/src/libraries/resserv/src/rs_server.c index a5f00f017..f2426cb83 100644 --- a/src/nvidia/src/libraries/resserv/src/rs_server.c +++ b/src/nvidia/src/libraries/resserv/src/rs_server.c @@ -198,15 +198,14 @@ NV_STATUS serverFreeResourceRpcUnderLock(RsServer *pServer, RS_RES_FREE_PARAMS * // // Client handle format: // -// fn [ C 1 D/E ] [ *INDEX* ] -// bit 31 20 19 0 +// fn [ C[1..3][0..F]] [ *INDEX* ] +// bit 31 20 19 0 // -#define RS_CLIENT_HANDLE_DECODE_MASK 0xFFFFF +#define RS_CLIENT_HANDLE_DECODE_MASK (RS_CLIENT_HANDLE_MAX - 1) #define CLIENT_DECODEHANDLE(handle) (handle & RS_CLIENT_HANDLE_DECODE_MASK) -#define CLIENT_ENCODEHANDLE(index) (RS_CLIENT_HANDLE_BASE | index) -#define CLIENT_ENCODEHANDLE_INTERNAL(internalBase, index) (internalBase | index) +#define CLIENT_ENCODEHANDLE(handleBase, index) (handleBase | index) NV_STATUS serverConstruct @@ -225,6 +224,7 @@ serverConstruct pServer->bDebugFreeList = NV_FALSE; pServer->bRsAccessEnabled = NV_TRUE; pServer->internalHandleBase = RS_CLIENT_INTERNAL_HANDLE_BASE; + pServer->clientHandleBase = RS_CLIENT_HANDLE_BASE; pServer->activeClientCount = 0; pServer->activeResourceCount= 0; pServer->roTopLockApiMask = 0; @@ -356,6 +356,35 @@ serverDestruct return NV_OK; } +NV_STATUS +serverSetClientHandleBase +( + RsServer *pServer, + NvU32 clientHandleBase +) +{ + NvU32 releaseFlags = 0; + RS_LOCK_INFO lockInfo; + portMemSet(&lockInfo, 0, sizeof(lockInfo)); + + // Grab top level lock before updating the internal state + NV_ASSERT_OK_OR_RETURN(serverTopLock_Prologue(pServer, LOCK_ACCESS_WRITE, &lockInfo, &releaseFlags)); + + // Do not allow fixedClientHandle base to be same as internalHandleBase + if (clientHandleBase != pServer->internalHandleBase) + { + pServer->clientHandleBase = clientHandleBase; + } + else + { + NV_PRINTF(LEVEL_ERROR, "Error setting fixed Client handle base\n"); + } + + serverTopLock_Epilogue(pServer, LOCK_ACCESS_WRITE, &lockInfo, &releaseFlags); + + return NV_OK; +} + static NV_STATUS _serverFreeClient_underlock @@ -532,10 +561,7 @@ done: PORT_FREE(pServer->pAllocator, pClientEntry); } - if (pClient != NULL) - { - objDelete(pClient); - } + objDelete(pClient); } return status; @@ -2103,6 +2129,8 @@ _serverCreateEntryAndLockForNewClient NvHandle hClient = *phClient; CLIENT_ENTRY **ppClientNext = 0; PORT_RWLOCK *pLock=NULL; + NvU32 handleBase = bInternalHandle ? pServer->internalHandleBase : + pServer->clientHandleBase; if (hClient == 0) { @@ -2110,10 +2138,7 @@ _serverCreateEntryAndLockForNewClient NvU16 clientHandleBucketInit = clientHandleIndex & RS_CLIENT_HANDLE_BUCKET_MASK; do { - hClient = bInternalHandle - ? CLIENT_ENCODEHANDLE_INTERNAL(pServer->internalHandleBase, clientHandleIndex) - : CLIENT_ENCODEHANDLE(clientHandleIndex); - + hClient = CLIENT_ENCODEHANDLE(handleBase, clientHandleIndex); clientHandleIndex++; if (clientHandleIndex > RS_CLIENT_HANDLE_DECODE_MASK) { @@ -2138,9 +2163,7 @@ _serverCreateEntryAndLockForNewClient #if !(RS_COMPATABILITY_MODE) // Re-encode handle so it matches expected format NvU32 clientIndex = CLIENT_DECODEHANDLE(hClient); - hClient = bInternalHandle - ? CLIENT_ENCODEHANDLE_INTERNAL(clientIndex) - : CLIENT_ENCODEHANDLE(clientIndex); + hClient = CLIENT_ENCODEHANDLE(handleBase, clientIndex); #endif if (_serverFindClientEntry(pServer, hClient, NV_FALSE, NULL) == NV_OK) @@ -2869,10 +2892,7 @@ serverAllocShareWithHalspecParent return NV_OK; fail: - if (pShare != NULL) - { - objDelete(pShare); - } + objDelete(pShare); return status; } diff --git a/src/nvidia/srcs.mk b/src/nvidia/srcs.mk index 807919149..b698a44eb 100644 --- a/src/nvidia/srcs.mk +++ b/src/nvidia/srcs.mk @@ -43,18 +43,21 @@ SRCS += generated/g_gpu_mgmt_api_nvoc.c SRCS += generated/g_gpu_mgr_nvoc.c SRCS += generated/g_gpu_nvoc.c SRCS += generated/g_gpu_resource_nvoc.c +SRCS += generated/g_gpu_user_shared_data_nvoc.c SRCS += generated/g_gpu_vaspace_nvoc.c SRCS += generated/g_gr_pb.c +SRCS += generated/g_gsync_api_nvoc.c +SRCS += generated/g_gsync_nvoc.c SRCS += generated/g_hal_mgr_nvoc.c SRCS += generated/g_hal_nvoc.c SRCS += generated/g_hda_codec_api_nvoc.c SRCS += generated/g_heap_nvoc.c SRCS += generated/g_host_eng_nvoc.c SRCS += generated/g_hw_resources_nvoc.c +SRCS += generated/g_hypervisor_nvoc.c SRCS += generated/g_i2c_api_nvoc.c SRCS += generated/g_intr_nvoc.c SRCS += generated/g_intr_service_nvoc.c -SRCS += generated/g_intrable_nvoc.c SRCS += generated/g_io_vaspace_nvoc.c SRCS += generated/g_journal_nvoc.c SRCS += generated/g_journal_pb.c @@ -83,6 +86,7 @@ SRCS += generated/g_kernel_graphics_nvoc.c SRCS += generated/g_kernel_graphics_object_nvoc.c SRCS += generated/g_kernel_gsp_nvoc.c SRCS += generated/g_kernel_head_nvoc.c +SRCS += generated/g_kernel_hostvgpudeviceapi_nvoc.c SRCS += generated/g_kernel_ioctrl_nvoc.c SRCS += generated/g_kernel_mc_nvoc.c SRCS += generated/g_kernel_mig_manager_nvoc.c @@ -95,8 +99,12 @@ SRCS += generated/g_kernel_rc_nvoc.c SRCS += generated/g_kernel_sched_mgr_nvoc.c SRCS += generated/g_kernel_sec2_nvoc.c SRCS += generated/g_kernel_sm_debugger_session_nvoc.c +SRCS += generated/g_kernel_vgpu_mgr_nvoc.c SRCS += generated/g_mem_fabric_nvoc.c +SRCS += generated/g_mem_list_nvoc.c +SRCS += generated/g_mem_mapper_nvoc.c SRCS += generated/g_mem_mgr_nvoc.c +SRCS += generated/g_mem_multicast_fabric_nvoc.c SRCS += generated/g_mem_nvoc.c SRCS += generated/g_mig_config_session_nvoc.c SRCS += generated/g_mig_monitor_session_nvoc.c @@ -110,7 +118,7 @@ SRCS += generated/g_objgpumon_nvoc.c SRCS += generated/g_objsweng_nvoc.c SRCS += generated/g_objtmr_nvoc.c SRCS += generated/g_os_desc_mem_nvoc.c -SRCS += generated/g_os_iom.c +SRCS += generated/g_os_nvoc.c SRCS += generated/g_p2p_api_nvoc.c SRCS += generated/g_phys_mem_nvoc.c SRCS += generated/g_platform_nvoc.c @@ -147,6 +155,7 @@ SRCS += generated/g_uvm_sw_nvoc.c SRCS += generated/g_vaspace_api_nvoc.c SRCS += generated/g_vaspace_nvoc.c SRCS += generated/g_vblank_callback_nvoc.c +SRCS += generated/g_vgpuconfigapi_nvoc.c SRCS += generated/g_video_mem_nvoc.c SRCS += generated/g_virt_mem_allocator_nvoc.c SRCS += generated/g_virt_mem_mgr_nvoc.c @@ -208,6 +217,20 @@ SRCS += ../common/nvswitch/kernel/lr10/pmgr_lr10.c SRCS += ../common/nvswitch/kernel/lr10/smbpbi_lr10.c SRCS += ../common/nvswitch/kernel/lr10/soe_lr10.c SRCS += ../common/nvswitch/kernel/lr10/therm_lr10.c +SRCS += ../common/nvswitch/kernel/ls10/clock_ls10.c +SRCS += ../common/nvswitch/kernel/ls10/discovery_ls10.c +SRCS += ../common/nvswitch/kernel/ls10/flcn_ls10.c +SRCS += ../common/nvswitch/kernel/ls10/inforom_ls10.c +SRCS += ../common/nvswitch/kernel/ls10/intr_ls10.c +SRCS += ../common/nvswitch/kernel/ls10/link_ls10.c +SRCS += ../common/nvswitch/kernel/ls10/ls10.c +SRCS += ../common/nvswitch/kernel/ls10/minion_ls10.c +SRCS += ../common/nvswitch/kernel/ls10/multicast_ls10.c +SRCS += ../common/nvswitch/kernel/ls10/pmgr_ls10.c +SRCS += ../common/nvswitch/kernel/ls10/smbpbi_ls10.c +SRCS += ../common/nvswitch/kernel/ls10/soe_ls10.c +SRCS += ../common/nvswitch/kernel/ls10/sugen_ls10.c +SRCS += ../common/nvswitch/kernel/ls10/therm_ls10.c SRCS += ../common/nvswitch/kernel/nvswitch.c SRCS += ../common/nvswitch/kernel/pmgr_nvswitch.c SRCS += ../common/nvswitch/kernel/rom_nvswitch.c @@ -220,7 +243,7 @@ SRCS += arch/nvalloc/unix/src/asm/x86/nv_rdcr.c SRCS += arch/nvalloc/unix/src/escape.c SRCS += arch/nvalloc/unix/src/exports-stubs.c SRCS += arch/nvalloc/unix/src/gcc_helper.c -SRCS += arch/nvalloc/unix/src/os-hypervisor-stubs.c +SRCS += arch/nvalloc/unix/src/os-hypervisor.c SRCS += arch/nvalloc/unix/src/os.c SRCS += arch/nvalloc/unix/src/osapi.c SRCS += arch/nvalloc/unix/src/osinit.c @@ -242,6 +265,7 @@ SRCS += interface/deprecated/rmapi_gss_legacy_control.c SRCS += interface/rmapi/src/finn_rm_api.c SRCS += kernel/nvd/nv/dbgbuffer.c SRCS += kernel/nvd/nv/nvdctrl.c +SRCS += kernel/vgpu/nv/objvgpu.c SRCS += kernel/vgpu/nv/rpc.c SRCS += src/kernel/compute/fabric.c SRCS += src/kernel/compute/fm_session_api.c @@ -288,6 +312,7 @@ SRCS += src/kernel/gpu/bus/p2p.c SRCS += src/kernel/gpu/bus/p2p_api.c SRCS += src/kernel/gpu/bus/third_party_p2p.c SRCS += src/kernel/gpu/bus/third_party_p2p_ctrl.c +SRCS += src/kernel/gpu/ccu/arch/hopper/kernel_ccu_gh100.c SRCS += src/kernel/gpu/ccu/kernel_ccu.c SRCS += src/kernel/gpu/ccu/kernel_ccu_api.c SRCS += src/kernel/gpu/ce/arch/ampere/kernel_ce_ga100.c @@ -304,16 +329,19 @@ SRCS += src/kernel/gpu/deferred_api.c SRCS += src/kernel/gpu/device.c SRCS += src/kernel/gpu/device_ctrl.c SRCS += src/kernel/gpu/device_share.c +SRCS += src/kernel/gpu/disp/arch/v02/kern_disp_0207.c SRCS += src/kernel/gpu/disp/arch/v03/kern_disp_0300.c SRCS += src/kernel/gpu/disp/arch/v04/kern_disp_0400.c -SRCS += src/kernel/gpu/disp/arch/v04/kernel_head_gpu.c SRCS += src/kernel/gpu/disp/disp_capabilities.c SRCS += src/kernel/gpu/disp/disp_channel.c +SRCS += src/kernel/gpu/disp/disp_common_ctrl_acpi.c SRCS += src/kernel/gpu/disp/disp_common_kern_ctrl_minimal.c SRCS += src/kernel/gpu/disp/disp_object_kern_ctrl_minimal.c SRCS += src/kernel/gpu/disp/disp_objs.c SRCS += src/kernel/gpu/disp/disp_sf_user.c +SRCS += src/kernel/gpu/disp/head/arch/v04/kernel_head_gpu_0400.c SRCS += src/kernel/gpu/disp/head/kernel_head.c +SRCS += src/kernel/gpu/disp/head/kernel_head_gpu.c SRCS += src/kernel/gpu/disp/inst_mem/arch/v03/disp_inst_mem_0300.c SRCS += src/kernel/gpu/disp/inst_mem/disp_inst_mem.c SRCS += src/kernel/gpu/disp/kern_disp.c @@ -321,6 +349,12 @@ SRCS += src/kernel/gpu/disp/rg_line_callback/rg_line_callback.c SRCS += src/kernel/gpu/disp/vblank_callback/vblank.c SRCS += src/kernel/gpu/disp/vblank_callback/vblank_callback.c SRCS += src/kernel/gpu/eng_state.c +SRCS += src/kernel/gpu/external_device/arch/kepler/kern_external_device_gk104.c +SRCS += src/kernel/gpu/external_device/arch/kepler/kern_gsync_p2060.c +SRCS += src/kernel/gpu/external_device/arch/pascal/kern_gsync_p2061.c +SRCS += src/kernel/gpu/external_device/gsync.c +SRCS += src/kernel/gpu/external_device/gsync_api.c +SRCS += src/kernel/gpu/external_device/kern_external_device.c SRCS += src/kernel/gpu/falcon/arch/ampere/kernel_falcon_ga100.c SRCS += src/kernel/gpu/falcon/arch/ampere/kernel_falcon_ga102.c SRCS += src/kernel/gpu/falcon/arch/turing/kernel_falcon_tu102.c @@ -358,6 +392,8 @@ SRCS += src/kernel/gpu/fsp/kern_fsp.c SRCS += src/kernel/gpu/gpu.c SRCS += src/kernel/gpu/gpu_access.c SRCS += src/kernel/gpu/gpu_device_mapping.c +SRCS += src/kernel/gpu/gpu_engine_type.c +SRCS += src/kernel/gpu/gpu_fabric_probe.c SRCS += src/kernel/gpu/gpu_gspclient.c SRCS += src/kernel/gpu/gpu_name_kernel.c SRCS += src/kernel/gpu/gpu_protobuf.c @@ -366,7 +402,9 @@ SRCS += src/kernel/gpu/gpu_registry.c SRCS += src/kernel/gpu/gpu_resource.c SRCS += src/kernel/gpu/gpu_resource_desc.c SRCS += src/kernel/gpu/gpu_rmapi.c +SRCS += src/kernel/gpu/gpu_suspend.c SRCS += src/kernel/gpu/gpu_timeout.c +SRCS += src/kernel/gpu/gpu_user_shared_data.c SRCS += src/kernel/gpu/gpu_uuid.c SRCS += src/kernel/gpu/gr/arch/maxwell/kgraphics_gm200.c SRCS += src/kernel/gpu/gr/arch/pascal/kgraphics_gp100.c @@ -403,12 +441,12 @@ SRCS += src/kernel/gpu/intr/arch/maxwell/intr_gm107.c SRCS += src/kernel/gpu/intr/arch/pascal/intr_gp100.c SRCS += src/kernel/gpu/intr/arch/turing/intr_cpu_tu102.c SRCS += src/kernel/gpu/intr/arch/turing/intr_nonstall_tu102.c +SRCS += src/kernel/gpu/intr/arch/turing/intr_sriov_tu102.c SRCS += src/kernel/gpu/intr/arch/turing/intr_swintr_tu102.c SRCS += src/kernel/gpu/intr/arch/turing/intr_tu102.c SRCS += src/kernel/gpu/intr/intr.c SRCS += src/kernel/gpu/intr/intr_service.c SRCS += src/kernel/gpu/intr/swintr.c -SRCS += src/kernel/gpu/intrable/intrable.c SRCS += src/kernel/gpu/mc/arch/ampere/kernel_mc_ga100.c SRCS += src/kernel/gpu/mc/arch/maxwell/kernel_mc_gm107.c SRCS += src/kernel/gpu/mc/kernel_mc.c @@ -434,9 +472,11 @@ SRCS += src/kernel/gpu/mem_mgr/fbsr.c SRCS += src/kernel/gpu/mem_mgr/heap.c SRCS += src/kernel/gpu/mem_mgr/mem_ctrl.c SRCS += src/kernel/gpu/mem_mgr/mem_desc.c +SRCS += src/kernel/gpu/mem_mgr/mem_mapper.c SRCS += src/kernel/gpu/mem_mgr/mem_mgr.c SRCS += src/kernel/gpu/mem_mgr/mem_mgr_ctrl.c SRCS += src/kernel/gpu/mem_mgr/mem_mgr_gsp_client.c +SRCS += src/kernel/gpu/mem_mgr/mem_mgr_pwr_mgmt.c SRCS += src/kernel/gpu/mem_mgr/mem_mgr_regions.c SRCS += src/kernel/gpu/mem_mgr/mem_scrub.c SRCS += src/kernel/gpu/mem_mgr/mem_utils.c @@ -501,6 +541,7 @@ SRCS += src/kernel/gpu/nvlink/arch/pascal/kernel_nvlink_gp100.c SRCS += src/kernel/gpu/nvlink/arch/turing/kernel_nvlink_tu102.c SRCS += src/kernel/gpu/nvlink/arch/volta/kernel_minion_gv100.c SRCS += src/kernel/gpu/nvlink/arch/volta/kernel_nvlink_gv100.c +SRCS += src/kernel/gpu/nvlink/common_nvlinkapi.c SRCS += src/kernel/gpu/nvlink/kernel_ioctrl.c SRCS += src/kernel/gpu/nvlink/kernel_nvlink.c SRCS += src/kernel/gpu/nvlink/kernel_nvlinkapi.c @@ -512,12 +553,12 @@ SRCS += src/kernel/gpu/nvlink/kernel_nvlinkstate.c SRCS += src/kernel/gpu/ofa/kernel_ofa_ctx.c SRCS += src/kernel/gpu/perf/kern_cuda_limit.c SRCS += src/kernel/gpu/perf/kern_perf.c -SRCS += src/kernel/gpu/perf/kern_perf_1hz.c SRCS += src/kernel/gpu/perf/kern_perf_boost.c SRCS += src/kernel/gpu/perf/kern_perf_gpuboostsync.c SRCS += src/kernel/gpu/perf/kern_perf_pm.c SRCS += src/kernel/gpu/perf/kern_perf_pwr.c SRCS += src/kernel/gpu/perf/kern_perfbuffer.c +SRCS += src/kernel/gpu/pmu/arch/ada/kern_pmu_ad102.c SRCS += src/kernel/gpu/pmu/kern_pmu.c SRCS += src/kernel/gpu/rc/kernel_rc.c SRCS += src/kernel/gpu/rc/kernel_rc_callback.c @@ -570,6 +611,8 @@ SRCS += src/kernel/mem_mgr/hw_resources.c SRCS += src/kernel/mem_mgr/io_vaspace.c SRCS += src/kernel/mem_mgr/mem.c SRCS += src/kernel/mem_mgr/mem_fabric.c +SRCS += src/kernel/mem_mgr/mem_list.c +SRCS += src/kernel/mem_mgr/mem_multicast_fabric.c SRCS += src/kernel/mem_mgr/no_device_mem.c SRCS += src/kernel/mem_mgr/os_desc_mem.c SRCS += src/kernel/mem_mgr/phys_mem.c @@ -587,12 +630,17 @@ SRCS += src/kernel/os/os_init.c SRCS += src/kernel/os/os_sanity.c SRCS += src/kernel/os/os_stubs.c SRCS += src/kernel/os/os_timer.c +SRCS += src/kernel/platform/acpi_common.c SRCS += src/kernel/platform/chipset/chipset.c SRCS += src/kernel/platform/chipset/chipset_info.c SRCS += src/kernel/platform/chipset/chipset_pcie.c SRCS += src/kernel/platform/chipset/pci_pbi.c SRCS += src/kernel/platform/cpu.c +SRCS += src/kernel/platform/guids.c SRCS += src/kernel/platform/hwbc.c +SRCS += src/kernel/platform/nbsi/nbsi_getv.c +SRCS += src/kernel/platform/nbsi/nbsi_init.c +SRCS += src/kernel/platform/nbsi/nbsi_osrg.c SRCS += src/kernel/platform/p2p/p2p_caps.c SRCS += src/kernel/platform/platform.c SRCS += src/kernel/power/gpu_boost_mgr.c @@ -621,6 +669,16 @@ SRCS += src/kernel/rmapi/rmapi_utils.c SRCS += src/kernel/rmapi/rpc_common.c SRCS += src/kernel/rmapi/rs_utils.c SRCS += src/kernel/rmapi/sharing.c +SRCS += src/kernel/virtualization/common_vgpu_mgr.c +SRCS += src/kernel/virtualization/hypervisor/hyperv/hyperv.c +SRCS += src/kernel/virtualization/hypervisor/hypervisor.c +SRCS += src/kernel/virtualization/hypervisor/hypervisor_access.c +SRCS += src/kernel/virtualization/hypervisor/kvm/kvm.c +SRCS += src/kernel/virtualization/hypervisor/vmware/vmware.c +SRCS += src/kernel/virtualization/hypervisor/xen/xen.c +SRCS += src/kernel/virtualization/kernel_hostvgpudeviceapi.c +SRCS += src/kernel/virtualization/kernel_vgpu_mgr.c +SRCS += src/kernel/virtualization/vgpuconfigapi.c SRCS += src/lib/base_utils.c SRCS += src/lib/protobuf/prbenc.c SRCS += src/lib/protobuf/prbutil.c @@ -633,6 +691,7 @@ SRCS += src/libraries/containers/map.c SRCS += src/libraries/containers/multimap.c SRCS += src/libraries/containers/queue.c SRCS += src/libraries/eventbuffer/eventbufferproducer.c +SRCS += src/libraries/fnv_hash/fnv_hash.c SRCS += src/libraries/ioaccess/ioaccess.c SRCS += src/libraries/mmu/gmmu_fmt.c SRCS += src/libraries/mmu/mmu_fmt.c @@ -654,7 +713,6 @@ SRCS += src/libraries/nvport/crypto/crypto_random_xorshift.c SRCS += src/libraries/nvport/memory/memory_tracking.c SRCS += src/libraries/nvport/memory/memory_unix_kernel_os.c SRCS += src/libraries/nvport/string/string_generic.c -SRCS += src/libraries/nvport/sync/sync_rwlock.c SRCS += src/libraries/nvport/sync/sync_unix_kernel_os.c SRCS += src/libraries/nvport/thread/thread_unix_kernel_os.c SRCS += src/libraries/nvport/util/util_gcc_clang.c @@ -669,6 +727,6 @@ SRCS += src/libraries/resserv/src/rs_resource.c SRCS += src/libraries/resserv/src/rs_server.c SRCS += src/libraries/tls/tls.c SRCS += src/libraries/utils/nvassert.c -SRCS += ../common/uproc/os/libos-v2.0.0/debug/elf.c -SRCS += ../common/uproc/os/libos-v2.0.0/debug/lines.c -SRCS += ../common/uproc/os/libos-v2.0.0/debug/logdecode.c +SRCS += ../common/uproc/os/libos-v3.1.0/lib/libdwarf.c +SRCS += ../common/uproc/os/libos-v3.1.0/lib/libelf.c +SRCS += ../common/uproc/os/libos-v3.1.0/lib/liblogdecode.c diff --git a/utils.mk b/utils.mk index ec2b51f64..17421ba9f 100644 --- a/utils.mk +++ b/utils.mk @@ -44,6 +44,7 @@ CC_ONLY_CFLAGS ?= CXX_ONLY_CFLAGS ?= LDFLAGS ?= BIN_LDFLAGS ?= +EXTRA_CFLAGS ?= STACK_USAGE_WARNING ?= CFLAGS += $(if $(STACK_USAGE_WARNING),-Wstack-usage=$(STACK_USAGE_WARNING)) @@ -84,6 +85,8 @@ ifeq ($(DEVELOP),1) CFLAGS += -DDEVELOP=1 endif +CFLAGS += $(EXTRA_CFLAGS) + STRIP_CMD ?= strip DO_STRIP ?= 1 @@ -209,7 +212,6 @@ ifneq ($(_eval_available),T) $(error This Makefile requires a GNU Make that supports 'eval'. Please upgrade to GNU make 3.80 or later) endif - ############################################################################## # Test passing $(1) to $(CC). If $(CC) succeeds, then echo $(1). # @@ -225,6 +227,19 @@ TEST_CC_ARG = \ $(ECHO) $(1)) +############################################################################## +# Test if instruction $(1) is understood by the assembler +# Returns "1" if the instruction is understood, else returns empty string. +# +# Example usage: +# ENDBR_SUPPORTED := $(call AS_HAS_INSTR, endbr64) +############################################################################## + +AS_HAS_INSTR = \ + $(shell if ($(ECHO) "$(1)" | $(CC) -c -x assembler - -o /dev/null) >/dev/null 2>&1 ;\ + then $(ECHO) "1"; else $(ECHO) ""; fi) + + ############################################################################## # define variables used when installing the open source utilities from # the source tarball @@ -243,7 +258,7 @@ MANDIR = $(DESTDIR)$(PREFIX)/share/man/man1 ############################################################################## default build: all - +.PHONY: default build ############################################################################## # get the definition of NVIDIA_VERSION from version.mk diff --git a/version.mk b/version.mk index a2736a132..4af4f75cb 100644 --- a/version.mk +++ b/version.mk @@ -1,4 +1,4 @@ -NVIDIA_VERSION = 520.56.06 +NVIDIA_VERSION = 525.53 # This file. VERSION_MK_FILE := $(lastword $(MAKEFILE_LIST))